diff --git a/TESTS/integration/COMMON/target_extended.json b/TESTS/integration/COMMON/target_extended.json index e112a626227..c708a827093 100644 --- a/TESTS/integration/COMMON/target_extended.json +++ b/TESTS/integration/COMMON/target_extended.json @@ -172,7 +172,7 @@ "lwip.tcp-enabled" : true, "mbed-trace.enable" : false }, - "MTB_MXCHIP_EMW3166": { + "WIO_EMW3166": { "target.components_add" : ["SPIF"], "spif-driver.SPI_MOSI" : "PB_15", "spif-driver.SPI_MISO" : "PB_14", diff --git a/TESTS/network/emac/main.cpp b/TESTS/network/emac/main.cpp index da8028744da..bbc98d06134 100644 --- a/TESTS/network/emac/main.cpp +++ b/TESTS/network/emac/main.cpp @@ -33,13 +33,9 @@ #else #if (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI) && \ - !defined(TARGET_UBLOX_EVK_ODIN_W2) && \ - !defined(TARGET_REALTEK_RTL8195AM) && \ !defined(TARGET_MTB_ADV_WISE_1530) && \ !defined(TARGET_MTB_USI_WM_BN_BM_22) && \ - !defined(TARGET_MTB_MXCHIP_EMW3166) && \ - !defined(TARGET_MTB_UBLOX_ODIN_W2) && \ - !defined(TARGET_UNO_91H) + !defined(TARGET_WIO_EMW3166) #error [NOT_SUPPORTED] Wifi tests are not valid for the target #else diff --git a/TESTS/network/emac/mbed_lib.json b/TESTS/network/emac/mbed_lib.json index e329450fba8..08b4f457a7b 100644 --- a/TESTS/network/emac/mbed_lib.json +++ b/TESTS/network/emac/mbed_lib.json @@ -5,13 +5,7 @@ "NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": false }, "target_overrides": { - "MTB_UBLOX_ODIN_W2": { - "NO_SUPPORT_FOR_MULTICAST_FILTER": true - }, - "UBLOX_EVK_ODIN_W2": { - "NO_SUPPORT_FOR_MULTICAST_FILTER": true - }, - "MTB_MXCHIP_EMW3166": { + "WIO_EMW3166": { "NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": true }, "MTB_ADV_WISE_1530": { diff --git a/TEST_APPS/device/socket_app/mbed_app.json b/TEST_APPS/device/socket_app/mbed_app.json index 14e0edb152c..1f697c529f2 100644 --- a/TEST_APPS/device/socket_app/mbed_app.json +++ b/TEST_APPS/device/socket_app/mbed_app.json @@ -13,9 +13,6 @@ "platform.stdio-buffered-serial": true, "platform.stdio-flush-at-exit": true, "drivers.uart-serial-rxbuf-size": 768 - }, - "UBLOX_EVK_ODIN_W2" : { - "target.device_has_remove": ["EMAC"] } } } diff --git a/TEST_APPS/readme.md b/TEST_APPS/readme.md index 2d5f50bfac7..01c9c417511 100644 --- a/TEST_APPS/readme.md +++ b/TEST_APPS/readme.md @@ -42,17 +42,15 @@ If you only want to run some specific tests, you can use the `-n` option. You ca #### Running the tests with a specific test-config -Some devices may offer multiple network interfaces to operate with. For example, `UBLOX_EVK_ODIN_W2` offers ethernet and Wi-Fi capabilities. - -The tests can be run for either one of those using already existing test-config -files. +Some devices may offer multiple network interfaces to operate with. The tests can be run for either one of those using already existing test-config -files. To run the tests with the Wi-Fi interface: -`mbed test -m UBLOX_EVK_ODIN_W2 -t --icetea --test-config tools/test_configs/HeapBlockDeviceAndWifiInterface.json` +`mbed test -m -t --icetea --test-config tools/test_configs/HeapBlockDeviceAndWifiInterface.json` To run the tests with the ethernet interface: -`mbed test -m UBLOX_EVK_ODIN_W2 -t --icetea --test-config tools/test_configs/HeapBlockDeviceAndEthernetInterface.json` +`mbed test -m -t --icetea --test-config tools/test_configs/HeapBlockDeviceAndEthernetInterface.json` #### Providing Wi-Fi access point information diff --git a/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py b/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py index 11d034edfd1..7812d20f26e 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py @@ -42,7 +42,7 @@ def __init__(self): '*': { "count":3, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py b/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py index d65100d2282..95ca6cdab80 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py @@ -41,7 +41,7 @@ def __init__(self): '*': { "count":1, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py b/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py index 91a7f8b50d5..fca749ff5ef 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py @@ -41,7 +41,7 @@ def __init__(self): '*': { "count":3, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_data.py b/TEST_APPS/testcases/nanostack_mac_tester/send_data.py index 40db26069dc..0d3bd4514cb 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_data.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_data.py @@ -41,7 +41,7 @@ def __init__(self): '*': { "count":2, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py b/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py index 709321da6d2..8fce10732b1 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py @@ -41,7 +41,7 @@ def __init__(self): '*': { "count":3, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py b/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py index f0fb4b87bf6..7553ca5de83 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py @@ -41,7 +41,7 @@ def __init__(self): '*': { "count":2, "type": "hardware", - "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"], + "allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"], "application": { "name": "TEST_APPS-device-nanostack_mac_tester" } diff --git a/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json index f9cf25a18d8..cead28a9a59 100644 --- a/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json @@ -113,18 +113,6 @@ "SPI_CLK": "D13", "SPI_CS": "D10" }, - "UBLOX_EVK_ODIN_W2": { - "SPI_CS": "D9", - "SPI_MOSI": "D11", - "SPI_MISO": "D12", - "SPI_CLK": "D13" - }, - "MTB_UBLOX_ODIN_W2": { - "SPI_CS": "PG_4", - "SPI_MOSI": "PE_14", - "SPI_MISO": "PE_13", - "SPI_CLK": "PE_12" - }, "RZ_A1H": { "SPI_MOSI": "P8_5", "SPI_MISO": "P8_6", @@ -161,12 +149,6 @@ "SPI_CLK": "p7", "SPI_CS": "p8" }, - "REALTEK_RTL8195AM": { - "SPI_MOSI": "D11", - "SPI_MISO": "D12", - "SPI_CLK": "D13", - "SPI_CS": "D10" - }, "CC3220SF_LAUNCHXL": { "SPI_MOSI": "D11", "SPI_MISO": "D12", diff --git a/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json index 104d8998512..cfb7b79ef4f 100644 --- a/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json @@ -37,19 +37,13 @@ "SPI_CLK": "PTD5", "SPI_CS": "PTD4" }, - "MTB_UBLOX_ODIN_W2": { - "SPI_MOSI": "PE_14", - "SPI_MISO": "PE_13", - "SPI_CLK": "PE_12", - "SPI_CS": "PE_11" - }, "MTB_ADV_WISE_1530": { "SPI_MOSI": "PC_3", "SPI_MISO": "PC_2", "SPI_CLK": "PB_13", "SPI_CS": "PC_12" }, - "MTB_MXCHIP_EMW3166": { + "WIO_EMW3166": { "SPI_MOSI": "PB_15", "SPI_MISO": "PB_14", "SPI_CLK": "PB_13", diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO_ODIN_W2/HCIDriver.cpp b/features/FEATURE_BLE/targets/TARGET_CORDIO_ODIN_W2/HCIDriver.cpp deleted file mode 100644 index 48131619222..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO_ODIN_W2/HCIDriver.cpp +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "CordioBLE.h" -#include "CordioHCIDriver.h" -#include "hci_defs.h" -#include "hci_api.h" -#include "hci_cmd.h" -#include "hci_core.h" -#include "bstream.h" -#include "wsf_buf.h" -#include -#include "hci_mbed_os_adaptation.h" -#include "H4TransportDriver.h" -#include "OdinCordioInterface.h" - -namespace ble { -namespace vendor { -namespace odin_w2 { - -class HCIDriver : public cordio::CordioHCIDriver { -public: - HCIDriver(cordio::CordioHCITransportDriver &transport_driver, PinName shutdown_name, PinName hci_rts_name) : - cordio::CordioHCIDriver(transport_driver), - shutdown(shutdown_name, 0), - hci_rts(hci_rts_name, 0), - service_pack_index(0), - service_pack_transfered(false) { - }; - - virtual cordio::buf_pool_desc_t get_buffer_pool_description(); - - virtual void do_initialize(); - - virtual void do_terminate(); - - virtual void start_reset_sequence(); - - virtual void handle_reset_sequence(uint8_t *pMsg); - -private: - void start_service_pack_transfer(void) - { - service_pack_index = 0; - service_pack_transfered = false; - send_service_pack_command(); - } - - void send_service_pack_command(void) - { - uint16_t cmd_len = odin_service_pack[service_pack_index + HCI_CMD_HDR_LEN]; - cmd_opcode_ack_expected = (odin_service_pack[service_pack_index + 2] << 8) | odin_service_pack[service_pack_index + 1]; - uint8_t *pBuf = hciCmdAlloc(cmd_opcode_ack_expected, cmd_len); - if (pBuf) { - memcpy(pBuf, odin_service_pack + service_pack_index + 1, cmd_len + HCI_CMD_HDR_LEN); - hciCmdSend(pBuf); - } else { - printf("Error cannot allocate memory for the buffer"); - } - } - - void ack_service_pack_command(uint16_t opcode, uint8_t *msg) - { - /* check if response opcode is same as expected command opcode */ - MBED_ASSERT (cmd_opcode_ack_expected == opcode); - - /* update service pack index */ - service_pack_index += (1 + HCI_CMD_HDR_LEN + odin_service_pack[service_pack_index + HCI_CMD_HDR_LEN]); - - if (service_pack_index < service_pack_size) - send_service_pack_command(); - else if (opcode == HCID_VS_WRITE_BD_ADDR) { - /* send an HCI Reset command to start the sequence */ - HciResetCmd(); - service_pack_transfered = true; - } else { - /* send BT device hardware address write command */ - send_hci_vs_cmd(HCID_VS_WRITE_BD_ADDR); - cmd_opcode_ack_expected = HCID_VS_WRITE_BD_ADDR; - } - } - - void hci_read_resolving_list_size(void) - { - /* if LL Privacy is supported by Controller and included */ - if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_PRIVACY) && - (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_PRIVACY)) { - /* send next command in sequence */ - HciLeReadResolvingListSize(); - } else { - hciCoreCb.resListSize = 0; - - /* send next command in sequence */ - hci_read_max_data_len(); - } - } - - void hci_read_max_data_len(void) - { - /* if LE Data Packet Length Extensions is supported by Controller and included */ - if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_DATA_LEN_EXT) && - (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_DATA_LEN_EXT)) { - /* send next command in sequence */ - HciLeReadMaxDataLen(); - } else { - /* send next command in sequence */ - HciLeRandCmd(); - } - } - - DigitalOut shutdown; // power/shutdown pin for bt device - DigitalOut hci_rts; // request to sent pin - size_t service_pack_index; // Index of command to be recently sent over hci - bool service_pack_transfered; // Flag to notify if service pack is completely transferred or not - uint16_t cmd_opcode_ack_expected; // Command against which acknowledgment is expected - uint32_t service_pack_size; // size of service pack - char *odin_service_pack ; // Service pack needs to be provided by driver - vs_cmd_send_t send_hci_vs_cmd ; // callback function to call vendor specific call handler - -}; - -} // namespace odin_w2 -} // namespace vendor -} // namespace ble - - -ble::vendor::cordio::buf_pool_desc_t ble::vendor::odin_w2::HCIDriver::get_buffer_pool_description() -{ - // Use default buffer pool - return ble::vendor::cordio::CordioHCIDriver::get_default_buffer_pool_description(); -} - -void ble::vendor::odin_w2::HCIDriver::do_initialize() -{ - cordio_callback_s callback; - - hci_rts = 1; // Flow Control is OFF - - shutdown = 0; // BT Power is OFF - ThisThread::sleep_for(20); - shutdown = 1; // BT Power is ON - ThisThread::sleep_for(500); - - hci_rts = 0; // Flow Control is ON - - /* ODIN ble driver initialization function */ - cbCordio_Btinit(&callback); - - odin_service_pack = callback.Service_pack; - send_hci_vs_cmd = callback.vs_command_callback; - service_pack_size = callback.service_pack_size; -} - -void ble::vendor::odin_w2::HCIDriver::do_terminate() -{ - -} - -void ble::vendor::odin_w2::HCIDriver::start_reset_sequence() -{ - /* Update baudrate of ble to speed up setup time */ - send_hci_vs_cmd(HCID_VS_UPDATE_UART_BAUD_RATE); - -} - -void ble::vendor::odin_w2::HCIDriver::handle_reset_sequence(uint8_t *pMsg) -{ - uint16_t opcode; - static uint8_t randCnt; - - /* if event is a command complete event */ - if (*pMsg == HCI_CMD_CMPL_EVT) { - /* parse parameters */ - pMsg += HCI_EVT_HDR_LEN; - pMsg++; /* skip num packets */ - BSTREAM_TO_UINT16(opcode, pMsg); - pMsg++; /* skip status */ - - if (opcode == HCID_VS_UPDATE_UART_BAUD_RATE) { - update_uart_baud_rate(); - start_service_pack_transfer(); - return; - } - - if (service_pack_transfered == false) { - ack_service_pack_command(opcode, pMsg); - return; - } - - /* decode opcode */ - switch (opcode) { - - case HCI_OPCODE_RESET: - /* Send (fast and slow) clock configuration command */ - send_hci_vs_cmd(HCID_VS_FAST_CLOCK_CONFIG_BTIP); - break; - - case HCID_VS_FAST_CLOCK_CONFIG_BTIP: - /* Send deep-sleep behavior control command (setting retransmission, inactivity and rts pulse width for Bt) */ - send_hci_vs_cmd(HCID_VS_HCILL_PARS_CFG); - break; - - case HCID_VS_HCILL_PARS_CFG: - /* Send sleep mode configuration command */ - send_hci_vs_cmd(HCID_VS_SLEEP_PROTOCOLS_CFG); - break; - - case HCID_VS_SLEEP_PROTOCOLS_CFG: - /* initialize rand command count */ - randCnt = 0; - - /* send next command in sequence */ - HciSetEventMaskCmd((uint8_t *)hciEventMask); - break; - - case HCI_OPCODE_SET_EVENT_MASK: - /* send next command in sequence */ - HciLeSetEventMaskCmd((uint8_t *)hciLeEventMask); - break; - - case HCI_OPCODE_LE_SET_EVENT_MASK: - /* send next command in sequence */ - HciSetEventMaskPage2Cmd((uint8_t *)hciEventMaskPage2); - break; - - case HCI_OPCODE_SET_EVENT_MASK_PAGE2: - /* send next command in sequence */ - HciReadBdAddrCmd(); - break; - - case HCI_OPCODE_READ_BD_ADDR: - /* parse and store event parameters */ - BdaCpy(hciCoreCb.bdAddr, pMsg); - - /* send next command in sequence */ - HciLeReadBufSizeCmd(); - break; - - case HCI_OPCODE_LE_READ_BUF_SIZE: - /* parse and store event parameters */ - BSTREAM_TO_UINT16(hciCoreCb.bufSize, pMsg); - BSTREAM_TO_UINT8(hciCoreCb.numBufs, pMsg); - - /* initialize ACL buffer accounting */ - hciCoreCb.availBufs = hciCoreCb.numBufs; - - /* send next command in sequence */ - HciLeReadSupStatesCmd(); - break; - - case HCI_OPCODE_LE_READ_SUP_STATES: - /* parse and store event parameters */ - memcpy(hciCoreCb.leStates, pMsg, HCI_LE_STATES_LEN); - - /* send next command in sequence */ - HciLeReadWhiteListSizeCmd(); - break; - - case HCI_OPCODE_LE_READ_WHITE_LIST_SIZE: - /* parse and store event parameters */ - BSTREAM_TO_UINT8(hciCoreCb.whiteListSize, pMsg); - - /* send next command in sequence */ - HciLeReadLocalSupFeatCmd(); - break; - - case HCI_OPCODE_LE_READ_LOCAL_SUP_FEAT: - /* parse and store event parameters */ - BSTREAM_TO_UINT16(hciCoreCb.leSupFeat, pMsg); - - /* send next command in sequence */ - hci_read_resolving_list_size(); - break; - - case HCI_OPCODE_LE_READ_RES_LIST_SIZE: - /* parse and store event parameters */ - BSTREAM_TO_UINT8(hciCoreCb.resListSize, pMsg); - - /* send next command in sequence */ - hci_read_max_data_len(); - break; - - case HCI_OPCODE_LE_READ_MAX_DATA_LEN: - uint16_t maxTxOctets; - uint16_t maxTxTime; - - BSTREAM_TO_UINT16(maxTxOctets, pMsg); - BSTREAM_TO_UINT16(maxTxTime, pMsg); - - /* use Controller's maximum supported payload octets and packet duration times - * for transmission as Host's suggested values for maximum transmission number - * of payload octets and maximum packet transmission time for new connections. - */ - HciLeWriteDefDataLen(maxTxOctets, maxTxTime); - break; - - case HCI_OPCODE_LE_WRITE_DEF_DATA_LEN: - if (hciCoreCb.extResetSeq) { - /* send first extended command */ - (*hciCoreCb.extResetSeq)(pMsg, opcode); - } else { - /* initialize extended parameters */ - hciCoreCb.maxAdvDataLen = 0; - hciCoreCb.numSupAdvSets = 0; - hciCoreCb.perAdvListSize = 0; - - /* send next command in sequence */ - HciLeRandCmd(); - } - break; - - case HCI_OPCODE_LE_READ_MAX_ADV_DATA_LEN: - case HCI_OPCODE_LE_READ_NUM_SUP_ADV_SETS: - case HCI_OPCODE_LE_READ_PER_ADV_LIST_SIZE: - if (hciCoreCb.extResetSeq) { - /* send next extended command in sequence */ - (*hciCoreCb.extResetSeq)(pMsg, opcode); - } - break; - - case HCI_OPCODE_LE_RAND: - /* check if need to send second rand command */ - if (randCnt < (HCI_RESET_RAND_CNT - 1)) { - randCnt++; - HciLeRandCmd(); - } else { - uint8_t addr[6] = { 0 }; - memcpy(addr, pMsg, sizeof(addr)); - DM_RAND_ADDR_SET(addr, DM_RAND_ADDR_STATIC); - // note: will invoke set rand address - set_random_static_address(addr); - } - break; - - case HCI_OPCODE_LE_SET_RAND_ADDR: - /* send next command in sequence */ - signal_reset_sequence_done(); - break; - - default: - break; - } - } -} - -ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() { - static ble::vendor::cordio::H4TransportDriver transport_driver (/* cbCFG_PIO_PIN_BT_HCI_TX */ PG_14, - /* cbCFG_PIO_PIN_BT_HCI_RX */ PC_7, - /* cbCFG_PIO_PIN_BT_HCI_CTS */ PG_15, - /* cbCFG_PIO_PIN_BT_HCI_RTS */ PG_12, - 115200); - static ble::vendor::odin_w2::HCIDriver hci_driver ( transport_driver, - /* cbCFG_PIO_PIN_BT_ENABLE */ PG_7, - /* cbCFG_PIO_PIN_BT_HCI_RTS */ PG_12); - - return hci_driver; -} diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO_ODIN_W2/OdinCordioInterface.h b/features/FEATURE_BLE/targets/TARGET_CORDIO_ODIN_W2/OdinCordioInterface.h deleted file mode 100644 index d84756c8ff6..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO_ODIN_W2/OdinCordioInterface.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017-2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ODIN_CORDIO_INTF_H -#define ODIN_CORDIO_INTF_H - -#include -#include "cb_main.h" - -/*------------------------------------------------------------------------------ -* Vendor specific commands opcode -* ------------------------------------------------------------------------------ -*/ - -/* Command to write hardware address to BT device */ -#define HCID_VS_WRITE_BD_ADDR 0xFC06 - -/* It configures clk parameters for fast and slow clock */ -#define HCID_VS_FAST_CLOCK_CONFIG_BTIP 0xFD1C - -/* Command to configure stand-by behavior */ -#define HCID_VS_HCILL_PARS_CFG 0xFD2B - -/* Command to configures the sleep mode */ -#define HCID_VS_SLEEP_PROTOCOLS_CFG 0xFD0C - -/* Command to Update BT device baudrate */ -#define HCID_VS_UPDATE_UART_BAUD_RATE 0xFF36 - -#define HCI_RESET_RAND_CNT 4 - -#endif /* ODIN_CORDIO_INTF_H */ diff --git a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/LICENSE b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/LICENSE deleted file mode 100644 index 591ac296153..00000000000 --- a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/LICENSE +++ /dev/null @@ -1,49 +0,0 @@ -Permissive Binary License - -Version 1.0, September 2015 - -Redistribution. Redistribution and use in binary form, without -modification, are permitted provided that the following conditions are -met: - -1) Redistributions must reproduce the above copyright notice and the - following disclaimer in the documentation and/or other materials - provided with the distribution. - -2) Unless to the extent explicitly permitted by law, no reverse - engineering, decompilation, or disassembly of this software is - permitted. - -3) Redistribution as part of a software development kit must include the - accompanying file named "DEPENDENCIES" and any dependencies listed in - that file. - -4) Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -Limited patent license. The copyright holders (and contributors) grant a -worldwide, non-exclusive, no-charge, royalty-free patent license to -make, have made, use, offer to sell, sell, import, and otherwise -transfer this software, where such license applies only to those patent -claims licensable by the copyright holders (and contributors) that are -necessarily infringed by this software. This patent license shall not -apply to any combinations that include this software. No hardware is -licensed hereunder. - -If you institute patent litigation against any entity (including a -cross-claim or counterclaim in a lawsuit) alleging that the software -itself infringes your patent(s), then your rights granted under this -license shall terminate as of the date such litigation is filed. - -DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND -CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT -NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/mbed-bootloader-sotp-v3_4_0.bin b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/mbed-bootloader-sotp-v3_4_0.bin deleted file mode 100644 index 50768780121..00000000000 Binary files a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/mbed-bootloader-sotp-v3_4_0.bin and /dev/null differ diff --git a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/mbed_lib.json b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/mbed_lib.json deleted file mode 100644 index 14738868533..00000000000 --- a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/mbed_lib.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "name": "bootloader_UBLOX_EVK_ODIN_W2", - "target_overrides": { - "*": { - "target.app_offset": "0x10400", - "target.header_offset": "0x10000", - "target.bootloader_img": "mbed-bootloader-sotp-v3_4_0.bin" - } - } -} diff --git a/features/lwipstack/mbed_lib.json b/features/lwipstack/mbed_lib.json index 22f32852d00..e41f9efb80e 100644 --- a/features/lwipstack/mbed_lib.json +++ b/features/lwipstack/mbed_lib.json @@ -156,13 +156,6 @@ } }, "target_overrides": { - "REALTEK_RTL8195AM": { - "tcpip-thread-stacksize": 1600, - "mem-size": 12800 - }, - "UBLOX_EVK_ODIN_W2": { - "pbuf-pool-size" : 10 - }, "STM": { "mem-size": 2310 }, diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h index 43a595ccb4a..f38740cb8f2 100644 --- a/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h +++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h @@ -20,8 +20,4 @@ #ifndef MBEDTLS_DEVICE_H #define MBEDTLS_DEVICE_H -#ifdef TARGET_UBLOX_EVK_ODIN_W2 -#define MBEDTLS_MPI_WINDOW_SIZE 3 /**< Maximum windows size used. */ -#endif - #endif /* MBEDTLS_DEVICE_H */ diff --git a/features/storage/kvstore/conf/global/mbed_lib.json b/features/storage/kvstore/conf/global/mbed_lib.json index 58e0b689242..173a7422af8 100644 --- a/features/storage/kvstore/conf/global/mbed_lib.json +++ b/features/storage/kvstore/conf/global/mbed_lib.json @@ -35,9 +35,6 @@ "DISCO_H747I_CM4": { "storage_type": "TDB_INTERNAL" }, - "UBLOX_EVK_ODIN_W2": { - "storage_type": "TDB_INTERNAL" - }, "LPC55S69_S": { "storage_type": "TDB_INTERNAL" }, diff --git a/platform/mbed_lib.json b/platform/mbed_lib.json index 97e13c5c4ca..250ef92f99e 100644 --- a/platform/mbed_lib.json +++ b/platform/mbed_lib.json @@ -209,10 +209,6 @@ "crash-capture-enabled": true, "fatal-error-auto-reboot-enabled": true }, - "UBLOX_EVK_ODIN_W2": { - "crash-capture-enabled": true, - "fatal-error-auto-reboot-enabled": true - }, "UBLOX_C030_U201": { "crash-capture-enabled": true, "fatal-error-auto-reboot-enabled": true diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/PortNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/PortNames.h deleted file mode 100644 index cc9e85e33b7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/PortNames.h +++ /dev/null @@ -1,35 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, -#if defined(TARGET_SAMR21G18A) - PortC, -#endif - PortMax -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis.h deleted file mode 100644 index 919fb83d569..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in samd21j18a specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "samd21.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis_nvic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis_nvic.h deleted file mode 100644 index 3d787468a37..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis_nvic.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 29) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralNames.h deleted file mode 100644 index d83d7081f6d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralNames.h +++ /dev/null @@ -1,150 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include -#include "cmsis.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define _SERCOM_SPI_NAME(n, unused) \ - SPI##n, - -#define _SERCOM_PAD_NAME(n, pad) \ - SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)), - -#define _SERCOM_I2C_NAME(n, unused) \ - I2C##n, - - - -typedef enum { - UART_0 = (int)0x42000800UL, // Base address of SERCOM0 - UART_1 = (int)0x42000C00UL, // Base address of SERCOM1 - UART_2 = (int)0x42001000UL, // Base address of SERCOM2 - UART_3 = (int)0x42001400UL, // Base address of SERCOM3 - UART_4 = (int)0x42001800UL, // Base address of SERCOM4 - UART_5 = (int)0x42001C00UL // Base address of SERCOM5 -} UARTName; - -typedef enum { - ADC_0 = 0x0ul, - ADC_1 = 0x1ul, - ADC_2 = 0x2ul, - ADC_3 = 0x3ul, - ADC_4 = 0x4ul, - ADC_5 = 0x5ul, - ADC_6 = 0x6ul, - ADC_7 = 0x7ul, - ADC_10 = 0xAul, - ADC_11 = 0xBul, - ADC_16 = 0x10ul, - ADC_17 = 0x11ul, - ADC_18 = 0x12ul, - ADC_19 = 0x13ul -} ADCName; - -typedef enum { - DAC_0 = 0x42004800UL -} DACName; - -typedef enum { // for each channel - EXTINT_0 = 0, - EXTINT_1, - EXTINT_2, - EXTINT_3, - EXTINT_4, - EXTINT_5, - EXTINT_6, - EXTINT_7, - EXTINT_8, - EXTINT_9, - EXTINT_10, - EXTINT_11, - EXTINT_12, - EXTINT_13, - EXTINT_14, - EXTINT_15 -} EXTINTName; - -typedef enum { - MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~) -} SPIName; - -typedef enum { - MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~) -} I2CName; - -typedef enum { - /* Pad 0 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0) - - /* Pad 1 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1) - - /* Pad 2 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2) - - /* Pad 3 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3) -} SercomPadName; - -typedef enum { - PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */ - PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */ - PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */ -} PWMName; - -struct pwm_pin_channel { - PinName pin; - PWMName pwm; - uint8_t channel_index; -}; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_3 - -// Default peripherals -#define MBED_SPI0 PA18, PA16, PA19, PA17 - -#define MBED_UART0 PA04, PA05 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 PA08, PA09 - -#define MBED_ANALOGOUT0 PA02 - -#define MBED_ANALOGIN0 PA03 -#define MBED_ANALOGIN1 PA08 -#define MBED_ANALOGIN2 PB09 -#define MBED_ANALOGIN3 PA04 -#define MBED_ANALOGIN4 PA05 -#define MBED_ANALOGIN5 PA06 -#define MBED_ANALOGIN7 PA07 - -#define MBED_PWMOUT0 PA18 -#define MBED_PWMOUT1 PA19 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.c deleted file mode 100644 index 117e7a53693..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.c +++ /dev/null @@ -1,244 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PA02, ADC_0, 1}, - {PA03, ADC_1, 1}, - {PB08, ADC_2, 1}, - {PB09, ADC_3, 1}, - {PA04, ADC_4, 1}, - {PA05, ADC_5, 1}, - {PA06, ADC_6, 1}, - {PA07, ADC_7, 1}, - {PB02, ADC_10, 1}, - {PB03, ADC_11, 1}, - {PA08, ADC_16, 1}, - {PA09, ADC_17, 1}, - {PA10, ADC_18, 1}, - {PA11, ADC_19, 1}, - - /* Not connected */ - {NC , NC , NC} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {PA02, DAC_0, 1}, - - /* Not connected */ - {NC , NC , NC} -}; - -/************SERCOM Pins***********/ -const PinMap PinMap_SERCOM_PAD[] = { - {PA00, SERCOM1_PAD0, 3}, - {PA01, SERCOM1_PAD1, 3}, - {PA04, SERCOM0_PAD0, 3}, - {PA05, SERCOM0_PAD1, 3}, - {PA06, SERCOM0_PAD2, 3}, - {PA07, SERCOM0_PAD3, 3}, - {PA08, SERCOM0_PAD0, 2}, - {PA09, SERCOM0_PAD1, 2}, - {PA10, SERCOM0_PAD2, 2}, - {PA11, SERCOM0_PAD3, 2}, - {PA12, SERCOM2_PAD0, 2}, - {PA13, SERCOM2_PAD1, 2}, - {PA14, SERCOM2_PAD2, 2}, - {PA15, SERCOM2_PAD3, 2}, - {PA16, SERCOM1_PAD0, 2}, - {PA17, SERCOM1_PAD1, 2}, - {PA18, SERCOM1_PAD2, 2}, - {PA19, SERCOM1_PAD3, 2}, - {PA20, SERCOM3_PAD2, 3}, - {PA21, SERCOM3_PAD3, 3}, - {PA22, SERCOM3_PAD0, 2}, - {PA23, SERCOM3_PAD1, 2}, - {PA24, SERCOM3_PAD2, 2}, - {PA25, SERCOM3_PAD3, 2}, - {PA30, SERCOM1_PAD2, 3}, - {PA31, SERCOM1_PAD3, 3}, - {PB02, SERCOM5_PAD0, 3}, - {PB03, SERCOM5_PAD1, 3}, - {PB08, SERCOM4_PAD0, 3}, - {PB09, SERCOM4_PAD1, 3}, - {PB10, SERCOM4_PAD2, 3}, - {PB11, SERCOM4_PAD3, 3}, - {PB22, SERCOM5_PAD2, 3}, - {PB23, SERCOM5_PAD3, 3}, - - /* Not connected */ - {NC , NC , NC} -}; - -/*******SERCOM Pins extended*******/ -const PinMap PinMap_SERCOM_PADEx[] = { - {PA08, SERCOM2_PAD0, 3}, - {PA09, SERCOM2_PAD1, 3}, - {PA10, SERCOM2_PAD2, 3}, - {PA11, SERCOM2_PAD3, 3}, - {PA12, SERCOM4_PAD0, 3}, - {PA13, SERCOM4_PAD1, 3}, - {PA14, SERCOM4_PAD2, 3}, - {PA15, SERCOM4_PAD3, 3}, - {PA16, SERCOM3_PAD0, 3}, - {PA17, SERCOM3_PAD1, 3}, - {PA18, SERCOM3_PAD2, 3}, - {PA19, SERCOM3_PAD3, 3}, - {PA20, SERCOM5_PAD2, 2}, - {PA21, SERCOM5_PAD3, 2}, - {PA22, SERCOM5_PAD0, 3}, - {PA23, SERCOM5_PAD1, 3}, - {PA24, SERCOM5_PAD2, 3}, - {PA25, SERCOM5_PAD3, 3}, - - /* Not connected */ - {NC , NC , NC} -}; - - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PA00, PWM_2, 4}, - {PA01, PWM_2, 4}, - {PA04, PWM_0, 4}, - {PA05, PWM_0, 4}, - {PA06, PWM_1, 4}, - {PA07, PWM_1, 4}, - {PA08, PWM_1, 5}, - {PA09, PWM_1, 5}, - {PA10, PWM_1, 4}, - {PA11, PWM_1, 4}, - {PA12, PWM_2, 4}, - {PA13, PWM_2, 4}, - {PA14, PWM_0, 5}, - {PA15, PWM_0, 5}, - {PA16, PWM_2, 4}, - {PA17, PWM_2, 4}, - {PA18, PWM_0, 5}, - {PA19, PWM_0, 5}, - {PA20, PWM_0, 5}, - {PA21, PWM_0, 5}, - {PA22, PWM_0, 5}, - {PA23, PWM_0, 5}, - {PA24, PWM_1, 5}, - {PA25, PWM_1, 5}, - {PA30, PWM_1, 4}, - {PA31, PWM_1, 4}, - {PB10, PWM_0, 5}, - {PB11, PWM_0, 5}, - - /* Not connected */ - {NC , NC , NC} -}; - -/**********EXTINT*************/ -const PinMap PinMap_EXTINT[] = { - {PA16, EXTINT_0, 0}, - {PA00, EXTINT_0, 0}, - - {PA17, EXTINT_1, 0}, - {PA01, EXTINT_1, 0}, - - {PA18, EXTINT_2, 0}, - {PA02, EXTINT_2, 0}, - {PB02, EXTINT_2, 0}, - - {PA03, EXTINT_3, 0}, - {PA19, EXTINT_3, 0}, - {PB03, EXTINT_3, 0}, - - {PA04, EXTINT_4, 0}, - {PA20, EXTINT_4, 0}, - - {PA05, EXTINT_5, 0}, - {PA21, EXTINT_5, 0}, - - {PA06, EXTINT_6, 0}, - {PA22, EXTINT_6, 0}, - {PB22, EXTINT_6, 0}, - - {PA07, EXTINT_7, 0}, - {PA23, EXTINT_7, 0}, - {PB23, EXTINT_7, 0}, - - {PA28, EXTINT_8, 0}, - {PB08, EXTINT_8, 0}, - - {PA09, EXTINT_9, 0}, - {PB09, EXTINT_9, 0}, - - {PA10, EXTINT_10, 0}, - {PA30, EXTINT_10, 0}, - {PB10, EXTINT_10, 0}, - - {PA11, EXTINT_11, 0}, - {PA31, EXTINT_11, 0}, - {PB11, EXTINT_11, 0}, - - {PA12, EXTINT_12, 0}, - {PA24, EXTINT_12, 0}, - - {PA13, EXTINT_13, 0}, - {PA25, EXTINT_13, 0}, - - {PA14, EXTINT_14, 0}, - - {PA15, EXTINT_15, 0}, - {PA27, EXTINT_15, 0}, - - /* Not connected */ - {NC , NC , NC} -}; - -const struct pwm_pin_channel pwn_pins[] = { - {PA00, PWM_2, 0}, - {PA01, PWM_2, 1}, - {PA04, PWM_0, 0}, - {PA05, PWM_0, 1}, - {PA06, PWM_1, 0}, - {PA07, PWM_1, 1}, - {PA08, PWM_1, 2}, - {PA09, PWM_1, 3}, - {PA10, PWM_1, 0}, - {PA11, PWM_1, 1}, - {PA12, PWM_2, 0}, - {PA13, PWM_2, 1}, - {PA14, PWM_0, 4}, - {PA15, PWM_0, 5}, - {PA16, PWM_2, 0}, - {PA17, PWM_2, 1}, - {PA18, PWM_0, 2}, - {PA19, PWM_0, 3}, - {PA20, PWM_0, 6}, - {PA21, PWM_0, 7}, - {PA22, PWM_0, 4}, - {PA23, PWM_0, 5}, - {PA24, PWM_1, 2}, - {PA25, PWM_1, 3}, - {PA30, PWM_1, 0}, - {PA31, PWM_1, 1}, - {PB10, PWM_0, 4}, - {PB11, PWM_0, 5}, - - /* Not connected */ - {NC , NC , NC} -}; - - - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.h deleted file mode 100644 index 1982babc491..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************DAC***************/ -extern const PinMap PinMap_DAC[]; - -/*********SERCOM*************/ -extern const PinMap PinMap_SERCOM_PAD[]; -extern const PinMap PinMap_SERCOM_PADEx[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -/**********EXTINT*************/ -extern const PinMap PinMap_EXTINT[]; - - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PinNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PinNames.h deleted file mode 100644 index afcfd2cd76c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PinNames.h +++ /dev/null @@ -1,95 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INPUT_OUTPUT //pin state can be set and read back -} PinDirection; - -typedef enum { - PA00 = 0, - PA01 = 1, - PA02 = 2, - PA03 = 3, - PA04 = 4, - PA05 = 5, - PA06 = 6, - PA07 = 7, - PA08 = 8, - PA09 = 9, - PA10 = 10, - PA11 = 11, - PA12 = 12, - PA13 = 13, - PA14 = 14, - PA15 = 15, - PA16 = 16, - PA17 = 17, - PA18 = 18, - PA19 = 19, - PA20 = 20, - PA21 = 21, - PA22 = 22, - PA23 = 23, - PA24 = 24, - PA25 = 25, - PA27 = 27, - PA28 = 28, - PA30 = 30, - PA31 = 31, - - PB02 = 34, - PB03 = 35, - PB08 = 40, - PB09 = 41, - PB10 = 42, - PB11 = 43, - PB22 = 54, - PB23 = 55, - - USBTX = PB10, - USBRX = PB11, - - LED1 = PA23, - LED2 = PA23, - LED3 = PA23, - LED4 = PA23, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/mbed_overrides.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/mbed_overrides.c deleted file mode 100644 index f6b9e401051..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/mbed_overrides.c +++ /dev/null @@ -1,32 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "compiler.h" -#include "system.h" - -uint8_t g_sys_init = 0; - -//called before main - implement here if board needs it ortherwise, let -// the application override this if necessary -//TODO: To be implemented by adding system init and board init -void mbed_sdk_init() -{ - if(g_sys_init == 0) { - g_sys_init = 1; - system_init(); - } -} -/***************************************************************/ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/samw25_xplained_pro.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/samw25_xplained_pro.h deleted file mode 100644 index bb677c618a2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/samw25_xplained_pro.h +++ /dev/null @@ -1,530 +0,0 @@ -/** - * \file - * - * \brief SAM W25 Xplained Pro board definition - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef SAMW25_XPLAINED_PRO_H_INCLUDED -#define SAMW25_XPLAINED_PRO_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup group_common_boards - * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board - * - * @{ - */ - -void system_board_init(void); - -/** - * \defgroup samd21_xplained_pro_features_group Features - * - * Symbols that describe features and capabilities of the board. - * - * @{ - */ - -/** Name string macro */ -#define BOARD_NAME "SAMW25_XPLAINED_PRO" - -/** \name Resonator definitions - * @{ */ -#define BOARD_FREQ_SLCK_XTAL (32768U) -#define BOARD_FREQ_SLCK_BYPASS (32768U) -#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */ -#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */ -#define BOARD_MCK CHIP_FREQ_CPU_MAX -#define BOARD_OSC_STARTUP_US 15625 -/** @} */ - -/** \name LED0 definitions - * @{ */ -#define LED0_PIN PIN_PA23 -#define LED0_ACTIVE false -#define LED0_INACTIVE !LED0_ACTIVE -/** @} */ - -/** \name SW0 definitions - * @{ */ -#define SW0_PIN PIN_PB23 -#define SW0_ACTIVE false -#define SW0_INACTIVE !SW0_ACTIVE -#define SW0_EIC_PIN PIN_PB23A_EIC_EXTINT7 -#define SW0_EIC_MUX MUX_PA23A_EIC_EXTINT7 -#define SW0_EIC_PINMUX PINMUX_PA23A_EIC_EXTINT7 -#define SW0_EIC_LINE 7 -/** @} */ - -/** - * \name LED #0 definitions - * - * Wrapper macros for LED0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define LED_0_NAME "LED0 (yellow)" -#define LED_0_PIN LED0_PIN -#define LED_0_ACTIVE LED0_ACTIVE -#define LED_0_INACTIVE LED0_INACTIVE -#define LED0_GPIO LED0_PIN -#define LED0 LED0_PIN - -#define LED_0_PWM_MODULE TCC0 -#define LED_0_PWM_CHANNEL 0 -#define LED_0_PWM_OUTPUT 0 -#define LED_0_PWM_PIN PIN_PA23F_TCC0_WO5 -#define LED_0_PWM_MUX MUX_PA23F_TCC0_WO5 -#define LED_0_PWM_PINMUX PINMUX_PA23F_TCC0_WO5 -/** @} */ - -/** Number of on-board LEDs */ -#define LED_COUNT 1 - - -/** - * \name Button #0 definitions - * - * Wrapper macros for SW0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define BUTTON_0_NAME "SW0" -#define BUTTON_0_PIN SW0_PIN -#define BUTTON_0_ACTIVE SW0_ACTIVE -#define BUTTON_0_INACTIVE SW0_INACTIVE -#define BUTTON_0_EIC_PIN SW0_EIC_PIN -#define BUTTON_0_EIC_MUX SW0_EIC_MUX -#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX -#define BUTTON_0_EIC_LINE SW0_EIC_LINE -/** @} */ - -/** Number of on-board buttons */ -#define BUTTON_COUNT 1 - -/** \name Extension header #1 pin definitions - * @{ - */ -#define EXT1_PIN_3 PIN_PA02 -#define EXT1_PIN_4 PIN_PA03 -#define EXT1_PIN_5 PIN_PB02 -#define EXT1_PIN_6 PIN_PB03 -#define EXT1_PIN_7 PIN_PA10 -#define EXT1_PIN_8 PIN_PA11 -#define EXT1_PIN_9 PIN_PA20 -#define EXT1_PIN_10 PIN_PA21 -#define EXT1_PIN_11 PIN_PA08 -#define EXT1_PIN_12 PIN_PA09 -#define EXT1_PIN_13 PIN_PB11 -#define EXT1_PIN_14 PIN_PB10 -#define EXT1_PIN_15 PIN_PA17 -#define EXT1_PIN_16 PIN_PA18 -#define EXT1_PIN_17 PIN_PA16 -#define EXT1_PIN_18 PIN_PA19 -/** @} */ - -/** \name Extension header #1 pin definitions by function - * @{ - */ -#define EXT1_PIN_ADC_0 EXT1_PIN_3 -#define EXT1_PIN_ADC_1 EXT1_PIN_4 -#define EXT1_PIN_GPIO_0 EXT1_PIN_5 -#define EXT1_PIN_GPIO_1 EXT1_PIN_6 -#define EXT1_PIN_PWM_0 EXT1_PIN_7 -#define EXT1_PIN_PWM_1 EXT1_PIN_8 -#define EXT1_PIN_IRQ EXT1_PIN_9 -#define EXT1_PIN_I2C_SDA EXT1_PIN_11 -#define EXT1_PIN_I2C_SCL EXT1_PIN_12 -#define EXT1_PIN_UART_RX EXT1_PIN_13 -#define EXT1_PIN_UART_TX EXT1_PIN_14 -#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10 -#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 -#define EXT1_PIN_SPI_MOSI EXT1_PIN_16 -#define EXT1_PIN_SPI_MISO EXT1_PIN_17 -#define EXT1_PIN_SPI_SCK EXT1_PIN_18 -/** @} */ - -/** \name Extension header #1 ADC definitions - * @{ - */ -#define EXT1_ADC_MODULE ADC -#define EXT1_ADC_0_CHANNEL 0 -#define EXT1_ADC_0_PIN PIN_PA02B_ADC_AIN0 -#define EXT1_ADC_0_MUX MUX_PA02B_ADC_AIN0 -#define EXT1_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0 -#define EXT1_ADC_1_CHANNEL 1 -#define EXT1_ADC_1_PIN PIN_PA03B_ADC_AIN1 -#define EXT1_ADC_1_MUX MUX_PA03B_ADC_AIN1 -#define EXT1_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1 -/** @} */ - -/** \name Extension header #1 PWM definitions - * @{ - */ -#define EXT1_PWM_MODULE TCC0 -#define EXT1_PWM_0_CHANNEL 2 -#define EXT1_PWM_0_PIN PIN_PA10F_TCC0_WO2 -#define EXT1_PWM_0_MUX MUX_PA10F_TCC0_WO2 -#define EXT1_PWM_0_PINMUX PINMUX_PA10F_TCC0_WO2 -#define EXT1_PWM_1_CHANNEL 3 -#define EXT1_PWM_1_PIN PIN_PA11F_TCC0_WO3 -#define EXT1_PWM_1_MUX MUX_PA11F_TCC0_WO3 -#define EXT1_PWM_1_PINMUX PINMUX_PA11F_TCC0_WO3 -/** @} */ - -/** \name Extension header #1 IRQ/External interrupt definitions - * @{ - */ -#define EXT1_IRQ_MODULE EIC -#define EXT1_IRQ_INPUT 4 -#define EXT1_IRQ_PIN PIN_PA20A_EIC_EXTINT4 -#define EXT1_IRQ_MUX MUX_PA20A_EIC_EXTINT4 -#define EXT1_IRQ_PINMUX PINMUX_PA20A_EIC_EXTINT4 -/** @} */ - -/** \name Extension header #1 I2C definitions - * @{ - */ -#define EXT1_I2C_MODULE SERCOM0 -#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0 -#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1 -/** @} */ - -/** \name Extension header #1 UART definitions - * @{ - */ -#define EXT1_UART_MODULE SERCOM4 -#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 -#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED -#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2 -#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3 -/** @} */ - -/** \name Extension header #1 SPI definitions - * @{ - */ -#define EXT1_SPI_MODULE SERCOM1 -#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 -#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1 -#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 -#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 - -/** \name Extension header #3 pin definitions - * @{ - */ -#define EXT3_PIN_3 PIN_PA04 -#define EXT3_PIN_4 PIN_PA05 -#define EXT3_PIN_5 PIN_PB22 -#define EXT3_PIN_6 PIN_PB23 -#define EXT3_PIN_7 PIN_PA22 -#define EXT3_PIN_8 PIN_PA23 -#define EXT3_PIN_9 PIN_PA06 -#define EXT3_PIN_10 0 -#define EXT3_PIN_11 PIN_PA08 -#define EXT3_PIN_12 PIN_PA09 -#define EXT3_PIN_13 PIN_PA01 -#define EXT3_PIN_14 PIN_PA00 -#define EXT3_PIN_15 PIN_PA07 -#define EXT3_PIN_16 PIN_PA18 -#define EXT3_PIN_17 PIN_PA16 -#define EXT3_PIN_18 PIN_PA19 -/** @} */ - -/** \name Extension header #3 pin definitions by function - * @{ - */ -#define EXT3_PIN_ADC_0 EXT3_PIN_3 -#define EXT3_PIN_ADC_1 EXT3_PIN_4 -#define EXT3_PIN_GPIO_0 EXT3_PIN_5 -#define EXT3_PIN_GPIO_1 EXT3_PIN_6 -#define EXT3_PIN_PWM_0 EXT3_PIN_7 -#define EXT3_PIN_PWM_1 EXT3_PIN_8 -#define EXT3_PIN_IRQ EXT3_PIN_9 -#define EXT3_PIN_I2C_SDA EXT3_PIN_11 -#define EXT3_PIN_I2C_SCL EXT3_PIN_12 -#define EXT3_PIN_UART_RX EXT3_PIN_13 -#define EXT3_PIN_UART_TX EXT3_PIN_14 -#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15 -#define EXT3_PIN_SPI_MOSI EXT3_PIN_16 -#define EXT3_PIN_SPI_MISO EXT3_PIN_17 -#define EXT3_PIN_SPI_SCK EXT3_PIN_18 -/** @} */ - -/** \name Extension header #3 ADC definitions - * @{ - */ -#define EXT3_ADC_MODULE ADC -#define EXT3_ADC_0_CHANNEL 4 -#define EXT3_ADC_0_PIN PIN_PA04B_ADC_AIN4 -#define EXT3_ADC_0_MUX MUX_PA04B_ADC_AIN4 -#define EXT3_ADC_0_PINMUX PINMUX_PA04B_ADC_AIN4 -#define EXT3_ADC_1_CHANNEL 5 -#define EXT3_ADC_1_PIN PIN_PA05B_ADC_AIN5 -#define EXT3_ADC_1_MUX MUX_PA05B_ADC_AIN5 -#define EXT3_ADC_1_PINMUX PINMUX_PA05B_ADC_AIN5 -/** @} */ - -/** \name Extension header #3 PWM definitions - * @{ - */ -#define EXT3_PWM_MODULE TC4 -#define EXT3_PWM_0_CHANNEL 0 -#define EXT3_PWM_0_PIN PIN_PA22E_TC4_WO0 -#define EXT3_PWM_0_MUX MUX_PA22E_TC4_WO0 -#define EXT3_PWM_0_PINMUX PINMUX_PA22E_TC4_WO0 -#define EXT3_PWM_1_CHANNEL 1 -#define EXT3_PWM_1_PIN PIN_PA23E_TC4_WO1 -#define EXT3_PWM_1_MUX MUX_PA23E_TC4_WO1 -#define EXT3_PWM_1_PINMUX PINMUX_PA23E_TC4_WO1 -/** @} */ - -/** \name Extension header #3 IRQ/External interrupt definitions - * @{ - */ -#define EXT3_IRQ_MODULE EIC -#define EXT3_IRQ_INPUT 6 -#define EXT3_IRQ_PIN PIN_PA06A_EIC_EXTINT6 -#define EXT3_IRQ_MUX MUX_PA06A_EIC_EXTINT6 -#define EXT3_IRQ_PINMUX PINMUX_PA06A_EIC_EXTINT6 -/** @} */ - -/** \name Extension header #3 I2C definitions - * @{ - */ -#define EXT3_I2C_MODULE SERCOM0 -#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0 -#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1 -/** @} */ - -/** \name Extension header #3 UART definitions - * @{ - */ -#define EXT3_UART_MODULE SERCOM1 -#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 -#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_PA00D_SERCOM1_PAD0 -#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_PA01D_SERCOM1_PAD1 -#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED -#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED -/** @} */ - -/** \name Extension header #3 SPI definitions - * @{ - */ -#define EXT3_SPI_MODULE SERCOM1 -#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 -#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED /* PA07 */ -#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 -#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 -/** @} */ - -/** \name Extension header #3 Dataflash - * @{ - */ -#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE -#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING -#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3 -/** @} */ - -/** \name USB definitions - * @{ - */ -#define USB_ID -#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP -#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP -#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP -#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM -#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM -#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM -#define USB_VBUS_PIN PIN_PA05 -#define USB_VBUS_EIC_LINE 5 -#define USB_VBUS_EIC_MUX MUX_PA05A_EIC_EXTINT5 -#define USB_VBUS_EIC_PINMUX PINMUX_PA05A_EIC_EXTINT5 -#define USB_ID_PIN PIN_PA04 -#define USB_ID_EIC_LINE 4 -#define USB_ID_EIC_MUX MUX_PA04A_EIC_EXTINT4 -#define USB_ID_EIC_PINMUX PINMUX_PA04A_EIC_EXTINT4 -/** @} */ - -/** \name Embedded debugger GPIO interface definitions - * @{ - */ -#define EDBG_GPIO0_PIN PIN_PB22 -#define EDBG_GPIO1_PIN PIN_PB23 -#define EDBG_GPIO2_PIN PIN_PA22 -#define EDBG_GPIO3_PIN PIN_PA24 -/** @} */ - -/** \name Embedded debugger USART interface definitions - * @{ - */ -#define EDBG_UART_MODULE -1 /* Not available on this board */ -#define EDBG_UART_RX_PIN -1 /* Not available on this board */ -#define EDBG_UART_RX_MUX -1 /* Not available on this board */ -#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */ -#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */ -#define EDBG_UART_TX_PIN -1 /* Not available on this board */ -#define EDBG_UART_TX_MUX -1 /* Not available on this board */ -#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */ -#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */ -/** @} */ - -/** \name Embedded debugger I2C interface definitions - * @{ - */ -#define EDBG_I2C_MODULE SERCOM0 -#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0 -#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1 -/** @} */ - -/** \name Embedded debugger SPI interface definitions - * @{ - */ -#define EDBG_SPI_MODULE SERCOM1 -#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 -#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED /* PA_06 */ -#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 -#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 -/** @} */ - -/** \name Embedded debugger CDC Gateway USART interface definitions - * @{ - */ -#define EDBG_CDC_MODULE SERCOM4 -#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 -#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_UNUSED -#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2 -#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3 -/** @} */ - -/** @} */ - -/** \name 802.15.4 TRX Interface definitions - * @{ - */ - -#define AT86RFX_SPI EXT1_SPI_MODULE -#define AT86RFX_RST_PIN EXT1_PIN_7 -#define AT86RFX_MISC_PIN EXT1_PIN_12 -#define AT86RFX_IRQ_PIN EXT1_PIN_9 -#define AT86RFX_SLP_PIN EXT1_PIN_10 -#define AT86RFX_SPI_CS EXT1_PIN_15 -#define AT86RFX_SPI_MOSI EXT1_PIN_16 -#define AT86RFX_SPI_MISO EXT1_PIN_17 -#define AT86RFX_SPI_SCK EXT1_PIN_18 -#define AT86RFX_CSD EXT1_PIN_5 -#define AT86RFX_CPS EXT1_PIN_8 - -#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING -#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0 -#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2 -#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3 - -#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT -#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX - - -/** Enables the transceiver main interrupt. */ -#define ENABLE_TRX_IRQ() - -/** Disables the transceiver main interrupt. */ -#define DISABLE_TRX_IRQ() - -/** Clears the transceiver main interrupt. */ -#define CLEAR_TRX_IRQ() - -/* - * This macro saves the trx interrupt status and disables the trx interrupt. - */ -#define ENTER_TRX_REGION() - -/* - * This macro restores the transceiver interrupt status - */ -#define LEAVE_TRX_REGION() - -/** @} */ - -/** - * \brief Turns off the specified LEDs. - * - * \param led_gpio LED to turn off (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true) - -/** - * \brief Turns on the specified LEDs. - * - * \param led_gpio LED to turn on (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false) - -/** - * \brief Toggles the specified LEDs. - * - * \param led_gpio LED to toggle (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio) - -#ifdef __cplusplus -} -#endif - -#endif /* SAMW25_XPLAINED_PRO_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/analogout_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/analogout_api.c deleted file mode 100644 index f11d47fb598..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/analogout_api.c +++ /dev/null @@ -1,115 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "dac.h" - -struct dac_module dac_instance; -extern uint8_t g_sys_init; - -#define MAX_VAL_10BIT 0x03FF - -void analogout_init(dac_t *obj, PinName pin) -{ - MBED_ASSERT(obj); - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - - struct dac_config config_dac; - struct dac_chan_config config_dac_chan; - uint32_t pos_input; - pos_input = pinmap_find_peripheral(pin, PinMap_DAC); - MBED_ASSERT(pos_input != NC); - - obj->dac = DAC_0; - - dac_get_config_defaults(&config_dac); - dac_init(&dac_instance, (Dac *)DAC_0, &config_dac); - - dac_chan_get_config_defaults(&config_dac_chan); - dac_chan_set_config(&dac_instance, DAC_CHANNEL_0, &config_dac_chan); - dac_chan_enable(&dac_instance, DAC_CHANNEL_0); - - dac_enable(&dac_instance); -} - -void analogout_free(dac_t *obj) -{ - MBED_ASSERT(obj); - struct system_pinmux_config pin_conf; - - dac_disable(&dac_instance); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pin_conf.powersave = false; - pin_conf.mux_position = SYSTEM_PINMUX_GPIO; - system_pinmux_pin_set_config(PA02, &pin_conf); /*PA02 is the only DAC pin available*/ -} - -void analogout_write(dac_t *obj, float value) -{ - MBED_ASSERT(obj); - uint16_t count_val = 0; - if (value < 0.0f) { - count_val = 0; - } else if (value > 1.0f) { - count_val = MAX_VAL_10BIT; - } else { - count_val = (uint16_t)(value * (float)MAX_VAL_10BIT); - } - dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val); - -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - MBED_ASSERT(obj); - uint16_t count_val; - count_val = (uint16_t)((value * (float)MAX_VAL_10BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/ - dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val); - -} - -static uint32_t data_reg_read(dac_t *obj) -{ - Dac *const dac_module = (Dac *)obj->dac; - return (uint32_t)dac_module->DATA.reg; -} - -float analogout_read(dac_t *obj) -{ - MBED_ASSERT(obj); - uint32_t data_val = data_reg_read(obj); - return data_val/(float)MAX_VAL_10BIT; -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - MBED_ASSERT(obj); - uint32_t data_val = data_reg_read(obj); - return (uint16_t)((data_val / (float)MAX_VAL_10BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/ -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device.h deleted file mode 100644 index 3b470c68647..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct deleted file mode 100644 index a68af788cee..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct +++ /dev/null @@ -1,50 +0,0 @@ -#! armcc -E - -;SAMD21G18A -; 256KB FLASH (0x40000) @ 0x000000000 -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; SAMD21G18A: 256KB FLASH (0x40000) -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x40000 -#endif - -; 32KB RAM (0x8000) @ 0x20000000 -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x8000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment -#define VECTOR_SIZE 0xB8 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S deleted file mode 100644 index fc1e37a00a4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S +++ /dev/null @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/SAMD21G18A.sct b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/SAMD21G18A.sct deleted file mode 100644 index 61cc8b5128d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/SAMD21G18A.sct +++ /dev/null @@ -1,27 +0,0 @@ -#! armcc -E - -;SAMD21G18A -;256KB FLASH (0x40000) @ 0x000000000 -;2KB RAM (0x8000) @ 0x20000000 - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) -LR_IROM1 0x00000000 0x40000 { ; load region size_region - ER_IROM1 0x00000000 0x40000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment - RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down - } -} \ No newline at end of file diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S deleted file mode 100644 index fc1e37a00a4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S +++ /dev/null @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/samd21g18a.ld b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/samd21g18a.ld deleted file mode 100644 index b5c27ac3e6f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/samd21g18a.ld +++ /dev/null @@ -1,127 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Memory Spaces Definitions */ -MEMORY { - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8 - } - - /* Section Definitions */ - SECTIONS { -.text : - { - . = ALIGN(8); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(8); - KEEP(*(.init)) - . = ALIGN(8); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(8); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(8); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(8); - KEEP(*(.fini)) - - . = ALIGN(8); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(8); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); -.ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(8); - _etext = .; - -.relocate : - AT (_etext) - { - . = ALIGN(8); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(8); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(8); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(8); - _ebss = . ; - _ezero = .; - } > ram - - .heap (NOLOAD) : - { - . = ALIGN(8); - __end__ = . ; - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(ram) + LENGTH(ram); - __StackLimit = __StackTop - STACK_SIZE; - - . = ALIGN(8); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c deleted file mode 100644 index cb64012fe86..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c +++ /dev/null @@ -1,158 +0,0 @@ -#include "samd21.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (void*) (&_estack), - - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ - (void*) USB_Handler, /* 7 Universal Serial Bus */ - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ - (void*) ADC_Handler, /* 23 Analog Digital Converter */ - (void*) AC_Handler, /* 24 Analog Comparators */ - (void*) DAC_Handler, /* 25 Digital Analog Converter */ - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ - (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ // expected to be done by MBED OS - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_IAR/startup_samd21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_IAR/startup_samd21.c deleted file mode 100644 index 9476ec86ed6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_IAR/startup_samd21.c +++ /dev/null @@ -1,173 +0,0 @@ -#include "samd21.h" - -void __iar_program_start(void); -int __low_level_init(void); - -void Dummy_Handler(void); -void Reset_Handler(void); - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} - -/* Cortex-M0+ core handlers */ -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* Cortex-M0+ core handlers */ -#pragma weak NMI_Handler = Dummy_Handler -#pragma weak HardFault_Handler = Dummy_Handler -#pragma weak SVC_Handler = Dummy_Handler -#pragma weak PendSV_Handler = Dummy_Handler -#pragma weak SysTick_Handler = Dummy_Handler - -/* Peripherals handlers */ -#pragma weak PM_Handler = Dummy_Handler -#pragma weak SYSCTRL_Handler = Dummy_Handler -#pragma weak WDT_Handler = Dummy_Handler -#pragma weak RTC_Handler = Dummy_Handler -#pragma weak EIC_Handler = Dummy_Handler -#pragma weak NVMCTRL_Handler = Dummy_Handler -#pragma weak DMAC_Handler = Dummy_Handler -#pragma weak USB_Handler = Dummy_Handler -#pragma weak EVSYS_Handler = Dummy_Handler -#pragma weak SERCOM0_Handler = Dummy_Handler -#pragma weak SERCOM1_Handler = Dummy_Handler -#pragma weak SERCOM2_Handler = Dummy_Handler -#pragma weak SERCOM3_Handler = Dummy_Handler -#pragma weak SERCOM4_Handler = Dummy_Handler -#pragma weak SERCOM5_Handler = Dummy_Handler -#pragma weak TCC0_Handler = Dummy_Handler -#pragma weak TCC1_Handler = Dummy_Handler -#pragma weak TCC2_Handler = Dummy_Handler -#pragma weak TC3_Handler = Dummy_Handler -#pragma weak TC4_Handler = Dummy_Handler -#pragma weak TC5_Handler = Dummy_Handler -#pragma weak TC6_Handler = Dummy_Handler -#pragma weak TC7_Handler = Dummy_Handler -#pragma weak ADC_Handler = Dummy_Handler -#pragma weak AC_Handler = Dummy_Handler -#pragma weak DAC_Handler = Dummy_Handler -#pragma weak PTC_Handler = Dummy_Handler -#pragma weak I2S_Handler = Dummy_Handler - -/* Exception Table */ -#pragma language=extended -#pragma segment="CSTACK" - -/* The name "__vector_table" has special meaning for C-SPY: */ -/* it is where the SP start value is found, and the NVIC vector */ -/* table register (VTOR) is initialized to this address if != 0 */ - -#pragma section = ".intvec" -#pragma location = ".intvec" -//! [startup_vector_table] -const DeviceVectors __vector_table[] = { - __sfe("CSTACK"), - (void*) __iar_program_start, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ - (void*) USB_Handler, /* 7 Universal Serial Bus */ - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ - (void*) ADC_Handler, /* 23 Analog Digital Converter */ - (void*) AC_Handler, /* 24 Analog Comparators */ - (void*) DAC_Handler, /* 25 Digital Analog Converter */ - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ - (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ -}; -//! [startup_vector_table] - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -int __low_level_init(void) -{ - uint32_t *pSrc = __section_begin(".intvec"); - - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - return 1; /* if return 0, the data sections will not be initialized */ -} - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - __iar_program_start(); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralNames.h deleted file mode 100644 index 50c46e0b619..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralNames.h +++ /dev/null @@ -1,158 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include -#include "cmsis.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define _SERCOM_SPI_NAME(n, unused) \ - SPI##n, - -#define _SERCOM_PAD_NAME(n, pad) \ - SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)), - -#define _SERCOM_I2C_NAME(n, unused) \ - I2C##n, - - - -typedef enum { - UART_0 = (int)0x42000800UL, // Base address of SERCOM0 - UART_1 = (int)0x42000C00UL, // Base address of SERCOM1 - UART_2 = (int)0x42001000UL, // Base address of SERCOM2 - UART_3 = (int)0x42001400UL, // Base address of SERCOM3 - UART_4 = (int)0x42001800UL, // Base address of SERCOM4 - UART_5 = (int)0x42001C00UL // Base address of SERCOM5 -} UARTName; - -typedef enum { - ADC_0 = 0x0ul, - ADC_1 = 0x1ul, - ADC_2 = 0x2ul, - ADC_3 = 0x3ul, - ADC_4 = 0x4ul, - ADC_5 = 0x5ul, - ADC_6 = 0x6ul, - ADC_7 = 0x7ul, - ADC_8 = 0x8ul, - ADC_9 = 0x8ul, - ADC_10 = 0xAul, - ADC_11 = 0xBul, - ADC_12 = 0xCul, - ADC_13 = 0xDul, - ADC_14 = 0xEul, - ADC_15 = 0xFul, - ADC_16 = 0x10ul, - ADC_17 = 0x11ul, - ADC_18 = 0x12ul, - ADC_19 = 0x13ul -} ADCName; - -typedef enum { - DAC_0 = 0x42004800UL -} DACName; - -typedef enum { // for each channel - EXTINT_0 = 0, - EXTINT_1, - EXTINT_2, - EXTINT_3, - EXTINT_4, - EXTINT_5, - EXTINT_6, - EXTINT_7, - EXTINT_8, - EXTINT_9, - EXTINT_10, - EXTINT_11, - EXTINT_12, - EXTINT_13, - EXTINT_14, - EXTINT_15 -} EXTINTName; - -typedef enum { - MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~) -} SPIName; - -typedef enum { - MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~) -} I2CName; - -typedef enum { - /* Pad 0 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0) - - /* Pad 1 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1) - - /* Pad 2 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2) - - /* Pad 3 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3) -} SercomPadName; - -typedef enum { - PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */ - PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */ - PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */ -} PWMName; - -struct pwm_pin_channel { - PinName pin; - PWMName pwm; - uint8_t channel_index; -}; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_3 - -// Default peripherals -#define MBED_SPI0 PA18, PA16, PA19, PA17 - -#define MBED_UART0 PA04, PA05 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 PA08, PA09 - -#define MBED_ANALOGOUT0 PA02 - -#define MBED_ANALOGIN0 PA03 -#define MBED_ANALOGIN1 PA08 -#define MBED_ANALOGIN2 PB09 -#define MBED_ANALOGIN3 PA04 -#define MBED_ANALOGIN4 PA05 -#define MBED_ANALOGIN5 PA06 -#define MBED_ANALOGIN7 PA07 -#define MBED_ANALOGIN8 PB00 -#define MBED_ANALOGIN9 PB01 - -#define MBED_PWMOUT0 PA18 -#define MBED_PWMOUT1 PA19 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.c deleted file mode 100644 index 5ab715d6f36..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.c +++ /dev/null @@ -1,286 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PA02, ADC_0, 1}, - {PA03, ADC_1, 1}, - {PB08, ADC_2, 1}, - {PB09, ADC_3, 1}, - {PA04, ADC_4, 1}, - {PA05, ADC_5, 1}, - {PA06, ADC_6, 1}, - {PA07, ADC_7, 1}, - {PB00, ADC_8, 1}, - {PB01, ADC_9, 1}, - {PB02, ADC_10, 1}, - {PB03, ADC_11, 1}, - {PB04, ADC_12, 1}, - {PB05, ADC_13, 1}, - {PB06, ADC_14, 1}, - {PB07, ADC_15, 1}, - {PA08, ADC_16, 1}, - {PA09, ADC_17, 1}, - {PA10, ADC_18, 1}, - {PA11, ADC_19, 1}, - - /* Not connected */ - {NC , NC , NC} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {PA02, DAC_0, 1}, - - /* Not connected */ - {NC , NC , NC} -}; - -/************SERCOM Pins***********/ -const PinMap PinMap_SERCOM_PAD[] = { - {PA00, SERCOM1_PAD0, 3}, - {PA01, SERCOM1_PAD1, 3}, - {PA04, SERCOM0_PAD0, 3}, - {PA05, SERCOM0_PAD1, 3}, - {PA06, SERCOM0_PAD2, 3}, - {PA07, SERCOM0_PAD3, 3}, - {PA08, SERCOM0_PAD0, 2}, - {PA09, SERCOM0_PAD1, 2}, - {PA10, SERCOM0_PAD2, 2}, - {PA11, SERCOM0_PAD3, 2}, - {PA12, SERCOM2_PAD0, 2}, - {PA13, SERCOM2_PAD1, 2}, - {PA14, SERCOM2_PAD2, 2}, - {PA15, SERCOM2_PAD3, 2}, - {PA16, SERCOM1_PAD0, 2}, - {PA17, SERCOM1_PAD1, 2}, - {PA18, SERCOM1_PAD2, 2}, - {PA19, SERCOM1_PAD3, 2}, - {PA20, SERCOM3_PAD2, 3}, - {PA21, SERCOM3_PAD3, 3}, - {PA22, SERCOM3_PAD0, 2}, - {PA23, SERCOM3_PAD1, 2}, - {PA24, SERCOM3_PAD2, 2}, - {PA25, SERCOM3_PAD3, 2}, - {PA30, SERCOM1_PAD2, 3}, - {PA31, SERCOM1_PAD3, 3}, - {PB00, SERCOM5_PAD2, 3}, - {PB01, SERCOM5_PAD3, 3}, - {PB02, SERCOM5_PAD0, 3}, - {PB03, SERCOM5_PAD1, 3}, - {PB08, SERCOM4_PAD0, 3}, - {PB09, SERCOM4_PAD1, 3}, - {PB10, SERCOM4_PAD2, 3}, - {PB11, SERCOM4_PAD3, 3}, - {PB12, SERCOM4_PAD0, 2}, - {PB13, SERCOM4_PAD1, 2}, - {PB14, SERCOM4_PAD2, 2}, - {PB15, SERCOM4_PAD3, 2}, - {PB16, SERCOM5_PAD0, 2}, - {PB17, SERCOM5_PAD1, 2}, - {PB22, SERCOM5_PAD2, 3}, - {PB23, SERCOM5_PAD3, 3}, - {PB30, SERCOM5_PAD0, 3}, - {PB31, SERCOM5_PAD1, 3}, - - /* Not connected */ - {NC , NC , NC} -}; - -/*******SERCOM Pins extended*******/ -const PinMap PinMap_SERCOM_PADEx[] = { - {PA08, SERCOM2_PAD0, 3}, - {PA09, SERCOM2_PAD1, 3}, - {PA10, SERCOM2_PAD2, 3}, - {PA11, SERCOM2_PAD3, 3}, - {PA12, SERCOM4_PAD0, 3}, - {PA13, SERCOM4_PAD1, 3}, - {PA14, SERCOM4_PAD2, 3}, - {PA15, SERCOM4_PAD3, 3}, - {PA16, SERCOM3_PAD0, 3}, - {PA17, SERCOM3_PAD1, 3}, - {PA18, SERCOM3_PAD2, 3}, - {PA19, SERCOM3_PAD3, 3}, - {PA20, SERCOM5_PAD2, 2}, - {PA21, SERCOM5_PAD3, 2}, - {PA22, SERCOM5_PAD0, 3}, - {PA23, SERCOM5_PAD1, 3}, - {PA24, SERCOM5_PAD2, 3}, - {PA25, SERCOM5_PAD3, 3}, - - /* Not connected */ - {NC , NC , NC} -}; - - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PA00, PWM_2, 4}, - {PA01, PWM_2, 4}, - {PA04, PWM_0, 4}, - {PA05, PWM_0, 4}, - {PA06, PWM_1, 4}, - {PA07, PWM_1, 4}, - {PA08, PWM_1, 5}, - {PA09, PWM_1, 5}, - {PA10, PWM_1, 4}, - {PA11, PWM_1, 4}, - {PA12, PWM_2, 4}, - {PA13, PWM_2, 4}, - {PA14, PWM_0, 5}, - {PA15, PWM_0, 5}, - {PA16, PWM_2, 4}, - {PA17, PWM_2, 4}, - {PA18, PWM_0, 5}, - {PA19, PWM_0, 5}, - {PA20, PWM_0, 5}, - {PA21, PWM_0, 5}, - {PA22, PWM_0, 5}, - {PA23, PWM_0, 5}, - {PA24, PWM_1, 5}, - {PA25, PWM_1, 5}, - {PA30, PWM_1, 4}, - {PA31, PWM_1, 4}, - {PB10, PWM_0, 5}, - {PB11, PWM_0, 5}, - {PB12, PWM_0, 5}, - {PB13, PWM_0, 5}, - {PB16, PWM_0, 5}, - {PB17, PWM_0, 5}, - {PB30, PWM_1, 5}, - {PB31, PWM_1, 5}, - - /* Not connected */ - {NC , NC , NC} -}; - -/**********EXTINT*************/ -const PinMap PinMap_EXTINT[] = { - {PA16, EXTINT_0, 0}, - {PB00, EXTINT_0, 0}, - {PB16, EXTINT_0, 0}, - {PA00, EXTINT_0, 0}, - - {PA17, EXTINT_1, 0}, - {PB01, EXTINT_1, 0}, - {PB17, EXTINT_1, 0}, - {PA01, EXTINT_1, 0}, - - {PA18, EXTINT_2, 0}, - {PA02, EXTINT_2, 0}, - {PB02, EXTINT_2, 0}, - - {PA03, EXTINT_3, 0}, - {PA19, EXTINT_3, 0}, - {PB03, EXTINT_3, 0}, - - {PA04, EXTINT_4, 0}, - {PA20, EXTINT_4, 0}, - {PB04, EXTINT_4, 0}, - - {PA05, EXTINT_5, 0}, - {PA21, EXTINT_5, 0}, - {PB05, EXTINT_5, 0}, - - {PA06, EXTINT_6, 0}, - {PA22, EXTINT_6, 0}, - {PB06, EXTINT_6, 0}, - {PB22, EXTINT_6, 0}, - - {PA07, EXTINT_7, 0}, - {PA23, EXTINT_7, 0}, - {PB07, EXTINT_7, 0}, - {PB23, EXTINT_7, 0}, - - {PA28, EXTINT_8, 0}, - {PB08, EXTINT_8, 0}, - - {PA09, EXTINT_9, 0}, - {PB09, EXTINT_9, 0}, - - {PA10, EXTINT_10, 0}, - {PA30, EXTINT_10, 0}, - {PB10, EXTINT_10, 0}, - - {PA11, EXTINT_11, 0}, - {PA31, EXTINT_11, 0}, - {PB11, EXTINT_11, 0}, - - {PA12, EXTINT_12, 0}, - {PA24, EXTINT_12, 0}, - {PB12, EXTINT_12, 0}, - - {PA13, EXTINT_13, 0}, - {PA25, EXTINT_13, 0}, - {PB13, EXTINT_13, 0}, - - {PB14, EXTINT_14, 0}, - {PB30, EXTINT_14, 0}, - {PA14, EXTINT_14, 0}, - - {PA15, EXTINT_15, 0}, - {PA27, EXTINT_15, 0}, - {PB15, EXTINT_15, 0}, - {PB31, EXTINT_15, 0}, - - /* Not connected */ - {NC , NC , NC} -}; - -const struct pwm_pin_channel pwn_pins[] = { - {PA00, PWM_2, 0}, - {PA01, PWM_2, 1}, - {PA04, PWM_0, 0}, - {PA05, PWM_0, 1}, - {PA06, PWM_1, 0}, - {PA07, PWM_1, 1}, - {PA08, PWM_1, 2}, - {PA09, PWM_1, 3}, - {PA10, PWM_1, 0}, - {PA11, PWM_1, 1}, - {PA12, PWM_2, 0}, - {PA13, PWM_2, 1}, - {PA14, PWM_0, 4}, - {PA15, PWM_0, 5}, - {PA16, PWM_2, 0}, - {PA17, PWM_2, 1}, - {PA18, PWM_0, 2}, - {PA19, PWM_0, 3}, - {PA20, PWM_0, 6}, - {PA21, PWM_0, 7}, - {PA22, PWM_0, 4}, - {PA23, PWM_0, 5}, - {PA24, PWM_1, 2}, - {PA25, PWM_1, 3}, - {PA30, PWM_1, 0}, - {PA31, PWM_1, 1}, - {PB10, PWM_0, 4}, - {PB11, PWM_0, 5}, - {PB12, PWM_0, 6}, - {PB13, PWM_0, 7}, - {PB16, PWM_0, 4}, - {PB17, PWM_0, 5}, - {PB30, PWM_1, 2}, - {PB31, PWM_1, 3}, - - /* Not connected */ - {NC , NC , NC} -}; - - - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.h deleted file mode 100644 index 1982babc491..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************DAC***************/ -extern const PinMap PinMap_DAC[]; - -/*********SERCOM*************/ -extern const PinMap PinMap_SERCOM_PAD[]; -extern const PinMap PinMap_SERCOM_PADEx[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -/**********EXTINT*************/ -extern const PinMap PinMap_EXTINT[]; - - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PinNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PinNames.h deleted file mode 100644 index 9a81eb4239d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PinNames.h +++ /dev/null @@ -1,109 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INPUT_OUTPUT //pin state can be set and read back -} PinDirection; - -typedef enum { - PA00 = 0, - PA01 = 1, - PA02 = 2, - PA03 = 3, - PA04 = 4, - PA05 = 5, - PA06 = 6, - PA07 = 7, - PA08 = 8, - PA09 = 9, - PA10 = 10, - PA11 = 11, - PA12 = 12, - PA13 = 13, - PA14 = 14, - PA15 = 15, - PA16 = 16, - PA17 = 17, - PA18 = 18, - PA19 = 19, - PA20 = 20, - PA21 = 21, - PA22 = 22, - PA23 = 23, - PA24 = 24, - PA25 = 25, - PA27 = 27, - PA28 = 28, - PA30 = 30, - PA31 = 31, - - PB00 = 32, - PB01 = 33, - PB02 = 34, - PB03 = 35, - PB04 = 36, - PB05 = 37, - PB06 = 38, - PB07 = 39, - PB08 = 40, - PB09 = 41, - PB10 = 42, - PB11 = 43, - PB12 = 44, - PB13 = 45, - PB14 = 46, - PB15 = 47, - PB16 = 48, - PB17 = 49, - PB22 = 54, - PB23 = 55, - PB30 = 62, - PB31 = 63, - - USBTX = PA22, - USBRX = PA23, - - LED1 = PB30, - LED2 = PB30, - LED3 = PB30, - LED4 = PB30, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c deleted file mode 100644 index f6b9e401051..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c +++ /dev/null @@ -1,32 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "compiler.h" -#include "system.h" - -uint8_t g_sys_init = 0; - -//called before main - implement here if board needs it ortherwise, let -// the application override this if necessary -//TODO: To be implemented by adding system init and board init -void mbed_sdk_init() -{ - if(g_sys_init == 0) { - g_sys_init = 1; - system_init(); - } -} -/***************************************************************/ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h deleted file mode 100644 index 39f3955dd75..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h +++ /dev/null @@ -1,662 +0,0 @@ -#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED -#define SAMD21_XPLAINED_PRO_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup group_common_boards - * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board - * - * @{ - */ - -void system_board_init(void); - -/** - * \defgroup samd21_xplained_pro_features_group Features - * - * Symbols that describe features and capabilities of the board. - * - * @{ - */ - -/** Name string macro */ -#define BOARD_NAME "SAMD21_XPLAINED_PRO" - -/** \name Resonator definitions - * @{ */ -#define BOARD_FREQ_SLCK_XTAL (32768U) -#define BOARD_FREQ_SLCK_BYPASS (32768U) -#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */ -#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */ -#define BOARD_MCK CHIP_FREQ_CPU_MAX -#define BOARD_OSC_STARTUP_US 15625 -/** @} */ - -/** \name LED0 definitions - * @{ */ -#define LED0_PIN PIN_PB30 -#define LED0_ACTIVE false -#define LED0_INACTIVE !LED0_ACTIVE -/** @} */ - -/** \name SW0 definitions - * @{ */ -#define SW0_PIN PIN_PA15 -#define SW0_ACTIVE false -#define SW0_INACTIVE !SW0_ACTIVE -#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15 -#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15 -#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15 -#define SW0_EIC_LINE 15 -/** @} */ - -/** - * \name LED #0 definitions - * - * Wrapper macros for LED0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define LED_0_NAME "LED0 (yellow)" -#define LED_0_PIN LED0_PIN -#define LED_0_ACTIVE LED0_ACTIVE -#define LED_0_INACTIVE LED0_INACTIVE -#define LED0_GPIO LED0_PIN -#define LED0 LED0_PIN - -#define LED_0_PWM4CTRL_MODULE TCC0 -#define LED_0_PWM4CTRL_CHANNEL 0 -#define LED_0_PWM4CTRL_OUTPUT 0 -#define LED_0_PWM4CTRL_PIN PIN_PB30E_TCC0_WO0 -#define LED_0_PWM4CTRL_MUX MUX_PB30E_TCC0_WO0 -#define LED_0_PWM4CTRL_PINMUX PINMUX_PB30E_TCC0_WO0 -/** @} */ - -/** Number of on-board LEDs */ -#define LED_COUNT 1 - -/** - * \name Serialflash definitions - * - * On board Serialflash definitions. - * - * @{ */ -#define SERIALFLASH_SPI_MODULE SERCOM5 -#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 -#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED -#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define SERIALFLASH_SPI_CS PIN_PA13 -/** @} */ - -/** - * \name Button #0 definitions - * - * Wrapper macros for SW0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define BUTTON_0_NAME "SW0" -#define BUTTON_0_PIN SW0_PIN -#define BUTTON_0_ACTIVE SW0_ACTIVE -#define BUTTON_0_INACTIVE SW0_INACTIVE -#define BUTTON_0_EIC_PIN SW0_EIC_PIN -#define BUTTON_0_EIC_MUX SW0_EIC_MUX -#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX -#define BUTTON_0_EIC_LINE SW0_EIC_LINE -/** @} */ - -/** Number of on-board buttons */ -#define BUTTON_COUNT 1 - -/** \name Extension header #1 pin definitions - * @{ - */ -#define EXT1_PIN_3 PIN_PB00 -#define EXT1_PIN_4 PIN_PB01 -#define EXT1_PIN_5 PIN_PB06 -#define EXT1_PIN_6 PIN_PB07 -#define EXT1_PIN_7 PIN_PB02 -#define EXT1_PIN_8 PIN_PB03 -#define EXT1_PIN_9 PIN_PB04 -#define EXT1_PIN_10 PIN_PB05 -#define EXT1_PIN_11 PIN_PA08 -#define EXT1_PIN_12 PIN_PA09 -#define EXT1_PIN_13 PIN_PB09 -#define EXT1_PIN_14 PIN_PB08 -#define EXT1_PIN_15 PIN_PA05 -#define EXT1_PIN_16 PIN_PA06 -#define EXT1_PIN_17 PIN_PA04 -#define EXT1_PIN_18 PIN_PA07 -/** @} */ - -/** \name Extension header #1 pin definitions by function - * @{ - */ -#define EXT1_PIN_ADC_0 EXT1_PIN_3 -#define EXT1_PIN_ADC_1 EXT1_PIN_4 -#define EXT1_PIN_GPIO_0 EXT1_PIN_5 -#define EXT1_PIN_GPIO_1 EXT1_PIN_6 -#define EXT1_PIN_PWM_0 EXT1_PIN_7 -#define EXT1_PIN_PWM_1 EXT1_PIN_8 -#define EXT1_PIN_IRQ EXT1_PIN_9 -#define EXT1_PIN_I2C_SDA EXT1_PIN_11 -#define EXT1_PIN_I2C_SCL EXT1_PIN_12 -#define EXT1_PIN_UART_RX EXT1_PIN_13 -#define EXT1_PIN_UART_TX EXT1_PIN_14 -#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10 -#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 -#define EXT1_PIN_SPI_MOSI EXT1_PIN_16 -#define EXT1_PIN_SPI_MISO EXT1_PIN_17 -#define EXT1_PIN_SPI_SCK EXT1_PIN_18 -/** @} */ - -/** \name Extension header #1 ADC definitions - * @{ - */ -#define EXT1_ADC_MODULE ADC -#define EXT1_ADC_0_CHANNEL 8 -#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8 -#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8 -#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8 -#define EXT1_ADC_1_CHANNEL 9 -#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9 -#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9 -#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9 -/** @} */ - -/** \name Extension header #1 PWM definitions - * @{ - */ -#define EXT1_PWM_MODULE TC6 -#define EXT1_PWM_0_CHANNEL 0 -#define EXT1_PWM_0_PIN PIN_PB02E_TC6_WO0 -#define EXT1_PWM_0_MUX MUX_PB02E_TC6_WO0 -#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC6_WO0 -#define EXT1_PWM_1_CHANNEL 1 -#define EXT1_PWM_1_PIN PIN_PB03E_TC6_WO1 -#define EXT1_PWM_1_MUX MUX_PB03E_TC6_WO1 -#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC6_WO1 -/** @} */ - -/** \name Extension header #1 IRQ/External interrupt definitions - * @{ - */ -#define EXT1_IRQ_MODULE EIC -#define EXT1_IRQ_INPUT 4 -#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4 -#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4 -#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4 -/** @} */ - -/** \name Extension header #1 I2C definitions - * @{ - */ -#define EXT1_I2C_MODULE SERCOM2 -#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 -#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 -#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX -#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX -/** @} */ - -/** \name Extension header #1 UART definitions - * @{ - */ -#define EXT1_UART_MODULE SERCOM4 -#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 -#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0 -#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1 -#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED -#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED -#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX -#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX -/** @} */ - -/** \name Extension header #1 SPI definitions - * @{ - */ -#define EXT1_SPI_MODULE SERCOM0 -#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0 -#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1 -#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2 -#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3 -#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX -#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX -/** @} */ - -/** \name Extension header #2 pin definitions - * @{ - */ -#define EXT2_PIN_3 PIN_PA10 -#define EXT2_PIN_4 PIN_PA11 -#define EXT2_PIN_5 PIN_PA20 -#define EXT2_PIN_6 PIN_PA21 -#define EXT2_PIN_7 PIN_PB12 -#define EXT2_PIN_8 PIN_PB13 -#define EXT2_PIN_9 PIN_PB14 -#define EXT2_PIN_10 PIN_PB15 -#define EXT2_PIN_11 PIN_PA08 -#define EXT2_PIN_12 PIN_PA09 -#define EXT2_PIN_13 PIN_PB11 -#define EXT2_PIN_14 PIN_PB10 -#define EXT2_PIN_15 PIN_PA17 -#define EXT2_PIN_16 PIN_PA18 -#define EXT2_PIN_17 PIN_PA16 -#define EXT2_PIN_18 PIN_PA19 -/** @} */ - -/** \name Extension header #2 pin definitions by function - * @{ - */ -#define EXT2_PIN_ADC_0 EXT2_PIN_3 -#define EXT2_PIN_ADC_1 EXT2_PIN_4 -#define EXT2_PIN_GPIO_0 EXT2_PIN_5 -#define EXT2_PIN_GPIO_1 EXT2_PIN_6 -#define EXT2_PIN_PWM_0 EXT2_PIN_7 -#define EXT2_PIN_PWM_1 EXT2_PIN_8 -#define EXT2_PIN_IRQ EXT2_PIN_9 -#define EXT2_PIN_I2C_SDA EXT2_PIN_11 -#define EXT2_PIN_I2C_SCL EXT2_PIN_12 -#define EXT2_PIN_UART_RX EXT2_PIN_13 -#define EXT2_PIN_UART_TX EXT2_PIN_14 -#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10 -#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15 -#define EXT2_PIN_SPI_MOSI EXT2_PIN_16 -#define EXT2_PIN_SPI_MISO EXT2_PIN_17 -#define EXT2_PIN_SPI_SCK EXT2_PIN_18 -/** @} */ - -/** \name Extension header #2 ADC definitions - * @{ - */ -#define EXT2_ADC_MODULE ADC -#define EXT2_ADC_0_CHANNEL 18 -#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18 -#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18 -#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18 -#define EXT2_ADC_1_CHANNEL 19 -#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19 -#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19 -#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19 -/** @} */ - -/** \name Extension header #2 PWM definitions - * @{ - */ -#define EXT2_PWM_MODULE TC4 -#define EXT2_PWM_0_CHANNEL 0 -#define EXT2_PWM_0_PIN PIN_PB12E_TC4_WO0 -#define EXT2_PWM_0_MUX MUX_PB12E_TC4_WO0 -#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC4_WO0 -#define EXT2_PWM_1_CHANNEL 1 -#define EXT2_PWM_1_PIN PIN_PB13E_TC4_WO1 -#define EXT2_PWM_1_MUX MUX_PB13E_TC4_WO1 -#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC4_WO1 -/** @} */ - -/** \name Extension header #2 PWM for Control definitions - * @{ - */ -#define EXT2_PWM4CTRL_MODULE TCC0 -#define EXT2_PWM4CTRL_0_CHANNEL 2 -#define EXT2_PWM4CTRL_0_OUTPUT 6 -#define EXT2_PWM4CTRL_0_PIN PIN_PB12F_TCC0_WO6 -#define EXT2_PWM4CTRL_0_MUX MUX_PB12F_TCC0_WO6 -#define EXT2_PWM4CTRL_0_PINMUX PINMUX_PB12F_TCC0_WO6 -#define EXT2_PWM4CTRL_1_CHANNEL 3 -#define EXT2_PWM4CTRL_1_OUTPUT 7 -#define EXT2_PWM4CTRL_1_PIN PIN_PB13F_TCC0_WO7 -#define EXT2_PWM4CTRL_1_MUX MUX_PB13F_TCC0_WO7 -#define EXT2_PWM4CTRL_1_PINMUX PINMUX_PB13F_TCC0_WO7 -/** @} */ - -/** \name Extension header #2 IRQ/External interrupt definitions - * @{ - */ -#define EXT2_IRQ_MODULE EIC -#define EXT2_IRQ_INPUT 14 -#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14 -#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14 -#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14 -/** @} */ - -/** \name Extension header #2 I2C definitions -* @{ -*/ -#define EXT2_I2C_MODULE SERCOM2 -#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 -#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 -#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX -#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX -/** @} */ - -/** \name Extension header #2 UART definitions - * @{ - */ -#define EXT2_UART_MODULE SERCOM4 -#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 -#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0 -#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1 -#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED -#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED -#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX -#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX -/** @} */ - -/** \name Extension header #2 SPI definitions - * @{ - */ -#define EXT2_SPI_MODULE SERCOM1 -#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 -#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1 -#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 -#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 -#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX -#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX -/** @} */ - -/** \name Extension header #3 pin definitions - * @{ - */ -#define EXT3_PIN_3 PIN_PA02 -#define EXT3_PIN_4 PIN_PA03 -#define EXT3_PIN_5 PIN_PB30 -#define EXT3_PIN_6 PIN_PA15 -#define EXT3_PIN_7 PIN_PA12 -#define EXT3_PIN_8 PIN_PA13 -#define EXT3_PIN_9 PIN_PA28 -#define EXT3_PIN_10 PIN_PA27 -#define EXT3_PIN_11 PIN_PA08 -#define EXT3_PIN_12 PIN_PA09 -#define EXT3_PIN_13 PIN_PB11 -#define EXT3_PIN_14 PIN_PB10 -#define EXT3_PIN_15 PIN_PB17 -#define EXT3_PIN_16 PIN_PB22 -#define EXT3_PIN_17 PIN_PB16 -#define EXT3_PIN_18 PIN_PB23 -/** @} */ - -/** \name Extension header #3 pin definitions by function - * @{ - */ -#define EXT3_PIN_ADC_0 EXT3_PIN_3 -#define EXT3_PIN_ADC_1 EXT3_PIN_4 -#define EXT3_PIN_GPIO_0 EXT3_PIN_5 -#define EXT3_PIN_GPIO_1 EXT3_PIN_6 -#define EXT3_PIN_PWM_0 EXT3_PIN_7 -#define EXT3_PIN_PWM_1 EXT3_PIN_8 -#define EXT3_PIN_IRQ EXT3_PIN_9 -#define EXT3_PIN_I2C_SDA EXT3_PIN_11 -#define EXT3_PIN_I2C_SCL EXT3_PIN_12 -#define EXT3_PIN_UART_RX EXT3_PIN_13 -#define EXT3_PIN_UART_TX EXT3_PIN_14 -#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10 -#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15 -#define EXT3_PIN_SPI_MOSI EXT3_PIN_16 -#define EXT3_PIN_SPI_MISO EXT3_PIN_17 -#define EXT3_PIN_SPI_SCK EXT3_PIN_18 -/** @} */ - -/** \name Extension header #3 ADC definitions - * @{ - */ -#define EXT3_ADC_MODULE ADC -#define EXT3_ADC_0_CHANNEL 0 -#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0 -#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0 -#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0 -#define EXT3_ADC_1_CHANNEL 1 -#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1 -#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1 -#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1 -/** @} */ - -/** \name Extension header #3 PWM for Control definitions - * @{ - */ -#define EXT3_PWM4CTRL_MODULE TCC2 -#define EXT3_PWM4CTRL_0_CHANNEL 0 -#define EXT3_PWM4CTRL_0_OUTPUT 0 -#define EXT3_PWM4CTRL_0_PIN PIN_PA12E_TCC2_WO0 -#define EXT3_PWM4CTRL_0_MUX MUX_PA12E_TCC2_WO0 -#define EXT3_PWM4CTRL_0_PINMUX PINMUX_PA12E_TCC2_WO0 -#define EXT3_PWM4CTRL_1_CHANNEL 1 -#define EXT3_PWM4CTRL_1_OUTPUT 1 -#define EXT3_PWM4CTRL_1_PIN PIN_PA13E_TCC2_WO1 -#define EXT3_PWM4CTRL_1_MUX MUX_PA13E_TCC2_WO1 -#define EXT3_PWM4CTRL_1_PINMUX PINMUX_PA13E_TCC2_WO1 -/** @} */ - -/** \name Extension header #3 IRQ/External interrupt definitions - * @{ - */ -#define EXT3_IRQ_MODULE EIC -#define EXT3_IRQ_INPUT 8 -#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8 -#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8 -#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8 -/** @} */ - -/** \name Extension header #3 I2C definitions - * @{ - */ -#define EXT3_I2C_MODULE SERCOM2 -#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 -#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 -#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX -#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX -/** @} */ - -/** \name Extension header #3 UART definitions - * @{ - */ -#define EXT3_UART_MODULE SERCOM4 -#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 -#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED -#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2 -#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3 -#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX -#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX -/** @} */ - -/** \name Extension header #3 SPI definitions - * @{ - */ -#define EXT3_SPI_MODULE SERCOM5 -#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 -#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1 -#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX -#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX -/** @} */ - -/** \name Extension header #3 Dataflash - * @{ - */ -#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE -#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING -#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3 -/** @} */ - -/** \name USB definitions - * @{ - */ -#define USB_ID -#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP -#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP -#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP -#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM -#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM -#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM -#define USB_VBUS_PIN PIN_PA14 -#define USB_VBUS_EIC_LINE 14 -#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14 -#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14 -#define USB_ID_PIN PIN_PA03 -#define USB_ID_EIC_LINE 3 -#define USB_ID_EIC_MUX MUX_PA03A_EIC_EXTINT3 -#define USB_ID_EIC_PINMUX PINMUX_PA03A_EIC_EXTINT3 -/** @} */ - -/** \name Embedded debugger GPIO interface definitions - * @{ - */ -#define EDBG_GPIO0_PIN PIN_PA27 -#define EDBG_GPIO1_PIN PIN_PA28 -#define EDBG_GPIO2_PIN PIN_PA20 -#define EDBG_GPIO3_PIN PIN_PA21 -/** @} */ - -/** \name Embedded debugger USART interface definitions - * @{ - */ -#define EDBG_UART_MODULE -1 /* Not available on this board */ -#define EDBG_UART_RX_PIN -1 /* Not available on this board */ -#define EDBG_UART_RX_MUX -1 /* Not available on this board */ -#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */ -#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */ -#define EDBG_UART_TX_PIN -1 /* Not available on this board */ -#define EDBG_UART_TX_MUX -1 /* Not available on this board */ -#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */ -#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */ -/** @} */ - -/** \name Embedded debugger I2C interface definitions - * @{ - */ -#define EDBG_I2C_MODULE SERCOM2 -#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 -#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 -#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX -#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX -/** @} */ - -/** \name Embedded debugger SPI interface definitions - * @{ - */ -#define EDBG_SPI_MODULE SERCOM5 -#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 -#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1 -#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX -#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX -/** @} */ - -/** \name Embedded debugger CDC Gateway USART interface definitions - * @{ - */ -#define EDBG_CDC_MODULE SERCOM3 -#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 -#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0 -#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1 -#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED -#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED -#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX -#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX -/** @} */ - -/** @} */ - -/** \name 802.15.4 TRX Interface definitions - * @{ - */ - -#define AT86RFX_SPI EXT1_SPI_MODULE -#define AT86RFX_RST_PIN EXT1_PIN_7 -#define AT86RFX_MISC_PIN EXT1_PIN_12 -#define AT86RFX_IRQ_PIN EXT1_PIN_9 -#define AT86RFX_SLP_PIN EXT1_PIN_10 -#define AT86RFX_SPI_CS EXT1_PIN_15 -#define AT86RFX_SPI_MOSI EXT1_PIN_16 -#define AT86RFX_SPI_MISO EXT1_PIN_17 -#define AT86RFX_SPI_SCK EXT1_PIN_18 -#define AT86RFX_CSD EXT1_PIN_5 -#define AT86RFX_CPS EXT1_PIN_8 - -#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING -#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0 -#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2 -#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3 - -#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT -#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX - - -/** Enables the transceiver main interrupt. */ -#define ENABLE_TRX_IRQ() \ - extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT) - -/** Disables the transceiver main interrupt. */ -#define DISABLE_TRX_IRQ() \ - extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT) - -/** Clears the transceiver main interrupt. */ -#define CLEAR_TRX_IRQ() \ - extint_chan_clear_detected(AT86RFX_IRQ_CHAN); - -/* - * This macro saves the trx interrupt status and disables the trx interrupt. - */ -#define ENTER_TRX_REGION() \ - { extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT) - -/* - * This macro restores the transceiver interrupt status - */ -#define LEAVE_TRX_REGION() \ - extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); } - -/** @} */ - -/** - * \brief Turns off the specified LEDs. - * - * \param led_gpio LED to turn off (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true) - -/** - * \brief Turns on the specified LEDs. - * - * \param led_gpio LED to turn on (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false) - -/** - * \brief Toggles the specified LEDs. - * - * \param led_gpio LED to toggle (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio) - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* SAMD21_XPLAINED_PRO_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/analogout_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/analogout_api.c deleted file mode 100644 index f11d47fb598..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/analogout_api.c +++ /dev/null @@ -1,115 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "dac.h" - -struct dac_module dac_instance; -extern uint8_t g_sys_init; - -#define MAX_VAL_10BIT 0x03FF - -void analogout_init(dac_t *obj, PinName pin) -{ - MBED_ASSERT(obj); - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - - struct dac_config config_dac; - struct dac_chan_config config_dac_chan; - uint32_t pos_input; - pos_input = pinmap_find_peripheral(pin, PinMap_DAC); - MBED_ASSERT(pos_input != NC); - - obj->dac = DAC_0; - - dac_get_config_defaults(&config_dac); - dac_init(&dac_instance, (Dac *)DAC_0, &config_dac); - - dac_chan_get_config_defaults(&config_dac_chan); - dac_chan_set_config(&dac_instance, DAC_CHANNEL_0, &config_dac_chan); - dac_chan_enable(&dac_instance, DAC_CHANNEL_0); - - dac_enable(&dac_instance); -} - -void analogout_free(dac_t *obj) -{ - MBED_ASSERT(obj); - struct system_pinmux_config pin_conf; - - dac_disable(&dac_instance); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pin_conf.powersave = false; - pin_conf.mux_position = SYSTEM_PINMUX_GPIO; - system_pinmux_pin_set_config(PA02, &pin_conf); /*PA02 is the only DAC pin available*/ -} - -void analogout_write(dac_t *obj, float value) -{ - MBED_ASSERT(obj); - uint16_t count_val = 0; - if (value < 0.0f) { - count_val = 0; - } else if (value > 1.0f) { - count_val = MAX_VAL_10BIT; - } else { - count_val = (uint16_t)(value * (float)MAX_VAL_10BIT); - } - dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val); - -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - MBED_ASSERT(obj); - uint16_t count_val; - count_val = (uint16_t)((value * (float)MAX_VAL_10BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/ - dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val); - -} - -static uint32_t data_reg_read(dac_t *obj) -{ - Dac *const dac_module = (Dac *)obj->dac; - return (uint32_t)dac_module->DATA.reg; -} - -float analogout_read(dac_t *obj) -{ - MBED_ASSERT(obj); - uint32_t data_val = data_reg_read(obj); - return data_val/(float)MAX_VAL_10BIT; -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - MBED_ASSERT(obj); - uint32_t data_val = data_reg_read(obj); - return (uint16_t)((data_val / (float)MAX_VAL_10BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/ -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device.h deleted file mode 100644 index 3b470c68647..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct deleted file mode 100644 index 099b6029764..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct +++ /dev/null @@ -1,50 +0,0 @@ -#! armcc -E - -;SAMD21J18A -; 256KB FLASH (0x40000) @ 0x000000000 -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; SAMD21J18A: 256KB FLASH (0x40000) -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x40000 -#endif - -; 32KB RAM (0x8000) @ 0x20000000 -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x8000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment -#define VECTOR_SIZE 0xB8 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S deleted file mode 100644 index fc1e37a00a4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S +++ /dev/null @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/SAMD21J18A.sct b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/SAMD21J18A.sct deleted file mode 100644 index ad1df9d8cd0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/SAMD21J18A.sct +++ /dev/null @@ -1,27 +0,0 @@ -#! armcc -E - -;SAMD21J18A -;256KB FLASH (0x40000) @ 0x000000000 -;2KB RAM (0x8000) @ 0x20000000 - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) -LR_IROM1 0x00000000 0x40000 { ; load region size_region - ER_IROM1 0x00000000 0x40000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment - RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down - } -} \ No newline at end of file diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S deleted file mode 100644 index fc1e37a00a4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S +++ /dev/null @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/samd21j18a.ld b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/samd21j18a.ld deleted file mode 100644 index 52f2992e41a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/samd21j18a.ld +++ /dev/null @@ -1,127 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Memory Spaces Definitions */ -MEMORY { - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8 - } - - /* Section Definitions */ - SECTIONS { -.text : - { - . = ALIGN(8); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(8); - KEEP(*(.init)) - . = ALIGN(8); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(8); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(8); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(8); - KEEP(*(.fini)) - - . = ALIGN(8); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(8); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); -.ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(8); - _etext = .; - -.relocate : - AT (_etext) - { - . = ALIGN(8); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(8); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(8); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(8); - _ebss = . ; - _ezero = .; - } > ram - - .heap (NOLOAD) : - { - . = ALIGN(8); - __end__ = . ; - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - - . = ALIGN(8); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c deleted file mode 100644 index cb64012fe86..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c +++ /dev/null @@ -1,158 +0,0 @@ -#include "samd21.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (void*) (&_estack), - - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ - (void*) USB_Handler, /* 7 Universal Serial Bus */ - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ - (void*) ADC_Handler, /* 23 Analog Digital Converter */ - (void*) AC_Handler, /* 24 Analog Comparators */ - (void*) DAC_Handler, /* 25 Digital Analog Converter */ - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ - (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ // expected to be done by MBED OS - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_IAR/startup_samd21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_IAR/startup_samd21.c deleted file mode 100644 index 9476ec86ed6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_IAR/startup_samd21.c +++ /dev/null @@ -1,173 +0,0 @@ -#include "samd21.h" - -void __iar_program_start(void); -int __low_level_init(void); - -void Dummy_Handler(void); -void Reset_Handler(void); - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} - -/* Cortex-M0+ core handlers */ -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* Cortex-M0+ core handlers */ -#pragma weak NMI_Handler = Dummy_Handler -#pragma weak HardFault_Handler = Dummy_Handler -#pragma weak SVC_Handler = Dummy_Handler -#pragma weak PendSV_Handler = Dummy_Handler -#pragma weak SysTick_Handler = Dummy_Handler - -/* Peripherals handlers */ -#pragma weak PM_Handler = Dummy_Handler -#pragma weak SYSCTRL_Handler = Dummy_Handler -#pragma weak WDT_Handler = Dummy_Handler -#pragma weak RTC_Handler = Dummy_Handler -#pragma weak EIC_Handler = Dummy_Handler -#pragma weak NVMCTRL_Handler = Dummy_Handler -#pragma weak DMAC_Handler = Dummy_Handler -#pragma weak USB_Handler = Dummy_Handler -#pragma weak EVSYS_Handler = Dummy_Handler -#pragma weak SERCOM0_Handler = Dummy_Handler -#pragma weak SERCOM1_Handler = Dummy_Handler -#pragma weak SERCOM2_Handler = Dummy_Handler -#pragma weak SERCOM3_Handler = Dummy_Handler -#pragma weak SERCOM4_Handler = Dummy_Handler -#pragma weak SERCOM5_Handler = Dummy_Handler -#pragma weak TCC0_Handler = Dummy_Handler -#pragma weak TCC1_Handler = Dummy_Handler -#pragma weak TCC2_Handler = Dummy_Handler -#pragma weak TC3_Handler = Dummy_Handler -#pragma weak TC4_Handler = Dummy_Handler -#pragma weak TC5_Handler = Dummy_Handler -#pragma weak TC6_Handler = Dummy_Handler -#pragma weak TC7_Handler = Dummy_Handler -#pragma weak ADC_Handler = Dummy_Handler -#pragma weak AC_Handler = Dummy_Handler -#pragma weak DAC_Handler = Dummy_Handler -#pragma weak PTC_Handler = Dummy_Handler -#pragma weak I2S_Handler = Dummy_Handler - -/* Exception Table */ -#pragma language=extended -#pragma segment="CSTACK" - -/* The name "__vector_table" has special meaning for C-SPY: */ -/* it is where the SP start value is found, and the NVIC vector */ -/* table register (VTOR) is initialized to this address if != 0 */ - -#pragma section = ".intvec" -#pragma location = ".intvec" -//! [startup_vector_table] -const DeviceVectors __vector_table[] = { - __sfe("CSTACK"), - (void*) __iar_program_start, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ - (void*) USB_Handler, /* 7 Universal Serial Bus */ - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ - (void*) ADC_Handler, /* 23 Analog Digital Converter */ - (void*) AC_Handler, /* 24 Analog Comparators */ - (void*) DAC_Handler, /* 25 Digital Analog Converter */ - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ - (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ -}; -//! [startup_vector_table] - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -int __low_level_init(void) -{ - uint32_t *pSrc = __section_begin(".intvec"); - - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - return 1; /* if return 0, the data sections will not be initialized */ -} - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - __iar_program_start(); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis.h deleted file mode 100644 index 116f676c15e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in samr21j18a specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "saml21.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis_nvic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis_nvic.h deleted file mode 100644 index 3d787468a37..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis_nvic.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 29) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralNames.h deleted file mode 100644 index 66ac2f0add8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralNames.h +++ /dev/null @@ -1,161 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include -#include "cmsis.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define _SERCOM_SPI_NAME(n, unused) \ - SPI##n, - -#define _SERCOM_PAD_NAME(n, pad) \ - SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)), - -#define _SERCOM_I2C_NAME(n, unused) \ - I2C##n, - - - -typedef enum { - UART_0 = (int)0x42000000UL, // Base address of SERCOM0 - UART_1 = (int)0x42000400UL, // Base address of SERCOM1 - UART_2 = (int)0x42000800UL, // Base address of SERCOM2 - UART_3 = (int)0x42000C00UL, // Base address of SERCOM3 - UART_4 = (int)0x42001000UL, // Base address of SERCOM4 - UART_5 = (int)0x43000400UL // Base address of SERCOM5 -} UARTName; - -typedef enum { - ADC_0 = 0x0ul, - ADC_1 = 0x1ul, - ADC_2 = 0x2ul, - ADC_3 = 0x3ul, - ADC_4 = 0x4ul, - ADC_5 = 0x5ul, - ADC_6 = 0x6ul, - ADC_7 = 0x7ul, - ADC_8 = 0x8ul, - ADC_9 = 0x9ul, - ADC_10 = 0xAul, - ADC_11 = 0xBul, - ADC_12 = 0xCul, - ADC_13 = 0xDul, - ADC_14 = 0xEul, - ADC_15 = 0xFul, - ADC_16 = 0x10ul, - ADC_17 = 0x11ul, - ADC_18 = 0x12ul, - ADC_19 = 0x13ul -} ADCName; - -typedef enum { - DAC_0 = 0x42003000UL -} DACName; - -typedef enum { // for each channel - EXTINT_0 = 0, - EXTINT_1, - EXTINT_2, - EXTINT_3, - EXTINT_4, - EXTINT_5, - EXTINT_6, - EXTINT_7, - EXTINT_8, - EXTINT_9, - EXTINT_10, - EXTINT_11, - EXTINT_12, - EXTINT_13, - EXTINT_14, - EXTINT_15 -} EXTINTName; - -typedef enum { - MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~) -} SPIName; - -typedef enum { - MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~) -} I2CName; - -typedef enum { - /* Pad 0 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0) - - /* Pad 1 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1) - - /* Pad 2 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2) - - /* Pad 3 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3) -} SercomPadName; - -typedef enum { - PWM_0 = (0x42001400UL), /**< \brief (TCC0) APB Base Address */ - PWM_1 = (0x42001800UL), /**< \brief (TCC1) APB Base Address */ - PWM_2 = (0x42001C00UL), /**< \brief (TCC2) APB Base Address */ -} PWMName; - -struct pwm_pin_channel { - PinName pin; - PWMName pwm; - uint8_t channel_index; -}; - -struct dac_pin_channel { - PinName pin; - DACName dac; - uint8_t channel_index; -}; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_3 - -// Default peripherals -#define MBED_SPI0 PA06, PA04, PA07, PA05 - -#define MBED_UART0 PB08, PB09 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 PA08, PA09 - -#define MBED_ANALOGIN0 PB05 -#define MBED_ANALOGIN1 PA03 -#define MBED_ANALOGIN2 PA06 -#define MBED_ANALOGIN3 PA07 -#define MBED_ANALOGIN4 PB02 -#define MBED_ANALOGIN5 PB03 -#define MBED_ANALOGIN7 PA08 -#define MBED_ANALOGIN8 PA09 - -#define MBED_PWMOUT0 PB12 -#define MBED_PWMOUT1 PB13 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.c deleted file mode 100644 index ebb38b66ae9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.c +++ /dev/null @@ -1,313 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PA02, ADC_0, 1}, - {PA03, ADC_1, 1}, - {PB08, ADC_2, 1}, - {PB09, ADC_3, 1}, - {PA04, ADC_4, 1}, - {PA05, ADC_5, 1}, - {PA06, ADC_6, 1}, - {PA07, ADC_7, 1}, - {PB00, ADC_8, 1}, - {PB01, ADC_9, 1}, - {PB02, ADC_10, 1}, - {PB03, ADC_11, 1}, - {PB04, ADC_12, 1}, - {PB05, ADC_13, 1}, - {PB06, ADC_14, 1}, - {PB07, ADC_15, 1}, - {PA08, ADC_16, 1}, - {PA09, ADC_17, 1}, - {PA10, ADC_18, 1}, - {PA11, ADC_19, 1}, - - /* Not connected */ - {NC , NC , NC} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {PA02, DAC_0, 1}, - {PA05, DAC_0, 1}, - - /* Not connected */ - {NC , NC , NC} -}; - -/************SERCOM Pins***********/ -const PinMap PinMap_SERCOM_PAD[] = { - {PA04, SERCOM0_PAD0, 3}, - {PA08, SERCOM0_PAD0, 2}, - {PA05, SERCOM0_PAD1, 3}, - {PA09, SERCOM0_PAD1, 2}, - {PA06, SERCOM0_PAD2, 3}, - {PA10, SERCOM0_PAD2, 2}, - {PA07, SERCOM0_PAD3, 3}, - {PA11, SERCOM0_PAD3, 2}, - {PA16, SERCOM1_PAD0, 2}, - {PA00, SERCOM1_PAD0, 3}, - {PA17, SERCOM1_PAD1, 2}, - {PA01, SERCOM1_PAD1, 3}, - {PA30, SERCOM1_PAD2, 3}, - {PA18, SERCOM1_PAD2, 2}, - {PA31, SERCOM1_PAD3, 3}, - {PA19, SERCOM1_PAD3, 2}, - {PA12, SERCOM2_PAD0, 2}, - {PA13, SERCOM2_PAD1, 2}, - {PA14, SERCOM2_PAD2, 2}, - {PA15, SERCOM2_PAD3, 2}, - {PA22, SERCOM3_PAD0, 2}, - {PA27, SERCOM3_PAD0, 5}, - {PA23, SERCOM3_PAD1, 2}, - {PA20, SERCOM3_PAD2, 3}, - {PA24, SERCOM3_PAD2, 2}, - {PA21, SERCOM3_PAD3, 3}, - {PA25, SERCOM3_PAD3, 2}, - {PB08, SERCOM4_PAD0, 3}, - {PB12, SERCOM4_PAD0, 2}, - {PB09, SERCOM4_PAD1, 3}, - {PB13, SERCOM4_PAD1, 2}, - {PB31, SERCOM4_PAD1, 5}, - {PB10, SERCOM4_PAD2, 3}, - {PB14, SERCOM4_PAD2, 2}, - {PB30, SERCOM4_PAD2, 5}, - {PB11, SERCOM4_PAD3, 3}, - {PB15, SERCOM4_PAD3, 2}, - {PB02, SERCOM5_PAD0, 3}, - {PB16, SERCOM5_PAD0, 2}, - {PB03, SERCOM5_PAD1, 3}, - {PB17, SERCOM5_PAD1, 2}, - {PB00, SERCOM5_PAD2, 3}, - {PB22, SERCOM5_PAD2, 3}, - {PB01, SERCOM5_PAD3, 3}, - {PB23, SERCOM5_PAD3, 3}, - - /* Not connected */ - {NC , NC , NC} -}; - -/*******SERCOM Pins extended*******/ -const PinMap PinMap_SERCOM_PADEx[] = { - {PA08, SERCOM2_PAD0, 3}, - {PA09, SERCOM2_PAD1, 3}, - {PA10, SERCOM2_PAD2, 3}, - {PA11, SERCOM2_PAD3, 3}, - {PA16, SERCOM3_PAD0, 3}, - {PA17, SERCOM3_PAD1, 3}, - {PA18, SERCOM3_PAD2, 3}, - {PA19, SERCOM3_PAD3, 3}, - {PA12, SERCOM4_PAD0, 3}, - {PA13, SERCOM4_PAD1, 3}, - {PA14, SERCOM4_PAD2, 3}, - {PA15, SERCOM4_PAD3, 3}, - {PA22, SERCOM5_PAD0, 3}, - {PA23, SERCOM5_PAD1, 3}, - {PA20, SERCOM5_PAD2, 2}, - {PA24, SERCOM5_PAD2, 3}, - {PA21, SERCOM5_PAD3, 2}, - {PA25, SERCOM5_PAD3, 3}, - {PB31, SERCOM5_PAD1, 3}, - {PB30, SERCOM5_PAD0, 3}, - - /* Not connected */ - {NC , NC , NC} -}; - - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PA04, PWM_0, 4}, - {PA08, PWM_0, 4}, - {PB30, PWM_0, 4}, - {PA16, PWM_0, 5}, - {PA05, PWM_0, 4}, - {PA09, PWM_0, 4}, - {PB31, PWM_0, 4}, - {PA17, PWM_2, 4}, - {PA10, PWM_0, 5}, - {PA18, PWM_0, 5}, - {PA11, PWM_0, 5}, - {PA19, PWM_0, 5}, - {PA22, PWM_0, 5}, - {PB10, PWM_0, 5}, - {PB16, PWM_0, 5}, - {PA14, PWM_0, 5}, - {PA15, PWM_0, 5}, - {PA23, PWM_0, 5}, - {PB11, PWM_0, 5}, - {PB17, PWM_0, 5}, - {PA12, PWM_0, 5}, - {PA16, PWM_0, 5}, - {PA20, PWM_0, 5}, - {PB12, PWM_0, 5}, - {PA13, PWM_0, 5}, - {PA17, PWM_0, 5}, - {PA21, PWM_0, 5}, - {PB13, PWM_0, 5}, - {PA06, PWM_1, 4}, - {PA10, PWM_1, 4}, - {PA30, PWM_1, 4}, - {PA07, PWM_1, 4}, - {PA11, PWM_1, 4}, - {PA31, PWM_1, 4}, - {PA08, PWM_1, 5}, - {PA24, PWM_1, 5}, - {PB30, PWM_1, 5}, - {PA09, PWM_1, 5}, - {PA25, PWM_1, 5}, - {PB31, PWM_1, 5}, - {PA12, PWM_2, 4}, - {PA16, PWM_2, 4}, - {PA00, PWM_2, 4}, - {PA13, PWM_2, 4}, - {PA17, PWM_2, 4}, - {PA01, PWM_2, 4}, - - /* Not connected */ - {NC , NC , NC} -}; - -/**********EXTINT*************/ -const PinMap PinMap_EXTINT[] = { - {PA16, EXTINT_0, 0}, - {PB00, EXTINT_0, 0}, - {PB16, EXTINT_0, 0}, - {PA00, EXTINT_0, 0}, - - {PA17, EXTINT_1, 0}, - {PB01, EXTINT_1, 0}, - {PB17, EXTINT_1, 0}, - {PA01, EXTINT_1, 0}, - - {PA02, EXTINT_2, 0}, - {PA18, EXTINT_2, 0}, - {PB02, EXTINT_2, 0}, - - {PA03, EXTINT_3, 0}, - {PA19, EXTINT_3, 0}, - {PB03, EXTINT_3, 0}, - - {PA04, EXTINT_4, 0}, - {PA20, EXTINT_4, 0}, - {PB04, EXTINT_4, 0}, - - {PA05, EXTINT_5, 0}, - {PA21, EXTINT_5, 0}, - {PB05, EXTINT_5, 0}, - - {PA06, EXTINT_6, 0}, - {PA22, EXTINT_6, 0}, - {PB06, EXTINT_6, 0}, - {PB22, EXTINT_6, 0}, - - {PA07, EXTINT_7, 0}, - {PA23, EXTINT_7, 0}, - {PB07, EXTINT_7, 0}, - {PB23, EXTINT_7, 0}, - - {PB08, EXTINT_8, 0}, - - {PA09, EXTINT_9, 0}, - {PB09, EXTINT_9, 0}, - - {PA10, EXTINT_10, 0}, - {PA30, EXTINT_10, 0}, - {PB10, EXTINT_10, 0}, - - {PA11, EXTINT_11, 0}, - {PA31, EXTINT_11, 0}, - {PB11, EXTINT_11, 0}, - - {PA12, EXTINT_12, 0}, - {PA24, EXTINT_12, 0}, - {PB12, EXTINT_12, 0}, - - {PA13, EXTINT_13, 0}, - {PA25, EXTINT_13, 0}, - {PB13, EXTINT_13, 0}, - - {PB14, EXTINT_14, 0}, - {PB30, EXTINT_14, 0}, - {PA14, EXTINT_14, 0}, - - {PA27, EXTINT_15, 0}, - {PB15, EXTINT_15, 0}, - {PB31, EXTINT_15, 0}, - {PA15, EXTINT_15, 0}, - - /* Not connected */ - {NC , NC , NC} -}; - -const struct pwm_pin_channel pwn_pins[] = { - {PA04, PWM_0, 0}, - {PA08, PWM_0, 0}, - {PB30, PWM_0, 0}, - {PA16, PWM_0, 6}, - {PA05, PWM_0, 1}, - {PA09, PWM_0, 1}, - {PB31, PWM_0, 1}, - {PA17, PWM_0, 1}, - {PA10, PWM_0, 2}, - {PA18, PWM_0, 2}, - {PA11, PWM_0, 3}, - {PA19, PWM_0, 3}, - {PA22, PWM_0, 4}, - {PB10, PWM_0, 4}, - {PB16, PWM_0, 4}, - {PA14, PWM_0, 4}, - {PA15, PWM_0, 5}, - {PA23, PWM_0, 5}, - {PB11, PWM_0, 5}, - {PB17, PWM_0, 5}, - {PA12, PWM_0, 6}, - {PA16, PWM_0, 6}, - {PA20, PWM_0, 6}, - {PB12, PWM_0, 6}, - {PA13, PWM_0, 7}, - {PA17, PWM_2, 1}, - {PA21, PWM_0, 7}, - {PB13, PWM_0, 7}, - {PA06, PWM_1, 0}, - {PA10, PWM_1, 0}, - {PA30, PWM_1, 0}, - {PA07, PWM_1, 1}, - {PA11, PWM_1, 1}, - {PA31, PWM_1, 1}, - {PA08, PWM_1, 2}, - {PA24, PWM_1, 2}, - {PB30, PWM_1, 2}, - {PA09, PWM_1, 3}, - {PA25, PWM_1, 3}, - {PB31, PWM_1, 3}, - {PA12, PWM_2, 0}, - {PA16, PWM_2, 0}, - {PA00, PWM_2, 0}, - {PA13, PWM_2, 1}, - {PA17, PWM_2, 1}, - {PA01, PWM_2, 1}, - - /* Not connected */ - {NC , NC , NC} -}; - - - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.h deleted file mode 100644 index 9c66f5587a3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************DAC***************/ -extern const PinMap PinMap_DAC[]; - -/*********SERCOM*************/ -extern const PinMap PinMap_SERCOM_PAD[]; -extern const PinMap PinMap_SERCOM_PADEx[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -/**********EXTINT*************/ -extern const PinMap PinMap_EXTINT[]; - - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PinNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PinNames.h deleted file mode 100644 index 27e0c66f3ed..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PinNames.h +++ /dev/null @@ -1,107 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INPUT_OUTPUT //pin state can be set and read back -} PinDirection; - -typedef enum { - PA00 = 0, - PA01 = 1, - PA02 = 2, - PA03 = 3, - PA04 = 4, - PA05 = 5, - PA06 = 6, - PA07 = 7, - PA08 = 8, - PA09 = 9, - PA10 = 10, - PA11 = 11, - PA12 = 12, - PA13 = 13, - PA14 = 14, - PA15 = 15, - PA16 = 16, - PA17 = 17, - PA18 = 18, - PA19 = 19, - PA20 = 20, - PA21 = 21, - PA22 = 22, - PA23 = 23, - PA24 = 24, - PA25 = 25, - PA27 = 27, - PA30 = 30, - PA31 = 31, - PB00 = 32, - PB01 = 33, - PB02 = 34, - PB03 = 35, - PB04 = 36, - PB05 = 37, - PB06 = 38, - PB07 = 39, - PB08 = 40, - PB09 = 41, - PB10 = 42, - PB11 = 43, - PB12 = 44, - PB13 = 45, - PB14 = 46, - PB15 = 47, - PB16 = 48, - PB17 = 49, - PB22 = 54, - PB23 = 55, - PB30 = 62, - PB31 = 63, - - USBTX = PA22, - USBRX = PA23, - - LED1 = PB10, - LED2 = PB10, - LED3 = PB10, - LED4 = PB10, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/mbed_overrides.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/mbed_overrides.c deleted file mode 100644 index 73e8d6009b5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/mbed_overrides.c +++ /dev/null @@ -1,32 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "compiler.h" -#include "system.h" - -uint8_t g_sys_init = 0; - -//called before main - implement here if board needs it ortherwise, let -// the application override this if necessary -//TODO: To be implemented by adding system init and board init -void mbed_sdk_init() -{ - if(g_sys_init == 0) { - g_sys_init = 1; - system_init(); - } -} -/***************************************************************/ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/saml21_xplained_pro.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/saml21_xplained_pro.h deleted file mode 100644 index 27e9f03764c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/saml21_xplained_pro.h +++ /dev/null @@ -1,599 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Xplained Pro board definition - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SAML21_XPLAINED_PRO_H_INCLUDED -#define SAML21_XPLAINED_PRO_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup group_common_boards - * \defgroup saml21_xplained_pro_group SAM L21 Xplained Pro board - * - * @{ - */ - -void system_board_init(void); - -/** - * \defgroup saml21_xplained_pro_features_group Features - * - * Symbols that describe features and capabilities of the board. - * - * @{ - */ - -/** Name string macro */ -#define BOARD_NAME "SAML21_XPLAINED_PRO" - -/** \name Resonator definitions - * @{ */ -#define BOARD_FREQ_SLCK_XTAL (32768U) -#define BOARD_FREQ_SLCK_BYPASS (32768U) -#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */ -#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */ -#define BOARD_MCK CHIP_FREQ_CPU_MAX -#define BOARD_OSC_STARTUP_US 15625 -/** @} */ - -/** \name LED0 definitions - * @{ */ -#define LED0_PIN PIN_PB10 -#define LED0_ACTIVE false -#define LED0_INACTIVE !LED0_ACTIVE -/** @} */ - -/** \name SW0 definitions - * @{ */ -#define SW0_PIN PIN_PA02 -#define SW0_ACTIVE false -#define SW0_INACTIVE !SW0_ACTIVE -#define SW0_EIC_PIN PIN_PA02A_EIC_EXTINT2 -#define SW0_EIC_MUX MUX_PA02A_EIC_EXTINT2 -#define SW0_EIC_PINMUX PINMUX_PA02A_EIC_EXTINT2 -#define SW0_EIC_LINE 2 -/** @} */ - -/** - * \name LED #0 definitions - * - * Wrapper macros for LED0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define LED_0_NAME "LED0 (yellow)" -#define LED_0_PIN LED0_PIN -#define LED_0_ACTIVE LED0_ACTIVE -#define LED_0_INACTIVE LED0_INACTIVE -#define LED0_GPIO LED0_PIN -#define LED0 LED0_PIN - -#define LED_0_PWM4CTRL_MODULE TCC0 -#define LED_0_PWM4CTRL_CHANNEL 0 -#define LED_0_PWM4CTRL_OUTPUT 0 -#define LED_0_PWM4CTRL_PIN PIN_PB10F_TCC0_WO4 -#define LED_0_PWM4CTRL_MUX MUX_PB10F_TCC0_WO4 -#define LED_0_PWM4CTRL_PINMUX PINMUX_PB10F_TCC0_WO4 -/** @} */ - -/** Number of on-board LEDs */ -#define LED_COUNT 1 - - -/** - * \name Button #0 definitions - * - * Wrapper macros for SW0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define BUTTON_0_NAME "SW0" -#define BUTTON_0_PIN SW0_PIN -#define BUTTON_0_ACTIVE SW0_ACTIVE -#define BUTTON_0_INACTIVE SW0_INACTIVE -#define BUTTON_0_EIC_PIN SW0_EIC_PIN -#define BUTTON_0_EIC_MUX SW0_EIC_MUX -#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX -#define BUTTON_0_EIC_LINE SW0_EIC_LINE -/** @} */ - -/** Number of on-board buttons */ -#define BUTTON_COUNT 1 - -/** \name Extension header #1 pin definitions - * @{ - */ -#define EXT1_PIN_3 PIN_PB05 -#define EXT1_PIN_4 PIN_PA03 -#define EXT1_PIN_5 PIN_PB06 -#define EXT1_PIN_6 PIN_PB07 -#define EXT1_PIN_7 PIN_PA12 -#define EXT1_PIN_8 PIN_PA13 -#define EXT1_PIN_9 PIN_PB04 -#define EXT1_PIN_10 PIN_PA02 -#define EXT1_PIN_11 PIN_PA08 -#define EXT1_PIN_12 PIN_PA09 -#define EXT1_PIN_13 PIN_PB09 -#define EXT1_PIN_14 PIN_PB08 -#define EXT1_PIN_15 PIN_PA05 -#define EXT1_PIN_16 PIN_PA06 -#define EXT1_PIN_17 PIN_PA04 -#define EXT1_PIN_18 PIN_PA07 -/** @} */ - -/** \name Extension header #1 pin definitions by function - * @{ - */ -#define EXT1_PIN_ADC_0 EXT1_PIN_3 -#define EXT1_PIN_ADC_1 EXT1_PIN_4 -#define EXT1_PIN_GPIO_0 EXT1_PIN_5 -#define EXT1_PIN_GPIO_1 EXT1_PIN_6 -#define EXT1_PIN_PWM_0 EXT1_PIN_7 -#define EXT1_PIN_PWM_1 EXT1_PIN_8 -#define EXT1_PIN_IRQ EXT1_PIN_9 -#define EXT1_PIN_I2C_SDA EXT1_PIN_11 -#define EXT1_PIN_I2C_SCL EXT1_PIN_12 -#define EXT1_PIN_UART_RX EXT1_PIN_13 -#define EXT1_PIN_UART_TX EXT1_PIN_14 -#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10 -#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 -#define EXT1_PIN_SPI_MOSI EXT1_PIN_16 -#define EXT1_PIN_SPI_MISO EXT1_PIN_17 -#define EXT1_PIN_SPI_SCK EXT1_PIN_18 -/** @} */ - -/** \name Extension header #1 ADC definitions - * @{ - */ -#define EXT1_ADC_MODULE ADC -#define EXT1_ADC_13_CHANNEL 13 -#define EXT1_ADC_13_PIN PIN_PB05B_ADC_AIN13 -#define EXT1_ADC_13_MUX MUX_PB05B_ADC_AIN13 -#define EXT1_ADC_13_PINMUX PINMUX_PB05B_ADC_AIN13 -#define EXT1_ADC_1_CHANNEL 1 -#define EXT1_ADC_1_PIN PIN_PA03B_ADC_AIN1 -#define EXT1_ADC_1_MUX MUX_PA03B_ADC_AIN1 -#define EXT1_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1 -/** @} */ - -/** \name Extension header #1 PWM definitions - * @{ - */ -#define EXT1_PWM_MODULE TC2 -#define EXT1_PWM_0_CHANNEL 0 -#define EXT1_PWM_0_PIN PIN_PB02E_TC2_WO0 -#define EXT1_PWM_0_MUX MUX_PB02E_TC2_WO0 -#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC2_WO0 -#define EXT1_PWM_1_CHANNEL 1 -#define EXT1_PWM_1_PIN PIN_PB03E_TC2_WO1 -#define EXT1_PWM_1_MUX MUX_PB03E_TC2_WO1 -#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC2_WO1 -/** @} */ - -/** \name Extension header #1 IRQ/External interrupt definitions - * @{ - */ -#define EXT1_IRQ_MODULE EIC -#define EXT1_IRQ_INPUT 4 -#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4 -#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4 -#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4 -/** @} */ - -/** \name Extension header #1 I2C definitions - * @{ - */ -#define EXT1_I2C_MODULE SERCOM2 -#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 -#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 -#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX -#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX -/** @} */ - -/** \name Extension header #1 UART definitions - * @{ - */ -#define EXT1_UART_MODULE SERCOM4 -#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 -#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0 -#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1 -#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED -#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED -#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX -#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX -/** @} */ - -/** \name Extension header #1 SPI definitions - * @{ - */ -#define EXT1_SPI_MODULE SERCOM0 -#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0 -#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1 -#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2 -#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3 -#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX -#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX -/** @} */ - -/** \name Extension header #2 pin definitions - * @{ - */ -#define EXT2_PIN_3 PIN_PA10 -#define EXT2_PIN_4 PIN_PA11 -#define EXT2_PIN_5 PIN_PA20 -#define EXT2_PIN_6 PIN_PA21 -#define EXT2_PIN_7 PIN_PB12 -#define EXT2_PIN_8 PIN_PB13 -#define EXT2_PIN_9 PIN_PB14 -#define EXT2_PIN_10 PIN_PB15 -#define EXT2_PIN_11 PIN_PA08 -#define EXT2_PIN_12 PIN_PA09 -#define EXT2_PIN_13 PIN_PA19 -#define EXT2_PIN_14 PIN_PA18 -#define EXT2_PIN_15 PIN_PA17 -#define EXT2_PIN_16 PIN_PB22 -#define EXT2_PIN_17 PIN_PB16 -#define EXT2_PIN_18 PIN_PB23 -/** @} */ - -/** \name Extension header #2 pin definitions by function - * @{ - */ -#define EXT2_PIN_ADC_0 EXT2_PIN_3 -#define EXT2_PIN_ADC_1 EXT2_PIN_4 -#define EXT2_PIN_GPIO_0 EXT2_PIN_5 -#define EXT2_PIN_GPIO_1 EXT2_PIN_6 -#define EXT2_PIN_PWM_0 EXT2_PIN_7 -#define EXT2_PIN_PWM_1 EXT2_PIN_8 -#define EXT2_PIN_IRQ EXT2_PIN_9 -#define EXT2_PIN_I2C_SDA EXT2_PIN_11 -#define EXT2_PIN_I2C_SCL EXT2_PIN_12 -#define EXT2_PIN_UART_RX EXT2_PIN_13 -#define EXT2_PIN_UART_TX EXT2_PIN_14 -#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10 -#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15 -#define EXT2_PIN_SPI_MOSI EXT2_PIN_16 -#define EXT2_PIN_SPI_MISO EXT2_PIN_17 -#define EXT2_PIN_SPI_SCK EXT2_PIN_18 -/** @} */ - -/** \name Extension header #2 ADC definitions - * @{ - */ -#define EXT2_ADC_MODULE ADC -#define EXT2_ADC_0_CHANNEL 18 -#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18 -#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18 -#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18 -#define EXT2_ADC_1_CHANNEL 19 -#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19 -#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19 -#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19 -/** @} */ - -/** \name Extension header #2 PWM definitions - * @{ - */ -#define EXT2_PWM_MODULE TC0 -#define EXT2_PWM_0_CHANNEL 0 -#define EXT2_PWM_0_PIN PIN_PB12E_TC0_WO0 -#define EXT2_PWM_0_MUX MUX_PB12E_TC0_WO0 -#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC0_WO0 -#define EXT2_PWM_1_CHANNEL 1 -#define EXT2_PWM_1_PIN PIN_PB13E_TC0_WO1 -#define EXT2_PWM_1_MUX MUX_PB13E_TC0_WO1 -#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC0_WO1 -/** @} */ - -/** \name Extension header #2 IRQ/External interrupt definitions - * @{ - */ -#define EXT2_IRQ_MODULE EIC -#define EXT2_IRQ_INPUT 14 -#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14 -#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14 -#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14 -/** @} */ - -/** \name Extension header #2 I2C definitions -* @{ -*/ -#define EXT2_I2C_MODULE SERCOM2 -#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 -#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 -#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX -#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX -/** @} */ - -/** \name Extension header #2 UART definitions - * @{ - */ -#define EXT2_UART_MODULE SERCOM1 -#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 -#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED -#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 -#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 -#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX -#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX -/** @} */ - -/** \name Extension header #2 SPI definitions - * @{ - */ -#define EXT2_SPI_MODULE SERCOM5 -#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 -#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX -#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX -/** @} */ - -/** \name Extension header #3 pin definitions - * @{ - */ -#define EXT3_PIN_3 PIN_PB00 -#define EXT3_PIN_4 PIN_PB01 -#define EXT3_PIN_5 PIN_PB30 -#define EXT3_PIN_6 PIN_PA15 -#define EXT3_PIN_7 PIN_PB10 -#define EXT3_PIN_8 PIN_PB11 -#define EXT3_PIN_9 PIN_PA16 -#define EXT3_PIN_10 PIN_PA27 -#define EXT3_PIN_11 PIN_PA08 -#define EXT3_PIN_12 PIN_PA09 -#define EXT3_PIN_13 PIN_PA19 -#define EXT3_PIN_14 PIN_PA18 -#define EXT3_PIN_15 PIN_PB17 -#define EXT3_PIN_16 PIN_PB22 -#define EXT3_PIN_17 PIN_PB16 -#define EXT3_PIN_18 PIN_PB23 -/** @} */ - -/** \name Extension header #3 pin definitions by function - * @{ - */ -#define EXT3_PIN_ADC_0 EXT3_PIN_3 -#define EXT3_PIN_ADC_1 EXT3_PIN_4 -#define EXT3_PIN_GPIO_0 EXT3_PIN_5 -#define EXT3_PIN_GPIO_1 EXT3_PIN_6 -#define EXT3_PIN_PWM_0 EXT3_PIN_7 -#define EXT3_PIN_PWM_1 EXT3_PIN_8 -#define EXT3_PIN_IRQ EXT3_PIN_9 -#define EXT3_PIN_I2C_SDA EXT3_PIN_11 -#define EXT3_PIN_I2C_SCL EXT3_PIN_12 -#define EXT3_PIN_UART_RX EXT3_PIN_13 -#define EXT3_PIN_UART_TX EXT3_PIN_14 -#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10 -#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15 -#define EXT3_PIN_SPI_MOSI EXT3_PIN_16 -#define EXT3_PIN_SPI_MISO EXT3_PIN_17 -#define EXT3_PIN_SPI_SCK EXT3_PIN_18 -/** @} */ - -/** \name Extension header #3 ADC definitions - * @{ - */ -#define EXT3_ADC_MODULE ADC -#define EXT3_ADC_0_CHANNEL 8 -#define EXT3_ADC_0_PIN PIN_PB00B_ADC_AIN8 -#define EXT3_ADC_0_MUX MUX_PB00B_ADC_AIN8 -#define EXT3_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8 -#define EXT3_ADC_1_CHANNEL 9 -#define EXT3_ADC_1_PIN PIN_PB01B_ADC_AIN9 -#define EXT3_ADC_1_MUX MUX_PB01B_ADC_AIN9 -#define EXT3_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9 -/** @} */ - -/** \name Extension header #3 IRQ/External interrupt definitions - * @{ - */ -#define EXT3_IRQ_MODULE EIC -#define EXT3_IRQ_INPUT 0 -#define EXT3_IRQ_PIN PIN_PA16A_EIC_EXTINT0 -#define EXT3_IRQ_MUX MUX_PA16A_EIC_EXTINT0 -#define EXT3_IRQ_PINMUX PINMUX_PA16A_EIC_EXTINT0 -/** @} */ - -/** \name Extension header #3 I2C definitions - * @{ - */ -#define EXT3_I2C_MODULE SERCOM2 -#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 -#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 -#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX -#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX -/** @} */ - -/** \name Extension header #3 UART definitions - * @{ - */ -#define EXT3_UART_MODULE SERCOM1 -#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 -#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED -#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 -#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 -#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX -#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX - -/** @} */ - -/** \name Extension header #3 SPI definitions - * @{ - */ -#define EXT3_SPI_MODULE SERCOM5 -#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 -#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1 -#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX -#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX -/** @} */ - -/** \name Embedded debugger I2C interface definitions - * @{ - */ -#define EDBG_I2C_MODULE SERCOM2 -#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 -#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 -#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX -#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX -/** @} */ - -/** \name Embedded debugger SPI interface definitions - * @{ - */ -#define EDBG_SPI_MODULE SERCOM5 -#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 -#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1 -#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX -#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX -/** @} */ - -/** \name Embedded debugger CDC Gateway USART interface definitions - * @{ - */ -#define EDBG_CDC_MODULE SERCOM3 -#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 -#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0 -#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1 -#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED -#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED -#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX -#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX -/** @} */ - -/** \name USB definitions - * @{ - */ -#define USB_ID -#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP -#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP -#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP -#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM -#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM -#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM -#define USB_VBUS_PIN PIN_PA14 -#define USB_VBUS_EIC_LINE 14 -#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14 -#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14 -#define USB_ID_PIN PIN_PB02 -#define USB_ID_EIC_LINE 2 -#define USB_ID_EIC_MUX MUX_PB02A_EIC_EXTINT2 -#define USB_ID_EIC_PINMUX PINMUX_PB02A_EIC_EXTINT2 -/** @} */ - -/** \name CCL interface definitions - * @{ - */ -#define CCL_LUT0_IN0_MUX MUX_PA04I_CCL_IN0 -#define CCL_LUT0_IN1_MUX MUX_PA05I_CCL_IN1 -#define CCL_LUT0_IN2_MUX MUX_PA06I_CCL_IN2 -#define CCL_LUT0_OUT_MUX MUX_PA07I_CCL_OUT0 - -#define CCL_LUT0_IN0_PIN PIN_PA04I_CCL_IN0 -#define CCL_LUT0_IN1_PIN PIN_PA05I_CCL_IN1 -#define CCL_LUT0_IN2_PIN PIN_PA06I_CCL_IN2 -#define CCL_LUT0_OUT_PIN PIN_PA07I_CCL_OUT0 - -#define CCL_LUT1_IN0_MUX MUX_PA08I_CCL_IN3 -#define CCL_LUT1_IN1_MUX MUX_PA09I_CCL_IN4 -#define CCL_LUT1_IN2_MUX MUX_PA10I_CCL_IN5 -#define CCL_LUT1_OUT_MUX MUX_PA11I_CCL_OUT1 - -#define CCL_LUT1_IN0_PIN PIN_PA08I_CCL_IN3 -#define CCL_LUT1_IN1_PIN PIN_PA09I_CCL_IN4 -#define CCL_LUT1_IN2_PIN PIN_PA10I_CCL_IN5 -#define CCL_LUT1_OUT_PIN PIN_PA11I_CCL_OUT1 -/** @} */ - -/** - * \brief Turns off the specified LEDs. - * - * \param led_gpio LED to turn off (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true) - -/** - * \brief Turns on the specified LEDs. - * - * \param led_gpio LED to turn on (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false) - -/** - * \brief Toggles the specified LEDs. - * - * \param led_gpio LED to toggle (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio) - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* SAML21_XPLAINED_PRO_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/analogout_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/analogout_api.c deleted file mode 100644 index a548f381c9d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/analogout_api.c +++ /dev/null @@ -1,125 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "dac.h" - -#if DEVICE_ANALOGOUT - -extern uint8_t g_sys_init; - -#define MAX_VAL_12BIT 0x0FFF /*12 Bit DAC for SAML21*/ - -void analogout_init(dac_t *obj, PinName pin) -{ - MBED_ASSERT(obj); - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - struct dac_config config_dac; - struct dac_chan_config config_dac_chan; - uint32_t dacperipheral; - uint32_t ch_index; - - dacperipheral = pinmap_find_peripheral(pin, PinMap_DAC); - MBED_ASSERT(dacperipheral != NC); - obj->pin = pin; - obj->dac = dacperipheral; - if (pin == PA02) { - ch_index = 0; - } else if (pin == PA05) { - ch_index = 1; - } else { /*Only 2 pins for DAC*/ - return 0; - } - obj->channel = ch_index; - - dac_get_config_defaults(&config_dac); - dac_init(&(obj->dac_instance), (Dac *)dacperipheral, &config_dac); - dac_chan_get_config_defaults(&config_dac_chan); - dac_chan_set_config(&(obj->dac_instance), ch_index, &config_dac_chan); - dac_chan_enable(&(obj->dac_instance), ch_index); - dac_enable(&(obj->dac_instance)); -} - -void analogout_free(dac_t *obj) -{ - MBED_ASSERT(obj); - struct system_pinmux_config pin_conf; - - dac_disable(&(obj->dac_instance)); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pin_conf.powersave = false; - pin_conf.mux_position = SYSTEM_PINMUX_GPIO; - system_pinmux_pin_set_config(obj->pin, &pin_conf); -} - -void analogout_write(dac_t *obj, float value) -{ - MBED_ASSERT(obj); - uint16_t count_val = 0; - if (value < 0.0f) { - count_val = 0; - } else if (value > 1.0f) { - count_val = MAX_VAL_12BIT; - } else { - count_val = (uint16_t)(value * (float)MAX_VAL_12BIT); - } - dac_chan_write(&(obj->dac_instance), obj->channel, count_val); - -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - MBED_ASSERT(obj); - uint16_t count_val; - count_val = (uint16_t)((value * (float)MAX_VAL_12BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/ - dac_chan_write(&(obj->dac_instance), obj->channel, count_val); - -} - -static uint32_t data_reg_read(dac_t *obj) -{ - Dac *const dac_module = (Dac *)obj->dac; - return (uint32_t)dac_module->DATA[obj->channel].reg; -} - -float analogout_read(dac_t *obj) -{ - MBED_ASSERT(obj); - uint32_t data_val = data_reg_read(obj); - return data_val/(float)MAX_VAL_12BIT; -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - MBED_ASSERT(obj); - uint32_t data_val = data_reg_read(obj); - return (uint16_t)((data_val / (float)MAX_VAL_12BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/ -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} - -#endif // DEVICE_ANALOGOUT diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device.h deleted file mode 100644 index 2427e752ea9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct deleted file mode 100644 index 099b6029764..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct +++ /dev/null @@ -1,50 +0,0 @@ -#! armcc -E - -;SAMD21J18A -; 256KB FLASH (0x40000) @ 0x000000000 -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; SAMD21J18A: 256KB FLASH (0x40000) -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x40000 -#endif - -; 32KB RAM (0x8000) @ 0x20000000 -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x8000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment -#define VECTOR_SIZE 0xB8 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S deleted file mode 100644 index 562c36aba00..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S +++ /dev/null @@ -1,194 +0,0 @@ -;/**************************************************************************//** -; * @file startup_SAML21.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Atmel SAML21 Device Series -; * @version V1.00 -; * @date 10. February 2015 -; * -; * @note -; * Copyright (C) 2015 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - PRESERVE8 - THUMB - - -;Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ;Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator - DCD WDT_Handler ;1 Watchdog Timer - DCD RTC_Handler ;2 Real-Time Counter - DCD EIC_Handler ;3 External Interrupt Controller - DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller - DCD DMAC_Handler ;5 Direct Memory Access Controller - DCD USB_Handler ;6 Universal Serial Bus - DCD EVSYS_Handler ;7 Event System Interface - DCD SERCOM0_Handler ;8 Serial Communication Interface 0 - DCD SERCOM1_Handler ;9 Serial Communication Interface 1 - DCD SERCOM2_Handler ;10 Serial Communication Interface 2 - DCD SERCOM3_Handler ;11 Serial Communication Interface 3 - DCD SERCOM4_Handler ;12 Serial Communication Interface 4 - DCD SERCOM5_Handler ;13 Serial Communication Interface 5 - DCD TCC0_Handler ;14 Timer Counter Control 0 - DCD TCC1_Handler ;15 Timer Counter Control 1 - DCD TCC2_Handler ;16 Timer Counter Control 2 - DCD TC0_Handler ;17 Basic Timer Counter 0 - DCD TC1_Handler ;18 Basic Timer Counter 1 - DCD TC2_Handler ;19 Basic Timer Counter 2 - DCD TC3_Handler ;20 Basic Timer Counter 3 - DCD TC4_Handler ;21 Basic Timer Counter 4 - DCD ADC_Handler ;22 Analog Digital Converter - DCD AC_Handler ;23 Analog Comparators - DCD DAC_Handler ;24 Digital-to-Analog Converter - DCD PTC_Handler ;25 Peripheral Touch Controller - DCD AES_Handler ;26 Advanced Encryption Standard - DCD TRNG_Handler ;27 True Random Generator - DCD PICOP_Handler ;28 PicoProcessor -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -;Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -;Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT SYSTEM_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC0_Handler [WEAK] - EXPORT TC1_Handler [WEAK] - EXPORT TC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT AES_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - EXPORT PICOP_Handler [WEAK] - -SYSTEM_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC0_Handler -TC1_Handler -TC2_Handler -TC3_Handler -TC4_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -AES_Handler -TRNG_Handler -PICOP_Handler - B . - ENDP - - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/SAML21J18A.sct b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/SAML21J18A.sct deleted file mode 100644 index 7ffda3b72cf..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/SAML21J18A.sct +++ /dev/null @@ -1,27 +0,0 @@ -#! armcc -E - -;SAML21J18A -;256KB FLASH (0x40000) @ 0x000000000 -;32KB RAM (0x8000) @ 0x20000000 - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -;SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) -LR_IROM1 0x00000000 0x40000 { ; load region size_region - ER_IROM1 0x00000000 0x40000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment - RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S deleted file mode 100644 index 562c36aba00..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S +++ /dev/null @@ -1,194 +0,0 @@ -;/**************************************************************************//** -; * @file startup_SAML21.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Atmel SAML21 Device Series -; * @version V1.00 -; * @date 10. February 2015 -; * -; * @note -; * Copyright (C) 2015 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - PRESERVE8 - THUMB - - -;Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ;Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator - DCD WDT_Handler ;1 Watchdog Timer - DCD RTC_Handler ;2 Real-Time Counter - DCD EIC_Handler ;3 External Interrupt Controller - DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller - DCD DMAC_Handler ;5 Direct Memory Access Controller - DCD USB_Handler ;6 Universal Serial Bus - DCD EVSYS_Handler ;7 Event System Interface - DCD SERCOM0_Handler ;8 Serial Communication Interface 0 - DCD SERCOM1_Handler ;9 Serial Communication Interface 1 - DCD SERCOM2_Handler ;10 Serial Communication Interface 2 - DCD SERCOM3_Handler ;11 Serial Communication Interface 3 - DCD SERCOM4_Handler ;12 Serial Communication Interface 4 - DCD SERCOM5_Handler ;13 Serial Communication Interface 5 - DCD TCC0_Handler ;14 Timer Counter Control 0 - DCD TCC1_Handler ;15 Timer Counter Control 1 - DCD TCC2_Handler ;16 Timer Counter Control 2 - DCD TC0_Handler ;17 Basic Timer Counter 0 - DCD TC1_Handler ;18 Basic Timer Counter 1 - DCD TC2_Handler ;19 Basic Timer Counter 2 - DCD TC3_Handler ;20 Basic Timer Counter 3 - DCD TC4_Handler ;21 Basic Timer Counter 4 - DCD ADC_Handler ;22 Analog Digital Converter - DCD AC_Handler ;23 Analog Comparators - DCD DAC_Handler ;24 Digital-to-Analog Converter - DCD PTC_Handler ;25 Peripheral Touch Controller - DCD AES_Handler ;26 Advanced Encryption Standard - DCD TRNG_Handler ;27 True Random Generator - DCD PICOP_Handler ;28 PicoProcessor -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -;Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -;Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT SYSTEM_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC0_Handler [WEAK] - EXPORT TC1_Handler [WEAK] - EXPORT TC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT AES_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - EXPORT PICOP_Handler [WEAK] - -SYSTEM_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC0_Handler -TC1_Handler -TC2_Handler -TC3_Handler -TC4_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -AES_Handler -TRNG_Handler -PICOP_Handler - B . - ENDP - - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/saml21j18a.ld b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/saml21j18a.ld deleted file mode 100644 index 3797cf95d4f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/saml21j18a.ld +++ /dev/null @@ -1,127 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Memory Spaces Definitions */ -MEMORY { - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8 - } - - /* Section Definitions */ - SECTIONS { -.text : - { - . = ALIGN(8); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(8); - KEEP(*(.init)) - . = ALIGN(8); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(8); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(8); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(8); - KEEP(*(.fini)) - - . = ALIGN(8); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(8); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); -.ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(8); - _etext = .; - -.relocate : - AT (_etext) - { - . = ALIGN(8); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(8); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(8); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(8); - _ebss = . ; - _ezero = .; - } > ram - - .heap (NOLOAD) : - { - . = ALIGN(8); - __end__ = . ; - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - - . = ALIGN(8); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/startup_saml21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/startup_saml21.c deleted file mode 100644 index d7e53ee06af..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/startup_saml21.c +++ /dev/null @@ -1,281 +0,0 @@ -/** - * \file - * - * \brief gcc starttup file for SAML21 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "saml21.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */ -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_USB -void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_SERCOM4 -void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_SERCOM5 -void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_TC2 -void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC3 -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_ADC -void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_AC -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_DAC -void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_PTC -void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_AES -void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TRNG -void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_PICOP -void PICOP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (void*) (&_estack), - - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - (void*) WDT_Handler, /* 1 Watchdog Timer */ - (void*) RTC_Handler, /* 2 Real-Time Counter */ - (void*) EIC_Handler, /* 3 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 5 Direct Memory Access Controller */ -#ifdef ID_USB - (void*) USB_Handler, /* 6 Universal Serial Bus */ -#else - (void*) (0UL), /* Reserved */ -#endif - (void*) EVSYS_Handler, /* 7 Event System Interface */ - (void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */ -#ifdef ID_SERCOM4 - (void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ID_SERCOM5 - (void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */ -#else - (void*) (0UL), /* Reserved */ -#endif - (void*) TCC0_Handler, /* 14 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 15 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 16 Timer Counter Control 2 */ - (void*) TC0_Handler, /* 17 Basic Timer Counter 0 */ - (void*) TC1_Handler, /* 18 Basic Timer Counter 1 */ -#ifdef ID_TC2 - (void*) TC2_Handler, /* 19 Basic Timer Counter 2 */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ID_TC3 - (void*) TC3_Handler, /* 20 Basic Timer Counter 3 */ -#else - (void*) (0UL), /* Reserved */ -#endif - (void*) TC4_Handler, /* 21 Basic Timer Counter 4 */ -#ifdef ID_ADC - (void*) ADC_Handler, /* 22 Analog Digital Converter */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ID_AC - (void*) AC_Handler, /* 23 Analog Comparators */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ID_DAC - (void*) DAC_Handler, /* 24 Digital-to-Analog Converter */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ID_PTC - (void*) PTC_Handler, /* 25 Peripheral Touch Controller */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ID_AES - (void*) AES_Handler, /* 26 Advanced Encryption Standard */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ID_TRNG - (void*) TRNG_Handler, /* 27 True Random Generator */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ID_PICOP - (void*) PICOP_Handler /* 28 PicoProcessor */ -#else - (void*) (0UL) /* Reserved */ -#endif -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ - NVMCTRL->CTRLB.bit.MANW = 1; - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_IAR/startup_saml21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_IAR/startup_saml21.c deleted file mode 100644 index 61585962117..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_IAR/startup_saml21.c +++ /dev/null @@ -1,261 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "saml21.h" - -typedef void (*intfunc) (void); -typedef union { - intfunc __fun; - void * __ptr; -} intvec_elem; - -void __iar_program_start(void); -int __low_level_init(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -#pragma weak NMI_Handler = Dummy_Handler -#pragma weak HardFault_Handler = Dummy_Handler -#pragma weak SVC_Handler = Dummy_Handler -#pragma weak PendSV_Handler = Dummy_Handler -#pragma weak SysTick_Handler = Dummy_Handler - -/* Peripherals handlers */ -#pragma weak SYSTEM_Handler = Dummy_Handler /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */ -#pragma weak WDT_Handler = Dummy_Handler -#pragma weak RTC_Handler = Dummy_Handler -#pragma weak EIC_Handler = Dummy_Handler -#pragma weak NVMCTRL_Handler = Dummy_Handler -#pragma weak DMAC_Handler = Dummy_Handler -#ifdef ID_USB -#pragma weak USB_Handler = Dummy_Handler -#endif -#pragma weak EVSYS_Handler = Dummy_Handler -#pragma weak SERCOM0_Handler = Dummy_Handler -#pragma weak SERCOM1_Handler = Dummy_Handler -#pragma weak SERCOM2_Handler = Dummy_Handler -#pragma weak SERCOM3_Handler = Dummy_Handler -#ifdef ID_SERCOM4 -#pragma weak SERCOM4_Handler = Dummy_Handler -#endif -#ifdef ID_SERCOM5 -#pragma weak SERCOM5_Handler = Dummy_Handler -#endif -#pragma weak TCC0_Handler = Dummy_Handler -#pragma weak TCC1_Handler = Dummy_Handler -#pragma weak TCC2_Handler = Dummy_Handler -#pragma weak TC0_Handler = Dummy_Handler -#pragma weak TC1_Handler = Dummy_Handler -#ifdef ID_TC2 -#pragma weak TC2_Handler = Dummy_Handler -#endif -#ifdef ID_TC3 -#pragma weak TC3_Handler = Dummy_Handler -#endif -#pragma weak TC4_Handler = Dummy_Handler -#ifdef ID_ADC -#pragma weak ADC_Handler = Dummy_Handler -#endif -#ifdef ID_AC -#pragma weak AC_Handler = Dummy_Handler -#endif -#ifdef ID_DAC -#pragma weak DAC_Handler = Dummy_Handler -#endif -#ifdef ID_PTC -#pragma weak PTC_Handler = Dummy_Handler -#endif -#ifdef ID_AES -#pragma weak AES_Handler = Dummy_Handler -#endif -#ifdef ID_TRNG -#pragma weak TRNG_Handler = Dummy_Handler -#endif -#ifdef ID_PICOP -#pragma weak PICOP_Handler = Dummy_Handler -#endif - -/* Exception Table */ -#pragma language = extended -#pragma segment = "CSTACK" - -/* The name "__vector_table" has special meaning for C-SPY: */ -/* it is where the SP start value is found, and the NVIC vector */ -/* table register (VTOR) is initialized to this address if != 0 */ - -#pragma section = ".intvec" -#pragma location = ".intvec" -const DeviceVectors __vector_table[] = { - __sfe("CSTACK"), - (void*) __iar_program_start, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - (void*) WDT_Handler, /* 1 Watchdog Timer */ - (void*) RTC_Handler, /* 2 Real-Time Counter */ - (void*) EIC_Handler, /* 3 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 5 Direct Memory Access Controller */ -#ifdef ID_USB - (void*) USB_Handler, /* 6 Universal Serial Bus */ -#else - (void*) (0UL), /* Reserved*/ -#endif - (void*) EVSYS_Handler, /* 7 Event System Interface */ - (void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */ -#ifdef ID_SERCOM4 - (void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_SERCOM5 - (void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */ -#else - (void*) (0UL), /* Reserved*/ -#endif - (void*) TCC0_Handler, /* 14 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 15 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 16 Timer Counter Control 2 */ - (void*) TC0_Handler, /* 17 Basic Timer Counter 0 */ - (void*) TC1_Handler, /* 18 Basic Timer Counter 1 */ -#ifdef ID_TC2 - (void*) TC2_Handler, /* 19 Basic Timer Counter 2 */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_TC3 - (void*) TC3_Handler, /* 20 Basic Timer Counter 3 */ -#else - (void*) (0UL), /* Reserved*/ -#endif - (void*) TC4_Handler, /* 21 Basic Timer Counter 4 */ -#ifdef ID_ADC - (void*) ADC_Handler, /* 22 Analog Digital Converter */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_AC - (void*) AC_Handler, /* 23 Analog Comparators */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_DAC - (void*) DAC_Handler, /* 24 Digital-to-Analog Converter */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_PTC - (void*) PTC_Handler, /* 25 Peripheral Touch Controller */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_AES - (void*) AES_Handler, /* 26 Advanced Encryption Standard */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_TRNG - (void*) TRNG_Handler, /* 27 True Random Generator */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_PICOP - (void*) PICOP_Handler /* 28 PicoProcessor */ -#else - (void*) (0UL) /* Reserved*/ -#endif -}; - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -int __low_level_init(void) -{ - uint32_t *pSrc = __section_begin(".intvec"); - - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - return 1; /* if return 0, the data sections will not be initialized */ -} - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ - NVMCTRL->CTRLB.bit.MANW = 1; - - __iar_program_start(); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis.h deleted file mode 100644 index fb33059b226..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in samr21j18a specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "samr21.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis_nvic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis_nvic.h deleted file mode 100644 index e53c6057f94..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis_nvic.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 28) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralNames.h deleted file mode 100644 index 46dd46a34ca..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralNames.h +++ /dev/null @@ -1,144 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include -#include "cmsis.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define _SERCOM_SPI_NAME(n, unused) \ - SPI##n, - -#define _SERCOM_PAD_NAME(n, pad) \ - SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)), - -#define _SERCOM_I2C_NAME(n, unused) \ - I2C##n, - - - -typedef enum { - UART_0 = (int)0x42000800UL, // Base address of SERCOM0 - UART_1 = (int)0x42000C00UL, // Base address of SERCOM1 - UART_2 = (int)0x42001000UL, // Base address of SERCOM2 - UART_3 = (int)0x42001400UL, // Base address of SERCOM3 - UART_4 = (int)0x42001800UL, // Base address of SERCOM4 - UART_5 = (int)0x42001C00UL // Base address of SERCOM5 -} UARTName; - -typedef enum { // for each input control mux 4,5,6,7,16,17,10,11 used in R21 - ADC_2 = 0x2ul, - ADC_3 = 0x3ul, - ADC_4 = 0x4ul, - ADC_5 = 0x5ul, - ADC_6 = 0x6ul, - ADC_7 = 0x7ul, - ADC_8 = 0x8ul, - ADC_10 = 0xAul, - ADC_11 = 0xBul, - ADC_16 = 0x10ul, - ADC_17 = 0x11ul, - ADC_18 = 0x12ul, - ADC_19 = 0x13ul -} ADCName; - -typedef enum { // for each channel - EXTINT_0 = 0, - EXTINT_1, - EXTINT_2, - EXTINT_3, - EXTINT_4, - EXTINT_5, - EXTINT_6, - EXTINT_7, - EXTINT_8, - EXTINT_9, - EXTINT_10, - EXTINT_11, - EXTINT_12, - EXTINT_13, - EXTINT_14, - EXTINT_15 -} EXTINTName; - -typedef enum { - MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~) -} SPIName; - -typedef enum { - MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~) -} I2CName; - -typedef enum { - /* Pad 0 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0) - - /* Pad 1 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1) - - /* Pad 2 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2) - - /* Pad 3 definitions */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3) -} SercomPadName; - -typedef enum { - PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */ - PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */ - PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */ -} PWMName; - -struct pwm_pin_channel { - PinName pin; - PWMName pwm; - uint8_t channel_index; -}; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -// Default peripherals -#define MBED_SPI0 PB22, PB02, PB23, PA14 - -#define MBED_UART0 PA04, PA05 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 PA16, PA17 - -#define MBED_ANALOGIN0 PA04 -#define MBED_ANALOGIN1 PA05 -#define MBED_ANALOGIN2 PA06 -#define MBED_ANALOGIN3 PA07 -#define MBED_ANALOGIN4 PB02 -#define MBED_ANALOGIN5 PB03 -#define MBED_ANALOGIN7 PA08 -#define MBED_ANALOGIN8 PA09 - -#define MBED_PWMOUT0 PA18 -#define MBED_PWMOUT1 PA19 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c deleted file mode 100644 index bc8fa32ec06..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c +++ /dev/null @@ -1,225 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PB08, ADC_2, 1}, - {PB09, ADC_3, 1}, - {PA04, ADC_4, 1}, - {PA05, ADC_5, 1}, - {PA06, ADC_6, 1}, - {PA07, ADC_7, 1}, - {PB00, ADC_8, 1}, - {PB02, ADC_10, 1}, - {PB03, ADC_11, 1}, - {PA08, ADC_16, 1}, - {PA09, ADC_17, 1}, - {PA10, ADC_18, 1}, - {PA11, ADC_19, 1}, - - /* Not connected */ - {NC , NC , NC} -}; - -/************SERCOM Pins***********/ -const PinMap PinMap_SERCOM_PAD[] = { - {PA00, SERCOM1_PAD0, 3}, - {PA01, SERCOM1_PAD1, 3}, - {PA04, SERCOM0_PAD0, 3}, - {PA05, SERCOM0_PAD1, 3}, - {PA06, SERCOM0_PAD2, 3}, - {PA07, SERCOM0_PAD3, 3}, - {PA08, SERCOM0_PAD0, 2}, - {PA09, SERCOM0_PAD1, 2}, - {PA12, SERCOM2_PAD0, 2}, - {PA13, SERCOM2_PAD1, 2}, - {PA14, SERCOM2_PAD2, 2}, - {PA15, SERCOM2_PAD3, 2}, - {PA16, SERCOM1_PAD0, 2}, - {PA17, SERCOM1_PAD1, 2}, - {PA18, SERCOM1_PAD2, 2}, - {PA19, SERCOM1_PAD3, 2}, - {PA22, SERCOM3_PAD0, 2}, - {PA23, SERCOM3_PAD1, 2}, - {PA24, SERCOM3_PAD2, 2}, - {PA25, SERCOM3_PAD3, 2}, - {PA27, SERCOM3_PAD0, 5}, - {PA28, SERCOM3_PAD1, 5}, - {PA30, SERCOM1_PAD2, 3}, - {PA31, SERCOM1_PAD3, 3}, - {PB02, SERCOM5_PAD0, 3}, - {PB03, SERCOM5_PAD1, 3}, - {PB22, SERCOM5_PAD2, 3}, - {PB23, SERCOM5_PAD3, 3}, - {PB30, SERCOM4_PAD2, 5}, - {PB31, SERCOM4_PAD1, 5}, - {PC18, SERCOM4_PAD3, 5}, - {PC19, SERCOM4_PAD0, 5}, - - /* Not connected */ - {NC , NC , NC} -}; - -/*******SERCOM Pins extended*******/ -const PinMap PinMap_SERCOM_PADEx[] = { - {PA08, SERCOM2_PAD0, 3}, - {PA09, SERCOM2_PAD1, 3}, - {PA16, SERCOM3_PAD0, 3}, - {PA17, SERCOM3_PAD1, 3}, - {PA18, SERCOM3_PAD2, 3}, - {PA19, SERCOM3_PAD3, 3}, - {PA22, SERCOM5_PAD0, 3}, - {PA23, SERCOM5_PAD1, 3}, - {PA24, SERCOM5_PAD2, 3}, - {PA25, SERCOM5_PAD3, 3}, - - /* Not connected */ - {NC , NC , NC} -}; - - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PA00, PWM_2, 4}, - {PA01, PWM_2, 4}, - {PA04, PWM_0, 4}, - {PA05, PWM_0, 4}, - {PA06, PWM_1, 4}, - {PA07, PWM_1, 4}, - {PA08, PWM_0, 4}, - {PA09, PWM_0, 4}, - {PA10, PWM_1, 4}, - {PA11, PWM_1, 4}, - {PA12, PWM_2, 4}, - {PA13, PWM_2, 4}, - {PA16, PWM_2, 4}, - {PA17, PWM_2, 4}, - {PA18, PWM_0, 5}, - {PA19, PWM_0, 5}, - {PA20, PWM_0, 5}, - {PA22, PWM_0, 5}, - {PA23, PWM_0, 5}, - {PA24, PWM_1, 5}, - {PA25, PWM_1, 5}, - {PA30, PWM_1, 4}, - {PA31, PWM_1, 4}, - {PB16, PWM_0, 5}, - {PB17, PWM_0, 5}, - {PB30, PWM_0, 4}, - {PB31, PWM_0, 4}, - - /* Not connected */ - {NC , NC , NC} -}; - -/**********EXTINT*************/ -const PinMap PinMap_EXTINT[] = { - {PA16, EXTINT_0, 0}, - {PB00, EXTINT_0, 0}, - {PB16, EXTINT_0, 0}, - {PA00, EXTINT_0, 0}, - - {PA17, EXTINT_1, 0}, - {PB17, EXTINT_1, 0}, - {PA01, EXTINT_1, 0}, - - {PA18, EXTINT_2, 0}, - {PB02, EXTINT_2, 0}, - - {PA19, EXTINT_3, 0}, - {PB03, EXTINT_3, 0}, - - {PA04, EXTINT_4, 0}, - {PA20, EXTINT_4, 0}, - - {PA05, EXTINT_5, 0}, - - {PA06, EXTINT_6, 0}, - {PA22, EXTINT_6, 0}, - {PB22, EXTINT_6, 0}, - - {PA07, EXTINT_7, 0}, - {PA23, EXTINT_7, 0}, - {PB23, EXTINT_7, 0}, - - {PA28, EXTINT_8, 0}, - {PB08, EXTINT_8, 0}, - - {PA09, EXTINT_9, 0}, - {PB09, EXTINT_9, 0}, - - {PA30, EXTINT_10, 0}, - {PA10, EXTINT_10, 0}, - - {PA31, EXTINT_11, 0}, - {PA11, EXTINT_11, 0}, - - {PA12, EXTINT_12, 0}, - {PA24, EXTINT_12, 0}, - - {PA13, EXTINT_13, 0}, - {PA25, EXTINT_13, 0}, - - {PB14, EXTINT_14, 0}, - {PB30, EXTINT_14, 0}, - {PA14, EXTINT_14, 0}, - - {PA15, EXTINT_15, 0}, - {PA27, EXTINT_15, 0}, - {PB15, EXTINT_15, 0}, - {PB31, EXTINT_15, 0}, - - /* Not connected */ - {NC , NC , NC} -}; - -const struct pwm_pin_channel pwn_pins[] = { - {PA00, PWM_2, 0}, - {PA01, PWM_2, 1}, - {PA04, PWM_0, 0}, - {PA05, PWM_0, 1}, - {PA06, PWM_1, 0}, - {PA07, PWM_1, 1}, - {PA08, PWM_0, 0}, - {PA09, PWM_0, 1}, - {PA10, PWM_1, 0}, - {PA11, PWM_1, 1}, - {PA12, PWM_2, 0}, - {PA13, PWM_2, 1}, - {PA16, PWM_2, 0}, - {PA17, PWM_2, 1}, - {PA18, PWM_0, 2}, - {PA19, PWM_0, 3}, - {PA20, PWM_0, 6}, - {PA22, PWM_0, 4}, - {PA23, PWM_0, 5}, - {PA24, PWM_1, 2}, - {PA25, PWM_1, 3}, - {PA30, PWM_1, 0}, - {PA31, PWM_1, 1}, - {PB16, PWM_0, 4}, - {PB17, PWM_0, 5}, - {PB30, PWM_0, 0}, - {PB31, PWM_0, 1}, - - /* Not connected */ - {(PinName) NC ,(PWMName) NC ,(uint8_t) NC} -}; - - - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.h deleted file mode 100644 index edc62995d75..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -//*********SERCOM*************/ -extern const PinMap PinMap_SERCOM_PAD[]; -extern const PinMap PinMap_SERCOM_PADEx[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -/**********EXTINT*************/ -extern const PinMap PinMap_EXTINT[]; - - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PinNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PinNames.h deleted file mode 100644 index d4aa73f78e4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PinNames.h +++ /dev/null @@ -1,101 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INPUT_OUTPUT //pin state can be set and read back -} PinDirection; - -typedef enum { - PA00 = 0, - PA01 = 1, - PA04 = 4, - PA05 = 5, - PA06 = 6, - PA07 = 7, - PA08 = 8, - PA09 = 9, - PA10 = 10, - PA11 = 11, - PA12 = 12, - PA13 = 13, - PA14 = 14, - PA15 = 15, - PA16 = 16, - PA17 = 17, - PA18 = 18, - PA19 = 19, - PA20 = 20, - PA22 = 22, - PA23 = 23, - PA24 = 24, - PA25 = 25, - PA27 = 27, - PA28 = 28, - PA30 = 30, - PA31 = 31, - - PB00 = 32, - PB02 = 34, - PB03 = 35, - PB08 = 40, - PB09 = 41, - PB14 = 46, - PB15 = 47, - PB16 = 48, - PB17 = 49, - PB22 = 54, - PB23 = 55, - PB30 = 62, - PB31 = 63, - - PC16 = 80, - PC18 = 82, - PC19 = 83, - - USBTX = PA04, - USBRX = PA05, - - LED1 = PA19, - LED2 = PA19, - LED3 = PA19, - LED4 = PA19, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c deleted file mode 100644 index 3864ccd6b0f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "compiler.h" -#include "system.h" - - -uint8_t g_sys_init = 0; - -//called before main - implement here if board needs it ortherwise, let -// the application override this if necessary -//TODO: To be implemented by adding system init and board init -void mbed_sdk_init() -{ - if(g_sys_init == 0) { - g_sys_init = 1; - system_init(); - } -} -/***************************************************************/ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h deleted file mode 100644 index 2286e2bf10d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h +++ /dev/null @@ -1,475 +0,0 @@ -#ifndef SAMR21_XPLAINED_PRO_H_INCLUDED -#define SAMR21_XPLAINED_PRO_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup group_common_boards - * \defgroup samr21_xplained_pro_group SAM R21 Xplained Pro board - * - * @{ - */ - -void system_board_init(void); - -/** - * \defgroup samr21_xplained_pro_features_group Features - * - * Symbols that describe features and capabilities of the board. - * - * @{ - */ - -/** Name string macro */ -#define BOARD_NAME "SAMR21_XPLAINED_PRO" - -/** \name Resonator definitions - * @{ */ -#define BOARD_FREQ_SLCK_XTAL (32768U) -#define BOARD_FREQ_SLCK_BYPASS (32768U) -#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */ -#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */ -#define BOARD_MCK CHIP_FREQ_CPU_MAX -#define BOARD_OSC_STARTUP_US 15625 -/** @} */ - -/** \name LED0 definitions - * @{ */ -#define LED0_PIN PIN_PA19 -#define LED0_ACTIVE false -#define LED0_INACTIVE !LED0_ACTIVE -#define LED0 LED0_PIN -/** @} */ - -/** \name SW0 definitions - * @{ */ -#define SW0_PIN PIN_PA28 -#define SW0_ACTIVE false -#define SW0_INACTIVE !SW0_ACTIVE -#define SW0_EIC_PIN PIN_PA28A_EIC_EXTINT8 -#define SW0_EIC_MUX MUX_PA28A_EIC_EXTINT8 -#define SW0_EIC_PINMUX PINMUX_PA28A_EIC_EXTINT8 -#define SW0_EIC_LINE 8 -/** @} */ - -/** - * \name LED #0 definitions - * - * Wrapper macros for LED0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define LED_0_NAME "LED0 (yellow)" -#define LED_0_PIN LED0_PIN -#define LED_0_ACTIVE LED0_ACTIVE -#define LED_0_INACTIVE LED0_INACTIVE -#define LED0_GPIO LED0_PIN - -#define LED_0_PWM_MODULE TC3 -#define LED_0_PWM_CHANNEL 1 -#define LED_0_PWM_OUTPUT 1 -#define LED_0_PWM_PIN PIN_PA19E_TC3_WO1 -#define LED_0_PWM_MUX MUX_PA19E_TC3_WO1 -#define LED_0_PWM_PINMUX PINMUX_PA19E_TC3_WO1 - -#define LED_0_PWM4CTRL_MODULE TCC0 -#define LED_0_PWM4CTRL_CHANNEL 3 -#define LED_0_PWM4CTRL_OUTPUT 3 -#define LED_0_PWM4CTRL_PIN PIN_PA19F_TCC0_WO3 -#define LED_0_PWM4CTRL_MUX MUX_PA19F_TCC0_WO3 -#define LED_0_PWM4CTRL_PINMUX PINMUX_PA19F_TCC0_WO3 -/** @} */ - -/** Number of on-board LEDs */ -#define LED_COUNT 1 - - -/** - * \name Button #0 definitions - * - * Wrapper macros for SW0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define BUTTON_0_NAME "SW0" -#define BUTTON_0_PIN SW0_PIN -#define BUTTON_0_ACTIVE SW0_ACTIVE -#define BUTTON_0_INACTIVE SW0_INACTIVE -#define BUTTON_0_EIC_PIN SW0_EIC_PIN -#define BUTTON_0_EIC_MUX SW0_EIC_MUX -#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX -#define BUTTON_0_EIC_LINE SW0_EIC_LINE -/** @} */ - -/** Number of on-board buttons */ -#define BUTTON_COUNT 1 - -/** \name Extension header #1 pin definitions - * @{ - */ -#define EXT1_PIN_3 PIN_PA06 -#define EXT1_PIN_4 PIN_PA07 -#define EXT1_PIN_5 PIN_PA13 -#define EXT1_PIN_6 PIN_PA28 -#define EXT1_PIN_7 PIN_PA18 -#define EXT1_PIN_8 PIN_PA19 -#define EXT1_PIN_9 PIN_PA22 -#define EXT1_PIN_10 PIN_PA23 -#define EXT1_PIN_11 PIN_PA16 -#define EXT1_PIN_12 PIN_PA17 -#define EXT1_PIN_13 PIN_PA05 -#define EXT1_PIN_14 PIN_PA04 -#define EXT1_PIN_15 PIN_PB03 -#define EXT1_PIN_16 PIN_PB22 -#define EXT1_PIN_17 PIN_PB02 -#define EXT1_PIN_18 PIN_PB23 -/** @} */ - -/** \name Extension header #1 pin definitions by function - * @{ - */ -#define EXT1_PIN_ADC_0 EXT1_PIN_3 -#define EXT1_PIN_ADC_1 EXT1_PIN_4 -#define EXT1_PIN_GPIO_0 EXT1_PIN_5 -#define EXT1_PIN_GPIO_1 EXT1_PIN_6 -#define EXT1_PIN_PWM_0 EXT1_PIN_7 -#define EXT1_PIN_PWM_1 EXT1_PIN_8 -#define EXT1_PIN_GPIO_3 EXT1_PIN_9 -#define EXT1_PIN_GPIO_4 EXT1_PIN_10 -#define EXT1_PIN_I2C_SDA EXT1_PIN_11 -#define EXT1_PIN_I2C_SCL EXT1_PIN_12 -#define EXT1_PIN_UART_RX EXT1_PIN_13 -#define EXT1_PIN_UART_TX EXT1_PIN_14 -#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 -#define EXT1_PIN_SPI_MOSI EXT1_PIN_16 -#define EXT1_PIN_SPI_MISO EXT1_PIN_17 -#define EXT1_PIN_SPI_SCK EXT1_PIN_18 -/** @} */ - -/** \name Extension header #1 ADC definitions - * @{ - */ -#define EXT1_ADC_MODULE ADC -#define EXT1_ADC_0_CHANNEL 6 -#define EXT1_ADC_0_PIN PIN_PA06B_ADC_AIN6 -#define EXT1_ADC_0_MUX MUX_PA06B_ADC_AIN6 -#define EXT1_ADC_0_PINMUX PINMUX_PA06B_ADC_AIN6 -#define EXT1_ADC_1_CHANNEL 7 -#define EXT1_ADC_1_PIN PIN_PA07B_ADC_AIN7 -#define EXT1_ADC_1_MUX MUX_PA07B_ADC_AIN7 -#define EXT1_ADC_1_PINMUX PINMUX_PA07B_ADC_AIN7 -/** @} */ - -/** \name Extension header #1 PWM definitions - * @{ - */ -#define EXT1_PWM_MODULE TC3 -#define EXT1_PWM_0_CHANNEL 0 -#define EXT1_PWM_0_PIN PIN_PA18E_TC3_WO0 -#define EXT1_PWM_0_MUX MUX_PA18E_TC3_WO0 -#define EXT1_PWM_0_PINMUX PINMUX_PA18E_TC3_WO0 -#define EXT1_PWM_1_CHANNEL 1 -#define EXT1_PWM_1_PIN PIN_PA19E_TC3_WO1 -#define EXT1_PWM_1_MUX MUX_PA19E_TC3_WO1 -#define EXT1_PWM_1_PINMUX PINMUX_PA19E_TC3_WO1 -/** @} */ - -/** \name Extension header #1 PWM for Control definitions - * @{ - */ -#define EXT1_PWM4CTRL_MODULE TCC0 -#define EXT1_PWM4CTRL_0_CHANNEL 2 -#define EXT1_PWM4CTRL_0_OUTPUT 2 -#define EXT1_PWM4CTRL_0_PIN PIN_PA18F_TCC0_WO2 -#define EXT1_PWM4CTRL_0_MUX MUX_PA18F_TCC0_WO2 -#define EXT1_PWM4CTRL_0_PINMUX PINMUX_PA18F_TCC0_WO2 -#define EXT1_PWM4CTRL_1_CHANNEL 3 -#define EXT1_PWM4CTRL_1_OUTPUT 3 -#define EXT1_PWM4CTRL_1_PIN PIN_PA19F_TCC0_WO3 -#define EXT1_PWM4CTRL_1_MUX MUX_PA19F_TCC0_WO3 -#define EXT1_PWM4CTRL_1_PINMUX PINMUX_PA19F_TCC0_WO3 -/** @} */ - -/** \name Extension header #1 IRQ/External interrupt definitions - * @{ - */ -#define EXT1_IRQ_MODULE EIC -#define EXT1_IRQ_INPUT 6 -#define EXT1_IRQ_PIN PIN_PA22A_EIC_EXTINT6 -#define EXT1_IRQ_MUX MUX_PA22A_EIC_EXTINT6 -#define EXT1_IRQ_PINMUX PINMUX_PA22A_EIC_EXTINT6 -/** @} */ - -/** \name Extension header #1 I2C definitions - * @{ - */ -#define EXT1_I2C_MODULE SERCOM1 -#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 -#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1 -#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX -#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX -/** @} */ - -/** \name Extension header #1 UART definitions - * @{ - */ -#define EXT1_UART_MODULE SERCOM0 -#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 -#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0 -#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1 -#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED -#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED -#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX -#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX -/** @} */ - -/** \name Extension header #1 SPI definitions - * @{ - */ -#define EXT1_SPI_MODULE SERCOM5 -#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0 -#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB03D_SERCOM5_PAD1 -#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX -#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX -/** @} */ - -/** \name Extension header #3 pin definitions - * @{ - */ -#define EXT3_PIN_5 PIN_PA15 -#define EXT3_PIN_10 PIN_PA08 -#define EXT3_PIN_11 PIN_PA16 -#define EXT3_PIN_12 PIN_PA17 -#define EXT3_PIN_15 PIN_PA14 -#define EXT3_PIN_16 PIN_PB22 -#define EXT3_PIN_17 PIN_PB02 -#define EXT3_PIN_18 PIN_PB23 -/** @} */ - -/** \name Extension header #3 pin definitions by function - * @{ - */ -#define EXT3_PIN_GPIO_0 EXT3_PIN_5 -#define EXT3_PIN_GPIO_1 EXT3_PIN_10 -#define EXT3_PIN_I2C_SDA EXT3_PIN_11 -#define EXT3_PIN_I2C_SCL EXT3_PIN_12 -#define EXT3_PIN_GPIO_2 EXT3_PIN_15 -#define EXT3_PIN_SPI_MOSI EXT3_PIN_16 -#define EXT3_PIN_SPI_MISO EXT3_PIN_17 -#define EXT3_PIN_SPI_SCK EXT3_PIN_18 -/** @} */ - -/** \name Extension header #3 SPI definitions - * @{ - */ -#define EXT3_SPI_SLAVE_SELECT_PIN PIN_PA14 -#define EXT3_SPI_MODULE SERCOM5 -#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0 -#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX -#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX -/** @} */ - -/** \name Extension header #3 Dataflash - * @{ - */ -#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE -#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING -#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2 -#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3 -/** @} */ - -/** \name USB definitions - * @{ - */ -#define USB_ID -#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP -#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP -#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP -#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM -#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM -#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM -#define USB_VBUS_PIN PIN_PA07 -#define USB_VBUS_EIC_LINE 7 -#define USB_VBUS_EIC_MUX MUX_PA07A_EIC_EXTINT7 -#define USB_VBUS_EIC_PINMUX PINMUX_PA07A_EIC_EXTINT7 -/* USB ID pin is not connected */ -//#define USB_ID_PIN -1 -//#define USB_ID_EIC_LINE -1 -//#define USB_ID_EIC_MUX -1 -//#define USB_ID_EIC_PINMUX -1 -/** @} */ - -/** \name Embedded debugger GPIO interface definitions - * @{ - */ -#define EDBG_GPIO0_PIN PIN_PA08 -#define EDBG_GPIO1_PIN PIN_PA09 -#define EDBG_GPIO2_PIN PIN_PA12 -#define EDBG_GPIO3_PIN PIN_PA14 -/** @} */ - -/** \name Embedded debugger USART interface definitions - * @{ - */ -#define EDBG_UART_MODULE -1 /* Not available on this board */ -#define EDBG_UART_RX_PIN -1 /* Not available on this board */ -#define EDBG_UART_RX_MUX -1 /* Not available on this board */ -#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */ -#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */ -#define EDBG_UART_TX_PIN -1 /* Not available on this board */ -#define EDBG_UART_TX_MUX -1 /* Not available on this board */ -#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */ -#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */ -/** @} */ - -/** \name Embedded debugger I2C interface definitions - * @{ - */ -#define EDBG_I2C_MODULE SERCOM1 -#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 -#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1 -#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX -#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX -/** @} */ - -/** \name Embedded debugger SPI interface definitions - * @{ - */ -#define EDBG_SPI_SLAVE_SELECT_PIN PIN_PA27 -#define EDBG_SPI_MODULE SERCOM5 -#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0 -#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 -#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 -#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX -#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX -/** @} */ - -/** \name Embedded debugger CDC Gateway USART interface definitions - * @{ - */ -#define EDBG_CDC_MODULE SERCOM0 -#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 -#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0 -#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1 -#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED -#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED -#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX -#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX -/** @} */ - -#define RF_SPI_MODULE SERCOM4 -#define RF_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E -#define RF_SPI_SERCOM_PINMUX_PAD0 PINMUX_PC19F_SERCOM4_PAD0 -#define RF_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1 -#define RF_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB30F_SERCOM4_PAD2 -#define RF_SPI_SERCOM_PINMUX_PAD3 PINMUX_PC18F_SERCOM4_PAD3 - - -#define RF_IRQ_MODULE EIC -#define RF_IRQ_INPUT 0 -#define RF_IRQ_PIN PIN_PB00A_EIC_EXTINT0 -#define RF_IRQ_MUX MUX_PB00A_EIC_EXTINT0 -#define RF_IRQ_PINMUX PINMUX_PB00A_EIC_EXTINT0 - -/** \name 802.15.4 TRX Interface definitions - * @{ - */ - -#define AT86RFX_SPI SERCOM4 -#define AT86RFX_RST_PIN PIN_PB15 -#define AT86RFX_IRQ_PIN PIN_PB00 -#define AT86RFX_SLP_PIN PIN_PA20 -#define AT86RFX_SPI_CS PIN_PB31 -#define AT86RFX_SPI_MOSI PIN_PB30 -#define AT86RFX_SPI_MISO PIN_PC19 -#define AT86RFX_SPI_SCK PIN_PC18 -#define PIN_RFCTRL1 PIN_PA09 -#define PIN_RFCTRL2 PIN_PA12 -#define RFCTRL_CFG_ANT_DIV 4 - - -#define AT86RFX_SPI_SERCOM_MUX_SETTING RF_SPI_SERCOM_MUX_SETTING -#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 RF_SPI_SERCOM_PINMUX_PAD0 -#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED -#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 RF_SPI_SERCOM_PINMUX_PAD2 -#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 RF_SPI_SERCOM_PINMUX_PAD3 - -#define AT86RFX_IRQ_CHAN RF_IRQ_INPUT -#define AT86RFX_IRQ_PINMUX RF_IRQ_PINMUX - - -/** Enables the transceiver main interrupt. */ -#define ENABLE_TRX_IRQ() \ - extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT) - -/** Disables the transceiver main interrupt. */ -#define DISABLE_TRX_IRQ() \ - extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT) - -/** Clears the transceiver main interrupt. */ -#define CLEAR_TRX_IRQ() \ - extint_chan_clear_detected(AT86RFX_IRQ_CHAN); - -/* - * This macro saves the trx interrupt status and disables the trx interrupt. - */ -#define ENTER_TRX_REGION() \ - { extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT) - -/* - * This macro restores the transceiver interrupt status - */ -#define LEAVE_TRX_REGION() \ - extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); } - -/** @} */ -/** - * \brief Turns off the specified LEDs. - * - * \param led_gpio LED to turn off (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true) - -/** - * \brief Turns on the specified LEDs. - * - * \param led_gpio LED to turn on (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false) - -/** - * \brief Toggles the specified LEDs. - * - * \param led_gpio LED to toggle (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio) - - - -#ifdef __cplusplus -} -#endif - -#endif /* SAMR21_XPLAINED_PRO_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device.h deleted file mode 100644 index 3b470c68647..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct deleted file mode 100644 index c2916a08168..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct +++ /dev/null @@ -1,50 +0,0 @@ -#! armcc -E - -;SAMR21G18A -; 256KB FLASH (0x40000) @ 0x000000000 -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; SAMR21G18A: 256KB FLASH (0x40000) -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x40000 -#endif - -; 32KB RAM (0x8000) @ 0x20000000 -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x8000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment -#define VECTOR_SIZE 0xB0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S deleted file mode 100644 index 760ede74a8e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S +++ /dev/null @@ -1,189 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMR21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMR21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/SAMR21G18A.sct b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/SAMR21G18A.sct deleted file mode 100644 index b3b1c653dea..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/SAMR21G18A.sct +++ /dev/null @@ -1,27 +0,0 @@ -#! armcc -E - -;SAMR21G18A -;256KB FLASH (0x40000) @ 0x000000000 -;2KB RAM (0x8000) @ 0x20000000 - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) -LR_IROM1 0x00000000 0x40000 { ; load region size_region - ER_IROM1 0x00000000 0x40000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment - RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down - } -} \ No newline at end of file diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S deleted file mode 100644 index 760ede74a8e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S +++ /dev/null @@ -1,189 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMR21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMR21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/samr21g18a.ld b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/samr21g18a.ld deleted file mode 100644 index 9c04e8d1bcb..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/samr21g18a.ld +++ /dev/null @@ -1,127 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Memory Spaces Definitions */ -MEMORY { - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000 + 0xB0, LENGTH = 0x00008000 - 0xB0 - } - - /* Section Definitions */ - SECTIONS { -.text : - { - . = ALIGN(8); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(8); - KEEP(*(.init)) - . = ALIGN(8); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(8); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(8); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(8); - KEEP(*(.fini)) - - . = ALIGN(8); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(8); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); -.ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(8); - _etext = .; - -.relocate : - AT (_etext) - { - . = ALIGN(8); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(8); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(8); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(8); - _ebss = . ; - _ezero = .; - } > ram - - .heap (NOLOAD) : - { - . = ALIGN(8); - __end__ = . ; - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - - . = ALIGN(8); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/startup_samr21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/startup_samr21.c deleted file mode 100644 index a0361f3c5d4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/startup_samr21.c +++ /dev/null @@ -1,212 +0,0 @@ -#include "samr21.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef USB_IRQn -void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef SERCOM4_IRQn -void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef SERCOM5_IRQn -void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef TC6_IRQn -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef TC7_IRQn -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ADC_IRQn -void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef AC_IRQn -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef DAC_IRQn -void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef PTC_IRQn -void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (void*) (&_estack), - - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ -#ifdef USB_IRQn - (void*) USB_Handler, /* 7 Universal Serial Bus */ -#else - (void*) (0UL), /* Reserved */ -#endif - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ -#ifdef SERCOM4_IRQn - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef SERCOM5_IRQn - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ -#else - (void*) (0UL), /* Reserved */ -#endif - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ -#ifdef TC6_IRQn - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef TC7_IRQn - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef ADC_IRQn - (void*) ADC_Handler, /* 23 Analog Digital Converter */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef AC_IRQn - (void*) AC_Handler, /* 24 Analog Comparators */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef DAC_IRQn - (void*) DAC_Handler, /* 25 Digital Analog Converter */ -#else - (void*) (0UL), /* Reserved */ -#endif -#ifdef PTC_IRQn - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ -#else - (void*) (0UL), /* Reserved */ -#endif - (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_IAR/startup_samr21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_IAR/startup_samr21.c deleted file mode 100644 index 8fab8a8ea98..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_IAR/startup_samr21.c +++ /dev/null @@ -1,249 +0,0 @@ -/** - * \file - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "samr21.h" - -typedef void (*intfunc) (void); -typedef union { - intfunc __fun; - void * __ptr; -} intvec_elem; - -void __iar_program_start(void); -int __low_level_init(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -#pragma weak NMI_Handler = Dummy_Handler -#pragma weak HardFault_Handler = Dummy_Handler -#pragma weak SVC_Handler = Dummy_Handler -#pragma weak PendSV_Handler = Dummy_Handler -#pragma weak SysTick_Handler = Dummy_Handler - -/* Peripherals handlers */ -#pragma weak PM_Handler = Dummy_Handler -#pragma weak SYSCTRL_Handler = Dummy_Handler -#pragma weak WDT_Handler = Dummy_Handler -#pragma weak RTC_Handler = Dummy_Handler -#pragma weak EIC_Handler = Dummy_Handler -#pragma weak NVMCTRL_Handler = Dummy_Handler -#pragma weak DMAC_Handler = Dummy_Handler -#ifdef ID_USB -#pragma weak USB_Handler = Dummy_Handler -#endif -#pragma weak EVSYS_Handler = Dummy_Handler -#pragma weak SERCOM0_Handler = Dummy_Handler -#pragma weak SERCOM1_Handler = Dummy_Handler -#pragma weak SERCOM2_Handler = Dummy_Handler -#pragma weak SERCOM3_Handler = Dummy_Handler -#ifdef ID_SERCOM4 -#pragma weak SERCOM4_Handler = Dummy_Handler -#endif -#ifdef ID_SERCOM5 -#pragma weak SERCOM5_Handler = Dummy_Handler -#endif -#pragma weak TCC0_Handler = Dummy_Handler -#pragma weak TCC1_Handler = Dummy_Handler -#pragma weak TCC2_Handler = Dummy_Handler -#pragma weak TC3_Handler = Dummy_Handler -#pragma weak TC4_Handler = Dummy_Handler -#pragma weak TC5_Handler = Dummy_Handler -#ifdef ID_TC6 -#pragma weak TC6_Handler = Dummy_Handler -#endif -#ifdef ID_TC7 -#pragma weak TC7_Handler = Dummy_Handler -#endif -#ifdef ID_ADC -#pragma weak ADC_Handler = Dummy_Handler -#endif -#ifdef ID_AC -#pragma weak AC_Handler = Dummy_Handler -#endif -#ifdef ID_DAC -#pragma weak DAC_Handler = Dummy_Handler -#endif -#ifdef ID_PTC -#pragma weak PTC_Handler = Dummy_Handler -#endif -#pragma weak I2S_Handler = Dummy_Handler - -/* Exception Table */ -#pragma language = extended -#pragma segment = "CSTACK" - -/* The name "__vector_table" has special meaning for C-SPY: */ -/* it is where the SP start value is found, and the NVIC vector */ -/* table register (VTOR) is initialized to this address if != 0 */ - -#pragma section = ".intvec" -#pragma location = ".intvec" -const DeviceVectors __vector_table[] = { - __sfe("CSTACK"), - (void*) __iar_program_start, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ -#ifdef ID_USB - (void*) USB_Handler, /* 7 Universal Serial Bus */ -#else - (void*) (0UL), /* Reserved*/ -#endif - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ -#ifdef ID_SERCOM4 - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_SERCOM5 - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ -#else - (void*) (0UL), /* Reserved*/ -#endif - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ -#ifdef ID_TC6 - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_TC7 - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_ADC - (void*) ADC_Handler, /* 23 Analog Digital Converter */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_AC - (void*) AC_Handler, /* 24 Analog Comparators */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_DAC - (void*) DAC_Handler, /* 25 Digital Analog Converter */ -#else - (void*) (0UL), /* Reserved*/ -#endif -#ifdef ID_PTC - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ -#else - (void*) (0UL), /* Reserved*/ -#endif - (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */ - (void*) (0UL), /* Reserved */ -}; - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -int __low_level_init(void) -{ - uint32_t *pSrc = __section_begin(".intvec"); - - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - return 1; /* if return 0, the data sections will not be initialized */ -} - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - /* Change default QOS values to have the best performance and correct USB behaviour */ - SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; -#if defined(ID_USB) - USB->DEVICE.QOSCTRL.bit.CQOS = 2; - USB->DEVICE.QOSCTRL.bit.DQOS = 2; -#endif - DMAC->QOSCTRL.bit.DQOS = 2; - DMAC->QOSCTRL.bit.FQOS = 2; - DMAC->QOSCTRL.bit.WRBQOS = 2; - - /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ - NVMCTRL->CTRLB.bit.MANW = 1; - - __iar_program_start(); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/analogin_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/analogin_api.c deleted file mode 100644 index 46dbe082402..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/analogin_api.c +++ /dev/null @@ -1,231 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "adc.h" -#include "status_codes.h" - -extern uint8_t g_sys_init; -struct adc_module adc_instance; - -void adc_configure_ain_pin(uint32_t pin) -{ -#define PIN_INVALID_ADC_AIN 0xFFFFUL - - /* Pinmapping table for AINxx -> GPIO pin number */ - const uint32_t pinmapping[] = { -#if (SAMD20E | SAMD21E) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD20G | SAMD21G) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD20J | SAMD21J) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, - PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif SAMR21E - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif SAMR21G - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_PB00B_ADC_AIN8, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD10C | SAMD11C) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10DS | SAMD11DS) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10DM | SAMD11DM) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAML21E) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAML21G) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAML21J) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, - PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#else -# error ADC pin mappings are not defined for this device. -#endif - }; - - uint32_t pin_map_result = PIN_INVALID_ADC_AIN; - - if (pin <= ADC_EXTCHANNEL_MSB) { - pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; - - Assert(pin_map_result != PIN_INVALID_ADC_AIN); - - struct system_pinmux_config config; - system_pinmux_get_config_defaults(&config); - - /* Analog functions are all on MUX setting B */ - config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - config.mux_position = 1; - - system_pinmux_pin_set_config(pin_map_result, &config); - } -} - -void analogin_init(analogin_t *obj, PinName pin) -{ - MBED_ASSERT(obj); - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - uint32_t pos_input; - static uint8_t init_flag = 0; - - pos_input = pinmap_find_peripheral(pin, PinMap_ADC); - MBED_ASSERT(pos_input != (uint32_t)NC); - - adc_get_config_defaults(&(obj->config_adc)); - obj->config_adc.positive_input = (enum adc_positive_input)pos_input; - if (init_flag == 0) { // ADC init and enable to be done only once. - adc_init(&adc_instance, ADC, &(obj->config_adc)); - adc_enable(&adc_instance); - init_flag = 1; - } - adc_configure_ain_pin(obj->config_adc.positive_input); - adc_configure_ain_pin(obj->config_adc.negative_input); -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - MBED_ASSERT(obj); - uint16_t result; - adc_set_positive_input(&adc_instance, obj->config_adc.positive_input); - adc_set_negative_input(&adc_instance, obj->config_adc.negative_input); - adc_start_conversion(&adc_instance); - do { - } while(adc_read(&(adc_instance), &result) == STATUS_BUSY); // 12 bit value - - return (uint16_t)(((uint32_t)result * 0xFFFF) / 0x0FFF); // for normalizing to 16 bit value -} - -float analogin_read(analogin_t *obj) -{ - MBED_ASSERT(obj); - uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)0xFFFF); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_board.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_board.h deleted file mode 100644 index be06f54b719..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_board.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * \file - * - * \brief SAM D21 Xplained Pro board configuration. - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H_INCLUDED -#define CONF_BOARD_H_INCLUDED - -#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_clocks.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_clocks.h deleted file mode 100644 index c847dbe97ca..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_clocks.h +++ /dev/null @@ -1,198 +0,0 @@ -/** - * \file - * - * \brief SAM D21 Clock configuration - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -#ifndef CONF_CLOCKS_H_INCLUDED -# define CONF_CLOCKS_H_INCLUDED - -/* System clock bus configuration */ -# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false -# define CONF_CLOCK_FLASH_WAIT_STATES 0 -# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 - -/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */ -# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1 -# define CONF_CLOCK_OSC8M_ON_DEMAND true -# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY true - -/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ -# define CONF_CLOCK_XOSC_ENABLE false -# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL -# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 -# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true -# define CONF_CLOCK_XOSC_ON_DEMAND true -# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ -# define CONF_CLOCK_XOSC32K_ENABLE false -# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 -# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false -# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false -# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_XOSC32K_ON_DEMAND false -# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY true - -/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ -# define CONF_CLOCK_OSC32K_ENABLE false -# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 -# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT false -# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ON_DEMAND true -# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ -# define CONF_CLOCK_DFLL_ENABLE false -# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN -# define CONF_CLOCK_DFLL_ON_DEMAND false - -/* DFLL open loop mode configuration */ -# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4) - -/* DFLL closed loop mode configuration */ -# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 -# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768) -# define CONF_CLOCK_DFLL_QUICK_LOCK true -# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true -# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true -# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true -# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 8) -# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 8) - -/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ -# define CONF_CLOCK_DPLL_ENABLE false -# define CONF_CLOCK_DPLL_ON_DEMAND false -# define CONF_CLOCK_DPLL_RUN_IN_STANDBY true -# define CONF_CLOCK_DPLL_LOCK_BYPASS false -# define CONF_CLOCK_DPLL_WAKE_UP_FAST false -# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE true - -# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT -# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K -# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT - -# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 -# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1 -# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 - -/* DPLL GCLK reference configuration */ -# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1 -/* DPLL GCLK lock timer configuration */ -# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1 - -/* Set this to true to configure the GCLK when running clocks_init. If set to - * false, none of the GCLK generators will be configured in clocks_init(). */ -# define CONF_CLOCK_CONFIGURE_GCLK true - -/* Configure GCLK generator 0 (Main Clock) */ -# define CONF_CLOCK_GCLK_0_ENABLE true -# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_0_PRESCALER 1 -# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false - -/* Configure GCLK generator 1 */ -# define CONF_CLOCK_GCLK_1_ENABLE true -# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY true -# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_1_PRESCALER 1 -# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false - -/* Configure GCLK generator 2 (RTC) */ -# define CONF_CLOCK_GCLK_2_ENABLE true -# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY true -# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_ULP32K -# define CONF_CLOCK_GCLK_2_PRESCALER 32 -# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false - -/* Configure GCLK generator 3 */ -# define CONF_CLOCK_GCLK_3_ENABLE false -# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_3_PRESCALER 1 -# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false - -/* Configure GCLK generator 4 */ -# define CONF_CLOCK_GCLK_4_ENABLE false -# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_4_PRESCALER 1 -# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false - -/* Configure GCLK generator 5 */ -# define CONF_CLOCK_GCLK_5_ENABLE false -# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_5_PRESCALER 1 -# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false - -/* Configure GCLK generator 6 */ -# define CONF_CLOCK_GCLK_6_ENABLE false -# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_6_PRESCALER 1 -# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false - -/* Configure GCLK generator 7 */ -# define CONF_CLOCK_GCLK_7_ENABLE false -# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_7_PRESCALER 1 -# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false - -/* Configure GCLK generator 8 */ -# define CONF_CLOCK_GCLK_8_ENABLE false -# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_8_PRESCALER 1 -# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false - -#endif /* CONF_CLOCKS_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_dma.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_dma.h deleted file mode 100644 index ffb71f634fb..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_dma.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief SAM D21 Direct Memory Access Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_DMA_H_INCLUDED -#define CONF_DMA_H_INCLUDED - -# define CONF_MAX_USED_CHANNEL_NUM 1 - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_extint.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_extint.h deleted file mode 100644 index fac3865bd06..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_extint.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief SAM D21 External Interrupt Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_EXTINT_H_INCLUDED -#define CONF_EXTINT_H_INCLUDED - -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_spi.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_spi.h deleted file mode 100644 index c01eb2bd0d0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_spi.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * \brief SAM D21 SPI configuration - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef CONF_SPI_H_INCLUDED -# define CONF_SPI_H_INCLUDED - -# define CONF_SPI_MASTER_ENABLE true -# define CONF_SPI_SLAVE_ENABLE false -# define CONF_SPI_TIMEOUT 10000 - -#endif /* CONF_SPI_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_test.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_test.h deleted file mode 100644 index 35943dad1cd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_test.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \file - * - * \brief SAM D21 Xplained Pro test configuration. - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_TEST_H_INCLUDED -#define CONF_TEST_H_INCLUDED - -#define CONF_STDIO_USART EDBG_CDC_MODULE -#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING -#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0 -#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1 -#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2 -#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3 -#define CONF_STDIO_BAUDRATE 38400 - -#endif /* CONF_TEST_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_board.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_board.h deleted file mode 100644 index 5bc0a39e262..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_board.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Xplained Pro board configuration. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H_INCLUDED -#define CONF_BOARD_H_INCLUDED - -#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_clocks.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_clocks.h deleted file mode 100644 index efc5de493ac..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_clocks.h +++ /dev/null @@ -1,200 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Clock configuration - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -#ifndef CONF_CLOCKS_H_INCLUDED -# define CONF_CLOCKS_H_INCLUDED - -/* System clock bus configuration */ -# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false -# define CONF_CLOCK_FLASH_WAIT_STATES 0 -# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_LOW_POWER_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_BACKUP_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 - -/* SYSTEM_CLOCK_SOURCE_OSC16M configuration - Internal 16MHz oscillator */ -# define CONF_CLOCK_OSC16M_FREQ_SEL SYSTEM_OSC16M_4M -# define CONF_CLOCK_OSC16M_ON_DEMAND true -# define CONF_CLOCK_OSC16M_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ -# define CONF_CLOCK_XOSC_ENABLE false -# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL -# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 -# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true -# define CONF_CLOCK_XOSC_ON_DEMAND true -# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ -# define CONF_CLOCK_XOSC32K_ENABLE false -# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 -# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false -# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_XOSC32K_ON_DEMAND true -# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ -# define CONF_CLOCK_OSC32K_ENABLE false -# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 -# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ON_DEMAND true -# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false - - -/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ -# define CONF_CLOCK_DFLL_ENABLE false -# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN -# define CONF_CLOCK_DFLL_ON_DEMAND false -# define CONF_CLOCK_DFLL_RUN_IN_STANDBY false - -/* DFLL open loop mode configuration */ -# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4) - -/* DFLL closed loop mode configuration */ -# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 -# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768) -# define CONF_CLOCK_DFLL_QUICK_LOCK true -# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true -# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true -# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true -# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4) -# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4) - -/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ -# define CONF_CLOCK_DPLL_ENABLE false -# define CONF_CLOCK_DPLL_ON_DEMAND true -# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false -# define CONF_CLOCK_DPLL_LOCK_BYPASS false -# define CONF_CLOCK_DPLL_WAKE_UP_FAST false -# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false - -# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT -# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K -# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT -# define CONF_CLOCK_DPLL_PRESCALER SYSTEM_CLOCK_SOURCE_DPLL_DIV_1 - - -# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 -# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1 -# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 - -/* DPLL GCLK reference configuration */ -# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1 -/* DPLL GCLK lock timer configuration */ -# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1 - - -/* Set this to true to configure the GCLK when running clocks_init. If set to - * false, none of the GCLK generators will be configured in clocks_init(). */ -# define CONF_CLOCK_CONFIGURE_GCLK true - -/* Configure GCLK generator 0 (Main Clock) */ -# define CONF_CLOCK_GCLK_0_ENABLE true -# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M -# define CONF_CLOCK_GCLK_0_PRESCALER 1 -# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false - -/* Configure GCLK generator 1 */ -# define CONF_CLOCK_GCLK_1_ENABLE false -# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K -# define CONF_CLOCK_GCLK_1_PRESCALER 1 -# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false - -/* Configure GCLK generator 2 */ -# define CONF_CLOCK_GCLK_2_ENABLE false -# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M -# define CONF_CLOCK_GCLK_2_PRESCALER 1 -# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false - -/* Configure GCLK generator 3 */ -# define CONF_CLOCK_GCLK_3_ENABLE false -# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M -# define CONF_CLOCK_GCLK_3_PRESCALER 1 -# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false - -/* Configure GCLK generator 4 */ -# define CONF_CLOCK_GCLK_4_ENABLE false -# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M -# define CONF_CLOCK_GCLK_4_PRESCALER 1 -# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false - -/* Configure GCLK generator 5 */ -# define CONF_CLOCK_GCLK_5_ENABLE false -# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M -# define CONF_CLOCK_GCLK_5_PRESCALER 1 -# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false - -/* Configure GCLK generator 6 */ -# define CONF_CLOCK_GCLK_6_ENABLE false -# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M -# define CONF_CLOCK_GCLK_6_PRESCALER 1 -# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false - -/* Configure GCLK generator 7 */ -# define CONF_CLOCK_GCLK_7_ENABLE false -# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M -# define CONF_CLOCK_GCLK_7_PRESCALER 1 -# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false - -/* Configure GCLK generator 8 */ -# define CONF_CLOCK_GCLK_8_ENABLE false -# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M -# define CONF_CLOCK_GCLK_8_PRESCALER 1 -# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false -#endif /* CONF_CLOCKS_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_dma.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_dma.h deleted file mode 100644 index d69e2c875b3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_dma.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Direct Memory Access Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_DMA_H_INCLUDED -#define CONF_DMA_H_INCLUDED - -# define CONF_MAX_USED_CHANNEL_NUM 1 - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_extint.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_extint.h deleted file mode 100644 index 55ffb24fae3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_extint.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief SAM L21 External Interrupt Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_EXTINT_H_INCLUDED -#define CONF_EXTINT_H_INCLUDED - -# define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_spi.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_spi.h deleted file mode 100644 index 499cd2692e1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_spi.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * \brief SAM L21 SPI configuration - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef CONF_SPI_H_INCLUDED -# define CONF_SPI_H_INCLUDED - -# define CONF_SPI_MASTER_ENABLE true -# define CONF_SPI_SLAVE_ENABLE false -# define CONF_SPI_TIMEOUT 10000 - -#endif /* CONF_SPI_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_test.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_test.h deleted file mode 100644 index 4d98422ea72..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_test.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Xplained Pro test configuration. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_TEST_H_INCLUDED -#define CONF_TEST_H_INCLUDED - -#define CONF_STDIO_USART EDBG_CDC_MODULE -#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING -#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0 -#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1 -#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2 -#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3 -#define CONF_STDIO_BAUDRATE 38400 - -#endif /* CONF_TEST_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_board.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_board.h deleted file mode 100644 index 814b959e193..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_board.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * \file - * - * \brief SAM R21 Xplained Pro board configuration. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H_INCLUDED -#define CONF_BOARD_H_INCLUDED - -#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_clocks.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_clocks.h deleted file mode 100644 index 5d6424a2d9e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_clocks.h +++ /dev/null @@ -1,202 +0,0 @@ -/** - * \file - * - * \brief SAM R21 Clock configuration - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -#ifndef CONF_CLOCKS_H_INCLUDED -# define CONF_CLOCKS_H_INCLUDED - -/* System clock bus configuration */ -# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false -# define CONF_CLOCK_FLASH_WAIT_STATES 0 -# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 - -/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */ -# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1 -# define CONF_CLOCK_OSC8M_ON_DEMAND true -# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ -# define CONF_CLOCK_XOSC_ENABLE false -# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL -# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 -# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true -# define CONF_CLOCK_XOSC_ON_DEMAND true -# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ -# define CONF_CLOCK_XOSC32K_ENABLE false -# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 -# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false -# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false -# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_XOSC32K_ON_DEMAND true -# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false - -//! [oscillator_settings] -/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ -# define CONF_CLOCK_OSC32K_ENABLE true -# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 -# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ON_DEMAND true -# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false -//! [oscillator_settings] - -/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ -# define CONF_CLOCK_DFLL_ENABLE false -# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN -# define CONF_CLOCK_DFLL_ON_DEMAND false - -/* DFLL open loop mode configuration */ -# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4) - -/* DFLL closed loop mode configuration */ -# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 -# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR 6 -# define CONF_CLOCK_DFLL_QUICK_LOCK true -# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true -# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true -# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true -# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4) -# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4) - -/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ -# define CONF_CLOCK_DPLL_ENABLE false -# define CONF_CLOCK_DPLL_ON_DEMAND true -# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false -# define CONF_CLOCK_DPLL_LOCK_BYPASS false -# define CONF_CLOCK_DPLL_WAKE_UP_FAST false -# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false - -# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT -# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K -# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT - -# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 -# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1 -# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 - -/* DPLL GCLK reference configuration */ -# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1 -/* DPLL GCLK lock timer configuration */ -# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1 - -/* Set this to true to configure the GCLK when running clocks_init. If set to - * false, none of the GCLK generators will be configured in clocks_init(). */ -# define CONF_CLOCK_CONFIGURE_GCLK true - -/* Configure GCLK generator 0 (Main Clock) */ -# define CONF_CLOCK_GCLK_0_ENABLE true -# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_0_PRESCALER 1 -# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false - -/* Configure GCLK generator 1 */ -# define CONF_CLOCK_GCLK_1_ENABLE false -# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_1_PRESCALER 1 -# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false - -//! [gclk_settings] -/* Configure GCLK generator 2 (RTC) */ -# define CONF_CLOCK_GCLK_2_ENABLE true -# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K -# define CONF_CLOCK_GCLK_2_PRESCALER 32 -# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false -//! [gclk_settings] - -/* Configure GCLK generator 3 */ -# define CONF_CLOCK_GCLK_3_ENABLE false -# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_3_PRESCALER 1 -# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false - -/* Configure GCLK generator 4 */ -# define CONF_CLOCK_GCLK_4_ENABLE false -# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_4_PRESCALER 1 -# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false - -/* Configure GCLK generator 5 */ -# define CONF_CLOCK_GCLK_5_ENABLE false -# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_5_PRESCALER 1 -# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false - -/* Configure GCLK generator 6 */ -# define CONF_CLOCK_GCLK_6_ENABLE false -# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_6_PRESCALER 1 -# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false - -/* Configure GCLK generator 7 */ -# define CONF_CLOCK_GCLK_7_ENABLE false -# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_7_PRESCALER 1 -# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false - -/* Configure GCLK generator 8 */ -# define CONF_CLOCK_GCLK_8_ENABLE false -# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_8_PRESCALER 1 -# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false - -#endif /* CONF_CLOCKS_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_dma.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_dma.h deleted file mode 100644 index 490182e3c50..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_dma.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef CONF_DMA_H_INCLUDED -#define CONF_DMA_H_INCLUDED - -# define CONF_MAX_USED_CHANNEL_NUM 1 - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_extint.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_extint.h deleted file mode 100644 index f9088c07de9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_extint.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef CONF_EXTINT_H_INCLUDED -#define CONF_EXTINT_H_INCLUDED - -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_spi.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_spi.h deleted file mode 100644 index a9fc98fe8ed..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_spi.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef CONF_SPI_H_INCLUDED -# define CONF_SPI_H_INCLUDED - -# define CONF_SPI_MASTER_ENABLE true -# define CONF_SPI_SLAVE_ENABLE false -# define CONF_SPI_TIMEOUT 10000 - -#endif /* CONF_SPI_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_test.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_test.h deleted file mode 100644 index d7027a72763..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_test.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * \file - * - * \brief SAM R21 Xplained Pro test configuration. - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_TEST_H_INCLUDED -#define CONF_TEST_H_INCLUDED - -#define CONF_STDIO_USART EDBG_CDC_MODULE -#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING -#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0 -#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1 -#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2 -#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3 -#define CONF_STDIO_BAUDRATE 38400 - -#endif /* CONF_TEST_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api.c deleted file mode 100644 index b8d0994afb3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api.c +++ /dev/null @@ -1,372 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "system.h" -#include "dma_api.h" -#include "dma_api_HAL.h" - -#include - -#include "cmsis.h" -#include "pinmap.h" - -/** - * \internal - * Structure redefinition, already defined in dma.c. - * Redefining as that definition is not available here - */ -struct _dma_module { - volatile bool _dma_init; - volatile uint32_t allocated_channels; - uint8_t free_channels; -}; - -extern struct _dma_module _dma_inst; -extern uint8_t g_sys_init; - -static struct dma_instance_s dma_channels[CONF_MAX_USED_CHANNEL_NUM]; - -/** - * \internal - * Get resource index from channel id - * - * @param[in] channelid Valid DMA channel id - * @return index to DMA instance - */ -static uint8_t get_index_from_id(int channelid) -{ - /* Sanity check arguments */ - MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM); - - uint8_t i; - - for (i=0; ichannel_id; - uint8_t channel_index; - - channel_index = get_index_from_id(channelid); - if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) { - return; - } - - callback_func = (void(*)(void))(dma_channels[channel_index].handler); - if (callback_func) { - callback_func(); - } -} - -/** - * \internal - * Configure a DMA channel for specified resource - * - * @param[in] channel_index index to the resource - * @return void - */ -static void configure_dma_resource(uint8_t channel_index) -{ - /* Sanity check arguments */ - MBED_ASSERT(channel_index < CONF_MAX_USED_CHANNEL_NUM); - - enum status_code ret; - struct dma_resource_config config; - - if (dma_channels[channel_index].status & DMA_ALLOCATED) { - return; - } - - /* Get default configuration for DMA */ - dma_get_config_defaults(&config); - - /* Allocate a free channel */ - ret = dma_allocate(&dma_channels[channel_index].resource, &config); - - if (ret == STATUS_OK) { - dma_channels[channel_index].status = DMA_ALLOCATED; - } -} - -/** Setup a DMA descriptor for specified resource - * - * @param[in] channel_index DMA channel id - * @param[in] src source address - * @param[in] src_inc_enable source address auto increment enable flag - * @param[in] desc destination address - * @param[in] desc_inc_enable destination address auto increment enable flag - * @param[in] length length of data to be transferred - * @param[in] beat_size beat size to be set - * @return void - */ -void dma_setup_transfer(uint8_t channelid, uint32_t src, bool src_inc_enable, uint32_t desc, bool desc_inc_enable, uint32_t length, uint8_t beat_size) -{ - enum status_code result; - uint8_t channel_index; - struct dma_descriptor_config descriptor_config; - - /* Sanity check arguments */ - MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM); - MBED_ASSERT(src); - MBED_ASSERT(desc); - - channel_index = get_index_from_id(channelid); - - dma_descriptor_get_config_defaults(&descriptor_config); - - if (beat_size <= 8) { - descriptor_config.beat_size = DMA_BEAT_SIZE_BYTE; - } else if ((beat_size > 8) && (beat_size <= 16)) { - descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD; - } else { - descriptor_config.beat_size = DMA_BEAT_SIZE_WORD; - } - descriptor_config.block_transfer_count = length; - descriptor_config.source_address = src; - descriptor_config.destination_address = desc; - - /* Source address auto-increment is enabled by default */ - if (!src_inc_enable) { - descriptor_config.src_increment_enable = false; - } - - /* Destination address auto-increment is enabled by default */ - if (!desc_inc_enable) { - descriptor_config.dst_increment_enable = false; - } - - dma_descriptor_create(&dma_channels[channel_index].descriptor, &descriptor_config); - - /* Add descriptor to resource */ - if (dma_channels[channel_index].resource.descriptor == NULL) { - /* Multiple calls to this function without releasing already allocated channel is not handled now */ - result = dma_add_descriptor(&dma_channels[channel_index].resource, &dma_channels[channel_index].descriptor); - if (result != STATUS_OK) { - dma_channels[channel_index].status |= DMA_ERROR; - } - } -} - - -/** Initialize the DMA - * - * Configures clock for DMAC - */ -void dma_init() -{ - int i; - - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - - if (!_dma_inst._dma_init) { - for (i=0; i= CONF_MAX_USED_CHANNEL_NUM) { - /* Return invalid value for now */ - return false; - } - - if (!(dma_channels[channel_index].status & DMA_ALLOCATED)) { - /* DMA not allocated, return invalid value for now */ - return false; - } - - /* Start DMA transfer */ - if (STATUS_OK != dma_start_transfer_job(&dma_channels[channel_index].resource)) { - /* Error in starting DMA transfer */ - return false; - } - - return true; -} - -/** DMA channel busy check - * - * To check whether DMA channel is busy with a job or not - * @param[in] channelid Channel id of DMA channel - * @return non zero if busy otherwise zero - */ -bool dma_busy(int channelid) -{ - /* Sanity check arguments */ - MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM); - - uint8_t channel_index; - - channel_index = get_index_from_id(channelid); - - if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) { - /* This channel is not active! return zero for now */ - //res = 0; - return 0; - } - - return dma_is_busy(&dma_channels[channel_index].resource); -} - -/** DMA channel transfer completion check - * - * To check whether DMA channel job is completed or not - * @param[in] channelid Channel id of DMA channel - * @return non zero if busy otherwise zero - */ -bool dma_is_transfer_complete(int channelid) -{ - /* Sanity check arguments */ - MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM); - - uint8_t channel_index; - - channel_index = get_index_from_id(channelid); - - if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) { - /* This channel is not active! return zero for now */ - // res = 0; - return 0; - } - - return (STATUS_OK == dma_get_job_status(&dma_channels[channel_index].resource)); -} - -/** Registers callback function for DMA - * - * Registers callback function for DMA for specified events - * @param[in] channelid Channel id of DMA channel - * @param[in] handler Callback function pointer - * @param[in] event Events mask - * @return void - */ -void dma_set_handler(int channelid, uint32_t handler, uint32_t event) -{ - /* Sanity check arguments */ - MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM); - - uint8_t channel_index; - - channel_index = get_index_from_id(channelid); - - if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) { - /* Return for now */ - return; - } - - dma_channels[channel_index].handler = handler; - if (event & DMA_TRANSFER_ERROR) { - dma_register_callback(&dma_channels[channel_index].resource, (dma_callback_t)dma_handler, DMA_CALLBACK_TRANSFER_ERROR); - } - if (event & DMA_TRANSFER_COMPLETE) { - dma_register_callback(&dma_channels[channel_index].resource, (dma_callback_t)dma_handler, DMA_CALLBACK_TRANSFER_DONE); - } - - /* Set interrupt vector if someone have removed it */ - NVIC_SetVector(DMAC_IRQn, (uint32_t)DMAC_Handler); - /* Enable interrupt */ - NVIC_EnableIRQ(DMAC_IRQn); -} - -/** Frees an allocated DMA channel - * - * Frees an already allocated DMA channel with specified channel id - * @param[in] channelid Channel id of DMA channel to be disabled - * @return zero if success - */ -int dma_channel_free(int channelid) -{ - /* Sanity check arguments */ - MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM); - - uint8_t channel_index; - - channel_index = get_index_from_id(channelid); - - if (STATUS_OK == dma_free(&dma_channels[channel_index].resource)) { - dma_channels[channel_index].status = DMA_NOT_USED; - dma_channels[channel_index].resource.descriptor = NULL; - return 0; - } else { - /* Return invalid value for now */ - return -1; - } -} - - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api_HAL.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api_HAL.h deleted file mode 100644 index a0b674bb197..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api_HAL.h +++ /dev/null @@ -1,106 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _DMA_API_HAL_H -#define _DMA_API_HAL_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "dma.h" - -enum dma_status_flags { - DMA_NOT_USED = (uint32_t)1, - DMA_ALLOCATED = (DMA_NOT_USED << 1), - DMA_TEMPORARY = (DMA_NOT_USED << 2), - DMA_ERROR = (DMA_NOT_USED << 3), -}; - -/* No other capabilities supported now */ -#define DMA_CAP_NONE 0 - -#define DMA_ADDRESS_INC_DISABLE 0 -#define DMA_ADDRESS_INC_ENABLE 1 - -#define DMA_TRANSFER_ERROR ((uint32_t)1 << 1) -#define DMA_TRANSFER_COMPLETE ((uint32_t)1 << 2) - -#define DMA_EVENT_ALL (DMA_TRANSFER_ERROR | DMA_TRANSFER_COMPLETE) - - -COMPILER_ALIGNED(16) -struct dma_instance_s { - struct dma_resource resource; - DmacDescriptor descriptor; - uint8_t status; - uint32_t events; - uint32_t handler; -}; - -/** Setup a DMA descriptor for specified resource - * - * @param[in] channel_index DMA channel id - * @param[in] src source address - * @param[in] src_inc_enable source address auto increment enable flag - * @param[in] desc destination address - * @param[in] desc_inc_enable destination address auto increment enable flag - * @param[in] length length of data to be transferred - * @param[in] beat_size beat size to be set - * @return void - */ -void dma_setup_transfer(uint8_t channelid, uint32_t src, bool src_inc_enable, uint32_t desc, bool desc_inc_enable, uint32_t length, uint8_t beat_size); - -/** Start DMA transfer - * - * Kick starts transfer in DMA channel with specified channel id - * @param[in] channelid Channel id of DMA channel - * @return non zero if success otherwise zero - */ -bool dma_start_transfer(int channelid); - -/** DMA channel busy check - * - * To check whether DMA channel is busy with a job or not - * @param[in] channelid Channel id of DMA channel - * @return non zero if busy otherwise zero - */ -bool dma_busy(int channelid); - -/** DMA channel transfer completion check - * - * To check whether DMA channel job is completed or not - * @param[in] channelid Channel id of DMA channel - * @return non zero if busy otherwise zero - */ -bool dma_is_transfer_complete(int channelid); - -/** Registers callback function for DMA - * - * Registers callback function for DMA for specified events - * @param[in] channelid Channel id of DMA channel - * @param[in] handler Callback function pointer - * @param[in] event Events mask - * @return void - */ -void dma_set_handler(int channelid, uint32_t handler, uint32_t event); - -#ifdef __cplusplus -} -#endif - -#endif /* _DMA_API_HAL_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc.c deleted file mode 100644 index 94330712a3a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc.c +++ /dev/null @@ -1,704 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "adc.h" - -#if SAMD20 -/* The Die revision D number */ -#define REVISON_D_NUM 3 -#endif - -/** - * \brief Initializes an ADC configuration structure to defaults - * - * Initializes a given ADC configuration struct to a set of known default - * values. This function should be called on any new instance of the - * configuration struct before being modified by the user application. - * - * The default configuration is as follows: - * \li GCLK generator 0 (GCLK main) clock source - * \li 1V from internal bandgap reference - * \li Div 4 clock prescaler - * \li 12-bit resolution - * \li Window monitor disabled - * \li No gain - * \li Positive input on ADC PIN 0 - * \li Negative input on ADC PIN 1 - * \li Averaging disabled - * \li Oversampling disabled - * \li Right adjust data - * \li Single-ended mode - * \li Free running disabled - * \li All events (input and generation) disabled - * \li Sleep operation disabled - * \li No reference compensation - * \li No gain/offset correction - * \li No added sampling time - * \li Pin scan mode disabled - * - * \param[out] config Pointer to configuration struct to initialize to - * default values - */ -void adc_get_config_defaults(struct adc_config *const config) -{ - Assert(config); - config->clock_source = GCLK_GENERATOR_0; - config->reference = ADC_REFERENCE_INT1V; - config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4; - config->resolution = ADC_RESOLUTION_12BIT; - config->window.window_mode = ADC_WINDOW_MODE_DISABLE; - config->window.window_upper_value = 0; - config->window.window_lower_value = 0; - config->gain_factor = ADC_GAIN_FACTOR_1X; -#if SAMR21 - config->positive_input = ADC_POSITIVE_INPUT_PIN6 ; -#else - config->positive_input = ADC_POSITIVE_INPUT_PIN0 ; -#endif - config->negative_input = ADC_NEGATIVE_INPUT_GND ; - config->accumulate_samples = ADC_ACCUMULATE_DISABLE; - config->divide_result = ADC_DIVIDE_RESULT_DISABLE; - config->left_adjust = false; - config->differential_mode = false; - config->freerunning = false; - config->event_action = ADC_EVENT_ACTION_DISABLED; - config->run_in_standby = false; - config->reference_compensation_enable = false; - config->correction.correction_enable = false; - config->correction.gain_correction = ADC_GAINCORR_RESETVALUE; - config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE; - config->sample_length = 0; - config->pin_scan.offset_start_scan = 0; - config->pin_scan.inputs_to_scan = 0; -} - -/** - * \brief Sets the ADC window mode - * - * Sets the ADC window mode to a given mode and value range. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] window_mode Window monitor mode to set - * \param[in] window_lower_value Lower window monitor threshold value - * \param[in] window_upper_value Upper window monitor threshold value - */ -void adc_set_window_mode( - struct adc_module *const module_inst, - const enum adc_window_mode window_mode, - const int16_t window_lower_value, - const int16_t window_upper_value) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set window mode */ - adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set lower window monitor threshold value */ - adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set upper window monitor threshold value */ - adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos; -} - -/** -* \internal Configure MUX settings for the analog pins -* -* This function will set the given ADC input pins -* to the analog function in the pinmux, giving -* the ADC access to the analog signal -* -* \param [in] pin AINxx pin to configure -*/ -static inline void _adc_configure_ain_pin(uint32_t pin) -{ -#define PIN_INVALID_ADC_AIN 0xFFFFUL - - /* Pinmapping table for AINxx -> GPIO pin number */ - const uint32_t pinmapping[] = { -#if (SAMD20E) || (SAMD21E)|| (SAMDA1E) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, - PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif SAMR21E - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif SAMR21G - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10C) || (SAMD11C) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10DS) || (SAMD11DS) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10DM) || (SAMD11DM) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#else -# error ADC pin mappings are not defined for this device. -#endif - }; - - uint32_t pin_map_result = PIN_INVALID_ADC_AIN; - - if (pin <= ADC_EXTCHANNEL_MSB) { - pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; - - Assert(pin_map_result != PIN_INVALID_ADC_AIN); - - struct system_pinmux_config config; - system_pinmux_get_config_defaults(&config); - - /* Analog functions are all on MUX setting B */ - config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - config.mux_position = 1; - - system_pinmux_pin_set_config(pin_map_result, &config); - } -} - -/** - * \internal Writes an ADC configuration to the hardware module - * - * Writes out a given ADC module configuration to the hardware module. - * - * \param[out] module_inst Pointer to the ADC software instance struct - * \param[in] config Pointer to configuration struct - * - * \return Status of the configuration procedure - * \retval STATUS_OK The configuration was successful - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided - */ -static enum status_code _adc_set_config( - struct adc_module *const module_inst, - struct adc_config *const config) -{ - uint8_t adjres = 0; - uint32_t resolution = ADC_RESOLUTION_16BIT; - enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE; -#if SAMD20 - uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos); -#endif - - /* Get the hardware module pointer */ - Adc *const adc_module = module_inst->hw; - - /* Configure GCLK channel and enable clock */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->clock_source; - system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(ADC_GCLK_ID); - - /* Setup pinmuxing for analog inputs */ - if (config->pin_scan.inputs_to_scan != 0) { - uint8_t offset = config->pin_scan.offset_start_scan; - uint8_t start_pin = - offset +(uint8_t)config->positive_input; - uint8_t end_pin = - start_pin + config->pin_scan.inputs_to_scan; - - while (start_pin < end_pin) { - _adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input); - start_pin++; - offset++; - } - _adc_configure_ain_pin(config->negative_input); - } else { - _adc_configure_ain_pin(config->positive_input); - _adc_configure_ain_pin(config->negative_input); - } - - /* Configure run in standby */ - adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos); - - /* Configure reference */ - adc_module->REFCTRL.reg = - (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) | - (config->reference); - - /* Set adjusting result and number of samples */ - switch (config->resolution) { - - case ADC_RESOLUTION_CUSTOM: - adjres = config->divide_result; - accumulate = config->accumulate_samples; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_13BIT: - /* Increase resolution by 1 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_4; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_14BIT: - /* Increase resolution by 2 bit */ - adjres = ADC_DIVIDE_RESULT_4; - accumulate = ADC_ACCUMULATE_SAMPLES_16; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#if SAMD20 - /* See $35.1.8 for ADC errata of SAM D20. - The revisions before D have this issue.*/ - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - if(revision_num < REVISON_D_NUM) { - adjres = ADC_DIVIDE_RESULT_8; - } else { - adjres = ADC_DIVIDE_RESULT_2; - } - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_16BIT: - if(revision_num < REVISON_D_NUM) { - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_16; - } else { - adjres = ADC_DIVIDE_RESULT_DISABLE; - } - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#else - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_16BIT: - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_DISABLE; - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#endif - case ADC_RESOLUTION_8BIT: - /* 8-bit result register */ - resolution = ADC_RESOLUTION_8BIT; - break; - case ADC_RESOLUTION_10BIT: - /* 10-bit result register */ - resolution = ADC_RESOLUTION_10BIT; - break; - case ADC_RESOLUTION_12BIT: - /* 12-bit result register */ - resolution = ADC_RESOLUTION_12BIT; - break; - - default: - /* Unknown. Abort. */ - return STATUS_ERR_INVALID_ARG; - } - - adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate; - - /* Check validity of sample length value */ - if (config->sample_length > 63) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Configure sample length */ - adc_module->SAMPCTRL.reg = - (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos); - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure CTRLB */ - adc_module->CTRLB.reg = - config->clock_prescaler | - resolution | - (config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) | - (config->freerunning << ADC_CTRLB_FREERUN_Pos) | - (config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) | - (config->differential_mode << ADC_CTRLB_DIFFMODE_Pos); - - /* Check validity of window thresholds */ - if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) { - switch (resolution) { - case ADC_RESOLUTION_8BIT: - if (config->differential_mode && - (config->window.window_lower_value > 127 || - config->window.window_lower_value < -128 || - config->window.window_upper_value > 127 || - config->window.window_upper_value < -128)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 255 || - config->window.window_upper_value > 255) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_10BIT: - if (config->differential_mode && - (config->window.window_lower_value > 511 || - config->window.window_lower_value < -512 || - config->window.window_upper_value > 511 || - config->window.window_upper_value < -512)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 1023 || - config->window.window_upper_value > 1023) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_12BIT: - if (config->differential_mode && - (config->window.window_lower_value > 2047 || - config->window.window_lower_value < -2048 || - config->window.window_upper_value > 2047 || - config->window.window_upper_value < -2048)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 4095 || - config->window.window_upper_value > 4095) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_16BIT: - if (config->differential_mode && - (config->window.window_lower_value > 32767 || - config->window.window_lower_value < -32768 || - config->window.window_upper_value > 32767 || - config->window.window_upper_value < -32768)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 65535 || - config->window.window_upper_value > 65535) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - } - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure window mode */ - adc_module->WINCTRL.reg = config->window.window_mode; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure lower threshold */ - adc_module->WINLT.reg = - config->window.window_lower_value << ADC_WINLT_WINLT_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure lower threshold */ - adc_module->WINUT.reg = config->window.window_upper_value << - ADC_WINUT_WINUT_Pos; - - uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan; - if (inputs_to_scan > 0) { - /* - * Number of input sources included is the value written to INPUTSCAN - * plus 1. - */ - inputs_to_scan--; - } - - if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || - config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { - /* Invalid number of input pins or input offset */ - return STATUS_ERR_INVALID_ARG; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure pin scan mode and positive and negative input pins */ - adc_module->INPUTCTRL.reg = - config->gain_factor | - (config->pin_scan.offset_start_scan << - ADC_INPUTCTRL_INPUTOFFSET_Pos) | - (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) | - config->negative_input | - config->positive_input; - - /* Configure events */ - adc_module->EVCTRL.reg = config->event_action; - - /* Disable all interrupts */ - adc_module->INTENCLR.reg = - (1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) | - (1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos); - - if (config->correction.correction_enable) { - /* Make sure gain_correction value is valid */ - if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set gain correction value */ - adc_module->GAINCORR.reg = config->correction.gain_correction << - ADC_GAINCORR_GAINCORR_Pos; - } - - /* Make sure offset correction value is valid */ - if (config->correction.offset_correction > 2047 || - config->correction.offset_correction < -2048) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set offset correction value */ - adc_module->OFFSETCORR.reg = config->correction.offset_correction << - ADC_OFFSETCORR_OFFSETCORR_Pos; - } - } - - /* Load in the fixed device ADC calibration constants */ - adc_module->CALIB.reg = - ADC_CALIB_BIAS_CAL( - (*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos) - ) | - ADC_CALIB_LINEARITY_CAL( - (*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos) - ); - - return STATUS_OK; -} - -/** - * \brief Initializes the ADC channel sequence - * - * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one - * automatically after a conversion done, causing the next conversion - * to be done with the positive input equal to MUXPOS + INPUTOFFSET, - * it is scanning continuously one by one even ADC channels are not continuous. - * - * Initializes the ADC channel sequence by the sequence of pin_array. - * - * \param[in] pin_array The array of the Mux selection for the positive ADC input - * \param[in] size The size of pin_array - */ -void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size) -{ - for (int i = 0; i < size; i++) { - _adc_configure_ain_pin(pin_array[i]); - } -} - -/** - * \brief Initializes the ADC - * - * Initializes the ADC device struct and the hardware module based on the - * given configuration struct values. - * - * \param[out] module_inst Pointer to the ADC software instance struct - * \param[in] hw Pointer to the ADC module instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of the initialization procedure. - * \retval STATUS_OK The initialization was successful - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided - * \retval STATUS_BUSY The module is busy with a reset operation - * \retval STATUS_ERR_DENIED The module is enabled - */ -enum status_code adc_init( - struct adc_module *const module_inst, - Adc *hw, - struct adc_config *config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(hw); - Assert(config); - - /* Associate the software module instance with the hardware module */ - module_inst->hw = hw; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC); - - if (hw->CTRLA.reg & ADC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } - - if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } - - /* Store the selected reference for later use */ - module_inst->reference = config->reference; - - /* Make sure bandgap is enabled if requested by the config */ - if (module_inst->reference == ADC_REFERENCE_INT1V) { - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP); - } - -#if ADC_CALLBACK_MODE == true - for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - }; - - module_inst->registered_callback_mask = 0; - module_inst->enabled_callback_mask = 0; - module_inst->remaining_conversions = 0; - module_inst->job_status = STATUS_OK; - - _adc_instances[0] = module_inst; - - if (config->event_action == ADC_EVENT_ACTION_DISABLED && - !config->freerunning) { - module_inst->software_trigger = true; - } else { - module_inst->software_trigger = false; - } -#endif - - /* Write configuration to module */ - return _adc_set_config(module_inst, config); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc_feature.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc_feature.h deleted file mode 100644 index abd7b12ce8f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc_feature.h +++ /dev/null @@ -1,728 +0,0 @@ -/** - * \file - * - * \brief SAM ADC functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef ADC_FEATURE_H_INCLUDED -#define ADC_FEATURE_H_INCLUDED - -/** - * \addtogroup asfdoc_sam0_adc_group - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if ADC_CALLBACK_MODE == true -# include - -#if !defined(__DOXYGEN__) -extern struct adc_module *_adc_instances[ADC_INST_NUM]; -#endif - -/** Forward definition of the device instance. */ -struct adc_module; - -/** Type of the callback functions. */ -typedef void (*adc_callback_t)(struct adc_module *const module); - -/** - * \brief ADC Callback enum - * - * Callback types for ADC callback driver. - * - */ -enum adc_callback { - /** Callback for buffer received. */ - ADC_CALLBACK_READ_BUFFER, - /** Callback when window is hit. */ - ADC_CALLBACK_WINDOW, - /** Callback for error. */ - ADC_CALLBACK_ERROR, -# if !defined(__DOXYGEN__) - /** Number of available callbacks. */ - ADC_CALLBACK_N, -# endif -}; - -#endif - -/** - * \brief ADC reference voltage enum - * - * Enum for the possible reference voltages for the ADC. - * - */ -enum adc_reference { - /** 1.0V voltage reference. */ - ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V, - /** 1/1.48VCC reference. */ - ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, - /** 1/2VCC (only for internal VCC > 2.1V). */ - ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, - /** External reference A. */ - ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, - /** External reference B. */ - ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, -}; - -/** - * \brief ADC clock prescaler enum - * - * Enum for the possible clock prescaler values for the ADC. - * - */ -enum adc_clock_prescaler { - /** ADC clock division factor 4. */ - ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, - /** ADC clock division factor 8. */ - ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, - /** ADC clock division factor 16. */ - ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, - /** ADC clock division factor 32. */ - ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, - /** ADC clock division factor 64. */ - ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, - /** ADC clock division factor 128. */ - ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, - /** ADC clock division factor 256. */ - ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, - /** ADC clock division factor 512. */ - ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512, -}; - -/** - * \brief ADC resolution enum - * - * Enum for the possible resolution values for the ADC. - * - */ -enum adc_resolution { - /** ADC 12-bit resolution. */ - ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT, - /** ADC 16-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT, - /** ADC 10-bit resolution. */ - ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT, - /** ADC 8-bit resolution. */ - ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT, - /** ADC 13-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_13BIT, - /** ADC 14-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_14BIT, - /** ADC 15-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_15BIT, - /** ADC 16-bit result register for use with averaging. When using this mode - * the ADC result register will be set to 16-bit wide, and the number of - * samples to accumulate and the division factor is configured by the - * \ref adc_config.accumulate_samples and \ref adc_config.divide_result - * members in the configuration struct. - */ - ADC_RESOLUTION_CUSTOM, -}; - -/** - * \brief ADC window monitor mode enum - * - * Enum for the possible window monitor modes for the ADC. - * - */ -enum adc_window_mode { - /** No window mode. */ - ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE, - /** RESULT > WINLT. */ - ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1, - /** RESULT < WINUT. */ - ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2, - /** WINLT < RESULT < WINUT. */ - ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3, - /** !(WINLT < RESULT < WINUT). */ - ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4, -}; - -/** - * \brief ADC gain factor selection enum - * - * Enum for the possible gain factor values for the ADC. - * - */ -enum adc_gain_factor { - /** 1x gain. */ - ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X, - /** 2x gain. */ - ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X, - /** 4x gain. */ - ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X, - /** 8x gain. */ - ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X, - /** 16x gain. */ - ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X, - /** 1/2x gain. */ - ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2, -}; - -/** - * \brief ADC event action enum - * - * Enum for the possible actions to take on an incoming event. - * - */ -enum adc_event_action { - /** Event action disabled. */ - ADC_EVENT_ACTION_DISABLED = 0, - /** Flush ADC and start conversion. */ - ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI, - /** Start conversion. */ - ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, -}; - -/** - * \brief ADC positive MUX input selection enum - * - * Enum for the possible positive MUX input selections for the ADC. - * - */ -enum adc_positive_input { - /** ADC0 pin. */ - ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0, - /** ADC1 pin. */ - ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1, - /** ADC2 pin. */ - ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2, - /** ADC3 pin. */ - ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3, - /** ADC4 pin. */ - ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4, - /** ADC5 pin. */ - ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5, - /** ADC6 pin. */ - ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6, - /** ADC7 pin. */ - ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7, - /** ADC8 pin. */ - ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8, - /** ADC9 pin. */ - ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9, - /** ADC10 pin. */ - ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10, - /** ADC11 pin. */ - ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11, - /** ADC12 pin. */ - ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12, - /** ADC13 pin. */ - ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13, - /** ADC14 pin. */ - ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14, - /** ADC15 pin. */ - ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15, - /** ADC16 pin. */ - ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16, - /** ADC17 pin. */ - ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17, - /** ADC18 pin. */ - ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18, - /** ADC19 pin. */ - ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19, - /** Temperature reference. */ - ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, - /** Bandgap voltage. */ - ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, - /** 1/4 scaled core supply. */ - ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, - /** 1/4 scaled I/O supply. */ - ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, - /** DAC input. */ - ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, -}; - -/** - * \brief ADC negative MUX input selection enum - * - * Enum for the possible negative MUX input selections for the ADC. - * - */ -enum adc_negative_input { - /** ADC0 pin. */ - ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0, - /** ADC1 pin. */ - ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1, - /** ADC2 pin. */ - ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2, - /** ADC3 pin. */ - ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3, - /** ADC4 pin. */ - ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4, - /** ADC5 pin. */ - ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5, - /** ADC6 pin. */ - ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6, - /** ADC7 pin. */ - ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7, - /** Internal ground. */ - ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, - /** I/O ground. */ - ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND, -}; - -/** - * \brief ADC number of accumulated samples enum - * - * Enum for the possible numbers of ADC samples to accumulate. - * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM - * resolution setting is used. - * - */ -enum adc_accumulate_samples { - /** No averaging. */ - ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, - /** Average 2 samples. */ - ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, - /** Average 4 samples. */ - ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, - /** Average 8 samples. */ - ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, - /** Average 16 samples. */ - ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, - /** Average 32 samples. */ - ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, - /** Average 64 samples. */ - ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, - /** Average 128 samples. */ - ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, - /** Average 256 samples. */ - ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, - /** Average 512 samples. */ - ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, - /** Average 1024 samples. */ - ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, -}; - -/** - * \brief ADC possible dividers for the result register - * - * Enum for the possible division factors to use when accumulating - * multiple samples. To keep the same resolution for the averaged - * result and the actual input value, the division factor must - * be equal to the number of samples accumulated. This setting is only - * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used. - */ -enum adc_divide_result { - /** Don't divide result register after accumulation. */ - ADC_DIVIDE_RESULT_DISABLE = 0, - /** Divide result register by 2 after accumulation. */ - ADC_DIVIDE_RESULT_2 = 1, - /** Divide result register by 4 after accumulation. */ - ADC_DIVIDE_RESULT_4 = 2, - /** Divide result register by 8 after accumulation. */ - ADC_DIVIDE_RESULT_8 = 3, - /** Divide result register by 16 after accumulation. */ - ADC_DIVIDE_RESULT_16 = 4, - /** Divide result register by 32 after accumulation. */ - ADC_DIVIDE_RESULT_32 = 5, - /** Divide result register by 64 after accumulation. */ - ADC_DIVIDE_RESULT_64 = 6, - /** Divide result register by 128 after accumulation. */ - ADC_DIVIDE_RESULT_128 = 7, -}; - -#if ADC_CALLBACK_MODE == true -/** - * Enum for the possible ADC interrupt flags. - */ -enum adc_interrupt_flag { - /** ADC result ready. */ - ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, - /** Window monitor match. */ - ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, - /** ADC result overwritten before read. */ - ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, -}; -#endif - -/** - * \brief ADC oversampling and decimation enum - * - * Enum for the possible numbers of bits resolution can be increased by when - * using oversampling and decimation. - * - */ -enum adc_oversampling_and_decimation { - /** Don't use oversampling and decimation mode. */ - ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, - /** 1 bit resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_1BIT, - /** 2 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_2BIT, - /** 3 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_3BIT, - /** 4 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_4BIT -}; - -/** - * \brief Window monitor configuration structure - * - * Window monitor configuration structure. - */ -struct adc_window_config { - /** Selected window mode. */ - enum adc_window_mode window_mode; - /** Lower window value. */ - int32_t window_lower_value; - /** Upper window value. */ - int32_t window_upper_value; -}; - -/** - * \brief ADC event enable/disable structure. - * - * Event flags for the ADC module. This is used to enable and - * disable events via \ref adc_enable_events() and \ref adc_disable_events(). - */ -struct adc_events { - /** Enable event generation on conversion done. */ - bool generate_event_on_conversion_done; - /** Enable event generation on window monitor. */ - bool generate_event_on_window_monitor; -}; - -/** - * \brief Gain and offset correction configuration structure - * - * Gain and offset correction configuration structure. - * Part of the \ref adc_config struct and will be initialized by - * \ref adc_get_config_defaults. - */ -struct adc_correction_config { - /** - * Enables correction for gain and offset based on values of gain_correction and - * offset_correction if set to true. - */ - bool correction_enable; - /** - * This value defines how the ADC conversion result is compensated for gain - * error before written to the result register. This is a fractional value, - * 1-bit integer plus an 11-bit fraction, therefore - * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from - * \c 0b010000000000 to \c 0b111111111111. - */ - uint16_t gain_correction; - /** - * This value defines how the ADC conversion result is compensated for - * offset error before written to the result register. This is a 12-bit - * value in two's complement format. - */ - int16_t offset_correction; -}; - -/** - * \brief Pin scan configuration structure - * - * Pin scan configuration structure. Part of the \ref adc_config struct and will - * be initialized by \ref adc_get_config_defaults. - */ -struct adc_pin_scan_config { - /** - * Offset (relative to selected positive input) of the first input pin to be - * used in pin scan mode. - */ - uint8_t offset_start_scan; - /** - * Number of input pins to scan in pin scan mode. A value below two will - * disable pin scan mode. - */ - uint8_t inputs_to_scan; -}; - -/** - * \brief ADC configuration structure - * - * Configuration structure for an ADC instance. This structure should be - * initialized by the \ref adc_get_config_defaults() - * function before being modified by the user application. - */ -struct adc_config { - /** GCLK generator used to clock the peripheral. */ - enum gclk_generator clock_source; - /** Voltage reference. */ - enum adc_reference reference; - /** Clock prescaler. */ - enum adc_clock_prescaler clock_prescaler; - /** Result resolution. */ - enum adc_resolution resolution; - /** Gain factor. */ - enum adc_gain_factor gain_factor; - /** Positive MUX input. */ - enum adc_positive_input positive_input; - /** Negative MUX input. For singled-ended conversion mode, the negative - * input must be connected to ground. This ground could be the internal - * GND, IOGND or an external ground connected to a pin. */ - enum adc_negative_input negative_input; - /** Number of ADC samples to accumulate when using the - * \c ADC_RESOLUTION_CUSTOM mode.Note: if the result width increases, - * result resolution will be changed accordingly. - */ - enum adc_accumulate_samples accumulate_samples; - /** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */ - enum adc_divide_result divide_result; - /** Left adjusted result. */ - bool left_adjust; - /** Enables differential mode if true. - * if false, ADC will run in singled-ended mode. */ - bool differential_mode; - /** Enables free running mode if true. */ - bool freerunning; - /** Enables ADC in standby sleep mode if true. */ - bool run_in_standby; - /** - * Enables reference buffer offset compensation if true. - * This will increase the accuracy of the gain stage, but decreases the input - * impedance; therefore the startup time of the reference must be increased. - */ - bool reference_compensation_enable; - /** - * This value (0-63) control the ADC sampling time in number of half ADC - * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus - * controlling the ADC input impedance. Sampling time is set according to - * the formula: - * Sample time = (sample_length+1) * (ADCclk / 2). - */ - uint8_t sample_length; - /** Window monitor configuration structure. */ - struct adc_window_config window; - /** Gain and offset correction configuration structure. */ - struct adc_correction_config correction; - /** Event action to take on incoming event. */ - enum adc_event_action event_action; - /** Pin scan configuration structure. */ - struct adc_pin_scan_config pin_scan; -}; - -/** - * \brief ADC software device instance structure. - * - * ADC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct adc_module { -#if !defined(__DOXYGEN__) - /** Pointer to ADC hardware module. */ - Adc *hw; - /** Keep reference configuration so we know when enable is called. */ - enum adc_reference reference; -# if ADC_CALLBACK_MODE == true - /** Array to store callback functions. */ - adc_callback_t callback[ADC_CALLBACK_N]; - /** Pointer to buffer used for ADC results. */ - volatile uint16_t *job_buffer; - /** Remaining number of conversions in current job. */ - volatile uint16_t remaining_conversions; - /** Bit mask for callbacks registered. */ - uint8_t registered_callback_mask; - /** Bit mask for callbacks enabled. */ - uint8_t enabled_callback_mask; - /** Holds the status of the ongoing or last conversion job. */ - volatile enum status_code job_status; - /** If software triggering is needed. */ - bool software_trigger; -# endif -#endif -}; - -#if !defined(__DOXYGEN__) - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true if the module synchronization is ongoing - * \retval false if the module has completed synchronization - */ -static inline bool adc_is_syncing( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - - Adc *const adc_module = module_inst->hw; - - if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) { - return true; - } - - return false; -} -#endif - -/** - * \name ADC Gain and Pin Scan Mode - * @{ - */ - -/** - * \brief Sets ADC gain factor - * - * Sets the ADC gain factor to a specified gain setting. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] gain_factor Gain factor value to set - */ -static inline void adc_set_gain( - struct adc_module *const module_inst, - const enum adc_gain_factor gain_factor) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set new gain factor */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) | - (gain_factor); -} - -/** - * \brief Sets the ADC pin scan mode - * - * Configures the pin scan mode of the ADC module. In pin scan mode, the first - * conversion will start at the configured positive input + start_offset. When - * a conversion is done, a conversion will start on the next input, until - * \c inputs_to_scan number of conversions are made. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] inputs_to_scan Number of input pins to perform a conversion on - * (must be two or more) - * \param[in] start_offset Offset of first pin to scan (relative to - * configured positive input) - * - * \return Status of the pin scan configuration set request. - * - * \retval STATUS_OK Pin scan mode has been set successfully - * \retval STATUS_ERR_INVALID_ARG Number of input pins to scan or offset has - * an invalid value - */ -static inline enum status_code adc_set_pin_scan_mode( - struct adc_module *const module_inst, - uint8_t inputs_to_scan, - const uint8_t start_offset) - -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - if (inputs_to_scan > 0) { - /* - * Number of input sources included is the value written to INPUTSCAN - * plus 1. - */ - inputs_to_scan--; - } - - if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || - start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { - /* Invalid number of input pins */ - return STATUS_ERR_INVALID_ARG; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set pin scan mode */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & - ~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) | - (start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) | - (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos); - - return STATUS_OK; -} - -/** - * \brief Disables pin scan mode - * - * Disables pin scan mode. The next conversion will be made on only one pin - * (the configured positive input pin). - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline void adc_disable_pin_scan_mode( - struct adc_module *const module_inst) -{ - /* Disable pin scan mode */ - adc_set_pin_scan_mode(module_inst, 0, 0); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* ADC_FEATURE_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc.c deleted file mode 100644 index 3ae68f5fb7c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc.c +++ /dev/null @@ -1,769 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "adc.h" -#if (ADC_INST_NUM > 1) || (SAMC20) - -# define _ADC_GCLK_ID(n,unused) TPASTE3(ADC,n,_GCLK_ID), -# define _ADC_APBCMASK(n,unused) TPASTE2(MCLK_APBCMASK_ADC,n), - -# define _ADC_FUSES_BIASCOMP_ADDR(n,unused) TPASTE3(ADC,n,_FUSES_BIASCOMP_ADDR), -# define _ADC_FUSES_BIASCOMP_Pos(n,unused) TPASTE3(ADC,n,_FUSES_BIASCOMP_Pos), -# define _ADC_FUSES_BIASREFBUF_ADDR(n,unused) TPASTE3(ADC,n,_FUSES_BIASREFBUF_ADDR), -# define _ADC_FUSES_BIASREFBUF_Pos(n,unused) TPASTE3(ADC,n,_FUSES_BIASREFBUF_Pos), -# define _ADC_EXTCHANNEL_MSB(n,unused) TPASTE3(ADC,n,_EXTCHANNEL_MSB), - -# define ADC_GCLK_ID MREPEAT(ADC_INST_NUM, _ADC_GCLK_ID, 0) -# define ADC_APBCMASKS MREPEAT(ADC_INST_NUM, _ADC_APBCMASK, 0) - -# define ADC_FUSES_BIASCOMP_ADDR MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_ADDR, 0) -# define ADC_FUSES_BIASCOMP_Pos MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_Pos, 0) -# define ADC_FUSES_BIASREFBUF_ADDR MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_ADDR, 0) -# define ADC_FUSES_BIASREFBUF_Pos MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_Pos, 0) -# define ADC_EXTCHANNEL_MSB MREPEAT(ADC_INST_NUM, _ADC_EXTCHANNEL_MSB, 0) - -#endif - -/* List of ADC GCLK IDs */ -const uint8_t _adc_gclk_ids[ADC_INST_NUM] = { ADC_GCLK_ID }; - -/* List of ADC APB Masks */ -#if (SAML21) -const uint32_t _adc_apbcmasks[ADC_INST_NUM] = { MCLK_APBDMASK_ADC }; -#else -const uint32_t _adc_apbcmasks[ADC_INST_NUM] = { ADC_APBCMASKS }; -#endif - -/* List of Number of external channels of ADC modules. */ -const uint32_t _adc_extchannel_msb[ADC_INST_NUM] = { ADC_EXTCHANNEL_MSB }; - -/* List of address of comparator scaling of ADC modules. */ -const uint32_t _adc_biascomp_addr[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_ADDR }; - -/* List of address of bias reference buffer scaling of ADC modules. */ -const uint32_t _adc_biasrefbuf_addr[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_ADDR }; - -/* List of offset of comparator scaling of ADC modules. */ -const uint8_t _adc_biascomp_pos[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_Pos }; - -/* List of offset of bias reference buffer scaling of ADC modules. */ -const uint8_t _adc_biasrefbuf_pos[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_Pos }; - - -/** - * \internal Find the index of given ADC module instance. - * - * \param[in] ADC module instance pointer. - * - * \return Index of the given ADC module instance. - */ -uint8_t _adc_get_inst_index( - Adc *const hw) -{ - /* List of available ADC modules. */ - Adc *const adc_modules[ADC_INST_NUM] = ADC_INSTS; - - /* Find index for ADC instance. */ - for (uint32_t i = 0; i < ADC_INST_NUM; i++) { - if (hw == adc_modules[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} - -/** - * \brief Initializes an ADC configuration structure to defaults. - * - * Initializes a given ADC configuration struct to a set of known default - * values. This function should be called on any new instance of the - * configuration struct before being modified by the user application. - * - * The default configuration is as follows: - * \li GCLK generator 0 (GCLK main) clock source - * \li Internal bandgap reference - * \li Div 2 clock prescaler - * \li 12-bit resolution - * \li Window monitor disabled - * \li Positive input on ADC PIN 1 - * \li Negative input on Internal ground - * \li Averaging disabled - * \li Oversampling disabled - * \li Right adjust data - * \li Single-ended mode - * \li Free running disabled - * \li All events (input and generation) disabled - * \li ADC run in standby disabled - * \li ADC On demand disabled - * \li No sampling time compensation - * \li Disable the positive input sequense - * \li No reference compensation - * \li No gain/offset correction - * \li No added sampling time - * - * \param[out] config Pointer to configuration struct to initialize to - * default values - */ -void adc_get_config_defaults(struct adc_config *const config) -{ - Assert(config); - config->clock_source = GCLK_GENERATOR_0; - config->reference = ADC_REFERENCE_INTREF; - config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV2; - config->resolution = ADC_RESOLUTION_12BIT; - config->window.window_mode = ADC_WINDOW_MODE_DISABLE; - config->window.window_upper_value = 0; - config->window.window_lower_value = 0; - config->positive_input = ADC_POSITIVE_INPUT_PIN1; - config->negative_input = ADC_NEGATIVE_INPUT_GND; - config->accumulate_samples = ADC_ACCUMULATE_DISABLE; - config->divide_result = ADC_DIVIDE_RESULT_DISABLE; - config->left_adjust = false; - config->differential_mode = false; - config->freerunning = false; - config->event_action = ADC_EVENT_ACTION_DISABLED; - config->run_in_standby = false; - config->on_demand = false; - config->sampling_time_compensation_enable = false; - config->positive_input_sequence_mask_enable = 0; - config->reference_compensation_enable = false; - config->correction.correction_enable = false; - config->correction.gain_correction = ADC_GAINCORR_RESETVALUE; - config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE; - config->sample_length = 0; -} - -/** - * \brief Sets the ADC window mode. - * - * Sets the ADC window mode to a given mode and value range. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] window_mode Window monitor mode to set - * \param[in] window_lower_value Lower window monitor threshold value - * \param[in] window_upper_value Upper window monitor threshold value - */ -void adc_set_window_mode( - struct adc_module *const module_inst, - const enum adc_window_mode window_mode, - const int16_t window_lower_value, - const int16_t window_upper_value) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set window mode */ - adc_module->CTRLC.reg = window_mode; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set lower window monitor threshold value */ - adc_module->WINLT.reg = window_lower_value; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set upper window monitor threshold value */ - adc_module->WINUT.reg = window_upper_value; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} - -/** -* \internal Configure MUX settings for the analog pins. -* -* This function will set the given ADC input pins -* to the analog function in the pin mux, giving -* the ADC access to the analog signal. -* -* \param [in] index Index of the ADC module instance. -* \param [in] pin AINxx pin to configure -*/ -static inline void _adc_configure_ain_pin(uint8_t index, uint32_t pin) -{ -#define PIN_INVALID_ADC_AIN 0xFFFFUL - - /* Pinmapping table for AINxx -> GPIO pin number */ -#if (SAML21) - const uint32_t pinmapping[] = { -# if (SAML21E) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -# elif (SAML21G) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -# elif (SAML21J) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, - PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -# else -# error ADC pin mappings are not defined for this device. -# endif - }; -#elif (SAMC20) - const uint32_t pinmapping[] = { -# if (SAMC20E) - PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, - PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, - PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, - PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, -# elif (SAMC20G) - PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, - PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3, - PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, - PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, - PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, - PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, -# elif (SAMC20J) - PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, - PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3, - PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, - PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, - PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, - PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, -# else -# error ADC pin mappings are not defined for this device. -# endif - }; -#elif (SAMC21) - const uint32_t *pinmapping = NULL;; - const uint32_t pinmapping0[] = { -# if (SAMC21E) - PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, - PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, - PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, - PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, -# elif (SAMC21G) - PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, - PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3, - PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, - PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, - PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, - PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, -# elif (SAMC21J) - PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, - PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3, - PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, - PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, - PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, - PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, -# else -# error ADC pin mappings are not defined for this device. -# endif - }; - const uint32_t pinmapping1[] = { -# if (SAMC21E) - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11, -# elif (SAMC21G) - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC1_AIN2, PIN_PB03B_ADC1_AIN3, - PIN_PB08B_ADC1_AIN4, PIN_PB09B_ADC1_AIN5, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11, -# elif (SAMC21J) - PIN_PB00B_ADC1_AIN0, PIN_PB01B_ADC1_AIN1, - PIN_PB02B_ADC1_AIN2, PIN_PB03B_ADC1_AIN3, - PIN_PB08B_ADC1_AIN4, PIN_PB09B_ADC1_AIN5, - PIN_PB04B_ADC1_AIN6, PIN_PB05B_ADC1_AIN7, - PIN_PB06B_ADC1_AIN8, PIN_PB07B_ADC1_AIN9, - PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11, -# else -# error ADC pin mappings are not defined for this device. -# endif - }; - - switch(index) { - case 0: - pinmapping = pinmapping0; - break; - case 1: - pinmapping = pinmapping1; - break; - default: - break; - } - Assert(pinmapping); -#endif - - uint32_t pin_map_result = PIN_INVALID_ADC_AIN; - - if (pin <= _adc_extchannel_msb[index]) { - pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; - - Assert(pin_map_result != PIN_INVALID_ADC_AIN); - - struct system_pinmux_config config; - system_pinmux_get_config_defaults(&config); - - /* Analog functions are all on MUX setting B */ - config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - config.mux_position = 1; - - system_pinmux_pin_set_config(pin_map_result, &config); - } -} - -/** - * \internal Writes an ADC configuration to the hardware module. - * - * Writes out a given ADC module configuration to the hardware module. - * - * \param[in] index Index of the ADC module instance - * \param[out] module_inst Pointer to the ADC software instance struct - * \param[in] config Pointer to configuration struct - * - * \return Status of the configuration procedure. - * \retval STATUS_OK The configuration was successful - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided - */ -static enum status_code _adc_set_config( - uint8_t index, - struct adc_module *const module_inst, - struct adc_config *const config) -{ - uint8_t adjres = 0; - uint32_t resolution = ADC_RESOLUTION_16BIT; - enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE; - - /* Get the hardware module pointer */ - Adc *const adc_module = module_inst->hw; - - /* Configure GCLK channel and enable clock */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->clock_source; - system_gclk_chan_set_config(_adc_gclk_ids[index], &gclk_chan_conf); - system_gclk_chan_enable(_adc_gclk_ids[index]); - - /* Setup pinmuxing for analog inputs */ - _adc_configure_ain_pin(index, config->positive_input); - _adc_configure_ain_pin(index, config->negative_input); - - /* Set pinmux for positive input sequence*/ - for(uint8_t i=0; i <= _adc_extchannel_msb[index]; i++) { - if(config->positive_input_sequence_mask_enable & (1 << i)) { - _adc_configure_ain_pin(index, i); - } - } - - /* Configure run in standby and on demand */ - adc_module->CTRLA.reg = ((config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos) - | (config->on_demand << ADC_CTRLA_ONDEMAND_Pos)) ; - - /* Configure reference */ - adc_module->REFCTRL.reg = - (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) - | (config->reference); - - /* Set adjusting result and number of samples */ - switch (config->resolution) { - - case ADC_RESOLUTION_CUSTOM: - adjres = config->divide_result; - accumulate = config->accumulate_samples; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_13BIT: - /* Increase resolution by 1 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_4; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_14BIT: - /* Increase resolution by 2 bit */ - adjres = ADC_DIVIDE_RESULT_4; - accumulate = ADC_ACCUMULATE_SAMPLES_16; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_16BIT: - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_DISABLE; - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - case ADC_RESOLUTION_8BIT: - /* 8-bit result register */ - resolution = ADC_RESOLUTION_8BIT; - break; - case ADC_RESOLUTION_10BIT: - /* 10-bit result register */ - resolution = ADC_RESOLUTION_10BIT; - break; - case ADC_RESOLUTION_12BIT: - /* 12-bit result register */ - resolution = ADC_RESOLUTION_12BIT; - break; - - default: - /* Unknown. Abort. */ - return STATUS_ERR_INVALID_ARG; - } - - adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Check validity of sample length value */ - if (config->sample_length > 63) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Configure sample length */ - adc_module->SAMPCTRL.reg = - (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos) - | (config->sampling_time_compensation_enable << ADC_SAMPCTRL_OFFCOMP_Pos); - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure CTRLB */ - adc_module->CTRLB.reg = - config->clock_prescaler; - adc_module->CTRLC.reg = - resolution | - (config->correction.correction_enable << ADC_CTRLC_CORREN_Pos) | - (config->freerunning << ADC_CTRLC_FREERUN_Pos) | - (config->left_adjust << ADC_CTRLC_LEFTADJ_Pos) | - (config->differential_mode << ADC_CTRLC_DIFFMODE_Pos); - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Check validity of window thresholds */ - if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) { - switch (resolution) { - case ADC_RESOLUTION_8BIT: - if (config->differential_mode && - (config->window.window_lower_value > 127 || - config->window.window_lower_value < -128 || - config->window.window_upper_value > 127 || - config->window.window_upper_value < -128)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 255 || - config->window.window_upper_value > 255) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_10BIT: - if (config->differential_mode && - (config->window.window_lower_value > 511 || - config->window.window_lower_value < -512 || - config->window.window_upper_value > 511 || - config->window.window_upper_value < -512)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 1023 || - config->window.window_upper_value > 1023) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_12BIT: - if (config->differential_mode && - (config->window.window_lower_value > 2047 || - config->window.window_lower_value < -2048 || - config->window.window_upper_value > 2047 || - config->window.window_upper_value < -2048)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 4095 || - config->window.window_upper_value > 4095) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_16BIT: - if (config->differential_mode && - (config->window.window_lower_value > 32767 || - config->window.window_lower_value < -32768 || - config->window.window_upper_value > 32767 || - config->window.window_upper_value < -32768)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 65535 || - config->window.window_upper_value > 65535) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - } - } - - /* Configure window mode */ - adc_module->CTRLC.reg |= config->window.window_mode; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure lower threshold */ - adc_module->WINLT.reg = - config->window.window_lower_value << ADC_WINLT_WINLT_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure lower threshold */ - adc_module->WINUT.reg = config->window.window_upper_value << - ADC_WINUT_WINUT_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure pin scan mode and positive and negative input pins */ - adc_module->INPUTCTRL.reg = - config->negative_input | - config->positive_input; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure events */ - adc_module->EVCTRL.reg = config->event_action; - - /* Disable all interrupts */ - adc_module->INTENCLR.reg = - (1 << ADC_INTENCLR_WINMON_Pos) |(1 << ADC_INTENCLR_OVERRUN_Pos) - | (1 << ADC_INTENCLR_RESRDY_Pos); - - if (config->correction.correction_enable) { - /* Make sure gain_correction value is valid */ - if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set gain correction value */ - adc_module->GAINCORR.reg = config->correction.gain_correction << - ADC_GAINCORR_GAINCORR_Pos; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Make sure offset correction value is valid */ - if (config->correction.offset_correction > 2047 || - config->correction.offset_correction < -2048) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set offset correction value */ - adc_module->OFFSETCORR.reg = config->correction.offset_correction << - ADC_OFFSETCORR_OFFSETCORR_Pos; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - } - - /* Load in the fixed device ADC calibration constants */ - adc_module->CALIB.reg = - ADC_CALIB_BIASREFBUF( - (*(uint32_t *)_adc_biasrefbuf_addr[index] >> _adc_biasrefbuf_pos[index]) - ) | - ADC_CALIB_BIASCOMP( - (*(uint32_t *)_adc_biascomp_addr[index] >> _adc_biascomp_pos[index]) - ); - - return STATUS_OK; -} - -/** - * \brief Initializes the ADC. - * - * Initializes the ADC device struct and the hardware module based on the - * given configuration struct values. - * - * \param[out] module_inst Pointer to the ADC software instance struct - * \param[in] hw Pointer to the ADC module instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of the initialization procedure. - * \retval STATUS_OK The initialization was successful - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided - * \retval STATUS_BUSY The module is busy with a reset operation - * \retval STATUS_ERR_DENIED The module is enabled - */ -enum status_code adc_init( - struct adc_module *const module_inst, - Adc *hw, - struct adc_config *config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(hw); - Assert(config); - - /* Temporary variable to hold ADC instance number */ - uint8_t instance = _adc_get_inst_index(hw); - - /* Associate the software module instance with the hardware module */ - module_inst->hw = hw; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, _adc_apbcmasks[instance]); - - if (hw->CTRLA.reg & ADC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } - - /* Store the selected reference for later use */ - module_inst->reference = config->reference; - - /* Make sure the voltage reference is enabled if requested by the config */ - if (module_inst->reference == ADC_REFERENCE_INTREF) { - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT); - } - -#if ADC_CALLBACK_MODE == true - for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - }; - - module_inst->registered_callback_mask = 0; - module_inst->enabled_callback_mask = 0; - module_inst->remaining_conversions = 0; - module_inst->job_status = STATUS_OK; - - _adc_instances[instance] = module_inst; - - if (config->event_action == ADC_EVENT_ACTION_DISABLED && - !config->freerunning) { - module_inst->software_trigger = true; - } else { - module_inst->software_trigger = false; - } -#endif - - /* Write configuration to module */ - return _adc_set_config(instance, module_inst, config); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc_feature.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc_feature.h deleted file mode 100644 index 2c146181cb6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc_feature.h +++ /dev/null @@ -1,726 +0,0 @@ -/** - * \file - * - * \brief SAM ADC functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef ADC_FEATURE_H_INCLUDED -#define ADC_FEATURE_H_INCLUDED - -/** - * \addtogroup asfdoc_sam0_adc_group - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/*@{*/ -#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** Output Driver Strength Selection feature support. */ -# define FEATURE_ADC_SUPPORT_MASTER_SLAVE -#endif -/*@}*/ - -#if ADC_CALLBACK_MODE == true -# include - -#if !defined(__DOXYGEN__) -extern struct adc_module *_adc_instances[ADC_INST_NUM]; -#endif - -/** Forward definition of the device instance. */ -struct adc_module; - -/** Type of the callback functions. */ -typedef void (*adc_callback_t)(struct adc_module *const module); - -/** - * \brief ADC callback enum. - * - * Callback types for ADC callback driver. - * - */ -enum adc_callback { - /** Callback for buffer received */ - ADC_CALLBACK_READ_BUFFER, - /** Callback when window is hit */ - ADC_CALLBACK_WINDOW, - /** Callback for error */ - ADC_CALLBACK_ERROR, -# if !defined(__DOXYGEN__) - /** Number of available callbacks */ - ADC_CALLBACK_N, -# endif -}; - -#endif - -/** - * \brief ADC reference voltage enum. - * - * Enum for the possible reference voltages for the ADC. - * - */ -enum adc_reference { - /** Internal Bandgap Reference */ - ADC_REFERENCE_INTREF = ADC_REFCTRL_REFSEL_INTREF, - /** 1/1.48VCC reference */ - ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, - /** 1/2VCC (only for internal VCC > 2.1V) */ - ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, - /** External reference A */ - ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, -#if (SAML21) - /** External reference B. */ - ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, -#endif -#if (SAMC20) || (SAMC21) - /** DAC. */ - ADC_REFERENCE_DAC = ADC_REFCTRL_REFSEL_DAC, -#endif - /** VDDANA. */ - ADC_REFERENCE_INTVCC2 = ADC_REFCTRL_REFSEL_INTVCC2, -}; - -/** - * \brief ADC clock prescaler enum. - * - * Enum for the possible clock prescaler values for the ADC. - * - */ -enum adc_clock_prescaler { - /** ADC clock division factor 2 */ - ADC_CLOCK_PRESCALER_DIV2 = ADC_CTRLB_PRESCALER_DIV2, - /** ADC clock division factor 4 */ - ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, - /** ADC clock division factor 8 */ - ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, - /** ADC clock division factor 16 */ - ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, - /** ADC clock division factor 32 */ - ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, - /** ADC clock division factor 64 */ - ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, - /** ADC clock division factor 128 */ - ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, - /** ADC clock division factor 256 */ - ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, -}; - -/** - * \brief ADC resolution enum. - * - * Enum for the possible resolution values for the ADC. - * - */ -enum adc_resolution { - /** ADC 12-bit resolution */ - ADC_RESOLUTION_12BIT = ADC_CTRLC_RESSEL_12BIT, - /** ADC 16-bit resolution using oversampling and decimation */ - ADC_RESOLUTION_16BIT = ADC_CTRLC_RESSEL_16BIT, - /** ADC 10-bit resolution */ - ADC_RESOLUTION_10BIT = ADC_CTRLC_RESSEL_10BIT, - /** ADC 8-bit resolution */ - ADC_RESOLUTION_8BIT = ADC_CTRLC_RESSEL_8BIT, - /** ADC 13-bit resolution using oversampling and decimation */ - ADC_RESOLUTION_13BIT, - /** ADC 14-bit resolution using oversampling and decimation */ - ADC_RESOLUTION_14BIT, - /** ADC 15-bit resolution using oversampling and decimation */ - ADC_RESOLUTION_15BIT, - /** ADC 16-bit result register for use with averaging. When using this mode - * the ADC result register will be set to 16-bit wide, and the number of - * samples to accumulate and the division factor is configured by the - * \ref adc_config.accumulate_samples and \ref adc_config.divide_result - * members in the configuration struct. - */ - ADC_RESOLUTION_CUSTOM, -}; - -/** - * \brief ADC window monitor mode enum. - * - * Enum for the possible window monitor modes for the ADC. - * - */ -enum adc_window_mode { - /** No window mode */ - ADC_WINDOW_MODE_DISABLE = ADC_CTRLC_WINMODE_DISABLE, - /** RESULT > WINLT */ - ADC_WINDOW_MODE_ABOVE_LOWER = ADC_CTRLC_WINMODE_MODE1, - /** RESULT < WINUT */ - ADC_WINDOW_MODE_BELOW_UPPER = ADC_CTRLC_WINMODE_MODE2, - /** WINLT < RESULT < WINUT */ - ADC_WINDOW_MODE_BETWEEN = ADC_CTRLC_WINMODE_MODE3, - /** !(WINLT < RESULT < WINUT) */ - ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_CTRLC_WINMODE_MODE4, -}; - -/** - * \brief ADC event action enum. - * - * Enum for the possible actions to take on an incoming event. - * - */ -enum adc_event_action { - /** Event action disabled */ - ADC_EVENT_ACTION_DISABLED = 0, - /** Flush ADC and start conversion */ - ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_FLUSHEI, - /** Start conversion */ - ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, -}; - -/** - * \brief ADC positive MUX input selection enum. - * - * Enum for the possible positive MUX input selections for the ADC. - * - */ -enum adc_positive_input { - /** ADC0 pin */ - ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_AIN0, - /** ADC1 pin */ - ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_AIN1, - /** ADC2 pin */ - ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_AIN2, - /** ADC3 pin */ - ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_AIN3, - /** ADC4 pin */ - ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, - /** ADC5 pin */ - ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_AIN5, - /** ADC6 pin */ - ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_AIN6, - /** ADC7 pin */ - ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_AIN7, - /** ADC8 pin */ - ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_AIN8, - /** ADC9 pin */ - ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_AIN9, - /** ADC10 pin */ - ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_AIN10, - /** ADC11 pin */ - ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_AIN11, -#if !(SAMC20) && !(SAMC21) - /** ADC12 pin. */ - ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_AIN12, - /** ADC13 pin */ - ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_AIN13, - /** ADC14 pin */ - ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_AIN14, - /** ADC15 pin */ - ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_AIN15, - /** ADC16 pin */ - ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_AIN16, - /** ADC17 pin */ - ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_AIN17, - /** ADC18 pin */ - ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_AIN18, - /** ADC19 pin */ - ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_AIN19, - /** ADC20 pin */ - ADC_POSITIVE_INPUT_PIN20 = ADC_INPUTCTRL_MUXPOS_AIN20, - /** ADC21 pin */ - ADC_POSITIVE_INPUT_PIN21 = ADC_INPUTCTRL_MUXPOS_AIN21, - /** ADC22 pin */ - ADC_POSITIVE_INPUT_PIN22 = ADC_INPUTCTRL_MUXPOS_AIN22, - /** ADC23 pin */ - ADC_POSITIVE_INPUT_PIN23 = ADC_INPUTCTRL_MUXPOS_AIN23, - /** Temperature reference */ - ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, -#endif - /** Bandgap voltage. */ - ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, - /** 1/4 scaled core supply */ - ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, - /** 1/4 scaled I/O supply */ - ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, - /** DAC input */ - ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, -#if !(SAMC20) && !(SAMC21) - /** SCALEDVBAT. */ - ADC_POSITIVE_INPUT_SCALEDVBAT = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT, - /** OPAMP01 */ - ADC_POSITIVE_INPUT_OPAMP01 = ADC_INPUTCTRL_MUXPOS_OPAMP01, - /** OPAMP02 */ - ADC_POSITIVE_INPUT_OPAMP2 = ADC_INPUTCTRL_MUXPOS_OPAMP2, -#endif -}; - -/** - * \brief ADC negative MUX input selection enum. - * - * Enum for the possible negative MUX input selections for the ADC. - * - */ -enum adc_negative_input { - /** ADC0 pin */ - ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_AIN0, - /** ADC1 pin */ - ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_AIN1, - /** ADC2 pin */ - ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_AIN2, - /** ADC3 pin */ - ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_AIN3, - /** ADC4 pin */ - ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_AIN4, - /** ADC5 pin */ - ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_AIN5, -#if !(SAMC20) && !(SAMC21) - /** ADC6 pin. */ - ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_AIN6, - /** ADC7 pin */ - ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_AIN7, -#endif - /** Internal ground. */ - ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG(0x18u), -}; - -/** - * \brief ADC number of accumulated samples enum. - * - * Enum for the possible numbers of ADC samples to accumulate. - * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM - * resolution setting is used. - * - */ -enum adc_accumulate_samples { - /** No averaging */ - ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, - /** Average 2 samples */ - ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, - /** Average 4 samples */ - ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, - /** Average 8 samples */ - ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, - /** Average 16 samples */ - ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, - /** Average 32 samples */ - ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, - /** Average 64 samples */ - ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, - /** Average 128 samples */ - ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, - /** Average 256 samples */ - ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, - /** Average 512 samples */ - ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, - /** Average 1024 samples */ - ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, -}; - -/** - * \brief ADC possible dividers for the result register. - * - * Enum for the possible division factors to use when accumulating - * multiple samples. To keep the same resolution for the averaged - * result and the actual input value, the division factor must - * be equal to the number of samples accumulated. This setting is only - * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used. - */ -enum adc_divide_result { - /** Don't divide result register after accumulation */ - ADC_DIVIDE_RESULT_DISABLE = 0, - /** Divide result register by 2 after accumulation */ - ADC_DIVIDE_RESULT_2 = 1, - /** Divide result register by 4 after accumulation */ - ADC_DIVIDE_RESULT_4 = 2, - /** Divide result register by 8 after accumulation */ - ADC_DIVIDE_RESULT_8 = 3, - /** Divide result register by 16 after accumulation */ - ADC_DIVIDE_RESULT_16 = 4, - /** Divide result register by 32 after accumulation */ - ADC_DIVIDE_RESULT_32 = 5, - /** Divide result register by 64 after accumulation */ - ADC_DIVIDE_RESULT_64 = 6, - /** Divide result register by 128 after accumulation */ - ADC_DIVIDE_RESULT_128 = 7, -}; - -#if ADC_CALLBACK_MODE == true -/** - * Enum for the possible ADC interrupt flags. - */ -enum adc_interrupt_flag { - /** ADC result ready */ - ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, - /** Window monitor match */ - ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, - /** ADC result overwritten before read */ - ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, -}; -#endif - -/** - * \brief ADC oversampling and decimation enum. - * - * Enum for the possible numbers of bits resolution can be increased by when - * using oversampling and decimation. - * - */ -enum adc_oversampling_and_decimation { - /** Don't use oversampling and decimation mode */ - ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, - /** 1 bit resolution increase */ - ADC_OVERSAMPLING_AND_DECIMATION_1BIT, - /** 2 bits resolution increase */ - ADC_OVERSAMPLING_AND_DECIMATION_2BIT, - /** 3 bits resolution increase */ - ADC_OVERSAMPLING_AND_DECIMATION_3BIT, - /** 4 bits resolution increase */ - ADC_OVERSAMPLING_AND_DECIMATION_4BIT -}; - -#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE -/** - * Enum for the trigger selection in dual mode. - */ -enum adc_dual_mode_trigger_selection { - /** Start event or software trigger will start a conversion on both ADCs. */ - ADC_DUAL_MODE_BOTH = ADC_CTRLC_DUALSEL_BOTH, - /** START event or software trigger will alternatingly start a conversion on ADC0 and ADC1. */ - ADC_DUAL_MODE_INTERLEAVE = ADC_CTRLC_DUALSEL_INTERLEAVE, -}; -#endif - -/** - * \brief Window monitor configuration structure. - * - * Window monitor configuration structure. - */ -struct adc_window_config { - /** Selected window mode */ - enum adc_window_mode window_mode; - /** Lower window value */ - int32_t window_lower_value; - /** Upper window value */ - int32_t window_upper_value; -}; - -/** - * \brief ADC event enable/disable structure. - * - * Event flags for the ADC module. This is used to enable and - * disable events via \ref adc_enable_events() and \ref adc_disable_events(). - */ -struct adc_events { - /** Enable event generation on conversion done */ - bool generate_event_on_conversion_done; - /** Enable event generation on window monitor */ - bool generate_event_on_window_monitor; -}; - -/** - * \brief Gain and offset correction configuration structure. - * - * Gain and offset correction configuration structure. - * Part of the \ref adc_config struct and will be initialized by - * \ref adc_get_config_defaults. - */ -struct adc_correction_config { - /** - * Enables correction for gain and offset based on values of gain_correction and - * offset_correction if set to true - */ - bool correction_enable; - /** - * This value defines how the ADC conversion result is compensated for gain - * error before written to the result register. This is a fractional value, - * 1-bit integer plus an 11-bit fraction, therefore - * 1/2 �� gain_correction < 2. Valid \c gain_correction values ranges from - * \c 0b010000000000 to \c 0b111111111111. - */ - uint16_t gain_correction; - /** - * This value defines how the ADC conversion result is compensated for - * offset error before written to the result register. This is a 12-bit - * value in two's complement format. - */ - int16_t offset_correction; -}; - -/** - * \brief ADC configuration structure. - * - * Configuration structure for an ADC instance. This structure should be - * initialized by the \ref adc_get_config_defaults() - * function before being modified by the user application. - */ -struct adc_config { - /** GCLK generator used to clock the peripheral */ - enum gclk_generator clock_source; - /** Voltage reference */ - enum adc_reference reference; - /** Clock prescaler */ - enum adc_clock_prescaler clock_prescaler; - /** Result resolution */ - enum adc_resolution resolution; - /** Positive MUX input */ - enum adc_positive_input positive_input; - /** Negative MUX input */ - enum adc_negative_input negative_input; - /** Number of ADC samples to accumulate when using the - * \c ADC_RESOLUTION_CUSTOM mode - */ - enum adc_accumulate_samples accumulate_samples; - /** Division ration when using the ADC_RESOLUTION_CUSTOM mode */ - enum adc_divide_result divide_result; - /** Left adjusted result */ - bool left_adjust; - /** Enables differential mode if true */ - bool differential_mode; - /** Enables free running mode if true */ - bool freerunning; - /** ADC run in standby control */ - bool run_in_standby; - /** ADC On demand control */ - bool on_demand; - /** - * Enables sampling period offset compensation if true - */ - bool sampling_time_compensation_enable; - /** - * Positive input enabled mask for conversion sequence. - * The sequence start from the lowest input, and go to the next enabled input - * automatically when the conversion is done. If no bits are set the - * sequence is disabled. - */ - uint32_t positive_input_sequence_mask_enable; - /** - * Enables reference buffer offset compensation if true. - * This will increase the accuracy of the gain stage, but decreases the input - * impedance; therefore the startup time of the reference must be increased. - */ - bool reference_compensation_enable; - /** - * This value (0-63) control the ADC sampling time in number of half ADC - * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus - * controlling the ADC input impedance. Sampling time is set according to - * the formula: - * Sample time = (sample_length+1) * (ADCclk / 2). - */ - uint8_t sample_length; - /** Window monitor configuration structure */ - struct adc_window_config window; - /** Gain and offset correction configuration structure */ - struct adc_correction_config correction; - /** Event action to take on incoming event */ - enum adc_event_action event_action; -}; - -/** - * \brief ADC software device instance structure. - * - * ADC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct adc_module { -#if !defined(__DOXYGEN__) - /** Pointer to ADC hardware module */ - Adc *hw; - /** Keep reference configuration so we know when enable is called */ - enum adc_reference reference; -# if ADC_CALLBACK_MODE == true - /** Array to store callback functions */ - adc_callback_t callback[ADC_CALLBACK_N]; - /** Pointer to buffer used for ADC results */ - volatile uint16_t *job_buffer; - /** Remaining number of conversions in current job */ - volatile uint16_t remaining_conversions; - /** Bit mask for callbacks registered */ - uint8_t registered_callback_mask; - /** Bit mask for callbacks enabled */ - uint8_t enabled_callback_mask; - /** Holds the status of the ongoing or last conversion job */ - volatile enum status_code job_status; - /** If software triggering is needed */ - bool software_trigger; -# endif -#endif -}; - -#if !defined(__DOXYGEN__) - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true if the module synchronization is ongoing - * \retval false if the module has completed synchronization - */ -static inline bool adc_is_syncing( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - - Adc *const adc_module = module_inst->hw; - - if (adc_module->SYNCBUSY.reg) { - return true; - } - - return false; -} -#endif - -/** - * \name Positive Input Sequence - * @{ - */ - -/** - * \brief Enable positive input sequence mask for conversion. - * - * The sequence start from the lowest input, and go to the next enabled input - * automatically when the conversion is done. If no bits are set the - * sequence is disabled. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] eanble_seq_mask Sequence mask - */ -static inline void adc_enable_positive_input_sequence( - struct adc_module *const module_inst, - uint32_t positive_input_sequence_mask_enable) -{ - /* Sanity check arguments */ - Assert(module_inst); - - Adc *const adc_module = module_inst->hw; - adc_module->SEQCTRL.reg = positive_input_sequence_mask_enable; -} - -/** - * \brief Disable positive input in the sequence. - * - * Disable positive input in the sequence. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline void adc_disable_positive_input_sequence( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - - Adc *const adc_module = module_inst->hw; - adc_module->SEQCTRL.reg = 0; -} - -/** - * \brief Get ADC sequence status. - * - * Check if a sequence is done and get last conversion done in the sequence. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[out] is_sequence_busy Sequence busy status - * \param[out] sequence_state This value identifies the last conversion - * done in the sequence - */ -static inline void adc_get_sequence_status( - struct adc_module *const module_inst, - bool * is_sequence_busy, - uint8_t *sequence_state) -{ - /* Sanity check arguments */ - Assert(module_inst); - uint8_t temp = false; - Adc *const adc_module = module_inst->hw; - temp = adc_module->SEQSTATUS.reg; - if(temp & ADC_SEQSTATUS_SEQBUSY) { - *is_sequence_busy = true; - } - *sequence_state = temp & ADC_SEQSTATUS_SEQSTATE_Msk; -} - -/** @} */ - -#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE -/** - * \brief Set ADC master and slave mode. - * - * Enable ADC module Master-Slave Operation and select dual mode trigger. - * - * \param[in] master_inst Pointer to the master ADC software instance struct - * \param[in] slave_inst Pointer to the slave ADC software instance struct - * \param[in] dualsel Dual mode trigger selection - * - */ -static inline void adc_set_master_slave_mode( - struct adc_module *const master_inst, - struct adc_module *const slave_inst, - enum adc_dual_mode_trigger_selection dualsel) -{ - /* Sanity check arguments */ - Assert(master_inst); - Assert(slave_inst); - - slave_inst->hw->CTRLA.reg |= ADC_CTRLA_SLAVEEN; - master_inst->hw->CTRLC.reg |= dualsel; - -}; -#endif -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* ADC_FEATURE_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc.c deleted file mode 100644 index 94330712a3a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc.c +++ /dev/null @@ -1,704 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "adc.h" - -#if SAMD20 -/* The Die revision D number */ -#define REVISON_D_NUM 3 -#endif - -/** - * \brief Initializes an ADC configuration structure to defaults - * - * Initializes a given ADC configuration struct to a set of known default - * values. This function should be called on any new instance of the - * configuration struct before being modified by the user application. - * - * The default configuration is as follows: - * \li GCLK generator 0 (GCLK main) clock source - * \li 1V from internal bandgap reference - * \li Div 4 clock prescaler - * \li 12-bit resolution - * \li Window monitor disabled - * \li No gain - * \li Positive input on ADC PIN 0 - * \li Negative input on ADC PIN 1 - * \li Averaging disabled - * \li Oversampling disabled - * \li Right adjust data - * \li Single-ended mode - * \li Free running disabled - * \li All events (input and generation) disabled - * \li Sleep operation disabled - * \li No reference compensation - * \li No gain/offset correction - * \li No added sampling time - * \li Pin scan mode disabled - * - * \param[out] config Pointer to configuration struct to initialize to - * default values - */ -void adc_get_config_defaults(struct adc_config *const config) -{ - Assert(config); - config->clock_source = GCLK_GENERATOR_0; - config->reference = ADC_REFERENCE_INT1V; - config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4; - config->resolution = ADC_RESOLUTION_12BIT; - config->window.window_mode = ADC_WINDOW_MODE_DISABLE; - config->window.window_upper_value = 0; - config->window.window_lower_value = 0; - config->gain_factor = ADC_GAIN_FACTOR_1X; -#if SAMR21 - config->positive_input = ADC_POSITIVE_INPUT_PIN6 ; -#else - config->positive_input = ADC_POSITIVE_INPUT_PIN0 ; -#endif - config->negative_input = ADC_NEGATIVE_INPUT_GND ; - config->accumulate_samples = ADC_ACCUMULATE_DISABLE; - config->divide_result = ADC_DIVIDE_RESULT_DISABLE; - config->left_adjust = false; - config->differential_mode = false; - config->freerunning = false; - config->event_action = ADC_EVENT_ACTION_DISABLED; - config->run_in_standby = false; - config->reference_compensation_enable = false; - config->correction.correction_enable = false; - config->correction.gain_correction = ADC_GAINCORR_RESETVALUE; - config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE; - config->sample_length = 0; - config->pin_scan.offset_start_scan = 0; - config->pin_scan.inputs_to_scan = 0; -} - -/** - * \brief Sets the ADC window mode - * - * Sets the ADC window mode to a given mode and value range. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] window_mode Window monitor mode to set - * \param[in] window_lower_value Lower window monitor threshold value - * \param[in] window_upper_value Upper window monitor threshold value - */ -void adc_set_window_mode( - struct adc_module *const module_inst, - const enum adc_window_mode window_mode, - const int16_t window_lower_value, - const int16_t window_upper_value) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set window mode */ - adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set lower window monitor threshold value */ - adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set upper window monitor threshold value */ - adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos; -} - -/** -* \internal Configure MUX settings for the analog pins -* -* This function will set the given ADC input pins -* to the analog function in the pinmux, giving -* the ADC access to the analog signal -* -* \param [in] pin AINxx pin to configure -*/ -static inline void _adc_configure_ain_pin(uint32_t pin) -{ -#define PIN_INVALID_ADC_AIN 0xFFFFUL - - /* Pinmapping table for AINxx -> GPIO pin number */ - const uint32_t pinmapping[] = { -#if (SAMD20E) || (SAMD21E)|| (SAMDA1E) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, - PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif SAMR21E - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif SAMR21G - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10C) || (SAMD11C) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10DS) || (SAMD11DS) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10DM) || (SAMD11DM) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#else -# error ADC pin mappings are not defined for this device. -#endif - }; - - uint32_t pin_map_result = PIN_INVALID_ADC_AIN; - - if (pin <= ADC_EXTCHANNEL_MSB) { - pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; - - Assert(pin_map_result != PIN_INVALID_ADC_AIN); - - struct system_pinmux_config config; - system_pinmux_get_config_defaults(&config); - - /* Analog functions are all on MUX setting B */ - config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - config.mux_position = 1; - - system_pinmux_pin_set_config(pin_map_result, &config); - } -} - -/** - * \internal Writes an ADC configuration to the hardware module - * - * Writes out a given ADC module configuration to the hardware module. - * - * \param[out] module_inst Pointer to the ADC software instance struct - * \param[in] config Pointer to configuration struct - * - * \return Status of the configuration procedure - * \retval STATUS_OK The configuration was successful - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided - */ -static enum status_code _adc_set_config( - struct adc_module *const module_inst, - struct adc_config *const config) -{ - uint8_t adjres = 0; - uint32_t resolution = ADC_RESOLUTION_16BIT; - enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE; -#if SAMD20 - uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos); -#endif - - /* Get the hardware module pointer */ - Adc *const adc_module = module_inst->hw; - - /* Configure GCLK channel and enable clock */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->clock_source; - system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(ADC_GCLK_ID); - - /* Setup pinmuxing for analog inputs */ - if (config->pin_scan.inputs_to_scan != 0) { - uint8_t offset = config->pin_scan.offset_start_scan; - uint8_t start_pin = - offset +(uint8_t)config->positive_input; - uint8_t end_pin = - start_pin + config->pin_scan.inputs_to_scan; - - while (start_pin < end_pin) { - _adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input); - start_pin++; - offset++; - } - _adc_configure_ain_pin(config->negative_input); - } else { - _adc_configure_ain_pin(config->positive_input); - _adc_configure_ain_pin(config->negative_input); - } - - /* Configure run in standby */ - adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos); - - /* Configure reference */ - adc_module->REFCTRL.reg = - (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) | - (config->reference); - - /* Set adjusting result and number of samples */ - switch (config->resolution) { - - case ADC_RESOLUTION_CUSTOM: - adjres = config->divide_result; - accumulate = config->accumulate_samples; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_13BIT: - /* Increase resolution by 1 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_4; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_14BIT: - /* Increase resolution by 2 bit */ - adjres = ADC_DIVIDE_RESULT_4; - accumulate = ADC_ACCUMULATE_SAMPLES_16; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#if SAMD20 - /* See $35.1.8 for ADC errata of SAM D20. - The revisions before D have this issue.*/ - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - if(revision_num < REVISON_D_NUM) { - adjres = ADC_DIVIDE_RESULT_8; - } else { - adjres = ADC_DIVIDE_RESULT_2; - } - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_16BIT: - if(revision_num < REVISON_D_NUM) { - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_16; - } else { - adjres = ADC_DIVIDE_RESULT_DISABLE; - } - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#else - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_16BIT: - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_DISABLE; - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#endif - case ADC_RESOLUTION_8BIT: - /* 8-bit result register */ - resolution = ADC_RESOLUTION_8BIT; - break; - case ADC_RESOLUTION_10BIT: - /* 10-bit result register */ - resolution = ADC_RESOLUTION_10BIT; - break; - case ADC_RESOLUTION_12BIT: - /* 12-bit result register */ - resolution = ADC_RESOLUTION_12BIT; - break; - - default: - /* Unknown. Abort. */ - return STATUS_ERR_INVALID_ARG; - } - - adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate; - - /* Check validity of sample length value */ - if (config->sample_length > 63) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Configure sample length */ - adc_module->SAMPCTRL.reg = - (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos); - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure CTRLB */ - adc_module->CTRLB.reg = - config->clock_prescaler | - resolution | - (config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) | - (config->freerunning << ADC_CTRLB_FREERUN_Pos) | - (config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) | - (config->differential_mode << ADC_CTRLB_DIFFMODE_Pos); - - /* Check validity of window thresholds */ - if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) { - switch (resolution) { - case ADC_RESOLUTION_8BIT: - if (config->differential_mode && - (config->window.window_lower_value > 127 || - config->window.window_lower_value < -128 || - config->window.window_upper_value > 127 || - config->window.window_upper_value < -128)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 255 || - config->window.window_upper_value > 255) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_10BIT: - if (config->differential_mode && - (config->window.window_lower_value > 511 || - config->window.window_lower_value < -512 || - config->window.window_upper_value > 511 || - config->window.window_upper_value < -512)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 1023 || - config->window.window_upper_value > 1023) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_12BIT: - if (config->differential_mode && - (config->window.window_lower_value > 2047 || - config->window.window_lower_value < -2048 || - config->window.window_upper_value > 2047 || - config->window.window_upper_value < -2048)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 4095 || - config->window.window_upper_value > 4095) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_16BIT: - if (config->differential_mode && - (config->window.window_lower_value > 32767 || - config->window.window_lower_value < -32768 || - config->window.window_upper_value > 32767 || - config->window.window_upper_value < -32768)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 65535 || - config->window.window_upper_value > 65535) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - } - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure window mode */ - adc_module->WINCTRL.reg = config->window.window_mode; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure lower threshold */ - adc_module->WINLT.reg = - config->window.window_lower_value << ADC_WINLT_WINLT_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure lower threshold */ - adc_module->WINUT.reg = config->window.window_upper_value << - ADC_WINUT_WINUT_Pos; - - uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan; - if (inputs_to_scan > 0) { - /* - * Number of input sources included is the value written to INPUTSCAN - * plus 1. - */ - inputs_to_scan--; - } - - if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || - config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { - /* Invalid number of input pins or input offset */ - return STATUS_ERR_INVALID_ARG; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure pin scan mode and positive and negative input pins */ - adc_module->INPUTCTRL.reg = - config->gain_factor | - (config->pin_scan.offset_start_scan << - ADC_INPUTCTRL_INPUTOFFSET_Pos) | - (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) | - config->negative_input | - config->positive_input; - - /* Configure events */ - adc_module->EVCTRL.reg = config->event_action; - - /* Disable all interrupts */ - adc_module->INTENCLR.reg = - (1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) | - (1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos); - - if (config->correction.correction_enable) { - /* Make sure gain_correction value is valid */ - if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set gain correction value */ - adc_module->GAINCORR.reg = config->correction.gain_correction << - ADC_GAINCORR_GAINCORR_Pos; - } - - /* Make sure offset correction value is valid */ - if (config->correction.offset_correction > 2047 || - config->correction.offset_correction < -2048) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set offset correction value */ - adc_module->OFFSETCORR.reg = config->correction.offset_correction << - ADC_OFFSETCORR_OFFSETCORR_Pos; - } - } - - /* Load in the fixed device ADC calibration constants */ - adc_module->CALIB.reg = - ADC_CALIB_BIAS_CAL( - (*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos) - ) | - ADC_CALIB_LINEARITY_CAL( - (*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos) - ); - - return STATUS_OK; -} - -/** - * \brief Initializes the ADC channel sequence - * - * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one - * automatically after a conversion done, causing the next conversion - * to be done with the positive input equal to MUXPOS + INPUTOFFSET, - * it is scanning continuously one by one even ADC channels are not continuous. - * - * Initializes the ADC channel sequence by the sequence of pin_array. - * - * \param[in] pin_array The array of the Mux selection for the positive ADC input - * \param[in] size The size of pin_array - */ -void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size) -{ - for (int i = 0; i < size; i++) { - _adc_configure_ain_pin(pin_array[i]); - } -} - -/** - * \brief Initializes the ADC - * - * Initializes the ADC device struct and the hardware module based on the - * given configuration struct values. - * - * \param[out] module_inst Pointer to the ADC software instance struct - * \param[in] hw Pointer to the ADC module instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of the initialization procedure. - * \retval STATUS_OK The initialization was successful - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided - * \retval STATUS_BUSY The module is busy with a reset operation - * \retval STATUS_ERR_DENIED The module is enabled - */ -enum status_code adc_init( - struct adc_module *const module_inst, - Adc *hw, - struct adc_config *config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(hw); - Assert(config); - - /* Associate the software module instance with the hardware module */ - module_inst->hw = hw; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC); - - if (hw->CTRLA.reg & ADC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } - - if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } - - /* Store the selected reference for later use */ - module_inst->reference = config->reference; - - /* Make sure bandgap is enabled if requested by the config */ - if (module_inst->reference == ADC_REFERENCE_INT1V) { - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP); - } - -#if ADC_CALLBACK_MODE == true - for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - }; - - module_inst->registered_callback_mask = 0; - module_inst->enabled_callback_mask = 0; - module_inst->remaining_conversions = 0; - module_inst->job_status = STATUS_OK; - - _adc_instances[0] = module_inst; - - if (config->event_action == ADC_EVENT_ACTION_DISABLED && - !config->freerunning) { - module_inst->software_trigger = true; - } else { - module_inst->software_trigger = false; - } -#endif - - /* Write configuration to module */ - return _adc_set_config(module_inst, config); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc_feature.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc_feature.h deleted file mode 100644 index abd7b12ce8f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc_feature.h +++ /dev/null @@ -1,728 +0,0 @@ -/** - * \file - * - * \brief SAM ADC functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef ADC_FEATURE_H_INCLUDED -#define ADC_FEATURE_H_INCLUDED - -/** - * \addtogroup asfdoc_sam0_adc_group - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if ADC_CALLBACK_MODE == true -# include - -#if !defined(__DOXYGEN__) -extern struct adc_module *_adc_instances[ADC_INST_NUM]; -#endif - -/** Forward definition of the device instance. */ -struct adc_module; - -/** Type of the callback functions. */ -typedef void (*adc_callback_t)(struct adc_module *const module); - -/** - * \brief ADC Callback enum - * - * Callback types for ADC callback driver. - * - */ -enum adc_callback { - /** Callback for buffer received. */ - ADC_CALLBACK_READ_BUFFER, - /** Callback when window is hit. */ - ADC_CALLBACK_WINDOW, - /** Callback for error. */ - ADC_CALLBACK_ERROR, -# if !defined(__DOXYGEN__) - /** Number of available callbacks. */ - ADC_CALLBACK_N, -# endif -}; - -#endif - -/** - * \brief ADC reference voltage enum - * - * Enum for the possible reference voltages for the ADC. - * - */ -enum adc_reference { - /** 1.0V voltage reference. */ - ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V, - /** 1/1.48VCC reference. */ - ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, - /** 1/2VCC (only for internal VCC > 2.1V). */ - ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, - /** External reference A. */ - ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, - /** External reference B. */ - ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, -}; - -/** - * \brief ADC clock prescaler enum - * - * Enum for the possible clock prescaler values for the ADC. - * - */ -enum adc_clock_prescaler { - /** ADC clock division factor 4. */ - ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, - /** ADC clock division factor 8. */ - ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, - /** ADC clock division factor 16. */ - ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, - /** ADC clock division factor 32. */ - ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, - /** ADC clock division factor 64. */ - ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, - /** ADC clock division factor 128. */ - ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, - /** ADC clock division factor 256. */ - ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, - /** ADC clock division factor 512. */ - ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512, -}; - -/** - * \brief ADC resolution enum - * - * Enum for the possible resolution values for the ADC. - * - */ -enum adc_resolution { - /** ADC 12-bit resolution. */ - ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT, - /** ADC 16-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT, - /** ADC 10-bit resolution. */ - ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT, - /** ADC 8-bit resolution. */ - ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT, - /** ADC 13-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_13BIT, - /** ADC 14-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_14BIT, - /** ADC 15-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_15BIT, - /** ADC 16-bit result register for use with averaging. When using this mode - * the ADC result register will be set to 16-bit wide, and the number of - * samples to accumulate and the division factor is configured by the - * \ref adc_config.accumulate_samples and \ref adc_config.divide_result - * members in the configuration struct. - */ - ADC_RESOLUTION_CUSTOM, -}; - -/** - * \brief ADC window monitor mode enum - * - * Enum for the possible window monitor modes for the ADC. - * - */ -enum adc_window_mode { - /** No window mode. */ - ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE, - /** RESULT > WINLT. */ - ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1, - /** RESULT < WINUT. */ - ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2, - /** WINLT < RESULT < WINUT. */ - ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3, - /** !(WINLT < RESULT < WINUT). */ - ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4, -}; - -/** - * \brief ADC gain factor selection enum - * - * Enum for the possible gain factor values for the ADC. - * - */ -enum adc_gain_factor { - /** 1x gain. */ - ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X, - /** 2x gain. */ - ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X, - /** 4x gain. */ - ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X, - /** 8x gain. */ - ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X, - /** 16x gain. */ - ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X, - /** 1/2x gain. */ - ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2, -}; - -/** - * \brief ADC event action enum - * - * Enum for the possible actions to take on an incoming event. - * - */ -enum adc_event_action { - /** Event action disabled. */ - ADC_EVENT_ACTION_DISABLED = 0, - /** Flush ADC and start conversion. */ - ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI, - /** Start conversion. */ - ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, -}; - -/** - * \brief ADC positive MUX input selection enum - * - * Enum for the possible positive MUX input selections for the ADC. - * - */ -enum adc_positive_input { - /** ADC0 pin. */ - ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0, - /** ADC1 pin. */ - ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1, - /** ADC2 pin. */ - ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2, - /** ADC3 pin. */ - ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3, - /** ADC4 pin. */ - ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4, - /** ADC5 pin. */ - ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5, - /** ADC6 pin. */ - ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6, - /** ADC7 pin. */ - ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7, - /** ADC8 pin. */ - ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8, - /** ADC9 pin. */ - ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9, - /** ADC10 pin. */ - ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10, - /** ADC11 pin. */ - ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11, - /** ADC12 pin. */ - ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12, - /** ADC13 pin. */ - ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13, - /** ADC14 pin. */ - ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14, - /** ADC15 pin. */ - ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15, - /** ADC16 pin. */ - ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16, - /** ADC17 pin. */ - ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17, - /** ADC18 pin. */ - ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18, - /** ADC19 pin. */ - ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19, - /** Temperature reference. */ - ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, - /** Bandgap voltage. */ - ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, - /** 1/4 scaled core supply. */ - ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, - /** 1/4 scaled I/O supply. */ - ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, - /** DAC input. */ - ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, -}; - -/** - * \brief ADC negative MUX input selection enum - * - * Enum for the possible negative MUX input selections for the ADC. - * - */ -enum adc_negative_input { - /** ADC0 pin. */ - ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0, - /** ADC1 pin. */ - ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1, - /** ADC2 pin. */ - ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2, - /** ADC3 pin. */ - ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3, - /** ADC4 pin. */ - ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4, - /** ADC5 pin. */ - ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5, - /** ADC6 pin. */ - ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6, - /** ADC7 pin. */ - ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7, - /** Internal ground. */ - ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, - /** I/O ground. */ - ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND, -}; - -/** - * \brief ADC number of accumulated samples enum - * - * Enum for the possible numbers of ADC samples to accumulate. - * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM - * resolution setting is used. - * - */ -enum adc_accumulate_samples { - /** No averaging. */ - ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, - /** Average 2 samples. */ - ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, - /** Average 4 samples. */ - ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, - /** Average 8 samples. */ - ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, - /** Average 16 samples. */ - ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, - /** Average 32 samples. */ - ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, - /** Average 64 samples. */ - ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, - /** Average 128 samples. */ - ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, - /** Average 256 samples. */ - ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, - /** Average 512 samples. */ - ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, - /** Average 1024 samples. */ - ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, -}; - -/** - * \brief ADC possible dividers for the result register - * - * Enum for the possible division factors to use when accumulating - * multiple samples. To keep the same resolution for the averaged - * result and the actual input value, the division factor must - * be equal to the number of samples accumulated. This setting is only - * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used. - */ -enum adc_divide_result { - /** Don't divide result register after accumulation. */ - ADC_DIVIDE_RESULT_DISABLE = 0, - /** Divide result register by 2 after accumulation. */ - ADC_DIVIDE_RESULT_2 = 1, - /** Divide result register by 4 after accumulation. */ - ADC_DIVIDE_RESULT_4 = 2, - /** Divide result register by 8 after accumulation. */ - ADC_DIVIDE_RESULT_8 = 3, - /** Divide result register by 16 after accumulation. */ - ADC_DIVIDE_RESULT_16 = 4, - /** Divide result register by 32 after accumulation. */ - ADC_DIVIDE_RESULT_32 = 5, - /** Divide result register by 64 after accumulation. */ - ADC_DIVIDE_RESULT_64 = 6, - /** Divide result register by 128 after accumulation. */ - ADC_DIVIDE_RESULT_128 = 7, -}; - -#if ADC_CALLBACK_MODE == true -/** - * Enum for the possible ADC interrupt flags. - */ -enum adc_interrupt_flag { - /** ADC result ready. */ - ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, - /** Window monitor match. */ - ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, - /** ADC result overwritten before read. */ - ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, -}; -#endif - -/** - * \brief ADC oversampling and decimation enum - * - * Enum for the possible numbers of bits resolution can be increased by when - * using oversampling and decimation. - * - */ -enum adc_oversampling_and_decimation { - /** Don't use oversampling and decimation mode. */ - ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, - /** 1 bit resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_1BIT, - /** 2 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_2BIT, - /** 3 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_3BIT, - /** 4 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_4BIT -}; - -/** - * \brief Window monitor configuration structure - * - * Window monitor configuration structure. - */ -struct adc_window_config { - /** Selected window mode. */ - enum adc_window_mode window_mode; - /** Lower window value. */ - int32_t window_lower_value; - /** Upper window value. */ - int32_t window_upper_value; -}; - -/** - * \brief ADC event enable/disable structure. - * - * Event flags for the ADC module. This is used to enable and - * disable events via \ref adc_enable_events() and \ref adc_disable_events(). - */ -struct adc_events { - /** Enable event generation on conversion done. */ - bool generate_event_on_conversion_done; - /** Enable event generation on window monitor. */ - bool generate_event_on_window_monitor; -}; - -/** - * \brief Gain and offset correction configuration structure - * - * Gain and offset correction configuration structure. - * Part of the \ref adc_config struct and will be initialized by - * \ref adc_get_config_defaults. - */ -struct adc_correction_config { - /** - * Enables correction for gain and offset based on values of gain_correction and - * offset_correction if set to true. - */ - bool correction_enable; - /** - * This value defines how the ADC conversion result is compensated for gain - * error before written to the result register. This is a fractional value, - * 1-bit integer plus an 11-bit fraction, therefore - * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from - * \c 0b010000000000 to \c 0b111111111111. - */ - uint16_t gain_correction; - /** - * This value defines how the ADC conversion result is compensated for - * offset error before written to the result register. This is a 12-bit - * value in two's complement format. - */ - int16_t offset_correction; -}; - -/** - * \brief Pin scan configuration structure - * - * Pin scan configuration structure. Part of the \ref adc_config struct and will - * be initialized by \ref adc_get_config_defaults. - */ -struct adc_pin_scan_config { - /** - * Offset (relative to selected positive input) of the first input pin to be - * used in pin scan mode. - */ - uint8_t offset_start_scan; - /** - * Number of input pins to scan in pin scan mode. A value below two will - * disable pin scan mode. - */ - uint8_t inputs_to_scan; -}; - -/** - * \brief ADC configuration structure - * - * Configuration structure for an ADC instance. This structure should be - * initialized by the \ref adc_get_config_defaults() - * function before being modified by the user application. - */ -struct adc_config { - /** GCLK generator used to clock the peripheral. */ - enum gclk_generator clock_source; - /** Voltage reference. */ - enum adc_reference reference; - /** Clock prescaler. */ - enum adc_clock_prescaler clock_prescaler; - /** Result resolution. */ - enum adc_resolution resolution; - /** Gain factor. */ - enum adc_gain_factor gain_factor; - /** Positive MUX input. */ - enum adc_positive_input positive_input; - /** Negative MUX input. For singled-ended conversion mode, the negative - * input must be connected to ground. This ground could be the internal - * GND, IOGND or an external ground connected to a pin. */ - enum adc_negative_input negative_input; - /** Number of ADC samples to accumulate when using the - * \c ADC_RESOLUTION_CUSTOM mode.Note: if the result width increases, - * result resolution will be changed accordingly. - */ - enum adc_accumulate_samples accumulate_samples; - /** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */ - enum adc_divide_result divide_result; - /** Left adjusted result. */ - bool left_adjust; - /** Enables differential mode if true. - * if false, ADC will run in singled-ended mode. */ - bool differential_mode; - /** Enables free running mode if true. */ - bool freerunning; - /** Enables ADC in standby sleep mode if true. */ - bool run_in_standby; - /** - * Enables reference buffer offset compensation if true. - * This will increase the accuracy of the gain stage, but decreases the input - * impedance; therefore the startup time of the reference must be increased. - */ - bool reference_compensation_enable; - /** - * This value (0-63) control the ADC sampling time in number of half ADC - * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus - * controlling the ADC input impedance. Sampling time is set according to - * the formula: - * Sample time = (sample_length+1) * (ADCclk / 2). - */ - uint8_t sample_length; - /** Window monitor configuration structure. */ - struct adc_window_config window; - /** Gain and offset correction configuration structure. */ - struct adc_correction_config correction; - /** Event action to take on incoming event. */ - enum adc_event_action event_action; - /** Pin scan configuration structure. */ - struct adc_pin_scan_config pin_scan; -}; - -/** - * \brief ADC software device instance structure. - * - * ADC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct adc_module { -#if !defined(__DOXYGEN__) - /** Pointer to ADC hardware module. */ - Adc *hw; - /** Keep reference configuration so we know when enable is called. */ - enum adc_reference reference; -# if ADC_CALLBACK_MODE == true - /** Array to store callback functions. */ - adc_callback_t callback[ADC_CALLBACK_N]; - /** Pointer to buffer used for ADC results. */ - volatile uint16_t *job_buffer; - /** Remaining number of conversions in current job. */ - volatile uint16_t remaining_conversions; - /** Bit mask for callbacks registered. */ - uint8_t registered_callback_mask; - /** Bit mask for callbacks enabled. */ - uint8_t enabled_callback_mask; - /** Holds the status of the ongoing or last conversion job. */ - volatile enum status_code job_status; - /** If software triggering is needed. */ - bool software_trigger; -# endif -#endif -}; - -#if !defined(__DOXYGEN__) - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true if the module synchronization is ongoing - * \retval false if the module has completed synchronization - */ -static inline bool adc_is_syncing( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - - Adc *const adc_module = module_inst->hw; - - if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) { - return true; - } - - return false; -} -#endif - -/** - * \name ADC Gain and Pin Scan Mode - * @{ - */ - -/** - * \brief Sets ADC gain factor - * - * Sets the ADC gain factor to a specified gain setting. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] gain_factor Gain factor value to set - */ -static inline void adc_set_gain( - struct adc_module *const module_inst, - const enum adc_gain_factor gain_factor) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set new gain factor */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) | - (gain_factor); -} - -/** - * \brief Sets the ADC pin scan mode - * - * Configures the pin scan mode of the ADC module. In pin scan mode, the first - * conversion will start at the configured positive input + start_offset. When - * a conversion is done, a conversion will start on the next input, until - * \c inputs_to_scan number of conversions are made. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] inputs_to_scan Number of input pins to perform a conversion on - * (must be two or more) - * \param[in] start_offset Offset of first pin to scan (relative to - * configured positive input) - * - * \return Status of the pin scan configuration set request. - * - * \retval STATUS_OK Pin scan mode has been set successfully - * \retval STATUS_ERR_INVALID_ARG Number of input pins to scan or offset has - * an invalid value - */ -static inline enum status_code adc_set_pin_scan_mode( - struct adc_module *const module_inst, - uint8_t inputs_to_scan, - const uint8_t start_offset) - -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - if (inputs_to_scan > 0) { - /* - * Number of input sources included is the value written to INPUTSCAN - * plus 1. - */ - inputs_to_scan--; - } - - if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || - start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { - /* Invalid number of input pins */ - return STATUS_ERR_INVALID_ARG; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set pin scan mode */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & - ~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) | - (start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) | - (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos); - - return STATUS_OK; -} - -/** - * \brief Disables pin scan mode - * - * Disables pin scan mode. The next conversion will be made on only one pin - * (the configured positive input pin). - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline void adc_disable_pin_scan_mode( - struct adc_module *const module_inst) -{ - /* Disable pin scan mode */ - adc_set_pin_scan_mode(module_inst, 0, 0); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* ADC_FEATURE_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/adc.h deleted file mode 100644 index 1a07cf1da5a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/adc.h +++ /dev/null @@ -1,1140 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef ADC_H_INCLUDED -#define ADC_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_adc_group SAM Analog-to-Digital Converter (ADC) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the device's Analog-to-Digital Converter functionality, for - * the conversion of analog voltages into a corresponding digital form. - * The following driver Application Programming Interface (API) modes are covered by this manual: - * - Polled APIs - * \if ADC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - ADC (Analog-to-Digital Converter) - * - * The following devices can use this module: - * \if DEVICE_SAML21_SUPPORT - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM C20/C21 - * \else - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM DA0/DA1 - * \endif - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_adc_prerequisites - * - \ref asfdoc_sam0_adc_module_overview - * - \ref asfdoc_sam0_adc_special_considerations - * - \ref asfdoc_sam0_adc_extra_info - * - \ref asfdoc_sam0_adc_examples - * - \ref asfdoc_sam0_adc_api_overview - * - * - * \section asfdoc_sam0_adc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_adc_module_overview Module Overview - * - * This driver provides an interface for the Analog-to-Digital conversion - * functions on the device, to convert analog voltages to a corresponding - * digital value. The ADC has up to 12-bit resolution, and is capable of - * \if DEVICE_SAML21_SUPPORT - * converting up to 1,000,000 samples per second (MSPS). - * \else - * converting up to 500K samples per second (KSPS). - * \endif - * - * The ADC has a compare function for accurate monitoring of user defined - * thresholds with minimum software intervention required. - * The ADC may be configured for 8-, 10-, or 12-bit result, reducing the - * conversion time. ADC conversion results are provided left or right adjusted - * which eases calculation when the result is represented as a signed integer. - * - * The input selection is flexible, and both single-ended and differential - * measurements can be made. For differential measurements, an optional gain - * stage is available to increase the dynamic range. In addition, several - * internal signal inputs are available. The ADC can provide both signed and - * unsigned results. - * - * The ADC measurements can either be started by application software or an - * incoming event from another peripheral in the device, and both internal and - * external reference voltages can be selected. - * - * \note Internal references will be enabled by the driver, but not disabled. - * Any reference not used by the application should be disabled by the application. - * - * A simplified block diagram of the ADC can be seen in - * \ref asfdoc_sam0_adc_module_block_diagram "the figure below". - * - * \anchor asfdoc_sam0_adc_module_block_diagram - * \dot - * digraph overview { - * splines = false; - * rankdir=LR; - * - * mux1 [label="Positive input", shape=box]; - * mux2 [label="Negative input", shape=box]; - * - * - * mux3 [label="Reference", shape=box]; - * - * adc [label="ADC", shape=polygon, sides=5, orientation=90, distortion=-0.6, style=filled, fillcolor=darkolivegreen1, height=1, width=1]; - * prescaler [label="PRESCALER", shape=box, style=filled, fillcolor=lightblue]; - * - * mux1 -> adc; - * mux2 -> adc; - * mux3 -> adc:sw; - * prescaler -> adc; - * - * postproc [label="Post processing", shape=box]; - * result [label="RESULT", shape=box, style=filled, fillcolor=lightblue]; - * - * adc:e -> postproc:w; - * postproc:e -> result:w; - * - * {rank=same; mux1 mux2} - * {rank=same; prescaler adc} - * - * } - * \enddot - * - * - * \subsection asfdoc_sam0_adc_module_overview_prescaler Sample Clock Prescaler - * The ADC features a prescaler, which enables conversion at lower clock rates - * than the input Generic Clock to the ADC module. This feature can be used to - * lower the synchronization time of the digital interface to the ADC module - * via a high speed Generic Clock frequency, while still allowing the ADC - * sampling rate to be reduced. - * - * \subsection asfdoc_sam0_adc_module_overview_resolution ADC Resolution - * The ADC supports full 8-, 10-, or 12-bit resolution. Hardware - * oversampling and decimation can be used to increase the - * effective resolution at the expense of throughput. Using oversampling and - * decimation mode the ADC resolution is increased from 12-bit to an effective - * 13-, 14-, 15-, or 16-bit. In these modes the conversion rate is reduced, as - * a greater number of samples is used to achieve the increased resolution. The - * available resolutions and effective conversion rate is listed in - * \ref asfdoc_sam0_adc_module_conversion_rate "the table below". - * - * \anchor asfdoc_sam0_adc_module_conversion_rate - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Effective ADC Conversion Speed Using Oversampling
ResolutionEffective conversion rate
13-bitConversion rate divided by 4
14-bitConversion rate divided by 16
15-bitConversion rate divided by 64
16-bitConversion rate divided by 256
- * - * \subsection asfdoc_sam0_adc_module_overview_conversion Conversion Modes - * ADC conversions can be software triggered on demand by the user application, - * if continuous sampling is not required. It is also possible to configure the - * ADC in free running mode, where new conversions are started as soon as the - * previous conversion is completed, or configure the ADC to scan across a - * number of input pins (see \ref asfdoc_sam0_adc_module_overview_pin_scan). - * - * \subsection asfdoc_sam0_adc_module_overview_diff_mode Differential and Single-ended Conversion - * The ADC has two conversion modes; differential and single-ended. When - * measuring signals where the positive input pin is always at a higher voltage - * than the negative input pin, the single-ended conversion mode should be used - * in order to achieve a full 12-bit output resolution. - * - * If however the positive input pin voltage may drop below the negative input - * pin the signed differential mode should be used. - * - * \subsection asfdoc_sam0_adc_module_overview_sample_time Sample Time - * The sample time for each ADC conversion is configurable as a number of half - * prescaled ADC clock cycles (depending on the prescaler value), allowing the - * user application to achieve faster or slower sampling depending on the - * source impedance of the ADC input channels. For applications with high - * impedance inputs the sample time can be increased to give the ADC an adequate - * time to sample and convert the input channel. - * - * The resulting sampling time is given by the following equation: - * \f[ - * t_{SAMPLE} = (sample\_length+1) \times \frac{ADC_{CLK}} {2} - * \f] - * - * \subsection asfdoc_sam0_adc_module_overview_averaging Averaging - * The ADC can be configured to trade conversion speed for accuracy by averaging - * multiple samples in hardware. This feature is suitable when operating in - * noisy conditions. - * - * You can specify any number of samples to accumulate (up to 1024) and the - * divide ratio to use (up to divide by 128). To modify these settings the - * ADC_RESOLUTION_CUSTOM needs to be set as the resolution. When this is set - * the number of samples to accumulate and the division ratio can be set by - * the configuration struct members \ref adc_config.accumulate_samples and - * \ref adc_config.divide_result. When using this mode the ADC result register - * will be set to be 16-bit wide to accommodate the larger result sizes - * produced by the accumulator. - * - * The effective ADC conversion rate will be reduced by a factor of the number - * of accumulated samples; - * however, the effective resolution will be increased according to - * \ref asfdoc_sam0_adc_module_hw_av_resolution "the table below". - * - * \anchor asfdoc_sam0_adc_module_hw_av_resolution - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Effective ADC Resolution From Various Hardware Averaging Modes
Number of samples
Final result
112-bit
213-bit
414-bit
815-bit
1616-bit
3216-bit
6416-bit
12816-bit
25616-bit
51216-bit
102416-bit
- * - * - * \subsection asfdoc_sam0_adc_module_overview_offset_corr Offset and Gain Correction - * Inherent gain and offset errors affect the absolute accuracy of the ADC. - * - * The offset error is defined as the deviation of the ADC's actual transfer - * function from ideal straight line at zero input voltage. - * - * The gain error is defined as the deviation of the last output step's - * midpoint from the ideal straight line, after compensating for offset error. - * - * The offset correction value is subtracted from the converted data before the - * result is ready. The gain correction value is multiplied with the offset - * corrected value. - * - * The equation for both offset and gain error compensation is shown below: - * \f[ - * ADC_{RESULT} = (VALUE_{CONV} + CORR_{OFFSET}) \times CORR_{GAIN} - * \f] - * - * When enabled, a given set of offset and gain correction values can be applied - * to the sampled data in hardware, giving a corrected stream of sample data to - * the user application at the cost of an increased sample latency. - * - * In single conversion, a latency of 13 ADC Generic Clock cycles is added for - * the final sample result availability. As the correction time is always less - * than the propagation delay, in free running mode this latency appears only - * during the first conversion. After the first conversion is complete, future - * conversion results are available at the defined sampling rate. - * - * \subsection asfdoc_sam0_adc_module_overview_pin_scan Pin Scan - * In pin scan mode, the first ADC conversion will begin from the configured - * positive channel, plus the requested starting offset. When the first - * conversion is completed, the next conversion will start at the next positive - * input channel and so on, until all requested pins to scan have been sampled - * and converted. - * SAM L21 has automatic sequences feature instead of pin scan mode. In automatic - * sequence mode, all of 32 positives inputs can be included in a sequence. The - * sequence starts from the lowest input, and go to the next enabled input - * automatically. - * - * Pin scanning gives a simple mechanism to sample a large number of physical - * input channel samples, using a single physical ADC channel. - * - * \subsection asfdoc_sam0_adc_module_overview_window_monitor Window Monitor - * The ADC module window monitor function can be used to automatically compare - * the conversion result against a preconfigured pair of upper and lower - * threshold values. - * - * The threshold values are evaluated differently, depending on whether - * differential or single-ended mode is selected. In differential mode, the - * upper and lower thresholds are evaluated as signed values for the comparison, - * while in single-ended mode the comparisons are made as a set of unsigned - * values. - * - * The significant bits of the lower window monitor threshold and upper window - * monitor threshold values are user-configurable, and follow the overall ADC - * sampling bit precision set when the ADC is configured by the user application. - * For example, only the eight lower bits of the window threshold values will be - * compared to the sampled data whilst the ADC is configured in 8-bit mode. - * In addition, if using differential mode, the 8th bit will be considered as - * the sign bit even if bit 9 is zero. - * - * \subsection asfdoc_sam0_adc_module_overview_events Events - * Event generation and event actions are configurable in the ADC. - * - * The ADC has two actions that can be triggered upon event reception: - * \li Start conversion - * \li Flush pipeline and start conversion - * - * The ADC can generate two events: - * \li Window monitor - * \li Result ready - * - * If the event actions are enabled in the configuration, any incoming event - * will trigger the action. - * - * If the window monitor event is enabled, an event will be generated - * when the configured window condition is detected. - * - * If the result ready event is enabled, an event will be generated when a - * conversion is completed. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * - * \section asfdoc_sam0_adc_special_considerations Special Considerations - * - * An integrated analog temperature sensor is available for use with the ADC. - * The bandgap voltage, as well as the scaled I/O and core voltages can also be - * measured by the ADC. For internal ADC inputs, the internal source(s) may need - * to be manually enabled by the user application before they can be measured. - * - * - * \section asfdoc_sam0_adc_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_adc_extra. This includes: - * - \ref asfdoc_sam0_adc_extra_acronyms - * - \ref asfdoc_sam0_adc_extra_dependencies - * - \ref asfdoc_sam0_adc_extra_errata - * - \ref asfdoc_sam0_adc_extra_history - * - * - * \section asfdoc_sam0_adc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_adc_exqsg. - * - * - * \section asfdoc_sam0_adc_api_overview API Overview - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \name Module Status Flags - * - * ADC status flags, returned by \ref adc_get_status() and cleared by - * \ref adc_clear_status(). - * - * @{ - */ - -/** ADC result ready. */ -#define ADC_STATUS_RESULT_READY (1UL << 0) -/** Window monitor match. */ -#define ADC_STATUS_WINDOW (1UL << 1) -/** ADC result overwritten before read. */ -#define ADC_STATUS_OVERRUN (1UL << 2) - -/** @} */ - -#if ADC_CALLBACK_MODE == true -# if (ADC_INST_NUM > 1) -# define _ADC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_ADC##n, -/** - * \internal Get the interrupt vector for the given device instance - * - * \param[in] The ADC module instance number - * - * \return Interrupt vector for of the given ADC module instance. - */ -static enum system_interrupt_vector _adc_interrupt_get_interrupt_vector( - uint32_t inst_num) -{ - static uint8_t adc_interrupt_vectors[ADC_INST_NUM] = { - MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_VECT_NUM, 0) - }; - - return (enum system_interrupt_vector)adc_interrupt_vectors[inst_num]; -} -# endif -#endif - -#if !defined(__DOXYGEN__) -uint8_t _adc_get_inst_index( - Adc *const hw); -#endif - -/** - * \name Driver Initialization and Configuration - * @{ - */ -enum status_code adc_init( - struct adc_module *const module_inst, - Adc *hw, - struct adc_config *config); - -void adc_get_config_defaults( - struct adc_config *const config); - -#if (SAMD) || (SAMR21) -void adc_regular_ain_channel( - uint32_t *pin_array, uint8_t size); -#endif - -/** @} */ - -/** - * \name Status Management - * @{ - */ - -/** - * \brief Retrieves the current module status. - * - * Retrieves the status of the module, giving overall state information. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * - * \return Bitmask of \c ADC_STATUS_* flags. - * - * \retval ADC_STATUS_RESULT_READY ADC result is ready to be read - * \retval ADC_STATUS_WINDOW ADC has detected a value inside the set - * window range - * \retval ADC_STATUS_OVERRUN ADC result has overrun - */ -static inline uint32_t adc_get_status( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - uint32_t int_flags = adc_module->INTFLAG.reg; - - uint32_t status_flags = 0; - - /* Check for ADC Result Ready */ - if (int_flags & ADC_INTFLAG_RESRDY) { - status_flags |= ADC_STATUS_RESULT_READY; - } - - /* Check for ADC Window Match */ - if (int_flags & ADC_INTFLAG_WINMON) { - status_flags |= ADC_STATUS_WINDOW; - } - - /* Check for ADC Overrun */ - if (int_flags & ADC_INTFLAG_OVERRUN) { - status_flags |= ADC_STATUS_OVERRUN; - } - - return status_flags; -} - -/** - * \brief Clears a module status flag. - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] status_flags Bitmask of \c ADC_STATUS_* flags to clear - */ -static inline void adc_clear_status( - struct adc_module *const module_inst, - const uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - uint32_t int_flags = 0; - - /* Check for ADC Result Ready */ - if (status_flags & ADC_STATUS_RESULT_READY) { - int_flags |= ADC_INTFLAG_RESRDY; - } - - /* Check for ADC Window Match */ - if (status_flags & ADC_STATUS_WINDOW) { - int_flags |= ADC_INTFLAG_WINMON; - } - - /* Check for ADC Overrun */ - if (status_flags & ADC_STATUS_OVERRUN) { - int_flags |= ADC_INTFLAG_OVERRUN; - } - - /* Clear interrupt flag */ - adc_module->INTFLAG.reg = int_flags; -} -/** @} */ - -/** - * \name Enable, Disable, and Reset ADC Module, Start Conversion and Read Result - * @{ - */ - -/** - * \brief Enables the ADC module. - * - * Enables an ADC module that has previously been configured. If any internal reference - * is selected it will be enabled. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline enum status_code adc_enable( - struct adc_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - -#if ADC_CALLBACK_MODE == true -# if (ADC_INST_NUM > 1) - system_interrupt_enable(_adc_interrupt_get_interrupt_vector( - _adc_get_inst_index(adc_module))); -# elif (SAMC20) - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC0); -# else - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC); -# endif -#endif - - adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; -} - -/** - * \brief Disables the ADC module. - * - * Disables an ADC module that was previously enabled. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline enum status_code adc_disable( - struct adc_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - -#if ADC_CALLBACK_MODE == true -# if (ADC_INST_NUM > 1) - system_interrupt_disable(_adc_interrupt_get_interrupt_vector( - _adc_get_inst_index(adc_module))); -# elif (SAMC20) - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC0); -# else - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC); -# endif -#endif - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; -} - -/** - * \brief Resets the ADC module. - * - * Resets an ADC module, clearing all module state and registers to their - * default values. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline enum status_code adc_reset( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - /* Disable to make sure the pipeline is flushed before reset */ - adc_disable(module_inst); - - /* Software reset the module */ - adc_module->CTRLA.reg |= ADC_CTRLA_SWRST; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; -} - - -/** - * \brief Enables an ADC event input or output. - * - * Enables one or more input or output events to or from the ADC module. See - * \ref adc_events "Struct adc_events" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the ADC peripheral - * \param[in] events Struct containing flags of events to enable - */ -static inline void adc_enable_events( - struct adc_module *const module_inst, - struct adc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Adc *const adc_module = module_inst->hw; - - uint32_t event_mask = 0; - - /* Configure Window Monitor event */ - if (events->generate_event_on_window_monitor) { - event_mask |= ADC_EVCTRL_WINMONEO; - } - - /* Configure Result Ready event */ - if (events->generate_event_on_conversion_done) { - event_mask |= ADC_EVCTRL_RESRDYEO; - } - - adc_module->EVCTRL.reg |= event_mask; -} - -/** - * \brief Disables an ADC event input or output. - * - * Disables one or more input or output events to or from the ADC module. See - * \ref adc_events "Struct adc_events" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the ADC peripheral - * \param[in] events Struct containing flags of events to disable - */ -static inline void adc_disable_events( - struct adc_module *const module_inst, - struct adc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Adc *const adc_module = module_inst->hw; - - uint32_t event_mask = 0; - - /* Configure Window Monitor event */ - if (events->generate_event_on_window_monitor) { - event_mask |= ADC_EVCTRL_WINMONEO; - } - - /* Configure Result Ready event */ - if (events->generate_event_on_conversion_done) { - event_mask |= ADC_EVCTRL_RESRDYEO; - } - - adc_module->EVCTRL.reg &= ~event_mask; -} - -/** - * \brief Starts an ADC conversion. - * - * Starts a new ADC conversion. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline void adc_start_conversion( - struct adc_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - adc_module->SWTRIG.reg |= ADC_SWTRIG_START; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} - -/** - * \brief Reads the ADC result. - * - * Reads the result from an ADC conversion that was previously started. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[out] result Pointer to store the result value in - * - * \return Status of the ADC read request. - * \retval STATUS_OK The result was retrieved successfully - * \retval STATUS_BUSY A conversion result was not ready - * \retval STATUS_ERR_OVERFLOW The result register has been overwritten by the - * ADC module before the result was read by the software - */ -static inline enum status_code adc_read( - struct adc_module *const module_inst, - uint16_t *result) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(result); - - if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) { - /* Result not ready */ - return STATUS_BUSY; - } - - Adc *const adc_module = module_inst->hw; - -#if (SAMD) || (SAMR21) - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -#endif - - /* Get ADC result */ - *result = adc_module->RESULT.reg; - - /* Reset ready flag */ - adc_clear_status(module_inst, ADC_STATUS_RESULT_READY); - - if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) { - adc_clear_status(module_inst, ADC_STATUS_OVERRUN); - return STATUS_ERR_OVERFLOW; - } - - return STATUS_OK; -} - -/** @} */ - -/** - * \name Runtime Changes of ADC Module - * @{ - */ - -/** - * \brief Flushes the ADC pipeline. - * - * Flushes the pipeline and restarts the ADC clock on the next peripheral clock - * edge. All conversions in progress will be lost. When flush is complete, the - * module will resume where it left off. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline void adc_flush( - struct adc_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} -void adc_set_window_mode( - struct adc_module *const module_inst, - const enum adc_window_mode window_mode, - const int16_t window_lower_value, - const int16_t window_upper_value); - -/** - * \brief Sets positive ADC input pin. - * - * Sets the positive ADC input pin selection. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] positive_input Positive input pin - */ -static inline void adc_set_positive_input( - struct adc_module *const module_inst, - const enum adc_positive_input positive_input) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set positive input pin */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) | - (positive_input); - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} - - -/** - * \brief Sets negative ADC input pin for differential mode. - * - * Sets the negative ADC input pin, when the ADC is configured in differential - * mode. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] negative_input Negative input pin - */ -static inline void adc_set_negative_input( - struct adc_module *const module_inst, - const enum adc_negative_input negative_input) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set negative input pin */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) | - (negative_input); - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} - -/** @} */ - -#if ADC_CALLBACK_MODE == true -/** - * \name Enable and Disable Interrupts - * @{ - */ - -/** - * \brief Enable interrupt. - * - * Enable the given interrupt request from the ADC module. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] interrupt Interrupt to enable - */ -static inline void adc_enable_interrupt(struct adc_module *const module_inst, - enum adc_interrupt_flag interrupt) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - /* Enable interrupt */ - adc_module->INTENSET.reg = interrupt; -} - -/** - * \brief Disable interrupt. - * - * Disable the given interrupt request from the ADC module. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] interrupt Interrupt to disable - */ -static inline void adc_disable_interrupt(struct adc_module *const module_inst, - enum adc_interrupt_flag interrupt) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - /* Enable interrupt */ - adc_module->INTENCLR.reg = interrupt; -} - -/** @} */ -#endif /* ADC_CALLBACK_MODE == true */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - - -/** - * \page asfdoc_sam0_adc_extra Extra Information for ADC Driver - * - * \section asfdoc_sam0_adc_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
ADCAnalog-to-Digital Converter
DACDigital-to-Analog Converter
LSBLeast Significant Bit
MSBMost Significant Bit
DMADirect Memory Access
- * - * - * \section asfdoc_sam0_adc_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_adc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_adc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * \if DEVICE_SAML21_SUPPORT - * - * - * - * \else - * - * - * - * - * - * - * - * - * - * - * - * - * \endif - *
Changelog
Initial Release
Added support for SAMR21
Added support for SAMD21 and new DMA quick start guide
Added ADC calibration constant loading from the device signature - * row when the module is initialized
Initial Release
- */ - -/** - * \page asfdoc_sam0_adc_exqsg Examples for ADC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_adc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_adc_basic_use_case - * \if ADC_CALLBACK_MODE - * - \subpage asfdoc_sam0_adc_basic_use_case_callback - * \endif - * - \subpage asfdoc_sam0_adc_dma_use_case - * - * \page asfdoc_sam0_adc_document_revision_history Document Revision History - * - * - * - * - * \if DEVICE_SAML21_SUPPORT - * - * - * - * - * - * \else - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * \endif - *
Doc. Rev. - * Date - * Comments - *
42451A07/2015Initial document release
42109E04/2015Added support for SAMDAx.
42109D12/2014Added support for SAMR21 and SAMD10/D11
42109C01/2014Added support for SAMD21
42109B06/2013Added additional documentation on the event system. Corrected - * documentation typos.
42109A06/2013Initial release
- */ - -#endif /* ADC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac.c deleted file mode 100644 index ef476f1b97c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac.c +++ /dev/null @@ -1,774 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Digital-to-Analog Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "dac.h" -#include -#include - -/** - * \internal Writes a DAC configuration to the hardware module. - * - * Writes out a given configuration to the hardware module. - * - * \param[out] module_inst Pointer to the DAC software instance struct - * \param[in] config Pointer to the configuration struct - * - */ -static void _dac_set_config( - struct dac_module *const module_inst, - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(config); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Set selected DAC output to be enabled when enabling the module */ - module_inst->output = config->output; - module_inst->start_on_event = false; - - uint32_t new_ctrla = 0; - uint32_t new_ctrlb = 0; - - /* Enable DAC in standby sleep mode if configured */ - if (config->run_in_standby) { - new_ctrla |= DAC_CTRLA_RUNSTDBY; - } - - /* Set reference voltage */ - new_ctrlb |= config->reference; - - /* Left adjust data if configured */ - if (config->left_adjust) { - new_ctrlb |= DAC_CTRLB_LEFTADJ; - } - -#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION - /* Bypass DATABUF write protection if configured */ - if (config->databuf_protection_bypass) { - new_ctrlb |= DAC_CTRLB_BDWP; - } -#endif - - /* Voltage pump disable if configured */ - if (config->voltage_pump_disable) { - new_ctrlb |= DAC_CTRLB_VPD; - } - - /* Apply the new configuration to the hardware module */ - dac_module->CTRLA.reg = new_ctrla; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - dac_module->CTRLB.reg = new_ctrlb; -} - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] dev_inst Pointer to the DAC software instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true If the module synchronization is ongoing - * \retval false If the module has completed synchronization - */ -bool dac_is_syncing( - struct dac_module *const dev_inst) -{ - /* Sanity check arguments */ - Assert(dev_inst); - - Dac *const dac_module = dev_inst->hw; - -#if (SAMC21) - if (dac_module->SYNCBUSY.reg) { -#else - if (dac_module->STATUS.reg & DAC_STATUS_SYNCBUSY) { -#endif - return true; - } - - return false; -} - -/** - * \brief Initializes a DAC configuration structure to defaults. - * - * Initializes a given DAC configuration structure to a set of - * known default values. This function should be called on any new - * instance of the configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li 1V from internal bandgap reference - * \li Drive the DAC output to the VOUT pin - * \li Right adjust data - * \li GCLK generator 0 (GCLK main) clock source - * \li The output buffer is disabled when the chip enters STANDBY sleep - * mode - * - * \param[out] config Configuration structure to initialize to default values - */ -void dac_get_config_defaults( - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->reference = DAC_REFERENCE_INT1V; - config->output = DAC_OUTPUT_EXTERNAL; - config->left_adjust = false; -#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION - config->databuf_protection_bypass = false; -#endif - config->voltage_pump_disable = false; - config->clock_source = GCLK_GENERATOR_0; - config->run_in_standby = false; -#if (SAMC21) - config->dither_mode = false; -#endif -} - -/** - * \brief Initialize the DAC device struct. - * - * Use this function to initialize the Digital to Analog Converter. Resets the - * underlying hardware module and configures it. - * - * \note The DAC channel must be configured separately. - * - * \param[out] module_inst Pointer to the DAC software instance struct - * \param[in] module Pointer to the DAC module instance - * \param[in] config Pointer to the config struct, created by the user - * application - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - */ -enum status_code dac_init( - struct dac_module *const module_inst, - Dac *const module, - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module); - Assert(config); - - /* Initialize device instance */ - module_inst->hw = module; - - /* Turn on the digital interface clock */ -#if (SAMC21) - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC); -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_DAC); -#endif - - /* Check if module is enabled. */ - if (module->CTRLA.reg & DAC_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress. */ - if (module->CTRLA.reg & DAC_CTRLA_SWRST) { - return STATUS_BUSY; - } - - /* Configure GCLK channel and enable clock */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->clock_source; - system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(DAC_GCLK_ID); - - /* MUX the DAC VOUT pin */ - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - /* Set up the DAC VOUT pin */ - pin_conf.mux_position = MUX_PA02B_DAC_VOUT; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT, &pin_conf); - - /* Write configuration to module */ - _dac_set_config(module_inst, config); - - /* Store reference selection for later use */ - module_inst->reference = config->reference; - -#if DAC_CALLBACK_MODE == true - for (uint8_t i = 0; i < DAC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - }; - - _dac_instances[0] = module_inst; -#endif - - return STATUS_OK; -} - -/** - * \brief Resets the DAC module. - * - * This function will reset the DAC module to its power on default values and - * disable it. - * - * \param[in] module_inst Pointer to the DAC software instance struct - */ -void dac_reset( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - /* Software reset the module */ - dac_module->CTRLA.reg |= DAC_CTRLA_SWRST; -} - -/** - * \brief Enable the DAC module. - * - * Enables the DAC interface and the selected output. If any internal reference - * is selected it will be enabled. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * - */ -void dac_enable( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Enable selected output */ - dac_module->CTRLB.reg |= module_inst->output; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - /* Enable the module */ - dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE; - - /* Enable internal bandgap reference if selected in the configuration */ - if (module_inst->reference == DAC_REFERENCE_INT1V) { -#if (SAMC21) - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT); - } - - if(dac_module->CTRLA.reg & DAC_CTRLA_ENABLE) { - while(! (dac_module->STATUS.reg & DAC_STATUS_READY)) { - }; - } -#else - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP); - } - -#endif -} - -/** - * \brief Disable the DAC module. - * - * Disables the DAC interface and the output buffer. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * - */ -void dac_disable( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Wait until the synchronization is complete */ - while (dac_is_syncing(module_inst)) { - }; - - /* Disable DAC */ - dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE; -} - -/** - * \brief Enables a DAC event input or output. - * - * Enables one or more input or output events to or from the DAC module. See - * \ref dac_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the DAC peripheral - * \param[in] events Struct containing flags of events to enable - */ -void dac_enable_events( - struct dac_module *const module_inst, - struct dac_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Dac *const dac_module = module_inst->hw; - - uint32_t event_mask = 0; - -#if(SAMC21) - /* Configure Enable Inversion of input event */ - if (events->generate_event_on_chan_falling_edge) { - event_mask |= DAC_EVCTRL_INVEI; - } -#endif - - /* Configure Buffer Empty event */ - if (events->generate_event_on_buffer_empty) { - event_mask |= DAC_EVCTRL_EMPTYEO; - } - - /* Configure Conversion Start event */ - if (events->on_event_start_conversion) { - event_mask |= DAC_EVCTRL_STARTEI; - module_inst->start_on_event = true; - } - - dac_module->EVCTRL.reg |= event_mask; -} - -/** - * \brief Disables a DAC event input or output. - * - * Disables one or more input or output events to or from the DAC module. See - * \ref dac_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the DAC peripheral - * \param[in] events Struct containing flags of events to disable - */ -void dac_disable_events( - struct dac_module *const module_inst, - struct dac_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Dac *const dac_module = module_inst->hw; - - uint32_t event_mask = 0; - - /* Configure Buffer Empty event */ - if (events->generate_event_on_buffer_empty) { - event_mask |= DAC_EVCTRL_EMPTYEO; - } - - /* Configure Conversion Start event */ - if (events->on_event_start_conversion) { - event_mask |= DAC_EVCTRL_STARTEI; - module_inst->start_on_event = false; - } - - dac_module->EVCTRL.reg &= ~event_mask; -} - -/** - * \brief Initializes a DAC channel configuration structure to defaults. - * - * Initializes a given DAC channel configuration structure to a set of - * known default values. This function should be called on any new - * instance of the configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Start Conversion Event Input enabled - * \li Start Data Buffer Empty Event Output disabled - * - * \param[out] config Configuration structure to initialize to default values - */ -void dac_chan_get_config_defaults( - struct dac_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); -} - -/** - * \brief Writes a DAC channel configuration to the hardware module. - * - * Writes a given channel configuration to the hardware module. - * - * \note The DAC device instance structure must be initialized before calling - * this function. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to configure - * \param[in] config Pointer to the configuration struct - * - */ -void dac_chan_set_config( - struct dac_module *const module_inst, - const enum dac_channel channel, - struct dac_chan_config *const config) -{ - /* No channel support yet */ - UNUSED(channel); -} - -/** - * \brief Enable a DAC channel. - * - * Enables the selected DAC channel. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to enable - * - */ -void dac_chan_enable( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* No channel support yet */ - UNUSED(channel); -} - -/** - * \brief Disable a DAC channel. - * - * Disables the selected DAC channel. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to disable - * - */ -void dac_chan_disable( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* No channel support yet */ - UNUSED(channel); -} - -/** - * \brief Enable the output buffer. - * - * Enables the output buffer and drives the DAC output to the VOUT pin. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel DAC channel to alter - */ -void dac_chan_enable_output_buffer( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* No channel support yet */ - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* Enable output buffer */ - dac_module->CTRLB.reg |= DAC_OUTPUT_EXTERNAL; -} - -/** - * \brief Disable the output buffer. - * - * Disables the output buffer. - * - * \note The output buffer(s) should be disabled when a channel's output is not - * currently needed, as it will draw current even if the system is in - * sleep mode. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel DAC channel to alter - */ -void dac_chan_disable_output_buffer( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* Sanity check arguments*/ - Assert(module_inst); - Assert(module_inst->hw); - - /* No channel support yet */ - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* Disable output buffer */ - dac_module->CTRLB.reg &= ~DAC_OUTPUT_EXTERNAL; -} - -/** - * \brief Write to the DAC. - * - * This function writes to the DATA or DATABUF register. - * If the conversion is not event-triggered, the data will be written to - * the DATA register and the conversion will start. - * If the conversion is event-triggered, the data will be written to DATABUF - * and transferred to the DATA register and converted when a Start Conversion - * Event is issued. - * Conversion data must be right or left adjusted according to configuration - * settings. - * \note To be event triggered, the enable_start_on_event must be - * enabled in the configuration. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] channel DAC channel to write to - * \param[in] data Conversion data - * - * \return Status of the operation. - * \retval STATUS_OK If the data was written - */ -enum status_code dac_chan_write( - struct dac_module *const module_inst, - enum dac_channel channel, - const uint16_t data) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* No channel support yet */ - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* Wait until the synchronization is complete */ - while (dac_is_syncing(module_inst)) { - }; - - if (module_inst->start_on_event) { - /* Write the new value to the buffered DAC data register */ - dac_module->DATABUF.reg = data; - } else { - /* Write the new value to the DAC data register */ - dac_module->DATA.reg = data; - } - - return STATUS_OK; -} - -/** - * \brief Write to the DAC. - * - * This function converts a specific number of digital data. - * The conversion should be event-triggered, the data will be written to DATABUF - * and transferred to the DATA register and converted when a Start Conversion - * Event is issued. - * Conversion data must be right or left adjusted according to configuration - * settings. - * \note To be event triggered, the enable_start_on_event must be - * enabled in the configuration. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] channel DAC channel to write to - * \param[in] buffer Pointer to the digital data write buffer to be converted - * \param[in] length Length of the write buffer - * - * \return Status of the operation. - * \retval STATUS_OK If the data was written or no data conversion required - * \retval STATUS_ERR_UNSUPPORTED_DEV The DAC is not configured as using event trigger - * \retval STATUS_BUSY The DAC is busy to convert - */ -enum status_code dac_chan_write_buffer_wait( - struct dac_module *const module_inst, - enum dac_channel channel, - uint16_t *buffer, - uint32_t length) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* No channel support yet */ - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* Wait until the synchronization is complete */ - while (dac_is_syncing(module_inst)) { - }; - - /* Zero length request */ - if (length == 0) { - /* No data to be converted */ - return STATUS_OK; - } - -#if DAC_CALLBACK_MODE == true - /* Check if busy */ - if (module_inst->job_status == STATUS_BUSY) { - return STATUS_BUSY; - } -#endif - - /* Only support event triggered conversion */ - if (module_inst->start_on_event == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Blocks while buffer is being transferred */ - while (length--) { - /* Convert one data */ - dac_chan_write(module_inst, channel, buffer[length]); - - /* Wait until Transmit is complete or timeout */ - for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) { - if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY) { - break; - } else if (i == DAC_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - } - - return STATUS_OK; -} - -/** - * \brief Retrieves the current module status - * - * Checks the status of the module and returns it as a bitmask of status - * flags. - * - * \param[in] module_inst Pointer to the DAC software device struct - * - * \return Bitmask of status flags. - * - * \retval DAC_STATUS_CHANNEL_0_EMPTY Data has been transferred from DATABUF - * to DATA by a start conversion event - * and DATABUF is ready for new data - * \retval DAC_STATUS_CHANNEL_0_UNDERRUN A start conversion event has occurred - * when DATABUF is empty - * - */ -uint32_t dac_get_status( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - uint8_t intflags = dac_module->INTFLAG.reg; - uint32_t status_flags = 0; - - if (intflags & DAC_INTFLAG_EMPTY) { - status_flags |= DAC_STATUS_CHANNEL_0_EMPTY; - } - - if (intflags & DAC_INTFLAG_UNDERRUN) { - status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN; - } - - return status_flags; -} - -/** - * \brief Clears a module status flag - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] status_flags Bit mask of status flags to clear - * - */ -void dac_clear_status( - struct dac_module *const module_inst, - uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - uint32_t intflags = 0; - - if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) { - intflags |= DAC_INTFLAG_EMPTY; - } - - if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) { - intflags |= DAC_INTFLAG_UNDERRUN; - } - - dac_module->INTFLAG.reg = intflags; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac_feature.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac_feature.h deleted file mode 100644 index 8203d7ee091..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac_feature.h +++ /dev/null @@ -1,635 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Digital-to-Analog Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DAC_FEATURE_H_INCLUDED -#define DAC_FEATURE_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_dac_group SAM Digital-to-Analog Driver (DAC) - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the conversion of - * digital values to analog voltage. The following driver API modes are covered - * by this manual: - * - * - Polled APIs - * \if DAC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripherals are used by this module: - * - DAC (Digital-to-Analog Converter) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM DA0/DA1 - * - Atmel | SMART SAM C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_dac_prerequisites - * - \ref asfdoc_sam0_dac_module_overview - * - \ref asfdoc_sam0_dac_special_considerations - * - \ref asfdoc_sam0_dac_extra_info - * - \ref asfdoc_sam0_dac_examples - * - \ref asfdoc_sam0_dac_api_overview - * - * - * \section asfdoc_sam0_dac_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_dac_module_overview Module Overview - * - * The Digital-to-Analog converter converts a digital value to analog voltage. - * The SAM DAC module has one channel with 10-bit resolution, - * and is capable of converting up to 350k samples per second (ksps). - * - * A common use of DAC is to generate audio signals by connecting the DAC - * output to a speaker, or to generate a reference voltage; either for an - * external circuit or an internal peripheral such as the Analog Comparator. - * - * After being set up, the DAC will convert new digital values written to the - * conversion data register (DATA) to an analog value either on the VOUT pin of - * the device, or internally for use as an input to the AC, ADC, and other analog - * modules. - * - * Writing the DATA register will start a new conversion. It is also possible - * to trigger the conversion from the event system. - * - * A simplified block diagram of the DAC can be seen in - * \ref asfdoc_sam0_dac_module_block_diagram "the figure below". - * - * \anchor asfdoc_sam0_dac_module_block_diagram - * \image html dac_block_diagram.svg "DAC Block Diagram" - * - * \subsection asfdoc_sam0_dac_conversion_range Conversion Range - * The conversion range is between GND and the selected voltage reference. - * Available voltage references are: - * \li AVCC voltage reference - * \li Internal 1V reference (INT1V) - * \li External voltage reference (AREF) - * - * \note Internal references will be enabled by the driver, but not disabled. - * Any reference not used by the application should be disabled by the application. - * - * The output voltage from a DAC channel is given as: - * \f[ - * V_{OUT} = \frac{DATA}{0x3FF} \times VREF - * \f] - * - * \subsection asfdoc_sam0_dac_conversion Conversion - * The digital value written to the conversion data register (DATA) will be - * converted to an analog value. - * Writing the DATA register will start a new conversion. - * It is also possible to write the conversion data to the DATABUF register, - * the writing of the DATA register can then be triggered from the event - * system, which will load the value from DATABUF to DATA. - * - * \subsection asfdoc_sam0_dac_analog_output Analog Output - * The analog output value can be output to either the VOUT pin or internally, - * but not both at the same time. - * - * \subsubsection asfdoc_sam0_dac_analog_output_external External Output - * The output buffer must be enabled in order to drive the DAC output to the - * VOUT pin. Due to the output buffer, the DAC has high drive strength, and is - * capable of driving both resistive and capacitive loads, as well as loads - * which combine both. - * - * \subsubsection asfdoc_sam0_dac_analog_output_internal Internal Output - * The analog value can be internally available for use as input to the - * AC or ADC modules. - * - * \subsection asfdoc_sam0_dac_events Events - * Events generation and event actions are configurable in the DAC. - * The DAC has one event line input and one event output: Start Conversion - * and Data Buffer Empty. - * - * If the Start Conversion input event is enabled in the module configuration, - * an incoming event will load data from the data buffer to the data register - * and start a new conversion. This method synchronizes conversions with - * external events (such as those from a timer module) and ensures regular and - * fixed conversion intervals. - * - * If the Data Buffer Empty output event is enabled in the module configuration, - * events will be generated when the DAC data buffer register becomes empty and - * new data can be loaded to the buffer. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * \subsection asfdoc_sam0_dac_data_adjust Left and Right Adjusted Values - * The 10-bit input value to the DAC is contained in a 16-bit register. This - * can be configured to be either left or right adjusted. In - * \ref asfdoc_sam0_dac_module_adj_modes "the figure below" both options are - * shown, and the position of the most (MSB) and the least (LSB) significant bits - * are indicated. The unused bits should always be written to zero. - * - * \anchor asfdoc_sam0_dac_module_adj_modes - * \dot - * digraph { - * subgraph cluster_right { - * msbl [label="MSB", shape=none, group="msbl"]; - * lsbl [label="LSB", shape=none]; - * node [shape=none]; - * color="white"; - * reg_left [label=< - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
1514131211109876543210
DATA[9:0]
- * >]; - * msbl -> reg_left:msb:n; - * lsbl -> reg_left:lsb; - * label ="Left adjusted.\n"; - * } - * subgraph cluster_left { - * rankdir=TB; - * msb [label="MSB", shape=none]; - * lsb [label="LSB", shape=none]; - * color="white"; - * node [shape=none]; - * reg_right [label=< - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
1514131211109876543210
DATA[9:0]
- * >]; - * msb -> reg_right:msb; - * lsb -> reg_right:lsb:n; - * label = "Right adjusted.\n"; - * graph [shape=none]; - * } - * } - * \enddot - * - * \subsection asfdoc_sam0_dac_clk_sources Clock Sources - * The clock for the DAC interface (CLK_DAC) is generated by the Power Manager. - * This clock is turned on by default, and can be enabled and disabled in the - * Power Manager. - * - * Additionally, an asynchronous clock source (GCLK_DAC) is required. - * These clocks are normally disabled by default. The selected clock source - * must be enabled in the Power Manager before it can be used by the DAC. - * The DAC core operates asynchronously from the user interface and - * peripheral bus. As a consequence, the DAC needs two clock cycles of both - * CLK_DAC and GCLK_DAC to synchronize the values written to some of the - * control and data registers. - * The oscillator source for the GCLK_DAC clock is selected in the System - * Control Interface (SCIF). - * - * \section asfdoc_sam0_dac_special_considerations Special Considerations - * - * \subsection asfdoc_sam0_dac_special_considerations_output_buffer Output Driver - * The DAC can only do conversions in Active or Idle modes. However, if the - * output buffer is enabled it will draw current even if the system is in - * sleep mode. Therefore, always make sure that the output buffer is not - * enabled when it is not needed, to ensure minimum power consumption. - * - * \subsection asfdoc_sam0_dac_special_considerations_conversion_time Conversion Time - * DAC conversion time is approximately 2.85µs. The user must ensure that new - * data is not written to the DAC before the last conversion is complete. - * Conversions should be triggered by a periodic event from a Timer/Counter or - * another peripheral. - * - * - * \section asfdoc_sam0_dac_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_dac_extra. This includes: - * - \ref asfdoc_sam0_dac_extra_acronyms - * - \ref asfdoc_sam0_dac_extra_dependencies - * - \ref asfdoc_sam0_dac_extra_errata - * - \ref asfdoc_sam0_dac_extra_history - * - * - * \section asfdoc_sam0_dac_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_dac_exqsg. - * - * - * \section asfdoc_sam0_dac_api_overview API Overview - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - - -/** - * \name DAC Status Flags - * - * DAC status flags, returned by \ref dac_get_status() and cleared by - * \ref dac_clear_status(). - * @{ - */ - -/** Data Buffer Empty Channel 0 - Set when data is transferred from DATABUF - * to DATA by a start conversion event and DATABUF is ready for new data. - */ -#define DAC_STATUS_CHANNEL_0_EMPTY (1UL << 0) - -/** Under-run Channel 0 - Set when a start conversion event occurs when - * DATABUF is empty. - */ -#define DAC_STATUS_CHANNEL_0_UNDERRUN (1UL << 1) - -/** @} */ - -/** - * \brief DAC reference voltage enum. - * - * Enum for the possible reference voltages for the DAC. - */ -enum dac_reference { - /** 1V from the internal band-gap reference.*/ - DAC_REFERENCE_INT1V = DAC_CTRLB_REFSEL(0), - /** Analog VCC as reference. */ - DAC_REFERENCE_AVCC = DAC_CTRLB_REFSEL(1), - /** External reference on AREF. */ - DAC_REFERENCE_AREF = DAC_CTRLB_REFSEL(2), -}; - -/** - * \brief DAC output selection enum. - * - * Enum for the DAC output selection. - */ -enum dac_output { - /** DAC output to VOUT pin */ - DAC_OUTPUT_EXTERNAL = DAC_CTRLB_EOEN, - /** DAC output as internal reference */ - DAC_OUTPUT_INTERNAL = DAC_CTRLB_IOEN, - /** No output */ - DAC_OUTPUT_NONE = 0, -}; - -/** - * \brief DAC channel selection enum. - * - * Enum for the DAC channel selection. - */ -enum dac_channel { - /** DAC output channel 0. */ - DAC_CHANNEL_0, -}; - -/** - * \brief DAC software device instance structure. - * - * DAC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct dac_module { -#if !defined(__DOXYGEN__) - /** DAC hardware module. */ - Dac *hw; - /** DAC output selection. */ - enum dac_output output; - /** Reference selection. */ - enum dac_reference reference; - /** DAC event selection. */ - bool start_on_event; -# if DAC_CALLBACK_MODE == true - /** Pointer to buffer used for ADC results. */ - volatile uint16_t *job_buffer; - /** Remaining number of conversions in current job. */ - volatile uint16_t remaining_conversions; - /** Transferred number of conversions in current job. */ - volatile uint16_t transferred_conversions; - /** DAC callback enable. */ - bool callback_enable[DAC_CALLBACK_N]; - /** DAC registered callback functions. */ - dac_callback_t callback[DAC_CALLBACK_N]; - /** Holds the status of the ongoing or last conversion job. */ - volatile enum status_code job_status; -# endif -#endif -}; - -/** - * \brief DAC configuration structure. - * - * Configuration structure for a DAC instance. This structure should be - * initialized by the \ref dac_get_config_defaults() - * function before being modified by the user application. - */ -struct dac_config { - /** Reference voltage. */ - enum dac_reference reference; - /** Select DAC output. */ - enum dac_output output; - /** Left adjusted data. */ - bool left_adjust; - /** GCLK generator used to clock the peripheral. */ - enum gclk_generator clock_source; -#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION - /** Bypass DATABUF write protection. */ - bool databuf_protection_bypass; -#endif - /** Voltage pump disable. */ - bool voltage_pump_disable; - /** - * The DAC behaves as in normal mode when the chip enters STANDBY sleep - * mode. - */ - bool run_in_standby; -#if (SAMC21) - /** Dither mode enable data. */ - bool dither_mode; -#endif -}; - -/** - * \brief DAC event enable/disable structure. - * - * Event flags for the DAC module. This is used to enable and - * disable events via \ref dac_enable_events() and \ref dac_disable_events(). - */ -struct dac_events { - /** Start a new DAC conversion. */ - bool on_event_start_conversion; - /** Enable event generation on data buffer empty. */ - bool generate_event_on_buffer_empty; -#if (SAMC21) - /** Enable the falling edge of the input event for DAC1. */ - bool generate_event_on_chan_falling_edge; -#endif -}; - -/** - * \brief DAC channel configuration structure - * - * Configuration for a DAC channel. This structure should be initialized by the - * \ref dac_chan_get_config_defaults() function before being modified by the - * user application. - */ -struct dac_chan_config { -#if !defined(__DOXYGEN__) - /** Dummy value to ensure the struct has at least one member. */ - uint8_t _dummy; -#endif -}; - -/** - * \name Configuration and Initialization (Channel) - * @{ - */ - -void dac_chan_enable_output_buffer( - struct dac_module *const dev_inst, - const enum dac_channel channel); - -void dac_chan_disable_output_buffer( - struct dac_module *const dev_inst, - const enum dac_channel channel); - -/** @} */ - -/** @} */ - -/** - * \page asfdoc_sam0_dac_extra Extra Information for DAC Driver - * - * \section asfdoc_sam0_dac_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
ADCAnalog-to-Digital Converter
ACAnalog Comparator
DACDigital-to-Analog Converter
LSBLeast Significant Bit
MSBMost Significant Bit
DMADirect Memory Access
- * - * - * \section asfdoc_sam0_dac_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_dac_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_dac_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Add configuration for using 14-bit hardware dithering (SAMC21 support)
Added new configuration parameters \c databuf_protection_bypass, - * \c voltage_pump_disable. Added new callback functions - * \c dac_chan_write_buffer_wait, - * \c dac_chan_write_buffer_job, \c dac_chan_write_job, - * \c dac_get_job_status, \c dac_abort_job and new callback type - * \c DAC_CALLBACK_TRANSFER_COMPLETE for DAC conversion job
Initial Release
- */ - -/** - * \page asfdoc_sam0_dac_exqsg Examples for DAC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_dac_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_dac_basic_use_case - * \if DAC_CALLBACK_MODE - * - \subpage asfdoc_sam0_dac_basic_use_case_callback - * \endif - * \if DAC_DMA_USE_MODE_SELECTION - * - \subpage asfdoc_sam0_adc_dma_use_case_dac_in_dma - * \endif - * - * \if DAC_DMA_USE_MODE_SELECTION - * \page asfdoc_sam0_adc_dma_use_case_dac_in_dma Quick Start Guide for Using DMA with ADC/DAC - * For this examples, see - * \ref asfdoc_sam0_adc_dma_use_case - * \endif - * - * \page asfdoc_sam0_dac_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42110E06/2015Add SAMC21 and SAMDAx support
42110D12/2014Add SAMD10/D11 support
42110C01/2014Add SAMD21 support
42110B06/2013Added additional documentation on the event system. Corrected - * documentation typos.
42110A06/2013Initial document release
- */ - -#ifdef __cplusplus -} -#endif - - -#endif /* DAC_FEATURE_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac.c deleted file mode 100644 index 05d5ed2a120..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac.c +++ /dev/null @@ -1,790 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Digital-to-Analog Converter Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "dac.h" -#include -#include - -/** - * \internal Writes a DAC configuration to the hardware module. - * - * Writes out a given configuration to the hardware module. - * - * \param[out] module_inst Pointer to the DAC software instance struct - * \param[in] config Pointer to the configuration struct - * - */ -static void _dac_set_config( - struct dac_module *const module_inst, - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(config); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Set selected DAC start on event to be disable when enabling the module */ - module_inst->start_on_event[DAC_CHANNEL_0] = false; - module_inst->start_on_event[DAC_CHANNEL_1] = false; - - uint32_t new_ctrlb = 0; - - /* Enable DAC in differential mode if configured */ - if (config->differential_mode) { - new_ctrlb |= DAC_CTRLB_DIFF; - } - - /* Set reference voltage */ - new_ctrlb |= config->reference; - - /* Apply the new configuration to the hardware module */ - dac_module->CTRLB.reg = new_ctrlb; -} - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] dev_inst Pointer to the DAC software instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true If the module synchronization is ongoing - * \retval false If the module has completed synchronization - */ -bool dac_is_syncing( - struct dac_module *const dev_inst) -{ - /* Sanity check arguments */ - Assert(dev_inst); - - Dac *const dac_module = dev_inst->hw; - - if (dac_module->SYNCBUSY.reg) { - return true; - } - - return false; -} - -/** - * \brief Initializes a DAC configuration structure to defaults. - * - * Initializes a given DAC configuration structure to a set of - * known default values. This function should be called on any new - * instance of the configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li 1V from internal bandgap reference - * \li Drive the DAC output to the VOUT pin - * \li Right adjust data - * \li GCLK generator 0 (GCLK main) clock source - * \li The output buffer is disabled when the chip enters STANDBY sleep - * mode - * - * \param[out] config Configuration structure to initialize to default values - */ -void dac_get_config_defaults( - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->differential_mode = false; - config->reference = DAC_REFERENCE_INTREF; - config->clock_source = GCLK_GENERATOR_0; -} - -/** - * \brief Initialize the DAC device struct. - * - * Use this function to initialize the Digital to Analog Converter. Resets the - * underlying hardware module and configures it. - * - * \note The DAC channel must be configured separately. - * - * \param[out] module_inst Pointer to the DAC software instance struct - * \param[in] module Pointer to the DAC module instance - * \param[in] config Pointer to the config struct, created by the user - * application - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - */ -enum status_code dac_init( - struct dac_module *const module_inst, - Dac *const module, - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module); - Assert(config); - - /* Initialize device instance */ - module_inst->hw = module; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC); - - /* Check if module is enabled. */ - if (module->CTRLA.reg & DAC_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress. */ - if (module->CTRLA.reg & DAC_CTRLA_SWRST) { - return STATUS_BUSY; - } - - /* Configure GCLK channel and enable clock */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->clock_source; - system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(DAC_GCLK_ID); - - /* Write configuration to module */ - _dac_set_config(module_inst, config); - - /* Store reference selection for later use */ - module_inst->reference = config->reference; - -#if DAC_CALLBACK_MODE == true - for (uint8_t i = 0; i < DAC_CHANNEL_N; i++) { - for (uint8_t j = 0; j < DAC_CALLBACK_N; j++) { - module_inst->callback[i][j] = NULL; - } - }; - - _dac_instances[0] = module_inst; -#endif - - return STATUS_OK; -} - -/** - * \brief Resets the DAC module. - * - * This function will reset the DAC module to its power on default values and - * disable it. - * - * \param[in] module_inst Pointer to the DAC software instance struct - */ -void dac_reset( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - /* Software reset the module */ - dac_module->CTRLA.reg |= DAC_CTRLA_SWRST; -} - -/** - * \brief Enable the DAC module. - * - * Enables the DAC interface and the selected output. If any internal reference - * is selected it will be enabled. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * - */ -void dac_enable( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - /* Enable the module */ - dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE; - - /* Enable internal bandgap reference if selected in the configuration */ - if (module_inst->reference == DAC_REFERENCE_INTREF) { - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT); - } - - if(dac_module->DACCTRL[DAC_CHANNEL_0].reg & DAC_DACCTRL_ENABLE) { - while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_0 + 1))) { - }; - } else if(dac_module->DACCTRL[DAC_CHANNEL_1].reg & DAC_DACCTRL_ENABLE) { - while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_1 + 1))) { - }; - } -} - -/** - * \brief Disable the DAC module. - * - * Disables the DAC interface and the output buffer. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * - */ -void dac_disable( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - /* Disable DAC */ - dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE; -} - -/** - * \brief Enables a DAC event input or output. - * - * Enables one or more input or output events to or from the DAC module. See - * \ref dac_events "Struct dac_events" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the DAC peripheral - * \param[in] events Struct containing flags of events to enable - */ -void dac_enable_events( - struct dac_module *const module_inst, - struct dac_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Dac *const dac_module = module_inst->hw; - - uint32_t event_mask = 0; - - /* Configure Enable Inversion of input event */ - if (events->generate_event_on_chan0_falling_edge) { - event_mask |= DAC_EVCTRL_INVEI0; - } - - /* Configure Enable Inversion of input event */ - if (events->generate_event_on_chan1_falling_edge) { - event_mask |= DAC_EVCTRL_INVEI1; - } - - /* Configure Buffer Empty event */ - if (events->generate_event_on_chan0_buffer_empty) { - event_mask |= DAC_EVCTRL_EMPTYEO0; - } - - /* Configure Buffer Empty event */ - if (events->generate_event_on_chan1_buffer_empty) { - event_mask |= DAC_EVCTRL_EMPTYEO1; - } - - /* Configure Conversion Start event */ - if (events->on_event_chan0_start_conversion) { - event_mask |= DAC_EVCTRL_STARTEI0; - module_inst->start_on_event[DAC_CHANNEL_0] = true; - } - - /* Configure Conversion Start event */ - if (events->on_event_chan1_start_conversion) { - event_mask |= DAC_EVCTRL_STARTEI1; - module_inst->start_on_event[DAC_CHANNEL_1] = true; - } - - dac_module->EVCTRL.reg |= event_mask; -} - -/** - * \brief Disables a DAC event input or output. - * - * Disables one or more input or output events to or from the DAC module. See - * \ref dac_events "Struct dac_events" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the DAC peripheral - * \param[in] events Struct containing flags of events to disable - */ -void dac_disable_events( - struct dac_module *const module_inst, - struct dac_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Dac *const dac_module = module_inst->hw; - - uint32_t event_mask = 0; - - /* Configure Buffer Empty event */ - if (events->on_event_chan0_start_conversion) { - event_mask |= DAC_EVCTRL_EMPTYEO0; - } - - /* Configure Buffer Empty event */ - if (events->on_event_chan1_start_conversion) { - event_mask |= DAC_EVCTRL_EMPTYEO1; - } - - /* Configure Conversion Start event */ - if (events->generate_event_on_chan0_buffer_empty) { - event_mask |= DAC_EVCTRL_STARTEI0; - module_inst->start_on_event[DAC_CHANNEL_0] = false; - } - - /* Configure Conversion Start event */ - if (events->generate_event_on_chan0_buffer_empty) { - event_mask |= DAC_EVCTRL_STARTEI1; - module_inst->start_on_event[DAC_CHANNEL_1] = false; - } - - dac_module->EVCTRL.reg &= ~event_mask; -} - -void dac_chan_get_config_defaults( - struct dac_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Dac channel default configuration values */ - config->left_adjust = false; - config->current = DAC_CURRENT_12M; - config->run_in_standby = false; - config->dither_mode = false; - config->refresh_period = 1; -} - - -/** - * \brief Writes a DAC channel configuration to the hardware module. - * - * Writes out a given channel configuration to the hardware module. - * - * \note The DAC device instance structure must be initialized before calling - * this function. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to configure - * \param[in] config Pointer to the configuration struct - * - */ -void dac_chan_set_config( - struct dac_module *const module_inst, - const enum dac_channel channel, - struct dac_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(config); - - /* MUX the DAC VOUT pin */ - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - - if(channel == DAC_CHANNEL_0) { - /* Set up the DAC VOUT0 pin */ - pin_conf.mux_position = MUX_PA02B_DAC_VOUT0; - system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT0, &pin_conf); - } else if(channel == DAC_CHANNEL_1) { - /* Set up the DAC VOUT1 pin */ - pin_conf.mux_position = MUX_PA05B_DAC_VOUT1; - system_pinmux_pin_set_config(PIN_PA05B_DAC_VOUT1, &pin_conf); - } - - Dac *const dac_module = module_inst->hw; - - uint32_t new_dacctrl = 0; - - /* Left adjust data if configured */ - if (config->left_adjust) { - new_dacctrl |= DAC_DACCTRL_LEFTADJ; - } - - /* Set current control */ - new_dacctrl |= config->current; - - /* Enable DAC in standby sleep mode if configured */ - if (config->run_in_standby) { - new_dacctrl |= DAC_DACCTRL_RUNSTDBY; - } - - /* Voltage pump disable if configured */ - if (config->dither_mode) { - new_dacctrl |= DAC_DACCTRL_DITHER; - } - - new_dacctrl |= DAC_DACCTRL_REFRESH(config->refresh_period); - - /* Apply the new configuration to the hardware module */ - dac_module->DACCTRL[channel].reg = new_dacctrl; -} - -/** - * \brief Enable a DAC channel. - * - * Enables the selected DAC channel. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to enable - * - */ -void dac_chan_enable( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Enable the module */ - dac_module->DACCTRL[channel].reg |= DAC_DACCTRL_ENABLE; -} - -/** - * \brief Disable a DAC channel. - * - * Disables the selected DAC channel. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to disable - * - */ -void dac_chan_disable( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Enable the module */ - dac_module->DACCTRL[channel].reg &= ~DAC_DACCTRL_ENABLE; - -} - -/** - * \brief Write to the DAC. - * - * This function writes to the DATA or DATABUF register. - * If the conversion is not event-triggered, the data will be written to - * the DATA register and the conversion will start. - * If the conversion is event-triggered, the data will be written to DATABUF - * and transferred to the DATA register and converted when a Start Conversion - * Event is issued. - * Conversion data must be right or left adjusted according to configuration - * settings. - * \note To be event triggered, the enable_start_on_event must be - * enabled in the configuration. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] channel DAC channel to write to - * \param[in] data Conversion data - * - * \return Status of the operation. - * \retval STATUS_OK If the data was written - */ -enum status_code dac_chan_write( - struct dac_module *const module_inst, - enum dac_channel channel, - const uint16_t data) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - if (module_inst->start_on_event[channel]) { - /* Write the new value to the buffered DAC data register */ - dac_module->DATABUF[channel].reg = data; - } else { - /* Write the new value to the DAC data register */ - dac_module->DATA[channel].reg = data; - } - - return STATUS_OK; -} - -/** - * \brief Write to the DAC. - * - * This function converts a specific number of digital data. - * The conversion should be event-triggered, the data will be written to DATABUF - * and transferred to the DATA register and converted when a Start Conversion - * Event is issued. - * Conversion data must be right or left adjusted according to configuration - * settings. - * \note To be event triggered, the enable_start_on_event must be - * enabled in the configuration. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] channel DAC channel to write to - * \param[in] buffer Pointer to the digital data write buffer to be converted - * \param[in] length Length of the write buffer - * - * \return Status of the operation. - * \retval STATUS_OK If the data was written or no data conversion required - * \retval STATUS_ERR_UNSUPPORTED_DEV The DAC is not configured as using event trigger - * \retval STATUS_BUSY The DAC is busy and can not do the conversion - */ -enum status_code dac_chan_write_buffer_wait( - struct dac_module *const module_inst, - enum dac_channel channel, - uint16_t *buffer, - uint32_t length) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - /* Zero length request */ - if (length == 0) { - /* No data to be converted */ - return STATUS_OK; - } - -#if DAC_CALLBACK_MODE == true - /* Check if busy */ - if (module_inst->job_status[channel] == STATUS_BUSY) { - return STATUS_BUSY; - } -#endif - - /* Only support event triggered conversion */ - if (module_inst->start_on_event[channel] == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Blocks while buffer is being transferred */ - while (length--) { - /* Convert one data */ - dac_chan_write(module_inst, channel, buffer[length]); - - /* Wait until Transmit is complete or timeout */ - for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) { - if(channel == DAC_CHANNEL_0) { - if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY0) { - break; - } else if (i == DAC_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } else if(channel == DAC_CHANNEL_1) { - if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY1) { - break; - } else if (i == DAC_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - } - } - - return STATUS_OK; -} - -/** - * \brief Retrieves the status of DAC channel end of conversion. - * - * Checks if the conversion is completed or not and returns boolean flag - * of status. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to disable - * - * \retval true Conversion is complete, VOUT is stable - * \retval false No conversion completed since last load of DATA - */ -bool dac_chan_is_end_of_conversion( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - if(dac_module->STATUS.reg & DAC_STATUS_EOC(channel + 1)) { - return true; - } else { - return false; - } -} - -/** - * \brief Retrieves the current module status. - * - * Checks the status of the module and returns it as a bitmask of status - * flags. - * - * \param[in] module_inst Pointer to the DAC software device struct - * - * \return Bitmask of status flags. - * - * \retval DAC_STATUS_CHANNEL_0_EMPTY Data has been transferred from DATABUF - * to DATA by a start conversion event - * and DATABUF is ready for new data - * \retval DAC_STATUS_CHANNEL_0_UNDERRUN A start conversion event has occurred - * when DATABUF is empty - * - */ -uint32_t dac_get_status( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - uint8_t intflags = dac_module->INTFLAG.reg; - uint32_t status_flags = 0; - - if (intflags & DAC_INTFLAG_EMPTY0) { - status_flags |= DAC_STATUS_CHANNEL_0_EMPTY; - } - - if (intflags & DAC_INTFLAG_EMPTY1) { - status_flags |= DAC_STATUS_CHANNEL_1_EMPTY; - } - - if (intflags & DAC_INTFLAG_UNDERRUN0) { - status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN; - } - - if (intflags & DAC_INTFLAG_UNDERRUN1) { - status_flags |= DAC_STATUS_CHANNEL_1_UNDERRUN; - } - - return status_flags; -} - -/** - * \brief Clears a module status flag. - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] status_flags Bit mask of status flags to clear - * - */ -void dac_clear_status( - struct dac_module *const module_inst, - uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - uint32_t intflags = 0; - - if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) { - intflags |= DAC_INTFLAG_EMPTY0; - } - - if (status_flags & DAC_STATUS_CHANNEL_1_EMPTY) { - intflags |= DAC_INTFLAG_EMPTY1; - } - - if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) { - intflags |= DAC_INTFLAG_UNDERRUN0; - } - - if (status_flags & DAC_STATUS_CHANNEL_1_UNDERRUN) { - intflags |= DAC_INTFLAG_UNDERRUN1; - } - - dac_module->INTFLAG.reg = intflags; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac_feature.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac_feature.h deleted file mode 100644 index 584d77cfd8a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac_feature.h +++ /dev/null @@ -1,611 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Digital-to-Analog Converter Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DAC_FEATURE_H_INCLUDED -#define DAC_FEATURE_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_dac_group SAM Digital-to-Analog (DAC) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the conversion of - * digital values to analog voltage. The following driver API modes are covered - * by this manual: - * - * - Polled APIs - * \if DAC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - DAC (Digital-to-Analog Converter) - * - * The following devices can use this module: - * - Atmel | SMART SAM L21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_dac_prerequisites - * - \ref asfdoc_sam0_dac_module_overview - * - \ref asfdoc_sam0_dac_special_considerations - * - \ref asfdoc_sam0_dac_extra_info - * - \ref asfdoc_sam0_dac_examples - * - \ref asfdoc_sam0_dac_api_overview - * - * - * \section asfdoc_sam0_dac_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_dac_module_overview Module Overview - * - * The Digital-to-Analog converter converts a digital value to an analog voltage. - * The DAC Controller can operate as two independent DACs or as a single DAC - * in differential mode. Each DAC has a 12-bit resolution and it is capable of - * converting up to 1M samples per second (Msps). - * - * A common use of DAC is to generate audio signals by connecting the DAC - * output to a speaker, or to generate a reference voltage; either for an - * external circuit or an internal peripheral such as the Analog Comparator. - * - * After being set up, the DAC will convert new digital values written to the - * conversion data register (DATA0 or DATA1) to an analog value either on the - * DAC output (VOUT0 or VOUT1) pin of the device, or internally for use as an - * input to the AC, ADC, and other analog modules. - * - * Writing the DATA register will start a new conversion. It is also possible - * to trigger the conversion from the event system. - * - * A simplified block diagram of the DAC can be seen in - * \ref asfdoc_sam0_dac_module_block_diagram "the figure below". - * - * \anchor asfdoc_sam0_dac_module_block_diagram - * \image html dac_block_diagram_saml.svg "DAC Block Diagram" - * - * \subsection asfdoc_sam0_dac_conversion_range Conversion Range - * The conversion range is between GND and the selected voltage reference. - * Available voltage references are: - * \li Voltage supply (VDDANA) - * \li Internal bandgap reference (INTREF) - * \li Unbuffered External voltage reference (VREFPU) - * \li Buffered External voltage reference (VREFPB) - * - * \note Internal references will be enabled by the driver, but not disabled. - * Any reference not used by the application should be disabled by the application. - * - * The output voltage from a DAC channel is given as: - * \f[ - * V_{OUTx} = \frac{DATAx}{0x3FF} \times VREF - * \f] - * The differential output voltage is given as: - * \f[ - * V_{OUT} = \frac{DATA0}{0x1FF} \times VREF = (V_{OUT0}-V_{OUT1}) - * \f] - * - * \subsection asfdoc_sam0_dac_conversion Conversion - * The conversion digital value written to the DATA register will be converted - * to an analog value. Writing the DATA register will start a new conversion. - * It is also possible to write the conversion value to the DATABUF register, - * the writing of the DATA register can then be triggered from the event - * system, which will load the value from DATABUF to DATA. - * - * \subsection asfdoc_sam0_dac_analog_output Analog Output - * The analog output value can be output to the VOUTx converted by DACx, and - * each data conversion can be started independently. - * - * In differential mode, DAC0 and DAC1 are operating synchronously to convert - * value. VOUT0 is the positive output and VOUT1 the negative output. - * - * VOUT0 signal is internally connected so that it can be used as input for - * AC, ADC, or OPAMP modules when DAC0 is enabled. - * \note The pin VOUT0 will be dedicated to internal input and cannot be - * configured as alternate function. - * - * \subsection asfdoc_sam0_dac_events Events - * Events generation and event actions are configurable in the DAC. - * The DAC has one event line input and one event output: Start Conversion - * and Data Buffer Empty. - * - * If the Start Conversion input event is enabled in the module configuration, - * an incoming event will load data from the data buffer to the data register - * and start a new conversion. This method synchronizes conversions with - * external events (such as those from a timer module) and ensures regular and - * fixed conversion intervals. - * - * If the Data Buffer Empty output event is enabled in the module configuration, - * events will be generated when the DAC data buffer register becomes empty and - * new data can be loaded to the buffer. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * \subsection asfdoc_sam0_dac_data_adjust Left and Right Adjusted Values - * The 12-bit input value to the DAC is contained in a 16-bit register. This - * can be configured to be either left or right adjusted. In - * \ref asfdoc_sam0_dac_module_adj_modes "the figure below" both options are - * shown, and the position of the most (MSB) and the least (LSB) significant bits - * are indicated. The unused bits should always be written to zero. - * - * \anchor asfdoc_sam0_dac_module_adj_modes - * \dot - * digraph { - * subgraph cluster_right { - * msbl [label="MSB", shape=none, group="msbl"]; - * lsbl [label="LSB", shape=none]; - * node [shape=none]; - * color="white"; - * reg_left [label=< - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
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DATA[11:0]
- * >]; - * msbl -> reg_left:msb:n; - * lsbl -> reg_left:lsb; - * label ="Left adjusted.\n"; - * } - * subgraph cluster_left { - * rankdir=TB; - * msb [label="MSB", shape=none]; - * lsb [label="LSB", shape=none]; - * color="white"; - * node [shape=none]; - * reg_right [label=< - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
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DATA[11:0]
- * >]; - * msb -> reg_right:msb; - * lsb -> reg_right:lsb:n; - * label = "Right adjusted.\n"; - * graph [shape=none]; - * } - * } - * \enddot - * - * \subsection asfdoc_sam0_dac_clk_sources Clock Sources - * The clock for the DAC interface (CLK_DAC) is generated by the Power Manager. - * This clock is turned on by default, and can be enabled and disabled in the - * Power Manager. - * - * Additionally, an asynchronous clock source (GCLK_DAC) is required. - * These clocks are normally disabled by default. The selected clock source - * must be enabled in the Power Manager before it can be used by the DAC. - * The DAC core operates asynchronously from the user interface and - * peripheral bus. As a consequence, the DAC needs two clock cycles of both - * CLK_DAC and GCLK_DAC to synchronize the values written to some of the - * control and data registers. - * The oscillator source for the GCLK_DAC clock is selected in the Supply - * Control Interface (SUPC). - * - * \section asfdoc_sam0_dac_special_considerations Special Considerations - * - * \subsection asfdoc_sam0_dac_special_considerations_sleep Sleep Mode - * The DAC can do conversions in Active or Idle modes, and will continue the - * conversions in standby sleep mode if the RUNSTDBY bit in the DACCTRLx - * register is set. Otherwise, the DACx will stop conversions. - * - * If DACx conversion is stopped in standby sleep mode, DACx is disabled to - * reduce power consumption. When exiting standby sleep mode, DACx is enabled - * therefore startup time is required before starting a new conversion. - * - * \subsection asfdoc_sam0_dac_special_considerations_conversion_time Conversion Time - * DAC conversion time is approximately 2.85µs. The user must ensure that new - * data is not written to the DAC before the last conversion is complete. - * Conversions should be triggered by a periodic event from a Timer/Counter or - * another peripheral. - * - * - * \section asfdoc_sam0_dac_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_dac_extra. This includes: - * - \ref asfdoc_sam0_dac_extra_acronyms - * - \ref asfdoc_sam0_dac_extra_dependencies - * - \ref asfdoc_sam0_dac_extra_errata - * - \ref asfdoc_sam0_dac_extra_history - * - * - * \section asfdoc_sam0_dac_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_dac_exqsg. - * - * - * \section asfdoc_sam0_dac_api_overview API Overview - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - - -/** - * \name DAC Status Flags - * - * DAC status flags, returned by \ref dac_get_status() and cleared by - * \ref dac_clear_status(). - * @{ - */ - -/** Data Buffer Empty Channel 0 - Set when data is transferred from DATABUF - * to DATA by a start conversion event and DATABUF is ready for new data. - */ -#define DAC_STATUS_CHANNEL_0_EMPTY (1UL << 0) - -/** Data Buffer Empty Channel 1 - Set when data is transferred from DATABUF - * to DATA by a start conversion event and DATABUF is ready for new data. - */ -#define DAC_STATUS_CHANNEL_1_EMPTY (1UL << 1) - -/** Underrun Channel 0 - Set when a start conversion event occurs when - * DATABUF is empty. - */ -#define DAC_STATUS_CHANNEL_0_UNDERRUN (1UL << 2) - -/** Underrun Channel 1 - Set when a start conversion event occurs when - * DATABUF is empty. - */ -#define DAC_STATUS_CHANNEL_1_UNDERRUN (1UL << 3) - -/** @} */ - -/** - * \brief DAC reference voltage enum. - * - * Enum for the possible reference voltages for the DAC. - */ -enum dac_reference { - /** Unbuffered external voltage reference */ - DAC_REFERENCE_VREFPU = DAC_CTRLB_REFSEL(0), - /** Analog VCC as reference */ - DAC_REFERENCE_VDDANA = DAC_CTRLB_REFSEL(1), - /** Buffered external voltage reference */ - DAC_REFERENCE_VREFPB = DAC_CTRLB_REFSEL(2), - /** Internal bandgap reference */ - DAC_REFERENCE_INTREF = DAC_CTRLB_REFSEL(3), -}; - -/** - * \brief DAC current control enum. - * - * Enum for the current in output buffer according the conversion rate. - */ -enum dac_current_ctrl { - /** 1MHz < GCLK_DAC < 12MHz */ - DAC_CURRENT_12M = DAC_DACCTRL_CCTRL(0), - /** 100KHz < GCLK_DAC < 1MHz */ - DAC_CURRENT_1M = DAC_DACCTRL_CCTRL(1), - /** 10KHz < GCLK_DAC < 100KHz */ - DAC_CURRENT_100K = DAC_DACCTRL_CCTRL(2), - /** GCLK_DAC < 10KHz */ - DAC_CURRENT_10K = DAC_DACCTRL_CCTRL(3), -}; - -/** - * \brief DAC channel selection enum. - * - * Enum for the DAC channel selection. - */ -enum dac_channel { - /** DAC output channel 0 */ - DAC_CHANNEL_0, - /** DAC output channel 1 */ - DAC_CHANNEL_1, -#if !defined(__DOXYGEN__) - DAC_CHANNEL_N, -#endif -}; - -/** - * \brief DAC software device instance structure. - * - * DAC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct dac_module { -#if !defined(__DOXYGEN__) - /** DAC hardware module */ - Dac *hw; - /** Reference selection */ - enum dac_reference reference; - /** DAC event selection */ - bool start_on_event[DAC_CHANNEL_N]; -# if DAC_CALLBACK_MODE == true - /** Pointer to buffer used for ADC results */ - volatile uint16_t *job_buffer[DAC_CHANNEL_N]; - /** Remaining number of conversions in current job */ - volatile uint16_t remaining_conversions[DAC_CHANNEL_N]; - /** Transferred number of conversions in current job */ - volatile uint16_t transferred_conversions[DAC_CHANNEL_N]; - /** DAC callback enable */ - bool callback_enable[DAC_CHANNEL_N][DAC_CALLBACK_N]; - /** DAC registered callback functions */ - dac_callback_t callback[DAC_CHANNEL_N][DAC_CALLBACK_N]; - /** Holds the status of the ongoing or last conversion job */ - volatile enum status_code job_status[DAC_CHANNEL_N]; -# endif -#endif -}; - -/** - * \brief DAC configuration structure. - * - * Configuration structure for a DAC instance. This structure should be - * initialized by the \ref dac_get_config_defaults() - * function before being modified by the user application. - */ -struct dac_config { - /** Differential mode enable data */ - bool differential_mode; - /** Reference voltage */ - enum dac_reference reference; - /** GCLK generator used to clock the peripheral */ - enum gclk_generator clock_source; -}; - -/** - * \brief DAC channel configuration structure. - * - * Configuration for a DAC channel. This structure should be initialized by the - * \ref dac_chan_get_config_defaults() function before being modified by the - * user application. - */ -struct dac_chan_config { - /** Left adjusted data */ - bool left_adjust; - /** Current control data */ - enum dac_current_ctrl current; - /** - * The DAC behaves as in normal mode when the chip enters STANDBY sleep - * mode - */ - bool run_in_standby; - /** Dither mode enable data */ - bool dither_mode; - /** - * The DAC conversion refreshed periodically when used to generate a static - * voltage - */ - uint8_t refresh_period; -}; - -/** - * \brief DAC event enable/disable structure. - * - * Event flags for the DAC module. This is used to enable and - * disable events via \ref dac_enable_events() and \ref dac_disable_events(). - */ -struct dac_events { - /** Start a new DAC0 conversion */ - bool on_event_chan0_start_conversion; - /** Start a new DAC1 conversion */ - bool on_event_chan1_start_conversion; - /** Enable event generation on DAC0 data buffer empty */ - bool generate_event_on_chan0_buffer_empty; - /** Enable event generation on DAC1 data buffer empty */ - bool generate_event_on_chan1_buffer_empty; - /** Enable the falling edge of the input event for DAC0 */ - bool generate_event_on_chan0_falling_edge; - /** Enable the falling edge of the input event for DAC1 */ - bool generate_event_on_chan1_falling_edge; -}; - -/** - * \name Status Management (Channel) - * @{ - */ -bool dac_chan_is_end_of_conversion( - struct dac_module *const module_inst, - enum dac_channel channel); -/** @} */ - -/** @} */ - -/** - * \page asfdoc_sam0_dac_extra Extra Information for DAC Driver - * - * \section asfdoc_sam0_dac_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
ADCAnalog-to-Digital Converter
ACAnalog Comparator
DACDigital-to-Analog Converter
LSBLeast Significant Bit
MSBMost Significant Bit
DMADirect Memory Access
- * - * - * \section asfdoc_sam0_dac_extra_dependencies Dependencies - * This driver has the following dependency: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_dac_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_dac_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial Release
- */ - -/** - * \page asfdoc_sam0_dac_exqsg Examples for DAC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_dac_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_dac_basic_use_case - * \if DAC_CALLBACK_MODE - * - \subpage asfdoc_sam0_dac_basic_use_case_callback - * \endif - * \if DAC_DMA_USE_MODE_SELECTION - * - \subpage asfdoc_sam0_adc_dma_use_case_dac_in_dma - * \endif - * - * \if DAC_DMA_USE_MODE_SELECTION - * \page asfdoc_sam0_adc_dma_use_case_dac_in_dma Quick Start Guide for Using DMA with ADC/DAC - * For this examples, see - * \ref asfdoc_sam0_adc_dma_use_case - * \endif - * - * \page asfdoc_sam0_dac_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42450A07/2015Initial document release
- */ -#ifdef __cplusplus -} -#endif - - -#endif /* DAC_FEATURE_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/dac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/dac.h deleted file mode 100644 index d925388bfd1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/dac.h +++ /dev/null @@ -1,207 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Digital-to-Analog Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DAC_H_INCLUDED -#define DAC_H_INCLUDED - - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \addtogroup asfdoc_sam0_dac_group - * - * @{ - */ - -/** - * Define DAC features set according to different device families. - * @{ - */ -#if (SAMD21 || SAMD10 || SAMD11 || SAMDA1) -# define FEATURE_DAC_DATABUF_WRITE_PROTECTION -#endif -/**@}*/ - -#ifndef DAC_TIMEOUT -# define DAC_TIMEOUT 0xFFFF -#endif - -#if DAC_CALLBACK_MODE == true -# include - -/** Forward definition of the device instance. */ -struct dac_module; - -#if !defined(__DOXYGEN__) -extern struct dac_module *_dac_instances[DAC_INST_NUM]; -#endif - -/** Type definition for a DAC module callback function. */ -typedef void (*dac_callback_t)(uint8_t channel); - -/** Enum for the possible callback types for the DAC module. */ -enum dac_callback { - /** Callback type for when a DAC channel data empty condition occurs - * (requires event triggered mode) */ - DAC_CALLBACK_DATA_EMPTY, - - /** Callback type for when a DAC channel data underrun condition occurs - * (requires event triggered mode) */ - DAC_CALLBACK_DATA_UNDERRUN, - - /** Callback type for when a DAC channel write buffer job complete (requires - * event triggered mode) */ - DAC_CALLBACK_TRANSFER_COMPLETE, -#if !defined(__DOXYGEN__) - DAC_CALLBACK_N, -#endif -}; - -#endif - -#include - -/** - * \name Configuration and Initialization - * @{ - */ - -bool dac_is_syncing( - struct dac_module *const dev_inst); - -void dac_get_config_defaults( - struct dac_config *const config); - -enum status_code dac_init( - struct dac_module *const dev_inst, - Dac *const module, - struct dac_config *const config); - -void dac_reset( - struct dac_module *const dev_inst); - -void dac_enable( - struct dac_module *const dev_inst); - -void dac_disable( - struct dac_module *const dev_inst); - -void dac_enable_events( - struct dac_module *const module_inst, - struct dac_events *const events); - -void dac_disable_events( - struct dac_module *const module_inst, - struct dac_events *const events); - -/** @} */ - -/** - * \name Configuration and Initialization (Channel) - * @{ - */ - -void dac_chan_get_config_defaults( - struct dac_chan_config *const config); - -void dac_chan_set_config( - struct dac_module *const dev_inst, - const enum dac_channel channel, - struct dac_chan_config *const config); - -void dac_chan_enable( - struct dac_module *const dev_inst, - enum dac_channel channel); - -void dac_chan_disable( - struct dac_module *const dev_inst, - enum dac_channel channel); - -/** @} */ - -/** - * \name Channel Data Management - * @{ - */ - -enum status_code dac_chan_write( - struct dac_module *const dev_inst, - enum dac_channel channel, - const uint16_t data); - -enum status_code dac_chan_write_buffer_wait( - struct dac_module *const module_inst, - enum dac_channel channel, - uint16_t *buffer, - uint32_t length); - -/** @} */ - -/** - * \name Status Management - * @{ - */ -uint32_t dac_get_status( - struct dac_module *const module_inst); -void dac_clear_status( - struct dac_module *const module_inst, - uint32_t status_flags); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - - -#endif /* DAC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.c deleted file mode 100644 index 5fc04a976af..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.c +++ /dev/null @@ -1,654 +0,0 @@ -/* - * \file - * - * \brief SAM Direct Memory Access Controller Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include "dma.h" -#include "clock.h" -#include "system_interrupt.h" - -struct _dma_module { - volatile bool _dma_init; - volatile uint32_t allocated_channels; - uint8_t free_channels; -}; - -struct _dma_module _dma_inst = { - ._dma_init = false, - .allocated_channels = 0, - .free_channels = CONF_MAX_USED_CHANNEL_NUM, -}; - -/** Maximum retry counter for resuming a job transfer. */ -#define MAX_JOB_RESUME_COUNT 10000 - -/** DMA channel mask. */ -#define DMA_CHANNEL_MASK (0x1f) - -COMPILER_ALIGNED(16) -DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR; - -/** Initial write back memory section. */ -COMPILER_ALIGNED(16) -static DmacDescriptor _write_back_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR; - -/** Internal DMA resource pool. */ -static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM]; - -/* DMA channel interrup flag. */ -uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]= {0}; - -/** - * \brief Find a free channel for a DMA resource. - * - * Find a channel for the requested DMA resource. - * - * \return Status of channel allocation. - * \retval DMA_INVALID_CHANNEL No channel available - * \retval count Allocated channel for the DMA resource - */ -static uint8_t _dma_find_first_free_channel_and_allocate(void) -{ - uint8_t count; - uint32_t tmp; - bool allocated = false; - - system_interrupt_enter_critical_section(); - - tmp = _dma_inst.allocated_channels; - - for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) { - if (!(tmp & 0x00000001)) { - /* If free channel found, set as allocated and return - *number */ - - _dma_inst.allocated_channels |= 1 << count; - _dma_inst.free_channels--; - allocated = true; - - break; - } - - tmp = tmp >> 1; - } - - system_interrupt_leave_critical_section(); - - if (!allocated) { - return DMA_INVALID_CHANNEL; - } else { - return count; - } -} - -/** - * \brief Release an allocated DMA channel. - * - * \param[in] channel Channel id to be released - * - */ -static void _dma_release_channel(uint8_t channel) -{ - _dma_inst.allocated_channels &= ~(1 << channel); - _dma_inst.free_channels++; -} - -/** - * \brief Configure the DMA resource. - * - * \param[in] dma_resource Pointer to a DMA resource instance - * \param[out] resource_config Configurations of the DMA resource - * - */ -static void _dma_set_config(struct dma_resource *resource, - struct dma_resource_config *resource_config) -{ - Assert(resource); - Assert(resource_config); - uint32_t temp_CHCTRLB_reg; - system_interrupt_enter_critical_section(); - - /** Select the DMA channel and clear software trigger */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id)); - - temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \ - DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \ - DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action); - - - if(resource_config->event_config.input_action) { - temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT( - resource_config->event_config.input_action); - } - - /** Enable event output, the event output selection is configured in - * each transfer descriptor */ - if (resource_config->event_config.event_output_enable) { - temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE; - } - - /* Write config to CTRLB register */ - DMAC->CHCTRLB.reg = temp_CHCTRLB_reg; - - - - system_interrupt_leave_critical_section(); -} - -/** - * \brief DMA interrupt service routine. - * - */ -void DMAC_Handler( void ) -{ - uint8_t active_channel; - struct dma_resource *resource; - uint8_t isr; - uint32_t write_size; - uint32_t total_size; - - system_interrupt_enter_critical_section(); - - /* Get Pending channel */ - active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk; - - Assert(_dma_active_resource[active_channel]); - - /* Get active DMA resource based on channel */ - resource = _dma_active_resource[active_channel]; - - /* Select the active channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - isr = DMAC->CHINTFLAG.reg; - - /* Calculate block transfer size of the DMA transfer */ - total_size = descriptor_section[resource->channel_id].BTCNT.reg; - write_size = _write_back_section[resource->channel_id].BTCNT.reg; - resource->transfered_size = total_size - write_size; - - /* DMA channel interrupt handler */ - if (isr & DMAC_CHINTENCLR_TERR) { - /* Clear transfer error flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR; - - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - - /* Execute the callback function */ - if ((resource->callback_enable & (1<callback[DMA_CALLBACK_TRANSFER_ERROR])) { - resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource); - } - } else if (isr & DMAC_CHINTENCLR_TCMPL) { - /* Clear the transfer complete flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL; - - /* Set job status */ - resource->job_status = STATUS_OK; - - /* Execute the callback function */ - if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) && - (resource->callback[DMA_CALLBACK_TRANSFER_DONE])) { - resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource); - } - } else if (isr & DMAC_CHINTENCLR_SUSP) { - /* Clear channel suspend flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP; - - /* Set job status */ - resource->job_status = STATUS_SUSPEND; - - /* Execute the callback function */ - if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) && - (resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])) { - resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource); - } - } - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Initializes config with predefined default values. - * - * This function will initialize a given DMA configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structure before being - * modified by the user application. - * - * The default configuration is as follows: - * \li Software trigger is used as the transfer trigger - * \li Priority level 0 - * \li Only software/event trigger - * \li Requires a trigger for each transaction - * \li No event input /output - * \li DMA channel is disabled during sleep mode (if has the feature) - * \param[out] config Pointer to the configuration - * - */ -void dma_get_config_defaults(struct dma_resource_config *config) -{ - Assert(config); - /* Set as priority 0 */ - config->priority = DMA_PRIORITY_LEVEL_0; - /* Only software/event trigger */ - config->peripheral_trigger = 0; - /* Transaction trigger */ - config->trigger_action = DMA_TRIGGER_ACTON_TRANSACTION; - - /* Event configurations, no event input/output */ - config->event_config.input_action = DMA_EVENT_INPUT_NOACT; - config->event_config.event_output_enable = false; -#ifdef FEATURE_DMA_CHANNEL_STANDBY - config->run_in_standby = false; -#endif -} - -/** - * \brief Allocate a DMA with configurations. - * - * This function will allocate a proper channel for a DMA transfer request. - * - * \param[in,out] dma_resource Pointer to a DMA resource instance - * \param[in] transfer_config Configurations of the DMA transfer - * - * \return Status of the allocation procedure. - * - * \retval STATUS_OK The DMA resource was allocated successfully - * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed - */ -enum status_code dma_allocate(struct dma_resource *resource, - struct dma_resource_config *config) -{ - uint8_t new_channel; - - Assert(resource); - - system_interrupt_enter_critical_section(); - - if (!_dma_inst._dma_init) { - /* Initialize clocks for DMA */ -#if (SAML21) || (SAMC20) || (SAMC21) - system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC); -#else - system_ahb_clock_set_mask(PM_AHBMASK_DMAC); - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, - PM_APBBMASK_DMAC); -#endif - - /* Perform a software reset before enable DMA controller */ - DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; - DMAC->CTRL.reg = DMAC_CTRL_SWRST; - - /* Setup descriptor base address and write back section base - * address */ - DMAC->BASEADDR.reg = (uint32_t)descriptor_section; - DMAC->WRBADDR.reg = (uint32_t)_write_back_section; - - /* Enable all priority level at the same time */ - DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf); - - _dma_inst._dma_init = true; - } - - /* Find the proper channel */ - new_channel = _dma_find_first_free_channel_and_allocate(); - - /* If no channel available, return not found */ - if (new_channel == DMA_INVALID_CHANNEL) { - system_interrupt_leave_critical_section(); - - return STATUS_ERR_NOT_FOUND; - } - - /* Set the channel */ - resource->channel_id = new_channel; - - /** Perform a reset for the allocated channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST; - -#ifdef FEATURE_DMA_CHANNEL_STANDBY - if(config->run_in_standby) { - DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - } -#endif - - /** Configure the DMA control,channel registers and descriptors here */ - _dma_set_config(resource, config); - - resource->descriptor = NULL; - - /* Log the DMA resource into the internal DMA resource pool */ - _dma_active_resource[resource->channel_id] = resource; - - system_interrupt_leave_critical_section(); - - return STATUS_OK; -} - -/** - * \brief Free an allocated DMA resource. - * - * This function will free an allocated DMA resource. - * - * \param[in,out] resource Pointer to the DMA resource - * - * \return Status of the free procedure. - * - * \retval STATUS_OK The DMA resource was freed successfully - * \retval STATUS_BUSY The DMA resource was busy and can't be freed - * \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized - */ -enum status_code dma_free(struct dma_resource *resource) -{ - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - system_interrupt_enter_critical_section(); - - /* Check if channel is busy */ - if (dma_is_busy(resource)) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } - - /* Check if DMA resource was not allocated */ - if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) { - system_interrupt_leave_critical_section(); - return STATUS_ERR_NOT_INITIALIZED; - } - - /* Release the DMA resource */ - _dma_release_channel(resource->channel_id); - - /* Reset the item in the DMA resource pool */ - _dma_active_resource[resource->channel_id] = NULL; - - system_interrupt_leave_critical_section(); - - return STATUS_OK; -} - -/** - * \brief Start a DMA transfer. - * - * This function will start a DMA transfer through an allocated DMA resource. - * - * \param[in,out] resource Pointer to the DMA resource - * - * \return Status of the transfer start procedure. - * - * \retval STATUS_OK The transfer was started successfully - * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started - * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started - */ -enum status_code dma_start_transfer_job(struct dma_resource *resource) -{ - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - system_interrupt_enter_critical_section(); - - /* Check if resource was busy */ - if (resource->job_status == STATUS_BUSY) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } - - /* Check if transfer size is valid */ - if (resource->descriptor->BTCNT.reg == 0) { - system_interrupt_leave_critical_section(); - return STATUS_ERR_INVALID_ARG; - } - - /* Enable DMA interrupt */ - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA); - - /* Set the interrupt flag */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]); - /* Set job status */ - resource->job_status = STATUS_BUSY; - - /* Set channel x descriptor 0 to the descriptor base address */ - memcpy(&descriptor_section[resource->channel_id], resource->descriptor, - sizeof(DmacDescriptor)); - - /* Enable the transfer channel */ - DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - - system_interrupt_leave_critical_section(); - - return STATUS_OK; -} - -/** - * \brief Abort a DMA transfer. - * - * This function will abort a DMA transfer. The DMA channel used for the DMA - * resource will be disabled. - * The block transfer count will be also calculated and written to the DMA - * resource structure. - * - * \note The DMA resource will not be freed after calling this function. - * The function \ref dma_free() can be used to free an allocated resource. - * - * \param[in,out] resource Pointer to the DMA resource - * - */ -void dma_abort_job(struct dma_resource *resource) -{ - uint32_t write_size; - uint32_t total_size; - - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - system_interrupt_enter_critical_section(); - - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLA.reg = 0; - - system_interrupt_leave_critical_section(); - - /* Get transferred size */ - total_size = descriptor_section[resource->channel_id].BTCNT.reg; - write_size = _write_back_section[resource->channel_id].BTCNT.reg; - resource->transfered_size = total_size - write_size; - - resource->job_status = STATUS_ABORTED; -} - -/** - * \brief Suspend a DMA transfer. - * - * This function will request to suspend the transfer of the DMA resource. - * The channel is kept enabled, can receive transfer triggers (the transfer - * pending bit will be set), but will be removed from the arbitration scheme. - * The channel operation can be resumed by calling \ref dma_resume_job(). - * - * \note This function sets the command to suspend the DMA channel - * associated with a DMA resource. The channel suspend interrupt flag - * indicates whether the transfer is truly suspended. - * - * \param[in] resource Pointer to the DMA resource - * - */ -void dma_suspend_job(struct dma_resource *resource) -{ - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - system_interrupt_enter_critical_section(); - - /* Select the channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - - /* Send the suspend request */ - DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Resume a suspended DMA transfer. - * - * This function try to resume a suspended transfer of a DMA resource. - * - * \param[in] resource Pointer to the DMA resource - * - */ -void dma_resume_job(struct dma_resource *resource) -{ - uint32_t bitmap_channel; - uint32_t count = 0; - - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - /* Get bitmap of the allocated DMA channel */ - bitmap_channel = (1 << resource->channel_id); - - /* Check if channel was suspended */ - if (resource->job_status != STATUS_SUSPEND) { - return; - } - - system_interrupt_enter_critical_section(); - - /* Send resume request */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME; - - system_interrupt_leave_critical_section(); - - /* Check if transfer job resumed */ - for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) { - if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) { - break; - } - } - - if (count < MAX_JOB_RESUME_COUNT) { - /* Job resumed */ - resource->job_status = STATUS_BUSY; - } else { - /* Job resume timeout */ - resource->job_status = STATUS_ERR_TIMEOUT; - } -} - -/** - * \brief Create a DMA transfer descriptor with configurations. - * - * This function will set the transfer configurations to the DMA transfer - * descriptor. - * - * \param[in] descriptor Pointer to the DMA transfer descriptor - * \param[in] config Pointer to the descriptor configuration structure - * - */ -void dma_descriptor_create(DmacDescriptor* descriptor, - struct dma_descriptor_config *config) -{ - /* Set block transfer control */ - descriptor->BTCTRL.bit.VALID = config->descriptor_valid; - descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection; - descriptor->BTCTRL.bit.BLOCKACT = config->block_action; - descriptor->BTCTRL.bit.BEATSIZE = config->beat_size; - descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable; - descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable; - descriptor->BTCTRL.bit.STEPSEL = config->step_selection; - descriptor->BTCTRL.bit.STEPSIZE = config->step_size; - - /* Set transfer size, source address and destination address */ - descriptor->BTCNT.reg = config->block_transfer_count; - descriptor->SRCADDR.reg = config->source_address; - descriptor->DSTADDR.reg = config->destination_address; - - /* Set next transfer descriptor address */ - descriptor->DESCADDR.reg = config->next_descriptor_address; -} - -/** - * \brief Add a DMA transfer descriptor to a DMA resource. - * - * This function will add a DMA transfer descriptor to a DMA resource. - * If there was a transfer descriptor already allocated to the DMA resource, - * the descriptor will be linked to the next descriptor address. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] descriptor Pointer to the transfer descriptor - * - * \retval STATUS_OK The descriptor is added to the DMA resource - * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added - */ -enum status_code dma_add_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor) -{ - DmacDescriptor* desc = resource->descriptor; - - if (resource->job_status == STATUS_BUSY) { - return STATUS_BUSY; - } - - /* Look up for an empty space for the descriptor */ - if (desc == NULL) { - resource->descriptor = descriptor; - } else { - /* Looking for end of descriptor link */ - while(desc->DESCADDR.reg != 0) { - desc = (DmacDescriptor*)(desc->DESCADDR.reg); - } - - /* Set to the end of descriptor list */ - desc->DESCADDR.reg = (uint32_t)descriptor; - } - - return STATUS_OK; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.h deleted file mode 100644 index 5812bbb5f08..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.h +++ /dev/null @@ -1,879 +0,0 @@ -/** - * \file - * - * \brief SAM Direct Memory Access Controller Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DMA_H_INCLUDED -#define DMA_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_dma_group SAM Direct Memory Access Controller Driver (DMAC) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of the Direct Memory Access Controller(DMAC) module within - * the device. The DMAC can transfer data between memories and peripherals, and - * thus off-load these tasks from the CPU. The module supports peripheral to - * peripheral, peripheral to memory, memory to peripheral, and memory to memory - * transfers. - * - * The following peripherals are used by the DMAC Driver: - * - DMAC (Direct Memory Access Controller) - * - * The following devices can use this module: - * - Atmel | SMART SAM D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_dma_prerequisites - * - \ref asfdoc_sam0_dma_module_overview - * - \ref asfdoc_sam0_dma_special_considerations - * - \ref asfdoc_sam0_dma_extra_info - * - \ref asfdoc_sam0_dma_examples - * - \ref asfdoc_sam0_dma_api_overview - * - * - * \section asfdoc_sam0_dma_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_dma_module_overview Module Overview - * - * SAM devices with DMAC enables high data transfer rates with minimum - * CPU intervention and frees up CPU time. With access to all peripherals, - * the DMAC can handle automatic transfer of data to/from modules. - * It supports static and incremental addressing for both source and - * destination. - * - * The DMAC when used with Event System or peripheral triggers, provides a - * considerable advantage by reducing the power consumption and performing - * data transfer in the background. - * For example if the ADC is configured to generate an event, it can trigger - * the DMAC to transfer the data into another peripheral or into SRAM. - * The CPU can remain in sleep during this time to reduce power consumption. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
DeviceDma channel number
SAMD21/R21/C20/C2112
SAMD10/D116
SAML2116
- * The DMA channel operation can be suspended at any time by software, by events - * from event system, or after selectable descriptor execution. The operation - * can be resumed by software or by events from event system. - * The DMAC driver for SAM supports four types of transfers such as - * peripheral to peripheral, peripheral to memory, memory to peripheral, and - * memory to memory. - * - * The basic transfer unit is a beat which is defined as a single bus access. - * There can be multiple beats in a single block transfer and multiple block - * transfers in a DMA transaction. - * DMA transfer is based on descriptors, which holds transfer properties - * such as the source and destination addresses, transfer counter, and other - * additional transfer control information. - * The descriptors can be static or linked. When static, a single block transfer - * is performed. When linked, a number of transfer descriptors can be used to - * enable multiple block transfers within a single DMA transaction. - * - * The implementation of the DMA driver is based on the idea that DMA channel - * is a finite resource of entities with the same abilities. A DMA channel resource - * is able to move a defined set of data from a source address to destination - * address triggered by a transfer trigger. On the SAM devices there are 12 - * DMA resources available for allocation. Each of these DMA resources can trigger - * interrupt callback routines and peripheral events. - * The other main features are - * - * - Selectable transfer trigger source - * - Software - * - Event System - * - Peripheral - * - Event input and output is supported for the four lower channels - * - Four level channel priority - * - Optional interrupt generation on transfer complete, channel error or channel suspend - * - Supports multi-buffer or circular buffer mode by linking multiple descriptors - * - Beat size configurable as 8-bit, 16-bit, or 32-bit - * - * A simplified block diagram of the DMA Resource can be seen in - * \ref asfdoc_sam0_dma_module_block_diagram "the figure below". - * - * \anchor asfdoc_sam0_dma_module_block_diagram - * \dot - * digraph overview { - * splines = false; - * rankdir=LR; - * - * mux1 [label="Transfer Trigger", shape=box]; - * - * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1]; - * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue]; - * - * mux1 -> dma; - * descriptor -> dma; - * - * interrupt [label="Interrupt", shape=box]; - * events [label="Events", shape=box]; - * - * dma:e -> interrupt:w; - * dma:e -> events:w; - * - * {rank=same; descriptor dma} - * - * } - * \enddot - * - * \subsection asfdoc_sam0_dma_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_DMA_CHANNEL_STANDBYSAML21/C20/C21
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_dma_module_overview_dma_transf_term Terminology Used in DMAC Transfers - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Name Description
Beat It is a single bus access by the DMAC. - * Configurable as 8-bit, 16-bit, or 32-bit - *
Burst It is a transfer of n-beats (n=1,4,8,16). - * For the DMAC module in SAM, the burst size is one beat. - * Arbitration takes place each time a burst transfer is completed - *
Block transfer A single block transfer is a configurable number of (1 to 64k) - * beat transfers - *
- * - * \subsection asfdoc_sam0_dma_module_overview_dma_channels DMA Channels - * The DMAC in each device consists of several DMA channels, which - * along with the transfer descriptors defines the data transfer properties. - * - The transfer control descriptor defines the source and destination - * addresses, source and destination address increment settings, the - * block transfer count and event output condition selection - * - Dedicated channel registers control the peripheral trigger source, - * trigger mode settings, event input actions, and channel priority level - * settings - * - * With a successful DMA resource allocation, a dedicated - * DMA channel will be assigned. The channel will be occupied until the - * DMA resource is freed. A DMA resource handle is used to identify the specific - * DMA resource. - * When there are multiple channels with active requests, the arbiter prioritizes - * the channels requesting access to the bus. - * - * \subsection asfdoc_sam0_dma_module_overview_dma_trigger DMA Triggers - * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A - * transfer request can be triggered from software, peripheral, or an event. There - * are dedicated source trigger selections for each DMA channel usage. - - * - * \subsection asfdoc_sam0_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor - * The transfer descriptor resides in the SRAM and - * defines these channel properties. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Field name Field width
Descriptor Next Address 32 bits
Destination Address 32 bits
Source Address 32 bits
Block Transfer Counter 16 bits
Block Transfer Control 16 bits
- * - * Before starting a transfer, at least one descriptor should be configured. - * After a successful allocation of a DMA channel, the transfer descriptor can - * be added with a call to \ref dma_add_descriptor(). If there is a transfer - * descriptor already allocated to the DMA resource, the descriptor will - * be linked to the next descriptor address. - * - * \subsection asfdoc_sam0_dma_module_overview_dma_output DMA Interrupts/Events - * Both an interrupt callback and an peripheral event can be triggered by the - * DMA transfer. Three types of callbacks are supported by the DMA driver: - * transfer complete, channel suspend, and transfer error. Each of these callback - * types can be registered and enabled for each channel independently through - * the DMA driver API. - * - * The DMAC module can also generate events on transfer complete. Event - * generation is enabled through the DMA channel, event channel configuration, - * and event user multiplexing is done through the events driver. - * - * The DMAC can generate events in the below cases: - * - * - When a block transfer is complete - * - * - When each beat transfer within a block transfer is complete - * - * \section asfdoc_sam0_dma_special_considerations Special Considerations - * - * There are no special considerations for this module. - * - * - * \section asfdoc_sam0_dma_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_dma_extra. This includes: - * - \ref asfdoc_sam0_dma_extra_acronyms - * - \ref asfdoc_sam0_dma_extra_dependencies - * - \ref asfdoc_sam0_dma_extra_errata - * - \ref asfdoc_sam0_dma_extra_history - * - * - * \section asfdoc_sam0_dma_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_dma_exqsg. - * - * - * \section asfdoc_sam0_dma_api_overview API Overview - * @{ - */ - -#include -#include "conf_dma.h" - -#if (SAML21) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -#define FEATURE_DMA_CHANNEL_STANDBY -#endif - -/** DMA invalid channel number. */ -#define DMA_INVALID_CHANNEL 0xff - -/** ExInitial description section. */ -extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM]; - -/* DMA channel interrup flag. */ -extern uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]; - -/** DMA priority level. */ -enum dma_priority_level { - /** Priority level 0. */ - DMA_PRIORITY_LEVEL_0, - /** Priority level 1. */ - DMA_PRIORITY_LEVEL_1, - /** Priority level 2. */ - DMA_PRIORITY_LEVEL_2, - /** Priority level 3. */ - DMA_PRIORITY_LEVEL_3, -}; - -/** DMA input actions. */ -enum dma_event_input_action { - /** No action. */ - DMA_EVENT_INPUT_NOACT, - /** Normal transfer and periodic transfer trigger. */ - DMA_EVENT_INPUT_TRIG, - /** Conditional transfer trigger. */ - DMA_EVENT_INPUT_CTRIG, - /** Conditional block transfer. */ - DMA_EVENT_INPUT_CBLOCK, - /** Channel suspend operation. */ - DMA_EVENT_INPUT_SUSPEND, - /** Channel resume operation. */ - DMA_EVENT_INPUT_RESUME, - /** Skip next block suspend action. */ - DMA_EVENT_INPUT_SSKIP, -}; - -/** - * Address increment step size. These bits select the address increment step - * size. The setting apply to source or destination address, depending on - * STEPSEL setting. - */ -enum dma_address_increment_stepsize { - /** The address is incremented by (beat size * 1). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0, - /** The address is incremented by (beat size * 2). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_2, - /** The address is incremented by (beat size * 4). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_4, - /** The address is incremented by (beat size * 8). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_8, - /** The address is incremented by (beat size * 16). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_16, - /** The address is incremented by (beat size * 32). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_32, - /** The address is incremented by (beat size * 64). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_64, - /** The address is incremented by (beat size * 128). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_128, -}; - -/** - * DMA step selection. This bit determines whether the step size setting - * is applied to source or destination address. - */ -enum dma_step_selection { - /** Step size settings apply to the destination address. */ - DMA_STEPSEL_DST = 0, - /** Step size settings apply to the source address. */ - DMA_STEPSEL_SRC, -}; - -/** The basic transfer unit in DMAC is a beat, which is defined as a - * single bus access. Its size is configurable and applies to both read - * and write. */ -enum dma_beat_size { - /** 8-bit access. */ - DMA_BEAT_SIZE_BYTE = 0, - /** 16-bit access. */ - DMA_BEAT_SIZE_HWORD, - /** 32-bit access. */ - DMA_BEAT_SIZE_WORD, -}; - -/** - * Block action definitions. - */ -enum dma_block_action { - /** No action. */ - DMA_BLOCK_ACTION_NOACT = 0, - /** Channel in normal operation and sets transfer complete interrupt flag - * after block transfer. */ - DMA_BLOCK_ACTION_INT, - /** Trigger channel suspend after block transfer and sets channel - * suspend interrupt flag once the channel is suspended. */ - DMA_BLOCK_ACTION_SUSPEND, - /** Sets transfer complete interrupt flag after a block transfer and - * trigger channel suspend. The channel suspend interrupt flag will be set - * once the channel is suspended. */ - DMA_BLOCK_ACTION_BOTH, -}; - -/** Event output selection. */ -enum dma_event_output_selection { - /** Event generation disable. */ - DMA_EVENT_OUTPUT_DISABLE = 0, - /** Event strobe when block transfer complete. */ - DMA_EVENT_OUTPUT_BLOCK, - /** Event output reserved. */ - DMA_EVENT_OUTPUT_RESERVED, - /** Event strobe when beat transfer complete. */ - DMA_EVENT_OUTPUT_BEAT, -}; - -/** DMA trigger action type. */ -enum dma_transfer_trigger_action { - /** Perform a block transfer when triggered. */ - DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val, - /** Perform a beat transfer when triggered. */ - DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val, - /** Perform a transaction when triggered. */ - DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val, -}; - -/** - * Callback types for DMA callback driver. - */ -enum dma_callback_type { - /** Callback for any of transfer errors. A transfer error is flagged - * if a bus error is detected during an AHB access or when the DMAC - * fetches an invalid descriptor. */ - DMA_CALLBACK_TRANSFER_ERROR, - /** Callback for transfer complete. */ - DMA_CALLBACK_TRANSFER_DONE, - /** Callback for channel suspend. */ - DMA_CALLBACK_CHANNEL_SUSPEND, - /** Number of available callbacks. */ - DMA_CALLBACK_N, -}; - -/** - * DMA transfer descriptor configuration. When the source or destination address - * increment is enabled, the addresses stored into the configuration structure - * must correspond to the end of the transfer. - * - */ -struct dma_descriptor_config { - /** Descriptor valid flag used to identify whether a descriptor is - valid or not. */ - bool descriptor_valid; - /** This is used to generate an event on specific transfer action in - a channel. Supported only in four lower channels. */ - enum dma_event_output_selection event_output_selection; - /** Action taken when a block transfer is completed. */ - enum dma_block_action block_action; - /** Beat size is configurable as 8-bit, 16-bit, or 32-bit. */ - enum dma_beat_size beat_size; - /** Used for enabling the source address increment. */ - bool src_increment_enable; - /** Used for enabling the destination address increment. */ - bool dst_increment_enable; - /** This bit selects whether the source or destination address is - using the step size settings. */ - enum dma_step_selection step_selection; - /** The step size for source/destination address increment. - The next address is calculated - as next_addr = addr + (2^step_size * beat size). */ - enum dma_address_increment_stepsize step_size; - /** It is the number of beats in a block. This count value is - * decremented by one after each beat data transfer. */ - uint16_t block_transfer_count; - /** Transfer source address. */ - uint32_t source_address; - /** Transfer destination address. */ - uint32_t destination_address; - /** Set to zero for static descriptors. This must have a valid memory - address for linked descriptors. */ - uint32_t next_descriptor_address; -}; - -/** Configurations for DMA events. */ -struct dma_events_config { - /** Event input actions. */ - enum dma_event_input_action input_action; - /** Enable DMA event output. */ - bool event_output_enable; -}; - -/** DMA configurations for transfer. */ -struct dma_resource_config { - /** DMA transfer priority. */ - enum dma_priority_level priority; - /**DMA peripheral trigger index. */ - uint8_t peripheral_trigger; - /** DMA trigger action. */ - enum dma_transfer_trigger_action trigger_action; -#ifdef FEATURE_DMA_CHANNEL_STANDBY - /** Keep DMA channel enabled in standby sleep mode if true. */ - bool run_in_standby; -#endif - /** DMA events configurations. */ - struct dma_events_config event_config; -}; - -/** Forward definition of the DMA resource. */ -struct dma_resource; -/** Type definition for a DMA resource callback function. */ -typedef void (*dma_callback_t)(struct dma_resource *const resource); - -/** Structure for DMA transfer resource. */ -struct dma_resource { - /** Allocated DMA channel ID. */ - uint8_t channel_id; - /** Array of callback functions for DMA transfer job. */ - dma_callback_t callback[DMA_CALLBACK_N]; - /** Bit mask for enabled callbacks. */ - uint8_t callback_enable; - /** Status of the last job. */ - volatile enum status_code job_status; - /** Transferred data size. */ - uint32_t transfered_size; - /** DMA transfer descriptor. */ - DmacDescriptor* descriptor; -}; - -/** - * \brief Get DMA resource status. - * - * \param[in] resource Pointer to the DMA resource - * - * \return Status of the DMA resource. - */ -static inline enum status_code dma_get_job_status(struct dma_resource *resource) -{ - Assert(resource); - - return resource->job_status; -} - -/** - * \brief Check if the given DMA resource is busy. - * - * \param[in] resource Pointer to the DMA resource - * - * \return Status which indicates whether the DMA resource is busy. - * - * \retval true The DMA resource has an on-going transfer - * \retval false The DMA resource is not busy - */ -static inline bool dma_is_busy(struct dma_resource *resource) -{ - Assert(resource); - - return (resource->job_status == STATUS_BUSY); -} - -/** - * \brief Enable a callback function for a dedicated DMA resource. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_enable_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - Assert(resource); - - resource->callback_enable |= 1 << type; - g_chan_interrupt_flag[resource->channel_id] |= (1UL << type); -} - -/** - * \brief Disable a callback function for a dedicated DMA resource. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_disable_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - Assert(resource); - - resource->callback_enable &= ~(1 << type); - g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK); - DMAC->CHINTENCLR.reg = (1UL << type); -} - -/** - * \brief Register a callback function for a dedicated DMA resource. - * - * There are three types of callback functions, which can be registered: - * - Callback for transfer complete - * - Callback for transfer error - * - Callback for channel suspend - * - * \param[in] resource Pointer to the DMA resource - * \param[in] callback Pointer to the callback function - * \param[in] type Callback function type - * - */ -static inline void dma_register_callback(struct dma_resource *resource, - dma_callback_t callback, enum dma_callback_type type) -{ - Assert(resource); - - resource->callback[type] = callback; -} - -/** - * \brief Unregister a callback function for a dedicated DMA resource. - * - * There are three types of callback functions: - * - Callback for transfer complete - * - Callback for transfer error - * - Callback for channel suspend - * - * The application can unregister any of the callback functions which - * are already registered and are no longer needed. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_unregister_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - Assert(resource); - - resource->callback[type] = NULL; -} - -/** - * \brief Will set a software trigger for resource. - * - * This function is used to set a software trigger on the DMA channel - * associated with resource. If a trigger is already pending no new trigger - * will be generated for the channel. - * - * \param[in] resource Pointer to the DMA resource - */ -static inline void dma_trigger_transfer(struct dma_resource *resource) -{ - Assert(resource); - - DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id); -} - -/** - * \brief Initializes DMA transfer configuration with predefined default values. - * - * This function will initialize a given DMA descriptor configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structure before being - * modified by the user application. - * - * The default configuration is as follows: - * \li Set the descriptor as valid - * \li Disable event output - * \li No block action - * \li Set beat size as byte - * \li Enable source increment - * \li Enable destination increment - * \li Step size is applied to the destination address - * \li Address increment is beat size multiplied by 1 - * \li Default transfer size is set to 0 - * \li Default source address is set to NULL - * \li Default destination address is set to NULL - * \li Default next descriptor not available - * \param[out] config Pointer to the configuration - * - */ -static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config) -{ - Assert(config); - - /* Set descriptor as valid */ - config->descriptor_valid = true; - /* Disable event output */ - config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE; - /* No block action */ - config->block_action = DMA_BLOCK_ACTION_NOACT; - /* Set beat size to one byte */ - config->beat_size = DMA_BEAT_SIZE_BYTE; - /* Enable source increment */ - config->src_increment_enable = true; - /* Enable destination increment */ - config->dst_increment_enable = true; - /* Step size is applied to the destination address */ - config->step_selection = DMA_STEPSEL_DST; - /* Address increment is beat size multiplied by 1*/ - config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1; - /* Default transfer size is set to 0 */ - config->block_transfer_count = 0; - /* Default source address is set to NULL */ - config->source_address = (uint32_t)NULL; - /* Default destination address is set to NULL */ - config->destination_address = (uint32_t)NULL; - /** Next descriptor address set to 0 */ - config->next_descriptor_address = 0; -} - -/** - * \brief Update DMA descriptor. - * - * This function can update the descriptor of an allocated DMA resource. - * - */ -static inline void dma_update_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor) -{ - Assert(resource); - - resource->descriptor = descriptor; -} - -/** - * \brief Reset DMA descriptor. - * - * This function will clear the DESCADDR register of an allocated DMA resource. - * - */ -static inline void dma_reset_descriptor(struct dma_resource *resource) -{ - Assert(resource); - - resource->descriptor = NULL; -} - -void dma_get_config_defaults(struct dma_resource_config *config); -enum status_code dma_allocate(struct dma_resource *resource, - struct dma_resource_config *config); -enum status_code dma_free(struct dma_resource *resource); -enum status_code dma_start_transfer_job(struct dma_resource *resource); -void dma_abort_job(struct dma_resource *resource); -void dma_suspend_job(struct dma_resource *resource); -void dma_resume_job(struct dma_resource *resource); -void dma_descriptor_create(DmacDescriptor* descriptor, - struct dma_descriptor_config *config); -enum status_code dma_add_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor); - -/** @} */ - -/** - * \page asfdoc_sam0_dma_extra Extra Information for DMAC Driver - * - * \section asfdoc_sam0_dma_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DMADirect Memory Access
DMACDirect Memory Access Controller
CPUCentral Processing Unit
- * - * - * \section asfdoc_sam0_dma_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_clock_group "System Clock Driver" - * - * - * \section asfdoc_sam0_dma_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_dma_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Add SAM C21 support
Add SAM L21 support
Initial Release
- */ - -/** -* \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver -* -* This is a list of the available Quick Start Guides (QSGs) and example -* applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with -* step-by-step instructions to configure and use this driver in a selection of -* use cases. Note that QSGs can be compiled as a standalone application or be -* added to the user application. -* -* - \subpage asfdoc_sam0_dma_basic_use_case -* -* \note More DMA usage examples are available in peripheral QSGs. -* A quick start guide for TC/TCC -* shows the usage of DMA event trigger; SERCOM SPI/USART/I2C has example for -* DMA transfer from peripheral to memory or from memory to peripheral; -* ADC/DAC shows peripheral to peripheral transfer. -* -* \page asfdoc_sam0_dma_document_revision_history Document Revision History -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
Doc. Rev. -* Date -* Comments -*
C06/2015Added SAML21, SAMC21, and SAMDAx support
B12/2014Added SAMR21 and SAMD10/D11 support
A02/2014Initial release
-*/ - -#ifdef __cplusplus -} -#endif - -#endif /* DMA_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma_crc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma_crc.h deleted file mode 100644 index f32274f33f6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma_crc.h +++ /dev/null @@ -1,230 +0,0 @@ -/** - * \file - * - * \brief SAM DMA cyclic redundancy check (CRC) Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DMA_CRC_H_INCLUDED -#define DMA_CRC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** DMA channel n offset. */ -#define DMA_CRC_CHANNEL_N_OFFSET 0x20 - -/** CRC Polynomial Type. */ -enum crc_polynomial_type { - /** CRC16 (CRC-CCITT). */ - CRC_TYPE_16, - /** CRC32 (IEEE 802.3). */ - CRC_TYPE_32, -}; - -/** CRC Beat Type. */ -enum crc_beat_size { - /** Byte bus access. */ - CRC_BEAT_SIZE_BYTE, - /** Half-word bus access. */ - CRC_BEAT_SIZE_HWORD, - /** Word bus access. */ - CRC_BEAT_SIZE_WORD, -}; - -/** Configurations for CRC calculation. */ -struct dma_crc_config { - /** CRC polynomial type. */ - enum crc_polynomial_type type; - /** CRC beat size. */ - enum crc_beat_size size; -}; - -/** - * \brief Get DMA CRC default configurations. - * - * The default configuration is as follows: - * \li Polynomial type is set to CRC-16(CRC-CCITT) - * \li CRC Beat size: BYTE - * - * \param[in] config default configurations - */ -static inline void dma_crc_get_config_defaults(struct dma_crc_config *config) -{ - Assert(config); - - config->type = CRC_TYPE_16; - config->size = CRC_BEAT_SIZE_BYTE; -} - -/** - * \brief Enable DMA CRC module with an DMA channel. - * - * This function enables a CRC calculation with an allocated DMA channel. This channel ID - * can be gotten from a successful \ref dma_allocate. - * - * \param[in] channel_id DMA channel expected with CRC calculation - * \param[in] config CRC calculation configurations - * - * \return Status of the DMC CRC. - * \retval STATUS_OK Get the DMA CRC module - * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet - */ -static inline enum status_code dma_crc_channel_enable(uint32_t channel_id, - struct dma_crc_config *config) -{ - if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { - return STATUS_BUSY; - } - - DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | - DMAC_CRCCTRL_CRCPOLY(config->type) | - DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET); - - DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; - - return STATUS_OK; -} - -/** - * \brief Disable DMA CRC module. - * - */ -static inline void dma_crc_disable(void) -{ - DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; - DMAC->CRCCTRL.reg = 0; -} - -/** - * \brief Get DMA CRC checksum value. - * - * \return Calculated CRC checksum. - */ -static inline uint32_t dma_crc_get_checksum(void) -{ - if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) { - DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; - } - - return DMAC->CRCCHKSUM.reg; -} - -/** - * \brief Enable DMA CRC module with I/O. - * - * This function enables a CRC calculation with I/O mode. - * - * \param[in] config CRC calculation configurations. - * - * \return Status of the DMC CRC. - * \retval STATUS_OK Get the DMA CRC module - * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet - */ -static inline enum status_code dma_crc_io_enable( - struct dma_crc_config *config) -{ - if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { - return STATUS_BUSY; - } - - if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) { - return STATUS_BUSY; - } - - DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | - DMAC_CRCCTRL_CRCPOLY(config->type) | - DMAC_CRCCTRL_CRCSRC_IO; - - if (config->type == CRC_TYPE_32) { - DMAC->CRCCHKSUM.reg = 0xFFFFFFFF; - } - - DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; - - return STATUS_OK; -} - -/** - * \brief Calculate CRC with I/O. - * - * This function calculate the CRC of the input data buffer. - * - * \param[in] buffer CRC Pointer to calculation buffer - * \param[in] total_beat_size Total beat size to be calculated - * - * \return Calculated CRC checksum value. - */ -static inline void dma_crc_io_calculation(void *buffer, - uint32_t total_beat_size) -{ - uint32_t counter = total_beat_size; - uint8_t *buffer_8; - uint16_t *buffer_16; - uint32_t *buffer_32; - - for (counter=0; counterCRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) { - buffer_8 = buffer; - DMAC->CRCDATAIN.reg = buffer_8[counter]; - } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) { - buffer_16 = buffer; - DMAC->CRCDATAIN.reg = buffer_16[counter]; - } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) { - buffer_32 = buffer; - DMAC->CRCDATAIN.reg = buffer_32[counter]; - } - /* Wait several cycle to make sure CRC complete */ - nop(); - nop(); - nop(); - nop(); - } -} - -#ifdef __cplusplus -} -#endif - -#endif /* DMA_CRC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMD21/extint.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMD21/extint.c deleted file mode 100644 index aab86fedf9e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMD21/extint.c +++ /dev/null @@ -1,425 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include -#include - -#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__) -# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0. - -/** Configuration option, setting the EIC clock source which can be used for - * EIC edge detection or filtering. This option may be overridden in the module - * configuration header file \c conf_extint.h. - */ -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 -#endif - -/** - * \internal - * Internal driver device instance struct. - */ -struct _extint_module _extint_dev; - -/** - * \brief Determin if the general clock is required - * - * \param[in] filter_input_signal Filter the raw input signal to prevent noise - * \param[in] detection_criteria Edge detection mode to use (\ref extint_detect) - */ -#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \ - ((filter_input_signal) ? true : (\ - (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false)))) - -static void _extint_enable(void); -static void _extint_disable(void); - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true If the module synchronization is ongoing - * \retval false If the module has completed synchronization - */ -static inline bool extint_is_syncing(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) { - return true; - } - } - return false; -} -/** - * \internal - * \brief Initializes and enables the External Interrupt driver. - * - * Enable the clocks used by External Interrupt driver. - * - * Resets the External Interrupt driver, resetting all hardware - * module registers to their power-on defaults, then enable it for further use. - * - * Reset the callback list if callback mode is used. - * - * This function must be called before attempting to use any NMI or standard - * external interrupt channel functions. - * - * \note When SYSTEM module is used, this function will be invoked by - * \ref system_init() automatically if the module is included. - */ -void _system_extint_init(void); -void _system_extint_init(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC); - - /* Configure the generic clock for the module and enable it */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; - system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); - - /* Enable the clock anyway, since when needed it will be requested - * by External Interrupt driver */ - system_gclk_chan_enable(EIC_GCLK_ID); - - /* Reset all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg |= EIC_CTRL_SWRST; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } - - /* Reset the software module */ -#if EXTINT_CALLBACK_MODE == true - /* Clear callback registration table */ - for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { - _extint_dev.callbacks[j] = NULL; - } - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); -#endif - - /* Enables the driver for further use */ - _extint_enable(); -} - -/** - * \internal - * \brief Enables the External Interrupt driver. - * - * Enables EIC modules. - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_enable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Enable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg |= EIC_CTRL_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \internal - * \brief Disables the External Interrupt driver. - * - * Disables EIC modules that were previously started via a call to - * \ref _extint_enable(). - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_disable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Disable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \brief Initializes an External Interrupt channel configuration structure to defaults. - * - * Initializes a given External Interrupt channel configuration structure to a - * set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Wake the device if an edge detection occurs whilst in sleep - * \li Input filtering disabled - * \li Internal pull-up enabled - * \li Detect falling edges of a signal - * - * \param[out] config Configuration structure to initialize to default values - */ -void extint_chan_get_config_defaults( - struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->wake_if_sleeping = true; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; -} - -/** - * \brief Writes an External Interrupt channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] channel External Interrupt channel to configure - * \param[in] config Configuration settings for the channel - - */ -void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(channel); - - uint32_t config_pos = (4 * (channel % 8)); - uint32_t new_config; - - /* Determine the channel's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_CONFIG_FILTEN0; - } - - /* Clear the existing and set the new channel configuration */ - EIC_module->CONFIG[channel / 8].reg - = (EIC_module->CONFIG[channel / 8].reg & - ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | - (new_config << config_pos); - - /* Set the channel's new wake up mode setting */ - if (config->wake_if_sleeping) { - EIC_module->WAKEUP.reg |= (1UL << channel); - } else { - EIC_module->WAKEUP.reg &= ~(1UL << channel); - } -} - -/** - * \brief Writes an External Interrupt NMI channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt NMI channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] nmi_channel External Interrupt NMI channel to configure - * \param[in] config Configuration settings for the channel - * - * \returns Status code indicating the success or failure of the request. - * \retval STATUS_OK Configuration succeeded - * \retval STATUS_ERR_PIN_MUX_INVALID An invalid pinmux value was supplied - * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested - */ -enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); - - uint32_t new_config; - - /* Determine the NMI's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_NMICTRL_NMIFILTEN; - } - - /* Disable EIC and general clock to configure NMI */ - _extint_disable(); - system_gclk_chan_disable(EIC_GCLK_ID); - - EIC_module->NMICTRL.reg = new_config; - - /* Enable the general clock and EIC after configure NMI */ - system_gclk_chan_enable(EIC_GCLK_ID); - _extint_enable(); - - return STATUS_OK; -} - -/** - * \brief Enables an External Interrupt event output. - * - * Enables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to enable - */ -void extint_enable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create an enable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Enable the masked events */ - eics[i]->EVCTRL.reg |= event_mask; - } -} - -/** - * \brief Disables an External Interrupt event output. - * - * Disables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to disable - */ -void extint_disable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create a disable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Disable the masked events */ - eics[i]->EVCTRL.reg &= ~event_mask; - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAML21/extint.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAML21/extint.c deleted file mode 100644 index e7b36100236..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAML21/extint.c +++ /dev/null @@ -1,481 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include -#include - -#if !defined(EXTINT_CLOCK_SELECTION) || defined(__DOXYGEN__) -# warning EXTINT_CLOCK_SELECTION is not defined, assuming EXTINT_CLK_GCLK. - -/** Configuration option, setting the EIC clock source which can be used for - * EIC edge detection or filtering. This option may be overridden in the module - * configuration header file \c conf_extint.h. - */ -# define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK -#endif - -#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) -#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__) -# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0. - -/** Configuration option, setting the EIC clock source which can be used for - * EIC edge detection or filtering. This option may be overridden in the module - * configuration header file \c conf_extint.h. - */ -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 -#endif -#endif - -/** - * \internal - * Internal driver device instance struct. - */ -struct _extint_module _extint_dev; - -/** - * \brief Determin if the general clock is required. - * - * \param[in] filter_input_signal Filter the raw input signal to prevent noise - * \param[in] detection_criteria Edge detection mode to use (\ref extint_detect) - */ -#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \ - ((filter_input_signal) ? true : (\ - (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false)))) - -static void _extint_enable(void); -static void _extint_disable(void); - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true If the module synchronization is ongoing - * \retval false If the module has completed synchronization - */ -static inline bool extint_is_syncing(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - if((eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) - || (eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST)) { - return true; - } - } - return false; -} - -/** - * \internal - * \brief Initializes and enables the External Interrupt driver. - * - * Enable the clocks used by External Interrupt driver. - * - * Resets the External Interrupt driver, resetting all hardware - * module registers to their power-on defaults, then enable it for further use. - * - * Reset the callback list if callback mode is used. - * - * This function must be called before attempting to use any NMI or standard - * external interrupt channel functions. - * - * \note When SYSTEM module is used, this function will be invoked by - * \ref system_init() automatically if the module is included. - */ -void _system_extint_init(void); -void _system_extint_init(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_EIC); - -#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - /* Configure the generic clock for the module and enable it */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; - system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); - - /* Enable the clock anyway, since when needed it will be requested - * by External Interrupt driver */ - system_gclk_chan_enable(EIC_GCLK_ID); -#endif - - /* Reset all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.reg |= EIC_CTRLA_SWRST; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } - -#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK; - } -#else - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K; - } -#endif - - /* Reset the software module */ -#if EXTINT_CALLBACK_MODE == true - /* Clear callback registration table */ - for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { - _extint_dev.callbacks[j] = NULL; - } - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); -#endif - - /* Enables the driver for further use */ - _extint_enable(); -} - -/** - * \internal - * \brief Enables the External Interrupt driver. - * - * Enables EIC modules. - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_enable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Enable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.reg |= EIC_CTRLA_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \internal - * \brief Disables the External Interrupt driver. - * - * Disables EIC modules that were previously started via a call to - * \ref _extint_enable(). - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_disable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Disable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.reg &= ~EIC_CTRLA_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \brief Initializes an External Interrupt channel configuration structure to defaults. - * - * Initializes a given External Interrupt channel configuration structure to a - * set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Input filtering disabled - * \li Internal pull-up enabled - * \li Detect falling edges of a signal - * \li Asynchronous edge detection is disabled - * - * \param[out] config Configuration structure to initialize to default values - */ -void extint_chan_get_config_defaults( - struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; - config->enable_async_edge_detection = false; -} - -/** - * \brief Writes an External Interrupt channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] channel External Interrupt channel to configure - * \param[in] config Configuration settings for the channel - - */ -void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - _extint_disable(); -#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); -#endif - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(channel); - - uint32_t config_pos = (4 * (channel % 8)); - uint32_t new_config; - - /* Determine the channel's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_CONFIG_FILTEN0; - } - - /* Clear the existing and set the new channel configuration */ - EIC_module->CONFIG[channel / 8].reg - = (EIC_module->CONFIG[channel / 8].reg & - ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | - (new_config << config_pos); - - /* Config asynchronous edge detection */ - if (config->enable_async_edge_detection) { - EIC_module->EIC_ASYNCH.reg |= (1UL << channel); - } else { - EIC_module->EIC_ASYNCH.reg &= (EIC_EIC_ASYNCH_MASK & (~(1UL << channel))); - } - - _extint_enable(); -} - -/** - * \brief Writes an External Interrupt NMI channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt NMI channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] nmi_channel External Interrupt NMI channel to configure - * \param[in] config Configuration settings for the channel - * - * \returns Status code indicating the success or failure of the request. - * \retval STATUS_OK Configuration succeeded - * \retval STATUS_ERR_PIN_MUX_INVALID An invalid pin mux value was supplied - * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested - */ -enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); - - uint32_t new_config; - - /* Determine the NMI's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_NMICTRL_NMIFILTEN; - } - - /* Enable asynchronous edge detection if requested in the config */ - if (config->enable_async_edge_detection) { - new_config |= EIC_NMICTRL_NMIASYNCH; - } - - /* Disable EIC and general clock to configure NMI */ - _extint_disable(); -#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - system_gclk_chan_disable(EIC_GCLK_ID); -#else - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK; - system_gclk_chan_disable(EIC_GCLK_ID); - } -#endif - - EIC_module->NMICTRL.reg = new_config; - - /* Enable the EIC clock and EIC after configure NMI */ -#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - system_gclk_chan_enable(EIC_GCLK_ID); -#else - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K; - } -#endif - _extint_enable(); - - return STATUS_OK; -} - -/** - * \brief Enables an External Interrupt event output. - * - * Enables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to enable - */ -void extint_enable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - _extint_disable(); - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create an enable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Enable the masked events */ - eics[i]->EVCTRL.reg |= event_mask; - } - _extint_enable(); -} - -/** - * \brief Disables an External Interrupt event output. - * - * Disables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to disable - */ -void extint_disable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - _extint_disable(); - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create a disable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Disable the masked events */ - eics[i]->EVCTRL.reg &= ~event_mask; - } - _extint_enable(); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMR21/extint.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMR21/extint.c deleted file mode 100644 index aab86fedf9e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMR21/extint.c +++ /dev/null @@ -1,425 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include -#include - -#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__) -# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0. - -/** Configuration option, setting the EIC clock source which can be used for - * EIC edge detection or filtering. This option may be overridden in the module - * configuration header file \c conf_extint.h. - */ -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 -#endif - -/** - * \internal - * Internal driver device instance struct. - */ -struct _extint_module _extint_dev; - -/** - * \brief Determin if the general clock is required - * - * \param[in] filter_input_signal Filter the raw input signal to prevent noise - * \param[in] detection_criteria Edge detection mode to use (\ref extint_detect) - */ -#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \ - ((filter_input_signal) ? true : (\ - (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false)))) - -static void _extint_enable(void); -static void _extint_disable(void); - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true If the module synchronization is ongoing - * \retval false If the module has completed synchronization - */ -static inline bool extint_is_syncing(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) { - return true; - } - } - return false; -} -/** - * \internal - * \brief Initializes and enables the External Interrupt driver. - * - * Enable the clocks used by External Interrupt driver. - * - * Resets the External Interrupt driver, resetting all hardware - * module registers to their power-on defaults, then enable it for further use. - * - * Reset the callback list if callback mode is used. - * - * This function must be called before attempting to use any NMI or standard - * external interrupt channel functions. - * - * \note When SYSTEM module is used, this function will be invoked by - * \ref system_init() automatically if the module is included. - */ -void _system_extint_init(void); -void _system_extint_init(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC); - - /* Configure the generic clock for the module and enable it */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; - system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); - - /* Enable the clock anyway, since when needed it will be requested - * by External Interrupt driver */ - system_gclk_chan_enable(EIC_GCLK_ID); - - /* Reset all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg |= EIC_CTRL_SWRST; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } - - /* Reset the software module */ -#if EXTINT_CALLBACK_MODE == true - /* Clear callback registration table */ - for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { - _extint_dev.callbacks[j] = NULL; - } - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); -#endif - - /* Enables the driver for further use */ - _extint_enable(); -} - -/** - * \internal - * \brief Enables the External Interrupt driver. - * - * Enables EIC modules. - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_enable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Enable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg |= EIC_CTRL_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \internal - * \brief Disables the External Interrupt driver. - * - * Disables EIC modules that were previously started via a call to - * \ref _extint_enable(). - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_disable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Disable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \brief Initializes an External Interrupt channel configuration structure to defaults. - * - * Initializes a given External Interrupt channel configuration structure to a - * set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Wake the device if an edge detection occurs whilst in sleep - * \li Input filtering disabled - * \li Internal pull-up enabled - * \li Detect falling edges of a signal - * - * \param[out] config Configuration structure to initialize to default values - */ -void extint_chan_get_config_defaults( - struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->wake_if_sleeping = true; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; -} - -/** - * \brief Writes an External Interrupt channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] channel External Interrupt channel to configure - * \param[in] config Configuration settings for the channel - - */ -void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(channel); - - uint32_t config_pos = (4 * (channel % 8)); - uint32_t new_config; - - /* Determine the channel's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_CONFIG_FILTEN0; - } - - /* Clear the existing and set the new channel configuration */ - EIC_module->CONFIG[channel / 8].reg - = (EIC_module->CONFIG[channel / 8].reg & - ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | - (new_config << config_pos); - - /* Set the channel's new wake up mode setting */ - if (config->wake_if_sleeping) { - EIC_module->WAKEUP.reg |= (1UL << channel); - } else { - EIC_module->WAKEUP.reg &= ~(1UL << channel); - } -} - -/** - * \brief Writes an External Interrupt NMI channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt NMI channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] nmi_channel External Interrupt NMI channel to configure - * \param[in] config Configuration settings for the channel - * - * \returns Status code indicating the success or failure of the request. - * \retval STATUS_OK Configuration succeeded - * \retval STATUS_ERR_PIN_MUX_INVALID An invalid pinmux value was supplied - * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested - */ -enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); - - uint32_t new_config; - - /* Determine the NMI's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_NMICTRL_NMIFILTEN; - } - - /* Disable EIC and general clock to configure NMI */ - _extint_disable(); - system_gclk_chan_disable(EIC_GCLK_ID); - - EIC_module->NMICTRL.reg = new_config; - - /* Enable the general clock and EIC after configure NMI */ - system_gclk_chan_enable(EIC_GCLK_ID); - _extint_enable(); - - return STATUS_OK; -} - -/** - * \brief Enables an External Interrupt event output. - * - * Enables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to enable - */ -void extint_enable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create an enable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Enable the masked events */ - eics[i]->EVCTRL.reg |= event_mask; - } -} - -/** - * \brief Disables an External Interrupt event output. - * - * Disables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to disable - */ -void extint_disable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create a disable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Disable the masked events */ - eics[i]->EVCTRL.reg &= ~event_mask; - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint.h deleted file mode 100644 index b03fd03f436..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint.h +++ /dev/null @@ -1,705 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef EXTINT_H_INCLUDED -#define EXTINT_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_extint_group SAM External Interrupt Driver (EXTINT) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of external interrupts generated by the physical device pins, - * including edge detection. The following driver API modes are covered by this - * manual: - * - * - Polled APIs - * \if EXTINT_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripherals are used by this module: - * - EIC (External Interrupt Controller) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_extint_prerequisites - * - \ref asfdoc_sam0_extint_module_overview - * - \ref asfdoc_sam0_extint_special_considerations - * - \ref asfdoc_sam0_extint_extra_info - * - \ref asfdoc_sam0_extint_examples - * - \ref asfdoc_sam0_extint_api_overview - * - * - * \section asfdoc_sam0_extint_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_extint_module_overview Module Overview - * - * The External Interrupt (EXTINT) module provides a method of asynchronously - * detecting rising edge, falling edge or specific level detection on individual - * I/O pins of a device. This detection can then be used to trigger a software - * interrupt or event, or polled for later use if required. External interrupts - * can also optionally be used to automatically wake up the device from sleep - * mode, allowing the device to conserve power while still being able to react - * to an external stimulus in a timely manner. - * - * \subsection asfdoc_sam0_extint_logical_channels Logical Channels - * The External Interrupt module contains a number of logical channels, each of - * which is capable of being individually configured for a given pin routing, - * detection mode, and filtering/wake up characteristics. - * - * Each individual logical external interrupt channel may be routed to a single - * physical device I/O pin in order to detect a particular edge or level of the - * incoming signal. - * - * \subsection asfdoc_sam0_extint_module_overview_nmi_chanel NMI Channels - * - * One or more Non Maskable Interrupt (NMI) channels are provided within each - * physical External Interrupt Controller module, allowing a single physical pin - * of the device to fire a single NMI interrupt in response to a particular - * edge or level stimulus. A NMI cannot, as the name suggests, be disabled in - * firmware and will take precedence over any in-progress interrupt sources. - * - * NMIs can be used to implement critical device features such as forced - * software reset or other functionality where the action should be executed in - * preference to all other running code with a minimum amount of latency. - * - * \subsection asfdoc_sam0_extint_module_overview_filtering Input Filtering and Detection - * - * To reduce the possibility of noise or other transient signals causing - * unwanted device wake-ups, interrupts and/or events via an external interrupt - * channel, a hardware signal filter can be enabled on individual channels. This - * filter provides a Majority-of-Three voter filter on the incoming signal, so - * that the input state is considered to be the majority vote of three - * subsequent samples of the pin input buffer. The possible sampled input and - * resulting filtered output when the filter is enabled is shown in - * \ref asfdoc_sam0_extint_filter_table "the table below". - * - * \anchor asfdoc_sam0_extint_filter_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Sampled Input and Rresulting Filtered Output
Input Sample 1Input Sample 2Input Sample 3Filtered Output
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
- * - * \subsection asfdoc_sam0_extint_module_overview_events Events and Interrupts - * - * Channel detection states may be polled inside the application for synchronous - * detection, or events and interrupts may be used for asynchronous behavior. - * Each channel can be configured to give an asynchronous hardware event (which - * may in turn trigger actions in other hardware modules) or an asynchronous - * software interrupt. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * \subsection asfdoc_sam0_extint_module_overview_physical Physical Connection - * - * \ref asfdoc_sam0_extint_int_connections "The diagram below" shows how this - * module is interconnected within the device. - * - * \anchor asfdoc_sam0_extint_int_connections - * \dot - * digraph overview { - * node [label="Port Pad" shape=square] pad; - * - * subgraph driver { - * node [label="Peripheral MUX" shape=trapezium] pinmux; - * node [label="EIC Module" shape=ellipse] eic; - * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals; - * } - * - * pinmux -> eic; - * pad -> pinmux; - * pinmux -> peripherals; - * } - * \enddot - * - * \section asfdoc_sam0_extint_special_considerations Special Considerations - * - * Not all devices support disabling of the NMI channel(s) detection mode - see - * your device datasheet. - * - * - * \section asfdoc_sam0_extint_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_extint_extra. This includes: - * - \ref asfdoc_sam0_extint_extra_acronyms - * - \ref asfdoc_sam0_extint_extra_dependencies - * - \ref asfdoc_sam0_extint_extra_errata - * - \ref asfdoc_sam0_extint_extra_history - * - * - * \section asfdoc_sam0_extint_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_extint_exqsg. - * - * - * \section asfdoc_sam0_extint_api_overview API Overview - * @{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief External interrupt edge detection configuration enum. - * - * Enum for the possible signal edge detection modes of the External - * Interrupt Controller module. - */ -enum extint_detect { - /** No edge detection. Not allowed as a NMI detection mode on some - * devices. */ - EXTINT_DETECT_NONE = 0, - /** Detect rising signal edges. */ - EXTINT_DETECT_RISING = 1, - /** Detect falling signal edges. */ - EXTINT_DETECT_FALLING = 2, - /** Detect both signal edges. */ - EXTINT_DETECT_BOTH = 3, - /** Detect high signal levels. */ - EXTINT_DETECT_HIGH = 4, - /** Detect low signal levels. */ - EXTINT_DETECT_LOW = 5, -}; - -/** - * \brief External interrupt internal pull configuration enum. - * - * Enum for the possible pin internal pull configurations. - * - * \note Disabling the internal pull resistor is not recommended if the driver - * is used in interrupt (callback) mode, due the possibility of floating - * inputs generating continuous interrupts. - */ -enum extint_pull { - /** Internal pull-up resistor is enabled on the pin. */ - EXTINT_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, - /** Internal pull-down resistor is enabled on the pin. */ - EXTINT_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, - /** Internal pull resistor is disconnected from the pin. */ - EXTINT_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, -}; - -/** The EIC is clocked by GCLK_EIC. */ -#define EXTINT_CLK_GCLK 0 -/** The EIC is clocked by CLK_ULP32K. */ -#define EXTINT_CLK_ULP32K 1 - -/** - * \brief External Interrupt Controller channel configuration structure. - * - * Configuration structure for the edge detection mode of an external - * interrupt channel. - */ -struct extint_chan_conf { - /** GPIO pin the NMI should be connected to. */ - uint32_t gpio_pin; - /** MUX position the GPIO pin should be configured to. */ - uint32_t gpio_pin_mux; - /** Internal pull to enable on the input pin. */ - enum extint_pull gpio_pin_pull; -#if (SAML21) || (SAMC20) || (SAMC21) - /** Enable asynchronous edge detection. */ - bool enable_async_edge_detection; -#else - /** Wake up the device if the channel interrupt fires during sleep mode. */ - bool wake_if_sleeping; -#endif - /** Filter the raw input signal to prevent noise from triggering an - * interrupt accidentally, using a 3 sample majority filter. */ - bool filter_input_signal; - /** Edge detection mode to use. */ - enum extint_detect detection_criteria; -}; - -/** - * \brief External Interrupt event enable/disable structure. - * - * Event flags for the \ref extint_enable_events() and - * \ref extint_disable_events(). - */ -struct extint_events { - /** If \c true, an event will be generated when an external interrupt - * channel detection state changes. */ - bool generate_event_on_detect[32 * EIC_INST_NUM]; -}; - -/** - * \brief External Interrupt Controller NMI configuration structure. - * - * Configuration structure for the edge detection mode of an external - * interrupt NMI channel. - */ -struct extint_nmi_conf { - /** GPIO pin the NMI should be connected to. */ - uint32_t gpio_pin; - /** MUX position the GPIO pin should be configured to. */ - uint32_t gpio_pin_mux; - /** Internal pull to enable on the input pin. */ - enum extint_pull gpio_pin_pull; - /** Filter the raw input signal to prevent noise from triggering an - * interrupt accidentally, using a 3 sample majority filter. */ - bool filter_input_signal; - /** Edge detection mode to use. Not all devices support all possible - * detection modes for NMIs. - */ - enum extint_detect detection_criteria; -#if (SAML21) || (SAMC20) || (SAMC21) - /** Enable asynchronous edge detection. */ - bool enable_async_edge_detection; -#endif -}; - -#if EXTINT_CALLBACK_MODE == true -/** Type definition for an EXTINT module callback function. */ -typedef void (*extint_callback_t)(void); - -#ifndef EIC_NUMBER_OF_INTERRUPTS -# define EIC_NUMBER_OF_INTERRUPTS 16 -#endif -#endif - -#if !defined(__DOXYGEN__) -/** \internal - * Internal EXTINT module device instance structure definition. - */ -struct _extint_module { -# if EXTINT_CALLBACK_MODE == true - /** Asynchronous channel callback table, for user-registered handlers. */ - extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS]; -# else - /** Dummy value to ensure the struct has at least one member. */ - uint8_t _dummy; -# endif -}; - -/** - * \brief Retrieves the base EIC module address from a given channel number. - * - * Retrieves the base address of a EIC hardware module associated with the - * given external interrupt channel. - * - * \param[in] channel External interrupt channel index to convert - * - * \return Base address of the associated EIC module. - */ -static inline Eic * _extint_get_eic_from_channel( - const uint8_t channel) -{ - uint8_t eic_index = (channel / 32); - - if (eic_index < EIC_INST_NUM) { - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - return eics[eic_index]; - } else { - Assert(false); - return NULL; - } -} - -/** - * \brief Retrieves the base EIC module address from a given NMI channel number. - * - * Retrieves the base address of a EIC hardware module associated with the - * given non-maskable external interrupt channel. - * - * \param[in] nmi_channel Non-Maskable interrupt channel index to convert - * - * \return Base address of the associated EIC module. - */ -static inline Eic * _extint_get_eic_from_nmi( - const uint8_t nmi_channel) -{ - uint8_t eic_index = nmi_channel; - - if (eic_index < EIC_INST_NUM) { - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - return eics[eic_index]; - } else { - Assert(false); - return NULL; - } -} -#endif - -/** \name Event Management - * @{ - */ - -void extint_enable_events( - struct extint_events *const events); - -void extint_disable_events( - struct extint_events *const events); - -/** @} */ - -/** \name Configuration and Initialization (Channel) - * @{ - */ - -void extint_chan_get_config_defaults( - struct extint_chan_conf *const config); - -void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config); - -/** @} */ - -/** \name Configuration and Initialization (NMI) - * @{ - */ - -/** - * \brief Initializes an External Interrupt NMI channel configuration structure to defaults. - * - * Initializes a given External Interrupt NMI channel configuration structure - * to a set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Input filtering disabled - * \li Detect falling edges of a signal - * \li Asynchronous edge detection is disabled - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void extint_nmi_get_config_defaults( - struct extint_nmi_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; -#if (SAML21) || (SAMC20) || (SAMC21) - config->enable_async_edge_detection = false; -#endif - -} - -enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config); - -/** @} */ - -/** \name Detection testing and clearing (channel) - * @{ - */ - -/** - * \brief Retrieves the edge detection state of a configured channel. - * - * Reads the current state of a configured channel, and determines - * if the detection criteria of the channel has been met. - * - * \param[in] channel External Interrupt channel index to check - * - * \return Status of the requested channel's edge detection state. - * \retval true If the channel's edge/level detection criteria was met - * \retval false If the channel has not detected its configured criteria - */ -static inline bool extint_chan_is_detected( - const uint8_t channel) -{ - Eic *const eic_module = _extint_get_eic_from_channel(channel); - uint32_t eic_mask = (1UL << (channel % 32)); - - return (eic_module->INTFLAG.reg & eic_mask); -} - -/** - * \brief Clears the edge detection state of a configured channel. - * - * Clears the current state of a configured channel, readying it for - * the next level or edge detection. - * - * \param[in] channel External Interrupt channel index to check - */ -static inline void extint_chan_clear_detected( - const uint8_t channel) -{ - Eic *const eic_module = _extint_get_eic_from_channel(channel); - uint32_t eic_mask = (1UL << (channel % 32)); - - eic_module->INTFLAG.reg = eic_mask; -} - -/** @} */ - -/** \name Detection Testing and Clearing (NMI) - * @{ - */ - -/** - * \brief Retrieves the edge detection state of a configured NMI channel. - * - * Reads the current state of a configured NMI channel, and determines - * if the detection criteria of the NMI channel has been met. - * - * \param[in] nmi_channel External Interrupt NMI channel index to check - * - * \return Status of the requested NMI channel's edge detection state. - * \retval true If the NMI channel's edge/level detection criteria was met - * \retval false If the NMI channel has not detected its configured criteria - */ -static inline bool extint_nmi_is_detected( - const uint8_t nmi_channel) -{ - Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel); - - return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI); -} - -/** - * \brief Clears the edge detection state of a configured NMI channel. - * - * Clears the current state of a configured NMI channel, readying it for - * the next level or edge detection. - * - * \param[in] nmi_channel External Interrupt NMI channel index to check - */ -static inline void extint_nmi_clear_detected( - const uint8_t nmi_channel) -{ - Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel); - - eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#if EXTINT_CALLBACK_MODE == true -# include "extint_callback.h" -#endif - -/** - * \page asfdoc_sam0_extint_extra Extra Information for EXTINT Driver - * - * \section asfdoc_sam0_extint_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
EICExternal Interrupt Controller
MUXMultiplexer
NMINon-Maskable Interrupt
- * - * - * \section asfdoc_sam0_extint_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_extint_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_extint_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
- * \li Driver updated to follow driver type convention. - * \li Removed \c %extint_reset(), \c %extint_disable() and - * \c extint_enable() functions. Added internal function - * \c %_system_extint_init(). - * \li Added configuration EXTINT_CLOCK_SOURCE in conf_extint.h. - * \li Removed configuration EXTINT_CALLBACKS_MAX in conf_extint.h, and - * added channel parameter in the register functions - * \c %extint_register_callback() and \c %extint_unregister_callback(). - *
Updated interrupt handler to clear interrupt flag before calling - * callback function.
Updated initialization function to also enable the digital interface - * clock to the module if it is disabled.
Initial Release
- */ - -/** - * \page asfdoc_sam0_extint_exqsg Examples for EXTINT Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_extint_group. - * QSGs are simple examples with step-by-step instructions to configure and - * use this driver in a selection of use cases. Note that QSGs can be compiled - * as a standalone application or be added to the user application. - * - * - \subpage asfdoc_sam0_extint_basic_use_case - * \if EXTINT_CALLBACK_MODE - * - \subpage asfdoc_sam0_extint_callback_use_case - * \endif - * - * \page asfdoc_sam0_extint_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
E06/2015Added support for SAML21, SAMC21, and SAMDAx.
D12/2014Added support for SAMR21 and SAMD10/D11.
C01/2014Added support for SAMD21.
B06/2013Added additional documentation on the event system. Corrected - * documentation typos.
A06/2013Initial release
- */ - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.c deleted file mode 100644 index 1c65ccfb821..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.c +++ /dev/null @@ -1,230 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "extint.h" -#include "extint_callback.h" - -/** - * \internal - * Internal driver device instance struct, declared in the main module driver. - */ -extern struct _extint_module _extint_dev; - -/** - * \internal - * This is the number of the channel whose callback is currently running. - */ -uint8_t _current_channel; - -/** - * \brief Registers an asynchronous callback function with the driver. - * - * Registers an asynchronous callback with the EXTINT driver, fired when a - * channel detects the configured channel detection criteria - * (e.g. edge or level). Callbacks are fired once for each detected channel. - * - * \note NMI channel callbacks cannot be registered via this function; the - * device's NMI interrupt should be hooked directly in the user - * application and the NMI flags manually cleared via - * \ref extint_nmi_clear_detected(). - * - * \param[in] callback Pointer to the callback function to register - * \param[in] channel Logical channel to register callback for - * \param[in] type Type of callback function to register - * - * \return Status of the registration operation. - * \retval STATUS_OK The callback was registered successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - * \retval STATUS_ERR_ALREADY_INITIALIZED Callback function has been - * registered, need unregister first - */ -enum status_code extint_register_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type) -{ - /* Sanity check arguments */ - Assert(callback); - - if (type != EXTINT_CALLBACK_TYPE_DETECT) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - if (_extint_dev.callbacks[channel] == NULL) { - _extint_dev.callbacks[channel] = callback; - return STATUS_OK; - } else if (_extint_dev.callbacks[channel] == callback) { - return STATUS_OK; - } - - return STATUS_ERR_ALREADY_INITIALIZED; -} - -/** - * \brief Unregisters an asynchronous callback function with the driver. - * - * Unregisters an asynchronous callback with the EXTINT driver, removing it - * from the internal callback registration table. - * - * \param[in] callback Pointer to the callback function to unregister - * \param[in] channel Logical channel to unregister callback for - * \param[in] type Type of callback function to unregister - * - * \return Status of the de-registration operation. - * \retval STATUS_OK The callback was Unregistered successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - * \retval STATUS_ERR_BAD_ADDRESS No matching entry was found in the - * registration table - */ -enum status_code extint_unregister_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type) -{ - /* Sanity check arguments */ - Assert(callback); - - if (type != EXTINT_CALLBACK_TYPE_DETECT) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - if (_extint_dev.callbacks[channel] == callback) { - _extint_dev.callbacks[channel] = NULL; - return STATUS_OK; - } - - return STATUS_ERR_BAD_ADDRESS; -} - -/** - * \brief Enables asynchronous callback generation for a given channel and type. - * - * Enables asynchronous callbacks for a given logical external interrupt channel - * and type. This must be called before an external interrupt channel will - * generate callback events. - * - * \param[in] channel Logical channel to enable callback generation for - * \param[in] type Type of callback function callbacks to enable - * - * \return Status of the callback enable operation. - * \retval STATUS_OK The callback was enabled successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - */ -enum status_code extint_chan_enable_callback( - const uint8_t channel, - const enum extint_callback_type type) -{ - if (type == EXTINT_CALLBACK_TYPE_DETECT) { - Eic *const eic = _extint_get_eic_from_channel(channel); - - eic->INTENSET.reg = (1UL << channel); - } else { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Disables asynchronous callback generation for a given channel and type. - * - * Disables asynchronous callbacks for a given logical external interrupt - * channel and type. - * - * \param[in] channel Logical channel to disable callback generation for - * \param[in] type Type of callback function callbacks to disable - * - * \return Status of the callback disable operation. - * \retval STATUS_OK The callback was disabled successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - */ -enum status_code extint_chan_disable_callback( - const uint8_t channel, - const enum extint_callback_type type) -{ - if (type == EXTINT_CALLBACK_TYPE_DETECT) { - Eic *const eic = _extint_get_eic_from_channel(channel); - - eic->INTENCLR.reg = (1UL << channel); - } else { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Find what channel caused the callback. - * - * Can be used in an EXTINT callback function to find what channel caused - * the callback in case same callback is used by multiple channels. - * - * \return Channel number. - */ -uint8_t extint_get_current_channel(void) -{ - return _current_channel; -} - -/** Handler for the EXTINT hardware module interrupt. */ -void EIC_Handler(void) -{ - /* Find any triggered channels, run associated callback handlers */ - for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) { - if (extint_chan_is_detected(_current_channel)) { - /* Clear flag */ - extint_chan_clear_detected(_current_channel); - /* Find any associated callback entries in the callback table */ - if (_extint_dev.callbacks[_current_channel] != NULL) { - /* Run the registered callback */ - _extint_dev.callbacks[_current_channel](); - } - } - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.h deleted file mode 100644 index cc21155faf2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef EXTINT_CALLBACK_H_INCLUDED -#define EXTINT_CALLBACK_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_extint_group - * - * @{ - */ - -/** \name Callback Configuration and Initialization - * @{ - */ - -/** Enum for the possible callback types for the EXTINT module. */ -enum extint_callback_type { - /** Callback type for when an external interrupt detects the configured - * channel criteria.(i.e. edge or level detection) - */ - EXTINT_CALLBACK_TYPE_DETECT, -}; - -enum status_code extint_register_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type); - -enum status_code extint_unregister_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type); - -uint8_t extint_get_current_channel(void); - -/** @} */ - -/** \name Callback Enabling and Disabling (Channel) - * @{ - */ - -enum status_code extint_chan_enable_callback( - const uint8_t channel, - const enum extint_callback_type type); - -enum status_code extint_chan_disable_callback( - const uint8_t channel, - const enum extint_callback_type type); - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.c deleted file mode 100644 index 5878a3b323b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.c +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief SAM GPIO Port Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -/** - * \brief Writes a Port pin configuration to the hardware module. - * - * Writes out a given configuration of a Port pin configuration to the hardware - * module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] config Configuration settings for the pin - */ -void port_pin_set_config( - const uint8_t gpio_pin, - const struct port_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = SYSTEM_PINMUX_GPIO; - pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull; - pinmux_config.powersave = config->powersave; - - system_pinmux_pin_set_config(gpio_pin, &pinmux_config); -} - -/** - * \brief Writes a Port group configuration group to the hardware module. - * - * Writes out a given configuration of a Port group configuration to the - * hardware module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[out] port Base of the PORT module to write to - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] config Configuration settings for the pin group - */ -void port_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct port_config *const config) -{ - /* Sanity check arguments */ - Assert(port); - Assert(config); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = SYSTEM_PINMUX_GPIO; - pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull; - pinmux_config.powersave = config->powersave; - - system_pinmux_group_set_config(port, mask, &pinmux_config); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.h deleted file mode 100644 index e471791c12b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.h +++ /dev/null @@ -1,789 +0,0 @@ -/** - * \file - * - * \brief SAM GPIO Port Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef PORT_H_INCLUDED -#define PORT_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_port_group SAM Port Driver (PORT) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of the device's General Purpose Input/Output (GPIO) pin - * functionality, for manual pin state reading and writing. - * - * The following peripherals are used by this module: - * - PORT (GPIO Management) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_port_prerequisites - * - \ref asfdoc_sam0_port_module_overview - * - \ref asfdoc_sam0_port_special_considerations - * - \ref asfdoc_sam0_port_extra_info - * - \ref asfdoc_sam0_port_examples - * - \ref asfdoc_sam0_port_api_overview - * - * - * \section asfdoc_sam0_port_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_port_module_overview Module Overview - * - * The device GPIO (PORT) module provides an interface between the user - * application logic and external hardware peripherals, when general pin state - * manipulation is required. This driver provides an easy-to-use interface to - * the physical pin input samplers and output drivers, so that pins can be read - * from or written to for general purpose external hardware control. - * - * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_PORT_INPUT_EVENTSAML21/C20/C21
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins - * SAM devices use two naming conventions for the I/O pins in the device; one - * physical and one logical. Each physical pin on a device package is assigned - * both a physical port and pin identifier (e.g. "PORTA.0") as well as a - * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the - * former is used to map physical pins to their physical internal device module - * counterparts, for simplicity the design of this driver uses the logical GPIO - * numbers instead. - * - * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection - * - * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how - * this module is interconnected within the device. - * - * \anchor asfdoc_sam0_port_module_int_connections - * \dot - * digraph overview { - * node [label="Port Pad" shape=square] pad; - * - * subgraph driver { - * node [label="Peripheral MUX" shape=trapezium] pinmux; - * node [label="GPIO Module" shape=ellipse] gpio; - * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals; - * } - * - * pinmux -> gpio; - * pad -> pinmux; - * pinmux -> peripherals; - * } - * \enddot - * - * - * \section asfdoc_sam0_port_special_considerations Special Considerations - * - * The SAM port pin input sampler can be disabled when the pin is configured - * in pure output mode to save power; reading the pin state of a pin configured - * in output-only mode will read the logical output state that was last set. - * - * \section asfdoc_sam0_port_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_port_extra. This includes: - * - \ref asfdoc_sam0_port_extra_acronyms - * - \ref asfdoc_sam0_port_extra_dependencies - * - \ref asfdoc_sam0_port_extra_errata - * - \ref asfdoc_sam0_port_extra_history - * - * - * \section asfdoc_sam0_port_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_port_exqsg. - * - * - * \section asfdoc_sam0_port_api_overview API Overview - * @{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name Driver Feature Definition - * Define port features set according to different device family. - * @{ -*/ -#if (SAML21) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** Event input control feature support for PORT group. */ -# define FEATURE_PORT_INPUT_EVENT -#endif -/*@}*/ - -/** \name PORT Alias Macros - * @{ - */ - -/** Convenience definition for GPIO module group A on the device (if - * available). */ -#if (PORT_GROUPS > 0) || defined(__DOXYGEN__) -# define PORTA PORT->Group[0] -#endif - -#if (PORT_GROUPS > 1) || defined(__DOXYGEN__) -/** Convenience definition for GPIO module group B on the device (if - * available). */ -# define PORTB PORT->Group[1] -#endif - -#if (PORT_GROUPS > 2) || defined(__DOXYGEN__) -/** Convenience definition for GPIO module group C on the device (if - * available). */ -# define PORTC PORT->Group[2] -#endif - -#if (PORT_GROUPS > 3) || defined(__DOXYGEN__) -/** Convenience definition for GPIO module group D on the device (if - * available). */ -# define PORTD PORT->Group[3] -#endif - -/** @} */ - -/** - * \brief Port pin direction configuration enum. - * - * Enum for the possible pin direction settings of the port pin configuration - * structure, to indicate the direction the pin should use. - */ -enum port_pin_dir { - /** The pin's input buffer should be enabled, so that the pin state can - * be read. */ - PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT, - /** The pin's output buffer should be enabled, so that the pin state can - * be set. */ - PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT, - /** The pin's output and input buffers should be enabled, so that the pin - * state can be set and read back. */ - PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, -}; - -/** - * \brief Port pin input pull configuration enum. - * - * Enum for the possible pin pull settings of the port pin configuration - * structure, to indicate the type of logic level pull the pin should use. - */ -enum port_pin_pull { - /** No logical pull should be applied to the pin. */ - PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, - /** Pin should be pulled up when idle. */ - PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, - /** Pin should be pulled down when idle. */ - PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, -}; - -#ifdef FEATURE_PORT_INPUT_EVENT -/** - * \brief Port input event action. - * - * List of port input events action on pin. - */ -enum port_input_event_action { - /** Event out to pin. */ - PORT_INPUT_EVENT_ACTION_OUT = 0, - /** Set output register of pin on event. */ - PORT_INPUT_EVENT_ACTION_SET, - /** Clear output register pin on event. */ - PORT_INPUT_EVENT_ACTION_CLR, - /** Toggle output register pin on event. */ - PORT_INPUT_EVENT_ACTION_TGL, -}; - -/** - * \brief Port input event. - * - * List of port input events. - */ -enum port_input_event { - /** Port input event 0. */ - PORT_INPUT_EVENT_0 = 0, - /** Port input event 1. */ - PORT_INPUT_EVENT_1 = 1, - /** Port input event 2. */ - PORT_INPUT_EVENT_2 = 2, - /** Port input event 3. */ - PORT_INPUT_EVENT_3 = 3, -}; - -/** - * \brief Port input event configuration structure. - * - * Configuration structure for a port input event. - */ -struct port_input_event_config { - /** Port input event action. */ - enum port_input_event_action action; - /** GPIO pin. */ - uint8_t gpio_pin; -}; -#endif - -/** - * \brief Port pin configuration structure. - * - * Configuration structure for a port pin instance. This structure should be - * initialized by the \ref port_get_config_defaults() function before being - * modified by the user application. - */ -struct port_config { - /** Port buffer input/output direction. */ - enum port_pin_dir direction; - - /** Port pull-up/pull-down for input pins. */ - enum port_pin_pull input_pull; - - /** Enable lowest possible powerstate on the pin. - * - * \note All other configurations will be ignored, the pin will be disabled. - */ - bool powersave; -}; - -/** \name State Reading/Writing (Physical Group Orientated) - * @{ - */ - -/** - * \brief Retrieves the PORT module group instance from a given GPIO pin number. - * - * Retrieves the PORT module group instance associated with a given logical - * GPIO pin number. - * - * \param[in] gpio_pin Index of the GPIO pin to convert - * - * \return Base address of the associated PORT module. - */ -static inline PortGroup* port_get_group_from_gpio_pin( - const uint8_t gpio_pin) -{ - return system_pinmux_get_group_from_gpio_pin(gpio_pin); -} - -/** - * \brief Retrieves the state of a group of port pins that are configured as inputs. - * - * Reads the current logic level of a port module's pins and returns the - * current levels as a bitmask. - * - * \param[in] port Base of the PORT module to read from - * \param[in] mask Mask of the port pin(s) to read - * - * \return Status of the port pin(s) input buffers. - */ -static inline uint32_t port_group_get_input_level( - const PortGroup *const port, - const uint32_t mask) -{ - /* Sanity check arguments */ - Assert(port); - - return (port->IN.reg & mask); -} - -/** - * \brief Retrieves the state of a group of port pins that are configured as outputs. - * - * Reads the current logical output level of a port module's pins and returns - * the current levels as a bitmask. - * - * \param[in] port Base of the PORT module to read from - * \param[in] mask Mask of the port pin(s) to read - * - * \return Status of the port pin(s) output buffers. - */ -static inline uint32_t port_group_get_output_level( - const PortGroup *const port, - const uint32_t mask) -{ - /* Sanity check arguments */ - Assert(port); - - return (port->OUT.reg & mask); -} - -/** - * \brief Sets the state of a group of port pins that are configured as outputs. - * - * Sets the current output level of a port module's pins to a given logic - * level. - * - * \param[out] port Base of the PORT module to write to - * \param[in] mask Mask of the port pin(s) to change - * \param[in] level_mask Mask of the port level(s) to set - */ -static inline void port_group_set_output_level( - PortGroup *const port, - const uint32_t mask, - const uint32_t level_mask) -{ - /* Sanity check arguments */ - Assert(port); - - port->OUTSET.reg = (mask & level_mask); - port->OUTCLR.reg = (mask & ~level_mask); -} - -/** - * \brief Toggles the state of a group of port pins that are configured as an outputs. - * - * Toggles the current output levels of a port module's pins. - * - * \param[out] port Base of the PORT module to write to - * \param[in] mask Mask of the port pin(s) to toggle - */ -static inline void port_group_toggle_output_level( - PortGroup *const port, - const uint32_t mask) -{ - /* Sanity check arguments */ - Assert(port); - - port->OUTTGL.reg = mask; -} - -/** @} */ - -/** \name Configuration and Initialization - * @{ - */ - -/** - * \brief Initializes a Port pin/group configuration structure to defaults. - * - * Initializes a given Port pin/group configuration structure to a set of - * known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Input mode with internal pullup enabled - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void port_get_config_defaults( - struct port_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->direction = PORT_PIN_DIR_INPUT; - config->input_pull = PORT_PIN_PULL_UP; - config->powersave = false; -} - -void port_pin_set_config( - const uint8_t gpio_pin, - const struct port_config *const config); - -void port_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct port_config *const config); - -/** @} */ - -/** \name State Reading/Writing (Logical Pin Orientated) - * @{ - */ - -/** - * \brief Retrieves the state of a port pin that is configured as an input. - * - * Reads the current logic level of a port pin and returns the current - * level as a Boolean value. - * - * \param[in] gpio_pin Index of the GPIO pin to read - * - * \return Status of the port pin's input buffer. - */ -static inline bool port_pin_get_input_level( - const uint8_t gpio_pin) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - return (port_base->IN.reg & pin_mask); -} - -/** - * \brief Retrieves the state of a port pin that is configured as an output. - * - * Reads the current logical output level of a port pin and returns the current - * level as a Boolean value. - * - * \param[in] gpio_pin Index of the GPIO pin to read - * - * \return Status of the port pin's output buffer. - */ -static inline bool port_pin_get_output_level( - const uint8_t gpio_pin) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - return (port_base->OUT.reg & pin_mask); -} - -/** - * \brief Sets the state of a port pin that is configured as an output. - * - * Sets the current output level of a port pin to a given logic level. - * - * \param[in] gpio_pin Index of the GPIO pin to write to - * \param[in] level Logical level to set the given pin to - */ -static inline void port_pin_set_output_level( - const uint8_t gpio_pin, - const bool level) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - /* Set the pin to high or low atomically based on the requested level */ - if (level) { - port_base->OUTSET.reg = pin_mask; - } else { - port_base->OUTCLR.reg = pin_mask; - } -} - -/** - * \brief Toggles the state of a port pin that is configured as an output. - * - * Toggles the current output level of a port pin. - * - * \param[in] gpio_pin Index of the GPIO pin to toggle - */ -static inline void port_pin_toggle_output_level( - const uint8_t gpio_pin) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - /* Toggle pin output level */ - port_base->OUTTGL.reg = pin_mask; -} - -/** @} */ - -#ifdef FEATURE_PORT_INPUT_EVENT - -/** \name Port Input Event - * @{ - */ - -/** - * \brief Enable the port event input. - * - * Enable the port event input with the given pin and event. - * - * \param[in] gpio_pin Index of the GPIO pin - * \param[in] n Port input event - * - * \retval STATUS_ERR_INVALID_ARG Invalid parameter - * \retval STATUS_OK Successfully - */ -static inline enum status_code port_enable_input_event( - const uint8_t gpio_pin, - const enum port_input_event n) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** - * \brief Disable the port event input. - * - * Disable the port event input with the given pin and event. - * - * \param[in] gpio_pin Index of the GPIO pin - * \param[in] gpio_pin Port input event - * - * \retval STATUS_ERR_INVALID_ARG Invalid parameter - * \retval STATUS_OK Successfully - */ -static inline enum status_code port_disable_input_event( - const uint8_t gpio_pin, - const enum port_input_event n) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** - * \brief Retrieve the default configuration for port input event. - * - * Fills a configuration structure with the default configuration for port input event: - * - Event output to pin - * - Event action to be executed on PIN 0 - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void port_input_event_get_config_defaults( - struct port_input_event_config *const config) -{ - Assert(config); - config->action = PORT_INPUT_EVENT_ACTION_OUT; - config->gpio_pin = 0; -} - -/** - * \brief Configure port input event. - * - * Configures port input event with the given configuration settings. - * - * \param[in] config Port input even configuration structure containing the new config - * - * \retval STATUS_ERR_INVALID_ARG Invalid parameter - * \retval STATUS_OK Successfully - */ - -static inline enum status_code port_input_event_set_config( - const enum port_input_event n, - struct port_input_event_config *const config) -{ - Assert(config); - PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin); - uint8_t pin_index = config->gpio_pin % 32; - struct port_config pin_conf; - - port_get_config_defaults(&pin_conf); - /* Configure the GPIO pin as outputs*/ - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - port_pin_set_config(config->gpio_pin, &pin_conf); - - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) - | PORT_EVCTRL_PID0(pin_index); - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action) - | PORT_EVCTRL_PID1(pin_index); - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action) - | PORT_EVCTRL_PID2(pin_index); - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action) - | PORT_EVCTRL_PID3(pin_index); - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** @} */ - -#endif - -#ifdef __cplusplus -} -#endif - -/** @} */ - -/** - * \page asfdoc_sam0_port_extra Extra Information for PORT Driver - * - * \section asfdoc_sam0_port_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
GPIOGeneral Purpose Input/Output
MUXMultiplexer
- * - * - * \section asfdoc_sam0_port_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_port_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_port_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Added input event feature
Initial Release
- */ - -/** - * \page asfdoc_sam0_port_exqsg Examples for PORT Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_port_basic_use_case - * - * \page asfdoc_sam0_port_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
E06/2015Added input event feature and support for SAML21, SAMC21, and SAMDAx.
D12/2014Added support for SAMR21 and SAMD10/D11.
C01/2014Added support for SAMD21.
B06/2013Corrected documentation typos.
A06/2013Initial release
- */ - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMD21/rtc_count.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMD21/rtc_count.c deleted file mode 100644 index e5fcc0daf83..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMD21/rtc_count.c +++ /dev/null @@ -1,773 +0,0 @@ -/** - * \file - * - * \brief SAM RTC Driver (Count Mode) - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "rtc_count.h" -#include - -#if !defined(__DOXYGEN__) -struct rtc_module *_rtc_instance[RTC_INST_NUM]; -#endif - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module RTC hardware module - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true if the module synchronization is ongoing - * \retval false if the module has completed synchronization - */ -static bool rtc_count_is_syncing(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - if (rtc_module->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) { - return true; - } - - return false; -} - -/** - * \brief Enables the RTC module. - * - * Enables the RTC module once it has been configured, ready for use. Most - * module configuration parameters cannot be altered while the module is enabled. - * - * \param[in,out] module RTC hardware module - */ -void rtc_count_enable(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - -#if RTC_COUNT_ASYNC == true - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC); -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Enable RTC module. */ - rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE; -} - -/** - * \brief Disables the RTC module. - * - * Disables the RTC module. - * - * \param[in,out] module RTC hardware module - */ -void rtc_count_disable(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - -#if RTC_COUNT_ASYNC == true - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC); -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Disable RTC module. */ - rtc_module->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE; -} - -/** - * \brief Resets the RTC module. - * Resets the RTC to hardware defaults. - * - * \param[in,out] module Pointer to the software instance struct - */ -void rtc_count_reset(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Disable module before reset. */ - rtc_count_disable(module); - -#if RTC_COUNT_ASYNC == true - module->registered_callback = 0; - module->enabled_callback = 0; -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Initiate software reset. */ - rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST; -} - -/** - * \internal Applies the given configuration. - * - * Sets the configurations given from the configuration structure to the - * hardware module. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] config Pointer to the configuration structure. - * - * \return Status of the configuration procedure. - * \retval STATUS_OK RTC configurations was set successfully. - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given. - */ -static enum status_code _rtc_count_set_config( - struct rtc_module *const module, - const struct rtc_count_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - rtc_module->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | config->prescaler; - - /* Set mode and clear on match if applicable. */ - switch (config->mode) { - case RTC_COUNT_MODE_32BIT: - /* Set 32bit mode and clear on match if applicable. */ - rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(0); - - /* Check if clear on compare match should be set. */ - if (config->clear_on_match) { - /* Set clear on match. */ - rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR; - } - /* Set compare values. */ - for (uint8_t i = 0; i < RTC_NUM_OF_COMP32; i++) { - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - rtc_count_set_compare(module, config->compare_values[i], - (enum rtc_count_compare)i); - } - break; - - case RTC_COUNT_MODE_16BIT: - /* Set 16bit mode. */ - rtc_module->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(1); - - /* Check if match on clear is set, and return invalid - * argument if set. */ - if (config->clear_on_match) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - /* Set compare values. */ - for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) { - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - rtc_count_set_compare(module, config->compare_values[i], - (enum rtc_count_compare)i); - } - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - /* Check to set continuously clock read update mode. */ - if (config->continuously_update) { - /* Set continuously mode. */ - rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT; - } - - /* Return status OK if everything was configured. */ - return STATUS_OK; -} - -/** - * \brief Initializes the RTC module with given configurations. - * - * Initializes the module, setting up all given configurations to provide - * the desired functionality of the RTC. - * - * \param[out] module Pointer to the software instance struct - * \param[in] hw Pointer to hardware instance - * \param[in] config Pointer to the configuration structure - * - * \return Status of the initialization procedure. - * \retval STATUS_OK If the initialization was run stressfully - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given - */ -enum status_code rtc_count_init( - struct rtc_module *const module, - Rtc *const hw, - const struct rtc_count_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize device instance */ - module->hw = hw; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC); - - /* Set up GCLK */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = GCLK_GENERATOR_2; - system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(RTC_GCLK_ID); - - /* Reset module to hardware defaults. */ - rtc_count_reset(module); - - /* Save conf_struct internally for continued use. */ - module->mode = config->mode; - module->continuously_update = config->continuously_update; - -# if (RTC_INST_NUM == 1) - _rtc_instance[0] = module; -# else - /* Register this instance for callbacks*/ - _rtc_instance[_rtc_get_inst_index(hw)] = module; -# endif - - /* Set config and return status. */ - return _rtc_count_set_config(module, config); -} - -/** - * \brief Set the current count value to desired value. - * - * Sets the value of the counter to the specified value. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] count_value The value to be set in count register - * - * \return Status of setting the register. - * \retval STATUS_OK If everything was executed correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - */ -enum status_code rtc_count_set_count( - struct rtc_module *const module, - const uint32_t count_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set count according to mode */ - switch(module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Write value to register. */ - rtc_module->MODE0.COUNT.reg = count_value; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check if 16-bit value is provided. */ - if(count_value > 0xffff) { - return STATUS_ERR_INVALID_ARG; - } - - /* Write value to register. */ - rtc_module->MODE1.COUNT.reg = (uint32_t)count_value; - - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** - * \brief Get the current count value. - * - * \param[in,out] module Pointer to the software instance struct - * - * Returns the current count value. - * - * \return The current counter value as a 32-bit unsigned integer. - */ -uint32_t rtc_count_get_count(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Initialize return value. */ - uint32_t ret_val; - - /* Change of read method based on value of continuously_update value in - * the configuration structure. */ - if(!(module->continuously_update)) { - /* Request read on count register. */ - rtc_module->MODE0.READREQ.reg = RTC_READREQ_RREQ; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - } - - /* Read value based on mode. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Return count value in 32-bit mode. */ - ret_val = rtc_module->MODE0.COUNT.reg; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Return count value in 16-bit mode. */ - ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg; - - break; - - default: - Assert(false); - /* Counter not initialized. Assume counter value 0.*/ - ret_val = 0; - break; - } - - return ret_val; -} - -/** - * \brief Set the compare value for the specified compare. - * - * Sets the value specified by the implementer to the requested compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_value The value to be written to the compare - * \param[in] comp_index Index of the compare to set - * - * \return Status indicating if compare was successfully set. - * \retval STATUS_OK If compare was successfully set - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_set_compare( - struct rtc_module *const module, - const uint32_t comp_value, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set compare values based on operation mode. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) { - return STATUS_ERR_INVALID_ARG; - } - - /* Set compare value for COMP. */ - rtc_module->MODE0.COMP[comp_index].reg = comp_value; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that 16-bit value is provided. */ - if (comp_value > 0xffff) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - /* Set compare value for COMP. */ - rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff; - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - - /* Return status if everything is OK. */ - return STATUS_OK; -} - -/** - * \brief Get the current compare value of specified compare. - * - * Retrieves the current value of the specified compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[out] comp_value Pointer to 32-bit integer that will be populated with - * the current compare value - * \param[in] comp_index Index of compare to check - * - * \return Status of the reading procedure. - * \retval STATUS_OK If the value was read correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_get_compare( - struct rtc_module *const module, - uint32_t *const comp_value, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) { - return STATUS_ERR_INVALID_ARG; - } - - /* Get compare value for COMP. */ - *comp_value = rtc_module->MODE0.COMP[comp_index].reg; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - /* Get compare value for COMP. */ - *comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg; - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - /* Return status showing everything is OK. */ - return STATUS_OK; -} - -/** - * \brief Retrieves the value of period. - * - * Retrieves the value of the period for the 16-bit mode counter. - * - * \note Only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[out] period_value Pointer to value for return argument - * - * \return Status of getting the period value. - * \retval STATUS_OK If the period value was read correctly - * \retval STATUS_ERR_UNSUPPORTED_DEV If incorrect mode was set - */ -enum status_code rtc_count_get_period( - struct rtc_module *const module, - uint16_t *const period_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check that correct mode is set. */ - if (module->mode != RTC_COUNT_MODE_16BIT) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Returns the value. */ - *period_value = rtc_module->MODE1.PER.reg; - - return STATUS_OK; -} - -/** - * \brief Set the given value to the period. - * - * Sets the given value to the period. - * - * \note Only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] period_value The value to set to the period - * - * \return Status of setting the period value. - * \retval STATUS_OK If the period was set correctly - * \retval STATUS_ERR_UNSUPPORTED_DEV If module is not operated in 16-bit mode - */ -enum status_code rtc_count_set_period( - struct rtc_module *const module, - const uint16_t period_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check that correct mode is set. */ - if (module->mode != RTC_COUNT_MODE_16BIT) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Write value to register. */ - rtc_module->MODE1.PER.reg = period_value; - - return STATUS_OK; -} - -/** - * \brief Check if RTC compare match has occurred. - * - * Checks the compare flag to see if a match has occurred. The compare flag is - * set when there is a compare match between counter and the compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_index Index of compare to check current flag - */ -bool rtc_count_is_compare_match( - struct rtc_module *const module, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check sanity. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity for 32-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP32) { - return false; - } - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity for 16-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP16) { - return false; - } - - break; - - default: - Assert(false); - return false; - } - - /* Set status of INTFLAG as return argument. */ - return (rtc_module->MODE0.INTFLAG.reg & (1 << comp_index)) ? true : false; -} - -/** - * \brief Clears RTC compare match flag. - * - * Clears the compare flag. The compare flag is set when there is a compare - * match between the counter and the compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_index Index of compare to check current flag - * - * \return Status indicating if flag was successfully cleared. - * \retval STATUS_OK If flag was successfully cleared - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_clear_compare_match( - struct rtc_module *const module, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check sanity. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity for 32-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP32) { - return STATUS_ERR_INVALID_ARG; - } - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity for 16-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - - /* Clear INTFLAG. */ - rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index); - - return STATUS_OK; -} - -/** - * \brief Calibrate for too-slow or too-fast oscillator. - * - * When used, the RTC will compensate for an inaccurate oscillator. The - * RTC module will add or subtract cycles from the RTC prescaler to adjust the - * frequency in approximately 1 PPM steps. The provided correction value should - * be between 0 and 127, allowing for a maximum 127 PPM correction. - * - * If no correction is needed, set value to zero. - * - * \note Can only be used when the RTC is operated in 1Hz. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] value Ranging from -127 to 127 used for the correction - * - * \return Status of the calibration procedure. - * \retval STATUS_OK If calibration was executed correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - */ -enum status_code rtc_count_frequency_correction( - struct rtc_module *const module, - const int8_t value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check if valid argument. */ - if (abs(value) > 0x7F) { - /* Value bigger than allowed, return invalid argument. */ - return STATUS_ERR_INVALID_ARG; - } - - uint32_t new_correction_value; - - /* Load the new correction value as a positive value, sign added later */ - new_correction_value = abs(value); - - /* Convert to positive value and adjust register sign bit. */ - if (value < 0) { - new_correction_value |= RTC_FREQCORR_SIGN; - } - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set value. */ - rtc_module->MODE0.FREQCORR.reg = new_correction_value; - - return STATUS_OK; -} - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/module_config/conf_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/module_config/conf_rtc.h deleted file mode 100644 index f337c7ec4b0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/module_config/conf_rtc.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief SAM RTC Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_RTC_H_INCLUDED -#define CONF_RTC_H_INCLUDED - -/** Select RTC clock. Use 1.024kHz from 32kHz internal ULP oscillator(OSCULP32K) - * for RTC clock. - */ -# define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/rtc_count.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/rtc_count.c deleted file mode 100644 index e6b10d71b6c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/rtc_count.c +++ /dev/null @@ -1,795 +0,0 @@ -/** - * \file - * - * \brief SAM RTC Driver (Count Mode) - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "rtc_count.h" -#include -#include -#include "conf_rtc.h" - -#if !defined(__DOXYGEN__) -struct rtc_module *_rtc_instance[RTC_INST_NUM]; -#endif - -#if !defined(RTC_CLOCK_SOURCE) -# warning RTC_CLOCK_SOURCE is not defined, assuming RTC_CLOCK_SELECTION_ULP1K. -# define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K -#endif - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module RTC hardware module - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true if the module synchronization is ongoing - * \retval false if the module has completed synchronization - */ -static bool rtc_count_is_syncing(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - if (rtc_module->MODE0.SYNCBUSY.reg) { - return true; - } - - return false; -} - -/** - * \brief Enables the RTC module. - * - * Enables the RTC module once it has been configured, ready for use. Most - * module configuration parameters cannot be altered while the module is enabled. - * - * \param[in,out] module RTC hardware module - */ -void rtc_count_enable(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - -#if RTC_COUNT_ASYNC == true - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC); -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Enable RTC module. */ - rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } -} - -/** - * \brief Disables the RTC module. - * - * Disables the RTC module. - * - * \param[in,out] module RTC hardware module - */ -void rtc_count_disable(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - -#if RTC_COUNT_ASYNC == true - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC); -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Disable RTC module. */ - rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } -} - -/** - * \brief Resets the RTC module. - * Resets the RTC to hardware defaults. - * - * \param[in,out] module Pointer to the software instance struct - */ -void rtc_count_reset(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Disable module before reset. */ - rtc_count_disable(module); - -#if RTC_COUNT_ASYNC == true - module->registered_callback = 0; - module->enabled_callback = 0; -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Initiate software reset. */ - rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } -} - -/** - * \internal Applies the given configuration. - * - * Sets the configurations given from the configuration structure to the - * hardware module - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] config Pointer to the configuration structure - * - * \return Status of the configuration procedure. - * \retval STATUS_OK RTC configurations was set successfully - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given - */ -static enum status_code _rtc_count_set_config( - struct rtc_module *const module, - const struct rtc_count_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - -#if SAML21 - rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | config->prescaler - | (config->enable_read_sync << RTC_MODE0_CTRLA_SYNCDIS_Pos); -#endif -#if (SAMC20) || (SAMC21) - rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | config->prescaler - | (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos); -#endif - - /* Set mode and clear on match if applicable. */ - switch (config->mode) { - case RTC_COUNT_MODE_32BIT: - /* Set 32-bit mode and clear on match if applicable. */ - rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(0); - - /* Check if clear on compare match should be set. */ - if (config->clear_on_match) { - /* Set clear on match. */ - rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; - } - /* Set compare values. */ - for (uint8_t i = 0; i < RTC_COMP32_NUM; i++) { - rtc_count_set_compare(module, config->compare_values[i], - (enum rtc_count_compare)i); - } - break; - - case RTC_COUNT_MODE_16BIT: - /* Set 16bit mode. */ - rtc_module->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(1); - - /* Check if match on clear is set, and return invalid - * argument if set. */ - if (config->clear_on_match) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - /* Set compare values. */ - for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) { - rtc_count_set_compare(module, config->compare_values[i], - (enum rtc_count_compare)i); - } - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - /* Return status OK if everything was configured. */ - return STATUS_OK; -} - -/** - * \brief Initializes the RTC module with given configurations. - * - * Initializes the module, setting up all given configurations to provide - * the desired functionality of the RTC. - * - * \param[out] module Pointer to the software instance struct - * \param[in] hw Pointer to hardware instance - * \param[in] config Pointer to the configuration structure - * - * \return Status of the initialization procedure. - * \retval STATUS_OK If the initialization was run stressfully - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given - */ -enum status_code rtc_count_init( - struct rtc_module *const module, - Rtc *const hw, - const struct rtc_count_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize device instance */ - module->hw = hw; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC); - - /* Select RTC clock */ - OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE; - - /* Reset module to hardware defaults. */ - rtc_count_reset(module); - - /* Save conf_struct internally for continued use. */ - module->mode = config->mode; - -# if (RTC_INST_NUM == 1) - _rtc_instance[0] = module; -# else - /* Register this instance for callbacks*/ - _rtc_instance[_rtc_get_inst_index(hw)] = module; -# endif - - /* Set config and return status. */ - return _rtc_count_set_config(module, config); -} - -/** - * \brief Set the current count value to desired value. - * - * Sets the value of the counter to the specified value. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] count_value The value to be set in count register - * - * \return Status of setting the register. - * \retval STATUS_OK If everything was executed correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - */ -enum status_code rtc_count_set_count( - struct rtc_module *const module, - const uint32_t count_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set count according to mode */ - switch(module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Write value to register. */ - rtc_module->MODE0.COUNT.reg = count_value; - break; - case RTC_COUNT_MODE_16BIT: - /* Check if 16-bit value is provided. */ - if(count_value > 0xffff) { - return STATUS_ERR_INVALID_ARG; - } - - /* Write value to register. */ - rtc_module->MODE1.COUNT.reg = (uint32_t)count_value; - - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - return STATUS_OK; -} - -/** - * \brief Get the current count value. - * - * \param[in,out] module Pointer to the software instance struct - * - * Returns the current count value. - * - * \return The current counter value as a 32-bit unsigned integer. - */ -uint32_t rtc_count_get_count(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Initialize return value. */ - uint32_t ret_val; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Read value based on mode. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Return count value in 32-bit mode. */ - ret_val = rtc_module->MODE0.COUNT.reg; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Return count value in 16-bit mode. */ - ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg; - - break; - - default: - Assert(false); - /* Counter not initialized. Assume counter value 0.*/ - ret_val = 0; - break; - } - - return ret_val; -} - -/** - * \brief Set the compare value for the specified compare. - * - * Sets the value specified by the implementer to the requested compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_value The value to be written to the compare - * \param[in] comp_index Index of the compare to set - * - * \return Status indicating if compare was successfully set. - * \retval STATUS_OK If compare was successfully set - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_set_compare( - struct rtc_module *const module, - const uint32_t comp_value, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set compare values based on operation mode. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_COMP32_NUM) { - return STATUS_ERR_INVALID_ARG; - } - - /* Set compare value for COMP. */ - rtc_module->MODE0.COMP[comp_index].reg = comp_value; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that 16-bit value is provided. */ - if (comp_value > 0xffff) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - /* Set compare value for COMP. */ - rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff; - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Return status if everything is OK. */ - return STATUS_OK; -} - -/** - * \brief Get the current compare value of specified compare. - * - * Retrieves the current value of the specified compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[out] comp_value Pointer to 32-bit integer that will be populated with - * the current compare value - * \param[in] comp_index Index of compare to check - * - * \return Status of the reading procedure. - * \retval STATUS_OK If the value was read correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_get_compare( - struct rtc_module *const module, - uint32_t *const comp_value, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_COMP32_NUM) { - return STATUS_ERR_INVALID_ARG; - } - - /* Get compare value for COMP. */ - *comp_value = rtc_module->MODE0.COMP[comp_index].reg; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - /* Get compare value for COMP. */ - *comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg; - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - /* Return status showing everything is OK. */ - return STATUS_OK; -} - -/** - * \brief Retrieves the value of period. - * - * Retrieves the value of the period for the 16-bit mode counter. - * - * \note Only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[out] period_value Pointer to value for return argument - * - * \return Status of getting the period value. - * \retval STATUS_OK If the period value was read correctly - * \retval STATUS_ERR_UNSUPPORTED_DEV If incorrect mode was set - */ -enum status_code rtc_count_get_period( - struct rtc_module *const module, - uint16_t *const period_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Check that correct mode is set. */ - if (module->mode != RTC_COUNT_MODE_16BIT) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Returns the value. */ - *period_value = rtc_module->MODE1.PER.reg; - - return STATUS_OK; -} - -/** - * \brief Set the given value to the period. - * - * Sets the given value to the period. - * - * \note Only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] period_value The value to set to the period - * - * \return Status of setting the period value. - * \retval STATUS_OK If the period was set correctly - * \retval STATUS_ERR_UNSUPPORTED_DEV If module is not operated in 16-bit mode - */ -enum status_code rtc_count_set_period( - struct rtc_module *const module, - const uint16_t period_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check that correct mode is set. */ - if (module->mode != RTC_COUNT_MODE_16BIT) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Write value to register. */ - rtc_module->MODE1.PER.reg = period_value; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - return STATUS_OK; -} - -/** - * \brief Check if RTC compare match has occurred. - * - * Checks the compare flag to see if a match has occurred. The compare flag is - * set when there is a compare match between counter and the compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_index Index of compare to check current flag - */ -bool rtc_count_is_compare_match( - struct rtc_module *const module, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check sanity. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity for 32-bit mode. */ - if (comp_index > RTC_COMP32_NUM) { - return false; - } - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity for 16-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP16) { - return false; - } - - break; - - default: - Assert(false); - return false; - } - - /* Set status of INTFLAG as return argument. */ - return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP(1 << comp_index)) ? true : false; -} - -/** - * \brief Clears RTC compare match flag. - * - * Clears the compare flag. The compare flag is set when there is a compare - * match between the counter and the compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_index Index of compare to check current flag - * - * \return Status indicating if flag was successfully cleared. - * \retval STATUS_OK If flag was successfully cleared - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_clear_compare_match( - struct rtc_module *const module, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check sanity. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity for 32-bit mode. */ - if (comp_index > RTC_COMP32_NUM) { - return STATUS_ERR_INVALID_ARG; - } - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity for 16-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - - /* Clear INTFLAG. */ - rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index); - - return STATUS_OK; -} - -/** - * \brief Calibrate for too-slow or too-fast oscillator. - * - * When used, the RTC will compensate for an inaccurate oscillator. The - * RTC module will add or subtract cycles from the RTC prescaler to adjust the - * frequency in approximately 1 PPM steps. The provided correction value should - * be between 0 and 127, allowing for a maximum 127 PPM correction. - * - * If no correction is needed, set value to zero. - * - * \note Can only be used when the RTC is operated in 1Hz. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] value Ranging from -127 to 127 used for the correction - * - * \return Status of the calibration procedure. - * \retval STATUS_OK If calibration was executed correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - */ -enum status_code rtc_count_frequency_correction( - struct rtc_module *const module, - const int8_t value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check if valid argument. */ - if (abs(value) > 0x7F) { - /* Value bigger than allowed, return invalid argument. */ - return STATUS_ERR_INVALID_ARG; - } - - uint32_t new_correction_value; - - /* Load the new correction value as a positive value, sign added later */ - new_correction_value = abs(value); - - /* Convert to positive value and adjust register sign bit. */ - if (value < 0) { - new_correction_value |= RTC_FREQCORR_SIGN; - } - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set value. */ - rtc_module->MODE0.FREQCORR.reg = new_correction_value; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - return STATUS_OK; -} - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMR21/rtc_count.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMR21/rtc_count.c deleted file mode 100644 index e5fcc0daf83..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMR21/rtc_count.c +++ /dev/null @@ -1,773 +0,0 @@ -/** - * \file - * - * \brief SAM RTC Driver (Count Mode) - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "rtc_count.h" -#include - -#if !defined(__DOXYGEN__) -struct rtc_module *_rtc_instance[RTC_INST_NUM]; -#endif - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module RTC hardware module - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true if the module synchronization is ongoing - * \retval false if the module has completed synchronization - */ -static bool rtc_count_is_syncing(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - if (rtc_module->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) { - return true; - } - - return false; -} - -/** - * \brief Enables the RTC module. - * - * Enables the RTC module once it has been configured, ready for use. Most - * module configuration parameters cannot be altered while the module is enabled. - * - * \param[in,out] module RTC hardware module - */ -void rtc_count_enable(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - -#if RTC_COUNT_ASYNC == true - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC); -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Enable RTC module. */ - rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE; -} - -/** - * \brief Disables the RTC module. - * - * Disables the RTC module. - * - * \param[in,out] module RTC hardware module - */ -void rtc_count_disable(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - -#if RTC_COUNT_ASYNC == true - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC); -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Disable RTC module. */ - rtc_module->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE; -} - -/** - * \brief Resets the RTC module. - * Resets the RTC to hardware defaults. - * - * \param[in,out] module Pointer to the software instance struct - */ -void rtc_count_reset(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Disable module before reset. */ - rtc_count_disable(module); - -#if RTC_COUNT_ASYNC == true - module->registered_callback = 0; - module->enabled_callback = 0; -#endif - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Initiate software reset. */ - rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST; -} - -/** - * \internal Applies the given configuration. - * - * Sets the configurations given from the configuration structure to the - * hardware module. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] config Pointer to the configuration structure. - * - * \return Status of the configuration procedure. - * \retval STATUS_OK RTC configurations was set successfully. - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given. - */ -static enum status_code _rtc_count_set_config( - struct rtc_module *const module, - const struct rtc_count_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - rtc_module->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | config->prescaler; - - /* Set mode and clear on match if applicable. */ - switch (config->mode) { - case RTC_COUNT_MODE_32BIT: - /* Set 32bit mode and clear on match if applicable. */ - rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(0); - - /* Check if clear on compare match should be set. */ - if (config->clear_on_match) { - /* Set clear on match. */ - rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR; - } - /* Set compare values. */ - for (uint8_t i = 0; i < RTC_NUM_OF_COMP32; i++) { - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - rtc_count_set_compare(module, config->compare_values[i], - (enum rtc_count_compare)i); - } - break; - - case RTC_COUNT_MODE_16BIT: - /* Set 16bit mode. */ - rtc_module->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(1); - - /* Check if match on clear is set, and return invalid - * argument if set. */ - if (config->clear_on_match) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - /* Set compare values. */ - for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) { - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - rtc_count_set_compare(module, config->compare_values[i], - (enum rtc_count_compare)i); - } - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - /* Check to set continuously clock read update mode. */ - if (config->continuously_update) { - /* Set continuously mode. */ - rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT; - } - - /* Return status OK if everything was configured. */ - return STATUS_OK; -} - -/** - * \brief Initializes the RTC module with given configurations. - * - * Initializes the module, setting up all given configurations to provide - * the desired functionality of the RTC. - * - * \param[out] module Pointer to the software instance struct - * \param[in] hw Pointer to hardware instance - * \param[in] config Pointer to the configuration structure - * - * \return Status of the initialization procedure. - * \retval STATUS_OK If the initialization was run stressfully - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given - */ -enum status_code rtc_count_init( - struct rtc_module *const module, - Rtc *const hw, - const struct rtc_count_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize device instance */ - module->hw = hw; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC); - - /* Set up GCLK */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = GCLK_GENERATOR_2; - system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(RTC_GCLK_ID); - - /* Reset module to hardware defaults. */ - rtc_count_reset(module); - - /* Save conf_struct internally for continued use. */ - module->mode = config->mode; - module->continuously_update = config->continuously_update; - -# if (RTC_INST_NUM == 1) - _rtc_instance[0] = module; -# else - /* Register this instance for callbacks*/ - _rtc_instance[_rtc_get_inst_index(hw)] = module; -# endif - - /* Set config and return status. */ - return _rtc_count_set_config(module, config); -} - -/** - * \brief Set the current count value to desired value. - * - * Sets the value of the counter to the specified value. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] count_value The value to be set in count register - * - * \return Status of setting the register. - * \retval STATUS_OK If everything was executed correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - */ -enum status_code rtc_count_set_count( - struct rtc_module *const module, - const uint32_t count_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set count according to mode */ - switch(module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Write value to register. */ - rtc_module->MODE0.COUNT.reg = count_value; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check if 16-bit value is provided. */ - if(count_value > 0xffff) { - return STATUS_ERR_INVALID_ARG; - } - - /* Write value to register. */ - rtc_module->MODE1.COUNT.reg = (uint32_t)count_value; - - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** - * \brief Get the current count value. - * - * \param[in,out] module Pointer to the software instance struct - * - * Returns the current count value. - * - * \return The current counter value as a 32-bit unsigned integer. - */ -uint32_t rtc_count_get_count(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Initialize return value. */ - uint32_t ret_val; - - /* Change of read method based on value of continuously_update value in - * the configuration structure. */ - if(!(module->continuously_update)) { - /* Request read on count register. */ - rtc_module->MODE0.READREQ.reg = RTC_READREQ_RREQ; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - } - - /* Read value based on mode. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Return count value in 32-bit mode. */ - ret_val = rtc_module->MODE0.COUNT.reg; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Return count value in 16-bit mode. */ - ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg; - - break; - - default: - Assert(false); - /* Counter not initialized. Assume counter value 0.*/ - ret_val = 0; - break; - } - - return ret_val; -} - -/** - * \brief Set the compare value for the specified compare. - * - * Sets the value specified by the implementer to the requested compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_value The value to be written to the compare - * \param[in] comp_index Index of the compare to set - * - * \return Status indicating if compare was successfully set. - * \retval STATUS_OK If compare was successfully set - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_set_compare( - struct rtc_module *const module, - const uint32_t comp_value, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set compare values based on operation mode. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) { - return STATUS_ERR_INVALID_ARG; - } - - /* Set compare value for COMP. */ - rtc_module->MODE0.COMP[comp_index].reg = comp_value; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that 16-bit value is provided. */ - if (comp_value > 0xffff) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - /* Set compare value for COMP. */ - rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff; - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - - /* Return status if everything is OK. */ - return STATUS_OK; -} - -/** - * \brief Get the current compare value of specified compare. - * - * Retrieves the current value of the specified compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[out] comp_value Pointer to 32-bit integer that will be populated with - * the current compare value - * \param[in] comp_index Index of compare to check - * - * \return Status of the reading procedure. - * \retval STATUS_OK If the value was read correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_get_compare( - struct rtc_module *const module, - uint32_t *const comp_value, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) { - return STATUS_ERR_INVALID_ARG; - } - - /* Get compare value for COMP. */ - *comp_value = rtc_module->MODE0.COMP[comp_index].reg; - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity of comp_index. */ - if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - /* Get compare value for COMP. */ - *comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg; - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - /* Return status showing everything is OK. */ - return STATUS_OK; -} - -/** - * \brief Retrieves the value of period. - * - * Retrieves the value of the period for the 16-bit mode counter. - * - * \note Only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[out] period_value Pointer to value for return argument - * - * \return Status of getting the period value. - * \retval STATUS_OK If the period value was read correctly - * \retval STATUS_ERR_UNSUPPORTED_DEV If incorrect mode was set - */ -enum status_code rtc_count_get_period( - struct rtc_module *const module, - uint16_t *const period_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check that correct mode is set. */ - if (module->mode != RTC_COUNT_MODE_16BIT) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Returns the value. */ - *period_value = rtc_module->MODE1.PER.reg; - - return STATUS_OK; -} - -/** - * \brief Set the given value to the period. - * - * Sets the given value to the period. - * - * \note Only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] period_value The value to set to the period - * - * \return Status of setting the period value. - * \retval STATUS_OK If the period was set correctly - * \retval STATUS_ERR_UNSUPPORTED_DEV If module is not operated in 16-bit mode - */ -enum status_code rtc_count_set_period( - struct rtc_module *const module, - const uint16_t period_value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check that correct mode is set. */ - if (module->mode != RTC_COUNT_MODE_16BIT) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Write value to register. */ - rtc_module->MODE1.PER.reg = period_value; - - return STATUS_OK; -} - -/** - * \brief Check if RTC compare match has occurred. - * - * Checks the compare flag to see if a match has occurred. The compare flag is - * set when there is a compare match between counter and the compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_index Index of compare to check current flag - */ -bool rtc_count_is_compare_match( - struct rtc_module *const module, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check sanity. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity for 32-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP32) { - return false; - } - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity for 16-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP16) { - return false; - } - - break; - - default: - Assert(false); - return false; - } - - /* Set status of INTFLAG as return argument. */ - return (rtc_module->MODE0.INTFLAG.reg & (1 << comp_index)) ? true : false; -} - -/** - * \brief Clears RTC compare match flag. - * - * Clears the compare flag. The compare flag is set when there is a compare - * match between the counter and the compare. - * - * \note Compare 4 and 5 are only available in 16-bit mode. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] comp_index Index of compare to check current flag - * - * \return Status indicating if flag was successfully cleared. - * \retval STATUS_OK If flag was successfully cleared - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode - */ -enum status_code rtc_count_clear_compare_match( - struct rtc_module *const module, - const enum rtc_count_compare comp_index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check sanity. */ - switch (module->mode) { - case RTC_COUNT_MODE_32BIT: - /* Check sanity for 32-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP32) { - return STATUS_ERR_INVALID_ARG; - } - - break; - - case RTC_COUNT_MODE_16BIT: - /* Check sanity for 16-bit mode. */ - if (comp_index > RTC_NUM_OF_COMP16) { - return STATUS_ERR_INVALID_ARG; - } - - break; - - default: - Assert(false); - return STATUS_ERR_BAD_FORMAT; - } - - /* Clear INTFLAG. */ - rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index); - - return STATUS_OK; -} - -/** - * \brief Calibrate for too-slow or too-fast oscillator. - * - * When used, the RTC will compensate for an inaccurate oscillator. The - * RTC module will add or subtract cycles from the RTC prescaler to adjust the - * frequency in approximately 1 PPM steps. The provided correction value should - * be between 0 and 127, allowing for a maximum 127 PPM correction. - * - * If no correction is needed, set value to zero. - * - * \note Can only be used when the RTC is operated in 1Hz. - * - * \param[in,out] module Pointer to the software instance struct - * \param[in] value Ranging from -127 to 127 used for the correction - * - * \return Status of the calibration procedure. - * \retval STATUS_OK If calibration was executed correctly - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - */ -enum status_code rtc_count_frequency_correction( - struct rtc_module *const module, - const int8_t value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Check if valid argument. */ - if (abs(value) > 0x7F) { - /* Value bigger than allowed, return invalid argument. */ - return STATUS_ERR_INVALID_ARG; - } - - uint32_t new_correction_value; - - /* Load the new correction value as a positive value, sign added later */ - new_correction_value = abs(value); - - /* Convert to positive value and adjust register sign bit. */ - if (value < 0) { - new_correction_value |= RTC_FREQCORR_SIGN; - } - - while (rtc_count_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* Set value. */ - rtc_module->MODE0.FREQCORR.reg = new_correction_value; - - return STATUS_OK; -} - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/rtc_count.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/rtc_count.h deleted file mode 100644 index a6a90daae14..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/rtc_count.h +++ /dev/null @@ -1,1219 +0,0 @@ -/** - * \file - * - * \brief SAM RTC Driver (Count Mode) - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef RTC_COUNT_H_INCLUDED -#define RTC_COUNT_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_rtc_count_group SAM RTC Count Driver (RTC COUNT) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of the device's Real Time Clock functionality in Count - * operating mode, for the configuration and retrieval of the current RTC - * counter value. The following driver API modes are covered by this - * manual: - * - * - Polled APIs - * \if RTC_COUNT_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripherals are used by this module: - * - RTC (Real Time Clock) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_rtc_count_prerequisites - * - \ref asfdoc_sam0_rtc_count_module_overview - * - \ref asfdoc_sam0_rtc_count_special_considerations - * - \ref asfdoc_sam0_rtc_count_extra_info - * - \ref asfdoc_sam0_rtc_count_examples - * - \ref asfdoc_sam0_rtc_count_api_overview - * - * - * \section asfdoc_sam0_rtc_count_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_rtc_count_module_overview Module Overview - * - * The RTC module in the SAM devices is a 32-bit counter, with a 10-bit - * programmable prescaler. Typically, the RTC clock is run continuously, - * including in the device's low-power sleep modes, to track the current time - * and date information. The RTC can be used as a source to wake up the system - * at a scheduled time or periodically using the alarm functions. - * - * In this driver, the RTC is operated in Count mode. This allows for an - * easy integration of an asynchronous counter into a user application, which is - * capable of operating while the device is in sleep mode. - * - * Whilst operating in Count mode, the RTC features: - * - 16-bit counter mode - * - Selectable counter period - * - Up to six configurable compare values - * - 32-bit counter mode - * - Clear counter value on match - * - Up to four configurable compare values - * - * \subsection asfdoc_sam0_rtc_count_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_RTC_PERIODIC_INTSAML21/C20/C21
FEATURE_RTC_PRESCALER_OFFSAML21/C20/C21
FEATURE_RTC_CLOCK_SELECTIONSAML21/C20/C21
FEATURE_RTC_GENERAL_PURPOSE_REGSAML21
FEATURE_RTC_CONTINUOUSLY_UPDATEDSAMD20, SAMD21, SAMR21, SAMD10, SAMD11, SAMDAx
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \section asfdoc_sam0_rtc_count_module_overview_compares Compare and Overflow - * The RTC can be used with up to 4/6 compare values (depending on selected - * operation mode). These compare values will trigger on match with the current - * RTC counter value, and can be set up to trigger an interrupt, event, or both. - * The RTC can also be configured to clear the counter value on compare match - * in 32-bit mode, resetting the count value back to zero. - * - * If the RTC is operated without the Clear on Match option enabled, or in - * 16-bit mode, the RTC counter value will instead be cleared on overflow once - * the maximum count value has been reached: - * - * \f[ COUNT_{MAX} = 2^{32}-1 \f] for 32-bit counter mode, and - * \f[ COUNT_{MAX} = 2^{16}-1 \f] for 16-bit counter mode. - * - * When running in 16-bit mode, the overflow value is selectable with a period - * value. The counter overflow will then occur when the counter value reaches - * the specified period value. - * - * \subsection asfdoc_sam0_rtc_count_module_overview_periodic Periodic Events - * The RTC can generate events at periodic intervals, allowing for direct - * peripheral actions without CPU intervention. The periodic events can be - * generated on the upper eight bits of the RTC prescaler, and will be generated on - * the rising edge transition of the specified bit. The resulting periodic - * frequency can be calculated by the following formula: - * - * \f[ f_{PERIODIC}=\frac{f_{ASY}}{2^{n+3}} \f] - * - * Where \f$f_{ASY}\f$ refers to the \e asynchronous clock set up in the RTC - * module configuration. The \b n parameter is the event source generator index - * of the RTC module. If the asynchronous clock is operated at the recommended - * frequency of 1KHz, the formula results in the values shown in - * \ref asfdoc_sam0_rtc_count_module_rtc_hz "the table below". - * - * \anchor asfdoc_sam0_rtc_count_module_rtc_hz - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
RTC Event Frequencies for Each Prescaler Bit Using a 1KHz Clock
n Periodic event
7 1Hz
6 2Hz
5 4Hz
4 8Hz
3 16Hz
2 32Hz
1 64Hz
0 128Hz
- * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * \subsection asfdoc_sam0_rtc_count_module_overview_correction Digital Frequency Correction - * The RTC module contains Digital Frequency Correction logic to compensate for - * inaccurate source clock frequencies which would otherwise result in skewed - * time measurements. The correction scheme requires that at least two bits - * in the RTC module prescaler are reserved by the correction logic. As a - * result of this implementation, frequency correction is only available when - * the RTC is running from a 1Hz reference clock. - * - * The correction procedure is implemented by subtracting or adding a single - * cycle from the RTC prescaler every 1024 RTC GCLK cycles. The adjustment is - * applied the specified number of time (maximum 127) over 976 of these periods. The - * corresponding correction in PPM will be given by: - * - * \f[ Correction(PPM) = \frac{VALUE}{999424}10^6 \f] - * - * The RTC clock will tick faster if provided with a positive correction value, - * and slower when given a negative correction value. - * - * - * \section asfdoc_sam0_rtc_count_special_considerations Special Considerations - * - * \subsection asfdoc_sam0_rtc_count_special_considerations_clock Clock Setup - * \subsubsection asfdoc_sam0_rtc_count_clock_samd_r SAM D20/D21/R21/D10/D11/DA0/DA1 Clock Setup - * The RTC is typically clocked by a specialized GCLK generator that has a - * smaller prescaler than the others. By default the RTC clock is on, selected - * to use the internal 32KHz RC-oscillator with a prescaler of 32, giving a - * resulting clock frequency of 1KHz to the RTC. When the internal RTC - * prescaler is set to 1024, this yields an end-frequency of 1Hz. - * - * The implementer also has the option to set other end-frequencies. - * \ref asfdoc_sam0_rtc_count_rtc_out_freq "The table below" lists the - * available RTC frequencies for each possible GCLK and RTC input prescaler - * options. - * - * \anchor asfdoc_sam0_rtc_count_rtc_out_freq - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
RTC Output Frequencies from Allowable Input Clocks
End-frequencyGCLK prescalerRTC prescaler
32KHz11
1KHz321
1Hz321024
- * - * The overall RTC module clocking scheme is shown in - * \ref asfdoc_sam0_rtc_count_rtc_clock_fig "the figure below". - * - * \anchor asfdoc_sam0_rtc_count_rtc_clock_fig - * \dot - * digraph clocking_scheme { - * rankdir=LR; - * GCLK [shape="record", label=" GCLK | RTC_GCLK", - * bgcolor="lightgray", style="filled"]; - * RTCPRE [shape="record" label=" RTC | RTC PRESCALER"]; - * RTC [shape="record", label=" RTC | RTC CLOCK"]; - * - * GCLK:f1 -> RTCPRE:f1; - * RTCPRE:f1 -> RTC:f1; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_rtc_count_clock_saml SAM L21/C20/C21 Clock Setup - * The RTC clock can be selected from OSC32K,XOSC32K or OSCULP32K , and a 32KHz - * or 1KHz oscillator clock frequency is required. This clock must be - * configured and enabled in the 32KHz oscillator controller before using the RTC. - * - * The table below lists the available RTC clock \ref asfdoc_sam0_rtc_count_rtc_clk - * - * \anchor asfdoc_sam0_rtc_count_rtc_clk - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
RTC clocks source
RTC clock frequencyClock sourceDescription
1.024KHzULP1K1.024KHz from 32KHz internal ULP oscillator
32.768KHzULP32K32.768KHz from 32KHz internal ULP oscillator
1.024KHzOSC1K1.024KHz from 32KHz internal oscillator
32.768KHzOSC32K32.768KHz from 32KHz internal oscillator
1.024KHzXOSC1K1.024KHz from 32KHz internal oscillator
32.768KHzXOSC32K32.768KHz from 32KHz external crystal oscillator
- * - * \section asfdoc_sam0_rtc_count_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_rtc_count_extra. This includes: - * - \ref asfdoc_sam0_rtc_count_extra_acronyms - * - \ref asfdoc_sam0_rtc_count_extra_dependencies - * - \ref asfdoc_sam0_rtc_count_extra_errata - * - \ref asfdoc_sam0_rtc_count_extra_history - * - * - * \section asfdoc_sam0_rtc_count_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_rtc_count_exqsg. - * - * - * \section asfdoc_sam0_rtc_count_api_overview API Overview - * @{ - */ - -#include -#include - -#if RTC_COUNT_ASYNC == true -# include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Define port features set according to different device family - * @{ -*/ -#if (SAML21) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** RTC periodic interval interrupt. */ -# define FEATURE_RTC_PERIODIC_INT -/** RTC prescaler is off. */ -# define FEATURE_RTC_PRESCALER_OFF -/** RTC clock selection. */ -# define FEATURE_RTC_CLOCK_SELECTION -# if !(SAMC20) && !(SAMC21) -/** General purpose registers. */ -# define FEATURE_RTC_GENERAL_PURPOSE_REG -# endif -#else -/** RTC continuously updated. */ -# define FEATURE_RTC_CONTINUOUSLY_UPDATED -#endif -/*@}*/ - -#ifdef FEATURE_RTC_CLOCK_SELECTION -/** - * \brief Available clock source for RTC. - * RTC clock source. - */ -enum rtc_clock_sel { - /** 1.024KHz from 32KHz internal ULP oscillator. */ - RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val, - /** 32.768KHz from 32KHz internal ULP oscillator. */ - RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val, - /** 1.024KHz from 32KHz internal oscillator. */ - RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val, - /** 32.768KHz from 32KHz internal oscillator. */ - RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val, - /** 1.024KHz from 32KHz internal oscillator. */ - RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val, - /** 32.768KHz from 32.768KHz external crystal oscillator. */ - RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val, -}; -#endif - -/** - * \brief Available operation modes for the RTC. - * - * RTC Count operating modes, to select the counting width and associated module - * operation. - */ -enum rtc_count_mode { - /** RTC Count module operates in 16-bit mode. */ - RTC_COUNT_MODE_16BIT = 0, - /** RTC Count module operates in 32-bit mode. */ - RTC_COUNT_MODE_32BIT = 1, -}; - -#if !defined (RTC_NUM_OF_COMP16) && defined(RTC_COMP16_NUM) -#define RTC_NUM_OF_COMP16 RTC_COMP16_NUM -#endif - -/** - * \brief Available compare channels. - * - * \note Not all compare channels are available in all devices and modes. - */ -enum rtc_count_compare { - /** Compare channel 0. */ - RTC_COUNT_COMPARE_0 = 0, -#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__) - /** Compare channel 1. */ - RTC_COUNT_COMPARE_1 = 1, -#endif -#if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__) - /** Compare channel 2. */ - RTC_COUNT_COMPARE_2 = 2, -#endif -#if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__) - /** Compare channel 3. */ - RTC_COUNT_COMPARE_3 = 3, -#endif -#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__) - /** Compare channel 4. */ - RTC_COUNT_COMPARE_4 = 4, -#endif -#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__) - /** Compare channel 5. */ - RTC_COUNT_COMPARE_5 = 5, -#endif -}; - -#ifdef FEATURE_RTC_PERIODIC_INT -/** - * \brief Available periodic interval source. - */ -enum rtc_count_periodic_interval { - /** Periodic interval 0. */ - RTC_COUNT_PERIODIC_INTERVAL_0 = 0, - /** Periodic interval 1. */ - RTC_COUNT_PERIODIC_INTERVAL_1 = 1, - /** Periodic interval 2. */ - RTC_COUNT_PERIODIC_INTERVAL_2 = 2, - /** Periodic interval 3. */ - RTC_COUNT_PERIODIC_INTERVAL_3 = 3, - /** Periodic interval 4. */ - RTC_COUNT_PERIODIC_INTERVAL_4 = 4, - /** Periodic interval 5. */ - RTC_COUNT_PERIODIC_INTERVAL_5 = 5, - /** Periodic interval 6. */ - RTC_COUNT_PERIODIC_INTERVAL_6 = 6, - /** Periodic interval 7. */ - RTC_COUNT_PERIODIC_INTERVAL_7 = 7, -}; -#endif - -#if RTC_COUNT_ASYNC == true -#ifdef FEATURE_RTC_PERIODIC_INT -/** - * \brief Callback types. - * - * The available callback types for the RTC count module. - */ -enum rtc_count_callback { - /** Callback for Periodic Interval 0 Interrupt. */ - RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0 = 0, - /** Callback for Periodic Interval 1 Interrupt. */ - RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_1, - /** Callback for Periodic Interval 2 Interrupt. */ - RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_2, - /** Callback for Periodic Interval 3 Interrupt. */ - RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_3, - /** Callback for Periodic Interval 4 Interrupt. */ - RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_4, - /** Callback for Periodic Interval 5 Interrupt. */ - RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_5, - /** Callback for Periodic Interval 6 Interrupt. */ - RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_6, - /** Callback for Periodic Interval 7 Interrupt. */ - RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7, - /** Callback for compare channel 0. */ - RTC_COUNT_CALLBACK_COMPARE_0, -# if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__) - /** Callback for compare channel 1. */ - RTC_COUNT_CALLBACK_COMPARE_1, -# endif -# if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__) - /** Callback for compare channel 2. */ - RTC_COUNT_CALLBACK_COMPARE_2, -# endif -# if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__) - /** Callback for compare channel 3. */ - RTC_COUNT_CALLBACK_COMPARE_3, -# endif -# if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__) - /** Callback for compare channel 4. */ - RTC_COUNT_CALLBACK_COMPARE_4, -# endif -# if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__) - /** Callback for compare channel 5. */ - RTC_COUNT_CALLBACK_COMPARE_5, -# endif - - /** Callback for overflow. */ - RTC_COUNT_CALLBACK_OVERFLOW, -# if !defined(__DOXYGEN__) - /** Total number of callbacks. */ - _RTC_COUNT_CALLBACK_N -# endif -}; -#else -/** - * \brief Callback types. - * - * The available callback types for the RTC count module. - */ -enum rtc_count_callback { - /** Callback for compare channel 0. */ - RTC_COUNT_CALLBACK_COMPARE_0 = 0, -# if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__) - /** Callback for compare channel 1. */ - RTC_COUNT_CALLBACK_COMPARE_1, -# endif -# if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__) - /** Callback for compare channel 2. */ - RTC_COUNT_CALLBACK_COMPARE_2, -# endif -# if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__) - /** Callback for compare channel 3. */ - RTC_COUNT_CALLBACK_COMPARE_3, -# endif -# if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__) - /** Callback for compare channel 4. */ - RTC_COUNT_CALLBACK_COMPARE_4, -# endif -# if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__) - /** Callback for compare channel 5. */ - RTC_COUNT_CALLBACK_COMPARE_5, -# endif - /** Callback for overflow. */ - RTC_COUNT_CALLBACK_OVERFLOW, -# if !defined(__DOXYGEN__) - /** Total number of callbacks. */ - _RTC_COUNT_CALLBACK_N -# endif -}; -#endif - -# if !defined(__DOXYGEN__) -typedef void (*rtc_count_callback_t)(void); -# endif -#endif - -#ifdef FEATURE_RTC_PRESCALER_OFF -/** - * \brief RTC input clock prescaler settings. - * - * The available input clock prescaler values for the RTC count module. - */ -enum rtc_count_prescaler { - /** RTC prescaler is off, and the input clock frequency is - prescaled by a factor of 1. */ - RTC_COUNT_PRESCALER_OFF = RTC_MODE0_CTRLA_PRESCALER_OFF, - /** RTC input clock frequency is prescaled by a factor of 1. */ - RTC_COUNT_PRESCALER_DIV_1 = RTC_MODE0_CTRLA_PRESCALER_DIV1, - /** RTC input clock frequency is prescaled by a factor of 2. */ - RTC_COUNT_PRESCALER_DIV_2 = RTC_MODE0_CTRLA_PRESCALER_DIV2, - /** RTC input clock frequency is prescaled by a factor of 4. */ - RTC_COUNT_PRESCALER_DIV_4 = RTC_MODE0_CTRLA_PRESCALER_DIV4, - /** RTC input clock frequency is prescaled by a factor of 8. */ - RTC_COUNT_PRESCALER_DIV_8 = RTC_MODE0_CTRLA_PRESCALER_DIV8, - /** RTC input clock frequency is prescaled by a factor of 16. */ - RTC_COUNT_PRESCALER_DIV_16 = RTC_MODE0_CTRLA_PRESCALER_DIV16, - /** RTC input clock frequency is prescaled by a factor of 32. */ - RTC_COUNT_PRESCALER_DIV_32 = RTC_MODE0_CTRLA_PRESCALER_DIV32, - /** RTC input clock frequency is prescaled by a factor of 64. */ - RTC_COUNT_PRESCALER_DIV_64 = RTC_MODE0_CTRLA_PRESCALER_DIV64, - /** RTC input clock frequency is prescaled by a factor of 128. */ - RTC_COUNT_PRESCALER_DIV_128 = RTC_MODE0_CTRLA_PRESCALER_DIV128, - /** RTC input clock frequency is prescaled by a factor of 256. */ - RTC_COUNT_PRESCALER_DIV_256 = RTC_MODE0_CTRLA_PRESCALER_DIV256, - /** RTC input clock frequency is prescaled by a factor of 512. */ - RTC_COUNT_PRESCALER_DIV_512 = RTC_MODE0_CTRLA_PRESCALER_DIV512, - /** RTC input clock frequency is prescaled by a factor of 1024. */ - RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRLA_PRESCALER_DIV1024, -}; -#else -/** - * \brief RTC input clock prescaler settings. - * - * The available input clock prescaler values for the RTC count module. - */ -enum rtc_count_prescaler { - /** RTC input clock frequency is prescaled by a factor of 1. */ - RTC_COUNT_PRESCALER_DIV_1 = RTC_MODE0_CTRL_PRESCALER_DIV1, - /** RTC input clock frequency is prescaled by a factor of 2. */ - RTC_COUNT_PRESCALER_DIV_2 = RTC_MODE0_CTRL_PRESCALER_DIV2, - /** RTC input clock frequency is prescaled by a factor of 4. */ - RTC_COUNT_PRESCALER_DIV_4 = RTC_MODE0_CTRL_PRESCALER_DIV4, - /** RTC input clock frequency is prescaled by a factor of 8. */ - RTC_COUNT_PRESCALER_DIV_8 = RTC_MODE0_CTRL_PRESCALER_DIV8, - /** RTC input clock frequency is prescaled by a factor of 16. */ - RTC_COUNT_PRESCALER_DIV_16 = RTC_MODE0_CTRL_PRESCALER_DIV16, - /** RTC input clock frequency is prescaled by a factor of 32. */ - RTC_COUNT_PRESCALER_DIV_32 = RTC_MODE0_CTRL_PRESCALER_DIV32, - /** RTC input clock frequency is prescaled by a factor of 64. */ - RTC_COUNT_PRESCALER_DIV_64 = RTC_MODE0_CTRL_PRESCALER_DIV64, - /** RTC input clock frequency is prescaled by a factor of 128. */ - RTC_COUNT_PRESCALER_DIV_128 = RTC_MODE0_CTRL_PRESCALER_DIV128, - /** RTC input clock frequency is prescaled by a factor of 256. */ - RTC_COUNT_PRESCALER_DIV_256 = RTC_MODE0_CTRL_PRESCALER_DIV256, - /** RTC input clock frequency is prescaled by a factor of 512. */ - RTC_COUNT_PRESCALER_DIV_512 = RTC_MODE0_CTRL_PRESCALER_DIV512, - /** RTC input clock frequency is prescaled by a factor of 1024. */ - RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRL_PRESCALER_DIV1024, -}; -#endif - -/** - * \brief RTC Count event enable/disable structure. - * - * Event flags for the \ref rtc_count_enable_events() and - * \ref rtc_count_disable_events(). - */ -struct rtc_count_events { - /** Generate an output event on each overflow of the RTC count. */ - bool generate_event_on_overflow; - /** Generate an output event on a compare channel match against the RTC - * count. */ - bool generate_event_on_compare[RTC_NUM_OF_COMP16]; - /** Generate an output event periodically at a binary division of the RTC - * counter frequency. */ - bool generate_event_on_periodic[8]; -}; - -#if !defined(__DOXYGEN__) -/** - * \brief Device structure. - */ -struct rtc_module { - /** RTC hardware module. */ - Rtc *hw; - /** Operation mode of count. */ - enum rtc_count_mode mode; -#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED - /** Set if counter value should be continuously updated. */ - bool continuously_update; -#endif -# if RTC_COUNT_ASYNC == true - /** Pointers to callback functions. */ - volatile rtc_count_callback_t callbacks[_RTC_COUNT_CALLBACK_N]; - /** Mask for registered callbacks. */ - volatile uint16_t registered_callback; - /** Mask for enabled callbacks. */ - volatile uint16_t enabled_callback; -# endif -}; -#endif - -/** - * \brief RTC Count configuration structure. - * - * Configuration structure for the RTC instance. This structure should - * be initialized using the \ref rtc_count_get_config_defaults() before any - * user configurations are set. - */ -struct rtc_count_config { - /** Input clock prescaler for the RTC module. */ - enum rtc_count_prescaler prescaler; - /** Select the operation mode of the RTC.*/ - enum rtc_count_mode mode; - /** If true, clears the counter value on compare match. Only available - * whilst running in 32-bit mode. */ - bool clear_on_match; -#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED - /** Continuously update the counter value so no synchronization is - * needed for reading. */ - bool continuously_update; -#endif -#if (SAML21) || (SAMC20) || (SAMC21) - /** Enable count read synchronization. The COUNT value requires - * synchronization when reading. Disabling the synchronization - * will prevent the COUNT value from displaying the current value. */ - bool enable_read_sync; -#endif - - /** Array of Compare values. Not all Compare values are available in 32-bit - * mode. */ - uint32_t compare_values[RTC_NUM_OF_COMP16]; -}; - - -/** - * \name Configuration and Initialization - * @{ - */ - -/** - * \brief Gets the RTC default configurations. - * - * Initializes the configuration structure to default values. This - * function should be called at the start of any RTC initialization. - * - * The default configuration is as follows: - * - Input clock divided by a factor of 1024 - * - RTC in 32-bit mode - * - Clear on compare match off - * - Continuously sync count register off - * - No event source on - * - All compare values equal 0 - * - Count read synchronization is disabled for SAML21 - * - * \param[out] config Configuration structure to be initialized to default - * values. - */ -static inline void rtc_count_get_config_defaults( - struct rtc_count_config *const config) -{ - /* Sanity check argument */ - Assert(config); - - /* Set default into configuration structure */ - config->prescaler = RTC_COUNT_PRESCALER_DIV_1024; - config->mode = RTC_COUNT_MODE_32BIT; - config->clear_on_match = false; - -#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED - config->continuously_update = false; -#endif -#if (SAML21) - config->enable_read_sync = false; -#endif - - for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) { - config->compare_values[i] = 0; - } -} - -void rtc_count_reset(struct rtc_module *const module); -void rtc_count_enable(struct rtc_module *const module); -void rtc_count_disable(struct rtc_module *const module); - -#if (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) -/** - * \internal Find the index of given RTC module instance. - * - * \param[in] RTC module instance pointer - * - * \return Index of the given AC module instance. - */ -uint8_t _rtc_get_inst_index( - Rtc *const hw) -{ - /* List of available RTC modules. */ - static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS; - - /* Find index for RTC instance. */ - for (uint32_t i = 0; i < RTC_INST_NUM; i++) { - if (hw == rtc_modules[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} -#endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */ - -enum status_code rtc_count_init( - struct rtc_module *const module, - Rtc *const hw, - const struct rtc_count_config *const config); - -enum status_code rtc_count_frequency_correction( - struct rtc_module *const module, - const int8_t value); - -/** @} */ - -/** \name Count and Compare Value Management - * @{ - */ -enum status_code rtc_count_set_count( - struct rtc_module *const module, - const uint32_t count_value); - -uint32_t rtc_count_get_count(struct rtc_module *const module); - -enum status_code rtc_count_set_compare( - struct rtc_module *const module, - const uint32_t comp_value, - const enum rtc_count_compare comp_index); - -enum status_code rtc_count_get_compare( - struct rtc_module *const module, - uint32_t *const comp_value, - const enum rtc_count_compare comp_index); - -enum status_code rtc_count_set_period( - struct rtc_module *const module, - uint16_t period_value); - -enum status_code rtc_count_get_period( - struct rtc_module *const module, - uint16_t *const period_value); - -/** @} */ - - -/** \name Status Management - * @{ - */ - -/** - * \brief Check if an RTC overflow has occurred. - * - * Checks the overflow flag in the RTC. The flag is set when there - * is an overflow in the clock. - * - * \param[in,out] module RTC hardware module - * - * \return Overflow state of the RTC module. - * - * \retval true If the RTC count value has overflowed - * \retval false If the RTC count value has not overflowed - */ - -static inline bool rtc_count_is_overflow(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Return status of flag */ - return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF); -} - -/** - * \brief Clears the RTC overflow flag. - * - * Clears the RTC module counter overflow flag, so that new overflow conditions - * can be detected. - * - * \param[in,out] module RTC hardware module - */ -static inline void rtc_count_clear_overflow(struct rtc_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Clear OVF flag */ - rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -#ifdef FEATURE_RTC_PERIODIC_INT -/** - * \brief Check if an RTC periodic interval interrupt has occurred. - * - * Checks the periodic interval flag in the RTC. - * - * \param[in,out] module RTC hardware module - * \param[in] n RTC periodic interval interrupt - * - * \return periodic interval interrupt state of the RTC module. - * - * \retval true RTC periodic interval interrupt occurs - * \retval false RTC periodic interval interrupt dosen't occurs - */ -static inline bool rtc_count_is_periodic_interval(struct rtc_module *const module, - enum rtc_count_periodic_interval n) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Return status of flag */ - return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER(1 << n)); -} - -/** - * \brief Clears the RTC periodic interval flag. - * - * Clears the RTC module counter periodic interval flag, so that new periodic - * interval conditions can be detected. - * - * \param[in,out] module RTC hardware module - * \param[in] n RTC periodic interval interrupt - */ -static inline void rtc_count_clear_periodic_interval(struct rtc_module *const module, - enum rtc_count_periodic_interval n) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - /* Clear periodic interval flag */ - rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER(1 << n); -} -#endif -bool rtc_count_is_compare_match( - struct rtc_module *const module, - const enum rtc_count_compare comp_index); - -enum status_code rtc_count_clear_compare_match( - struct rtc_module *const module, - const enum rtc_count_compare comp_index); - -/** @} */ - - -/** - * \name Event Management - * @{ - */ - -/** - * \brief Enables a RTC event output. - * - * Enables one or more output events from the RTC module. See - * \ref rtc_count_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in,out] module RTC hardware module - * \param[in] events Struct containing flags of events to enable - */ -static inline void rtc_count_enable_events( - struct rtc_module *const module, - struct rtc_count_events *const events) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - uint32_t event_mask = 0; - - /* Check if the user has requested an overflow event. */ - if (events->generate_event_on_overflow) { - event_mask |= RTC_MODE0_EVCTRL_OVFEO; - } - - /* Check if the user has requested any compare events. */ - for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) { - if (events->generate_event_on_compare[i]) { - event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i); - } - } - - /* Check if the user has requested any periodic events. */ - for (uint8_t i = 0; i < 8; i++) { - if (events->generate_event_on_periodic[i]) { - event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i); - } - } - - /* Enable given event(s). */ - rtc_module->MODE0.EVCTRL.reg |= event_mask; -} - -/** - * \brief Disables a RTC event output. - * - * Disabled one or more output events from the RTC module. See - * \ref rtc_count_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in,out] module RTC hardware module - * \param[in] events Struct containing flags of events to disable - */ -static inline void rtc_count_disable_events( - struct rtc_module *const module, - struct rtc_count_events *const events) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - Rtc *const rtc_module = module->hw; - - uint32_t event_mask = 0; - - /* Check if the user has requested an overflow event. */ - if (events->generate_event_on_overflow) { - event_mask |= RTC_MODE0_EVCTRL_OVFEO; - } - - /* Check if the user has requested any compare events. */ - for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) { - if (events->generate_event_on_compare[i]) { - event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i); - } - } - - /* Check if the user has requested any periodic events. */ - for (uint8_t i = 0; i < 8; i++) { - if (events->generate_event_on_periodic[i]) { - event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i); - } - } - - /* Disable given event(s). */ - rtc_module->MODE0.EVCTRL.reg &= ~event_mask; -} - -/** @} */ - -#ifdef FEATURE_RTC_GENERAL_PURPOSE_REG -/** - * \name RTC General Purpose Registers - * @{ - */ - -/** - * \brief Write a value into general purpose register. - * - * \param[in] module Pointer to the software instance struct - * \param[in] n General purpose type - * \param[in] index General purpose register index (0..3) - * - */ -static inline void rtc_write_general_purpose_reg( - struct rtc_module *const module, - const uint8_t index, - uint32_t value) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(index <= 3); - - Rtc *const rtc_module = module->hw; - - rtc_module->MODE0.GP[index].reg = value; -} - -/** - * \brief Read the value from general purpose register. - * - * \param[in] module Pointer to the software instance struct - * \param[in] index General purpose register index (0..3) - * - * \return Value of general purpose register - */ -static inline uint32_t rtc_read_general_purpose_reg( - struct rtc_module *const module, - const uint8_t index) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(index <= 3); - - Rtc *const rtc_module = module->hw; - - return rtc_module->MODE0.GP[index].reg; -} - -/** @} */ -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** - * \page asfdoc_sam0_rtc_count_extra Extra Information for RTC COUNT Driver - * - * \section asfdoc_sam0_rtc_count_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Acronym - * Description - *
RTCReal Time Counter
PPMPart Per Million
RCResistor/Capacitor
- * - * - * \section asfdoc_sam0_rtc_count_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_rtc_count_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_rtc_count_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Added support for SAMC21
Added support for SAML21
- * Added support for SAMD21 and added driver instance parameter to all - * API function calls, except get_config_defaults - *
Updated initialization function to also enable the digital interface - * clock to the module if it is disabled
Initial Release
- */ - -/** - * \page asfdoc_sam0_rtc_count_exqsg Examples for RTC (COUNT) Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_rtc_count_group. QSGs are simple - * examples with step-by-step instructions to configure and use this driver in a - * selection of use cases. Note that QSGs can be compiled as a standalone - * application or be added to the user application. - * - * - \subpage asfdoc_sam0_rtc_count_basic_use_case - * \if RTC_COUNT_CALLBACK_MODE - * - \subpage asfdoc_sam0_rtc_count_callback_use_case - * \endif - * - * \page asfdoc_sam0_rtc_count_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
E06/2015Added support for SAML21, SAMC21, and SAMDAx.
D12/2014Added support for SAMR21 and SAMD10/D11.
C01/2014Added support for SAMD21.
B06/2013Added additional documentation on the event system. Corrected - * documentation typos.
A06/2013Initial release
- */ - -#endif /* RTC_COUNT_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_common.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_common.h deleted file mode 100644 index e31fb3d23e1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_common.h +++ /dev/null @@ -1,572 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Common Driver - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef I2C_COMMON_H_INCLUDED -#define I2C_COMMON_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \if (I2C_MASTER_MODE && I2C_SLAVE_MODE) - * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Driver (SERCOM I2C) - * \elseif I2C_MASTER_MODE - * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Master Mode Driver (SERCOM I2C) - * \elseif I2C_SLAVE_MODE - * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Slave Mode Driver (SERCOM I2C) - * \endif - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of the device's SERCOM I2C module, for the transfer - * of data via an I2C bus. The following driver API modes are covered - * by this manual: - * - * \if I2C_MASTER_MODE - * - Master Mode Polled APIs - * \endif - * \if I2C_MASTER_CALLBACK_MODE - * - Master Mode Callback APIs - * \endif - * \if I2C_SLAVE_MODE - * - Slave Mode Polled APIs - * \endif - * \if I2C_SLAVE_CALLBACK_MODE - * - Slave Mode Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - SERCOM (Serial Communication Interface) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_sercom_i2c_prerequisites - * - \ref asfdoc_sam0_sercom_i2c_overview - * - \ref asfdoc_sam0_sercom_i2c_special_considerations - * - \ref asfdoc_sam0_sercom_i2c_extra - * - \ref asfdoc_sam0_sercom_i2c_examples - * - \ref asfdoc_sam0_sercom_i2c_api_overview - * - * \section asfdoc_sam0_sercom_i2c_prerequisites Prerequisites - * There are no prerequisites. - * - * \section asfdoc_sam0_sercom_i2c_overview Module Overview - * The outline of this section is as follows: - * - \ref asfdoc_sam0_sercom_i2c_module_features - * - \ref asfdoc_sam0_sercom_i2c_functional_desc - * - \ref asfdoc_sam0_sercom_i2c_bus_topology - * - \ref asfdoc_sam0_sercom_i2c_transactions - * - \ref asfdoc_sam0_sercom_i2c_multi_master - * - \ref asfdoc_sam0_sercom_i2c_bus_states - * - \ref asfdoc_sam0_sercom_i2c_timeout - * - \ref asfdoc_sam0_sercom_i2c_sleep_modes - * - * \subsection asfdoc_sam0_sercom_i2c_module_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEEDSAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_I2C_10_BIT_ADDRESSSAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_I2C_SCL_STRETCH_MODESAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_I2C_SCL_EXTEND_TIMEOUTSAM D21/R21/D10/D11/L21/DAx/C20/C21
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_sercom_i2c_functional_desc Functional Description - * The I2C provides a simple two-wire bidirectional bus consisting of a - * wired-AND type serial clock line (SCL) and a wired-AND type serial data line - * (SDA). - * - * The I2C bus provides a simple, but efficient method of interconnecting - * multiple master and slave devices. An arbitration mechanism is provided for - * resolving bus ownership between masters, as only one master device may own - * the bus at any given time. The arbitration mechanism relies on the wired-AND - * connections to avoid bus drivers short-circuiting. - * - * A unique address is assigned to all slave devices connected to the bus. A - * device can contain both master and slave logic, and can emulate multiple - * slave devices by responding to more than one address. - * - * \subsection asfdoc_sam0_sercom_i2c_bus_topology Bus Topology - * The I2C bus topology is illustrated in - * \ref asfdoc_sam0_sercom_i2c_bus_topology_figure "the figure below". The pull-up - * resistors (Rs) will provide a high level on the bus lines when none of the - * I2C devices are driving the bus. These are optional, and can be - * replaced with a constant current source. - * - * \anchor asfdoc_sam0_sercom_i2c_bus_topology_figure - * \image html bus_topology.svg "I2C Bus Topology" Width=100% - * - * \subsection asfdoc_sam0_sercom_i2c_transactions Transactions - * The I2C standard defines three fundamental transaction formats: - * - Master Write - * - The master transmits data packets to the slave after addressing it - * - Master Read - * - The slave transmits data packets to the master after being addressed - * - Combined Read/Write - * - A combined transaction consists of several write and read transactions - * - * A data transfer starts with the master issuing a \b Start condition on the - * bus, followed by the address of the slave together with a bit to indicate - * whether the master wants to read from or write to the slave. - * The addressed slave must respond to this by sending an \b ACK back to the - * master. - * - * After this, data packets are sent from the master or slave, according to the - * read/write bit. Each packet must be acknowledged (ACK) or not - * acknowledged (NACK) by the receiver. - * - * If a slave responds with a NACK, the master must assume that the slave - * cannot receive any more data and cancel the write operation. - * - * The master completes a transaction by issuing a \b Stop condition. - * - * A master can issue multiple \b Start conditions during a transaction; this - * is then called a \b Repeated \b Start condition. - * - * \subsubsection asfdoc_sam0_sercom_i2c_address_packets Address Packets - * The slave address consists of seven bits. The 8th bit in the transfer - * determines the data direction (read or write). An address packet always - * succeeds a \b Start or \b Repeated \b Start condition. The 8th bit is handled - * in the driver, and the user will only have to provide the 7-bit address. - * - * \subsubsection asfdoc_sam0_sercom_i2c_data_packets Data Packets - * Data packets are nine bits long, consisting of one 8-bit data byte, and an - * acknowledgement bit. Data packets follow either an address packet or another - * data packet on the bus. - * - * \subsubsection asfdoc_sam0_sercom_i2c_trans_examples Transaction Examples - * The gray bits in the following examples are sent from master to slave, and - * the white bits are sent from slave to master. - * Example of a read transaction is shown in - * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_read "the figure below". Here, the - * master first issues a \b Start condition and gets ownership of the bus. An - * address packet with the direction flag set to read is then sent and - * acknowledged by the slave. Then the slave sends one data packet which is - * acknowledged by the master. The slave sends another packet, which is not - * acknowledged by the master and indicates that the master will terminate the - * transaction. In the end, the transaction is terminated by the master issuing - * a \b Stop condition. - * - * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_read - * \image html i2c_read.svg "I2C Packet Read" Width=100% - * - * Example of a write transaction is shown in - * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_write "the figure below". Here, the - * master first issues a \b Start condition and gets ownership of the bus. An - * address packet with the dir flag set to write is then sent and acknowledged - * by the slave. Then the master sends two data packets, each acknowledged by - * the slave. In the end, the transaction is terminated by the master issuing - * a \b Stop condition. - * - * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_write - * \image html i2c_write.svg "I2C Packet Write" Width=100% - * - * \subsubsection asfdoc_sam0_sercom_i2c_packet_timeout Packet Timeout - * When a master sends an I2C packet, there is no way of - * being sure that a slave will acknowledge the packet. To avoid stalling the - * device forever while waiting for an acknowledge, a user selectable timeout - * is provided in the \ref i2c_master_config struct which - * lets the driver exit a read or write operation after the specified time. - * The function will then return the STATUS_ERR_TIMEOUT flag. - * - * This is also the case for the slave when using the functions postfixed - * \c _wait. - * - * The time before the timeout occurs, will be the same as - * for \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "unknown bus state" timeout. - * - * \subsubsection asfdoc_sam0_sercom_i2c_repeated_start Repeated Start - * To issue a \b Repeated \b Start, the functions postfixed \c _no_stop must be - * used. - * These functions will not send a \b Stop condition when the transfer is done, - * thus the next transfer will start with a \b Repeated \b Start. To end the - * transaction, the functions without the \c _no_stop postfix must be used - * for the last read/write. - * - * \subsection asfdoc_sam0_sercom_i2c_multi_master Multi Master - * In a multi master environment, arbitration of the bus is important, as only - * one master can own the bus at any point. - * - * \subsubsection asfdoc_sam0_sercom_i2c_arbitration Arbitration - * - * \par Clock stretching - * The serial clock line is always driven by a master device. However, all - * devices connected to the bus are allowed stretch the low period of the clock - * to slow down the overall clock frequency or to insert wait states while - * processing data. - * Both master and slave can randomly stretch the clock, which will force the - * other device into a wait-state until the clock line goes high again. - * - * \par Arbitration on the data line - * If two masters start transmitting at the same time, they will both transmit - * until one master detects that the other master is pulling the data line low. - * When this is detected, the master not pulling the line low, will stop the - * transmission and wait until the bus is idle. - * As it is the master trying to contact the slave with the lowest address that - * will get the bus ownership, this will create an arbitration scheme always - * prioritizing the slaves with the lowest address in case of a bus collision. - * - * \subsubsection asfdoc_sam0_sercom_i2c_clock_sync Clock Synchronization - * In situations where more than one master is trying to control the bus clock - * line at the same time, a clock synchronization algorithm based on the same - * principles used for clock stretching is necessary. - * - * - * \subsection asfdoc_sam0_sercom_i2c_bus_states Bus States - * As the I2C bus is limited to one transaction at the time, - * a master that wants to perform a bus transaction must wait until the bus is - * free. - * Because of this, it is necessary for all masters in a multi-master system to - * know the current status of the bus to be able to avoid conflicts and to - * ensure data integrity. - * \li \b IDLE No activity on the bus (between a \b Stop and a new \b Start - * condition) - * \li \b OWNER If the master initiates a transaction successfully - * \li \b BUSY If another master is driving the bus - * \li \b UNKNOWN If the master has recently been enabled or connected to - * the bus. Is forced to \b IDLE after given - * \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" when - * the master module is enabled - * - * The bus state diagram can be seen in - * \ref asfdoc_sam0_sercom_i2c_bus_states_figure "the figure below". - * \li S: Start condition - * \li P: Stop condition - * \li Sr: Repeated start condition - * \anchor asfdoc_sam0_sercom_i2c_bus_states_figure - * \image html bus_state_diagram.svg "I2C Bus State Diagram" Width=100% - * - * \subsection asfdoc_sam0_sercom_i2c_timeout Bus Timing - * Inactive bus timeout for the master and SDA hold time is configurable in the - * drivers. - * - * \subsubsection asfdoc_sam0_sercom_i2c_unknown_bus_timeout Unknown Bus State Timeout - * When a master is enabled or connected to the bus, the bus state will be - * unknown until either a given timeout or a stop command has occurred. The - * timeout is configurable in the \ref i2c_master_config struct. - * The timeout time will depend on toolchain and optimization level used, as - * the timeout is a loop incrementing a value until it reaches the specified - * timeout value. - * - * \subsubsection sda_hold SDA Hold Timeout - * When using the I2C in slave mode, it will be important to - * set a SDA hold time which assures that the master will be able to pick up - * the bit sent from the slave. The SDA hold time makes sure that this is the - * case by holding the data line low for a given period after the negative edge - * on the clock. - * - * The SDA hold time is also available for the master driver, but is not a - * necessity. - * - * \subsection asfdoc_sam0_sercom_i2c_sleep_modes Operation in Sleep Modes - * The I2C module can operate in all sleep modes by setting - * the run_in_standby Boolean in the \ref i2c_master_config or - * \ref i2c_slave_config struct. - * The operation in slave and master mode is shown in - * \ref asfdoc_sam0_sercom_i2c_sleep_modes_table "the table below". - * - * \anchor asfdoc_sam0_sercom_i2c_sleep_modes_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
I2C Standby Operations
Run in standbySlaveMaster
falseDisabled, all reception is droppedGCLK disabled when master is idle
trueWake on address match when enabledGCLK enabled while in sleep modes
- * - * - * \section asfdoc_sam0_sercom_i2c_special_considerations Special Considerations - * - * \if (I2C_MASTER_CALLBACK_MODE || I2C_SLAVE_CALLBACK_MODE) - * \subsection asfdoc_sam0_sercom_i2c_common_interrupt Interrupt-driven Operation - * While an interrupt-driven operation is in progress, subsequent calls to a - * write or read operation will return the STATUS_BUSY flag, indicating that - * only one operation is allowed at any given time. - * - * To check if another transmission can be initiated, the user can either call - * another transfer operation, or use the - * \ref i2c_master_get_job_status/\ref i2c_slave_get_job_status functions - * depending on mode. - * - * If the user would like to get callback from operations while using the - * interrupt-driven driver, the callback must be registered and then enabled - * using the "register_callback" and "enable_callback" functions. - * \else - * There are no special considerations for this driver for the APIs listed in - * this document. - * \endif - * - * \section asfdoc_sam0_sercom_i2c_extra Extra Information - * For extra information, see \ref asfdoc_sam0_sercom_i2c_extra_info_page. - * This includes: - * - \ref asfdoc_sam0_sercom_i2c_acronyms - * - \ref asfdoc_sam0_sercom_i2c_extra_dependencies - * - \ref asfdoc_sam0_sercom_i2c_extra_errata - * - \ref asfdoc_sam0_sercom_i2c_extra_history - * - * \section asfdoc_sam0_sercom_i2c_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_sercom_i2c_exqsg. - * - * \section asfdoc_sam0_sercom_i2c_api_overview API Overview - * @{ - */ - -/** - * \name Driver Feature Definition - * Define SERCOM I2C driver features set according to different device family. - * - * \note The high speed mode and 10-bit address feature are not - * supported by the driver now. - * @{ - */ -#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || (SAMDA1) || \ - (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** Fast mode plus and high speed support. */ -# define FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED -/** 10-bit address support. */ -# define FEATURE_I2C_10_BIT_ADDRESS -/** SCL stretch mode support. */ -# define FEATURE_I2C_SCL_STRETCH_MODE -/** SCL extend timeout support. */ -# define FEATURE_I2C_SCL_EXTEND_TIMEOUT -# define FEATURE_I2C_DMA_SUPPORT -#endif -/*@}*/ - -/** \brief Transfer direction - * - * For master: transfer direction or setting direction bit in address. - * For slave: direction of request from master. - */ -enum i2c_transfer_direction { - /** Master write operation is in progress. */ - I2C_TRANSFER_WRITE = 0, - /** Master read operation is in progress. */ - I2C_TRANSFER_READ = 1, -}; - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** - * \page asfdoc_sam0_sercom_i2c_extra_info_page Extra Information for SERCOM I2C Driver - * - * \section asfdoc_sam0_sercom_i2c_acronyms Acronyms - * \ref asfdoc_sam0_sercom_i2c_acronyms_table "Below" is a table listing the acronyms - * used in this module, along with their intended meanings. - * - * \anchor asfdoc_sam0_sercom_i2c_acronyms_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Acronyms
AcronymDescription
SDASerial Data Line
SCLSerial Clock Line
SERCOMSerial Communication Interface
DMADirect Memory Access
- * - * \section asfdoc_sam0_sercom_i2c_extra_dependencies Dependencies - * The I2C driver has the following dependencies: - * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_sercom_i2c_extra_errata Errata - * There are no errata related to this driver. - * - * \section asfdoc_sam0_sercom_i2c_extra_history Module History - * \ref asfdoc_sam0_sercom_i2c_extra_history_table "Below" is an overview of the - * module history, detailing enhancements and fixes made to the module since - * its first release. The current version of this corresponds to the newest - * version listed in - * \ref asfdoc_sam0_sercom_i2c_extra_history_table "the table below". - * - * \anchor asfdoc_sam0_sercom_i2c_extra_history_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Module History
Changelog
- * \li Added 10-bit addressing and high speed support in SAM D21 - * \li Separate structure i2c_packet into i2c_master_packet and i2c_slave packet - *
- * \li Added support for SCL stretch and extended timeout hardware features in SAM D21 - * \li Added fast mode plus support in SAM D21 - *
Fixed incorrect logical mask for determining if a bus error has - * occurred in I2C Slave mode - *
Initial Release
- */ - -/** - * \page asfdoc_sam0_sercom_i2c_exqsg Examples for SERCOM I2C Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_sercom_i2c_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * \if I2C_MASTER_MODE - * - \subpage asfdoc_sam0_sercom_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case" - * \endif - * \if I2C_MASTER_CALLBACK_MODE - * - \subpage asfdoc_sam0_sercom_i2c_master_callback_use_case "Quick Start Guide for the I2C Master module - Callback Use Case" - * - \subpage asfdoc_sam0_sercom_i2c_master_dma_use_case "Quick Start Guide for the I2C Master module - DMA Use Case" - * \endif - * \if I2C_SLAVE_MODE - * - \subpage asfdoc_sam0_sercom_i2c_slave_basic_use_case "Quick Start Guide for the I2C Slave module - Basic Use Case" - * \endif - * \if I2C_SLAVE_CALLBACK_MODE - * - \subpage asfdoc_sam0_sercom_i2c_slave_callback_use_case "Quick Start Guide for the I2C Slave module - Callback Use Case" - * - \subpage asfdoc_sam0_sercom_i2c_slave_dma_use_case "Quick Start Guide for the I2C Slave module - DMA Use Case" - * \endif - * - * \page asfdoc_sam0_sercom_i2c_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
E06/2015Added SAM L21, SAMDAx and SAMC21 support.
D12/2014Added 10-bit addressing and high speed support in SAM D21 - * Added SAM R21/D10/D11 support.
C01/2014Added the SAM D21 to the application note.
B06/2013Corrected documentation typos. Updated I2C Bus State Diagram.
A06/2013Initial release.
- */ - -#endif /* I2C_COMMON_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master.h deleted file mode 100644 index 61ebb084236..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master.h +++ /dev/null @@ -1,623 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Master Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2C_MASTER_H_INCLUDED -#define I2C_MASTER_H_INCLUDED - -#include "i2c_common.h" -#include -#include - -#if I2C_MASTER_CALLBACK_MODE == true -# include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef PINMUX_DEFAULT -# define PINMUX_DEFAULT 0 -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_i2c_group - * - * @{ - */ - -/** - * \brief I2C master packet for read/write - * - * Structure to be used when transferring I2C master packets. - */ -struct i2c_master_packet { - /** Address to slave device. */ - uint16_t address; - /** Length of data array. */ - uint16_t data_length; - /** Data array containing all data to be transferred. */ - uint8_t *data; - /** Use 10-bit addressing. Set to false if the feature is not supported by the device. */ - bool ten_bit_address; - /** Use high speed transfer. Set to false if the feature is not supported by the device. */ - bool high_speed; - /** High speed mode master code (0000 1XXX), valid when high_speed is true. */ - uint8_t hs_master_code; -}; - -/** \brief Interrupt flags - * - * Flags used when reading or setting interrupt flags. - */ -enum i2c_master_interrupt_flag { - /** Interrupt flag used for write. */ - I2C_MASTER_INTERRUPT_WRITE = 0, - /** Interrupt flag used for read. */ - I2C_MASTER_INTERRUPT_READ = 1, -}; - -/** - * \brief Values for hold time after start bit. - * - * Values for the possible I2C master mode SDA internal hold times after start - * bit has been sent. - */ -enum i2c_master_start_hold_time { - /** Internal SDA hold time disabled. */ - I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0), - /** Internal SDA hold time 50ns - 100ns. */ - I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1), - /** Internal SDA hold time 300ns - 600ns. */ - I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2), - /** Internal SDA hold time 400ns - 800ns. */ - I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3), -}; - -/** - * \brief Values for inactive bus time-out. - * - * If the inactive bus time-out is enabled and the bus is inactive for - * longer than the time-out setting, the bus state logic will be set to idle. - */ -enum i2c_master_inactive_timeout { - /** Inactive bus time-out disabled. */ - I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0), - /** Inactive bus time-out 5-6 SCL cycle time-out. */ - I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1), - /** Inactive bus time-out 10-11 SCL cycle time-out. */ - I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2), - /** Inactive bus time-out 20-21 SCL cycle time-out. */ - I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3), -}; - -/** - * \brief I2C frequencies - * - * Values for I2C speeds supported by the module. The driver - * will also support setting any other value, in which case set - * the value in the \ref i2c_master_config at desired value divided by 1000. - * - * Example: If 10KHz operation is required, give baud_rate in the configuration - * structure the value 10. - */ -enum i2c_master_baud_rate { - /** Baud rate at 100KHz (Standard-mode). */ - I2C_MASTER_BAUD_RATE_100KHZ = 100, - /** Baud rate at 400KHz (Fast-mode). */ - I2C_MASTER_BAUD_RATE_400KHZ = 400, -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Baud rate at 1MHz (Fast-mode Plus). */ - I2C_MASTER_BAUD_RATE_1000KHZ = 1000, - /** Baud rate at 3.4MHz (High-speed mode). */ - I2C_MASTER_BAUD_RATE_3400KHZ = 3400, -#endif -}; - -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED -/** - * \brief Enum for the transfer speed - * - * Enum for the transfer speed. - */ -enum i2c_master_transfer_speed { - /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz. */ - I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0), - /** Fast-mode Plus (Fm+) up to 1MHz. */ - I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1), - /** High-speed mode (Hs-mode) up to 3.4MHz. */ - I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2), -}; -#endif - -#if I2C_MASTER_CALLBACK_MODE == true -/** - * \brief Callback types - * - * The available callback types for the I2C master module. - */ -enum i2c_master_callback { - /** Callback for packet write complete. */ - I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0, - /** Callback for packet read complete. */ - I2C_MASTER_CALLBACK_READ_COMPLETE = 1, - /** Callback for error. */ - I2C_MASTER_CALLBACK_ERROR = 2, -# if !defined(__DOXYGEN__) - /** Total number of callbacks. */ - _I2C_MASTER_CALLBACK_N = 3, -# endif -}; - -# if !defined(__DOXYGEN__) -/* Prototype for software module. */ -struct i2c_master_module; - -typedef void (*i2c_master_callback_t)( - struct i2c_master_module *const module); -# endif -#endif - -/** - * \brief SERCOM I2C Master driver software device instance structure. - * - * SERCOM I2C Master driver software instance structure, used to - * retain software state information of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct i2c_master_module { -#if !defined(__DOXYGEN__) - /** Hardware instance initialized for the struct. */ - Sercom *hw; - /** Module lock. */ - volatile bool locked; - /** Unknown bus state timeout. */ - uint16_t unknown_bus_state_timeout; - /** Buffer write timeout value. */ - uint16_t buffer_timeout; - /** If true, stop condition will be sent after a read/write. */ - bool send_stop; - /** If true, nack signal will be sent after a read/write. */ - bool send_nack; -# if I2C_MASTER_CALLBACK_MODE == true - /** Pointers to callback functions. */ - volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N]; - /** Mask for registered callbacks. */ - volatile uint8_t registered_callback; - /** Mask for enabled callbacks. */ - volatile uint8_t enabled_callback; - /** The total number of bytes to transfer. */ - volatile uint16_t buffer_length; - /** - * Counter used for bytes left to send in write and to count number of - * obtained bytes in read. - */ - volatile uint16_t buffer_remaining; - /** Data buffer for packet write and read. */ - volatile uint8_t *buffer; - /** Save direction of async request. 1 = read, 0 = write. */ - volatile enum i2c_transfer_direction transfer_direction; - /** Status for status read back in error callback. */ - volatile enum status_code status; -# endif -#endif -}; - -/** - * \brief Configuration structure for the I2C Master device - * - * This is the configuration structure for the I2C Master device. It - * is used as an argument for \ref i2c_master_init to provide the desired - * configurations for the module. The structure should be initialized using the - * \ref i2c_master_get_config_defaults . - */ -struct i2c_master_config { - /** Baud rate (in KHz) for I2C operations in - * standard-mode, Fast-mode and Fast-mode Plus Transfers, - * \ref i2c_master_baud_rate. */ - uint32_t baud_rate; -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Baud rate (in KHz) for I2C operations in - * High-speed mode, \ref i2c_master_baud_rate. */ - uint32_t baud_rate_high_speed; - /** Transfer speed mode. */ - enum i2c_master_transfer_speed transfer_speed; -#endif - /** GCLK generator to use as clock source. */ - enum gclk_generator generator_source; - /** Bus hold time after start signal on data line. */ - enum i2c_master_start_hold_time start_hold_time; - /** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout". */ - uint16_t unknown_bus_state_timeout; - /** Timeout for packet write to wait for slave. */ - uint16_t buffer_timeout; - /** Set to keep module active in sleep modes. */ - bool run_in_standby; - /** PAD0 (SDA) pinmux. */ - uint32_t pinmux_pad0; - /** PAD1 (SCL) pinmux. */ - uint32_t pinmux_pad1; - /** Set to enable SCL low time-out. */ - bool scl_low_timeout; - /** Inactive bus time out. */ - enum i2c_master_inactive_timeout inactive_timeout; -#ifdef FEATURE_I2C_SCL_STRETCH_MODE - /** Set to enable SCL stretch only after ACK bit (required for high speed). */ - bool scl_stretch_only_after_ack_bit; -#endif -#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - /** Set to enable slave SCL low extend time-out. */ - bool slave_scl_low_extend_timeout; - /** Set to enable maser SCL low extend time-out. */ - bool master_scl_low_extend_timeout; -#endif - /** Get more accurate BAUD, considering rise time(required for standard-mode and Fast-mode). */ - uint16_t sda_scl_rise_time_ns; -}; - -/** - * \name Lock/Unlock - * @{ - */ - -/** - * \brief Attempt to get lock on driver instance - * - * This function checks the instance's lock, which indicates whether or not it - * is currently in use, and sets the lock if it was not already set. - * - * The purpose of this is to enable exclusive access to driver instances, so - * that, e.g., transactions by different services will not interfere with each - * other. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline enum status_code i2c_master_lock( - struct i2c_master_module *const module) -{ - enum status_code status; - - system_interrupt_enter_critical_section(); - - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } - - system_interrupt_leave_critical_section(); - - return status; -} - -/** - * \brief Unlock driver instance - * - * This function clears the instance lock, indicating that it is available for - * use. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline void i2c_master_unlock(struct i2c_master_module *const module) -{ - module->locked = false; -} - -/** @} */ - -/** - * \name Configuration and Initialization - * @{ - */ - -/** - * \brief Returns the synchronization status of the module - * - * Returns the synchronization status of the module. - * - * \param[in] module Pointer to software module structure - * - * \return Status of the synchronization. - * \retval true Module is busy synchronizing - * \retval false Module is not synchronizing - */ -static inline bool i2c_master_is_syncing ( - const struct i2c_master_module *const module) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_hw = &(module->hw->I2CM); - -#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1) - return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY); -#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2) - return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK); -#else -# error Unknown SERCOM SYNCBUSY scheme! -#endif -} - -#if !defined(__DOXYGEN__) -/** - * \internal - * Wait for hardware module to sync - * - * \param[in] module Pointer to software module structure - */ -static void _i2c_master_wait_for_sync( - const struct i2c_master_module *const module) -{ - /* Sanity check. */ - Assert(module); - - while (i2c_master_is_syncing(module)) { - /* Wait for I2C module to sync. */ - } -} -#endif - -/** - * \brief Gets the I2C master default configurations - * - * Use to initialize the configuration structure to known default values. - * - * The default configuration is as follows: - * - Baudrate 100KHz - * - GCLK generator 0 - * - Do not run in standby - * - Start bit hold time 300ns - 600ns - * - Buffer timeout = 65535 - * - Unknown bus status timeout = 65535 - * - Do not run in standby - * - PINMUX_DEFAULT for SERCOM pads - * - * Those default configuration only available if the device supports it: - * - High speed baudrate 3.4MHz - * - Standard-mode and Fast-mode transfer speed - * - SCL stretch disabled - * - slave SCL low extend time-out disabled - * - maser SCL low extend time-out disabled - * - * \param[out] config Pointer to configuration structure to be initiated - */ -static inline void i2c_master_get_config_defaults( - struct i2c_master_config *const config) -{ - /*Sanity check argument. */ - Assert(config); - config->baud_rate = I2C_MASTER_BAUD_RATE_100KHZ; -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ; - config->transfer_speed = I2C_MASTER_SPEED_STANDARD_AND_FAST; -#endif - config->generator_source = GCLK_GENERATOR_0; - config->run_in_standby = false; - config->start_hold_time = I2C_MASTER_START_HOLD_TIME_300NS_600NS; - config->buffer_timeout = 65535; - config->unknown_bus_state_timeout = 65535; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->scl_low_timeout = false; - config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED; -#ifdef FEATURE_I2C_SCL_STRETCH_MODE - config->scl_stretch_only_after_ack_bit = false; -#endif -#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - config->slave_scl_low_extend_timeout = false; - config->master_scl_low_extend_timeout = false; -#endif - /* The typical value is 215ns */ - config->sda_scl_rise_time_ns = 215; -} - -enum status_code i2c_master_init( - struct i2c_master_module *const module, - Sercom *const hw, - const struct i2c_master_config *const config); - -/** - * \brief Enables the I2C module - * - * Enables the requested I2C module and set the bus state to IDLE - * after the specified \ref asfdoc_sam0_sercom_i2c_timeout "timeout" period if no - * stop bit is detected. - * - * \param[in] module Pointer to the software module struct - */ -static inline void i2c_master_enable( - const struct i2c_master_module *const module) -{ - /* Sanity check of arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Timeout counter used to force bus state. */ - uint32_t timeout_counter = 0; - - /* Wait for module to sync. */ - _i2c_master_wait_for_sync(module); - - /* Enable module. */ - i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; - -#if I2C_MASTER_CALLBACK_MODE == true - /* Enable module interrupts */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); -#endif - /* Start timeout if bus state is unknown. */ - while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) { - timeout_counter++; - if(timeout_counter >= (module->unknown_bus_state_timeout)) { - /* Timeout, force bus state to idle. */ - i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1); - /* Workaround #1 */ - return; - } - } -} - -/** - * \brief Disable the I2C module - * - * Disables the requested I2C module. - * - * \param[in] module Pointer to the software module struct - */ -static inline void i2c_master_disable( - const struct i2c_master_module *const module) -{ - /* Sanity check of arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for module to sync. */ - _i2c_master_wait_for_sync(module); - - /* Disable module. */ - i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; - -#if I2C_MASTER_CALLBACK_MODE == true - /* Disable module interrupts */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); -#endif -} - -void i2c_master_reset(struct i2c_master_module *const module); - -/** @} */ - -/** -* \name Read and Write -* @{ -*/ - -enum status_code i2c_master_read_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_read_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -void i2c_master_send_stop(struct i2c_master_module *const module); - -void i2c_master_send_nack(struct i2c_master_module *const module); - -enum status_code i2c_master_read_byte( - struct i2c_master_module *const module, - uint8_t *byte); - -enum status_code i2c_master_write_byte( - struct i2c_master_module *const module, - uint8_t byte); - -enum status_code i2c_master_read_packet_wait_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -/** @} */ - -#ifdef FEATURE_I2C_DMA_SUPPORT -/** -* \name SERCOM I2C Master with DMA Interfaces -* @{ -*/ - -/** - * \brief Set I2C for DMA transfer with slave address and transfer size. - * - * This function will set the slave address, transfer size and enable the auto transfer - * mode for DMA. - * - * \param[in,out] module Pointer to the driver instance to lock - * \param[in] addr I2C slave address - * \param[in] length I2C transfer length with DMA - * \param[in] direction I2C transfer direction - * - */ -static inline void i2c_master_dma_set_transfer(struct i2c_master_module *const module, - uint16_t addr, uint8_t length, enum i2c_transfer_direction direction) -{ - module->hw->I2CM.ADDR.reg = - SERCOM_I2CM_ADDR_ADDR(addr<<1) | - SERCOM_I2CM_ADDR_LENEN | - SERCOM_I2CM_ADDR_LEN(length) | - direction; -} - -/** @} */ -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* I2C_MASTER_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master_interrupt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master_interrupt.h deleted file mode 100644 index 8b8c2cc2021..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master_interrupt.h +++ /dev/null @@ -1,214 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Master Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2C_MASTER_INTERRUPT_H_INCLUDED -#define I2C_MASTER_INTERRUPT_H_INCLUDED - -#include "i2c_master.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_i2c_group - * @{ - * - */ - -/** - * \name Callbacks - * @{ - */ -#if !defined(__DOXYGEN__) -void _i2c_master_interrupt_handler( - uint8_t instance); -#endif - -void i2c_master_register_callback( - struct i2c_master_module *const module, - i2c_master_callback_t callback, - enum i2c_master_callback callback_type); - -void i2c_master_unregister_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type); - -/** - * \brief Enables callback - * - * Enables the callback specified by the callback_type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to enable - */ -static inline void i2c_master_enable_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - - /* Mark callback as enabled. */ - module->enabled_callback |= (1 << callback_type); -} - -/** - * \brief Disables callback - * - * Disables the callback specified by the callback_type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to disable - */ -static inline void i2c_master_disable_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - - /* Mark callback as disabled. */ - module->enabled_callback &= ~(1 << callback_type); -} - -/** @} */ - -/** - * \name Read and Write, Interrupt-Driven - * @{ - */ - -enum status_code i2c_master_read_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_read_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_read_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_read_packet_job_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -/** - * \brief Cancel any currently ongoing operation - * - * Terminates the running transfer operation. - * - * \param[in,out] module Pointer to software module structure - */ -static inline void i2c_master_cancel_job( - struct i2c_master_module *const module) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - - /* Set buffer to 0. */ - module->buffer_remaining = 0; - /* Update status*/ - module->status = STATUS_ABORTED; -} - -/** - * \brief Get status from ongoing job - * - * Will return the status of a transfer operation. - * - * \param[in] module Pointer to software module structure - * - * \return Last status code from transfer operation. - * \retval STATUS_OK No error has occurred - * \retval STATUS_BUSY If transfer is in progress - * \retval STATUS_BUSY If master module is busy - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * \retval STATUS_ERR_TIMEOUT If timeout occurred - * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent - * data, indicating that slave does not - * want more data and was not able to read - */ -static inline enum status_code i2c_master_get_job_status( - struct i2c_master_module *const module) -{ - /* Check sanity. */ - Assert(module); - Assert(module->hw); - - /* Return current status code. */ - return module->status; -} - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* I2C_MASTER_INTERRUPT_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master.c deleted file mode 100644 index c7d9c39fb8d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master.c +++ /dev/null @@ -1,1040 +0,0 @@ -/** - * \file - * - * \brief SAM I2C Master Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_master.h" - -#if I2C_MASTER_CALLBACK_MODE == true -# include "i2c_master_interrupt.h" -#endif - -/* Forward declaration */ -enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module); - -enum status_code _i2c_master_address_response( - struct i2c_master_module *const module); - -enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code); - -#if !defined(__DOXYGEN__) - -/** - * \internal Sets configurations to module - * - * \param[out] module Pointer to software module structure - * \param[in] config Configuration structure with configurations to set - * - * \return Status of setting configuration. - * \retval STATUS_OK If module was configured correctly - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible - * with set GCLK frequency - */ -static enum status_code _i2c_master_set_config( - struct i2c_master_module *const module, - const struct i2c_master_config *const config) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(config); - - /* Temporary variables. */ - uint32_t tmp_ctrla; - int32_t tmp_baud; - int32_t tmp_baud_hs; - enum status_code tmp_status_code = STATUS_OK; - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - Sercom *const sercom_hw = module->hw; - - uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw); - - /* Pin configuration */ - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - uint32_t pad0 = config->pinmux_pad0; - uint32_t pad1 = config->pinmux_pad1; - - /* SERCOM PAD0 - SDA */ - if (pad0 == PINMUX_DEFAULT) { - pad0 = _sercom_get_default_pad(sercom_hw, 0); - } - pin_conf.mux_position = pad0 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); - - /* SERCOM PAD1 - SCL */ - if (pad1 == PINMUX_DEFAULT) { - pad1 = _sercom_get_default_pad(sercom_hw, 1); - } - pin_conf.mux_position = pad1 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); - - /* Save timeout on unknown bus state in software module. */ - module->unknown_bus_state_timeout = config->unknown_bus_state_timeout; - - /* Save timeout on buffer write. */ - module->buffer_timeout = config->buffer_timeout; - - /* Set whether module should run in standby. */ - if (config->run_in_standby || system_is_debugger_present()) { - tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY; - } else { - tmp_ctrla = 0; - } - - /* Check and set start data hold timeout. */ - if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) { - tmp_ctrla |= config->start_hold_time; - } - - /* Check and set transfer speed */ - tmp_ctrla |= config->transfer_speed; - - /* Check and set SCL low timeout. */ - if (config->scl_low_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN; - } - - /* Check and set inactive bus timeout. */ - if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) { - tmp_ctrla |= config->inactive_timeout; - } - - /* Check and set SCL clock stretch mode. */ - if (config->scl_stretch_only_after_ack_bit) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM; - } - - /* Check and set slave SCL low extend timeout. */ - if (config->slave_scl_low_extend_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN; - } - - /* Check and set master SCL low extend timeout. */ - if (config->master_scl_low_extend_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN; - } - - /* Write config to register CTRLA. */ - i2c_module->CTRLA.reg |= tmp_ctrla; - - /* Set configurations in CTRLB. */ - i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN; - - /* Find and set baudrate, considering sda/scl rise time */ - uint32_t fgclk = system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index); - uint32_t fscl = 1000*config->baud_rate; - uint32_t trise = config->sda_scl_rise_time_ns; - int32_t numerator = fgclk - fscl*(10 + fgclk*trise/1000000000); - int32_t denominator = 2*fscl; - /* For more accurate result, can use round div. */ - tmp_baud = (int32_t)(div_ceil(numerator, denominator)); - - /* Check that baudrate is supported at current speed. */ - if (tmp_baud > 255 || tmp_baud < 0) { - /* Baud rate not supported. */ - tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; - } else { - /* Find baudrate for high speed */ - tmp_baud_hs = (int32_t)(div_ceil( - system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index), - (2000*(config->baud_rate_high_speed))) - 1); - - /* Check that baudrate is supported at current speed. */ - if (tmp_baud_hs > 255 || tmp_baud_hs < 0) { - /* Baud rate not supported. */ - tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - } - if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) { - /* Baud rate acceptable. */ - i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) | - SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs); - } - - return tmp_status_code; -} -#endif /* __DOXYGEN__ */ - -/** - * \brief Initializes the requested I2C hardware module - * - * Initializes the SERCOM I2C master device requested and sets the provided - * software module struct. Run this function before any further use of - * the driver. - * - * \param[out] module Pointer to software module struct - * \param[in] hw Pointer to the hardware instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible - * with set GCLK frequency - * - */ -enum status_code i2c_master_init( - struct i2c_master_module *const module, - Sercom *const hw, - const struct i2c_master_config *const config) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize software module */ - module->hw = hw; - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index, gclk_index; -#if (SAML21) || (SAMC20) || (SAMC21) -#if (SAML21) - if (sercom_index == 5) { - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#else - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - /* Turn on module in PM */ -#if (SAML21) - if (sercom_index == 5) { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - - /* Check if module is enabled. */ - if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress. */ - if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) { - return STATUS_BUSY; - } - -#if I2C_MASTER_CALLBACK_MODE == true - /* Get sercom instance index and register callback. */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - _sercom_set_handler(instance_index, _i2c_master_interrupt_handler); - _sercom_instances[instance_index] = module; - - /* Initialize values in module. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->buffer_remaining = 0; - - module->status = STATUS_OK; - module->buffer = NULL; -#endif - - /* Set sercom module to operate in I2C master mode. */ - i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5); - - /* Set config and return status. */ - return _i2c_master_set_config(module, config); -} - -/** - * \brief Resets the hardware module - * - * Reset the module to hardware defaults. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_master_reset(struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for sync */ - _i2c_master_wait_for_sync(module); - - /* Disable module */ - i2c_master_disable(module); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Clear all pending interrupts */ - system_interrupt_enter_critical_section(); - system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); - system_interrupt_leave_critical_section(); -#endif - - /* Wait for sync */ - _i2c_master_wait_for_sync(module); - - /* Reset module */ - i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST; -} - -#if !defined(__DOXYGEN__) -/** - * \internal - * Address response. Called when address is answered or timed out. - * - * \param[in,out] module Pointer to software module structure - * - * \return Status of address response. - * \retval STATUS_OK No error has occurred - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code _i2c_master_address_response( - struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in - * BUSY */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) { - - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; - - /* Check arbitration. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) { - /* Return packet collision. */ - return STATUS_ERR_PACKET_COLLISION; - } - /* Check that slave responded with ack. */ - } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Slave busy. Issue ack and stop command. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - - /* Return bad address value. */ - return STATUS_ERR_BAD_ADDRESS; - } - - return STATUS_OK; -} - -/** - * \internal - * Waits for answer on bus. - * - * \param[in,out] module Pointer to software module structure - * - * \return Status of bus. - * \retval STATUS_OK If given response from slave device - * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout - * period - */ -enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for reply. */ - uint16_t timeout_counter = 0; - while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) && - !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) { - - /* Check timeout condition. */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; -} -#endif /* __DOXYGEN__ */ - -/** - * \internal - * Send master code for high speed transfer. - * - * \param[in,out] module Pointer to software module structure - * \param[in] hs_master_code 8-bit master code (0000 1XXX) - * - * \return Status of bus. - * \retval STATUS_OK No error happen - */ -enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code) -{ - SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Return value. */ - enum status_code tmp_status; - - /* Set NACK for high speed code */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - /* Send high speed code */ - i2c_module->ADDR.reg = hs_master_code; - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB; - - return tmp_status; -} - - -/** - * \internal - * Starts blocking read operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * - */ -static enum status_code _i2c_master_read_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Return value. */ - enum status_code tmp_status; - uint16_t tmp_data_length = packet->data_length; - - /* Written buffer counter. */ - uint16_t counter = 0; - - bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; - - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } - - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Set address and direction bit. Will send start command on bus. */ - if (packet->ten_bit_address) { - /* - * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must - * be set and read/write bit (ADDR.ADDR[0]) equal to 0. - */ - i2c_module->ADDR.reg = (packet->address << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - if (tmp_status == STATUS_OK) { - /* - * Write ADDR[7:0] register to "11110 address[9:8] 1" - * ADDR.TENBITEN must be cleared - */ - i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - I2C_TRANSFER_READ; - } else { - return tmp_status; - } - } else { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - /* Check that no error has occurred. */ - if (tmp_status == STATUS_OK) { - /* Read data buffer. */ - while (tmp_data_length--) { - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return STATUS_ERR_PACKET_COLLISION; - } - - if (module->send_nack && (((!sclsm_flag) && (tmp_data_length == 0)) || - ((sclsm_flag) && (tmp_data_length == 1)))) { - /* Set action to NACK */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } else { - /* Save data to buffer. */ - _i2c_master_wait_for_sync(module); - packet->data[counter++] = i2c_module->DATA.reg; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - } - - /* Check for error. */ - if (tmp_status != STATUS_OK) { - break; - } - } - - if (module->send_stop) { - /* Send stop command unless arbitration is lost. */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - - /* Save last data to buffer. */ - _i2c_master_wait_for_sync(module); - packet->data[counter] = i2c_module->DATA.reg; - } - - return tmp_status; -} - -/** - * \brief Reads data packet from slave - * - * Reads a data packet from the specified slave address on the I2C - * bus and sends a stop condition when finished. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = true; - module->send_nack = true; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Reads data packet from slave without sending a stop condition when done - * - * Reads a data packet from the specified slave address on the I2C - * bus without sending a stop condition when done, thus retaining ownership of - * the bus when done. To end the transaction, a - * \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = true; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts blocking read operation. - * \brief Reads data packet from slave without sending a nack signal and a stop - * condition when done - * - * Reads a data packet from the specified slave address on the I2C - * bus without sending a nack signal and a stop condition when done, - * thus retaining ownership of the bus when done. To end the transaction, a - * \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = false; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts blocking write operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK The packet was write successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -static enum status_code _i2c_master_write_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Return value. */ - enum status_code tmp_status; - uint16_t tmp_data_length = packet->data_length; - - _i2c_master_wait_for_sync(module); - - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } - - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Set address and direction bit. Will send start command on bus. */ - if (packet->ten_bit_address) { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - } else { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - /* Check that no error has occurred. */ - if (tmp_status == STATUS_OK) { - /* Buffer counter. */ - uint16_t buffer_counter = 0; - - /* Write data buffer. */ - while (tmp_data_length--) { - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return STATUS_ERR_PACKET_COLLISION; - } - - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = packet->data[buffer_counter++]; - - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Check for error. */ - if (tmp_status != STATUS_OK) { - break; - } - - /* Check for NACK from slave. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Return bad data value. */ - tmp_status = STATUS_ERR_OVERFLOW; - break; - } - } - - if (module->send_stop) { - /* Stop command */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } - - return tmp_status; -} - -/** - * \brief Writes data packet to slave - * - * Writes a data packet to the specified slave address on the I2C bus - * and sends a stop condition when finished. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK If packet was write successfully - * \retval STATUS_BUSY If master module is busy with a job - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * \retval STATUS_ERR_TIMEOUT If timeout occurred - * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent - * data, indicating that slave does not - * want more data and was not able to read - * last data sent - */ -enum status_code i2c_master_write_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = true; - module->send_nack = true; - - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Writes data packet to slave without sending a stop condition when done - * - * Writes a data packet to the specified slave address on the I2C bus - * without sending a stop condition, thus retaining ownership of the bus when - * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition or sending a - * stop with the \ref i2c_master_send_stop function must be performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK If packet was write successfully - * \retval STATUS_BUSY If master module is busy - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * \retval STATUS_ERR_TIMEOUT If timeout occurred - * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent - * data, indicating that slave do not want - * more data - */ -enum status_code i2c_master_write_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = true; - - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Sends stop condition on bus - * - * Sends a stop condition on bus. - * - * \note This function can only be used after the - * \ref i2c_master_write_packet_wait_no_stop function. If a stop condition - * is to be sent after a read, the \ref i2c_master_read_packet_wait - * function must be used. - * - * \param[in,out] module Pointer to the software instance struct - */ -void i2c_master_send_stop(struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Send stop command */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); -} - -/** - * \brief Sends nack signal on bus - * - * Sends a nack signal on bus. - * - * \note This function can only be used after the - * \ref i2c_master_write_packet_wait_no_nack function, - * or \ref i2c_master_read_byte function. - * \param[in,out] module Pointer to the software instance struct - */ -void i2c_master_send_nack(struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Send nack signal */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; -} - -/** - * \brief Reads one byte data from slave - * - * \param[in,out] module Pointer to software module struct - * \param[out] byte Read one byte data to slave - * - * \return Status of reading byte. - * \retval STATUS_OK One byte was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_byte( - struct i2c_master_module *const module, - uint8_t *byte) -{ - enum status_code tmp_status; - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - *byte = i2c_module->DATA.reg; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - - return tmp_status; -} - -/** - * \brief Write one byte data to slave - * - * \param[in,out] module Pointer to software module struct - * \param[in] byte Send one byte data to slave - * - * \return Status of writing byte. - * \retval STATUS_OK One byte was write successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_write_byte( - struct i2c_master_module *const module, - uint8_t byte) -{ - enum status_code tmp_status; - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = byte; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - return tmp_status; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c deleted file mode 100644 index 305f3e9ab4d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c +++ /dev/null @@ -1,753 +0,0 @@ -/** - * \file - * - * \brief SAM I2C Master Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_master_interrupt.h" - -extern enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module); - -extern enum status_code _i2c_master_address_response( - struct i2c_master_module *const module); - -extern enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code);; - -/** - * \internal - * Read next data. Used by interrupt handler to get next data byte from slave. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_read( - struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; - - /* Find index to save next value in buffer */ - uint16_t buffer_index = module->buffer_length; - buffer_index -= module->buffer_remaining; - - module->buffer_remaining--; - - if (sclsm_flag) { - if (module->send_nack && module->buffer_remaining == 1) { - /* Set action to NACK. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } - } else { - if (module->send_nack && module->buffer_remaining == 0) { - /* Set action to NACK. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } - } - - if (module->buffer_remaining == 0) { - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } - - /* Read byte from slave and put in buffer */ - _i2c_master_wait_for_sync(module); - module->buffer[buffer_index] = i2c_module->DATA.reg; -} - -/** - * \internal - * - * Write next data. Used by interrupt handler to send next data byte to slave. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_write(struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for ack from slave */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Set status */ - module->status = STATUS_ERR_OVERFLOW; - /* Do not write more data */ - return; - } - - /* Find index to get next byte in buffer */ - uint16_t buffer_index = module->buffer_length; - buffer_index -= module->buffer_remaining; - - module->buffer_remaining--; - - /* Write byte from buffer to slave */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = module->buffer[buffer_index]; -} - -/** - * \internal - * Acts on slave address response. Checks for errors concerning master->slave - * handshake. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_async_address_response( - struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for error. Ignore bus-error; workaround for bus state stuck in - * BUSY. - */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) { - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB; - - /* Check arbitration */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) { - /* Return busy */ - module->status = STATUS_ERR_PACKET_COLLISION; - } - } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Return bad address value */ - module->status = STATUS_ERR_BAD_ADDRESS; - module->buffer_remaining = 0; - - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } - - module->buffer_length = module->buffer_remaining; - - /* Check for status OK. */ - if (module->status == STATUS_BUSY) { - /* Call function based on transfer direction. */ - if (module->transfer_direction == I2C_TRANSFER_WRITE) { - _i2c_master_write(module); - } else { - _i2c_master_read(module); - } - } -} - -/** - * \brief Registers callback for the specified callback type - * - * Associates the given callback function with the - * specified callback type. - * - * To enable the callback, the \ref i2c_master_enable_callback function - * must be used. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback Pointer to the function desired for the - * specified callback - * \param[in] callback_type Callback type to register - */ -void i2c_master_register_callback( - struct i2c_master_module *const module, - const i2c_master_callback_t callback, - enum i2c_master_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(callback); - - /* Register callback */ - module->callbacks[callback_type] = callback; - - /* Set corresponding bit to set callback as registered */ - module->registered_callback |= (1 << callback_type); -} - -/** - * \brief Unregisters callback for the specified callback type - * - * When called, the currently registered callback for the given callback type - * will be removed. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Specifies the callback type to unregister - */ -void i2c_master_unregister_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Register callback */ - module->callbacks[callback_type] = NULL; - - /* Clear corresponding bit to set callback as unregistered */ - module->registered_callback &= ~(1 << callback_type); -} - -/** - * \internal - * Starts a read bytes operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_read_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_READ; - module->status = STATUS_BUSY; - module->send_stop = false; - module->send_nack = false; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - return STATUS_OK; -} - -/** - * \internal - * Starts a read packet operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -static enum status_code _i2c_master_read_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - enum status_code tmp_status; - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_READ; - module->status = STATUS_BUSY; - - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } - - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - if (packet->ten_bit_address) { - /* - * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must - * be set and read/write bit (ADDR.ADDR[0]) equal to 0. - */ - i2c_module->ADDR.reg = (packet->address << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - if (tmp_status == STATUS_OK) { - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - /* - * Write ADDR[7:0] register to "11110 address[9:8] 1" - * ADDR.TENBITEN must be cleared - */ - i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - I2C_TRANSFER_READ; - } else { - return tmp_status; - } - } else { - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - /* Set address and direction bit. Will send start command on bus */ - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - - return STATUS_OK; -} - -/** - * \brief Initiates a read packet operation - * - * Reads a data packet from the specified slave address on the I2C - * bus. This is the non-blocking equivalent of \ref i2c_master_read_packet_wait. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_read_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we send STOP */ - module->send_stop = true; - module->send_nack = true; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Initiates a read packet operation without sending a STOP condition when done - * - * Reads a data packet from the specified slave address on the I2C bus without - * sending a stop condition, thus retaining ownership of the bus when done. - * To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another operation - */ -enum status_code i2c_master_read_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we don't send STOP */ - module->send_stop = false; - module->send_nack = true; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Initiates a read packet operation without sending a NACK signal and a - * STOP condition when done - * - * Reads a data packet from the specified slave address on the I2C bus without - * sending a nack and a stop condition, thus retaining ownership of the bus when done. - * To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another operation - */ -enum status_code i2c_master_read_packet_job_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we don't send STOP */ - module->send_stop = false; - module->send_nack = false; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts a write bytes operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting write I2C bytes. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_write_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_WRITE; - module->status = STATUS_BUSY; - module->send_stop = false; - module->send_nack = false; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - return STATUS_OK; -} - -/** - * \internal Initiates a write packet operation - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -static enum status_code _i2c_master_write_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } - - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_WRITE; - module->status = STATUS_BUSY; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - /* Set address and direction bit, will send start command on bus */ - if (packet->ten_bit_address) { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - } else { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - - return STATUS_OK; -} - -/** - * \brief Initiates a write packet operation - * - * Writes a data packet to the specified slave address on the I2C - * bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_write_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with another job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we send STOP at end*/ - module->send_stop = true; - module->send_nack = true; - /* Start write operation */ - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Initiates a write packet operation without sending a STOP condition when done - * - * Writes a data packet to the specified slave address on the I2C bus - * without sending a stop condition, thus retaining ownership of the bus when - * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition or sending - * a stop with the \ref i2c_master_send_stop function must be performed. - * - * This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another - */ -enum status_code i2c_master_write_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with another job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Do not send stop condition when done */ - module->send_stop = false; - module->send_nack = true; - /* Start write operation */ - return _i2c_master_write_packet(module, packet); -} - -/** - * \internal - * Interrupt handler for I2C master. - * - * \param[in] instance SERCOM instance that triggered the interrupt - */ -void _i2c_master_interrupt_handler( - uint8_t instance) -{ - /* Get software module for callback handling */ - struct i2c_master_module *module = - (struct i2c_master_module*)_sercom_instances[instance]; - - Assert(module); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; - - /* Combine callback registered and enabled masks */ - uint8_t callback_mask = module->enabled_callback; - callback_mask &= module->registered_callback; - - /* Check if the module should respond to address ack */ - if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) { - /* Call function for address response */ - _i2c_master_async_address_response(module); - - /* Check if buffer write is done */ - } else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) && - (module->status == STATUS_BUSY) && - (module->transfer_direction == I2C_TRANSFER_WRITE)) { - /* Stop packet operation */ - i2c_module->INTENCLR.reg = - SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB; - - module->buffer_length = 0; - module->status = STATUS_OK; - - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } else { - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; - } - - if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) { - module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module); - } - - /* Continue buffer write/read */ - } else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)) { - /* Check that bus ownership is not lost */ - if ((!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) && - (!(sclsm_flag && (module->buffer_remaining == 1)))) { - module->status = STATUS_ERR_PACKET_COLLISION; - } else if (module->transfer_direction == I2C_TRANSFER_WRITE) { - _i2c_master_write(module); - } else { - _i2c_master_read(module); - } - } - - /* Check if read buffer transfer is complete */ - if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) && - (module->status == STATUS_BUSY) && - (module->transfer_direction == I2C_TRANSFER_READ)) { - - /* Clear read interrupt flag */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) { - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; - } - /* Stop packet operation */ - i2c_module->INTENCLR.reg = - SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB; - module->buffer_length = 0; - module->status = STATUS_OK; - - /* Call appropriate callback if enabled and registered */ - if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_READ)) { - module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module); - } else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_WRITE)) { - module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module); - } - } - - /* Check for error */ - if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) { - /* Stop packet operation */ - i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB | - SERCOM_I2CM_INTENCLR_SB; - - module->buffer_length = 0; - module->buffer_remaining = 0; - - /* Send nack and stop command unless arbitration is lost */ - if ((module->status != STATUS_ERR_PACKET_COLLISION) && - module->send_stop) { - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT | - SERCOM_I2CM_CTRLB_CMD(3); - } - - /* Call error callback if enabled and registered */ - if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) { - module->callbacks[I2C_MASTER_CALLBACK_ERROR](module); - } - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_slave.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_slave.c deleted file mode 100644 index f740b502aae..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_slave.c +++ /dev/null @@ -1,740 +0,0 @@ -/** - * \file - * - * \brief SAM I2C Slave Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_slave.h" -#if I2C_SLAVE_CALLBACK_MODE == true -# include "i2c_slave_interrupt.h" -#endif - -/** - * \internal Sets configuration to module - * - * \param[out] module Pointer to software module structure - * \param[in] config Configuration structure with configurations to set - * - * \return Status of setting configuration. - * \retval STATUS_OK Module was configured correctly - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - */ -static enum status_code _i2c_slave_set_config( - struct i2c_slave_module *const module, - const struct i2c_slave_config *const config) -{ - uint32_t tmp_ctrla; - - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(config); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - Sercom *const sercom_hw = module->hw; - - module->buffer_timeout = config->buffer_timeout; - module->ten_bit_address = config->ten_bit_address; - - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - uint32_t pad0 = config->pinmux_pad0; - uint32_t pad1 = config->pinmux_pad1; - - /* SERCOM PAD0 - SDA */ - if (pad0 == PINMUX_DEFAULT) { - pad0 = _sercom_get_default_pad(sercom_hw, 0); - } - pin_conf.mux_position = pad0 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); - - /* SERCOM PAD1 - SCL */ - if (pad1 == PINMUX_DEFAULT) { - pad1 = _sercom_get_default_pad(sercom_hw, 1); - } - pin_conf.mux_position = pad1 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); - - /* Prepare config to write to register CTRLA */ - if (config->run_in_standby || system_is_debugger_present()) { - tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY; - } else { - tmp_ctrla = 0; - } - - tmp_ctrla |= ((uint32_t)config->sda_hold_time | - config->transfer_speed | - (config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) | - (config->scl_stretch_only_after_ack_bit << SERCOM_I2CS_CTRLA_SCLSM_Pos) | - (config->slave_scl_low_extend_timeout << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)); - - i2c_hw->CTRLA.reg |= tmp_ctrla; - - /* Set CTRLB configuration */ - i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode; - - i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos | - config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos | - config->ten_bit_address << SERCOM_I2CS_ADDR_TENBITEN_Pos | - config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos; - - return STATUS_OK; -} - -/** - * \brief Initializes the requested I2C hardware module - * - * Initializes the SERCOM I2C Slave device requested and sets the provided - * software module struct. Run this function before any further use of - * the driver. - * - * \param[out] module Pointer to software module struct - * \param[in] hw Pointer to the hardware instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - */ -enum status_code i2c_slave_init( - struct i2c_slave_module *const module, - Sercom *const hw, - const struct i2c_slave_config *const config) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize software module */ - module->hw = hw; - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Check if module is enabled. */ - if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress. */ - if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) { - return STATUS_BUSY; - } - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index, gclk_index; -#if (SAML21) || (SAMC20) || (SAMC21) -#if (SAML21) - if (sercom_index == 5) { - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#else - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - /* Turn on module in PM */ -#if (SAML21) - if (sercom_index == 5) { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Get sercom instance index. */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - - /* Save software module in interrupt handler. */ - _sercom_set_handler(instance_index, _i2c_slave_interrupt_handler); - - /* Save software module. */ - _sercom_instances[instance_index] = module; - - /* Initialize values in module. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->nack_on_address = config->enable_nack_on_address; -#endif - - /* Set SERCOM module to operate in I2C slave mode. */ - i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x4); - - /* Set config and return status. */ - return _i2c_slave_set_config(module, config); -} - -/** - * \brief Resets the hardware module - * - * This will reset the module to hardware defaults. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_slave_reset( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Reset module instance. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->buffer_remaining = 0; - module->buffer = NULL; -#endif - - /* Disable module */ - i2c_slave_disable(module); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Clear all pending interrupts. */ - system_interrupt_enter_critical_section(); - system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); - system_interrupt_leave_critical_section(); -#endif - - /* Wait for sync. */ - _i2c_slave_wait_for_sync(module); - - /* Reset module. */ - i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST; -} - -/** - * \internal Waits for answer on bus - * - * \param[in] module Pointer to software module structure - * - * \return Status of bus. - * \retval STATUS_OK If given response from slave device - * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout - * period - */ -static enum status_code _i2c_slave_wait_for_bus( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for reply. */ - uint16_t timeout_counter = 0; - while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) && - (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) && - (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) { - - /* Check timeout condition. */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; -} - -/** - * \brief Writes a packet to the master - * - * Writes a packet to the master. This will wait for the master to issue - * a request. - * - * \param[in] module Pointer to software module structure - * \param[in] packet Packet to write to master - * - * \return Status of packet write. - * \retval STATUS_OK Packet was written successfully - * \retval STATUS_ERR_DENIED Start condition not received, another - * interrupt flag is set - * \retval STATUS_ERR_IO There was an error in the previous transfer - * \retval STATUS_ERR_BAD_FORMAT Master wants to write data - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) was provided - * \retval STATUS_ERR_BUSY The I2C module is busy with a job - * \retval STATUS_ERR_ERR_OVERFLOW Master NACKed before entire packet was - * transferred - * \retval STATUS_ERR_TIMEOUT No response was given within the timeout - * period - */ -enum status_code i2c_slave_write_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint16_t length = packet->data_length; - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Check if the module is busy with a job or AMATCH is enabled */ - if (module->buffer_remaining > 0 || - (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - return STATUS_BUSY; - } -#endif - - enum status_code status; - /* Wait for master to send address packet */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - - if (module->ten_bit_address) { - /* ACK the first address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - - /* Wait for address interrupt */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return STATUS_ERR_TIMEOUT; - } - - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - } - - /* Check if there was an error in last transfer */ - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - return STATUS_ERR_IO; - } - - /* Check direction */ - if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Write request from master, send NACK and return */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - return STATUS_ERR_BAD_FORMAT; - } - - /* Read request from master, ACK address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - - uint16_t i = 0; - - /* Wait for data interrupt */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - while (length--) { - /* Write data */ - _i2c_slave_wait_for_sync(module); - i2c_hw->DATA.reg = packet->data[i++]; - - /* Wait for response from master */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK && - length !=0) { - /* NACK from master, abort */ - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - - return STATUS_ERR_OVERFLOW; - } - /* ACK from master, continue writing */ - } - - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - - return STATUS_OK; -} - -/** - * \brief Reads a packet from the master - * - * Reads a packet from the master. This will wait for the master to issue a - * request. - * - * \param[in] module Pointer to software module structure - * \param[out] packet Packet to read from master - * - * \return Status of packet read. - * \retval STATUS_OK Packet was read successfully - * \retval STATUS_ABORTED Master sent stop condition or repeated - * start before specified length of bytes - * was received - * \retval STATUS_ERR_IO There was an error in the previous transfer - * \retval STATUS_ERR_DENIED Start condition not received, another - * interrupt flag is set - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) was provided - * \retval STATUS_ERR_BUSY The I2C module is busy with a job - * \retval STATUS_ERR_BAD_FORMAT Master wants to read data - * \retval STATUS_ERR_ERR_OVERFLOW Last byte received overflows buffer - */ -enum status_code i2c_slave_read_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint16_t length = packet->data_length; - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Check if the module is busy with a job or AMATCH is enabled */ - if (module->buffer_remaining > 0 || - (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - return STATUS_BUSY; - } -#endif - - enum status_code status; - - /* Wait for master to send address packet */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - - /* Check if there was an error in the last transfer */ - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - return STATUS_ERR_IO; - } - /* Check direction */ - if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Read request from master, send NACK and return */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - return STATUS_ERR_BAD_FORMAT; - } - - /* Write request from master, ACK address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - - uint16_t i = 0; - while (length--) { - - /* Wait for next byte or stop condition */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) || - i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - /* Master sent stop condition, or repeated start, read done */ - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - return STATUS_ABORTED; - } - - /* Read data */ - _i2c_slave_wait_for_sync(module); - packet->data[i++] = i2c_hw->DATA.reg; - - } - - /* Packet read done, wait for packet to NACK, Stop or repeated start */ - status = _i2c_slave_wait_for_bus(module); - - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) { - /* Buffer is full, send NACK */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - } - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) { - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - return STATUS_OK; -} - -/** - * \brief Waits for a start condition on the bus - * - * \note This function is only available for 7-bit slave addressing. - * - * Waits for the master to issue a start condition on the bus. - * Note that this function does not check for errors in the last transfer, - * this will be discovered when reading or writing. - * - * \param[in] module Pointer to software module structure - * - * \return Direction of the current transfer, when in slave mode. - * \retval I2C_SLAVE_DIRECTION_NONE No request from master within timeout - * period - * \retval I2C_SLAVE_DIRECTION_READ Write request from master - * \retval I2C_SLAVE_DIRECTION_WRITE Read request from master - */ -enum i2c_slave_direction i2c_slave_get_direction_wait( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - enum status_code status; - - /* Wait for address interrupt */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return I2C_SLAVE_DIRECTION_NONE; - } - - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return I2C_SLAVE_DIRECTION_NONE; - } - - /* Check direction */ - if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Read request from master */ - return I2C_SLAVE_DIRECTION_WRITE; - } else { - /* Write request from master */ - return I2C_SLAVE_DIRECTION_READ; - } -} - -/** - * \brief Retrieves the current module status - * - * Checks the status of the module and returns it as a bitmask of status - * flags. - * - * \param[in] module Pointer to the I2C slave software device struct - * - * \return Bitmask of status flags. - * - * \retval I2C_SLAVE_STATUS_ADDRESS_MATCH A valid address has been received - * \retval I2C_SLAVE_STATUS_DATA_READY A I2C slave byte transmission is - * successfully completed - * \retval I2C_SLAVE_STATUS_STOP_RECEIVED A stop condition is detected for a - * transaction being processed - * \retval I2C_SLAVE_STATUS_CLOCK_HOLD The slave is holding the SCL line - * low - * \retval I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT An SCL low time-out has occurred - * \retval I2C_SLAVE_STATUS_REPEATED_START Indicates a repeated start, only - * valid if \ref - * I2C_SLAVE_STATUS_ADDRESS_MATCH is - * set - * \retval I2C_SLAVE_STATUS_RECEIVED_NACK The last data packet sent was not - * acknowledged - * \retval I2C_SLAVE_STATUS_COLLISION The I2C slave was not able to - * transmit a high data or NACK bit - * \retval I2C_SLAVE_STATUS_BUS_ERROR An illegal bus condition has - * occurred on the bus - */ -uint32_t i2c_slave_get_status( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint8_t intflags = i2c_hw->INTFLAG.reg; - uint8_t status = i2c_hw->STATUS.reg; - uint32_t status_flags = 0; - - /* Check Address Match flag */ - if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) { - status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH; - } - /* Check Data Ready flag */ - if (intflags & SERCOM_I2CS_INTFLAG_DRDY) { - status_flags |= I2C_SLAVE_STATUS_DATA_READY; - } - /* Check Stop flag */ - if (intflags & SERCOM_I2CS_INTFLAG_PREC) { - status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED; - } - /* Check Clock Hold */ - if (status & SERCOM_I2CS_STATUS_CLKHOLD) { - status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD; - } - /* Check SCL Low Timeout */ - if (status & SERCOM_I2CS_STATUS_LOWTOUT) { - status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT; - } - /* Check Repeated Start */ - if (status & SERCOM_I2CS_STATUS_SR) { - status_flags |= I2C_SLAVE_STATUS_REPEATED_START; - } - /* Check Received Not Acknowledge */ - if (status & SERCOM_I2CS_STATUS_RXNACK) { - status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK; - } - /* Check Transmit Collision */ - if (status & SERCOM_I2CS_STATUS_COLL) { - status_flags |= I2C_SLAVE_STATUS_COLLISION; - } - /* Check Bus Error */ - if (status & SERCOM_I2CS_STATUS_BUSERR) { - status_flags |= I2C_SLAVE_STATUS_BUS_ERROR; - } - - return status_flags; -} - -/** - * \brief Clears a module status flag - * - * Clears the given status flag of the module. - * - * \note Not all status flags can be cleared. - * - * \param[in] module Pointer to the I2C software device struct - * \param[in] status_flags Bit mask of status flags to clear - * - */ -void i2c_slave_clear_status( - struct i2c_slave_module *const module, - uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Clear Address Match flag */ - if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } - /* Clear Data Ready flag */ - if (status_flags & I2C_SLAVE_STATUS_DATA_READY) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; - } - /* Clear Stop flag */ - if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - /* Clear SCL Low Timeout */ - if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - } - /* Clear Transmit Collision */ - if (status_flags & I2C_SLAVE_STATUS_COLLISION) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL; - } - /* Clear Bus Error */ - if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave.h deleted file mode 100644 index 642952f71fb..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave.h +++ /dev/null @@ -1,749 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Slave Driver - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2C_SLAVE_H_INCLUDED -#define I2C_SLAVE_H_INCLUDED - -#include "i2c_common.h" -#include -#include - -#if I2C_SLAVE_CALLBACK_MODE == true -# include -#endif - -#ifndef PINMUX_DEFAULT -# define PINMUX_DEFAULT 0 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_i2c_group - * - * @{ - * - */ - -/** - * \name I2C Slave Status Flags - * - * I2C slave status flags, returned by \ref i2c_slave_get_status() and cleared - * by \ref i2c_slave_clear_status(). - * @{ - */ - -/** Address Match. - * \note Should only be cleared internally by driver. - */ -#define I2C_SLAVE_STATUS_ADDRESS_MATCH (1UL << 0) -/** Data Ready. */ -#define I2C_SLAVE_STATUS_DATA_READY (1UL << 1) -/** Stop Received. */ -#define I2C_SLAVE_STATUS_STOP_RECEIVED (1UL << 2) -/** Clock Hold. - * \note Cannot be cleared, only valid when I2C_SLAVE_STATUS_ADDRESS_MATCH is - * set. - */ -#define I2C_SLAVE_STATUS_CLOCK_HOLD (1UL << 3) -/** SCL Low Timeout. */ -#define I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT (1UL << 4) -/** Repeated Start. - * \note Cannot be cleared, only valid when I2C_SLAVE_STATUS_ADDRESS_MATCH is - * set. - */ -#define I2C_SLAVE_STATUS_REPEATED_START (1UL << 5) -/** Received not acknowledge. - * \note Cannot be cleared. - */ -#define I2C_SLAVE_STATUS_RECEIVED_NACK (1UL << 6) -/** Transmit Collision. */ -#define I2C_SLAVE_STATUS_COLLISION (1UL << 7) -/** Bus error. */ -#define I2C_SLAVE_STATUS_BUS_ERROR (1UL << 8) - -/** @} */ - -/** - * \brief I2C slave packet for read/write - * - * Structure to be used when transferring I2C slave packets. - */ -struct i2c_slave_packet { - /** Length of data array. */ - uint16_t data_length; - /** Data array containing all data to be transferred. */ - uint8_t *data; -}; - -#if I2C_SLAVE_CALLBACK_MODE == true -/** -* \brief Callback types -* -* The available callback types for the I2C slave. -*/ -enum i2c_slave_callback { - /** Callback for packet write complete. */ - I2C_SLAVE_CALLBACK_WRITE_COMPLETE, - /** Callback for packet read complete. */ - I2C_SLAVE_CALLBACK_READ_COMPLETE, - /** - * Callback for read request from master - can be used to - * issue a write. - */ - I2C_SLAVE_CALLBACK_READ_REQUEST, - /** - * Callback for write request from master - can be used to issue a read. - */ - I2C_SLAVE_CALLBACK_WRITE_REQUEST, - /** Callback for error. */ - I2C_SLAVE_CALLBACK_ERROR, - /** - * Callback for error in last transfer. Discovered on a new address - * interrupt. - */ - I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER, -# if !defined(__DOXYGEN__) - /** Total number of callbacks. */ - _I2C_SLAVE_CALLBACK_N, -# endif -}; - -# if !defined(__DOXYGEN__) -/** Software module prototype. */ -struct i2c_slave_module; - -/** Callback type. */ -typedef void (*i2c_slave_callback_t)( - struct i2c_slave_module *const module); -# endif -#endif - -/** - * \brief Enum for the possible SDA hold times with respect to the negative - * edge of SCL - * - * Enum for the possible SDA hold times with respect to the negative edge - * of SCL. - */ -enum i2c_slave_sda_hold_time { - /** SDA hold time disabled. */ - I2C_SLAVE_SDA_HOLD_TIME_DISABLED = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((0) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 50ns - 100ns. */ - I2C_SLAVE_SDA_HOLD_TIME_50NS_100NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((1) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 300ns - 600ns. */ - I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((2) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 400ns - 800ns. */ - I2C_SLAVE_SDA_HOLD_TIME_400NS_800NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), -}; - -/** - * \brief Enum for the possible address modes - * - * Enum for the possible address modes. - */ -enum i2c_slave_address_mode { - /** Address match on address_mask used as a mask to address. */ - I2C_SLAVE_ADDRESS_MODE_MASK = SERCOM_I2CS_CTRLB_AMODE(0), - /** Address math on both address and address_mask. */ - I2C_SLAVE_ADDRESS_MODE_TWO_ADDRESSES = SERCOM_I2CS_CTRLB_AMODE(1), - /** - * Address match on range of addresses between and including address and - * address_mask. - */ - I2C_SLAVE_ADDRESS_MODE_RANGE = SERCOM_I2CS_CTRLB_AMODE(2), -}; - -/** - * \brief Enum for the direction of a request - * - * Enum for the direction of a request. - */ -enum i2c_slave_direction { - /** Read. */ - I2C_SLAVE_DIRECTION_READ, - /** Write. */ - I2C_SLAVE_DIRECTION_WRITE, - /** No direction. */ - I2C_SLAVE_DIRECTION_NONE, -}; - -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED -/** - * \brief Enum for the transfer speed - * - * Enum for the transfer speed. - */ -enum i2c_slave_transfer_speed { - /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz. */ - I2C_SLAVE_SPEED_STANDARD_AND_FAST = SERCOM_I2CS_CTRLA_SPEED(0), - /** Fast-mode Plus (Fm+) up to 1MHz. */ - I2C_SLAVE_SPEED_FAST_MODE_PLUS = SERCOM_I2CS_CTRLA_SPEED(1), - /** High-speed mode (Hs-mode) up to 3.4MHz. */ - I2C_SLAVE_SPEED_HIGH_SPEED = SERCOM_I2CS_CTRLA_SPEED(2), -}; -#endif - -/** - * \brief SERCOM I2C Slave driver software device instance structure. - * - * SERCOM I2C Slave driver software instance structure, used to - * retain software state information of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct i2c_slave_module { -#if !defined(__DOXYGEN__) - /** Hardware instance initialized for the struct. */ - Sercom *hw; - /** Module lock. */ - volatile bool locked; - /** Timeout value for polled functions. */ - uint16_t buffer_timeout; -# ifdef FEATURE_I2C_10_BIT_ADDRESS - /** Using 10-bit addressing for the slave. */ - bool ten_bit_address; -# endif -# if I2C_SLAVE_CALLBACK_MODE == true - /** Nack on address match. */ - bool nack_on_address; - /** Pointers to callback functions. */ - volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N]; - /** Mask for registered callbacks. */ - volatile uint8_t registered_callback; - /** Mask for enabled callbacks. */ - volatile uint8_t enabled_callback; - /** The total number of bytes to transfer. */ - volatile uint16_t buffer_length; - /** - * Counter used for bytes left to send in write and to count number of - * obtained bytes in read. - */ - uint16_t buffer_remaining; - /** Data buffer for packet write and read. */ - volatile uint8_t *buffer; - /** Save direction of request from master. 1 = read, 0 = write. */ - volatile enum i2c_transfer_direction transfer_direction; - /** Status for status read back in error callback. */ - volatile enum status_code status; -# endif -#endif -}; - -/** - * \brief Configuration structure for the I2C Slave device - * - * This is the configuration structure for the I2C Slave device. It is used - * as an argument for \ref i2c_slave_init to provide the desired - * configurations for the module. The structure should be initialized using the - * \ref i2c_slave_get_config_defaults. - */ -struct i2c_slave_config { - /** Set to enable the SCL low timeout. */ - bool enable_scl_low_timeout; - /** SDA hold time with respect to the negative edge of SCL. */ - enum i2c_slave_sda_hold_time sda_hold_time; - /** Timeout to wait for master in polled functions. */ - uint16_t buffer_timeout; - /** Addressing mode. */ - enum i2c_slave_address_mode address_mode; - /** Address or upper limit of address range. */ - uint16_t address; - /** Address mask, second address or lower limit of address range. */ - uint16_t address_mask; -#ifdef FEATURE_I2C_10_BIT_ADDRESS - /** Enable 10-bit addressing. */ - bool ten_bit_address; -#endif - /** - * Enable general call address recognition (general call address - * is defined as 0000000 with direction bit 0). - */ - bool enable_general_call_address; - -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Transfer speed mode. */ - enum i2c_slave_transfer_speed transfer_speed; -#endif - -#if I2C_SLAVE_CALLBACK_MODE == true - /** - * Enable NACK on address match (this can be changed after initialization - * via the \ref i2c_slave_enable_nack_on_address and - * \ref i2c_slave_disable_nack_on_address functions). - */ - bool enable_nack_on_address; -#endif - /** GCLK generator to use as clock source. */ - enum gclk_generator generator_source; - /** Set to keep module active in sleep modes. */ - bool run_in_standby; - /** PAD0 (SDA) pinmux. */ - uint32_t pinmux_pad0; - /** PAD1 (SCL) pinmux. */ - uint32_t pinmux_pad1; - /** Set to enable SCL low time-out. */ - bool scl_low_timeout; -#ifdef FEATURE_I2C_SCL_STRETCH_MODE - /** Set to enable SCL stretch only after ACK bit (required for high speed). */ - bool scl_stretch_only_after_ack_bit; -#endif -#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - /** Set to enable slave SCL low extend time-out. */ - bool slave_scl_low_extend_timeout; -#endif -}; - - -/** - * \name Lock/Unlock - * @{ - */ - -/** - * \brief Attempt to get lock on driver instance - * - * This function checks the instance's lock, which indicates whether or not it - * is currently in use, and sets the lock if it was not already set. - * - * The purpose of this is to enable exclusive access to driver instances, so - * that, e.g., transactions by different services will not interfere with each - * other. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline enum status_code i2c_slave_lock( - struct i2c_slave_module *const module) -{ - enum status_code status; - - system_interrupt_enter_critical_section(); - - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } - - system_interrupt_leave_critical_section(); - - return status; -} - -/** - * \brief Unlock driver instance - * - * This function clears the instance lock, indicating that it is available for - * use. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline void i2c_slave_unlock(struct i2c_slave_module *const module) -{ - module->locked = false; -} - -/** @} */ - -/** - * \name Configuration and Initialization - * @{ - */ - -/** - * \brief Returns the synchronization status of the module - * - * Returns the synchronization status of the module. - * - * \param[out] module Pointer to software module structure - * - * \return Status of the synchronization. - * \retval true Module is busy synchronizing - * \retval false Module is not synchronizing - */ -static inline bool i2c_slave_is_syncing( - const struct i2c_slave_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Return sync status */ -#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1) - return (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_SYNCBUSY); -#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2) - return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_MASK); -#else -# error Unknown SERCOM SYNCBUSY scheme! -#endif -} - -#if !defined(__DOXYGEN__) -/** - * \internal Wait for hardware module to sync - * - * \param[in] module Pointer to software module structure - */ -static void _i2c_slave_wait_for_sync( - const struct i2c_slave_module *const module) -{ - /* Sanity check. */ - Assert(module); - - while (i2c_slave_is_syncing(module)) { - /* Wait for I2C module to sync */ - } -} -#endif - -///@cond INTERNAL -/** - * \internal Workaround for errata 13574 - * Instead set ACK/NACK of CTRLB - * - * This errata exist in part revisions of SAMD20/D21 - * D10/D11/L21/DAx/C20/C21, but workaround can be works in all - * revision of those device. As this function operation - * should be use less cpu time as possible, so caller - * function can ignore to check revision number, and use - * this workaround in all revision of those device. - * - * \param[in,out] module Pointer to software module structure - * \param[in] send_ack true send ACK, false send NACK - */ -static inline void _i2c_slave_set_ctrlb_ackact( - struct i2c_slave_module *const module, - bool send_ack) -{ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if (SAMD20 || SAMD21 || SAMD10 || SAMD11 || SAML21 || SAMDA1 || SAMC20 || SAMC21) - /* Workaround, Following two write are atomic */ - system_interrupt_enter_critical_section(); - i2c_hw->STATUS.reg = 0; - - if (send_ack == true) { - i2c_hw->CTRLB.reg = 0; - } else { - i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; - } - system_interrupt_leave_critical_section(); -#else - /* Normal operation */ - if (send_ack == true) { - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - } else { - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - } -#endif - return; -} - -/** - * \internal Workaround for SAM0 errata 13574, - * instead Set CMD3 of CTRLB - * - * This errata exist in part revisions of SAMD20/D21 - * D10/D11/L21/DAx/C20/C21, but workaround can be works in all - * revision of those device. As this function operation - * should be use less cpu time as possible, so caller - * function can ignore to check revision number, and use - * this workaround in all revision of those device. - * - * \param[in,out] module Pointer to software module structure - */ -static inline void _i2c_slave_set_ctrlb_cmd3( - struct i2c_slave_module *const module) -{ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if (SAMD20 || SAMD21 || SAMD10 || SAMD11 || SAML21 || SAMDA1 || SAMC20 || SAMC21) - /* Workaround */ - /* - * Below code instead i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3); - * CMD=0x3 clears all interrupts, so to keep the result similar - * PREC is cleared if it was set - */ - if (i2c_hw->INTFLAG.bit.PREC) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -#else - /* Normal operation */ - i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3); -#endif - return; -} -///@endcond - -/** - * \brief Gets the I2C slave default configurations - * - * This will initialize the configuration structure to known default values. - * - * The default configuration is as follows: - * - Disable SCL low timeout - * - 300ns - 600ns SDA hold time - * - Buffer timeout = 65535 - * - Address with mask - * - Address = 0 - * - Address mask = 0 (one single address) - * - General call address disabled - * - Address nack disabled if the interrupt driver is used - * - GCLK generator 0 - * - Do not run in standby - * - PINMUX_DEFAULT for SERCOM pads - * - * Those default configuration only available if the device supports it: - * - Not using 10-bit addressing - * - Standard-mode and Fast-mode transfer speed - * - SCL stretch disabled - * - slave SCL low extend time-out disabled - * - * \param[out] config Pointer to configuration structure to be initialized - */ -static inline void i2c_slave_get_config_defaults( - struct i2c_slave_config *const config) -{ - /*Sanity check argument. */ - Assert(config); - config->enable_scl_low_timeout = false; - config->sda_hold_time = I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS; - config->buffer_timeout = 65535; - config->address_mode = I2C_SLAVE_ADDRESS_MODE_MASK; - config->address = 0; - config->address_mask = 0; -#ifdef FEATURE_I2C_10_BIT_ADDRESS - config->ten_bit_address = false; -#endif - config->enable_general_call_address = false; -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - config->transfer_speed = I2C_SLAVE_SPEED_STANDARD_AND_FAST; -#endif -#if I2C_SLAVE_CALLBACK_MODE == true - config->enable_nack_on_address = false; -#endif - config->generator_source = GCLK_GENERATOR_0; - config->run_in_standby = false; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->scl_low_timeout = false; -#ifdef FEATURE_I2C_SCL_STRETCH_MODE - config->scl_stretch_only_after_ack_bit = false; -#endif -#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - config->slave_scl_low_extend_timeout = false; -#endif -} - -enum status_code i2c_slave_init(struct i2c_slave_module *const module, - Sercom *const hw, - const struct i2c_slave_config *const config); - -/** - * \brief Enables the I2C module - * - * This will enable the requested I2C module. - * - * \param[in] module Pointer to the software module struct - */ -static inline void i2c_slave_enable( - const struct i2c_slave_module *const module) -{ - /* Sanity check of arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Enable global interrupt for module */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); -#endif - - /* Wait for module to sync */ - _i2c_slave_wait_for_sync(module); - - /* Enable module */ - i2c_hw->CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; -} - - -/** - * \brief Disables the I2C module - * - * This will disable the I2C module specified in the provided software module - * structure. - * - * \param[in] module Pointer to the software module struct - */ -static inline void i2c_slave_disable( - const struct i2c_slave_module *const module) -{ - /* Sanity check of arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Disable interrupts */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC | - SERCOM_I2CS_INTENSET_AMATCH | SERCOM_I2CS_INTENSET_DRDY; - - /* Clear interrupt flags */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_AMATCH | - SERCOM_I2CS_INTFLAG_DRDY; - - /* Disable global interrupt for module */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); -#endif - - /* Wait for module to sync */ - _i2c_slave_wait_for_sync(module); - - /* Disable module */ - i2c_hw->CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; -} - -void i2c_slave_reset( - struct i2c_slave_module *const module); - -/** @} */ - -/** - * \name Read and Write - * @{ - */ - -enum status_code i2c_slave_write_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); -enum status_code i2c_slave_read_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); -enum i2c_slave_direction i2c_slave_get_direction_wait( - struct i2c_slave_module *const module); - -/** @} */ - -/** - * \name Status Management - * @{ - */ -uint32_t i2c_slave_get_status( - struct i2c_slave_module *const module); -void i2c_slave_clear_status( - struct i2c_slave_module *const module, - uint32_t status_flags); -/** @} */ - -#ifdef FEATURE_I2C_DMA_SUPPORT -/** - * \name SERCOM I2C Slave with DMA Interfaces - * @{ - */ - -/** - * \brief Read SERCOM I2C interrupt status. - * - * Read I2C interrupt status for DMA transfer. - * - * \param[in,out] module Pointer to the driver instance to lock - * - */ -static inline uint8_t i2c_slave_dma_read_interrupt_status(struct i2c_slave_module *const module) -{ - return (uint8_t)module->hw->I2CS.INTFLAG.reg; -} - -/** - * \brief Write SERCOM I2C interrupt status. - * - * Write I2C interrupt status for DMA transfer. - * - * \param[in,out] module Pointer to the driver instance to lock - * \param[in] flag Interrupt flag status - * - */ -static inline void i2c_slave_dma_write_interrupt_status(struct i2c_slave_module *const module, - uint8_t flag) -{ - module->hw->I2CS.INTFLAG.reg = flag; -} - -/** @} */ -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* I2C_SLAVE_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave_interrupt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave_interrupt.h deleted file mode 100644 index 76a6a89bb29..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave_interrupt.h +++ /dev/null @@ -1,215 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Slave Interrupt Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2C_SLAVE_INTERRUPT_H_INCLUDED -#define I2C_SLAVE_INTERRUPT_H_INCLUDED - -#include "i2c_slave.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_i2c_group - * @{ - * - */ - -/** - * \name Address Match Functionality - * @{ - */ - -void i2c_slave_enable_nack_on_address( - struct i2c_slave_module *const module); -void i2c_slave_disable_nack_on_address( - struct i2c_slave_module *const module); - -/** @} */ - -/** - * \name Callbacks - * @{ - */ -#if !defined(__DOXYGEN__) -void _i2c_slave_interrupt_handler(uint8_t instance); -#endif - -void i2c_slave_register_callback( - struct i2c_slave_module *const module, - i2c_slave_callback_t callback, - enum i2c_slave_callback callback_type); - -void i2c_slave_unregister_callback( - struct i2c_slave_module *const module, - enum i2c_slave_callback callback_type); - -/** - * \brief Enables callback - * - * Enables the callback specified by the callback_type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to enable - */ -static inline void i2c_slave_enable_callback( - struct i2c_slave_module *const module, - enum i2c_slave_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Mark callback as enabled */ - module->enabled_callback |= (1 << callback_type); - - /* Enable address callback */ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST || - callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST) { - i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } -} - -/** - * \brief Disables callback - * - * Disables the callback specified by the callback_type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to disable - */ -static inline void i2c_slave_disable_callback( - struct i2c_slave_module *const module, - enum i2c_slave_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Mark callback as disabled */ - module->enabled_callback &= ~(1 << callback_type); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST || - callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST || - module->status != STATUS_BUSY) { - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } -} - -/** @} */ - -/** - * \name Read and Write, Interrupt-Driven - * @{ - */ - - -enum status_code i2c_slave_read_packet_job( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); - -enum status_code i2c_slave_write_packet_job( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); - -/** - * \brief Cancels any currently ongoing operation - * - * Terminates the running transfer operation. - * - * \param[in,out] module Pointer to software module structure - */ -static inline void i2c_slave_cancel_job( - struct i2c_slave_module *const module) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - - /* Set buffer to 0. */ - module->buffer_remaining = 0; - module->buffer_length = 0; -} - -/** - * \brief Gets status of ongoing job - * - * Will return the status of the ongoing job, or the error that occurred - * in the last transfer operation. - * The status will be cleared when starting a new job. - * - * \param[in,out] module Pointer to software module structure - * - * \return Status of job. - * \retval STATUS_OK No error has occurred - * \retval STATUS_BUSY Transfer is in progress - * \retval STATUS_ERR_IO A collision, timeout or bus error happened in - * the last transfer - * \retval STATUS_ERR_TIMEOUT A timeout occurred - * \retval STATUS_ERR_OVERFLOW Data from master overflows receive buffer - */ -static inline enum status_code i2c_slave_get_job_status( - struct i2c_slave_module *const module) -{ - /* Check sanity. */ - Assert(module); - Assert(module->hw); - - /* Return current status code. */ - return module->status; -} - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* I2C_SLAVE_INTERRUPT_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.c deleted file mode 100644 index 699ca5b2a18..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.c +++ /dev/null @@ -1,296 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "sercom.h" - -#define SHIFT 32 -#define BAUD_INT_MAX 8192 -#define BAUD_FP_MAX 8 - -#if !defined(__DOXYGEN__) -/** - * \internal Configuration structure to save current gclk status. - */ -struct _sercom_conf { - /* Status of gclk generator initialization. */ - bool generator_is_set; - /* Sercom gclk generator used. */ - enum gclk_generator generator_source; -}; - -static struct _sercom_conf _sercom_config; - - -/** - * \internal Calculate 64 bit division, ref can be found in - * http://en.wikipedia.org/wiki/Division_algorithm#Long_division - */ -static uint64_t long_division(uint64_t n, uint64_t d) -{ - int32_t i; - uint64_t q = 0, r = 0, bit_shift; - for (i = 63; i >= 0; i--) { - bit_shift = (uint64_t)1 << i; - - r = r << 1; - - if (n & bit_shift) { - r |= 0x01; - } - - if (r >= d) { - r = r - d; - q |= bit_shift; - } - } - - return q; -} - -/** - * \internal Calculate synchronous baudrate value (SPI/UART) - */ -enum status_code _sercom_get_sync_baud_val( - const uint32_t baudrate, - const uint32_t external_clock, - uint16_t *const baudvalue) -{ - /* Baud value variable */ - uint16_t baud_calculated = 0; - uint32_t clock_value = external_clock; - - - /* Check if baudrate is outside of valid range. */ - if (baudrate > (external_clock / 2)) { - /* Return with error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - - /* Calculate BAUD value from clock frequency and baudrate */ - clock_value = external_clock / 2; - while (clock_value >= baudrate) { - clock_value = clock_value - baudrate; - baud_calculated++; - } - baud_calculated = baud_calculated - 1; - - /* Check if BAUD value is more than 255, which is maximum - * for synchronous mode */ - if (baud_calculated > 0xFF) { - /* Return with an error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } else { - *baudvalue = baud_calculated; - return STATUS_OK; - } -} - -/** - * \internal Calculate asynchronous baudrate value (UART) -*/ -enum status_code _sercom_get_async_baud_val( - const uint32_t baudrate, - const uint32_t peripheral_clock, - uint16_t *const baudval, - enum sercom_asynchronous_operation_mode mode, - enum sercom_asynchronous_sample_num sample_num) -{ - /* Temporary variables */ - uint64_t ratio = 0; - uint64_t scale = 0; - uint64_t baud_calculated = 0; - uint8_t baud_fp; - uint32_t baud_int = 0; - uint64_t temp1, temp2; - - /* Check if the baudrate is outside of valid range */ - if ((baudrate * sample_num) > peripheral_clock) { - /* Return with error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - - if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) { - /* Calculate the BAUD value */ - temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT); - ratio = long_division(temp1, peripheral_clock); - scale = ((uint64_t)1 << SHIFT) - ratio; - baud_calculated = (65536 * scale) >> SHIFT; - } else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) { - for(baud_fp = 0; baud_fp < BAUD_FP_MAX; baud_fp++) { - temp1 = BAUD_FP_MAX * (uint64_t)peripheral_clock; - temp2 = ((uint64_t)baudrate * sample_num); - baud_int = long_division(temp1, temp2); - baud_int -= baud_fp; - baud_int = baud_int / BAUD_FP_MAX; - if(baud_int < BAUD_INT_MAX) { - break; - } - } - if(baud_fp == BAUD_FP_MAX) { - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - baud_calculated = baud_int | (baud_fp << 13); - } - - *baudval = baud_calculated; - return STATUS_OK; -} -#endif - -/** - * \brief Set GCLK channel to generator. - * - * This will set the appropriate GCLK channel to the requested GCLK generator. - * This will set the generator for all SERCOM instances, and the user will thus - * only be able to set the same generator that has previously been set, if any. - * - * After the generator has been set the first time, the generator can be changed - * using the \c force_change flag. - * - * \param[in] generator_source The generator to use for SERCOM. - * \param[in] force_change Force change the generator. - * - * \return Status code indicating the GCLK generator change operation. - * \retval STATUS_OK If the generator update request was - * successful. - * \retval STATUS_ERR_ALREADY_INITIALIZED If a generator was already configured - * and the new configuration was not - * forced. - */ -enum status_code sercom_set_gclk_generator( - const enum gclk_generator generator_source, - const bool force_change) -{ - /* Check if valid option. */ - if (!_sercom_config.generator_is_set || force_change) { - /* Create and fill a GCLK configuration structure for the new config. */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = generator_source; - system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(SERCOM_GCLK_ID); - - /* Save config. */ - _sercom_config.generator_source = generator_source; - _sercom_config.generator_is_set = true; - - return STATUS_OK; - } else if (generator_source == _sercom_config.generator_source) { - /* Return status OK if same config. */ - return STATUS_OK; - } - - /* Return invalid config to already initialized GCLK. */ - return STATUS_ERR_ALREADY_INITIALIZED; -} - -/** \internal - * Creates a switch statement case entry to convert a SERCOM instance and pad - * index to the default SERCOM pad MUX setting. - */ -#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \ - case (uintptr_t)SERCOM##n: \ - switch (pad) { \ - case 0: \ - return SERCOM##n##_PAD0_DEFAULT; \ - case 1: \ - return SERCOM##n##_PAD1_DEFAULT; \ - case 2: \ - return SERCOM##n##_PAD2_DEFAULT; \ - case 3: \ - return SERCOM##n##_PAD3_DEFAULT; \ - } \ - break; - -/** - * \internal Gets the default PAD pinout for a given SERCOM. - * - * Returns the pinmux settings for the given SERCOM and pad. This is used - * for default configuration of pins. - * - * \param[in] sercom_module Pointer to the SERCOM module - * \param[in] pad PAD to get default pinout for - * - * \returns The default pinmux for the given SERCOM instance and PAD - * - */ -uint32_t _sercom_get_default_pad( - Sercom *const sercom_module, - const uint8_t pad) -{ - switch ((uintptr_t)sercom_module) { - /* Auto-generate a lookup table for the default SERCOM pad defaults */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad) - } - - Assert(false); - return 0; -} - -/** - * \internal - * Find index of given instance. - * - * \param[in] sercom_instance Instance pointer. - * - * \return Index of given instance. - */ -uint8_t _sercom_get_sercom_inst_index( - Sercom *const sercom_instance) -{ - /* Save all available SERCOM instances for compare. */ - Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS; - - /* Find index for sercom instance. */ - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.h deleted file mode 100644 index bfe0820f8a3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SERCOM_H_INCLUDED -#define SERCOM_H_INCLUDED - -#include -#include -#include -#include -#include "sercom_pinout.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if (SAMD10) || (SAMD11) - -#if (SERCOM0_GCLK_ID_SLOW == SERCOM1_GCLK_ID_SLOW && \ - SERCOM0_GCLK_ID_SLOW == SERCOM2_GCLK_ID_SLOW) -# define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW -#else -# error "SERCOM modules must share the same slow GCLK channel ID." -#endif - -#else - -#if (SERCOM0_GCLK_ID_SLOW == SERCOM1_GCLK_ID_SLOW && \ - SERCOM0_GCLK_ID_SLOW == SERCOM2_GCLK_ID_SLOW && \ - SERCOM0_GCLK_ID_SLOW == SERCOM3_GCLK_ID_SLOW) -# define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW -#else -# error "SERCOM modules must share the same slow GCLK channel ID." -#endif - -#endif - -#if (0x1ff >= REV_SERCOM) -# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1 -#elif (0x400 >= REV_SERCOM) -# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2 -#else -# error "Unknown SYNCBUSY scheme for this SERCOM revision" -#endif - -/** - * \brief sercom asynchronous operation mode - * - * Select sercom asynchronous operation mode - */ -enum sercom_asynchronous_operation_mode { - SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0, - SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL, -}; - -/** - * \brief sercom asynchronous samples per bit - * - * Select number of samples per bit - */ -enum sercom_asynchronous_sample_num { - SERCOM_ASYNC_SAMPLE_NUM_3 = 3, - SERCOM_ASYNC_SAMPLE_NUM_8 = 8, - SERCOM_ASYNC_SAMPLE_NUM_16 = 16, -}; - -enum status_code sercom_set_gclk_generator( - const enum gclk_generator generator_source, - const bool force_change); - -enum status_code _sercom_get_sync_baud_val( - const uint32_t baudrate, - const uint32_t external_clock, - uint16_t *const baudval); - -enum status_code _sercom_get_async_baud_val( - const uint32_t baudrate, - const uint32_t peripheral_clock, - uint16_t *const baudval, - enum sercom_asynchronous_operation_mode mode, - enum sercom_asynchronous_sample_num sample_num); - -uint32_t _sercom_get_default_pad( - Sercom *const sercom_module, - const uint8_t pad); - -uint8_t _sercom_get_sercom_inst_index( - Sercom *const sercom_instance); -#ifdef __cplusplus -} -#endif - -#endif //__SERCOM_H_INCLUDED diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.c deleted file mode 100644 index f682f1b4194..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.c +++ /dev/null @@ -1,140 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "sercom_interrupt.h" - -void *_sercom_instances[SERCOM_INST_NUM]; - -/** Save status of initialized handlers. */ -static bool _handler_table_initialized = false; - -/** Void pointers for saving device instance structures. */ -static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance); - -/** - * \internal - * Default interrupt handler. - * - * \param[in] instance SERCOM instance used. - */ -static void _sercom_default_handler( - const uint8_t instance) -{ - Assert(false); -} - -/** - * \internal - * Saves the given callback handler. - * - * \param[in] instance Instance index. - * \param[in] interrupt_handler Pointer to instance callback handler. - */ -void _sercom_set_handler( - const uint8_t instance, - const sercom_handler_t interrupt_handler) -{ - /* Initialize handlers with default handler and device instances with 0. */ - if (_handler_table_initialized == false) { - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - _sercom_interrupt_handlers[i] = &_sercom_default_handler; - _sercom_instances[i] = NULL; - } - - _handler_table_initialized = true; - } - - /* Save interrupt handler. */ - _sercom_interrupt_handlers[instance] = interrupt_handler; -} - - -/** \internal - * Converts a given SERCOM index to its interrupt vector index. - */ -#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_SERCOM##n, - -/** \internal - * Generates a SERCOM interrupt handler function for a given SERCOM index. - */ -#define _SERCOM_INTERRUPT_HANDLER(n, unused) \ - void SERCOM##n##_Handler(void) \ - { \ - _sercom_interrupt_handlers[n](n); \ - } - -/** - * \internal - * Returns the system interrupt vector. - * - * \param[in] sercom_instance Instance pointer - * - * \return Enum of system interrupt vector - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7 - */ -enum system_interrupt_vector _sercom_get_interrupt_vector( - Sercom *const sercom_instance) -{ - const uint8_t sercom_int_vectors[SERCOM_INST_NUM] = { - MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~) - }; - - /* Retrieve the index of the SERCOM being requested */ - uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance); - - /* Get the vector number from the lookup table for the requested SERCOM */ - return (enum system_interrupt_vector)sercom_int_vectors[instance_index]; -} - -/** Auto-generate a set of interrupt handlers for each SERCOM in the device */ -MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~) diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.h deleted file mode 100644 index 031dcd8112c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SERCOM_INTERRUPT_H_INCLUDED -#define SERCOM_INTERRUPT_H_INCLUDED - -#include "sercom.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Look-up table for device instances. */ -extern void *_sercom_instances[SERCOM_INST_NUM]; - -typedef void (*sercom_handler_t)(uint8_t instance); - -enum system_interrupt_vector _sercom_get_interrupt_vector( - Sercom *const sercom_instance); - -void _sercom_set_handler( - const uint8_t instance, - const sercom_handler_t interrupt_handler); - -#ifdef __cplusplus -} -#endif - -#endif /* SERCOM_INTERRUPT_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_pinout.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_pinout.h deleted file mode 100644 index 2c83eeeee3b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_pinout.h +++ /dev/null @@ -1,315 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM Module Pinout Definitions - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SERCOM_PINOUT_H_INCLUDED -#define SERCOM_PINOUT_H_INCLUDED - -#include - -#if SAMR21E -/* SERCOM0 */ -#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0 -#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1 -#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 -#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - -/* SERCOM1 */ -#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 -#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 -#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 -#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - -/* SERCOM2 */ -#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 -#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 -#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 -#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - -/* SERCOM3 */ -#define SERCOM3_PAD0_DEFAULT PINMUX_PA27F_SERCOM3_PAD0 -#define SERCOM3_PAD1_DEFAULT PINMUX_PA28F_SERCOM3_PAD1 -#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 -#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - -/* SERCOM4 */ -#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 -#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 -#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 -#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 - -/* SERCOM5 */ -#define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0 -#define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1 -#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 -#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - -#elif SAMR21G -/* SERCOM0 */ -#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 -#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 -#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 -#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - -/* SERCOM1 */ -#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 -#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 -#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 -#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - -/* SERCOM2 */ -#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 -#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 -#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 -#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - -/* SERCOM3 */ -#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 -#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 -#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 -#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 - -/* SERCOM4 */ -#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 -#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 -#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 -#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 - -/* SERCOM5 */ -#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 -#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 -#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 -#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - -#elif (SAMD10) || (SAMD11) -/* SERCOM0 */ -#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 -#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 -#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 -#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - -/* SERCOM1 */ -#define SERCOM1_PAD0_DEFAULT PINMUX_PA22C_SERCOM1_PAD0 -#define SERCOM1_PAD1_DEFAULT PINMUX_PA23C_SERCOM1_PAD1 -#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 -#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - -/* SERCOM2 */ -#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0 -#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1 -#define SERCOM2_PAD2_DEFAULT PINMUX_PA16D_SERCOM2_PAD2 -#define SERCOM2_PAD3_DEFAULT PINMUX_PA25D_SERCOM2_PAD3 - -#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L) - -/* SERCOM0 */ -#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 -#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 -#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 -#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - -/* SERCOM1 */ -#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 -#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 -#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 -#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - -/* SERCOM2 */ -#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 -#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 -#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 -#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - -/* SERCOM3 */ -#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0 -#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1 -#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 -#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - -#elif (SAMC20E) || (SAMC21E) -/* SERCOM0 */ -#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 -#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 -#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 -#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - -/* SERCOM1 */ -#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 -#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 -#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 -#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - -/* SERCOM2 */ -#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 -#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 -#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 -#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - -/* SERCOM3 */ -#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0 -#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1 -#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 -#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - -#elif (SAMC20G) || (SAMC21G) -/* SERCOM0 */ -#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 -#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 -#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 -#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - -/* SERCOM1 */ -#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 -#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 -#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 -#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - -/* SERCOM2 */ -#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 -#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 -#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 -#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - -/* SERCOM3 */ -#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0 -#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1 -#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 -#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - -#ifdef ID_SERCOM4 -/* SERCOM4 */ -#define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0 -#define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1 -#define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2 -#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3 -#endif - -#ifdef ID_SERCOM5 -/* SERCOM5 */ -#define SERCOM5_PAD0_DEFAULT PINMUX_PB02D_SERCOM5_PAD0 -#define SERCOM5_PAD1_DEFAULT PINMUX_PB03D_SERCOM5_PAD1 -#define SERCOM5_PAD2_DEFAULT PINMUX_PB22D_SERCOM5_PAD2 -#define SERCOM5_PAD3_DEFAULT PINMUX_PB23D_SERCOM5_PAD3 -#endif - -#elif (SAMC20J) || (SAMC21J) -/* SERCOM0 */ -#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 -#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 -#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 -#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - -/* SERCOM1 */ -#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 -#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 -#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 -#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - -/* SERCOM2 */ -#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 -#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 -#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 -#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - -/* SERCOM3 */ -#define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0 -#define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1 -#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 -#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - -#ifdef ID_SERCOM4 -/* SERCOM4 */ -#define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0 -#define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1 -#define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2 -#define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3 -#endif - -#ifdef ID_SERCOM5 -/* SERCOM5 */ -#define SERCOM5_PAD0_DEFAULT PINMUX_PB02D_SERCOM5_PAD0 -#define SERCOM5_PAD1_DEFAULT PINMUX_PB03D_SERCOM5_PAD1 -#define SERCOM5_PAD2_DEFAULT PINMUX_PB00D_SERCOM5_PAD2 -#define SERCOM5_PAD3_DEFAULT PINMUX_PB01D_SERCOM5_PAD3 -#endif - -#else -/* SERCOM0 */ -#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 -#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 -#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 -#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - -/* SERCOM1 */ -#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 -#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 -#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 -#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - -/* SERCOM2 */ -#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 -#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 -#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 -#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - -/* SERCOM3 */ -#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 -#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 -#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 -#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 - -/* SERCOM4 */ -#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0 -#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1 -#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 -#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 - -/* SERCOM5 */ -#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 -#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 -#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 -#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 -#endif - -#endif /* SERCOM_PINOUT_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.c deleted file mode 100644 index af4e570084c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.c +++ /dev/null @@ -1,752 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM USART Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "usart.h" -#include -#if USART_CALLBACK_MODE == true -# include "usart_interrupt.h" -#endif - -/** - * \internal - * Set Configuration of the USART module - */ -static enum status_code _usart_set_config( - struct usart_module *const module, - const struct usart_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Index for generic clock */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - - /* Cache new register values to minimize the number of register writes */ - uint32_t ctrla = 0; - uint32_t ctrlb = 0; - uint16_t baud = 0; - - enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - -#ifdef FEATURE_USART_OVER_SAMPLE - switch (config->sample_rate) { - case USART_SAMPLE_RATE_16X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - break; - case USART_SAMPLE_RATE_8X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_8; - break; - case USART_SAMPLE_RATE_3X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_3; - break; - case USART_SAMPLE_RATE_16X_FRACTIONAL: - mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - break; - case USART_SAMPLE_RATE_8X_FRACTIONAL: - mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_8; - break; - } -#endif - - /* Set data order, internal muxing, and clock polarity */ - ctrla = (uint32_t)config->data_order | - (uint32_t)config->mux_setting | -#ifdef FEATURE_USART_OVER_SAMPLE - config->sample_adjustment | - config->sample_rate | -#endif -#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - (config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) | -#endif - (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos); - - enum status_code status_code = STATUS_OK; - - /* Get baud value from mode and clock */ - switch (config->transfer_mode) { - case USART_TRANSFER_SYNCHRONOUSLY: - if (!config->use_external_clock) { - status_code = _sercom_get_sync_baud_val(config->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud); - } - - break; - - case USART_TRANSFER_ASYNCHRONOUSLY: - if (config->use_external_clock) { - status_code = - _sercom_get_async_baud_val(config->baudrate, - config->ext_clock_freq, &baud, mode, sample_num); - } else { - status_code = - _sercom_get_async_baud_val(config->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); - } - - break; - } - - /* Check if calculating the baudrate failed */ - if (status_code != STATUS_OK) { - /* Abort */ - return status_code; - } - -#ifdef FEATURE_USART_IRDA - if(config->encoding_format_enable) { - usart_hw->RXPL.reg = config->receive_pulse_length; - } -#endif - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /*Set baud val */ - usart_hw->BAUD.reg = baud; - - /* Set sample mode */ - ctrla |= config->transfer_mode; - - if (config->use_external_clock == false) { - ctrla |= SERCOM_USART_CTRLA_MODE(0x1); - } else { - ctrla |= SERCOM_USART_CTRLA_MODE(0x0); - } - - /* Set stopbits, character size and enable transceivers */ - ctrlb = (uint32_t)config->stopbits | (uint32_t)config->character_size | -#ifdef FEATURE_USART_IRDA - (config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) | -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - (config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) | -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - (config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) | -#endif - (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) | - (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos); - - /* Check parity mode bits */ - if (config->parity != USART_PARITY_NONE) { - ctrla |= SERCOM_USART_CTRLA_FORM(1); - ctrlb |= config->parity; - } else { -#ifdef FEATURE_USART_LIN_SLAVE - if(config->lin_slave_enable) { - ctrla |= SERCOM_USART_CTRLA_FORM(0x4); - } else { - ctrla |= SERCOM_USART_CTRLA_FORM(0); - } -#else - ctrla |= SERCOM_USART_CTRLA_FORM(0); -#endif - } - -#ifdef FEATURE_USART_LIN_MASTER - usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk) - | config->lin_header_delay - | config->lin_break_length; - - if (config->lin_node != LIN_INVALID_MODE) { - ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf)); - ctrla |= config->lin_node; - } -#endif - - /* Set whether module should run in standby. */ - if (config->run_in_standby || system_is_debugger_present()) { - ctrla |= SERCOM_USART_CTRLA_RUNSTDBY; - } - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Write configuration to CTRLB */ - usart_hw->CTRLB.reg = ctrlb; - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Write configuration to CTRLA */ - usart_hw->CTRLA.reg = ctrla; - -#ifdef FEATURE_USART_RS485 - usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7)); - usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time); -#endif - - return STATUS_OK; -} - -/** - * \brief Initializes the device - * - * Initializes the USART device based on the setting specified in the - * configuration struct. - * - * \param[out] module Pointer to USART device - * \param[in] hw Pointer to USART hardware instance - * \param[in] config Pointer to configuration struct - * - * \return Status of the initialization. - * - * \retval STATUS_OK The initialization was successful - * \retval STATUS_BUSY The USART module is busy - * resetting - * \retval STATUS_ERR_DENIED The USART have not been disabled in - * advance of initialization - * \retval STATUS_ERR_INVALID_ARG The configuration struct contains - * invalid configuration - * \retval STATUS_ERR_ALREADY_INITIALIZED The SERCOM instance has already been - * initialized with different clock - * configuration - * \retval STATUS_ERR_BAUD_UNAVAILABLE The BAUD rate given by the - * configuration - * struct cannot be reached with - * the current clock configuration - */ -enum status_code usart_init( - struct usart_module *const module, - Sercom *const hw, - const struct usart_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); - - enum status_code status_code = STATUS_OK; - - /* Assign module pointer to software instance struct */ - module->hw = hw; - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index, gclk_index; -#if (SAML21) || (SAMC20) || (SAMC21) -#if (SAML21) - if (sercom_index == 5) { - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#else - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) { - /* The module is busy resetting itself */ - return STATUS_BUSY; - } - - if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) { - /* Check the module is enabled */ - return STATUS_ERR_DENIED; - } - - /* Turn on module in PM */ -#if (SAML21) - if (sercom_index == 5) { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - - /* Set character size */ - module->character_size = config->character_size; - - /* Set transmitter and receiver status */ - module->receiver_enabled = config->receiver_enable; - module->transmitter_enabled = config->transmitter_enable; - -#ifdef FEATURE_USART_LIN_SLAVE - module->lin_slave_enabled = config->lin_slave_enable; -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - module->start_frame_detection_enabled = config->start_frame_detection_enable; -#endif - /* Set configuration according to the config struct */ - status_code = _usart_set_config(module, config); - if(status_code != STATUS_OK) { - return status_code; - } - - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - - uint32_t pad_pinmuxes[] = { - config->pinmux_pad0, config->pinmux_pad1, - config->pinmux_pad2, config->pinmux_pad3 - }; - - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pinmux = pad_pinmuxes[pad]; - - if (current_pinmux == PINMUX_DEFAULT) { - current_pinmux = _sercom_get_default_pad(hw, pad); - } - - if (current_pinmux != PINMUX_UNUSED) { - pin_conf.mux_position = current_pinmux & 0xFFFF; - system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); - } - } - -#if USART_CALLBACK_MODE == true - /* Initialize parameters */ - for (uint32_t i = 0; i < USART_CALLBACK_N; i++) { - module->callback[i] = NULL; - } - - module->tx_buffer_ptr = NULL; - module->rx_buffer_ptr = NULL; - module->remaining_tx_buffer_length = 0x0000; - module->remaining_rx_buffer_length = 0x0000; - module->callback_reg_mask = 0x00; - module->callback_enable_mask = 0x00; - module->rx_status = STATUS_OK; - module->tx_status = STATUS_OK; - - /* Set interrupt handler and register USART software module struct in - * look-up table */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - _sercom_set_handler(instance_index, _usart_interrupt_handler); - _sercom_instances[instance_index] = module; -#endif - - return status_code; -} - -/** - * \brief Transmit a character via the USART - * - * This blocking function will transmit a single character via the - * USART. - * - * \param[in] module Pointer to the software instance struct - * \param[in] tx_data Data to transfer - * - * \return Status of the operation. - * \retval STATUS_OK If the operation was completed - * \retval STATUS_BUSY If the operation was not completed, due to the USART - * module being busy - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_write_wait( - struct usart_module *const module, - const uint16_t tx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } - -#if USART_CALLBACK_MODE == true - /* Check if the USART is busy doing asynchronous operation. */ - if (module->remaining_tx_buffer_length > 0) { - return STATUS_BUSY; - } - -#else - /* Check if USART is ready for new data */ - if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) { - /* Return error code */ - return STATUS_BUSY; - } -#endif - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Write data to USART module */ - usart_hw->DATA.reg = tx_data; - - while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) { - /* Wait until data is sent */ - } - - return STATUS_OK; -} - -/** - * \brief Receive a character via the USART - * - * This blocking function will receive a character via the USART. - * - * \param[in] module Pointer to the software instance struct - * \param[out] rx_data Pointer to received data - * - * \return Status of the operation. - * \retval STATUS_OK If the operation was completed - * \retval STATUS_BUSY If the operation was not completed, - * due to the USART module being busy - * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed, - * due to configuration mismatch between USART - * and the sender - * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed, - * due to the baudrate being too low or the - * system frequency being too high - * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due to - * data being corrupted - * \retval STATUS_ERR_DENIED If the receiver is not enabled - */ -enum status_code usart_read_wait( - struct usart_module *const module, - uint16_t *const rx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Error variable */ - uint8_t error_code; - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - -#if USART_CALLBACK_MODE == true - /* Check if the USART is busy doing asynchronous operation. */ - if (module->remaining_rx_buffer_length > 0) { - return STATUS_BUSY; - } -#endif - - /* Check if USART has new data */ - if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) { - /* Return error code */ - return STATUS_BUSY; - } - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Read out the status code and mask away all but the 3 LSBs*/ - error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK); - - /* Check if an error has occurred during the receiving */ - if (error_code) { - /* Check which error occurred */ - if (error_code & SERCOM_USART_STATUS_FERR) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR; - - return STATUS_ERR_BAD_FORMAT; - } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - - return STATUS_ERR_OVERFLOW; - } else if (error_code & SERCOM_USART_STATUS_PERR) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR; - - return STATUS_ERR_BAD_DATA; - } -#ifdef FEATURE_USART_LIN_SLAVE - else if (error_code & SERCOM_USART_STATUS_ISF) { - /* Clear flag by writing 1 to it and - * return with an error code */ - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF; - - return STATUS_ERR_PROTOCOL; - } -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - else if (error_code & SERCOM_USART_STATUS_COLL) { - /* Clear flag by writing 1 to it - * return with an error code */ - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL; - - return STATUS_ERR_PACKET_COLLISION; - } -#endif - } - - /* Read data from USART module */ - *rx_data = usart_hw->DATA.reg; - - return STATUS_OK; -} - -/** - * \brief Transmit a buffer of characters via the USART - * - * This blocking function will transmit a block of \c length characters - * via the USART. - * - * \note Using this function in combination with the interrupt (\c _job) functions is - * not recommended as it has no functionality to check if there is an - * ongoing interrupt driven operation running or not. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] tx_data Pointer to data to transmit - * \param[in] length Number of characters to transmit - * - * \note If using 9-bit data, the array that *tx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it - * is an address pointer, the highest byte is not discarded. For example: - * \code - #define TX_LEN 3 - uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133}; - usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN); - \endcode - * - * \return Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid - * arguments - * \retval STATUS_ERR_TIMEOUT If operation was not completed, due to USART - * module timing out - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_write_buffer_wait( - struct usart_module *const module, - const uint8_t *tx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Check if the buffer length is valid */ - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - uint16_t tx_pos = 0; - - /* Blocks while buffer is being transferred */ - while (length--) { - /* Wait for the USART to be ready for new data and abort - * operation if it doesn't get ready within the timeout*/ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - - /* Data to send is at least 8 bits long */ - uint16_t data_to_send = tx_data[tx_pos++]; - - /* Check if the character size exceeds 8 bit */ - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - data_to_send |= (tx_data[tx_pos++] << 8); - } - - /* Send the data through the USART module */ - usart_write_wait(module, data_to_send); - } - - /* Wait until Transmit is complete or timeout */ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - - return STATUS_OK; -} - -/** - * \brief Receive a buffer of \c length characters via the USART - * - * This blocking function will receive a block of \c length characters - * via the USART. - * - * \note Using this function in combination with the interrupt (\c *_job) - * functions is not recommended as it has no functionality to check if - * there is an ongoing interrupt driven operation running or not. - * - * \param[in] module Pointer to USART software instance struct - * \param[out] rx_data Pointer to receive buffer - * \param[in] length Number of characters to receive - * - * \note If using 9-bit data, the array that *rx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it - * is an address pointer, the highest byte is not discarded. For example: - * \code - #define RX_LEN 3 - uint16_t rx_buf[RX_LEN] = {0x0,}; - usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN); - \endcode - * - * \return Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to an - * invalid argument being supplied - * \retval STATUS_ERR_TIMEOUT If operation was not completed, due - * to USART module timing out - * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed, - * due to a configuration mismatch - * between USART and the sender - * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed, - * due to the baudrate being too low or the - * system frequency being too high - * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due - * to data being corrupted - * \retval STATUS_ERR_DENIED If the receiver is not enabled - */ -enum status_code usart_read_buffer_wait( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Check if the buffer length is valid */ - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - uint16_t rx_pos = 0; - - /* Blocks while buffer is being received */ - while (length--) { - /* Wait for the USART to have new data and abort operation if it - * doesn't get ready within the timeout*/ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - - enum status_code retval; - uint16_t received_data = 0; - - retval = usart_read_wait(module, &received_data); - - if (retval != STATUS_OK) { - /* Overflow, abort */ - return retval; - } - - /* Read value will be at least 8-bits long */ - rx_data[rx_pos++] = received_data; - - /* If 9-bit data, write next received byte to the buffer */ - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - rx_data[rx_pos++] = (received_data >> 8); - } - } - - return STATUS_OK; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.h deleted file mode 100644 index 2908241f119..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.h +++ /dev/null @@ -1,1474 +0,0 @@ -/** - * - * \file - * - * \brief SAM SERCOM USART Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef USART_H_INCLUDED -#define USART_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_sercom_usart_group SAM Serial USART Driver (SERCOM USART) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of the SERCOM module in its USART mode to transfer or receive - * USART data frames. The following driver API modes are covered by this - * manual: - * - * - Polled APIs - * \if USART_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripherals are used by this module: - * - SERCOM (Serial Communication Interface) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_sercom_usart_prerequisites - * - \ref asfdoc_sam0_sercom_usart_overview - * - \ref asfdoc_sam0_sercom_usart_special_considerations - * - \ref asfdoc_sam0_sercom_usart_extra_info - * - \ref asfdoc_sam0_sercom_usart_examples - * - \ref asfdoc_sam0_sercom_usart_api_overview - * - * \section asfdoc_sam0_sercom_usart_prerequisites Prerequisites - * - * To use the USART you need to have a GCLK generator enabled and running - * that can be used as the SERCOM clock source. This can either be configured - * in conf_clocks.h or by using the system clock driver. - * - * \section asfdoc_sam0_sercom_usart_overview Module Overview - * - * This driver will use one (or more) SERCOM interfaces on the system - * and configure it to run as a USART interface in either synchronous - * or asynchronous mode. - * - * \subsection asfdoc_sam0_sercom_usart_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_USART_SYNC_SCHEME_V2SAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_USART_OVER_SAMPLESAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_USART_HARDWARE_FLOW_CONTROLSAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_USART_IRDASAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_USART_LIN_SLAVESAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_USART_COLLISION_DECTIONSAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_USART_START_FRAME_DECTIONSAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATIONSAM D21/R21/D10/D11/L21/DAx/C20/C21
FEATURE_USART_RS485SAM C20/C21
FEATURE_USART_LIN_MASTERSAM C20/C21
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_sercom_usart_overview_frame_format Frame Format - * - * Communication is based on frames, where the frame format can be customized - * to accommodate a wide range of standards. A frame consists of a start bit, - * a number of data bits, an optional parity bit for error detection as well - * as a configurable length stop bit(s) - see - * \ref asfdoc_sam0_sercom_usart_frame_diagram "the figure below". - * \ref asfdoc_sam0_sercom_usart_frame_params "The table below" shows the - * available parameters you can change in a frame. - * - * \anchor asfdoc_sam0_sercom_usart_frame_params - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
USART Frame Parameters
ParameterOptions
Start bit1
Data bits5, 6, 7, 8, 9
Parity bitNone, Even, Odd
Stop bits1, 2
- * - * \anchor asfdoc_sam0_sercom_usart_frame_diagram - * \image html usart_frame.svg "USART Frame Overview" width=100% - * - * \subsection asfdoc_sam0_sercom_usart_overview_sync Synchronous Mode - * - * In synchronous mode a dedicated clock line is provided; either by the USART - * itself if in master mode, or by an external master if in slave mode. - * Maximum transmission speed is the same as the GCLK clocking the USART - * peripheral when in slave mode, and the GCLK divided by two if in - * master mode. In synchronous mode the interface needs three lines to - * communicate: - * - TX (Transmit pin) - * - RX (Receive pin) - * - XCK (Clock pin) - * - * \subsubsection asfdoc_sam0_sercom_usart_overview_sync_sampling Data Sampling - * In synchronous mode the data is sampled on either the rising or falling edge - * of the clock signal. This is configured by setting the clock polarity in the - * configuration struct. - * - * \subsection asfdoc_sam0_sercom_usart_overview_async Asynchronous Mode - * - * In asynchronous mode no dedicated clock line is used, and the communication - * is based on matching the clock speed on the transmitter and receiver. The - * clock is generated from the internal SERCOM baudrate generator, and the - * frames are synchronized by using the frame start bits. Maximum transmission - * speed is limited to the SERCOM GCLK divided by 16. - * In asynchronous mode the interface only needs two lines to communicate: - * - TX (Transmit pin) - * - RX (Receive pin) - * - * \subsubsection asfdoc_sam0_sercom_usart_overview_async_clock_matching Transmitter/receiver Clock Matching - * - * For successful transmit and receive using the asynchronous mode the receiver - * and transmitter clocks needs to be closely matched. When receiving a frame - * that does not match the selected baudrate closely enough the receiver will - * be unable to synchronize the frame(s), and garbage transmissions will - * result. - * - * \subsection asfdoc_sam0_sercom_usart_parity Parity - * Parity can be enabled to detect if a transmission was in error. This is done - * by counting the number of "1" bits in the frame. When using Even parity the - * parity bit will be set if the total number of "1"s in the frame are an even - * number. If using Odd parity the parity bit will be set if the total number - * of "1"s are Odd. - * - * When receiving a character the receiver will count the number of "1"s in the - * frame and give an error if the received frame and parity bit disagree. - * - * \subsection asfdoc_sam0_sercom_usart_overview_pin_configuration GPIO Configuration - * - * The SERCOM module has four internal pads; the RX pin can be placed freely on - * any one of the four pads, and the TX and XCK pins have two predefined - * positions that can be selected as a pair. The pads can then be routed to an - * external GPIO pin using the normal pin multiplexing scheme on the SAM. - * - * \section asfdoc_sam0_sercom_usart_special_considerations Special Considerations - * - * \if USART_CALLBACK_MODE - * Never execute large portions of code in the callbacks. These - * are run from the interrupt routine, and thus having long callbacks will - * keep the processor in the interrupt handler for an equally long time. - * A common way to handle this is to use global flags signaling the - * main application that an interrupt event has happened, and only do the - * minimal needed processing in the callback. - * \else - * No special considerations. - * \endif - * - * \section asfdoc_sam0_sercom_usart_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_sercom_usart_extra. This includes: - * - \ref asfdoc_sam0_sercom_usart_extra_acronyms - * - \ref asfdoc_sam0_sercom_usart_extra_dependencies - * - \ref asfdoc_sam0_sercom_usart_extra_errata - * - \ref asfdoc_sam0_sercom_usart_extra_history - * - * \section asfdoc_sam0_sercom_usart_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_sercom_usart_exqsg. - * - * \section asfdoc_sam0_sercom_usart_api_overview API Overview - * @{ - */ - -#include -#include -#include - -#if USART_CALLBACK_MODE == true -# include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name Driver Feature Definition - * Define SERCOM USART features set according to different device family. - * @{ - */ -#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || \ - (SAMDA1) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** Usart sync scheme version 2. */ -# define FEATURE_USART_SYNC_SCHEME_V2 -/** Usart over sampling. */ -# define FEATURE_USART_OVER_SAMPLE -/** Usart hardware control flow. */ -# define FEATURE_USART_HARDWARE_FLOW_CONTROL -/** IrDA mode. */ -# define FEATURE_USART_IRDA -/** LIN slave mode. */ -# define FEATURE_USART_LIN_SLAVE -/** Usart collision detection. */ -# define FEATURE_USART_COLLISION_DECTION -/** Usart start frame detection. */ -# define FEATURE_USART_START_FRAME_DECTION -/** Usart start buffer overflow notification. */ -# define FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION -#endif - -#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** LIN master mode. */ -#define FEATURE_USART_LIN_MASTER -/** RS485 mode. */ -# define FEATURE_USART_RS485 -#endif -/*@}*/ - -#ifdef FEATURE_USART_LIN_MASTER -/** - * \brief LIN Node Type. - * - * LIN node type. - */ -enum lin_node_type { - /** LIN master mode */ - LIN_MASTER_NODE = SERCOM_USART_CTRLA_FORM(0x02), - /** LIN slave mode */ - LIN_SLAVE_NODE = SERCOM_USART_CTRLA_FORM(0x04), - /** Neither LIN master nor LIN slave mode */ - LIN_INVALID_MODE = SERCOM_USART_CTRLA_FORM(0x00), -}; - -/** - * \brief LIN Master Command Enum. - * - * LIN master command enum. - */ -enum lin_master_cmd { - /** LIN master software control transmission command */ - LIN_MASTER_SOFTWARE_CONTROL_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x01), - /** LIN master automatically transmission command */ - LIN_MASTER_AUTO_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x02), -}; - -/** - * \brief LIN Master Header Delay. - * - * LIN master header delay between break and sync transmission, - * and between the sync and identifier (ID) fields. - * This field is only valid when using automatically transmission command - */ -enum lin_master_header_delay { - /** Delay between break and sync transmission is 1 bit time. - Delay between sync and ID transmission is 1 bit time. */ - LIN_MASTER_HEADER_DELAY_0 = SERCOM_USART_CTRLC_HDRDLY(0x0), - /** Delay between break and sync transmission is 4 bit time. - Delay between sync and ID transmission is 4 bit time. */ - LIN_MASTER_HEADER_DELAY_1 = SERCOM_USART_CTRLC_HDRDLY(0x01), - /** Delay between break and sync transmission is 8 bit time. - Delay between sync and ID transmission is 4 bit time. */ - LIN_MASTER_HEADER_DELAY_2 = SERCOM_USART_CTRLC_HDRDLY(0x02), - /** Delay between break and sync transmission is 14 bit time. - Delay between sync and ID transmission is 4 bit time. */ - LIN_MASTER_HEADER_DELAY_3 = SERCOM_USART_CTRLC_HDRDLY(0x03), -}; - -/** - * \brief LIN Master Break Length. - * - * Length of the break field transmitted when in LIN master mode - */ -enum lin_master_break_length { - /** Break field transmission is 13 bit times. */ - LIN_MASTER_BREAK_LENGTH_13_BIT = SERCOM_USART_CTRLC_BRKLEN(0x0), - /** Break field transmission is 17 bit times. */ - LIN_MASTER_BREAK_LENGTH_17_BIT = SERCOM_USART_CTRLC_BRKLEN(0x1), - /** Break field transmission is 21 bit times. */ - LIN_MASTER_BREAK_LENGTH_21_BIT = SERCOM_USART_CTRLC_BRKLEN(0x2), - /** Break field transmission is 26 bit times. */ - LIN_MASTER_BREAK_LENGTH_26_BIT = SERCOM_USART_CTRLC_BRKLEN(0x3), -}; -#endif - -#ifndef PINMUX_DEFAULT -/** Default pinmux. */ -# define PINMUX_DEFAULT 0 -#endif - -#ifndef PINMUX_UNUSED -/** Unused pinmux. */ -# define PINMUX_UNUSED 0xFFFFFFFF -#endif - -#ifndef USART_TIMEOUT -/** USART timeout value. */ -# define USART_TIMEOUT 0xFFFF -#endif - -#if USART_CALLBACK_MODE == true -/** - * \brief USART Callback enum - * - * Callbacks for the Asynchronous USART driver. - */ -enum usart_callback { - /** Callback for buffer transmitted. */ - USART_CALLBACK_BUFFER_TRANSMITTED, - /** Callback for buffer received. */ - USART_CALLBACK_BUFFER_RECEIVED, - /** Callback for error. */ - USART_CALLBACK_ERROR, -#ifdef FEATURE_USART_LIN_SLAVE - /** Callback for break character is received. */ - USART_CALLBACK_BREAK_RECEIVED, -#endif -#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - /** Callback for a change is detected on the CTS pin. */ - USART_CALLBACK_CTS_INPUT_CHANGE, -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - /** Callback for a start condition is detected on the RxD line. */ - USART_CALLBACK_START_RECEIVED, -#endif -# if !defined(__DOXYGEN__) - /** Number of available callbacks. */ - USART_CALLBACK_N, -# endif -}; -#endif - -/** - * \brief USART Data Order enum - * - * The data order decides which of MSB or LSB is shifted out first when data is - * transferred. - */ -enum usart_dataorder { - /** The MSB will be shifted out first during transmission, - * and shifted in first during reception. */ - USART_DATAORDER_MSB = 0, - /** The LSB will be shifted out first during transmission, - * and shifted in first during reception. */ - USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD, -}; - -/** - * \brief USART Transfer mode enum - * - * Select USART transfer mode. - */ -enum usart_transfer_mode { - /** Transfer of data is done synchronously. */ - USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE), - /** Transfer of data is done asynchronously. */ - USART_TRANSFER_ASYNCHRONOUSLY = 0 -}; - -/** - * \brief USART Parity enum - * - * Select parity USART parity mode. - */ -enum usart_parity { - /** For odd parity checking, the parity bit will be set if number of - * ones being transferred is even. */ - USART_PARITY_ODD = SERCOM_USART_CTRLB_PMODE, - - /** For even parity checking, the parity bit will be set if number of - * ones being received is odd. */ - USART_PARITY_EVEN = 0, - - /** No parity checking will be executed, and there will be no parity bit - * in the received frame. */ - USART_PARITY_NONE = 0xFF, -}; - -/** - * \brief USART signal MUX settings - * - * Set the functionality of the SERCOM pins. - * - * See \ref asfdoc_sam0_sercom_usart_mux_settings for a description of the - * various MUX setting options. - */ -enum usart_signal_mux_settings { -#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - /** MUX setting RX_0_TX_0_XCK_1. */ - USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_0_TX_2_XCK_3. */ - USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3. */ - USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_1_TX_0_XCK_1. */ - USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_1_TX_2_XCK_3. */ - USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3. */ - USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_2_TX_0_XCK_1. */ - USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_2_TX_2_XCK_3. */ - USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3. */ - USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_3_TX_0_XCK_1. */ - USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_3_TX_2_XCK_3. */ - USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3. */ - USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)), -#ifdef FEATURE_USART_RS485 - /** MUX setting USART_RX_0_TX_0_XCK_1_TE_2. */ - USART_RX_0_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(3)), - /** MUX setting USART_RX_1_TX_0_XCK_1_TE_2. */ - USART_RX_1_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(3)), - /** MUX setting USART_RX_2_TX_0_XCK_1_TE_2. */ - USART_RX_2_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(3)), - /** MUX setting USART_RX_3_TX_0_XCK_1_TE_2. */ - USART_RX_3_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(3)), -#endif -#else - /** MUX setting RX_0_TX_0_XCK_1. */ - USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)), - /** MUX setting RX_0_TX_2_XCK_3. */ - USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_1_TX_0_XCK_1. */ - USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)), - /** MUX setting RX_1_TX_2_XCK_3. */ - USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_2_TX_0_XCK_1. */ - USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)), - /** MUX setting RX_2_TX_2_XCK_3. */ - USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_3_TX_0_XCK_1. */ - USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)), - /** MUX setting RX_3_TX_2_XCK_3. */ - USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO), -#endif -}; - -/** - * \brief USART Stop Bits enum - * - * Number of stop bits for a frame. - */ -enum usart_stopbits { - /** Each transferred frame contains one stop bit. */ - USART_STOPBITS_1 = 0, - /** Each transferred frame contains two stop bits. */ - USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE, -}; - -/** - * \brief USART Character Size - * - * Number of bits for the character sent in a frame. - */ -enum usart_character_size { - /** The char being sent in a frame is five bits long. */ - USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5), - /** The char being sent in a frame is six bits long. */ - USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6), - /** The char being sent in a frame is seven bits long. */ - USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7), - /** The char being sent in a frame is eight bits long. */ - USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0), - /** The char being sent in a frame is nine bits long. */ - USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1), -}; - -#ifdef FEATURE_USART_OVER_SAMPLE -/** - * \brief USART Sample Rate - * - * The value of sample rate and baudrate generation mode. - */ -enum usart_sample_rate { - /** 16x over-sampling using arithmetic baudrate generation. */ - USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0), - /** 16x over-sampling using fractional baudrate generation. */ - USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1), - /** 8x over-sampling using arithmetic baudrate generation. */ - USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2), - /** 8x over-sampling using fractional baudrate generation. */ - USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3), - /** 3x over-sampling using arithmetic baudrate generation. */ - USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4), -}; - -/** - * \brief USART Sample Adjustment - * - * The value of sample number used for majority voting. - */ -enum usart_sample_adjustment { - /** The first, middle and last sample number used for majority voting is 7-8-9. */ - USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0), - /** The first, middle and last sample number used for majority voting is 9-10-11. */ - USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1), - /** The first, middle and last sample number used for majority voting is 11-12-13. */ - USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2), - /** The first, middle and last sample number used for majority voting is 13-14-15. */ - USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3), -}; -#endif - -#ifdef FEATURE_USART_RS485 -/** - * \brief RS485 Guard Time - * - * The value of RS485 guard time. - */ -enum rs485_guard_time { - /** The guard time is 0-bit time. */ - RS485_GUARD_TIME_0_BIT = 0, - /** The guard time is 1-bit time. */ - RS485_GUARD_TIME_1_BIT, - /** The guard time is 2-bit times. */ - RS485_GUARD_TIME_2_BIT, - /** The guard time is 3-bit times. */ - RS485_GUARD_TIME_3_BIT, - /** The guard time is 4-bit times. */ - RS485_GUARD_TIME_4_BIT, - /** The guard time is 5-bit times. */ - RS485_GUARD_TIME_5_BIT, - /** The guard time is 6-bit times. */ - RS485_GUARD_TIME_6_BIT, - /** The guard time is 7-bit times. */ - RS485_GUARD_TIME_7_BIT, -}; -#endif - -/** - * \brief USART Transceiver - * - * Select Receiver or Transmitter. - */ -enum usart_transceiver_type { - /** The parameter is for the Receiver. */ - USART_TRANSCEIVER_RX, - /** The parameter is for the Transmitter. */ - USART_TRANSCEIVER_TX, -}; - -/** - * \brief USART configuration struct - * - * Configuration options for USART. - */ -struct usart_config { - /** USART bit order (MSB or LSB first). */ - enum usart_dataorder data_order; - /** USART in asynchronous or synchronous mode. */ - enum usart_transfer_mode transfer_mode; - /** USART parity. */ - enum usart_parity parity; - /** Number of stop bits. */ - enum usart_stopbits stopbits; - /** USART character size. */ - enum usart_character_size character_size; - /** USART pin out. */ - enum usart_signal_mux_settings mux_setting; -#ifdef FEATURE_USART_OVER_SAMPLE - /** USART sample rate. */ - enum usart_sample_rate sample_rate; - /** USART sample adjustment. */ - enum usart_sample_adjustment sample_adjustment; -#endif -#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - /** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs.*/ - bool immediate_buffer_overflow_notification; -#endif -#ifdef FEATURE_USART_IRDA - /** Enable IrDA encoding format. */ - bool encoding_format_enable; - /** The minimum pulse length that is required for a pulse to be accepted by the IrDA receiver. */ - uint8_t receive_pulse_length; -#endif -#ifdef FEATURE_USART_LIN_SLAVE - /** Enable LIN Slave Support. */ - bool lin_slave_enable; -#endif - -#ifdef FEATURE_USART_LIN_MASTER - /** LIN node type. */ - enum lin_node_type lin_node; - /** LIN master header delay. */ - enum lin_master_header_delay lin_header_delay; - /** LIN Master Break Length. */ - enum lin_master_break_length lin_break_length; -#endif - -#ifdef FEATURE_USART_START_FRAME_DECTION - /** Enable start of frame dection. */ - bool start_frame_detection_enable; -#endif -#ifdef FEATURE_USART_RS485 - /** RS485 guard time. */ - enum rs485_guard_time rs485_guard_time; -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - /** Enable collision dection. */ - bool collision_detection_enable; -#endif - /** USART baudrate. */ - uint32_t baudrate; - /** Enable receiver. */ - bool receiver_enable; - /** Enable transmitter. */ - bool transmitter_enable; - - /** USART Clock Polarity. - * If true, data changes on falling XCK edge and - * is sampled at rising edge. - * If false, data changes on rising XCK edge and - * is sampled at falling edge. - * */ - bool clock_polarity_inverted; - - /** States whether to use the external clock applied to the XCK pin. - * In synchronous mode the shift register will act directly on the XCK clock. - * In asynchronous mode the XCK will be the input to the USART hardware module. - */ - bool use_external_clock; - /** External clock frequency in synchronous mode. - * This must be set if \c use_external_clock is true. */ - uint32_t ext_clock_freq; - /** If true the USART will be kept running in Standby sleep mode. */ - bool run_in_standby; - /** GCLK generator source. */ - enum gclk_generator generator_source; - /** PAD0 pinmux. - * - * If current USARTx has several alternative multiplexing I/O pin for PAD0, then - * only one peripheral multiplexing I/O can be enabled for current USARTx PAD0 - * function. Make sure other alternative multiplexing I/O associated current - * USARTx PAD0 is not setup usart function. - */ - uint32_t pinmux_pad0; - /** PAD1 pinmux. - * - * If current USARTx has several alternative multiplexing I/O pin for PAD1, then - * only one peripheral multiplexing I/O can be enabled for current USARTx PAD1 - * function. Make sure other alternative multiplexing I/O associated current - * USARTx PAD1 is not setup usart function. - */ - uint32_t pinmux_pad1; - /** PAD2 pinmux. - * - * If current USARTx has several alternative multiplexing I/O pin for PAD2, then - * only one peripheral multiplexing I/O can be enabled for current USARTx PAD2 - * function. Make sure other alternative multiplexing I/O associated current - * USARTx PAD2 is not setup usart function. - */ - uint32_t pinmux_pad2; - /** PAD3 pinmux. - * - * If current USARTx has several alternative multiplexing I/O pin for PAD3, then - * only one peripheral multiplexing I/O can be enabled for current USARTx PAD3 - * function. Make sure other alternative multiplexing I/O associated current - * USARTx PAD3 is not setup usart function. - */ - uint32_t pinmux_pad3; -}; - -#if USART_CALLBACK_MODE == true -/** - * \brief USART module instance - * - * Forward Declaration for the device instance. - */ -struct usart_module; - -/** - * \brief USART callback type - * - * Type of the callback functions. - */ -typedef void (*usart_callback_t)(struct usart_module *const module); -#endif - -/** - * \brief SERCOM USART driver software device instance structure. - * - * SERCOM USART driver software instance structure, used to retain software - * state information of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct usart_module { -#if !defined(__DOXYGEN__) - /** Pointer to the hardware instance. */ - Sercom *hw; - /** Module lock. */ - volatile bool locked; - /** Character size of the data being transferred. */ - enum usart_character_size character_size; - /** Receiver enabled. */ - bool receiver_enabled; - /** Transmitter enabled. */ - bool transmitter_enabled; -#ifdef FEATURE_USART_LIN_SLAVE - /** LIN Slave Support enabled. */ - bool lin_slave_enabled; -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - /** Start of frame dection enabled. */ - bool start_frame_detection_enabled; -#endif -# if USART_CALLBACK_MODE == true - /** Array to store callback function pointers in. */ - usart_callback_t callback[USART_CALLBACK_N]; - /** Buffer pointer to where the next received character will be put. */ - volatile uint8_t *rx_buffer_ptr; - - /** Buffer pointer to where the next character will be transmitted from. - **/ - volatile uint8_t *tx_buffer_ptr; - /** Remaining characters to receive. */ - volatile uint16_t remaining_rx_buffer_length; - /** Remaining characters to transmit. */ - volatile uint16_t remaining_tx_buffer_length; - /** Bit mask for callbacks registered. */ - uint8_t callback_reg_mask; - /** Bit mask for callbacks enabled. */ - uint8_t callback_enable_mask; - /** Holds the status of the ongoing or last read operation. */ - volatile enum status_code rx_status; - /** Holds the status of the ongoing or last write operation. */ - volatile enum status_code tx_status; -# endif -#endif -}; - -/** -* \name Lock/Unlock -* @{ -*/ - -/** - * \brief Attempt to get lock on driver instance - * - * This function checks the instance's lock, which indicates whether or not it - * is currently in use, and sets the lock if it was not already set. - * - * The purpose of this is to enable exclusive access to driver instances, so - * that, e.g., transactions by different services will not interfere with each - * other. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline enum status_code usart_lock( - struct usart_module *const module) -{ - enum status_code status; - - system_interrupt_enter_critical_section(); - - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } - - system_interrupt_leave_critical_section(); - - return status; -} - -/** - * \brief Unlock driver instance - * - * This function clears the instance lock, indicating that it is available for - * use. - * - * \param[in,out] module Pointer to the driver instance to lock - * - */ -static inline void usart_unlock(struct usart_module *const module) -{ - module->locked = false; -} - -/** @} */ - -/** - * \brief Check if peripheral is busy syncing registers across clock domains - * - * Return peripheral synchronization status. If doing a non-blocking - * implementation this function can be used to check the sync state and hold of - * any new actions until sync is complete. If this functions is not run; the - * functions will block until the sync has completed. - * - * \param[in] module Pointer to peripheral module - * - * \return Peripheral sync status. - * - * \retval true Peripheral is busy syncing - * \retval false Peripheral is not busy syncing and can be read/written without - * stalling the bus. - */ -static inline bool usart_is_syncing( - const struct usart_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomUsart *const usart_hw = &(module->hw->USART); - -#ifdef FEATURE_USART_SYNC_SCHEME_V2 - return (usart_hw->SYNCBUSY.reg); -#else - return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY); -#endif -} - -#if !defined (__DOXYGEN__) -/** - * \internal - * Waits until synchronization is complete - */ -static inline void _usart_wait_for_sync( - const struct usart_module *const module) -{ - /* Sanity check. */ - Assert(module); - - while (usart_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } -} -#endif - -/** - * \brief Initializes the device to predefined defaults - * - * Initialize the USART device to predefined defaults: - * - 8-bit asynchronous USART - * - No parity - * - One stop bit - * - 9600 baud - * - Transmitter enabled - * - Receiver enabled - * - GCLK generator 0 as clock source - * - Default pin configuration - * - * The configuration struct will be updated with the default - * configuration. - * - * \param[in,out] config Pointer to configuration struct - */ -static inline void usart_get_config_defaults( - struct usart_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Set default config in the config struct */ - config->data_order = USART_DATAORDER_LSB; - config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY; - config->parity = USART_PARITY_NONE; - config->stopbits = USART_STOPBITS_1; - config->character_size = USART_CHARACTER_SIZE_8BIT; - config->baudrate = 9600; - config->receiver_enable = true; - config->transmitter_enable = true; - config->clock_polarity_inverted = false; - config->use_external_clock = false; - config->ext_clock_freq = 0; - config->mux_setting = USART_RX_1_TX_2_XCK_3; - config->run_in_standby = false; - config->generator_source = GCLK_GENERATOR_0; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->pinmux_pad2 = PINMUX_DEFAULT; - config->pinmux_pad3 = PINMUX_DEFAULT; -#ifdef FEATURE_USART_OVER_SAMPLE - config->sample_adjustment = USART_SAMPLE_ADJUSTMENT_7_8_9; - config->sample_rate = USART_SAMPLE_RATE_16X_ARITHMETIC; -#endif -#ifdef FEATURE_USART_LIN_SLAVE - config->lin_slave_enable = false; -#endif - -#ifdef FEATURE_USART_LIN_MASTER - config->lin_node = LIN_INVALID_MODE; - config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0; - config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT; -#endif - -#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - config->immediate_buffer_overflow_notification = false; -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - config->start_frame_detection_enable = false; -#endif -#ifdef FEATURE_USART_IRDA - config->encoding_format_enable = false; - config->receive_pulse_length = 19; -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - config->collision_detection_enable = false; -#endif -#ifdef FEATURE_USART_RS485 - config->rs485_guard_time = RS485_GUARD_TIME_0_BIT; -#endif -} - -enum status_code usart_init( - struct usart_module *const module, - Sercom *const hw, - const struct usart_config *const config); - -/** - * \brief Enable the module - * - * Enables the USART module. - * - * \param[in] module Pointer to USART software instance struct - */ -static inline void usart_enable( - const struct usart_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - -#if USART_CALLBACK_MODE == true - /* Enable Global interrupt for module */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); -#endif - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Enable USART module */ - usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; -} - -/** - * \brief Disable module - * - * Disables the USART module. - * - * \param[in] module Pointer to USART software instance struct - */ -static inline void usart_disable( - const struct usart_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - -#if USART_CALLBACK_MODE == true - /* Disable Global interrupt for module */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); -#endif - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Disable USART module */ - usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; -} - -/** - * \brief Resets the USART module - * - * Disables and resets the USART module. - * - * \param[in] module Pointer to the USART software instance struct - */ -static inline void usart_reset( - const struct usart_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - usart_disable(module); - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Reset module */ - usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST; -} - -/** - * \name Writing and Reading - * @{ - */ -enum status_code usart_write_wait( - struct usart_module *const module, - const uint16_t tx_data); - -enum status_code usart_read_wait( - struct usart_module *const module, - uint16_t *const rx_data); - -enum status_code usart_write_buffer_wait( - struct usart_module *const module, - const uint8_t *tx_data, - uint16_t length); - -enum status_code usart_read_buffer_wait( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); -/** @} */ - -/** - * \name Enabling/Disabling Receiver and Transmitter - * @{ - */ - -/** - * \brief Enable Transceiver - * - * Enable the given transceiver. Either RX or TX. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] transceiver_type Transceiver type - */ -static inline void usart_enable_transceiver( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - switch (transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Enable RX */ - usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; - module->receiver_enabled = true; - break; - - case USART_TRANSCEIVER_TX: - /* Enable TX */ - usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; - module->transmitter_enabled = true; - break; - } - _usart_wait_for_sync(module); -} - -/** - * \brief Disable Transceiver - * - * Disable the given transceiver (RX or TX). - * - * \param[in] module Pointer to USART software instance struct - * \param[in] transceiver_type Transceiver type - */ -static inline void usart_disable_transceiver( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - switch (transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Disable RX */ - usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; - module->receiver_enabled = false; - break; - - case USART_TRANSCEIVER_TX: - /* Disable TX */ - usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; - module->transmitter_enabled = false; - break; - } -} - -/** @} */ - -#ifdef FEATURE_USART_LIN_MASTER -/** - * \name LIN Master Command and Status - * @{ - */ - -/** - * \brief Sending LIN command. - * - * Sending LIN command. - * - * \param[in] module Pointer to USART software instance struct. - * \param[in] cmd Cammand type. - */ -static inline void lin_master_send_cmd( - struct usart_module *const module, - enum lin_master_cmd cmd) -{ - SercomUsart *const usart_hw = &(module->hw->USART); - _usart_wait_for_sync(module); - usart_hw->CTRLB.reg |= cmd; -} - -/** - * \brief Get LIN transmission status. - * - * Get LIN transmission status. - * - * \param[in] module Pointer to USART software instance struct. - * - * \return Status of LIN master transmission. - * \retval true Data transmission completed - * \retval false Transmission is ongoing - */ -static inline bool lin_master_transmission_status(struct usart_module *const module) -{ - SercomUsart *const usart_hw = &(module->hw->USART); - return ((usart_hw->STATUS.reg & SERCOM_USART_STATUS_TXE)? true:false); -} - -/** @} */ -#endif - -#ifdef __cplusplus -} -#endif - -/** @} */ - -/** -* \page asfdoc_sam0_sercom_usart_extra Extra Information for SERCOM USART Driver -* -* \section asfdoc_sam0_sercom_usart_extra_acronyms Acronyms -* -* Below is a table listing the acronyms used in this module, along with their -* intended meanings. -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
AcronymDescription
SERCOMSerial Communication Interface
USARTUniversal Synchronous and Asynchronous Serial Receiver and Transmitter
LSBLeast Significant Bit
MSBMost Significant Bit
DMADirect Memory Access
-* -* -* \section asfdoc_sam0_sercom_usart_extra_dependencies Dependencies -* This driver has the following dependencies: -* -* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" -* - \ref asfdoc_sam0_system_clock_group "System clock configuration" -* -* -* \section asfdoc_sam0_sercom_usart_extra_errata Errata -* There are no errata related to this driver. -* -* -* \section asfdoc_sam0_sercom_usart_extra_history Module History -* An overview of the module history is presented in the table below, with -* details on the enhancements and fixes made to the module since its first -* release. The current version of this corresponds to the newest version in -* the table. -* - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Added new feature as below: - * \li LIN master - * \li RS485 - *
Added new feature as below: - * \li Oversample - * \li Buffer overflow notification - * \li Irda - * \li Lin slave - * \li Start frame detection - * \li Hardware flow control - * \li Collision detection - * \li DMA support
\li Added new \c transmitter_enable and \c receiver_enable Boolean - * values to \c struct usart_config - * \li Altered \c usart_write_* and usart_read_* functions to abort with - * an error code if the relevant transceiver is not enabled - * \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait() - * not aborting correctly when a timeout condition occurs
Initial Release
-*/ - -/** - * \page asfdoc_sam0_sercom_usart_exqsg Examples for SERCOM USART Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_sercom_usart_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_sercom_usart_basic_use_case - * \if USART_CALLBACK_MODE - * - \subpage asfdoc_sam0_sercom_usart_callback_use_case - * \endif - * - \subpage asfdoc_sam0_sercom_usart_dma_use_case - * - \subpage asfdoc_sam0_sercom_usart_lin_use_case - */ - -/** - * \page asfdoc_sam0_sercom_usart_mux_settings SERCOM USART MUX Settings - * - * The following lists the possible internal SERCOM module pad function - * assignments, for the four SERCOM pads when in USART mode. Note that this is - * in addition to the physical GPIO pin MUX of the device, and can be used in - * conjunction to optimize the serial data pin-out. - * - * When TX and RX are connected to the same pin, the USART will operate in - * half-duplex mode if both the transmitter and receivers are enabled. - * - * \note When RX and XCK are connected to the same pin, the receiver must not - * be enabled if the USART is configured to use an external clock. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
MUX/PadPAD 0PAD 1PAD 2PAD 3
RX_0_TX_0_XCK_1TX / RXXCK--
RX_0_TX_2_XCK_3RX-TXXCK
RX_1_TX_0_XCK_1TXRX / XCK--
RX_1_TX_2_XCK_3-RXTXXCK
RX_2_TX_0_XCK_1TXXCKRX-
RX_2_TX_2_XCK_3--TX / RXXCK
RX_3_TX_0_XCK_1TXXCK-RX
RX_3_TX_2_XCK_3--TXRX / XCK
- * - * \page asfdoc_sam0_sercom_usart_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42118F06/2015Add support for SAML21, SAMDAx, and SAMC20/C21.
42118E12/2014Add support for SAMR21 and SAMD10/D11.
42118D01/2014Add support for SAMD21.
42118C10/2013Replaced the pad multiplexing documentation with a condensed table.
42118B06/2013Corrected documentation typos.
42118A06/2013Initial release
- */ -#endif /* USART_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.c deleted file mode 100644 index 5d429e473cb..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.c +++ /dev/null @@ -1,668 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM USART Asynchronous Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "usart_interrupt.h" - -/** - * \internal - * Asynchronous write of a buffer with a given length - * - * \param[in] module Pointer to USART software instance struct - * \param[in] tx_data Pointer to data to be transmitted - * \param[in] length Length of data buffer - * - */ -enum status_code _usart_write_buffer( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(tx_data); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - system_interrupt_enter_critical_section(); - - /* Check if the USART transmitter is busy */ - if (module->remaining_tx_buffer_length > 0) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } - - /* Write parameters to the device instance */ - module->remaining_tx_buffer_length = length; - - system_interrupt_leave_critical_section(); - - module->tx_buffer_ptr = tx_data; - module->tx_status = STATUS_BUSY; - - /* Enable the Data Register Empty Interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE; - - return STATUS_OK; -} - -/** - * \internal - * Asynchronous read of a buffer with a given length - * - * \param[in] module Pointer to USART software instance struct - * \param[in] rx_data Pointer to data to be received - * \param[in] length Length of data buffer - * - */ -enum status_code _usart_read_buffer( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(rx_data); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - system_interrupt_enter_critical_section(); - - /* Check if the USART receiver is busy */ - if (module->remaining_rx_buffer_length > 0) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } - - /* Set length for the buffer and the pointer, and let - * the interrupt handler do the rest */ - module->remaining_rx_buffer_length = length; - - system_interrupt_leave_critical_section(); - - module->rx_buffer_ptr = rx_data; - module->rx_status = STATUS_BUSY; - - /* Enable the RX Complete Interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC; - -#ifdef FEATURE_USART_LIN_SLAVE - /* Enable the break character is received Interrupt */ - if(module->lin_slave_enabled) { - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK; - } -#endif - -#ifdef FEATURE_USART_START_FRAME_DECTION - /* Enable a start condition is detected Interrupt */ - if(module->start_frame_detection_enabled) { - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS; - } -#endif - - return STATUS_OK; -} - -/** - * \brief Registers a callback - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref usart_enable_callback, - * in order for the interrupt handler to call it when the conditions for - * the callback type are met. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] callback_func Pointer to callback function - * \param[in] callback_type Callback type given by an enum - * - */ -void usart_register_callback( - struct usart_module *const module, - usart_callback_t callback_func, - enum usart_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); - - /* Register callback function */ - module->callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module->callback_reg_mask |= (1 << callback_type); -} - -/** - * \brief Unregisters a callback - * - * Unregisters a callback function which is implemented by the user. - * - * \param[in,out] module Pointer to USART software instance struct - * \param[in] callback_type Callback type given by an enum - * - */ -void usart_unregister_callback( - struct usart_module *const module, - enum usart_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Unregister callback function */ - module->callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module->callback_reg_mask &= ~(1 << callback_type); -} - -/** - * \brief Asynchronous write a data - * - * Sets up the driver to write the data given. If registered and enabled, - * a callback function will be called when the transmit is completed. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] tx_data Data to transfer - * - * \returns Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_BUSY If operation was not completed, due to the - * USART module being busy - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_write_job( - struct usart_module *const module, - const uint16_t *tx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(tx_data); - - - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Call internal write buffer function with length 1 */ - return _usart_write_buffer(module, (uint8_t *)tx_data, 1); -} - -/** - * \brief Asynchronous read a data - * - * Sets up the driver to read data from the USART module to the data - * pointer given. If registered and enabled, a callback will be called - * when the receiving is completed. - * - * \param[in] module Pointer to USART software instance struct - * \param[out] rx_data Pointer to where received data should be put - * - * \returns Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_BUSY If operation was not completed - */ -enum status_code usart_read_job( - struct usart_module *const module, - uint16_t *const rx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(rx_data); - - /* Call internal read buffer function with length 1 */ - return _usart_read_buffer(module, (uint8_t *)rx_data, 1); -} - -/** - * \brief Asynchronous buffer write - * - * Sets up the driver to write a given buffer over the USART. If registered and - * enabled, a callback function will be called. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] tx_data Pointer do data buffer to transmit - * \param[in] length Length of the data to transmit - * - * \note If using 9-bit data, the array that *tx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it - * is an address pointer, the highest byte is not discarded. For example: - * \code - #define TX_LEN 3 - uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133}; - usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN); - \endcode - * - * \returns Status of the operation. - * \retval STATUS_OK If operation was completed successfully. - * \retval STATUS_BUSY If operation was not completed, due to the - * USART module being busy - * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid - * arguments - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_write_buffer_job( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(tx_data); - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that the receiver is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Issue internal asynchronous write */ - return _usart_write_buffer(module, tx_data, length); -} - -/** - * \brief Asynchronous buffer read - * - * Sets up the driver to read from the USART to a given buffer. If registered - * and enabled, a callback function will be called. - * - * \param[in] module Pointer to USART software instance struct - * \param[out] rx_data Pointer to data buffer to receive - * \param[in] length Data buffer length - * - * \note If using 9-bit data, the array that *rx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it - * is an address pointer, the highest byte is not discarded. For example: - * \code - #define RX_LEN 3 - uint16_t rx_buf[RX_LEN] = {0x0,}; - usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN); - \endcode - * - * \returns Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_BUSY If operation was not completed, due to the - * USART module being busy - * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid - * arguments - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_read_buffer_job( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(rx_data); - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Issue internal asynchronous read */ - return _usart_read_buffer(module, rx_data, length); -} - -/** - * \brief Cancels ongoing read/write operation - * - * Cancels the ongoing read/write operation modifying parameters in the - * USART software struct. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] transceiver_type Transfer type to cancel - */ -void usart_abort_job( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - switch(transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Clear the interrupt flag in order to prevent the receive - * complete callback to fire */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; - - /* Clear the software reception buffer */ - module->remaining_rx_buffer_length = 0; - - break; - - case USART_TRANSCEIVER_TX: - /* Clear the interrupt flag in order to prevent the receive - * complete callback to fire */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; - - /* Clear the software reception buffer */ - module->remaining_tx_buffer_length = 0; - - break; - } -} - -/** - * \brief Get status from the ongoing or last asynchronous transfer operation - * - * Returns the error from a given ongoing or last asynchronous transfer operation. - * Either from a read or write transfer. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] transceiver_type Transfer type to check - * - * \return Status of the given job. - * \retval STATUS_OK No error occurred during the last transfer - * \retval STATUS_BUSY A transfer is ongoing - * \retval STATUS_ERR_BAD_DATA The last operation was aborted due to a - * parity error. The transfer could be affected - * by external noise - * \retval STATUS_ERR_BAD_FORMAT The last operation was aborted due to a - * frame error - * \retval STATUS_ERR_OVERFLOW The last operation was aborted due to a - * buffer overflow - * \retval STATUS_ERR_INVALID_ARG An invalid transceiver enum given - */ -enum status_code usart_get_job_status( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Variable for status code */ - enum status_code status_code; - - switch(transceiver_type) { - case USART_TRANSCEIVER_RX: - status_code = module->rx_status; - break; - - case USART_TRANSCEIVER_TX: - status_code = module->tx_status; - break; - - default: - status_code = STATUS_ERR_INVALID_ARG; - break; - } - - return status_code; -} - -/** - * \internal - * Handles interrupts as they occur, and it will run callback functions - * which are registered and enabled. - * - * \param[in] instance ID of the SERCOM instance calling the interrupt - * handler. - */ -void _usart_interrupt_handler( - uint8_t instance) -{ - /* Temporary variables */ - uint16_t interrupt_status; - uint16_t callback_status; - uint8_t error_code; - - - /* Get device instance from the look-up table */ - struct usart_module *module - = (struct usart_module *)_sercom_instances[instance]; - - /* Pointer to the hardware module instance */ - SercomUsart *const usart_hw - = &(module->hw->USART); - - /* Wait for the synchronization to complete */ - _usart_wait_for_sync(module); - - /* Read and mask interrupt flag register */ - interrupt_status = usart_hw->INTFLAG.reg; - interrupt_status &= usart_hw->INTENSET.reg; - callback_status = module->callback_reg_mask & - module->callback_enable_mask; - - /* Check if a DATA READY interrupt has occurred, - * and if there is more to transfer */ - if (interrupt_status & SERCOM_USART_INTFLAG_DRE) { - if (module->remaining_tx_buffer_length) { - /* Write value will be at least 8-bits long */ - uint16_t data_to_send = *(module->tx_buffer_ptr); - /* Increment 8-bit pointer */ - (module->tx_buffer_ptr)++; - - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - data_to_send |= (*(module->tx_buffer_ptr) << 8); - /* Increment 8-bit pointer */ - (module->tx_buffer_ptr)++; - } - /* Write the data to send */ - usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK); - - if (--(module->remaining_tx_buffer_length) == 0) { - /* Disable the Data Register Empty Interrupt */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - /* Enable Transmission Complete interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC; - - } - } else { - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - } - - /* Check if the Transmission Complete interrupt has occurred and - * that the transmit buffer is empty */ - } - - if (interrupt_status & SERCOM_USART_INTFLAG_TXC) { - - /* Disable TX Complete Interrupt, and set STATUS_OK */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; - module->tx_status = STATUS_OK; - - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) { - (*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module); - } - - /* Check if the Receive Complete interrupt has occurred, and that - * there's more data to receive */ - } - - if (interrupt_status & SERCOM_USART_INTFLAG_RXC) { - - if (module->remaining_rx_buffer_length) { - /* Read out the status code and mask away all but the 4 LSBs*/ - error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK); -#if !SAMD20 - /* CTS status should not be considered as an error */ - if(error_code & SERCOM_USART_STATUS_CTS) { - error_code &= ~SERCOM_USART_STATUS_CTS; - } -#endif -#ifdef FEATURE_USART_LIN_MASTER - /* TXE status should not be considered as an error */ - if(error_code & SERCOM_USART_STATUS_TXE) { - error_code &= ~SERCOM_USART_STATUS_TXE; - } -#endif - /* Check if an error has occurred during the receiving */ - if (error_code) { - /* Check which error occurred */ - if (error_code & SERCOM_USART_STATUS_FERR) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_BAD_FORMAT; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_FERR; - } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_OVERFLOW; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF; - } else if (error_code & SERCOM_USART_STATUS_PERR) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_BAD_DATA; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_PERR; - } -#ifdef FEATURE_USART_LIN_SLAVE - else if (error_code & SERCOM_USART_STATUS_ISF) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_PROTOCOL; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF; - } -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - else if (error_code & SERCOM_USART_STATUS_COLL) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_PACKET_COLLISION; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL; - } -#endif - - /* Run callback if registered and enabled */ - if (callback_status - & (1 << USART_CALLBACK_ERROR)) { - (*(module->callback[USART_CALLBACK_ERROR]))(module); - } - - } else { - - /* Read current packet from DATA register, - * increment buffer pointer and decrement buffer length */ - uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK); - - /* Read value will be at least 8-bits long */ - *(module->rx_buffer_ptr) = received_data; - /* Increment 8-bit pointer */ - module->rx_buffer_ptr += 1; - - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - /* 9-bit data, write next received byte to the buffer */ - *(module->rx_buffer_ptr) = (received_data >> 8); - /* Increment 8-bit pointer */ - module->rx_buffer_ptr += 1; - } - - /* Check if the last character have been received */ - if(--(module->remaining_rx_buffer_length) == 0) { - /* Disable RX Complete Interrupt, - * and set STATUS_OK */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; - module->rx_status = STATUS_OK; - - /* Run callback if registered and enabled */ - if (callback_status - & (1 << USART_CALLBACK_BUFFER_RECEIVED)) { - (*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module); - } - } - } - } else { - /* This should not happen. Disable Receive Complete interrupt. */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; - } - } - -#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; - - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) { - (*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module); - } - } -#endif - -#ifdef FEATURE_USART_LIN_SLAVE - if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; - - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) { - (*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module); - } - } -#endif - -#ifdef FEATURE_USART_START_FRAME_DECTION - if (interrupt_status & SERCOM_USART_INTFLAG_RXS) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; - - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) { - (*(module->callback[USART_CALLBACK_START_RECEIVED]))(module); - } - } -#endif -} - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.h deleted file mode 100644 index 199d036a758..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.h +++ /dev/null @@ -1,177 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM USART Asynchronous Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef USART_INTERRUPT_H_INCLUDED -#define USART_INTERRUPT_H_INCLUDED - -#include "usart.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__DOXYGEN__) -enum status_code _usart_write_buffer( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length); - -enum status_code _usart_read_buffer( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); - -void _usart_interrupt_handler( - uint8_t instance); -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_usart_group - * - * @{ - */ - -/** - * \name Callback Management - * @{ - */ -void usart_register_callback( - struct usart_module *const module, - usart_callback_t callback_func, - enum usart_callback callback_type); - -void usart_unregister_callback( - struct usart_module *module, - enum usart_callback callback_type); - -/** - * \brief Enables callback - * - * Enables the callback function registered by the \ref usart_register_callback. - * The callback function will be called from the interrupt handler when the - * conditions for the callback type are met. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void usart_enable_callback( - struct usart_module *const module, - enum usart_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Enable callback */ - module->callback_enable_mask |= (1 << callback_type); - -} - -/** - * \brief Disable callback - * - * Disables the callback function registered by the \ref usart_register_callback, - * and the callback will not be called from the interrupt routine. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void usart_disable_callback( - struct usart_module *const module, - enum usart_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Disable callback */ - module->callback_enable_mask &= ~(1 << callback_type); -} - -/** - * @} - */ - -/** - * \name Writing and Reading - * @{ - */ -enum status_code usart_write_job( - struct usart_module *const module, - const uint16_t *tx_data); - -enum status_code usart_read_job( - struct usart_module *const module, - uint16_t *const rx_data); - -enum status_code usart_write_buffer_job( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length); - -enum status_code usart_read_buffer_job( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); - -void usart_abort_job( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type); - -enum status_code usart_get_job_status( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type); -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* USART_INTERRUPT_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/delay.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/delay.h deleted file mode 100644 index a838807aae7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/delay.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef DELAY_H_INCLUDED -#define DELAY_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup group_common_services_delay Busy-Wait Delay Routines - * - * This module provides simple loop-based delay routines for those - * applications requiring a brief wait during execution. Common for - * API ver. 2. - * - * @{ - */ -#include -#include - -// TEMP: Added by V -#include "sam0/systick_counter.h" -#ifdef SYSTICK_MODE -#include "sam0/systick_counter.h" -#endif -#ifdef CYCLE_MODE -#include "sam0/cycle_counter.h" -#endif - -void delay_init(void); - -/** - * \def delay_s - * \brief Delay in at least specified number of seconds. - * \param delay Delay in seconds - */ -#define delay_s(delay) cpu_delay_s(delay) - -/** - * \def delay_ms - * \brief Delay in at least specified number of milliseconds. - * \param delay Delay in milliseconds - */ -#define delay_ms(delay) cpu_delay_ms(delay) - -/** - * \def delay_us - * \brief Delay in at least specified number of microseconds. - * \param delay Delay in microseconds - */ -#define delay_us(delay) cpu_delay_us(delay) - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* DELAY_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.c deleted file mode 100644 index 3fa8f8d4def..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.c +++ /dev/null @@ -1,50 +0,0 @@ -#include "delay.h" - -/** - * Value used to calculate ms delay. Default to be used with a 8MHz clock; - */ -static uint32_t cycles_per_ms = 8000000UL / 1000; -static uint32_t cycles_per_us = 8000000UL / 1000000; - -/** - * \brief Initialize the delay driver. - * - * This must be called during start up to initialize the delay routine with - * the current used main clock. It must run any time the main CPU clock is changed. - */ -void delay_init(void) -{ - cycles_per_ms = system_gclk_gen_get_hz(0); - cycles_per_ms /= 1000; - cycles_per_us = cycles_per_ms / 1000; - - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; -} - -/** - * \brief Delay loop to delay at least n number of microseconds - * - * \param n Number of microseconds to wait - */ -void delay_cycles_us( - uint32_t n) -{ - while (n--) { - /* Devide up to blocks of 10u */ - delay_cycles(cycles_per_us); - } -} - -/** - * \brief Delay loop to delay at least n number of milliseconds - * - * \param n Number of milliseconds to wait - */ -void delay_cycles_ms( - uint32_t n) -{ - while (n--) { - /* Devide up to blocks of 1ms */ - delay_cycles(cycles_per_ms); - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.h deleted file mode 100644 index 39fc84006aa..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef CYCLE_COUNTER_H_INCLUDED -#define CYCLE_COUNTER_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name Convenience functions for busy-wait delay loops - * - * @{ - */ - -/** - * \brief Delay loop to delay n number of cycles - * Delay program execution for at least the specified number of CPU cycles. - * - * \param n Number of cycles to delay - */ -static inline void delay_cycles( - const uint32_t n) -{ - if (n > 0) { - SysTick->LOAD = n; - SysTick->VAL = 0; - - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) { - }; - } -} - -void delay_cycles_us(uint32_t n); - -void delay_cycles_ms(uint32_t n); - -/** - * \brief Delay program execution for at least the specified number of microseconds. - * - * \param delay number of microseconds to wait - */ -#define cpu_delay_us(delay) delay_cycles_us(delay) - -/** - * \brief Delay program execution for at least the specified number of milliseconds. - * - * \param delay number of milliseconds to wait - */ -#define cpu_delay_ms(delay) delay_cycles_ms(delay) - -/** - * \brief Delay program execution for at least the specified number of seconds. - * - * \param delay number of seconds to wait - */ -#define cpu_delay_s(delay) delay_cycles_ms(1000 * delay) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* CYCLE_COUNTER_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock.c deleted file mode 100644 index d062f367f40..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock.c +++ /dev/null @@ -1,1020 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Clock Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include - -#ifndef SYSCTRL_FUSES_OSC32K_ADDR -#if (SAMR21) || (SAMD) -# define SYSCTRL_FUSES_OSC32K_ADDR FUSES_OSC32K_CAL_ADDR -# define SYSCTRL_FUSES_OSC32K_Pos FUSES_OSC32K_CAL_Pos -#elif (SAML21) -# define SYSCTRL_FUSES_OSC32K_ADDR NVMCTRL_OTP4 -# define SYSCTRL_FUSES_OSC32K_Pos 6 - -#else -# define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR -# define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos -#endif -#endif - -/** - * \internal - * \brief DFLL-specific data container. - */ -struct _system_clock_dfll_config { - uint32_t control; - uint32_t val; - uint32_t mul; -}; - -/** - * \internal - * \brief DPLL-specific data container. - */ -struct _system_clock_dpll_config { - uint32_t frequency; -}; - - -/** - * \internal - * \brief XOSC-specific data container. - */ -struct _system_clock_xosc_config { - uint32_t frequency; -}; - -/** - * \internal - * \brief System clock module data container. - */ -struct _system_clock_module { - volatile struct _system_clock_dfll_config dfll; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - volatile struct _system_clock_dpll_config dpll; -#endif - - volatile struct _system_clock_xosc_config xosc; - volatile struct _system_clock_xosc_config xosc32k; -}; - -/** - * \internal - * \brief Internal module instance to cache configuration values. - */ -static struct _system_clock_module _system_clock_inst = { - .dfll = { - .control = 0, - .val = 0, - .mul = 0, - }, - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - .dpll = { - .frequency = 0, - }, -#endif - .xosc = { - .frequency = 0, - }, - .xosc32k = { - .frequency = 0, - }, -}; - -/** - * \internal - * \brief Wait for sync to the DFLL control registers. - */ -static inline void _system_dfll_wait_for_sync(void) -{ - while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) { - /* Wait for DFLL sync */ - } -} - -/** - * \internal - * \brief Wait for sync to the OSC32K control registers. - */ -static inline void _system_osc32k_wait_for_sync(void) -{ - while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) { - /* Wait for OSC32K sync */ - } -} - -static inline void _system_clock_source_dfll_set_config_errata_9905(void) -{ - - /* Disable ONDEMAND mode while writing configurations */ - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND; - _system_dfll_wait_for_sync(); - - SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; - SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; - - /* Write full configuration to DFLL control register */ - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; -} - -/** - * \brief Retrieve the frequency of a clock source. - * - * Determines the current operating frequency of a given clock source. - * - * \param[in] clock_source Clock source to get the frequency - * - * \returns Frequency of the given clock source, in Hz. - */ -uint32_t system_clock_source_get_hz( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_XOSC: - return _system_clock_inst.xosc.frequency; - - case SYSTEM_CLOCK_SOURCE_OSC8M: - return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - return 32768UL; - - case SYSTEM_CLOCK_SOURCE_ULP32K: - return 32768UL; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - return _system_clock_inst.xosc32k.frequency; - - case SYSTEM_CLOCK_SOURCE_DFLL: - - /* Check if the DFLL has been configured */ - if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE)) - return 0; - - /* Make sure that the DFLL module is ready */ - _system_dfll_wait_for_sync(); - - /* Check if operating in closed loop mode */ - if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) { - return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) * - (_system_clock_inst.dfll.mul & 0xffff); - } - - return 48000000UL; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) { - return 0; - } - - return _system_clock_inst.dpll.frequency; -#endif - - default: - return 0; - } -} - -/** - * \brief Configure the internal OSC8M oscillator clock source. - * - * Configures the 8MHz (nominal) internal RC oscillator with the given - * configuration settings. - * - * \param[in] config OSC8M configuration structure containing the new config - */ -void system_clock_source_osc8m_set_config( - struct system_clock_source_osc8m_config *const config) -{ - SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; - - /* Use temporary struct to reduce register access */ - temp.bit.PRESC = config->prescaler; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - - SYSCTRL->OSC8M = temp; -} - -/** - * \brief Configure the internal OSC32K oscillator clock source. - * - * Configures the 32KHz (nominal) internal RC oscillator with the given - * configuration settings. - * - * \param[in] config OSC32K configuration structure containing the new config - */ -void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config) -{ - SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; - - /* Update settings via a temporary struct to reduce register access */ - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - temp.bit.STARTUP = config->startup_time; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; - - SYSCTRL->OSC32K = temp; -} - -/** - * \brief Configure the external oscillator clock source. - * - * Configures the external oscillator clock source with the given configuration - * settings. - * - * \param[in] config External oscillator configuration structure containing - * the new config - */ -void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config) -{ - SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; - - temp.bit.STARTUP = config->startup_time; - - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } - - temp.bit.AMPGC = config->auto_gain_control; - - /* Set gain if automatic gain control is not selected */ - if (!config->auto_gain_control) { - if (config->frequency <= 2000000) { - temp.bit.GAIN = 0; - } else if (config->frequency <= 4000000) { - temp.bit.GAIN = 1; - } else if (config->frequency <= 8000000) { - temp.bit.GAIN = 2; - } else if (config->frequency <= 16000000) { - temp.bit.GAIN = 3; - } else if (config->frequency <= 30000000) { - temp.bit.GAIN = 4; - } - - } - - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - - /* Store XOSC frequency for internal use */ - _system_clock_inst.xosc.frequency = config->frequency; - - SYSCTRL->XOSC = temp; -} - -/** - * \brief Configure the XOSC32K external 32KHz oscillator clock source. - * - * Configures the external 32KHz oscillator clock source with the given - * configuration settings. - * - * \param[in] config XOSC32K configuration structure containing the new config - */ -void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config) -{ - SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K; - - temp.bit.STARTUP = config->startup_time; - - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } - - temp.bit.AAMPEN = config->auto_gain_control; - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; - - /* Cache the new frequency in case the user needs to check the current - * operating frequency later */ - _system_clock_inst.xosc32k.frequency = config->frequency; - - SYSCTRL->XOSC32K = temp; -} - -/** - * \brief Configure the DFLL clock source. - * - * Configures the Digital Frequency Locked Loop clock source with the given - * configuration settings. - * - * \note The DFLL will be running when this function returns, as the DFLL module - * needs to be enabled in order to perform the module configuration. - * - * \param[in] config DFLL configuration structure containing the new config - */ -void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config) -{ - _system_clock_inst.dfll.val = - SYSCTRL_DFLLVAL_COARSE(config->coarse_value) | - SYSCTRL_DFLLVAL_FINE(config->fine_value); - - _system_clock_inst.dfll.control = - (uint32_t)config->wakeup_lock | - (uint32_t)config->stable_tracking | - (uint32_t)config->quick_lock | - (uint32_t)config->chill_cycle | - ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos); - - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - - _system_clock_inst.dfll.mul = - SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | - SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | - SYSCTRL_DFLLMUL_MUL(config->multiply_factor); - - /* Enable the closed loop mode */ - _system_clock_inst.dfll.control |= config->loop_mode; - } - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - - _system_clock_inst.dfll.mul = - SYSCTRL_DFLLMUL_MUL(config->multiply_factor); - - /* Enable the USB recovery mode */ - _system_clock_inst.dfll.control |= config->loop_mode | - SYSCTRL_DFLLCTRL_BPLCKC; - } -} - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL -/** - * \brief Configure the DPLL clock source. - * - * Configures the Digital Phase-Locked Loop clock source with the given - * configuration settings. - * - * \note The DPLL will be running when this function returns, as the DPLL module - * needs to be enabled in order to perform the module configuration. - * - * \param[in] config DPLL configuration structure containing the new config - */ -void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config) -{ - - uint32_t tmpldr; - uint8_t tmpldrfrac; - uint32_t refclk; - - refclk = config->reference_frequency; - - /* Only reference clock REF1 can be divided */ - if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { - refclk = refclk / (2 * (config->reference_divider + 1)); - } - - /* Calculate LDRFRAC and LDR */ - tmpldr = (config->output_frequency << 4) / refclk; - tmpldrfrac = tmpldr & 0x0f; - tmpldr = (tmpldr >> 4) - 1; - - SYSCTRL->DPLLCTRLA.reg = - ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) | - ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos); - - SYSCTRL->DPLLRATIO.reg = - SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | - SYSCTRL_DPLLRATIO_LDR(tmpldr); - - SYSCTRL->DPLLCTRLB.reg = - SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) | - ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) | - SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) | - SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | - ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) | - ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) | - SYSCTRL_DPLLCTRLB_FILTER(config->filter); - - /* - * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) - */ - _system_clock_inst.dpll.frequency = - (refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4; -} -#endif - -/** - * \brief Writes the calibration values for a given oscillator clock source. - * - * Writes an oscillator calibration value to the given oscillator control - * registers. The acceptable ranges are: - * - * For OSC32K: - * - 7 bits (max value 128) - * For OSC8MHZ: - * - 8 bits (Max value 255) - * For OSCULP: - * - 5 bits (Max value 32) - * - * \note The frequency range parameter applies only when configuring the 8MHz - * oscillator and will be ignored for the other oscillators. - * - * \param[in] clock_source Clock source to calibrate - * \param[in] calibration_value Calibration value to write - * \param[in] freq_range Frequency range (8MHz oscillator only) - * - * \retval STATUS_OK The calibration value was written - * successfully. - * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock - * source. - */ -enum status_code system_clock_source_write_calibration( - const enum system_clock_source clock_source, - const uint16_t calibration_value, - const uint8_t freq_range) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - if (calibration_value > 0xfff || freq_range > 4) { - return STATUS_ERR_INVALID_ARG; - } - SYSCTRL->OSC8M.bit.CALIB = calibration_value; - SYSCTRL->OSC8M.bit.FRANGE = freq_range; - break; - case SYSTEM_CLOCK_SOURCE_OSC32K: - if (calibration_value > 128) { - return STATUS_ERR_INVALID_ARG; - } - _system_osc32k_wait_for_sync(); - SYSCTRL->OSC32K.bit.CALIB = calibration_value; - break; - case SYSTEM_CLOCK_SOURCE_ULP32K: - if (calibration_value > 32) { - return STATUS_ERR_INVALID_ARG; - } - SYSCTRL->OSCULP32K.bit.CALIB = calibration_value; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** - * \brief Enables a clock source. - * - * Enables a clock source which has been previously configured. - * - * \param[in] clock_source Clock source to enable - * - * \retval STATUS_OK Clock source was enabled successfully and - * is ready - * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this - * device - */ -enum status_code system_clock_source_enable( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; - return STATUS_OK; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE; - _system_clock_source_dfll_set_config_errata_9905(); - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; - break; -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Always enabled */ - return STATUS_OK; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; - } - - /** - * \brief Disables a clock source. - * - * Disables a clock source that was previously enabled. - * - * \param[in] clock_source Clock source to disable - * - * \retval STATUS_OK Clock source was disabled successfully - * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was - * given - */ - enum status_code system_clock_source_disable( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE; - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; - break; -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; - } - - /** - * \brief Checks if a clock source is ready. - * - * Checks if a given clock source is ready to be used. - * - * \param[in] clock_source Clock source to check if ready - * - * \returns Ready state of the given clock source. - * - * \retval true Clock source is enabled and ready - * \retval false Clock source is disabled or not yet ready - */ - bool system_clock_source_is_ready( - const enum system_clock_source clock_source) -{ - uint32_t mask = 0; - - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - mask = SYSCTRL_PCLKSR_OSC8MRDY; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - mask = SYSCTRL_PCLKSR_OSC32KRDY; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - mask = SYSCTRL_PCLKSR_XOSCRDY; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - mask = SYSCTRL_PCLKSR_XOSC32KRDY; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - mask = (SYSCTRL_PCLKSR_DFLLRDY | - SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC); - } else { - mask = SYSCTRL_PCLKSR_DFLLRDY; - } - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - return ((SYSCTRL->DPLLSTATUS.reg & - (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) == - (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)); -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - return true; - - default: - return false; - } - - return ((SYSCTRL->PCLKSR.reg & mask) == mask); -} - -/* Include some checks for conf_clocks.h validation */ -#include "clock_config_check.h" - -#if !defined(__DOXYGEN__) -/** \internal - * - * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h. - */ -# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \ - if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \ - struct system_gclk_gen_config gclk_conf; \ - system_gclk_gen_get_config_defaults(&gclk_conf); \ - gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \ - gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \ - gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \ - gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \ - system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \ - system_gclk_gen_enable(GCLK_GENERATOR_##n); \ - } - -/** \internal - * - * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h, - * provided that it is not the main Generic Clock Generator channel. - */ -# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \ - if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); } -#endif - -/** \internal - * - * Switch all peripheral clock to a not enabled general clock - * to save power. - */ -static void _switch_peripheral_gclk(void) -{ - uint32_t gclk_id; - struct system_gclk_chan_config gclk_conf; - -#if CONF_CLOCK_GCLK_1_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_1; -#elif CONF_CLOCK_GCLK_2_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_2; -#elif CONF_CLOCK_GCLK_3_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_3; -#elif CONF_CLOCK_GCLK_4_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_4; -#elif CONF_CLOCK_GCLK_5_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_5; -#elif CONF_CLOCK_GCLK_6_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_6; -#elif CONF_CLOCK_GCLK_7_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_7; -#else - gclk_conf.source_generator = GCLK_GENERATOR_7; -#endif - - for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) { - system_gclk_chan_set_config(gclk_id, &gclk_conf); - } -} - -/** - * \brief Initialize clock system based on the configuration in conf_clocks.h. - * - * This function will apply the settings in conf_clocks.h when run from the user - * application. All clock sources and GCLK generators are running when this function - * returns. - * - * \note OSC8M is always enabled and if user selects other clocks for GCLK generators, - * the OSC8M default enable can be disabled after system_clock_init. Make sure the - * clock switch successfully before disabling OSC8M. - */ -void system_clock_init(void) -{ - /* Various bits in the INTFLAG register can be set to one at startup. - This will ensure that these bits are cleared */ - SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | - SYSCTRL_INTFLAG_DFLLRDY; - - system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); - - /* Switch all peripheral clock to a not enabled general clock to save power. */ - _switch_peripheral_gclk(); - - /* XOSC */ -#if CONF_CLOCK_XOSC_ENABLE == true - struct system_clock_source_xosc_config xosc_conf; - system_clock_source_xosc_get_config_defaults(&xosc_conf); - - xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; - xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; - xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; - xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; - xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; - xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; - - system_clock_source_xosc_set_config(&xosc_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); -#endif - - - /* XOSC32K */ -#if CONF_CLOCK_XOSC32K_ENABLE == true - struct system_clock_source_xosc32k_config xosc32k_conf; - system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); - - xosc32k_conf.frequency = 32768UL; - xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; - xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; - xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL; - xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; - xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; - xosc32k_conf.on_demand = false; - xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; - - system_clock_source_xosc32k_set_config(&xosc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); - if (CONF_CLOCK_XOSC32K_ON_DEMAND) { - SYSCTRL->XOSC32K.bit.ONDEMAND = 1; - } -#endif - - - /* OSCK32K */ -#if CONF_CLOCK_OSC32K_ENABLE == true - SYSCTRL->OSC32K.bit.CALIB = - ((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> - SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful); - - struct system_clock_source_osc32k_config osc32k_conf; - system_clock_source_osc32k_get_config_defaults(&osc32k_conf); - - osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; - osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; - osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; - osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; - osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; - - system_clock_source_osc32k_set_config(&osc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); -#endif - - - /* DFLL Config (Open and Closed Loop) */ -#if CONF_CLOCK_DFLL_ENABLE == true - struct system_clock_source_dfll_config dfll_conf; - system_clock_source_dfll_get_config_defaults(&dfll_conf); - - dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; - dfll_conf.on_demand = false; - - /* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping - in DFLL.COARSE helps to output a frequency close to 48 MHz.*/ -#define NVM_DFLL_COARSE_POS 58 /* DFLL48M Coarse calibration value bit position.*/ -#define NVM_DFLL_COARSE_SIZE 6 /* DFLL48M Coarse calibration value bit size.*/ - - uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) - + (NVM_DFLL_COARSE_POS / 32)) - >> (NVM_DFLL_COARSE_POS % 32)) - & ((1 << NVM_DFLL_COARSE_SIZE) - 1); - /* In some revision chip, the coarse calibration value is not correct. */ - if (coarse == 0x3f) { - coarse = 0x1f; - } - dfll_conf.coarse_value = coarse; - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { - dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; - } - -# if CONF_CLOCK_DFLL_QUICK_LOCK == true - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; -# else - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; -# endif - -# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; -# else - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; -# endif - -# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; -# else - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; -# endif - -# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; -# else - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; -# endif - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; - } - - dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; - dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - dfll_conf.fine_value = 0x1ff; - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; - - dfll_conf.multiply_factor = 48000; - } - - system_clock_source_dfll_set_config(&dfll_conf); -#endif - - - /* OSC8M */ - struct system_clock_source_osc8m_config osc8m_conf; - system_clock_source_osc8m_get_config_defaults(&osc8m_conf); - - osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER; - osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND; - osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY; - - system_clock_source_osc8m_set_config(&osc8m_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M); - - - /* GCLK */ -#if CONF_CLOCK_CONFIGURE_GCLK == true - system_gclk_init(); - - /* Configure all GCLK generators except for the main generator, which - * is configured later after all other clock systems are set up */ - MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); - -# if CONF_CLOCK_DFLL_ENABLE == true - /* Enable DFLL reference clock if in closed loop mode */ - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - struct system_gclk_chan_config dfll_gclk_chan_conf; - - system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); - dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); - } -# endif - -# if CONF_CLOCK_DPLL_ENABLE == true - /* Enable DPLL internal lock timer and reference clock */ - struct system_gclk_chan_config dpll_gclk_chan_conf; - system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf); - if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) { - dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K); - } - - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { - dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL); - } -# endif -#endif - - - /* DFLL Enable (Open and Closed Loop) */ -#if CONF_CLOCK_DFLL_ENABLE == true - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); - if (CONF_CLOCK_DFLL_ON_DEMAND) { - SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1; - } -#endif - - /* DPLL */ -#ifdef FEATURE_SYSTEM_CLOCK_DPLL -# if (CONF_CLOCK_DPLL_ENABLE == true) - - /* Enable DPLL reference clock */ - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) { - /* XOSC32K should have been enabled for DPLL_REF0 */ - Assert(CONF_CLOCK_XOSC32K_ENABLE); - } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { - /* XOSC should have been enabled for DPLL_REF1 */ - Assert(CONF_CLOCK_XOSC_ENABLE); - } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { - /* GCLK should have been enabled */ - Assert(CONF_CLOCK_CONFIGURE_GCLK); - } else { - Assert(false); - } - - struct system_clock_source_dpll_config dpll_config; - system_clock_source_dpll_get_config_defaults(&dpll_config); - - dpll_config.on_demand = false; - dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; - dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; - dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; - dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; - - dpll_config.filter = CONF_CLOCK_DPLL_FILTER; - dpll_config.lock_time = CONF_CLOCK_DPLL_LOCK_TIME; - - dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; - dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; - dpll_config.reference_divider = CONF_CLOCK_DPLL_REFERENCE_DIVIDER; - dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; - - system_clock_source_dpll_set_config(&dpll_config); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); - if (CONF_CLOCK_DPLL_ON_DEMAND) { - SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1; - } - -# endif -#endif - - /* CPU and BUS clocks */ - system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); - - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER); - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER); - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER); - - /* GCLK 0 */ -#if CONF_CLOCK_CONFIGURE_GCLK == true - /* Configure the main GCLK last as it might depend on other generators */ - _CONF_CLOCK_GCLK_CONFIG(0, ~); -#endif -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_config_check.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_config_check.h deleted file mode 100644 index fd4757e2821..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_config_check.h +++ /dev/null @@ -1,454 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CLOCK_CONFIG_CHECK_H -# define CLOCK_CONFIG_CHECK_H - -#if !defined(CONF_CLOCK_FLASH_WAIT_STATES) -# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_CPU_DIVIDER) -# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBA_DIVIDER) -# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBB_DIVIDER) -# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBC_DIVIDER) -# error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_PRESCALER) -# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND) -# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY) -# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_ENABLE) -# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL) -# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY) -# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME) -# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) -# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_ON_DEMAND) -# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY) -# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE) -# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL) -# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME) -# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL) -# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT) -# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT) -# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND) -# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY) -# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE) -# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME) -# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT) -# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT) -# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND) -# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY) -# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ENABLE) -# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_LOOP_MODE) -# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ON_DEMAND) -# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_FINE_VALUE) -# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR) -# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR) -# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK) -# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK) -# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP) -# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE) -# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE) -# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE) -# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_ENABLE) -# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_ON_DEMAND) -# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY) -# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS) -# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST) -# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE) -# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_TIME) -# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK) -# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_FILTER) -# error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY) -# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER) -# error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY) -# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR) -# error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR) -# error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_CONFIGURE_GCLK) -# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_ENABLE) -# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_PRESCALER) -# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_ENABLE) -# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_PRESCALER) -# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_ENABLE) -# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_PRESCALER) -# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_ENABLE) -# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_PRESCALER) -# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_ENABLE) -# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_PRESCALER) -# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_ENABLE) -# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_PRESCALER) -# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_ENABLE) -# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_PRESCALER) -# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_ENABLE) -# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_PRESCALER) -# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_ENABLE) -# error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_PRESCALER) -# error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#endif /* CLOCK_CONFIG_CHECK_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_feature.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_feature.h deleted file mode 100644 index b647b7f694b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_feature.h +++ /dev/null @@ -1,1492 +0,0 @@ -/** - * \file - * - * \brief SAM Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED -#define SYSTEM_CLOCK_FEATURE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK) - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the device's clocking related functions. This includes - * the various clock sources, bus clocks, and generic clocks within the device, - * with functions to manage the enabling, disabling, source selection, and - * prescaling of clocks to various internal peripherals. - * - * The following peripherals are used by this module: - * - * - GCLK (Generic Clock Management) - * - PM (Power Management) - * - SYSCTRL (Clock Source Control) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM DA0/DA1 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_clock_prerequisites - * - \ref asfdoc_sam0_system_clock_module_overview - * - \ref asfdoc_sam0_system_clock_special_considerations - * - \ref asfdoc_sam0_system_clock_extra_info - * - \ref asfdoc_sam0_system_clock_examples - * - \ref asfdoc_sam0_system_clock_api_overview - * - * - * \section asfdoc_sam0_system_clock_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_clock_module_overview Module Overview - * The SAM devices contain a sophisticated clocking system, which is designed - * to give the maximum flexibility to the user application. This system allows - * a system designer to tune the performance and power consumption of the device - * in a dynamic manner, to achieve the best trade-off between the two for a - * particular application. - * - * This driver provides a set of functions for the configuration and management - * of the various clock related functionality within the device. - * - * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_SYSTEM_CLOCK_DPLLSAMD21, SAMR21, SAMD10, SAMD11, SAMDAx
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources - * The SAM devices have a number of master clock source modules, each of - * which being capable of producing a stabilized output frequency, which can then - * be fed into the various peripherals and modules within the device. - * - * Possible clock source modules include internal R/C oscillators, internal - * DFLL modules, as well as external crystal oscillators and/or clock inputs. - * - * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks - * The CPU and AHB/APBx buses are clocked by the same physical clock source - * (referred in this module as the Main Clock), however the APBx buses may - * have additional prescaler division ratios set to give each peripheral bus a - * different clock speed. - * - * The general main clock tree for the CPU and associated buses is shown in - * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below". - * - * \anchor asfdoc_sam0_system_clock_module_clock_tree - * \dot - * digraph overview { - * rankdir=LR; - * clk_src [label="Clock Sources", shape=none, height=0]; - * node [label="CPU Bus" shape=ellipse] cpu_bus; - * node [label="AHB Bus" shape=ellipse] ahb_bus; - * node [label="APBA Bus" shape=ellipse] apb_a_bus; - * node [label="APBB Bus" shape=ellipse] apb_b_bus; - * node [label="APBC Bus" shape=ellipse] apb_c_bus; - * node [label="Main Bus\nPrescaler" shape=square] main_prescaler; - * node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler; - * node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler; - * node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler; - * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux; - * - * clk_src -> main_clock_mux; - * main_clock_mux -> main_prescaler; - * main_prescaler -> cpu_bus; - * main_prescaler -> ahb_bus; - * main_prescaler -> apb_a_prescaler; - * main_prescaler -> apb_b_prescaler; - * main_prescaler -> apb_c_prescaler; - * apb_a_prescaler -> apb_a_bus; - * apb_b_prescaler -> apb_b_bus; - * apb_c_prescaler -> apb_c_bus; - * } - * \enddot - * - * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking - * To save power, the input clock to one or more peripherals on the AHB and APBx - * buses can be masked away - when masked, no clock is passed into the module. - * Disabling of clocks of unused modules will prevent all access to the masked - * module, but will reduce the overall device power consumption. - * - * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks - * Within the SAM devices there are a number of Generic Clocks; these are used to - * provide clocks to the various peripheral clock domains in the device in a - * standardized manner. One or more master source clocks can be selected as the - * input clock to a Generic Clock Generator, which can prescale down the input - * frequency to a slower rate for use in a peripheral. - * - * Additionally, a number of individually selectable Generic Clock Channels are - * provided, which multiplex and gate the various generator outputs for one or - * more peripherals within the device. This setup allows for a single common - * generator to feed one or more channels, which can then be enabled or disabled - * individually as required. - * - * \anchor asfdoc_sam0_system_clock_module_chain_overview - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Clock\nSource a" shape=square] system_clock_source; - * node [label="Generator 1" shape=square] clock_gen; - * node [label="Channel x" shape=square] clock_chan0; - * node [label="Channel y" shape=square] clock_chan1; - * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0; - * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1; - * - * system_clock_source -> clock_gen; - * clock_gen -> clock_chan0; - * clock_chan0 -> peripheral0; - * clock_gen -> clock_chan1; - * clock_chan1 -> peripheral1; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example - * An example setup of a complete clock chain within the device is shown in - * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below". - * - * \anchor asfdoc_sam0_system_clock_module_chain_example_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="External\nOscillator" shape=square] system_clock_source0; - * node [label="Generator 0" shape=square] clock_gen0; - * node [label="Channel x" shape=square] clock_chan0; - * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0; - * - * system_clock_source0 -> clock_gen0; - * clock_gen0 -> clock_chan0; - * clock_chan0 -> peripheral0; - * node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1; - * node [label="Generator 1" shape=square] clock_gen1; - * node [label="Channel y" shape=square] clock_chan1; - * node [label="Channel z" shape=square] clock_chan2; - * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1; - * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2; - * - * system_clock_source1 -> clock_gen1; - * clock_gen1 -> clock_chan1; - * clock_gen1 -> clock_chan2; - * clock_chan1 -> peripheral1; - * clock_chan2 -> peripheral2; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators - * Each Generic Clock generator within the device can source its input clock - * from one of the provided Source Clocks, and prescale the output for one or - * more Generic Clock Channels in a one-to-many relationship. The generators - * thus allow for several clocks to be generated of different frequencies, - * power usages, and accuracies, which can be turned on and off individually to - * disable the clocks to multiple peripherals as a group. - * - * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels - * To connect a Generic Clock Generator to a peripheral within the - * device, a Generic Clock Channel is used. Each peripheral or - * peripheral group has an associated Generic Clock Channel, which serves as the - * clock input for the peripheral(s). To supply a clock to the peripheral - * module(s), the associated channel must be connected to a running Generic - * Clock Generator and the channel enabled. - * - * \section asfdoc_sam0_system_clock_special_considerations Special Considerations - * - * There are no special considerations for this module. - * - * - * \section asfdoc_sam0_system_clock_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes: - * - \ref asfdoc_sam0_system_clock_extra_acronyms - * - \ref asfdoc_sam0_system_clock_extra_dependencies - * - \ref asfdoc_sam0_system_clock_extra_errata - * - \ref asfdoc_sam0_system_clock_extra_history - * - * - * \section asfdoc_sam0_system_clock_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_system_clock_exqsg. - * - * - * \section asfdoc_sam0_system_clock_api_overview API Overview - * @{ - */ - -#include -#include - -/** - * \name Driver Feature Definition - * Define system clock features set according to different device family. - * @{ - */ -#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAMDA1) || defined(__DOXYGEN__) -/** Digital Phase Locked Loop (DPLL) feature support. */ -# define FEATURE_SYSTEM_CLOCK_DPLL -#endif -/*@}*/ - -/** - * \brief Available start-up times for the XOSC32K. - * - * Available external 32KHz oscillator start-up times, as a number of external - * clock cycles. - */ -enum system_xosc32k_startup { - /** Wait zero clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_0, - /** Wait 32 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_32, - /** Wait 2048 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_4096, - /** Wait 16384 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_32768, - /** Wait 65536 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_65536, - /** Wait 131072 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_131072, -}; - -/** - * \brief Available start-up times for the XOSC. - * - * Available external oscillator start-up times, as a number of external clock - * cycles. - */ -enum system_xosc_startup { - /** Wait one clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_1, - /** Wait two clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_2, - /** Wait four clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_4, - /** Wait eight clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_8, - /** Wait 16 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_16, - /** Wait 32 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_32, - /** Wait 64 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_64, - /** Wait 128 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_128, - /** Wait 256 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_256, - /** Wait 512 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_512, - /** Wait 1024 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_1024, - /** Wait 2048 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_4096, - /** Wait 8192 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_8192, - /** Wait 16384 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_32768, -}; - -/** - * \brief Available start-up times for the OSC32K. - * - * Available internal 32KHz oscillator start-up times, as a number of internal - * OSC32K clock cycles. - */ -enum system_osc32k_startup { - /** Wait three clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_3, - /** Wait four clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_4, - /** Wait six clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_6, - /** Wait ten clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_10, - /** Wait 18 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_18, - /** Wait 34 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_34, - /** Wait 66 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_66, - /** Wait 130 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_130, -}; - -/** - * \brief Division prescalers for the internal 8MHz system clock. - * - * Available prescalers for the internal 8MHz (nominal) system clock. - */ -enum system_osc8m_div { - /** Do not divide the 8MHz RC oscillator output. */ - SYSTEM_OSC8M_DIV_1, - /** Divide the 8MHz RC oscillator output by two. */ - SYSTEM_OSC8M_DIV_2, - /** Divide the 8MHz RC oscillator output by four. */ - SYSTEM_OSC8M_DIV_4, - /** Divide the 8MHz RC oscillator output by eight. */ - SYSTEM_OSC8M_DIV_8, -}; - -/** - * \brief Frequency range for the internal 8MHz RC oscillator. - * - * Internal 8MHz RC oscillator frequency range setting - */ -enum system_osc8m_frequency_range { - /** Frequency range 4MHz to 6MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6, - /** Frequency range 6MHz to 8MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8, - /** Frequency range 8MHz to 11MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11, - /** Frequency range 11MHz to 15MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15, -}; - -/** - * \brief Main CPU and APB/AHB bus clock source prescaler values. - * - * Available division ratios for the CPU and APB/AHB bus clocks. - */ -enum system_main_clock_div { - /** Divide Main clock by one. */ - SYSTEM_MAIN_CLOCK_DIV_1, - /** Divide Main clock by two. */ - SYSTEM_MAIN_CLOCK_DIV_2, - /** Divide Main clock by four. */ - SYSTEM_MAIN_CLOCK_DIV_4, - /** Divide Main clock by eight. */ - SYSTEM_MAIN_CLOCK_DIV_8, - /** Divide Main clock by 16. */ - SYSTEM_MAIN_CLOCK_DIV_16, - /** Divide Main clock by 32. */ - SYSTEM_MAIN_CLOCK_DIV_32, - /** Divide Main clock by 64. */ - SYSTEM_MAIN_CLOCK_DIV_64, - /** Divide Main clock by 128. */ - SYSTEM_MAIN_CLOCK_DIV_128, -}; - -/** - * \brief External clock source types. - * - * Available external clock source types. - */ -enum system_clock_external { - /** The external clock source is a crystal oscillator. */ - SYSTEM_CLOCK_EXTERNAL_CRYSTAL, - /** The connected clock source is an external logic level clock signal. */ - SYSTEM_CLOCK_EXTERNAL_CLOCK, -}; - -/** - * \brief Operating modes of the DFLL clock source. - * - * Available operating modes of the DFLL clock source module. - */ -enum system_clock_dfll_loop_mode { - /** The DFLL is operating in open loop mode with no feedback. */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, - /** The DFLL is operating in closed loop mode with frequency feedback from - * a low frequency reference clock. - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE, - -#ifdef SYSCTRL_DFLLCTRL_USBCRM - /** The DFLL is operating in USB recovery mode with frequency feedback - * from USB SOF. - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM, -#endif -}; - -/** - * \brief Locking behavior for the DFLL during device wake-up. - * - * DFLL lock behavior modes on device wake-up from sleep. - */ -enum system_clock_dfll_wakeup_lock { - /** Keep DFLL lock when the device wakes from sleep. */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, - /** Lose DFLL lock when the devices wakes from sleep. */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW, -}; - -/** - * \brief Fine tracking behavior for the DFLL once a lock has been acquired. - * - * DFLL fine tracking behavior modes after a lock has been acquired. - */ -enum system_clock_dfll_stable_tracking { - /** Keep tracking after the DFLL has gotten a fine lock. */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, - /** Stop tracking after the DFLL has gotten a fine lock. */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE, -}; - -/** - * \brief Chill-cycle behavior of the DFLL module. - * - * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period - * of time when the DFLL output frequency is not measured by the unit, to allow - * the output to stabilize after a change in the input clock source. - */ -enum system_clock_dfll_chill_cycle { - /** Enable a chill cycle, where the DFLL output frequency is not measured. */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, - /** Disable a chill cycle, where the DFLL output frequency is not measured. */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS, -}; - -/** - * \brief QuickLock settings for the DFLL module. - * - * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of - * the DFLL output frequency at the expense of accuracy. - */ -enum system_clock_dfll_quick_lock { - /** Enable the QuickLock feature for looser lock requirements on the DFLL. */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, - /** Disable the QuickLock feature for strict lock requirements on the DFLL. */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS, -}; - -/** - * \brief Available clock sources in the system. - * - * Clock sources available to the GCLK generators. - */ -enum system_clock_source { - /** Internal 8MHz RC oscillator. */ - SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M, - /** Internal 32KHz RC oscillator. */ - SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K, - /** External oscillator. */ - SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC , - /** External 32KHz oscillator. */ - SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K, - /** Digital Frequency Locked Loop (DFLL). */ - SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M, - /** Internal Ultra Low Power 32KHz oscillator. */ - SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K, - /** Generator input pad. */ - SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN, - /** Generic clock generator one output. */ - SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1, -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - /** Digital Phase Locked Loop (DPLL). - * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it. - */ - SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL, -#endif -}; - -/** - * \brief List of APB peripheral buses. - * - * Available bus clock domains on the APB bus. - */ -enum system_clock_apb_bus { - /** Peripheral bus A on the APB bus. */ - SYSTEM_CLOCK_APB_APBA, - /** Peripheral bus B on the APB bus. */ - SYSTEM_CLOCK_APB_APBB, - /** Peripheral bus C on the APB bus. */ - SYSTEM_CLOCK_APB_APBC, -}; - -/** - * \brief Configuration structure for XOSC. - * - * External oscillator clock configuration structure. - */ -struct system_clock_source_xosc_config { - /** External clock type. */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time. */ - enum system_xosc_startup startup_time; - /** Enable automatic amplitude gain control. */ - bool auto_gain_control; - /** External clock/crystal frequency. */ - uint32_t frequency; - /** Keep the XOSC enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC won't run - * until requested by a peripheral. */ - bool on_demand; -}; - -/** - * \brief Configuration structure for XOSC32K. - * - * External 32KHz oscillator clock configuration structure. - */ -struct system_clock_source_xosc32k_config { - /** External clock type. */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time. */ - enum system_xosc32k_startup startup_time; - /** Enable automatic amplitude control. */ - bool auto_gain_control; - /** Enable 1KHz output. */ - bool enable_1khz_output; - /** Enable 32KHz output. */ - bool enable_32khz_output; - /** External clock/crystal frequency. */ - uint32_t frequency; - /** Keep the XOSC32K enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC32K won't run - * until requested by a peripheral. */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock. */ - bool write_once; -}; - -/** - * \brief Configuration structure for OSC8M. - * - * Internal 8MHz (nominal) oscillator configuration structure. - */ -struct system_clock_source_osc8m_config { - /** Internal 8MHz RC oscillator prescaler. */ - enum system_osc8m_div prescaler; - /** Keep the OSC8M enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC8M won't run - * until requested by a peripheral. */ - bool on_demand; -}; - -/** - * \brief Configuration structure for OSC32K. - * - * Internal 32KHz (nominal) oscillator configuration structure. - */ -struct system_clock_source_osc32k_config { - /** Startup time. */ - enum system_osc32k_startup startup_time; - /** Enable 1KHz output. */ - bool enable_1khz_output; - /** Enable 32KHz output. */ - bool enable_32khz_output; - /** Keep the OSC32K enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC32K won't run - * until requested by a peripheral. */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock. */ - bool write_once; -}; - -/** - * \brief Configuration structure for DFLL. - * - * DFLL oscillator configuration structure. - */ -struct system_clock_source_dfll_config { - /** Loop mode. */ - enum system_clock_dfll_loop_mode loop_mode; - /** Run On Demand. If this is set the DFLL won't run - * until requested by a peripheral. */ - bool on_demand; - /** Enable Quick Lock. */ - enum system_clock_dfll_quick_lock quick_lock; - /** Enable Chill Cycle. */ - enum system_clock_dfll_chill_cycle chill_cycle; - /** DFLL lock state on wakeup. */ - enum system_clock_dfll_wakeup_lock wakeup_lock; - /** DFLL tracking after fine lock. */ - enum system_clock_dfll_stable_tracking stable_tracking; - /** Coarse calibration value (Open loop mode). */ - uint8_t coarse_value; - /** Fine calibration value (Open loop mode). */ - uint16_t fine_value; - /** Coarse adjustment maximum step size (Closed loop mode). */ - uint8_t coarse_max_step; - /** Fine adjustment maximum step size (Closed loop mode). */ - uint16_t fine_max_step; - /** DFLL multiply factor (Closed loop mode. */ - uint16_t multiply_factor; -}; - -/** - * \name External Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for XOSC. - * - * Fills a configuration structure with the default configuration for an - * external oscillator module: - * - External Crystal - * - Start-up time of 16384 external clock cycles - * - Automatic crystal gain control mode enabled - * - Frequency of 12MHz - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_xosc_get_config_defaults( - struct system_clock_source_xosc_config *const config) -{ - Assert(config); - - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC_STARTUP_16384; - config->auto_gain_control = true; - config->frequency = 12000000UL; - config->run_in_standby = false; - config->on_demand = true; -} - -void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config); - -/** - * @} - */ - - -/** - * \name External 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for XOSC32K. - * - * Fills a configuration structure with the default configuration for an - * external 32KHz oscillator module: - * - External Crystal - * - Start-up time of 16384 external clock cycles - * - Automatic crystal gain control mode disabled - * - Frequency of 32.768KHz - * - 1KHz clock output disabled - * - 32KHz clock output enabled - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - Don't lock registers after configuration has been written - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_xosc32k_get_config_defaults( - struct system_clock_source_xosc32k_config *const config) -{ - Assert(config); - - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC32K_STARTUP_16384; - config->auto_gain_control = false; - config->frequency = 32768UL; - config->enable_1khz_output = false; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->write_once = false; -} - -void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config); -/** - * @} - */ - - -/** - * \name Internal 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSC32K. - * - * Fills a configuration structure with the default configuration for an - * internal 32KHz oscillator module: - * - 1KHz clock output enabled - * - 32KHz clock output enabled - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - Set startup time to 130 cycles - * - Don't lock registers after configuration has been written - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osc32k_get_config_defaults( - struct system_clock_source_osc32k_config *const config) -{ - Assert(config); - - config->enable_1khz_output = true; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->startup_time = SYSTEM_OSC32K_STARTUP_130; - config->write_once = false; -} - -void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config); - -/** - * @} - */ - - -/** - * \name Internal 8MHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSC8M. - * - * Fills a configuration structure with the default configuration for an - * internal 8MHz (nominal) oscillator module: - * - Clock output frequency divided by a factor of eight - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osc8m_get_config_defaults( - struct system_clock_source_osc8m_config *const config) -{ - Assert(config); - - config->prescaler = SYSTEM_OSC8M_DIV_8; - config->run_in_standby = false; - config->on_demand = true; -} - -void system_clock_source_osc8m_set_config( - struct system_clock_source_osc8m_config *const config); - -/** - * @} - */ - - -/** - * \name Internal DFLL Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for DFLL. - * - * Fills a configuration structure with the default configuration for a - * DFLL oscillator module: - * - Open loop mode - * - QuickLock mode enabled - * - Chill cycle enabled - * - Output frequency lock maintained during device wake-up - * - Continuous tracking of the output frequency - * - Default tracking values at the mid-points for both coarse and fine - * tracking parameters - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_dfll_get_config_defaults( - struct system_clock_source_dfll_config *const config) -{ - Assert(config); - - config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN; - config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; - config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; - config->on_demand = true; - - /* Open loop mode calibration value */ - config->coarse_value = 0x1f / 4; /* Midpoint */ - config->fine_value = 0xff / 4; /* Midpoint */ - - /* Closed loop mode */ - config->coarse_max_step = 1; - config->fine_max_step = 1; - config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */ -} - -void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config); - -/** - * @} - */ - -/** - * \name Clock Source Management - * @{ - */ -enum status_code system_clock_source_write_calibration( - const enum system_clock_source system_clock_source, - const uint16_t calibration_value, - const uint8_t freq_range); - -enum status_code system_clock_source_enable( - const enum system_clock_source system_clock_source); - -enum status_code system_clock_source_disable( - const enum system_clock_source clk_source); - -bool system_clock_source_is_ready( - const enum system_clock_source clk_source); - -uint32_t system_clock_source_get_hz( - const enum system_clock_source clk_source); - -/** - * @} - */ - -/** - * \name Main Clock Management - * @{ - */ - -/** - * \brief Set main CPU clock divider. - * - * Sets the clock divider used on the main clock to provide the CPU clock. - * - * \param[in] divider CPU clock divider to set - */ -static inline void system_cpu_clock_set_divider( - const enum system_main_clock_div divider) -{ - Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider); - PM->CPUSEL.reg = (uint32_t)divider; -} - -/** - * \brief Retrieves the current frequency of the CPU core. - * - * Retrieves the operating frequency of the CPU core, obtained from the main - * generic clock and the set CPU bus divider. - * - * \return Current CPU frequency in Hz. - */ -static inline uint32_t system_cpu_clock_get_hz(void) -{ - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg); -} - -/** - * \brief Set APBx clock divider. - * - * Set the clock divider used on the main clock to provide the clock for the - * given APBx bus. - * - * \param[in] divider APBx bus divider to set - * \param[in] bus APBx bus to set divider - * - * \returns Status of the clock division change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given - * \retval STATUS_OK The APBx clock was set successfully - */ -static inline enum status_code system_apb_clock_set_divider( - const enum system_clock_apb_bus bus, - const enum system_main_clock_div divider) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBASEL.reg = (uint32_t)divider; - break; - case SYSTEM_CLOCK_APB_APBB: - PM->APBBSEL.reg = (uint32_t)divider; - break; - case SYSTEM_CLOCK_APB_APBC: - PM->APBCSEL.reg = (uint32_t)divider; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; - } - - /** - * \brief Retrieves the current frequency of a ABPx. - * - * Retrieves the operating frequency of an APBx bus, obtained from the main - * generic clock and the set APBx bus divider. - * - * \return Current APBx bus frequency in Hz. - */ - static inline uint32_t system_apb_clock_get_hz( - const enum system_clock_apb_bus bus) -{ - uint16_t bus_divider = 0; - - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - bus_divider = PM->APBASEL.reg; - break; - case SYSTEM_CLOCK_APB_APBB: - bus_divider = PM->APBBSEL.reg; - break; - case SYSTEM_CLOCK_APB_APBC: - bus_divider = PM->APBCSEL.reg; - break; - default: - Assert(false); - return 0; - } - - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider); -} - - -/** - * @} - */ - -/** - * \name Bus Clock Masking - * @{ - */ - -/** - * \brief Set bits in the clock mask for the AHB bus. - * - * This function will set bits in the clock mask for the AHB bus. - * Any bits set to 1 will enable that clock, 0 bits in the mask - * will be ignored. - * - * \param[in] ahb_mask AHB clock mask to enable - */ -static inline void system_ahb_clock_set_mask( - const uint32_t ahb_mask) -{ - PM->AHBMASK.reg |= ahb_mask; -} - -/** - * \brief Clear bits in the clock mask for the AHB bus. - * - * This function will clear bits in the clock mask for the AHB bus. - * Any bits set to 1 will disable that clock, 0 bits in the mask - * will be ignored. - * - * \param[in] ahb_mask AHB clock mask to disable - */ -static inline void system_ahb_clock_clear_mask( - const uint32_t ahb_mask) -{ - PM->AHBMASK.reg &= ~ahb_mask; -} - -/** - * \brief Set bits in the clock mask for an APBx bus. - * - * This function will set bits in the clock mask for an APBx bus. - * Any bits set to 1 will enable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_* - * constants from the device header files - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus given - * \retval STATUS_OK The clock mask was set successfully - */ -static inline enum status_code system_apb_clock_set_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBAMASK.reg |= mask; - break; - - case SYSTEM_CLOCK_APB_APBB: - PM->APBBMASK.reg |= mask; - break; - - case SYSTEM_CLOCK_APB_APBC: - PM->APBCMASK.reg |= mask; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; - } - - /** - * \brief Clear bits in the clock mask for an APBx bus. - * - * This function will clear bits in the clock mask for an APBx bus. - * Any bits set to 1 will disable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to clear clock mask bits - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given - * \retval STATUS_OK The clock mask was changed successfully - */ - static inline enum status_code system_apb_clock_clear_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBAMASK.reg &= ~mask; - break; - - case SYSTEM_CLOCK_APB_APBB: - PM->APBBMASK.reg &= ~mask; - break; - - case SYSTEM_CLOCK_APB_APBC: - PM->APBCMASK.reg &= ~mask; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; - } - - /** - * @} - */ - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - /** - * \brief Reference clock source of the DPLL module. - */ - enum system_clock_source_dpll_reference_clock { - /** Select XOSC32K as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K, - /** Select XOSC as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC, - /** Select GCLK as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, -}; - -/** - * \brief Lock time-out value of the DPLL module. - */ -enum system_clock_source_dpll_lock_time { - /** Set no time-out as default. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, - /** Set time-out if no lock within 8ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04, - /** Set time-out if no lock within 9ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS, - /** Set time-out if no lock within 10ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS, - /** Set time-out if no lock within 11ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS, -}; - -/** - * \brief Filter type of the DPLL module. - */ -enum system_clock_source_dpll_filter { - /** Default filter mode. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, - /** Low bandwidth filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER, - /** High bandwidth filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER, - /** High damping filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER, -}; - -/** - * \brief Configuration structure for DPLL. - * - * DPLL oscillator configuration structure. - */ -struct system_clock_source_dpll_config { - /** Run On Demand. If this is set the DPLL won't run - * until requested by a peripheral. */ - bool on_demand; - /** Keep the DPLL enabled in standby sleep mode. */ - bool run_in_standby; - /** Bypass lock signal. */ - bool lock_bypass; - /** Wake up fast. If this is set DPLL output clock is enabled after - * the startup time. */ - bool wake_up_fast; - /** Enable low power mode. */ - bool low_power_enable; - - /** Output frequency of the clock. */ - uint32_t output_frequency; - /** Reference frequency of the clock. */ - uint32_t reference_frequency; - /** Devider of reference clock. */ - uint16_t reference_divider; - - /** Filter type of the DPLL module. */ - enum system_clock_source_dpll_filter filter; - /** Lock time-out value of the DPLL module. */ - enum system_clock_source_dpll_lock_time lock_time; - /** Reference clock source of the DPLL module. */ - enum system_clock_source_dpll_reference_clock reference_clock; -}; - -/** - * \name Internal DPLL Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for DPLL. - * - * Fills a configuration structure with the default configuration for a - * DPLL oscillator module: - * - Run only when requested by peripheral (on demand) - * - Don't run in STANDBY sleep mode - * - Lock bypass disabled - * - Fast wake up disabled - * - Low power mode disabled - * - Output frequency is 48MHz - * - Reference clock frequency is 32768Hz - * - Not divide reference clock - * - Select REF0 as reference clock - * - Set lock time to default mode - * - Use default filter - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_dpll_get_config_defaults( - struct system_clock_source_dpll_config *const config) -{ - config->on_demand = true; - config->run_in_standby = false; - config->lock_bypass = false; - config->wake_up_fast = false; - config->low_power_enable = false; - - config->output_frequency = 48000000; - config->reference_frequency = 32768; - config->reference_divider = 1; - config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K; - - config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT; - config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT; -}; - -void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config); - -/* @} */ -#endif - -/** - * \name System Clock Initialization - * @{ - */ - -void system_clock_init(void); - -/** - * @} - */ - -/** - * \name System Flash Wait States - * @{ - */ - -/** - * \brief Set flash controller wait states. - * - * Will set the number of wait states that are used by the onboard - * flash memory. The number of wait states depend on both device - * supply voltage and CPU speed. The required number of wait states - * can be found in the electrical characteristics of the device. - * - * \param[in] wait_states Number of wait states to use for internal flash - */ -static inline void system_flash_set_waitstates(uint8_t wait_states) -{ - Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) == - ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos)); - - NVMCTRL->CTRLB.bit.RWS = wait_states; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver - * - * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DFLLDigital Frequency Locked Loop
MUXMultiplexer
OSC32KInternal 32KHz Oscillator
OSC8MInternal 8MHz Oscillator
PLLPhase Locked Loop
OSCOscillator
XOSCExternal Oscillator
XOSC32KExternal 32KHz Oscillator
AHBAdvanced High-performance Bus
APBAdvanced Peripheral Bus
DPLLDigital Phase Locked Loop
- * - * - * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_clock_extra_errata Errata - * - * - This driver implements experimental workaround for errata 9905 - * - * "The DFLL clock must be requested before being configured otherwise a - * write access to a DFLL register can freeze the device." - * This driver will enable and configure the DFLL before the ONDEMAND bit is set. - * - * - * \section asfdoc_sam0_system_clock_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
- * \li Corrected OSC32K startup time definitions - * \li Support locking of OSC32K and XOSC32K config register (default: false) - * \li Added DPLL support, functions added: - * \c system_clock_source_dpll_get_config_defaults() and - * \c system_clock_source_dpll_set_config() - * \li Moved gclk channel locking feature out of the config struct - * functions added: - * \c system_gclk_chan_lock(), - * \c system_gclk_chan_is_locked() - * \c system_gclk_chan_is_enabled() and - * \c system_gclk_gen_is_enabled() - *
Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled - * and configured to a failed/not running clock generator
- * \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false - * \li Fixed system_flash_set_waitstates() failing with an assertion - * if an odd number of wait states provided - *
- * \li Updated dfll configuration function to implement workaround for - * errata 9905 in the DFLL module - * \li Updated \c system_clock_init() to reset interrupt flags before - * they are used - * \li Fixed \c system_clock_source_get_hz() to return correcy DFLL - * frequency number - *
\li Fixed \c system_clock_source_is_ready not returning the correct - * state for \c SYSTEM_CLOCK_SOURCE_OSC8M - * \li Renamed the various \c system_clock_source_*_get_default_config() - * functions to \c system_clock_source_*_get_config_defaults() to - * match the remainder of ASF - * \li Added OSC8M calibration constant loading from the device signature - * row when the oscillator is initialized - * \li Updated default configuration of the XOSC32 to disable Automatic - * Gain Control due to silicon errata - *
Initial Release
- */ - -/** - * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple - * examples with step-by-step instructions to configure and use this driver in - * a selection of use cases. Note that QSGs can be compiled as a standalone - * application or be added to the user application. - * - * - \subpage asfdoc_sam0_system_clock_basic_use_case - * - \subpage asfdoc_sam0_system_gclk_basic_use_case - * - * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
E04/2015Added support for SAMDAx.
D12/2014Added support for SAMR21 and SAMD10/D11.
C01/2014Added support for SAMD21.
B06/2013Corrected documentation typos. Fixed missing steps in the Basic - * Use Case Quick Start Guide.
A06/2013Initial release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/gclk.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/gclk.c deleted file mode 100644 index 607818c2ede..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/gclk.c +++ /dev/null @@ -1,515 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Generic Clock Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval false if the module has completed synchronization - * \retval true if the module synchronization is ongoing - */ -static inline bool system_gclk_is_syncing(void) -{ - if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) { - return true; - } - - return false; -} - -/** - * \brief Initializes the GCLK driver. - * - * Initializes the Generic Clock module, disabling and resetting all active - * Generic Clock Generators and Channels to their power-on default values. - */ -void system_gclk_init(void) -{ - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK); - - /* Software reset the module to ensure it is re-initialized correctly */ - GCLK->CTRL.reg = GCLK_CTRL_SWRST; - while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) { - /* Wait for reset to complete */ - } -} - -/** - * \brief Writes a Generic Clock Generator configuration to the hardware module. - * - * Writes out a given configuration of a Generic Clock Generator configuration - * to the hardware module. - * - * \note Changing the clock source on the fly (on a running - * generator) can take additional time if the clock source is configured - * to only run on-demand (ONDEMAND bit is set) and it is not currently - * running (no peripheral is requesting the clock source). In this case - * the GCLK will request the new clock while still keeping a request to - * the old clock source until the new clock source is ready. - * - * \note This function will not start a generator that is not already running; - * to start the generator, call \ref system_gclk_gen_enable() - * after configuring a generator. - * - * \param[in] generator Generic Clock Generator index to configure - * \param[in] config Configuration settings for the generator - */ -void system_gclk_gen_set_config( - const uint8_t generator, - struct system_gclk_gen_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Cache new register configurations to minimize sync requirements. */ - uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos); - uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos); - - /* Select the requested source clock for the generator */ - new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos; - - /* Configure the clock to be either high or low when disabled */ - if (config->high_when_disabled) { - new_genctrl_config |= GCLK_GENCTRL_OOV; - } - - /* Configure if the clock output to I/O pin should be enabled. */ - if (config->output_enable) { - new_genctrl_config |= GCLK_GENCTRL_OE; - } - - /* Set division factor */ - if (config->division_factor > 1) { - /* Check if division is a power of two */ - if (((config->division_factor & (config->division_factor - 1)) == 0)) { - /* Determine the index of the highest bit set to get the - * division factor that must be loaded into the division - * register */ - - uint32_t div2_count = 0; - - uint32_t mask; - for (mask = (1UL << 1); mask < config->division_factor; - mask <<= 1) { - div2_count++; - } - - /* Set binary divider power of 2 division factor */ - new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos; - new_genctrl_config |= GCLK_GENCTRL_DIVSEL; - } else { - /* Set integer division factor */ - - new_gendiv_config |= - (config->division_factor) << GCLK_GENDIV_DIV_Pos; - - /* Enable non-binary division with increased duty cycle accuracy */ - new_genctrl_config |= GCLK_GENCTRL_IDC; - } - - } - - /* Enable or disable the clock in standby mode */ - if (config->run_in_standby) { - new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY; - } - - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - GCLK->GENDIV.reg = new_gendiv_config; - - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Enables a Generic Clock Generator that was previously configured. - * - * Starts the clock generation of a Generic Clock Generator that was previously - * configured via a call to \ref system_gclk_gen_set_config(). - * - * \param[in] generator Generic Clock Generator index to enable - */ -void system_gclk_gen_enable( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Enable generator */ - GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Disables a Generic Clock Generator that was previously enabled. - * - * Stops the clock generation of a Generic Clock Generator that was previously - * started via a call to \ref system_gclk_gen_enable(). - * - * \param[in] generator Generic Clock Generator index to disable - */ -void system_gclk_gen_disable( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Disable generator */ - GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; - while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) { - /* Wait for clock to become disabled */ - } - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock Generator is enabled. - * - * \param[in] generator Generic Clock Generator index to check - * - * \return The enabled status. - * \retval true The Generic Clock Generator is enabled - * \retval false The Generic Clock Generator is disabled - */ -bool system_gclk_gen_is_enabled( - const uint8_t generator) -{ - bool enabled; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - /* Obtain the enabled status */ - enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); - - system_interrupt_leave_critical_section(); - - return enabled; -} - -/** - * \brief Retrieves the clock frequency of a Generic Clock generator. - * - * Determines the clock frequency (in Hz) of a specified Generic Clock - * generator, used as a source to a Generic Clock Channel module. - * - * \param[in] generator Generic Clock Generator index - * - * \return The frequency of the generic clock generator, in Hz. - */ -uint32_t system_gclk_gen_get_hz( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the appropriate generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Get the frequency of the source connected to the GCLK generator */ - uint32_t gen_input_hz = system_clock_source_get_hz( - (enum system_clock_source)GCLK->GENCTRL.bit.SRC); - - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - - uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL; - - /* Select the appropriate generator division register */ - *((uint8_t*)&GCLK->GENDIV.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - uint32_t divider = GCLK->GENDIV.bit.DIV; - - system_interrupt_leave_critical_section(); - - /* Check if the generator is using fractional or binary division */ - if (!divsel && divider > 1) { - gen_input_hz /= divider; - } else if (divsel) { - gen_input_hz >>= (divider+1); - } - - return gen_input_hz; -} - -/** - * \brief Writes a Generic Clock configuration to the hardware module. - * - * Writes out a given configuration of a Generic Clock configuration to the - * hardware module. If the clock is currently running, it will be stopped. - * - * \note Once called the clock will not be running; to start the clock, - * call \ref system_gclk_chan_enable() after configuring a clock channel. - * - * \param[in] channel Generic Clock channel to configure - * \param[in] config Configuration settings for the clock - * - */ -void system_gclk_chan_set_config( - const uint8_t channel, - struct system_gclk_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Cache the new config to reduce sync requirements */ - uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos); - - /* Select the desired generic clock generator */ - new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos; - - /* Disable generic clock channel */ - system_gclk_chan_disable(channel); - - /* Write the new configuration */ - GCLK->CLKCTRL.reg = new_clkctrl_config; -} - -/** - * \brief Enables a Generic Clock that was previously configured. - * - * Starts the clock generation of a Generic Clock that was previously - * configured via a call to \ref system_gclk_chan_set_config(). - * - * \param[in] channel Generic Clock channel to enable - */ -void system_gclk_chan_enable( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Enable the generic clock */ - GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Disables a Generic Clock that was previously enabled. - * - * Stops the clock generation of a Generic Clock that was previously started - * via a call to \ref system_gclk_chan_enable(). - * - * \param[in] channel Generic Clock channel to disable - */ -void system_gclk_chan_disable( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Sanity check WRTLOCK */ - Assert(!GCLK->CLKCTRL.bit.WRTLOCK); - - /* Switch to known-working source so that the channel can be disabled */ - uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN; - GCLK->CLKCTRL.bit.GEN = 0; - - /* Disable the generic clock */ - GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN; - while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) { - /* Wait for clock to become disabled */ - } - - /* Restore previous configured clock generator */ - GCLK->CLKCTRL.bit.GEN = prev_gen_id; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock channel is enabled. - * - * \param[in] channel Generic Clock Channel index - * - * \return The enabled status. - * \retval true The Generic Clock channel is enabled - * \retval false The Generic Clock channel is disabled - */ -bool system_gclk_chan_is_enabled( - const uint8_t channel) -{ - bool enabled; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - enabled = GCLK->CLKCTRL.bit.CLKEN; - - system_interrupt_leave_critical_section(); - - return enabled; -} - -/** - * \brief Locks a Generic Clock channel from further configuration writes. - * - * Locks a generic clock channel from further configuration writes. It is only - * possible to unlock the channel configuration through a power on reset. - * - * \param[in] channel Generic Clock channel to enable - */ -void system_gclk_chan_lock( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Lock the generic clock */ - GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock channel is locked. - * - * \param[in] channel Generic Clock Channel index - * - * \return The lock status. - * \retval true The Generic Clock channel is locked - * \retval false The Generic Clock channel is not locked - */ -bool system_gclk_chan_is_locked( - const uint8_t channel) -{ - bool locked; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - locked = GCLK->CLKCTRL.bit.WRTLOCK; - - system_interrupt_leave_critical_section(); - - return locked; -} - -/** - * \brief Retrieves the clock frequency of a Generic Clock channel. - * - * Determines the clock frequency (in Hz) of a specified Generic Clock - * channel, used as a source to a device peripheral module. - * - * \param[in] channel Generic Clock Channel index - * - * \return The frequency of the generic clock channel, in Hz. - */ -uint32_t system_gclk_chan_get_hz( - const uint8_t channel) -{ - uint8_t gen_id; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - gen_id = GCLK->CLKCTRL.bit.GEN; - - system_interrupt_leave_critical_section(); - - /* Return the clock speed of the associated GCLK generator */ - return system_gclk_gen_get_hz(gen_id); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock.c deleted file mode 100644 index f9190af4eb8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock.c +++ /dev/null @@ -1,1021 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Clock Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include - - -/** - * \internal - * \brief DFLL-specific data container. - */ -struct _system_clock_dfll_config { - uint32_t control; - uint32_t val; - uint32_t mul; -}; - -/** - * \internal - * \brief DPLL-specific data container. - */ -struct _system_clock_dpll_config { - uint32_t frequency; -}; - - -/** - * \internal - * \brief XOSC-specific data container. - */ -struct _system_clock_xosc_config { - uint32_t frequency; -}; - -/** - * \internal - * \brief System clock module data container. - */ -struct _system_clock_module { - volatile struct _system_clock_dfll_config dfll; - volatile struct _system_clock_dpll_config dpll; - - volatile struct _system_clock_xosc_config xosc; - volatile struct _system_clock_xosc_config xosc32k; -}; - -/** - * \internal - * \brief Internal module instance to cache configuration values. - */ -static struct _system_clock_module _system_clock_inst = { - .dfll = { - .control = 0, - .val = 0, - .mul = 0, - }, - .dpll = { - .frequency = 0, - }, - .xosc = { - .frequency = 0, - }, - .xosc32k = { - .frequency = 0, - }, -}; - -/** - * \internal - * \brief Wait for sync to the DFLL control registers. - */ -static inline void _system_dfll_wait_for_sync(void) -{ - while (!(OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY)) { - /* Wait for DFLL sync */ - } -} - -/** - * \internal - * \brief Wait for sync to the OSC32K control registers. - */ -static inline void _system_osc32k_wait_for_sync(void) -{ - while (!(OSC32KCTRL->STATUS.reg & OSC32KCTRL_STATUS_OSC32KRDY)) { - /* Wait for OSC32K sync */ - } -} - -/** - * \internal - * \brief OSC16M frequency selection. - * Frequency selection can be done only when OSC16M is disabled,thus, - * OSCULP32K is temporarily used as a new clocksource for mainclock . - * - */ -static inline void _system_clock_source_osc16m_freq_sel(void) -{ - struct system_gclk_gen_config gclk_conf; - struct system_clock_source_osc16m_config osc16m_conf; - - /* Select OSCULP32K as new clock source for mainclock temporarily */ - system_gclk_gen_get_config_defaults(&gclk_conf); - gclk_conf.source_clock = SYSTEM_CLOCK_SOURCE_ULP32K; - system_gclk_gen_set_config(GCLK_GENERATOR_0, &gclk_conf); - - /* GCLK0 is enabled after POR */ - - /* Disable OSC16M clock*/ - system_clock_source_disable(SYSTEM_CLOCK_SOURCE_OSC16M); - - /* Switch to new frequency selection and enable OSC16M */ - system_clock_source_osc16m_get_config_defaults(&osc16m_conf); - osc16m_conf.fsel = CONF_CLOCK_OSC16M_FREQ_SEL; - osc16m_conf.on_demand = 0; - osc16m_conf.run_in_standby = CONF_CLOCK_OSC16M_RUN_IN_STANDBY; - system_clock_source_osc16m_set_config(&osc16m_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC16M); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_OSC16M)); - - /* Select OSC16M for mainclock again */ - system_gclk_gen_get_config_defaults(&gclk_conf); - gclk_conf.source_clock = SYSTEM_CLOCK_SOURCE_OSC16M; - system_gclk_gen_set_config(GCLK_GENERATOR_0, &gclk_conf); - if (CONF_CLOCK_OSC16M_ON_DEMAND) { - OSCCTRL->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND; - } -} - -static inline void _system_clock_source_dfll_set_config_errata_9905(void) -{ - - /* Disable ONDEMAND mode while writing configurations */ - OSCCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~OSCCTRL_DFLLCTRL_ONDEMAND; - _system_dfll_wait_for_sync(); - - OSCCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; - OSCCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; - - /* Write full configuration to DFLL control register */ - OSCCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; -} - -/** - * \brief Retrieve the frequency of a clock source. - * - * Determines the current operating frequency of a given clock source. - * - * \param[in] clock_source Clock source to get the frequency of - * - * \returns Frequency of the given clock source, in Hz. - */ -uint32_t system_clock_source_get_hz( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_XOSC: - return _system_clock_inst.xosc.frequency; - - case SYSTEM_CLOCK_SOURCE_OSC16M: - return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - return 32768UL; - - case SYSTEM_CLOCK_SOURCE_ULP32K: - return 32768UL; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - return _system_clock_inst.xosc32k.frequency; - - case SYSTEM_CLOCK_SOURCE_DFLL: - - /* Check if the DFLL has been configured */ - if (!(_system_clock_inst.dfll.control & OSCCTRL_DFLLCTRL_ENABLE)) - return 0; - - /* Make sure that the DFLL module is ready */ - _system_dfll_wait_for_sync(); - - /* Check if operating in closed loop mode */ - if (_system_clock_inst.dfll.control & OSCCTRL_DFLLCTRL_MODE) { - return system_gclk_chan_get_hz(OSCCTRL_GCLK_ID_DFLL48) * - (_system_clock_inst.dfll.mul & 0xffff); - } - - return 48000000UL; - - case SYSTEM_CLOCK_SOURCE_DPLL: - if (!(OSCCTRL->DPLLCTRLA.reg & OSCCTRL_DPLLCTRLA_ENABLE)) { - return 0; - } - - return _system_clock_inst.dpll.frequency; - - default: - return 0; - } -} - -/** - * \brief Configure the internal OSC16M oscillator clock source. - * - * Configures the 16MHz (nominal) internal RC oscillator with the given - * configuration settings. - * - * \note Frequency selection can be done only when OSC16M is disabled. - * - * \param[in] config OSC16M configuration structure containing the new config - */ -void system_clock_source_osc16m_set_config( - struct system_clock_source_osc16m_config *const config) -{ - OSCCTRL_OSC16MCTRL_Type temp = OSCCTRL->OSC16MCTRL; - - /* Use temporary struct to reduce register access */ - temp.bit.FSEL = config->fsel; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - - OSCCTRL->OSC16MCTRL = temp; -} - -/** - * \brief Configure the internal OSC32K oscillator clock source. - * - * Configures the 32KHz (nominal) internal RC oscillator with the given - * configuration settings. - * - * \param[in] config OSC32K configuration structure containing the new config - */ -void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config) -{ - OSC32KCTRL_OSC32K_Type temp = OSC32KCTRL->OSC32K; - - - /* Update settings via a temporary struct to reduce register access */ - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - temp.bit.STARTUP = config->startup_time; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; - - OSC32KCTRL->OSC32K = temp; -} - -/** - * \brief Configure the internal OSCULP32K oscillator clock source. - * - * Configures the Ultra Low Power 32KHz internal RC oscillator with the given - * configuration settings. - * - * \note The OSCULP32K is enabled by default after a Power On Reset (POR) and - * will always run except during POR. - * - * \param[in] config OSCULP32K configuration structure containing the new config - */ -void system_clock_source_osculp32k_set_config( - struct system_clock_source_osculp32k_config *const config) -{ - OSC32KCTRL_OSCULP32K_Type temp = OSC32KCTRL->OSCULP32K; - /* Update settings via a temporary struct to reduce register access */ - temp.bit.WRTLOCK = config->write_once; - OSC32KCTRL->OSCULP32K = temp; -} - -/** - * \brief Configure the external oscillator clock source. - * - * Configures the external oscillator clock source with the given configuration - * settings. - * - * \param[in] config External oscillator configuration structure containing - * the new config - */ -void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config) -{ - OSCCTRL_XOSCCTRL_Type temp = OSCCTRL->XOSCCTRL; - - temp.bit.STARTUP = config->startup_time; - - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } - - temp.bit.AMPGC = config->auto_gain_control; - - /* Set gain if automatic gain control is not selected */ - if (!config->auto_gain_control) { - if (config->frequency <= 2000000) { - temp.bit.GAIN = 0; - } else if (config->frequency <= 4000000) { - temp.bit.GAIN = 1; - } else if (config->frequency <= 8000000) { - temp.bit.GAIN = 2; - } else if (config->frequency <= 16000000) { - temp.bit.GAIN = 3; - } else if (config->frequency <= 30000000) { - temp.bit.GAIN = 4; - } - - } - - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - - /* Store XOSC frequency for internal use */ - _system_clock_inst.xosc.frequency = config->frequency; - - OSCCTRL->XOSCCTRL = temp; -} - -/** - * \brief Configure the XOSC32K external 32KHz oscillator clock source. - * - * Configures the external 32KHz oscillator clock source with the given - * configuration settings. - * - * \param[in] config XOSC32K configuration structure containing the new config - */ -void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config) -{ - OSC32KCTRL_XOSC32K_Type temp = OSC32KCTRL->XOSC32K; - - temp.bit.STARTUP = config->startup_time; - - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } - - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; - - /* Cache the new frequency in case the user needs to check the current - * operating frequency later */ - _system_clock_inst.xosc32k.frequency = config->frequency; - - OSC32KCTRL->XOSC32K = temp; -} - -/** - * \brief Configure the DFLL clock source. - * - * Configures the Digital Frequency Locked Loop clock source with the given - * configuration settings. - * - * \note The DFLL will be running when this function returns, as the DFLL module - * needs to be enabled in order to perform the module configuration. - * - * \param[in] config DFLL configuration structure containing the new config - */ -void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config) -{ - _system_clock_inst.dfll.val = - OSCCTRL_DFLLVAL_COARSE(config->coarse_value) | - OSCCTRL_DFLLVAL_FINE(config->fine_value); - - _system_clock_inst.dfll.control = - (uint32_t)config->wakeup_lock | - (uint32_t)config->stable_tracking | - (uint32_t)config->quick_lock | - (uint32_t)config->chill_cycle | - ((uint32_t)config->on_demand << OSCCTRL_DFLLCTRL_ONDEMAND_Pos) | - ((uint32_t)config->run_in_stanby << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos); - - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - - _system_clock_inst.dfll.mul = - OSCCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | - OSCCTRL_DFLLMUL_FSTEP(config->fine_max_step) | - OSCCTRL_DFLLMUL_MUL(config->multiply_factor); - - /* Enable the closed loop mode */ - _system_clock_inst.dfll.control |= config->loop_mode; - } - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - - _system_clock_inst.dfll.mul = - OSCCTRL_DFLLMUL_MUL(config->multiply_factor); - - /* Enable the USB recovery mode */ - _system_clock_inst.dfll.control |= config->loop_mode | - OSCCTRL_DFLLCTRL_BPLCKC; - } -} - -/** - * \brief Configure the DPLL clock source. - * - * Configures the Digital Phase-Locked Loop clock source with the given - * configuration settings. - * - * \note The DPLL will be running when this function returns, as the DPLL module - * needs to be enabled in order to perform the module configuration. - * - * \param[in] config DPLL configuration structure containing the new config - */ -void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config) -{ - - uint32_t tmpldr; - uint8_t tmpldrfrac; - uint32_t refclk; - - refclk = config->reference_frequency; - - /* Only reference clock REF1 can be divided */ - if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { - refclk = refclk / (2 * (config->reference_divider + 1)); - } - - /* Calculate LDRFRAC and LDR */ - tmpldr = (config->output_frequency << 4) / refclk; - tmpldrfrac = tmpldr & 0x0f; - tmpldr = (tmpldr >> 4) - 1; - - OSCCTRL->DPLLCTRLA.reg = - ((uint32_t)config->on_demand << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) | - ((uint32_t)config->run_in_standby << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos); - - OSCCTRL->DPLLRATIO.reg = - OSCCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | - OSCCTRL_DPLLRATIO_LDR(tmpldr); - - while(OSCCTRL->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) { - } - - OSCCTRL->DPLLCTRLB.reg = - OSCCTRL_DPLLCTRLB_DIV(config->reference_divider) | - ((uint32_t)config->lock_bypass << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | - OSCCTRL_DPLLCTRLB_LTIME(config->lock_time) | - OSCCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | - ((uint32_t)config->wake_up_fast << OSCCTRL_DPLLCTRLB_WUF_Pos) | - ((uint32_t)config->low_power_enable << OSCCTRL_DPLLCTRLB_LPEN_Pos) | - OSCCTRL_DPLLCTRLB_FILTER(config->filter); - - OSCCTRL->DPLLPRESC.reg = OSCCTRL_DPLLPRESC_PRESC(config->prescaler); - while(OSCCTRL->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) { - } - /* - * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) - */ - _system_clock_inst.dpll.frequency = - (refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4; -} - -/** - * \brief Writes the calibration values for a given oscillator clock source. - * - * Writes an oscillator calibration value to the given oscillator control - * registers. The acceptable ranges are: - * - * For OSC32K: - * - 7 bits (max value 128) - * For OSC16MHZ: - * - 8 bits (Max value 255) - * For OSCULP: - * - 5 bits (Max value 32) - * - * \note The frequency range parameter applies only when configuring the 8MHz - * oscillator and will be ignored for the other oscillators. - * - * \param[in] clock_source Clock source to calibrate - * \param[in] calibration_value Calibration value to write - * \param[in] freq_range Frequency range (8MHz oscillator only) - * - * \retval STATUS_OK The calibration value was written - * successfully. - * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock - * source. - */ -enum status_code system_clock_source_write_calibration( - const enum system_clock_source clock_source, - const uint16_t calibration_value, - const uint8_t freq_select) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC16M: - //to enable DSU test mode and add calibration value - return STATUS_OK; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - - if (calibration_value > 128) { - return STATUS_ERR_INVALID_ARG; - } - - _system_osc32k_wait_for_sync(); - OSC32KCTRL->OSC32K.bit.CALIB = calibration_value; - break; - - case SYSTEM_CLOCK_SOURCE_ULP32K: - - if (calibration_value > 32) { - return STATUS_ERR_INVALID_ARG; - } - - OSC32KCTRL->OSCULP32K.bit.CALIB = calibration_value; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - break; - } - - return STATUS_OK; -} - -/** - * \brief Enables a clock source. - * - * Enables a clock source which has been previously configured. - * - * \param[in] clock_source Clock source to enable - * - * \retval STATUS_OK Clock source was enabled successfully and - * is ready - * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this - * device - */ -enum status_code system_clock_source_enable( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC16M: - OSCCTRL->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ENABLE; - return STATUS_OK; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - OSC32KCTRL->OSC32K.reg |= OSC32KCTRL_OSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - OSCCTRL->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - OSC32KCTRL->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control |= OSCCTRL_DFLLCTRL_ENABLE; - _system_clock_source_dfll_set_config_errata_9905(); - break; - - case SYSTEM_CLOCK_SOURCE_DPLL: - OSCCTRL->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; - while(OSCCTRL->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) { - } - break; - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Always enabled */ - return STATUS_OK; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Disables a clock source. - * - * Disables a clock source that was previously enabled. - * - * \param[in] clock_source Clock source to disable - * - * \retval STATUS_OK Clock source was disabled successfully - * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was - * given - */ -enum status_code system_clock_source_disable( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC16M: - OSCCTRL->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - OSC32KCTRL->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - OSCCTRL->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - OSC32KCTRL->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control &= ~OSCCTRL_DFLLCTRL_ENABLE; - OSCCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; - break; - case SYSTEM_CLOCK_SOURCE_DPLL: - OSCCTRL->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; - break; - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; - } - - /** - * \brief Checks if a clock source is ready. - * - * Checks if a given clock source is ready to be used. - * - * \param[in] clock_source Clock source to check if ready - * - * \returns Ready state of the given clock source. - * - * \retval true Clock source is enabled and ready - * \retval false Clock source is disabled or not yet ready - */ - bool system_clock_source_is_ready( - const enum system_clock_source clock_source) -{ - uint32_t mask = 0; - - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC16M: - mask = OSCCTRL_STATUS_OSC16MRDY; - return ((OSCCTRL->STATUS.reg & mask) == mask); - - case SYSTEM_CLOCK_SOURCE_OSC32K: - mask = OSC32KCTRL_STATUS_OSC32KRDY; - return ((OSC32KCTRL->STATUS.reg & mask) == mask); - - case SYSTEM_CLOCK_SOURCE_XOSC: - mask = OSCCTRL_STATUS_XOSCRDY; - return ((OSCCTRL->STATUS.reg & mask) == mask); - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - mask = OSC32KCTRL_STATUS_XOSC32KRDY; - return ((OSC32KCTRL->STATUS.reg & mask) == mask); - - case SYSTEM_CLOCK_SOURCE_DFLL: - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - mask = (OSCCTRL_STATUS_DFLLRDY | - OSCCTRL_STATUS_DFLLLCKF | OSCCTRL_STATUS_DFLLLCKC); - } else { - mask = OSCCTRL_STATUS_DFLLRDY; - } - return ((OSCCTRL->STATUS.reg & mask) == mask); - - case SYSTEM_CLOCK_SOURCE_DPLL: - return ((OSCCTRL->DPLLSTATUS.reg & - (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK)) == - (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK)); - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - return true; - - default: - return false; - } -} - -/* Include some checks for conf_clocks.h validation */ -#include "clock_config_check.h" - -#if !defined(__DOXYGEN__) -/** \internal - * - * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h. - */ -# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \ - if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \ - struct system_gclk_gen_config gclk_conf; \ - system_gclk_gen_get_config_defaults(&gclk_conf); \ - gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \ - gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \ - gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \ - gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \ - system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \ - system_gclk_gen_enable(GCLK_GENERATOR_##n); \ - } - -/** \internal - * - * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h, - * provided that it is not the main Generic Clock Generator channel. - */ -# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \ - if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); } -#endif - -/** - * \brief Initialize clock system based on the configuration in conf_clocks.h. - * - * This function will apply the settings in conf_clocks.h when run from the user - * application. All clock sources and GCLK generators are running when this function - * returns. - * - * \note OSC16M is always enabled and if user selects other clocks for GCLK generators, - * the OSC16M default enable can be disabled after system_clock_init. Make sure the - * clock switches successfully before disabling OSC8M. - */ -void system_clock_init(void) -{ - /* Various bits in the INTFLAG register can be set to one at startup. - This will ensure that these bits are cleared */ - OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; - SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY | SUPC_INTFLAG_BOD33DET; - - system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); - - /* Switch to PL2 to be sure configuration of GCLK0 is safe */ - system_switch_performance_level(SYSTEM_PERFORMANCE_LEVEL_2); - - /* XOSC */ -#if CONF_CLOCK_XOSC_ENABLE == true - struct system_clock_source_xosc_config xosc_conf; - system_clock_source_xosc_get_config_defaults(&xosc_conf); - - xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; - xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; - xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; - xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; - xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; - xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; - - system_clock_source_xosc_set_config(&xosc_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); -#endif - - /* XOSC32K */ -#if CONF_CLOCK_XOSC32K_ENABLE == true - struct system_clock_source_xosc32k_config xosc32k_conf; - system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); - - xosc32k_conf.frequency = 32768UL; - xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; - xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; - xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; - xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; - xosc32k_conf.on_demand = false; - xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; - - system_clock_source_xosc32k_set_config(&xosc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); - if (CONF_CLOCK_XOSC32K_ON_DEMAND) { - OSC32KCTRL->XOSC32K.bit.ONDEMAND = 1; - } -#endif - - /* OSCK32K */ -#if CONF_CLOCK_OSC32K_ENABLE == true - - struct system_clock_source_osc32k_config osc32k_conf; - system_clock_source_osc32k_get_config_defaults(&osc32k_conf); - - osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; - osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; - osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; - osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; - osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; - - system_clock_source_osc32k_set_config(&osc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); -#endif - - /* OSC16M */ - if (CONF_CLOCK_OSC16M_FREQ_SEL == SYSTEM_OSC16M_4M) { - OSCCTRL->OSC16MCTRL.bit.ONDEMAND = CONF_CLOCK_OSC16M_ON_DEMAND ; - OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = CONF_CLOCK_OSC16M_RUN_IN_STANDBY; - } else { - _system_clock_source_osc16m_freq_sel(); - } - - /* DFLL Config (Open and Closed Loop) */ -#if CONF_CLOCK_DFLL_ENABLE == true - struct system_clock_source_dfll_config dfll_conf; - system_clock_source_dfll_get_config_defaults(&dfll_conf); - - dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; - dfll_conf.on_demand = false; - dfll_conf.run_in_stanby = CONF_CLOCK_DFLL_RUN_IN_STANDBY; - - /* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping - in DFLL.COARSE helps to output a frequency close to 48 MHz.*/ -#define NVM_DFLL_COARSE_POS 26 /* DFLL48M Coarse calibration value bit position.*/ -#define NVM_DFLL_COARSE_SIZE 6 /* DFLL48M Coarse calibration value bit size.*/ - - uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP5) - + (NVM_DFLL_COARSE_POS / 32)) - >> (NVM_DFLL_COARSE_POS % 32)) - & ((1 << NVM_DFLL_COARSE_SIZE) - 1); - /* In some revision chip, the Calibration value is not correct */ - if (coarse == 0x3f) { - coarse = 0x1f; - } - - dfll_conf.coarse_value = coarse; - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { - dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; - } - -# if CONF_CLOCK_DFLL_QUICK_LOCK == true - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; -# else - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; -# endif - -# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; -# else - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; -# endif - -# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; -# else - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; -# endif - -# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; -# else - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; -# endif - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; - } - - dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; - dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - dfll_conf.fine_value = 0x1ff; - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; - - dfll_conf.multiply_factor = 48000; - } - - system_clock_source_dfll_set_config(&dfll_conf); -#endif - - /* GCLK */ -#if CONF_CLOCK_CONFIGURE_GCLK == true - system_gclk_init(); - - /* Configure all GCLK generators except for the main generator, which - * is configured later after all other clock systems are set up */ - MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); -# if CONF_CLOCK_DFLL_ENABLE == true - /* Enable DFLL reference clock if in closed loop mode */ - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - struct system_gclk_chan_config dfll_gclk_chan_conf; - - system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); - dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; - system_gclk_chan_set_config(OSCCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); - system_gclk_chan_enable(OSCCTRL_GCLK_ID_DFLL48); - } -# endif - -# if CONF_CLOCK_DPLL_ENABLE == true - /* Enable DPLL internal lock timer and reference clock */ - struct system_gclk_chan_config dpll_gclk_chan_conf; - system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf); - if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) { - dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR; - system_gclk_chan_set_config(OSCCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf); - system_gclk_chan_enable(OSCCTRL_GCLK_ID_FDPLL32K); - } - - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { - dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR; - system_gclk_chan_set_config(OSCCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf); - system_gclk_chan_enable(OSCCTRL_GCLK_ID_FDPLL); - } -# endif -#endif - - /* DFLL Enable (Open and Closed Loop) */ -#if CONF_CLOCK_DFLL_ENABLE == true - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); - if (CONF_CLOCK_DFLL_ON_DEMAND) { - OSCCTRL->DFLLCTRL.bit.ONDEMAND = 1; - } -#endif - - /* DPLL */ -# if (CONF_CLOCK_DPLL_ENABLE == true) - - /* Enable DPLL reference clock */ - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) { - /* XOSC32K should have been enabled for GCLK_XOSC32 */ - Assert(CONF_CLOCK_XOSC32K_ENABLE); - } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { - /* XOSC should have been enabled for GCLK_XOSC */ - Assert(CONF_CLOCK_XOSC_ENABLE); - } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { - /* GCLK should have been enabled */ - Assert(CONF_CLOCK_CONFIGURE_GCLK); - } else { - Assert(false); - } - - struct system_clock_source_dpll_config dpll_config; - system_clock_source_dpll_get_config_defaults(&dpll_config); - - dpll_config.on_demand = false; - dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; - dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; - dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; - dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; - - dpll_config.filter = CONF_CLOCK_DPLL_FILTER; - dpll_config.lock_time = CONF_CLOCK_DPLL_LOCK_TIME; - - dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; - dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; - dpll_config.reference_divider = CONF_CLOCK_DPLL_REFERENCE_DIVIDER; - dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; - dpll_config.prescaler = CONF_CLOCK_DPLL_PRESCALER; - - system_clock_source_dpll_set_config(&dpll_config); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); - if (CONF_CLOCK_DPLL_ON_DEMAND) { - OSCCTRL->DPLLCTRLA.bit.ONDEMAND = 1; - } - -# endif - - /* CPU and BUS clocks */ - system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); - system_main_clock_set_failure_detect(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT); - system_low_power_clock_set_divider(CONF_CLOCK_LOW_POWER_DIVIDER); - system_backup_clock_set_divider(CONF_CLOCK_BACKUP_DIVIDER); - - /* GCLK 0 */ -#if CONF_CLOCK_CONFIGURE_GCLK == true - /* Configure the main GCLK last as it might depend on other generators */ - _CONF_CLOCK_GCLK_CONFIG(0, ~); -#endif - - /* If CPU frequency is less than 12MHz, scale down performance level to PL0 */ - uint32_t cpu_freq = system_cpu_clock_get_hz(); - if (cpu_freq <= 12000000) { - system_switch_performance_level(SYSTEM_PERFORMANCE_LEVEL_0); - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_config_check.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_config_check.h deleted file mode 100644 index 62156d81261..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_config_check.h +++ /dev/null @@ -1,459 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Clock Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CLOCK_CONFIG_CHECK_H -# define CLOCK_CONFIG_CHECK_H - -#if !defined(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT) -# error CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_FLASH_WAIT_STATES) -# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_CPU_DIVIDER) -# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_LOW_POWER_DIVIDER) -# error CONF_CLOCK_LOW_POWER_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_BACKUP_DIVIDER) -# error CONF_CLOCK_BACK_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC16M_FREQ_SEL) -# error CONF_CLOCK_OSC16M_FREQ_SEL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC16M_ON_DEMAND) -# error CONF_CLOCK_OSC16M_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC16M_RUN_IN_STANDBY) -# error CONF_CLOCK_OSC16M_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_ENABLE) -# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL) -# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY) -# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME) -# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) -# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_ON_DEMAND) -# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY) -# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE) -# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL) -# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME) -# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT) -# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT) -# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND) -# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY) -# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE) -# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME) -# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT) -# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT) -# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND) -# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY) -# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ENABLE) -# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_LOOP_MODE) -# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ON_DEMAND) -# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_FINE_VALUE) -# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_RUN_IN_STANDBY) -# error CONF_CLOCK_DFLL_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR) -# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR) -# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK) -# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK) -# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP) -# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE) -# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE) -# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE) -# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_ENABLE) -# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_ON_DEMAND) -# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY) -# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS) -# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST) -# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE) -# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_TIME) -# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK) -# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_FILTER) -# error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY) -# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER) -# error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY) -# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_PRESCALER) -# error CONF_CLOCK_DPLL_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR) -# error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR) -# error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h -#endif - - -#if !defined(CONF_CLOCK_CONFIGURE_GCLK) -# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_ENABLE) -# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_PRESCALER) -# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_ENABLE) -# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_PRESCALER) -# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_ENABLE) -# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_PRESCALER) -# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_ENABLE) -# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_PRESCALER) -# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_ENABLE) -# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_PRESCALER) -# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_ENABLE) -# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_PRESCALER) -# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_ENABLE) -# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_PRESCALER) -# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_ENABLE) -# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_PRESCALER) -# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_ENABLE) -# error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_PRESCALER) -# error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#endif /* CLOCK_CONFIG_CHECK_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_feature.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_feature.h deleted file mode 100644 index 79abcf751c1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_feature.h +++ /dev/null @@ -1,1488 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Clock Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED -#define SYSTEM_CLOCK_FEATURE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management (SYSTEM CLOCK) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the device's clocking related functions. This includes - * the various clock sources, bus clocks, and generic clocks within the device, - * with functions to manage the enabling, disabling, source selection, and - * prescaling of clocks to various internal peripherals. - * - * The following peripherals are used by this module: - * - * - GCLK (Generic Clock Management) - * - PM (Power Management) - * - OSCCTRL (Oscillators Controller) - * - OSC32KCTRL (32K Oscillators Controller) - * - MCLK (Main Clock) - * - * The following devices can use this module: - * - Atmel | SMART SAM L21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_clock_prerequisites - * - \ref asfdoc_sam0_system_clock_module_overview - * - \ref asfdoc_sam0_system_clock_special_considerations - * - \ref asfdoc_sam0_system_clock_extra_info - * - \ref asfdoc_sam0_system_clock_examples - * - \ref asfdoc_sam0_system_clock_api_overview - * - * - * \section asfdoc_sam0_system_clock_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_clock_module_overview Module Overview - * The SAM devices contain a sophisticated clocking system, which is designed - * to give the maximum flexibility to the user application. This system allows - * a system designer to tune the performance and power consumption of the device - * in a dynamic manner, to achieve the best trade-off between the two for a - * particular application. - * - * This driver provides a set of functions for the configuration and management - * of the various clock related functionalities within the device. - * - * - * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources - * The SAM devices have a number of master clock source modules, each of - * which being capable of producing a stabilized output frequency which can then - * be fed into the various peripherals and modules within the device. - * - * Possible clock source modules include internal R/C oscillators, internal - * DFLL modules, as well as external crystal oscillators and/or clock inputs. - * - * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks - * The CPU and AHB/APBx buses are clocked by the same physical clock source - * (referred in this module as the Main Clock). - * The CPU and bus clocks are divided into a number of clock domains. Each clock domain can - * run at different frequencies. - * - * There are three clock domains: - * - * - CPU Clock Domain - * - Low Power Clock Domain(LP Clock Domain) - * - Backup Clock Domain(BUP Clock Domain) - * - * Each clock domain (CPU, LP, BUP) can be changed on the fly. To ensure - * correct operation, frequencies must be selected so that BUPDIV ≥ LPDIV ≥ HSDIV. - * Also, frequencies must never exceed the specified maximum frequency for each clock domain. - * A module may be connected to several clock domains (for instance, AHB and APB). - * - * The general main clock tree for the CPU and associated buses is shown in - * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below". - * - * \anchor asfdoc_sam0_system_clock_module_clock_tree - * \dot - * digraph overview { - * rankdir=LR; - * clk_src [label="Clock Sources", shape=none, height=0]; - * node [label="CPU Bus" shape=ellipse] cpu_bus; - * node [label="AHB Bus" shape=ellipse] ahb_bus; - * node [label="APBx Bus" shape=ellipse] apb_bus; - * node [label="Main Bus\nPrescaler" shape=square] main_prescaler; - * node [label="CPU Clock\nPrescaler" shape=square] cpu_prescaler; - * node [label="Low Power Clock\nPrescaler" shape=square] low_power_prescaler; - * node [label="Backup clock\nPrescaler" shape=square] backup_prescaler; - * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux; - * - * clk_src -> main_clock_mux; - * main_clock_mux -> main_prescaler; - * main_prescaler -> cpu_prescaler; - * main_prescaler -> low_power_prescaler; - * main_prescaler -> backup_prescaler; - * cpu_prescaler -> cpu_bus; - * cpu_prescaler -> ahb_bus; - * cpu_prescaler -> apb_bus; - * low_power_prescaler -> ahb_bus; - * low_power_prescaler -> apb_bus; - * backup_prescaler -> apb_bus; - * } - * \enddot - * - * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking - * To save power, the input clock to one or more peripherals on the AHB and APBx - * buses can be masked away. When masked, no clock is passed into the module. - * Disabling of clocks of unused modules will prevent all access to the masked - * module, but will reduce the overall device power consumption. - * - * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks - * Within the SAM devices are a number of Generic Clocks; these are used to - * provide clocks to the various peripheral clock domains in the device in a - * standardized manner. One or more master source clocks can be selected as the - * input clock to a Generic Clock Generator, which can prescale down the input - * frequency to a slower rate for use in a peripheral. - * - * Additionally, a number of individually selectable Generic Clock Channels are - * provided, which multiplex and gate the various generator outputs for one or - * more peripherals within the device. This setup allows for a single common - * generator to feed one or more channels, which can then be enabled or disabled - * individually as required. - * - * \anchor asfdoc_sam0_system_clock_module_chain_overview - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Clock\nSource a" shape=square] system_clock_source; - * node [label="Generator n" shape=square] clock_gen; - * node [label="Channel x" shape=square] clock_chan0; - * node [label="Channel y" shape=square] clock_chan1; - * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0; - * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1; - * - * system_clock_source -> clock_gen; - * clock_gen -> clock_chan0; - * clock_chan0 -> peripheral0; - * clock_gen -> clock_chan1; - * clock_chan1 -> peripheral1; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example - * An example setup of a complete clock chain within the device is shown in - * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below". - * - * \anchor asfdoc_sam0_system_clock_module_chain_example_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="External\nOscillator" shape=square] system_clock_source0; - * node [label="Generator 0" shape=square] clock_gen0; - * node [label="Channel x" shape=square] clock_chan0; - * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0; - * - * system_clock_source0 -> clock_gen0; - * clock_gen0 -> clock_chan0; - * clock_chan0 -> peripheral0; - * node [label="16MHz R/C\nOscillator (OSC16M)" shape=square fillcolor=white] system_clock_source1; - * node [label="Generator 1" shape=square] clock_gen1; - * node [label="Channel y" shape=square] clock_chan1; - * node [label="Channel z" shape=square] clock_chan2; - * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1; - * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2; - * - * system_clock_source1 -> clock_gen1; - * clock_gen1 -> clock_chan1; - * clock_gen1 -> clock_chan2; - * clock_chan1 -> peripheral1; - * clock_chan2 -> peripheral2; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators - * Each Generic Clock generator within the device can source its input clock - * from one of the provided Source Clocks, and prescale the output for one or - * more Generic Clock Channels in a one-to-many relationship. The generators - * thus allow for several clocks to be generated of different frequencies, - * power usages, and accuracies, which can be turned on and off individually to - * disable the clocks to multiple peripherals as a group. - * - * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels - * To connect a Generic Clock Generator to a peripheral within the - * device, a Generic Clock Channel is used. Each peripheral or - * peripheral group has an associated Generic Clock Channel, which serves as the - * clock input for the peripheral(s). To supply a clock to the peripheral - * module(s), the associated channel must be connected to a running Generic - * Clock Generator and the channel enabled. - * - * \section asfdoc_sam0_system_clock_special_considerations Special Considerations - * - * There are no special considerations for this module. - * - * - * \section asfdoc_sam0_system_clock_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes: - * - \ref asfdoc_sam0_system_clock_extra_acronyms - * - \ref asfdoc_sam0_system_clock_extra_dependencies - * - \ref asfdoc_sam0_system_clock_extra_errata - * - \ref asfdoc_sam0_system_clock_extra_history - * - * - * \section asfdoc_sam0_system_clock_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_system_clock_exqsg. - * - * - * \section asfdoc_sam0_system_clock_api_overview API Overview - * @{ - */ - -#include -#include - - - -/** - * \brief Available start-up times for the XOSC32K. - * - * Available external 32KHz oscillator start-up times, as a number of external - * clock cycles. - */ -enum system_xosc32k_startup { - /** Wait 2048 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_4096, - /** Wait 16384 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_32768, - /** Wait 65536 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_65536, - /** Wait 131072 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_131072, - /** Wait 262144 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_262144, -}; - -/** - * \brief Available start-up times for the XOSC. - * - * Available external oscillator start-up times, as a number of external clock - * cycles. - */ -enum system_xosc_startup { - /** Wait one clock cycle until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_1, - /** Wait two clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_2, - /** Wait four clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_4, - /** Wait eight clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_8, - /** Wait 16 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_16, - /** Wait 32 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_32, - /** Wait 64 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_64, - /** Wait 128 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_128, - /** Wait 256 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_256, - /** Wait 512 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_512, - /** Wait 1024 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_1024, - /** Wait 2048 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_4096, - /** Wait 8192 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_8192, - /** Wait 16384 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_32768, -}; - -/** - * \brief Available start-up times for the OSC32K. - * - * Available internal 32KHz oscillator start-up times, as a number of internal - * OSC32K clock cycles. - */ -enum system_osc32k_startup { - /** Wait three clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_3, - /** Wait four clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_4, - /** Wait six clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_6, - /** Wait ten clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_10, - /** Wait 18 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_18, - /** Wait 34 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_34, - /** Wait 66 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_66, - /** Wait 130 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_130, -}; - -/** - * \brief Frequency selection for the internal 16MHz system clock. - * - * Available frequency selection for the internal 16MHz (nominal) system clock. - */ -enum system_osc16m_fsel { - /** Frequency Selection 4MHz */ - SYSTEM_OSC16M_4M, - /** Frequency Selection 8MHz */ - SYSTEM_OSC16M_8M, - /** Frequency Selection 12MHz */ - SYSTEM_OSC16M_12M, - /** Frequency Selection 16MHz */ - SYSTEM_OSC16M_16M, -}; - - - -/** - * \brief Main CPU, Lowpower and Backup clock division. - * - * Available division ratios for the CPU and Lowpower and Backup clocks. - */ -enum system_main_clock_div { - /** Divide Main clock by one */ - SYSTEM_MAIN_CLOCK_DIV_1, - /** Divide Main clock by two */ - SYSTEM_MAIN_CLOCK_DIV_2, - /** Divide Main clock by four */ - SYSTEM_MAIN_CLOCK_DIV_4, - /** Divide Main clock by eight */ - SYSTEM_MAIN_CLOCK_DIV_8, - /** Divide Main clock by 16 */ - SYSTEM_MAIN_CLOCK_DIV_16, - /** Divide Main clock by 32 */ - SYSTEM_MAIN_CLOCK_DIV_32, - /** Divide Main clock by 64 */ - SYSTEM_MAIN_CLOCK_DIV_64, - /** Divide Main clock by 128 */ - SYSTEM_MAIN_CLOCK_DIV_128, -}; - -/** - * \brief External clock source types. - * - * Available external clock source types. - */ -enum system_clock_external { - /** The external clock source is a crystal oscillator */ - SYSTEM_CLOCK_EXTERNAL_CRYSTAL, - /** The connected clock source is an external logic level clock signal */ - SYSTEM_CLOCK_EXTERNAL_CLOCK, -}; - -/** - * \brief Operating modes of the DFLL clock source. - * - * Available operating modes of the DFLL clock source module. - */ -enum system_clock_dfll_loop_mode { - /** The DFLL is operating in open loop mode with no feedback */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, - /** The DFLL is operating in closed loop mode with frequency feedback from - * a low frequency reference clock - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = OSCCTRL_DFLLCTRL_MODE, - -#ifdef OSCCTRL_DFLLCTRL_USBCRM - /** The DFLL is operating in USB recovery mode with frequency feedback - * from USB SOF - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = OSCCTRL_DFLLCTRL_USBCRM, -#endif -}; - -/** - * \brief Locking behavior for the DFLL during device wake-up. - * - * DFLL lock behavior modes on device wake-up from sleep. - */ -enum system_clock_dfll_wakeup_lock { - /** Keep DFLL lock when the device wakes from sleep */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, - /** Lose DFLL lock when the devices wakes from sleep */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = OSCCTRL_DFLLCTRL_LLAW, -}; - -/** - * \brief Fine tracking behavior for the DFLL once a lock has been acquired. - * - * DFLL fine tracking behavior modes after a lock has been acquired. - */ -enum system_clock_dfll_stable_tracking { - /** Keep tracking after the DFLL has gotten a fine lock */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, - /** Stop tracking after the DFLL has gotten a fine lock */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = OSCCTRL_DFLLCTRL_STABLE, -}; - -/** - * \brief Chill cycle behavior of the DFLL module. - * - * DFLL chill cycle behavior modes of the DFLL module. A chill cycle is a period - * of time when the DFLL output frequency is not measured by the unit, to allow - * the output to stabilize after a change in the input clock source. - */ -enum system_clock_dfll_chill_cycle { - /** Enable a chill cycle, where the DFLL output frequency is not measured */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, - /** Disable a chill cycle, where the DFLL output frequency is not measured */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = OSCCTRL_DFLLCTRL_CCDIS, -}; - -/** - * \brief QuickLock settings for the DFLL module. - * - * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of - * the DFLL output frequency at the expense of accuracy. - */ -enum system_clock_dfll_quick_lock { - /** Enable the QuickLock feature for looser lock requirements on the DFLL */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, - /** Disable the QuickLock feature for strict lock requirements on the DFLL */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = OSCCTRL_DFLLCTRL_QLDIS, -}; - -/** - * \brief Available clock sources in the system. - * - * Clock sources available to the GCLK generators - */ -enum system_clock_source { - /** Internal 16MHz RC oscillator */ - SYSTEM_CLOCK_SOURCE_OSC16M = GCLK_SOURCE_OSC16M, - /** Internal 32KHz RC oscillator */ - SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K, - /** External oscillator */ - SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC , - /** External 32KHz oscillator */ - SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K, - /** Digital Frequency Locked Loop (DFLL) */ - SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M, - /** Internal Ultra Low Power 32KHz oscillator */ - SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K, - /** Generator input pad */ - SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN, - /** Generic clock generator one output */ - SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1, - - /** Digital Phase Locked Loop (DPLL) */ - SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL, -}; - -/** - * \brief List of APB peripheral buses. - * - * Available bus clock domains on the APB bus. - */ -enum system_clock_apb_bus { - /** Peripheral bus A on the APB bus */ - SYSTEM_CLOCK_APB_APBA, - /** Peripheral bus B on the APB bus */ - SYSTEM_CLOCK_APB_APBB, - /** Peripheral bus C on the APB bus */ - SYSTEM_CLOCK_APB_APBC, - /** Peripheral bus D on the APB bus */ - SYSTEM_CLOCK_APB_APBD, - /** Peripheral bus E on the APB bus */ - SYSTEM_CLOCK_APB_APBE, -}; - -/** - * \brief Configuration structure for XOSC. - * - * External oscillator clock configuration structure. - */ -struct system_clock_source_xosc_config { - /** External clock type */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time */ - enum system_xosc_startup startup_time; - /** Enable automatic amplitude gain control */ - bool auto_gain_control; - /** External clock/crystal frequency */ - uint32_t frequency; - /** Keep the XOSC enabled in standby sleep mode */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC won't run - * until requested by a peripheral */ - bool on_demand; -}; - -/** - * \brief Configuration structure for XOSC32K. - * - * External 32KHz oscillator clock configuration structure. - */ -struct system_clock_source_xosc32k_config { - /** External clock type */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time */ - enum system_xosc32k_startup startup_time; - /** Enable 1KHz output */ - bool enable_1khz_output; - /** Enable 32KHz output */ - bool enable_32khz_output; - /** External clock/crystal frequency */ - uint32_t frequency; - /** Keep the XOSC32K enabled in standby sleep mode */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC32K won't run - * until requested by a peripheral */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock */ - bool write_once; -}; - -/** - * \brief Configuration structure for OSC16M. - * - * Internal 16MHz (nominal) oscillator configuration structure. - */ -struct system_clock_source_osc16m_config { - /** Internal 16MHz RC oscillator prescaler */ - enum system_osc16m_fsel fsel; - /** Keep the OSC16M enabled in standby sleep mode */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC16M won't run - * until requested by a peripheral */ - bool on_demand; -}; - -/** - * \brief Configuration structure for OSCULP32K. - * - * Internal 32KHz Ultra Low Power oscillator configuration structure. - */ -struct system_clock_source_osculp32k_config { - /** Lock configuration after it has been written, - * a device reset will release the lock */ - bool write_once; -}; - -/** - * \brief Configuration structure for OSCULP32K. - * - * Internal 32KHz oscillator configuration structure. - */ -struct system_clock_source_osc32k_config { - /** Start-up time */ - enum system_osc32k_startup startup_time; - /** Enable 1KHz output */ - bool enable_1khz_output; - /** Enable 32KHz output */ - bool enable_32khz_output; - /** Keep the OSC32K enabled in standby sleep mode */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC32K won't run - * until requested by a peripheral */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock */ - bool write_once; -}; - -/** - * \brief Configuration structure for DFLL. - * - * DFLL oscillator configuration structure. - */ -struct system_clock_source_dfll_config { - /** Loop mode */ - enum system_clock_dfll_loop_mode loop_mode; - /** Run On Demand. If this is set the DFLL won't run - * until requested by a peripheral */ - bool on_demand; - /** Run in stanby*/ - bool run_in_stanby; - /** Enable quick lock */ - enum system_clock_dfll_quick_lock quick_lock; - /** Enable chill cycle */ - enum system_clock_dfll_chill_cycle chill_cycle; - /** DFLL lock state on wakeup */ - enum system_clock_dfll_wakeup_lock wakeup_lock; - /** DFLL tracking after fine lock */ - enum system_clock_dfll_stable_tracking stable_tracking; - /** Coarse calibration value (Open loop mode) */ - uint8_t coarse_value; - /** Fine calibration value (Open loop mode) */ - uint16_t fine_value; - /** Coarse adjustment maximum step size (Closed loop mode) */ - uint8_t coarse_max_step; - /** Fine adjustment maximum step size (Closed loop mode) */ - uint16_t fine_max_step; - /** DFLL multiply factor (Closed loop mode) */ - uint16_t multiply_factor; -}; - -/** - * \name External Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for XOSC. - * - * Fills a configuration structure with the default configuration for an - * external oscillator module: - * - External Crystal - * - Start-up time of 16384 external clock cycles - * - Automatic crystal gain control mode enabled - * - Frequency of 12MHz - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_xosc_get_config_defaults( - struct system_clock_source_xosc_config *const config) -{ - Assert(config); - - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC_STARTUP_16384; - config->auto_gain_control = true; - config->frequency = 12000000UL; - config->run_in_standby = false; - config->on_demand = true; -} - -void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config); - -/** - * @} - */ - - -/** - * \name External 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for XOSC32K. - * - * Fills a configuration structure with the default configuration for an - * external 32KHz oscillator module: - * - External Crystal - * - Start-up time of 16384 external clock cycles - * - Automatic crystal gain control mode disabled - * - Frequency of 32.768KHz - * - 1KHz clock output disabled - * - 32KHz clock output enabled - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - Don't lock registers after configuration has been written - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_xosc32k_get_config_defaults( - struct system_clock_source_xosc32k_config *const config) -{ - Assert(config); - - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC32K_STARTUP_16384; - config->frequency = 32768UL; - config->enable_1khz_output = false; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->write_once = false; -} - -void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config); -/** - * @} - */ - - -/** - * \name Internal 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSC32K. - * - * Fills a configuration structure with the default configuration for an - * internal 32KHz oscillator module: - * - 1KHz clock output enabled - * - 32KHz clock output enabled - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - Set start-up time to 130 cycles - * - Don't lock registers after configuration has been written - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osc32k_get_config_defaults( - struct system_clock_source_osc32k_config *const config) -{ - Assert(config); - - config->enable_1khz_output = true; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->startup_time = SYSTEM_OSC32K_STARTUP_130; - config->write_once = false; -} - -void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config); - -/** - * @} - */ - -/** - * \name Internal Ultra Low Power 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSCULP32K. - * - * Fills a configuration structure with the default configuration for an - * internal Ultra Low Power 32KHz oscillator module: - * - 1KHz clock output enabled - * - 32KHz clock output enabled - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osculp32k_get_config_defaults( - struct system_clock_source_osculp32k_config *const config) -{ - Assert(config); - - config->write_once = false; -} - -void system_clock_source_osculp32k_set_config( - struct system_clock_source_osculp32k_config *const config); - -/** - * @} - */ - - -/** - * \name Internal 16MHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSC16M. - * - * Fills a configuration structure with the default configuration for an - * internal 16MHz (nominal) oscillator module: - * - Clock output frequency select 4MHz - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osc16m_get_config_defaults( - struct system_clock_source_osc16m_config *const config) -{ - Assert(config); - - config->fsel = SYSTEM_OSC16M_4M; - config->run_in_standby = false; - config->on_demand = true; -} - -void system_clock_source_osc16m_set_config( - struct system_clock_source_osc16m_config *const config); - -/** - * @} - */ - - -/** - * \name Internal DFLL Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for DFLL. - * - * Fills a configuration structure with the default configuration for a - * DFLL oscillator module: - * - Open loop mode - * - QuickLock mode enabled - * - Chill cycle enabled - * - Output frequency lock maintained during device wake-up - * - Continuous tracking of the output frequency - * - Default tracking values at the mid-points for both coarse and fine - * tracking parameters - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_dfll_get_config_defaults( - struct system_clock_source_dfll_config *const config) -{ - Assert(config); - - config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN; - config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; - config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; - config->on_demand = true; - config->run_in_stanby = false; - - /* Open loop mode calibration value */ - config->coarse_value = 0x1f / 4; /* Midpoint */ - config->fine_value = 0xff / 4; /* Midpoint */ - - /* Closed loop mode */ - config->coarse_max_step = 1; - config->fine_max_step = 1; - config->multiply_factor = 12; /* Multiply 4MHz by 12 to get 48MHz */ -} - -void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config); - -/** - * @} - */ - -/** - * \name Clock Source Management - * @{ - */ -enum status_code system_clock_source_write_calibration( - const enum system_clock_source system_clock_source, - const uint16_t calibration_value, - const uint8_t freq_range); - -enum status_code system_clock_source_enable( - const enum system_clock_source system_clock_source); - -enum status_code system_clock_source_disable( - const enum system_clock_source clk_source); - -bool system_clock_source_is_ready( - const enum system_clock_source clk_source); - -uint32_t system_clock_source_get_hz( - const enum system_clock_source clk_source); - -/** - * @} - */ - -/** - * \name Main Clock Management - * @{ - */ - -/** - * \brief Enable or disable the main clock failure detection. - * - * This mechanism allows switching automatically the main clock to the safe - * RCSYS clock, when the main clock source is considered off. - * - * This may happen for instance when an external crystal is selected as the - * clock source of the main clock and the crystal dies. The mechanism is to - * detect, during a RCSYS period, at least one rising edge of the main clock. - * If no rising edge is seen the clock is considered failed. - * As soon as the detector is enabled, the clock failure detector - * (CFD) will monitor the divided main clock. When a clock failure is detected, - * the main clock automatically switches to the RCSYS clock and the CFD - * interrupt is generated if enabled. - * - * \note The failure detect must be disabled if the system clock is the same or - * slower than 32KHz as it will believe the system clock has failed with - * a too slow clock. - * - * \param[in] enable Boolean \c true to enable, \c false to disable detection - */ -static inline void system_main_clock_set_failure_detect( - const bool enable) -{ - if (enable) { - MCLK->CTRLA.reg |= MCLK_CTRLA_CFDEN; - } else { - MCLK->CTRLA.reg &= ~MCLK_CTRLA_CFDEN; - } -} - -/** - * \brief Set main CPU clock divider. - * - * Sets the clock divider used on the main clock to provide the CPU clock. - * - * \param[in] divider CPU clock divider to set - */ -static inline void system_cpu_clock_set_divider( - const enum system_main_clock_div divider) -{ - Assert(((uint32_t)divider & MCLK_CPUDIV_CPUDIV_Msk) == divider); - MCLK->CPUDIV.reg = (uint32_t)divider; - -} - -/** - * \brief Set Low-Power Clock divider. - * - * Sets the clock divider used on the main clock to provide the CPU clock. - * - * \param[in] divider CPU clock divider to set - */ -static inline void system_low_power_clock_set_divider( - const enum system_main_clock_div divider) -{ - Assert(((uint32_t)divider & MCLK_LPDIV_LPDIV_Msk) == divider); - MCLK->LPDIV.reg = (uint32_t)divider; - -} - -/** - * \brief Set Backup Clock divider. - * - * Sets the clock divider used on the main clock to provide the CPU clock. - * - * \param[in] divider CPU clock divider to set - */ -static inline void system_backup_clock_set_divider( - const enum system_main_clock_div divider) -{ - Assert(((uint32_t)divider & MCLK_BUPDIV_BUPDIV_Msk) == divider); - MCLK->BUPDIV.reg = (uint32_t)divider; - -} - - -/** - * \brief Retrieves the current frequency of the CPU core. - * - * Retrieves the operating frequency of the CPU core, obtained from the main - * generic clock and the set CPU bus divider. - * - * \return Current CPU frequency in Hz. - */ -static inline uint32_t system_cpu_clock_get_hz(void) -{ - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1)); - -} - -/** - * \brief Retrieves the current frequency of Low-Power clock. - * - * Retrieves the operating frequency of Low-Power, obtained from Low-Power - * clock and the set Low-Power clock divider. - * - * \return Current CPU frequency in Hz. - */ -static inline uint32_t system_low_power_clock_get_hz(void) -{ - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->LPDIV.reg - 1)); - -} - -/** - * \brief Retrieves the current frequency of backup clock. - * - * Retrieves the operating frequency of backup clock, obtained from backup - * clock and the set backup clock divider. - * - * \return Current CPU frequency in Hz. - */ -static inline uint32_t system_backup_clock_get_hz(void) -{ - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->BUPDIV.reg - 1)); - -} - - -/** - * @} - */ - -/** - * \name Bus Clock Masking - * @{ - */ - -/** - * \brief Set bits in the clock mask for the AHB bus. - * - * This function will set bits in the clock mask for the AHB bus. - * Any bits set to 1 will enable that clock, 0 bits in the mask - * will be ignored - * - * \param[in] ahb_mask AHB clock mask to enable - */ -static inline void system_ahb_clock_set_mask( - const uint32_t ahb_mask) -{ - MCLK->AHBMASK.reg |= ahb_mask; -} - -/** - * \brief Clear bits in the clock mask for the AHB bus. - * - * This function will clear bits in the clock mask for the AHB bus. - * Any bits set to 1 will disable that clock, zero bits in the mask - * will be ignored. - * - * \param[in] ahb_mask AHB clock mask to disable - */ -static inline void system_ahb_clock_clear_mask( - const uint32_t ahb_mask) -{ - MCLK->AHBMASK.reg &= ~ahb_mask; -} - -/** - * \brief Set bits in the clock mask for an APBx bus. - * - * This function will set bits in the clock mask for an APBx bus. - * Any bits set to 1 will enable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_* - * constants from the device header files - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus given - * \retval STATUS_OK The clock mask was set successfully - */ -static inline enum status_code system_apb_clock_set_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - MCLK->APBAMASK.reg |= mask; - break; - - case SYSTEM_CLOCK_APB_APBB: - MCLK->APBBMASK.reg |= mask; - break; - - case SYSTEM_CLOCK_APB_APBC: - MCLK->APBCMASK.reg |= mask; - break; - case SYSTEM_CLOCK_APB_APBD: - MCLK->APBDMASK.reg |= mask; - break; - case SYSTEM_CLOCK_APB_APBE: - MCLK->APBEMASK.reg |= mask; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; - } - - /** - * \brief Clear bits in the clock mask for an APBx bus. - * - * This function will clear bits in the clock mask for an APBx bus. - * Any bits set to 1 will disable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to clear clock mask bits - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given. - * \retval STATUS_OK The clock mask was changed successfully. - */ - static inline enum status_code system_apb_clock_clear_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - MCLK->APBAMASK.reg &= ~mask; - break; - - case SYSTEM_CLOCK_APB_APBB: - MCLK->APBBMASK.reg &= ~mask; - break; - - case SYSTEM_CLOCK_APB_APBC: - MCLK->APBCMASK.reg &= ~mask; - break; - case SYSTEM_CLOCK_APB_APBD: - MCLK->APBDMASK.reg &= ~mask; - break; - case SYSTEM_CLOCK_APB_APBE: - MCLK->APBEMASK.reg &= ~mask; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; - } - - /** - * @} - */ - - /** - * \brief Reference clock source of the DPLL module. - */ - enum system_clock_source_dpll_reference_clock { - /** Select XOSC32K as clock reference */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K, - /** Select XOSC as clock reference */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC, - /** Select GCLK as clock reference */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, -}; - -/** - * \brief Lock time-out value of the DPLL module. - */ -enum system_clock_source_dpll_lock_time { - /** Set no time-out as default */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, - /** Set time-out if no lock within 8ms */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04, - /** Set time-out if no lock within 9ms */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS, - /** Set time-out if no lock within 10ms */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS, - /** Set time-out if no lock within 11ms */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS, -}; - -/** - * \brief Filter type of the DPLL module. - */ -enum system_clock_source_dpll_filter { - /** Default filter mode */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, - /** Low bandwidth filter */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER, - /** High bandwidth filter */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER, - /** High damping filter */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER, -}; - -/** - * \brief DPLL Output Clock Prescaler. - */ -enum system_clock_source_dpll_prescaler { - /** DPLL output is divided by 1 */ - SYSTEM_CLOCK_SOURCE_DPLL_DIV_1, - /** DPLL output is divided by 2 */ - SYSTEM_CLOCK_SOURCE_DPLL_DIV_2, - /** DPLL output is divided by 4 */ - SYSTEM_CLOCK_SOURCE_DPLL_DIV_4, -}; - -/** - * \brief Configuration structure for DPLL. - * - * DPLL oscillator configuration structure. - */ -struct system_clock_source_dpll_config { - /** Run On Demand. If this is set the DPLL won't run - * until requested by a peripheral */ - bool on_demand; - /** Keep the DPLL enabled in standby sleep mode */ - bool run_in_standby; - /** Bypass lock signal */ - bool lock_bypass; - /** Wake up fast. If this is set DPLL output clock is enabled after - * the start-up time */ - bool wake_up_fast; - /** Enable low power mode */ - bool low_power_enable; - - /** Output frequency of the clock */ - uint32_t output_frequency; - /** Reference frequency of the clock */ - uint32_t reference_frequency; - /** Devider of reference clock */ - uint16_t reference_divider; - - /** Filter type of the DPLL module */ - enum system_clock_source_dpll_filter filter; - /** Lock time-out value of the DPLL module */ - enum system_clock_source_dpll_lock_time lock_time; - /** Reference clock source of the DPLL module */ - enum system_clock_source_dpll_reference_clock reference_clock; - /** DPLL prescaler */ - enum system_clock_source_dpll_prescaler prescaler; -}; - -/** - * \name Internal DPLL Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for DPLL. - * - * Fills a configuration structure with the default configuration for a - * DPLL oscillator module: - * - Run only when requested by peripheral (on demand) - * - Don't run in STANDBY sleep mode - * - Lock bypass disabled - * - Fast wake up disabled - * - Low power mode disabled - * - Output frequency is 48MHz - * - Reference clock frequency is 32768Hz - * - Not divide reference clock - * - Select REF0 as reference clock - * - Set lock time to default mode - * - Use default filter - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_dpll_get_config_defaults( - struct system_clock_source_dpll_config *const config) -{ - config->on_demand = true; - config->run_in_standby = false; - config->lock_bypass = false; - config->wake_up_fast = false; - config->low_power_enable = false; - - config->output_frequency = 48000000; - config->reference_frequency = 32768; - config->reference_divider = 1; - config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK; - config->prescaler = SYSTEM_CLOCK_SOURCE_DPLL_DIV_1; - - config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT; - config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT; -}; - -void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config); - -/* @} */ - -/** - * \name System Clock Initialization - * @{ - */ - -void system_clock_init(void); - -/** - * @} - */ - -/** - * \name System Flash Wait States - * @{ - */ - -/** - * \brief Set flash controller wait states. - * - * Will set the number of wait states that are used by the onboard - * flash memory. The number of wait states depend on both device - * supply voltage and CPU speed. The required number of wait states - * can be found in the electrical characteristics of the device. - * - * \param[in] wait_states Number of wait states to use for internal flash - */ -static inline void system_flash_set_waitstates(uint8_t wait_states) -{ - Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) == - ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos)); - - NVMCTRL->CTRLB.bit.RWS = wait_states; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver - * - * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DFLLDigital Frequency Locked Loop
MUXMultiplexer
MCLKMain Clock
OSC32KInternal 32KHz Oscillator
OSC16MInternal 16MHz Oscillator
PLLPhase Locked Loop
OSCOscillator
XOSCExternal Oscillator
XOSC32KExternal 32KHz Oscillator
AHBAdvanced High-performance Bus
APBAdvanced Peripheral Bus
DPLLDigital Phase Locked Loop
- * - * - * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_clock_extra_errata Errata - * - * - This driver implements experimental workaround for errata 9905 - * - * "The DFLL clock must be requested before being configured. Otherwise a - * write access to a DFLL register can freeze the device." - * This driver will enable and configure the DFLL before the ONDEMAND bit is set. - * - * - * \section asfdoc_sam0_system_clock_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial Release
- */ - -/** - * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple - * examples with step-by-step instructions to configure and use this driver in - * a selection of use cases. Note that a QSG can be compiled as a standalone - * application or be added to the user application. - * - * - \subpage asfdoc_sam0_system_clock_basic_use_case - * - \subpage asfdoc_sam0_system_gclk_basic_use_case - * - * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42452A06/2015Initial document release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/gclk.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/gclk.c deleted file mode 100644 index 7e0d083bfbe..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/gclk.c +++ /dev/null @@ -1,464 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Generic Clock Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include - - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * \param[in] generator Generic Clock Generator index to sync - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval false if the module has completed synchronization - * \retval true if the module synchronization is ongoing - */ -static inline bool system_gclk_is_syncing(const uint8_t generator) -{ - - if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )) { - return true; - } - - return false; -} - - -/** - * \brief Initializes the GCLK driver. - * - * Initializes the Generic Clock module, disabling and resetting all active - * Generic Clock Generators and Channels to their power-on default values. - */ -void system_gclk_init(void) -{ - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_GCLK); - - /* Software reset the module to ensure it is re-initialized correctly */ - GCLK->CTRLA.reg = GCLK_CTRLA_SWRST; - while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) { - /* Wait for reset to complete */ - } -} - -/** - * \brief Writes a Generic Clock Generator configuration to the hardware module. - * - * Writes out a given configuration of a Generic Clock Generator configuration - * to the hardware module. - * - * \note Changing the clock source on the fly (on a running - * generator) can take additional time if the clock source is configured - * to only run on-demand (ONDEMAND bit is set) and it is not currently - * running (no peripheral is requesting the clock source). In this case - * the GCLK will request the new clock while still keeping a request to - * the old clock source until the new clock source is ready. - * - * \note This function will not start a generator that is not already running; - * to start the generator, call \ref system_gclk_gen_enable() - * after configuring a generator. - * - * \param[in] generator Generic Clock Generator index to configure - * \param[in] config Configuration settings for the generator - */ -void system_gclk_gen_set_config( - const uint8_t generator, - struct system_gclk_gen_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Cache new register configurations to minimize sync requirements. */ - uint32_t new_genctrl_config ; - - - /* Select the requested source clock for the generator */ - new_genctrl_config = config->source_clock << GCLK_GENCTRL_SRC_Pos; - - /* Configure the clock to be either high or low when disabled */ - if (config->high_when_disabled) { - new_genctrl_config |= GCLK_GENCTRL_OOV; - } - - /* Configure if the clock output to I/O pin should be enabled. */ - if (config->output_enable) { - new_genctrl_config |= GCLK_GENCTRL_OE; - } - - /* Set division factor */ - if (config->division_factor > 1) { - /* Check if division is a power of two */ - if (((config->division_factor & (config->division_factor - 1)) == 0)) { - /* Determine the index of the highest bit set to get the - * division factor that must be loaded into the division - * register */ - - uint32_t div2_count = 0; - - uint32_t mask; - for (mask = (1UL << 1); mask < config->division_factor; - mask <<= 1) { - div2_count++; - } - - /* Set binary divider power of 2 division factor */ - new_genctrl_config |= div2_count << GCLK_GENCTRL_DIV_Pos; - new_genctrl_config |= GCLK_GENCTRL_DIVSEL; - } else { - /* Set integer division factor */ - - new_genctrl_config |= - (config->division_factor) << GCLK_GENCTRL_DIV_Pos; - - /* Enable non-binary division with increased duty cycle accuracy */ - new_genctrl_config |= GCLK_GENCTRL_IDC; - } - - } - - /* Enable or disable the clock in standby mode */ - if (config->run_in_standby) { - new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY; - } - - while (system_gclk_is_syncing(generator)) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN); - - while (system_gclk_is_syncing(generator)) { - /* Wait for synchronization */ - }; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Enables a Generic Clock Generator that was previously configured. - * - * Starts the clock generation of a Generic Clock Generator that was previously - * configured via a call to \ref system_gclk_gen_set_config(). - * - * \param[in] generator Generic Clock Generator index to enable - */ -void system_gclk_gen_enable( - const uint8_t generator) -{ - while (system_gclk_is_syncing(generator)) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Enable generator */ - GCLK->GENCTRL[generator].reg |= GCLK_GENCTRL_GENEN; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Disables a Generic Clock Generator that was previously enabled. - * - * Stops the clock generation of a Generic Clock Generator that was previously - * started via a call to \ref system_gclk_gen_enable(). - * - * \param[in] generator Generic Clock Generator index to disable - */ -void system_gclk_gen_disable( - const uint8_t generator) -{ - while (system_gclk_is_syncing(generator)) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Disable generator */ - GCLK->GENCTRL[generator].reg &= ~GCLK_GENCTRL_GENEN; - while (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN) { - /* Wait for clock to become disabled */ - } - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock Generator is enabled. - * - * \param[in] generator Generic Clock Generator index to check - * - * \return The enabled status. - * \retval true The Generic Clock Generator is enabled - * \retval false The Generic Clock Generator is disabled - */ -bool system_gclk_gen_is_enabled( - const uint8_t generator) -{ - bool enabled; - - system_interrupt_enter_critical_section(); - - /* Obtain the enabled status */ - enabled = (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN); - - system_interrupt_leave_critical_section(); - - return enabled; -} - -/** - * \brief Retrieves the clock frequency of a Generic Clock generator. - * - * Determines the clock frequency (in Hz) of a specified Generic Clock - * generator, used as a source to a Generic Clock Channel module. - * - * \param[in] generator Generic Clock Generator index - * - * \return The frequency of the generic clock generator, in Hz. - */ -uint32_t system_gclk_gen_get_hz( - const uint8_t generator) -{ - while (system_gclk_is_syncing(generator)) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Get the frequency of the source connected to the GCLK generator */ - uint32_t gen_input_hz = system_clock_source_get_hz( - (enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC); - - uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL; - uint32_t divider = GCLK->GENCTRL[generator].bit.DIV; - - system_interrupt_leave_critical_section(); - - /* Check if the generator is using fractional or binary division */ - if (!divsel && divider > 1) { - gen_input_hz /= divider; - } else if (divsel) { - gen_input_hz >>= (divider+1); - } - - return gen_input_hz; -} - -/** - * \brief Writes a Generic Clock configuration to the hardware module. - * - * Writes out a given configuration of a Generic Clock configuration to the - * hardware module. If the clock is currently running, it will be stopped. - * - * \note Once called the clock will not be running; to start the clock, - * call \ref system_gclk_chan_enable() after configuring a clock channel. - * - * \param[in] channel Generic Clock channel to configure - * \param[in] config Configuration settings for the clock - * - */ -void system_gclk_chan_set_config( - const uint8_t channel, - struct system_gclk_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Disable generic clock channel */ - system_gclk_chan_disable(channel); - - /* Configure the peripheral channel */ - GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator); - - -} - -/** - * \brief Enables a Generic Clock that was previously configured. - * - * Starts the clock generation of a Generic Clock that was previously - * configured via a call to \ref system_gclk_chan_set_config(). - * - * \param[in] channel Generic Clock channel to enable - */ -void system_gclk_chan_enable( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Enable the peripheral channel */ - GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN; - - while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) { - /* Wait for clock synchronization */ - } - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Disables a Generic Clock that was previously enabled. - * - * Stops the clock generation of a Generic Clock that was previously started - * via a call to \ref system_gclk_chan_enable(). - * - * \param[in] channel Generic Clock channel to disable - */ -void system_gclk_chan_disable( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Sanity check WRTLOCK */ - Assert(!GCLK->PCHCTRL[channel].bit.WRTLOCK); - - /* Disable the peripheral channel */ - GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN; - - while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) { - /* Wait for clock synchronization */ - } - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock channel is enabled. - * - * \param[in] channel Generic Clock Channel index - * - * \return The enabled status. - * \retval true The Generic Clock channel is enabled - * \retval false The Generic Clock channel is disabled - */ -bool system_gclk_chan_is_enabled( - const uint8_t channel) -{ - bool enabled; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - enabled = GCLK->PCHCTRL[channel].bit.CHEN; - - system_interrupt_leave_critical_section(); - - return enabled; -} - -/** - * \brief Locks a Generic Clock channel from further configuration writes. - * - * Locks a generic clock channel from further configuration writes. It is only - * possible to unlock the channel configuration through a power on reset. - * - * \param[in] channel Generic Clock channel to enable - */ -void system_gclk_chan_lock( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_WRTLOCK; - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock channel is locked. - * - * \param[in] channel Generic Clock Channel index - * - * \return The lock status. - * \retval true The Generic Clock channel is locked - * \retval false The Generic Clock channel is not locked - */ -bool system_gclk_chan_is_locked( - const uint8_t channel) -{ - bool locked; - - system_interrupt_enter_critical_section(); - locked = GCLK->PCHCTRL[channel].bit.WRTLOCK; - system_interrupt_leave_critical_section(); - - return locked; -} - -/** - * \brief Retrieves the clock frequency of a Generic Clock channel. - * - * Determines the clock frequency (in Hz) of a specified Generic Clock - * channel, used as a source to a device peripheral module. - * - * \param[in] channel Generic Clock Channel index - * - * \return The frequency of the generic clock channel, in Hz. - */ -uint32_t system_gclk_chan_get_hz( - const uint8_t channel) -{ - uint8_t gen_id; - - system_interrupt_enter_critical_section(); - /* Select the requested generic clock channel */ - gen_id = GCLK->PCHCTRL[channel].bit.GEN; - system_interrupt_leave_critical_section(); - - /* Return the clock speed of the associated GCLK generator */ - return system_gclk_gen_get_hz(gen_id); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock.c deleted file mode 100644 index 3060c04f09b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock.c +++ /dev/null @@ -1,1031 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Clock Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include - -#ifndef SYSCTRL_FUSES_OSC32K_ADDR -#if (SAMR21) || (SAMD) -# define SYSCTRL_FUSES_OSC32K_ADDR FUSES_OSC32K_CAL_ADDR -# define SYSCTRL_FUSES_OSC32K_Pos FUSES_OSC32K_CAL_Pos -#elif (SAML21) -# define SYSCTRL_FUSES_OSC32K_ADDR NVMCTRL_OTP4 -# define SYSCTRL_FUSES_OSC32K_Pos 6 - -#else -# define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR -# define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos -#endif -#endif - -/** - * \internal - * \brief DFLL-specific data container. - */ -struct _system_clock_dfll_config { - uint32_t control; - uint32_t val; - uint32_t mul; -}; - -/** - * \internal - * \brief DPLL-specific data container. - */ -struct _system_clock_dpll_config { - uint32_t frequency; -}; - - -/** - * \internal - * \brief XOSC-specific data container. - */ -struct _system_clock_xosc_config { - uint32_t frequency; -}; - -/** - * \internal - * \brief System clock module data container. - */ -struct _system_clock_module { - volatile struct _system_clock_dfll_config dfll; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - volatile struct _system_clock_dpll_config dpll; -#endif - - volatile struct _system_clock_xosc_config xosc; - volatile struct _system_clock_xosc_config xosc32k; -}; - -/** - * \internal - * \brief Internal module instance to cache configuration values. - */ -static struct _system_clock_module _system_clock_inst = { - .dfll = { - .control = 0, - .val = 0, - .mul = 0, - }, - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - .dpll = { - .frequency = 0, - }, -#endif - .xosc = { - .frequency = 0, - }, - .xosc32k = { - .frequency = 0, - }, -}; - -/** - * \internal - * \brief Wait for sync to the DFLL control registers. - */ -static inline void _system_dfll_wait_for_sync(void) -{ - while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) { - /* Wait for DFLL sync */ - } -} - -/** - * \internal - * \brief Wait for sync to the OSC32K control registers. - */ -static inline void _system_osc32k_wait_for_sync(void) -{ - while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) { - /* Wait for OSC32K sync */ - } -} - -static inline void _system_clock_source_dfll_set_config_errata_9905(void) -{ - - /* Disable ONDEMAND mode while writing configurations */ - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND; - _system_dfll_wait_for_sync(); - - SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; - SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; - - /* Write full configuration to DFLL control register */ - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; -} - -/** - * \brief Retrieve the frequency of a clock source. - * - * Determines the current operating frequency of a given clock source. - * - * \param[in] clock_source Clock source to get the frequency - * - * \returns Frequency of the given clock source, in Hz. - */ -uint32_t system_clock_source_get_hz( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_XOSC: - return _system_clock_inst.xosc.frequency; - - case SYSTEM_CLOCK_SOURCE_OSC8M: - return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - return 32768UL; - - case SYSTEM_CLOCK_SOURCE_ULP32K: - return 32768UL; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - return _system_clock_inst.xosc32k.frequency; - - case SYSTEM_CLOCK_SOURCE_DFLL: - - /* Check if the DFLL has been configured */ - if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE)) - return 0; - - /* Make sure that the DFLL module is ready */ - _system_dfll_wait_for_sync(); - - /* Check if operating in closed loop mode */ - if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) { - return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) * - (_system_clock_inst.dfll.mul & 0xffff); - } - - return 48000000UL; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) { - return 0; - } - - return _system_clock_inst.dpll.frequency; -#endif - - default: - return 0; - } -} - -/** - * \brief Configure the internal OSC8M oscillator clock source. - * - * Configures the 8MHz (nominal) internal RC oscillator with the given - * configuration settings. - * - * \param[in] config OSC8M configuration structure containing the new config - */ -void system_clock_source_osc8m_set_config( - struct system_clock_source_osc8m_config *const config) -{ - SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; - - /* Use temporary struct to reduce register access */ - temp.bit.PRESC = config->prescaler; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - - SYSCTRL->OSC8M = temp; -} - -/** - * \brief Configure the internal OSC32K oscillator clock source. - * - * Configures the 32KHz (nominal) internal RC oscillator with the given - * configuration settings. - * - * \param[in] config OSC32K configuration structure containing the new config - */ -void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config) -{ - SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; - - /* Update settings via a temporary struct to reduce register access */ - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - temp.bit.STARTUP = config->startup_time; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; - - SYSCTRL->OSC32K = temp; -} - -/** - * \brief Configure the external oscillator clock source. - * - * Configures the external oscillator clock source with the given configuration - * settings. - * - * \param[in] config External oscillator configuration structure containing - * the new config - */ -void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config) -{ - SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; - - temp.bit.STARTUP = config->startup_time; - - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } - - temp.bit.AMPGC = config->auto_gain_control; - - /* Set gain if automatic gain control is not selected */ - if (!config->auto_gain_control) { - if (config->frequency <= 2000000) { - temp.bit.GAIN = 0; - } else if (config->frequency <= 4000000) { - temp.bit.GAIN = 1; - } else if (config->frequency <= 8000000) { - temp.bit.GAIN = 2; - } else if (config->frequency <= 16000000) { - temp.bit.GAIN = 3; - } else if (config->frequency <= 30000000) { - temp.bit.GAIN = 4; - } - - } - - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - - /* Store XOSC frequency for internal use */ - _system_clock_inst.xosc.frequency = config->frequency; - - SYSCTRL->XOSC = temp; -} - -/** - * \brief Configure the XOSC32K external 32KHz oscillator clock source. - * - * Configures the external 32KHz oscillator clock source with the given - * configuration settings. - * - * \param[in] config XOSC32K configuration structure containing the new config - */ -void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config) -{ - SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K; - - temp.bit.STARTUP = config->startup_time; - - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } - - temp.bit.AAMPEN = config->auto_gain_control; - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; - - /* Cache the new frequency in case the user needs to check the current - * operating frequency later */ - _system_clock_inst.xosc32k.frequency = config->frequency; - - SYSCTRL->XOSC32K = temp; -} - -/** - * \brief Configure the DFLL clock source. - * - * Configures the Digital Frequency Locked Loop clock source with the given - * configuration settings. - * - * \note The DFLL will be running when this function returns, as the DFLL module - * needs to be enabled in order to perform the module configuration. - * - * \param[in] config DFLL configuration structure containing the new config - */ -void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config) -{ - _system_clock_inst.dfll.val = - SYSCTRL_DFLLVAL_COARSE(config->coarse_value) | - SYSCTRL_DFLLVAL_FINE(config->fine_value); - - _system_clock_inst.dfll.control = - (uint32_t)config->wakeup_lock | - (uint32_t)config->stable_tracking | - (uint32_t)config->quick_lock | - (uint32_t)config->chill_cycle | - ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos); - - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - - _system_clock_inst.dfll.mul = - SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | - SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | - SYSCTRL_DFLLMUL_MUL(config->multiply_factor); - - /* Enable the closed loop mode */ - _system_clock_inst.dfll.control |= config->loop_mode; - } - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - - _system_clock_inst.dfll.mul = - SYSCTRL_DFLLMUL_MUL(config->multiply_factor); - - /* Enable the USB recovery mode */ - _system_clock_inst.dfll.control |= config->loop_mode | - SYSCTRL_DFLLCTRL_BPLCKC; - } -} - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL -/** - * \brief Configure the DPLL clock source. - * - * Configures the Digital Phase-Locked Loop clock source with the given - * configuration settings. - * - * \note The DPLL will be running when this function returns, as the DPLL module - * needs to be enabled in order to perform the module configuration. - * - * \param[in] config DPLL configuration structure containing the new config - */ -void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config) -{ - - uint32_t tmpldr; - uint8_t tmpldrfrac; - uint32_t refclk; - - refclk = config->reference_frequency; - - /* Only reference clock REF1 can be divided */ - if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { - refclk = refclk / (2 * (config->reference_divider + 1)); - } - - /* Calculate LDRFRAC and LDR */ - tmpldr = (config->output_frequency << 4) / refclk; - tmpldrfrac = tmpldr & 0x0f; - tmpldr = (tmpldr >> 4) - 1; - - SYSCTRL->DPLLCTRLA.reg = - ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) | - ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos); - - SYSCTRL->DPLLRATIO.reg = - SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | - SYSCTRL_DPLLRATIO_LDR(tmpldr); - - SYSCTRL->DPLLCTRLB.reg = - SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) | - ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) | - SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) | - SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | - ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) | - ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) | - SYSCTRL_DPLLCTRLB_FILTER(config->filter); - - /* - * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) - */ - _system_clock_inst.dpll.frequency = - (refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4; -} -#endif - -/** - * \brief Writes the calibration values for a given oscillator clock source. - * - * Writes an oscillator calibration value to the given oscillator control - * registers. The acceptable ranges are: - * - * For OSC32K: - * - 7 bits (max value 128) - * For OSC8MHZ: - * - 8 bits (Max value 255) - * For OSCULP: - * - 5 bits (Max value 32) - * - * \note The frequency range parameter applies only when configuring the 8MHz - * oscillator and will be ignored for the other oscillators. - * - * \param[in] clock_source Clock source to calibrate - * \param[in] calibration_value Calibration value to write - * \param[in] freq_range Frequency range (8MHz oscillator only) - * - * \retval STATUS_OK The calibration value was written - * successfully. - * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock - * source. - */ -enum status_code system_clock_source_write_calibration( - const enum system_clock_source clock_source, - const uint16_t calibration_value, - const uint8_t freq_range) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - - if (calibration_value > 0xfff || freq_range > 4) { - return STATUS_ERR_INVALID_ARG; - } - - SYSCTRL->OSC8M.bit.CALIB = calibration_value; - SYSCTRL->OSC8M.bit.FRANGE = freq_range; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - - if (calibration_value > 128) { - return STATUS_ERR_INVALID_ARG; - } - - _system_osc32k_wait_for_sync(); - SYSCTRL->OSC32K.bit.CALIB = calibration_value; - break; - - case SYSTEM_CLOCK_SOURCE_ULP32K: - - if (calibration_value > 32) { - return STATUS_ERR_INVALID_ARG; - } - - SYSCTRL->OSCULP32K.bit.CALIB = calibration_value; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; -} - -/** - * \brief Enables a clock source. - * - * Enables a clock source which has been previously configured. - * - * \param[in] clock_source Clock source to enable - * - * \retval STATUS_OK Clock source was enabled successfully and - * is ready - * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this - * device - */ -enum status_code system_clock_source_enable( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; - return STATUS_OK; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE; - _system_clock_source_dfll_set_config_errata_9905(); - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; - break; -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Always enabled */ - return STATUS_OK; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; - } - - /** - * \brief Disables a clock source. - * - * Disables a clock source that was previously enabled. - * - * \param[in] clock_source Clock source to disable - * - * \retval STATUS_OK Clock source was disabled successfully - * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was - * given - */ - enum status_code system_clock_source_disable( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE; - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; - break; -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; - } - - /** - * \brief Checks if a clock source is ready. - * - * Checks if a given clock source is ready to be used. - * - * \param[in] clock_source Clock source to check if ready - * - * \returns Ready state of the given clock source. - * - * \retval true Clock source is enabled and ready - * \retval false Clock source is disabled or not yet ready - */ - bool system_clock_source_is_ready( - const enum system_clock_source clock_source) -{ - uint32_t mask = 0; - - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - mask = SYSCTRL_PCLKSR_OSC8MRDY; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - mask = SYSCTRL_PCLKSR_OSC32KRDY; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - mask = SYSCTRL_PCLKSR_XOSCRDY; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - mask = SYSCTRL_PCLKSR_XOSC32KRDY; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - mask = (SYSCTRL_PCLKSR_DFLLRDY | - SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC); - } else { - mask = SYSCTRL_PCLKSR_DFLLRDY; - } - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - return ((SYSCTRL->DPLLSTATUS.reg & - (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) == - (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)); -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - return true; - - default: - return false; - } - - return ((SYSCTRL->PCLKSR.reg & mask) == mask); -} - -/* Include some checks for conf_clocks.h validation */ -#include "clock_config_check.h" - -#if !defined(__DOXYGEN__) -/** \internal - * - * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h. - */ -# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \ - if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \ - struct system_gclk_gen_config gclk_conf; \ - system_gclk_gen_get_config_defaults(&gclk_conf); \ - gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \ - gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \ - gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \ - gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \ - system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \ - system_gclk_gen_enable(GCLK_GENERATOR_##n); \ - } - -/** \internal - * - * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h, - * provided that it is not the main Generic Clock Generator channel. - */ -# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \ - if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); } -#endif - -/** \internal - * - * Switch all peripheral clock to a not enabled general clock - * to save power. - */ -static void _switch_peripheral_gclk(void) -{ - uint32_t gclk_id; - struct system_gclk_chan_config gclk_conf; - -#if CONF_CLOCK_GCLK_1_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_1; -#elif CONF_CLOCK_GCLK_2_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_2; -#elif CONF_CLOCK_GCLK_3_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_3; -#elif CONF_CLOCK_GCLK_4_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_4; -#elif CONF_CLOCK_GCLK_5_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_5; -#elif CONF_CLOCK_GCLK_6_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_6; -#elif CONF_CLOCK_GCLK_7_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_7; -#else - gclk_conf.source_generator = GCLK_GENERATOR_7; -#endif - - for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) { - system_gclk_chan_set_config(gclk_id, &gclk_conf); - } -} - -/** - * \brief Initialize clock system based on the configuration in conf_clocks.h. - * - * This function will apply the settings in conf_clocks.h when run from the user - * application. All clock sources and GCLK generators are running when this function - * returns. - * - * \note OSC8M is always enabled and if user selects other clocks for GCLK generators, - * the OSC8M default enable can be disabled after system_clock_init. Make sure the - * clock switch successfully before disabling OSC8M. - */ -void system_clock_init(void) -{ - /* Various bits in the INTFLAG register can be set to one at startup. - This will ensure that these bits are cleared */ - SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | - SYSCTRL_INTFLAG_DFLLRDY; - - system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); - - /* Switch all peripheral clock to a not enabled general clock to save power. */ - _switch_peripheral_gclk(); - - /* XOSC */ -#if CONF_CLOCK_XOSC_ENABLE == true - struct system_clock_source_xosc_config xosc_conf; - system_clock_source_xosc_get_config_defaults(&xosc_conf); - - xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; - xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; - xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; - xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; - xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; - xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; - - system_clock_source_xosc_set_config(&xosc_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); -#endif - - - /* XOSC32K */ -#if CONF_CLOCK_XOSC32K_ENABLE == true - struct system_clock_source_xosc32k_config xosc32k_conf; - system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); - - xosc32k_conf.frequency = 32768UL; - xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; - xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; - xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL; - xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; - xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; - xosc32k_conf.on_demand = false; - xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; - - system_clock_source_xosc32k_set_config(&xosc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); - if (CONF_CLOCK_XOSC32K_ON_DEMAND) { - SYSCTRL->XOSC32K.bit.ONDEMAND = 1; - } -#endif - - - /* OSCK32K */ -#if CONF_CLOCK_OSC32K_ENABLE == true - SYSCTRL->OSC32K.bit.CALIB = - ((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> - SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful); - - struct system_clock_source_osc32k_config osc32k_conf; - system_clock_source_osc32k_get_config_defaults(&osc32k_conf); - - osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; - osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; - osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; - osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; - osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; - - system_clock_source_osc32k_set_config(&osc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); -#endif - - - /* DFLL Config (Open and Closed Loop) */ -#if CONF_CLOCK_DFLL_ENABLE == true - struct system_clock_source_dfll_config dfll_conf; - system_clock_source_dfll_get_config_defaults(&dfll_conf); - - dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; - dfll_conf.on_demand = false; - - /* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping - in DFLL.COARSE helps to output a frequency close to 48 MHz.*/ -#define NVM_DFLL_COARSE_POS 58 /* DFLL48M Coarse calibration value bit position.*/ -#define NVM_DFLL_COARSE_SIZE 6 /* DFLL48M Coarse calibration value bit size.*/ - - uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) - + (NVM_DFLL_COARSE_POS / 32)) - >> (NVM_DFLL_COARSE_POS % 32)) - & ((1 << NVM_DFLL_COARSE_SIZE) - 1); - /* In some revision chip, the coarse calibration value is not correct. */ - if (coarse == 0x3f) { - coarse = 0x1f; - } - dfll_conf.coarse_value = coarse; - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { - dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; - } - -# if CONF_CLOCK_DFLL_QUICK_LOCK == true - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; -# else - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; -# endif - -# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; -# else - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; -# endif - -# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; -# else - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; -# endif - -# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; -# else - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; -# endif - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; - } - - dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; - dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - dfll_conf.fine_value = 0x1ff; - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; - - dfll_conf.multiply_factor = 48000; - } - - system_clock_source_dfll_set_config(&dfll_conf); -#endif - - - /* OSC8M */ - struct system_clock_source_osc8m_config osc8m_conf; - system_clock_source_osc8m_get_config_defaults(&osc8m_conf); - - osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER; - osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND; - osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY; - - system_clock_source_osc8m_set_config(&osc8m_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M); - - - /* GCLK */ -#if CONF_CLOCK_CONFIGURE_GCLK == true - system_gclk_init(); - - /* Configure all GCLK generators except for the main generator, which - * is configured later after all other clock systems are set up */ - MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); - -# if CONF_CLOCK_DFLL_ENABLE == true - /* Enable DFLL reference clock if in closed loop mode */ - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - struct system_gclk_chan_config dfll_gclk_chan_conf; - - system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); - dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); - } -# endif - -# if CONF_CLOCK_DPLL_ENABLE == true - /* Enable DPLL internal lock timer and reference clock */ - struct system_gclk_chan_config dpll_gclk_chan_conf; - system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf); - if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) { - dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K); - } - - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { - dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL); - } -# endif -#endif - - - /* DFLL Enable (Open and Closed Loop) */ -#if CONF_CLOCK_DFLL_ENABLE == true - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); - if (CONF_CLOCK_DFLL_ON_DEMAND) { - SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1; - } -#endif - - /* DPLL */ -#ifdef FEATURE_SYSTEM_CLOCK_DPLL -# if (CONF_CLOCK_DPLL_ENABLE == true) - - /* Enable DPLL reference clock */ - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) { - /* XOSC32K should have been enabled for DPLL_REF0 */ - Assert(CONF_CLOCK_XOSC32K_ENABLE); - } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { - /* XOSC should have been enabled for DPLL_REF1 */ - Assert(CONF_CLOCK_XOSC_ENABLE); - } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { - /* GCLK should have been enabled */ - Assert(CONF_CLOCK_CONFIGURE_GCLK); - } else { - Assert(false); - } - - struct system_clock_source_dpll_config dpll_config; - system_clock_source_dpll_get_config_defaults(&dpll_config); - - dpll_config.on_demand = false; - dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; - dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; - dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; - dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; - - dpll_config.filter = CONF_CLOCK_DPLL_FILTER; - dpll_config.lock_time = CONF_CLOCK_DPLL_LOCK_TIME; - - dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; - dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; - dpll_config.reference_divider = CONF_CLOCK_DPLL_REFERENCE_DIVIDER; - dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; - - system_clock_source_dpll_set_config(&dpll_config); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); - if (CONF_CLOCK_DPLL_ON_DEMAND) { - SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1; - } - -# endif -#endif - - /* CPU and BUS clocks */ - system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); - - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER); - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER); - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER); - - /* GCLK 0 */ -#if CONF_CLOCK_CONFIGURE_GCLK == true - /* Configure the main GCLK last as it might depend on other generators */ - _CONF_CLOCK_GCLK_CONFIG(0, ~); -#endif -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_config_check.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_config_check.h deleted file mode 100644 index fd4757e2821..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_config_check.h +++ /dev/null @@ -1,454 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CLOCK_CONFIG_CHECK_H -# define CLOCK_CONFIG_CHECK_H - -#if !defined(CONF_CLOCK_FLASH_WAIT_STATES) -# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_CPU_DIVIDER) -# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBA_DIVIDER) -# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBB_DIVIDER) -# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBC_DIVIDER) -# error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_PRESCALER) -# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND) -# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY) -# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_ENABLE) -# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL) -# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY) -# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME) -# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) -# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_ON_DEMAND) -# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY) -# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE) -# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL) -# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME) -# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL) -# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT) -# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT) -# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND) -# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY) -# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE) -# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME) -# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT) -# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT) -# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND) -# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY) -# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ENABLE) -# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_LOOP_MODE) -# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ON_DEMAND) -# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_FINE_VALUE) -# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR) -# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR) -# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK) -# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK) -# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP) -# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE) -# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE) -# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE) -# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_ENABLE) -# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_ON_DEMAND) -# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY) -# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS) -# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST) -# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE) -# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_TIME) -# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK) -# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_FILTER) -# error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY) -# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER) -# error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY) -# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR) -# error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR) -# error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_CONFIGURE_GCLK) -# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_ENABLE) -# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_PRESCALER) -# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_ENABLE) -# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_PRESCALER) -# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_ENABLE) -# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_PRESCALER) -# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_ENABLE) -# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_PRESCALER) -# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_ENABLE) -# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_PRESCALER) -# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_ENABLE) -# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_PRESCALER) -# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_ENABLE) -# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_PRESCALER) -# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_ENABLE) -# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_PRESCALER) -# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_ENABLE) -# error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_PRESCALER) -# error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#endif /* CLOCK_CONFIG_CHECK_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_feature.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_feature.h deleted file mode 100644 index b647b7f694b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_feature.h +++ /dev/null @@ -1,1492 +0,0 @@ -/** - * \file - * - * \brief SAM Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED -#define SYSTEM_CLOCK_FEATURE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK) - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the device's clocking related functions. This includes - * the various clock sources, bus clocks, and generic clocks within the device, - * with functions to manage the enabling, disabling, source selection, and - * prescaling of clocks to various internal peripherals. - * - * The following peripherals are used by this module: - * - * - GCLK (Generic Clock Management) - * - PM (Power Management) - * - SYSCTRL (Clock Source Control) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM DA0/DA1 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_clock_prerequisites - * - \ref asfdoc_sam0_system_clock_module_overview - * - \ref asfdoc_sam0_system_clock_special_considerations - * - \ref asfdoc_sam0_system_clock_extra_info - * - \ref asfdoc_sam0_system_clock_examples - * - \ref asfdoc_sam0_system_clock_api_overview - * - * - * \section asfdoc_sam0_system_clock_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_clock_module_overview Module Overview - * The SAM devices contain a sophisticated clocking system, which is designed - * to give the maximum flexibility to the user application. This system allows - * a system designer to tune the performance and power consumption of the device - * in a dynamic manner, to achieve the best trade-off between the two for a - * particular application. - * - * This driver provides a set of functions for the configuration and management - * of the various clock related functionality within the device. - * - * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_SYSTEM_CLOCK_DPLLSAMD21, SAMR21, SAMD10, SAMD11, SAMDAx
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources - * The SAM devices have a number of master clock source modules, each of - * which being capable of producing a stabilized output frequency, which can then - * be fed into the various peripherals and modules within the device. - * - * Possible clock source modules include internal R/C oscillators, internal - * DFLL modules, as well as external crystal oscillators and/or clock inputs. - * - * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks - * The CPU and AHB/APBx buses are clocked by the same physical clock source - * (referred in this module as the Main Clock), however the APBx buses may - * have additional prescaler division ratios set to give each peripheral bus a - * different clock speed. - * - * The general main clock tree for the CPU and associated buses is shown in - * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below". - * - * \anchor asfdoc_sam0_system_clock_module_clock_tree - * \dot - * digraph overview { - * rankdir=LR; - * clk_src [label="Clock Sources", shape=none, height=0]; - * node [label="CPU Bus" shape=ellipse] cpu_bus; - * node [label="AHB Bus" shape=ellipse] ahb_bus; - * node [label="APBA Bus" shape=ellipse] apb_a_bus; - * node [label="APBB Bus" shape=ellipse] apb_b_bus; - * node [label="APBC Bus" shape=ellipse] apb_c_bus; - * node [label="Main Bus\nPrescaler" shape=square] main_prescaler; - * node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler; - * node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler; - * node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler; - * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux; - * - * clk_src -> main_clock_mux; - * main_clock_mux -> main_prescaler; - * main_prescaler -> cpu_bus; - * main_prescaler -> ahb_bus; - * main_prescaler -> apb_a_prescaler; - * main_prescaler -> apb_b_prescaler; - * main_prescaler -> apb_c_prescaler; - * apb_a_prescaler -> apb_a_bus; - * apb_b_prescaler -> apb_b_bus; - * apb_c_prescaler -> apb_c_bus; - * } - * \enddot - * - * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking - * To save power, the input clock to one or more peripherals on the AHB and APBx - * buses can be masked away - when masked, no clock is passed into the module. - * Disabling of clocks of unused modules will prevent all access to the masked - * module, but will reduce the overall device power consumption. - * - * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks - * Within the SAM devices there are a number of Generic Clocks; these are used to - * provide clocks to the various peripheral clock domains in the device in a - * standardized manner. One or more master source clocks can be selected as the - * input clock to a Generic Clock Generator, which can prescale down the input - * frequency to a slower rate for use in a peripheral. - * - * Additionally, a number of individually selectable Generic Clock Channels are - * provided, which multiplex and gate the various generator outputs for one or - * more peripherals within the device. This setup allows for a single common - * generator to feed one or more channels, which can then be enabled or disabled - * individually as required. - * - * \anchor asfdoc_sam0_system_clock_module_chain_overview - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Clock\nSource a" shape=square] system_clock_source; - * node [label="Generator 1" shape=square] clock_gen; - * node [label="Channel x" shape=square] clock_chan0; - * node [label="Channel y" shape=square] clock_chan1; - * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0; - * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1; - * - * system_clock_source -> clock_gen; - * clock_gen -> clock_chan0; - * clock_chan0 -> peripheral0; - * clock_gen -> clock_chan1; - * clock_chan1 -> peripheral1; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example - * An example setup of a complete clock chain within the device is shown in - * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below". - * - * \anchor asfdoc_sam0_system_clock_module_chain_example_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="External\nOscillator" shape=square] system_clock_source0; - * node [label="Generator 0" shape=square] clock_gen0; - * node [label="Channel x" shape=square] clock_chan0; - * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0; - * - * system_clock_source0 -> clock_gen0; - * clock_gen0 -> clock_chan0; - * clock_chan0 -> peripheral0; - * node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1; - * node [label="Generator 1" shape=square] clock_gen1; - * node [label="Channel y" shape=square] clock_chan1; - * node [label="Channel z" shape=square] clock_chan2; - * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1; - * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2; - * - * system_clock_source1 -> clock_gen1; - * clock_gen1 -> clock_chan1; - * clock_gen1 -> clock_chan2; - * clock_chan1 -> peripheral1; - * clock_chan2 -> peripheral2; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators - * Each Generic Clock generator within the device can source its input clock - * from one of the provided Source Clocks, and prescale the output for one or - * more Generic Clock Channels in a one-to-many relationship. The generators - * thus allow for several clocks to be generated of different frequencies, - * power usages, and accuracies, which can be turned on and off individually to - * disable the clocks to multiple peripherals as a group. - * - * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels - * To connect a Generic Clock Generator to a peripheral within the - * device, a Generic Clock Channel is used. Each peripheral or - * peripheral group has an associated Generic Clock Channel, which serves as the - * clock input for the peripheral(s). To supply a clock to the peripheral - * module(s), the associated channel must be connected to a running Generic - * Clock Generator and the channel enabled. - * - * \section asfdoc_sam0_system_clock_special_considerations Special Considerations - * - * There are no special considerations for this module. - * - * - * \section asfdoc_sam0_system_clock_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes: - * - \ref asfdoc_sam0_system_clock_extra_acronyms - * - \ref asfdoc_sam0_system_clock_extra_dependencies - * - \ref asfdoc_sam0_system_clock_extra_errata - * - \ref asfdoc_sam0_system_clock_extra_history - * - * - * \section asfdoc_sam0_system_clock_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_system_clock_exqsg. - * - * - * \section asfdoc_sam0_system_clock_api_overview API Overview - * @{ - */ - -#include -#include - -/** - * \name Driver Feature Definition - * Define system clock features set according to different device family. - * @{ - */ -#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAMDA1) || defined(__DOXYGEN__) -/** Digital Phase Locked Loop (DPLL) feature support. */ -# define FEATURE_SYSTEM_CLOCK_DPLL -#endif -/*@}*/ - -/** - * \brief Available start-up times for the XOSC32K. - * - * Available external 32KHz oscillator start-up times, as a number of external - * clock cycles. - */ -enum system_xosc32k_startup { - /** Wait zero clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_0, - /** Wait 32 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_32, - /** Wait 2048 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_4096, - /** Wait 16384 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_32768, - /** Wait 65536 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_65536, - /** Wait 131072 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_131072, -}; - -/** - * \brief Available start-up times for the XOSC. - * - * Available external oscillator start-up times, as a number of external clock - * cycles. - */ -enum system_xosc_startup { - /** Wait one clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_1, - /** Wait two clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_2, - /** Wait four clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_4, - /** Wait eight clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_8, - /** Wait 16 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_16, - /** Wait 32 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_32, - /** Wait 64 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_64, - /** Wait 128 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_128, - /** Wait 256 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_256, - /** Wait 512 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_512, - /** Wait 1024 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_1024, - /** Wait 2048 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_4096, - /** Wait 8192 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_8192, - /** Wait 16384 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_32768, -}; - -/** - * \brief Available start-up times for the OSC32K. - * - * Available internal 32KHz oscillator start-up times, as a number of internal - * OSC32K clock cycles. - */ -enum system_osc32k_startup { - /** Wait three clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_3, - /** Wait four clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_4, - /** Wait six clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_6, - /** Wait ten clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_10, - /** Wait 18 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_18, - /** Wait 34 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_34, - /** Wait 66 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_66, - /** Wait 130 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_130, -}; - -/** - * \brief Division prescalers for the internal 8MHz system clock. - * - * Available prescalers for the internal 8MHz (nominal) system clock. - */ -enum system_osc8m_div { - /** Do not divide the 8MHz RC oscillator output. */ - SYSTEM_OSC8M_DIV_1, - /** Divide the 8MHz RC oscillator output by two. */ - SYSTEM_OSC8M_DIV_2, - /** Divide the 8MHz RC oscillator output by four. */ - SYSTEM_OSC8M_DIV_4, - /** Divide the 8MHz RC oscillator output by eight. */ - SYSTEM_OSC8M_DIV_8, -}; - -/** - * \brief Frequency range for the internal 8MHz RC oscillator. - * - * Internal 8MHz RC oscillator frequency range setting - */ -enum system_osc8m_frequency_range { - /** Frequency range 4MHz to 6MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6, - /** Frequency range 6MHz to 8MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8, - /** Frequency range 8MHz to 11MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11, - /** Frequency range 11MHz to 15MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15, -}; - -/** - * \brief Main CPU and APB/AHB bus clock source prescaler values. - * - * Available division ratios for the CPU and APB/AHB bus clocks. - */ -enum system_main_clock_div { - /** Divide Main clock by one. */ - SYSTEM_MAIN_CLOCK_DIV_1, - /** Divide Main clock by two. */ - SYSTEM_MAIN_CLOCK_DIV_2, - /** Divide Main clock by four. */ - SYSTEM_MAIN_CLOCK_DIV_4, - /** Divide Main clock by eight. */ - SYSTEM_MAIN_CLOCK_DIV_8, - /** Divide Main clock by 16. */ - SYSTEM_MAIN_CLOCK_DIV_16, - /** Divide Main clock by 32. */ - SYSTEM_MAIN_CLOCK_DIV_32, - /** Divide Main clock by 64. */ - SYSTEM_MAIN_CLOCK_DIV_64, - /** Divide Main clock by 128. */ - SYSTEM_MAIN_CLOCK_DIV_128, -}; - -/** - * \brief External clock source types. - * - * Available external clock source types. - */ -enum system_clock_external { - /** The external clock source is a crystal oscillator. */ - SYSTEM_CLOCK_EXTERNAL_CRYSTAL, - /** The connected clock source is an external logic level clock signal. */ - SYSTEM_CLOCK_EXTERNAL_CLOCK, -}; - -/** - * \brief Operating modes of the DFLL clock source. - * - * Available operating modes of the DFLL clock source module. - */ -enum system_clock_dfll_loop_mode { - /** The DFLL is operating in open loop mode with no feedback. */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, - /** The DFLL is operating in closed loop mode with frequency feedback from - * a low frequency reference clock. - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE, - -#ifdef SYSCTRL_DFLLCTRL_USBCRM - /** The DFLL is operating in USB recovery mode with frequency feedback - * from USB SOF. - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM, -#endif -}; - -/** - * \brief Locking behavior for the DFLL during device wake-up. - * - * DFLL lock behavior modes on device wake-up from sleep. - */ -enum system_clock_dfll_wakeup_lock { - /** Keep DFLL lock when the device wakes from sleep. */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, - /** Lose DFLL lock when the devices wakes from sleep. */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW, -}; - -/** - * \brief Fine tracking behavior for the DFLL once a lock has been acquired. - * - * DFLL fine tracking behavior modes after a lock has been acquired. - */ -enum system_clock_dfll_stable_tracking { - /** Keep tracking after the DFLL has gotten a fine lock. */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, - /** Stop tracking after the DFLL has gotten a fine lock. */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE, -}; - -/** - * \brief Chill-cycle behavior of the DFLL module. - * - * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period - * of time when the DFLL output frequency is not measured by the unit, to allow - * the output to stabilize after a change in the input clock source. - */ -enum system_clock_dfll_chill_cycle { - /** Enable a chill cycle, where the DFLL output frequency is not measured. */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, - /** Disable a chill cycle, where the DFLL output frequency is not measured. */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS, -}; - -/** - * \brief QuickLock settings for the DFLL module. - * - * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of - * the DFLL output frequency at the expense of accuracy. - */ -enum system_clock_dfll_quick_lock { - /** Enable the QuickLock feature for looser lock requirements on the DFLL. */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, - /** Disable the QuickLock feature for strict lock requirements on the DFLL. */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS, -}; - -/** - * \brief Available clock sources in the system. - * - * Clock sources available to the GCLK generators. - */ -enum system_clock_source { - /** Internal 8MHz RC oscillator. */ - SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M, - /** Internal 32KHz RC oscillator. */ - SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K, - /** External oscillator. */ - SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC , - /** External 32KHz oscillator. */ - SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K, - /** Digital Frequency Locked Loop (DFLL). */ - SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M, - /** Internal Ultra Low Power 32KHz oscillator. */ - SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K, - /** Generator input pad. */ - SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN, - /** Generic clock generator one output. */ - SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1, -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - /** Digital Phase Locked Loop (DPLL). - * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it. - */ - SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL, -#endif -}; - -/** - * \brief List of APB peripheral buses. - * - * Available bus clock domains on the APB bus. - */ -enum system_clock_apb_bus { - /** Peripheral bus A on the APB bus. */ - SYSTEM_CLOCK_APB_APBA, - /** Peripheral bus B on the APB bus. */ - SYSTEM_CLOCK_APB_APBB, - /** Peripheral bus C on the APB bus. */ - SYSTEM_CLOCK_APB_APBC, -}; - -/** - * \brief Configuration structure for XOSC. - * - * External oscillator clock configuration structure. - */ -struct system_clock_source_xosc_config { - /** External clock type. */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time. */ - enum system_xosc_startup startup_time; - /** Enable automatic amplitude gain control. */ - bool auto_gain_control; - /** External clock/crystal frequency. */ - uint32_t frequency; - /** Keep the XOSC enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC won't run - * until requested by a peripheral. */ - bool on_demand; -}; - -/** - * \brief Configuration structure for XOSC32K. - * - * External 32KHz oscillator clock configuration structure. - */ -struct system_clock_source_xosc32k_config { - /** External clock type. */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time. */ - enum system_xosc32k_startup startup_time; - /** Enable automatic amplitude control. */ - bool auto_gain_control; - /** Enable 1KHz output. */ - bool enable_1khz_output; - /** Enable 32KHz output. */ - bool enable_32khz_output; - /** External clock/crystal frequency. */ - uint32_t frequency; - /** Keep the XOSC32K enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC32K won't run - * until requested by a peripheral. */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock. */ - bool write_once; -}; - -/** - * \brief Configuration structure for OSC8M. - * - * Internal 8MHz (nominal) oscillator configuration structure. - */ -struct system_clock_source_osc8m_config { - /** Internal 8MHz RC oscillator prescaler. */ - enum system_osc8m_div prescaler; - /** Keep the OSC8M enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC8M won't run - * until requested by a peripheral. */ - bool on_demand; -}; - -/** - * \brief Configuration structure for OSC32K. - * - * Internal 32KHz (nominal) oscillator configuration structure. - */ -struct system_clock_source_osc32k_config { - /** Startup time. */ - enum system_osc32k_startup startup_time; - /** Enable 1KHz output. */ - bool enable_1khz_output; - /** Enable 32KHz output. */ - bool enable_32khz_output; - /** Keep the OSC32K enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC32K won't run - * until requested by a peripheral. */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock. */ - bool write_once; -}; - -/** - * \brief Configuration structure for DFLL. - * - * DFLL oscillator configuration structure. - */ -struct system_clock_source_dfll_config { - /** Loop mode. */ - enum system_clock_dfll_loop_mode loop_mode; - /** Run On Demand. If this is set the DFLL won't run - * until requested by a peripheral. */ - bool on_demand; - /** Enable Quick Lock. */ - enum system_clock_dfll_quick_lock quick_lock; - /** Enable Chill Cycle. */ - enum system_clock_dfll_chill_cycle chill_cycle; - /** DFLL lock state on wakeup. */ - enum system_clock_dfll_wakeup_lock wakeup_lock; - /** DFLL tracking after fine lock. */ - enum system_clock_dfll_stable_tracking stable_tracking; - /** Coarse calibration value (Open loop mode). */ - uint8_t coarse_value; - /** Fine calibration value (Open loop mode). */ - uint16_t fine_value; - /** Coarse adjustment maximum step size (Closed loop mode). */ - uint8_t coarse_max_step; - /** Fine adjustment maximum step size (Closed loop mode). */ - uint16_t fine_max_step; - /** DFLL multiply factor (Closed loop mode. */ - uint16_t multiply_factor; -}; - -/** - * \name External Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for XOSC. - * - * Fills a configuration structure with the default configuration for an - * external oscillator module: - * - External Crystal - * - Start-up time of 16384 external clock cycles - * - Automatic crystal gain control mode enabled - * - Frequency of 12MHz - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_xosc_get_config_defaults( - struct system_clock_source_xosc_config *const config) -{ - Assert(config); - - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC_STARTUP_16384; - config->auto_gain_control = true; - config->frequency = 12000000UL; - config->run_in_standby = false; - config->on_demand = true; -} - -void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config); - -/** - * @} - */ - - -/** - * \name External 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for XOSC32K. - * - * Fills a configuration structure with the default configuration for an - * external 32KHz oscillator module: - * - External Crystal - * - Start-up time of 16384 external clock cycles - * - Automatic crystal gain control mode disabled - * - Frequency of 32.768KHz - * - 1KHz clock output disabled - * - 32KHz clock output enabled - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - Don't lock registers after configuration has been written - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_xosc32k_get_config_defaults( - struct system_clock_source_xosc32k_config *const config) -{ - Assert(config); - - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC32K_STARTUP_16384; - config->auto_gain_control = false; - config->frequency = 32768UL; - config->enable_1khz_output = false; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->write_once = false; -} - -void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config); -/** - * @} - */ - - -/** - * \name Internal 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSC32K. - * - * Fills a configuration structure with the default configuration for an - * internal 32KHz oscillator module: - * - 1KHz clock output enabled - * - 32KHz clock output enabled - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - Set startup time to 130 cycles - * - Don't lock registers after configuration has been written - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osc32k_get_config_defaults( - struct system_clock_source_osc32k_config *const config) -{ - Assert(config); - - config->enable_1khz_output = true; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->startup_time = SYSTEM_OSC32K_STARTUP_130; - config->write_once = false; -} - -void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config); - -/** - * @} - */ - - -/** - * \name Internal 8MHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSC8M. - * - * Fills a configuration structure with the default configuration for an - * internal 8MHz (nominal) oscillator module: - * - Clock output frequency divided by a factor of eight - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osc8m_get_config_defaults( - struct system_clock_source_osc8m_config *const config) -{ - Assert(config); - - config->prescaler = SYSTEM_OSC8M_DIV_8; - config->run_in_standby = false; - config->on_demand = true; -} - -void system_clock_source_osc8m_set_config( - struct system_clock_source_osc8m_config *const config); - -/** - * @} - */ - - -/** - * \name Internal DFLL Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for DFLL. - * - * Fills a configuration structure with the default configuration for a - * DFLL oscillator module: - * - Open loop mode - * - QuickLock mode enabled - * - Chill cycle enabled - * - Output frequency lock maintained during device wake-up - * - Continuous tracking of the output frequency - * - Default tracking values at the mid-points for both coarse and fine - * tracking parameters - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_dfll_get_config_defaults( - struct system_clock_source_dfll_config *const config) -{ - Assert(config); - - config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN; - config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; - config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; - config->on_demand = true; - - /* Open loop mode calibration value */ - config->coarse_value = 0x1f / 4; /* Midpoint */ - config->fine_value = 0xff / 4; /* Midpoint */ - - /* Closed loop mode */ - config->coarse_max_step = 1; - config->fine_max_step = 1; - config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */ -} - -void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config); - -/** - * @} - */ - -/** - * \name Clock Source Management - * @{ - */ -enum status_code system_clock_source_write_calibration( - const enum system_clock_source system_clock_source, - const uint16_t calibration_value, - const uint8_t freq_range); - -enum status_code system_clock_source_enable( - const enum system_clock_source system_clock_source); - -enum status_code system_clock_source_disable( - const enum system_clock_source clk_source); - -bool system_clock_source_is_ready( - const enum system_clock_source clk_source); - -uint32_t system_clock_source_get_hz( - const enum system_clock_source clk_source); - -/** - * @} - */ - -/** - * \name Main Clock Management - * @{ - */ - -/** - * \brief Set main CPU clock divider. - * - * Sets the clock divider used on the main clock to provide the CPU clock. - * - * \param[in] divider CPU clock divider to set - */ -static inline void system_cpu_clock_set_divider( - const enum system_main_clock_div divider) -{ - Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider); - PM->CPUSEL.reg = (uint32_t)divider; -} - -/** - * \brief Retrieves the current frequency of the CPU core. - * - * Retrieves the operating frequency of the CPU core, obtained from the main - * generic clock and the set CPU bus divider. - * - * \return Current CPU frequency in Hz. - */ -static inline uint32_t system_cpu_clock_get_hz(void) -{ - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg); -} - -/** - * \brief Set APBx clock divider. - * - * Set the clock divider used on the main clock to provide the clock for the - * given APBx bus. - * - * \param[in] divider APBx bus divider to set - * \param[in] bus APBx bus to set divider - * - * \returns Status of the clock division change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given - * \retval STATUS_OK The APBx clock was set successfully - */ -static inline enum status_code system_apb_clock_set_divider( - const enum system_clock_apb_bus bus, - const enum system_main_clock_div divider) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBASEL.reg = (uint32_t)divider; - break; - case SYSTEM_CLOCK_APB_APBB: - PM->APBBSEL.reg = (uint32_t)divider; - break; - case SYSTEM_CLOCK_APB_APBC: - PM->APBCSEL.reg = (uint32_t)divider; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; - } - - /** - * \brief Retrieves the current frequency of a ABPx. - * - * Retrieves the operating frequency of an APBx bus, obtained from the main - * generic clock and the set APBx bus divider. - * - * \return Current APBx bus frequency in Hz. - */ - static inline uint32_t system_apb_clock_get_hz( - const enum system_clock_apb_bus bus) -{ - uint16_t bus_divider = 0; - - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - bus_divider = PM->APBASEL.reg; - break; - case SYSTEM_CLOCK_APB_APBB: - bus_divider = PM->APBBSEL.reg; - break; - case SYSTEM_CLOCK_APB_APBC: - bus_divider = PM->APBCSEL.reg; - break; - default: - Assert(false); - return 0; - } - - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider); -} - - -/** - * @} - */ - -/** - * \name Bus Clock Masking - * @{ - */ - -/** - * \brief Set bits in the clock mask for the AHB bus. - * - * This function will set bits in the clock mask for the AHB bus. - * Any bits set to 1 will enable that clock, 0 bits in the mask - * will be ignored. - * - * \param[in] ahb_mask AHB clock mask to enable - */ -static inline void system_ahb_clock_set_mask( - const uint32_t ahb_mask) -{ - PM->AHBMASK.reg |= ahb_mask; -} - -/** - * \brief Clear bits in the clock mask for the AHB bus. - * - * This function will clear bits in the clock mask for the AHB bus. - * Any bits set to 1 will disable that clock, 0 bits in the mask - * will be ignored. - * - * \param[in] ahb_mask AHB clock mask to disable - */ -static inline void system_ahb_clock_clear_mask( - const uint32_t ahb_mask) -{ - PM->AHBMASK.reg &= ~ahb_mask; -} - -/** - * \brief Set bits in the clock mask for an APBx bus. - * - * This function will set bits in the clock mask for an APBx bus. - * Any bits set to 1 will enable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_* - * constants from the device header files - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus given - * \retval STATUS_OK The clock mask was set successfully - */ -static inline enum status_code system_apb_clock_set_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBAMASK.reg |= mask; - break; - - case SYSTEM_CLOCK_APB_APBB: - PM->APBBMASK.reg |= mask; - break; - - case SYSTEM_CLOCK_APB_APBC: - PM->APBCMASK.reg |= mask; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; - } - - /** - * \brief Clear bits in the clock mask for an APBx bus. - * - * This function will clear bits in the clock mask for an APBx bus. - * Any bits set to 1 will disable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to clear clock mask bits - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given - * \retval STATUS_OK The clock mask was changed successfully - */ - static inline enum status_code system_apb_clock_clear_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBAMASK.reg &= ~mask; - break; - - case SYSTEM_CLOCK_APB_APBB: - PM->APBBMASK.reg &= ~mask; - break; - - case SYSTEM_CLOCK_APB_APBC: - PM->APBCMASK.reg &= ~mask; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; - } - - /** - * @} - */ - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - /** - * \brief Reference clock source of the DPLL module. - */ - enum system_clock_source_dpll_reference_clock { - /** Select XOSC32K as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K, - /** Select XOSC as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC, - /** Select GCLK as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, -}; - -/** - * \brief Lock time-out value of the DPLL module. - */ -enum system_clock_source_dpll_lock_time { - /** Set no time-out as default. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, - /** Set time-out if no lock within 8ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04, - /** Set time-out if no lock within 9ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS, - /** Set time-out if no lock within 10ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS, - /** Set time-out if no lock within 11ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS, -}; - -/** - * \brief Filter type of the DPLL module. - */ -enum system_clock_source_dpll_filter { - /** Default filter mode. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, - /** Low bandwidth filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER, - /** High bandwidth filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER, - /** High damping filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER, -}; - -/** - * \brief Configuration structure for DPLL. - * - * DPLL oscillator configuration structure. - */ -struct system_clock_source_dpll_config { - /** Run On Demand. If this is set the DPLL won't run - * until requested by a peripheral. */ - bool on_demand; - /** Keep the DPLL enabled in standby sleep mode. */ - bool run_in_standby; - /** Bypass lock signal. */ - bool lock_bypass; - /** Wake up fast. If this is set DPLL output clock is enabled after - * the startup time. */ - bool wake_up_fast; - /** Enable low power mode. */ - bool low_power_enable; - - /** Output frequency of the clock. */ - uint32_t output_frequency; - /** Reference frequency of the clock. */ - uint32_t reference_frequency; - /** Devider of reference clock. */ - uint16_t reference_divider; - - /** Filter type of the DPLL module. */ - enum system_clock_source_dpll_filter filter; - /** Lock time-out value of the DPLL module. */ - enum system_clock_source_dpll_lock_time lock_time; - /** Reference clock source of the DPLL module. */ - enum system_clock_source_dpll_reference_clock reference_clock; -}; - -/** - * \name Internal DPLL Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for DPLL. - * - * Fills a configuration structure with the default configuration for a - * DPLL oscillator module: - * - Run only when requested by peripheral (on demand) - * - Don't run in STANDBY sleep mode - * - Lock bypass disabled - * - Fast wake up disabled - * - Low power mode disabled - * - Output frequency is 48MHz - * - Reference clock frequency is 32768Hz - * - Not divide reference clock - * - Select REF0 as reference clock - * - Set lock time to default mode - * - Use default filter - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_dpll_get_config_defaults( - struct system_clock_source_dpll_config *const config) -{ - config->on_demand = true; - config->run_in_standby = false; - config->lock_bypass = false; - config->wake_up_fast = false; - config->low_power_enable = false; - - config->output_frequency = 48000000; - config->reference_frequency = 32768; - config->reference_divider = 1; - config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K; - - config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT; - config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT; -}; - -void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config); - -/* @} */ -#endif - -/** - * \name System Clock Initialization - * @{ - */ - -void system_clock_init(void); - -/** - * @} - */ - -/** - * \name System Flash Wait States - * @{ - */ - -/** - * \brief Set flash controller wait states. - * - * Will set the number of wait states that are used by the onboard - * flash memory. The number of wait states depend on both device - * supply voltage and CPU speed. The required number of wait states - * can be found in the electrical characteristics of the device. - * - * \param[in] wait_states Number of wait states to use for internal flash - */ -static inline void system_flash_set_waitstates(uint8_t wait_states) -{ - Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) == - ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos)); - - NVMCTRL->CTRLB.bit.RWS = wait_states; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver - * - * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DFLLDigital Frequency Locked Loop
MUXMultiplexer
OSC32KInternal 32KHz Oscillator
OSC8MInternal 8MHz Oscillator
PLLPhase Locked Loop
OSCOscillator
XOSCExternal Oscillator
XOSC32KExternal 32KHz Oscillator
AHBAdvanced High-performance Bus
APBAdvanced Peripheral Bus
DPLLDigital Phase Locked Loop
- * - * - * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_clock_extra_errata Errata - * - * - This driver implements experimental workaround for errata 9905 - * - * "The DFLL clock must be requested before being configured otherwise a - * write access to a DFLL register can freeze the device." - * This driver will enable and configure the DFLL before the ONDEMAND bit is set. - * - * - * \section asfdoc_sam0_system_clock_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
- * \li Corrected OSC32K startup time definitions - * \li Support locking of OSC32K and XOSC32K config register (default: false) - * \li Added DPLL support, functions added: - * \c system_clock_source_dpll_get_config_defaults() and - * \c system_clock_source_dpll_set_config() - * \li Moved gclk channel locking feature out of the config struct - * functions added: - * \c system_gclk_chan_lock(), - * \c system_gclk_chan_is_locked() - * \c system_gclk_chan_is_enabled() and - * \c system_gclk_gen_is_enabled() - *
Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled - * and configured to a failed/not running clock generator
- * \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false - * \li Fixed system_flash_set_waitstates() failing with an assertion - * if an odd number of wait states provided - *
- * \li Updated dfll configuration function to implement workaround for - * errata 9905 in the DFLL module - * \li Updated \c system_clock_init() to reset interrupt flags before - * they are used - * \li Fixed \c system_clock_source_get_hz() to return correcy DFLL - * frequency number - *
\li Fixed \c system_clock_source_is_ready not returning the correct - * state for \c SYSTEM_CLOCK_SOURCE_OSC8M - * \li Renamed the various \c system_clock_source_*_get_default_config() - * functions to \c system_clock_source_*_get_config_defaults() to - * match the remainder of ASF - * \li Added OSC8M calibration constant loading from the device signature - * row when the oscillator is initialized - * \li Updated default configuration of the XOSC32 to disable Automatic - * Gain Control due to silicon errata - *
Initial Release
- */ - -/** - * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple - * examples with step-by-step instructions to configure and use this driver in - * a selection of use cases. Note that QSGs can be compiled as a standalone - * application or be added to the user application. - * - * - \subpage asfdoc_sam0_system_clock_basic_use_case - * - \subpage asfdoc_sam0_system_gclk_basic_use_case - * - * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
E04/2015Added support for SAMDAx.
D12/2014Added support for SAMR21 and SAMD10/D11.
C01/2014Added support for SAMD21.
B06/2013Corrected documentation typos. Fixed missing steps in the Basic - * Use Case Quick Start Guide.
A06/2013Initial release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/gclk.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/gclk.c deleted file mode 100644 index 607818c2ede..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/gclk.c +++ /dev/null @@ -1,515 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Generic Clock Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval false if the module has completed synchronization - * \retval true if the module synchronization is ongoing - */ -static inline bool system_gclk_is_syncing(void) -{ - if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) { - return true; - } - - return false; -} - -/** - * \brief Initializes the GCLK driver. - * - * Initializes the Generic Clock module, disabling and resetting all active - * Generic Clock Generators and Channels to their power-on default values. - */ -void system_gclk_init(void) -{ - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK); - - /* Software reset the module to ensure it is re-initialized correctly */ - GCLK->CTRL.reg = GCLK_CTRL_SWRST; - while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) { - /* Wait for reset to complete */ - } -} - -/** - * \brief Writes a Generic Clock Generator configuration to the hardware module. - * - * Writes out a given configuration of a Generic Clock Generator configuration - * to the hardware module. - * - * \note Changing the clock source on the fly (on a running - * generator) can take additional time if the clock source is configured - * to only run on-demand (ONDEMAND bit is set) and it is not currently - * running (no peripheral is requesting the clock source). In this case - * the GCLK will request the new clock while still keeping a request to - * the old clock source until the new clock source is ready. - * - * \note This function will not start a generator that is not already running; - * to start the generator, call \ref system_gclk_gen_enable() - * after configuring a generator. - * - * \param[in] generator Generic Clock Generator index to configure - * \param[in] config Configuration settings for the generator - */ -void system_gclk_gen_set_config( - const uint8_t generator, - struct system_gclk_gen_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Cache new register configurations to minimize sync requirements. */ - uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos); - uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos); - - /* Select the requested source clock for the generator */ - new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos; - - /* Configure the clock to be either high or low when disabled */ - if (config->high_when_disabled) { - new_genctrl_config |= GCLK_GENCTRL_OOV; - } - - /* Configure if the clock output to I/O pin should be enabled. */ - if (config->output_enable) { - new_genctrl_config |= GCLK_GENCTRL_OE; - } - - /* Set division factor */ - if (config->division_factor > 1) { - /* Check if division is a power of two */ - if (((config->division_factor & (config->division_factor - 1)) == 0)) { - /* Determine the index of the highest bit set to get the - * division factor that must be loaded into the division - * register */ - - uint32_t div2_count = 0; - - uint32_t mask; - for (mask = (1UL << 1); mask < config->division_factor; - mask <<= 1) { - div2_count++; - } - - /* Set binary divider power of 2 division factor */ - new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos; - new_genctrl_config |= GCLK_GENCTRL_DIVSEL; - } else { - /* Set integer division factor */ - - new_gendiv_config |= - (config->division_factor) << GCLK_GENDIV_DIV_Pos; - - /* Enable non-binary division with increased duty cycle accuracy */ - new_genctrl_config |= GCLK_GENCTRL_IDC; - } - - } - - /* Enable or disable the clock in standby mode */ - if (config->run_in_standby) { - new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY; - } - - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - GCLK->GENDIV.reg = new_gendiv_config; - - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Enables a Generic Clock Generator that was previously configured. - * - * Starts the clock generation of a Generic Clock Generator that was previously - * configured via a call to \ref system_gclk_gen_set_config(). - * - * \param[in] generator Generic Clock Generator index to enable - */ -void system_gclk_gen_enable( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Enable generator */ - GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Disables a Generic Clock Generator that was previously enabled. - * - * Stops the clock generation of a Generic Clock Generator that was previously - * started via a call to \ref system_gclk_gen_enable(). - * - * \param[in] generator Generic Clock Generator index to disable - */ -void system_gclk_gen_disable( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Disable generator */ - GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; - while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) { - /* Wait for clock to become disabled */ - } - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock Generator is enabled. - * - * \param[in] generator Generic Clock Generator index to check - * - * \return The enabled status. - * \retval true The Generic Clock Generator is enabled - * \retval false The Generic Clock Generator is disabled - */ -bool system_gclk_gen_is_enabled( - const uint8_t generator) -{ - bool enabled; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - /* Obtain the enabled status */ - enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); - - system_interrupt_leave_critical_section(); - - return enabled; -} - -/** - * \brief Retrieves the clock frequency of a Generic Clock generator. - * - * Determines the clock frequency (in Hz) of a specified Generic Clock - * generator, used as a source to a Generic Clock Channel module. - * - * \param[in] generator Generic Clock Generator index - * - * \return The frequency of the generic clock generator, in Hz. - */ -uint32_t system_gclk_gen_get_hz( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the appropriate generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Get the frequency of the source connected to the GCLK generator */ - uint32_t gen_input_hz = system_clock_source_get_hz( - (enum system_clock_source)GCLK->GENCTRL.bit.SRC); - - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - - uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL; - - /* Select the appropriate generator division register */ - *((uint8_t*)&GCLK->GENDIV.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - uint32_t divider = GCLK->GENDIV.bit.DIV; - - system_interrupt_leave_critical_section(); - - /* Check if the generator is using fractional or binary division */ - if (!divsel && divider > 1) { - gen_input_hz /= divider; - } else if (divsel) { - gen_input_hz >>= (divider+1); - } - - return gen_input_hz; -} - -/** - * \brief Writes a Generic Clock configuration to the hardware module. - * - * Writes out a given configuration of a Generic Clock configuration to the - * hardware module. If the clock is currently running, it will be stopped. - * - * \note Once called the clock will not be running; to start the clock, - * call \ref system_gclk_chan_enable() after configuring a clock channel. - * - * \param[in] channel Generic Clock channel to configure - * \param[in] config Configuration settings for the clock - * - */ -void system_gclk_chan_set_config( - const uint8_t channel, - struct system_gclk_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Cache the new config to reduce sync requirements */ - uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos); - - /* Select the desired generic clock generator */ - new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos; - - /* Disable generic clock channel */ - system_gclk_chan_disable(channel); - - /* Write the new configuration */ - GCLK->CLKCTRL.reg = new_clkctrl_config; -} - -/** - * \brief Enables a Generic Clock that was previously configured. - * - * Starts the clock generation of a Generic Clock that was previously - * configured via a call to \ref system_gclk_chan_set_config(). - * - * \param[in] channel Generic Clock channel to enable - */ -void system_gclk_chan_enable( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Enable the generic clock */ - GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Disables a Generic Clock that was previously enabled. - * - * Stops the clock generation of a Generic Clock that was previously started - * via a call to \ref system_gclk_chan_enable(). - * - * \param[in] channel Generic Clock channel to disable - */ -void system_gclk_chan_disable( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Sanity check WRTLOCK */ - Assert(!GCLK->CLKCTRL.bit.WRTLOCK); - - /* Switch to known-working source so that the channel can be disabled */ - uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN; - GCLK->CLKCTRL.bit.GEN = 0; - - /* Disable the generic clock */ - GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN; - while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) { - /* Wait for clock to become disabled */ - } - - /* Restore previous configured clock generator */ - GCLK->CLKCTRL.bit.GEN = prev_gen_id; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock channel is enabled. - * - * \param[in] channel Generic Clock Channel index - * - * \return The enabled status. - * \retval true The Generic Clock channel is enabled - * \retval false The Generic Clock channel is disabled - */ -bool system_gclk_chan_is_enabled( - const uint8_t channel) -{ - bool enabled; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - enabled = GCLK->CLKCTRL.bit.CLKEN; - - system_interrupt_leave_critical_section(); - - return enabled; -} - -/** - * \brief Locks a Generic Clock channel from further configuration writes. - * - * Locks a generic clock channel from further configuration writes. It is only - * possible to unlock the channel configuration through a power on reset. - * - * \param[in] channel Generic Clock channel to enable - */ -void system_gclk_chan_lock( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Lock the generic clock */ - GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock channel is locked. - * - * \param[in] channel Generic Clock Channel index - * - * \return The lock status. - * \retval true The Generic Clock channel is locked - * \retval false The Generic Clock channel is not locked - */ -bool system_gclk_chan_is_locked( - const uint8_t channel) -{ - bool locked; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - locked = GCLK->CLKCTRL.bit.WRTLOCK; - - system_interrupt_leave_critical_section(); - - return locked; -} - -/** - * \brief Retrieves the clock frequency of a Generic Clock channel. - * - * Determines the clock frequency (in Hz) of a specified Generic Clock - * channel, used as a source to a device peripheral module. - * - * \param[in] channel Generic Clock Channel index - * - * \return The frequency of the generic clock channel, in Hz. - */ -uint32_t system_gclk_chan_get_hz( - const uint8_t channel) -{ - uint8_t gen_id; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - gen_id = GCLK->CLKCTRL.bit.GEN; - - system_interrupt_leave_critical_section(); - - /* Return the clock speed of the associated GCLK generator */ - return system_gclk_gen_get_hz(gen_id); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/clock.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/clock.h deleted file mode 100644 index 0d350428d50..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * \file - * - * \brief SAM Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_CLOCK_H_INCLUDED -#define SYSTEM_CLOCK_H_INCLUDED - -#include -#include -#include - -#endif /* SYSTEM_CLOCK_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/gclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/gclk.h deleted file mode 100644 index ea5edf5dab3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/gclk.h +++ /dev/null @@ -1,307 +0,0 @@ -/** - * \file - * - * \brief SAM Generic Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED -#define SYSTEM_CLOCK_GCLK_H_INCLUDED - -/** - * \addtogroup asfdoc_sam0_system_clock_group - * - * @{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief List of available GCLK generators. - * - * List of Available GCLK generators. This enum is used in the peripheral - * device drivers to select the GCLK generator to be used for its operation. - * - * The number of GCLK generators available is device dependent. - */ -enum gclk_generator { - /** GCLK generator channel 0 */ - GCLK_GENERATOR_0, -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0) - /** GCLK generator channel 1 */ - GCLK_GENERATOR_1, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1) - /** GCLK generator channel 2 */ - GCLK_GENERATOR_2, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2) - /** GCLK generator channel 3 */ - GCLK_GENERATOR_3, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3) - /** GCLK generator channel 4 */ - GCLK_GENERATOR_4, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4) - /** GCLK generator channel 5 */ - GCLK_GENERATOR_5, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5) - /** GCLK generator channel 6 */ - GCLK_GENERATOR_6, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6) - /** GCLK generator channel 7 */ - GCLK_GENERATOR_7, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7) - /** GCLK generator channel 8 */ - GCLK_GENERATOR_8, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8) - /** GCLK generator channel 9 */ - GCLK_GENERATOR_9, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9) - /** GCLK generator channel 10 */ - GCLK_GENERATOR_10, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10) - /** GCLK generator channel 11 */ - GCLK_GENERATOR_11, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11) - /** GCLK generator channel 12 */ - GCLK_GENERATOR_12, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12) - /** GCLK generator channel 13 */ - GCLK_GENERATOR_13, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13) - /** GCLK generator channel 14 */ - GCLK_GENERATOR_14, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14) - /** GCLK generator channel 15 */ - GCLK_GENERATOR_15, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15) - /** GCLK generator channel 16 */ - GCLK_GENERATOR_16, -#endif -}; - -/** - * \brief Generic Clock Generator configuration structure. - * - * Configuration structure for a Generic Clock Generator channel. This - * structure should be initialized by the - * \ref system_gclk_gen_get_config_defaults() function before being modified by - * the user application. - */ -struct system_gclk_gen_config { - /** Source clock input channel index, see the \ref system_clock_source */ - uint8_t source_clock; - /** If \c true, the generator output level is high when disabled */ - bool high_when_disabled; - /** Integer division factor of the clock output compared to the input */ - uint32_t division_factor; - /** If \c true, the clock is kept enabled during device standby mode */ - bool run_in_standby; - /** If \c true, enables GCLK generator clock output to a GPIO pin */ - bool output_enable; -}; - -/** - * \brief Generic Clock configuration structure. - * - * Configuration structure for a Generic Clock channel. This structure - * should be initialized by the \ref system_gclk_chan_get_config_defaults() - * function before being modified by the user application. - */ -struct system_gclk_chan_config { - /** Generic Clock Generator source channel */ - enum gclk_generator source_generator; -}; - -/** \name Generic Clock Management - * @{ - */ -void system_gclk_init(void); - -/** @} */ - - -/** - * \name Generic Clock Management (Generators) - * @{ - */ - -/** - * \brief Initializes a Generic Clock Generator configuration structure to defaults. - * - * Initializes a given Generic Clock Generator configuration structure to - * a set of known default values. This function should be called on all - * new instances of these configuration structures before being modified - * by the user application. - * - * The default configuration is: - * \li Clock is generated undivided from the source frequency - * \li Clock generator output is low when the generator is disabled - * \li The input clock is sourced from input clock channel 0 - * \li Clock will be disabled during sleep - * \li The clock output will not be routed to a physical GPIO pin - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void system_gclk_gen_get_config_defaults( - struct system_gclk_gen_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->division_factor = 1; - config->high_when_disabled = false; -#if SAML21 - config->source_clock = GCLK_SOURCE_OSC16M; -#elif (SAMC20) || (SAMC21) - config->source_clock = GCLK_SOURCE_OSC48M; -#else - config->source_clock = GCLK_SOURCE_OSC8M; -#endif - config->run_in_standby = false; - config->output_enable = false; -} - -void system_gclk_gen_set_config( - const uint8_t generator, - struct system_gclk_gen_config *const config); - -void system_gclk_gen_enable( - const uint8_t generator); - -void system_gclk_gen_disable( - const uint8_t generator); - -bool system_gclk_gen_is_enabled( - const uint8_t generator); - -/** @} */ - - -/** - * \name Generic Clock Management (Channels) - * @{ - */ - -/** - * \brief Initializes a Generic Clock configuration structure to defaults. - * - * Initializes a given Generic Clock configuration structure to a set of - * known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Clock is sourced from the Generic Clock Generator channel 0 - * \li Clock configuration will not be write-locked when set - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void system_gclk_chan_get_config_defaults( - struct system_gclk_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->source_generator = GCLK_GENERATOR_0; -} - -void system_gclk_chan_set_config( - const uint8_t channel, - struct system_gclk_chan_config *const config); - -void system_gclk_chan_enable( - const uint8_t channel); - -void system_gclk_chan_disable( - const uint8_t channel); - -bool system_gclk_chan_is_enabled( - const uint8_t channel); - -void system_gclk_chan_lock( - const uint8_t channel); - -bool system_gclk_chan_is_locked( - const uint8_t channel); - -/** @} */ - - -/** - * \name Generic Clock Frequency Retrieval - * @{ - */ - -uint32_t system_gclk_gen_get_hz( - const uint8_t generator); - -uint32_t system_gclk_chan_get_hz( - const uint8_t channel); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMD21/system_interrupt_features.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMD21/system_interrupt_features.h deleted file mode 100644 index 1179b3e59c5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMD21/system_interrupt_features.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - * \file - * - * \brief SAM D21 System Interrupt Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED -#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED - -#if !defined(__DOXYGEN__) - -/* Generates a interrupt vector table enum list entry for a given module type - and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */ -# define _MODULE_IRQn(n, module) \ - SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn, - -/* Generates interrupt vector table enum list entries for all instances of a - given module type on the selected device. */ -# define _SYSTEM_INTERRUPT_MODULES(name) \ - MREPEAT(name##_INST_NUM, _MODULE_IRQn, name) - -# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f -# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000003 - -# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0 - -# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 30 -#endif - -/** - * \addtogroup asfdoc_sam0_system_interrupt_group - * @{ - */ - -/** - * \brief Table of possible system interrupt/exception vector numbers. - * - * Table of all possible interrupt and exception vector indexes within the - * SAMD21 device. Check peripherals configuration in SAMD21 datasheet for - * available vector index for specific device. - * - */ -#if defined(__DOXYGEN__) -/** \note The actual enumeration name is "system_interrupt_vector". */ -enum system_interrupt_vector_samd21 { -#else -enum system_interrupt_vector { -#endif - /** Interrupt vector index for a NMI interrupt. */ - SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn, - /** Interrupt vector index for a Hard Fault memory access exception. */ - SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn, - /** Interrupt vector index for a Supervisor Call exception. */ - SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn, - /** Interrupt vector index for a Pending Supervisor interrupt. */ - SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn, - /** Interrupt vector index for a System Tick interrupt. */ - SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn, - - /** Interrupt vector index for a Power Manager peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn, - /** Interrupt vector index for a System Control peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn, - /** Interrupt vector index for a Watch Dog peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn, - /** Interrupt vector index for a Real Time Clock peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn, - /** Interrupt vector index for an External Interrupt peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn, - /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */ - SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn, - /** Interrupt vector index for a Direct Memory Access interrupt. */ - SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn, -#if defined(__DOXYGEN__) || defined(ID_USB) - /** Interrupt vector index for a Universal Serial Bus interrupt. */ - SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn, -#endif - /** Interrupt vector index for an Event System interrupt. */ - SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn, -#if defined(__DOXYGEN__) - /** Interrupt vector index for a SERCOM peripheral interrupt. - * - * Each specific device may contain several SERCOM peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_SERCOM0). - */ - SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn, - - /** Interrupt vector index for a Timer/Counter Control peripheral interrupt. - * - * Each specific device may contain several TCC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TCC0). - */ - SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn, - - /** Interrupt vector index for a Timer/Counter peripheral interrupt. - * - * Each specific device may contain several TC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TC3). - */ - SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn, -#else - _SYSTEM_INTERRUPT_MODULES(SERCOM) - - _SYSTEM_INTERRUPT_MODULES(TCC) - - SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn, - SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn, - SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn, -# if defined(ID_TC6) - SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn, -# endif -# if defined(ID_TC7) - SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn, -# endif -#endif - -#if defined(__DOXYGEN__) || defined(ID_ADC) - /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn, -#endif - -#if defined(__DOXYGEN__) || defined(ID_AC) - /** Interrupt vector index for an Analog Comparator peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn, -#endif - -#if defined(__DOXYGEN__) || defined(ID_DAC) - /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn, -#endif -#if defined(__DOXYGEN__) || defined(ID_PTC) - /** Interrupt vector index for a Peripheral Touch Controller peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn, -#endif -#if defined(__DOXYGEN__) || defined(ID_I2S) - /** Interrupt vector index for a Inter-IC Sound Interface peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn, -#endif -#if defined(__DOXYGEN__) || defined(ID_AC1) - /** Interrupt vector index for an Analog Comparator 1 peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_AC1 = AC1_IRQn, -#endif -}; - -/** @} */ - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAML21/system_interrupt_features.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAML21/system_interrupt_features.h deleted file mode 100644 index 2b565282f93..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAML21/system_interrupt_features.h +++ /dev/null @@ -1,176 +0,0 @@ -/** - * \file - * - * \brief SAM L21 System Interrupt Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED -#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED - -#if !defined(__DOXYGEN__) - -/* Generates a interrupt vector table enum list entry for a given module type - and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */ -# define _MODULE_IRQn(n, module) \ - SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn, - -/* Generates interrupt vector table enum list entries for all instances of a - given module type on the selected device. */ -# define _SYSTEM_INTERRUPT_MODULES(name) \ - MREPEAT(name##_INST_NUM, _MODULE_IRQn, name) - -# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f -# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000003 - -# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0 - -# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 30 -#endif - -/** - * \addtogroup asfdoc_sam0_system_interrupt_group - * @{ - */ - -/** - * \brief Table of possible system interrupt/exception vector numbers. - * - * Table of all possible interrupt and exception vector indexes within the - * SAML21 device. - */ -#if defined(__DOXYGEN__) -/** \note The actual enumeration name is "system_interrupt_vector". */ -enum system_interrupt_vector_saml21 { -#else -enum system_interrupt_vector { -#endif - /** Interrupt vector index for a NMI interrupt. */ - SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn, - /** Interrupt vector index for a Hard Fault memory access exception. */ - SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn, - /** Interrupt vector index for a Supervisor Call exception. */ - SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn, - /** Interrupt vector index for a Pending Supervisor interrupt. */ - SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn, - /** Interrupt vector index for a System Tick interrupt. */ - SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn, - - /** Interrupt vector index for MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_SYSTEM = SYSTEM_IRQn, - /** Interrupt vector index for a Watch Dog peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn, - /** Interrupt vector index for a Real Time Clock peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn, - /** Interrupt vector index for an External Interrupt peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn, - /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */ - SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn, - /** Interrupt vector index for a Direct Memory Access interrupt. */ - SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn, - /** Interrupt vector index for a Universal Serial Bus interrupt. */ - SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn, - /** Interrupt vector index for an Event System interrupt. */ - SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn, -#if defined(__DOXYGEN__) - /** Interrupt vector index for a SERCOM peripheral interrupt. - * - * Each specific device may contain several SERCOM peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_SERCOM0). - */ - SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn, - - /** Interrupt vector index for a Timer/Counter Control peripheral interrupt. - * - * Each specific device may contain several TCC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TCC0). - */ - SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn, - - /** Interrupt vector index for a Timer/Counter peripheral interrupt. - * - * Each specific device may contain several TC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TC3). - */ - SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn, -#else - _SYSTEM_INTERRUPT_MODULES(SERCOM) - - _SYSTEM_INTERRUPT_MODULES(TCC) -#if (SAML21J) - _SYSTEM_INTERRUPT_MODULES(TC) -#else - SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn, - SYSTEM_INTERRUPT_MODULE_TC1 = TC1_IRQn, - SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn, -#endif -#endif - - /** Interrupt vector index for an Analog Comparator peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn, - /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn, - /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn, - /** Interrupt vector index for a Peripheral Touch Controller peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn, - /** Interrupt vector index for a AES peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_AES = AES_IRQn, - /** Interrupt vector index for a TRNG peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_TRNG = TRNG_IRQn, - /** Interrupt vector index for a PICOP peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_PICOP = PICOP_IRQn, -}; - -/** @} */ - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMR21/system_interrupt_features.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMR21/system_interrupt_features.h deleted file mode 100644 index 0984dc8f5de..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMR21/system_interrupt_features.h +++ /dev/null @@ -1,165 +0,0 @@ -/** - * \file - * - * \brief SAM R21 System Interrupt Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED -#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED - -#if !defined(__DOXYGEN__) - -/* Generates a interrupt vector table enum list entry for a given module type - and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */ -# define _MODULE_IRQn(n, module) \ - SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn, - -/* Generates interrupt vector table enum list entries for all instances of a - given module type on the selected device. */ -# define _SYSTEM_INTERRUPT_MODULES(name) \ - MREPEAT(name##_INST_NUM, _MODULE_IRQn, name) - -# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f -# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000003 - -# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0 - -# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 30 -#endif - -/** - * \addtogroup asfdoc_sam0_system_interrupt_group - * @{ - */ - -/** - * \brief Table of possible system interrupt/exception vector numbers. - * - * Table of all possible interrupt and exception vector indexes within the - * SAMR21 device. - */ -#if defined(__DOXYGEN__) -/** \note The actual enumeration name is "system_interrupt_vector". */ -enum system_interrupt_vector_samr21 { -#else -enum system_interrupt_vector { -#endif - /** Interrupt vector index for a NMI interrupt. */ - SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn, - /** Interrupt vector index for a Hard Fault memory access exception. */ - SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn, - /** Interrupt vector index for a Supervisor Call exception. */ - SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn, - /** Interrupt vector index for a Pending Supervisor interrupt. */ - SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn, - /** Interrupt vector index for a System Tick interrupt. */ - SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn, - - /** Interrupt vector index for a Power Manager peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn, - /** Interrupt vector index for a System Control peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn, - /** Interrupt vector index for a Watch Dog peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn, - /** Interrupt vector index for a Real Time Clock peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn, - /** Interrupt vector index for an External Interrupt peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn, - /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */ - SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn, - /** Interrupt vector index for a Direct Memory Access interrupt. */ - SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn, - /** Interrupt vector index for a Universal Serial Bus interrupt. */ - SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn, - /** Interrupt vector index for an Event System interrupt. */ - SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn, -#if defined(__DOXYGEN__) - /** Interrupt vector index for a SERCOM peripheral interrupt. - * - * Each specific device may contain several SERCOM peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_SERCOM0). - */ - SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn, - - /** Interrupt vector index for a Timer/Counter Control peripheral interrupt. - * - * Each specific device may contain several TCC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TCC0). - */ - SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn, - - /** Interrupt vector index for a Timer/Counter peripheral interrupt. - * - * Each specific device may contain several TC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TC3). - */ - SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn, -#else - _SYSTEM_INTERRUPT_MODULES(SERCOM) - - _SYSTEM_INTERRUPT_MODULES(TCC) - - SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn, - SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn, - SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn, - -#endif - - /** Interrupt vector index for an Analog Comparator peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn, - /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn, - /** Interrupt vector index for a Peripheral Touch Controller peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn, -}; - -/** @} */ - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.c deleted file mode 100644 index 072d38e28a0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.c +++ /dev/null @@ -1,217 +0,0 @@ -/** - * \file - * - * \brief SAM System Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "system_interrupt.h" - -/** - * \brief Check if a interrupt line is pending. - * - * Checks if the requested interrupt vector is pending. - * - * \param[in] vector Interrupt vector number to check - * - * \returns A boolean identifying if the requested interrupt vector is pending. - * - * \retval true Specified interrupt vector is pending - * \retval false Specified interrupt vector is not pending - * - */ -bool system_interrupt_is_pending( - const enum system_interrupt_vector vector) -{ - bool result; - - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - result = ((NVIC->ISPR[0] & (1 << vector)) != 0); - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0); - } else { - Assert(false); - result = false; - } - - return result; -} - -/** - * \brief Set a interrupt vector as pending. - * - * Set the requested interrupt vector as pending (i.e. issues a software - * interrupt request for the specified vector). The software handler will be - * handled (if enabled) in a priority order based on vector number and - * configured priority settings. - * - * \param[in] vector Interrupt vector number which is set as pending - * - * \returns Status code identifying if the vector was successfully set as - * pending. - * - * \retval STATUS_OK If no error was detected - * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given - */ -enum status_code system_interrupt_set_pending( - const enum system_interrupt_vector vector) -{ - enum status_code status = STATUS_OK; - - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - NVIC->ISPR[0] = (1 << vector); - } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) { - /* Note: Because NMI has highest priority it will be executed - * immediately after it has been set pending */ - SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk; - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; - } else { - /* The user want to set something unsupported as pending */ - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } - - return status; -} - -/** - * \brief Clear pending interrupt vector. - * - * Clear a pending interrupt vector, so the software handler is not executed. - * - * \param[in] vector Interrupt vector number to clear - * - * \returns A status code identifying if the interrupt pending state was - * successfully cleared. - * - * \retval STATUS_OK If no error was detected - * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given - */ -enum status_code system_interrupt_clear_pending( - const enum system_interrupt_vector vector) -{ - enum status_code status = STATUS_OK; - - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - NVIC->ICPR[0] = (1 << vector); - } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) { - /* Note: Clearing of NMI pending interrupts does not make sense and is - * not supported by the device, as it has the highest priority and will - * always be executed at the moment it is set */ - return STATUS_ERR_INVALID_ARG; - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; - } else { - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } - - return status; -} - -/** - * \brief Set interrupt vector priority level. - * - * Set the priority level of an external interrupt or exception. - * - * \param[in] vector Interrupt vector to change - * \param[in] priority_level New vector priority level to set - * - * \returns Status code indicating if the priority level of the interrupt was - * successfully set. - * - * \retval STATUS_OK If no error was detected - * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given - */ -enum status_code system_interrupt_set_priority( - const enum system_interrupt_vector vector, - const enum system_interrupt_priority_level priority_level) -{ - enum status_code status = STATUS_OK; - - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - uint8_t register_num = vector / 4; - uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS); - - NVIC->IP[register_num] = - (NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) | - (priority_level << priority_pos); - - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS); - } else { - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } - - return status; -} - -/** - * \brief Get interrupt vector priority level. - * - * Retrieves the priority level of the requested external interrupt or exception. - * - * \param[in] vector Interrupt vector of which the priority level will be read - * - * \return Currently configured interrupt priority level of the given interrupt - * vector. - */ -enum system_interrupt_priority_level system_interrupt_get_priority( - const enum system_interrupt_vector vector) -{ - uint8_t register_num = vector / 4; - uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS); - - enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0; - - if (vector >= 0) { - priority = (enum system_interrupt_priority_level) - ((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK); - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - priority = (enum system_interrupt_priority_level) - ((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK); - } - - return priority; -} - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.h deleted file mode 100644 index c6d09e9fdad..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.h +++ /dev/null @@ -1,428 +0,0 @@ -/** - * \file - * - * \brief SAM System Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_INTERRUPT_H_INCLUDED -#define SYSTEM_INTERRUPT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt Driver (SYSTEM INTERRUPT) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of internal software and hardware interrupts/exceptions. - * - * The following peripherals are used by this module: - * - NVIC (Nested Vector Interrupt Controller) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_interrupt_prerequisites - * - \ref asfdoc_sam0_system_interrupt_module_overview - * - \ref asfdoc_sam0_system_interrupt_special_considerations - * - \ref asfdoc_sam0_system_interrupt_extra_info - * - \ref asfdoc_sam0_system_interrupt_examples - * - \ref asfdoc_sam0_system_interrupt_api_overview - * - * - * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_interrupt_module_overview Module Overview - * - * The ARM® Cortex® M0+ core contains an interrupt and exception vector table, which - * can be used to configure the device's interrupt handlers; individual - * interrupts and exceptions can be enabled and disabled, as well as configured - * with a variable priority. - * - * This driver provides a set of wrappers around the core interrupt functions, - * to expose a simple API for the management of global and individual interrupts - * within the device. - * - * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections - * In some applications it is important to ensure that no interrupts may be - * executed by the system whilst a critical portion of code is being run; for - * example, a buffer may be copied from one context to another - during which - * interrupts must be disabled to avoid corruption of the source buffer contents - * until the copy has completed. This driver provides a basic API to enter and - * exit nested critical sections, so that global interrupts can be kept disabled - * for as long as necessary to complete a critical application code section. - * - * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts - * For some applications, it may be desirable to raise a module or core - * interrupt via software. For this reason, a set of APIs to set an interrupt or - * exception as pending are provided to the user application. - * - * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations - * - * Interrupts from peripherals in the SAM devices are on a per-module basis; - * an interrupt raised from any source within a module will cause a single, - * module-common handler to execute. It is the user application or driver's - * responsibility to de-multiplex the module-common interrupt to determine the - * exact interrupt cause. - * - * \section asfdoc_sam0_system_interrupt_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes: - * - \ref asfdoc_sam0_system_interrupt_extra_acronyms - * - \ref asfdoc_sam0_system_interrupt_extra_dependencies - * - \ref asfdoc_sam0_system_interrupt_extra_errata - * - \ref asfdoc_sam0_system_interrupt_extra_history - * - * - * \section asfdoc_sam0_system_interrupt_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_system_interrupt_exqsg. - * - * \section asfdoc_sam0_system_interrupt_api_overview API Overview - * @{ - */ - -#include -#include -#include "system_interrupt_features.h" - -/** - * \brief Table of possible system interrupt/exception vector priorities. - * - * Table of all possible interrupt and exception vector priorities within the - * device. - */ -enum system_interrupt_priority_level { - /** Priority level 0, the highest possible interrupt priority. */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0, - /** Priority level 1. */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1, - /** Priority level 2. */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2, - /** Priority level 3, the lowest possible interrupt priority. */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3, -}; - -/** - * \name Critical Section Management - * @{ - */ - -/** - * \brief Enters a critical section. - * - * Disables global interrupts. To support nested critical sections, an internal - * count of the critical section nesting will be kept, so that global interrupts - * are only re-enabled upon leaving the outermost nested critical section. - * - */ -static inline void system_interrupt_enter_critical_section(void) -{ - cpu_irq_enter_critical(); -} - -/** - * \brief Leaves a critical section. - * - * Enables global interrupts. To support nested critical sections, an internal - * count of the critical section nesting will be kept, so that global interrupts - * are only re-enabled upon leaving the outermost nested critical section. - * - */ -static inline void system_interrupt_leave_critical_section(void) -{ - cpu_irq_leave_critical(); -} - -/** @} */ - -/** - * \name Interrupt Enabling/Disabling - * @{ - */ - -/** - * \brief Check if global interrupts are enabled. - * - * Checks if global interrupts are currently enabled. - * - * \returns A boolean that identifies if the global interrupts are enabled or not. - * - * \retval true Global interrupts are currently enabled - * \retval false Global interrupts are currently disabled - * - */ -static inline bool system_interrupt_is_global_enabled(void) -{ - return cpu_irq_is_enabled(); -} - -/** - * \brief Enables global interrupts. - * - * Enables global interrupts in the device to fire any enabled interrupt handlers. - */ -static inline void system_interrupt_enable_global(void) -{ - cpu_irq_enable(); -} - -/** - * \brief Disables global interrupts. - * - * Disabled global interrupts in the device, preventing any enabled interrupt - * handlers from executing. - */ -static inline void system_interrupt_disable_global(void) -{ - cpu_irq_disable(); -} - -/** - * \brief Checks if an interrupt vector is enabled or not. - * - * Checks if a specific interrupt vector is currently enabled. - * - * \param[in] vector Interrupt vector number to check - * - * \returns A variable identifying if the requested interrupt vector is enabled. - * - * \retval true Specified interrupt vector is currently enabled - * \retval false Specified interrupt vector is currently disabled - * - */ -static inline bool system_interrupt_is_enabled( - const enum system_interrupt_vector vector) -{ - return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001); -} - -/** - * \brief Enable interrupt vector. - * - * Enables execution of the software handler for the requested interrupt vector. - * - * \param[in] vector Interrupt vector to enable - */ -static inline void system_interrupt_enable( - const enum system_interrupt_vector vector) -{ - NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f)); -} - -/** - * \brief Disable interrupt vector. - * - * Disables execution of the software handler for the requested interrupt vector. - * - * \param[in] vector Interrupt vector to disable - */ -static inline void system_interrupt_disable( - const enum system_interrupt_vector vector) -{ - NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f)); -} - -/** @} */ - -/** - * \name Interrupt State Management - * @{ - */ - -/** - * \brief Get active interrupt (if any). - * - * Return the vector number for the current executing software handler, if any. - * - * \return Interrupt number that is currently executing. - */ -static inline enum system_interrupt_vector system_interrupt_get_active(void) -{ - uint32_t IPSR = __get_IPSR(); - /* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */ - return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16); -} - -bool system_interrupt_is_pending( - const enum system_interrupt_vector vector); - -enum status_code system_interrupt_set_pending( - const enum system_interrupt_vector vector); - -enum status_code system_interrupt_clear_pending( - const enum system_interrupt_vector vector); - -/** @} */ - -/** - * \name Interrupt Priority Management - * @{ - */ - -enum status_code system_interrupt_set_priority( - const enum system_interrupt_vector vector, - const enum system_interrupt_priority_level priority_level); - -enum system_interrupt_priority_level system_interrupt_get_priority( - const enum system_interrupt_vector vector); - -/** @} */ - -/** @} */ - -/** - * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver - * - * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
ISRInterrupt Service Routine
NMINon-maskable Interrupt
SERCOMSerial Communication Interface
- * - * - * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_interrupt_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_system_interrupt_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial Release
- */ - -/** - * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_system_interrupt_critsec_use_case - * - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case - * - * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
E06/2015Add support for SAML21, SAMDAx, and SAMC20/C21.
D12/2014Add support for SAMR21 and SAMD10/D11.
C01/2014Add support for SAMD21.
B06/2013Corrected documentation typos.
A06/2013Initial release
- */ - -#ifdef __cplusplus -} -#endif - -#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.c deleted file mode 100644 index 6763c734842..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.c +++ /dev/null @@ -1,311 +0,0 @@ -/** - * \file - * - * \brief SAM Pin Multiplexer Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -/** - * \internal - * Writes out a given configuration of a Port pin configuration to the - * hardware module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[in] port Base of the PORT module to configure - * \param[in] pin_mask Mask of the port pin to configure - * \param[in] config Configuration settings for the pin - */ -static void _system_pinmux_config( - PortGroup *const port, - const uint32_t pin_mask, - const struct system_pinmux_config *const config) -{ - Assert(port); - Assert(config); - - /* Track the configuration bits into a temporary variable before writing */ - uint32_t pin_cfg = 0; - - /* Enabled powersave mode, don't create configuration */ - if (!config->powersave) { - /* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will - * be written later) and store the new MUX mask */ - if (config->mux_position != SYSTEM_PINMUX_GPIO) { - pin_cfg |= PORT_WRCONFIG_PMUXEN; - pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos); - } - - /* Check if the user has requested that the input buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Enable input buffer flag */ - pin_cfg |= PORT_WRCONFIG_INEN; - - /* Enable pull-up/pull-down control flag if requested */ - if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) { - pin_cfg |= PORT_WRCONFIG_PULLEN; - } - - /* Clear the port DIR bits to disable the output buffer */ - port->DIRCLR.reg = pin_mask; - } - - /* Check if the user has requested that the output buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Cannot use a pull-up if the output driver is enabled, - * if requested the input buffer can only sample the current - * output state */ - pin_cfg &= ~PORT_WRCONFIG_PULLEN; - } - } else { - port->DIRCLR.reg = pin_mask; - } - - /* The Write Configuration register (WRCONFIG) requires the - * pins to to grouped into two 16-bit half-words - split them out here */ - uint32_t lower_pin_mask = (pin_mask & 0xFFFF); - uint32_t upper_pin_mask = (pin_mask >> 16); - - /* Configure the lower 16-bits of the port to the desired configuration, - * including the pin peripheral multiplexer just in case it is enabled */ - port->WRCONFIG.reg - = (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) | - pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG; - - /* Configure the upper 16-bits of the port to the desired configuration, - * including the pin peripheral multiplexer just in case it is enabled */ - port->WRCONFIG.reg - = (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) | - pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG | - PORT_WRCONFIG_HWSEL; - - if(!config->powersave) { - /* Set the pull-up state once the port pins are configured if one was - * requested and it does not violate the valid set of port - * configurations */ - if (pin_cfg & PORT_WRCONFIG_PULLEN) { - /* Set the OUT register bits to enable the pull-up if requested, - * clear to enable pull-down */ - if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) { - port->OUTSET.reg = pin_mask; - } else { - port->OUTCLR.reg = pin_mask; - } - } - - /* Check if the user has requested that the output buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Set the port DIR bits to enable the output buffer */ - port->DIRSET.reg = pin_mask; - } - } -} - -/** - * \brief Writes a Port pin configuration to the hardware module. - * - * Writes out a given configuration of a Port pin configuration to the hardware - * module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] config Configuration settings for the pin - */ -void system_pinmux_pin_set_config( - const uint8_t gpio_pin, - const struct system_pinmux_config *const config) -{ - PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - _system_pinmux_config(port, pin_mask, config); -} - -/** - * \brief Writes a Port pin group configuration to the hardware module. - * - * Writes out a given configuration of a Port pin group configuration to the - * hardware module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] config Configuration settings for the pin - */ -void system_pinmux_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct system_pinmux_config *const config) -{ - Assert(port); - - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - _system_pinmux_config(port, (1UL << i), config); - } - } -} - -/** - * \brief Configures the input sampling mode for a group of pins. - * - * Configures the input sampling mode for a group of pins, to - * control when the physical I/O pin value is sampled and - * stored inside the microcontroller. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] mode New pin sampling mode to configure - */ -void system_pinmux_group_set_input_sample_mode( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_sample mode) -{ - Assert(port); - - if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) { - port->CTRL.reg |= mask; - } else { - port->CTRL.reg &= ~mask; - } -} - -#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER -/** - * \brief Configures the output slew rate mode for a group of pins. - * - * Configures the output slew rate mode for a group of pins, to - * control the speed at which the physical output pin can react to - * logical changes of the I/O pin value. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] mode New pin slew rate mode to configure - */ -void system_pinmux_group_set_output_slew_rate( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_slew_rate mode) -{ - Assert(port); - - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) { - port->PINCFG[i].reg |= PORT_PINCFG_SLEWLIM; - } else { - port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM; - } - } - } -} -#endif - -#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH -/** - * \brief Configures the output driver strength mode for a group of pins. - * - * Configures the output drive strength for a group of pins, to - * control the amount of current the pad is able to sink/source. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] mode New output driver strength mode to configure - */ -void system_pinmux_group_set_output_strength( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_strength mode) -{ - Assert(port); - - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) { - port->PINCFG[i].reg |= PORT_PINCFG_DRVSTR; - } else { - port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR; - } - } - } -} -#endif - -#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN -/** - * \brief Configures the output driver mode for a group of pins. - * - * Configures the output driver mode for a group of pins, to - * control the pad behavior. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] mode New pad output driver mode to configure - */ -void system_pinmux_group_set_output_drive( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_drive mode) -{ - Assert(port); - - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) { - port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN; - } else { - port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN; - } - } - } -} -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.h deleted file mode 100644 index c894c57b6e5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.h +++ /dev/null @@ -1,675 +0,0 @@ -/** - * \file - * - * \brief SAM Pin Multiplexer Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef PINMUX_H_INCLUDED -#define PINMUX_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer Driver (SYSTEM PINMUX) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the - * configuration and management of the device's physical I/O Pins, to alter the - * direction and input/drive characteristics as well as to configure the pin - * peripheral multiplexer selection. - * - * The following peripherals are used by this module: - * - PORT (Port I/O Management) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * Physically, the modules are interconnected within the device as shown in the - * following diagram: - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_pinmux_prerequisites - * - \ref asfdoc_sam0_system_pinmux_module_overview - * - \ref asfdoc_sam0_system_pinmux_special_considerations - * - \ref asfdoc_sam0_system_pinmux_extra_info - * - \ref asfdoc_sam0_system_pinmux_examples - * - \ref asfdoc_sam0_system_pinmux_api_overview - * - * - * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_pinmux_module_overview Module Overview - * - * The SAM devices contain a number of General Purpose I/O pins, used to - * interface the user application logic and internal hardware peripherals to - * an external system. The Pin Multiplexer (PINMUX) driver provides a method - * of configuring the individual pin peripheral multiplexers to select - * alternate pin functions. - * - * \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTHSAML21, SAMC20/C21
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins - * SAM devices use two naming conventions for the I/O pins in the device; one - * physical and one logical. Each physical pin on a device package is assigned - * both a physical port and pin identifier (e.g. "PORTA.0") as well as a - * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the - * former is used to map physical pins to their physical internal device module - * counterparts, for simplicity the design of this driver uses the logical GPIO - * numbers instead. - * - * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing - * SAM devices contain a peripheral MUX, which is individually controllable - * for each I/O pin of the device. The peripheral MUX allows you to select the - * function of a physical package pin - whether it will be controlled as a user - * controllable GPIO pin, or whether it will be connected internally to one of - * several peripheral modules (such as an I2C module). When a pin is - * configured in GPIO mode, other peripherals connected to the same pin will be - * disabled. - * - * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics - * There are several special modes that can be selected on one or more I/O pins - * of the device, which alter the input and output characteristics of the pad. - * - * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength - * The Drive Strength configures the strength of the output driver on the - * pad. Normally, there is a fixed current limit that each I/O pin can safely - * drive, however some I/O pads offer a higher drive mode which increases this - * limit for that I/O pin at the expense of an increased power consumption. - * - * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate - * The Slew Rate configures the slew rate of the output driver, limiting the - * rate at which the pad output voltage can change with time. - * - * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode - * The Input Sample Mode configures the input sampler buffer of the pad. By - * default, the input buffer is only sampled "on-demand", i.e. when the user - * application attempts to read from the input buffer. This mode is the most - * power efficient, but increases the latency of the input sample by two clock - * cycles of the port clock. To reduce latency, the input sampler can instead - * be configured to always sample the input buffer on each port clock cycle, at - * the expense of an increased power consumption. - * - * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection - * - * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows - * how this module is interconnected within the device: - * - * \anchor asfdoc_sam0_system_pinmux_intconnections - * \dot - * digraph overview { - * node [label="Port Pad" shape=square] pad; - * - * subgraph driver { - * node [label="Peripheral MUX" shape=trapezium] pinmux; - * node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio; - * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals; - * } - * - * pinmux -> gpio; - * pad -> pinmux; - * pinmux -> peripherals; - * } - * \enddot - * - * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations - * - * The SAM port pin input sampling mode is set in groups of four physical - * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins - * will configure the sampling mode of the entire sub-group. - * - * High Drive Strength output driver mode is not available on all device pins - - * refer to your device specific datasheet. - * - * - * \section asfdoc_sam0_system_pinmux_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes: - * - \ref asfdoc_sam0_system_pinmux_extra_acronyms - * - \ref asfdoc_sam0_system_pinmux_extra_dependencies - * - \ref asfdoc_sam0_system_pinmux_extra_errata - * - \ref asfdoc_sam0_system_pinmux_extra_history - * - * - * \section asfdoc_sam0_system_pinmux_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_system_pinmux_exqsg. - * - * - * \section asfdoc_sam0_system_pinmux_api_overview API Overview - * @{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*@{*/ -#if (SAML21) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** Output Driver Strength Selection feature support. */ -# define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH -#endif -/*@}*/ - -/** Peripheral multiplexer index to select GPIO mode for a pin. */ -#define SYSTEM_PINMUX_GPIO (1 << 7) - -/** - * \brief Port pin direction configuration enum. - * - * Enum for the possible pin direction settings of the port pin configuration - * structure, to indicate the direction the pin should use. - */ -enum system_pinmux_pin_dir { - /** The pin's input buffer should be enabled, so that the pin state can - * be read. */ - SYSTEM_PINMUX_PIN_DIR_INPUT, - /** The pin's output buffer should be enabled, so that the pin state can - * be set (but not read back). */ - SYSTEM_PINMUX_PIN_DIR_OUTPUT, - /** The pin's output and input buffers should both be enabled, so that the - * pin state can be set and read back. */ - SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, -}; - -/** - * \brief Port pin input pull configuration enum. - * - * Enum for the possible pin pull settings of the port pin configuration - * structure, to indicate the type of logic level pull the pin should use. - */ -enum system_pinmux_pin_pull { - /** No logical pull should be applied to the pin. */ - SYSTEM_PINMUX_PIN_PULL_NONE, - /** Pin should be pulled up when idle. */ - SYSTEM_PINMUX_PIN_PULL_UP, - /** Pin should be pulled down when idle. */ - SYSTEM_PINMUX_PIN_PULL_DOWN, -}; - -/** - * \brief Port pin digital input sampling mode enum. - * - * Enum for the possible input sampling modes for the port pin configuration - * structure, to indicate the type of sampling a port pin should use. - */ -enum system_pinmux_pin_sample { - /** Pin input buffer should continuously sample the pin state. */ - SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS, - /** Pin input buffer should be enabled when the IN register is read. */ - SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND, -}; - -/** - * \brief Port pin configuration structure. - * - * Configuration structure for a port pin instance. This structure should be - * structure should be initialized by the - * \ref system_pinmux_get_config_defaults() function before being modified by - * the user application. - */ -struct system_pinmux_config { - /** MUX index of the peripheral that should control the pin, if peripheral - * control is desired. For GPIO use, this should be set to - * \ref SYSTEM_PINMUX_GPIO. */ - uint8_t mux_position; - - /** Port buffer input/output direction. */ - enum system_pinmux_pin_dir direction; - - /** Logic level pull of the input buffer. */ - enum system_pinmux_pin_pull input_pull; - - /** Enable lowest possible powerstate on the pin. - * - * \note All other configurations will be ignored, the pin will be disabled. - */ - bool powersave; -}; - -/** \name Configuration and Initialization - * @{ - */ - -/** - * \brief Initializes a Port pin configuration structure to defaults. - * - * Initializes a given Port pin configuration structure to a set of - * known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Non peripheral (i.e. GPIO) controlled - * \li Input mode with internal pull-up enabled - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void system_pinmux_get_config_defaults( - struct system_pinmux_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->mux_position = SYSTEM_PINMUX_GPIO; - config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - config->powersave = false; -} - -void system_pinmux_pin_set_config( - const uint8_t gpio_pin, - const struct system_pinmux_config *const config); - -void system_pinmux_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct system_pinmux_config *const config); - -/** @} */ - -/** \name Special Mode Configuration (Physical Group Orientated) - * @{ - */ - -/** - * \brief Retrieves the PORT module group instance from a given GPIO pin number. - * - * Retrieves the PORT module group instance associated with a given logical - * GPIO pin number. - * - * \param[in] gpio_pin Index of the GPIO pin to convert - * - * \return Base address of the associated PORT module. - */ -static inline PortGroup* system_pinmux_get_group_from_gpio_pin( - const uint8_t gpio_pin) -{ - uint8_t port_index = (gpio_pin / 128); - uint8_t group_index = (gpio_pin / 32); - - /* Array of available ports. */ - Port *const ports[PORT_INST_NUM] = PORT_INSTS; - - if (port_index < PORT_INST_NUM) { - return &(ports[port_index]->Group[group_index]); - } else { - Assert(false); - return NULL; - } -} - -void system_pinmux_group_set_input_sample_mode( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_sample mode); - -/** @} */ - -/** \name Special Mode Configuration (Logical Pin Orientated) - * @{ - */ - -/** - * \brief Retrieves the currently selected MUX position of a logical pin. - * - * Retrieves the selected MUX peripheral on a given logical GPIO pin. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * - * \return Currently selected peripheral index on the specified pin. - */ -static inline uint8_t system_pinmux_pin_get_mux_position( - const uint8_t gpio_pin) -{ - PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) { - return SYSTEM_PINMUX_GPIO; - } - - uint32_t pmux_reg = port->PMUX[pin_index / 2].reg; - - if (pin_index & 1) { - return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - } else { - return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - } -} - -/** - * \brief Configures the input sampling mode for a GPIO pin. - * - * Configures the input sampling mode for a GPIO input, to - * control when the physical I/O pin value is sampled and - * stored inside the microcontroller. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] mode New pin sampling mode to configure - */ -static inline void system_pinmux_pin_set_input_sample_mode( - const uint8_t gpio_pin, - const enum system_pinmux_pin_sample mode) -{ - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) { - port->CTRL.reg |= (1 << pin_index); - } else { - port->CTRL.reg &= ~(1 << pin_index); - } -} - -/** @} */ - -#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH -/** - * \brief Port pin drive output strength enum. - * - * Enum for the possible output drive strengths for the port pin - * configuration structure, to indicate the driver strength the pin should - * use. - */ -enum system_pinmux_pin_strength { - /** Normal output driver strength. */ - SYSTEM_PINMUX_PIN_STRENGTH_NORMAL, - /** High current output driver strength. */ - SYSTEM_PINMUX_PIN_STRENGTH_HIGH, -}; - -/** - * \brief Configures the output driver strength mode for a GPIO pin. - * - * Configures the output drive strength for a GPIO output, to - * control the amount of current the pad is able to sink/source. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] mode New output driver strength mode to configure - */ -static inline void system_pinmux_pin_set_output_strength( - const uint8_t gpio_pin, - const enum system_pinmux_pin_strength mode) -{ - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_DRVSTR; - } else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR; - } -} - -void system_pinmux_group_set_output_strength( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_strength mode); -#endif - -#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER -/** - * \brief Port pin output slew rate enum. - * - * Enum for the possible output drive slew rates for the port pin - * configuration structure, to indicate the driver slew rate the pin should - * use. - */ -enum system_pinmux_pin_slew_rate { - /** Normal pin output slew rate. */ - SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL, - /** Enable slew rate limiter on the pin. */ - SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED, -}; - -/** - * \brief Configures the output slew rate mode for a GPIO pin. - * - * Configures the output slew rate mode for a GPIO output, to - * control the speed at which the physical output pin can react to - * logical changes of the I/O pin value. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] mode New pin slew rate mode to configure - */ -static inline void system_pinmux_pin_set_output_slew_rate( - const uint8_t gpio_pin, - const enum system_pinmux_pin_slew_rate mode) -{ - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_SLEWLIM; - } else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM; - } -} - -void system_pinmux_group_set_output_slew_rate( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_slew_rate mode); -#endif - -#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN -/** - * \brief Port pin output drive mode enum. - * - * Enum for the possible output drive modes for the port pin configuration - * structure, to indicate the output mode the pin should use. - */ -enum system_pinmux_pin_drive { - /** Use totem pole output drive mode. */ - SYSTEM_PINMUX_PIN_DRIVE_TOTEM, - /** Use open drain output drive mode. */ - SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN, -}; - -/** - * \brief Configures the output driver mode for a GPIO pin. - * - * Configures the output driver mode for a GPIO output, to - * control the pad behavior. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] mode New pad output driver mode to configure - */ -static inline void system_pinmux_pin_set_output_drive( - const uint8_t gpio_pin, - const enum system_pinmux_pin_drive mode) -{ - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_ODRAIN; - } else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN; - } -} - -void system_pinmux_group_set_output_drive( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_drive mode); -#endif - -#ifdef __cplusplus -} -#endif - -/** @} */ - -/** - * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver - * - * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
GPIOGeneral Purpose Input/Output
MUXMultiplexer
- * - * - * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_pinmux_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_system_pinmux_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Removed code of open drain, slew limit and drive strength - * features
Fixed broken sampling mode function implementations, which wrote - * corrupt configuration values to the device registers
Added missing NULL pointer asserts to the PORT driver functions
Initial Release
- */ - -/** - * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple - * examples with step-by-step instructions to configure and use this driver in a - * selection of use cases. Note that QSGs can be compiled as a standalone - * application or be added to the user application. - * - * - \subpage asfdoc_sam0_system_pinmux_basic_use_case - * - * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
F06/2015Add support for SAML21, SAMDAx, and SAMC20/C21.
E12/2014Add support for SAMR21 and SAMD10/D11.
D01/2014Add support for SAMD21.
C09/2013Fixed incorrect documentation for the device pin sampling mode.
B06/2013Corrected documentation typos.
A06/2013Initial release
- */ - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMD21/power.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMD21/power.h deleted file mode 100644 index c0920ab668a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMD21/power.h +++ /dev/null @@ -1,224 +0,0 @@ -/** - * \file - * - * \brief SAM Power related functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef POWER_H_INCLUDED -#define POWER_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_system_group - * @{ - */ - -/** - * \brief Voltage references within the device. - * - * List of available voltage references (VREF) that may be used within the - * device. - */ -enum system_voltage_reference { - /** Temperature sensor voltage reference. */ - SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE, - /** Bandgap voltage reference. */ - SYSTEM_VOLTAGE_REFERENCE_BANDGAP, -}; - -/** - * \brief Device sleep modes. - * - * List of available sleep modes in the device. A table of clocks available in - * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode. - */ -enum system_sleepmode { - /** IDLE 0 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_0, - /** IDLE 1 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_1, - /** IDLE 2 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_2, - /** Standby sleep mode. */ - SYSTEM_SLEEPMODE_STANDBY, -}; - - - -/** - * \name Voltage References - * @{ - */ - -/** - * \brief Enable the selected voltage reference - * - * Enables the selected voltage reference source, making the voltage reference - * available on a pin as well as an input source to the analog peripherals. - * - * \param[in] vref Voltage reference to enable - */ -static inline void system_voltage_reference_enable( - const enum system_voltage_reference vref) -{ - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN; - break; - - case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: - SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN; - break; - - default: - Assert(false); - return; - } -} - -/** - * \brief Disable the selected voltage reference - * - * Disables the selected voltage reference source. - * - * \param[in] vref Voltage reference to disable - */ -static inline void system_voltage_reference_disable( - const enum system_voltage_reference vref) -{ - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN; - break; - - case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: - SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; - break; - - default: - Assert(false); - return; - } -} - -/** - * @} - */ - - -/** - * \name Device Sleep Control - * @{ - */ - -/** - * \brief Set the sleep mode of the device - * - * Sets the sleep mode of the device; the configured sleep mode will be entered - * upon the next call of the \ref system_sleep() function. - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode. - * - * \param[in] sleep_mode Sleep mode to configure for the next sleep operation - * - * \retval STATUS_OK Operation completed successfully - * \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not - * available - */ -static inline enum status_code system_set_sleepmode( - const enum system_sleepmode sleep_mode) -{ -#if (SAMD20 || SAMD21) - /* Errata: Make sure that the Flash does not power all the way down - * when in sleep mode. */ - NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val; -#endif - - switch (sleep_mode) { - case SYSTEM_SLEEPMODE_IDLE_0: - case SYSTEM_SLEEPMODE_IDLE_1: - case SYSTEM_SLEEPMODE_IDLE_2: - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - PM->SLEEP.reg = sleep_mode; - break; - - case SYSTEM_SLEEPMODE_STANDBY: - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - break; - - default: - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Put the system to sleep waiting for interrupt - * - * Executes a device DSB (Data Synchronization Barrier) instruction to ensure - * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt) - * instruction to place the device into the sleep mode specified by - * \ref system_set_sleepmode until woken by an interrupt. - */ -static inline void system_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * @} - */ - -/** @} */ -#ifdef __cplusplus -} -#endif - -#endif /* POWER_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAML21/power.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAML21/power.h deleted file mode 100644 index 8bce873c267..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAML21/power.h +++ /dev/null @@ -1,889 +0,0 @@ -/** - * \file - * - * \brief SAM L21 Power functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef POWER_H_INCLUDED -#define POWER_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_system_group - * @{ - */ - -/** - * \brief Device sleep modes. - * - * List of available sleep modes in the device. A table of clocks available in - * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode. - */ -enum system_sleepmode { - /** IDLE sleep mode */ - SYSTEM_SLEEPMODE_IDLE = PM_SLEEPCFG_SLEEPMODE(0x2), - /** STANDBY sleep mode */ - SYSTEM_SLEEPMODE_STANDBY = PM_SLEEPCFG_SLEEPMODE_STANDBY, - /** BACKUP sleep mode */ - SYSTEM_SLEEPMODE_BACKUP = PM_SLEEPCFG_SLEEPMODE_BACKUP, - /** OFF sleep mode */ - SYSTEM_SLEEPMODE_OFF = PM_SLEEPCFG_SLEEPMODE_OFF, -}; - -/** - * \brief Performance level. - * - * List of performance levels. Performance level technique consists of - * adjusting the regulator output voltage to reduce power consumption. - */ -enum system_performance_level { - /** Performance level 0 */ - SYSTEM_PERFORMANCE_LEVEL_0 = PM_PLCFG_PLSEL_PL0, - /** Performance level 2 */ - SYSTEM_PERFORMANCE_LEVEL_2 = PM_PLCFG_PLSEL_PL2, -}; - -/** - * \brief RAM Back-biasing mode. - * - * List of RAM back bias modes. By default, in standby sleep mode, - * RAM is in low power mode (back biased) if its power domain is in - * retention state. This behavior can be changed by configuring the Back Bias - * bit groups in STDBYCFG(STDBYCFG.BBIASxx). - */ -enum system_ram_back_bias_mode { - /** Retention Back biasing mode */ - SYSTEM_RAM_BACK_BIAS_RETENTION = 0, - /** Standby Back Biasing mode */ - SYSTEM_RAM_BACK_BIAS_STANDBY, - /** Standby OFF mode */ - SYSTEM_RAM_BACK_BIAS_STANDBY_OFF, - /** Always OFF mode */ - SYSTEM_RAM_BACK_BIAS_OFF, -}; - -/** - * \brief Linked power domain. - * - * List of linked power domains. Power domains can be linked to each other. - * It allows a power domain (PDn) to be kept in active state if the inferior - * power domain (PDn-1) is in active state too. - */ -enum system_linked_power_domain { - /** Power domains PD0/PD1/PD2 are not linked */ - SYSTEM_LINKED_POWER_DOMAIN_DEFAULT = PM_STDBYCFG_LINKPD_DEFAULT_Val, - /** Power domains PD0 and PD1 are linked */ - SYSTEM_LINKED_POWER_DOMAIN_PD01 = PM_STDBYCFG_LINKPD_PD01_Val, - /** Power domains PD1 and PD2 are linked */ - SYSTEM_LINKED_POWER_DOMAIN_PD12 = PM_STDBYCFG_LINKPD_PD12_Val, - /** All Power domains are linked */ - SYSTEM_LINKED_POWER_DOMAIN_PD012 = PM_STDBYCFG_LINKPD_PD012_Val, -}; - -/** - * \brief Power domain. - * - * List of power domains. Power domain gating technique consists of turning - * on or off power domain voltage to save power while keeping other domains - * powered up. - */ -enum system_power_domain { - /** All power domains switching are handled by hardware */ - SYSTEM_POWER_DOMAIN_DEFAULT = PM_STDBYCFG_PDCFG_DEFAULT_Val, - /** Power domain 0 (PD0) is forced ACTIVE */ - SYSTEM_POWER_DOMAIN_PD0 = PM_STDBYCFG_PDCFG_PD0_Val, - /** Power domain 0 and 1 (PD0 and PD1) are forced ACTIVE */ - SYSTEM_POWER_DOMAIN_PD01 = PM_STDBYCFG_PDCFG_PD01_Val, - /** All power domains are forced ACTIVE */ - SYSTEM_POWER_DOMAIN_PD012 = PM_STDBYCFG_PDCFG_PD012_Val, -}; - -/** - * \brief Voltage regulator. - * - * Voltage regulators selection. In active mode, the voltage regulator - * can be chosen on the fly between a LDO or a Buck converter. - */ -enum system_voltage_regulator_sel { - /** The voltage regulator in active mode is a LDO voltage regulator */ - SYSTEM_VOLTAGE_REGULATOR_LDO = SUPC_VREG_SEL_LDO_Val, - /** The voltage regulator in active mode is a buck converter */ - SYSTEM_VOLTAGE_REGULATOR_BUCK = SUPC_VREG_SEL_BUCK_Val, -}; - -/** - * \brief Low power efficiency. - * - * Low power mode efficiency. - */ -enum system_voltage_regulator_low_power_efficiency { - /** The voltage regulator in Low power mode has the default efficiency and - support the whole VDD range (1.62V to 3.6V) */ - SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT, - /** The voltage regulator in Low power mode has the highest efficiency and - support the limited VDD range (2.5V to 3.6V) */ - SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_HIGHTEST, -}; - -/** - * \brief Voltage reference value. - * - * Voltage references selection. - */ -enum system_voltage_references_sel { - /** 1.0V voltage reference typical value */ - SYSTEM_VOLTAGE_REFERENCE_1V0 = SUPC_VREF_SEL_1V0_Val, - /** 1.1V voltage reference typical value */ - SYSTEM_VOLTAGE_REFERENCE_1V1 = SUPC_VREF_SEL_1V1_Val, - /** 1.2V voltage reference typical value */ - SYSTEM_VOLTAGE_REFERENCE_1V2 = SUPC_VREF_SEL_1V2_Val, - /** 1.25V voltage reference typical value */ - SYSTEM_VOLTAGE_REFERENCE_1V25 = SUPC_VREF_SEL_1V25_Val, - /** 2.0V voltage reference typical value */ - SYSTEM_VOLTAGE_REFERENCE_2V0 = SUPC_VREF_SEL_2V0_Val, - /** 2.2V voltage reference typical value */ - SYSTEM_VOLTAGE_REFERENCE_2V2 = SUPC_VREF_SEL_2V2_Val, - /** 2.4V voltage reference typical value */ - SYSTEM_VOLTAGE_REFERENCE_2V4 = SUPC_VREF_SEL_2V4_Val, - /** 2.5V voltage reference typical value */ - SYSTEM_VOLTAGE_REFERENCE_2V5 = SUPC_VREF_SEL_2V5_Val, -}; - -/** - * \brief Battery power switch configuration enum. - * - * Enum for Battery power switch modes. - */ -enum system_battery_power_switch { - /** The backup domain is always supplied by main power */ - SYSTEM_BATTERY_POWER_SWITCH_NONE = SUPC_BBPS_CONF_NONE_Val, - /** The power switch is handled by the automatic power switch */ - SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC = SUPC_BBPS_CONF_APWS_Val, - /** The backup domain is always supplied by battery backup power */ - SYSTEM_BATTERY_POWER_SWITCH_FORCED = SUPC_BBPS_CONF_FORCED_Val, - /** The power switch is handled by the BOD33 */ - SYSTEM_BATTERY_POWER_SWITCH_BOD33 = SUPC_BBPS_CONF_BOD33_Val, -}; - -/** - * \brief Voltage reference. - * - * List of available voltage references (VREF) that may be used within the - * device. - */ -enum system_voltage_reference { - /** Temperature sensor voltage reference */ - SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE, - /** Voltage reference output */ - SYSTEM_VOLTAGE_REFERENCE_OUTPUT, -}; - -/** - * \brief Backup IO enum. - * - * List of Backup input and output pins. - * If enabled (\ref system_backup_pin_output_enable), the pins can be driven - * by the SUPC. - */ -enum system_backup_pin { - /** Power Supply OK status pin */ - SYSTEM_BACKUP_PIN_PSOK = (0x1 << 0), - /** Backup output pin 0 */ - SYSTEM_BACKUP_PIN_OUT_0 = (0x1 << 1), - /** Backup output pin 1 */ - SYSTEM_BACKUP_PIN_OUT_1 = (0x1 << 2) -}; - -/** - * \brief Standby configuration. - * - * Configuration structure for standby mode. - */ -struct system_standby_config { - /** Power domain */ - enum system_power_domain power_domain; - /** Enable dynamic power gating for power domain 0 */ - bool enable_dpgpd0; - /** Enable dynamic power gating for power domain 1 */ - bool enable_dpgpd1; - /** Automatic VREG switching disable */ - bool disable_avregsd; - /** Linked power domain */ - enum system_linked_power_domain linked_power_domain; - /** Back bias for HMCRAMCHS */ - enum system_ram_back_bias_mode hmcramchs_back_bias; - /** Back bias for HMCRAMCLP */ - enum system_ram_back_bias_mode hmcramclp_back_bias; -}; - -/** - * \brief Voltage Regulator System (VREG) Control configuration. - * - * Configuration structure for VREG. - */ -struct system_voltage_regulator_config { - /** Voltage scaling period */ - uint8_t voltage_scale_period; - /** Voltage scaling voltage step */ - uint8_t voltage_scale_step; - /** Run in standby in standby sleep mode */ - bool run_in_standby; - /** Voltage Regulator Selection */ - enum system_voltage_regulator_sel regulator_sel; - /** Low power efficiency */ - enum system_voltage_regulator_low_power_efficiency low_power_efficiency; -}; - -/** - * \brief Voltage References System (VREF) Control configuration. - * - * Configuration structure for VREF. - */ -struct system_voltage_references_config { - /** Voltage References Selection */ - enum system_voltage_references_sel sel; - /** On Demand Control */ - bool on_demand; - /** Run in standby */ - bool run_in_standby; -}; - -/** - * \brief Battery Backup Power Switch (BBPS) Control configuration. - * - * Configuration structure for Battery Backup Power Switch (BBPS). - */ -struct system_battery_backup_power_switch_config { - /** Enable device wake up when BBPS switches from - battery backup power to main power */ - bool wake_enabled; - /** Battery backup power switch configuration */ - enum system_battery_power_switch battery_power_switch; -}; - -/** - * \name Voltage Regulator - * @{ - */ - -/** - * \brief Retrieve the default configuration for voltage regulator. - * - * Fills a configuration structure with the default configuration: - * - Voltage scaling period is 1μs - * - Voltage scaling voltage step is 2*min_step - * - The voltage regulator is in low power mode in Standby sleep mode - * - The voltage regulator in active mode is an LDO voltage regulator - * - The voltage regulator in Low power mode has the default efficiency - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_voltage_regulator_get_config_defaults( - struct system_voltage_regulator_config *const config) -{ - Assert(config); - config->voltage_scale_period = 0; - config->voltage_scale_step = 0; - config->run_in_standby = false; - config->regulator_sel = SYSTEM_VOLTAGE_REGULATOR_LDO; - config->low_power_efficiency = SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT; -} - -/** - * \brief Configure voltage regulator. - * - * Configures voltage regulator with the given configuration. - * - * \param[in] config Voltage regulator configuration structure containing - * the new config - */ -static inline void system_voltage_regulator_set_config( - struct system_voltage_regulator_config *const config) -{ - Assert(config); - SUPC->VREG.bit.VSPER = config->voltage_scale_period; - SUPC->VREG.bit.VSVSTEP = config->voltage_scale_step; - SUPC->VREG.bit.RUNSTDBY = config->run_in_standby; - SUPC->VREG.bit.SEL = config->regulator_sel; - SUPC->VREG.bit.LPEFF = config->low_power_efficiency; - while(!(SUPC->STATUS.reg & SUPC_STATUS_VREGRDY)) { - ; - } -} - -/** -* \brief Enable the selected voltage regulator. - * - * Enables the selected voltage regulator source. - */ -static inline void system_voltage_regulator_enable(void) -{ - SUPC->VREG.reg |= SUPC_VREG_ENABLE; -} - -/** - * \brief Disable the selected voltage regulator. - * - * Disables the selected voltage regulator. - */ -static inline void system_voltage_regulator_disable(void) -{ - SUPC->VREG.reg &= ~SUPC_VREG_ENABLE; -} - -/** - * @} - */ - -/** - * \name Voltage References - * @{ - */ - -/** - * \brief Retrieve the default configuration for voltage reference. - * - * Fill a configuration structure with the default configuration: - * - 1.0V voltage reference typical value - * - On demand control disabled - * - The voltage reference and the temperature sensor are halted during standby sleep mode - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_voltage_reference_get_config_defaults( - struct system_voltage_references_config *const config) -{ - Assert(config); - config->sel = SYSTEM_VOLTAGE_REFERENCE_1V0; - config->on_demand = false; - config->run_in_standby = false; -} - -/** - * \brief Configure voltage reference. - * - * Configures voltage reference with the given configuration. - * - * \param[in] config Voltage reference configuration structure containing - * the new config - */ -static inline void system_voltage_reference_set_config( - struct system_voltage_references_config *const config) -{ - Assert(config); - SUPC->VREF.bit.SEL = config->sel; - SUPC->VREF.bit.ONDEMAND = config->on_demand; - SUPC->VREF.bit.RUNSTDBY = config->run_in_standby; -} - -/** - * \brief Enable the selected voltage reference. - * - * Enables the selected voltage reference source, making the voltage reference - * available on a pin as well as an input source to the analog peripherals. - * - * \param[in] vref Voltage reference to enable - */ -static inline void system_voltage_reference_enable( - const enum system_voltage_reference vref) -{ - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SUPC->VREF.reg |= SUPC_VREF_TSEN; - break; - case SYSTEM_VOLTAGE_REFERENCE_OUTPUT: - SUPC->VREF.reg |= SUPC_VREF_VREFOE; - break; - default: - Assert(false); - return; - } -} - -/** - * \brief Disable the selected voltage reference. - * - * Disables the selected voltage reference source. - * - * \param[in] vref Voltage reference to disable - */ -static inline void system_voltage_reference_disable( - const enum system_voltage_reference vref) -{ - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SUPC->VREF.reg &= ~SUPC_VREF_TSEN; - break; - case SYSTEM_VOLTAGE_REFERENCE_OUTPUT: - SUPC->VREF.reg &= ~SUPC_VREF_VREFOE; - break; - default: - Assert(false); - return; - } -} - -/** - * @} - */ - -/** - * \name Battery Backup Power Switch - * @{ - */ - -/** - * \brief Retrieve the default configuration for battery backup power switch control. - * - * Fills a configuration structure with the default configuration: - * - The main Power Supply OK status is not available on the PSOK pin - * - The device is not woken up when switched from battery backup power to main power - * - The backup domain is always supplied by main power - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_battery_backup_power_switch_get_config_defaults( - struct system_battery_backup_power_switch_config *const config) -{ - Assert(config); - config->wake_enabled = false; - config->battery_power_switch = SYSTEM_BATTERY_POWER_SWITCH_NONE; -} - -/** - * \brief Configure battery backup power switch. - * - * Configures battery backup power switch with the given configuration. - * - * \param[in] config Battery backup power switch configuration structure containing - * the new config - */ -static inline void system_battery_backup_power_switch_set_config( - struct system_battery_backup_power_switch_config *const config) -{ - Assert(config); - uint32_t new_config = SUPC->BBPS.reg & SUPC_BBPS_PSOKEN; - - if(config->wake_enabled) { - new_config |= SUPC_BBPS_WAKEEN; - } - - new_config |= SUPC_BBPS_CONF(config->battery_power_switch); - - SUPC->BBPS.reg = new_config; - - if (config->battery_power_switch == SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC) { - while (!(SUPC->STATUS.reg & SUPC_STATUS_APWSRDY)) { - ; - } - } -} - -/** - * @} - */ - -/** - * \name Output Pins in Backup Mode - * @{ - */ - -/** - * \brief Enable the backup pin output. - * - * The output is enabled and driven by the SUPC. - * - * \param[in] pin Backup pin index - */ -static inline void system_backup_pin_output_enable( - enum system_backup_pin pin) -{ - if (pin == SYSTEM_BACKUP_PIN_PSOK) { - SUPC->BBPS.reg |= SUPC_BBPS_PSOKEN; - } else { - SUPC->BKOUT.reg |= SUPC_BKOUT_EN(pin >> 1); - } -} - -/** - * \brief Disable the backup pin output. - * - * The output is not enabled. - * - * \param[in] pin Backup pin index - */ -static inline void system_backup_pin_output_disable( - enum system_backup_pin pin) -{ - if (pin == SYSTEM_BACKUP_PIN_PSOK) { - SUPC->BBPS.reg &= ~SUPC_BBPS_PSOKEN; - } else { - SUPC->BKOUT.reg &= ~SUPC_BKOUT_EN(pin >> 1); - } -} - -/** - * \brief Check if backup pin output is enabled. - * - * \param[in] pin Backup pin index - * - * \return The enabled status. - * \retval true The output is enabled - * \retval false The output is not enabled - */ -static inline bool system_backup_pin_output_is_enabled( - enum system_backup_pin pin) -{ - bool enabled = false; - - if (pin == SYSTEM_BACKUP_PIN_PSOK) { - if (SUPC->BBPS.reg & SUPC_BBPS_PSOKEN) { - enabled = true; - } - } else { - if (SUPC->BKOUT.reg & SUPC_BKOUT_EN(pin >> 1)) { - enabled = true; - } - } - return enabled; -} - -/** - * \brief Enable the backup pin toggle on RTC event. - * - * Toggle output on RTC event is enabled. - * - * \param[in] pin Backup pin index - */ -static inline void system_backup_pin_output_enable_rtc_toggle( - enum system_backup_pin pin) -{ - Assert(pin != SYSTEM_BACKUP_PIN_PSOK); - - SUPC->BKOUT.reg |= SUPC_BKOUT_RTCTGL(pin >> 1); -} - -/** - * \brief Disable the backup pin toggle on RTC event. - * - * Toggle output on RTC event is disabled. - * - * \param[in] pin Backup pin index - */ -static inline void system_backup_pin_output_disable_rtc_toggle( - enum system_backup_pin pin) -{ - Assert(pin != SYSTEM_BACKUP_PIN_PSOK); - - SUPC->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(pin >> 1); -} - -/** - * \brief Set the backup pin. - * - * Set the corresponding output pin. - * - * \param[in] pin Backup pin index - */ -static inline void system_backup_pin_output_set( - enum system_backup_pin pin) -{ - Assert(pin != SYSTEM_BACKUP_PIN_PSOK); - - SUPC->BKOUT.reg |= SUPC_BKOUT_SET(pin >> 1); -} - -/** - * \brief Clear the backup pin. - * - * Clear the corresponding output. - * - * \param[in] pin Backup pin index - */ -static inline void system_backup_pin_output_clear( - enum system_backup_pin pin) -{ - Assert(pin != SYSTEM_BACKUP_PIN_PSOK); - - SUPC->BKOUT.reg |= SUPC_BKOUT_CLR(pin >> 1); -} - -/** - * \brief Get the backup I/O input values. - * - * Get the backup I/O data input values. If the corresponding pin is enabled, - * the I/O input value is given on the pin. - * - * \param[in] pin Backup pin index - * - * \return The backup I/O input level value. - */ -static inline bool system_backup_pin_output_get(enum system_backup_pin pin) -{ - Assert(pin != SYSTEM_BACKUP_PIN_PSOK); - - return (SUPC->BKIN.reg & SUPC_BKIN_BKIN(pin >> 1)); -} - -/** - * @} - */ - -/** - * \name Device Sleep Control - * @{ - */ - -/** - * \brief Set the sleep mode of the device. - * - * Sets the sleep mode of the device; the configured sleep mode will be entered - * upon the next call of the \ref system_sleep() function. - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode. - * - * \param[in] sleep_mode Sleep mode to configure for the next sleep operation - */ -static inline void system_set_sleepmode( - const enum system_sleepmode sleep_mode) -{ - PM->SLEEPCFG.reg = sleep_mode; - while(PM->SLEEPCFG.reg != sleep_mode) ; -} - -/** - * \brief Put the system to sleep waiting for interrupt. - * - * Executes a device DSB (Data Synchronization Barrier) instruction to ensure - * all ongoing memory accesses have completed. Further, a WFI (Wait For Interrupt) - * instruction is executed to place the device into the sleep mode specified by - * \ref system_set_sleepmode. - */ -static inline void system_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * @} - */ - -/** - * \name Performance Level Control - * @{ - */ - -/** - * \brief Switch performance level. - * - * The bus frequency must be reduced prior to scaling down the performance level, - * in order to not exceed the maximum frequency allowed for the performance level. - * - * When scaling up the performance level (for example from PL0 to PL2), the bus - * frequency can be increased first when the performance level transition is - * completed. Check the performance level status before increasing the frequency. - * - * \param[in] performance_level Performance level to switch - * - * \retval STATUS_ERR_INVALID_ARG Invalid parameter - * \retval STATUS_OK Successfully - */ -static inline enum status_code system_switch_performance_level( - const enum system_performance_level performance_level) -{ - - if (performance_level == (enum system_performance_level)PM->PLCFG.reg) { - return STATUS_OK; - } - - /* Clear performance level status */ - PM->INTFLAG.reg = PM_INTFLAG_PLRDY; - - /* Switch performance level */ - PM->PLCFG.reg = performance_level; - - /* Waiting performance level ready */ - while (!PM->INTFLAG.reg) { - ; - } - return STATUS_OK; -} - -/** - * \brief Get performance level. - * - * Get performance level. - * - * \return Current performance level. - */ -static inline enum system_performance_level system_get_performance_level(void) -{ - return (enum system_performance_level)PM->PLCFG.reg; -} - -/** - * \brief Get performance level status. - * - * Get performance level status. - * \return Performance level status: Written to one when the performance level is ready. - */ -static inline uint8_t system_get_performance_level_status(void) -{ - return PM->INTFLAG.reg; -} - -/** - * \brief Clear performance level status. - * - * Clear performance level status. - */ -static inline void system_clear_performance_level_status(void) -{ - PM->INTFLAG.reg = PM_INTFLAG_PLRDY; -} - -/** - * @} - */ - -/** - * \name Standby Configuration - * @{ - */ - -/** - * \brief Retrieve the default configuration for standby. - * - * Fills a configuration structure with the default configuration for standby: - * - Retention back biasing mode for HMCRAMCLP - * - Retention back biasing mode for HMCRAMCHS - * - Power domains PD0/PD1/PD2 are not linked - * - Automatic VREG switching is used - * - Dynamic power gating for power domain 1 is disabled - * - Dynamic power gating for power domain 0 is disabled - * - All power domains switching are handled by hardware - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_standby_get_config_defaults( - struct system_standby_config *const config) -{ - Assert(config); - config->power_domain = SYSTEM_POWER_DOMAIN_DEFAULT; - config->enable_dpgpd0 = false; - config->enable_dpgpd1 = false; - config->disable_avregsd = false; - config->linked_power_domain = SYSTEM_LINKED_POWER_DOMAIN_DEFAULT; - config->hmcramchs_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION; - config->hmcramclp_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION; -} - -/** - * \brief Configure standby mode. - * - * Configures standby with the given configuration. - * - * \param[in] config Standby configuration structure containing - * the new config - */ -static inline void system_standby_set_config( - struct system_standby_config *const config) -{ - Assert(config); - PM->STDBYCFG.reg = PM_STDBYCFG_PDCFG(config->power_domain) - | (config->enable_dpgpd0 << PM_STDBYCFG_DPGPD0_Pos) - | (config->enable_dpgpd1 << PM_STDBYCFG_DPGPD1_Pos) - | (config->disable_avregsd << PM_STDBYCFG_AVREGSD_Pos) - | PM_STDBYCFG_LINKPD(config->linked_power_domain) - | PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias) - | PM_STDBYCFG_BBIASLP(config->hmcramclp_back_bias); -} - -/** - * @} - */ - -/** - * \name I/O Retention - * @{ - */ - -/** - * \brief Enable I/O retention. - * - * Enable I/O retention. After waking up from Backup mode, I/O lines are held - * until the bit is written to 0. - */ -static inline void system_io_retension_enable(void) -{ - PM->CTRLA.reg = PM_CTRLA_IORET; -} - -/** - * \brief Disable I/O retention. - * - * Disable IO retention. After waking up from Backup mode, I/O lines are not held. - */ -static inline void system_io_retension_disable(void) -{ - PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET); -} - -/** - * @} - */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* POWER_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMR21/power.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMR21/power.h deleted file mode 100644 index c0920ab668a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMR21/power.h +++ /dev/null @@ -1,224 +0,0 @@ -/** - * \file - * - * \brief SAM Power related functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef POWER_H_INCLUDED -#define POWER_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_system_group - * @{ - */ - -/** - * \brief Voltage references within the device. - * - * List of available voltage references (VREF) that may be used within the - * device. - */ -enum system_voltage_reference { - /** Temperature sensor voltage reference. */ - SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE, - /** Bandgap voltage reference. */ - SYSTEM_VOLTAGE_REFERENCE_BANDGAP, -}; - -/** - * \brief Device sleep modes. - * - * List of available sleep modes in the device. A table of clocks available in - * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode. - */ -enum system_sleepmode { - /** IDLE 0 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_0, - /** IDLE 1 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_1, - /** IDLE 2 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_2, - /** Standby sleep mode. */ - SYSTEM_SLEEPMODE_STANDBY, -}; - - - -/** - * \name Voltage References - * @{ - */ - -/** - * \brief Enable the selected voltage reference - * - * Enables the selected voltage reference source, making the voltage reference - * available on a pin as well as an input source to the analog peripherals. - * - * \param[in] vref Voltage reference to enable - */ -static inline void system_voltage_reference_enable( - const enum system_voltage_reference vref) -{ - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN; - break; - - case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: - SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN; - break; - - default: - Assert(false); - return; - } -} - -/** - * \brief Disable the selected voltage reference - * - * Disables the selected voltage reference source. - * - * \param[in] vref Voltage reference to disable - */ -static inline void system_voltage_reference_disable( - const enum system_voltage_reference vref) -{ - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN; - break; - - case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: - SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; - break; - - default: - Assert(false); - return; - } -} - -/** - * @} - */ - - -/** - * \name Device Sleep Control - * @{ - */ - -/** - * \brief Set the sleep mode of the device - * - * Sets the sleep mode of the device; the configured sleep mode will be entered - * upon the next call of the \ref system_sleep() function. - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode. - * - * \param[in] sleep_mode Sleep mode to configure for the next sleep operation - * - * \retval STATUS_OK Operation completed successfully - * \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not - * available - */ -static inline enum status_code system_set_sleepmode( - const enum system_sleepmode sleep_mode) -{ -#if (SAMD20 || SAMD21) - /* Errata: Make sure that the Flash does not power all the way down - * when in sleep mode. */ - NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val; -#endif - - switch (sleep_mode) { - case SYSTEM_SLEEPMODE_IDLE_0: - case SYSTEM_SLEEPMODE_IDLE_1: - case SYSTEM_SLEEPMODE_IDLE_2: - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - PM->SLEEP.reg = sleep_mode; - break; - - case SYSTEM_SLEEPMODE_STANDBY: - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - break; - - default: - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Put the system to sleep waiting for interrupt - * - * Executes a device DSB (Data Synchronization Barrier) instruction to ensure - * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt) - * instruction to place the device into the sleep mode specified by - * \ref system_set_sleepmode until woken by an interrupt. - */ -static inline void system_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * @} - */ - -/** @} */ -#ifdef __cplusplus -} -#endif - -#endif /* POWER_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h deleted file mode 100644 index 75216c48420..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * \brief SAM Reset related functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef RESET_H_INCLUDED -#define RESET_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_system_group - * @{ - */ - -/** - * \brief Reset causes of the system. - * - * List of possible reset causes of the system. - */ -enum system_reset_cause { - /** The system was last reset by a software reset. */ - SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST, - /** The system was last reset by the watchdog timer. */ - SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT, - /** The system was last reset because the external reset line was pulled low. */ - SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT, - /** The system was last reset by the BOD33. */ - SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33, - /** The system was last reset by the BOD12. */ - SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12, - /** The system was last reset by the POR (Power on reset). */ - SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR, -}; - - -/** - * \name Reset Control - * @{ - */ - -/** - * \brief Return the reset cause. - * - * Retrieves the cause of the last system reset. - * - * \return An enum value indicating the cause of the last system reset. - */ -static inline enum system_reset_cause system_get_reset_cause(void) -{ - return (enum system_reset_cause)PM->RCAUSE.reg; -} - -/** - * @} - */ - -/** @} */ -#ifdef __cplusplus -} -#endif - -#endif /* RESET_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h deleted file mode 100644 index 0dde18a18d7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h +++ /dev/null @@ -1,241 +0,0 @@ -/** - * \file - * - * \brief SAM Reset functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef RESET_H_INCLUDED -#define RESET_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_system_group - * @{ - */ - -/** - * \brief Reset causes of the system. - * - * List of possible reset causes of the system. - */ -enum system_reset_cause { - /** The system was last reset by a backup reset */ - SYSTEM_RESET_CAUSE_BACKUP = RSTC_RCAUSE_BACKUP, - /** The system was last reset by a software reset */ - SYSTEM_RESET_CAUSE_SOFTWARE = RSTC_RCAUSE_SYST, - /** The system was last reset by the watchdog timer */ - SYSTEM_RESET_CAUSE_WDT = RSTC_RCAUSE_WDT, - /** The system was last reset because the external reset line was pulled low */ - SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT, - /** The system was last reset by the BOD33 */ - SYSTEM_RESET_CAUSE_BOD33 = RSTC_RCAUSE_BOD33, - /** The system was last reset by the BOD12 */ - SYSTEM_RESET_CAUSE_BOD12 = RSTC_RCAUSE_BOD12, - /** The system was last reset by the POR (Power on reset) */ - SYSTEM_RESET_CAUSE_POR = RSTC_RCAUSE_POR, -}; - -/** - * \brief Backup exit source after a backup reset occurs. - * - * List of possible backup exit source. - */ -enum system_reset_backup_exit_source { - /** The backup exit source was external wakeup */ - SYSTEM_RESET_BACKKUP_EXIT_EXTWAKE = RSTC_BKUPEXIT_EXTWAKE, - /** The backup exit source was RTC interrupt */ - SYSTEM_RESET_BACKKUP_EXIT_RTC = RSTC_BKUPEXIT_RTC, - /** The backup exit source was battery backup power switch */ - SYSTEM_RESET_BACKKUP_EXIT_BBPS = RSTC_BKUPEXIT_BBPS, -}; - -/** - * \brief Wakeup debounce counter value. - * - * Wakeup debounce counter value when waking up by external wakeup pin from backup mode. - */ -enum system_wakeup_debounce_count { - /** No debouncing */ - SYSTEM_WAKEUP_DEBOUNCE_OFF = RSTC_WKDBCONF_WKDBCNT_OFF, - /** Input pin shall be active for at least two 32KHz clock periods */ - SYSTEM_WAKEUP_DEBOUNCE_2CK32 = RSTC_WKDBCONF_WKDBCNT_2K32, - /** Input pin shall be active for at least three 32KHz clock periods */ - SYSTEM_WAKEUP_DEBOUNCE_3CK32 = RSTC_WKDBCONF_WKDBCNT_3CK32, - /** Input pin shall be active for at least 32 32KHz clock periods */ - SYSTEM_WAKEUP_DEBOUNCE_32CK32 = RSTC_WKDBCONF_WKDBCNT_32CK32, - /** Input pin shall be active for at least 512 32KHz clock periods */ - SYSTEM_WAKEUP_DEBOUNCE_512CK32 = RSTC_WKDBCONF_WKDBCNT_512CK32, - /** Input pin shall be active for at least 4096 32KHz clock periods */ - SYSTEM_WAKEUP_DEBOUNCE_4096CK32 = RSTC_WKDBCONF_WKDBCNT_4096CK32, - /** Input pin shall be active for at least 32768 32KHz clock periods */ - SYSTEM_WAKEUP_DEBOUNCE_32768CK32 = RSTC_WKDBCONF_WKDBCNT_32768CK32, -}; - -/** - * \name Reset Control - * @{ - */ - -/** - * \brief Get the reset cause. - * - * Retrieves the cause of the last system reset. - * - * \return An enum value indicating the cause of the last system reset. - */ -static inline enum system_reset_cause system_get_reset_cause(void) -{ - return (enum system_reset_cause)RSTC->RCAUSE.reg; -} - -/** - * @} - */ - -/** - * \name Backup Exit Control - * @{ - */ - -/** - * \brief Get the backup exit source. - * - * Get the backup exit source when a backup reset occurs. - * - * \return An enum value indicating the latest backup exit source. - */ -static inline enum system_reset_backup_exit_source system_get_backup_exit_source(void) -{ - return (enum system_reset_backup_exit_source)RSTC->BKUPEXIT.reg; -} - -/** - * \brief Set wakeup debounce counter. - * - * Set the wakeup debounce counter value with the given count. - * - * \param[in] wakeup_debounce_count Wakeup debounce counter value - */ -static inline void system_set_pin_wakeup_debounce_counter( - const enum system_wakeup_debounce_count wakeup_debounce_count) -{ - RSTC->WKDBCONF.reg = wakeup_debounce_count; -} - -/** - * \brief Set low polarity of wakeup input pin. - * - * Set low polarity with the given wakeup input pin mask. - * - * \param[in] pin_mask Input pin mask - */ -static inline void system_set_pin_wakeup_polarity_low(const uint16_t pin_mask) -{ - RSTC->WKPOL.reg &= ~(RSTC_WKPOL_WKPOL(pin_mask)); -} - -/** - * \brief Set high polarity of wakeup input pin. - * - * Set high polarity with the given wakeup input pin mask. - * - * \param[in] pin_mask Input pin mask - */ -static inline void system_set_pin_wakeup_polarity_high(const uint16_t pin_mask) -{ - RSTC->WKPOL.reg |= RSTC_WKPOL_WKPOL(pin_mask); -} - -/** - * \brief Enable wakeup of input pin from the backup mode. - * - * Enable pin wakeup from the backup mode with the given pin mask. - * - * \param[in] pin Input pin mask - */ -static inline void system_enable_pin_wakeup(const uint16_t pin_mask) -{ - RSTC->WKEN.reg |= RSTC_WKEN_WKEN(pin_mask); -} - -/** - * \brief Disable wakeup of input pin from the backup mode. - * - * Disable pin wakeup from the backup mode with the given pin mask. - * - * \param[in] pin Input pin mask - */ -static inline void system_disable_pin_wakeup(const uint16_t pin_mask) -{ - RSTC->WKEN.reg &= ~(RSTC_WKEN_WKEN(pin_mask)); -} - -/** - * \brief Check whether any of the enabled wake up pins are active and caused the wakeup. - * - * Check whether any of the enabled wake up pins are active and caused the wakeup - * from backup sleep mode when exiting backup mode. - * - * \return Pin mask, the corresponding pin is active when its pin mask is 1. - */ -static inline uint16_t system_get_pin_wakeup_cause(void) -{ - return (RSTC_WKCAUSE_MASK & (RSTC->WKCAUSE.reg >> RSTC_WKCAUSE_WKCAUSE_Pos)); -} - -/** - * @} - */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* RESET_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h deleted file mode 100644 index 75216c48420..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * \brief SAM Reset related functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef RESET_H_INCLUDED -#define RESET_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_system_group - * @{ - */ - -/** - * \brief Reset causes of the system. - * - * List of possible reset causes of the system. - */ -enum system_reset_cause { - /** The system was last reset by a software reset. */ - SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST, - /** The system was last reset by the watchdog timer. */ - SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT, - /** The system was last reset because the external reset line was pulled low. */ - SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT, - /** The system was last reset by the BOD33. */ - SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33, - /** The system was last reset by the BOD12. */ - SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12, - /** The system was last reset by the POR (Power on reset). */ - SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR, -}; - - -/** - * \name Reset Control - * @{ - */ - -/** - * \brief Return the reset cause. - * - * Retrieves the cause of the last system reset. - * - * \return An enum value indicating the cause of the last system reset. - */ -static inline enum system_reset_cause system_get_reset_cause(void) -{ - return (enum system_reset_cause)PM->RCAUSE.reg; -} - -/** - * @} - */ - -/** @} */ -#ifdef __cplusplus -} -#endif - -#endif /* RESET_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.c deleted file mode 100644 index c2695a4ee0c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.c +++ /dev/null @@ -1,112 +0,0 @@ -/** - * \file - * - * \brief SAM System related functionality - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include - -/** - * \internal - * Dummy initialization function, used as a weak alias target for the various - * init functions called by \ref system_init(). - */ -void _system_dummy_init(void); -void _system_dummy_init(void) -{ - return; -} - -#if !defined(__DOXYGEN__) -# if defined(__GNUC__) -void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -void _system_divas_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -# elif defined(__ICCARM__) -void system_clock_init(void); -void system_board_init(void); -void _system_events_init(void); -void _system_extint_init(void); -void _system_divas_init(void); -# pragma weak system_clock_init=_system_dummy_init -# pragma weak system_board_init=_system_dummy_init -# pragma weak _system_events_init=_system_dummy_init -# pragma weak _system_extint_init=_system_dummy_init -# pragma weak _system_divas_init=_system_dummy_init -# endif -#endif - -/** - * \brief Initialize system - * - * This function will call the various initialization functions within the - * system namespace. If a given optional system module is not available, the - * associated call will effectively be a NOP (No Operation). - * - * Currently the following initialization functions are supported: - * - System clock initialization (via the SYSTEM CLOCK sub-module) - * - Board hardware initialization (via the Board module) - * - Event system driver initialization (via the EVSYS module) - * - External Interrupt driver initialization (via the EXTINT module) - */ -void system_init(void) -{ - /* Configure GCLK and clock sources according to conf_clocks.h */ - system_clock_init(); - - /* Initialize board hardware */ - system_board_init(); - - /* Initialize EVSYS hardware */ - _system_events_init(); - - /* Initialize External hardware */ - _system_extint_init(); - - /* Initialize DIVAS hardware */ - _system_divas_init(); -} - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.h deleted file mode 100644 index ced58c29c45..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.h +++ /dev/null @@ -1,726 +0,0 @@ -/** - * \file - * - * \brief SAM System related functionality - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_H_INCLUDED -#define SYSTEM_H_INCLUDED - -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_system_group SAM System (SYSTEM) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the device's system relation functionality, necessary for - * the basic device operation. This is not limited to a single peripheral, but - * extends across multiple hardware peripherals. - * - * The following peripherals are used by this module: - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - PM (Power Manager) - * - RSTC(Reset Controller) - * - SUPC(Supply Controller) - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - PM (Power Manager) - * - RSTC(Reset Controller) - * - SUPC(Supply Controller) - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - SYSCTRL (System Control) - * - PM (Power Manager) - * \endif - * - * The following devices can use this module: - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - Atmel | SMART SAM L21 - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - Atmel | SMART SAM C20/C21 - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM DAx - * \endif - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_prerequisites - * - \ref asfdoc_sam0_system_module_overview - * - \ref asfdoc_sam0_system_special_considerations - * - \ref asfdoc_sam0_system_extra_info - * - \ref asfdoc_sam0_system_examples - * - \ref asfdoc_sam0_system_api_overview - * - * - * \section asfdoc_sam0_system_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_module_overview Module Overview - * - * The System driver provides a collection of interfaces between the user - * application logic, and the core device functionality (such as clocks, reset - * cause determination, etc.) that is required for all applications. It contains - * a number of sub-modules that control one specific aspect of the device: - * - * - System Core (this module) - * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module) - * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module) - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module) - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * \subsection asfdoc_sam0_system_module_overview_vreg_l21 Voltage Regulator - * The SAM device controls the voltage regulators for the core (VDDCORE) and - * backup (VDDBU) domains. It sets the voltage regulators according to the sleep - * modes, the performance level, or the user configuration. - * - * In active mode, the voltage regulator can be chosen on the fly between a LDO - * or a Buck converter. In standby mode, the low power voltage regulator is used - * to supply VDDCORE. - * - * \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch - * The SAM device supports connection of a battery backup to the VBAT power pin. - * It includes functionality that enables automatic power switching between main - * power and battery backup power. This will ensure power to the backup domain, - * when the main battery or power source is unavailable. - * \endif - * - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * \subsection asfdoc_sam0_system_module_overview_vreg_c21 Voltage Regulator - * The SAM device controls the voltage regulators for the core (VDDCORE). It sets - * the voltage regulators according to the sleep modes. - * - * There are a selectable reference voltage and voltage dependent on the temperature - * which can be used by analog modules like the ADC. - * \endif - * - * \subsection asfdoc_sam0_system_module_overview_vref Voltage References - * The various analog modules within the SAM devices (such as AC, ADC, and - * DAC) require a voltage reference to be configured to act as a reference point - * for comparisons and conversions. - * - * The SAM devices contain multiple references, including an internal - * temperature sensor and a fixed band-gap voltage source. When enabled, the - * associated voltage reference can be selected within the desired peripheral - * where applicable. - * - * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause - * In some applications there may be a need to execute a different program - * flow based on how the device was reset. For example, if the cause of reset - * was the Watchdog timer (WDT), this might indicate an error in the application, - * and a form of error handling or error logging might be needed. - * - * For this reason, an API is provided to retrieve the cause of the last system - * reset, so that appropriate action can be taken. - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * There are three groups of reset sources: - * - Power supply reset: Resets caused by an electrical issue. It covers POR and BOD reset. - * - User reset: Resets caused by the application. It covers external reset, - * system reset, and watchdog reset. - * - Backup reset: Resets caused by a backup mode exit condition. - * - * \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level - * Performance level allows the user to adjust the regulator output voltage to reduce - * power consumption. The user can on the fly select the most suitable performance - * level, depending on the application demands. - * - * The SAM device can operate at two different performance levels (PL0 and PL2). - * When operating at PL0, the voltage applied on the full logic area is reduced - * by voltage scaling. This voltage scaling technique allows to reduce the active - * power consumption while decreasing the maximum frequency of the device. When - * operating at PL2, the voltage regulator supplies the highest voltage, allowing - * the device to run at higher clock speeds. - * - * Performance level transition is possible only when the device is in active - * mode. After a reset, the device starts at the lowest performance level - * (lowest power consumption and lowest max. frequency). The application can then - * switch to another performance level at any time without any stop in the code - * execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure. - * - * \note When scaling down the performance level, the bus frequency should first be - * scaled down in order to not exceed the maximum frequency allowed for the - * low performance level. - * When scaling up the performance level (e.g. from PL0 to PL2), check the performance - * level status before increasing the bus frequency. It can be increased only - * when the performance level transition is completed. - * - * \anchor asfdoc_sam0_system_performance_level_transition_figure - * \image html performance_level_transition.svg "Performance Level Transition" - * - * \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating - * Power domain gating allows power saving by reducing the voltage in logic - * areas in the device to a low-power supply. The feature is available in - * Standby sleep mode and will reduce the voltage in domains where all peripherals - * are idle. Internal logic will maintain its content, meaning the corresponding - * peripherals will not need to be reconfigured when normal operating voltage - * is returned. Most power domains can be in the following three states: - * - * - Active state: The power domain is powered on. - * - Retention state: The main voltage supply for the power domain is switched off, - * while maintaining a secondary low-power supply for the sequential cells. The - * logic context is restored when waking up. - * - Off state: The power domain is entirely powered off. The logic context is lost. - * - * The SAM L21 device contains three power domains which can be controlled using - * power domain gating, namely PD0, PD1, and PD2. These power domains can be - * configured to the following cases: - * - Default with no sleepwalking peripherals: A power domain is automatically set - * to retention state in standby sleep mode if no activity require it. The application - * can force all power domains to remain in active state during standby sleep mode - * in order to accelerate wakeup time. - * - Default with sleepwalking peripherals: If one or more peripherals are enabled - * to perform sleepwalking tasks in standby sleep mode, the corresponding power - * domain (PDn) remains in active state as well as all inferior power domains (PDn) in order - * to perform a sleepwalking task. The superior power domain is then automatically - * set to active state. At the end of the sleepwalking task, the device can either - * be woken up or the superior power domain can return to retention state. - * - * Power domains can be linked to each other, it allows a power domain (PDn) to be kept - * in active state if the inferior power domain (PDn-1) is in active state too. - * - * \ref asfdoc_sam0_system_power_domain_overview_table illustrates the - * four cases to consider in standby mode. - * - * \anchor asfdoc_sam0_system_power_domain_overview_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Sleep Mode versus Power Domain State Overview
Sleep modePD0PD1PD2PDTOPPDBACKUP
Idleactiveactiveactiveactiveactive
Standby - Case 1activeactiveactiveactiveactive
Standby - Case 2activeactiveretentionactiveactive
Standby - Case 3activeretentionretentionactiveactive
Standby - Case 4retentionretentionretentionactiveactive
Backupoffoffoffoffactive
Offoffoffoffoffoff
- * - * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode - * By default, in standby sleep mode, RAM is in low power mode (back biased) - * if its power domain is in retention state. - * \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode. - * - * \anchor asfdoc_sam0_system_power_ram_state_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
RAM Back-biasing Mode
RAM modeDescription
Retention Back-biasing modeRAM is back-biased if its power domain is in retention mode
Standby Back-biasing modeRAM is back-biased if the device is in standby mode
Standby OFF modeRAM is OFF if the device is in standby mode
Always OFF modeRAM is OFF if the device is in RET mode
- * - * \endif - * - * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes - * The SAM devices have several sleep modes. The sleep mode controls - * which clock systems on the device will remain enabled or disabled when the - * device enters a low power sleep mode. - * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the - * clock settings of the different sleep modes. - * - * \anchor asfdoc_sam0_system_module_sleep_mode_table - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * \else - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * \endif - *
SAM Device Sleep Modes
Sleep modeSystem clockCPU clockAHB/AHB clockGCLK clocksOscillators (ONDEMAND = 0)Oscillators (ONDEMAND = 1)Regulator modeRAM mode
IdleRunStopRun if requestedRunRunRun if requestedNormalNormal
StandbyStopStopRun if requestedRun if requestedRun if requested or RUNSTDBY = 1Run if requestedLow pwerLow pwer
BackupStopStopStopStopStopStopBackupOff
OffOffOffOffOffOffOffOffOff
Sleep modeCPU clockAHB clockAPB clocksClock sourcesSystem clock32KHzReg modeRAM mode
Idle 0StopRunRunRunRunRunNormalNormal
Idle 1StopStopRunRunRunRunNormalNormal
Idle 2StopStopStopRunRunRunNormalNormal
StandbyStopStopStopStopStopStopLow PowerSource/Drain biasing
- * - * Before entering device sleep, one of the available sleep modes must be set. - * The device will automatically wake up in response to an interrupt being - * generated or upon any other sleep mode exit condition. - * - * Some peripheral clocks will remain enabled during sleep, depending on their - * configuration. If desired, the modules can remain clocked during sleep to allow - * them continue to operate while other parts of the system are powered down - * to save power. - * - * - * \section asfdoc_sam0_system_special_considerations Special Considerations - * - * Most of the functions in this driver have device specific restrictions and - * caveats; refer to your device datasheet. - * - * - * \section asfdoc_sam0_system_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_extra. This includes: - * - \ref asfdoc_sam0_system_extra_acronyms - * - \ref asfdoc_sam0_system_extra_dependencies - * - \ref asfdoc_sam0_system_extra_errata - * - \ref asfdoc_sam0_system_extra_history - * - * - * \section asfdoc_sam0_system_examples Examples - * - * For SYSTEM module related examples, refer to the sub-modules listed in - * the \ref asfdoc_sam0_system_module_overview "system module overview". - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_drivers_power_exqsg. - * - * - * \section asfdoc_sam0_system_api_overview API Overview - * @{ - */ - -/** - * \name System Debugger - * @{ - */ - -/** - * \brief Check if debugger is present. - * - * Check if debugger is connected to the onboard debug system (DAP). - * - * \return A bool identifying if a debugger is present. - * - * \retval true Debugger is connected to the system - * \retval false Debugger is not connected to the system - * - */ -static inline bool system_is_debugger_present(void) -{ - return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES; -} - -/** - * @} - */ - -/** - * \name System Identification - * @{ - */ - -/** - * \brief Retrieve the device identification signature. - * - * Retrieves the signature of the current device. - * - * \return Device ID signature as a 32-bit integer. - */ -static inline uint32_t system_get_device_id(void) -{ - return DSU->DID.reg; -} - -/** - * @} - */ - -/** - * \name System Initialization - * @{ - */ - -void system_init(void); - -/** - * @} - */ - - -/** - * @} - */ - -/** - -* \page asfdoc_sam0_drivers_power_exqsg Examples for Power Driver - * - * This is a list of the available Quick Start Guides (QSGs) and example - * applications. QSGs are simple examples with step-by-step instructions to - * configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - \subpage asfdoc_sam0_power_basic_use_case - * \endif - * - * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver - * - * \section asfdoc_sam0_system_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - * - * - * - * \endif - *
AcronymDefinition
PMPower Manager
SUPCSupply Controller
RSTCReset Controller
SUPCSupply Controller
RSTCReset Controller
SYSCTRLSystem control interface
- * - * - * \section asfdoc_sam0_system_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_system_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - * - * - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - * - * - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * - * \endif - *
Changelog
Initial Release
Initial Release
Added new \c system_reset() to reset the complete MCU with some exceptions
Added new \c system_get_device_id() function to retrieved the device - * ID.
Initial Release
- * - * \page asfdoc_sam0_system_document_revision_history Document Revision History - * - * - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - * - * - * - * - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - * - * - * - * - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * \endif - *
Doc. Rev. - * Date - * Comments - *
42449A07/2015Initial document release
42484A08/2015Initial document release.
42120E04/2015Added support for SAMDAx
42120D12/2014Added support for SAMR21 and SAMD10/D11
42120C01/2014Added support for SAMD21
42120B06/2013Corrected documentation typos
42120A06/2013Initial document release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_H_INCLUDED */ - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMD21/tc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMD21/tc.c deleted file mode 100644 index 00702905bea..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMD21/tc.c +++ /dev/null @@ -1,684 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tc.h" - -#if TC_ASYNC == true -# include "tc_interrupt.h" -# include - -/** \internal - * Converts a given TC index to its interrupt vector index. - */ -# define _TC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_TC##n, -#endif - -#if !defined(__DOXYGEN__) -# define _TC_GCLK_ID(n,unused) TPASTE3(TC,n,_GCLK_ID) , -# define _TC_PM_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TC,n) , - -# define TC_INST_GCLK_ID { MRECURSION(TC_INST_NUM, _TC_GCLK_ID, TC_INST_MAX_ID) } -# define TC_INST_PM_APBCMASK { MRECURSION(TC_INST_NUM, _TC_PM_APBCMASK, TC_INST_MAX_ID) } - -#endif - -/** - * \internal Find the index of given TC module instance. - * - * \param[in] TC module instance pointer. - * - * \return Index of the given TC module instance. - */ -uint8_t _tc_get_inst_index( - Tc *const hw) -{ - /* List of available TC modules. */ - Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; - - /* Find index for TC instance. */ - for (uint32_t i = 0; i < TC_INST_NUM; i++) { - if (hw == tc_modules[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} - - -/** - * \brief Initializes a hardware TC module instance. - * - * Enables the clock and initializes the TC module, based on the given - * configuration values. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] hw Pointer to the TC hardware module - * \param[in] config Pointer to the TC configuration options struct - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY Hardware module was busy when the - * initialization procedure was attempted - * \retval STATUS_INVALID_ARG An invalid configuration option or argument - * was supplied - * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the - * hardware module is configured in 32-bit - * slave mode - */ -enum status_code tc_init( - struct tc_module *const module_inst, - Tc *const hw, - const struct tc_config *const config) -{ - /* Sanity check arguments */ - Assert(hw); - Assert(module_inst); - Assert(config); - - /* Temporary variable to hold all updates to the CTRLA - * register before they are written to it */ - uint16_t ctrla_tmp = 0; - /* Temporary variable to hold all updates to the CTRLBSET - * register before they are written to it */ - uint8_t ctrlbset_tmp = 0; - /* Temporary variable to hold all updates to the CTRLC - * register before they are written to it */ - uint8_t ctrlc_tmp = 0; - /* Temporary variable to hold TC instance number */ - uint8_t instance = _tc_get_inst_index(hw); - - /* Array of GLCK ID for different TC instances */ - uint8_t inst_gclk_id[] = TC_INST_GCLK_ID; - /* Array of PM APBC mask bit position for different TC instances */ - uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK; - - struct system_pinmux_config pin_config; - struct system_gclk_chan_config gclk_chan_config; - -#if TC_ASYNC == true - /* Initialize parameters */ - for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - } - module_inst->register_callback_mask = 0x00; - module_inst->enable_callback_mask = 0x00; - - /* Register this instance for callbacks*/ - _tc_instances[instance] = module_inst; -#endif - - /* Associate the given device instance with the hardware module */ - module_inst->hw = hw; - -#if SAMD10 || SAMD11 - /* Check if even numbered TC modules are being configured in 32-bit - * counter size. Only odd numbered counters are allowed to be - * configured in 32-bit counter size. - */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - !((instance + TC_INSTANCE_OFFSET) & 0x01)) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -#else - /* Check if odd numbered TC modules are being configured in 32-bit - * counter size. Only even numbered counters are allowed to be - * configured in 32-bit counter size. - */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - ((instance + TC_INSTANCE_OFFSET) & 0x01)) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -#endif - - /* Make the counter size variable in the module_inst struct reflect - * the counter size in the module - */ - module_inst->counter_size = config->counter_size; - - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } - - if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { - /* Module is used as a slave */ - return STATUS_ERR_DENIED; - } - - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } - - /* Set up the TC PWM out pin for channel 0 */ - if (config->pwm_channel[0].enabled) { - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pwm_channel[0].pin_mux; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pwm_channel[0].pin_out, &pin_config); - } - - /* Set up the TC PWM out pin for channel 1 */ - if (config->pwm_channel[1].enabled) { - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pwm_channel[1].pin_mux; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pwm_channel[1].pin_out, &pin_config); - } - - /* Enable the user interface clock in the PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - inst_pm_apbmask[instance]); - - /* Enable the slave counter if counter_size is 32-bit */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) { - /* Enable the user interface clock in the PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - inst_pm_apbmask[instance + 1]); - } - - /* Setup clock for module */ - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = config->clock_source; - system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); - system_gclk_chan_enable(inst_gclk_id[instance]); - - /* Set ctrla register */ - ctrla_tmp = - (uint32_t)config->counter_size | - (uint32_t)config->wave_generation | - (uint32_t)config->reload_action | - (uint32_t)config->clock_prescaler; - - if (config->run_in_standby) { - ctrla_tmp |= TC_CTRLA_RUNSTDBY; - } - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLA.reg = ctrla_tmp; - - /* Set ctrlb register */ - if (config->oneshot) { - ctrlbset_tmp = TC_CTRLBSET_ONESHOT; - } - - if (config->count_direction) { - ctrlbset_tmp |= TC_CTRLBSET_DIR; - } - - /* Clear old ctrlb configuration */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLBCLR.reg = 0xFF; - - /* Check if we actually need to go into a wait state. */ - if (ctrlbset_tmp) { - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - /* Write configuration to register */ - hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; - } - - /* Set ctrlc register*/ - ctrlc_tmp = config->waveform_invert_output; - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (config->enable_capture_on_channel[i] == true) { - ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i); - } - } - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLC.reg = ctrlc_tmp; - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Switch for TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.COUNT.reg = - config->counter_8_bit.value; - - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.PER.reg = - config->counter_8_bit.period; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.CC[0].reg = - config->counter_8_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.CC[1].reg = - config->counter_8_bit.compare_capture_channel[1]; - - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.COUNT.reg - = config->counter_16_bit.value; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.CC[0].reg = - config->counter_16_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.CC[1].reg = - config->counter_16_bit.compare_capture_channel[1]; - - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.COUNT.reg - = config->counter_32_bit.value; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.CC[0].reg = - config->counter_32_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.CC[1].reg = - config->counter_32_bit.compare_capture_channel[1]; - - return STATUS_OK; - } - - Assert(false); - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Sets TC module count value. - * - * Sets the current timer count value of a initialized TC module. The - * specified TC module may be started or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] count New timer count value to set - * - * \return Status of the count update procedure. - * - * \retval STATUS_OK The timer count was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified - */ -enum status_code tc_set_count_value( - const struct tc_module *const module_inst, - const uint32_t count) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance*/ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write to based on the TC counter_size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.COUNT.reg = (uint8_t)count; - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.COUNT.reg = (uint16_t)count; - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.COUNT.reg = (uint32_t)count; - return STATUS_OK; - - default: - return STATUS_ERR_INVALID_ARG; - } -} - -/** - * \brief Get TC module count value. - * - * Retrieves the current count value of a TC module. The specified TC module - * may be started or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Count value of the specified TC module. - */ -uint32_t tc_get_count_value( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read from based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - return (uint32_t)tc_module->COUNT8.COUNT.reg; - - case TC_COUNTER_SIZE_16BIT: - return (uint32_t)tc_module->COUNT16.COUNT.reg; - - case TC_COUNTER_SIZE_32BIT: - return tc_module->COUNT32.COUNT.reg; - } - - Assert(false); - return 0; -} - -/** - * \brief Gets the TC module capture value. - * - * Retrieves the capture value in the indicated TC module capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the Compare Capture channel to read - * - * \return Capture value stored in the specified timer channel. - */ -uint32_t tc_get_capture_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT8.CC[channel_index].reg; - } - - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT16.CC[channel_index].reg; - } - - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT32.CC[channel_index].reg; - } - } - - Assert(false); - return 0; -} - -/** - * \brief Sets a TC module compare value. - * - * Writes a compare value to the given TC module compare/capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value to set - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied - */ -enum status_code tc_set_compare_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index, - const uint32_t compare) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT8.CC[channel_index].reg = - (uint8_t)compare; - return STATUS_OK; - } - - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT16.CC[channel_index].reg = - (uint16_t)compare; - return STATUS_OK; - } - - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT32.CC[channel_index].reg = - (uint32_t)compare; - return STATUS_OK; - } - } - - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Resets the TC module. - * - * Resets the TC module, restoring all hardware module registers to their - * default values and disabling the module. The TC module will not be - * accessible while the reset is being performed. - * - * \note When resetting a 32-bit counter only the master TC module's instance - * structure should be passed to the function. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Status of the procedure. - * \retval STATUS_OK The module was reset successfully - * \retval STATUS_ERR_UNSUPPORTED_DEV A 32-bit slave TC module was passed to - * the function. Only use reset on master - * TC - */ -enum status_code tc_reset( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - if (tc_module->STATUS.reg & TC_STATUS_SLAVE) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Disable this module if it is running */ - if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { - tc_disable(module_inst); - while (tc_is_syncing(module_inst)) { - /* wait while module is disabling */ - } - } - - /* Reset this TC module */ - tc_module->CTRLA.reg |= TC_CTRLA_SWRST; - - return STATUS_OK; -} - -/** - * \brief Set the timer TOP/period value. - * - * For 8-bit counter size this function writes the top value to the period - * register. - * - * For 16- and 32-bit counter size this function writes the top value to - * Capture Compare register 0. The value in this register can not be used for - * any other purpose. - * - * \note This function is designed to be used in PWM or frequency - * match modes only. When the counter is set to 16- or 32-bit counter - * size. In 8-bit counter size it will always be possible to change the - * top value even in normal mode. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New timer TOP value to set - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the - * module instance is invalid - */ -enum status_code tc_set_top_value ( - const struct tc_module *const module_inst, - const uint32_t top_value) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(top_value); - - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.PER.reg = (uint8_t)top_value; - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.CC[0].reg = (uint16_t)top_value; - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.CC[0].reg = (uint32_t)top_value; - return STATUS_OK; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAML21/tc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAML21/tc.c deleted file mode 100644 index 05ecf901c53..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAML21/tc.c +++ /dev/null @@ -1,717 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tc.h" - -#if TC_ASYNC == true -# include "tc_interrupt.h" -# include -#endif - -/** - * \internal Find the index of given TC module instance. - * - * \param[in] TC module instance pointer. - * - * \return Index of the given TC module instance. - */ -uint8_t _tc_get_inst_index( - Tc *const hw) -{ - /* List of available TC modules. */ - Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; - - /* Find index for TC instance. */ - for (uint32_t i = 0; i < TC_INST_NUM; i++) { - if (hw == tc_modules[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} - - -/** - * \brief Initializes a hardware TC module instance. - * - * Enables the clock and initializes the TC module, based on the given - * configuration values. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] hw Pointer to the TC hardware module - * \param[in] config Pointer to the TC configuration options struct - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY Hardware module was busy when the - * initialization procedure was attempted - * \retval STATUS_INVALID_ARG An invalid configuration option or argument - * was supplied - * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the - * hardware module is configured in 32-bit - * slave mode - */ -enum status_code tc_init( - struct tc_module *const module_inst, - Tc *const hw, - const struct tc_config *const config) -{ - /* Sanity check arguments */ - Assert(hw); - Assert(module_inst); - Assert(config); - - /* Temporary variable to hold all updates to the CTRLA - * register before they are written to it */ - uint32_t ctrla_tmp = 0; - /* Temporary variable to hold all updates to the CTRLBSET - * register before they are written to it */ - uint8_t ctrlbset_tmp = 0; - /* Temporary variable to hold TC instance number */ - uint8_t instance = _tc_get_inst_index(hw); - -#if (SAMC20) || (SAMC21) - /* Array of GLCK ID for different TC instances */ - uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID}; - /* Array of MCLK APB mask bit position for different TC instances */ - uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0, - SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1, - SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2, - SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3, - SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC4 - }; -#elif (SAML21J) - /* Array of GLCK ID for different TC instances */ - uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID}; - /* Array of MCLK APB mask bit position for different TC instances */ - uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0, - SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1, - SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2, - SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3, - SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4 - }; -#else - /* Array of GLCK ID for different TC instances */ - uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC4_GCLK_ID}; - /* Array of PM APB mask bit position for different TC instances */ - uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0, - SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1, - SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4 - }; -#endif - - struct system_pinmux_config pin_config; - struct system_gclk_chan_config gclk_chan_config; - -#if TC_ASYNC == true - /* Initialize parameters */ - for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - } - module_inst->register_callback_mask = 0x00; - module_inst->enable_callback_mask = 0x00; - - /* Register this instance for callbacks*/ - _tc_instances[instance] = module_inst; -#endif - - /* Associate the given device instance with the hardware module */ - module_inst->hw = hw; - - module_inst->double_buffering_enabled = config->double_buffering_enabled; - - /* Check if odd numbered TC modules are being configured in 32-bit - * counter size. Only even numbered counters are allowed to be - * configured in 32-bit counter size. - */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - ((instance + TC_INSTANCE_OFFSET) & 0x01)) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - /* Make the counter size variable in the module_inst struct reflect - * the counter size in the module - */ - module_inst->counter_size = config->counter_size; - - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } - - if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { - /* Module is used as a slave */ - return STATUS_ERR_DENIED; - } - - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } - - /* Set up the TC PWM out pin for channel 0 */ - if (config->pwm_channel[0].enabled) { - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pwm_channel[0].pin_mux; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pwm_channel[0].pin_out, &pin_config); - } - - /* Set up the TC PWM out pin for channel 1 */ - if (config->pwm_channel[1].enabled) { - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pwm_channel[1].pin_mux; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pwm_channel[1].pin_out, &pin_config); - } - - /* Enable the user interface clock in the MCLK */ - system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[instance*2], - inst_mclk_apbmask[2*instance+1]); - - /* Enable the slave counter if counter_size is 32-bit */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && (instance+1 < TC_INST_NUM)) { - /* Enable the user interface clock in the MCLK */ - system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[instance*2+1], - inst_mclk_apbmask[2*instance+2]); - } - - - /* Setup clock for module */ - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = config->clock_source; - system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); - system_gclk_chan_enable(inst_gclk_id[instance]); - - /* Set ctrla register */ - ctrla_tmp = - (uint32_t)config->counter_size | - (uint32_t)config->reload_action | - (uint32_t)config->clock_prescaler; - - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (config->enable_capture_on_channel[i] == true) { - ctrla_tmp |= (TC_CTRLA_CAPTEN(1) << i); - } - } - - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (config->enable_capture_on_IO[i] == true) { - ctrla_tmp |= (TC_CTRLA_COPEN(1) << i); - } - } - - ctrla_tmp |= (config->run_in_standby << TC_CTRLA_RUNSTDBY_Pos) - |(config->on_demand << TC_CTRLA_ONDEMAND_Pos); - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLA.reg = ctrla_tmp; - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.WAVE.reg = config->wave_generation; - - /* Set ctrlb register */ - if (config->oneshot) { - ctrlbset_tmp = TC_CTRLBSET_ONESHOT; - } - - if (config->count_direction) { - ctrlbset_tmp |= TC_CTRLBSET_DIR; - } - - /* Clear old ctrlb configuration */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLBCLR.reg = 0xFF; - - /* Check if we actually need to go into a wait state. */ - if (ctrlbset_tmp) { - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - /* Write configuration to register */ - hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; - } - - /* Set drvvtrl register*/ - hw->COUNT8.DRVCTRL.reg = config->waveform_invert_output; - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Switch for TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.COUNT.reg = - config->counter_8_bit.value; - - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.PER.reg = - config->counter_8_bit.period; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.CC[0].reg = - config->counter_8_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.CC[1].reg = - config->counter_8_bit.compare_capture_channel[1]; - - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.COUNT.reg - = config->counter_16_bit.value; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.CC[0].reg = - config->counter_16_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.CC[1].reg = - config->counter_16_bit.compare_capture_channel[1]; - - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.COUNT.reg - = config->counter_32_bit.value; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.CC[0].reg = - config->counter_32_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.CC[1].reg = - config->counter_32_bit.compare_capture_channel[1]; - - return STATUS_OK; - } - - Assert(false); - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Sets TC module count value. - * - * Sets the current timer count value of a initialized TC module. The - * specified TC module may be started or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] count New timer count value to set - * - * \return Status of the count update procedure. - * - * \retval STATUS_OK The timer count was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified - */ -enum status_code tc_set_count_value( - const struct tc_module *const module_inst, - const uint32_t count) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance*/ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write to based on the TC counter_size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.COUNT.reg = (uint8_t)count; - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.COUNT.reg = (uint16_t)count; - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.COUNT.reg = (uint32_t)count; - return STATUS_OK; - - default: - return STATUS_ERR_INVALID_ARG; - } -} - -/** - * \brief Get TC module count value. - * - * Retrieves the current count value of a TC module. The specified TC module - * may be started or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Count value of the specified TC module. - */ -uint32_t tc_get_count_value( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Read synchronization */ - tc_sync_read_count(module_inst); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read from based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - return (uint32_t)tc_module->COUNT8.COUNT.reg; - - case TC_COUNTER_SIZE_16BIT: - return (uint32_t)tc_module->COUNT16.COUNT.reg; - - case TC_COUNTER_SIZE_32BIT: - return tc_module->COUNT32.COUNT.reg; - } - - Assert(false); - return 0; -} - -/** - * \brief Gets the TC module capture value. - * - * Retrieves the capture value in the indicated TC module capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the Compare Capture channel to read - * - * \return Capture value stored in the specified timer channel. - */ -uint32_t tc_get_capture_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT8.CC[channel_index].reg; - } - - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT16.CC[channel_index].reg; - } - - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT32.CC[channel_index].reg; - } - } - - Assert(false); - return 0; -} - -/** - * \brief Sets a TC module compare value. - * - * Writes a compare value to the given TC module compare/capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value to set - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied - */ -enum status_code tc_set_compare_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index, - const uint32_t compare) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(compare); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - if (module_inst->double_buffering_enabled) { - tc_module->COUNT8.CCBUF[channel_index].reg = - (uint8_t)compare; - } else { - tc_module->COUNT8.CC[channel_index].reg = - (uint8_t)compare; - } - return STATUS_OK; - } - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - if (module_inst->double_buffering_enabled) { - tc_module->COUNT16.CCBUF[channel_index].reg = - (uint16_t)compare; - } else { - tc_module->COUNT16.CC[channel_index].reg = - (uint16_t)compare; - } - return STATUS_OK; - } - - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - if (module_inst->double_buffering_enabled) { - tc_module->COUNT32.CCBUF[channel_index].reg = - (uint32_t)compare; - } else { - tc_module->COUNT32.CC[channel_index].reg = - (uint32_t)compare; - } - return STATUS_OK; - } - } - - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Resets the TC module. - * - * Resets the TC module, restoring all hardware module registers to their - * default values and disabling the module. The TC module will not be - * accessible while the reset is being performed. - * - * \note When resetting a 32-bit counter only the master TC module's instance - * structure should be passed to the function. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Status of the procedure. - * \retval STATUS_OK The module was reset successfully - * \retval STATUS_ERR_UNSUPPORTED_DEV A 32-bit slave TC module was passed to - * the function. Only use reset on master - * TC - */ -enum status_code tc_reset( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - if (tc_module->STATUS.reg & TC_STATUS_SLAVE) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Disable this module if it is running */ - if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { - tc_disable(module_inst); - while (tc_is_syncing(module_inst)) { - /* wait while module is disabling */ - } - } - - /* Reset this TC module */ - tc_module->CTRLA.reg |= TC_CTRLA_SWRST; - - return STATUS_OK; -} - -/** - * \brief Set the timer TOP/period value. - * - * For 8-bit counter size this function writes the top value to the period - * register. - * - * For 16- and 32-bit counter size this function writes the top value to - * Capture Compare register 0. The value in this register can not be used for - * any other purpose. - * - * \note This function is designed to be used in PWM or frequency - * match modes only. When the counter is set to 16- or 32-bit counter - * size. In 8-bit counter size it will always be possible to change the - * top value even in normal mode. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New timer TOP value to set - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the - * module instance is invalid - */ -enum status_code tc_set_top_value ( - const struct tc_module *const module_inst, - const uint32_t top_value) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(top_value); - - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (module_inst->double_buffering_enabled) { - tc_module->COUNT8.PERBUF.reg = (uint8_t)top_value; - } else { - tc_module->COUNT8.PER.reg = (uint8_t)top_value; - } - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - if (module_inst->double_buffering_enabled) { - tc_module->COUNT16.CCBUF[0].reg = (uint16_t)top_value; - } else { - tc_module->COUNT16.CC[0].reg = (uint16_t)top_value; - } - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - if (module_inst->double_buffering_enabled) { - tc_module->COUNT32.CCBUF[0].reg = (uint32_t)top_value; - } else { - tc_module->COUNT32.CC[0].reg = (uint32_t)top_value; - } - return STATUS_OK; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMR21/tc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMR21/tc.c deleted file mode 100644 index 00702905bea..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMR21/tc.c +++ /dev/null @@ -1,684 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tc.h" - -#if TC_ASYNC == true -# include "tc_interrupt.h" -# include - -/** \internal - * Converts a given TC index to its interrupt vector index. - */ -# define _TC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_TC##n, -#endif - -#if !defined(__DOXYGEN__) -# define _TC_GCLK_ID(n,unused) TPASTE3(TC,n,_GCLK_ID) , -# define _TC_PM_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TC,n) , - -# define TC_INST_GCLK_ID { MRECURSION(TC_INST_NUM, _TC_GCLK_ID, TC_INST_MAX_ID) } -# define TC_INST_PM_APBCMASK { MRECURSION(TC_INST_NUM, _TC_PM_APBCMASK, TC_INST_MAX_ID) } - -#endif - -/** - * \internal Find the index of given TC module instance. - * - * \param[in] TC module instance pointer. - * - * \return Index of the given TC module instance. - */ -uint8_t _tc_get_inst_index( - Tc *const hw) -{ - /* List of available TC modules. */ - Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; - - /* Find index for TC instance. */ - for (uint32_t i = 0; i < TC_INST_NUM; i++) { - if (hw == tc_modules[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} - - -/** - * \brief Initializes a hardware TC module instance. - * - * Enables the clock and initializes the TC module, based on the given - * configuration values. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] hw Pointer to the TC hardware module - * \param[in] config Pointer to the TC configuration options struct - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY Hardware module was busy when the - * initialization procedure was attempted - * \retval STATUS_INVALID_ARG An invalid configuration option or argument - * was supplied - * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the - * hardware module is configured in 32-bit - * slave mode - */ -enum status_code tc_init( - struct tc_module *const module_inst, - Tc *const hw, - const struct tc_config *const config) -{ - /* Sanity check arguments */ - Assert(hw); - Assert(module_inst); - Assert(config); - - /* Temporary variable to hold all updates to the CTRLA - * register before they are written to it */ - uint16_t ctrla_tmp = 0; - /* Temporary variable to hold all updates to the CTRLBSET - * register before they are written to it */ - uint8_t ctrlbset_tmp = 0; - /* Temporary variable to hold all updates to the CTRLC - * register before they are written to it */ - uint8_t ctrlc_tmp = 0; - /* Temporary variable to hold TC instance number */ - uint8_t instance = _tc_get_inst_index(hw); - - /* Array of GLCK ID for different TC instances */ - uint8_t inst_gclk_id[] = TC_INST_GCLK_ID; - /* Array of PM APBC mask bit position for different TC instances */ - uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK; - - struct system_pinmux_config pin_config; - struct system_gclk_chan_config gclk_chan_config; - -#if TC_ASYNC == true - /* Initialize parameters */ - for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - } - module_inst->register_callback_mask = 0x00; - module_inst->enable_callback_mask = 0x00; - - /* Register this instance for callbacks*/ - _tc_instances[instance] = module_inst; -#endif - - /* Associate the given device instance with the hardware module */ - module_inst->hw = hw; - -#if SAMD10 || SAMD11 - /* Check if even numbered TC modules are being configured in 32-bit - * counter size. Only odd numbered counters are allowed to be - * configured in 32-bit counter size. - */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - !((instance + TC_INSTANCE_OFFSET) & 0x01)) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -#else - /* Check if odd numbered TC modules are being configured in 32-bit - * counter size. Only even numbered counters are allowed to be - * configured in 32-bit counter size. - */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - ((instance + TC_INSTANCE_OFFSET) & 0x01)) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -#endif - - /* Make the counter size variable in the module_inst struct reflect - * the counter size in the module - */ - module_inst->counter_size = config->counter_size; - - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } - - if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { - /* Module is used as a slave */ - return STATUS_ERR_DENIED; - } - - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } - - /* Set up the TC PWM out pin for channel 0 */ - if (config->pwm_channel[0].enabled) { - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pwm_channel[0].pin_mux; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pwm_channel[0].pin_out, &pin_config); - } - - /* Set up the TC PWM out pin for channel 1 */ - if (config->pwm_channel[1].enabled) { - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pwm_channel[1].pin_mux; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pwm_channel[1].pin_out, &pin_config); - } - - /* Enable the user interface clock in the PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - inst_pm_apbmask[instance]); - - /* Enable the slave counter if counter_size is 32-bit */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) { - /* Enable the user interface clock in the PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - inst_pm_apbmask[instance + 1]); - } - - /* Setup clock for module */ - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = config->clock_source; - system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); - system_gclk_chan_enable(inst_gclk_id[instance]); - - /* Set ctrla register */ - ctrla_tmp = - (uint32_t)config->counter_size | - (uint32_t)config->wave_generation | - (uint32_t)config->reload_action | - (uint32_t)config->clock_prescaler; - - if (config->run_in_standby) { - ctrla_tmp |= TC_CTRLA_RUNSTDBY; - } - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLA.reg = ctrla_tmp; - - /* Set ctrlb register */ - if (config->oneshot) { - ctrlbset_tmp = TC_CTRLBSET_ONESHOT; - } - - if (config->count_direction) { - ctrlbset_tmp |= TC_CTRLBSET_DIR; - } - - /* Clear old ctrlb configuration */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLBCLR.reg = 0xFF; - - /* Check if we actually need to go into a wait state. */ - if (ctrlbset_tmp) { - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - /* Write configuration to register */ - hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; - } - - /* Set ctrlc register*/ - ctrlc_tmp = config->waveform_invert_output; - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (config->enable_capture_on_channel[i] == true) { - ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i); - } - } - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLC.reg = ctrlc_tmp; - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Switch for TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.COUNT.reg = - config->counter_8_bit.value; - - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.PER.reg = - config->counter_8_bit.period; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.CC[0].reg = - config->counter_8_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT8.CC[1].reg = - config->counter_8_bit.compare_capture_channel[1]; - - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.COUNT.reg - = config->counter_16_bit.value; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.CC[0].reg = - config->counter_16_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.CC[1].reg = - config->counter_16_bit.compare_capture_channel[1]; - - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.COUNT.reg - = config->counter_32_bit.value; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.CC[0].reg = - config->counter_32_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT32.CC[1].reg = - config->counter_32_bit.compare_capture_channel[1]; - - return STATUS_OK; - } - - Assert(false); - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Sets TC module count value. - * - * Sets the current timer count value of a initialized TC module. The - * specified TC module may be started or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] count New timer count value to set - * - * \return Status of the count update procedure. - * - * \retval STATUS_OK The timer count was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified - */ -enum status_code tc_set_count_value( - const struct tc_module *const module_inst, - const uint32_t count) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance*/ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write to based on the TC counter_size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.COUNT.reg = (uint8_t)count; - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.COUNT.reg = (uint16_t)count; - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.COUNT.reg = (uint32_t)count; - return STATUS_OK; - - default: - return STATUS_ERR_INVALID_ARG; - } -} - -/** - * \brief Get TC module count value. - * - * Retrieves the current count value of a TC module. The specified TC module - * may be started or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Count value of the specified TC module. - */ -uint32_t tc_get_count_value( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read from based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - return (uint32_t)tc_module->COUNT8.COUNT.reg; - - case TC_COUNTER_SIZE_16BIT: - return (uint32_t)tc_module->COUNT16.COUNT.reg; - - case TC_COUNTER_SIZE_32BIT: - return tc_module->COUNT32.COUNT.reg; - } - - Assert(false); - return 0; -} - -/** - * \brief Gets the TC module capture value. - * - * Retrieves the capture value in the indicated TC module capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the Compare Capture channel to read - * - * \return Capture value stored in the specified timer channel. - */ -uint32_t tc_get_capture_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT8.CC[channel_index].reg; - } - - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT16.CC[channel_index].reg; - } - - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT32.CC[channel_index].reg; - } - } - - Assert(false); - return 0; -} - -/** - * \brief Sets a TC module compare value. - * - * Writes a compare value to the given TC module compare/capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value to set - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied - */ -enum status_code tc_set_compare_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index, - const uint32_t compare) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT8.CC[channel_index].reg = - (uint8_t)compare; - return STATUS_OK; - } - - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT16.CC[channel_index].reg = - (uint16_t)compare; - return STATUS_OK; - } - - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT32.CC[channel_index].reg = - (uint32_t)compare; - return STATUS_OK; - } - } - - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Resets the TC module. - * - * Resets the TC module, restoring all hardware module registers to their - * default values and disabling the module. The TC module will not be - * accessible while the reset is being performed. - * - * \note When resetting a 32-bit counter only the master TC module's instance - * structure should be passed to the function. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Status of the procedure. - * \retval STATUS_OK The module was reset successfully - * \retval STATUS_ERR_UNSUPPORTED_DEV A 32-bit slave TC module was passed to - * the function. Only use reset on master - * TC - */ -enum status_code tc_reset( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - if (tc_module->STATUS.reg & TC_STATUS_SLAVE) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Disable this module if it is running */ - if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { - tc_disable(module_inst); - while (tc_is_syncing(module_inst)) { - /* wait while module is disabling */ - } - } - - /* Reset this TC module */ - tc_module->CTRLA.reg |= TC_CTRLA_SWRST; - - return STATUS_OK; -} - -/** - * \brief Set the timer TOP/period value. - * - * For 8-bit counter size this function writes the top value to the period - * register. - * - * For 16- and 32-bit counter size this function writes the top value to - * Capture Compare register 0. The value in this register can not be used for - * any other purpose. - * - * \note This function is designed to be used in PWM or frequency - * match modes only. When the counter is set to 16- or 32-bit counter - * size. In 8-bit counter size it will always be possible to change the - * top value even in normal mode. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New timer TOP value to set - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the - * module instance is invalid - */ -enum status_code tc_set_top_value ( - const struct tc_module *const module_inst, - const uint32_t top_value) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(top_value); - - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.PER.reg = (uint8_t)top_value; - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.CC[0].reg = (uint16_t)top_value; - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.CC[0].reg = (uint32_t)top_value; - return STATUS_OK; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc.h deleted file mode 100644 index 7a45564dcbc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc.h +++ /dev/null @@ -1,1764 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef TC_H_INCLUDED -#define TC_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_tc_group SAM Timer/Counter Driver (TC) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of the timer modules within the device, for waveform - * generation and timing operations. The following driver API modes are covered - * by this manual: - * - * - Polled APIs - * \if TC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * - * The following peripherals are used by this module: - * - TC (Timer/Counter) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_tc_prerequisites - * - \ref asfdoc_sam0_tc_module_overview - * - \ref asfdoc_sam0_tc_special_considerations - * - \ref asfdoc_sam0_tc_extra_info - * - \ref asfdoc_sam0_tc_examples - * - \ref asfdoc_sam0_tc_api_overview - * - * - * \section asfdoc_sam0_tc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_tc_module_overview Module Overview - * - * The Timer/Counter (TC) module provides a set of timing and counting related - * functionality, such as the generation of periodic waveforms, the capturing - * of a periodic waveform's frequency/duty cycle, and software timekeeping for - * periodic operations. TC modules can be configured to use an 8-, 16-, or - * 32-bit counter size. - * - * This TC module for the SAM is capable of the following functions: - * - * - Generation of PWM signals - * - Generation of timestamps for events - * - General time counting - * - Waveform period capture - * - Waveform frequency capture - * - * \ref asfdoc_sam0_tc_block_diagram "The diagram below" shows the overview - * of the TC module design. - * - * \anchor asfdoc_sam0_tc_block_diagram - * \image html overview.svg "Basic Overview of the TC Module" - * - * - * \subsection asfdoc_sam0_tc_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_TC_DOUBLE_BUFFEREDSAML21/C20/C21
FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2SAML21/C20/C21
FEATURE_TC_STAMP_PW_CAPTURESAML21/C20/C21
FEATURE_TC_READ_SYNCSAML21/C20/C21
FEATURE_TC_IO_CAPTURESAML21/C20/C21
FEATURE_TC_GENERATE_DMA_TRIGGERSAML21
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_tc_module_overview_func_desc Functional Description - * Independent of the configured counter size, each TC module can be set up - * in one of two different modes; capture and compare. - * - * In capture mode, the counter value is stored when a configurable event - * occurs. This mode can be used to generate timestamps used in event capture, - * or it can be used for the measurement of a periodic input signal's - * frequency/duty cycle. - * - * In compare mode, the counter value is compared against one or more of the - * configured channel compare values. When the counter value coincides with a - * compare value an action can be taken automatically by the module, such as - * generating an output event or toggling a pin when used for frequency or PWM - * signal generation. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * \subsection asfdoc_sam0_tc_module_overview_tc_size Timer/Counter Size - * Each timer module can be configured in one of three different counter - * sizes; 8-, 16-, and 32-bit. The size of the counter determines the maximum - * value it can count to before an overflow occurs and the count is reset back - * to zero. \ref asfdoc_sam0_tc_count_size_vs_top "The table below" shows the - * maximum values for each of the possible counter sizes. - * - * \anchor asfdoc_sam0_tc_count_size_vs_top - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Timer Counter Sizes and Their Maximum Count Values
Counter sizeMax. (hexadecimal)Max. (decimal)
8-bit0xFF255
16-bit0xFFFF65,535
32-bit0xFFFFFFFF4,294,967,295
- * - * When using the counter in 16- or 32-bit count mode, Compare Capture - * register 0 (CC0) is used to store the period value when running in PWM - * generation match mode. - * - * When using 32-bit counter size, two 16-bit counters are chained together - * in a cascade formation. Except in SAM D10/D11, Even numbered TC modules - * (e.g. TC0, TC2) can be configured as 32-bit counters. The odd numbered - * counters will act as slaves to the even numbered masters, and will not - * be reconfigurable until the master timer is disabled. The pairing of timer - * modules for 32-bit mode is shown in \ref asfdoc_sam0_tc_module_ms_pairs - * "the table below". - * - * \anchor asfdoc_sam0_tc_module_ms_pairs - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TC Master and Slave Module Pairings
Master TC ModuleSlave TC Module
TC0TC1
TC2TC3
......
TCn-1TCn
- * - * In SAMD10/D11, odd numbered TC modules (e.g. TC1) can be configured as 32-bit - * counters. The even numbered(e.g. TC2) counters will act as slaves to the odd - * numbered masters. - * - * \subsection asfdoc_sam0_tc_module_overview_clock Clock Settings - * - * \subsubsection asfdoc_sam0_tc_module_overview_clock_selection Clock Selection - * Each TC peripheral is clocked asynchronously to the system clock by a GCLK - * (Generic Clock) channel. The GCLK channel connects to any of the GCLK - * generators. The GCLK generators are configured to use one of the available - * clock sources on the system such as internal oscillator, external crystals, - * etc. see the \ref asfdoc_sam0_system_clock_group "Generic Clock driver" - *for - * more information. - * - * \subsubsection asfdoc_sam0_tc_module_overview_clock_prescaler Prescaler - * Each TC module in the SAM has its own individual clock prescaler, which - * can be used to divide the input clock frequency used in the counter. This - * prescaler only scales the clock used to provide clock pulses for the counter - * to count, and does not affect the digital register interface portion of - * the module, thus the timer registers will synchronize to the raw GCLK - * frequency input to the module. - * - * As a result of this, when selecting a GCLK frequency and timer prescaler - * value the user application should consider both the timer resolution - * required and the synchronization frequency, to avoid lengthy - * synchronization times of the module if a very slow GCLK frequency is fed - * into the TC module. It is preferable to use a higher module GCLK frequency - * as the input to the timer, and prescale this down as much as possible to - * obtain a suitable counter frequency in latency-sensitive applications. - * - * \subsubsection asfdoc_sam0_tc_module_overview_clock_reloading Reloading - * Timer modules also contain a configurable reload action, used when a - * re-trigger event occurs. Examples of a re-trigger event are the counter - * reaching the maximum value when counting up, or when an event from the event - * system tells the counter to re-trigger. The reload action determines if the - * prescaler should be reset, and when this should happen. The counter will - * always be reloaded with the value it is set to start counting from. The user - * can choose between three different reload actions, described in - * \ref asfdoc_sam0_tc_module_reload_act "the table below". - * - * \anchor asfdoc_sam0_tc_module_reload_act - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TC Module Reload Actions
Reload actionDescription
\ref TC_RELOAD_ACTION_GCLK Reload TC counter value on next GCLK cycle. Leave prescaler - * as-is.
\ref TC_RELOAD_ACTION_PRESC Reloads TC counter value on next prescaler clock. Leave prescaler - * as-is.
\ref TC_RELOAD_ACTION_RESYNC Reload TC counter value on next GCLK cycle. Clear prescaler to - * zero.
- * - * The reload action to use will depend on the specific application being - * implemented. One example is when an external trigger for a reload occurs; if - * the TC uses the prescaler, the counter in the prescaler should not have a - * value between zero and the division factor. The TC counter and the counter - * in the prescaler should both start at zero. When the counter is set to - * re-trigger when it reaches the maximum value on the other hand, this is not the - * right option to use. In such a case it would be better if the prescaler is - * left unaltered when the re-trigger happens, letting the counter reset on the - * next GCLK cycle. - * - * \subsection asfdoc_sam0_tc_module_overview_compare_match Compare Match Operations - * In compare match operation, Compare/Capture registers are used in comparison - * with the counter value. When the timer's count value matches the value of a - * compare channel, a user defined action can be taken. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_timer Basic Timer - * - * A Basic Timer is a simple application where compare match operations is used - * to determine when a specific period has elapsed. In Basic Timer operations, - * one or more values in the module's Compare/Capture registers are used to - * specify the time (as a number of prescaled GCLK cycles) when an action should - * be taken by the microcontroller. This can be an Interrupt Service Routine - * (ISR), event generator via the event system, or a software flag that is - * polled via the user application. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg Waveform Generation - * - * Waveform generation enables the TC module to generate square waves, or if - * combined with an external passive low-pass filter; analog waveforms. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_pwm Waveform Generation - PWM - * - * Pulse width modulation is a form of waveform generation and a signalling - * technique that can be useful in many situations. When PWM mode is used, - * a digital pulse train with a configurable frequency and duty cycle can be - * generated by the TC module and output to a GPIO pin of the device. - * - * Often PWM is used to communicate a control or information parameter to an - * external circuit or component. Differing impedances of the source generator - * and sink receiver circuits is less of an issue when using PWM compared to - * using an analog voltage value, as noise will not generally affect the - * signal's integrity to a meaningful extent. - * - * \ref asfdoc_sam0_tc_module_pwm_normal_diag "The figure below" illustrates - * operations and different states of the counter and its output when running - * the counter in PWM normal mode. As can be seen, the TOP value is unchanged - * and is set to MAX. The compare match value is changed at several points to - * illustrate the resulting waveform output changes. The PWM output is set to - * normal (i.e. non-inverted) output mode. - * - * \anchor asfdoc_sam0_tc_module_pwm_normal_diag - * \image html pwm_normal_ex.svg "Example of PWM in Normal Mode, and Different Counter Operations" - * - * - * In \ref asfdoc_sam0_tc_module_pwm_match_diag "the figure below", the - * counter is set to generate PWM in Match mode. The PWM output is inverted via - * the appropriate configuration option in the TC driver configuration - * structure. In this example, the counter value is changed once, but the - * compare match value is kept unchanged. As can be seen, it is possible to - * change the TOP value when running in PWM match mode. - * - * \anchor asfdoc_sam0_tc_module_pwm_match_diag - * \image html pwm_match_ex.svg "Example of PWM in Match Mode, and Different Counter Operations" - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_freq Waveform Generation - Frequency - * - * Frequency Generation mode is in many ways identical to PWM - * generation. However, in Frequency Generation a toggle only occurs - * on the output when a match on a capture channels occurs. When the - * match is made, the timer value is reset, resulting in a variable - * frequency square wave with a fixed 50% duty cycle. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt Capture Operations - * - * In capture operations, any event from the event system or a pin change can - * trigger a capture of the counter value. This captured counter value can be - * used as a timestamp for the event, or it can be used in frequency and pulse - * width capture. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_event_capture Capture Operations - Event - * - * Event capture is a simple use of the capture functionality, - * designed to create timestamps for specific events. When the TC - * module's input capture pin is externally toggled, the current timer - * count value is copied into a buffered register which can then be - * read out by the user application. - * - * Note that when performing any capture operation, there is a risk that the - * counter reaches its top value (MAX) when counting up, or the bottom value - * (zero) when counting down, before the capture event occurs. This can distort - * the result, making event timestamps to appear shorter than reality; the - * user application should check for timer overflow when reading a capture - * result in order to detect this situation and perform an appropriate - * adjustment. - * - * Before checking for a new capture, \ref TC_STATUS_COUNT_OVERFLOW - * should be checked. The response to an overflow error is left to the user - * application, however it may be necessary to clear both the capture overflow - * flag and the capture flag upon each capture reading. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_pwc Capture Operations - Pulse Width - * - * Pulse Width Capture mode makes it possible to measure the pulse width and - * period of PWM signals. This mode uses two capture channels of the counter. - * This means that the counter module used for Pulse Width Capture can not be - * used for any other purpose. There are two modes for pulse width capture; - * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture - * channel 0 is used for storing the pulse width and capture channel 1 stores - * the observed period. While in PPW mode, the roles of the two capture channels - * is reversed. - * - * As in the above example it is necessary to poll on interrupt flags to see - * if a new capture has happened and check that a capture overflow error has - * not occurred. - * - * \subsection asfdoc_sam0_tc_module_overview_oneshot One-shot Mode - * - * TC modules can be configured into a one-shot mode. When configured in this - * manner, starting the timer will cause it to count until the next overflow - * or underflow condition before automatically halting, waiting to be manually - * triggered by the user application software or an event signal from the event - * system. - * - * \subsubsection asfdoc_sam0_tc_module_overview_inversion Wave Generation Output Inversion - * - * The output of the wave generation can be inverted by hardware if desired, - * resulting in the logically inverted value being output to the configured - * device GPIO pin. - * - * - * \section asfdoc_sam0_tc_special_considerations Special Considerations - * - * The number of capture compare registers in each TC module is dependent on - * the specific SAM device being used, and in some cases the counter size. - * - * The maximum amount of capture compare registers available in any SAM - * device is two when running in 32-bit mode and four in 8- and 16-bit modes. - * - * - * \section asfdoc_sam0_tc_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_tc_extra. This includes: - * - \ref asfdoc_sam0_tc_extra_acronyms - * - \ref asfdoc_sam0_tc_extra_dependencies - * - \ref asfdoc_sam0_tc_extra_errata - * - \ref asfdoc_sam0_tc_extra_history - * - * - * \section asfdoc_sam0_tc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_tc_exqsg. - * - * \section asfdoc_sam0_tc_api_overview API Overview - * @{ - */ - -#include -#include -#include -#include - -/** - * Define port features set according to different device family - * @{ -*/ -#if (SAML21) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** TC double buffered. */ -# define FEATURE_TC_DOUBLE_BUFFERED -/** SYNCBUSY scheme version 2. */ -# define FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2 -/** TC time stamp capture and pulse width capture. */ -# define FEATURE_TC_STAMP_PW_CAPTURE -/** Read synchronization of COUNT. */ -# define FEATURE_TC_READ_SYNC -/** IO pin edge capture. */ -# define FEATURE_TC_IO_CAPTURE -/** Generate DMA triggers. */ -# define FEATURE_TC_GENERATE_DMA_TRIGGER -#endif -/*@}*/ - -#if !defined(__DOXYGEN__) -#if SAMD20 || SAML21 || SAMC20 || SAMC21 -# define TC_INSTANCE_OFFSET 0 -#endif -#if SAMD21 || SAMR21 || SAMDA1 -# define TC_INSTANCE_OFFSET 3 -#endif -#if SAMD10 || SAMD11 -# define TC_INSTANCE_OFFSET 1 -#endif - -#if SAMD20 -# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC8_NUM -#elif SAML21 || SAMC20 || SAMC21 -# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC_NUM -#elif SAMD10 || SAMD11 -# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC1_CC8_NUM -#else -# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC3_CC8_NUM -/* Same number for 8-, 16- and 32-bit TC and all TC instances */ -#endif - -/** TC Instance MAX ID Number. */ -#if SAMD20E || SAMD21G || SAMD21E || SAMR21 -#define TC_INST_MAX_ID 5 -#elif SAML21 || SAMC20 || SAMC21 -#define TC_INST_MAX_ID 4 -#elif SAMD10 || SAMD11 -#define TC_INST_MAX_ID 2 -#else -#define TC_INST_MAX_ID 7 -#endif - -#endif - -#if TC_ASYNC == true -# include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if TC_ASYNC == true -/** Enum for the possible callback types for the TC module. */ -enum tc_callback { - /** Callback for TC overflow. */ - TC_CALLBACK_OVERFLOW, - /** Callback for capture overflow error. */ - TC_CALLBACK_ERROR, - /** Callback for capture compare channel 0. */ - TC_CALLBACK_CC_CHANNEL0, - /** Callback for capture compare channel 1. */ - TC_CALLBACK_CC_CHANNEL1, -# if !defined(__DOXYGEN__) - /** Number of available callbacks. */ - TC_CALLBACK_N, -# endif -}; -#endif - -/** - * \name Module Status Flags - * - * TC status flags, returned by \ref tc_get_status() and cleared by - * \ref tc_clear_status(). - * - * @{ - */ - -/** Timer channel 0 has matched against its compare value, or has captured a - * new value. - */ -#define TC_STATUS_CHANNEL_0_MATCH (1UL << 0) - -/** Timer channel 1 has matched against its compare value, or has captured a - * new value. - */ -#define TC_STATUS_CHANNEL_1_MATCH (1UL << 1) - -/** Timer register synchronization has completed, and the synchronized count - * value may be read. - */ -#define TC_STATUS_SYNC_READY (1UL << 2) - -/** A new value was captured before the previous value was read, resulting in - * lost data. - */ -#define TC_STATUS_CAPTURE_OVERFLOW (1UL << 3) - -/** The timer count value has overflowed from its maximum value to its minimum - * when counting upward, or from its minimum value to its maximum when - * counting downward. - */ -#define TC_STATUS_COUNT_OVERFLOW (1UL << 4) - -#ifdef FEATURE_TC_DOUBLE_BUFFERED -/** Channel 0 compare or capture buffer valid. */ -#define TC_STATUS_CHN0_BUFFER_VALID (1UL << 5) -/** Channel 1 compare or capture buffer valid. */ -#define TC_STATUS_CHN1_BUFFER_VALID (1UL << 6) -/** Period buffer valid. */ -#define TC_STATUS_PERIOD_BUFFER_VALID (1UL << 7) -#endif -/** @} */ - -/** - * \brief Index of the compare capture channels. - * - * This enum is used to specify which capture/compare channel to do - * operations on. - */ -enum tc_compare_capture_channel { - /** Index of compare capture channel 0. */ - TC_COMPARE_CAPTURE_CHANNEL_0, - /** Index of compare capture channel 1. */ - TC_COMPARE_CAPTURE_CHANNEL_1, -}; - -/** TC wave generation mode. */ -#if SAML21 || SAMC20 || SAMC21 -#define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_WAVE_WAVEGEN_NFRQ -#define TC_WAVE_GENERATION_MATCH_FREQ_MODE TC_WAVE_WAVEGEN_MFRQ -#define TC_WAVE_GENERATION_NORMAL_PWM_MODE TC_WAVE_WAVEGEN_NPWM -#define TC_WAVE_GENERATION_MATCH_PWM_MODE TC_WAVE_WAVEGEN_MPWM -#else -#define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_CTRLA_WAVEGEN_NFRQ -#define TC_WAVE_GENERATION_MATCH_FREQ_MODE TC_CTRLA_WAVEGEN_MFRQ -#define TC_WAVE_GENERATION_NORMAL_PWM_MODE TC_CTRLA_WAVEGEN_NPWM -#define TC_WAVE_GENERATION_MATCH_PWM_MODE TC_CTRLA_WAVEGEN_MPWM -#endif - -/** - * \brief TC wave generation mode enum. - * - * This enum is used to select which mode to run the wave - * generation in. - * - */ -enum tc_wave_generation { - /** Top is maximum, except in 8-bit counter size where it is the PER - * register. - */ - TC_WAVE_GENERATION_NORMAL_FREQ = TC_WAVE_GENERATION_NORMAL_FREQ_MODE, - - /** Top is CC0, except in 8-bit counter size where it is the PER - * register. - */ - TC_WAVE_GENERATION_MATCH_FREQ = TC_WAVE_GENERATION_MATCH_FREQ_MODE, - - /** Top is maximum, except in 8-bit counter size where it is the PER - * register. - */ - TC_WAVE_GENERATION_NORMAL_PWM = TC_WAVE_GENERATION_NORMAL_PWM_MODE, - - /** Top is CC0, except in 8-bit counter size where it is the PER - * register. - */ - TC_WAVE_GENERATION_MATCH_PWM = TC_WAVE_GENERATION_MATCH_PWM_MODE, -}; - -/** - * \brief Specifies if the counter is 8-, 16-, or 32-bit. - * - * This enum specifies the maximum value it is possible to count to. - */ -enum tc_counter_size { - /** The counter's maximum value is 0xFF, the period register is - * available to be used as top value. - */ - TC_COUNTER_SIZE_8BIT = TC_CTRLA_MODE_COUNT8, - - /** The counter's maximum value is 0xFFFF. There is no separate - * period register, to modify top one of the capture compare - * registers has to be used. This limits the amount of - * available channels. - */ - TC_COUNTER_SIZE_16BIT = TC_CTRLA_MODE_COUNT16, - - /** The counter's maximum value is 0xFFFFFFFF. There is no separate - * period register, to modify top one of the capture compare - * registers has to be used. This limits the amount of - * available channels. - */ - TC_COUNTER_SIZE_32BIT = TC_CTRLA_MODE_COUNT32, -}; - -/** - * \brief TC Counter reload action enum. - * - * This enum specify how the counter and prescaler should reload. - */ -enum tc_reload_action { - /** The counter is reloaded/reset on the next GCLK and starts - * counting on the prescaler clock. - */ - TC_RELOAD_ACTION_GCLK = TC_CTRLA_PRESCSYNC_GCLK, - - /** The counter is reloaded/reset on the next prescaler clock. - */ - TC_RELOAD_ACTION_PRESC = TC_CTRLA_PRESCSYNC_PRESC, - - /** The counter is reloaded/reset on the next GCLK, and the - * prescaler is restarted as well. - */ - TC_RELOAD_ACTION_RESYNC = TC_CTRLA_PRESCSYNC_RESYNC, -}; - -/** - * \brief TC clock prescaler values. - * - * This enum is used to choose the clock prescaler - * configuration. The prescaler divides the clock frequency of the TC - * module to make the counter count slower. - */ -enum tc_clock_prescaler { - /** Divide clock by 1. */ - TC_CLOCK_PRESCALER_DIV1 = TC_CTRLA_PRESCALER(0), - /** Divide clock by 2. */ - TC_CLOCK_PRESCALER_DIV2 = TC_CTRLA_PRESCALER(1), - /** Divide clock by 4. */ - TC_CLOCK_PRESCALER_DIV4 = TC_CTRLA_PRESCALER(2), - /** Divide clock by 8. */ - TC_CLOCK_PRESCALER_DIV8 = TC_CTRLA_PRESCALER(3), - /** Divide clock by 16. */ - TC_CLOCK_PRESCALER_DIV16 = TC_CTRLA_PRESCALER(4), - /** Divide clock by 64. */ - TC_CLOCK_PRESCALER_DIV64 = TC_CTRLA_PRESCALER(5), - /** Divide clock by 256. */ - TC_CLOCK_PRESCALER_DIV256 = TC_CTRLA_PRESCALER(6), - /** Divide clock by 1024. */ - TC_CLOCK_PRESCALER_DIV1024 = TC_CTRLA_PRESCALER(7), -}; - -/** - * \brief TC module count direction. - * - * Timer/Counter count direction. - */ -enum tc_count_direction { - /** Timer should count upward from zero to MAX. */ - TC_COUNT_DIRECTION_UP, - - /** Timer should count downward to zero from MAX. */ - TC_COUNT_DIRECTION_DOWN, -}; - -/** Waveform inversion mode. */ -#if SAML21 || SAMC20 || SAMC21 -#define TC_WAVEFORM_INVERT_CC0_MODE TC_DRVCTRL_INVEN(1) -#define TC_WAVEFORM_INVERT_CC1_MODE TC_DRVCTRL_INVEN(2) -#else -#define TC_WAVEFORM_INVERT_CC0_MODE TC_CTRLC_INVEN(1) -#define TC_WAVEFORM_INVERT_CC1_MODE TC_CTRLC_INVEN(2) -#endif - -/** - * \brief Waveform inversion mode. - * - * Output waveform inversion mode. - */ -enum tc_waveform_invert_output { - /** No inversion of the waveform output. */ - TC_WAVEFORM_INVERT_OUTPUT_NONE = 0, - /** Invert output from compare channel 0. */ - TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE, - /** Invert output from compare channel 1. */ - TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE, -}; - -/** - * \brief Action to perform when the TC module is triggered by an event. - * - * Event action to perform when the module is triggered by an event. - */ -enum tc_event_action { - /** No event action. */ - TC_EVENT_ACTION_OFF = TC_EVCTRL_EVACT_OFF, - /** Re-trigger on event. */ - TC_EVENT_ACTION_RETRIGGER = TC_EVCTRL_EVACT_RETRIGGER, - /** Increment counter on event. */ - TC_EVENT_ACTION_INCREMENT_COUNTER = TC_EVCTRL_EVACT_COUNT, - /** Start counter on event. */ - TC_EVENT_ACTION_START = TC_EVCTRL_EVACT_START, - - /** Store period in capture register 0, pulse width in capture - * register 1. - */ - TC_EVENT_ACTION_PPW = TC_EVCTRL_EVACT_PPW, - - /** Store pulse width in capture register 0, period in capture - * register 1. - */ - TC_EVENT_ACTION_PWP = TC_EVCTRL_EVACT_PWP, -#ifdef FEATURE_TC_STAMP_PW_CAPTURE - /** Time stamp capture. */ - TC_EVENT_ACTION_STAMP = TC_EVCTRL_EVACT_STAMP, - /** Pulse width capture. */ - TC_EVENT_ACTION_PW = TC_EVCTRL_EVACT_PW, -#endif -}; - -/** - * \brief TC event enable/disable structure. - * - * Event flags for the \ref tc_enable_events() and \ref tc_disable_events(). - */ -struct tc_events { - /** Generate an output event on a compare channel match. */ - bool generate_event_on_compare_channel - [NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; - /** Generate an output event on counter overflow. */ - bool generate_event_on_overflow; - /** Perform the configured event action when an incoming event is signalled. */ - bool on_event_perform_action; - /** Specifies if the input event source is inverted, when used in PWP or - * PPW event action modes. - */ - bool invert_event_input; - /** Specifies which event to trigger if an event is triggered. */ - enum tc_event_action event_action; -}; - -/** - * \brief Configuration struct for TC module in 8-bit size counter mode. - */ -struct tc_8bit_config { - /** Initial timer count value. */ - uint8_t value; - /** Where to count to or from depending on the direction on the counter. */ - uint8_t period; - /** Value to be used for compare match on each channel. */ - uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -}; - -/** - * \brief Configuration struct for TC module in 16-bit size counter mode. - */ -struct tc_16bit_config { - /** Initial timer count value. */ - uint16_t value; - /** Value to be used for compare match on each channel. */ - uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -}; - -/** - * \brief Configuration struct for TC module in 32-bit size counter mode. - */ -struct tc_32bit_config { - /** Initial timer count value. */ - uint32_t value; - /** Value to be used for compare match on each channel. */ - uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -}; - -/** - * \brief Configuration struct for TC module in 32-bit size counter mode. - */ -struct tc_pwm_channel { - /** When \c true, PWM output for the given channel is enabled. */ - bool enabled; - /** Specifies pin output for each channel. */ - uint32_t pin_out; - /** Specifies MUX setting for each output channel pin. */ - uint32_t pin_mux; -}; - -/** - * \brief TC configuration structure. - * - * Configuration struct for a TC instance. This structure should be - * initialized by the \ref tc_get_config_defaults function before being - * modified by the user application. - */ -struct tc_config { - /** GCLK generator used to clock the peripheral. */ - enum gclk_generator clock_source; - - /** When \c true the module is enabled during standby. */ - bool run_in_standby; -#if (SAML21) || (SAMC20) || (SAMC21) - /** Run on demand. */ - bool on_demand; -#endif - /** Specifies either 8-, 16-, or 32-bit counter size. */ - enum tc_counter_size counter_size; - /** Specifies the prescaler value for GCLK_TC. */ - enum tc_clock_prescaler clock_prescaler; - /** Specifies which waveform generation mode to use. */ - enum tc_wave_generation wave_generation; - - /** Specifies the reload or reset time of the counter and prescaler - * resynchronization on a re-trigger event for the TC. - */ - enum tc_reload_action reload_action; - - /** Specifies which channel(s) to invert the waveform on. - For SAML21/C20/C21, it's also used to invert IO input pin. */ - uint8_t waveform_invert_output; - - /** Specifies which channel(s) to enable channel capture - * operation on. - */ - bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -#ifdef FEATURE_TC_IO_CAPTURE - /** Specifies which channel(s) to enable I/O capture - * operation on. - */ - bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -#endif - - /** When \c true, one-shot will stop the TC on next hardware or software - * re-trigger event or overflow/underflow. - */ - bool oneshot; - - /** Specifies the direction for the TC to count. */ - enum tc_count_direction count_direction; - - /** Specifies the PWM channel for TC. */ - struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; - - /** Access the different counter size settings though this configuration member. */ - union { - /** Struct for 8-bit specific timer configuration. */ - struct tc_8bit_config counter_8_bit; - /** Struct for 16-bit specific timer configuration. */ - struct tc_16bit_config counter_16_bit; - /** Struct for 32-bit specific timer configuration. */ - struct tc_32bit_config counter_32_bit; - }; - -#ifdef FEATURE_TC_DOUBLE_BUFFERED - /** Set to \c true to enable double buffering write. When enabled any write - * through \ref tc_set_top_value(), \ref tc_set_compare_value() and - * will direct to the buffer register as buffered - * value, and the buffered value will be committed to effective register - * on UPDATE condition, if update is not locked. - */ - bool double_buffering_enabled; -#endif -}; - -#if TC_ASYNC == true -/* Forward Declaration for the device instance. */ -struct tc_module; - -/* Type of the callback functions. */ -typedef void (*tc_callback_t)(struct tc_module *const module); -#endif - -/** - * \brief TC software device instance structure. - * - * TC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct tc_module { -#if !defined(__DOXYGEN__) - /** Hardware module pointer of the associated Timer/Counter peripheral. */ - Tc *hw; - - /** Size of the initialized Timer/Counter module configuration. */ - enum tc_counter_size counter_size; -# if TC_ASYNC == true - /** Array of callbacks. */ - tc_callback_t callback[TC_CALLBACK_N]; - /** Bit mask for callbacks registered. */ - uint8_t register_callback_mask; - /** Bit mask for callbacks enabled. */ - uint8_t enable_callback_mask; -# endif -#ifdef FEATURE_TC_DOUBLE_BUFFERED - /** Set to \c true to enable double buffering write. */ - bool double_buffering_enabled; -#endif -#endif -}; - -#if !defined(__DOXYGEN__) -uint8_t _tc_get_inst_index( - Tc *const hw); -#endif - -/** - * \name Driver Initialization and Configuration - * @{ - */ - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to - *the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval false If the module has completed synchronization - * \retval true If the module synchronization is ongoing - */ -static inline bool tc_is_syncing( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - -#if (SAML21) || (SAMC20) || (SAMC21) - return (tc_module->SYNCBUSY.reg); -#else - return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY); -#endif -} - -/** - * \brief Initializes config with predefined default values. - * - * This function will initialize a given TC configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structures before being - * modified by the user application. - * - * The default configuration is as follows: - * \li GCLK generator 0 (GCLK main) clock source - * \li 16-bit counter size on the counter - * \li No prescaler - * \li Normal frequency wave generation - * \li GCLK reload action - * \li Don't run in standby - * \li Don't run on demand for SAML21/C20/C21 - * \li No inversion of waveform output - * \li No capture enabled - * \li No I/O capture enabled for SAML21/C20/C21 - * \li No event input enabled - * \li Count upward - * \li Don't perform one-shot operations - * \li No event action - * \li No channel 0 PWM output - * \li No channel 1 PWM output - * \li Counter starts on 0 - * \li Capture compare channel 0 set to 0 - * \li Capture compare channel 1 set to 0 - * \li No PWM pin output enabled - * \li Pin and MUX configuration not set - * \li Double buffer disabled (if have this feature) - * - * \param[out] config Pointer to a TC module configuration structure to set - */ -static inline void tc_get_config_defaults( - struct tc_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Write default config to config struct */ - config->clock_source = GCLK_GENERATOR_0; - config->counter_size = TC_COUNTER_SIZE_16BIT; - config->clock_prescaler = TC_CLOCK_PRESCALER_DIV1; - config->wave_generation = TC_WAVE_GENERATION_NORMAL_FREQ; - config->reload_action = TC_RELOAD_ACTION_GCLK; - config->run_in_standby = false; -#if (SAML21) || (SAMC20) || (SAMC21) - config->on_demand = false; -#endif - config->waveform_invert_output = TC_WAVEFORM_INVERT_OUTPUT_NONE; - config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false; - config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false; -#ifdef FEATURE_TC_IO_CAPTURE - config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false; - config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false; -#endif - - config->count_direction = TC_COUNT_DIRECTION_UP; - config->oneshot = false; - - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0; - - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0; - - config->counter_16_bit.value = 0x0000; - config->counter_16_bit.compare_capture_channel\ - [TC_COMPARE_CAPTURE_CHANNEL_0] = 0x0000; - config->counter_16_bit.compare_capture_channel\ - [TC_COMPARE_CAPTURE_CHANNEL_1] = 0x0000; -#ifdef FEATURE_TC_DOUBLE_BUFFERED - config->double_buffering_enabled = false; -#endif - -} - -enum status_code tc_init( - struct tc_module *const module_inst, - Tc *const hw, - const struct tc_config *const config); - -/** @} */ - -/** - * \name Event Management - * @{ - */ - -/** - * \brief Enables a TC module event input or output. - * - * Enables one or more input or output events to or from the TC module. - * See \ref tc_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] events Struct containing flags of events to enable - */ -static inline void tc_enable_events( - struct tc_module *const module_inst, - struct tc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Tc *const tc_module = module_inst->hw; - - uint32_t event_mask = 0; - - if (events->invert_event_input == true) { - event_mask |= TC_EVCTRL_TCINV; - } - - if (events->on_event_perform_action == true) { - event_mask |= TC_EVCTRL_TCEI; - } - - if (events->generate_event_on_overflow == true) { - event_mask |= TC_EVCTRL_OVFEO; - } - - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (events->generate_event_on_compare_channel[i] == true) { - event_mask |= (TC_EVCTRL_MCEO(1) << i); - } - } - - tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action; -} - -/** - * \brief Disables a TC module event input or output. - * - * Disables one or more input or output events to or from the TC module. - * See \ref tc_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] events Struct containing flags of events to disable - */ -static inline void tc_disable_events( - struct tc_module *const module_inst, - struct tc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Tc *const tc_module = module_inst->hw; - - uint32_t event_mask = 0; - - if (events->invert_event_input == true) { - event_mask |= TC_EVCTRL_TCINV; - } - - if (events->on_event_perform_action == true) { - event_mask |= TC_EVCTRL_TCEI; - } - - if (events->generate_event_on_overflow == true) { - event_mask |= TC_EVCTRL_OVFEO; - } - - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (events->generate_event_on_compare_channel[i] == true) { - event_mask |= (TC_EVCTRL_MCEO(1) << i); - } - } - - tc_module->COUNT8.EVCTRL.reg &= ~event_mask; -} - -/** @} */ - -/** - * \name Enable/Disable/Reset - * @{ - */ - -enum status_code tc_reset( - const struct tc_module *const module_inst); - -/** - * \brief Enable the TC module. - * - * Enables a TC module that has been previously initialized. The counter will - * start when the counter is enabled. - * - * \note When the counter is configured to re-trigger on an event, the counter - * will not start until the start function is used. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_enable( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Enable TC module */ - tc_module->CTRLA.reg |= TC_CTRLA_ENABLE; -} - -/** - * \brief Disables the TC module. - * - * Disables a TC module and stops the counter. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_disable( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Disable TC module */ - tc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; -} - -/** @} */ - -/** - * \name Get/Set Count Value - * @{ - */ - -uint32_t tc_get_count_value( - const struct tc_module *const module_inst); - -enum status_code tc_set_count_value( - const struct tc_module *const module_inst, - const uint32_t count); - -/** @} */ - -/** - * \name Start/Stop Counter - * @{ - */ - -/** - * \brief Stops the counter. - * - * This function will stop the counter. When the counter is stopped - * the value in the count value is set to 0 if the counter was - * counting up, or maximum if the counter was counting - * down when stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_stop_counter( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_STOP_Val); -} - -/** - * \brief Starts the counter. - * - * Starts or restarts an initialized TC module's counter. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_start_counter( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_RETRIGGER_Val); -} - -/** @} */ - -#ifdef FEATURE_TC_DOUBLE_BUFFERED -/** - * \name Double Buffering - * @{ - */ - -/** - * \brief Update double buffer. - * - * Update double buffer. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_update_double_buffer( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_UPDATE_Val); -} -/** @} */ -#endif - -#ifdef FEATURE_TC_READ_SYNC -/** - * \name Count Read Synchronization - * @{ - */ - -/** - * \brief Read synchronization of COUNT. - * - * Read synchronization of COUNT. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_sync_read_count( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_READSYNC_Val); -} -/** @} */ -#endif - -#ifdef FEATURE_TC_GENERATE_DMA_TRIGGER -/** - * \name Generate TC DMA Triggers command - * @{ - */ - -/** - * \brief TC DMA Trigger. - * - * TC DMA trigger command. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_dma_trigger_command( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - -#if SAML21 - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_DMATRG_Val); -#endif -#if (SAMC20) || (SAMC21) - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_DMAOS_Val); -#endif -} -/** @} */ -#endif - -/** - * \name Get Capture Set Compare - * @{ - */ - -uint32_t tc_get_capture_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index); - -enum status_code tc_set_compare_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index, - const uint32_t compare_value); - -/** @} */ - -/** - * \name Set Top Value - * @{ - */ - -enum status_code tc_set_top_value( - const struct tc_module *const module_inst, - const uint32_t top_value); - -/** @} */ - -/** - * \name Status Management - * @{ - */ - -/** - * \brief Retrieves the current module status. - * - * Retrieves the status of the module, giving overall state information. - * - * \param[in] module_inst Pointer to the TC software instance struct - * - * \return Bitmask of \c TC_STATUS_* flags. - * - * \retval TC_STATUS_CHANNEL_0_MATCH Timer channel 0 compare/capture match - * \retval TC_STATUS_CHANNEL_1_MATCH Timer channel 1 compare/capture match - * \retval TC_STATUS_SYNC_READY Timer read synchronization has completed - * \retval TC_STATUS_CAPTURE_OVERFLOW Timer capture data has overflowed - * \retval TC_STATUS_COUNT_OVERFLOW Timer count value has overflowed - * \retval TC_STATUS_CHN0_BUFFER_VALID Timer count channel 0 compare/capture buffer valid - * \retval TC_STATUS_CHN1_BUFFER_VALID Timer count channel 1 compare/capture buffer valid - * \retval TC_STATUS_PERIOD_BUFFER_VALID Timer count period buffer valid - */ -static inline uint32_t tc_get_status( - struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - uint32_t int_flags = tc_module->INTFLAG.reg; - - uint32_t status_flags = 0; - - /* Check for TC channel 0 match */ - if (int_flags & TC_INTFLAG_MC(1)) { - status_flags |= TC_STATUS_CHANNEL_0_MATCH; - } - - /* Check for TC channel 1 match */ - if (int_flags & TC_INTFLAG_MC(2)) { - status_flags |= TC_STATUS_CHANNEL_1_MATCH; - } - -#if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2) - /* Check for TC read synchronization ready */ - if (int_flags & TC_INTFLAG_SYNCRDY) { - status_flags |= TC_STATUS_SYNC_READY; - } -#endif - - /* Check for TC capture overflow */ - if (int_flags & TC_INTFLAG_ERR) { - status_flags |= TC_STATUS_CAPTURE_OVERFLOW; - } - - /* Check for TC count overflow */ - if (int_flags & TC_INTFLAG_OVF) { - status_flags |= TC_STATUS_COUNT_OVERFLOW; - } -#ifdef FEATURE_TC_DOUBLE_BUFFERED - uint8_t double_buffer_valid_status = tc_module->STATUS.reg; - - /* Check channel 0 compare or capture buffer valid */ - if (double_buffer_valid_status & TC_STATUS_CCBUFV0) { - status_flags |= TC_STATUS_CHN0_BUFFER_VALID; - } - /* Check channel 0 compare or capture buffer valid */ - if (double_buffer_valid_status & TC_STATUS_CCBUFV1) { - status_flags |= TC_STATUS_CHN1_BUFFER_VALID; - } - /* Check period buffer valid */ - if (double_buffer_valid_status & TC_STATUS_PERBUFV) { - status_flags |= TC_STATUS_PERIOD_BUFFER_VALID; - } -#endif - - return status_flags; -} - -/** - * \brief Clears a module status flag. - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the TC software instance struct - * \param[in] status_flags Bitmask of \c TC_STATUS_* flags to clear - */ -static inline void tc_clear_status( - struct tc_module *const module_inst, - const uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - uint32_t int_flags = 0; - - /* Check for TC channel 0 match */ - if (status_flags & TC_STATUS_CHANNEL_0_MATCH) { - int_flags |= TC_INTFLAG_MC(1); - } - - /* Check for TC channel 1 match */ - if (status_flags & TC_STATUS_CHANNEL_1_MATCH) { - int_flags |= TC_INTFLAG_MC(2); - } - -#if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2) - /* Check for TC read synchronization ready */ - if (status_flags & TC_STATUS_SYNC_READY) { - int_flags |= TC_INTFLAG_SYNCRDY; - } -#endif - - /* Check for TC capture overflow */ - if (status_flags & TC_STATUS_CAPTURE_OVERFLOW) { - int_flags |= TC_INTFLAG_ERR; - } - - /* Check for TC count overflow */ - if (status_flags & TC_STATUS_COUNT_OVERFLOW) { - int_flags |= TC_INTFLAG_OVF; - } - - /* Clear interrupt flag */ - tc_module->INTFLAG.reg = int_flags; -} - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** - * \page asfdoc_sam0_tc_extra Extra Information for TC Driver - * - * \section asfdoc_sam0_tc_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DMADirect Memory Access
TCTimer Counter
PWMPulse Width Modulation
PWPPulse Width Period
PPWPeriod Pulse Width
- * - * - * \section asfdoc_sam0_tc_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_tc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_tc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Added support for SAMD21 and do some modifications as below: - * \li Clean up in the configuration structure, the counter size - * setting specific registers is accessed through the counter_8_bit, - * counter_16_bit and counter_32_bit structures - * \li All event related settings moved into the tc_event structure
Added automatic digital clock interface enable for the slave TC - * module when a timer is initialized in 32-bit mode
Initial Release
- */ - -/** - * \page asfdoc_sam0_tc_exqsg Examples for TC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_tc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_tc_basic_use_case - * - \subpage asfdoc_sam0_tc_macth_freq_use_case - * \if TC_CALLBACK_MODE - * - \subpage asfdoc_sam0_tc_timer_use_case - * - \subpage asfdoc_sam0_tc_callback_use_case - * \endif - * - \subpage asfdoc_sam0_tc_dma_use_case - * - * \page asfdoc_sam0_tc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
F12/2014Added support for SAMC21.
E04/2015Added support for SAML21 and SAMDAx.
D12/2014Added timer use case. - * Added support for SAMR21 and SAMD10/D11.
C01/2014Added support for SAMD21.
B06/2013Corrected documentation typos.
A06/2013Initial release
- */ - -#endif /* TC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.c deleted file mode 100644 index 2e51b45602c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.c +++ /dev/null @@ -1,195 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Callback Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tc_interrupt.h" - -void *_tc_instances[TC_INST_NUM]; - -void _tc_interrupt_handler(uint8_t instance); - -/** - * \brief Registers a callback. - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref tc_enable_callback, - * in order for the interrupt handler to call it when the conditions for the - * callback type is met. - * - * \param[in] module Pointer to TC software instance struct - * \param[in] callback_func Pointer to callback function - * \param[in] callback_type Callback type given by an enum - */ -enum status_code tc_register_callback( - struct tc_module *const module, - tc_callback_t callback_func, - const enum tc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); - - /* Register callback function */ - module->callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->register_callback_mask |= TC_INTFLAG_MC(1); - } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->register_callback_mask |= TC_INTFLAG_MC(2); - } else { - module->register_callback_mask |= (1 << callback_type); - } - return STATUS_OK; -} - -/** - * \brief Unregisters a callback. - * - * Unregisters a callback function implemented by the user. The callback should be - * disabled before it is unregistered. - * - * \param[in] module Pointer to TC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -enum status_code tc_unregister_callback( - struct tc_module *const module, - const enum tc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Unregister callback function */ - module->callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->register_callback_mask &= ~TC_INTFLAG_MC(1); - } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->register_callback_mask &= ~TC_INTFLAG_MC(2); - } else { - module->register_callback_mask &= ~(1 << callback_type); - } - return STATUS_OK; -} - -/** - * \internal ISR handler for TC - * - * Auto-generate a set of interrupt handlers for each TC in the device. - */ -#define _TC_INTERRUPT_HANDLER(n, m) \ - void TC##n##_Handler(void) \ - { \ - _tc_interrupt_handler(m); \ - } - -#if (SAML21E) || (SAML21G) -_TC_INTERRUPT_HANDLER(0,0) -_TC_INTERRUPT_HANDLER(1,1) -_TC_INTERRUPT_HANDLER(4,2) -#else -MRECURSION(TC_INST_NUM, _TC_INTERRUPT_HANDLER, TC_INST_MAX_ID) -#endif - - -/** - * \internal Interrupt Handler for TC module - * - * Handles interrupts as they occur, it will run the callback functions - * that are registered and enabled. - * - * \param[in] instance ID of the TC instance calling the interrupt - * handler. - */ -void _tc_interrupt_handler( - uint8_t instance) -{ - /* Temporary variable */ - uint8_t interrupt_and_callback_status_mask; - - /* Get device instance from the look-up table */ - struct tc_module *module - = (struct tc_module *)_tc_instances[instance]; - - /* Read and mask interrupt flag register */ - interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg & - module->register_callback_mask & - module->enable_callback_mask; - - /* Check if an Overflow interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_OVERFLOW])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; - } - - /* Check if an Error interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_ERROR])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; - } - - /* Check if an Match/Capture Channel 0 interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1)) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_CC_CHANNEL0])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1); - } - - /* Check if an Match/Capture Channel 1 interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2)) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_CC_CHANNEL1])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2); - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.h deleted file mode 100644 index 8ac9ae3885b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.h +++ /dev/null @@ -1,175 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Callback Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef TC_INTERRUPT_H_INCLUDED -#define TC_INTERRUPT_H_INCLUDED - -#include "tc.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__DOXYGEN__) -extern void *_tc_instances[TC_INST_NUM]; - -# define _TC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_TC##n, -/** - * \internal Get the interrupt vector for the given device instance - * - * \param[in] TC module instance number. - * - * \return Interrupt vector for of the given TC module instance. - */ -static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector( - uint32_t inst_num) -{ - static uint8_t tc_interrupt_vectors[TC_INST_NUM] = { -#if (SAML21E) || (SAML21G) - SYSTEM_INTERRUPT_MODULE_TC0, - SYSTEM_INTERRUPT_MODULE_TC1, - SYSTEM_INTERRUPT_MODULE_TC4 -#else - MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID) -#endif - }; - - return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num]; -} -#endif /* !defined(__DOXYGEN__) */ - -/** - * \name Callback Management - * {@ - */ - -enum status_code tc_register_callback( - struct tc_module *const module, - tc_callback_t callback_func, - const enum tc_callback callback_type); - -enum status_code tc_unregister_callback( - struct tc_module *const module, - const enum tc_callback callback_type); - -/** - * \brief Enables callback. - * - * Enables the callback function registered by the \ref - * tc_register_callback. The callback function will be called from the - * interrupt handler when the conditions for the callback type are - * met. This function will also enable the appropriate interrupts. - * - * \param[in] module Pointer to TC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void tc_enable_callback( - struct tc_module *const module, - const enum tc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - - /* Enable interrupts for this TC module */ - system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw))); - - /* Enable callback */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->enable_callback_mask |= TC_INTFLAG_MC(1); - module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1); - } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->enable_callback_mask |= TC_INTFLAG_MC(2); - module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2); - } else { - module->enable_callback_mask |= (1 << callback_type); - module->hw->COUNT8.INTENSET.reg = (1 << callback_type); - } -} - -/** - * \brief Disables callback. - * - * Disables the callback function registered by the \ref - * tc_register_callback, and the callback will not be called from the - * interrupt routine. The function will also disable the appropriate - * interrupts. - * - * \param[in] module Pointer to TC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void tc_disable_callback( - struct tc_module *const module, - const enum tc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Disable callback */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1); - module->enable_callback_mask &= ~TC_INTFLAG_MC(1); - } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2); - module->enable_callback_mask &= ~TC_INTFLAG_MC(2); - } else { - module->hw->COUNT8.INTENCLR.reg = (1 << callback_type); - module->enable_callback_mask &= ~(1 << callback_type); - } -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* TC_INTERRUPT_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c deleted file mode 100644 index 68e9defcc36..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c +++ /dev/null @@ -1,1593 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - Timer Counter for Control Applications Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tcc.h" - -#if TCC_ASYNC == true -# include "tcc_callback.h" -# include - -/** \internal - * Converts a given TCC index to its interrupt vector index. - */ -# define _TCC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_TCC##n, -#endif - -#define _SIZE_MAX(size) ((size==32u) ? 0xFFFFFFFF : ( \ - (1u << size) - 1)) - -#define _SIZE_MAX_WITH_DITHER 0x03FFFFFF - -/* Extension support mapping bits */ -#define _TCC_DITHERING_B 16u -#define _TCC_PG_B 8u -#define _TCC_SWAP_B 4u -#define _TCC_DTI_B 2u -#define _TCC_OTMX_B 1u - -#if !defined(__DOXYGEN__) - -# define _TCC_GCLK_ID(n,unused) TPASTE3(TCC,n,_GCLK_ID), -# if (SAML21) || (SAMC20) || (SAMC21) -# define _TCC_APBCMASK(n,unused) TPASTE2(MCLK_APBCMASK_TCC,n), -# else -# define _TCC_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TCC,n), -# endif - -# define _TCC_SIZE(n,unused) TPASTE3(TCC,n,_SIZE), -# define _TCC_MAX(n,unused) _SIZE_MAX(TPASTE3(TCC,n,_SIZE)), -# define _TCC_EXT(n,unused) TPASTE3(TCC,n,_EXT), -# define _TCC_CC_NUM(n,unused) min(TPASTE3(TCC,n,_CC_NUM),TCC_NUM_CHANNELS), -# define _TCC_OW_NUM(n,unused) min(TPASTE3(TCC,n,_OW_NUM),TCC_NUM_WAVE_OUTPUTS), - -# define TCC_GCLK_IDS { MREPEAT(TCC_INST_NUM, _TCC_GCLK_ID, 0) } -# define TCC_APBCMASKS { MREPEAT(TCC_INST_NUM, _TCC_APBCMASK, 0) } - -# define TCC_SIZES { MREPEAT(TCC_INST_NUM, _TCC_SIZE, 0) } -# define TCC_MAXS { MREPEAT(TCC_INST_NUM, _TCC_MAX, 0) } -# define TCC_EXTS { MREPEAT(TCC_INST_NUM, _TCC_EXT, 0) } -# define TCC_CC_NUMS { MREPEAT(TCC_INST_NUM, _TCC_CC_NUM, 0) } -# define TCC_OW_NUMS { MREPEAT(TCC_INST_NUM, _TCC_OW_NUM, 0) } - -#endif - -/* List of available TCC modules. */ -const Tcc *const tcc_modules[TCC_INST_NUM] = TCC_INSTS; - -/* List of TCC GCLK IDs */ -const uint8_t _tcc_gclk_ids[TCC_INST_NUM] = TCC_GCLK_IDS; - -/* List of TCC APBC Masks */ -const uint32_t _tcc_apbcmasks[TCC_INST_NUM] = TCC_APBCMASKS; - -/* List of extension support of TCC modules. */ -const uint8_t _tcc_exts[TCC_INST_NUM] = TCC_EXTS; - -/* List of sizes support of TCC modules. */ -const uint8_t _tcc_sizes[TCC_INST_NUM] = TCC_SIZES; - -/* List of maximumvalues supported of TCC modules. */ -const uint32_t _tcc_maxs[TCC_INST_NUM] = TCC_MAXS; - -/* List of available channel number of TCC modules. */ -const uint8_t _tcc_cc_nums[TCC_INST_NUM] = TCC_CC_NUMS; - -/* List of available output number of TCC modules. */ -const uint8_t _tcc_ow_nums[TCC_INST_NUM] = TCC_OW_NUMS; - -/** - * \internal Find the index of the given TCC module instance. - * - * \param[in] The TCC module instance pointer - * - * \return Index of the given TCC module instance. - */ -uint8_t _tcc_get_inst_index( - Tcc *const hw) -{ - /* Find index for TCC instance. */ - for (uint32_t i = 0; i < TCC_INST_NUM; i++) { - if (hw == tcc_modules[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} - -/** - * \brief Initializes config with predefined default values. - * - * This function will initialize a given TCC configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structures before being - * modified by the user application. - * - * The default configuration is as follows: - * \li Don't run in standby - * \li When setting top,compare or pattern by API, do double buffering write - * \li The base timer/counter configurations: - * - GCLK generator 0 clock source - * - No prescaler - * - GCLK reload action - * - Count upward - * - Don't perform one-shot operations - * - Counter starts on 0 - * - Period/top value set to maximum - * \li The match/capture configurations: - * - All Capture compare channel value set to 0 - * - No capture enabled (all channels use compare function) - * - Normal frequency wave generation - * - Waveform generation polarity set to 0 - * - Don't perform ramp on waveform - * \li The waveform extension configurations: - * - No recoverable fault is enabled, fault actions are disabled, filter - * is set to 0 - * - No non-recoverable fault state output is enabled and filter is 0 - * - No inversion of waveform output - * \li No channel output enabled - * \li No PWM pin output enabled - * \li Pin and MUX configuration not set - * - * \param[out] config Pointer to a TCC module configuration structure to set - * \param[in] hw Pointer to the TCC hardware module - * - */ -void tcc_get_config_defaults( - struct tcc_config *const config, - Tcc *const hw) -{ - /* TCC instance index */ - uint8_t module_index = _tcc_get_inst_index(hw); - - /* Base counter defaults */ - config->counter.count = 0; - - config->counter.period = _tcc_maxs[module_index]; - - config->counter.clock_source = GCLK_GENERATOR_0; - config->counter.clock_prescaler = TCC_CLOCK_PRESCALER_DIV1; - config->counter.reload_action = TCC_RELOAD_ACTION_GCLK; - - config->counter.direction = TCC_COUNT_DIRECTION_UP; - config->counter.oneshot = false; - - /* Match/Capture defaults */ -# define _TCC_CHANNEL_MATCH_VALUE_INIT(n, value) \ - config->compare.match[n] = value; - MREPEAT(TCC_NUM_CHANNELS, - _TCC_CHANNEL_MATCH_VALUE_INIT, 0) -# undef _TCC_CHANNEL_MATCH_VALUE_INIT - - /* Wave polarity defaults */ -# define _TCC_CHANNEL_WAVE_POLARITY_INIT(n, value) \ - config->compare.wave_polarity[n] = value; - MREPEAT(TCC_NUM_CHANNELS, - _TCC_CHANNEL_WAVE_POLARITY_INIT, TCC_WAVE_POLARITY_0) -# undef _TCC_CHANNEL_WAVE_POLARITY_INIT - - config->compare.wave_generation = TCC_WAVE_GENERATION_NORMAL_FREQ; - config->compare.wave_ramp = TCC_RAMP_RAMP1; - -# define _TCC_CHANNEL_FUNCTION_INIT(n, value) \ - config->compare.channel_function[n] = value; - MREPEAT(TCC_NUM_CHANNELS, - _TCC_CHANNEL_FUNCTION_INIT, TCC_CHANNEL_FUNCTION_COMPARE) -# undef _TCC_CHANNEL_FUNCTION_INIT - - /* Recoverable fault defaults */ -# define _TCC_FAULT_FUNCTION_INIT(n, dummy) \ - config->wave_ext.recoverable_fault[n].filter_value = 0; \ - config->wave_ext.recoverable_fault[n].blanking_cycles = 0; \ - config->wave_ext.recoverable_fault[n].restart = false; \ - config->wave_ext.recoverable_fault[n].keep = false; \ - config->wave_ext.recoverable_fault[n].qualification = false; \ - config->wave_ext.recoverable_fault[n].source = TCC_FAULT_SOURCE_DISABLE; \ - config->wave_ext.recoverable_fault[n].blanking = TCC_FAULT_BLANKING_DISABLE; \ - config->wave_ext.recoverable_fault[n].halt_action = TCC_FAULT_HALT_ACTION_DISABLE; \ - config->wave_ext.recoverable_fault[n].capture_action = TCC_FAULT_CAPTURE_DISABLE; \ - config->wave_ext.recoverable_fault[n].capture_channel = TCC_FAULT_CAPTURE_CHANNEL_0; - MREPEAT(TCC_NUM_FAULTS, _TCC_FAULT_FUNCTION_INIT, 0) -# undef _TCC_FAULT_FUNCTION_INIT - - /* Non-recoverable fault defaults */ -# define _TCC_NRF_FUNCTION_INIT(n, dummy) \ - config->wave_ext.non_recoverable_fault[n].filter_value = 0; \ - config->wave_ext.non_recoverable_fault[n].output = TCC_FAULT_STATE_OUTPUT_OFF; - MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_NRF_FUNCTION_INIT, 0) -# undef _TCC_NRF_FUNCTION_INIT - - /* Output inversion defaults */ -# define _TCC_OUT_INVERT_INIT(n, value) \ - config->wave_ext.invert[n] = value; - MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_OUT_INVERT_INIT, false) -# undef _TCC_OUT_INVERT_INIT - -# define _TCC_CHANNEL_OUT_PIN_INIT(n, dummy) \ - config->pins.enable_wave_out_pin[n] = false;\ - config->pins.wave_out_pin[TCC_WAVE_OUTPUT_##n] = 0; \ - config->pins.wave_out_pin_mux[TCC_WAVE_OUTPUT_##n] = 0; - MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_CHANNEL_OUT_PIN_INIT, 0) -# undef _TCC_CHANNEL_OUT_PIN_INIT - - config->double_buffering_enabled = true; - config->run_in_standby = false; -} - - -/** - * \brief Build CTRLA register value from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built value - * - * \return Configuration validation status. - * - * \retval STATUS_OK Configuration values are good and register - * value built and save to buffer - * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: - * assigned dither mode is invalid for module; - * used capture channel is invalid for module - */ -static inline enum status_code _tcc_build_ctrla( - const uint8_t module_index, - const struct tcc_config *const config, - uint32_t *value_buffer) -{ - uint32_t ctrla = 0; - - int i; - for (i = 0; i < TCC_NUM_CHANNELS; i ++) { - if (config->capture.channel_function[i] == - TCC_CHANNEL_FUNCTION_CAPTURE) { - - if (i > _tcc_cc_nums[module_index]) { - /* Channel not supported */ - return STATUS_ERR_INVALID_ARG; - } - ctrla |= (TCC_CTRLA_CPTEN0 << i); - } - } - - if (config->run_in_standby) { - ctrla |= TCC_CTRLA_RUNSTDBY; - } - ctrla |= config->counter.reload_action << TCC_CTRLA_PRESCSYNC_Pos; - ctrla |= config->counter.clock_prescaler << TCC_CTRLA_PRESCALER_Pos; - - *value_buffer = ctrla; - return STATUS_OK; -} - -/** - * \brief Build CTRLB register value from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built value - */ -static inline void _tcc_build_ctrlb( - const uint8_t module_index, - const struct tcc_config *const config, - uint8_t *value_buffer) -{ - uint8_t ctrlb = 0; - - if (config->counter.oneshot) { - ctrlb |= TCC_CTRLBSET_ONESHOT; - } - if (config->counter.direction == TCC_COUNT_DIRECTION_DOWN) { - ctrlb |= TCC_CTRLBSET_DIR; - } - - *value_buffer = ctrlb; -} - -/** - * \brief Build FAULTs register values from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built values - * - * \retval STATUS_OK Configuration values are good and register - * value built and save to buffer - * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned fault - * capture channel is invalid; assigned filter - * value is invalid - */ -static inline enum status_code _tcc_build_faults( - const uint8_t module_index, - const struct tcc_config *const config, - uint32_t *value_buffer) -{ - struct tcc_recoverable_fault_config *cfg; - uint8_t cc_num = _tcc_cc_nums[module_index]; - uint32_t fault; - int i; - for (i = 0; i < TCC_NUM_FAULTS; i ++) { - cfg = (struct tcc_recoverable_fault_config *) - &config->wave_ext.recoverable_fault[i]; - if (cfg->capture_channel >= cc_num) { - return STATUS_ERR_INVALID_ARG; - } - if (cfg->filter_value > 0xF) { - return STATUS_ERR_INVALID_ARG; - } - fault = TCC_FCTRLA_FILTERVAL(cfg->filter_value) - | TCC_FCTRLA_BLANKVAL(cfg->blanking_cycles) - | (cfg->restart ? TCC_FCTRLA_RESTART : 0) - | (cfg->keep ? TCC_FCTRLA_KEEP : 0) - | (cfg->qualification ? TCC_FCTRLA_QUAL : 0) - | TCC_FCTRLA_SRC(cfg->source) - | TCC_FCTRLA_BLANK(cfg->blanking) - | TCC_FCTRLA_HALT(cfg->halt_action) - | TCC_FCTRLA_CAPTURE(cfg->capture_action) - | TCC_FCTRLA_CHSEL(cfg->capture_channel); - value_buffer[i] = fault; - } - return STATUS_OK; -} - -/** - * \brief Build DRVCTRL register values from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built value - * - * \retval STATUS_OK Configuration values are good and register - * value built and save to buffer - * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned output line - * is invalid; filter value is invalid - */ -static inline enum status_code _tcc_build_drvctrl( - const uint8_t module_index, - const struct tcc_config *const config, - uint32_t *value_buffer) -{ - uint32_t i; - uint8_t ow_num = _tcc_ow_nums[module_index]; - uint32_t drvctrl; - - drvctrl = 0; - - for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) { - if (config->wave_ext.invert[i]) { - if (i >= ow_num) { - return STATUS_ERR_INVALID_ARG; - } - drvctrl |= (TCC_DRVCTRL_INVEN0 << i); - } - if (config->wave_ext.non_recoverable_fault[i].output != - TCC_FAULT_STATE_OUTPUT_OFF) { - if (i >= ow_num) { - return STATUS_ERR_INVALID_ARG; - } - if (config->wave_ext.non_recoverable_fault[i].output == - TCC_FAULT_STATE_OUTPUT_1) { - drvctrl |= (TCC_DRVCTRL_NRE0 | TCC_DRVCTRL_NRV0) << i; - } else { - drvctrl |= (TCC_DRVCTRL_NRE0) << i; - } - } - } - *value_buffer = drvctrl; - return STATUS_OK; -} - -/** - * \brief Build WAVE & WAVEB register values from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built value - * - * \retval STATUS_OK Configuration values are good and register - * value built and save to buffer - * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned output line - * is invalid; circular and double buffering - * conflict; assigned function not supported by - * module - */ -static inline enum status_code _tcc_build_waves( - const uint8_t module_index, - const struct tcc_config *const config, - uint32_t *value_buffer) -{ - int n; - - uint8_t cc_num = _tcc_cc_nums[module_index]; - struct tcc_match_wave_config const *wav_cfg = &config->compare; - - uint32_t wave; - - wave = TCC_WAVE_RAMP(wav_cfg->wave_ramp) | - TCC_WAVE_WAVEGEN(wav_cfg->wave_generation); - - for (n = 0; n < TCC_NUM_CHANNELS; n++) { - if (wav_cfg->wave_polarity[n]) { - if (n >= cc_num) { - return STATUS_ERR_INVALID_ARG; - } - wave |= (TCC_WAVE_POL0 << n); - } - } - - value_buffer[0] = wave; - - return STATUS_OK; -} - -/** - * \brief Initializes a hardware TCC module instance. - * - * Enables the clock and initializes the given TCC module, based on the given - * configuration values. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] hw Pointer to the TCC hardware module - * \param[in] config Pointer to the TCC configuration options struct - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY Hardware module was busy when the - * initialization procedure was attempted - * \retval STATUS_INVALID_ARG An invalid configuration option or argument - * was supplied - * \retval STATUS_ERR_DENIED Hardware module was already enabled - */ -enum status_code tcc_init( - struct tcc_module *const module_inst, - Tcc *const hw, - const struct tcc_config *const config) -{ - int i; - - /* Sanity check arguments */ - Assert(hw); - Assert(module_inst); - Assert(config); - - /* TCC instance index */ - uint8_t module_index = _tcc_get_inst_index(hw); - - /* Enable the user interface clock for TCC */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - _tcc_apbcmasks[module_index]); - - /* Check if it's enabled. */ - if (hw->CTRLA.reg & TCC_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - /* Check if it's resetting */ - if (hw->CTRLA.reg & TCC_CTRLA_SWRST) { - return STATUS_ERR_DENIED; - } - - enum status_code status; - - /* Check COUNT, PER, CCx */ - uint32_t count_max = _tcc_maxs[module_index]; - - /* Check all counter values */ - if ((config->counter.count > count_max) - || (config->counter.period > count_max) - ) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check all channel values */ - for (i = 0; i < TCC_NUM_CHANNELS; i ++) { - if ((config->compare.match[i] > count_max) - ) { - return STATUS_ERR_INVALID_ARG; - } - } - - /* Check all outputs */ - for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) { - if (!config->pins.enable_wave_out_pin[i]) { - continue; - } - /* Output line is not supported */ - if (i >= _tcc_ow_nums[module_index]) { - return STATUS_ERR_INVALID_ARG; - } - } - - /* CTRLA settings */ - uint32_t ctrla = 0; - status = _tcc_build_ctrla(module_index, config, &ctrla); - if (STATUS_OK != status) { - return status; - } - - /* CTRLB settings */ - uint8_t ctrlb; - _tcc_build_ctrlb(module_index, config, &ctrlb); - - /* FAULTs settings */ - uint32_t faults[TCC_NUM_FAULTS]; - - status = _tcc_build_faults(module_index, config, faults); - if (STATUS_OK != status) { - return status; - } - - /* DRVCTRL */ - uint32_t drvctrl = 0; - - status = _tcc_build_drvctrl(module_index, config, &drvctrl); - if (STATUS_OK != status) { - return status; - } - - /* WAVE */ - uint32_t waves[1]; - - status = _tcc_build_waves(module_index, config, waves); - if (STATUS_OK != status) { - return status; - } - - /* Initialize module */ -#if TCC_ASYNC - /* Initialize parameters */ - for (i = 0; i < TCC_CALLBACK_N; i ++) { - module_inst->callback[i] = NULL; - } - module_inst->register_callback_mask = 0; - module_inst->enable_callback_mask = 0; - _tcc_instances[module_index] = module_inst; -#endif - - module_inst->hw = hw; - - module_inst->double_buffering_enabled = config->double_buffering_enabled; - - /* Setup clock for module */ - struct system_gclk_chan_config gclk_chan_config; - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = config->counter.clock_source; - system_gclk_chan_set_config(_tcc_gclk_ids[module_index], &gclk_chan_config); - system_gclk_chan_enable(_tcc_gclk_ids[module_index]); - - /* Initialize pins */ - struct system_pinmux_config pin_config; - for (i = 0; i < _tcc_ow_nums[module_index]; i ++) { - if (!config->pins.enable_wave_out_pin[i]) { - continue; - } - - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pins.wave_out_pin_mux[i]; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pins.wave_out_pin[i], &pin_config); - } - - /* Write to registers */ - - hw->CTRLA.reg = ctrla; - while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - - hw->CTRLBCLR.reg = 0xFF; - while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - hw->CTRLBSET.reg = ctrlb; - - hw->FCTRLA.reg = faults[0]; - hw->FCTRLB.reg = faults[1]; - - hw->DRVCTRL.reg = drvctrl; - -#if (!SAML21) && (!SAMC20) && (!SAMC21) - while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_WAVE | TCC_SYNCBUSY_WAVEB)) { - /* Wait for sync */ - } -#endif - hw->WAVE.reg = waves[0]; - - while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) { - /* Wait for sync */ - } - hw->COUNT.reg = config->counter.count; - -#if (!SAML21) && (!SAMC20) && (!SAMC21) - while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_PER | TCC_SYNCBUSY_PERB)) { - /* Wait for sync */ - } -#endif - hw->PER.reg = (config->counter.period); - - for (i = 0; i < _tcc_cc_nums[module_index]; i ++) { -#if (!SAML21) && (!SAMC20) && (!SAMC21) - while (hw->SYNCBUSY.reg & ( - (TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CCB0) << i)) { - /* Wait for sync */ - } -#endif - hw->CC[i].reg = (config->compare.match[i]); - } - - return STATUS_OK; -} - - -/** - * \brief Enables the TCC module event input or output. - * - * Enables one or more input or output events to or from the TCC module. - * See \ref tcc_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] events Struct containing flags of events to enable or - * configure - * - * \return Status of the events setup procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_INVALID_ARG An invalid configuration option or argument - * was supplied - */ -enum status_code tcc_enable_events( - struct tcc_module *const module_inst, - struct tcc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Tcc *const tcc_module = module_inst->hw; - - /* Check if it's enabled or resetting. */ - if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) { - return STATUS_ERR_DENIED; - } - - uint32_t evctrl = tcc_module->EVCTRL.reg; - - /* Setup event output action */ - if (events->output_config.modify_generation_selection) { - evctrl &= ~ TCC_EVCTRL_CNTSEL_Msk; - switch(events->output_config.generation_selection) { - case TCC_EVENT_GENERATION_SELECTION_START: - evctrl |= TCC_EVCTRL_CNTSEL_START; - break; - case TCC_EVENT_GENERATION_SELECTION_END: - evctrl |= TCC_EVCTRL_CNTSEL_END; - break; - case TCC_EVENT_GENERATION_SELECTION_BETWEEN: - evctrl |= TCC_EVCTRL_CNTSEL_BETWEEN; - break; - case TCC_EVENT_GENERATION_SELECTION_BOUNDARY: - evctrl |= TCC_EVCTRL_CNTSEL_BOUNDARY; - break; - default: - Assert(false); - /* Wrong configuration */ - return STATUS_ERR_INVALID_ARG; - } - } - /* Setup input event0 */ - if (events->on_input_event_perform_action[0]) { - evctrl |= TCC_EVCTRL_TCEI0; - } - if (events->input_config[0].invert) { - evctrl |= TCC_EVCTRL_TCINV0; - } - if (events->input_config[0].modify_action) { - evctrl &= ~ TCC_EVCTRL_EVACT0_Msk; - switch(events->input_config[0].action) { - case TCC_EVENT0_ACTION_OFF: - evctrl |= TCC_EVCTRL_EVACT0_OFF; - break; - case TCC_EVENT0_ACTION_RETRIGGER: - evctrl |= TCC_EVCTRL_EVACT0_RETRIGGER; - break; - case TCC_EVENT0_ACTION_COUNT_EVENT: - evctrl |= TCC_EVCTRL_EVACT0_COUNTEV; - break; - case TCC_EVENT0_ACTION_START: - evctrl |= TCC_EVCTRL_EVACT0_START; - break; - case TCC_EVENT0_ACTION_INCREMENT: - evctrl |= TCC_EVCTRL_EVACT0_INC; - break; - case TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE: - evctrl |= TCC_EVCTRL_EVACT0_COUNT; - break; - case TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT: - evctrl |= TCC_EVCTRL_EVACT0_FAULT; - break; - default: - Assert(false); - /* Wrong configuration */ - return STATUS_ERR_INVALID_ARG; - } - } - /* Setup input event1 */ - if (events->on_input_event_perform_action[1]) { - evctrl |= TCC_EVCTRL_TCEI1; - } - if (events->input_config[1].invert) { - evctrl |= TCC_EVCTRL_TCINV1; - } - if (events->input_config[1].modify_action) { - evctrl &= ~ TCC_EVCTRL_EVACT1_Msk; - switch(events->input_config[1].action) { - case TCC_EVENT1_ACTION_OFF: - evctrl |= TCC_EVCTRL_EVACT1_OFF; - break; - case TCC_EVENT1_ACTION_RETRIGGER: - evctrl |= TCC_EVCTRL_EVACT1_RETRIGGER; - break; - case TCC_EVENT1_ACTION_DIR_CONTROL: - evctrl |= TCC_EVCTRL_EVACT1_DIR; - break; - case TCC_EVENT1_ACTION_STOP: - evctrl |= TCC_EVCTRL_EVACT1_STOP; - break; - case TCC_EVENT1_ACTION_DECREMENT: - evctrl |= TCC_EVCTRL_EVACT1_DEC; - break; - case TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE: - evctrl |= TCC_EVCTRL_EVACT1_PPW | - TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1; - break; - case TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE: - evctrl |= TCC_EVCTRL_EVACT1_PWP | - TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1; - break; - case TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT: - evctrl |= TCC_EVCTRL_EVACT1_FAULT; - break; - default: - Assert(false); - /* Wrong configuration */ - return STATUS_ERR_INVALID_ARG; - } - } - uint32_t ch; - for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) { - if (events->generate_event_on_channel[ch]) { - evctrl |= (TCC_EVCTRL_MCEO(1) << ch); - } - if (events->on_event_perform_channel_action[ch]) { - evctrl |= (TCC_EVCTRL_MCEI(1) << ch); - } - } - if (events->generate_event_on_counter_overflow) { - evctrl |= TCC_EVCTRL_OVFEO; - } - if (events->generate_event_on_counter_retrigger) { - evctrl |= TCC_EVCTRL_TRGEO; - } - if (events->generate_event_on_counter_event) { - evctrl |= TCC_EVCTRL_CNTEO; - } - - tcc_module->EVCTRL.reg = evctrl; - - return STATUS_OK; -} - -/** - * \brief Disables the event input or output of a TCC instance. - * - * Disables one or more input or output events for the given TCC module. - * See \ref tcc_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] events Struct containing flags of events to disable - */ -void tcc_disable_events( - struct tcc_module *const module_inst, - struct tcc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Tcc *const tcc_module = module_inst->hw; - - /* Check if it's enabled or resetting. */ - if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) { - return; - } - - - uint32_t evctrl = 0; - uint32_t ch; - for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) { - if (events->generate_event_on_channel[ch]) { - evctrl |= (TCC_EVCTRL_MCEO(1) << ch); - } - if (events->on_event_perform_channel_action[ch]) { - evctrl |= (TCC_EVCTRL_MCEI(1) << ch); - } - } - if (events->generate_event_on_counter_overflow) { - evctrl |= TCC_EVCTRL_OVFEO; - } - if (events->generate_event_on_counter_retrigger) { - evctrl |= TCC_EVCTRL_TRGEO; - } - if (events->generate_event_on_counter_event) { - evctrl |= TCC_EVCTRL_CNTEO; - } - if (events->on_input_event_perform_action[0]) { - evctrl |= TCC_EVCTRL_TCEI0; - } - if (events->on_input_event_perform_action[1]) { - evctrl |= TCC_EVCTRL_TCEI1; - } - if (events->input_config[0].invert) { - evctrl |= TCC_EVCTRL_TCINV0; - } - if (events->input_config[1].invert) { - evctrl |= TCC_EVCTRL_TCINV1; - } - - tcc_module->EVCTRL.reg &= ~evctrl; -} - - - -/** - * \brief Sets count value for the given TCC module. - * - * Sets the timer count value of an initialized TCC module. The - * specified TCC module can remain running or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] count New timer count value to set - * - * \return Status which indicates whether the new value is set. - * - * \retval STATUS_OK The timer count was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified - */ -enum status_code tcc_set_count_value( - const struct tcc_module *const module_inst, - const uint32_t count) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance*/ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - uint32_t max_count = _tcc_maxs[module_index]; - - if (count > max_count) { - return STATUS_ERR_INVALID_ARG; - } - - while (tcc_module->SYNCBUSY.bit.COUNT) { - /* Wait for sync */ - } - - /* Write to based on the TCC dithering */ - tcc_module->COUNT.reg = (count); - - return STATUS_OK; -} - -/** - * \brief Get count value of the given TCC module. - * - * Retrieves the current count value of a TCC module. The specified TCC module - * can remain running or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Count value of the specified TCC module. - */ -uint32_t tcc_get_count_value( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance*/ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait last command done */ - do { - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; - if (TCC_CTRLBSET_CMD_NONE == last_cmd) { - /* Issue read command and break */ - tcc_module->CTRLBSET.bit.CMD = TCC_CTRLBSET_CMD_READSYNC_Val; - break; - } else if (TCC_CTRLBSET_CMD_READSYNC == last_cmd) { - /* Command have been issued */ - break; - } - } while (1); - - while (tcc_module->SYNCBUSY.bit.COUNT) { - /* Wait for sync */ - } - return (tcc_module->COUNT.reg); -} - - - -/** - * \brief Gets the TCC module capture value. - * - * Retrieves the capture value in the indicated TCC module capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the Compare Capture channel to read - * - * \return Capture value stored in the specified timer channel. - */ -uint32_t tcc_get_capture_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Assert(channel_index < _tcc_cc_nums[_tcc_get_inst_index(module_inst->hw)]); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while(tcc_module->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << channel_index)) { - /* Sync wait */ - } - - return tcc_module->CC[channel_index].reg; -} - -/** - * \internal - * \brief Sets a TCC module compare value/buffer. - * - * Writes a compare value to the given TCC module compare/capture channel or - * buffer one. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value/buffer value to set - * \param[in] double_buffering_enabled Set to \c true to write to CCBx - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * compare value exceed resolution - */ -static enum status_code _tcc_set_compare_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index, - const uint32_t compare, - const bool double_buffering_enabled) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - /* Check index */ - if (channel_index >= _tcc_cc_nums[module_index]) { - return STATUS_ERR_INVALID_ARG; - } - - uint32_t max_count = _tcc_maxs[module_index]; - - /* Check compare value */ - if (compare > max_count) { - return STATUS_ERR_INVALID_ARG; - } - - if (double_buffering_enabled) { -#if (SAML21) || (SAMC20) || (SAMC21) - tcc_module->CCBUF[channel_index].reg = compare; -#else - while(tcc_module->SYNCBUSY.reg & - (TCC_SYNCBUSY_CCB0 << channel_index)) { - /* Sync wait */ - } - tcc_module->CCB[channel_index].reg = compare; -#endif - } else { - while(tcc_module->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << channel_index)) { - /* Sync wait */ - } - tcc_module->CC[channel_index].reg = compare; - } - return STATUS_OK; -} - - -/** - * \brief Sets a TCC module compare value. - * - * Writes a compare value to the given TCC module compare/capture channel. - * - * If double buffering is enabled it always write to the buffer - * register. The value will then be updated immediately by calling - * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit - * is cleared and the UPDATE condition happen. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value to set - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * compare value exceed resolution - */ -enum status_code tcc_set_compare_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index, - const uint32_t compare) -{ - /* Sanity check arguments */ - Assert(module_inst); - - return _tcc_set_compare_value(module_inst, channel_index, compare, - module_inst->double_buffering_enabled); -} - -/** - * \brief Sets a TCC module compare value and buffer value. - * - * Writes compare value and buffer to the given TCC module compare/capture - * channel. Usually as preparation for double buffer or circulared double buffer - * (circular buffer). - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value to set - * \param[in] compare_buffer New compare buffer value to set - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * compare value exceed resolution - */ -enum status_code tcc_set_double_buffer_compare_values( - struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index, - const uint32_t compare, const uint32_t compare_buffer) -{ - /* Sanity check arguments */ - Assert(module_inst); - - enum status_code status; - status = _tcc_set_compare_value(module_inst, channel_index, compare, false); - if (status != STATUS_OK) { - return status; - } - return _tcc_set_compare_value(module_inst, channel_index, compare_buffer, - true); -} - - -/** - * \internal - * \brief Set the timer TOP/PERIOD buffer/value. - * - * This function writes the given value to the PER/PERB register. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New value to be loaded into the PER/PERB register - * \param[in] double_buffering_enabled Set to \c true to write to PERB - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * top/period value exceed resolution - */ -static enum status_code _tcc_set_top_value( - const struct tcc_module *const module_inst, - const uint32_t top_value, - const bool double_buffering_enabled) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - uint32_t max_count = _tcc_maxs[module_index]; - - /* Check compare value */ - if (top_value > max_count) { - return STATUS_ERR_INVALID_ARG; - } - - if (double_buffering_enabled) { -#if (SAML21) || (SAMC20) || (SAMC21) - tcc_module->PERBUF.reg = top_value; -#else - while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PERB) { - /* Sync wait */ - } - tcc_module->PERB.reg = top_value; -#endif - } else { - while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PER) { - /* Sync wait */ - } - tcc_module->PER.reg = top_value; - } - return STATUS_OK; -} - - -/** - * \brief Set the timer TOP/PERIOD value. - * - * This function writes the given value to the PER/PERB register. - * - * If double buffering is enabled it always write to the buffer - * register (PERB). The value will then be updated immediately by calling - * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit - * is cleared and the UPDATE condition happen. - * - * When using MFRQ, the top value is defined by the CC0 register value and the - * PER value is ignored, so - * \ref tcc_set_compare_value (module,channel_0,value) must be used instead of - * this function to change the actual top value in that case. - * For all other waveforms operation the top value is defined by PER register - * value. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New value to be loaded into the PER/PERB register - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * top/period value exceed resolution - */ -enum status_code tcc_set_top_value( - const struct tcc_module *const module_inst, - const uint32_t top_value) -{ - /* Sanity check arguments */ - Assert(module_inst); - - return _tcc_set_top_value(module_inst, top_value, - module_inst->double_buffering_enabled); -} - -/** - * \brief Set the timer TOP/PERIOD value and buffer value. - * - * This function writes the given value to the PER and PERB register. Usually as - * preparation for double buffer or circulared double buffer (circular buffer). - * - * When using MFRQ, the top values are defined by the CC0 and CCB0, the PER and - * PERB values are ignored, so - * \ref tcc_set_double_buffer_compare_values (module,channel_0,value,buffer) must - * be used instead of this function to change the actual top values in that - * case. For all other waveforms operation the top values are defined by PER and - * PERB registers values. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New value to be loaded into the PER register - * \param[in] top_buffer_value New value to be loaded into the PERB register - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * top/period value exceed resolution - */ -enum status_code tcc_set_double_buffer_top_values( - const struct tcc_module *const module_inst, - const uint32_t top_value, const uint32_t top_buffer_value) -{ - /* Sanity check arguments */ - Assert(module_inst); - - enum status_code status; - status = _tcc_set_top_value(module_inst, top_value, false); - if (status != STATUS_OK) { - return status; - } - return _tcc_set_top_value(module_inst, top_buffer_value, true); -} - - -/** - * \brief Sets the TCC module waveform output pattern. - * - * Force waveform output line to generate specific pattern (0, 1, or as is). - * - * If double buffering is enabled it always write to the buffer - * register. The value will then be updated immediately by calling - * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit - * is cleared and the UPDATE condition happen. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] line_index Output line index - * \param[in] pattern Output pattern to use (\ref tcc_output_pattern) - * - * \return Status of the pattern set procedure. - * - * \retval STATUS_OK The PATT register is updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid line index was supplied - */ -enum status_code tcc_set_pattern( - const struct tcc_module *const module_inst, - const uint32_t line_index, - const enum tcc_output_pattern pattern) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - /* Get number of output lines */ - uint8_t ow_num = _tcc_ow_nums[module_index]; - - /* Check if line number is OK */ - if (line_index >= ow_num) { - return STATUS_ERR_INVALID_ARG; - } - - uint32_t patt_value; - - while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) { - /* Sync wait */ - } - patt_value = tcc_module->PATT.reg; - if (TCC_OUTPUT_PATTERN_DISABLE == pattern) { - patt_value &= ~(TCC_PATT_PGE0 << line_index); - } else if (TCC_OUTPUT_PATTERN_0 == pattern) { - patt_value &= ~(TCC_PATT_PGV0 << line_index); - patt_value |= (TCC_PATT_PGE0 << line_index); - } else { - patt_value |= ((TCC_PATT_PGE0 | TCC_PATT_PGV0) << line_index); - } - - if (module_inst->double_buffering_enabled) { -#if (SAML21) || (SAMC20) || (SAMC21) - tcc_module->PATTBUF.reg = patt_value; -#else - while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PATTB) { - /* Sync wait */ - } - tcc_module->PATTB.reg = patt_value; -#endif - } else { - tcc_module->PATT.reg = patt_value; - } - return STATUS_OK; -} - -/** - * \brief Retrieves the current module status. - * - * Retrieves the status of the module, giving overall state information. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - * \return Bitmask of \c TCC_STATUS_* flags. - * - * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occured - * \retval TCC_STATUS_CHANNEL_OUTPUT(n) Channel n match/capture output state - * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occured - * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occured - * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) Non-recoverable fault x input present - * \retval TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) Recoverable fault n input present - * \retval TCC_STATUS_SYNC_READY None of register is syncing - * \retval TCC_STATUS_CAPTURE_OVERFLOW Timer capture data has overflowed - * \retval TCC_STATUS_COUNTER_EVENT Timer counter event has occurred - * \retval TCC_STATUS_COUNT_OVERFLOW Timer count value has overflowed - * \retval TCC_STATUS_COUNTER_RETRIGGERED Timer counter has been retriggered - * \retval TCC_STATUS_STOP Timer counter has been stopped - * \retval TCC_STATUS_RAMP_CYCLE_INDEX Wave ramp index for cycle - */ -uint32_t tcc_get_status( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint32_t int_flags = module_inst->hw->INTFLAG.reg; - uint32_t status_flags = module_inst->hw->STATUS.reg; - uint32_t status = 0; - int i; - - /* SYNC */ - if (module_inst->hw->SYNCBUSY.reg == 0) { - status |= TCC_STATUS_SYNC_READY; - } - - /* Channels */ - for (i = 0; i < TCC_NUM_CHANNELS; i++) { - if (int_flags & TCC_INTFLAG_MC(i)) { - status |= TCC_STATUS_CHANNEL_MATCH_CAPTURE(i); - } - if (status_flags & TCC_STATUS_CMP(i)) { - status |= TCC_STATUS_CHANNEL_OUTPUT(i); - } - } - /* Non-recoverable fault state */ - if ((int_flags & TCC_INTFLAG_FAULT1) || - (status_flags & TCC_STATUS_FAULT1)) { - status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1); - } - if ((int_flags & TCC_INTFLAG_FAULT0) || - (status_flags & TCC_STATUS_FAULT0)) { - status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0); - } - /* Non-recoverable fault inputs */ - if (status_flags & TCC_STATUS_FAULT0IN) { - status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(0); - } - if (status_flags & TCC_STATUS_FAULT1IN) { - status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(1); - } - /* Recoverable fault state */ - if ((int_flags & TCC_INTFLAG_FAULTB) || - (status_flags & TCC_STATUS_FAULTB)) { - status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1); - } - if ((int_flags & TCC_INTFLAG_FAULTA) || - (status_flags & TCC_STATUS_FAULTA)) { - status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0); - } - /* Recoverable fault inputs */ - if (status_flags & TCC_STATUS_FAULTAIN) { - status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(0); - } - if (status_flags & TCC_STATUS_FAULTBIN) { - status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(1); - } - - /* Check for TCC capture overflow */ - if (int_flags & TCC_INTFLAG_ERR) { - status |= TCC_STATUS_CAPTURE_OVERFLOW; - } - /* Check for TCC count counter */ - if (int_flags & TCC_INTFLAG_CNT) { - status |= TCC_STATUS_COUNTER_EVENT; - } - /* Check for TCC count retrigger */ - if (int_flags & TCC_INTFLAG_TRG) { - status |= TCC_STATUS_COUNTER_RETRIGGERED; - } - /* Check for TCC count overflow */ - if (int_flags & TCC_INTFLAG_OVF) { - status |= TCC_STATUS_COUNT_OVERFLOW; - } - /* Check for TCC count stop */ - if (status_flags & TCC_STATUS_STOP) { - status |= TCC_STATUS_STOPPED; - } - return status; -} - -/** - * \brief Clears a module status flag. - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * \param[in] status_flags Bitmask of \c TCC_STATUS_* flags to clear - */ -void tcc_clear_status( - struct tcc_module *const module_inst, - const uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint32_t int_clr = 0; - uint32_t status_clr = 0; - int i; - - /* Channels */ - for (i = 0; i < TCC_NUM_CHANNELS; i++) { - if (status_flags & TCC_STATUS_CHANNEL_MATCH_CAPTURE(i)) { - int_clr |= TCC_INTFLAG_MC(i); - } - } - /* Faults */ - if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1)) { - int_clr |= TCC_INTFLAG_FAULT1; - status_clr |= TCC_STATUS_FAULT1; - } - if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0)) { - int_clr |= TCC_INTFLAG_FAULT0; - status_clr |= TCC_STATUS_FAULT0; - } - if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1)) { - int_clr |= TCC_INTFLAG_FAULTB; - status_clr |= TCC_STATUS_FAULTB; - } - if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0)) { - int_clr |= TCC_INTFLAG_FAULTA; - status_clr |= TCC_STATUS_FAULTA; - } - /* Check for TCC capture overflow */ - if (status_flags & TCC_STATUS_CAPTURE_OVERFLOW) { - int_clr |= TCC_INTFLAG_ERR; - } - /* Check for TCC count counter */ - if (status_flags & TCC_STATUS_COUNTER_EVENT) { - int_clr |= TCC_INTFLAG_CNT; - } - /* Check for TCC count retrigger */ - if (status_flags & TCC_STATUS_COUNTER_RETRIGGERED) { - int_clr = TCC_INTFLAG_TRG; - } - /* Check for TCC count overflow */ - if (status_flags & TCC_STATUS_COUNT_OVERFLOW) { - int_clr |= TCC_INTFLAG_OVF; - } - /* Clear status flag */ - module_inst->hw->STATUS.reg = status_clr; - /* Clear interrupt flag */ - module_inst->hw->INTFLAG.reg = int_clr; -} - -/** - * \brief Enable circular option for double buffered compare values. - * - * Enable circular option for the double buffered channel compare values. - * On each UPDATE condition, the contents of CCBx and CCx are switched, meaning - * that the contents of CCBx are transferred to CCx and the contents of CCx are - * transferred to CCBx. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * \param[in] channel_index Index of the compare channel to set up to - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_INVALID_ARG An invalid channel index is supplied - */ -enum status_code tcc_enable_circular_buffer_compare( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - /* Check index */ - if (channel_index > 3) { - return STATUS_ERR_INVALID_ARG; - } - if (channel_index >= _tcc_cc_nums[module_index]) { - return STATUS_ERR_INVALID_ARG; - } - - tcc_module->WAVE.reg |= (TCC_WAVE_CICCEN0 << channel_index); - - return STATUS_OK; -} - -/** - * \brief Disable circular option for double buffered compare values. - * - * Stop circularing the double buffered compare values. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * \param[in] channel_index Index of the compare channel to set up to - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_INVALID_ARG An invalid channel index is supplied - */ -enum status_code tcc_disable_circular_buffer_compare( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - /* Check index */ - if (channel_index > 3) { - return STATUS_ERR_INVALID_ARG; - } - if (channel_index >= _tcc_cc_nums[module_index]) { - return STATUS_ERR_INVALID_ARG; - } - - tcc_module->WAVE.reg &= ~(TCC_WAVE_CICCEN0 << channel_index); - - return STATUS_OK; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h deleted file mode 100644 index ec409a340dc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h +++ /dev/null @@ -1,2456 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - Timer Counter for Control Applications Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef TCC_H_INCLUDED -#define TCC_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_tcc_group SAM Timer Counter for Control Applications Driver (TCC) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of the TCC module within the device, for waveform - * generation and timing operations. It also provides extended options for - * control applications. - * - * The following driver API modes are covered - * by this manual: - * - * - Polled APIs - * \if TCC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripherals are used by this module: - * - TCC (Timer/Counter for Control Applications) - * - * The following devices can use this module: - * - Atmel | SMART SAM D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM DAx - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_tcc_prerequisites - * - \ref asfdoc_sam0_tcc_module_overview - * - \ref asfdoc_sam0_tcc_special_considerations - * - \ref asfdoc_sam0_tcc_extra_info - * - \ref asfdoc_sam0_tcc_examples - * - \ref asfdoc_sam0_tcc_api_overview - * - * \section asfdoc_sam0_tcc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * \section asfdoc_sam0_tcc_module_overview Module Overview - * - * The Timer/Counter for Control Applications (TCC) module provides a set of - * timing and counting related functionality, such as the generation of periodic - * waveforms, the capturing of a periodic waveform's frequency/duty cycle, - * software timekeeping for periodic operations, waveform extension control, - * fault detection etc. - * - * The counter size of the TCC modules can be 16- or 24-bit depending on - * the TCC instance. - * Refer \ref asfdoc_sam0_tcc_special_considerations_tcc_d21 and - * \ref asfdoc_sam0_tcc_special_considerations_tcc_d11 for details on TCC instances. - * - * The TCC module for the SAM includes the following functions: - * - * - Generation of PWM signals - * - Generation of timestamps for events - * - General time counting - * - Waveform period capture - * - Waveform frequency capture - * - Additional control for generated waveform outputs - * - Fault protection for waveform generation - * - * \ref asfdoc_sam0_tcc_block_diagram "The diagram below" shows the overview - * of the TCC Module. - * - * \anchor asfdoc_sam0_tcc_block_diagram - * \image html overview.svg "Overview of the TCC Module" - * - * \subsection asfdoc_sam0_tcc_module_overview_parts Functional Description - * The TCC module consists of following sections: - * - Base Counter - * - Compare/Capture channels, with waveform generation - * - Waveform extension control and fault detection - * - Interface to the event system, DMAC, and the interrupt system - * - * The base counter can be configured to either count a prescaled generic - * clock or events from the event system.(TCEx, with event action configured - * to counting). - * The counter value can be used by compare/capture channels which can be - * set up either in compare mode or capture mode. - * - * In capture mode, the counter value is stored when a configurable event - * occurs. This mode can be used to generate timestamps used in event capture, - * or it can be used for the measurement of a periodic input signal's - * frequency/duty cycle. - * - * In compare mode, the counter value is compared against one or more of the - * configured channels' compare values. When the counter value coincides with a - * compare value an action can be taken automatically by the module, such as - * generating an output event or toggling a pin when used for frequency or PWM - * signal generation. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * In compare mode, when output signal is generated, extended waveform controls - * are available, to arrange the compare outputs into specific formats. - * The Output matrix can change the channel output routing. Pattern generation - * unit can overwrite the output signal line to specific state. - * The Fault protection feature of the TCC supports recoverable and - * non-recoverable faults. - * - * \subsection asfdoc_sam0_tcc_module_overview_tc Base Timer/Counter - * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_size Timer/Counter Size - * Each TCC has a counter size of either 16- or 24-bits. The size of the - * counter determines the maximum value it can count to before an overflow - * occurs. - * \ref asfdoc_sam0_tcc_count_size_vs_top "The table below" shows the - * maximum values for each of the possible counter sizes. - * - * \anchor asfdoc_sam0_tcc_count_size_vs_top - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Timer Counter Sizes and Their Maximum Count Values
Counter sizeMax. (hexadecimal)Max. (decimal)
16-bit0xFFFF65,535
24-bit0xFFFFFF16,777,215
- * - * The period/top value of the counter can be set, to define counting period. - * This will allow the counter to overflow when the counter value reaches the - * period/top value. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_clk Timer/Counter Clock and Prescaler - * TCC is clocked asynchronously to the system clock by a GCLK - * (Generic Clock) channel. The GCLK channel can be connected to any of the GCLK - * generators. The GCLK generators are configured to use one of the available - * clock sources in the system such as internal oscillator, external crystals, - * etc. - see the \ref asfdoc_sam0_system_clock_group "Generic Clock driver" for - * more information. - * - * Each TCC module in the SAM has its own individual clock prescaler, which - * can be used to divide the input clock frequency used by the counter. This - * prescaler only scales the clock used to provide clock pulses for the counter - * to count, and does not affect the digital register interface portion of - * the module, thus the timer registers will synchronized to the raw GCLK - * frequency input to the module. - * - * As a result of this, when selecting a GCLK frequency and timer prescaler - * value the user application should consider both the timer resolution - * required and the synchronization frequency, to avoid lengthy - * synchronization times of the module if a very slow GCLK frequency is fed - * into the TCC module. It is preferable to use a higher module GCLK frequency - * as the input to the timer and prescale this down as much as possible to - * obtain a suitable counter frequency in latency-sensitive applications. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_ctrl Timer/Counter Control Inputs (Events) - * - * The TCC can take several actions on the occurrence of an input event. - * The event actions are listed - * in \ref asfdoc_sam0_tcc_module_event_act "events action settings". - * - * \anchor asfdoc_sam0_tcc_module_event_act - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Event Actions
Event actionDescriptionApplied event
TCC_EVENT_ACTION_OFFNo action on the event inputAll
TCC_EVENT_ACTION_RETRIGGERRe-trigger Counter on eventAll
TCC_EVENT_ACTION_NON_RECOVERABLE_FAULTGenerate Non-Recoverable Fault on eventAll
TCC_EVENT_ACTION_STARTCounter start on eventEV0
TCC_EVENT_ACTION_DIR_CONTROLCounter direction controlEV0
TCC_EVENT_ACTION_DECREMENTCounter decrement on eventEV0
TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURECapture pulse period and pulse widthEV0
TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURECapture pulse width and pulse periodEV0
TCC_EVENT_ACTION_STOPCounter stop on eventEV1
TCC_EVENT_ACTION_COUNT_EVENTCounter count on eventEV1
TCC_EVENT_ACTION_INCREMENTCounter increment on eventEV1
TCC_EVENT_ACTION_COUNT_DURING_ACTIVECounter count during active state of asynchronous eventEV1
- * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_reload Timer/Counter Reloading - * - * The TCC also has a configurable reload action, used when a - * re-trigger event occurs. Examples of a re-trigger event could be the counter - * reaching the maximum value when counting up, or when an event from the event - * system makes the counter to re-trigger. The reload action determines if the - * prescaler should be reset, and on which clock. The counter will - * always be reloaded with the value it is set to start counting. The user - * can choose between three different reload actions, described in - * \ref asfdoc_sam0_tcc_module_reload_act "the table below". - * - * \anchor asfdoc_sam0_tcc_module_reload_act - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Reload Actions
Reload actionDescription
TCC_RELOAD_ACTION_GCLKReload TCC counter value on next GCLK cycle. Leave prescaler - * as-is.
TCC_RELOAD_ACTION_PRESCReloads TCC counter value on next prescaler clock. Leave prescaler - * as-is.
TCC_RELOAD_ACTION_RESYNCReload TCC counter value on next GCLK cycle. Clear prescaler to - * zero.
- * - * The reload action to use will depend on the specific application being - * implemented. One example is when an external trigger for a reload occurs; if - * the TCC uses the prescaler, the counter in the prescaler should not have a - * value between zero and the division factor. The counter in the TCC module - * and the counter in the prescaler should both start at zero. - * If the counter is set to re-trigger when it reaches the maximum value, - * this is not the right option to use. In such a case it would be better if - * the prescaler is left unaltered when the re-trigger happens, letting the - * counter reset on the next GCLK cycle. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_oneshot One-shot Mode - * - * The TCC module can be configured in one-shot mode. When configured in this - * manner, starting the timer will cause it to count until the next overflow - * or underflow condition before automatically halting, waiting to be manually - * triggered by the user application software or an event from the event - * system. - * - * \subsection asfdoc_sam0_tcc_module_overview_capt Capture Operations - * - * In capture operations, any event from the event system or a pin change can - * trigger a capture of the counter value. This captured counter value can be - * used as timestamps for the events, or it can be used in frequency and pulse - * width capture. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_capt_ev Capture Operations - Event - * - * Event capture is a simple use of the capture functionality, - * designed to create timestamps for specific events. When the input event - * appears, the current counter value is copied into the corresponding - * compare/capture register, which can then be read by the user application. - * - * Note that when performing any capture operation, there is a risk that the - * counter reaches its top value (MAX) when counting up, or the bottom value - * (zero) when counting down, before the capture event occurs. This can distort - * the result, making event timestamps to appear shorter than they really are. - * In this case, the user application should check for timer overflow when - * reading a capture result in order to detect this situation and perform an - * appropriate adjustment. - * - * Before checking for a new capture, \ref TCC_STATUS_COUNT_OVERFLOW - * should be checked. The response to an overflow error is left to the user - * application, however it may be necessary to clear both the overflow - * flag and the capture flag upon each capture reading. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_capt_pulse Capture Operations - Pulse Width - * - * Pulse Width Capture mode makes it possible to measure the pulse width and - * period of PWM signals. This mode uses two capture channels of the counter. - * There are two modes for pulse width capture; - * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture - * channel 0 is used for storing the pulse width and capture channel 1 stores - * the observed period. While in PPW mode, the roles of the two capture channels - * are reversed. - * - * As in the above example it is necessary to poll on interrupt flags to see - * if a new capture has happened and check that a capture overflow error has - * not occurred. - * - * Refer to \ref asfdoc_sam0_tcc_module_overview_tc_ctrl to set up the input - * event to perform pulse width capture. - * - * \subsection asfdoc_sam0_tcc_module_overview_mc Compare Match Operation - * - * In compare match operation, Compare/Capture registers are compared - * with the counter value. When the timer's count value matches the value of a - * compare channel, a user defined action can be taken. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_mc_timer Basic Timer - * - * A Basic Timer is a simple application where compare match operation is used - * to determine when a specific period has elapsed. In Basic Timer operations, - * one or more values in the module's Compare/Capture registers are used to - * specify the time (in terms of the number of prescaled GCLK cycles, or - * input events) at which - * an action should be taken by the microcontroller. This can be an Interrupt - * Service Routine (ISR), event generation via the event system, or a software - * flag that is polled from the user application. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave Waveform Generation - * - * Waveform generation enables the TCC module to generate square waves, or if - * combined with an external passive low-pass filter, analog waveforms. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave_pwm Waveform Generation - PWM - * - * Pulse width modulation is a form of waveform generation and a signalling - * technique that can be useful in many applications. When PWM mode is used, - * a digital pulse train with a configurable frequency and duty cycle can be - * generated by the TCC module and output to a GPIO pin of the device. - * - * Often PWM is used to communicate a control or information parameter to an - * external circuit or component. Differing impedances of the source generator - * and sink receiver circuits is less of an issue when using PWM compared to - * using an analog voltage value, as noise will not generally affect the - * signal's integrity to a meaningful extent. - * - * \ref asfdoc_sam0_tcc_module_pwm_single_diag "The figure below" illustrates - * operations and different states of the counter and its output when using - * the timer in Normal PWM mode (Single Slope). As can be seen, the TOP/PERIOD - * value is - * unchanged and is set to MAX. The compare match value is changed at several - * points to illustrate the resulting waveform output changes. The PWM output is - * set to normal (i.e. non-inverted) output mode. - * - * \anchor asfdoc_sam0_tcc_module_pwm_single_diag - * \image html pwm_single_ex.svg "Example Of PWM In Single-Slope Mode, and Different Counter Operations" - * - * Several PWM modes are supported by the TCC module, refer to - * datasheet for the details on PWM waveform generation. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave_freq Waveform Generation - Frequency - * - * Normal Frequency Generation is in many ways identical to PWM generation. - * However, only in Frequency Generation, a toggle occurs on the output when a - * match on a compare channels occurs. - * - * When the Match Frequency Generation is used, the timer value is reset on - * match condition, resulting in a variable frequency square wave with a - * fixed 50% duty cycle. - * - * \subsection asfdoc_sam0_tcc_module_overview_ext Waveform Extended Controls - * - * \subsubsection asfdoc_sam0_tcc_module_overview_ext_pat Pattern Generation - * - * Pattern insertion allows the TCC module to change the actual pin output level - * without modifying the compare/match settings. - * - * \anchor asfdoc_sam0_tcc_module_pattern_gen - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Output Pattern Generation
PatternDescription
TCC_OUTPUT_PATTERN_DISABLEPattern disabled, generate output as is
TCC_OUTPUT_PATTERN_0Generate pattern 0 on output (keep the output LOW)
TCC_OUTPUT_PATTERN_1Generate pattern 1 on output (keep the output HIGH)
- * - * \subsubsection asfdoc_sam0_tcc_module_overview_ext_r_fault Recoverable Faults - * - * The recoverable faults can trigger one or several of following fault actions: - * -# *Halt* action: The recoverable faults can halt the TCC timer/counter, - * so that the final output wave is kept at a defined state. When the fault - * state is removed it is possible to recover the counter and waveform - * generation. The halt action is defined as: - * \anchor asfdoc_sam0_tcc_module_fault_halt_action - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Recoverable Fault Halt Actions
ActionDescription
TCC_FAULT_HALT_ACTION_DISABLEHalt action is disabled
TCC_FAULT_HALT_ACTION_HW_HALTThe timer/counter is halted as long as the corresponding fault is - * present
TCC_FAULT_HALT_ACTION_SW_HALTThe timer/counter is halted until the corresponding fault is removed - * and fault state cleared by software
TCC_FAULT_HALT_ACTION_NON_RECOVERABLEForce all the TCC output pins to a pre-defined level, as what - * Non-Recoverable Fault do
- * -# *Restart* action: When enabled, the recoverable faults can restart the TCC - * timer/counter. - * -# *Keep* action: When enabled, the recoverable faults can keep the - * corresponding channel output to zero when the fault condition is present. - * -# *Capture* action: When the recoverable fault occurs, the capture action can - * time stamps the corresponding fault. The following capture mode is - * supported: - * \anchor asfdoc_sam0_tcc_module_fault_capt_action - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Recoverable Fault Capture Actions
ActionDescription
TCC_FAULT_CAPTURE_DISABLECapture action is disabled
TCC_FAULT_CAPTURE_EACHEquivalent to standard capture operation, on each fault occurrence - * the time stamp is captured
TCC_FAULT_CAPTURE_MINIMUMGet the minimum time stamped value in all time stamps
TCC_FAULT_CAPTURE_MAXIMUMGet the maximum time stamped value in all time stamps
TCC_FAULT_CAPTURE_SMALLERTime stamp the fault input if the value is smaller than last one
TCC_FAULT_CAPTURE_BIGGERTime stamp the fault input if the value is bigger than last one
TCC_FAULT_CAPTURE_CHANGETime stamp the fault input if the time stamps changes its increment - * direction
- * - * In TCC module, only the first two compare channels (CC0 and CC1) can work - * with recoverable fault inputs. The corresponding event inputs (TCCx MC0 - * and TCCx MC1) are then used as fault inputs respectively. - * The faults are called Fault A and Fault B. - * - * The recoverable fault can be filtered or effected by corresponding channel - * output. On fault condition there are many other settings that can be chosen. - * Refer to data sheet for more details about the recoverable fault - * operations. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_ext_n_fault Non-Recoverable Faults - * - * The non-recoverable faults force all the TCC output pins to a pre-defined - * level (can be forced to 0 or 1). The input control signal of non-recoverable - * fault is from timer/counter event (TCCx EV0 and TCCx EV1). - * To enable non-recoverable fault, - * corresponding TCEx event action must be set to non-recoverable fault action - * (\ref TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT). - * Refer to \ref asfdoc_sam0_tcc_module_overview_tc_ctrl to see the available - * event input action. - * - * \subsection asfdoc_sam0_tcc_module_overview_buffering Double and Circular Buffering - * - * The pattern, period and the compare channels registers are double buffered. - * For these options there are effective registers (PATT, PER, and CCx) and - * buffer registers (PATTB, PERB, and CCx). When writing to the buffer - * registers, the values are buffered and will be committed to effective - * registers on UPDATE condition. - * - * Usually the buffered value is cleared after it's committed, but there is also - * option to circular the register buffers. The period (PER) and four lowest - * compare channels register (CCx, x is 0 ~ 3) support this function. When - * circular buffer is used, on UPDATE the previous period or compare values are - * copied back into the corresponding period buffer and compare buffers. - * This way, the register value and its buffer register value is actually - * switched on UPDATE condition, and will be switched back on next UPDATE - * condition. - * - * For input capture, the buffer register (CCBx) and the corresponding capture - * channel register (CCx) act like a FIFO. When regular register (CCx) is empty - * or read, any content in the buffer register is passed to regular one. - * - * In TCC module driver, when the double buffering write is enabled, any - * write through \ref tcc_set_top_value(), \ref tcc_set_compare_value(), and - * \ref tcc_set_pattern() will be done to the corresponding buffer register. - * Then the value in the buffer register will be transferred to the regular - * register on the next UPDATE condition or by a force UPDATE using - * \ref tcc_force_double_buffer_update(). - * - * \subsection asfdoc_sam0_tcc_module_overview_sleep Sleep Mode - * - * TCC modules can be configured to operate in any sleep mode, with its "run - * in standby" function enabled. It can wake up the device using interrupts or - * perform internal actions with the help of the Event System. - * - * \section asfdoc_sam0_tcc_special_considerations Special Considerations - * - * \subsection asfdoc_sam0_tcc_special_considerations_specific_features Driver Feature Macro Definition - * \ref asfdoc_sam0_tcc_feature_table "The table below" shows some specific features - * of the TCC Module. - * - * \anchor asfdoc_sam0_tcc_feature_table - * - * - * - * - * - * - * - * - * - * - *
TCC Module Specific Features
Driver Feature MacroSupported devices
FEATURE_TCC_GENERATE_DMA_TRIGGERSAML21
- * - * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_tcc_special_considerations_tcc_feature Module Features - * - * The features of TCC, such as timer/counter size, number of compare capture - * channels, and number of outputs, are dependent on the TCC module instance being - * used. - * - * \subsubsection asfdoc_sam0_tcc_special_considerations_tcc_d21 SAM TCC Feature List - * For SAM D21/R21/L21/DAx/C21, the TCC features are: - * \anchor asfdoc_sam0_tcc_features_d21 - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC module features for SAM D21/R21/L21/DAx/C21
TCC#Match/Capture channelsWave outputsCounter size [bits]FaultDitheringOutput matrixDead-Time insertionSWAPPattern
04824YYYYYY
12424YYY
22216Y
- * - * \subsubsection asfdoc_sam0_tcc_special_considerations_tcc_d11 SAM D10/D11 TCC Feature List - * For SAM D10/D11, the TCC features are: - * \anchor asfdoc_sam0_tcc_features_d11 - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Features For SAM D10/D11
TCC#Match/Capture channelsWave outputsCounter size [bits]FaultDitheringOutput matrixDead-Time insertionSWAPPattern
04824YYYYYY
- * - * \subsection asfdoc_sam0_tcc_special_considerations_tcc_pin Channels vs. Pin outs - * - * As the TCC module may have more waveform output pins than the number of - * compare/capture channels, the free pins (with number higher than number of - * channels) will reuse the waveform generated by channels subsequently. E.g., - * if the number of channels is four and the number of wave output pins is eight, channel - * 0 output will be available on out pin 0 and 4, channel 1 output - * on wave out pin 1 and 5, and so on. - * - * \section asfdoc_sam0_tcc_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_tcc_extra. This includes: - * - \ref asfdoc_sam0_tcc_extra_acronyms - * - \ref asfdoc_sam0_tcc_extra_dependencies - * - \ref asfdoc_sam0_tcc_extra_errata - * - \ref asfdoc_sam0_tcc_extra_history - * - * - * \section asfdoc_sam0_tcc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_tcc_exqsg. - * - * \section asfdoc_sam0_tcc_api_overview API Overview - * @{ - */ - -#include -#include -#include -#include - -/** Maximum number of channels supported by the driver - * (Channel index from 0 to \c TCC_NUM_CHANNELS - 1). - */ -#define TCC_NUM_CHANNELS 4 - -/** Maximum number of wave outputs lines supported by the driver - * (Output line index from 0 to \c TCC_NUM_WAVE_OUTPUTS - 1). - */ -#define TCC_NUM_WAVE_OUTPUTS 8 - -/** Maximum number of (recoverable) faults supported by the driver. */ -#define TCC_NUM_FAULTS 2 - -#if TCC_ASYNC == true -# include -#endif - -/** - * Define port features set according to different device family. - * @{ -*/ -#if (SAML21) || defined(__DOXYGEN__) -/** Generate DMA triggers. */ -# define FEATURE_TCC_GENERATE_DMA_TRIGGER -#endif -/*@}*/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Generates a table enum list entry for a given type - and index (e.g. "TCC_CALLBACK_MC_CHANNEL_0,"). */ -#define _TCC_ENUM(n, type) TCC_##type##_##n, - -/* Generates table enum list entries for all channels of a - given type and channel number on TCC module. */ -#define _TCC_CHANNEL_ENUM_LIST(type) \ - MREPEAT(TCC_NUM_CHANNELS, _TCC_ENUM, type##_CHANNEL) -/* Generates table enum list entries for all output of a - given type and waveform output number on TCC module. */ -#define _TCC_WO_ENUM_LIST(type) \ - MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_ENUM, type) - - -#if TCC_ASYNC == true -/** Enum for the possible callback types for the TCC module. */ -enum tcc_callback { - /** Callback for TCC overflow. */ - TCC_CALLBACK_OVERFLOW, - /** Callback for TCC Retrigger. */ - TCC_CALLBACK_RETRIGGER, - /** Callback for TCC counter event. */ - TCC_CALLBACK_COUNTER_EVENT, - /** Callback for capture overflow error. */ - TCC_CALLBACK_ERROR, - /** Callback for Recoverable Fault A. */ - TCC_CALLBACK_FAULTA, - /** Callback for Recoverable Fault B. */ - TCC_CALLBACK_FAULTB, - /** Callback for Non-Recoverable Fault 0. */ - TCC_CALLBACK_FAULT0, - /** Callback for Non-Recoverable Fault 1. */ - TCC_CALLBACK_FAULT1, - -# if defined(__DOXYGEN__) - /** Channel callback type table for TCC - * - * Each TCC module may contain several callback types for channels; each - * channel will have its own callback type in the table, with the channel - * index number substituted for "n" in the channel callback type - * (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0). - */ - TCC_CALLBACK_CHANNEL_n = n, -# else - /** Callbacks for Match/Capture channels, e.g., TCC_CALLBACK_CHANNEL_0. */ - _TCC_CHANNEL_ENUM_LIST(CALLBACK) -# endif - -# if !defined(__DOXYGEN__) - /** Number of available callbacks. */ - TCC_CALLBACK_N -# endif -}; -#endif /* #if TCC_ASYNC == true */ - -/** - * \name Module Status Flags - * - * TCC status flags, returned by \ref tcc_get_status() and cleared by - * \ref tcc_clear_status(). - * - * @{ - */ - -/** Timer channel \c ch (0 ~ 3) has matched against its compare value, - * or has captured a new value. - */ -#define TCC_STATUS_CHANNEL_MATCH_CAPTURE(ch) (1UL << (ch)) -/** Timer channel \c ch (0 ~ 3) match/compare output state. */ -#define TCC_STATUS_CHANNEL_OUTPUT(ch) (1UL << ((ch)+8)) -/** A Non-Recoverable Fault \c x (0 ~ 1) has occurred. */ -#define TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) (1UL << ((x)+16)) -/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occured. */ -#define TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) (1UL << ((n)+18)) -/** The Non-Recoverable Fault \c x (0 ~ 1) input is present. */ -#define TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) (1UL << ((x)+20)) -/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) is present. */ -#define TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) (1UL << ((n)+22)) -/** Timer registers synchronization has completed, and the synchronized count - * value may be read. - */ -#define TCC_STATUS_SYNC_READY (1UL << 23) -/** A new value was captured before the previous value was read, resulting in - * lost data. - */ -#define TCC_STATUS_CAPTURE_OVERFLOW (1UL << 24) -/** A counter event occurred. */ -#define TCC_STATUS_COUNTER_EVENT (1UL << 25) -/** A counter retrigger occurred. */ -#define TCC_STATUS_COUNTER_RETRIGGERED (1UL << 26) -/** The timer count value has overflowed from its maximum value to its minimum - * when counting upward, or from its minimum value to its maximum when - * counting downward. - */ -#define TCC_STATUS_COUNT_OVERFLOW (1UL << 27) -/** Ramp period cycle index. - * In ramp operation, each two period cycles are marked as cycle A and B, - * the index 0 represents cycle A and 1 represents cycle B. */ -#define TCC_STATUS_RAMP_CYCLE_INDEX (1UL << 28) -/** The counter has been stopped (due to disable, stop command or one-shot). */ -#define TCC_STATUS_STOPPED (1UL << 29) - -/** @} */ - -/** - * \brief Index of the match capture channels - * - * This enum is used to specify which capture/match channel to do - * operations on. - */ -enum tcc_match_capture_channel { -# if defined(__DOXYGEN__) - /** Match capture channel index table for TCC - * - * Each TCC module may contain several match capture channels; each channel - * will have its own index in the table, with the index number substituted - * for "n" in the index name (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0). - */ - TCC_MATCH_CAPTURE_CHANNEL_n = n, -# else - /** Indexes of match capture channels, e.g., TCC_MATCH_CAPTURE_CHANNEL_0. */ - _TCC_CHANNEL_ENUM_LIST(MATCH_CAPTURE) -# endif -# if !defined(__DOXYGEN__) - /** Number of supported channels. */ - TCC_MATCH_CAPTURE_CHANNEL_N -# endif -}; - -/** - * \brief Index of the wave outputs - * - * This enum is used to specify which wave output to do - * operations on. - */ -enum tcc_wave_output { -# if defined(__DOXYGEN__) - /** Waveform output index table for TCC - * - * Each TCC module may contain several wave outputs; each output - * will have its own index in the table, with the index number substituted - * for "n" in the index name (e.g. \c TCC_WAVE_OUTPUT_0). - */ - TCC_WAVE_OUTPUT_n = n, -# else - /** Indexes of match capture channels, e.g., TCC_WAVEFORM_OUTPUT_0. */ - _TCC_WO_ENUM_LIST(WAVE_OUTPUT) -# endif -# if !defined(__DOXYGEN__) - /** Number of supported channels. */ - TCC_WAVE_OUTPUT_N -# endif -}; - -/** - * \brief TCC wave generation mode enum - * - * This enum is used to specify the waveform generation mode. - * - */ -enum tcc_wave_generation { - /** Normal Frequency: Top is the PER register, output toggled on each - * compare match. */ - TCC_WAVE_GENERATION_NORMAL_FREQ = 0, - /** Match Frequency: Top is CC0 register, output toggles on each update - * condition. */ - TCC_WAVE_GENERATION_MATCH_FREQ = 1, - /** Single-Slope PWM: Top is the PER register, CCx controls duty cycle ( - * output active when count is greater than CCx). */ - TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM = 2, - - /** Double-slope (count up and down), non centre-aligned: Top is the PER - * register, CC[x] controls duty cycle while counting up and CC[x+N/2] - * controls it while counting down. */ - TCC_WAVE_GENERATION_DOUBLE_SLOPE_CRITICAL = 4, - /** Double-slope (count up and down), interrupt/event at Bottom (Top is the - * PER register, output active when count is greater than CCx). */ - TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTTOM = 5, - /** Double-slope (count up and down), interrupt/event at Bottom and Top: (Top is the - * PER register, output active when count is lower than CCx). */ - TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTH = 6, - /** Double-slope (count up and down), interrupt/event at Top (Top is the - * PER register, output active when count is greater than CCx). */ - TCC_WAVE_GENERATION_DOUBLE_SLOPE_TOP = 7, -}; - -/** - * \brief Polarity of TCC wave generation on channels - * - * Specifies whether the wave output needs to be inverted or not. - */ -enum tcc_wave_polarity { - /** Wave output is not inverted. */ - TCC_WAVE_POLARITY_0, - /** Wave output is inverted. */ - TCC_WAVE_POLARITY_1 -}; - -/** - * \brief TCC pattern generator for outputs - * - * Used when disabling output pattern or when selecting a specific pattern. - */ -enum tcc_output_pattern { - /** SWAP output pattern is not used. */ - TCC_OUTPUT_PATTERN_DISABLE, - /** Pattern 0 is applied to SWAP output. */ - TCC_OUTPUT_PATTERN_0, - /** Pattern 1 is applied to SWAP output. */ - TCC_OUTPUT_PATTERN_1 -}; - -/** - * \brief Ramp Operations which are supported in single-slope PWM generation - * - * Ramp operations which are supported in single-slope PWM generation. - */ -enum tcc_ramp { - /** Default timer/counter PWM operation. */ - TCC_RAMP_RAMP1 = 0, - - /** Uses a single channel (CC0) to control both CC0/CC1 compare outputs. - * In cycle A, the channel 0 output is disabled, and - * in cycle B, the channel 1 output is disabled. */ - TCC_RAMP_RAMP2A, - - /** Uses channels CC0 and CC1 to control compare outputs. - * In cycle A, the channel 0 output is disabled, and - * in cycle B, the channel 1 output is disabled.*/ - TCC_RAMP_RAMP2 -}; - -/** - * \brief Ramp Index for TCC wave generation - * - * In ramp operation, each two period cycles are marked as cycle A and B, - * the index 0 represents cycle A and 1 represents cycle B. - */ -enum tcc_ramp_index { - /** Default, cycle index toggles. */ - TCC_RAMP_INDEX_DEFAULT, - /** Force next cycle to be cycle B (set to 1). */ - TCC_RAMP_INDEX_FORCE_B, - /** Force next cycle to be cycle A (clear to 0). */ - TCC_RAMP_INDEX_FORCE_A, - /** Force next cycle keeping the same as current. */ - TCC_RAMP_INDEX_FORCE_KEEP -}; - -/** - * \brief TCC output inversion - * - * Used when enabling or disabling output inversion. - */ -enum tcc_output_invertion { - /** Output inversion not to be enabled. */ - TCC_OUTPUT_INVERTION_DISABLE, - /** Invert the output from WO[x]. */ - TCC_OUTPUT_INVERTION_ENABLE -}; - -/** - * \brief TCC Counter reload action enum - * - * This enum specify how the counter is reloaded and whether the prescaler - * should be restarted. - */ -enum tcc_reload_action { - /** The counter is reloaded/reset on the next GCLK and starts - * counting on the prescaler clock. - */ - TCC_RELOAD_ACTION_GCLK, - /** The counter is reloaded/reset on the next prescaler clock. - */ - TCC_RELOAD_ACTION_PRESC, - /** The counter is reloaded/reset on the next GCLK, and the - * prescaler is restarted as well. - */ - TCC_RELOAD_ACTION_RESYNC -}; - - -/** - * \brief TCC clock prescaler values - * - * This enum is used to choose the clock prescaler - * configuration. The prescaler divides the clock frequency of the TCC - * module to operate TCC at a slower clock rate. - */ -enum tcc_clock_prescaler { - /** Divide clock by 1. */ - TCC_CLOCK_PRESCALER_DIV1, - /** Divide clock by 2. */ - TCC_CLOCK_PRESCALER_DIV2, - /** Divide clock by 4. */ - TCC_CLOCK_PRESCALER_DIV4, - /** Divide clock by 8. */ - TCC_CLOCK_PRESCALER_DIV8, - /** Divide clock by 16. */ - TCC_CLOCK_PRESCALER_DIV16, - /** Divide clock by 64. */ - TCC_CLOCK_PRESCALER_DIV64, - /** Divide clock by 256. */ - TCC_CLOCK_PRESCALER_DIV256, - /** Divide clock by 1024. */ - TCC_CLOCK_PRESCALER_DIV1024 -}; - -/** - * \brief TCC module count direction - * - * Used when selecting the Timer/Counter count direction. - */ -enum tcc_count_direction { - /** Timer should count upward. */ - TCC_COUNT_DIRECTION_UP, - /** Timer should count downward. */ - TCC_COUNT_DIRECTION_DOWN, -}; - -/** - * \brief Action to perform when the TCC module is triggered by events - * - * Event action to perform when the module is triggered by events. - */ -enum tcc_event_action { - /** No event action. */ - TCC_EVENT_ACTION_OFF, - /** Stop counting, the counter will maintain its current value, waveforms - * are set to a defined Non-Recoverable State output - * (\ref tcc_non_recoverable_state_output). */ - TCC_EVENT_ACTION_STOP, - /** Re-trigger counter on event, may generate an event if the re-trigger - * event output is enabled. - * \note When re-trigger event action is enabled, enabling the counter - * will not start until the next incoming event appears. */ - TCC_EVENT_ACTION_RETRIGGER, - - /** Start counter when previously stopped. - * Start counting on the event rising edge. Further events will not - * restart the counter; - * the counter keeps on counting using prescaled GCLK_TCCx, until it - * reaches TOP or Zero - * depending on the direction. */ - TCC_EVENT_ACTION_START, - /** Count events; i.e. Increment or decrement depending on count - * direction. */ - TCC_EVENT_ACTION_COUNT_EVENT, - /** The event source must be an asynchronous event, input value will - * overrides the direction settings (input low: counting up, input high - * counting down). */ - TCC_EVENT_ACTION_DIR_CONTROL, - /** Increment the counter on event, irrespective of count direction. */ - TCC_EVENT_ACTION_INCREMENT, - /** Decrement the counter on event, irrespective of count direction. */ - TCC_EVENT_ACTION_DECREMENT, - /** Count during active state of asynchronous event. In this case, - * depending on the count direction, the count will be incremented - * or decremented on each prescaled GCLK_TCCx, as long as the input - * event remains active. */ - TCC_EVENT_ACTION_COUNT_DURING_ACTIVE, - - /** Store period in capture register 0, pulse width in capture - * register 1. - */ - TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE, - /** Store pulse width in capture register 0, period in capture - * register 1. - */ - TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE, - - /** Generate Non-Recoverable Fault on event. */ - TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT, -}; - - -/** - * \brief Action to be performed when the TCC module is triggered by event0 - * - * Event action to perform when the module is triggered by event0. - */ -enum tcc_event0_action { - /** No event action. */ - TCC_EVENT0_ACTION_OFF = TCC_EVENT_ACTION_OFF, - /** Re-trigger Counter on event. */ - TCC_EVENT0_ACTION_RETRIGGER = TCC_EVENT_ACTION_RETRIGGER, - /** Count events (increment or decrement, depending on count direction). - */ - TCC_EVENT0_ACTION_COUNT_EVENT = TCC_EVENT_ACTION_COUNT_EVENT, - /** Start counter on event. */ - TCC_EVENT0_ACTION_START = TCC_EVENT_ACTION_START, - /** Increment counter on event. */ - TCC_EVENT0_ACTION_INCREMENT = TCC_EVENT_ACTION_INCREMENT, - /** Count during active state of asynchronous event. */ - TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE = TCC_EVENT_ACTION_COUNT_DURING_ACTIVE, - - /** Generate Non-Recoverable Fault on event. */ - TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT -}; - -/** - * \brief Action to perform when the TCC module is triggered by event1 - * - * Event action to perform when the module is triggered by event1. - */ -enum tcc_event1_action { - /** No event action. */ - TCC_EVENT1_ACTION_OFF = TCC_EVENT_ACTION_OFF, - /** Re-trigger Counter on event. */ - TCC_EVENT1_ACTION_RETRIGGER = TCC_EVENT_ACTION_RETRIGGER, - /** The event source must be an asynchronous event, input value will - * override the direction settings. - * If TCEINVx is 0 and input event is LOW: counter will count up. - * If TCEINVx is 0 and input event is HIGH: counter will count down. - */ - TCC_EVENT1_ACTION_DIR_CONTROL = TCC_EVENT_ACTION_DIR_CONTROL, - /** Stop counter on event. */ - TCC_EVENT1_ACTION_STOP = TCC_EVENT_ACTION_STOP, - /** Decrement on event. */ - TCC_EVENT1_ACTION_DECREMENT = TCC_EVENT_ACTION_DECREMENT, - - /** Store period in capture register 0, pulse width in capture - * register 1. - */ - TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE = TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE, - /** Store pulse width in capture register 0, period in capture - * register 1. - */ - TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE = TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE, - - /** Generate Non-Recoverable Fault on event. */ - TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT -}; - -/** - * \brief On which part of the counter cycle the counter event output is generated - * - * This enum is used to define the point at which the counter event is generated. - */ -enum tcc_event_generation_selection { - /** Counter Event is generated when a new counter cycle starts. */ - TCC_EVENT_GENERATION_SELECTION_START, - /** Counter Event is generated when a counter cycle ends. */ - TCC_EVENT_GENERATION_SELECTION_END, - /** Counter Event is generated when a counter cycle ends, except for the - * first and last cycles. */ - TCC_EVENT_GENERATION_SELECTION_BETWEEN, - /** Counter Event is generated when a new counter cycle starts or ends. */ - TCC_EVENT_GENERATION_SELECTION_BOUNDARY -}; - -/** - * \brief TCC channel operation modes - * - * To set a timer channel either in compare or in capture mode. - */ -enum tcc_channel_function { - /** TCC channel performs compare operation. */ - TCC_CHANNEL_FUNCTION_COMPARE, - /** TCC channel performs capture operation. */ - TCC_CHANNEL_FUNCTION_CAPTURE -}; - -/** - * \brief TCC (recoverable) fault Halt action - */ -enum tcc_fault_halt_action { - /** Halt action disabled. */ - TCC_FAULT_HALT_ACTION_DISABLE, - /** Hardware halt action, counter is halted until restart. */ - TCC_FAULT_HALT_ACTION_HW_HALT, - /** Software halt action, counter is halted until fault bit cleared. */ - TCC_FAULT_HALT_ACTION_SW_HALT, - /** Non-Recoverable fault, force output to pre-defined level. */ - TCC_FAULT_HALT_ACTION_NON_RECOVERABLE -}; - -/** - * \brief TCC (recoverable) fault Capture action - */ -enum tcc_fault_capture_action { - /** Capture disabled. */ - TCC_FAULT_CAPTURE_DISABLE, - /** Capture on Fault, each value is captured. */ - TCC_FAULT_CAPTURE_EACH, - /** Capture the minimum detection, but notify on smaller ones. */ - TCC_FAULT_CAPTURE_MINIMUM, - /** Capture the maximum detection, but notify on bigger ones. */ - TCC_FAULT_CAPTURE_MAXIMUM, - /** Capture if the value is smaller than last, notify event or interrupt - * if previous stamp is confirmed to be "local minimum" (not bigger than - * current stamp). */ - TCC_FAULT_CAPTURE_SMALLER, - /** Capture if the value is bigger than last, notify event or interrupt - * if previous stamp is confirmed to be "local maximum" (not smaller than - * current stamp). */ - TCC_FAULT_CAPTURE_BIGGER, - /** Capture if the time stamps changes its increment direction. */ - TCC_FAULT_CAPTURE_CHANGE -}; - -/** - * \brief Capture Channel triggered by TCC (recoverable) fault - */ -enum tcc_fault_capture_channel { - /** Recoverable fault triggers channel 0 capture operation. */ - TCC_FAULT_CAPTURE_CHANNEL_0, - /** Recoverable fault triggers channel 1 capture operation. */ - TCC_FAULT_CAPTURE_CHANNEL_1, - /** Recoverable fault triggers channel 2 capture operation. */ - TCC_FAULT_CAPTURE_CHANNEL_2, - /** Recoverable fault triggers channel 3 capture operation. */ - TCC_FAULT_CAPTURE_CHANNEL_3 -}; - -/** - * \brief TCC (recoverable) fault Input Source - */ -enum tcc_fault_source { - /** Fault input is disabled. */ - TCC_FAULT_SOURCE_DISABLE, - /** Match Capture Event x (x=0,1) input. */ - TCC_FAULT_SOURCE_ENABLE, - /** Inverted MCEx (x=0,1) event input. */ - TCC_FAULT_SOURCE_INVERT, - /** Alternate fault (A or B) state at the end of the previous period. */ - TCC_FAULT_SOURCE_ALTFAULT -}; - -/** - * \brief TCC (recoverable) fault Input Blanking Start Point - */ -enum tcc_fault_blanking { - /** No blanking. */ - TCC_FAULT_BLANKING_DISABLE, - /** Blanking applied from rising edge of the output waveform. */ - TCC_FAULT_BLANKING_RISING_EDGE, - /** Blanking applied from falling edge of the output waveform. */ - TCC_FAULT_BLANKING_FALLING_EDGE, - /** Blanking applied from each toggle of the output waveform. */ - TCC_FAULT_BLANKING_BOTH_EDGE -}; - -/** - * \brief TCC (recoverable) fault Input Qualification Action - */ -enum tcc_fault_qualification { - /** The input is not disabled on compare condition. */ - TCC_FAULT_QUALIFICATION_DISABLE, - /** The input is disabled when match output signal is at inactive level. */ - TCC_FAULT_QUALIFICATION_BY_OUTPUT -}; - -/** - * \brief TCC (recoverable) fault Output Keep Action - */ -enum tcc_fault_keep { - /** Disable keeping, wave output released as soon as fault is released. */ - TCC_FAULT_KEEP_DISABLE, - /** Keep wave output until end of TCC cycle. */ - TCC_FAULT_KEEP_TILL_END -}; - -/** - * \brief TCC Non-recoverable State Outupt - */ -enum tcc_fault_state_output { - /** Non-recoverable fault output is tri-stated. */ - TCC_FAULT_STATE_OUTPUT_OFF, - /** Non-recoverable fault force output 0. */ - TCC_FAULT_STATE_OUTPUT_0, - /** Non-recoverable fault force output 1. */ - TCC_FAULT_STATE_OUTPUT_1 -}; - -/** - * \brief TCC (recoverable) fault Restart Action - */ -enum tcc_fault_restart { - /** Restart Action disabled. */ - TCC_FAULT_RESTART_DISABLE, - /** Restart Action enabled. */ - TCC_FAULT_RESTART_ENABLE -}; - -/** - * \brief Configuration struct for TCC module recoverable fault - */ -struct tcc_recoverable_fault_config { - /** Fault filter value applied on MCEx event input line (0x0 ~ 0xF). - * Must be 0 when MCEx event is used as synchronous event. - * Apply to both recoverable and non-recoverable fault. */ - uint8_t filter_value; - /** Fault blanking value (0 ~ 255), disable input source for several TCC - * clocks after the detection of the waveform edge. */ - uint8_t blanking_cycles; - - /** Set to \c true to enable restart action. */ - bool restart; - /** Set to \c true to enable keep action (keep until end of TCC cycle). */ - bool keep; - - /** Set to \c true to enable input qualification - * (disable input when output is inactive). */ - bool qualification; - - /** Specifies if the event input generates recoverable Fault. - * The event system channel connected to MCEx event input must be - * configured as asynchronous. - */ - enum tcc_fault_source source; - /** Fault Blanking Start Point for recoverable Fault. */ - enum tcc_fault_blanking blanking; - - /** Halt action for recoverable Fault. */ - enum tcc_fault_halt_action halt_action; - /** Capture action for recoverable Fault. */ - enum tcc_fault_capture_action capture_action; - /** Channel triggered by recoverable Fault. */ - enum tcc_fault_capture_channel capture_channel; -}; - -/** - * \brief Configuration struct for TCC module non-recoverable fault - */ -struct tcc_non_recoverable_fault_config { - /** Fault filter value applied on TCEx event input line (0x0 ~ 0xF). - * Must be 0 when TCEx event is used as synchronous event. */ - uint8_t filter_value; - /** Output. */ - enum tcc_fault_state_output output; -}; - -/** - * \brief TCC input event enable/disable/configure structure - * - * For configuring an input event. - */ -struct tcc_input_event_config { - /** Event action on incoming event. */ - enum tcc_event_action action; - /** Modify event action. */ - bool modify_action; - /** Invert incoming event input line. */ - bool invert; -}; - -/** - * \brief TCC output event enable/disable/configure structure - * - * Structure used for configuring an output event. - */ -struct tcc_output_event_config { - /** It decides which part of the counter cycle the counter event output - * is generated. */ - enum tcc_event_generation_selection generation_selection; - /** A switch to allow enable/disable of events, without modifying the - * event output configuration. - */ - bool modify_generation_selection; -}; - -/** - * \brief TCC event enable/disable structure - * - * Event flags for the \ref tcc_enable_events() and \ref tcc_disable_events(). - */ -struct tcc_events { - /** Input events configuration. */ - struct tcc_input_event_config input_config[2]; - /** Output event configuration. */ - struct tcc_output_event_config output_config; - - /** Perform the configured event action when an incoming event is - * signalled. */ - bool on_input_event_perform_action[2]; - - /** Perform the configured event action when an incoming channel event is - * signalled. */ - bool on_event_perform_channel_action[TCC_NUM_CHANNELS]; - /** Generate an output event on a channel capture/match. - * Specify which channels will generate events. */ - bool generate_event_on_channel[TCC_NUM_CHANNELS]; - - /** Generate an output event on counter overflow/underflow. */ - bool generate_event_on_counter_overflow; - /** Generate an output event on counter retrigger. */ - bool generate_event_on_counter_retrigger; - /** Generate an output event on counter boundary. - * See \ref tcc_event_output_action. */ - bool generate_event_on_counter_event; -}; - -/** - * \brief Configuration struct for the TCC module base counter - * - * Structure for configuring a TCC as a counter. - */ -struct tcc_counter_config { - /** Value to initialize the count register. */ - uint32_t count; - /** Period/top and period/top buffer values for counter. */ - uint32_t period; - - /** When \c true, counter will be stopped on the next hardware or - * software re-trigger event or overflow/underflow. - */ - bool oneshot; - - /** Specifies the direction for the TCC to count. */ - enum tcc_count_direction direction; - - /** GCLK generator used to clock the peripheral. */ - enum gclk_generator clock_source; - /** Specifies the prescaler value for GCLK_TCC. */ - enum tcc_clock_prescaler clock_prescaler; - /** Specifies the reload or reset time of the counter and prescaler - * resynchronization on a re-trigger event for the TCC. - */ - enum tcc_reload_action reload_action; -}; - -/** - * \brief Configuration struct for the TCC module capture - * - * Structure used when configuring TCC channels in capture mode. - */ -struct tcc_capture_config { - /** Channel functions selection (capture/match). */ - enum tcc_channel_function channel_function[TCC_NUM_CHANNELS]; -}; - -/** - * \brief Configuration struct for the TCC module match/wave generation - * - * The structure, which helps to configure a TCC channel for compare - * operation and wave generation. - */ -struct tcc_match_wave_config { - /** Channel functions selection (capture/match). */ - enum tcc_channel_function channel_function[TCC_NUM_CHANNELS]; - - /** Specifies polarity for match output waveform generation. */ - enum tcc_wave_polarity wave_polarity[TCC_NUM_CHANNELS]; - /** Specifies which waveform generation mode to use. */ - enum tcc_wave_generation wave_generation; - /** Specifies Ramp mode for waveform generation. */ - enum tcc_ramp wave_ramp; - - /** Value to be used for compare match on each channel. */ - uint32_t match[TCC_NUM_CHANNELS]; -}; - -/** - * \brief Configuration struct for the TCC module waveform extension - * - * This structure is used to specify the waveform extension features for TCC. - */ -struct tcc_wave_extension_config { - /** Configuration for recoverable faults. */ - struct tcc_recoverable_fault_config - recoverable_fault[TCC_NUM_FAULTS]; - /** Configuration for non-recoverable faults. */ - struct tcc_non_recoverable_fault_config - non_recoverable_fault[TCC_NUM_WAVE_OUTPUTS]; - - /** Invert waveform final outputs lines. */ - bool invert[TCC_NUM_WAVE_OUTPUTS]; -}; - -/** - * \brief Configuration struct for the TCC module output pins - * - * Structure which is used when taking wave output from TCC. - */ -struct tcc_pins_config { - /** Specifies pin output for each channel. */ - uint32_t wave_out_pin[TCC_NUM_WAVE_OUTPUTS]; - /** Specifies MUX setting for each output channel pin. */ - uint32_t wave_out_pin_mux[TCC_NUM_WAVE_OUTPUTS]; - /** When \c true, PWM output pin for the given channel is enabled. */ - bool enable_wave_out_pin[TCC_NUM_WAVE_OUTPUTS]; -}; - -/** - * \brief TCC configuration structure - * - * Configuration struct for a TCC instance. This structure should be - * initialized by the \ref tcc_get_config_defaults function before being - * modified by the user application. - */ -struct tcc_config { - /** Structure for configuring TCC base timer/counter. */ - struct tcc_counter_config counter; - /** TCC match/capture configurations. */ - union { - /** Helps to configure a TCC channel in capture mode. */ - struct tcc_capture_config capture; - /** For configuring a TCC channel in compare mode. */ - struct tcc_match_wave_config compare; - /** Serves the same purpose as compare. Used as an alias for - * compare, - * when a TCC channel is configured for wave generation. */ - struct tcc_match_wave_config wave; - }; - - /** Structure for configuring TCC waveform extension. */ - struct tcc_wave_extension_config wave_ext; - - /** Structure for configuring TCC output pins. */ - struct tcc_pins_config pins; - - /** Set to \c true to enable double buffering write. When enabled any write - * through \ref tcc_set_top_value(), \ref tcc_set_compare_value() and - * \ref tcc_set_pattern() will direct to the buffer register as buffered - * value, and the buffered value will be committed to effective register - * on UPDATE condition, if update is not locked. - * - * \note The init values in \ref tcc_config for \ref tcc_init are always - * filled to effective registers, no matter double buffering - * enabled or not. - */ - bool double_buffering_enabled; - - /** When \c true the module is enabled during standby. */ - bool run_in_standby; -}; - -#if TCC_ASYNC == true -/* Forward Declaration for the device instance. */ -struct tcc_module; - -/** Type definition for the TCC callback function. */ -typedef void (*tcc_callback_t)(struct tcc_module *const module); -#endif - -/** - * \brief TCC software device instance structure - * - * TCC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved only for module-internal use. - */ -struct tcc_module { - /** Hardware module pointer of the associated Timer/Counter peripheral. */ - Tcc *hw; - -# if TCC_ASYNC == true - /** Array of callbacks. */ - tcc_callback_t callback[TCC_CALLBACK_N]; - /** Bit mask for callbacks registered. */ - uint32_t register_callback_mask; - /** Bit mask for callbacks enabled. */ - uint32_t enable_callback_mask; -# endif - - /** Set to \c true to write to buffered registers. */ - bool double_buffering_enabled; -}; - -#if !defined(__DOXYGEN__) -uint8_t _tcc_get_inst_index( - Tcc *const hw); -#endif - -/** - * \name Driver Initialization and Configuration - * @{ - */ - -/** - * \brief Determines if the hardware module is currently synchronizing to the bus - * - * Checks to see if the underlying hardware peripheral module is currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Synchronization status of the underlying hardware module. - * - * \retval false If the module has completed synchronization - * \retval true If the module synchronization is ongoing - */ -static inline bool tcc_is_syncing( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return (module_inst->hw->SYNCBUSY.reg > 0); -} - - -void tcc_get_config_defaults( - struct tcc_config *const config, - Tcc *const hw); - -enum status_code tcc_init( - struct tcc_module *const module_inst, - Tcc *const hw, - const struct tcc_config *const config); - -/** @} */ - -/** - * \name Event Management - * @{ - */ - -enum status_code tcc_enable_events( - struct tcc_module *const module_inst, - struct tcc_events *const events); - -void tcc_disable_events( - struct tcc_module *const module_inst, - struct tcc_events *const events); - -/** @} */ - -/** - * \name Enable/Disable/Reset - * @{ - */ - -/** - * \brief Enable the TCC module - * - * Enables a TCC module that has been previously initialized. The counter will - * start when the counter is enabled. - * - * \note When the counter is configured to re-trigger on an event, the counter - * will not start until the next incoming event appears. Then it - * restarts on any following event. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_enable( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) { - /* Wait for sync */ - } - - /* Enable the TCC module */ - tcc_module->CTRLA.reg |= TCC_CTRLA_ENABLE; -} - -/** - * \brief Disables the TCC module - * - * Disables a TCC module and stops the counter. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_disable( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) { - /* Wait for sync */ - } - - /* Disable the TCC module */ - tcc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; -} - -/** - * \brief Resets the TCC module - * - * Resets the TCC module, restoring all hardware module registers to their - * default values and disabling the module. The TCC module will not be - * accessible while the reset is being performed. - * - * \note When resetting a 32-bit counter only the master TCC module's instance - * structure should be passed to the function. - * - * \param[in] module_inst Pointer to the software module instance struct - * - */ -static inline void tcc_reset( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - /* Disable this module if it is running */ - if (tcc_module->CTRLA.reg & TCC_CTRLA_ENABLE) { - tcc_disable(module_inst); - while (tcc_is_syncing(module_inst)) { - /* wait while module is disabling */ - } - } - - /* Reset this TC module */ - tcc_module->CTRLA.reg |= TCC_CTRLA_SWRST; -} - -/** @} */ - - -/** - * \name Set/Toggle Count Direction - * @{ - */ - -/** - * \brief Sets the TCC module count direction - * - * Sets the count direction of an initialized TCC module. The - * specified TCC module can remain running or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] dir New timer count direction to set - */ -static inline void tcc_set_count_direction( - const struct tcc_module *const module_inst, - enum tcc_count_direction dir) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - - /* Set count direction */ - if (TCC_COUNT_DIRECTION_DOWN == dir) { - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR; - return; - } - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR; -} - -/** - * \brief Toggles the TCC module count direction - * - * Toggles the count direction of an initialized TCC module. The - * specified TCC module can remain running or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_toggle_count_direction( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - bool dir_value_1 = tcc_module->CTRLBSET.bit.DIR; - if (dir_value_1) { - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR; - } else { - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR; - } -} - -/** @} */ - -/** - * \name Get/Set Count Value - * @{ - */ - -uint32_t tcc_get_count_value( - const struct tcc_module *const module_inst); - -enum status_code tcc_set_count_value( - const struct tcc_module *const module_inst, - const uint32_t count); - -/** @} */ - -/** - * \name Stop/Restart Counter - * @{ - */ - -/** - * \brief Stops the counter - * - * This function will stop the counter. When the counter is stopped - * the value in the count register is set to 0 if the counter was - * counting up, or maximum or the top value if the counter was counting - * down. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_stop_counter( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait until last command is done */ - do { - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; - if (last_cmd == TCC_CTRLBSET_CMD_NONE) { - break; - } else if (last_cmd == TCC_CTRLBSET_CMD_STOP) { - /* Command have been issued */ - return; - } else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) { - /* Cancel RETRIGGER command and issue STOP */ - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk; - } - } while (1); - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_STOP; -} - -/** - * \brief Starts the counter from beginning - * - * Restarts an initialized TCC module's counter. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_restart_counter( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait until last command is done */ - do { - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; - if (last_cmd == TCC_CTRLBSET_CMD_NONE) { - break; - } else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) { - /* Command have been issued */ - return; - } else if (last_cmd == TCC_CTRLBSET_CMD_STOP) { - /* Cancel STOP command and issue RETRIGGER */ - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk; - } - } while (1); - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_RETRIGGER; -} - -/** @} */ - -#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER -/** - * \name Generate TCC DMA Triggers command - * @{ - */ - -/** - * \brief TCC DMA Trigger. - * - * TCC DMA trigger command. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_dma_trigger_command( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_NONE; - - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMATRG; -} -/** @} */ -#endif - -/** - * \name Get/Set Compare/Capture Register - * @{ - */ - -uint32_t tcc_get_capture_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index); - -enum status_code tcc_set_compare_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index, - const uint32_t compare); - -/** @} */ - -/** - * \name Set Top Value - * @{ - */ - -enum status_code tcc_set_top_value( - const struct tcc_module *const module_inst, - const uint32_t top_value); - -/** @} */ - - -/** - * \name Set Output Pattern - * @{ - */ - -enum status_code tcc_set_pattern( - const struct tcc_module *const module_inst, - const uint32_t line_index, - const enum tcc_output_pattern pattern); - -/** @} */ - - -/** - * \name Set Ramp Index - * @{ - */ - -/** - * \brief Sets the TCC module ramp index on next cycle - * - * In RAMP2 and RAMP2A operation, we can force either cycle A or cycle B at - * the output, on the next clock cycle. - * When ramp index command is disabled, cycle A and cycle B will appear at - * the output, on alternate clock cycles. - * See \ref tcc_ramp. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] ramp_index Ramp index (\ref tcc_ramp_index) of the next cycle - */ -static inline void tcc_set_ramp_index( - const struct tcc_module *const module_inst, - const enum tcc_ramp_index ramp_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait until last command is done */ - do { - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - if (TCC_RAMP_INDEX_DEFAULT == ramp_index) { - /* Cancel pending command */ - tcc_module->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD_DISABLE; - return; - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_IDXCMD_Msk; - if (last_cmd == TCC_CTRLBSET_IDXCMD_DISABLE) { - break; - } else if (last_cmd == TCC_CTRLBSET_CMD(ramp_index)) { - /* Command have been issued */ - return; - } - } while (1); - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD(ramp_index); -} - -/** @} */ - -/** - * \name Status Management - * @{ - */ - -/** - * \brief Checks if the timer/counter is running - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - * \return Status which indicates whether the module is running. - * - * \retval true The timer/counter is running - * \retval false The timer/counter is stopped - */ -static inline bool tcc_is_running( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return !module_inst->hw->STATUS.bit.STOP; -} - -uint32_t tcc_get_status( - struct tcc_module *const module_inst); - -void tcc_clear_status( - struct tcc_module *const module_inst, - const uint32_t status_flags); - -/** @} */ - -/** - * \name Double Buffering Management - * @{ - */ - -/** - * \brief Enable TCC double buffering write - * - * When double buffering write is enabled, following function will write values - * to buffered registers instead of effective ones (buffered): - * - PERB: through \ref tcc_set_top_value() - * - CCBx(x is 0~3): through \ref tcc_set_compare_value() - * - PATTB: through \ref tcc_set_pattern() - * - * Then on UPDATE condition the buffered registers are committed to regular ones - * to take effect. - * - * \param[in] module_inst Pointer to the TCC software instance struct - */ -static inline void tcc_enable_double_buffering( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - - module_inst->double_buffering_enabled = true; -} - -/** - * \brief Disable TCC double buffering Write - * - * When double buffering write is disabled, following function will write values - * to effective registers (not buffered): - * - PER: through \ref tcc_set_top_value() - * - CCx(x is 0~3): through \ref tcc_set_compare_value() - * - PATT: through \ref tcc_set_pattern() - * - * \note This function does not lock double buffer update, which means on next - * UPDATE condition the last written buffered values will be committed to - * take effect. Invoke \ref tcc_lock_double_buffer_update() before this - * function to disable double buffering update, if this change is not - * expected. - * - * \param[in] module_inst Pointer to the TCC software instance struct - */ -static inline void tcc_disable_double_buffering( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->double_buffering_enabled = false; -} - -/** - * \brief Lock the TCC double buffered registers updates - * - * Locks the double buffered registers so they will not be updated through - * their buffered values on UPDATE conditions. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - */ -static inline void tcc_lock_double_buffer_update( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - while (module_inst->hw->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - module_inst->hw->CTRLBSET.reg = TCC_CTRLBSET_LUPD; -} - -/** - * \brief Unlock the TCC double buffered registers updates - * - * Unlock the double buffered registers so they will be updated through - * their buffered values on UPDATE conditions. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - */ -static inline void tcc_unlock_double_buffer_update( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - while (module_inst->hw->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - module_inst->hw->CTRLBCLR.reg = TCC_CTRLBCLR_LUPD; -} - -/** - * \brief Force the TCC double buffered registers to update once - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - */ -static inline void tcc_force_double_buffer_update( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait until last command is done */ - do { - while (tcc_module->SYNCBUSY.bit.CTRLB) { - /* Wait for sync */ - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; - if (last_cmd == TCC_CTRLBSET_CMD_NONE) { - break; - } else if (last_cmd == TCC_CTRLBSET_CMD_UPDATE) { - /* Command have been issued */ - return; - } - } while (1); - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_UPDATE; -} - -/** - * \brief Enable Circular option for double buffered Top/Period Values - * - * Enable circular option for the double buffered top/period values. - * On each UPDATE condition, the contents of PERB and PER are switched, meaning - * that the contents of PERB are transferred to PER and the contents of PER are - * transferred to PERB. - * - * \param[in] module_inst Pointer to the TCC software instance struct - */ -static inline void tcc_enable_circular_buffer_top( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->WAVE.reg |= TCC_WAVE_CIPEREN; -} - -/** - * \brief Disable Circular option for double buffered Top/Period Values - * - * Stop circularing the double buffered top/period values. - * - * \param[in] module_inst Pointer to the TCC software instance struct - */ -static inline void tcc_disable_circular_buffer_top( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->WAVE.reg &= ~TCC_WAVE_CIPEREN; -} - -enum status_code tcc_set_double_buffer_top_values( - const struct tcc_module *const module_inst, - const uint32_t top_value, const uint32_t top_buffer_value); - - -enum status_code tcc_enable_circular_buffer_compare( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index); -enum status_code tcc_disable_circular_buffer_compare( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index); -enum status_code tcc_set_double_buffer_compare_values( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index, - const uint32_t compare, - const uint32_t compare_buffer); - - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** - * \page asfdoc_sam0_tcc_extra Extra Information for TCC Driver - * - * \section asfdoc_sam0_tcc_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DMADirect Memory Access
TCCTimer Counter for Control Applications
PWMPulse Width Modulation
PWPPulse Width Period
PPWPeriod Pulse Width
- * - * - * \section asfdoc_sam0_tcc_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_tcc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_tcc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Add double buffering functionality
Add fault handling functionality
Initial Release
- */ - -/** - * \page asfdoc_sam0_tcc_exqsg Examples for TCC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_tcc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_tcc_basic_use_case - * - \subpage asfdoc_sam0_tcc_buffering_use_case - * \if TCC_CALLBACK_MODE - * - \subpage asfdoc_sam0_tcc_timer_use_case - * - \subpage asfdoc_sam0_tcc_callback_use_case - * - \subpage asfdoc_sam0_tcc_faultx_use_case - * - \subpage asfdoc_sam0_tcc_faultn_use_case - * \endif - * - \subpage asfdoc_sam0_tcc_dma_use_case - * - * \page asfdoc_sam0_tcc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
C04/2015Added support for SAML21 and SAMDAx
B12/2014Added fault handling functionality; - * Added double buffering functionality with use case; - * Added timer use case; - * Added SAM R21/D10/D11 support
A01/2014Initial release
- */ - -#endif /* TCC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_api.c deleted file mode 100644 index 66bf6ca4cc2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_api.c +++ /dev/null @@ -1,92 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "PinNames.h" -#include "gpio_object.h" -#include "gpio_api.h" -#include "compiler.h" -#include "port.h" - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - return (1UL << (pin % 32)); -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - struct port_config pin_conf; - PortGroup *const port_base = (PortGroup*)port_get_group_from_gpio_pin(pin); - - obj->pin = pin; - if (pin == (PinName)NC) - return; - - obj->mask = gpio_set(pin); - port_get_config_defaults(&pin_conf); - obj->powersave = pin_conf.powersave; - obj->direction = PORT_PIN_DIR_INPUT; - obj->mode = PORT_PIN_PULL_UP; - port_pin_set_config(pin, &pin_conf); - - obj->OUTCLR = &port_base->OUTCLR.reg; - obj->OUTSET = &port_base->OUTSET.reg; - obj->IN = &port_base->IN.reg; - obj->OUT = &port_base->OUT.reg; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - struct port_config pin_conf; - - obj->mode = mode; - pin_conf.direction = (enum port_pin_dir)obj->direction; - pin_conf.powersave = obj->powersave; - switch (mode) { - case PullNone : - pin_conf.input_pull = PORT_PIN_PULL_NONE; - break; - case PullUp: - pin_conf.input_pull = PORT_PIN_PULL_UP; - break; - case PullDown: - pin_conf.input_pull = PORT_PIN_PULL_DOWN; - break; - } - port_pin_set_config(obj->pin, &pin_conf); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - struct port_config pin_conf; - obj->direction = direction; - pin_conf.input_pull = (enum port_pin_pull)obj->mode; - pin_conf.powersave = obj->powersave; - switch (direction) { - case PIN_INPUT : - pin_conf.direction = PORT_PIN_DIR_INPUT; - break; - case PIN_OUTPUT: - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - break; - case PIN_INPUT_OUTPUT: - pin_conf.direction = PORT_PIN_DIR_OUTPUT_WTH_READBACK; - break; - } - port_pin_set_config(obj->pin, &pin_conf); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_irq_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_irq_api.c deleted file mode 100644 index bbb369a63a4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_irq_api.c +++ /dev/null @@ -1,153 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" - -#include "gpio_irq_api.h" -#include "gpio_api.h" -#include "mbed_error.h" -#include "extint.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "port.h" - -#define IRQ_RISE_POSITION 1 -#define IRQ_FALL_POSITION 2 -#define CHANNEL_NUM 16 -#define pEXT_CONF(obj) (obj->config_extint_chan) -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; -uint8_t ext_int_pins[EIC_NUMBER_OF_INTERRUPTS] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; - -void gpio_irq(void) -{ - uint32_t current_channel; - uint32_t mask; - gpio_irq_event event; - PortGroup *port_base; - - for (current_channel = 0; current_channel < EIC_NUMBER_OF_INTERRUPTS ; current_channel++) { - if (extint_chan_is_detected(current_channel)) { - extint_chan_clear_detected(current_channel); - port_base = (PortGroup*)port_get_group_from_gpio_pin(ext_int_pins[current_channel]); - mask = gpio_set((PinName)ext_int_pins[current_channel]); - if ((port_base->IN.reg & mask) != 0) { - event = IRQ_RISE; - } else { - event = IRQ_FALL; - } - if(irq_handler) { - irq_handler(channel_ids[current_channel], event); - } - } - } -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - MBED_ASSERT(obj); - if (pin == NC) - return -1; - - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - int int_channel = 0; - irq_handler = handler; // assuming the usage of these apis in mbed layer only - - obj->pin = pin; - - extint_chan_get_config_defaults(&pEXT_CONF(obj)); - pEXT_CONF(obj).gpio_pin = (uint32_t)pin; - pEXT_CONF(obj).gpio_pin_mux = 0; // mux setting for ext int is 0 - pEXT_CONF(obj).gpio_pin_pull = EXTINT_PULL_UP; - pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_NONE; - - int_channel = pinmap_find_peripheral(pin, PinMap_EXTINT); - if (int_channel == NC) { - return -1; - } - extint_chan_set_config(int_channel, &pEXT_CONF(obj)); - ext_int_pins[int_channel] = pin; - - irq_n = EIC_IRQn; - vector = (uint32_t)gpio_irq; - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - obj->ch = int_channel; - channel_ids[int_channel] = id; - obj->irqmask = 0; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - MBED_ASSERT(obj); - Eic *const eic = _extint_get_eic_from_channel(obj->ch); - channel_ids[obj->ch] = 0; - eic->INTENCLR.reg = (1UL << obj->ch); -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - MBED_ASSERT(obj); - Eic *const eic = _extint_get_eic_from_channel(obj->ch); - if (enable) { - if (event == IRQ_RISE) { - obj->irqmask |= IRQ_RISE_POSITION; - } else if (event == IRQ_FALL) { - obj->irqmask |= IRQ_FALL_POSITION; - } - eic->INTENSET.reg = (1UL << obj->ch); - } else { - if (event == IRQ_RISE) { - obj->irqmask &= ~IRQ_RISE_POSITION; - } else if (event == IRQ_FALL) { - obj->irqmask &= ~IRQ_FALL_POSITION; - } - } - - if (obj->irqmask == (IRQ_RISE_POSITION | IRQ_FALL_POSITION)) { - pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_BOTH; - } else if (obj->irqmask == IRQ_RISE_POSITION) { - pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_RISING; - } else if (obj->irqmask == IRQ_FALL_POSITION) { - pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_FALLING; - } else { - pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_NONE; - eic->INTENCLR.reg = (1UL << obj->ch); - } - - extint_chan_set_config(obj->ch, &pEXT_CONF(obj)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - MBED_ASSERT(obj); - Eic *const eic = _extint_get_eic_from_channel(obj->ch); - NVIC_EnableIRQ(EIC_IRQn); - eic->INTENSET.reg = (1UL << obj->ch); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - MBED_ASSERT(obj); - Eic *const eic = _extint_get_eic_from_channel(obj->ch); - eic->INTENCLR.reg = (1UL << obj->ch); - if (eic->INTENSET.reg == 0) { - NVIC_DisableIRQ(EIC_IRQn); - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_object.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_object.h deleted file mode 100644 index 3f6d305f6d5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_object.h +++ /dev/null @@ -1,65 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - uint8_t powersave; - uint8_t mode; - uint8_t direction; - - __IO uint32_t *OUTCLR; - __IO uint32_t *OUTSET; - __I uint32_t *IN; - __I uint32_t *OUT; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) - *obj->OUTSET = obj->mask; - else - *obj->OUTCLR = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (obj->direction == PIN_INPUT) - return ((*obj->IN & obj->mask) ? 1 : 0); - else - return ((*obj->OUT & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c deleted file mode 100644 index 53e88606b8c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c +++ /dev/null @@ -1,1019 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include - -#include "cmsis.h" -#include "pinmap.h" -#include "sercom.h" -#include "i2c_master.h" -#include "i2c_slave.h" - -#include "pinmap_function.h" - -#if DEVICE_I2C_ASYNCH -#include "i2c_master_interrupt.h" -#endif - - -#if DEVICE_I2C_ASYNCH -#define pI2C_S(obj) (&obj->i2c) -#else -#define pI2C_S(obj) obj -#endif - -#define I2C_MASTER_DEFAULT_BAUD 100000 - -/** - * \brief I2C modes enum - * - * I2C mode selection. - */ -enum i2c_mode { - /** Master mode. */ - I2C_MODE_MASTER = 0x5, - /** Slave mode. */ - I2C_MODE_SLAVE = 0x4, -}; - -/* Extern Variables */ -extern uint8_t g_sys_init; - -typedef void (*I2CHandler)(void); - -#if DEVICE_I2C_ASYNCH -#define _SERCOM_INTERRUPT_HANDLERS(n, unused) (uint32_t)SERCOM##n##_Handler, - -/* To save the i2c objects */ -static uint32_t i2c_instances[SERCOM_INST_NUM] = {0}; -const uint32_t sercom_irq_handlers[SERCOM_INST_NUM] = { - MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLERS, ~) -}; - -#endif - -/* Forward declaration */ -enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module); - -enum status_code _i2c_master_address_response( - struct i2c_master_module *const module); - -enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code); - -/* Adding function from ASF for compatibility */ -static enum status_code _i2c_slave_wait_for_bus( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - MBED_ASSERT(module); - MBED_ASSERT(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Wait for reply. */ - uint16_t timeout_counter = 0; - while ((!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) && - (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) && - (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) { - - /* Check timeout condition. */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; -} - -/** Initialize the I2C peripheral - * - * Configures the pins used by I2C, sets a default format and frequency, and enables the peripheral - * @param[out] obj The I2C object to initialize - * @param[in] sda The pin to use for SDA - * @param[in] scl The pin to use for SCL - * @return void - */ -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - Sercom* hw; - uint32_t mux_func; - struct i2c_master_config config_i2c_master; - - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(sda != NC); - MBED_ASSERT(scl != NC); - - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - - pI2C_S(obj)->pins[0] = sda; - pI2C_S(obj)->pins[1] = scl; - - /* Calculate SERCOM instance from pins */ - uint32_t sercom_index = pinmap_merge_sercom(sda, scl); - if (sercom_index == (uint32_t)NC) { - return; - } - hw = (Sercom*)pinmap_peripheral_sercom(NC, sercom_index); - - i2c_master_get_config_defaults(&config_i2c_master); - - /* SERCOM PAD0 - SDA */ - mux_func = pinmap_function_sercom(sda, sercom_index); - if (mux_func == (uint32_t)NC) return; - config_i2c_master.pinmux_pad0 = (sda << 16) | (mux_func & 0xFFFF); - - /* SERCOM PAD1 - SCL */ - mux_func = pinmap_function_sercom(scl, sercom_index); - if (mux_func == (uint32_t)NC) return; - config_i2c_master.pinmux_pad1 = (scl << 16) | (mux_func & 0xFFFF); - - /* Default baud rate is set to 100kHz */ - pI2C_S(obj)->baud_rate = I2C_MASTER_DEFAULT_BAUD; - config_i2c_master.baud_rate = pI2C_S(obj)->baud_rate / 1000; - - while(i2c_master_init(&pI2C_S(obj)->master, hw, &config_i2c_master) != STATUS_OK); - pI2C_S(obj)->mode = I2C_MODE_MASTER; - -#if DEVICE_I2C_ASYNCH - /* Save the i2c object */ - i2c_instances[sercom_index] = (uint32_t)obj; -#endif - - i2c_master_enable(&pI2C_S(obj)->master); -} - -/** Configure the I2C frequency. - * @param obj The i2c object - * @param hz Frequency in Hz - */ -void i2c_frequency(i2c_t *obj, int hz) -{ - /* Temporary variables. */ - int32_t baud_rate; - int32_t tmp_baud; - int32_t tmp_baud_hs; - enum status_code tmp_status_code = STATUS_OK; - - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - /* Return if in Slave mode, slave do not have any baud to set */ - if (pI2C_S(obj)->mode != I2C_MODE_MASTER) return; - - SercomI2cm *const i2c_module = &(pI2C_S(obj)->master.hw->I2CM); - - /* Disable I2C Module */ - i2c_master_disable(&pI2C_S(obj)->master); - - baud_rate = hz / 1000; /* To kHz */ - - /* Give a dummy supported value */ - pI2C_S(obj)->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ; - - uint32_t sercom_index = _sercom_get_sercom_inst_index(pI2C_S(obj)->master.hw); - - /* Find and set baudrate. */ - tmp_baud = (int32_t)(div_ceil( - system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index), (2000*(baud_rate))) - 5); - - /* Check that baudrate is supported at current speed. */ - if (tmp_baud > 255 || tmp_baud < 0) { - /* Baud rate not supported. */ - tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; - } else { - /* Find baudrate for high speed */ - tmp_baud_hs = (int32_t)(div_ceil( - system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index), - (2000*(pI2C_S(obj)->baud_rate_high_speed))) - 1); - - /* Check that baudrate is supported at current speed. */ - if (tmp_baud_hs > 255 || tmp_baud_hs < 0) { - /* Baud rate not supported. */ - tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - } - if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) { - /* Baud rate acceptable. */ - i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) | SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs); - pI2C_S(obj)->baud_rate = hz; - } - - /* Enable back the I2C Module */ - i2c_master_enable(&pI2C_S(obj)->master); -} - -/** Send START command. - * @param obj The i2c object - */ -int i2c_start(i2c_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - if (pI2C_S(obj)->mode == I2C_MODE_MASTER) { - pI2C_S(obj)->start_pending = 1; - } - return 0; -} - -/** Send STOP command. - * @param obj The i2c object - */ -int i2c_stop(i2c_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - if (pI2C_S(obj)->mode == I2C_MODE_MASTER) { - /* Send STOP command */ - i2c_master_send_stop(&pI2C_S(obj)->master); - } else { - SercomI2cs *const i2c_hw = &(pI2C_S(obj)->slave.hw->I2CS); - /* Release line and wait for next start condition */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - } - - pI2C_S(obj)->start_pending = 0; - - /* TODO: Wait till STOP is send */ - return 0; -} - -/** Blocking reading data. - * @param obj The i2c object - * @param address 7-bit address (last bit is 1) - * @param data The buffer for receiving - * @param length Number of bytes to read - * @param stop Stop to be generated after the transfer is done - * @return Number of read bytes - */ -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - enum status_code tmp_status; - -#if DEVICE_I2C_ASYNCH - if (i2c_active(obj)) { - /* I2C is busy with a job */ - return 0; - } -#endif - - struct i2c_master_packet packet; - packet.address = (address & 0xFF) >> 1; - packet.data_length = length; - packet.data = (uint8_t*)data; - packet.ten_bit_address = false; - packet.high_speed = false; - - if (stop) { - tmp_status = i2c_master_read_packet_wait(&pI2C_S(obj)->master, &packet); - } else { - tmp_status = i2c_master_read_packet_wait_no_stop(&pI2C_S(obj)->master, &packet); - } - - if (tmp_status == STATUS_OK) { - return length; - } else { - /* Currently, no way to track no of bytes received, so return 0 if fail */ - return 0; - } -} - -/** Blocking sending data. - * @param obj The i2c object - * @param address 7-bit address (last bit is 0) - * @param data The buffer for sending - * @param length Number of bytes to write - * @param stop Stop to be generated after the transfer is done - * @return Number of written bytes - */ -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - enum status_code tmp_status; - -#if DEVICE_I2C_ASYNCH - if (i2c_active(obj)) { - /* I2C is busy with a job */ - return 0; - } -#endif - - struct i2c_master_packet packet; - packet.address = (address & 0xFF) >> 1; - packet.data_length = length; - packet.data = (uint8_t *)data; - packet.ten_bit_address = false; - packet.high_speed = false; - - if (stop) { - tmp_status = i2c_master_write_packet_wait(&pI2C_S(obj)->master, &packet); - } else { - tmp_status = i2c_master_write_packet_wait_no_stop(&pI2C_S(obj)->master, &packet); - } - - if (tmp_status == STATUS_OK) { - return length; - } else { - /* Currently, no way to track no of bytes transmitted, so return 0 if fail */ - return 0; - } -} - -/** Reset I2C peripheral. - * @param obj The i2c object - */ -void i2c_reset(i2c_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Send STOP */ - i2c_stop(obj); - - pI2C_S(obj)->start_pending = 0; -} - -/** Write address preceded by START condition. - * @param obj The i2c object - * @param address Address to be placed - * @param rw_flag read or write flag - * @return 1 if NAK was received, 0 if ACK was received, 2 for timeout. - */ -int i2c_write_address(i2c_t *obj, int address, int rw_flag) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - enum status_code tmp_status; - SercomI2cm *const i2c_module = &(pI2C_S(obj)->master.hw->I2CM); - - _i2c_master_wait_for_sync(&pI2C_S(obj)->master); - - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Write 7-bit address + read/write flag */ - i2c_module->ADDR.reg = ((address & 0x7F) << 1) | (rw_flag & 0x01) | (0 << SERCOM_I2CM_ADDR_HS_Pos); - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(&pI2C_S(obj)->master); - /* Check for error. */ - if (tmp_status != STATUS_OK) { - return I2C_ERROR_BUS_BUSY; - } - /* Check for address response error unless previous error is detected. */ - tmp_status = _i2c_master_address_response(&pI2C_S(obj)->master); - if (tmp_status != STATUS_OK) { - return I2C_ERROR_NO_SLAVE; - } - - return 0; -} - -/** Read one byte. - * @param obj The i2c object - * @param last Acknowledge - * @return The read byte - */ -int i2c_byte_read(i2c_t *obj, int last) -{ - int data = -1; - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - enum status_code tmp_status; - - if (pI2C_S(obj)->mode == I2C_MODE_MASTER) { - SercomI2cm *const i2c_module = &(pI2C_S(obj)->master.hw->I2CM); - - if (last) { - /* Set action to nack. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } else { - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - } - - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return -1; /* Return invalid data*/ - } - - /* Save data to buffer. */ - _i2c_master_wait_for_sync(&pI2C_S(obj)->master); - data = i2c_module->DATA.reg; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(&pI2C_S(obj)->master); - - /* Check for error. */ - if (tmp_status != STATUS_OK) { - return -1; /* Return invalid data*/ - } - - } else { -#if DEVICE_I2CSLAVE - SercomI2cs *const i2c_hw = &(pI2C_S(obj)->slave.hw->I2CS); - - /* Check direction */ - if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR) { - /* Write request from master, send NACK and return */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - return -1; /* Return invalid data*/ - } - - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - /* Request from master, Address not yet acknowledged */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } - if (last) { - /* Set action to nack. */ - i2c_hw->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } else { - /* Set action to ack. */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - } - - /* Wait for next byte or stop condition */ - tmp_status = _i2c_slave_wait_for_bus(&pI2C_S(obj)->slave); - if (tmp_status != STATUS_OK) { - /* Timeout, return */ - return -1; - } - - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) { - /* Master sent stop condition, or repeated start, read done */ - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - return -1; - } - - /* Read data */ - _i2c_slave_wait_for_sync(&pI2C_S(obj)->slave); - data = i2c_hw->DATA.reg; -#endif - } - - return data; -} - -/** Write one byte. - * @param obj The i2c object - * @param data Byte to be written - * @return 1 if NAK was received, 0 if ACK was received, 2 for timeout. - */ -int i2c_byte_write(i2c_t *obj, int data) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - enum status_code tmp_status; - - data = data & 0xFF; - - if (pI2C_S(obj)->mode == I2C_MODE_MASTER) { - SercomI2cm *const i2c_module = &(pI2C_S(obj)->master.hw->I2CM); - - if (pI2C_S(obj)->start_pending) { - pI2C_S(obj)->start_pending = 0; - /* Write address */ - return i2c_write_address(obj, (data >> 1), (data & 0x01)); - } else { - /* Write data */ - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return I2C_ERROR_NO_SLAVE; - } - - /* Write byte to slave. */ - _i2c_master_wait_for_sync(&pI2C_S(obj)->master); - i2c_module->DATA.reg = data; - - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(&pI2C_S(obj)->master); - /* Check for error. */ - if (tmp_status != STATUS_OK) { - return I2C_ERROR_BUS_BUSY; - } - - /* Check for NACK from slave. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Return bad data value. */ - return I2C_ERROR_NO_SLAVE; - } - } - } else { -#if DEVICE_I2CSLAVE - SercomI2cs *const i2c_hw = &(pI2C_S(obj)->slave.hw->I2CS); - - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - /* Read request from master, Address not yet acknowledged */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } - - /* Write data */ - _i2c_slave_wait_for_sync(&pI2C_S(obj)->slave); - i2c_hw->DATA.reg = data; - - /* Wait for response from master */ - tmp_status = _i2c_slave_wait_for_bus(&pI2C_S(obj)->slave); - - if (tmp_status != STATUS_OK) { - /* Timeout, return */ - return I2C_ERROR_BUS_BUSY; - } - - if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) { - /* NACK from master, abort */ - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - - return I2C_ERROR_NO_SLAVE; - } -#endif - } - - return 0; -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_SERCOM_PAD; -} - - -#if DEVICE_I2CSLAVE - -/** - * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave - * @{ - */ - -/** Configure I2C as slave or master. - * @param obj The I2C object - * @param enable_slave configure I2C in slave mode or not - * @return void - */ -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - int i; - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - uint32_t mux_func[2]; - uint32_t sercom_index = _sercom_get_sercom_inst_index(pI2C_S(obj)->master.hw); - for (i=0; i<2; i++) { - mux_func[i] = pinmap_function_sercom(pI2C_S(obj)->pins[0], sercom_index); - if (mux_func[i] == (uint32_t)NC) return; - } - - if (enable_slave) { - /* Disable I2C Master module if active */ - i2c_master_disable(&pI2C_S(obj)->master); - - struct i2c_slave_config config_i2c_slave; - i2c_slave_get_config_defaults(&config_i2c_slave); - - /* SERCOM PAD0 - SDA */ - config_i2c_slave.pinmux_pad0 = (pI2C_S(obj)->pins[0] << 16) | (mux_func[0] & 0xFFFF); - /* SERCOM PAD1 - SCL */ - config_i2c_slave.pinmux_pad1 = (pI2C_S(obj)->pins[1] << 16) | (mux_func[1] & 0xFFFF); - - i2c_slave_init(&pI2C_S(obj)->slave, pI2C_S(obj)->master.hw, &config_i2c_slave); - - pI2C_S(obj)->mode = I2C_MODE_SLAVE; - - i2c_slave_enable(&pI2C_S(obj)->slave); - } else { - if ((pI2C_S(obj)->master.hw) && (pI2C_S(obj)->mode == I2C_MODE_MASTER)) { - /* Already configured, enable and return */ - i2c_master_enable(&pI2C_S(obj)->master); - return; - } else if ((pI2C_S(obj)->slave.hw) && (pI2C_S(obj)->mode == I2C_MODE_SLAVE)) { - /* Disable slave */ - i2c_slave_disable(&pI2C_S(obj)->slave); - } - - struct i2c_master_config config_i2c_master; - /* SERCOM PAD0 - SDA */ - config_i2c_master.pinmux_pad0 = (pI2C_S(obj)->pins[0] << 16) | (mux_func[0] & 0xFFFF); - /* SERCOM PAD1 - SCL */ - config_i2c_master.pinmux_pad1 = (pI2C_S(obj)->pins[1] << 16) | (mux_func[1] & 0xFFFF); - /* Baud rate */ - config_i2c_master.baud_rate = pI2C_S(obj)->baud_rate / 1000; - - while(i2c_master_init(&pI2C_S(obj)->master, pI2C_S(obj)->master.hw, &config_i2c_master) != STATUS_OK); - pI2C_S(obj)->mode = I2C_MODE_MASTER; - - i2c_master_enable(&pI2C_S(obj)->master); - } -} - -/** Check to see if the I2C slave has been addressed. - * @param obj The I2C object - * @return The status - 1 - read addresses, 2 - write to all slaves, - * 3 write addressed, 0 - the slave has not been addressed - */ -int i2c_slave_receive(i2c_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->slave.hw); - - SercomI2cs *const i2c_module = &(pI2C_S(obj)->slave.hw->I2CS); - - if (i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - if (i2c_module->STATUS.reg & SERCOM_I2CS_STATUS_DIR) { - /* Slave is read addressed */ - return 1; - } else { - if (!(i2c_module->DATA.reg & 0xFF)) { - /* General call address detected */ - return 2; - } else { - /* Slave is write addressed */ - return 3; - } - } - } - - return 0; -} - -/** Blocking reading data. - * @param obj The i2c slave object - * @param data The buffer for receiving - * @param length Number of bytes to read - * @return Number of read bytes - */ -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->slave.hw); - - if (!data || !length) return 0; - - enum status_code tmp_status; - - struct i2c_slave_packet packet; - packet.data_length = length; - packet.data = (uint8_t*)data; - - tmp_status = i2c_slave_read_packet_wait(&pI2C_S(obj)->slave, &packet); - - if (tmp_status == STATUS_OK) { - return length; - } else { - /* Currently, no way to track no of bytes transmitted, so return 0 */ - return 0; - } - -} - -/** Blocking writing data. - * @param obj The i2c slave object - * @param data The buffer for transmitting - * @param length Number of bytes to write - * @return Number of bytes written - */ -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->slave.hw); - - if (!data || !length) return 0; - - enum status_code tmp_status; - - struct i2c_slave_packet packet; - packet.data_length = length; - packet.data = (uint8_t *)data; - - tmp_status = i2c_slave_write_packet_wait(&pI2C_S(obj)->slave, &packet); - - if (tmp_status == STATUS_OK) { - return length; - } else { - /* Currently, no way to track no of bytes transmitted, so return 0 */ - return 0; - } - -} - -/** Configure I2C slave address. - * @param obj The I2C object - * @param idx Currently not used - * @param address The address to be set - * @param mask Currently not used - */ -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->slave.hw); - - /* Disable I2C Module */ - i2c_slave_disable(&pI2C_S(obj)->slave); - - SercomI2cs *const i2c_hw = &(pI2C_S(obj)->slave.hw->I2CS); - - address = (address & 0xFF) >> 1; - if (!mask) { - mask = (0xFE >> 1); - } - /* Set the address and address mask */ - i2c_hw->ADDR.reg = (address << SERCOM_I2CS_ADDR_ADDR_Pos) | - (mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos) | - (0 << SERCOM_I2CS_ADDR_TENBITEN_Pos) | - (1 << SERCOM_I2CS_ADDR_GENCEN_Pos); - - /* Enable I2C Module */ - i2c_slave_enable(&pI2C_S(obj)->slave); -} - -#endif /* DEVICE_I2CSLAVE */ - -/**@}*/ - -#if DEVICE_I2C_ASYNCH - -/** - * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer - * @{ - */ - -/** -* \internal -* Callback for transfer finish. -* -* \param[in,out] module Pointer to SPI software instance struct -*/ -void i2c_transfer_complete_callback(struct i2c_master_module *const module) -{ - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - - if (sercom_index >= SERCOM_INST_NUM) { - /* TODO: Abort operation */ - return; - } - - i2c_t *obj = (i2c_t*)i2c_instances[sercom_index]; - - i2c_master_disable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_WRITE_COMPLETE); - i2c_master_disable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_READ_COMPLETE); - i2c_master_disable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_ERROR); - - /* Call the handler function */ - if (pI2C_S(obj)->handler) { - ((I2CHandler)pI2C_S(obj)->handler)(); - } -} - -/** -* \internal -* Callback for write complete. Initiate read from here. -* -* \param[in,out] module Pointer to SPI software instance struct -*/ -void i2c_write_complete_callback(struct i2c_master_module *const module) -{ - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - - if (sercom_index >= SERCOM_INST_NUM) { - /* TODO: Abort operation */ - return; - } - - i2c_t *obj = (i2c_t*)i2c_instances[sercom_index]; - - if (!(pI2C_S(obj)->rd_packet.data) || (pI2C_S(obj)->rd_packet.data_length == 0)) { - /* Call the handler function */ - i2c_transfer_complete_callback(module); - } else { - i2c_master_disable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_WRITE_COMPLETE); - - /* Register read complete callback */ - i2c_master_register_callback(&pI2C_S(obj)->master, i2c_transfer_complete_callback, I2C_MASTER_CALLBACK_READ_COMPLETE); - i2c_master_enable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_READ_COMPLETE); - - /* Initiate read operation */ - if (pI2C_S(obj)->master.send_stop) { - i2c_master_read_packet_job(&pI2C_S(obj)->master,&pI2C_S(obj)->rd_packet); - } else { - i2c_master_read_packet_job_no_stop(&pI2C_S(obj)->master, &pI2C_S(obj)->rd_packet); - } - } -} - -/** Start i2c asynchronous transfer. - * @param obj The I2C object - * @param tx The buffer to send - * @param tx_length The number of words to transmit - * @param rx The buffer to receive - * @param rx_length The number of words to receive - * @param address The address to be set - 7bit or 9 bit - * @param stop If true, stop will be generated after the transfer is done - * @param handler The I2C IRQ handler to be set - * @param hint DMA hint usage - */ -void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - /* Return if in Slave mode */ - if (pI2C_S(obj)->mode != I2C_MODE_MASTER) return; - - uint32_t sercom_index = _sercom_get_sercom_inst_index(pI2C_S(obj)->master.hw); - - /* Init i2c packet. */ - pI2C_S(obj)->wr_packet.address = address >> 1; - pI2C_S(obj)->wr_packet.data_length = tx_length; - pI2C_S(obj)->wr_packet.data = (uint8_t *)tx; - - pI2C_S(obj)->rd_packet.address = address >> 1; - pI2C_S(obj)->rd_packet.data_length = rx_length; - pI2C_S(obj)->rd_packet.data = rx; - - /* Save event mask and handler function pointer */ - pI2C_S(obj)->events = event; - pI2C_S(obj)->handler = handler; - - /* TODO: Current implementation is interrupt based only */ - - /* Set interrupt handler to default handler of ASF */ - /* Enable interrupt */ - NVIC_SetVector((IRQn_Type)((uint32_t)SERCOM0_IRQn + sercom_index), sercom_irq_handlers[sercom_index]); - NVIC_EnableIRQ((IRQn_Type)((uint32_t)SERCOM0_IRQn + sercom_index)); - - /* Register callbacks */ - i2c_master_register_callback(&pI2C_S(obj)->master, i2c_transfer_complete_callback, I2C_MASTER_CALLBACK_ERROR); - i2c_master_enable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_ERROR); - if (tx && tx_length) { - i2c_master_register_callback(&pI2C_S(obj)->master, i2c_write_complete_callback, I2C_MASTER_CALLBACK_WRITE_COMPLETE); - i2c_master_enable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_WRITE_COMPLETE); - - /* Start I2C write */ - if (stop) { - i2c_master_write_packet_job(&pI2C_S(obj)->master, &pI2C_S(obj)->wr_packet); - } else { - i2c_master_write_packet_job_no_stop(&pI2C_S(obj)->master, &pI2C_S(obj)->wr_packet); - } - } else if (rx && rx_length) { - i2c_master_register_callback(&pI2C_S(obj)->master, i2c_transfer_complete_callback, I2C_MASTER_CALLBACK_READ_COMPLETE); - i2c_master_enable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_READ_COMPLETE); - - /* Start I2C read */ - if (stop) { - i2c_master_read_packet_job(&pI2C_S(obj)->master,&pI2C_S(obj)->rd_packet); - } else { - i2c_master_read_packet_job_no_stop(&pI2C_S(obj)->master, &pI2C_S(obj)->rd_packet); - } - } else { - /* Nothing to transfer, invoke callback */ - i2c_transfer_complete_callback(&pI2C_S(obj)->master); - } -} - -/** The asynchronous IRQ handler - * @param obj The I2C object which holds the transfer information - * @return event flags if a transfer termination condition was met or 0 otherwise. - */ -uint32_t i2c_irq_handler_asynch(i2c_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - uint32_t event_mask = pI2C_S(obj)->events; - - /* TODO: Current implementation is interrupt based only */ - - switch (pI2C_S(obj)->master.status) { - case STATUS_OK: - /* Transfer is complete */ - return (I2C_EVENT_TRANSFER_COMPLETE & event_mask); - - case STATUS_ERR_BAD_ADDRESS: - /* Received a NACK */ - return (I2C_EVENT_ERROR_NO_SLAVE & event_mask); - - case STATUS_ERR_PACKET_COLLISION: - /* An error occurred in between transfer */ - return (I2C_EVENT_ERROR & event_mask); - - default: - return 0; - } - - //return 0; -} - -/** Attempts to determine if I2C peripheral is already in use. - * @param obj The I2C object - * @return non-zero if the I2C module is active or zero if it is not - */ -uint8_t i2c_active(i2c_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - return (pI2C_S(obj)->master.status == STATUS_BUSY); -} - -/** Abort ongoing asynchronous transaction. - * @param obj The I2C object - */ -void i2c_abort_asynch(i2c_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(pI2C_S(obj)->master.hw); - - /* Pointer to the hardware module instance */ - SercomI2cm *const i2c_module = &(pI2C_S(obj)->master.hw->I2CM); - - /* Abort ongoing job */ - - /* Stop packet operation */ - i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB; - - pI2C_S(obj)->master.buffer_length = 0; - pI2C_S(obj)->master.buffer_remaining = 0; - - /* Send nack and stop command unless arbitration is lost */ - if ((pI2C_S(obj)->master.status != STATUS_ERR_PACKET_COLLISION) && pI2C_S(obj)->master.send_stop) { - _i2c_master_wait_for_sync(&pI2C_S(obj)->master); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT | SERCOM_I2CM_CTRLB_CMD(3); - } - - /* Disable any registered callback */ - i2c_master_disable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_WRITE_COMPLETE); - i2c_master_disable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_READ_COMPLETE); - i2c_master_disable_callback(&pI2C_S(obj)->master, I2C_MASTER_CALLBACK_ERROR); - - pI2C_S(obj)->master.status = STATUS_ABORTED; -} - -#endif - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/objects.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/objects.h deleted file mode 100644 index 01ac3f6796a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/objects.h +++ /dev/null @@ -1,132 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "gpio_object.h" -#include "tc.h" -#include "tcc.h" -#include "adc.h" -#include "extint.h" -#include "i2c_master.h" -#include "i2c_slave.h" -#include "dma_api.h" - -#if DEVICE_ANALOGOUT -#include "dac.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint8_t irqmask; - uint32_t port; - uint32_t pin; - uint32_t ch; - struct extint_chan_conf config_extint_chan; -}; - -struct port_s { - __IO uint32_t *OUTCLR; - __IO uint32_t *OUTSET; - __I uint32_t *IN; - __I uint32_t *OUT; - - PortName port; - uint32_t mask; - uint8_t powersave; - uint8_t mode; - uint8_t direction; -}; - -struct serial_s { - Sercom *usart; - uint32_t index; - uint32_t parity; - uint32_t stopbits; - uint32_t character_size; - uint32_t mux_setting; - uint32_t baudrate; - PinName pins[4]; -#if DEVICE_SERIAL_ASYNCH - uint32_t events; -#endif -}; - -struct analogin_s { - ADCName adc; - struct adc_config config_adc; -}; - -#if DEVICE_ANALOGOUT -struct dac_s { - DACName dac; - PinName pin; - uint32_t channel; - struct dac_module dac_instance; -}; -#endif - -struct pwmout_s { - struct tcc_module tcc; - PinName pin; - uint32_t period; - float duty_cycle; - double us_per_cycle; - enum gclk_generator clock_source; - enum tc_clock_prescaler clock_prescaler; -}; - -struct i2c_s { - struct i2c_master_module master; - struct i2c_slave_module slave; - uint8_t mode; - uint32_t baud_rate; - uint32_t baud_rate_high_speed; - uint8_t start_pending; - PinName pins[2]; -#if DEVICE_I2C_ASYNCH - uint32_t events; - uint32_t handler; - struct i2c_master_packet wr_packet; - struct i2c_master_packet rd_packet; -#endif -}; - -struct spi_s { - Sercom *spi; - uint8_t mode; - PinName pins[4]; -#if DEVICE_SPI_ASYNCH - uint8_t status; - uint32_t mask; - uint32_t event; - void *tx_buffer; - void *rx_buffer; - uint8_t dma_usage; -#endif -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap.c deleted file mode 100644 index f2b7627be49..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap.c +++ /dev/null @@ -1,106 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "cmsis.h" -#include "mbed_assert.h" -#include "compiler.h" - -#include "pinmux.h" -#include "pinmap.h" - -extern uint8_t g_sys_init; - - -static inline void pinmux_get_current_config(PinName pin, struct system_pinmux_config *const config) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t pin_index = pin % 32; - uint32_t pin_mask = (uint32_t)(1UL << pin_index); - - PortGroup *const port = system_pinmux_get_group_from_gpio_pin(pin); - MBED_ASSERT(port); - - config->mux_position = system_pinmux_pin_get_mux_position(pin); - - if (port->PINCFG[pin_index].reg & PORT_PINCFG_INEN) { - if (port->DIR.reg & pin_mask) { - config->direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - config->input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - } else { - config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - if (port->PINCFG[pin_index].reg & PORT_PINCFG_PULLEN) { - if (port->OUT.reg & pin_mask) { - config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - } else { - config->input_pull = SYSTEM_PINMUX_PIN_PULL_DOWN; - } - } else { - config->input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - } - } - } else { - config->input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - config->direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - } - - /* Not relevant for now */ - config->powersave = false; -} - -/** Change the MUX padding of input pin - * - * Configure the pin for specific module - * @param[in] pin Pin name whose MUX padding is to be changed - * @param[in] function The MUX mode to be selected - * @return void - */ -void pin_function(PinName pin, int function) -{ - MBED_ASSERT(pin != (PinName)NC); - - struct system_pinmux_config pin_conf; - - pinmux_get_current_config(pin, &pin_conf); - pin_conf.mux_position = function; - - system_pinmux_pin_set_config(pin, &pin_conf); -} - -/** Change the pin pull mode - * - * Configure the pin pull mode - * @param[in] pin Pin name whose MUX padding is to be changed - * @param[in] mode Pin pull mode to be set - * @return void - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - - struct system_pinmux_config pin_conf; - - pinmux_get_current_config(pin, &pin_conf); - if (mode == PullUp) { - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - } else if (mode == PullDown) { - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_DOWN; - } else { - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - } - - system_pinmux_pin_set_config(pin, &pin_conf); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.c deleted file mode 100644 index 49eddfefc89..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.c +++ /dev/null @@ -1,226 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "cmsis.h" -#include "mbed_assert.h" -#include "compiler.h" - -#include "pinmap_function.h" - -extern struct pwm_pin_channel pwn_pins[]; - -static uint32_t pinmap_merge_pins(uint32_t a, uint32_t b) -{ - /* both are the same (inc both NC) */ - if (a == b) - return a; - - /* one (or both) is not connected */ - if (a == (uint32_t)NC) - return b; - if (b == (uint32_t)NC) - return a; - - return (uint32_t)NC; -} - -/** Find the SERCOM peripheral of given pin - * - * Find and return the SERCOM peripheral of input pin, either from default pads, or from extended pads - * @param[in] pin1 First pin - * @param[in] pad_select to select which pad is to be used first to find - * @return SERCOM peripheral if found, else, NC - */ -uint32_t pinmap_find_peripheral_from_pad(PinName pin, enum sercom_pad_selection pad_select) -{ - uint32_t pin_sercom =(uint32_t)NC; - - if (pin == NC) return (uint32_t)NC; - - if (pad_select == SERCOM_USE_EXTENDED_PAD) { - pin_sercom = pinmap_find_peripheral(pin, PinMap_SERCOM_PADEx); - } - if (pin_sercom == (uint32_t)NC) { - pin_sercom = pinmap_find_peripheral(pin, PinMap_SERCOM_PAD); - } - - return pin_sercom; -} - -/** Find the common SERCOM shared by two pins - * - * Finds the common SERCOM index of two input pins. - * Currently uses default pad only - * @param[in] pin1 First pin - * @param[in] pin2 Second pin - * @return SERCOM index if found, else, NC - */ -uint32_t pinmap_merge_sercom(PinName pin1, PinName pin2) -{ - uint32_t pin1_sercom, pin2_sercom; - - /* Using default pads for now */ - pin1_sercom = pinmap_find_peripheral_from_pad(pin1, SERCOM_USE_DEFAULT_PAD); - if (pin1_sercom != (uint32_t)NC) { - pin1_sercom &= 0x0F; - } - pin2_sercom = pinmap_find_peripheral_from_pad(pin2, SERCOM_USE_DEFAULT_PAD); - if (pin2_sercom != (uint32_t)NC) { - pin2_sercom &= 0x0F; - } - - return pinmap_merge_pins(pin1_sercom, pin2_sercom); -} - -/** Find the common SERCOM shared by four pins - * - * Finds the common SERCOM index shared by four input pins. - * @param[in] pin1 First pin - * @param[in] pin2 Second pin - * @param[in] pin3 Third pin - * @param[in] pin4 Fourth pin - * @return SERCOM index if found, else, NC - */ -uint32_t pinmap_find_sercom(PinName pin1, PinName pin2, PinName pin3, PinName pin4) -{ - int i; - uint32_t sercom_index[4]; - uint32_t pin_com = (uint32_t)NC; - - sercom_index[0] = pinmap_find_peripheral_from_pad(pin1, SERCOM_USE_DEFAULT_PAD); - sercom_index[1] = pinmap_find_peripheral_from_pad(pin2, SERCOM_USE_DEFAULT_PAD); - sercom_index[2] = pinmap_find_peripheral_from_pad(pin3, SERCOM_USE_DEFAULT_PAD); - sercom_index[3] = pinmap_find_peripheral_from_pad(pin4, SERCOM_USE_DEFAULT_PAD); - - /* Find common SERCOM, if there are conflicts, return NC */ - for (i=0; i<4; i++) { - if (sercom_index[i] != (uint32_t)NC) { - if (pin_com == (uint32_t)NC) { - pin_com = sercom_index[i] & 0x0F; - } else if (pin_com != (sercom_index[i] & 0x0F)) { - return (uint32_t)NC; - } - } - } - - return pin_com; -} - -/** Find the MUX function of input pin specific to given SERCOM index - * - * @param[in] pin Pin whose function is to be found out - * @param[in] sercom_index SERCOM index - * @return MUX function if found, else, NC - */ -uint32_t pinmap_function_sercom(PinName pin, uint32_t sercom_index) -{ - uint32_t func = (uint32_t)NC; - uint32_t index; - sercom_index &= 0x0F; - - if ((pin == NC) || (sercom_index >= SERCOM_INST_NUM)) { - return (uint32_t)NC; - } - index = pinmap_peripheral(pin, PinMap_SERCOM_PAD); - if ((index & 0x0F) == sercom_index) { - func = pinmap_function(pin, PinMap_SERCOM_PAD); - return func; - } - index = pinmap_peripheral(pin, PinMap_SERCOM_PADEx); - if ((index & 0x0F) == sercom_index) { - func = pinmap_function(pin, PinMap_SERCOM_PADEx); - return func; - } - return (uint32_t)NC; -} - -/** Find the MUX pad of input pin specific to given SERCOM index - * - * @param[in] pin Pin whose function is to be found out - * @param[in] sercom_index SERCOM index - * @return MUX pad if found, else, NC - */ -uint32_t pinmap_pad_sercom(PinName pin, uint32_t sercom_index) -{ - uint32_t index; - sercom_index &= 0x0F; - - if ((pin == NC) || (sercom_index >= SERCOM_INST_NUM)) { - return (uint32_t)NC; - } - index = pinmap_peripheral(pin, PinMap_SERCOM_PAD); - if ((index & 0x0F) == sercom_index) { - return ((index >> 4) & 0x0F); - } - index = pinmap_peripheral(pin, PinMap_SERCOM_PADEx); - if ((index & 0x0F) == sercom_index) { - return ((index >> 4) & 0x0F); - } - return (uint32_t)NC; -} - -/** Find the MUX function of input pin specific to given SERCOM index - * - * @param[in] pin unused - * @param[in] sercom_index SERCOM index - * @return base address to SERCOM if found, else NC - */ -uint32_t pinmap_peripheral_sercom(PinName pin, uint32_t sercom_index) -{ - uint32_t sercom_address[6] = { -#if (SAMD21) || (SAMR21) - 0x42000800UL, // Base address of SERCOM0 - 0x42000C00UL, // Base address of SERCOM1 - 0x42001000UL, // Base address of SERCOM2 - 0x42001400UL, // Base address of SERCOM3 - 0x42001800UL, // Base address of SERCOM4 - 0x42001C00UL // Base address of SERCOM5 -#elif (SAML21) - 0x42000000UL, // Base address of SERCOM0 - 0x42000400UL, // Base address of SERCOM1 - 0x42000800UL, // Base address of SERCOM2 - 0x42000C00UL, // Base address of SERCOM3 - 0x42001000UL, // Base address of SERCOM4 - 0x43000400UL // Base address of SERCOM5 -#endif - }; - uint32_t index = sercom_index & 0x0F; - - if (index >= SERCOM_INST_NUM) { - return (uint32_t)NC; - } - return sercom_address[(sercom_index&0x0F)]; -} - -/** Find the channel index of a pin specific to a PWM instance - * - * @param[in] pin pin name - * @param[in] pwm pwm peripheral (unused now) - * @return Channel index of the specified pin - */ -uint32_t pinmap_channel_pwm(PinName pin, PWMName pwm) -{ - struct pwm_pin_channel *pwm_ch = pwn_pins; - - while (pwm_ch->pin != NC) { - if (pin == pwm_ch->pin) { - return (uint32_t)pwm_ch->channel_index; - } - pwm_ch++; - } - return (uint32_t)NC; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.h deleted file mode 100644 index 4660b8d83a8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.h +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PINMAP_FUNCTION_H -#define PINMAP_FUNCTION_H - -#include -#include "cmsis.h" -#include "PinNames.h" -#include "pinmux.h" -#include "pinmap.h" - -#include "PeripheralPins.h" - -#ifdef __cplusplus -extern "C" { -#endif - -enum sercom_pad_selection { - SERCOM_USE_DEFAULT_PAD, - SERCOM_USE_EXTENDED_PAD, -}; - -/** Find the SERCOM peripheral of given pin - * - * Find and return the SERCOM peripheral of input pin, either from default pas, or from extended pads - * @param[in] pin1 First pin - * @param[in] pad_select Second pin - * @return SERCOM peripheral if found, else, NC - */ -uint32_t pinmap_find_peripheral_from_pad(PinName pin, enum sercom_pad_selection pad_select); - -/** Find the common SERCOM shared by two pins - * - * Finds the common SERCOM index of two input pins. - * If swapping the input argument gives different result, it means, two SERCOMs share both pins - * @param[in] pin1 First pin - * @param[in] pin2 Second pin - * @return SERCOM index if found, else, NC - */ -uint32_t pinmap_merge_sercom(PinName pin1, PinName pin2); - -/** Find the common SERCOM shared by four pins - * - * Finds the common SERCOM index shared by four input pins. - * If reversing the input argument order gives different result, it means, two SERCOMs share the pins - * @param[in] pin1 First pin - * @param[in] pin2 Second pin - * @param[in] pin3 Third pin - * @param[in] pin4 Fourth pin - * @return SERCOM index if found, else, NC - */ -uint32_t pinmap_find_sercom(PinName pin1, PinName pin2, PinName pin3, PinName pin4); - -/** Find the MUX function of input pin specific to given SERCOM index - * - * @param[in] pin Pin whose function is to be found out - * @param[in] sercom_index SERCOM index - * @return MUX function if found, else, NC - */ -uint32_t pinmap_function_sercom(PinName pin, uint32_t sercom_index); - -/** Find the MUX pad of input pin specific to given SERCOM index - * - * @param[in] pin Pin whose function is to be found out - * @param[in] sercom_index SERCOM index - * @return MUX pad if found, else, NC - */ -uint32_t pinmap_pad_sercom(PinName pin, uint32_t sercom_index); - -/** Find the MUX function of input pin specific to given SERCOM index - * - * @param[in] pin unused - * @param[in] sercom_index SERCOM index - * @return base address to SERCOM if found, else NC - */ -uint32_t pinmap_peripheral_sercom(PinName pin, uint32_t sercom_index); - -/** Find the channel index of a pin specific to a PWM instance - * - * @param[in] pin pin name - * @param[in] pwm pwm peripheral (unused now) - * @return Channel index of the specified pin - */ -uint32_t pinmap_channel_pwm(PinName pin, PWMName pwm); - -#ifdef __cplusplus -} -#endif - -#endif /* PINMAP_FUNCTION_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/port_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/port_api.c deleted file mode 100644 index af190708b16..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/port_api.c +++ /dev/null @@ -1,180 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "port.h" - - -#if defined(TARGET_SAMR21G18A) -#define PORTA_MASK 0xDBDFFFF3 // mask for available pins in Port A -#define PORTB_MASK 0xC0C3C30D // mask for available pins in Port B -#define PORTC_MASK 0x000D0000 // mask for available pins in Port C -#elif defined(TARGET_SAMD21J18A) -#define PORTA_MASK 0xDBFFFFFF // mask for available pins in Port A -#define PORTB_MASK 0xC0C3FFFF // mask for available pins in Port B -#elif defined(TARGET_SAMD21G18A) -#define PORTA_MASK 0xDBFFFFFF // mask for available pins in Port A -#define PORTB_MASK 0x00C00F0C // mask for available pins in Port B -#elif defined(TARGET_SAML21J18A) -#define PORTA_MASK 0xCBFFFFFF // mask for available pins in Port A -#define PORTB_MASK 0xC0C3FFFF // mask for available pins in Port B -#else -#endif - -uint32_t start_pin(PortName port) -{ - if(port < PortMax) { /* PortC value is 2*/ - return port * 32; - } else { - return (uint32_t)NC; - } -} -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - MBED_ASSERT(obj); - struct port_config pin_conf; - int i, j; - int start; - - port_get_config_defaults(&pin_conf); - switch (dir) { - case PIN_INPUT : - pin_conf.direction = PORT_PIN_DIR_INPUT; - break; - case PIN_OUTPUT: - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - break; - case PIN_INPUT_OUTPUT: - pin_conf.direction = PORT_PIN_DIR_OUTPUT_WTH_READBACK; - break; - default: - return; - } - - PortGroup *const port_base = (PortGroup*)port_get_group_from_gpio_pin(port * 32); // 32 pins in port // function reused to get the port base - if(port_base == NULL) return; /* returns NULL if invalid*/ - switch (port) { - case PortA: - obj->mask = (uint32_t)mask & PORTA_MASK; - break; - case PortB: - obj->mask = (uint32_t)mask & PORTB_MASK; - break; -#if defined(TARGET_SAMR21G18A) - case PortC: - obj->mask = (uint32_t)mask & PORTC_MASK; - break; -#endif - default: - return; - } - start = start_pin(port); - if(start == NC) - return; - obj->port = port; - obj->direction = dir; - obj->powersave = pin_conf.powersave; - obj->mode = PORT_PIN_PULL_UP; - - for (i = start, j = 0; j < 32; i++, j++) { - if (obj->mask & (1<OUTCLR = &port_base->OUTCLR.reg; - obj->OUTSET = &port_base->OUTSET.reg; - obj->IN = &port_base->IN.reg; - obj->OUT = &port_base->OUT.reg; -} - -void port_mode(port_t *obj, PinMode mode) -{ - MBED_ASSERT(obj); - int i, j; - int start; - start = start_pin(obj->port); - if(start == NC) - return; - for (i = start, j = 0; j < 32; i++, j++) { - if (obj->mask & (1<port); - if(start == NC) - return; - obj->direction = dir; - pin_conf.input_pull = (enum port_pin_pull)obj->mode; - pin_conf.powersave = obj->powersave; - - for (i = start, j = 0; j < 32; i++, j++) { - if (obj->mask & (1<port); - if(start == NC) - return; - for (i = 0; i < 32 ; i++) { - if (obj->mask & (1<OUTSET = 1 << i; - } else { - *obj->OUTCLR = 1 << i; - } - } - } -} - -int port_read(port_t *obj) -{ - MBED_ASSERT(obj); - if (obj->direction == PIN_OUTPUT) { - return (*obj->OUT & obj->mask); - } else { - return (*obj->IN & obj->mask); - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pwmout_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pwmout_api.c deleted file mode 100644 index 0d286b37b6f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pwmout_api.c +++ /dev/null @@ -1,307 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" - -#include "cmsis.h" - -#include "pinmap_function.h" - -/* Prescaler values for TCC Module */ -const uint32_t tcc_prescaler[] = { - TCC_CLOCK_PRESCALER_DIV1, - TCC_CLOCK_PRESCALER_DIV2, - TCC_CLOCK_PRESCALER_DIV4, - TCC_CLOCK_PRESCALER_DIV8, - TCC_CLOCK_PRESCALER_DIV16, - TCC_CLOCK_PRESCALER_DIV64, - TCC_CLOCK_PRESCALER_DIV256, - TCC_CLOCK_PRESCALER_DIV1024 -}; - -/* Max count limits of TCC Modules */ -extern const uint32_t _tcc_maxs[TCC_INST_NUM]; - -/** Set the period of PWM object (will not update the waveform) - * - * @param[in] obj The PWM object whose period is to be updated - * @param[in] period_us Period in microseconds - * @return void - */ -static void pwmout_set_period(pwmout_t* obj, int period_us) -{ - uint8_t i; - uint32_t freq_hz; - uint32_t div_freq; - double us_per_cycle; - uint64_t max_period = 0; - uint32_t us_period = period_us; - - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* TCC instance index */ - uint8_t module_index = _tcc_get_inst_index(obj->tcc.hw); - - uint32_t count_max = _tcc_maxs[module_index]; - - freq_hz = system_gclk_gen_get_hz(obj->clock_source); - - for (i=0; i> tcc_prescaler[i]; - if (!div_freq) break; - us_per_cycle = 1000000.00 / div_freq; - max_period = us_per_cycle * count_max; - if (max_period >= us_period) { - obj->clock_prescaler = (enum tc_clock_prescaler)tcc_prescaler[i]; - obj->period = us_period / us_per_cycle; - obj->us_per_cycle = us_per_cycle; - break; - } - } -} - -/** Initialize PWM Module with updated values - * - * @param[in][out] obj The PWM object to initialize - * @return non-zero if success - */ -bool pwmout_init_hw(pwmout_t* obj) -{ - uint32_t mux_func = (uint32_t)NC; - uint32_t pwm = (uint32_t)NC; - PinName pin; - uint32_t ch_index = (uint32_t)NC; - struct tcc_config config_tcc; - uint32_t tcc_channel = (uint32_t)NC; - - /* Sanity check arguments */ - MBED_ASSERT(obj); - - pin = obj->pin; - pwm = pinmap_peripheral(pin, PinMap_PWM); - if (pwm == (uint32_t)NC) return 0; /* Pin not supported */ - - mux_func = pinmap_function(pin, PinMap_PWM); - ch_index = pinmap_channel_pwm(pin, (PWMName) pwm); - if ((mux_func == (uint32_t)NC) || (ch_index == (uint32_t)NC)) { - /* Pin not supported */ - return 0; - } - if ((ch_index == 0) || (ch_index == 4)) { - tcc_channel = 0; - } else if ((ch_index == 1) || (ch_index == 5)) { - tcc_channel = 1; - } else if ((ch_index == 2) || (ch_index == 6)) { - tcc_channel = 2; - } else if ((ch_index == 3) || (ch_index == 7)) { - tcc_channel = 3; - } - - tcc_get_config_defaults(&config_tcc, (Tcc*)pwm); - - config_tcc.counter.clock_source = obj->clock_source; - config_tcc.counter.clock_prescaler = (enum tcc_clock_prescaler)obj->clock_prescaler; - - config_tcc.counter.period = obj->period; - config_tcc.compare.wave_generation = TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM; - config_tcc.compare.match[tcc_channel] = obj->period * obj->duty_cycle; - - config_tcc.pins.enable_wave_out_pin[ch_index] = true; - config_tcc.pins.wave_out_pin[ch_index] = pin; - config_tcc.pins.wave_out_pin_mux[ch_index] = mux_func; - - return (STATUS_OK == tcc_init(&obj->tcc, (Tcc*)pwm, &config_tcc)); - -} - -/** Initialize PWM Module - * - * @param[in][out] obj The PWM object to initialize - * @return void - */ -void pwmout_init(pwmout_t* obj, PinName pin) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - if ((uint32_t)NC == pinmap_peripheral(pin, PinMap_PWM)) { - /* Pin not supported */ - return; - } - - obj->pin = pin; - obj->period = 0xFFFF; - obj->duty_cycle = 1; - obj->clock_source = GCLK_GENERATOR_0; /* 8Mhz input clock */ - obj->clock_prescaler = (enum tc_clock_prescaler)TCC_CLOCK_PRESCALER_DIV8; /* Default to 1MHz for 8Mhz input clock */ - - /* Update the changes */ - if (pwmout_init_hw(obj)) { - /* Enable PWM Module */ - tcc_enable(&obj->tcc); - } - -} - -/** Free the PWM Module - * - * @param[in] obj The PWM object to free - * @return void - */ -void pwmout_free(pwmout_t* obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - tcc_disable(&obj->tcc); -} - -/** Set the duty cycle of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] value New duty cycle to be set - * @return void - */ -void pwmout_write(pwmout_t* obj, float value) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - if (value < 0.0f) { - value = 0; - } else if (value > 1.0f) { - value = 1; - } - - /* Modify the pulse width keeping period same */ - obj->duty_cycle = value; - - /* Disable PWM Module */ - tcc_disable(&obj->tcc); - - /* Update the changes */ - if (pwmout_init_hw(obj)) { - /* Enable PWM Module */ - tcc_enable(&obj->tcc); - } -} - -/** Get the duty cycle of PWM Waveform - * - * @param[in] obj The PWM object - * @return Current duty cycle - */ -float pwmout_read(pwmout_t* obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - return obj->duty_cycle; -} - -/** Set the period of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] seconds New period in seconds - * @return void - */ -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -/** Set the period of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] value New period in milliseconds - * @return void - */ -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -/** Set the period of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] us New period in microseconds - * @return void - */ -void pwmout_period_us(pwmout_t* obj, int us) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Disable PWM Module */ - tcc_disable(&obj->tcc); - - /* TODO: Find and set the period */ - pwmout_set_period(obj, us); - - /* Update the changes */ - if (pwmout_init_hw(obj)) { - /* Enable PWM Module */ - tcc_enable(&obj->tcc); - } -} - -/** Set the pulse width of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] seconds New pulse width in seconds - * @return void - */ -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -/** Set the pulse width of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] ms New pulse width in milliseconds - * @return void - */ -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -/** Set the pulse width of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] us New pulse width in microseconds - * @return void - */ -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint32_t us_pulse = us; - - /* Find the new duty cycle */ - double duty_cycle = us_pulse / ((double)obj->period * obj->us_per_cycle); - - /* This call updates pulse width as well as period */ - pwmout_write(obj, duty_cycle); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/rtc_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/rtc_api.c deleted file mode 100644 index b7332fb688b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/rtc_api.c +++ /dev/null @@ -1,125 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "rtc_api.h" - -#include "cmsis.h" -#include "system.h" - -#include "rtc_count.h" - -#if !defined(RTC_CLOCK_SOURCE) -# warning RTC_CLOCK_SOURCE is not defined, assuming RTC_CLOCK_SELECTION_ULP1K. -# define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K -#endif - -/* Global RTC instance*/ -static struct rtc_module rtc_instance; - -static int rtc_inited = 0; - -/* Extern variables */ -extern uint8_t g_sys_init; - -/** Initialize the RTC - * - * Initialize the RTC with default time - * @param[void] void - */ -void rtc_init(void) -{ - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - - struct rtc_count_config config_rtc_count; - - rtc_count_get_config_defaults(&config_rtc_count); - - config_rtc_count.prescaler = RTC_COUNT_PRESCALER_DIV_1024; - config_rtc_count.mode = RTC_COUNT_MODE_32BIT; -#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED - config_rtc_count.continuously_update = true; -#endif - - rtc_count_init(&rtc_instance, RTC, &config_rtc_count); - - rtc_count_enable(&rtc_instance); - rtc_inited = 1; -} - -/** Frees the RTC - * - * @param[void] void - */ -void rtc_free(void) -{ - if (rtc_inited) { - /* Disable the RTC module */ - rtc_count_disable(&rtc_instance); - /* Disable the RTC clock */ -#if (SAMD21) || (SAMR21) - system_gclk_chan_disable(RTC_GCLK_ID); -#elif (SAML21) - system_gclk_chan_disable(RTC_CLOCK_SOURCE); -#endif - rtc_inited = 0; - } -} - -/** Checks whether RTC is enabled or not - * - * To check whether RTC module is enabled or not - * @param[void] void - * @return Non zero if RTC is already enabled, else zero - */ -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/** Reads the RTC value - * - * Reads and return the current time in RTC - * @param[void] void - * @return the current value in RTC - */ -time_t rtc_read(void) -{ - if (!rtc_inited) { - /* Return invalid time for now! */ - return 0; - } - return (time_t)rtc_count_get_count(&rtc_instance); -} - -/** Write the RTC value - * - * Update the time value in RTC - * @param[in] t The time value to be written - * @return void - */ -void rtc_write(time_t t) -{ - if (!rtc_inited) { - /* Initialize the RTC is not yet initialized */ - rtc_init(); - } - - uint32_t count_value = (uint32_t)t; - rtc_count_set_count(&rtc_instance, count_value); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.c deleted file mode 100644 index 7204e8197ce..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.c +++ /dev/null @@ -1,91 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" - -#include "cmsis.h" -#include "sercom.h" -#include "dma_api.h" -#include "dma_api_HAL.h" -#include "sercom_dma.h" - -static struct sercom_dma sercom_channels[SERCOM_INST_NUM] = {{0}}; - -/** Allocate a channel for TX - * - * @param[in] sercom_index index of sercom instance - * @param[out] tx_id pointer to channel id - * @return allocated channel id - */ -uint8_t sercom_setup_tx_channel(uint8_t sercom_index, uint8_t *tx_id) -{ - if (sercom_channels[sercom_index].tx_status & DMA_ALLOCATED) { - *tx_id = sercom_channels[sercom_index].tx_channel_id; - } else { - /* Try to allocate a channel */ - sercom_channels[sercom_index].tx_channel_id = dma_channel_allocate(DMA_CAP_NONE); - if (sercom_channels[sercom_index].tx_channel_id != (uint8_t)DMA_ERROR_OUT_OF_CHANNELS) { - *tx_id = sercom_channels[sercom_index].tx_channel_id; - sercom_channels[sercom_index].tx_status = DMA_ALLOCATED; - } else { - /* Couldn't find a channel */ - return (uint8_t)DMA_ERROR_OUT_OF_CHANNELS; - } - } - return *tx_id; -} - -/** Allocate a channel for RX - * - * @param[in] sercom_index index of sercom instance - * @param[out] rx_id pointer to channel id - * @return allocated channel id - */ -uint8_t sercom_setup_rx_channel(uint8_t sercom_index, uint8_t *rx_id) -{ - if (sercom_channels[sercom_index].rx_status & DMA_ALLOCATED) { - *rx_id = sercom_channels[sercom_index].rx_channel_id; - } else { - /* Try to allocate a channel */ - sercom_channels[sercom_index].rx_channel_id = dma_channel_allocate(DMA_CAP_NONE); - if (sercom_channels[sercom_index].rx_channel_id != (uint8_t)DMA_ERROR_OUT_OF_CHANNELS) { - *rx_id = sercom_channels[sercom_index].rx_channel_id; - sercom_channels[sercom_index].rx_status = DMA_ALLOCATED; - } else { - /* Couldn't find a channel */ - return (uint8_t)DMA_ERROR_OUT_OF_CHANNELS; - } - } - return *rx_id; -} - -/** Release DMA channels if allocated - * - * @param[in] sercom_index index of sercom instance - * @return void - */ -void sercom_release_channel(uint8_t sercom_index) -{ - if (sercom_channels[sercom_index].rx_status & DMA_ALLOCATED) { - if (0 == dma_channel_free(sercom_channels[sercom_index].rx_channel_id)) { - sercom_channels[sercom_index].rx_status = DMA_NOT_USED; - } - } - if (sercom_channels[sercom_index].tx_status & DMA_ALLOCATED) { - if (0 == dma_channel_free(sercom_channels[sercom_index].tx_channel_id)) { - sercom_channels[sercom_index].tx_status = DMA_NOT_USED; - } - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.h deleted file mode 100644 index e9f86f2603b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.h +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _SERCOM_DMA_H -#define _SERCOM_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "dma.h" - - -struct sercom_dma { - uint8_t tx_channel_id; - uint8_t rx_channel_id; - enum dma_status_flags tx_status; - enum dma_status_flags rx_status; -}; - -/** Allocate a channel for TX - * - * @param[in] sercom_index index of sercom instance - * @param[out] tx_id pointer to channel id - * @return allocated channel id - */ -uint8_t sercom_setup_tx_channel(uint8_t sercom_index, uint8_t *tx_id); - -/** Allocate a channel for RX - * - * @param[in] sercom_index index of sercom instance - * @param[out] rx_id pointer to channel id - * @return allocated channel id - */ -uint8_t sercom_setup_rx_channel(uint8_t sercom_index, uint8_t *rx_id); - -/** Release DMA channels if allocated - * - * @param[in] sercom_index index of sercom instance - * @return void - */ -void sercom_release_channel(uint8_t sercom_index); - -#ifdef __cplusplus -} -#endif - -#endif /* _SERCOM_DMA_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c deleted file mode 100644 index 18666306201..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c +++ /dev/null @@ -1,1110 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "mbed_assert.h" -#include "cmsis.h" -#include "serial_api.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "usart.h" -#include "pinmap_function.h" - -#define USART_TX_INDEX 0 -#define USART_RX_INDEX 1 -#define USART_RXFLOW_INDEX 2 -#define USART_TXFLOW_INDEX 3 - - -#if DEVICE_SERIAL_ASYNCH -#define pUSART_S(obj) obj->serial.usart -#define pSERIAL_S(obj) ((struct serial_s*)&(obj->serial)) -#else -#define pUSART_S(obj) obj->usart -#define pSERIAL_S(obj) ((struct serial_s*)obj) -#endif -#define _USART(obj) pUSART_S(obj)->USART -#define USART_NUM 6 -#define SUPPRESS_WARNING(a) (void)a - -uint8_t serial_get_index(serial_t *obj); -IRQn_Type get_serial_irq_num (serial_t *obj); -uint32_t get_serial_vector (serial_t *obj); -void uart0_irq(void); -void uart1_irq(void); -void uart2_irq(void); -void uart3_irq(void); -void uart4_irq(void); -void uart5_irq(void); - -static uint32_t serial_irq_ids[USART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -extern uint8_t g_sys_init; - -static inline void usart_syncing(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); -#ifdef FEATURE_USART_SYNC_SCHEME_V2 - while(_USART(obj).SYNCBUSY.reg); -#else - while(_USART(obj).SYNCBUSY.reg & SERCOM_USART_STATUS_SYNCBUSY); -#endif -} - -static inline void enable_usart(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /* Enable USART module */ - _USART(obj).CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; -} - -static inline void disable_usart(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /* Disable USART module */ - _USART(obj).CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; -} - -static inline void reset_usart(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - disable_usart(obj); - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /* Reset module */ - _USART(obj).CTRLA.reg = SERCOM_USART_CTRLA_SWRST; - SUPPRESS_WARNING(reset_usart); -} - -uint32_t serial_find_mux_settings (serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t mux_setting = 0; - uint32_t pinpad[4] = {0}; - uint8_t i = 0; - uint32_t sercom_index = pinmap_merge_sercom(pSERIAL_S(obj)->pins[0], pSERIAL_S(obj)->pins[1]); - - for (i = 0; i < 4 ; i++) { - pinpad[i] = pinmap_pad_sercom(pSERIAL_S(obj)->pins[i], sercom_index); - } - - switch(pinpad[USART_RX_INDEX]) { - case 0: - mux_setting |= SERCOM_USART_CTRLA_RXPO(0); - break; - case 1: - mux_setting |= SERCOM_USART_CTRLA_RXPO(1); - break; - case 2: - mux_setting |= SERCOM_USART_CTRLA_RXPO(2); - break; - case 3: - mux_setting |= SERCOM_USART_CTRLA_RXPO(3); - break; - } - - if ((pSERIAL_S(obj)->pins[USART_RXFLOW_INDEX] == NC) && (pSERIAL_S(obj)->pins[USART_TXFLOW_INDEX] == NC)) { - if (pinpad[USART_TX_INDEX] == 0) { - mux_setting |= SERCOM_USART_CTRLA_TXPO(0); - } else if(pinpad[USART_TX_INDEX] == 2) { - mux_setting |= SERCOM_USART_CTRLA_TXPO(1); - } else { - } - } else { // for hardware flow control and uart // expecting the tx in pad 0, rts in pad2 and cts in pad 3 - if((pinpad[USART_TX_INDEX] == 0) && (pinpad[USART_RXFLOW_INDEX]/*rts pin*/ == 2) && (pinpad[USART_TXFLOW_INDEX] /*cts pin*/ == 3)) { - mux_setting |= SERCOM_USART_CTRLA_TXPO(2); - } - } - return mux_setting; -} - -static enum status_code usart_set_config_default(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - /* Index for generic clock */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj)); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - - /* Cache new register values to minimize the number of register writes */ - uint32_t ctrla = 0; - uint32_t ctrlb = 0; - uint16_t baud = 0; - - enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - - /* Set data order, internal muxing, and clock polarity */ - ctrla = (uint32_t)USART_DATAORDER_LSB | // data order - (uint32_t)pSERIAL_S(obj)->mux_setting; // mux setting // clock polarity is not used - - - /* Get baud value from mode and clock */ - _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate,system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); // for asynchronous transfer mode - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /*Set baud val */ - _USART(obj).BAUD.reg = baud; - - /* Set sample mode */ - ctrla |= USART_TRANSFER_ASYNCHRONOUSLY; - - /* for disabled external clock source */ - ctrla |= SERCOM_USART_CTRLA_MODE(0x1); - - /* Set stopbits, character size and enable transceivers */ - ctrlb = (uint32_t)pSERIAL_S(obj)->stopbits | (uint32_t)pSERIAL_S(obj)->character_size | - SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN; /*transmitter and receiver enable*/ - if (pSERIAL_S(obj)->pins[USART_RX_INDEX] == NC) { /* if pin is NC, have to disable the corresponding transmitter/receiver part */ - ctrlb &= ~SERCOM_USART_CTRLB_RXEN; /* receiver disable */ - } - if (pSERIAL_S(obj)->pins[USART_TX_INDEX] == NC) { - ctrlb &= ~SERCOM_USART_CTRLB_TXEN; /* transmitter disable */ - } - - /* Check parity mode bits */ - if (pSERIAL_S(obj)->parity != USART_PARITY_NONE) { - ctrla |= SERCOM_USART_CTRLA_FORM(1); - ctrlb |= pSERIAL_S(obj)->parity; - } else { - ctrla |= SERCOM_USART_CTRLA_FORM(0); - } - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /* Write configuration to CTRLB */ - _USART(obj).CTRLB.reg = ctrlb; - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /* Write configuration to CTRLA */ - _USART(obj).CTRLA.reg = ctrla; - - return STATUS_OK; -} - -void get_default_serial_values(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - /* Set default config to object */ - pSERIAL_S(obj)->parity = USART_PARITY_NONE; - pSERIAL_S(obj)->stopbits = USART_STOPBITS_1; - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT; - pSERIAL_S(obj)->baudrate = 9600; - pSERIAL_S(obj)->mux_setting = USART_RX_1_TX_2_XCK_3; -}; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - struct system_gclk_chan_config gclk_chan_conf; - UARTName uart; - uint32_t gclk_index; - uint32_t pm_index; - uint32_t sercom_index = 0; - uint32_t muxsetting = 0; - - get_default_serial_values(obj); - - pSERIAL_S(obj)->pins[USART_TX_INDEX] = tx; - pSERIAL_S(obj)->pins[USART_RX_INDEX] = rx; - pSERIAL_S(obj)->pins[USART_RXFLOW_INDEX] = NC; - pSERIAL_S(obj)->pins[USART_TXFLOW_INDEX] = NC; - - muxsetting = serial_find_mux_settings(obj); // getting mux setting from pins - sercom_index = pinmap_merge_sercom(tx, rx); // same variable sercom_index reused for optimization - if (sercom_index == (uint32_t)NC) { - /*expecting a valid value for sercom index*/ - return; - } - sercom_index &= 0x0F; - uart = (UARTName)pinmap_peripheral_sercom(NC, sercom_index); - pUSART_S(obj) = (Sercom *)uart; - - /* Disable USART module */ - disable_usart(obj); - -#if (SAML21) || (SAMC20) || (SAMC21) -#if (SAML21) - if (sercom_index == 5) { - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#else - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_SWRST) { - return; /* The module is busy resetting itself */ - } - - if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) { - return; /* Check the module is enabled */ - } - - /* Turn on module in PM */ -#if (SAML21) - if (sercom_index == 5) { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - gclk_chan_conf.source_generator = GCLK_GENERATOR_0; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(GCLK_GENERATOR_0, false); - - pSERIAL_S(obj)->mux_setting = muxsetting; - /* Set configuration according to the config struct */ - usart_set_config_default(obj); - - struct system_pinmux_config pin_conf; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - pin_conf.powersave = false; - - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pin = pSERIAL_S(obj)->pins[pad]; - if (current_pin != (uint32_t)NC) { - pin_conf.mux_position = pinmap_function_sercom((PinName)current_pin, sercom_index); - if ((uint8_t)NC != pin_conf.mux_position) { - system_pinmux_pin_set_config(current_pin, &pin_conf); - } - } - } - - if (uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /* Enable USART module */ - enable_usart(obj); -} - -void serial_free(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - struct system_pinmux_config pin_conf; - serial_irq_ids[serial_get_index(obj)] = 0; - disable_usart(obj); - - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pin_conf.powersave = false; - pin_conf.mux_position = SYSTEM_PINMUX_GPIO; - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pin = pSERIAL_S(obj)->pins[pad]; - if (current_pin != (uint32_t)NC) { - system_pinmux_pin_set_config(current_pin, &pin_conf); - } - } -} - -void serial_baud(serial_t *obj, int baudrate) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT((baudrate == 110) || (baudrate == 150) || (baudrate == 300) || (baudrate == 1200) || - (baudrate == 2400) || (baudrate == 4800) || (baudrate == 9600) || (baudrate == 19200) || (baudrate == 38400) || - (baudrate == 57600) || (baudrate == 115200) || (baudrate == 230400) || (baudrate == 460800) || (baudrate == 921600) ); - - struct system_gclk_chan_config gclk_chan_conf; - uint32_t gclk_index; - uint16_t baud = 0; - uint32_t sercom_index = 0; - enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - - pSERIAL_S(obj)->baudrate = baudrate; - disable_usart(obj); - - sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj)); -#if (SAML21) || (SAMC20) || (SAMC21) -#if (SAML21) - if (sercom_index == 5) { - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#else - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif -#else - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - gclk_chan_conf.source_generator = GCLK_GENERATOR_0; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(GCLK_GENERATOR_0, false); - - /* Get baud value from mode and clock */ - _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /*Set baud val */ - _USART(obj).BAUD.reg = baud; - /* Wait until synchronization is complete */ - usart_syncing(obj); - - enable_usart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8) /*|| (data_bits == 9)*/); - - /* Cache new register values to minimize the number of register writes */ - uint32_t ctrla = 0; - uint32_t ctrlb = 0; - - disable_usart(obj); - - ctrla = _USART(obj).CTRLA.reg; - ctrlb = _USART(obj).CTRLB.reg; - - ctrla &= ~(SERCOM_USART_CTRLA_FORM_Msk); - ctrlb &= ~(SERCOM_USART_CTRLB_CHSIZE_Msk); - ctrlb &= ~(SERCOM_USART_CTRLB_SBMODE); - ctrlb &= ~(SERCOM_USART_CTRLB_PMODE); - - switch (stop_bits) { - case 1: - pSERIAL_S(obj)->stopbits = USART_STOPBITS_1; - break; - case 2: - pSERIAL_S(obj)->stopbits = USART_STOPBITS_2; - break; - default: - pSERIAL_S(obj)->stopbits = USART_STOPBITS_1; - } - - switch (parity) { - case ParityNone: - pSERIAL_S(obj)->parity = USART_PARITY_NONE; - break; - case ParityOdd: - pSERIAL_S(obj)->parity = USART_PARITY_ODD; - break; - case ParityEven: - pSERIAL_S(obj)->parity = USART_PARITY_EVEN; - break; - default: - pSERIAL_S(obj)->parity = USART_PARITY_NONE; - } - - switch (data_bits) { - case 5: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_5BIT; - break; - case 6: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_6BIT; - break; - case 7: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_7BIT; - break; - case 8: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT; - break; // 9 bit transfer not required in mbed - default: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT; - } - - - /* Set stopbits, character size and enable transceivers */ - ctrlb |= (pSERIAL_S(obj)->stopbits | pSERIAL_S(obj)->character_size); - - /* Check parity mode bits */ - if (pSERIAL_S(obj)->parity != USART_PARITY_NONE) { - ctrla |= SERCOM_USART_CTRLA_FORM(1); - ctrlb |= pSERIAL_S(obj)->parity; - } else { - ctrla |= SERCOM_USART_CTRLA_FORM(0); - } - - /* Write configuration to CTRLB */ - _USART(obj).CTRLB.reg = ctrlb; - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - /* Write configuration to CTRLA */ - _USART(obj).CTRLA.reg = ctrla; - - /* Wait until synchronization is complete */ - usart_syncing(obj); - - enable_usart(obj); -} - -#if DEVICE_SERIAL_FC - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t muxsetting = 0; - uint32_t sercom_index = 0; - - pSERIAL_S(obj)->pins[USART_RXFLOW_INDEX] = rxflow; - pSERIAL_S(obj)->pins[USART_TXFLOW_INDEX] = txflow; - muxsetting = serial_find_mux_settings(obj); // getting mux setting from pins - sercom_index = pinmap_merge_sercom(pSERIAL_S(obj)->pins[USART_TX_INDEX], pSERIAL_S(obj)->pins[USART_RX_INDEX]); // same variable sercom_index reused for optimization - if (sercom_index == (uint32_t)NC) { - /*expecting a valid value for sercom index*/ - return; - } - - disable_usart(obj); - - /* Set configuration according to the config struct */ - pSERIAL_S(obj)->mux_setting = muxsetting; // mux setting to be changed for configuring hardware control - usart_set_config_default(obj); - - struct system_pinmux_config pin_conf; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - pin_conf.powersave = false; - - for (uint8_t pad = 0; pad < 2; pad++) { // setting for rx and tx - uint32_t current_pin = pSERIAL_S(obj)->pins[pad]; - if (current_pin != (uint32_t)NC) { - pin_conf.mux_position = pinmap_function_sercom((PinName)current_pin, sercom_index); - if ((uint8_t)NC != pin_conf.mux_position) { - system_pinmux_pin_set_config(current_pin, &pin_conf); - } - } - } - if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) { - if (pSERIAL_S(obj)->pins[USART_RXFLOW_INDEX] != NC) { - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; // setting for rxflow - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pin_conf.mux_position = pinmap_function_sercom(pSERIAL_S(obj)->pins[USART_RXFLOW_INDEX] , sercom_index); - if ((uint8_t)NC != pin_conf.mux_position) { - system_pinmux_pin_set_config(pSERIAL_S(obj)->pins[USART_RXFLOW_INDEX], &pin_conf); - } - } - } - if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) { - if (pSERIAL_S(obj)->pins[USART_TXFLOW_INDEX] != NC) { - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; // setting for txflow - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pin_conf.mux_position = pinmap_function_sercom(pSERIAL_S(obj)->pins[USART_TXFLOW_INDEX] , sercom_index); - if ((uint8_t)NC != pin_conf.mux_position) { - system_pinmux_pin_set_config(pSERIAL_S(obj)->pins[USART_TXFLOW_INDEX], &pin_conf); - } - } - } - enable_usart(obj); -} - -#endif //DEVICE_SERIAL_FC - -void serial_break_set(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - struct system_pinmux_config pin_conf; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - pin_conf.mux_position = SYSTEM_PINMUX_GPIO; - pin_conf.powersave = false; - - if (pSERIAL_S(obj)->pins[USART_TX_INDEX] != NC) { - system_pinmux_pin_set_config(pSERIAL_S(obj)->pins[USART_TX_INDEX], &pin_conf); - } -} - -void serial_break_clear(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t sercom_index = pinmap_merge_sercom(pSERIAL_S(obj)->pins[USART_TX_INDEX], pSERIAL_S(obj)->pins[USART_RX_INDEX]); - - struct system_pinmux_config pin_conf; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - pin_conf.powersave = false; - - if (pSERIAL_S(obj)->pins[USART_TX_INDEX] != NC) { - pin_conf.mux_position = pinmap_function_sercom(pSERIAL_S(obj)->pins[USART_TX_INDEX], sercom_index); - if ((uint8_t)NC != pin_conf.mux_position) { - system_pinmux_pin_set_config(pSERIAL_S(obj)->pins[USART_TX_INDEX], &pin_conf); - } - } -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_SERCOM_PAD); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -inline uint8_t serial_get_index(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - switch ((int)pUSART_S(obj)) { - case UART_0: - return 0; - case UART_1: - return 1; - case UART_2: - return 2; - case UART_3: - return 3; - case UART_4: - return 4; - case UART_5: - return 5; - } - return 0; -} - -static inline void uart_irq(SercomUsart *const usart, uint32_t index) -{ - MBED_ASSERT(usart != (void*)0); - uint16_t interrupt_status; - interrupt_status = usart->INTFLAG.reg; - interrupt_status &= usart->INTENSET.reg; - - if (serial_irq_ids[index] != 0) { - if (interrupt_status & SERCOM_USART_INTFLAG_TXC) { // for transmit complete - usart->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; - if (irq_handler) { - irq_handler(serial_irq_ids[index], TxIrq); - } - } - if (interrupt_status & SERCOM_USART_INTFLAG_RXC) { // for receive complete - usart->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; - if (irq_handler) { - irq_handler(serial_irq_ids[index], RxIrq); - } - } - } -} - -void uart0_irq() -{ - uart_irq((SercomUsart *)UART_0, 0); -} - -void uart1_irq() -{ - uart_irq((SercomUsart *)UART_1, 1); -} - -void uart2_irq() -{ - uart_irq((SercomUsart *)UART_2, 2); -} - -void uart3_irq() -{ - uart_irq((SercomUsart *)UART_3, 3); -} - -void uart4_irq() -{ - uart_irq((SercomUsart *)UART_4, 4); -} - -void uart5_irq() -{ - uart_irq((SercomUsart *)UART_5, 5); -} - -uint32_t get_serial_vector (serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t vector = 0; - switch ((int)pUSART_S(obj)) { - case UART_0: - vector = (uint32_t)uart0_irq; - break; - case UART_1: - vector = (uint32_t)uart1_irq; - break; - case UART_2: - vector = (uint32_t)uart2_irq; - break; - case UART_3: - vector = (uint32_t)uart3_irq; - break; - case UART_4: - vector = (uint32_t)uart4_irq; - break; - case UART_5: - vector = (uint32_t)uart5_irq; - break; - } - return vector; -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - irq_handler = handler; - serial_irq_ids[serial_get_index(obj)] = id; -} - -IRQn_Type get_serial_irq_num (serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - switch ((int)pUSART_S(obj)) { - case UART_0: - return SERCOM0_IRQn; - case UART_1: - return SERCOM1_IRQn; - case UART_2: - return SERCOM2_IRQn; - case UART_3: - return SERCOM3_IRQn; - case UART_4: - return SERCOM4_IRQn; - case UART_5: - return SERCOM5_IRQn; - default: - MBED_ASSERT(0); - } - return SERCOM0_IRQn; // to avoid warning -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - vector = get_serial_vector(obj); - irq_n = get_serial_irq_num(obj); - - if (enable) { - switch (irq) { - case RxIrq: - _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_RXC; - break; - case TxIrq: - _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_TXC; - break; - } - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { - switch (irq) { - case RxIrq: - _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; - break; - case TxIrq: - _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; - break; - } - NVIC_DisableIRQ(irq_n); - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - while (!serial_readable(obj)); - return _USART(obj).DATA.reg ; -} - -void serial_putc(serial_t *obj, int c) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint16_t q = (c & SERCOM_USART_DATA_MASK); - while (!serial_writable(obj)); - _USART(obj).DATA.reg = q; - while (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)); // wait till data is sent -} - -int serial_readable(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t status = 1; - if (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) { - status = 0; - } else { - status = 1; - } - return status; -} - -int serial_writable(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t status = 1; - if (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) { - status = 0; - } else { - status = 1; - } - return status; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -/************************************************************************************ - * ASYNCHRONOUS HAL * - ************************************************************************************/ - -#if DEVICE_SERIAL_ASYNCH - -/************************************ - * HELPER FUNCTIONS * - ***********************************/ -void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - if(enable) { - pSERIAL_S(obj)->events |= event; - } else { - pSERIAL_S(obj)->events &= ~ event; - } -} - -void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - if(enable) { - pSERIAL_S(obj)->events |= event; - } else { - pSERIAL_S(obj)->events &= ~ event; - } -} - -void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(tx != (void*)0); - // We only support byte buffers for now - MBED_ASSERT(width == 8); - - if(serial_tx_active(obj)) return; - - obj->tx_buff.buffer = tx; - obj->tx_buff.length = tx_length; - obj->tx_buff.pos = 0; - - return; -} - -void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); - // We only support byte buffers for now - MBED_ASSERT(width == 8); - - if(serial_rx_active(obj)) return; - - obj->rx_buff.buffer = rx; - obj->rx_buff.length = rx_length; - obj->rx_buff.pos = 0; - - return; -} - -void serial_set_char_match(serial_t *obj, uint8_t char_match) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - if (char_match != SERIAL_RESERVED_CHAR_MATCH) { - obj->char_match = char_match; - } -} - -/************************************ - * TRANSFER FUNCTIONS * - ***********************************/ -int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(tx != (void*)0); - if(tx_length == 0) return 0; - - serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - serial_tx_enable_event(obj, event, true); - - NVIC_ClearPendingIRQ(get_serial_irq_num(obj)); - NVIC_DisableIRQ(get_serial_irq_num(obj)); - NVIC_SetVector(get_serial_irq_num(obj), (uint32_t)handler); - NVIC_EnableIRQ(get_serial_irq_num(obj)); - - if (pUSART_S(obj)) { - _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; - _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_DRE; - } - return 0; -} - -void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); - - serial_rx_enable_event(obj, SERIAL_EVENT_RX_ALL, false); - serial_rx_enable_event(obj, event, true); - serial_set_char_match(obj, char_match); - serial_rx_buffer_set(obj, rx, rx_length, rx_width); - - NVIC_ClearPendingIRQ(get_serial_irq_num(obj)); - NVIC_DisableIRQ(get_serial_irq_num(obj)); - NVIC_SetVector(get_serial_irq_num(obj), (uint32_t)handler); - NVIC_EnableIRQ(get_serial_irq_num(obj)); - - if (pUSART_S(obj)) { - _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_RXC; - } - return; -} - -uint8_t serial_tx_active(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - return ((obj->tx_buff.length > 0) ? true : false); -} - -uint8_t serial_rx_active(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - return ((obj->rx_buff.length > 0) ? true : false); -} - -int serial_tx_irq_handler_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; - serial_tx_abort_asynch(obj); - return SERIAL_EVENT_TX_COMPLETE & obj->serial.events; -} - -int serial_rx_irq_handler_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - int event = 0; - /* This interrupt handler is called from USART irq */ - uint8_t *buf = (uint8_t*)obj->rx_buff.buffer; - uint8_t error_code = 0; - uint16_t received_data = 0; - - error_code = (uint8_t)(_USART(obj).STATUS.reg & SERCOM_USART_STATUS_MASK); - /* Check if an error has occurred during the receiving */ - if (error_code) { - /* Check which error occurred */ - if (error_code & SERCOM_USART_STATUS_FERR) { - /* Store the error code and clear flag by writing 1 to it */ - _USART(obj).STATUS.reg |= SERCOM_USART_STATUS_FERR; - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_FRAMING_ERROR; - } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { - /* Store the error code and clear flag by writing 1 to it */ - _USART(obj).STATUS.reg |= SERCOM_USART_STATUS_BUFOVF; - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_OVERFLOW; - } else if (error_code & SERCOM_USART_STATUS_PERR) { - /* Store the error code and clear flag by writing 1 to it */ - _USART(obj).STATUS.reg |= SERCOM_USART_STATUS_PERR; - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_PARITY_ERROR; - } - } - - /* Read current packet from DATA register, - * increment buffer pointer and decrement buffer length */ - received_data = (_USART(obj).DATA.reg & SERCOM_USART_DATA_MASK); - - /* Read value will be at least 8-bits long */ - buf[obj->rx_buff.pos] = received_data; - /* Increment 8-bit pointer */ - obj->rx_buff.pos++; - - /* Check if the last character have been received */ - if(--(obj->rx_buff.length) == 0) { - event |= SERIAL_EVENT_RX_COMPLETE; - if((buf[obj->rx_buff.pos - 1] == obj->char_match) && (obj->serial.events & SERIAL_EVENT_RX_CHARACTER_MATCH)) { - event |= SERIAL_EVENT_RX_CHARACTER_MATCH; - } - _USART(obj).INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; - serial_rx_abort_asynch(obj); - return event & obj->serial.events; - } - - /* Check for character match event */ - if((buf[obj->rx_buff.pos - 1] == obj->char_match) && (obj->serial.events & SERIAL_EVENT_RX_CHARACTER_MATCH)) { - event |= SERIAL_EVENT_RX_CHARACTER_MATCH; - } - - /* Return to the call back if character match occured */ - if(event != 0) { - serial_rx_abort_asynch(obj); - return event & obj->serial.events; - } - return 0; -} - -int serial_irq_handler_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint16_t interrupt_status; - uint8_t *buf = obj->tx_buff.buffer; - - interrupt_status = _USART(obj).INTFLAG.reg; - interrupt_status &= _USART(obj).INTENSET.reg; - - if (pUSART_S(obj)) { - if (interrupt_status & SERCOM_USART_INTFLAG_DRE) { - /* Interrupt has another TX source */ - if(obj->tx_buff.pos >= obj->tx_buff.length) { - /* Transfer complete. Switch off interrupt and return event. */ - _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_TXC; - } else { - while((serial_writable(obj)) && (obj->tx_buff.pos <= (obj->tx_buff.length - 1))) { - _USART(obj).DATA.reg = buf[obj->tx_buff.pos]; - obj->tx_buff.pos++; - } - } - } - if (interrupt_status & SERCOM_USART_INTFLAG_TXC) { - return serial_tx_irq_handler_asynch(obj); - } - if (interrupt_status & SERCOM_USART_INTFLAG_RXC) { - return serial_rx_irq_handler_asynch(obj); - } - } - return 0; -} - -void serial_tx_abort_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - _USART(obj).INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; - _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; - obj->tx_buff.length = 0; - obj->rx_buff.pos = 0; - -} - -void serial_rx_abort_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - _USART(obj).INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; - _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; - obj->rx_buff.length = 0; - obj->rx_buff.pos = 0; -} - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sleep_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sleep_api.c deleted file mode 100644 index c6834311790..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sleep_api.c +++ /dev/null @@ -1,50 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "sleep_api.h" - -#include "power.h" - -/** Send the device to sleep - * - * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the - * system clock to the core is stopped until a reset or an interrupt occurs. - * @param[void] void - * @return void - */ -void hal_sleep(void) -{ -#if (SAMD21) || (SAMR21) - system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE_2); -#elif (SAML21) - system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE); -#endif - system_sleep(); -} - -/** Send the device to deep sleep - * - * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode - * has the same sleep features as sleep plus it powers down peripherals and clocks. All state - * is still maintained. - * @param[void] void - * @return void - */ -void hal_deepsleep(void) -{ - system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY); - system_sleep(); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c deleted file mode 100644 index 83b8ab8678c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c +++ /dev/null @@ -1,1056 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#include "cmsis.h" -#include "pinmap.h" -#include "sercom.h" - -#include "pinmap_function.h" - -#define SERCOM_SPI_STATUS_SYNCBUSY_Pos 15 -#define SERCOM_SPI_STATUS_SYNCBUSY (0x1u << SERCOM_SPI_STATUS_SYNCBUSY_Pos) - -#define SPI_MOSI_INDEX 0 -#define SPI_MISO_INDEX 1 -#define SPI_SCLK_INDEX 2 -#define SPI_SSEL_INDEX 3 - -/** - * \brief SPI modes enum - * - * SPI mode selection. - */ -enum spi_mode { - /** Master mode. */ - SPI_MODE_MASTER = 1, - /** Slave mode. */ - SPI_MODE_SLAVE = 0, -}; - -#if DEVICE_SPI_ASYNCH -#define pSPI_S(obj) (&obj->spi) -#define pSPI_SERCOM(obj) obj->spi.spi -#else -#define pSPI_S(obj) (obj) -#define pSPI_SERCOM(obj) (obj->spi) -#endif -#define _SPI(obj) pSPI_SERCOM(obj)->SPI - -/** SPI default baud rate. */ -#define SPI_DEFAULT_BAUD 100000 - - -/** SPI timeout value. */ -# define SPI_TIMEOUT 10000 - -extern uint8_t g_sys_init; -uint16_t dummy_fill_word = 0xFFFF; - - -static inline bool spi_is_syncing(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - -# ifdef FEATURE_SPI_SYNC_SCHEME_VERSION_2 - /* Return synchronization status */ - return (_SPI(obj).SYNCBUSY.reg); -# else - /* Return synchronization status */ - return (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY); -# endif -} - -static inline void spi_enable(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Wait until the synchronization is complete */ - while (spi_is_syncing(obj)); - - /* Enable SPI */ - _SPI(obj).CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; -} - -static inline void spi_disable(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Wait until the synchronization is complete */ - while (spi_is_syncing(obj)); - - /* Disable SPI */ - _SPI(obj).CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; -} - -static inline bool spi_is_write_complete(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check interrupt flag */ - return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC); -} - -static inline bool spi_is_ready_to_write(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check interrupt flag */ - return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE); -} - -static inline bool spi_is_ready_to_read(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check interrupt flag */ - return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC); -} - -static inline bool spi_write(spi_t *obj, uint16_t tx_data) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check if the data register has been copied to the shift register */ - if (!spi_is_ready_to_write(obj)) { - /* Data register has not been copied to the shift register, return */ - return false; - } - - /* Write the character to the DATA register */ - _SPI(obj).DATA.reg = tx_data & SERCOM_SPI_DATA_MASK; - - return true; -} - -static inline bool spi_read(spi_t *obj, uint16_t *rx_data) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check if data is ready to be read */ - if (!spi_is_ready_to_read(obj)) { - /* No data has been received, return */ - return false; - } - - /* Check if data is overflown */ - if (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) { - /* Clear overflow flag */ - _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; - } - - /* Read the character from the DATA register */ - if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { - *rx_data = (_SPI(obj).DATA.reg & SERCOM_SPI_DATA_MASK); - } else { - *rx_data = (uint8_t)_SPI(obj).DATA.reg; - } - - return true; -} - -static uint32_t spi_find_mux_settings(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint8_t i_dipo; - uint8_t i_dopo; - uint32_t dipo = 0; - uint32_t dopo = 0; - uint32_t mux_pad; - - uint32_t mux_settings = 0; - - uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); - - if (pSPI_S(obj)->mode == SPI_MODE_MASTER) { - i_dipo = SPI_MISO_INDEX; - i_dopo = SPI_MOSI_INDEX; - } else { - i_dipo = SPI_MOSI_INDEX; - i_dopo = SPI_MISO_INDEX; - } - - /* Find MUX setting */ - if (pSPI_S(obj)->pins[i_dipo] != NC) { - /* Set Data input MUX padding for master */ - mux_pad = pinmap_pad_sercom(pSPI_S(obj)->pins[i_dipo], sercom_index); - if (mux_pad != (uint32_t)NC) { - /* MUX pad value is same as DIPO value */ - dipo = mux_pad; - mux_settings |= ((dipo << SERCOM_SPI_CTRLA_DIPO_Pos) & SERCOM_SPI_CTRLA_DIPO_Msk); - } - } - - if (pSPI_S(obj)->pins[i_dopo] != NC) { - /* Set Data output MUX padding for master */ - mux_pad = pinmap_pad_sercom(pSPI_S(obj)->pins[i_dopo], sercom_index); - if (mux_pad != (uint32_t)NC) { - if (mux_pad != 0) { - dopo = mux_pad - 1; - } else { - if (3 == pinmap_pad_sercom(pSPI_S(obj)->pins[SPI_SCLK_INDEX], sercom_index)) { - dopo = 3; - } else { - dopo = 0; - } - } - mux_settings |= ((dopo << SERCOM_SPI_CTRLA_DOPO_Pos) & SERCOM_SPI_CTRLA_DOPO_Msk); - } - } - - return mux_settings; -} - -/** - * \defgroup GeneralSPI SPI Configuration Functions - * @{ - */ - -/** Initialize the SPI peripheral - * - * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral - * @param[out] obj The SPI object to initialize - * @param[in] mosi The pin to use for MOSI - * @param[in] miso The pin to use for MISO - * @param[in] sclk The pin to use for SCLK - * @param[in] ssel The pin to use for SSEL - */ -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(sclk != NC); - - uint16_t baud = 0; - uint32_t ctrla = 0; - uint32_t ctrlb = 0; - enum status_code error_code; - - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - - /* Calculate SERCOM instance from pins */ - uint32_t sercom_index = pinmap_find_sercom(mosi, miso, sclk, ssel); - pSPI_SERCOM(obj) = (Sercom*)pinmap_peripheral_sercom(NC, sercom_index); - - /* Disable SPI */ - spi_disable(obj); - - /* Check if reset is in progress. */ - if (_SPI(obj).CTRLA.reg & SERCOM_SPI_CTRLA_SWRST) { - return; - } - - uint32_t pm_index, gclk_index; -#if (SAML21) - if (sercom_index == 5) { -# ifdef ID_SERCOM5 - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; -# else - return STATUS_ERR_INVALID_ARG; -# endif - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#elif (SAMC21) - if (sercom_index == 5) { -# ifdef ID_SERCOM5 - pm_index = MCLK_APBCMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; -# else - return STATUS_ERR_INVALID_ARG; -# endif - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#elif (SAMC20) - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - /* Turn on module in PM */ -#if (SAML21) - if (sercom_index == 5) { -# ifdef ID_SERCOM5 - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); -# else - return STATUS_ERR_INVALID_ARG; -# endif - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = GCLK_GENERATOR_0; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(GCLK_GENERATOR_0, false); - - /* Set the SERCOM in SPI master mode */ - _SPI(obj).CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3); - pSPI_S(obj)->mode = SPI_MODE_MASTER; - - /* TODO: Do pin muxing here */ - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - - pSPI_S(obj)->pins[SPI_MOSI_INDEX] = mosi; - pSPI_S(obj)->pins[SPI_MISO_INDEX] = miso; - pSPI_S(obj)->pins[SPI_SCLK_INDEX] = sclk; - pSPI_S(obj)->pins[SPI_SSEL_INDEX] = ssel; - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pin = pSPI_S(obj)->pins[pad]; - if (current_pin != (uint32_t)NC) { - pin_conf.mux_position = pinmap_function_sercom((PinName)current_pin, sercom_index); - if ((uint8_t)NC != pin_conf.mux_position) { - system_pinmux_pin_set_config(current_pin, &pin_conf); - } - } - } - - /* Get baud value, based on baudrate and the internal clock frequency */ - uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); - //internal_clock = 8000000; - error_code = _sercom_get_sync_baud_val(SPI_DEFAULT_BAUD, internal_clock, &baud); - if (error_code != STATUS_OK) { - /* Baud rate calculation error */ - return; - } - _SPI(obj).BAUD.reg = (uint8_t)baud; - - /* TODO: Find MUX settings */ - ctrla |= spi_find_mux_settings(obj); - - /* Set SPI character size */ - ctrlb |= SERCOM_SPI_CTRLB_CHSIZE(0); - - /* Enable receiver */ - ctrlb |= SERCOM_SPI_CTRLB_RXEN; - - /* Write CTRLA register */ - _SPI(obj).CTRLA.reg |= ctrla; - - /* Write CTRLB register */ - _SPI(obj).CTRLB.reg |= ctrlb; - - /* Enable SPI */ - spi_enable(obj); -} - -/** Release a SPI object - * - * TODO: spi_free is currently unimplemented - * This will require reference counting at the C++ level to be safe - * - * Return the pins owned by the SPI object to their reset state - * Disable the SPI peripheral - * Disable the SPI clock - * @param[in] obj The SPI object to deinitialize - */ -void spi_free(spi_t *obj) -{ - // [TODO] -} - -/** Configure the SPI format - * - * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode - * @param[in,out] obj The SPI object to configure - * @param[in] bits The number of bits per frame - * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) - * @param[in] slave Zero for master mode or non-zero for slave mode - */ -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - PinMode pull_mode; - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Disable SPI */ - spi_disable(obj); - - - if (slave) { - /* Set the SERCOM in SPI mode */ - _SPI(obj).CTRLA.bit.MODE = 0x2; - pSPI_S(obj)->mode = SPI_MODE_SLAVE; - pull_mode = PullNone; - /* Enable PLOADEN to avoid sending dummy character by slave */ - _SPI(obj).CTRLB.bit.PLOADEN = 1; - } else { - /* Set the SERCOM in SPI mode */ - _SPI(obj).CTRLA.bit.MODE = 0x3; - pSPI_S(obj)->mode = SPI_MODE_MASTER; - pull_mode = PullUp; - } - - /* Change pull mode of pins */ - for (uint8_t pad = 0; pad < 4; pad++) { - if (pSPI_S(obj)->pins[pad] != NC) { - pin_mode(pSPI_S(obj)->pins[pad], pull_mode); - } - } - - /* Change MUX settings */ - uint32_t ctrla = _SPI(obj).CTRLA.reg; - ctrla &= ~(SERCOM_SPI_CTRLA_DIPO_Msk | SERCOM_SPI_CTRLA_DOPO_Msk); - ctrla |= spi_find_mux_settings(obj); - _SPI(obj).CTRLA.reg = ctrla; - - /* Set SPI Frame size - only 8-bit and 9-bit supported now */ - _SPI(obj).CTRLB.bit.CHSIZE = (bits > 8)? 1 : 0; - - /* Set SPI Clock Phase */ - _SPI(obj).CTRLA.bit.CPHA = (mode & 0x01)? 1 : 0; - - /* Set SPI Clock Polarity */ - _SPI(obj).CTRLA.bit.CPOL = (mode & 0x02)? 1 : 0; - - /* Enable SPI */ - spi_enable(obj); -} - -/** Set the SPI baud rate - * - * Actual frequency may differ from the desired frequency due to available dividers and bus clock - * Configures the SPI peripheral's baud rate - * @param[in,out] obj The SPI object to configure - * @param[in] hz The baud rate in Hz - */ -void spi_frequency(spi_t *obj, int hz) -{ - uint16_t baud = 0; - uint32_t gclk_index = 0; - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Disable SPI */ - spi_disable(obj); - - /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); -#if (SAML21) - if (sercom_index == 5) { -# ifdef ID_SERCOM5 - gclk_index = SERCOM5_GCLK_ID_CORE; -# else - return STATUS_ERR_INVALID_ARG; -# endif - } else { - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#elif (SAMC21) - if (sercom_index == 5) { -# ifdef ID_SERCOM5 - gclk_index = SERCOM5_GCLK_ID_CORE; -# else - return STATUS_ERR_INVALID_ARG; -# endif - } else { - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#elif (SAMC20) - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#else - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); - - /* Get baud value, based on baudrate and the internal clock frequency */ - enum status_code error_code = _sercom_get_sync_baud_val(hz, internal_clock, &baud); - - if (error_code != STATUS_OK) { - /* Baud rate calculation error, return status code */ - /* Enable SPI */ - spi_enable(obj); - return; - } - - _SPI(obj).BAUD.reg = (uint8_t)baud; - - /* Enable SPI */ - spi_enable(obj); -} - -/**@}*/ -/** - * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer - * @{ - */ - -/** Write a byte out in master mode and receive a value - * - * @param[in] obj The SPI peripheral to use for sending - * @param[in] value The value to send - * @return Returns the value received during send - */ -int spi_master_write(spi_t *obj, int value) -{ - uint16_t rx_data = 0; - - /* Sanity check arguments */ - MBED_ASSERT(obj); - -#if DEVICE_SPI_ASYNCH - if (obj->spi.status == STATUS_BUSY) { - /* Check if the SPI module is busy with a job */ - return 0; - } -#endif - - /* Wait until the module is ready to write the character */ - while (!spi_is_ready_to_write(obj)); - - /* Write data */ - spi_write(obj, value); - - if (!(_SPI(obj).CTRLB.bit.RXEN)) { - return 0; - } - - /* Wait until the module is ready to read the character */ - while (!spi_is_ready_to_read(obj)); - - /* Read data */ - spi_read(obj, &rx_data); - - return rx_data; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -/** Check if a value is available to read - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if a value is available - */ -int spi_slave_receive(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - return spi_is_ready_to_read(obj); -} - -/** Get a received value out of the SPI receive buffer in slave mode - * - * Blocks until a value is available - * @param[in] obj The SPI peripheral to read - * @return The value received - */ -int spi_slave_read(spi_t *obj) -{ - int i; - uint16_t rx_data = 0; - - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check for timeout period */ - for (i = 0; i < SPI_TIMEOUT; i++) { - if (spi_is_ready_to_read(obj)) { - break; - } - } - if (i == SPI_TIMEOUT) { - /* Not ready to read data within timeout period */ - return 0; - } - - /* Read data */ - spi_read(obj, &rx_data); - - return rx_data; -} - -/** Write a value to the SPI peripheral in slave mode - * - * Blocks until the SPI peripheral can be written to - * @param[in] obj The SPI peripheral to write - * @param[in] value The value to write - */ -void spi_slave_write(spi_t *obj, int value) -{ - int i; - - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check for timeout period */ - for (i = 0; i < SPI_TIMEOUT; i++) { - if (spi_is_ready_to_write(obj)) { - break; - } - } - if (i == SPI_TIMEOUT) { - /* Not ready to write data within timeout period */ - return; - } - - /* Write data */ - spi_write(obj, value); -} - -/** Checks if the specified SPI peripheral is in use - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if the peripheral is currently transmitting - */ -int spi_busy(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - return spi_is_write_complete(obj); -} - -/** Get the module number - * - * @param[in] obj The SPI peripheral to check - * @return The module number - */ -uint8_t spi_get_module(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - return _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SERCOM_PAD; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SERCOM_PAD; -} - - -#if DEVICE_SPI_ASYNCH -/** - * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer - * @{ - */ - - -/** - * \internal - * Writes a character from the TX buffer to the Data register. - * - * \param[in,out] module Pointer to SPI software instance struct - */ -static void _spi_write_async(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint16_t data_to_send; - uint8_t *tx_buffer = obj->tx_buff.buffer; - - /* Do nothing if we are at the end of buffer */ - if (obj->tx_buff.pos < obj->tx_buff.length) { - /* Write value will be at least 8-bits long */ - if (tx_buffer) { - data_to_send = tx_buffer[obj->tx_buff.pos]; - } else { - data_to_send = dummy_fill_word; - } - /* Increment 8-bit index */ - obj->tx_buff.pos++; - - if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { - if (tx_buffer) - data_to_send |= (tx_buffer[obj->tx_buff.pos] << 8); - /* Increment 8-bit index */ - obj->tx_buff.pos++; - } - } else { - /* Write a dummy packet */ - /* TODO: Current implementation do not enter this condition, remove if not needed */ - data_to_send = dummy_fill_word; - } - - /* Write the data to send*/ - _SPI(obj).DATA.reg = data_to_send & SERCOM_SPI_DATA_MASK; - - /* Check for error */ - if ((_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) && (obj->spi.mask & SPI_EVENT_ERROR)) { - obj->spi.event |= SPI_EVENT_ERROR; - } -} - -/** - * \internal - * Reads a character from the Data register to the RX buffer. - * - * \param[in,out] module Pointer to SPI software instance struct - */ -static void _spi_read_async(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint8_t *rx_buffer = obj->rx_buff.buffer; - - /* Check if data is overflown */ - if (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) { - /* Clear overflow flag */ - _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; - if (obj->spi.mask & SPI_EVENT_RX_OVERFLOW) { - /* Set overflow error */ - obj->spi.event |= SPI_EVENT_RX_OVERFLOW; - return; - } - } - - /* Read data, either valid, or dummy */ - uint16_t received_data = (_SPI(obj).DATA.reg & SERCOM_SPI_DATA_MASK); - - /* Do nothing if we are at the end of buffer */ - if ((obj->rx_buff.pos >= obj->rx_buff.length) && rx_buffer) { - return; - } - - /* Read value will be at least 8-bits long */ - rx_buffer[obj->rx_buff.pos] = received_data; - /* Increment 8-bit index */ - obj->rx_buff.pos++; - - if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { - /* 9-bit data, write next received byte to the buffer */ - rx_buffer[obj->rx_buff.pos] = (received_data >> 8); - /* Increment 8-bit index */ - obj->rx_buff.pos++; - } - - /* Check for error */ - if ((_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) && (obj->spi.mask & SPI_EVENT_ERROR)) { - obj->spi.event |= SPI_EVENT_ERROR; - } -} - -/** - * \internal - * Clears all interrupt flags of SPI - * - * \param[in,out] module Pointer to SPI software instance struct - */ -static void _spi_clear_interrupts(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); - - /* Clear all interrupts */ - _SPI(obj).INTENCLR.reg = - SERCOM_SPI_INTFLAG_DRE | - SERCOM_SPI_INTFLAG_TXC | - SERCOM_SPI_INTFLAG_RXC | - SERCOM_SPI_INTFLAG_ERROR; - NVIC_DisableIRQ((IRQn_Type)((uint8_t)SERCOM0_IRQn + sercom_index)); - NVIC_SetVector((IRQn_Type)((uint8_t)SERCOM0_IRQn + sercom_index), (uint32_t)NULL); -} - -/** - * \internal - * Starts transceive of buffers with a given length - * - * \param[in,out] obj Pointer to SPI software instance struct - * - */ -static enum status_code _spi_transceive_buffer(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint16_t interrupt_status = _SPI(obj).INTFLAG.reg; - interrupt_status &= _SPI(obj).INTENSET.reg; - - if (interrupt_status & SERCOM_SPI_INTFLAG_DRE) { - /* Clear DRE interrupt */ - _SPI(obj).INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE; - /* Write data */ - _spi_write_async(obj); - /* Set TXC interrupt */ - _SPI(obj).INTENSET.reg |= SERCOM_SPI_INTFLAG_TXC; - } - if (interrupt_status & SERCOM_SPI_INTFLAG_TXC) { - /* Clear TXC interrupt */ - _SPI(obj).INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC; - if ((obj->rx_buff.buffer) && (obj->rx_buff.pos < obj->rx_buff.length)) { - while (!spi_is_ready_to_read(obj)); - _spi_read_async(obj); - if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->tx_buff.length < obj->rx_buff.length)) { - obj->tx_buff.length = obj->rx_buff.length; - obj->tx_buff.buffer = 0; - } - } - if (obj->tx_buff.pos < obj->tx_buff.length) { - /* Set DRE interrupt */ - _SPI(obj).INTENSET.reg |= SERCOM_SPI_INTFLAG_DRE; - } - } - - if (obj->spi.event & (SPI_EVENT_ERROR | SPI_EVENT_RX_OVERFLOW) || (interrupt_status & SERCOM_SPI_INTFLAG_ERROR)) { - /* Clear all interrupts */ - _spi_clear_interrupts(obj); - - if (interrupt_status & SERCOM_SPI_INTFLAG_ERROR) { - obj->spi.event = STATUS_ERR_BAD_DATA; - } - - /* Transfer interrupted, invoke the callback function */ - if (obj->spi.event & SPI_EVENT_RX_OVERFLOW) { - obj->spi.status = STATUS_ERR_OVERFLOW; - } else { - obj->spi.status = STATUS_ERR_BAD_DATA; - } - return (enum status_code)obj->spi.status; - } - - if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->rx_buff.pos >= obj->rx_buff.length) && (interrupt_status & SERCOM_SPI_INTFLAG_TXC)) { - /* Clear all interrupts */ - _spi_clear_interrupts(obj); - - /* Transfer complete, invoke the callback function */ - obj->spi.event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; - obj->spi.status = STATUS_OK; - } - - return (enum status_code)(obj->spi.status); -} - -/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff - * - * @param[in] obj The SPI object which holds the transfer information - * @param[in] tx The buffer to send - * @param[in] tx_length The number of words to transmit - * @param[out]rx The buffer to receive - * @param[in] rx_length The number of words to receive - * @param[in] bit_width The bit width of buffer words - * @param[in] event The logical OR of events to be registered - * @param[in] handler SPI interrupt handler - * @param[in] hint A suggestion for how to use DMA with this transfer **< DMA currently not implemented >** - */ -void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ - uint16_t dummy_read; - (void) dummy_read; - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); - - obj->spi.tx_buffer = (void *)tx; - obj->tx_buff.buffer =(void *)tx; - obj->tx_buff.pos = 0; - if (tx) { - /* Only two bit rates supported now */ - obj->tx_buff.length = tx_length * ((bit_width > 8)? 2 : 1); - } else { - if (rx) { - obj->tx_buff.length = rx_length * ((bit_width > 8)? 2 : 1); - } else { - /* Nothing to transfer */ - return; - } - } - - obj->spi.rx_buffer = rx; - obj->rx_buff.buffer = rx; - obj->rx_buff.pos = 0; - if (rx) { - /* Only two bit rates supported now */ - obj->rx_buff.length = rx_length * ((bit_width > 8)? 2 : 1); - } else { - /* Disable RXEN */ - spi_disable(obj); - _SPI(obj).CTRLB.bit.RXEN = 0; - spi_enable(obj); - obj->rx_buff.length = 0; - } - - /* Clear data buffer if there is anything pending to read */ - while (spi_is_ready_to_read(obj)) { - dummy_read = _SPI(obj).DATA.reg; - } - - obj->spi.mask = event; - - obj->spi.dma_usage = hint; - - /*if (hint == DMA_USAGE_NEVER) {** TEMP: Commented as DMA is not implemented now */ - /* Use irq method */ - uint16_t irq_mask = 0; - obj->spi.status = STATUS_BUSY; - - /* Enable interrupt */ - NVIC_SetVector((IRQn_Type)((uint8_t)SERCOM0_IRQn + sercom_index), handler); - NVIC_EnableIRQ((IRQn_Type)((uint8_t)SERCOM0_IRQn + sercom_index)); - - /* Clear all interrupts */ - _SPI(obj).INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_ERROR; - _SPI(obj).INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_ERROR; - _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; - - /* Set SPI interrupts */ - /* Set DRE flag to kick start transmission */ - irq_mask |= SERCOM_SPI_INTFLAG_DRE; - - if (event & SPI_EVENT_ERROR) { - irq_mask |= SERCOM_SPI_INTFLAG_ERROR; - } - _SPI(obj).INTENSET.reg = irq_mask; - /*} ** TEMP: Commented as DMA is not implemented now */ -} - -/** The asynchronous IRQ handler - * - * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination - * conditions, such as buffer overflows or transfer complete. - * @param[in] obj The SPI object which holds the transfer information - * @return event flags if a transfer termination condition was met or 0 otherwise. - */ -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - enum status_code tmp_status; - - uint32_t transfer_event = 0; - - /*if (obj->spi.dma_usage == DMA_USAGE_NEVER) {** TEMP: Commented as DMA is not implemented now */ - /* IRQ method */ - tmp_status = _spi_transceive_buffer(obj); - if (STATUS_BUSY != tmp_status) { - if ((obj->spi.event & SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) && (tmp_status == STATUS_OK)) { - obj->spi.event |= SPI_EVENT_COMPLETE; - } - transfer_event = obj->spi.event & (obj->spi.mask | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE); - } - /*}** TEMP: Commented as DMA is not implemented now */ - return transfer_event; -} - -/** Attempts to determine if the SPI peripheral is already in use. - * @param[in] obj The SPI object to check for activity - * @return non-zero if the SPI port is active or zero if it is not. - */ -uint8_t spi_active(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check if the SPI module is busy with a job */ - return (obj->spi.status == STATUS_BUSY); -} - -/** Abort an SPI transfer - * - * @param obj The SPI peripheral to stop - */ -void spi_abort_asynch(spi_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); - - /* Clear all interrupts */ - _SPI(obj).INTENCLR.reg = - SERCOM_SPI_INTFLAG_DRE | - SERCOM_SPI_INTFLAG_TXC | - SERCOM_SPI_INTFLAG_RXC | - SERCOM_SPI_INTFLAG_ERROR; - - // TODO: Disable and remove irq handler - NVIC_DisableIRQ((IRQn_Type)((uint8_t)SERCOM0_IRQn + sercom_index)); - NVIC_SetVector((IRQn_Type)((uint8_t)SERCOM0_IRQn + sercom_index), (uint32_t)NULL); - - obj->spi.status = STATUS_ABORTED; -} - -#endif /* DEVICE_SPI_ASYNCH */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c deleted file mode 100644 index 568aa89ef0d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c +++ /dev/null @@ -1,174 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "cmsis.h" -#include "mbed_assert.h" -#include "ins_gclk.h" -#include "compiler.h" -#include "system.h" -#include "tc.h" -#include "tc_interrupt.h" - -#if (SAMD21) || (SAMR21) -#define TICKER_COUNTER_uS TC4 -#define TICKER_COUNTER_IRQn TC4_IRQn -#define TICKER_COUNTER_Handlr TC4_Handler -#elif (SAML21) /*SAML21 TCC4 does not support 32 bit counter operations*/ -#define TICKER_COUNTER_uS TC0 -#define TICKER_COUNTER_IRQn TC0_IRQn -#define TICKER_COUNTER_Handlr TC0_Handler -#endif - -static int us_ticker_inited = 0; -extern uint8_t g_sys_init; - -struct tc_module us_ticker_module; - - -static inline void tc_clear_interrupt( - struct tc_module *const module, - const enum tc_callback callback_type) -{ - /* Sanity check arguments */ - MBED_ASSERT(module); - - /* Clear interrupt flags */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1); - } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2); - } else { - module->hw->COUNT8.INTENCLR.reg = (1 << callback_type); - } -} - -void us_ticker_irq_handler_internal(struct tc_module* us_tc_module) -{ - uint32_t status_flags; - - /* Clear TC capture overflow and TC count overflow */ - status_flags = TC_STATUS_CAPTURE_OVERFLOW | TC_STATUS_COUNT_OVERFLOW; - tc_clear_status(&us_ticker_module, status_flags); - - us_ticker_irq_handler(); -} - -void us_ticker_init(void) -{ - uint32_t cycles_per_us; - uint32_t prescaler = 0; - struct tc_config config_tc; - - if (us_ticker_inited) return; - us_ticker_inited = 1; - - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - - tc_get_config_defaults(&config_tc); - - cycles_per_us = system_gclk_gen_get_hz(config_tc.clock_source) / 1000000; - MBED_ASSERT(cycles_per_us > 0); - /*while((cycles_per_us & 1) == 0 && prescaler <= 10) { - cycles_per_us = cycles_per_us >> 1; - prescaler++; - }*/ - while((cycles_per_us > 1) && (prescaler <= 10)) { - cycles_per_us = cycles_per_us >> 1; - prescaler++; - } - if (prescaler >= 9) { - prescaler = 7; - } else if (prescaler >= 7) { - prescaler = 6; - } else if (prescaler >= 5) { - prescaler = 5; - } - - config_tc.clock_prescaler = (enum tc_clock_prescaler)TC_CTRLA_PRESCALER(prescaler); - config_tc.counter_size = TC_COUNTER_SIZE_32BIT; - config_tc.run_in_standby = true; - config_tc.counter_32_bit.value = 0; - config_tc.counter_32_bit.compare_capture_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = 0xFFFFFFFF; - - /* Initialize the timer */ - tc_init(&us_ticker_module, TICKER_COUNTER_uS, &config_tc); - - /* Register callback function */ - tc_register_callback(&us_ticker_module, (tc_callback_t)us_ticker_irq_handler_internal, TC_CALLBACK_CC_CHANNEL0); - - /* Enable the timer module */ - tc_enable(&us_ticker_module); -} - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) - us_ticker_init(); - - return tc_get_count_value(&us_ticker_module); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - uint32_t cur_time; - int32_t delta; - - cur_time = us_ticker_read(); - delta = (int32_t)((uint32_t)timestamp - cur_time); - if (delta < 0) { - /* Event already occurred in past */ - us_ticker_irq_handler(); - return; - } - - NVIC_DisableIRQ(TICKER_COUNTER_IRQn); - NVIC_SetVector(TICKER_COUNTER_IRQn, (uint32_t)TICKER_COUNTER_Handlr); - - /* Enable the callback */ - tc_enable_callback(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); - tc_set_compare_value(&us_ticker_module, TC_COMPARE_CAPTURE_CHANNEL_0, (uint32_t)timestamp); - - NVIC_EnableIRQ(TICKER_COUNTER_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - /* Disable the callback */ - tc_disable_callback(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); - NVIC_DisableIRQ(TICKER_COUNTER_IRQn); -} - -void us_ticker_clear_interrupt(void) -{ - uint32_t status_flags; - - /* Clear TC channel 0 match */ - status_flags = TC_STATUS_CHANNEL_0_MATCH; - tc_clear_status(&us_ticker_module, status_flags); - - /* Clear the interrupt */ - tc_clear_interrupt(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); - NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn); -} - -void us_ticker_free(void) -{ - -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h deleted file mode 100644 index 55f0b63ce67..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h +++ /dev/null @@ -1,562 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_AC_COMPONENT_ -#define _SAMD21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2205 -#define REV_AC 0x112 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ -#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos) -#define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))) -#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ -#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos) -#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))) -#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ -#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ -#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ -#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))) -#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))) -#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))) -#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))) -#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))) -#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))) -#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ -#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos) -#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ -#define AC_STATUSC_RESETVALUE 0x00ul /**< \brief (AC_STATUSC reset_value) Status C */ - -#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ -#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) -#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ -#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) -#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ -#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos) -#define AC_STATUSC_STATE(value) ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))) -#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ -#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))) -#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */ -#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */ -#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */ -#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_MASK 0x33ul /**< \brief (AC_STATUSC) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))) -#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))) -#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))) -#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))) -#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))) -#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_MASK 0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))) -#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h deleted file mode 100644 index 65ea3e1aced..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h +++ /dev/null @@ -1,702 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_ADC_COMPONENT_ -#define _SAMD21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2204 -#define REV_ADC 0x120 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))) -#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ -#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))) -#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))) -#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ -#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))) -#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ -#define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos) -#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ -#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))) -#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))) -#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ -#define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ - -#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ -#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))) -#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */ -#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ -#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ -#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ -#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))) -#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))) -#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */ -#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ -#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos) -#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))) -#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ -#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos) -#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))) -#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ -#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))) -#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */ -#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */ -#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */ -#define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */ -#define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */ -#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */ -#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ -#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ -#define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ -#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ -#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ -#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos) -#define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ -#define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos) -#define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ -#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ -#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ -#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ -#define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos) -#define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ -#define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos) -#define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))) -#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))) -#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))) -#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))) -#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))) -#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ -#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos) -#define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))) -#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ -#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos) -#define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))) -#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h deleted file mode 100644 index 968f00463e2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_DAC_COMPONENT_ -#define _SAMD21_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DAC Digital Analog Converter */ -/*@{*/ - -#define DAC_U2214 -#define REV_DAC 0x110 - -/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ -#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ -#define DAC_CTRLA_RUNSTDBY (0x1ul << DAC_CTRLA_RUNSTDBY_Pos) -#define DAC_CTRLA_MASK 0x07ul /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ - uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ - uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ - uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ - uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ -#define DAC_CTRLB_EOEN (0x1ul << DAC_CTRLB_EOEN_Pos) -#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ -#define DAC_CTRLB_IOEN (0x1ul << DAC_CTRLB_IOEN_Pos) -#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ -#define DAC_CTRLB_LEFTADJ (0x1ul << DAC_CTRLB_LEFTADJ_Pos) -#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ -#define DAC_CTRLB_VPD (0x1ul << DAC_CTRLB_VPD_Pos) -#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ -#define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos) -#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ -#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))) -#define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */ -#define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */ -#define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */ -#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK 0xDFul /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ - uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ -#define DAC_EVCTRL_STARTEI (0x1ul << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ -#define DAC_EVCTRL_EMPTYEO (0x1ul << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_MASK 0x03ul /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN (0x1ul << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY (0x1ul << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define DAC_INTENCLR_SYNCRDY (0x1ul << DAC_INTENCLR_SYNCRDY_Pos) -#define DAC_INTENCLR_MASK 0x07ul /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN (0x1ul << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY (0x1ul << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ -#define DAC_INTENSET_SYNCRDY (0x1ul << DAC_INTENSET_SYNCRDY_Pos) -#define DAC_INTENSET_MASK 0x07ul /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ -#define DAC_INTFLAG_UNDERRUN (0x1ul << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ -#define DAC_INTFLAG_EMPTY (0x1ul << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ -#define DAC_INTFLAG_SYNCRDY (0x1ul << DAC_INTFLAG_SYNCRDY_Pos) -#define DAC_INTFLAG_MASK 0x07ul /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ -#define DAC_STATUS_SYNCBUSY (0x1ul << DAC_STATUS_SYNCBUSY_Pos) -#define DAC_STATUS_MASK 0x80ul /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ -#define DAC_DATA_RESETVALUE 0x0000ul /**< \brief (DAC_DATA reset_value) Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ -#define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))) -#define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ -#define DAC_DATABUF_RESETVALUE 0x0000ul /**< \brief (DAC_DATABUF reset_value) Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))) -#define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ - RoReg8 Reserved2[0x2]; - __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h deleted file mode 100644 index 7f187915a09..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h +++ /dev/null @@ -1,1088 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_DMAC_COMPONENT_ -#define _SAMD21_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2223 -#define REV_DMAC 0x110 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ -#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))) -#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) Byte bus access */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) Half-word bus access */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) Word bus access */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))) -#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))) -#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))) -#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ -#define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ - -#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ -#define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS(value) ((DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))) -#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ -#define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS(value) ((DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))) -#define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ -#define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS(value) ((DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))) -#define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))) -#define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))) -#define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))) -#define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))) -#define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))) -#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))) -#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))) -#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ -#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */ - -#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ -#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos) -#define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))) -#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ -#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ -#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ - -#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ -#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))) -#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ -#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ -#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ -#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos) -#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ -#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos) -#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ -#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))) -#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ -#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ -#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ -#define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ -#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */ -#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))) -#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ -#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ -#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))) -#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ -#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ -#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))) -#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Transfer Error */ - uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Transfer Error */ -#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ -#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Fetch Error */ -#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) No action */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit access */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit access */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit access */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))) -#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 1 */ -#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 2 */ -#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 4 */ -#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 8 */ -#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 16 */ -#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 32 */ -#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 64 */ -#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 128 */ -#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */ - -/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */ - -#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */ -#define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos) -#define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))) -#define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */ - -/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SRCADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */ - -#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */ -#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos) -#define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))) -#define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */ - -/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_DSTADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */ - -#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */ -#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos) -#define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))) -#define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */ - -/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_DESCADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */ - -#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */ -#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos) -#define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))) -#define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */ - -/** \brief DMAC APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ - __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ - __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ - __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ - __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ - __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ - __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ - RoReg8 Reserved1[0x1]; - __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ - __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ - RoReg8 Reserved2[0x8]; - __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ - RoReg8 Reserved3[0x2]; - __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ - __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ - __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ - __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ - __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ - __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ - RoReg8 Reserved4[0x3]; - __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ - __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ - RoReg8 Reserved5[0x3]; - __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ - RoReg8 Reserved6[0x4]; - __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ - __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ - __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ - __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ -} Dmac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief DMAC Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ - __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ - __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */ - __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */ - __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ -} DmacDescriptor -#ifdef __GNUC__ -__attribute__ ((aligned (8))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_DMAC_DESCRIPTOR - -/*@}*/ - -#endif /* _SAMD21_DMAC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h deleted file mode 100644 index 450f3444e5b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h +++ /dev/null @@ -1,554 +0,0 @@ -/** - * \file - * - * \brief Component description for DSU - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_DSU_COMPONENT_ -#define _SAMD21_DSU_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DSU */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DSU Device Service Unit */ -/*@{*/ - -#define DSU_U2209 -#define REV_DSU 0x202 - -/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ - uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ - uint8_t CE:1; /*!< bit: 4 Chip Erase */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ -#define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */ - -#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ -#define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos) -#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */ -#define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos) -#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */ -#define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos) -#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */ -#define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos) -#define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */ - -/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DONE:1; /*!< bit: 0 Done */ - uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ - uint8_t BERR:1; /*!< bit: 2 Bus Error */ - uint8_t FAIL:1; /*!< bit: 3 Failure */ - uint8_t PERR:1; /*!< bit: 4 Protection Error */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ -#define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */ - -#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ -#define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos) -#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ -#define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos) -#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ -#define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos) -#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ -#define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos) -#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ -#define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos) -#define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */ - -/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PROT:1; /*!< bit: 0 Protected */ - uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ - uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ - uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ - uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ -#define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */ - -#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ -#define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos) -#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ -#define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos) -#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ -#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos) -#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ -#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos) -#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ -#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos) -#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))) -#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ -#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos) -#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */ - -/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t ADDR:30; /*!< bit: 2..31 Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ -#define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */ - -#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ -#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos) -#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))) -#define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */ - -/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t LENGTH:30; /*!< bit: 2..31 Length */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_LENGTH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ -#define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */ - -#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ -#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos) -#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))) -#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */ - -/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ -#define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */ - -#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ -#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos) -#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))) -#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */ - -/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ -#define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ - -#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ -#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos) -#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))) -#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */ - -/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ - uint32_t REVISION:4; /*!< bit: 8..11 Revision */ - uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ - uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ - uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ - -#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ -#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos) -#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))) -#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */ -#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos) -#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))) -#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */ -#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos) -#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))) -#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */ -#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos) -#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))) -#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */ -#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos) -#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))) -#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ -#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos) -#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))) -#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */ - -/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EPRES:1; /*!< bit: 0 Entry Present */ - uint32_t FMT:1; /*!< bit: 1 Format */ - uint32_t :10; /*!< bit: 2..11 Reserved */ - uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_ENTRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */ -#define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */ - -#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */ -#define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos) -#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */ -#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos) -#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */ -#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos) -#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))) -#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */ - -/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t END:32; /*!< bit: 0..31 End Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_END_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */ -#define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */ - -#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ -#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos) -#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos))) -#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */ - -/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_MEMTYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */ -#define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */ - -#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ -#define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos) -#define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */ - -/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ - uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID4_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ -#define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ - -#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ -#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos) -#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))) -#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */ -#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos) -#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))) -#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */ - -/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ -#define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ - -#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ -#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos) -#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))) -#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */ - -/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ - uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ -#define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ - -#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ -#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos) -#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))) -#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ -#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos) -#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))) -#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */ - -/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ - uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ - uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ -#define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ - -#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ -#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos) -#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))) -#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ -#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos) -#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ -#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos) -#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))) -#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */ - -/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ - uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ -#define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ - -#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ -#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos) -#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))) -#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ -#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos) -#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))) -#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */ - -/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ -#define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ - -#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ -#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos) -#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))) -#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */ - -/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ - uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ -#define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ - -#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ -#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos) -#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))) -#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ -#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos) -#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))) -#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */ - -/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ -#define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ - -#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ -#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos) -#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))) -#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */ - -/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ -#define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ - -#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ -#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos) -#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))) -#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */ - -/** \brief DSU hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ - __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ - __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ - RoReg8 Reserved1[0x1]; - __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ - __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ - __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ - __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ - __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ - RoReg8 Reserved2[0xFE4]; - __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ - __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ - RoReg8 Reserved3[0xFC0]; - __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ - __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ - RoReg8 Reserved4[0xC]; - __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ - __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ - __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ - __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ - __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ - __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ - __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ - __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ -} Dsu; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_DSU_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h deleted file mode 100644 index 7ea6fe2833e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h +++ /dev/null @@ -1,684 +0,0 @@ -/** - * \file - * - * \brief Component description for EIC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_EIC_COMPONENT_ -#define _SAMD21_EIC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR EIC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_EIC External Interrupt Controller */ -/*@{*/ - -#define EIC_U2217 -#define REV_EIC 0x101 - -/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */ -#define EIC_CTRL_RESETVALUE 0x00ul /**< \brief (EIC_CTRL reset_value) Control */ - -#define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */ -#define EIC_CTRL_SWRST (0x1ul << EIC_CTRL_SWRST_Pos) -#define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */ -#define EIC_CTRL_ENABLE (0x1ul << EIC_CTRL_ENABLE_Pos) -#define EIC_CTRL_MASK 0x03ul /**< \brief (EIC_CTRL) MASK Register */ - -/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */ -#define EIC_STATUS_RESETVALUE 0x00ul /**< \brief (EIC_STATUS reset_value) Status */ - -#define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */ -#define EIC_STATUS_SYNCBUSY (0x1ul << EIC_STATUS_SYNCBUSY_Pos) -#define EIC_STATUS_MASK 0x80ul /**< \brief (EIC_STATUS) MASK Register */ - -/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ - uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_NMICTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */ -#define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */ - -#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */ -#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))) -#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */ -#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */ -#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */ -#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both-edges detection */ -#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High-level detection */ -#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low-level detection */ -#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */ -#define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos) -#define EIC_NMICTRL_MASK 0x0Ful /**< \brief (EIC_NMICTRL) MASK Register */ - -/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_NMIFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */ -#define EIC_NMIFLAG_RESETVALUE 0x00ul /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */ - -#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */ -#define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos) -#define EIC_NMIFLAG_MASK 0x01ul /**< \brief (EIC_NMIFLAG) MASK Register */ - -/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ - uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ - uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ - uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ - uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ - uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ - uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ - uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ - uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ - uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ - uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ - uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ - uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ - uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ - uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ - uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */ -#define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */ - -#define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos) -#define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos) -#define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos) -#define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos) -#define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos) -#define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos) -#define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos) -#define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos) -#define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos) -#define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos) -#define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos) -#define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos) -#define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos) -#define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos) -#define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos) -#define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos) -#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos) -#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))) -#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */ - -/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */ -#define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */ -#define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos) -#define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */ -#define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos) -#define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */ -#define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos) -#define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */ -#define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos) -#define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */ -#define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos) -#define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */ -#define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos) -#define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */ -#define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos) -#define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */ -#define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos) -#define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */ -#define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos) -#define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */ -#define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos) -#define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */ -#define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos) -#define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */ -#define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos) -#define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */ -#define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos) -#define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */ -#define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos) -#define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */ -#define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos) -#define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */ -#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos) -#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */ -#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos) -#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))) -#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */ - -/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */ -#define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */ - -#define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */ -#define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos) -#define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */ -#define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos) -#define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */ -#define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos) -#define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */ -#define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos) -#define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */ -#define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos) -#define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */ -#define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos) -#define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */ -#define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos) -#define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */ -#define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos) -#define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */ -#define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos) -#define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */ -#define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos) -#define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */ -#define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos) -#define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */ -#define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos) -#define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */ -#define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos) -#define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */ -#define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos) -#define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */ -#define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos) -#define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */ -#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos) -#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */ -#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos) -#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))) -#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */ - -/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */ -#define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos) -#define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */ -#define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos) -#define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */ -#define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos) -#define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */ -#define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos) -#define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */ -#define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos) -#define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */ -#define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos) -#define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */ -#define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos) -#define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */ -#define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos) -#define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */ -#define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos) -#define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */ -#define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos) -#define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */ -#define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos) -#define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */ -#define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos) -#define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */ -#define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos) -#define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */ -#define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos) -#define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */ -#define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos) -#define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */ -#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos) -#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */ -#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos) -#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))) -#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */ - -/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ - uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ - uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ - uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ - uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ - uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ - uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ - uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ - uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ - uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ - uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ - uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ - uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ - uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ - uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ - uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_WAKEUP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */ -#define EIC_WAKEUP_RESETVALUE 0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */ - -#define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos) -#define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos) -#define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos) -#define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos) -#define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos) -#define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos) -#define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos) -#define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos) -#define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos) -#define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos) -#define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos) -#define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos) -#define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos) -#define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos) -#define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos) -#define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos) -#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos) -#define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))) -#define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */ - -/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ - uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ - uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ - uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ - uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ - uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ - uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ - uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ - uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ - uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ - uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ - uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ - uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ - uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ - uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ - uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_CONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */ -#define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */ - -#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */ -#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))) -#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */ -#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */ -#define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both-edges detection */ -#define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High-level detection */ -#define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low-level detection */ -#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */ -#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos) -#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */ -#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))) -#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */ -#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos) -#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */ -#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))) -#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */ -#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos) -#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */ -#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))) -#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */ -#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos) -#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */ -#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))) -#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */ -#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos) -#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */ -#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))) -#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */ -#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos) -#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */ -#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))) -#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */ -#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos) -#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */ -#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))) -#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */ -#define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos) -#define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */ - -/** \brief EIC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ - __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ - __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ - __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ - __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ - __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ - __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ - __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ - __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ -} Eic; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_EIC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h deleted file mode 100644 index 5f28cf416b0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h +++ /dev/null @@ -1,607 +0,0 @@ -/** - * \file - * - * \brief Component description for EVSYS - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_EVSYS_COMPONENT_ -#define _SAMD21_EVSYS_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR EVSYS */ -/* ========================================================================== */ -/** \addtogroup SAMD21_EVSYS Event System Interface */ -/*@{*/ - -#define EVSYS_U2208 -#define REV_EVSYS 0x101 - -/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :3; /*!< bit: 1.. 3 Reserved */ - uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EVSYS_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */ -#define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */ - -#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */ -#define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos) -#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */ -#define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos) -#define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */ - -/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SWEVT:1; /*!< bit: 8 Software Event */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ - uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_CHANNEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */ -#define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */ - -#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */ -#define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos) -#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))) -#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */ -#define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos) -#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */ -#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos) -#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))) -#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */ -#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))) -#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */ -#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */ -#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */ -#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */ -#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))) -#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */ - -/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} EVSYS_USER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */ -#define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */ - -#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */ -#define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos) -#define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))) -#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */ -#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos) -#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))) -#define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */ -#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos) -#define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */ - -/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ - uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ - uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ - uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ - uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ - uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ - uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ - uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ - uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ - uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ - uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ - uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ - uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ - uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ - uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ - uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ - uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ - uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ - uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ - uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ - uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ - uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ - uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ - uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ - uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */ -#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */ - -#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */ -#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos) -#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */ -#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos) -#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */ -#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos) -#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */ -#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos) -#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */ -#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos) -#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */ -#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos) -#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */ -#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos) -#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */ -#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos) -#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */ -#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos) -#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))) -#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */ -#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos) -#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */ -#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos) -#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */ -#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos) -#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */ -#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos) -#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */ -#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos) -#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */ -#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos) -#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */ -#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos) -#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */ -#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos) -#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */ -#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos) -#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))) -#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */ -#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos) -#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */ -#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos) -#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */ -#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos) -#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */ -#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos) -#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */ -#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos) -#define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))) -#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */ -#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos) -#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */ -#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos) -#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */ -#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos) -#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */ -#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos) -#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */ -#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos) -#define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))) -#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */ - -/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */ -#define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */ - -#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos) -#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos) -#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos) -#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos) -#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos) -#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos) -#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos) -#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos) -#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos) -#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))) -#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos) -#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos) -#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos) -#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos) -#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos) -#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos) -#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos) -#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos) -#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos) -#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))) -#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos) -#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos) -#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos) -#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos) -#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos) -#define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))) -#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos) -#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos) -#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos) -#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos) -#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos) -#define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))) -#define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */ - -/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */ -#define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */ - -#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos) -#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos) -#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos) -#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos) -#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos) -#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos) -#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos) -#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos) -#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos) -#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))) -#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos) -#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos) -#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos) -#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos) -#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos) -#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos) -#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos) -#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos) -#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos) -#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))) -#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos) -#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos) -#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos) -#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos) -#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos) -#define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))) -#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos) -#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos) -#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos) -#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos) -#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos) -#define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))) -#define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */ - -/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */ -#define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */ -#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos) -#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */ -#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos) -#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */ -#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos) -#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */ -#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos) -#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */ -#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos) -#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */ -#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos) -#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */ -#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos) -#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */ -#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos) -#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */ -#define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos) -#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))) -#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */ -#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos) -#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */ -#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos) -#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */ -#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos) -#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */ -#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos) -#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */ -#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos) -#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */ -#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos) -#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */ -#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos) -#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */ -#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos) -#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */ -#define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos) -#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))) -#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */ -#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos) -#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */ -#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos) -#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */ -#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos) -#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */ -#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos) -#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */ -#define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos) -#define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))) -#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */ -#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos) -#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */ -#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos) -#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */ -#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos) -#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */ -#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos) -#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */ -#define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos) -#define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))) -#define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */ - -/** \brief EVSYS hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ - __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ - RoReg8 Reserved2[0x2]; - __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ - __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ - __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ - __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ -} Evsys; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_EVSYS_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h deleted file mode 100644 index 2d2348f3c5b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h +++ /dev/null @@ -1,313 +0,0 @@ -/** - * \file - * - * \brief Component description for GCLK - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_GCLK_COMPONENT_ -#define _SAMD21_GCLK_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR GCLK */ -/* ========================================================================== */ -/** \addtogroup SAMD21_GCLK Generic Clock Generator */ -/*@{*/ - -#define GCLK_U2102 -#define REV_GCLK 0x210 - -/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} GCLK_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */ -#define GCLK_CTRL_RESETVALUE 0x00ul /**< \brief (GCLK_CTRL reset_value) Control */ - -#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */ -#define GCLK_CTRL_SWRST (0x1ul << GCLK_CTRL_SWRST_Pos) -#define GCLK_CTRL_MASK 0x01ul /**< \brief (GCLK_CTRL) MASK Register */ - -/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} GCLK_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */ -#define GCLK_STATUS_RESETVALUE 0x00ul /**< \brief (GCLK_STATUS reset_value) Status */ - -#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */ -#define GCLK_STATUS_SYNCBUSY (0x1ul << GCLK_STATUS_SYNCBUSY_Pos) -#define GCLK_STATUS_MASK 0x80ul /**< \brief (GCLK_STATUS) MASK Register */ - -/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ - uint16_t :2; /*!< bit: 12..13 Reserved */ - uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ - uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} GCLK_CLKCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */ -#define GCLK_CLKCTRL_RESETVALUE 0x0000ul /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */ - -#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */ -#define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))) -#define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */ -#define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */ -#define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */ -#define GCLK_CLKCTRL_ID_WDT_Val 0x3ul /**< \brief (GCLK_CLKCTRL) WDT */ -#define GCLK_CLKCTRL_ID_RTC_Val 0x4ul /**< \brief (GCLK_CLKCTRL) RTC */ -#define GCLK_CLKCTRL_ID_EIC_Val 0x5ul /**< \brief (GCLK_CLKCTRL) EIC */ -#define GCLK_CLKCTRL_ID_USB_Val 0x6ul /**< \brief (GCLK_CLKCTRL) USB */ -#define GCLK_CLKCTRL_ID_EVSYS_0_Val 0x7ul /**< \brief (GCLK_CLKCTRL) EVSYS_0 */ -#define GCLK_CLKCTRL_ID_EVSYS_1_Val 0x8ul /**< \brief (GCLK_CLKCTRL) EVSYS_1 */ -#define GCLK_CLKCTRL_ID_EVSYS_2_Val 0x9ul /**< \brief (GCLK_CLKCTRL) EVSYS_2 */ -#define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */ -#define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */ -#define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */ -#define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */ -#define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */ -#define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */ -#define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */ -#define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */ -#define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */ -#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */ -#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */ -#define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */ -#define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */ -#define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */ -#define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */ -#define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */ -#define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */ -#define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */ -#define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */ -#define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */ -#define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */ -#define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */ -#define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */ -#define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))) -#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */ -#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */ -#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */ -#define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */ -#define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */ -#define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */ -#define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */ -#define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */ -#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */ -#define GCLK_CLKCTRL_CLKEN (0x1ul << GCLK_CLKCTRL_CLKEN_Pos) -#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */ -#define GCLK_CLKCTRL_WRTLOCK (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos) -#define GCLK_CLKCTRL_MASK 0xCF3Ful /**< \brief (GCLK_CLKCTRL) MASK Register */ - -/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SRC:5; /*!< bit: 8..12 Source Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ - uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ - uint32_t OOV:1; /*!< bit: 18 Output Off Value */ - uint32_t OE:1; /*!< bit: 19 Output Enable */ - uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ - uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} GCLK_GENCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */ -#define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */ - -#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */ -#define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos) -#define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))) -#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */ -#define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))) -#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */ -#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */ -#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */ -#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */ -#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */ -#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */ -#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */ -#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */ -#define GCLK_GENCTRL_SRC_FDPLL_Val 0x8ul /**< \brief (GCLK_GENCTRL) FDPLL output */ -#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */ -#define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos) -#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */ -#define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos) -#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */ -#define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos) -#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */ -#define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos) -#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */ -#define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos) -#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */ -#define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos) -#define GCLK_GENCTRL_MASK 0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */ - -/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} GCLK_GENDIV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */ -#define GCLK_GENDIV_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */ - -#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */ -#define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos) -#define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))) -#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */ -#define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos) -#define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))) -#define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */ - -/** \brief GCLK hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ - __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ - __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ - __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ -} Gclk; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_GCLK_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h deleted file mode 100644 index 21647a68bfa..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - * \file - * - * \brief Component description for HMATRIXB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_HMATRIXB_COMPONENT_ -#define _SAMD21_HMATRIXB_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR HMATRIXB */ -/* ========================================================================== */ -/** \addtogroup SAMD21_HMATRIXB HSB Matrix */ -/*@{*/ - -#define HMATRIXB_I7638 -#define REV_HMATRIXB 0x212 - -/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} HMATRIXB_PRAS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */ -#define HMATRIXB_PRAS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */ - -#define HMATRIXB_PRAS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */ - -/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} HMATRIXB_PRBS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */ -#define HMATRIXB_PRBS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */ - -#define HMATRIXB_PRBS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */ - -/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} HMATRIXB_SFR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */ -#define HMATRIXB_SFR_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */ - -#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */ -#define HMATRIXB_SFR_SFR_Msk (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos) -#define HMATRIXB_SFR_SFR(value) ((HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))) -#define HMATRIXB_SFR_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */ - -/** \brief HmatrixbPrs hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ - __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ -} HmatrixbPrs; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief HMATRIXB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - RoReg8 Reserved1[0x80]; - HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ - RoReg8 Reserved2[0x10]; - __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ -} Hmatrixb; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_HMATRIXB_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h deleted file mode 100644 index da7b7a0e3ef..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h +++ /dev/null @@ -1,642 +0,0 @@ -/** - * \file - * - * \brief Component description for I2S - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_I2S_COMPONENT_ -#define _SAMD21_I2S_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR I2S */ -/* ========================================================================== */ -/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */ -/*@{*/ - -#define I2S_U2224 -#define REV_I2S 0x110 - -/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */ - uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */ - uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */ - uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */ - uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} I2S_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */ -#define I2S_CTRLA_RESETVALUE 0x00ul /**< \brief (I2S_CTRLA reset_value) Control A */ - -#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */ -#define I2S_CTRLA_SWRST (0x1ul << I2S_CTRLA_SWRST_Pos) -#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */ -#define I2S_CTRLA_ENABLE (0x1ul << I2S_CTRLA_ENABLE_Pos) -#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */ -#define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos) -#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */ -#define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos) -#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */ -#define I2S_CTRLA_CKEN_Msk (0x3ul << I2S_CTRLA_CKEN_Pos) -#define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))) -#define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */ -#define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos) -#define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */ -#define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos) -#define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */ -#define I2S_CTRLA_SEREN_Msk (0x3ul << I2S_CTRLA_SEREN_Pos) -#define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))) -#define I2S_CTRLA_MASK 0x3Ful /**< \brief (I2S_CTRLA) MASK Register */ - -/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */ - uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */ - uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */ - uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */ - uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */ - uint32_t :2; /*!< bit: 9..10 Reserved */ - uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */ - uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */ - uint32_t :1; /*!< bit: 17 Reserved */ - uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */ - uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */ - uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */ - uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */ - uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */ - uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} I2S_CLKCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */ -#define I2S_CLKCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */ - -#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */ -#define I2S_CLKCTRL_SLOTSIZE_Msk (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos) -#define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))) -#define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0ul /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */ -#define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1ul /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */ -#define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2ul /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */ -#define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3ul /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */ -#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos) -#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos) -#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos) -#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos) -#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */ -#define I2S_CLKCTRL_NBSLOTS_Msk (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos) -#define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))) -#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */ -#define I2S_CLKCTRL_FSWIDTH_Msk (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos) -#define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))) -#define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */ -#define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */ -#define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */ -#define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3ul /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */ -#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos) -#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos) -#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos) -#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos) -#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */ -#define I2S_CLKCTRL_BITDELAY (0x1ul << I2S_CLKCTRL_BITDELAY_Pos) -#define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0ul /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */ -#define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1ul /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */ -#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos) -#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos) -#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */ -#define I2S_CLKCTRL_FSSEL (0x1ul << I2S_CLKCTRL_FSSEL_Pos) -#define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */ -#define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */ -#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos) -#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos) -#define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */ -#define I2S_CLKCTRL_FSINV (0x1ul << I2S_CLKCTRL_FSINV_Pos) -#define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */ -#define I2S_CLKCTRL_SCKSEL (0x1ul << I2S_CLKCTRL_SCKSEL_Pos) -#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */ -#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */ -#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos) -#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos) -#define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */ -#define I2S_CLKCTRL_MCKSEL (0x1ul << I2S_CLKCTRL_MCKSEL_Pos) -#define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0ul /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */ -#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */ -#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos) -#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos) -#define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */ -#define I2S_CLKCTRL_MCKEN (0x1ul << I2S_CLKCTRL_MCKEN_Pos) -#define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */ -#define I2S_CLKCTRL_MCKDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos) -#define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))) -#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */ -#define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos) -#define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))) -#define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */ -#define I2S_CLKCTRL_FSOUTINV (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos) -#define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */ -#define I2S_CLKCTRL_SCKOUTINV (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos) -#define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */ -#define I2S_CLKCTRL_MCKOUTINV (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos) -#define I2S_CLKCTRL_MASK 0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */ - -/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} I2S_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */ -#define I2S_INTENCLR_RESETVALUE 0x0000ul /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */ - -#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */ -#define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos) -#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */ -#define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos) -#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */ -#define I2S_INTENCLR_RXRDY_Msk (0x3ul << I2S_INTENCLR_RXRDY_Pos) -#define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))) -#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */ -#define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos) -#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */ -#define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos) -#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */ -#define I2S_INTENCLR_RXOR_Msk (0x3ul << I2S_INTENCLR_RXOR_Pos) -#define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))) -#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */ -#define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos) -#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */ -#define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos) -#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */ -#define I2S_INTENCLR_TXRDY_Msk (0x3ul << I2S_INTENCLR_TXRDY_Pos) -#define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))) -#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */ -#define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos) -#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */ -#define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos) -#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */ -#define I2S_INTENCLR_TXUR_Msk (0x3ul << I2S_INTENCLR_TXUR_Pos) -#define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))) -#define I2S_INTENCLR_MASK 0x3333ul /**< \brief (I2S_INTENCLR) MASK Register */ - -/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} I2S_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */ -#define I2S_INTENSET_RESETVALUE 0x0000ul /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */ - -#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */ -#define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos) -#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */ -#define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos) -#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */ -#define I2S_INTENSET_RXRDY_Msk (0x3ul << I2S_INTENSET_RXRDY_Pos) -#define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))) -#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */ -#define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos) -#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */ -#define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos) -#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */ -#define I2S_INTENSET_RXOR_Msk (0x3ul << I2S_INTENSET_RXOR_Pos) -#define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))) -#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */ -#define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos) -#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */ -#define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos) -#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */ -#define I2S_INTENSET_TXRDY_Msk (0x3ul << I2S_INTENSET_TXRDY_Pos) -#define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))) -#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */ -#define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos) -#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */ -#define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos) -#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */ -#define I2S_INTENSET_TXUR_Msk (0x3ul << I2S_INTENSET_TXUR_Pos) -#define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))) -#define I2S_INTENSET_MASK 0x3333ul /**< \brief (I2S_INTENSET) MASK Register */ - -/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} I2S_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */ -#define I2S_INTFLAG_RESETVALUE 0x0000ul /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */ -#define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos) -#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */ -#define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos) -#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */ -#define I2S_INTFLAG_RXRDY_Msk (0x3ul << I2S_INTFLAG_RXRDY_Pos) -#define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))) -#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */ -#define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos) -#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */ -#define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos) -#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */ -#define I2S_INTFLAG_RXOR_Msk (0x3ul << I2S_INTFLAG_RXOR_Pos) -#define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))) -#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */ -#define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos) -#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */ -#define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos) -#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */ -#define I2S_INTFLAG_TXRDY_Msk (0x3ul << I2S_INTFLAG_TXRDY_Pos) -#define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))) -#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */ -#define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos) -#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */ -#define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos) -#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */ -#define I2S_INTFLAG_TXUR_Msk (0x3ul << I2S_INTFLAG_TXUR_Pos) -#define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))) -#define I2S_INTFLAG_MASK 0x3333ul /**< \brief (I2S_INTFLAG) MASK Register */ - -/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */ - uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */ - uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */ - uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */ - uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */ - uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */ - uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */ - uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} I2S_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */ -#define I2S_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */ - -#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */ -#define I2S_SYNCBUSY_SWRST (0x1ul << I2S_SYNCBUSY_SWRST_Pos) -#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */ -#define I2S_SYNCBUSY_ENABLE (0x1ul << I2S_SYNCBUSY_ENABLE_Pos) -#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */ -#define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos) -#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */ -#define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos) -#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */ -#define I2S_SYNCBUSY_CKEN_Msk (0x3ul << I2S_SYNCBUSY_CKEN_Pos) -#define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))) -#define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */ -#define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos) -#define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */ -#define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos) -#define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */ -#define I2S_SYNCBUSY_SEREN_Msk (0x3ul << I2S_SYNCBUSY_SEREN_Pos) -#define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))) -#define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */ -#define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos) -#define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */ -#define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos) -#define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */ -#define I2S_SYNCBUSY_DATA_Msk (0x3ul << I2S_SYNCBUSY_DATA_Pos) -#define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))) -#define I2S_SYNCBUSY_MASK 0x033Ful /**< \brief (I2S_SYNCBUSY) MASK Register */ - -/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */ - uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */ - uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */ - uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ - uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ - uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ - uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ - uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ - uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ - uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ - uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ - uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ - uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ - uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ - uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ - uint32_t MONO:1; /*!< bit: 24 Mono Mode */ - uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ - uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} I2S_SERCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */ -#define I2S_SERCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */ - -#define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */ -#define I2S_SERCTRL_SERMODE_Msk (0x3ul << I2S_SERCTRL_SERMODE_Pos) -#define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))) -#define I2S_SERCTRL_SERMODE_RX_Val 0x0ul /**< \brief (I2S_SERCTRL) Receive */ -#define I2S_SERCTRL_SERMODE_TX_Val 0x1ul /**< \brief (I2S_SERCTRL) Transmit */ -#define I2S_SERCTRL_SERMODE_PDM2_Val 0x2ul /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */ -#define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos) -#define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos) -#define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos) -#define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */ -#define I2S_SERCTRL_TXDEFAULT_Msk (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos) -#define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))) -#define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Output Default Value is 0 */ -#define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Output Default Value is 1 */ -#define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3ul /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */ -#define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos) -#define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos) -#define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos) -#define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */ -#define I2S_SERCTRL_TXSAME (0x1ul << I2S_SERCTRL_TXSAME_Pos) -#define I2S_SERCTRL_TXSAME_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */ -#define I2S_SERCTRL_TXSAME_SAME_Val 0x1ul /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */ -#define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos) -#define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos) -#define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */ -#define I2S_SERCTRL_CLKSEL (0x1ul << I2S_SERCTRL_CLKSEL_Pos) -#define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0ul /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */ -#define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1ul /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */ -#define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos) -#define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos) -#define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */ -#define I2S_SERCTRL_SLOTADJ (0x1ul << I2S_SERCTRL_SLOTADJ_Pos) -#define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */ -#define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */ -#define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos) -#define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos) -#define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */ -#define I2S_SERCTRL_DATASIZE_Msk (0x7ul << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))) -#define I2S_SERCTRL_DATASIZE_32_Val 0x0ul /**< \brief (I2S_SERCTRL) 32 bits */ -#define I2S_SERCTRL_DATASIZE_24_Val 0x1ul /**< \brief (I2S_SERCTRL) 24 bits */ -#define I2S_SERCTRL_DATASIZE_20_Val 0x2ul /**< \brief (I2S_SERCTRL) 20 bits */ -#define I2S_SERCTRL_DATASIZE_18_Val 0x3ul /**< \brief (I2S_SERCTRL) 18 bits */ -#define I2S_SERCTRL_DATASIZE_16_Val 0x4ul /**< \brief (I2S_SERCTRL) 16 bits */ -#define I2S_SERCTRL_DATASIZE_16C_Val 0x5ul /**< \brief (I2S_SERCTRL) 16 bits compact stereo */ -#define I2S_SERCTRL_DATASIZE_8_Val 0x6ul /**< \brief (I2S_SERCTRL) 8 bits */ -#define I2S_SERCTRL_DATASIZE_8C_Val 0x7ul /**< \brief (I2S_SERCTRL) 8 bits compact stereo */ -#define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos) -#define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */ -#define I2S_SERCTRL_WORDADJ (0x1ul << I2S_SERCTRL_WORDADJ_Pos) -#define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in word */ -#define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in word */ -#define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos) -#define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos) -#define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */ -#define I2S_SERCTRL_EXTEND_Msk (0x3ul << I2S_SERCTRL_EXTEND_Pos) -#define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))) -#define I2S_SERCTRL_EXTEND_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Extend with zeroes */ -#define I2S_SERCTRL_EXTEND_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Extend with ones */ -#define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2ul /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */ -#define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3ul /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */ -#define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos) -#define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos) -#define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos) -#define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos) -#define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */ -#define I2S_SERCTRL_BITREV (0x1ul << I2S_SERCTRL_BITREV_Pos) -#define I2S_SERCTRL_BITREV_MSBIT_Val 0x0ul /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */ -#define I2S_SERCTRL_BITREV_LSBIT_Val 0x1ul /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */ -#define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos) -#define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos) -#define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos) -#define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos) -#define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos) -#define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos) -#define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos) -#define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos) -#define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos) -#define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos) -#define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */ -#define I2S_SERCTRL_SLOTDIS_Msk (0xFFul << I2S_SERCTRL_SLOTDIS_Pos) -#define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))) -#define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */ -#define I2S_SERCTRL_MONO (0x1ul << I2S_SERCTRL_MONO_Pos) -#define I2S_SERCTRL_MONO_STEREO_Val 0x0ul /**< \brief (I2S_SERCTRL) Normal mode */ -#define I2S_SERCTRL_MONO_MONO_Val 0x1ul /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */ -#define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos) -#define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos) -#define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */ -#define I2S_SERCTRL_DMA (0x1ul << I2S_SERCTRL_DMA_Pos) -#define I2S_SERCTRL_DMA_SINGLE_Val 0x0ul /**< \brief (I2S_SERCTRL) Single DMA channel */ -#define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1ul /**< \brief (I2S_SERCTRL) One DMA channel per data channel */ -#define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos) -#define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos) -#define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */ -#define I2S_SERCTRL_RXLOOP (0x1ul << I2S_SERCTRL_RXLOOP_Pos) -#define I2S_SERCTRL_MASK 0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */ - -/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} I2S_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */ -#define I2S_DATA_RESETVALUE 0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */ - -#define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */ -#define I2S_DATA_DATA_Msk (0xFFFFFFFFul << I2S_DATA_DATA_Pos) -#define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))) -#define I2S_DATA_MASK 0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */ - -/** \brief I2S hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - RoReg8 Reserved1[0x3]; - __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */ - __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ - RoReg8 Reserved2[0x2]; - __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */ - RoReg8 Reserved3[0x2]; - __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x2]; - __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */ - RoReg8 Reserved5[0x6]; - __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */ - RoReg8 Reserved6[0x8]; - __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */ -} I2s; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_I2S_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h deleted file mode 100644 index 75c35112211..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h +++ /dev/null @@ -1,399 +0,0 @@ -/** - * \file - * - * \brief Component description for MTB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_MTB_COMPONENT_ -#define _SAMD21_MTB_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR MTB */ -/* ========================================================================== */ -/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */ -/*@{*/ - -#define MTB_U2002 -#define REV_MTB 0x100 - -/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ - uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_POSITION_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */ - -#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */ -#define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos) -#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */ -#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos) -#define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))) -#define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */ - -/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ - uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ - uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ - uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ - uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ - uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ - uint32_t :21; /*!< bit: 10..30 Reserved */ - uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_MASTER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */ -#define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */ - -#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */ -#define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos) -#define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))) -#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */ -#define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos) -#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */ -#define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos) -#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */ -#define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos) -#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */ -#define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos) -#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */ -#define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos) -#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */ -#define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos) -#define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */ - -/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ - uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_FLOW_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */ -#define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */ - -#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */ -#define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos) -#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */ -#define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos) -#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */ -#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos) -#define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))) -#define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */ - -/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_BASE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */ -#define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */ - -/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_ITCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */ -#define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */ - -/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CLAIMSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */ -#define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */ - -/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CLAIMCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */ -#define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */ - -/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_LOCKACCESS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */ -#define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */ - -/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_LOCKSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */ -#define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */ - -/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_AUTHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */ -#define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */ - -/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVARCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */ -#define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */ - -/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */ -#define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */ - -/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVTYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */ -#define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */ - -/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID4_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */ -#define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */ - -/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID5_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */ -#define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */ - -/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID6_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */ -#define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */ - -/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID7_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */ -#define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */ - -/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */ -#define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */ - -/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */ -#define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */ - -/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */ -#define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */ - -/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */ -#define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */ - -/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */ -#define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */ - -/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */ -#define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */ - -/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */ -#define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */ - -/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */ -#define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */ - -/** \brief MTB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ - __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ - __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ - __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ - RoReg8 Reserved1[0xEF0]; - __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ - RoReg8 Reserved2[0x9C]; - __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ - __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ - RoReg8 Reserved3[0x8]; - __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ - __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ - __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ - __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ - RoReg8 Reserved4[0x8]; - __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ - __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ - __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ - __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ - __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ - __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ - __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ - __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ - __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ - __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ - __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ - __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ - __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ - __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ -} Mtb; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_MTB_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h deleted file mode 100644 index 143af0a0ecc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h +++ /dev/null @@ -1,623 +0,0 @@ -/** - * \file - * - * \brief Component description for NVMCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_NVMCTRL_COMPONENT_ -#define _SAMD21_NVMCTRL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR NVMCTRL */ -/* ========================================================================== */ -/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */ -/*@{*/ - -#define NVMCTRL_U2207 -#define REV_NVMCTRL 0x201 - -/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CMD:7; /*!< bit: 0.. 6 Command */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ -#define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ - -#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */ -#define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))) -#define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ -#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ -#define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */ -#define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */ -#define NVMCTRL_CTRLA_CMD_RWWEEER_Val 0x1Aul /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_RWWEEWP_Val 0x1Cul /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */ -#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */ -#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */ -#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */ -#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */ -#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_RWWEEER (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_RWWEEWP (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */ -#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos) -#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))) -#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */ -#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos) -#define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */ - -/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t MANW:1; /*!< bit: 7 Manual Write */ - uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ - uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ -#define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ - -#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */ -#define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))) -#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */ -#define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */ -#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))) -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */ -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */ -#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */ -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */ -#define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))) -#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */ -#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */ -#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */ -#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */ -#define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos) -#define NVMCTRL_CTRLB_MASK 0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */ - -/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ - uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_PARAM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ -#define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ - -#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ -#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos) -#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))) -#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ -#define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))) -#define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */ -#define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */ -#define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */ -#define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */ -#define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */ -#define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */ -#define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */ -#define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */ -#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_RWWEEP_Pos 20 /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */ -#define NVMCTRL_PARAM_RWWEEP_Msk (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos) -#define NVMCTRL_PARAM_RWWEEP(value) ((NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))) -#define NVMCTRL_PARAM_MASK 0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */ - -/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ -#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ - -#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */ -#define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos) -#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */ -#define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos) -#define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */ - -/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ -#define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ - -#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */ -#define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos) -#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */ -#define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos) -#define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */ - -/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready */ - uint8_t ERROR:1; /*!< bit: 1 Error */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ -#define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */ -#define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos) -#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */ -#define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos) -#define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */ - -/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ - uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ - uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ - uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ - uint16_t NVME:1; /*!< bit: 4 NVM Error */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t SB:1; /*!< bit: 8 Security Bit Status */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */ -#define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */ - -#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ -#define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos) -#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ -#define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos) -#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */ -#define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos) -#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */ -#define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos) -#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */ -#define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos) -#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */ -#define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos) -#define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */ - -/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */ -#define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */ - -#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ -#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos) -#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))) -#define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */ - -/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_LOCK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */ - -#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */ -#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos) -#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))) -#define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */ - -/** \brief NVMCTRL APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - RoReg8 Reserved1[0x2]; - __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ - __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ - __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - RoReg8 Reserved2[0x3]; - __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ - RoReg8 Reserved3[0x3]; - __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x3]; - __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ - RoReg8 Reserved5[0x2]; - __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ - __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ -} Nvmctrl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_NVMCTRL_CAL -#define SECTION_NVMCTRL_LOCKBIT -#define SECTION_NVMCTRL_OTP1 -#define SECTION_NVMCTRL_OTP2 -#define SECTION_NVMCTRL_OTP4 -#define SECTION_NVMCTRL_TEMP_LOG -#define SECTION_NVMCTRL_USER - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ -/* ************************************************************************** */ -/** \addtogroup fuses_api Peripheral Software API */ -/*@{*/ - - -#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4) -#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */ -#define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos) -#define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))) - -#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4 -#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */ -#define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos) -#define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))) - -#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4) -#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */ -#define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos) -#define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))) - -#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER -#define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */ -#define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos) -#define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))) - -#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER -#define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */ -#define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos) -#define FUSES_BOD33_ACTION(value) ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))) - -#define FUSES_BOD33_EN_ADDR NVMCTRL_USER -#define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */ -#define FUSES_BOD33_EN_Msk (0x1ul << FUSES_BOD33_EN_Pos) - -#define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4) -#define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ -#define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos) - -#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4) -#define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */ -#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos) -#define FUSES_DFLL48M_COARSE_CAL(value) ((FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))) - -#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8) -#define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */ -#define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos) -#define FUSES_DFLL48M_FINE_CAL(value) ((FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))) - -#define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */ -#define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos) -#define FUSES_HOT_ADC_VAL(value) ((FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))) - -#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ -#define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos) -#define FUSES_HOT_INT1V_VAL(value) ((FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))) - -#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG -#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ -#define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos) -#define FUSES_HOT_TEMP_VAL_DEC(value) ((FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))) - -#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG -#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ -#define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos) -#define FUSES_HOT_TEMP_VAL_INT(value) ((FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))) - -#define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4) -#define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */ -#define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos) -#define FUSES_OSC32K_CAL(value) ((FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))) - -#define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */ -#define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos) -#define FUSES_ROOM_ADC_VAL(value) ((FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))) - -#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ -#define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos) -#define FUSES_ROOM_INT1V_VAL(value) ((FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))) - -#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ -#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos) -#define FUSES_ROOM_TEMP_VAL_DEC(value) ((FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))) - -#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ -#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos) -#define FUSES_ROOM_TEMP_VAL_INT(value) ((FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))) - -#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER -#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */ -#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos) -#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))) - -#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER -#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */ -#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos) -#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))) - -/* Compatible definition for previous driver (begin 1) */ -#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */ -#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos) -#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos))) - -#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ -#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos) -#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos))) - -#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG -#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ -#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos) -#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos))) - -#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG -#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ -#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos) -#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos))) -/* Compatible definition for previous driver (end 1) */ - -#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */ -#define NVMCTRL_FUSES_NVMP_Msk (0x1FFFul << NVMCTRL_FUSES_NVMP_Pos) -#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos))) - -#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */ -#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos) -#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos))) - -#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */ -#define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos) -#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))) - -#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4) -#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */ -#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos) -#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))) - -#define NVMCTRL_FUSES_RWWEEP_ADDR (NVMCTRL_OTP1 + 4) -#define NVMCTRL_FUSES_RWWEEP_Pos 0 /**< \brief (NVMCTRL_OTP1) RWW EEPROM */ -#define NVMCTRL_FUSES_RWWEEP_Msk (0xFFul << NVMCTRL_FUSES_RWWEEP_Pos) -#define NVMCTRL_FUSES_RWWEEP(value) ((NVMCTRL_FUSES_RWWEEP_Msk & ((value) << NVMCTRL_FUSES_RWWEEP_Pos))) - -/* Compatible definition for previous driver (begin 2) */ -#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */ -#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos) -#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos))) - -#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG -#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ -#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos) -#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos))) - -#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG -#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ -#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos) -#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos))) - -#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG -#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ -#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos) -#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos))) - -#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER -#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */ -#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos) -#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos))) - -#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER -#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */ -#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos) -#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos))) - -#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER -#define SYSCTRL_FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */ -#define SYSCTRL_FUSES_BOD33_EN_Msk (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos) - -#define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4) -#define SYSCTRL_FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ -#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos) - -#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4) -#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */ -#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos) -#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos))) - -#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4) -#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */ -#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos) -#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos))) -/* Compatible definition for previous driver (end 2) */ - -#define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4) -#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */ -#define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos) -#define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))) - -#define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4) -#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */ -#define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos) -#define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))) - -#define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4) -#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */ -#define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos) -#define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))) - -#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER -#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */ -#define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos) - -#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER -#define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */ -#define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos) - -#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ -#define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos) -#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))) - -#define WDT_FUSES_PER_ADDR NVMCTRL_USER -#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */ -#define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos) -#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))) - -#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ -#define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos) - -#define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER -#define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */ -#define WDT_FUSES_WINDOW_0_Msk (0x1ul << WDT_FUSES_WINDOW_0_Pos) - -#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */ -#define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos) -#define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))) - -/*@}*/ - -#endif /* _SAMD21_NVMCTRL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h deleted file mode 100644 index 43b8a4f792d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * \brief Component description for PAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_PAC_COMPONENT_ -#define _SAMD21_PAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_PAC Peripheral Access Controller */ -/*@{*/ - -#define PAC_U2211 -#define REV_PAC 0x101 - -/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_WPCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */ -#define PAC_WPCLR_RESETVALUE 0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */ - -#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */ -#define PAC_WPCLR_WP_Msk (0x7FFFFFFFul << PAC_WPCLR_WP_Pos) -#define PAC_WPCLR_WP(value) ((PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))) -#define PAC_WPCLR_MASK 0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */ - -/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_WPSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */ -#define PAC_WPSET_RESETVALUE 0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */ - -#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */ -#define PAC_WPSET_WP_Msk (0x7FFFFFFFul << PAC_WPSET_WP_Pos) -#define PAC_WPSET_WP(value) ((PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))) -#define PAC_WPSET_MASK 0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */ - -/** \brief PAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ - __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ -} Pac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_PAC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h deleted file mode 100644 index 1dde1771ba7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h +++ /dev/null @@ -1,561 +0,0 @@ -/** - * \file - * - * \brief Component description for PM - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_PM_COMPONENT_ -#define _SAMD21_PM_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PM */ -/* ========================================================================== */ -/** \addtogroup SAMD21_PM Power Manager */ -/*@{*/ - -#define PM_U2206 -#define REV_PM 0x211 - -/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint8_t reg; /*!< Type used for register access */ -} PM_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */ -#define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */ - -#define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */ - -/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_SLEEP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */ -#define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */ - -#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */ -#define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos) -#define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))) -#define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */ -#define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */ -#define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */ -#define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos) -#define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos) -#define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos) -#define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */ - -/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W 8) External Reset Controller -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_EXTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_EXTCTRL_OFFSET 0x02 /**< \brief (PM_EXTCTRL offset) External Reset Controller */ -#define PM_EXTCTRL_RESETVALUE 0x00ul /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */ - -#define PM_EXTCTRL_SETDIS_Pos 0 /**< \brief (PM_EXTCTRL) External Reset Disable */ -#define PM_EXTCTRL_SETDIS (0x1ul << PM_EXTCTRL_SETDIS_Pos) -#define PM_EXTCTRL_MASK 0x01ul /**< \brief (PM_EXTCTRL) MASK Register */ - -/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_CPUSEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */ -#define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */ - -#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */ -#define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))) -#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */ -#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */ -#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */ -#define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */ -#define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */ -#define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */ -#define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */ -#define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */ -#define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */ - -/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_APBASEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */ -#define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */ - -#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */ -#define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))) -#define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */ -#define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */ -#define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */ -#define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */ -#define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */ -#define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */ -#define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */ -#define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */ -#define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */ - -/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_APBBSEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */ -#define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */ - -#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */ -#define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))) -#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */ -#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */ -#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */ -#define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */ -#define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */ -#define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */ -#define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */ -#define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */ -#define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */ - -/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_APBCSEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */ -#define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */ - -#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */ -#define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))) -#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */ -#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */ -#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */ -#define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */ -#define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */ -#define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */ -#define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */ -#define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */ -#define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */ - -/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ - uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ - uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ - uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ - uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ - uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ - uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PM_AHBMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */ -#define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */ - -#define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */ -#define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos) -#define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */ -#define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos) -#define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */ -#define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos) -#define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */ -#define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos) -#define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */ -#define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos) -#define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */ -#define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos) -#define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */ -#define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos) -#define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */ - -/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ - uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ - uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ - uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ - uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ - uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ - uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PM_APBAMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */ -#define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */ - -#define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */ -#define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos) -#define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */ -#define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos) -#define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */ -#define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos) -#define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */ -#define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos) -#define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */ -#define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos) -#define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */ -#define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos) -#define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */ -#define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos) -#define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */ - -/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ - uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ - uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ - uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ - uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ - uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ - uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PM_APBBMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */ -#define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */ - -#define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */ -#define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos) -#define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */ -#define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos) -#define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */ -#define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos) -#define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */ -#define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos) -#define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */ -#define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos) -#define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */ -#define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos) -#define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */ -#define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos) -#define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */ - -/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ - uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ - uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ - uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ - uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ - uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ - uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ - uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ - uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ - uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ - uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ - uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ - uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ - uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ - uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */ - uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */ - uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ - uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ - uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */ - uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ - uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */ - uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */ - uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PM_APBCMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */ -#define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */ - -#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */ -#define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos) -#define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */ -#define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos) -#define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */ -#define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos) -#define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */ -#define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos) -#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */ -#define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos) -#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */ -#define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos) -#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */ -#define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos) -#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */ -#define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos) -#define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */ -#define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos) -#define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */ -#define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos) -#define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */ -#define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos) -#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */ -#define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos) -#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */ -#define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos) -#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */ -#define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos) -#define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */ -#define PM_APBCMASK_TC6 (0x1ul << PM_APBCMASK_TC6_Pos) -#define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */ -#define PM_APBCMASK_TC7 (0x1ul << PM_APBCMASK_TC7_Pos) -#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */ -#define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos) -#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */ -#define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos) -#define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */ -#define PM_APBCMASK_DAC (0x1ul << PM_APBCMASK_DAC_Pos) -#define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */ -#define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos) -#define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */ -#define PM_APBCMASK_I2S (0x1ul << PM_APBCMASK_I2S_Pos) -#define PM_APBCMASK_AC1_Pos 21 /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */ -#define PM_APBCMASK_AC1 (0x1ul << PM_APBCMASK_AC1_Pos) -#define PM_APBCMASK_LINCTRL_Pos 22 /**< \brief (PM_APBCMASK) LINCTRL APB Clock Enable */ -#define PM_APBCMASK_LINCTRL (0x1ul << PM_APBCMASK_LINCTRL_Pos) -#define PM_APBCMASK_MASK 0x007FFFFFul /**< \brief (PM_APBCMASK) MASK Register */ - -/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */ -#define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */ - -#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */ -#define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos) -#define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */ - -/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */ -#define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */ - -#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */ -#define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos) -#define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */ - -/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */ -#define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */ -#define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos) -#define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */ - -/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t POR:1; /*!< bit: 0 Power On Reset */ - uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ - uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EXT:1; /*!< bit: 4 External Reset */ - uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ - uint8_t SYST:1; /*!< bit: 6 System Reset Request */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_RCAUSE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */ -#define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */ - -#define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */ -#define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos) -#define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */ -#define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos) -#define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */ -#define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos) -#define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */ -#define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos) -#define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */ -#define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos) -#define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */ -#define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos) -#define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */ - -/** \brief PM hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ - __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */ - RoReg8 Reserved1[0x5]; - __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ - __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ - __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ - __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ - RoReg8 Reserved2[0x8]; - __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ - __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ - __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ - __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ - RoReg8 Reserved3[0x10]; - __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ - __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ - __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ -} Pm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_PM_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h deleted file mode 100644 index 5d357d6e278..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h +++ /dev/null @@ -1,398 +0,0 @@ -/** - * \file - * - * \brief Component description for PORT - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_PORT_COMPONENT_ -#define _SAMD21_PORT_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PORT */ -/* ========================================================================== */ -/** \addtogroup SAMD21_PORT Port Module */ -/*@{*/ - -#define PORT_U2210 -#define REV_PORT 0x100 - -/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_DIR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */ -#define PORT_DIR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */ - -#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */ -#define PORT_DIR_DIR_Msk (0xFFFFFFFFul << PORT_DIR_DIR_Pos) -#define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))) -#define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */ - -/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */ -#define PORT_DIRCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */ - -#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */ -#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos) -#define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))) -#define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */ - -/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */ -#define PORT_DIRSET_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */ - -#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */ -#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos) -#define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))) -#define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */ - -/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRTGL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */ -#define PORT_DIRTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */ - -#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */ -#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos) -#define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))) -#define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */ - -/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_OUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */ -#define PORT_OUT_RESETVALUE 0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */ - -#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */ -#define PORT_OUT_OUT_Msk (0xFFFFFFFFul << PORT_OUT_OUT_Pos) -#define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))) -#define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */ - -/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */ -#define PORT_OUTCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */ - -#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */ -#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos) -#define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))) -#define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */ - -/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */ -#define PORT_OUTSET_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */ - -#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */ -#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos) -#define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))) -#define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */ - -/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTTGL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */ -#define PORT_OUTTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */ - -#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */ -#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos) -#define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))) -#define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */ - -/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_IN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */ -#define PORT_IN_RESETVALUE 0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */ - -#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */ -#define PORT_IN_IN_Msk (0xFFFFFFFFul << PORT_IN_IN_Pos) -#define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))) -#define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */ - -/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */ -#define PORT_CTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */ - -#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */ -#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos) -#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))) -#define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */ - -/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ - uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ - uint32_t INEN:1; /*!< bit: 17 Input Enable */ - uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ - uint32_t :3; /*!< bit: 19..21 Reserved */ - uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ - uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ - uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_WRCONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */ -#define PORT_WRCONFIG_RESETVALUE 0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */ - -#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */ -#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos) -#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))) -#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */ -#define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos) -#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */ -#define PORT_WRCONFIG_INEN (0x1ul << PORT_WRCONFIG_INEN_Pos) -#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */ -#define PORT_WRCONFIG_PULLEN (0x1ul << PORT_WRCONFIG_PULLEN_Pos) -#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */ -#define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos) -#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */ -#define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos) -#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))) -#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */ -#define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos) -#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */ -#define PORT_WRCONFIG_WRPINCFG (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos) -#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */ -#define PORT_WRCONFIG_HWSEL (0x1ul << PORT_WRCONFIG_HWSEL_Pos) -#define PORT_WRCONFIG_MASK 0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */ - -/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */ - uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PORT_PMUX_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */ -#define PORT_PMUX_RESETVALUE 0x00ul /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */ - -#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */ -#define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))) -#define PORT_PMUX_PMUXE_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */ -#define PORT_PMUX_PMUXE_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */ -#define PORT_PMUX_PMUXE_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */ -#define PORT_PMUX_PMUXE_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */ -#define PORT_PMUX_PMUXE_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */ -#define PORT_PMUX_PMUXE_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */ -#define PORT_PMUX_PMUXE_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */ -#define PORT_PMUX_PMUXE_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */ -#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */ -#define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))) -#define PORT_PMUX_PMUXO_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */ -#define PORT_PMUX_PMUXO_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */ -#define PORT_PMUX_PMUXO_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */ -#define PORT_PMUX_PMUXO_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */ -#define PORT_PMUX_PMUXO_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */ -#define PORT_PMUX_PMUXO_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */ -#define PORT_PMUX_PMUXO_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */ -#define PORT_PMUX_PMUXO_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */ -#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_MASK 0xFFul /**< \brief (PORT_PMUX) MASK Register */ - -/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ - uint8_t INEN:1; /*!< bit: 1 Input Enable */ - uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PORT_PINCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */ -#define PORT_PINCFG_RESETVALUE 0x00ul /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */ - -#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */ -#define PORT_PINCFG_PMUXEN (0x1ul << PORT_PINCFG_PMUXEN_Pos) -#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */ -#define PORT_PINCFG_INEN (0x1ul << PORT_PINCFG_INEN_Pos) -#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */ -#define PORT_PINCFG_PULLEN (0x1ul << PORT_PINCFG_PULLEN_Pos) -#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */ -#define PORT_PINCFG_DRVSTR (0x1ul << PORT_PINCFG_DRVSTR_Pos) -#define PORT_PINCFG_MASK 0x47ul /**< \brief (PORT_PINCFG) MASK Register */ - -/** \brief PortGroup hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ - __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ - __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ - __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ - __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ - __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ - __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ - __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ - __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ - __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ - __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ - RoReg8 Reserved1[0x4]; - __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ - __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ - RoReg8 Reserved2[0x20]; -} PortGroup; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief PORT hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ -} Port; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_PORT_IOBUS - -/*@}*/ - -#endif /* _SAMD21_PORT_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h deleted file mode 100644 index eff57382300..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h +++ /dev/null @@ -1,1065 +0,0 @@ -/** - * \file - * - * \brief Component description for RTC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_RTC_COMPONENT_ -#define _SAMD21_RTC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR RTC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_RTC Real-Time Counter */ -/*@{*/ - -#define RTC_U2202 -#define REV_RTC 0x101 - -/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :3; /*!< bit: 4.. 6 Reserved */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE0_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */ -#define RTC_MODE0_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */ - -#define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */ -#define RTC_MODE0_CTRL_SWRST (0x1ul << RTC_MODE0_CTRL_SWRST_Pos) -#define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */ -#define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos) -#define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */ -#define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos) -#define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))) -#define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */ -#define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */ -#define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */ -#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos) -#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos) -#define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos) -#define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */ -#define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos) -#define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */ -#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))) -#define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_MASK 0x0F8Ful /**< \brief (RTC_MODE0_CTRL) MASK Register */ - -/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */ -#define RTC_MODE1_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */ - -#define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */ -#define RTC_MODE1_CTRL_SWRST (0x1ul << RTC_MODE1_CTRL_SWRST_Pos) -#define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */ -#define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos) -#define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */ -#define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos) -#define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))) -#define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */ -#define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */ -#define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */ -#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos) -#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos) -#define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos) -#define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */ -#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))) -#define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_MASK 0x0F0Ful /**< \brief (RTC_MODE1_CTRL) MASK Register */ - -/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE2_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */ -#define RTC_MODE2_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */ - -#define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */ -#define RTC_MODE2_CTRL_SWRST (0x1ul << RTC_MODE2_CTRL_SWRST_Pos) -#define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */ -#define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos) -#define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */ -#define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos) -#define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))) -#define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */ -#define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */ -#define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */ -#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos) -#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos) -#define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos) -#define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */ -#define RTC_MODE2_CTRL_CLKREP (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos) -#define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */ -#define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos) -#define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */ -#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))) -#define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_MASK 0x0FCFul /**< \brief (RTC_MODE2_CTRL) MASK Register */ - -/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ - uint16_t :8; /*!< bit: 6..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_READREQ_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */ -#define RTC_READREQ_RESETVALUE 0x0010ul /**< \brief (RTC_READREQ reset_value) Read Request */ - -#define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */ -#define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos) -#define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))) -#define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */ -#define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos) -#define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */ -#define RTC_READREQ_RREQ (0x1ul << RTC_READREQ_RREQ_Pos) -#define RTC_READREQ_MASK 0xC03Ful /**< \brief (RTC_READREQ) MASK Register */ - -/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE0_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */ -#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */ - -#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos) -#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos) -#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos) -#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos) -#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos) -#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos) -#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos) -#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos) -#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos) -#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))) -#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */ -#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos) -#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */ -#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos) -#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))) -#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos) -#define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */ - -/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ - uint16_t :5; /*!< bit: 10..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */ -#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */ - -#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos) -#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos) -#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos) -#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos) -#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos) -#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos) -#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos) -#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos) -#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos) -#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))) -#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos) -#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos) -#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos) -#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))) -#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos) -#define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */ - -/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE2_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */ -#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */ - -#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos) -#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos) -#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos) -#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos) -#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos) -#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos) -#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos) -#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos) -#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos) -#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))) -#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */ -#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos) -#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */ -#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos) -#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))) -#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos) -#define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */ - -/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */ -#define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */ - -#define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos) -#define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */ -#define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos) -#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))) -#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */ -#define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos) -#define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos) -#define RTC_MODE0_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */ - -/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */ -#define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */ - -#define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos) -#define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos) -#define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos) -#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))) -#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */ -#define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos) -#define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos) -#define RTC_MODE1_INTENCLR_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */ - -/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */ -#define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */ - -#define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos) -#define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */ -#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos) -#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))) -#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */ -#define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos) -#define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos) -#define RTC_MODE2_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */ - -/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */ -#define RTC_MODE0_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */ - -#define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */ -#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos) -#define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */ -#define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos) -#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))) -#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */ -#define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos) -#define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos) -#define RTC_MODE0_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENSET) MASK Register */ - -/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */ -#define RTC_MODE1_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */ - -#define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos) -#define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos) -#define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos) -#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))) -#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */ -#define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos) -#define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos) -#define RTC_MODE1_INTENSET_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENSET) MASK Register */ - -/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */ -#define RTC_MODE2_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */ - -#define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */ -#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos) -#define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */ -#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos) -#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))) -#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */ -#define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos) -#define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos) -#define RTC_MODE2_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENSET) MASK Register */ - -/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */ -#define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */ - -#define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */ -#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos) -#define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */ -#define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos) -#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))) -#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */ -#define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos) -#define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */ -#define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos) -#define RTC_MODE0_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */ - -/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */ -#define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */ - -#define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */ -#define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos) -#define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */ -#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos) -#define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */ -#define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos) -#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))) -#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */ -#define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos) -#define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */ -#define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos) -#define RTC_MODE1_INTFLAG_MASK 0xC3ul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */ - -/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */ -#define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */ - -#define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */ -#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos) -#define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */ -#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos) -#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))) -#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */ -#define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos) -#define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */ -#define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos) -#define RTC_MODE2_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */ - -/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */ -#define RTC_STATUS_RESETVALUE 0x00ul /**< \brief (RTC_STATUS reset_value) Status */ - -#define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */ -#define RTC_STATUS_SYNCBUSY (0x1ul << RTC_STATUS_SYNCBUSY_Pos) -#define RTC_STATUS_MASK 0x80ul /**< \brief (RTC_STATUS) MASK Register */ - -/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */ -#define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */ - -#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */ -#define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos) -#define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */ - -/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ - uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_FREQCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */ -#define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */ - -#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */ -#define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos) -#define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))) -#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */ -#define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos) -#define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */ - -/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE0_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */ -#define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */ - -#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */ -#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos) -#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))) -#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */ - -/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */ -#define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */ - -#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */ -#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos) -#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))) -#define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */ - -/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE2_CLOCK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */ -#define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */ - -#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */ -#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos) -#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))) -#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */ -#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos) -#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))) -#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */ -#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos) -#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))) -#define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */ -#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos) -#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */ -#define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos) -#define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))) -#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */ -#define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos) -#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))) -#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */ -#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos) -#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))) -#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */ - -/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER:16; /*!< bit: 0..15 Counter Period */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */ -#define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */ - -#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */ -#define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos) -#define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))) -#define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */ - -/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE0_COMP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */ -#define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */ - -#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */ -#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos) -#define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))) -#define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */ - -/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_COMP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */ -#define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */ - -#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */ -#define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos) -#define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))) -#define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */ - -/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE2_ALARM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ -#define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ - -#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ -#define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos) -#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))) -#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ -#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos) -#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))) -#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ -#define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos) -#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))) -#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ -#define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos) -#define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))) -#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ -#define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos) -#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))) -#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ -#define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos) -#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))) -#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */ - -/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_MASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ -#define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ - -#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ -#define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))) -#define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ -#define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */ -#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ -#define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ -#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ -#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ -#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ -#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */ - -/** \brief RtcMode2Alarm hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ - __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ - RoReg8 Reserved1[0x3]; -} RtcMode2Alarm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE0 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 32-bit Counter with Single 32-bit Compare */ - __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ - __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ - __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ - __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ -} RtcMode0; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE1 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 16-bit Counter with Two 16-bit Compares */ - __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ - __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ - __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ - __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ - RoReg8 Reserved3[0x2]; - __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ - RoReg8 Reserved4[0x2]; - __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ -} RtcMode1; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE2 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* Clock/Calendar with Alarm */ - __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ - __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ - __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ - __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ - RoReg8 Reserved3[0x4]; - RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ -} RtcMode2; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ - RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ - RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ -} Rtc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_RTC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h deleted file mode 100644 index ee0733bea3d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h +++ /dev/null @@ -1,1511 +0,0 @@ -/** - * \file - * - * \brief Component description for SERCOM - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SERCOM_COMPONENT_ -#define _SAMD21_SERCOM_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR SERCOM */ -/* ========================================================================== */ -/** \addtogroup SAMD21_SERCOM Serial Communication Interface */ -/*@{*/ - -#define SERCOM_U2201 -#define REV_SERCOM 0x201 - -/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ -#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ - -#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ -#define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos) -#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ -#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ -#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))) -#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */ -#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */ -#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */ -#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */ -#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */ -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */ -#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ -#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) -#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ -#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos) -#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ -#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) -#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))) -#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ -#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) -#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) -#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ -#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos) -#define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))) -#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ -#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos) -#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ -#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos) -#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))) -#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ -#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) -#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ - -/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ -#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ - -#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ -#define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos) -#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ -#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ -#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))) -#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */ -#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */ -#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */ -#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */ -#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */ -#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */ -#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ -#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) -#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ -#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos) -#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ -#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) -#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))) -#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) -#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ -#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos) -#define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))) -#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ -#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos) -#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ -#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) -#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ - -/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ -#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ - -#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ -#define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos) -#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ -#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos) -#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ -#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))) -#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */ -#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */ -#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */ -#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */ -#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */ -#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */ -#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ -#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) -#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ -#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos) -#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ -#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos) -#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))) -#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ -#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos) -#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))) -#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ -#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos) -#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))) -#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ -#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos) -#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ -#define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos) -#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ -#define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos) -#define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ - -/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :4; /*!< bit: 9..12 Reserved */ - uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ - uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ - uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ -#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ - -#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ -#define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos) -#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ -#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos) -#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ -#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))) -#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */ -#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */ -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */ -#define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */ -#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */ -#define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */ -#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ -#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos) -#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ -#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos) -#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ -#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos) -#define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))) -#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ -#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos) -#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))) -#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ -#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos) -#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))) -#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ -#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos) -#define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))) -#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ -#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos) -#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))) -#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ -#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos) -#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ -#define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos) -#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ -#define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos) -#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */ - -/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ -#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ - -#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ -#define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos) -#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ -#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos) -#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ -#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos) -#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))) -#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ -#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos) -#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ - -/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ - uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ - uint32_t :3; /*!< bit: 11..13 Reserved */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ -#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ - -#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ -#define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos) -#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ -#define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos) -#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ -#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos) -#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ -#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos) -#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))) -#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ -#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos) -#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))) -#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ -#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos) -#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ - -/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ - uint32_t :2; /*!< bit: 7.. 8 Reserved */ - uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ - uint32_t :3; /*!< bit: 10..12 Reserved */ - uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ -#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ - -#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ -#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos) -#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))) -#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ -#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos) -#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ -#define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos) -#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ -#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos) -#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ -#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos) -#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))) -#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ -#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos) -#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ - -/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ - uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ - uint32_t ENC:1; /*!< bit: 10 Encoding Format */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ -#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ - -#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ -#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos) -#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))) -#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ -#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos) -#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ -#define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos) -#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ -#define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos) -#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ -#define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos) -#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ -#define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos) -#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ -#define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos) -#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ -#define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos) -#define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */ - -/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ - uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ - uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ -#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ - -#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ -#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos) -#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))) -#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ -#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos) -#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))) -#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ -#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos) -#define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))) -#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ -#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) -#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))) -#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ - -/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ -#define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ - -#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ -#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos) -#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))) -#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */ - -/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - struct { // FRAC mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRAC; /*!< Structure used for FRAC */ - struct { // FRACFP mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRACFP; /*!< Structure used for FRACFP */ - struct { // USARTFP mode - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } USARTFP; /*!< Structure used for USARTFP */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ -#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ - -#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ -#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos) -#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))) -#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */ - -// FRAC mode -#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ -#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos) -#define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))) -#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ -#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos) -#define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))) -#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ - -// FRACFP mode -#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ -#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) -#define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))) -#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ -#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos) -#define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))) -#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ - -// USARTFP mode -#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ -#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) -#define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))) -#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ - -/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_RXPL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ -#define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ - -#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ -#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos) -#define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))) -#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */ - -/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ -#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ - -#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos) -#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos) -#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos) -#define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ - -/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ -#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ - -#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos) -#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos) -#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos) -#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos) -#define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ - -/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ -#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ - -#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos) -#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos) -#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos) -#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos) -#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos) -#define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ - -/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ -#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ - -#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ -#define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos) -#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ -#define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos) -#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos) -#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos) -#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ -#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos) -#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos) -#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos) -#define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ - -/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ -#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ - -#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos) -#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos) -#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos) -#define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ - -/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ -#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ - -#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos) -#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos) -#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos) -#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos) -#define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ - -/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ -#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ - -#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ -#define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos) -#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ -#define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos) -#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ -#define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos) -#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ -#define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos) -#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos) -#define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ - -/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ -#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ - -#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ -#define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos) -#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ -#define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos) -#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos) -#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos) -#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ -#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos) -#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos) -#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos) -#define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */ - -/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ -#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ - -#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ -#define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos) -#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ -#define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos) -#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ -#define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos) -#define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ - -/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ -#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ - -#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ -#define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos) -#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ -#define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos) -#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ -#define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos) -#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ -#define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos) -#define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ - -/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ -#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ - -#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ -#define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos) -#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ -#define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos) -#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ -#define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos) -#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ -#define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos) -#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ -#define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos) -#define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ - -/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ -#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ - -#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ -#define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos) -#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ -#define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos) -#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ -#define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos) -#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ -#define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos) -#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ -#define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos) -#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ -#define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos) -#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ -#define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos) -#define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ - -/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t LENERR:1; /*!< bit: 10 Length Error */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ -#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ - -#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ -#define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos) -#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ -#define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos) -#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ -#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos) -#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ -#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos) -#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))) -#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ -#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos) -#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ -#define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos) -#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ -#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) -#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) -#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ -#define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos) -#define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ - -/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ - uint16_t SR:1; /*!< bit: 4 Repeated Start */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t :1; /*!< bit: 8 Reserved */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t HS:1; /*!< bit: 10 High Speed */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ -#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ - -#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ -#define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos) -#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ -#define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos) -#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ -#define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos) -#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ -#define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos) -#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ -#define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos) -#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ -#define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos) -#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ -#define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos) -#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) -#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ -#define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos) -#define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ - -/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t :13; /*!< bit: 3..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_SPI_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ -#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ - -#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ -#define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos) -#define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */ - -/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PERR:1; /*!< bit: 0 Parity Error */ - uint16_t FERR:1; /*!< bit: 1 Frame Error */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t CTS:1; /*!< bit: 3 Clear To Send */ - uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ - uint16_t COLL:1; /*!< bit: 5 Collision Detected */ - uint16_t :10; /*!< bit: 6..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ -#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ - -#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ -#define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos) -#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ -#define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos) -#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ -#define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos) -#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ -#define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos) -#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ -#define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos) -#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ -#define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos) -#define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */ - -/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */ -#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */ - -#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) -#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) -#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) -#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */ -#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */ - -#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) -#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) -#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */ -#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */ - -#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos) -#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) -#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) -#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */ -#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */ - -#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos) -#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos) -#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos) -#define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t LENEN:1; /*!< bit: 13 Length Enable */ - uint32_t HS:1; /*!< bit: 14 High Speed Mode */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t LEN:8; /*!< bit: 16..23 Length */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ -#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ - -#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ -#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos) -#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))) -#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ -#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos) -#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ -#define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos) -#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ -#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos) -#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ -#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos) -#define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))) -#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ - -/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ - uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ - uint32_t :4; /*!< bit: 11..14 Reserved */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ -#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ - -#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ -#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos) -#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ -#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos) -#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))) -#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ -#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos) -#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ -#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos) -#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))) -#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ - -/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ -#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ - -#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ -#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos) -#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))) -#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ -#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos) -#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))) -#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */ - -/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ -#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ - -#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ -#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos) -#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))) -#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */ - -/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ -#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ - -#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ -#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos) -#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))) -#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */ - -/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint32_t :23; /*!< bit: 9..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ -#define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ - -#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ -#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos) -#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))) -#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */ - -/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ -#define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ - -#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ -#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos) -#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))) -#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */ - -/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ -#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ - -#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ -#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ - -/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ -#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ - -#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ -#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ - -/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ -#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ - -#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ -#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ - -/** \brief SERCOM_I2CM hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* I2C Master Mode */ - __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ - __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ - RoReg8 Reserved2[0x4]; - __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ - __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ - __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ - RoReg8 Reserved7[0x7]; - __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ -} SercomI2cm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_I2CS hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* I2C Slave Mode */ - __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ - __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ - RoReg8 Reserved1[0xC]; - __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ - RoReg8 Reserved2[0x1]; - __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ - __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ - RoReg8 Reserved5[0x4]; - __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ - __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ -} SercomI2cs; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_SPI hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* SPI Mode */ - __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ - __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ - RoReg8 Reserved2[0x7]; - __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ - __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ - __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ - RoReg8 Reserved7[0x4]; - __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ -} SercomSpi; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_USART hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USART Mode */ - __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ - __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ - __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ - RoReg8 Reserved2[0x5]; - __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ - __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ - RoReg8 Reserved6[0x8]; - __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ - RoReg8 Reserved7[0x6]; - __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ -} SercomUsart; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ - SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ - SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ - SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ -} Sercom; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_SERCOM_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h deleted file mode 100644 index 6cd64b6ea98..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h +++ /dev/null @@ -1,951 +0,0 @@ -/** - * \file - * - * \brief Component description for SYSCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SYSCTRL_COMPONENT_ -#define _SAMD21_SYSCTRL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR SYSCTRL */ -/* ========================================================================== */ -/** \addtogroup SAMD21_SYSCTRL System Control */ -/*@{*/ - -#define SYSCTRL_U2100 -#define REV_SYSCTRL 0x201 - -/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */ -#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */ - -#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_XOSCRDY (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos) -#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos) -#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_OSC32KRDY (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos) -#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_OSC8MRDY (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos) -#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLRDY (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos) -#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLOOB (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos) -#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLLCKF (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos) -#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLLCKC (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos) -#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLRCS (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos) -#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_BOD33RDY (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos) -#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */ -#define SYSCTRL_INTENCLR_BOD33DET (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos) -#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_B33SRDY (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos) -#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ -#define SYSCTRL_INTENCLR_DPLLLCKR (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos) -#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ -#define SYSCTRL_INTENCLR_DPLLLCKF (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos) -#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */ -#define SYSCTRL_INTENCLR_DPLLLTO (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos) -#define SYSCTRL_INTENCLR_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */ - -/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */ -#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */ - -#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_XOSCRDY (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos) -#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos) -#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_OSC32KRDY (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos) -#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_OSC8MRDY (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos) -#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLRDY (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos) -#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLOOB (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos) -#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLLCKF (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos) -#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLLCKC (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos) -#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLRCS (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos) -#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_BOD33RDY (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos) -#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */ -#define SYSCTRL_INTENSET_BOD33DET (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos) -#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_B33SRDY (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos) -#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ -#define SYSCTRL_INTENSET_DPLLLCKR (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos) -#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ -#define SYSCTRL_INTENSET_DPLLLCKF (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos) -#define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */ -#define SYSCTRL_INTENSET_DPLLLTO (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos) -#define SYSCTRL_INTENSET_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */ - -/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ -#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */ -#define SYSCTRL_INTFLAG_XOSCRDY (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos) -#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */ -#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos) -#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */ -#define SYSCTRL_INTFLAG_OSC32KRDY (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos) -#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */ -#define SYSCTRL_INTFLAG_OSC8MRDY (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos) -#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */ -#define SYSCTRL_INTFLAG_DFLLRDY (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos) -#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */ -#define SYSCTRL_INTFLAG_DFLLOOB (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos) -#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */ -#define SYSCTRL_INTFLAG_DFLLLCKF (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos) -#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */ -#define SYSCTRL_INTFLAG_DFLLLCKC (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos) -#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */ -#define SYSCTRL_INTFLAG_DFLLRCS (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos) -#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */ -#define SYSCTRL_INTFLAG_BOD33RDY (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos) -#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */ -#define SYSCTRL_INTFLAG_BOD33DET (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos) -#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */ -#define SYSCTRL_INTFLAG_B33SRDY (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos) -#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */ -#define SYSCTRL_INTFLAG_DPLLLCKR (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos) -#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */ -#define SYSCTRL_INTFLAG_DPLLLCKF (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos) -#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */ -#define SYSCTRL_INTFLAG_DPLLLTO (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos) -#define SYSCTRL_INTFLAG_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */ - -/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_PCLKSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */ -#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */ - -#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */ -#define SYSCTRL_PCLKSR_XOSCRDY (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos) -#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */ -#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos) -#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */ -#define SYSCTRL_PCLKSR_OSC32KRDY (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos) -#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */ -#define SYSCTRL_PCLKSR_OSC8MRDY (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos) -#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */ -#define SYSCTRL_PCLKSR_DFLLRDY (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos) -#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */ -#define SYSCTRL_PCLKSR_DFLLOOB (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos) -#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */ -#define SYSCTRL_PCLKSR_DFLLLCKF (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos) -#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */ -#define SYSCTRL_PCLKSR_DFLLLCKC (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos) -#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */ -#define SYSCTRL_PCLKSR_DFLLRCS (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos) -#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */ -#define SYSCTRL_PCLKSR_BOD33RDY (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos) -#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */ -#define SYSCTRL_PCLKSR_BOD33DET (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos) -#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */ -#define SYSCTRL_PCLKSR_B33SRDY (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos) -#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */ -#define SYSCTRL_PCLKSR_DPLLLCKR (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos) -#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */ -#define SYSCTRL_PCLKSR_DPLLLCKF (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos) -#define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */ -#define SYSCTRL_PCLKSR_DPLLLTO (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos) -#define SYSCTRL_PCLKSR_MASK 0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */ - -/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t :3; /*!< bit: 3.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ - uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ - uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SYSCTRL_XOSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define SYSCTRL_XOSC_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ - -#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */ -#define SYSCTRL_XOSC_ENABLE (0x1ul << SYSCTRL_XOSC_ENABLE_Pos) -#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */ -#define SYSCTRL_XOSC_XTALEN (0x1ul << SYSCTRL_XOSC_XTALEN_Pos) -#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */ -#define SYSCTRL_XOSC_RUNSTDBY (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos) -#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */ -#define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos) -#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */ -#define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos))) -#define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */ -#define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */ -#define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */ -#define SYSCTRL_XOSC_GAIN_3_Val 0x3ul /**< \brief (SYSCTRL_XOSC) 16MHz */ -#define SYSCTRL_XOSC_GAIN_4_Val 0x4ul /**< \brief (SYSCTRL_XOSC) 30MHz */ -#define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */ -#define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos) -#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */ -#define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos) -#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos))) -#define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */ - -/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ - uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ - uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SYSCTRL_XOSC32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define SYSCTRL_XOSC32K_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ - -#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */ -#define SYSCTRL_XOSC32K_ENABLE (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos) -#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */ -#define SYSCTRL_XOSC32K_XTALEN (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos) -#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */ -#define SYSCTRL_XOSC32K_EN32K (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos) -#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */ -#define SYSCTRL_XOSC32K_EN1K (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos) -#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */ -#define SYSCTRL_XOSC32K_AAMPEN (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos) -#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */ -#define SYSCTRL_XOSC32K_RUNSTDBY (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos) -#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */ -#define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos) -#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */ -#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos) -#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos))) -#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */ -#define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos) -#define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */ - -/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ - uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ - uint32_t :2; /*!< bit: 4.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_OSC32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ -#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ - -#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */ -#define SYSCTRL_OSC32K_ENABLE (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos) -#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */ -#define SYSCTRL_OSC32K_EN32K (0x1ul << SYSCTRL_OSC32K_EN32K_Pos) -#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */ -#define SYSCTRL_OSC32K_EN1K (0x1ul << SYSCTRL_OSC32K_EN1K_Pos) -#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */ -#define SYSCTRL_OSC32K_RUNSTDBY (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos) -#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */ -#define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos) -#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */ -#define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos) -#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos))) -#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */ -#define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos) -#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */ -#define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos) -#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos))) -#define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */ - -/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SYSCTRL_OSCULP32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ - -#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */ -#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos) -#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos))) -#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */ -#define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos) -#define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */ - -/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_OSC8M_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */ -#define SYSCTRL_OSC8M_RESETVALUE 0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */ - -#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */ -#define SYSCTRL_OSC8M_ENABLE (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos) -#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */ -#define SYSCTRL_OSC8M_RUNSTDBY (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos) -#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */ -#define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos) -#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */ -#define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos))) -#define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */ -#define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */ -#define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */ -#define SYSCTRL_OSC8M_PRESC_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 8 */ -#define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */ -#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos) -#define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos))) -#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */ -#define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos))) -#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */ -#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */ -#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */ -#define SYSCTRL_OSC8M_FRANGE_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */ -#define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_MASK 0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */ - -/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ - uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ - uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ - uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ - uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ - uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ - uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ - uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SYSCTRL_DFLLCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */ -#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */ - -#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */ -#define SYSCTRL_DFLLCTRL_ENABLE (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos) -#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */ -#define SYSCTRL_DFLLCTRL_MODE (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos) -#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */ -#define SYSCTRL_DFLLCTRL_STABLE (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos) -#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */ -#define SYSCTRL_DFLLCTRL_LLAW (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos) -#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */ -#define SYSCTRL_DFLLCTRL_USBCRM (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos) -#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */ -#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos) -#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */ -#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos) -#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */ -#define SYSCTRL_DFLLCTRL_CCDIS (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos) -#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */ -#define SYSCTRL_DFLLCTRL_QLDIS (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos) -#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */ -#define SYSCTRL_DFLLCTRL_BPLCKC (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos) -#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */ -#define SYSCTRL_DFLLCTRL_WAITLOCK (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos) -#define SYSCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */ - -/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ - uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ - uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_DFLLVAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */ -#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */ - -#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */ -#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos) -#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos))) -#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */ -#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos) -#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos))) -#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */ -#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos) -#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos))) -#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */ - -/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ - uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ - uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_DFLLMUL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */ -#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ - -#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */ -#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos) -#define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos))) -#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */ -#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos) -#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos))) -#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */ -#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos) -#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos))) -#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */ - -/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t READREQ:1; /*!< bit: 7 Read Request */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SYSCTRL_DFLLSYNC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */ -#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ - -#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */ -#define SYSCTRL_DFLLSYNC_READREQ (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos) -#define SYSCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */ - -/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t HYST:1; /*!< bit: 2 Hysteresis */ - uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MODE:1; /*!< bit: 8 Operation Mode */ - uint32_t CEN:1; /*!< bit: 9 Clock Enable */ - uint32_t :2; /*!< bit: 10..11 Reserved */ - uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ - uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_BOD33_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */ -#define SYSCTRL_BOD33_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */ - -#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */ -#define SYSCTRL_BOD33_ENABLE (0x1ul << SYSCTRL_BOD33_ENABLE_Pos) -#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */ -#define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos) -#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */ -#define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos) -#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos))) -#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */ -#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */ -#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */ -#define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos) -#define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos) -#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos) -#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */ -#define SYSCTRL_BOD33_RUNSTDBY (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos) -#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */ -#define SYSCTRL_BOD33_MODE (0x1ul << SYSCTRL_BOD33_MODE_Pos) -#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */ -#define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos) -#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */ -#define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos))) -#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */ -#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */ -#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */ -#define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */ -#define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */ -#define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */ -#define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */ -#define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */ -#define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */ -#define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9ul /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */ -#define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAul /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */ -#define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBul /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */ -#define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCul /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */ -#define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDul /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */ -#define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEul /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */ -#define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFul /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */ -#define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */ -#define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos) -#define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos))) -#define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */ - -/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :6; /*!< bit: 0.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t :6; /*!< bit: 7..12 Reserved */ - uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SYSCTRL_VREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */ -#define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */ - -#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */ -#define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos) -#define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */ -#define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos) -#define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */ - -/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ - uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ - uint32_t :13; /*!< bit: 3..15 Reserved */ - uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_VREF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */ -#define SYSCTRL_VREF_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */ - -#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */ -#define SYSCTRL_VREF_TSEN (0x1ul << SYSCTRL_VREF_TSEN_Pos) -#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */ -#define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos) -#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */ -#define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos) -#define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos))) -#define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */ - -/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SYSCTRL_DPLLCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */ -#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */ - -#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */ -#define SYSCTRL_DPLLCTRLA_ENABLE (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos) -#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */ -#define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos) -#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */ -#define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) -#define SYSCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */ - -/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_DPLLRATIO_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */ -#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ - -#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */ -#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos) -#define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos))) -#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ -#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos) -#define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos))) -#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */ - -/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ - uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ - uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ - uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_DPLLCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */ -#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */ - -#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ -#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos))) -#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */ -#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */ -#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */ -#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */ -#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */ -#define SYSCTRL_DPLLCTRLB_LPEN (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos) -#define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */ -#define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos) -#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */ -#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos) -#define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos))) -#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */ -#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */ -#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */ -#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) -#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) -#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */ -#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos))) -#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */ -#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */ -#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */ -#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */ -#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */ -#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */ -#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) -#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */ -#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos) -#define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos))) -#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */ - -/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ - uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ - uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ - uint8_t DIV:1; /*!< bit: 3 Divider Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SYSCTRL_DPLLSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */ -#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */ - -#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */ -#define SYSCTRL_DPLLSTATUS_LOCK (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos) -#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */ -#define SYSCTRL_DPLLSTATUS_CLKRDY (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos) -#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */ -#define SYSCTRL_DPLLSTATUS_ENABLE (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos) -#define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */ -#define SYSCTRL_DPLLSTATUS_DIV (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos) -#define SYSCTRL_DPLLSTATUS_MASK 0x0Ful /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */ - -/** \brief SYSCTRL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ - __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ - __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ - __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ - __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ - RoReg8 Reserved1[0x2]; - __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ - RoReg8 Reserved2[0x2]; - __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ - __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ - RoReg8 Reserved3[0x3]; - __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ - __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ - RoReg8 Reserved4[0x2]; - __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ - __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ - __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ - RoReg8 Reserved5[0x3]; - __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ - RoReg8 Reserved6[0x4]; - __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ - RoReg8 Reserved7[0x2]; - __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ - __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ - RoReg8 Reserved8[0x3]; - __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ - __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ - __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ -} Sysctrl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_SYSCTRL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h deleted file mode 100644 index 5bf0b1f9f66..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h +++ /dev/null @@ -1,687 +0,0 @@ -/** - * \file - * - * \brief Component description for TC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TC_COMPONENT_ -#define _SAMD21_TC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_TC Basic Timer Counter */ -/*@{*/ - -#define TC_U2212 -#define REV_TC 0x131 - -/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ -#define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */ - -#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ -#define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos) -#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ -#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) -#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */ -#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))) -#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */ -#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */ -#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */ -#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */ -#define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))) -#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */ -#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */ -#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */ -#define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */ -#define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ -#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))) -#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */ -#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */ -#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */ -#define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */ -#define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */ -#define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */ -#define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */ -#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */ -#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */ -#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos) -#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ -#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))) -#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */ -#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */ -#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */ -#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */ - -/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ - uint16_t :9; /*!< bit: 5..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_READREQ_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */ -#define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */ - -#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */ -#define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos) -#define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))) -#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */ -#define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos) -#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */ -#define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos) -#define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */ - -/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_CTRLBCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ -#define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ - -#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ -#define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos) -#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */ -#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos) -#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */ -#define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))) -#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */ -#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */ -#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */ -#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */ - -/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_CTRLBSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ -#define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */ - -#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ -#define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos) -#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */ -#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos) -#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */ -#define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))) -#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */ -#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */ -#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */ -#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */ - -/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ - uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ - uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_CTRLC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */ -#define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */ - -#define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */ -#define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos) -#define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */ -#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos) -#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */ -#define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos) -#define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))) -#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */ -#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos) -#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */ -#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos) -#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */ -#define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos) -#define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))) -#define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */ - -/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */ -#define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */ - -#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */ -#define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos) -#define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */ - -/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ - uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ - uint16_t :3; /*!< bit: 9..11 Reserved */ - uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ - uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :12; /*!< bit: 0..11 Reserved */ - uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */ -#define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */ - -#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ -#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))) -#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */ -#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ -#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */ -#define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */ -#define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */ -#define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */ -#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */ -#define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos) -#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */ -#define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos) -#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */ -#define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos) -#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ -#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos) -#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ -#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos) -#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */ -#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos) -#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))) -#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */ - -/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ -#define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */ -#define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos) -#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */ -#define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos) -#define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos) -#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ -#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos) -#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ -#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos) -#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */ -#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos) -#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))) -#define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */ - -/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ -#define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ - -#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */ -#define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos) -#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */ -#define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos) -#define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */ -#define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos) -#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ -#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos) -#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ -#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos) -#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */ -#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos) -#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))) -#define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */ - -/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow */ - uint8_t ERR:1; /*!< bit: 1 Error */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */ -#define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos) -#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */ -#define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos) -#define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */ -#define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos) -#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */ -#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos) -#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */ -#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos) -#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */ -#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos) -#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))) -#define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */ - -/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :3; /*!< bit: 0.. 2 Reserved */ - uint8_t STOP:1; /*!< bit: 3 Stop */ - uint8_t SLAVE:1; /*!< bit: 4 Slave */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */ -#define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */ - -#define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */ -#define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos) -#define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */ -#define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos) -#define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */ -#define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos) -#define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */ - -/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_COUNT16_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */ -#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */ - -#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */ -#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos) -#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))) -#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */ - -/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TC_COUNT32_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */ -#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */ - -#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */ -#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos) -#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))) -#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */ - -/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */ -#define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */ - -#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ -#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos) -#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))) -#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */ - -/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */ -#define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */ - -#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ -#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos) -#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))) -#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */ - -/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_COUNT16_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */ -#define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */ - -#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */ -#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos) -#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))) -#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */ - -/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TC_COUNT32_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */ -#define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */ - -#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */ -#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos) -#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))) -#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */ - -/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */ -#define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */ - -#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */ -#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos) -#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))) -#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */ - -/** \brief TC_COUNT8 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 8-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ - RoReg8 Reserved3[0x3]; - __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ - RoReg8 Reserved4[0x3]; - __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ -} TcCount8; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief TC_COUNT16 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 16-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ - RoReg8 Reserved3[0x6]; - __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ -} TcCount16; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief TC_COUNT32 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 32-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ -} TcCount32; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ - TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ - TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ -} Tc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_TC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h deleted file mode 100644 index fc23a16d11f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h +++ /dev/null @@ -1,1820 +0,0 @@ -/** - * \file - * - * \brief Component description for TCC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TCC_COMPONENT_ -#define _SAMD21_TCC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TCC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_TCC Timer Counter Control */ -/*@{*/ - -#define TCC_U2213 -#define REV_TCC 0x121 - -/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t :3; /*!< bit: 2.. 4 Reserved */ - uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ - uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ - uint32_t :9; /*!< bit: 15..23 Reserved */ - uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ - uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ - uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ - uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :24; /*!< bit: 0..23 Reserved */ - uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ -#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */ - -#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ -#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos) -#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ -#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos) -#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ -#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))) -#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */ -#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ -#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ -#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ -#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ -#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))) -#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */ -#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */ -#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */ -#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */ -#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */ -#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */ -#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */ -#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */ -#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ -#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos) -#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ -#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))) -#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ -#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ -#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ -#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ -#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos) -#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ -#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) -#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ -#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) -#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ -#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) -#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ -#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) -#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ -#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos) -#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))) -#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */ - -/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_CTRLBCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ -#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ - -#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ -#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos) -#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ -#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos) -#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ -#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos) -#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ -#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))) -#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ -#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ -#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ -#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ -#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ -#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))) -#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */ -#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ -#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */ -#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */ -#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ -#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */ - -/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_CTRLBSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ -#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ - -#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ -#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos) -#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ -#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos) -#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ -#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos) -#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ -#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))) -#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ -#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ -#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ -#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ -#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ -#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))) -#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */ -#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ -#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */ -#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */ -#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ -#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */ - -/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ - uint32_t STATUS:1; /*!< bit: 3 Status Busy */ - uint32_t COUNT:1; /*!< bit: 4 Count Busy */ - uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ - uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ - uint32_t PER:1; /*!< bit: 7 Period busy */ - uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ - uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ - uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ - uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ - uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ - uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ - uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ - uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ - uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ - uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ - uint32_t :7; /*!< bit: 12..18 Reserved */ - uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ -#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ - -#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ -#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos) -#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ -#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos) -#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ -#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos) -#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ -#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos) -#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ -#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos) -#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ -#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos) -#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ -#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos) -#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */ -#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos) -#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ -#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) -#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ -#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) -#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ -#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) -#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ -#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) -#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ -#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos) -#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))) -#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */ -#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos) -#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */ -#define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos) -#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */ -#define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos) -#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */ -#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos) -#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */ -#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos) -#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */ -#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos) -#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */ -#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos) -#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */ -#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos) -#define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))) -#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */ - -/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_FCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ -#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ - -#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ -#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))) -#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */ -#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ -#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ -#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ -#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ -#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos) -#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ -#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos) -#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ -#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))) -#define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */ -#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ -#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ -#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ -#define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ -#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos) -#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ -#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))) -#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */ -#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */ -#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */ -#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */ -#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ -#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))) -#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ -#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ -#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ -#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ -#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ -#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))) -#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */ -#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */ -#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */ -#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */ -#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */ -#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */ -#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ -#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ -#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos) -#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))) -#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ -#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos) -#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))) -#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */ - -/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_FCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ -#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ - -#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ -#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))) -#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */ -#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ -#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ -#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ -#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ -#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos) -#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ -#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos) -#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ -#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))) -#define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */ -#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ -#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ -#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ -#define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ -#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos) -#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ -#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))) -#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */ -#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */ -#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */ -#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */ -#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ -#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))) -#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ -#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ -#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ -#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ -#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ -#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))) -#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */ -#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */ -#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */ -#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */ -#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */ -#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */ -#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ -#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ -#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos) -#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))) -#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ -#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos) -#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))) -#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */ - -/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ - uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ - uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ - uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ - uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WEXCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ -#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ - -#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ -#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos) -#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))) -#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ -#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) -#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ -#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) -#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ -#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) -#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ -#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) -#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ -#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos) -#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))) -#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ -#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos) -#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))) -#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ -#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos) -#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))) -#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */ - -/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ - uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ - uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ - uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ - uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ - uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ - uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ - uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ - uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ - uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ - uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ - uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ - uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ - uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ - uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ - uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ - uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ - uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ - uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ - uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ - uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ - uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ - uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ - uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ - uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ - uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ - uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ - uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_DRVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ -#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ - -#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ -#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) -#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ -#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) -#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ -#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) -#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ -#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) -#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ -#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) -#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ -#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) -#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ -#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) -#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ -#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) -#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ -#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos) -#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))) -#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ -#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) -#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ -#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) -#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ -#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) -#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ -#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) -#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ -#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) -#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ -#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) -#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ -#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) -#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ -#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) -#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ -#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos) -#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))) -#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ -#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) -#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ -#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) -#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ -#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) -#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ -#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) -#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ -#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) -#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ -#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) -#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ -#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) -#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ -#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) -#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ -#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos) -#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))) -#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ -#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos) -#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))) -#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ -#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos) -#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))) -#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */ - -/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ -#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ - -#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ -#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos) -#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ -#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos) -#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */ - -/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ - uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ - uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ - uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ - uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ - uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ - uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ - uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ - uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ - uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ - uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ - uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ - uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ - uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ - uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ - uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :12; /*!< bit: 0..11 Reserved */ - uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ - uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ - uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ -#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */ - -#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ -#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))) -#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ -#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ -#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */ -#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */ -#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */ -#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ -#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ -#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ -#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))) -#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ -#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ -#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */ -#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */ -#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */ -#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ -#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ -#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ -#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ -#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))) -#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ -#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ -#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ -#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ -#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ -#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos) -#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ -#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos) -#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ -#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos) -#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ -#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) -#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ -#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) -#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ -#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos) -#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))) -#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ -#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) -#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ -#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) -#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ -#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos) -#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))) -#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ -#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) -#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ -#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) -#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ -#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) -#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ -#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) -#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ -#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos) -#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))) -#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ -#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) -#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ -#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) -#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ -#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) -#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ -#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) -#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ -#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos) -#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))) -#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */ - -/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ -#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ -#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos) -#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ -#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos) -#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ -#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos) -#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ -#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos) -#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ -#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos) -#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ -#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos) -#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ -#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos) -#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ -#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos) -#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ -#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos) -#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ -#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) -#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ -#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) -#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ -#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) -#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ -#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) -#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ -#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos) -#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))) -#define TCC_INTENCLR_MASK 0x000FF80Ful /**< \brief (TCC_INTENCLR) MASK Register */ - -/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ -#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ - -#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ -#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos) -#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ -#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos) -#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ -#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos) -#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ -#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos) -#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ -#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos) -#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ -#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos) -#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ -#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos) -#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ -#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos) -#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ -#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos) -#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ -#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) -#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ -#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) -#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ -#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) -#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ -#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) -#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ -#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos) -#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))) -#define TCC_INTENSET_MASK 0x000FF80Ful /**< \brief (TCC_INTENSET) MASK Register */ - -/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow */ - uint32_t TRG:1; /*!< bit: 1 Retrigger */ - uint32_t CNT:1; /*!< bit: 2 Counter */ - uint32_t ERR:1; /*!< bit: 3 Error */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ -#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos) -#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ -#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos) -#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ -#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos) -#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ -#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos) -#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ -#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos) -#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ -#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos) -#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ -#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos) -#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ -#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos) -#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ -#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos) -#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ -#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) -#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ -#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) -#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ -#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) -#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ -#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) -#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ -#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos) -#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))) -#define TCC_INTFLAG_MASK 0x000FF80Ful /**< \brief (TCC_INTFLAG) MASK Register */ - -/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t STOP:1; /*!< bit: 0 Stop */ - uint32_t IDX:1; /*!< bit: 1 Ramp */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ - uint32_t SLAVE:1; /*!< bit: 4 Slave */ - uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ - uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ - uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ - uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ - uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ - uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ - uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ - uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ - uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ - uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ - uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ - uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ - uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ - uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ -#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */ - -#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ -#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos) -#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ -#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos) -#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ -#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos) -#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ -#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos) -#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ -#define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos) -#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ -#define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos) -#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ -#define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos) -#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ -#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos) -#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ -#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos) -#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ -#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos) -#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ -#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos) -#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ -#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos) -#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ -#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos) -#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ -#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos) -#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ -#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos) -#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ -#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos) -#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ -#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos) -#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ -#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos) -#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ -#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos) -#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ -#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos) -#define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))) -#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ -#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) -#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ -#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) -#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ -#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) -#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ -#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) -#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ -#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos) -#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))) -#define TCC_STATUS_MASK 0x0F0FFFFBul /**< \brief (TCC_STATUS) MASK Register */ - -/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ -#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */ - -// DITH4 mode -#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ -#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos) -#define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))) -#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ -#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos) -#define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))) -#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ -#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos) -#define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))) -#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */ - -#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ -#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos) -#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))) -#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */ - -/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ - uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ - uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ - uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ - uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ - uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ - uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ - uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ - uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ - uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ - uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ - uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ - uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ - uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ - uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ - uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ - uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TCC_PATT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ -#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */ - -#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ -#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) -#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ -#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) -#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ -#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) -#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ -#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) -#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ -#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) -#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ -#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) -#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ -#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) -#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ -#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) -#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ -#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos) -#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))) -#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ -#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) -#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ -#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) -#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ -#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) -#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ -#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) -#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ -#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) -#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ -#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) -#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ -#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) -#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ -#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) -#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ -#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos) -#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))) -#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */ - -/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ - uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ - uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ - uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ - uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ - uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ - uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ - uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ - uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ - uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ - uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WAVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ -#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */ - -#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ -#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))) -#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */ -#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */ -#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */ -#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */ -#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ -#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ -#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ -#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ -#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))) -#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */ -#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ -#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos) -#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ -#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) -#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ -#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) -#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ -#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) -#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ -#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) -#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ -#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos) -#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))) -#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ -#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) -#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ -#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) -#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ -#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) -#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ -#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) -#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ -#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos) -#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))) -#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ -#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) -#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ -#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) -#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ -#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) -#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ -#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) -#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ -#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos) -#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))) -#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */ - -/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t PER:20; /*!< bit: 4..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t PER:19; /*!< bit: 5..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t PER:18; /*!< bit: 6..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PER:24; /*!< bit: 0..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ -#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */ - -// DITH4 mode -#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ -#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos) -#define TCC_PER_DITH4_DITHERCY(value) ((TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))) -#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ -#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos) -#define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))) -#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ -#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos) -#define TCC_PER_DITH5_DITHERCY(value) ((TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))) -#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ -#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos) -#define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))) -#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ -#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos) -#define TCC_PER_DITH6_DITHERCY(value) ((TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))) -#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ -#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos) -#define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))) -#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */ - -#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ -#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos) -#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))) -#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */ - -/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ -#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */ - -// DITH4 mode -#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ -#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos) -#define TCC_CC_DITH4_DITHERCY(value) ((TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))) -#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ -#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos) -#define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))) -#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ -#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos) -#define TCC_CC_DITH5_DITHERCY(value) ((TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))) -#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ -#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos) -#define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))) -#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ -#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos) -#define TCC_CC_DITH6_DITHERCY(value) ((TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))) -#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ -#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos) -#define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))) -#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */ - -#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ -#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos) -#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))) -#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */ - -/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ - uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ - uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ - uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ - uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ - uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ - uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ - uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ - uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ - uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ - uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ - uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ - uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ - uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ - uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ - uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ - uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TCC_PATTB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */ -#define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */ - -#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */ -#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos) -#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */ -#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos) -#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */ -#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos) -#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */ -#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos) -#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */ -#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos) -#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */ -#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos) -#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */ -#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos) -#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */ -#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos) -#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */ -#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos) -#define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))) -#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */ -#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos) -#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */ -#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos) -#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */ -#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos) -#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */ -#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos) -#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */ -#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos) -#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */ -#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos) -#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */ -#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos) -#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */ -#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos) -#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */ -#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos) -#define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))) -#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */ - -/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ - uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ - uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ - uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ - uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ - uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ - uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ - uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ - uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ - uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ - uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WAVEB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */ -#define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */ - -#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */ -#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))) -#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */ -#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */ -#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */ -#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */ -#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ -#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ -#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */ -#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */ -#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))) -#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */ -#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */ -#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */ -#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */ -#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos) -#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */ -#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos) -#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */ -#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos) -#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */ -#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos) -#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */ -#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos) -#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */ -#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos) -#define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))) -#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */ -#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos) -#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */ -#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos) -#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */ -#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos) -#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */ -#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos) -#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */ -#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos) -#define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))) -#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */ -#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos) -#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */ -#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos) -#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */ -#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos) -#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */ -#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos) -#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */ -#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos) -#define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))) -#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */ - -/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_PERB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */ -#define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */ - -// DITH4 mode -#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos) -#define TCC_PERB_DITH4_DITHERCYB(value) ((TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))) -#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */ -#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos) -#define TCC_PERB_DITH4_PERB(value) ((TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))) -#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos) -#define TCC_PERB_DITH5_DITHERCYB(value) ((TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))) -#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */ -#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos) -#define TCC_PERB_DITH5_PERB(value) ((TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))) -#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos) -#define TCC_PERB_DITH6_DITHERCYB(value) ((TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))) -#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */ -#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos) -#define TCC_PERB_DITH6_PERB(value) ((TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))) -#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */ - -#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */ -#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos) -#define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))) -#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */ - -/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CCB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */ -#define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */ - -// DITH4 mode -#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos) -#define TCC_CCB_DITH4_DITHERCYB(value) ((TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))) -#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos) -#define TCC_CCB_DITH4_CCB(value) ((TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))) -#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos) -#define TCC_CCB_DITH5_DITHERCYB(value) ((TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))) -#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos) -#define TCC_CCB_DITH5_CCB(value) ((TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))) -#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos) -#define TCC_CCB_DITH6_DITHERCYB(value) ((TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))) -#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos) -#define TCC_CCB_DITH6_CCB(value) ((TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))) -#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */ - -#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos) -#define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))) -#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */ - -/** \brief TCC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - RoReg8 Reserved1[0x2]; - __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ - __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ - __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ - __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ - RoReg8 Reserved2[0x2]; - __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ - RoReg8 Reserved3[0x1]; - __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ - __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ - __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ - __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ - __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ - __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ - __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ - RoReg8 Reserved4[0x2]; - __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ - __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ - __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ - RoReg8 Reserved5[0x10]; - __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ - RoReg8 Reserved6[0x2]; - __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ - __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ - __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ -} Tcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_TCC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h deleted file mode 100644 index 9c1f64a7bd9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h +++ /dev/null @@ -1,1838 +0,0 @@ -/** - * \file - * - * \brief Component description for TCC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_TCC_COMPONENT_ -#define _SAMD21_TCC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TCC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_TCC Timer Counter Control */ -/*@{*/ - -#define TCC_U2213 -#define REV_TCC 0x121 - -/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t :3; /*!< bit: 2.. 4 Reserved */ - uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ - uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ - uint32_t :9; /*!< bit: 15..23 Reserved */ - uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ - uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ - uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ - uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :24; /*!< bit: 0..23 Reserved */ - uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ -#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */ - -#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ -#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos) -#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ -#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos) -#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ -#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))) -#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */ -#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ -#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ -#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ -#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ -#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))) -#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */ -#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */ -#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */ -#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */ -#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */ -#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */ -#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */ -#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */ -#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ -#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos) -#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ -#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))) -#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ -#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ -#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ -#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ -#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos) -#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ -#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) -#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ -#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) -#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ -#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) -#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ -#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) -#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ -#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos) -#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))) -#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */ - -/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_CTRLBCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ -#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ - -#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ -#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos) -#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ -#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos) -#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ -#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos) -#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ -#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))) -#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ -#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ -#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ -#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ -#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ -#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))) -#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */ -#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ -#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */ -#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */ -#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ -#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */ - -/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_CTRLBSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ -#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ - -#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ -#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos) -#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ -#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos) -#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ -#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos) -#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ -#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))) -#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ -#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ -#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ -#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ -#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ -#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))) -#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */ -#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ -#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */ -#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */ -#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ -#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */ - -/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ - uint32_t STATUS:1; /*!< bit: 3 Status Busy */ - uint32_t COUNT:1; /*!< bit: 4 Count Busy */ - uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ - uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ - uint32_t PER:1; /*!< bit: 7 Period busy */ - uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ - uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ - uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ - uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ - uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ - uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ - uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ - uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ - uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ - uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ - uint32_t :7; /*!< bit: 12..18 Reserved */ - uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ -#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ - -#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ -#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos) -#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ -#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos) -#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ -#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos) -#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ -#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos) -#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ -#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos) -#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ -#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos) -#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ -#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos) -#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */ -#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos) -#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ -#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) -#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ -#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) -#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ -#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) -#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ -#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) -#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ -#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos) -#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))) -#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */ -#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos) -#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */ -#define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos) -#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */ -#define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos) -#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */ -#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos) -#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */ -#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos) -#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */ -#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos) -#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */ -#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos) -#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */ -#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos) -#define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))) -#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */ - -/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_FCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ -#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ - -#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ -#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))) -#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */ -#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ -#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ -#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ -#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ -#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos) -#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ -#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos) -#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ -#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))) -#define TCC_FCTRLA_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */ -#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ -#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ -#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ -#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ -#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos) -#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ -#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))) -#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */ -#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */ -#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */ -#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */ -#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ -#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))) -#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ -#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ -#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ -#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ -#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ -#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))) -#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */ -#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */ -#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */ -#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */ -#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */ -#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */ -#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ -#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */ -#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ -#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos) -#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))) -#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ -#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos) -#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))) -#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */ - -/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_FCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ -#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ - -#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ -#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))) -#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */ -#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ -#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ -#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ -#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ -#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos) -#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ -#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos) -#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ -#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))) -#define TCC_FCTRLB_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */ -#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ -#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ -#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ -#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ -#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos) -#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ -#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))) -#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */ -#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */ -#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */ -#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */ -#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ -#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))) -#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ -#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ -#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ -#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ -#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ -#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))) -#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */ -#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */ -#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */ -#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */ -#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */ -#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */ -#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ -#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */ -#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ -#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos) -#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))) -#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ -#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos) -#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))) -#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */ - -/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ - uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ - uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ - uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ - uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WEXCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ -#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ - -#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ -#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos) -#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))) -#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ -#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) -#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ -#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) -#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ -#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) -#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ -#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) -#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ -#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos) -#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))) -#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ -#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos) -#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))) -#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ -#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos) -#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))) -#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */ - -/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ - uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ - uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ - uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ - uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ - uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ - uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ - uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ - uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ - uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ - uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ - uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ - uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ - uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ - uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ - uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ - uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ - uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ - uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ - uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ - uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ - uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ - uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ - uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ - uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ - uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ - uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ - uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_DRVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ -#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ - -#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ -#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) -#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ -#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) -#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ -#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) -#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ -#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) -#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ -#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) -#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ -#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) -#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ -#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) -#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ -#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) -#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ -#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos) -#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))) -#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ -#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) -#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ -#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) -#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ -#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) -#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ -#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) -#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ -#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) -#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ -#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) -#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ -#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) -#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ -#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) -#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ -#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos) -#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))) -#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ -#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) -#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ -#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) -#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ -#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) -#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ -#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) -#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ -#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) -#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ -#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) -#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ -#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) -#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ -#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) -#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ -#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos) -#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))) -#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ -#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos) -#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))) -#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ -#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos) -#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))) -#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */ - -/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ -#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ - -#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ -#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos) -#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ -#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos) -#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */ - -/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ - uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ - uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ - uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ - uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ - uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ - uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ - uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ - uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ - uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ - uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ - uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ - uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ - uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ - uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ - uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :12; /*!< bit: 0..11 Reserved */ - uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ - uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ - uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ -#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */ - -#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ -#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))) -#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ -#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ -#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */ -#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */ -#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */ -#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ -#define TCC_EVCTRL_EVACT0_STAMP_Val 0x6ul /**< \brief (TCC_EVCTRL) Stamp capture */ -#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ -#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ -#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))) -#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ -#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ -#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */ -#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */ -#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */ -#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ -#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ -#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ -#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ -#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))) -#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ -#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ -#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ -#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ -#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ -#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos) -#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ -#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos) -#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ -#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos) -#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ -#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) -#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ -#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) -#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ -#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos) -#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))) -#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ -#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) -#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ -#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) -#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ -#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos) -#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))) -#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ -#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) -#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ -#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) -#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ -#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) -#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ -#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) -#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ -#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos) -#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))) -#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ -#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) -#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ -#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) -#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ -#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) -#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ -#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) -#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ -#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos) -#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))) -#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */ - -/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ -#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ -#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos) -#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ -#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos) -#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ -#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos) -#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ -#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos) -#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */ -#define TCC_INTENCLR_UFS (0x1ul << TCC_INTENCLR_UFS_Pos) -#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ -#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos) -#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ -#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos) -#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ -#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos) -#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ -#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos) -#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ -#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos) -#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ -#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) -#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ -#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) -#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ -#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) -#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ -#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) -#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ -#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos) -#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))) -#define TCC_INTENCLR_MASK 0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */ - -/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ -#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ - -#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ -#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos) -#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ -#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos) -#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ -#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos) -#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ -#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos) -#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */ -#define TCC_INTENSET_UFS (0x1ul << TCC_INTENSET_UFS_Pos) -#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ -#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos) -#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ -#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos) -#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ -#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos) -#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ -#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos) -#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ -#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos) -#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ -#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) -#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ -#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) -#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ -#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) -#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ -#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) -#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ -#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos) -#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))) -#define TCC_INTENSET_MASK 0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */ - -/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow */ - uint32_t TRG:1; /*!< bit: 1 Retrigger */ - uint32_t CNT:1; /*!< bit: 2 Counter */ - uint32_t ERR:1; /*!< bit: 3 Error */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ -#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos) -#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ -#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos) -#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ -#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos) -#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ -#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos) -#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */ -#define TCC_INTFLAG_UFS (0x1ul << TCC_INTFLAG_UFS_Pos) -#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ -#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos) -#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ -#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos) -#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ -#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos) -#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ -#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos) -#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ -#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos) -#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ -#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) -#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ -#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) -#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ -#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) -#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ -#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) -#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ -#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos) -#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))) -#define TCC_INTFLAG_MASK 0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */ - -/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t STOP:1; /*!< bit: 0 Stop */ - uint32_t IDX:1; /*!< bit: 1 Ramp */ - uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */ - uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ - uint32_t SLAVE:1; /*!< bit: 4 Slave */ - uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ - uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ - uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ - uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ - uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ - uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ - uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ - uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ - uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ - uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ - uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ - uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ - uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ - uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ -#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */ - -#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ -#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos) -#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ -#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos) -#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */ -#define TCC_STATUS_UFS (0x1ul << TCC_STATUS_UFS_Pos) -#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ -#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos) -#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ -#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos) -#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ -#define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos) -#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ -#define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos) -#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ -#define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos) -#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ -#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos) -#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ -#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos) -#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ -#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos) -#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ -#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos) -#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ -#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos) -#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ -#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos) -#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ -#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos) -#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ -#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos) -#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ -#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos) -#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ -#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos) -#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ -#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos) -#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ -#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos) -#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ -#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos) -#define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))) -#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ -#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) -#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ -#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) -#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ -#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) -#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ -#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) -#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ -#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos) -#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))) -#define TCC_STATUS_MASK 0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */ - -/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ -#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */ - -// DITH4 mode -#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ -#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos) -#define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))) -#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ -#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos) -#define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))) -#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ -#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos) -#define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))) -#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */ - -#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ -#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos) -#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))) -#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */ - -/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ - uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ - uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ - uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ - uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ - uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ - uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ - uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ - uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ - uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ - uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ - uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ - uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ - uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ - uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ - uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ - uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TCC_PATT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ -#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */ - -#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ -#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) -#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ -#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) -#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ -#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) -#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ -#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) -#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ -#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) -#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ -#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) -#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ -#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) -#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ -#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) -#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ -#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos) -#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))) -#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ -#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) -#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ -#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) -#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ -#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) -#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ -#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) -#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ -#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) -#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ -#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) -#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ -#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) -#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ -#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) -#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ -#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos) -#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))) -#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */ - -/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ - uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ - uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ - uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ - uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ - uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ - uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ - uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ - uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ - uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ - uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WAVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ -#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */ - -#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ -#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))) -#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */ -#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */ -#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */ -#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */ -#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ -#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ -#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ -#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ -#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))) -#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */ -#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVE) Critical RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ -#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos) -#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ -#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) -#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ -#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) -#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ -#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) -#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ -#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) -#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ -#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos) -#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))) -#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ -#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) -#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ -#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) -#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ -#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) -#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ -#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) -#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ -#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos) -#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))) -#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ -#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) -#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ -#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) -#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ -#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) -#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ -#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) -#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ -#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos) -#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))) -#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */ - -/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t PER:20; /*!< bit: 4..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t PER:19; /*!< bit: 5..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t PER:18; /*!< bit: 6..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PER:24; /*!< bit: 0..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ -#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */ - -// DITH4 mode -#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ -#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos) -#define TCC_PER_DITH4_DITHERCY(value) ((TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))) -#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ -#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos) -#define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))) -#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ -#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos) -#define TCC_PER_DITH5_DITHERCY(value) ((TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))) -#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ -#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos) -#define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))) -#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ -#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos) -#define TCC_PER_DITH6_DITHERCY(value) ((TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))) -#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ -#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos) -#define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))) -#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */ - -#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ -#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos) -#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))) -#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */ - -/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ -#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */ - -// DITH4 mode -#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ -#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos) -#define TCC_CC_DITH4_DITHERCY(value) ((TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))) -#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ -#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos) -#define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))) -#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ -#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos) -#define TCC_CC_DITH5_DITHERCY(value) ((TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))) -#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ -#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos) -#define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))) -#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ -#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos) -#define TCC_CC_DITH6_DITHERCY(value) ((TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))) -#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ -#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos) -#define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))) -#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */ - -#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ -#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos) -#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))) -#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */ - -/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ - uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ - uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ - uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ - uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ - uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ - uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ - uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ - uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ - uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ - uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ - uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ - uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ - uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ - uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ - uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ - uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TCC_PATTB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */ -#define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */ - -#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */ -#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos) -#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */ -#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos) -#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */ -#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos) -#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */ -#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos) -#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */ -#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos) -#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */ -#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos) -#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */ -#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos) -#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */ -#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos) -#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */ -#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos) -#define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))) -#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */ -#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos) -#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */ -#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos) -#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */ -#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos) -#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */ -#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos) -#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */ -#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos) -#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */ -#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos) -#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */ -#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos) -#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */ -#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos) -#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */ -#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos) -#define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))) -#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */ - -/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ - uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ - uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ - uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ - uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ - uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ - uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ - uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ - uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ - uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ - uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WAVEB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */ -#define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */ - -#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */ -#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))) -#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */ -#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */ -#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */ -#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */ -#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ -#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ -#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */ -#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */ -#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))) -#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */ -#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */ -#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */ -#define TCC_WAVEB_RAMPB_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVEB) Critical RAMP2 operation */ -#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB_RAMP2C (TCC_WAVEB_RAMPB_RAMP2C_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */ -#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos) -#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */ -#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos) -#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */ -#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos) -#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */ -#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos) -#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */ -#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos) -#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */ -#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos) -#define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))) -#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */ -#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos) -#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */ -#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos) -#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */ -#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos) -#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */ -#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos) -#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */ -#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos) -#define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))) -#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */ -#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos) -#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */ -#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos) -#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */ -#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos) -#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */ -#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos) -#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */ -#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos) -#define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))) -#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */ - -/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_PERB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */ -#define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */ - -// DITH4 mode -#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos) -#define TCC_PERB_DITH4_DITHERCYB(value) ((TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))) -#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */ -#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos) -#define TCC_PERB_DITH4_PERB(value) ((TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))) -#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos) -#define TCC_PERB_DITH5_DITHERCYB(value) ((TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))) -#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */ -#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos) -#define TCC_PERB_DITH5_PERB(value) ((TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))) -#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos) -#define TCC_PERB_DITH6_DITHERCYB(value) ((TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))) -#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */ -#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos) -#define TCC_PERB_DITH6_PERB(value) ((TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))) -#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */ - -#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */ -#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos) -#define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))) -#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */ - -/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CCB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */ -#define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */ - -// DITH4 mode -#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos) -#define TCC_CCB_DITH4_DITHERCYB(value) ((TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))) -#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos) -#define TCC_CCB_DITH4_CCB(value) ((TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))) -#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos) -#define TCC_CCB_DITH5_DITHERCYB(value) ((TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))) -#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos) -#define TCC_CCB_DITH5_CCB(value) ((TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))) -#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos) -#define TCC_CCB_DITH6_DITHERCYB(value) ((TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))) -#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos) -#define TCC_CCB_DITH6_CCB(value) ((TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))) -#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */ - -#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos) -#define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))) -#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */ - -/** \brief TCC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - RoReg8 Reserved1[0x2]; - __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ - __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ - __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ - __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ - RoReg8 Reserved2[0x2]; - __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ - RoReg8 Reserved3[0x1]; - __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ - __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ - __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ - __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ - __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ - __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ - __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ - RoReg8 Reserved4[0x2]; - __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ - __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ - __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ - RoReg8 Reserved5[0x10]; - __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ - RoReg8 Reserved6[0x2]; - __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ - __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ - __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ -} Tcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_TCC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h deleted file mode 100644 index 8a74359425f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h +++ /dev/null @@ -1,1807 +0,0 @@ -/** - * \file - * - * \brief Component description for USB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_USB_COMPONENT_ -#define _SAMD21_USB_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR USB */ -/* ========================================================================== */ -/** \addtogroup SAMD21_USB Universal Serial Bus */ -/*@{*/ - -#define USB_U2222 -#define REV_USB 0x103 - -/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t MODE:1; /*!< bit: 7 Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */ -#define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */ - -#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */ -#define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos) -#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */ -#define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos) -#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */ -#define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos) -#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */ -#define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */ -#define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */ -#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */ - -/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */ -#define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */ - -#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */ -#define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos) -#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */ -#define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos) -#define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */ - -/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ - uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */ -#define USB_QOSCTRL_RESETVALUE 0x05ul /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */ - -#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */ -#define USB_QOSCTRL_CQOS_Msk (0x3ul << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_CQOS(value) ((USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))) -#define USB_QOSCTRL_CQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ -#define USB_QOSCTRL_CQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ -#define USB_QOSCTRL_CQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */ -#define USB_QOSCTRL_CQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */ -#define USB_QOSCTRL_CQOS_DISABLE (USB_QOSCTRL_CQOS_DISABLE_Val << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_CQOS_LOW (USB_QOSCTRL_CQOS_LOW_Val << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_CQOS_MEDIUM (USB_QOSCTRL_CQOS_MEDIUM_Val << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */ -#define USB_QOSCTRL_DQOS_Msk (0x3ul << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_DQOS(value) ((USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))) -#define USB_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ -#define USB_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ -#define USB_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */ -#define USB_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */ -#define USB_QOSCTRL_DQOS_DISABLE (USB_QOSCTRL_DQOS_DISABLE_Val << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_DQOS_LOW (USB_QOSCTRL_DQOS_LOW_Val << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_DQOS_MEDIUM (USB_QOSCTRL_DQOS_MEDIUM_Val << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_DQOS_HIGH (USB_QOSCTRL_DQOS_HIGH_Val << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_MASK 0x0Ful /**< \brief (USB_QOSCTRL) MASK Register */ - -/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DETACH:1; /*!< bit: 0 Detach */ - uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ - uint16_t NREPLY:1; /*!< bit: 4 No Reply */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ - uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ - uint16_t GNAK:1; /*!< bit: 9 Global NAK */ - uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */ -#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */ - -#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */ -#define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos) -#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */ -#define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */ -#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))) -#define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */ -#define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */ -#define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */ -#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */ -#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */ -#define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos) -#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */ -#define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos) -#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */ -#define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos) -#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */ -#define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos) -#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */ -#define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos) -#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */ -#define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */ -#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))) -#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ -#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */ -#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */ -#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */ -#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */ - -/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ - uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ - uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ - uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */ -#define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */ - -#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */ -#define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos) -#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */ -#define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))) -#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */ -#define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */ -#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */ -#define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos) -#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */ -#define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos) -#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */ -#define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos) -#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */ -#define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos) -#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */ -#define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos) -#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */ -#define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos) -#define USB_HOST_CTRLB_MASK 0x0F6Eul /**< \brief (USB_HOST_CTRLB) MASK Register */ - -/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ - uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_DADD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */ -#define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */ - -#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */ -#define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos) -#define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))) -#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */ -#define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos) -#define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */ - -/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_HSOFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */ -#define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */ - -#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */ -#define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos) -#define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))) -#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */ -#define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos) -#define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */ - -/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */ -#define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */ - -#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */ -#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))) -#define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */ -#define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */ -#define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */ -#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */ -#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))) -#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */ -#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */ -#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */ -#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */ - -/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */ -#define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */ - -#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */ -#define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos) -#define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))) -#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */ -#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos) -#define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))) -#define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */ - -/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_FSMSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */ -#define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */ - -#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */ -#define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))) -#define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ -#define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ -#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */ -#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */ -#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ -#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ -#define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */ -#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */ - -/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :1; /*!< bit: 14 Reserved */ - uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_FNUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */ -#define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */ - -#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */ -#define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos) -#define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))) -#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */ -#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos) -#define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))) -#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */ -#define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos) -#define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */ - -/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_FNUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */ -#define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */ - -#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */ -#define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos) -#define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))) -#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */ -#define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos) -#define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))) -#define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */ - -/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_FLENHIGH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */ -#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */ - -#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */ -#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos) -#define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))) -#define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */ - -/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */ -#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */ - -#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */ -#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos) -#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */ -#define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos) -#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */ -#define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos) -#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */ -#define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos) -#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */ -#define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos) -#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */ -#define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos) -#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */ -#define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos) -#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */ -#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos) -#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */ -#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos) -#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */ -#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos) -#define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */ - -/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ - uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */ -#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */ - -#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */ -#define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos) -#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */ -#define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos) -#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */ -#define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos) -#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */ -#define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos) -#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */ -#define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos) -#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */ -#define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos) -#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */ -#define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos) -#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */ -#define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos) -#define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */ - -/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */ -#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */ - -#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */ -#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos) -#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */ -#define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos) -#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */ -#define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos) -#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */ -#define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos) -#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */ -#define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos) -#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */ -#define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos) -#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */ -#define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos) -#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */ -#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos) -#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */ -#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos) -#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */ -#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos) -#define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */ - -/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ - uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */ -#define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */ - -#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */ -#define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos) -#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */ -#define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos) -#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */ -#define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos) -#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */ -#define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos) -#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */ -#define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos) -#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */ -#define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos) -#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */ -#define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos) -#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */ -#define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos) -#define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */ - -/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ - uint16_t EORST:1; /*!< bit: 3 End of Reset */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */ -#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */ - -#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */ -#define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos) -#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */ -#define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos) -#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */ -#define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos) -#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */ -#define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos) -#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */ -#define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos) -#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */ -#define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos) -#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */ -#define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos) -#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */ -#define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos) -#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */ -#define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos) -#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */ -#define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos) -#define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */ - -/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ - uint16_t RST:1; /*!< bit: 3 Bus Reset */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - uint16_t DNRSM:1; /*!< bit: 5 Downstream */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */ -#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */ - -#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */ -#define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos) -#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */ -#define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos) -#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */ -#define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos) -#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */ -#define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos) -#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */ -#define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos) -#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */ -#define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos) -#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */ -#define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos) -#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */ -#define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos) -#define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */ - -/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTSMRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */ -#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */ - -#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))) -#define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */ - -/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_PINTSMRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */ -#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */ - -#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos) -#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos) -#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos) -#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos) -#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos) -#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos) -#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos) -#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos) -#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */ -#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos) -#define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))) -#define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */ - -/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DESCADD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */ -#define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */ - -#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */ -#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos) -#define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))) -#define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */ - -/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_PADCAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */ -#define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */ - -#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */ -#define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos) -#define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))) -#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */ -#define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos) -#define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))) -#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */ -#define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos) -#define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))) -#define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */ - -/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ - uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */ -#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */ - -#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */ -#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos) -#define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))) -#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */ -#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos) -#define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))) -#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */ -#define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos) -#define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */ - -/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ - uint8_t BK:1; /*!< bit: 2 Pipe Bank */ - uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */ -#define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */ - -#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */ -#define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos) -#define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))) -#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */ -#define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos) -#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */ -#define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos) -#define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))) -#define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */ - -/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_BINTERVAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */ -#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */ - -#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */ -#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos) -#define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))) -#define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUSCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */ -#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */ - -#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */ -#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */ -#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */ -#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))) -#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */ -#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */ -#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */ - -/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUSCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */ -#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */ - -#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */ -#define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos) -#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */ -#define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos) -#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */ -#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos) -#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */ -#define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos) -#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */ -#define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos) -#define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUSSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */ -#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */ - -#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */ -#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */ -#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */ -#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))) -#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */ -#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */ -#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */ - -/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUSSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */ -#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */ - -#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */ -#define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos) -#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */ -#define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos) -#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */ -#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos) -#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */ -#define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos) -#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */ -#define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos) -#define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */ -#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */ - -#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */ -#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */ -#define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */ -#define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))) -#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */ -#define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */ -#define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */ - -/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */ -#define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */ - -#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */ -#define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos) -#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */ -#define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos) -#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */ -#define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos) -#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */ -#define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos) -#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */ -#define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos) -#define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */ - -/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */ -#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */ - -#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */ -#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */ -#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */ -#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))) -#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */ -#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */ -#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */ -#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))) -#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */ -#define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos) -#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */ -#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos) -#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */ -#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos) -#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */ -#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos) -#define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))) -#define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */ - -/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */ -#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */ - -#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos) -#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos) -#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos) -#define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))) -#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos) -#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */ -#define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos) -#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */ -#define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos) -#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */ -#define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos) -#define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */ - -/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ -#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - -#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))) -#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))) -#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos) -#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos) -#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos) -#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos) -#define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))) -#define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */ - -/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */ -#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */ - -#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */ -#define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos) -#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */ -#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos) -#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */ -#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos) -#define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))) -#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */ -#define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos) -#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */ -#define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos) -#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */ -#define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos) -#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Interrupt Disable */ -#define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos) -#define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */ - -/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */ -#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - -#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))) -#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))) -#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos) -#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos) -#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos) -#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos) -#define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))) -#define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */ - -/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */ -#define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */ - -#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos) -#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos) -#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos) -#define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))) -#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */ -#define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos) -#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */ -#define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos) -#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */ -#define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos) -#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */ -#define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos) -#define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */ - -/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DEVICE_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - -#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */ -#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos) -#define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))) -#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */ - -/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_HOST_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - -#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */ -#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos) -#define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))) -#define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */ - -/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DEVICE_PCKSIZE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - -#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */ -#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) -#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))) -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */ -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))) -#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */ -#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos) -#define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))) -#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */ -#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) -#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */ - -/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_HOST_PCKSIZE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */ - -#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */ -#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) -#define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))) -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */ -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))) -#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */ -#define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos) -#define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))) -#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */ -#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) -#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */ - -/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_EXTREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */ - -#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */ -#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos) -#define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))) -#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */ -#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos) -#define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))) -#define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */ - -/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_EXTREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */ - -#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */ -#define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos) -#define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))) -#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */ -#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos) -#define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))) -#define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */ - -/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_STATUS_BK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - -#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */ -#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos) -#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */ -#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) -#define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */ - -/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_BK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */ - -#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */ -#define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos) -#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */ -#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos) -#define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */ - -/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ - uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_CTRL_PIPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */ -#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */ - -#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */ -#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos) -#define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))) -#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */ -#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos) -#define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))) -#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */ -#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos) -#define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))) -#define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */ - -/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ - uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ - uint16_t PIDER:1; /*!< bit: 2 PID Error */ - uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ - uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ - uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_PIPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */ - -#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */ -#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos) -#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */ -#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos) -#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */ -#define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos) -#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */ -#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos) -#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */ -#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos) -#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */ -#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos) -#define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))) -#define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */ - -/** \brief UsbDeviceDescBank SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ - __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - RoReg8 Reserved1[0x5]; -} UsbDeviceDescBank; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbHostDescBank SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ - __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ - __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ - RoReg8 Reserved1[0x1]; - __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ - __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ -} UsbHostDescBank; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbDeviceEndpoint hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ - RoReg8 Reserved1[0x3]; - __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ - __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ - __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ - __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ - __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - RoReg8 Reserved2[0x16]; -} UsbDeviceEndpoint; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbHostPipe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ - RoReg8 Reserved1[0x2]; - __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ - __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ - __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ - __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ - __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ - __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ - __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ - RoReg8 Reserved2[0x16]; -} UsbHostPipe; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_DEVICE APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Device */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ - __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ - RoReg8 Reserved3[0x1]; - __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ - RoReg8 Reserved5[0x2]; - __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ -} UsbDevice; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_HOST hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Host */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ - __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ - RoReg8 Reserved3[0x1]; - __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ - __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ - RoReg8 Reserved5[0x1]; - __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ -} UsbHost; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_DEVICE Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Device */ - UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ -} UsbDeviceDescriptor; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_HOST Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Host */ - UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ -} UsbHostDescriptor; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_USB_DESCRIPTOR - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ - UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ -} Usb; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_USB_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h deleted file mode 100644 index 05d0aaec6bf..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h +++ /dev/null @@ -1,306 +0,0 @@ -/** - * \file - * - * \brief Component description for WDT - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_WDT_COMPONENT_ -#define _SAMD21_WDT_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR WDT */ -/* ========================================================================== */ -/** \addtogroup SAMD21_WDT Watchdog Timer */ -/*@{*/ - -#define WDT_U2203 -#define REV_WDT 0x200 - -/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */ -#define WDT_CTRL_RESETVALUE 0x00ul /**< \brief (WDT_CTRL reset_value) Control */ - -#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */ -#define WDT_CTRL_ENABLE (0x1ul << WDT_CTRL_ENABLE_Pos) -#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */ -#define WDT_CTRL_WEN (0x1ul << WDT_CTRL_WEN_Pos) -#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */ -#define WDT_CTRL_ALWAYSON (0x1ul << WDT_CTRL_ALWAYSON_Pos) -#define WDT_CTRL_MASK 0x86ul /**< \brief (WDT_CTRL) MASK Register */ - -/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ - uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */ -#define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */ - -#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */ -#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))) -#define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ -#define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ -#define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ -#define WDT_CONFIG_PER_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ -#define WDT_CONFIG_PER_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ -#define WDT_CONFIG_PER_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ -#define WDT_CONFIG_PER_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ -#define WDT_CONFIG_PER_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ -#define WDT_CONFIG_PER_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ -#define WDT_CONFIG_PER_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ -#define WDT_CONFIG_PER_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ -#define WDT_CONFIG_PER_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ -#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */ -#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))) -#define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ -#define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ -#define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ -#define WDT_CONFIG_WINDOW_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ -#define WDT_CONFIG_WINDOW_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ -#define WDT_CONFIG_WINDOW_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ -#define WDT_CONFIG_WINDOW_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ -#define WDT_CONFIG_WINDOW_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ -#define WDT_CONFIG_WINDOW_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ -#define WDT_CONFIG_WINDOW_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ -#define WDT_CONFIG_WINDOW_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ -#define WDT_CONFIG_WINDOW_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ -#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */ - -/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_EWCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */ -#define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */ - -#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */ -#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))) -#define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_1K_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_2K_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_4K_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_8K_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_16K_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */ - -/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */ -#define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */ - -#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */ -#define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos) -#define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */ - -/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */ -#define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */ - -#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */ -#define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos) -#define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */ - -/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */ -#define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */ -#define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos) -#define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */ - -/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */ -#define WDT_STATUS_RESETVALUE 0x00ul /**< \brief (WDT_STATUS reset_value) Status */ - -#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */ -#define WDT_STATUS_SYNCBUSY (0x1ul << WDT_STATUS_SYNCBUSY_Pos) -#define WDT_STATUS_MASK 0x80ul /**< \brief (WDT_STATUS) MASK Register */ - -/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CLEAR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */ -#define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */ - -#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */ -#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos) -#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))) -#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */ -#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) -#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */ - -/** \brief WDT hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ - __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ - RoReg8 Reserved1[0x1]; - __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ -} Wdt; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_WDT_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h deleted file mode 100644 index 95556474750..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - * \file - * - * \brief Instance description for AC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_AC_INSTANCE_ -#define _SAMD21_AC_INSTANCE_ - -/* ========== Register definition for AC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */ -#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */ -#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */ -#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */ -#else -#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */ -#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */ -#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */ -#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AC peripheral ========== */ -#define AC_CMP_NUM 2 // Number of comparators -#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog -#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC_NUM_CMP 2 -#define AC_PAIRS 1 // Number of pairs of comparators - -#endif /* _SAMD21_AC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h deleted file mode 100644 index 1cf4789d554..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief Instance description for AC1 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_AC1_INSTANCE_ -#define _SAMD21_AC1_INSTANCE_ - -/* ========== Register definition for AC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AC1_CTRLA (0x42005400U) /**< \brief (AC1) Control A */ -#define REG_AC1_CTRLB (0x42005401U) /**< \brief (AC1) Control B */ -#define REG_AC1_EVCTRL (0x42005402U) /**< \brief (AC1) Event Control */ -#define REG_AC1_INTENCLR (0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */ -#define REG_AC1_INTENSET (0x42005405U) /**< \brief (AC1) Interrupt Enable Set */ -#define REG_AC1_INTFLAG (0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */ -#define REG_AC1_STATUSA (0x42005408U) /**< \brief (AC1) Status A */ -#define REG_AC1_STATUSB (0x42005409U) /**< \brief (AC1) Status B */ -#define REG_AC1_STATUSC (0x4200540AU) /**< \brief (AC1) Status C */ -#define REG_AC1_WINCTRL (0x4200540CU) /**< \brief (AC1) Window Control */ -#define REG_AC1_COMPCTRL0 (0x42005410U) /**< \brief (AC1) Comparator Control 0 */ -#define REG_AC1_COMPCTRL1 (0x42005414U) /**< \brief (AC1) Comparator Control 1 */ -#define REG_AC1_SCALER0 (0x42005420U) /**< \brief (AC1) Scaler 0 */ -#define REG_AC1_SCALER1 (0x42005421U) /**< \brief (AC1) Scaler 1 */ -#else -#define REG_AC1_CTRLA (*(RwReg8 *)0x42005400U) /**< \brief (AC1) Control A */ -#define REG_AC1_CTRLB (*(WoReg8 *)0x42005401U) /**< \brief (AC1) Control B */ -#define REG_AC1_EVCTRL (*(RwReg16*)0x42005402U) /**< \brief (AC1) Event Control */ -#define REG_AC1_INTENCLR (*(RwReg8 *)0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */ -#define REG_AC1_INTENSET (*(RwReg8 *)0x42005405U) /**< \brief (AC1) Interrupt Enable Set */ -#define REG_AC1_INTFLAG (*(RwReg8 *)0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */ -#define REG_AC1_STATUSA (*(RoReg8 *)0x42005408U) /**< \brief (AC1) Status A */ -#define REG_AC1_STATUSB (*(RoReg8 *)0x42005409U) /**< \brief (AC1) Status B */ -#define REG_AC1_STATUSC (*(RoReg8 *)0x4200540AU) /**< \brief (AC1) Status C */ -#define REG_AC1_WINCTRL (*(RwReg8 *)0x4200540CU) /**< \brief (AC1) Window Control */ -#define REG_AC1_COMPCTRL0 (*(RwReg *)0x42005410U) /**< \brief (AC1) Comparator Control 0 */ -#define REG_AC1_COMPCTRL1 (*(RwReg *)0x42005414U) /**< \brief (AC1) Comparator Control 1 */ -#define REG_AC1_SCALER0 (*(RwReg8 *)0x42005420U) /**< \brief (AC1) Scaler 0 */ -#define REG_AC1_SCALER1 (*(RwReg8 *)0x42005421U) /**< \brief (AC1) Scaler 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AC1 peripheral ========== */ -#define AC1_CMP_NUM 2 // Number of comparators -#define AC1_GCLK_ID_ANA 32 // Index of Generic Clock for analog -#define AC1_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC1_NUM_CMP 2 -#define AC1_PAIRS 1 // Number of pairs of comparators - -#endif /* _SAMD21_AC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_adc.h deleted file mode 100644 index 1e498c17220..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_adc.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * \file - * - * \brief Instance description for ADC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_ADC_INSTANCE_ -#define _SAMD21_ADC_INSTANCE_ - -/* ========== Register definition for ADC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */ -#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */ -#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */ -#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */ -#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */ -#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */ -#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */ -#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */ -#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */ -#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */ -#else -#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */ -#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */ -#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */ -#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */ -#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */ -#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */ -#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */ -#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */ -#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */ -#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for ADC peripheral ========== */ -#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger -#define ADC_EXTCHANNEL_MSB 19 // Number of external channels -#define ADC_GCLK_ID 30 // Index of Generic Clock -#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield -#define ADC_RESULT_MSB 15 // Size of Result - -#endif /* _SAMD21_ADC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dac.h deleted file mode 100644 index 8c9e7927f7a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dac.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * \file - * - * \brief Instance description for DAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_DAC_INSTANCE_ -#define _SAMD21_DAC_INSTANCE_ - -/* ========== Register definition for DAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control A */ -#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control B */ -#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control */ -#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */ -#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */ -#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */ -#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status */ -#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data */ -#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer */ -#else -#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */ -#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */ -#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */ -#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */ -#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */ -#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */ -#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */ -#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */ -#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DAC peripheral ========== */ -#define DAC_DMAC_ID_EMPTY 40 // Index of DMAC EMPTY trigger -#define DAC_GCLK_ID 33 // Index of Generic Clock - -#endif /* _SAMD21_DAC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dmac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dmac.h deleted file mode 100644 index 98022d6cfdc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dmac.h +++ /dev/null @@ -1,112 +0,0 @@ -/** - * \file - * - * \brief Instance description for DMAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_DMAC_INSTANCE_ -#define _SAMD21_DMAC_INSTANCE_ - -/* ========== Register definition for DMAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_QOSCTRL (0x4100480EU) /**< \brief (DMAC) QOS Control */ -#define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */ -#else -#define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */ -#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DMAC peripheral ========== */ -#define DMAC_CH_BITS 4 // Number of bits to select channel -#define DMAC_CH_NUM 12 // Number of channels -#define DMAC_CLK_AHB_ID 5 // AHB clock index -#define DMAC_EVIN_NUM 4 // Number of input events -#define DMAC_EVOUT_NUM 4 // Number of output events -#define DMAC_LVL_BITS 2 // Number of bit to select level priority -#define DMAC_LVL_NUM 4 // Enable priority level number -#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source -#define DMAC_TRIG_NUM 45 // Number of peripheral triggers - -#endif /* _SAMD21_DMAC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dsu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dsu.h deleted file mode 100644 index 5c84af8000f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dsu.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * \file - * - * \brief Instance description for DSU - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_DSU_INSTANCE_ -#define _SAMD21_DSU_INSTANCE_ - -/* ========== Register definition for DSU peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */ -#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ -#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ -#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ -#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ -#else -#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */ -#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ -#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ -#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ -#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DSU peripheral ========== */ -#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register - -#endif /* _SAMD21_DSU_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_eic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_eic.h deleted file mode 100644 index 9ce1af3bfca..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_eic.h +++ /dev/null @@ -1,81 +0,0 @@ -/** - * \file - * - * \brief Instance description for EIC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_EIC_INSTANCE_ -#define _SAMD21_EIC_INSTANCE_ - -/* ========== Register definition for EIC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control */ -#define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status */ -#define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */ -#define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ -#define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-Up Enable */ -#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Configuration 1 */ -#else -#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */ -#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */ -#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */ -#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ -#define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */ -#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Configuration 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EIC peripheral ========== */ -#define EIC_CONFIG_NUM 2 // Number of CONFIG registers -#define EIC_GCLK_ID 5 // Index of Generic Clock - -#endif /* _SAMD21_EIC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_evsys.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_evsys.h deleted file mode 100644 index f356bd38c9a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_evsys.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - * \file - * - * \brief Instance description for EVSYS - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_EVSYS_INSTANCE_ -#define _SAMD21_EVSYS_INSTANCE_ - -/* ========== Register definition for EVSYS peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EVSYS_CTRL (0x42000400U) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHANNEL (0x42000404U) /**< \brief (EVSYS) Channel */ -#define REG_EVSYS_USER (0x42000408U) /**< \brief (EVSYS) User Multiplexer */ -#define REG_EVSYS_CHSTATUS (0x4200040CU) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#else -#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404U) /**< \brief (EVSYS) Channel */ -#define REG_EVSYS_USER (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */ -#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CU) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EVSYS peripheral ========== */ -#define EVSYS_CHANNELS 12 // Number of Channels -#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel -#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1 -#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators -#define EVSYS_GCLK_ID_0 7 -#define EVSYS_GCLK_ID_1 8 -#define EVSYS_GCLK_ID_2 9 -#define EVSYS_GCLK_ID_3 10 -#define EVSYS_GCLK_ID_4 11 -#define EVSYS_GCLK_ID_5 12 -#define EVSYS_GCLK_ID_6 13 -#define EVSYS_GCLK_ID_7 14 -#define EVSYS_GCLK_ID_8 15 -#define EVSYS_GCLK_ID_9 16 -#define EVSYS_GCLK_ID_10 17 -#define EVSYS_GCLK_ID_11 18 -#define EVSYS_GCLK_ID_LSB 7 -#define EVSYS_GCLK_ID_MSB 18 -#define EVSYS_GCLK_ID_SIZE 12 -#define EVSYS_GENERATORS 76 // Total Number of Event Generators -#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator -#define EVSYS_USERS 31 // Total Number of Event Users -#define EVSYS_USERS_BITS 5 // Number of bits to select Event User - -// GENERATORS -#define EVSYS_ID_GEN_RTC_CMP_0 1 -#define EVSYS_ID_GEN_RTC_CMP_1 2 -#define EVSYS_ID_GEN_RTC_OVF 3 -#define EVSYS_ID_GEN_RTC_PER_0 4 -#define EVSYS_ID_GEN_RTC_PER_1 5 -#define EVSYS_ID_GEN_RTC_PER_2 6 -#define EVSYS_ID_GEN_RTC_PER_3 7 -#define EVSYS_ID_GEN_RTC_PER_4 8 -#define EVSYS_ID_GEN_RTC_PER_5 9 -#define EVSYS_ID_GEN_RTC_PER_6 10 -#define EVSYS_ID_GEN_RTC_PER_7 11 -#define EVSYS_ID_GEN_EIC_EXTINT_0 12 -#define EVSYS_ID_GEN_EIC_EXTINT_1 13 -#define EVSYS_ID_GEN_EIC_EXTINT_2 14 -#define EVSYS_ID_GEN_EIC_EXTINT_3 15 -#define EVSYS_ID_GEN_EIC_EXTINT_4 16 -#define EVSYS_ID_GEN_EIC_EXTINT_5 17 -#define EVSYS_ID_GEN_EIC_EXTINT_6 18 -#define EVSYS_ID_GEN_EIC_EXTINT_7 19 -#define EVSYS_ID_GEN_EIC_EXTINT_8 20 -#define EVSYS_ID_GEN_EIC_EXTINT_9 21 -#define EVSYS_ID_GEN_EIC_EXTINT_10 22 -#define EVSYS_ID_GEN_EIC_EXTINT_11 23 -#define EVSYS_ID_GEN_EIC_EXTINT_12 24 -#define EVSYS_ID_GEN_EIC_EXTINT_13 25 -#define EVSYS_ID_GEN_EIC_EXTINT_14 26 -#define EVSYS_ID_GEN_EIC_EXTINT_15 27 -#define EVSYS_ID_GEN_EIC_EXTINT_16 28 -#define EVSYS_ID_GEN_EIC_EXTINT_17 29 -#define EVSYS_ID_GEN_DMAC_CH_0 30 -#define EVSYS_ID_GEN_DMAC_CH_1 31 -#define EVSYS_ID_GEN_DMAC_CH_2 32 -#define EVSYS_ID_GEN_DMAC_CH_3 33 -#define EVSYS_ID_GEN_TCC0_OVF 34 -#define EVSYS_ID_GEN_TCC0_TRG 35 -#define EVSYS_ID_GEN_TCC0_CNT 36 -#define EVSYS_ID_GEN_TCC0_MCX_0 37 -#define EVSYS_ID_GEN_TCC0_MCX_1 38 -#define EVSYS_ID_GEN_TCC0_MCX_2 39 -#define EVSYS_ID_GEN_TCC0_MCX_3 40 -#define EVSYS_ID_GEN_TCC1_OVF 41 -#define EVSYS_ID_GEN_TCC1_TRG 42 -#define EVSYS_ID_GEN_TCC1_CNT 43 -#define EVSYS_ID_GEN_TCC1_MCX_0 44 -#define EVSYS_ID_GEN_TCC1_MCX_1 45 -#define EVSYS_ID_GEN_TCC2_OVF 46 -#define EVSYS_ID_GEN_TCC2_TRG 47 -#define EVSYS_ID_GEN_TCC2_CNT 48 -#define EVSYS_ID_GEN_TCC2_MCX_0 49 -#define EVSYS_ID_GEN_TCC2_MCX_1 50 -#define EVSYS_ID_GEN_TC3_OVF 51 -#define EVSYS_ID_GEN_TC3_MCX_0 52 -#define EVSYS_ID_GEN_TC3_MCX_1 53 -#define EVSYS_ID_GEN_TC4_OVF 54 -#define EVSYS_ID_GEN_TC4_MCX_0 55 -#define EVSYS_ID_GEN_TC4_MCX_1 56 -#define EVSYS_ID_GEN_TC5_OVF 57 -#define EVSYS_ID_GEN_TC5_MCX_0 58 -#define EVSYS_ID_GEN_TC5_MCX_1 59 -#define EVSYS_ID_GEN_TC6_OVF 60 -#define EVSYS_ID_GEN_TC6_MCX_0 61 -#define EVSYS_ID_GEN_TC6_MCX_1 62 -#define EVSYS_ID_GEN_TC7_OVF 63 -#define EVSYS_ID_GEN_TC7_MCX_0 64 -#define EVSYS_ID_GEN_TC7_MCX_1 65 -#define EVSYS_ID_GEN_ADC_RESRDY 66 -#define EVSYS_ID_GEN_ADC_WINMON 67 -#define EVSYS_ID_GEN_AC_COMP_0 68 -#define EVSYS_ID_GEN_AC_COMP_1 69 -#define EVSYS_ID_GEN_AC_WIN_0 70 -#define EVSYS_ID_GEN_DAC_EMPTY 71 -#define EVSYS_ID_GEN_PTC_EOC 72 -#define EVSYS_ID_GEN_PTC_WCOMP 73 -#define EVSYS_ID_GEN_AC1_COMP_0 74 -#define EVSYS_ID_GEN_AC1_COMP_1 75 -#define EVSYS_ID_GEN_AC1_WIN_0 76 - -// USERS -#define EVSYS_ID_USER_DMAC_CH_0 0 -#define EVSYS_ID_USER_DMAC_CH_1 1 -#define EVSYS_ID_USER_DMAC_CH_2 2 -#define EVSYS_ID_USER_DMAC_CH_3 3 -#define EVSYS_ID_USER_TCC0_EV_0 4 -#define EVSYS_ID_USER_TCC0_EV_1 5 -#define EVSYS_ID_USER_TCC0_MC_0 6 -#define EVSYS_ID_USER_TCC0_MC_1 7 -#define EVSYS_ID_USER_TCC0_MC_2 8 -#define EVSYS_ID_USER_TCC0_MC_3 9 -#define EVSYS_ID_USER_TCC1_EV_0 10 -#define EVSYS_ID_USER_TCC1_EV_1 11 -#define EVSYS_ID_USER_TCC1_MC_0 12 -#define EVSYS_ID_USER_TCC1_MC_1 13 -#define EVSYS_ID_USER_TCC2_EV_0 14 -#define EVSYS_ID_USER_TCC2_EV_1 15 -#define EVSYS_ID_USER_TCC2_MC_0 16 -#define EVSYS_ID_USER_TCC2_MC_1 17 -#define EVSYS_ID_USER_TC3_EVU 18 -#define EVSYS_ID_USER_TC4_EVU 19 -#define EVSYS_ID_USER_TC5_EVU 20 -#define EVSYS_ID_USER_TC6_EVU 21 -#define EVSYS_ID_USER_TC7_EVU 22 -#define EVSYS_ID_USER_ADC_START 23 -#define EVSYS_ID_USER_ADC_SYNC 24 -#define EVSYS_ID_USER_AC_SOC_0 25 -#define EVSYS_ID_USER_AC_SOC_1 26 -#define EVSYS_ID_USER_DAC_START 27 -#define EVSYS_ID_USER_PTC_STCONV 28 -#define EVSYS_ID_USER_AC1_SOC_0 29 -#define EVSYS_ID_USER_AC1_SOC_1 30 - -#endif /* _SAMD21_EVSYS_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h deleted file mode 100644 index 6868a46fe08..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * \file - * - * \brief Instance description for GCLK - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_GCLK_INSTANCE_ -#define _SAMD21_GCLK_INSTANCE_ - -/* ========== Register definition for GCLK peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */ -#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */ -#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ -#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ -#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ -#else -#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */ -#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */ -#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ -#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ -#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 -#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators -#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 -#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 -#define GCLK_NUM 37 // Number of Generic Clock Users -#define GCLK_SOURCE_DFLL48M 7 // DFLL48M output -#define GCLK_SOURCE_FDPLL 8 // FDPLL output -#define GCLK_SOURCE_GCLKGEN1 2 // Generic clock generator 1 output -#define GCLK_SOURCE_GCLKIN 1 // Generator input pad -#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 // OSCULP32K oscillator output -#define GCLK_SOURCE_OSC8M 6 // OSC8M oscillator output -#define GCLK_SOURCE_OSC32K 4 // OSC32K oscillator outpur -#define GCLK_SOURCE_XOSC 0 // XOSC oscillator output -#define GCLK_SOURCE_XOSC32K 5 // XOSC32K oscillator output - -#endif /* _SAMD21_GCLK_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_i2s.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_i2s.h deleted file mode 100644 index f5b2a66a31e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_i2s.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * \brief Instance description for I2S - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_I2S_INSTANCE_ -#define _SAMD21_I2S_INSTANCE_ - -/* ========== Register definition for I2S peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_I2S_CTRLA (0x42005000U) /**< \brief (I2S) Control A */ -#define REG_I2S_CLKCTRL0 (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */ -#define REG_I2S_CLKCTRL1 (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */ -#define REG_I2S_INTENCLR (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */ -#define REG_I2S_INTENSET (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */ -#define REG_I2S_INTFLAG (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */ -#define REG_I2S_SYNCBUSY (0x42005018U) /**< \brief (I2S) Synchronization Status */ -#define REG_I2S_SERCTRL0 (0x42005020U) /**< \brief (I2S) Serializer 0 Control */ -#define REG_I2S_SERCTRL1 (0x42005024U) /**< \brief (I2S) Serializer 1 Control */ -#define REG_I2S_DATA0 (0x42005030U) /**< \brief (I2S) Data 0 */ -#define REG_I2S_DATA1 (0x42005034U) /**< \brief (I2S) Data 1 */ -#else -#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */ -#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */ -#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */ -#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */ -#define REG_I2S_INTENSET (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */ -#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */ -#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */ -#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */ -#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */ -#define REG_I2S_DATA0 (*(RwReg *)0x42005030U) /**< \brief (I2S) Data 0 */ -#define REG_I2S_DATA1 (*(RwReg *)0x42005034U) /**< \brief (I2S) Data 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for I2S peripheral ========== */ -#define I2S_CLK_NUM 2 // Number of clock units -#define I2S_DMAC_ID_RX_0 41 -#define I2S_DMAC_ID_RX_1 42 -#define I2S_DMAC_ID_RX_LSB 41 -#define I2S_DMAC_ID_RX_MSB 42 -#define I2S_DMAC_ID_RX_SIZE 2 -#define I2S_DMAC_ID_TX_0 43 -#define I2S_DMAC_ID_TX_1 44 -#define I2S_DMAC_ID_TX_LSB 43 -#define I2S_DMAC_ID_TX_MSB 44 -#define I2S_DMAC_ID_TX_SIZE 2 -#define I2S_GCLK_ID_0 35 -#define I2S_GCLK_ID_1 36 -#define I2S_GCLK_ID_LSB 35 -#define I2S_GCLK_ID_MSB 36 -#define I2S_GCLK_ID_SIZE 2 -#define I2S_MAX_SLOTS 8 // Max number of data slots in frame -#define I2S_SER_NUM 2 // Number of serializers - -#endif /* _SAMD21_I2S_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_mtb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_mtb.h deleted file mode 100644 index 21508c79b50..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_mtb.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * \file - * - * \brief Instance description for MTB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_MTB_INSTANCE_ -#define _SAMD21_MTB_INSTANCE_ - -/* ========== Register definition for MTB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) CoreSight */ -#else -#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) CoreSight */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAMD21_MTB_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h deleted file mode 100644 index fc6350ac7f7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * \file - * - * \brief Instance description for NVMCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_NVMCTRL_INSTANCE_ -#define _SAMD21_NVMCTRL_INSTANCE_ - -/* ========== Register definition for NVMCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */ -#else -#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for NVMCTRL peripheral ========== */ -#define NVMCTRL_AUX0_ADDRESS 0x00804000 -#define NVMCTRL_AUX1_ADDRESS 0x00806000 -#define NVMCTRL_AUX2_ADDRESS 0x00808000 -#define NVMCTRL_AUX3_ADDRESS 0x0080A000 -#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register -#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 65536 -#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGES 1024 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 -#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 -#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 -#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF -#define NVMCTRL_RWWEE_PAGES 32 // Page size -#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area - -#endif /* _SAMD21_NVMCTRL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac0.h deleted file mode 100644 index 129306ec6dc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac0.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC0 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_PAC0_INSTANCE_ -#define _SAMD21_PAC0_INSTANCE_ - -/* ========== Register definition for PAC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear */ -#define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set */ -#else -#define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */ -#define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC0 peripheral ========== */ -#define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset - -#endif /* _SAMD21_PAC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac1.h deleted file mode 100644 index e4832066fe7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac1.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC1 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_PAC1_INSTANCE_ -#define _SAMD21_PAC1_INSTANCE_ - -/* ========== Register definition for PAC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear */ -#define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set */ -#else -#define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */ -#define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC1 peripheral ========== */ -#define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset - -#endif /* _SAMD21_PAC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac2.h deleted file mode 100644 index 9e3381be19a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac2.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC2 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_PAC2_INSTANCE_ -#define _SAMD21_PAC2_INSTANCE_ - -/* ========== Register definition for PAC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear */ -#define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set */ -#else -#define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */ -#define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC2 peripheral ========== */ -#define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset - -#endif /* _SAMD21_PAC2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h deleted file mode 100644 index 5bd92cb87c0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * \file - * - * \brief Instance description for PM - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_PM_INSTANCE_ -#define _SAMD21_PM_INSTANCE_ - -/* ========== Register definition for PM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */ -#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */ -#define REG_PM_EXTCTRL (0x40000402U) /**< \brief (PM) External Reset Controller */ -#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */ -#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */ -#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */ -#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */ -#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */ -#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */ -#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */ -#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */ -#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */ -#else -#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */ -#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */ -#define REG_PM_EXTCTRL (*(RwReg8 *)0x40000402U) /**< \brief (PM) External Reset Controller */ -#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */ -#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */ -#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */ -#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */ -#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */ -#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */ -#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */ -#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */ -#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PM peripheral ========== */ -#define PM_CTRL_MCSEL_DFLL48M 3 -#define PM_CTRL_MCSEL_GCLK 0 -#define PM_CTRL_MCSEL_OSC8M 1 -#define PM_CTRL_MCSEL_XOSC 2 -#define PM_PM_CLK_APB_NUM 2 - -#endif /* _SAMD21_PM_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_port.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_port.h deleted file mode 100644 index 2041e624ea4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_port.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * \file - * - * \brief Instance description for PORT - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_PORT_INSTANCE_ -#define _SAMD21_PORT_INSTANCE_ - -/* ========== Register definition for PORT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */ -#else -#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PORT peripheral ========== */ -#define PORT_BITS 64 // Number of PORT pins -#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for DIR of all pins -#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins -#define PORT_DRVSTR 1 // DRVSTR supported -#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins -#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins -#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000 } -#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for INEN of all pins -#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins -#define PORT_ODRAIN 0 // ODRAIN supported -#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins -#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins -#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for OUT of all pins -#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins -#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins -#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins -#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins -#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins -#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins -#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins -#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF7, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins -#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins -#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins -#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins -#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins -#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins -#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins -#define PORT_SLEWLIM 0 // SLEWLIM supported -#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins -#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins - -#endif /* _SAMD21_PORT_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_rtc.h deleted file mode 100644 index 8e858bd1d82..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_rtc.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * \file - * - * \brief Instance description for RTC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_RTC_INSTANCE_ -#define _SAMD21_RTC_INSTANCE_ - -/* ========== Register definition for RTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */ -#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */ -#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */ -#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */ -#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */ -#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#else -#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */ -#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */ -#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */ -#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */ -#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */ -#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RTC peripheral ========== */ -#define RTC_ALARM_NUM 1 // Number of Alarms -#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators -#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators -#define RTC_GCLK_ID 4 // Index of Generic Clock -#define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete) -#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete) -#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete) - -#endif /* _SAMD21_RTC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h deleted file mode 100644 index d3523080916..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h +++ /dev/null @@ -1,168 +0,0 @@ -/** - * \file - * - * \brief Instance description for SBMATRIX - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SBMATRIX_INSTANCE_ -#define _SAMD21_SBMATRIX_INSTANCE_ - -/* ========== Register definition for SBMATRIX peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SBMATRIX_PRAS0 (0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */ -#define REG_SBMATRIX_PRBS0 (0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */ -#define REG_SBMATRIX_PRAS1 (0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */ -#define REG_SBMATRIX_PRBS1 (0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */ -#define REG_SBMATRIX_PRAS2 (0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */ -#define REG_SBMATRIX_PRBS2 (0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */ -#define REG_SBMATRIX_PRAS3 (0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */ -#define REG_SBMATRIX_PRBS3 (0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */ -#define REG_SBMATRIX_PRAS4 (0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */ -#define REG_SBMATRIX_PRBS4 (0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */ -#define REG_SBMATRIX_PRAS5 (0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */ -#define REG_SBMATRIX_PRBS5 (0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */ -#define REG_SBMATRIX_PRAS6 (0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */ -#define REG_SBMATRIX_PRBS6 (0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */ -#define REG_SBMATRIX_PRAS7 (0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */ -#define REG_SBMATRIX_PRBS7 (0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */ -#define REG_SBMATRIX_PRAS8 (0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */ -#define REG_SBMATRIX_PRBS8 (0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */ -#define REG_SBMATRIX_PRAS9 (0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */ -#define REG_SBMATRIX_PRBS9 (0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */ -#define REG_SBMATRIX_PRAS10 (0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */ -#define REG_SBMATRIX_PRBS10 (0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */ -#define REG_SBMATRIX_PRAS11 (0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */ -#define REG_SBMATRIX_PRBS11 (0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */ -#define REG_SBMATRIX_PRAS12 (0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */ -#define REG_SBMATRIX_PRBS12 (0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */ -#define REG_SBMATRIX_PRAS13 (0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */ -#define REG_SBMATRIX_PRBS13 (0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */ -#define REG_SBMATRIX_PRAS14 (0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */ -#define REG_SBMATRIX_PRBS14 (0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */ -#define REG_SBMATRIX_PRAS15 (0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */ -#define REG_SBMATRIX_PRBS15 (0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */ -#define REG_SBMATRIX_SFR0 (0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */ -#define REG_SBMATRIX_SFR1 (0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */ -#define REG_SBMATRIX_SFR2 (0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */ -#define REG_SBMATRIX_SFR3 (0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */ -#define REG_SBMATRIX_SFR4 (0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */ -#define REG_SBMATRIX_SFR5 (0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */ -#define REG_SBMATRIX_SFR6 (0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */ -#define REG_SBMATRIX_SFR7 (0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */ -#define REG_SBMATRIX_SFR8 (0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */ -#define REG_SBMATRIX_SFR9 (0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */ -#define REG_SBMATRIX_SFR10 (0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */ -#define REG_SBMATRIX_SFR11 (0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */ -#define REG_SBMATRIX_SFR12 (0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */ -#define REG_SBMATRIX_SFR13 (0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */ -#define REG_SBMATRIX_SFR14 (0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */ -#define REG_SBMATRIX_SFR15 (0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */ -#else -#define REG_SBMATRIX_PRAS0 (*(RwReg *)0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */ -#define REG_SBMATRIX_PRBS0 (*(RwReg *)0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */ -#define REG_SBMATRIX_PRAS1 (*(RwReg *)0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */ -#define REG_SBMATRIX_PRBS1 (*(RwReg *)0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */ -#define REG_SBMATRIX_PRAS2 (*(RwReg *)0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */ -#define REG_SBMATRIX_PRBS2 (*(RwReg *)0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */ -#define REG_SBMATRIX_PRAS3 (*(RwReg *)0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */ -#define REG_SBMATRIX_PRBS3 (*(RwReg *)0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */ -#define REG_SBMATRIX_PRAS4 (*(RwReg *)0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */ -#define REG_SBMATRIX_PRBS4 (*(RwReg *)0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */ -#define REG_SBMATRIX_PRAS5 (*(RwReg *)0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */ -#define REG_SBMATRIX_PRBS5 (*(RwReg *)0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */ -#define REG_SBMATRIX_PRAS6 (*(RwReg *)0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */ -#define REG_SBMATRIX_PRBS6 (*(RwReg *)0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */ -#define REG_SBMATRIX_PRAS7 (*(RwReg *)0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */ -#define REG_SBMATRIX_PRBS7 (*(RwReg *)0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */ -#define REG_SBMATRIX_PRAS8 (*(RwReg *)0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */ -#define REG_SBMATRIX_PRBS8 (*(RwReg *)0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */ -#define REG_SBMATRIX_PRAS9 (*(RwReg *)0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */ -#define REG_SBMATRIX_PRBS9 (*(RwReg *)0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */ -#define REG_SBMATRIX_PRAS10 (*(RwReg *)0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */ -#define REG_SBMATRIX_PRBS10 (*(RwReg *)0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */ -#define REG_SBMATRIX_PRAS11 (*(RwReg *)0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */ -#define REG_SBMATRIX_PRBS11 (*(RwReg *)0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */ -#define REG_SBMATRIX_PRAS12 (*(RwReg *)0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */ -#define REG_SBMATRIX_PRBS12 (*(RwReg *)0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */ -#define REG_SBMATRIX_PRAS13 (*(RwReg *)0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */ -#define REG_SBMATRIX_PRBS13 (*(RwReg *)0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */ -#define REG_SBMATRIX_PRAS14 (*(RwReg *)0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */ -#define REG_SBMATRIX_PRBS14 (*(RwReg *)0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */ -#define REG_SBMATRIX_PRAS15 (*(RwReg *)0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */ -#define REG_SBMATRIX_PRBS15 (*(RwReg *)0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */ -#define REG_SBMATRIX_SFR0 (*(RwReg *)0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */ -#define REG_SBMATRIX_SFR1 (*(RwReg *)0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */ -#define REG_SBMATRIX_SFR2 (*(RwReg *)0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */ -#define REG_SBMATRIX_SFR3 (*(RwReg *)0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */ -#define REG_SBMATRIX_SFR4 (*(RwReg *)0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */ -#define REG_SBMATRIX_SFR5 (*(RwReg *)0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */ -#define REG_SBMATRIX_SFR6 (*(RwReg *)0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */ -#define REG_SBMATRIX_SFR7 (*(RwReg *)0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */ -#define REG_SBMATRIX_SFR8 (*(RwReg *)0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */ -#define REG_SBMATRIX_SFR9 (*(RwReg *)0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */ -#define REG_SBMATRIX_SFR10 (*(RwReg *)0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */ -#define REG_SBMATRIX_SFR11 (*(RwReg *)0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */ -#define REG_SBMATRIX_SFR12 (*(RwReg *)0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */ -#define REG_SBMATRIX_SFR13 (*(RwReg *)0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */ -#define REG_SBMATRIX_SFR14 (*(RwReg *)0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */ -#define REG_SBMATRIX_SFR15 (*(RwReg *)0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SBMATRIX peripheral ========== */ -#define SBMATRIX_DEFINED -/* ========== Instance parameters for SBMATRIX ========== */ -#define SBMATRIX_SLAVE_FLASH 0 -#define SBMATRIX_SLAVE_HPB0 1 -#define SBMATRIX_SLAVE_HPB1 2 -#define SBMATRIX_SLAVE_HPB2 3 -#define SBMATRIX_SLAVE_HMCRAMC0 4 -#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5 -#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6 -#define SBMATRIX_SLAVE_NUM 7 - -#define SBMATRIX_MASTER_CM0PLUS 0 -#define SBMATRIX_MASTER_DSU 1 -#define SBMATRIX_MASTER_DMAC 2 -#define SBMATRIX_MASTER_NUM 3 - -#endif /* _SAMD21_SBMATRIX_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h deleted file mode 100644 index cb294f27f8f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM0 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SERCOM0_INSTANCE_ -#define _SAMD21_SERCOM0_INSTANCE_ - -/* ========== Register definition for SERCOM0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */ -#define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */ -#define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */ -#define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */ -#define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ -#else -#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */ -#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */ -#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */ -#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */ -#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM0 peripheral ========== */ -#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger -#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger -#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core -#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM0_INT_MSB 6 - -#endif /* _SAMD21_SERCOM0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h deleted file mode 100644 index aeeafcd1390..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM1 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SERCOM1_INSTANCE_ -#define _SAMD21_SERCOM1_INSTANCE_ - -/* ========== Register definition for SERCOM1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */ -#define REG_SERCOM1_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */ -#define REG_SERCOM1_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */ -#define REG_SERCOM1_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (0x42000C28U) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */ -#define REG_SERCOM1_USART_DATA (0x42000C28U) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */ -#else -#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */ -#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */ -#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */ -#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */ -#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM1 peripheral ========== */ -#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger -#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger -#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core -#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM1_INT_MSB 6 - -#endif /* _SAMD21_SERCOM1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h deleted file mode 100644 index d662b5d83dd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM2 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SERCOM2_INSTANCE_ -#define _SAMD21_SERCOM2_INSTANCE_ - -/* ========== Register definition for SERCOM2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */ -#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */ -#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */ -#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */ -#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */ -#else -#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */ -#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */ -#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */ -#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */ -#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM2 peripheral ========== */ -#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger -#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger -#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core -#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM2_INT_MSB 6 - -#endif /* _SAMD21_SERCOM2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h deleted file mode 100644 index 1da53d6be0b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM3 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SERCOM3_INSTANCE_ -#define _SAMD21_SERCOM3_INSTANCE_ - -/* ========== Register definition for SERCOM3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */ -#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */ -#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */ -#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */ -#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */ -#else -#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */ -#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */ -#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */ -#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */ -#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM3 peripheral ========== */ -#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger -#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger -#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core -#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM3_INT_MSB 6 - -#endif /* _SAMD21_SERCOM3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h deleted file mode 100644 index b4d74044a0d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM4 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SERCOM4_INSTANCE_ -#define _SAMD21_SERCOM4_INSTANCE_ - -/* ========== Register definition for SERCOM4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */ -#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */ -#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */ -#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */ -#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */ -#else -#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */ -#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */ -#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */ -#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */ -#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM4 peripheral ========== */ -#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger -#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger -#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core -#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM4_INT_MSB 6 - -#endif /* _SAMD21_SERCOM4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h deleted file mode 100644 index a468d17e85b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM5 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SERCOM5_INSTANCE_ -#define _SAMD21_SERCOM5_INSTANCE_ - -/* ========== Register definition for SERCOM5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */ -#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */ -#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */ -#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_BAUD (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */ -#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */ -#else -#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */ -#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */ -#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */ -#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */ -#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM5 peripheral ========== */ -#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger -#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger -#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core -#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM5_INT_MSB 6 - -#endif /* _SAMD21_SERCOM5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h deleted file mode 100644 index 5b696479da6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief Instance description for SYSCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_SYSCTRL_INSTANCE_ -#define _SAMD21_SYSCTRL_INSTANCE_ - -/* ========== Register definition for SYSCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ -#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ -#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ -#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ -#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ -#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ -#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ -#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ -#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ -#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ -#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ -#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ -#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ -#define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ -#define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ -#define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ -#define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ -#else -#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ -#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ -#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ -#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ -#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ -#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ -#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ -#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ -#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ -#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ -#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ -#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ -#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ -#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ -#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ -#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ -#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SYSCTRL peripheral ========== */ -#define SYSCTRL_BGAP_CALIB_MSB 11 -#define SYSCTRL_BOD33_CALIB_MSB 5 -#define SYSCTRL_DFLL48M_COARSE_MSB 5 -#define SYSCTRL_DFLL48M_FINE_MSB 9 -#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 -#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL -#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 -#define SYSCTRL_POR33_ENTEST_MSB 1 -#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 -#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 -#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 -#define SYSCTRL_VREF_CONTROL_MSB 48 -#define SYSCTRL_VREF_STATUS_MSB 7 -#define SYSCTRL_VREG_LEVEL_MSB 2 -#define SYSCTRL_BOD12_VERSION 0x111 -#define SYSCTRL_BOD33_VERSION 0x111 -#define SYSCTRL_DFLL48M_VERSION 0x301 -#define SYSCTRL_FDPLL_VERSION 0x111 -#define SYSCTRL_OSCULP32K_VERSION 0x111 -#define SYSCTRL_OSC8M_VERSION 0x120 -#define SYSCTRL_OSC32K_VERSION 0x112 -#define SYSCTRL_VREF_VERSION 0x201 -#define SYSCTRL_VREG_VERSION 0x201 -#define SYSCTRL_XOSC_VERSION 0x114 -#define SYSCTRL_XOSC32K_VERSION 0x113 - -#endif /* _SAMD21_SYSCTRL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h deleted file mode 100644 index 07ad9025d50..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC3 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TC3_INSTANCE_ -#define _SAMD21_TC3_INSTANCE_ - -/* ========== Register definition for TC3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */ -#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */ -#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */ -#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */ -#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */ -#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ -#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ -#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ -#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ -#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ -#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ -#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ -#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ -#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ -#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ -#else -#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */ -#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */ -#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */ -#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */ -#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */ -#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ -#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ -#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ -#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ -#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ -#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ -#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ -#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ -#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ -#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC3 peripheral ========== */ -#define TC3_CC8_NUM 2 // Number of 8-bit Counters -#define TC3_CC16_NUM 2 // Number of 16-bit Counters -#define TC3_CC32_NUM 2 // Number of 32-bit Counters -#define TC3_DITHERING_EXT 0 // Dithering feature implemented -#define TC3_DMAC_ID_MC_0 25 -#define TC3_DMAC_ID_MC_1 26 -#define TC3_DMAC_ID_MC_LSB 25 -#define TC3_DMAC_ID_MC_MSB 26 -#define TC3_DMAC_ID_MC_SIZE 2 -#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger -#define TC3_GCLK_ID 27 // Index of Generic Clock -#define TC3_MASTER 0 -#define TC3_OW_NUM 2 // Number of Output Waveforms -#define TC3_PERIOD_EXT 0 // Period feature implemented -#define TC3_SHADOW_EXT 0 // Shadow feature implemented - -#endif /* _SAMD21_TC3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h deleted file mode 100644 index 8539bca755c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC4 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TC4_INSTANCE_ -#define _SAMD21_TC4_INSTANCE_ - -/* ========== Register definition for TC4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A */ -#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request */ -#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear */ -#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set */ -#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C */ -#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Control */ -#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control */ -#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */ -#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */ -#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */ -#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status */ -#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */ -#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ -#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ -#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */ -#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ -#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ -#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */ -#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */ -#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ -#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ -#else -#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */ -#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */ -#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */ -#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */ -#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */ -#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */ -#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */ -#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */ -#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */ -#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */ -#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */ -#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */ -#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ -#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ -#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */ -#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ -#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ -#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */ -#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */ -#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ -#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC4 peripheral ========== */ -#define TC4_CC8_NUM 2 // Number of 8-bit Counters -#define TC4_CC16_NUM 2 // Number of 16-bit Counters -#define TC4_CC32_NUM 2 // Number of 32-bit Counters -#define TC4_DITHERING_EXT 0 // Dithering feature implemented -#define TC4_DMAC_ID_MC_0 28 -#define TC4_DMAC_ID_MC_1 29 -#define TC4_DMAC_ID_MC_LSB 28 -#define TC4_DMAC_ID_MC_MSB 29 -#define TC4_DMAC_ID_MC_SIZE 2 -#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger -#define TC4_GCLK_ID 28 // Index of Generic Clock -#define TC4_MASTER 1 -#define TC4_OW_NUM 2 // Number of Output Waveforms -#define TC4_PERIOD_EXT 0 // Period feature implemented -#define TC4_SHADOW_EXT 0 // Shadow feature implemented - -#endif /* _SAMD21_TC4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h deleted file mode 100644 index 0dfecceeb5e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC5 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TC5_INSTANCE_ -#define _SAMD21_TC5_INSTANCE_ - -/* ========== Register definition for TC5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */ -#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */ -#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */ -#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */ -#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */ -#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */ -#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */ -#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */ -#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */ -#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */ -#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */ -#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */ -#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ -#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ -#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */ -#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ -#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ -#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */ -#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */ -#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ -#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ -#else -#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */ -#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */ -#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */ -#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */ -#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */ -#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */ -#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */ -#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */ -#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */ -#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */ -#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */ -#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */ -#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ -#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ -#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */ -#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ -#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ -#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */ -#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */ -#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ -#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC5 peripheral ========== */ -#define TC5_CC8_NUM 2 // Number of 8-bit Counters -#define TC5_CC16_NUM 2 // Number of 16-bit Counters -#define TC5_CC32_NUM 2 // Number of 32-bit Counters -#define TC5_DITHERING_EXT 0 // Dithering feature implemented -#define TC5_DMAC_ID_MC_0 31 -#define TC5_DMAC_ID_MC_1 32 -#define TC5_DMAC_ID_MC_LSB 31 -#define TC5_DMAC_ID_MC_MSB 32 -#define TC5_DMAC_ID_MC_SIZE 2 -#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger -#define TC5_GCLK_ID 28 // Index of Generic Clock -#define TC5_MASTER 0 -#define TC5_OW_NUM 2 // Number of Output Waveforms -#define TC5_PERIOD_EXT 0 // Period feature implemented -#define TC5_SHADOW_EXT 0 // Shadow feature implemented - -#endif /* _SAMD21_TC5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h deleted file mode 100644 index 11cd7d2c10e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC6 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TC6_INSTANCE_ -#define _SAMD21_TC6_INSTANCE_ - -/* ========== Register definition for TC6 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A */ -#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request */ -#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear */ -#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set */ -#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C */ -#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Control */ -#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control */ -#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */ -#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */ -#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */ -#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status */ -#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */ -#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ -#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ -#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */ -#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ -#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ -#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */ -#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */ -#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ -#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ -#else -#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */ -#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */ -#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */ -#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */ -#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */ -#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */ -#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */ -#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */ -#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */ -#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */ -#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */ -#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */ -#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ -#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ -#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */ -#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ -#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ -#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */ -#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */ -#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ -#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC6 peripheral ========== */ -#define TC6_CC8_NUM 2 // Number of 8-bit Counters -#define TC6_CC16_NUM 2 // Number of 16-bit Counters -#define TC6_CC32_NUM 2 // Number of 32-bit Counters -#define TC6_DITHERING_EXT 0 // Dithering feature implemented -#define TC6_DMAC_ID_MC_0 34 -#define TC6_DMAC_ID_MC_1 35 -#define TC6_DMAC_ID_MC_LSB 34 -#define TC6_DMAC_ID_MC_MSB 35 -#define TC6_DMAC_ID_MC_SIZE 2 -#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger -#define TC6_GCLK_ID 29 // Index of Generic Clock -#define TC6_MASTER 1 -#define TC6_OW_NUM 2 // Number of Output Waveforms -#define TC6_PERIOD_EXT 0 // Period feature implemented -#define TC6_SHADOW_EXT 0 // Shadow feature implemented - -#endif /* _SAMD21_TC6_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h deleted file mode 100644 index 190990f773f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC7 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TC7_INSTANCE_ -#define _SAMD21_TC7_INSTANCE_ - -/* ========== Register definition for TC7 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC7_CTRLA (0x42003C00U) /**< \brief (TC7) Control A */ -#define REG_TC7_READREQ (0x42003C02U) /**< \brief (TC7) Read Request */ -#define REG_TC7_CTRLBCLR (0x42003C04U) /**< \brief (TC7) Control B Clear */ -#define REG_TC7_CTRLBSET (0x42003C05U) /**< \brief (TC7) Control B Set */ -#define REG_TC7_CTRLC (0x42003C06U) /**< \brief (TC7) Control C */ -#define REG_TC7_DBGCTRL (0x42003C08U) /**< \brief (TC7) Debug Control */ -#define REG_TC7_EVCTRL (0x42003C0AU) /**< \brief (TC7) Event Control */ -#define REG_TC7_INTENCLR (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */ -#define REG_TC7_INTENSET (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */ -#define REG_TC7_INTFLAG (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */ -#define REG_TC7_STATUS (0x42003C0FU) /**< \brief (TC7) Status */ -#define REG_TC7_COUNT16_COUNT (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */ -#define REG_TC7_COUNT16_CC0 (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ -#define REG_TC7_COUNT16_CC1 (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ -#define REG_TC7_COUNT32_COUNT (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */ -#define REG_TC7_COUNT32_CC0 (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ -#define REG_TC7_COUNT32_CC1 (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ -#define REG_TC7_COUNT8_COUNT (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */ -#define REG_TC7_COUNT8_PER (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */ -#define REG_TC7_COUNT8_CC0 (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ -#define REG_TC7_COUNT8_CC1 (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ -#else -#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */ -#define REG_TC7_READREQ (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */ -#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */ -#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */ -#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */ -#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */ -#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */ -#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */ -#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */ -#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */ -#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */ -#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */ -#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ -#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ -#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */ -#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ -#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ -#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */ -#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */ -#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ -#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC7 peripheral ========== */ -#define TC7_CC8_NUM 2 // Number of 8-bit Counters -#define TC7_CC16_NUM 2 // Number of 16-bit Counters -#define TC7_CC32_NUM 2 // Number of 32-bit Counters -#define TC7_DITHERING_EXT 0 // Dithering feature implemented -#define TC7_DMAC_ID_MC_0 37 -#define TC7_DMAC_ID_MC_1 38 -#define TC7_DMAC_ID_MC_LSB 37 -#define TC7_DMAC_ID_MC_MSB 38 -#define TC7_DMAC_ID_MC_SIZE 2 -#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger -#define TC7_GCLK_ID 29 // Index of Generic Clock -#define TC7_MASTER 0 -#define TC7_OW_NUM 2 // Number of Output Waveforms -#define TC7_PERIOD_EXT 0 // Period feature implemented -#define TC7_SHADOW_EXT 0 // Shadow feature implemented - -#endif /* _SAMD21_TC7_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h deleted file mode 100644 index dcc737a45db..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC0 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TCC0_INSTANCE_ -#define _SAMD21_TCC0_INSTANCE_ - -/* ========== Register definition for TCC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ -#define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#else -#define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ -#define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC0 peripheral ========== */ -#define TCC0_CC_NUM 4 // Number of Compare/Capture units -#define TCC0_DITHERING 1 // Dithering feature implemented -#define TCC0_DMAC_ID_MC_0 14 -#define TCC0_DMAC_ID_MC_1 15 -#define TCC0_DMAC_ID_MC_2 16 -#define TCC0_DMAC_ID_MC_3 17 -#define TCC0_DMAC_ID_MC_LSB 14 -#define TCC0_DMAC_ID_MC_MSB 17 -#define TCC0_DMAC_ID_MC_SIZE 4 -#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger -#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented -#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1) -#define TCC0_GCLK_ID 26 // Index of Generic Clock -#define TCC0_MASTER 0 -#define TCC0_OTMX 1 // Output Matrix feature implemented -#define TCC0_OW_NUM 8 // Number of Output Waveforms -#define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 -#define TCC0_SWAP 1 // DTI outputs swap feature implemented -#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAMD21_TCC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h deleted file mode 100644 index bc4c1710e58..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC1 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TCC1_INSTANCE_ -#define _SAMD21_TCC1_INSTANCE_ - -/* ========== Register definition for TCC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */ -#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */ -#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */ -#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */ -#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ -#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ -#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */ -#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */ -#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */ -#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ -#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ -#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ -#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */ -#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */ -#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */ -#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */ -#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */ -#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ -#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ -#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */ -#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ -#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */ -#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ -#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ -#else -#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */ -#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */ -#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */ -#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */ -#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ -#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ -#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */ -#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */ -#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */ -#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ -#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ -#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ -#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */ -#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */ -#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */ -#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */ -#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */ -#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ -#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ -#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */ -#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ -#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */ -#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ -#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC1 peripheral ========== */ -#define TCC1_CC_NUM 2 // Number of Compare/Capture units -#define TCC1_DITHERING 1 // Dithering feature implemented -#define TCC1_DMAC_ID_MC_0 19 -#define TCC1_DMAC_ID_MC_1 20 -#define TCC1_DMAC_ID_MC_LSB 19 -#define TCC1_DMAC_ID_MC_MSB 20 -#define TCC1_DMAC_ID_MC_SIZE 2 -#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger -#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented -#define TCC1_EXT 24 // Coding of implemented extended features -#define TCC1_GCLK_ID 26 // Index of Generic Clock -#define TCC1_MASTER 1 -#define TCC1_OTMX 0 // Output Matrix feature implemented -#define TCC1_OW_NUM 4 // Number of Output Waveforms -#define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 -#define TCC1_SWAP 0 // DTI outputs swap feature implemented -#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAMD21_TCC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h deleted file mode 100644 index 7b96139ca71..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC2 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_TCC2_INSTANCE_ -#define _SAMD21_TCC2_INSTANCE_ - -/* ========== Register definition for TCC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */ -#define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */ -#define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */ -#define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */ -#define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ -#define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */ -#define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Control */ -#define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */ -#define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */ -#define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */ -#define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */ -#define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ -#define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */ -#define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */ -#define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */ -#define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */ -#define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */ -#define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */ -#define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */ -#define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */ -#define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ -#define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ -#else -#define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */ -#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */ -#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */ -#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */ -#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ -#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */ -#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Control */ -#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */ -#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */ -#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */ -#define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */ -#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ -#define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */ -#define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */ -#define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */ -#define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */ -#define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */ -#define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */ -#define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */ -#define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */ -#define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ -#define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC2 peripheral ========== */ -#define TCC2_CC_NUM 2 // Number of Compare/Capture units -#define TCC2_DITHERING 0 // Dithering feature implemented -#define TCC2_DMAC_ID_MC_0 22 -#define TCC2_DMAC_ID_MC_1 23 -#define TCC2_DMAC_ID_MC_LSB 22 -#define TCC2_DMAC_ID_MC_MSB 23 -#define TCC2_DMAC_ID_MC_SIZE 2 -#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger -#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented -#define TCC2_EXT 0 // Coding of implemented extended features -#define TCC2_GCLK_ID 27 // Index of Generic Clock -#define TCC2_MASTER 0 -#define TCC2_OTMX 0 // Output Matrix feature implemented -#define TCC2_OW_NUM 2 // Number of Output Waveforms -#define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 -#define TCC2_SWAP 0 // DTI outputs swap feature implemented -#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAMD21_TCC2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_usb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_usb.h deleted file mode 100644 index 2d6a664718e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_usb.h +++ /dev/null @@ -1,347 +0,0 @@ -/** - * \file - * - * \brief Instance description for USB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_USB_INSTANCE_ -#define _SAMD21_USB_INSTANCE_ - -/* ========== Register definition for USB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USB_CTRLA (0x41005000U) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (0x41005002U) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_QOSCTRL (0x41005003U) /**< \brief (USB) USB Quality Of Service */ -#define REG_USB_FSMSTATUS (0x4100500DU) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (0x41005024U) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (0x41005028U) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (0x41005008U) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (0x4100500AU) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (0x4100500CU) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#define REG_USB_HOST_CTRLB (0x41005008U) /**< \brief (USB) HOST Control B */ -#define REG_USB_HOST_HSOFC (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */ -#define REG_USB_HOST_STATUS (0x4100500CU) /**< \brief (USB) HOST Status */ -#define REG_USB_HOST_FNUM (0x41005010U) /**< \brief (USB) HOST Host Frame Number */ -#define REG_USB_HOST_FLENHIGH (0x41005012U) /**< \brief (USB) HOST Host Frame Length */ -#define REG_USB_HOST_INTENCLR (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ -#define REG_USB_HOST_INTENSET (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ -#define REG_USB_HOST_INTFLAG (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */ -#define REG_USB_HOST_PINTSMRY (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ -#define REG_USB_HOST_PIPE_PCFG0 (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ -#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ -#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ -#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ -#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ -#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ -#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ -#define REG_USB_HOST_PIPE_PCFG1 (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ -#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ -#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ -#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ -#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ -#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ -#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ -#define REG_USB_HOST_PIPE_PCFG2 (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ -#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ -#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ -#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ -#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ -#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ -#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ -#define REG_USB_HOST_PIPE_PCFG3 (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ -#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ -#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ -#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ -#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ -#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ -#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ -#define REG_USB_HOST_PIPE_PCFG4 (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ -#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ -#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ -#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ -#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ -#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ -#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ -#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ -#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ -#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ -#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ -#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ -#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ -#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ -#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ -#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ -#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ -#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ -#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ -#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ -#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ -#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ -#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ -#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ -#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ -#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ -#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ -#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ -#else -#define REG_USB_CTRLA (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003U) /**< \brief (USB) USB Quality Of Service */ -#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (*(RwReg *)0x41005024U) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */ -#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */ -#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */ -#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */ -#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */ -#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ -#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ -#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */ -#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ -#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ -#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ -#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ -#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ -#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ -#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ -#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ -#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ -#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ -#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ -#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ -#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ -#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ -#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ -#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ -#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ -#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ -#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ -#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ -#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ -#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ -#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ -#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ -#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ -#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ -#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ -#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ -#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ -#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ -#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ -#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ -#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ -#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ -#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ -#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ -#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ -#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ -#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ -#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ -#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ -#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ -#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ -#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ -#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ -#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ -#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ -#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ -#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ -#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ -#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ -#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ -#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ -#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ -#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ -#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ -#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for USB peripheral ========== */ -#define USB_EPT_NBR 8 // Number of USB end points (obsolete) -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 6 // Index of Generic Clock -#define USB_PIPE_NUM 8 // Number of USB pipes - -#endif /* _SAMD21_USB_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_wdt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_wdt.h deleted file mode 100644 index 96ab4e37532..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_wdt.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_WDT_INSTANCE_ -#define _SAMD21_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status */ -#define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for WDT peripheral ========== */ -#define WDT_GCLK_ID 3 // Index of Generic Clock - -#endif /* _SAMD21_WDT_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15a.h deleted file mode 100644 index 152aaa0d064..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15a.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E15A_PIO_ -#define _SAMD21E15A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E15A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15b.h deleted file mode 100644 index 1ab51260fc4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15b.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15B_PIO_ -#define _SAMD21E15B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E15B_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15bu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15bu.h deleted file mode 100644 index 7fdf91adbf4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15bu.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E15BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15BU_PIO_ -#define _SAMD21E15BU_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E15BU_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15l.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15l.h deleted file mode 100644 index 3938fd62b24..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15l.h +++ /dev/null @@ -1,620 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E15L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15L_PIO_ -#define _SAMD21E15L_PIO_ - -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for AC1 peripheral ========== */ -#define PIN_PB04B_AC1_AIN0 36L /**< \brief AC1 signal: AIN0 on PB04 mux B */ -#define MUX_PB04B_AC1_AIN0 1L -#define PINMUX_PB04B_AC1_AIN0 ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0) -#define PORT_PB04B_AC1_AIN0 (1ul << 4) -#define PIN_PB05B_AC1_AIN1 37L /**< \brief AC1 signal: AIN1 on PB05 mux B */ -#define MUX_PB05B_AC1_AIN1 1L -#define PINMUX_PB05B_AC1_AIN1 ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1) -#define PORT_PB05B_AC1_AIN1 (1ul << 5) -#define PIN_PB02B_AC1_AIN2 34L /**< \brief AC1 signal: AIN2 on PB02 mux B */ -#define MUX_PB02B_AC1_AIN2 1L -#define PINMUX_PB02B_AC1_AIN2 ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2) -#define PORT_PB02B_AC1_AIN2 (1ul << 2) -#define PIN_PB03B_AC1_AIN3 35L /**< \brief AC1 signal: AIN3 on PB03 mux B */ -#define MUX_PB03B_AC1_AIN3 1L -#define PINMUX_PB03B_AC1_AIN3 ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3) -#define PORT_PB03B_AC1_AIN3 (1ul << 3) -#define PIN_PA24H_AC1_CMP0 24L /**< \brief AC1 signal: CMP0 on PA24 mux H */ -#define MUX_PA24H_AC1_CMP0 7L -#define PINMUX_PA24H_AC1_CMP0 ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0) -#define PORT_PA24H_AC1_CMP0 (1ul << 24) -#define PIN_PA25H_AC1_CMP1 25L /**< \brief AC1 signal: CMP1 on PA25 mux H */ -#define MUX_PA25H_AC1_CMP1 7L -#define PINMUX_PA25H_AC1_CMP1 ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1) -#define PORT_PA25H_AC1_CMP1 (1ul << 25) - -#endif /* _SAMD21E15L_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16a.h deleted file mode 100644 index 8ebe8bbed7c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16a.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E16A_PIO_ -#define _SAMD21E16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E16A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16b.h deleted file mode 100644 index 0a12729b391..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16b.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16B_PIO_ -#define _SAMD21E16B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E16B_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16bu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16bu.h deleted file mode 100644 index ab890b5cc6e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16bu.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E16BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16BU_PIO_ -#define _SAMD21E16BU_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E16BU_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16l.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16l.h deleted file mode 100644 index 85ac1e76eba..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16l.h +++ /dev/null @@ -1,620 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E16L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16L_PIO_ -#define _SAMD21E16L_PIO_ - -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for AC1 peripheral ========== */ -#define PIN_PB04B_AC1_AIN0 36L /**< \brief AC1 signal: AIN0 on PB04 mux B */ -#define MUX_PB04B_AC1_AIN0 1L -#define PINMUX_PB04B_AC1_AIN0 ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0) -#define PORT_PB04B_AC1_AIN0 (1ul << 4) -#define PIN_PB05B_AC1_AIN1 37L /**< \brief AC1 signal: AIN1 on PB05 mux B */ -#define MUX_PB05B_AC1_AIN1 1L -#define PINMUX_PB05B_AC1_AIN1 ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1) -#define PORT_PB05B_AC1_AIN1 (1ul << 5) -#define PIN_PB02B_AC1_AIN2 34L /**< \brief AC1 signal: AIN2 on PB02 mux B */ -#define MUX_PB02B_AC1_AIN2 1L -#define PINMUX_PB02B_AC1_AIN2 ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2) -#define PORT_PB02B_AC1_AIN2 (1ul << 2) -#define PIN_PB03B_AC1_AIN3 35L /**< \brief AC1 signal: AIN3 on PB03 mux B */ -#define MUX_PB03B_AC1_AIN3 1L -#define PINMUX_PB03B_AC1_AIN3 ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3) -#define PORT_PB03B_AC1_AIN3 (1ul << 3) -#define PIN_PA24H_AC1_CMP0 24L /**< \brief AC1 signal: CMP0 on PA24 mux H */ -#define MUX_PA24H_AC1_CMP0 7L -#define PINMUX_PA24H_AC1_CMP0 ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0) -#define PORT_PA24H_AC1_CMP0 (1ul << 24) -#define PIN_PA25H_AC1_CMP1 25L /**< \brief AC1 signal: CMP1 on PA25 mux H */ -#define MUX_PA25H_AC1_CMP1 7L -#define PINMUX_PA25H_AC1_CMP1 ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1) -#define PORT_PA25H_AC1_CMP1 (1ul << 25) - -#endif /* _SAMD21E16L_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e17a.h deleted file mode 100644 index cced9bdc93d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e17a.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E17A_PIO_ -#define _SAMD21E17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E17A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e18a.h deleted file mode 100644 index fa4b94953a3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e18a.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E18A_PIO_ -#define _SAMD21E18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E18A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15a.h deleted file mode 100644 index 9c29c035bf2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15a.h +++ /dev/null @@ -1,918 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G15A_PIO_ -#define _SAMD21G15A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G15A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15b.h deleted file mode 100644 index be61191bb55..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15b.h +++ /dev/null @@ -1,915 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15B_PIO_ -#define _SAMD21G15B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G15B_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16a.h deleted file mode 100644 index c5781d9119a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16a.h +++ /dev/null @@ -1,918 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G16A_PIO_ -#define _SAMD21G16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G16A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16b.h deleted file mode 100644 index 0c86fcc9b3d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16b.h +++ /dev/null @@ -1,915 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16B_PIO_ -#define _SAMD21G16B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G16B_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17a.h deleted file mode 100644 index 6bf8421f8a4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17a.h +++ /dev/null @@ -1,918 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G17A_PIO_ -#define _SAMD21G17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G17A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h deleted file mode 100644 index 37dc08b552c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h +++ /dev/null @@ -1,866 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G17AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* -* Support and FAQ: visit Atmel Support -*/ - -#ifndef _SAMD21G17AU_PIO_ -#define _SAMD21G17AU_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G17AU_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18a.h deleted file mode 100644 index 06605fadf94..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18a.h +++ /dev/null @@ -1,918 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G18A_PIO_ -#define _SAMD21G18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G18A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h deleted file mode 100644 index e4c3f08e8e8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h +++ /dev/null @@ -1,866 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G18AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* -* Support and FAQ: visit Atmel Support -*/ - -#ifndef _SAMD21G18AU_PIO_ -#define _SAMD21G18AU_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G18AU_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15a.h deleted file mode 100644 index e113f94d7ce..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15a.h +++ /dev/null @@ -1,1192 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J15A_PIO_ -#define _SAMD21J15A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J15A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15b.h deleted file mode 100644 index d0056e08b4f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15b.h +++ /dev/null @@ -1,1189 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J15B_PIO_ -#define _SAMD21J15B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J15B_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16a.h deleted file mode 100644 index fe330c4dff4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16a.h +++ /dev/null @@ -1,1192 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J16A_PIO_ -#define _SAMD21J16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J16A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16b.h deleted file mode 100644 index 1628f5b2a7a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16b.h +++ /dev/null @@ -1,1189 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J16B_PIO_ -#define _SAMD21J16B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J16B_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j17a.h deleted file mode 100644 index 990f75fef47..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j17a.h +++ /dev/null @@ -1,1192 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J17A_PIO_ -#define _SAMD21J17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J17A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j18a.h deleted file mode 100644 index 4ca3810cb2b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j18a.h +++ /dev/null @@ -1,1192 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J18A_PIO_ -#define _SAMD21J18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J18A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21.h deleted file mode 100644 index 56cb09907dc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * \brief Top header file for SAMD21 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_ -#define _SAMD21_ - -/** - * \defgroup SAMD21_definitions SAMD21 Device Definitions - * \brief SAMD21 CMSIS Definitions. - */ - -#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__) -#include "samd21e15a.h" -#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__) -#include "samd21e16a.h" -#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__) -#include "samd21e17a.h" -#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__) -#include "samd21e18a.h" -#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__) -#include "samd21g15a.h" -#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__) -#include "samd21g16a.h" -#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__) -#include "samd21g17a.h" -#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__) -#include "samd21g17au.h" -#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__) -#include "samd21g18a.h" -#elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__) -#include "samd21g18au.h" -#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__) -#include "samd21j15a.h" -#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__) -#include "samd21j16a.h" -#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__) -#include "samd21j17a.h" -#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__) -#include "samd21j18a.h" -#elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__) -#include "samd21e15b.h" -#elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__) -#include "samd21e15bu.h" -#elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__) -#include "samd21e15l.h" -#elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__) -#include "samd21e16b.h" -#elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__) -#include "samd21e16bu.h" -#elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__) -#include "samd21e16l.h" -#elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__) -#include "samd21g15b.h" -#elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__) -#include "samd21g16b.h" -#elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__) -#include "samd21j15b.h" -#elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__) -#include "samd21j16b.h" -#else -#error Library does not support the specified device. -#endif - -#endif /* _SAMD21_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h deleted file mode 100644 index ce18ac2b5c9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E15A_ -#define _SAMD21E15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions - * This file defines all structures and symbols for SAMD21E15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001000DUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h deleted file mode 100644 index 383ebbc320c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15B_ -#define _SAMD21E15B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E15B_definitions SAMD21E15B definitions - * This file defines all structures and symbols for SAMD21E15B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e15b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10011427UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 1 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15B_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h deleted file mode 100644 index 4381001c3d7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E15BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15BU_ -#define _SAMD21E15BU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E15BU_definitions SAMD21E15BU definitions - * This file defines all structures and symbols for SAMD21E15BU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15BU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e15bu.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10011456UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15BU_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h deleted file mode 100644 index fc4893f00ee..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h +++ /dev/null @@ -1,531 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E15L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15L_ -#define _SAMD21E15L_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E15L_definitions SAMD21E15L definitions - * This file defines all structures and symbols for SAMD21E15L: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15L-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */ - AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnReserved7; - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnReserved26; - void* pfnReserved27; - void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void AC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc_lighting.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_ac1.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 (0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 ((Ac *)0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define AC_INST_NUM 2 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC, AC1 } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e15l.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001143FUL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 0 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15L_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h deleted file mode 100644 index e84da564030..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E16A_ -#define _SAMD21E16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions - * This file defines all structures and symbols for SAMD21E16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001000CUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h deleted file mode 100644 index 951d1f4889b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16B_ -#define _SAMD21E16B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16B_definitions SAMD21E16B definitions - * This file defines all structures and symbols for SAMD21E16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10011426UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 1 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16B_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h deleted file mode 100644 index 497b0d4fca9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16BU_ -#define _SAMD21E16BU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16BU_definitions SAMD21E16BU definitions - * This file defines all structures and symbols for SAMD21E16BU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16BU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e16bu.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10011455UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16BU_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h deleted file mode 100644 index 9ca3de0e884..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h +++ /dev/null @@ -1,531 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16L_ -#define _SAMD21E16L_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16L_definitions SAMD21E16L definitions - * This file defines all structures and symbols for SAMD21E16L: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16L-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */ - AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnReserved7; - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnReserved26; - void* pfnReserved27; - void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void AC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc_lighting.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_ac1.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 (0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 ((Ac *)0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define AC_INST_NUM 2 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC, AC1 } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e16l.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001143EUL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 0 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16L_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h deleted file mode 100644 index 9e433c26e6f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E17A_ -#define _SAMD21E17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions - * This file defines all structures and symbols for SAMD21E17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001000BUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E17A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h deleted file mode 100644 index 6d51d950977..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E18A_ -#define _SAMD21E18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions - * This file defines all structures and symbols for SAMD21E18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21e18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001000AUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E18A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h deleted file mode 100644 index 65129029c05..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G15A_ -#define _SAMD21G15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions - * This file defines all structures and symbols for SAMD21G15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21g15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010008UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G15A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h deleted file mode 100644 index 005b09076cf..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15B_ -#define _SAMD21G15B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G15B_definitions SAMD21G15B definitions - * This file defines all structures and symbols for SAMD21G15B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21g15b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10011424UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G15B_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h deleted file mode 100644 index 707fbd3e89c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G16A_ -#define _SAMD21G16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions - * This file defines all structures and symbols for SAMD21G16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21g16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010007UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G16A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h deleted file mode 100644 index 1703045c4e4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16B_ -#define _SAMD21G16B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G16B_definitions SAMD21G16B definitions - * This file defines all structures and symbols for SAMD21G16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21g16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10011423UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G16B_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h deleted file mode 100644 index ccf9f074f4a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G17A_ -#define _SAMD21G17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions - * This file defines all structures and symbols for SAMD21G17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21g17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010006UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h deleted file mode 100644 index 01502c92ee4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h +++ /dev/null @@ -1,577 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G17AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* -* Support and FAQ: visit Atmel Support -*/ - -#ifndef _SAMD21G17AU_ -#define _SAMD21G17AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions - * This file defines all structures and symbols for SAMD21G17AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tc6.h" -#include "ins_tc7.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21g17au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010010UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17AU_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h deleted file mode 100644 index 83e232a224f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G18A_ -#define _SAMD21G18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions - * This file defines all structures and symbols for SAMD21G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010005UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h deleted file mode 100644 index dda17586c6f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G18AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* -* Support and FAQ: visit Atmel Support -*/ - -#ifndef _SAMD21G18AU_ -#define _SAMD21G18AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions - * This file defines all structures and symbols for SAMD21G18AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tc6.h" -#include "ins_tc7.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21g18au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001000FUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18AU_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h deleted file mode 100644 index 932efa39149..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J15A_ -#define _SAMD21J15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions - * This file defines all structures and symbols for SAMD21J15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tc6.h" -#include "ins_tc7.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21j15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010003UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J15A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h deleted file mode 100644 index daaabc0794e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J15B_ -#define _SAMD21J15B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J15B_definitions SAMD21J15B definitions - * This file defines all structures and symbols for SAMD21J15B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tc6.h" -#include "ins_tc7.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21j15b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10011421UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J15B_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h deleted file mode 100644 index 78628939871..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J16A_ -#define _SAMD21J16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions - * This file defines all structures and symbols for SAMD21J16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tc6.h" -#include "ins_tc7.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21j16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010002UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J16A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h deleted file mode 100644 index 471dc95ce26..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J16B_ -#define _SAMD21J16B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J16B_definitions SAMD21J16B definitions - * This file defines all structures and symbols for SAMD21J16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tc6.h" -#include "ins_tc7.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21j16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10011420UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J16B_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h deleted file mode 100644 index c61c596149d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J17A_ -#define _SAMD21J17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions - * This file defines all structures and symbols for SAMD21J17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tc6.h" -#include "ins_tc7.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21j17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010001UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J17A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h deleted file mode 100644 index c00fccdfca8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J18A_ -#define _SAMD21J18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions - * This file defines all structures and symbols for SAMD21J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_i2s.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_i2s.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tc6.h" -#include "ins_tc7.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_port PORT Definitions */ -/*@{*/ - -#include "pio_samd21j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010000UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J18A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.c deleted file mode 100644 index bebeec689e2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.c +++ /dev/null @@ -1,34 +0,0 @@ -#include "samd21.h" -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (1000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.h deleted file mode 100644 index 16dca9aaad2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _SYSTEM_SAMD21_H_INCLUDED_ -#define _SYSTEM_SAMD21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMD21_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ac.h deleted file mode 100644 index 482a111298e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ac.h +++ /dev/null @@ -1,603 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_AC_COMPONENT_ -#define _SAML21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAML21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2245 -#define REV_AC 0x100 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK 0x03ul /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))) -#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ - uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ -#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ -#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))) -#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI0 (1 << AC_EVCTRL_INVEI0_Pos) -#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI1 (1 << AC_EVCTRL_INVEI1_Pos) -#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (0x3ul << AC_EVCTRL_INVEI_Pos) -#define AC_EVCTRL_INVEI(value) ((AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))) -#define AC_EVCTRL_MASK 0x3313ul /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))) -#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))) -#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))) -#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))) -#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))) -#define AC_STATUSB_MASK 0x03ul /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AC_DBGCTRL reset_value) Debug Control */ - -#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (0x1ul << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK 0x01ul /**< \brief (AC_DBGCTRL) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))) -#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ - uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t OUT:2; /*!< bit: 28..29 Output */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (0x1ul << AC_COMPCTRL_RUNSTDBY_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))) -#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (0x7ul << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))) -#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val 0x4ul /**< \brief (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))) -#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_MEDLOW_Val 0x1ul /**< \brief (AC_COMPCTRL) Medium low speed */ -#define AC_COMPCTRL_SPEED_MEDHIGH_Val 0x2ul /**< \brief (AC_COMPCTRL) Medium high speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val 0x3ul /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (0x1ul << AC_COMPCTRL_HYSTEN_Pos) -#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (0x3ul << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST(value) ((AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))) -#define AC_COMPCTRL_HYST_HYST50_Val 0x0ul /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST70_Val 0x1ul /**< \brief (AC_COMPCTRL) 70mV */ -#define AC_COMPCTRL_HYST_HYST90_Val 0x2ul /**< \brief (AC_COMPCTRL) 90mV */ -#define AC_COMPCTRL_HYST_HYST110_Val 0x3ul /**< \brief (AC_COMPCTRL) 110mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))) -#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))) -#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK 0x373BF75Eul /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ - uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ - uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :3; /*!< bit: 0.. 2 Reserved */ - uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} AC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ - -#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (0x1ul << AC_SYNCBUSY_SWRST_Pos) -#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (0x1ul << AC_SYNCBUSY_ENABLE_Pos) -#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (0x1ul << AC_SYNCBUSY_WINCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL0 (1 << AC_SYNCBUSY_COMPCTRL0_Pos) -#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL1 (1 << AC_SYNCBUSY_COMPCTRL1_Pos) -#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (0x3ul << AC_SYNCBUSY_COMPCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL(value) ((AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))) -#define AC_SYNCBUSY_MASK 0x0000001Ful /**< \brief (AC_SYNCBUSY) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ - __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ - RoReg8 Reserved1[0x1]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ - RoReg8 Reserved2[0x2]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved3[0x8]; - __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_AC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_adc.h deleted file mode 100644 index 3cba27bb15e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_adc.h +++ /dev/null @@ -1,763 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_ADC_COMPONENT_ -#define _SAML21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAML21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2247 -#define REV_ADC 0x100 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run during Standby */ -#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (0x1ul << ADC_CTRLA_ONDEMAND_Pos) -#define ADC_CTRLA_MASK 0xC3ul /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE 0x00ul /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))) -#define ADC_CTRLB_PRESCALER_DIV2_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ -#define ADC_CTRLB_PRESCALER_DIV4_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK 0x07ul /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))) -#define ADC_REFCTRL_REFSEL_INTREF_Val 0x0ul /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC2_Val 0x5ul /**< \brief (ADC_REFCTRL) VCCANA */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ - uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ - uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ - uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (0x1ul << ADC_EVCTRL_FLUSHEI_Pos) -#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (0x1ul << ADC_EVCTRL_FLUSHINV_Pos) -#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (0x1ul << ADC_EVCTRL_STARTINV_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK 0x3Ful /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK 0x07ul /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK 0x07ul /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK 0x07ul /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SEQSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ -#define ADC_SEQSTATUS_RESETVALUE 0x00ul /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ - -#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ -#define ADC_SEQSTATUS_SEQSTATE_Msk (0x1Ful << ADC_SEQSTATUS_SEQSTATE_Pos) -#define ADC_SEQSTATUS_SEQSTATE(value) ((ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos))) -#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ -#define ADC_SEQSTATUS_SEQBUSY (0x1ul << ADC_SEQSTATUS_SEQBUSY_Pos) -#define ADC_SEQSTATUS_MASK 0x9Ful /**< \brief (ADC_SEQSTATUS) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE 0x0000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val 0x14ul /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val 0x15ul /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val 0x16ul /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val 0x17ul /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val 0x1Dul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_OPAMP01_Val 0x1Eul /**< \brief (ADC_INPUTCTRL) OPAMP0 or OPAMP1 output */ -#define ADC_INPUTCTRL_MUXPOS_OPAMP2_Val 0x1Ful /**< \brief (ADC_INPUTCTRL) OPAMP2 output */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_OPAMP01 (ADC_INPUTCTRL_MUXPOS_OPAMP01_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_OPAMP2 (ADC_INPUTCTRL_MUXPOS_OPAMP2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MASK 0x1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ -#define ADC_CTRLC_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLC reset_value) Control C */ - -#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ -#define ADC_CTRLC_DIFFMODE (0x1ul << ADC_CTRLC_DIFFMODE_Pos) -#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ -#define ADC_CTRLC_LEFTADJ (0x1ul << ADC_CTRLC_LEFTADJ_Pos) -#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ -#define ADC_CTRLC_FREERUN (0x1ul << ADC_CTRLC_FREERUN_Pos) -#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ -#define ADC_CTRLC_CORREN (0x1ul << ADC_CTRLC_CORREN_Pos) -#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ -#define ADC_CTRLC_RESSEL_Msk (0x3ul << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL(value) ((ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos))) -#define ADC_CTRLC_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLC) 12-bit result */ -#define ADC_CTRLC_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLC) For averaging mode output */ -#define ADC_CTRLC_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLC) 10-bit result */ -#define ADC_CTRLC_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLC) 8-bit result */ -#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ -#define ADC_CTRLC_WINMODE_Msk (0x7ul << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE(value) ((ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos))) -#define ADC_CTRLC_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_CTRLC) No window mode (default) */ -#define ADC_CTRLC_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_CTRLC) RESULT > WINLT */ -#define ADC_CTRLC_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_CTRLC) RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_MASK 0x073Ful /**< \brief (ADC_CTRLC) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))) -#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))) -#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))) -#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (0x1ul << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK 0xBFul /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))) -#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))) -#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))) -#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))) -#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ - uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ -#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ - uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ - uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ - uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ - uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ - uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ - uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ - uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ - uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ - uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ - uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ - -#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (0x1ul << ADC_SYNCBUSY_SWRST_Pos) -#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (0x1ul << ADC_SYNCBUSY_ENABLE_Pos) -#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (0x1ul << ADC_SYNCBUSY_INPUTCTRL_Pos) -#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLC (0x1ul << ADC_SYNCBUSY_CTRLC_Pos) -#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (0x1ul << ADC_SYNCBUSY_AVGCTRL_Pos) -#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (0x1ul << ADC_SYNCBUSY_SAMPCTRL_Pos) -#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (0x1ul << ADC_SYNCBUSY_WINLT_Pos) -#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (0x1ul << ADC_SYNCBUSY_WINUT_Pos) -#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (0x1ul << ADC_SYNCBUSY_GAINCORR_Pos) -#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (0x1ul << ADC_SYNCBUSY_OFFSETCORR_Pos) -#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (0x1ul << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK 0x07FFul /**< \brief (ADC_SYNCBUSY) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ -#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))) -#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ -#define ADC_SEQCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ - -#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ -#define ADC_SEQCTRL_SEQEN_Msk (0xFFFFFFFFul << ADC_SEQCTRL_SEQEN_Pos) -#define ADC_SEQCTRL_SEQEN(value) ((ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos))) -#define ADC_SEQCTRL_MASK 0xFFFFFFFFul /**< \brief (ADC_SEQCTRL) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (0x7ul << ADC_CALIB_BIASCOMP_Pos) -#define ADC_CALIB_BIASCOMP(value) ((ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))) -#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (0x7ul << ADC_CALIB_BIASREFBUF_Pos) -#define ADC_CALIB_BIASREFBUF(value) ((ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))) -#define ADC_CALIB_MASK 0x0707ul /**< \brief (ADC_CALIB) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ - __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ - RoReg8 Reserved1[0x2]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ - RoReg8 Reserved2[0x3]; - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ - RoReg8 Reserved3[0x3]; - __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ - RoReg8 Reserved4[0x2]; - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ - RoReg8 Reserved5[0x2]; - __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_ADC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_aes.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_aes.h deleted file mode 100644 index d4d262d42a8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_aes.h +++ /dev/null @@ -1,350 +0,0 @@ -/** - * \file - * - * \brief Component description for AES - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_AES_COMPONENT_ -#define _SAML21_AES_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AES */ -/* ========================================================================== */ -/** \addtogroup SAML21_AES Advanced Encryption Standard */ -/*@{*/ - -#define AES_U2238 -#define REV_AES 0x200 - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ - uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ - uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ - uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ - uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ - uint32_t LOD:1; /*!< bit: 12 LOD Enable */ - uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ - uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AES_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE 0x00000000ul /**< \brief (AES_CTRLA reset_value) Control A */ - -#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (0x1ul << AES_CTRLA_SWRST_Pos) -#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (0x1ul << AES_CTRLA_ENABLE_Pos) -#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (0x7ul << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE(value) ((AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))) -#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ -#define AES_CTRLA_CFBS_Msk (0x7ul << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS(value) ((AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))) -#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ -#define AES_CTRLA_KEYSIZE_Msk (0x3ul << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE(value) ((AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))) -#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ -#define AES_CTRLA_CIPHER (0x1ul << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ -#define AES_CTRLA_STARTMODE (0x1ul << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ -#define AES_CTRLA_LOD (0x1ul << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ -#define AES_CTRLA_KEYGEN (0x1ul << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ -#define AES_CTRLA_XORKEY (0x1ul << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ -#define AES_CTRLA_CTYPE_Msk (0xFul << AES_CTRLA_CTYPE_Pos) -#define AES_CTRLA_CTYPE(value) ((AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))) -#define AES_CTRLA_MASK 0x000F7FFFul /**< \brief (AES_CTRLA) MASK Register */ - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START:1; /*!< bit: 0 Manual Start */ - uint8_t NEWMSG:1; /*!< bit: 1 New message */ - uint8_t EOM:1; /*!< bit: 2 End of message */ - uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE 0x00ul /**< \brief (AES_CTRLB reset_value) Control B */ - -#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ -#define AES_CTRLB_START (0x1ul << AES_CTRLB_START_Pos) -#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (0x1ul << AES_CTRLB_NEWMSG_Pos) -#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (0x1ul << AES_CTRLB_EOM_Pos) -#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (0x1ul << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK 0x0Ful /**< \brief (AES_CTRLB) MASK Register */ - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE 0x00ul /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ -#define AES_INTENCLR_ENCCMP (0x1ul << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_0_Val 0x0ul /**< \brief (AES_INTENCLR) 1 (no division) */ -#define AES_INTENCLR_ENCCMP_1_Val 0x1ul /**< \brief (AES_INTENCLR) 2 */ -#define AES_INTENCLR_ENCCMP_2_Val 0x2ul /**< \brief (AES_INTENCLR) 4 */ -#define AES_INTENCLR_ENCCMP_3_Val 0x3ul /**< \brief (AES_INTENCLR) 8 */ -#define AES_INTENCLR_ENCCMP_0 (AES_INTENCLR_ENCCMP_0_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_1 (AES_INTENCLR_ENCCMP_1_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_2 (AES_INTENCLR_ENCCMP_2_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_3 (AES_INTENCLR_ENCCMP_3_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ -#define AES_INTENCLR_GFMCMP (0x1ul << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK 0x03ul /**< \brief (AES_INTENCLR) MASK Register */ - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE 0x00ul /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ - -#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ -#define AES_INTENSET_ENCCMP (0x1ul << AES_INTENSET_ENCCMP_Pos) -#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ -#define AES_INTENSET_GFMCMP (0x1ul << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK 0x03ul /**< \brief (AES_INTENSET) MASK Register */ - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE 0x00ul /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ - -#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (0x1ul << AES_INTFLAG_ENCCMP_Pos) -#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (0x1ul << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK 0x03ul /**< \brief (AES_INTFLAG) MASK Register */ - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DATABUFPTR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE 0x00ul /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ - -#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (0x3ul << AES_DATABUFPTR_INDATAPTR_Pos) -#define AES_DATABUFPTR_INDATAPTR(value) ((AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))) -#define AES_DATABUFPTR_MASK 0x03ul /**< \brief (AES_DATABUFPTR) MASK Register */ - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AES_DBGCTRL reset_value) Debug control */ - -#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (0x1ul << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK 0x01ul /**< \brief (AES_DBGCTRL) MASK Register */ - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_KEYWORD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE 0x00000000ul /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK 0xFFFFFFFFul /**< \brief (AES_KEYWORD) MASK Register */ - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE 0x00000000ul /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK 0xFFFFFFFFul /**< \brief (AES_INDATA) MASK Register */ - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INTVECTV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE 0x00000000ul /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK 0xFFFFFFFFul /**< \brief (AES_INTVECTV) MASK Register */ - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_HASHKEY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE 0x00000000ul /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK 0xFFFFFFFFul /**< \brief (AES_HASHKEY) MASK Register */ - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_GHASH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE 0x00000000ul /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK 0xFFFFFFFFul /**< \brief (AES_GHASH) MASK Register */ - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_CIPLEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE 0x00000000ul /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK 0xFFFFFFFFul /**< \brief (AES_CIPLEN) MASK Register */ - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_RANDSEED_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE 0x00000000ul /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK 0xFFFFFFFFul /**< \brief (AES_RANDSEED) MASK Register */ - -/** \brief AES hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ - __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ - __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ - RoReg8 Reserved1[0x2]; - __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ - RoReg8 Reserved2[0xC]; - __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ - __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ - RoReg8 Reserved3[0x10]; - __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ - __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ - RoReg8 Reserved4[0x4]; - __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ - __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_AES_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ccl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ccl.h deleted file mode 100644 index 0529623ec23..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ccl.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - * \file - * - * \brief Component description for CCL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_CCL_COMPONENT_ -#define _SAML21_CCL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CCL */ -/* ========================================================================== */ -/** \addtogroup SAML21_CCL Configurable Custom Logic */ -/*@{*/ - -#define CCL_U2225 -#define REV_CCL 0x100 - -/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE 0x00ul /**< \brief (CCL_CTRL reset_value) Control */ - -#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (0x1ul << CCL_CTRL_SWRST_Pos) -#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (0x1ul << CCL_CTRL_ENABLE_Pos) -#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ -#define CCL_CTRL_RUNSTDBY (0x1ul << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK 0x43ul /**< \brief (CCL_CTRL) MASK Register */ - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE 0x00ul /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ - -#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (0xFul << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL(value) ((CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val 0x0ul /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val 0x1ul /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val 0x2ul /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val 0x3ul /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val 0x4ul /**< \brief (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK 0x0Ful /**< \brief (CCL_SEQCTRL) MASK Register */ - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ - uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ - uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ - uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ - uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ - uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ - uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CCL_LUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE 0x00000000ul /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ - -#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (0x1ul << CCL_LUTCTRL_ENABLE_Pos) -#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (0x3ul << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL(value) ((CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val 0x0ul /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val 0x1ul /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val 0x2ul /**< \brief (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (0x1ul << CCL_LUTCTRL_EDGESEL_Pos) -#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (0xFul << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0(value) ((CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))) -#define CCL_LUTCTRL_INSEL0_MASK_Val 0x0ul /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val 0x1ul /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val 0x2ul /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val 0x3ul /**< \brief (CCL_LUTCTRL) Event in put source */ -#define CCL_LUTCTRL_INSEL0_IO_Val 0x4ul /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val 0x5ul /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val 0x6ul /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val 0x7ul /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val 0x8ul /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val 0x9ul /**< \brief (CCL_LUTCTRL) SERCOM inout source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (0xFul << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1(value) ((CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))) -#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (0xFul << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2(value) ((CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))) -#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ -#define CCL_LUTCTRL_INVEI (0x1ul << CCL_LUTCTRL_INVEI_Pos) -#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (0x1ul << CCL_LUTCTRL_LUTEI_Pos) -#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (0x1ul << CCL_LUTCTRL_LUTEO_Pos) -#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (0xFFul << CCL_LUTCTRL_TRUTH_Pos) -#define CCL_LUTCTRL_TRUTH(value) ((CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))) -#define CCL_LUTCTRL_MASK 0xFF7FFFB2ul /**< \brief (CCL_LUTCTRL) MASK Register */ - -/** \brief CCL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ - RoReg8 Reserved2[0x2]; - __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ -} Ccl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_CCL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dac.h deleted file mode 100644 index eacec2df805..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dac.h +++ /dev/null @@ -1,474 +0,0 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_DAC_COMPONENT_ -#define _SAML21_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAML21_DAC Digital-to-Analog Converter */ -/*@{*/ - -#define DAC_U2244 -#define REV_DAC 0x100 - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ -#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_MASK 0x03ul /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ - uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ -#define DAC_CTRLB_DIFF (0x1ul << DAC_CTRLB_DIFF_Pos) -#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ -#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))) -#define DAC_CTRLB_REFSEL_VREFPU_Val 0x0ul /**< \brief (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val 0x1ul /**< \brief (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val 0x2ul /**< \brief (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val 0x3ul /**< \brief (DAC_CTRLB) Internal bandgap reference */ -#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK 0x07ul /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ - uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ - uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ - uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ - uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ - uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ - uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ - uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ -#define DAC_EVCTRL_STARTEI0 (1 << DAC_EVCTRL_STARTEI0_Pos) -#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ -#define DAC_EVCTRL_STARTEI1 (1 << DAC_EVCTRL_STARTEI1_Pos) -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (0x3ul << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_STARTEI(value) ((DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))) -#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ -#define DAC_EVCTRL_EMPTYEO0 (1 << DAC_EVCTRL_EMPTYEO0_Pos) -#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ -#define DAC_EVCTRL_EMPTYEO1 (1 << DAC_EVCTRL_EMPTYEO1_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (0x3ul << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_EMPTYEO(value) ((DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))) -#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ -#define DAC_EVCTRL_INVEI0 (1 << DAC_EVCTRL_INVEI0_Pos) -#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ -#define DAC_EVCTRL_INVEI1 (1 << DAC_EVCTRL_INVEI1_Pos) -#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (0x3ul << DAC_EVCTRL_INVEI_Pos) -#define DAC_EVCTRL_INVEI(value) ((DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))) -#define DAC_EVCTRL_MASK 0x3Ful /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 0 */ -#define DAC_INTENCLR_UNDERRUN0 (1 << DAC_INTENCLR_UNDERRUN0_Pos) -#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 1 */ -#define DAC_INTENCLR_UNDERRUN1 (1 << DAC_INTENCLR_UNDERRUN1_Pos) -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC x */ -#define DAC_INTENCLR_UNDERRUN_Msk (0x3ul << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_UNDERRUN(value) ((DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))) -#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY0 (1 << DAC_INTENCLR_EMPTY0_Pos) -#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY1 (1 << DAC_INTENCLR_EMPTY1_Pos) -#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (0x3ul << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_EMPTY(value) ((DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))) -#define DAC_INTENCLR_MASK 0x0Ful /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 0 */ -#define DAC_INTENSET_UNDERRUN0 (1 << DAC_INTENSET_UNDERRUN0_Pos) -#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 1 */ -#define DAC_INTENSET_UNDERRUN1 (1 << DAC_INTENSET_UNDERRUN1_Pos) -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC x */ -#define DAC_INTENSET_UNDERRUN_Msk (0x3ul << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_UNDERRUN(value) ((DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))) -#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY0 (1 << DAC_INTENSET_EMPTY0_Pos) -#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY1 (1 << DAC_INTENSET_EMPTY1_Pos) -#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (0x3ul << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_EMPTY(value) ((DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))) -#define DAC_INTENSET_MASK 0x0Ful /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 DAC 0 Underrun */ - uint8_t UNDERRUN1:1; /*!< bit: 1 DAC 1 Underrun */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 DAC x Underrun */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) DAC 0 Underrun */ -#define DAC_INTFLAG_UNDERRUN0 (1 << DAC_INTFLAG_UNDERRUN0_Pos) -#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) DAC 1 Underrun */ -#define DAC_INTFLAG_UNDERRUN1 (1 << DAC_INTFLAG_UNDERRUN1_Pos) -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) DAC x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (0x3ul << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_UNDERRUN(value) ((DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))) -#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ -#define DAC_INTFLAG_EMPTY0 (1 << DAC_INTFLAG_EMPTY0_Pos) -#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ -#define DAC_INTFLAG_EMPTY1 (1 << DAC_INTFLAG_EMPTY1_Pos) -#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (0x3ul << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_EMPTY(value) ((DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))) -#define DAC_INTFLAG_MASK 0x0Ful /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ - uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ - uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ - uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ - uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ -#define DAC_STATUS_READY0 (1 << DAC_STATUS_READY0_Pos) -#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ -#define DAC_STATUS_READY1 (1 << DAC_STATUS_READY1_Pos) -#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (0x3ul << DAC_STATUS_READY_Pos) -#define DAC_STATUS_READY(value) ((DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))) -#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ -#define DAC_STATUS_EOC0 (1 << DAC_STATUS_EOC0_Pos) -#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ -#define DAC_STATUS_EOC1 (1 << DAC_STATUS_EOC1_Pos) -#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (0x3ul << DAC_STATUS_EOC_Pos) -#define DAC_STATUS_EOC(value) ((DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))) -#define DAC_STATUS_MASK 0x0Ful /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ - uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ - uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ - uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ - uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ - uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DAC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ -#define DAC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ - -#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ -#define DAC_SYNCBUSY_SWRST (0x1ul << DAC_SYNCBUSY_SWRST_Pos) -#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ -#define DAC_SYNCBUSY_ENABLE (0x1ul << DAC_SYNCBUSY_ENABLE_Pos) -#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ -#define DAC_SYNCBUSY_DATA0 (1 << DAC_SYNCBUSY_DATA0_Pos) -#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ -#define DAC_SYNCBUSY_DATA1 (1 << DAC_SYNCBUSY_DATA1_Pos) -#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (0x3ul << DAC_SYNCBUSY_DATA_Pos) -#define DAC_SYNCBUSY_DATA(value) ((DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))) -#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ -#define DAC_SYNCBUSY_DATABUF0 (1 << DAC_SYNCBUSY_DATABUF0_Pos) -#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ -#define DAC_SYNCBUSY_DATABUF1 (1 << DAC_SYNCBUSY_DATABUF1_Pos) -#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (0x3ul << DAC_SYNCBUSY_DATABUF_Pos) -#define DAC_SYNCBUSY_DATABUF(value) ((DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))) -#define DAC_SYNCBUSY_MASK 0x0000003Ful /**< \brief (DAC_SYNCBUSY) MASK Register */ - -/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ - uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ - uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ - uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DACCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ -#define DAC_DACCTRL_RESETVALUE 0x0000ul /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ - -#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ -#define DAC_DACCTRL_LEFTADJ (0x1ul << DAC_DACCTRL_LEFTADJ_Pos) -#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ -#define DAC_DACCTRL_ENABLE (0x1ul << DAC_DACCTRL_ENABLE_Pos) -#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ -#define DAC_DACCTRL_CCTRL_Msk (0x3ul << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL(value) ((DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))) -#define DAC_DACCTRL_CCTRL_CC12M_Val 0x0ul /**< \brief (DAC_DACCTRL) 1MHzAtmel Support - */ - -#ifndef _SAML21_DMAC_COMPONENT_ -#define _SAML21_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAML21_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2223 -#define REV_DMAC 0x221 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ -#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))) -#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))) -#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))) -#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))) -#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ - uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ - uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ - uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:16; /*!< bit: 0..15 Channel x Software Trigger */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG12 (1 << DMAC_SWTRIGCTRL_SWTRIG12_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG13 (1 << DMAC_SWTRIGCTRL_SWTRIG13_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG14 (1 << DMAC_SWTRIGCTRL_SWTRIG14_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG15 (1 << DMAC_SWTRIGCTRL_SWTRIG15_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))) -#define DMAC_SWTRIGCTRL_MASK 0x0000FFFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ - uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ - uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ - uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:16; /*!< bit: 0..15 Channel x Pending Interrupt */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT12 (1 << DMAC_INTSTATUS_CHINT12_Pos) -#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT13 (1 << DMAC_INTSTATUS_CHINT13_Pos) -#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT14 (1 << DMAC_INTSTATUS_CHINT14_Pos) -#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT15 (1 << DMAC_INTSTATUS_CHINT15_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (0xFFFFul << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))) -#define DMAC_INTSTATUS_MASK 0x0000FFFFul /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ - uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ - uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ - uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:16; /*!< bit: 0..15 Busy Channel x */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ -#define DMAC_BUSYCH_BUSYCH12 (1 << DMAC_BUSYCH_BUSYCH12_Pos) -#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ -#define DMAC_BUSYCH_BUSYCH13 (1 << DMAC_BUSYCH_BUSYCH13_Pos) -#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ -#define DMAC_BUSYCH_BUSYCH14 (1 << DMAC_BUSYCH_BUSYCH14_Pos) -#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ -#define DMAC_BUSYCH_BUSYCH15 (1 << DMAC_BUSYCH_BUSYCH15_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFFul << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))) -#define DMAC_BUSYCH_MASK 0x0000FFFFul /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ - uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ - uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ - uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:16; /*!< bit: 0..15 Pending Channel x */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ -#define DMAC_PENDCH_PENDCH12 (1 << DMAC_PENDCH_PENDCH12_Pos) -#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ -#define DMAC_PENDCH_PENDCH13 (1 << DMAC_PENDCH_PENDCH13_Pos) -#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ -#define DMAC_PENDCH_PENDCH14 (1 << DMAC_PENDCH_PENDCH14_Pos) -#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ -#define DMAC_PENDCH_PENDCH15 (1 << DMAC_PENDCH_PENDCH15_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (0xFFFFul << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))) -#define DMAC_PENDCH_MASK 0x0000FFFFul /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))) -#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))) -#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))) -#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ -#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */ - -#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ -#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos) -#define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))) -#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Channel run in standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ -#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel run in standby */ -#define DMAC_CHCTRLA_RUNSTDBY (0x1ul << DMAC_CHCTRLA_RUNSTDBY_Pos) -#define DMAC_CHCTRLA_MASK 0x43ul /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ -#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ - -#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ -#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))) -#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ -#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ -#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ -#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos) -#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ -#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos) -#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ -#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))) -#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ -#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))) -#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ -#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ -#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))) -#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ -#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ -#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))) -#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ -#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))) -#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 */ -#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 */ -#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 */ -#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 */ -#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 */ -#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 */ -#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 */ -#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 */ -#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */ - -/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */ - -#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */ -#define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos) -#define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))) -#define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */ - -/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SRCADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */ - -#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */ -#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos) -#define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))) -#define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */ - -/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_DSTADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */ - -#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */ -#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos) -#define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))) -#define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */ - -/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_DESCADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */ - -#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */ -#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos) -#define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))) -#define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */ - -/** \brief DMAC APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ - __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ - __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ - __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ - __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ - __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ - RoReg8 Reserved1[0x2]; - __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ - __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ - RoReg8 Reserved2[0x8]; - __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ - RoReg8 Reserved3[0x2]; - __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ - __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ - __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ - __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ - __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ - __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ - RoReg8 Reserved4[0x3]; - __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ - __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ - RoReg8 Reserved5[0x3]; - __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ - RoReg8 Reserved6[0x4]; - __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ - __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ - __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ - __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ -} Dmac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief DMAC Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ - __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ - __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ - __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ - __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ -} DmacDescriptor -#ifdef __GNUC__ -__attribute__ ((aligned (8))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#ifdef __GNUC__ -#define SECTION_DMAC_DESCRIPTOR __attribute__ ((section(".lpram"))) -#elif defined(__ICCARM__) -#define SECTION_DMAC_DESCRIPTOR @".lpram" -#endif - -/*@}*/ - -#endif /* _SAML21_DMAC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dsu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dsu.h deleted file mode 100644 index e936bf17e98..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dsu.h +++ /dev/null @@ -1,630 +0,0 @@ -/** - * \file - * - * \brief Component description for DSU - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_DSU_COMPONENT_ -#define _SAML21_DSU_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DSU */ -/* ========================================================================== */ -/** \addtogroup SAML21_DSU Device Service Unit */ -/*@{*/ - -#define DSU_U2209 -#define REV_DSU 0x250 - -/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */ - uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */ - uint8_t CE:1; /*!< bit: 4 Chip-Erase */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */ - uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ -#define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */ - -#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ -#define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos) -#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */ -#define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos) -#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */ -#define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos) -#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */ -#define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos) -#define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */ -#define DSU_CTRL_ARR (0x1ul << DSU_CTRL_ARR_Pos) -#define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */ -#define DSU_CTRL_SMSA (0x1ul << DSU_CTRL_SMSA_Pos) -#define DSU_CTRL_MASK 0xDDul /**< \brief (DSU_CTRL) MASK Register */ - -/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DONE:1; /*!< bit: 0 Done */ - uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ - uint8_t BERR:1; /*!< bit: 2 Bus Error */ - uint8_t FAIL:1; /*!< bit: 3 Failure */ - uint8_t PERR:1; /*!< bit: 4 Protection Error */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ -#define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */ - -#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ -#define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos) -#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ -#define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos) -#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ -#define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos) -#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ -#define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos) -#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ -#define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos) -#define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */ - -/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PROT:1; /*!< bit: 0 Protected */ - uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ - uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ - uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ - uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ -#define DSU_STATUSB_RESETVALUE 0x00ul /**< \brief (DSU_STATUSB reset_value) Status B */ - -#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ -#define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos) -#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ -#define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos) -#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ -#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos) -#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ -#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos) -#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ -#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos) -#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))) -#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ -#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos) -#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */ - -/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */ - uint32_t ADDR:30; /*!< bit: 2..31 Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ -#define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */ - -#define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */ -#define DSU_ADDR_AMOD_Msk (0x3ul << DSU_ADDR_AMOD_Pos) -#define DSU_ADDR_AMOD(value) ((DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))) -#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ -#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos) -#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))) -#define DSU_ADDR_MASK 0xFFFFFFFFul /**< \brief (DSU_ADDR) MASK Register */ - -/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t LENGTH:30; /*!< bit: 2..31 Length */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_LENGTH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ -#define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */ - -#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ -#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos) -#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))) -#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */ - -/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ -#define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */ - -#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ -#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos) -#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))) -#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */ - -/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ -#define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ - -#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ -#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos) -#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))) -#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */ - -/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ - uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */ - uint32_t DIE:4; /*!< bit: 12..15 Die Number */ - uint32_t SERIES:6; /*!< bit: 16..21 Series */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t FAMILY:5; /*!< bit: 23..27 Family */ - uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ - -#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ -#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos) -#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))) -#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */ -#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos) -#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))) -#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */ -#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos) -#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))) -#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */ -#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos) -#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))) -#define DSU_DID_SERIES_0_Val 0x0ul /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */ -#define DSU_DID_SERIES_1_Val 0x1ul /**< \brief (DSU_DID) Cortex-M0+ processor, USB */ -#define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos) -#define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos) -#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */ -#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos) -#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))) -#define DSU_DID_FAMILY_0_Val 0x0ul /**< \brief (DSU_DID) General purpose microcontroller */ -#define DSU_DID_FAMILY_1_Val 0x1ul /**< \brief (DSU_DID) PicoPower */ -#define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos) -#define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) -#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ -#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos) -#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))) -#define DSU_DID_PROCESSOR_0_Val 0x0ul /**< \brief (DSU_DID) Cortex-M0 */ -#define DSU_DID_PROCESSOR_1_Val 0x1ul /**< \brief (DSU_DID) Cortex-M0+ */ -#define DSU_DID_PROCESSOR_2_Val 0x2ul /**< \brief (DSU_DID) Cortex-M3 */ -#define DSU_DID_PROCESSOR_3_Val 0x3ul /**< \brief (DSU_DID) Cortex-M4 */ -#define DSU_DID_PROCESSOR_0 (DSU_DID_PROCESSOR_0_Val << DSU_DID_PROCESSOR_Pos) -#define DSU_DID_PROCESSOR_1 (DSU_DID_PROCESSOR_1_Val << DSU_DID_PROCESSOR_Pos) -#define DSU_DID_PROCESSOR_2 (DSU_DID_PROCESSOR_2_Val << DSU_DID_PROCESSOR_Pos) -#define DSU_DID_PROCESSOR_3 (DSU_DID_PROCESSOR_3_Val << DSU_DID_PROCESSOR_Pos) -#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */ - -/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */ -#define DSU_DCFG_RESETVALUE 0x00000000ul /**< \brief (DSU_DCFG reset_value) Device Configuration */ - -#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */ -#define DSU_DCFG_DCFG_Msk (0xFFFFFFFFul << DSU_DCFG_DCFG_Pos) -#define DSU_DCFG_DCFG(value) ((DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))) -#define DSU_DCFG_MASK 0xFFFFFFFFul /**< \brief (DSU_DCFG) MASK Register */ - -/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EPRES:1; /*!< bit: 0 Entry Present */ - uint32_t FMT:1; /*!< bit: 1 Format */ - uint32_t :10; /*!< bit: 2..11 Reserved */ - uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_ENTRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */ - -#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */ -#define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos) -#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */ -#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos) -#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */ -#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos) -#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))) -#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */ - -/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t END:32; /*!< bit: 0..31 End Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_END_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */ -#define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */ - -#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ -#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos) -#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos))) -#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */ - -/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_MEMTYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */ -#define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */ - -#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ -#define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos) -#define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */ - -/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ - uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID4_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ -#define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ - -#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ -#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos) -#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))) -#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */ -#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos) -#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))) -#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */ - -/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} DSU_PID5_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */ -#define DSU_PID5_MASK 0x00000000ul /**< \brief (DSU_PID5) MASK Register */ - -/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} DSU_PID6_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */ -#define DSU_PID6_MASK 0x00000000ul /**< \brief (DSU_PID6) MASK Register */ - -/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} DSU_PID7_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */ -#define DSU_PID7_MASK 0x00000000ul /**< \brief (DSU_PID7) MASK Register */ - -/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ -#define DSU_PID0_RESETVALUE 0x00000000ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ - -#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ -#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos) -#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))) -#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */ - -/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ - uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ -#define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ - -#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ -#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos) -#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))) -#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ -#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos) -#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))) -#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */ - -/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ - uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ - uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ -#define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ - -#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ -#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos) -#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))) -#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ -#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos) -#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ -#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos) -#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))) -#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */ - -/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ - uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ -#define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ - -#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ -#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos) -#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))) -#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ -#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos) -#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))) -#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */ - -/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ -#define DSU_CID0_RESETVALUE 0x00000000ul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ - -#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ -#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos) -#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))) -#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */ - -/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ - uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ -#define DSU_CID1_RESETVALUE 0x00000000ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ - -#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ -#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos) -#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))) -#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ -#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos) -#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))) -#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */ - -/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ -#define DSU_CID2_RESETVALUE 0x00000000ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ - -#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ -#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos) -#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))) -#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */ - -/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ -#define DSU_CID3_RESETVALUE 0x00000000ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ - -#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ -#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos) -#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))) -#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */ - -/** \brief DSU hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ - __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ - __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ - RoReg8 Reserved1[0x1]; - __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ - __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ - __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ - __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ - __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ - RoReg8 Reserved2[0xD4]; - __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */ - RoReg8 Reserved3[0xF08]; - __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ - __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ - RoReg8 Reserved4[0xFC0]; - __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ - __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ - __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ - __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */ - __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */ - __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ - __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ - __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ - __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ - __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ - __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ - __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ - __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ -} Dsu; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_DSU_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_eic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_eic.h deleted file mode 100644 index 930554bf925..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_eic.h +++ /dev/null @@ -1,439 +0,0 @@ -/** - * \file - * - * \brief Component description for EIC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_EIC_COMPONENT_ -#define _SAML21_EIC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR EIC */ -/* ========================================================================== */ -/** \addtogroup SAML21_EIC External Interrupt Controller */ -/*@{*/ - -#define EIC_U2254 -#define REV_EIC 0x200 - -/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control */ -#define EIC_CTRLA_RESETVALUE 0x00ul /**< \brief (EIC_CTRLA reset_value) Control */ - -#define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */ -#define EIC_CTRLA_SWRST (0x1ul << EIC_CTRLA_SWRST_Pos) -#define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */ -#define EIC_CTRLA_ENABLE (0x1ul << EIC_CTRLA_ENABLE_Pos) -#define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */ -#define EIC_CTRLA_CKSEL (0x1ul << EIC_CTRLA_CKSEL_Pos) -#define EIC_CTRLA_MASK 0x13ul /**< \brief (EIC_CTRLA) MASK Register */ - -/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) NMI Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t NMISENSE:3; /*!< bit: 0.. 2 NMI Input Sense Configuration */ - uint8_t NMIFILTEN:1; /*!< bit: 3 NMI Filter Enable */ - uint8_t NMIASYNCH:1; /*!< bit: 4 NMI Asynchronous edge Detection Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_NMICTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) NMI Control */ -#define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) NMI Control */ - -#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) NMI Input Sense Configuration */ -#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))) -#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */ -#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising edge detection */ -#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling edge detection */ -#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both edges detection */ -#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High level detection */ -#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low level detection */ -#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) NMI Filter Enable */ -#define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos) -#define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) NMI Asynchronous edge Detection Enable */ -#define EIC_NMICTRL_NMIASYNCH (0x1ul << EIC_NMICTRL_NMIASYNCH_Pos) -#define EIC_NMICTRL_MASK 0x1Ful /**< \brief (EIC_NMICTRL) MASK Register */ - -/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) NMI Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t NMI:1; /*!< bit: 0 NMI Interrupt Flag */ - uint16_t :15; /*!< bit: 1..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} EIC_NMIFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) NMI Interrupt Flag */ -#define EIC_NMIFLAG_RESETVALUE 0x0000ul /**< \brief (EIC_NMIFLAG reset_value) NMI Interrupt Flag */ - -#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) NMI Interrupt Flag */ -#define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos) -#define EIC_NMIFLAG_MASK 0x0001ul /**< \brief (EIC_NMIFLAG) MASK Register */ - -/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Syncbusy register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software reset synchronisation */ - uint32_t ENABLE:1; /*!< bit: 1 Enable synchronisation */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Syncbusy register */ -#define EIC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (EIC_SYNCBUSY reset_value) Syncbusy register */ - -#define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software reset synchronisation */ -#define EIC_SYNCBUSY_SWRST (0x1ul << EIC_SYNCBUSY_SWRST_Pos) -#define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable synchronisation */ -#define EIC_SYNCBUSY_ENABLE (0x1ul << EIC_SYNCBUSY_ENABLE_Pos) -#define EIC_SYNCBUSY_MASK 0x00000003ul /**< \brief (EIC_SYNCBUSY) MASK Register */ - -/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */ -#define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */ - -#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos) -#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))) -#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */ - -/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */ -#define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Disable */ -#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos) -#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))) -#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */ - -/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */ -#define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */ - -#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Disable */ -#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos) -#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))) -#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */ - -/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Flag */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt Flag */ -#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos) -#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))) -#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */ - -/* -------- EIC_EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) EIC Asynchronous edge Detection Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ASYNCH:16; /*!< bit: 0..15 EIC Asynchronous edge Detection Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_EIC_ASYNCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_EIC_ASYNCH offset) EIC Asynchronous edge Detection Enable */ -#define EIC_EIC_ASYNCH_RESETVALUE 0x00000000ul /**< \brief (EIC_EIC_ASYNCH reset_value) EIC Asynchronous edge Detection Enable */ - -#define EIC_EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_EIC_ASYNCH) EIC Asynchronous edge Detection Enable */ -#define EIC_EIC_ASYNCH_ASYNCH_Msk (0xFFFFul << EIC_EIC_ASYNCH_ASYNCH_Pos) -#define EIC_EIC_ASYNCH_ASYNCH(value) ((EIC_EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_EIC_ASYNCH_ASYNCH_Pos))) -#define EIC_EIC_ASYNCH_MASK 0x0000FFFFul /**< \brief (EIC_EIC_ASYNCH) MASK Register */ - -/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) Configuration n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */ - uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */ - uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */ - uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */ - uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */ - uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */ - uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */ - uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */ - uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */ - uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */ - uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */ - uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */ - uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */ - uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */ - uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */ - uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_CONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) Configuration n */ -#define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */ - -#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */ -#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))) -#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */ -#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos) -#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */ -#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))) -#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */ -#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos) -#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */ -#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))) -#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */ -#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos) -#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */ -#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))) -#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */ -#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos) -#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */ -#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))) -#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */ -#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos) -#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */ -#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))) -#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */ -#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos) -#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */ -#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))) -#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */ -#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos) -#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */ -#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))) -#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */ -#define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos) -#define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */ - -/** \brief EIC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ - __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) NMI Control */ - __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) NMI Interrupt Flag */ - __I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Syncbusy register */ - __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */ - __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */ - __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */ - __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */ - __IO EIC_EIC_ASYNCH_Type EIC_ASYNCH; /**< \brief Offset: 0x18 (R/W 32) EIC Asynchronous edge Detection Enable */ - __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) Configuration n */ -} Eic; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_EIC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_evsys.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_evsys.h deleted file mode 100644 index 56d5ed21f08..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_evsys.h +++ /dev/null @@ -1,621 +0,0 @@ -/** - * \file - * - * \brief Component description for EVSYS - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_EVSYS_COMPONENT_ -#define _SAML21_EVSYS_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR EVSYS */ -/* ========================================================================== */ -/** \addtogroup SAML21_EVSYS Event System Interface */ -/*@{*/ - -#define EVSYS_U2256 -#define REV_EVSYS 0x100 - -/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EVSYS_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CTRLA_OFFSET 0x00 /**< \brief (EVSYS_CTRLA offset) Control */ -#define EVSYS_CTRLA_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRLA reset_value) Control */ - -#define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */ -#define EVSYS_CTRLA_SWRST (0x1ul << EVSYS_CTRLA_SWRST_Pos) -#define EVSYS_CTRLA_MASK 0x01ul /**< \brief (EVSYS_CTRLA) MASK Register */ - -/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ - uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ - uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ - uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ - uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ - uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ - uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ - uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ - uint32_t USRRDY8:1; /*!< bit: 8 Channel 8 User Ready */ - uint32_t USRRDY9:1; /*!< bit: 9 Channel 9 User Ready */ - uint32_t USRRDY10:1; /*!< bit: 10 Channel 10 User Ready */ - uint32_t USRRDY11:1; /*!< bit: 11 Channel 11 User Ready */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t CHBUSY0:1; /*!< bit: 16 Channel 0 Busy */ - uint32_t CHBUSY1:1; /*!< bit: 17 Channel 1 Busy */ - uint32_t CHBUSY2:1; /*!< bit: 18 Channel 2 Busy */ - uint32_t CHBUSY3:1; /*!< bit: 19 Channel 3 Busy */ - uint32_t CHBUSY4:1; /*!< bit: 20 Channel 4 Busy */ - uint32_t CHBUSY5:1; /*!< bit: 21 Channel 5 Busy */ - uint32_t CHBUSY6:1; /*!< bit: 22 Channel 6 Busy */ - uint32_t CHBUSY7:1; /*!< bit: 23 Channel 7 Busy */ - uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ - uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ - uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ - uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t USRRDY:12; /*!< bit: 0..11 Channel x User Ready */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t CHBUSY:12; /*!< bit: 16..27 Channel x Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */ -#define EVSYS_CHSTATUS_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */ - -#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */ -#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos) -#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */ -#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos) -#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */ -#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos) -#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */ -#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos) -#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */ -#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos) -#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */ -#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos) -#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */ -#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos) -#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */ -#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos) -#define EVSYS_CHSTATUS_USRRDY8_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */ -#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos) -#define EVSYS_CHSTATUS_USRRDY9_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */ -#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos) -#define EVSYS_CHSTATUS_USRRDY10_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */ -#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos) -#define EVSYS_CHSTATUS_USRRDY11_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */ -#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos) -#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */ -#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFFul << EVSYS_CHSTATUS_USRRDY_Pos) -#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))) -#define EVSYS_CHSTATUS_CHBUSY0_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */ -#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos) -#define EVSYS_CHSTATUS_CHBUSY1_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */ -#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos) -#define EVSYS_CHSTATUS_CHBUSY2_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */ -#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos) -#define EVSYS_CHSTATUS_CHBUSY3_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */ -#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos) -#define EVSYS_CHSTATUS_CHBUSY4_Pos 20 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */ -#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos) -#define EVSYS_CHSTATUS_CHBUSY5_Pos 21 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */ -#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos) -#define EVSYS_CHSTATUS_CHBUSY6_Pos 22 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */ -#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos) -#define EVSYS_CHSTATUS_CHBUSY7_Pos 23 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */ -#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos) -#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */ -#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos) -#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */ -#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos) -#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */ -#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos) -#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */ -#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos) -#define EVSYS_CHSTATUS_CHBUSY_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */ -#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFFul << EVSYS_CHSTATUS_CHBUSY_Pos) -#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))) -#define EVSYS_CHSTATUS_MASK 0x0FFF0FFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */ - -/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection Interrupt Enable */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */ -#define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */ - -#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos) -#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos) -#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos) -#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos) -#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos) -#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos) -#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos) -#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos) -#define EVSYS_INTENCLR_OVR8_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos) -#define EVSYS_INTENCLR_OVR9_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos) -#define EVSYS_INTENCLR_OVR10_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos) -#define EVSYS_INTENCLR_OVR11_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos) -#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR_Msk (0xFFFul << EVSYS_INTENCLR_OVR_Pos) -#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))) -#define EVSYS_INTENCLR_EVD0_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos) -#define EVSYS_INTENCLR_EVD1_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos) -#define EVSYS_INTENCLR_EVD2_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos) -#define EVSYS_INTENCLR_EVD3_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos) -#define EVSYS_INTENCLR_EVD4_Pos 20 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos) -#define EVSYS_INTENCLR_EVD5_Pos 21 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos) -#define EVSYS_INTENCLR_EVD6_Pos 22 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos) -#define EVSYS_INTENCLR_EVD7_Pos 23 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos) -#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos) -#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos) -#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos) -#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos) -#define EVSYS_INTENCLR_EVD_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD_Msk (0xFFFul << EVSYS_INTENCLR_EVD_Pos) -#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))) -#define EVSYS_INTENCLR_MASK 0x0FFF0FFFul /**< \brief (EVSYS_INTENCLR) MASK Register */ - -/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection Interrupt Enable */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */ -#define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */ - -#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos) -#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos) -#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos) -#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos) -#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos) -#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos) -#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos) -#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos) -#define EVSYS_INTENSET_OVR8_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos) -#define EVSYS_INTENSET_OVR9_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos) -#define EVSYS_INTENSET_OVR10_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos) -#define EVSYS_INTENSET_OVR11_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos) -#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR_Msk (0xFFFul << EVSYS_INTENSET_OVR_Pos) -#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))) -#define EVSYS_INTENSET_EVD0_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos) -#define EVSYS_INTENSET_EVD1_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos) -#define EVSYS_INTENSET_EVD2_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos) -#define EVSYS_INTENSET_EVD3_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos) -#define EVSYS_INTENSET_EVD4_Pos 20 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos) -#define EVSYS_INTENSET_EVD5_Pos 21 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos) -#define EVSYS_INTENSET_EVD6_Pos 22 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos) -#define EVSYS_INTENSET_EVD7_Pos 23 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos) -#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos) -#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos) -#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos) -#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos) -#define EVSYS_INTENSET_EVD_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD_Msk (0xFFFul << EVSYS_INTENSET_EVD_Pos) -#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))) -#define EVSYS_INTENSET_MASK 0x0FFF0FFFul /**< \brief (EVSYS_INTENSET) MASK Register */ - -/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ - uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun */ - uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun */ - uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun */ - uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection */ - uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection */ - uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection */ - uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection */ - uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection */ - uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection */ - uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection */ - uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */ -#define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */ -#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos) -#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */ -#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos) -#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */ -#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos) -#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */ -#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos) -#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */ -#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos) -#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */ -#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos) -#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */ -#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos) -#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */ -#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos) -#define EVSYS_INTFLAG_OVR8_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */ -#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos) -#define EVSYS_INTFLAG_OVR9_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */ -#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos) -#define EVSYS_INTFLAG_OVR10_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */ -#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos) -#define EVSYS_INTFLAG_OVR11_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */ -#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos) -#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */ -#define EVSYS_INTFLAG_OVR_Msk (0xFFFul << EVSYS_INTFLAG_OVR_Pos) -#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))) -#define EVSYS_INTFLAG_EVD0_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */ -#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos) -#define EVSYS_INTFLAG_EVD1_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */ -#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos) -#define EVSYS_INTFLAG_EVD2_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */ -#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos) -#define EVSYS_INTFLAG_EVD3_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */ -#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos) -#define EVSYS_INTFLAG_EVD4_Pos 20 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */ -#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos) -#define EVSYS_INTFLAG_EVD5_Pos 21 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */ -#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos) -#define EVSYS_INTFLAG_EVD6_Pos 22 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */ -#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos) -#define EVSYS_INTFLAG_EVD7_Pos 23 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */ -#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos) -#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */ -#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos) -#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */ -#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos) -#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */ -#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos) -#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */ -#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos) -#define EVSYS_INTFLAG_EVD_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */ -#define EVSYS_INTFLAG_EVD_Msk (0xFFFul << EVSYS_INTFLAG_EVD_Pos) -#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))) -#define EVSYS_INTFLAG_MASK 0x0FFF0FFFul /**< \brief (EVSYS_INTFLAG) MASK Register */ - -/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x1C) ( /W 32) Software Event -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */ - uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */ - uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */ - uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */ - uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */ - uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */ - uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */ - uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */ - uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */ - uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */ - uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */ - uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHANNEL:12; /*!< bit: 0..11 Channel x Software Selection */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_SWEVT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_SWEVT_OFFSET 0x1C /**< \brief (EVSYS_SWEVT offset) Software Event */ -#define EVSYS_SWEVT_RESETVALUE 0x00000000ul /**< \brief (EVSYS_SWEVT reset_value) Software Event */ - -#define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */ -#define EVSYS_SWEVT_CHANNEL0 (1 << EVSYS_SWEVT_CHANNEL0_Pos) -#define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */ -#define EVSYS_SWEVT_CHANNEL1 (1 << EVSYS_SWEVT_CHANNEL1_Pos) -#define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */ -#define EVSYS_SWEVT_CHANNEL2 (1 << EVSYS_SWEVT_CHANNEL2_Pos) -#define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */ -#define EVSYS_SWEVT_CHANNEL3 (1 << EVSYS_SWEVT_CHANNEL3_Pos) -#define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */ -#define EVSYS_SWEVT_CHANNEL4 (1 << EVSYS_SWEVT_CHANNEL4_Pos) -#define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */ -#define EVSYS_SWEVT_CHANNEL5 (1 << EVSYS_SWEVT_CHANNEL5_Pos) -#define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */ -#define EVSYS_SWEVT_CHANNEL6 (1 << EVSYS_SWEVT_CHANNEL6_Pos) -#define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */ -#define EVSYS_SWEVT_CHANNEL7 (1 << EVSYS_SWEVT_CHANNEL7_Pos) -#define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */ -#define EVSYS_SWEVT_CHANNEL8 (1 << EVSYS_SWEVT_CHANNEL8_Pos) -#define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */ -#define EVSYS_SWEVT_CHANNEL9 (1 << EVSYS_SWEVT_CHANNEL9_Pos) -#define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */ -#define EVSYS_SWEVT_CHANNEL10 (1 << EVSYS_SWEVT_CHANNEL10_Pos) -#define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */ -#define EVSYS_SWEVT_CHANNEL11 (1 << EVSYS_SWEVT_CHANNEL11_Pos) -#define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */ -#define EVSYS_SWEVT_CHANNEL_Msk (0xFFFul << EVSYS_SWEVT_CHANNEL_Pos) -#define EVSYS_SWEVT_CHANNEL(value) ((EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))) -#define EVSYS_SWEVT_MASK 0x00000FFFul /**< \brief (EVSYS_SWEVT) MASK Register */ - -/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x20) (R/W 32) Channel n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */ - uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */ - uint32_t :2; /*!< bit: 12..13 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */ - uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_CHANNEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CHANNEL_OFFSET 0x20 /**< \brief (EVSYS_CHANNEL offset) Channel n */ -#define EVSYS_CHANNEL_RESETVALUE 0x00008000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel n */ - -#define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */ -#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos) -#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))) -#define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */ -#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))) -#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */ -#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */ -#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */ -#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */ -#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))) -#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */ -#define EVSYS_CHANNEL_RUNSTDBY (0x1ul << EVSYS_CHANNEL_RUNSTDBY_Pos) -#define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */ -#define EVSYS_CHANNEL_ONDEMAND (0x1ul << EVSYS_CHANNEL_ONDEMAND_Pos) -#define EVSYS_CHANNEL_MASK 0x0000CF7Ful /**< \brief (EVSYS_CHANNEL) MASK Register */ - -/* -------- EVSYS_USER : (EVSYS Offset: 0x80) (R/W 32) User Multiplexer n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHANNEL:5; /*!< bit: 0.. 4 Channel Event Selection */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_USER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_USER_OFFSET 0x80 /**< \brief (EVSYS_USER offset) User Multiplexer n */ -#define EVSYS_USER_RESETVALUE 0x00000000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer n */ - -#define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */ -#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos) -#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))) -#define EVSYS_USER_MASK 0x0000001Ful /**< \brief (EVSYS_USER) MASK Register */ - -/** \brief EVSYS hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ - RoReg8 Reserved1[0xB]; - __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ - __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ - __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ - __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ - __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x1C ( /W 32) Software Event */ - __IO EVSYS_CHANNEL_Type CHANNEL[12]; /**< \brief Offset: 0x20 (R/W 32) Channel n */ - RoReg8 Reserved2[0x30]; - __IO EVSYS_USER_Type USER[45]; /**< \brief Offset: 0x80 (R/W 32) User Multiplexer n */ -} Evsys; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_EVSYS_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_gclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_gclk.h deleted file mode 100644 index 743797da847..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_gclk.h +++ /dev/null @@ -1,235 +0,0 @@ -/** - * \file - * - * \brief Component description for GCLK - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_GCLK_COMPONENT_ -#define _SAML21_GCLK_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR GCLK */ -/* ========================================================================== */ -/** \addtogroup SAML21_GCLK Generic Clock Generator */ -/*@{*/ - -#define GCLK_U2122 -#define REV_GCLK 0x111 - -/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} GCLK_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */ -#define GCLK_CTRLA_RESETVALUE 0x00ul /**< \brief (GCLK_CTRLA reset_value) Control */ - -#define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */ -#define GCLK_CTRLA_SWRST (0x1ul << GCLK_CTRLA_SWRST_Pos) -#define GCLK_CTRLA_MASK 0x01ul /**< \brief (GCLK_CTRLA) MASK Register */ - -/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */ - uint32_t :1; /*!< bit: 1 Reserved */ - uint32_t GENCTRL:9; /*!< bit: 2..10 Generic Clock Generator Control Synchronization Busy bits */ - uint32_t :21; /*!< bit: 11..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} GCLK_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */ -#define GCLK_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */ - -#define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */ -#define GCLK_SYNCBUSY_SWRST (0x1ul << GCLK_SYNCBUSY_SWRST_Pos) -#define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control Synchronization Busy bits */ -#define GCLK_SYNCBUSY_GENCTRL_Msk (0x1FFul << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL(value) ((GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))) -#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val 0x0ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val 0x1ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val 0x2ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val 0x3ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val 0x4ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val 0x5ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val 0x6ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val 0x7ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val 0x8ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */ -#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos) -#define GCLK_SYNCBUSY_MASK 0x000007FDul /**< \brief (GCLK_SYNCBUSY) MASK Register */ - -/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */ - uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */ - uint32_t OOV:1; /*!< bit: 10 Output Off Value */ - uint32_t OE:1; /*!< bit: 11 Output Enable */ - uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */ - uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t DIV:16; /*!< bit: 16..31 Division Factor */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} GCLK_GENCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */ -#define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */ - -#define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */ -#define GCLK_GENCTRL_SRC_Msk (0xFul << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))) -#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */ -#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */ -#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */ -#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */ -#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */ -#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */ -#define GCLK_GENCTRL_SRC_OSC16M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC16M oscillator output */ -#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */ -#define GCLK_GENCTRL_SRC_DPLL96M_Val 0x8ul /**< \brief (GCLK_GENCTRL) DPLL96M output */ -#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSC16M (GCLK_GENCTRL_SRC_OSC16M_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_DPLL96M (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */ -#define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos) -#define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */ -#define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos) -#define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */ -#define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos) -#define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */ -#define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos) -#define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */ -#define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos) -#define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */ -#define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos) -#define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */ -#define GCLK_GENCTRL_DIV_Msk (0xFFFFul << GCLK_GENCTRL_DIV_Pos) -#define GCLK_GENCTRL_DIV(value) ((GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))) -#define GCLK_GENCTRL_MASK 0xFFFF3F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */ - -/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */ - uint32_t :2; /*!< bit: 4.. 5 Reserved */ - uint32_t CHEN:1; /*!< bit: 6 Channel Enable */ - uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} GCLK_PCHCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */ -#define GCLK_PCHCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */ - -#define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */ -#define GCLK_PCHCTRL_GEN_Msk (0xFul << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_GEN(value) ((GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))) -#define GCLK_PCHCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */ -#define GCLK_PCHCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */ -#define GCLK_PCHCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */ -#define GCLK_PCHCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */ -#define GCLK_PCHCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */ -#define GCLK_PCHCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */ -#define GCLK_PCHCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */ -#define GCLK_PCHCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */ -#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos) -#define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */ -#define GCLK_PCHCTRL_CHEN (0x1ul << GCLK_PCHCTRL_CHEN_Pos) -#define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */ -#define GCLK_PCHCTRL_WRTLOCK (0x1ul << GCLK_PCHCTRL_WRTLOCK_Pos) -#define GCLK_PCHCTRL_MASK 0x000000CFul /**< \brief (GCLK_PCHCTRL) MASK Register */ - -/** \brief GCLK hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */ - RoReg8 Reserved2[0x18]; - __IO GCLK_GENCTRL_Type GENCTRL[9]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */ - RoReg8 Reserved3[0x3C]; - __IO GCLK_PCHCTRL_Type PCHCTRL[36]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */ -} Gclk; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_GCLK_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mclk.h deleted file mode 100644 index 5a3ecc098a8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mclk.h +++ /dev/null @@ -1,531 +0,0 @@ -/** - * \file - * - * \brief Component description for MCLK - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_MCLK_COMPONENT_ -#define _SAML21_MCLK_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR MCLK */ -/* ========================================================================== */ -/** \addtogroup SAML21_MCLK Main Clock */ -/*@{*/ - -#define MCLK_U2234 -#define REV_MCLK 0x100 - -/* -------- MCLK_CTRLA : (MCLK Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t CFDEN:1; /*!< bit: 2 Clock Failure Detector Enable */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EMCLK:1; /*!< bit: 4 Emergency Clock Select */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} MCLK_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_CTRLA_OFFSET 0x00 /**< \brief (MCLK_CTRLA offset) Control A */ -#define MCLK_CTRLA_RESETVALUE 0x00ul /**< \brief (MCLK_CTRLA reset_value) Control A */ - -#define MCLK_CTRLA_CFDEN_Pos 2 /**< \brief (MCLK_CTRLA) Clock Failure Detector Enable */ -#define MCLK_CTRLA_CFDEN (0x1ul << MCLK_CTRLA_CFDEN_Pos) -#define MCLK_CTRLA_EMCLK_Pos 4 /**< \brief (MCLK_CTRLA) Emergency Clock Select */ -#define MCLK_CTRLA_EMCLK (0x1ul << MCLK_CTRLA_EMCLK_Pos) -#define MCLK_CTRLA_MASK 0x14ul /**< \brief (MCLK_CTRLA) MASK Register */ - -/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} MCLK_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */ -#define MCLK_INTENCLR_RESETVALUE 0x00ul /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */ - -#define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */ -#define MCLK_INTENCLR_CKRDY (0x1ul << MCLK_INTENCLR_CKRDY_Pos) -#define MCLK_INTENCLR_CFD_Pos 1 /**< \brief (MCLK_INTENCLR) Clock Failure Detector Interrupt Enable */ -#define MCLK_INTENCLR_CFD (0x1ul << MCLK_INTENCLR_CFD_Pos) -#define MCLK_INTENCLR_MASK 0x03ul /**< \brief (MCLK_INTENCLR) MASK Register */ - -/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} MCLK_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */ -#define MCLK_INTENSET_RESETVALUE 0x00ul /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */ - -#define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */ -#define MCLK_INTENSET_CKRDY (0x1ul << MCLK_INTENSET_CKRDY_Pos) -#define MCLK_INTENSET_CFD_Pos 1 /**< \brief (MCLK_INTENSET) Clock Failure Detector Interrupt Enable */ -#define MCLK_INTENSET_CFD (0x1ul << MCLK_INTENSET_CFD_Pos) -#define MCLK_INTENSET_MASK 0x03ul /**< \brief (MCLK_INTENSET) MASK Register */ - -/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ - uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} MCLK_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */ -#define MCLK_INTFLAG_RESETVALUE 0x01ul /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */ -#define MCLK_INTFLAG_CKRDY (0x1ul << MCLK_INTFLAG_CKRDY_Pos) -#define MCLK_INTFLAG_CFD_Pos 1 /**< \brief (MCLK_INTFLAG) Clock Failure Detector */ -#define MCLK_INTFLAG_CFD (0x1ul << MCLK_INTFLAG_CFD_Pos) -#define MCLK_INTFLAG_MASK 0x03ul /**< \brief (MCLK_INTFLAG) MASK Register */ - -/* -------- MCLK_CPUDIV : (MCLK Offset: 0x04) (R/W 8) CPU Clock Division -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CPUDIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} MCLK_CPUDIV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_CPUDIV_OFFSET 0x04 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */ -#define MCLK_CPUDIV_RESETVALUE 0x01ul /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */ - -#define MCLK_CPUDIV_CPUDIV_Pos 0 /**< \brief (MCLK_CPUDIV) CPU Clock Division Factor */ -#define MCLK_CPUDIV_CPUDIV_Msk (0xFFul << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_CPUDIV(value) ((MCLK_CPUDIV_CPUDIV_Msk & ((value) << MCLK_CPUDIV_CPUDIV_Pos))) -#define MCLK_CPUDIV_CPUDIV_DIV1_Val 0x1ul /**< \brief (MCLK_CPUDIV) Divide by 1 */ -#define MCLK_CPUDIV_CPUDIV_DIV2_Val 0x2ul /**< \brief (MCLK_CPUDIV) Divide by 2 */ -#define MCLK_CPUDIV_CPUDIV_DIV4_Val 0x4ul /**< \brief (MCLK_CPUDIV) Divide by 4 */ -#define MCLK_CPUDIV_CPUDIV_DIV8_Val 0x8ul /**< \brief (MCLK_CPUDIV) Divide by 8 */ -#define MCLK_CPUDIV_CPUDIV_DIV16_Val 0x10ul /**< \brief (MCLK_CPUDIV) Divide by 16 */ -#define MCLK_CPUDIV_CPUDIV_DIV32_Val 0x20ul /**< \brief (MCLK_CPUDIV) Divide by 32 */ -#define MCLK_CPUDIV_CPUDIV_DIV64_Val 0x40ul /**< \brief (MCLK_CPUDIV) Divide by 64 */ -#define MCLK_CPUDIV_CPUDIV_DIV128_Val 0x80ul /**< \brief (MCLK_CPUDIV) Divide by 128 */ -#define MCLK_CPUDIV_CPUDIV_DIV1 (MCLK_CPUDIV_CPUDIV_DIV1_Val << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_CPUDIV_DIV2 (MCLK_CPUDIV_CPUDIV_DIV2_Val << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_CPUDIV_DIV4 (MCLK_CPUDIV_CPUDIV_DIV4_Val << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_CPUDIV_DIV8 (MCLK_CPUDIV_CPUDIV_DIV8_Val << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_CPUDIV_DIV16 (MCLK_CPUDIV_CPUDIV_DIV16_Val << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_CPUDIV_DIV32 (MCLK_CPUDIV_CPUDIV_DIV32_Val << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_CPUDIV_DIV64 (MCLK_CPUDIV_CPUDIV_DIV64_Val << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_CPUDIV_DIV128 (MCLK_CPUDIV_CPUDIV_DIV128_Val << MCLK_CPUDIV_CPUDIV_Pos) -#define MCLK_CPUDIV_MASK 0xFFul /**< \brief (MCLK_CPUDIV) MASK Register */ - -/* -------- MCLK_LPDIV : (MCLK Offset: 0x05) (R/W 8) Low-Power Clock Division -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t LPDIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} MCLK_LPDIV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_LPDIV_OFFSET 0x05 /**< \brief (MCLK_LPDIV offset) Low-Power Clock Division */ -#define MCLK_LPDIV_RESETVALUE 0x01ul /**< \brief (MCLK_LPDIV reset_value) Low-Power Clock Division */ - -#define MCLK_LPDIV_LPDIV_Pos 0 /**< \brief (MCLK_LPDIV) Low-Power Clock Division Factor */ -#define MCLK_LPDIV_LPDIV_Msk (0xFFul << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_LPDIV(value) ((MCLK_LPDIV_LPDIV_Msk & ((value) << MCLK_LPDIV_LPDIV_Pos))) -#define MCLK_LPDIV_LPDIV_DIV1_Val 0x1ul /**< \brief (MCLK_LPDIV) Divide by 1 */ -#define MCLK_LPDIV_LPDIV_DIV2_Val 0x2ul /**< \brief (MCLK_LPDIV) Divide by 2 */ -#define MCLK_LPDIV_LPDIV_DIV4_Val 0x4ul /**< \brief (MCLK_LPDIV) Divide by 4 */ -#define MCLK_LPDIV_LPDIV_DIV8_Val 0x8ul /**< \brief (MCLK_LPDIV) Divide by 8 */ -#define MCLK_LPDIV_LPDIV_DIV16_Val 0x10ul /**< \brief (MCLK_LPDIV) Divide by 16 */ -#define MCLK_LPDIV_LPDIV_DIV32_Val 0x20ul /**< \brief (MCLK_LPDIV) Divide by 32 */ -#define MCLK_LPDIV_LPDIV_DIV64_Val 0x40ul /**< \brief (MCLK_LPDIV) Divide by 64 */ -#define MCLK_LPDIV_LPDIV_DIV128_Val 0x80ul /**< \brief (MCLK_LPDIV) Divide by 128 */ -#define MCLK_LPDIV_LPDIV_DIV1 (MCLK_LPDIV_LPDIV_DIV1_Val << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_LPDIV_DIV2 (MCLK_LPDIV_LPDIV_DIV2_Val << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_LPDIV_DIV4 (MCLK_LPDIV_LPDIV_DIV4_Val << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_LPDIV_DIV8 (MCLK_LPDIV_LPDIV_DIV8_Val << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_LPDIV_DIV16 (MCLK_LPDIV_LPDIV_DIV16_Val << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_LPDIV_DIV32 (MCLK_LPDIV_LPDIV_DIV32_Val << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_LPDIV_DIV64 (MCLK_LPDIV_LPDIV_DIV64_Val << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_LPDIV_DIV128 (MCLK_LPDIV_LPDIV_DIV128_Val << MCLK_LPDIV_LPDIV_Pos) -#define MCLK_LPDIV_MASK 0xFFul /**< \brief (MCLK_LPDIV) MASK Register */ - -/* -------- MCLK_BUPDIV : (MCLK Offset: 0x06) (R/W 8) Backup Clock Division -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BUPDIV:8; /*!< bit: 0.. 7 Backup Clock Division Factor */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} MCLK_BUPDIV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_BUPDIV_OFFSET 0x06 /**< \brief (MCLK_BUPDIV offset) Backup Clock Division */ -#define MCLK_BUPDIV_RESETVALUE 0x01ul /**< \brief (MCLK_BUPDIV reset_value) Backup Clock Division */ - -#define MCLK_BUPDIV_BUPDIV_Pos 0 /**< \brief (MCLK_BUPDIV) Backup Clock Division Factor */ -#define MCLK_BUPDIV_BUPDIV_Msk (0xFFul << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_BUPDIV(value) ((MCLK_BUPDIV_BUPDIV_Msk & ((value) << MCLK_BUPDIV_BUPDIV_Pos))) -#define MCLK_BUPDIV_BUPDIV_DIV1_Val 0x1ul /**< \brief (MCLK_BUPDIV) Divide by 1 */ -#define MCLK_BUPDIV_BUPDIV_DIV2_Val 0x2ul /**< \brief (MCLK_BUPDIV) Divide by 2 */ -#define MCLK_BUPDIV_BUPDIV_DIV4_Val 0x4ul /**< \brief (MCLK_BUPDIV) Divide by 4 */ -#define MCLK_BUPDIV_BUPDIV_DIV8_Val 0x8ul /**< \brief (MCLK_BUPDIV) Divide by 8 */ -#define MCLK_BUPDIV_BUPDIV_DIV16_Val 0x10ul /**< \brief (MCLK_BUPDIV) Divide by 16 */ -#define MCLK_BUPDIV_BUPDIV_DIV32_Val 0x20ul /**< \brief (MCLK_BUPDIV) Divide by 32 */ -#define MCLK_BUPDIV_BUPDIV_DIV64_Val 0x40ul /**< \brief (MCLK_BUPDIV) Divide by 64 */ -#define MCLK_BUPDIV_BUPDIV_DIV128_Val 0x80ul /**< \brief (MCLK_BUPDIV) Divide by 128 */ -#define MCLK_BUPDIV_BUPDIV_DIV1 (MCLK_BUPDIV_BUPDIV_DIV1_Val << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_BUPDIV_DIV2 (MCLK_BUPDIV_BUPDIV_DIV2_Val << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_BUPDIV_DIV4 (MCLK_BUPDIV_BUPDIV_DIV4_Val << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_BUPDIV_DIV8 (MCLK_BUPDIV_BUPDIV_DIV8_Val << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_BUPDIV_DIV16 (MCLK_BUPDIV_BUPDIV_DIV16_Val << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_BUPDIV_DIV32 (MCLK_BUPDIV_BUPDIV_DIV32_Val << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_BUPDIV_DIV64 (MCLK_BUPDIV_BUPDIV_DIV64_Val << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_BUPDIV_DIV128 (MCLK_BUPDIV_BUPDIV_DIV128_Val << MCLK_BUPDIV_BUPDIV_Pos) -#define MCLK_BUPDIV_MASK 0xFFul /**< \brief (MCLK_BUPDIV) MASK Register */ - -/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ - uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ - uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ - uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */ - uint32_t HPB4_:1; /*!< bit: 4 HPB4 AHB Clock Mask */ - uint32_t DSU_:1; /*!< bit: 5 DSU AHB Clock Mask */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t NVMCTRL_:1; /*!< bit: 8 NVMCTRL AHB Clock Mask */ - uint32_t HMCRAMCHS_:1; /*!< bit: 9 HMCRAMCHS AHB Clock Mask */ - uint32_t HMCRAMCLP_:1; /*!< bit: 10 HMCRAMCLP AHB Clock Mask */ - uint32_t DMAC_:1; /*!< bit: 11 DMAC AHB Clock Mask */ - uint32_t USB_:1; /*!< bit: 12 USB AHB Clock Mask */ - uint32_t PICOPRAM_:1; /*!< bit: 13 PICOPRAM AHB Clock Mask */ - uint32_t PAC_:1; /*!< bit: 14 PAC AHB Clock Mask */ - uint32_t NVMCTRL_PICACHU_:1; /*!< bit: 15 NVMCTRL_PICACHU AHB Clock Mask */ - uint32_t L2HBRIDGES_H_:1; /*!< bit: 16 L2HBRIDGES_H AHB Clock Mask */ - uint32_t H2LBRIDGES_H_:1; /*!< bit: 17 H2LBRIDGES_H AHB Clock Mask */ - uint32_t HMCRAMCHS_AHBSETUPKEEPER_:1; /*!< bit: 18 HMCRAMCHS_AHBSETUPKEEPER AHB Clock Mask */ - uint32_t HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_:1; /*!< bit: 19 HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MCLK_AHBMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */ -#define MCLK_AHBMASK_RESETVALUE 0x000FFFFFul /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */ - -#define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */ -#define MCLK_AHBMASK_HPB0 (0x1ul << MCLK_AHBMASK_HPB0_Pos) -#define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */ -#define MCLK_AHBMASK_HPB1 (0x1ul << MCLK_AHBMASK_HPB1_Pos) -#define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */ -#define MCLK_AHBMASK_HPB2 (0x1ul << MCLK_AHBMASK_HPB2_Pos) -#define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */ -#define MCLK_AHBMASK_HPB3 (0x1ul << MCLK_AHBMASK_HPB3_Pos) -#define MCLK_AHBMASK_HPB4_Pos 4 /**< \brief (MCLK_AHBMASK) HPB4 AHB Clock Mask */ -#define MCLK_AHBMASK_HPB4 (0x1ul << MCLK_AHBMASK_HPB4_Pos) -#define MCLK_AHBMASK_DSU_Pos 5 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */ -#define MCLK_AHBMASK_DSU (0x1ul << MCLK_AHBMASK_DSU_Pos) -#define MCLK_AHBMASK_NVMCTRL_Pos 8 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */ -#define MCLK_AHBMASK_NVMCTRL (0x1ul << MCLK_AHBMASK_NVMCTRL_Pos) -#define MCLK_AHBMASK_HMCRAMCHS_Pos 9 /**< \brief (MCLK_AHBMASK) HMCRAMCHS AHB Clock Mask */ -#define MCLK_AHBMASK_HMCRAMCHS (0x1ul << MCLK_AHBMASK_HMCRAMCHS_Pos) -#define MCLK_AHBMASK_HMCRAMCLP_Pos 10 /**< \brief (MCLK_AHBMASK) HMCRAMCLP AHB Clock Mask */ -#define MCLK_AHBMASK_HMCRAMCLP (0x1ul << MCLK_AHBMASK_HMCRAMCLP_Pos) -#define MCLK_AHBMASK_DMAC_Pos 11 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */ -#define MCLK_AHBMASK_DMAC (0x1ul << MCLK_AHBMASK_DMAC_Pos) -#define MCLK_AHBMASK_USB_Pos 12 /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */ -#define MCLK_AHBMASK_USB (0x1ul << MCLK_AHBMASK_USB_Pos) -#define MCLK_AHBMASK_PICOPRAM_Pos 13 /**< \brief (MCLK_AHBMASK) PICOPRAM AHB Clock Mask */ -#define MCLK_AHBMASK_PICOPRAM (0x1ul << MCLK_AHBMASK_PICOPRAM_Pos) -#define MCLK_AHBMASK_PAC_Pos 14 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */ -#define MCLK_AHBMASK_PAC (0x1ul << MCLK_AHBMASK_PAC_Pos) -#define MCLK_AHBMASK_NVMCTRL_PICACHU_Pos 15 /**< \brief (MCLK_AHBMASK) NVMCTRL_PICACHU AHB Clock Mask */ -#define MCLK_AHBMASK_NVMCTRL_PICACHU (0x1ul << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos) -#define MCLK_AHBMASK_L2HBRIDGES_H_Pos 16 /**< \brief (MCLK_AHBMASK) L2HBRIDGES_H AHB Clock Mask */ -#define MCLK_AHBMASK_L2HBRIDGES_H (0x1ul << MCLK_AHBMASK_L2HBRIDGES_H_Pos) -#define MCLK_AHBMASK_H2LBRIDGES_H_Pos 17 /**< \brief (MCLK_AHBMASK) H2LBRIDGES_H AHB Clock Mask */ -#define MCLK_AHBMASK_H2LBRIDGES_H (0x1ul << MCLK_AHBMASK_H2LBRIDGES_H_Pos) -#define MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_Pos 18 /**< \brief (MCLK_AHBMASK) HMCRAMCHS_AHBSETUPKEEPER AHB Clock Mask */ -#define MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER (0x1ul << MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_Pos) -#define MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_Pos 19 /**< \brief (MCLK_AHBMASK) HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask */ -#define MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE (0x1ul << MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_Pos) -#define MCLK_AHBMASK_MASK 0x000FFF3Ful /**< \brief (MCLK_AHBMASK) MASK Register */ - -/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PM_:1; /*!< bit: 0 PM APB Clock Enable */ - uint32_t MCLK_:1; /*!< bit: 1 MCLK APB Clock Enable */ - uint32_t RSTC_:1; /*!< bit: 2 RSTC APB Clock Enable */ - uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL APB Clock Enable */ - uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL APB Clock Enable */ - uint32_t SUPC_:1; /*!< bit: 5 SUPC APB Clock Enable */ - uint32_t GCLK_:1; /*!< bit: 6 GCLK APB Clock Enable */ - uint32_t WDT_:1; /*!< bit: 7 WDT APB Clock Enable */ - uint32_t RTC_:1; /*!< bit: 8 RTC APB Clock Enable */ - uint32_t EIC_:1; /*!< bit: 9 EIC APB Clock Enable */ - uint32_t PORT_:1; /*!< bit: 10 PORT APB Clock Enable */ - uint32_t TAL_:1; /*!< bit: 11 TAL APB Clock Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MCLK_APBAMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */ -#define MCLK_APBAMASK_RESETVALUE 0x00001FFFul /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */ - -#define MCLK_APBAMASK_PM_Pos 0 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */ -#define MCLK_APBAMASK_PM (0x1ul << MCLK_APBAMASK_PM_Pos) -#define MCLK_APBAMASK_MCLK_Pos 1 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */ -#define MCLK_APBAMASK_MCLK (0x1ul << MCLK_APBAMASK_MCLK_Pos) -#define MCLK_APBAMASK_RSTC_Pos 2 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */ -#define MCLK_APBAMASK_RSTC (0x1ul << MCLK_APBAMASK_RSTC_Pos) -#define MCLK_APBAMASK_OSCCTRL_Pos 3 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */ -#define MCLK_APBAMASK_OSCCTRL (0x1ul << MCLK_APBAMASK_OSCCTRL_Pos) -#define MCLK_APBAMASK_OSC32KCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */ -#define MCLK_APBAMASK_OSC32KCTRL (0x1ul << MCLK_APBAMASK_OSC32KCTRL_Pos) -#define MCLK_APBAMASK_SUPC_Pos 5 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */ -#define MCLK_APBAMASK_SUPC (0x1ul << MCLK_APBAMASK_SUPC_Pos) -#define MCLK_APBAMASK_GCLK_Pos 6 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */ -#define MCLK_APBAMASK_GCLK (0x1ul << MCLK_APBAMASK_GCLK_Pos) -#define MCLK_APBAMASK_WDT_Pos 7 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */ -#define MCLK_APBAMASK_WDT (0x1ul << MCLK_APBAMASK_WDT_Pos) -#define MCLK_APBAMASK_RTC_Pos 8 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */ -#define MCLK_APBAMASK_RTC (0x1ul << MCLK_APBAMASK_RTC_Pos) -#define MCLK_APBAMASK_EIC_Pos 9 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */ -#define MCLK_APBAMASK_EIC (0x1ul << MCLK_APBAMASK_EIC_Pos) -#define MCLK_APBAMASK_PORT_Pos 10 /**< \brief (MCLK_APBAMASK) PORT APB Clock Enable */ -#define MCLK_APBAMASK_PORT (0x1ul << MCLK_APBAMASK_PORT_Pos) -#define MCLK_APBAMASK_TAL_Pos 11 /**< \brief (MCLK_APBAMASK) TAL APB Clock Enable */ -#define MCLK_APBAMASK_TAL (0x1ul << MCLK_APBAMASK_TAL_Pos) -#define MCLK_APBAMASK_MASK 0x00000FFFul /**< \brief (MCLK_APBAMASK) MASK Register */ - -/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */ - uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ - uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MCLK_APBBMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */ -#define MCLK_APBBMASK_RESETVALUE 0x00000017ul /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */ - -#define MCLK_APBBMASK_USB_Pos 0 /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */ -#define MCLK_APBBMASK_USB (0x1ul << MCLK_APBBMASK_USB_Pos) -#define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */ -#define MCLK_APBBMASK_DSU (0x1ul << MCLK_APBBMASK_DSU_Pos) -#define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */ -#define MCLK_APBBMASK_NVMCTRL (0x1ul << MCLK_APBBMASK_NVMCTRL_Pos) -#define MCLK_APBBMASK_MASK 0x00000007ul /**< \brief (MCLK_APBBMASK) MASK Register */ - -/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 APB Clock Enable */ - uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 APB Clock Enable */ - uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 APB Clock Enable */ - uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 APB Clock Enable */ - uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 APB Clock Enable */ - uint32_t TCC0_:1; /*!< bit: 5 TCC0 APB Clock Enable */ - uint32_t TCC1_:1; /*!< bit: 6 TCC1 APB Clock Enable */ - uint32_t TCC2_:1; /*!< bit: 7 TCC2 APB Clock Enable */ - uint32_t TC0_:1; /*!< bit: 8 TC0 APB Clock Enable */ - uint32_t TC1_:1; /*!< bit: 9 TC1 APB Clock Enable */ - uint32_t TC2_:1; /*!< bit: 10 TC2 APB Clock Enable */ - uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ - uint32_t DAC_:1; /*!< bit: 12 DAC APB Clock Enable */ - uint32_t AES_:1; /*!< bit: 13 AES APB Clock Enable */ - uint32_t TRNG_:1; /*!< bit: 14 TRNG APB Clock Enable */ - uint32_t :17; /*!< bit: 15..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MCLK_APBCMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */ -#define MCLK_APBCMASK_RESETVALUE 0x00007FFFul /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */ - -#define MCLK_APBCMASK_SERCOM0_Pos 0 /**< \brief (MCLK_APBCMASK) SERCOM0 APB Clock Enable */ -#define MCLK_APBCMASK_SERCOM0 (0x1ul << MCLK_APBCMASK_SERCOM0_Pos) -#define MCLK_APBCMASK_SERCOM1_Pos 1 /**< \brief (MCLK_APBCMASK) SERCOM1 APB Clock Enable */ -#define MCLK_APBCMASK_SERCOM1 (0x1ul << MCLK_APBCMASK_SERCOM1_Pos) -#define MCLK_APBCMASK_SERCOM2_Pos 2 /**< \brief (MCLK_APBCMASK) SERCOM2 APB Clock Enable */ -#define MCLK_APBCMASK_SERCOM2 (0x1ul << MCLK_APBCMASK_SERCOM2_Pos) -#define MCLK_APBCMASK_SERCOM3_Pos 3 /**< \brief (MCLK_APBCMASK) SERCOM3 APB Clock Enable */ -#define MCLK_APBCMASK_SERCOM3 (0x1ul << MCLK_APBCMASK_SERCOM3_Pos) -#define MCLK_APBCMASK_SERCOM4_Pos 4 /**< \brief (MCLK_APBCMASK) SERCOM4 APB Clock Enable */ -#define MCLK_APBCMASK_SERCOM4 (0x1ul << MCLK_APBCMASK_SERCOM4_Pos) -#define MCLK_APBCMASK_TCC0_Pos 5 /**< \brief (MCLK_APBCMASK) TCC0 APB Clock Enable */ -#define MCLK_APBCMASK_TCC0 (0x1ul << MCLK_APBCMASK_TCC0_Pos) -#define MCLK_APBCMASK_TCC1_Pos 6 /**< \brief (MCLK_APBCMASK) TCC1 APB Clock Enable */ -#define MCLK_APBCMASK_TCC1 (0x1ul << MCLK_APBCMASK_TCC1_Pos) -#define MCLK_APBCMASK_TCC2_Pos 7 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */ -#define MCLK_APBCMASK_TCC2 (0x1ul << MCLK_APBCMASK_TCC2_Pos) -#define MCLK_APBCMASK_TC0_Pos 8 /**< \brief (MCLK_APBCMASK) TC0 APB Clock Enable */ -#define MCLK_APBCMASK_TC0 (0x1ul << MCLK_APBCMASK_TC0_Pos) -#define MCLK_APBCMASK_TC1_Pos 9 /**< \brief (MCLK_APBCMASK) TC1 APB Clock Enable */ -#define MCLK_APBCMASK_TC1 (0x1ul << MCLK_APBCMASK_TC1_Pos) -#define MCLK_APBCMASK_TC2_Pos 10 /**< \brief (MCLK_APBCMASK) TC2 APB Clock Enable */ -#define MCLK_APBCMASK_TC2 (0x1ul << MCLK_APBCMASK_TC2_Pos) -#define MCLK_APBCMASK_TC3_Pos 11 /**< \brief (MCLK_APBCMASK) TC3 APB Clock Enable */ -#define MCLK_APBCMASK_TC3 (0x1ul << MCLK_APBCMASK_TC3_Pos) -#define MCLK_APBCMASK_DAC_Pos 12 /**< \brief (MCLK_APBCMASK) DAC APB Clock Enable */ -#define MCLK_APBCMASK_DAC (0x1ul << MCLK_APBCMASK_DAC_Pos) -#define MCLK_APBCMASK_AES_Pos 13 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */ -#define MCLK_APBCMASK_AES (0x1ul << MCLK_APBCMASK_AES_Pos) -#define MCLK_APBCMASK_TRNG_Pos 14 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */ -#define MCLK_APBCMASK_TRNG (0x1ul << MCLK_APBCMASK_TRNG_Pos) -#define MCLK_APBCMASK_MASK 0x00007FFFul /**< \brief (MCLK_APBCMASK) MASK Register */ - -/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Clock Enable */ - uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */ - uint32_t TC4_:1; /*!< bit: 2 TC4 APB Clock Enable */ - uint32_t ADC_:1; /*!< bit: 3 ADC APB Clock Enable */ - uint32_t AC_:1; /*!< bit: 4 AC APB Clock Enable */ - uint32_t PTC_:1; /*!< bit: 5 PTC APB Clock Enable */ - uint32_t OPAMP_:1; /*!< bit: 6 OPAMP APB Clock Enable */ - uint32_t CCL_:1; /*!< bit: 7 CCL APB Clock Enable */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MCLK_APBDMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */ -#define MCLK_APBDMASK_RESETVALUE 0x000000FFul /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */ - -#define MCLK_APBDMASK_EVSYS_Pos 0 /**< \brief (MCLK_APBDMASK) EVSYS APB Clock Enable */ -#define MCLK_APBDMASK_EVSYS (0x1ul << MCLK_APBDMASK_EVSYS_Pos) -#define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */ -#define MCLK_APBDMASK_SERCOM5 (0x1ul << MCLK_APBDMASK_SERCOM5_Pos) -#define MCLK_APBDMASK_TC4_Pos 2 /**< \brief (MCLK_APBDMASK) TC4 APB Clock Enable */ -#define MCLK_APBDMASK_TC4 (0x1ul << MCLK_APBDMASK_TC4_Pos) -#define MCLK_APBDMASK_ADC_Pos 3 /**< \brief (MCLK_APBDMASK) ADC APB Clock Enable */ -#define MCLK_APBDMASK_ADC (0x1ul << MCLK_APBDMASK_ADC_Pos) -#define MCLK_APBDMASK_AC_Pos 4 /**< \brief (MCLK_APBDMASK) AC APB Clock Enable */ -#define MCLK_APBDMASK_AC (0x1ul << MCLK_APBDMASK_AC_Pos) -#define MCLK_APBDMASK_PTC_Pos 5 /**< \brief (MCLK_APBDMASK) PTC APB Clock Enable */ -#define MCLK_APBDMASK_PTC (0x1ul << MCLK_APBDMASK_PTC_Pos) -#define MCLK_APBDMASK_OPAMP_Pos 6 /**< \brief (MCLK_APBDMASK) OPAMP APB Clock Enable */ -#define MCLK_APBDMASK_OPAMP (0x1ul << MCLK_APBDMASK_OPAMP_Pos) -#define MCLK_APBDMASK_CCL_Pos 7 /**< \brief (MCLK_APBDMASK) CCL APB Clock Enable */ -#define MCLK_APBDMASK_CCL (0x1ul << MCLK_APBDMASK_CCL_Pos) -#define MCLK_APBDMASK_MASK 0x000000FFul /**< \brief (MCLK_APBDMASK) MASK Register */ - -/* -------- MCLK_APBEMASK : (MCLK Offset: 0x24) (R/W 32) APBE Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MCLK_APBEMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MCLK_APBEMASK_OFFSET 0x24 /**< \brief (MCLK_APBEMASK offset) APBE Mask */ -#define MCLK_APBEMASK_RESETVALUE 0x0000000Dul /**< \brief (MCLK_APBEMASK reset_value) APBE Mask */ - -#define MCLK_APBEMASK_PAC_Pos 0 /**< \brief (MCLK_APBEMASK) PAC APB Clock Enable */ -#define MCLK_APBEMASK_PAC (0x1ul << MCLK_APBEMASK_PAC_Pos) -#define MCLK_APBEMASK_MASK 0x00000001ul /**< \brief (MCLK_APBEMASK) MASK Register */ - -/** \brief MCLK hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO MCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */ - __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */ - __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */ - __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x04 (R/W 8) CPU Clock Division */ - __IO MCLK_LPDIV_Type LPDIV; /**< \brief Offset: 0x05 (R/W 8) Low-Power Clock Division */ - __IO MCLK_BUPDIV_Type BUPDIV; /**< \brief Offset: 0x06 (R/W 8) Backup Clock Division */ - RoReg8 Reserved1[0x9]; - __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */ - __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */ - __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */ - __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */ - __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */ - __IO MCLK_APBEMASK_Type APBEMASK; /**< \brief Offset: 0x24 (R/W 32) APBE Mask */ -} Mclk; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_MCLK_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mtb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mtb.h deleted file mode 100644 index 28fc408e776..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mtb.h +++ /dev/null @@ -1,399 +0,0 @@ -/** - * \file - * - * \brief Component description for MTB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_MTB_COMPONENT_ -#define _SAML21_MTB_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR MTB */ -/* ========================================================================== */ -/** \addtogroup SAML21_MTB Cortex-M0+ Micro-Trace Buffer */ -/*@{*/ - -#define MTB_U2002 -#define REV_MTB 0x100 - -/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ - uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_POSITION_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */ - -#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */ -#define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos) -#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */ -#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos) -#define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))) -#define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */ - -/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ - uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ - uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ - uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ - uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ - uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ - uint32_t :21; /*!< bit: 10..30 Reserved */ - uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_MASTER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */ -#define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */ - -#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */ -#define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos) -#define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))) -#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */ -#define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos) -#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */ -#define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos) -#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */ -#define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos) -#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */ -#define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos) -#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */ -#define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos) -#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */ -#define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos) -#define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */ - -/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ - uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_FLOW_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */ -#define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */ - -#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */ -#define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos) -#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */ -#define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos) -#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */ -#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos) -#define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))) -#define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */ - -/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_BASE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */ -#define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */ - -/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_ITCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */ -#define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */ - -/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CLAIMSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */ -#define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */ - -/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CLAIMCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */ -#define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */ - -/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_LOCKACCESS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */ -#define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */ - -/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_LOCKSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */ -#define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */ - -/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_AUTHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */ -#define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */ - -/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVARCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */ -#define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */ - -/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */ -#define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */ - -/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVTYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */ -#define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */ - -/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) Peripheral Identification 4 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID4_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) Peripheral Identification 4 */ -#define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */ - -/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) Peripheral Identification 5 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID5_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) Peripheral Identification 5 */ -#define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */ - -/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) Peripheral Identification 6 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID6_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) Peripheral Identification 6 */ -#define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */ - -/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) Peripheral Identification 7 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID7_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) Peripheral Identification 7 */ -#define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */ - -/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) Peripheral Identification 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) Peripheral Identification 0 */ -#define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */ - -/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) Peripheral Identification 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) Peripheral Identification 1 */ -#define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */ - -/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) Peripheral Identification 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) Peripheral Identification 2 */ -#define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */ - -/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) Peripheral Identification 3 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) Peripheral Identification 3 */ -#define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */ - -/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) Component Identification 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) Component Identification 0 */ -#define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */ - -/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) Component Identification 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) Component Identification 1 */ -#define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */ - -/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) Component Identification 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) Component Identification 2 */ -#define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */ - -/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) Component Identification 3 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) Component Identification 3 */ -#define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */ - -/** \brief MTB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ - __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ - __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ - __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ - RoReg8 Reserved1[0xEF0]; - __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ - RoReg8 Reserved2[0x9C]; - __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ - __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ - RoReg8 Reserved3[0x8]; - __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ - __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ - __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ - __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ - RoReg8 Reserved4[0x8]; - __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ - __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ - __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) Peripheral Identification 4 */ - __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) Peripheral Identification 5 */ - __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) Peripheral Identification 6 */ - __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) Peripheral Identification 7 */ - __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) Peripheral Identification 0 */ - __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) Peripheral Identification 1 */ - __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) Peripheral Identification 2 */ - __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) Peripheral Identification 3 */ - __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) Component Identification 0 */ - __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) Component Identification 1 */ - __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) Component Identification 2 */ - __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) Component Identification 3 */ -} Mtb; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_MTB_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_nvmctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_nvmctrl.h deleted file mode 100644 index a37a2f1fd86..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_nvmctrl.h +++ /dev/null @@ -1,582 +0,0 @@ -/** - * \file - * - * \brief Component description for NVMCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_NVMCTRL_COMPONENT_ -#define _SAML21_NVMCTRL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR NVMCTRL */ -/* ========================================================================== */ -/** \addtogroup SAML21_NVMCTRL Non-Volatile Memory Controller */ -/*@{*/ - -#define NVMCTRL_U2207 -#define REV_NVMCTRL 0x302 - -/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CMD:7; /*!< bit: 0.. 6 Command */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ -#define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ - -#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */ -#define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))) -#define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ -#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ -#define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */ -#define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */ -#define NVMCTRL_CTRLA_CMD_RWWEEER_Val 0x1Aul /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_RWWEEWP_Val 0x1Cul /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */ -#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */ -#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */ -#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */ -#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */ -#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_RWWEEER (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_RWWEEWP (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */ -#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos) -#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))) -#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */ -#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos) -#define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */ - -/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t MANW:1; /*!< bit: 7 Manual Write */ - uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ - uint32_t :1; /*!< bit: 10 Reserved */ - uint32_t FWUP:1; /*!< bit: 11 fast wake-up */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ - uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ -#define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ - -#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */ -#define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))) -#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */ -#define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */ -#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))) -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */ -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */ -#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */ -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_FWUP_Pos 11 /**< \brief (NVMCTRL_CTRLB) fast wake-up */ -#define NVMCTRL_CTRLB_FWUP (0x1ul << NVMCTRL_CTRLB_FWUP_Pos) -#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */ -#define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))) -#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */ -#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */ -#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */ -#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */ -#define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos) -#define NVMCTRL_CTRLB_MASK 0x00070B9Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */ - -/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ - uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_PARAM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ -#define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ - -#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ -#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos) -#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))) -#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ -#define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))) -#define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */ -#define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */ -#define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */ -#define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */ -#define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */ -#define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */ -#define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */ -#define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */ -#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_RWWEEP_Pos 20 /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */ -#define NVMCTRL_PARAM_RWWEEP_Msk (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos) -#define NVMCTRL_PARAM_RWWEEP(value) ((NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))) -#define NVMCTRL_PARAM_MASK 0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */ - -/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ -#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ - -#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */ -#define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos) -#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */ -#define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos) -#define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */ - -/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ -#define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ - -#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */ -#define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos) -#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */ -#define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos) -#define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */ - -/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready */ - uint8_t ERROR:1; /*!< bit: 1 Error */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ -#define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */ -#define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos) -#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */ -#define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos) -#define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */ - -/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ - uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ - uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ - uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ - uint16_t NVME:1; /*!< bit: 4 NVM Error */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t SB:1; /*!< bit: 8 Security Bit Status */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */ -#define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */ - -#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ -#define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos) -#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ -#define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos) -#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */ -#define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos) -#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */ -#define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos) -#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */ -#define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos) -#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */ -#define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos) -#define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */ - -/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */ -#define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */ - -#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ -#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos) -#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))) -#define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */ - -/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_LOCK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */ - -#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */ -#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos) -#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))) -#define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */ - -/** \brief NVMCTRL APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - RoReg8 Reserved1[0x2]; - __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ - __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ - __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - RoReg8 Reserved2[0x3]; - __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ - RoReg8 Reserved3[0x3]; - __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x3]; - __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ - RoReg8 Reserved5[0x2]; - __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ - __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ -} Nvmctrl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_CAL __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_CAL @".flash" -#endif - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_LOCKBIT __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_LOCKBIT @".flash" -#endif - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_OTP1 __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_OTP1 @".flash" -#endif - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_OTP2 __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_OTP2 @".flash" -#endif - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_OTP3 __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_OTP3 @".flash" -#endif - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_OTP4 __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_OTP4 @".flash" -#endif - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_OTP5 __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_OTP5 @".flash" -#endif - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_TEMP_LOG __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_TEMP_LOG @".flash" -#endif - -#ifdef __GNUC__ -#define SECTION_NVMCTRL_USER __attribute__ ((section(".flash"))) -#elif defined(__ICCARM__) -#define SECTION_NVMCTRL_USER @".flash" -#endif - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ -/* ************************************************************************** */ -/** \addtogroup fuses_api Peripheral Software API */ -/*@{*/ - - -#define ADC_FUSES_BIASCOMP_ADDR NVMCTRL_OTP5 -#define ADC_FUSES_BIASCOMP_Pos 3 /**< \brief (NVMCTRL_OTP5) ADC Comparator Scaling */ -#define ADC_FUSES_BIASCOMP_Msk (0x7ul << ADC_FUSES_BIASCOMP_Pos) -#define ADC_FUSES_BIASCOMP(value) ((ADC_FUSES_BIASCOMP_Msk & ((value) << ADC_FUSES_BIASCOMP_Pos))) - -#define ADC_FUSES_BIASREFBUF_ADDR NVMCTRL_OTP5 -#define ADC_FUSES_BIASREFBUF_Pos 0 /**< \brief (NVMCTRL_OTP5) ADC Bias Reference Buffer Scaling */ -#define ADC_FUSES_BIASREFBUF_Msk (0x7ul << ADC_FUSES_BIASREFBUF_Pos) -#define ADC_FUSES_BIASREFBUF(value) ((ADC_FUSES_BIASREFBUF_Msk & ((value) << ADC_FUSES_BIASREFBUF_Pos))) - -#define FUSES_BOD12_HYST_ADDR (NVMCTRL_USER + 4) -#define FUSES_BOD12_HYST_Pos 10 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */ -#define FUSES_BOD12_HYST_Msk (0x1ul << FUSES_BOD12_HYST_Pos) - -#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER -#define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */ -#define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos) -#define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))) - -#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER -#define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */ -#define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos) -#define FUSES_BOD33_ACTION(value) ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))) - -#define FUSES_BOD33_DIS_ADDR NVMCTRL_USER -#define FUSES_BOD33_DIS_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Disable */ -#define FUSES_BOD33_DIS_Msk (0x1ul << FUSES_BOD33_DIS_Pos) - -#define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4) -#define FUSES_BOD33_HYST_Pos 9 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ -#define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos) - -#define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */ -#define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos) -#define FUSES_HOT_ADC_VAL(value) ((FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))) - -#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ -#define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos) -#define FUSES_HOT_INT1V_VAL(value) ((FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))) - -#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG -#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ -#define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos) -#define FUSES_HOT_TEMP_VAL_DEC(value) ((FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))) - -#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG -#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ -#define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos) -#define FUSES_HOT_TEMP_VAL_INT(value) ((FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))) - -#define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */ -#define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos) -#define FUSES_ROOM_ADC_VAL(value) ((FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))) - -#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ -#define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos) -#define FUSES_ROOM_INT1V_VAL(value) ((FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))) - -#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ -#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos) -#define FUSES_ROOM_TEMP_VAL_DEC(value) ((FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))) - -#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ -#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos) -#define FUSES_ROOM_TEMP_VAL_INT(value) ((FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))) - -#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER -#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */ -#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos) -#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))) - -#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER -#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */ -#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos) -#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))) - -#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */ -#define NVMCTRL_FUSES_NVMP_Msk (0x1FFFul << NVMCTRL_FUSES_NVMP_Pos) -#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos))) - -#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */ -#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos) -#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos))) - -#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */ -#define NVMCTRL_FUSES_PSZ_Msk (0x3ul << NVMCTRL_FUSES_PSZ_Pos) -#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))) - -#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4) -#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */ -#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos) -#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))) - -#define NVMCTRL_FUSES_RWWEEP_ADDR (NVMCTRL_OTP1 + 4) -#define NVMCTRL_FUSES_RWWEEP_Pos 0 /**< \brief (NVMCTRL_OTP1) Number of RWW EEPROM Pages */ -#define NVMCTRL_FUSES_RWWEEP_Msk (0xFFul << NVMCTRL_FUSES_RWWEEP_Pos) -#define NVMCTRL_FUSES_RWWEEP(value) ((NVMCTRL_FUSES_RWWEEP_Msk & ((value) << NVMCTRL_FUSES_RWWEEP_Pos))) - -#define USB_FUSES_TRANSN_ADDR NVMCTRL_OTP5 -#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP5) USB pad Transn calibration */ -#define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos) -#define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))) - -#define USB_FUSES_TRANSP_ADDR NVMCTRL_OTP5 -#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP5) USB pad Transp calibration */ -#define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos) -#define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))) - -#define USB_FUSES_TRIM_ADDR NVMCTRL_OTP5 -#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP5) USB pad Trim calibration */ -#define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos) -#define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))) - -#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER -#define WDT_FUSES_ALWAYSON_Pos 27 /**< \brief (NVMCTRL_USER) WDT Always On */ -#define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos) - -#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER -#define WDT_FUSES_ENABLE_Pos 26 /**< \brief (NVMCTRL_USER) WDT Enable */ -#define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos) - -#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_EWOFFSET_Pos 4 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ -#define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos) -#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))) - -#define WDT_FUSES_PER_ADDR NVMCTRL_USER -#define WDT_FUSES_PER_Pos 28 /**< \brief (NVMCTRL_USER) WDT Period */ -#define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos) -#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))) - -#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_WEN_Pos 8 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ -#define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos) - -#define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_WINDOW_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window */ -#define WDT_FUSES_WINDOW_Msk (0xFul << WDT_FUSES_WINDOW_Pos) -#define WDT_FUSES_WINDOW(value) ((WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))) - -/*@}*/ - -#endif /* _SAML21_NVMCTRL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_opamp.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_opamp.h deleted file mode 100644 index 974eb52f937..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_opamp.h +++ /dev/null @@ -1,186 +0,0 @@ -/** - * \file - * - * \brief Component description for OPAMP - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_OPAMP_COMPONENT_ -#define _SAML21_OPAMP_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR OPAMP */ -/* ========================================================================== */ -/** \addtogroup SAML21_OPAMP Operational Amplifier */ -/*@{*/ - -#define OPAMP_U2237 -#define REV_OPAMP 0x100 - -/* -------- OPAMP_CTRLA : (OPAMP Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} OPAMP_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OPAMP_CTRLA_OFFSET 0x00 /**< \brief (OPAMP_CTRLA offset) Control A */ -#define OPAMP_CTRLA_RESETVALUE 0x00ul /**< \brief (OPAMP_CTRLA reset_value) Control A */ - -#define OPAMP_CTRLA_SWRST_Pos 0 /**< \brief (OPAMP_CTRLA) Software Reset */ -#define OPAMP_CTRLA_SWRST (0x1ul << OPAMP_CTRLA_SWRST_Pos) -#define OPAMP_CTRLA_ENABLE_Pos 1 /**< \brief (OPAMP_CTRLA) Enable */ -#define OPAMP_CTRLA_ENABLE (0x1ul << OPAMP_CTRLA_ENABLE_Pos) -#define OPAMP_CTRLA_LPMUX_Pos 7 /**< \brief (OPAMP_CTRLA) Low-Power Mux */ -#define OPAMP_CTRLA_LPMUX (0x1ul << OPAMP_CTRLA_LPMUX_Pos) -#define OPAMP_CTRLA_MASK 0x83ul /**< \brief (OPAMP_CTRLA) MASK Register */ - -/* -------- OPAMP_STATUS : (OPAMP Offset: 0x02) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 OPAMP 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 OPAMP 1 Ready */ - uint8_t READY2:1; /*!< bit: 2 OPAMP 2 Ready */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:3; /*!< bit: 0.. 2 OPAMP x Ready */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} OPAMP_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OPAMP_STATUS_OFFSET 0x02 /**< \brief (OPAMP_STATUS offset) Status */ -#define OPAMP_STATUS_RESETVALUE 0x00ul /**< \brief (OPAMP_STATUS reset_value) Status */ - -#define OPAMP_STATUS_READY0_Pos 0 /**< \brief (OPAMP_STATUS) OPAMP 0 Ready */ -#define OPAMP_STATUS_READY0 (1 << OPAMP_STATUS_READY0_Pos) -#define OPAMP_STATUS_READY1_Pos 1 /**< \brief (OPAMP_STATUS) OPAMP 1 Ready */ -#define OPAMP_STATUS_READY1 (1 << OPAMP_STATUS_READY1_Pos) -#define OPAMP_STATUS_READY2_Pos 2 /**< \brief (OPAMP_STATUS) OPAMP 2 Ready */ -#define OPAMP_STATUS_READY2 (1 << OPAMP_STATUS_READY2_Pos) -#define OPAMP_STATUS_READY_Pos 0 /**< \brief (OPAMP_STATUS) OPAMP x Ready */ -#define OPAMP_STATUS_READY_Msk (0x7ul << OPAMP_STATUS_READY_Pos) -#define OPAMP_STATUS_READY(value) ((OPAMP_STATUS_READY_Msk & ((value) << OPAMP_STATUS_READY_Pos))) -#define OPAMP_STATUS_MASK 0x07ul /**< \brief (OPAMP_STATUS) MASK Register */ - -/* -------- OPAMP_OPAMPCTRL : (OPAMP Offset: 0x04) (R/W 32) OPAMP n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Operational Amplifier Enable */ - uint32_t ANAOUT:1; /*!< bit: 2 Analog Output */ - uint32_t BIAS:2; /*!< bit: 3.. 4 Bias Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t RES2OUT:1; /*!< bit: 8 Resistor ladder To Output */ - uint32_t RES2VCC:1; /*!< bit: 9 Resistor ladder To VCC */ - uint32_t RES1EN:1; /*!< bit: 10 Resistor 1 Enable */ - uint32_t RES1MUX:2; /*!< bit: 11..12 Resistor 1 Mux */ - uint32_t POTMUX:3; /*!< bit: 13..15 Potentiometer Selection */ - uint32_t MUXPOS:3; /*!< bit: 16..18 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 20..22 Negative Input Mux Selection */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OPAMP_OPAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OPAMP_OPAMPCTRL_OFFSET 0x04 /**< \brief (OPAMP_OPAMPCTRL offset) OPAMP n Control */ -#define OPAMP_OPAMPCTRL_RESETVALUE 0x00000000ul /**< \brief (OPAMP_OPAMPCTRL reset_value) OPAMP n Control */ - -#define OPAMP_OPAMPCTRL_ENABLE_Pos 1 /**< \brief (OPAMP_OPAMPCTRL) Operational Amplifier Enable */ -#define OPAMP_OPAMPCTRL_ENABLE (0x1ul << OPAMP_OPAMPCTRL_ENABLE_Pos) -#define OPAMP_OPAMPCTRL_ANAOUT_Pos 2 /**< \brief (OPAMP_OPAMPCTRL) Analog Output */ -#define OPAMP_OPAMPCTRL_ANAOUT (0x1ul << OPAMP_OPAMPCTRL_ANAOUT_Pos) -#define OPAMP_OPAMPCTRL_BIAS_Pos 3 /**< \brief (OPAMP_OPAMPCTRL) Bias Selection */ -#define OPAMP_OPAMPCTRL_BIAS_Msk (0x3ul << OPAMP_OPAMPCTRL_BIAS_Pos) -#define OPAMP_OPAMPCTRL_BIAS(value) ((OPAMP_OPAMPCTRL_BIAS_Msk & ((value) << OPAMP_OPAMPCTRL_BIAS_Pos))) -#define OPAMP_OPAMPCTRL_RUNSTDBY_Pos 6 /**< \brief (OPAMP_OPAMPCTRL) Run in Standby */ -#define OPAMP_OPAMPCTRL_RUNSTDBY (0x1ul << OPAMP_OPAMPCTRL_RUNSTDBY_Pos) -#define OPAMP_OPAMPCTRL_ONDEMAND_Pos 7 /**< \brief (OPAMP_OPAMPCTRL) On Demand Control */ -#define OPAMP_OPAMPCTRL_ONDEMAND (0x1ul << OPAMP_OPAMPCTRL_ONDEMAND_Pos) -#define OPAMP_OPAMPCTRL_RES2OUT_Pos 8 /**< \brief (OPAMP_OPAMPCTRL) Resistor ladder To Output */ -#define OPAMP_OPAMPCTRL_RES2OUT (0x1ul << OPAMP_OPAMPCTRL_RES2OUT_Pos) -#define OPAMP_OPAMPCTRL_RES2VCC_Pos 9 /**< \brief (OPAMP_OPAMPCTRL) Resistor ladder To VCC */ -#define OPAMP_OPAMPCTRL_RES2VCC (0x1ul << OPAMP_OPAMPCTRL_RES2VCC_Pos) -#define OPAMP_OPAMPCTRL_RES1EN_Pos 10 /**< \brief (OPAMP_OPAMPCTRL) Resistor 1 Enable */ -#define OPAMP_OPAMPCTRL_RES1EN (0x1ul << OPAMP_OPAMPCTRL_RES1EN_Pos) -#define OPAMP_OPAMPCTRL_RES1MUX_Pos 11 /**< \brief (OPAMP_OPAMPCTRL) Resistor 1 Mux */ -#define OPAMP_OPAMPCTRL_RES1MUX_Msk (0x3ul << OPAMP_OPAMPCTRL_RES1MUX_Pos) -#define OPAMP_OPAMPCTRL_RES1MUX(value) ((OPAMP_OPAMPCTRL_RES1MUX_Msk & ((value) << OPAMP_OPAMPCTRL_RES1MUX_Pos))) -#define OPAMP_OPAMPCTRL_POTMUX_Pos 13 /**< \brief (OPAMP_OPAMPCTRL) Potentiometer Selection */ -#define OPAMP_OPAMPCTRL_POTMUX_Msk (0x7ul << OPAMP_OPAMPCTRL_POTMUX_Pos) -#define OPAMP_OPAMPCTRL_POTMUX(value) ((OPAMP_OPAMPCTRL_POTMUX_Msk & ((value) << OPAMP_OPAMPCTRL_POTMUX_Pos))) -#define OPAMP_OPAMPCTRL_MUXPOS_Pos 16 /**< \brief (OPAMP_OPAMPCTRL) Positive Input Mux Selection */ -#define OPAMP_OPAMPCTRL_MUXPOS_Msk (0x7ul << OPAMP_OPAMPCTRL_MUXPOS_Pos) -#define OPAMP_OPAMPCTRL_MUXPOS(value) ((OPAMP_OPAMPCTRL_MUXPOS_Msk & ((value) << OPAMP_OPAMPCTRL_MUXPOS_Pos))) -#define OPAMP_OPAMPCTRL_MUXNEG_Pos 20 /**< \brief (OPAMP_OPAMPCTRL) Negative Input Mux Selection */ -#define OPAMP_OPAMPCTRL_MUXNEG_Msk (0x7ul << OPAMP_OPAMPCTRL_MUXNEG_Pos) -#define OPAMP_OPAMPCTRL_MUXNEG(value) ((OPAMP_OPAMPCTRL_MUXNEG_Msk & ((value) << OPAMP_OPAMPCTRL_MUXNEG_Pos))) -#define OPAMP_OPAMPCTRL_MASK 0x0077FFDEul /**< \brief (OPAMP_OPAMPCTRL) MASK Register */ - -/** \brief OPAMP hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO OPAMP_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I OPAMP_STATUS_Type STATUS; /**< \brief Offset: 0x02 (R/ 8) Status */ - RoReg8 Reserved2[0x1]; - __IO OPAMP_OPAMPCTRL_Type OPAMPCTRL[3]; /**< \brief Offset: 0x04 (R/W 32) OPAMP n Control */ -} Opamp; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_OPAMP_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_osc32kctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_osc32kctrl.h deleted file mode 100644 index 7d3a1afb675..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_osc32kctrl.h +++ /dev/null @@ -1,301 +0,0 @@ -/** - * \file - * - * \brief Component description for OSC32KCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_OSC32KCTRL_COMPONENT_ -#define _SAML21_OSC32KCTRL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR OSC32KCTRL */ -/* ========================================================================== */ -/** \addtogroup SAML21_OSC32KCTRL 32k Oscillators Control */ -/*@{*/ - -#define OSC32KCTRL_U2246 -#define REV_OSC32KCTRL 0x110 - -/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSC32KCTRL_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */ -#define OSC32KCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */ - -#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ -#define OSC32KCTRL_INTENCLR_XOSC32KRDY (0x1ul << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) -#define OSC32KCTRL_INTENCLR_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ -#define OSC32KCTRL_INTENCLR_OSC32KRDY (0x1ul << OSC32KCTRL_INTENCLR_OSC32KRDY_Pos) -#define OSC32KCTRL_INTENCLR_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */ - -/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSC32KCTRL_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */ -#define OSC32KCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */ - -#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ -#define OSC32KCTRL_INTENSET_XOSC32KRDY (0x1ul << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) -#define OSC32KCTRL_INTENSET_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENSET) OSC32K Ready Interrupt Enable */ -#define OSC32KCTRL_INTENSET_OSC32KRDY (0x1ul << OSC32KCTRL_INTENSET_OSC32KRDY_Pos) -#define OSC32KCTRL_INTENSET_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTENSET) MASK Register */ - -/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSC32KCTRL_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ -#define OSC32KCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */ -#define OSC32KCTRL_INTFLAG_XOSC32KRDY (0x1ul << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) -#define OSC32KCTRL_INTFLAG_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTFLAG) OSC32K Ready */ -#define OSC32KCTRL_INTFLAG_OSC32KRDY (0x1ul << OSC32KCTRL_INTFLAG_OSC32KRDY_Pos) -#define OSC32KCTRL_INTFLAG_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */ - -/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSC32KCTRL_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */ -#define OSC32KCTRL_STATUS_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */ - -#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */ -#define OSC32KCTRL_STATUS_XOSC32KRDY (0x1ul << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) -#define OSC32KCTRL_STATUS_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_STATUS) OSC32K Ready */ -#define OSC32KCTRL_STATUS_OSC32KRDY (0x1ul << OSC32KCTRL_STATUS_OSC32KRDY_Pos) -#define OSC32KCTRL_STATUS_MASK 0x00000003ul /**< \brief (OSC32KCTRL_STATUS) MASK Register */ - -/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock selection -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSC32KCTRL_RTCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) Clock selection */ -#define OSC32KCTRL_RTCCTRL_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_RTCCTRL reset_value) Clock selection */ - -#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */ -#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (0x7ul << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) -#define OSC32KCTRL_RTCCTRL_RTCSEL(value) ((OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))) -#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val 0x0ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */ -#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val 0x1ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */ -#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val 0x2ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ -#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val 0x3ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator */ -#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val 0x4ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ -#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val 0x5ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */ -#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) -#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) -#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) -#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) -#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) -#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) -#define OSC32KCTRL_RTCCTRL_MASK 0x00000007ul /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */ - -/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint32_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ - uint32_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint32_t :19; /*!< bit: 13..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSC32KCTRL_XOSC32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define OSC32KCTRL_XOSC32K_RESETVALUE 0x00000080ul /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ - -#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */ -#define OSC32KCTRL_XOSC32K_ENABLE (0x1ul << OSC32KCTRL_XOSC32K_ENABLE_Pos) -#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */ -#define OSC32KCTRL_XOSC32K_XTALEN (0x1ul << OSC32KCTRL_XOSC32K_XTALEN_Pos) -#define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */ -#define OSC32KCTRL_XOSC32K_EN32K (0x1ul << OSC32KCTRL_XOSC32K_EN32K_Pos) -#define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */ -#define OSC32KCTRL_XOSC32K_EN1K (0x1ul << OSC32KCTRL_XOSC32K_EN1K_Pos) -#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */ -#define OSC32KCTRL_XOSC32K_RUNSTDBY (0x1ul << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) -#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */ -#define OSC32KCTRL_XOSC32K_ONDEMAND (0x1ul << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) -#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */ -#define OSC32KCTRL_XOSC32K_STARTUP_Msk (0x7ul << OSC32KCTRL_XOSC32K_STARTUP_Pos) -#define OSC32KCTRL_XOSC32K_STARTUP(value) ((OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))) -#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */ -#define OSC32KCTRL_XOSC32K_WRTLOCK (0x1ul << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) -#define OSC32KCTRL_XOSC32K_MASK 0x000017DEul /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */ - -/* -------- OSC32KCTRL_OSC32K : (OSC32KCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ - uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ - uint32_t :2; /*!< bit: 4.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSC32KCTRL_OSC32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSC32KCTRL_OSC32K_OFFSET 0x18 /**< \brief (OSC32KCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ -#define OSC32KCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (OSC32KCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ - -#define OSC32KCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Enable */ -#define OSC32KCTRL_OSC32K_ENABLE (0x1ul << OSC32KCTRL_OSC32K_ENABLE_Pos) -#define OSC32KCTRL_OSC32K_EN32K_Pos 2 /**< \brief (OSC32KCTRL_OSC32K) 32kHz Output Enable */ -#define OSC32KCTRL_OSC32K_EN32K (0x1ul << OSC32KCTRL_OSC32K_EN32K_Pos) -#define OSC32KCTRL_OSC32K_EN1K_Pos 3 /**< \brief (OSC32KCTRL_OSC32K) 1kHz Output Enable */ -#define OSC32KCTRL_OSC32K_EN1K (0x1ul << OSC32KCTRL_OSC32K_EN1K_Pos) -#define OSC32KCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_OSC32K) Run in Standby */ -#define OSC32KCTRL_OSC32K_RUNSTDBY (0x1ul << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) -#define OSC32KCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_OSC32K) On Demand Control */ -#define OSC32KCTRL_OSC32K_ONDEMAND (0x1ul << OSC32KCTRL_OSC32K_ONDEMAND_Pos) -#define OSC32KCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Start-Up Time */ -#define OSC32KCTRL_OSC32K_STARTUP_Msk (0x7ul << OSC32KCTRL_OSC32K_STARTUP_Pos) -#define OSC32KCTRL_OSC32K_STARTUP(value) ((OSC32KCTRL_OSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_OSC32K_STARTUP_Pos))) -#define OSC32KCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_OSC32K) Write Lock */ -#define OSC32KCTRL_OSC32K_WRTLOCK (0x1ul << OSC32KCTRL_OSC32K_WRTLOCK_Pos) -#define OSC32KCTRL_OSC32K_CALIB_Pos 16 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Calibration */ -#define OSC32KCTRL_OSC32K_CALIB_Msk (0x7Ful << OSC32KCTRL_OSC32K_CALIB_Pos) -#define OSC32KCTRL_OSC32K_CALIB(value) ((OSC32KCTRL_OSC32K_CALIB_Msk & ((value) << OSC32KCTRL_OSC32K_CALIB_Pos))) -#define OSC32KCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (OSC32KCTRL_OSC32K) MASK Register */ - -/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CALIB:5; /*!< bit: 8..12 Oscillator Calibration */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSC32KCTRL_OSCULP32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ - -#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */ -#define OSC32KCTRL_OSCULP32K_CALIB_Msk (0x1Ful << OSC32KCTRL_OSCULP32K_CALIB_Pos) -#define OSC32KCTRL_OSCULP32K_CALIB(value) ((OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))) -#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */ -#define OSC32KCTRL_OSCULP32K_WRTLOCK (0x1ul << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) -#define OSC32KCTRL_OSCULP32K_MASK 0x00009F00ul /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */ - -/** \brief OSC32KCTRL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ - __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ - __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ - __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ - __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 32) Clock selection */ - __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control */ - __IO OSC32KCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ - __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -} Osc32kctrl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_OSC32KCTRL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_oscctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_oscctrl.h deleted file mode 100644 index 253a3d2cc9d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_oscctrl.h +++ /dev/null @@ -1,652 +0,0 @@ -/** - * \file - * - * \brief Component description for OSCCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_OSCCTRL_COMPONENT_ -#define _SAML21_OSCCTRL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR OSCCTRL */ -/* ========================================================================== */ -/** \addtogroup SAML21_OSCCTRL Oscillators Control */ -/*@{*/ - -#define OSCCTRL_U2119 -#define REV_OSCCTRL 0x100 - -/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 1.. 3 Reserved */ - uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Time Out Interrupt Enable */ - uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSCCTRL_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */ -#define OSCCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */ - -#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable */ -#define OSCCTRL_INTENCLR_XOSCRDY (0x1ul << OSCCTRL_INTENCLR_XOSCRDY_Pos) -#define OSCCTRL_INTENCLR_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTENCLR) OSC16M Ready Interrupt Enable */ -#define OSCCTRL_INTENCLR_OSC16MRDY (0x1ul << OSCCTRL_INTENCLR_OSC16MRDY_Pos) -#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */ -#define OSCCTRL_INTENCLR_DFLLRDY (0x1ul << OSCCTRL_INTENCLR_DFLLRDY_Pos) -#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ -#define OSCCTRL_INTENCLR_DFLLOOB (0x1ul << OSCCTRL_INTENCLR_DFLLOOB_Pos) -#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ -#define OSCCTRL_INTENCLR_DFLLLCKF (0x1ul << OSCCTRL_INTENCLR_DFLLLCKF_Pos) -#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ -#define OSCCTRL_INTENCLR_DFLLLCKC (0x1ul << OSCCTRL_INTENCLR_DFLLLCKC_Pos) -#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ -#define OSCCTRL_INTENCLR_DFLLRCS (0x1ul << OSCCTRL_INTENCLR_DFLLRCS_Pos) -#define OSCCTRL_INTENCLR_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ -#define OSCCTRL_INTENCLR_DPLLLCKR (0x1ul << OSCCTRL_INTENCLR_DPLLLCKR_Pos) -#define OSCCTRL_INTENCLR_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ -#define OSCCTRL_INTENCLR_DPLLLCKF (0x1ul << OSCCTRL_INTENCLR_DPLLLCKF_Pos) -#define OSCCTRL_INTENCLR_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL Time Out Interrupt Enable */ -#define OSCCTRL_INTENCLR_DPLLLTO (0x1ul << OSCCTRL_INTENCLR_DPLLLTO_Pos) -#define OSCCTRL_INTENCLR_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL Ratio Ready Interrupt Enable */ -#define OSCCTRL_INTENCLR_DPLLLDRTO (0x1ul << OSCCTRL_INTENCLR_DPLLLDRTO_Pos) -#define OSCCTRL_INTENCLR_MASK 0x000F1F11ul /**< \brief (OSCCTRL_INTENCLR) MASK Register */ - -/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 1.. 3 Reserved */ - uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Time Out Interrupt Enable */ - uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSCCTRL_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */ -#define OSCCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */ - -#define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable */ -#define OSCCTRL_INTENSET_XOSCRDY (0x1ul << OSCCTRL_INTENSET_XOSCRDY_Pos) -#define OSCCTRL_INTENSET_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTENSET) OSC16M Ready Interrupt Enable */ -#define OSCCTRL_INTENSET_OSC16MRDY (0x1ul << OSCCTRL_INTENSET_OSC16MRDY_Pos) -#define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */ -#define OSCCTRL_INTENSET_DFLLRDY (0x1ul << OSCCTRL_INTENSET_DFLLRDY_Pos) -#define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ -#define OSCCTRL_INTENSET_DFLLOOB (0x1ul << OSCCTRL_INTENSET_DFLLOOB_Pos) -#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ -#define OSCCTRL_INTENSET_DFLLLCKF (0x1ul << OSCCTRL_INTENSET_DFLLLCKF_Pos) -#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ -#define OSCCTRL_INTENSET_DFLLLCKC (0x1ul << OSCCTRL_INTENSET_DFLLLCKC_Pos) -#define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ -#define OSCCTRL_INTENSET_DFLLRCS (0x1ul << OSCCTRL_INTENSET_DFLLRCS_Pos) -#define OSCCTRL_INTENSET_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ -#define OSCCTRL_INTENSET_DPLLLCKR (0x1ul << OSCCTRL_INTENSET_DPLLLCKR_Pos) -#define OSCCTRL_INTENSET_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ -#define OSCCTRL_INTENSET_DPLLLCKF (0x1ul << OSCCTRL_INTENSET_DPLLLCKF_Pos) -#define OSCCTRL_INTENSET_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL Time Out Interrupt Enable */ -#define OSCCTRL_INTENSET_DPLLLTO (0x1ul << OSCCTRL_INTENSET_DPLLLTO_Pos) -#define OSCCTRL_INTENSET_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL Ratio Ready Interrupt Enable */ -#define OSCCTRL_INTENSET_DPLLLDRTO (0x1ul << OSCCTRL_INTENSET_DPLLLDRTO_Pos) -#define OSCCTRL_INTENSET_MASK 0x000F1F11ul /**< \brief (OSCCTRL_INTENSET) MASK Register */ - -/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t :3; /*!< bit: 1.. 3 Reserved */ - uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Timeout */ - uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSCCTRL_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ -#define OSCCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC Ready */ -#define OSCCTRL_INTFLAG_XOSCRDY (0x1ul << OSCCTRL_INTFLAG_XOSCRDY_Pos) -#define OSCCTRL_INTFLAG_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTFLAG) OSC16M Ready */ -#define OSCCTRL_INTFLAG_OSC16MRDY (0x1ul << OSCCTRL_INTFLAG_OSC16MRDY_Pos) -#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */ -#define OSCCTRL_INTFLAG_DFLLRDY (0x1ul << OSCCTRL_INTFLAG_DFLLRDY_Pos) -#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */ -#define OSCCTRL_INTFLAG_DFLLOOB (0x1ul << OSCCTRL_INTFLAG_DFLLOOB_Pos) -#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */ -#define OSCCTRL_INTFLAG_DFLLLCKF (0x1ul << OSCCTRL_INTFLAG_DFLLLCKF_Pos) -#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */ -#define OSCCTRL_INTFLAG_DFLLLCKC (0x1ul << OSCCTRL_INTFLAG_DFLLLCKC_Pos) -#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */ -#define OSCCTRL_INTFLAG_DFLLRCS (0x1ul << OSCCTRL_INTFLAG_DFLLRCS_Pos) -#define OSCCTRL_INTFLAG_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Rise */ -#define OSCCTRL_INTFLAG_DPLLLCKR (0x1ul << OSCCTRL_INTFLAG_DPLLLCKR_Pos) -#define OSCCTRL_INTFLAG_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Fall */ -#define OSCCTRL_INTFLAG_DPLLLCKF (0x1ul << OSCCTRL_INTFLAG_DPLLLCKF_Pos) -#define OSCCTRL_INTFLAG_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL Timeout */ -#define OSCCTRL_INTFLAG_DPLLLTO (0x1ul << OSCCTRL_INTFLAG_DPLLLTO_Pos) -#define OSCCTRL_INTFLAG_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL Ratio Ready */ -#define OSCCTRL_INTFLAG_DPLLLDRTO (0x1ul << OSCCTRL_INTFLAG_DPLLLDRTO_Pos) -#define OSCCTRL_INTFLAG_MASK 0x000F1F11ul /**< \brief (OSCCTRL_INTFLAG) MASK Register */ - -/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t :3; /*!< bit: 1.. 3 Reserved */ - uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall */ - uint32_t DPLLTO:1; /*!< bit: 18 DPLL Timeout */ - uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSCCTRL_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_STATUS_OFFSET 0x0C /**< \brief (OSCCTRL_STATUS offset) Power and Clocks Status */ -#define OSCCTRL_STATUS_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_STATUS reset_value) Power and Clocks Status */ - -#define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC Ready */ -#define OSCCTRL_STATUS_XOSCRDY (0x1ul << OSCCTRL_STATUS_XOSCRDY_Pos) -#define OSCCTRL_STATUS_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_STATUS) OSC16M Ready */ -#define OSCCTRL_STATUS_OSC16MRDY (0x1ul << OSCCTRL_STATUS_OSC16MRDY_Pos) -#define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */ -#define OSCCTRL_STATUS_DFLLRDY (0x1ul << OSCCTRL_STATUS_DFLLRDY_Pos) -#define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */ -#define OSCCTRL_STATUS_DFLLOOB (0x1ul << OSCCTRL_STATUS_DFLLOOB_Pos) -#define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */ -#define OSCCTRL_STATUS_DFLLLCKF (0x1ul << OSCCTRL_STATUS_DFLLLCKF_Pos) -#define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */ -#define OSCCTRL_STATUS_DFLLLCKC (0x1ul << OSCCTRL_STATUS_DFLLLCKC_Pos) -#define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */ -#define OSCCTRL_STATUS_DFLLRCS (0x1ul << OSCCTRL_STATUS_DFLLRCS_Pos) -#define OSCCTRL_STATUS_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL Lock Rise */ -#define OSCCTRL_STATUS_DPLLLCKR (0x1ul << OSCCTRL_STATUS_DPLLLCKR_Pos) -#define OSCCTRL_STATUS_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL Lock Fall */ -#define OSCCTRL_STATUS_DPLLLCKF (0x1ul << OSCCTRL_STATUS_DPLLLCKF_Pos) -#define OSCCTRL_STATUS_DPLLTO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL Timeout */ -#define OSCCTRL_STATUS_DPLLTO (0x1ul << OSCCTRL_STATUS_DPLLTO_Pos) -#define OSCCTRL_STATUS_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL Ratio Ready */ -#define OSCCTRL_STATUS_DPLLLDRTO (0x1ul << OSCCTRL_STATUS_DPLLLDRTO_Pos) -#define OSCCTRL_STATUS_MASK 0x000F1F11ul /**< \brief (OSCCTRL_STATUS) MASK Register */ - -/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t :3; /*!< bit: 3.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ - uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ - uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} OSCCTRL_XOSCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_XOSCCTRL_OFFSET 0x10 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define OSCCTRL_XOSCCTRL_RESETVALUE 0x0080ul /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ - -#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */ -#define OSCCTRL_XOSCCTRL_ENABLE (0x1ul << OSCCTRL_XOSCCTRL_ENABLE_Pos) -#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */ -#define OSCCTRL_XOSCCTRL_XTALEN (0x1ul << OSCCTRL_XOSCCTRL_XTALEN_Pos) -#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */ -#define OSCCTRL_XOSCCTRL_RUNSTDBY (0x1ul << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) -#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */ -#define OSCCTRL_XOSCCTRL_ONDEMAND (0x1ul << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) -#define OSCCTRL_XOSCCTRL_GAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Gain */ -#define OSCCTRL_XOSCCTRL_GAIN_Msk (0x7ul << OSCCTRL_XOSCCTRL_GAIN_Pos) -#define OSCCTRL_XOSCCTRL_GAIN(value) ((OSCCTRL_XOSCCTRL_GAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_GAIN_Pos))) -#define OSCCTRL_XOSCCTRL_AMPGC_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Amplitude Gain Control */ -#define OSCCTRL_XOSCCTRL_AMPGC (0x1ul << OSCCTRL_XOSCCTRL_AMPGC_Pos) -#define OSCCTRL_XOSCCTRL_STARTUP_Pos 12 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */ -#define OSCCTRL_XOSCCTRL_STARTUP_Msk (0xFul << OSCCTRL_XOSCCTRL_STARTUP_Pos) -#define OSCCTRL_XOSCCTRL_STARTUP(value) ((OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))) -#define OSCCTRL_XOSCCTRL_MASK 0xFFC6ul /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */ - -/* -------- OSCCTRL_OSC16MCTRL : (OSCCTRL Offset: 0x14) (R/W 8) 16MHz Internal Oscillator (OSC16M) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint8_t FSEL:2; /*!< bit: 2.. 3 Oscillator Frequency Select */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} OSCCTRL_OSC16MCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_OSC16MCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_OSC16MCTRL offset) 16MHz Internal Oscillator (OSC16M) Control */ -#define OSCCTRL_OSC16MCTRL_RESETVALUE 0x82ul /**< \brief (OSCCTRL_OSC16MCTRL reset_value) 16MHz Internal Oscillator (OSC16M) Control */ - -#define OSCCTRL_OSC16MCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Enable */ -#define OSCCTRL_OSC16MCTRL_ENABLE (0x1ul << OSCCTRL_OSC16MCTRL_ENABLE_Pos) -#define OSCCTRL_OSC16MCTRL_FSEL_Pos 2 /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Frequency Select */ -#define OSCCTRL_OSC16MCTRL_FSEL_Msk (0x3ul << OSCCTRL_OSC16MCTRL_FSEL_Pos) -#define OSCCTRL_OSC16MCTRL_FSEL(value) ((OSCCTRL_OSC16MCTRL_FSEL_Msk & ((value) << OSCCTRL_OSC16MCTRL_FSEL_Pos))) -#define OSCCTRL_OSC16MCTRL_FSEL_4_Val 0x0ul /**< \brief (OSCCTRL_OSC16MCTRL) 4MHz */ -#define OSCCTRL_OSC16MCTRL_FSEL_8_Val 0x1ul /**< \brief (OSCCTRL_OSC16MCTRL) 8MHz */ -#define OSCCTRL_OSC16MCTRL_FSEL_12_Val 0x2ul /**< \brief (OSCCTRL_OSC16MCTRL) 12MHz */ -#define OSCCTRL_OSC16MCTRL_FSEL_16_Val 0x3ul /**< \brief (OSCCTRL_OSC16MCTRL) 16MHz */ -#define OSCCTRL_OSC16MCTRL_FSEL_4 (OSCCTRL_OSC16MCTRL_FSEL_4_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) -#define OSCCTRL_OSC16MCTRL_FSEL_8 (OSCCTRL_OSC16MCTRL_FSEL_8_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) -#define OSCCTRL_OSC16MCTRL_FSEL_12 (OSCCTRL_OSC16MCTRL_FSEL_12_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) -#define OSCCTRL_OSC16MCTRL_FSEL_16 (OSCCTRL_OSC16MCTRL_FSEL_16_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) -#define OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_OSC16MCTRL) Run in Standby */ -#define OSCCTRL_OSC16MCTRL_RUNSTDBY (0x1ul << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos) -#define OSCCTRL_OSC16MCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_OSC16MCTRL) On Demand Control */ -#define OSCCTRL_OSC16MCTRL_ONDEMAND (0x1ul << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos) -#define OSCCTRL_OSC16MCTRL_MASK 0xCEul /**< \brief (OSCCTRL_OSC16MCTRL) MASK Register */ - -/* -------- OSCCTRL_DFLLCTRL : (OSCCTRL Offset: 0x18) (R/W 16) DFLL48M Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ - uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ - uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ - uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ - uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ - uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ - uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ - uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} OSCCTRL_DFLLCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DFLLCTRL_OFFSET 0x18 /**< \brief (OSCCTRL_DFLLCTRL offset) DFLL48M Control */ -#define OSCCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (OSCCTRL_DFLLCTRL reset_value) DFLL48M Control */ - -#define OSCCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRL) DFLL Enable */ -#define OSCCTRL_DFLLCTRL_ENABLE (0x1ul << OSCCTRL_DFLLCTRL_ENABLE_Pos) -#define OSCCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (OSCCTRL_DFLLCTRL) Operating Mode Selection */ -#define OSCCTRL_DFLLCTRL_MODE (0x1ul << OSCCTRL_DFLLCTRL_MODE_Pos) -#define OSCCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (OSCCTRL_DFLLCTRL) Stable DFLL Frequency */ -#define OSCCTRL_DFLLCTRL_STABLE (0x1ul << OSCCTRL_DFLLCTRL_STABLE_Pos) -#define OSCCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (OSCCTRL_DFLLCTRL) Lose Lock After Wake */ -#define OSCCTRL_DFLLCTRL_LLAW (0x1ul << OSCCTRL_DFLLCTRL_LLAW_Pos) -#define OSCCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (OSCCTRL_DFLLCTRL) USB Clock Recovery Mode */ -#define OSCCTRL_DFLLCTRL_USBCRM (0x1ul << OSCCTRL_DFLLCTRL_USBCRM_Pos) -#define OSCCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRL) Run in Standby */ -#define OSCCTRL_DFLLCTRL_RUNSTDBY (0x1ul << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) -#define OSCCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRL) On Demand Control */ -#define OSCCTRL_DFLLCTRL_ONDEMAND (0x1ul << OSCCTRL_DFLLCTRL_ONDEMAND_Pos) -#define OSCCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (OSCCTRL_DFLLCTRL) Chill Cycle Disable */ -#define OSCCTRL_DFLLCTRL_CCDIS (0x1ul << OSCCTRL_DFLLCTRL_CCDIS_Pos) -#define OSCCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (OSCCTRL_DFLLCTRL) Quick Lock Disable */ -#define OSCCTRL_DFLLCTRL_QLDIS (0x1ul << OSCCTRL_DFLLCTRL_QLDIS_Pos) -#define OSCCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (OSCCTRL_DFLLCTRL) Bypass Coarse Lock */ -#define OSCCTRL_DFLLCTRL_BPLCKC (0x1ul << OSCCTRL_DFLLCTRL_BPLCKC_Pos) -#define OSCCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (OSCCTRL_DFLLCTRL) Wait Lock */ -#define OSCCTRL_DFLLCTRL_WAITLOCK (0x1ul << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) -#define OSCCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (OSCCTRL_DFLLCTRL) MASK Register */ - -/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x1C) (R/W 32) DFLL48M Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ - uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ - uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSCCTRL_DFLLVAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DFLLVAL_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */ -#define OSCCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */ - -#define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */ -#define OSCCTRL_DFLLVAL_FINE_Msk (0x3FFul << OSCCTRL_DFLLVAL_FINE_Pos) -#define OSCCTRL_DFLLVAL_FINE(value) ((OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))) -#define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */ -#define OSCCTRL_DFLLVAL_COARSE_Msk (0x3Ful << OSCCTRL_DFLLVAL_COARSE_Pos) -#define OSCCTRL_DFLLVAL_COARSE(value) ((OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))) -#define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */ -#define OSCCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << OSCCTRL_DFLLVAL_DIFF_Pos) -#define OSCCTRL_DFLLVAL_DIFF(value) ((OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))) -#define OSCCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (OSCCTRL_DFLLVAL) MASK Register */ - -/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x20) (R/W 32) DFLL48M Multiplier -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ - uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ - uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSCCTRL_DFLLMUL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DFLLMUL_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */ -#define OSCCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ - -#define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */ -#define OSCCTRL_DFLLMUL_MUL_Msk (0xFFFFul << OSCCTRL_DFLLMUL_MUL_Pos) -#define OSCCTRL_DFLLMUL_MUL(value) ((OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))) -#define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */ -#define OSCCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << OSCCTRL_DFLLMUL_FSTEP_Pos) -#define OSCCTRL_DFLLMUL_FSTEP(value) ((OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))) -#define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */ -#define OSCCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << OSCCTRL_DFLLMUL_CSTEP_Pos) -#define OSCCTRL_DFLLMUL_CSTEP(value) ((OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))) -#define OSCCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (OSCCTRL_DFLLMUL) MASK Register */ - -/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x24) (R/W 8) DFLL48M Synchronization -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t READREQ:1; /*!< bit: 7 Read Request */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} OSCCTRL_DFLLSYNC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DFLLSYNC_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */ -#define OSCCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ - -#define OSCCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (OSCCTRL_DFLLSYNC) Read Request */ -#define OSCCTRL_DFLLSYNC_READREQ (0x1ul << OSCCTRL_DFLLSYNC_READREQ_Pos) -#define OSCCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */ - -/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x28) (R/W 8) DPLL Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} OSCCTRL_DPLLCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DPLLCTRLA_OFFSET 0x28 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control */ -#define OSCCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control */ - -#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) Enable */ -#define OSCCTRL_DPLLCTRLA_ENABLE (0x1ul << OSCCTRL_DPLLCTRLA_ENABLE_Pos) -#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */ -#define OSCCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) -#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand */ -#define OSCCTRL_DPLLCTRLA_ONDEMAND (0x1ul << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) -#define OSCCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */ - -/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x2C) (R/W 32) DPLL Ratio Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSCCTRL_DPLLRATIO_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DPLLRATIO_OFFSET 0x2C /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */ -#define OSCCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ - -#define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */ -#define OSCCTRL_DPLLRATIO_LDR_Msk (0xFFFul << OSCCTRL_DPLLRATIO_LDR_Pos) -#define OSCCTRL_DPLLRATIO_LDR(value) ((OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))) -#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ -#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) -#define OSCCTRL_DPLLRATIO_LDRFRAC(value) ((OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))) -#define OSCCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */ - -/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x30) (R/W 32) Digital Core Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ - uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ - uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ - uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} OSCCTRL_DPLLCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DPLLCTRLB_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLB offset) Digital Core Configuration */ -#define OSCCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_DPLLCTRLB reset_value) Digital Core Configuration */ - -#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ -#define OSCCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << OSCCTRL_DPLLCTRLB_FILTER_Pos) -#define OSCCTRL_DPLLCTRLB_FILTER(value) ((OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))) -#define OSCCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (OSCCTRL_DPLLCTRLB) Low-Power Enable */ -#define OSCCTRL_DPLLCTRLB_LPEN (0x1ul << OSCCTRL_DPLLCTRLB_LPEN_Pos) -#define OSCCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */ -#define OSCCTRL_DPLLCTRLB_WUF (0x1ul << OSCCTRL_DPLLCTRLB_WUF_Pos) -#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */ -#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << OSCCTRL_DPLLCTRLB_REFCLK_Pos) -#define OSCCTRL_DPLLCTRLB_REFCLK(value) ((OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))) -#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */ -#define OSCCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << OSCCTRL_DPLLCTRLB_LTIME_Pos) -#define OSCCTRL_DPLLCTRLB_LTIME(value) ((OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))) -#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */ -#define OSCCTRL_DPLLCTRLB_LBYPASS (0x1ul << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) -#define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */ -#define OSCCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << OSCCTRL_DPLLCTRLB_DIV_Pos) -#define OSCCTRL_DPLLCTRLB_DIV(value) ((OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))) -#define OSCCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */ - -/* -------- OSCCTRL_DPLLPRESC : (OSCCTRL Offset: 0x34) (R/W 8) DPLL Prescaler -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRESC:2; /*!< bit: 0.. 1 Output Clock Prescaler */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} OSCCTRL_DPLLPRESC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DPLLPRESC_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLPRESC offset) DPLL Prescaler */ -#define OSCCTRL_DPLLPRESC_RESETVALUE 0x00ul /**< \brief (OSCCTRL_DPLLPRESC reset_value) DPLL Prescaler */ - -#define OSCCTRL_DPLLPRESC_PRESC_Pos 0 /**< \brief (OSCCTRL_DPLLPRESC) Output Clock Prescaler */ -#define OSCCTRL_DPLLPRESC_PRESC_Msk (0x3ul << OSCCTRL_DPLLPRESC_PRESC_Pos) -#define OSCCTRL_DPLLPRESC_PRESC(value) ((OSCCTRL_DPLLPRESC_PRESC_Msk & ((value) << OSCCTRL_DPLLPRESC_PRESC_Pos))) -#define OSCCTRL_DPLLPRESC_PRESC_DIV1_Val 0x0ul /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 1 */ -#define OSCCTRL_DPLLPRESC_PRESC_DIV2_Val 0x1ul /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 2 */ -#define OSCCTRL_DPLLPRESC_PRESC_DIV4_Val 0x2ul /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 4 */ -#define OSCCTRL_DPLLPRESC_PRESC_DIV1 (OSCCTRL_DPLLPRESC_PRESC_DIV1_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) -#define OSCCTRL_DPLLPRESC_PRESC_DIV2 (OSCCTRL_DPLLPRESC_PRESC_DIV2_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) -#define OSCCTRL_DPLLPRESC_PRESC_DIV4 (OSCCTRL_DPLLPRESC_PRESC_DIV4_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) -#define OSCCTRL_DPLLPRESC_MASK 0x03ul /**< \brief (OSCCTRL_DPLLPRESC) MASK Register */ - -/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x38) (R/ 8) DPLL Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */ - uint8_t DPLLRATIO:1; /*!< bit: 2 DPLL Ratio Synchronization Status */ - uint8_t DPLLPRESC:1; /*!< bit: 3 DPLL Prescaler Synchronization Status */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} OSCCTRL_DPLLSYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */ -#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE 0x00ul /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */ - -#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */ -#define OSCCTRL_DPLLSYNCBUSY_ENABLE (0x1ul << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) -#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Ratio Synchronization Status */ -#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (0x1ul << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) -#define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos 3 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Prescaler Synchronization Status */ -#define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC (0x1ul << OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos) -#define OSCCTRL_DPLLSYNCBUSY_MASK 0x0Eul /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */ - -/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x3C) (R/ 8) DPLL Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ - uint8_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} OSCCTRL_DPLLSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define OSCCTRL_DPLLSTATUS_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */ -#define OSCCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */ - -#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */ -#define OSCCTRL_DPLLSTATUS_LOCK (0x1ul << OSCCTRL_DPLLSTATUS_LOCK_Pos) -#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */ -#define OSCCTRL_DPLLSTATUS_CLKRDY (0x1ul << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) -#define OSCCTRL_DPLLSTATUS_MASK 0x03ul /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */ - -/** \brief OSCCTRL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ - __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ - __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ - __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ - __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ - RoReg8 Reserved1[0x2]; - __IO OSCCTRL_OSC16MCTRL_Type OSC16MCTRL; /**< \brief Offset: 0x14 (R/W 8) 16MHz Internal Oscillator (OSC16M) Control */ - RoReg8 Reserved2[0x3]; - __IO OSCCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x18 (R/W 16) DFLL48M Control */ - RoReg8 Reserved3[0x2]; - __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x1C (R/W 32) DFLL48M Value */ - __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x20 (R/W 32) DFLL48M Multiplier */ - __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x24 (R/W 8) DFLL48M Synchronization */ - RoReg8 Reserved4[0x3]; - __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x28 (R/W 8) DPLL Control */ - RoReg8 Reserved5[0x3]; - __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x2C (R/W 32) DPLL Ratio Control */ - __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x30 (R/W 32) Digital Core Configuration */ - __IO OSCCTRL_DPLLPRESC_Type DPLLPRESC; /**< \brief Offset: 0x34 (R/W 8) DPLL Prescaler */ - RoReg8 Reserved6[0x3]; - __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x38 (R/ 8) DPLL Synchronization Busy */ - RoReg8 Reserved7[0x3]; - __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x3C (R/ 8) DPLL Status */ -} Oscctrl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_OSCCTRL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pac.h deleted file mode 100644 index 221758132c6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pac.h +++ /dev/null @@ -1,627 +0,0 @@ -/** - * \file - * - * \brief Component description for PAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_PAC_COMPONENT_ -#define _SAML21_PAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PAC */ -/* ========================================================================== */ -/** \addtogroup SAML21_PAC Peripheral Access Controller */ -/*@{*/ - -#define PAC_U2120 -#define REV_PAC 0x110 - -/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */ - uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_WRCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */ -#define PAC_WRCTRL_RESETVALUE 0x00000000ul /**< \brief (PAC_WRCTRL reset_value) Write control */ - -#define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */ -#define PAC_WRCTRL_PERID_Msk (0xFFFFul << PAC_WRCTRL_PERID_Pos) -#define PAC_WRCTRL_PERID(value) ((PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))) -#define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */ -#define PAC_WRCTRL_KEY_Msk (0xFFul << PAC_WRCTRL_KEY_Pos) -#define PAC_WRCTRL_KEY(value) ((PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))) -#define PAC_WRCTRL_KEY_OFF_Val 0x0ul /**< \brief (PAC_WRCTRL) No action */ -#define PAC_WRCTRL_KEY_CLR_Val 0x1ul /**< \brief (PAC_WRCTRL) Clear protection */ -#define PAC_WRCTRL_KEY_SET_Val 0x2ul /**< \brief (PAC_WRCTRL) Set protection */ -#define PAC_WRCTRL_KEY_SETLCK_Val 0x3ul /**< \brief (PAC_WRCTRL) Set and lock protection */ -#define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) -#define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) -#define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) -#define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) -#define PAC_WRCTRL_MASK 0x00FFFFFFul /**< \brief (PAC_WRCTRL) MASK Register */ - -/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */ -#define PAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (PAC_EVCTRL reset_value) Event control */ - -#define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */ -#define PAC_EVCTRL_ERREO (0x1ul << PAC_EVCTRL_ERREO_Pos) -#define PAC_EVCTRL_MASK 0x01ul /**< \brief (PAC_EVCTRL) MASK Register */ - -/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */ -#define PAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */ - -#define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */ -#define PAC_INTENCLR_ERR (0x1ul << PAC_INTENCLR_ERR_Pos) -#define PAC_INTENCLR_MASK 0x01ul /**< \brief (PAC_INTENCLR) MASK Register */ - -/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */ -#define PAC_INTENSET_RESETVALUE 0x00ul /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */ - -#define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */ -#define PAC_INTENSET_ERR (0x1ul << PAC_INTENSET_ERR_Pos) -#define PAC_INTENSET_MASK 0x01ul /**< \brief (PAC_INTENSET) MASK Register */ - -/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FLASH_:1; /*!< bit: 0 FLASH */ - uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */ - uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */ - uint32_t HPB1_:1; /*!< bit: 3 HPB1 */ - uint32_t H2LBRIDGES_:1; /*!< bit: 4 H2LBRIDGES */ - uint32_t :11; /*!< bit: 5..15 Reserved */ - uint32_t HPB0_:1; /*!< bit: 16 HPB0 */ - uint32_t HPB2_:1; /*!< bit: 17 HPB2 */ - uint32_t HPB3_:1; /*!< bit: 18 HPB3 */ - uint32_t HPB4_:1; /*!< bit: 19 HPB4 */ - uint32_t PICOPRAM_:1; /*!< bit: 20 PICOPRAM */ - uint32_t LPRAMHS_:1; /*!< bit: 21 LPRAMHS */ - uint32_t LPRAMPICOP_:1; /*!< bit: 22 LPRAMPICOP */ - uint32_t LPRAMDMAC_:1; /*!< bit: 23 LPRAMDMAC */ - uint32_t L2HBRIDGES_:1; /*!< bit: 24 L2HBRIDGES */ - uint32_t HSRAMLP_:1; /*!< bit: 25 HSRAMLP */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_INTFLAGAHB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */ -#define PAC_INTFLAGAHB_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */ - -#define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */ -#define PAC_INTFLAGAHB_FLASH (0x1ul << PAC_INTFLAGAHB_FLASH_Pos) -#define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1 /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */ -#define PAC_INTFLAGAHB_HSRAMCM0P (0x1ul << PAC_INTFLAGAHB_HSRAMCM0P_Pos) -#define PAC_INTFLAGAHB_HSRAMDSU_Pos 2 /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */ -#define PAC_INTFLAGAHB_HSRAMDSU (0x1ul << PAC_INTFLAGAHB_HSRAMDSU_Pos) -#define PAC_INTFLAGAHB_HPB1_Pos 3 /**< \brief (PAC_INTFLAGAHB) HPB1 */ -#define PAC_INTFLAGAHB_HPB1 (0x1ul << PAC_INTFLAGAHB_HPB1_Pos) -#define PAC_INTFLAGAHB_H2LBRIDGES_Pos 4 /**< \brief (PAC_INTFLAGAHB) H2LBRIDGES */ -#define PAC_INTFLAGAHB_H2LBRIDGES (0x1ul << PAC_INTFLAGAHB_H2LBRIDGES_Pos) -#define PAC_INTFLAGAHB_HPB0_Pos 16 /**< \brief (PAC_INTFLAGAHB) HPB0 */ -#define PAC_INTFLAGAHB_HPB0 (0x1ul << PAC_INTFLAGAHB_HPB0_Pos) -#define PAC_INTFLAGAHB_HPB2_Pos 17 /**< \brief (PAC_INTFLAGAHB) HPB2 */ -#define PAC_INTFLAGAHB_HPB2 (0x1ul << PAC_INTFLAGAHB_HPB2_Pos) -#define PAC_INTFLAGAHB_HPB3_Pos 18 /**< \brief (PAC_INTFLAGAHB) HPB3 */ -#define PAC_INTFLAGAHB_HPB3 (0x1ul << PAC_INTFLAGAHB_HPB3_Pos) -#define PAC_INTFLAGAHB_HPB4_Pos 19 /**< \brief (PAC_INTFLAGAHB) HPB4 */ -#define PAC_INTFLAGAHB_HPB4 (0x1ul << PAC_INTFLAGAHB_HPB4_Pos) -#define PAC_INTFLAGAHB_PICOPRAM_Pos 20 /**< \brief (PAC_INTFLAGAHB) PICOPRAM */ -#define PAC_INTFLAGAHB_PICOPRAM (0x1ul << PAC_INTFLAGAHB_PICOPRAM_Pos) -#define PAC_INTFLAGAHB_LPRAMHS_Pos 21 /**< \brief (PAC_INTFLAGAHB) LPRAMHS */ -#define PAC_INTFLAGAHB_LPRAMHS (0x1ul << PAC_INTFLAGAHB_LPRAMHS_Pos) -#define PAC_INTFLAGAHB_LPRAMPICOP_Pos 22 /**< \brief (PAC_INTFLAGAHB) LPRAMPICOP */ -#define PAC_INTFLAGAHB_LPRAMPICOP (0x1ul << PAC_INTFLAGAHB_LPRAMPICOP_Pos) -#define PAC_INTFLAGAHB_LPRAMDMAC_Pos 23 /**< \brief (PAC_INTFLAGAHB) LPRAMDMAC */ -#define PAC_INTFLAGAHB_LPRAMDMAC (0x1ul << PAC_INTFLAGAHB_LPRAMDMAC_Pos) -#define PAC_INTFLAGAHB_L2HBRIDGES_Pos 24 /**< \brief (PAC_INTFLAGAHB) L2HBRIDGES */ -#define PAC_INTFLAGAHB_L2HBRIDGES (0x1ul << PAC_INTFLAGAHB_L2HBRIDGES_Pos) -#define PAC_INTFLAGAHB_HSRAMLP_Pos 25 /**< \brief (PAC_INTFLAGAHB) HSRAMLP */ -#define PAC_INTFLAGAHB_HSRAMLP (0x1ul << PAC_INTFLAGAHB_HSRAMLP_Pos) -#define PAC_INTFLAGAHB_MASK 0x03FF001Ful /**< \brief (PAC_INTFLAGAHB) MASK Register */ - -/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PM_:1; /*!< bit: 0 PM */ - uint32_t MCLK_:1; /*!< bit: 1 MCLK */ - uint32_t RSTC_:1; /*!< bit: 2 RSTC */ - uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL */ - uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL */ - uint32_t SUPC_:1; /*!< bit: 5 SUPC */ - uint32_t GCLK_:1; /*!< bit: 6 GCLK */ - uint32_t WDT_:1; /*!< bit: 7 WDT */ - uint32_t RTC_:1; /*!< bit: 8 RTC */ - uint32_t EIC_:1; /*!< bit: 9 EIC */ - uint32_t PORT_:1; /*!< bit: 10 PORT */ - uint32_t TAL_:1; /*!< bit: 11 TAL */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_INTFLAGA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */ -#define PAC_INTFLAGA_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */ - -#define PAC_INTFLAGA_PM_Pos 0 /**< \brief (PAC_INTFLAGA) PM */ -#define PAC_INTFLAGA_PM (0x1ul << PAC_INTFLAGA_PM_Pos) -#define PAC_INTFLAGA_MCLK_Pos 1 /**< \brief (PAC_INTFLAGA) MCLK */ -#define PAC_INTFLAGA_MCLK (0x1ul << PAC_INTFLAGA_MCLK_Pos) -#define PAC_INTFLAGA_RSTC_Pos 2 /**< \brief (PAC_INTFLAGA) RSTC */ -#define PAC_INTFLAGA_RSTC (0x1ul << PAC_INTFLAGA_RSTC_Pos) -#define PAC_INTFLAGA_OSCCTRL_Pos 3 /**< \brief (PAC_INTFLAGA) OSCCTRL */ -#define PAC_INTFLAGA_OSCCTRL (0x1ul << PAC_INTFLAGA_OSCCTRL_Pos) -#define PAC_INTFLAGA_OSC32KCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */ -#define PAC_INTFLAGA_OSC32KCTRL (0x1ul << PAC_INTFLAGA_OSC32KCTRL_Pos) -#define PAC_INTFLAGA_SUPC_Pos 5 /**< \brief (PAC_INTFLAGA) SUPC */ -#define PAC_INTFLAGA_SUPC (0x1ul << PAC_INTFLAGA_SUPC_Pos) -#define PAC_INTFLAGA_GCLK_Pos 6 /**< \brief (PAC_INTFLAGA) GCLK */ -#define PAC_INTFLAGA_GCLK (0x1ul << PAC_INTFLAGA_GCLK_Pos) -#define PAC_INTFLAGA_WDT_Pos 7 /**< \brief (PAC_INTFLAGA) WDT */ -#define PAC_INTFLAGA_WDT (0x1ul << PAC_INTFLAGA_WDT_Pos) -#define PAC_INTFLAGA_RTC_Pos 8 /**< \brief (PAC_INTFLAGA) RTC */ -#define PAC_INTFLAGA_RTC (0x1ul << PAC_INTFLAGA_RTC_Pos) -#define PAC_INTFLAGA_EIC_Pos 9 /**< \brief (PAC_INTFLAGA) EIC */ -#define PAC_INTFLAGA_EIC (0x1ul << PAC_INTFLAGA_EIC_Pos) -#define PAC_INTFLAGA_PORT_Pos 10 /**< \brief (PAC_INTFLAGA) PORT */ -#define PAC_INTFLAGA_PORT (0x1ul << PAC_INTFLAGA_PORT_Pos) -#define PAC_INTFLAGA_TAL_Pos 11 /**< \brief (PAC_INTFLAGA) TAL */ -#define PAC_INTFLAGA_TAL (0x1ul << PAC_INTFLAGA_TAL_Pos) -#define PAC_INTFLAGA_MASK 0x00000FFFul /**< \brief (PAC_INTFLAGA) MASK Register */ - -/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t USB_:1; /*!< bit: 0 USB */ - uint32_t DSU_:1; /*!< bit: 1 DSU */ - uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */ - uint32_t MTB_:1; /*!< bit: 3 MTB */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_INTFLAGB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */ -#define PAC_INTFLAGB_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */ - -#define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */ -#define PAC_INTFLAGB_USB (0x1ul << PAC_INTFLAGB_USB_Pos) -#define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */ -#define PAC_INTFLAGB_DSU (0x1ul << PAC_INTFLAGB_DSU_Pos) -#define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */ -#define PAC_INTFLAGB_NVMCTRL (0x1ul << PAC_INTFLAGB_NVMCTRL_Pos) -#define PAC_INTFLAGB_MTB_Pos 3 /**< \brief (PAC_INTFLAGB) MTB */ -#define PAC_INTFLAGB_MTB (0x1ul << PAC_INTFLAGB_MTB_Pos) -#define PAC_INTFLAGB_MASK 0x0000000Ful /**< \brief (PAC_INTFLAGB) MASK Register */ - -/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 */ - uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 */ - uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 */ - uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 */ - uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 */ - uint32_t TCC0_:1; /*!< bit: 5 TCC0 */ - uint32_t TCC1_:1; /*!< bit: 6 TCC1 */ - uint32_t TCC2_:1; /*!< bit: 7 TCC2 */ - uint32_t TC0_:1; /*!< bit: 8 TC0 */ - uint32_t TC1_:1; /*!< bit: 9 TC1 */ - uint32_t TC2_:1; /*!< bit: 10 TC2 */ - uint32_t TC3_:1; /*!< bit: 11 TC3 */ - uint32_t DAC_:1; /*!< bit: 12 DAC */ - uint32_t AES_:1; /*!< bit: 13 AES */ - uint32_t TRNG_:1; /*!< bit: 14 TRNG */ - uint32_t :17; /*!< bit: 15..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_INTFLAGC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */ -#define PAC_INTFLAGC_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */ - -#define PAC_INTFLAGC_SERCOM0_Pos 0 /**< \brief (PAC_INTFLAGC) SERCOM0 */ -#define PAC_INTFLAGC_SERCOM0 (0x1ul << PAC_INTFLAGC_SERCOM0_Pos) -#define PAC_INTFLAGC_SERCOM1_Pos 1 /**< \brief (PAC_INTFLAGC) SERCOM1 */ -#define PAC_INTFLAGC_SERCOM1 (0x1ul << PAC_INTFLAGC_SERCOM1_Pos) -#define PAC_INTFLAGC_SERCOM2_Pos 2 /**< \brief (PAC_INTFLAGC) SERCOM2 */ -#define PAC_INTFLAGC_SERCOM2 (0x1ul << PAC_INTFLAGC_SERCOM2_Pos) -#define PAC_INTFLAGC_SERCOM3_Pos 3 /**< \brief (PAC_INTFLAGC) SERCOM3 */ -#define PAC_INTFLAGC_SERCOM3 (0x1ul << PAC_INTFLAGC_SERCOM3_Pos) -#define PAC_INTFLAGC_SERCOM4_Pos 4 /**< \brief (PAC_INTFLAGC) SERCOM4 */ -#define PAC_INTFLAGC_SERCOM4 (0x1ul << PAC_INTFLAGC_SERCOM4_Pos) -#define PAC_INTFLAGC_TCC0_Pos 5 /**< \brief (PAC_INTFLAGC) TCC0 */ -#define PAC_INTFLAGC_TCC0 (0x1ul << PAC_INTFLAGC_TCC0_Pos) -#define PAC_INTFLAGC_TCC1_Pos 6 /**< \brief (PAC_INTFLAGC) TCC1 */ -#define PAC_INTFLAGC_TCC1 (0x1ul << PAC_INTFLAGC_TCC1_Pos) -#define PAC_INTFLAGC_TCC2_Pos 7 /**< \brief (PAC_INTFLAGC) TCC2 */ -#define PAC_INTFLAGC_TCC2 (0x1ul << PAC_INTFLAGC_TCC2_Pos) -#define PAC_INTFLAGC_TC0_Pos 8 /**< \brief (PAC_INTFLAGC) TC0 */ -#define PAC_INTFLAGC_TC0 (0x1ul << PAC_INTFLAGC_TC0_Pos) -#define PAC_INTFLAGC_TC1_Pos 9 /**< \brief (PAC_INTFLAGC) TC1 */ -#define PAC_INTFLAGC_TC1 (0x1ul << PAC_INTFLAGC_TC1_Pos) -#define PAC_INTFLAGC_TC2_Pos 10 /**< \brief (PAC_INTFLAGC) TC2 */ -#define PAC_INTFLAGC_TC2 (0x1ul << PAC_INTFLAGC_TC2_Pos) -#define PAC_INTFLAGC_TC3_Pos 11 /**< \brief (PAC_INTFLAGC) TC3 */ -#define PAC_INTFLAGC_TC3 (0x1ul << PAC_INTFLAGC_TC3_Pos) -#define PAC_INTFLAGC_DAC_Pos 12 /**< \brief (PAC_INTFLAGC) DAC */ -#define PAC_INTFLAGC_DAC (0x1ul << PAC_INTFLAGC_DAC_Pos) -#define PAC_INTFLAGC_AES_Pos 13 /**< \brief (PAC_INTFLAGC) AES */ -#define PAC_INTFLAGC_AES (0x1ul << PAC_INTFLAGC_AES_Pos) -#define PAC_INTFLAGC_TRNG_Pos 14 /**< \brief (PAC_INTFLAGC) TRNG */ -#define PAC_INTFLAGC_TRNG (0x1ul << PAC_INTFLAGC_TRNG_Pos) -#define PAC_INTFLAGC_MASK 0x00007FFFul /**< \brief (PAC_INTFLAGC) MASK Register */ - -/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVSYS_:1; /*!< bit: 0 EVSYS */ - uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */ - uint32_t TC4_:1; /*!< bit: 2 TC4 */ - uint32_t ADC_:1; /*!< bit: 3 ADC */ - uint32_t AC_:1; /*!< bit: 4 AC */ - uint32_t PTC_:1; /*!< bit: 5 PTC */ - uint32_t OPAMP_:1; /*!< bit: 6 OPAMP */ - uint32_t CCL_:1; /*!< bit: 7 CCL */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_INTFLAGD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */ -#define PAC_INTFLAGD_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */ - -#define PAC_INTFLAGD_EVSYS_Pos 0 /**< \brief (PAC_INTFLAGD) EVSYS */ -#define PAC_INTFLAGD_EVSYS (0x1ul << PAC_INTFLAGD_EVSYS_Pos) -#define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */ -#define PAC_INTFLAGD_SERCOM5 (0x1ul << PAC_INTFLAGD_SERCOM5_Pos) -#define PAC_INTFLAGD_TC4_Pos 2 /**< \brief (PAC_INTFLAGD) TC4 */ -#define PAC_INTFLAGD_TC4 (0x1ul << PAC_INTFLAGD_TC4_Pos) -#define PAC_INTFLAGD_ADC_Pos 3 /**< \brief (PAC_INTFLAGD) ADC */ -#define PAC_INTFLAGD_ADC (0x1ul << PAC_INTFLAGD_ADC_Pos) -#define PAC_INTFLAGD_AC_Pos 4 /**< \brief (PAC_INTFLAGD) AC */ -#define PAC_INTFLAGD_AC (0x1ul << PAC_INTFLAGD_AC_Pos) -#define PAC_INTFLAGD_PTC_Pos 5 /**< \brief (PAC_INTFLAGD) PTC */ -#define PAC_INTFLAGD_PTC (0x1ul << PAC_INTFLAGD_PTC_Pos) -#define PAC_INTFLAGD_OPAMP_Pos 6 /**< \brief (PAC_INTFLAGD) OPAMP */ -#define PAC_INTFLAGD_OPAMP (0x1ul << PAC_INTFLAGD_OPAMP_Pos) -#define PAC_INTFLAGD_CCL_Pos 7 /**< \brief (PAC_INTFLAGD) CCL */ -#define PAC_INTFLAGD_CCL (0x1ul << PAC_INTFLAGD_CCL_Pos) -#define PAC_INTFLAGD_MASK 0x000000FFul /**< \brief (PAC_INTFLAGD) MASK Register */ - -/* -------- PAC_INTFLAGE : (PAC Offset: 0x24) (R/W 32) Peripheral interrupt flag status - Bridge E -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC_:1; /*!< bit: 0 PAC */ - uint32_t DMAC_:1; /*!< bit: 1 DMAC */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_INTFLAGE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_INTFLAGE_OFFSET 0x24 /**< \brief (PAC_INTFLAGE offset) Peripheral interrupt flag status - Bridge E */ -#define PAC_INTFLAGE_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGE reset_value) Peripheral interrupt flag status - Bridge E */ - -#define PAC_INTFLAGE_PAC_Pos 0 /**< \brief (PAC_INTFLAGE) PAC */ -#define PAC_INTFLAGE_PAC (0x1ul << PAC_INTFLAGE_PAC_Pos) -#define PAC_INTFLAGE_DMAC_Pos 1 /**< \brief (PAC_INTFLAGE) DMAC */ -#define PAC_INTFLAGE_DMAC (0x1ul << PAC_INTFLAGE_DMAC_Pos) -#define PAC_INTFLAGE_MASK 0x00000003ul /**< \brief (PAC_INTFLAGE) MASK Register */ - -/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PM_:1; /*!< bit: 0 PM APB Protect Enable */ - uint32_t MCLK_:1; /*!< bit: 1 MCLK APB Protect Enable */ - uint32_t RSTC_:1; /*!< bit: 2 RSTC APB Protect Enable */ - uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL APB Protect Enable */ - uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL APB Protect Enable */ - uint32_t SUPC_:1; /*!< bit: 5 SUPC APB Protect Enable */ - uint32_t GCLK_:1; /*!< bit: 6 GCLK APB Protect Enable */ - uint32_t WDT_:1; /*!< bit: 7 WDT APB Protect Enable */ - uint32_t RTC_:1; /*!< bit: 8 RTC APB Protect Enable */ - uint32_t EIC_:1; /*!< bit: 9 EIC APB Protect Enable */ - uint32_t PORT_:1; /*!< bit: 10 PORT APB Protect Enable */ - uint32_t TAL_:1; /*!< bit: 11 TAL APB Protect Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */ -#define PAC_STATUSA_RESETVALUE 0x00003000ul /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */ - -#define PAC_STATUSA_PM_Pos 0 /**< \brief (PAC_STATUSA) PM APB Protect Enable */ -#define PAC_STATUSA_PM (0x1ul << PAC_STATUSA_PM_Pos) -#define PAC_STATUSA_MCLK_Pos 1 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */ -#define PAC_STATUSA_MCLK (0x1ul << PAC_STATUSA_MCLK_Pos) -#define PAC_STATUSA_RSTC_Pos 2 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */ -#define PAC_STATUSA_RSTC (0x1ul << PAC_STATUSA_RSTC_Pos) -#define PAC_STATUSA_OSCCTRL_Pos 3 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */ -#define PAC_STATUSA_OSCCTRL (0x1ul << PAC_STATUSA_OSCCTRL_Pos) -#define PAC_STATUSA_OSC32KCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */ -#define PAC_STATUSA_OSC32KCTRL (0x1ul << PAC_STATUSA_OSC32KCTRL_Pos) -#define PAC_STATUSA_SUPC_Pos 5 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */ -#define PAC_STATUSA_SUPC (0x1ul << PAC_STATUSA_SUPC_Pos) -#define PAC_STATUSA_GCLK_Pos 6 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */ -#define PAC_STATUSA_GCLK (0x1ul << PAC_STATUSA_GCLK_Pos) -#define PAC_STATUSA_WDT_Pos 7 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */ -#define PAC_STATUSA_WDT (0x1ul << PAC_STATUSA_WDT_Pos) -#define PAC_STATUSA_RTC_Pos 8 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */ -#define PAC_STATUSA_RTC (0x1ul << PAC_STATUSA_RTC_Pos) -#define PAC_STATUSA_EIC_Pos 9 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */ -#define PAC_STATUSA_EIC (0x1ul << PAC_STATUSA_EIC_Pos) -#define PAC_STATUSA_PORT_Pos 10 /**< \brief (PAC_STATUSA) PORT APB Protect Enable */ -#define PAC_STATUSA_PORT (0x1ul << PAC_STATUSA_PORT_Pos) -#define PAC_STATUSA_TAL_Pos 11 /**< \brief (PAC_STATUSA) TAL APB Protect Enable */ -#define PAC_STATUSA_TAL (0x1ul << PAC_STATUSA_TAL_Pos) -#define PAC_STATUSA_MASK 0x00000FFFul /**< \brief (PAC_STATUSA) MASK Register */ - -/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */ - uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */ - uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */ - uint32_t MTB_:1; /*!< bit: 3 MTB APB Protect Enable */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */ -#define PAC_STATUSB_RESETVALUE 0x00000002ul /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */ - -#define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */ -#define PAC_STATUSB_USB (0x1ul << PAC_STATUSB_USB_Pos) -#define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */ -#define PAC_STATUSB_DSU (0x1ul << PAC_STATUSB_DSU_Pos) -#define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */ -#define PAC_STATUSB_NVMCTRL (0x1ul << PAC_STATUSB_NVMCTRL_Pos) -#define PAC_STATUSB_MTB_Pos 3 /**< \brief (PAC_STATUSB) MTB APB Protect Enable */ -#define PAC_STATUSB_MTB (0x1ul << PAC_STATUSB_MTB_Pos) -#define PAC_STATUSB_MASK 0x0000000Ful /**< \brief (PAC_STATUSB) MASK Register */ - -/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 APB Protect Enable */ - uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 APB Protect Enable */ - uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 APB Protect Enable */ - uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 APB Protect Enable */ - uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 APB Protect Enable */ - uint32_t TCC0_:1; /*!< bit: 5 TCC0 APB Protect Enable */ - uint32_t TCC1_:1; /*!< bit: 6 TCC1 APB Protect Enable */ - uint32_t TCC2_:1; /*!< bit: 7 TCC2 APB Protect Enable */ - uint32_t TC0_:1; /*!< bit: 8 TC0 APB Protect Enable */ - uint32_t TC1_:1; /*!< bit: 9 TC1 APB Protect Enable */ - uint32_t TC2_:1; /*!< bit: 10 TC2 APB Protect Enable */ - uint32_t TC3_:1; /*!< bit: 11 TC3 APB Protect Enable */ - uint32_t DAC_:1; /*!< bit: 12 DAC APB Protect Enable */ - uint32_t AES_:1; /*!< bit: 13 AES APB Protect Enable */ - uint32_t TRNG_:1; /*!< bit: 14 TRNG APB Protect Enable */ - uint32_t :17; /*!< bit: 15..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_STATUSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */ -#define PAC_STATUSC_RESETVALUE 0x00000000ul /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */ - -#define PAC_STATUSC_SERCOM0_Pos 0 /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */ -#define PAC_STATUSC_SERCOM0 (0x1ul << PAC_STATUSC_SERCOM0_Pos) -#define PAC_STATUSC_SERCOM1_Pos 1 /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */ -#define PAC_STATUSC_SERCOM1 (0x1ul << PAC_STATUSC_SERCOM1_Pos) -#define PAC_STATUSC_SERCOM2_Pos 2 /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */ -#define PAC_STATUSC_SERCOM2 (0x1ul << PAC_STATUSC_SERCOM2_Pos) -#define PAC_STATUSC_SERCOM3_Pos 3 /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */ -#define PAC_STATUSC_SERCOM3 (0x1ul << PAC_STATUSC_SERCOM3_Pos) -#define PAC_STATUSC_SERCOM4_Pos 4 /**< \brief (PAC_STATUSC) SERCOM4 APB Protect Enable */ -#define PAC_STATUSC_SERCOM4 (0x1ul << PAC_STATUSC_SERCOM4_Pos) -#define PAC_STATUSC_TCC0_Pos 5 /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */ -#define PAC_STATUSC_TCC0 (0x1ul << PAC_STATUSC_TCC0_Pos) -#define PAC_STATUSC_TCC1_Pos 6 /**< \brief (PAC_STATUSC) TCC1 APB Protect Enable */ -#define PAC_STATUSC_TCC1 (0x1ul << PAC_STATUSC_TCC1_Pos) -#define PAC_STATUSC_TCC2_Pos 7 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */ -#define PAC_STATUSC_TCC2 (0x1ul << PAC_STATUSC_TCC2_Pos) -#define PAC_STATUSC_TC0_Pos 8 /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */ -#define PAC_STATUSC_TC0 (0x1ul << PAC_STATUSC_TC0_Pos) -#define PAC_STATUSC_TC1_Pos 9 /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */ -#define PAC_STATUSC_TC1 (0x1ul << PAC_STATUSC_TC1_Pos) -#define PAC_STATUSC_TC2_Pos 10 /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */ -#define PAC_STATUSC_TC2 (0x1ul << PAC_STATUSC_TC2_Pos) -#define PAC_STATUSC_TC3_Pos 11 /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */ -#define PAC_STATUSC_TC3 (0x1ul << PAC_STATUSC_TC3_Pos) -#define PAC_STATUSC_DAC_Pos 12 /**< \brief (PAC_STATUSC) DAC APB Protect Enable */ -#define PAC_STATUSC_DAC (0x1ul << PAC_STATUSC_DAC_Pos) -#define PAC_STATUSC_AES_Pos 13 /**< \brief (PAC_STATUSC) AES APB Protect Enable */ -#define PAC_STATUSC_AES (0x1ul << PAC_STATUSC_AES_Pos) -#define PAC_STATUSC_TRNG_Pos 14 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */ -#define PAC_STATUSC_TRNG (0x1ul << PAC_STATUSC_TRNG_Pos) -#define PAC_STATUSC_MASK 0x00007FFFul /**< \brief (PAC_STATUSC) MASK Register */ - -/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Protect Enable */ - uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */ - uint32_t TC4_:1; /*!< bit: 2 TC4 APB Protect Enable */ - uint32_t ADC_:1; /*!< bit: 3 ADC APB Protect Enable */ - uint32_t AC_:1; /*!< bit: 4 AC APB Protect Enable */ - uint32_t PTC_:1; /*!< bit: 5 PTC APB Protect Enable */ - uint32_t OPAMP_:1; /*!< bit: 6 OPAMP APB Protect Enable */ - uint32_t CCL_:1; /*!< bit: 7 CCL APB Protect Enable */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_STATUSD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */ -#define PAC_STATUSD_RESETVALUE 0x00000000ul /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */ - -#define PAC_STATUSD_EVSYS_Pos 0 /**< \brief (PAC_STATUSD) EVSYS APB Protect Enable */ -#define PAC_STATUSD_EVSYS (0x1ul << PAC_STATUSD_EVSYS_Pos) -#define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */ -#define PAC_STATUSD_SERCOM5 (0x1ul << PAC_STATUSD_SERCOM5_Pos) -#define PAC_STATUSD_TC4_Pos 2 /**< \brief (PAC_STATUSD) TC4 APB Protect Enable */ -#define PAC_STATUSD_TC4 (0x1ul << PAC_STATUSD_TC4_Pos) -#define PAC_STATUSD_ADC_Pos 3 /**< \brief (PAC_STATUSD) ADC APB Protect Enable */ -#define PAC_STATUSD_ADC (0x1ul << PAC_STATUSD_ADC_Pos) -#define PAC_STATUSD_AC_Pos 4 /**< \brief (PAC_STATUSD) AC APB Protect Enable */ -#define PAC_STATUSD_AC (0x1ul << PAC_STATUSD_AC_Pos) -#define PAC_STATUSD_PTC_Pos 5 /**< \brief (PAC_STATUSD) PTC APB Protect Enable */ -#define PAC_STATUSD_PTC (0x1ul << PAC_STATUSD_PTC_Pos) -#define PAC_STATUSD_OPAMP_Pos 6 /**< \brief (PAC_STATUSD) OPAMP APB Protect Enable */ -#define PAC_STATUSD_OPAMP (0x1ul << PAC_STATUSD_OPAMP_Pos) -#define PAC_STATUSD_CCL_Pos 7 /**< \brief (PAC_STATUSD) CCL APB Protect Enable */ -#define PAC_STATUSD_CCL (0x1ul << PAC_STATUSD_CCL_Pos) -#define PAC_STATUSD_MASK 0x000000FFul /**< \brief (PAC_STATUSD) MASK Register */ - -/* -------- PAC_STATUSE : (PAC Offset: 0x44) (R/ 32) Peripheral write protection status - Bridge E -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */ - uint32_t DMAC_:1; /*!< bit: 1 DMAC APB Protect Enable */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_STATUSE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_STATUSE_OFFSET 0x44 /**< \brief (PAC_STATUSE offset) Peripheral write protection status - Bridge E */ -#define PAC_STATUSE_RESETVALUE 0x00000000ul /**< \brief (PAC_STATUSE reset_value) Peripheral write protection status - Bridge E */ - -#define PAC_STATUSE_PAC_Pos 0 /**< \brief (PAC_STATUSE) PAC APB Protect Enable */ -#define PAC_STATUSE_PAC (0x1ul << PAC_STATUSE_PAC_Pos) -#define PAC_STATUSE_DMAC_Pos 1 /**< \brief (PAC_STATUSE) DMAC APB Protect Enable */ -#define PAC_STATUSE_DMAC (0x1ul << PAC_STATUSE_DMAC_Pos) -#define PAC_STATUSE_MASK 0x00000003ul /**< \brief (PAC_STATUSE) MASK Register */ - -/** \brief PAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */ - __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */ - RoReg8 Reserved1[0x3]; - __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */ - __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */ - RoReg8 Reserved2[0x6]; - __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */ - __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ - __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ - __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ - __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */ - __IO PAC_INTFLAGE_Type INTFLAGE; /**< \brief Offset: 0x24 (R/W 32) Peripheral interrupt flag status - Bridge E */ - RoReg8 Reserved3[0xC]; - __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ - __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ - __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ - __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */ - __I PAC_STATUSE_Type STATUSE; /**< \brief Offset: 0x44 (R/ 32) Peripheral write protection status - Bridge E */ -} Pac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_PAC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pm.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pm.h deleted file mode 100644 index 52de0994411..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pm.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - * \file - * - * \brief Component description for PM - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_PM_COMPONENT_ -#define _SAML21_PM_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PM */ -/* ========================================================================== */ -/** \addtogroup SAML21_PM Power Manager */ -/*@{*/ - -#define PM_U2240 -#define REV_PM 0x101 - -/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t IORET:1; /*!< bit: 2 I/O Retention */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */ -#define PM_CTRLA_RESETVALUE 0x00ul /**< \brief (PM_CTRLA reset_value) Control A */ - -#define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */ -#define PM_CTRLA_IORET (0x1ul << PM_CTRLA_IORET_Pos) -#define PM_CTRLA_MASK 0x04ul /**< \brief (PM_CTRLA) MASK Register */ - -/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_SLEEPCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */ -#define PM_SLEEPCFG_RESETVALUE 0x02ul /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */ - -#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */ -#define PM_SLEEPCFG_SLEEPMODE_Msk (0x7ul << PM_SLEEPCFG_SLEEPMODE_Pos) -#define PM_SLEEPCFG_SLEEPMODE(value) ((PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))) -#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val 0x0ul /**< \brief (PM_SLEEPCFG) CPU clock is OFF */ -#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val 0x1ul /**< \brief (PM_SLEEPCFG) AHB clock is OFF */ -#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val 0x2ul /**< \brief (PM_SLEEPCFG) APB clock are OFF */ -#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val 0x4ul /**< \brief (PM_SLEEPCFG) All Clocks are OFF */ -#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val 0x5ul /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */ -#define PM_SLEEPCFG_SLEEPMODE_OFF_Val 0x6ul /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */ -#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos) -#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos) -#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos) -#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos) -#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos) -#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos) -#define PM_SLEEPCFG_MASK 0x07ul /**< \brief (PM_SLEEPCFG) MASK Register */ - -/* -------- PM_PLCFG : (PM Offset: 0x02) (R/W 8) Performance Level Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PLSEL:2; /*!< bit: 0.. 1 Performance Level Select */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_PLCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_PLCFG_OFFSET 0x02 /**< \brief (PM_PLCFG offset) Performance Level Configuration */ -#define PM_PLCFG_RESETVALUE 0x00ul /**< \brief (PM_PLCFG reset_value) Performance Level Configuration */ - -#define PM_PLCFG_PLSEL_Pos 0 /**< \brief (PM_PLCFG) Performance Level Select */ -#define PM_PLCFG_PLSEL_Msk (0x3ul << PM_PLCFG_PLSEL_Pos) -#define PM_PLCFG_PLSEL(value) ((PM_PLCFG_PLSEL_Msk & ((value) << PM_PLCFG_PLSEL_Pos))) -#define PM_PLCFG_PLSEL_PL0_Val 0x0ul /**< \brief (PM_PLCFG) Performance Level 0 */ -#define PM_PLCFG_PLSEL_PL1_Val 0x1ul /**< \brief (PM_PLCFG) Performance Level 1 */ -#define PM_PLCFG_PLSEL_PL2_Val 0x2ul /**< \brief (PM_PLCFG) Performance Level 2 */ -#define PM_PLCFG_PLSEL_PL0 (PM_PLCFG_PLSEL_PL0_Val << PM_PLCFG_PLSEL_Pos) -#define PM_PLCFG_PLSEL_PL1 (PM_PLCFG_PLSEL_PL1_Val << PM_PLCFG_PLSEL_Pos) -#define PM_PLCFG_PLSEL_PL2 (PM_PLCFG_PLSEL_PL2_Val << PM_PLCFG_PLSEL_Pos) -#define PM_PLCFG_MASK 0x03ul /**< \brief (PM_PLCFG) MASK Register */ - -/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PLRDY:1; /*!< bit: 0 Performance Level Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */ -#define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */ - -#define PM_INTENCLR_PLRDY_Pos 0 /**< \brief (PM_INTENCLR) Performance Level Interrupt Enable */ -#define PM_INTENCLR_PLRDY (0x1ul << PM_INTENCLR_PLRDY_Pos) -#define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */ - -/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PLRDY:1; /*!< bit: 0 Performance Level Ready interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */ -#define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */ - -#define PM_INTENSET_PLRDY_Pos 0 /**< \brief (PM_INTENSET) Performance Level Ready interrupt Enable */ -#define PM_INTENSET_PLRDY (0x1ul << PM_INTENSET_PLRDY_Pos) -#define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */ - -/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PLRDY:1; /*!< bit: 0 Performance Level Ready */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */ -#define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define PM_INTFLAG_PLRDY_Pos 0 /**< \brief (PM_INTFLAG) Performance Level Ready */ -#define PM_INTFLAG_PLRDY (0x1ul << PM_INTFLAG_PLRDY_Pos) -#define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */ - -/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 16) Standby Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PDCFG:2; /*!< bit: 0.. 1 Power Domain Configuration */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t DPGPD0:1; /*!< bit: 4 Dynamic Power Gating for PD0 */ - uint16_t DPGPD1:1; /*!< bit: 5 Dynamic Power Gating for PD1 */ - uint16_t :1; /*!< bit: 6 Reserved */ - uint16_t AVREGSD:1; /*!< bit: 7 Automatic VREG Switching Disable */ - uint16_t LINKPD:2; /*!< bit: 8.. 9 Linked Power Domain */ - uint16_t BBIASHS:2; /*!< bit: 10..11 Back Bias for HMCRAMCHS */ - uint16_t BBIASLP:2; /*!< bit: 12..13 Back Bias for HMCRAMCLP */ - uint16_t BBIASPP:2; /*!< bit: 14..15 Back Bias for PicoPram */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} PM_STDBYCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */ -#define PM_STDBYCFG_RESETVALUE 0x0000ul /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */ - -#define PM_STDBYCFG_PDCFG_Pos 0 /**< \brief (PM_STDBYCFG) Power Domain Configuration */ -#define PM_STDBYCFG_PDCFG_Msk (0x3ul << PM_STDBYCFG_PDCFG_Pos) -#define PM_STDBYCFG_PDCFG(value) ((PM_STDBYCFG_PDCFG_Msk & ((value) << PM_STDBYCFG_PDCFG_Pos))) -#define PM_STDBYCFG_PDCFG_DEFAULT_Val 0x0ul /**< \brief (PM_STDBYCFG) All power domains switching is handled by hardware. */ -#define PM_STDBYCFG_PDCFG_PD0_Val 0x1ul /**< \brief (PM_STDBYCFG) PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware. */ -#define PM_STDBYCFG_PDCFG_PD01_Val 0x2ul /**< \brief (PM_STDBYCFG) PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware. */ -#define PM_STDBYCFG_PDCFG_PD012_Val 0x3ul /**< \brief (PM_STDBYCFG) All power domains are forced ACTIVE. */ -#define PM_STDBYCFG_PDCFG_DEFAULT (PM_STDBYCFG_PDCFG_DEFAULT_Val << PM_STDBYCFG_PDCFG_Pos) -#define PM_STDBYCFG_PDCFG_PD0 (PM_STDBYCFG_PDCFG_PD0_Val << PM_STDBYCFG_PDCFG_Pos) -#define PM_STDBYCFG_PDCFG_PD01 (PM_STDBYCFG_PDCFG_PD01_Val << PM_STDBYCFG_PDCFG_Pos) -#define PM_STDBYCFG_PDCFG_PD012 (PM_STDBYCFG_PDCFG_PD012_Val << PM_STDBYCFG_PDCFG_Pos) -#define PM_STDBYCFG_DPGPD0_Pos 4 /**< \brief (PM_STDBYCFG) Dynamic Power Gating for PD0 */ -#define PM_STDBYCFG_DPGPD0 (0x1ul << PM_STDBYCFG_DPGPD0_Pos) -#define PM_STDBYCFG_DPGPD1_Pos 5 /**< \brief (PM_STDBYCFG) Dynamic Power Gating for PD1 */ -#define PM_STDBYCFG_DPGPD1 (0x1ul << PM_STDBYCFG_DPGPD1_Pos) -#define PM_STDBYCFG_AVREGSD_Pos 7 /**< \brief (PM_STDBYCFG) Automatic VREG Switching Disable */ -#define PM_STDBYCFG_AVREGSD (0x1ul << PM_STDBYCFG_AVREGSD_Pos) -#define PM_STDBYCFG_LINKPD_Pos 8 /**< \brief (PM_STDBYCFG) Linked Power Domain */ -#define PM_STDBYCFG_LINKPD_Msk (0x3ul << PM_STDBYCFG_LINKPD_Pos) -#define PM_STDBYCFG_LINKPD(value) ((PM_STDBYCFG_LINKPD_Msk & ((value) << PM_STDBYCFG_LINKPD_Pos))) -#define PM_STDBYCFG_LINKPD_DEFAULT_Val 0x0ul /**< \brief (PM_STDBYCFG) Power domains are not linked */ -#define PM_STDBYCFG_LINKPD_PD01_Val 0x1ul /**< \brief (PM_STDBYCFG) PD0 and PD1 power domains are linked */ -#define PM_STDBYCFG_LINKPD_PD12_Val 0x2ul /**< \brief (PM_STDBYCFG) PD1 and PD2 power domains are linked */ -#define PM_STDBYCFG_LINKPD_PD012_Val 0x3ul /**< \brief (PM_STDBYCFG) All power domains are linked */ -#define PM_STDBYCFG_LINKPD_DEFAULT (PM_STDBYCFG_LINKPD_DEFAULT_Val << PM_STDBYCFG_LINKPD_Pos) -#define PM_STDBYCFG_LINKPD_PD01 (PM_STDBYCFG_LINKPD_PD01_Val << PM_STDBYCFG_LINKPD_Pos) -#define PM_STDBYCFG_LINKPD_PD12 (PM_STDBYCFG_LINKPD_PD12_Val << PM_STDBYCFG_LINKPD_Pos) -#define PM_STDBYCFG_LINKPD_PD012 (PM_STDBYCFG_LINKPD_PD012_Val << PM_STDBYCFG_LINKPD_Pos) -#define PM_STDBYCFG_BBIASHS_Pos 10 /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCHS */ -#define PM_STDBYCFG_BBIASHS_Msk (0x3ul << PM_STDBYCFG_BBIASHS_Pos) -#define PM_STDBYCFG_BBIASHS(value) ((PM_STDBYCFG_BBIASHS_Msk & ((value) << PM_STDBYCFG_BBIASHS_Pos))) -#define PM_STDBYCFG_BBIASLP_Pos 12 /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCLP */ -#define PM_STDBYCFG_BBIASLP_Msk (0x3ul << PM_STDBYCFG_BBIASLP_Pos) -#define PM_STDBYCFG_BBIASLP(value) ((PM_STDBYCFG_BBIASLP_Msk & ((value) << PM_STDBYCFG_BBIASLP_Pos))) -#define PM_STDBYCFG_BBIASPP_Pos 14 /**< \brief (PM_STDBYCFG) Back Bias for PicoPram */ -#define PM_STDBYCFG_BBIASPP_Msk (0x3ul << PM_STDBYCFG_BBIASPP_Pos) -#define PM_STDBYCFG_BBIASPP(value) ((PM_STDBYCFG_BBIASPP_Msk & ((value) << PM_STDBYCFG_BBIASPP_Pos))) -#define PM_STDBYCFG_MASK 0xFFB3ul /**< \brief (PM_STDBYCFG) MASK Register */ - -/* -------- PM_PWSAKDLY : (PM Offset: 0x0C) (R/W 8) Power Switch Acknowledge Delay -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */ - uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_PWSAKDLY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_PWSAKDLY_OFFSET 0x0C /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */ -#define PM_PWSAKDLY_RESETVALUE 0x00ul /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */ - -#define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */ -#define PM_PWSAKDLY_DLYVAL_Msk (0x7Ful << PM_PWSAKDLY_DLYVAL_Pos) -#define PM_PWSAKDLY_DLYVAL(value) ((PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))) -#define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */ -#define PM_PWSAKDLY_IGNACK (0x1ul << PM_PWSAKDLY_IGNACK_Pos) -#define PM_PWSAKDLY_MASK 0xFFul /**< \brief (PM_PWSAKDLY) MASK Register */ - -/** \brief PM hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */ - __IO PM_PLCFG_Type PLCFG; /**< \brief Offset: 0x02 (R/W 8) Performance Level Configuration */ - RoReg8 Reserved1[0x1]; - __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved2[0x1]; - __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 16) Standby Configuration */ - RoReg8 Reserved3[0x2]; - __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x0C (R/W 8) Power Switch Acknowledge Delay */ -} Pm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_PM_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_port.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_port.h deleted file mode 100644 index 73a8f8bd280..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_port.h +++ /dev/null @@ -1,361 +0,0 @@ -/** - * \file - * - * \brief Component description for PORT - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_PORT_COMPONENT_ -#define _SAML21_PORT_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PORT */ -/* ========================================================================== */ -/** \addtogroup SAML21_PORT Port Module */ -/*@{*/ - -#define PORT_U2210 -#define REV_PORT 0x201 - -/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_DIR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */ -#define PORT_DIR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */ -#define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */ - -/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */ -#define PORT_DIRCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */ -#define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */ - -/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */ -#define PORT_DIRSET_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */ -#define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */ - -/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRTGL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */ -#define PORT_DIRTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */ -#define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */ - -/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_OUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */ -#define PORT_OUT_RESETVALUE 0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */ -#define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */ - -/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */ -#define PORT_OUTCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */ -#define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */ - -/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */ -#define PORT_OUTSET_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */ -#define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */ - -/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTTGL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */ -#define PORT_OUTTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */ -#define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */ - -/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} PORT_IN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */ -#define PORT_IN_RESETVALUE 0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */ -#define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */ - -/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */ -#define PORT_CTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */ - -#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */ -#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos) -#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))) -#define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */ - -/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ - uint32_t PMUXEN:1; /*!< bit: 16 Select Peripheral Multiplexer */ - uint32_t INEN:1; /*!< bit: 17 Input Enable */ - uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ - uint32_t :3; /*!< bit: 19..21 Reserved */ - uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing Template */ - uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX Registers */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG Registers */ - uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_WRCONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */ -#define PORT_WRCONFIG_RESETVALUE 0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */ - -#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */ -#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos) -#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))) -#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Select Peripheral Multiplexer */ -#define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos) -#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */ -#define PORT_WRCONFIG_INEN (0x1ul << PORT_WRCONFIG_INEN_Pos) -#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */ -#define PORT_WRCONFIG_PULLEN (0x1ul << PORT_WRCONFIG_PULLEN_Pos) -#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */ -#define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos) -#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing Template */ -#define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos) -#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))) -#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX Registers */ -#define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos) -#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG Registers */ -#define PORT_WRCONFIG_WRPINCFG (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos) -#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */ -#define PORT_WRCONFIG_HWSEL (0x1ul << PORT_WRCONFIG_HWSEL_Pos) -#define PORT_WRCONFIG_MASK 0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */ - -/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PID0:5; /*!< bit: 0.. 4 Port Event Pin Identifier 0 */ - uint32_t EVACT0:2; /*!< bit: 5.. 6 Port Event Action 0 */ - uint32_t PORTEI0:1; /*!< bit: 7 Port Event Enable Input 0 */ - uint32_t PID1:5; /*!< bit: 8..12 Port Event Pin Identifier 1 */ - uint32_t EVACT1:2; /*!< bit: 13..14 Port Event Action 1 */ - uint32_t PORTEI1:1; /*!< bit: 15 Port Event Enable Input 1 */ - uint32_t PID2:5; /*!< bit: 16..20 Port Event Pin Identifier 2 */ - uint32_t EVACT2:2; /*!< bit: 21..22 Port Event Action 2 */ - uint32_t PORTEI2:1; /*!< bit: 23 Port Event Enable Input 2 */ - uint32_t PID3:5; /*!< bit: 24..28 Port Event Pin Identifier 3 */ - uint32_t EVACT3:2; /*!< bit: 29..30 Port Event Action 3 */ - uint32_t PORTEI3:1; /*!< bit: 31 Port Event Enable Input 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */ -#define PORT_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_EVCTRL reset_value) Event Input Control */ - -#define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 0 */ -#define PORT_EVCTRL_PID0_Msk (0x1Ful << PORT_EVCTRL_PID0_Pos) -#define PORT_EVCTRL_PID0(value) ((PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))) -#define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) Port Event Action 0 */ -#define PORT_EVCTRL_EVACT0_Msk (0x3ul << PORT_EVCTRL_EVACT0_Pos) -#define PORT_EVCTRL_EVACT0(value) ((PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))) -#define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) Port Event Enable Input 0 */ -#define PORT_EVCTRL_PORTEI0 (0x1ul << PORT_EVCTRL_PORTEI0_Pos) -#define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 1 */ -#define PORT_EVCTRL_PID1_Msk (0x1Ful << PORT_EVCTRL_PID1_Pos) -#define PORT_EVCTRL_PID1(value) ((PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))) -#define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) Port Event Action 1 */ -#define PORT_EVCTRL_EVACT1_Msk (0x3ul << PORT_EVCTRL_EVACT1_Pos) -#define PORT_EVCTRL_EVACT1(value) ((PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))) -#define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) Port Event Enable Input 1 */ -#define PORT_EVCTRL_PORTEI1 (0x1ul << PORT_EVCTRL_PORTEI1_Pos) -#define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 2 */ -#define PORT_EVCTRL_PID2_Msk (0x1Ful << PORT_EVCTRL_PID2_Pos) -#define PORT_EVCTRL_PID2(value) ((PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))) -#define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) Port Event Action 2 */ -#define PORT_EVCTRL_EVACT2_Msk (0x3ul << PORT_EVCTRL_EVACT2_Pos) -#define PORT_EVCTRL_EVACT2(value) ((PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))) -#define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) Port Event Enable Input 2 */ -#define PORT_EVCTRL_PORTEI2 (0x1ul << PORT_EVCTRL_PORTEI2_Pos) -#define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 3 */ -#define PORT_EVCTRL_PID3_Msk (0x1Ful << PORT_EVCTRL_PID3_Pos) -#define PORT_EVCTRL_PID3(value) ((PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))) -#define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) Port Event Action 3 */ -#define PORT_EVCTRL_EVACT3_Msk (0x3ul << PORT_EVCTRL_EVACT3_Pos) -#define PORT_EVCTRL_EVACT3(value) ((PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))) -#define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) Port Event Enable Input 3 */ -#define PORT_EVCTRL_PORTEI3 (0x1ul << PORT_EVCTRL_PORTEI3_Pos) -#define PORT_EVCTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_EVCTRL) MASK Register */ - -/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */ - uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PORT_PMUX_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */ -#define PORT_PMUX_RESETVALUE 0x00ul /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */ - -#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */ -#define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))) -#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */ -#define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))) -#define PORT_PMUX_MASK 0xFFul /**< \brief (PORT_PMUX) MASK Register */ - -/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PMUXEN:1; /*!< bit: 0 Select Peripheral Multiplexer */ - uint8_t INEN:1; /*!< bit: 1 Input Enable */ - uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PORT_PINCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */ -#define PORT_PINCFG_RESETVALUE 0x00ul /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */ - -#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Select Peripheral Multiplexer */ -#define PORT_PINCFG_PMUXEN (0x1ul << PORT_PINCFG_PMUXEN_Pos) -#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */ -#define PORT_PINCFG_INEN (0x1ul << PORT_PINCFG_INEN_Pos) -#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */ -#define PORT_PINCFG_PULLEN (0x1ul << PORT_PINCFG_PULLEN_Pos) -#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */ -#define PORT_PINCFG_DRVSTR (0x1ul << PORT_PINCFG_DRVSTR_Pos) -#define PORT_PINCFG_MASK 0x47ul /**< \brief (PORT_PINCFG) MASK Register */ - -/** \brief PortGroup hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ - __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ - __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ - __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ - __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ - __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ - __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ - __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ - __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ - __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ - __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ - __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */ - __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ - __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ - RoReg8 Reserved1[0x20]; -} PortGroup; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief PORT hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ -} Port; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_PORT_IOBUS - -/*@}*/ - -#endif /* _SAML21_PORT_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rstc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rstc.h deleted file mode 100644 index b8affb96bff..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rstc.h +++ /dev/null @@ -1,225 +0,0 @@ -/** - * \file - * - * \brief Component description for RSTC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_RSTC_COMPONENT_ -#define _SAML21_RSTC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR RSTC */ -/* ========================================================================== */ -/** \addtogroup SAML21_RSTC Reset Controller */ -/*@{*/ - -#define RSTC_U2239 -#define REV_RSTC 0x110 - -/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t POR:1; /*!< bit: 0 Power On Reset */ - uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ - uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EXT:1; /*!< bit: 4 External Reset */ - uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ - uint8_t SYST:1; /*!< bit: 6 System Reset Request */ - uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RSTC_RCAUSE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */ - -#define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */ -#define RSTC_RCAUSE_POR (0x1ul << RSTC_RCAUSE_POR_Pos) -#define RSTC_RCAUSE_BOD12_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out 12 Detector Reset */ -#define RSTC_RCAUSE_BOD12 (0x1ul << RSTC_RCAUSE_BOD12_Pos) -#define RSTC_RCAUSE_BOD33_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out 33 Detector Reset */ -#define RSTC_RCAUSE_BOD33 (0x1ul << RSTC_RCAUSE_BOD33_Pos) -#define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */ -#define RSTC_RCAUSE_EXT (0x1ul << RSTC_RCAUSE_EXT_Pos) -#define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */ -#define RSTC_RCAUSE_WDT (0x1ul << RSTC_RCAUSE_WDT_Pos) -#define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */ -#define RSTC_RCAUSE_SYST (0x1ul << RSTC_RCAUSE_SYST_Pos) -#define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */ -#define RSTC_RCAUSE_BACKUP (0x1ul << RSTC_RCAUSE_BACKUP_Pos) -#define RSTC_RCAUSE_MASK 0xF7ul /**< \brief (RSTC_RCAUSE) MASK Register */ - -/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EXTWAKE:1; /*!< bit: 0 External Wakeup */ - uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */ - uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RSTC_BKUPEXIT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */ - -#define RSTC_BKUPEXIT_EXTWAKE_Pos 0 /**< \brief (RSTC_BKUPEXIT) External Wakeup */ -#define RSTC_BKUPEXIT_EXTWAKE (0x1ul << RSTC_BKUPEXIT_EXTWAKE_Pos) -#define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */ -#define RSTC_BKUPEXIT_RTC (0x1ul << RSTC_BKUPEXIT_RTC_Pos) -#define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */ -#define RSTC_BKUPEXIT_BBPS (0x1ul << RSTC_BKUPEXIT_BBPS_Pos) -#define RSTC_BKUPEXIT_MASK 0x07ul /**< \brief (RSTC_BKUPEXIT) MASK Register */ - -/* -------- RSTC_WKDBCONF : (RSTC Offset: 0x04) (R/W 8) Wakeup Debounce Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WKDBCNT:5; /*!< bit: 0.. 4 Wakeup Debounce Counter */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RSTC_WKDBCONF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RSTC_WKDBCONF_OFFSET 0x04 /**< \brief (RSTC_WKDBCONF offset) Wakeup Debounce Configuration */ -#define RSTC_WKDBCONF_RESETVALUE 0x00ul /**< \brief (RSTC_WKDBCONF reset_value) Wakeup Debounce Configuration */ - -#define RSTC_WKDBCONF_WKDBCNT_Pos 0 /**< \brief (RSTC_WKDBCONF) Wakeup Debounce Counter */ -#define RSTC_WKDBCONF_WKDBCNT_Msk (0x1Ful << RSTC_WKDBCONF_WKDBCNT_Pos) -#define RSTC_WKDBCONF_WKDBCNT(value) ((RSTC_WKDBCONF_WKDBCNT_Msk & ((value) << RSTC_WKDBCONF_WKDBCNT_Pos))) -#define RSTC_WKDBCONF_WKDBCNT_OFF_Val 0x0ul /**< \brief (RSTC_WKDBCONF) No debouncing.Input pin is low or high level sensitive depending on its WKPOLx bit. */ -#define RSTC_WKDBCONF_WKDBCNT_2K32_Val 0x1ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least two 32kHz clock period. */ -#define RSTC_WKDBCONF_WKDBCNT_3CK32_Val 0x2ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least three 32kHz clock period. */ -#define RSTC_WKDBCONF_WKDBCNT_32CK32_Val 0x3ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 32 32kHz clock period. */ -#define RSTC_WKDBCONF_WKDBCNT_512CK32_Val 0x4ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 512 32kHz clock period. */ -#define RSTC_WKDBCONF_WKDBCNT_4096CK32_Val 0x5ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 4096 32kHz clock period. */ -#define RSTC_WKDBCONF_WKDBCNT_32768CK32_Val 0x6ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 32768 32kHz clock period. */ -#define RSTC_WKDBCONF_WKDBCNT_OFF (RSTC_WKDBCONF_WKDBCNT_OFF_Val << RSTC_WKDBCONF_WKDBCNT_Pos) -#define RSTC_WKDBCONF_WKDBCNT_2K32 (RSTC_WKDBCONF_WKDBCNT_2K32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) -#define RSTC_WKDBCONF_WKDBCNT_3CK32 (RSTC_WKDBCONF_WKDBCNT_3CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) -#define RSTC_WKDBCONF_WKDBCNT_32CK32 (RSTC_WKDBCONF_WKDBCNT_32CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) -#define RSTC_WKDBCONF_WKDBCNT_512CK32 (RSTC_WKDBCONF_WKDBCNT_512CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) -#define RSTC_WKDBCONF_WKDBCNT_4096CK32 (RSTC_WKDBCONF_WKDBCNT_4096CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) -#define RSTC_WKDBCONF_WKDBCNT_32768CK32 (RSTC_WKDBCONF_WKDBCNT_32768CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) -#define RSTC_WKDBCONF_MASK 0x1Ful /**< \brief (RSTC_WKDBCONF) MASK Register */ - -/* -------- RSTC_WKPOL : (RSTC Offset: 0x08) (R/W 16) Wakeup Polarity -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WKPOL:8; /*!< bit: 0.. 7 Wakeup Polarity */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RSTC_WKPOL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RSTC_WKPOL_OFFSET 0x08 /**< \brief (RSTC_WKPOL offset) Wakeup Polarity */ -#define RSTC_WKPOL_RESETVALUE 0x0000ul /**< \brief (RSTC_WKPOL reset_value) Wakeup Polarity */ - -#define RSTC_WKPOL_WKPOL_Pos 0 /**< \brief (RSTC_WKPOL) Wakeup Polarity */ -#define RSTC_WKPOL_WKPOL_Msk (0xFFul << RSTC_WKPOL_WKPOL_Pos) -#define RSTC_WKPOL_WKPOL(value) ((RSTC_WKPOL_WKPOL_Msk & ((value) << RSTC_WKPOL_WKPOL_Pos))) -#define RSTC_WKPOL_MASK 0x00FFul /**< \brief (RSTC_WKPOL) MASK Register */ - -/* -------- RSTC_WKEN : (RSTC Offset: 0x0C) (R/W 16) Wakeup Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WKEN:8; /*!< bit: 0.. 7 Wakeup Enable */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RSTC_WKEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RSTC_WKEN_OFFSET 0x0C /**< \brief (RSTC_WKEN offset) Wakeup Enable */ -#define RSTC_WKEN_RESETVALUE 0x0000ul /**< \brief (RSTC_WKEN reset_value) Wakeup Enable */ - -#define RSTC_WKEN_WKEN_Pos 0 /**< \brief (RSTC_WKEN) Wakeup Enable */ -#define RSTC_WKEN_WKEN_Msk (0xFFul << RSTC_WKEN_WKEN_Pos) -#define RSTC_WKEN_WKEN(value) ((RSTC_WKEN_WKEN_Msk & ((value) << RSTC_WKEN_WKEN_Pos))) -#define RSTC_WKEN_MASK 0x00FFul /**< \brief (RSTC_WKEN) MASK Register */ - -/* -------- RSTC_WKCAUSE : (RSTC Offset: 0x10) (R/W 16) Wakeup Cause -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WKCAUSE:16; /*!< bit: 0..15 Wakeup Cause */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RSTC_WKCAUSE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RSTC_WKCAUSE_OFFSET 0x10 /**< \brief (RSTC_WKCAUSE offset) Wakeup Cause */ -#define RSTC_WKCAUSE_RESETVALUE 0x0000ul /**< \brief (RSTC_WKCAUSE reset_value) Wakeup Cause */ - -#define RSTC_WKCAUSE_WKCAUSE_Pos 0 /**< \brief (RSTC_WKCAUSE) Wakeup Cause */ -#define RSTC_WKCAUSE_WKCAUSE_Msk (0xFFFFul << RSTC_WKCAUSE_WKCAUSE_Pos) -#define RSTC_WKCAUSE_WKCAUSE(value) ((RSTC_WKCAUSE_WKCAUSE_Msk & ((value) << RSTC_WKCAUSE_WKCAUSE_Pos))) -#define RSTC_WKCAUSE_MASK 0xFFFFul /**< \brief (RSTC_WKCAUSE) MASK Register */ - -/** \brief RSTC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */ - RoReg8 Reserved1[0x1]; - __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */ - RoReg8 Reserved2[0x1]; - __IO RSTC_WKDBCONF_Type WKDBCONF; /**< \brief Offset: 0x04 (R/W 8) Wakeup Debounce Configuration */ - RoReg8 Reserved3[0x3]; - __IO RSTC_WKPOL_Type WKPOL; /**< \brief Offset: 0x08 (R/W 16) Wakeup Polarity */ - RoReg8 Reserved4[0x2]; - __IO RSTC_WKEN_Type WKEN; /**< \brief Offset: 0x0C (R/W 16) Wakeup Enable */ - RoReg8 Reserved5[0x2]; - __IO RSTC_WKCAUSE_Type WKCAUSE; /**< \brief Offset: 0x10 (R/W 16) Wakeup Cause */ -} Rstc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_RSTC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rtc.h deleted file mode 100644 index 08008e20738..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rtc.h +++ /dev/null @@ -1,1423 +0,0 @@ -/** - * \file - * - * \brief Component description for RTC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_RTC_COMPONENT_ -#define _SAML21_RTC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR RTC */ -/* ========================================================================== */ -/** \addtogroup SAML21_RTC Real-Time Counter */ -/*@{*/ - -#define RTC_U2250 -#define REV_RTC 0x110 - -/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :3; /*!< bit: 4.. 6 Reserved */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :3; /*!< bit: 12..14 Reserved */ - uint16_t SYNCDIS:1; /*!< bit: 15 Count Read Synchronization Disable */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE0_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */ -#define RTC_MODE0_CTRLA_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */ - -#define RTC_MODE0_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRLA) Software Reset */ -#define RTC_MODE0_CTRLA_SWRST (0x1ul << RTC_MODE0_CTRLA_SWRST_Pos) -#define RTC_MODE0_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRLA) Enable */ -#define RTC_MODE0_CTRLA_ENABLE (0x1ul << RTC_MODE0_CTRLA_ENABLE_Pos) -#define RTC_MODE0_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRLA) Operating Mode */ -#define RTC_MODE0_CTRLA_MODE_Msk (0x3ul << RTC_MODE0_CTRLA_MODE_Pos) -#define RTC_MODE0_CTRLA_MODE(value) ((RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))) -#define RTC_MODE0_CTRLA_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */ -#define RTC_MODE0_CTRLA_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */ -#define RTC_MODE0_CTRLA_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */ -#define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos) -#define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos) -#define RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos) -#define RTC_MODE0_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRLA) Clear on Match */ -#define RTC_MODE0_CTRLA_MATCHCLR (0x1ul << RTC_MODE0_CTRLA_MATCHCLR_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRLA) Prescaler */ -#define RTC_MODE0_CTRLA_PRESCALER_Msk (0xFul << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER(value) ((RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))) -#define RTC_MODE0_CTRLA_PRESCALER_OFF_Val 0x0ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV1_Val 0x1ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV2_Val 0x2ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV4_Val 0x3ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV8_Val 0x4ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV16_Val 0x5ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV32_Val 0x6ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV64_Val 0x7ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV128_Val 0x8ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV256_Val 0x9ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV512_Val 0xAul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val 0xBul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) -#define RTC_MODE0_CTRLA_SYNCDIS_Pos 15 /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Disable */ -#define RTC_MODE0_CTRLA_SYNCDIS (0x1ul << RTC_MODE0_CTRLA_SYNCDIS_Pos) -#define RTC_MODE0_CTRLA_MASK 0x8F8Ful /**< \brief (RTC_MODE0_CTRLA) MASK Register */ - -/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :3; /*!< bit: 12..14 Reserved */ - uint16_t SYNCDIS:1; /*!< bit: 15 Count Read Synchronization Disable */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */ -#define RTC_MODE1_CTRLA_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */ - -#define RTC_MODE1_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRLA) Software Reset */ -#define RTC_MODE1_CTRLA_SWRST (0x1ul << RTC_MODE1_CTRLA_SWRST_Pos) -#define RTC_MODE1_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRLA) Enable */ -#define RTC_MODE1_CTRLA_ENABLE (0x1ul << RTC_MODE1_CTRLA_ENABLE_Pos) -#define RTC_MODE1_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRLA) Operating Mode */ -#define RTC_MODE1_CTRLA_MODE_Msk (0x3ul << RTC_MODE1_CTRLA_MODE_Pos) -#define RTC_MODE1_CTRLA_MODE(value) ((RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))) -#define RTC_MODE1_CTRLA_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */ -#define RTC_MODE1_CTRLA_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */ -#define RTC_MODE1_CTRLA_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */ -#define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos) -#define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos) -#define RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRLA) Prescaler */ -#define RTC_MODE1_CTRLA_PRESCALER_Msk (0xFul << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER(value) ((RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))) -#define RTC_MODE1_CTRLA_PRESCALER_OFF_Val 0x0ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV1_Val 0x1ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV2_Val 0x2ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV4_Val 0x3ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV8_Val 0x4ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV16_Val 0x5ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV32_Val 0x6ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV64_Val 0x7ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV128_Val 0x8ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV256_Val 0x9ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV512_Val 0xAul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val 0xBul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) -#define RTC_MODE1_CTRLA_SYNCDIS_Pos 15 /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Disable */ -#define RTC_MODE1_CTRLA_SYNCDIS (0x1ul << RTC_MODE1_CTRLA_SYNCDIS_Pos) -#define RTC_MODE1_CTRLA_MASK 0x8F0Ful /**< \brief (RTC_MODE1_CTRLA) MASK Register */ - -/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :3; /*!< bit: 12..14 Reserved */ - uint16_t SYNCDIS:1; /*!< bit: 15 Clock Read Synchronization Disable */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE2_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */ -#define RTC_MODE2_CTRLA_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */ - -#define RTC_MODE2_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRLA) Software Reset */ -#define RTC_MODE2_CTRLA_SWRST (0x1ul << RTC_MODE2_CTRLA_SWRST_Pos) -#define RTC_MODE2_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRLA) Enable */ -#define RTC_MODE2_CTRLA_ENABLE (0x1ul << RTC_MODE2_CTRLA_ENABLE_Pos) -#define RTC_MODE2_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRLA) Operating Mode */ -#define RTC_MODE2_CTRLA_MODE_Msk (0x3ul << RTC_MODE2_CTRLA_MODE_Pos) -#define RTC_MODE2_CTRLA_MODE(value) ((RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))) -#define RTC_MODE2_CTRLA_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */ -#define RTC_MODE2_CTRLA_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */ -#define RTC_MODE2_CTRLA_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */ -#define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos) -#define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos) -#define RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos) -#define RTC_MODE2_CTRLA_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRLA) Clock Representation */ -#define RTC_MODE2_CTRLA_CLKREP (0x1ul << RTC_MODE2_CTRLA_CLKREP_Pos) -#define RTC_MODE2_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRLA) Clear on Match */ -#define RTC_MODE2_CTRLA_MATCHCLR (0x1ul << RTC_MODE2_CTRLA_MATCHCLR_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRLA) Prescaler */ -#define RTC_MODE2_CTRLA_PRESCALER_Msk (0xFul << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER(value) ((RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))) -#define RTC_MODE2_CTRLA_PRESCALER_OFF_Val 0x0ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV1_Val 0x1ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV2_Val 0x2ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV4_Val 0x3ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV8_Val 0x4ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV16_Val 0x5ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV32_Val 0x6ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV64_Val 0x7ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV128_Val 0x8ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV256_Val 0x9ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV512_Val 0xAul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val 0xBul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) -#define RTC_MODE2_CTRLA_SYNCDIS_Pos 15 /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Disable */ -#define RTC_MODE2_CTRLA_SYNCDIS (0x1ul << RTC_MODE2_CTRLA_SYNCDIS_Pos) -#define RTC_MODE2_CTRLA_MASK 0x8FCFul /**< \brief (RTC_MODE2_CTRLA) MASK Register */ - -/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint32_t :6; /*!< bit: 9..14 Reserved */ - uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint32_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ - uint32_t :23; /*!< bit: 9..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE0_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */ -#define RTC_MODE0_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */ - -#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos) -#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos) -#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos) -#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos) -#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos) -#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos) -#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos) -#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos) -#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos) -#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))) -#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */ -#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos) -#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */ -#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos) -#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))) -#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos) -#define RTC_MODE0_EVCTRL_MASK 0x000081FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */ - -/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ - uint32_t :5; /*!< bit: 10..14 Reserved */ - uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint32_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ - uint32_t :22; /*!< bit: 10..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE1_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */ -#define RTC_MODE1_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */ - -#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos) -#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos) -#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos) -#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos) -#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos) -#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos) -#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos) -#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos) -#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos) -#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))) -#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos) -#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos) -#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos) -#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))) -#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos) -#define RTC_MODE1_EVCTRL_MASK 0x000083FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */ - -/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint32_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ - uint32_t :6; /*!< bit: 9..14 Reserved */ - uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint32_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ - uint32_t :23; /*!< bit: 9..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE2_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */ -#define RTC_MODE2_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */ - -#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos) -#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos) -#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos) -#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos) -#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos) -#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos) -#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos) -#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos) -#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos) -#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))) -#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */ -#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos) -#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */ -#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos) -#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))) -#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos) -#define RTC_MODE2_EVCTRL_MASK 0x000081FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */ - -/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ - uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ - uint16_t CMP:1; /*!< bit: 8 Compare x Interrupt Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */ -#define RTC_MODE0_INTENCLR_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */ - -#define RTC_MODE0_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER0 (1 << RTC_MODE0_INTENCLR_PER0_Pos) -#define RTC_MODE0_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER1 (1 << RTC_MODE0_INTENCLR_PER1_Pos) -#define RTC_MODE0_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER2 (1 << RTC_MODE0_INTENCLR_PER2_Pos) -#define RTC_MODE0_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER3 (1 << RTC_MODE0_INTENCLR_PER3_Pos) -#define RTC_MODE0_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER4 (1 << RTC_MODE0_INTENCLR_PER4_Pos) -#define RTC_MODE0_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER5 (1 << RTC_MODE0_INTENCLR_PER5_Pos) -#define RTC_MODE0_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER6 (1 << RTC_MODE0_INTENCLR_PER6_Pos) -#define RTC_MODE0_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER7 (1 << RTC_MODE0_INTENCLR_PER7_Pos) -#define RTC_MODE0_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */ -#define RTC_MODE0_INTENCLR_PER_Msk (0xFFul << RTC_MODE0_INTENCLR_PER_Pos) -#define RTC_MODE0_INTENCLR_PER(value) ((RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))) -#define RTC_MODE0_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos) -#define RTC_MODE0_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */ -#define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos) -#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))) -#define RTC_MODE0_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos) -#define RTC_MODE0_INTENCLR_MASK 0x81FFul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */ - -/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ - uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ - uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ - uint16_t :5; /*!< bit: 10..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ - uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */ -#define RTC_MODE1_INTENCLR_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */ - -#define RTC_MODE1_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER0 (1 << RTC_MODE1_INTENCLR_PER0_Pos) -#define RTC_MODE1_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER1 (1 << RTC_MODE1_INTENCLR_PER1_Pos) -#define RTC_MODE1_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER2 (1 << RTC_MODE1_INTENCLR_PER2_Pos) -#define RTC_MODE1_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER3 (1 << RTC_MODE1_INTENCLR_PER3_Pos) -#define RTC_MODE1_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER4 (1 << RTC_MODE1_INTENCLR_PER4_Pos) -#define RTC_MODE1_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER5 (1 << RTC_MODE1_INTENCLR_PER5_Pos) -#define RTC_MODE1_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER6 (1 << RTC_MODE1_INTENCLR_PER6_Pos) -#define RTC_MODE1_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER7 (1 << RTC_MODE1_INTENCLR_PER7_Pos) -#define RTC_MODE1_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */ -#define RTC_MODE1_INTENCLR_PER_Msk (0xFFul << RTC_MODE1_INTENCLR_PER_Pos) -#define RTC_MODE1_INTENCLR_PER(value) ((RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))) -#define RTC_MODE1_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos) -#define RTC_MODE1_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos) -#define RTC_MODE1_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos) -#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))) -#define RTC_MODE1_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos) -#define RTC_MODE1_INTENCLR_MASK 0x83FFul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */ - -/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ - uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ - uint16_t ALARM:1; /*!< bit: 8 Alarm x Interrupt Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */ -#define RTC_MODE2_INTENCLR_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */ - -#define RTC_MODE2_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER0 (1 << RTC_MODE2_INTENCLR_PER0_Pos) -#define RTC_MODE2_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER1 (1 << RTC_MODE2_INTENCLR_PER1_Pos) -#define RTC_MODE2_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER2 (1 << RTC_MODE2_INTENCLR_PER2_Pos) -#define RTC_MODE2_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER3 (1 << RTC_MODE2_INTENCLR_PER3_Pos) -#define RTC_MODE2_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER4 (1 << RTC_MODE2_INTENCLR_PER4_Pos) -#define RTC_MODE2_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER5 (1 << RTC_MODE2_INTENCLR_PER5_Pos) -#define RTC_MODE2_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER6 (1 << RTC_MODE2_INTENCLR_PER6_Pos) -#define RTC_MODE2_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER7 (1 << RTC_MODE2_INTENCLR_PER7_Pos) -#define RTC_MODE2_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */ -#define RTC_MODE2_INTENCLR_PER_Msk (0xFFul << RTC_MODE2_INTENCLR_PER_Pos) -#define RTC_MODE2_INTENCLR_PER(value) ((RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))) -#define RTC_MODE2_INTENCLR_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos) -#define RTC_MODE2_INTENCLR_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */ -#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos) -#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))) -#define RTC_MODE2_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos) -#define RTC_MODE2_INTENCLR_MASK 0x81FFul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */ - -/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ - uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ - uint16_t CMP:1; /*!< bit: 8 Compare x Interrupt Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */ -#define RTC_MODE0_INTENSET_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */ - -#define RTC_MODE0_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER0 (1 << RTC_MODE0_INTENSET_PER0_Pos) -#define RTC_MODE0_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER1 (1 << RTC_MODE0_INTENSET_PER1_Pos) -#define RTC_MODE0_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER2 (1 << RTC_MODE0_INTENSET_PER2_Pos) -#define RTC_MODE0_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER3 (1 << RTC_MODE0_INTENSET_PER3_Pos) -#define RTC_MODE0_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER4 (1 << RTC_MODE0_INTENSET_PER4_Pos) -#define RTC_MODE0_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER5 (1 << RTC_MODE0_INTENSET_PER5_Pos) -#define RTC_MODE0_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER6 (1 << RTC_MODE0_INTENSET_PER6_Pos) -#define RTC_MODE0_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER7 (1 << RTC_MODE0_INTENSET_PER7_Pos) -#define RTC_MODE0_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */ -#define RTC_MODE0_INTENSET_PER_Msk (0xFFul << RTC_MODE0_INTENSET_PER_Pos) -#define RTC_MODE0_INTENSET_PER(value) ((RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))) -#define RTC_MODE0_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */ -#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos) -#define RTC_MODE0_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */ -#define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos) -#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))) -#define RTC_MODE0_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos) -#define RTC_MODE0_INTENSET_MASK 0x81FFul /**< \brief (RTC_MODE0_INTENSET) MASK Register */ - -/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ - uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ - uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ - uint16_t :5; /*!< bit: 10..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ - uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */ -#define RTC_MODE1_INTENSET_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */ - -#define RTC_MODE1_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER0 (1 << RTC_MODE1_INTENSET_PER0_Pos) -#define RTC_MODE1_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER1 (1 << RTC_MODE1_INTENSET_PER1_Pos) -#define RTC_MODE1_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER2 (1 << RTC_MODE1_INTENSET_PER2_Pos) -#define RTC_MODE1_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER3 (1 << RTC_MODE1_INTENSET_PER3_Pos) -#define RTC_MODE1_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER4 (1 << RTC_MODE1_INTENSET_PER4_Pos) -#define RTC_MODE1_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER5 (1 << RTC_MODE1_INTENSET_PER5_Pos) -#define RTC_MODE1_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER6 (1 << RTC_MODE1_INTENSET_PER6_Pos) -#define RTC_MODE1_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER7 (1 << RTC_MODE1_INTENSET_PER7_Pos) -#define RTC_MODE1_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */ -#define RTC_MODE1_INTENSET_PER_Msk (0xFFul << RTC_MODE1_INTENSET_PER_Pos) -#define RTC_MODE1_INTENSET_PER(value) ((RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))) -#define RTC_MODE1_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos) -#define RTC_MODE1_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos) -#define RTC_MODE1_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos) -#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))) -#define RTC_MODE1_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos) -#define RTC_MODE1_INTENSET_MASK 0x83FFul /**< \brief (RTC_MODE1_INTENSET) MASK Register */ - -/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Enable */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Enable */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Enable */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Enable */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Enable */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Enable */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Enable */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Enable */ - uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */ - uint16_t ALARM:1; /*!< bit: 8 Alarm x Interrupt Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */ -#define RTC_MODE2_INTENSET_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */ - -#define RTC_MODE2_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */ -#define RTC_MODE2_INTENSET_PER0 (1 << RTC_MODE2_INTENSET_PER0_Pos) -#define RTC_MODE2_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */ -#define RTC_MODE2_INTENSET_PER1 (1 << RTC_MODE2_INTENSET_PER1_Pos) -#define RTC_MODE2_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */ -#define RTC_MODE2_INTENSET_PER2 (1 << RTC_MODE2_INTENSET_PER2_Pos) -#define RTC_MODE2_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */ -#define RTC_MODE2_INTENSET_PER3 (1 << RTC_MODE2_INTENSET_PER3_Pos) -#define RTC_MODE2_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */ -#define RTC_MODE2_INTENSET_PER4 (1 << RTC_MODE2_INTENSET_PER4_Pos) -#define RTC_MODE2_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */ -#define RTC_MODE2_INTENSET_PER5 (1 << RTC_MODE2_INTENSET_PER5_Pos) -#define RTC_MODE2_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */ -#define RTC_MODE2_INTENSET_PER6 (1 << RTC_MODE2_INTENSET_PER6_Pos) -#define RTC_MODE2_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */ -#define RTC_MODE2_INTENSET_PER7 (1 << RTC_MODE2_INTENSET_PER7_Pos) -#define RTC_MODE2_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */ -#define RTC_MODE2_INTENSET_PER_Msk (0xFFul << RTC_MODE2_INTENSET_PER_Pos) -#define RTC_MODE2_INTENSET_PER(value) ((RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))) -#define RTC_MODE2_INTENSET_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */ -#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos) -#define RTC_MODE2_INTENSET_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */ -#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos) -#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))) -#define RTC_MODE2_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos) -#define RTC_MODE2_INTENSET_MASK 0x81FFul /**< \brief (RTC_MODE2_INTENSET) MASK Register */ - -/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ - uint16_t CMP0:1; /*!< bit: 8 Compare 0 */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ - uint16_t CMP:1; /*!< bit: 8 Compare x */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */ -#define RTC_MODE0_INTFLAG_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */ - -#define RTC_MODE0_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */ -#define RTC_MODE0_INTFLAG_PER0 (1 << RTC_MODE0_INTFLAG_PER0_Pos) -#define RTC_MODE0_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */ -#define RTC_MODE0_INTFLAG_PER1 (1 << RTC_MODE0_INTFLAG_PER1_Pos) -#define RTC_MODE0_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */ -#define RTC_MODE0_INTFLAG_PER2 (1 << RTC_MODE0_INTFLAG_PER2_Pos) -#define RTC_MODE0_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */ -#define RTC_MODE0_INTFLAG_PER3 (1 << RTC_MODE0_INTFLAG_PER3_Pos) -#define RTC_MODE0_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */ -#define RTC_MODE0_INTFLAG_PER4 (1 << RTC_MODE0_INTFLAG_PER4_Pos) -#define RTC_MODE0_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */ -#define RTC_MODE0_INTFLAG_PER5 (1 << RTC_MODE0_INTFLAG_PER5_Pos) -#define RTC_MODE0_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */ -#define RTC_MODE0_INTFLAG_PER6 (1 << RTC_MODE0_INTFLAG_PER6_Pos) -#define RTC_MODE0_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */ -#define RTC_MODE0_INTFLAG_PER7 (1 << RTC_MODE0_INTFLAG_PER7_Pos) -#define RTC_MODE0_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */ -#define RTC_MODE0_INTFLAG_PER_Msk (0xFFul << RTC_MODE0_INTFLAG_PER_Pos) -#define RTC_MODE0_INTFLAG_PER(value) ((RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))) -#define RTC_MODE0_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */ -#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos) -#define RTC_MODE0_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare x */ -#define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos) -#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))) -#define RTC_MODE0_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE0_INTFLAG) Overflow */ -#define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos) -#define RTC_MODE0_INTFLAG_MASK 0x81FFul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */ - -/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ - uint16_t CMP0:1; /*!< bit: 8 Compare 0 */ - uint16_t CMP1:1; /*!< bit: 9 Compare 1 */ - uint16_t :5; /*!< bit: 10..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ - uint16_t CMP:2; /*!< bit: 8.. 9 Compare x */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */ -#define RTC_MODE1_INTFLAG_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */ - -#define RTC_MODE1_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */ -#define RTC_MODE1_INTFLAG_PER0 (1 << RTC_MODE1_INTFLAG_PER0_Pos) -#define RTC_MODE1_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */ -#define RTC_MODE1_INTFLAG_PER1 (1 << RTC_MODE1_INTFLAG_PER1_Pos) -#define RTC_MODE1_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */ -#define RTC_MODE1_INTFLAG_PER2 (1 << RTC_MODE1_INTFLAG_PER2_Pos) -#define RTC_MODE1_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */ -#define RTC_MODE1_INTFLAG_PER3 (1 << RTC_MODE1_INTFLAG_PER3_Pos) -#define RTC_MODE1_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */ -#define RTC_MODE1_INTFLAG_PER4 (1 << RTC_MODE1_INTFLAG_PER4_Pos) -#define RTC_MODE1_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */ -#define RTC_MODE1_INTFLAG_PER5 (1 << RTC_MODE1_INTFLAG_PER5_Pos) -#define RTC_MODE1_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */ -#define RTC_MODE1_INTFLAG_PER6 (1 << RTC_MODE1_INTFLAG_PER6_Pos) -#define RTC_MODE1_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */ -#define RTC_MODE1_INTFLAG_PER7 (1 << RTC_MODE1_INTFLAG_PER7_Pos) -#define RTC_MODE1_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */ -#define RTC_MODE1_INTFLAG_PER_Msk (0xFFul << RTC_MODE1_INTFLAG_PER_Pos) -#define RTC_MODE1_INTFLAG_PER(value) ((RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))) -#define RTC_MODE1_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */ -#define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos) -#define RTC_MODE1_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */ -#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos) -#define RTC_MODE1_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare x */ -#define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos) -#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))) -#define RTC_MODE1_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE1_INTFLAG) Overflow */ -#define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos) -#define RTC_MODE1_INTFLAG_MASK 0x83FFul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */ - -/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ - uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ - uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ - uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ - uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ - uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ - uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ - uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ - uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVF:1; /*!< bit: 15 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ - uint16_t ALARM:1; /*!< bit: 8 Alarm x */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */ -#define RTC_MODE2_INTFLAG_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */ - -#define RTC_MODE2_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */ -#define RTC_MODE2_INTFLAG_PER0 (1 << RTC_MODE2_INTFLAG_PER0_Pos) -#define RTC_MODE2_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */ -#define RTC_MODE2_INTFLAG_PER1 (1 << RTC_MODE2_INTFLAG_PER1_Pos) -#define RTC_MODE2_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */ -#define RTC_MODE2_INTFLAG_PER2 (1 << RTC_MODE2_INTFLAG_PER2_Pos) -#define RTC_MODE2_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */ -#define RTC_MODE2_INTFLAG_PER3 (1 << RTC_MODE2_INTFLAG_PER3_Pos) -#define RTC_MODE2_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */ -#define RTC_MODE2_INTFLAG_PER4 (1 << RTC_MODE2_INTFLAG_PER4_Pos) -#define RTC_MODE2_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */ -#define RTC_MODE2_INTFLAG_PER5 (1 << RTC_MODE2_INTFLAG_PER5_Pos) -#define RTC_MODE2_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */ -#define RTC_MODE2_INTFLAG_PER6 (1 << RTC_MODE2_INTFLAG_PER6_Pos) -#define RTC_MODE2_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */ -#define RTC_MODE2_INTFLAG_PER7 (1 << RTC_MODE2_INTFLAG_PER7_Pos) -#define RTC_MODE2_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */ -#define RTC_MODE2_INTFLAG_PER_Msk (0xFFul << RTC_MODE2_INTFLAG_PER_Pos) -#define RTC_MODE2_INTFLAG_PER(value) ((RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))) -#define RTC_MODE2_INTFLAG_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */ -#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos) -#define RTC_MODE2_INTFLAG_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */ -#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos) -#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))) -#define RTC_MODE2_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE2_INTFLAG) Overflow */ -#define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos) -#define RTC_MODE2_INTFLAG_MASK 0x81FFul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */ - -/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_DBGCTRL_OFFSET 0x0E /**< \brief (RTC_DBGCTRL offset) Debug Control */ -#define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */ - -#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */ -#define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos) -#define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */ - -/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE0 MODE0 Synchronization Busy Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ - uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ - uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */ - uint32_t :9; /*!< bit: 6..14 Reserved */ - uint32_t SYNCDIS:1; /*!< bit: 15 Count Read Synchronization Disable Bit Busy */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COMP:1; /*!< bit: 5 COMP x Register Busy */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE0_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */ -#define RTC_MODE0_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */ - -#define RTC_MODE0_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */ -#define RTC_MODE0_SYNCBUSY_SWRST (0x1ul << RTC_MODE0_SYNCBUSY_SWRST_Pos) -#define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */ -#define RTC_MODE0_SYNCBUSY_ENABLE (0x1ul << RTC_MODE0_SYNCBUSY_ENABLE_Pos) -#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */ -#define RTC_MODE0_SYNCBUSY_FREQCORR (0x1ul << RTC_MODE0_SYNCBUSY_FREQCORR_Pos) -#define RTC_MODE0_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */ -#define RTC_MODE0_SYNCBUSY_COUNT (0x1ul << RTC_MODE0_SYNCBUSY_COUNT_Pos) -#define RTC_MODE0_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */ -#define RTC_MODE0_SYNCBUSY_COMP0 (1 << RTC_MODE0_SYNCBUSY_COMP0_Pos) -#define RTC_MODE0_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */ -#define RTC_MODE0_SYNCBUSY_COMP_Msk (0x1ul << RTC_MODE0_SYNCBUSY_COMP_Pos) -#define RTC_MODE0_SYNCBUSY_COMP(value) ((RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))) -#define RTC_MODE0_SYNCBUSY_SYNCDIS_Pos 15 /**< \brief (RTC_MODE0_SYNCBUSY) Count Read Synchronization Disable Bit Busy */ -#define RTC_MODE0_SYNCBUSY_SYNCDIS (0x1ul << RTC_MODE0_SYNCBUSY_SYNCDIS_Pos) -#define RTC_MODE0_SYNCBUSY_MASK 0x0000802Ful /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */ - -/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE1 MODE1 Synchronization Busy Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ - uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ - uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */ - uint32_t PER:1; /*!< bit: 4 PER Register Busy */ - uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */ - uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */ - uint32_t :8; /*!< bit: 7..14 Reserved */ - uint32_t SYNCDIS:1; /*!< bit: 15 Count Read Synchronization Disable Bit Busy */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COMP:2; /*!< bit: 5.. 6 COMP x Register Busy */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE1_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */ -#define RTC_MODE1_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */ - -#define RTC_MODE1_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */ -#define RTC_MODE1_SYNCBUSY_SWRST (0x1ul << RTC_MODE1_SYNCBUSY_SWRST_Pos) -#define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */ -#define RTC_MODE1_SYNCBUSY_ENABLE (0x1ul << RTC_MODE1_SYNCBUSY_ENABLE_Pos) -#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */ -#define RTC_MODE1_SYNCBUSY_FREQCORR (0x1ul << RTC_MODE1_SYNCBUSY_FREQCORR_Pos) -#define RTC_MODE1_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */ -#define RTC_MODE1_SYNCBUSY_COUNT (0x1ul << RTC_MODE1_SYNCBUSY_COUNT_Pos) -#define RTC_MODE1_SYNCBUSY_PER_Pos 4 /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */ -#define RTC_MODE1_SYNCBUSY_PER (0x1ul << RTC_MODE1_SYNCBUSY_PER_Pos) -#define RTC_MODE1_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */ -#define RTC_MODE1_SYNCBUSY_COMP0 (1 << RTC_MODE1_SYNCBUSY_COMP0_Pos) -#define RTC_MODE1_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */ -#define RTC_MODE1_SYNCBUSY_COMP1 (1 << RTC_MODE1_SYNCBUSY_COMP1_Pos) -#define RTC_MODE1_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */ -#define RTC_MODE1_SYNCBUSY_COMP_Msk (0x3ul << RTC_MODE1_SYNCBUSY_COMP_Pos) -#define RTC_MODE1_SYNCBUSY_COMP(value) ((RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))) -#define RTC_MODE1_SYNCBUSY_SYNCDIS_Pos 15 /**< \brief (RTC_MODE1_SYNCBUSY) Count Read Synchronization Disable Bit Busy */ -#define RTC_MODE1_SYNCBUSY_SYNCDIS (0x1ul << RTC_MODE1_SYNCBUSY_SYNCDIS_Pos) -#define RTC_MODE1_SYNCBUSY_MASK 0x0000807Ful /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */ - -/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE2 MODE2 Synchronization Busy Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ - uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ - uint32_t CLOCK:1; /*!< bit: 3 CLOCK Register Busy */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t ALARM0:1; /*!< bit: 5 ALARM 0 Register Busy */ - uint32_t :5; /*!< bit: 6..10 Reserved */ - uint32_t MASK0:1; /*!< bit: 11 MASK 0 Register Busy */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t SYNCDIS:1; /*!< bit: 15 Clock Read Synchronization Disable Bit Busy */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t ALARM:1; /*!< bit: 5 ALARM x Register Busy */ - uint32_t :5; /*!< bit: 6..10 Reserved */ - uint32_t MASK:1; /*!< bit: 11 MASK x Register Busy */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE2_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */ -#define RTC_MODE2_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */ - -#define RTC_MODE2_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */ -#define RTC_MODE2_SYNCBUSY_SWRST (0x1ul << RTC_MODE2_SYNCBUSY_SWRST_Pos) -#define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */ -#define RTC_MODE2_SYNCBUSY_ENABLE (0x1ul << RTC_MODE2_SYNCBUSY_ENABLE_Pos) -#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */ -#define RTC_MODE2_SYNCBUSY_FREQCORR (0x1ul << RTC_MODE2_SYNCBUSY_FREQCORR_Pos) -#define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3 /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */ -#define RTC_MODE2_SYNCBUSY_CLOCK (0x1ul << RTC_MODE2_SYNCBUSY_CLOCK_Pos) -#define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */ -#define RTC_MODE2_SYNCBUSY_ALARM0 (1 << RTC_MODE2_SYNCBUSY_ALARM0_Pos) -#define RTC_MODE2_SYNCBUSY_ALARM_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */ -#define RTC_MODE2_SYNCBUSY_ALARM_Msk (0x1ul << RTC_MODE2_SYNCBUSY_ALARM_Pos) -#define RTC_MODE2_SYNCBUSY_ALARM(value) ((RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))) -#define RTC_MODE2_SYNCBUSY_MASK0_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */ -#define RTC_MODE2_SYNCBUSY_MASK0 (1 << RTC_MODE2_SYNCBUSY_MASK0_Pos) -#define RTC_MODE2_SYNCBUSY_MASK_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */ -#define RTC_MODE2_SYNCBUSY_MASK_Msk (0x1ul << RTC_MODE2_SYNCBUSY_MASK_Pos) -#define RTC_MODE2_SYNCBUSY_MASK(value) ((RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))) -#define RTC_MODE2_SYNCBUSY_SYNCDIS_Pos 15 /**< \brief (RTC_MODE2_SYNCBUSY) Clock Read Synchronization Disable Bit Busy */ -#define RTC_MODE2_SYNCBUSY_SYNCDIS (0x1ul << RTC_MODE2_SYNCBUSY_SYNCDIS_Pos) -#define RTC_MODE2_SYNCBUSY_MASK_ 0x0000882Ful /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */ - -/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ - uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_FREQCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_FREQCORR_OFFSET 0x14 /**< \brief (RTC_FREQCORR offset) Frequency Correction */ -#define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */ - -#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */ -#define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos) -#define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))) -#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */ -#define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos) -#define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */ - -/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE0_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */ -#define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */ - -#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */ -#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos) -#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))) -#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */ - -/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */ -#define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */ - -#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */ -#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos) -#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))) -#define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */ - -/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE2_CLOCK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_CLOCK_OFFSET 0x18 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */ -#define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */ - -#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */ -#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos) -#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))) -#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */ -#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos) -#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))) -#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */ -#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos) -#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))) -#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */ -#define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos) -#define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))) -#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */ -#define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos) -#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))) -#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */ -#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos) -#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))) -#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */ - -/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER:16; /*!< bit: 0..15 Counter Period */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_PER_OFFSET 0x1C /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */ -#define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */ - -#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */ -#define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos) -#define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))) -#define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */ - -/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE0_COMP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_COMP_OFFSET 0x20 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */ -#define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */ - -#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */ -#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos) -#define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))) -#define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */ - -/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_COMP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_COMP_OFFSET 0x20 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */ -#define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */ - -#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */ -#define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos) -#define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))) -#define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */ - -/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE2_ALARM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_ALARM_OFFSET 0x20 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ -#define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ - -#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ -#define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos) -#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))) -#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ -#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos) -#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))) -#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ -#define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos) -#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))) -#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ -#define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos) -#define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))) -#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ -#define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos) -#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))) -#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ -#define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos) -#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))) -#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */ - -/* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_MASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_MASK_OFFSET 0x24 /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ -#define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ - -#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ -#define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))) -#define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ -#define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */ -#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ -#define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ -#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ -#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ -#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ -#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */ - -/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} RTC_GP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_GP_OFFSET 0x40 /**< \brief (RTC_GP offset) General Purpose */ -#define RTC_GP_RESETVALUE 0x00000000ul /**< \brief (RTC_GP reset_value) General Purpose */ -#define RTC_GP_MASK 0xFFFFFFFFul /**< \brief (RTC_GP) MASK Register */ - -/** \brief RtcMode2Alarm hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ - __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ - RoReg8 Reserved1[0x3]; -} RtcMode2Alarm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE0 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 32-bit Counter with Single 32-bit Compare */ - __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */ - RoReg8 Reserved1[0x2]; - __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */ - __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */ - __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */ - __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __I RTC_MODE0_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ - RoReg8 Reserved3[0x3]; - __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */ - RoReg8 Reserved4[0x4]; - __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */ - RoReg8 Reserved5[0x1C]; - __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ -} RtcMode0; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE1 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 16-bit Counter with Two 16-bit Compares */ - __IO RTC_MODE1_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */ - RoReg8 Reserved1[0x2]; - __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */ - __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */ - __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */ - __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __I RTC_MODE1_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ - RoReg8 Reserved3[0x3]; - __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */ - RoReg8 Reserved4[0x2]; - __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */ - RoReg8 Reserved5[0x2]; - __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */ - RoReg8 Reserved6[0x1C]; - __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ -} RtcMode1; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE2 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* Clock/Calendar with Alarm */ - __IO RTC_MODE2_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */ - RoReg8 Reserved1[0x2]; - __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */ - __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */ - __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */ - __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __I RTC_MODE2_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ - RoReg8 Reserved3[0x3]; - __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */ - RoReg8 Reserved4[0x4]; - RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [ALARM_NUM] */ - RoReg8 Reserved5[0x18]; - __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ -} RtcMode2; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ - RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ - RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ -} Rtc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_RTC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_sercom.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_sercom.h deleted file mode 100644 index 07d03daf143..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_sercom.h +++ /dev/null @@ -1,1463 +0,0 @@ -/** - * \file - * - * \brief Component description for SERCOM - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SERCOM_COMPONENT_ -#define _SAML21_SERCOM_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR SERCOM */ -/* ========================================================================== */ -/** \addtogroup SAML21_SERCOM Serial Communication Interface */ -/*@{*/ - -#define SERCOM_U2201 -#define REV_SERCOM 0x220 - -/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ -#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ - -#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ -#define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos) -#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ -#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ -#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))) -#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ -#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) -#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ -#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos) -#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ -#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) -#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))) -#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ -#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) -#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) -#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ -#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos) -#define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))) -#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ -#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos) -#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ -#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos) -#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))) -#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ -#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) -#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ - -/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ -#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ - -#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ -#define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos) -#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ -#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ -#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))) -#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ -#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) -#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ -#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos) -#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ -#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) -#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))) -#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) -#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ -#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos) -#define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))) -#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ -#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos) -#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ -#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) -#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ - -/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ -#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ - -#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ -#define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos) -#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ -#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos) -#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ -#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))) -#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ -#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) -#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ -#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos) -#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ -#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos) -#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))) -#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ -#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos) -#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))) -#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ -#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos) -#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))) -#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ -#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos) -#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ -#define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos) -#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ -#define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos) -#define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ - -/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :4; /*!< bit: 9..12 Reserved */ - uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ - uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ - uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ -#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ - -#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ -#define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos) -#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ -#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos) -#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ -#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))) -#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ -#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos) -#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ -#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos) -#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ -#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos) -#define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))) -#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ -#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos) -#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))) -#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ -#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos) -#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))) -#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ -#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos) -#define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))) -#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ -#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos) -#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))) -#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ -#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos) -#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ -#define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos) -#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ -#define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos) -#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */ - -/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ -#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ - -#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ -#define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos) -#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ -#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos) -#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ -#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos) -#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))) -#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ -#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos) -#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ - -/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ - uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ - uint32_t :3; /*!< bit: 11..13 Reserved */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ -#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ - -#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ -#define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos) -#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ -#define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos) -#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ -#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos) -#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ -#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos) -#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))) -#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ -#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos) -#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))) -#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ -#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos) -#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ - -/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ - uint32_t :2; /*!< bit: 7.. 8 Reserved */ - uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ - uint32_t :3; /*!< bit: 10..12 Reserved */ - uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ -#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ - -#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ -#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos) -#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))) -#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ -#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos) -#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ -#define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos) -#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ -#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos) -#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ -#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos) -#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))) -#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ -#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos) -#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ - -/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ - uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ - uint32_t ENC:1; /*!< bit: 10 Encoding Format */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ -#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ - -#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ -#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos) -#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))) -#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ -#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos) -#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ -#define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos) -#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ -#define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos) -#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ -#define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos) -#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ -#define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos) -#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ -#define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos) -#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ -#define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos) -#define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */ - -/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ - uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ - uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ -#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ - -#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ -#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos) -#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))) -#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ -#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos) -#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))) -#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ -#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos) -#define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))) -#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ -#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) -#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))) -#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ - -/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ -#define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ - -#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ -#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos) -#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))) -#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */ - -/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - struct { // FRAC mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRAC; /*!< Structure used for FRAC */ - struct { // FRACFP mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRACFP; /*!< Structure used for FRACFP */ - struct { // USARTFP mode - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } USARTFP; /*!< Structure used for USARTFP */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ -#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ - -#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ -#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos) -#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))) -#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */ - -// FRAC mode -#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ -#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos) -#define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))) -#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ -#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos) -#define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))) -#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ - -// FRACFP mode -#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ -#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) -#define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))) -#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ -#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos) -#define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))) -#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ - -// USARTFP mode -#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ -#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) -#define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))) -#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ - -/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_RXPL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ -#define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ - -#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ -#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos) -#define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))) -#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */ - -/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ -#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ - -#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos) -#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos) -#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos) -#define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ - -/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ -#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ - -#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos) -#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos) -#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos) -#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos) -#define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ - -/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ -#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ - -#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos) -#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos) -#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos) -#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos) -#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos) -#define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ - -/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ -#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ - -#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ -#define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos) -#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ -#define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos) -#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos) -#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos) -#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ -#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos) -#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos) -#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos) -#define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ - -/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ -#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ - -#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos) -#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos) -#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos) -#define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ - -/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ -#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ - -#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos) -#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos) -#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos) -#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos) -#define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ - -/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ -#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ - -#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ -#define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos) -#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ -#define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos) -#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ -#define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos) -#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ -#define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos) -#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos) -#define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ - -/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ -#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ - -#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ -#define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos) -#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ -#define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos) -#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos) -#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos) -#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ -#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos) -#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos) -#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos) -#define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */ - -/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ -#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ - -#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ -#define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos) -#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ -#define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos) -#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ -#define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos) -#define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ - -/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ -#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ - -#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ -#define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos) -#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ -#define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos) -#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ -#define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos) -#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ -#define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos) -#define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ - -/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ -#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ - -#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ -#define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos) -#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ -#define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos) -#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ -#define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos) -#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ -#define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos) -#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ -#define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos) -#define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ - -/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ -#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ - -#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ -#define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos) -#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ -#define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos) -#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ -#define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos) -#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ -#define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos) -#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ -#define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos) -#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ -#define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos) -#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ -#define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos) -#define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ - -/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t LENERR:1; /*!< bit: 10 Length Error */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ -#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ - -#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ -#define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos) -#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ -#define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos) -#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ -#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos) -#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ -#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos) -#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))) -#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ -#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos) -#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ -#define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos) -#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ -#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) -#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) -#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ -#define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos) -#define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ - -/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ - uint16_t SR:1; /*!< bit: 4 Repeated Start */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t :1; /*!< bit: 8 Reserved */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t HS:1; /*!< bit: 10 High Speed */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ -#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ - -#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ -#define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos) -#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ -#define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos) -#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ -#define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos) -#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ -#define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos) -#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ -#define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos) -#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ -#define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos) -#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ -#define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos) -#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) -#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ -#define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos) -#define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ - -/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t :13; /*!< bit: 3..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_SPI_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ -#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ - -#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ -#define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos) -#define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */ - -/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PERR:1; /*!< bit: 0 Parity Error */ - uint16_t FERR:1; /*!< bit: 1 Frame Error */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t CTS:1; /*!< bit: 3 Clear To Send */ - uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ - uint16_t COLL:1; /*!< bit: 5 Collision Detected */ - uint16_t :10; /*!< bit: 6..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ -#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ - -#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ -#define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos) -#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ -#define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos) -#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ -#define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos) -#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ -#define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos) -#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ -#define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos) -#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ -#define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos) -#define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */ - -/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */ - -#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) -#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) -#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) -#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */ -#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */ - -#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) -#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) -#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */ - -#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos) -#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) -#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) -#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */ - -#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos) -#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos) -#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos) -#define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t LENEN:1; /*!< bit: 13 Length Enable */ - uint32_t HS:1; /*!< bit: 14 High Speed Mode */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t LEN:8; /*!< bit: 16..23 Length */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ -#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ - -#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ -#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos) -#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))) -#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ -#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos) -#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ -#define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos) -#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ -#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos) -#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ -#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos) -#define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))) -#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ - -/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ - uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ - uint32_t :4; /*!< bit: 11..14 Reserved */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ -#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ - -#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ -#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos) -#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ -#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos) -#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))) -#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ -#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos) -#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ -#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos) -#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))) -#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ - -/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ -#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ - -#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ -#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos) -#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))) -#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ -#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos) -#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))) -#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */ - -/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ -#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ - -#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ -#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos) -#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))) -#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */ - -/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ -#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ - -#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ -#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos) -#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))) -#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */ - -/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint32_t :23; /*!< bit: 9..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ -#define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ - -#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ -#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos) -#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))) -#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */ - -/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ -#define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ - -#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ -#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos) -#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))) -#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */ - -/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ -#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ - -#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ -#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ - -/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ -#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ - -#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ -#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ - -/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ -#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ - -#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ -#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ - -/** \brief SERCOM_I2CM hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* I2C Master Mode */ - __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ - __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ - RoReg8 Reserved2[0x4]; - __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ - __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ - __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ - RoReg8 Reserved7[0x7]; - __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ -} SercomI2cm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_I2CS hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* I2C Slave Mode */ - __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ - __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ - RoReg8 Reserved1[0xC]; - __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ - RoReg8 Reserved2[0x1]; - __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ - __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */ - RoReg8 Reserved5[0x4]; - __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ - __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ -} SercomI2cs; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_SPI hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* SPI Mode */ - __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ - __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ - RoReg8 Reserved2[0x7]; - __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ - __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ - __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ - RoReg8 Reserved7[0x4]; - __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ -} SercomSpi; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_USART hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USART Mode */ - __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ - __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ - __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ - RoReg8 Reserved2[0x5]; - __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ - __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */ - RoReg8 Reserved6[0x8]; - __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ - RoReg8 Reserved7[0x6]; - __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ -} SercomUsart; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ - SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ - SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ - SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ -} Sercom; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_SERCOM_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_supc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_supc.h deleted file mode 100644 index f19e209e6cb..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_supc.h +++ /dev/null @@ -1,614 +0,0 @@ -/** - * \file - * - * \brief Component description for SUPC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SUPC_COMPONENT_ -#define _SAML21_SUPC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR SUPC */ -/* ========================================================================== */ -/** \addtogroup SAML21_SUPC Supply Controller */ -/*@{*/ - -#define SUPC_U2117 -#define REV_SUPC 0x110 - -/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ - uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ - uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ - uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ - uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ - uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ - uint32_t :21; /*!< bit: 11..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */ -#define SUPC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define SUPC_INTENCLR_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENCLR) BOD33 Ready */ -#define SUPC_INTENCLR_BOD33RDY (0x1ul << SUPC_INTENCLR_BOD33RDY_Pos) -#define SUPC_INTENCLR_BOD33DET_Pos 1 /**< \brief (SUPC_INTENCLR) BOD33 Detection */ -#define SUPC_INTENCLR_BOD33DET (0x1ul << SUPC_INTENCLR_BOD33DET_Pos) -#define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */ -#define SUPC_INTENCLR_B33SRDY (0x1ul << SUPC_INTENCLR_B33SRDY_Pos) -#define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */ -#define SUPC_INTENCLR_BOD12RDY (0x1ul << SUPC_INTENCLR_BOD12RDY_Pos) -#define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */ -#define SUPC_INTENCLR_BOD12DET (0x1ul << SUPC_INTENCLR_BOD12DET_Pos) -#define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */ -#define SUPC_INTENCLR_B12SRDY (0x1ul << SUPC_INTENCLR_B12SRDY_Pos) -#define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */ -#define SUPC_INTENCLR_VREGRDY (0x1ul << SUPC_INTENCLR_VREGRDY_Pos) -#define SUPC_INTENCLR_APWSRDY_Pos 9 /**< \brief (SUPC_INTENCLR) Automatic Power Switch Ready */ -#define SUPC_INTENCLR_APWSRDY (0x1ul << SUPC_INTENCLR_APWSRDY_Pos) -#define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */ -#define SUPC_INTENCLR_VCORERDY (0x1ul << SUPC_INTENCLR_VCORERDY_Pos) -#define SUPC_INTENCLR_MASK 0x0000073Ful /**< \brief (SUPC_INTENCLR) MASK Register */ - -/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ - uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ - uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ - uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ - uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ - uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ - uint32_t :21; /*!< bit: 11..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */ -#define SUPC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */ - -#define SUPC_INTENSET_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENSET) BOD33 Ready */ -#define SUPC_INTENSET_BOD33RDY (0x1ul << SUPC_INTENSET_BOD33RDY_Pos) -#define SUPC_INTENSET_BOD33DET_Pos 1 /**< \brief (SUPC_INTENSET) BOD33 Detection */ -#define SUPC_INTENSET_BOD33DET (0x1ul << SUPC_INTENSET_BOD33DET_Pos) -#define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */ -#define SUPC_INTENSET_B33SRDY (0x1ul << SUPC_INTENSET_B33SRDY_Pos) -#define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */ -#define SUPC_INTENSET_BOD12RDY (0x1ul << SUPC_INTENSET_BOD12RDY_Pos) -#define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */ -#define SUPC_INTENSET_BOD12DET (0x1ul << SUPC_INTENSET_BOD12DET_Pos) -#define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */ -#define SUPC_INTENSET_B12SRDY (0x1ul << SUPC_INTENSET_B12SRDY_Pos) -#define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */ -#define SUPC_INTENSET_VREGRDY (0x1ul << SUPC_INTENSET_VREGRDY_Pos) -#define SUPC_INTENSET_APWSRDY_Pos 9 /**< \brief (SUPC_INTENSET) Automatic Power Switch Ready */ -#define SUPC_INTENSET_APWSRDY (0x1ul << SUPC_INTENSET_APWSRDY_Pos) -#define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */ -#define SUPC_INTENSET_VCORERDY (0x1ul << SUPC_INTENSET_VCORERDY_Pos) -#define SUPC_INTENSET_MASK 0x0000073Ful /**< \brief (SUPC_INTENSET) MASK Register */ - -/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ - uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ - uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ - uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ - uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ - uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ - uint32_t :21; /*!< bit: 11..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define SUPC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define SUPC_INTFLAG_BOD33RDY_Pos 0 /**< \brief (SUPC_INTFLAG) BOD33 Ready */ -#define SUPC_INTFLAG_BOD33RDY (0x1ul << SUPC_INTFLAG_BOD33RDY_Pos) -#define SUPC_INTFLAG_BOD33DET_Pos 1 /**< \brief (SUPC_INTFLAG) BOD33 Detection */ -#define SUPC_INTFLAG_BOD33DET (0x1ul << SUPC_INTFLAG_BOD33DET_Pos) -#define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */ -#define SUPC_INTFLAG_B33SRDY (0x1ul << SUPC_INTFLAG_B33SRDY_Pos) -#define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */ -#define SUPC_INTFLAG_BOD12RDY (0x1ul << SUPC_INTFLAG_BOD12RDY_Pos) -#define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */ -#define SUPC_INTFLAG_BOD12DET (0x1ul << SUPC_INTFLAG_BOD12DET_Pos) -#define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */ -#define SUPC_INTFLAG_B12SRDY (0x1ul << SUPC_INTFLAG_B12SRDY_Pos) -#define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */ -#define SUPC_INTFLAG_VREGRDY (0x1ul << SUPC_INTFLAG_VREGRDY_Pos) -#define SUPC_INTFLAG_APWSRDY_Pos 9 /**< \brief (SUPC_INTFLAG) Automatic Power Switch Ready */ -#define SUPC_INTFLAG_APWSRDY (0x1ul << SUPC_INTFLAG_APWSRDY_Pos) -#define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */ -#define SUPC_INTFLAG_VCORERDY (0x1ul << SUPC_INTFLAG_VCORERDY_Pos) -#define SUPC_INTFLAG_MASK 0x0000073Ful /**< \brief (SUPC_INTFLAG) MASK Register */ - -/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ - uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ - uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ - uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ - uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ - uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ - uint32_t BBPS:1; /*!< bit: 11 Battery Backup Power Switch */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */ -#define SUPC_STATUS_RESETVALUE 0x00000000ul /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */ - -#define SUPC_STATUS_BOD33RDY_Pos 0 /**< \brief (SUPC_STATUS) BOD33 Ready */ -#define SUPC_STATUS_BOD33RDY (0x1ul << SUPC_STATUS_BOD33RDY_Pos) -#define SUPC_STATUS_BOD33DET_Pos 1 /**< \brief (SUPC_STATUS) BOD33 Detection */ -#define SUPC_STATUS_BOD33DET (0x1ul << SUPC_STATUS_BOD33DET_Pos) -#define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */ -#define SUPC_STATUS_B33SRDY (0x1ul << SUPC_STATUS_B33SRDY_Pos) -#define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */ -#define SUPC_STATUS_BOD12RDY (0x1ul << SUPC_STATUS_BOD12RDY_Pos) -#define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */ -#define SUPC_STATUS_BOD12DET (0x1ul << SUPC_STATUS_BOD12DET_Pos) -#define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */ -#define SUPC_STATUS_B12SRDY (0x1ul << SUPC_STATUS_B12SRDY_Pos) -#define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */ -#define SUPC_STATUS_VREGRDY (0x1ul << SUPC_STATUS_VREGRDY_Pos) -#define SUPC_STATUS_APWSRDY_Pos 9 /**< \brief (SUPC_STATUS) Automatic Power Switch Ready */ -#define SUPC_STATUS_APWSRDY (0x1ul << SUPC_STATUS_APWSRDY_Pos) -#define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */ -#define SUPC_STATUS_VCORERDY (0x1ul << SUPC_STATUS_VCORERDY_Pos) -#define SUPC_STATUS_BBPS_Pos 11 /**< \brief (SUPC_STATUS) Battery Backup Power Switch */ -#define SUPC_STATUS_BBPS (0x1ul << SUPC_STATUS_BBPS_Pos) -#define SUPC_STATUS_MASK 0x00000F3Ful /**< \brief (SUPC_STATUS) MASK Register */ - -/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ - uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ - uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint32_t RUNBKUP:1; /*!< bit: 7 Configuration in Backup mode */ - uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ - uint32_t :1; /*!< bit: 9 Reserved */ - uint32_t VMON:1; /*!< bit: 10 Voltage Monitored in active and standby mode */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ - uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level for VDD */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t BKUPLEVEL:6; /*!< bit: 24..29 Threshold Level in backup sleep mode or for VBAT */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_BOD33_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_BOD33_OFFSET 0x10 /**< \brief (SUPC_BOD33 offset) BOD33 Control */ -#define SUPC_BOD33_RESETVALUE 0x00000000ul /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */ - -#define SUPC_BOD33_ENABLE_Pos 1 /**< \brief (SUPC_BOD33) Enable */ -#define SUPC_BOD33_ENABLE (0x1ul << SUPC_BOD33_ENABLE_Pos) -#define SUPC_BOD33_HYST_Pos 2 /**< \brief (SUPC_BOD33) Hysteresis Enable */ -#define SUPC_BOD33_HYST (0x1ul << SUPC_BOD33_HYST_Pos) -#define SUPC_BOD33_ACTION_Pos 3 /**< \brief (SUPC_BOD33) Action when Threshold Crossed */ -#define SUPC_BOD33_ACTION_Msk (0x3ul << SUPC_BOD33_ACTION_Pos) -#define SUPC_BOD33_ACTION(value) ((SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))) -#define SUPC_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SUPC_BOD33) No action */ -#define SUPC_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SUPC_BOD33) The BOD33 generates a reset */ -#define SUPC_BOD33_ACTION_INT_Val 0x2ul /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */ -#define SUPC_BOD33_ACTION_BKUP_Val 0x3ul /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode if VMON=0 */ -#define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos) -#define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos) -#define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos) -#define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos) -#define SUPC_BOD33_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD33) Configuration in Standby mode */ -#define SUPC_BOD33_STDBYCFG (0x1ul << SUPC_BOD33_STDBYCFG_Pos) -#define SUPC_BOD33_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD33) Run during Standby */ -#define SUPC_BOD33_RUNSTDBY (0x1ul << SUPC_BOD33_RUNSTDBY_Pos) -#define SUPC_BOD33_RUNBKUP_Pos 7 /**< \brief (SUPC_BOD33) Configuration in Backup mode */ -#define SUPC_BOD33_RUNBKUP (0x1ul << SUPC_BOD33_RUNBKUP_Pos) -#define SUPC_BOD33_ACTCFG_Pos 8 /**< \brief (SUPC_BOD33) Configuration in Active mode */ -#define SUPC_BOD33_ACTCFG (0x1ul << SUPC_BOD33_ACTCFG_Pos) -#define SUPC_BOD33_VMON_Pos 10 /**< \brief (SUPC_BOD33) Voltage Monitored in active and standby mode */ -#define SUPC_BOD33_VMON (0x1ul << SUPC_BOD33_VMON_Pos) -#define SUPC_BOD33_PSEL_Pos 12 /**< \brief (SUPC_BOD33) Prescaler Select */ -#define SUPC_BOD33_PSEL_Msk (0xFul << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL(value) ((SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))) -#define SUPC_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SUPC_BOD33) Divide clock by 2 */ -#define SUPC_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SUPC_BOD33) Divide clock by 4 */ -#define SUPC_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SUPC_BOD33) Divide clock by 8 */ -#define SUPC_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SUPC_BOD33) Divide clock by 16 */ -#define SUPC_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SUPC_BOD33) Divide clock by 32 */ -#define SUPC_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SUPC_BOD33) Divide clock by 64 */ -#define SUPC_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SUPC_BOD33) Divide clock by 128 */ -#define SUPC_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SUPC_BOD33) Divide clock by 256 */ -#define SUPC_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SUPC_BOD33) Divide clock by 512 */ -#define SUPC_BOD33_PSEL_DIV1024_Val 0x9ul /**< \brief (SUPC_BOD33) Divide clock by 1024 */ -#define SUPC_BOD33_PSEL_DIV2048_Val 0xAul /**< \brief (SUPC_BOD33) Divide clock by 2048 */ -#define SUPC_BOD33_PSEL_DIV4096_Val 0xBul /**< \brief (SUPC_BOD33) Divide clock by 4096 */ -#define SUPC_BOD33_PSEL_DIV8192_Val 0xCul /**< \brief (SUPC_BOD33) Divide clock by 8192 */ -#define SUPC_BOD33_PSEL_DIV16384_Val 0xDul /**< \brief (SUPC_BOD33) Divide clock by 16384 */ -#define SUPC_BOD33_PSEL_DIV32768_Val 0xEul /**< \brief (SUPC_BOD33) Divide clock by 32768 */ -#define SUPC_BOD33_PSEL_DIV65536_Val 0xFul /**< \brief (SUPC_BOD33) Divide clock by 65536 */ -#define SUPC_BOD33_PSEL_DIV2 (SUPC_BOD33_PSEL_DIV2_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV512 (SUPC_BOD33_PSEL_DIV512_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV1024 (SUPC_BOD33_PSEL_DIV1024_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV2048 (SUPC_BOD33_PSEL_DIV2048_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV4096 (SUPC_BOD33_PSEL_DIV4096_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV8192 (SUPC_BOD33_PSEL_DIV8192_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV16384 (SUPC_BOD33_PSEL_DIV16384_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV32768 (SUPC_BOD33_PSEL_DIV32768_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_PSEL_DIV65536 (SUPC_BOD33_PSEL_DIV65536_Val << SUPC_BOD33_PSEL_Pos) -#define SUPC_BOD33_LEVEL_Pos 16 /**< \brief (SUPC_BOD33) Threshold Level for VDD */ -#define SUPC_BOD33_LEVEL_Msk (0x3Ful << SUPC_BOD33_LEVEL_Pos) -#define SUPC_BOD33_LEVEL(value) ((SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))) -#define SUPC_BOD33_BKUPLEVEL_Pos 24 /**< \brief (SUPC_BOD33) Threshold Level in backup sleep mode or for VBAT */ -#define SUPC_BOD33_BKUPLEVEL_Msk (0x3Ful << SUPC_BOD33_BKUPLEVEL_Pos) -#define SUPC_BOD33_BKUPLEVEL(value) ((SUPC_BOD33_BKUPLEVEL_Msk & ((value) << SUPC_BOD33_BKUPLEVEL_Pos))) -#define SUPC_BOD33_MASK 0x3F3FF5FEul /**< \brief (SUPC_BOD33) MASK Register */ - -/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ - uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ - uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ - uint32_t :3; /*!< bit: 9..11 Reserved */ - uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ - uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_BOD12_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */ -#define SUPC_BOD12_RESETVALUE 0x00000000ul /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */ - -#define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */ -#define SUPC_BOD12_ENABLE (0x1ul << SUPC_BOD12_ENABLE_Pos) -#define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */ -#define SUPC_BOD12_HYST (0x1ul << SUPC_BOD12_HYST_Pos) -#define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */ -#define SUPC_BOD12_ACTION_Msk (0x3ul << SUPC_BOD12_ACTION_Pos) -#define SUPC_BOD12_ACTION(value) ((SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))) -#define SUPC_BOD12_ACTION_NONE_Val 0x0ul /**< \brief (SUPC_BOD12) No action */ -#define SUPC_BOD12_ACTION_RESET_Val 0x1ul /**< \brief (SUPC_BOD12) The BOD12 generates a reset */ -#define SUPC_BOD12_ACTION_INT_Val 0x2ul /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */ -#define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos) -#define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos) -#define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos) -#define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */ -#define SUPC_BOD12_STDBYCFG (0x1ul << SUPC_BOD12_STDBYCFG_Pos) -#define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */ -#define SUPC_BOD12_RUNSTDBY (0x1ul << SUPC_BOD12_RUNSTDBY_Pos) -#define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */ -#define SUPC_BOD12_ACTCFG (0x1ul << SUPC_BOD12_ACTCFG_Pos) -#define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */ -#define SUPC_BOD12_PSEL_Msk (0xFul << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL(value) ((SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))) -#define SUPC_BOD12_PSEL_DIV2_Val 0x0ul /**< \brief (SUPC_BOD12) Divide clock by 2 */ -#define SUPC_BOD12_PSEL_DIV4_Val 0x1ul /**< \brief (SUPC_BOD12) Divide clock by 4 */ -#define SUPC_BOD12_PSEL_DIV8_Val 0x2ul /**< \brief (SUPC_BOD12) Divide clock by 8 */ -#define SUPC_BOD12_PSEL_DIV16_Val 0x3ul /**< \brief (SUPC_BOD12) Divide clock by 16 */ -#define SUPC_BOD12_PSEL_DIV32_Val 0x4ul /**< \brief (SUPC_BOD12) Divide clock by 32 */ -#define SUPC_BOD12_PSEL_DIV64_Val 0x5ul /**< \brief (SUPC_BOD12) Divide clock by 64 */ -#define SUPC_BOD12_PSEL_DIV128_Val 0x6ul /**< \brief (SUPC_BOD12) Divide clock by 128 */ -#define SUPC_BOD12_PSEL_DIV256_Val 0x7ul /**< \brief (SUPC_BOD12) Divide clock by 256 */ -#define SUPC_BOD12_PSEL_DIV512_Val 0x8ul /**< \brief (SUPC_BOD12) Divide clock by 512 */ -#define SUPC_BOD12_PSEL_DIV1024_Val 0x9ul /**< \brief (SUPC_BOD12) Divide clock by 1024 */ -#define SUPC_BOD12_PSEL_DIV2048_Val 0xAul /**< \brief (SUPC_BOD12) Divide clock by 2048 */ -#define SUPC_BOD12_PSEL_DIV4096_Val 0xBul /**< \brief (SUPC_BOD12) Divide clock by 4096 */ -#define SUPC_BOD12_PSEL_DIV8192_Val 0xCul /**< \brief (SUPC_BOD12) Divide clock by 8192 */ -#define SUPC_BOD12_PSEL_DIV16384_Val 0xDul /**< \brief (SUPC_BOD12) Divide clock by 16384 */ -#define SUPC_BOD12_PSEL_DIV32768_Val 0xEul /**< \brief (SUPC_BOD12) Divide clock by 32768 */ -#define SUPC_BOD12_PSEL_DIV65536_Val 0xFul /**< \brief (SUPC_BOD12) Divide clock by 65536 */ -#define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */ -#define SUPC_BOD12_LEVEL_Msk (0x3Ful << SUPC_BOD12_LEVEL_Pos) -#define SUPC_BOD12_LEVEL(value) ((SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))) -#define SUPC_BOD12_MASK 0x003FF17Eul /**< \brief (SUPC_BOD12) MASK Register */ - -/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SEL:2; /*!< bit: 2.. 3 Voltage Regulator Selection in active mode */ - uint32_t :2; /*!< bit: 4.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t LPEFF:1; /*!< bit: 8 Low Power Efficiency */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t VSVSTEP:4; /*!< bit: 16..19 Voltage Scaling Voltage Step */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t VSPER:8; /*!< bit: 24..31 Voltage Scaling Period */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_VREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */ -#define SUPC_VREG_RESETVALUE 0x00000000ul /**< \brief (SUPC_VREG reset_value) VREG Control */ - -#define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */ -#define SUPC_VREG_ENABLE (0x1ul << SUPC_VREG_ENABLE_Pos) -#define SUPC_VREG_SEL_Pos 2 /**< \brief (SUPC_VREG) Voltage Regulator Selection in active mode */ -#define SUPC_VREG_SEL_Msk (0x3ul << SUPC_VREG_SEL_Pos) -#define SUPC_VREG_SEL(value) ((SUPC_VREG_SEL_Msk & ((value) << SUPC_VREG_SEL_Pos))) -#define SUPC_VREG_SEL_LDO_Val 0x0ul /**< \brief (SUPC_VREG) LDO selection */ -#define SUPC_VREG_SEL_BUCK_Val 0x1ul /**< \brief (SUPC_VREG) Buck selection */ -#define SUPC_VREG_SEL_SCVREG_Val 0x2ul /**< \brief (SUPC_VREG) Switched Cap selection */ -#define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos) -#define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos) -#define SUPC_VREG_SEL_SCVREG (SUPC_VREG_SEL_SCVREG_Val << SUPC_VREG_SEL_Pos) -#define SUPC_VREG_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREG) Run during Standby */ -#define SUPC_VREG_RUNSTDBY (0x1ul << SUPC_VREG_RUNSTDBY_Pos) -#define SUPC_VREG_LPEFF_Pos 8 /**< \brief (SUPC_VREG) Low Power Efficiency */ -#define SUPC_VREG_LPEFF (0x1ul << SUPC_VREG_LPEFF_Pos) -#define SUPC_VREG_VSVSTEP_Pos 16 /**< \brief (SUPC_VREG) Voltage Scaling Voltage Step */ -#define SUPC_VREG_VSVSTEP_Msk (0xFul << SUPC_VREG_VSVSTEP_Pos) -#define SUPC_VREG_VSVSTEP(value) ((SUPC_VREG_VSVSTEP_Msk & ((value) << SUPC_VREG_VSVSTEP_Pos))) -#define SUPC_VREG_VSPER_Pos 24 /**< \brief (SUPC_VREG) Voltage Scaling Period */ -#define SUPC_VREG_VSPER_Msk (0xFFul << SUPC_VREG_VSPER_Pos) -#define SUPC_VREG_VSPER(value) ((SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))) -#define SUPC_VREG_MASK 0xFF0F014Eul /**< \brief (SUPC_VREG) MASK Register */ - -/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */ - uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_VREF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */ -#define SUPC_VREF_RESETVALUE 0x00000000ul /**< \brief (SUPC_VREF reset_value) VREF Control */ - -#define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */ -#define SUPC_VREF_TSEN (0x1ul << SUPC_VREF_TSEN_Pos) -#define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */ -#define SUPC_VREF_VREFOE (0x1ul << SUPC_VREF_VREFOE_Pos) -#define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */ -#define SUPC_VREF_RUNSTDBY (0x1ul << SUPC_VREF_RUNSTDBY_Pos) -#define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */ -#define SUPC_VREF_ONDEMAND (0x1ul << SUPC_VREF_ONDEMAND_Pos) -#define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */ -#define SUPC_VREF_SEL_Msk (0xFul << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_SEL(value) ((SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))) -#define SUPC_VREF_SEL_1V0_Val 0x0ul /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */ -#define SUPC_VREF_SEL_1V1_Val 0x1ul /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */ -#define SUPC_VREF_SEL_1V2_Val 0x2ul /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */ -#define SUPC_VREF_SEL_1V25_Val 0x3ul /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */ -#define SUPC_VREF_SEL_2V0_Val 0x4ul /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */ -#define SUPC_VREF_SEL_2V2_Val 0x5ul /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */ -#define SUPC_VREF_SEL_2V4_Val 0x6ul /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */ -#define SUPC_VREF_SEL_2V5_Val 0x7ul /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */ -#define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos) -#define SUPC_VREF_MASK 0x000F00C6ul /**< \brief (SUPC_VREF) MASK Register */ - -/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CONF:2; /*!< bit: 0.. 1 Battery Backup Configuration */ - uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */ - uint32_t PSOKEN:1; /*!< bit: 3 Power Supply OK Enable */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_BBPS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_BBPS_OFFSET 0x20 /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */ -#define SUPC_BBPS_RESETVALUE 0x00000000ul /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */ - -#define SUPC_BBPS_CONF_Pos 0 /**< \brief (SUPC_BBPS) Battery Backup Configuration */ -#define SUPC_BBPS_CONF_Msk (0x3ul << SUPC_BBPS_CONF_Pos) -#define SUPC_BBPS_CONF(value) ((SUPC_BBPS_CONF_Msk & ((value) << SUPC_BBPS_CONF_Pos))) -#define SUPC_BBPS_CONF_NONE_Val 0x0ul /**< \brief (SUPC_BBPS) The backup domain is always supplied by main power */ -#define SUPC_BBPS_CONF_APWS_Val 0x1ul /**< \brief (SUPC_BBPS) The power switch is handled by the automatic power switch */ -#define SUPC_BBPS_CONF_FORCED_Val 0x2ul /**< \brief (SUPC_BBPS) The backup domain is always supplied by battery backup power */ -#define SUPC_BBPS_CONF_BOD33_Val 0x3ul /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */ -#define SUPC_BBPS_CONF_NONE (SUPC_BBPS_CONF_NONE_Val << SUPC_BBPS_CONF_Pos) -#define SUPC_BBPS_CONF_APWS (SUPC_BBPS_CONF_APWS_Val << SUPC_BBPS_CONF_Pos) -#define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos) -#define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos) -#define SUPC_BBPS_WAKEEN_Pos 2 /**< \brief (SUPC_BBPS) Wake Enable */ -#define SUPC_BBPS_WAKEEN (0x1ul << SUPC_BBPS_WAKEEN_Pos) -#define SUPC_BBPS_PSOKEN_Pos 3 /**< \brief (SUPC_BBPS) Power Supply OK Enable */ -#define SUPC_BBPS_PSOKEN (0x1ul << SUPC_BBPS_PSOKEN_Pos) -#define SUPC_BBPS_MASK 0x0000000Ful /**< \brief (SUPC_BBPS) MASK Register */ - -/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t SET:2; /*!< bit: 16..17 Set Output */ - uint32_t :6; /*!< bit: 18..23 Reserved */ - uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_BKOUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_BKOUT_OFFSET 0x24 /**< \brief (SUPC_BKOUT offset) Backup Output Control */ -#define SUPC_BKOUT_RESETVALUE 0x00000000ul /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */ - -#define SUPC_BKOUT_EN_Pos 0 /**< \brief (SUPC_BKOUT) Enable Output */ -#define SUPC_BKOUT_EN_Msk (0x3ul << SUPC_BKOUT_EN_Pos) -#define SUPC_BKOUT_EN(value) ((SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))) -#define SUPC_BKOUT_CLR_Pos 8 /**< \brief (SUPC_BKOUT) Clear Output */ -#define SUPC_BKOUT_CLR_Msk (0x3ul << SUPC_BKOUT_CLR_Pos) -#define SUPC_BKOUT_CLR(value) ((SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))) -#define SUPC_BKOUT_SET_Pos 16 /**< \brief (SUPC_BKOUT) Set Output */ -#define SUPC_BKOUT_SET_Msk (0x3ul << SUPC_BKOUT_SET_Pos) -#define SUPC_BKOUT_SET(value) ((SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))) -#define SUPC_BKOUT_RTCTGL_Pos 24 /**< \brief (SUPC_BKOUT) RTC Toggle Output */ -#define SUPC_BKOUT_RTCTGL_Msk (0x3ul << SUPC_BKOUT_RTCTGL_Pos) -#define SUPC_BKOUT_RTCTGL(value) ((SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))) -#define SUPC_BKOUT_MASK 0x03030303ul /**< \brief (SUPC_BKOUT) MASK Register */ - -/* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/ 32) Backup Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_BKIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_BKIN_OFFSET 0x28 /**< \brief (SUPC_BKIN offset) Backup Input Control */ -#define SUPC_BKIN_RESETVALUE 0x00000000ul /**< \brief (SUPC_BKIN reset_value) Backup Input Control */ - -#define SUPC_BKIN_BKIN_Pos 0 /**< \brief (SUPC_BKIN) Backup Input Value */ -#define SUPC_BKIN_BKIN_Msk (0xFFul << SUPC_BKIN_BKIN_Pos) -#define SUPC_BKIN_BKIN(value) ((SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))) -#define SUPC_BKIN_MASK 0x000000FFul /**< \brief (SUPC_BKIN) MASK Register */ - -/** \brief SUPC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ - __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ - __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ - __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ - __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */ - __IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */ - __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ - __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ - __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */ - __IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */ - __I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */ -} Supc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_SUPC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tal.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tal.h deleted file mode 100644 index c6e7610305f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tal.h +++ /dev/null @@ -1,883 +0,0 @@ -/** - * \file - * - * \brief Component description for TAL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TAL_COMPONENT_ -#define _SAML21_TAL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TAL */ -/* ========================================================================== */ -/** \addtogroup SAML21_TAL Trigger Allocator */ -/*@{*/ - -#define TAL_U2253 -#define REV_TAL 0x102 - -/* -------- TAL_CTRLA : (TAL Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_CTRLA_OFFSET 0x00 /**< \brief (TAL_CTRLA offset) Control A */ -#define TAL_CTRLA_RESETVALUE 0x00ul /**< \brief (TAL_CTRLA reset_value) Control A */ - -#define TAL_CTRLA_SWRST_Pos 0 /**< \brief (TAL_CTRLA) Software Reset */ -#define TAL_CTRLA_SWRST (0x1ul << TAL_CTRLA_SWRST_Pos) -#define TAL_CTRLA_ENABLE_Pos 1 /**< \brief (TAL_CTRLA) Enable */ -#define TAL_CTRLA_ENABLE (0x1ul << TAL_CTRLA_ENABLE_Pos) -#define TAL_CTRLA_MASK 0x03ul /**< \brief (TAL_CTRLA) MASK Register */ - -/* -------- TAL_RSTCTRL : (TAL Offset: 0x04) (R/W 8) Reset Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint8_t reg; /*!< Type used for register access */ -} TAL_RSTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_RSTCTRL_OFFSET 0x04 /**< \brief (TAL_RSTCTRL offset) Reset Control */ -#define TAL_RSTCTRL_RESETVALUE 0x00ul /**< \brief (TAL_RSTCTRL reset_value) Reset Control */ -#define TAL_RSTCTRL_MASK 0x00ul /**< \brief (TAL_RSTCTRL) MASK Register */ - -/* -------- TAL_EXTCTRL : (TAL Offset: 0x05) (R/W 8) External Break Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENABLE:1; /*!< bit: 0 Enable BRK Pin */ - uint8_t INV:1; /*!< bit: 1 Invert BRK Pin */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_EXTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_EXTCTRL_OFFSET 0x05 /**< \brief (TAL_EXTCTRL offset) External Break Control */ -#define TAL_EXTCTRL_RESETVALUE 0x00ul /**< \brief (TAL_EXTCTRL reset_value) External Break Control */ - -#define TAL_EXTCTRL_ENABLE_Pos 0 /**< \brief (TAL_EXTCTRL) Enable BRK Pin */ -#define TAL_EXTCTRL_ENABLE (0x1ul << TAL_EXTCTRL_ENABLE_Pos) -#define TAL_EXTCTRL_INV_Pos 1 /**< \brief (TAL_EXTCTRL) Invert BRK Pin */ -#define TAL_EXTCTRL_INV (0x1ul << TAL_EXTCTRL_INV_Pos) -#define TAL_EXTCTRL_MASK 0x03ul /**< \brief (TAL_EXTCTRL) MASK Register */ - -/* -------- TAL_EVCTRL : (TAL Offset: 0x06) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BRKEI:1; /*!< bit: 0 Break Input Event Enable */ - uint8_t BRKEO:1; /*!< bit: 1 Break Output Event Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_EVCTRL_OFFSET 0x06 /**< \brief (TAL_EVCTRL offset) Event Control */ -#define TAL_EVCTRL_RESETVALUE 0x00ul /**< \brief (TAL_EVCTRL reset_value) Event Control */ - -#define TAL_EVCTRL_BRKEI_Pos 0 /**< \brief (TAL_EVCTRL) Break Input Event Enable */ -#define TAL_EVCTRL_BRKEI (0x1ul << TAL_EVCTRL_BRKEI_Pos) -#define TAL_EVCTRL_BRKEO_Pos 1 /**< \brief (TAL_EVCTRL) Break Output Event Enable */ -#define TAL_EVCTRL_BRKEO (0x1ul << TAL_EVCTRL_BRKEO_Pos) -#define TAL_EVCTRL_MASK 0x03ul /**< \brief (TAL_EVCTRL) MASK Register */ - -/* -------- TAL_INTENCLR : (TAL Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_INTENCLR_OFFSET 0x08 /**< \brief (TAL_INTENCLR offset) Interrupt Enable Clear */ -#define TAL_INTENCLR_RESETVALUE 0x00ul /**< \brief (TAL_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TAL_INTENCLR_BRK_Pos 0 /**< \brief (TAL_INTENCLR) Break Interrupt Enable */ -#define TAL_INTENCLR_BRK (0x1ul << TAL_INTENCLR_BRK_Pos) -#define TAL_INTENCLR_MASK 0x01ul /**< \brief (TAL_INTENCLR) MASK Register */ - -/* -------- TAL_INTENSET : (TAL Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_INTENSET_OFFSET 0x09 /**< \brief (TAL_INTENSET offset) Interrupt Enable Set */ -#define TAL_INTENSET_RESETVALUE 0x00ul /**< \brief (TAL_INTENSET reset_value) Interrupt Enable Set */ - -#define TAL_INTENSET_BRK_Pos 0 /**< \brief (TAL_INTENSET) Break Interrupt Enable */ -#define TAL_INTENSET_BRK (0x1ul << TAL_INTENSET_BRK_Pos) -#define TAL_INTENSET_MASK 0x01ul /**< \brief (TAL_INTENSET) MASK Register */ - -/* -------- TAL_INTFLAG : (TAL Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BRK:1; /*!< bit: 0 Break */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_INTFLAG_OFFSET 0x0A /**< \brief (TAL_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TAL_INTFLAG_RESETVALUE 0x00ul /**< \brief (TAL_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TAL_INTFLAG_BRK_Pos 0 /**< \brief (TAL_INTFLAG) Break */ -#define TAL_INTFLAG_BRK (0x1ul << TAL_INTFLAG_BRK_Pos) -#define TAL_INTFLAG_MASK 0x01ul /**< \brief (TAL_INTFLAG) MASK Register */ - -/* -------- TAL_GLOBMASK : (TAL Offset: 0x0B) (R/W 8) Global Break Requests Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ - uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ - uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_GLOBMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_GLOBMASK_OFFSET 0x0B /**< \brief (TAL_GLOBMASK offset) Global Break Requests Mask */ -#define TAL_GLOBMASK_RESETVALUE 0x00ul /**< \brief (TAL_GLOBMASK reset_value) Global Break Requests Mask */ - -#define TAL_GLOBMASK_CM0P_Pos 0 /**< \brief (TAL_GLOBMASK) CM0P Break Master */ -#define TAL_GLOBMASK_CM0P (0x1ul << TAL_GLOBMASK_CM0P_Pos) -#define TAL_GLOBMASK_PPP_Pos 1 /**< \brief (TAL_GLOBMASK) PPP Break Master */ -#define TAL_GLOBMASK_PPP (0x1ul << TAL_GLOBMASK_PPP_Pos) -#define TAL_GLOBMASK_EVBRK_Pos 6 /**< \brief (TAL_GLOBMASK) Event Break Master */ -#define TAL_GLOBMASK_EVBRK (0x1ul << TAL_GLOBMASK_EVBRK_Pos) -#define TAL_GLOBMASK_EXTBRK_Pos 7 /**< \brief (TAL_GLOBMASK) External Break Master */ -#define TAL_GLOBMASK_EXTBRK (0x1ul << TAL_GLOBMASK_EXTBRK_Pos) -#define TAL_GLOBMASK_MASK 0xC3ul /**< \brief (TAL_GLOBMASK) MASK Register */ - -/* -------- TAL_HALT : (TAL Offset: 0x0C) ( /W 8) Debug Halt Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ - uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ - uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_HALT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_HALT_OFFSET 0x0C /**< \brief (TAL_HALT offset) Debug Halt Request */ -#define TAL_HALT_RESETVALUE 0x00ul /**< \brief (TAL_HALT reset_value) Debug Halt Request */ - -#define TAL_HALT_CM0P_Pos 0 /**< \brief (TAL_HALT) CM0P Break Master */ -#define TAL_HALT_CM0P (0x1ul << TAL_HALT_CM0P_Pos) -#define TAL_HALT_PPP_Pos 1 /**< \brief (TAL_HALT) PPP Break Master */ -#define TAL_HALT_PPP (0x1ul << TAL_HALT_PPP_Pos) -#define TAL_HALT_EVBRK_Pos 6 /**< \brief (TAL_HALT) Event Break Master */ -#define TAL_HALT_EVBRK (0x1ul << TAL_HALT_EVBRK_Pos) -#define TAL_HALT_EXTBRK_Pos 7 /**< \brief (TAL_HALT) External Break Master */ -#define TAL_HALT_EXTBRK (0x1ul << TAL_HALT_EXTBRK_Pos) -#define TAL_HALT_MASK 0xC3ul /**< \brief (TAL_HALT) MASK Register */ - -/* -------- TAL_RESTART : (TAL Offset: 0x0D) ( /W 8) Debug Restart Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ - uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_RESTART_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_RESTART_OFFSET 0x0D /**< \brief (TAL_RESTART offset) Debug Restart Request */ -#define TAL_RESTART_RESETVALUE 0x00ul /**< \brief (TAL_RESTART reset_value) Debug Restart Request */ - -#define TAL_RESTART_CM0P_Pos 0 /**< \brief (TAL_RESTART) CM0P Break Master */ -#define TAL_RESTART_CM0P (0x1ul << TAL_RESTART_CM0P_Pos) -#define TAL_RESTART_PPP_Pos 1 /**< \brief (TAL_RESTART) PPP Break Master */ -#define TAL_RESTART_PPP (0x1ul << TAL_RESTART_PPP_Pos) -#define TAL_RESTART_EXTBRK_Pos 7 /**< \brief (TAL_RESTART) External Break Master */ -#define TAL_RESTART_EXTBRK (0x1ul << TAL_RESTART_EXTBRK_Pos) -#define TAL_RESTART_MASK 0x83ul /**< \brief (TAL_RESTART) MASK Register */ - -/* -------- TAL_BRKSTATUS : (TAL Offset: 0x0E) (R/ 16) Break Request Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CM0P:2; /*!< bit: 0.. 1 CM0P Break Request */ - uint16_t PPP:2; /*!< bit: 2.. 3 PPP Break Request */ - uint16_t :8; /*!< bit: 4..11 Reserved */ - uint16_t EVBRK:2; /*!< bit: 12..13 Event Break Request */ - uint16_t EXTBRK:2; /*!< bit: 14..15 External Break Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TAL_BRKSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_BRKSTATUS_OFFSET 0x0E /**< \brief (TAL_BRKSTATUS offset) Break Request Status */ -#define TAL_BRKSTATUS_RESETVALUE 0x0000ul /**< \brief (TAL_BRKSTATUS reset_value) Break Request Status */ - -#define TAL_BRKSTATUS_CM0P_Pos 0 /**< \brief (TAL_BRKSTATUS) CM0P Break Request */ -#define TAL_BRKSTATUS_CM0P_Msk (0x3ul << TAL_BRKSTATUS_CM0P_Pos) -#define TAL_BRKSTATUS_CM0P(value) ((TAL_BRKSTATUS_CM0P_Msk & ((value) << TAL_BRKSTATUS_CM0P_Pos))) -#define TAL_BRKSTATUS_PPP_Pos 2 /**< \brief (TAL_BRKSTATUS) PPP Break Request */ -#define TAL_BRKSTATUS_PPP_Msk (0x3ul << TAL_BRKSTATUS_PPP_Pos) -#define TAL_BRKSTATUS_PPP(value) ((TAL_BRKSTATUS_PPP_Msk & ((value) << TAL_BRKSTATUS_PPP_Pos))) -#define TAL_BRKSTATUS_EVBRK_Pos 12 /**< \brief (TAL_BRKSTATUS) Event Break Request */ -#define TAL_BRKSTATUS_EVBRK_Msk (0x3ul << TAL_BRKSTATUS_EVBRK_Pos) -#define TAL_BRKSTATUS_EVBRK(value) ((TAL_BRKSTATUS_EVBRK_Msk & ((value) << TAL_BRKSTATUS_EVBRK_Pos))) -#define TAL_BRKSTATUS_EXTBRK_Pos 14 /**< \brief (TAL_BRKSTATUS) External Break Request */ -#define TAL_BRKSTATUS_EXTBRK_Msk (0x3ul << TAL_BRKSTATUS_EXTBRK_Pos) -#define TAL_BRKSTATUS_EXTBRK(value) ((TAL_BRKSTATUS_EXTBRK_Msk & ((value) << TAL_BRKSTATUS_EXTBRK_Pos))) -#define TAL_BRKSTATUS_MASK 0xF00Ful /**< \brief (TAL_BRKSTATUS) MASK Register */ - -/* -------- TAL_CTICTRLA : (TAL Offset: 0x10) (R/W 8) CTIS Cross-Trigger Interface n Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ACTION:2; /*!< bit: 0.. 1 Action when global break issued */ - uint8_t RESTART:1; /*!< bit: 2 Action when global restart issued */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_CTICTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_CTICTRLA_OFFSET 0x10 /**< \brief (TAL_CTICTRLA offset) Cross-Trigger Interface n Control A */ -#define TAL_CTICTRLA_RESETVALUE 0x00ul /**< \brief (TAL_CTICTRLA reset_value) Cross-Trigger Interface n Control A */ - -#define TAL_CTICTRLA_ACTION_Pos 0 /**< \brief (TAL_CTICTRLA) Action when global break issued */ -#define TAL_CTICTRLA_ACTION_Msk (0x3ul << TAL_CTICTRLA_ACTION_Pos) -#define TAL_CTICTRLA_ACTION(value) ((TAL_CTICTRLA_ACTION_Msk & ((value) << TAL_CTICTRLA_ACTION_Pos))) -#define TAL_CTICTRLA_ACTION_BREAK_Val 0x0ul /**< \brief (TAL_CTICTRLA) Break when requested */ -#define TAL_CTICTRLA_ACTION_INTERRUPT_Val 0x1ul /**< \brief (TAL_CTICTRLA) Trigger DBG interrupt instead of break */ -#define TAL_CTICTRLA_ACTION_IGNORE_Val 0x2ul /**< \brief (TAL_CTICTRLA) Ignore break request */ -#define TAL_CTICTRLA_ACTION_BREAK (TAL_CTICTRLA_ACTION_BREAK_Val << TAL_CTICTRLA_ACTION_Pos) -#define TAL_CTICTRLA_ACTION_INTERRUPT (TAL_CTICTRLA_ACTION_INTERRUPT_Val << TAL_CTICTRLA_ACTION_Pos) -#define TAL_CTICTRLA_ACTION_IGNORE (TAL_CTICTRLA_ACTION_IGNORE_Val << TAL_CTICTRLA_ACTION_Pos) -#define TAL_CTICTRLA_RESTART_Pos 2 /**< \brief (TAL_CTICTRLA) Action when global restart issued */ -#define TAL_CTICTRLA_RESTART (0x1ul << TAL_CTICTRLA_RESTART_Pos) -#define TAL_CTICTRLA_MASK 0x07ul /**< \brief (TAL_CTICTRLA) MASK Register */ - -/* -------- TAL_CTIMASK : (TAL Offset: 0x11) (R/W 8) CTIS Cross-Trigger Interface n Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ - uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ - uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_CTIMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_CTIMASK_OFFSET 0x11 /**< \brief (TAL_CTIMASK offset) Cross-Trigger Interface n Mask */ -#define TAL_CTIMASK_RESETVALUE 0x00ul /**< \brief (TAL_CTIMASK reset_value) Cross-Trigger Interface n Mask */ - -#define TAL_CTIMASK_CM0P_Pos 0 /**< \brief (TAL_CTIMASK) CM0P Break Master */ -#define TAL_CTIMASK_CM0P (0x1ul << TAL_CTIMASK_CM0P_Pos) -#define TAL_CTIMASK_PPP_Pos 1 /**< \brief (TAL_CTIMASK) PPP Break Master */ -#define TAL_CTIMASK_PPP (0x1ul << TAL_CTIMASK_PPP_Pos) -#define TAL_CTIMASK_EVBRK_Pos 6 /**< \brief (TAL_CTIMASK) Event Break Master */ -#define TAL_CTIMASK_EVBRK (0x1ul << TAL_CTIMASK_EVBRK_Pos) -#define TAL_CTIMASK_EXTBRK_Pos 7 /**< \brief (TAL_CTIMASK) External Break Master */ -#define TAL_CTIMASK_EXTBRK (0x1ul << TAL_CTIMASK_EXTBRK_Pos) -#define TAL_CTIMASK_MASK 0xC3ul /**< \brief (TAL_CTIMASK) MASK Register */ - -/* -------- TAL_INTSTATUS : (TAL Offset: 0x20) (R/ 8) Interrupt n Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t IRQ0:1; /*!< bit: 0 Interrupt Status for Interrupt Request 0 within Interrupt n */ - uint8_t IRQ1:1; /*!< bit: 1 Interrupt Status for Interrupt Request 1 within Interrupt n */ - uint8_t IRQ2:1; /*!< bit: 2 Interrupt Status for Interrupt Request 2 within Interrupt n */ - uint8_t IRQ3:1; /*!< bit: 3 Interrupt Status for Interrupt Request 3 within Interrupt n */ - uint8_t IRQ4:1; /*!< bit: 4 Interrupt Status for Interrupt Request 4 within Interrupt n */ - uint8_t IRQ5:1; /*!< bit: 5 Interrupt Status for Interrupt Request 5 within Interrupt n */ - uint8_t IRQ6:1; /*!< bit: 6 Interrupt Status for Interrupt Request 6 within Interrupt n */ - uint8_t IRQ7:1; /*!< bit: 7 Interrupt Status for Interrupt Request 7 within Interrupt n */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t IRQ:8; /*!< bit: 0.. 7 Interrupt Status for Interrupt Request x within Interrupt n */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TAL_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_INTSTATUS_OFFSET 0x20 /**< \brief (TAL_INTSTATUS offset) Interrupt n Status */ -#define TAL_INTSTATUS_RESETVALUE 0x00ul /**< \brief (TAL_INTSTATUS reset_value) Interrupt n Status */ - -#define TAL_INTSTATUS_IRQ0_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 0 within Interrupt n */ -#define TAL_INTSTATUS_IRQ0 (1 << TAL_INTSTATUS_IRQ0_Pos) -#define TAL_INTSTATUS_IRQ1_Pos 1 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 1 within Interrupt n */ -#define TAL_INTSTATUS_IRQ1 (1 << TAL_INTSTATUS_IRQ1_Pos) -#define TAL_INTSTATUS_IRQ2_Pos 2 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 2 within Interrupt n */ -#define TAL_INTSTATUS_IRQ2 (1 << TAL_INTSTATUS_IRQ2_Pos) -#define TAL_INTSTATUS_IRQ3_Pos 3 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 3 within Interrupt n */ -#define TAL_INTSTATUS_IRQ3 (1 << TAL_INTSTATUS_IRQ3_Pos) -#define TAL_INTSTATUS_IRQ4_Pos 4 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 4 within Interrupt n */ -#define TAL_INTSTATUS_IRQ4 (1 << TAL_INTSTATUS_IRQ4_Pos) -#define TAL_INTSTATUS_IRQ5_Pos 5 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 5 within Interrupt n */ -#define TAL_INTSTATUS_IRQ5 (1 << TAL_INTSTATUS_IRQ5_Pos) -#define TAL_INTSTATUS_IRQ6_Pos 6 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 6 within Interrupt n */ -#define TAL_INTSTATUS_IRQ6 (1 << TAL_INTSTATUS_IRQ6_Pos) -#define TAL_INTSTATUS_IRQ7_Pos 7 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 7 within Interrupt n */ -#define TAL_INTSTATUS_IRQ7 (1 << TAL_INTSTATUS_IRQ7_Pos) -#define TAL_INTSTATUS_IRQ_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request x within Interrupt n */ -#define TAL_INTSTATUS_IRQ_Msk (0xFFul << TAL_INTSTATUS_IRQ_Pos) -#define TAL_INTSTATUS_IRQ(value) ((TAL_INTSTATUS_IRQ_Msk & ((value) << TAL_INTSTATUS_IRQ_Pos))) -#define TAL_INTSTATUS_MASK 0xFFul /**< \brief (TAL_INTSTATUS) MASK Register */ - -/* -------- TAL_DMACPUSEL0 : (TAL Offset: 0x40) (R/W 32) DMA Channel Interrupts CPU Select 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CH0:1; /*!< bit: 0 DMA Channel 0 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 1 Reserved */ - uint32_t CH1:1; /*!< bit: 2 DMA Channel 1 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t CH2:1; /*!< bit: 4 DMA Channel 2 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t CH3:1; /*!< bit: 6 DMA Channel 3 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t CH4:1; /*!< bit: 8 DMA Channel 4 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 9 Reserved */ - uint32_t CH5:1; /*!< bit: 10 DMA Channel 5 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t CH6:1; /*!< bit: 12 DMA Channel 6 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 13 Reserved */ - uint32_t CH7:1; /*!< bit: 14 DMA Channel 7 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CH8:1; /*!< bit: 16 DMA Channel 8 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 17 Reserved */ - uint32_t CH9:1; /*!< bit: 18 DMA Channel 9 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t CH10:1; /*!< bit: 20 DMA Channel 10 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 21 Reserved */ - uint32_t CH11:1; /*!< bit: 22 DMA Channel 11 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t CH12:1; /*!< bit: 24 DMA Channel 12 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 25 Reserved */ - uint32_t CH13:1; /*!< bit: 26 DMA Channel 13 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t CH14:1; /*!< bit: 28 DMA Channel 14 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t CH15:1; /*!< bit: 30 DMA Channel 15 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TAL_DMACPUSEL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_DMACPUSEL0_OFFSET 0x40 /**< \brief (TAL_DMACPUSEL0 offset) DMA Channel Interrupts CPU Select 0 */ -#define TAL_DMACPUSEL0_RESETVALUE 0x00000000ul /**< \brief (TAL_DMACPUSEL0 reset_value) DMA Channel Interrupts CPU Select 0 */ - -#define TAL_DMACPUSEL0_CH0_Pos 0 /**< \brief (TAL_DMACPUSEL0) DMA Channel 0 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH0_Msk (0x1ul << TAL_DMACPUSEL0_CH0_Pos) -#define TAL_DMACPUSEL0_CH0(value) ((TAL_DMACPUSEL0_CH0_Msk & ((value) << TAL_DMACPUSEL0_CH0_Pos))) -#define TAL_DMACPUSEL0_CH1_Pos 2 /**< \brief (TAL_DMACPUSEL0) DMA Channel 1 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH1_Msk (0x1ul << TAL_DMACPUSEL0_CH1_Pos) -#define TAL_DMACPUSEL0_CH1(value) ((TAL_DMACPUSEL0_CH1_Msk & ((value) << TAL_DMACPUSEL0_CH1_Pos))) -#define TAL_DMACPUSEL0_CH2_Pos 4 /**< \brief (TAL_DMACPUSEL0) DMA Channel 2 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH2_Msk (0x1ul << TAL_DMACPUSEL0_CH2_Pos) -#define TAL_DMACPUSEL0_CH2(value) ((TAL_DMACPUSEL0_CH2_Msk & ((value) << TAL_DMACPUSEL0_CH2_Pos))) -#define TAL_DMACPUSEL0_CH3_Pos 6 /**< \brief (TAL_DMACPUSEL0) DMA Channel 3 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH3_Msk (0x1ul << TAL_DMACPUSEL0_CH3_Pos) -#define TAL_DMACPUSEL0_CH3(value) ((TAL_DMACPUSEL0_CH3_Msk & ((value) << TAL_DMACPUSEL0_CH3_Pos))) -#define TAL_DMACPUSEL0_CH4_Pos 8 /**< \brief (TAL_DMACPUSEL0) DMA Channel 4 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH4_Msk (0x1ul << TAL_DMACPUSEL0_CH4_Pos) -#define TAL_DMACPUSEL0_CH4(value) ((TAL_DMACPUSEL0_CH4_Msk & ((value) << TAL_DMACPUSEL0_CH4_Pos))) -#define TAL_DMACPUSEL0_CH5_Pos 10 /**< \brief (TAL_DMACPUSEL0) DMA Channel 5 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH5_Msk (0x1ul << TAL_DMACPUSEL0_CH5_Pos) -#define TAL_DMACPUSEL0_CH5(value) ((TAL_DMACPUSEL0_CH5_Msk & ((value) << TAL_DMACPUSEL0_CH5_Pos))) -#define TAL_DMACPUSEL0_CH6_Pos 12 /**< \brief (TAL_DMACPUSEL0) DMA Channel 6 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH6_Msk (0x1ul << TAL_DMACPUSEL0_CH6_Pos) -#define TAL_DMACPUSEL0_CH6(value) ((TAL_DMACPUSEL0_CH6_Msk & ((value) << TAL_DMACPUSEL0_CH6_Pos))) -#define TAL_DMACPUSEL0_CH7_Pos 14 /**< \brief (TAL_DMACPUSEL0) DMA Channel 7 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH7_Msk (0x1ul << TAL_DMACPUSEL0_CH7_Pos) -#define TAL_DMACPUSEL0_CH7(value) ((TAL_DMACPUSEL0_CH7_Msk & ((value) << TAL_DMACPUSEL0_CH7_Pos))) -#define TAL_DMACPUSEL0_CH8_Pos 16 /**< \brief (TAL_DMACPUSEL0) DMA Channel 8 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH8_Msk (0x1ul << TAL_DMACPUSEL0_CH8_Pos) -#define TAL_DMACPUSEL0_CH8(value) ((TAL_DMACPUSEL0_CH8_Msk & ((value) << TAL_DMACPUSEL0_CH8_Pos))) -#define TAL_DMACPUSEL0_CH9_Pos 18 /**< \brief (TAL_DMACPUSEL0) DMA Channel 9 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH9_Msk (0x1ul << TAL_DMACPUSEL0_CH9_Pos) -#define TAL_DMACPUSEL0_CH9(value) ((TAL_DMACPUSEL0_CH9_Msk & ((value) << TAL_DMACPUSEL0_CH9_Pos))) -#define TAL_DMACPUSEL0_CH10_Pos 20 /**< \brief (TAL_DMACPUSEL0) DMA Channel 10 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH10_Msk (0x1ul << TAL_DMACPUSEL0_CH10_Pos) -#define TAL_DMACPUSEL0_CH10(value) ((TAL_DMACPUSEL0_CH10_Msk & ((value) << TAL_DMACPUSEL0_CH10_Pos))) -#define TAL_DMACPUSEL0_CH11_Pos 22 /**< \brief (TAL_DMACPUSEL0) DMA Channel 11 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH11_Msk (0x1ul << TAL_DMACPUSEL0_CH11_Pos) -#define TAL_DMACPUSEL0_CH11(value) ((TAL_DMACPUSEL0_CH11_Msk & ((value) << TAL_DMACPUSEL0_CH11_Pos))) -#define TAL_DMACPUSEL0_CH12_Pos 24 /**< \brief (TAL_DMACPUSEL0) DMA Channel 12 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH12_Msk (0x1ul << TAL_DMACPUSEL0_CH12_Pos) -#define TAL_DMACPUSEL0_CH12(value) ((TAL_DMACPUSEL0_CH12_Msk & ((value) << TAL_DMACPUSEL0_CH12_Pos))) -#define TAL_DMACPUSEL0_CH13_Pos 26 /**< \brief (TAL_DMACPUSEL0) DMA Channel 13 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH13_Msk (0x1ul << TAL_DMACPUSEL0_CH13_Pos) -#define TAL_DMACPUSEL0_CH13(value) ((TAL_DMACPUSEL0_CH13_Msk & ((value) << TAL_DMACPUSEL0_CH13_Pos))) -#define TAL_DMACPUSEL0_CH14_Pos 28 /**< \brief (TAL_DMACPUSEL0) DMA Channel 14 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH14_Msk (0x1ul << TAL_DMACPUSEL0_CH14_Pos) -#define TAL_DMACPUSEL0_CH14(value) ((TAL_DMACPUSEL0_CH14_Msk & ((value) << TAL_DMACPUSEL0_CH14_Pos))) -#define TAL_DMACPUSEL0_CH15_Pos 30 /**< \brief (TAL_DMACPUSEL0) DMA Channel 15 Interrupt CPU Select */ -#define TAL_DMACPUSEL0_CH15_Msk (0x1ul << TAL_DMACPUSEL0_CH15_Pos) -#define TAL_DMACPUSEL0_CH15(value) ((TAL_DMACPUSEL0_CH15_Msk & ((value) << TAL_DMACPUSEL0_CH15_Pos))) -#define TAL_DMACPUSEL0_MASK 0x55555555ul /**< \brief (TAL_DMACPUSEL0) MASK Register */ - -/* -------- TAL_EVCPUSEL0 : (TAL Offset: 0x48) (R/W 32) EVSYS Channel Interrupts CPU Select 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CH0:1; /*!< bit: 0 Event Channel 0 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 1 Reserved */ - uint32_t CH1:1; /*!< bit: 2 Event Channel 1 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t CH2:1; /*!< bit: 4 Event Channel 2 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t CH3:1; /*!< bit: 6 Event Channel 3 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t CH4:1; /*!< bit: 8 Event Channel 4 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 9 Reserved */ - uint32_t CH5:1; /*!< bit: 10 Event Channel 5 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t CH6:1; /*!< bit: 12 Event Channel 6 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 13 Reserved */ - uint32_t CH7:1; /*!< bit: 14 Event Channel 7 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CH8:1; /*!< bit: 16 Event Channel 8 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 17 Reserved */ - uint32_t CH9:1; /*!< bit: 18 Event Channel 9 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t CH10:1; /*!< bit: 20 Event Channel 10 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 21 Reserved */ - uint32_t CH11:1; /*!< bit: 22 Event Channel 11 Interrupt CPU Select */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TAL_EVCPUSEL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_EVCPUSEL0_OFFSET 0x48 /**< \brief (TAL_EVCPUSEL0 offset) EVSYS Channel Interrupts CPU Select 0 */ -#define TAL_EVCPUSEL0_RESETVALUE 0x00000000ul /**< \brief (TAL_EVCPUSEL0 reset_value) EVSYS Channel Interrupts CPU Select 0 */ - -#define TAL_EVCPUSEL0_CH0_Pos 0 /**< \brief (TAL_EVCPUSEL0) Event Channel 0 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH0_Msk (0x1ul << TAL_EVCPUSEL0_CH0_Pos) -#define TAL_EVCPUSEL0_CH0(value) ((TAL_EVCPUSEL0_CH0_Msk & ((value) << TAL_EVCPUSEL0_CH0_Pos))) -#define TAL_EVCPUSEL0_CH1_Pos 2 /**< \brief (TAL_EVCPUSEL0) Event Channel 1 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH1_Msk (0x1ul << TAL_EVCPUSEL0_CH1_Pos) -#define TAL_EVCPUSEL0_CH1(value) ((TAL_EVCPUSEL0_CH1_Msk & ((value) << TAL_EVCPUSEL0_CH1_Pos))) -#define TAL_EVCPUSEL0_CH2_Pos 4 /**< \brief (TAL_EVCPUSEL0) Event Channel 2 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH2_Msk (0x1ul << TAL_EVCPUSEL0_CH2_Pos) -#define TAL_EVCPUSEL0_CH2(value) ((TAL_EVCPUSEL0_CH2_Msk & ((value) << TAL_EVCPUSEL0_CH2_Pos))) -#define TAL_EVCPUSEL0_CH3_Pos 6 /**< \brief (TAL_EVCPUSEL0) Event Channel 3 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH3_Msk (0x1ul << TAL_EVCPUSEL0_CH3_Pos) -#define TAL_EVCPUSEL0_CH3(value) ((TAL_EVCPUSEL0_CH3_Msk & ((value) << TAL_EVCPUSEL0_CH3_Pos))) -#define TAL_EVCPUSEL0_CH4_Pos 8 /**< \brief (TAL_EVCPUSEL0) Event Channel 4 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH4_Msk (0x1ul << TAL_EVCPUSEL0_CH4_Pos) -#define TAL_EVCPUSEL0_CH4(value) ((TAL_EVCPUSEL0_CH4_Msk & ((value) << TAL_EVCPUSEL0_CH4_Pos))) -#define TAL_EVCPUSEL0_CH5_Pos 10 /**< \brief (TAL_EVCPUSEL0) Event Channel 5 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH5_Msk (0x1ul << TAL_EVCPUSEL0_CH5_Pos) -#define TAL_EVCPUSEL0_CH5(value) ((TAL_EVCPUSEL0_CH5_Msk & ((value) << TAL_EVCPUSEL0_CH5_Pos))) -#define TAL_EVCPUSEL0_CH6_Pos 12 /**< \brief (TAL_EVCPUSEL0) Event Channel 6 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH6_Msk (0x1ul << TAL_EVCPUSEL0_CH6_Pos) -#define TAL_EVCPUSEL0_CH6(value) ((TAL_EVCPUSEL0_CH6_Msk & ((value) << TAL_EVCPUSEL0_CH6_Pos))) -#define TAL_EVCPUSEL0_CH7_Pos 14 /**< \brief (TAL_EVCPUSEL0) Event Channel 7 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH7_Msk (0x1ul << TAL_EVCPUSEL0_CH7_Pos) -#define TAL_EVCPUSEL0_CH7(value) ((TAL_EVCPUSEL0_CH7_Msk & ((value) << TAL_EVCPUSEL0_CH7_Pos))) -#define TAL_EVCPUSEL0_CH8_Pos 16 /**< \brief (TAL_EVCPUSEL0) Event Channel 8 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH8_Msk (0x1ul << TAL_EVCPUSEL0_CH8_Pos) -#define TAL_EVCPUSEL0_CH8(value) ((TAL_EVCPUSEL0_CH8_Msk & ((value) << TAL_EVCPUSEL0_CH8_Pos))) -#define TAL_EVCPUSEL0_CH9_Pos 18 /**< \brief (TAL_EVCPUSEL0) Event Channel 9 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH9_Msk (0x1ul << TAL_EVCPUSEL0_CH9_Pos) -#define TAL_EVCPUSEL0_CH9(value) ((TAL_EVCPUSEL0_CH9_Msk & ((value) << TAL_EVCPUSEL0_CH9_Pos))) -#define TAL_EVCPUSEL0_CH10_Pos 20 /**< \brief (TAL_EVCPUSEL0) Event Channel 10 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH10_Msk (0x1ul << TAL_EVCPUSEL0_CH10_Pos) -#define TAL_EVCPUSEL0_CH10(value) ((TAL_EVCPUSEL0_CH10_Msk & ((value) << TAL_EVCPUSEL0_CH10_Pos))) -#define TAL_EVCPUSEL0_CH11_Pos 22 /**< \brief (TAL_EVCPUSEL0) Event Channel 11 Interrupt CPU Select */ -#define TAL_EVCPUSEL0_CH11_Msk (0x1ul << TAL_EVCPUSEL0_CH11_Pos) -#define TAL_EVCPUSEL0_CH11(value) ((TAL_EVCPUSEL0_CH11_Msk & ((value) << TAL_EVCPUSEL0_CH11_Pos))) -#define TAL_EVCPUSEL0_MASK 0x00555555ul /**< \brief (TAL_EVCPUSEL0) MASK Register */ - -/* -------- TAL_EICCPUSEL0 : (TAL Offset: 0x50) (R/W 32) EIC External Interrupts CPU Select 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 CPU Select */ - uint32_t :1; /*!< bit: 1 Reserved */ - uint32_t EXTINT1:1; /*!< bit: 2 External Interrupt 1 CPU Select */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t EXTINT2:1; /*!< bit: 4 External Interrupt 2 CPU Select */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t EXTINT3:1; /*!< bit: 6 External Interrupt 3 CPU Select */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t EXTINT4:1; /*!< bit: 8 External Interrupt 4 CPU Select */ - uint32_t :1; /*!< bit: 9 Reserved */ - uint32_t EXTINT5:1; /*!< bit: 10 External Interrupt 5 CPU Select */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t EXTINT6:1; /*!< bit: 12 External Interrupt 6 CPU Select */ - uint32_t :1; /*!< bit: 13 Reserved */ - uint32_t EXTINT7:1; /*!< bit: 14 External Interrupt 7 CPU Select */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t EXTINT8:1; /*!< bit: 16 External Interrupt 8 CPU Select */ - uint32_t :1; /*!< bit: 17 Reserved */ - uint32_t EXTINT9:1; /*!< bit: 18 External Interrupt 9 CPU Select */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t EXTINT10:1; /*!< bit: 20 External Interrupt 10 CPU Select */ - uint32_t :1; /*!< bit: 21 Reserved */ - uint32_t EXTINT11:1; /*!< bit: 22 External Interrupt 11 CPU Select */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t EXTINT12:1; /*!< bit: 24 External Interrupt 12 CPU Select */ - uint32_t :1; /*!< bit: 25 Reserved */ - uint32_t EXTINT13:1; /*!< bit: 26 External Interrupt 13 CPU Select */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t EXTINT14:1; /*!< bit: 28 External Interrupt 14 CPU Select */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t EXTINT15:1; /*!< bit: 30 External Interrupt 15 CPU Select */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TAL_EICCPUSEL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_EICCPUSEL0_OFFSET 0x50 /**< \brief (TAL_EICCPUSEL0 offset) EIC External Interrupts CPU Select 0 */ -#define TAL_EICCPUSEL0_RESETVALUE 0x00000000ul /**< \brief (TAL_EICCPUSEL0 reset_value) EIC External Interrupts CPU Select 0 */ - -#define TAL_EICCPUSEL0_EXTINT0_Pos 0 /**< \brief (TAL_EICCPUSEL0) External Interrupt 0 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT0_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT0_Pos) -#define TAL_EICCPUSEL0_EXTINT0(value) ((TAL_EICCPUSEL0_EXTINT0_Msk & ((value) << TAL_EICCPUSEL0_EXTINT0_Pos))) -#define TAL_EICCPUSEL0_EXTINT1_Pos 2 /**< \brief (TAL_EICCPUSEL0) External Interrupt 1 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT1_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT1_Pos) -#define TAL_EICCPUSEL0_EXTINT1(value) ((TAL_EICCPUSEL0_EXTINT1_Msk & ((value) << TAL_EICCPUSEL0_EXTINT1_Pos))) -#define TAL_EICCPUSEL0_EXTINT2_Pos 4 /**< \brief (TAL_EICCPUSEL0) External Interrupt 2 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT2_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT2_Pos) -#define TAL_EICCPUSEL0_EXTINT2(value) ((TAL_EICCPUSEL0_EXTINT2_Msk & ((value) << TAL_EICCPUSEL0_EXTINT2_Pos))) -#define TAL_EICCPUSEL0_EXTINT3_Pos 6 /**< \brief (TAL_EICCPUSEL0) External Interrupt 3 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT3_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT3_Pos) -#define TAL_EICCPUSEL0_EXTINT3(value) ((TAL_EICCPUSEL0_EXTINT3_Msk & ((value) << TAL_EICCPUSEL0_EXTINT3_Pos))) -#define TAL_EICCPUSEL0_EXTINT4_Pos 8 /**< \brief (TAL_EICCPUSEL0) External Interrupt 4 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT4_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT4_Pos) -#define TAL_EICCPUSEL0_EXTINT4(value) ((TAL_EICCPUSEL0_EXTINT4_Msk & ((value) << TAL_EICCPUSEL0_EXTINT4_Pos))) -#define TAL_EICCPUSEL0_EXTINT5_Pos 10 /**< \brief (TAL_EICCPUSEL0) External Interrupt 5 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT5_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT5_Pos) -#define TAL_EICCPUSEL0_EXTINT5(value) ((TAL_EICCPUSEL0_EXTINT5_Msk & ((value) << TAL_EICCPUSEL0_EXTINT5_Pos))) -#define TAL_EICCPUSEL0_EXTINT6_Pos 12 /**< \brief (TAL_EICCPUSEL0) External Interrupt 6 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT6_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT6_Pos) -#define TAL_EICCPUSEL0_EXTINT6(value) ((TAL_EICCPUSEL0_EXTINT6_Msk & ((value) << TAL_EICCPUSEL0_EXTINT6_Pos))) -#define TAL_EICCPUSEL0_EXTINT7_Pos 14 /**< \brief (TAL_EICCPUSEL0) External Interrupt 7 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT7_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT7_Pos) -#define TAL_EICCPUSEL0_EXTINT7(value) ((TAL_EICCPUSEL0_EXTINT7_Msk & ((value) << TAL_EICCPUSEL0_EXTINT7_Pos))) -#define TAL_EICCPUSEL0_EXTINT8_Pos 16 /**< \brief (TAL_EICCPUSEL0) External Interrupt 8 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT8_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT8_Pos) -#define TAL_EICCPUSEL0_EXTINT8(value) ((TAL_EICCPUSEL0_EXTINT8_Msk & ((value) << TAL_EICCPUSEL0_EXTINT8_Pos))) -#define TAL_EICCPUSEL0_EXTINT9_Pos 18 /**< \brief (TAL_EICCPUSEL0) External Interrupt 9 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT9_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT9_Pos) -#define TAL_EICCPUSEL0_EXTINT9(value) ((TAL_EICCPUSEL0_EXTINT9_Msk & ((value) << TAL_EICCPUSEL0_EXTINT9_Pos))) -#define TAL_EICCPUSEL0_EXTINT10_Pos 20 /**< \brief (TAL_EICCPUSEL0) External Interrupt 10 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT10_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT10_Pos) -#define TAL_EICCPUSEL0_EXTINT10(value) ((TAL_EICCPUSEL0_EXTINT10_Msk & ((value) << TAL_EICCPUSEL0_EXTINT10_Pos))) -#define TAL_EICCPUSEL0_EXTINT11_Pos 22 /**< \brief (TAL_EICCPUSEL0) External Interrupt 11 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT11_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT11_Pos) -#define TAL_EICCPUSEL0_EXTINT11(value) ((TAL_EICCPUSEL0_EXTINT11_Msk & ((value) << TAL_EICCPUSEL0_EXTINT11_Pos))) -#define TAL_EICCPUSEL0_EXTINT12_Pos 24 /**< \brief (TAL_EICCPUSEL0) External Interrupt 12 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT12_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT12_Pos) -#define TAL_EICCPUSEL0_EXTINT12(value) ((TAL_EICCPUSEL0_EXTINT12_Msk & ((value) << TAL_EICCPUSEL0_EXTINT12_Pos))) -#define TAL_EICCPUSEL0_EXTINT13_Pos 26 /**< \brief (TAL_EICCPUSEL0) External Interrupt 13 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT13_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT13_Pos) -#define TAL_EICCPUSEL0_EXTINT13(value) ((TAL_EICCPUSEL0_EXTINT13_Msk & ((value) << TAL_EICCPUSEL0_EXTINT13_Pos))) -#define TAL_EICCPUSEL0_EXTINT14_Pos 28 /**< \brief (TAL_EICCPUSEL0) External Interrupt 14 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT14_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT14_Pos) -#define TAL_EICCPUSEL0_EXTINT14(value) ((TAL_EICCPUSEL0_EXTINT14_Msk & ((value) << TAL_EICCPUSEL0_EXTINT14_Pos))) -#define TAL_EICCPUSEL0_EXTINT15_Pos 30 /**< \brief (TAL_EICCPUSEL0) External Interrupt 15 CPU Select */ -#define TAL_EICCPUSEL0_EXTINT15_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT15_Pos) -#define TAL_EICCPUSEL0_EXTINT15(value) ((TAL_EICCPUSEL0_EXTINT15_Msk & ((value) << TAL_EICCPUSEL0_EXTINT15_Pos))) -#define TAL_EICCPUSEL0_MASK 0x55555555ul /**< \brief (TAL_EICCPUSEL0) MASK Register */ - -/* -------- TAL_INTCPUSEL0 : (TAL Offset: 0x58) (R/W 32) Interrupts CPU Select 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SYSTEM:1; /*!< bit: 0 SYSTEM Interrupt CPU Select */ - uint32_t :1; /*!< bit: 1 Reserved */ - uint32_t WDT:1; /*!< bit: 2 WDT Interrupt CPU Select */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RTC:1; /*!< bit: 4 RTC Interrupt CPU Select */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t NVMCTRL:1; /*!< bit: 8 NVMCTRL Interrupt CPU Select */ - uint32_t :3; /*!< bit: 9..11 Reserved */ - uint32_t USB:1; /*!< bit: 12 USB Interrupt CPU Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t SERCOM0:1; /*!< bit: 16 SERCOM0 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 17 Reserved */ - uint32_t SERCOM1:1; /*!< bit: 18 SERCOM1 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t SERCOM2:1; /*!< bit: 20 SERCOM2 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 21 Reserved */ - uint32_t SERCOM3:1; /*!< bit: 22 SERCOM3 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t SERCOM4:1; /*!< bit: 24 SERCOM4 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 25 Reserved */ - uint32_t SERCOM5:1; /*!< bit: 26 SERCOM5 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t TCC0:1; /*!< bit: 28 TCC0 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t TCC1:1; /*!< bit: 30 TCC1 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TAL_INTCPUSEL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_INTCPUSEL0_OFFSET 0x58 /**< \brief (TAL_INTCPUSEL0 offset) Interrupts CPU Select 0 */ -#define TAL_INTCPUSEL0_RESETVALUE 0x00000000ul /**< \brief (TAL_INTCPUSEL0 reset_value) Interrupts CPU Select 0 */ - -#define TAL_INTCPUSEL0_SYSTEM_Pos 0 /**< \brief (TAL_INTCPUSEL0) SYSTEM Interrupt CPU Select */ -#define TAL_INTCPUSEL0_SYSTEM_Msk (0x1ul << TAL_INTCPUSEL0_SYSTEM_Pos) -#define TAL_INTCPUSEL0_SYSTEM(value) ((TAL_INTCPUSEL0_SYSTEM_Msk & ((value) << TAL_INTCPUSEL0_SYSTEM_Pos))) -#define TAL_INTCPUSEL0_WDT_Pos 2 /**< \brief (TAL_INTCPUSEL0) WDT Interrupt CPU Select */ -#define TAL_INTCPUSEL0_WDT_Msk (0x1ul << TAL_INTCPUSEL0_WDT_Pos) -#define TAL_INTCPUSEL0_WDT(value) ((TAL_INTCPUSEL0_WDT_Msk & ((value) << TAL_INTCPUSEL0_WDT_Pos))) -#define TAL_INTCPUSEL0_RTC_Pos 4 /**< \brief (TAL_INTCPUSEL0) RTC Interrupt CPU Select */ -#define TAL_INTCPUSEL0_RTC_Msk (0x1ul << TAL_INTCPUSEL0_RTC_Pos) -#define TAL_INTCPUSEL0_RTC(value) ((TAL_INTCPUSEL0_RTC_Msk & ((value) << TAL_INTCPUSEL0_RTC_Pos))) -#define TAL_INTCPUSEL0_NVMCTRL_Pos 8 /**< \brief (TAL_INTCPUSEL0) NVMCTRL Interrupt CPU Select */ -#define TAL_INTCPUSEL0_NVMCTRL_Msk (0x1ul << TAL_INTCPUSEL0_NVMCTRL_Pos) -#define TAL_INTCPUSEL0_NVMCTRL(value) ((TAL_INTCPUSEL0_NVMCTRL_Msk & ((value) << TAL_INTCPUSEL0_NVMCTRL_Pos))) -#define TAL_INTCPUSEL0_USB_Pos 12 /**< \brief (TAL_INTCPUSEL0) USB Interrupt CPU Select */ -#define TAL_INTCPUSEL0_USB_Msk (0x1ul << TAL_INTCPUSEL0_USB_Pos) -#define TAL_INTCPUSEL0_USB(value) ((TAL_INTCPUSEL0_USB_Msk & ((value) << TAL_INTCPUSEL0_USB_Pos))) -#define TAL_INTCPUSEL0_SERCOM0_Pos 16 /**< \brief (TAL_INTCPUSEL0) SERCOM0 Interrupt CPU Select */ -#define TAL_INTCPUSEL0_SERCOM0_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM0_Pos) -#define TAL_INTCPUSEL0_SERCOM0(value) ((TAL_INTCPUSEL0_SERCOM0_Msk & ((value) << TAL_INTCPUSEL0_SERCOM0_Pos))) -#define TAL_INTCPUSEL0_SERCOM1_Pos 18 /**< \brief (TAL_INTCPUSEL0) SERCOM1 Interrupt CPU Select */ -#define TAL_INTCPUSEL0_SERCOM1_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM1_Pos) -#define TAL_INTCPUSEL0_SERCOM1(value) ((TAL_INTCPUSEL0_SERCOM1_Msk & ((value) << TAL_INTCPUSEL0_SERCOM1_Pos))) -#define TAL_INTCPUSEL0_SERCOM2_Pos 20 /**< \brief (TAL_INTCPUSEL0) SERCOM2 Interrupt CPU Select */ -#define TAL_INTCPUSEL0_SERCOM2_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM2_Pos) -#define TAL_INTCPUSEL0_SERCOM2(value) ((TAL_INTCPUSEL0_SERCOM2_Msk & ((value) << TAL_INTCPUSEL0_SERCOM2_Pos))) -#define TAL_INTCPUSEL0_SERCOM3_Pos 22 /**< \brief (TAL_INTCPUSEL0) SERCOM3 Interrupt CPU Select */ -#define TAL_INTCPUSEL0_SERCOM3_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM3_Pos) -#define TAL_INTCPUSEL0_SERCOM3(value) ((TAL_INTCPUSEL0_SERCOM3_Msk & ((value) << TAL_INTCPUSEL0_SERCOM3_Pos))) -#define TAL_INTCPUSEL0_SERCOM4_Pos 24 /**< \brief (TAL_INTCPUSEL0) SERCOM4 Interrupt CPU Select */ -#define TAL_INTCPUSEL0_SERCOM4_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM4_Pos) -#define TAL_INTCPUSEL0_SERCOM4(value) ((TAL_INTCPUSEL0_SERCOM4_Msk & ((value) << TAL_INTCPUSEL0_SERCOM4_Pos))) -#define TAL_INTCPUSEL0_SERCOM5_Pos 26 /**< \brief (TAL_INTCPUSEL0) SERCOM5 Interrupt CPU Select */ -#define TAL_INTCPUSEL0_SERCOM5_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM5_Pos) -#define TAL_INTCPUSEL0_SERCOM5(value) ((TAL_INTCPUSEL0_SERCOM5_Msk & ((value) << TAL_INTCPUSEL0_SERCOM5_Pos))) -#define TAL_INTCPUSEL0_TCC0_Pos 28 /**< \brief (TAL_INTCPUSEL0) TCC0 Interrupt CPU Select */ -#define TAL_INTCPUSEL0_TCC0_Msk (0x1ul << TAL_INTCPUSEL0_TCC0_Pos) -#define TAL_INTCPUSEL0_TCC0(value) ((TAL_INTCPUSEL0_TCC0_Msk & ((value) << TAL_INTCPUSEL0_TCC0_Pos))) -#define TAL_INTCPUSEL0_TCC1_Pos 30 /**< \brief (TAL_INTCPUSEL0) TCC1 Interrupt CPU Select */ -#define TAL_INTCPUSEL0_TCC1_Msk (0x1ul << TAL_INTCPUSEL0_TCC1_Pos) -#define TAL_INTCPUSEL0_TCC1(value) ((TAL_INTCPUSEL0_TCC1_Msk & ((value) << TAL_INTCPUSEL0_TCC1_Pos))) -#define TAL_INTCPUSEL0_MASK 0x55551115ul /**< \brief (TAL_INTCPUSEL0) MASK Register */ - -/* -------- TAL_INTCPUSEL1 : (TAL Offset: 0x5C) (R/W 32) Interrupts CPU Select 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TCC2:1; /*!< bit: 0 TCC2 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 1 Reserved */ - uint32_t TC0:1; /*!< bit: 2 TC0 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t TC1:1; /*!< bit: 4 TC1 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t TC2:1; /*!< bit: 6 TC2 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TC3:1; /*!< bit: 8 TC3 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 9 Reserved */ - uint32_t TC4:1; /*!< bit: 10 TC4 Interrupt CPU Select */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t ADC:1; /*!< bit: 12 ADC Interrupt CPU Select */ - uint32_t :1; /*!< bit: 13 Reserved */ - uint32_t AC:1; /*!< bit: 14 AC Interrupt CPU Select */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t DAC:1; /*!< bit: 16 DAC Interrupt CPU Select */ - uint32_t :1; /*!< bit: 17 Reserved */ - uint32_t PTC:1; /*!< bit: 18 PTC Interrupt CPU Select */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t AES:1; /*!< bit: 20 AES Interrupt CPU Select */ - uint32_t :1; /*!< bit: 21 Reserved */ - uint32_t TRNG:1; /*!< bit: 22 TRNG Interrupt CPU Select */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PICOP:1; /*!< bit: 24 PICOP Interrupt CPU Select */ - uint32_t :7; /*!< bit: 25..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TAL_INTCPUSEL1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_INTCPUSEL1_OFFSET 0x5C /**< \brief (TAL_INTCPUSEL1 offset) Interrupts CPU Select 1 */ -#define TAL_INTCPUSEL1_RESETVALUE 0x00000000ul /**< \brief (TAL_INTCPUSEL1 reset_value) Interrupts CPU Select 1 */ - -#define TAL_INTCPUSEL1_TCC2_Pos 0 /**< \brief (TAL_INTCPUSEL1) TCC2 Interrupt CPU Select */ -#define TAL_INTCPUSEL1_TCC2_Msk (0x1ul << TAL_INTCPUSEL1_TCC2_Pos) -#define TAL_INTCPUSEL1_TCC2(value) ((TAL_INTCPUSEL1_TCC2_Msk & ((value) << TAL_INTCPUSEL1_TCC2_Pos))) -#define TAL_INTCPUSEL1_TC0_Pos 2 /**< \brief (TAL_INTCPUSEL1) TC0 Interrupt CPU Select */ -#define TAL_INTCPUSEL1_TC0_Msk (0x1ul << TAL_INTCPUSEL1_TC0_Pos) -#define TAL_INTCPUSEL1_TC0(value) ((TAL_INTCPUSEL1_TC0_Msk & ((value) << TAL_INTCPUSEL1_TC0_Pos))) -#define TAL_INTCPUSEL1_TC1_Pos 4 /**< \brief (TAL_INTCPUSEL1) TC1 Interrupt CPU Select */ -#define TAL_INTCPUSEL1_TC1_Msk (0x1ul << TAL_INTCPUSEL1_TC1_Pos) -#define TAL_INTCPUSEL1_TC1(value) ((TAL_INTCPUSEL1_TC1_Msk & ((value) << TAL_INTCPUSEL1_TC1_Pos))) -#define TAL_INTCPUSEL1_TC2_Pos 6 /**< \brief (TAL_INTCPUSEL1) TC2 Interrupt CPU Select */ -#define TAL_INTCPUSEL1_TC2_Msk (0x1ul << TAL_INTCPUSEL1_TC2_Pos) -#define TAL_INTCPUSEL1_TC2(value) ((TAL_INTCPUSEL1_TC2_Msk & ((value) << TAL_INTCPUSEL1_TC2_Pos))) -#define TAL_INTCPUSEL1_TC3_Pos 8 /**< \brief (TAL_INTCPUSEL1) TC3 Interrupt CPU Select */ -#define TAL_INTCPUSEL1_TC3_Msk (0x1ul << TAL_INTCPUSEL1_TC3_Pos) -#define TAL_INTCPUSEL1_TC3(value) ((TAL_INTCPUSEL1_TC3_Msk & ((value) << TAL_INTCPUSEL1_TC3_Pos))) -#define TAL_INTCPUSEL1_TC4_Pos 10 /**< \brief (TAL_INTCPUSEL1) TC4 Interrupt CPU Select */ -#define TAL_INTCPUSEL1_TC4_Msk (0x1ul << TAL_INTCPUSEL1_TC4_Pos) -#define TAL_INTCPUSEL1_TC4(value) ((TAL_INTCPUSEL1_TC4_Msk & ((value) << TAL_INTCPUSEL1_TC4_Pos))) -#define TAL_INTCPUSEL1_ADC_Pos 12 /**< \brief (TAL_INTCPUSEL1) ADC Interrupt CPU Select */ -#define TAL_INTCPUSEL1_ADC_Msk (0x1ul << TAL_INTCPUSEL1_ADC_Pos) -#define TAL_INTCPUSEL1_ADC(value) ((TAL_INTCPUSEL1_ADC_Msk & ((value) << TAL_INTCPUSEL1_ADC_Pos))) -#define TAL_INTCPUSEL1_AC_Pos 14 /**< \brief (TAL_INTCPUSEL1) AC Interrupt CPU Select */ -#define TAL_INTCPUSEL1_AC_Msk (0x1ul << TAL_INTCPUSEL1_AC_Pos) -#define TAL_INTCPUSEL1_AC(value) ((TAL_INTCPUSEL1_AC_Msk & ((value) << TAL_INTCPUSEL1_AC_Pos))) -#define TAL_INTCPUSEL1_DAC_Pos 16 /**< \brief (TAL_INTCPUSEL1) DAC Interrupt CPU Select */ -#define TAL_INTCPUSEL1_DAC_Msk (0x1ul << TAL_INTCPUSEL1_DAC_Pos) -#define TAL_INTCPUSEL1_DAC(value) ((TAL_INTCPUSEL1_DAC_Msk & ((value) << TAL_INTCPUSEL1_DAC_Pos))) -#define TAL_INTCPUSEL1_PTC_Pos 18 /**< \brief (TAL_INTCPUSEL1) PTC Interrupt CPU Select */ -#define TAL_INTCPUSEL1_PTC_Msk (0x1ul << TAL_INTCPUSEL1_PTC_Pos) -#define TAL_INTCPUSEL1_PTC(value) ((TAL_INTCPUSEL1_PTC_Msk & ((value) << TAL_INTCPUSEL1_PTC_Pos))) -#define TAL_INTCPUSEL1_AES_Pos 20 /**< \brief (TAL_INTCPUSEL1) AES Interrupt CPU Select */ -#define TAL_INTCPUSEL1_AES_Msk (0x1ul << TAL_INTCPUSEL1_AES_Pos) -#define TAL_INTCPUSEL1_AES(value) ((TAL_INTCPUSEL1_AES_Msk & ((value) << TAL_INTCPUSEL1_AES_Pos))) -#define TAL_INTCPUSEL1_TRNG_Pos 22 /**< \brief (TAL_INTCPUSEL1) TRNG Interrupt CPU Select */ -#define TAL_INTCPUSEL1_TRNG_Msk (0x1ul << TAL_INTCPUSEL1_TRNG_Pos) -#define TAL_INTCPUSEL1_TRNG(value) ((TAL_INTCPUSEL1_TRNG_Msk & ((value) << TAL_INTCPUSEL1_TRNG_Pos))) -#define TAL_INTCPUSEL1_PICOP_Pos 24 /**< \brief (TAL_INTCPUSEL1) PICOP Interrupt CPU Select */ -#define TAL_INTCPUSEL1_PICOP_Msk (0x1ul << TAL_INTCPUSEL1_PICOP_Pos) -#define TAL_INTCPUSEL1_PICOP(value) ((TAL_INTCPUSEL1_PICOP_Msk & ((value) << TAL_INTCPUSEL1_PICOP_Pos))) -#define TAL_INTCPUSEL1_MASK 0x01555555ul /**< \brief (TAL_INTCPUSEL1) MASK Register */ - -/* -------- TAL_IRQTRIG : (TAL Offset: 0x60) (R/W 16) Interrupt Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ENABLE:1; /*!< bit: 0 Trigger Enable */ - uint16_t IRQNUM:5; /*!< bit: 1.. 5 Interrupt Request Number */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t OVERRIDE:8; /*!< bit: 8..15 Interrupt Request Override Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TAL_IRQTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TAL_IRQTRIG_OFFSET 0x60 /**< \brief (TAL_IRQTRIG offset) Interrupt Trigger */ -#define TAL_IRQTRIG_RESETVALUE 0x0000ul /**< \brief (TAL_IRQTRIG reset_value) Interrupt Trigger */ - -#define TAL_IRQTRIG_ENABLE_Pos 0 /**< \brief (TAL_IRQTRIG) Trigger Enable */ -#define TAL_IRQTRIG_ENABLE (0x1ul << TAL_IRQTRIG_ENABLE_Pos) -#define TAL_IRQTRIG_IRQNUM_Pos 1 /**< \brief (TAL_IRQTRIG) Interrupt Request Number */ -#define TAL_IRQTRIG_IRQNUM_Msk (0x1Ful << TAL_IRQTRIG_IRQNUM_Pos) -#define TAL_IRQTRIG_IRQNUM(value) ((TAL_IRQTRIG_IRQNUM_Msk & ((value) << TAL_IRQTRIG_IRQNUM_Pos))) -#define TAL_IRQTRIG_OVERRIDE_Pos 8 /**< \brief (TAL_IRQTRIG) Interrupt Request Override Value */ -#define TAL_IRQTRIG_OVERRIDE_Msk (0xFFul << TAL_IRQTRIG_OVERRIDE_Pos) -#define TAL_IRQTRIG_OVERRIDE(value) ((TAL_IRQTRIG_OVERRIDE_Msk & ((value) << TAL_IRQTRIG_OVERRIDE_Pos))) -#define TAL_IRQTRIG_MASK 0xFF3Ful /**< \brief (TAL_IRQTRIG) MASK Register */ - -/** \brief TalCtis hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO TAL_CTICTRLA_Type CTICTRLA; /**< \brief Offset: 0x00 (R/W 8) Cross-Trigger Interface n Control A */ - __IO TAL_CTIMASK_Type CTIMASK; /**< \brief Offset: 0x01 (R/W 8) Cross-Trigger Interface n Mask */ -} TalCtis; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief TAL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO TAL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - RoReg8 Reserved1[0x3]; - __IO TAL_RSTCTRL_Type RSTCTRL; /**< \brief Offset: 0x04 (R/W 8) Reset Control */ - __IO TAL_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x05 (R/W 8) External Break Control */ - __IO TAL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 8) Event Control */ - RoReg8 Reserved2[0x1]; - __IO TAL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ - __IO TAL_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ - __IO TAL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ - __IO TAL_GLOBMASK_Type GLOBMASK; /**< \brief Offset: 0x0B (R/W 8) Global Break Requests Mask */ - __O TAL_HALT_Type HALT; /**< \brief Offset: 0x0C ( /W 8) Debug Halt Request */ - __O TAL_RESTART_Type RESTART; /**< \brief Offset: 0x0D ( /W 8) Debug Restart Request */ - __I TAL_BRKSTATUS_Type BRKSTATUS; /**< \brief Offset: 0x0E (R/ 16) Break Request Status */ - TalCtis Ctis[4]; /**< \brief Offset: 0x10 TalCtis groups [CTI_NUM] */ - RoReg8 Reserved3[0x8]; - __I TAL_INTSTATUS_Type INTSTATUS[29]; /**< \brief Offset: 0x20 (R/ 8) Interrupt n Status */ - RoReg8 Reserved4[0x3]; - __IO TAL_DMACPUSEL0_Type DMACPUSEL0; /**< \brief Offset: 0x40 (R/W 32) DMA Channel Interrupts CPU Select 0 */ - RoReg8 Reserved5[0x4]; - __IO TAL_EVCPUSEL0_Type EVCPUSEL0; /**< \brief Offset: 0x48 (R/W 32) EVSYS Channel Interrupts CPU Select 0 */ - RoReg8 Reserved6[0x4]; - __IO TAL_EICCPUSEL0_Type EICCPUSEL0; /**< \brief Offset: 0x50 (R/W 32) EIC External Interrupts CPU Select 0 */ - RoReg8 Reserved7[0x4]; - __IO TAL_INTCPUSEL0_Type INTCPUSEL0; /**< \brief Offset: 0x58 (R/W 32) Interrupts CPU Select 0 */ - __IO TAL_INTCPUSEL1_Type INTCPUSEL1; /**< \brief Offset: 0x5C (R/W 32) Interrupts CPU Select 1 */ - __IO TAL_IRQTRIG_Type IRQTRIG; /**< \brief Offset: 0x60 (R/W 16) Interrupt Trigger */ -} Tal; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_TAL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tc.h deleted file mode 100644 index 9a9a1c93bc8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tc.h +++ /dev/null @@ -1,846 +0,0 @@ -/** - * \file - * - * \brief Component description for TC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TC_COMPONENT_ -#define _SAML21_TC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TC */ -/* ========================================================================== */ -/** \addtogroup SAML21_TC Basic Timer Counter */ -/*@{*/ - -#define TC_U2249 -#define REV_TC 0x200 - -/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */ - uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */ - uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */ - uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ -#define TC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TC_CTRLA reset_value) Control A */ - -#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ -#define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos) -#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ -#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) -#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */ -#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))) -#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */ -#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */ -#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */ -#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ -#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))) -#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */ -#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */ -#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */ -#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */ -#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos) -#define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */ -#define TC_CTRLA_ONDEMAND (0x1ul << TC_CTRLA_ONDEMAND_Pos) -#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ -#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))) -#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */ -#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */ -#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */ -#define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */ -#define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */ -#define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */ -#define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */ -#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */ -#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */ -#define TC_CTRLA_ALOCK (0x1ul << TC_CTRLA_ALOCK_Pos) -#define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */ -#define TC_CTRLA_CAPTEN0 (1 << TC_CTRLA_CAPTEN0_Pos) -#define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */ -#define TC_CTRLA_CAPTEN1 (1 << TC_CTRLA_CAPTEN1_Pos) -#define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */ -#define TC_CTRLA_CAPTEN_Msk (0x3ul << TC_CTRLA_CAPTEN_Pos) -#define TC_CTRLA_CAPTEN(value) ((TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))) -#define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */ -#define TC_CTRLA_COPEN0 (1 << TC_CTRLA_COPEN0_Pos) -#define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */ -#define TC_CTRLA_COPEN1 (1 << TC_CTRLA_COPEN1_Pos) -#define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */ -#define TC_CTRLA_COPEN_Msk (0x3ul << TC_CTRLA_COPEN_Pos) -#define TC_CTRLA_COPEN(value) ((TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))) -#define TC_CTRLA_MASK 0x00330FFFul /**< \brief (TC_CTRLA) MASK Register */ - -/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ - uint8_t :2; /*!< bit: 3.. 4 Reserved */ - uint8_t CMD:3; /*!< bit: 5.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_CTRLBCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ -#define TC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ - -#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ -#define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos) -#define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */ -#define TC_CTRLBCLR_LUPD (0x1ul << TC_CTRLBCLR_LUPD_Pos) -#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */ -#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos) -#define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */ -#define TC_CTRLBCLR_CMD_Msk (0x7ul << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))) -#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */ -#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */ -#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */ -#define TC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */ -#define TC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */ -#define TC_CTRLBCLR_CMD_DMATRG_Val 0x5ul /**< \brief (TC_CTRLBCLR) Generate DMA triggers */ -#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_DMATRG (TC_CTRLBCLR_CMD_DMATRG_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_MASK 0xE7ul /**< \brief (TC_CTRLBCLR) MASK Register */ - -/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ - uint8_t :2; /*!< bit: 3.. 4 Reserved */ - uint8_t CMD:3; /*!< bit: 5.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_CTRLBSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ -#define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */ - -#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ -#define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos) -#define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */ -#define TC_CTRLBSET_LUPD (0x1ul << TC_CTRLBSET_LUPD_Pos) -#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */ -#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos) -#define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */ -#define TC_CTRLBSET_CMD_Msk (0x7ul << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))) -#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */ -#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */ -#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */ -#define TC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TC_CTRLBSET) Force update of double-buffered register */ -#define TC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */ -#define TC_CTRLBSET_CMD_DMATRG_Val 0x5ul /**< \brief (TC_CTRLBSET) Generate DMA triggers */ -#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_DMATRG (TC_CTRLBSET_CMD_DMATRG_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_MASK 0xE7ul /**< \brief (TC_CTRLBSET) MASK Register */ - -/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */ - uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */ - uint16_t :3; /*!< bit: 9..11 Reserved */ - uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */ - uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :12; /*!< bit: 0..11 Reserved */ - uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */ -#define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */ - -#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ -#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))) -#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */ -#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ -#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */ -#define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */ -#define TC_EVCTRL_EVACT_STAMP_Val 0x4ul /**< \brief (TC_EVCTRL) Time stamp capture */ -#define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */ -#define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */ -#define TC_EVCTRL_EVACT_PW_Val 0x7ul /**< \brief (TC_EVCTRL) Pulse width capture */ -#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */ -#define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos) -#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */ -#define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos) -#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */ -#define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos) -#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */ -#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos) -#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */ -#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos) -#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */ -#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos) -#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))) -#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */ - -/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */ - uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */ - uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ -#define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */ -#define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos) -#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */ -#define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos) -#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */ -#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos) -#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */ -#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos) -#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */ -#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos) -#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))) -#define TC_INTENCLR_MASK 0x33ul /**< \brief (TC_INTENCLR) MASK Register */ - -/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */ - uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ -#define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ - -#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */ -#define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos) -#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */ -#define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos) -#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */ -#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos) -#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */ -#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos) -#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */ -#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos) -#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))) -#define TC_INTENSET_MASK 0x33ul /**< \brief (TC_INTENSET) MASK Register */ - -/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */ - uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */ - uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */ -#define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos) -#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */ -#define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos) -#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */ -#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos) -#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */ -#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos) -#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */ -#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos) -#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))) -#define TC_INTFLAG_MASK 0x33ul /**< \brief (TC_INTFLAG) MASK Register */ - -/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */ - uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */ - uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */ - uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */ -#define TC_STATUS_RESETVALUE 0x01ul /**< \brief (TC_STATUS reset_value) Status */ - -#define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */ -#define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos) -#define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */ -#define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos) -#define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */ -#define TC_STATUS_PERBUFV (0x1ul << TC_STATUS_PERBUFV_Pos) -#define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */ -#define TC_STATUS_CCBUFV0 (1 << TC_STATUS_CCBUFV0_Pos) -#define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */ -#define TC_STATUS_CCBUFV1 (1 << TC_STATUS_CCBUFV1_Pos) -#define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */ -#define TC_STATUS_CCBUFV_Msk (0x3ul << TC_STATUS_CCBUFV_Pos) -#define TC_STATUS_CCBUFV(value) ((TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))) -#define TC_STATUS_MASK 0x3Bul /**< \brief (TC_STATUS) MASK Register */ - -/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_WAVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */ -#define TC_WAVE_RESETVALUE 0x00ul /**< \brief (TC_WAVE reset_value) Waveform Generation Control */ - -#define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */ -#define TC_WAVE_WAVEGEN_Msk (0x3ul << TC_WAVE_WAVEGEN_Pos) -#define TC_WAVE_WAVEGEN(value) ((TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))) -#define TC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_WAVE) Normal frequency */ -#define TC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_WAVE) Match frequency */ -#define TC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_WAVE) Normal PWM */ -#define TC_WAVE_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_WAVE) Match PWM */ -#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos) -#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos) -#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos) -#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos) -#define TC_WAVE_MASK 0x03ul /**< \brief (TC_WAVE) MASK Register */ - -/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */ - uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_DRVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */ -#define TC_DRVCTRL_RESETVALUE 0x00ul /**< \brief (TC_DRVCTRL reset_value) Control C */ - -#define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */ -#define TC_DRVCTRL_INVEN0 (1 << TC_DRVCTRL_INVEN0_Pos) -#define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */ -#define TC_DRVCTRL_INVEN1 (1 << TC_DRVCTRL_INVEN1_Pos) -#define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */ -#define TC_DRVCTRL_INVEN_Msk (0x3ul << TC_DRVCTRL_INVEN_Pos) -#define TC_DRVCTRL_INVEN(value) ((TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))) -#define TC_DRVCTRL_MASK 0x03ul /**< \brief (TC_DRVCTRL) MASK Register */ - -/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */ -#define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */ - -#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */ -#define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos) -#define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */ - -/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 swrst */ - uint32_t ENABLE:1; /*!< bit: 1 enable */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB */ - uint32_t STATUS:1; /*!< bit: 3 STATUS */ - uint32_t COUNT:1; /*!< bit: 4 Counter */ - uint32_t PER:1; /*!< bit: 5 Period */ - uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */ - uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */ -#define TC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */ - -#define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */ -#define TC_SYNCBUSY_SWRST (0x1ul << TC_SYNCBUSY_SWRST_Pos) -#define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */ -#define TC_SYNCBUSY_ENABLE (0x1ul << TC_SYNCBUSY_ENABLE_Pos) -#define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */ -#define TC_SYNCBUSY_CTRLB (0x1ul << TC_SYNCBUSY_CTRLB_Pos) -#define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */ -#define TC_SYNCBUSY_STATUS (0x1ul << TC_SYNCBUSY_STATUS_Pos) -#define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */ -#define TC_SYNCBUSY_COUNT (0x1ul << TC_SYNCBUSY_COUNT_Pos) -#define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */ -#define TC_SYNCBUSY_PER (0x1ul << TC_SYNCBUSY_PER_Pos) -#define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */ -#define TC_SYNCBUSY_CC0 (1 << TC_SYNCBUSY_CC0_Pos) -#define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */ -#define TC_SYNCBUSY_CC1 (1 << TC_SYNCBUSY_CC1_Pos) -#define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */ -#define TC_SYNCBUSY_CC_Msk (0x3ul << TC_SYNCBUSY_CC_Pos) -#define TC_SYNCBUSY_CC(value) ((TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))) -#define TC_SYNCBUSY_MASK 0x000000FFul /**< \brief (TC_SYNCBUSY) MASK Register */ - -/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_COUNT16_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */ -#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */ - -#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */ -#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos) -#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))) -#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */ - -/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TC_COUNT32_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */ -#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */ - -#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */ -#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos) -#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))) -#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */ - -/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */ -#define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */ - -#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ -#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos) -#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))) -#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */ - -/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */ -#define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */ - -#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ -#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos) -#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))) -#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */ - -/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_COUNT16_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */ -#define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */ - -#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */ -#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos) -#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))) -#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */ - -/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TC_COUNT32_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */ -#define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */ - -#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */ -#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos) -#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))) -#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */ - -/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */ -#define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */ - -#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */ -#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos) -#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))) -#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */ - -/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PERB:8; /*!< bit: 0.. 7 Period Buffer Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_PERBUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */ -#define TC_COUNT8_PERBUF_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */ - -#define TC_COUNT8_PERBUF_PERB_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */ -#define TC_COUNT8_PERBUF_PERB_Msk (0xFFul << TC_COUNT8_PERBUF_PERB_Pos) -#define TC_COUNT8_PERBUF_PERB(value) ((TC_COUNT8_PERBUF_PERB_Msk & ((value) << TC_COUNT8_PERBUF_PERB_Pos))) -#define TC_COUNT8_PERBUF_MASK 0xFFul /**< \brief (TC_COUNT8_PERBUF) MASK Register */ - -/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_COUNT16_CCBUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */ -#define TC_COUNT16_CCBUF_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */ - -#define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */ -#define TC_COUNT16_CCBUF_CCBUF_Msk (0xFFFFul << TC_COUNT16_CCBUF_CCBUF_Pos) -#define TC_COUNT16_CCBUF_CCBUF(value) ((TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))) -#define TC_COUNT16_CCBUF_MASK 0xFFFFul /**< \brief (TC_COUNT16_CCBUF) MASK Register */ - -/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TC_COUNT32_CCBUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */ -#define TC_COUNT32_CCBUF_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */ - -#define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */ -#define TC_COUNT32_CCBUF_CCBUF_Msk (0xFFFFFFFFul << TC_COUNT32_CCBUF_CCBUF_Pos) -#define TC_COUNT32_CCBUF_CCBUF(value) ((TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))) -#define TC_COUNT32_CCBUF_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CCBUF) MASK Register */ - -/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_CCBUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */ -#define TC_COUNT8_CCBUF_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */ - -#define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */ -#define TC_COUNT8_CCBUF_CCBUF_Msk (0xFFul << TC_COUNT8_CCBUF_CCBUF_Pos) -#define TC_COUNT8_CCBUF_CCBUF(value) ((TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))) -#define TC_COUNT8_CCBUF_MASK 0xFFul /**< \brief (TC_COUNT8_CCBUF) MASK Register */ - -/** \brief TC_COUNT8 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 8-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ - __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ - __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ - __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ - __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ - __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */ - RoReg8 Reserved2[0x6]; - __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */ - __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */ - RoReg8 Reserved3[0x11]; - __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */ - __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */ -} TcCount8; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief TC_COUNT16 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 16-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ - __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ - __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ - __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ - __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ - __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */ - RoReg8 Reserved2[0x6]; - __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */ - RoReg8 Reserved3[0x10]; - __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */ -} TcCount16; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief TC_COUNT32 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 32-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ - __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ - __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ - __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ - __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ - __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */ - RoReg8 Reserved2[0x4]; - __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */ - RoReg8 Reserved3[0xC]; - __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */ -} TcCount32; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ - TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ - TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ -} Tc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_TC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tcc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tcc.h deleted file mode 100644 index 3730a728f36..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tcc.h +++ /dev/null @@ -1,1828 +0,0 @@ -/** - * \file - * - * \brief Component description for TCC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TCC_COMPONENT_ -#define _SAML21_TCC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TCC */ -/* ========================================================================== */ -/** \addtogroup SAML21_TCC Timer Counter Control */ -/*@{*/ - -#define TCC_U2213 -#define REV_TCC 0x300 - -/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t :3; /*!< bit: 2.. 4 Reserved */ - uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ - uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ - uint32_t MSYNC:1; /*!< bit: 15 Master Synchronization (only for TCC Slave Instance) */ - uint32_t :7; /*!< bit: 16..22 Reserved */ - uint32_t DTRG:1; /*!< bit: 23 DMA Trigger Mode */ - uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ - uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ - uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ - uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :24; /*!< bit: 0..23 Reserved */ - uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ -#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */ - -#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ -#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos) -#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ -#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos) -#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ -#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))) -#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */ -#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ -#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ -#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ -#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ -#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))) -#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */ -#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */ -#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */ -#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */ -#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */ -#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */ -#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */ -#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */ -#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ -#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos) -#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ -#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))) -#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ -#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ -#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ -#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ -#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos) -#define TCC_CTRLA_MSYNC_Pos 15 /**< \brief (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) */ -#define TCC_CTRLA_MSYNC (0x1ul << TCC_CTRLA_MSYNC_Pos) -#define TCC_CTRLA_DTRG_Pos 23 /**< \brief (TCC_CTRLA) DMA Trigger Mode */ -#define TCC_CTRLA_DTRG (0x1ul << TCC_CTRLA_DTRG_Pos) -#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ -#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) -#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ -#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) -#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ -#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) -#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ -#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) -#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ -#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos) -#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))) -#define TCC_CTRLA_MASK 0x0F80FF63ul /**< \brief (TCC_CTRLA) MASK Register */ - -/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_CTRLBCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ -#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ - -#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ -#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos) -#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ -#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos) -#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ -#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos) -#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ -#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))) -#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ -#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ -#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ -#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ -#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ -#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))) -#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */ -#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ -#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */ -#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */ -#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ -#define TCC_CTRLBCLR_CMD_DMATRG_Val 0x5ul /**< \brief (TCC_CTRLBCLR) Generate DMA triggers */ -#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_DMATRG (TCC_CTRLBCLR_CMD_DMATRG_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */ - -/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_CTRLBSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ -#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ - -#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ -#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos) -#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ -#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos) -#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ -#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos) -#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ -#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))) -#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ -#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ -#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ -#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ -#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ -#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))) -#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */ -#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ -#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */ -#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */ -#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ -#define TCC_CTRLBSET_CMD_DMATRG_Val 0x5ul /**< \brief (TCC_CTRLBSET) Generate DMA triggers */ -#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_DMATRG (TCC_CTRLBSET_CMD_DMATRG_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */ - -/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ - uint32_t STATUS:1; /*!< bit: 3 Status Busy */ - uint32_t COUNT:1; /*!< bit: 4 Count Busy */ - uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ - uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ - uint32_t PER:1; /*!< bit: 7 Period Busy */ - uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ - uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ - uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ - uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ -#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ - -#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ -#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos) -#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ -#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos) -#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ -#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos) -#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ -#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos) -#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ -#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos) -#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ -#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos) -#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ -#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos) -#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period Busy */ -#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos) -#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ -#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) -#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ -#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) -#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ -#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) -#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ -#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) -#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ -#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos) -#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))) -#define TCC_SYNCBUSY_MASK 0x00000FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */ - -/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ - uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_FCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ -#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ - -#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ -#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))) -#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */ -#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ -#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ -#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ -#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ -#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos) -#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ -#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos) -#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ -#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))) -#define TCC_FCTRLA_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLA) Blanking applied from start of the ramp */ -#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ -#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ -#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ -#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ -#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos) -#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ -#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))) -#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */ -#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */ -#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */ -#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */ -#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ -#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))) -#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ -#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ -#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ -#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ -#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ -#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))) -#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */ -#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */ -#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */ -#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */ -#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */ -#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */ -#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ -#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */ -#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */ -#define TCC_FCTRLA_BLANKPRESC (0x1ul << TCC_FCTRLA_BLANKPRESC_Pos) -#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ -#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos) -#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))) -#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ -#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos) -#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))) -#define TCC_FCTRLA_MASK 0x0FFFFFFBul /**< \brief (TCC_FCTRLA) MASK Register */ - -/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ - uint32_t BLANKPRESC:1; /*!< bit: 15 Fault B Blanking Prescaler */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_FCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ -#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ - -#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ -#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))) -#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */ -#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ -#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ -#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ -#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ -#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos) -#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ -#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos) -#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ -#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))) -#define TCC_FCTRLB_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLB) Blanking applied from start of the ramp */ -#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ -#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ -#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ -#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ -#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos) -#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ -#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))) -#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */ -#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */ -#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */ -#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */ -#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ -#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))) -#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ -#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ -#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ -#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ -#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ -#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))) -#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */ -#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */ -#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */ -#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */ -#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */ -#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */ -#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ -#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */ -#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */ -#define TCC_FCTRLB_BLANKPRESC (0x1ul << TCC_FCTRLB_BLANKPRESC_Pos) -#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ -#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos) -#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))) -#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ -#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos) -#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))) -#define TCC_FCTRLB_MASK 0x0FFFFFFBul /**< \brief (TCC_FCTRLB) MASK Register */ - -/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ - uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ - uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ - uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ - uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WEXCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ -#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ - -#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ -#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos) -#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))) -#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ -#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) -#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ -#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) -#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ -#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) -#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ -#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) -#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ -#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos) -#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))) -#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ -#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos) -#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))) -#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ -#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos) -#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))) -#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */ - -/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ - uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ - uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ - uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ - uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ - uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ - uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ - uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ - uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ - uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ - uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ - uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ - uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ - uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ - uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ - uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ - uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ - uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ - uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ - uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ - uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ - uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ - uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ - uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ - uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ - uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ - uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ - uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_DRVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ -#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ - -#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ -#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) -#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ -#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) -#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ -#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) -#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ -#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) -#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ -#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) -#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ -#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) -#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ -#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) -#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ -#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) -#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ -#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos) -#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))) -#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ -#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) -#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ -#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) -#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ -#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) -#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ -#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) -#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ -#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) -#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ -#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) -#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ -#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) -#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ -#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) -#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ -#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos) -#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))) -#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ -#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) -#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ -#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) -#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ -#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) -#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ -#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) -#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ -#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) -#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ -#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) -#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ -#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) -#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ -#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) -#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ -#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos) -#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))) -#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ -#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos) -#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))) -#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ -#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos) -#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))) -#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */ - -/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ -#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ - -#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ -#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos) -#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ -#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos) -#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */ - -/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ - uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ - uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ - uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ - uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ - uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ - uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ - uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ - uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ - uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ - uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ - uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ - uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ - uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ - uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ - uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :12; /*!< bit: 0..11 Reserved */ - uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ - uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ - uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ -#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */ - -#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ -#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))) -#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ -#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ -#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */ -#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */ -#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */ -#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ -#define TCC_EVCTRL_EVACT0_STAMP_Val 0x6ul /**< \brief (TCC_EVCTRL) Stamp capture */ -#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ -#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ -#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))) -#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ -#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ -#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */ -#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */ -#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */ -#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ -#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ -#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ -#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ -#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))) -#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ -#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ -#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ -#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ -#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ -#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos) -#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ -#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos) -#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ -#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos) -#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ -#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) -#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ -#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) -#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ -#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos) -#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))) -#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ -#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) -#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ -#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) -#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ -#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos) -#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))) -#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ -#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) -#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ -#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) -#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ -#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) -#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ -#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) -#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ -#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos) -#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))) -#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ -#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) -#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ -#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) -#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ -#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) -#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ -#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) -#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ -#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos) -#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))) -#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */ - -/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ -#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ -#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos) -#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ -#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos) -#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ -#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos) -#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ -#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos) -#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */ -#define TCC_INTENCLR_UFS (0x1ul << TCC_INTENCLR_UFS_Pos) -#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ -#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos) -#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ -#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos) -#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ -#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos) -#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ -#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos) -#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ -#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos) -#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ -#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) -#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ -#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) -#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ -#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) -#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ -#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) -#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ -#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos) -#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))) -#define TCC_INTENCLR_MASK 0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */ - -/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ -#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ - -#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ -#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos) -#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ -#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos) -#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ -#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos) -#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ -#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos) -#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */ -#define TCC_INTENSET_UFS (0x1ul << TCC_INTENSET_UFS_Pos) -#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ -#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos) -#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ -#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos) -#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ -#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos) -#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ -#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos) -#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ -#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos) -#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ -#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) -#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ -#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) -#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ -#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) -#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ -#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) -#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ -#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos) -#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))) -#define TCC_INTENSET_MASK 0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */ - -/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow */ - uint32_t TRG:1; /*!< bit: 1 Retrigger */ - uint32_t CNT:1; /*!< bit: 2 Counter */ - uint32_t ERR:1; /*!< bit: 3 Error */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ -#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos) -#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ -#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos) -#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ -#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos) -#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ -#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos) -#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */ -#define TCC_INTFLAG_UFS (0x1ul << TCC_INTFLAG_UFS_Pos) -#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ -#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos) -#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ -#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos) -#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ -#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos) -#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ -#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos) -#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ -#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos) -#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ -#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) -#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ -#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) -#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ -#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) -#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ -#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) -#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ -#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos) -#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))) -#define TCC_INTFLAG_MASK 0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */ - -/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t STOP:1; /*!< bit: 0 Stop */ - uint32_t IDX:1; /*!< bit: 1 Ramp */ - uint32_t UFS:1; /*!< bit: 2 Non-recoverable Update Fault State */ - uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ - uint32_t SLAVE:1; /*!< bit: 4 Slave */ - uint32_t PATTBUFV:1; /*!< bit: 5 Pattern Buffer Valid */ - uint32_t WAVEBUFV:1; /*!< bit: 6 Wave Buffer Valid */ - uint32_t PERBUFV:1; /*!< bit: 7 Period Buffer Valid */ - uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ - uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ - uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ - uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ - uint32_t CCBUFV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ - uint32_t CCBUFV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ - uint32_t CCBUFV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ - uint32_t CCBUFV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ - uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ - uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ - uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CCBUFV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ -#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */ - -#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ -#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos) -#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ -#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos) -#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-recoverable Update Fault State */ -#define TCC_STATUS_UFS (0x1ul << TCC_STATUS_UFS_Pos) -#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ -#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos) -#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ -#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos) -#define TCC_STATUS_PATTBUFV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ -#define TCC_STATUS_PATTBUFV (0x1ul << TCC_STATUS_PATTBUFV_Pos) -#define TCC_STATUS_WAVEBUFV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ -#define TCC_STATUS_WAVEBUFV (0x1ul << TCC_STATUS_WAVEBUFV_Pos) -#define TCC_STATUS_PERBUFV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ -#define TCC_STATUS_PERBUFV (0x1ul << TCC_STATUS_PERBUFV_Pos) -#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ -#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos) -#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ -#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos) -#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ -#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos) -#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ -#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos) -#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ -#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos) -#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ -#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos) -#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ -#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos) -#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ -#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos) -#define TCC_STATUS_CCBUFV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ -#define TCC_STATUS_CCBUFV0 (1 << TCC_STATUS_CCBUFV0_Pos) -#define TCC_STATUS_CCBUFV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ -#define TCC_STATUS_CCBUFV1 (1 << TCC_STATUS_CCBUFV1_Pos) -#define TCC_STATUS_CCBUFV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ -#define TCC_STATUS_CCBUFV2 (1 << TCC_STATUS_CCBUFV2_Pos) -#define TCC_STATUS_CCBUFV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ -#define TCC_STATUS_CCBUFV3 (1 << TCC_STATUS_CCBUFV3_Pos) -#define TCC_STATUS_CCBUFV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ -#define TCC_STATUS_CCBUFV_Msk (0xFul << TCC_STATUS_CCBUFV_Pos) -#define TCC_STATUS_CCBUFV(value) ((TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos))) -#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ -#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) -#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ -#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) -#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ -#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) -#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ -#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) -#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ -#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos) -#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))) -#define TCC_STATUS_MASK 0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */ - -/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ -#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */ - -// DITH4 mode -#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ -#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos) -#define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))) -#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ -#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos) -#define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))) -#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ -#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos) -#define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))) -#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */ - -#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ -#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos) -#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))) -#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */ - -/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ - uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ - uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ - uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ - uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ - uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ - uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ - uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ - uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ - uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ - uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ - uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ - uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ - uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ - uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ - uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ - uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TCC_PATT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ -#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */ - -#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ -#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) -#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ -#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) -#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ -#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) -#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ -#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) -#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ -#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) -#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ -#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) -#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ -#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) -#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ -#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) -#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ -#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos) -#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))) -#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ -#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) -#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ -#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) -#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ -#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) -#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ -#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) -#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ -#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) -#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ -#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) -#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ -#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) -#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ -#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) -#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ -#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos) -#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))) -#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */ - -/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ - uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ - uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ - uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ - uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ - uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ - uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ - uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ - uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ - uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ - uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WAVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ -#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */ - -#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ -#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))) -#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */ -#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */ -#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */ -#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */ -#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ -#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ -#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ -#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ -#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))) -#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */ -#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVE) Critical RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ -#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos) -#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ -#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) -#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ -#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) -#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ -#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) -#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ -#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) -#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ -#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos) -#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))) -#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ -#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) -#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ -#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) -#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ -#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) -#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ -#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) -#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ -#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos) -#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))) -#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ -#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) -#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ -#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) -#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ -#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) -#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ -#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) -#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ -#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos) -#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))) -#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */ - -/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t PER:20; /*!< bit: 4..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t PER:19; /*!< bit: 5..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t PER:18; /*!< bit: 6..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PER:24; /*!< bit: 0..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ -#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */ - -// DITH4 mode -#define TCC_PER_DITH4_DITHER_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ -#define TCC_PER_DITH4_DITHER_Msk (0xFul << TCC_PER_DITH4_DITHER_Pos) -#define TCC_PER_DITH4_DITHER(value) ((TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos))) -#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ -#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos) -#define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))) -#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_PER_DITH5_DITHER_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ -#define TCC_PER_DITH5_DITHER_Msk (0x1Ful << TCC_PER_DITH5_DITHER_Pos) -#define TCC_PER_DITH5_DITHER(value) ((TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos))) -#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ -#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos) -#define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))) -#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_PER_DITH6_DITHER_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ -#define TCC_PER_DITH6_DITHER_Msk (0x3Ful << TCC_PER_DITH6_DITHER_Pos) -#define TCC_PER_DITH6_DITHER(value) ((TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos))) -#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ -#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos) -#define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))) -#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */ - -#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ -#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos) -#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))) -#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */ - -/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ -#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */ - -// DITH4 mode -#define TCC_CC_DITH4_DITHER_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ -#define TCC_CC_DITH4_DITHER_Msk (0xFul << TCC_CC_DITH4_DITHER_Pos) -#define TCC_CC_DITH4_DITHER(value) ((TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos))) -#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ -#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos) -#define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))) -#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_CC_DITH5_DITHER_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ -#define TCC_CC_DITH5_DITHER_Msk (0x1Ful << TCC_CC_DITH5_DITHER_Pos) -#define TCC_CC_DITH5_DITHER(value) ((TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos))) -#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ -#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos) -#define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))) -#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_CC_DITH6_DITHER_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ -#define TCC_CC_DITH6_DITHER_Msk (0x3Ful << TCC_CC_DITH6_DITHER_Pos) -#define TCC_CC_DITH6_DITHER(value) ((TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos))) -#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ -#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos) -#define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))) -#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */ - -#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ -#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos) -#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))) -#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */ - -/* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ - uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ - uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ - uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ - uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ - uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ - uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ - uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ - uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ - uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ - uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ - uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ - uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ - uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ - uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ - uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ - uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TCC_PATTBUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PATTBUF_OFFSET 0x64 /**< \brief (TCC_PATTBUF offset) Pattern Buffer */ -#define TCC_PATTBUF_RESETVALUE 0x0000ul /**< \brief (TCC_PATTBUF reset_value) Pattern Buffer */ - -#define TCC_PATTBUF_PGEB0_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer */ -#define TCC_PATTBUF_PGEB0 (1 << TCC_PATTBUF_PGEB0_Pos) -#define TCC_PATTBUF_PGEB1_Pos 1 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer */ -#define TCC_PATTBUF_PGEB1 (1 << TCC_PATTBUF_PGEB1_Pos) -#define TCC_PATTBUF_PGEB2_Pos 2 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer */ -#define TCC_PATTBUF_PGEB2 (1 << TCC_PATTBUF_PGEB2_Pos) -#define TCC_PATTBUF_PGEB3_Pos 3 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer */ -#define TCC_PATTBUF_PGEB3 (1 << TCC_PATTBUF_PGEB3_Pos) -#define TCC_PATTBUF_PGEB4_Pos 4 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer */ -#define TCC_PATTBUF_PGEB4 (1 << TCC_PATTBUF_PGEB4_Pos) -#define TCC_PATTBUF_PGEB5_Pos 5 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer */ -#define TCC_PATTBUF_PGEB5 (1 << TCC_PATTBUF_PGEB5_Pos) -#define TCC_PATTBUF_PGEB6_Pos 6 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer */ -#define TCC_PATTBUF_PGEB6 (1 << TCC_PATTBUF_PGEB6_Pos) -#define TCC_PATTBUF_PGEB7_Pos 7 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer */ -#define TCC_PATTBUF_PGEB7 (1 << TCC_PATTBUF_PGEB7_Pos) -#define TCC_PATTBUF_PGEB_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable Buffer */ -#define TCC_PATTBUF_PGEB_Msk (0xFFul << TCC_PATTBUF_PGEB_Pos) -#define TCC_PATTBUF_PGEB(value) ((TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos))) -#define TCC_PATTBUF_PGVB0_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable */ -#define TCC_PATTBUF_PGVB0 (1 << TCC_PATTBUF_PGVB0_Pos) -#define TCC_PATTBUF_PGVB1_Pos 9 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable */ -#define TCC_PATTBUF_PGVB1 (1 << TCC_PATTBUF_PGVB1_Pos) -#define TCC_PATTBUF_PGVB2_Pos 10 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable */ -#define TCC_PATTBUF_PGVB2 (1 << TCC_PATTBUF_PGVB2_Pos) -#define TCC_PATTBUF_PGVB3_Pos 11 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable */ -#define TCC_PATTBUF_PGVB3 (1 << TCC_PATTBUF_PGVB3_Pos) -#define TCC_PATTBUF_PGVB4_Pos 12 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable */ -#define TCC_PATTBUF_PGVB4 (1 << TCC_PATTBUF_PGVB4_Pos) -#define TCC_PATTBUF_PGVB5_Pos 13 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable */ -#define TCC_PATTBUF_PGVB5 (1 << TCC_PATTBUF_PGVB5_Pos) -#define TCC_PATTBUF_PGVB6_Pos 14 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable */ -#define TCC_PATTBUF_PGVB6 (1 << TCC_PATTBUF_PGVB6_Pos) -#define TCC_PATTBUF_PGVB7_Pos 15 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable */ -#define TCC_PATTBUF_PGVB7 (1 << TCC_PATTBUF_PGVB7_Pos) -#define TCC_PATTBUF_PGVB_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable */ -#define TCC_PATTBUF_PGVB_Msk (0xFFul << TCC_PATTBUF_PGVB_Pos) -#define TCC_PATTBUF_PGVB(value) ((TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos))) -#define TCC_PATTBUF_MASK 0xFFFFul /**< \brief (TCC_PATTBUF) MASK Register */ - -/* -------- TCC_WAVEBUF : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ - uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ - uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ - uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ - uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ - uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ - uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ - uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ - uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ - uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ - uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WAVEBUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WAVEBUF_OFFSET 0x68 /**< \brief (TCC_WAVEBUF offset) Waveform Control Buffer */ -#define TCC_WAVEBUF_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEBUF reset_value) Waveform Control Buffer */ - -#define TCC_WAVEBUF_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEBUF) Waveform Generation Buffer */ -#define TCC_WAVEBUF_WAVEGENB_Msk (0x7ul << TCC_WAVEBUF_WAVEGENB_Pos) -#define TCC_WAVEBUF_WAVEGENB(value) ((TCC_WAVEBUF_WAVEGENB_Msk & ((value) << TCC_WAVEBUF_WAVEGENB_Pos))) -#define TCC_WAVEBUF_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEBUF) Normal frequency */ -#define TCC_WAVEBUF_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEBUF) Match frequency */ -#define TCC_WAVEBUF_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEBUF) Normal PWM */ -#define TCC_WAVEBUF_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEBUF) Dual-slope critical */ -#define TCC_WAVEBUF_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEBUF) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ -#define TCC_WAVEBUF_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEBUF) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ -#define TCC_WAVEBUF_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEBUF) Dual-slope with interrupt/event condition when COUNT reaches TOP */ -#define TCC_WAVEBUF_WAVEGENB_NFRQ (TCC_WAVEBUF_WAVEGENB_NFRQ_Val << TCC_WAVEBUF_WAVEGENB_Pos) -#define TCC_WAVEBUF_WAVEGENB_MFRQ (TCC_WAVEBUF_WAVEGENB_MFRQ_Val << TCC_WAVEBUF_WAVEGENB_Pos) -#define TCC_WAVEBUF_WAVEGENB_NPWM (TCC_WAVEBUF_WAVEGENB_NPWM_Val << TCC_WAVEBUF_WAVEGENB_Pos) -#define TCC_WAVEBUF_WAVEGENB_DSCRITICAL (TCC_WAVEBUF_WAVEGENB_DSCRITICAL_Val << TCC_WAVEBUF_WAVEGENB_Pos) -#define TCC_WAVEBUF_WAVEGENB_DSBOTTOM (TCC_WAVEBUF_WAVEGENB_DSBOTTOM_Val << TCC_WAVEBUF_WAVEGENB_Pos) -#define TCC_WAVEBUF_WAVEGENB_DSBOTH (TCC_WAVEBUF_WAVEGENB_DSBOTH_Val << TCC_WAVEBUF_WAVEGENB_Pos) -#define TCC_WAVEBUF_WAVEGENB_DSTOP (TCC_WAVEBUF_WAVEGENB_DSTOP_Val << TCC_WAVEBUF_WAVEGENB_Pos) -#define TCC_WAVEBUF_RAMPB_Pos 4 /**< \brief (TCC_WAVEBUF) Ramp Mode Buffer */ -#define TCC_WAVEBUF_RAMPB_Msk (0x3ul << TCC_WAVEBUF_RAMPB_Pos) -#define TCC_WAVEBUF_RAMPB(value) ((TCC_WAVEBUF_RAMPB_Msk & ((value) << TCC_WAVEBUF_RAMPB_Pos))) -#define TCC_WAVEBUF_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEBUF) RAMP1 operation */ -#define TCC_WAVEBUF_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEBUF) Alternative RAMP2 operation */ -#define TCC_WAVEBUF_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEBUF) RAMP2 operation */ -#define TCC_WAVEBUF_RAMPB_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVEBUF) Critical RAMP2 operation */ -#define TCC_WAVEBUF_RAMPB_RAMP1 (TCC_WAVEBUF_RAMPB_RAMP1_Val << TCC_WAVEBUF_RAMPB_Pos) -#define TCC_WAVEBUF_RAMPB_RAMP2A (TCC_WAVEBUF_RAMPB_RAMP2A_Val << TCC_WAVEBUF_RAMPB_Pos) -#define TCC_WAVEBUF_RAMPB_RAMP2 (TCC_WAVEBUF_RAMPB_RAMP2_Val << TCC_WAVEBUF_RAMPB_Pos) -#define TCC_WAVEBUF_RAMPB_RAMP2C (TCC_WAVEBUF_RAMPB_RAMP2C_Val << TCC_WAVEBUF_RAMPB_Pos) -#define TCC_WAVEBUF_CIPERENB_Pos 7 /**< \brief (TCC_WAVEBUF) Circular Period Enable Buffer */ -#define TCC_WAVEBUF_CIPERENB (0x1ul << TCC_WAVEBUF_CIPERENB_Pos) -#define TCC_WAVEBUF_CICCENB0_Pos 8 /**< \brief (TCC_WAVEBUF) Circular Channel 0 Enable Buffer */ -#define TCC_WAVEBUF_CICCENB0 (1 << TCC_WAVEBUF_CICCENB0_Pos) -#define TCC_WAVEBUF_CICCENB1_Pos 9 /**< \brief (TCC_WAVEBUF) Circular Channel 1 Enable Buffer */ -#define TCC_WAVEBUF_CICCENB1 (1 << TCC_WAVEBUF_CICCENB1_Pos) -#define TCC_WAVEBUF_CICCENB2_Pos 10 /**< \brief (TCC_WAVEBUF) Circular Channel 2 Enable Buffer */ -#define TCC_WAVEBUF_CICCENB2 (1 << TCC_WAVEBUF_CICCENB2_Pos) -#define TCC_WAVEBUF_CICCENB3_Pos 11 /**< \brief (TCC_WAVEBUF) Circular Channel 3 Enable Buffer */ -#define TCC_WAVEBUF_CICCENB3 (1 << TCC_WAVEBUF_CICCENB3_Pos) -#define TCC_WAVEBUF_CICCENB_Pos 8 /**< \brief (TCC_WAVEBUF) Circular Channel x Enable Buffer */ -#define TCC_WAVEBUF_CICCENB_Msk (0xFul << TCC_WAVEBUF_CICCENB_Pos) -#define TCC_WAVEBUF_CICCENB(value) ((TCC_WAVEBUF_CICCENB_Msk & ((value) << TCC_WAVEBUF_CICCENB_Pos))) -#define TCC_WAVEBUF_POLB0_Pos 16 /**< \brief (TCC_WAVEBUF) Channel 0 Polarity Buffer */ -#define TCC_WAVEBUF_POLB0 (1 << TCC_WAVEBUF_POLB0_Pos) -#define TCC_WAVEBUF_POLB1_Pos 17 /**< \brief (TCC_WAVEBUF) Channel 1 Polarity Buffer */ -#define TCC_WAVEBUF_POLB1 (1 << TCC_WAVEBUF_POLB1_Pos) -#define TCC_WAVEBUF_POLB2_Pos 18 /**< \brief (TCC_WAVEBUF) Channel 2 Polarity Buffer */ -#define TCC_WAVEBUF_POLB2 (1 << TCC_WAVEBUF_POLB2_Pos) -#define TCC_WAVEBUF_POLB3_Pos 19 /**< \brief (TCC_WAVEBUF) Channel 3 Polarity Buffer */ -#define TCC_WAVEBUF_POLB3 (1 << TCC_WAVEBUF_POLB3_Pos) -#define TCC_WAVEBUF_POLB_Pos 16 /**< \brief (TCC_WAVEBUF) Channel x Polarity Buffer */ -#define TCC_WAVEBUF_POLB_Msk (0xFul << TCC_WAVEBUF_POLB_Pos) -#define TCC_WAVEBUF_POLB(value) ((TCC_WAVEBUF_POLB_Msk & ((value) << TCC_WAVEBUF_POLB_Pos))) -#define TCC_WAVEBUF_SWAPB0_Pos 24 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair 0 Buffer */ -#define TCC_WAVEBUF_SWAPB0 (1 << TCC_WAVEBUF_SWAPB0_Pos) -#define TCC_WAVEBUF_SWAPB1_Pos 25 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair 1 Buffer */ -#define TCC_WAVEBUF_SWAPB1 (1 << TCC_WAVEBUF_SWAPB1_Pos) -#define TCC_WAVEBUF_SWAPB2_Pos 26 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair 2 Buffer */ -#define TCC_WAVEBUF_SWAPB2 (1 << TCC_WAVEBUF_SWAPB2_Pos) -#define TCC_WAVEBUF_SWAPB3_Pos 27 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair 3 Buffer */ -#define TCC_WAVEBUF_SWAPB3 (1 << TCC_WAVEBUF_SWAPB3_Pos) -#define TCC_WAVEBUF_SWAPB_Pos 24 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair x Buffer */ -#define TCC_WAVEBUF_SWAPB_Msk (0xFul << TCC_WAVEBUF_SWAPB_Pos) -#define TCC_WAVEBUF_SWAPB(value) ((TCC_WAVEBUF_SWAPB_Msk & ((value) << TCC_WAVEBUF_SWAPB_Pos))) -#define TCC_WAVEBUF_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEBUF) MASK Register */ - -/* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERBUF:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t PERBUF:20; /*!< bit: 4..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t PERBUF:19; /*!< bit: 5..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t PERBUF:18; /*!< bit: 6..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PERBUF:24; /*!< bit: 0..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_PERBUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PERBUF_OFFSET 0x6C /**< \brief (TCC_PERBUF offset) Period Buffer */ -#define TCC_PERBUF_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERBUF reset_value) Period Buffer */ - -// DITH4 mode -#define TCC_PERBUF_DITH4_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number */ -#define TCC_PERBUF_DITH4_DITHERBUF_Msk (0xFul << TCC_PERBUF_DITH4_DITHERBUF_Pos) -#define TCC_PERBUF_DITH4_DITHERBUF(value) ((TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))) -#define TCC_PERBUF_DITH4_PERBUF_Pos 4 /**< \brief (TCC_PERBUF_DITH4) Period Buffer Value */ -#define TCC_PERBUF_DITH4_PERBUF_Msk (0xFFFFFul << TCC_PERBUF_DITH4_PERBUF_Pos) -#define TCC_PERBUF_DITH4_PERBUF(value) ((TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos))) -#define TCC_PERBUF_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERBUF_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_PERBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number */ -#define TCC_PERBUF_DITH5_DITHERBUF_Msk (0x1Ful << TCC_PERBUF_DITH5_DITHERBUF_Pos) -#define TCC_PERBUF_DITH5_DITHERBUF(value) ((TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))) -#define TCC_PERBUF_DITH5_PERBUF_Pos 5 /**< \brief (TCC_PERBUF_DITH5) Period Buffer Value */ -#define TCC_PERBUF_DITH5_PERBUF_Msk (0x7FFFFul << TCC_PERBUF_DITH5_PERBUF_Pos) -#define TCC_PERBUF_DITH5_PERBUF(value) ((TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos))) -#define TCC_PERBUF_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERBUF_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_PERBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number */ -#define TCC_PERBUF_DITH6_DITHERBUF_Msk (0x3Ful << TCC_PERBUF_DITH6_DITHERBUF_Pos) -#define TCC_PERBUF_DITH6_DITHERBUF(value) ((TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))) -#define TCC_PERBUF_DITH6_PERBUF_Pos 6 /**< \brief (TCC_PERBUF_DITH6) Period Buffer Value */ -#define TCC_PERBUF_DITH6_PERBUF_Msk (0x3FFFFul << TCC_PERBUF_DITH6_PERBUF_Pos) -#define TCC_PERBUF_DITH6_PERBUF(value) ((TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos))) -#define TCC_PERBUF_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERBUF_DITH6) MASK Register */ - -#define TCC_PERBUF_PERBUF_Pos 0 /**< \brief (TCC_PERBUF) Period Buffer Value */ -#define TCC_PERBUF_PERBUF_Msk (0xFFFFFFul << TCC_PERBUF_PERBUF_Pos) -#define TCC_PERBUF_PERBUF(value) ((TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos))) -#define TCC_PERBUF_MASK 0x00FFFFFFul /**< \brief (TCC_PERBUF) MASK Register */ - -/* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t CCBUF:4; /*!< bit: 0.. 3 Channel Compare/Capture Buffer Value */ - uint32_t DITHERBUF:20; /*!< bit: 4..23 Dithering Buffer Cycle Number */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t CCBUF:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t CCBUF:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CCBUF:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CCBUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CCBUF_OFFSET 0x70 /**< \brief (TCC_CCBUF offset) Compare and Capture Buffer */ -#define TCC_CCBUF_RESETVALUE 0x00000000ul /**< \brief (TCC_CCBUF reset_value) Compare and Capture Buffer */ - -// DITH4 mode -#define TCC_CCBUF_DITH4_CCBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value */ -#define TCC_CCBUF_DITH4_CCBUF_Msk (0xFul << TCC_CCBUF_DITH4_CCBUF_Pos) -#define TCC_CCBUF_DITH4_CCBUF(value) ((TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos))) -#define TCC_CCBUF_DITH4_DITHERBUF_Pos 4 /**< \brief (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number */ -#define TCC_CCBUF_DITH4_DITHERBUF_Msk (0xFFFFFul << TCC_CCBUF_DITH4_DITHERBUF_Pos) -#define TCC_CCBUF_DITH4_DITHERBUF(value) ((TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))) -#define TCC_CCBUF_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCBUF_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_CCBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number */ -#define TCC_CCBUF_DITH5_DITHERBUF_Msk (0x1Ful << TCC_CCBUF_DITH5_DITHERBUF_Pos) -#define TCC_CCBUF_DITH5_DITHERBUF(value) ((TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))) -#define TCC_CCBUF_DITH5_CCBUF_Pos 5 /**< \brief (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value */ -#define TCC_CCBUF_DITH5_CCBUF_Msk (0x7FFFFul << TCC_CCBUF_DITH5_CCBUF_Pos) -#define TCC_CCBUF_DITH5_CCBUF(value) ((TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos))) -#define TCC_CCBUF_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCBUF_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_CCBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number */ -#define TCC_CCBUF_DITH6_DITHERBUF_Msk (0x3Ful << TCC_CCBUF_DITH6_DITHERBUF_Pos) -#define TCC_CCBUF_DITH6_DITHERBUF(value) ((TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))) -#define TCC_CCBUF_DITH6_CCBUF_Pos 6 /**< \brief (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value */ -#define TCC_CCBUF_DITH6_CCBUF_Msk (0x3FFFFul << TCC_CCBUF_DITH6_CCBUF_Pos) -#define TCC_CCBUF_DITH6_CCBUF(value) ((TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos))) -#define TCC_CCBUF_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCBUF_DITH6) MASK Register */ - -#define TCC_CCBUF_CCBUF_Pos 0 /**< \brief (TCC_CCBUF) Channel Compare/Capture Buffer Value */ -#define TCC_CCBUF_CCBUF_Msk (0xFFFFFFul << TCC_CCBUF_CCBUF_Pos) -#define TCC_CCBUF_CCBUF(value) ((TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos))) -#define TCC_CCBUF_MASK 0x00FFFFFFul /**< \brief (TCC_CCBUF) MASK Register */ - -/** \brief TCC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - RoReg8 Reserved1[0x2]; - __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ - __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ - __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ - __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ - RoReg8 Reserved2[0x2]; - __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ - RoReg8 Reserved3[0x1]; - __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ - __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ - __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ - __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ - __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ - __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ - __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ - RoReg8 Reserved4[0x2]; - __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ - __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ - __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ - RoReg8 Reserved5[0x10]; - __IO TCC_PATTBUF_Type PATTBUF; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ - RoReg8 Reserved6[0x2]; - __IO TCC_WAVEBUF_Type WAVEBUF; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ - __IO TCC_PERBUF_Type PERBUF; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ - __IO TCC_CCBUF_Type CCBUF[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ -} Tcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_TCC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_trng.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_trng.h deleted file mode 100644 index 831ce0993f4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_trng.h +++ /dev/null @@ -1,189 +0,0 @@ -/** - * \file - * - * \brief Component description for TRNG - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TRNG_COMPONENT_ -#define _SAML21_TRNG_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TRNG */ -/* ========================================================================== */ -/** \addtogroup SAML21_TRNG True Random Generator */ -/*@{*/ - -#define TRNG_U2242 -#define REV_TRNG 0x100 - -/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TRNG_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */ -#define TRNG_CTRLA_RESETVALUE 0x00ul /**< \brief (TRNG_CTRLA reset_value) Control A */ - -#define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */ -#define TRNG_CTRLA_ENABLE (0x1ul << TRNG_CTRLA_ENABLE_Pos) -#define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */ -#define TRNG_CTRLA_RUNSTDBY (0x1ul << TRNG_CTRLA_RUNSTDBY_Pos) -#define TRNG_CTRLA_MASK 0x42ul /**< \brief (TRNG_CTRLA) MASK Register */ - -/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TRNG_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */ -#define TRNG_EVCTRL_RESETVALUE 0x00ul /**< \brief (TRNG_EVCTRL reset_value) Event Control */ - -#define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */ -#define TRNG_EVCTRL_DATARDYEO (0x1ul << TRNG_EVCTRL_DATARDYEO_Pos) -#define TRNG_EVCTRL_MASK 0x01ul /**< \brief (TRNG_EVCTRL) MASK Register */ - -/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TRNG_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */ -#define TRNG_INTENCLR_RESETVALUE 0x00ul /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */ -#define TRNG_INTENCLR_DATARDY (0x1ul << TRNG_INTENCLR_DATARDY_Pos) -#define TRNG_INTENCLR_MASK 0x01ul /**< \brief (TRNG_INTENCLR) MASK Register */ - -/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TRNG_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */ -#define TRNG_INTENSET_RESETVALUE 0x00ul /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */ - -#define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */ -#define TRNG_INTENSET_DATARDY (0x1ul << TRNG_INTENSET_DATARDY_Pos) -#define TRNG_INTENSET_MASK 0x01ul /**< \brief (TRNG_INTENSET) MASK Register */ - -/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TRNG_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TRNG_INTFLAG_RESETVALUE 0x00ul /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */ -#define TRNG_INTFLAG_DATARDY (0x1ul << TRNG_INTFLAG_DATARDY_Pos) -#define TRNG_INTFLAG_MASK 0x01ul /**< \brief (TRNG_INTFLAG) MASK Register */ - -/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Output Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TRNG_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */ -#define TRNG_DATA_RESETVALUE 0x00000000ul /**< \brief (TRNG_DATA reset_value) Output Data */ - -#define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */ -#define TRNG_DATA_DATA_Msk (0xFFFFFFFFul << TRNG_DATA_DATA_Pos) -#define TRNG_DATA_DATA(value) ((TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))) -#define TRNG_DATA_MASK 0xFFFFFFFFul /**< \brief (TRNG_DATA) MASK Register */ - -/** \brief TRNG hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - RoReg8 Reserved1[0x3]; - __IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */ - RoReg8 Reserved2[0x3]; - __IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ - __IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ - __IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved3[0x15]; - __I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */ -} Trng; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_TRNG_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_usb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_usb.h deleted file mode 100644 index e3a91afabc5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_usb.h +++ /dev/null @@ -1,1773 +0,0 @@ -/** - * \file - * - * \brief Component description for USB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_USB_COMPONENT_ -#define _SAML21_USB_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR USB */ -/* ========================================================================== */ -/** \addtogroup SAML21_USB Universal Serial Bus */ -/*@{*/ - -#define USB_U2222 -#define REV_USB 0x110 - -/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t MODE:1; /*!< bit: 7 Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */ -#define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */ - -#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */ -#define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos) -#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */ -#define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos) -#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */ -#define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos) -#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */ -#define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */ -#define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */ -#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */ - -/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */ -#define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */ - -#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */ -#define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos) -#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */ -#define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos) -#define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */ - -/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DETACH:1; /*!< bit: 0 Detach */ - uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ - uint16_t NREPLY:1; /*!< bit: 4 No Reply */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ - uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ - uint16_t GNAK:1; /*!< bit: 9 Global NAK */ - uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */ -#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */ - -#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */ -#define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos) -#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */ -#define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */ -#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))) -#define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */ -#define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */ -#define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */ -#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */ -#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */ -#define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos) -#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */ -#define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos) -#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */ -#define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos) -#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */ -#define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos) -#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */ -#define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos) -#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */ -#define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */ -#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))) -#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ -#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */ -#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */ -#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */ -#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */ - -/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ - uint16_t AUTORESUME:1; /*!< bit: 4 Auto Resume Enable */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ - uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ - uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ - uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */ -#define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */ - -#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */ -#define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos) -#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */ -#define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))) -#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */ -#define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */ -#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_AUTORESUME_Pos 4 /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */ -#define USB_HOST_CTRLB_AUTORESUME (0x1ul << USB_HOST_CTRLB_AUTORESUME_Pos) -#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */ -#define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos) -#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */ -#define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos) -#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */ -#define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos) -#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */ -#define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos) -#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */ -#define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos) -#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */ -#define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos) -#define USB_HOST_CTRLB_MASK 0x0F7Eul /**< \brief (USB_HOST_CTRLB) MASK Register */ - -/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ - uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_DADD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */ -#define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */ - -#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */ -#define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos) -#define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))) -#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */ -#define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos) -#define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */ - -/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_HSOFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */ -#define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */ - -#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */ -#define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos) -#define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))) -#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */ -#define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos) -#define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */ - -/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */ -#define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */ - -#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */ -#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))) -#define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */ -#define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */ -#define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */ -#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */ -#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))) -#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */ -#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */ -#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */ -#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */ - -/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */ -#define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */ - -#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */ -#define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos) -#define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))) -#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */ -#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos) -#define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))) -#define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */ - -/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_FSMSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */ -#define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */ - -#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */ -#define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))) -#define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ -#define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ -#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */ -#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */ -#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ -#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ -#define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */ -#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */ - -/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :1; /*!< bit: 14 Reserved */ - uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_FNUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */ -#define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */ - -#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */ -#define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos) -#define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))) -#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */ -#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos) -#define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))) -#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */ -#define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos) -#define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */ - -/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_FNUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */ -#define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */ - -#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */ -#define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos) -#define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))) -#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */ -#define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos) -#define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))) -#define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */ - -/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_FLENHIGH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */ -#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */ - -#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */ -#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos) -#define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))) -#define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */ - -/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */ -#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */ - -#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */ -#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos) -#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */ -#define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos) -#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */ -#define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos) -#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */ -#define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos) -#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */ -#define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos) -#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */ -#define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos) -#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */ -#define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos) -#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */ -#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos) -#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */ -#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos) -#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */ -#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos) -#define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */ - -/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ - uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */ -#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */ - -#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */ -#define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos) -#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */ -#define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos) -#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */ -#define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos) -#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */ -#define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos) -#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */ -#define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos) -#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */ -#define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos) -#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */ -#define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos) -#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */ -#define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos) -#define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */ - -/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */ -#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */ - -#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */ -#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos) -#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */ -#define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos) -#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */ -#define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos) -#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */ -#define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos) -#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */ -#define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos) -#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */ -#define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos) -#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */ -#define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos) -#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */ -#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos) -#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */ -#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos) -#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */ -#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos) -#define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */ - -/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ - uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */ -#define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */ - -#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */ -#define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos) -#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */ -#define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos) -#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */ -#define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos) -#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */ -#define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos) -#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */ -#define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos) -#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */ -#define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos) -#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */ -#define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos) -#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */ -#define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos) -#define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */ - -/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ - uint16_t EORST:1; /*!< bit: 3 End of Reset */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */ -#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */ - -#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */ -#define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos) -#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */ -#define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos) -#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */ -#define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos) -#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */ -#define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos) -#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */ -#define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos) -#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */ -#define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos) -#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */ -#define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos) -#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */ -#define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos) -#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */ -#define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos) -#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */ -#define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos) -#define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */ - -/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ - uint16_t RST:1; /*!< bit: 3 Bus Reset */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - uint16_t DNRSM:1; /*!< bit: 5 Downstream */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */ -#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */ - -#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */ -#define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos) -#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */ -#define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos) -#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */ -#define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos) -#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */ -#define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos) -#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */ -#define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos) -#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */ -#define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos) -#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */ -#define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos) -#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */ -#define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos) -#define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */ - -/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTSMRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */ -#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */ - -#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))) -#define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */ - -/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_PINTSMRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */ -#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */ - -#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos) -#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos) -#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos) -#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos) -#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos) -#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos) -#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos) -#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos) -#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */ -#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos) -#define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))) -#define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */ - -/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DESCADD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */ -#define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */ - -#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */ -#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos) -#define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))) -#define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */ - -/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_PADCAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */ -#define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */ - -#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */ -#define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos) -#define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))) -#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */ -#define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos) -#define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))) -#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */ -#define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos) -#define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))) -#define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */ - -/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ - uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */ -#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */ - -#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */ -#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos) -#define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))) -#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */ -#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos) -#define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))) -#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */ -#define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos) -#define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */ - -/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ - uint8_t BK:1; /*!< bit: 2 Pipe Bank */ - uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */ -#define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */ - -#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */ -#define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos) -#define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))) -#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */ -#define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos) -#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */ -#define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos) -#define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))) -#define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */ - -/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_BINTERVAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */ -#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */ - -#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */ -#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos) -#define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))) -#define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUSCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */ -#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */ - -#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */ -#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */ -#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */ -#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))) -#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */ -#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */ -#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */ - -/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUSCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */ -#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */ - -#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */ -#define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos) -#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */ -#define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos) -#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */ -#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos) -#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */ -#define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos) -#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */ -#define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos) -#define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUSSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */ -#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */ - -#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */ -#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */ -#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */ -#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))) -#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */ -#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */ -#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */ - -/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUSSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */ -#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */ - -#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */ -#define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos) -#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */ -#define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos) -#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */ -#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos) -#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */ -#define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos) -#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */ -#define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos) -#define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */ -#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */ - -#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */ -#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */ -#define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */ -#define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))) -#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */ -#define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */ -#define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */ - -/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */ -#define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */ - -#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */ -#define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos) -#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */ -#define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos) -#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */ -#define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos) -#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */ -#define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos) -#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */ -#define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos) -#define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */ - -/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */ -#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */ - -#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */ -#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */ -#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */ -#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))) -#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */ -#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */ -#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */ -#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))) -#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */ -#define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos) -#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */ -#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos) -#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */ -#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos) -#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */ -#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos) -#define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))) -#define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */ - -/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */ -#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */ - -#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos) -#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos) -#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos) -#define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))) -#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos) -#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */ -#define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos) -#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */ -#define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos) -#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */ -#define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos) -#define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */ - -/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ -#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - -#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))) -#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))) -#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos) -#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos) -#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos) -#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos) -#define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))) -#define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */ - -/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ - uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */ -#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */ - -#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */ -#define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos) -#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */ -#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos) -#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */ -#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos) -#define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))) -#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */ -#define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos) -#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */ -#define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos) -#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */ -#define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos) -#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */ -#define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos) -#define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */ - -/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */ -#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - -#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))) -#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))) -#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos) -#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos) -#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos) -#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos) -#define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))) -#define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */ - -/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */ -#define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */ - -#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos) -#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos) -#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos) -#define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))) -#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */ -#define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos) -#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */ -#define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos) -#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */ -#define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos) -#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */ -#define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos) -#define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */ - -/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DEVICE_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - -#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */ -#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos) -#define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))) -#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */ - -/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_HOST_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - -#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */ -#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos) -#define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))) -#define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */ - -/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DEVICE_PCKSIZE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - -#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */ -#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) -#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))) -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */ -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))) -#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */ -#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos) -#define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))) -#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */ -#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) -#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */ - -/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_HOST_PCKSIZE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */ - -#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */ -#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) -#define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))) -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */ -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))) -#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */ -#define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos) -#define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))) -#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */ -#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) -#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */ - -/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_EXTREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */ - -#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */ -#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos) -#define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))) -#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */ -#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos) -#define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))) -#define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */ - -/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_EXTREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */ - -#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */ -#define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos) -#define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))) -#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */ -#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos) -#define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))) -#define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */ - -/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_STATUS_BK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - -#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */ -#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos) -#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */ -#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) -#define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */ - -/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_BK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */ - -#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */ -#define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos) -#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */ -#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos) -#define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */ - -/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ - uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_CTRL_PIPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */ -#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */ - -#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */ -#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos) -#define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))) -#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */ -#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos) -#define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))) -#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */ -#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos) -#define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))) -#define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */ - -/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ - uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ - uint16_t PIDER:1; /*!< bit: 2 PID Error */ - uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ - uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ - uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_PIPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */ - -#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */ -#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos) -#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */ -#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos) -#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */ -#define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos) -#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */ -#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos) -#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */ -#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos) -#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */ -#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos) -#define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))) -#define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */ - -/** \brief UsbDeviceDescBank SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ - __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - RoReg8 Reserved1[0x5]; -} UsbDeviceDescBank; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbHostDescBank SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ - __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ - __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ - RoReg8 Reserved1[0x1]; - __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ - __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ -} UsbHostDescBank; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbDeviceEndpoint hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ - RoReg8 Reserved1[0x3]; - __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ - __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ - __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ - __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ - __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - RoReg8 Reserved2[0x16]; -} UsbDeviceEndpoint; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbHostPipe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ - RoReg8 Reserved1[0x2]; - __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ - __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ - __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ - __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ - __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ - __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ - __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ - RoReg8 Reserved2[0x16]; -} UsbHostPipe; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_DEVICE APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Device */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - RoReg8 Reserved2[0x5]; - __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ - __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ - RoReg8 Reserved3[0x1]; - __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ - RoReg8 Reserved5[0x2]; - __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ -} UsbDevice; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_HOST hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Host */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - RoReg8 Reserved2[0x5]; - __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ - __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ - RoReg8 Reserved3[0x1]; - __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ - __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ - RoReg8 Reserved5[0x1]; - __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ -} UsbHost; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_DEVICE Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Device */ - UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ -} UsbDeviceDescriptor; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_HOST Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Host */ - UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ -} UsbHostDescriptor; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#ifdef __GNUC__ -#define SECTION_USB_DESCRIPTOR __attribute__ ((section(".hsram"))) -#elif defined(__ICCARM__) -#define SECTION_USB_DESCRIPTOR @".hsram" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ - UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ -} Usb; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_USB_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_wdt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_wdt.h deleted file mode 100644 index 2d76e72c47c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_wdt.h +++ /dev/null @@ -1,317 +0,0 @@ -/** - * \file - * - * \brief Component description for WDT - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_WDT_COMPONENT_ -#define _SAML21_WDT_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR WDT */ -/* ========================================================================== */ -/** \addtogroup SAML21_WDT Watchdog Timer */ -/*@{*/ - -#define WDT_U2251 -#define REV_WDT 0x100 - -/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */ -#define WDT_CTRLA_RESETVALUE 0x00ul /**< \brief (WDT_CTRLA reset_value) Control */ - -#define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */ -#define WDT_CTRLA_ENABLE (0x1ul << WDT_CTRLA_ENABLE_Pos) -#define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */ -#define WDT_CTRLA_WEN (0x1ul << WDT_CTRLA_WEN_Pos) -#define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */ -#define WDT_CTRLA_ALWAYSON (0x1ul << WDT_CTRLA_ALWAYSON_Pos) -#define WDT_CTRLA_MASK 0x86ul /**< \brief (WDT_CTRLA) MASK Register */ - -/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ - uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */ -#define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */ - -#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */ -#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))) -#define WDT_CONFIG_PER_CYC8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ -#define WDT_CONFIG_PER_CYC16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ -#define WDT_CONFIG_PER_CYC32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ -#define WDT_CONFIG_PER_CYC64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ -#define WDT_CONFIG_PER_CYC128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ -#define WDT_CONFIG_PER_CYC256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ -#define WDT_CONFIG_PER_CYC512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ -#define WDT_CONFIG_PER_CYC1024_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ -#define WDT_CONFIG_PER_CYC2048_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ -#define WDT_CONFIG_PER_CYC4096_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ -#define WDT_CONFIG_PER_CYC8192_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ -#define WDT_CONFIG_PER_CYC16384_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ -#define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */ -#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))) -#define WDT_CONFIG_WINDOW_CYC8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC1024_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC2048_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC4096_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC8192_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC16384_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ -#define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */ - -/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_EWCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */ -#define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */ - -#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */ -#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))) -#define WDT_EWCTRL_EWOFFSET_CYC8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC1024_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC2048_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC4096_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC8192_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC16384_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */ - -/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */ -#define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */ - -#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */ -#define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos) -#define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */ - -/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */ -#define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */ - -#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */ -#define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos) -#define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */ - -/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */ -#define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */ -#define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos) -#define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */ - -/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t WEN:1; /*!< bit: 2 Window Enable Busy */ - uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Busy */ - uint32_t CLEAR:1; /*!< bit: 4 Clear Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} WDT_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */ -#define WDT_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */ - -#define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Busy */ -#define WDT_SYNCBUSY_ENABLE (0x1ul << WDT_SYNCBUSY_ENABLE_Pos) -#define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Busy */ -#define WDT_SYNCBUSY_WEN (0x1ul << WDT_SYNCBUSY_WEN_Pos) -#define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Busy */ -#define WDT_SYNCBUSY_ALWAYSON (0x1ul << WDT_SYNCBUSY_ALWAYSON_Pos) -#define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Busy */ -#define WDT_SYNCBUSY_CLEAR (0x1ul << WDT_SYNCBUSY_CLEAR_Pos) -#define WDT_SYNCBUSY_MASK 0x0000001Eul /**< \brief (WDT_SYNCBUSY) MASK Register */ - -/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CLEAR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */ -#define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */ - -#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */ -#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos) -#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))) -#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */ -#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) -#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */ - -/** \brief WDT hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */ - __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ - __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ - RoReg8 Reserved1[0x1]; - __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved2[0x1]; - __I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */ - __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */ -} Wdt; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_WDT_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ac.h deleted file mode 100644 index c931887c671..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ac.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * \file - * - * \brief Instance description for AC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_AC_INSTANCE_ -#define _SAML21_AC_INSTANCE_ - -/* ========== Register definition for AC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AC_CTRLA (0x43001000U) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (0x43001001U) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (0x43001002U) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (0x43001004U) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (0x43001005U) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (0x43001006U) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (0x43001007U) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (0x43001008U) /**< \brief (AC) Status B */ -#define REG_AC_DBGCTRL (0x43001009U) /**< \brief (AC) Debug Control */ -#define REG_AC_WINCTRL (0x4300100AU) /**< \brief (AC) Window Control */ -#define REG_AC_SCALER0 (0x4300100CU) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (0x4300100DU) /**< \brief (AC) Scaler 1 */ -#define REG_AC_COMPCTRL0 (0x43001010U) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (0x43001014U) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SYNCBUSY (0x43001020U) /**< \brief (AC) Synchronization Busy */ -#else -#define REG_AC_CTRLA (*(RwReg8 *)0x43001000U) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (*(WoReg8 *)0x43001001U) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (*(RwReg16*)0x43001002U) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (*(RwReg8 *)0x43001004U) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (*(RwReg8 *)0x43001005U) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (*(RwReg8 *)0x43001006U) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (*(RoReg8 *)0x43001007U) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (*(RoReg8 *)0x43001008U) /**< \brief (AC) Status B */ -#define REG_AC_DBGCTRL (*(RwReg8 *)0x43001009U) /**< \brief (AC) Debug Control */ -#define REG_AC_WINCTRL (*(RwReg8 *)0x4300100AU) /**< \brief (AC) Window Control */ -#define REG_AC_SCALER0 (*(RwReg8 *)0x4300100CU) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (*(RwReg8 *)0x4300100DU) /**< \brief (AC) Scaler 1 */ -#define REG_AC_COMPCTRL0 (*(RwReg *)0x43001010U) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (*(RwReg *)0x43001014U) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SYNCBUSY (*(RoReg *)0x43001020U) /**< \brief (AC) Synchronization Busy */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AC peripheral ========== */ -#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG -#define AC_GCLK_ID 31 // Index of Generic Clock -#define AC_NUM_CMP 2 // Number of comparators -#define AC_PAIRS 1 // Number of pairs of comparators - -#endif /* _SAML21_AC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_adc.h deleted file mode 100644 index 2073853b655..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_adc.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * \file - * - * \brief Instance description for ADC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_ADC_INSTANCE_ -#define _SAML21_ADC_INSTANCE_ - -/* ========== Register definition for ADC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_ADC_CTRLA (0x43000C00U) /**< \brief (ADC) Control A */ -#define REG_ADC_CTRLB (0x43000C01U) /**< \brief (ADC) Control B */ -#define REG_ADC_REFCTRL (0x43000C02U) /**< \brief (ADC) Reference Control */ -#define REG_ADC_EVCTRL (0x43000C03U) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (0x43000C04U) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (0x43000C05U) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (0x43000C06U) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_SEQSTATUS (0x43000C07U) /**< \brief (ADC) Sequence Status */ -#define REG_ADC_INPUTCTRL (0x43000C08U) /**< \brief (ADC) Input Control */ -#define REG_ADC_CTRLC (0x43000C0AU) /**< \brief (ADC) Control C */ -#define REG_ADC_AVGCTRL (0x43000C0CU) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (0x43000C0DU) /**< \brief (ADC) Sample Time Control */ -#define REG_ADC_WINLT (0x43000C0EU) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (0x43000C10U) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (0x43000C12U) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (0x43000C14U) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_SWTRIG (0x43000C18U) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_DBGCTRL (0x43000C1CU) /**< \brief (ADC) Debug Control */ -#define REG_ADC_SYNCBUSY (0x43000C20U) /**< \brief (ADC) Synchronization Busy */ -#define REG_ADC_RESULT (0x43000C24U) /**< \brief (ADC) Result */ -#define REG_ADC_SEQCTRL (0x43000C28U) /**< \brief (ADC) Sequence Control */ -#define REG_ADC_CALIB (0x43000C2CU) /**< \brief (ADC) Calibration */ -#else -#define REG_ADC_CTRLA (*(RwReg8 *)0x43000C00U) /**< \brief (ADC) Control A */ -#define REG_ADC_CTRLB (*(RwReg8 *)0x43000C01U) /**< \brief (ADC) Control B */ -#define REG_ADC_REFCTRL (*(RwReg8 *)0x43000C02U) /**< \brief (ADC) Reference Control */ -#define REG_ADC_EVCTRL (*(RwReg8 *)0x43000C03U) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (*(RwReg8 *)0x43000C04U) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (*(RwReg8 *)0x43000C05U) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (*(RwReg8 *)0x43000C06U) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_SEQSTATUS (*(RoReg8 *)0x43000C07U) /**< \brief (ADC) Sequence Status */ -#define REG_ADC_INPUTCTRL (*(RwReg16*)0x43000C08U) /**< \brief (ADC) Input Control */ -#define REG_ADC_CTRLC (*(RwReg16*)0x43000C0AU) /**< \brief (ADC) Control C */ -#define REG_ADC_AVGCTRL (*(RwReg8 *)0x43000C0CU) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x43000C0DU) /**< \brief (ADC) Sample Time Control */ -#define REG_ADC_WINLT (*(RwReg16*)0x43000C0EU) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (*(RwReg16*)0x43000C10U) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (*(RwReg16*)0x43000C12U) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (*(RwReg16*)0x43000C14U) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_SWTRIG (*(RwReg8 *)0x43000C18U) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_DBGCTRL (*(RwReg8 *)0x43000C1CU) /**< \brief (ADC) Debug Control */ -#define REG_ADC_SYNCBUSY (*(RoReg16*)0x43000C20U) /**< \brief (ADC) Synchronization Busy */ -#define REG_ADC_RESULT (*(RoReg16*)0x43000C24U) /**< \brief (ADC) Result */ -#define REG_ADC_SEQCTRL (*(RwReg *)0x43000C28U) /**< \brief (ADC) Sequence Control */ -#define REG_ADC_CALIB (*(RwReg16*)0x43000C2CU) /**< \brief (ADC) Calibration */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for ADC peripheral ========== */ -#define ADC_DMAC_ID_RESRDY 37 // index of DMA RESRDY trigger -#define ADC_EXTCHANNEL_MSB 19 // Number of external channels -#define ADC_GCLK_ID 30 // index of Generic Clock -#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield -#define ADC_RESULT_MSB 15 // Size of Result - -#endif /* _SAML21_ADC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_aes.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_aes.h deleted file mode 100644 index 9189f19068e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_aes.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * \file - * - * \brief Instance description for AES - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_AES_INSTANCE_ -#define _SAML21_AES_INSTANCE_ - -/* ========== Register definition for AES peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AES_CTRLA (0x42003400U) /**< \brief (AES) Control A */ -#define REG_AES_CTRLB (0x42003404U) /**< \brief (AES) Control B */ -#define REG_AES_INTENCLR (0x42003405U) /**< \brief (AES) Interrupt Enable Clear */ -#define REG_AES_INTENSET (0x42003406U) /**< \brief (AES) Interrupt Enable Set */ -#define REG_AES_INTFLAG (0x42003407U) /**< \brief (AES) Interrupt Flag Status */ -#define REG_AES_DATABUFPTR (0x42003408U) /**< \brief (AES) Data buffer pointer */ -#define REG_AES_DBGCTRL (0x42003409U) /**< \brief (AES) Debug control */ -#define REG_AES_KEYWORD0 (0x4200340CU) /**< \brief (AES) Keyword 0 */ -#define REG_AES_KEYWORD1 (0x42003410U) /**< \brief (AES) Keyword 1 */ -#define REG_AES_KEYWORD2 (0x42003414U) /**< \brief (AES) Keyword 2 */ -#define REG_AES_KEYWORD3 (0x42003418U) /**< \brief (AES) Keyword 3 */ -#define REG_AES_KEYWORD4 (0x4200341CU) /**< \brief (AES) Keyword 4 */ -#define REG_AES_KEYWORD5 (0x42003420U) /**< \brief (AES) Keyword 5 */ -#define REG_AES_KEYWORD6 (0x42003424U) /**< \brief (AES) Keyword 6 */ -#define REG_AES_KEYWORD7 (0x42003428U) /**< \brief (AES) Keyword 7 */ -#define REG_AES_INDATA (0x42003438U) /**< \brief (AES) Indata */ -#define REG_AES_INTVECTV0 (0x4200343CU) /**< \brief (AES) Initialisation Vector 0 */ -#define REG_AES_INTVECTV1 (0x42003440U) /**< \brief (AES) Initialisation Vector 1 */ -#define REG_AES_INTVECTV2 (0x42003444U) /**< \brief (AES) Initialisation Vector 2 */ -#define REG_AES_INTVECTV3 (0x42003448U) /**< \brief (AES) Initialisation Vector 3 */ -#define REG_AES_HASHKEY0 (0x4200345CU) /**< \brief (AES) Hash key 0 */ -#define REG_AES_HASHKEY1 (0x42003460U) /**< \brief (AES) Hash key 1 */ -#define REG_AES_HASHKEY2 (0x42003464U) /**< \brief (AES) Hash key 2 */ -#define REG_AES_HASHKEY3 (0x42003468U) /**< \brief (AES) Hash key 3 */ -#define REG_AES_GHASH0 (0x4200346CU) /**< \brief (AES) Galois Hash 0 */ -#define REG_AES_GHASH1 (0x42003470U) /**< \brief (AES) Galois Hash 1 */ -#define REG_AES_GHASH2 (0x42003474U) /**< \brief (AES) Galois Hash 2 */ -#define REG_AES_GHASH3 (0x42003478U) /**< \brief (AES) Galois Hash 3 */ -#define REG_AES_CIPLEN (0x42003480U) /**< \brief (AES) Cipher Length */ -#define REG_AES_RANDSEED (0x42003484U) /**< \brief (AES) Random Seed */ -#else -#define REG_AES_CTRLA (*(RwReg *)0x42003400U) /**< \brief (AES) Control A */ -#define REG_AES_CTRLB (*(RwReg8 *)0x42003404U) /**< \brief (AES) Control B */ -#define REG_AES_INTENCLR (*(RwReg8 *)0x42003405U) /**< \brief (AES) Interrupt Enable Clear */ -#define REG_AES_INTENSET (*(RwReg8 *)0x42003406U) /**< \brief (AES) Interrupt Enable Set */ -#define REG_AES_INTFLAG (*(RwReg8 *)0x42003407U) /**< \brief (AES) Interrupt Flag Status */ -#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42003408U) /**< \brief (AES) Data buffer pointer */ -#define REG_AES_DBGCTRL (*(WoReg8 *)0x42003409U) /**< \brief (AES) Debug control */ -#define REG_AES_KEYWORD0 (*(WoReg *)0x4200340CU) /**< \brief (AES) Keyword 0 */ -#define REG_AES_KEYWORD1 (*(WoReg *)0x42003410U) /**< \brief (AES) Keyword 1 */ -#define REG_AES_KEYWORD2 (*(WoReg *)0x42003414U) /**< \brief (AES) Keyword 2 */ -#define REG_AES_KEYWORD3 (*(WoReg *)0x42003418U) /**< \brief (AES) Keyword 3 */ -#define REG_AES_KEYWORD4 (*(WoReg *)0x4200341CU) /**< \brief (AES) Keyword 4 */ -#define REG_AES_KEYWORD5 (*(WoReg *)0x42003420U) /**< \brief (AES) Keyword 5 */ -#define REG_AES_KEYWORD6 (*(WoReg *)0x42003424U) /**< \brief (AES) Keyword 6 */ -#define REG_AES_KEYWORD7 (*(WoReg *)0x42003428U) /**< \brief (AES) Keyword 7 */ -#define REG_AES_INDATA (*(RwReg *)0x42003438U) /**< \brief (AES) Indata */ -#define REG_AES_INTVECTV0 (*(WoReg *)0x4200343CU) /**< \brief (AES) Initialisation Vector 0 */ -#define REG_AES_INTVECTV1 (*(WoReg *)0x42003440U) /**< \brief (AES) Initialisation Vector 1 */ -#define REG_AES_INTVECTV2 (*(WoReg *)0x42003444U) /**< \brief (AES) Initialisation Vector 2 */ -#define REG_AES_INTVECTV3 (*(WoReg *)0x42003448U) /**< \brief (AES) Initialisation Vector 3 */ -#define REG_AES_HASHKEY0 (*(RwReg *)0x4200345CU) /**< \brief (AES) Hash key 0 */ -#define REG_AES_HASHKEY1 (*(RwReg *)0x42003460U) /**< \brief (AES) Hash key 1 */ -#define REG_AES_HASHKEY2 (*(RwReg *)0x42003464U) /**< \brief (AES) Hash key 2 */ -#define REG_AES_HASHKEY3 (*(RwReg *)0x42003468U) /**< \brief (AES) Hash key 3 */ -#define REG_AES_GHASH0 (*(RwReg *)0x4200346CU) /**< \brief (AES) Galois Hash 0 */ -#define REG_AES_GHASH1 (*(RwReg *)0x42003470U) /**< \brief (AES) Galois Hash 1 */ -#define REG_AES_GHASH2 (*(RwReg *)0x42003474U) /**< \brief (AES) Galois Hash 2 */ -#define REG_AES_GHASH3 (*(RwReg *)0x42003478U) /**< \brief (AES) Galois Hash 3 */ -#define REG_AES_CIPLEN (*(RwReg *)0x42003480U) /**< \brief (AES) Cipher Length */ -#define REG_AES_RANDSEED (*(RwReg *)0x42003484U) /**< \brief (AES) Random Seed */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AES peripheral ========== */ -#define AES_DMAC_ID_RD 45 // DMA DATA Read trigger -#define AES_DMAC_ID_WR 44 // DMA DATA Write trigger - -#endif /* _SAML21_AES_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ccl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ccl.h deleted file mode 100644 index b543ccbe998..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ccl.h +++ /dev/null @@ -1,75 +0,0 @@ -/** - * \file - * - * \brief Instance description for CCL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_CCL_INSTANCE_ -#define _SAML21_CCL_INSTANCE_ - -/* ========== Register definition for CCL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CCL_CTRL (0x43001C00U) /**< \brief (CCL) Control */ -#define REG_CCL_SEQCTRL0 (0x43001C04U) /**< \brief (CCL) SEQ Control x 0 */ -#define REG_CCL_SEQCTRL1 (0x43001C05U) /**< \brief (CCL) SEQ Control x 1 */ -#define REG_CCL_LUTCTRL0 (0x43001C08U) /**< \brief (CCL) LUT Control x 0 */ -#define REG_CCL_LUTCTRL1 (0x43001C0CU) /**< \brief (CCL) LUT Control x 1 */ -#define REG_CCL_LUTCTRL2 (0x43001C10U) /**< \brief (CCL) LUT Control x 2 */ -#define REG_CCL_LUTCTRL3 (0x43001C14U) /**< \brief (CCL) LUT Control x 3 */ -#else -#define REG_CCL_CTRL (*(RwReg8 *)0x43001C00U) /**< \brief (CCL) Control */ -#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x43001C04U) /**< \brief (CCL) SEQ Control x 0 */ -#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x43001C05U) /**< \brief (CCL) SEQ Control x 1 */ -#define REG_CCL_LUTCTRL0 (*(RwReg *)0x43001C08U) /**< \brief (CCL) LUT Control x 0 */ -#define REG_CCL_LUTCTRL1 (*(RwReg *)0x43001C0CU) /**< \brief (CCL) LUT Control x 1 */ -#define REG_CCL_LUTCTRL2 (*(RwReg *)0x43001C10U) /**< \brief (CCL) LUT Control x 2 */ -#define REG_CCL_LUTCTRL3 (*(RwReg *)0x43001C14U) /**< \brief (CCL) LUT Control x 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for CCL peripheral ========== */ -#define CCL_GCLK_ID 34 // GCLK index for CCL -#define CCL_IO_NUM 12 // Numer of input pins -#define CCL_LUT_NUM 4 // Number of LUT in a CCL -#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL - -#endif /* _SAML21_CCL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dac.h deleted file mode 100644 index c46b407e538..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dac.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * \brief Instance description for DAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_DAC_INSTANCE_ -#define _SAML21_DAC_INSTANCE_ - -/* ========== Register definition for DAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DAC_CTRLA (0x42003000U) /**< \brief (DAC) Control A */ -#define REG_DAC_CTRLB (0x42003001U) /**< \brief (DAC) Control B */ -#define REG_DAC_EVCTRL (0x42003002U) /**< \brief (DAC) Event Control */ -#define REG_DAC_INTENCLR (0x42003004U) /**< \brief (DAC) Interrupt Enable Clear */ -#define REG_DAC_INTENSET (0x42003005U) /**< \brief (DAC) Interrupt Enable Set */ -#define REG_DAC_INTFLAG (0x42003006U) /**< \brief (DAC) Interrupt Flag Status and Clear */ -#define REG_DAC_STATUS (0x42003007U) /**< \brief (DAC) Status */ -#define REG_DAC_SYNCBUSY (0x42003008U) /**< \brief (DAC) Synchronization Busy */ -#define REG_DAC_DACCTRL0 (0x4200300CU) /**< \brief (DAC) DAC 0 Control */ -#define REG_DAC_DACCTRL1 (0x4200300EU) /**< \brief (DAC) DAC 1 Control */ -#define REG_DAC_DATA0 (0x42003010U) /**< \brief (DAC) DAC 0 Data */ -#define REG_DAC_DATA1 (0x42003012U) /**< \brief (DAC) DAC 1 Data */ -#define REG_DAC_DATABUF0 (0x42003014U) /**< \brief (DAC) DAC 0 Data Buffer */ -#define REG_DAC_DATABUF1 (0x42003016U) /**< \brief (DAC) DAC 1 Data Buffer */ -#define REG_DAC_DBGCTRL (0x42003018U) /**< \brief (DAC) Debug Control */ -#else -#define REG_DAC_CTRLA (*(RwReg8 *)0x42003000U) /**< \brief (DAC) Control A */ -#define REG_DAC_CTRLB (*(RwReg8 *)0x42003001U) /**< \brief (DAC) Control B */ -#define REG_DAC_EVCTRL (*(RwReg8 *)0x42003002U) /**< \brief (DAC) Event Control */ -#define REG_DAC_INTENCLR (*(RwReg8 *)0x42003004U) /**< \brief (DAC) Interrupt Enable Clear */ -#define REG_DAC_INTENSET (*(RwReg8 *)0x42003005U) /**< \brief (DAC) Interrupt Enable Set */ -#define REG_DAC_INTFLAG (*(RwReg8 *)0x42003006U) /**< \brief (DAC) Interrupt Flag Status and Clear */ -#define REG_DAC_STATUS (*(RoReg8 *)0x42003007U) /**< \brief (DAC) Status */ -#define REG_DAC_SYNCBUSY (*(RoReg *)0x42003008U) /**< \brief (DAC) Synchronization Busy */ -#define REG_DAC_DACCTRL0 (*(RwReg16*)0x4200300CU) /**< \brief (DAC) DAC 0 Control */ -#define REG_DAC_DACCTRL1 (*(RwReg16*)0x4200300EU) /**< \brief (DAC) DAC 1 Control */ -#define REG_DAC_DATA0 (*(WoReg16*)0x42003010U) /**< \brief (DAC) DAC 0 Data */ -#define REG_DAC_DATA1 (*(WoReg16*)0x42003012U) /**< \brief (DAC) DAC 1 Data */ -#define REG_DAC_DATABUF0 (*(WoReg16*)0x42003014U) /**< \brief (DAC) DAC 0 Data Buffer */ -#define REG_DAC_DATABUF1 (*(WoReg16*)0x42003016U) /**< \brief (DAC) DAC 1 Data Buffer */ -#define REG_DAC_DBGCTRL (*(RwReg8 *)0x42003018U) /**< \brief (DAC) Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DAC peripheral ========== */ -#define DAC_DAC_NUM 2 // Number of DACs -#define DAC_DATA_SIZE 12 // Number of bits in data -#define DAC_DMAC_ID_EMPTY_0 38 -#define DAC_DMAC_ID_EMPTY_1 39 -#define DAC_DMAC_ID_EMPTY_LSB 38 -#define DAC_DMAC_ID_EMPTY_MSB 39 -#define DAC_DMAC_ID_EMPTY_SIZE 2 -#define DAC_GCLK_ID 32 // Index of Generic Clock - -#endif /* _SAML21_DAC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dmac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dmac.h deleted file mode 100644 index 6eb9c47b777..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dmac.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * \file - * - * \brief Instance description for DMAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_DMAC_INSTANCE_ -#define _SAML21_DMAC_INSTANCE_ - -/* ========== Register definition for DMAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DMAC_CTRL (0x44000400U) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (0x44000402U) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (0x44000404U) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (0x44000408U) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (0x4400040CU) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (0x4400040DU) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_SWTRIGCTRL (0x44000410U) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (0x44000414U) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (0x44000420U) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (0x44000424U) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (0x44000428U) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (0x4400042CU) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (0x44000430U) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (0x44000434U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (0x44000438U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (0x4400043FU) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (0x44000440U) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (0x44000444U) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (0x4400044CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (0x4400044DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (0x4400044EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (0x4400044FU) /**< \brief (DMAC) Channel Status */ -#else -#define REG_DMAC_CTRL (*(RwReg16*)0x44000400U) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (*(RwReg16*)0x44000402U) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (*(RwReg *)0x44000404U) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x44000408U) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4400040CU) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4400040DU) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x44000410U) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (*(RwReg *)0x44000414U) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (*(RwReg16*)0x44000420U) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (*(RoReg *)0x44000424U) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (*(RoReg *)0x44000428U) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (*(RoReg *)0x4400042CU) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (*(RoReg *)0x44000430U) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (*(RwReg *)0x44000434U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (*(RwReg *)0x44000438U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (*(RwReg8 *)0x4400043FU) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x44000440U) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (*(RwReg *)0x44000444U) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4400044CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4400044DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4400044EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4400044FU) /**< \brief (DMAC) Channel Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DMAC peripheral ========== */ -#define DMAC_CH_BITS 4 // Number of bits to select channel -#define DMAC_CH_NUM 16 // Number of channels -#define DMAC_CLK_AHB_ID 11 // AHB clock index -#define DMAC_EVIN_NUM 8 // Number of input events -#define DMAC_EVOUT_NUM 8 // Number of output events -#define DMAC_LVL_BITS 2 // Number of bit to select level priority -#define DMAC_LVL_NUM 4 // Enable priority level number -#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value -#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value -#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value -#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source -#define DMAC_TRIG_NUM 46 // Number of peripheral triggers - -#endif /* _SAML21_DMAC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dsu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dsu.h deleted file mode 100644 index b2261ccb3e1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dsu.h +++ /dev/null @@ -1,112 +0,0 @@ -/** - * \file - * - * \brief Instance description for DSU - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_DSU_INSTANCE_ -#define _SAML21_DSU_INSTANCE_ - -/* ========== Register definition for DSU peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */ -#define REG_DSU_DCFG0 (0x410020F0U) /**< \brief (DSU) Device Configuration 0 */ -#define REG_DSU_DCFG1 (0x410020F4U) /**< \brief (DSU) Device Configuration 1 */ -#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ -#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ -#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ -#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID5 (0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */ -#define REG_DSU_PID6 (0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */ -#define REG_DSU_PID7 (0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */ -#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ -#else -#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */ -#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0U) /**< \brief (DSU) Device Configuration 0 */ -#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4U) /**< \brief (DSU) Device Configuration 1 */ -#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ -#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ -#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ -#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID5 (*(RoReg *)0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */ -#define REG_DSU_PID6 (*(RoReg *)0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */ -#define REG_DSU_PID7 (*(RoReg *)0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */ -#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DSU peripheral ========== */ -#define DSU_CLK_AHB_ID 5 - -#endif /* _SAML21_DSU_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_eic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_eic.h deleted file mode 100644 index 7ccbfeaff84..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_eic.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * \brief Instance description for EIC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_EIC_INSTANCE_ -#define _SAML21_EIC_INSTANCE_ - -/* ========== Register definition for EIC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EIC_CTRLA (0x40002400U) /**< \brief (EIC) Control */ -#define REG_EIC_NMICTRL (0x40002401U) /**< \brief (EIC) NMI Control */ -#define REG_EIC_NMIFLAG (0x40002402U) /**< \brief (EIC) NMI Interrupt Flag */ -#define REG_EIC_SYNCBUSY (0x40002404U) /**< \brief (EIC) Syncbusy register */ -#define REG_EIC_EVCTRL (0x40002408U) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (0x4000240CU) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (0x40002410U) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (0x40002414U) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_EIC_ASYNCH (0x40002418U) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ -#define REG_EIC_CONFIG0 (0x4000241CU) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (0x40002420U) /**< \brief (EIC) Configuration 1 */ -#else -#define REG_EIC_CTRLA (*(RwReg8 *)0x40002400U) /**< \brief (EIC) Control */ -#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002401U) /**< \brief (EIC) NMI Control */ -#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002402U) /**< \brief (EIC) NMI Interrupt Flag */ -#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002404U) /**< \brief (EIC) Syncbusy register */ -#define REG_EIC_EVCTRL (*(RwReg *)0x40002408U) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (*(RwReg *)0x4000240CU) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (*(RwReg *)0x40002410U) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (*(RwReg *)0x40002414U) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_EIC_ASYNCH (*(RwReg *)0x40002418U) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ -#define REG_EIC_CONFIG0 (*(RwReg *)0x4000241CU) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (*(RwReg *)0x40002420U) /**< \brief (EIC) Configuration 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EIC peripheral ========== */ -#define EIC_EXTINT_NUM 16 -#define EIC_GCLK_ID 3 -#define EIC_NUMBER_OF_CONFIG_REGS 2 -#define EIC_NUMBER_OF_INTERRUPTS 16 - -#endif /* _SAML21_EIC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_evsys.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_evsys.h deleted file mode 100644 index fc69aefa977..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_evsys.h +++ /dev/null @@ -1,338 +0,0 @@ -/** - * \file - * - * \brief Instance description for EVSYS - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_EVSYS_INSTANCE_ -#define _SAML21_EVSYS_INSTANCE_ - -/* ========== Register definition for EVSYS peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EVSYS_CTRLA (0x43000000U) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHSTATUS (0x4300000CU) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (0x43000010U) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (0x43000014U) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (0x43000018U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#define REG_EVSYS_SWEVT (0x4300001CU) /**< \brief (EVSYS) Software Event */ -#define REG_EVSYS_CHANNEL0 (0x43000020U) /**< \brief (EVSYS) Channel 0 */ -#define REG_EVSYS_CHANNEL1 (0x43000024U) /**< \brief (EVSYS) Channel 1 */ -#define REG_EVSYS_CHANNEL2 (0x43000028U) /**< \brief (EVSYS) Channel 2 */ -#define REG_EVSYS_CHANNEL3 (0x4300002CU) /**< \brief (EVSYS) Channel 3 */ -#define REG_EVSYS_CHANNEL4 (0x43000030U) /**< \brief (EVSYS) Channel 4 */ -#define REG_EVSYS_CHANNEL5 (0x43000034U) /**< \brief (EVSYS) Channel 5 */ -#define REG_EVSYS_CHANNEL6 (0x43000038U) /**< \brief (EVSYS) Channel 6 */ -#define REG_EVSYS_CHANNEL7 (0x4300003CU) /**< \brief (EVSYS) Channel 7 */ -#define REG_EVSYS_CHANNEL8 (0x43000040U) /**< \brief (EVSYS) Channel 8 */ -#define REG_EVSYS_CHANNEL9 (0x43000044U) /**< \brief (EVSYS) Channel 9 */ -#define REG_EVSYS_CHANNEL10 (0x43000048U) /**< \brief (EVSYS) Channel 10 */ -#define REG_EVSYS_CHANNEL11 (0x4300004CU) /**< \brief (EVSYS) Channel 11 */ -#define REG_EVSYS_USER0 (0x43000080U) /**< \brief (EVSYS) User Multiplexer 0 */ -#define REG_EVSYS_USER1 (0x43000084U) /**< \brief (EVSYS) User Multiplexer 1 */ -#define REG_EVSYS_USER2 (0x43000088U) /**< \brief (EVSYS) User Multiplexer 2 */ -#define REG_EVSYS_USER3 (0x4300008CU) /**< \brief (EVSYS) User Multiplexer 3 */ -#define REG_EVSYS_USER4 (0x43000090U) /**< \brief (EVSYS) User Multiplexer 4 */ -#define REG_EVSYS_USER5 (0x43000094U) /**< \brief (EVSYS) User Multiplexer 5 */ -#define REG_EVSYS_USER6 (0x43000098U) /**< \brief (EVSYS) User Multiplexer 6 */ -#define REG_EVSYS_USER7 (0x4300009CU) /**< \brief (EVSYS) User Multiplexer 7 */ -#define REG_EVSYS_USER8 (0x430000A0U) /**< \brief (EVSYS) User Multiplexer 8 */ -#define REG_EVSYS_USER9 (0x430000A4U) /**< \brief (EVSYS) User Multiplexer 9 */ -#define REG_EVSYS_USER10 (0x430000A8U) /**< \brief (EVSYS) User Multiplexer 10 */ -#define REG_EVSYS_USER11 (0x430000ACU) /**< \brief (EVSYS) User Multiplexer 11 */ -#define REG_EVSYS_USER12 (0x430000B0U) /**< \brief (EVSYS) User Multiplexer 12 */ -#define REG_EVSYS_USER13 (0x430000B4U) /**< \brief (EVSYS) User Multiplexer 13 */ -#define REG_EVSYS_USER14 (0x430000B8U) /**< \brief (EVSYS) User Multiplexer 14 */ -#define REG_EVSYS_USER15 (0x430000BCU) /**< \brief (EVSYS) User Multiplexer 15 */ -#define REG_EVSYS_USER16 (0x430000C0U) /**< \brief (EVSYS) User Multiplexer 16 */ -#define REG_EVSYS_USER17 (0x430000C4U) /**< \brief (EVSYS) User Multiplexer 17 */ -#define REG_EVSYS_USER18 (0x430000C8U) /**< \brief (EVSYS) User Multiplexer 18 */ -#define REG_EVSYS_USER19 (0x430000CCU) /**< \brief (EVSYS) User Multiplexer 19 */ -#define REG_EVSYS_USER20 (0x430000D0U) /**< \brief (EVSYS) User Multiplexer 20 */ -#define REG_EVSYS_USER21 (0x430000D4U) /**< \brief (EVSYS) User Multiplexer 21 */ -#define REG_EVSYS_USER22 (0x430000D8U) /**< \brief (EVSYS) User Multiplexer 22 */ -#define REG_EVSYS_USER23 (0x430000DCU) /**< \brief (EVSYS) User Multiplexer 23 */ -#define REG_EVSYS_USER24 (0x430000E0U) /**< \brief (EVSYS) User Multiplexer 24 */ -#define REG_EVSYS_USER25 (0x430000E4U) /**< \brief (EVSYS) User Multiplexer 25 */ -#define REG_EVSYS_USER26 (0x430000E8U) /**< \brief (EVSYS) User Multiplexer 26 */ -#define REG_EVSYS_USER27 (0x430000ECU) /**< \brief (EVSYS) User Multiplexer 27 */ -#define REG_EVSYS_USER28 (0x430000F0U) /**< \brief (EVSYS) User Multiplexer 28 */ -#define REG_EVSYS_USER29 (0x430000F4U) /**< \brief (EVSYS) User Multiplexer 29 */ -#define REG_EVSYS_USER30 (0x430000F8U) /**< \brief (EVSYS) User Multiplexer 30 */ -#define REG_EVSYS_USER31 (0x430000FCU) /**< \brief (EVSYS) User Multiplexer 31 */ -#define REG_EVSYS_USER32 (0x43000100U) /**< \brief (EVSYS) User Multiplexer 32 */ -#define REG_EVSYS_USER33 (0x43000104U) /**< \brief (EVSYS) User Multiplexer 33 */ -#define REG_EVSYS_USER34 (0x43000108U) /**< \brief (EVSYS) User Multiplexer 34 */ -#define REG_EVSYS_USER35 (0x4300010CU) /**< \brief (EVSYS) User Multiplexer 35 */ -#define REG_EVSYS_USER36 (0x43000110U) /**< \brief (EVSYS) User Multiplexer 36 */ -#define REG_EVSYS_USER37 (0x43000114U) /**< \brief (EVSYS) User Multiplexer 37 */ -#define REG_EVSYS_USER38 (0x43000118U) /**< \brief (EVSYS) User Multiplexer 38 */ -#define REG_EVSYS_USER39 (0x4300011CU) /**< \brief (EVSYS) User Multiplexer 39 */ -#define REG_EVSYS_USER40 (0x43000120U) /**< \brief (EVSYS) User Multiplexer 40 */ -#define REG_EVSYS_USER41 (0x43000124U) /**< \brief (EVSYS) User Multiplexer 41 */ -#define REG_EVSYS_USER42 (0x43000128U) /**< \brief (EVSYS) User Multiplexer 42 */ -#define REG_EVSYS_USER43 (0x4300012CU) /**< \brief (EVSYS) User Multiplexer 43 */ -#define REG_EVSYS_USER44 (0x43000130U) /**< \brief (EVSYS) User Multiplexer 44 */ -#else -#define REG_EVSYS_CTRLA (*(RwReg8 *)0x43000000U) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4300000CU) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (*(RwReg *)0x43000010U) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (*(RwReg *)0x43000014U) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (*(RwReg *)0x43000018U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#define REG_EVSYS_SWEVT (*(WoReg *)0x4300001CU) /**< \brief (EVSYS) Software Event */ -#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x43000020U) /**< \brief (EVSYS) Channel 0 */ -#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x43000024U) /**< \brief (EVSYS) Channel 1 */ -#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x43000028U) /**< \brief (EVSYS) Channel 2 */ -#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4300002CU) /**< \brief (EVSYS) Channel 3 */ -#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x43000030U) /**< \brief (EVSYS) Channel 4 */ -#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x43000034U) /**< \brief (EVSYS) Channel 5 */ -#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x43000038U) /**< \brief (EVSYS) Channel 6 */ -#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4300003CU) /**< \brief (EVSYS) Channel 7 */ -#define REG_EVSYS_CHANNEL8 (*(RwReg *)0x43000040U) /**< \brief (EVSYS) Channel 8 */ -#define REG_EVSYS_CHANNEL9 (*(RwReg *)0x43000044U) /**< \brief (EVSYS) Channel 9 */ -#define REG_EVSYS_CHANNEL10 (*(RwReg *)0x43000048U) /**< \brief (EVSYS) Channel 10 */ -#define REG_EVSYS_CHANNEL11 (*(RwReg *)0x4300004CU) /**< \brief (EVSYS) Channel 11 */ -#define REG_EVSYS_USER0 (*(RwReg *)0x43000080U) /**< \brief (EVSYS) User Multiplexer 0 */ -#define REG_EVSYS_USER1 (*(RwReg *)0x43000084U) /**< \brief (EVSYS) User Multiplexer 1 */ -#define REG_EVSYS_USER2 (*(RwReg *)0x43000088U) /**< \brief (EVSYS) User Multiplexer 2 */ -#define REG_EVSYS_USER3 (*(RwReg *)0x4300008CU) /**< \brief (EVSYS) User Multiplexer 3 */ -#define REG_EVSYS_USER4 (*(RwReg *)0x43000090U) /**< \brief (EVSYS) User Multiplexer 4 */ -#define REG_EVSYS_USER5 (*(RwReg *)0x43000094U) /**< \brief (EVSYS) User Multiplexer 5 */ -#define REG_EVSYS_USER6 (*(RwReg *)0x43000098U) /**< \brief (EVSYS) User Multiplexer 6 */ -#define REG_EVSYS_USER7 (*(RwReg *)0x4300009CU) /**< \brief (EVSYS) User Multiplexer 7 */ -#define REG_EVSYS_USER8 (*(RwReg *)0x430000A0U) /**< \brief (EVSYS) User Multiplexer 8 */ -#define REG_EVSYS_USER9 (*(RwReg *)0x430000A4U) /**< \brief (EVSYS) User Multiplexer 9 */ -#define REG_EVSYS_USER10 (*(RwReg *)0x430000A8U) /**< \brief (EVSYS) User Multiplexer 10 */ -#define REG_EVSYS_USER11 (*(RwReg *)0x430000ACU) /**< \brief (EVSYS) User Multiplexer 11 */ -#define REG_EVSYS_USER12 (*(RwReg *)0x430000B0U) /**< \brief (EVSYS) User Multiplexer 12 */ -#define REG_EVSYS_USER13 (*(RwReg *)0x430000B4U) /**< \brief (EVSYS) User Multiplexer 13 */ -#define REG_EVSYS_USER14 (*(RwReg *)0x430000B8U) /**< \brief (EVSYS) User Multiplexer 14 */ -#define REG_EVSYS_USER15 (*(RwReg *)0x430000BCU) /**< \brief (EVSYS) User Multiplexer 15 */ -#define REG_EVSYS_USER16 (*(RwReg *)0x430000C0U) /**< \brief (EVSYS) User Multiplexer 16 */ -#define REG_EVSYS_USER17 (*(RwReg *)0x430000C4U) /**< \brief (EVSYS) User Multiplexer 17 */ -#define REG_EVSYS_USER18 (*(RwReg *)0x430000C8U) /**< \brief (EVSYS) User Multiplexer 18 */ -#define REG_EVSYS_USER19 (*(RwReg *)0x430000CCU) /**< \brief (EVSYS) User Multiplexer 19 */ -#define REG_EVSYS_USER20 (*(RwReg *)0x430000D0U) /**< \brief (EVSYS) User Multiplexer 20 */ -#define REG_EVSYS_USER21 (*(RwReg *)0x430000D4U) /**< \brief (EVSYS) User Multiplexer 21 */ -#define REG_EVSYS_USER22 (*(RwReg *)0x430000D8U) /**< \brief (EVSYS) User Multiplexer 22 */ -#define REG_EVSYS_USER23 (*(RwReg *)0x430000DCU) /**< \brief (EVSYS) User Multiplexer 23 */ -#define REG_EVSYS_USER24 (*(RwReg *)0x430000E0U) /**< \brief (EVSYS) User Multiplexer 24 */ -#define REG_EVSYS_USER25 (*(RwReg *)0x430000E4U) /**< \brief (EVSYS) User Multiplexer 25 */ -#define REG_EVSYS_USER26 (*(RwReg *)0x430000E8U) /**< \brief (EVSYS) User Multiplexer 26 */ -#define REG_EVSYS_USER27 (*(RwReg *)0x430000ECU) /**< \brief (EVSYS) User Multiplexer 27 */ -#define REG_EVSYS_USER28 (*(RwReg *)0x430000F0U) /**< \brief (EVSYS) User Multiplexer 28 */ -#define REG_EVSYS_USER29 (*(RwReg *)0x430000F4U) /**< \brief (EVSYS) User Multiplexer 29 */ -#define REG_EVSYS_USER30 (*(RwReg *)0x430000F8U) /**< \brief (EVSYS) User Multiplexer 30 */ -#define REG_EVSYS_USER31 (*(RwReg *)0x430000FCU) /**< \brief (EVSYS) User Multiplexer 31 */ -#define REG_EVSYS_USER32 (*(RwReg *)0x43000100U) /**< \brief (EVSYS) User Multiplexer 32 */ -#define REG_EVSYS_USER33 (*(RwReg *)0x43000104U) /**< \brief (EVSYS) User Multiplexer 33 */ -#define REG_EVSYS_USER34 (*(RwReg *)0x43000108U) /**< \brief (EVSYS) User Multiplexer 34 */ -#define REG_EVSYS_USER35 (*(RwReg *)0x4300010CU) /**< \brief (EVSYS) User Multiplexer 35 */ -#define REG_EVSYS_USER36 (*(RwReg *)0x43000110U) /**< \brief (EVSYS) User Multiplexer 36 */ -#define REG_EVSYS_USER37 (*(RwReg *)0x43000114U) /**< \brief (EVSYS) User Multiplexer 37 */ -#define REG_EVSYS_USER38 (*(RwReg *)0x43000118U) /**< \brief (EVSYS) User Multiplexer 38 */ -#define REG_EVSYS_USER39 (*(RwReg *)0x4300011CU) /**< \brief (EVSYS) User Multiplexer 39 */ -#define REG_EVSYS_USER40 (*(RwReg *)0x43000120U) /**< \brief (EVSYS) User Multiplexer 40 */ -#define REG_EVSYS_USER41 (*(RwReg *)0x43000124U) /**< \brief (EVSYS) User Multiplexer 41 */ -#define REG_EVSYS_USER42 (*(RwReg *)0x43000128U) /**< \brief (EVSYS) User Multiplexer 42 */ -#define REG_EVSYS_USER43 (*(RwReg *)0x4300012CU) /**< \brief (EVSYS) User Multiplexer 43 */ -#define REG_EVSYS_USER44 (*(RwReg *)0x43000130U) /**< \brief (EVSYS) User Multiplexer 44 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EVSYS peripheral ========== */ -#define EVSYS_CHANNELS 12 // Number of Channels -#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel -#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1 -#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators -#define EVSYS_GCLK_ID_0 5 -#define EVSYS_GCLK_ID_1 6 -#define EVSYS_GCLK_ID_2 7 -#define EVSYS_GCLK_ID_3 8 -#define EVSYS_GCLK_ID_4 9 -#define EVSYS_GCLK_ID_5 10 -#define EVSYS_GCLK_ID_6 11 -#define EVSYS_GCLK_ID_7 12 -#define EVSYS_GCLK_ID_8 13 -#define EVSYS_GCLK_ID_9 14 -#define EVSYS_GCLK_ID_10 15 -#define EVSYS_GCLK_ID_11 16 -#define EVSYS_GCLK_ID_LSB 5 -#define EVSYS_GCLK_ID_MSB 16 -#define EVSYS_GCLK_ID_SIZE 12 -#define EVSYS_GENERATORS 83 // Total Number of Event Generators -#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator -#define EVSYS_USERS 45 // Total Number of Event Users -#define EVSYS_USERS_BITS 6 // Number of bits to select Event User - -// GENERATORS -#define EVSYS_ID_GEN_RTC_CMP_0 1 -#define EVSYS_ID_GEN_RTC_CMP_1 2 -#define EVSYS_ID_GEN_RTC_OVF 3 -#define EVSYS_ID_GEN_RTC_PER_0 4 -#define EVSYS_ID_GEN_RTC_PER_1 5 -#define EVSYS_ID_GEN_RTC_PER_2 6 -#define EVSYS_ID_GEN_RTC_PER_3 7 -#define EVSYS_ID_GEN_RTC_PER_4 8 -#define EVSYS_ID_GEN_RTC_PER_5 9 -#define EVSYS_ID_GEN_RTC_PER_6 10 -#define EVSYS_ID_GEN_RTC_PER_7 11 -#define EVSYS_ID_GEN_EIC_EXTINT_0 12 -#define EVSYS_ID_GEN_EIC_EXTINT_1 13 -#define EVSYS_ID_GEN_EIC_EXTINT_2 14 -#define EVSYS_ID_GEN_EIC_EXTINT_3 15 -#define EVSYS_ID_GEN_EIC_EXTINT_4 16 -#define EVSYS_ID_GEN_EIC_EXTINT_5 17 -#define EVSYS_ID_GEN_EIC_EXTINT_6 18 -#define EVSYS_ID_GEN_EIC_EXTINT_7 19 -#define EVSYS_ID_GEN_EIC_EXTINT_8 20 -#define EVSYS_ID_GEN_EIC_EXTINT_9 21 -#define EVSYS_ID_GEN_EIC_EXTINT_10 22 -#define EVSYS_ID_GEN_EIC_EXTINT_11 23 -#define EVSYS_ID_GEN_EIC_EXTINT_12 24 -#define EVSYS_ID_GEN_EIC_EXTINT_13 25 -#define EVSYS_ID_GEN_EIC_EXTINT_14 26 -#define EVSYS_ID_GEN_EIC_EXTINT_15 27 -#define EVSYS_ID_GEN_DMAC_CH_0 28 -#define EVSYS_ID_GEN_DMAC_CH_1 29 -#define EVSYS_ID_GEN_DMAC_CH_2 30 -#define EVSYS_ID_GEN_DMAC_CH_3 31 -#define EVSYS_ID_GEN_DMAC_CH_4 32 -#define EVSYS_ID_GEN_DMAC_CH_5 33 -#define EVSYS_ID_GEN_DMAC_CH_6 34 -#define EVSYS_ID_GEN_DMAC_CH_7 35 -#define EVSYS_ID_GEN_TCC0_OVF 36 -#define EVSYS_ID_GEN_TCC0_TRG 37 -#define EVSYS_ID_GEN_TCC0_CNT 38 -#define EVSYS_ID_GEN_TCC0_MCX_0 39 -#define EVSYS_ID_GEN_TCC0_MCX_1 40 -#define EVSYS_ID_GEN_TCC0_MCX_2 41 -#define EVSYS_ID_GEN_TCC0_MCX_3 42 -#define EVSYS_ID_GEN_TCC1_OVF 43 -#define EVSYS_ID_GEN_TCC1_TRG 44 -#define EVSYS_ID_GEN_TCC1_CNT 45 -#define EVSYS_ID_GEN_TCC1_MCX_0 46 -#define EVSYS_ID_GEN_TCC1_MCX_1 47 -#define EVSYS_ID_GEN_TCC2_OVF 48 -#define EVSYS_ID_GEN_TCC2_TRG 49 -#define EVSYS_ID_GEN_TCC2_CNT 50 -#define EVSYS_ID_GEN_TCC2_MCX_0 51 -#define EVSYS_ID_GEN_TCC2_MCX_1 52 -#define EVSYS_ID_GEN_TC0_OVF 53 -#define EVSYS_ID_GEN_TC0_MCX_0 54 -#define EVSYS_ID_GEN_TC0_MCX_1 55 -#define EVSYS_ID_GEN_TC1_OVF 56 -#define EVSYS_ID_GEN_TC1_MCX_0 57 -#define EVSYS_ID_GEN_TC1_MCX_1 58 -#define EVSYS_ID_GEN_TC2_OVF 59 -#define EVSYS_ID_GEN_TC2_MCX_0 60 -#define EVSYS_ID_GEN_TC2_MCX_1 61 -#define EVSYS_ID_GEN_TC3_OVF 62 -#define EVSYS_ID_GEN_TC3_MCX_0 63 -#define EVSYS_ID_GEN_TC3_MCX_1 64 -#define EVSYS_ID_GEN_TC4_OVF 65 -#define EVSYS_ID_GEN_TC4_MCX_0 66 -#define EVSYS_ID_GEN_TC4_MCX_1 67 -#define EVSYS_ID_GEN_ADC_RESRDY 68 -#define EVSYS_ID_GEN_ADC_WINMON 69 -#define EVSYS_ID_GEN_AC_COMP_0 70 -#define EVSYS_ID_GEN_AC_COMP_1 71 -#define EVSYS_ID_GEN_AC_WIN_0 72 -#define EVSYS_ID_GEN_DAC_EMPTY_0 73 -#define EVSYS_ID_GEN_DAC_EMPTY_1 74 -#define EVSYS_ID_GEN_PTC_EOC 75 -#define EVSYS_ID_GEN_PTC_WCOMP 76 -#define EVSYS_ID_GEN_TRNG_READY 77 -#define EVSYS_ID_GEN_CCL_LUTOUT_0 78 -#define EVSYS_ID_GEN_CCL_LUTOUT_1 79 -#define EVSYS_ID_GEN_CCL_LUTOUT_2 80 -#define EVSYS_ID_GEN_CCL_LUTOUT_3 81 -#define EVSYS_ID_GEN_PAC_ACCERR 82 -#define EVSYS_ID_GEN_TAL_BRK 83 - -// USERS -#define EVSYS_ID_USER_PORT_EV_0 0 -#define EVSYS_ID_USER_PORT_EV_1 1 -#define EVSYS_ID_USER_PORT_EV_2 2 -#define EVSYS_ID_USER_PORT_EV_3 3 -#define EVSYS_ID_USER_DMAC_CH_0 4 -#define EVSYS_ID_USER_DMAC_CH_1 5 -#define EVSYS_ID_USER_DMAC_CH_2 6 -#define EVSYS_ID_USER_DMAC_CH_3 7 -#define EVSYS_ID_USER_DMAC_CH_4 8 -#define EVSYS_ID_USER_DMAC_CH_5 9 -#define EVSYS_ID_USER_DMAC_CH_6 10 -#define EVSYS_ID_USER_DMAC_CH_7 11 -#define EVSYS_ID_USER_TCC0_EV_0 12 -#define EVSYS_ID_USER_TCC0_EV_1 13 -#define EVSYS_ID_USER_TCC0_MC_0 14 -#define EVSYS_ID_USER_TCC0_MC_1 15 -#define EVSYS_ID_USER_TCC0_MC_2 16 -#define EVSYS_ID_USER_TCC0_MC_3 17 -#define EVSYS_ID_USER_TCC1_EV_0 18 -#define EVSYS_ID_USER_TCC1_EV_1 19 -#define EVSYS_ID_USER_TCC1_MC_0 20 -#define EVSYS_ID_USER_TCC1_MC_1 21 -#define EVSYS_ID_USER_TCC2_EV_0 22 -#define EVSYS_ID_USER_TCC2_EV_1 23 -#define EVSYS_ID_USER_TCC2_MC_0 24 -#define EVSYS_ID_USER_TCC2_MC_1 25 -#define EVSYS_ID_USER_TC0_EVU 26 -#define EVSYS_ID_USER_TC1_EVU 27 -#define EVSYS_ID_USER_TC2_EVU 28 -#define EVSYS_ID_USER_TC3_EVU 29 -#define EVSYS_ID_USER_TC4_EVU 30 -#define EVSYS_ID_USER_ADC_START 31 -#define EVSYS_ID_USER_ADC_SYNC 32 -#define EVSYS_ID_USER_AC_SOC_0 33 -#define EVSYS_ID_USER_AC_SOC_1 34 -#define EVSYS_ID_USER_DAC_START_0 35 -#define EVSYS_ID_USER_DAC_START_1 36 -#define EVSYS_ID_USER_PTC_STCONV 37 -#define EVSYS_ID_USER_CCL_LUTIN_0 38 -#define EVSYS_ID_USER_CCL_LUTIN_1 39 -#define EVSYS_ID_USER_CCL_LUTIN_2 40 -#define EVSYS_ID_USER_CCL_LUTIN_3 41 -#define EVSYS_ID_USER_TAL_BRK 42 -#define EVSYS_ID_USER_MTB_START 43 -#define EVSYS_ID_USER_MTB_STOP 44 - -#endif /* _SAML21_EVSYS_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_gclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_gclk.h deleted file mode 100644 index 329c69cd52d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_gclk.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - * \file - * - * \brief Instance description for GCLK - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_GCLK_INSTANCE_ -#define _SAML21_GCLK_INSTANCE_ - -/* ========== Register definition for GCLK peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_GCLK_CTRLA (0x40001800U) /**< \brief (GCLK) Control */ -#define REG_GCLK_SYNCBUSY (0x40001804U) /**< \brief (GCLK) Synchronization Busy */ -#define REG_GCLK_GENCTRL0 (0x40001820U) /**< \brief (GCLK) Generic Clock Generator Control 0 */ -#define REG_GCLK_GENCTRL1 (0x40001824U) /**< \brief (GCLK) Generic Clock Generator Control 1 */ -#define REG_GCLK_GENCTRL2 (0x40001828U) /**< \brief (GCLK) Generic Clock Generator Control 2 */ -#define REG_GCLK_GENCTRL3 (0x4000182CU) /**< \brief (GCLK) Generic Clock Generator Control 3 */ -#define REG_GCLK_GENCTRL4 (0x40001830U) /**< \brief (GCLK) Generic Clock Generator Control 4 */ -#define REG_GCLK_GENCTRL5 (0x40001834U) /**< \brief (GCLK) Generic Clock Generator Control 5 */ -#define REG_GCLK_GENCTRL6 (0x40001838U) /**< \brief (GCLK) Generic Clock Generator Control 6 */ -#define REG_GCLK_GENCTRL7 (0x4000183CU) /**< \brief (GCLK) Generic Clock Generator Control 7 */ -#define REG_GCLK_GENCTRL8 (0x40001840U) /**< \brief (GCLK) Generic Clock Generator Control 8 */ -#define REG_GCLK_PCHCTRL0 (0x40001880U) /**< \brief (GCLK) Peripheral Clock Control 0 */ -#define REG_GCLK_PCHCTRL1 (0x40001884U) /**< \brief (GCLK) Peripheral Clock Control 1 */ -#define REG_GCLK_PCHCTRL2 (0x40001888U) /**< \brief (GCLK) Peripheral Clock Control 2 */ -#define REG_GCLK_PCHCTRL3 (0x4000188CU) /**< \brief (GCLK) Peripheral Clock Control 3 */ -#define REG_GCLK_PCHCTRL4 (0x40001890U) /**< \brief (GCLK) Peripheral Clock Control 4 */ -#define REG_GCLK_PCHCTRL5 (0x40001894U) /**< \brief (GCLK) Peripheral Clock Control 5 */ -#define REG_GCLK_PCHCTRL6 (0x40001898U) /**< \brief (GCLK) Peripheral Clock Control 6 */ -#define REG_GCLK_PCHCTRL7 (0x4000189CU) /**< \brief (GCLK) Peripheral Clock Control 7 */ -#define REG_GCLK_PCHCTRL8 (0x400018A0U) /**< \brief (GCLK) Peripheral Clock Control 8 */ -#define REG_GCLK_PCHCTRL9 (0x400018A4U) /**< \brief (GCLK) Peripheral Clock Control 9 */ -#define REG_GCLK_PCHCTRL10 (0x400018A8U) /**< \brief (GCLK) Peripheral Clock Control 10 */ -#define REG_GCLK_PCHCTRL11 (0x400018ACU) /**< \brief (GCLK) Peripheral Clock Control 11 */ -#define REG_GCLK_PCHCTRL12 (0x400018B0U) /**< \brief (GCLK) Peripheral Clock Control 12 */ -#define REG_GCLK_PCHCTRL13 (0x400018B4U) /**< \brief (GCLK) Peripheral Clock Control 13 */ -#define REG_GCLK_PCHCTRL14 (0x400018B8U) /**< \brief (GCLK) Peripheral Clock Control 14 */ -#define REG_GCLK_PCHCTRL15 (0x400018BCU) /**< \brief (GCLK) Peripheral Clock Control 15 */ -#define REG_GCLK_PCHCTRL16 (0x400018C0U) /**< \brief (GCLK) Peripheral Clock Control 16 */ -#define REG_GCLK_PCHCTRL17 (0x400018C4U) /**< \brief (GCLK) Peripheral Clock Control 17 */ -#define REG_GCLK_PCHCTRL18 (0x400018C8U) /**< \brief (GCLK) Peripheral Clock Control 18 */ -#define REG_GCLK_PCHCTRL19 (0x400018CCU) /**< \brief (GCLK) Peripheral Clock Control 19 */ -#define REG_GCLK_PCHCTRL20 (0x400018D0U) /**< \brief (GCLK) Peripheral Clock Control 20 */ -#define REG_GCLK_PCHCTRL21 (0x400018D4U) /**< \brief (GCLK) Peripheral Clock Control 21 */ -#define REG_GCLK_PCHCTRL22 (0x400018D8U) /**< \brief (GCLK) Peripheral Clock Control 22 */ -#define REG_GCLK_PCHCTRL23 (0x400018DCU) /**< \brief (GCLK) Peripheral Clock Control 23 */ -#define REG_GCLK_PCHCTRL24 (0x400018E0U) /**< \brief (GCLK) Peripheral Clock Control 24 */ -#define REG_GCLK_PCHCTRL25 (0x400018E4U) /**< \brief (GCLK) Peripheral Clock Control 25 */ -#define REG_GCLK_PCHCTRL26 (0x400018E8U) /**< \brief (GCLK) Peripheral Clock Control 26 */ -#define REG_GCLK_PCHCTRL27 (0x400018ECU) /**< \brief (GCLK) Peripheral Clock Control 27 */ -#define REG_GCLK_PCHCTRL28 (0x400018F0U) /**< \brief (GCLK) Peripheral Clock Control 28 */ -#define REG_GCLK_PCHCTRL29 (0x400018F4U) /**< \brief (GCLK) Peripheral Clock Control 29 */ -#define REG_GCLK_PCHCTRL30 (0x400018F8U) /**< \brief (GCLK) Peripheral Clock Control 30 */ -#define REG_GCLK_PCHCTRL31 (0x400018FCU) /**< \brief (GCLK) Peripheral Clock Control 31 */ -#define REG_GCLK_PCHCTRL32 (0x40001900U) /**< \brief (GCLK) Peripheral Clock Control 32 */ -#define REG_GCLK_PCHCTRL33 (0x40001904U) /**< \brief (GCLK) Peripheral Clock Control 33 */ -#define REG_GCLK_PCHCTRL34 (0x40001908U) /**< \brief (GCLK) Peripheral Clock Control 34 */ -#define REG_GCLK_PCHCTRL35 (0x4000190CU) /**< \brief (GCLK) Peripheral Clock Control 35 */ -#else -#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001800U) /**< \brief (GCLK) Control */ -#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001804U) /**< \brief (GCLK) Synchronization Busy */ -#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001820U) /**< \brief (GCLK) Generic Clock Generator Control 0 */ -#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001824U) /**< \brief (GCLK) Generic Clock Generator Control 1 */ -#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001828U) /**< \brief (GCLK) Generic Clock Generator Control 2 */ -#define REG_GCLK_GENCTRL3 (*(RwReg *)0x4000182CU) /**< \brief (GCLK) Generic Clock Generator Control 3 */ -#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001830U) /**< \brief (GCLK) Generic Clock Generator Control 4 */ -#define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001834U) /**< \brief (GCLK) Generic Clock Generator Control 5 */ -#define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001838U) /**< \brief (GCLK) Generic Clock Generator Control 6 */ -#define REG_GCLK_GENCTRL7 (*(RwReg *)0x4000183CU) /**< \brief (GCLK) Generic Clock Generator Control 7 */ -#define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001840U) /**< \brief (GCLK) Generic Clock Generator Control 8 */ -#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001880U) /**< \brief (GCLK) Peripheral Clock Control 0 */ -#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001884U) /**< \brief (GCLK) Peripheral Clock Control 1 */ -#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001888U) /**< \brief (GCLK) Peripheral Clock Control 2 */ -#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x4000188CU) /**< \brief (GCLK) Peripheral Clock Control 3 */ -#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001890U) /**< \brief (GCLK) Peripheral Clock Control 4 */ -#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001894U) /**< \brief (GCLK) Peripheral Clock Control 5 */ -#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001898U) /**< \brief (GCLK) Peripheral Clock Control 6 */ -#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x4000189CU) /**< \brief (GCLK) Peripheral Clock Control 7 */ -#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x400018A0U) /**< \brief (GCLK) Peripheral Clock Control 8 */ -#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x400018A4U) /**< \brief (GCLK) Peripheral Clock Control 9 */ -#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x400018A8U) /**< \brief (GCLK) Peripheral Clock Control 10 */ -#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x400018ACU) /**< \brief (GCLK) Peripheral Clock Control 11 */ -#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x400018B0U) /**< \brief (GCLK) Peripheral Clock Control 12 */ -#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x400018B4U) /**< \brief (GCLK) Peripheral Clock Control 13 */ -#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x400018B8U) /**< \brief (GCLK) Peripheral Clock Control 14 */ -#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x400018BCU) /**< \brief (GCLK) Peripheral Clock Control 15 */ -#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x400018C0U) /**< \brief (GCLK) Peripheral Clock Control 16 */ -#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x400018C4U) /**< \brief (GCLK) Peripheral Clock Control 17 */ -#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x400018C8U) /**< \brief (GCLK) Peripheral Clock Control 18 */ -#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x400018CCU) /**< \brief (GCLK) Peripheral Clock Control 19 */ -#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x400018D0U) /**< \brief (GCLK) Peripheral Clock Control 20 */ -#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x400018D4U) /**< \brief (GCLK) Peripheral Clock Control 21 */ -#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x400018D8U) /**< \brief (GCLK) Peripheral Clock Control 22 */ -#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x400018DCU) /**< \brief (GCLK) Peripheral Clock Control 23 */ -#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x400018E0U) /**< \brief (GCLK) Peripheral Clock Control 24 */ -#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x400018E4U) /**< \brief (GCLK) Peripheral Clock Control 25 */ -#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x400018E8U) /**< \brief (GCLK) Peripheral Clock Control 26 */ -#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x400018ECU) /**< \brief (GCLK) Peripheral Clock Control 27 */ -#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x400018F0U) /**< \brief (GCLK) Peripheral Clock Control 28 */ -#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x400018F4U) /**< \brief (GCLK) Peripheral Clock Control 29 */ -#define REG_GCLK_PCHCTRL30 (*(RwReg *)0x400018F8U) /**< \brief (GCLK) Peripheral Clock Control 30 */ -#define REG_GCLK_PCHCTRL31 (*(RwReg *)0x400018FCU) /**< \brief (GCLK) Peripheral Clock Control 31 */ -#define REG_GCLK_PCHCTRL32 (*(RwReg *)0x40001900U) /**< \brief (GCLK) Peripheral Clock Control 32 */ -#define REG_GCLK_PCHCTRL33 (*(RwReg *)0x40001904U) /**< \brief (GCLK) Peripheral Clock Control 33 */ -#define REG_GCLK_PCHCTRL34 (*(RwReg *)0x40001908U) /**< \brief (GCLK) Peripheral Clock Control 34 */ -#define REG_GCLK_PCHCTRL35 (*(RwReg *)0x4000190CU) /**< \brief (GCLK) Peripheral Clock Control 35 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 -#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators -#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 -#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 -#define GCLK_NUM 36 // Number of Generic Clock Users -#define GCLK_SOURCE_BITS 4 -#define GCLK_SOURCE_DFLL48M 7 -#define GCLK_SOURCE_FDPLL 8 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 -#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC16M 6 -#define GCLK_SOURCE_OSC32K 4 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 5 - -#endif /* _SAML21_GCLK_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mclk.h deleted file mode 100644 index 20fb36f8fe3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mclk.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief Instance description for MCLK - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_MCLK_INSTANCE_ -#define _SAML21_MCLK_INSTANCE_ - -/* ========== Register definition for MCLK peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MCLK_CTRLA (0x40000400U) /**< \brief (MCLK) Control A */ -#define REG_MCLK_INTENCLR (0x40000401U) /**< \brief (MCLK) Interrupt Enable Clear */ -#define REG_MCLK_INTENSET (0x40000402U) /**< \brief (MCLK) Interrupt Enable Set */ -#define REG_MCLK_INTFLAG (0x40000403U) /**< \brief (MCLK) Interrupt Flag Status and Clear */ -#define REG_MCLK_CPUDIV (0x40000404U) /**< \brief (MCLK) CPU Clock Division */ -#define REG_MCLK_LPDIV (0x40000405U) /**< \brief (MCLK) Low-Power Clock Division */ -#define REG_MCLK_BUPDIV (0x40000406U) /**< \brief (MCLK) Backup Clock Division */ -#define REG_MCLK_AHBMASK (0x40000410U) /**< \brief (MCLK) AHB Mask */ -#define REG_MCLK_APBAMASK (0x40000414U) /**< \brief (MCLK) APBA Mask */ -#define REG_MCLK_APBBMASK (0x40000418U) /**< \brief (MCLK) APBB Mask */ -#define REG_MCLK_APBCMASK (0x4000041CU) /**< \brief (MCLK) APBC Mask */ -#define REG_MCLK_APBDMASK (0x40000420U) /**< \brief (MCLK) APBD Mask */ -#define REG_MCLK_APBEMASK (0x40000424U) /**< \brief (MCLK) APBE Mask */ -#else -#define REG_MCLK_CTRLA (*(RwReg8 *)0x40000400U) /**< \brief (MCLK) Control A */ -#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000401U) /**< \brief (MCLK) Interrupt Enable Clear */ -#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000402U) /**< \brief (MCLK) Interrupt Enable Set */ -#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000403U) /**< \brief (MCLK) Interrupt Flag Status and Clear */ -#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000404U) /**< \brief (MCLK) CPU Clock Division */ -#define REG_MCLK_LPDIV (*(RwReg8 *)0x40000405U) /**< \brief (MCLK) Low-Power Clock Division */ -#define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000406U) /**< \brief (MCLK) Backup Clock Division */ -#define REG_MCLK_AHBMASK (*(RwReg *)0x40000410U) /**< \brief (MCLK) AHB Mask */ -#define REG_MCLK_APBAMASK (*(RwReg *)0x40000414U) /**< \brief (MCLK) APBA Mask */ -#define REG_MCLK_APBBMASK (*(RwReg *)0x40000418U) /**< \brief (MCLK) APBB Mask */ -#define REG_MCLK_APBCMASK (*(RwReg *)0x4000041CU) /**< \brief (MCLK) APBC Mask */ -#define REG_MCLK_APBDMASK (*(RwReg *)0x40000420U) /**< \brief (MCLK) APBD Mask */ -#define REG_MCLK_APBEMASK (*(RwReg *)0x40000424U) /**< \brief (MCLK) APBE Mask */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for MCLK peripheral ========== */ -#define MCLK_CTRLA_MCSEL_GCLK 1 -#define MCLK_CTRLA_MCSEL_OSC8M 0 -#define MCLK_MCLK_CLK_APB_NUM 5 -#define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset - -#endif /* _SAML21_MCLK_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mtb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mtb.h deleted file mode 100644 index e9b493f4376..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mtb.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * \file - * - * \brief Instance description for MTB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_MTB_INSTANCE_ -#define _SAML21_MTB_INSTANCE_ - -/* ========== Register definition for MTB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) Peripheral Identification 4 */ -#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) Peripheral Identification 5 */ -#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) Peripheral Identification 6 */ -#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) Peripheral Identification 7 */ -#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) Peripheral Identification 0 */ -#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) Peripheral Identification 1 */ -#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) Peripheral Identification 2 */ -#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) Peripheral Identification 3 */ -#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) Component Identification 0 */ -#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) Component Identification 1 */ -#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) Component Identification 2 */ -#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) Component Identification 3 */ -#else -#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) Peripheral Identification 4 */ -#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) Peripheral Identification 5 */ -#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) Peripheral Identification 6 */ -#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) Peripheral Identification 7 */ -#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) Peripheral Identification 0 */ -#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) Peripheral Identification 1 */ -#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) Peripheral Identification 2 */ -#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) Peripheral Identification 3 */ -#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) Component Identification 0 */ -#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) Component Identification 1 */ -#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) Component Identification 2 */ -#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) Component Identification 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML21_MTB_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_nvmctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_nvmctrl.h deleted file mode 100644 index 568eba5d6ab..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_nvmctrl.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Instance description for NVMCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_NVMCTRL_INSTANCE_ -#define _SAML21_NVMCTRL_INSTANCE_ - -/* ========== Register definition for NVMCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */ -#else -#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for NVMCTRL peripheral ========== */ -#define NVMCTRL_AUX0_ADDRESS 0x00804000 -#define NVMCTRL_AUX1_ADDRESS 0x00806000 -#define NVMCTRL_AUX2_ADDRESS 0x00808000 -#define NVMCTRL_AUX3_ADDRESS 0x0080A000 -#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register -#define NVMCTRL_CLK_AHB_ID_PICACHU 15 // Index of PICACHU AHB Clock -#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 -#define NVMCTRL_GCLK_ID 35 // Index of Generic Clock for test -#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGES 4096 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 -#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 -#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 -#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF -#define NVMCTRL_RWWEE_PAGES 128 -#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area - -#endif /* _SAML21_NVMCTRL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_opamp.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_opamp.h deleted file mode 100644 index 0432eadc5d0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_opamp.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief Instance description for OPAMP - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_OPAMP_INSTANCE_ -#define _SAML21_OPAMP_INSTANCE_ - -/* ========== Register definition for OPAMP peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_OPAMP_CTRLA (0x43001800U) /**< \brief (OPAMP) Control A */ -#define REG_OPAMP_STATUS (0x43001802U) /**< \brief (OPAMP) Status */ -#define REG_OPAMP_OPAMPCTRL0 (0x43001804U) /**< \brief (OPAMP) OPAMP 0 Control */ -#define REG_OPAMP_OPAMPCTRL1 (0x43001808U) /**< \brief (OPAMP) OPAMP 1 Control */ -#define REG_OPAMP_OPAMPCTRL2 (0x4300180CU) /**< \brief (OPAMP) OPAMP 2 Control */ -#else -#define REG_OPAMP_CTRLA (*(RwReg8 *)0x43001800U) /**< \brief (OPAMP) Control A */ -#define REG_OPAMP_STATUS (*(RoReg8 *)0x43001802U) /**< \brief (OPAMP) Status */ -#define REG_OPAMP_OPAMPCTRL0 (*(RwReg *)0x43001804U) /**< \brief (OPAMP) OPAMP 0 Control */ -#define REG_OPAMP_OPAMPCTRL1 (*(RwReg *)0x43001808U) /**< \brief (OPAMP) OPAMP 1 Control */ -#define REG_OPAMP_OPAMPCTRL2 (*(RwReg *)0x4300180CU) /**< \brief (OPAMP) OPAMP 2 Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML21_OPAMP_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_osc32kctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_osc32kctrl.h deleted file mode 100644 index d8887c9da86..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_osc32kctrl.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * \brief Instance description for OSC32KCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_OSC32KCTRL_INSTANCE_ -#define _SAML21_OSC32KCTRL_INSTANCE_ - -/* ========== Register definition for OSC32KCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_OSC32KCTRL_INTENCLR (0x40001000U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ -#define REG_OSC32KCTRL_INTENSET (0x40001004U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ -#define REG_OSC32KCTRL_INTFLAG (0x40001008U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ -#define REG_OSC32KCTRL_STATUS (0x4000100CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */ -#define REG_OSC32KCTRL_RTCCTRL (0x40001010U) /**< \brief (OSC32KCTRL) Clock selection */ -#define REG_OSC32KCTRL_XOSC32K (0x40001014U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_OSC32KCTRL_OSC32K (0x40001018U) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */ -#define REG_OSC32KCTRL_OSCULP32K (0x4000101CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#else -#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001000U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ -#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001004U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ -#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001008U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ -#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000100CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */ -#define REG_OSC32KCTRL_RTCCTRL (*(RwReg *)0x40001010U) /**< \brief (OSC32KCTRL) Clock selection */ -#define REG_OSC32KCTRL_XOSC32K (*(RwReg *)0x40001014U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_OSC32KCTRL_OSC32K (*(RwReg *)0x40001018U) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */ -#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000101CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for OSC32KCTRL peripheral ========== */ -#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 - -#endif /* _SAML21_OSC32KCTRL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_oscctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_oscctrl.h deleted file mode 100644 index 298e0e37198..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_oscctrl.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Instance description for OSCCTRL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_OSCCTRL_INSTANCE_ -#define _SAML21_OSCCTRL_INSTANCE_ - -/* ========== Register definition for OSCCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_OSCCTRL_INTENCLR (0x40000C00U) /**< \brief (OSCCTRL) Interrupt Enable Clear */ -#define REG_OSCCTRL_INTENSET (0x40000C04U) /**< \brief (OSCCTRL) Interrupt Enable Set */ -#define REG_OSCCTRL_INTFLAG (0x40000C08U) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ -#define REG_OSCCTRL_STATUS (0x40000C0CU) /**< \brief (OSCCTRL) Power and Clocks Status */ -#define REG_OSCCTRL_XOSCCTRL (0x40000C10U) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_OSCCTRL_OSC16MCTRL (0x40000C14U) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ -#define REG_OSCCTRL_DFLLCTRL (0x40000C18U) /**< \brief (OSCCTRL) DFLL48M Control */ -#define REG_OSCCTRL_DFLLVAL (0x40000C1CU) /**< \brief (OSCCTRL) DFLL48M Value */ -#define REG_OSCCTRL_DFLLMUL (0x40000C20U) /**< \brief (OSCCTRL) DFLL48M Multiplier */ -#define REG_OSCCTRL_DFLLSYNC (0x40000C24U) /**< \brief (OSCCTRL) DFLL48M Synchronization */ -#define REG_OSCCTRL_DPLLCTRLA (0x40000C28U) /**< \brief (OSCCTRL) DPLL Control */ -#define REG_OSCCTRL_DPLLRATIO (0x40000C2CU) /**< \brief (OSCCTRL) DPLL Ratio Control */ -#define REG_OSCCTRL_DPLLCTRLB (0x40000C30U) /**< \brief (OSCCTRL) Digital Core Configuration */ -#define REG_OSCCTRL_DPLLPRESC (0x40000C34U) /**< \brief (OSCCTRL) DPLL Prescaler */ -#define REG_OSCCTRL_DPLLSYNCBUSY (0x40000C38U) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ -#define REG_OSCCTRL_DPLLSTATUS (0x40000C3CU) /**< \brief (OSCCTRL) DPLL Status */ -#else -#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40000C00U) /**< \brief (OSCCTRL) Interrupt Enable Clear */ -#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40000C04U) /**< \brief (OSCCTRL) Interrupt Enable Set */ -#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40000C08U) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ -#define REG_OSCCTRL_STATUS (*(RoReg *)0x40000C0CU) /**< \brief (OSCCTRL) Power and Clocks Status */ -#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40000C10U) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40000C14U) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ -#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40000C18U) /**< \brief (OSCCTRL) DFLL48M Control */ -#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40000C1CU) /**< \brief (OSCCTRL) DFLL48M Value */ -#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40000C20U) /**< \brief (OSCCTRL) DFLL48M Multiplier */ -#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40000C24U) /**< \brief (OSCCTRL) DFLL48M Synchronization */ -#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40000C28U) /**< \brief (OSCCTRL) DPLL Control */ -#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40000C2CU) /**< \brief (OSCCTRL) DPLL Ratio Control */ -#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40000C30U) /**< \brief (OSCCTRL) Digital Core Configuration */ -#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40000C34U) /**< \brief (OSCCTRL) DPLL Prescaler */ -#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40000C38U) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ -#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40000C3CU) /**< \brief (OSCCTRL) DPLL Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for OSCCTRL peripheral ========== */ -#define OSCCTRL_DFLL48M_COARSE_MSB 5 -#define OSCCTRL_DFLL48M_FINE_MSB 9 -#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 -#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL -#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define OSCCTRL_DFLL48M_VERSION 0x310 -#define OSCCTRL_FDPLL_VERSION 0x200 -#define OSCCTRL_OSC16M_VERSION 0x100 -#define OSCCTRL_XOSC_VERSION 0x120 - -#endif /* _SAML21_OSCCTRL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pac.h deleted file mode 100644 index 8c0ab56d0c5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pac.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_PAC_INSTANCE_ -#define _SAML21_PAC_INSTANCE_ - -/* ========== Register definition for PAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC_WRCTRL (0x44000000U) /**< \brief (PAC) Write control */ -#define REG_PAC_EVCTRL (0x44000004U) /**< \brief (PAC) Event control */ -#define REG_PAC_INTENCLR (0x44000008U) /**< \brief (PAC) Interrupt enable clear */ -#define REG_PAC_INTENSET (0x44000009U) /**< \brief (PAC) Interrupt enable set */ -#define REG_PAC_INTFLAGAHB (0x44000010U) /**< \brief (PAC) Bridge interrupt flag status */ -#define REG_PAC_INTFLAGA (0x44000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ -#define REG_PAC_INTFLAGB (0x44000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ -#define REG_PAC_INTFLAGC (0x4400001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ -#define REG_PAC_INTFLAGD (0x44000020U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */ -#define REG_PAC_INTFLAGE (0x44000024U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge E */ -#define REG_PAC_STATUSA (0x44000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */ -#define REG_PAC_STATUSB (0x44000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */ -#define REG_PAC_STATUSC (0x4400003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */ -#define REG_PAC_STATUSD (0x44000040U) /**< \brief (PAC) Peripheral write protection status - Bridge D */ -#define REG_PAC_STATUSE (0x44000044U) /**< \brief (PAC) Peripheral write protection status - Bridge E */ -#else -#define REG_PAC_WRCTRL (*(RwReg *)0x44000000U) /**< \brief (PAC) Write control */ -#define REG_PAC_EVCTRL (*(RwReg8 *)0x44000004U) /**< \brief (PAC) Event control */ -#define REG_PAC_INTENCLR (*(RwReg8 *)0x44000008U) /**< \brief (PAC) Interrupt enable clear */ -#define REG_PAC_INTENSET (*(RwReg8 *)0x44000009U) /**< \brief (PAC) Interrupt enable set */ -#define REG_PAC_INTFLAGAHB (*(RwReg *)0x44000010U) /**< \brief (PAC) Bridge interrupt flag status */ -#define REG_PAC_INTFLAGA (*(RwReg *)0x44000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ -#define REG_PAC_INTFLAGB (*(RwReg *)0x44000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ -#define REG_PAC_INTFLAGC (*(RwReg *)0x4400001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ -#define REG_PAC_INTFLAGD (*(RwReg *)0x44000020U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */ -#define REG_PAC_INTFLAGE (*(RwReg *)0x44000024U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge E */ -#define REG_PAC_STATUSA (*(RoReg *)0x44000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */ -#define REG_PAC_STATUSB (*(RoReg *)0x44000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */ -#define REG_PAC_STATUSC (*(RoReg *)0x4400003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */ -#define REG_PAC_STATUSD (*(RoReg *)0x44000040U) /**< \brief (PAC) Peripheral write protection status - Bridge D */ -#define REG_PAC_STATUSE (*(RoReg *)0x44000044U) /**< \brief (PAC) Peripheral write protection status - Bridge E */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC peripheral ========== */ -#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock -#define PAC_CLK_AHB_ID 14 // AHB clock index -#define PAC_HPB_NUM 5 // Number of bridges AHB/APB -#define PAC_INTFLAG_NUM 6 // Number of intflag registers - -#endif /* _SAML21_PAC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pm.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pm.h deleted file mode 100644 index a80807decaf..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * \brief Instance description for PM - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_PM_INSTANCE_ -#define _SAML21_PM_INSTANCE_ - -/* ========== Register definition for PM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PM_CTRLA (0x40000000U) /**< \brief (PM) Control A */ -#define REG_PM_SLEEPCFG (0x40000001U) /**< \brief (PM) Sleep Configuration */ -#define REG_PM_PLCFG (0x40000002U) /**< \brief (PM) Performance Level Configuration */ -#define REG_PM_INTENCLR (0x40000004U) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (0x40000005U) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (0x40000006U) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_STDBYCFG (0x40000008U) /**< \brief (PM) Standby Configuration */ -#define REG_PM_PWSAKDLY (0x4000000CU) /**< \brief (PM) Power Switch Acknowledge Delay */ -#else -#define REG_PM_CTRLA (*(RwReg8 *)0x40000000U) /**< \brief (PM) Control A */ -#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000001U) /**< \brief (PM) Sleep Configuration */ -#define REG_PM_PLCFG (*(RwReg8 *)0x40000002U) /**< \brief (PM) Performance Level Configuration */ -#define REG_PM_INTENCLR (*(RwReg8 *)0x40000004U) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (*(RwReg8 *)0x40000005U) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (*(RwReg8 *)0x40000006U) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_STDBYCFG (*(RwReg16*)0x40000008U) /**< \brief (PM) Standby Configuration */ -#define REG_PM_PWSAKDLY (*(RwReg8 *)0x4000000CU) /**< \brief (PM) Power Switch Acknowledge Delay */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PM peripheral ========== */ -#define PM_PD_NUM 3 // Number of switchable Power Domain - -#endif /* _SAML21_PM_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_port.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_port.h deleted file mode 100644 index 2f7dc012576..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_port.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * \file - * - * \brief Instance description for PORT - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_PORT_INSTANCE_ -#define _SAML21_PORT_INSTANCE_ - -/* ========== Register definition for PORT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PORT_DIR0 (0x40002800U) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (0x40002804U) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (0x40002808U) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (0x4000280CU) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (0x40002810U) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (0x40002814U) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (0x40002818U) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (0x4000281CU) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (0x40002820U) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (0x40002824U) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (0x40002828U) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_EVCTRL0 (0x4000282CU) /**< \brief (PORT) Event Input Control 0 */ -#define REG_PORT_PMUX0 (0x40002830U) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (0x40002840U) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (0x40002880U) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (0x40002884U) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (0x40002888U) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (0x4000288CU) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (0x40002890U) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (0x40002894U) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (0x40002898U) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (0x4000289CU) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (0x400028A0U) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (0x400028A4U) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (0x400028A8U) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_EVCTRL1 (0x400028ACU) /**< \brief (PORT) Event Input Control 1 */ -#define REG_PORT_PMUX1 (0x400028B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (0x400028C0U) /**< \brief (PORT) Pin Configuration 1 */ -#else -#define REG_PORT_DIR0 (*(RwReg *)0x40002800U) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (*(RwReg *)0x40002804U) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (*(RwReg *)0x40002808U) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (*(RwReg *)0x4000280CU) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (*(RwReg *)0x40002810U) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (*(RwReg *)0x40002814U) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (*(RwReg *)0x40002818U) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (*(RwReg *)0x4000281CU) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (*(RoReg *)0x40002820U) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (*(RwReg *)0x40002824U) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (*(WoReg *)0x40002828U) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_EVCTRL0 (*(RwReg *)0x4000282CU) /**< \brief (PORT) Event Input Control 0 */ -#define REG_PORT_PMUX0 (*(RwReg *)0x40002830U) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (*(RwReg *)0x40002840U) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (*(RwReg *)0x40002880U) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (*(RwReg *)0x40002884U) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (*(RwReg *)0x40002888U) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (*(RwReg *)0x4000288CU) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (*(RwReg *)0x40002890U) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (*(RwReg *)0x40002894U) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (*(RwReg *)0x40002898U) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (*(RwReg *)0x4000289CU) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (*(RoReg *)0x400028A0U) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (*(RwReg *)0x400028A4U) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (*(WoReg *)0x400028A8U) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_EVCTRL1 (*(RwReg *)0x400028ACU) /**< \brief (PORT) Event Input Control 1 */ -#define REG_PORT_PMUX1 (*(RwReg *)0x400028B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (*(RwReg *)0x400028C0U) /**< \brief (PORT) Pin Configuration 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PORT peripheral ========== */ -#define PORT_BITS 84 -#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } -#define PORT_DRVSTR 1 // DRVSTR supported? -#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000D0000 } -#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF, 0x00000000 } -#define PORT_EV_NUM 4 -#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } -#define PORT_ODRAIN 0 // ODRAIN supported? -#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } -#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } -#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x000D0000 } -#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x00000000 } -#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } -#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x000D0000 } -#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } -#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CFC7, 0x00000000 } -#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } -#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } -#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } -#define PORT_SLEWLIM 0 // SLEWLIM supported? -#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } - -#endif /* _SAML21_PORT_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rstc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rstc.h deleted file mode 100644 index 9b8b23f51d1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rstc.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * \file - * - * \brief Instance description for RSTC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_RSTC_INSTANCE_ -#define _SAML21_RSTC_INSTANCE_ - -/* ========== Register definition for RSTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RSTC_RCAUSE (0x40000800U) /**< \brief (RSTC) Reset Cause */ -#define REG_RSTC_BKUPEXIT (0x40000802U) /**< \brief (RSTC) Backup Exit Source */ -#define REG_RSTC_WKDBCONF (0x40000804U) /**< \brief (RSTC) Wakeup Debounce Configuration */ -#define REG_RSTC_WKPOL (0x40000808U) /**< \brief (RSTC) Wakeup Polarity */ -#define REG_RSTC_WKEN (0x4000080CU) /**< \brief (RSTC) Wakeup Enable */ -#define REG_RSTC_WKCAUSE (0x40000810U) /**< \brief (RSTC) Wakeup Cause */ -#else -#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000800U) /**< \brief (RSTC) Reset Cause */ -#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000802U) /**< \brief (RSTC) Backup Exit Source */ -#define REG_RSTC_WKDBCONF (*(RwReg8 *)0x40000804U) /**< \brief (RSTC) Wakeup Debounce Configuration */ -#define REG_RSTC_WKPOL (*(RwReg16*)0x40000808U) /**< \brief (RSTC) Wakeup Polarity */ -#define REG_RSTC_WKEN (*(RwReg16*)0x4000080CU) /**< \brief (RSTC) Wakeup Enable */ -#define REG_RSTC_WKCAUSE (*(RwReg16*)0x40000810U) /**< \brief (RSTC) Wakeup Cause */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RSTC peripheral ========== */ -#define RSTC_NUMBER_OF_EXTWAKE 8 // number of external wakeup line - -#endif /* _SAML21_RSTC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rtc.h deleted file mode 100644 index 7e399616d1b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rtc.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - * \file - * - * \brief Instance description for RTC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_RTC_INSTANCE_ -#define _SAML21_RTC_INSTANCE_ - -/* ========== Register definition for RTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTC_DBGCTRL (0x4000200EU) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (0x40002014U) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_GP0 (0x40002040U) /**< \brief (RTC) General Purpose 0 */ -#define REG_RTC_GP1 (0x40002044U) /**< \brief (RTC) General Purpose 1 */ -#define REG_RTC_GP2 (0x40002048U) /**< \brief (RTC) General Purpose 2 */ -#define REG_RTC_GP3 (0x4000204CU) /**< \brief (RTC) General Purpose 3 */ -#define REG_RTC_MODE0_CTRLA (0x40002000U) /**< \brief (RTC) MODE0 Control A */ -#define REG_RTC_MODE0_EVCTRL (0x40002004U) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (0x40002008U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (0x4000200AU) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (0x4000200CU) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_SYNCBUSY (0x40002010U) /**< \brief (RTC) MODE0 Synchronization Busy Status */ -#define REG_RTC_MODE0_COUNT (0x40002018U) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (0x40002020U) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE1_CTRLA (0x40002000U) /**< \brief (RTC) MODE1 Control A */ -#define REG_RTC_MODE1_EVCTRL (0x40002004U) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (0x40002008U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (0x4000200AU) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (0x4000200CU) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_SYNCBUSY (0x40002010U) /**< \brief (RTC) MODE1 Synchronization Busy Status */ -#define REG_RTC_MODE1_COUNT (0x40002018U) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (0x4000201CU) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (0x40002020U) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (0x40002022U) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE2_CTRLA (0x40002000U) /**< \brief (RTC) MODE2 Control A */ -#define REG_RTC_MODE2_EVCTRL (0x40002004U) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (0x40002008U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (0x4000200AU) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (0x4000200CU) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_SYNCBUSY (0x40002010U) /**< \brief (RTC) MODE2 Synchronization Busy Status */ -#define REG_RTC_MODE2_CLOCK (0x40002018U) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002020U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (0x40002024U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#else -#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000200EU) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002014U) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_GP0 (*(RwReg *)0x40002040U) /**< \brief (RTC) General Purpose 0 */ -#define REG_RTC_GP1 (*(RwReg *)0x40002044U) /**< \brief (RTC) General Purpose 1 */ -#define REG_RTC_GP2 (*(RwReg *)0x40002048U) /**< \brief (RTC) General Purpose 2 */ -#define REG_RTC_GP3 (*(RwReg *)0x4000204CU) /**< \brief (RTC) General Purpose 3 */ -#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002000U) /**< \brief (RTC) MODE0 Control A */ -#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002004U) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002008U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000200AU) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000200CU) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002010U) /**< \brief (RTC) MODE0 Synchronization Busy Status */ -#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002018U) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002020U) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002000U) /**< \brief (RTC) MODE1 Control A */ -#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002004U) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002008U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000200AU) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000200CU) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002010U) /**< \brief (RTC) MODE1 Synchronization Busy Status */ -#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002018U) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000201CU) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002020U) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002022U) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002000U) /**< \brief (RTC) MODE2 Control A */ -#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002004U) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002008U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000200AU) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000200CU) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002010U) /**< \brief (RTC) MODE2 Synchronization Busy Status */ -#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002018U) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002020U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x40002024U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RTC peripheral ========== */ -#define RTC_ALARM_NUM 1 // Number of Alarms -#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators -#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators -#define RTC_GPR_NUM 4 // Number of General-Purpose Registers -#define RTC_PER_NUM 8 // Number of Periodic Intervals - -#endif /* _SAML21_RTC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom0.h deleted file mode 100644 index 59a7b1ea642..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom0.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM0 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SERCOM0_INSTANCE_ -#define _SAML21_SERCOM0_INSTANCE_ - -/* ========== Register definition for SERCOM0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM0_I2CM_CTRLA (0x42000000U) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (0x42000004U) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (0x4200000CU) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (0x42000014U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (0x42000016U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (0x42000018U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (0x4200001AU) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200001CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */ -#define REG_SERCOM0_I2CM_ADDR (0x42000024U) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (0x42000028U) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (0x42000030U) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (0x42000000U) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (0x42000004U) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (0x42000014U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (0x42000016U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (0x42000018U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (0x4200001AU) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200001CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */ -#define REG_SERCOM0_I2CS_ADDR (0x42000024U) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (0x42000028U) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (0x42000000U) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (0x42000004U) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (0x4200000CU) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (0x42000014U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (0x42000016U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (0x42000018U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (0x4200001AU) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (0x4200001CU) /**< \brief (SERCOM0) SPI Synchronization Busy */ -#define REG_SERCOM0_SPI_ADDR (0x42000024U) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (0x42000028U) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (0x42000030U) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (0x42000000U) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (0x42000004U) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_BAUD (0x4200000CU) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (0x4200000EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (0x42000014U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (0x42000016U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (0x42000018U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (0x4200001AU) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (0x4200001CU) /**< \brief (SERCOM0) USART Synchronization Busy */ -#define REG_SERCOM0_USART_DATA (0x42000028U) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (0x42000030U) /**< \brief (SERCOM0) USART Debug Control */ -#else -#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000000U) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000004U) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200000CU) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000014U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000016U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000018U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200001AU) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200001CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */ -#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000024U) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000028U) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000030U) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000000U) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000004U) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000014U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000016U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000018U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200001AU) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200001CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */ -#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000024U) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000028U) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000000U) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000004U) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200000CU) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000014U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000016U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000018U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200001AU) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200001CU) /**< \brief (SERCOM0) SPI Synchronization Busy */ -#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000024U) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000028U) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000030U) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000000U) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000004U) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200000CU) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200000EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000014U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000016U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000018U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200001AU) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200001CU) /**< \brief (SERCOM0) USART Synchronization Busy */ -#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000028U) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000030U) /**< \brief (SERCOM0) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM0 peripheral ========== */ -#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger -#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger -#define SERCOM0_GCLK_ID_CORE 18 -#define SERCOM0_GCLK_ID_SLOW 17 -#define SERCOM0_INT_MSB 6 -#define SERCOM0_PMSB 3 - -#endif /* _SAML21_SERCOM0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom1.h deleted file mode 100644 index c4529e0ca2c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom1.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM1 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SERCOM1_INSTANCE_ -#define _SAML21_SERCOM1_INSTANCE_ - -/* ========== Register definition for SERCOM1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM1_I2CM_CTRLA (0x42000400U) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (0x42000404U) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (0x4200040CU) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (0x42000414U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (0x42000416U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (0x42000418U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (0x4200041AU) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */ -#define REG_SERCOM1_I2CM_ADDR (0x42000424U) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (0x42000428U) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (0x42000430U) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (0x42000400U) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (0x42000404U) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (0x42000414U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (0x42000416U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (0x42000418U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (0x4200041AU) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */ -#define REG_SERCOM1_I2CS_ADDR (0x42000424U) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (0x42000428U) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (0x42000400U) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (0x42000404U) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (0x4200040CU) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (0x42000414U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (0x42000416U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (0x42000418U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (0x4200041AU) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM1) SPI Synchronization Busy */ -#define REG_SERCOM1_SPI_ADDR (0x42000424U) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (0x42000428U) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (0x42000430U) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (0x42000400U) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (0x42000404U) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_BAUD (0x4200040CU) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (0x4200040EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (0x42000414U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (0x42000416U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (0x42000418U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (0x4200041AU) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM1) USART Synchronization Busy */ -#define REG_SERCOM1_USART_DATA (0x42000428U) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (0x42000430U) /**< \brief (SERCOM1) USART Debug Control */ -#else -#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200040CU) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */ -#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000428U) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */ -#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000428U) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200040CU) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM1) SPI Synchronization Busy */ -#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000428U) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200040CU) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200040EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM1) USART Synchronization Busy */ -#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000428U) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM1) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM1 peripheral ========== */ -#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger -#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger -#define SERCOM1_GCLK_ID_CORE 19 -#define SERCOM1_GCLK_ID_SLOW 17 -#define SERCOM1_INT_MSB 6 -#define SERCOM1_PMSB 3 - -#endif /* _SAML21_SERCOM1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom2.h deleted file mode 100644 index 6a0ef980042..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom2.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM2 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SERCOM2_INSTANCE_ -#define _SAML21_SERCOM2_INSTANCE_ - -/* ========== Register definition for SERCOM2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM2_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */ -#define REG_SERCOM2_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (0x42000828U) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */ -#define REG_SERCOM2_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (0x42000828U) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM2) SPI Synchronization Busy */ -#define REG_SERCOM2_SPI_ADDR (0x42000824U) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (0x42000828U) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (0x42000800U) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (0x42000804U) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_BAUD (0x4200080CU) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (0x4200080EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (0x42000816U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (0x4200081AU) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM2) USART Synchronization Busy */ -#define REG_SERCOM2_USART_DATA (0x42000828U) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM2) USART Debug Control */ -#else -#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */ -#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */ -#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM2) SPI Synchronization Busy */ -#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM2) USART Synchronization Busy */ -#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM2) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM2 peripheral ========== */ -#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger -#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger -#define SERCOM2_GCLK_ID_CORE 20 -#define SERCOM2_GCLK_ID_SLOW 17 -#define SERCOM2_INT_MSB 6 -#define SERCOM2_PMSB 3 - -#endif /* _SAML21_SERCOM2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom3.h deleted file mode 100644 index c5b619764e7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom3.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM3 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SERCOM3_INSTANCE_ -#define _SAML21_SERCOM3_INSTANCE_ - -/* ========== Register definition for SERCOM3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM3_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */ -#define REG_SERCOM3_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */ -#define REG_SERCOM3_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM3) SPI Synchronization Busy */ -#define REG_SERCOM3_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (0x42000C28U) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM3) USART Synchronization Busy */ -#define REG_SERCOM3_USART_DATA (0x42000C28U) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM3) USART Debug Control */ -#else -#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */ -#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */ -#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM3) SPI Synchronization Busy */ -#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM3) USART Synchronization Busy */ -#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM3) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM3 peripheral ========== */ -#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger -#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger -#define SERCOM3_GCLK_ID_CORE 21 -#define SERCOM3_GCLK_ID_SLOW 17 -#define SERCOM3_INT_MSB 6 -#define SERCOM3_PMSB 3 - -#endif /* _SAML21_SERCOM3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom4.h deleted file mode 100644 index 29febfb5b02..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom4.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM4 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SERCOM4_INSTANCE_ -#define _SAML21_SERCOM4_INSTANCE_ - -/* ========== Register definition for SERCOM4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM4_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */ -#define REG_SERCOM4_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (0x42001028U) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */ -#define REG_SERCOM4_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (0x42001028U) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM4) SPI Synchronization Busy */ -#define REG_SERCOM4_SPI_ADDR (0x42001024U) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (0x42001028U) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (0x42001000U) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (0x42001004U) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_BAUD (0x4200100CU) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (0x4200100EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (0x42001016U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (0x4200101AU) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM4) USART Synchronization Busy */ -#define REG_SERCOM4_USART_DATA (0x42001028U) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM4) USART Debug Control */ -#else -#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */ -#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */ -#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM4) SPI Synchronization Busy */ -#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM4) USART Synchronization Busy */ -#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM4) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM4 peripheral ========== */ -#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger -#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger -#define SERCOM4_GCLK_ID_CORE 22 -#define SERCOM4_GCLK_ID_SLOW 17 -#define SERCOM4_INT_MSB 6 -#define SERCOM4_PMSB 3 - -#endif /* _SAML21_SERCOM4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom5.h deleted file mode 100644 index a6eecaac8b9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom5.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM5 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SERCOM5_INSTANCE_ -#define _SAML21_SERCOM5_INSTANCE_ - -/* ========== Register definition for SERCOM5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM5_I2CM_CTRLA (0x43000400U) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (0x43000404U) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (0x4300040CU) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (0x43000414U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (0x43000416U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (0x43000418U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (0x4300041AU) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (0x4300041CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */ -#define REG_SERCOM5_I2CM_ADDR (0x43000424U) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (0x43000428U) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (0x43000430U) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (0x43000400U) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (0x43000404U) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (0x43000414U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (0x43000416U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (0x43000418U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (0x4300041AU) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (0x4300041CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */ -#define REG_SERCOM5_I2CS_ADDR (0x43000424U) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (0x43000428U) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (0x43000400U) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (0x43000404U) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (0x4300040CU) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (0x43000414U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (0x43000416U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (0x43000418U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (0x4300041AU) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (0x4300041CU) /**< \brief (SERCOM5) SPI Synchronization Busy */ -#define REG_SERCOM5_SPI_ADDR (0x43000424U) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (0x43000428U) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (0x43000430U) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (0x43000400U) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (0x43000404U) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_BAUD (0x4300040CU) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (0x4300040EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (0x43000414U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (0x43000416U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (0x43000418U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (0x4300041AU) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (0x4300041CU) /**< \brief (SERCOM5) USART Synchronization Busy */ -#define REG_SERCOM5_USART_DATA (0x43000428U) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (0x43000430U) /**< \brief (SERCOM5) USART Debug Control */ -#else -#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x43000400U) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x43000404U) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4300040CU) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x43000414U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x43000416U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x43000418U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4300041AU) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4300041CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */ -#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x43000424U) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x43000428U) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x43000430U) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x43000400U) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x43000404U) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x43000414U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x43000416U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x43000418U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4300041AU) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4300041CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */ -#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x43000424U) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x43000428U) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x43000400U) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x43000404U) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4300040CU) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x43000414U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x43000416U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x43000418U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4300041AU) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4300041CU) /**< \brief (SERCOM5) SPI Synchronization Busy */ -#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x43000424U) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x43000428U) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x43000430U) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x43000400U) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x43000404U) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4300040CU) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4300040EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x43000414U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x43000416U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x43000418U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4300041AU) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4300041CU) /**< \brief (SERCOM5) USART Synchronization Busy */ -#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x43000428U) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x43000430U) /**< \brief (SERCOM5) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM5 peripheral ========== */ -#define SERCOM5_DMAC_ID_RX // Index of DMA RX trigger -#define SERCOM5_DMAC_ID_TX // Index of DMA TX trigger -#define SERCOM5_GCLK_ID_CORE 24 -#define SERCOM5_GCLK_ID_SLOW 23 -#define SERCOM5_INT_MSB 3 -#define SERCOM5_PMSB 3 - -#endif /* _SAML21_SERCOM5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_supc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_supc.h deleted file mode 100644 index 26f8402d999..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_supc.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * \file - * - * \brief Instance description for SUPC - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_SUPC_INSTANCE_ -#define _SAML21_SUPC_INSTANCE_ - -/* ========== Register definition for SUPC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SUPC_INTENCLR (0x40001400U) /**< \brief (SUPC) Interrupt Enable Clear */ -#define REG_SUPC_INTENSET (0x40001404U) /**< \brief (SUPC) Interrupt Enable Set */ -#define REG_SUPC_INTFLAG (0x40001408U) /**< \brief (SUPC) Interrupt Flag Status and Clear */ -#define REG_SUPC_STATUS (0x4000140CU) /**< \brief (SUPC) Power and Clocks Status */ -#define REG_SUPC_BOD33 (0x40001410U) /**< \brief (SUPC) BOD33 Control */ -#define REG_SUPC_BOD12 (0x40001414U) /**< \brief (SUPC) BOD12 Control */ -#define REG_SUPC_VREG (0x40001418U) /**< \brief (SUPC) VREG Control */ -#define REG_SUPC_VREF (0x4000141CU) /**< \brief (SUPC) VREF Control */ -#define REG_SUPC_BBPS (0x40001420U) /**< \brief (SUPC) Battery Backup Power Switch */ -#define REG_SUPC_BKOUT (0x40001424U) /**< \brief (SUPC) Backup Output Control */ -#define REG_SUPC_BKIN (0x40001428U) /**< \brief (SUPC) Backup Input Control */ -#else -#define REG_SUPC_INTENCLR (*(RwReg *)0x40001400U) /**< \brief (SUPC) Interrupt Enable Clear */ -#define REG_SUPC_INTENSET (*(RwReg *)0x40001404U) /**< \brief (SUPC) Interrupt Enable Set */ -#define REG_SUPC_INTFLAG (*(RwReg *)0x40001408U) /**< \brief (SUPC) Interrupt Flag Status and Clear */ -#define REG_SUPC_STATUS (*(RoReg *)0x4000140CU) /**< \brief (SUPC) Power and Clocks Status */ -#define REG_SUPC_BOD33 (*(RwReg *)0x40001410U) /**< \brief (SUPC) BOD33 Control */ -#define REG_SUPC_BOD12 (*(RwReg *)0x40001414U) /**< \brief (SUPC) BOD12 Control */ -#define REG_SUPC_VREG (*(RwReg *)0x40001418U) /**< \brief (SUPC) VREG Control */ -#define REG_SUPC_VREF (*(RwReg *)0x4000141CU) /**< \brief (SUPC) VREF Control */ -#define REG_SUPC_BBPS (*(RwReg *)0x40001420U) /**< \brief (SUPC) Battery Backup Power Switch */ -#define REG_SUPC_BKOUT (*(RwReg *)0x40001424U) /**< \brief (SUPC) Backup Output Control */ -#define REG_SUPC_BKIN (*(RoReg *)0x40001428U) /**< \brief (SUPC) Backup Input Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SUPC peripheral ========== */ -#define SUPC_BOD12_CALIB_MSB 5 -#define SUPC_BOD33_CALIB_MSB 5 -#define SUPC_SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number - -#endif /* _SAML21_SUPC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tal.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tal.h deleted file mode 100644 index 6dc5b256c2e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tal.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - * \file - * - * \brief Instance description for TAL - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TAL_INSTANCE_ -#define _SAML21_TAL_INSTANCE_ - -/* ========== Register definition for TAL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TAL_CTRLA (0x40002C00U) /**< \brief (TAL) Control A */ -#define REG_TAL_RSTCTRL (0x40002C04U) /**< \brief (TAL) Reset Control */ -#define REG_TAL_EXTCTRL (0x40002C05U) /**< \brief (TAL) External Break Control */ -#define REG_TAL_EVCTRL (0x40002C06U) /**< \brief (TAL) Event Control */ -#define REG_TAL_INTENCLR (0x40002C08U) /**< \brief (TAL) Interrupt Enable Clear */ -#define REG_TAL_INTENSET (0x40002C09U) /**< \brief (TAL) Interrupt Enable Set */ -#define REG_TAL_INTFLAG (0x40002C0AU) /**< \brief (TAL) Interrupt Flag Status and Clear */ -#define REG_TAL_GLOBMASK (0x40002C0BU) /**< \brief (TAL) Global Break Requests Mask */ -#define REG_TAL_HALT (0x40002C0CU) /**< \brief (TAL) Debug Halt Request */ -#define REG_TAL_RESTART (0x40002C0DU) /**< \brief (TAL) Debug Restart Request */ -#define REG_TAL_BRKSTATUS (0x40002C0EU) /**< \brief (TAL) Break Request Status */ -#define REG_TAL_CTICTRLA0 (0x40002C10U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */ -#define REG_TAL_CTIMASK0 (0x40002C11U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */ -#define REG_TAL_CTICTRLA1 (0x40002C12U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */ -#define REG_TAL_CTIMASK1 (0x40002C13U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */ -#define REG_TAL_CTICTRLA2 (0x40002C14U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */ -#define REG_TAL_CTIMASK2 (0x40002C15U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */ -#define REG_TAL_CTICTRLA3 (0x40002C16U) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */ -#define REG_TAL_CTIMASK3 (0x40002C17U) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */ -#define REG_TAL_INTSTATUS0 (0x40002C20U) /**< \brief (TAL) Interrupt 0 Status */ -#define REG_TAL_INTSTATUS1 (0x40002C21U) /**< \brief (TAL) Interrupt 1 Status */ -#define REG_TAL_INTSTATUS2 (0x40002C22U) /**< \brief (TAL) Interrupt 2 Status */ -#define REG_TAL_INTSTATUS3 (0x40002C23U) /**< \brief (TAL) Interrupt 3 Status */ -#define REG_TAL_INTSTATUS4 (0x40002C24U) /**< \brief (TAL) Interrupt 4 Status */ -#define REG_TAL_INTSTATUS5 (0x40002C25U) /**< \brief (TAL) Interrupt 5 Status */ -#define REG_TAL_INTSTATUS6 (0x40002C26U) /**< \brief (TAL) Interrupt 6 Status */ -#define REG_TAL_INTSTATUS7 (0x40002C27U) /**< \brief (TAL) Interrupt 7 Status */ -#define REG_TAL_INTSTATUS8 (0x40002C28U) /**< \brief (TAL) Interrupt 8 Status */ -#define REG_TAL_INTSTATUS9 (0x40002C29U) /**< \brief (TAL) Interrupt 9 Status */ -#define REG_TAL_INTSTATUS10 (0x40002C2AU) /**< \brief (TAL) Interrupt 10 Status */ -#define REG_TAL_INTSTATUS11 (0x40002C2BU) /**< \brief (TAL) Interrupt 11 Status */ -#define REG_TAL_INTSTATUS12 (0x40002C2CU) /**< \brief (TAL) Interrupt 12 Status */ -#define REG_TAL_INTSTATUS13 (0x40002C2DU) /**< \brief (TAL) Interrupt 13 Status */ -#define REG_TAL_INTSTATUS14 (0x40002C2EU) /**< \brief (TAL) Interrupt 14 Status */ -#define REG_TAL_INTSTATUS15 (0x40002C2FU) /**< \brief (TAL) Interrupt 15 Status */ -#define REG_TAL_INTSTATUS16 (0x40002C30U) /**< \brief (TAL) Interrupt 16 Status */ -#define REG_TAL_INTSTATUS17 (0x40002C31U) /**< \brief (TAL) Interrupt 17 Status */ -#define REG_TAL_INTSTATUS18 (0x40002C32U) /**< \brief (TAL) Interrupt 18 Status */ -#define REG_TAL_INTSTATUS19 (0x40002C33U) /**< \brief (TAL) Interrupt 19 Status */ -#define REG_TAL_INTSTATUS20 (0x40002C34U) /**< \brief (TAL) Interrupt 20 Status */ -#define REG_TAL_INTSTATUS21 (0x40002C35U) /**< \brief (TAL) Interrupt 21 Status */ -#define REG_TAL_INTSTATUS22 (0x40002C36U) /**< \brief (TAL) Interrupt 22 Status */ -#define REG_TAL_INTSTATUS23 (0x40002C37U) /**< \brief (TAL) Interrupt 23 Status */ -#define REG_TAL_INTSTATUS24 (0x40002C38U) /**< \brief (TAL) Interrupt 24 Status */ -#define REG_TAL_INTSTATUS25 (0x40002C39U) /**< \brief (TAL) Interrupt 25 Status */ -#define REG_TAL_INTSTATUS26 (0x40002C3AU) /**< \brief (TAL) Interrupt 26 Status */ -#define REG_TAL_INTSTATUS27 (0x40002C3BU) /**< \brief (TAL) Interrupt 27 Status */ -#define REG_TAL_INTSTATUS28 (0x40002C3CU) /**< \brief (TAL) Interrupt 28 Status */ -#define REG_TAL_DMACPUSEL0 (0x40002C40U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */ -#define REG_TAL_EVCPUSEL0 (0x40002C48U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */ -#define REG_TAL_EICCPUSEL0 (0x40002C50U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */ -#define REG_TAL_INTCPUSEL0 (0x40002C58U) /**< \brief (TAL) Interrupts CPU Select 0 */ -#define REG_TAL_INTCPUSEL1 (0x40002C5CU) /**< \brief (TAL) Interrupts CPU Select 1 */ -#define REG_TAL_IRQTRIG (0x40002C60U) /**< \brief (TAL) Interrupt Trigger */ -#else -#define REG_TAL_CTRLA (*(RwReg8 *)0x40002C00U) /**< \brief (TAL) Control A */ -#define REG_TAL_RSTCTRL (*(RwReg8 *)0x40002C04U) /**< \brief (TAL) Reset Control */ -#define REG_TAL_EXTCTRL (*(RwReg8 *)0x40002C05U) /**< \brief (TAL) External Break Control */ -#define REG_TAL_EVCTRL (*(RwReg8 *)0x40002C06U) /**< \brief (TAL) Event Control */ -#define REG_TAL_INTENCLR (*(RwReg8 *)0x40002C08U) /**< \brief (TAL) Interrupt Enable Clear */ -#define REG_TAL_INTENSET (*(RwReg8 *)0x40002C09U) /**< \brief (TAL) Interrupt Enable Set */ -#define REG_TAL_INTFLAG (*(RwReg8 *)0x40002C0AU) /**< \brief (TAL) Interrupt Flag Status and Clear */ -#define REG_TAL_GLOBMASK (*(RwReg8 *)0x40002C0BU) /**< \brief (TAL) Global Break Requests Mask */ -#define REG_TAL_HALT (*(WoReg8 *)0x40002C0CU) /**< \brief (TAL) Debug Halt Request */ -#define REG_TAL_RESTART (*(WoReg8 *)0x40002C0DU) /**< \brief (TAL) Debug Restart Request */ -#define REG_TAL_BRKSTATUS (*(RoReg16*)0x40002C0EU) /**< \brief (TAL) Break Request Status */ -#define REG_TAL_CTICTRLA0 (*(RwReg8 *)0x40002C10U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */ -#define REG_TAL_CTIMASK0 (*(RwReg8 *)0x40002C11U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */ -#define REG_TAL_CTICTRLA1 (*(RwReg8 *)0x40002C12U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */ -#define REG_TAL_CTIMASK1 (*(RwReg8 *)0x40002C13U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */ -#define REG_TAL_CTICTRLA2 (*(RwReg8 *)0x40002C14U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */ -#define REG_TAL_CTIMASK2 (*(RwReg8 *)0x40002C15U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */ -#define REG_TAL_CTICTRLA3 (*(RwReg8 *)0x40002C16U) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */ -#define REG_TAL_CTIMASK3 (*(RwReg8 *)0x40002C17U) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */ -#define REG_TAL_INTSTATUS0 (*(RoReg8 *)0x40002C20U) /**< \brief (TAL) Interrupt 0 Status */ -#define REG_TAL_INTSTATUS1 (*(RoReg8 *)0x40002C21U) /**< \brief (TAL) Interrupt 1 Status */ -#define REG_TAL_INTSTATUS2 (*(RoReg8 *)0x40002C22U) /**< \brief (TAL) Interrupt 2 Status */ -#define REG_TAL_INTSTATUS3 (*(RoReg8 *)0x40002C23U) /**< \brief (TAL) Interrupt 3 Status */ -#define REG_TAL_INTSTATUS4 (*(RoReg8 *)0x40002C24U) /**< \brief (TAL) Interrupt 4 Status */ -#define REG_TAL_INTSTATUS5 (*(RoReg8 *)0x40002C25U) /**< \brief (TAL) Interrupt 5 Status */ -#define REG_TAL_INTSTATUS6 (*(RoReg8 *)0x40002C26U) /**< \brief (TAL) Interrupt 6 Status */ -#define REG_TAL_INTSTATUS7 (*(RoReg8 *)0x40002C27U) /**< \brief (TAL) Interrupt 7 Status */ -#define REG_TAL_INTSTATUS8 (*(RoReg8 *)0x40002C28U) /**< \brief (TAL) Interrupt 8 Status */ -#define REG_TAL_INTSTATUS9 (*(RoReg8 *)0x40002C29U) /**< \brief (TAL) Interrupt 9 Status */ -#define REG_TAL_INTSTATUS10 (*(RoReg8 *)0x40002C2AU) /**< \brief (TAL) Interrupt 10 Status */ -#define REG_TAL_INTSTATUS11 (*(RoReg8 *)0x40002C2BU) /**< \brief (TAL) Interrupt 11 Status */ -#define REG_TAL_INTSTATUS12 (*(RoReg8 *)0x40002C2CU) /**< \brief (TAL) Interrupt 12 Status */ -#define REG_TAL_INTSTATUS13 (*(RoReg8 *)0x40002C2DU) /**< \brief (TAL) Interrupt 13 Status */ -#define REG_TAL_INTSTATUS14 (*(RoReg8 *)0x40002C2EU) /**< \brief (TAL) Interrupt 14 Status */ -#define REG_TAL_INTSTATUS15 (*(RoReg8 *)0x40002C2FU) /**< \brief (TAL) Interrupt 15 Status */ -#define REG_TAL_INTSTATUS16 (*(RoReg8 *)0x40002C30U) /**< \brief (TAL) Interrupt 16 Status */ -#define REG_TAL_INTSTATUS17 (*(RoReg8 *)0x40002C31U) /**< \brief (TAL) Interrupt 17 Status */ -#define REG_TAL_INTSTATUS18 (*(RoReg8 *)0x40002C32U) /**< \brief (TAL) Interrupt 18 Status */ -#define REG_TAL_INTSTATUS19 (*(RoReg8 *)0x40002C33U) /**< \brief (TAL) Interrupt 19 Status */ -#define REG_TAL_INTSTATUS20 (*(RoReg8 *)0x40002C34U) /**< \brief (TAL) Interrupt 20 Status */ -#define REG_TAL_INTSTATUS21 (*(RoReg8 *)0x40002C35U) /**< \brief (TAL) Interrupt 21 Status */ -#define REG_TAL_INTSTATUS22 (*(RoReg8 *)0x40002C36U) /**< \brief (TAL) Interrupt 22 Status */ -#define REG_TAL_INTSTATUS23 (*(RoReg8 *)0x40002C37U) /**< \brief (TAL) Interrupt 23 Status */ -#define REG_TAL_INTSTATUS24 (*(RoReg8 *)0x40002C38U) /**< \brief (TAL) Interrupt 24 Status */ -#define REG_TAL_INTSTATUS25 (*(RoReg8 *)0x40002C39U) /**< \brief (TAL) Interrupt 25 Status */ -#define REG_TAL_INTSTATUS26 (*(RoReg8 *)0x40002C3AU) /**< \brief (TAL) Interrupt 26 Status */ -#define REG_TAL_INTSTATUS27 (*(RoReg8 *)0x40002C3BU) /**< \brief (TAL) Interrupt 27 Status */ -#define REG_TAL_INTSTATUS28 (*(RoReg8 *)0x40002C3CU) /**< \brief (TAL) Interrupt 28 Status */ -#define REG_TAL_DMACPUSEL0 (*(RwReg *)0x40002C40U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */ -#define REG_TAL_EVCPUSEL0 (*(RwReg *)0x40002C48U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */ -#define REG_TAL_EICCPUSEL0 (*(RwReg *)0x40002C50U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */ -#define REG_TAL_INTCPUSEL0 (*(RwReg *)0x40002C58U) /**< \brief (TAL) Interrupts CPU Select 0 */ -#define REG_TAL_INTCPUSEL1 (*(RwReg *)0x40002C5CU) /**< \brief (TAL) Interrupts CPU Select 1 */ -#define REG_TAL_IRQTRIG (*(RwReg16*)0x40002C60U) /**< \brief (TAL) Interrupt Trigger */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TAL peripheral ========== */ -#define TAL_CPU_NUM 2 // Number of CPUs -#define TAL_CTI_NUM 4 // Number of Cross-Trigger Interfaces -#define TAL_DMA_CH_NUM 16 // Number of DMAC Channels -#define TAL_EV_CH_NUM 12 // Number of EVSYS Channels -#define TAL_EXTINT_NUM 16 // Number of EIC External Interrrupts -#define TAL_INT_NUM 29 // Number of Interrupt Requests - -#endif /* _SAML21_TAL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc0.h deleted file mode 100644 index f85c1279fd0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc0.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC0 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TC0_INSTANCE_ -#define _SAML21_TC0_INSTANCE_ - -/* ========== Register definition for TC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC0_CTRLA (0x42002000U) /**< \brief (TC0) Control A */ -#define REG_TC0_CTRLBCLR (0x42002004U) /**< \brief (TC0) Control B Clear */ -#define REG_TC0_CTRLBSET (0x42002005U) /**< \brief (TC0) Control B Set */ -#define REG_TC0_EVCTRL (0x42002006U) /**< \brief (TC0) Event Control */ -#define REG_TC0_INTENCLR (0x42002008U) /**< \brief (TC0) Interrupt Enable Clear */ -#define REG_TC0_INTENSET (0x42002009U) /**< \brief (TC0) Interrupt Enable Set */ -#define REG_TC0_INTFLAG (0x4200200AU) /**< \brief (TC0) Interrupt Flag Status and Clear */ -#define REG_TC0_STATUS (0x4200200BU) /**< \brief (TC0) Status */ -#define REG_TC0_WAVE (0x4200200CU) /**< \brief (TC0) Waveform Generation Control */ -#define REG_TC0_DRVCTRL (0x4200200DU) /**< \brief (TC0) Control C */ -#define REG_TC0_DBGCTRL (0x4200200FU) /**< \brief (TC0) Debug Control */ -#define REG_TC0_SYNCBUSY (0x42002010U) /**< \brief (TC0) Synchronization Status */ -#define REG_TC0_COUNT16_COUNT (0x42002014U) /**< \brief (TC0) COUNT16 Count */ -#define REG_TC0_COUNT16_CC0 (0x4200201CU) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ -#define REG_TC0_COUNT16_CC1 (0x4200201EU) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ -#define REG_TC0_COUNT16_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT16_CCBUF1 (0x42002032U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT32_COUNT (0x42002014U) /**< \brief (TC0) COUNT32 Count */ -#define REG_TC0_COUNT32_CC0 (0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ -#define REG_TC0_COUNT32_CC1 (0x42002020U) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ -#define REG_TC0_COUNT32_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT32_CCBUF1 (0x42002034U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT8_COUNT (0x42002014U) /**< \brief (TC0) COUNT8 Count */ -#define REG_TC0_COUNT8_PER (0x4200201BU) /**< \brief (TC0) COUNT8 Period */ -#define REG_TC0_COUNT8_CC0 (0x4200201CU) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ -#define REG_TC0_COUNT8_CC1 (0x4200201DU) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ -#define REG_TC0_COUNT8_PERBUF (0x4200202FU) /**< \brief (TC0) COUNT8 Period Buffer */ -#define REG_TC0_COUNT8_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT8_CCBUF1 (0x42002031U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TC0) Control A */ -#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TC0) Control B Clear */ -#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TC0) Control B Set */ -#define REG_TC0_EVCTRL (*(RwReg16*)0x42002006U) /**< \brief (TC0) Event Control */ -#define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008U) /**< \brief (TC0) Interrupt Enable Clear */ -#define REG_TC0_INTENSET (*(RwReg8 *)0x42002009U) /**< \brief (TC0) Interrupt Enable Set */ -#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AU) /**< \brief (TC0) Interrupt Flag Status and Clear */ -#define REG_TC0_STATUS (*(RwReg8 *)0x4200200BU) /**< \brief (TC0) Status */ -#define REG_TC0_WAVE (*(RwReg8 *)0x4200200CU) /**< \brief (TC0) Waveform Generation Control */ -#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DU) /**< \brief (TC0) Control C */ -#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FU) /**< \brief (TC0) Debug Control */ -#define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010U) /**< \brief (TC0) Synchronization Status */ -#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014U) /**< \brief (TC0) COUNT16 Count */ -#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CU) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ -#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EU) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ -#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014U) /**< \brief (TC0) COUNT32 Count */ -#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ -#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020U) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ -#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014U) /**< \brief (TC0) COUNT8 Count */ -#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BU) /**< \brief (TC0) COUNT8 Period */ -#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CU) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ -#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DU) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ -#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FU) /**< \brief (TC0) COUNT8 Period Buffer */ -#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC0 peripheral ========== */ -#define TC0_CC_NUM 2 -#define TC0_DMAC_ID_MC_0 23 -#define TC0_DMAC_ID_MC_1 24 -#define TC0_DMAC_ID_MC_LSB 23 -#define TC0_DMAC_ID_MC_MSB 24 -#define TC0_DMAC_ID_MC_SIZE 2 -#define TC0_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger -#define TC0_EXT 0 -#define TC0_GCLK_ID 27 -#define TC0_MASTER 1 -#define TC0_OW_NUM 2 - -#endif /* _SAML21_TC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc1.h deleted file mode 100644 index e9582972233..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc1.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC1 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TC1_INSTANCE_ -#define _SAML21_TC1_INSTANCE_ - -/* ========== Register definition for TC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC1_CTRLA (0x42002400U) /**< \brief (TC1) Control A */ -#define REG_TC1_CTRLBCLR (0x42002404U) /**< \brief (TC1) Control B Clear */ -#define REG_TC1_CTRLBSET (0x42002405U) /**< \brief (TC1) Control B Set */ -#define REG_TC1_EVCTRL (0x42002406U) /**< \brief (TC1) Event Control */ -#define REG_TC1_INTENCLR (0x42002408U) /**< \brief (TC1) Interrupt Enable Clear */ -#define REG_TC1_INTENSET (0x42002409U) /**< \brief (TC1) Interrupt Enable Set */ -#define REG_TC1_INTFLAG (0x4200240AU) /**< \brief (TC1) Interrupt Flag Status and Clear */ -#define REG_TC1_STATUS (0x4200240BU) /**< \brief (TC1) Status */ -#define REG_TC1_WAVE (0x4200240CU) /**< \brief (TC1) Waveform Generation Control */ -#define REG_TC1_DRVCTRL (0x4200240DU) /**< \brief (TC1) Control C */ -#define REG_TC1_DBGCTRL (0x4200240FU) /**< \brief (TC1) Debug Control */ -#define REG_TC1_SYNCBUSY (0x42002410U) /**< \brief (TC1) Synchronization Status */ -#define REG_TC1_COUNT16_COUNT (0x42002414U) /**< \brief (TC1) COUNT16 Count */ -#define REG_TC1_COUNT16_CC0 (0x4200241CU) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ -#define REG_TC1_COUNT16_CC1 (0x4200241EU) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ -#define REG_TC1_COUNT16_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT16_CCBUF1 (0x42002432U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT32_COUNT (0x42002414U) /**< \brief (TC1) COUNT32 Count */ -#define REG_TC1_COUNT32_CC0 (0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ -#define REG_TC1_COUNT32_CC1 (0x42002420U) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ -#define REG_TC1_COUNT32_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT32_CCBUF1 (0x42002434U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT8_COUNT (0x42002414U) /**< \brief (TC1) COUNT8 Count */ -#define REG_TC1_COUNT8_PER (0x4200241BU) /**< \brief (TC1) COUNT8 Period */ -#define REG_TC1_COUNT8_CC0 (0x4200241CU) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ -#define REG_TC1_COUNT8_CC1 (0x4200241DU) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ -#define REG_TC1_COUNT8_PERBUF (0x4200242FU) /**< \brief (TC1) COUNT8 Period Buffer */ -#define REG_TC1_COUNT8_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT8_CCBUF1 (0x42002431U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TC1) Control A */ -#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TC1) Control B Clear */ -#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TC1) Control B Set */ -#define REG_TC1_EVCTRL (*(RwReg16*)0x42002406U) /**< \brief (TC1) Event Control */ -#define REG_TC1_INTENCLR (*(RwReg8 *)0x42002408U) /**< \brief (TC1) Interrupt Enable Clear */ -#define REG_TC1_INTENSET (*(RwReg8 *)0x42002409U) /**< \brief (TC1) Interrupt Enable Set */ -#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240AU) /**< \brief (TC1) Interrupt Flag Status and Clear */ -#define REG_TC1_STATUS (*(RwReg8 *)0x4200240BU) /**< \brief (TC1) Status */ -#define REG_TC1_WAVE (*(RwReg8 *)0x4200240CU) /**< \brief (TC1) Waveform Generation Control */ -#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200240DU) /**< \brief (TC1) Control C */ -#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200240FU) /**< \brief (TC1) Debug Control */ -#define REG_TC1_SYNCBUSY (*(RoReg *)0x42002410U) /**< \brief (TC1) Synchronization Status */ -#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002414U) /**< \brief (TC1) COUNT16 Count */ -#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200241CU) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ -#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241EU) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ -#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42002430U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42002432U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002414U) /**< \brief (TC1) COUNT32 Count */ -#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ -#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42002420U) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ -#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42002430U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42002434U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002414U) /**< \brief (TC1) COUNT8 Count */ -#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200241BU) /**< \brief (TC1) COUNT8 Period */ -#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200241CU) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ -#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200241DU) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ -#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200242FU) /**< \brief (TC1) COUNT8 Period Buffer */ -#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42002430U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42002431U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC1 peripheral ========== */ -#define TC1_CC_NUM 2 -#define TC1_DMAC_ID_MC_0 26 -#define TC1_DMAC_ID_MC_1 27 -#define TC1_DMAC_ID_MC_LSB 26 -#define TC1_DMAC_ID_MC_MSB 27 -#define TC1_DMAC_ID_MC_SIZE 2 -#define TC1_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger -#define TC1_EXT 0 -#define TC1_GCLK_ID 27 -#define TC1_MASTER 0 -#define TC1_OW_NUM 2 - -#endif /* _SAML21_TC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc2.h deleted file mode 100644 index 495b772ab90..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc2.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC2 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TC2_INSTANCE_ -#define _SAML21_TC2_INSTANCE_ - -/* ========== Register definition for TC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC2_CTRLA (0x42002800U) /**< \brief (TC2) Control A */ -#define REG_TC2_CTRLBCLR (0x42002804U) /**< \brief (TC2) Control B Clear */ -#define REG_TC2_CTRLBSET (0x42002805U) /**< \brief (TC2) Control B Set */ -#define REG_TC2_EVCTRL (0x42002806U) /**< \brief (TC2) Event Control */ -#define REG_TC2_INTENCLR (0x42002808U) /**< \brief (TC2) Interrupt Enable Clear */ -#define REG_TC2_INTENSET (0x42002809U) /**< \brief (TC2) Interrupt Enable Set */ -#define REG_TC2_INTFLAG (0x4200280AU) /**< \brief (TC2) Interrupt Flag Status and Clear */ -#define REG_TC2_STATUS (0x4200280BU) /**< \brief (TC2) Status */ -#define REG_TC2_WAVE (0x4200280CU) /**< \brief (TC2) Waveform Generation Control */ -#define REG_TC2_DRVCTRL (0x4200280DU) /**< \brief (TC2) Control C */ -#define REG_TC2_DBGCTRL (0x4200280FU) /**< \brief (TC2) Debug Control */ -#define REG_TC2_SYNCBUSY (0x42002810U) /**< \brief (TC2) Synchronization Status */ -#define REG_TC2_COUNT16_COUNT (0x42002814U) /**< \brief (TC2) COUNT16 Count */ -#define REG_TC2_COUNT16_CC0 (0x4200281CU) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ -#define REG_TC2_COUNT16_CC1 (0x4200281EU) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ -#define REG_TC2_COUNT16_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT16_CCBUF1 (0x42002832U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT32_COUNT (0x42002814U) /**< \brief (TC2) COUNT32 Count */ -#define REG_TC2_COUNT32_CC0 (0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ -#define REG_TC2_COUNT32_CC1 (0x42002820U) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ -#define REG_TC2_COUNT32_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT32_CCBUF1 (0x42002834U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT8_COUNT (0x42002814U) /**< \brief (TC2) COUNT8 Count */ -#define REG_TC2_COUNT8_PER (0x4200281BU) /**< \brief (TC2) COUNT8 Period */ -#define REG_TC2_COUNT8_CC0 (0x4200281CU) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ -#define REG_TC2_COUNT8_CC1 (0x4200281DU) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ -#define REG_TC2_COUNT8_PERBUF (0x4200282FU) /**< \brief (TC2) COUNT8 Period Buffer */ -#define REG_TC2_COUNT8_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT8_CCBUF1 (0x42002831U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TC2) Control A */ -#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TC2) Control B Clear */ -#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TC2) Control B Set */ -#define REG_TC2_EVCTRL (*(RwReg16*)0x42002806U) /**< \brief (TC2) Event Control */ -#define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808U) /**< \brief (TC2) Interrupt Enable Clear */ -#define REG_TC2_INTENSET (*(RwReg8 *)0x42002809U) /**< \brief (TC2) Interrupt Enable Set */ -#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AU) /**< \brief (TC2) Interrupt Flag Status and Clear */ -#define REG_TC2_STATUS (*(RwReg8 *)0x4200280BU) /**< \brief (TC2) Status */ -#define REG_TC2_WAVE (*(RwReg8 *)0x4200280CU) /**< \brief (TC2) Waveform Generation Control */ -#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DU) /**< \brief (TC2) Control C */ -#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FU) /**< \brief (TC2) Debug Control */ -#define REG_TC2_SYNCBUSY (*(RoReg *)0x42002810U) /**< \brief (TC2) Synchronization Status */ -#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002814U) /**< \brief (TC2) COUNT16 Count */ -#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200281CU) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ -#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281EU) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ -#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42002830U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42002832U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002814U) /**< \brief (TC2) COUNT32 Count */ -#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ -#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42002820U) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ -#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42002830U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42002834U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814U) /**< \brief (TC2) COUNT8 Count */ -#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200281BU) /**< \brief (TC2) COUNT8 Period */ -#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200281CU) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ -#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200281DU) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ -#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200282FU) /**< \brief (TC2) COUNT8 Period Buffer */ -#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42002830U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42002831U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC2 peripheral ========== */ -#define TC2_CC_NUM 2 -#define TC2_DMAC_ID_MC_0 29 -#define TC2_DMAC_ID_MC_1 30 -#define TC2_DMAC_ID_MC_LSB 29 -#define TC2_DMAC_ID_MC_MSB 30 -#define TC2_DMAC_ID_MC_SIZE 2 -#define TC2_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger -#define TC2_EXT 0 -#define TC2_GCLK_ID 28 -#define TC2_MASTER 1 -#define TC2_OW_NUM 2 - -#endif /* _SAML21_TC2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc3.h deleted file mode 100644 index 2ff7883a822..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc3.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC3 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TC3_INSTANCE_ -#define _SAML21_TC3_INSTANCE_ - -/* ========== Register definition for TC3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */ -#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */ -#define REG_TC3_EVCTRL (0x42002C06U) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (0x42002C0BU) /**< \brief (TC3) Status */ -#define REG_TC3_WAVE (0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */ -#define REG_TC3_DRVCTRL (0x42002C0DU) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (0x42002C0FU) /**< \brief (TC3) Debug Control */ -#define REG_TC3_SYNCBUSY (0x42002C10U) /**< \brief (TC3) Synchronization Status */ -#define REG_TC3_COUNT16_COUNT (0x42002C14U) /**< \brief (TC3) COUNT16 Count */ -#define REG_TC3_COUNT16_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ -#define REG_TC3_COUNT16_CC1 (0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ -#define REG_TC3_COUNT16_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT16_CCBUF1 (0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT32_COUNT (0x42002C14U) /**< \brief (TC3) COUNT32 Count */ -#define REG_TC3_COUNT32_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ -#define REG_TC3_COUNT32_CC1 (0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ -#define REG_TC3_COUNT32_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT32_CCBUF1 (0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT8_COUNT (0x42002C14U) /**< \brief (TC3) COUNT8 Count */ -#define REG_TC3_COUNT8_PER (0x42002C1BU) /**< \brief (TC3) COUNT8 Period */ -#define REG_TC3_COUNT8_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ -#define REG_TC3_COUNT8_CC1 (0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ -#define REG_TC3_COUNT8_PERBUF (0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */ -#define REG_TC3_COUNT8_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT8_CCBUF1 (0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC3_CTRLA (*(RwReg *)0x42002C00U) /**< \brief (TC3) Control A */ -#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */ -#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06U) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BU) /**< \brief (TC3) Status */ -#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */ -#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FU) /**< \brief (TC3) Debug Control */ -#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10U) /**< \brief (TC3) Synchronization Status */ -#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14U) /**< \brief (TC3) COUNT16 Count */ -#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ -#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ -#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14U) /**< \brief (TC3) COUNT32 Count */ -#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ -#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ -#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Count */ -#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BU) /**< \brief (TC3) COUNT8 Period */ -#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ -#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ -#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */ -#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC3 peripheral ========== */ -#define TC3_CC_NUM 2 -#define TC3_DMAC_ID_MC_0 32 -#define TC3_DMAC_ID_MC_1 33 -#define TC3_DMAC_ID_MC_LSB 32 -#define TC3_DMAC_ID_MC_MSB 33 -#define TC3_DMAC_ID_MC_SIZE 2 -#define TC3_DMAC_ID_OVF 31 // Indexes of DMA Overflow trigger -#define TC3_EXT 0 -#define TC3_GCLK_ID 28 -#define TC3_MASTER 0 -#define TC3_OW_NUM 2 - -#endif /* _SAML21_TC3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc4.h deleted file mode 100644 index f811d2fa763..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc4.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC4 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TC4_INSTANCE_ -#define _SAML21_TC4_INSTANCE_ - -/* ========== Register definition for TC4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC4_CTRLA (0x43000800U) /**< \brief (TC4) Control A */ -#define REG_TC4_CTRLBCLR (0x43000804U) /**< \brief (TC4) Control B Clear */ -#define REG_TC4_CTRLBSET (0x43000805U) /**< \brief (TC4) Control B Set */ -#define REG_TC4_EVCTRL (0x43000806U) /**< \brief (TC4) Event Control */ -#define REG_TC4_INTENCLR (0x43000808U) /**< \brief (TC4) Interrupt Enable Clear */ -#define REG_TC4_INTENSET (0x43000809U) /**< \brief (TC4) Interrupt Enable Set */ -#define REG_TC4_INTFLAG (0x4300080AU) /**< \brief (TC4) Interrupt Flag Status and Clear */ -#define REG_TC4_STATUS (0x4300080BU) /**< \brief (TC4) Status */ -#define REG_TC4_WAVE (0x4300080CU) /**< \brief (TC4) Waveform Generation Control */ -#define REG_TC4_DRVCTRL (0x4300080DU) /**< \brief (TC4) Control C */ -#define REG_TC4_DBGCTRL (0x4300080FU) /**< \brief (TC4) Debug Control */ -#define REG_TC4_SYNCBUSY (0x43000810U) /**< \brief (TC4) Synchronization Status */ -#define REG_TC4_COUNT16_COUNT (0x43000814U) /**< \brief (TC4) COUNT16 Count */ -#define REG_TC4_COUNT16_CC0 (0x4300081CU) /**< \brief (TC4) COUNT16 Compare and Capture 0 */ -#define REG_TC4_COUNT16_CC1 (0x4300081EU) /**< \brief (TC4) COUNT16 Compare and Capture 1 */ -#define REG_TC4_COUNT16_CCBUF0 (0x43000830U) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC4_COUNT16_CCBUF1 (0x43000832U) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC4_COUNT32_COUNT (0x43000814U) /**< \brief (TC4) COUNT32 Count */ -#define REG_TC4_COUNT32_CC0 (0x4300081CU) /**< \brief (TC4) COUNT32 Compare and Capture 0 */ -#define REG_TC4_COUNT32_CC1 (0x43000820U) /**< \brief (TC4) COUNT32 Compare and Capture 1 */ -#define REG_TC4_COUNT32_CCBUF0 (0x43000830U) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC4_COUNT32_CCBUF1 (0x43000834U) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC4_COUNT8_COUNT (0x43000814U) /**< \brief (TC4) COUNT8 Count */ -#define REG_TC4_COUNT8_PER (0x4300081BU) /**< \brief (TC4) COUNT8 Period */ -#define REG_TC4_COUNT8_CC0 (0x4300081CU) /**< \brief (TC4) COUNT8 Compare and Capture 0 */ -#define REG_TC4_COUNT8_CC1 (0x4300081DU) /**< \brief (TC4) COUNT8 Compare and Capture 1 */ -#define REG_TC4_COUNT8_PERBUF (0x4300082FU) /**< \brief (TC4) COUNT8 Period Buffer */ -#define REG_TC4_COUNT8_CCBUF0 (0x43000830U) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC4_COUNT8_CCBUF1 (0x43000831U) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC4_CTRLA (*(RwReg *)0x43000800U) /**< \brief (TC4) Control A */ -#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x43000804U) /**< \brief (TC4) Control B Clear */ -#define REG_TC4_CTRLBSET (*(RwReg8 *)0x43000805U) /**< \brief (TC4) Control B Set */ -#define REG_TC4_EVCTRL (*(RwReg16*)0x43000806U) /**< \brief (TC4) Event Control */ -#define REG_TC4_INTENCLR (*(RwReg8 *)0x43000808U) /**< \brief (TC4) Interrupt Enable Clear */ -#define REG_TC4_INTENSET (*(RwReg8 *)0x43000809U) /**< \brief (TC4) Interrupt Enable Set */ -#define REG_TC4_INTFLAG (*(RwReg8 *)0x4300080AU) /**< \brief (TC4) Interrupt Flag Status and Clear */ -#define REG_TC4_STATUS (*(RwReg8 *)0x4300080BU) /**< \brief (TC4) Status */ -#define REG_TC4_WAVE (*(RwReg8 *)0x4300080CU) /**< \brief (TC4) Waveform Generation Control */ -#define REG_TC4_DRVCTRL (*(RwReg8 *)0x4300080DU) /**< \brief (TC4) Control C */ -#define REG_TC4_DBGCTRL (*(RwReg8 *)0x4300080FU) /**< \brief (TC4) Debug Control */ -#define REG_TC4_SYNCBUSY (*(RoReg *)0x43000810U) /**< \brief (TC4) Synchronization Status */ -#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x43000814U) /**< \brief (TC4) COUNT16 Count */ -#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x4300081CU) /**< \brief (TC4) COUNT16 Compare and Capture 0 */ -#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4300081EU) /**< \brief (TC4) COUNT16 Compare and Capture 1 */ -#define REG_TC4_COUNT16_CCBUF0 (*(RwReg16*)0x43000830U) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC4_COUNT16_CCBUF1 (*(RwReg16*)0x43000832U) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x43000814U) /**< \brief (TC4) COUNT32 Count */ -#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x4300081CU) /**< \brief (TC4) COUNT32 Compare and Capture 0 */ -#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x43000820U) /**< \brief (TC4) COUNT32 Compare and Capture 1 */ -#define REG_TC4_COUNT32_CCBUF0 (*(RwReg *)0x43000830U) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC4_COUNT32_CCBUF1 (*(RwReg *)0x43000834U) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x43000814U) /**< \brief (TC4) COUNT8 Count */ -#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x4300081BU) /**< \brief (TC4) COUNT8 Period */ -#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x4300081CU) /**< \brief (TC4) COUNT8 Compare and Capture 0 */ -#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x4300081DU) /**< \brief (TC4) COUNT8 Compare and Capture 1 */ -#define REG_TC4_COUNT8_PERBUF (*(RwReg8 *)0x4300082FU) /**< \brief (TC4) COUNT8 Period Buffer */ -#define REG_TC4_COUNT8_CCBUF0 (*(RwReg8 *)0x43000830U) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC4_COUNT8_CCBUF1 (*(RwReg8 *)0x43000831U) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC4 peripheral ========== */ -#define TC4_CC_NUM 2 -#define TC4_DMAC_ID_MC_0 35 -#define TC4_DMAC_ID_MC_1 36 -#define TC4_DMAC_ID_MC_LSB 35 -#define TC4_DMAC_ID_MC_MSB 36 -#define TC4_DMAC_ID_MC_SIZE 2 -#define TC4_DMAC_ID_OVF 34 // Indexes of DMA Overflow trigger -#define TC4_EXT 0 -#define TC4_GCLK_ID 29 -#define TC4_MASTER 0 -#define TC4_OW_NUM 2 - -#endif /* _SAML21_TC4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc0.h deleted file mode 100644 index 6846434f648..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc0.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC0 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TCC0_INSTANCE_ -#define _SAML21_TCC0_INSTANCE_ - -/* ========== Register definition for TCC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC0_CTRLA (0x42001400U) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (0x42001404U) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (0x42001405U) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (0x42001408U) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (0x4200140CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (0x42001410U) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (0x42001414U) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (0x42001418U) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (0x4200141EU) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (0x42001420U) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (0x42001424U) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (0x42001428U) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (0x4200142CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (0x42001430U) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (0x42001434U) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (0x42001438U) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (0x4200143CU) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (0x42001440U) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (0x42001444U) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (0x42001448U) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (0x4200144CU) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (0x42001450U) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTBUF (0x42001464U) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_WAVEBUF (0x42001468U) /**< \brief (TCC0) Waveform Control Buffer */ -#define REG_TCC0_PERBUF (0x4200146CU) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCBUF0 (0x42001470U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCBUF1 (0x42001474U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCBUF2 (0x42001478U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCBUF3 (0x4200147CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#else -#define REG_TCC0_CTRLA (*(RwReg *)0x42001400U) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001404U) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001405U) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001408U) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (*(RwReg *)0x4200140CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (*(RwReg *)0x42001410U) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001414U) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001418U) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200141EU) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (*(RwReg *)0x42001420U) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (*(RwReg *)0x42001424U) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (*(RwReg *)0x42001428U) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (*(RwReg *)0x4200142CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (*(RwReg *)0x42001430U) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (*(RwReg *)0x42001434U) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (*(RwReg16*)0x42001438U) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (*(RwReg *)0x4200143CU) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (*(RwReg *)0x42001440U) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (*(RwReg *)0x42001444U) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (*(RwReg *)0x42001448U) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (*(RwReg *)0x4200144CU) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (*(RwReg *)0x42001450U) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTBUF (*(RwReg16*)0x42001464U) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_WAVEBUF (*(RwReg *)0x42001468U) /**< \brief (TCC0) Waveform Control Buffer */ -#define REG_TCC0_PERBUF (*(RwReg *)0x4200146CU) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCBUF0 (*(RwReg *)0x42001470U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCBUF1 (*(RwReg *)0x42001474U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCBUF2 (*(RwReg *)0x42001478U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCBUF3 (*(RwReg *)0x4200147CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC0 peripheral ========== */ -#define TCC0_CC_NUM 4 // Number of Compare/Capture units -#define TCC0_DITHERING 1 // Dithering feature implemented -#define TCC0_DMAC_ID_MC_0 12 -#define TCC0_DMAC_ID_MC_1 13 -#define TCC0_DMAC_ID_MC_2 14 -#define TCC0_DMAC_ID_MC_3 15 -#define TCC0_DMAC_ID_MC_LSB 12 -#define TCC0_DMAC_ID_MC_MSB 15 -#define TCC0_DMAC_ID_MC_SIZE 4 -#define TCC0_DMAC_ID_OVF 11 // DMA overflow/underflow/retrigger trigger -#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented -#define TCC0_EXT 31 // Coding of implemented extended features -#define TCC0_GCLK_ID 25 // Index of Generic Clock -#define TCC0_OTMX 1 // Output Matrix feature implemented -#define TCC0_OW_NUM 8 // Number of Output Waveforms -#define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 -#define TCC0_SWAP 1 // DTI outputs swap feature implemented -#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAML21_TCC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc1.h deleted file mode 100644 index 9507b3a5cd5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc1.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC1 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TCC1_INSTANCE_ -#define _SAML21_TCC1_INSTANCE_ - -/* ========== Register definition for TCC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC1_CTRLA (0x42001800U) /**< \brief (TCC1) Control A */ -#define REG_TCC1_CTRLBCLR (0x42001804U) /**< \brief (TCC1) Control B Clear */ -#define REG_TCC1_CTRLBSET (0x42001805U) /**< \brief (TCC1) Control B Set */ -#define REG_TCC1_SYNCBUSY (0x42001808U) /**< \brief (TCC1) Synchronization Busy */ -#define REG_TCC1_FCTRLA (0x4200180CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ -#define REG_TCC1_FCTRLB (0x42001810U) /**< \brief (TCC1) Recoverable Fault B Configuration */ -#define REG_TCC1_DRVCTRL (0x42001818U) /**< \brief (TCC1) Driver Control */ -#define REG_TCC1_DBGCTRL (0x4200181EU) /**< \brief (TCC1) Debug Control */ -#define REG_TCC1_EVCTRL (0x42001820U) /**< \brief (TCC1) Event Control */ -#define REG_TCC1_INTENCLR (0x42001824U) /**< \brief (TCC1) Interrupt Enable Clear */ -#define REG_TCC1_INTENSET (0x42001828U) /**< \brief (TCC1) Interrupt Enable Set */ -#define REG_TCC1_INTFLAG (0x4200182CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ -#define REG_TCC1_STATUS (0x42001830U) /**< \brief (TCC1) Status */ -#define REG_TCC1_COUNT (0x42001834U) /**< \brief (TCC1) Count */ -#define REG_TCC1_PATT (0x42001838U) /**< \brief (TCC1) Pattern */ -#define REG_TCC1_WAVE (0x4200183CU) /**< \brief (TCC1) Waveform Control */ -#define REG_TCC1_PER (0x42001840U) /**< \brief (TCC1) Period */ -#define REG_TCC1_CC0 (0x42001844U) /**< \brief (TCC1) Compare and Capture 0 */ -#define REG_TCC1_CC1 (0x42001848U) /**< \brief (TCC1) Compare and Capture 1 */ -#define REG_TCC1_PATTBUF (0x42001864U) /**< \brief (TCC1) Pattern Buffer */ -#define REG_TCC1_WAVEBUF (0x42001868U) /**< \brief (TCC1) Waveform Control Buffer */ -#define REG_TCC1_PERBUF (0x4200186CU) /**< \brief (TCC1) Period Buffer */ -#define REG_TCC1_CCBUF0 (0x42001870U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ -#define REG_TCC1_CCBUF1 (0x42001874U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ -#else -#define REG_TCC1_CTRLA (*(RwReg *)0x42001800U) /**< \brief (TCC1) Control A */ -#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42001804U) /**< \brief (TCC1) Control B Clear */ -#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42001805U) /**< \brief (TCC1) Control B Set */ -#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42001808U) /**< \brief (TCC1) Synchronization Busy */ -#define REG_TCC1_FCTRLA (*(RwReg *)0x4200180CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ -#define REG_TCC1_FCTRLB (*(RwReg *)0x42001810U) /**< \brief (TCC1) Recoverable Fault B Configuration */ -#define REG_TCC1_DRVCTRL (*(RwReg *)0x42001818U) /**< \brief (TCC1) Driver Control */ -#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200181EU) /**< \brief (TCC1) Debug Control */ -#define REG_TCC1_EVCTRL (*(RwReg *)0x42001820U) /**< \brief (TCC1) Event Control */ -#define REG_TCC1_INTENCLR (*(RwReg *)0x42001824U) /**< \brief (TCC1) Interrupt Enable Clear */ -#define REG_TCC1_INTENSET (*(RwReg *)0x42001828U) /**< \brief (TCC1) Interrupt Enable Set */ -#define REG_TCC1_INTFLAG (*(RwReg *)0x4200182CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ -#define REG_TCC1_STATUS (*(RwReg *)0x42001830U) /**< \brief (TCC1) Status */ -#define REG_TCC1_COUNT (*(RwReg *)0x42001834U) /**< \brief (TCC1) Count */ -#define REG_TCC1_PATT (*(RwReg16*)0x42001838U) /**< \brief (TCC1) Pattern */ -#define REG_TCC1_WAVE (*(RwReg *)0x4200183CU) /**< \brief (TCC1) Waveform Control */ -#define REG_TCC1_PER (*(RwReg *)0x42001840U) /**< \brief (TCC1) Period */ -#define REG_TCC1_CC0 (*(RwReg *)0x42001844U) /**< \brief (TCC1) Compare and Capture 0 */ -#define REG_TCC1_CC1 (*(RwReg *)0x42001848U) /**< \brief (TCC1) Compare and Capture 1 */ -#define REG_TCC1_PATTBUF (*(RwReg16*)0x42001864U) /**< \brief (TCC1) Pattern Buffer */ -#define REG_TCC1_WAVEBUF (*(RwReg *)0x42001868U) /**< \brief (TCC1) Waveform Control Buffer */ -#define REG_TCC1_PERBUF (*(RwReg *)0x4200186CU) /**< \brief (TCC1) Period Buffer */ -#define REG_TCC1_CCBUF0 (*(RwReg *)0x42001870U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ -#define REG_TCC1_CCBUF1 (*(RwReg *)0x42001874U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC1 peripheral ========== */ -#define TCC1_CC_NUM 2 // Number of Compare/Capture units -#define TCC1_DITHERING 1 // Dithering feature implemented -#define TCC1_DMAC_ID_MC_0 17 -#define TCC1_DMAC_ID_MC_1 18 -#define TCC1_DMAC_ID_MC_LSB 17 -#define TCC1_DMAC_ID_MC_MSB 18 -#define TCC1_DMAC_ID_MC_SIZE 2 -#define TCC1_DMAC_ID_OVF 16 // DMA overflow/underflow/retrigger trigger -#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented -#define TCC1_EXT 24 // Coding of implemented extended features -#define TCC1_GCLK_ID 25 // Index of Generic Clock -#define TCC1_OTMX 0 // Output Matrix feature implemented -#define TCC1_OW_NUM 4 // Number of Output Waveforms -#define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 -#define TCC1_SWAP 0 // DTI outputs swap feature implemented -#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAML21_TCC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc2.h deleted file mode 100644 index a1af67f8790..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc2.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC2 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TCC2_INSTANCE_ -#define _SAML21_TCC2_INSTANCE_ - -/* ========== Register definition for TCC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC2_CTRLA (0x42001C00U) /**< \brief (TCC2) Control A */ -#define REG_TCC2_CTRLBCLR (0x42001C04U) /**< \brief (TCC2) Control B Clear */ -#define REG_TCC2_CTRLBSET (0x42001C05U) /**< \brief (TCC2) Control B Set */ -#define REG_TCC2_SYNCBUSY (0x42001C08U) /**< \brief (TCC2) Synchronization Busy */ -#define REG_TCC2_FCTRLA (0x42001C0CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ -#define REG_TCC2_FCTRLB (0x42001C10U) /**< \brief (TCC2) Recoverable Fault B Configuration */ -#define REG_TCC2_DRVCTRL (0x42001C18U) /**< \brief (TCC2) Driver Control */ -#define REG_TCC2_DBGCTRL (0x42001C1EU) /**< \brief (TCC2) Debug Control */ -#define REG_TCC2_EVCTRL (0x42001C20U) /**< \brief (TCC2) Event Control */ -#define REG_TCC2_INTENCLR (0x42001C24U) /**< \brief (TCC2) Interrupt Enable Clear */ -#define REG_TCC2_INTENSET (0x42001C28U) /**< \brief (TCC2) Interrupt Enable Set */ -#define REG_TCC2_INTFLAG (0x42001C2CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ -#define REG_TCC2_STATUS (0x42001C30U) /**< \brief (TCC2) Status */ -#define REG_TCC2_COUNT (0x42001C34U) /**< \brief (TCC2) Count */ -#define REG_TCC2_WAVE (0x42001C3CU) /**< \brief (TCC2) Waveform Control */ -#define REG_TCC2_PER (0x42001C40U) /**< \brief (TCC2) Period */ -#define REG_TCC2_CC0 (0x42001C44U) /**< \brief (TCC2) Compare and Capture 0 */ -#define REG_TCC2_CC1 (0x42001C48U) /**< \brief (TCC2) Compare and Capture 1 */ -#define REG_TCC2_WAVEBUF (0x42001C68U) /**< \brief (TCC2) Waveform Control Buffer */ -#define REG_TCC2_PERBUF (0x42001C6CU) /**< \brief (TCC2) Period Buffer */ -#define REG_TCC2_CCBUF0 (0x42001C70U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ -#define REG_TCC2_CCBUF1 (0x42001C74U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ -#else -#define REG_TCC2_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (TCC2) Control A */ -#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42001C04U) /**< \brief (TCC2) Control B Clear */ -#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42001C05U) /**< \brief (TCC2) Control B Set */ -#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42001C08U) /**< \brief (TCC2) Synchronization Busy */ -#define REG_TCC2_FCTRLA (*(RwReg *)0x42001C0CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ -#define REG_TCC2_FCTRLB (*(RwReg *)0x42001C10U) /**< \brief (TCC2) Recoverable Fault B Configuration */ -#define REG_TCC2_DRVCTRL (*(RwReg *)0x42001C18U) /**< \brief (TCC2) Driver Control */ -#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42001C1EU) /**< \brief (TCC2) Debug Control */ -#define REG_TCC2_EVCTRL (*(RwReg *)0x42001C20U) /**< \brief (TCC2) Event Control */ -#define REG_TCC2_INTENCLR (*(RwReg *)0x42001C24U) /**< \brief (TCC2) Interrupt Enable Clear */ -#define REG_TCC2_INTENSET (*(RwReg *)0x42001C28U) /**< \brief (TCC2) Interrupt Enable Set */ -#define REG_TCC2_INTFLAG (*(RwReg *)0x42001C2CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ -#define REG_TCC2_STATUS (*(RwReg *)0x42001C30U) /**< \brief (TCC2) Status */ -#define REG_TCC2_COUNT (*(RwReg *)0x42001C34U) /**< \brief (TCC2) Count */ -#define REG_TCC2_WAVE (*(RwReg *)0x42001C3CU) /**< \brief (TCC2) Waveform Control */ -#define REG_TCC2_PER (*(RwReg *)0x42001C40U) /**< \brief (TCC2) Period */ -#define REG_TCC2_CC0 (*(RwReg *)0x42001C44U) /**< \brief (TCC2) Compare and Capture 0 */ -#define REG_TCC2_CC1 (*(RwReg *)0x42001C48U) /**< \brief (TCC2) Compare and Capture 1 */ -#define REG_TCC2_WAVEBUF (*(RwReg *)0x42001C68U) /**< \brief (TCC2) Waveform Control Buffer */ -#define REG_TCC2_PERBUF (*(RwReg *)0x42001C6CU) /**< \brief (TCC2) Period Buffer */ -#define REG_TCC2_CCBUF0 (*(RwReg *)0x42001C70U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ -#define REG_TCC2_CCBUF1 (*(RwReg *)0x42001C74U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC2 peripheral ========== */ -#define TCC2_CC_NUM 2 // Number of Compare/Capture units -#define TCC2_DITHERING 0 // Dithering feature implemented -#define TCC2_DMAC_ID_MC_0 20 -#define TCC2_DMAC_ID_MC_1 21 -#define TCC2_DMAC_ID_MC_LSB 20 -#define TCC2_DMAC_ID_MC_MSB 21 -#define TCC2_DMAC_ID_MC_SIZE 2 -#define TCC2_DMAC_ID_OVF 19 // DMA overflow/underflow/retrigger trigger -#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented -#define TCC2_EXT 0 // Coding of implemented extended features -#define TCC2_GCLK_ID 26 // Index of Generic Clock -#define TCC2_OTMX 0 // Output Matrix feature implemented -#define TCC2_OW_NUM 2 // Number of Output Waveforms -#define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 -#define TCC2_SWAP 0 // DTI outputs swap feature implemented -#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAML21_TCC2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_trng.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_trng.h deleted file mode 100644 index b6793ad1a23..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_trng.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * \file - * - * \brief Instance description for TRNG - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_TRNG_INSTANCE_ -#define _SAML21_TRNG_INSTANCE_ - -/* ========== Register definition for TRNG peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TRNG_CTRLA (0x42003800U) /**< \brief (TRNG) Control A */ -#define REG_TRNG_EVCTRL (0x42003804U) /**< \brief (TRNG) Event Control */ -#define REG_TRNG_INTENCLR (0x42003808U) /**< \brief (TRNG) Interrupt Enable Clear */ -#define REG_TRNG_INTENSET (0x42003809U) /**< \brief (TRNG) Interrupt Enable Set */ -#define REG_TRNG_INTFLAG (0x4200380AU) /**< \brief (TRNG) Interrupt Flag Status and Clear */ -#define REG_TRNG_DATA (0x42003820U) /**< \brief (TRNG) Output Data */ -#else -#define REG_TRNG_CTRLA (*(RwReg8 *)0x42003800U) /**< \brief (TRNG) Control A */ -#define REG_TRNG_EVCTRL (*(RwReg8 *)0x42003804U) /**< \brief (TRNG) Event Control */ -#define REG_TRNG_INTENCLR (*(RwReg8 *)0x42003808U) /**< \brief (TRNG) Interrupt Enable Clear */ -#define REG_TRNG_INTENSET (*(RwReg8 *)0x42003809U) /**< \brief (TRNG) Interrupt Enable Set */ -#define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200380AU) /**< \brief (TRNG) Interrupt Flag Status and Clear */ -#define REG_TRNG_DATA (*(RoReg *)0x42003820U) /**< \brief (TRNG) Output Data */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML21_TRNG_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_usb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_usb.h deleted file mode 100644 index 6ab18bccb6b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_usb.h +++ /dev/null @@ -1,345 +0,0 @@ -/** - * \file - * - * \brief Instance description for USB - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_USB_INSTANCE_ -#define _SAML21_USB_INSTANCE_ - -/* ========== Register definition for USB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USB_CTRLA (0x41000000U) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (0x41000002U) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_FSMSTATUS (0x4100000DU) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (0x41000024U) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (0x41000028U) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (0x41000008U) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (0x4100000AU) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (0x4100000CU) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (0x41000010U) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (0x41000014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (0x41000018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (0x4100001CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (0x41000020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#define REG_USB_HOST_CTRLB (0x41000008U) /**< \brief (USB) HOST Control B */ -#define REG_USB_HOST_HSOFC (0x4100000AU) /**< \brief (USB) HOST Host Start Of Frame Control */ -#define REG_USB_HOST_STATUS (0x4100000CU) /**< \brief (USB) HOST Status */ -#define REG_USB_HOST_FNUM (0x41000010U) /**< \brief (USB) HOST Host Frame Number */ -#define REG_USB_HOST_FLENHIGH (0x41000012U) /**< \brief (USB) HOST Host Frame Length */ -#define REG_USB_HOST_INTENCLR (0x41000014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ -#define REG_USB_HOST_INTENSET (0x41000018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ -#define REG_USB_HOST_INTFLAG (0x4100001CU) /**< \brief (USB) HOST Host Interrupt Flag */ -#define REG_USB_HOST_PINTSMRY (0x41000020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ -#define REG_USB_HOST_PIPE_PCFG0 (0x41000100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ -#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41000103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41000104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ -#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41000105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ -#define REG_USB_HOST_PIPE_PSTATUS0 (0x41000106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ -#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41000107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ -#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41000108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ -#define REG_USB_HOST_PIPE_PINTENSET0 (0x41000109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ -#define REG_USB_HOST_PIPE_PCFG1 (0x41000120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ -#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41000123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41000124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ -#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41000125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ -#define REG_USB_HOST_PIPE_PSTATUS1 (0x41000126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ -#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41000127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ -#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41000128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ -#define REG_USB_HOST_PIPE_PINTENSET1 (0x41000129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ -#define REG_USB_HOST_PIPE_PCFG2 (0x41000140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ -#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41000143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41000144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ -#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41000145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ -#define REG_USB_HOST_PIPE_PSTATUS2 (0x41000146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ -#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41000147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ -#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41000148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ -#define REG_USB_HOST_PIPE_PINTENSET2 (0x41000149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ -#define REG_USB_HOST_PIPE_PCFG3 (0x41000160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ -#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41000163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41000164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ -#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41000165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ -#define REG_USB_HOST_PIPE_PSTATUS3 (0x41000166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ -#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41000167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ -#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41000168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ -#define REG_USB_HOST_PIPE_PINTENSET3 (0x41000169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ -#define REG_USB_HOST_PIPE_PCFG4 (0x41000180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ -#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41000183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41000184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ -#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41000185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ -#define REG_USB_HOST_PIPE_PSTATUS4 (0x41000186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ -#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41000187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ -#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41000188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ -#define REG_USB_HOST_PIPE_PINTENSET4 (0x41000189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ -#define REG_USB_HOST_PIPE_PCFG5 (0x410001A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ -#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410001A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410001A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ -#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410001A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ -#define REG_USB_HOST_PIPE_PSTATUS5 (0x410001A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ -#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410001A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ -#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410001A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ -#define REG_USB_HOST_PIPE_PINTENSET5 (0x410001A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ -#define REG_USB_HOST_PIPE_PCFG6 (0x410001C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ -#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410001C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410001C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ -#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410001C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ -#define REG_USB_HOST_PIPE_PSTATUS6 (0x410001C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ -#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410001C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ -#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410001C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ -#define REG_USB_HOST_PIPE_PINTENSET6 (0x410001C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ -#define REG_USB_HOST_PIPE_PCFG7 (0x410001E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ -#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410001E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410001E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ -#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410001E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ -#define REG_USB_HOST_PIPE_PSTATUS7 (0x410001E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ -#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410001E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ -#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410001E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ -#define REG_USB_HOST_PIPE_PINTENSET7 (0x410001E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ -#else -#define REG_USB_CTRLA (*(RwReg8 *)0x41000000U) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002U) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DU) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (*(RwReg *)0x41000024U) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (*(RwReg16*)0x41000028U) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008U) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AU) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CU) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010U) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41000008U) /**< \brief (USB) HOST Control B */ -#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100000AU) /**< \brief (USB) HOST Host Start Of Frame Control */ -#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100000CU) /**< \brief (USB) HOST Status */ -#define REG_USB_HOST_FNUM (*(RwReg16*)0x41000010U) /**< \brief (USB) HOST Host Frame Number */ -#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41000012U) /**< \brief (USB) HOST Host Frame Length */ -#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41000014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ -#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41000018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ -#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100001CU) /**< \brief (USB) HOST Host Interrupt Flag */ -#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41000020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ -#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41000100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ -#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41000103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41000104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ -#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41000105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ -#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41000106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ -#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41000107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ -#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41000108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ -#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41000109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ -#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41000120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ -#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41000123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41000124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ -#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41000125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ -#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41000126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ -#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41000127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ -#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41000128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ -#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41000129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ -#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41000140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ -#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41000143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41000144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ -#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41000145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ -#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41000146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ -#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41000147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ -#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41000148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ -#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41000149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ -#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41000160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ -#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41000163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41000164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ -#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41000165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ -#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41000166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ -#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41000167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ -#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41000168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ -#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41000169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ -#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41000180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ -#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41000183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41000184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ -#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41000185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ -#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41000186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ -#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41000187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ -#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41000188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ -#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41000189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ -#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410001A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ -#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410001A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410001A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ -#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410001A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ -#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410001A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ -#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410001A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ -#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410001A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ -#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410001A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ -#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410001C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ -#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410001C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410001C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ -#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410001C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ -#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410001C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ -#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410001C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ -#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410001C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ -#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410001C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ -#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410001E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ -#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410001E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410001E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ -#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410001E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ -#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410001E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ -#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410001E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ -#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410001E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ -#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410001E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for USB peripheral ========== */ -#define USB_EPT_NBR 8 // Number of USB end points (obsolete) -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 4 // Index of Generic Clock -#define USB_PIPE_NUM 8 // Number of USB pipes - -#endif /* _SAML21_USB_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_wdt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_wdt.h deleted file mode 100644 index faf3b75ea9b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_wdt.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_WDT_INSTANCE_ -#define _SAML21_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRLA (0x40001C00U) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40001C01U) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40001C02U) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40001C04U) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40001C05U) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40001C06U) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (0x40001C08U) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (0x40001C0CU) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRLA (*(RwReg8 *)0x40001C00U) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40001C01U) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001C02U) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001C04U) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40001C05U) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001C06U) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (*(RoReg *)0x40001C08U) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x40001C0CU) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML21_WDT_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e15a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e15a.h deleted file mode 100644 index ac918a04c5f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e15a.h +++ /dev/null @@ -1,757 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21E15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21E15A_PIO_ -#define _SAML21E15A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) - -#endif /* _SAML21E15A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e16a.h deleted file mode 100644 index 0457c5ee966..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e16a.h +++ /dev/null @@ -1,757 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21E16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21E16A_PIO_ -#define _SAML21E16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) - -#endif /* _SAML21E16A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e17a.h deleted file mode 100644 index 1ed2a183cc8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e17a.h +++ /dev/null @@ -1,757 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21E17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21E17A_PIO_ -#define _SAML21E17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) - -#endif /* _SAML21E17A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g16a.h deleted file mode 100644 index d564312b220..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g16a.h +++ /dev/null @@ -1,1060 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21G16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21G16A_PIO_ -#define _SAML21G16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 7L -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (1ul << 2) -#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT 7L -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (1ul << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 4L -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (1ul << 8) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 4L -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (1ul << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC1_WO0 4L -#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) -#define PORT_PB10E_TC1_WO0 (1ul << 10) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 4L -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (1ul << 11) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ -#define MUX_PB08B_OPAMP_OANEG2 1L -#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) -#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ -#define MUX_PB09B_OPAMP_OAPOS1 1L -#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) -#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 8L -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (1ul << 22) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ -#define MUX_PB10I_CCL_IN5 8L -#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) -#define PORT_PB10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 8L -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (1ul << 8) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 8L -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (1ul << 2) -#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 8L -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (1ul << 23) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 8L -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (1ul << 11) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) -#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 8L -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (1ul << 9) - -#endif /* _SAML21G16A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g17a.h deleted file mode 100644 index a6e1db3050b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g17a.h +++ /dev/null @@ -1,1060 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21G17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21G17A_PIO_ -#define _SAML21G17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 7L -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (1ul << 2) -#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT 7L -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (1ul << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 4L -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (1ul << 8) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 4L -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (1ul << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC1_WO0 4L -#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) -#define PORT_PB10E_TC1_WO0 (1ul << 10) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 4L -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (1ul << 11) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ -#define MUX_PB08B_OPAMP_OANEG2 1L -#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) -#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ -#define MUX_PB09B_OPAMP_OAPOS1 1L -#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) -#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 8L -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (1ul << 22) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ -#define MUX_PB10I_CCL_IN5 8L -#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) -#define PORT_PB10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 8L -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (1ul << 8) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 8L -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (1ul << 2) -#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 8L -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (1ul << 23) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 8L -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (1ul << 11) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) -#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 8L -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (1ul << 9) - -#endif /* _SAML21G17A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g18a.h deleted file mode 100644 index 444d98abb1f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g18a.h +++ /dev/null @@ -1,1060 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21G18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21G18A_PIO_ -#define _SAML21G18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 7L -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (1ul << 2) -#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT 7L -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (1ul << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 4L -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (1ul << 8) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 4L -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (1ul << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC1_WO0 4L -#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) -#define PORT_PB10E_TC1_WO0 (1ul << 10) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 4L -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (1ul << 11) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ -#define MUX_PB08B_OPAMP_OANEG2 1L -#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) -#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ -#define MUX_PB09B_OPAMP_OAPOS1 1L -#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) -#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 8L -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (1ul << 22) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ -#define MUX_PB10I_CCL_IN5 8L -#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) -#define PORT_PB10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 8L -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (1ul << 8) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 8L -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (1ul << 2) -#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 8L -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (1ul << 23) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 8L -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (1ul << 11) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) -#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 8L -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (1ul << 9) - -#endif /* _SAML21G18A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j16a.h deleted file mode 100644 index d3ca7de05d3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j16a.h +++ /dev/null @@ -1,1378 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21J16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21J16A_PIO_ -#define _SAML21J16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 7L -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (1ul << 1) -#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 7L -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (1ul << 2) -#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK 7L -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (1ul << 0) -#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT 7L -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (1ul << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 4L -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (1ul << 8) -#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 4L -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (1ul << 12) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 4L -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (1ul << 9) -#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 4L -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (1ul << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC1_WO0 4L -#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) -#define PORT_PB10E_TC1_WO0 (1ul << 10) -#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 4L -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (1ul << 14) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 4L -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (1ul << 11) -#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 4L -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (1ul << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 4L -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (1ul << 2) -#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 4L -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (1ul << 16) -#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 4L -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (1ul << 3) -#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 4L -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 4L -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (1ul << 20) -#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 4L -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (1ul << 0) -#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 4L -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (1ul << 22) -#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 4L -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (1ul << 21) -#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 4L -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (1ul << 1) -#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 4L -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (1ul << 23) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PB05B_OPAMP_OANEG1 37L /**< \brief OPAMP signal: OANEG1 on PB05 mux B */ -#define MUX_PB05B_OPAMP_OANEG1 1L -#define PINMUX_PB05B_OPAMP_OANEG1 ((PIN_PB05B_OPAMP_OANEG1 << 16) | MUX_PB05B_OPAMP_OANEG1) -#define PORT_PB05B_OPAMP_OANEG1 (1ul << 5) -#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ -#define MUX_PB08B_OPAMP_OANEG2 1L -#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) -#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PB06B_OPAMP_OAOUT1 38L /**< \brief OPAMP signal: OAOUT1 on PB06 mux B */ -#define MUX_PB06B_OPAMP_OAOUT1 1L -#define PINMUX_PB06B_OPAMP_OAOUT1 ((PIN_PB06B_OPAMP_OAOUT1 << 16) | MUX_PB06B_OPAMP_OAOUT1) -#define PORT_PB06B_OPAMP_OAOUT1 (1ul << 6) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ -#define MUX_PB09B_OPAMP_OAPOS1 1L -#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) -#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 8L -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (1ul << 22) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 8L -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (1ul << 0) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 8L -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (1ul << 1) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ -#define MUX_PB10I_CCL_IN5 8L -#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) -#define PORT_PB10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 8L -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (1ul << 6) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 8L -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (1ul << 7) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 8L -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (1ul << 8) -#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 8L -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (1ul << 14) -#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 8L -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (1ul << 15) -#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 8L -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (1ul << 16) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 8L -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (1ul << 2) -#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 8L -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (1ul << 23) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 8L -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (1ul << 11) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) -#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 8L -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (1ul << 9) -#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 8L -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (1ul << 17) - -#endif /* _SAML21J16A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j17a.h deleted file mode 100644 index 64ae420b02b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j17a.h +++ /dev/null @@ -1,1378 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21J17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21J17A_PIO_ -#define _SAML21J17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 7L -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (1ul << 1) -#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 7L -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (1ul << 2) -#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK 7L -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (1ul << 0) -#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT 7L -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (1ul << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 4L -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (1ul << 8) -#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 4L -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (1ul << 12) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 4L -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (1ul << 9) -#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 4L -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (1ul << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC1_WO0 4L -#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) -#define PORT_PB10E_TC1_WO0 (1ul << 10) -#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 4L -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (1ul << 14) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 4L -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (1ul << 11) -#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 4L -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (1ul << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 4L -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (1ul << 2) -#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 4L -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (1ul << 16) -#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 4L -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (1ul << 3) -#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 4L -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 4L -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (1ul << 20) -#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 4L -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (1ul << 0) -#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 4L -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (1ul << 22) -#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 4L -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (1ul << 21) -#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 4L -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (1ul << 1) -#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 4L -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (1ul << 23) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PB05B_OPAMP_OANEG1 37L /**< \brief OPAMP signal: OANEG1 on PB05 mux B */ -#define MUX_PB05B_OPAMP_OANEG1 1L -#define PINMUX_PB05B_OPAMP_OANEG1 ((PIN_PB05B_OPAMP_OANEG1 << 16) | MUX_PB05B_OPAMP_OANEG1) -#define PORT_PB05B_OPAMP_OANEG1 (1ul << 5) -#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ -#define MUX_PB08B_OPAMP_OANEG2 1L -#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) -#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PB06B_OPAMP_OAOUT1 38L /**< \brief OPAMP signal: OAOUT1 on PB06 mux B */ -#define MUX_PB06B_OPAMP_OAOUT1 1L -#define PINMUX_PB06B_OPAMP_OAOUT1 ((PIN_PB06B_OPAMP_OAOUT1 << 16) | MUX_PB06B_OPAMP_OAOUT1) -#define PORT_PB06B_OPAMP_OAOUT1 (1ul << 6) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ -#define MUX_PB09B_OPAMP_OAPOS1 1L -#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) -#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 8L -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (1ul << 22) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 8L -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (1ul << 0) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 8L -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (1ul << 1) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ -#define MUX_PB10I_CCL_IN5 8L -#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) -#define PORT_PB10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 8L -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (1ul << 6) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 8L -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (1ul << 7) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 8L -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (1ul << 8) -#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 8L -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (1ul << 14) -#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 8L -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (1ul << 15) -#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 8L -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (1ul << 16) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 8L -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (1ul << 2) -#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 8L -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (1ul << 23) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 8L -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (1ul << 11) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) -#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 8L -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (1ul << 9) -#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 8L -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (1ul << 17) - -#endif /* _SAML21J17A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j18a.h deleted file mode 100644 index 2464b89737d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j18a.h +++ /dev/null @@ -1,1378 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML21J18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21J18A_PIO_ -#define _SAML21J18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for RSTC peripheral ========== */ -#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ -#define MUX_PA00A_RSTC_EXTWAKE0 0L -#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) -#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) -#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ -#define MUX_PA01A_RSTC_EXTWAKE1 0L -#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) -#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) -#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ -#define MUX_PA02A_RSTC_EXTWAKE2 0L -#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) -#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) -#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ -#define MUX_PA03A_RSTC_EXTWAKE3 0L -#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) -#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) -#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ -#define MUX_PA04A_RSTC_EXTWAKE4 0L -#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) -#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) -#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ -#define MUX_PA05A_RSTC_EXTWAKE5 0L -#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) -#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) -#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ -#define MUX_PA06A_RSTC_EXTWAKE6 0L -#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) -#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) -#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ -#define MUX_PA07A_RSTC_EXTWAKE7 0L -#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) -#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 7L -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (1ul << 1) -#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 7L -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (1ul << 2) -#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK 7L -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (1ul << 0) -#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT 7L -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (1ul << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ -#define MUX_PA27G_TAL_BRK 6L -#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) -#define PORT_PA27G_TAL_BRK (1ul << 27) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 4L -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (1ul << 22) -#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 4L -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (1ul << 8) -#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 4L -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (1ul << 12) -#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 4L -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (1ul << 23) -#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 4L -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (1ul << 9) -#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 4L -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (1ul << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 4L -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (1ul << 24) -#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC1_WO0 4L -#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) -#define PORT_PB10E_TC1_WO0 (1ul << 10) -#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 4L -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (1ul << 14) -#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 4L -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (1ul << 25) -#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 4L -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (1ul << 11) -#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 4L -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (1ul << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 4L -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (1ul << 2) -#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 4L -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (1ul << 16) -#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 4L -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (1ul << 3) -#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 4L -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 4L -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (1ul << 20) -#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 4L -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (1ul << 0) -#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 4L -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (1ul << 22) -#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 4L -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (1ul << 21) -#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 4L -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (1ul << 1) -#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 4L -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (1ul << 23) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 1L -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (1ul << 2) -#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 1L -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (1ul << 5) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC4_WO0 4L -#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) -#define PORT_PA18E_TC4_WO0 (1ul << 18) -#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC4_WO0 4L -#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) -#define PORT_PA14E_TC4_WO0 (1ul << 14) -#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC4_WO1 4L -#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) -#define PORT_PA19E_TC4_WO1 (1ul << 19) -#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC4_WO1 4L -#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) -#define PORT_PA15E_TC4_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for OPAMP peripheral ========== */ -#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ -#define MUX_PA02B_OPAMP_OANEG0 1L -#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) -#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) -#define PIN_PB05B_OPAMP_OANEG1 37L /**< \brief OPAMP signal: OANEG1 on PB05 mux B */ -#define MUX_PB05B_OPAMP_OANEG1 1L -#define PINMUX_PB05B_OPAMP_OANEG1 ((PIN_PB05B_OPAMP_OANEG1 << 16) | MUX_PB05B_OPAMP_OANEG1) -#define PORT_PB05B_OPAMP_OANEG1 (1ul << 5) -#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ -#define MUX_PB08B_OPAMP_OANEG2 1L -#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) -#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) -#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ -#define MUX_PA07B_OPAMP_OAOUT0 1L -#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) -#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) -#define PIN_PB06B_OPAMP_OAOUT1 38L /**< \brief OPAMP signal: OAOUT1 on PB06 mux B */ -#define MUX_PB06B_OPAMP_OAOUT1 1L -#define PINMUX_PB06B_OPAMP_OAOUT1 ((PIN_PB06B_OPAMP_OAOUT1 << 16) | MUX_PB06B_OPAMP_OAOUT1) -#define PORT_PB06B_OPAMP_OAOUT1 (1ul << 6) -#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ -#define MUX_PA04B_OPAMP_OAOUT2 1L -#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) -#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) -#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ -#define MUX_PA06B_OPAMP_OAPOS0 1L -#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) -#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) -#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ -#define MUX_PB09B_OPAMP_OAPOS1 1L -#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) -#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) -#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ -#define MUX_PA05B_OPAMP_OAPOS2 1L -#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) -#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 8L -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (1ul << 4) -#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 8L -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (1ul << 16) -#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 8L -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (1ul << 22) -#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 8L -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (1ul << 5) -#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 8L -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (1ul << 17) -#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 8L -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (1ul << 0) -#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 8L -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (1ul << 6) -#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 8L -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (1ul << 18) -#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 8L -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (1ul << 1) -#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 8L -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (1ul << 8) -#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 8L -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (1ul << 30) -#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 8L -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (1ul << 9) -#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 8L -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (1ul << 10) -#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ -#define MUX_PB10I_CCL_IN5 8L -#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) -#define PORT_PB10I_CCL_IN5 (1ul << 10) -#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 8L -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (1ul << 22) -#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 8L -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (1ul << 6) -#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 8L -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (1ul << 23) -#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 8L -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (1ul << 7) -#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 8L -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (1ul << 24) -#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 8L -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (1ul << 8) -#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 8L -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (1ul << 14) -#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 8L -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (1ul << 15) -#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 8L -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (1ul << 16) -#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 8L -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (1ul << 7) -#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 8L -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (1ul << 19) -#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 8L -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (1ul << 2) -#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 8L -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (1ul << 23) -#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 8L -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (1ul << 11) -#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 8L -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (1ul << 31) -#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 8L -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (1ul << 11) -#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 8L -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (1ul << 25) -#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 8L -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (1ul << 9) -#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 8L -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (1ul << 17) - -#endif /* _SAML21J18A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21.h deleted file mode 100644 index 06b72f33642..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * \file - * - * \brief Top header file for SAML21 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21_ -#define _SAML21_ - -/** - * \defgroup SAML21_definitions SAML21 Device Definitions - * \brief SAML21 CMSIS Definitions. - */ - -#if defined(__SAML21E15A__) || defined(__ATSAML21E15A__) -#include "saml21e15a.h" -#elif defined(__SAML21E16A__) || defined(__ATSAML21E16A__) -#include "saml21e16a.h" -#elif defined(__SAML21E17A__) || defined(__ATSAML21E17A__) -#include "saml21e17a.h" -#elif defined(__SAML21G16A__) || defined(__ATSAML21G16A__) -#include "saml21g16a.h" -#elif defined(__SAML21G17A__) || defined(__ATSAML21G17A__) -#include "saml21g17a.h" -#elif defined(__SAML21G18A__) || defined(__ATSAML21G18A__) -#include "saml21g18a.h" -#elif defined(__SAML21J16A__) || defined(__ATSAML21J16A__) -#include "saml21j16a.h" -#elif defined(__SAML21J17A__) || defined(__ATSAML21J17A__) -#include "saml21j17a.h" -#elif defined(__SAML21J18A__) || defined(__ATSAML21J18A__) -#include "saml21j18a.h" -#else -#error Library does not support the specified device. -#endif - -#endif /* _SAML21_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e15a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e15a.h deleted file mode 100644 index 506a3a573ca..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e15a.h +++ /dev/null @@ -1,623 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21E15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21E15A_ -#define _SAML21E15A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21E15A_definitions SAML21E15A definitions - * This file defines all structures and symbols for SAML21E15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21E15A */ -/* ************************************************************************** */ -/** \defgroup SAML21E15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21E15A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21E15A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21E15A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21E15A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21E15A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21E15A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21E15A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21E15A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21E15A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21E15A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21E15A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21E15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21E15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21E15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21E15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21E15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21E15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21E15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21E15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21E15A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 14, /**< 14 SAML21E15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21E15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21E15A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21E15A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21E15A Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21E15A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21E15A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21E15A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21E15A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21E15A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21E15A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21E15A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21E15A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnReserved12; - void* pfnReserved13; - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E15A */ -/* ************************************************************************** */ -/** \defgroup SAML21E15A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21E15A */ -/* ************************************************************************** */ -/** \defgroup SAML21E15A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21E15A */ -/* ************************************************************************** */ -/** \defgroup SAML21E15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21E15A */ -/* ************************************************************************** */ -/** \defgroup SAML21E15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21E15A */ -/* ************************************************************************** */ -/** \defgroup SAML21E15A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21e15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21E15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x1000UL /* 4 kB */ -#define LPRAM_SIZE 0x800UL /* 2 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x1081000DUL -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 1 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21E15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21E15A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e16a.h deleted file mode 100644 index cedbfa696a6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e16a.h +++ /dev/null @@ -1,623 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21E16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21E16A_ -#define _SAML21E16A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21E16A_definitions SAML21E16A definitions - * This file defines all structures and symbols for SAML21E16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21E16A */ -/* ************************************************************************** */ -/** \defgroup SAML21E16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21E16A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21E16A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21E16A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21E16A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21E16A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21E16A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21E16A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21E16A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21E16A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21E16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 14, /**< 14 SAML21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21E16A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21E16A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21E16A Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21E16A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21E16A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21E16A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21E16A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21E16A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21E16A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21E16A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnReserved12; - void* pfnReserved13; - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E16A */ -/* ************************************************************************** */ -/** \defgroup SAML21E16A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21E16A */ -/* ************************************************************************** */ -/** \defgroup SAML21E16A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21E16A */ -/* ************************************************************************** */ -/** \defgroup SAML21E16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21E16A */ -/* ************************************************************************** */ -/** \defgroup SAML21E16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21E16A */ -/* ************************************************************************** */ -/** \defgroup SAML21E16A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21e16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21E16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x2000UL /* 8 kB */ -#define LPRAM_SIZE 0x1000UL /* 4 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x1081000CUL -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 1 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21E16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21E16A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e17a.h deleted file mode 100644 index 93464bb3252..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e17a.h +++ /dev/null @@ -1,623 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21E17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21E17A_ -#define _SAML21E17A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21E17A_definitions SAML21E17A definitions - * This file defines all structures and symbols for SAML21E17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21E17A */ -/* ************************************************************************** */ -/** \defgroup SAML21E17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21E17A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21E17A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21E17A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21E17A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21E17A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21E17A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21E17A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21E17A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21E17A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21E17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 14, /**< 14 SAML21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21E17A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21E17A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21E17A Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21E17A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21E17A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21E17A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21E17A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21E17A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21E17A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21E17A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnReserved12; - void* pfnReserved13; - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E17A */ -/* ************************************************************************** */ -/** \defgroup SAML21E17A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21E17A */ -/* ************************************************************************** */ -/** \defgroup SAML21E17A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21E17A */ -/* ************************************************************************** */ -/** \defgroup SAML21E17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21E17A */ -/* ************************************************************************** */ -/** \defgroup SAML21E17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21E17A */ -/* ************************************************************************** */ -/** \defgroup SAML21E17A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21e17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21E17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x4000UL /* 16 kB */ -#define LPRAM_SIZE 0x1800UL /* 6 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x1081000BUL -#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ -#define PORT_GROUPS 1 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21E17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21E17A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g16a.h deleted file mode 100644 index 1c9e7f826a5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g16a.h +++ /dev/null @@ -1,635 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21G16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21G16A_ -#define _SAML21G16A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21G16A_definitions SAML21G16A definitions - * This file defines all structures and symbols for SAML21G16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21G16A */ -/* ************************************************************************** */ -/** \defgroup SAML21G16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21G16A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21G16A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21G16A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21G16A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21G16A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21G16A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21G16A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21G16A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21G16A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21G16A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21G16A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21G16A Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21G16A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21G16A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21G16A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21G16A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21G16A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21G16A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21G16A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G16A */ -/* ************************************************************************** */ -/** \defgroup SAML21G16A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21G16A */ -/* ************************************************************************** */ -/** \defgroup SAML21G16A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21G16A */ -/* ************************************************************************** */ -/** \defgroup SAML21G16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21G16A */ -/* ************************************************************************** */ -/** \defgroup SAML21G16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21G16A */ -/* ************************************************************************** */ -/** \defgroup SAML21G16A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21g16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21G16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x2000UL /* 8 kB */ -#define LPRAM_SIZE 0x1000UL /* 4 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x10810007UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21G16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21G16A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g17a.h deleted file mode 100644 index 634c0d32bcd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g17a.h +++ /dev/null @@ -1,635 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21G17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21G17A_ -#define _SAML21G17A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21G17A_definitions SAML21G17A definitions - * This file defines all structures and symbols for SAML21G17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21G17A */ -/* ************************************************************************** */ -/** \defgroup SAML21G17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21G17A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21G17A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21G17A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21G17A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21G17A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21G17A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21G17A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21G17A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21G17A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21G17A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21G17A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21G17A Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21G17A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21G17A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21G17A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21G17A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21G17A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21G17A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21G17A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G17A */ -/* ************************************************************************** */ -/** \defgroup SAML21G17A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21G17A */ -/* ************************************************************************** */ -/** \defgroup SAML21G17A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21G17A */ -/* ************************************************************************** */ -/** \defgroup SAML21G17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21G17A */ -/* ************************************************************************** */ -/** \defgroup SAML21G17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21G17A */ -/* ************************************************************************** */ -/** \defgroup SAML21G17A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21g17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21G17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x4000UL /* 16 kB */ -#define LPRAM_SIZE 0x1800UL /* 6 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x10810006UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21G17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21G17A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g18a.h deleted file mode 100644 index 0b108ae74c1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g18a.h +++ /dev/null @@ -1,635 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21G18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21G18A_ -#define _SAML21G18A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21G18A_definitions SAML21G18A definitions - * This file defines all structures and symbols for SAML21G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21G18A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21G18A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21G18A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21G18A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21G18A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21G18A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21G18A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21G18A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21G18A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21G18A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21G18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21G18A Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21G18A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21G18A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21G18A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21G18A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21G18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21G18A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21G18A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x8000UL /* 32 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x10810005UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21G18A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j16a.h deleted file mode 100644 index e5ac8baa658..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j16a.h +++ /dev/null @@ -1,647 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21J16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21J16A_ -#define _SAML21J16A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21J16A_definitions SAML21J16A definitions - * This file defines all structures and symbols for SAML21J16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21J16A */ -/* ************************************************************************** */ -/** \defgroup SAML21J16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21J16A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21J16A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21J16A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21J16A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21J16A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21J16A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21J16A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21J16A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21J16A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21J16A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21J16A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21J16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21J16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21J16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21J16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21J16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21J16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21J16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21J16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21J16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21J16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21J16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21J16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21J16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21J16A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21J16A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21J16A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 19, /**< 19 SAML21J16A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 20, /**< 20 SAML21J16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 21, /**< 21 SAML21J16A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21J16A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21J16A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21J16A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21J16A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21J16A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21J16A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21J16A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J16A */ -/* ************************************************************************** */ -/** \defgroup SAML21J16A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21J16A */ -/* ************************************************************************** */ -/** \defgroup SAML21J16A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc2.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21J16A */ -/* ************************************************************************** */ -/** \defgroup SAML21J16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21J16A */ -/* ************************************************************************** */ -/** \defgroup SAML21J16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21J16A */ -/* ************************************************************************** */ -/** \defgroup SAML21J16A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21j16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21J16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x2000UL /* 8 kB */ -#define LPRAM_SIZE 0x1000UL /* 4 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x10810002UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21J16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21J16A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j17a.h deleted file mode 100644 index ea00c47a2fc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j17a.h +++ /dev/null @@ -1,647 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21J17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21J17A_ -#define _SAML21J17A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21J17A_definitions SAML21J17A definitions - * This file defines all structures and symbols for SAML21J17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21J17A */ -/* ************************************************************************** */ -/** \defgroup SAML21J17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21J17A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21J17A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21J17A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21J17A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21J17A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21J17A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21J17A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21J17A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21J17A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21J17A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21J17A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21J17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21J17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21J17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21J17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21J17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21J17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21J17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21J17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21J17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21J17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21J17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21J17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21J17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21J17A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21J17A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21J17A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 19, /**< 19 SAML21J17A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 20, /**< 20 SAML21J17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 21, /**< 21 SAML21J17A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21J17A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21J17A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21J17A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21J17A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21J17A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21J17A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21J17A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J17A */ -/* ************************************************************************** */ -/** \defgroup SAML21J17A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21J17A */ -/* ************************************************************************** */ -/** \defgroup SAML21J17A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc2.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21J17A */ -/* ************************************************************************** */ -/** \defgroup SAML21J17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21J17A */ -/* ************************************************************************** */ -/** \defgroup SAML21J17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21J17A */ -/* ************************************************************************** */ -/** \defgroup SAML21J17A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21j17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21J17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x4000UL /* 16 kB */ -#define LPRAM_SIZE 0x1800UL /* 6 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x10810001UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21J17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21J17A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j18a.h deleted file mode 100644 index 51bb0f554f0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j18a.h +++ /dev/null @@ -1,647 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML21J18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAML21J18A_ -#define _SAML21J18A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21J18A_definitions SAML21J18A definitions - * This file defines all structures and symbols for SAML21J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21J18A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21J18A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21J18A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21J18A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21J18A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21J18A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21J18A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21J18A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21J18A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21J18A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21J18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21J18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 19, /**< 19 SAML21J18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 20, /**< 20 SAML21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 21, /**< 21 SAML21J18A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21J18A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21J18A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21J18A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21J18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21J18A True Random Generator (TRNG) */ - PICOP_IRQn = 28, /**< 28 SAML21J18A PicoProcessor (PICOP) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnPICOP_Handler; /* 28 PicoProcessor */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void PICOP_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_aes.h" -#include "comp_ccl.h" -#include "comp_dac.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_mclk.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_opamp.h" -#include "comp_oscctrl.h" -#include "comp_osc32kctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_supc.h" -#include "comp_tal.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_trng.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_aes.h" -#include "ins_ccl.h" -#include "ins_dac.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_mclk.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_opamp.h" -#include "ins_oscctrl.h" -#include "ins_osc32kctrl.h" -#include "ins_pac.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rstc.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_supc.h" -#include "ins_tal.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_tc2.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_trng.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_port PORT Definitions */ -/*@{*/ - -#include "pio_saml21j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x8000UL /* 32 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ -#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ -#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ - -#define DSU_DID_RESETVALUE 0x10810000UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21J18A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.c deleted file mode 100644 index 74727a166f9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.c +++ /dev/null @@ -1,81 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "saml21.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (4000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.h deleted file mode 100644 index 65285ac3f44..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SYSTEM_SAML21_H_INCLUDED_ -#define _SYSTEM_SAML21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAML21_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h deleted file mode 100644 index 1973b025f65..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_AC_COMPONENT_ -#define _SAMR21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMR21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2205 -#define REV_AC 0x111 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ -#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos) -#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) -#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ -#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos) -#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ -#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ -#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ -#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ -#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos) -#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ -#define AC_STATUSC_RESETVALUE 0x00ul /**< \brief (AC_STATUSC reset_value) Status C */ - -#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ -#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) -#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ -#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) -#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ -#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos) -#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) -#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ -#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) -#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */ -#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */ -#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */ -#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_MASK 0x33ul /**< \brief (AC_STATUSC) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_MASK 0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_AC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h deleted file mode 100644 index 871f0bff690..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h +++ /dev/null @@ -1,699 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_ADC_COMPONENT_ -#define _SAMR21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMR21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2204 -#define REV_ADC 0x120 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ -#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ -#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ -#define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos) -#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ -#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) -#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ -#define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ - -#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ -#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) -#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */ -#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ -#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ -#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ -#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */ -#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ -#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos) -#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) -#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ -#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos) -#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) -#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ -#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) -#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */ -#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */ -#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */ -#define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */ -#define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */ -#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */ -#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ -#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ -#define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ -#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ -#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ -#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos) -#define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ -#define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos) -#define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ -#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ -#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ -#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ -#define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos) -#define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ -#define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos) -#define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ -#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos) -#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) -#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ -#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos) -#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) -#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_ADC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h deleted file mode 100644 index 8ddc41bb5d6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h +++ /dev/null @@ -1,1086 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_DMAC_COMPONENT_ -#define _SAMR21_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMR21_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2223 -#define REV_DMAC 0x100 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ -#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ -#define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ - -#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ -#define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) -#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ -#define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) -#define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ -#define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) -#define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ -#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */ - -#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ -#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos) -#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) -#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ -#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ -#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ - -#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ -#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) -#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ -#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ -#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ -#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos) -#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ -#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos) -#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ -#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) -#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ -#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ -#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ -#define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ -#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ -#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) -#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ -#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ -#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) -#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ -#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ -#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ -#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 */ -#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 */ -#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 */ -#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 */ -#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 */ -#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 */ -#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 */ -#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 */ -#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */ - -/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */ - -#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */ -#define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos) -#define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)) -#define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */ - -/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SRCADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */ - -#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */ -#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos) -#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)) -#define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */ - -/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_DSTADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */ - -#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */ -#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos) -#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)) -#define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */ - -/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_DESCADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */ - -#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */ -#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos) -#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)) -#define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */ - -/** \brief DMAC APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ - __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ - __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ - __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ - __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ - __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ - __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ - RoReg8 Reserved1[0x1]; - __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ - __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ - RoReg8 Reserved2[0x8]; - __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ - RoReg8 Reserved3[0x2]; - __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ - __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ - __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ - __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ - __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ - __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ - RoReg8 Reserved4[0x3]; - __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ - __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ - RoReg8 Reserved5[0x3]; - __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ - RoReg8 Reserved6[0x4]; - __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ - __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ - __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ - __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ -} Dmac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief DMAC Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ - __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ - __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ - __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ - __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ -} DmacDescriptor -#ifdef __GNUC__ -__attribute__ ((aligned (8))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_DMAC_DESCRIPTOR - -/*@}*/ - -#endif /* _SAMR21_DMAC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h deleted file mode 100644 index 6fc3b837148..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h +++ /dev/null @@ -1,551 +0,0 @@ -/** - * \file - * - * \brief Component description for DSU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_DSU_COMPONENT_ -#define _SAMR21_DSU_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DSU */ -/* ========================================================================== */ -/** \addtogroup SAMR21_DSU Device Service Unit */ -/*@{*/ - -#define DSU_U2209 -#define REV_DSU 0x200 - -/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ - uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ - uint8_t CE:1; /*!< bit: 4 Chip Erase */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ -#define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */ - -#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ -#define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos) -#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */ -#define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos) -#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */ -#define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos) -#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */ -#define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos) -#define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */ - -/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DONE:1; /*!< bit: 0 Done */ - uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ - uint8_t BERR:1; /*!< bit: 2 Bus Error */ - uint8_t FAIL:1; /*!< bit: 3 Failure */ - uint8_t PERR:1; /*!< bit: 4 Protection Error */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ -#define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */ - -#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ -#define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos) -#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ -#define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos) -#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ -#define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos) -#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ -#define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos) -#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ -#define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos) -#define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */ - -/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PROT:1; /*!< bit: 0 Protected */ - uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ - uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ - uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ - uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DSU_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ -#define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */ - -#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ -#define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos) -#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ -#define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos) -#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ -#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos) -#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ -#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos) -#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ -#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos) -#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) -#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ -#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos) -#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */ - -/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t ADDR:30; /*!< bit: 2..31 Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ -#define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */ - -#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ -#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos) -#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)) -#define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */ - -/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t LENGTH:30; /*!< bit: 2..31 Length */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_LENGTH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ -#define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */ - -#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ -#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos) -#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)) -#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */ - -/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ -#define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */ - -#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ -#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos) -#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)) -#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */ - -/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ -#define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ - -#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ -#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos) -#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)) -#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */ - -/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ - uint32_t REVISION:4; /*!< bit: 8..11 Revision */ - uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ - uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ - uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ - -#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ -#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos) -#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)) -#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */ -#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos) -#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)) -#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */ -#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos) -#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)) -#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */ -#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos) -#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)) -#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */ -#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos) -#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)) -#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ -#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos) -#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)) -#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */ - -/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EPRES:1; /*!< bit: 0 Entry Present */ - uint32_t FMT:1; /*!< bit: 1 Format */ - uint32_t :10; /*!< bit: 2..11 Reserved */ - uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_ENTRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */ -#define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */ - -#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */ -#define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos) -#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */ -#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos) -#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */ -#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos) -#define DSU_ENTRY_ADDOFF(value) (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)) -#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */ - -/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t END:32; /*!< bit: 0..31 End Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_END_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */ -#define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */ - -#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ -#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos) -#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos)) -#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */ - -/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_MEMTYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */ -#define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */ - -#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ -#define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos) -#define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */ - -/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ - uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID4_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ -#define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ - -#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ -#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos) -#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)) -#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */ -#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos) -#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)) -#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */ - -/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ -#define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ - -#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ -#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos) -#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)) -#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */ - -/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ - uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ -#define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ - -#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ -#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos) -#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)) -#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ -#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos) -#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)) -#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */ - -/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ - uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ - uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ -#define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ - -#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ -#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos) -#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)) -#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ -#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos) -#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ -#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos) -#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)) -#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */ - -/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ - uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_PID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ -#define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ - -#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ -#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos) -#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)) -#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ -#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos) -#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)) -#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */ - -/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ -#define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ - -#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ -#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos) -#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)) -#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */ - -/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ - uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ -#define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ - -#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ -#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos) -#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)) -#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ -#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos) -#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)) -#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */ - -/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ -#define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ - -#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ -#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos) -#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)) -#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */ - -/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_CID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ -#define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ - -#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ -#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos) -#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)) -#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */ - -/** \brief DSU hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ - __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ - __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ - RoReg8 Reserved1[0x1]; - __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ - __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ - __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ - __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ - __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ - RoReg8 Reserved2[0xFE4]; - __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ - __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ - RoReg8 Reserved3[0xFC0]; - __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ - __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ - RoReg8 Reserved4[0xC]; - __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ - __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ - __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ - __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ - __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ - __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ - __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ - __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ -} Dsu; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_DSU_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h deleted file mode 100644 index 1f7322d85a8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h +++ /dev/null @@ -1,681 +0,0 @@ -/** - * \file - * - * \brief Component description for EIC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_EIC_COMPONENT_ -#define _SAMR21_EIC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR EIC */ -/* ========================================================================== */ -/** \addtogroup SAMR21_EIC External Interrupt Controller */ -/*@{*/ - -#define EIC_U2217 -#define REV_EIC 0x101 - -/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */ -#define EIC_CTRL_RESETVALUE 0x00ul /**< \brief (EIC_CTRL reset_value) Control */ - -#define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */ -#define EIC_CTRL_SWRST (0x1ul << EIC_CTRL_SWRST_Pos) -#define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */ -#define EIC_CTRL_ENABLE (0x1ul << EIC_CTRL_ENABLE_Pos) -#define EIC_CTRL_MASK 0x03ul /**< \brief (EIC_CTRL) MASK Register */ - -/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */ -#define EIC_STATUS_RESETVALUE 0x00ul /**< \brief (EIC_STATUS reset_value) Status */ - -#define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */ -#define EIC_STATUS_SYNCBUSY (0x1ul << EIC_STATUS_SYNCBUSY_Pos) -#define EIC_STATUS_MASK 0x80ul /**< \brief (EIC_STATUS) MASK Register */ - -/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ - uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_NMICTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */ -#define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */ - -#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */ -#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)) -#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */ -#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */ -#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */ -#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both-edges detection */ -#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High-level detection */ -#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low-level detection */ -#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) -#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */ -#define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos) -#define EIC_NMICTRL_MASK 0x0Ful /**< \brief (EIC_NMICTRL) MASK Register */ - -/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EIC_NMIFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */ -#define EIC_NMIFLAG_RESETVALUE 0x00ul /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */ - -#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */ -#define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos) -#define EIC_NMIFLAG_MASK 0x01ul /**< \brief (EIC_NMIFLAG) MASK Register */ - -/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ - uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ - uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ - uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ - uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ - uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ - uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ - uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ - uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ - uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ - uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ - uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ - uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ - uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ - uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ - uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */ -#define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */ - -#define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos) -#define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos) -#define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos) -#define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos) -#define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos) -#define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos) -#define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos) -#define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos) -#define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos) -#define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos) -#define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos) -#define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos) -#define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos) -#define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos) -#define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos) -#define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos) -#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */ -#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos) -#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)) -#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */ - -/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */ -#define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */ -#define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos) -#define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */ -#define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos) -#define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */ -#define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos) -#define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */ -#define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos) -#define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */ -#define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos) -#define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */ -#define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos) -#define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */ -#define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos) -#define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */ -#define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos) -#define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */ -#define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos) -#define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */ -#define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos) -#define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */ -#define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos) -#define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */ -#define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos) -#define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */ -#define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos) -#define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */ -#define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos) -#define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */ -#define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos) -#define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */ -#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos) -#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */ -#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos) -#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)) -#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */ - -/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */ -#define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */ - -#define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */ -#define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos) -#define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */ -#define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos) -#define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */ -#define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos) -#define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */ -#define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos) -#define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */ -#define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos) -#define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */ -#define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos) -#define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */ -#define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos) -#define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */ -#define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos) -#define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */ -#define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos) -#define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */ -#define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos) -#define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */ -#define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos) -#define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */ -#define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos) -#define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */ -#define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos) -#define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */ -#define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos) -#define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */ -#define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos) -#define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */ -#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos) -#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */ -#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos) -#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)) -#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */ - -/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ - __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ - __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ - __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ - __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ - __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ - __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ - __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ - __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ - __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ - __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ - __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ - __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ - __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ - __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ - __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ - __I uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ - __I uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */ -#define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos) -#define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */ -#define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos) -#define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */ -#define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos) -#define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */ -#define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos) -#define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */ -#define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos) -#define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */ -#define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos) -#define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */ -#define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos) -#define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */ -#define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos) -#define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */ -#define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos) -#define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */ -#define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos) -#define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */ -#define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos) -#define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */ -#define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos) -#define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */ -#define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos) -#define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */ -#define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos) -#define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */ -#define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos) -#define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */ -#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos) -#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */ -#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos) -#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)) -#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */ - -/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ - uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ - uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ - uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ - uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ - uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ - uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ - uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ - uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ - uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ - uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ - uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ - uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ - uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ - uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ - uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_WAKEUP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */ -#define EIC_WAKEUP_RESETVALUE 0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */ - -#define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos) -#define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos) -#define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos) -#define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos) -#define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos) -#define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos) -#define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos) -#define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos) -#define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos) -#define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos) -#define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos) -#define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos) -#define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos) -#define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos) -#define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos) -#define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos) -#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */ -#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos) -#define EIC_WAKEUP_WAKEUPEN(value) (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)) -#define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */ - -/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ - uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ - uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ - uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ - uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ - uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ - uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ - uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ - uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ - uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ - uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ - uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ - uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ - uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ - uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ - uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EIC_CONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */ -#define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */ - -#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */ -#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)) -#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */ -#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */ -#define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both-edges detection */ -#define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High-level detection */ -#define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low-level detection */ -#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) -#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */ -#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos) -#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */ -#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)) -#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) -#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */ -#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos) -#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */ -#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)) -#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) -#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */ -#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos) -#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */ -#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)) -#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) -#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */ -#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos) -#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */ -#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)) -#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) -#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */ -#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos) -#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */ -#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)) -#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) -#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */ -#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos) -#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */ -#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)) -#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) -#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */ -#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos) -#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */ -#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)) -#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ -#define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ -#define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ -#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) -#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */ -#define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos) -#define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */ - -/** \brief EIC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ - __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ - __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ - __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ - __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ - __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ - __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ - __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ - __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ -} Eic; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_EIC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h deleted file mode 100644 index 32d12f23168..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h +++ /dev/null @@ -1,604 +0,0 @@ -/** - * \file - * - * \brief Component description for EVSYS - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_EVSYS_COMPONENT_ -#define _SAMR21_EVSYS_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR EVSYS */ -/* ========================================================================== */ -/** \addtogroup SAMR21_EVSYS Event System Interface */ -/*@{*/ - -#define EVSYS_U2208 -#define REV_EVSYS 0x101 - -/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :3; /*!< bit: 1.. 3 Reserved */ - uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} EVSYS_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */ -#define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */ - -#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */ -#define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos) -#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */ -#define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos) -#define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */ - -/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SWEVT:1; /*!< bit: 8 Software Event */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ - uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_CHANNEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */ -#define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */ - -#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */ -#define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos) -#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)) -#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */ -#define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos) -#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */ -#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos) -#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)) -#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */ -#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)) -#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */ -#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */ -#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */ -#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) -#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */ -#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)) -#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */ -#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) -#define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */ - -/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} EVSYS_USER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */ -#define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */ - -#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */ -#define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos) -#define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)) -#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */ -#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos) -#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)) -#define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */ -#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos) -#define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */ - -/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ - uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ - uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ - uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ - uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ - uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ - uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ - uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ - uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ - uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ - uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ - uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ - uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ - uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ - uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ - uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ - uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ - uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ - uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ - uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ - uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ - uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ - uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ - uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ - uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */ -#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */ - -#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */ -#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos) -#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */ -#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos) -#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */ -#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos) -#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */ -#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos) -#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */ -#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos) -#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */ -#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos) -#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */ -#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos) -#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */ -#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos) -#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */ -#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos) -#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)) -#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */ -#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos) -#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */ -#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos) -#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */ -#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos) -#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */ -#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos) -#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */ -#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos) -#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */ -#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos) -#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */ -#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos) -#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */ -#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos) -#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */ -#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos) -#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)) -#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */ -#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos) -#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */ -#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos) -#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */ -#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos) -#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */ -#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos) -#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */ -#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos) -#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)) -#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */ -#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos) -#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */ -#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos) -#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */ -#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos) -#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */ -#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos) -#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */ -#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos) -#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)) -#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */ - -/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */ -#define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */ - -#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos) -#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos) -#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos) -#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos) -#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos) -#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos) -#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos) -#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos) -#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos) -#define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)) -#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos) -#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos) -#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos) -#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos) -#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos) -#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos) -#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos) -#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos) -#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos) -#define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)) -#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos) -#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos) -#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos) -#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos) -#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */ -#define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos) -#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)) -#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos) -#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos) -#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos) -#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos) -#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */ -#define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos) -#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)) -#define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */ - -/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */ -#define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */ - -#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos) -#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos) -#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos) -#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos) -#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos) -#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos) -#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos) -#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos) -#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos) -#define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)) -#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos) -#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos) -#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos) -#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos) -#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos) -#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos) -#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos) -#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos) -#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos) -#define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)) -#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos) -#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos) -#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos) -#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos) -#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */ -#define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos) -#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)) -#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos) -#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos) -#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos) -#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos) -#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */ -#define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos) -#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)) -#define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */ - -/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ - __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ - __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ - __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ - __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ - __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ - __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ - __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ - __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ - __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ - __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ - __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ - __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ - __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ - __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ - __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ - __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ - __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ - __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ - __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ - __I uint32_t :4; /*!< bit: 20..23 Reserved */ - __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ - __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ - __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ - __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ - __I uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ - __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ - __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ - __I uint32_t :4; /*!< bit: 20..23 Reserved */ - __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ - __I uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} EVSYS_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */ -#define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */ -#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos) -#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */ -#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos) -#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */ -#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos) -#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */ -#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos) -#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */ -#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos) -#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */ -#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos) -#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */ -#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos) -#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */ -#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos) -#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */ -#define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos) -#define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)) -#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */ -#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos) -#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */ -#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos) -#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */ -#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos) -#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */ -#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos) -#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */ -#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos) -#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */ -#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos) -#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */ -#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos) -#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */ -#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos) -#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */ -#define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos) -#define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)) -#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */ -#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos) -#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */ -#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos) -#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */ -#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos) -#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */ -#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos) -#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */ -#define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos) -#define EVSYS_INTFLAG_OVRp8(value) (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)) -#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */ -#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos) -#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */ -#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos) -#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */ -#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos) -#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */ -#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos) -#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */ -#define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos) -#define EVSYS_INTFLAG_EVDp8(value) (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)) -#define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */ - -/** \brief EVSYS hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ - __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ - RoReg8 Reserved2[0x2]; - __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ - __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ - __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ - __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ -} Evsys; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_EVSYS_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h deleted file mode 100644 index 86e97913db9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h +++ /dev/null @@ -1,310 +0,0 @@ -/** - * \file - * - * \brief Component description for GCLK - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_GCLK_COMPONENT_ -#define _SAMR21_GCLK_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR GCLK */ -/* ========================================================================== */ -/** \addtogroup SAMR21_GCLK Generic Clock Generator */ -/*@{*/ - -#define GCLK_U2102 -#define REV_GCLK 0x210 - -/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} GCLK_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */ -#define GCLK_CTRL_RESETVALUE 0x00ul /**< \brief (GCLK_CTRL reset_value) Control */ - -#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */ -#define GCLK_CTRL_SWRST (0x1ul << GCLK_CTRL_SWRST_Pos) -#define GCLK_CTRL_MASK 0x01ul /**< \brief (GCLK_CTRL) MASK Register */ - -/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} GCLK_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */ -#define GCLK_STATUS_RESETVALUE 0x00ul /**< \brief (GCLK_STATUS reset_value) Status */ - -#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */ -#define GCLK_STATUS_SYNCBUSY (0x1ul << GCLK_STATUS_SYNCBUSY_Pos) -#define GCLK_STATUS_MASK 0x80ul /**< \brief (GCLK_STATUS) MASK Register */ - -/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ - uint16_t :2; /*!< bit: 12..13 Reserved */ - uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ - uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} GCLK_CLKCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */ -#define GCLK_CLKCTRL_RESETVALUE 0x0000ul /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */ - -#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */ -#define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID(value) (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)) -#define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */ -#define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */ -#define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */ -#define GCLK_CLKCTRL_ID_WDT_Val 0x3ul /**< \brief (GCLK_CLKCTRL) WDT */ -#define GCLK_CLKCTRL_ID_RTC_Val 0x4ul /**< \brief (GCLK_CLKCTRL) RTC */ -#define GCLK_CLKCTRL_ID_EIC_Val 0x5ul /**< \brief (GCLK_CLKCTRL) EIC */ -#define GCLK_CLKCTRL_ID_USB_Val 0x6ul /**< \brief (GCLK_CLKCTRL) USB */ -#define GCLK_CLKCTRL_ID_EVSYS_0_Val 0x7ul /**< \brief (GCLK_CLKCTRL) EVSYS_0 */ -#define GCLK_CLKCTRL_ID_EVSYS_1_Val 0x8ul /**< \brief (GCLK_CLKCTRL) EVSYS_1 */ -#define GCLK_CLKCTRL_ID_EVSYS_2_Val 0x9ul /**< \brief (GCLK_CLKCTRL) EVSYS_2 */ -#define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */ -#define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */ -#define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */ -#define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */ -#define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */ -#define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */ -#define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */ -#define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */ -#define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */ -#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */ -#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */ -#define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */ -#define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */ -#define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */ -#define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */ -#define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */ -#define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */ -#define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */ -#define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */ -#define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */ -#define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */ -#define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */ -#define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */ -#define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos) -#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */ -#define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN(value) (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)) -#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */ -#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */ -#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */ -#define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */ -#define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */ -#define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */ -#define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */ -#define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */ -#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos) -#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */ -#define GCLK_CLKCTRL_CLKEN (0x1ul << GCLK_CLKCTRL_CLKEN_Pos) -#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */ -#define GCLK_CLKCTRL_WRTLOCK (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos) -#define GCLK_CLKCTRL_MASK 0xCF3Ful /**< \brief (GCLK_CLKCTRL) MASK Register */ - -/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SRC:5; /*!< bit: 8..12 Source Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ - uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ - uint32_t OOV:1; /*!< bit: 18 Output Off Value */ - uint32_t OE:1; /*!< bit: 19 Output Enable */ - uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ - uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} GCLK_GENCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */ -#define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */ - -#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */ -#define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos) -#define GCLK_GENCTRL_ID(value) (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)) -#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */ -#define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)) -#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */ -#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */ -#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */ -#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */ -#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */ -#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */ -#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */ -#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */ -#define GCLK_GENCTRL_SRC_FDPLL_Val 0x8ul /**< \brief (GCLK_GENCTRL) FDPLL output */ -#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos) -#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */ -#define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos) -#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */ -#define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos) -#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */ -#define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos) -#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */ -#define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos) -#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */ -#define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos) -#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */ -#define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos) -#define GCLK_GENCTRL_MASK 0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */ - -/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} GCLK_GENDIV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */ -#define GCLK_GENDIV_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */ - -#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */ -#define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos) -#define GCLK_GENDIV_ID(value) (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)) -#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */ -#define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos) -#define GCLK_GENDIV_DIV(value) (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)) -#define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */ - -/** \brief GCLK hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ - __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ - __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ - __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ -} Gclk; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_GCLK_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h deleted file mode 100644 index 465c605b7cf..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * \file - * - * \brief Component description for HMATRIXB - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_HMATRIXB_COMPONENT_ -#define _SAMR21_HMATRIXB_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR HMATRIXB */ -/* ========================================================================== */ -/** \addtogroup SAMR21_HMATRIXB HSB Matrix */ -/*@{*/ - -#define HMATRIXB_I7638 -#define REV_HMATRIXB 0x212 - -/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} HMATRIXB_PRAS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */ -#define HMATRIXB_PRAS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */ - -#define HMATRIXB_PRAS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */ - -/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} HMATRIXB_PRBS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */ -#define HMATRIXB_PRBS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */ - -#define HMATRIXB_PRBS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */ - -/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} HMATRIXB_SFR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */ -#define HMATRIXB_SFR_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */ - -#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */ -#define HMATRIXB_SFR_SFR_Msk (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos) -#define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos)) -#define HMATRIXB_SFR_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */ - -/** \brief HmatrixbPrs hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ - __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ -} HmatrixbPrs; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief HMATRIXB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - RoReg8 Reserved1[0x80]; - HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ - RoReg8 Reserved2[0x10]; - __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ -} Hmatrixb; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_HMATRIXB_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h deleted file mode 100644 index b180c85346e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h +++ /dev/null @@ -1,396 +0,0 @@ -/** - * \file - * - * \brief Component description for MTB - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_MTB_COMPONENT_ -#define _SAMR21_MTB_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR MTB */ -/* ========================================================================== */ -/** \addtogroup SAMR21_MTB Cortex-M0+ Micro-Trace Buffer */ -/*@{*/ - -#define MTB_U2002 -#define REV_MTB 0x100 - -/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ - uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_POSITION_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */ - -#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */ -#define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos) -#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */ -#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos) -#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)) -#define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */ - -/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ - uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ - uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ - uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ - uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ - uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ - uint32_t :21; /*!< bit: 10..30 Reserved */ - uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_MASTER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */ -#define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */ - -#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */ -#define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos) -#define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)) -#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */ -#define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos) -#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */ -#define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos) -#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */ -#define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos) -#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */ -#define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos) -#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */ -#define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos) -#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */ -#define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos) -#define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */ - -/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ - uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} MTB_FLOW_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */ -#define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */ - -#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */ -#define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos) -#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */ -#define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos) -#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */ -#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos) -#define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)) -#define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */ - -/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_BASE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */ -#define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */ - -/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_ITCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */ -#define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */ - -/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CLAIMSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */ -#define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */ - -/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CLAIMCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */ -#define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */ - -/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_LOCKACCESS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */ -#define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */ - -/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_LOCKSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */ -#define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */ - -/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_AUTHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */ -#define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */ - -/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVARCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */ -#define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */ - -/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */ -#define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */ - -/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_DEVTYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */ -#define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */ - -/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID4_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */ -#define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */ - -/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID5_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */ -#define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */ - -/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID6_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */ -#define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */ - -/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID7_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */ -#define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */ - -/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */ -#define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */ - -/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */ -#define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */ - -/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */ -#define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */ - -/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_PID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */ -#define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */ - -/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */ -#define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */ - -/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */ -#define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */ - -/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */ -#define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */ - -/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} MTB_CID3_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */ -#define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */ - -/** \brief MTB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ - __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ - __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ - __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ - RoReg8 Reserved1[0xEF0]; - __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ - RoReg8 Reserved2[0x9C]; - __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ - __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ - RoReg8 Reserved3[0x8]; - __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ - __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ - __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ - __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ - RoReg8 Reserved4[0x8]; - __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ - __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ - __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ - __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ - __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ - __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ - __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ - __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ - __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ - __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ - __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ - __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ - __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ - __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ -} Mtb; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_MTB_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h deleted file mode 100644 index e014da1069d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h +++ /dev/null @@ -1,535 +0,0 @@ -/** - * \file - * - * \brief Component description for NVMCTRL - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_NVMCTRL_COMPONENT_ -#define _SAMR21_NVMCTRL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR NVMCTRL */ -/* ========================================================================== */ -/** \addtogroup SAMR21_NVMCTRL Non-Volatile Memory Controller */ -/*@{*/ - -#define NVMCTRL_U2207 -#define REV_NVMCTRL 0x106 - -/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CMD:7; /*!< bit: 0.. 6 Command */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ -#define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ - -#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */ -#define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)) -#define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ -#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ -#define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */ -#define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */ -#define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ -#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */ -#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */ -#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */ -#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */ -#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */ -#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos) -#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */ -#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos) -#define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)) -#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */ -#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos) -#define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */ - -/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t MANW:1; /*!< bit: 7 Manual Write */ - uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ - uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ -#define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ - -#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */ -#define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)) -#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */ -#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos) -#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */ -#define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */ -#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)) -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */ -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */ -#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */ -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) -#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */ -#define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)) -#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */ -#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */ -#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */ -#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos) -#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */ -#define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos) -#define NVMCTRL_CTRLB_MASK 0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */ - -/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ - uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_PARAM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ -#define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ - -#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ -#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos) -#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)) -#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ -#define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)) -#define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */ -#define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */ -#define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */ -#define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */ -#define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */ -#define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */ -#define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */ -#define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */ -#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) -#define NVMCTRL_PARAM_MASK 0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */ - -/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ -#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ - -#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */ -#define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos) -#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */ -#define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos) -#define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */ - -/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ -#define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ - -#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */ -#define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos) -#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */ -#define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos) -#define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */ - -/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t READY:1; /*!< bit: 0 NVM Ready */ - __I uint8_t ERROR:1; /*!< bit: 1 Error */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} NVMCTRL_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ -#define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */ -#define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos) -#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */ -#define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos) -#define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */ - -/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ - uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ - uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ - uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ - uint16_t NVME:1; /*!< bit: 4 NVM Error */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t SB:1; /*!< bit: 8 Security Bit Status */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */ -#define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */ - -#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ -#define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos) -#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ -#define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos) -#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */ -#define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos) -#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */ -#define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos) -#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */ -#define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos) -#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */ -#define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos) -#define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */ - -/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} NVMCTRL_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */ -#define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */ - -#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ -#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos) -#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)) -#define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */ - -/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} NVMCTRL_LOCK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */ - -#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */ -#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos) -#define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)) -#define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */ - -/** \brief NVMCTRL APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - RoReg8 Reserved1[0x2]; - __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ - __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ - __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - RoReg8 Reserved2[0x3]; - __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ - RoReg8 Reserved3[0x3]; - __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x3]; - __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ - RoReg8 Reserved5[0x2]; - __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ - __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ -} Nvmctrl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_NVMCTRL_CAL -#define SECTION_NVMCTRL_LOCKBIT -#define SECTION_NVMCTRL_OTP1 -#define SECTION_NVMCTRL_OTP2 -#define SECTION_NVMCTRL_OTP4 -#define SECTION_NVMCTRL_TEMP_LOG -#define SECTION_NVMCTRL_USER - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ -/* ************************************************************************** */ -/** \addtogroup fuses_api Peripheral Software API */ -/*@{*/ - - -#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4) -#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */ -#define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos) -#define ADC_FUSES_BIASCAL(value) (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)) - -#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4 -#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */ -#define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos) -#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)) - -#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4) -#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */ -#define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos) -#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)) - -#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER -#define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */ -#define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos) -#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)) - -#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER -#define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */ -#define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos) -#define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)) - -#define FUSES_BOD33_EN_ADDR NVMCTRL_USER -#define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */ -#define FUSES_BOD33_EN_Msk (0x1ul << FUSES_BOD33_EN_Pos) - -#define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4) -#define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ -#define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos) - -#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4) -#define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */ -#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos) -#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos)) - -#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8) -#define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */ -#define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos) -#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos)) - -#define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */ -#define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos) -#define FUSES_HOT_ADC_VAL(value) (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos)) - -#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ -#define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos) -#define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos)) - -#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG -#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ -#define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos) -#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos)) - -#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG -#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ -#define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos) -#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos)) - -#define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4) -#define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */ -#define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos) -#define FUSES_OSC32K_CAL(value) (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos)) - -#define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) -#define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */ -#define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos) -#define FUSES_ROOM_ADC_VAL(value) (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos)) - -#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ -#define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos) -#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos)) - -#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ -#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos) -#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos)) - -#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG -#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ -#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos) -#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos)) - -#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER -#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */ -#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos) -#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)) - -#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER -#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */ -#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos) -#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)) - -#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */ -#define NVMCTRL_FUSES_NVMP_Msk (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos) -#define NVMCTRL_FUSES_NVMP(value) (NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)) - -#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */ -#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos) -#define NVMCTRL_FUSES_NVM_LOCK(value) (NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)) - -#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1 -#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */ -#define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos) -#define NVMCTRL_FUSES_PSZ(value) (NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)) - -#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4) -#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */ -#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos) -#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)) - -#define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4) -#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */ -#define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos) -#define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)) - -#define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4) -#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */ -#define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos) -#define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)) - -#define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4) -#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */ -#define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos) -#define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)) - -#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER -#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */ -#define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos) - -#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER -#define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */ -#define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos) - -#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ -#define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos) -#define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)) - -#define WDT_FUSES_PER_ADDR NVMCTRL_USER -#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */ -#define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos) -#define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)) - -#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ -#define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos) - -#define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER -#define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */ -#define WDT_FUSES_WINDOW_0_Msk (0x1ul << WDT_FUSES_WINDOW_0_Pos) - -#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4) -#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */ -#define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos) -#define WDT_FUSES_WINDOW_1(value) (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)) - -/*@}*/ - -#endif /* _SAMR21_NVMCTRL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h deleted file mode 100644 index 9a4bc89e6d6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - * \file - * - * \brief Component description for PAC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_PAC_COMPONENT_ -#define _SAMR21_PAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PAC */ -/* ========================================================================== */ -/** \addtogroup SAMR21_PAC Peripheral Access Controller */ -/*@{*/ - -#define PAC_U2211 -#define REV_PAC 0x101 - -/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_WPCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */ -#define PAC_WPCLR_RESETVALUE 0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */ - -#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */ -#define PAC_WPCLR_WP_Msk (0x7FFFFFFFul << PAC_WPCLR_WP_Pos) -#define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)) -#define PAC_WPCLR_MASK 0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */ - -/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PAC_WPSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */ -#define PAC_WPSET_RESETVALUE 0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */ - -#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */ -#define PAC_WPSET_WP_Msk (0x7FFFFFFFul << PAC_WPSET_WP_Pos) -#define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)) -#define PAC_WPSET_MASK 0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */ - -/** \brief PAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ - __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ -} Pac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_PAC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h deleted file mode 100644 index 4832dc43a4d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h +++ /dev/null @@ -1,527 +0,0 @@ -/** - * \file - * - * \brief Component description for PM - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_PM_COMPONENT_ -#define _SAMR21_PM_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PM */ -/* ========================================================================== */ -/** \addtogroup SAMR21_PM Power Manager */ -/*@{*/ - -#define PM_U2206 -#define REV_PM 0x201 - -/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint8_t reg; /*!< Type used for register access */ -} PM_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */ -#define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */ - -#define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */ - -/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_SLEEP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */ -#define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */ - -#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */ -#define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos) -#define PM_SLEEP_IDLE(value) (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)) -#define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */ -#define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */ -#define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */ -#define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos) -#define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos) -#define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos) -#define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */ - -/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_CPUSEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */ -#define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */ - -#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */ -#define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV(value) (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)) -#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */ -#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */ -#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */ -#define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */ -#define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */ -#define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */ -#define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */ -#define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */ -#define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos) -#define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */ - -/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_APBASEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */ -#define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */ - -#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */ -#define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV(value) (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)) -#define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */ -#define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */ -#define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */ -#define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */ -#define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */ -#define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */ -#define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */ -#define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */ -#define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos) -#define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */ - -/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_APBBSEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */ -#define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */ - -#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */ -#define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV(value) (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)) -#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */ -#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */ -#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */ -#define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */ -#define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */ -#define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */ -#define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */ -#define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */ -#define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos) -#define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */ - -/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_APBCSEL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */ -#define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */ - -#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */ -#define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV(value) (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)) -#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */ -#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */ -#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */ -#define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */ -#define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */ -#define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */ -#define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */ -#define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */ -#define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos) -#define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */ - -/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ - uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ - uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ - uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ - uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ - uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ - uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PM_AHBMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */ -#define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */ - -#define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */ -#define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos) -#define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */ -#define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos) -#define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */ -#define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos) -#define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */ -#define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos) -#define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */ -#define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos) -#define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */ -#define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos) -#define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */ -#define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos) -#define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */ - -/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ - uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ - uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ - uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ - uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ - uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ - uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PM_APBAMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */ -#define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */ - -#define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */ -#define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos) -#define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */ -#define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos) -#define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */ -#define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos) -#define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */ -#define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos) -#define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */ -#define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos) -#define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */ -#define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos) -#define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */ -#define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos) -#define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */ - -/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ - uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ - uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ - uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ - uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ - uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ - uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PM_APBBMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */ -#define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */ - -#define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */ -#define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos) -#define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */ -#define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos) -#define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */ -#define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos) -#define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */ -#define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos) -#define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */ -#define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos) -#define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */ -#define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos) -#define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */ -#define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos) -#define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */ - -/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ - uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ - uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ - uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ - uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ - uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ - uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ - uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ - uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ - uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ - uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ - uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ - uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ - uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ - uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ - uint32_t :1; /*!< bit: 20 Reserved */ - uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PM_APBCMASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */ -#define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */ - -#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */ -#define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos) -#define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */ -#define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos) -#define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */ -#define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos) -#define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */ -#define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos) -#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */ -#define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos) -#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */ -#define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos) -#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */ -#define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos) -#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */ -#define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos) -#define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */ -#define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos) -#define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */ -#define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos) -#define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */ -#define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos) -#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */ -#define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos) -#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */ -#define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos) -#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */ -#define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos) -#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */ -#define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos) -#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */ -#define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos) -#define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */ -#define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos) -#define PM_APBCMASK_RFCTRL_Pos 21 /**< \brief (PM_APBCMASK) RFCTRL APB Clock Enable */ -#define PM_APBCMASK_RFCTRL (0x1ul << PM_APBCMASK_RFCTRL_Pos) -#define PM_APBCMASK_MASK 0x002B3FFFul /**< \brief (PM_APBCMASK) MASK Register */ - -/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */ -#define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */ - -#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */ -#define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos) -#define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */ - -/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */ -#define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */ - -#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */ -#define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos) -#define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */ - -/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ - __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */ -#define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */ -#define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos) -#define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */ - -/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t POR:1; /*!< bit: 0 Power On Reset */ - uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ - uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EXT:1; /*!< bit: 4 External Reset */ - uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ - uint8_t SYST:1; /*!< bit: 6 System Reset Request */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PM_RCAUSE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */ -#define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */ - -#define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */ -#define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos) -#define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */ -#define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos) -#define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */ -#define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos) -#define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */ -#define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos) -#define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */ -#define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos) -#define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */ -#define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos) -#define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */ - -/** \brief PM hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ - RoReg8 Reserved1[0x6]; - __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ - __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ - __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ - __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ - RoReg8 Reserved2[0x8]; - __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ - __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ - __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ - __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ - RoReg8 Reserved3[0x10]; - __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ - __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ - __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ -} Pm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_PM_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h deleted file mode 100644 index 344e41bc75f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h +++ /dev/null @@ -1,395 +0,0 @@ -/** - * \file - * - * \brief Component description for PORT - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_PORT_COMPONENT_ -#define _SAMR21_PORT_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR PORT */ -/* ========================================================================== */ -/** \addtogroup SAMR21_PORT Port Module */ -/*@{*/ - -#define PORT_U2210 -#define REV_PORT 0x100 - -/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_DIR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */ -#define PORT_DIR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */ - -#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */ -#define PORT_DIR_DIR_Msk (0xFFFFFFFFul << PORT_DIR_DIR_Pos) -#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)) -#define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */ - -/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */ -#define PORT_DIRCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */ - -#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */ -#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos) -#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)) -#define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */ - -/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */ -#define PORT_DIRSET_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */ - -#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */ -#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos) -#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)) -#define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */ - -/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_DIRTGL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */ -#define PORT_DIRTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */ - -#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */ -#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos) -#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)) -#define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */ - -/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_OUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */ -#define PORT_OUT_RESETVALUE 0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */ - -#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */ -#define PORT_OUT_OUT_Msk (0xFFFFFFFFul << PORT_OUT_OUT_Pos) -#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)) -#define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */ - -/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */ -#define PORT_OUTCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */ - -#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */ -#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos) -#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)) -#define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */ - -/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */ -#define PORT_OUTSET_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */ - -#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */ -#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos) -#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)) -#define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */ - -/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_OUTTGL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */ -#define PORT_OUTTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */ - -#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */ -#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos) -#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)) -#define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */ - -/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_IN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */ -#define PORT_IN_RESETVALUE 0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */ - -#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */ -#define PORT_IN_IN_Msk (0xFFFFFFFFul << PORT_IN_IN_Pos) -#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)) -#define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */ - -/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */ -#define PORT_CTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */ - -#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */ -#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos) -#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)) -#define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */ - -/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ - uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ - uint32_t INEN:1; /*!< bit: 17 Input Enable */ - uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ - uint32_t :3; /*!< bit: 19..21 Reserved */ - uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ - uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ - uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} PORT_WRCONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */ -#define PORT_WRCONFIG_RESETVALUE 0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */ - -#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */ -#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos) -#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)) -#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */ -#define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos) -#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */ -#define PORT_WRCONFIG_INEN (0x1ul << PORT_WRCONFIG_INEN_Pos) -#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */ -#define PORT_WRCONFIG_PULLEN (0x1ul << PORT_WRCONFIG_PULLEN_Pos) -#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */ -#define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos) -#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */ -#define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos) -#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)) -#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */ -#define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos) -#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */ -#define PORT_WRCONFIG_WRPINCFG (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos) -#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */ -#define PORT_WRCONFIG_HWSEL (0x1ul << PORT_WRCONFIG_HWSEL_Pos) -#define PORT_WRCONFIG_MASK 0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */ - -/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */ - uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PORT_PMUX_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */ -#define PORT_PMUX_RESETVALUE 0x00ul /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */ - -#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */ -#define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)) -#define PORT_PMUX_PMUXE_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */ -#define PORT_PMUX_PMUXE_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */ -#define PORT_PMUX_PMUXE_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */ -#define PORT_PMUX_PMUXE_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */ -#define PORT_PMUX_PMUXE_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */ -#define PORT_PMUX_PMUXE_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */ -#define PORT_PMUX_PMUXE_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */ -#define PORT_PMUX_PMUXE_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */ -#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos) -#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */ -#define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)) -#define PORT_PMUX_PMUXO_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */ -#define PORT_PMUX_PMUXO_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */ -#define PORT_PMUX_PMUXO_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */ -#define PORT_PMUX_PMUXO_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */ -#define PORT_PMUX_PMUXO_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */ -#define PORT_PMUX_PMUXO_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */ -#define PORT_PMUX_PMUXO_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */ -#define PORT_PMUX_PMUXO_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */ -#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos) -#define PORT_PMUX_MASK 0xFFul /**< \brief (PORT_PMUX) MASK Register */ - -/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ - uint8_t INEN:1; /*!< bit: 1 Input Enable */ - uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} PORT_PINCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */ -#define PORT_PINCFG_RESETVALUE 0x00ul /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */ - -#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */ -#define PORT_PINCFG_PMUXEN (0x1ul << PORT_PINCFG_PMUXEN_Pos) -#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */ -#define PORT_PINCFG_INEN (0x1ul << PORT_PINCFG_INEN_Pos) -#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */ -#define PORT_PINCFG_PULLEN (0x1ul << PORT_PINCFG_PULLEN_Pos) -#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */ -#define PORT_PINCFG_DRVSTR (0x1ul << PORT_PINCFG_DRVSTR_Pos) -#define PORT_PINCFG_MASK 0x47ul /**< \brief (PORT_PINCFG) MASK Register */ - -/** \brief PortGroup hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ - __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ - __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ - __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ - __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ - __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ - __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ - __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ - __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ - __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ - __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ - RoReg8 Reserved1[0x4]; - __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ - __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ - RoReg8 Reserved2[0x20]; -} PortGroup; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief PORT hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ -} Port; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_PORT_IOBUS - -/*@}*/ - -#endif /* _SAMR21_PORT_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h deleted file mode 100644 index d18226b3891..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - * \file - * - * \brief Component description for RFCTRL - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_RFCTRL_COMPONENT_ -#define _SAMR21_RFCTRL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR RFCTRL */ -/* ========================================================================== */ -/** \addtogroup SAMR21_RFCTRL RF233 control module */ -/*@{*/ - -#define RFCTRL_U2233 -#define REV_RFCTRL 0x100 - -/* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */ - uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */ - uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */ - uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */ - uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */ - uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RFCTRL_FECFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RFCTRL_FECFG_OFFSET 0x0 /**< \brief (RFCTRL_FECFG offset) Front-end control bus configuration */ -#define RFCTRL_FECFG_RESETVALUE 0x0000ul /**< \brief (RFCTRL_FECFG reset_value) Front-end control bus configuration */ - -#define RFCTRL_FECFG_F0CFG_Pos 0 /**< \brief (RFCTRL_FECFG) Front-end control signal 0 configuration */ -#define RFCTRL_FECFG_F0CFG_Msk (0x3ul << RFCTRL_FECFG_F0CFG_Pos) -#define RFCTRL_FECFG_F0CFG(value) (RFCTRL_FECFG_F0CFG_Msk & ((value) << RFCTRL_FECFG_F0CFG_Pos)) -#define RFCTRL_FECFG_F1CFG_Pos 2 /**< \brief (RFCTRL_FECFG) Front-end control signal 1 configuration */ -#define RFCTRL_FECFG_F1CFG_Msk (0x3ul << RFCTRL_FECFG_F1CFG_Pos) -#define RFCTRL_FECFG_F1CFG(value) (RFCTRL_FECFG_F1CFG_Msk & ((value) << RFCTRL_FECFG_F1CFG_Pos)) -#define RFCTRL_FECFG_F2CFG_Pos 4 /**< \brief (RFCTRL_FECFG) Front-end control signal 2 configuration */ -#define RFCTRL_FECFG_F2CFG_Msk (0x3ul << RFCTRL_FECFG_F2CFG_Pos) -#define RFCTRL_FECFG_F2CFG(value) (RFCTRL_FECFG_F2CFG_Msk & ((value) << RFCTRL_FECFG_F2CFG_Pos)) -#define RFCTRL_FECFG_F3CFG_Pos 6 /**< \brief (RFCTRL_FECFG) Front-end control signal 3 configuration */ -#define RFCTRL_FECFG_F3CFG_Msk (0x3ul << RFCTRL_FECFG_F3CFG_Pos) -#define RFCTRL_FECFG_F3CFG(value) (RFCTRL_FECFG_F3CFG_Msk & ((value) << RFCTRL_FECFG_F3CFG_Pos)) -#define RFCTRL_FECFG_F4CFG_Pos 8 /**< \brief (RFCTRL_FECFG) Front-end control signal 4 configuration */ -#define RFCTRL_FECFG_F4CFG_Msk (0x3ul << RFCTRL_FECFG_F4CFG_Pos) -#define RFCTRL_FECFG_F4CFG(value) (RFCTRL_FECFG_F4CFG_Msk & ((value) << RFCTRL_FECFG_F4CFG_Pos)) -#define RFCTRL_FECFG_F5CFG_Pos 10 /**< \brief (RFCTRL_FECFG) Front-end control signal 5 configuration */ -#define RFCTRL_FECFG_F5CFG_Msk (0x3ul << RFCTRL_FECFG_F5CFG_Pos) -#define RFCTRL_FECFG_F5CFG(value) (RFCTRL_FECFG_F5CFG_Msk & ((value) << RFCTRL_FECFG_F5CFG_Pos)) -#define RFCTRL_FECFG_MASK 0x0FFFul /**< \brief (RFCTRL_FECFG) MASK Register */ - -/** \brief RFCTRL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */ -} Rfctrl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_RFCTRL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h deleted file mode 100644 index 6c1e8c48c1e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h +++ /dev/null @@ -1,1062 +0,0 @@ -/** - * \file - * - * \brief Component description for RTC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_RTC_COMPONENT_ -#define _SAMR21_RTC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR RTC */ -/* ========================================================================== */ -/** \addtogroup SAMR21_RTC Real-Time Counter */ -/*@{*/ - -#define RTC_U2202 -#define REV_RTC 0x101 - -/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :3; /*!< bit: 4.. 6 Reserved */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE0_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */ -#define RTC_MODE0_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */ - -#define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */ -#define RTC_MODE0_CTRL_SWRST (0x1ul << RTC_MODE0_CTRL_SWRST_Pos) -#define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */ -#define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos) -#define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */ -#define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos) -#define RTC_MODE0_CTRL_MODE(value) (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)) -#define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */ -#define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */ -#define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */ -#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos) -#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos) -#define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos) -#define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */ -#define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos) -#define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */ -#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)) -#define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos) -#define RTC_MODE0_CTRL_MASK 0x0F8Ful /**< \brief (RTC_MODE0_CTRL) MASK Register */ - -/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */ -#define RTC_MODE1_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */ - -#define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */ -#define RTC_MODE1_CTRL_SWRST (0x1ul << RTC_MODE1_CTRL_SWRST_Pos) -#define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */ -#define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos) -#define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */ -#define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos) -#define RTC_MODE1_CTRL_MODE(value) (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)) -#define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */ -#define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */ -#define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */ -#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos) -#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos) -#define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos) -#define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */ -#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)) -#define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos) -#define RTC_MODE1_CTRL_MASK 0x0F0Ful /**< \brief (RTC_MODE1_CTRL) MASK Register */ - -/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE2_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */ -#define RTC_MODE2_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */ - -#define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */ -#define RTC_MODE2_CTRL_SWRST (0x1ul << RTC_MODE2_CTRL_SWRST_Pos) -#define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */ -#define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos) -#define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */ -#define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos) -#define RTC_MODE2_CTRL_MODE(value) (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)) -#define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */ -#define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */ -#define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */ -#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos) -#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos) -#define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos) -#define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */ -#define RTC_MODE2_CTRL_CLKREP (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos) -#define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */ -#define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos) -#define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */ -#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)) -#define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ -#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos) -#define RTC_MODE2_CTRL_MASK 0x0FCFul /**< \brief (RTC_MODE2_CTRL) MASK Register */ - -/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ - uint16_t :8; /*!< bit: 6..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_READREQ_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */ -#define RTC_READREQ_RESETVALUE 0x0010ul /**< \brief (RTC_READREQ reset_value) Read Request */ - -#define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */ -#define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos) -#define RTC_READREQ_ADDR(value) (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)) -#define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */ -#define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos) -#define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */ -#define RTC_READREQ_RREQ (0x1ul << RTC_READREQ_RREQ_Pos) -#define RTC_READREQ_MASK 0xC03Ful /**< \brief (RTC_READREQ) MASK Register */ - -/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE0_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */ -#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */ - -#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos) -#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos) -#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos) -#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos) -#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos) -#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos) -#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos) -#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos) -#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos) -#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)) -#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */ -#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos) -#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */ -#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos) -#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)) -#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos) -#define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */ - -/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ - uint16_t :5; /*!< bit: 10..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */ -#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */ - -#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos) -#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos) -#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos) -#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos) -#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos) -#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos) -#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos) -#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos) -#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos) -#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)) -#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos) -#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos) -#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */ -#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos) -#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)) -#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos) -#define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */ - -/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE2_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */ -#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */ - -#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos) -#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos) -#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos) -#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos) -#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos) -#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos) -#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos) -#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos) -#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */ -#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos) -#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)) -#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */ -#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos) -#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */ -#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos) -#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)) -#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */ -#define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos) -#define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */ - -/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */ -#define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */ - -#define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */ -#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos) -#define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */ -#define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos) -#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)) -#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */ -#define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos) -#define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos) -#define RTC_MODE0_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */ - -/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */ -#define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */ - -#define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos) -#define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos) -#define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */ -#define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos) -#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)) -#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */ -#define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos) -#define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos) -#define RTC_MODE1_INTENCLR_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */ - -/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */ -#define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */ - -#define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */ -#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos) -#define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */ -#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos) -#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)) -#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */ -#define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos) -#define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */ -#define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos) -#define RTC_MODE2_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */ - -/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */ -#define RTC_MODE0_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */ - -#define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */ -#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos) -#define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */ -#define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos) -#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)) -#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */ -#define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos) -#define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos) -#define RTC_MODE0_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENSET) MASK Register */ - -/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */ -#define RTC_MODE1_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */ - -#define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos) -#define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos) -#define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */ -#define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos) -#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)) -#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */ -#define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos) -#define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos) -#define RTC_MODE1_INTENSET_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENSET) MASK Register */ - -/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */ -#define RTC_MODE2_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */ - -#define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */ -#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos) -#define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */ -#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos) -#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)) -#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */ -#define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos) -#define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */ -#define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos) -#define RTC_MODE2_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENSET) MASK Register */ - -/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ - __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - __I uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t CMP:1; /*!< bit: 0 Compare x */ - __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE0_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */ -#define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */ - -#define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */ -#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos) -#define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */ -#define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos) -#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)) -#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */ -#define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos) -#define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */ -#define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos) -#define RTC_MODE0_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */ - -/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ - __I uint8_t :4; /*!< bit: 2.. 5 Reserved */ - __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - __I uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE1_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */ -#define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */ - -#define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */ -#define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos) -#define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */ -#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos) -#define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */ -#define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos) -#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)) -#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */ -#define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos) -#define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */ -#define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos) -#define RTC_MODE1_INTFLAG_MASK 0xC3ul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */ - -/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ - __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ - __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - __I uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */ - __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */ -#define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */ - -#define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */ -#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos) -#define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */ -#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos) -#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)) -#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */ -#define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos) -#define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */ -#define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos) -#define RTC_MODE2_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */ - -/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */ -#define RTC_STATUS_RESETVALUE 0x00ul /**< \brief (RTC_STATUS reset_value) Status */ - -#define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */ -#define RTC_STATUS_SYNCBUSY (0x1ul << RTC_STATUS_SYNCBUSY_Pos) -#define RTC_STATUS_MASK 0x80ul /**< \brief (RTC_STATUS) MASK Register */ - -/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */ -#define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */ - -#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */ -#define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos) -#define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */ - -/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ - uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_FREQCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */ -#define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */ - -#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */ -#define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos) -#define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)) -#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */ -#define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos) -#define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */ - -/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE0_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */ -#define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */ - -#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */ -#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos) -#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)) -#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */ - -/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */ -#define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */ - -#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */ -#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos) -#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)) -#define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */ - -/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE2_CLOCK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */ -#define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */ - -#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */ -#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos) -#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)) -#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */ -#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos) -#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)) -#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */ -#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos) -#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)) -#define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */ -#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos) -#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */ -#define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos) -#define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)) -#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */ -#define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos) -#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)) -#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */ -#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos) -#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)) -#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */ - -/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PER:16; /*!< bit: 0..15 Counter Period */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */ -#define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */ - -#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */ -#define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos) -#define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)) -#define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */ - -/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE0_COMP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */ -#define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */ - -#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */ -#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos) -#define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)) -#define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */ - -/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} RTC_MODE1_COMP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */ -#define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */ - -#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */ -#define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos) -#define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)) -#define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */ - -/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} RTC_MODE2_ALARM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ -#define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ - -#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ -#define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos) -#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)) -#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ -#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos) -#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)) -#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ -#define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos) -#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)) -#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ -#define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos) -#define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)) -#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ -#define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos) -#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)) -#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ -#define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos) -#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)) -#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */ - -/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} RTC_MODE2_MASK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ -#define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ - -#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ -#define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)) -#define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ -#define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */ -#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ -#define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ -#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ -#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ -#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ -#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) -#define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */ - -/** \brief RtcMode2Alarm hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ - __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ - RoReg8 Reserved1[0x3]; -} RtcMode2Alarm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE0 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 32-bit Counter with Single 32-bit Compare */ - __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ - __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ - __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ - __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ -} RtcMode0; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE1 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 16-bit Counter with Two 16-bit Compares */ - __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ - __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ - __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ - __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ - RoReg8 Reserved3[0x2]; - __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ - RoReg8 Reserved4[0x2]; - __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ -} RtcMode1; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief RTC_MODE2 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* Clock/Calendar with Alarm */ - __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ - __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ - __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ - __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ - RoReg8 Reserved3[0x4]; - RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ -} RtcMode2; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ - RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ - RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ -} Rtc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_RTC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h deleted file mode 100644 index 055938af599..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h +++ /dev/null @@ -1,1508 +0,0 @@ -/** - * \file - * - * \brief Component description for SERCOM - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SERCOM_COMPONENT_ -#define _SAMR21_SERCOM_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR SERCOM */ -/* ========================================================================== */ -/** \addtogroup SAMR21_SERCOM Serial Communication Interface */ -/*@{*/ - -#define SERCOM_U2201 -#define REV_SERCOM 0x200 - -/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ -#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ - -#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ -#define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos) -#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ -#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ -#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)) -#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */ -#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */ -#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */ -#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */ -#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */ -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */ -#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) -#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ -#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) -#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ -#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos) -#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ -#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) -#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)) -#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ -#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) -#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) -#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ -#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos) -#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)) -#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ -#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos) -#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ -#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos) -#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)) -#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ -#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) -#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ - -/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ -#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ - -#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ -#define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos) -#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ -#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ -#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)) -#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */ -#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */ -#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */ -#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */ -#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */ -#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */ -#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) -#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ -#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) -#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ -#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos) -#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ -#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) -#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)) -#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) -#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ -#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos) -#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)) -#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ -#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos) -#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ -#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) -#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ - -/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ -#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ - -#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ -#define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos) -#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ -#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos) -#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ -#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)) -#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */ -#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */ -#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */ -#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */ -#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */ -#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */ -#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) -#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ -#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) -#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ -#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos) -#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ -#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos) -#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)) -#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ -#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos) -#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)) -#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ -#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos) -#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)) -#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ -#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos) -#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ -#define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos) -#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ -#define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos) -#define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ - -/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :4; /*!< bit: 9..12 Reserved */ - uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ - uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ - uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ -#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ - -#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ -#define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos) -#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ -#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos) -#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ -#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)) -#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */ -#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */ -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */ -#define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */ -#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */ -#define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */ -#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) -#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ -#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos) -#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ -#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos) -#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ -#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos) -#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)) -#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ -#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos) -#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)) -#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ -#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos) -#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)) -#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ -#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos) -#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)) -#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ -#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos) -#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)) -#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ -#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos) -#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ -#define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos) -#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ -#define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos) -#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */ - -/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ -#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ - -#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ -#define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos) -#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ -#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos) -#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ -#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos) -#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)) -#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ -#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos) -#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ - -/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ - uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ - uint32_t :3; /*!< bit: 11..13 Reserved */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ -#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ - -#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ -#define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos) -#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ -#define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos) -#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ -#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos) -#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ -#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos) -#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)) -#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ -#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos) -#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)) -#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ -#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos) -#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ - -/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ - uint32_t :2; /*!< bit: 7.. 8 Reserved */ - uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ - uint32_t :3; /*!< bit: 10..12 Reserved */ - uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ -#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ - -#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ -#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos) -#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)) -#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ -#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos) -#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ -#define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos) -#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ -#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos) -#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ -#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos) -#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)) -#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ -#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos) -#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ - -/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ - uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ - uint32_t ENC:1; /*!< bit: 10 Encoding Format */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ -#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ - -#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ -#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos) -#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)) -#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ -#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos) -#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ -#define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos) -#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ -#define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos) -#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ -#define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos) -#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ -#define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos) -#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ -#define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos) -#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ -#define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos) -#define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */ - -/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ - uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ - uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ -#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ - -#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ -#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos) -#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)) -#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ -#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos) -#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)) -#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ -#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos) -#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)) -#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ -#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) -#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)) -#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ - -/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ -#define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ - -#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ -#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos) -#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)) -#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */ - -/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - struct { // FRAC mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRAC; /*!< Structure used for FRAC */ - struct { // FRACFP mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRACFP; /*!< Structure used for FRACFP */ - struct { // USARTFP mode - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } USARTFP; /*!< Structure used for USARTFP */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_BAUD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ -#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ - -#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ -#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos) -#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)) -#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */ - -// FRAC mode -#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ -#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos) -#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)) -#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ -#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos) -#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)) -#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ - -// FRACFP mode -#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ -#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) -#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)) -#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ -#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos) -#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)) -#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ - -// USARTFP mode -#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ -#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) -#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)) -#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ - -/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_RXPL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ -#define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ - -#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ -#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos) -#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)) -#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */ - -/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ -#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ - -#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos) -#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos) -#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos) -#define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ - -/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ -#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ - -#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos) -#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos) -#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos) -#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos) -#define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ - -/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ -#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ - -#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos) -#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos) -#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos) -#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos) -#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos) -#define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ - -/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ -#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ - -#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ -#define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos) -#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ -#define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos) -#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos) -#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos) -#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ -#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos) -#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ -#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos) -#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ -#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos) -#define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ - -/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ -#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ - -#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos) -#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos) -#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos) -#define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ - -/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ -#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ - -#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos) -#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos) -#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos) -#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos) -#define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ - -/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ -#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ - -#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ -#define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos) -#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ -#define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos) -#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ -#define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos) -#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ -#define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos) -#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos) -#define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ - -/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ -#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ - -#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ -#define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos) -#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ -#define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos) -#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos) -#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos) -#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ -#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos) -#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ -#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos) -#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ -#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos) -#define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */ - -/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ - __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ - __I uint8_t :5; /*!< bit: 2.. 6 Reserved */ - __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ -#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ - -#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ -#define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos) -#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ -#define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos) -#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ -#define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos) -#define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ - -/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ - __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ - __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ - __I uint8_t :4; /*!< bit: 3.. 6 Reserved */ - __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ -#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ - -#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ -#define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos) -#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ -#define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos) -#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ -#define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos) -#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ -#define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos) -#define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ - -/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ - __I uint8_t :3; /*!< bit: 4.. 6 Reserved */ - __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ -#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ - -#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ -#define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos) -#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ -#define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos) -#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ -#define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos) -#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ -#define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos) -#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ -#define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos) -#define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ - -/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ - __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ - __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ - __I uint8_t :1; /*!< bit: 6 Reserved */ - __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ -#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ - -#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ -#define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos) -#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ -#define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos) -#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ -#define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos) -#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ -#define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos) -#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ -#define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos) -#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ -#define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos) -#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ -#define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos) -#define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ - -/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t LENERR:1; /*!< bit: 10 Length Error */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ -#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ - -#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ -#define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos) -#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ -#define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos) -#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ -#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos) -#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ -#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos) -#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)) -#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ -#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos) -#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ -#define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos) -#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ -#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) -#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) -#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ -#define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos) -#define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ - -/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ - uint16_t SR:1; /*!< bit: 4 Repeated Start */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t :1; /*!< bit: 8 Reserved */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t HS:1; /*!< bit: 10 High Speed */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ -#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ - -#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ -#define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos) -#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ -#define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos) -#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ -#define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos) -#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ -#define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos) -#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ -#define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos) -#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ -#define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos) -#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ -#define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos) -#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ -#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) -#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ -#define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos) -#define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ - -/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t :13; /*!< bit: 3..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_SPI_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ -#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ - -#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ -#define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos) -#define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */ - -/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PERR:1; /*!< bit: 0 Parity Error */ - uint16_t FERR:1; /*!< bit: 1 Frame Error */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t CTS:1; /*!< bit: 3 Clear To Send */ - uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ - uint16_t COLL:1; /*!< bit: 5 Collision Detected */ - uint16_t :10; /*!< bit: 6..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ -#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ - -#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ -#define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos) -#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ -#define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos) -#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ -#define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos) -#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ -#define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos) -#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ -#define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos) -#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ -#define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos) -#define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */ - -/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */ -#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */ - -#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) -#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) -#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ -#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) -#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */ -#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */ - -#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) -#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) -#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */ -#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */ - -#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos) -#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) -#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ -#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) -#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_USART_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */ -#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */ - -#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos) -#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos) -#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ -#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos) -#define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ - -/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t LENEN:1; /*!< bit: 13 Length Enable */ - uint32_t HS:1; /*!< bit: 14 High Speed Mode */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t LEN:8; /*!< bit: 16..23 Length */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ -#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ - -#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ -#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos) -#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)) -#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ -#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos) -#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ -#define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos) -#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ -#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos) -#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ -#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos) -#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)) -#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ - -/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ - uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ - uint32_t :4; /*!< bit: 11..14 Reserved */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ -#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ - -#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ -#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos) -#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ -#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos) -#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)) -#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ -#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos) -#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ -#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos) -#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)) -#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ - -/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ -#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ - -#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ -#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos) -#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)) -#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ -#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos) -#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)) -#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */ - -/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ -#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ - -#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ -#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos) -#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)) -#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */ - -/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CS_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ -#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ - -#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ -#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos) -#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)) -#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */ - -/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint32_t :23; /*!< bit: 9..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SERCOM_SPI_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ -#define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ - -#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ -#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos) -#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)) -#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */ - -/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SERCOM_USART_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ -#define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ - -#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ -#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos) -#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)) -#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */ - -/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_I2CM_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ -#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ - -#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ -#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ - -/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_SPI_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ -#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ - -#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ -#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ - -/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SERCOM_USART_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ -#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ - -#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ -#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) -#define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ - -/** \brief SERCOM_I2CM hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* I2C Master Mode */ - __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ - __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ - RoReg8 Reserved2[0x4]; - __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ - __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ - __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ - RoReg8 Reserved7[0x7]; - __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ -} SercomI2cm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_I2CS hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* I2C Slave Mode */ - __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ - __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ - RoReg8 Reserved1[0xC]; - __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ - RoReg8 Reserved2[0x1]; - __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ - __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ - RoReg8 Reserved5[0x4]; - __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ - __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ -} SercomI2cs; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_SPI hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* SPI Mode */ - __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ - __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ - RoReg8 Reserved2[0x7]; - __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ - __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ - __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ - RoReg8 Reserved7[0x4]; - __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ -} SercomSpi; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief SERCOM_USART hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USART Mode */ - __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ - __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ - __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ - RoReg8 Reserved2[0x5]; - __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ - __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ - RoReg8 Reserved6[0x8]; - __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ - RoReg8 Reserved7[0x6]; - __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ -} SercomUsart; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ - SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ - SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ - SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ -} Sercom; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_SERCOM_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h deleted file mode 100644 index 52eb8bddd1c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h +++ /dev/null @@ -1,948 +0,0 @@ -/** - * \file - * - * \brief Component description for SYSCTRL - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SYSCTRL_COMPONENT_ -#define _SAMR21_SYSCTRL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR SYSCTRL */ -/* ========================================================================== */ -/** \addtogroup SAMR21_SYSCTRL System Control */ -/*@{*/ - -#define SYSCTRL_U2100 -#define REV_SYSCTRL 0x201 - -/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */ -#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */ - -#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_XOSCRDY (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos) -#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos) -#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_OSC32KRDY (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos) -#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_OSC8MRDY (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos) -#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLRDY (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos) -#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLOOB (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos) -#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLLCKF (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos) -#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLLCKC (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos) -#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ -#define SYSCTRL_INTENCLR_DFLLRCS (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos) -#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_BOD33RDY (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos) -#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */ -#define SYSCTRL_INTENCLR_BOD33DET (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos) -#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */ -#define SYSCTRL_INTENCLR_B33SRDY (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos) -#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ -#define SYSCTRL_INTENCLR_DPLLLCKR (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos) -#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ -#define SYSCTRL_INTENCLR_DPLLLCKF (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos) -#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */ -#define SYSCTRL_INTENCLR_DPLLLTO (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos) -#define SYSCTRL_INTENCLR_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */ - -/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */ -#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */ - -#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_XOSCRDY (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos) -#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos) -#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_OSC32KRDY (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos) -#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_OSC8MRDY (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos) -#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLRDY (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos) -#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLOOB (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos) -#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLLCKF (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos) -#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLLCKC (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos) -#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ -#define SYSCTRL_INTENSET_DFLLRCS (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos) -#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_BOD33RDY (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos) -#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */ -#define SYSCTRL_INTENSET_BOD33DET (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos) -#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */ -#define SYSCTRL_INTENSET_B33SRDY (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos) -#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ -#define SYSCTRL_INTENSET_DPLLLCKR (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos) -#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ -#define SYSCTRL_INTENSET_DPLLLCKF (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos) -#define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */ -#define SYSCTRL_INTENSET_DPLLLTO (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos) -#define SYSCTRL_INTENSET_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */ - -/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - __I uint32_t :3; /*!< bit: 12..14 Reserved */ - __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - __I uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ -#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */ -#define SYSCTRL_INTFLAG_XOSCRDY (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos) -#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */ -#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos) -#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */ -#define SYSCTRL_INTFLAG_OSC32KRDY (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos) -#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */ -#define SYSCTRL_INTFLAG_OSC8MRDY (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos) -#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */ -#define SYSCTRL_INTFLAG_DFLLRDY (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos) -#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */ -#define SYSCTRL_INTFLAG_DFLLOOB (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos) -#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */ -#define SYSCTRL_INTFLAG_DFLLLCKF (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos) -#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */ -#define SYSCTRL_INTFLAG_DFLLLCKC (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos) -#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */ -#define SYSCTRL_INTFLAG_DFLLRCS (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos) -#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */ -#define SYSCTRL_INTFLAG_BOD33RDY (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos) -#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */ -#define SYSCTRL_INTFLAG_BOD33DET (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos) -#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */ -#define SYSCTRL_INTFLAG_B33SRDY (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos) -#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */ -#define SYSCTRL_INTFLAG_DPLLLCKR (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos) -#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */ -#define SYSCTRL_INTFLAG_DPLLLCKF (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos) -#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */ -#define SYSCTRL_INTFLAG_DPLLLTO (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos) -#define SYSCTRL_INTFLAG_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */ - -/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_PCLKSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */ -#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */ - -#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */ -#define SYSCTRL_PCLKSR_XOSCRDY (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos) -#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */ -#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos) -#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */ -#define SYSCTRL_PCLKSR_OSC32KRDY (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos) -#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */ -#define SYSCTRL_PCLKSR_OSC8MRDY (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos) -#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */ -#define SYSCTRL_PCLKSR_DFLLRDY (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos) -#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */ -#define SYSCTRL_PCLKSR_DFLLOOB (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos) -#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */ -#define SYSCTRL_PCLKSR_DFLLLCKF (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos) -#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */ -#define SYSCTRL_PCLKSR_DFLLLCKC (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos) -#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */ -#define SYSCTRL_PCLKSR_DFLLRCS (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos) -#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */ -#define SYSCTRL_PCLKSR_BOD33RDY (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos) -#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */ -#define SYSCTRL_PCLKSR_BOD33DET (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos) -#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */ -#define SYSCTRL_PCLKSR_B33SRDY (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos) -#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */ -#define SYSCTRL_PCLKSR_DPLLLCKR (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos) -#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */ -#define SYSCTRL_PCLKSR_DPLLLCKF (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos) -#define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */ -#define SYSCTRL_PCLKSR_DPLLLTO (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos) -#define SYSCTRL_PCLKSR_MASK 0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */ - -/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t :3; /*!< bit: 3.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ - uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ - uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SYSCTRL_XOSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define SYSCTRL_XOSC_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ - -#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */ -#define SYSCTRL_XOSC_ENABLE (0x1ul << SYSCTRL_XOSC_ENABLE_Pos) -#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */ -#define SYSCTRL_XOSC_XTALEN (0x1ul << SYSCTRL_XOSC_XTALEN_Pos) -#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */ -#define SYSCTRL_XOSC_RUNSTDBY (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos) -#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */ -#define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos) -#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */ -#define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN(value) (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)) -#define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */ -#define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */ -#define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */ -#define SYSCTRL_XOSC_GAIN_3_Val 0x3ul /**< \brief (SYSCTRL_XOSC) 16MHz */ -#define SYSCTRL_XOSC_GAIN_4_Val 0x4ul /**< \brief (SYSCTRL_XOSC) 30MHz */ -#define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos) -#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */ -#define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos) -#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */ -#define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos) -#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)) -#define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */ - -/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ - uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ - uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SYSCTRL_XOSC32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define SYSCTRL_XOSC32K_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ - -#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */ -#define SYSCTRL_XOSC32K_ENABLE (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos) -#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */ -#define SYSCTRL_XOSC32K_XTALEN (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos) -#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */ -#define SYSCTRL_XOSC32K_EN32K (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos) -#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */ -#define SYSCTRL_XOSC32K_EN1K (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos) -#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */ -#define SYSCTRL_XOSC32K_AAMPEN (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos) -#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */ -#define SYSCTRL_XOSC32K_RUNSTDBY (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos) -#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */ -#define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos) -#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */ -#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos) -#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)) -#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */ -#define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos) -#define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */ - -/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ - uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ - uint32_t :2; /*!< bit: 4.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_OSC32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ -#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ - -#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */ -#define SYSCTRL_OSC32K_ENABLE (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos) -#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */ -#define SYSCTRL_OSC32K_EN32K (0x1ul << SYSCTRL_OSC32K_EN32K_Pos) -#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */ -#define SYSCTRL_OSC32K_EN1K (0x1ul << SYSCTRL_OSC32K_EN1K_Pos) -#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */ -#define SYSCTRL_OSC32K_RUNSTDBY (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos) -#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */ -#define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos) -#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */ -#define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos) -#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)) -#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */ -#define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos) -#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */ -#define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos) -#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)) -#define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */ - -/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SYSCTRL_OSCULP32K_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ - -#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */ -#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos) -#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)) -#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */ -#define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos) -#define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */ - -/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_OSC8M_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */ -#define SYSCTRL_OSC8M_RESETVALUE 0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */ - -#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */ -#define SYSCTRL_OSC8M_ENABLE (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos) -#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */ -#define SYSCTRL_OSC8M_RUNSTDBY (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos) -#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */ -#define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos) -#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */ -#define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_PRESC(value) (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)) -#define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */ -#define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */ -#define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */ -#define SYSCTRL_OSC8M_PRESC_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 8 */ -#define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos) -#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */ -#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos) -#define SYSCTRL_OSC8M_CALIB(value) (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)) -#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */ -#define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)) -#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */ -#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */ -#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */ -#define SYSCTRL_OSC8M_FRANGE_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */ -#define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos) -#define SYSCTRL_OSC8M_MASK 0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */ - -/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ - uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ - uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ - uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ - uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ - uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ - uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ - uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SYSCTRL_DFLLCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */ -#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */ - -#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */ -#define SYSCTRL_DFLLCTRL_ENABLE (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos) -#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */ -#define SYSCTRL_DFLLCTRL_MODE (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos) -#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */ -#define SYSCTRL_DFLLCTRL_STABLE (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos) -#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */ -#define SYSCTRL_DFLLCTRL_LLAW (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos) -#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */ -#define SYSCTRL_DFLLCTRL_USBCRM (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos) -#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */ -#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos) -#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */ -#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos) -#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */ -#define SYSCTRL_DFLLCTRL_CCDIS (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos) -#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */ -#define SYSCTRL_DFLLCTRL_QLDIS (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos) -#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */ -#define SYSCTRL_DFLLCTRL_BPLCKC (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos) -#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */ -#define SYSCTRL_DFLLCTRL_WAITLOCK (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos) -#define SYSCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */ - -/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ - uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ - uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_DFLLVAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */ -#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */ - -#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */ -#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos) -#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)) -#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */ -#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos) -#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)) -#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */ -#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos) -#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)) -#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */ - -/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ - uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ - uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_DFLLMUL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */ -#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ - -#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */ -#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos) -#define SYSCTRL_DFLLMUL_MUL(value) (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)) -#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */ -#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos) -#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)) -#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */ -#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos) -#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)) -#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */ - -/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t READREQ:1; /*!< bit: 7 Read Request */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SYSCTRL_DFLLSYNC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */ -#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ - -#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */ -#define SYSCTRL_DFLLSYNC_READREQ (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos) -#define SYSCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */ - -/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t HYST:1; /*!< bit: 2 Hysteresis */ - uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MODE:1; /*!< bit: 8 Operation Mode */ - uint32_t CEN:1; /*!< bit: 9 Clock Enable */ - uint32_t :2; /*!< bit: 10..11 Reserved */ - uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ - uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_BOD33_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */ -#define SYSCTRL_BOD33_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */ - -#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */ -#define SYSCTRL_BOD33_ENABLE (0x1ul << SYSCTRL_BOD33_ENABLE_Pos) -#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */ -#define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos) -#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */ -#define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos) -#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)) -#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */ -#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */ -#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */ -#define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos) -#define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos) -#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos) -#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */ -#define SYSCTRL_BOD33_RUNSTDBY (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos) -#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */ -#define SYSCTRL_BOD33_MODE (0x1ul << SYSCTRL_BOD33_MODE_Pos) -#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */ -#define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos) -#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */ -#define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL(value) (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)) -#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */ -#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */ -#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */ -#define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */ -#define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */ -#define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */ -#define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */ -#define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */ -#define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */ -#define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9ul /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */ -#define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAul /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */ -#define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBul /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */ -#define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCul /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */ -#define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDul /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */ -#define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEul /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */ -#define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFul /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */ -#define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos) -#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */ -#define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos) -#define SYSCTRL_BOD33_LEVEL(value) (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)) -#define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */ - -/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :6; /*!< bit: 0.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t :6; /*!< bit: 7..12 Reserved */ - uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} SYSCTRL_VREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */ -#define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */ - -#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */ -#define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos) -#define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */ -#define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos) -#define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */ - -/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ - uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ - uint32_t :13; /*!< bit: 3..15 Reserved */ - uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_VREF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */ -#define SYSCTRL_VREF_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */ - -#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */ -#define SYSCTRL_VREF_TSEN (0x1ul << SYSCTRL_VREF_TSEN_Pos) -#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */ -#define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos) -#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */ -#define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos) -#define SYSCTRL_VREF_CALIB(value) (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)) -#define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */ - -/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SYSCTRL_DPLLCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */ -#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */ - -#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */ -#define SYSCTRL_DPLLCTRLA_ENABLE (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos) -#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */ -#define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos) -#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */ -#define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) -#define SYSCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */ - -/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_DPLLRATIO_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */ -#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ - -#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */ -#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos) -#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)) -#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ -#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos) -#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)) -#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */ - -/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ - uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ - uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ - uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SYSCTRL_DPLLCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */ -#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */ - -#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ -#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)) -#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */ -#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */ -#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */ -#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */ -#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) -#define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */ -#define SYSCTRL_DPLLCTRLB_LPEN (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos) -#define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */ -#define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos) -#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */ -#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos) -#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)) -#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */ -#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */ -#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */ -#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) -#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) -#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */ -#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)) -#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */ -#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */ -#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */ -#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */ -#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */ -#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) -#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */ -#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) -#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */ -#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos) -#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)) -#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */ - -/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ - uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ - uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ - uint8_t DIV:1; /*!< bit: 3 Divider Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} SYSCTRL_DPLLSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */ -#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */ - -#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */ -#define SYSCTRL_DPLLSTATUS_LOCK (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos) -#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */ -#define SYSCTRL_DPLLSTATUS_CLKRDY (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos) -#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */ -#define SYSCTRL_DPLLSTATUS_ENABLE (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos) -#define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */ -#define SYSCTRL_DPLLSTATUS_DIV (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos) -#define SYSCTRL_DPLLSTATUS_MASK 0x0Ful /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */ - -/** \brief SYSCTRL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ - __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ - __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ - __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ - __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ - RoReg8 Reserved1[0x2]; - __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ - RoReg8 Reserved2[0x2]; - __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ - __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ - RoReg8 Reserved3[0x3]; - __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ - __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ - RoReg8 Reserved4[0x2]; - __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ - __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ - __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ - RoReg8 Reserved5[0x3]; - __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ - RoReg8 Reserved6[0x4]; - __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ - RoReg8 Reserved7[0x2]; - __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ - __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ - RoReg8 Reserved8[0x3]; - __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ - __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ - __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ -} Sysctrl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_SYSCTRL_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h deleted file mode 100644 index 44f2f706e29..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h +++ /dev/null @@ -1,684 +0,0 @@ -/** - * \file - * - * \brief Component description for TC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_TC_COMPONENT_ -#define _SAMR21_TC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TC */ -/* ========================================================================== */ -/** \addtogroup SAMR21_TC Basic Timer Counter */ -/*@{*/ - -#define TC_U2212 -#define REV_TC 0x121 - -/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ -#define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */ - -#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ -#define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos) -#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ -#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) -#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */ -#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)) -#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */ -#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */ -#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */ -#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) -#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */ -#define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)) -#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */ -#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */ -#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */ -#define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */ -#define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos) -#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ -#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)) -#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */ -#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */ -#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */ -#define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */ -#define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */ -#define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */ -#define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */ -#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */ -#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) -#define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */ -#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos) -#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ -#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)) -#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */ -#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */ -#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */ -#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) -#define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */ - -/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ - uint16_t :9; /*!< bit: 5..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_READREQ_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */ -#define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */ - -#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */ -#define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos) -#define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)) -#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */ -#define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos) -#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */ -#define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos) -#define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */ - -/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_CTRLBCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ -#define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ - -#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ -#define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos) -#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */ -#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos) -#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */ -#define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)) -#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */ -#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */ -#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */ -#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) -#define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */ - -/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_CTRLBSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ -#define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */ - -#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ -#define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos) -#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */ -#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos) -#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */ -#define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)) -#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */ -#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */ -#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */ -#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) -#define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */ - -/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ - uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ - uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_CTRLC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */ -#define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */ - -#define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */ -#define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos) -#define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */ -#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos) -#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */ -#define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos) -#define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)) -#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */ -#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos) -#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */ -#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos) -#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */ -#define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos) -#define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)) -#define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */ - -/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */ -#define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */ - -#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */ -#define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos) -#define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */ - -/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ - uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ - uint16_t :3; /*!< bit: 9..11 Reserved */ - uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ - uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :12; /*!< bit: 0..11 Reserved */ - uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */ -#define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */ - -#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ -#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)) -#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */ -#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ -#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */ -#define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */ -#define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */ -#define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */ -#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) -#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */ -#define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos) -#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */ -#define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos) -#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */ -#define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos) -#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ -#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos) -#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ -#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos) -#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */ -#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos) -#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)) -#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */ - -/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ -#define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */ -#define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos) -#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */ -#define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos) -#define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos) -#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ -#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos) -#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ -#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos) -#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */ -#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos) -#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)) -#define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */ - -/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ -#define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ - -#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */ -#define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos) -#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */ -#define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos) -#define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */ -#define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos) -#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ -#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos) -#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ -#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos) -#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */ -#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos) -#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)) -#define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */ - -/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t OVF:1; /*!< bit: 0 Overflow */ - __I uint8_t ERR:1; /*!< bit: 1 Error */ - __I uint8_t :1; /*!< bit: 2 Reserved */ - __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ - __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ - __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ - __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ - __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} TC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */ -#define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos) -#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */ -#define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos) -#define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */ -#define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos) -#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */ -#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos) -#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */ -#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos) -#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */ -#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos) -#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)) -#define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */ - -/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :3; /*!< bit: 0.. 2 Reserved */ - uint8_t STOP:1; /*!< bit: 3 Stop */ - uint8_t SLAVE:1; /*!< bit: 4 Slave */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */ -#define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */ - -#define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */ -#define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos) -#define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */ -#define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos) -#define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */ -#define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos) -#define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */ - -/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_COUNT16_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */ -#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */ - -#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */ -#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos) -#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)) -#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */ - -/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TC_COUNT32_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */ -#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */ - -#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */ -#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos) -#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)) -#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */ - -/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */ -#define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */ - -#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ -#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos) -#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)) -#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */ - -/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */ -#define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */ - -#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ -#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos) -#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)) -#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */ - -/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} TC_COUNT16_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */ -#define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */ - -#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */ -#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos) -#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)) -#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */ - -/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TC_COUNT32_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */ -#define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */ - -#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */ -#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos) -#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)) -#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */ - -/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TC_COUNT8_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */ -#define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */ - -#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */ -#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos) -#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)) -#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */ - -/** \brief TC_COUNT8 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 8-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ - RoReg8 Reserved3[0x3]; - __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ - RoReg8 Reserved4[0x3]; - __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ -} TcCount8; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief TC_COUNT16 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 16-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ - RoReg8 Reserved3[0x6]; - __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ -} TcCount16; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief TC_COUNT32 hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* 32-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ -} TcCount32; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ - TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ - TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ -} Tc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_TC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h deleted file mode 100644 index 82747024970..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h +++ /dev/null @@ -1,1817 +0,0 @@ -/** - * \file - * - * \brief Component description for TCC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_TCC_COMPONENT_ -#define _SAMR21_TCC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR TCC */ -/* ========================================================================== */ -/** \addtogroup SAMR21_TCC Timer Counter Control */ -/*@{*/ - -#define TCC_U2213 -#define REV_TCC 0x101 - -/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t :3; /*!< bit: 2.. 4 Reserved */ - uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ - uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ - uint32_t :9; /*!< bit: 15..23 Reserved */ - uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ - uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ - uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ - uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :24; /*!< bit: 0..23 Reserved */ - uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ -#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */ - -#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ -#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos) -#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ -#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos) -#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ -#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)) -#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */ -#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ -#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ -#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ -#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) -#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ -#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)) -#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */ -#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */ -#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */ -#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */ -#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */ -#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */ -#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */ -#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */ -#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) -#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ -#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos) -#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ -#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)) -#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ -#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ -#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ -#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) -#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ -#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos) -#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ -#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) -#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ -#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) -#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ -#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) -#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ -#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) -#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ -#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos) -#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)) -#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */ - -/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_CTRLBCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ -#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ - -#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ -#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos) -#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ -#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos) -#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ -#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos) -#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ -#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)) -#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ -#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ -#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ -#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ -#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) -#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ -#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)) -#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */ -#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ -#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */ -#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */ -#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ -#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) -#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */ - -/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_CTRLBSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ -#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ - -#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ -#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos) -#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ -#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos) -#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ -#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos) -#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ -#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)) -#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ -#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ -#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ -#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ -#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) -#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ -#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)) -#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */ -#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ -#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */ -#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */ -#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ -#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) -#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */ - -/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ - uint32_t STATUS:1; /*!< bit: 3 Status Busy */ - uint32_t COUNT:1; /*!< bit: 4 Count Busy */ - uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ - uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ - uint32_t PER:1; /*!< bit: 7 Period busy */ - uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ - uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ - uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ - uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ - uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ - uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ - uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ - uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ - uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ - uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ - uint32_t :7; /*!< bit: 12..18 Reserved */ - uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ -#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ - -#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ -#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos) -#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ -#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos) -#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ -#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos) -#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ -#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos) -#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ -#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos) -#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ -#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos) -#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ -#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos) -#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */ -#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos) -#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ -#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) -#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ -#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) -#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ -#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) -#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ -#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) -#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ -#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos) -#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)) -#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */ -#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos) -#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */ -#define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos) -#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */ -#define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos) -#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */ -#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos) -#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */ -#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos) -#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */ -#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos) -#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */ -#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos) -#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */ -#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos) -#define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)) -#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */ - -/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_FCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ -#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ - -#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ -#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)) -#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */ -#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ -#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ -#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ -#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) -#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ -#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos) -#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ -#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos) -#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ -#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)) -#define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */ -#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ -#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ -#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ -#define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) -#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ -#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos) -#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ -#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)) -#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */ -#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */ -#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */ -#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */ -#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) -#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ -#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)) -#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ -#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ -#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ -#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ -#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) -#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ -#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)) -#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */ -#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */ -#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */ -#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */ -#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */ -#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */ -#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ -#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) -#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ -#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos) -#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)) -#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ -#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos) -#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)) -#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */ - -/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_FCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ -#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ - -#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ -#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)) -#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */ -#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ -#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ -#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ -#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) -#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ -#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos) -#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ -#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos) -#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ -#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)) -#define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */ -#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ -#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ -#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ -#define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) -#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ -#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos) -#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ -#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)) -#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */ -#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */ -#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */ -#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */ -#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) -#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ -#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)) -#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ -#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ -#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ -#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ -#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) -#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ -#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)) -#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */ -#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */ -#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */ -#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */ -#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */ -#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */ -#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ -#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) -#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ -#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos) -#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)) -#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ -#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos) -#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)) -#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */ - -/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ - uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ - uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ - uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ - uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WEXCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ -#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ - -#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ -#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos) -#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)) -#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ -#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) -#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ -#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) -#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ -#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) -#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ -#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) -#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ -#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos) -#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)) -#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ -#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos) -#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)) -#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ -#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos) -#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)) -#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */ - -/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ - uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ - uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ - uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ - uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ - uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ - uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ - uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ - uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ - uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ - uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ - uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ - uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ - uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ - uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ - uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ - uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ - uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ - uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ - uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ - uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ - uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ - uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ - uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ - uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ - uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ - uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ - uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_DRVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ -#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ - -#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ -#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) -#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ -#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) -#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ -#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) -#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ -#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) -#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ -#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) -#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ -#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) -#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ -#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) -#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ -#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) -#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ -#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos) -#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)) -#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ -#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) -#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ -#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) -#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ -#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) -#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ -#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) -#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ -#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) -#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ -#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) -#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ -#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) -#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ -#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) -#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ -#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos) -#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)) -#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ -#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) -#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ -#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) -#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ -#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) -#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ -#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) -#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ -#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) -#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ -#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) -#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ -#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) -#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ -#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) -#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ -#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos) -#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)) -#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ -#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos) -#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)) -#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ -#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos) -#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)) -#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */ - -/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} TCC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ -#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ - -#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ -#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos) -#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ -#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos) -#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */ - -/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ - uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ - uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ - uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ - uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ - uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ - uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ - uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ - uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ - uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ - uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ - uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ - uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ - uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ - uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ - uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :12; /*!< bit: 0..11 Reserved */ - uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ - uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ - uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ -#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */ - -#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ -#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)) -#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ -#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ -#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */ -#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */ -#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */ -#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ -#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ -#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) -#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ -#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)) -#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ -#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ -#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */ -#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */ -#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */ -#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ -#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ -#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ -#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) -#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ -#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)) -#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ -#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ -#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ -#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ -#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) -#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ -#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos) -#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ -#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos) -#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ -#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos) -#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ -#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) -#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ -#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) -#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ -#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos) -#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)) -#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ -#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) -#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ -#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) -#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ -#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos) -#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)) -#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ -#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) -#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ -#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) -#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ -#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) -#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ -#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) -#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ -#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos) -#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)) -#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ -#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) -#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ -#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) -#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ -#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) -#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ -#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) -#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ -#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos) -#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)) -#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */ - -/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ -#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ -#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos) -#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ -#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos) -#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ -#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos) -#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ -#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos) -#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ -#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos) -#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ -#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos) -#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ -#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos) -#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ -#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos) -#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ -#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos) -#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ -#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) -#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ -#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) -#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ -#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) -#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ -#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) -#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ -#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos) -#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)) -#define TCC_INTENCLR_MASK 0x000FF80Ful /**< \brief (TCC_INTENCLR) MASK Register */ - -/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ -#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ - -#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ -#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos) -#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ -#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos) -#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ -#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos) -#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ -#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos) -#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ -#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos) -#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ -#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos) -#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ -#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos) -#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ -#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos) -#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ -#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos) -#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ -#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) -#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ -#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) -#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ -#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) -#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ -#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) -#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ -#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos) -#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)) -#define TCC_INTENSET_MASK 0x000FF80Ful /**< \brief (TCC_INTENSET) MASK Register */ - -/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint32_t OVF:1; /*!< bit: 0 Overflow */ - __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ - __I uint32_t CNT:1; /*!< bit: 2 Counter */ - __I uint32_t ERR:1; /*!< bit: 3 Error */ - __I uint32_t :7; /*!< bit: 4..10 Reserved */ - __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ - __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ - __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ - __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ - __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ - __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ - __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ - __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ - __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ - __I uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint32_t :16; /*!< bit: 0..15 Reserved */ - __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ - __I uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ -#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos) -#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ -#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos) -#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ -#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos) -#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ -#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos) -#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ -#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos) -#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ -#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos) -#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ -#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos) -#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ -#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos) -#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ -#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos) -#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ -#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) -#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ -#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) -#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ -#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) -#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ -#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) -#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ -#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos) -#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)) -#define TCC_INTFLAG_MASK 0x000FF80Ful /**< \brief (TCC_INTFLAG) MASK Register */ - -/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t STOP:1; /*!< bit: 0 Stop */ - uint32_t IDX:1; /*!< bit: 1 Ramp */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ - uint32_t SLAVE:1; /*!< bit: 4 Slave */ - uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ - uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ - uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ - uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ - uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ - uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ - uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ - uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ - uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ - uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ - uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ - uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ - uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ - uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ -#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */ - -#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ -#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos) -#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ -#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos) -#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ -#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos) -#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ -#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos) -#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ -#define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos) -#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ -#define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos) -#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ -#define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos) -#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ -#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos) -#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ -#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos) -#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ -#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos) -#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ -#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos) -#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ -#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos) -#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ -#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos) -#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ -#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos) -#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ -#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos) -#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ -#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos) -#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ -#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos) -#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ -#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos) -#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ -#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos) -#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ -#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos) -#define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)) -#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ -#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) -#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ -#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) -#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ -#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) -#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ -#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) -#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ -#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos) -#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)) -#define TCC_STATUS_MASK 0x0F0FFFFBul /**< \brief (TCC_STATUS) MASK Register */ - -/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_COUNT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ -#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */ - -// DITH4 mode -#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ -#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos) -#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)) -#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ -#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos) -#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)) -#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ -#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos) -#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)) -#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */ - -#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ -#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos) -#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)) -#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */ - -/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ - uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ - uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ - uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ - uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ - uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ - uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ - uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ - uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ - uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ - uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ - uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ - uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ - uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ - uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ - uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ - uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TCC_PATT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ -#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */ - -#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ -#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) -#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ -#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) -#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ -#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) -#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ -#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) -#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ -#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) -#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ -#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) -#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ -#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) -#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ -#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) -#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ -#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos) -#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)) -#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ -#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) -#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ -#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) -#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ -#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) -#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ -#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) -#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ -#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) -#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ -#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) -#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ -#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) -#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ -#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) -#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ -#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos) -#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)) -#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */ - -/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ - uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ - uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ - uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ - uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ - uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ - uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ - uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ - uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ - uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ - uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WAVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ -#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */ - -#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ -#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)) -#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */ -#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */ -#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */ -#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */ -#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ -#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ -#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ -#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) -#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ -#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)) -#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */ -#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */ -#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) -#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ -#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos) -#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ -#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) -#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ -#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) -#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ -#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) -#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ -#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) -#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ -#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos) -#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)) -#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ -#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) -#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ -#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) -#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ -#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) -#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ -#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) -#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ -#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos) -#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)) -#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ -#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) -#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ -#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) -#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ -#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) -#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ -#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) -#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ -#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos) -#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)) -#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */ - -/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t PER:20; /*!< bit: 4..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t PER:19; /*!< bit: 5..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t PER:18; /*!< bit: 6..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PER:24; /*!< bit: 0..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_PER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ -#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */ - -// DITH4 mode -#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ -#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos) -#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)) -#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ -#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos) -#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)) -#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ -#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos) -#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)) -#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ -#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos) -#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)) -#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ -#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos) -#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)) -#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ -#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos) -#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)) -#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */ - -#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ -#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos) -#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)) -#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */ - -/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ -#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */ - -// DITH4 mode -#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ -#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos) -#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)) -#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ -#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos) -#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)) -#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ -#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos) -#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)) -#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ -#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos) -#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)) -#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ -#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos) -#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)) -#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ -#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos) -#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)) -#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */ - -#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ -#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos) -#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)) -#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */ - -/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ - uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ - uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ - uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ - uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ - uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ - uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ - uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ - uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ - uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ - uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ - uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ - uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ - uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ - uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ - uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ - uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} TCC_PATTB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */ -#define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */ - -#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */ -#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos) -#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */ -#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos) -#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */ -#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos) -#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */ -#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos) -#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */ -#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos) -#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */ -#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos) -#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */ -#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos) -#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */ -#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos) -#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */ -#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos) -#define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)) -#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */ -#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos) -#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */ -#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos) -#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */ -#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos) -#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */ -#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos) -#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */ -#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos) -#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */ -#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos) -#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */ -#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos) -#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */ -#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos) -#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */ -#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos) -#define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)) -#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */ - -/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ - uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ - uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ - uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ - uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ - uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ - uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ - uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ - uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ - uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ - uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_WAVEB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */ -#define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */ - -#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */ -#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)) -#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */ -#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */ -#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */ -#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */ -#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ -#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ -#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */ -#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos) -#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */ -#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)) -#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */ -#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */ -#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */ -#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos) -#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */ -#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos) -#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */ -#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos) -#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */ -#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos) -#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */ -#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos) -#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */ -#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos) -#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */ -#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos) -#define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)) -#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */ -#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos) -#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */ -#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos) -#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */ -#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos) -#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */ -#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos) -#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */ -#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos) -#define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)) -#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */ -#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos) -#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */ -#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos) -#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */ -#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos) -#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */ -#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos) -#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */ -#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos) -#define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)) -#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */ - -/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_PERB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */ -#define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */ - -// DITH4 mode -#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos) -#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)) -#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */ -#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos) -#define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)) -#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos) -#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)) -#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */ -#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos) -#define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)) -#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */ -#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos) -#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)) -#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */ -#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos) -#define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)) -#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */ - -#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */ -#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos) -#define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)) -#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */ - -/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} TCC_CCB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */ -#define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */ - -// DITH4 mode -#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos) -#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)) -#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos) -#define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)) -#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */ - -// DITH5 mode -#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos) -#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)) -#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos) -#define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)) -#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */ - -// DITH6 mode -#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */ -#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos) -#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)) -#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos) -#define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)) -#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */ - -#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */ -#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos) -#define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)) -#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */ - -/** \brief TCC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - RoReg8 Reserved1[0x2]; - __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ - __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ - __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ - __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ - RoReg8 Reserved2[0x2]; - __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ - RoReg8 Reserved3[0x1]; - __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ - __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ - __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ - __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ - __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ - __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ - __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ - RoReg8 Reserved4[0x2]; - __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ - __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ - __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ - RoReg8 Reserved5[0x10]; - __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ - RoReg8 Reserved6[0x2]; - __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ - __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ - __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ -} Tcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_TCC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h deleted file mode 100644 index 6c9ee674356..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h +++ /dev/null @@ -1,1804 +0,0 @@ -/** - * \file - * - * \brief Component description for USB - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_USB_COMPONENT_ -#define _SAMR21_USB_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR USB */ -/* ========================================================================== */ -/** \addtogroup SAMR21_USB Universal Serial Bus */ -/*@{*/ - -#define USB_U2222 -#define REV_USB 0x101 - -/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t MODE:1; /*!< bit: 7 Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */ -#define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */ - -#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */ -#define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos) -#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */ -#define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos) -#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */ -#define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos) -#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */ -#define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */ -#define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */ -#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) -#define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */ - -/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */ -#define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */ - -#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */ -#define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos) -#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */ -#define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos) -#define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */ - -/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ - uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */ -#define USB_QOSCTRL_RESETVALUE 0x05ul /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */ - -#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */ -#define USB_QOSCTRL_CQOS_Msk (0x3ul << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos)) -#define USB_QOSCTRL_CQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ -#define USB_QOSCTRL_CQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ -#define USB_QOSCTRL_CQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */ -#define USB_QOSCTRL_CQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */ -#define USB_QOSCTRL_CQOS_DISABLE (USB_QOSCTRL_CQOS_DISABLE_Val << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_CQOS_LOW (USB_QOSCTRL_CQOS_LOW_Val << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_CQOS_MEDIUM (USB_QOSCTRL_CQOS_MEDIUM_Val << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos) -#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */ -#define USB_QOSCTRL_DQOS_Msk (0x3ul << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos)) -#define USB_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ -#define USB_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ -#define USB_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */ -#define USB_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */ -#define USB_QOSCTRL_DQOS_DISABLE (USB_QOSCTRL_DQOS_DISABLE_Val << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_DQOS_LOW (USB_QOSCTRL_DQOS_LOW_Val << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_DQOS_MEDIUM (USB_QOSCTRL_DQOS_MEDIUM_Val << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_DQOS_HIGH (USB_QOSCTRL_DQOS_HIGH_Val << USB_QOSCTRL_DQOS_Pos) -#define USB_QOSCTRL_MASK 0x0Ful /**< \brief (USB_QOSCTRL) MASK Register */ - -/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DETACH:1; /*!< bit: 0 Detach */ - uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ - uint16_t NREPLY:1; /*!< bit: 4 No Reply */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ - uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ - uint16_t GNAK:1; /*!< bit: 9 Global NAK */ - uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */ -#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */ - -#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */ -#define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos) -#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */ -#define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */ -#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)) -#define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */ -#define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */ -#define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */ -#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */ -#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) -#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */ -#define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos) -#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */ -#define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos) -#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */ -#define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos) -#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */ -#define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos) -#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */ -#define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos) -#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */ -#define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */ -#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)) -#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ -#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */ -#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */ -#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */ -#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) -#define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */ - -/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ - uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ - uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ - uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */ -#define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */ - -#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */ -#define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos) -#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */ -#define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)) -#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */ -#define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */ -#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) -#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */ -#define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos) -#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */ -#define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos) -#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */ -#define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos) -#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */ -#define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos) -#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */ -#define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos) -#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */ -#define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos) -#define USB_HOST_CTRLB_MASK 0x0F6Eul /**< \brief (USB_HOST_CTRLB) MASK Register */ - -/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ - uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_DADD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */ -#define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */ - -#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */ -#define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos) -#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)) -#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */ -#define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos) -#define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */ - -/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_HSOFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */ -#define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */ - -#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */ -#define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos) -#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)) -#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */ -#define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos) -#define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */ - -/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */ -#define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */ - -#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */ -#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)) -#define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */ -#define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */ -#define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */ -#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) -#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */ -#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)) -#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */ -#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */ -#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */ -#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) -#define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */ - -/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */ -#define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */ - -#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */ -#define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos) -#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)) -#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */ -#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos) -#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)) -#define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */ - -/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_FSMSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */ -#define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */ - -#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */ -#define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)) -#define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ -#define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ -#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */ -#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */ -#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ -#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ -#define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */ -#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) -#define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */ - -/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :1; /*!< bit: 14 Reserved */ - uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_FNUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */ -#define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */ - -#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */ -#define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos) -#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)) -#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */ -#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos) -#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)) -#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */ -#define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos) -#define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */ - -/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_FNUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */ -#define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */ - -#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */ -#define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos) -#define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)) -#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */ -#define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos) -#define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)) -#define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */ - -/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_FLENHIGH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */ -#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */ - -#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */ -#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos) -#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)) -#define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */ - -/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */ -#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */ - -#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */ -#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos) -#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */ -#define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos) -#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */ -#define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos) -#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */ -#define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos) -#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */ -#define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos) -#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */ -#define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos) -#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */ -#define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos) -#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */ -#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos) -#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */ -#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos) -#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */ -#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos) -#define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */ - -/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ - uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */ -#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */ - -#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */ -#define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos) -#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */ -#define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos) -#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */ -#define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos) -#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */ -#define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos) -#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */ -#define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos) -#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */ -#define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos) -#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */ -#define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos) -#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */ -#define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos) -#define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */ - -/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */ -#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */ - -#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */ -#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos) -#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */ -#define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos) -#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */ -#define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos) -#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */ -#define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos) -#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */ -#define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos) -#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */ -#define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos) -#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */ -#define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos) -#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */ -#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos) -#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */ -#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos) -#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */ -#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos) -#define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */ - -/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ - uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */ -#define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */ - -#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */ -#define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos) -#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */ -#define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos) -#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */ -#define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos) -#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */ -#define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos) -#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */ -#define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos) -#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */ -#define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos) -#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */ -#define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos) -#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */ -#define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos) -#define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */ - -/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ - __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ - __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ - __I uint16_t EORST:1; /*!< bit: 3 End of Reset */ - __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ - __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ - __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ - __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ - __I uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */ -#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */ - -#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */ -#define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos) -#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */ -#define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos) -#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */ -#define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos) -#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */ -#define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos) -#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */ -#define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos) -#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */ -#define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos) -#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */ -#define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos) -#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */ -#define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos) -#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */ -#define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos) -#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */ -#define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos) -#define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */ - -/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint16_t :2; /*!< bit: 0.. 1 Reserved */ - __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ - __I uint16_t RST:1; /*!< bit: 3 Bus Reset */ - __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */ - __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ - __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */ - __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ - __I uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */ -#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */ - -#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */ -#define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos) -#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */ -#define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos) -#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */ -#define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos) -#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */ -#define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos) -#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */ -#define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos) -#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */ -#define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos) -#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */ -#define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos) -#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */ -#define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos) -#define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */ - -/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTSMRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */ -#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */ - -#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */ -#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos) -#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)) -#define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */ - -/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_PINTSMRY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */ -#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */ - -#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos) -#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos) -#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos) -#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos) -#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos) -#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos) -#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos) -#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */ -#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos) -#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */ -#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos) -#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)) -#define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */ - -/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DESCADD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */ -#define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */ - -#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */ -#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos) -#define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)) -#define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */ - -/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_PADCAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */ -#define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */ - -#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */ -#define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos) -#define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)) -#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */ -#define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos) -#define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)) -#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */ -#define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos) -#define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)) -#define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */ - -/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ - uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */ -#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */ - -#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */ -#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos) -#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)) -#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */ -#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos) -#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)) -#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */ -#define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos) -#define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */ - -/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ - uint8_t BK:1; /*!< bit: 2 Pipe Bank */ - uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */ -#define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */ - -#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */ -#define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos) -#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)) -#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */ -#define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos) -#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */ -#define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos) -#define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)) -#define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */ - -/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_BINTERVAL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */ -#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */ - -#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */ -#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos) -#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)) -#define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUSCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */ -#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */ - -#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */ -#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */ -#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */ -#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */ -#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)) -#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */ -#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */ -#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */ - -/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUSCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */ -#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */ - -#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */ -#define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos) -#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */ -#define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos) -#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */ -#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos) -#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */ -#define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos) -#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */ -#define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos) -#define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUSSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */ -#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */ - -#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */ -#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */ -#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */ -#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */ -#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)) -#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */ -#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */ -#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */ - -/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUSSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */ -#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */ - -#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */ -#define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos) -#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */ -#define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos) -#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */ -#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos) -#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */ -#define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos) -#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */ -#define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos) -#define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */ - -/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */ -#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */ - -#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */ -#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) -#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */ -#define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos) -#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */ -#define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */ -#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos) -#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)) -#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */ -#define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos) -#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */ -#define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos) -#define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */ - -/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */ -#define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */ - -#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */ -#define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos) -#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */ -#define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos) -#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */ -#define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos) -#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */ -#define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos) -#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */ -#define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos) -#define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */ - -/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ - __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ - __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ - __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ - __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ - __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ - __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ - __I uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ - __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ - __I uint8_t :1; /*!< bit: 4 Reserved */ - __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ - __I uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */ -#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */ - -#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */ -#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */ -#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */ -#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos) -#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)) -#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */ -#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */ -#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */ -#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) -#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)) -#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */ -#define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos) -#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */ -#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos) -#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */ -#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos) -#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */ -#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos) -#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)) -#define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */ - -/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ - __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ - __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ - __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ - __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ - __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ - __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */ -#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */ - -#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos) -#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos) -#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos) -#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)) -#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */ -#define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos) -#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */ -#define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos) -#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */ -#define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos) -#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */ -#define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos) -#define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */ - -/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ -#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - -#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos) -#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)) -#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) -#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)) -#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos) -#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos) -#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos) -#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */ -#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos) -#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)) -#define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */ - -/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ - uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */ -#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */ - -#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */ -#define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos) -#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */ -#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos) -#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */ -#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos) -#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)) -#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */ -#define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos) -#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */ -#define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos) -#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */ -#define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos) -#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */ -#define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos) -#define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */ - -/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_EPINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */ -#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - -#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos) -#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)) -#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos) -#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)) -#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */ -#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos) -#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos) -#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos) -#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */ -#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos) -#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)) -#define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */ - -/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_PINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */ -#define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */ - -#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos) -#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos) -#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */ -#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos) -#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)) -#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */ -#define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos) -#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */ -#define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos) -#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */ -#define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos) -#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */ -#define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos) -#define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */ - -/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DEVICE_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - -#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */ -#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos) -#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)) -#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */ - -/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_HOST_ADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - -#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */ -#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos) -#define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)) -#define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */ - -/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_DEVICE_PCKSIZE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - -#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */ -#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) -#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)) -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */ -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) -#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)) -#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */ -#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos) -#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)) -#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */ -#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) -#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */ - -/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} USB_HOST_PCKSIZE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */ - -#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */ -#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) -#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)) -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */ -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) -#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)) -#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */ -#define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos) -#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)) -#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */ -#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) -#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */ - -/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_DEVICE_EXTREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */ - -#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */ -#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos) -#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)) -#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */ -#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos) -#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)) -#define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */ - -/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_EXTREG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */ - -#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */ -#define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos) -#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)) -#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */ -#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos) -#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)) -#define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */ - -/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_DEVICE_STATUS_BK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - -#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */ -#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos) -#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */ -#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) -#define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */ - -/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_BK_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */ - -#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */ -#define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos) -#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */ -#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos) -#define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */ - -/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ - uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_CTRL_PIPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */ -#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */ - -#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */ -#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos) -#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)) -#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */ -#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos) -#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)) -#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */ -#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos) -#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)) -#define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */ - -/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ - uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ - uint16_t PIDER:1; /*!< bit: 2 PID Error */ - uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ - uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ - uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} USB_HOST_STATUS_PIPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */ - -#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */ -#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos) -#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */ -#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos) -#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */ -#define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos) -#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */ -#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos) -#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */ -#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos) -#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */ -#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos) -#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)) -#define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */ - -/** \brief UsbDeviceDescBank SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ - __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - RoReg8 Reserved1[0x5]; -} UsbDeviceDescBank; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbHostDescBank SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ - __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ - __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ - RoReg8 Reserved1[0x1]; - __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ - __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ -} UsbHostDescBank; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbDeviceEndpoint hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ - RoReg8 Reserved1[0x3]; - __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ - __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ - __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ - __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ - __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - RoReg8 Reserved2[0x16]; -} UsbDeviceEndpoint; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief UsbHostPipe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ - RoReg8 Reserved1[0x2]; - __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ - __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ - __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ - __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ - __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ - __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ - __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ - RoReg8 Reserved2[0x16]; -} UsbHostPipe; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_DEVICE APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Device */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ - __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ - RoReg8 Reserved3[0x1]; - __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ - RoReg8 Reserved5[0x2]; - __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ -} UsbDevice; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_HOST hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Host */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ - __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ - RoReg8 Reserved3[0x1]; - __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ - __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ - RoReg8 Reserved5[0x1]; - __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ -} UsbHost; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_DEVICE Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Device */ - UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ -} UsbDeviceDescriptor; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief USB_HOST Descriptor SRAM registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { /* USB is Host */ - UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ -} UsbHostDescriptor; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#define SECTION_USB_DESCRIPTOR - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ - UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ -} Usb; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_USB_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h deleted file mode 100644 index bb4f4107191..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h +++ /dev/null @@ -1,303 +0,0 @@ -/** - * \file - * - * \brief Component description for WDT - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_WDT_COMPONENT_ -#define _SAMR21_WDT_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR WDT */ -/* ========================================================================== */ -/** \addtogroup SAMR21_WDT Watchdog Timer */ -/*@{*/ - -#define WDT_U2203 -#define REV_WDT 0x200 - -/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */ -#define WDT_CTRL_RESETVALUE 0x00ul /**< \brief (WDT_CTRL reset_value) Control */ - -#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */ -#define WDT_CTRL_ENABLE (0x1ul << WDT_CTRL_ENABLE_Pos) -#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */ -#define WDT_CTRL_WEN (0x1ul << WDT_CTRL_WEN_Pos) -#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */ -#define WDT_CTRL_ALWAYSON (0x1ul << WDT_CTRL_ALWAYSON_Pos) -#define WDT_CTRL_MASK 0x86ul /**< \brief (WDT_CTRL) MASK Register */ - -/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ - uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CONFIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */ -#define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */ - -#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */ -#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)) -#define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ -#define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ -#define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ -#define WDT_CONFIG_PER_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ -#define WDT_CONFIG_PER_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ -#define WDT_CONFIG_PER_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ -#define WDT_CONFIG_PER_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ -#define WDT_CONFIG_PER_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ -#define WDT_CONFIG_PER_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ -#define WDT_CONFIG_PER_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ -#define WDT_CONFIG_PER_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ -#define WDT_CONFIG_PER_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ -#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos) -#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */ -#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)) -#define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ -#define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ -#define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ -#define WDT_CONFIG_WINDOW_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ -#define WDT_CONFIG_WINDOW_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ -#define WDT_CONFIG_WINDOW_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ -#define WDT_CONFIG_WINDOW_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ -#define WDT_CONFIG_WINDOW_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ -#define WDT_CONFIG_WINDOW_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ -#define WDT_CONFIG_WINDOW_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ -#define WDT_CONFIG_WINDOW_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ -#define WDT_CONFIG_WINDOW_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ -#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos) -#define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */ - -/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_EWCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */ -#define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */ - -#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */ -#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)) -#define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_1K_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_2K_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_4K_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_8K_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_16K_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */ -#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos) -#define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */ - -/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */ -#define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */ - -#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */ -#define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos) -#define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */ - -/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */ -#define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */ - -#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */ -#define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos) -#define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */ - -/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t EW:1; /*!< bit: 0 Early Warning */ - __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */ -#define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */ -#define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos) -#define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */ - -/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */ -#define WDT_STATUS_RESETVALUE 0x00ul /**< \brief (WDT_STATUS reset_value) Status */ - -#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */ -#define WDT_STATUS_SYNCBUSY (0x1ul << WDT_STATUS_SYNCBUSY_Pos) -#define WDT_STATUS_MASK 0x80ul /**< \brief (WDT_STATUS) MASK Register */ - -/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} WDT_CLEAR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */ -#define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */ - -#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */ -#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos) -#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)) -#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */ -#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) -#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */ - -/** \brief WDT hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ - __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ - RoReg8 Reserved1[0x1]; - __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ -} Wdt; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMR21_WDT_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h deleted file mode 100644 index 18d441ec3ac..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief Instance description for AC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_AC_INSTANCE_ -#define _SAMR21_AC_INSTANCE_ - -/* ========== Register definition for AC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */ -#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */ -#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */ -#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */ -#else -#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */ -#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */ -#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */ -#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AC peripheral ========== */ -#define AC_CMP_NUM 2 // Number of comparators -#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog -#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC_NUM_CMP 2 -#define AC_PAIRS 1 // Number of pairs of comparators - -#endif /* _SAMR21_AC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_adc.h deleted file mode 100644 index 793da7b6087..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_adc.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * \file - * - * \brief Instance description for ADC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_ADC_INSTANCE_ -#define _SAMR21_ADC_INSTANCE_ - -/* ========== Register definition for ADC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */ -#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */ -#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */ -#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */ -#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */ -#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */ -#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */ -#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */ -#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */ -#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */ -#else -#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */ -#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */ -#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */ -#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */ -#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */ -#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */ -#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */ -#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */ -#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */ -#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for ADC peripheral ========== */ -#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger -#define ADC_EXTCHANNEL_MSB 19 // Number of external channels -#define ADC_GCLK_ID 30 // Index of Generic Clock -#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield -#define ADC_RESULT_MSB 15 // Size of Result - -#endif /* _SAMR21_ADC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dmac.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dmac.h deleted file mode 100644 index f9f9b9c9728..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dmac.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for DMAC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_DMAC_INSTANCE_ -#define _SAMR21_DMAC_INSTANCE_ - -/* ========== Register definition for DMAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_QOSCTRL (0x4100480EU) /**< \brief (DMAC) QOS Control */ -#define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */ -#else -#define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */ -#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DMAC peripheral ========== */ -#define DMAC_CH_BITS 4 // Number of bits to select channel -#define DMAC_CH_NUM 12 // Number of channels -#define DMAC_CLK_AHB_ID 5 // AHB clock index -#define DMAC_EVIN_NUM 4 // Number of input events -#define DMAC_EVOUT_NUM 4 // Number of output events -#define DMAC_LVL_BITS 2 // Number of bit to select level priority -#define DMAC_LVL_NUM 4 // Enable priority level number -#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source -#define DMAC_TRIG_NUM 45 // Number of peripheral triggers - -#endif /* _SAMR21_DMAC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dsu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dsu.h deleted file mode 100644 index ec940c1c895..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dsu.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * \file - * - * \brief Instance description for DSU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_DSU_INSTANCE_ -#define _SAMR21_DSU_INSTANCE_ - -/* ========== Register definition for DSU peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */ -#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ -#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ -#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ -#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ -#else -#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */ -#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ -#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ -#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ -#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DSU peripheral ========== */ -#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register - -#endif /* _SAMR21_DSU_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_eic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_eic.h deleted file mode 100644 index 4e9823cf1c4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_eic.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - * \file - * - * \brief Instance description for EIC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_EIC_INSTANCE_ -#define _SAMR21_EIC_INSTANCE_ - -/* ========== Register definition for EIC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control */ -#define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status */ -#define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */ -#define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ -#define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-Up Enable */ -#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Configuration 1 */ -#else -#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */ -#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */ -#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */ -#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ -#define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */ -#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Configuration 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EIC peripheral ========== */ -#define EIC_CONFIG_NUM 2 // Number of CONFIG registers -#define EIC_GCLK_ID 5 // Index of Generic Clock - -#endif /* _SAMR21_EIC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_evsys.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_evsys.h deleted file mode 100644 index 34974ff3673..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_evsys.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - * \file - * - * \brief Instance description for EVSYS - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_EVSYS_INSTANCE_ -#define _SAMR21_EVSYS_INSTANCE_ - -/* ========== Register definition for EVSYS peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EVSYS_CTRL (0x42000400U) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHANNEL (0x42000404U) /**< \brief (EVSYS) Channel */ -#define REG_EVSYS_USER (0x42000408U) /**< \brief (EVSYS) User Multiplexer */ -#define REG_EVSYS_CHSTATUS (0x4200040CU) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#else -#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404U) /**< \brief (EVSYS) Channel */ -#define REG_EVSYS_USER (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */ -#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CU) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EVSYS peripheral ========== */ -#define EVSYS_CHANNELS 12 // Number of Channels -#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel -#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1 -#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators -#define EVSYS_GCLK_ID_0 7 -#define EVSYS_GCLK_ID_1 8 -#define EVSYS_GCLK_ID_2 9 -#define EVSYS_GCLK_ID_3 10 -#define EVSYS_GCLK_ID_4 11 -#define EVSYS_GCLK_ID_5 12 -#define EVSYS_GCLK_ID_6 13 -#define EVSYS_GCLK_ID_7 14 -#define EVSYS_GCLK_ID_8 15 -#define EVSYS_GCLK_ID_9 16 -#define EVSYS_GCLK_ID_10 17 -#define EVSYS_GCLK_ID_11 18 -#define EVSYS_GCLK_ID_LSB 7 -#define EVSYS_GCLK_ID_MSB 18 -#define EVSYS_GCLK_ID_SIZE 12 -#define EVSYS_GENERATORS 73 // Total Number of Event Generators -#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator -#define EVSYS_USERS 29 // Total Number of Event Users -#define EVSYS_USERS_BITS 5 // Number of bits to select Event User - -// GENERATORS -#define EVSYS_ID_GEN_RTC_CMP_0 1 -#define EVSYS_ID_GEN_RTC_CMP_1 2 -#define EVSYS_ID_GEN_RTC_OVF 3 -#define EVSYS_ID_GEN_RTC_PER_0 4 -#define EVSYS_ID_GEN_RTC_PER_1 5 -#define EVSYS_ID_GEN_RTC_PER_2 6 -#define EVSYS_ID_GEN_RTC_PER_3 7 -#define EVSYS_ID_GEN_RTC_PER_4 8 -#define EVSYS_ID_GEN_RTC_PER_5 9 -#define EVSYS_ID_GEN_RTC_PER_6 10 -#define EVSYS_ID_GEN_RTC_PER_7 11 -#define EVSYS_ID_GEN_EIC_EXTINT_0 12 -#define EVSYS_ID_GEN_EIC_EXTINT_1 13 -#define EVSYS_ID_GEN_EIC_EXTINT_2 14 -#define EVSYS_ID_GEN_EIC_EXTINT_3 15 -#define EVSYS_ID_GEN_EIC_EXTINT_4 16 -#define EVSYS_ID_GEN_EIC_EXTINT_5 17 -#define EVSYS_ID_GEN_EIC_EXTINT_6 18 -#define EVSYS_ID_GEN_EIC_EXTINT_7 19 -#define EVSYS_ID_GEN_EIC_EXTINT_8 20 -#define EVSYS_ID_GEN_EIC_EXTINT_9 21 -#define EVSYS_ID_GEN_EIC_EXTINT_10 22 -#define EVSYS_ID_GEN_EIC_EXTINT_11 23 -#define EVSYS_ID_GEN_EIC_EXTINT_12 24 -#define EVSYS_ID_GEN_EIC_EXTINT_13 25 -#define EVSYS_ID_GEN_EIC_EXTINT_14 26 -#define EVSYS_ID_GEN_EIC_EXTINT_15 27 -#define EVSYS_ID_GEN_EIC_EXTINT_16 28 -#define EVSYS_ID_GEN_EIC_EXTINT_17 29 -#define EVSYS_ID_GEN_DMAC_CH_0 30 -#define EVSYS_ID_GEN_DMAC_CH_1 31 -#define EVSYS_ID_GEN_DMAC_CH_2 32 -#define EVSYS_ID_GEN_DMAC_CH_3 33 -#define EVSYS_ID_GEN_TCC0_OVF 34 -#define EVSYS_ID_GEN_TCC0_TRG 35 -#define EVSYS_ID_GEN_TCC0_CNT 36 -#define EVSYS_ID_GEN_TCC0_MCX_0 37 -#define EVSYS_ID_GEN_TCC0_MCX_1 38 -#define EVSYS_ID_GEN_TCC0_MCX_2 39 -#define EVSYS_ID_GEN_TCC0_MCX_3 40 -#define EVSYS_ID_GEN_TCC1_OVF 41 -#define EVSYS_ID_GEN_TCC1_TRG 42 -#define EVSYS_ID_GEN_TCC1_CNT 43 -#define EVSYS_ID_GEN_TCC1_MCX_0 44 -#define EVSYS_ID_GEN_TCC1_MCX_1 45 -#define EVSYS_ID_GEN_TCC2_OVF 46 -#define EVSYS_ID_GEN_TCC2_TRG 47 -#define EVSYS_ID_GEN_TCC2_CNT 48 -#define EVSYS_ID_GEN_TCC2_MCX_0 49 -#define EVSYS_ID_GEN_TCC2_MCX_1 50 -#define EVSYS_ID_GEN_TC3_OVF 51 -#define EVSYS_ID_GEN_TC3_MCX_0 52 -#define EVSYS_ID_GEN_TC3_MCX_1 53 -#define EVSYS_ID_GEN_TC4_OVF 54 -#define EVSYS_ID_GEN_TC4_MCX_0 55 -#define EVSYS_ID_GEN_TC4_MCX_1 56 -#define EVSYS_ID_GEN_TC5_OVF 57 -#define EVSYS_ID_GEN_TC5_MCX_0 58 -#define EVSYS_ID_GEN_TC5_MCX_1 59 -#define EVSYS_ID_GEN_TC6_OVF 60 -#define EVSYS_ID_GEN_TC6_MCX_0 61 -#define EVSYS_ID_GEN_TC6_MCX_1 62 -#define EVSYS_ID_GEN_TC7_OVF 63 -#define EVSYS_ID_GEN_TC7_MCX_0 64 -#define EVSYS_ID_GEN_TC7_MCX_1 65 -#define EVSYS_ID_GEN_ADC_RESRDY 66 -#define EVSYS_ID_GEN_ADC_WINMON 67 -#define EVSYS_ID_GEN_AC_COMP_0 68 -#define EVSYS_ID_GEN_AC_COMP_1 69 -#define EVSYS_ID_GEN_AC_WIN_0 70 -#define EVSYS_ID_GEN_DAC_EMPTY 71 -#define EVSYS_ID_GEN_PTC_EOC 72 -#define EVSYS_ID_GEN_PTC_WCOMP 73 - -// USERS -#define EVSYS_ID_USER_DMAC_CH_0 0 -#define EVSYS_ID_USER_DMAC_CH_1 1 -#define EVSYS_ID_USER_DMAC_CH_2 2 -#define EVSYS_ID_USER_DMAC_CH_3 3 -#define EVSYS_ID_USER_TCC0_EV_0 4 -#define EVSYS_ID_USER_TCC0_EV_1 5 -#define EVSYS_ID_USER_TCC0_MC_0 6 -#define EVSYS_ID_USER_TCC0_MC_1 7 -#define EVSYS_ID_USER_TCC0_MC_2 8 -#define EVSYS_ID_USER_TCC0_MC_3 9 -#define EVSYS_ID_USER_TCC1_EV_0 10 -#define EVSYS_ID_USER_TCC1_EV_1 11 -#define EVSYS_ID_USER_TCC1_MC_0 12 -#define EVSYS_ID_USER_TCC1_MC_1 13 -#define EVSYS_ID_USER_TCC2_EV_0 14 -#define EVSYS_ID_USER_TCC2_EV_1 15 -#define EVSYS_ID_USER_TCC2_MC_0 16 -#define EVSYS_ID_USER_TCC2_MC_1 17 -#define EVSYS_ID_USER_TC3_EVU 18 -#define EVSYS_ID_USER_TC4_EVU 19 -#define EVSYS_ID_USER_TC5_EVU 20 -#define EVSYS_ID_USER_TC6_EVU 21 -#define EVSYS_ID_USER_TC7_EVU 22 -#define EVSYS_ID_USER_ADC_START 23 -#define EVSYS_ID_USER_ADC_SYNC 24 -#define EVSYS_ID_USER_AC_SOC_0 25 -#define EVSYS_ID_USER_AC_SOC_1 26 -#define EVSYS_ID_USER_DAC_START 27 -#define EVSYS_ID_USER_PTC_STCONV 28 - -#endif /* _SAMR21_EVSYS_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h deleted file mode 100644 index 96fd76c35f0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - * \file - * - * \brief Instance description for GCLK - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_GCLK_INSTANCE_ -#define _SAMR21_GCLK_INSTANCE_ - -/* ========== Register definition for GCLK peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */ -#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */ -#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ -#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ -#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ -#else -#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */ -#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */ -#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ -#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ -#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 -#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators -#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 -#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 -#define GCLK_NUM 37 // Number of Generic Clock Users -#define GCLK_SOURCE_DFLL48M 7 -#define GCLK_SOURCE_FDPLL 8 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 -#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC8M 6 -#define GCLK_SOURCE_OSC32K 4 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 5 - -#endif /* _SAMR21_GCLK_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_mtb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_mtb.h deleted file mode 100644 index de10cc812aa..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_mtb.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * \file - * - * \brief Instance description for MTB - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_MTB_INSTANCE_ -#define _SAMR21_MTB_INSTANCE_ - -/* ========== Register definition for MTB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) CoreSight */ -#else -#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) CoreSight */ -#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) CoreSight */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAMR21_MTB_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h deleted file mode 100644 index 4f95860e732..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * \file - * - * \brief Instance description for NVMCTRL - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_NVMCTRL_INSTANCE_ -#define _SAMR21_NVMCTRL_INSTANCE_ - -/* ========== Register definition for NVMCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */ -#else -#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for NVMCTRL peripheral ========== */ -#define NVMCTRL_AUX0_ADDRESS 0x00804000 -#define NVMCTRL_AUX1_ADDRESS 0x00806000 -#define NVMCTRL_AUX2_ADDRESS 0x00808000 -#define NVMCTRL_AUX3_ADDRESS 0x0080A000 -#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register -#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 -#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGES 4096 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 -#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 -#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 -#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 -#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF - -#endif /* _SAMR21_NVMCTRL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac0.h deleted file mode 100644 index 4abcd8def05..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac0.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC0 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_PAC0_INSTANCE_ -#define _SAMR21_PAC0_INSTANCE_ - -/* ========== Register definition for PAC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear */ -#define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set */ -#else -#define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */ -#define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC0 peripheral ========== */ -#define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset - -#endif /* _SAMR21_PAC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac1.h deleted file mode 100644 index c7761a2df68..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac1.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC1 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_PAC1_INSTANCE_ -#define _SAMR21_PAC1_INSTANCE_ - -/* ========== Register definition for PAC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear */ -#define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set */ -#else -#define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */ -#define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC1 peripheral ========== */ -#define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset - -#endif /* _SAMR21_PAC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac2.h deleted file mode 100644 index cc28478ad91..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac2.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC2 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_PAC2_INSTANCE_ -#define _SAMR21_PAC2_INSTANCE_ - -/* ========== Register definition for PAC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear */ -#define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set */ -#else -#define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */ -#define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC2 peripheral ========== */ -#define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset - -#endif /* _SAMR21_PAC2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h deleted file mode 100644 index c7d06c6c620..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief Instance description for PM - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_PM_INSTANCE_ -#define _SAMR21_PM_INSTANCE_ - -/* ========== Register definition for PM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */ -#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */ -#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */ -#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */ -#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */ -#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */ -#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */ -#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */ -#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */ -#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */ -#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */ -#else -#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */ -#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */ -#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */ -#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */ -#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */ -#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */ -#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */ -#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */ -#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */ -#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */ -#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PM peripheral ========== */ -#define PM_CTRL_MCSEL_DFLL48M 3 -#define PM_CTRL_MCSEL_GCLK 0 -#define PM_CTRL_MCSEL_OSC8M 1 -#define PM_CTRL_MCSEL_XOSC 2 -#define PM_PM_CLK_APB_NUM 2 - -#endif /* _SAMR21_PM_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_port.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_port.h deleted file mode 100644 index b258ce15059..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_port.h +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Instance description for PORT - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_PORT_INSTANCE_ -#define _SAMR21_PORT_INSTANCE_ - -/* ========== Register definition for PORT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */ -#define REG_PORT_DIR2 (0x41004500U) /**< \brief (PORT) Data Direction 2 */ -#define REG_PORT_DIRCLR2 (0x41004504U) /**< \brief (PORT) Data Direction Clear 2 */ -#define REG_PORT_DIRSET2 (0x41004508U) /**< \brief (PORT) Data Direction Set 2 */ -#define REG_PORT_DIRTGL2 (0x4100450CU) /**< \brief (PORT) Data Direction Toggle 2 */ -#define REG_PORT_OUT2 (0x41004510U) /**< \brief (PORT) Data Output Value 2 */ -#define REG_PORT_OUTCLR2 (0x41004514U) /**< \brief (PORT) Data Output Value Clear 2 */ -#define REG_PORT_OUTSET2 (0x41004518U) /**< \brief (PORT) Data Output Value Set 2 */ -#define REG_PORT_OUTTGL2 (0x4100451CU) /**< \brief (PORT) Data Output Value Toggle 2 */ -#define REG_PORT_IN2 (0x41004520U) /**< \brief (PORT) Data Input Value 2 */ -#define REG_PORT_CTRL2 (0x41004524U) /**< \brief (PORT) Control 2 */ -#define REG_PORT_WRCONFIG2 (0x41004528U) /**< \brief (PORT) Write Configuration 2 */ -#define REG_PORT_PMUX2 (0x41004530U) /**< \brief (PORT) Peripheral Multiplexing 2 */ -#define REG_PORT_PINCFG2 (0x41004540U) /**< \brief (PORT) Pin Configuration 2 */ -#else -#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */ -#define REG_PORT_DIR2 (*(RwReg *)0x41004500U) /**< \brief (PORT) Data Direction 2 */ -#define REG_PORT_DIRCLR2 (*(RwReg *)0x41004504U) /**< \brief (PORT) Data Direction Clear 2 */ -#define REG_PORT_DIRSET2 (*(RwReg *)0x41004508U) /**< \brief (PORT) Data Direction Set 2 */ -#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100450CU) /**< \brief (PORT) Data Direction Toggle 2 */ -#define REG_PORT_OUT2 (*(RwReg *)0x41004510U) /**< \brief (PORT) Data Output Value 2 */ -#define REG_PORT_OUTCLR2 (*(RwReg *)0x41004514U) /**< \brief (PORT) Data Output Value Clear 2 */ -#define REG_PORT_OUTSET2 (*(RwReg *)0x41004518U) /**< \brief (PORT) Data Output Value Set 2 */ -#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100451CU) /**< \brief (PORT) Data Output Value Toggle 2 */ -#define REG_PORT_IN2 (*(RoReg *)0x41004520U) /**< \brief (PORT) Data Input Value 2 */ -#define REG_PORT_CTRL2 (*(RwReg *)0x41004524U) /**< \brief (PORT) Control 2 */ -#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41004528U) /**< \brief (PORT) Write Configuration 2 */ -#define REG_PORT_PMUX2 (*(RwReg *)0x41004530U) /**< \brief (PORT) Peripheral Multiplexing 2 */ -#define REG_PORT_PINCFG2 (*(RwReg *)0x41004540U) /**< \brief (PORT) Pin Configuration 2 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PORT peripheral ========== */ -#define PORT_BITS 84 // Number of PORT pins -#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins -#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins -#define PORT_DRVSTR 1 // DRVSTR supported -#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins -#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins -#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins -#define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins -#define PORT_ODRAIN 0 // ODRAIN supported -#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins -#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins -#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins -#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins -#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins -#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins -#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins -#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins -#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins -#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins -#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins -#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins -#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins -#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins -#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins -#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins -#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins -#define PORT_SLEWLIM 0 // SLEWLIM supported -#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins -#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins - -#endif /* _SAMR21_PORT_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h deleted file mode 100644 index 60cdb6b2e42..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \file - * - * \brief Instance description for RFCTRL - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_RFCTRL_INSTANCE_ -#define _SAMR21_RFCTRL_INSTANCE_ - -/* ========== Register definition for RFCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RFCTRL_FECFG (0x42005400U) /**< \brief (RFCTRL) Front-end control bus configuration */ -#else -#define REG_RFCTRL_FECFG (*(RwReg16*)0x42005400U) /**< \brief (RFCTRL) Front-end control bus configuration */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RFCTRL peripheral ========== */ -#define RFCTRL_FBUSMSB 5 - -#endif /* _SAMR21_RFCTRL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rtc.h deleted file mode 100644 index 288e1ab047f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rtc.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * \file - * - * \brief Instance description for RTC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_RTC_INSTANCE_ -#define _SAMR21_RTC_INSTANCE_ - -/* ========== Register definition for RTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */ -#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */ -#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */ -#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */ -#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */ -#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#else -#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */ -#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */ -#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */ -#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */ -#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */ -#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RTC peripheral ========== */ -#define RTC_ALARM_NUM 1 // Number of Alarms -#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators -#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators -#define RTC_GCLK_ID 4 // Index of Generic Clock -#define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete) -#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete) -#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete) - -#endif /* _SAMR21_RTC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h deleted file mode 100644 index f8dd7396cc7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h +++ /dev/null @@ -1,165 +0,0 @@ -/** - * \file - * - * \brief Instance description for SBMATRIX - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SBMATRIX_INSTANCE_ -#define _SAMR21_SBMATRIX_INSTANCE_ - -/* ========== Register definition for SBMATRIX peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SBMATRIX_PRAS0 (0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */ -#define REG_SBMATRIX_PRBS0 (0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */ -#define REG_SBMATRIX_PRAS1 (0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */ -#define REG_SBMATRIX_PRBS1 (0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */ -#define REG_SBMATRIX_PRAS2 (0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */ -#define REG_SBMATRIX_PRBS2 (0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */ -#define REG_SBMATRIX_PRAS3 (0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */ -#define REG_SBMATRIX_PRBS3 (0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */ -#define REG_SBMATRIX_PRAS4 (0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */ -#define REG_SBMATRIX_PRBS4 (0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */ -#define REG_SBMATRIX_PRAS5 (0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */ -#define REG_SBMATRIX_PRBS5 (0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */ -#define REG_SBMATRIX_PRAS6 (0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */ -#define REG_SBMATRIX_PRBS6 (0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */ -#define REG_SBMATRIX_PRAS7 (0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */ -#define REG_SBMATRIX_PRBS7 (0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */ -#define REG_SBMATRIX_PRAS8 (0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */ -#define REG_SBMATRIX_PRBS8 (0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */ -#define REG_SBMATRIX_PRAS9 (0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */ -#define REG_SBMATRIX_PRBS9 (0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */ -#define REG_SBMATRIX_PRAS10 (0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */ -#define REG_SBMATRIX_PRBS10 (0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */ -#define REG_SBMATRIX_PRAS11 (0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */ -#define REG_SBMATRIX_PRBS11 (0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */ -#define REG_SBMATRIX_PRAS12 (0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */ -#define REG_SBMATRIX_PRBS12 (0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */ -#define REG_SBMATRIX_PRAS13 (0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */ -#define REG_SBMATRIX_PRBS13 (0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */ -#define REG_SBMATRIX_PRAS14 (0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */ -#define REG_SBMATRIX_PRBS14 (0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */ -#define REG_SBMATRIX_PRAS15 (0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */ -#define REG_SBMATRIX_PRBS15 (0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */ -#define REG_SBMATRIX_SFR0 (0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */ -#define REG_SBMATRIX_SFR1 (0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */ -#define REG_SBMATRIX_SFR2 (0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */ -#define REG_SBMATRIX_SFR3 (0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */ -#define REG_SBMATRIX_SFR4 (0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */ -#define REG_SBMATRIX_SFR5 (0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */ -#define REG_SBMATRIX_SFR6 (0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */ -#define REG_SBMATRIX_SFR7 (0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */ -#define REG_SBMATRIX_SFR8 (0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */ -#define REG_SBMATRIX_SFR9 (0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */ -#define REG_SBMATRIX_SFR10 (0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */ -#define REG_SBMATRIX_SFR11 (0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */ -#define REG_SBMATRIX_SFR12 (0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */ -#define REG_SBMATRIX_SFR13 (0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */ -#define REG_SBMATRIX_SFR14 (0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */ -#define REG_SBMATRIX_SFR15 (0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */ -#else -#define REG_SBMATRIX_PRAS0 (*(RwReg *)0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */ -#define REG_SBMATRIX_PRBS0 (*(RwReg *)0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */ -#define REG_SBMATRIX_PRAS1 (*(RwReg *)0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */ -#define REG_SBMATRIX_PRBS1 (*(RwReg *)0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */ -#define REG_SBMATRIX_PRAS2 (*(RwReg *)0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */ -#define REG_SBMATRIX_PRBS2 (*(RwReg *)0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */ -#define REG_SBMATRIX_PRAS3 (*(RwReg *)0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */ -#define REG_SBMATRIX_PRBS3 (*(RwReg *)0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */ -#define REG_SBMATRIX_PRAS4 (*(RwReg *)0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */ -#define REG_SBMATRIX_PRBS4 (*(RwReg *)0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */ -#define REG_SBMATRIX_PRAS5 (*(RwReg *)0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */ -#define REG_SBMATRIX_PRBS5 (*(RwReg *)0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */ -#define REG_SBMATRIX_PRAS6 (*(RwReg *)0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */ -#define REG_SBMATRIX_PRBS6 (*(RwReg *)0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */ -#define REG_SBMATRIX_PRAS7 (*(RwReg *)0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */ -#define REG_SBMATRIX_PRBS7 (*(RwReg *)0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */ -#define REG_SBMATRIX_PRAS8 (*(RwReg *)0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */ -#define REG_SBMATRIX_PRBS8 (*(RwReg *)0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */ -#define REG_SBMATRIX_PRAS9 (*(RwReg *)0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */ -#define REG_SBMATRIX_PRBS9 (*(RwReg *)0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */ -#define REG_SBMATRIX_PRAS10 (*(RwReg *)0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */ -#define REG_SBMATRIX_PRBS10 (*(RwReg *)0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */ -#define REG_SBMATRIX_PRAS11 (*(RwReg *)0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */ -#define REG_SBMATRIX_PRBS11 (*(RwReg *)0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */ -#define REG_SBMATRIX_PRAS12 (*(RwReg *)0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */ -#define REG_SBMATRIX_PRBS12 (*(RwReg *)0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */ -#define REG_SBMATRIX_PRAS13 (*(RwReg *)0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */ -#define REG_SBMATRIX_PRBS13 (*(RwReg *)0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */ -#define REG_SBMATRIX_PRAS14 (*(RwReg *)0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */ -#define REG_SBMATRIX_PRBS14 (*(RwReg *)0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */ -#define REG_SBMATRIX_PRAS15 (*(RwReg *)0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */ -#define REG_SBMATRIX_PRBS15 (*(RwReg *)0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */ -#define REG_SBMATRIX_SFR0 (*(RwReg *)0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */ -#define REG_SBMATRIX_SFR1 (*(RwReg *)0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */ -#define REG_SBMATRIX_SFR2 (*(RwReg *)0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */ -#define REG_SBMATRIX_SFR3 (*(RwReg *)0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */ -#define REG_SBMATRIX_SFR4 (*(RwReg *)0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */ -#define REG_SBMATRIX_SFR5 (*(RwReg *)0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */ -#define REG_SBMATRIX_SFR6 (*(RwReg *)0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */ -#define REG_SBMATRIX_SFR7 (*(RwReg *)0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */ -#define REG_SBMATRIX_SFR8 (*(RwReg *)0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */ -#define REG_SBMATRIX_SFR9 (*(RwReg *)0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */ -#define REG_SBMATRIX_SFR10 (*(RwReg *)0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */ -#define REG_SBMATRIX_SFR11 (*(RwReg *)0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */ -#define REG_SBMATRIX_SFR12 (*(RwReg *)0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */ -#define REG_SBMATRIX_SFR13 (*(RwReg *)0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */ -#define REG_SBMATRIX_SFR14 (*(RwReg *)0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */ -#define REG_SBMATRIX_SFR15 (*(RwReg *)0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SBMATRIX peripheral ========== */ -#define SBMATRIX_DEFINED -/* ========== Instance parameters for SBMATRIX ========== */ -#define SBMATRIX_SLAVE_FLASH 0 -#define SBMATRIX_SLAVE_HPB0 1 -#define SBMATRIX_SLAVE_HPB1 2 -#define SBMATRIX_SLAVE_HPB2 3 -#define SBMATRIX_SLAVE_HMCRAMC0 4 -#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5 -#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6 -#define SBMATRIX_SLAVE_NUM 7 - -#define SBMATRIX_MASTER_CM0PLUS 0 -#define SBMATRIX_MASTER_DSU 1 -#define SBMATRIX_MASTER_DMAC 2 -#define SBMATRIX_MASTER_NUM 3 - -#endif /* _SAMR21_SBMATRIX_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h deleted file mode 100644 index 1849d435317..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM0 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SERCOM0_INSTANCE_ -#define _SAMR21_SERCOM0_INSTANCE_ - -/* ========== Register definition for SERCOM0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */ -#define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */ -#define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */ -#define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */ -#define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ -#else -#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */ -#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */ -#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */ -#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */ -#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM0 peripheral ========== */ -#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger -#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger -#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core -#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM0_INT_MSB 6 - -#endif /* _SAMR21_SERCOM0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h deleted file mode 100644 index 6c0674bc2e0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM1 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SERCOM1_INSTANCE_ -#define _SAMR21_SERCOM1_INSTANCE_ - -/* ========== Register definition for SERCOM1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */ -#define REG_SERCOM1_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */ -#define REG_SERCOM1_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */ -#define REG_SERCOM1_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (0x42000C28U) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */ -#define REG_SERCOM1_USART_DATA (0x42000C28U) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */ -#else -#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */ -#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */ -#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */ -#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */ -#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM1 peripheral ========== */ -#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger -#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger -#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core -#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM1_INT_MSB 6 - -#endif /* _SAMR21_SERCOM1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h deleted file mode 100644 index 517225b90c7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM2 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SERCOM2_INSTANCE_ -#define _SAMR21_SERCOM2_INSTANCE_ - -/* ========== Register definition for SERCOM2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */ -#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */ -#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */ -#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */ -#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */ -#else -#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */ -#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */ -#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */ -#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */ -#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM2 peripheral ========== */ -#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger -#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger -#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core -#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM2_INT_MSB 6 - -#endif /* _SAMR21_SERCOM2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h deleted file mode 100644 index 8f69e39808a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM3 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SERCOM3_INSTANCE_ -#define _SAMR21_SERCOM3_INSTANCE_ - -/* ========== Register definition for SERCOM3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */ -#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */ -#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */ -#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */ -#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */ -#else -#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */ -#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */ -#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */ -#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */ -#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM3 peripheral ========== */ -#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger -#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger -#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core -#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM3_INT_MSB 6 - -#endif /* _SAMR21_SERCOM3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h deleted file mode 100644 index 52497513dfc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM4 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SERCOM4_INSTANCE_ -#define _SAMR21_SERCOM4_INSTANCE_ - -/* ========== Register definition for SERCOM4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */ -#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */ -#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */ -#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */ -#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */ -#else -#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */ -#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */ -#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */ -#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */ -#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM4 peripheral ========== */ -#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger -#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger -#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core -#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM4_INT_MSB 6 - -#endif /* _SAMR21_SERCOM4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h deleted file mode 100644 index 12f9a889835..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM5 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SERCOM5_INSTANCE_ -#define _SAMR21_SERCOM5_INSTANCE_ - -/* ========== Register definition for SERCOM5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */ -#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */ -#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */ -#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_BAUD (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */ -#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */ -#else -#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */ -#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */ -#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */ -#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */ -#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM5 peripheral ========== */ -#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger -#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger -#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core -#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM5_INT_MSB 6 - -#endif /* _SAMR21_SERCOM5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h deleted file mode 100644 index d7757ad16c5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * \file - * - * \brief Instance description for SYSCTRL - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_SYSCTRL_INSTANCE_ -#define _SAMR21_SYSCTRL_INSTANCE_ - -/* ========== Register definition for SYSCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ -#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ -#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ -#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ -#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ -#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ -#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ -#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ -#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ -#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ -#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ -#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ -#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ -#define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ -#define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ -#define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ -#define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ -#else -#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ -#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ -#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ -#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ -#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ -#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ -#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ -#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ -#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ -#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ -#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ -#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ -#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ -#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ -#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ -#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ -#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SYSCTRL peripheral ========== */ -#define SYSCTRL_BGAP_CALIB_MSB 11 -#define SYSCTRL_BOD33_CALIB_MSB 5 -#define SYSCTRL_DFLL48M_COARSE_MSB 5 -#define SYSCTRL_DFLL48M_FINE_MSB 9 -#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 -#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL -#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 -#define SYSCTRL_POR33_ENTEST_MSB 1 -#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 -#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 -#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 -#define SYSCTRL_VREF_CONTROL_MSB 48 -#define SYSCTRL_VREF_STATUS_MSB 7 -#define SYSCTRL_VREG_LEVEL_MSB 2 -#define SYSCTRL_BOD12_VERSION 0x111 -#define SYSCTRL_BOD33_VERSION 0x111 -#define SYSCTRL_DFLL48M_VERSION 0x301 -#define SYSCTRL_FDPLL_VERSION 0x111 -#define SYSCTRL_OSCULP32K_VERSION 0x111 -#define SYSCTRL_OSC8M_VERSION 0x120 -#define SYSCTRL_OSC32K_VERSION 0x1101 -#define SYSCTRL_VREF_VERSION 0x200 -#define SYSCTRL_VREG_VERSION 0x201 -#define SYSCTRL_XOSC_VERSION 0x1111 -#define SYSCTRL_XOSC32K_VERSION 0x1111 - -#endif /* _SAMR21_SYSCTRL_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h deleted file mode 100644 index 987f85240bd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC3 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_TC3_INSTANCE_ -#define _SAMR21_TC3_INSTANCE_ - -/* ========== Register definition for TC3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */ -#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */ -#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */ -#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */ -#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */ -#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ -#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ -#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ -#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ -#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ -#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ -#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ -#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ -#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ -#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ -#else -#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */ -#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */ -#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */ -#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */ -#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */ -#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ -#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ -#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ -#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ -#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ -#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ -#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ -#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ -#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ -#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC3 peripheral ========== */ -#define TC3_CC8_NUM 2 // Number of 8-bit Counters -#define TC3_CC16_NUM 2 // Number of 16-bit Counters -#define TC3_CC32_NUM 2 // Number of 32-bit Counters -#define TC3_DITHERING_EXT 0 // Dithering feature implemented -#define TC3_DMAC_ID_MC_0 25 -#define TC3_DMAC_ID_MC_1 26 -#define TC3_DMAC_ID_MC_LSB 25 -#define TC3_DMAC_ID_MC_MSB 26 -#define TC3_DMAC_ID_MC_SIZE 2 -#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger -#define TC3_GCLK_ID 27 // Index of Generic Clock -#define TC3_MASTER 0 -#define TC3_OW_NUM 2 // Number of Output Waveforms -#define TC3_PERIOD_EXT 0 // Period feature implemented -#define TC3_SHADOW_EXT 0 // Shadow feature implemented - -#endif /* _SAMR21_TC3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h deleted file mode 100644 index 598dc7b9008..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC4 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_TC4_INSTANCE_ -#define _SAMR21_TC4_INSTANCE_ - -/* ========== Register definition for TC4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A */ -#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request */ -#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear */ -#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set */ -#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C */ -#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Control */ -#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control */ -#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */ -#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */ -#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */ -#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status */ -#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */ -#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ -#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ -#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */ -#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ -#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ -#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */ -#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */ -#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ -#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ -#else -#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */ -#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */ -#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */ -#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */ -#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */ -#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */ -#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */ -#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */ -#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */ -#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */ -#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */ -#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */ -#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ -#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ -#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */ -#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ -#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ -#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */ -#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */ -#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ -#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC4 peripheral ========== */ -#define TC4_CC8_NUM 2 // Number of 8-bit Counters -#define TC4_CC16_NUM 2 // Number of 16-bit Counters -#define TC4_CC32_NUM 2 // Number of 32-bit Counters -#define TC4_DITHERING_EXT 0 // Dithering feature implemented -#define TC4_DMAC_ID_MC_0 28 -#define TC4_DMAC_ID_MC_1 29 -#define TC4_DMAC_ID_MC_LSB 28 -#define TC4_DMAC_ID_MC_MSB 29 -#define TC4_DMAC_ID_MC_SIZE 2 -#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger -#define TC4_GCLK_ID 28 // Index of Generic Clock -#define TC4_MASTER 1 -#define TC4_OW_NUM 2 // Number of Output Waveforms -#define TC4_PERIOD_EXT 0 // Period feature implemented -#define TC4_SHADOW_EXT 0 // Shadow feature implemented - -#endif /* _SAMR21_TC4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h deleted file mode 100644 index 3d0518800bd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC5 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_TC5_INSTANCE_ -#define _SAMR21_TC5_INSTANCE_ - -/* ========== Register definition for TC5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */ -#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */ -#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */ -#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */ -#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */ -#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */ -#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */ -#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */ -#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */ -#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */ -#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */ -#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */ -#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ -#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ -#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */ -#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ -#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ -#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */ -#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */ -#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ -#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ -#else -#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */ -#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */ -#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */ -#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */ -#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */ -#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */ -#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */ -#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */ -#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */ -#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */ -#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */ -#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */ -#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ -#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ -#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */ -#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ -#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ -#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */ -#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */ -#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ -#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC5 peripheral ========== */ -#define TC5_CC8_NUM 2 // Number of 8-bit Counters -#define TC5_CC16_NUM 2 // Number of 16-bit Counters -#define TC5_CC32_NUM 2 // Number of 32-bit Counters -#define TC5_DITHERING_EXT 0 // Dithering feature implemented -#define TC5_DMAC_ID_MC_0 31 -#define TC5_DMAC_ID_MC_1 32 -#define TC5_DMAC_ID_MC_LSB 31 -#define TC5_DMAC_ID_MC_MSB 32 -#define TC5_DMAC_ID_MC_SIZE 2 -#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger -#define TC5_GCLK_ID 28 // Index of Generic Clock -#define TC5_MASTER 0 -#define TC5_OW_NUM 2 // Number of Output Waveforms -#define TC5_PERIOD_EXT 0 // Period feature implemented -#define TC5_SHADOW_EXT 0 // Shadow feature implemented - -#endif /* _SAMR21_TC5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h deleted file mode 100644 index 5912bfbc8d2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC0 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_TCC0_INSTANCE_ -#define _SAMR21_TCC0_INSTANCE_ - -/* ========== Register definition for TCC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ -#define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#else -#define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ -#define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC0 peripheral ========== */ -#define TCC0_CC_NUM 4 // Number of Compare/Capture units -#define TCC0_DITHERING 1 // Dithering feature implemented -#define TCC0_DMAC_ID_MC_0 14 -#define TCC0_DMAC_ID_MC_1 15 -#define TCC0_DMAC_ID_MC_2 16 -#define TCC0_DMAC_ID_MC_3 17 -#define TCC0_DMAC_ID_MC_LSB 14 -#define TCC0_DMAC_ID_MC_MSB 17 -#define TCC0_DMAC_ID_MC_SIZE 4 -#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger -#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented -#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1) -#define TCC0_GCLK_ID 26 // Index of Generic Clock -#define TCC0_OTMX 1 // Output Matrix feature implemented -#define TCC0_OW_NUM 8 // Number of Output Waveforms -#define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 -#define TCC0_SWAP 1 // DTI outputs swap feature implemented -#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAMR21_TCC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h deleted file mode 100644 index da2ff09f445..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC1 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_TCC1_INSTANCE_ -#define _SAMR21_TCC1_INSTANCE_ - -/* ========== Register definition for TCC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */ -#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */ -#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */ -#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */ -#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ -#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ -#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */ -#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */ -#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */ -#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ -#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ -#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ -#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */ -#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */ -#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */ -#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */ -#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */ -#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ -#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ -#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */ -#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ -#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */ -#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ -#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ -#else -#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */ -#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */ -#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */ -#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */ -#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ -#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ -#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */ -#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */ -#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */ -#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ -#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ -#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ -#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */ -#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */ -#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */ -#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */ -#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */ -#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ -#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ -#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */ -#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ -#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */ -#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ -#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC1 peripheral ========== */ -#define TCC1_CC_NUM 2 // Number of Compare/Capture units -#define TCC1_DITHERING 1 // Dithering feature implemented -#define TCC1_DMAC_ID_MC_0 19 -#define TCC1_DMAC_ID_MC_1 20 -#define TCC1_DMAC_ID_MC_LSB 19 -#define TCC1_DMAC_ID_MC_MSB 20 -#define TCC1_DMAC_ID_MC_SIZE 2 -#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger -#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented -#define TCC1_EXT 24 // Coding of implemented extended features -#define TCC1_GCLK_ID 26 // Index of Generic Clock -#define TCC1_OTMX 0 // Output Matrix feature implemented -#define TCC1_OW_NUM 4 // Number of Output Waveforms -#define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 -#define TCC1_SWAP 0 // DTI outputs swap feature implemented -#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAMR21_TCC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h deleted file mode 100644 index 6090fc62969..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC2 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_TCC2_INSTANCE_ -#define _SAMR21_TCC2_INSTANCE_ - -/* ========== Register definition for TCC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */ -#define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */ -#define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */ -#define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */ -#define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ -#define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */ -#define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Control */ -#define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */ -#define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */ -#define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */ -#define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */ -#define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ -#define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */ -#define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */ -#define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */ -#define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */ -#define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */ -#define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */ -#define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */ -#define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */ -#define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ -#define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ -#else -#define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */ -#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */ -#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */ -#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */ -#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ -#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */ -#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Control */ -#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */ -#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */ -#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */ -#define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */ -#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ -#define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */ -#define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */ -#define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */ -#define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */ -#define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */ -#define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */ -#define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */ -#define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */ -#define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ -#define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC2 peripheral ========== */ -#define TCC2_CC_NUM 2 // Number of Compare/Capture units -#define TCC2_DITHERING 0 // Dithering feature implemented -#define TCC2_DMAC_ID_MC_0 22 -#define TCC2_DMAC_ID_MC_1 23 -#define TCC2_DMAC_ID_MC_LSB 22 -#define TCC2_DMAC_ID_MC_MSB 23 -#define TCC2_DMAC_ID_MC_SIZE 2 -#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger -#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented -#define TCC2_EXT 0 // Coding of implemented extended features -#define TCC2_GCLK_ID 27 // Index of Generic Clock -#define TCC2_OTMX 0 // Output Matrix feature implemented -#define TCC2_OW_NUM 2 // Number of Output Waveforms -#define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 -#define TCC2_SWAP 0 // DTI outputs swap feature implemented -#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAMR21_TCC2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_usb.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_usb.h deleted file mode 100644 index 3890af57594..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_usb.h +++ /dev/null @@ -1,344 +0,0 @@ -/** - * \file - * - * \brief Instance description for USB - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_USB_INSTANCE_ -#define _SAMR21_USB_INSTANCE_ - -/* ========== Register definition for USB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USB_CTRLA (0x41005000U) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (0x41005002U) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_QOSCTRL (0x41005003U) /**< \brief (USB) USB Quality Of Service */ -#define REG_USB_FSMSTATUS (0x4100500DU) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (0x41005024U) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (0x41005028U) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (0x41005008U) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (0x4100500AU) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (0x4100500CU) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#define REG_USB_HOST_CTRLB (0x41005008U) /**< \brief (USB) HOST Control B */ -#define REG_USB_HOST_HSOFC (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */ -#define REG_USB_HOST_STATUS (0x4100500CU) /**< \brief (USB) HOST Status */ -#define REG_USB_HOST_FNUM (0x41005010U) /**< \brief (USB) HOST Host Frame Number */ -#define REG_USB_HOST_FLENHIGH (0x41005012U) /**< \brief (USB) HOST Host Frame Length */ -#define REG_USB_HOST_INTENCLR (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ -#define REG_USB_HOST_INTENSET (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ -#define REG_USB_HOST_INTFLAG (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */ -#define REG_USB_HOST_PINTSMRY (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ -#define REG_USB_HOST_PIPE_PCFG0 (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ -#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ -#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ -#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ -#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ -#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ -#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ -#define REG_USB_HOST_PIPE_PCFG1 (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ -#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ -#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ -#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ -#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ -#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ -#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ -#define REG_USB_HOST_PIPE_PCFG2 (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ -#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ -#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ -#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ -#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ -#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ -#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ -#define REG_USB_HOST_PIPE_PCFG3 (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ -#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ -#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ -#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ -#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ -#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ -#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ -#define REG_USB_HOST_PIPE_PCFG4 (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ -#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ -#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ -#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ -#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ -#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ -#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ -#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ -#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ -#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ -#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ -#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ -#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ -#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ -#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ -#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ -#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ -#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ -#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ -#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ -#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ -#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ -#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ -#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ -#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ -#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ -#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ -#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ -#else -#define REG_USB_CTRLA (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003U) /**< \brief (USB) USB Quality Of Service */ -#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (*(RwReg *)0x41005024U) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */ -#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */ -#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */ -#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */ -#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */ -#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ -#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ -#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */ -#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ -#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ -#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ -#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ -#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ -#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ -#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ -#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ -#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ -#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ -#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ -#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ -#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ -#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ -#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ -#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ -#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ -#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ -#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ -#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ -#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ -#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ -#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ -#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ -#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ -#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ -#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ -#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ -#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ -#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ -#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ -#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ -#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ -#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ -#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ -#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ -#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ -#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ -#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ -#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ -#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ -#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ -#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ -#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ -#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ -#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ -#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ -#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ -#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ -#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ -#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ -#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ -#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ -#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ -#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ -#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ -#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ -#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for USB peripheral ========== */ -#define USB_EPT_NBR 8 // Number of USB end points (obsolete) -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 6 // Index of Generic Clock -#define USB_PIPE_NUM 8 // Number of USB pipes - -#endif /* _SAMR21_USB_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_wdt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_wdt.h deleted file mode 100644 index 37f420ae3cd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_wdt.h +++ /dev/null @@ -1,71 +0,0 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_WDT_INSTANCE_ -#define _SAMR21_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status */ -#define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for WDT peripheral ========== */ -#define WDT_GCLK_ID 3 // Index of Generic Clock - -#endif /* _SAMR21_WDT_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e16a.h deleted file mode 100644 index 62a28b9a1aa..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e16a.h +++ /dev/null @@ -1,688 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMR21E16A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21E16A_PIO_ -#define _SAMR21E16A_PIO_ - -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */ -#define MUX_PC16F_GCLK_IO1 5L -#define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) -#define PORT_PC16F_GCLK_IO1 (1ul << 16) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ -#define MUX_PA28F_SERCOM3_PAD1 5L -#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) -#define PORT_PA28F_SERCOM3_PAD1 (1ul << 28) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ -#define MUX_PC19F_SERCOM4_PAD0 5L -#define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) -#define PORT_PC19F_SERCOM4_PAD0 (1ul << 19) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -#define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ -#define MUX_PC18F_SERCOM4_PAD3 5L -#define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) -#define PORT_PC18F_SERCOM4_PAD3 (1ul << 18) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for RFCTRL peripheral ========== */ -#define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ -#define MUX_PA08F_RFCTRL_FECTRL0 5L -#define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) -#define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8) -#define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ -#define MUX_PA09F_RFCTRL_FECTRL1 5L -#define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) -#define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9) -#define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ -#define MUX_PA14F_RFCTRL_FECTRL4 5L -#define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) -#define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14) -#define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ -#define MUX_PA15F_RFCTRL_FECTRL5 5L -#define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) -#define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15) - -#endif /* _SAMR21E16A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e17a.h deleted file mode 100644 index 5eda97bb04f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e17a.h +++ /dev/null @@ -1,688 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMR21E17A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21E17A_PIO_ -#define _SAMR21E17A_PIO_ - -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */ -#define MUX_PC16F_GCLK_IO1 5L -#define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) -#define PORT_PC16F_GCLK_IO1 (1ul << 16) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ -#define MUX_PA28F_SERCOM3_PAD1 5L -#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) -#define PORT_PA28F_SERCOM3_PAD1 (1ul << 28) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ -#define MUX_PC19F_SERCOM4_PAD0 5L -#define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) -#define PORT_PC19F_SERCOM4_PAD0 (1ul << 19) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -#define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ -#define MUX_PC18F_SERCOM4_PAD3 5L -#define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) -#define PORT_PC18F_SERCOM4_PAD3 (1ul << 18) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for RFCTRL peripheral ========== */ -#define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ -#define MUX_PA08F_RFCTRL_FECTRL0 5L -#define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) -#define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8) -#define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ -#define MUX_PA09F_RFCTRL_FECTRL1 5L -#define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) -#define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9) -#define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ -#define MUX_PA14F_RFCTRL_FECTRL4 5L -#define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) -#define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14) -#define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ -#define MUX_PA15F_RFCTRL_FECTRL5 5L -#define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) -#define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15) - -#endif /* _SAMR21E17A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e18a.h deleted file mode 100644 index 190320401f5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e18a.h +++ /dev/null @@ -1,688 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMR21E18A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21E18A_PIO_ -#define _SAMR21E18A_PIO_ - -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */ -#define MUX_PC16F_GCLK_IO1 5L -#define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) -#define PORT_PC16F_GCLK_IO1 (1ul << 16) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ -#define MUX_PA28F_SERCOM3_PAD1 5L -#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) -#define PORT_PA28F_SERCOM3_PAD1 (1ul << 28) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ -#define MUX_PC19F_SERCOM4_PAD0 5L -#define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) -#define PORT_PC19F_SERCOM4_PAD0 (1ul << 19) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -#define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ -#define MUX_PC18F_SERCOM4_PAD3 5L -#define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) -#define PORT_PC18F_SERCOM4_PAD3 (1ul << 18) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for RFCTRL peripheral ========== */ -#define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ -#define MUX_PA08F_RFCTRL_FECTRL0 5L -#define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) -#define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8) -#define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ -#define MUX_PA09F_RFCTRL_FECTRL1 5L -#define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) -#define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9) -#define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ -#define MUX_PA14F_RFCTRL_FECTRL4 5L -#define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) -#define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14) -#define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ -#define MUX_PA15F_RFCTRL_FECTRL5 5L -#define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) -#define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15) - -#endif /* _SAMR21E18A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g16a.h deleted file mode 100644 index fc0da173bcc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g16a.h +++ /dev/null @@ -1,928 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMR21G16A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21G16A_PIO_ -#define _SAMR21G16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */ -#define MUX_PC16F_GCLK_IO1 5L -#define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) -#define PORT_PC16F_GCLK_IO1 (1ul << 16) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ -#define MUX_PA28F_SERCOM3_PAD1 5L -#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) -#define PORT_PA28F_SERCOM3_PAD1 (1ul << 28) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ -#define MUX_PC19F_SERCOM4_PAD0 5L -#define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) -#define PORT_PC19F_SERCOM4_PAD0 (1ul << 19) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -#define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ -#define MUX_PC18F_SERCOM4_PAD3 5L -#define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) -#define PORT_PC18F_SERCOM4_PAD3 (1ul << 18) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for RFCTRL peripheral ========== */ -#define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ -#define MUX_PA08F_RFCTRL_FECTRL0 5L -#define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) -#define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8) -#define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ -#define MUX_PA09F_RFCTRL_FECTRL1 5L -#define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) -#define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9) -#define PIN_PA12F_RFCTRL_FECTRL2 12L /**< \brief RFCTRL signal: FECTRL2 on PA12 mux F */ -#define MUX_PA12F_RFCTRL_FECTRL2 5L -#define PINMUX_PA12F_RFCTRL_FECTRL2 ((PIN_PA12F_RFCTRL_FECTRL2 << 16) | MUX_PA12F_RFCTRL_FECTRL2) -#define PORT_PA12F_RFCTRL_FECTRL2 (1ul << 12) -#define PIN_PA13F_RFCTRL_FECTRL3 13L /**< \brief RFCTRL signal: FECTRL3 on PA13 mux F */ -#define MUX_PA13F_RFCTRL_FECTRL3 5L -#define PINMUX_PA13F_RFCTRL_FECTRL3 ((PIN_PA13F_RFCTRL_FECTRL3 << 16) | MUX_PA13F_RFCTRL_FECTRL3) -#define PORT_PA13F_RFCTRL_FECTRL3 (1ul << 13) -#define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ -#define MUX_PA14F_RFCTRL_FECTRL4 5L -#define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) -#define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14) -#define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ -#define MUX_PA15F_RFCTRL_FECTRL5 5L -#define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) -#define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15) - -#endif /* _SAMR21G16A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g17a.h deleted file mode 100644 index c22c6fe15ca..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g17a.h +++ /dev/null @@ -1,928 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMR21G17A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21G17A_PIO_ -#define _SAMR21G17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */ -#define MUX_PC16F_GCLK_IO1 5L -#define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) -#define PORT_PC16F_GCLK_IO1 (1ul << 16) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ -#define MUX_PA28F_SERCOM3_PAD1 5L -#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) -#define PORT_PA28F_SERCOM3_PAD1 (1ul << 28) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ -#define MUX_PC19F_SERCOM4_PAD0 5L -#define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) -#define PORT_PC19F_SERCOM4_PAD0 (1ul << 19) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -#define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ -#define MUX_PC18F_SERCOM4_PAD3 5L -#define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) -#define PORT_PC18F_SERCOM4_PAD3 (1ul << 18) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for RFCTRL peripheral ========== */ -#define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ -#define MUX_PA08F_RFCTRL_FECTRL0 5L -#define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) -#define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8) -#define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ -#define MUX_PA09F_RFCTRL_FECTRL1 5L -#define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) -#define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9) -#define PIN_PA12F_RFCTRL_FECTRL2 12L /**< \brief RFCTRL signal: FECTRL2 on PA12 mux F */ -#define MUX_PA12F_RFCTRL_FECTRL2 5L -#define PINMUX_PA12F_RFCTRL_FECTRL2 ((PIN_PA12F_RFCTRL_FECTRL2 << 16) | MUX_PA12F_RFCTRL_FECTRL2) -#define PORT_PA12F_RFCTRL_FECTRL2 (1ul << 12) -#define PIN_PA13F_RFCTRL_FECTRL3 13L /**< \brief RFCTRL signal: FECTRL3 on PA13 mux F */ -#define MUX_PA13F_RFCTRL_FECTRL3 5L -#define PINMUX_PA13F_RFCTRL_FECTRL3 ((PIN_PA13F_RFCTRL_FECTRL3 << 16) | MUX_PA13F_RFCTRL_FECTRL3) -#define PORT_PA13F_RFCTRL_FECTRL3 (1ul << 13) -#define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ -#define MUX_PA14F_RFCTRL_FECTRL4 5L -#define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) -#define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14) -#define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ -#define MUX_PA15F_RFCTRL_FECTRL5 5L -#define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) -#define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15) - -#endif /* _SAMR21G17A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g18a.h deleted file mode 100644 index aca60810412..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g18a.h +++ /dev/null @@ -1,928 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMR21G18A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21G18A_PIO_ -#define _SAMR21G18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */ -#define MUX_PC16F_GCLK_IO1 5L -#define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) -#define PORT_PC16F_GCLK_IO1 (1ul << 16) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ -#define MUX_PA27F_SERCOM3_PAD0 5L -#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) -#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ -#define MUX_PA28F_SERCOM3_PAD1 5L -#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) -#define PORT_PA28F_SERCOM3_PAD1 (1ul << 28) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ -#define MUX_PC19F_SERCOM4_PAD0 5L -#define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) -#define PORT_PC19F_SERCOM4_PAD0 (1ul << 19) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ -#define MUX_PB31F_SERCOM4_PAD1 5L -#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) -#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ -#define MUX_PB30F_SERCOM4_PAD2 5L -#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) -#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -#define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ -#define MUX_PC18F_SERCOM4_PAD3 5L -#define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) -#define PORT_PC18F_SERCOM4_PAD3 (1ul << 18) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO0 5L -#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) -#define PORT_PA16F_TCC0_WO0 (1ul << 16) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO1 5L -#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) -#define PORT_PA17F_TCC0_WO1 (1ul << 17) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for RFCTRL peripheral ========== */ -#define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ -#define MUX_PA08F_RFCTRL_FECTRL0 5L -#define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) -#define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8) -#define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ -#define MUX_PA09F_RFCTRL_FECTRL1 5L -#define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) -#define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9) -#define PIN_PA12F_RFCTRL_FECTRL2 12L /**< \brief RFCTRL signal: FECTRL2 on PA12 mux F */ -#define MUX_PA12F_RFCTRL_FECTRL2 5L -#define PINMUX_PA12F_RFCTRL_FECTRL2 ((PIN_PA12F_RFCTRL_FECTRL2 << 16) | MUX_PA12F_RFCTRL_FECTRL2) -#define PORT_PA12F_RFCTRL_FECTRL2 (1ul << 12) -#define PIN_PA13F_RFCTRL_FECTRL3 13L /**< \brief RFCTRL signal: FECTRL3 on PA13 mux F */ -#define MUX_PA13F_RFCTRL_FECTRL3 5L -#define PINMUX_PA13F_RFCTRL_FECTRL3 ((PIN_PA13F_RFCTRL_FECTRL3 << 16) | MUX_PA13F_RFCTRL_FECTRL3) -#define PORT_PA13F_RFCTRL_FECTRL3 (1ul << 13) -#define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ -#define MUX_PA14F_RFCTRL_FECTRL4 5L -#define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) -#define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14) -#define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ -#define MUX_PA15F_RFCTRL_FECTRL5 5L -#define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) -#define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15) - -#endif /* _SAMR21G18A_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21.h deleted file mode 100644 index 769e7004d06..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * \file - * - * \brief Top header file for SAMR21 - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21_ -#define _SAMR21_ - -/** - * \defgroup SAMR21_definitions SAMR21 Device Definitions - * \brief SAMR21 CMSIS Definitions. - */ - -#if defined(__SAMR21E16A__) || defined(__ATSAMR21E16A__) -#include "samr21e16a.h" -#elif defined(__SAMR21E17A__) || defined(__ATSAMR21E17A__) -#include "samr21e17a.h" -#elif defined(__SAMR21E18A__) || defined(__ATSAMR21E18A__) -#include "samr21e18a.h" -#elif defined(__SAMR21G16A__) || defined(__ATSAMR21G16A__) -#include "samr21g16a.h" -#elif defined(__SAMR21G17A__) || defined(__ATSAMR21G17A__) -#include "samr21g17a.h" -#elif defined(__SAMR21G18A__) || defined(__ATSAMR21G18A__) -#include "samr21g18a.h" -#else -#error Library does not support the specified device. -#endif - -#endif /* _SAMR21_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h deleted file mode 100644 index 2208878819a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMR21E16A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21E16A_ -#define _SAMR21E16A_ - -/** - * \ingroup SAMR21_definitions - * \addtogroup SAMR21E16A_definitions SAMR21E16A definitions - * This file defines all structures and symbols for SAMR21E16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMR21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21E16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21E16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21E16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21E16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21E16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samr21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E16A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rfctrl.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMR21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E16A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rfctrl.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMR21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMR21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */ -#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMR21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E16A_port PORT Definitions */ -/*@{*/ - -#include "pio_samr21e16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMR21E16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001001EUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 3 -#define SIP_CONFIG RF233 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMR21E16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMR21E16A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h deleted file mode 100644 index e4c3c23319e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMR21E17A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21E17A_ -#define _SAMR21E17A_ - -/** - * \ingroup SAMR21_definitions - * \addtogroup SAMR21E17A_definitions SAMR21E17A definitions - * This file defines all structures and symbols for SAMR21E17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMR21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21E17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21E17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21E17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21E17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21E17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21E17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21E17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21E17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21E17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21E17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21E17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21E17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21E17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21E17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21E17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21E17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samr21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E17A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rfctrl.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMR21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E17A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rfctrl.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMR21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMR21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */ -#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMR21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E17A_port PORT Definitions */ -/*@{*/ - -#include "pio_samr21e17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMR21E17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001001DUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 3 -#define SIP_CONFIG RF233 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMR21E17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMR21E17A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h deleted file mode 100644 index 2e4e3dd90a1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMR21E18A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21E18A_ -#define _SAMR21E18A_ - -/** - * \ingroup SAMR21_definitions - * \addtogroup SAMR21E18A_definitions SAMR21E18A definitions - * This file defines all structures and symbols for SAMR21E18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMR21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21E18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21E18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21E18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21E18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21E18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21E18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21E18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21E18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21E18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21E18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21E18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21E18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21E18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21E18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21E18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21E18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samr21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E18A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rfctrl.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMR21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E18A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rfctrl.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMR21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMR21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */ -#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMR21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21E18A_port PORT Definitions */ -/*@{*/ - -#include "pio_samr21e18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMR21E18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001001CUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 3 -#define SIP_CONFIG RF233 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMR21E18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMR21E18A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h deleted file mode 100644 index 42d7c79af54..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMR21G16A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21G16A_ -#define _SAMR21G16A_ - -/** - * \ingroup SAMR21_definitions - * \addtogroup SAMR21G16A_definitions SAMR21G16A definitions - * This file defines all structures and symbols for SAMR21G16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMR21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21G16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21G16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21G16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21G16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21G16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21G16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21G16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21G16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21G16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21G16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21G16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21G16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21G16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samr21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G16A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rfctrl.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMR21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G16A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rfctrl.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMR21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMR21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */ -#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMR21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G16A_port PORT Definitions */ -/*@{*/ - -#include "pio_samr21g16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMR21G16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001001BUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 3 -#define SIP_CONFIG RF233 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMR21G16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMR21G16A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h deleted file mode 100644 index 44ba21d89b2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMR21G17A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21G17A_ -#define _SAMR21G17A_ - -/** - * \ingroup SAMR21_definitions - * \addtogroup SAMR21G17A_definitions SAMR21G17A definitions - * This file defines all structures and symbols for SAMR21G17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMR21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21G17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21G17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21G17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21G17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21G17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21G17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21G17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21G17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21G17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21G17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21G17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21G17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21G17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samr21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G17A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rfctrl.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMR21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G17A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rfctrl.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMR21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMR21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */ -#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMR21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G17A_port PORT Definitions */ -/*@{*/ - -#include "pio_samr21g17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMR21G17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x1001001AUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 3 -#define SIP_CONFIG RF233 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMR21G17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMR21G17A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h deleted file mode 100644 index 49123bb9597..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMR21G18A - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMR21G18A_ -#define _SAMR21G18A_ - -/** - * \ingroup SAMR21_definitions - * \addtogroup SAMR21G18A_definitions SAMR21G18A definitions - * This file defines all structures and symbols for SAMR21G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMR21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samr21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G18A_api Peripheral Software API */ -/*@{*/ - -#include "comp_ac.h" -#include "comp_adc.h" -#include "comp_dmac.h" -#include "comp_dsu.h" -#include "comp_eic.h" -#include "comp_evsys.h" -#include "comp_gclk.h" -#include "comp_hmatrixb.h" -#include "comp_mtb.h" -#include "comp_nvmctrl.h" -#include "comp_pac.h" -#include "comp_pm.h" -#include "comp_port.h" -#include "comp_rfctrl.h" -#include "comp_rtc.h" -#include "comp_sercom.h" -#include "comp_sysctrl.h" -#include "comp_tc.h" -#include "comp_tcc.h" -#include "comp_usb.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMR21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_ac.h" -#include "ins_adc.h" -#include "ins_dmac.h" -#include "ins_dsu.h" -#include "ins_eic.h" -#include "ins_evsys.h" -#include "ins_gclk.h" -#include "ins_sbmatrix.h" -#include "ins_mtb.h" -#include "ins_nvmctrl.h" -#include "ins_pac0.h" -#include "ins_pac1.h" -#include "ins_pac2.h" -#include "ins_pm.h" -#include "ins_port.h" -#include "ins_rfctrl.h" -#include "ins_rtc.h" -#include "ins_sercom0.h" -#include "ins_sercom1.h" -#include "ins_sercom2.h" -#include "ins_sercom3.h" -#include "ins_sercom4.h" -#include "ins_sercom5.h" -#include "ins_sysctrl.h" -#include "ins_tc3.h" -#include "ins_tc4.h" -#include "ins_tc5.h" -#include "ins_tcc0.h" -#include "ins_tcc1.h" -#include "ins_tcc2.h" -#include "ins_usb.h" -#include "ins_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMR21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMR21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */ -#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */ -#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMR21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMR21G18A_port PORT Definitions */ -/*@{*/ - -#include "pio_samr21g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMR21G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ -#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ - -#define DSU_DID_RESETVALUE 0x10010019UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 3 -#define SIP_CONFIG RF233 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMR21G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMR21G18A_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.c deleted file mode 100644 index dc728816735..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.c +++ /dev/null @@ -1,35 +0,0 @@ -#include "samr21.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (1000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.h deleted file mode 100644 index 28b0bfca997..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _SYSTEM_SAMR21_H_INCLUDED_ -#define _SYSTEM_SAMR21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMR21_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/compiler.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/compiler.h deleted file mode 100644 index 7db383e4426..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/compiler.h +++ /dev/null @@ -1,1113 +0,0 @@ -#ifndef UTILS_COMPILER_H_INCLUDED -#define UTILS_COMPILER_H_INCLUDED - -/** - * \defgroup group_sam0_utils Compiler abstraction layer and code utilities - * - * Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices. - * This module provides various abstraction layers and utilities to make code compatible between different compilers. - * - * @{ - */ - -#if (defined __ICCARM__) -# include -#endif - -#include -#include -#include -#include -#include - -#ifndef __ASSEMBLY__ - -#include -#include -#include -#include - -/** - * \def UNUSED - * \brief Marking \a v as a unused parameter or value. - */ -#define UNUSED(v) (void)(v) - -/** - * \def barrier - * \brief Memory barrier - */ -#ifdef __GNUC__ -# define barrier() asm volatile("" ::: "memory") -#else -# define barrier() asm ("") -#endif - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param[in] arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - - -/** - * \brief Set aligned boundary. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif (defined __ICCARM__) -# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#endif - -/** - * \brief Set word-aligned boundary. - */ -#if (defined __GNUC__) || defined(__CC_ARM) -#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) -#elif (defined __ICCARM__) -#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) -#endif - -/** - * \def __always_inline - * \brief The function should always be inlined. - * - * This annotation instructs the compiler to ignore its inlining - * heuristics and inline the function no matter how big it thinks it - * becomes. - */ -#if defined(__CC_ARM) -# define __always_inline __forceinline -#elif (defined __GNUC__) -# define __always_inline __attribute__((__always_inline__)) -#elif (defined __ICCARM__) -# define __always_inline _Pragma("inline=forced") -#endif - -/** - * \def __no_inline - * \brief The function should never be inlined - * - * This annotation instructs the compiler to ignore its inlining - * heuristics and not inline the function no matter how small it thinks it - * becomes. - */ -#if defined(__CC_ARM) -# define __no_inline __attribute__((noinline)) -#elif (defined __GNUC__) -# define __no_inline __attribute__((noinline)) -#elif (defined __ICCARM__) -# define __no_inline _Pragma("inline=never") -#endif - - -/** \brief This macro is used to test fatal errors. - * - * The macro tests if the expression is false. If it is, a fatal error is - * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO - * is defined, a unit test version of the macro is used, to allow execution - * of further tests after a false expression. - * - * \param[in] expr Expression to evaluate and supposed to be nonzero. - */ -#if defined(_ASSERT_ENABLE_) -# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO) -# include "unit_test/suite.h" -# else -# undef TEST_SUITE_DEFINE_ASSERT_MACRO -# define Assert(expr) \ - {\ - if (!(expr)) asm("BKPT #0");\ - } -# endif -#else -# define Assert(expr) ((void) 0) -#endif - -/* Define WEAK attribute */ -//defined in toochain.h -//#if defined ( __CC_ARM ) -//# define WEAK __attribute__ ((weak)) -//#elif defined ( __ICCARM__ ) -//# define WEAK __weak -//#elif defined ( __GNUC__ ) -//# define WEAK __attribute__ ((weak)) -//#endif - -/* Define NO_INIT attribute */ -#if defined ( __CC_ARM ) -# define NO_INIT __attribute__((zero_init)) -#elif defined ( __ICCARM__ ) -# define NO_INIT __no_init -#elif defined ( __GNUC__ ) -# define NO_INIT __attribute__((section(".no_init"))) -#endif - -#include "interrupt.h" - -/** \name Usual Types - * @{ */ -#ifndef __cplusplus -# if !defined(__bool_true_false_are_defined) -typedef unsigned char bool; -# endif -#endif -typedef uint16_t le16_t; -typedef uint16_t be16_t; -typedef uint32_t le32_t; -typedef uint32_t be32_t; -typedef uint32_t iram_size_t; -/** @} */ - -/** \name Aliasing Aggregate Types - * @{ */ - -/** 16-bit union. */ -typedef union { - int16_t s16; - uint16_t u16; - int8_t s8[2]; - uint8_t u8[2]; -} Union16; - -/** 32-bit union. */ -typedef union { - int32_t s32; - uint32_t u32; - int16_t s16[2]; - uint16_t u16[2]; - int8_t s8[4]; - uint8_t u8[4]; -} Union32; - -/** 64-bit union. */ -typedef union { - int64_t s64; - uint64_t u64; - int32_t s32[2]; - uint32_t u32[2]; - int16_t s16[4]; - uint16_t u16[4]; - int8_t s8[8]; - uint8_t u8[8]; -} Union64; - -/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union { - int64_t *s64ptr; - uint64_t *u64ptr; - int32_t *s32ptr; - uint32_t *u32ptr; - int16_t *s16ptr; - uint16_t *u16ptr; - int8_t *s8ptr; - uint8_t *u8ptr; -} UnionPtr; - -/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union { - volatile int64_t *s64ptr; - volatile uint64_t *u64ptr; - volatile int32_t *s32ptr; - volatile uint32_t *u32ptr; - volatile int16_t *s16ptr; - volatile uint16_t *u16ptr; - volatile int8_t *s8ptr; - volatile uint8_t *u8ptr; -} UnionVPtr; - -/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union { - const int64_t *s64ptr; - const uint64_t *u64ptr; - const int32_t *s32ptr; - const uint32_t *u32ptr; - const int16_t *s16ptr; - const uint16_t *u16ptr; - const int8_t *s8ptr; - const uint8_t *u8ptr; -} UnionCPtr; - -/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union { - const volatile int64_t *s64ptr; - const volatile uint64_t *u64ptr; - const volatile int32_t *s32ptr; - const volatile uint32_t *u32ptr; - const volatile int16_t *s16ptr; - const volatile uint16_t *u16ptr; - const volatile int8_t *s8ptr; - const volatile uint8_t *u8ptr; -} UnionCVPtr; - -/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct { - int64_t *s64ptr; - uint64_t *u64ptr; - int32_t *s32ptr; - uint32_t *u32ptr; - int16_t *s16ptr; - uint16_t *u16ptr; - int8_t *s8ptr; - uint8_t *u8ptr; -} StructPtr; - -/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct { - volatile int64_t *s64ptr; - volatile uint64_t *u64ptr; - volatile int32_t *s32ptr; - volatile uint32_t *u32ptr; - volatile int16_t *s16ptr; - volatile uint16_t *u16ptr; - volatile int8_t *s8ptr; - volatile uint8_t *u8ptr; -} StructVPtr; - -/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct { - const int64_t *s64ptr; - const uint64_t *u64ptr; - const int32_t *s32ptr; - const uint32_t *u32ptr; - const int16_t *s16ptr; - const uint16_t *u16ptr; - const int8_t *s8ptr; - const uint8_t *u8ptr; -} StructCPtr; - -/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct { - const volatile int64_t *s64ptr; - const volatile uint64_t *u64ptr; - const volatile int32_t *s32ptr; - const volatile uint32_t *u32ptr; - const volatile int16_t *s16ptr; - const volatile uint16_t *u16ptr; - const volatile int8_t *s8ptr; - const volatile uint8_t *u8ptr; -} StructCVPtr; - -/** @} */ - -#endif /* #ifndef __ASSEMBLY__ */ - -/** \name Usual Constants - * @{ */ -#define DISABLE 0 -#define ENABLE 1 - -#ifndef __cplusplus -# if !defined(__bool_true_false_are_defined) -# define false 0 -# define true 1 -# endif -#endif -/** @} */ - -#ifndef __ASSEMBLY__ - -/** \name Optimization Control - * @{ */ - -/** - * \def likely(exp) - * \brief The expression \a exp is likely to be true - */ -#if !defined(likely) || defined(__DOXYGEN__) -# define likely(exp) (exp) -#endif - -/** - * \def unlikely(exp) - * \brief The expression \a exp is unlikely to be true - */ -#if !defined(unlikely) || defined(__DOXYGEN__) -# define unlikely(exp) (exp) -#endif - -/** - * \def is_constant(exp) - * \brief Determine if an expression evaluates to a constant value. - * - * \param[in] exp Any expression - * - * \return true if \a exp is constant, false otherwise. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define is_constant(exp) __builtin_constant_p(exp) -#else -# define is_constant(exp) (0) -#endif - -/** @} */ - -/** \name Bit-Field Handling - * @{ */ - -/** \brief Reads the bits of a value specified by a given bit-mask. - * - * \param[in] value Value to read bits from. - * \param[in] mask Bit-mask indicating bits to read. - * - * \return Read bits. - */ -#define Rd_bits( value, mask) ((value) & (mask)) - -/** \brief Writes the bits of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue to write bits to. - * \param[in] mask Bit-mask indicating bits to write. - * \param[in] bits Bits to write. - * - * \return Resulting value with written bits. - */ -#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ - ((bits ) & (mask))) - -/** \brief Tests the bits of a value specified by a given bit-mask. - * - * \param[in] value Value of which to test bits. - * \param[in] mask Bit-mask indicating bits to test. - * - * \return \c 1 if at least one of the tested bits is set, else \c 0. - */ -#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) - -/** \brief Clears the bits of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue of which to clear bits. - * \param[in] mask Bit-mask indicating bits to clear. - * - * \return Resulting value with cleared bits. - */ -#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) - -/** \brief Sets the bits of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue of which to set bits. - * \param[in] mask Bit-mask indicating bits to set. - * - * \return Resulting value with set bits. - */ -#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) - -/** \brief Toggles the bits of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue of which to toggle bits. - * \param[in] mask Bit-mask indicating bits to toggle. - * - * \return Resulting value with toggled bits. - */ -#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) - -/** \brief Reads the bit-field of a value specified by a given bit-mask. - * - * \param[in] value Value to read a bit-field from. - * \param[in] mask Bit-mask indicating the bit-field to read. - * - * \return Read bit-field. - */ -#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) - -/** \brief Writes the bit-field of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue to write a bit-field to. - * \param[in] mask Bit-mask indicating the bit-field to write. - * \param[in] bitfield Bit-field to write. - * - * \return Resulting value with written bit-field. - */ -#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask))) - -/** @} */ - - -/** \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - * - * @{ */ - -/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define clz(u) __builtin_clz(u) -#else -# define clz(u) (((u) == 0) ? 32 : \ - ((u) & (1ul << 31)) ? 0 : \ - ((u) & (1ul << 30)) ? 1 : \ - ((u) & (1ul << 29)) ? 2 : \ - ((u) & (1ul << 28)) ? 3 : \ - ((u) & (1ul << 27)) ? 4 : \ - ((u) & (1ul << 26)) ? 5 : \ - ((u) & (1ul << 25)) ? 6 : \ - ((u) & (1ul << 24)) ? 7 : \ - ((u) & (1ul << 23)) ? 8 : \ - ((u) & (1ul << 22)) ? 9 : \ - ((u) & (1ul << 21)) ? 10 : \ - ((u) & (1ul << 20)) ? 11 : \ - ((u) & (1ul << 19)) ? 12 : \ - ((u) & (1ul << 18)) ? 13 : \ - ((u) & (1ul << 17)) ? 14 : \ - ((u) & (1ul << 16)) ? 15 : \ - ((u) & (1ul << 15)) ? 16 : \ - ((u) & (1ul << 14)) ? 17 : \ - ((u) & (1ul << 13)) ? 18 : \ - ((u) & (1ul << 12)) ? 19 : \ - ((u) & (1ul << 11)) ? 20 : \ - ((u) & (1ul << 10)) ? 21 : \ - ((u) & (1ul << 9)) ? 22 : \ - ((u) & (1ul << 8)) ? 23 : \ - ((u) & (1ul << 7)) ? 24 : \ - ((u) & (1ul << 6)) ? 25 : \ - ((u) & (1ul << 5)) ? 26 : \ - ((u) & (1ul << 4)) ? 27 : \ - ((u) & (1ul << 3)) ? 28 : \ - ((u) & (1ul << 2)) ? 29 : \ - ((u) & (1ul << 1)) ? 30 : \ - 31) -#endif - -/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define ctz(u) __builtin_ctz(u) -#else -# define ctz(u) ((u) & (1ul << 0) ? 0 : \ - (u) & (1ul << 1) ? 1 : \ - (u) & (1ul << 2) ? 2 : \ - (u) & (1ul << 3) ? 3 : \ - (u) & (1ul << 4) ? 4 : \ - (u) & (1ul << 5) ? 5 : \ - (u) & (1ul << 6) ? 6 : \ - (u) & (1ul << 7) ? 7 : \ - (u) & (1ul << 8) ? 8 : \ - (u) & (1ul << 9) ? 9 : \ - (u) & (1ul << 10) ? 10 : \ - (u) & (1ul << 11) ? 11 : \ - (u) & (1ul << 12) ? 12 : \ - (u) & (1ul << 13) ? 13 : \ - (u) & (1ul << 14) ? 14 : \ - (u) & (1ul << 15) ? 15 : \ - (u) & (1ul << 16) ? 16 : \ - (u) & (1ul << 17) ? 17 : \ - (u) & (1ul << 18) ? 18 : \ - (u) & (1ul << 19) ? 19 : \ - (u) & (1ul << 20) ? 20 : \ - (u) & (1ul << 21) ? 21 : \ - (u) & (1ul << 22) ? 22 : \ - (u) & (1ul << 23) ? 23 : \ - (u) & (1ul << 24) ? 24 : \ - (u) & (1ul << 25) ? 25 : \ - (u) & (1ul << 26) ? 26 : \ - (u) & (1ul << 27) ? 27 : \ - (u) & (1ul << 28) ? 28 : \ - (u) & (1ul << 29) ? 29 : \ - (u) & (1ul << 30) ? 30 : \ - (u) & (1ul << 31) ? 31 : \ - 32) -#endif - -/** @} */ - - -/** \name Bit Reversing - * @{ */ - -/** \brief Reverses the bits of \a u8. - * - * \param[in] u8 U8 of which to reverse the bits. - * - * \return Value resulting from \a u8 with reversed bits. - */ -#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) - -/** \brief Reverses the bits of \a u16. - * - * \param[in] u16 U16 of which to reverse the bits. - * - * \return Value resulting from \a u16 with reversed bits. - */ -#define bit_reverse16(u16) ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16)) - -/** \brief Reverses the bits of \a u32. - * - * \param[in] u32 U32 of which to reverse the bits. - * - * \return Value resulting from \a u32 with reversed bits. - */ -#define bit_reverse32(u32) __RBIT(u32) - -/** \brief Reverses the bits of \a u64. - * - * \param[in] u64 U64 of which to reverse the bits. - * - * \return Value resulting from \a u64 with reversed bits. - */ -#define bit_reverse64(u64) ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) |\ - ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32))) - -/** @} */ - - -/** \name Alignment - * @{ */ - -/** \brief Tests alignment of the number \a val with the \a n boundary. - * - * \param[in] val Input value. - * \param[in] n Boundary. - * - * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. - */ -#define Test_align(val, n) (!Tst_bits( val, (n) - 1 ) ) - -/** \brief Gets alignment of the number \a val with respect to the \a n boundary. - * - * \param[in] val Input value. - * \param[in] n Boundary. - * - * \return Alignment of the number \a val with respect to the \a n boundary. - */ -#define Get_align(val, n) ( Rd_bits( val, (n) - 1 ) ) - -/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. - * - * \param[in] lval Input/output lvalue. - * \param[in] n Boundary. - * \param[in] alg Alignment. - * - * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. - */ -#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) - -/** \brief Aligns the number \a val with the upper \a n boundary. - * - * \param[in] val Input value. - * \param[in] n Boundary. - * - * \return Value resulting from the number \a val aligned with the upper \a n boundary. - */ -#define Align_up( val, n) (((val) + ((n) - 1)) & ~((n) - 1)) - -/** \brief Aligns the number \a val with the lower \a n boundary. - * - * \param[in] val Input value. - * \param[in] n Boundary. - * - * \return Value resulting from the number \a val aligned with the lower \a n boundary. - */ -#define Align_down(val, n) ( (val) & ~((n) - 1)) - -/** @} */ - - -/** \name Mathematics - * - * The same considerations as for clz and ctz apply here but GCC does not - * provide built-in functions to access the assembly instructions abs, min and - * max and it does not produce them by itself in most cases, so two sets of - * macros are defined here: - * - Abs, Min and Max to apply to constant expressions (values known at - * compile time); - * - abs, min and max to apply to non-constant expressions (values unknown at - * compile time), abs is found in stdlib.h. - * - * @{ */ - -/** \brief Takes the absolute value of \a a. - * - * \param[in] a Input value. - * - * \return Absolute value of \a a. - * - * \note More optimized if only used with values known at compile time. - */ -#define Abs(a) (((a) < 0 ) ? -(a) : (a)) - -/** \brief Takes the minimal value of \a a and \a b. - * - * \param[in] a Input value. - * \param[in] b Input value. - * - * \return Minimal value of \a a and \a b. - * - * \note More optimized if only used with values known at compile time. - */ -#define Min(a, b) (((a) < (b)) ? (a) : (b)) - -/** \brief Takes the maximal value of \a a and \a b. - * - * \param[in] a Input value. - * \param[in] b Input value. - * - * \return Maximal value of \a a and \a b. - * - * \note More optimized if only used with values known at compile time. - */ -#define Max(a, b) (((a) > (b)) ? (a) : (b)) - -/** \brief Takes the minimal value of \a a and \a b. - * - * \param[in] a Input value. - * \param[in] b Input value. - * - * \return Minimal value of \a a and \a b. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define min(a, b) Min(a, b) - -/** \brief Takes the maximal value of \a a and \a b. - * - * \param[in] a Input value. - * \param[in] b Input value. - * - * \return Maximal value of \a a and \a b. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define max(a, b) Max(a, b) - -/** @} */ - - -/** \brief Calls the routine at address \a addr. - * - * It generates a long call opcode. - * - * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if - * it is invoked from the CPU supervisor mode. - * - * \param[in] addr Address of the routine to call. - * - * \note It may be used as a long jump opcode in some special cases. - */ -#define Long_call(addr) ((*(void (*)(void))(addr))()) - - -/** \name MCU Endianism Handling - * ARM is MCU little endian. - * - * @{ */ -#define BE16(x) Swap16(x) -#define LE16(x) (x) - -#define le16_to_cpu(x) (x) -#define cpu_to_le16(x) (x) -#define LE16_TO_CPU(x) (x) -#define CPU_TO_LE16(x) (x) - -#define be16_to_cpu(x) Swap16(x) -#define cpu_to_be16(x) Swap16(x) -#define BE16_TO_CPU(x) Swap16(x) -#define CPU_TO_BE16(x) Swap16(x) - -#define le32_to_cpu(x) (x) -#define cpu_to_le32(x) (x) -#define LE32_TO_CPU(x) (x) -#define CPU_TO_LE32(x) (x) - -#define be32_to_cpu(x) swap32(x) -#define cpu_to_be32(x) swap32(x) -#define BE32_TO_CPU(x) swap32(x) -#define CPU_TO_BE32(x) swap32(x) -/** @} */ - - -/** \name Endianism Conversion - * - * The same considerations as for clz and ctz apply here but GCC's - * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when - * applied to constant expressions, so two sets of macros are defined here: - * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known - * at compile time); - * - swap16, swap32 and swap64 to apply to non-constant expressions (values - * unknown at compile time). - * - * @{ */ - -/** \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param[in] u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) |\ - ((uint16_t)(u16) << 8))) - -/** \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param[in] u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) |\ - ((uint32_t)Swap16((uint32_t)(u32)) << 16))) - -/** \brief Toggles the endianism of \a u64 (by swapping its bytes). - * - * \param[in] u64 U64 of which to toggle the endianism. - * - * \return Value resulting from \a u64 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) |\ - ((uint64_t)Swap32((uint64_t)(u64)) << 32))) - -/** \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param[in] u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define swap16(u16) Swap16(u16) - -/** \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param[in] u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#if (defined __GNUC__) -# define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32))) -#else -# define swap32(u32) Swap32(u32) -#endif - -/** \brief Toggles the endianism of \a u64 (by swapping its bytes). - * - * \param[in] u64 U64 of which to toggle the endianism. - * - * \return Value resulting from \a u64 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#if (defined __GNUC__) -# define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64))) -#else -# define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) |\ - ((uint64_t)swap32((uint64_t)(u64)) << 32))) -#endif - -/** @} */ - - -/** \name Target Abstraction - * - * @{ */ - -#define _GLOBEXT_ extern /**< extern storage-class specifier. */ -#define _CONST_TYPE_ const /**< const type qualifier. */ -#define _MEM_TYPE_SLOW_ /**< Slow memory type. */ -#define _MEM_TYPE_MEDFAST_ /**< Fairly fast memory type. */ -#define _MEM_TYPE_FAST_ /**< Fast memory type. */ - -#define memcmp_ram2ram memcmp /**< Target-specific memcmp of RAM to RAM. */ -#define memcmp_code2ram memcmp /**< Target-specific memcmp of RAM to NVRAM. */ -#define memcpy_ram2ram memcpy /**< Target-specific memcpy from RAM to RAM. */ -#define memcpy_code2ram memcpy /**< Target-specific memcpy from NVRAM to RAM. */ - -/** @} */ - -/** - * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using - * integer arithmetic. - * - * \param[in] a An integer - * \param[in] b Another integer - * - * \return (\a a / \a b) rounded up to the nearest integer. - */ -#define div_ceil(a, b) (((a) + (b) - 1) / (b)) - -#endif /* #ifndef __ASSEMBLY__ */ -#ifdef __ICCARM__ -/** \name Compiler Keywords - * - * Port of some keywords from GCC to IAR Embedded Workbench. - * - * @{ */ - -#define __asm__ asm -#define __inline__ inline -#define __volatile__ - -/** @} */ - -#endif - -#define FUNC_PTR void * -/** - * \def unused - * \brief Marking \a v as a unused parameter or value. - */ -#define unused(v) do { (void)(v); } while(0) - -/* Define RAMFUNC attribute */ -#if defined ( __CC_ARM ) /* Keil uVision 4 */ -# define RAMFUNC __attribute__ ((section(".ramfunc"))) -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define RAMFUNC __ramfunc -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define RAMFUNC __attribute__ ((section(".ramfunc"))) -#endif - -/* Define OPTIMIZE_HIGH attribute */ -#if defined ( __CC_ARM ) /* Keil uVision 4 */ -# define OPTIMIZE_HIGH _Pragma("O3") -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define OPTIMIZE_HIGH _Pragma("optimize=high") -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define OPTIMIZE_HIGH __attribute__((optimize(s))) -#endif -#define PASS 0 -#define FAIL 1 -#define LOW 0 -#define HIGH 1 - -typedef int8_t S8 ; //!< 8-bit signed integer. -typedef uint8_t U8 ; //!< 8-bit unsigned integer. -typedef int16_t S16; //!< 16-bit signed integer. -typedef uint16_t U16; //!< 16-bit unsigned integer. -typedef int32_t S32; //!< 32-bit signed integer. -typedef uint32_t U32; //!< 32-bit unsigned integer. -typedef int64_t S64; //!< 64-bit signed integer. -typedef uint64_t U64; //!< 64-bit unsigned integer. -typedef float F32; //!< 32-bit floating-point number. -typedef double F64; //!< 64-bit floating-point number. - -#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. -#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. - -#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. -#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. -#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32. -#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32. -#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32. -#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32. -#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. -#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. -#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. -#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. - -#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. -#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. -#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64. -#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64. -#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64. -#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64. -#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. -#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. -#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. -#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. -#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64. -#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64. -#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64. -#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64. -#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64. -#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64. -#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64. -#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64. -#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. -#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. -#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. -#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. -#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. -#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. -#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. -#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. - -#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. -#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. -#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. -#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. -#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. -#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. -#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. -#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. - -#if defined(__ICCARM__) -#define SHORTENUM __packed -#elif defined(__GNUC__) -#define SHORTENUM __attribute__((packed)) -#endif - -/* No operation */ -#if defined(__ICCARM__) -#define nop() __no_operation() -#elif defined(__GNUC__) -#define nop() (__NOP()) -#endif - -#define FLASH_DECLARE(x) const x -#define FLASH_EXTERN(x) extern const x -#define PGM_READ_BYTE(x) *(x) -#define PGM_READ_WORD(x) *(x) -#define MEMCPY_ENDIAN memcpy -#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len)) - -/*Defines the Flash Storage for the request and response of MAC*/ -#define CMD_ID_OCTET (0) - -/* Converting of values from CPU endian to little endian. */ -#define CPU_ENDIAN_TO_LE16(x) (x) -#define CPU_ENDIAN_TO_LE32(x) (x) -#define CPU_ENDIAN_TO_LE64(x) (x) - -/* Converting of values from little endian to CPU endian. */ -#define LE16_TO_CPU_ENDIAN(x) (x) -#define LE32_TO_CPU_ENDIAN(x) (x) -#define LE64_TO_CPU_ENDIAN(x) (x) - -/* Converting of constants from little endian to CPU endian. */ -#define CLE16_TO_CPU_ENDIAN(x) (x) -#define CLE32_TO_CPU_ENDIAN(x) (x) -#define CLE64_TO_CPU_ENDIAN(x) (x) - -/* Converting of constants from CPU endian to little endian. */ -#define CCPU_ENDIAN_TO_LE16(x) (x) -#define CCPU_ENDIAN_TO_LE32(x) (x) -#define CCPU_ENDIAN_TO_LE64(x) (x) - -#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src)) -#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src)) - -/** - * @brief Converts a 64-Bit value into a 8 Byte array - * - * @param[in] value 64-Bit value - * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value - * @ingroup apiPalApi - */ -static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) -{ - uint8_t index = 0; - - while (index < 8) { - data[index++] = value & 0xFF; - value = value >> 8; - } -} - -/** - * @brief Converts a 16-Bit value into a 2 Byte array - * - * @param[in] value 16-Bit value - * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value - * @ingroup apiPalApi - */ -static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* Converts a 16-Bit value into a 2 Byte array */ -static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* Converts a 16-Bit value into a 2 Byte array */ -static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* - * @brief Converts a 2 Byte array into a 16-Bit value - * - * @param data Specifies the pointer to the 2 Byte array - * - * @return 16-Bit value - * @ingroup apiPalApi - */ -static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) -{ - return (data[0] | ((uint16_t)data[1] << 8)); -} - -/* Converts a 4 Byte array into a 32-Bit value */ -static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) -{ - union { - uint32_t u32; - uint8_t u8[4]; - } long_addr; - uint8_t index; - for (index = 0; index < 4; index++) { - long_addr.u8[index] = *data++; - } - return long_addr.u32; -} - -/** - * @brief Converts a 8 Byte array into a 64-Bit value - * - * @param data Specifies the pointer to the 8 Byte array - * - * @return 64-Bit value - * @ingroup apiPalApi - */ -static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) -{ - union { - uint64_t u64; - uint8_t u8[8]; - } long_addr; - - uint8_t index; - - for (index = 0; index < 8; index++) { - long_addr.u8[index] = *data++; - } - - return long_addr.u64; -} - -/** @} */ - -#endif /* UTILS_COMPILER_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/header_files/io.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/header_files/io.h deleted file mode 100644 index b85bd65353e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/header_files/io.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _SAM_IO_ -#define _SAM_IO_ - -#include -#include -#include - - -/* SAM D20 family */ -#if (SAMD20) -# include "samd20.h" -#endif - -#if (SAMD21) -# include "samd21.h" -#endif - -#if (SAMR21) -# include "samr21.h" -#endif - -#if (SAMD10) -# include "samd10.h" -#endif - -#if (SAMD11) -# include "samd11.h" -#endif - -#if (SAML21) -# include "saml21.h" -#endif - -#endif /* _SAM_IO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrecursion.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrecursion.h deleted file mode 100644 index e227dc8b45f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrecursion.h +++ /dev/null @@ -1,552 +0,0 @@ -#ifndef _MRECURSION_H_ -#define _MRECURSION_H_ - -/** - * \defgroup group_sam0_utils_mrecursion Preprocessor - Macro Recursion - * - * \ingroup group_sam0_utils - * - * @{ - */ - -#include "preprocessor.h" - -#define DEC_256 255 -#define DEC_255 254 -#define DEC_254 253 -#define DEC_253 252 -#define DEC_252 251 -#define DEC_251 250 -#define DEC_250 249 -#define DEC_249 248 -#define DEC_248 247 -#define DEC_247 246 -#define DEC_246 245 -#define DEC_245 244 -#define DEC_244 243 -#define DEC_243 242 -#define DEC_242 241 -#define DEC_241 240 -#define DEC_240 239 -#define DEC_239 238 -#define DEC_238 237 -#define DEC_237 236 -#define DEC_236 235 -#define DEC_235 234 -#define DEC_234 233 -#define DEC_233 232 -#define DEC_232 231 -#define DEC_231 230 -#define DEC_230 229 -#define DEC_229 228 -#define DEC_228 227 -#define DEC_227 226 -#define DEC_226 225 -#define DEC_225 224 -#define DEC_224 223 -#define DEC_223 222 -#define DEC_222 221 -#define DEC_221 220 -#define DEC_220 219 -#define DEC_219 218 -#define DEC_218 217 -#define DEC_217 216 -#define DEC_216 215 -#define DEC_215 214 -#define DEC_214 213 -#define DEC_213 212 -#define DEC_212 211 -#define DEC_211 210 -#define DEC_210 209 -#define DEC_209 208 -#define DEC_208 207 -#define DEC_207 206 -#define DEC_206 205 -#define DEC_205 204 -#define DEC_204 203 -#define DEC_203 202 -#define DEC_202 201 -#define DEC_201 200 -#define DEC_200 199 -#define DEC_199 198 -#define DEC_198 197 -#define DEC_197 196 -#define DEC_196 195 -#define DEC_195 194 -#define DEC_194 193 -#define DEC_193 192 -#define DEC_192 191 -#define DEC_191 190 -#define DEC_190 189 -#define DEC_189 188 -#define DEC_188 187 -#define DEC_187 186 -#define DEC_186 185 -#define DEC_185 184 -#define DEC_184 183 -#define DEC_183 182 -#define DEC_182 181 -#define DEC_181 180 -#define DEC_180 179 -#define DEC_179 178 -#define DEC_178 177 -#define DEC_177 176 -#define DEC_176 175 -#define DEC_175 174 -#define DEC_174 173 -#define DEC_173 172 -#define DEC_172 171 -#define DEC_171 170 -#define DEC_170 169 -#define DEC_169 168 -#define DEC_168 167 -#define DEC_167 166 -#define DEC_166 165 -#define DEC_165 164 -#define DEC_164 163 -#define DEC_163 162 -#define DEC_162 161 -#define DEC_161 160 -#define DEC_160 159 -#define DEC_159 158 -#define DEC_158 157 -#define DEC_157 156 -#define DEC_156 155 -#define DEC_155 154 -#define DEC_154 153 -#define DEC_153 152 -#define DEC_152 151 -#define DEC_151 150 -#define DEC_150 149 -#define DEC_149 148 -#define DEC_148 147 -#define DEC_147 146 -#define DEC_146 145 -#define DEC_145 144 -#define DEC_144 143 -#define DEC_143 142 -#define DEC_142 141 -#define DEC_141 140 -#define DEC_140 139 -#define DEC_139 138 -#define DEC_138 137 -#define DEC_137 136 -#define DEC_136 135 -#define DEC_135 134 -#define DEC_134 133 -#define DEC_133 132 -#define DEC_132 131 -#define DEC_131 130 -#define DEC_130 129 -#define DEC_129 128 -#define DEC_128 127 -#define DEC_127 126 -#define DEC_126 125 -#define DEC_125 124 -#define DEC_124 123 -#define DEC_123 122 -#define DEC_122 121 -#define DEC_121 120 -#define DEC_120 119 -#define DEC_119 118 -#define DEC_118 117 -#define DEC_117 116 -#define DEC_116 115 -#define DEC_115 114 -#define DEC_114 113 -#define DEC_113 112 -#define DEC_112 111 -#define DEC_111 110 -#define DEC_110 109 -#define DEC_109 108 -#define DEC_108 107 -#define DEC_107 106 -#define DEC_106 105 -#define DEC_105 104 -#define DEC_104 103 -#define DEC_103 102 -#define DEC_102 101 -#define DEC_101 100 -#define DEC_100 99 -#define DEC_99 98 -#define DEC_98 97 -#define DEC_97 96 -#define DEC_96 95 -#define DEC_95 94 -#define DEC_94 93 -#define DEC_93 92 -#define DEC_92 91 -#define DEC_91 90 -#define DEC_90 89 -#define DEC_89 88 -#define DEC_88 87 -#define DEC_87 86 -#define DEC_86 85 -#define DEC_85 84 -#define DEC_84 83 -#define DEC_83 82 -#define DEC_82 81 -#define DEC_81 80 -#define DEC_80 79 -#define DEC_79 78 -#define DEC_78 77 -#define DEC_77 76 -#define DEC_76 75 -#define DEC_75 74 -#define DEC_74 73 -#define DEC_73 72 -#define DEC_72 71 -#define DEC_71 70 -#define DEC_70 69 -#define DEC_69 68 -#define DEC_68 67 -#define DEC_67 66 -#define DEC_66 65 -#define DEC_65 64 -#define DEC_64 63 -#define DEC_63 62 -#define DEC_62 61 -#define DEC_61 60 -#define DEC_60 59 -#define DEC_59 58 -#define DEC_58 57 -#define DEC_57 56 -#define DEC_56 55 -#define DEC_55 54 -#define DEC_54 53 -#define DEC_53 52 -#define DEC_52 51 -#define DEC_51 50 -#define DEC_50 49 -#define DEC_49 48 -#define DEC_48 47 -#define DEC_47 46 -#define DEC_46 45 -#define DEC_45 44 -#define DEC_44 43 -#define DEC_43 42 -#define DEC_42 41 -#define DEC_41 40 -#define DEC_40 39 -#define DEC_39 38 -#define DEC_38 37 -#define DEC_37 36 -#define DEC_36 35 -#define DEC_35 34 -#define DEC_34 33 -#define DEC_33 32 -#define DEC_32 31 -#define DEC_31 30 -#define DEC_30 29 -#define DEC_29 28 -#define DEC_28 27 -#define DEC_27 26 -#define DEC_26 25 -#define DEC_25 24 -#define DEC_24 23 -#define DEC_23 22 -#define DEC_22 21 -#define DEC_21 20 -#define DEC_20 19 -#define DEC_19 18 -#define DEC_18 17 -#define DEC_17 16 -#define DEC_16 15 -#define DEC_15 14 -#define DEC_14 13 -#define DEC_13 12 -#define DEC_12 11 -#define DEC_11 10 -#define DEC_10 9 -#define DEC_9 8 -#define DEC_8 7 -#define DEC_7 6 -#define DEC_6 5 -#define DEC_5 4 -#define DEC_4 3 -#define DEC_3 2 -#define DEC_2 1 -#define DEC_1 0 -#define DEC_(n) DEC_##n - - -/** Maximal number of repetitions supported by MRECURSION. */ -#define MRECURSION_LIMIT 256 - -/** \brief Macro recursion. - * - * This macro represents a horizontal repetition construct. - * - * \param[in] count The number of repetitious calls to macro. Valid values - * range from 0 to MRECURSION_LIMIT. - * \param[in] macro A binary operation of the form macro(data, n). This macro - * is expanded by MRECURSION with the current repetition number - * and the auxiliary data argument. - * \param[in] data A recursive threshold, building on this to decline by times - * defined with param count. - * - * \return macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1) - */ -#define MRECURSION(count, macro, data) TPASTE2(MRECURSION, count) (macro, data) - -#define MRECURSION0( macro, data) -#define MRECURSION1( macro, data) MRECURSION0( macro, DEC_(data)) macro(data, 0) -#define MRECURSION2( macro, data) MRECURSION1( macro, DEC_(data)) macro(data, 1) -#define MRECURSION3( macro, data) MRECURSION2( macro, DEC_(data)) macro(data, 2) -#define MRECURSION4( macro, data) MRECURSION3( macro, DEC_(data)) macro(data, 3) -#define MRECURSION5( macro, data) MRECURSION4( macro, DEC_(data)) macro(data, 4) -#define MRECURSION6( macro, data) MRECURSION5( macro, DEC_(data)) macro(data, 5) -#define MRECURSION7( macro, data) MRECURSION6( macro, DEC_(data)) macro(data, 6) -#define MRECURSION8( macro, data) MRECURSION7( macro, DEC_(data)) macro(data, 7) -#define MRECURSION9( macro, data) MRECURSION8( macro, DEC_(data)) macro(data, 8) -#define MRECURSION10( macro, data) MRECURSION9( macro, DEC_(data)) macro(data, 9) -#define MRECURSION11( macro, data) MRECURSION10( macro, DEC_(data)) macro(data, 10) -#define MRECURSION12( macro, data) MRECURSION11( macro, DEC_(data)) macro(data, 11) -#define MRECURSION13( macro, data) MRECURSION12( macro, DEC_(data)) macro(data, 12) -#define MRECURSION14( macro, data) MRECURSION13( macro, DEC_(data)) macro(data, 13) -#define MRECURSION15( macro, data) MRECURSION14( macro, DEC_(data)) macro(data, 14) -#define MRECURSION16( macro, data) MRECURSION15( macro, DEC_(data)) macro(data, 15) -#define MRECURSION17( macro, data) MRECURSION16( macro, DEC_(data)) macro(data, 16) -#define MRECURSION18( macro, data) MRECURSION17( macro, DEC_(data)) macro(data, 17) -#define MRECURSION19( macro, data) MRECURSION18( macro, DEC_(data)) macro(data, 18) -#define MRECURSION20( macro, data) MRECURSION19( macro, DEC_(data)) macro(data, 19) -#define MRECURSION21( macro, data) MRECURSION20( macro, DEC_(data)) macro(data, 20) -#define MRECURSION22( macro, data) MRECURSION21( macro, DEC_(data)) macro(data, 21) -#define MRECURSION23( macro, data) MRECURSION22( macro, DEC_(data)) macro(data, 22) -#define MRECURSION24( macro, data) MRECURSION23( macro, DEC_(data)) macro(data, 23) -#define MRECURSION25( macro, data) MRECURSION24( macro, DEC_(data)) macro(data, 24) -#define MRECURSION26( macro, data) MRECURSION25( macro, DEC_(data)) macro(data, 25) -#define MRECURSION27( macro, data) MRECURSION26( macro, DEC_(data)) macro(data, 26) -#define MRECURSION28( macro, data) MRECURSION27( macro, DEC_(data)) macro(data, 27) -#define MRECURSION29( macro, data) MRECURSION28( macro, DEC_(data)) macro(data, 28) -#define MRECURSION30( macro, data) MRECURSION29( macro, DEC_(data)) macro(data, 29) -#define MRECURSION31( macro, data) MRECURSION30( macro, DEC_(data)) macro(data, 30) -#define MRECURSION32( macro, data) MRECURSION31( macro, DEC_(data)) macro(data, 31) -#define MRECURSION33( macro, data) MRECURSION32( macro, DEC_(data)) macro(data, 32) -#define MRECURSION34( macro, data) MRECURSION33( macro, DEC_(data)) macro(data, 33) -#define MRECURSION35( macro, data) MRECURSION34( macro, DEC_(data)) macro(data, 34) -#define MRECURSION36( macro, data) MRECURSION35( macro, DEC_(data)) macro(data, 35) -#define MRECURSION37( macro, data) MRECURSION36( macro, DEC_(data)) macro(data, 36) -#define MRECURSION38( macro, data) MRECURSION37( macro, DEC_(data)) macro(data, 37) -#define MRECURSION39( macro, data) MRECURSION38( macro, DEC_(data)) macro(data, 38) -#define MRECURSION40( macro, data) MRECURSION39( macro, DEC_(data)) macro(data, 39) -#define MRECURSION41( macro, data) MRECURSION40( macro, DEC_(data)) macro(data, 40) -#define MRECURSION42( macro, data) MRECURSION41( macro, DEC_(data)) macro(data, 41) -#define MRECURSION43( macro, data) MRECURSION42( macro, DEC_(data)) macro(data, 42) -#define MRECURSION44( macro, data) MRECURSION43( macro, DEC_(data)) macro(data, 43) -#define MRECURSION45( macro, data) MRECURSION44( macro, DEC_(data)) macro(data, 44) -#define MRECURSION46( macro, data) MRECURSION45( macro, DEC_(data)) macro(data, 45) -#define MRECURSION47( macro, data) MRECURSION46( macro, DEC_(data)) macro(data, 46) -#define MRECURSION48( macro, data) MRECURSION47( macro, DEC_(data)) macro(data, 47) -#define MRECURSION49( macro, data) MRECURSION48( macro, DEC_(data)) macro(data, 48) -#define MRECURSION50( macro, data) MRECURSION49( macro, DEC_(data)) macro(data, 49) -#define MRECURSION51( macro, data) MRECURSION50( macro, DEC_(data)) macro(data, 50) -#define MRECURSION52( macro, data) MRECURSION51( macro, DEC_(data)) macro(data, 51) -#define MRECURSION53( macro, data) MRECURSION52( macro, DEC_(data)) macro(data, 52) -#define MRECURSION54( macro, data) MRECURSION53( macro, DEC_(data)) macro(data, 53) -#define MRECURSION55( macro, data) MRECURSION54( macro, DEC_(data)) macro(data, 54) -#define MRECURSION56( macro, data) MRECURSION55( macro, DEC_(data)) macro(data, 55) -#define MRECURSION57( macro, data) MRECURSION56( macro, DEC_(data)) macro(data, 56) -#define MRECURSION58( macro, data) MRECURSION57( macro, DEC_(data)) macro(data, 57) -#define MRECURSION59( macro, data) MRECURSION58( macro, DEC_(data)) macro(data, 58) -#define MRECURSION60( macro, data) MRECURSION59( macro, DEC_(data)) macro(data, 59) -#define MRECURSION61( macro, data) MRECURSION60( macro, DEC_(data)) macro(data, 60) -#define MRECURSION62( macro, data) MRECURSION61( macro, DEC_(data)) macro(data, 61) -#define MRECURSION63( macro, data) MRECURSION62( macro, DEC_(data)) macro(data, 62) -#define MRECURSION64( macro, data) MRECURSION63( macro, DEC_(data)) macro(data, 63) -#define MRECURSION65( macro, data) MRECURSION64( macro, DEC_(data)) macro(data, 64) -#define MRECURSION66( macro, data) MRECURSION65( macro, DEC_(data)) macro(data, 65) -#define MRECURSION67( macro, data) MRECURSION66( macro, DEC_(data)) macro(data, 66) -#define MRECURSION68( macro, data) MRECURSION67( macro, DEC_(data)) macro(data, 67) -#define MRECURSION69( macro, data) MRECURSION68( macro, DEC_(data)) macro(data, 68) -#define MRECURSION70( macro, data) MRECURSION69( macro, DEC_(data)) macro(data, 69) -#define MRECURSION71( macro, data) MRECURSION70( macro, DEC_(data)) macro(data, 70) -#define MRECURSION72( macro, data) MRECURSION71( macro, DEC_(data)) macro(data, 71) -#define MRECURSION73( macro, data) MRECURSION72( macro, DEC_(data)) macro(data, 72) -#define MRECURSION74( macro, data) MRECURSION73( macro, DEC_(data)) macro(data, 73) -#define MRECURSION75( macro, data) MRECURSION74( macro, DEC_(data)) macro(data, 74) -#define MRECURSION76( macro, data) MRECURSION75( macro, DEC_(data)) macro(data, 75) -#define MRECURSION77( macro, data) MRECURSION76( macro, DEC_(data)) macro(data, 76) -#define MRECURSION78( macro, data) MRECURSION77( macro, DEC_(data)) macro(data, 77) -#define MRECURSION79( macro, data) MRECURSION78( macro, DEC_(data)) macro(data, 78) -#define MRECURSION80( macro, data) MRECURSION79( macro, DEC_(data)) macro(data, 79) -#define MRECURSION81( macro, data) MRECURSION80( macro, DEC_(data)) macro(data, 80) -#define MRECURSION82( macro, data) MRECURSION81( macro, DEC_(data)) macro(data, 81) -#define MRECURSION83( macro, data) MRECURSION82( macro, DEC_(data)) macro(data, 82) -#define MRECURSION84( macro, data) MRECURSION83( macro, DEC_(data)) macro(data, 83) -#define MRECURSION85( macro, data) MRECURSION84( macro, DEC_(data)) macro(data, 84) -#define MRECURSION86( macro, data) MRECURSION85( macro, DEC_(data)) macro(data, 85) -#define MRECURSION87( macro, data) MRECURSION86( macro, DEC_(data)) macro(data, 86) -#define MRECURSION88( macro, data) MRECURSION87( macro, DEC_(data)) macro(data, 87) -#define MRECURSION89( macro, data) MRECURSION88( macro, DEC_(data)) macro(data, 88) -#define MRECURSION90( macro, data) MRECURSION89( macro, DEC_(data)) macro(data, 89) -#define MRECURSION91( macro, data) MRECURSION90( macro, DEC_(data)) macro(data, 90) -#define MRECURSION92( macro, data) MRECURSION91( macro, DEC_(data)) macro(data, 91) -#define MRECURSION93( macro, data) MRECURSION92( macro, DEC_(data)) macro(data, 92) -#define MRECURSION94( macro, data) MRECURSION93( macro, DEC_(data)) macro(data, 93) -#define MRECURSION95( macro, data) MRECURSION94( macro, DEC_(data)) macro(data, 94) -#define MRECURSION96( macro, data) MRECURSION95( macro, DEC_(data)) macro(data, 95) -#define MRECURSION97( macro, data) MRECURSION96( macro, DEC_(data)) macro(data, 96) -#define MRECURSION98( macro, data) MRECURSION97( macro, DEC_(data)) macro(data, 97) -#define MRECURSION99( macro, data) MRECURSION98( macro, DEC_(data)) macro(data, 98) -#define MRECURSION100(macro, data) MRECURSION99( macro, DEC_(data)) macro(data, 99) -#define MRECURSION101(macro, data) MRECURSION100( macro, DEC_(data)) macro(data, 100) -#define MRECURSION102(macro, data) MRECURSION101( macro, DEC_(data)) macro(data, 101) -#define MRECURSION103(macro, data) MRECURSION102( macro, DEC_(data)) macro(data, 102) -#define MRECURSION104(macro, data) MRECURSION103( macro, DEC_(data)) macro(data, 103) -#define MRECURSION105(macro, data) MRECURSION104( macro, DEC_(data)) macro(data, 104) -#define MRECURSION106(macro, data) MRECURSION105( macro, DEC_(data)) macro(data, 105) -#define MRECURSION107(macro, data) MRECURSION106( macro, DEC_(data)) macro(data, 106) -#define MRECURSION108(macro, data) MRECURSION107( macro, DEC_(data)) macro(data, 107) -#define MRECURSION109(macro, data) MRECURSION108( macro, DEC_(data)) macro(data, 108) -#define MRECURSION110(macro, data) MRECURSION109( macro, DEC_(data)) macro(data, 109) -#define MRECURSION111(macro, data) MRECURSION110( macro, DEC_(data)) macro(data, 110) -#define MRECURSION112(macro, data) MRECURSION111( macro, DEC_(data)) macro(data, 111) -#define MRECURSION113(macro, data) MRECURSION112( macro, DEC_(data)) macro(data, 112) -#define MRECURSION114(macro, data) MRECURSION113( macro, DEC_(data)) macro(data, 113) -#define MRECURSION115(macro, data) MRECURSION114( macro, DEC_(data)) macro(data, 114) -#define MRECURSION116(macro, data) MRECURSION115( macro, DEC_(data)) macro(data, 115) -#define MRECURSION117(macro, data) MRECURSION116( macro, DEC_(data)) macro(data, 116) -#define MRECURSION118(macro, data) MRECURSION117( macro, DEC_(data)) macro(data, 117) -#define MRECURSION119(macro, data) MRECURSION118( macro, DEC_(data)) macro(data, 118) -#define MRECURSION120(macro, data) MRECURSION119( macro, DEC_(data)) macro(data, 119) -#define MRECURSION121(macro, data) MRECURSION120( macro, DEC_(data)) macro(data, 120) -#define MRECURSION122(macro, data) MRECURSION121( macro, DEC_(data)) macro(data, 121) -#define MRECURSION123(macro, data) MRECURSION122( macro, DEC_(data)) macro(data, 122) -#define MRECURSION124(macro, data) MRECURSION123( macro, DEC_(data)) macro(data, 123) -#define MRECURSION125(macro, data) MRECURSION124( macro, DEC_(data)) macro(data, 124) -#define MRECURSION126(macro, data) MRECURSION125( macro, DEC_(data)) macro(data, 125) -#define MRECURSION127(macro, data) MRECURSION126( macro, DEC_(data)) macro(data, 126) -#define MRECURSION128(macro, data) MRECURSION127( macro, DEC_(data)) macro(data, 127) -#define MRECURSION129(macro, data) MRECURSION128( macro, DEC_(data)) macro(data, 128) -#define MRECURSION130(macro, data) MRECURSION129( macro, DEC_(data)) macro(data, 129) -#define MRECURSION131(macro, data) MRECURSION130( macro, DEC_(data)) macro(data, 130) -#define MRECURSION132(macro, data) MRECURSION131( macro, DEC_(data)) macro(data, 131) -#define MRECURSION133(macro, data) MRECURSION132( macro, DEC_(data)) macro(data, 132) -#define MRECURSION134(macro, data) MRECURSION133( macro, DEC_(data)) macro(data, 133) -#define MRECURSION135(macro, data) MRECURSION134( macro, DEC_(data)) macro(data, 134) -#define MRECURSION136(macro, data) MRECURSION135( macro, DEC_(data)) macro(data, 135) -#define MRECURSION137(macro, data) MRECURSION136( macro, DEC_(data)) macro(data, 136) -#define MRECURSION138(macro, data) MRECURSION137( macro, DEC_(data)) macro(data, 137) -#define MRECURSION139(macro, data) MRECURSION138( macro, DEC_(data)) macro(data, 138) -#define MRECURSION140(macro, data) MRECURSION139( macro, DEC_(data)) macro(data, 139) -#define MRECURSION141(macro, data) MRECURSION140( macro, DEC_(data)) macro(data, 140) -#define MRECURSION142(macro, data) MRECURSION141( macro, DEC_(data)) macro(data, 141) -#define MRECURSION143(macro, data) MRECURSION142( macro, DEC_(data)) macro(data, 142) -#define MRECURSION144(macro, data) MRECURSION143( macro, DEC_(data)) macro(data, 143) -#define MRECURSION145(macro, data) MRECURSION144( macro, DEC_(data)) macro(data, 144) -#define MRECURSION146(macro, data) MRECURSION145( macro, DEC_(data)) macro(data, 145) -#define MRECURSION147(macro, data) MRECURSION146( macro, DEC_(data)) macro(data, 146) -#define MRECURSION148(macro, data) MRECURSION147( macro, DEC_(data)) macro(data, 147) -#define MRECURSION149(macro, data) MRECURSION148( macro, DEC_(data)) macro(data, 148) -#define MRECURSION150(macro, data) MRECURSION149( macro, DEC_(data)) macro(data, 149) -#define MRECURSION151(macro, data) MRECURSION150( macro, DEC_(data)) macro(data, 150) -#define MRECURSION152(macro, data) MRECURSION151( macro, DEC_(data)) macro(data, 151) -#define MRECURSION153(macro, data) MRECURSION152( macro, DEC_(data)) macro(data, 152) -#define MRECURSION154(macro, data) MRECURSION153( macro, DEC_(data)) macro(data, 153) -#define MRECURSION155(macro, data) MRECURSION154( macro, DEC_(data)) macro(data, 154) -#define MRECURSION156(macro, data) MRECURSION155( macro, DEC_(data)) macro(data, 155) -#define MRECURSION157(macro, data) MRECURSION156( macro, DEC_(data)) macro(data, 156) -#define MRECURSION158(macro, data) MRECURSION157( macro, DEC_(data)) macro(data, 157) -#define MRECURSION159(macro, data) MRECURSION158( macro, DEC_(data)) macro(data, 158) -#define MRECURSION160(macro, data) MRECURSION159( macro, DEC_(data)) macro(data, 159) -#define MRECURSION161(macro, data) MRECURSION160( macro, DEC_(data)) macro(data, 160) -#define MRECURSION162(macro, data) MRECURSION161( macro, DEC_(data)) macro(data, 161) -#define MRECURSION163(macro, data) MRECURSION162( macro, DEC_(data)) macro(data, 162) -#define MRECURSION164(macro, data) MRECURSION163( macro, DEC_(data)) macro(data, 163) -#define MRECURSION165(macro, data) MRECURSION164( macro, DEC_(data)) macro(data, 164) -#define MRECURSION166(macro, data) MRECURSION165( macro, DEC_(data)) macro(data, 165) -#define MRECURSION167(macro, data) MRECURSION166( macro, DEC_(data)) macro(data, 166) -#define MRECURSION168(macro, data) MRECURSION167( macro, DEC_(data)) macro(data, 167) -#define MRECURSION169(macro, data) MRECURSION168( macro, DEC_(data)) macro(data, 168) -#define MRECURSION170(macro, data) MRECURSION169( macro, DEC_(data)) macro(data, 169) -#define MRECURSION171(macro, data) MRECURSION170( macro, DEC_(data)) macro(data, 170) -#define MRECURSION172(macro, data) MRECURSION171( macro, DEC_(data)) macro(data, 171) -#define MRECURSION173(macro, data) MRECURSION172( macro, DEC_(data)) macro(data, 172) -#define MRECURSION174(macro, data) MRECURSION173( macro, DEC_(data)) macro(data, 173) -#define MRECURSION175(macro, data) MRECURSION174( macro, DEC_(data)) macro(data, 174) -#define MRECURSION176(macro, data) MRECURSION175( macro, DEC_(data)) macro(data, 175) -#define MRECURSION177(macro, data) MRECURSION176( macro, DEC_(data)) macro(data, 176) -#define MRECURSION178(macro, data) MRECURSION177( macro, DEC_(data)) macro(data, 177) -#define MRECURSION179(macro, data) MRECURSION178( macro, DEC_(data)) macro(data, 178) -#define MRECURSION180(macro, data) MRECURSION179( macro, DEC_(data)) macro(data, 179) -#define MRECURSION181(macro, data) MRECURSION180( macro, DEC_(data)) macro(data, 180) -#define MRECURSION182(macro, data) MRECURSION181( macro, DEC_(data)) macro(data, 181) -#define MRECURSION183(macro, data) MRECURSION182( macro, DEC_(data)) macro(data, 182) -#define MRECURSION184(macro, data) MRECURSION183( macro, DEC_(data)) macro(data, 183) -#define MRECURSION185(macro, data) MRECURSION184( macro, DEC_(data)) macro(data, 184) -#define MRECURSION186(macro, data) MRECURSION185( macro, DEC_(data)) macro(data, 185) -#define MRECURSION187(macro, data) MRECURSION186( macro, DEC_(data)) macro(data, 186) -#define MRECURSION188(macro, data) MRECURSION187( macro, DEC_(data)) macro(data, 187) -#define MRECURSION189(macro, data) MRECURSION188( macro, DEC_(data)) macro(data, 188) -#define MRECURSION190(macro, data) MRECURSION189( macro, DEC_(data)) macro(data, 189) -#define MRECURSION191(macro, data) MRECURSION190( macro, DEC_(data)) macro(data, 190) -#define MRECURSION192(macro, data) MRECURSION191( macro, DEC_(data)) macro(data, 191) -#define MRECURSION193(macro, data) MRECURSION192( macro, DEC_(data)) macro(data, 192) -#define MRECURSION194(macro, data) MRECURSION193( macro, DEC_(data)) macro(data, 193) -#define MRECURSION195(macro, data) MRECURSION194( macro, DEC_(data)) macro(data, 194) -#define MRECURSION196(macro, data) MRECURSION195( macro, DEC_(data)) macro(data, 195) -#define MRECURSION197(macro, data) MRECURSION196( macro, DEC_(data)) macro(data, 196) -#define MRECURSION198(macro, data) MRECURSION197( macro, DEC_(data)) macro(data, 197) -#define MRECURSION199(macro, data) MRECURSION198( macro, DEC_(data)) macro(data, 198) -#define MRECURSION200(macro, data) MRECURSION199( macro, DEC_(data)) macro(data, 199) -#define MRECURSION201(macro, data) MRECURSION200( macro, DEC_(data)) macro(data, 200) -#define MRECURSION202(macro, data) MRECURSION201( macro, DEC_(data)) macro(data, 201) -#define MRECURSION203(macro, data) MRECURSION202( macro, DEC_(data)) macro(data, 202) -#define MRECURSION204(macro, data) MRECURSION203( macro, DEC_(data)) macro(data, 203) -#define MRECURSION205(macro, data) MRECURSION204( macro, DEC_(data)) macro(data, 204) -#define MRECURSION206(macro, data) MRECURSION205( macro, DEC_(data)) macro(data, 205) -#define MRECURSION207(macro, data) MRECURSION206( macro, DEC_(data)) macro(data, 206) -#define MRECURSION208(macro, data) MRECURSION207( macro, DEC_(data)) macro(data, 207) -#define MRECURSION209(macro, data) MRECURSION208( macro, DEC_(data)) macro(data, 208) -#define MRECURSION210(macro, data) MRECURSION209( macro, DEC_(data)) macro(data, 209) -#define MRECURSION211(macro, data) MRECURSION210( macro, DEC_(data)) macro(data, 210) -#define MRECURSION212(macro, data) MRECURSION211( macro, DEC_(data)) macro(data, 211) -#define MRECURSION213(macro, data) MRECURSION212( macro, DEC_(data)) macro(data, 212) -#define MRECURSION214(macro, data) MRECURSION213( macro, DEC_(data)) macro(data, 213) -#define MRECURSION215(macro, data) MRECURSION214( macro, DEC_(data)) macro(data, 214) -#define MRECURSION216(macro, data) MRECURSION215( macro, DEC_(data)) macro(data, 215) -#define MRECURSION217(macro, data) MRECURSION216( macro, DEC_(data)) macro(data, 216) -#define MRECURSION218(macro, data) MRECURSION217( macro, DEC_(data)) macro(data, 217) -#define MRECURSION219(macro, data) MRECURSION218( macro, DEC_(data)) macro(data, 218) -#define MRECURSION220(macro, data) MRECURSION219( macro, DEC_(data)) macro(data, 219) -#define MRECURSION221(macro, data) MRECURSION220( macro, DEC_(data)) macro(data, 220) -#define MRECURSION222(macro, data) MRECURSION221( macro, DEC_(data)) macro(data, 221) -#define MRECURSION223(macro, data) MRECURSION222( macro, DEC_(data)) macro(data, 222) -#define MRECURSION224(macro, data) MRECURSION223( macro, DEC_(data)) macro(data, 223) -#define MRECURSION225(macro, data) MRECURSION224( macro, DEC_(data)) macro(data, 224) -#define MRECURSION226(macro, data) MRECURSION225( macro, DEC_(data)) macro(data, 225) -#define MRECURSION227(macro, data) MRECURSION226( macro, DEC_(data)) macro(data, 226) -#define MRECURSION228(macro, data) MRECURSION227( macro, DEC_(data)) macro(data, 227) -#define MRECURSION229(macro, data) MRECURSION228( macro, DEC_(data)) macro(data, 228) -#define MRECURSION230(macro, data) MRECURSION229( macro, DEC_(data)) macro(data, 229) -#define MRECURSION231(macro, data) MRECURSION230( macro, DEC_(data)) macro(data, 230) -#define MRECURSION232(macro, data) MRECURSION231( macro, DEC_(data)) macro(data, 231) -#define MRECURSION233(macro, data) MRECURSION232( macro, DEC_(data)) macro(data, 232) -#define MRECURSION234(macro, data) MRECURSION233( macro, DEC_(data)) macro(data, 233) -#define MRECURSION235(macro, data) MRECURSION234( macro, DEC_(data)) macro(data, 234) -#define MRECURSION236(macro, data) MRECURSION235( macro, DEC_(data)) macro(data, 235) -#define MRECURSION237(macro, data) MRECURSION236( macro, DEC_(data)) macro(data, 236) -#define MRECURSION238(macro, data) MRECURSION237( macro, DEC_(data)) macro(data, 237) -#define MRECURSION239(macro, data) MRECURSION238( macro, DEC_(data)) macro(data, 238) -#define MRECURSION240(macro, data) MRECURSION239( macro, DEC_(data)) macro(data, 239) -#define MRECURSION241(macro, data) MRECURSION240( macro, DEC_(data)) macro(data, 240) -#define MRECURSION242(macro, data) MRECURSION241( macro, DEC_(data)) macro(data, 241) -#define MRECURSION243(macro, data) MRECURSION242( macro, DEC_(data)) macro(data, 242) -#define MRECURSION244(macro, data) MRECURSION243( macro, DEC_(data)) macro(data, 243) -#define MRECURSION245(macro, data) MRECURSION244( macro, DEC_(data)) macro(data, 244) -#define MRECURSION246(macro, data) MRECURSION245( macro, DEC_(data)) macro(data, 245) -#define MRECURSION247(macro, data) MRECURSION246( macro, DEC_(data)) macro(data, 246) -#define MRECURSION248(macro, data) MRECURSION247( macro, DEC_(data)) macro(data, 247) -#define MRECURSION249(macro, data) MRECURSION248( macro, DEC_(data)) macro(data, 248) -#define MRECURSION250(macro, data) MRECURSION249( macro, DEC_(data)) macro(data, 249) -#define MRECURSION251(macro, data) MRECURSION250( macro, DEC_(data)) macro(data, 250) -#define MRECURSION252(macro, data) MRECURSION251( macro, DEC_(data)) macro(data, 251) -#define MRECURSION253(macro, data) MRECURSION252( macro, DEC_(data)) macro(data, 252) -#define MRECURSION254(macro, data) MRECURSION253( macro, DEC_(data)) macro(data, 253) -#define MRECURSION255(macro, data) MRECURSION254( macro, DEC_(data)) macro(data, 254) -#define MRECURSION256(macro, data) MRECURSION255( macro, DEC_(data)) macro(data, 255) - -/** @} */ - -#endif /* _MRECURSION_H_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrepeat.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrepeat.h deleted file mode 100644 index 42d3f362ee0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrepeat.h +++ /dev/null @@ -1,292 +0,0 @@ -#ifndef _MREPEAT_H_ -#define _MREPEAT_H_ - -/** - * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat - * - * \ingroup group_sam0_utils - * - * @{ - */ - -#include "preprocessor.h" - -/** Maximal number of repetitions supported by MREPEAT. */ -#define MREPEAT_LIMIT 256 - -/** \brief Macro repeat. - * - * This macro represents a horizontal repetition construct. - * - * \param[in] count The number of repetitious calls to macro. Valid values - * range from 0 to MREPEAT_LIMIT. - * \param[in] macro A binary operation of the form macro(n, data). This macro - * is expanded by MREPEAT with the current repetition number - * and the auxiliary data argument. - * \param[in] data Auxiliary data passed to macro. - * - * \return macro(0, data) macro(1, data) ... macro(count - 1, data) - */ -#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data) - -#define MREPEAT0( macro, data) -#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) -#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) -#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) -#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) -#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) -#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) -#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) -#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) -#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) -#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) -#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) -#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) -#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) -#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) -#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) -#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) -#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) -#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) -#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) -#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) -#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) -#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) -#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) -#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) -#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) -#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) -#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) -#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) -#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) -#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) -#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) -#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) -#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) -#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) -#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) -#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) -#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) -#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) -#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) -#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) -#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) -#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) -#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) -#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) -#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) -#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) -#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) -#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) -#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) -#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) -#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) -#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) -#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) -#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) -#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) -#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) -#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) -#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) -#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) -#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) -#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) -#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) -#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) -#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) -#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) -#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) -#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) -#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) -#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) -#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) -#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) -#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) -#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) -#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) -#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) -#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) -#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) -#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) -#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) -#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) -#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) -#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) -#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) -#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) -#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) -#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) -#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) -#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) -#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) -#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) -#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) -#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) -#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) -#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) -#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) -#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) -#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) -#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) -#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) -#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) -#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) -#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) -#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) -#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) -#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) -#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) -#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) -#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) -#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) -#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) -#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) -#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) -#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) -#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) -#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) -#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) -#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) -#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) -#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) -#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) -#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) -#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) -#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) -#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) -#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) -#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) -#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) -#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) -#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) -#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) -#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) -#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) -#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) -#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) -#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) -#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) -#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) -#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) -#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) -#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) -#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) -#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) -#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) -#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) -#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) -#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) -#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) -#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) -#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) -#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) -#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) -#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) -#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) -#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) -#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) -#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) -#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) -#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) -#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) -#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) -#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) -#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) -#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) -#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) -#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) -#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) -#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) -#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) -#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) -#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) -#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) -#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) -#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) -#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) -#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) -#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) -#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) -#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) -#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) -#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) -#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) -#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) -#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) -#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) -#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) -#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) -#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) -#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) -#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) -#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) -#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) -#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) -#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) -#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) -#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) -#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) -#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) -#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) -#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) -#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) -#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) -#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) -#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) -#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) -#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) -#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) -#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) -#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) -#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) -#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) -#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) -#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) -#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) -#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) -#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) -#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) -#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) -#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) -#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) -#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) -#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) -#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) -#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) -#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) -#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) -#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) -#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) -#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) -#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) -#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) -#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) -#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) -#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) -#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) -#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) -#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) -#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) -#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) -#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) -#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) -#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) -#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) -#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) -#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) -#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) -#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) -#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) -#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) -#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) -#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) -#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) -#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) -#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) -#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) -#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) -#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) - -/** @} */ - -#endif /* _MREPEAT_H_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/preprocessor.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/preprocessor.h deleted file mode 100644 index 674211330f7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/preprocessor.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _PREPROCESSOR_H_ -#define _PREPROCESSOR_H_ - -#include "tpaste.h" -#include "stringz.h" -#include "mrepeat.h" -#include "mrecursion.h" - -#endif // _PREPROCESSOR_H_ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/stringz.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/stringz.h deleted file mode 100644 index 1141623de2b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/stringz.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef _STRINGZ_H_ -#define _STRINGZ_H_ - -/** - * \defgroup group_sam0_utils_stringz Preprocessor - Stringize - * - * \ingroup group_sam0_utils - * - * @{ - */ - -/** \brief Stringize. - * - * Stringize a preprocessing token, this token being allowed to be \#defined. - * - * May be used only within macros with the token passed as an argument if the - * token is \#defined. - * - * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) - * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to - * writing "A0". - */ -#define STRINGZ(x) #x - -/** \brief Absolute stringize. - * - * Stringize a preprocessing token, this token being allowed to be \#defined. - * - * No restriction of use if the token is \#defined. - * - * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is - * equivalent to writing "A0". - */ -#define ASTRINGZ(x) STRINGZ(x) - -/** @} */ - -#endif // _STRINGZ_H_ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/tpaste.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/tpaste.h deleted file mode 100644 index f974d72c5ca..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/tpaste.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef _TPASTE_H_ -#define _TPASTE_H_ - -/** - * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste - * - * \ingroup group_sam0_utils - * - * @{ - */ - -/** \name Token Paste - * - * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. - * - * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. - * - * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by - * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is - * equivalent to writing U32. - * - * @{ */ -#define TPASTE2( a, b) a##b -#define TPASTE3( a, b, c) a##b##c -#define TPASTE4( a, b, c, d) a##b##c##d -#define TPASTE5( a, b, c, d, e) a##b##c##d##e -#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f -#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g -#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h -#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i -#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j -/** @} */ - -/** \name Absolute Token Paste - * - * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. - * - * No restriction of use if the tokens are \#defined. - * - * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined - * as 32 is equivalent to writing U32. - * - * @{ */ -#define ATPASTE2( a, b) TPASTE2( a, b) -#define ATPASTE3( a, b, c) TPASTE3( a, b, c) -#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) -#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) -#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) -#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) -#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) -#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) -#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) -/** @} */ - -/** @} */ - -#endif // _TPASTE_H_ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/status_codes.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/status_codes.h deleted file mode 100644 index d3b2b183815..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/status_codes.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef STATUS_CODES_H_INCLUDED -#define STATUS_CODES_H_INCLUDED - -#include - -/** - * \defgroup group_sam0_utils_status_codes Status Codes - * - * \ingroup group_sam0_utils - * - * @{ - */ - -/** Mask to retrieve the error category of a status code. */ -#define STATUS_CATEGORY_MASK 0xF0 - -/** Mask to retrieve the error code within the category of a status code. */ -#define STATUS_ERROR_MASK 0x0F - -/** Status code error categories. */ -enum status_categories { - STATUS_CATEGORY_OK = 0x00, - STATUS_CATEGORY_COMMON = 0x10, - STATUS_CATEGORY_ANALOG = 0x30, - STATUS_CATEGORY_COM = 0x40, - STATUS_CATEGORY_IO = 0x50, -}; - -/** - * Status code that may be returned by shell commands and protocol - * implementations. - * - * \note Any change to these status codes and the corresponding - * message strings is strictly forbidden. New codes can be added, - * however, but make sure that any message string tables are updated - * at the same time. - */ -enum status_code { - STATUS_OK = STATUS_CATEGORY_OK | 0x00, - STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01, - STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02, - STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04, - STATUS_BUSY = STATUS_CATEGORY_OK | 0x05, - STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06, - - STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00, - STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01, - STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02, - STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03, - STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04, - STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05, - STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06, - STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07, - STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08, - STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A, - STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B, - STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c, - STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d, - STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e, - STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f, - - STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00, - STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01, - - STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00, - STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01, - STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02, - - STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00, -}; -typedef enum status_code status_code_genare_t; - -/** - Status codes used by MAC stack. - */ -enum status_code_wireless { - //STATUS_OK = 0, //!< Success - ERR_IO_ERROR = -1, //!< I/O error - ERR_FLUSHED = -2, //!< Request flushed from queue - ERR_TIMEOUT = -3, //!< Operation timed out - ERR_BAD_DATA = -4, //!< Data integrity check failed - ERR_PROTOCOL = -5, //!< Protocol error - ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device - ERR_NO_MEMORY = -7, //!< Insufficient memory - ERR_INVALID_ARG = -8, //!< Invalid argument - ERR_BAD_ADDRESS = -9, //!< Bad address - ERR_BUSY = -10, //!< Resource is busy - ERR_BAD_FORMAT = -11, //!< Data format not recognized - ERR_NO_TIMER = -12, //!< No timer available - ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running - ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running - - /** - * \brief Operation in progress - * - * This status code is for driver-internal use when an operation - * is currently being performed. - * - * \note Drivers should never return this status code to any - * callers. It is strictly for internal use. - */ - OPERATION_IN_PROGRESS = -128, -}; - -typedef enum status_code_wireless status_code_t; - -/** @} */ - -#endif /* STATUS_CODES_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/PortNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/PortNames.h deleted file mode 100644 index fc95f631e31..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/PortNames.h +++ /dev/null @@ -1,32 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, - PortMax -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/device/cmsis.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/device/cmsis.h deleted file mode 100644 index c0c7659dcca..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in samd21j18a specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "samg55.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/device/cmsis_nvic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/device/cmsis_nvic.h deleted file mode 100644 index 08fc2933aad..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/device/cmsis_nvic.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 50) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralNames.h deleted file mode 100644 index 78a21dd9689..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralNames.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)0x4000C200U, - UART_1 = (int)0x40020200U, - UART_2 = (int)0x40024200U, - UART_3 = (int)0x40018200U, - UART_4 = (int)0x4001C200U, - UART_5 = (int)0x40008200U, - UART_6 = (int)0x40040200U, - UART_7 = (int)0x40034200U, -} UARTName; - -typedef enum { - ADC_0 = 0, - ADC_1, - ADC_2, - ADC_3, - ADC_4, - ADC_5, - ADC_6, - ADC_7, -} ADCName; - - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_7 - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralPins.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralPins.c deleted file mode 100644 index 534f8c74b89..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralPins.c +++ /dev/null @@ -1,195 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - /* Not connected */ - {PA17, ADC_0, NC}, /*NC in mux posiotn since it is a extra function and doesnt have a name*/ - {PA18, ADC_1, NC}, /*Pin is multiplexed to the extra function once the corresponding ADC channel is enabled*/ - {PA19, ADC_2, NC}, - {PA20, ADC_3, NC}, - {PB00, ADC_4, NC}, - {PB01, ADC_5, NC}, - {PB02, ADC_6, NC}, - {PB03, ADC_7, NC}, - /* Not connected */ - {NC , NC , NC} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {PA03, UART_3, 0}, - {PA06, UART_2, 0}, - {PA10, UART_0, 0}, - {PA13, UART_5, 0}, - {PA28, UART_7, 1}, - {PB00, UART_6, 1}, - {PB03, UART_1, 0}, - {PB08, UART_4, 0}, - {PB10, UART_4, 0}, - {PB10, UART_6, 1}, - /* Not connected */ - {NC , NC , NC} -}; - -const PinMap PinMap_UART_RX[] = { - {PA04, UART_3, 0}, - {PA05, UART_2, 0}, - {PA09, UART_0, 0}, - {PA12, UART_5, 0}, - {PA27, UART_7, 1}, - {PB01, UART_6, 1}, - {PB02, UART_1, 0}, - {PB09, UART_4, 0}, - {PB11, UART_4, 0}, - {PB11, UART_6, 1}, - /* Not connected */ - {NC , NC , NC} -}; - -const PinMap PinMap_UART_CTS[] = { - {PA11, UART_5, 0}, - {PA16, UART_2, 0}, - {PA25, UART_0, 0}, - {PA28, UART_1, 0}, - {PA30, UART_7, 1}, - {PB08, UART_4, 1}, - {PB14, UART_3, 0}, - {PB14, UART_6, 1}, - /* Not connected */ - {NC , NC , NC} -}; - -const PinMap PinMap_UART_RTS[] = { - {PA15, UART_2, 0}, - {PA26, UART_0, 0}, - {PA29, UART_1, 0}, - {PA31, UART_7, 1}, - {PB02, UART_5, 1}, - {PB09, UART_4, 1}, - {PB15, UART_3, 0}, - {PB15, UART_6, 1}, - /* Not connected */ - {NC , NC , NC} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PB00, (int)SPI0, 0}, - {PA27, (int)SPI1, 0}, - {PA15, (int)SPI2, 1}, - {PA24, (int)SPI2, 1}, - {PB13, (int)SPI3, 0}, - {PB01, (int)SPI4, 0}, - {PA14, (int)SPI5, 0}, - {PB13, (int)SPI6, 1}, - {PA29, (int)SPI7, 1}, - /* Not connected */ - {NC , (int)NC , NC} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PA10, (int)SPI0, 0}, - {PB03, (int)SPI1, 0}, - {PA06, (int)SPI2, 0}, - {PA03, (int)SPI3, 0}, - {PB08, (int)SPI4, 0}, - {PB10, (int)SPI4, 0}, - {PA13, (int)SPI5, 0}, - {PB00, (int)SPI6, 1}, - {PB10, (int)SPI6, 1}, - {PA28, (int)SPI7, 1}, - /* Not connected */ - {NC , (int)NC , NC} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA09, (int)SPI0, 0}, - {PB02, (int)SPI1, 0}, - {PA05, (int)SPI2, 0}, - {PA04, (int)SPI3, 0}, - {PB09, (int)SPI4, 0}, - {PB11, (int)SPI4, 0}, - {PA12, (int)SPI5, 0}, - {PB01, (int)SPI6, 1}, - {PB11, (int)SPI6, 1}, - {PA27, (int)SPI7, 1}, - /* Not connected */ - {NC , (int)NC , NC} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PA10, (int)TWI0, 0}, - {PB03, (int)TWI1, 0}, - {PA06, (int)TWI2, 0}, - {PA03, (int)TWI3, 0}, - {PB08, (int)TWI4, 0}, - {PB10, (int)TWI4, 0}, - {PB10, (int)TWI6, 1}, - {PA13, (int)TWI5, 0}, - {PB00, (int)TWI6, 1}, - {PB10, (int)TWI6, 1}, - {PA28, (int)TWI7, 1}, - /* Not connected */ - {NC , NC , NC} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA09, (int)TWI0, 0}, - {PB02, (int)TWI1, 0}, - {PA05, (int)TWI2, 0}, - {PA04, (int)TWI3, 0}, - {PB09, (int)TWI4, 0}, - {PB11, (int)TWI4, 0}, - {PA12, (int)TWI5, 0}, - {PB01, (int)TWI6, 1}, - {PB11, (int)TWI6, 1}, - {PA27, (int)TWI7, 1}, - /* Not connected */ - {NC , NC , NC} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PA00, (int)TC0, 1}, - {PA23, (int)TC0, 1}, - {PA21, (int)TC0, 0}, - {PA01, (int)TC0, 1}, - {PA16, (int)TC0, 1}, - {PA22, (int)TC0, 0}, - /* Not connected */ - {NC , NC , NC} -}; - -/************PWM***************/ -const PinMap PinMap_PWM_IO_Line[] = { - {PA00, 0, 0}, - {PA23, 1, 0}, - {PA21, 2, 0}, - {PA01, 0, 1}, - {PA16, 1, 1}, - {PA22, 2, 1}, - /* Not connected */ - {NC , NC , NC} -}; - - - - - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralPins.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralPins.h deleted file mode 100644 index 347e21ae181..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralPins.h +++ /dev/null @@ -1,47 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************UART***************/ -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_CTS[]; -extern const PinMap PinMap_UART_RTS[]; - -/************SPI***************/ -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SSEL[]; -/************I2C***************/ -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; -extern const PinMap PinMap_PWM_IO_Line[]; - - - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PinNames.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PinNames.h deleted file mode 100644 index dbc1b2b6786..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PinNames.h +++ /dev/null @@ -1,105 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INPUT_OUTPUT //pin state can be set and read back -} PinDirection; - -typedef enum { - PA00 = 0, - PA01 = 1, - PA02 = 2, - PA03 = 3, - PA04 = 4, - PA05 = 5, - PA06 = 6, - PA07 = 7, - PA08 = 8, - PA09 = 9, - PA10 = 10, - PA11 = 11, - PA12 = 12, - PA13 = 13, - PA14 = 14, - PA15 = 15, - PA16 = 16, - PA17 = 17, - PA18 = 18, - PA19 = 19, - PA20 = 20, - PA21 = 21, - PA22 = 22, - PA23 = 23, - PA24 = 24, - PA25 = 25, - PA26 = 26, - PA27 = 27, - PA28 = 28, - PA29 = 29, - PA30 = 30, - PA31 = 31, - - PB00 = 32, - PB01 = 33, - PB02 = 34, - PB03 = 35, - PB04 = 36, - PB05 = 37, - PB06 = 38, - PB07 = 39, - PB08 = 40, - PB09 = 41, - PB10 = 42, - PB11 = 43, - PB12 = 44, - PB13 = 45, - PB14 = 46, - PB15 = 47, - - USBTX = PA28, - USBRX = PA27, - - LED1 = PA06, - LED2 = PA06, - LED3 = PA06, - LED4 = PA06, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/board_init.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/board_init.c deleted file mode 100644 index d5ca2520031..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/board_init.c +++ /dev/null @@ -1,228 +0,0 @@ -/** - * \file - * - * \brief SAMG55 Xplained Pro board initialization - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include -#include - -/** - * \addtogroup samg55_xplained_pro_group - * @{ - */ - -/** - * \brief Set peripheral mode for IOPORT pins. - * It will configure port mode and disable pin mode (but enable peripheral). - * \param port IOPORT port to configure - * \param masks IOPORT pin masks to configure - * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) - */ -#define ioport_set_port_peripheral_mode(port, masks, mode) \ - do {\ - ioport_set_port_mode(port, masks, mode);\ - ioport_disable_port(port, masks);\ - } while (0) - -/** - * \brief Set peripheral mode for one single IOPORT pin. - * It will configure port mode and disable pin mode (but enable peripheral). - * \param pin IOPORT pin to configure - * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) - */ -#define ioport_set_pin_peripheral_mode(pin, mode) \ - do {\ - ioport_set_pin_mode(pin, mode);\ - ioport_disable_pin(pin);\ - } while (0) - -#if defined(__GNUC__) -void board_init(void) WEAK __attribute__((alias("system_board_init"))); -#elif defined(__ICCARM__) -void board_init(void); -# pragma weak board_init=system_board_init -#endif - -void system_board_init(void) -{ - -#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT - WDT->WDT_MR = WDT_MR_WDDIS; -#endif - ioport_init(); - - /* Initialize LED0, turned off */ - ioport_set_pin_dir(LED_0_PIN, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(LED_0_PIN, IOPORT_PIN_LEVEL_HIGH); - - /* Initialize SW0 */ - ioport_set_pin_dir(BUTTON_0_PIN, IOPORT_DIR_INPUT); - ioport_set_pin_mode(BUTTON_0_PIN, IOPORT_MODE_PULLUP); - - /* Initialize EXT3 LED0, LED1 & LED2, turned off */ - ioport_set_pin_level(OLED1_LED1_PIN, !OLED1_LED1_ACTIVE); - ioport_set_pin_dir(OLED1_LED1_PIN, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(OLED1_LED2_PIN, !OLED1_LED2_ACTIVE); - ioport_set_pin_dir(OLED1_LED2_PIN, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(OLED1_LED3_PIN, !OLED1_LED3_ACTIVE); - ioport_set_pin_dir(OLED1_LED3_PIN, IOPORT_DIR_OUTPUT); - -#if defined (CONF_BOARD_UART_CONSOLE) - /* Configure UART pins */ - ioport_set_port_peripheral_mode(PINS_USART7_PORT, PINS_USART7, - PINS_USART7_FLAGS); -#endif - -#ifdef CONF_BOARD_USART_RXD - /* Configure USART RXD pin */ - ioport_set_pin_peripheral_mode(EXT3_PIN_UART_RX, - IOPORT_MODE_MUX_B); -#endif - -#ifdef CONF_BOARD_USART_TXD - /* Configure USART TXD pin */ - ioport_set_pin_peripheral_mode(EXT3_PIN_UART_TX, - IOPORT_MODE_MUX_B); -#endif - -#ifdef CONF_BOARD_USART_SCK - /* Configure USART synchronous communication SCK pin */ - ioport_set_pin_peripheral_mode(EXT3_PIN_8, - IOPORT_MODE_MUX_B); -#endif - -#if defined(CONF_BOARD_SPI) || defined(CONF_BOARD_SD_MMC_SPI) - ioport_set_pin_peripheral_mode(SPI_MISO_GPIO, SPI_MISO_FLAGS); - ioport_set_pin_peripheral_mode(SPI_MOSI_GPIO, SPI_MOSI_FLAGS); - ioport_set_pin_peripheral_mode(SPI_SPCK_GPIO, SPI_SPCK_FLAGS); - -#ifdef CONF_BOARD_SD_MMC_SPI - /* Setting SD detection pin */ - ioport_set_pin_dir(SD_MMC_0_CD_GPIO, IOPORT_DIR_INPUT); - ioport_set_pin_mode(SD_MMC_0_CD_GPIO, IOPORT_MODE_PULLUP); -#endif - -#ifdef CONF_BOARD_SPI_NPCS0 - ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS); -#endif - -#ifdef CONF_BOARD_SPI_NPCS1 - ioport_set_pin_peripheral_mode(SPI_NPCS1_GPIO, SPI_NPCS1_FLAGS); -#endif -#endif - -#ifdef CONF_BOARD_OLED_UG_2832HSWEG04 - ioport_set_pin_dir(UG_2832HSWEG04_DATA_CMD_GPIO, IOPORT_DIR_OUTPUT); - ioport_set_pin_mode(UG_2832HSWEG04_DATA_CMD_GPIO, IOPORT_MODE_PULLUP); - ioport_set_pin_dir(UG_2832HSWEG04_RESET_GPIO, IOPORT_DIR_OUTPUT); - ioport_set_pin_mode(UG_2832HSWEG04_RESET_GPIO, IOPORT_MODE_PULLUP); -#endif - -#ifdef CONF_BOARD_TWI0 - ioport_set_pin_peripheral_mode(TWI0_DATA_GPIO, TWI0_DATA_FLAGS); - ioport_set_pin_peripheral_mode(TWI0_CLK_GPIO, TWI0_CLK_FLAGS); -#endif - -#ifdef CONF_BOARD_TWI1 - ioport_set_pin_peripheral_mode(TWI1_DATA_GPIO, TWI1_DATA_FLAGS); - ioport_set_pin_peripheral_mode(TWI1_CLK_GPIO, TWI1_CLK_FLAGS); -#endif - -#ifdef CONF_BOARD_TWI2 - ioport_set_pin_peripheral_mode(TWI2_DATA_GPIO, TWI2_DATA_FLAGS); - ioport_set_pin_peripheral_mode(TWI2_CLK_GPIO, TWI2_CLK_FLAGS); -#endif - -#if defined(CONF_BOARD_TWI4) ||defined(CONF_BOARD_AT30TSE) - ioport_set_pin_peripheral_mode(TWI4_DATA_GPIO, TWI4_DATA_FLAGS); - ioport_set_pin_peripheral_mode(TWI4_CLK_GPIO, TWI4_CLK_FLAGS); -#endif - -#ifdef CONF_BOARD_I2S0 - ioport_set_pin_peripheral_mode(I2S0_SCK_GPIO, I2S0_SCK_FLAGS); - ioport_set_pin_peripheral_mode(I2S0_MCK_GPIO, I2S0_MCK_FLAGS); - ioport_set_pin_peripheral_mode(I2S0_SDI_GPIO, I2S0_SDI_FLAGS); - ioport_set_pin_peripheral_mode(I2S0_SDO_GPIO, I2S0_SDO_FLAGS); - ioport_set_pin_peripheral_mode(I2S0_WS_GPIO, I2S0_WS_FLAGS); -#endif - -#ifdef CONF_BOARD_I2S1 - ioport_set_pin_peripheral_mode(I2S1_SCK_GPIO, I2S1_SCK_FLAGS); - ioport_set_pin_peripheral_mode(I2S1_MCK_GPIO, I2S1_MCK_FLAGS); - ioport_set_pin_peripheral_mode(I2S1_SDI_GPIO, I2S1_SDI_FLAGS); - ioport_set_pin_peripheral_mode(I2S1_SDO_GPIO, I2S1_SDO_FLAGS); - ioport_set_pin_peripheral_mode(I2S1_WS_GPIO, I2S1_WS_FLAGS); -#endif - -#ifdef CONF_BOARD_PDM - ioport_set_pin_peripheral_mode(PDM_CLK_GPIO, PDM_CLK_FLAGS); - ioport_set_pin_peripheral_mode(PDM_DAT_GPIO, PDM_DAT_FLAGS); -#endif - -#ifdef CONF_BOARD_USART0 - ioport_set_pin_peripheral_mode(USART0_RXD_GPIO, USART0_RXD_FLAGS); - ioport_set_pin_peripheral_mode(USART0_TXD_GPIO, USART0_TXD_FLAGS); - ioport_set_pin_peripheral_mode(USART0_SCK_GPIO, USART0_SCK_FLAGS); - ioport_set_pin_peripheral_mode(USART0_CTS_GPIO, USART0_CTS_FLAGS); - ioport_set_pin_peripheral_mode(USART0_RTS_GPIO, USART0_RTS_FLAGS); -#endif - -#ifdef CONF_BOARD_USART6 - ioport_set_pin_peripheral_mode(USART6_RXD_GPIO, USART6_RXD_FLAGS); - ioport_set_pin_peripheral_mode(USART6_TXD_GPIO, USART6_TXD_FLAGS); - ioport_set_pin_peripheral_mode(USART6_SCK_GPIO, USART6_SCK_FLAGS); - ioport_set_pin_peripheral_mode(USART6_CTS_GPIO, USART6_CTS_FLAGS); - ioport_set_pin_peripheral_mode(USART6_RTS_GPIO, USART6_RTS_FLAGS); -#endif - -#if defined(CONF_BOARD_USB_PORT) -# if defined(CONF_BOARD_USB_VBUS_DETECT) - gpio_configure_pin(USB_VBUS_PIN, USB_VBUS_FLAGS); -# endif -#endif -} - -/** @} */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/mbed_overrides.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/mbed_overrides.c deleted file mode 100644 index 6e3e4f3094c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/mbed_overrides.c +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "compiler.h" -#include "sysclk.h" - -uint8_t g_sys_init = 0; - -//called before main - implement here if board needs it ortherwise, let -// the application override this if necessary -//TODO: To be implemented by adding system init and board init -void mbed_sdk_init() -{ - if(g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } -} -/***************************************************************/ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/samg55_xplained_pro.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/samg55_xplained_pro.h deleted file mode 100644 index 52c2057d353..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/samg55_xplained_pro.h +++ /dev/null @@ -1,731 +0,0 @@ -/** - * \file - * - * \brief SAMG55 Xplained Pro board definition - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SAMG55_XPLAINED_PRO_H_INCLUDED -#define SAMG55_XPLAINED_PRO_H_INCLUDED - -#include -#include - -/** - * \ingroup group_common_boards - * \defgroup samg55_xplained_pro_group SAMG55 Xplained Pro board - * - * @{ - */ - -void system_board_init(void); - -/** - * \defgroup samg55_config_group Configuration - * - * Symbols to use for configuring the board and its initialization. - * - * @{ - */ -#ifdef __DOXYGEN__ - -/* ! \name Initialization */ -/* @{ */ - -/** - * \def CONF_BOARD_KEEP_WATCHDOG_AT_INIT - * \brief If defined, the watchdog will remain enabled - * - * If this symbol is defined, the watchdog is left running with its current - * configuration. Otherwise, it is disabled during board initialization. - */ -# ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT -# define CONF_BOARD_KEEP_WATCHDOG_AT_INIT -# endif - -/* @} */ - -#endif /* __DOXYGEN__ */ -/**@} */ - -/** - * \defgroup samg55_xplained_pro_features_group Features - * - * Symbols that describe features and capabilities of the board. - * - * @{ - */ - -/** Name string macro */ -#define BOARD_NAME "SAMG55_XPLAINED_PRO" - -/** \name Resonator definitions - * @{ */ -#define BOARD_FREQ_SLCK_XTAL (32768U) -#define BOARD_FREQ_SLCK_BYPASS (32768U) -#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */ -#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */ -#define BOARD_MCK CHIP_FREQ_CPU_MAX -/*TBD startup time needs to be adjusted according to measurements */ -#define BOARD_OSC_STARTUP_US 15625 - -/** @} */ - -/** \name LED0 definitions - * @{ */ -#define LED0_GPIO (PIO_PA6_IDX) -#define LED0_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT) - -#define LED0_PIN IOPORT_CREATE_PIN(PIOA, 6) -#define LED0_ACTIVE_LEVEL false -#define LED0_INACTIVE_LEVEL !LED0_ACTIVE_LEVEL -/** @} */ - -/** \name SW0 definitions - * @{ */ -#define SW0_PIN IOPORT_CREATE_PIN(PIOA, 2) -#define SW0_ACTIVE false -#define SW0_INACTIVE !SW0_ACTIVE -#define SW0_SUPC_INPUT 2 -/** @} */ - -/** - * Wrapper macros for SW0, to ensure common naming across all Xplained Pro - * boards. - */ -#define PIN_SW0 {PIO_PA2, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define PIN_SW0_MASK PIO_PA2 -#define PIN_SW0_PIO PIOA -#define PIN_SW0_ID ID_PIOA -#define PIN_SW0_TYPE PIO_INPUT -#define PIN_SW0_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) -//@} - -/** - * \name LED #0 definitions - * - * Wrapper macros for LED0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define LED_0_NAME "LED0 (yellow)" -#define LED_0_PIN LED0_PIN -#define LED_0_ACTIVE LED0_ACTIVE_LEVEL -#define LED_0_INACTIVE LED0_INACTIVE_LEVEL - -#define PIN_LED_0 {PIO_PA16, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -#define PIN_LED_0_MASK PIO_PA16 -#define PIN_LED_0_PIO PIOA -#define PIN_LED_0_ID ID_PIOA -#define PIN_LED_0_TYPE PIO_OUTPUT_1 -#define PIN_LED_0_ATTR PIO_DEFAULT -/** @} */ - -/** Number of on-board LEDs */ -#define LED_COUNT 1 - -/** - * \name Button #0 definitions - * - * Wrapper macros for SW0, to ensure common naming across all Xplained Pro - * boards. - * - * @{ */ -#define BUTTON_0_NAME "SW0" -#define BUTTON_0_PIN SW0_PIN -#define BUTTON_0_ACTIVE SW0_ACTIVE -#define BUTTON_0_INACTIVE SW0_INACTIVE -#define BUTTON_0_SUPC_INPUT SW0_SUPC_INPUT - -#define PUSHBUTTON_1_NAME "SW0" -#define PIN_PUSHBUTTON_1 {PIO_PA2, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define PIN_PUSHBUTTON_1_MASK PIO_PA2 -#define PIN_PUSHBUTTON_1_PIO PIOA -#define PIN_PUSHBUTTON_1_ID ID_PIOA -#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT -#define PIN_PUSHBUTTON_1_ATTR PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE -/** @} */ - -/** Number of on-board buttons */ -#define BUTTON_COUNT 1 - -#define CONSOLE_UART USART7 -#define CONSOLE_UART_ID ID_FLEXCOM7 -/** USART7 pins (TXD7 and RXD7) definitions, PA27,28. */ -#define PINS_USART7 (PIO_PA27B_RXD7| PIO_PA28B_TXD7) -#define PINS_USART7_FLAGS (IOPORT_MODE_MUX_B) - -#define PINS_USART7_PORT IOPORT_PIOA -#define PINS_USART7_MASK (PIO_PA27B_RXD7 | PIO_PA28B_TXD7) -#define PINS_USART7_PIO PIOA -#define PINS_USART7_ID ID_PIOA -#define PINS_USART7_TYPE PIO_PERIPH_B -#define PINS_USART7_ATTR PIO_DEFAULT - -/** PCK1 pin definition (PA17) */ -#define PIN_PCK1 (PIO_PA17_IDX) -#define PIN_PCK1_MUX (IOPORT_MODE_MUX_B) -#define PIN_PCK1_FLAGS (IOPORT_MODE_MUX_B) -#define PIN_PCK1_PORT IOPORT_PIOA -#define PIN_PCK1_MASK PIO_PA17B_PCK1 -#define PIN_PCK1_PIO PIOA -#define PIN_PCK1_ID ID_PIOA -#define PIN_PCK1_TYPE PIO_PERIPH_B -#define PIN_PCK1_ATTR PIO_DEFAULT - -#define PIN_TC0_TIOA0 (PIO_PA0_IDX) -#define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B) -#define PIN_TC0_TIOA0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) - -#define PIN_TC0_TIOA1 (PIO_PA23_IDX) -#define PIN_TC0_TIOA1_MUX (IOPORT_MODE_MUX_B) -#define PIN_TC0_TIOA1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -//! \name SPI -//@{ -/** SPI MISO pin definition. */ -#define SPI_MISO_GPIO (PIO_PA12_IDX) -#define SPI_MISO_FLAGS (IOPORT_MODE_MUX_A) -/** SPI MOSI pin definition. */ -#define SPI_MOSI_GPIO (PIO_PA13_IDX) -#define SPI_MOSI_FLAGS (IOPORT_MODE_MUX_A) -/** SPI SPCK pin definition. */ -#define SPI_SPCK_GPIO (PIO_PA14_IDX) -#define SPI_SPCK_FLAGS (IOPORT_MODE_MUX_A) - -/** SPI chip select 0 pin definition. */ -#define SPI_NPCS0_GPIO (PIO_PA11_IDX) -#define SPI_NPCS0_FLAGS (IOPORT_MODE_MUX_A) -/** SPI chip select 1 pin definition. */ -#define SPI_NPCS1_GPIO (PIO_PA5_IDX) -#define SPI_NPCS1_FLAGS (IOPORT_MODE_MUX_B) -//@} - -/** \name Extension header #1 pin definitions - * @{ - */ -#define EXT1_PIN_3 IOPORT_CREATE_PIN(PIOA, 17) -#define EXT1_PIN_4 IOPORT_CREATE_PIN(PIOA, 18) -#define EXT1_PIN_5 IOPORT_CREATE_PIN(PIOA, 26) -#define EXT1_PIN_6 IOPORT_CREATE_PIN(PIOA, 25) -#define EXT1_PIN_7 IOPORT_CREATE_PIN(PIOA, 0) -#define EXT1_PIN_8 IOPORT_CREATE_PIN(PIOA, 23) -#define EXT1_PIN_9 IOPORT_CREATE_PIN(PIOA, 24) -#define EXT1_PIN_10 IOPORT_CREATE_PIN(PIOA, 29) -#define EXT1_PIN_11 IOPORT_CREATE_PIN(PIOB, 10) -#define EXT1_PIN_12 IOPORT_CREATE_PIN(PIOB, 11) -#define EXT1_PIN_13 IOPORT_CREATE_PIN(PIOA, 9) -#define EXT1_PIN_14 IOPORT_CREATE_PIN(PIOA, 10) -#define EXT1_PIN_15 IOPORT_CREATE_PIN(PIOA, 11) -#define EXT1_PIN_16 IOPORT_CREATE_PIN(PIOA, 13) -#define EXT1_PIN_17 IOPORT_CREATE_PIN(PIOA, 12) -#define EXT1_PIN_18 IOPORT_CREATE_PIN(PIOA, 14) -/** @} */ - -/** \name Extension header #1 pin definitions by function - * @{ - */ -#define EXT1_PIN_ADC_0 EXT1_PIN_3 -#define EXT1_PIN_ADC_1 EXT1_PIN_4 -#define EXT1_PIN_GPIO_0 EXT1_PIN_5 -#define EXT1_PIN_GPIO_1 EXT1_PIN_6 -#define EXT1_PIN_PWM_0 EXT1_PIN_7 -#define EXT1_PIN_PWM_1 EXT1_PIN_8 -#define EXT1_PIN_IRQ EXT1_PIN_9 -#define EXT1_PIN_I2C_SDA EXT1_PIN_11 -#define EXT1_PIN_I2C_SCL EXT1_PIN_12 -#define EXT1_PIN_UART_RX EXT1_PIN_13 -#define EXT1_PIN_UART_TX EXT1_PIN_14 -#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10 -#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 -#define EXT1_PIN_SPI_MOSI EXT1_PIN_16 -#define EXT1_PIN_SPI_MISO EXT1_PIN_17 -#define EXT1_PIN_SPI_SCK EXT1_PIN_18 -/** @} */ - -/** \name Extension header #1 ADC definitions - * @{ - */ -#define EXT1_ADC_MODULE ADC -#define EXT1_ADC_0_CHANNEL 0 -#define EXT1_ADC_1_CHANNEL 1 -/** @} */ - -/** \name Extension header #1 PWM definitions - * @{ - */ -#define EXT1_PWM_MODULE TC0 -#define EXT1_PWM_0_CHANNEL 0 -#define EXT1_PWM_0_MUX IOPORT_MODE_MUX_B -#define EXT1_PWM_1_CHANNEL 1 -#define EXT1_PWM_1_MUX IOPORT_MODE_MUX_B -/** @} */ - -/** \name Extension header #1 IRQ/External interrupt definitions - * @{ - */ -#define EXT1_IRQ_MODULE SUPC -#define EXT1_IRQ_INPUT 11 -/** @} */ - -/** \name Extension header #1 I2C definitions - * @{ - */ -#define EXT1_TWI_MODULE TWI4 -#define EXT1_TWI_TWD_MUX IOPORT_MODE_MUX_B -#define EXT1_TWI_TWCK_MUX IOPORT_MODE_MUX_B -/** @} */ - -/** \name Extension header #1 UART definitions - * @{ - */ -#define EXT1_UART_MODULE USART0 -#define EXT1_UART_RXD_MUX IOPORT_MODE_MUX_A -#define EXT1_UART_TXD_MUX IOPORT_MODE_MUX_A -/** @} */ - -/** \name Extension header #1 SPI definitions - * @{ - */ -#define EXT1_SPI_MODULE SPI5 -#define EXT1_SPI_MISO_MUX IOPORT_MODE_MUX_A -#define EXT1_SPI_MOSI_MUX IOPORT_MODE_MUX_A -#define EXT1_SPI_SPCK_MUX IOPORT_MODE_MUX_A -#define EXT1_SPI_NPCS0_MUX IOPORT_MODE_MUX_A -/** @} */ - -/** \name Extension header #3 pin definitions - * @{ - */ -#define EXT3_PIN_3 IOPORT_CREATE_PIN(PIOA, 19) -#define EXT3_PIN_4 IOPORT_CREATE_PIN(PIOA, 20) -#define EXT3_PIN_5 IOPORT_CREATE_PIN(PIOA, 30) -#define EXT3_PIN_6 IOPORT_CREATE_PIN(PIOB, 15) -#define EXT3_PIN_7 IOPORT_CREATE_PIN(PIOA, 1) -#define EXT3_PIN_8 IOPORT_CREATE_PIN(PIOB, 13) -#define EXT3_PIN_9 IOPORT_CREATE_PIN(PIOB, 3) -#define EXT3_PIN_10 IOPORT_CREATE_PIN(PIOA, 15) -#define EXT3_PIN_11 IOPORT_CREATE_PIN(PIOB, 8) -#define EXT3_PIN_12 IOPORT_CREATE_PIN(PIOB, 9) -#define EXT3_PIN_13 IOPORT_CREATE_PIN(PIOB, 1) -#define EXT3_PIN_14 IOPORT_CREATE_PIN(PIOB, 0) -#define EXT3_PIN_15 IOPORT_CREATE_PIN(PIOA, 5) -#define EXT3_PIN_16 IOPORT_CREATE_PIN(PIOA, 13) -#define EXT3_PIN_17 IOPORT_CREATE_PIN(PIOA, 12) -#define EXT3_PIN_18 IOPORT_CREATE_PIN(PIOA, 14) -/** @} */ - -/** \name Extension header #3 pin definitions by function - * @{ - */ -#define EXT3_PIN_ADC_0 EXT3_PIN_3 -#define EXT3_PIN_ADC_1 EXT3_PIN_4 -#define EXT3_PIN_GPIO_0 EXT3_PIN_5 -#define EXT3_PIN_PWM_0 EXT3_PIN_7 -#define EXT3_PIN_IRQ EXT3_PIN_9 -#define EXT3_PIN_I2C_SDA EXT3_PIN_11 -#define EXT3_PIN_I2C_SCL EXT3_PIN_12 -#define EXT3_PIN_UART_RX EXT3_PIN_13 -#define EXT3_PIN_UART_TX EXT3_PIN_14 -#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10 -#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15 -#define EXT3_PIN_SPI_MOSI EXT3_PIN_16 -#define EXT3_PIN_SPI_MISO EXT3_PIN_17 -#define EXT3_PIN_SPI_SCK EXT3_PIN_18 -/** @} */ - -/** \name Extension header #3 ADC definitions - * @{ - */ -#define EXT3_ADC_MODULE ADC -#define EXT3_ADC_0_CHANNEL 2 -#define EXT3_ADC_1_CHANNEL 3 -/** @} */ - -/** \name Extension header #3 PWM definitions - * @{ - */ -#define EXT3_PWM_MODULE TC2 -#define EXT3_PWM_0_CHANNEL 0 -#define EXT3_PWM_0_MUX IOPORT_MODE_MUX_A -/** @} */ - -/** \name Extension header #3 IRQ/External interrupt definitions - * @{ - */ -#define EXT3_IRQ_MODULE SUPC -#define EXT3_IRQ_INPUT 10 -/** @} */ - -/** \name Extension header #3 I2C definitions - * @{ - */ -#define EXT3_TWI_MODULE TWI1 -#define EXT3_TWI_TWD_MUX IOPORT_MODE_MUX_A -#define EXT3_TWI_TWCK_MUX IOPORT_MODE_MUX_A -/** @} */ - -/** \name Extension header #3 UART definitions - * @{ - */ -#define EXT3_UART_MODULE UART0 -#define EXT3_UART_RXD_MUX IOPORT_MODE_MUX_A -#define EXT3_UART_TXD_MUX IOPORT_MODE_MUX_A -/** @} */ - -/** \name Extension header #3 SPI definitions - * @{ - */ -#define EXT3_SPI_MODULE SPI5 -#define EXT3_SPI_MISO_MUX IOPORT_MODE_MUX_A -#define EXT3_SPI_MOSI_MUX IOPORT_MODE_MUX_A -#define EXT3_SPI_SPCK_MUX IOPORT_MODE_MUX_A -#define EXT3_SPI_NPCS1_MUX IOPORT_MODE_MUX_B -/** @} */ - -/** \name Extension header #4 pin definitions - * @{ - */ -#define EXT4_PIN_5 IOPORT_CREATE_PIN(PIOA, 31) -#define EXT4_PIN_9 IOPORT_CREATE_PIN(PIOB, 14) -#define EXT4_PIN_11 IOPORT_CREATE_PIN(PIOB, 10) -#define EXT4_PIN_12 IOPORT_CREATE_PIN(PIOB, 11) -/** @} */ - -/** \name Extension header #4 pin definitions by function - * @{ - */ -#define EXT4_PIN_GPIO_0 EXT3_PIN_5 -#define EXT4_PIN_IRQ EXT3_PIN_9 -#define EXT4_PIN_I2C_SDA EXT3_PIN_11 -#define EXT4_PIN_I2C_SCL EXT3_PIN_12 -/** @} */ - -/** \name Extension header #4 IRQ/External interrupt definitions - * @{ - */ -#define EXT4_IRQ_MODULE SUPC -#define EXT4_IRQ_INPUT 14 -/** @} */ - -/** \name Extension header #4 TWI definitions - * @{ - */ -#define EXT4_TWI_MODULE TWI1 -#define EXT4_TWI_TWD_MUX IOPORT_MODE_MUX_A -#define EXT4_TWI_TWCK_MUX IOPORT_MODE_MUX_A -/** @} */ - -/** \name Embedded debugger GPIO interface definitions - * @{ - */ -#define EDBG_GPIO0_PIN IOPORT_CREATE_PIN(PIOA, 15) -#define EDBG_GPIO1_PIN IOPORT_CREATE_PIN(PIOB, 3) -#define EDBG_GPIO2_PIN IOPORT_CREATE_PIN(PIOB, 4) -#define EDBG_GPIO3_PIN IOPROT_CREATE_PIN(PIOB, 9) -/** @} */ - -/** \name Embedded debugger USART interface definitions - * @{ - */ -#define EDBG_UART_MODULE USART -#define EDBG_UART_RX_PIN IOPORT_CREATE_PIN(PIOA, 5) -#define EDBG_UART_RX_MUX IOPORT_MODE_MUX_A -#define EDBG_UART_TX_PIN IOPORT_CREATE_PIN(PIOA, 6) -#define EDBG_UART_TX_MUX IOPORT_MODE_MUX_A -/** @} */ - -/** \name Embedded debugger I2C interface definitions - * @{ - */ -#define EDBG_TWI_MODULE TWI1 -#define EDBG_TWI_TWD_MUX IOPORT_MODE_MUX_A -#define EDBG_TWI_TWCK_MUX IOPORT_MODE_MUX_A -/** @} */ - -/** \name Embedded debugger CDC Gateway USART interface definitions - * @{ - */ -#define EDBG_CDC_UART_MODULE UART0 -#define EDBG_CDC_UART_RX_PIN IOPORT_CREATE_PIN(PIOA, 9) -#define EDBG_CDC_UART_RX_MUX IOPORT_MODE_MUX_A -#define EDBG_CDC_UART_TX_PIN IOPORT_CREATE_PIN(PIOA, 10) -#define EDBG_CDC_UART_TX_MUX IOPORT_MODE_MUX_A -/** @} */ - -//! \name OLED -//@{ -/** OLED command/data select pin */ -#define UG_2832HSWEG04_DATA_CMD_GPIO (PIO_PA30_IDX) -/** OLED reset pin */ -#define UG_2832HSWEG04_RESET_GPIO (PIO_PA15_IDX) -/** OLED SPI configuration */ -#define UG_2832HSWEG04_SS 1 -#define UG_2832HSWEG04_BAUDRATE 5000000 -//! \name OLED dimensions -//@{ -#define LCD_WIDTH_PIXELS (128) -#define LCD_HEIGHT_PIXELS (32) -//@} -//@} - -/** \name TWI -* @{ -*/ -/** TWI0 pin definitions */ -#define TWI0_DATA_GPIO PIO_PA9_IDX -#define TWI0_DATA_FLAGS IOPORT_MODE_MUX_A -#define TWI0_CLK_GPIO PIO_PA10_IDX -#define TWI0_CLK_FLAGS IOPORT_MODE_MUX_A -/** TWI1 pin definitions */ -#define TWI1_DATA_GPIO PIO_PB2_IDX -#define TWI1_DATA_FLAGS IOPORT_MODE_MUX_A -#define TWI1_CLK_GPIO PIO_PB3_IDX -#define TWI1_CLK_FLAGS IOPORT_MODE_MUX_A -/** TWI4 pin definitions */ -#define TWI4_DATA_GPIO EXT1_PIN_11 -#define TWI4_DATA_FLAGS IOPORT_MODE_MUX_A -#define TWI4_CLK_GPIO EXT1_PIN_12 -#define TWI4_CLK_FLAGS IOPORT_MODE_MUX_A -/** TWI6 pin definitions */ -#define TWI6_DATA_GPIO EXT3_PIN_11 -#define TWI6_DATA_FLAGS IOPORT_MODE_MUX_B -#define TWI6_CLK_GPIO EXT3_PIN_12 -#define TWI6_CLK_FLAGS IOPORT_MODE_MUX_B -/** @} */ - -/** \name USART -* @{ -*/ -/** USART0 pin definitions */ -#define USART0_RXD_GPIO EXT1_PIN_13 -#define USART0_RXD_FLAGS IOPORT_MODE_MUX_A -#define USART0_TXD_GPIO EXT1_PIN_14 -#define USART0_TXD_FLAGS IOPORT_MODE_MUX_A -#define USART0_SCK_GPIO EXT3_PIN_14 -#define USART0_SCK_FLAGS IOPORT_MODE_MUX_A -#define USART0_CTS_GPIO EXT1_PIN_6 -#define USART0_CTS_FLAGS IOPORT_MODE_MUX_A -#define USART0_RTS_GPIO EXT1_PIN_5 -#define USART0_RTS_FLAGS IOPORT_MODE_MUX_A - -/** USART6 pin definitions */ -#define USART6_RXD_GPIO EXT4_PIN_12 -#define USART6_RXD_FLAGS IOPORT_MODE_MUX_B -#define USART6_TXD_GPIO EXT4_PIN_11 -#define USART6_TXD_FLAGS IOPORT_MODE_MUX_B -#define USART6_SCK_GPIO EXT3_PIN_8 -#define USART6_SCK_FLAGS IOPORT_MODE_MUX_B -#define USART6_CTS_GPIO EXT4_PIN_9 -#define USART6_CTS_FLAGS IOPORT_MODE_MUX_B -#define USART6_RTS_GPIO EXT3_PIN_6 -#define USART6_RTS_FLAGS IOPORT_MODE_MUX_B -/** @} */ - -//! \name I2S0 -//@{ -/** I2S0 SCK pin definition. */ -#define I2S0_SCK_GPIO (PIO_PA0_IDX) -#define I2S0_SCK_FLAGS (IOPORT_MODE_MUX_A) -/** I2S0 MCK pin definition. */ -#define I2S0_MCK_GPIO (PIO_PA4_IDX) -#define I2S0_MCK_FLAGS (IOPORT_MODE_MUX_B) -/** I2S0 SDI pin definition. */ -#define I2S0_SDI_GPIO (PIO_PA2_IDX) -#define I2S0_SDI_FLAGS (IOPORT_MODE_MUX_B) -/** I2S0 SDO pin definition. */ -#define I2S0_SDO_GPIO (PIO_PA3_IDX) -#define I2S0_SDO_FLAGS (IOPORT_MODE_MUX_B) -/** I2S0 WS pin definition. */ -#define I2S0_WS_GPIO (PIO_PA1_IDX) -#define I2S0_WS_FLAGS (IOPORT_MODE_MUX_A) -//@} - -//! \name I2S1 -//@{ -/** I2S1 SCK pin definition. */ -#define I2S1_SCK_GPIO (PIO_PA19_IDX) -#define I2S1_SCK_FLAGS (IOPORT_MODE_MUX_B) -/** I2S1 MCK pin definition. */ -#define I2S1_MCK_GPIO (PIO_PA24_IDX) -#define I2S1_MCK_FLAGS (IOPORT_MODE_MUX_A) -/** I2S1 SDI pin definition. */ -#define I2S1_SDI_GPIO (PIO_PA22_IDX) -#define I2S1_SDI_FLAGS (IOPORT_MODE_MUX_B) -/** I2S1 SDO pin definition. */ -#define I2S1_SDO_GPIO (PIO_PA23_IDX) -#define I2S1_SDO_FLAGS (IOPORT_MODE_MUX_A) -/** I2S1 WS pin definition. */ -#define I2S1_WS_GPIO (PIO_PA20_IDX) -#define I2S1_WS_FLAGS (IOPORT_MODE_MUX_B) -//@} - -//! \name IO1 button definitions */ -//@{ -/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define PUSHBUTTON_1_NAME "SW0" -#define GPIO_PUSH_BUTTON_1 (PIO_PA2_IDX) -#define GPIO_PUSH_BUTTON_1_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) -//@} - -//! \name Light Sensor -//@{ -#define LIGHT_SENSOR_GPIO PIO_PA17_IDX -#define LIGHT_SENSOR_FLAGS PIO_INPUT -//@} - -/** \name USB definitions - * @{ - */ -#define PIN_USB_VBUS {PIO_PB4, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP} -#define USB_VBUS_FLAGS (PIO_INPUT | PIO_DEBOUNCE | PIO_IT_EDGE) -#define USB_VBUS_PIN_IRQn (PIOB_IRQn) -#define USB_VBUS_PIN (PIO_PB4_IDX) -#define USB_VBUS_PIO_ID (ID_PIOB) -#define USB_VBUS_PIO_MASK (PIO_PB4) - -/** USB D- pin (System function) */ -#define PIN_USB_DM {PIO_PA21} -/** USB D+ pin (System function) */ -#define PIN_USB_DP {PIO_PA22} -/** @} */ - -//! \name IO1 SD card definitions */ -//@{ -#define SD_MMC_SPI_MEM_CNT 1 -#define SD_MMC_0_CD_GPIO (PIO_PA29_IDX) -#define SD_MMC_0_CD_DIR (IOPORT_DIR_INPUT) -#define SD_MMC_0_CD_MODE (IOPORT_MODE_PULLUP) -#define SD_MMC_0_CD_DETECT_VALUE 0 -#define SD_MMC_SPI SPI5 -#define SD_MMC_SPI_0_CS 0 -#define SD_MMC_0_CD_PIO_ID ID_PIOA -/** - * Wrapper macros for IO1 SD, to ensure common naming across all Xplained Pro - * boards. - */ -#define SD_MMC_0_CD_FLAGS (PIO_INPUT | PIO_PULLUP) -#define SD_MMC_0_CD {PIO_PA29, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define SD_MMC_0_CD_MASK PIO_PA29 -#define SD_MMC_0_CD_PIO PIOA -#define SD_MMC_0_CD_ID ID_PIOA -#define SD_MMC_0_CD_TYPE PIO_INPUT -#define SD_MMC_0_CD_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_EDGE) -//@} - -//! \name IO1 temperature sensor definitions */ -//@{ -#define BOARD_AT30TSE_TWI TWI4 -#define BOARD_AT30TSE_TWI_ID ID_TWI4 -#define BOARD_TWI_SPEED (400000u) -#define BOARD_USING_AT30TSE AT30TSE758 -#define BOARD_AT30TSE_DEVICE_ADDR 0x07 -//@} - -//! \name OLED1 led definitions */ -//@{ -#define OLED1_LED1_PIN EXT3_PIN_7 -#define OLED1_LED1_ACTIVE false -#define OLED1_LED1_INACTIVE !OLED1_LED1_ACTIVE - -#define OLED1_LED2_PIN EXT3_PIN_8 -#define OLED1_LED2_ACTIVE false -#define OLED1_LED2_INACTIVE !OLED1_LED2_ACTIVE - -#define OLED1_LED3_PIN EXT3_PIN_6 -#define OLED1_LED3_ACTIVE false -#define OLED1_LED3_INACTIVE !OLED1_LED3_ACTIVE -//@} - -//! \name OLED1 button definitions */ -//@{ -/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define OLED1_PUSHBUTTON_1_NAME "BUTTON 1" -#define OLED1_GPIO_PUSH_BUTTON_1 (PIO_PB3_IDX) -#define OLED1_GPIO_PUSH_BUTTON_1_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) - -#define OLED1_PIN_PUSHBUTTON_1 {PIO_PB3, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define OLED1_PIN_PUSHBUTTON_1_MASK PIO_PB3 -#define OLED1_PIN_PUSHBUTTON_1_PIO PIOB -#define OLED1_PIN_PUSHBUTTON_1_ID ID_PIOB -#define OLED1_PIN_PUSHBUTTON_1_TYPE PIO_INPUT -#define OLED1_PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) - -/** Push button #2 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define OLED1_PUSHBUTTON_2_NAME "BUTTON 2" -#define OLED1_GPIO_PUSH_BUTTON_2 (PIO_PA19_IDX) -#define OLED1_GPIO_PUSH_BUTTON_2_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) - -#define OLED1_PIN_PUSHBUTTON_2 {PIO_PA19, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define OLED1_PIN_PUSHBUTTON_2_MASK PIO_PA19 -#define OLED1_PIN_PUSHBUTTON_2_PIO PIOA -#define OLED1_PIN_PUSHBUTTON_2_ID ID_PIOA -#define OLED1_PIN_PUSHBUTTON_2_TYPE PIO_INPUT -#define OLED1_PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) - -/** Push button #3 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define OLED1_PUSHBUTTON_3_NAME "BUTTON 3" -#define OLED1_GPIO_PUSH_BUTTON_3 (PIO_PA20_IDX) -#define OLED1_GPIO_PUSH_BUTTON_3_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) - -#define OLED1_PIN_PUSHBUTTON_3 {PIO_PA20, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define OLED1_PIN_PUSHBUTTON_3_MASK PIO_PA20 -#define OLED1_PIN_PUSHBUTTON_3_PIO PIOA -#define OLED1_PIN_PUSHBUTTON_3_ID ID_PIOA -#define OLED1_PIN_PUSHBUTTON_3_TYPE PIO_INPUT -#define OLED1_PIN_PUSHBUTTON_3_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) -//@} - -//! \name PDM -//@{ -/** PDM CLK pin definition. */ -#define PDM_CLK_GPIO (PIO_PA10_IDX) -#define PDM_CLK_FLAGS (IOPORT_MODE_MUX_B) -/** PDM DAT pin definition. */ -#define PDM_DAT_GPIO (PIO_PA9_IDX) -#define PDM_DAT_FLAGS (IOPORT_MODE_MUX_B) -//@} - -/** @} */ - -/** @} */ - -#endif /* SAMG55_XPLAINED_PRO_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device.h deleted file mode 100644 index 3b470c68647..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device/TOOLCHAIN_GCC_ARM/samg55j19.ld b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device/TOOLCHAIN_GCC_ARM/samg55j19.ld deleted file mode 100644 index 2ffdfb67c29..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device/TOOLCHAIN_GCC_ARM/samg55j19.ld +++ /dev/null @@ -1,127 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Memory Spaces Definitions */ -MEMORY { - rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 - ram (rwx) : ORIGIN = 0x20000000 + 0x108, LENGTH = 0x00028000 - 0x108 - } - - /* Section Definitions */ - SECTIONS { -.text : - { - . = ALIGN(8); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(8); - KEEP(*(.init)) - . = ALIGN(8); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(8); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(8); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(8); - KEEP(*(.fini)) - - . = ALIGN(8); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(8); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); -.ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(8); - _etext = .; - -.relocate : - AT (_etext) - { - . = ALIGN(8); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(8); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(8); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(8); - _ebss = . ; - _ezero = .; - } > ram - - .heap (NOLOAD) : - { - . = ALIGN(8); - __end__ = . ; - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - - . = ALIGN(8); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device/TOOLCHAIN_GCC_ARM/startup_samg55.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device/TOOLCHAIN_GCC_ARM/startup_samg55.c deleted file mode 100644 index 978db2c0b19..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device/TOOLCHAIN_GCC_ARM/startup_samg55.c +++ /dev/null @@ -1,257 +0,0 @@ -/** - * \file - * - * \brief Startup file for SAMG55. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "samg55.h" - -#if __FPU_USED /* CMSIS defined value to indicate usage of FPU */ -#include "fpu.h" -#endif - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M4 core handlers */ -void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef _SAMG55_FLEXCOM7_INSTANCE_ -void FLEXCOM7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif /* _SAMG55_FLEXCOM7_INSTANCE_*/ -void FLEXCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FLEXCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDMIC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FLEXCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MEM2MEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void I2SC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDMIC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FLEXCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FLEXCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FLEXCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FLEXCOM6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ARM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UHP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UDP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CRCCU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void*) (&_estack), - - .pfnReset_Handler = (void*) Reset_Handler, - .pfnNMI_Handler = (void*) NMI_Handler, - .pfnHardFault_Handler = (void*) HardFault_Handler, - .pfnMemManage_Handler = (void*) MemManage_Handler, - .pfnBusFault_Handler = (void*) BusFault_Handler, - .pfnUsageFault_Handler = (void*) UsageFault_Handler, - .pfnReserved1_Handler = (void*) (0UL), /* Reserved */ - .pfnReserved2_Handler = (void*) (0UL), /* Reserved */ - .pfnReserved3_Handler = (void*) (0UL), /* Reserved */ - .pfnReserved4_Handler = (void*) (0UL), /* Reserved */ - .pfnSVC_Handler = (void*) SVC_Handler, - .pfnDebugMon_Handler = (void*) DebugMon_Handler, - .pfnReserved5_Handler = (void*) (0UL), /* Reserved */ - .pfnPendSV_Handler = (void*) PendSV_Handler, - .pfnSysTick_Handler = (void*) SysTick_Handler, - - /* Configurable interrupts */ - .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ - .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ - .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */ - .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */ - .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ - .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ - .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Flash Controller */ -#ifdef _SAMG55_FLEXCOM7_INSTANCE_ - .pfnFLEXCOM7_Handler = (void*) FLEXCOM7_Handler, /* 7 FLEXCOM 7 */ -#else - .pvReserved7 = (void*) (0UL), /* 7 Reserved */ -#endif /* _SAMG55_FLEXCOM7_INSTANCE_ */ - .pfnFLEXCOM0_Handler = (void*) FLEXCOM0_Handler, /* 8 FLEXCOM 0 */ - .pfnFLEXCOM1_Handler = (void*) FLEXCOM1_Handler, /* 9 FLEXCOM 1 */ - .pvReserved10 = (void*) (0UL), /* 10 Reserved */ - .pfnPIOA_Handler = (void*) PIOA_Handler, /* 11 Parallel I/O Controller A */ - .pfnPIOB_Handler = (void*) PIOB_Handler, /* 12 Parallel I/O Controller B */ - .pfnPDMIC0_Handler = (void*) PDMIC0_Handler, /* 13 PDM 0 */ - .pfnFLEXCOM2_Handler = (void*) FLEXCOM2_Handler, /* 14 FLEXCOM2 */ - .pfnMEM2MEM_Handler = (void*) MEM2MEM_Handler, /* 15 MEM2MEM */ - .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 16 I2SC0 */ - .pfnI2SC1_Handler = (void*) I2SC1_Handler, /* 17 I2SC1 */ - .pfnPDMIC1_Handler = (void*) PDMIC1_Handler, /* 18 PDM 1 */ - .pfnFLEXCOM3_Handler = (void*) FLEXCOM3_Handler, /* 19 FLEXCOM3 */ - .pfnFLEXCOM4_Handler = (void*) FLEXCOM4_Handler, /* 20 FLEXCOM4 */ - .pfnFLEXCOM5_Handler = (void*) FLEXCOM5_Handler, /* 21 FLEXCOM5 */ - .pfnFLEXCOM6_Handler = (void*) FLEXCOM6_Handler, /* 22 FLEXCOM6 */ - .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */ - .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */ - .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */ - .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */ - .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */ - .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */ - .pfnADC_Handler = (void*) ADC_Handler, /* 29 Analog To Digital Converter */ - .pfnARM_Handler = (void*) ARM_Handler, /* 30 FPU */ - .pvReserved31 = (void*) (0UL), /* 31 Reserved */ - .pvReserved32 = (void*) (0UL), /* 32 Reserved */ - .pvReserved33 = (void*) (0UL), /* 33 Reserved */ - .pvReserved34 = (void*) (0UL), /* 34 Reserved */ - .pvReserved35 = (void*) (0UL), /* 35 Reserved */ - .pvReserved36 = (void*) (0UL), /* 36 Reserved */ - .pvReserved37 = (void*) (0UL), /* 37 Reserved */ - .pvReserved38 = (void*) (0UL), /* 38 Reserved */ - .pvReserved39 = (void*) (0UL), /* 39 Reserved */ - .pvReserved40 = (void*) (0UL), /* 40 Reserved */ - .pvReserved41 = (void*) (0UL), /* 41 Reserved */ - .pvReserved42 = (void*) (0UL), /* 42 Reserved */ - .pvReserved43 = (void*) (0UL), /* 43 Reserved */ - .pvReserved44 = (void*) (0UL), /* 44 Reserved */ - .pvReserved45 = (void*) (0UL), /* 45 Reserved */ - .pvReserved46 = (void*) (0UL), /* 46 Reserved */ - .pfnUHP_Handler = (void*) UHP_Handler, /* 47 USB OHCI */ - .pfnUDP_Handler = (void*) UDP_Handler, /* 48 USB Device FS */ - .pfnCRCCU_Handler = (void*) CRCCU_Handler /* 49 CRCCU */ -}; - -/* TEMPORARY PATCH FOR SCB */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - -#if __FPU_USED - fpu_enable(); -#endif - - if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) { - SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos; - } - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/analogin_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/analogin_api.c deleted file mode 100644 index 099d6a1e151..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/analogin_api.c +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" -#include "cmsis.h" -#include "adc2.h" -#include "PeripheralPins.h" - -extern uint8_t g_sys_init; -static uint8_t adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) -{ - MBED_ASSERT(obj); - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - obj->channel = (enum adc_channel_num)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->channel != NC); - if(!adc_inited) { /*ADC hardare to be initialised only once*/ - adc_enable(); -#if SAMG55 - adc_select_clock_source_mck(ADC); -#endif - struct adc_config adc_cfg; - adc_get_config_defaults(&adc_cfg); - adc_cfg.resolution = ADC_16_BITS; - adc_init(ADC, &adc_cfg); - adc_average_on_single_trigger(ADC); - adc_set_trigger(ADC, ADC_TRIG_SW); - adc_start_calibration(ADC); - adc_inited = 1; - } - adc_channel_enable(ADC, obj->channel); -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - MBED_ASSERT(obj); - adc_channel_get_value(ADC, obj->channel); /*Dummy read of current value*/ - adc_start_software_conversion(ADC); - while (adc_get_interrupt_status(ADC) & (1 << obj->channel)); - return (uint16_t)adc_channel_get_value(ADC, obj->channel); -} - -float analogin_read(analogin_t *obj) -{ - MBED_ASSERT(obj); - uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)0xFFFF); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/board.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/board.h deleted file mode 100644 index 72e21f79ea7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/board.h +++ /dev/null @@ -1,415 +0,0 @@ -/** - * \file - * - * \brief Standard board header file. - * - * This file includes the appropriate board header file according to the - * defined board (parameter BOARD). - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/** - * \defgroup group_common_boards Generic board support - * - * The generic board support module includes board-specific definitions - * and function prototypes, such as the board initialization function. - * - * \{ - */ - -#include "compiler.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/*! \name Base Boards - */ -//! @{ -#define EVK1100 1 //!< AT32UC3A EVK1100 board. -#define EVK1101 2 //!< AT32UC3B EVK1101 board. -#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board. -#define EVK1104 4 //!< AT32UC3A3 EVK1104 board. -#define EVK1105 5 //!< AT32UC3A EVK1105 board. -#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board. -#define UC3L_EK 7 //!< AT32UC3L-EK board. -#define XPLAIN 8 //!< ATxmega128A1 Xplain board. -#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board. -#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board. -#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board. -#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board. -#define STK600_RCUC3D 16 //!< STK600 RCUC3D board. -#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board. -#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board. -#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board. -#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board. -#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board. -#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board. -#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board. -#define STK600_RC044X 24 //!< STK600 with RC044X routing card board. -#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board. -#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board. -#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board. -#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board. -#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board. -#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards. -#define RZ600 31 //!< AT32UC3A RZ600 MCU board. -#define SAM3S_EK 32 //!< SAM3S-EK board. -#define SAM3U_EK 33 //!< SAM3U-EK board. -#define SAM3X_EK 34 //!< SAM3X-EK board. -#define SAM3N_EK 35 //!< SAM3N-EK board. -#define SAM3S_EK2 36 //!< SAM3S-EK2 board. -#define SAM4S_EK 37 //!< SAM4S-EK board. -#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board. -#define STK600_MEGA 39 //!< STK600 MEGA board. -#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board. -#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board. -#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board. -#define ARDUINO_DUE_X 43 //!< Arduino Due/X board. -#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board. -#define SAM4L_EK 45 //!< SAM4L-EK board. -#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board. -#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board. -#define STK600_RC032X 48 //!< STK600 with RC032X routing card board. -#define SAM4S_EK2 49 //!< SAM4S-EK2 board. -#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board. -#define SAM4E_EK 51 //!< SAM4E-EK board. -#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board. -#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board. -#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board. -#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit. -#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit. -#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit. -#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board. -#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board. -#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board. -#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board. -#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board. -#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB. -#define SAM4C_EK 64 //!< SAM4C-EK board. -#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board. -#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board. -#define SAM4CP16BMB 67 //!< SAM4CP16BMB board. -#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board. -#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board. -#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board. -#define SAM4CMP_DB 71 //!< SAM4CMP demo board. -#define SAM4CMS_DB 72 //!< SAM4CMS demo board. -#define ATPL230AMB 73 //!< ATPL230AMB board. -#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board. -#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board. -#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board. -#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board. -#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board. -#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board. -#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board. -#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board. -#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board. -#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board. -#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices. -#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family. -#define USER_BOARD 99 //!< User-reserved board (if any). -#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader). -//! @} - -/*! \name Extension Boards - */ -//! @{ -#define EXT1102 1 //!< AT32UC3B EXT1102 board -#define MC300 2 //!< AT32UC3 MC300 board -#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1 -#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2 -#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board -#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board -#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A" -#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600 -#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600 -#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600 -#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard -#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board -#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any). -//! @} - -#if BOARD == EVK1100 -# include "evk1100/evk1100.h" -#elif BOARD == EVK1101 -# include "evk1101/evk1101.h" -#elif BOARD == UC3C_EK -# include "uc3c_ek/uc3c_ek.h" -#elif BOARD == EVK1104 -# include "evk1104/evk1104.h" -#elif BOARD == EVK1105 -# include "evk1105/evk1105.h" -#elif BOARD == STK600_RCUC3L0 -# include "stk600/rcuc3l0/stk600_rcuc3l0.h" -#elif BOARD == UC3L_EK -# include "uc3l_ek/uc3l_ek.h" -#elif BOARD == STK600_RCUC3L4 -# include "stk600/rcuc3l4/stk600_rcuc3l4.h" -#elif BOARD == XPLAIN -# include "xplain/xplain.h" -#elif BOARD == STK600_MEGA -/*No header-file to include*/ -#elif BOARD == STK600_MEGA_RF -# include "stk600.h" -#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO -# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h" -#elif BOARD == ATMEGA256RFR2_ZIGBIT -# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h" -#elif BOARD == STK600_RC032X -# include "stk600/rc032x/stk600_rc032x.h" -#elif BOARD == STK600_RC044X -# include "stk600/rc044x/stk600_rc044x.h" -#elif BOARD == STK600_RC064X -# include "stk600/rc064x/stk600_rc064x.h" -#elif BOARD == STK600_RC100X -# include "stk600/rc100x/stk600_rc100x.h" -#elif BOARD == UC3_A3_XPLAINED -# include "uc3_a3_xplained/uc3_a3_xplained.h" -#elif BOARD == UC3_L0_XPLAINED -# include "uc3_l0_xplained/uc3_l0_xplained.h" -#elif BOARD == STK600_RCUC3B0 -# include "stk600/rcuc3b0/stk600_rcuc3b0.h" -#elif BOARD == STK600_RCUC3D -# include "stk600/rcuc3d/stk600_rcuc3d.h" -#elif BOARD == STK600_RCUC3C0 -# include "stk600/rcuc3c0/stk600_rcuc3c0.h" -#elif BOARD == SAMG53_XPLAINED_PRO -# include "samg53_xplained_pro/samg53_xplained_pro.h" -#elif BOARD == SAMG55_XPLAINED_PRO -# include "samg55_xplained_pro/samg55_xplained_pro.h" -#elif BOARD == XMEGA_B1_XPLAINED -# include "xmega_b1_xplained/xmega_b1_xplained.h" -#elif BOARD == STK600_RC064X_LCDX -# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h" -#elif BOARD == STK600_RC100X_LCDX -# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h" -#elif BOARD == XMEGA_A1_XPLAINED -# include "xmega_a1_xplained/xmega_a1_xplained.h" -#elif BOARD == XMEGA_A1U_XPLAINED_PRO -# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h" -#elif BOARD == UC3_L0_XPLAINED_BC -# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h" -#elif BOARD == SAM3S_EK -# include "sam3s_ek/sam3s_ek.h" -# include "system_sam3s.h" -#elif BOARD == SAM3S_EK2 -# include "sam3s_ek2/sam3s_ek2.h" -# include "system_sam3sd8.h" -#elif BOARD == SAM3U_EK -# include "sam3u_ek/sam3u_ek.h" -# include "system_sam3u.h" -#elif BOARD == SAM3X_EK -# include "sam3x_ek/sam3x_ek.h" -# include "system_sam3x.h" -#elif BOARD == SAM3N_EK -# include "sam3n_ek/sam3n_ek.h" -# include "system_sam3n.h" -#elif BOARD == SAM4S_EK -# include "sam4s_ek/sam4s_ek.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_WPIR_RD -# include "sam4s_wpir_rd/sam4s_wpir_rd.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_XPLAINED -# include "sam4s_xplained/sam4s_xplained.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_EK2 -# include "sam4s_ek2/sam4s_ek2.h" -# include "system_sam4s.h" -#elif BOARD == MEGA_1284P_XPLAINED -/*No header-file to include*/ -#elif BOARD == ARDUINO_DUE_X -# include "arduino_due_x/arduino_due_x.h" -# include "system_sam3x.h" -#elif BOARD == SAM4L_EK -# include "sam4l_ek/sam4l_ek.h" -#elif BOARD == SAM4E_EK -# include "sam4e_ek/sam4e_ek.h" -#elif BOARD == SAMD20_XPLAINED_PRO -# include "samd20_xplained_pro/samd20_xplained_pro.h" -#elif BOARD == SAMD21_XPLAINED_PRO -# include "samd21_xplained_pro/samd21_xplained_pro.h" -#elif BOARD == SAMR21_XPLAINED_PRO -# include "samr21_xplained_pro/samr21_xplained_pro.h" -#elif BOARD == SAMD11_XPLAINED_PRO -# include "samd11_xplained_pro/samd11_xplained_pro.h" -#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__) -# include "saml21_xplained_pro/saml21_xplained_pro.h" -#elif BOARD == SAML22_XPLAINED_PRO -# include "saml22_xplained_pro/saml22_xplained_pro.h" -#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__) -# include "saml21_xplained_pro_b/saml21_xplained_pro.h" -#elif BOARD == SAMD10_XPLAINED_MINI -# include "samd10_xplained_mini/samd10_xplained_mini.h" -#elif BOARD == SAMDA1_XPLAINED_PRO -# include "samda1_xplained_pro/samda1_xplained_pro.h" -#elif BOARD == SAMC21_XPLAINED_PRO -# include "samc21_xplained_pro/samc21_xplained_pro.h" -#elif BOARD == SAM4N_XPLAINED_PRO -# include "sam4n_xplained_pro/sam4n_xplained_pro.h" -#elif BOARD == SAMW25_XPLAINED_PRO -# include "samw25_xplained_pro/samw25_xplained_pro.h" -#elif BOARD == SAMV71_XPLAINED_ULTRA -# include "samv71_xplained_ultra/samv71_xplained_ultra.h" -#elif BOARD == MEGA1284P_XPLAINED_BC -# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h" -#elif BOARD == UC3_L0_QT600 -# include "uc3_l0_qt600/uc3_l0_qt600.h" -#elif BOARD == XMEGA_A3BU_XPLAINED -# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h" -#elif BOARD == XMEGA_E5_XPLAINED -# include "xmega_e5_xplained/xmega_e5_xplained.h" -#elif BOARD == UC3B_BOARD_CONTROLLER -# include "uc3b_board_controller/uc3b_board_controller.h" -#elif BOARD == RZ600 -# include "rz600/rz600.h" -#elif BOARD == STK600_RCUC3A0 -# include "stk600/rcuc3a0/stk600_rcuc3a0.h" -#elif BOARD == ATXMEGA128A1_QT600 -# include "atxmega128a1_qt600/atxmega128a1_qt600.h" -#elif BOARD == STK600_RCUC3L3 -# include "stk600/rcuc3l3/stk600_rcuc3l3.h" -#elif BOARD == SAM4S_XPLAINED_PRO -# include "sam4s_xplained_pro/sam4s_xplained_pro.h" -#elif BOARD == SAM4L_XPLAINED_PRO -# include "sam4l_xplained_pro/sam4l_xplained_pro.h" -#elif BOARD == SAM4L8_XPLAINED_PRO -# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h" -#elif BOARD == SAM4C_EK -# include "sam4c_ek/sam4c_ek.h" -#elif BOARD == SAM4CMP_DB -# include "sam4cmp_db/sam4cmp_db.h" -#elif BOARD == SAM4CMS_DB -# include "sam4cms_db/sam4cms_db.h" -#elif BOARD == SAM4CP16BMB -# include "sam4cp16bmb/sam4cp16bmb.h" -#elif BOARD == ATPL230AMB -# include "atpl230amb/atpl230amb.h" -#elif BOARD == SIMULATOR_XMEGA_A1 -# include "simulator/xmega_a1/simulator_xmega_a1.h" -#elif BOARD == XMEGA_C3_XPLAINED -# include "xmega_c3_xplained/xmega_c3_xplained.h" -#elif BOARD == XMEGA_RF233_ZIGBIT -# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h" -#elif BOARD == XMEGA_A3_REB_CBB -# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h" -#elif BOARD == ATMEGARFX_RCB -# include "atmegarfx_rcb/atmegarfx_rcb.h" -#elif BOARD == RCB256RFR2_XPRO -# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h" -#elif BOARD == XMEGA_RF212B_ZIGBIT -# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h" -#elif BOARD == SAM4E_XPLAINED_PRO -# include "sam4e_xplained_pro/sam4e_xplained_pro.h" -#elif BOARD == AVR_SIMULATOR_UC3 -# include "avr_simulator_uc3/avr_simulator_uc3.h" -#elif BOARD == USER_BOARD -// User-reserved area: #include the header file of your board here (if any). -# include "user_board.h" -#elif BOARD == ATMEGA328P_XPLAINED_MINI -# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h" -#elif BOARD == DUMMY_BOARD -# include "dummy/dummy_board.h" -#else -# error No known Atmel board defined -#endif - -#if (defined EXT_BOARD) -# if EXT_BOARD == MC300 -# include "mc300/mc300.h" -# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \ - (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \ - (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD) -# include "sensors_xplained/sensors_xplained.h" -# elif EXT_BOARD == RZ600_AT86RF231 -# include "at86rf231/at86rf231.h" -# elif EXT_BOARD == RZ600_AT86RF230B -# include "at86rf230b/at86rf230b.h" -# elif EXT_BOARD == RZ600_AT86RF212 -# include "at86rf212/at86rf212.h" -# elif EXT_BOARD == SECURITY_XPLAINED -# include "security_xplained.h" -# elif EXT_BOARD == USER_EXT_BOARD -// User-reserved area: #include the header file of your extension board here -// (if any). -# endif -#endif - - -#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__)) -#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. - -/*! \brief This function initializes the board target resources - * - * This function should be called to ensure proper initialization of the target - * board hardware connected to the part. - */ -extern void board_init(void); - -#endif // #ifdef __AVR32_ABI_COMPILER__ -#else -/*! \brief This function initializes the board target resources - * - * This function should be called to ensure proper initialization of the target - * board hardware connected to the part. - */ -extern void board_init(void); -#endif - - -#ifdef __cplusplus -} -#endif - -/** - * \} - */ - -#endif // _BOARD_H_ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_board.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_board.h deleted file mode 100644 index 1af12b19c04..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_board.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Board configuration. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H_INCLUDED -#define CONF_BOARD_H_INCLUDED - -#define BAORD SAMG55_XPLAINED_PRO - -#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_clock.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_clock.h deleted file mode 100644 index dee333aa39e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_clock.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * \brief SAMG55 clock configuration. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_CLOCK_H_INCLUDED -#define CONF_CLOCK_H_INCLUDED - -/* - * ===== System Clock (MCK) Source Options - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_16M_RC - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_24M_RC - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS - */ -#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK - -/* - * ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES)) - */ -#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 -/* - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 - */ - -/* - * ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) - * Use mul and div effective values here. - */ -#define CONFIG_PLL0_SOURCE PLL_SRC_SLCK_XTAL -#define CONFIG_PLL0_MUL 3662 -#define CONFIG_PLL0_DIV 1 - -/* - * ===== Target frequency (System clock) - * - External XTAL frequency: 32768Hz - * - System clock source: SLCK XTAL - * - System clock prescaler: 1 (divided by 1) - * - PLLA source: SLCK_XTAL - * - PLLA output: SLCK_XTAL * 3662 / 1 - * - System clock: SLCK_XTAL * 3662 / 1 / 1 = 120MHz - */ - -#endif /* CONF_CLOCK_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_extint.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_extint.h deleted file mode 100644 index 592702b1a8b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_extint.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * \file - * - * \brief SAM G55 External Interrupt Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef CONF_EXTINT_H_INCLUDED -#define CONF_EXTINT_H_INCLUDED - -#include - -/** - * Push button definitions for sleep mode and active mode - * @{ - */ -#define PIN_PUSHBUTTON_WAKEUP_PIO PIOA -#define PIN_PUSHBUTTON_WAKEUP_MASK PIO_PA2 -#define PIN_PUSHBUTTON_WAKEUP_ID ID_PIOA -#define PIN_PUSHBUTTON_WAKEUP_ATTR PIO_DEFAULT -/** @} */ - -/** Wakeup pin for wait mode: SW0 */ -#define WAKEUP_WAIT_INPUT_ID (1u << 2) -/** Wakeup pin for backup mode: Touchscreen controller IRQ pin */ -#define WAKEUP_BACKUP_INPUT_ID (1u << 2) - -void button_cb(void); -static inline void button_handler(uint32_t ul_id, uint32_t ul_mask); - -/* Button Initialize */ -static inline void button_init(void) -{ - /* Adjust PIO debounce filter parameters, using 10 Hz filter. */ - pio_set_debounce_filter(PIN_PUSHBUTTON_WAKEUP_PIO, - PIN_PUSHBUTTON_WAKEUP_MASK, 10); - - /* Initialize PIO interrupt handlers, see PIO definition in board.h. */ - pio_handler_set(PIN_PUSHBUTTON_WAKEUP_PIO, PIN_PUSHBUTTON_WAKEUP_ID, - PIN_PUSHBUTTON_WAKEUP_MASK, PIN_PUSHBUTTON_WAKEUP_ATTR, - button_handler); - - /* Enable PIO controller IRQs. */ - NVIC_EnableIRQ((IRQn_Type)PIN_PUSHBUTTON_WAKEUP_ID); - - /* Enable PIO line interrupts. */ - pio_enable_interrupt(PIN_PUSHBUTTON_WAKEUP_PIO, - PIN_PUSHBUTTON_WAKEUP_MASK); -} - -/** - * \brief Handler for button interrupt. - * - * \note This interrupt is for waking up from sleep mode or exiting from active - * mode. - */ -static inline void button_handler(uint32_t ul_id, uint32_t ul_mask) -{ - if (PIN_PUSHBUTTON_WAKEUP_ID == ul_id && - PIN_PUSHBUTTON_WAKEUP_MASK == ul_mask) { - button_cb(); - } -} - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_serialdrv.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_serialdrv.h deleted file mode 100644 index 09247b58cb1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_serialdrv.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - * \file - * - * \brief SAM G55 serial driver configuration. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CONF_SERIALDRV_H_INCLUDED -#define CONF_SERIALDRV_H_INCLUDED - -/* BTLC1000 Wakeup Pin */ -#define BTLC1000_WAKEUP_PIN (EXT1_PIN_6) - -/* BTLC1000 Chip Enable Pin */ -#define BTLC1000_CHIP_ENABLE_PIN (EXT1_PIN_10) - -/* BTLC1000 50ms Reset Duration */ -#define BTLC1000_RESET_MS (50) - -/* set port pin high */ -#define IOPORT_PIN_LEVEL_HIGH (true) -/* Set port pin low */ -#define IOPORT_PIN_LEVEL_LOW (false) - -/** UART Interface */ -#define BLE_UART EXT1_UART_MODULE -#define BLE_UART_ID ID_FLEXCOM0 -#define BLE_USART_FLEXCOM FLEXCOM0 -#define BLE_UART_IRQn FLEXCOM0_IRQn -/* Configuration for console uart IRQ handler */ -#define BLE_UART_Handler FLEXCOM0_Handler - -/** Baudrate setting */ -#define CONF_UART_BAUDRATE (115200UL) -/** Character length setting */ -#define CONF_UART_CHAR_LENGTH US_MR_CHRL_8_BIT -/** Parity setting */ -#define CONF_UART_PARITY US_MR_PAR_NO -/** Stop bits setting */ -#define CONF_UART_STOP_BITS US_MR_NBSTOP_1_BIT - -void serial_rx_callback(void); -void serial_tx_callback(void); - -#define SERIAL_DRV_RX_CB serial_rx_callback -#define SERIAL_DRV_TX_CB serial_tx_callback -#define SERIAL_DRV_TX_CB_ENABLE true -#define SERIAL_DRV_RX_CB_ENABLE true - -#define BLE_MAX_TX_PAYLOAD_SIZE 512 -#define BLE_MAX_RX_PAYLOAD_SIZE 512 - -/* Set BLE Wakeup pin to be low */ -static inline bool ble_wakeup_pin_level(void) -{ - return (ioport_get_pin_level(BTLC1000_WAKEUP_PIN)); -} - -/* Set BLE Wakeup pin to be low */ -static inline void ble_wakeup_pin_set_low(void) -{ - ioport_set_pin_level(BTLC1000_WAKEUP_PIN, - IOPORT_PIN_LEVEL_LOW); -} - -/* Set wakeup pin to high */ -static inline void ble_wakeup_pin_set_high(void) -{ - ioport_set_pin_level(BTLC1000_WAKEUP_PIN, - IOPORT_PIN_LEVEL_HIGH); -} - -/* Set enable pin to Low */ -static inline void ble_enable_pin_set_low(void) -{ - ioport_set_pin_level(BTLC1000_CHIP_ENABLE_PIN, - IOPORT_PIN_LEVEL_LOW); -} - -/* Set enable pin to high */ -static inline void ble_enable_pin_set_high(void) -{ - ioport_set_pin_level(BTLC1000_CHIP_ENABLE_PIN, - IOPORT_PIN_LEVEL_HIGH); -} - -/* Configure the BTLC1000 control(chip_enable, wakeup) pins */ -static inline void ble_configure_control_pin(void) -{ - /* initialize the delay before use */ - delay_init(); - - /* Configure control pins as output */ - ioport_init(); - - ioport_set_pin_dir(BTLC1000_WAKEUP_PIN, IOPORT_DIR_OUTPUT); - - /* set wakeup pin to low */ - ble_wakeup_pin_set_high(); - - ioport_set_pin_dir(BTLC1000_CHIP_ENABLE_PIN, IOPORT_DIR_OUTPUT); - - /* set chip enable to low */ - ble_enable_pin_set_low(); - - /* Delay for 50ms */ - delay_ms(BTLC1000_RESET_MS); - - /* set chip enable to high */ - ble_enable_pin_set_high(); -} - -static inline void ble_reset(void) -{ - /* BTLC1000 Reset Sequence @Todo */ - ble_enable_pin_set_high(); - ble_wakeup_pin_set_high(); - delay_ms(BTLC1000_RESET_MS); - - ble_enable_pin_set_low(); - ble_wakeup_pin_set_low(); - delay_ms(BTLC1000_RESET_MS); - - ble_enable_pin_set_high(); - ble_wakeup_pin_set_high(); - delay_ms(BTLC1000_RESET_MS); -} - - -#endif /* CONF_SERIALDRV_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_sleepmgr.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_sleepmgr.h deleted file mode 100644 index 4c6708d91cf..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_sleepmgr.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief Sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_H -#define CONF_SLEEPMGR_H - -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_timer.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_timer.h deleted file mode 100644 index 36e69cf13d1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_timer.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief Timer Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef CONF_TIMER_H_INCLUDED -#define CONF_TIMER_H_INCLUDED - -#define TIMER (TC0) -#define TIMER_CHANNEL_ID 0 -#define ID_TC (ID_TC0) - -#define DEF_1MHZ (1000000) -#define DEF_120MHz (120000000) -#define TIMER_OVF_COUNT_1SEC (DEF_120MHz/(128*65535)) - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_uart_serial.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_uart_serial.h deleted file mode 100644 index 80a5e0e8f6b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_uart_serial.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * \file - * - * \brief USART Serial Configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_USART_SERIAL_H_INCLUDED -#define CONF_USART_SERIAL_H_INCLUDED - -/** UART Interface */ -#define CONF_UART CONSOLE_UART -/** Baudrate setting */ -#define CONF_UART_BAUDRATE (115200UL) -/** Character length setting */ -#define CONF_UART_CHAR_LENGTH US_MR_CHRL_8_BIT -/** Parity setting */ -#define CONF_UART_PARITY US_MR_PAR_NO -/** Stop bits setting */ -#define CONF_UART_STOP_BITS US_MR_NBSTOP_1_BIT - -#endif/* CONF_USART_SERIAL_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.c deleted file mode 100644 index 83dd2651824..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.c +++ /dev/null @@ -1,518 +0,0 @@ -/** - * \file - * - * \brief ADC Controller driver. - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "adc2.h" -#include "sleepmgr.h" -#include "status_codes.h" -#include "sysclk.h" -#include "pmc.h" - -/** - * \defgroup sam_drivers_adc2_group Analog-to-Digital Controller - * - * See \ref sam_adc2_quickstart. - * - * Driver for the Analog-to-Digital Controller. This driver provides access to - * the main features of the ADC controller. - * - * @{ - */ - -/* The number of channel in channel sequence1 register */ -#define ADC_SEQ1_CHANNEL_NUM (8UL) - -/* The number of ADC interrupt source */ -#define ADC_NUM_OF_INTERRUPT_SOURCE (24UL) - - -const uint32_t adc_interrupt_mask[ADC_NUM_OF_INTERRUPT_SOURCE] = { - ADC_ISR_EOC0, ADC_ISR_EOC1, ADC_ISR_EOC2, ADC_ISR_EOC3, - ADC_ISR_EOC4, ADC_ISR_EOC5, ADC_ISR_EOC6, ADC_ISR_EOC7, -#if (SAM4N) - ADC_ISR_EOC8, ADC_ISR_EOC9, ADC_ISR_EOC10, ADC_ISR_EOC11, - ADC_ISR_EOC12, ADC_ISR_EOC13, ADC_ISR_EOC14, ADC_ISR_EOC15, - ADC_ISR_EOC16, -#endif -#ifdef TEMP_SENSOR - ADC_ISR_TEMPCHG, -#endif - ADC_ISR_EOCAL, ADC_ISR_DRDY, - ADC_ISR_GOVRE, ADC_ISR_COMPE, ADC_ISR_ENDRX, ADC_ISR_RXBUFF, -}; - -adc_callback_t adc_callback_pointer[ADC_NUM_OF_INTERRUPT_SOURCE]; - -/** - * \brief Get the ADC default configurations. - * - * Use to initialize the configuration structure to known default values. This - * function should be called at the start of any ADC initiation. - * - * The default configuration is as follows: - * - 10-bit resolution - * - ADC clock frequency is 6MHz - * - Start Up Time is 64 periods ADC clock - * - Tracking Time is 3 periods of ADC clock - * - Transfer Period field shall be programmed with 2 as datasheet said - * - The controller converts channels in a simple numeric order - * - Appends the channel number to the conversion result in ADC_LCDR register - * - Only a Single Trigger is required to get an averaged value - * - * \param cfg Pointer to configuration structure to be initiated. - */ -void adc_get_config_defaults(struct adc_config *const cfg) -{ - /* Sanity check argument. */ - Assert(cfg); - -#if SAMG55 - cfg->resolution = ADC_12_BITS; -#else - cfg->resolution = ADC_10_BITS; -#endif - cfg->mck = sysclk_get_cpu_hz(); - cfg->adc_clock = 6000000UL; - cfg->startup_time = ADC_STARTUP_TIME_4; - cfg->tracktim = 2; - cfg->transfer = 2; - cfg->useq = false; - cfg->tag = false; - cfg->aste = false; -} - -/** - * \internal - * \brief Configure the ADC Module. - * - * \param adc Base address of the ADC - * \param config Configuration for the ADC - */ -static void adc_set_config(Adc *const adc, struct adc_config *config) -{ - uint32_t reg = 0; - - reg = (config->useq ? ADC_MR_USEQ_REG_ORDER : 0) | - ADC_MR_PRESCAL(config->mck / - (2 * config->adc_clock) - 1) | - ADC_MR_TRACKTIM(config->tracktim) | - ADC_MR_TRANSFER(config->transfer) | - (config->startup_time); - - adc->ADC_MR = reg; - - adc->ADC_EMR = (config->tag ? ADC_EMR_TAG : 0) | - (config->aste ? ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE : 0); - - adc_set_resolution(adc, config->resolution); -} - -#ifdef TEMP_SENSOR -/** - * \brief Get the ADC Temperature Sensor default configurations. - * - * Use to initialize the configuration structure to known default values. - * - * The default configuration is as follows: - * - Generates an event when the converted data is in the comparison window - * - The window range is 0xFF ~ 0xFFF - * - * \param cfg Pointer to temperature sensor configuration structure - * to be initiated. - */ -void adc_temp_sensor_get_config_defaults( - struct adc_temp_sensor_config *const cfg) -{ - /*Sanity check argument. */ - Assert(cfg); - - cfg->tempon = true; - cfg->mode = ADC_TEMP_CMP_MODE_2; - cfg->low_threshold = 0xFF; - cfg->high_threshold = 0xFFF; -} - -/** - * \brief Configure the ADC temperature sensor. - * - * \param adc Base address of the ADC - * \param config Configuration for the ADC temperature sensor - */ -void adc_temp_sensor_set_config(Adc *const adc, - struct adc_temp_sensor_config *config) -{ - uint32_t reg = 0; - - reg = ((config->tempon) ? ADC_TEMPMR_TEMPON : 0) | (config->mode); - adc->ADC_TEMPMR = reg; - - adc->ADC_TEMPCWR = ADC_TEMPCWR_TLOWTHRES(config->low_threshold) | - ADC_TEMPCWR_THIGHTHRES(config->high_threshold); -} -#endif - -#if (SAMG) -/** - * \brief Get the Last Channel Specific Measurement default configurations. - * - * Use to initialize the configuration structure to known default values. - * - * The default configuration is as follows: - * - Generates an event when the converted data is in the comparison window - * - The window range is 0xFF ~ 0xFFF - * - * \param cfg Pointer to last channel configuration structure - * to be initiated. - */ -void adc_last_channel_get_config_defaults( - struct adc_last_channel_config *const cfg) -{ - /*Sanity check argument. */ - Assert(cfg); - - cfg->dual_trig_on = true; - cfg->mode = ADC_LAST_CHANNEL_CMP_MODE_2; - cfg->low_threshold = 0xFF; - cfg->high_threshold = 0xFFF; -} - -/** - * \brief Configure the ADC Last Channel Specific Measurement. - * - * \param adc Base address of the ADC - * \param config Configuration for the last channel - */ -void adc_last_channel_set_config(Adc *const adc, - struct adc_last_channel_config *config) -{ - uint32_t reg = 0; - - reg = ((config->dual_trig_on) ? ADC_LCTMR_DUALTRIG : 0) | (config->mode); - adc->ADC_LCTMR = reg; - - adc->ADC_LCCWR = ADC_LCCWR_LOWTHRES(config->low_threshold) | - ADC_LCCWR_HIGHTHRES(config->high_threshold); -} -#endif - -/** - * \brief Initialize the ADC Module. - * - * \param adc Base address of the ADC - * \param config Configuration for the ADC - * - * \retval STATUS_OK Initialization is finished. - * \retval STATUS_ERR_BUSY Initialization failed. - */ -enum status_code adc_init(Adc *const adc, struct adc_config *config) -{ - Assert(adc); - Assert(config); - - if ((adc_get_interrupt_status(adc) & ADC_ISR_DRDY) == ADC_ISR_DRDY) { - return STATUS_ERR_BUSY; - } - - /* Reset and configure the ADC module */ - adc->ADC_CR = ADC_CR_SWRST; - adc_set_config(adc, config); - - uint32_t i; - for (i = 0; i < ADC_NUM_OF_INTERRUPT_SOURCE; i++) { - adc_callback_pointer[i] = 0; - } - - return STATUS_OK; -} - -/** - * \brief Configure conversion resolution. - * - * \param adc Base address of the ADC. - * \param res Conversion resolution. - * - */ -void adc_set_resolution(Adc *const adc, - const enum adc_resolution res) -{ -#if SAMG55 - adc->ADC_EMR |= res; -#else - if (res == ADC_11_BITS || res == ADC_12_BITS) { - adc->ADC_MR &= ~ADC_MR_LOWRES; - adc->ADC_EMR |= res; - } else { - adc->ADC_MR |= res; - adc->ADC_EMR &= ~ADC_EMR_OSR_Msk; - } -#endif -} - -/** - * \brief Configure comparison mode. - * - * \param adc Base address of the ADC. - * \param mode Comparison mode. - * \param channel Comparison Selected Channel. - * \param cmp_filter Compare Event Filtering. - */ -void adc_set_comparison_mode(Adc *const adc, - const enum adc_cmp_mode mode, - const enum adc_channel_num channel, uint8_t cmp_filter) -{ - if (channel != ADC_CHANNEL_ALL) { - adc_ch_sanity_check(adc, channel); - } - - uint32_t reg; - - reg = adc->ADC_EMR; - - reg &= ~(ADC_EMR_CMPSEL_Msk | - ADC_EMR_CMPMODE_Msk | - ADC_EMR_CMPFILTER_Msk); - reg |= mode | - ((channel == ADC_CHANNEL_ALL) ? ADC_EMR_CMPALL - : ADC_EMR_CMPSEL(channel)) | - ADC_EMR_CMPFILTER(cmp_filter); - - adc->ADC_EMR = reg; -} - -/** - * \brief Configure ADC power mode. - * - * \param adc Base address of the ADC. - * \param mode ADC power mode value. - */ -void adc_set_power_mode(Adc *const adc, - const enum adc_power_mode mode) -{ - uint32_t reg; - - reg = adc->ADC_MR; - - switch (mode) { - case ADC_POWER_MODE_0: - reg |= ADC_MR_SLEEP_NORMAL; - break; - - case ADC_POWER_MODE_1: - reg |= ADC_MR_SLEEP_SLEEP; - break; - } - - adc->ADC_MR = reg; -} - -/** - * \brief Set callback for ADC - * - * \param adc Base address of the ADC - * \param source Interrupt source - * \param callback Callback function pointer - * \param irq_level Interrupt level - */ -void adc_set_callback(Adc *const adc, enum adc_interrupt_source source, - adc_callback_t callback, uint8_t irq_level) -{ - Assert(adc); - Assert(callback); - - adc_callback_pointer[source] = callback; - irq_register_handler(ADC_IRQn, irq_level); - - /* Enable the specified interrupt source */ - adc_enable_interrupt(adc, source); -} - -/** - * \brief Enable ADC interrupts. - * - * \param adc Base address of the ADC. - * \param interrupt_source Interrupts to be enabled. - */ -void adc_enable_interrupt(Adc *const adc, - enum adc_interrupt_source interrupt_source) -{ - if (interrupt_source == ADC_INTERRUPT_ALL) { - adc->ADC_IER = ADC_INTERRUPT_ALL; - return; - } else { - adc->ADC_IER = adc_interrupt_mask[interrupt_source]; - } -} - -/** - * \brief Disable ADC interrupts. - * - * \param adc Base address of the ADC. - * \param interrupt_source Interrupts to be disabled. - */ -void adc_disable_interrupt(Adc *const adc, - enum adc_interrupt_source interrupt_source) -{ - if (interrupt_source == ADC_INTERRUPT_ALL) { - adc->ADC_IDR = ADC_INTERRUPT_ALL; - return; - } else { - adc->ADC_IDR = adc_interrupt_mask[interrupt_source]; - } -} - -/** - * \internal - * \brief Common ADC interrupt handler - * - * The optional callback used by the interrupt handler is set by the - * adc_set_callback() function. - * - * \param inst_num ADC instance number to handle interrupt for - * \param source Interrupt source number - */ -static void adc_interrupt(enum adc_interrupt_source source) -{ - if (adc_callback_pointer[source]) { - adc_callback_pointer[source](); - } -} - -/** - * \internal - * \brief Call the callback function if the corresponding interrupt is asserted - * - * \param adc Base address of the ADC. - */ -static void adc_process_callback(Adc *const adc) -{ - volatile uint32_t status; - uint32_t cnt; - - status = adc_get_interrupt_status(adc); - - for (cnt = 0; cnt < ADC_NUM_OF_INTERRUPT_SOURCE; cnt++) { - if (status & adc_interrupt_mask[cnt]) { - adc_interrupt((enum adc_interrupt_source)cnt); - } - } -} - -/** - * \brief Interrupt handler for ADC. - */ -void ADC_Handler(void) -{ - adc_process_callback(ADC); -} - -/** - * \brief Enable ADC Module. - * - */ -void adc_enable(void) -{ - /* Enable peripheral clock. */ - pmc_enable_periph_clk(ID_ADC); - sleepmgr_lock_mode(SLEEP_MODE_ADC); -} - -/** - * \brief Disable ADC Module. - * - */ -void adc_disable(void) -{ - /* Disable peripheral clock. */ - pmc_disable_periph_clk(ID_ADC); - sleepmgr_unlock_mode(SLEEP_MODE_ADC); -} - -/** - * \brief Configure conversion sequence. - * - * \param adc Base address of the ADC. - * \param ch_list Channel sequence list. - * \param uc_num Number of channels in the list. - */ -void adc_configure_sequence(Adc *const adc, - const enum adc_channel_num ch_list[], uint8_t uc_num) -{ - uint8_t uc_counter; - - /* Set user sequence mode */ - adc->ADC_MR |= ADC_MR_USEQ_REG_ORDER; -#if (SAM4N) - adc->ADC_SEQR1 = 0; - adc->ADC_SEQR2 = 0; -#endif -#if (SAMG) - adc->ADC_SEQR1 = 0; -#endif - - if (uc_num <= ADC_SEQ1_CHANNEL_NUM) { - for (uc_counter = 0; uc_counter < uc_num; uc_counter++) { -#if (SAM4N || SAMG) - adc->ADC_SEQR1 -#endif - |= ch_list[uc_counter] << (4 * uc_counter); - } - } else { - for (uc_counter = 0; uc_counter <= ADC_SEQ1_CHANNEL_NUM; - uc_counter++) { -#if (SAM4N || SAMG) - adc->ADC_SEQR1 -#endif - |= ch_list[uc_counter] << (4 * uc_counter); - } - for (uc_counter = 0; uc_counter < uc_num - ADC_SEQ1_CHANNEL_NUM; - uc_counter++) { -#if (SAM4N) - adc->ADC_SEQR2 |= ch_list[8 + uc_counter] << (4 * uc_counter); -#endif - } - } -} - -//@} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.h deleted file mode 100644 index 749fa1af5ae..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.h +++ /dev/null @@ -1,813 +0,0 @@ -/** - * \file - * - * \brief ADC Controller driver. - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef ADC2_H_INCLUDED -#define ADC2_H_INCLUDED - -#include "compiler.h" -#include "status_codes.h" - -#if (SAM4N) -#define TEMP_SENSOR -#define SLEEP_MODE_ADC SLEEPMGR_SLEEP_WFI -#endif - -#if (SAMG) -#define NO_TEMP_SENSOR -#define SLEEP_MODE_ADC SLEEPMGR_ACTIVE -#endif - -/** Write Protect Key */ -#ifndef ADC_WPMR_WPKEY_PASSWD -#define ADC_WPMR_WPKEY_PASSWD (0x414443u << 8) -#endif - -/** Definitions for ADC resolution */ -enum adc_resolution { -#if SAMG55 - ADC_12_BITS = ADC_EMR_OSR_NO_AVERAGE, /* ADC 12-bit resolution */ - ADC_13_BITS = ADC_EMR_OSR_OSR4, /* ADC 13-bit resolution */ - ADC_14_BITS = ADC_EMR_OSR_OSR16, /* ADC 14-bit resolution */ - ADC_15_BITS = ADC_EMR_OSR_OSR64, /* ADC 15-bit resolution */ - ADC_16_BITS = ADC_EMR_OSR_OSR256, /* ADC 16-bit resolution */ -#else - ADC_8_BITS = ADC_MR_LOWRES_BITS_8, /* ADC 8-bit resolution */ - ADC_10_BITS = ADC_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */ - ADC_11_BITS = ADC_EMR_OSR_OSR4, /* ADC 11-bit resolution */ - ADC_12_BITS = ADC_EMR_OSR_OSR16 /* ADC 12-bit resolution */ -#endif -}; - -/** Definitions for ADC power mode */ -enum adc_power_mode { - /* ADC core on and reference voltage circuitry on */ - ADC_POWER_MODE_0 = 0, - /* ADC core off and reference voltage circuitry off */ - ADC_POWER_MODE_1 -}; - -/** Definitions for ADC trigger */ -enum adc_trigger { - /* Starting a conversion is only possible by software. */ - ADC_TRIG_SW = ADC_MR_TRGEN_DIS, - /* External trigger */ - ADC_TRIG_EXT = ADC_MR_TRGSEL_ADC_TRIG0 | ADC_MR_TRGEN, - /* TIO Output of the Timer Counter Channel 0 */ - ADC_TRIG_TIO_CH_0 = ADC_MR_TRGSEL_ADC_TRIG1 | ADC_MR_TRGEN, - /* TIO Output of the Timer Counter Channel 1 */ - ADC_TRIG_TIO_CH_1 = ADC_MR_TRGSEL_ADC_TRIG2 | ADC_MR_TRGEN, - /* TIO Output of the Timer Counter Channel 2 */ - ADC_TRIG_TIO_CH_2 = ADC_MR_TRGSEL_ADC_TRIG3 | ADC_MR_TRGEN, -#if (SAMG) - /* RTCOUT0 */ - ADC_TRIG_RTC_0 = ADC_MR_TRGSEL_ADC_TRIG4 | ADC_MR_TRGEN, - /* RTTINC */ - ADC_TRIG_RTT = ADC_MR_TRGSEL_ADC_TRIG5 | ADC_MR_TRGEN, -#endif - /* Freerun mode conversion. */ - ADC_TRIG_FREERUN = 0xFF -}; - -/** Definitions for ADC channel number */ -enum adc_channel_num { - ADC_CHANNEL_0 = 0, - ADC_CHANNEL_1, - ADC_CHANNEL_2, - ADC_CHANNEL_3, - ADC_CHANNEL_4, - ADC_CHANNEL_5, - ADC_CHANNEL_6, - ADC_CHANNEL_7, -#if (SAM4N) - ADC_CHANNEL_8, - ADC_CHANNEL_9, - ADC_CHANNEL_10, - ADC_CHANNEL_11, - ADC_CHANNEL_12, - ADC_CHANNEL_13, - ADC_CHANNEL_14, - ADC_CHANNEL_15, -#endif -#ifdef TEMP_SENSOR - ADC_TEMPERATURE_SENSOR, -#endif - ADC_CHANNEL_ALL = 0xFFFF -}; - -/** Definitions for ADC Start Up Time */ -enum adc_startup_time { - ADC_STARTUP_TIME_0 = ADC_MR_STARTUP_SUT0, - ADC_STARTUP_TIME_1 = ADC_MR_STARTUP_SUT8, - ADC_STARTUP_TIME_2 = ADC_MR_STARTUP_SUT16, - ADC_STARTUP_TIME_3 = ADC_MR_STARTUP_SUT24, - ADC_STARTUP_TIME_4 = ADC_MR_STARTUP_SUT64, - ADC_STARTUP_TIME_5 = ADC_MR_STARTUP_SUT80, - ADC_STARTUP_TIME_6 = ADC_MR_STARTUP_SUT96, - ADC_STARTUP_TIME_7 = ADC_MR_STARTUP_SUT112, - ADC_STARTUP_TIME_8 = ADC_MR_STARTUP_SUT512, - ADC_STARTUP_TIME_9 = ADC_MR_STARTUP_SUT576, - ADC_STARTUP_TIME_10 = ADC_MR_STARTUP_SUT640, - ADC_STARTUP_TIME_11 = ADC_MR_STARTUP_SUT704, - ADC_STARTUP_TIME_12 = ADC_MR_STARTUP_SUT768, - ADC_STARTUP_TIME_13 = ADC_MR_STARTUP_SUT832, - ADC_STARTUP_TIME_14 = ADC_MR_STARTUP_SUT896, - ADC_STARTUP_TIME_15 = ADC_MR_STARTUP_SUT960 -}; - -/** Definitions for Comparison Mode */ -enum adc_cmp_mode { - ADC_CMP_MODE_0 = ADC_EMR_CMPMODE_LOW, - ADC_CMP_MODE_1 = ADC_EMR_CMPMODE_HIGH, - ADC_CMP_MODE_2 = ADC_EMR_CMPMODE_IN, - ADC_CMP_MODE_3 = ADC_EMR_CMPMODE_OUT -}; - -#ifdef TEMP_SENSOR -/** Definitions for Temperature Comparison Mode */ -enum adc_temp_cmp_mode { - ADC_TEMP_CMP_MODE_0 = ADC_TEMPMR_TEMPCMPMOD_LOW, - ADC_TEMP_CMP_MODE_1 = ADC_TEMPMR_TEMPCMPMOD_HIGH, - ADC_TEMP_CMP_MODE_2 = ADC_TEMPMR_TEMPCMPMOD_IN, - ADC_TEMP_CMP_MODE_3 = ADC_TEMPMR_TEMPCMPMOD_OUT -}; -#endif -#if (SAMG) -/** Definitions for Last Channel Specific Measurement Comparison Mode */ -enum adc_last_channel_cmp_mode { - ADC_LAST_CHANNEL_CMP_MODE_0 = ADC_LCTMR_CMPMOD_LOW, - ADC_LAST_CHANNEL_CMP_MODE_1 = ADC_LCTMR_CMPMOD_HIGH, - ADC_LAST_CHANNEL_CMP_MODE_2 = ADC_LCTMR_CMPMOD_IN, - ADC_LAST_CHANNEL_CMP_MODE_3 = ADC_LCTMR_CMPMOD_OUT -}; -#endif - -/** Definitions for Reference Voltage Selection */ -enum adc_refer_voltage_source { - ADC_REFER_VOL_EXTERNAL = 0, - ADC_REFER_VOL_STUCK_AT_MIN, - ADC_REFER_VOL_VDDANA, - ADC_REFER_VOL_IRVS -}; - -/** - * \brief ADC Enhanced configuration structure. - * - * Configuration structure for a ADC Enhanced instance. - * This structure could be initialized by the \ref ADC_get_config_defaults() - * function before being modified by the user application. - */ -struct adc_config { - /** Resolution */ - enum adc_resolution resolution; - /** Master Clock */ - uint32_t mck; - /** ADC Clock */ - uint32_t adc_clock; - /** Start Up Time */ - enum adc_startup_time startup_time; - /** Tracking Time = (tracktim+1) / ADC clock */ - uint8_t tracktim; - /** Transfer Period */ - uint8_t transfer; - /** Use Sequence Enable */ - bool useq; - /** TAG of ADC_LDCR register */ - bool tag; - /** Averaging on Single Trigger Event */ - bool aste; -}; - -#ifdef TEMP_SENSOR -/** ADC Temperature Sensor configuration structure.*/ -struct adc_temp_sensor_config { - /** Temperature Sensor On */ - bool tempon; - /** Temperature Comparison Mode */ - enum adc_temp_cmp_mode mode; - /** Temperature Low Threshold */ - uint16_t low_threshold; - /** Temperature High Threshold */ - uint16_t high_threshold; -}; -#endif - -#if (SAMG) -/** ADC Last Channel Specific Measurement configuration structure.*/ -struct adc_last_channel_config { - /** Specific Measurement On */ - bool dual_trig_on; - /** Specific Measurement Comparison Mode */ - enum adc_last_channel_cmp_mode mode; - /** Specific Measurement Low Threshold */ - uint16_t low_threshold; - /** Specific Measurement High Threshold */ - uint16_t high_threshold; -}; -#endif - -/** ADC interrupt source type */ -enum adc_interrupt_source { - ADC_INTERRUPT_EOC_0 = 0, - ADC_INTERRUPT_EOC_1, - ADC_INTERRUPT_EOC_2, - ADC_INTERRUPT_EOC_3, - ADC_INTERRUPT_EOC_4, - ADC_INTERRUPT_EOC_5, - ADC_INTERRUPT_EOC_6, - ADC_INTERRUPT_EOC_7, -#if (SAM4N) - ADC_INTERRUPT_EOC_8, - ADC_INTERRUPT_EOC_9, - ADC_INTERRUPT_EOC_10, - ADC_INTERRUPT_EOC_11, - ADC_INTERRUPT_EOC_12, - ADC_INTERRUPT_EOC_13, - ADC_INTERRUPT_EOC_14, - ADC_INTERRUPT_EOC_15, - ADC_INTERRUPT_EOC_16, -#endif -#ifdef TEMP_SENSOR - ADC_INTERRUPT_TEMP_CHANGE, -#endif - ADC_INTERRUPT_END_CAL, - ADC_INTERRUPT_DATA_READY, - ADC_INTERRUPT_OVERRUN_ERROR, - ADC_INTERRUPT_COMP_ERROR, - ADC_INTERRUPT_END_RXBUF, - ADC_INTERRUPT_RXBUF_FULL, - ADC_INTERRUPT_ALL = 0xFFFFFFFF -}; - -typedef void (*adc_callback_t)(void); - -void adc_get_config_defaults(struct adc_config *const cfg); -enum status_code adc_init(Adc *const adc, struct adc_config *const config); - -#ifdef TEMP_SENSOR -void adc_temp_sensor_get_config_defaults( - struct adc_temp_sensor_config *const cfg); -void adc_temp_sensor_set_config(Adc *const adc, - struct adc_temp_sensor_config *config); -#endif -#if (SAMG) -void adc_last_channel_get_config_defaults( - struct adc_last_channel_config *const cfg); -void adc_last_channel_set_config(Adc *const adc, - struct adc_last_channel_config *config); -#endif - -void adc_configure_sequence(Adc *const adc, - const enum adc_channel_num ch_list[], const uint8_t uc_num); -void adc_enable(void); -void adc_disable(void); -void adc_set_callback(Adc *const adc, enum adc_interrupt_source source, - adc_callback_t callback, uint8_t irq_level); - -/** - * \internal - * \brief ADC channel sanity check - * - * \param adc Base address of the ADC. - * \param channel Adc channel number. - * - */ -static inline void adc_ch_sanity_check(Adc *const adc, - const enum adc_channel_num channel) -{ - if (adc == ADC) { - Assert((channel < NB_CH_ADC) -#ifdef TEMP_SENSOR - ||(channel == ADC_TEMPERATURE_SENSOR) -#endif - ); - } - - UNUSED(channel); -} - -#if (SAMG) -#if SAMG55 -/** - * \brief Configure ADC clock to mck. - * - * \param adc Base address of the ADC. - * - */ -static inline void adc_select_clock_source_mck(Adc *const adc) -{ - uint32_t reg; - - reg = adc->ADC_EMR; - - reg &= ~ADC_EMR_SRCCLK_PMC_PCK; - - adc->ADC_EMR = reg; -} - -/** - * \brief Configure ADC clock to pck. - * - * \param adc Base address of the ADC. - * - */ -static inline void adc_select_clock_source_pck(Adc *const adc) -{ - uint32_t reg; - - reg = adc->ADC_EMR; - - reg |= ADC_EMR_SRCCLK_PMC_PCK; - - adc->ADC_EMR = reg; -} - -#else -/** - * \brief Configure ADC clock to MCK. - * - * \param adc Base address of the ADC. - * - */ -static inline void adc_set_clock_mck(Adc *const adc) -{ - uint32_t reg; - - reg = adc->ADC_EMR; - - reg |= ADC_MR_DIV1; - - adc->ADC_MR = reg; -} - -/** - * \brief Configure ADC clock to MCK/3. - * - * \param adc Base address of the ADC. - * - */ -static inline void adc_set_clock_mck_div3(Adc *const adc) -{ - uint32_t reg; - - reg = adc->ADC_MR; - - reg &= ~ADC_MR_DIV1; - reg |= ADC_MR_DIV3; - - adc->ADC_MR = reg; -} -#endif -#endif - -/** - * \brief Configure conversion trigger and free run mode. - * - * \param adc Base address of the ADC. - * \param trigger Conversion trigger. - * - */ -static inline void adc_set_trigger(Adc *const adc, - const enum adc_trigger trigger) -{ - uint32_t reg; - - reg = adc->ADC_MR; - - if (trigger == ADC_TRIG_FREERUN) { - reg |= ADC_MR_FREERUN_ON; - } else { - reg &= ~(ADC_MR_TRGSEL_Msk | ADC_MR_TRGEN | ADC_MR_FREERUN_ON); - reg |= trigger; - } - - adc->ADC_MR = reg; -} - -void adc_set_resolution(Adc *const adc, - const enum adc_resolution res); - -void adc_set_comparison_mode(Adc *const adc, - const enum adc_cmp_mode mode, - const enum adc_channel_num channel, - uint8_t cmp_filter); - -/** - * \brief Get comparison mode. - * - * \param adc Base address of the ADC. - * - * \retval Compare mode value. - */ -static inline enum adc_cmp_mode adc_get_comparison_mode(Adc *const adc) -{ - return (enum adc_cmp_mode)(adc->ADC_EMR & ADC_EMR_CMPMODE_Msk); -} - -/** - * \brief Configure ADC compare window. - * - * \param adc Base address of the ADC. - * \param us_low_threshold Low threshold of compare window. - * \param us_high_threshold High threshold of compare window. - */ -static inline void adc_set_comparison_window(Adc *const adc, - const uint16_t us_low_threshold, - const uint16_t us_high_threshold) -{ - adc->ADC_CWR = ADC_CWR_LOWTHRES(us_low_threshold) | - ADC_CWR_HIGHTHRES(us_high_threshold); -} - -/** - * \brief Enable or disable write protection of ADC registers. - * - * \param adc Base address of the ADC. - * \param is_enable 1 to enable, 0 to disable. - */ -static inline void adc_set_writeprotect(Adc *const adc, - const bool is_enable) -{ - if (is_enable) { - adc->ADC_WPMR = ADC_WPMR_WPEN | ADC_WPMR_WPKEY_PASSWD; - } else { - adc->ADC_WPMR = ADC_WPMR_WPKEY_PASSWD; - } -} - -/** - * \brief Indicate write protect status. - * - * \param adc Base address of the ADC. - * - * \return 0 if no write protect violation occurred, or 16-bit write protect - * violation source. - */ -static inline uint32_t adc_get_writeprotect_status(Adc *const adc) -{ - uint32_t reg_value; - - reg_value = adc->ADC_WPSR; - if (reg_value & ADC_WPSR_WPVS) { - return (reg_value & ADC_WPSR_WPVSRC_Msk) >> ADC_WPSR_WPVSRC_Pos; - } else { - return 0; - } -} - -/** - * \brief Get ADC overrun error status. - * - * \param adc Base address of the ADC. - * - * \return ADC overrun error status. - */ -static inline uint32_t adc_get_overrun_status(Adc *const adc) -{ - return adc->ADC_OVER; -} - -/** - * \brief Set ADC averaging on single trigger event - * - * \param adc Base address of the ADC. - */ -static inline void adc_average_on_single_trigger(Adc *const adc) -{ - adc->ADC_EMR |= ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE; -} - -/** - * \brief Set ADC averaging on serval trigger events - * - * \param adc Base address of the ADC. - */ -static inline void adc_average_on_multi_trigger(Adc *const adc) -{ - adc->ADC_EMR &= ~ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE; -} - -/** - * \brief Start analog-to-digital conversion. - * - * \note If one of the hardware event is selected as ADC trigger, - * this function can NOT start analog to digital conversion. - * - * \param adc Base address of the ADC. - */ -static inline void adc_start_software_conversion(Adc *const adc) -{ - adc->ADC_CR = ADC_CR_START; -} - -void adc_set_power_mode(Adc *const adc, - const enum adc_power_mode mode); - -/** - * \brief Enable the specified ADC channel. - * - * \param adc Base address of the ADC. - * \param adc_ch Adc channel number. - */ -static inline void adc_channel_enable(Adc *const adc, - const enum adc_channel_num adc_ch) -{ - if (adc_ch != ADC_CHANNEL_ALL) { - adc_ch_sanity_check(adc, adc_ch); - } - - adc->ADC_CHER = (adc_ch == ADC_CHANNEL_ALL) ? - ADC_CHANNEL_ALL : 1 << adc_ch; -} - -/** - * \brief Disable the specified ADC channel. - * - * \param adc Base address of the ADC. - * \param adc_ch Adc channel number. - */ -static inline void adc_channel_disable(Adc *const adc, - const enum adc_channel_num adc_ch) -{ - if (adc_ch != ADC_CHANNEL_ALL) { - adc_ch_sanity_check(adc, adc_ch); - } - - adc->ADC_CHDR = (adc_ch == ADC_CHANNEL_ALL) ? - ADC_CHANNEL_ALL : 1 << adc_ch; -} - -/** - * \brief Get the ADC channel status. - * - * \param adc Base address of the ADC. - * \param adc_ch Adc channel number. - * - * \retval 1 if channel is enabled. - * \retval 0 if channel is disabled. - */ -static inline uint32_t adc_channel_get_status(Adc *const adc, - const enum adc_channel_num adc_ch) -{ - adc_ch_sanity_check(adc, adc_ch); - - return adc->ADC_CHSR & (1 << adc_ch); -} - -/** - * \brief Read the Converted Data of the selected channel. - * - * \param adc Base address of the ADC. - * \param adc_ch Adc channel number. - * - * \return ADC converted value of the selected channel. - */ -static inline uint32_t adc_channel_get_value(Adc *const adc, - enum adc_channel_num adc_ch) -{ - adc_ch_sanity_check(adc, adc_ch); - - return adc->ADC_CDR[adc_ch]; -} - -/** - * \brief Get the Last Data Converted. - * - * \param adc Base address of the ADC. - * - * \return ADC latest converted value. - */ -static inline uint32_t adc_get_latest_value(Adc *const adc) -{ - return adc->ADC_LCDR & ADC_LCDR_LDATA_Msk; -} - -/** - * \brief Get the Last Converted Channel Number. - * - * \param adc Base address of the ADC. - * - * \return ADC Last Converted Channel Number. - */ -static inline uint32_t adc_get_latest_chan_num(Adc *const adc) -{ -#if SAMG55 - return (adc->ADC_LCDR & ADC_LCDR_CHNBOSR_Msk) >> ADC_LCDR_CHNBOSR_Pos; -#else - return (adc->ADC_LCDR & ADC_LCDR_CHNB_Msk) >> ADC_LCDR_CHNB_Pos; -#endif -} - -void adc_enable_interrupt(Adc *const adc, - enum adc_interrupt_source interrupt_source); - -void adc_disable_interrupt(Adc *const adc, - enum adc_interrupt_source interrupt_source); - -/** - * \brief Get ADC interrupt status. - * - * \param adc Base address of the ADC. - * - * \return The interrupt status value. - */ -static inline uint32_t adc_get_interrupt_status(Adc *const adc) -{ - return adc->ADC_ISR; -} - -/** - * \brief Get ADC interrupt mask. - * - * \param adc Base address of the ADC. - * - * \return The interrupt mask value. - */ -static inline uint32_t adc_get_interrupt_mask(Adc *const adc) -{ - return adc->ADC_IMR; -} - -/** - * \brief Get PDC registers base address. - * - * \param adc Base address of the ADC. - * - * \return Adc Pdc register base address. - */ -static inline Pdc *adc_get_pdc_base(Adc *const adc) -{ - Pdc *p_pdc_base = NULL; - - if (adc == ADC) { - p_pdc_base = PDC_ADC; - } - - return p_pdc_base; -} - -/** - * \brief Launch an automatic calibration of the ADC on next sequence. - * - * \param adc Base address of the ADC. - * - * \retval STATUS_OK An automatic calibration is launched. - * \retval STATUS_ERR_BUSY Automatic calibration can not be launched because - * the ADC is in freerun mode. - */ -static inline enum status_code adc_start_calibration(Adc *const adc) -{ - if ((adc->ADC_MR & ADC_MR_FREERUN) == ADC_MR_FREERUN_ON) { - return STATUS_ERR_BUSY; - } - - adc->ADC_CR = ADC_CR_AUTOCAL; - return STATUS_OK; -} - -#if (SAM4N) -/** - * \brief ADC Reference Voltage Selection - * - * \param adc Base address of the ADC. - * \param adc_ref_src The source selection for ADC reference voltage, - * ADC_REFER_VOL_EXTERNAL - the external pin ADVREF defines the voltage reference. - * ADC_REFER_VOL_STUCK_AT_MIN - the internal reference voltage is stuck at the minimum value - * ADC_REFER_VOL_VDDANA - the internal voltage reference is forced to VDDANA. Effective only if ONREF is 1. - * ADC_REFER_VOL_IRVS - the internal reference voltage is defined by field IRVS - * See the product electrical characteristics for further details. - * \param irvs Internal reference volatage selection, only be effective when - * adc_ref_src equals to ADC_REFER_VOL_IRVS - */ -static inline void adc_ref_vol_sel(Adc *const adc, - enum adc_refer_voltage_source adc_ref_src, - uint8_t irvs) -{ - if (ADC_REFER_VOL_EXTERNAL == adc_ref_src) { - adc->ADC_ACR &= ~ADC_ACR_ONREF_EN; - } else if (ADC_REFER_VOL_STUCK_AT_MIN == adc_ref_src) { - adc->ADC_ACR |= ADC_ACR_ONREF_EN; - adc->ADC_ACR &= ~(ADC_ACR_IRVCE_EN | ADC_ACR_FORCEREF_EN); - } else if (ADC_REFER_VOL_VDDANA == adc_ref_src) { - adc->ADC_ACR |= ADC_ACR_ONREF_EN | ADC_ACR_FORCEREF_EN; - } else if (ADC_REFER_VOL_IRVS == adc_ref_src) { - adc->ADC_ACR &= ~ADC_ACR_FORCEREF_EN; - adc->ADC_ACR |= ADC_ACR_ONREF_EN | ADC_ACR_IRVCE_EN | - (irvs << ADC_ACR_IRVS_Pos); - } -} -#endif - -/** - * \page sam_adc2_quickstart Quickstart guide for ADC driver - * - * This is the quickstart guide for the \ref sam_drivers_adc2_group - * "ADC2 driver" with step-by-step instructions on how to configure and use - * the driver in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section adc_basic_use_case Basic use case - * In this basic use case, the ADC module and single channel are configured for: - * - 10 -bit resolution - * - ADC clock frequency is 6MHz - * - Start Up Time is 64 periods ADC clock - * - Tracking Time is 3 periods of ADC clock - * - Transfer Period field shall be programmed with 2 as datasheet said - * - The controller converts channels in a simple numeric order - * - Appends the channel number to the conversion result in AFE_LDCR register - * - Single Trigger is optional to get an averaged value - * - Software triggering of conversions - * - Single channel measurement - * - ADC_CHANNEL_1 of ADC as input - * - * \subsection sam_adc2_quickstart_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (Sysclock)" - * - * \section adc_basic_use_case_setup Setup steps - * \subsection adc_basic_use_case_setup_code Example code - * Add to application C-file: - * \code - adc_enable(); - adc_get_config_defaults(&adc_cfg); - adc_init(ADC, &adc_cfg); - adc_set_trigger(ADC, ADC_TRIG_SW); - adc_channel_enable(ADC, ADC_CHANNEL_1); -\endcode - * - * \subsection adc_basic_use_case_setup_flow Workflow - * -# Enable ADC Module: - * - \code adc_enable(); \endcode - * -# Get the ADC default configurations: - * - \code adc_get_config_defaults(&adc_cfg); \endcode - * -# Initialize the ADC Module: - * - \code adc_init(ADC, &adc_cfg); \endcode - * -# Configure conversion trigger and free run mode: - * - \code adc_set_trigger(ADC, ADC_TRIG_SW); \endcode - * -# Enable Channel: - * - \code adc_channel_enable(ADC, ADC_CHANNEL_1); \endcode - * - * \section adc_basic_use_case_usage Usage steps - * \subsection adc_basic_use_case_usage_code Example code - * Add to, e.g., main loop in application C-file: - * \code - adc_start_software_conversion(ADC); - while (adc_get_interrupt_status(ADC) & (1 << ADC_CHANNEL_1)); - uint32_t result = adc_channel_get_value(ADC, ADC_CHANNEL_1); -\endcode - * - * \subsection adc_basic_use_case_usage_flow Workflow - * -# Start ADC conversion on channel: - * - \code adc_start_software_conversion(ADC); \endcode - * -# Wait for the conversion over: - * - \code while (adc_get_interrupt_status(ADC) & (1 << ADC_CHANNEL_1)); -\endcode - * -# Get the conversion result: - * - \code uint32_t result = adc_channel_get_value(ADC, ADC_CHANNEL_1); -\endcode - */ -#endif /* ADC2_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.c deleted file mode 100644 index 3398d5239c2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.c +++ /dev/null @@ -1,438 +0,0 @@ -/** - * \file - * - * \brief Enhanced Embedded Flash Controller (EEFC) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "efc.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \defgroup sam_drivers_efc_group Enhanced Embedded Flash Controller (EEFC) - * - * The Enhanced Embedded Flash Controller ensures the interface of the Flash - * block with the 32-bit internal bus. - * - * @{ - */ - - /* Address definition for read operation */ -#if (SAM3XA || SAM3U4 || SAM4SD16 || SAM4SD32) -# define READ_BUFF_ADDR0 IFLASH0_ADDR -# define READ_BUFF_ADDR1 IFLASH1_ADDR -#elif (SAM3S || SAM3N || SAM4E || SAM4N || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70) -# define READ_BUFF_ADDR IFLASH_ADDR -#elif (SAM4C || SAM4CP || SAM4CM) -#if SAM4C32 -# define READ_BUFF_ADDR0 IFLASH0_CNC_ADDR -# define READ_BUFF_ADDR1 IFLASH1_CNC_ADDR -#else -# define READ_BUFF_ADDR IFLASH_CNC_ADDR -#endif -#elif (SAM3U || SAM4S) -# define READ_BUFF_ADDR IFLASH0_ADDR -#else -# warning Only reading unique ID for sam3/4 is implemented. -#endif - - /* Flash Writing Protection Key */ -#define FWP_KEY 0x5Au - -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) -#define EEFC_FCR_FCMD(value) \ - ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) -#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR) -#elif (SAMV71 || SAMV70 || SAMS70 || SAME70) -#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR \ - | EEFC_FSR_UECCELSB | EEFC_FSR_MECCELSB | EEFC_FSR_UECCEMSB | EEFC_FSR_MECCEMSB) -#else -#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE) -#endif - -#ifndef EEFC_FCR_FKEY_PASSWD -#define EEFC_FCR_FKEY_PASSWD EEFC_FCR_FKEY(FWP_KEY) -#endif - - - /* - * Local function declaration. - * Because they are RAM functions, they need 'extern' declaration. - */ - extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr); - extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr); - - /** - * \brief Initialize the EFC controller. - * - * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. - * \param ul_fws The number of wait states in cycle (no shift). - * - * \return 0 if successful. - */ - uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws) -{ -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ - SAMV71 || SAMV70 || SAMS70 || SAME70) - efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws) | EEFC_FMR_CLOE); -#else - efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws)); -#endif - return EFC_RC_OK; -} - -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ - SAMV71 || SAMV70 || SAMS70 || SAME70) -/** - * \brief Enable code loop optimization. - * - * \param p_efc Pointer to an EFC instance. - */ -void efc_enable_cloe(Efc *p_efc) -{ - uint32_t ul_fmr = p_efc->EEFC_FMR; - efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_CLOE); -} - -/** - * \brief Disable code loop optimization. - * - * \param p_efc Pointer to an EFC instance. - */ -void efc_disable_cloe(Efc *p_efc) -{ - uint32_t ul_fmr = p_efc->EEFC_FMR; - efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_CLOE)); -} -#endif - - - -/** - * \brief Enable the flash ready interrupt. - * - * \param p_efc Pointer to an EFC instance. - */ -void efc_enable_frdy_interrupt(Efc *p_efc) -{ - uint32_t ul_fmr = p_efc->EEFC_FMR; - - efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY); -} - -/** - * \brief Disable the flash ready interrupt. - * - * \param p_efc Pointer to an EFC instance. - */ -void efc_disable_frdy_interrupt(Efc *p_efc) -{ - uint32_t ul_fmr = p_efc->EEFC_FMR; - - efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY)); -} - -#if (SAMV71 || SAMV70 || SAMS70 || SAME70) -/** - * \brief Enable the write protection. - * - * \param p_efc Pointer to an EFC instance. - */ -void efc_enable_write_protection(Efc *p_efc) -{ - p_efc->EEFC_WPMR = EEFC_WPMR_WPKEY_PASSWD | EEFC_WPMR_WPEN; -} - -/** - * \brief Disable the write protection. - * - * \param p_efc Pointer to an EFC instance. - */ -void efc_disable_write_protection(Efc *p_efc) -{ - p_efc->EEFC_WPMR = EEFC_WPMR_WPKEY_PASSWD; -} -#else -/** - * \brief Set flash access mode. - * - * \param p_efc Pointer to an EFC instance. - * \param ul_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. - */ -void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode) -{ - uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM); - - efc_write_fmr(p_efc, ul_fmr | ul_mode); -} - -/** - * \brief Get flash access mode. - * - * \param p_efc Pointer to an EFC instance. - * - * \return 0 for 128-bit or EEFC_FMR_FAM for 64-bit. - */ -uint32_t efc_get_flash_access_mode(Efc *p_efc) -{ - return (p_efc->EEFC_FMR & EEFC_FMR_FAM); -} -#endif - -/** - * \brief Set flash wait state. - * - * \param p_efc Pointer to an EFC instance. - * \param ul_fws The number of wait states in cycle (no shift). - */ -void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws) -{ - uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk); - - efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws)); -} - -/** - * \brief Get flash wait state. - * - * \param p_efc Pointer to an EFC instance. - * - * \return The number of wait states in cycle (no shift). - */ -uint32_t efc_get_wait_state(Efc *p_efc) -{ - return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos); -} - -/** - * \brief Perform the given command and wait until its completion (or an error). - * - * \note Unique ID commands are not supported, use efc_perform_read_sequence. - * - * \param p_efc Pointer to an EFC instance. - * \param ul_command Command to perform. - * \param ul_argument Optional command argument. - * - * \note This function will automatically choose to use IAP function. - * - * \return 0 if successful, otherwise returns an error code. - */ -uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, - uint32_t ul_argument) -{ - uint32_t result; - irqflags_t flags; - - /* Unique ID commands are not supported. */ - if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) { - return EFC_RC_NOT_SUPPORT; - } - - flags = cpu_irq_save(); - /* Use RAM Function. */ - result = efc_perform_fcr(p_efc, - EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) | - EEFC_FCR_FCMD(ul_command)); - cpu_irq_restore(flags); - return result; -} - -/** - * \brief Get the current status of the EEFC. - * - * \note This function clears the value of some status bits (FLOCKE, FCMDE). - * - * \param p_efc Pointer to an EFC instance. - * - * \return The current status. - */ -uint32_t efc_get_status(Efc *p_efc) -{ - return p_efc->EEFC_FSR; -} - -/** - * \brief Get the result of the last executed command. - * - * \param p_efc Pointer to an EFC instance. - * - * \return The result of the last executed command. - */ -uint32_t efc_get_result(Efc *p_efc) -{ - return p_efc->EEFC_FRR; -} - -/** - * \brief Perform read sequence. Supported sequences are read Unique ID and - * read User Signature - * - * \param p_efc Pointer to an EFC instance. - * \param ul_cmd_st Start command to perform. - * \param ul_cmd_sp Stop command to perform. - * \param p_ul_buf Pointer to an data buffer. - * \param ul_size Buffer size. - * - * \return 0 if successful, otherwise returns an error code. - */ -__no_inline -RAMFUNC -uint32_t efc_perform_read_sequence(Efc *p_efc, - uint32_t ul_cmd_st, uint32_t ul_cmd_sp, - uint32_t *p_ul_buf, uint32_t ul_size) -{ - volatile uint32_t ul_status; - uint32_t ul_cnt; - -#if (SAM3U4 || SAM3XA || SAM4SD16 || SAM4SD32 || SAM4C32) - uint32_t *p_ul_data = - (uint32_t *) ((p_efc == EFC0) ? - READ_BUFF_ADDR0 : READ_BUFF_ADDR1); -#elif (SAM3S || SAM4S || SAM3N || SAM3U || SAM4E || SAM4N || SAM4C || SAMG || \ - SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70) - uint32_t *p_ul_data = (uint32_t *) READ_BUFF_ADDR; -#else - return EFC_RC_NOT_SUPPORT; -#endif - - if (p_ul_buf == NULL) { - return EFC_RC_INVALID; - } - - p_efc->EEFC_FMR |= (0x1u << 16); - - /* Send the Start Read command */ -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ - SAMV71 || SAMV70 || SAMS70 || SAME70) - p_efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) - | EEFC_FCR_FCMD(ul_cmd_st); -#else - p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) - | EEFC_FCR_FCMD(ul_cmd_st); -#endif - /* Wait for the FRDY bit in the Flash Programming Status Register - * (EEFC_FSR) falls. - */ - do { - ul_status = p_efc->EEFC_FSR; - } while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY); - - /* The data is located in the first address of the Flash - * memory mapping. - */ - for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) { - p_ul_buf[ul_cnt] = p_ul_data[ul_cnt]; - } - - /* To stop the read mode */ - p_efc->EEFC_FCR = -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ - SAMV71 || SAMV70 || SAMS70 || SAME70) - EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) | - EEFC_FCR_FCMD(ul_cmd_sp); -#else - EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) | - EEFC_FCR_FCMD(ul_cmd_sp); -#endif - /* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR) - * rises. - */ - do { - ul_status = p_efc->EEFC_FSR; - } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); - - p_efc->EEFC_FMR &= ~(0x1u << 16); - - return EFC_RC_OK; -} - -/** - * \brief Set mode register. - * - * \param p_efc Pointer to an EFC instance. - * \param ul_fmr Value of mode register - */ -__no_inline -RAMFUNC -void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr) -{ - p_efc->EEFC_FMR = ul_fmr; -} - -/** - * \brief Perform command. - * - * \param p_efc Pointer to an EFC instance. - * \param ul_fcr Flash command. - * - * \return The current status. - */ -__no_inline -RAMFUNC -uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr) -{ - volatile uint32_t ul_status; - - p_efc->EEFC_FCR = ul_fcr; - do { - ul_status = p_efc->EEFC_FSR; - } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); - - return (ul_status & EEFC_ERROR_FLAGS); -} - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.h deleted file mode 100644 index b00854af528..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - * \file - * - * \brief Embedded Flash Controller (EFC) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef EFC_H_INCLUDED -#define EFC_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /*! \name EFC return codes */ -//! @{ -typedef enum efc_rc { - EFC_RC_OK = 0, //!< Operation OK - EFC_RC_YES = 0, //!< Yes - EFC_RC_NO = 1, //!< No - EFC_RC_ERROR = 1, //!< General error - EFC_RC_INVALID, //!< Invalid argument input - EFC_RC_NOT_SUPPORT = 0xFFFFFFFF //!< Operation is not supported -} efc_rc_t; -//! @} - -/*! \name EFC command */ -//! @{ -#define EFC_FCMD_GETD 0x00 //!< Get Flash Descriptor -#define EFC_FCMD_WP 0x01 //!< Write page -#define EFC_FCMD_WPL 0x02 //!< Write page and lock -#define EFC_FCMD_EWP 0x03 //!< Erase page and write page -#define EFC_FCMD_EWPL 0x04 //!< Erase page and write page then lock -#define EFC_FCMD_EA 0x05 //!< Erase all -#if (SAM3SD8) -#define EFC_FCMD_EPL 0x06 //!< Erase plane -#endif -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ - SAMV71 || SAMV70 || SAMS70 || SAME70) -#define EFC_FCMD_EPA 0x07 //!< Erase pages -#endif -#define EFC_FCMD_SLB 0x08 //!< Set Lock Bit -#define EFC_FCMD_CLB 0x09 //!< Clear Lock Bit -#define EFC_FCMD_GLB 0x0A //!< Get Lock Bit -#define EFC_FCMD_SGPB 0x0B //!< Set GPNVM Bit -#define EFC_FCMD_CGPB 0x0C //!< Clear GPNVM Bit -#define EFC_FCMD_GGPB 0x0D //!< Get GPNVM Bit -#define EFC_FCMD_STUI 0x0E //!< Start unique ID -#define EFC_FCMD_SPUI 0x0F //!< Stop unique ID -#if (!SAM3U && !SAM3SD8 && !SAM3S8) -#define EFC_FCMD_GCALB 0x10 //!< Get CALIB Bit -#endif -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ - SAMV71 || SAMV70 || SAMS70 || SAME70) -#define EFC_FCMD_ES 0x11 //!< Erase sector -#define EFC_FCMD_WUS 0x12 //!< Write user signature -#define EFC_FCMD_EUS 0x13 //!< Erase user signature -#define EFC_FCMD_STUS 0x14 //!< Start read user signature -#define EFC_FCMD_SPUS 0x15 //!< Stop read user signature -#endif -//! @} - -/*! The IAP function entry address */ -#define CHIP_FLASH_IAP_ADDRESS (IROM_ADDR + 8) - -/*! \name EFC access mode */ -//! @{ -#define EFC_ACCESS_MODE_128 0 -#define EFC_ACCESS_MODE_64 EEFC_FMR_FAM -//! @} - -uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws); -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ - SAMV71 || SAMV70 || SAMS70 || SAME70) -void efc_enable_cloe(Efc *p_efc); -void efc_disable_cloe(Efc *p_efc); -#endif -void efc_enable_frdy_interrupt(Efc *p_efc); -void efc_disable_frdy_interrupt(Efc *p_efc); -#if (SAMV71 || SAMV70 || SAMS70 || SAME70) -void efc_enable_write_protection(Efc *p_efc); -void efc_disable_write_protection(Efc *p_efc); -#else -void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode); -uint32_t efc_get_flash_access_mode(Efc *p_efc); -#endif -void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws); -uint32_t efc_get_wait_state(Efc *p_efc); -uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, - uint32_t ul_argument); -uint32_t efc_get_status(Efc *p_efc); -uint32_t efc_get_result(Efc *p_efc); -uint32_t efc_perform_read_sequence(Efc *p_efc, - uint32_t ul_cmd_st, uint32_t ul_cmd_sp, - uint32_t *p_ul_buf, uint32_t ul_size); - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* EFC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/flexcom/flexcom.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/flexcom/flexcom.c deleted file mode 100644 index 9b19176cf16..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/flexcom/flexcom.c +++ /dev/null @@ -1,273 +0,0 @@ -/** - * \file - * - * \brief FLEXCOM driver for SAM. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "flexcom.h" -#include "sysclk.h" -#include "sleepmgr.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - - /** - * \brief Enable the FLEXCOM module. - * - * \param p_flexcom Pointer to a FLEXCOM instance. - * - */ - void flexcom_enable(Flexcom *p_flexcom) -{ - sleepmgr_lock_mode(SLEEPMGR_ACTIVE); - /* Enable PMC clock for FLEXCOM */ -#ifdef ID_FLEXCOM7 - if (p_flexcom == FLEXCOM7) { - sysclk_enable_peripheral_clock(ID_FLEXCOM7); - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_7); - pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_7); - } else -#endif -#ifdef ID_FLEXCOM6 - if (p_flexcom == FLEXCOM6) { - sysclk_enable_peripheral_clock(ID_FLEXCOM6); - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_7); - pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_7); - } else -#endif -#ifdef ID_FLEXCOM5 - if (p_flexcom == FLEXCOM5) { - sysclk_enable_peripheral_clock(ID_FLEXCOM5); - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_7); - pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_7); - } else -#endif -#ifdef ID_FLEXCOM4 - if (p_flexcom == FLEXCOM4) { - sysclk_enable_peripheral_clock(ID_FLEXCOM4); - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_7); - pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_7); - } else -#endif -#ifdef ID_FLEXCOM3 - if (p_flexcom == FLEXCOM3) { - sysclk_enable_peripheral_clock(ID_FLEXCOM3); - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_6); - pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_6); - } else -#endif -#ifdef ID_FLEXCOM2 - if (p_flexcom == FLEXCOM2) { - sysclk_enable_peripheral_clock(ID_FLEXCOM2); - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_6); - pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_6); - } else -#endif -#ifdef ID_FLEXCOM1 - if (p_flexcom == FLEXCOM1) { - sysclk_enable_peripheral_clock(ID_FLEXCOM1); - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_6); - pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_6); - } else -#endif -#ifdef ID_FLEXCOM0 - if (p_flexcom == FLEXCOM0) { - sysclk_enable_peripheral_clock(ID_FLEXCOM0); - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_6); - pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_6); - } else -#endif - { - Assert(false); - } -} - -/** - * \brief Disable the FLEXCOM module. - * - * \param p_flexcom Pointer to a FLEXCOM instance. - * - */ -void flexcom_disable(Flexcom *p_flexcom) -{ - sleepmgr_unlock_mode(SLEEPMGR_ACTIVE); - /* Enable PMC clock for FLEXCOM */ -#ifdef ID_FLEXCOM7 - if (p_flexcom == FLEXCOM7) { - sysclk_disable_peripheral_clock(ID_FLEXCOM7); - /* Disable PCK output */ - pmc_disable_pck(PMC_PCK_7); - } else -#endif -#ifdef ID_FLEXCOM6 - if (p_flexcom == FLEXCOM6) { - sysclk_disable_peripheral_clock(ID_FLEXCOM6); - /* Disable PCK output */ - pmc_disable_pck(PMC_PCK_7); - } else -#endif -#ifdef ID_FLEXCOM5 - if (p_flexcom == FLEXCOM5) { - sysclk_disable_peripheral_clock(ID_FLEXCOM5); - /* Disable PCK output */ - pmc_disable_pck(PMC_PCK_7); - } else -#endif -#ifdef ID_FLEXCOM4 - if (p_flexcom == FLEXCOM4) { - sysclk_disable_peripheral_clock(ID_FLEXCOM4); - /* Disable PCK output */ - pmc_disable_pck(PMC_PCK_7); - } else -#endif -#ifdef ID_FLEXCOM3 - if (p_flexcom == FLEXCOM3) { - sysclk_disable_peripheral_clock(ID_FLEXCOM3); - /* Disable PCK output */ - pmc_disable_pck(PMC_PCK_6); - } else -#endif -#ifdef ID_FLEXCOM2 - if (p_flexcom == FLEXCOM2) { - sysclk_disable_peripheral_clock(ID_FLEXCOM2); - /* Disable PCK output */ - pmc_disable_pck(PMC_PCK_6); - } else -#endif -#ifdef ID_FLEXCOM1 - if (p_flexcom == FLEXCOM1) { - sysclk_disable_peripheral_clock(ID_FLEXCOM1); - /* Disable PCK output */ - pmc_disable_pck(PMC_PCK_6); - } else -#endif -#ifdef ID_FLEXCOM0 - if (p_flexcom == FLEXCOM0) { - /* Disable PCK output */ - pmc_disable_pck(PMC_PCK_6); - sysclk_disable_peripheral_clock(ID_FLEXCOM0); - } else -#endif - { - Assert(false); - } -} - -/** - * \brief Set the FLEXCOM opration mode. - * - * \param p_flexcom Pointer to a FLEXCOM instance. - * \param opmode Opration mode. - * - */ -void flexcom_set_opmode(Flexcom *p_flexcom, enum flexcom_opmode opmode) -{ - p_flexcom->FLEXCOM_MR = opmode; -} - -/** - * \brief Set the FLEXCOM opration mode. - * - * \param p_flexcom Pointer to a FLEXCOM instance. - * \param opmode Opration mode. - * - */ -void flexcom_get_opmode(Flexcom *p_flexcom, enum flexcom_opmode *opmode) -{ - *opmode = (enum flexcom_opmode)(p_flexcom->FLEXCOM_MR & FLEXCOM_MR_OPMODE_Msk); -} - -/** - * \brief Write to the FLEXCOM. - * - * \param p_flexcom Pointer to a FLEXCOM instance. - * \param data Data to be tansfer. - * - */ -void flexcom_write(Flexcom *p_flexcom, uint32_t data) -{ - p_flexcom->FLEXCOM_THR = data; -} - -/** - * \brief Read the FLEXCOM data. - * - * \param p_flexcom Pointer to a FLEXCOM instance. - * \param data Data received. - * - */ -void flexcom_read(Flexcom *p_flexcom, uint32_t *data) -{ - *data = p_flexcom->FLEXCOM_RHR; -} - - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/flexcom/flexcom.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/flexcom/flexcom.h deleted file mode 100644 index 6c403469e21..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/flexcom/flexcom.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * \brief FLEXCOM driver for SAM. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef FLEXCOM_H_INCLUDED -#define FLEXCOM_H_INCLUDED - -#include "compiler.h" -#include "status_codes.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \defgroup sam_drivers_flexcom_group Flexible Serial Communication Controller - * (FLEXCOM) Driver. - * - * \par Purpose - * - * The Flexible Serial Communication Controller (FLEXCOM) offers several - * serial communication protocols that are managed by the three submodules - * USART, SPI, and TWI. - * @{ - */ - - /** - * FLEXCOM opration Mode - */ -enum flexcom_opmode { - FLEXCOM_NONE = FLEXCOM_MR_OPMODE_NO_COM, - FLEXCOM_USART = FLEXCOM_MR_OPMODE_USART, - FLEXCOM_SPI = FLEXCOM_MR_OPMODE_SPI, - FLEXCOM_TWI = FLEXCOM_MR_OPMODE_TWI, -}; - -void flexcom_enable(Flexcom *p_flexcom); -void flexcom_disable(Flexcom *p_flexcom); -void flexcom_set_opmode(Flexcom *p_flexcom, enum flexcom_opmode opmode); -void flexcom_get_opmode(Flexcom *p_flexcom, enum flexcom_opmode *opmode); -void flexcom_write(Flexcom *p_flexcom, uint32_t data); -void flexcom_read(Flexcom *p_flexcom, uint32_t *data); - -/** @} */ - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \page sam_flexcom_quickstart Quickstart guide for SAM FLEXCOM module - * - * This is the quickstart guide for the "SAM FLEXCOM module", with - * instructions on how to configure and use the module in a selection of use - * cases. All details related to these submodules(USART/SPI/TWI) - * are provided in independent sections. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g.the main application function. - * - * \section flexcom_use_cases FLEXCOM use cases - * - \ref flexcom_basic_use_case - * - * \section flexcom_basic_use_case Basic use case - * - * \subsection sam_flexcom_quickstart_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (Sysclock)" - * - * - * \section flexcom_basic_use_case_setup Setup steps - * \subsection flexcom_basic_use_case_setup_code Example code - * -# Enable flexcom module access: - * - \code flexcom_enable(FLEXCOM0); \endcode - * -# Set flexcom operation module: - * - \code flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART); \endcode - * - * \section flexcom_basic_use_case_usage Usage steps - * \subsection flexcom_basic_use_case_usage_flow Workflow - * -# Use write/read function to access the data - * \code - flexcom_write(FLEXCOM0, data); - flexcom_read(FLEXCOM0, &data); - \endcode - */ - -#endif /* FLEXCOM_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.c deleted file mode 100644 index 678ccd60922..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.c +++ /dev/null @@ -1,334 +0,0 @@ -/** - * \file - * - * \brief SAM4 Peripheral DMA Controller (PDC) driver. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "pdc.h" - -/// @cond -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \brief Configure PDC for data transmit. - * - * \param[out] p_pdc Device structure pointer - * \param[in] p_packet Pointer to packet information for current buffer register - * set. Use NULL to leave unaltered. - * \param[in] p_next_packet Pointer to packet information for next buffer register - * set. Use NULL to leave unaltered. - */ - void pdc_tx_init( - Pdc *p_pdc, - pdc_packet_t *p_packet, - pdc_packet_t *p_next_packet) -{ - /* Validate inputs. */ - Assert(p_pdc); - - if (p_packet) { - p_pdc->PERIPH_TPR = p_packet->ul_addr; - p_pdc->PERIPH_TCR = p_packet->ul_size; - } - if (p_next_packet) { - p_pdc->PERIPH_TNPR = p_next_packet->ul_addr; - p_pdc->PERIPH_TNCR = p_next_packet->ul_size; - } -} - -/** - * \brief Configure PDC for data receive. - * - * \param[out] p_pdc Device structure pointer - * \param[in] p_packet Pointer to packet information for current buffer register - * set. Use NULL to leave unaltered. - * \param[in] p_next_packet Pointer to packet information for next buffer register - * set. Use NULL to leave unaltered. - */ -void pdc_rx_init( - Pdc *p_pdc, - pdc_packet_t *p_packet, - pdc_packet_t *p_next_packet) -{ - /* Validate inputs. */ - Assert(p_pdc); - - if (p_packet) { - p_pdc->PERIPH_RPR = p_packet->ul_addr; - p_pdc->PERIPH_RCR = p_packet->ul_size; - } - if (p_next_packet) { - p_pdc->PERIPH_RNPR = p_next_packet->ul_addr; - p_pdc->PERIPH_RNCR = p_next_packet->ul_size; - } -} - -/** - * \brief Clear PDC buffer receive counter. - * - * \param[out] p_pdc Device structure pointer - */ -void pdc_rx_clear_cnt( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - p_pdc->PERIPH_RNCR = 0; - p_pdc->PERIPH_RCR = 0; -} - -/** - * \brief Enable PDC transfers (TX and/or RX). - * - * \note It is forbidden to set both TXTEN and RXTEN for a half duplex - * peripheral. - * - * \param[out] p_pdc Device structure pointer - * \param[in] ul_controls Transfer directions - * (bit PERIPH_PTCR_RXTEN and bit PERIPH_PTCR_TXTEN) - */ -void pdc_enable_transfer( - Pdc *p_pdc, - uint32_t ul_controls) -{ - /* Validate inputs. */ - Assert(p_pdc); - - p_pdc->PERIPH_PTCR = - ul_controls & (PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); -} - -/** - * \brief Disable PDC transfers (TX and/or RX). - * - * \param[out] p_pdc Device structure pointer - * \param[in] ul_controls Transfer directions - * (bit PERIPH_PTCR_TXTDIS, bit PERIPH_PTCR_TXTDIS) - */ -void pdc_disable_transfer( - Pdc *p_pdc, - uint32_t ul_controls) -{ - /* Validate inputs. */ - Assert(p_pdc); - - p_pdc->PERIPH_PTCR = - ul_controls & (PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); -} - -/** - * \brief Read PDC status. - * - * \param[in] p_pdc Device structure pointer - * - * \return PDC status register bit map. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
NameDescriptionBit
RXTENReceiver Transfer Enabled8
TXTENTransmitter Transfer Enabled1
- * - */ -uint32_t pdc_read_status( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_PTSR; -} - -/** - * \brief Return Receive Pointer Register (RPR) value. - * - * \param[in] p_pdc Device structure pointer - * - * \return Receive Pointer Register value. - */ -uint32_t pdc_read_rx_ptr( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_RPR; -} - -/** - * \brief Return Receive Counter Register (RCR) value. - * - * \param[in] p_pdc Device structure pointer - * - * \return Receive Counter Register value. - */ -uint32_t pdc_read_rx_counter( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_RCR; -} - -/** - * \brief Return Transmit Pointer Register (TPR) value. - * - * \param[in] p_pdc Device structure pointer - * - * \return Transmit Pointer Register value. - */ -uint32_t pdc_read_tx_ptr( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_TPR; -} - -/** - * \brief Return Transmit Counter Register (TCR) value. - * - * \param[in] p_pdc Device structure pointer - * - * \return Transmit Counter Register value. - */ -uint32_t pdc_read_tx_counter( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_TCR; -} - -/** - * \brief Return Receive Next Pointer Register (RNPR) value. - * - * \param[in] p_pdc Device structure pointer - * - * \return Receive Next Pointer Register value. - */ -uint32_t pdc_read_rx_next_ptr( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_RNPR; -} - -/** - * \brief Return Receive Next Counter Register (RNCR) value. - * - * \param[in] p_pdc Device structure pointer - * - * \return Receive Next Counter Register value. - */ -uint32_t pdc_read_rx_next_counter( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_RNCR; -} - -/** - * \brief Return Transmit Next Pointer Register (TNPR) value. - * - * \param[in] p_pdc Device structure pointer - * - * \return Transmit Next Pointer Register value. - */ -uint32_t pdc_read_tx_next_ptr( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_TNPR; -} - -/** - * \brief Return Transmit Next Counter Register (TNCR) value. - * - * \param[in] p_pdc Device structure pointer - * - * \return Transmit Next Counter Register value. - */ -uint32_t pdc_read_tx_next_counter( - Pdc *p_pdc) -{ - /* Validate inputs. */ - Assert(p_pdc); - - return p_pdc->PERIPH_TNCR; -} - -/// @cond -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.h deleted file mode 100644 index 695153d6e62..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.h +++ /dev/null @@ -1,323 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral DMA Controller (PDC) driver. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef PDC_H_INCLUDED -#define PDC_H_INCLUDED - -/** - * \defgroup asfdoc_sam_drivers_pdc_group SAM3A/3N/3S/3U/3X/4E/4N/4S/G Peripheral DMA Controller (PDC) Driver - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of the the Peripheral - * Direct Memory Access (DMA) Controller (PDC) module. - * - * The PDC transfers data between on-chip serial peripherals and the on and/or - * off-chip memories. The link between the PDC and a serial peripheral is - * operated by the AHB to ABP bridge. - * - * This module: - * - Performs transfers to/from APB communication serial peripherals - * - Supports half-duplex and full-duplex peripherals - * - * Devices from the following series can use this module: - * - Atmel | SMART SAM3A - * - Atmel | SMART SAM3N - * - Atmel | SMART SAM3S - * - Atmel | SMART SAM3U - * - Atmel | SMART SAM3X - * - Atmel | SMART SAM4E - * - Atmel | SMART SAM4N - * - Atmel | SMART SAM4S - * - Atmel | SMART SAM G - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam_drivers_pdc_prerequisites - * - \ref asfdoc_sam_drivers_pdc_module_overview - * - \ref asfdoc_sam_drivers_pdc_special_considerations - * - \ref asfdoc_sam_drivers_pdc_extra_info - * - \ref asfdoc_sam_drivers_pdc_examples - * - \ref asfdoc_sam_drivers_pdc_api_overview - * - * - * \section asfdoc_sam_drivers_pdc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam_drivers_pdc_module_overview Module Overview - * The user interface of each PDC channel is integrated into the user interface - * of the peripheral it serves. The user interface of unidirectional channels - * (receive only or transmit only), contains two 32-bit memory pointers and - * two 16-bit counters, one set (pointer, counter) for current transfer and - * one set (pointer, counter) for next transfer. The bidirectional channel - * user interface contains four 32-bit memory pointers and four 16-bit counters. - * Each set (pointer, counter) is used by current transmit, next transmit, - * current receive and next receive. Using the PDC removes processor overhead - * by reducing its intervention during the transfer. This significantly reduces - * the number of clock cycles required for a data transfer, which improves - * microcontroller performance. To launch a transfer, the peripheral triggers - * its associated PDC channels by using transmit and receive signals. - * When the programmed data is transferred, an end of transfer interrupt is - * generated by the peripheral itself. - * - * \section asfdoc_sam_drivers_pdc_special_considerations Special Considerations - * There are no special considerations for this module. - * - * - * \section asfdoc_sam_drivers_pdc_extra_info Extra Information - - * For extra information, see \ref asfdoc_sam_drivers_pdc_extra. This includes: - * - \ref asfdoc_sam_drivers_pdc_extra_acronyms - * - \ref asfdoc_sam_drivers_pdc_extra_dependencies - * - \ref asfdoc_sam_drivers_pdc_extra_errata - * - \ref asfdoc_sam_drivers_pdc_extra_history - * - * \section asfdoc_sam_drivers_pdc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam_drivers_pdc_exqsg. - * - * - * \section asfdoc_sam_drivers_pdc_api_overview API Overview - * @{ - */ - -#include - -/// @cond -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \brief PDC data packet for transfer. - */ - typedef struct pdc_packet { - /** Start address of the transfer packet data. */ - uint32_t ul_addr; - /** Transfer packet size (in units of the peripheral data width). */ - uint32_t ul_size; - } pdc_packet_t; - - void pdc_tx_init(Pdc *p_pdc, pdc_packet_t *p_packet, - pdc_packet_t *p_next_packet); - void pdc_rx_init(Pdc *p_pdc, pdc_packet_t *p_packet, - pdc_packet_t *p_next_packet); - void pdc_rx_clear_cnt(Pdc *p_pdc); - void pdc_enable_transfer(Pdc *p_pdc, uint32_t ul_controls); - void pdc_disable_transfer(Pdc *p_pdc, uint32_t ul_controls); - uint32_t pdc_read_status(Pdc *p_pdc); - uint32_t pdc_read_rx_ptr(Pdc *p_pdc); - uint32_t pdc_read_rx_counter(Pdc *p_pdc); - uint32_t pdc_read_tx_ptr(Pdc *p_pdc); - uint32_t pdc_read_tx_counter(Pdc *p_pdc); - uint32_t pdc_read_rx_next_ptr(Pdc *p_pdc); - uint32_t pdc_read_rx_next_counter(Pdc *p_pdc); - uint32_t pdc_read_tx_next_ptr(Pdc *p_pdc); - uint32_t pdc_read_tx_next_counter(Pdc *p_pdc); - -/// @cond -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -/** @} */ - -/** - * \page asfdoc_sam_drivers_pdc_extra Extra Information for Peripheral DMA Controller - * - * \section asfdoc_sam_drivers_pdc_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDefinition
AHBAdvanced High-performance Bus
AMBA Advanced Microcontroller Bus Architecture
QSGQuick Start Guide
RCRReceive Counter Register
RNCRReturn Receive Next Counter Register
RNPRReceive Next Pointer Register
RPRReceive Pointer Register
TCRTransmit Counter Register
TNCRTransmit Next Counter Register
TNPRTransmit Next Pointer Register
TPRTransmit Pointer Register
- * - * - * \section asfdoc_sam_drivers_pdc_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam_drivers_pdc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam_drivers_pdc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial document release
- * - * - * - * \page asfdoc_sam_pdc_quickstart_basic Quick Start Guide for PDC - Basic - * This is the quickstart guide for \ref asfdoc_sam_drivers_pdc_group - * with step-by-step instructions on how to configure and use the driver. - * - * - * A handler is required for the interrupt, below is a simple example: - * \snippet pdc_uart_example.c int_handler - * - * First initialise the board: - * - * \snippet pdc_uart_example.c board_setup - * - * Now setup the PDC registers: - * \snippet pdc_uart_example.c pdc_config - * - * Enable UART IRQ: - * \snippet pdc_uart_example.c uart_irq - * - * Enable UART interrupt - * \snippet pdc_uart_example.c uart_nvic_irq - * - * Once the required number of bytes have been transferred, an interrupt is - * triggered and the handler will run. The main program may execute other code - * or be busy-waiting: - * - * \snippet pdc_uart_example.c busy_waiting - * - * \page asfdoc_sam_drivers_pdc_exqsg Examples for Peripheral DMA Controller - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam_drivers_pdc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam_pdc_quickstart_basic - * - \subpage asfdoc_sam_drivers_pdc_example - * - * - * \page asfdoc_sam_drivers_pdc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42316B07/2015Updated title of application note and added list of supported devices
42316A05/2014Initial document release
- * - */ - -#endif /* PDC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.c deleted file mode 100644 index 0847a481553..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.c +++ /dev/null @@ -1,1460 +0,0 @@ -/** - * \file - * - * \brief Parallel Input/Output (PIO) Controller driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "pio.h" - -#ifndef PIO_WPMR_WPKEY_PASSWD -# define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494Fu) -#endif - -/** - * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller - * - * \par Purpose - * - * The Parallel Input/Output Controller (PIO) manages up to 32 fully - * programmable input/output lines. Each I/O line may be dedicated as a - * general-purpose I/O or be assigned to a function of an embedded peripheral. - * This assures effective optimization of the pins of a product. - * - * @{ - */ - -#ifndef FREQ_SLOW_CLOCK_EXT -/* External slow clock frequency (hz) */ -#define FREQ_SLOW_CLOCK_EXT 32768 -#endif - -/** - * \brief Configure PIO internal pull-up. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be - * configured. - */ -void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_pull_up_enable) -{ - /* Enable the pull-up(s) if necessary */ - if (ul_pull_up_enable) { - p_pio->PIO_PUER = ul_mask; - } else { - p_pio->PIO_PUDR = ul_mask; - } -} - -/** - * \brief Configure Glitch or Debouncing filter for the specified input(s). - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - * \param ul_cut_off Cuts off frequency for debouncing filter. - */ -void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_cut_off) -{ -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - /* Set Debouncing, 0 bit field no effect */ - p_pio->PIO_IFSCER = ul_mask; -#elif (SAM3XA || SAM3U) - /* Set Debouncing, 0 bit field no effect */ - p_pio->PIO_DIFSR = ul_mask; -#else -#error "Unsupported device" -#endif - - /* - * The debouncing filter can filter a pulse of less than 1/2 Period of a - * programmable Divided Slow Clock: - * Tdiv_slclk = ((DIV+1)*2).Tslow_clock - */ - p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT / - (2 * (ul_cut_off))) - 1); -} - -/** - * \brief Set a high output level on all the PIOs defined in ul_mask. - * This has no immediate effects on PIOs that are not output, but the PIO - * controller will save the value if they are changed to outputs. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - */ -void pio_set(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_SODR = ul_mask; -} - -/** - * \brief Set a low output level on all the PIOs defined in ul_mask. - * This has no immediate effects on PIOs that are not output, but the PIO - * controller will save the value if they are changed to outputs. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - */ -void pio_clear(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_CODR = ul_mask; -} - -/** - * \brief Return 1 if one or more PIOs of the given Pin instance currently have - * a high level; otherwise returns 0. This method returns the actual value that - * is being read on the pin. To return the supposed output value of a pin, use - * pio_get_output_data_status() instead. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_type PIO type. - * \param ul_mask Bitmask of one or more pin(s) to configure. - * - * \retval 1 at least one PIO currently has a high level. - * \retval 0 all PIOs have a low level. - */ -uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, - const uint32_t ul_mask) -{ - uint32_t ul_reg; - - if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) { - ul_reg = p_pio->PIO_ODSR; - } else { - ul_reg = p_pio->PIO_PDSR; - } - - if ((ul_reg & ul_mask) == 0) { - return 0; - } else { - return 1; - } -} - -/** - * \brief Configure IO of a PIO controller as being controlled by a specific - * peripheral. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_type PIO type. - * \param ul_mask Bitmask of one or more pin(s) to configure. - */ -void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, - const uint32_t ul_mask) -{ - uint32_t ul_sr; - - /* Disable interrupts on the pin(s) */ - p_pio->PIO_IDR = ul_mask; - -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - switch (ul_type) { - case PIO_PERIPH_A: - ul_sr = p_pio->PIO_ABCDSR[0]; - p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); - - ul_sr = p_pio->PIO_ABCDSR[1]; - p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); - break; - case PIO_PERIPH_B: - ul_sr = p_pio->PIO_ABCDSR[0]; - p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); - - ul_sr = p_pio->PIO_ABCDSR[1]; - p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); - break; -#if (!SAMG) - case PIO_PERIPH_C: - ul_sr = p_pio->PIO_ABCDSR[0]; - p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); - - ul_sr = p_pio->PIO_ABCDSR[1]; - p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); - break; - case PIO_PERIPH_D: - ul_sr = p_pio->PIO_ABCDSR[0]; - p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); - - ul_sr = p_pio->PIO_ABCDSR[1]; - p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); - break; -#endif - /* Other types are invalid in this function */ - case PIO_INPUT: - case PIO_OUTPUT_0: - case PIO_OUTPUT_1: - case PIO_NOT_A_PIN: - return; - } -#elif (SAM3XA|| SAM3U) - switch (ul_type) { - case PIO_PERIPH_A: - ul_sr = p_pio->PIO_ABSR; - p_pio->PIO_ABSR &= (~ul_mask & ul_sr); - break; - - case PIO_PERIPH_B: - ul_sr = p_pio->PIO_ABSR; - p_pio->PIO_ABSR = (ul_mask | ul_sr); - break; - - // other types are invalid in this function - case PIO_INPUT: - case PIO_OUTPUT_0: - case PIO_OUTPUT_1: - case PIO_NOT_A_PIN: - return; - } -#else -#error "Unsupported device" -#endif - - /* Remove the pins from under the control of PIO */ - p_pio->PIO_PDR = ul_mask; -} - -/** - * \brief Configure one or more pin(s) or a PIO controller as inputs. - * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can - * be enabled. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask indicating which pin(s) to configure as input(s). - * \param ul_attribute PIO attribute(s). - */ -void pio_set_input(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_attribute) -{ - pio_disable_interrupt(p_pio, ul_mask); - pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP); - - /* Enable Input Filter if necessary */ - if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) { - p_pio->PIO_IFER = ul_mask; - } else { - p_pio->PIO_IFDR = ul_mask; - } - -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - /* Enable de-glitch or de-bounce if necessary */ - if (ul_attribute & PIO_DEGLITCH) { - p_pio->PIO_IFSCDR = ul_mask; - } else { - if (ul_attribute & PIO_DEBOUNCE) { - p_pio->PIO_IFSCER = ul_mask; - } - } -#elif (SAM3XA|| SAM3U) - /* Enable de-glitch or de-bounce if necessary */ - if (ul_attribute & PIO_DEGLITCH) { - p_pio->PIO_SCIFSR = ul_mask; - } else { - if (ul_attribute & PIO_DEBOUNCE) { - p_pio->PIO_DIFSR = ul_mask; - } - } -#else -#error "Unsupported device" -#endif - - /* Configure pin as input */ - p_pio->PIO_ODR = ul_mask; - p_pio->PIO_PER = ul_mask; -} - -/** - * \brief Configure one or more pin(s) of a PIO controller as outputs, with - * the given default value. Optionally, the multi-drive feature can be enabled - * on the pin(s). - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask indicating which pin(s) to configure. - * \param ul_default_level Default level on the pin(s). - * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as - * open-drain. - * \param ul_pull_up_enable Indicates if the pin shall have its pull-up - * activated. - */ -void pio_set_output(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_default_level, - const uint32_t ul_multidrive_enable, - const uint32_t ul_pull_up_enable) -{ - pio_disable_interrupt(p_pio, ul_mask); - pio_pull_up(p_pio, ul_mask, ul_pull_up_enable); - - /* Enable multi-drive if necessary */ - if (ul_multidrive_enable) { - p_pio->PIO_MDER = ul_mask; - } else { - p_pio->PIO_MDDR = ul_mask; - } - - /* Set default value */ - if (ul_default_level) { - p_pio->PIO_SODR = ul_mask; - } else { - p_pio->PIO_CODR = ul_mask; - } - - /* Configure pin(s) as output(s) */ - p_pio->PIO_OER = ul_mask; - p_pio->PIO_PER = ul_mask; -} - -/** - * \brief Perform complete pin(s) configuration; general attributes and PIO init - * if necessary. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_type PIO type. - * \param ul_mask Bitmask of one or more pin(s) to configure. - * \param ul_attribute Pins attributes. - * - * \return Whether the pin(s) have been configured properly. - */ -uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, - const uint32_t ul_mask, const uint32_t ul_attribute) -{ - /* Configure pins */ - switch (ul_type) { - case PIO_PERIPH_A: - case PIO_PERIPH_B: -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - case PIO_PERIPH_C: - case PIO_PERIPH_D: -#endif - pio_set_peripheral(p_pio, ul_type, ul_mask); - pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP)); - break; - - case PIO_INPUT: - pio_set_input(p_pio, ul_mask, ul_attribute); - break; - - case PIO_OUTPUT_0: - case PIO_OUTPUT_1: - pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1), - (ul_attribute & PIO_OPENDRAIN) ? 1 : 0, - (ul_attribute & PIO_PULLUP) ? 1 : 0); - break; - - default: - return 0; - } - - return 1; -} - -/** - * \brief Return 1 if one or more PIOs of the given Pin are configured to - * output a high level (even if they are not output). - * To get the actual value of the pin, use PIO_Get() instead. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s). - * - * \retval 1 At least one PIO is configured to output a high level. - * \retval 0 All PIOs are configured to output a low level. - */ -uint32_t pio_get_output_data_status(const Pio *p_pio, - const uint32_t ul_mask) -{ - if ((p_pio->PIO_ODSR & ul_mask) == 0) { - return 0; - } else { - return 1; - } -} - -/** - * \brief Configure PIO pin multi-driver. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be - * configured. - */ -void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_multi_driver_enable) -{ - /* Enable the multi-driver if necessary */ - if (ul_multi_driver_enable) { - p_pio->PIO_MDER = ul_mask; - } else { - p_pio->PIO_MDDR = ul_mask; - } -} - -/** - * \brief Get multi-driver status. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The multi-driver mask value. - */ -uint32_t pio_get_multi_driver_status(const Pio *p_pio) -{ - return p_pio->PIO_MDSR; -} - - -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Configure PIO pin internal pull-down. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall - * be configured. - */ -void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_pull_down_enable) -{ - /* Enable the pull-down if necessary */ - if (ul_pull_down_enable) { - p_pio->PIO_PPDER = ul_mask; - } else { - p_pio->PIO_PPDDR = ul_mask; - } -} -#endif - -/** - * \brief Enable PIO output write for synchronous data output. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - */ -void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_OWER = ul_mask; -} - -/** - * \brief Disable PIO output write. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - */ -void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_OWDR = ul_mask; -} - -/** - * \brief Read PIO output write status. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The output write mask value. - */ -uint32_t pio_get_output_write_status(const Pio *p_pio) -{ - return p_pio->PIO_OWSR; -} - -/** - * \brief Synchronously write on output pins. - * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are - * written. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - */ -void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_ODSR = ul_mask; -} - -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is - * active. - * Disabling the Schmitt Trigger is requested when using the QTouch Library. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - */ -void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_SCHMITT = ul_mask; -} - -/** - * \brief Get PIO pin schmitt trigger status. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The schmitt trigger mask value. - */ -uint32_t pio_get_schmitt_trigger(const Pio *p_pio) -{ - return p_pio->PIO_SCHMITT; -} -#endif - -/** - * \brief Configure the given interrupt source. - * Interrupt can be configured to trigger on rising edge, falling edge, - * high level, low level or simply on level change. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Interrupt source bit map. - * \param ul_attr Interrupt source attributes. - */ -void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_attr) -{ - /* Configure additional interrupt mode registers. */ - if (ul_attr & PIO_IT_AIME) { - /* Enable additional interrupt mode. */ - p_pio->PIO_AIMER = ul_mask; - - /* If bit field of the selected pin is 1, set as - Rising Edge/High level detection event. */ - if (ul_attr & PIO_IT_RE_OR_HL) { - /* Rising Edge or High Level */ - p_pio->PIO_REHLSR = ul_mask; - } else { - /* Falling Edge or Low Level */ - p_pio->PIO_FELLSR = ul_mask; - } - - /* If bit field of the selected pin is 1, set as - edge detection source. */ - if (ul_attr & PIO_IT_EDGE) { - /* Edge select */ - p_pio->PIO_ESR = ul_mask; - } else { - /* Level select */ - p_pio->PIO_LSR = ul_mask; - } - } else { - /* Disable additional interrupt mode. */ - p_pio->PIO_AIMDR = ul_mask; - } -} - -/** - * \brief Enable the given interrupt source. - * The PIO must be configured as an NVIC interrupt source as well. - * The status register of the corresponding PIO controller is cleared - * prior to enabling the interrupt. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Interrupt sources bit map. - */ -void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_ISR; - p_pio->PIO_IER = ul_mask; -} - -/** - * \brief Disable a given interrupt source, with no added side effects. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Interrupt sources bit map. - */ -void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_IDR = ul_mask; -} - -/** - * \brief Read PIO interrupt status. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The interrupt status mask value. - */ -uint32_t pio_get_interrupt_status(const Pio *p_pio) -{ - return p_pio->PIO_ISR; -} - -/** - * \brief Read PIO interrupt mask. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The interrupt mask value. - */ -uint32_t pio_get_interrupt_mask(const Pio *p_pio) -{ - return p_pio->PIO_IMR; -} - -/** - * \brief Set additional interrupt mode. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Interrupt sources bit map. - * \param ul_attribute Pin(s) attributes. - */ -void pio_set_additional_interrupt_mode(Pio *p_pio, - const uint32_t ul_mask, const uint32_t ul_attribute) -{ - /* Enables additional interrupt mode if needed */ - if (ul_attribute & PIO_IT_AIME) { - /* Enables additional interrupt mode */ - p_pio->PIO_AIMER = ul_mask; - - /* Configures the Polarity of the event detection */ - /* (Rising/Falling Edge or High/Low Level) */ - if (ul_attribute & PIO_IT_RE_OR_HL) { - /* Rising Edge or High Level */ - p_pio->PIO_REHLSR = ul_mask; - } else { - /* Falling Edge or Low Level */ - p_pio->PIO_FELLSR = ul_mask; - } - - /* Configures the type of event detection (Edge or Level) */ - if (ul_attribute & PIO_IT_EDGE) { - /* Edge select */ - p_pio->PIO_ESR = ul_mask; - } else { - /* Level select */ - p_pio->PIO_LSR = ul_mask; - } - } else { - /* Disable additional interrupt mode */ - p_pio->PIO_AIMDR = ul_mask; - } -} - -#ifndef PIO_WPMR_WPKEY_PASSWD -#define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494FU) -#endif - -/** - * \brief Enable or disable write protect of PIO registers. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_enable 1 to enable, 0 to disable. - */ -void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable) -{ - p_pio->PIO_WPMR = PIO_WPMR_WPKEY_PASSWD | (ul_enable & PIO_WPMR_WPEN); -} - -/** - * \brief Read write protect status. - * - * \param p_pio Pointer to a PIO instance. - * - * \return Return write protect status. - */ -uint32_t pio_get_writeprotect_status(const Pio *p_pio) -{ - return p_pio->PIO_WPSR; -} - -/** - * \brief Return the value of a pin. - * - * \param ul_pin The pin number. - * - * \return The pin value. - * - * \note If pin is output: a pull-up or pull-down could hide the actual value. - * The function \ref pio_get can be called to get the actual pin output - * level. - * \note If pin is input: PIOx must be clocked to sample the signal. - * See PMC driver. - */ -uint32_t pio_get_pin_value(uint32_t ul_pin) -{ - Pio *p_pio = pio_get_pin_group(ul_pin); - - return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1; -} - -/** - * \brief Drive a GPIO pin to 1. - * - * \param ul_pin The pin index. - * - * \note The function \ref pio_configure_pin must be called beforehand. - */ -void pio_set_pin_high(uint32_t ul_pin) -{ - Pio *p_pio = pio_get_pin_group(ul_pin); - - /* Value to be driven on the I/O line: 1. */ - p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); -} - -/** - * \brief Drive a GPIO pin to 0. - * - * \param ul_pin The pin index. - * - * \note The function \ref pio_configure_pin must be called before. - */ -void pio_set_pin_low(uint32_t ul_pin) -{ - Pio *p_pio = pio_get_pin_group(ul_pin); - - /* Value to be driven on the I/O line: 0. */ - p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); -} - -/** - * \brief Toggle a GPIO pin. - * - * \param ul_pin The pin index. - * - * \note The function \ref pio_configure_pin must be called before. - */ -void pio_toggle_pin(uint32_t ul_pin) -{ - Pio *p_pio = pio_get_pin_group(ul_pin); - - if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) { - /* Value to be driven on the I/O line: 0. */ - p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); - } else { - /* Value to be driven on the I/O line: 1. */ - p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); - } -} - -/** - * \brief Perform complete pin(s) configuration; general attributes and PIO init - * if necessary. - * - * \param ul_pin Bitmask of one or more pin(s) to configure. - * \param ul_flags Pins attributes. - * - * \return Whether the pin(s) have been configured properly. - */ -uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags) -{ - Pio *p_pio = pio_get_pin_group(ul_pin); - - /* Configure pins */ - switch (ul_flags & PIO_TYPE_Msk) { - case PIO_TYPE_PIO_PERIPH_A: - pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F))); - pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), - (ul_flags & PIO_PULLUP)); - break; - case PIO_TYPE_PIO_PERIPH_B: - pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F))); - pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), - (ul_flags & PIO_PULLUP)); - break; -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - case PIO_TYPE_PIO_PERIPH_C: - pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F))); - pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), - (ul_flags & PIO_PULLUP)); - break; - case PIO_TYPE_PIO_PERIPH_D: - pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F))); - pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), - (ul_flags & PIO_PULLUP)); - break; -#endif - - case PIO_TYPE_PIO_INPUT: - pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags); - break; - - case PIO_TYPE_PIO_OUTPUT_0: - case PIO_TYPE_PIO_OUTPUT_1: - pio_set_output(p_pio, (1 << (ul_pin & 0x1F)), - ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) - == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, - (ul_flags & PIO_OPENDRAIN) ? 1 : 0, - (ul_flags & PIO_PULLUP) ? 1 : 0); - break; - - default: - return 0; - } - - return 1; -} - -/** - * \brief Drive a GPIO port to 1. - * - * \param p_pio Base address of the PIO port. - * \param ul_mask Bitmask of one or more pin(s) to toggle. - */ -void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask) -{ - /* Value to be driven on the I/O line: 1. */ - p_pio->PIO_SODR = ul_mask; -} - -/** - * \brief Drive a GPIO port to 0. - * - * \param p_pio Base address of the PIO port. - * \param ul_mask Bitmask of one or more pin(s) to toggle. - */ -void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask) -{ - /* Value to be driven on the I/O line: 0. */ - p_pio->PIO_CODR = ul_mask; -} - -/** - * \brief Toggle a GPIO group. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - */ -void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask) -{ - if (p_pio->PIO_ODSR & ul_mask) { - /* Value to be driven on the I/O line: 0. */ - p_pio->PIO_CODR = ul_mask; - } else { - /* Value to be driven on the I/O line: 1. */ - p_pio->PIO_SODR = ul_mask; - } -} - -/** - * \brief Perform complete pin(s) configuration; general attributes and PIO init - * if necessary. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Bitmask of one or more pin(s) to configure. - * \param ul_flags Pin(s) attributes. - * - * \return Whether the pin(s) have been configured properly. - */ -uint32_t pio_configure_pin_group(Pio *p_pio, - uint32_t ul_mask, const uint32_t ul_flags) -{ - /* Configure pins */ - switch (ul_flags & PIO_TYPE_Msk) { - case PIO_TYPE_PIO_PERIPH_A: - pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask); - pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); - break; - case PIO_TYPE_PIO_PERIPH_B: - pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask); - pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); - break; -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - case PIO_TYPE_PIO_PERIPH_C: - pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask); - pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); - break; - case PIO_TYPE_PIO_PERIPH_D: - pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask); - pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); - break; -#endif - - case PIO_TYPE_PIO_INPUT: - pio_set_input(p_pio, ul_mask, ul_flags); - break; - - case PIO_TYPE_PIO_OUTPUT_0: - case PIO_TYPE_PIO_OUTPUT_1: - pio_set_output(p_pio, ul_mask, - ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) - == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, - (ul_flags & PIO_OPENDRAIN) ? 1 : 0, - (ul_flags & PIO_PULLUP) ? 1 : 0); - break; - - default: - return 0; - } - - return 1; -} - -/** - * \brief Enable interrupt for a GPIO pin. - * - * \param ul_pin The pin index. - * - * \note The function \ref gpio_configure_pin must be called before. - */ -void pio_enable_pin_interrupt(uint32_t ul_pin) -{ - Pio *p_pio = pio_get_pin_group(ul_pin); - - p_pio->PIO_IER = 1 << (ul_pin & 0x1F); -} - - -/** - * \brief Disable interrupt for a GPIO pin. - * - * \param ul_pin The pin index. - * - * \note The function \ref gpio_configure_pin must be called before. - */ -void pio_disable_pin_interrupt(uint32_t ul_pin) -{ - Pio *p_pio = pio_get_pin_group(ul_pin); - - p_pio->PIO_IDR = 1 << (ul_pin & 0x1F); -} - - -/** - * \brief Return GPIO port for a GPIO pin. - * - * \param ul_pin The pin index. - * - * \return Pointer to \ref Pio struct for GPIO port. - */ -Pio *pio_get_pin_group(uint32_t ul_pin) -{ - Pio *p_pio; - -#if (SAM4C || SAM4CP) -# ifdef ID_PIOD - if (ul_pin > PIO_PC9_IDX) { - p_pio = PIOD; - } else if (ul_pin > PIO_PB31_IDX) { -# else - if (ul_pin > PIO_PB31_IDX) { -# endif - p_pio = PIOC; - } else { - p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); - } -#elif (SAM4CM) - if (ul_pin > PIO_PB21_IDX) { - p_pio = PIOC; - } else { - p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); - } -#else - p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); -#endif - return p_pio; -} - -/** - * \brief Return GPIO port peripheral ID for a GPIO pin. - * - * \param ul_pin The pin index. - * - * \return GPIO port peripheral ID. - */ -uint32_t pio_get_pin_group_id(uint32_t ul_pin) -{ - uint32_t ul_id; - -#if (SAM4C || SAM4CP) -# ifdef ID_PIOD - if (ul_pin > PIO_PC9_IDX) { - ul_id = ID_PIOD; - } else if (ul_pin > PIO_PB31_IDX) { -# else - if (ul_pin > PIO_PB31_IDX) { -# endif - ul_id = ID_PIOC; - } else { - ul_id = ID_PIOA + (ul_pin >> 5); - } -#elif (SAM4CM) - if (ul_pin > PIO_PB21_IDX) { - ul_id = ID_PIOC; - } else { - ul_id = ID_PIOA + (ul_pin >> 5); - } -#else - ul_id = ID_PIOA + (ul_pin >> 5); -#endif - return ul_id; -} - - -/** - * \brief Return GPIO port pin mask for a GPIO pin. - * - * \param ul_pin The pin index. - * - * \return GPIO port pin mask. - */ -uint32_t pio_get_pin_group_mask(uint32_t ul_pin) -{ - uint32_t ul_mask = 1 << (ul_pin & 0x1F); - return ul_mask; -} - -#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70) -/* Capture mode enable flag */ -uint32_t pio_capture_enable_flag; - -/** - * \brief Configure PIO capture mode. - * \note PIO capture mode will be disabled automatically. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mode Bitmask of one or more modes. - */ -void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode) -{ - ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */ - p_pio->PIO_PCMR = ul_mode; -} - -/** - * \brief Enable PIO capture mode. - * - * \param p_pio Pointer to a PIO instance. - */ -void pio_capture_enable(Pio *p_pio) -{ - p_pio->PIO_PCMR |= PIO_PCMR_PCEN; - pio_capture_enable_flag = true; -} - -/** - * \brief Disable PIO capture mode. - * - * \param p_pio Pointer to a PIO instance. - */ -void pio_capture_disable(Pio *p_pio) -{ - p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN); - pio_capture_enable_flag = false; -} - -/** - * \brief Read from Capture Reception Holding Register. - * \note Data presence should be tested before any read attempt. - * - * \param p_pio Pointer to a PIO instance. - * \param pul_data Pointer to store the data. - * - * \retval 0 Success. - * \retval 1 I/O Failure, Capture data is not ready. - */ -uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data) -{ - /* Check if the data is ready */ - if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) { - return 1; - } - - /* Read data */ - *pul_data = p_pio->PIO_PCRHR; - return 0; -} - -/** - * \brief Enable the given interrupt source of PIO capture. The status - * register of the corresponding PIO capture controller is cleared prior - * to enabling the interrupt. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Interrupt sources bit map. - */ -void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_PCISR; - p_pio->PIO_PCIER = ul_mask; -} - -/** - * \brief Disable a given interrupt source of PIO capture. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Interrupt sources bit map. - */ -void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) -{ - p_pio->PIO_PCIDR = ul_mask; -} - -/** - * \brief Read PIO interrupt status of PIO capture. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The interrupt status mask value. - */ -uint32_t pio_capture_get_interrupt_status(const Pio *p_pio) -{ - return p_pio->PIO_PCISR; -} - -/** - * \brief Read PIO interrupt mask of PIO capture. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The interrupt mask value. - */ -uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio) -{ - return p_pio->PIO_PCIMR; -} -#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Get PDC registers base address. - * - * \param p_pio Pointer to an PIO peripheral. - * - * \return PIOA PDC register base address. - */ -Pdc *pio_capture_get_pdc_base(const Pio *p_pio) -{ - UNUSED(p_pio); /* Stop warning */ - return PDC_PIOA; -} -#endif -#endif - -#if (SAM4C || SAM4CP || SAM4CM || SAMG55) -/** - * \brief Set PIO IO drive. - * - * \param p_pio Pointer to an PIO peripheral. - * \param ul_line Line index (0..31). - * \param mode IO drive mode. - */ -void pio_set_io_drive(Pio *p_pio, uint32_t ul_line, - enum pio_io_drive_mode mode) -{ - p_pio->PIO_DRIVER &= ~(1 << ul_line); - p_pio->PIO_DRIVER |= mode << ul_line; -} -#endif - -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Enable PIO keypad controller. - * - * \param p_pio Pointer to a PIO instance. - */ -void pio_keypad_enable(Pio *p_pio) -{ - p_pio->PIO_KER |= PIO_KER_KCE; -} - -/** - * \brief Disable PIO keypad controller. - * - * \param p_pio Pointer to a PIO instance. - */ -void pio_keypad_disable(Pio *p_pio) -{ - p_pio->PIO_KER &= (~PIO_KER_KCE); -} - -/** - * \brief Set PIO keypad controller row number. - * - * \param p_pio Pointer to a PIO instance. - * \param num Number of row of the keypad matrix. - */ -void pio_keypad_set_row_num(Pio *p_pio, uint8_t num) -{ - p_pio->PIO_KRCR &= (~PIO_KRCR_NBR_Msk); - p_pio->PIO_KRCR |= PIO_KRCR_NBR(num); -} - -/** - * \brief Get PIO keypad controller row number. - * - * \param p_pio Pointer to a PIO instance. - * - * \return Number of row of the keypad matrix. - */ -uint8_t pio_keypad_get_row_num(const Pio *p_pio) -{ - return ((p_pio->PIO_KRCR & PIO_KRCR_NBR_Msk) >> PIO_KRCR_NBR_Pos); -} - -/** - * \brief Set PIO keypad controller column number. - * - * \param p_pio Pointer to a PIO instance. - * \param num Number of column of the keypad matrix. - */ -void pio_keypad_set_column_num(Pio *p_pio, uint8_t num) -{ - p_pio->PIO_KRCR &= (~PIO_KRCR_NBC_Msk); - p_pio->PIO_KRCR |= PIO_KRCR_NBC(num); -} - -/** - * \brief Get PIO keypad controller column number. - * - * \param p_pio Pointer to a PIO instance. - * - * \return Number of column of the keypad matrix. - */ -uint8_t pio_keypad_get_column_num(const Pio *p_pio) -{ - return ((p_pio->PIO_KRCR & PIO_KRCR_NBC_Msk) >> PIO_KRCR_NBC_Pos); -} - -/** - * \brief Set PIO keypad matrix debouncing value. - * - * \param p_pio Pointer to a PIO instance. - * \param num Number of debouncing value. - */ -void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value) -{ - p_pio->PIO_KDR = PIO_KDR_DBC(value); -} - -/** - * \brief Get PIO keypad matrix debouncing value. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The keypad debouncing value. - */ -uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio) -{ - return ((p_pio->PIO_KDR & PIO_KDR_DBC_Msk) >> PIO_KDR_DBC_Pos); -} - -/** - * \brief Enable the interrupt source of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Interrupt sources bit map. - */ -void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask) -{ - p_pio->PIO_KIER = ul_mask; -} - -/** - * \brief Disable the interrupt source of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * \param ul_mask Interrupt sources bit map. - */ -void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask) -{ - p_pio->PIO_KIDR = ul_mask; -} - -/** - * \brief Get interrupt mask of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The interrupt mask value. - */ -uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio) -{ - return p_pio->PIO_KIMR; -} - -/** - * \brief Get key press status of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The status of key press. - * 0: No key press has been detected. - * 1: At least one key press has been detected. - */ -uint32_t pio_keypad_get_press_status(const Pio *p_pio) -{ - if (p_pio->PIO_KSR & PIO_KSR_KPR) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Get key release status of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The status of key release. - * 0 No key release has been detected. - * 1 At least one key release has been detected. - */ -uint32_t pio_keypad_get_release_status(const Pio *p_pio) -{ - if (p_pio->PIO_KSR & PIO_KSR_KRL) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Get simultaneous key press number of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The number of simultaneous key press. - */ -uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio) -{ - return ((p_pio->PIO_KSR & PIO_KSR_NBKPR_Msk) >> PIO_KSR_NBKPR_Pos); -} - -/** - * \brief Get simultaneous key release number of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * - * \return The number of simultaneous key release. - */ -uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio) -{ - return ((p_pio->PIO_KSR & PIO_KSR_NBKRL_Msk) >> PIO_KSR_NBKRL_Pos); -} - -/** - * \brief Get detected key press row index of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * \param queue The queue of key press row - * - * \return The index of detected key press row. - */ -uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue) -{ - switch (queue) { - case 0: - return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0ROW_Msk) >> PIO_KKPR_KEY0ROW_Pos); - case 1: - return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1ROW_Msk) >> PIO_KKPR_KEY1ROW_Pos); - case 2: - return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2ROW_Msk) >> PIO_KKPR_KEY2ROW_Pos); - case 3: - return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3ROW_Msk) >> PIO_KKPR_KEY3ROW_Pos); - default: - return 0; - } -} - -/** - * \brief Get detected key press column index of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * \param queue The queue of key press column - * - * \return The index of detected key press column. - */ -uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue) -{ - switch (queue) { - case 0: - return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0COL_Msk) >> PIO_KKPR_KEY0COL_Pos); - case 1: - return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1COL_Msk) >> PIO_KKPR_KEY1COL_Pos); - case 2: - return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2COL_Msk) >> PIO_KKPR_KEY2COL_Pos); - case 3: - return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3COL_Msk) >> PIO_KKPR_KEY3COL_Pos); - default: - return 0; - } -} - -/** - * \brief Get detected key release row index of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * \param queue The queue of key release row - * - * \return The index of detected key release row. - */ -uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue) -{ - switch (queue) { - case 0: - return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0ROW_Msk) >> PIO_KKRR_KEY0ROW_Pos); - case 1: - return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1ROW_Msk) >> PIO_KKRR_KEY1ROW_Pos); - case 2: - return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2ROW_Msk) >> PIO_KKRR_KEY2ROW_Pos); - case 3: - return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3ROW_Msk) >> PIO_KKRR_KEY3ROW_Pos); - default: - return 0; - } -} - -/** - * \brief Get detected key release column index of PIO keypad. - * - * \param p_pio Pointer to a PIO instance. - * \param queue The queue of key release column - * - * \return The index of detected key release column. - */ -uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue) -{ - switch (queue) { - case 0: - return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0COL_Msk) >> PIO_KKRR_KEY0COL_Pos); - case 1: - return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1COL_Msk) >> PIO_KKRR_KEY1COL_Pos); - case 2: - return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2COL_Msk) >> PIO_KKRR_KEY2COL_Pos); - case 3: - return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3COL_Msk) >> PIO_KKRR_KEY3COL_Pos); - default: - return 0; - } -} - -#endif - -//@} - diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.h deleted file mode 100644 index da135a83615..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.h +++ /dev/null @@ -1,377 +0,0 @@ -/** - * \file - * - * \brief Parallel Input/Output (PIO) Controller driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef PIO_H_INCLUDED -#define PIO_H_INCLUDED - -#include "compiler.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Compute PIO register length */ -#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA) - -/* GPIO Support */ -#define PIO_TYPE_Pos 27 -/* PIO Type Mask */ -#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos) -/* The pin is not a function pin. */ -#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos) -/* The pin is controlled by the peripheral A. */ -#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos) -/* The pin is controlled by the peripheral B. */ -#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos) -/* The pin is controlled by the peripheral C. */ -#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos) -/* The pin is controlled by the peripheral D. */ -#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos) -/* The pin is an input. */ -#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos) -/* The pin is an output and has a default level of 0. */ -#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos) -/* The pin is an output and has a default level of 1. */ -#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos) - -typedef enum _pio_type { - PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN, - PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A, - PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B, -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C, - PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D, -#endif - PIO_INPUT = PIO_TYPE_PIO_INPUT, - PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0, - PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1 -} pio_type_t; - -/* Default pin configuration (no attribute). */ -#define PIO_DEFAULT (0u << 0) -/* The internal pin pull-up is active. */ -#define PIO_PULLUP (1u << 0) -/* The internal glitch filter is active. */ -#define PIO_DEGLITCH (1u << 1) -/* The pin is open-drain. */ -#define PIO_OPENDRAIN (1u << 2) - -/* The internal debouncing filter is active. */ -#define PIO_DEBOUNCE (1u << 3) - -/* Enable additional interrupt modes. */ -#define PIO_IT_AIME (1u << 4) - -/* Interrupt High Level/Rising Edge detection is active. */ -#define PIO_IT_RE_OR_HL (1u << 5) -/* Interrupt Edge detection is active. */ -#define PIO_IT_EDGE (1u << 6) - -/* Low level interrupt is active */ -#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) -/* High level interrupt is active */ -#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) -/* Falling edge interrupt is active */ -#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) -/* Rising edge interrupt is active */ -#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) - -/* - * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT, - * or combine (using bitwise OR '|') any number of the following constants: - * - PIO_PULLUP - * - PIO_DEGLITCH - * - PIO_DEBOUNCE - * - PIO_OPENDRAIN - * - PIO_IT_LOW_LEVEL - * - PIO_IT_HIGH_LEVEL - * - PIO_IT_FALL_EDGE - * - PIO_IT_RISE_EDGE - */ -void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_pull_up_enable); -void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_cut_off); -void pio_set(Pio *p_pio, const uint32_t ul_mask); -void pio_clear(Pio *p_pio, const uint32_t ul_mask); -uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, - const uint32_t ul_mask); -void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, - const uint32_t ul_mask); -void pio_set_input(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_attribute); -void pio_set_output(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_default_level, - const uint32_t ul_multidrive_enable, - const uint32_t ul_pull_up_enable); -uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, - const uint32_t ul_mask, const uint32_t ul_attribute); -uint32_t pio_get_output_data_status(const Pio *p_pio, - const uint32_t ul_mask); -void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_multi_driver_enable); -uint32_t pio_get_multi_driver_status(const Pio *p_pio); - -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) -void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_pull_down_enable); -#endif - -void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask); -void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask); -uint32_t pio_get_output_write_status(const Pio *p_pio); -void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask); - -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) -void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask); -uint32_t pio_get_schmitt_trigger(const Pio *p_pio); -#endif - -void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, - const uint32_t ul_attr); -void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); -void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask); -uint32_t pio_get_interrupt_status(const Pio *p_pio); -uint32_t pio_get_interrupt_mask(const Pio *p_pio); -void pio_set_additional_interrupt_mode(Pio *p_pio, - const uint32_t ul_mask, const uint32_t ul_attribute); -void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable); -uint32_t pio_get_writeprotect_status(const Pio *p_pio); - -#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70) -void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode); -void pio_capture_enable(Pio *p_pio); -void pio_capture_disable(Pio *p_pio); -uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data); -void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); -void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask); -uint32_t pio_capture_get_interrupt_status(const Pio *p_pio); -uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio); -#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) -Pdc *pio_capture_get_pdc_base(const Pio *p_pio); -#endif -#endif - -/* GPIO Support */ -uint32_t pio_get_pin_value(uint32_t pin); -void pio_set_pin_high(uint32_t pin); -void pio_set_pin_low(uint32_t pin); -void pio_toggle_pin(uint32_t pin); -void pio_enable_pin_interrupt(uint32_t pin); -void pio_disable_pin_interrupt(uint32_t pin); -Pio *pio_get_pin_group(uint32_t pin); -uint32_t pio_get_pin_group_id(uint32_t pin); -uint32_t pio_get_pin_group_mask(uint32_t pin); -uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags); -void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask); -void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask); -void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask); -uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask, - const uint32_t ul_flags); - -#if (SAM4C || SAM4CP || SAM4CM || SAMG55) -enum pio_io_drive_mode { - PIO_IO_DRIVE_LOW = 0, - PIO_IO_DRIVE_HIGH, -}; -void pio_set_io_drive(Pio *p_pio, uint32_t ul_line, - enum pio_io_drive_mode mode); -#endif - -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) -void pio_keypad_enable(Pio *p_pio); -void pio_keypad_disable(Pio *p_pio); -void pio_keypad_set_row_num(Pio *p_pio, uint8_t num); -uint8_t pio_keypad_get_row_num(const Pio *p_pio); -void pio_keypad_set_column_num(Pio *p_pio, uint8_t num); -uint8_t pio_keypad_get_column_num(const Pio *p_pio); -void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value); -uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio); -void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask); -void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask); -uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio); -uint32_t pio_keypad_get_press_status(const Pio *p_pio); -uint32_t pio_keypad_get_release_status(const Pio *p_pio); -uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio); -uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio); -uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue); -uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue); -uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue); -uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue); -#endif -/** - * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver - * - * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver", - * with step-by-step instructions on how to configure and use the driver for - * specific use cases. - * - * The section described below can be compiled into e.g. the main application - * loop or any other function that will need to interface with the IO port. - * - * \section sam_pio_usecases PIO use cases - * - \ref sam_pio_quickstart_basic - * - \ref sam_pio_quickstart_use_case_2 - * - * \section sam_pio_quickstart_basic Basic usage of the PIO driver - * This section will present a basic use case for the PIO driver. This use case - * will configure pin 23 on port A as output and pin 16 as an input with pullup, - * and then toggle the output pin's value to match that of the input pin. - * - * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites - * - \ref group_pmc "Power Management Controller driver" - * - * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code - * Add to the application initialization code: - * \code - pmc_enable_periph_clk(ID_PIOA); - - pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); - pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); -\endcode - * - * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow - * -# Enable the module clock to the PIOA peripheral: - * \code pmc_enable_periph_clk(ID_PIOA); \endcode - * -# Set pin 23 direction on PIOA as output, default low level: - * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode - * -# Set pin 16 direction on PIOA as input, with pullup: - * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode - * - * \subsection sam_pio_quickstart_use_case_1_example_code Example code - * Set the state of output pin 23 to match input pin 16: - * \code - if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) - pio_clear(PIOA, PIO_PA23); - else - pio_set(PIOA, PIO_PA23); -\endcode - * - * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow - * -# We check the value of the pin: - * \code - if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) -\endcode - * -# Then we set the new output value based on the read pin value: - * \code - pio_clear(PIOA, PIO_PA23); - else - pio_set(PIOA, PIO_PA23); -\endcode - */ - -/** - * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection - * - * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1 - * This section will present a more advanced use case for the PIO driver. This use case - * will configure pin 23 on port A as output and pin 16 as an input with pullup, - * and then toggle the output pin's value to match that of the input pin using the interrupt - * controller within the device. - * - * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites - * - \ref group_pmc "Power Management Controller driver" - * - * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code - * Add to the application initialization code: - * \code - pmc_enable_periph_clk(ID_PIOA); - - pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); - pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); - - pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); - pio_enable_interrupt(PIOA, PIO_PA16); - - NVIC_EnableIRQ(PIOA_IRQn); -\endcode - * - * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow - * -# Enable the module clock to the PIOA peripheral: - * \code pmc_enable_periph_clk(ID_PIOA); \endcode - * -# Set pin 23 direction on PIOA as output, default low level: - * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode - * -# Set pin 16 direction on PIOA as input, with pullup: - * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode - * -# Configure the input pin 16 interrupt mode and handler: - * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode - * -# Enable the interrupt for the configured input pin: - * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode - * -# Enable interrupt handling from the PIOA module: - * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode - * - * \subsection sam_pio_quickstart_use_case_2_example_code Example code - * Add the following function to your application: - * \code - void pin_edge_handler(const uint32_t id, const uint32_t index) - { - if ((id == ID_PIOA) && (index == PIO_PA16)){ - if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) - pio_clear(PIOA, PIO_PA23); - else - pio_set(PIOA, PIO_PA23); - } - } -\endcode - * - * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow - * -# We check the value of the pin: - * \code - if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) -\endcode - * -# Then we set the new output value based on the read pin value: - * \code - pio_clear(PIOA, PIO_PA23); - else - pio_set(PIOA, PIO_PA23); -\endcode - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PIO_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.c deleted file mode 100644 index e9c7f1ec9b9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.c +++ /dev/null @@ -1,286 +0,0 @@ -/** - * \file - * - * \brief Parallel Input/Output (PIO) interrupt handler for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "pio.h" -#include "pio_handler.h" - -/** - * Maximum number of interrupt sources that can be defined. This - * constant can be increased, but the current value is the smallest possible one - * that will be compatible with all existing projects. - */ -#define MAX_INTERRUPT_SOURCES 7 - -/** - * Describes a PIO interrupt source, including the PIO instance triggering the - * interrupt and the associated interrupt handler. - */ -struct s_interrupt_source { - uint32_t id; - uint32_t mask; - uint32_t attr; - - /* Interrupt handler. */ - void (*handler) (const uint32_t, const uint32_t); -}; - - -/* List of interrupt sources. */ -static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES]; - -/* Number of currently defined interrupt sources. */ -static uint32_t gs_ul_nb_sources = 0; - -#if (SAM3S || SAM4S || SAM4E) -/* PIO Capture handler */ -static void (*pio_capture_handler)(Pio *) = NULL; -extern uint32_t pio_capture_enable_flag; -#endif - -/** - * \brief Process an interrupt request on the given PIO controller. - * - * \param p_pio PIO controller base address. - * \param ul_id PIO controller ID. - */ -void pio_handler_process(Pio *p_pio, uint32_t ul_id) -{ - uint32_t status; - uint32_t i; - - /* Read PIO controller status */ - status = pio_get_interrupt_status(p_pio); - status &= pio_get_interrupt_mask(p_pio); - - /* Check pending events */ - if (status != 0) { - /* Find triggering source */ - i = 0; - while (status != 0) { - /* Source is configured on the same controller */ - if (gs_interrupt_sources[i].id == ul_id) { - /* Source has PIOs whose statuses have changed */ - if ((status & gs_interrupt_sources[i].mask) != 0) { - gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, - gs_interrupt_sources[i].mask); - status &= ~(gs_interrupt_sources[i].mask); - } - } - i++; - if (i >= MAX_INTERRUPT_SOURCES) { - break; - } - } - } - - /* Check capture events */ -#if (SAM3S || SAM4S || SAM4E) - if (pio_capture_enable_flag) { - if (pio_capture_handler) { - pio_capture_handler(p_pio); - } - } -#endif -} - -/** - * \brief Set an interrupt handler for the provided pins. - * The provided handler will be called with the triggering pin as its parameter - * as soon as an interrupt is detected. - * - * \param p_pio PIO controller base address. - * \param ul_id PIO ID. - * \param ul_mask Pins (bit mask) to configure. - * \param ul_attr Pins attribute to configure. - * \param p_handler Interrupt handler function pointer. - * - * \return 0 if successful, 1 if the maximum number of sources has been defined. - */ -uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, - uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)) -{ - struct s_interrupt_source *pSource; - - if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES) - return 1; - - /* Define new source */ - pSource = &(gs_interrupt_sources[gs_ul_nb_sources]); - pSource->id = ul_id; - pSource->mask = ul_mask; - pSource->attr = ul_attr; - pSource->handler = p_handler; - gs_ul_nb_sources++; - - /* Configure interrupt mode */ - pio_configure_interrupt(p_pio, ul_mask, ul_attr); - - return 0; -} - -#if (SAM3S || SAM4S || SAM4E) -/** - * \brief Set a capture interrupt handler for all PIO. - * - * The handler will be called with the triggering PIO as its parameter - * as soon as an interrupt is detected. - * - * \param p_handler Interrupt handler function pointer. - * - */ -void pio_capture_handler_set(void (*p_handler)(Pio *)) -{ - pio_capture_handler = p_handler; -} -#endif - -#ifdef ID_PIOA -/** - * \brief Set an interrupt handler for the specified pin. - * The provided handler will be called with the triggering pin as its parameter - * as soon as an interrupt is detected. - * - * \param ul_pin Pin index to configure. - * \param ul_flag Pin flag. - * \param p_handler Interrupt handler function pointer. - * - * \return 0 if successful, 1 if the maximum number of sources has been defined. - */ -uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, - void (*p_handler) (uint32_t, uint32_t)) -{ - Pio *p_pio = pio_get_pin_group(ul_pin); - uint32_t group_id = pio_get_pin_group_id(ul_pin); - uint32_t group_mask = pio_get_pin_group_mask(ul_pin); - - return pio_handler_set(p_pio, group_id, group_mask, ul_flag, p_handler); -} - -/** - * \brief Parallel IO Controller A interrupt handler. - * Redefined PIOA interrupt handler for NVIC interrupt table. - */ -void PIOA_Handler(void) -{ - pio_handler_process(PIOA, ID_PIOA); -} -#endif - -#ifdef ID_PIOB -/** - * \brief Parallel IO Controller B interrupt handler - * Redefined PIOB interrupt handler for NVIC interrupt table. - */ -void PIOB_Handler(void) -{ - pio_handler_process(PIOB, ID_PIOB); -} -#endif - -#ifdef ID_PIOC -/** - * \brief Parallel IO Controller C interrupt handler. - * Redefined PIOC interrupt handler for NVIC interrupt table. - */ -void PIOC_Handler(void) -{ - pio_handler_process(PIOC, ID_PIOC); -} -#endif - -#ifdef ID_PIOD -/** - * \brief Parallel IO Controller D interrupt handler. - * Redefined PIOD interrupt handler for NVIC interrupt table. - */ -void PIOD_Handler(void) -{ - pio_handler_process(PIOD, ID_PIOD); -} -#endif - -#ifdef ID_PIOE -/** - * \brief Parallel IO Controller E interrupt handler. - * Redefined PIOE interrupt handler for NVIC interrupt table. - */ -void PIOE_Handler(void) -{ - pio_handler_process(PIOE, ID_PIOE); -} -#endif - -#ifdef ID_PIOF -/** - * \brief Parallel IO Controller F interrupt handler. - * Redefined PIOF interrupt handler for NVIC interrupt table. - */ -void PIOF_Handler(void) -{ - pio_handler_process(PIOF, ID_PIOF); -} -#endif - -/** - * \brief Initialize PIO interrupt management logic. - * - * \param p_pio PIO controller base address. - * \param ul_irqn NVIC line number. - * \param ul_priority PIO controller interrupts priority. - */ -void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority) -{ - uint32_t bitmask = 0; - - bitmask = pio_get_interrupt_mask(p_pio); - pio_disable_interrupt(p_pio, 0xFFFFFFFF); - pio_get_interrupt_status(p_pio); - NVIC_DisableIRQ(ul_irqn); - NVIC_ClearPendingIRQ(ul_irqn); - NVIC_SetPriority(ul_irqn, ul_priority); - NVIC_EnableIRQ(ul_irqn); - pio_enable_interrupt(p_pio, bitmask); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.h deleted file mode 100644 index 9ab88cef0ad..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * \file - * - * \brief Parallel Input/Output (PIO) interrupt handler for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef PIO_HANDLER_H_INCLUDED -#define PIO_HANDLER_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -void pio_handler_process(Pio *p_pio, uint32_t ul_id); -void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority); -uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, - uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)); -uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, - void (*p_handler) (uint32_t, uint32_t)); - -#if (SAM3S || SAM4S || SAM4E) -void pio_capture_handler_set(void (*p_handler)(Pio *)); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* PIO_HANDLER_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.c deleted file mode 100644 index a06979e7159..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.c +++ /dev/null @@ -1,1647 +0,0 @@ -/** - * \file - * - * \brief Power Management Controller (PMC) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "pmc.h" - -#if (SAM3N) -# define MAX_PERIPH_ID 31 -#elif (SAM3XA) -# define MAX_PERIPH_ID 44 -#elif (SAM3U) -# define MAX_PERIPH_ID 29 -#elif (SAM3S || SAM4S) -# define MAX_PERIPH_ID 34 -#elif (SAM4E) -# define MAX_PERIPH_ID 47 -#elif (SAMV71) -# define MAX_PERIPH_ID 63 -#elif (SAMV70) -# define MAX_PERIPH_ID 63 -#elif (SAME70) -# define MAX_PERIPH_ID 63 -#elif (SAMS70) -# define MAX_PERIPH_ID 63 -#elif (SAM4N) -# define MAX_PERIPH_ID 31 -#elif (SAM4C || SAM4CM || SAM4CP) -# define MAX_PERIPH_ID 43 -#elif (SAMG51) -# define MAX_PERIPH_ID 47 -#elif (SAMG53) -# define MAX_PERIPH_ID 47 -#elif (SAMG54) -# define MAX_PERIPH_ID 47 -#elif (SAMG55) -# define MAX_PERIPH_ID 50 -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \defgroup sam_drivers_pmc_group Power Management Controller (PMC) - * - * \par Purpose - * - * The Power Management Controller (PMC) optimizes power consumption by - * controlling all system and user peripheral clocks. The PMC enables/disables - * the clock inputs to many of the peripherals and the Cortex-M Processor. - * - * @{ - */ - - /** - * \brief Set the prescaler of the MCK. - * - * \param ul_pres Prescaler value. - */ - void pmc_mck_set_prescaler(uint32_t ul_pres) -{ - PMC->PMC_MCKR = - (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); -} - -#if SAMV71 || SAMV70 || SAME70 || SAMS70 -/** - * \brief Set the division of the MCK. - * - * \param ul_div Division value. - */ -void pmc_mck_set_division(uint32_t ul_div) -{ - switch (ul_div) { - case 1: - ul_div = PMC_MCKR_MDIV_EQ_PCK; - break; - case 2: - ul_div = PMC_MCKR_MDIV_PCK_DIV2; - break; - case 3: - ul_div = PMC_MCKR_MDIV_PCK_DIV3; - break; - case 4: - ul_div = PMC_MCKR_MDIV_PCK_DIV4; - break; - default: - ul_div = PMC_MCKR_MDIV_EQ_PCK; - break; - } - PMC->PMC_MCKR = - (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); -} -#endif - -/** - * \brief Set the source of the MCK. - * - * \param ul_source Source selection value. - */ -void pmc_mck_set_source(uint32_t ul_source) -{ - PMC->PMC_MCKR = - (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); -} - -/** - * \brief Switch master clock source selection to slow clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_SLOW_CLK; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Switch master clock source selection to main clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_MAIN_CLK; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Switch master clock source selection to PLLA clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_PLLA_CLK; - - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) -/** - * \brief Switch master clock source selection to PLLB clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_PLLB_CLK; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} -#endif - -#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Switch master clock source selection to UPLL clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_UPLL_CLK; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} -#endif - -/** - * \brief Switch slow clock source selection to external 32k (Xtal or Bypass). - * - * \note Switching SCLK back to 32krc is only possible by shutting down the - * VDDIO power supply. - * - * \param ul_bypass 0 for Xtal, 1 for bypass. - */ -void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass) -{ - /* Set Bypass mode if required */ - if (ul_bypass == 1) { - SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD | - SUPC_MR_OSCBYPASS; - } - - SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; -} - -/** - * \brief Check if the external 32k Xtal is ready. - * - * \retval 1 External 32k Xtal is ready. - * \retval 0 External 32k Xtal is not ready. - */ -uint32_t pmc_osc_is_ready_32kxtal(void) -{ - return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) - && (PMC->PMC_SR & PMC_SR_OSCSELS)); -} - -/** - * \brief Switch main clock source selection to internal fast RC. - * - * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz). - * - * \retval 0 Success. - * \retval 1 Timeout error. - * \retval 2 Invalid frequency. - */ -void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf) -{ - /* Enable Fast RC oscillator but DO NOT switch to RC now */ - PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); - - /* Wait the Fast RC to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); - - /* Change Fast RC oscillator frequency */ - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | - CKGR_MOR_KEY_PASSWD | ul_moscrcf; - - /* Wait the Fast RC to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); - - /* Switch to Fast RC */ - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | - CKGR_MOR_KEY_PASSWD; -} - -/** - * \brief Enable fast RC oscillator. - * - * \param ul_rc Fast RC oscillator(4/8/12Mhz). - */ -void pmc_osc_enable_fastrc(uint32_t ul_rc) -{ - /* Enable Fast RC oscillator but DO NOT switch to RC */ - PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); - /* Wait the Fast RC to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); - - /* Change Fast RC oscillator frequency */ - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | - CKGR_MOR_KEY_PASSWD | ul_rc; - /* Wait the Fast RC to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); -} - -/** - * \brief Disable the internal fast RC. - */ -void pmc_osc_disable_fastrc(void) -{ - /* Disable Fast RC oscillator */ - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & - ~CKGR_MOR_MOSCRCF_Msk) - | CKGR_MOR_KEY_PASSWD; -} - -/** - * \brief Check if the main fastrc is ready. - * - * \retval 0 Xtal is not ready, otherwise ready. - */ -uint32_t pmc_osc_is_ready_fastrc(void) -{ - return (PMC->PMC_SR & PMC_SR_MOSCRCS); -} - -/** - * \brief Enable main XTAL oscillator. - * - * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks. - */ -void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time) -{ - uint32_t mor = PMC->CKGR_MOR; - mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); - mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | - CKGR_MOR_MOSCXTST(ul_xtal_startup_time); - PMC->CKGR_MOR = mor; - /* Wait the main Xtal to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); -} - -/** - * \brief Bypass main XTAL. - */ -void pmc_osc_bypass_main_xtal(void) -{ - uint32_t mor = PMC->CKGR_MOR; - mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); - mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY; - /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */ - PMC->CKGR_MOR = mor; - /* The MOSCXTS in PMC_SR is automatically set */ -} - -/** - * \brief Disable the main Xtal. - */ -void pmc_osc_disable_main_xtal(void) -{ - uint32_t mor = PMC->CKGR_MOR; - mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; -} - -/** - * \brief Check if the main crystal is bypassed. - * - * \retval 0 Xtal is bypassed, otherwise not. - */ -uint32_t pmc_osc_is_bypassed_main_xtal(void) -{ - return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY); -} - -/** - * \brief Check if the main crystal is ready. - * - * \note If main crystal is bypassed, it's always ready. - * - * \retval 0 main crystal is not ready, otherwise ready. - */ -uint32_t pmc_osc_is_ready_main_xtal(void) -{ - return (PMC->PMC_SR & PMC_SR_MOSCXTS); -} - -/** - * \brief Switch main clock source selection to external Xtal/Bypass. - * - * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid - * any system crash. - * - * \note If used in Xtal mode, the Xtal is automatically enabled. - * - * \param ul_bypass 0 for Xtal, 1 for bypass. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, - uint32_t ul_xtal_startup_time) -{ - /* Enable Main Xtal oscillator */ - if (ul_bypass) { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | - CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | - CKGR_MOR_MOSCSEL; - } else { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | - CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | - CKGR_MOR_MOSCXTST(ul_xtal_startup_time); - /* Wait the Xtal to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); - - PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; - } -} - -/** - * \brief Disable the external Xtal. - * - * \param ul_bypass 0 for Xtal, 1 for bypass. - */ -void pmc_osc_disable_xtal(uint32_t ul_bypass) -{ - /* Disable xtal oscillator */ - if (ul_bypass) { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | - CKGR_MOR_KEY_PASSWD; - } else { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | - CKGR_MOR_KEY_PASSWD; - } -} - -/** - * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one - * of Xtal, bypass or internal RC. - * - * \retval 1 Xtal is ready. - * \retval 0 Xtal is not ready. - */ -uint32_t pmc_osc_is_ready_mainck(void) -{ - return PMC->PMC_SR & PMC_SR_MOSCSELS; -} - -/** - * \brief Select Main Crystal or internal RC as main clock source. - * - * \note This function will not enable/disable RC or Main Crystal. - * - * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal. - */ -void pmc_mainck_osc_select(uint32_t ul_xtal_rc) -{ - uint32_t mor = PMC->CKGR_MOR; - if (ul_xtal_rc) { - mor |= CKGR_MOR_MOSCSEL; - } else { - mor &= ~CKGR_MOR_MOSCSEL; - } - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; -} - -/** - * \brief Enable PLLA clock. - * - * \param mula PLLA multiplier. - * \param pllacount PLLA counter. - * \param diva Divider. - */ -void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva) -{ - /* first disable the PLL to unlock the lock */ - pmc_disable_pllack(); - -#if (SAM4C || SAM4CM || SAM4CP || SAMG) - PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) | - CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); -#else - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) | - CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); -#endif - while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0); -} - -/** - * \brief Disable PLLA clock. - */ -void pmc_disable_pllack(void) -{ -#if (SAM4C || SAM4CM || SAM4CP || SAMG) - PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0); -#else - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0); -#endif -} - -/** - * \brief Is PLLA locked? - * - * \retval 0 Not locked. - * \retval 1 Locked. - */ -uint32_t pmc_is_locked_pllack(void) -{ - return (PMC->PMC_SR & PMC_SR_LOCKA); -} - -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) -/** - * \brief Enable PLLB clock. - * - * \param mulb PLLB multiplier. - * \param pllbcount PLLB counter. - * \param divb Divider. - */ -void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb) -{ - /* first disable the PLL to unlock the lock */ - pmc_disable_pllbck(); - -#if SAMG55 - PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) | - CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb); -#else - PMC->CKGR_PLLBR = - CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount) - | CKGR_PLLBR_MULB(mulb); -#endif - while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0); -} - -/** - * \brief Disable PLLB clock. - */ -void pmc_disable_pllbck(void) -{ - PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0); -} - -/** - * \brief Is PLLB locked? - * - * \retval 0 Not locked. - * \retval 1 Locked. - */ -uint32_t pmc_is_locked_pllbck(void) -{ - return (PMC->PMC_SR & PMC_SR_LOCKB); -} -#endif - -#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Enable UPLL clock. - */ -void pmc_enable_upll_clock(void) -{ - PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN; - - /* Wait UTMI PLL Lock Status */ - while (!(PMC->PMC_SR & PMC_SR_LOCKU)); -} - -/** - * \brief Disable UPLL clock. - */ -void pmc_disable_upll_clock(void) -{ - PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; -} - -/** - * \brief Is UPLL locked? - * - * \retval 0 Not locked. - * \retval 1 Locked. - */ -uint32_t pmc_is_locked_upll(void) -{ - return (PMC->PMC_SR & PMC_SR_LOCKU); -} -#endif - -/** - * \brief Enable the specified peripheral clock. - * - * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). - * - * \param ul_id Peripheral ID (ID_xxx). - * - * \retval 0 Success. - * \retval 1 Invalid parameter. - */ -uint32_t pmc_enable_periph_clk(uint32_t ul_id) -{ - if (ul_id > MAX_PERIPH_ID) { - return 1; - } - - if (ul_id < 32) { - if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { - PMC->PMC_PCER0 = 1 << ul_id; - } -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - } else { - ul_id -= 32; - if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { - PMC->PMC_PCER1 = 1 << ul_id; - } -#endif - } - - return 0; -} - -/** - * \brief Disable the specified peripheral clock. - * - * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). - * - * \param ul_id Peripheral ID (ID_xxx). - * - * \retval 0 Success. - * \retval 1 Invalid parameter. - */ -uint32_t pmc_disable_periph_clk(uint32_t ul_id) -{ - if (ul_id > MAX_PERIPH_ID) { - return 1; - } - - if (ul_id < 32) { - if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) { - PMC->PMC_PCDR0 = 1 << ul_id; - } -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \ - || SAMV70 || SAME70 || SAMS70) - } else { - ul_id -= 32; - if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) { - PMC->PMC_PCDR1 = 1 << ul_id; - } -#endif - } - return 0; -} - -/** - * \brief Enable all peripheral clocks. - */ -void pmc_enable_all_periph_clk(void) -{ - PMC->PMC_PCER0 = PMC_MASK_STATUS0; - while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0); - -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ - || SAMV70 || SAME70 || SAMS70) - PMC->PMC_PCER1 = PMC_MASK_STATUS1; - while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1); -#endif -} - -/** - * \brief Disable all peripheral clocks. - */ -void pmc_disable_all_periph_clk(void) -{ - PMC->PMC_PCDR0 = PMC_MASK_STATUS0; - while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0); - -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ - || SAMV70 || SAME70 || SAMS70) - PMC->PMC_PCDR1 = PMC_MASK_STATUS1; - while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0); -#endif -} - -/** - * \brief Check if the specified peripheral clock is enabled. - * - * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). - * - * \param ul_id Peripheral ID (ID_xxx). - * - * \retval 0 Peripheral clock is disabled or unknown. - * \retval 1 Peripheral clock is enabled. - */ -uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id) -{ - if (ul_id > MAX_PERIPH_ID) { - return 0; - } - -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ - || SAMV70 || SAME70 || SAMS70) - if (ul_id < 32) { -#endif - if ((PMC->PMC_PCSR0 & (1u << ul_id))) { - return 1; - } else { - return 0; - } -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ - || SAMV70 || SAME70 || SAMS70) - } else { - ul_id -= 32; - if ((PMC->PMC_PCSR1 & (1u << ul_id))) { - return 1; - } else { - return 0; - } - } -#endif -} - -/** - * \brief Set the prescaler for the specified programmable clock. - * - * \param ul_id Peripheral ID. - * \param ul_pres Prescaler value. - */ -void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres) -{ - PMC->PMC_PCK[ul_id] = - (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres; - while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) - && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); -} - -/** - * \brief Set the source oscillator for the specified programmable clock. - * - * \param ul_id Peripheral ID. - * \param ul_source Source selection value. - */ -void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source) -{ - PMC->PMC_PCK[ul_id] = - (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source; - while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) - && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); -} - -/** - * \brief Switch programmable clock source selection to slow clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Switch programmable clock source selection to main clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Switch programmable clock source selection to PLLA clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) -/** - * \brief Switch programmable clock source selection to PLLB clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} -#endif - -#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Switch programmable clock source selection to UPLL clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} -#endif - -/** - * \brief Switch programmable clock source selection to mck. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Enable the specified programmable clock. - * - * \param ul_id Id of the programmable clock. - */ -void pmc_enable_pck(uint32_t ul_id) -{ - PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id; -} - -/** - * \brief Disable the specified programmable clock. - * - * \param ul_id Id of the programmable clock. - */ -void pmc_disable_pck(uint32_t ul_id) -{ - PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id; -} - -/** - * \brief Enable all programmable clocks. - */ -void pmc_enable_all_pck(void) -{ - PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2; -} - -/** - * \brief Disable all programmable clocks. - */ -void pmc_disable_all_pck(void) -{ - PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; -} - -/** - * \brief Check if the specified programmable clock is enabled. - * - * \param ul_id Id of the programmable clock. - * - * \retval 0 Programmable clock is disabled or unknown. - * \retval 1 Programmable clock is enabled. - */ -uint32_t pmc_is_pck_enabled(uint32_t ul_id) -{ - if (ul_id > 2) { - return 0; - } - - return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id)); -} - -#if (SAM4C || SAM4CM || SAM4CP) -/** - * \brief Enable Coprocessor Clocks. - */ -void pmc_enable_cpck(void) -{ - PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; -} - -/** - * \brief Disable Coprocessor Clocks. - */ -void pmc_disable_cpck(void) -{ - PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD; -} - -/** - * \brief Check if the Coprocessor Clocks is enabled. - * - * \retval 0 Coprocessor Clocks is disabled. - * \retval 1 Coprocessor Clocks is enabled. - */ -bool pmc_is_cpck_enabled(void) -{ - if(PMC->PMC_SCSR & PMC_SCSR_CPCK) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Enable Coprocessor Bus Master Clocks. - */ -void pmc_enable_cpbmck(void) -{ - PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; -} - -/** - * \brief Disable Coprocessor Bus Master Clocks. - */ -void pmc_disable_cpbmck(void) -{ - PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD; -} - -/** - * \brief Check if the Coprocessor Bus Master Clocks is enabled. - * - * \retval 0 Coprocessor Bus Master Clocks is disabled. - * \retval 1 Coprocessor Bus Master Clocks is enabled. - */ -bool pmc_is_cpbmck_enabled(void) -{ - if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Set the prescaler for the Coprocessor Master Clock. - * - * \param ul_pres Prescaler value. - */ -void pmc_cpck_set_prescaler(uint32_t ul_pres) -{ - PMC->PMC_MCKR = - (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres); -} - -/** - * \brief Set the source for the Coprocessor Master Clock. - * - * \param ul_source Source selection value. - */ -void pmc_cpck_set_source(uint32_t ul_source) -{ - PMC->PMC_MCKR = - (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source; -} -#endif - -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Switch UDP (USB) clock source selection to PLLA clock. - * - * \param ul_usbdiv Clock divisor. - */ -void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv) -{ - PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); -} -#endif - -#if (SAM3S || SAM4S || SAMG55) -/** - * \brief Switch UDP (USB) clock source selection to PLLB clock. - * - * \param ul_usbdiv Clock divisor. - */ -void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv) -{ - PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; -} -#endif - -#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Switch UDP (USB) clock source selection to UPLL clock. - * - * \param ul_usbdiv Clock divisor. - */ -void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv) -{ - PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv); -} -#endif - -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Enable UDP (USB) clock. - */ -void pmc_enable_udpck(void) -{ -#if (SAM3S || SAM4S || SAM4E || SAMG55) - PMC->PMC_SCER = PMC_SCER_UDP; -#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) - PMC->PMC_SCER = PMC_SCER_USBCLK; -#else - PMC->PMC_SCER = PMC_SCER_UOTGCLK; -# endif -} - -/** - * \brief Disable UDP (USB) clock. - */ -void pmc_disable_udpck(void) -{ -#if (SAM3S || SAM4S || SAM4E || SAMG55) - PMC->PMC_SCDR = PMC_SCDR_UDP; -#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) - PMC->PMC_SCDR = PMC_SCDR_USBCLK; -#else - PMC->PMC_SCDR = PMC_SCDR_UOTGCLK; -# endif -} -#endif - -#if SAMG55 -/** - * \brief Switch UHP (USB) clock source selection to PLLA clock. - * - * \param ul_usbdiv Clock divisor. - */ -void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv) -{ - PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); -} - -/** - * \brief Switch UHP (USB) clock source selection to PLLB clock. - * - * \param ul_usbdiv Clock divisor. - */ -void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv) -{ - PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; -} - -/** - * \brief Enable UHP (USB) clock. - */ -void pmc_enable_uhpck(void) -{ - PMC->PMC_SCER = PMC_SCER_UHP; -} -#endif - -/** - * \brief Enable PMC interrupts. - * - * \param ul_sources Interrupt sources bit map. - */ -void pmc_enable_interrupt(uint32_t ul_sources) -{ - PMC->PMC_IER = ul_sources; -} - -/** - * \brief Disable PMC interrupts. - * - * \param ul_sources Interrupt sources bit map. - */ -void pmc_disable_interrupt(uint32_t ul_sources) -{ - PMC->PMC_IDR = ul_sources; -} - -/** - * \brief Get PMC interrupt mask. - * - * \return The interrupt mask value. - */ -uint32_t pmc_get_interrupt_mask(void) -{ - return PMC->PMC_IMR; -} - -/** - * \brief Get current status. - * - * \return The current PMC status. - */ -uint32_t pmc_get_status(void) -{ - return PMC->PMC_SR; -} - -/** - * \brief Set the wake-up inputs for fast startup mode registers - * (event generation). - * - * \param ul_inputs Wake up inputs to enable. - */ -void pmc_set_fast_startup_input(uint32_t ul_inputs) -{ - ul_inputs &= PMC_FAST_STARTUP_Msk; - PMC->PMC_FSMR |= ul_inputs; -} - -/** - * \brief Clear the wake-up inputs for fast startup mode registers - * (remove event generation). - * - * \param ul_inputs Wake up inputs to disable. - */ -void pmc_clr_fast_startup_input(uint32_t ul_inputs) -{ - ul_inputs &= PMC_FAST_STARTUP_Msk; - PMC->PMC_FSMR &= ~ul_inputs; -} - -#if (SAM4C || SAM4CM || SAM4CP) -/** - * \brief Set the wake-up inputs of coprocessor for fast startup mode registers - * (event generation). - * - * \param ul_inputs Wake up inputs to enable. - */ -void pmc_cp_set_fast_startup_input(uint32_t ul_inputs) -{ - ul_inputs &= PMC_FAST_STARTUP_Msk; - PMC->PMC_CPFSMR |= ul_inputs; -} - -/** - * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers - * (remove event generation). - * - * \param ul_inputs Wake up inputs to disable. - */ -void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs) -{ - ul_inputs &= PMC_FAST_STARTUP_Msk; - PMC->PMC_CPFSMR &= ~ul_inputs; -} -#endif - -#if (!(SAMG51 || SAMG53 || SAMG54)) -/** - * \brief Enable Sleep Mode. - * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0) - * - * \param uc_type 0 for wait for interrupt, 1 for wait for event. - * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series, - * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0. - */ -void pmc_enable_sleepmode(uint8_t uc_type) -{ -#if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) - PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode -#endif - SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep - -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) - UNUSED(uc_type); - __WFI(); -#else - if (uc_type == 0) { - __WFI(); - } else { - __WFE(); - } -#endif -} -#endif - -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) -static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN; - /** - * \brief Set the embedded flash state in wait mode - * - * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode, - * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode. - */ - void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state) -{ - ul_flash_in_wait_mode = ul_flash_state; -} - -/** - * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM - * - * \note In this function, FLPM will retain, WAITMODE bit will be set, - * Generally, this function will be called by pmc_sleep() in order to - * complete all sequence entering wait mode. - * See \ref pmc_sleep() for entering different sleep modes. - */ -void pmc_enable_waitmode(void) -{ - uint32_t i; - - /* Flash in wait mode */ - i = PMC->PMC_FSMR; - i &= ~PMC_FSMR_FLPM_Msk; - i |= ul_flash_in_wait_mode; - PMC->PMC_FSMR = i; - - /* Set the WAITMODE bit = 1 */ - PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE; - - /* Waiting for Master Clock Ready MCKRDY = 1 */ - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); - - /* Waiting for MOSCRCEN bit cleared is strongly recommended - * to ensure that the core will not execute undesired instructions - */ - for (i = 0; i < 500; i++) { - __NOP(); - } - while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); - -#if (!SAMG) - /* Restore Flash in idle mode */ - i = PMC->PMC_FSMR; - i &= ~PMC_FSMR_FLPM_Msk; - i |= PMC_WAIT_MODE_FLASH_IDLE; - PMC->PMC_FSMR = i; -#endif -} -#else -/** - * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) + - * (LPM bit = 1) - */ -void pmc_enable_waitmode(void) -{ - uint32_t i; - - PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */ - SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */ - - __WFE(); - - /* Waiting for MOSCRCEN bit cleared is strongly recommended - * to ensure that the core will not execute undesired instructions - */ - for (i = 0; i < 500; i++) { - __NOP(); - } - while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); - -} -#endif - -#if (!(SAMG51 || SAMG53 || SAMG54)) -/** - * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) + - * (SLEEPDEEP bit = 1) - */ -void pmc_enable_backupmode(void) -{ -#if (SAM4C || SAM4CM || SAM4CP) - uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk); - SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD; - while (SUPC->SUPC_SR & SUPC_SR_BUPPORS); -#endif - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; - __WFE(); - __WFI(); -#else - __WFE(); -#endif -} -#endif - -/** - * \brief Enable Clock Failure Detector. - */ -void pmc_enable_clock_failure_detector(void) -{ - uint32_t ul_reg = PMC->CKGR_MOR; - - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg; -} - -/** - * \brief Disable Clock Failure Detector. - */ -void pmc_disable_clock_failure_detector(void) -{ - uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN); - - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; -} - -#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Enable Slow Crystal Oscillator Frequency Monitoring. - */ -void pmc_enable_sclk_osc_freq_monitor(void) -{ - uint32_t ul_reg = PMC->CKGR_MOR; - - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg; -} - -/** - * \brief Disable Slow Crystal Oscillator Frequency Monitoring. - */ -void pmc_disable_sclk_osc_freq_monitor(void) -{ - uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME); - - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; -} -#endif - -/** - * \brief Enable or disable write protect of PMC registers. - * - * \param ul_enable 1 to enable, 0 to disable. - */ -void pmc_set_writeprotect(uint32_t ul_enable) -{ - if (ul_enable) { - PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN; - } else { - PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD; - } -} - -/** - * \brief Return write protect status. - * - * \return Return write protect status. - */ -uint32_t pmc_get_writeprotect_status(void) -{ - return PMC->PMC_WPSR; -} - -#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Enable the specified peripheral clock. - * - * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). - * - * \param ul_id Peripheral ID (ID_xxx). - * - * \retval 0 Success. - * \retval 1 Fail. - */ -uint32_t pmc_enable_sleepwalking(uint32_t ul_id) -{ - uint32_t temp; -#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - if ((7 <= ul_id) && (ul_id<= 29)) { -#else - if ((8 <= ul_id) && (ul_id<= 29)) { -#endif - temp = pmc_get_active_status0(); - if (temp & (1 << ul_id)) { - return 1; - } - PMC->PMC_SLPWK_ER0 = 1 << ul_id; - temp = pmc_get_active_status0(); - if (temp & (1 << ul_id)) { - pmc_disable_sleepwalking(ul_id); - return 1; - } - return 0; - } -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) - else if ((32 <= ul_id) && (ul_id<= 60)) { - ul_id -= 32; - temp = pmc_get_active_status1(); - if (temp & (1 << ul_id)) { - return 1; - } - PMC->PMC_SLPWK_ER1 = 1 << ul_id; - temp = pmc_get_active_status1(); - if (temp & (1 << ul_id)) { - pmc_disable_sleepwalking(ul_id); - return 1; - } - return 0; - } -#endif - else { - return 1; - } -} - -/** - * \brief Disable the sleepwalking of specified peripheral. - * - * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). - * - * \param ul_id Peripheral ID (ID_xxx). - * - * \retval 0 Success. - * \retval 1 Invalid parameter. - */ -uint32_t pmc_disable_sleepwalking(uint32_t ul_id) -{ -#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - if ((7 <= ul_id) && (ul_id<= 29)) { -#else - if ((8 <= ul_id) && (ul_id<= 29)) { -#endif - PMC->PMC_SLPWK_DR0 = 1 << ul_id; - return 0; - } -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) - else if ((32 <= ul_id) && (ul_id<= 60)) { - ul_id -= 32; - PMC->PMC_SLPWK_DR1 = 1 << ul_id; - return 0; - } -#endif - else { - return 1; - } -} - -/** - * \brief Return peripheral sleepwalking enable status. - * - * \return the status register value. - */ -uint32_t pmc_get_sleepwalking_status0(void) -{ - return PMC->PMC_SLPWK_SR0; -} - -/** - * \brief Return peripheral active status. - * - * \return the status register value. - */ -uint32_t pmc_get_active_status0(void) -{ - return PMC->PMC_SLPWK_ASR0; -} - -#endif - -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Return peripheral sleepwalking enable status. - * - * \return the status register value. - */ -uint32_t pmc_get_sleepwalking_status1(void) -{ - return PMC->PMC_SLPWK_SR1; -} - -/** - * \brief Return peripheral active status. - * - * \return the status register value. - */ -uint32_t pmc_get_active_status1(void) -{ - return PMC->PMC_SLPWK_ASR1; -} -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.h deleted file mode 100644 index af554518fa5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.h +++ /dev/null @@ -1,550 +0,0 @@ -/** - * \file - * - * \brief Power Management Controller (PMC) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef PMC_H_INCLUDED -#define PMC_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** Bit mask for peripheral clocks (PCER0) */ -#define PMC_MASK_STATUS0 (0xFFFFFFFC) - - /** Bit mask for peripheral clocks (PCER1) */ -#define PMC_MASK_STATUS1 (0xFFFFFFFF) - - /** Loop counter timeout value */ -#if !(SAME70) -#define PMC_TIMEOUT (2048) -#else -#define PMC_TIMEOUT (4096) -#endif - - /** Key to unlock CKGR_MOR register */ -#ifndef CKGR_MOR_KEY_PASSWD -#define CKGR_MOR_KEY_PASSWD CKGR_MOR_KEY(0x37U) -#endif - - /** Key used to write SUPC registers */ -#ifndef SUPC_CR_KEY_PASSWD -#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U) -#endif - -#ifndef SUPC_MR_KEY_PASSWD -#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U) -#endif - - /** Mask to access fast startup input */ -#define PMC_FAST_STARTUP_Msk (0x7FFFFu) - - /** PMC_WPMR Write Protect KEY, unlock it */ -#ifndef PMC_WPMR_WPKEY_PASSWD -#define PMC_WPMR_WPKEY_PASSWD PMC_WPMR_WPKEY((uint32_t) 0x504D43) -#endif - - /** Using external oscillator */ -#define PMC_OSC_XTAL 0 - - /** Oscillator in bypass mode */ -#define PMC_OSC_BYPASS 1 - -#define PMC_PCK_0 0 /* PCK0 ID */ -#define PMC_PCK_1 1 /* PCK1 ID */ -#define PMC_PCK_2 2 /* PCK2 ID */ -#if SAMG55 -#define PMC_PCK_3 3 /* PCK3 ID */ -#define PMC_PCK_4 4 /* PCK4 ID */ -#define PMC_PCK_5 5 /* PCK5 ID */ -#define PMC_PCK_6 6 /* PCK6 ID */ -#define PMC_PCK_7 7 /* PCK7 ID */ -#endif - -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) - /** Flash state in Wait Mode */ -#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY -#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN -#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE -#endif - - /** Convert startup time from us to MOSCXTST */ -#define pmc_us_to_moscxtst(startup_us, slowck_freq) \ - ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \ - (startup_us * slowck_freq / 8 / 1000000) : 0xFF) - - /** - * \name Master clock (MCK) Source and Prescaler configuration - * - * \note The following functions may be used to select the clock source and - * prescaler for the master clock. - */ -//@{ - - void pmc_mck_set_prescaler(uint32_t ul_pres); -#if SAMV71 || SAMV70 || SAME70 || SAMS70 - void pmc_mck_set_division(uint32_t ul_div); -#endif - void pmc_mck_set_source(uint32_t ul_source); - uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres); - uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres); - uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres); -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) - uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres); -#endif -#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) - uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres); -#endif -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) - void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state); -#endif - - -//@} - - /** - * \name Slow clock (SLCK) oscillator and configuration - * - */ -//@{ - - void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass); - uint32_t pmc_osc_is_ready_32kxtal(void); - -//@} - - /** - * \name Main Clock (MAINCK) oscillator and configuration - * - */ -//@{ - - void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf); - void pmc_osc_enable_fastrc(uint32_t ul_rc); - void pmc_osc_disable_fastrc(void); - uint32_t pmc_osc_is_ready_fastrc(void); - void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time); - void pmc_osc_bypass_main_xtal(void); - void pmc_osc_disable_main_xtal(void); - uint32_t pmc_osc_is_bypassed_main_xtal(void); - uint32_t pmc_osc_is_ready_main_xtal(void); - void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, - uint32_t ul_xtal_startup_time); - void pmc_osc_disable_xtal(uint32_t ul_bypass); - uint32_t pmc_osc_is_ready_mainck(void); - void pmc_mainck_osc_select(uint32_t ul_xtal_rc); - -//@} - - /** - * \name PLL oscillator and configuration - * - */ -//@{ - - void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva); - void pmc_disable_pllack(void); - uint32_t pmc_is_locked_pllack(void); - -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) - void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb); - void pmc_disable_pllbck(void); - uint32_t pmc_is_locked_pllbck(void); -#endif - -#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) - void pmc_enable_upll_clock(void); - void pmc_disable_upll_clock(void); - uint32_t pmc_is_locked_upll(void); -#endif - -//@} - - /** - * \name Peripherals clock configuration - * - */ -//@{ - - uint32_t pmc_enable_periph_clk(uint32_t ul_id); - uint32_t pmc_disable_periph_clk(uint32_t ul_id); - void pmc_enable_all_periph_clk(void); - void pmc_disable_all_periph_clk(void); - uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id); - -//@} - - /** - * \name Programmable clock Source and Prescaler configuration - * - * The following functions may be used to select the clock source and - * prescaler for the specified programmable clock. - */ -//@{ - - void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres); - void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source); - uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres); - uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres); - uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres); -#if (SAM4C || SAM4CM || SAM4CP) - void pmc_enable_cpck(void); - void pmc_disable_cpck(void); - bool pmc_is_cpck_enabled(void); - void pmc_enable_cpbmck(void); - void pmc_disable_cpbmck(void); - bool pmc_is_cpbmck_enabled(void); - void pmc_cpck_set_prescaler(uint32_t ul_pres); - void pmc_cpck_set_source(uint32_t ul_source); -#endif -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) - uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres); -#endif -#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) - uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres); -#endif - uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres); - void pmc_enable_pck(uint32_t ul_id); - void pmc_disable_pck(uint32_t ul_id); - void pmc_enable_all_pck(void); - void pmc_disable_all_pck(void); - uint32_t pmc_is_pck_enabled(uint32_t ul_id); - -//@} - - /** - * \name USB clock configuration - * - */ -//@{ - -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv); -#endif -#if (SAM3S || SAM4S || SAMG55) - void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv); -#endif -#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) - void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv); -#endif -#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - void pmc_enable_udpck(void); - void pmc_disable_udpck(void); -#endif -#if SAMG55 - void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv); - void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv); - void pmc_enable_uhpck(void); -#endif - -//@} - - /** - * \name Interrupt and status management - * - */ -//@{ - - void pmc_enable_interrupt(uint32_t ul_sources); - void pmc_disable_interrupt(uint32_t ul_sources); - uint32_t pmc_get_interrupt_mask(void); - uint32_t pmc_get_status(void); - -//@} - - /** - * \name Power management - * - * The following functions are used to configure sleep mode and additional - * wake up inputs. - */ -//@{ - - void pmc_set_fast_startup_input(uint32_t ul_inputs); - void pmc_clr_fast_startup_input(uint32_t ul_inputs); -#if (SAM4C || SAM4CM || SAM4CP) - void pmc_cp_set_fast_startup_input(uint32_t ul_inputs); - void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs); -#endif -#if (!(SAMG51 || SAMG53 || SAMG54)) - void pmc_enable_sleepmode(uint8_t uc_type); -#endif - void pmc_enable_waitmode(void); -#if (!(SAMG51 || SAMG53 || SAMG54)) - void pmc_enable_backupmode(void); -#endif -//@} - - /** - * \name Failure detector - * - */ -//@{ - - void pmc_enable_clock_failure_detector(void); - void pmc_disable_clock_failure_detector(void); - -//@} - -#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) - /** - * \name Slow Crystal Oscillator Frequency Monitoring - * - */ -//@{ - - void pmc_enable_sclk_osc_freq_monitor(void); - void pmc_disable_sclk_osc_freq_monitor(void); - -//@} -#endif - - /** - * \name Write protection - * - */ -//@{ - - void pmc_set_writeprotect(uint32_t ul_enable); - uint32_t pmc_get_writeprotect_status(void); - -//@} - -#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - /** - * \name Sleepwalking configuration - * - */ -//@{ - - uint32_t pmc_enable_sleepwalking(uint32_t ul_id); - uint32_t pmc_disable_sleepwalking(uint32_t ul_id); - uint32_t pmc_get_sleepwalking_status0(void); - uint32_t pmc_get_active_status0(void); -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) - uint32_t pmc_get_sleepwalking_status1(void); - uint32_t pmc_get_active_status1(void); -#endif -//@} -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -//! @} - -/** - * \page sam_pmc_quickstart Quick start guide for the SAM PMC module - * - * This is the quick start guide for the \ref sam_drivers_pmc_group "PMC module", - * with step-by-step instructions on how to configure and use the driver in a - * selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section pmc_use_cases PMC use cases - * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources - * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks - * - * \section pmc_basic_use_case Basic use case - Switch Main Clock sources - * In this use case, the PMC module is configured for a variety of system clock - * sources and speeds. A LED is used to visually indicate the current clock - * speed as the source is switched. - * - * \section pmc_basic_use_case_setup Setup - * - * \subsection pmc_basic_use_case_setup_prereq Prerequisites - * -# \ref gpio_group "General Purpose I/O Management (gpio)" - * - * \subsection pmc_basic_use_case_setup_code Code - * The following function needs to be added to the user application, to flash a - * board LED a variable number of times at a rate given in CPU ticks. - * - * \code - #define FLASH_TICK_COUNT 0x00012345 - - void flash_led(uint32_t tick_count, uint8_t flash_count) - { - SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; - SysTick->LOAD = tick_count; - - while (flash_count--) - { - gpio_toggle_pin(LED0_GPIO); - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); - gpio_toggle_pin(LED0_GPIO); - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); - } - } -\endcode - * - * \section pmc_basic_use_case_usage Use case - * - * \subsection pmc_basic_use_case_usage_code Example code - * Add to application C-file: - * \code - for (;;) - { - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); - flash_led(FLASH_TICK_COUNT, 5); - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); - flash_led(FLASH_TICK_COUNT, 5); - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); - flash_led(FLASH_TICK_COUNT, 5); - pmc_switch_mainck_to_xtal(0); - flash_led(FLASH_TICK_COUNT, 5); - } -\endcode - * - * \subsection pmc_basic_use_case_usage_flow Workflow - * -# Wrap the code in an infinite loop: - * \code - for (;;) -\endcode - * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash - * a LED on the board several times: - * \code - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); - flash_led(FLASH_TICK_COUNT, 5); -\endcode - * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash - * a LED on the board several times: - * \code - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); - flash_led(FLASH_TICK_COUNT, 5); -\endcode - * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash - * a LED on the board several times: - * \code - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); - flash_led(FLASH_TICK_COUNT, 5); -\endcode - * -# Switch the Master CPU frequency to the external crystal oscillator, flash - * a LED on the board several times: - * \code - pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US); - flash_led(FLASH_TICK_COUNT, 5); -\endcode - * - * \section pmc_use_case_2 Use case #2 - Configure Programmable Clocks - * In this use case, the PMC module is configured to start the Slow Clock from - * an attached 32KHz crystal, and start one of the Programmable Clock modules - * sourced from the Slow Clock divided down with a prescale factor of 64. - * - * \section pmc_use_case_2_setup Setup - * - * \subsection pmc_use_case_2_setup_prereq Prerequisites - * -# \ref pio_group "Parallel Input/Output Controller (pio)" - * - * \subsection pmc_use_case_2_setup_code Code - * The following code must be added to the user application: - * \code - pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); -\endcode - * - * \subsection pmc_use_case_2_setup_code_workflow Workflow - * -# Configure the PCK1 pin to output on a specific port pin (in this case, - * PIOA pin 17) of the microcontroller. - * \code - pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); -\endcode - * \note The peripheral selection and pin will vary according to your selected - * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O - * Lines" of your device's datasheet. - * - * \section pmc_use_case_2_usage Use case - * The generated PCK1 clock output can be viewed on an oscilloscope attached to - * the correct pin of the microcontroller. - * - * \subsection pmc_use_case_2_usage_code Example code - * Add to application C-file: - * \code - pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); - pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); - pmc_enable_pck(PMC_PCK_1); - - for (;;) - { - // Do Nothing - } -\endcode - * - * \subsection pmc_use_case_2_usage_flow Workflow - * -# Switch the Slow Clock source input to an external 32KHz crystal: - * \code - pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); -\endcode - * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock, - * with a prescaler of 64: - * \code - pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); -\endcode - * -# Enable Programmable Clock module PCK1: - * \code - pmc_enable_pck(PMC_PCK_1); -\endcode - * -# Enter an infinite loop: - * \code - for (;;) - { - // Do Nothing - } -\endcode - */ - -#endif /* PMC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c deleted file mode 100644 index 0e79bf2d729..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c +++ /dev/null @@ -1,389 +0,0 @@ -/** - * \file - * - * \brief Sleep mode access - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include "mbed_power_mgmt.h" - -/* SAM3 and SAM4 series */ -#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ - SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAMS70 || SAME70) -# include "pmc.h" -# include "board.h" - -/* Checking board configuration of main clock xtal statup time */ -#if !defined(BOARD_OSC_STARTUP_US) -# warning The board main clock xtal statup time has not been defined. Using default settings. -# define BOARD_OSC_STARTUP_US (15625UL) -#endif - -#if !defined(EFC0) -# define EFC0 EFC -#endif - -/** - * Save clock settings and shutdown PLLs - */ -__always_inline static void pmc_save_clock_settings( - uint32_t *p_osc_setting, - uint32_t *p_pll0_setting, - uint32_t *p_pll1_setting, - uint32_t *p_mck_setting, - uint32_t *p_fmr_setting, -#if defined(EFC1) - uint32_t *p_fmr_setting1, -#endif - const bool disable_xtal) -{ - uint32_t mor = PMC->CKGR_MOR; - uint32_t mckr = PMC->PMC_MCKR; - uint32_t fmr = EFC0->EEFC_FMR; -# if defined(EFC1) - uint32_t fmr1 = EFC1->EEFC_FMR; -# endif - - if (p_osc_setting) { - *p_osc_setting = mor; - } - if (p_pll0_setting) { - *p_pll0_setting = PMC->CKGR_PLLAR; - } - if (p_pll1_setting) { -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) - *p_pll1_setting = PMC->CKGR_PLLBR; -#elif (SAM3U || SAM3XA) - *p_pll1_setting = PMC->CKGR_UCKR; -#else - *p_pll1_setting = 0; -#endif - } - if (p_mck_setting) { - *p_mck_setting = mckr; - } - if (p_fmr_setting) { - *p_fmr_setting = fmr; - } -#if defined(EFC1) - if (p_fmr_setting1) { - *p_fmr_setting1 = fmr1; - } -#endif - - /* Enable FAST RC */ - PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor | CKGR_MOR_MOSCRCEN; - /* if MCK source is PLL, switch to mainck */ - if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) { - /* MCK -> MAINCK */ - mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK; - PMC->PMC_MCKR = mckr; - while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); - } - /* MCK prescale -> 1 */ - if (mckr & PMC_MCKR_PRES_Msk) { - mckr = (mckr & (~PMC_MCKR_PRES_Msk)); - PMC->PMC_MCKR = mckr; - while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); - } - /* Disable PLLs */ - pmc_disable_pllack(); -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) - pmc_disable_pllbck(); -#elif (SAM3U || SAM3XA) - pmc_disable_upll_clock(); -#endif - - /* Prepare for entering WAIT mode */ - /* Wait fast RC ready */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); - - /* Switch mainck to FAST RC */ -#if SAMG - /** - * For the sleepwalking feature, we need an accurate RC clock. Only 24M and - * 16M are trimmed in production. Here we select the 24M. - * And so wait state need to be 1. - */ - EFC0->EEFC_FMR = (fmr & (~EEFC_FMR_FWS_Msk)) | EEFC_FMR_FWS(1); - - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_MOSCRCF_24_MHz | - CKGR_MOR_KEY_PASSWD; -#else - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | - CKGR_MOR_KEY_PASSWD; -#endif - while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); - -#if (!SAMG) - /* FWS update */ - EFC0->EEFC_FMR = fmr & (~EEFC_FMR_FWS_Msk); -#if defined(EFC1) - EFC1->EEFC_FMR = fmr1 & (~EEFC_FMR_FWS_Msk); -#endif -#endif - - /* Disable XTALs */ - if (disable_xtal) { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | - CKGR_MOR_KEY_PASSWD; - } -} - -/** - * Restore clock settings - */ -__always_inline static void pmc_restore_clock_setting( - const uint32_t osc_setting, - const uint32_t pll0_setting, - const uint32_t pll1_setting, - const uint32_t mck_setting, - const uint32_t fmr_setting -#if defined(EFC1) - , const uint32_t fmr_setting1 -#endif -) -{ - uint32_t mckr; - uint32_t pll_sr = 0; - - /* Switch mainck to external xtal */ - if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) { - /* Bypass mode */ - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | - CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | - CKGR_MOR_MOSCSEL; - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & - ~CKGR_MOR_MOSCRCF_Msk) - | CKGR_MOR_KEY_PASSWD; - } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) { - /* Enable External XTAL */ - if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN)) { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | - CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN; - /* Wait the Xtal to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); - } - /* Select External XTAL */ - if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) { - PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; - while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); - } - /* Disable Fast RC */ - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & - ~CKGR_MOR_MOSCRCF_Msk) - | CKGR_MOR_KEY_PASSWD; - } - - if (pll0_setting & CKGR_PLLAR_MULA_Msk) { -#if (SAM4C || SAM4CM || SAMG || SAM4CP) - PMC->CKGR_PLLAR = pll0_setting; -#else - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting; -#endif - pll_sr |= PMC_SR_LOCKA; - } -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) - if (pll1_setting & CKGR_PLLBR_MULB_Msk) { - PMC->CKGR_PLLBR = pll1_setting; - pll_sr |= PMC_SR_LOCKB; - } -#elif (SAM3U || SAM3XA) - if (pll1_setting & CKGR_UCKR_UPLLEN) { - PMC->CKGR_UCKR = pll1_setting; - pll_sr |= PMC_SR_LOCKU; - } -#else - UNUSED(pll1_setting); -#endif - /* Wait MCK source ready */ - switch(mck_setting & PMC_MCKR_CSS_Msk) { - case PMC_MCKR_CSS_PLLA_CLK: - while (!(PMC->PMC_SR & PMC_SR_LOCKA)); - break; -#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) - case PMC_MCKR_CSS_PLLB_CLK: - while (!(PMC->PMC_SR & PMC_SR_LOCKB)); - break; -#elif (SAM3U || SAM3XA) - case PMC_MCKR_CSS_UPLL_CLK: - while (!(PMC->PMC_SR & PMC_SR_LOCKU)); - break; -#endif - } - - /* Switch to faster clock */ - mckr = PMC->PMC_MCKR; - - /* Set PRES */ - PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk) - | (mck_setting & PMC_MCKR_PRES_Msk); - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); - - /* Restore flash wait states */ - EFC0->EEFC_FMR = fmr_setting; -#if defined(EFC1) - EFC1->EEFC_FMR = fmr_setting1; -#endif - - /* Set CSS and others */ - PMC->PMC_MCKR = mck_setting; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); - - /* Waiting all restored PLLs ready */ - while (!(PMC->PMC_SR & pll_sr)); -} - -/** If clocks are switched for some sleep mode */ -static volatile bool b_is_sleep_clock_used = false; -/** Callback invoked once when clocks are restored */ -static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL; - -void pmc_sleep(int sleep_mode) -{ - switch (sleep_mode) { -#if (!(SAMG51 || SAMG53 || SAMG54)) - case SAM_PM_SMODE_SLEEP_WFI: - case SAM_PM_SMODE_SLEEP_WFE: -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70) - SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; - cpu_irq_enable(); - __WFI(); - break; -#else - PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM; - SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; - cpu_irq_enable(); - if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI) - __WFI(); - else - __WFE(); - break; -#endif -#endif - - case SAM_PM_SMODE_WAIT_FAST: - case SAM_PM_SMODE_WAIT: { - uint32_t mor, pllr0, pllr1, mckr; - uint32_t fmr; -#if defined(EFC1) - uint32_t fmr1; -#endif -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70) - (sleep_mode == SAM_PM_SMODE_WAIT_FAST) ? - pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_STANDBY) : - pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN); -#endif - cpu_irq_disable(); - b_is_sleep_clock_used = true; - -#if (SAM4C || SAM4CM || SAM4CP) - /* Backup the sub-system 1 status and stop sub-system 1 */ - uint32_t cpclk_backup = PMC->PMC_SCSR & - (PMC_SCSR_CPCK | PMC_SCSR_CPBMCK); - PMC->PMC_SCDR = cpclk_backup | PMC_SCDR_CPKEY_PASSWD; -#endif - pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr, &fmr, -#if defined(EFC1) - &fmr1, -#endif - (sleep_mode == SAM_PM_SMODE_WAIT)); - - /* Enter wait mode */ - cpu_irq_enable(); - - pmc_enable_waitmode(); - - cpu_irq_disable(); - pmc_restore_clock_setting(mor, pllr0, pllr1, mckr, fmr -#if defined(EFC1) - , fmr1 -#endif - ); - -#if (SAM4C || SAM4CM || SAM4CP) - /* Restore the sub-system 1 */ - PMC->PMC_SCER = cpclk_backup | PMC_SCER_CPKEY_PASSWD; -#endif - b_is_sleep_clock_used = false; - if (callback_clocks_restored) { - callback_clocks_restored(); - callback_clocks_restored = NULL; - } - cpu_irq_enable(); - - break; - } -#if (!(SAMG51 || SAMG53 || SAMG54)) - case SAM_PM_SMODE_BACKUP: - SCB->SCR |= SCR_SLEEPDEEP; -#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70) - SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; - cpu_irq_enable(); - __WFI() ; -#else - cpu_irq_enable(); - __WFE() ; -#endif - break; -#endif - } -} - -bool pmc_is_wakeup_clocks_restored(void) -{ - return !b_is_sleep_clock_used; -} - -void pmc_wait_wakeup_clocks_restore( - pmc_callback_wakeup_clocks_restored_t callback) -{ - if (b_is_sleep_clock_used) { - cpu_irq_disable(); - callback_clocks_restored = callback; - } else if (callback) { - callback(); - } -} - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.h deleted file mode 100644 index 06b9eb6737a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.h +++ /dev/null @@ -1,133 +0,0 @@ -/** - * \file - * - * \brief Sleep mode access - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SLEEP_H -#define SLEEP_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * \defgroup sleep_group Power Manager (PM) - * - * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr - * service. - * - * \note To minimize the code overhead, these functions do not feature - * interrupt-protected access since they are likely to be called inside - * interrupt handlers or in applications where such protection is not - * necessary. If such protection is needed, it must be ensured by the calling - * code. - * - * @{ - */ - -#if defined(__DOXYGEN__) -/** - * \brief Sets the MCU in the specified sleep mode - * \param sleep_mode Sleep mode to set. - */ -#endif -/* SAM3 and SAM4 series */ -#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ - SAM4CM || SAM4CP || SAMG || SAMV71 || SAME70) - -#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ - SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAME70) -# define SAM_PM_SMODE_ACTIVE 0 /**< Active */ -# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */ -# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */ -# define SAM_PM_SMODE_WAIT_FAST 3 /**< Wait Mode, startup fast (in 3ms) */ -# define SAM_PM_SMODE_WAIT 4 /**< Wait Mode */ -# define SAM_PM_SMODE_BACKUP 5 /**< Backup Mode */ -#else -# define SAM_PM_SMODE_ACTIVE 0 /**< Active */ -# define SAM_PM_SMODE_WAIT_FAST 1 /**< Wait Mode, startup fast (in 3ms) */ -# define SAM_PM_SMODE_WAIT 2 /**< Wait Mode */ -#endif - -/** (SCR) Sleep deep bit */ -#define SCR_SLEEPDEEP (0x1 << 2) - -/** - * Clocks restored callback function type. - * Registered by routine pmc_wait_wakeup_clocks_restore() - * Callback called when all clocks are restored. - */ -typedef void (*pmc_callback_wakeup_clocks_restored_t) (void); - -/** - * Enter sleep mode - * \param sleep_mode Sleep mode to enter - */ -void pmc_sleep(int sleep_mode); - -/** - * Check if clocks are restored after wakeup - * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC. - * After wakeup clocks should be restored, before that some of the - * ISR should not be served, otherwise there may be timing or clock issue.) - */ -bool pmc_is_wakeup_clocks_restored(void); - -/** - * \return true if start waiting - */ -void pmc_wait_wakeup_clocks_restore( - pmc_callback_wakeup_clocks_restored_t callback); - -#endif - -//! @} - -#ifdef __cplusplus -} -#endif - -#endif /* SLEEP_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtc/rtc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtc/rtc.c deleted file mode 100644 index 087a2cce9cd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtc/rtc.c +++ /dev/null @@ -1,904 +0,0 @@ -/** - * \file - * - * \brief Real-Time Clock (RTC) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "rtc.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \defgroup sam_drivers_rtc_group Real-Time Clock (RTC) - * - * See \ref sam_rtc_quickstart. - * - * The RTC provides a full binary-coded decimal (BCD) clock that includes - * century (19/20), year (with leap years), month, date, day, hour, minute - * and second. - * - * @{ - */ - - /* RTC Write Protect Key "RTC" in ASCII */ -#define RTC_WP_KEY (0x525443) - - /* The BCD code shift value */ -#define BCD_SHIFT 4 - - /* The BCD code mask value */ -#define BCD_MASK 0xfu - - /* The BCD mul/div factor value */ -#define BCD_FACTOR 10 - - /** - * \brief Set the RTC hour mode. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_mode 1 for 12-hour mode, 0 for 24-hour mode. - */ - void rtc_set_hour_mode(Rtc *p_rtc, uint32_t ul_mode) -{ - if (ul_mode) { - p_rtc->RTC_MR |= RTC_MR_HRMOD; - } else { - p_rtc->RTC_MR &= (~RTC_MR_HRMOD); - } -} - -/** - * \brief Get the RTC hour mode. - * - * \param p_rtc Pointer to an RTC instance. - * - * \return 1 for 12-hour mode, 0 for 24-hour mode. - */ -uint32_t rtc_get_hour_mode(Rtc *p_rtc) -{ - uint32_t ul_temp = p_rtc->RTC_MR; - - if (ul_temp & RTC_MR_HRMOD) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Enable RTC interrupts. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_sources Interrupts to be enabled. - */ -void rtc_enable_interrupt(Rtc *p_rtc, uint32_t ul_sources) -{ - p_rtc->RTC_IER = ul_sources; -} - -/** - * \brief Disable RTC interrupts. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_sources Interrupts to be disabled. - */ -void rtc_disable_interrupt(Rtc *p_rtc, uint32_t ul_sources) -{ - p_rtc->RTC_IDR = ul_sources; -} - -/** - * \brief Read RTC interrupt mask. - * - * \param p_rtc Pointer to an RTC instance. - * - * \return The interrupt mask value. - */ -uint32_t rtc_get_interrupt_mask(Rtc *p_rtc) -{ - return p_rtc->RTC_IMR; -} - -/** - * \brief Get the RTC time value. - * - * \param p_rtc Pointer to an RTC instance. - * \param pul_hour Current hour, 24-hour mode. - * \param pul_minute Current minute. - * \param pul_second Current second. - */ -void rtc_get_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute, - uint32_t *pul_second) -{ - uint32_t ul_time; - uint32_t ul_temp; - - /* Get the current RTC time (multiple reads are necessary to insure a stable value). */ - ul_time = p_rtc->RTC_TIMR; - while (ul_time != p_rtc->RTC_TIMR) { - ul_time = p_rtc->RTC_TIMR; - } - - /* Hour */ - if (pul_hour) { - ul_temp = (ul_time & RTC_TIMR_HOUR_Msk) >> RTC_TIMR_HOUR_Pos; - *pul_hour = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - - if ((ul_time & RTC_TIMR_AMPM) == RTC_TIMR_AMPM) { - *pul_hour += 12; - } - } - - /* Minute */ - if (pul_minute) { - ul_temp = (ul_time & RTC_TIMR_MIN_Msk) >> RTC_TIMR_MIN_Pos; - *pul_minute = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } - - /* Second */ - if (pul_second) { - ul_temp = (ul_time & RTC_TIMR_SEC_Msk) >> RTC_TIMR_SEC_Pos; - *pul_second = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } -} - -/** - * \brief Set the RTC time value. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_hour Current hour, 24-hour mode. - * \param ul_minute Current minute. - * \param ul_second Current second. - * - * \return 0 for OK, else invalid setting. - */ -uint32_t rtc_set_time(Rtc *p_rtc, uint32_t ul_hour, uint32_t ul_minute, - uint32_t ul_second) -{ - uint32_t ul_time = 0; - - /* If 12-hour mode, set AMPM bit */ - if ((p_rtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) { - if (ul_hour > 12) { - ul_hour -= 12; - ul_time |= RTC_TIMR_AMPM; - } - } - - /* Hour */ - ul_time |= ((ul_hour / BCD_FACTOR) << (RTC_TIMR_HOUR_Pos + BCD_SHIFT)) | - ((ul_hour % BCD_FACTOR) << RTC_TIMR_HOUR_Pos); - - /* Minute */ - ul_time |= ((ul_minute / BCD_FACTOR) << (RTC_TIMR_MIN_Pos + BCD_SHIFT)) | - ((ul_minute % BCD_FACTOR) << RTC_TIMR_MIN_Pos); - - /* Second */ - ul_time |= ((ul_second / BCD_FACTOR) << (RTC_TIMR_SEC_Pos + BCD_SHIFT)) | - ((ul_second % BCD_FACTOR) << RTC_TIMR_SEC_Pos); - - /* Update time register. Check the spec for the flow. */ - p_rtc->RTC_CR |= RTC_CR_UPDTIM; - while ((p_rtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD); - p_rtc->RTC_SCCR = RTC_SCCR_ACKCLR; - p_rtc->RTC_TIMR = ul_time; - p_rtc->RTC_CR &= (~RTC_CR_UPDTIM); - p_rtc->RTC_SCCR |= RTC_SCCR_SECCLR; - - return (p_rtc->RTC_VER & RTC_VER_NVTIM); -} - -/** - * \brief Set the RTC alarm time value. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_hour_flag 1 for setting, 0 for not setting. - * \param ul_hour Alarm hour value, 24-hour mode. - * \param ul_minute_flag 1 for setting, 0 for not setting. - * \param ul_minute Alarm minute value. - * \param ul_second_flag 1 for setting, 0 for not setting. - * \param ul_second Alarm second value. - * - * \return 0 for OK, else invalid setting. - */ -uint32_t rtc_set_time_alarm(Rtc *p_rtc, - uint32_t ul_hour_flag, uint32_t ul_hour, - uint32_t ul_minute_flag, uint32_t ul_minute, - uint32_t ul_second_flag, uint32_t ul_second) -{ - uint32_t ul_alarm = 0; - - /* Hour alarm setting */ - if (ul_hour_flag) { - /* If 12-hour mode, set AMPM bit */ - if ((p_rtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) { - if (ul_hour > 12) { - ul_hour -= 12; - ul_alarm |= RTC_TIMR_AMPM; - } - } - - ul_alarm |= ((ul_hour / BCD_FACTOR) << (RTC_TIMR_HOUR_Pos + BCD_SHIFT)) | - ((ul_hour % BCD_FACTOR) << RTC_TIMR_HOUR_Pos); - } - - /* Minute alarm setting */ - if (ul_minute_flag) { - ul_alarm |= ((ul_minute / BCD_FACTOR) << (RTC_TIMR_MIN_Pos + BCD_SHIFT)) | - ((ul_minute % BCD_FACTOR) << RTC_TIMR_MIN_Pos); - } - - /* Second alarm setting */ - if (ul_second_flag) { - ul_alarm |= ((ul_second / BCD_FACTOR) << (RTC_TIMR_SEC_Pos + BCD_SHIFT)) | - ((ul_second % BCD_FACTOR) << RTC_TIMR_SEC_Pos); - } - - p_rtc->RTC_TIMALR &= ~(RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN); - p_rtc->RTC_TIMALR = ul_alarm; - p_rtc->RTC_TIMALR |= (RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN); - - return (p_rtc->RTC_VER & RTC_VER_NVTIMALR); -} - -/** - * \brief Get the RTC date value. - * - * \param p_rtc Pointer to an RTC instance. - * \param pul_year Current year. - * \param pul_month Current month. - * \param pul_day Current day. - * \param pul_week Current day in current week. - */ -void rtc_get_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month, - uint32_t *pul_day, uint32_t *pul_week) -{ - uint32_t ul_date; - uint32_t ul_cent; - uint32_t ul_temp; - - /* Get the current date (multiple reads are necessary to insure a stable value). */ - ul_date = p_rtc->RTC_CALR; - while (ul_date != p_rtc->RTC_CALR) { - ul_date = p_rtc->RTC_CALR; - } - - /* Retrieve year */ - if (pul_year) { - ul_temp = (ul_date & RTC_CALR_CENT_Msk) >> RTC_CALR_CENT_Pos; - ul_cent = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - ul_temp = (ul_date & RTC_CALR_YEAR_Msk) >> RTC_CALR_YEAR_Pos; - *pul_year = (ul_cent * BCD_FACTOR * BCD_FACTOR) + - (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } - - /* Retrieve month */ - if (pul_month) { - ul_temp = (ul_date & RTC_CALR_MONTH_Msk) >> RTC_CALR_MONTH_Pos; - *pul_month = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } - - /* Retrieve day */ - if (pul_day) { - ul_temp = (ul_date & RTC_CALR_DATE_Msk) >> RTC_CALR_DATE_Pos; - *pul_day = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } - - /* Retrieve week */ - if (pul_week) { - *pul_week = ((ul_date & RTC_CALR_DAY_Msk) >> RTC_CALR_DAY_Pos); - } -} - -/** - * \brief Set the RTC date. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_year Current year. - * \param ul_month Current month. - * \param ul_day Current day. - * \param ul_week Current day in current week. - * - * \return 0 for OK, else invalid setting. - */ -uint32_t rtc_set_date(Rtc *p_rtc, uint32_t ul_year, uint32_t ul_month, - uint32_t ul_day, uint32_t ul_week) -{ - uint32_t ul_date = 0; - - /* Cent */ - ul_date |= ((ul_year / BCD_FACTOR / BCD_FACTOR / BCD_FACTOR) << - (RTC_CALR_CENT_Pos + BCD_SHIFT) | - ((ul_year / BCD_FACTOR / BCD_FACTOR) % BCD_FACTOR) << RTC_CALR_CENT_Pos); - - /* Year */ - ul_date |= (((ul_year / BCD_FACTOR) % BCD_FACTOR) << - (RTC_CALR_YEAR_Pos + BCD_SHIFT)) | - ((ul_year % BCD_FACTOR) << RTC_CALR_YEAR_Pos); - - /* Month */ - ul_date |= ((ul_month / BCD_FACTOR) << (RTC_CALR_MONTH_Pos + BCD_SHIFT)) | - ((ul_month % BCD_FACTOR) << RTC_CALR_MONTH_Pos); - - /* Week */ - ul_date |= (ul_week << RTC_CALR_DAY_Pos); - - /* Day */ - ul_date |= ((ul_day / BCD_FACTOR) << (RTC_CALR_DATE_Pos + BCD_SHIFT)) | - ((ul_day % BCD_FACTOR) << RTC_CALR_DATE_Pos); - - /* Update calendar register. Check the spec for the flow. */ - p_rtc->RTC_CR |= RTC_CR_UPDCAL; - while ((p_rtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD); - - p_rtc->RTC_SCCR = RTC_SCCR_ACKCLR; - p_rtc->RTC_CALR = ul_date; - p_rtc->RTC_CR &= (~RTC_CR_UPDCAL); - /* Clear SECENV in SCCR */ - p_rtc->RTC_SCCR |= RTC_SCCR_SECCLR; - - return (p_rtc->RTC_VER & RTC_VER_NVCAL); -} - -/** - * \brief Set the RTC alarm date value. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_month_flag 1 for setting, 0 for not setting. - * \param ul_month Alarm month value. - * \param ul_day_flag 1 for setting, 0 for not setting. - * \param ul_day Alarm day value. - * - * \return 0 for OK, else invalid setting. - */ -uint32_t rtc_set_date_alarm(Rtc *p_rtc, - uint32_t ul_month_flag, uint32_t ul_month, - uint32_t ul_day_flag, uint32_t ul_day) -{ - uint32_t ul_alarm = 0; - - /* Month alarm setting */ - if (ul_month_flag) { - ul_alarm |= ((ul_month / BCD_FACTOR) << (RTC_CALR_MONTH_Pos + BCD_SHIFT)) | - ((ul_month % BCD_FACTOR) << RTC_CALR_MONTH_Pos); - } - - /* Day alarm setting */ - if (ul_day_flag) { - ul_alarm |= ((ul_day / BCD_FACTOR) << (RTC_CALR_DATE_Pos + BCD_SHIFT)) | - ((ul_day % BCD_FACTOR) << RTC_CALR_DATE_Pos); - } - - /* Set alarm */ - p_rtc->RTC_CALALR &= ~(RTC_CALALR_MTHEN | RTC_CALALR_DATEEN); - p_rtc->RTC_CALALR = ul_alarm; - p_rtc->RTC_CALALR |= (RTC_CALALR_MTHEN | RTC_CALALR_DATEEN); - - return (p_rtc->RTC_VER & RTC_VER_NVCALALR); -} - -/** - * \brief Clear the RTC time alarm setting. - * - * \param p_rtc Pointer to an RTC instance. - */ -void rtc_clear_time_alarm(Rtc *p_rtc) -{ - p_rtc->RTC_TIMALR = 0; -} - -/** - * \brief Clear the RTC date alarm setting. - * - * \param p_rtc Pointer to an RTC instance. - */ -void rtc_clear_date_alarm(Rtc *p_rtc) -{ - /* Need a valid value without enabling */ - p_rtc->RTC_CALALR = RTC_CALALR_MONTH(0x01) | RTC_CALALR_DATE(0x01); -} - -/** - * \brief Get the RTC status. - * - * \param p_rtc Pointer to an RTC instance. - * - * \return Status of the RTC. - */ -uint32_t rtc_get_status(Rtc *p_rtc) -{ - return (p_rtc->RTC_SR); -} - -/** - * \brief Set the RTC SCCR to clear status bits. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_clear Some flag bits which will be cleared. - */ -void rtc_clear_status(Rtc *p_rtc, uint32_t ul_clear) -{ - p_rtc->RTC_SCCR = ul_clear; -} - -/** - * \brief Get the RTC valid entry. - * - * \param p_rtc Pointer to an RTC instance. - * - * \return 0 for no invalid data, else has contained invalid data. - */ -uint32_t rtc_get_valid_entry(Rtc *p_rtc) -{ - return (p_rtc->RTC_VER); -} - -/** - * \brief Set the RTC time event selection. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_selection Time event selection to be enabled. - */ -void rtc_set_time_event(Rtc *p_rtc, uint32_t ul_selection) -{ - p_rtc->RTC_CR &= ~RTC_CR_TIMEVSEL_Msk; - p_rtc->RTC_CR |= (ul_selection << RTC_CR_TIMEVSEL_Pos) & RTC_CR_TIMEVSEL_Msk; -} - -/** - * \brief Set the RTC calendar event selection. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_selection Calendar event selection to be enabled.. - */ -void rtc_set_calendar_event(Rtc *p_rtc, uint32_t ul_selection) -{ - p_rtc->RTC_CR &= ~RTC_CR_CALEVSEL_Msk; - p_rtc->RTC_CR |= (ul_selection << RTC_CR_CALEVSEL_Pos) & RTC_CR_CALEVSEL_Msk; -} - -#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4N) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM)) -/** - * \brief Set the RTC calendar mode. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_mode 1 for Persian mode,0 for Gregorian mode. - */ -void rtc_set_calendar_mode(Rtc *p_rtc, uint32_t ul_mode) -{ - if (ul_mode) { - p_rtc->RTC_MR |= RTC_MR_PERSIAN; - } else { - p_rtc->RTC_MR &= (~RTC_MR_PERSIAN); - } -} - -/** - * \brief Get the RTC calendar mode. - * - * \param p_rtc Pointer to an RTC instance. - * - * \return 1 for Persian calendar, 0 for Gregorian calendar. - */ -uint32_t rtc_get_calendar_mode(Rtc *p_rtc) -{ - uint32_t ul_temp = p_rtc->RTC_MR; - - if (ul_temp & RTC_MR_PERSIAN) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Set the RTC calibration. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_direction_ppm Positive/negative correction. - * \param ul_correction Correction value. - * \param ul_range_ppm Low/high range correction. - */ -void rtc_set_calibration(Rtc *p_rtc, uint32_t ul_direction_ppm, - uint32_t ul_correction, uint32_t ul_range_ppm) -{ - uint32_t ul_temp; - - ul_temp = p_rtc->RTC_MR; - - if (ul_direction_ppm) { - ul_temp |= RTC_MR_NEGPPM; - } else { - ul_temp &= (~RTC_MR_NEGPPM); - } - - ul_temp |= RTC_MR_CORRECTION(ul_correction); - - if (ul_range_ppm) { - ul_temp |= RTC_MR_HIGHPPM; - } else { - ul_temp &= (~RTC_MR_HIGHPPM); - } - - p_rtc->RTC_MR = ul_temp; -} -#endif - -#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Set the RTC output waveform. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_channel Output channel selection. - * \param ul_value Output source selection value. - */ -void rtc_set_waveform(Rtc *p_rtc, uint32_t ul_channel, uint32_t ul_value) -{ - if (ul_channel == 0) { - switch (ul_value) { - case 0: - p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT0_NO_WAVE; - break; - - case 1: - p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ1HZ; - break; - - case 2: - p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ32HZ; - break; - - case 3: - p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ64HZ; - break; - - case 4: - p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ512HZ; - break; - -#if (!SAMG) - case 5: - p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT0_ALARM_TOGGLE; - break; -#endif - - case 6: - p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT0_ALARM_FLAG; - break; - -#if (!SAMG) - case 7: - p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT0_PROG_PULSE; - break; -#endif - - default: - break; - } - } else { -#if (!SAM4C && !SAM4CP && !SAM4CM) - switch (ul_value) { - case 0: - p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT1_NO_WAVE; - break; - - case 1: - p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ1HZ; - break; - - case 2: - p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ32HZ; - break; - - case 3: - p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ64HZ; - break; - - case 4: - p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ512HZ; - break; - -#if (!SAMG) - case 5: - p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT1_ALARM_TOGGLE; - break; -#endif - - case 6: - p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT1_ALARM_FLAG; - break; - -#if (!SAMG) - case 7: - p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; - p_rtc->RTC_MR |= RTC_MR_OUT1_PROG_PULSE; - break; -#endif - - default: - break; - } -#endif - } -} - -#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Set the pulse output waveform parameters. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_time_high High duration of the output pulse. - * \param ul_period Period of the output pulse. - */ -void rtc_set_pulse_parameter(Rtc *p_rtc, uint32_t ul_time_high, - uint32_t ul_period) -{ - uint32_t ul_temp; - - ul_temp = p_rtc->RTC_MR; - - ul_temp |= (RTC_MR_THIGH_Msk & ((ul_time_high) << RTC_MR_THIGH_Pos)); - ul_temp |= (RTC_MR_TPERIOD_Msk & ((ul_period) << RTC_MR_TPERIOD_Pos)); - - p_rtc->RTC_MR = ul_temp; -} -#endif -#endif - - -#if ((SAM3N) || (SAM3U) || (SAM3XA)) -/** - * \brief Enable or disable write protection of RTC registers. - * - * \param p_rtc Pointer to an RTC instance. - * \param ul_enable 1 to enable, 0 to disable. - */ -void rtc_set_writeprotect(Rtc *p_rtc, uint32_t ul_enable) -{ - if (ul_enable) { - p_rtc->RTC_WPMR = RTC_WPMR_WPKEY(RTC_WP_KEY) | RTC_WPMR_WPEN; - } else { - p_rtc->RTC_WPMR = RTC_WPMR_WPKEY(RTC_WP_KEY); - } -} -#endif /* ((SAM3N) || (SAM3U) || (SAM3XA)) */ - -#if SAM4C || SAM4CP || SAM4CM -/** - * \brief Get the RTC tamper time value. - * - * \note This function should be called before rtc_get_tamper_source() - * function call, Otherwise the tamper time will be cleared. - * - * \param p_rtc Pointer to an RTC instance. - * \param pul_hour Current hour, 24-hour mode. - * \param pul_minute Current minute. - * \param pul_second Current second. - * \param reg_num Current tamper register set number. - */ -void rtc_get_tamper_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute, - uint32_t *pul_second, uint8_t reg_num) -{ - uint32_t ul_time; - uint32_t ul_temp; - - /* Get the current RTC time (multiple reads are to insure a stable value). */ - ul_time = p_rtc->RTC_TS[reg_num].RTC_TSTR; - while (ul_time != p_rtc->RTC_TS[reg_num].RTC_TSTR) { - ul_time = p_rtc->RTC_TS[reg_num].RTC_TSTR; - } - - /* Hour */ - if (pul_hour) { - ul_temp = (ul_time & RTC_TSTR_HOUR_Msk) >> RTC_TSTR_HOUR_Pos; - *pul_hour = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - - if ((ul_time & RTC_TSTR_AMPM) == RTC_TSTR_AMPM) { - *pul_hour += 12; - } - } - - /* Minute */ - if (pul_minute) { - ul_temp = (ul_time & RTC_TSTR_MIN_Msk) >> RTC_TSTR_MIN_Pos; - *pul_minute = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } - - /* Second */ - if (pul_second) { - ul_temp = (ul_time & RTC_TSTR_SEC_Msk) >> RTC_TSTR_SEC_Pos; - *pul_second = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } -} - -/** - * \brief Get the RTC tamper date. - * - * \note This function should be called before rtc_get_tamper_source() - * function call, Otherwise the tamper date will be cleared. - * - * \param p_rtc Pointer to an RTC instance. - * \param pul_year Current year. - * \param pul_month Current month. - * \param pul_day Current day. - * \param pul_week Current day in current week. - * \param reg_num Current tamper register set number. - */ -void rtc_get_tamper_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month, - uint32_t *pul_day, uint32_t *pul_week, uint8_t reg_num) -{ - uint32_t ul_date; - uint32_t ul_cent; - uint32_t ul_temp; - - /* Get the current date (multiple reads are to insure a stable value). */ - ul_date = p_rtc->RTC_TS[reg_num].RTC_TSDR; - while (ul_date != p_rtc->RTC_TS[reg_num].RTC_TSDR) { - ul_date = p_rtc->RTC_TS[reg_num].RTC_TSDR; - } - - /* Retrieve year */ - if (pul_year) { - ul_temp = (ul_date & RTC_TSDR_CENT_Msk) >> RTC_TSDR_CENT_Pos; - ul_cent = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - ul_temp = (ul_date & RTC_TSDR_YEAR_Msk) >> RTC_TSDR_YEAR_Pos; - *pul_year = (ul_cent * BCD_FACTOR * BCD_FACTOR) + - (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } - - /* Retrieve month */ - if (pul_month) { - ul_temp = (ul_date & RTC_TSDR_MONTH_Msk) >> RTC_TSDR_MONTH_Pos; - *pul_month = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } - - /* Retrieve day */ - if (pul_day) { - ul_temp = (ul_date & RTC_TSDR_DATE_Msk) >> RTC_TSDR_DATE_Pos; - *pul_day = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); - } - - /* Retrieve week */ - if (pul_week) { - *pul_week = ((ul_date & RTC_TSDR_DAY_Msk) >> RTC_TSDR_DAY_Pos); - } -} - -/** - * \brief Get the RTC tamper source. - * - * \param p_rtc Pointer to an RTC instance. - * \param reg_num Current tamper register set number. - * - * \return Tamper source. - */ -uint32_t rtc_get_tamper_source(Rtc *p_rtc, uint8_t reg_num) -{ - return (p_rtc->RTC_TS[reg_num].RTC_TSSR & RTC_TSSR_TSRC_Msk) >> - RTC_TSSR_TSRC_Pos; -} - -/** - * \brief Get the RTC tamper event counter. - * - * \note This function should be called before rtc_get_tamper_source() - * function call, Otherwise the tamper event counter will be cleared. - * - * \param p_rtc Pointer to an RTC instance. - * - * \return Tamper event counter - */ -uint32_t rtc_get_tamper_event_counter(Rtc *p_rtc) -{ - return (p_rtc->RTC_TS[0].RTC_TSTR & RTC_TSTR_TEVCNT_Msk) >> - RTC_TSTR_TEVCNT_Pos; -} - -/** - * \brief Check the system is in backup mode when RTC tamper event happen. - * - * \note This function should be called before rtc_get_tamper_source() - * function call, Otherwise the flag indicates tamper occur in backup - * mode will be cleared. - * - * \param p_rtc Pointer to an RTC instance. - * \param reg_num Current tamper register set number. - * - * \return True - The system is in backup mode when the tamper event occurs. - * Flase - The system is different from backup mode. - */ -bool rtc_is_tamper_occur_in_backup_mode(Rtc *p_rtc, uint8_t reg_num) -{ - if(p_rtc->RTC_TS[reg_num].RTC_TSTR & RTC_TSTR_BACKUP) { - return true; - } else { - return false; - } -} -#endif - -#if (SAMG55) -/** - * \brief Get the RTC milliseconds value. - * - * \param p_rtc Pointer to an RTC instance. - * - * \return Number of 1/1024 seconds elapsed within one second. - */ -uint32_t rtc_get_milliseconds(Rtc *p_rtc) -{ - return (p_rtc->RTC_MSR) & RTC_MSR_MS_Msk; -} -#endif - - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtc/rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtc/rtc.h deleted file mode 100644 index faea68a478a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtc/rtc.h +++ /dev/null @@ -1,192 +0,0 @@ -/** - * \file - * - * \brief Real-Time Clock (RTC) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef RTC_H_INCLUDED -#define RTC_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - void rtc_set_hour_mode(Rtc *p_rtc, uint32_t ul_mode); - uint32_t rtc_get_hour_mode(Rtc *p_rtc); - void rtc_enable_interrupt(Rtc *p_rtc, uint32_t ul_sources); - void rtc_disable_interrupt(Rtc *p_rtc, uint32_t ul_sources); - uint32_t rtc_get_interrupt_mask(Rtc *p_rtc); - void rtc_get_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute, - uint32_t *pul_second); - uint32_t rtc_set_time(Rtc *p_rtc, uint32_t ul_hour, uint32_t ul_minute, - uint32_t ul_second); - uint32_t rtc_set_time_alarm(Rtc *p_rtc, - uint32_t ul_hour_flag, uint32_t ul_hour, - uint32_t ul_minute_flag, uint32_t ul_minute, - uint32_t ul_second_flag, uint32_t ul_second); - void rtc_get_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month, - uint32_t *pul_day, uint32_t *pul_week); - uint32_t rtc_set_date(Rtc *p_rtc, uint32_t ul_year, uint32_t ul_month, - uint32_t ul_day, uint32_t ul_week); - uint32_t rtc_set_date_alarm(Rtc *p_rtc, - uint32_t ul_month_flag, uint32_t ul_month, - uint32_t ul_day_flag, uint32_t ul_day); - void rtc_clear_time_alarm(Rtc *p_rtc); - void rtc_clear_date_alarm(Rtc *p_rtc); - uint32_t rtc_get_status(Rtc *p_rtc); - void rtc_clear_status(Rtc *p_rtc, uint32_t ul_clear); - uint32_t rtc_get_valid_entry(Rtc *p_rtc); - void rtc_set_time_event(Rtc *p_rtc, uint32_t ul_selection); - void rtc_set_calendar_event(Rtc *p_rtc, uint32_t ul_selection); - -#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4N) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM)) - void rtc_set_calendar_mode(Rtc *p_rtc, uint32_t ul_mode); - uint32_t rtc_get_calendar_mode(Rtc *p_rtc); - void rtc_set_calibration(Rtc *p_rtc, uint32_t ul_direction_ppm, - uint32_t ul_correction, uint32_t ul_range_ppm); -#endif - -#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70) - void rtc_set_waveform(Rtc *p_rtc, uint32_t ul_channel, uint32_t ul_value); -#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C)|| (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70) - void rtc_set_pulse_parameter(Rtc *p_rtc, uint32_t ul_time_high, - uint32_t ul_period); -#endif -#endif - -#if ((SAM3N) || (SAM3U) || (SAM3XA)) - void rtc_set_writeprotect(Rtc *p_rtc, uint32_t ul_enable); -#endif /* ((SAM3N) || (SAM3U) || (SAM3XA)) */ - -#if ((SAM4C) || (SAM4CP) || (SAM4CM)) - void rtc_get_tamper_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute, - uint32_t *pul_second, uint8_t reg_num); - void rtc_get_tamper_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month, - uint32_t *pul_day, uint32_t *pul_week, uint8_t reg_num); - uint32_t rtc_get_tamper_source(Rtc *p_rtc, uint8_t reg_num); - uint32_t rtc_get_tamper_event_counter(Rtc *p_rtc); - bool rtc_is_tamper_occur_in_backup_mode(Rtc *p_rtc, uint8_t reg_num); -#endif - -#if (SAMG55) - uint32_t rtc_get_milliseconds(Rtc *p_rtc); -#endif - - /** - * \page sam_rtc_quickstart Quickstart guide for SAM RTC driver - * - * This is the quickstart guide for the \ref rtc_group "SAM RTC driver", - * with step-by-step instructions on how to configure and use the driver in a - * selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section rtc_basic_use_case Basic use case - * In this basic use case, the RTC module is using 32kHz external crystal and - * configured for 24-hour mode. It will read the current date and time. - * - * \subsection sam_rtc_quickstart_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (Sysclock)" - * - * \section rtc_basic_use_case_setup Setup steps - * \subsection rtc_basic_use_case_setup_code Example code - * Add to application C-file: - * \code - void rtc_setup(void) - { - pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); - - while (!pmc_osc_is_ready_32kxtal()); - - rtc_set_hour_mode(RTC, 0); - } - \endcode - * - * \subsection rtc_basic_use_case_setup_flow Workflow - * - \note Please make sure the external 32kHz crystal is available. - * -# Enable the External 32K crystal : - * - \code pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); \endcode - * -# Wait for 32K crystal ready: - * - \code while (!pmc_osc_is_ready_32kxtal()); \endcode - * -# Set default RTC configuration, 24-hour mode . - * - \code rtc_set_hour_mode(RTC, 0); \endcode - * - * \section rtc_basic_use_case_usage Usage steps - * \subsection rtc_basic_use_case_usage_code Example code - * Add to, e.g., main loop in application C-file: - * \code - uint32_t hour, minute, second; - uint32_t year, month, day, week; - - rtc_get_time(RTC, &hour, &minute, &second); - rtc_get_date(RTC, &year, &month, &day, &week); - \endcode - * - * \subsection rtc_basic_use_case_usage_flow Workflow - * -# Start Define the variables for the date and time: - * - \code uint32_t hour, minute, second; \endcode - * - \code uint32_t year, month, day, week; \endcode - * -# Read current time: - * - \code rtc_get_time(RTC, &hour, &minute, &second); \endcode - * -# Read current date: - * - \code rtc_get_date(RTC, &year, &month, &day, &week); \endcode - * - */ - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* RTC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtt/rtt.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtt/rtt.c deleted file mode 100644 index ea4272aaed0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtt/rtt.c +++ /dev/null @@ -1,260 +0,0 @@ -/** - * \file - * - * \brief Real-time Timer (RTT) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "rtt.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \defgroup sam_drivers_rtt_group Real-time Timer (RTT) - * - * The Real-time Timer is built around a 32-bit counter used to count - * roll-over events of the programmable 16-bit prescaler, which enables - * counting elapsed seconds from a 32 kHz slow clock source. - * This is a driver for configuration and use of the RTT peripheral. - * - * @{ - */ - - /* - * In follow series chip, the bit RTC1HZ and RTTDIS in RTT_MR are write only. - * So we use a variable to record status of these bits. - */ -#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - static uint32_t g_wobits_in_rtt_mr = 0; -#endif - - /** - * \brief Initialize the given RTT. - * - * \note This function restarts the real-time timer. If w_prescaler is equal to zero, - * the prescaler period is equal to 2^16 * SCLK period. If not, the prescaler period - * is equal to us_prescaler * SCLK period. - * - * \param p_rtt Pointer to an RTT instance. - * \param us_prescaler Prescaler value for the RTT. - * - * \return 0 if successful. - */ - uint32_t rtt_init(Rtt *p_rtt, uint16_t us_prescaler) -{ -#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - p_rtt->RTT_MR = (us_prescaler | RTT_MR_RTTRST | g_wobits_in_rtt_mr); -#else - p_rtt->RTT_MR = (us_prescaler | RTT_MR_RTTRST); -#endif - return 0; -} - -#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Select RTT counter source. - * - * \param p_rtt Pointer to an RTT instance. - * \param is_rtc_sel RTC 1Hz Clock Selection. - */ -void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel) -{ - if(is_rtc_sel) { - g_wobits_in_rtt_mr |= RTT_MR_RTC1HZ; - p_rtt->RTT_MR |= g_wobits_in_rtt_mr; - } else { - g_wobits_in_rtt_mr &= ~RTT_MR_RTC1HZ; - p_rtt->RTT_MR |= g_wobits_in_rtt_mr; - } -} - -/** - * \brief Enable RTT. - * - * \param p_rtt Pointer to an RTT instance. - */ -void rtt_enable(Rtt *p_rtt) -{ - g_wobits_in_rtt_mr &= ~RTT_MR_RTTDIS; - p_rtt->RTT_MR |= g_wobits_in_rtt_mr; -} -/** - * \brief Disable RTT. - * - * \param p_rtt Pointer to an RTT instance. - */ -void rtt_disable(Rtt *p_rtt) -{ - g_wobits_in_rtt_mr |= RTT_MR_RTTDIS; - p_rtt->RTT_MR |= g_wobits_in_rtt_mr; -} -#elif (SAMG53 || SAMG54 || SAMG55) -void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel) -{ - if(is_rtc_sel) { - p_rtt->RTT_MR |= RTT_MR_RTC1HZ; - } else { - p_rtt->RTT_MR &= ~RTT_MR_RTC1HZ; - } -} - -void rtt_enable(Rtt *p_rtt) -{ - p_rtt->RTT_MR &= ~RTT_MR_RTTDIS; -} -/** - * \brief Disable RTT. - * - * \param p_rtt Pointer to an RTT instance. - */ -void rtt_disable(Rtt *p_rtt) -{ - p_rtt->RTT_MR |= RTT_MR_RTTDIS; -} -#endif - -/** - * \brief Enable RTT interrupts. - * - * \param p_rtt Pointer to an RTT instance. - * \param ul_sources Interrupts to be enabled. - */ -void rtt_enable_interrupt(Rtt *p_rtt, uint32_t ul_sources) -{ - uint32_t temp; - - temp = p_rtt->RTT_MR; - temp |= ul_sources; -#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - temp |= g_wobits_in_rtt_mr; -#endif - p_rtt->RTT_MR = temp; -} - -/** - * \brief Disable RTT interrupts. - * - * \param p_rtt Pointer to an RTT instance. - * \param ul_sources Interrupts to be disabled. - */ -void rtt_disable_interrupt(Rtt *p_rtt, uint32_t ul_sources) -{ - uint32_t temp = 0; - - temp = p_rtt->RTT_MR; - temp &= (~ul_sources); -#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - temp |= g_wobits_in_rtt_mr; -#endif - p_rtt->RTT_MR = temp; -} - -/** - * \brief Read the current value of the RTT timer value. - * - * \param p_rtt Pointer to an RTT instance. - * - * \return The current Real-time Timer value. - */ -uint32_t rtt_read_timer_value(Rtt *p_rtt) -{ - return p_rtt->RTT_VR; -} - -/** - * \brief Get the status register value of the given RTT. - * - * \param p_rtt Pointer to an RTT instance. - * - * \return The Real-time Timer status. - */ -uint32_t rtt_get_status(Rtt *p_rtt) -{ - return p_rtt->RTT_SR; -} - -/** - * \brief Configure the RTT to generate an alarm at the given time. - * - * \param p_rtt Pointer to an RTT instance. - * \param ul_alarm_time Alarm time. - * - * \retval 0 Configuration is done. - * \retval 1 Parameter error. - */ -uint32_t rtt_write_alarm_time(Rtt *p_rtt, uint32_t ul_alarm_time) -{ - uint32_t flag; - - if (ul_alarm_time == 0) { - return 1; - } - - flag = p_rtt->RTT_MR & RTT_MR_ALMIEN; - - rtt_disable_interrupt(RTT, RTT_MR_ALMIEN); - - /* Alarm time = ALMV + 1 */ - p_rtt->RTT_AR = ul_alarm_time - 1; - - if (flag) { - rtt_enable_interrupt(RTT, RTT_MR_ALMIEN); - } - - return 0; -} - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtt/rtt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtt/rtt.h deleted file mode 100644 index 2d178ad9c1f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtt/rtt.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief Real-time Timer (RTT) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef RTT_H_INCLUDED -#define RTT_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - uint32_t rtt_init(Rtt *p_rtt, uint16_t us_prescaler); -#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel); - void rtt_enable(Rtt *p_rtt); - void rtt_disable(Rtt *p_rtt); -#endif - void rtt_enable_interrupt(Rtt *p_rtt, uint32_t ul_sources); - void rtt_disable_interrupt(Rtt *p_rtt, uint32_t ul_sources); - uint32_t rtt_read_timer_value(Rtt *p_rtt); - uint32_t rtt_get_status(Rtt *p_rtt); - uint32_t rtt_write_alarm_time(Rtt *p_rtt, uint32_t ul_alarm_time); - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* RTT_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.c deleted file mode 100644 index 869c54159ff..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.c +++ /dev/null @@ -1,453 +0,0 @@ -/** - * \file - * - * \brief Serial Peripheral Interface (SPI) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "spi_driver.h" -#include "sysclk.h" -#include "flexcom.h" - -/** - * \defgroup sam_drivers_spi_group Serial Peripheral Interface (SPI) - * - * See \ref sam_spi_quickstart. - * - * The SPI circuit is a synchronous serial data link that provides communication - * with external devices in Master or Slave mode. Connection to Peripheral DMA - * Controller channel capabilities optimizes data transfers. - * - * @{ - */ -#ifndef SPI_WPMR_WPKEY_PASSWD -#define SPI_WPMR_WPKEY_PASSWD SPI_WPMR_WPKEY((uint32_t) 0x535049) -#endif - -/** - * \brief Enable SPI clock. - * - * \param p_spi Pointer to an SPI instance. - */ -void spi_enable_clock(Spi *p_spi) -{ -#if (SAM4S || SAM3S || SAM3N || SAM3U || SAM4E || SAM4N || SAMG51|| SAMG53|| SAMG54) - UNUSED(p_spi); - sysclk_enable_peripheral_clock(ID_SPI); -#elif (SAM3XA || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - if (p_spi == SPI0) { - sysclk_enable_peripheral_clock(ID_SPI0); - } -#ifdef SPI1 - else if (p_spi == SPI1) { - sysclk_enable_peripheral_clock(ID_SPI1); - } -#endif -#elif (SAMG55) - if (p_spi == SPI0) { - sysclk_enable_peripheral_clock(ID_FLEXCOM0); - } -#ifdef SPI1 - else if (p_spi == SPI1) { - sysclk_enable_peripheral_clock(ID_FLEXCOM1); - } -#endif -#ifdef SPI2 - else if (p_spi == SPI2) { - sysclk_enable_peripheral_clock(ID_FLEXCOM2); - } -#endif -#ifdef SPI3 - else if (p_spi == SPI3) { - sysclk_enable_peripheral_clock(ID_FLEXCOM3); - } -#endif -#ifdef SPI4 - else if (p_spi == SPI4) { - sysclk_enable_peripheral_clock(ID_FLEXCOM4); - } -#endif -#ifdef SPI5 - else if (p_spi == SPI5) { - sysclk_enable_peripheral_clock(ID_FLEXCOM5); - } -#endif -#ifdef SPI6 - else if (p_spi == SPI6) { - sysclk_enable_peripheral_clock(ID_FLEXCOM6); - } -#endif -#ifdef SPI7 - else if (p_spi == SPI7) { - sysclk_enable_peripheral_clock(ID_FLEXCOM7); - } -#endif -#elif SAM4L - sysclk_enable_peripheral_clock(p_spi); -#endif -} - -/** - * \brief Disable SPI clock. - * - * \param p_spi Pointer to an SPI instance. - */ -void spi_disable_clock(Spi *p_spi) -{ -#if (SAM4S || SAM3S || SAM3N || SAM3U || SAM4E || SAM4N || SAMG51|| SAMG53|| SAMG54) - UNUSED(p_spi); - sysclk_disable_peripheral_clock(ID_SPI); -#elif (SAM3XA || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) - if (p_spi == SPI0) { - sysclk_disable_peripheral_clock(ID_SPI0); - } -#ifdef SPI1 - else if (p_spi == SPI1) { - sysclk_disable_peripheral_clock(ID_SPI1); - } -#endif -#elif (SAMG55) - if (p_spi == SPI0) { - sysclk_disable_peripheral_clock(ID_FLEXCOM0); - } -#ifdef SPI1 - else if (p_spi == SPI1) { - sysclk_disable_peripheral_clock(ID_FLEXCOM1); - } -#endif -#ifdef SPI2 - else if (p_spi == SPI2) { - sysclk_disable_peripheral_clock(ID_FLEXCOM2); - } -#endif -#ifdef SPI3 - else if (p_spi == SPI3) { - sysclk_disable_peripheral_clock(ID_FLEXCOM3); - } -#endif -#ifdef SPI4 - else if (p_spi == SPI4) { - sysclk_disable_peripheral_clock(ID_FLEXCOM4); - } -#endif -#ifdef SPI5 - else if (p_spi == SPI5) { - sysclk_disable_peripheral_clock(ID_FLEXCOM5); - } -#endif -#ifdef SPI6 - else if (p_spi == SPI6) { - sysclk_disable_peripheral_clock(ID_FLEXCOM6); - } -#endif -#ifdef SPI7 - else if (p_spi == SPI7) { - sysclk_disable_peripheral_clock(ID_FLEXCOM7); - } -#endif -#elif SAM4L - sysclk_disable_peripheral_clock(p_spi); -#endif -} - -/** - * \brief Set Peripheral Chip Select (PCS) value. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_value Peripheral Chip Select value. - * If PCS decode mode is not used, use \ref spi_get_pcs to build - * the value to use. - * On reset the decode mode is not enabled. - * The decode mode can be enabled/disabled by follow functions: - * \ref spi_enable_peripheral_select_decode, - * \ref spi_disable_peripheral_select_decode. - */ -void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value) -{ - p_spi->SPI_MR &= (~SPI_MR_PCS_Msk); - p_spi->SPI_MR |= SPI_MR_PCS(ul_value); -} - -/** - * \brief Set delay between chip selects (in number of MCK clocks). - * If DLYBCS <= 6, 6 MCK clocks will be inserted by default. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_delay Delay between chip selects (in number of MCK clocks). - */ -void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay) -{ - p_spi->SPI_MR &= (~SPI_MR_DLYBCS_Msk); - p_spi->SPI_MR |= SPI_MR_DLYBCS(ul_delay); -} - -/** - * \brief Read the received data and it's peripheral chip select value. - * While SPI works in fixed peripheral select mode, the peripheral chip select - * value is meaningless. - * - * \param p_spi Pointer to an SPI instance. - * \param data Pointer to the location where to store the received data word. - * \param p_pcs Pointer to fill Peripheral Chip Select Value. - * - * \retval SPI_OK on Success. - * \retval SPI_ERROR_TIMEOUT on Time-out. - */ -spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs) -{ - uint32_t timeout = SPI_TIMEOUT; - static uint32_t reg_value; - - while (!(p_spi->SPI_SR & SPI_SR_RDRF)) { - if (!timeout--) { - return SPI_ERROR_TIMEOUT; - } - } - - reg_value = p_spi->SPI_RDR; - if (spi_get_peripheral_select_mode(p_spi)) { - *p_pcs = (uint8_t) ((reg_value & SPI_RDR_PCS_Msk) >> SPI_RDR_PCS_Pos); - } - *us_data = (uint16_t) (reg_value & SPI_RDR_RD_Msk); - - return SPI_OK; -} - -/** - * \brief Write the transmitted data with specified peripheral chip select value. - * - * \param p_spi Pointer to an SPI instance. - * \param us_data The data to transmit. - * \param uc_pcs Peripheral Chip Select Value while SPI works in peripheral select - * mode, otherwise it's meaningless. - * \param uc_last Indicate whether this data is the last one while SPI is working - * in variable peripheral select mode. - * - * \retval SPI_OK on Success. - * \retval SPI_ERROR_TIMEOUT on Time-out. - */ -spi_status_t spi_write(Spi *p_spi, uint16_t us_data, - uint8_t uc_pcs, uint8_t uc_last) -{ - uint32_t timeout = SPI_TIMEOUT; - uint32_t value; - - while (!(p_spi->SPI_SR & SPI_SR_TDRE)) { - if (!timeout--) { - return SPI_ERROR_TIMEOUT; - } - } - - if (spi_get_peripheral_select_mode(p_spi)) { - value = SPI_TDR_TD(us_data) | SPI_TDR_PCS(uc_pcs); - if (uc_last) { - value |= SPI_TDR_LASTXFER; - } - } else { - value = SPI_TDR_TD(us_data); - } - - p_spi->SPI_TDR = value; - - return SPI_OK; -} - -/** - * \brief Set clock default state. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_pcs_ch Peripheral Chip Select channel (0~3). - * \param ul_polarity Default clock state is logical one(high)/zero(low). - */ -void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch, - uint32_t ul_polarity) -{ - if (ul_polarity) { - p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CPOL; - } else { - p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CPOL); - } -} - -/** - * \brief Set Data Capture Phase. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_pcs_ch Peripheral Chip Select channel (0~3). - * \param ul_phase Data capture on the rising/falling edge of clock. - */ -void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase) -{ - if (ul_phase) { - p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_NCPHA; - } else { - p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_NCPHA); - } -} - -/** - * \brief Configure CS behavior for SPI transfer (\ref spi_cs_behavior_t). - * - * \param p_spi Pointer to an SPI instance. - * \param ul_pcs_ch Peripheral Chip Select channel (0~3). - * \param ul_cs_behavior Behavior of the Chip Select after transfer. - */ -void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch, - uint32_t ul_cs_behavior) -{ - if (ul_cs_behavior == SPI_CS_RISE_FORCED) { - p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSAAT); - p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CSNAAT; - } else if (ul_cs_behavior == SPI_CS_RISE_NO_TX) { - p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSAAT); - p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSNAAT); - } else if (ul_cs_behavior == SPI_CS_KEEP_LOW) { - p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CSAAT; - } -} - -/** - * \brief Set number of bits per transfer. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_pcs_ch Peripheral Chip Select channel (0~3). - * \param ul_bits Number of bits (8~16), use the pattern defined - * in the device header file. - */ -void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, - uint32_t ul_bits) -{ - p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_BITS_Msk); - p_spi->SPI_CSR[ul_pcs_ch] |= ul_bits; -} - -/** - * \brief Calculate the baudrate divider. - * - * \param baudrate Baudrate value. - * \param mck SPI module input clock frequency (MCK clock, Hz). - * - * \return Divider or error code. - * \retval > 0 Success. - * \retval < 0 Error. - */ -int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck) -{ - int baud_div = div_ceil(mck, baudrate); - - /* The value of baud_div is from 1 to 255 in the SCBR field. */ - if (baud_div <= 0 || baud_div > 255) { - return -1; - } - - return baud_div; -} - -/** - * \brief Set Serial Clock Baud Rate divider value (SCBR). - * - * \param p_spi Pointer to an SPI instance. - * \param ul_pcs_ch Peripheral Chip Select channel (0~3). - * \param uc_baudrate_divider Baudrate divider from MCK. - */ -void spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch, - uint8_t uc_baudrate_divider) -{ - p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_SCBR_Msk); - p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_SCBR(uc_baudrate_divider); -} - -/** - * \brief Configure timing for SPI transfer. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_pcs_ch Peripheral Chip Select channel (0~3). - * \param uc_dlybs Delay before SPCK (in number of MCK clocks). - * \param uc_dlybct Delay between consecutive transfers (in number of MCK clocks). - */ -void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, - uint8_t uc_dlybs, uint8_t uc_dlybct) -{ - p_spi->SPI_CSR[ul_pcs_ch] &= ~(SPI_CSR_DLYBS_Msk | SPI_CSR_DLYBCT_Msk); - p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_DLYBS(uc_dlybs) - | SPI_CSR_DLYBCT(uc_dlybct); -} - - -/** - * \brief Enable or disable write protection of SPI registers. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_enable 1 to enable, 0 to disable. - */ -void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable) -{ -#if SAM4L - if (ul_enable) { - p_spi->SPI_WPCR = SPI_WPCR_SPIWPKEY_VALUE | SPI_WPCR_SPIWPEN; - } else { - p_spi->SPI_WPCR = SPI_WPCR_SPIWPKEY_VALUE; - } -#else - if (ul_enable) { - p_spi->SPI_WPMR = SPI_WPMR_WPKEY_PASSWD | SPI_WPMR_WPEN; - } else { - p_spi->SPI_WPMR = SPI_WPMR_WPKEY_PASSWD; - } -#endif -} - -/** - * \brief Indicate write protect status. - * - * \param p_spi Pointer to an SPI instance. - * - * \return SPI_WPSR value. - */ -uint32_t spi_get_writeprotect_status(Spi *p_spi) -{ - return p_spi->SPI_WPSR; -} - -/** - * @} - */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.h deleted file mode 100644 index adb62ef9212..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.h +++ /dev/null @@ -1,627 +0,0 @@ -/** - * \file - * - * \brief Serial Peripheral Interface (SPI) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SPI_H_INCLUDED -#define SPI_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** Time-out value (number of attempts). */ -#define SPI_TIMEOUT 15000 - - /** Status codes used by the SPI driver. */ -typedef enum { - SPI_ERROR = -1, - SPI_OK = 0, - SPI_ERROR_TIMEOUT = 1, - SPI_ERROR_ARGUMENT, - SPI_ERROR_OVERRUN, - SPI_ERROR_MODE_FAULT, - SPI_ERROR_OVERRUN_AND_MODE_FAULT -} spi_status_t; - -/** SPI Chip Select behavior modes while transferring. */ -typedef enum spi_cs_behavior { - /** CS does not rise until a new transfer is requested on different chip select. */ - SPI_CS_KEEP_LOW = SPI_CSR_CSAAT, - /** CS rises if there is no more data to transfer. */ - SPI_CS_RISE_NO_TX = 0, - /** CS is de-asserted systematically during a time DLYBCS. */ - SPI_CS_RISE_FORCED = SPI_CSR_CSNAAT -} spi_cs_behavior_t; - -/** - * \brief Generate Peripheral Chip Select Value from Chip Select ID - * \note When chip select n is working, PCS bit n is set to low level. - * - * \param chip_sel_id The chip select number used - */ -#define spi_get_pcs(chip_sel_id) ((~(1u<<(chip_sel_id)))&0xF) - -/** - * \brief Reset SPI and set it to Slave mode. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_reset(Spi *p_spi) -{ - p_spi->SPI_CR = SPI_CR_SWRST; -} - -/** - * \brief Enable SPI. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_enable(Spi *p_spi) -{ - p_spi->SPI_CR = SPI_CR_SPIEN; -} - -/** - * \brief Disable SPI. - * - * \note CS is de-asserted, which indicates that the last data is done, and user - * should check TX_EMPTY before disabling SPI. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_disable(Spi *p_spi) -{ - p_spi->SPI_CR = SPI_CR_SPIDIS; -} - -/** - * \brief Issue a LASTXFER command. - * The next transfer is the last transfer and after that CS is de-asserted. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_set_lastxfer(Spi *p_spi) -{ - p_spi->SPI_CR = SPI_CR_LASTXFER; -} - -/** - * \brief Set SPI to Master mode. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_set_master_mode(Spi *p_spi) -{ - p_spi->SPI_MR |= SPI_MR_MSTR; -} - -/** - * \brief Set SPI to Slave mode. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_set_slave_mode(Spi *p_spi) -{ - p_spi->SPI_MR &= (~SPI_MR_MSTR); -} - -/** - * \brief Get SPI work mode. - * - * \param p_spi Pointer to an SPI instance. - * - * \return 1 for master mode, 0 for slave mode. - */ -static inline uint32_t spi_get_mode(Spi *p_spi) -{ - if (p_spi->SPI_MR & SPI_MR_MSTR) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Set Variable Peripheral Select. - * Peripheral Chip Select can be controlled by SPI_TDR. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_set_variable_peripheral_select(Spi *p_spi) -{ - p_spi->SPI_MR |= SPI_MR_PS; -} - -/** - * \brief Set Fixed Peripheral Select. - * Peripheral Chip Select is controlled by SPI_MR. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_set_fixed_peripheral_select(Spi *p_spi) -{ - p_spi->SPI_MR &= (~SPI_MR_PS); -} - -/** - * \brief Get Peripheral Select mode. - * - * \param p_spi Pointer to an SPI instance. - * - * \return 1 for Variable mode, 0 for fixed mode. - */ -static inline uint32_t spi_get_peripheral_select_mode(Spi *p_spi) -{ - if (p_spi->SPI_MR & SPI_MR_PS) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Enable Peripheral Select Decode. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_enable_peripheral_select_decode(Spi *p_spi) -{ - p_spi->SPI_MR |= SPI_MR_PCSDEC; -} - -/** - * \brief Disable Peripheral Select Decode. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_disable_peripheral_select_decode(Spi *p_spi) -{ - p_spi->SPI_MR &= (~SPI_MR_PCSDEC); -} - -/** - * \brief Get Peripheral Select Decode mode. - * - * \param p_spi Pointer to an SPI instance. - * - * \return 1 for decode mode, 0 for direct mode. - */ -static inline uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi) -{ - if (p_spi->SPI_MR & SPI_MR_PCSDEC) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Enable Mode Fault Detection. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_enable_mode_fault_detect(Spi *p_spi) -{ - p_spi->SPI_MR &= (~SPI_MR_MODFDIS); -} - -/** - * \brief Disable Mode Fault Detection. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_disable_mode_fault_detect(Spi *p_spi) -{ - p_spi->SPI_MR |= SPI_MR_MODFDIS; -} - -/** - * \brief Check if mode fault detection is enabled. - * - * \param p_spi Pointer to an SPI instance. - * - * \return 1 for disabled, 0 for enabled. - */ -static inline uint32_t spi_get_mode_fault_detect_setting(Spi *p_spi) -{ - if (p_spi->SPI_MR & SPI_MR_MODFDIS) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Enable waiting RX_EMPTY before transfer starts. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_enable_tx_on_rx_empty(Spi *p_spi) -{ - p_spi->SPI_MR |= SPI_MR_WDRBT; -} - -/** - * \brief Disable waiting RX_EMPTY before transfer starts. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_disable_tx_on_rx_empty(Spi *p_spi) -{ - p_spi->SPI_MR &= (~SPI_MR_WDRBT); -} - -/** - * \brief Check if SPI waits RX_EMPTY before transfer starts. - * - * \param p_spi Pointer to an SPI instance. - * - * \return 1 for SPI waits, 0 for no wait. - */ -static inline uint32_t spi_get_tx_on_rx_empty_setting(Spi *p_spi) -{ - if (p_spi->SPI_MR & SPI_MR_WDRBT) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Enable loopback mode. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_enable_loopback(Spi *p_spi) -{ - p_spi->SPI_MR |= SPI_MR_LLB; -} - -/** - * \brief Disable loopback mode. - * - * \param p_spi Pointer to an SPI instance. - */ -static inline void spi_disable_loopback(Spi *p_spi) -{ - p_spi->SPI_MR &= (~SPI_MR_LLB); -} - -void spi_enable_clock(Spi *p_spi); -void spi_disable_clock(Spi *p_spi); -void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value); -void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay); -spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs); -spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs, - uint8_t uc_last); - -/** - * \brief Read status register. - * - * \param p_spi Pointer to an SPI instance. - * - * \return SPI status register value. - */ -static inline uint32_t spi_read_status(Spi *p_spi) -{ - return p_spi->SPI_SR; -} - -/** - * \brief Test if the SPI is enabled. - * - * \param p_spi Pointer to an SPI instance. - * - * \return 1 if the SPI is enabled, otherwise 0. - */ -static inline uint32_t spi_is_enabled(Spi *p_spi) -{ - if (p_spi->SPI_SR & SPI_SR_SPIENS) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Put one data to a SPI peripheral. - * - * \param p_spi Base address of the SPI instance. - * \param data The data byte to be loaded - * - */ -static inline void spi_put(Spi *p_spi, uint16_t data) -{ - p_spi->SPI_TDR = SPI_TDR_TD(data); -} - -/** \brief Get one data to a SPI peripheral. - * - * \param p_spi Base address of the SPI instance. - * \return The data byte - * - */ -static inline uint16_t spi_get(Spi *p_spi) -{ - return (p_spi->SPI_RDR & SPI_RDR_RD_Msk); -} - -/** - * \brief Check if all transmissions are complete. - * - * \param p_spi Pointer to an SPI instance. - * - * \retval 1 if transmissions are complete. - * \retval 0 if transmissions are not complete. - */ -static inline uint32_t spi_is_tx_empty(Spi *p_spi) -{ - if (p_spi->SPI_SR & SPI_SR_TXEMPTY) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Check if all transmissions are ready. - * - * \param p_spi Pointer to an SPI instance. - * - * \retval 1 if transmissions are complete. - * \retval 0 if transmissions are not complete. - */ -static inline uint32_t spi_is_tx_ready(Spi *p_spi) -{ - if (p_spi->SPI_SR & SPI_SR_TDRE) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Check if the SPI contains a received character. - * - * \param p_spi Pointer to an SPI instance. - * - * \return 1 if the SPI Receive Holding Register is full, otherwise 0. - */ -static inline uint32_t spi_is_rx_full(Spi *p_spi) -{ - if (p_spi->SPI_SR & SPI_SR_RDRF) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Check if all receptions are ready. - * - * \param p_spi Pointer to an SPI instance. - * - * \return 1 if the SPI Receiver is ready, otherwise 0. - */ -static inline uint32_t spi_is_rx_ready(Spi *p_spi) -{ - if ((p_spi->SPI_SR & (SPI_SR_RDRF | SPI_SR_TXEMPTY)) - == (SPI_SR_RDRF | SPI_SR_TXEMPTY)) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Enable SPI interrupts. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_sources Interrupts to be enabled. - */ -static inline void spi_enable_interrupt(Spi *p_spi, uint32_t ul_sources) -{ - p_spi->SPI_IER = ul_sources; -} - -/** - * \brief Disable SPI interrupts. - * - * \param p_spi Pointer to an SPI instance. - * \param ul_sources Interrupts to be disabled. - */ -static inline void spi_disable_interrupt(Spi *p_spi, uint32_t ul_sources) -{ - p_spi->SPI_IDR = ul_sources; -} - -/** - * \brief Read SPI interrupt mask. - * - * \param p_spi Pointer to an SPI instance. - * - * \return The interrupt mask value. - */ -static inline uint32_t spi_read_interrupt_mask(Spi *p_spi) -{ - return p_spi->SPI_IMR; -} - -void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch, - uint32_t ul_polarity); -void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase); -void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch, - uint32_t ul_cs_behavior); -void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits); -int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck); -void spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch, - uint8_t uc_baudrate_divider); -void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs, - uint8_t uc_dlybct); - -#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) -/** - * \brief Get PDC registers base address. - * - * \param p_spi Pointer to an SPI instance. - * - * \return PDC registers base for PDC driver to access. - */ -static inline Pdc *spi_get_pdc_base(Spi *p_spi) -{ - return (Pdc *)&(p_spi->SPI_RPR); -} -#endif - -#if (SAM3U || SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Get transmit data register address for DMA operation. - * - * \param p_spi Pointer to an SPI instance. - * - * \return Transmit address for DMA access. - */ -static inline void *spi_get_tx_access(Spi *p_spi) -{ - return (void *)&(p_spi->SPI_TDR); -} - -/** - * \brief Get receive data register address for DMA operation. - * - * \param p_spi Pointer to an SPI instance. - * - * \return Receive address for DMA access. - */ -static inline void *spi_get_rx_access(Spi *p_spi) -{ - return (void *)&(p_spi->SPI_RDR); -} -#endif - -void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable); -uint32_t spi_get_writeprotect_status(Spi *p_spi); - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \page sam_spi_quickstart Quickstart guide for SAM SPI driver - * - * This is the quickstart guide for the \ref spi_group "SAM SPI driver", - * with step-by-step instructions on how to configure and use the driver in a - * selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g.the main application function. - * - * \section spi_basic_use_case Basic use case - * In this basic use case, the SPI module are configured for: - * - Master mode - * - Interrupt-based handling - * - * \subsection sam_spi_quickstart_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (Sysclock)" - * - * \section spi_basic_use_case_setup Setup steps - * \subsection spi_basic_use_case_setup_code Example code - * Add to application C-file: - * \code - void spi_master_init(Spi *p_spi) - { - spi_enable_clock(p_spi); - spi_reset(p_spi); - spi_set_master_mode(p_spi); - spi_disable_mode_fault_detect(p_spi); - spi_disable_loopback(p_spi); - spi_set_peripheral_chip_select_value(p_spi, - spi_get_pcs(DEFAULT_CHIP_ID)); - spi_set_fixed_peripheral_select(p_spi); - spi_disable_peripheral_select_decode(p_spi); - spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS); - } - void spi_master_setup_device(Spi *p_spi, struct spi_device *device, - spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id) - { - spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS, - CONFIG_SPI_MASTER_DELAY_BCT); - - spi_set_bits_per_transfer(p_spi, device->id, CONFIG_SPI_MASTER_BITS_PER_TRANSFER); - spi_set_baudrate_div(p_spi, device->id, - spi_calc_baudrate_div(baud_rate, sysclk_get_cpu_hz())); - - spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW); - - spi_set_clock_polarity(p_spi, device->id, flags >> 1); - spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1)); - } -\endcode - * - * \subsection spi_basic_use_case_setup_flow Workflow - * -# Initialize the SPI in master mode: - * - \code - void spi_master_init(SPI_EXAMPLE); -\endcode - * -# Set up an SPI device: - * - \code void spi_master_setup_device(SPI_EXAMPLE, &SPI_DEVICE_EXAMPLE, - SPI_MODE_0, SPI_EXAMPLE_BAUDRATE, 0); \endcode - * - \note The returned device descriptor structure must be passed to the driver - * whenever that device should be used as current slave device. - * -# Enable SPI module: - * - \code spi_enable(SPI_EXAMPLE); \endcode - */ -#endif /* SPI_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/supc/supc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/supc/supc.c deleted file mode 100644 index 20f605ca1d5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/supc/supc.c +++ /dev/null @@ -1,424 +0,0 @@ -/** - * \file - * - * \brief Supply Controller (SUPC) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "supc.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \defgroup sam_drivers_supc_group Supply Controller (SUPC) - * - * Driver for the SUPC (Supply Controller). This driver provides access to the main - * features of the Supply Controller. - * - * @{ - */ - -#if (!SAMG) - /** - * \brief Switch off the voltage regulator to put the device in backup mode. - * - * \param p_supc Pointer to a SUPC instance. - */ - void supc_enable_backup_mode(Supc *p_supc) -{ - p_supc->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF; - __WFE(); - __WFI(); -} - -/** - * \brief Enable the internal voltage regulator. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_enable_voltage_regulator(Supc *p_supc) -{ -#if (SAM3U || SAM3XA) - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_VDDIORDYONREG)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_VDDIORDYONREG; -#else - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_ONREG)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_ONREG; -#endif -} - -/** - * \brief Disable the internal voltage regulator to supply VDDCORE with an external supply. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_disable_voltage_regulator(Supc *p_supc) -{ -#if (SAM3U || SAM3XA) - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_VDDIORDYONREG)); -#else - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_ONREG)); -#endif - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr; -} -#endif - -/** - * \brief Switch slow clock source selection to external 32k (Xtal or Bypass) oscillator. - * This function disables the PLLs. - * - * \note Switching sclk back to 32krc is only possible by shutting down the VDDIO power supply. - * - * \param ul_bypass 0 for Xtal, 1 for bypass. - */ -void supc_switch_sclk_to_32kxtal(Supc *p_supc, uint32_t ul_bypass) -{ - /* Set Bypass mode if required */ - if (ul_bypass == 1) { - p_supc->SUPC_MR |= SUPC_MR_KEY_PASSWD | SUPC_MR_OSCBYPASS; - } else { - p_supc->SUPC_MR &= ~(SUPC_MR_KEY_PASSWD | SUPC_MR_OSCBYPASS); - } - - p_supc->SUPC_CR |= SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; -} - -/** - * \brief Enable the core brownout detector. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_enable_brownout_detector(Supc *p_supc) -{ - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BODDIS)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr; -} - -/** - * \brief Disable the core brownout detector. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_disable_brownout_detector(Supc *p_supc) -{ - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BODDIS)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_BODDIS; -} - -/** - * \brief Enable the assertion of core reset signal when a brownout detection occurs. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_enable_brownout_reset(Supc *p_supc) -{ - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BODRSTEN)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_BODRSTEN; -} - -/** - * \brief Disable the assertion of core reset signal when a brownout detection occurs. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_disable_brownout_reset(Supc *p_supc) -{ - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BODRSTEN)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr; -} - -/** - * \brief Set Supply monitor threshold. - * - * \param p_supc Pointer to a SUPC instance. - * \param ul_threshold Supply monitor threshold (between 1.9V and 3.4V). - */ -void supc_set_monitor_threshold(Supc *p_supc, uint32_t ul_threshold) -{ - uint32_t ul_smmr = p_supc->SUPC_SMMR & (~SUPC_SMMR_SMTH_Msk); - p_supc->SUPC_SMMR = ul_smmr | (SUPC_SMMR_SMTH_Msk & ul_threshold); -} - -/** - * \brief Set Supply monitor sampling period. - * - * \param p_supc Pointer to a SUPC instance. - * \param ul_period Supply monitor sampling period. - */ -void supc_set_monitor_sampling_period(Supc *p_supc, uint32_t ul_period) -{ - uint32_t ul_smmr = p_supc->SUPC_SMMR & (~SUPC_SMMR_SMSMPL_Msk); - p_supc->SUPC_SMMR = ul_smmr | (SUPC_SMMR_SMSMPL_Msk & ul_period); -} - -/** - * \brief Enable the assertion of the core reset signal when a supply monitor detection occurs. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_enable_monitor_reset(Supc *p_supc) -{ - p_supc->SUPC_SMMR |= SUPC_SMMR_SMRSTEN; -} - -/** - * \brief Disable the assertion of core reset signal when a supply monitor detection occurs. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_disable_monitor_reset(Supc *p_supc) -{ - p_supc->SUPC_SMMR &= ~SUPC_SMMR_SMRSTEN; -} - -/** - * \brief Enable the assertion of SUPC interrupt signal when a supply monitor detection occurs. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_enable_monitor_interrupt(Supc *p_supc) -{ - p_supc->SUPC_SMMR |= SUPC_SMMR_SMIEN; -} - -/** - * \brief Disable the assertion of SUPC interrupt signal when a supply monitor detection occurs. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_disable_monitor_interrupt(Supc *p_supc) -{ - p_supc->SUPC_SMMR &= ~SUPC_SMMR_SMIEN; -} - -#if (!(SAMG51 || SAMG53 || SAMG54)) -/** - * \brief Set system controller wake up mode. - * - * \param p_supc Pointer to a SUPC instance. - * \param ul_mode Bitmask of wake up mode (please refer to datasheet for more details). - */ -void supc_set_wakeup_mode(Supc *p_supc, uint32_t ul_mode) -{ - p_supc->SUPC_WUMR = ul_mode; -} - -/** - * \brief Set system controller wake up inputs. - * - * \param p_supc Pointer to a SUPC instance. - * \param ul_inputs Bitmask of wake-up inputs that can force wake up of - * the core power supply. - * \param ul_transition Bitmask of level transition of the wake-up inputs. - * 1 means a high-to-low level transition forces the wake up of core power supply. - * 0 means a low-to-high level transition forces the wake up of core power supply. - */ -void supc_set_wakeup_inputs(Supc *p_supc, uint32_t ul_inputs, - uint32_t ul_transition) -{ - p_supc->SUPC_WUIR = ul_inputs | ul_transition; -} -#endif - -/** - * \brief Get supply controller status. - * - * \param p_supc Pointer to a SUPC instance. - * - * \return The status of supply controller. - */ -uint32_t supc_get_status(Supc *p_supc) -{ - return p_supc->SUPC_SR; -} - -#if (SAM4C || SAM4CP || SAM4CM) -/** - * \brief Enable Backup Area Power-On Reset. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_enable_backup_power_on_reset(Supc *p_supc) -{ - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BUPPOREN)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_BUPPOREN; -} - -/** - * \brief Disable Backup Area Power-On Reset. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_disable_backup_power_on_reset(Supc *p_supc) -{ - uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BUPPOREN)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr; -} -/** - * \brief Get SLCD power mode. - * - * \param p_supc Pointer to a SUPC instance. - * - * \return The mode of SLCDC. - */ -enum slcdc_power_mode supc_get_slcd_power_mode(Supc *p_supc) -{ - return (enum slcdc_power_mode)(p_supc->SUPC_MR & SUPC_MR_LCDMODE_Msk); -} - -/** - * \brief Set SLCD power mode. - * - * \param p_supc Pointer to a SUPC instance. - * \param mode The mode of SLCDC. - */ -void supc_set_slcd_power_mode(Supc *p_supc, enum slcdc_power_mode mode) -{ - enum slcdc_power_mode pre_mode; - uint32_t tmp; - - pre_mode = supc_get_slcd_power_mode(p_supc); - - if ((pre_mode == SLCDC_POWER_MODE_LCDON_EXTVR) && - (mode == SLCDC_POWER_MODE_LCDON_INVR)) { - return; - } else if ((pre_mode == SLCDC_POWER_MODE_LCDON_INVR) && - (mode == SLCDC_POWER_MODE_LCDON_EXTVR)) { - return; - } - tmp = p_supc->SUPC_MR; - tmp &= ~SUPC_MR_LCDMODE_Msk; - tmp |= SUPC_MR_KEY_PASSWD | mode; - p_supc->SUPC_MR = tmp; - - if (mode == SLCDC_POWER_MODE_LCDOFF) { - while(supc_get_status(p_supc) & SUPC_SR_LCDS_ENABLED); - } else { - while(!(supc_get_status(p_supc) & SUPC_SR_LCDS_ENABLED)); - } -} - -/** - * \brief Set LCD Voltage Regulator Output. - * - * \param p_supc Pointer to a SUPC instance. - * \param vol The voltage of Regulator Output. - */ -void supc_set_slcd_vol(Supc *p_supc, uint32_t vol) -{ - uint32_t tmp= p_supc->SUPC_MR; - tmp &= ~SUPC_MR_LCDVROUT_Msk; - tmp |= SUPC_MR_KEY_PASSWD | SUPC_MR_LCDVROUT(vol); - p_supc->SUPC_MR = tmp; - -} -#endif - -#if SAMG54 -/** - * \brief Set the internal voltage regulator to use factory trim value. - * - * \param p_supc Pointer to a SUPC instance. - */ -void supc_set_regulator_trim_factory(Supc *p_supc) -{ - uint32_t ul_mr = p_supc->SUPC_MR & - (~(SUPC_MR_VRVDD_Msk | SUPC_MR_VDDSEL_USER_VRVDD)); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr; -} - -/** - * \brief Set the internal voltage regulator trim value. - * - * \param p_supc Pointer to a SUPC instance. - * \param value the trim value. - * - * \note For the trim value in 96M PLL, please read the value in flash unique identifier area. - */ -void supc_set_regulator_trim_user(Supc *p_supc, uint32_t value) -{ - uint32_t ul_mr = p_supc->SUPC_MR & (~SUPC_MR_VRVDD_Msk); - p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_VDDSEL_USER_VRVDD - | SUPC_MR_VRVDD(value); -} - -#endif - -#if (SAMV70 || SAMV71 || SAME70 || SAMS70) -/** - * \brief SRAM On In Backup Mode. - * - * \param p_supc Pointer to a SUPC instance. - * - */ -void supc_backup_sram_on(Supc *p_supc) -{ - p_supc->SUPC_MR |= (SUPC_MR_KEY_PASSWD | SUPC_MR_BKUPRETON); -} - -/** - * \brief SRAM Off In Backup Mode. - * - * \param p_supc Pointer to a SUPC instance. - * - */ -void supc_backup_sram_off(Supc *p_supc) -{ - p_supc->SUPC_MR &= (~(SUPC_MR_KEY_PASSWD | SUPC_MR_BKUPRETON)); -} -#endif - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/supc/supc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/supc/supc.h deleted file mode 100644 index 484e118c3f2..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/supc/supc.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * \file - * - * \brief Supply Controller (SUPC) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SUPC_H_INCLUDED -#define SUPC_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** Key used to write SUPC registers */ -#ifndef SUPC_CR_KEY_PASSWD -#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U) -#endif - -#ifndef SUPC_MR_KEY_PASSWD -#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U) -#endif - -#if (SAM4C || SAM4CP || SAM4CM) - /** Power Mode */ -enum slcdc_power_mode { - /** The internal supply source and the external supply source are both deselected. */ - SLCDC_POWER_MODE_LCDOFF = SUPC_MR_LCDMODE_LCDOFF, - /** The external supply source for LCD is selected */ - SLCDC_POWER_MODE_LCDON_EXTVR = SUPC_MR_LCDMODE_LCDON_EXTVR, - /** The internal supply source for LCD is selected */ - SLCDC_POWER_MODE_LCDON_INVR = SUPC_MR_LCDMODE_LCDON_INVR, -}; -#endif - -#if (!SAMG) -void supc_enable_backup_mode(Supc *p_supc); -void supc_enable_voltage_regulator(Supc *p_supc); -void supc_disable_voltage_regulator(Supc *p_supc); -#endif -void supc_switch_sclk_to_32kxtal(Supc *p_supc, uint32_t ul_bypass); -void supc_enable_brownout_detector(Supc *p_supc); -void supc_disable_brownout_detector(Supc *p_supc); -void supc_enable_brownout_reset(Supc *p_supc); -void supc_disable_brownout_reset(Supc *p_supc); -void supc_set_monitor_threshold(Supc *p_supc, uint32_t ul_threshold); -void supc_set_monitor_sampling_period(Supc *p_supc, uint32_t ul_period); -void supc_enable_monitor_reset(Supc *p_supc); -void supc_disable_monitor_reset(Supc *p_supc); -void supc_enable_monitor_interrupt(Supc *p_supc); -void supc_disable_monitor_interrupt(Supc *p_supc); -#if (!(SAMG51 || SAMG53 || SAMG54)) -void supc_set_wakeup_mode(Supc *p_supc, uint32_t ul_mode); -void supc_set_wakeup_inputs(Supc *p_supc, uint32_t ul_inputs, - uint32_t ul_transition); -#endif -uint32_t supc_get_status(Supc *p_supc); -#if (SAM4C || SAM4CP || SAM4CM) -void supc_enable_backup_power_on_reset(Supc *p_supc); -void supc_disable_backup_power_on_reset(Supc *p_supc); -enum slcdc_power_mode supc_get_slcd_power_mode(Supc *p_supc); -void supc_set_slcd_power_mode(Supc *p_supc, enum slcdc_power_mode mode); -void supc_set_slcd_vol(Supc *p_supc, uint32_t vol); -#endif -#if SAMG54 -void supc_set_regulator_trim_factory(Supc *p_supc); -void supc_set_regulator_trim_user(Supc *p_supc, uint32_t value); -#endif -#if (SAMV70 || SAMV71 || SAME70 || SAMS70) -void supc_backup_sram_on(Supc *p_supc); -void supc_backup_sram_off(Supc *p_supc); -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* SUPC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/tc/tc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/tc/tc.c deleted file mode 100644 index 8132a5fb3cc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/tc/tc.c +++ /dev/null @@ -1,777 +0,0 @@ -/** - * \file - * - * \brief SAM Timer Counter (TC) driver. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include "tc.h" - -/// @cond -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -#ifndef TC_WPMR_WPKEY_PASSWD -#define TC_WPMR_WPKEY_PASSWD TC_WPMR_WPKEY((uint32_t)0x54494D) -#endif - - /** - * \brief Configure TC for timer, waveform generation, or capture. - * - * \param[in,out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to configure - * \param[in] ul_mode Control mode register bitmask value to set - * - * \note For more information regarding ul_mode configuration refer to - * the section entitled "Channel Mode Register: Capture Mode" and/or section - * "Waveform Operating Mode" in the device-specific datasheet. - * - * \note If the TC is configured for waveform generation then the external event - * selection (EEVT) should only be set to TC_CMR_EEVT_TIOB, or the - * equivalent value of 0, if it really is the intention to use TIOB as an - * external event trigger. This is because this setting forces TIOB to be - * an input, even if the external event trigger has not been enabled with - * TC_CMR_ENETRG, and thus prevents normal operation of TIOB. - */ - void tc_init( - Tc *p_tc, - uint32_t ul_channel, - uint32_t ul_mode) -{ - TcChannel *tc_channel; - - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - - /* Disable TC clock. */ - tc_channel->TC_CCR = TC_CCR_CLKDIS; - - /* Disable interrupts. */ - tc_channel->TC_IDR = 0xFFFFFFFF; - - /* Clear status register. */ - tc_channel->TC_SR; - - /* Set mode. */ - tc_channel->TC_CMR = ul_mode; -} - -/** - * \brief Asserts a SYNC signal to generate a software trigger on - * all channels. - * - * \param[out] p_tc Module hardware register base address pointer - * - */ -void tc_sync_trigger( - Tc *p_tc) -{ - /* Validate inputs. */ - Assert(p_tc); - - p_tc->TC_BCR = TC_BCR_SYNC; -} - -/** - * \brief Configure the TC Block mode. - * - * \note The function tc_init() must be called prior to this one. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_blockmode Block mode register value to set - * - * \note For more information regarding ul_blockmode configuration refer to - * the section entitled "TC Block Mode Register" in the device-specific datasheet. - */ -void tc_set_block_mode( - Tc *p_tc, - uint32_t ul_blockmode) -{ - /* Validate inputs. */ - Assert(p_tc); - - p_tc->TC_BMR = ul_blockmode; -} - -#if (!SAM3U) || defined(__DOXYGEN__) - -/** - * \brief Configure TC for 2-bit Gray Counter for Stepper Motor. - * \note The function tc_init() must be called prior to this one. - * - * \note This function is not available on SAM3U devices. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to configure - * \param[in] ul_steppermode Stepper motor mode register value to set - * - * \return 0 for OK. - */ -uint32_t tc_init_2bit_gray( - Tc *p_tc, - uint32_t ul_channel, - uint32_t ul_steppermode) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_SMMR = ul_steppermode; - return 0; -} - -#endif /* (!SAM3U) || defined(__DOXYGEN__) */ - -/** - * \brief Start the TC clock on the specified channel. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to configure - */ -void tc_start( - Tc *p_tc, - uint32_t ul_channel) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG; -} - -/** - * \brief Stop the TC clock on the specified channel. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to configure - */ -void tc_stop( - Tc *p_tc, - uint32_t ul_channel) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKDIS; -} - -/** - * \brief Read the counter value on the specified channel. - * - * \param[in] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to read - * - * \return The counter value. - */ -uint32_t tc_read_cv( - Tc *p_tc, - uint32_t ul_channel) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - return p_tc->TC_CHANNEL[ul_channel].TC_CV; -} - -/** - * \brief Read TC Register A (RA) on the specified channel. - * - * \param[in] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to read - * - * \return The TC Register A (RA) value. - */ -uint32_t tc_read_ra( - Tc *p_tc, - uint32_t ul_channel) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - return p_tc->TC_CHANNEL[ul_channel].TC_RA; -} - -/** - * \brief Read TC Register B (RB) on the specified channel. - * - * \param[in] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to read - * - * \return The TC Register B (RB) value. - */ -uint32_t tc_read_rb( - Tc *p_tc, - uint32_t ul_channel) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - return p_tc->TC_CHANNEL[ul_channel].TC_RB; -} - -/** - * \brief Read TC Register C (RC) on the specified channel. - * - * \param[in] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to read - * - * \return The Register C (RC) value. - */ -uint32_t tc_read_rc( - Tc *p_tc, - uint32_t ul_channel) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - return p_tc->TC_CHANNEL[ul_channel].TC_RC; -} - -/** - * \brief Write to TC Register A (RA) on the specified channel. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to write - * \param[in] ul_value Value to write - */ -void tc_write_ra( - Tc *p_tc, - uint32_t ul_channel, - uint32_t ul_value) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_RA = ul_value; -} - -/** - * \brief Write to TC Register B (RB) on the specified channel. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to write - * \param[in] ul_value Value to write - */ -void tc_write_rb( - Tc *p_tc, - uint32_t ul_channel, - uint32_t ul_value) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_RB = ul_value; -} - -/** - * \brief Write to TC Register C (RC) on the selected channel. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to write - * \param[in] ul_value Value to write - */ -void tc_write_rc( - Tc *p_tc, - uint32_t ul_channel, - uint32_t ul_value) -{ - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_RC = ul_value; -} - -/** - * \brief Enable the TC interrupts on the specified channel. - * - * \param[in,out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to configure - * \param[in] ul_sources Bitmask of interrupt sources - * - * Where the input parameter ul_sources can be one or more of the following: - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Parameter ValueDescription
TC_IER_COVFSEnables the Counter Overflow Interrupt
TC_IER_LOVRSEnables the Load Overrun Interrupt
TC_IER_CPASEnables the RA Compare Interrupt
TC_IER_CPBSEnables the RB Compare Interrupt
TC_IER_CPCSEnables the RC Compare Interrupt
TC_IER_LDRASEnables the RA Load Interrupt
TC_IER_LDRBSEnables the RB Load Interrupt
TC_IER_ETRGSEnables the External Trigger Interrupt
- */ -void tc_enable_interrupt( - Tc *p_tc, - uint32_t ul_channel, - uint32_t ul_sources) -{ - TcChannel *tc_channel; - - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - tc_channel->TC_IER = ul_sources; -} - -/** - * \brief Disable TC interrupts on the specified channel. - * - * \param[in,out] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to configure - * \param[in] ul_sources A bitmask of Interrupt sources - * - * Where the input parameter ul_sources can be one or more of the following: - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Parameter ValueDescription
TC_IDR_COVFSDisables the Counter Overflow Interrupt
TC_IDR_LOVRSDisables the Load Overrun Interrupt
TC_IDR_CPASDisables the RA Compare Interrupt
TC_IDR_CPBSDisables the RB Compare Interrupt
TC_IDR_CPCSDisables the RC Compare Interrupt
TC_IDR_LDRASDisables the RA Load Interrupt
TC_IDR_LDRBSDisables the RB Load Interrupt
TC_IDR_ETRGSDisables the External Trigger Interrupt
- */ -void tc_disable_interrupt( - Tc *p_tc, - uint32_t ul_channel, - uint32_t ul_sources) -{ - TcChannel *tc_channel; - - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - tc_channel->TC_IDR = ul_sources; -} - -/** - * \brief Read the TC interrupt mask for the specified channel. - * - * \param[in] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel to read - * - * \return The TC interrupt mask value. - */ -uint32_t tc_get_interrupt_mask( - Tc *p_tc, - uint32_t ul_channel) -{ - TcChannel *tc_channel; - - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - return tc_channel->TC_IMR; -} - -/** - * \brief Get the current status for the specified TC channel. - * - * \param[in] p_tc Module hardware register base address pointer - * \param[in] ul_channel Channel number - * - * \return The current TC status. - */ -uint32_t tc_get_status( - Tc *p_tc, - uint32_t ul_channel) -{ - TcChannel *tc_channel; - - /* Validate inputs. */ - Assert(p_tc); - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - tc_channel = p_tc->TC_CHANNEL + ul_channel; - return tc_channel->TC_SR; -} - -/* TC divisor used to find the lowest acceptable timer frequency */ -#define TC_DIV_FACTOR 65536 - -#if (!SAM4L) && !defined(__DOXYGEN__) - -#ifndef FREQ_SLOW_CLOCK_EXT -#define FREQ_SLOW_CLOCK_EXT 32768 /* External slow clock frequency (hz) */ -#endif - -/** - * \brief Find the best MCK divisor. - * - * Finds the best MCK divisor given the timer frequency and MCK. The result - * is guaranteed to satisfy the following equation: - * \code (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) \endcode - * With DIV being the lowest possible value, to maximize timing adjust resolution. - * - * \param[in] ul_freq Desired timer frequency - * \param[in] ul_mck Master clock frequency - * \param[out] p_uldiv Divisor value - * \param[out] p_ultcclks TCCLKS field value for divisor - * \param[in] ul_boardmck Board clock frequency - * - * \return The divisor found status. - * \retval 0 No suitable divisor was found - * \retval 1 A divisor was found - */ -uint32_t tc_find_mck_divisor( - uint32_t ul_freq, - uint32_t ul_mck, - uint32_t *p_uldiv, - uint32_t *p_ultcclks, - uint32_t ul_boardmck) -{ - const uint32_t divisors[5] = { 2, 8, 32, 128, - ul_boardmck / FREQ_SLOW_CLOCK_EXT - }; - uint32_t ul_index; - uint32_t ul_high, ul_low; - - /* Satisfy frequency bound. */ - for (ul_index = 0; - ul_index < (sizeof(divisors) / sizeof(divisors[0])); - ul_index++) { - ul_high = ul_mck / divisors[ul_index]; - ul_low = ul_high / TC_DIV_FACTOR; - if (ul_freq > ul_high) { - return 0; - } else if (ul_freq >= ul_low) { - break; - } - } - if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) { - return 0; - } - - /* Store results. */ - if (p_uldiv) { - *p_uldiv = divisors[ul_index]; - } - - if (p_ultcclks) { - *p_ultcclks = ul_index; - } - - return 1; -} - -#endif /* (!SAM4L) */ - -#if (SAM4L) || defined(__DOXYGEN__) -/** - * \brief Find the best PBA/MCK divisor. - * - * For SAM4L devices: Finds the best PBA divisor given the timer - * frequency and PBA clock. The result is guaranteed to satisfy the following equation: - * \code (ul_pbaclk / (2* DIV * 65536)) <= freq <= (ul_pbaclk / (2* DIV)) \endcode - * with DIV being the lowest possible value, to maximize timing adjust resolution. - * - * For non SAM4L devices: Finds the best MCK divisor given the timer frequency - * and MCK. The result is guaranteed to satisfy the following equation: - * \code (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) \endcode - * with DIV being the lowest possible value, to maximize timing adjust resolution. - * - * \param[in] ul_freq Desired timer frequency - * \param[in] ul_mck PBA clock frequency - * \param[out] p_uldiv Divisor value - * \param[out] p_ultcclks TCCLKS field value for divisor - * \param[in] ul_boardmck Board clock frequency (set to 0 for SAM4L devices) - * - * \return The divisor found status. - * \retval 0 No suitable divisor was found - * \retval 1 A divisor was found - */ -uint32_t tc_find_mck_divisor( - uint32_t ul_freq, - uint32_t ul_mck, - uint32_t *p_uldiv, - uint32_t *p_ultcclks, - uint32_t ul_boardmck) -{ - const uint32_t divisors[5] = { 0, 2, 8, 32, 128}; - uint32_t ul_index; - uint32_t ul_high, ul_low; - - UNUSED(ul_boardmck); - - /* Satisfy frequency bound. */ - for (ul_index = 1; - ul_index < (sizeof(divisors) / sizeof(divisors[0])); - ul_index++) { - ul_high = ul_mck / divisors[ul_index]; - ul_low = ul_high / TC_DIV_FACTOR; - if (ul_freq > ul_high) { - return 0; - } else if (ul_freq >= ul_low) { - break; - } - } - if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) { - return 0; - } - - /* Store results. */ - if (p_uldiv) { - *p_uldiv = divisors[ul_index]; - } - - if (p_ultcclks) { - *p_ultcclks = ul_index; - } - - return 1; -} - -#endif /* (SAM4L) || defined(__DOXYGEN__) */ - -#if (!SAM4L && !SAMG) || defined(__DOXYGEN__) - -/** - * \brief Enable TC QDEC interrupts. - * - * \note This function is not available on SAM4L or SAMG devices. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_sources A bitmask of QDEC interrupts to be enabled - * - * Where the input parameter ul_sources can be one or more of the following: - * - * - * - * - * - * - * - * - *
Parameter ValueDescription
TC_QIER_IDXEnable the rising edge detected on IDX input interrupt
TC_QIER_DIRCHGEnable the change in rotation direction detected interrupt
TC_QIER_QERREnable the quadrature error detected on PHA/PHB interrupt
- */ -void tc_enable_qdec_interrupt( - Tc *p_tc, - uint32_t ul_sources) -{ - /* Validate inputs. */ - Assert(p_tc); - - p_tc->TC_QIER = ul_sources; -} - -/** - * \brief Disable TC QDEC interrupts. - * - * \note This function is not available on SAM4L or SAMG devices. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_sources A bitmask of QDEC interrupts to be disabled - * - * Where the input parameter ul_sources can be one or more of the following: - * - * - * - * - * - * - * - * - *
Parameter ValueDescription
TC_QIDR_IDXDisable the rising edge detected on IDX input interrupt
TC_QIDR_DIRCHGDisable the change in rotation direction detected interrupt
TC_QIDR_QERRDisable the quadrature error detected on PHA/PHB interrupt
- */ -void tc_disable_qdec_interrupt( - Tc *p_tc, - uint32_t ul_sources) -{ - /* Validate inputs. */ - Assert(p_tc); - - p_tc->TC_QIDR = ul_sources; -} - -/** - * \brief Read TC QDEC interrupt mask. - * - * \note This function is not available on SAM4L or SAMG devices. - * - * \param[in] p_tc Module hardware register base address pointer - * - * \return The QDEC interrupt mask value. - */ -uint32_t tc_get_qdec_interrupt_mask( - Tc *p_tc) -{ - /* Validate inputs. */ - Assert(p_tc); - - return p_tc->TC_QIMR; -} - -/** - * \brief Get current TC QDEC interrupt status. - * - * \note This function is not available on SAM4L or SAMG devices. - * - * \param[in] p_tc Module hardware register base address pointer - * - * \return The TC QDEC interrupt status. - */ -uint32_t tc_get_qdec_interrupt_status( - Tc *p_tc) -{ - /* Validate inputs. */ - Assert(p_tc); - - return p_tc->TC_QISR; -} - -#endif /* (!SAM4L && !SAMG) || defined(__DOXYGEN__) */ - -#if (!SAM3U) || defined(__DOXYGEN__) - -/** - * \brief Enable or disable write protection of TC registers. - * - * \note This function is not available on SAM3U devices. - * - * \param[out] p_tc Module hardware register base address pointer - * \param[in] ul_enable 1 to enable, 0 to disable - */ -void tc_set_writeprotect( - Tc *p_tc, - uint32_t ul_enable) -{ - /* Validate inputs. */ - Assert(p_tc); - - if (ul_enable) { - p_tc->TC_WPMR = TC_WPMR_WPKEY_PASSWD | TC_WPMR_WPEN; - } else { - p_tc->TC_WPMR = TC_WPMR_WPKEY_PASSWD; - } -} - -#endif /* (!SAM3U) || defined(__DOXYGEN__) */ - -#if SAM4L || defined(__DOXYGEN__) - -/** - * \brief Indicate TC features. - * - * \note This function is only available on SAM4L devices. - * - * \param[in] p_tc Module hardware register base address pointer - * - * \return The TC FEATURES register contents. - */ -uint32_t tc_get_feature( - Tc *p_tc) -{ - /* Validate inputs. */ - Assert(p_tc); - - return p_tc->TC_FEATURES; -} - -/** - * \brief Indicate TC version. - * - * \note This function is only available on SAM4L devices. - * - * \param[in] p_tc Module hardware register base address pointer - * - * \return The TC VERSION register contents. - */ -uint32_t tc_get_version( - Tc *p_tc) -{ - /* Validate inputs. */ - Assert(p_tc); - - return p_tc->TC_VERSION; -} - -#endif /* SAM4L || defined(__DOXYGEN__) */ - -/// @cond -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/tc/tc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/tc/tc.h deleted file mode 100644 index 5693752e0d6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/tc/tc.h +++ /dev/null @@ -1,455 +0,0 @@ -/** - * \file - * - * \brief SAM Timer Counter (TC) driver. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef TC_H_INCLUDED -#define TC_H_INCLUDED - -/** - * \defgroup asfdoc_sam_drivers_tc_group SAM3/4S/4L/4E/4N/4CM/4C/G Timer Counter (TC) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers - * provides an interface for the configuration and management of the - * device's Timer Counter functionality. - * - * The Timer Counter (TC) includes several identical 16-bit or 32-bit - * Timer Counter channels. Each channel can be independently programmed - * to perform a wide range of functions that includes frequency - * measurement, event counting, interval measurement, pulse generation, - * delay timing, and pulse width modulation. - * - * Devices from the following series can use this module: - * - Atmel | SMART SAM3 - * - Atmel | SMART SAM4S - * - Atmel | SMART SAM4L - * - Atmel | SMART SAM4E - * - Atmel | SMART SAM4N - * - Atmel | SMART SAM4CM - * - Atmel | SMART SAM4C - * - Atmel | SMART SAMG - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam_drivers_tc_prerequisites - * - \ref asfdoc_sam_drivers_tc_module_overview - * - \ref asfdoc_sam_drivers_tc_special_considerations - * - \ref asfdoc_sam_drivers_tc_extra_info - * - \ref asfdoc_sam_drivers_tc_examples - * - \ref asfdoc_sam_drivers_tc_api_overview - * - * - * \section asfdoc_sam_drivers_tc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam_drivers_tc_module_overview Module Overview - * The Timer Counter (TC) includes several identical 16-bit or 32-bit Timer - * Counter channels. The number of TC channels is device specific, refer - * to the device-specific datasheet for more information. - * - * Each channel can be independently programmed to perform a wide range of - * functions that includes frequency measurement, event counting, interval measurement, - * pulse generation, delay timing, and pulse width modulation. - * - * Each channel has three external clock inputs, five internal clock inputs, - * and two multi-purpose input/output signals which can be configured by the user. - * Each channel drives an internal interrupt signal which can be programmed to - * generate processor interrupts. - * - * The Timer Counter (TC) embeds a quadrature decoder logic connected in front of - * the timers. When enabled, the quadrature decoder performs the input line - * filtering, decoding of quadrature signals and connects to the timers/counters - * in order to read the position and speed of the motor. - * - * - * \section asfdoc_sam_drivers_tc_special_considerations Special Considerations - * \subsection asfdoc_sam_drivers_tc_special_considerations_clock External Clock - * In all cases, if an external clock is used, the duration of each of its levels - * must be longer than the master clock (MCLK) period. The external clock frequency - * must be at least 2.5 times lower than the master clock. - * - * \subsection asfdoc_sam_drivers_tc_special_considerations_trigger External Trigger - * If an external trigger is used, the duration of its pulses must be longer than - * the master clock (MCLK) period in order to be detected. - * - * - * \section asfdoc_sam_drivers_tc_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam_drivers_tc_extra. This includes: - * - \ref asfdoc_sam_drivers_tc_extra_acronyms - * - \ref asfdoc_sam_drivers_tc_extra_dependencies - * - \ref asfdoc_sam_drivers_tc_extra_errata - * - \ref asfdoc_sam_drivers_tc_extra_history - * - * \section asfdoc_sam_drivers_tc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam_drivers_tc_exqsg. - * - * - * \section asfdoc_sam_drivers_tc_api_overview API Overview - * @{ - */ - -#include - -/// @cond -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - void tc_init(Tc *p_tc, uint32_t ul_Channel, uint32_t ul_Mode); - void tc_sync_trigger(Tc *p_tc); - void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode); - -#if (!SAM3U) || defined(__DOXYGEN__) - uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_steppermode); -#endif /* (!SAM3U) || defined(__DOXYGEN__) */ - - void tc_start(Tc *p_tc, uint32_t ul_channel); - void tc_stop(Tc *p_tc, uint32_t ul_channel); - - uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel); - uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel); - uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel); - uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel); - - void tc_write_ra(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value); - void tc_write_rb(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value); - void tc_write_rc(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value); - - uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, - uint32_t *p_uldiv, uint32_t *ul_tcclks, uint32_t ul_boardmck); - void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_sources); - void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_sources); - uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel); - uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel); -#if (!SAM4L && !SAMG) || defined(__DOXYGEN__) - void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources); - void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources); - uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc); - uint32_t tc_get_qdec_interrupt_status(Tc *p_tc); -#endif /* (!SAM4L && !SAMG) || defined(__DOXYGEN__) */ - -#if (!SAM3U) - void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable); -#endif /* (!SAM3U) */ - -#if SAM4L || defined(__DOXYGEN__) - uint32_t tc_get_feature(Tc *p_tc); - uint32_t tc_get_version(Tc *p_tc); -#endif /* SAM4L || defined(__DOXYGEN__) */ - -/// @cond -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -/** @} */ - -/** - * \page asfdoc_sam_drivers_tc_extra Extra Information for Timer Counter Driver - * - * \section asfdoc_sam_drivers_tc_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDefinition
MCKMaster Clock
PBAPeripheral Bus A clock
PHAQuadrature Decoder input signal Phase A
PHBQuadrature Decoder input signal Phase B
QDECQuadrature Decoder
QSGQuick Start Guide
RARegister A
RBRegister B
RCRegister C
TIOBTimer Input Output B
- * - * - * \section asfdoc_sam_drivers_tc_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref clk_group "System Clock Management (sysclock)" - * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver" - * - \ref asfdoc_sam_drivers_pmc_group "Power Manager Controller (PMC) driver" - * - * - * \section asfdoc_sam_drivers_tc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam_drivers_tc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial document release
- */ - -/** - * \page asfdoc_sam_drivers_tc_exqsg Examples for Timer Counter - * - * This is a list of the available Quick Start Guides (QSGs) and example - * applications for \ref asfdoc_sam_drivers_tc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam_drivers_tc_qsg - * - \subpage asfdoc_sam_drivers_tc_example - * - * \page asfdoc_sam_drivers_tc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42301B07/2015Updated title of application note and added list of supported devices
42301A05/2014Initial document release
- * - */ - -/** - * \page asfdoc_sam_drivers_tc_qsg Quick Start Guide for the TC driver - * - * This is the quick start guide for the \ref asfdoc_sam_drivers_tc_group, with - * step-by-step instructions on how to configure and use the driver for - * a specific use case. The code examples can be copied into the main - * application loop or any other function that will need to control the - * AST module. - * - * \section asfdoc_sam_drivers_tc_qsg_use_cases Use Cases - * - \ref asfdoc_sam_drivers_tc_qsg_basic_capture - * - \ref asfdoc_sam_drivers_tc_qsg_basic_waveform - * - * \section asfdoc_sam_drivers_tc_qsg_basic_capture TC Capture Mode Basic Usage - * - * This use case will demonstrate how to initialize the TC module to - * operate in capture mode using interrupts. Note, that the macros - * used to select the TC channel are device specific. Refer to the - * appropriate device-specific datasheet for more information. - * - * - * \section asfdoc_sam_drivers_tc_qsg_basic_capture_setup Setup Steps - * - * \subsection asfdoc_sam_tc_qsg_basic_capture_prereq Prerequisites - * - * This module requires the following services: - * - \ref clk_group "System Clock Management (sysclock)" - * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver" - * - * \subsection asfdoc_sam_drivers_tc_qsg_basic_capture_setup_code Setup Code - * - * Add these macros to the top of your main application C-file: - * \snippet conf_board.h tc_define_peripheral - * \snippet conf_board.h tc_define_ch2 - * \snippet conf_board.h tc_define_irq_handler - * - * Add this macro and functions to your main application C-file: - * \snippet tc_capture_waveform_example.c tc_capture_selection - * \snippet tc_capture_waveform_example.c tc_capture_init - * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_start - * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_end - * - * \subsection asfdoc_sam_drivers_tc_qsg_basic_capture_setup_workflow Workflow - * - * -# Enable the TC module's capture pin: - * \snippet tc_capture_waveform_example.c tc_capture_gpio - * -# Initialize the capture channel to the following: - * - Load RA on the rising edge of TIOA - * - Load RB on the falling edge of TIOA - * - Set the external trigger to TIOA - * - Set the external trigger to falling edge - * \snippet tc_capture_waveform_example.c tc_capture_init_call - * -# Enable the TC interrupt using NVIC: - * \snippet tc_capture_waveform_example.c tc_capture_init_irq - * -# Enable the capture channel interrupt: - * \snippet tc_capture_waveform_example.c tc_capture_init_module_irq - * -# In the \ref TC_Handler_null "TC_Handler()" function, the load. - * RB interrupt can be checked by: - * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_status - * \code } \endcode - * -# In the \ref TC_Handler_null "TC_Handler()" function, the RA value. - * can be read by: - * \code uint32_t gs_ul_captured_ra; \endcode - * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_read_ra - * -# In the \ref TC_Handler_null "TC_Handler()" function, the RB value. - * can be read by: - * \code uint32_t gs_ul_captured_rb; \endcode - * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_read_rb - * - * \section asfdoc_sam_drivers_tc_qsg_basic_waveform TC Waveform Mode Basic Usage - * - * This use case will demonstrate how to initialize the TC module to - * operate in waveform mode. Note, that the macros used to select - * the TC channel are device specific. Refer to the appropriate - * device-specific datasheet for more information. - * - * - * \section asfdoc_sam_drivers_tc_qsg_basic_waveform_setup Setup Steps - * - * \subsection asfdoc_sam_tc_qsg_basic_waveform_prereq Prerequisites - * - * This module requires the following services: - * - \ref clk_group "System Clock Management (sysclock)" - * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver" - * - * \subsection asfdoc_sam_drivers_tc_qsg_basic_waveform_setup_code Setup Code - * - * Add these macros to the top of your main application C-file: - * \snippet conf_board.h tc_define_peripheral - * \snippet conf_board.h tc_define_ch1 - * - * Add these macros and function to your main application C-file: - * \code #define TC_WAVEFORM_TIMER_SELECTION TC_CMR_TCCLKS_TIMER_CLOCK4 \endcode - * \code #define TC_WAVEFORM_DIVISOR 128 \endcode - * \code #define TC_WAVEFORM_FREQUENCY 178 \endcode - * \code #define TC_WAVEFORM_DUTY_CYCLE 30 \endcode - * \code - * static void tc_waveform_initialize(void) - * { - * uint32_t ra, rc; - * - * // Configure the PMC to enable the TC module. - * sysclk_enable_peripheral_clock(ID_TC_WAVEFORM); - * - * // Init TC to waveform mode. - * tc_init(TC, TC_CHANNEL_WAVEFORM, - * TC_WAVEFORM_TIMER_SELECTION // Waveform Clock Selection - * | TC_CMR_WAVE // Waveform mode is enabled - * | TC_CMR_ACPA_SET // RA Compare Effect: set - * | TC_CMR_ACPC_CLEAR // RC Compare Effect: clear - * | TC_CMR_CPCTRG // UP mode with automatic trigger on RC Compare - * ); - * - * // Configure waveform frequency and duty cycle. - * rc = (sysclk_get_peripheral_bus_hz(TC) / - * TC_WAVEFORM_DIVISOR / - * TC_WAVEFORM_FREQUENCY; - * tc_write_rc(TC, TC_CHANNEL_WAVEFORM, rc); - * ra = (100 - TC_WAVEFORM_FREQUENCY_DUTY_CYCLE * rc / 100; - * tc_write_ra(TC, TC_CHANNEL_WAVEFORM, ra); - * - * // Enable TC TC_CHANNEL_WAVEFORM. - * tc_start(TC, TC_CHANNEL_WAVEFORM); - * } \endcode - * - * \subsection asfdoc_sam_drivers_tc_qsg_basic_waveform_setup_workflow Workflow - * - * -# Enable the TC module's waveform pin: - * \snippet tc_capture_waveform_example.c tc_waveform_gpio - * -# Initialize the waveform channel to the following: - * - Output frequency of 178Hz, with a duty-cycle of 30% - * - Use TC_CMR_TCCLKS_TIMER_CLOCK4, with a divisor of 128 - * \snippet tc_capture_waveform_example.c tc_waveform_init_call - */ -#endif /* TC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.c deleted file mode 100644 index 268f56287ba..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.c +++ /dev/null @@ -1,744 +0,0 @@ -/** - * \file - * - * \brief Two-Wire Interface (TWI) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "twi.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \defgroup sam_drivers_twi_group Two-Wire Interface (TWI) - * - * Driver for the TWI (Two-Wire Interface). This driver provides access to the main - * features of the TWI controller. - * The TWI interconnects components on a unique two-wire bus. - * The TWI is programmable as a master or a slave with sequential or single-byte access. - * Multiple master capability is supported. - * - * \par Usage - * - * -# Enable the TWI peripheral clock in the PMC. - * -# Enable the required TWI PIOs (see pio.h). - * -# Enable TWI master mode by calling twi_enable_master_mode if it is a master on the I2C bus. - * -# Configure the TWI in master mode by calling twi_master_init. - * -# Send data to a slave device on the I2C bus by calling twi_master_write. - * -# Receive data from a slave device on the I2C bus by calling the twi_master_read. - * -# Enable TWI slave mode by calling twi_enable_slave_mode if it is a slave on the I2C bus. - * -# Configure the TWI in slave mode by calling twi_slave_init. - * - * @{ - */ - -#define I2C_FAST_MODE_SPEED 400000 -#define TWI_CLK_DIVIDER 2 -#define TWI_CLK_CALC_ARGU 4 -#define TWI_CLK_DIV_MAX 0xFF -#define TWI_CLK_DIV_MIN 7 - -#define TWI_WP_KEY_VALUE TWI_WPMR_WPKEY_PASSWD - - /** - * \brief Enable TWI master mode. - * - * \param p_twi Pointer to a TWI instance. - */ - void twi_enable_master_mode(Twi *p_twi) -{ - /* Set Master Disable bit and Slave Disable bit */ - p_twi->TWI_CR = TWI_CR_MSDIS; - p_twi->TWI_CR = TWI_CR_SVDIS; - - /* Set Master Enable bit */ - p_twi->TWI_CR = TWI_CR_MSEN; -} - -/** - * \brief Disable TWI master mode. - * - * \param p_twi Pointer to a TWI instance. - */ -void twi_disable_master_mode(Twi *p_twi) -{ - /* Set Master Disable bit */ - p_twi->TWI_CR = TWI_CR_MSDIS; -} - -/** - * \brief Initialize TWI master mode. - * - * \param p_twi Pointer to a TWI instance. - * \param p_opt Options for initializing the TWI module (see \ref twi_options_t). - * - * \return TWI_SUCCESS if initialization is complete, error code otherwise. - */ -uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt) -{ - uint32_t status = TWI_SUCCESS; - - /* Disable TWI interrupts */ - p_twi->TWI_IDR = ~0UL; - - /* Dummy read in status register */ - p_twi->TWI_SR; - - /* Reset TWI peripheral */ - twi_reset(p_twi); - - twi_enable_master_mode(p_twi); - - /* Select the speed */ - if (twi_set_speed(p_twi, p_opt->speed, p_opt->master_clk) == FAIL) { - /* The desired speed setting is rejected */ - status = TWI_INVALID_ARGUMENT; - } - - if (p_opt->smbus == 1) { - p_twi->TWI_CR = TWI_CR_QUICK; - } - - return status; -} - -/** - * \brief Set the I2C bus speed in conjunction with the clock frequency. - * - * \param p_twi Pointer to a TWI instance. - * \param ul_speed The desired I2C bus speed (in Hz). - * \param ul_mck Main clock of the device (in Hz). - * - * \retval PASS New speed setting is accepted. - * \retval FAIL New speed setting is rejected. - */ -uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck) -{ - uint32_t ckdiv = 0; - uint32_t c_lh_div; - - if (ul_speed > I2C_FAST_MODE_SPEED) { - return FAIL; - } - - c_lh_div = ul_mck / (ul_speed * TWI_CLK_DIVIDER) - TWI_CLK_CALC_ARGU; - - /* cldiv must fit in 8 bits, ckdiv must fit in 3 bits */ - while ((c_lh_div > TWI_CLK_DIV_MAX) && (ckdiv < TWI_CLK_DIV_MIN)) { - /* Increase clock divider */ - ckdiv++; - /* Divide cldiv value */ - c_lh_div /= TWI_CLK_DIVIDER; - } - - /* set clock waveform generator register */ - p_twi->TWI_CWGR = - TWI_CWGR_CLDIV(c_lh_div) | TWI_CWGR_CHDIV(c_lh_div) | - TWI_CWGR_CKDIV(ckdiv); - - return PASS; -} - -/** - * \brief Test if a chip answers a given I2C address. - * - * \param p_twi Pointer to a TWI instance. - * \param uc_slave_addr Address of the remote chip to search for. - * - * \return TWI_SUCCESS if a chip was found, error code otherwise. - */ -uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr) -{ - twi_packet_t packet; - uint8_t data = 0; - - /* Data to send */ - packet.buffer = &data; - /* Data length */ - packet.length = 1; - /* Slave chip address */ - packet.chip = (uint32_t) uc_slave_addr; - /* Internal chip address */ - packet.addr[0] = 0; - /* Address length */ - packet.addr_length = 0; - - /* Perform a master write access */ - return (twi_master_write(p_twi, &packet)); -} - - -/** - * \internal - * \brief Construct the TWI module address register field - * - * The TWI module address register is sent out MSB first. And the size controls - * which byte is the MSB to start with. - * - * Please see the device datasheet for details on this. - */ -static uint32_t twi_mk_addr(const uint8_t *addr, int len) -{ - uint32_t val; - - if (len == 0) - return 0; - - val = addr[0]; - if (len > 1) { - val <<= 8; - val |= addr[1]; - } - if (len > 2) { - val <<= 8; - val |= addr[2]; - } - return val; -} - -/** - * \brief Read multiple bytes from a TWI compatible slave device. - * - * \note This function will NOT return until all data has been read or error occurs. - * - * \param p_twi Pointer to a TWI instance. - * \param p_packet Packet information and data (see \ref twi_packet_t). - * - * \return TWI_SUCCESS if all bytes were read, error code otherwise. - */ -uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet) -{ - uint32_t status; - uint32_t cnt = p_packet->length; - uint8_t *buffer = p_packet->buffer; - uint8_t stop_sent = 0; - uint32_t timeout = TWI_TIMEOUT;; - - /* Check argument */ - if (cnt == 0) { - return TWI_INVALID_ARGUMENT; - } - - /* Set read mode, slave address and 3 internal address byte lengths */ - p_twi->TWI_MMR = 0; - p_twi->TWI_MMR = TWI_MMR_MREAD | TWI_MMR_DADR(p_packet->chip) | - ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) & - TWI_MMR_IADRSZ_Msk); - - /* Set internal address for remote chip */ - p_twi->TWI_IADR = 0; - p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length); - - /* Send a START condition */ - if (cnt == 1) { - p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP; - stop_sent = 1; - } else { - p_twi->TWI_CR = TWI_CR_START; - stop_sent = 0; - } - - while (cnt > 0) { - status = p_twi->TWI_SR; - if (status & TWI_SR_NACK) { - return TWI_RECEIVE_NACK; - } - - if (!timeout--) { - return TWI_ERROR_TIMEOUT; - } - - /* Last byte ? */ - if (cnt == 1 && !stop_sent) { - p_twi->TWI_CR = TWI_CR_STOP; - stop_sent = 1; - } - - if (!(status & TWI_SR_RXRDY)) { - continue; - } - *buffer++ = p_twi->TWI_RHR; - - cnt--; - timeout = TWI_TIMEOUT; - } - - while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) { - } - - p_twi->TWI_SR; - - return TWI_SUCCESS; -} - -/** - * \brief Write multiple bytes to a TWI compatible slave device. - * - * \note This function will NOT return until all data has been written or error occurred. - * - * \param p_twi Pointer to a TWI instance. - * \param p_packet Packet information and data (see \ref twi_packet_t). - * - * \return TWI_SUCCESS if all bytes were written, error code otherwise. - */ -uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet) -{ - uint32_t status; - uint32_t cnt = p_packet->length; - uint8_t *buffer = p_packet->buffer; - - /* Check argument */ - if (cnt == 0) { - return TWI_INVALID_ARGUMENT; - } - - /* Set write mode, slave address and 3 internal address byte lengths */ - p_twi->TWI_MMR = 0; - p_twi->TWI_MMR = TWI_MMR_DADR(p_packet->chip) | - ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) & - TWI_MMR_IADRSZ_Msk); - - /* Set internal address for remote chip */ - p_twi->TWI_IADR = 0; - p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length); - - /* Send all bytes */ - while (cnt > 0) { - status = p_twi->TWI_SR; - if (status & TWI_SR_NACK) { - return TWI_RECEIVE_NACK; - } - - if (!(status & TWI_SR_TXRDY)) { - continue; - } - p_twi->TWI_THR = *buffer++; - - cnt--; - } - - while (1) { - status = p_twi->TWI_SR; - if (status & TWI_SR_NACK) { - return TWI_RECEIVE_NACK; - } - - if (status & TWI_SR_TXRDY) { - break; - } - } - - p_twi->TWI_CR = TWI_CR_STOP; - - while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) { - } - - return TWI_SUCCESS; -} - -/** - * \brief Enable TWI interrupts. - * - * \param p_twi Pointer to a TWI instance. - * \param ul_sources Interrupts to be enabled. - */ -void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources) -{ - /* Enable the specified interrupts */ - p_twi->TWI_IER = ul_sources; -} - -/** - * \brief Disable TWI interrupts. - * - * \param p_twi Pointer to a TWI instance. - * \param ul_sources Interrupts to be disabled. - */ -void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources) -{ - /* Disable the specified interrupts */ - p_twi->TWI_IDR = ul_sources; - /* Dummy read */ - p_twi->TWI_SR; -} - -/** - * \brief Get TWI interrupt status. - * - * \param p_twi Pointer to a TWI instance. - * - * \retval TWI interrupt status. - */ -uint32_t twi_get_interrupt_status(Twi *p_twi) -{ - return p_twi->TWI_SR; -} - -/** - * \brief Read TWI interrupt mask. - * - * \param p_twi Pointer to a TWI instance. - * - * \return The interrupt mask value. - */ -uint32_t twi_get_interrupt_mask(Twi *p_twi) -{ - return p_twi->TWI_IMR; -} - -/** - * \brief Reads a byte from the TWI bus. - * - * \param p_twi Pointer to a TWI instance. - * - * \return The byte read. - */ -uint8_t twi_read_byte(Twi *p_twi) -{ - return p_twi->TWI_RHR; -} - -/** - * \brief Sends a byte of data to one of the TWI slaves on the bus. - * - * \param p_twi Pointer to a TWI instance. - * \param byte The byte to send. - */ -void twi_write_byte(Twi *p_twi, uint8_t uc_byte) -{ - p_twi->TWI_THR = uc_byte; -} - -/** - * \brief Enable TWI slave mode. - * - * \param p_twi Pointer to a TWI instance. - */ -void twi_enable_slave_mode(Twi *p_twi) -{ - /* Set Master Disable bit and Slave Disable bit */ - p_twi->TWI_CR = TWI_CR_MSDIS; - p_twi->TWI_CR = TWI_CR_SVDIS; - - /* Set Slave Enable bit */ - p_twi->TWI_CR = TWI_CR_SVEN; -} - -/** - * \brief Disable TWI slave mode. - * - * \param p_twi Pointer to a TWI instance. - */ -void twi_disable_slave_mode(Twi *p_twi) -{ - /* Set Slave Disable bit */ - p_twi->TWI_CR = TWI_CR_SVDIS; -} - -/** - * \brief Initialize TWI slave mode. - * - * \param p_twi Pointer to a TWI instance. - * \param ul_device_addr Device address of the SAM slave device on the I2C bus. - */ -void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr) -{ - /* Disable TWI interrupts */ - p_twi->TWI_IDR = ~0UL; - p_twi->TWI_SR; - - /* Reset TWI */ - twi_reset(p_twi); - - /* Set slave address in slave mode */ - p_twi->TWI_SMR = TWI_SMR_SADR(ul_device_addr); - - /* Enable slave mode */ - twi_enable_slave_mode(p_twi); -} - -/** - * \brief Set TWI slave address. - * - * \param p_twi Pointer to a TWI instance. - * \param ul_device_addr Device address of the SAM slave device on the I2C bus. - */ -void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr) -{ - /* Set slave address */ - p_twi->TWI_SMR = TWI_SMR_SADR(ul_device_addr); -} - -/** - * \brief Read data from master. - * - * \note This function will NOT return until master sends a STOP condition. - * - * \param p_twi Pointer to a TWI instance. - * \param p_data Pointer to the data buffer where data received will be stored. - * - * \return Number of bytes read. - */ -uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data) -{ - uint32_t status, cnt = 0; - - do { - status = p_twi->TWI_SR; - if (status & TWI_SR_SVACC) { - if (!(status & TWI_SR_GACC) && - ((status & (TWI_SR_SVREAD | TWI_SR_RXRDY)) - == (TWI_SR_SVREAD | TWI_SR_RXRDY))) { - *p_data++ = (uint8_t) p_twi->TWI_RHR; - cnt++; - } - } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP)) - == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) { - break; - } - } while (1); - - return cnt; -} - -/** - * \brief Write data to TWI bus. - * - * \note This function will NOT return until master sends a STOP condition. - * - * \param p_twi Pointer to a TWI instance. - * \param p_data Pointer to the data buffer to be sent. - * - * \return Number of bytes written. - */ -uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data) -{ - uint32_t status, cnt = 0; - - do { - status = p_twi->TWI_SR; - if (status & TWI_SR_SVACC) { - if (!(status & (TWI_SR_GACC | TWI_SR_SVREAD)) && - (status & TWI_SR_TXRDY)) { - p_twi->TWI_THR = *p_data++; - cnt++; - } - } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP)) - == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) { - break; - } - } while (1); - - return cnt; -} - -/** - * \brief Reset TWI. - * - * \param p_twi Pointer to a TWI instance. - */ -void twi_reset(Twi *p_twi) -{ - /* Set SWRST bit to reset TWI peripheral */ - p_twi->TWI_CR = TWI_CR_SWRST; - p_twi->TWI_RHR; -} - -/** - * \brief Get TWI PDC base address. - * - * \param p_twi Pointer to a TWI instance. - * - * \return TWI PDC registers base for PDC driver to access. - */ -Pdc *twi_get_pdc_base(Twi *p_twi) -{ - Pdc *p_pdc_base = NULL; -#if !SAMG - if (p_twi == TWI0) { - p_pdc_base = PDC_TWI0; - } else -#endif -#ifdef PDC_TWI1 - if (p_twi == TWI1) { - p_pdc_base = PDC_TWI1; - } else -#endif -#ifdef PDC_TWI2 - if (p_twi == TWI2) { - p_pdc_base = PDC_TWI2; - } else -#endif - { - Assert(false); - } - - return p_pdc_base; -} - -#if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM) -/** - * \brief Enables/Disables write protection mode. - * - * \param p_twi Pointer to a TWI instance. - * \param flag ture for enable, false for disable. - */ -void twi_set_write_protection(Twi *p_twi, bool flag) -{ - - p_twi->TWI_WPMR = (flag ? TWI_WPMR_WPEN : 0) | TWI_WP_KEY_VALUE; -} - -/** - * \brief Read the write protection status. - * - * \param p_twi Pointer to a TWI instance. - * \param p_status Pointer to save the status. - */ -void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status) -{ - - *p_status = p_twi->TWI_WPSR; -} -#endif - -#if SAMG55 -/** - * \brief Set the prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles for SMBUS mode. - * - * \param p_twi Base address of the TWI instance. - * \param ul_timing Parameter for prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles. - */ -void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing) -{ - p_twi->TWI_SMBTR = ul_timing;; -} - -/** - * \brief Set length/direction/PEC for alternative command mode. - * - * \param p_twi Base address of the TWI instance. - * \param ul_alt_cmd Alternative command parameters. - */ -void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd) -{ - p_twi->TWI_ACR = ul_alt_cmd;; -} - -/** - * \brief Set the filter for TWI. - * - * \param p_twi Base address of the TWI instance. - * \param ul_filter Filter value. - */ -void twi_set_filter(Twi *p_twi, uint32_t ul_filter) -{ - p_twi->TWI_FILTR = ul_filter;; -} - -/** - * \brief A mask can be applied on the slave device address in slave mode in order to allow multiple - * address answer. For each bit of the MASK field set to one the corresponding SADR bit will be masked. - * - * \param p_twi Base address of the TWI instance. - * \param ul_mask Mask value. - */ -void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask) -{ - p_twi->TWI_SMR |= TWI_SMR_MASK(ul_mask); -} - -/** - * \brief Set sleepwalking match mode. - * - * \param p_twi Pointer to a TWI instance. - * \param ul_matching_addr1 Address 1 value. - * \param ul_matching_addr2 Address 2 value. - * \param ul_matching_addr3 Address 3 value. - * \param ul_matching_data Data value. - * \param flag1 ture for set, false for no. - * \param flag2 ture for set, false for no. - * \param flag3 ture for set, false for no. - * \param flag ture for set, false for no. - */ -void twi_set_sleepwalking(Twi *p_twi, - uint32_t ul_matching_addr1, bool flag1, - uint32_t ul_matching_addr2, bool flag2, - uint32_t ul_matching_addr3, bool flag3, - uint32_t ul_matching_data, bool flag) -{ - uint32_t temp = 0; - - if (flag1) { - temp |= TWI_SWMR_SADR1(ul_matching_addr1); - } - - if (flag2) { - temp |= TWI_SWMR_SADR2(ul_matching_addr2); - } - - if (flag3) { - temp |= TWI_SWMR_SADR3(ul_matching_addr3); - } - - if (flag) { - temp |= TWI_SWMR_DATAM(ul_matching_data); - } - - p_twi->TWI_SWMR = temp; -} -#endif -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.h deleted file mode 100644 index 7f1b890f82f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.h +++ /dev/null @@ -1,446 +0,0 @@ -/** - * \file - * - * \brief Two-Wire Interface (TWI) driver for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef TWI_H_INCLUDED -#define TWI_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** Time-out value (number of attempts). */ -#define TWI_TIMEOUT 15000 - - /** - * \brief Return codes for TWI APIs. - * @{ - */ -#define TWI_SUCCESS 0 -#define TWI_INVALID_ARGUMENT 1 -#define TWI_ARBITRATION_LOST 2 -#define TWI_NO_CHIP_FOUND 3 -#define TWI_RECEIVE_OVERRUN 4 -#define TWI_RECEIVE_NACK 5 -#define TWI_SEND_OVERRUN 6 -#define TWI_SEND_NACK 7 -#define TWI_BUSY 8 -#define TWI_ERROR_TIMEOUT 9 - /** - * @} - */ - - /** - * \brief Input parameters when initializing the TWI module mode. - */ - typedef struct twi_options { - //! MCK for TWI. - uint32_t master_clk; - //! The baud rate of the TWI bus. - uint32_t speed; - //! The desired address. - uint8_t chip; - //! SMBUS mode (set 1 to use SMBUS quick command, otherwise don't). - uint8_t smbus; - } twi_options_t; - - /** - * \brief Information concerning the data transmission. - */ - typedef struct twi_packet { - //! TWI address/commands to issue to the other chip (node). - uint8_t addr[3]; - //! Length of the TWI data address segment (1-3 bytes). - uint32_t addr_length; - //! Where to find the data to be transferred. - void *buffer; - //! How many bytes do we want to transfer. - uint32_t length; - //! TWI chip address to communicate with. - uint8_t chip; - } twi_packet_t; - -#if SAMG55 -enum twi_source_clock { - TWI_SOURCE_PERIPH_CLK = TWI_CWGR_BRSRCCLK_PERIPH_CLK, - TWI_SOURCE_PCK_CLK = TWI_CWGR_BRSRCCLK_PMC_PCK, -}; -#endif - -void twi_enable_master_mode(Twi *p_twi); -void twi_disable_master_mode(Twi *p_twi); -uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt); -uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck); -uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr); -uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet); -uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet); -void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources); -void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources); -uint32_t twi_get_interrupt_status(Twi *p_twi); -uint32_t twi_get_interrupt_mask(Twi *p_twi); -uint8_t twi_read_byte(Twi *p_twi); -void twi_write_byte(Twi *p_twi, uint8_t uc_byte); -void twi_enable_slave_mode(Twi *p_twi); -void twi_disable_slave_mode(Twi *p_twi); -void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr); -void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr); -uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data); -uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data); -void twi_reset(Twi *p_twi); -Pdc *twi_get_pdc_base(Twi *p_twi); -#if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM) -void twi_set_write_protection(Twi *p_twi, bool flag); -void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status); -#endif - -#if SAMG55 -void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing); -void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd); -void twi_set_filter(Twi *p_twi, uint32_t ul_filter); -void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask); -void twi_set_sleepwalking(Twi *p_twi, - uint32_t ul_matching_addr1, bool flag1, - uint32_t ul_matching_addr2, bool flag2, - uint32_t ul_matching_addr3, bool flag3, - uint32_t ul_matching_data, bool flag); - -/** - * \brief Enable high speed mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_highspeed(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_HSEN; -} - -/** - * \brief Disable high speed mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_highspeed(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_HSDIS; -} - -/** - * \brief Enable SMBus mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_smbus(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_SMBEN; -} - -/** - * \brief Disable SMBus mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_smbus(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_SMBDIS; -} - -/** - * \brief Enable packet error checking. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_pec(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_PECEN; -} - -/** - * \brief Disable packet error checking. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_pec(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_PECDIS; -} - -/** - * \brief Request a packet error checking. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_request_pec(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_PECRQ; -} - -/** - * \brief If master mode is enabled, send a bus clear command. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_send_clear(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_CLEAR; -} - -/** - * \brief Enable alternative command mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_alternative_command(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_ACMEN; -} - -/** - * \brief Enable alternative command mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_alternative_command(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_ACMDIS; -} - -/** - * \brief Clear the Transmit Holding Register and set TXRDY, TXCOMP flags. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_thr_clear(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_THRCLR; -} - -/** - * \brief Clear the TWI FSM lock. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_lock_clear(Twi *p_twi) -{ - p_twi->TWI_CR = TWI_CR_LOCKCLR; -} - -/** - * \brief Normal value to be returned in the ACK cycle of the data phase in slave receiver mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_slave_nack(Twi *p_twi) -{ - p_twi->TWI_SMR &= ~TWI_SMR_NACKEN; -} - -/** - * \brief NACK value to be returned in the ACK cycle of the data phase in slave receiver mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_slave_nack(Twi *p_twi) -{ - p_twi->TWI_SMR |= TWI_SMR_NACKEN; -} - -/** - * \brief Acknowledge of the SMBus Default Address disabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_slave_default_addr(Twi *p_twi) -{ - p_twi->TWI_SMR &= ~TWI_SMR_SMDA; -} - -/** - * \brief Acknowledge of the SMBus Default Address enabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_slave_default_addr(Twi *p_twi) -{ - p_twi->TWI_SMR |= TWI_SMR_SMDA; -} - -/** - * \brief Acknowledge of the SMBus Host Header disabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_smbus_host_header(Twi *p_twi) -{ - p_twi->TWI_SMR &= ~TWI_SMR_SMHH; -} - -/** - * \brief Acknowledge of the SMBus Host Header enabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_smbus_host_header(Twi *p_twi) -{ - p_twi->TWI_SMR |= TWI_SMR_SMHH; -} - -/** - * \brief Clock stretching disabled in slave mode, OVRE and UNRE will indicate overrun and underrun. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_clock_wait_state(Twi *p_twi) -{ - p_twi->TWI_SMR |= TWI_SMR_SCLWSDIS; -} - -/** - * \brief Clear clock wait state disable mode. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_clear_disable_clock_wait_state(Twi *p_twi) -{ - p_twi->TWI_SMR &= ~TWI_SMR_SCLWSDIS; -} - -/** - * \brief Slave Address 1 matching disabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_slave_addr1_matching(Twi *p_twi) -{ - p_twi->TWI_SMR &= ~TWI_SMR_SADR1EN; -} - -/** - * \brief Slave Address 1 matching enabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_slave_addr1_matching(Twi *p_twi) -{ - p_twi->TWI_SMR |= TWI_SMR_SADR1EN; -} - -/** - * \brief Slave Address 2 matching disabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_slave_addr2_matching(Twi *p_twi) -{ - p_twi->TWI_SMR &= ~TWI_SMR_SADR2EN; -} - -/** - * \brief Slave Address 2 matching enabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_slave_addr2_matching(Twi *p_twi) -{ - p_twi->TWI_SMR |= TWI_SMR_SADR2EN; -} - -/** - * \brief Slave Address 3 matching disabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_slave_addr3_matching(Twi *p_twi) -{ - p_twi->TWI_SMR &= ~TWI_SMR_SADR3EN; -} - -/** - * \brief Slave Address 3 matching enabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_enable_slave_addr3_matching(Twi *p_twi) -{ - p_twi->TWI_SMR |= TWI_SMR_SADR3EN; -} - -/** - * \brief First received data matching disabled. - * - * \param p_twi Base address of the TWI instance. - */ -static inline void twi_disable_slave_data_matching(Twi *p_twi) -{ - p_twi->TWI_SMR &= ~TWI_SMR_DATAMEN; -} - -/** - * \brief Select the souce clock for the bit rate generation. - * - * \param p_twi Base address of the TWI instance. - * \param src_clk Source clock. - */ -static inline void twi_select_source_clock(Twi *p_twi, enum twi_source_clock src_clk) -{ - p_twi->TWI_CWGR &= ~TWI_CWGR_BRSRCCLK; - p_twi->TWI_CWGR |= src_clk; -} -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* TWI_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.c deleted file mode 100644 index b3aa059c42f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.c +++ /dev/null @@ -1,2102 +0,0 @@ -/** - * \file - * - * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver - * for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "usart.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous - * Receiver Transmitter (USART) - * - * The Universal Synchronous Asynchronous Receiver Transceiver (USART) - * provides one full duplex universal synchronous asynchronous serial link. - * Data frame format is widely programmable (data length, parity, number of - * stop bits) to support a maximum of standards. The receiver implements - * parity error, framing error and overrun error detection. The receiver - * time-out enables handling variable-length frames and the transmitter - * timeguard facilitates communications with slow remote devices. Multidrop - * communications are also supported through address bit handling in reception - * and transmission. The driver supports the following modes: - * RS232, RS485, SPI, IrDA, ISO7816, MODEM, Hardware handshaking and LIN. - * - * @{ - */ - - /* The write protect key value. */ -#ifndef US_WPMR_WPKEY_PASSWD -#define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(0x555341U) -#endif - -#ifndef US_WPMR_WPKEY_PASSWD -# define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE) -#endif - - /* The CD value scope programmed in MR register. */ -#define MIN_CD_VALUE 0x01 -#define MIN_CD_VALUE_SPI 0x04 -#define MAX_CD_VALUE US_BRGR_CD_Msk - - /* The receiver sampling divide of baudrate clock. */ -#define HIGH_FRQ_SAMPLE_DIV 16 -#define LOW_FRQ_SAMPLE_DIV 8 - - /* Max transmitter timeguard. */ -#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk - - /* The non-existent parity error number. */ -#define USART_PARITY_ERROR 5 - - /* ISO7816 protocol type. */ -#define ISO7816_T_0 0 -#define ISO7816_T_1 1 - - /** - * \brief Calculate a clock divider(CD) and a fractional part (FP) for the - * USART asynchronous modes to generate a baudrate as close as possible to - * the baudrate set point. - * - * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8)) - * (Over being 16 or 8). The maximal oversampling is selected if it allows to - * generate a baudrate close to the set point. - * - * \param p_usart Pointer to a USART instance. - * \param baudrate Baud rate set point. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 Baud rate is successfully initialized. - * \retval 1 Baud rate set point is out of range for the given input clock - * frequency. - */ - uint32_t usart_set_async_baudrate(Usart *p_usart, - uint32_t baudrate, uint32_t ul_mck) -{ - uint32_t over; - uint32_t cd_fp; - uint32_t cd; - uint32_t fp; - - /* Calculate the receiver sampling divide of baudrate clock. */ - if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) { - over = HIGH_FRQ_SAMPLE_DIV; - } else { - over = LOW_FRQ_SAMPLE_DIV; - } - - /* Calculate clock divider according to the fraction calculated formula. */ - cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate); - cd = cd_fp >> 3; - fp = cd_fp & 0x07; - if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { - return 1; - } - - /* Configure the OVER bit in MR register. */ - if (over == 8) { - p_usart->US_MR |= US_MR_OVER; - } - - /* Configure the baudrate generate register. */ - p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos); - - return 0; -} - -/** - * \brief Calculate a clock divider for the USART synchronous master modes - * to generate a baudrate as close as possible to the baudrate set point. - * - * \note Synchronous baudrate calculation: baudrate = ul_mck / cd - * - * \param p_usart Pointer to a USART instance. - * \param baudrate Baud rate set point. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 Baud rate is successfully initialized. - * \retval 1 Baud rate set point is out of range for the given input clock - * frequency. - */ -static uint32_t usart_set_sync_master_baudrate(Usart *p_usart, - uint32_t baudrate, uint32_t ul_mck) -{ - uint32_t cd; - - /* Calculate clock divider according to the formula in synchronous mode. */ - cd = (ul_mck + baudrate / 2) / baudrate; - - if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { - return 1; - } - - /* Configure the baudrate generate register. */ - p_usart->US_BRGR = cd << US_BRGR_CD_Pos; - - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | - US_MR_USCLKS_MCK | US_MR_SYNC; - return 0; -} - -/** - * \brief Select the SCK pin as the source of baud rate for the USART - * synchronous slave modes. - * - * \param p_usart Pointer to a USART instance. - */ -static void usart_set_sync_slave_baudrate(Usart *p_usart) -{ - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | - US_MR_USCLKS_SCK | US_MR_SYNC; -} - -/** - * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to - * generate a baud rate as close as possible to the baud rate set point. - * - * \note Baud rate calculation: - * \f$ Baudrate = \frac{SelectedClock}{CD} \f$. - * - * \param p_usart Pointer to a USART instance. - * \param baudrate Baud rate set point. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 Baud rate is successfully initialized. - * \retval 1 Baud rate set point is out of range for the given input clock - * frequency. - */ -static uint32_t usart_set_spi_master_baudrate(Usart *p_usart, - uint32_t baudrate, uint32_t ul_mck) -{ - uint32_t cd; - - /* Calculate the clock divider according to the formula in SPI mode. */ - cd = (ul_mck + baudrate / 2) / baudrate; - - if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) { - return 1; - } - - p_usart->US_BRGR = cd << US_BRGR_CD_Pos; - - return 0; -} - -/** - * \brief Select the SCK pin as the source of baudrate for the USART SPI slave - * mode. - * - * \param p_usart Pointer to a USART instance. - */ -static void usart_set_spi_slave_baudrate(Usart *p_usart) -{ - p_usart->US_MR &= ~US_MR_USCLKS_Msk; - p_usart->US_MR |= US_MR_USCLKS_SCK; -} - -/** - * \brief Reset the USART and disable TX and RX. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_reset(Usart *p_usart) -{ - /* Disable the Write Protect. */ - usart_disable_writeprotect(p_usart); - - /* Reset registers that could cause unpredictable behavior after reset. */ - p_usart->US_MR = 0; - p_usart->US_RTOR = 0; - p_usart->US_TTGR = 0; - - /* Disable TX and RX. */ - usart_reset_tx(p_usart); - usart_reset_rx(p_usart); - /* Reset status bits. */ - usart_reset_status(p_usart); - /* Turn off RTS and DTR if exist. */ - usart_drive_RTS_pin_high(p_usart); -#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) - usart_drive_DTR_pin_high(p_usart); -#endif -} - -/** - * \brief Configure USART to work in RS232 mode. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_rs232(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) -{ - static uint32_t ul_reg_val; - - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - ul_reg_val = 0; - /* Check whether the input values are legal. */ - if (!p_usart_opt || usart_set_async_baudrate(p_usart, - p_usart_opt->baudrate, ul_mck)) { - return 1; - } - - /* Configure the USART option. */ - ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | - p_usart_opt->channel_mode | p_usart_opt->stop_bits; - - /* Configure the USART mode as normal mode. */ - ul_reg_val |= US_MR_USART_MODE_NORMAL; - - p_usart->US_MR |= ul_reg_val; - - return 0; -} - -/** - * \brief Configure USART to work in hardware handshaking mode. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_hw_handshaking(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) -{ - /* Initialize the USART as standard RS232. */ - if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { - return 1; - } - - /* Set hardware handshaking mode. */ - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | - US_MR_USART_MODE_HW_HANDSHAKING; - - return 0; -} - -#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) - -/** - * \brief Configure USART to work in modem mode. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_modem(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) -{ - /* - * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1, - * SAM3U and SAM4L series support MODEM mode only on USART0. - */ -#if (SAM3S || SAM4S || SAM4E) -#ifdef USART1 - if (p_usart != USART1) { - return 1; - } -#endif -#elif (SAM3U || SAM4L) - if (p_usart != USART0) { - return 1; - } -#endif - - /* Initialize the USART as standard RS232. */ - if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { - return 1; - } - - /* Set MODEM mode. */ - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | - US_MR_USART_MODE_MODEM; - - return 0; -} -#endif - -/** - * \brief Configure USART to work in SYNC mode and act as a master. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_sync_master(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) -{ - static uint32_t ul_reg_val; - - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - ul_reg_val = 0; - /* Check whether the input values are legal. */ - if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart, - p_usart_opt->baudrate, ul_mck)) { - return 1; - } - - /* Configure the USART option. */ - ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | - p_usart_opt->channel_mode | p_usart_opt->stop_bits; - - /* Set normal mode and output clock as synchronous master. */ - ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO; - p_usart->US_MR |= ul_reg_val; - - return 0; -} - -/** - * \brief Configure USART to work in SYNC mode and act as a slave. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_sync_slave(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt) -{ - static uint32_t ul_reg_val; - - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - ul_reg_val = 0; - usart_set_sync_slave_baudrate(p_usart); - - /* Check whether the input values are legal. */ - if (!p_usart_opt) { - return 1; - } - - /* Configure the USART option. */ - ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | - p_usart_opt->channel_mode | p_usart_opt->stop_bits; - - /* Set normal mode. */ - ul_reg_val |= US_MR_USART_MODE_NORMAL; - p_usart->US_MR |= ul_reg_val; - - return 0; -} - -/** - * \brief Configure USART to work in RS485 mode. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_rs485(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) -{ - /* Initialize the USART as standard RS232. */ - if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { - return 1; - } - - /* Set RS485 mode. */ - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | - US_MR_USART_MODE_RS485; - - return 0; -} - -#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) -/** - * \brief Configure USART to work in IrDA mode. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_irda(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) -{ - /* Initialize the USART as standard RS232. */ - if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { - return 1; - } - - /* Set IrDA filter. */ - p_usart->US_IF = p_usart_opt->irda_filter; - - /* Set IrDA mode. */ - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | - US_MR_USART_MODE_IRDA; - - return 0; -} -#endif - -#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) -/** - * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to - * generate an ISO7816 clock as close as possible to the clock set point. - * - * \note ISO7816 clock calculation: Clock = ul_mck / cd - * - * \param p_usart Pointer to a USART instance. - * \param clock ISO7816 clock set point. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 ISO7816 clock is successfully initialized. - * \retval 1 ISO7816 clock set point is out of range for the given input clock - * frequency. - */ -static uint32_t usart_set_iso7816_clock(Usart *p_usart, - uint32_t clock, uint32_t ul_mck) -{ - uint32_t cd; - - /* Calculate clock divider according to the formula in ISO7816 mode. */ - cd = (ul_mck + clock / 2) / clock; - - if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { - return 1; - } - - p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC | - US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO; - - /* Configure the baudrate generate register. */ - p_usart->US_BRGR = cd << US_BRGR_CD_Pos; - - return 0; -} - -/** - * \brief Configure USART to work in ISO7816 mode. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_iso7816(Usart *p_usart, - const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck) -{ - static uint32_t ul_reg_val; - - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - ul_reg_val = 0; - - /* Check whether the input values are legal. */ - if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) && - (p_usart_opt->parity_type != US_MR_PAR_ODD))) { - return 1; - } - - if (p_usart_opt->protocol_type == ISO7816_T_0) { - ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT | - (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos); - - if (p_usart_opt->bit_order) { - ul_reg_val |= US_MR_MSBF; - } - } else if (p_usart_opt->protocol_type == ISO7816_T_1) { - /* - * Only LSBF is used in the T=1 protocol, and max_iterations field - * is only used in T=0 mode. - */ - if (p_usart_opt->bit_order || p_usart_opt->max_iterations) { - return 1; - } - - /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */ - ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT; - } else { - return 1; - } - - /* Set up the baudrate. */ - if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) { - return 1; - } - - /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */ - p_usart->US_FIDI = p_usart_opt->fidi_ratio; - - /* Set ISO7816 parity type in the MODE register. */ - ul_reg_val |= p_usart_opt->parity_type; - - if (p_usart_opt->inhibit_nack) { - ul_reg_val |= US_MR_INACK; - } - if (p_usart_opt->dis_suc_nack) { - ul_reg_val |= US_MR_DSNACK; - } - - p_usart->US_MR |= ul_reg_val; - - return 0; -} - -/** - * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_reset_iterations(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RSTIT; -} - -/** - * \brief Reset NACK in US_CSR. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_reset_nack(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RSTNACK; -} - -/** - * \brief Check if one receive buffer is filled. - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 Receive is complete. - * \retval 0 Receive is still pending. - */ -uint32_t usart_is_rx_buf_end(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_ENDRX) > 0; -} - -/** - * \brief Check if one transmit buffer is empty. - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 Transmit is complete. - * \retval 0 Transmit is still pending. - */ -uint32_t usart_is_tx_buf_end(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_ENDTX) > 0; -} - -/** - * \brief Check if both receive buffers are full. - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 Receive buffers are full. - * \retval 0 Receive buffers are not full. - */ -uint32_t usart_is_rx_buf_full(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_RXBUFF) > 0; -} - -/** - * \brief Check if both transmit buffers are empty. - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 Transmit buffers are empty. - * \retval 0 Transmit buffers are not empty. - */ -uint32_t usart_is_tx_buf_empty(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_TXBUFE) > 0; -} - -/** - * \brief Get the total number of errors that occur during an ISO7816 transfer. - * - * \param p_usart Pointer to a USART instance. - * - * \return The number of errors that occurred. - */ -uint8_t usart_get_error_number(Usart *p_usart) -{ - return (p_usart->US_NER & US_NER_NB_ERRORS_Msk); -} - -#endif - -/** - * \brief Configure USART to work in SPI mode and act as a master. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_spi_master(Usart *p_usart, - const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck) -{ - static uint32_t ul_reg_val; - - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - ul_reg_val = 0; - /* Check whether the input values are legal. */ - if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) || - usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, - ul_mck)) { - return 1; - } - - /* Configure the character length bit in MR register. */ - ul_reg_val |= p_usart_opt->char_length; - - /* Set SPI master mode and channel mode. */ - ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO | - p_usart_opt->channel_mode; - - switch (p_usart_opt->spi_mode) { - case SPI_MODE_0: - ul_reg_val |= US_MR_CPHA; - ul_reg_val &= ~US_MR_CPOL; - break; - - case SPI_MODE_1: - ul_reg_val &= ~US_MR_CPHA; - ul_reg_val &= ~US_MR_CPOL; - break; - - case SPI_MODE_2: - ul_reg_val |= US_MR_CPHA; - ul_reg_val |= US_MR_CPOL; - break; - - case SPI_MODE_3: - ul_reg_val &= ~US_MR_CPHA; - ul_reg_val |= US_MR_CPOL; - break; - - default: - break; - } - - p_usart->US_MR |= ul_reg_val; - - return 0; -} - -/** - * \brief Configure USART to work in SPI mode and act as a slave. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param p_usart_opt Pointer to sam_usart_opt_t instance. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_spi_slave(Usart *p_usart, - const usart_spi_opt_t *p_usart_opt) -{ - static uint32_t ul_reg_val; - - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - ul_reg_val = 0; - usart_set_spi_slave_baudrate(p_usart); - - /* Check whether the input values are legal. */ - if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) { - return 1; - } - - /* Configure the character length bit in MR register. */ - ul_reg_val |= p_usart_opt->char_length; - - /* Set SPI slave mode and channel mode. */ - ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode; - - switch (p_usart_opt->spi_mode) { - case SPI_MODE_0: - ul_reg_val |= US_MR_CPHA; - ul_reg_val &= ~US_MR_CPOL; - break; - - case SPI_MODE_1: - ul_reg_val &= ~US_MR_CPHA; - ul_reg_val &= ~US_MR_CPOL; - break; - - case SPI_MODE_2: - ul_reg_val |= US_MR_CPHA; - ul_reg_val |= US_MR_CPOL; - break; - - case SPI_MODE_3: - ul_reg_val |= US_MR_CPOL; - ul_reg_val &= ~US_MR_CPHA; - break; - - default: - break; - } - - p_usart->US_MR |= ul_reg_val; - - return 0; -} - -#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - -/** - * \brief Configure USART to work in LIN mode and act as a LIN master. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param ul_baudrate Baudrate to be used. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate, - uint32_t ul_mck) -{ - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - /* Set up the baudrate. */ - if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { - return 1; - } - - /* Set LIN master mode. */ - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | - US_MR_USART_MODE_LIN_MASTER; - - usart_enable_rx(p_usart); - usart_enable_tx(p_usart); - - return 0; -} - -/** - * \brief Configure USART to work in LIN mode and act as a LIN slave. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param ul_baudrate Baudrate to be used. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, - uint32_t ul_mck) -{ - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - usart_enable_rx(p_usart); - usart_enable_tx(p_usart); - - /* Set LIN slave mode. */ - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | - US_MR_USART_MODE_LIN_SLAVE; - - /* Set up the baudrate. */ - if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { - return 1; - } - - return 0; -} - -/** - * \brief Abort the current LIN transmission. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_abort_tx(Usart *p_usart) -{ - p_usart->US_CR = US_CR_LINABT; -} - -/** - * \brief Send a wakeup signal on the LIN bus. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_send_wakeup_signal(Usart *p_usart) -{ - p_usart->US_CR = US_CR_LINWKUP; -} - -/** - * \brief Configure the LIN node action, which should be one of PUBLISH, - * SUBSCRIBE or IGNORE. - * - * \param p_usart Pointer to a USART instance. - * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE. - */ -void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action) -{ - p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) | - (uc_action << US_LINMR_NACT_Pos); -} - -/** - * \brief Disable the parity check during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_disable_parity(Usart *p_usart) -{ - p_usart->US_LINMR |= US_LINMR_PARDIS; -} - -/** - * \brief Enable the parity check during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_enable_parity(Usart *p_usart) -{ - p_usart->US_LINMR &= ~US_LINMR_PARDIS; -} - -/** - * \brief Disable the checksum during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_disable_checksum(Usart *p_usart) -{ - p_usart->US_LINMR |= US_LINMR_CHKDIS; -} - -/** - * \brief Enable the checksum during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_enable_checksum(Usart *p_usart) -{ - p_usart->US_LINMR &= ~US_LINMR_CHKDIS; -} - -/** - * \brief Configure the checksum type during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic - * checksum. - */ -void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type) -{ - p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) | - (uc_type << 4); -} - -/** - * \brief Configure the data length mode during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - * \param uc_mode Indicate the data length type: 0 if the data length is - * defined by the DLC of LIN mode register or 1 if the data length is defined - * by the bit 5 and 6 of the identifier. - */ -void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode) -{ - p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) | - (uc_mode << 5); -} - -/** - * \brief Disable the frame slot mode during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_disable_frame_slot(Usart *p_usart) -{ - p_usart->US_LINMR |= US_LINMR_FSDIS; -} - -/** - * \brief Enable the frame slot mode during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_enable_frame_slot(Usart *p_usart) -{ - p_usart->US_LINMR &= ~US_LINMR_FSDIS; -} - -/** - * \brief Configure the wakeup signal type during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a - * LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal. - */ -void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type) -{ - p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) | - (uc_type << 7); -} - -/** - * \brief Configure the response data length if the data length is defined by - * the DLC field during the LIN communication. - * - * \param p_usart Pointer to a USART instance. - * \param uc_len Indicate the response data length. - */ -void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len) -{ - p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) | - ((uc_len - 1) << US_LINMR_DLC_Pos); -} - -/** - * \brief The LIN mode register is not written by the PDC. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_disable_pdc_mode(Usart *p_usart) -{ - p_usart->US_LINMR &= ~US_LINMR_PDCM; -} - -/** - * \brief The LIN mode register (except this flag) is written by the PDC. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lin_enable_pdc_mode(Usart *p_usart) -{ - p_usart->US_LINMR |= US_LINMR_PDCM; -} - -/** - * \brief Configure the LIN identifier when USART works in LIN master mode. - * - * \param p_usart Pointer to a USART instance. - * \param uc_id The identifier to be transmitted. - */ -void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id) -{ - p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) | - US_LINIR_IDCHR(uc_id); -} - -/** - * \brief Read the identifier when USART works in LIN mode. - * - * \param p_usart Pointer to a USART instance. - * - * \return The last identifier received in LIN slave mode or the last - * identifier transmitted in LIN master mode. - */ -uint8_t usart_lin_read_identifier(Usart *p_usart) -{ - return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk); -} - -/** - * \brief Get data length. - * - * \param p_usart Pointer to a USART instance. - * - * \return Data length. - */ -uint8_t usart_lin_get_data_length(Usart *usart) -{ - if (usart->US_LINMR & US_LINMR_DLM) { - uint8_t data_length = 1 << ((usart->US_LINIR >> - (US_LINIR_IDCHR_Pos + 4)) & 0x03); - return data_length; - } else { - return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1; - } -} - -#endif - -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) -/** - * \brief Get identifier send status. - * - * \param p_usart Pointer to a USART instance. - * - * \return - * 0: No LIN identifier has been sent since the last RSTSTA. - * 1: :At least one LIN identifier has been sent since the last RSTSTA. - */ -uint8_t usart_lin_identifier_send_complete(Usart *usart) -{ - return (usart->US_CSR & US_CSR_LINID) > 0; -} - -/** - * \brief Get identifier received status. - * - * \param p_usart Pointer to a USART instance. - * - * \return - * 0: No LIN identifier has been reveived since the last RSTSTA. - * 1: At least one LIN identifier has been received since the last RSTSTA. - */ -uint8_t usart_lin_identifier_reception_complete(Usart *usart) -{ - return (usart->US_CSR & US_CSR_LINID) > 0; -} - -/** - * \brief Get transmission status. - * - * \param p_usart Pointer to a USART instance. - * - * \return - * 0: The USART is idle or a LIN transfer is ongoing. - * 1: A LIN transfer has been completed since the last RSTSTA. - */ -uint8_t usart_lin_tx_complete(Usart *usart) -{ - return (usart->US_CSR & US_CSR_LINTC) > 0; -} - -/** - * \brief Configure USART to work in LON mode. - * - * \note By default, the transmitter and receiver aren't enabled. - * - * \param p_usart Pointer to a USART instance. - * \param ul_baudrate Baudrate to be used. - * \param ul_mck USART module input clock frequency. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate, - uint32_t ul_mck) -{ - /* Reset the USART and shut down TX and RX. */ - usart_reset(p_usart); - - /* Set up the baudrate. */ - if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { - return 1; - } - - /* Set LIN master mode. */ - p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | - US_MR_USART_MODE_LON; - - usart_enable_rx(p_usart); - usart_enable_tx(p_usart); - - return 0; -} - -/** - * \brief set LON parameter value. - * - * \param p_usart Pointer to a USART instance. - * \param uc_type 0: LON comm_type = 1 mode, - * 1: LON comm_type = 2 mode - */ -void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type) -{ - p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) | - (uc_type << 0); -} - -/** - * \brief Disable LON Collision Detection Feature. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lon_disable_coll_detection(Usart *p_usart) -{ - p_usart->US_LONMR |= US_LONMR_COLDET; -} - -/** - * \brief Enable LON Collision Detection Feature. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_lon_enable_coll_detection(Usart *p_usart) -{ - p_usart->US_LONMR &= ~US_LONMR_COLDET; -} - -/** - * \brief set Terminate Frame upon Collision Notification. - * - * \param p_usart Pointer to a USART instance. - * \param uc_type 0: Do not terminate the frame in LON comm_type = 1 mode upon collision detection. - * 1:Terminate the frame in LON comm_type = 1 mode upon collision detection if possible. - */ -void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type) -{ - p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) | - (uc_type << 2); -} - -/** - * \brief set LON Collision Detection on Frame Tail. - * - * \param p_usart Pointer to a USART instance. - * \param uc_type 0: Detect collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. - * 1: Ignore collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. - */ -void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type) -{ - p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) | - (uc_type << 3); -} - -/** - * \brief set LON DMA Mode. - * - * \param p_usart Pointer to a USART instance. - * \param uc_type 0: The LON data length register US_LONDL is not written by the DMA. - * 1: The LON data length register US_LONDL is written by the DMA. - */ -void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type) -{ - p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) | - (uc_type << 4); -} - -/** - * \brief set LON Beta1 Length after Transmission. - * - * \param p_usart Pointer to a USART instance. - * \param ul_len 1-16777215: LON beta1 length after transmission in tbit - */ -void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len) -{ - p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len); -} - -/** - * \brief set LON Beta1 Length after Reception. - * - * \param p_usart Pointer to a USART instance. - * \param ul_len 1-16777215: LON beta1 length after reception in tbit. - */ -void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len) -{ - p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len); -} - -/** - * \brief set LON Priority. - * - * \param p_usart Pointer to a USART instance. - * \param uc_psnb 0 -127: LON Priority Slot Number. - * \param uc_nps 0 -127: LON Node Priority Slot. - */ -void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps) -{ - p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) | US_LONPRIO_NPS(uc_nps); -} - -/** - * \brief set LON Indeterminate Time after Transmission. - * - * \param p_usart Pointer to a USART instance. - * \param ul_time 1-16777215: LON Indeterminate Time after Transmission (comm_type = 1 mode only). - */ -void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time) -{ - p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time); -} - -/** - * \brief set LON Indeterminate Time after Reception. - * - * \param p_usart Pointer to a USART instance. - * \param ul_time 1-16777215: LON Indeterminate Time after Reception (comm_type = 1 mode only). - */ -void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time) -{ - p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time); -} - -/** - * \brief set LON Preamble Length. - * - * \param p_usart Pointer to a USART instance. - * \param ul_len 1-16383: LON preamble length in tbit(without byte-sync). - */ -void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len) -{ - p_usart->US_LONPR = US_LONPR_LONPL(ul_len); -} - -/** - * \brief set LON Data Length. - * - * \param p_usart Pointer to a USART instance. - * \param uc_len 0-255: LON data length is LONDL+1 bytes. - */ -void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len) -{ - p_usart->US_LONDL = US_LONDL_LONDL(uc_len); -} - -/** - * \brief set LON Priority. - * - * \param p_usart Pointer to a USART instance. - * \param uc_bli LON Backlog Increment. - * \param uc_altp LON Alternate Path Bit. - * \param uc_pb LON Priority Bit. - */ -void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb) -{ - p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) | (uc_altp << 6) | (uc_pb << 7); -} - -/** - * \brief Check if LON Transmission End. - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 At least one transmission has been performed since the last RSTSTA. - * \retval 0 Transmission on going or no transmission occurred since the last RSTSTA. - */ -uint32_t usart_lon_is_tx_end(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_LTXD) > 0; -} - -/** - * \brief Check if LON Reception End. - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 At least one Reception has been performed since the last RSTSTA. - * \retval 0 Reception on going or no Reception occurred since the last RSTSTA. - */ -uint32_t usart_lon_is_rx_end(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_LRXD) > 0; -} -#endif - -/** - * \brief Enable USART transmitter. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_enable_tx(Usart *p_usart) -{ - p_usart->US_CR = US_CR_TXEN; -} - -/** - * \brief Disable USART transmitter. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_disable_tx(Usart *p_usart) -{ - p_usart->US_CR = US_CR_TXDIS; -} - -/** - * \brief Immediately stop and disable USART transmitter. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_reset_tx(Usart *p_usart) -{ - /* Reset transmitter */ - p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS; -} - -/** - * \brief Configure the transmit timeguard register. - * - * \param p_usart Pointer to a USART instance. - * \param timeguard The value of transmit timeguard. - */ -void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard) -{ - p_usart->US_TTGR = timeguard; -} - -/** - * \brief Enable USART receiver. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_enable_rx(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RXEN; -} - -/** - * \brief Disable USART receiver. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_disable_rx(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RXDIS; -} - -/** - * \brief Immediately stop and disable USART receiver. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_reset_rx(Usart *p_usart) -{ - /* Reset Receiver */ - p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS; -} - -/** - * \brief Configure the receive timeout register. - * - * \param p_usart Pointer to a USART instance. - * \param timeout The value of receive timeout. - */ -void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout) -{ - p_usart->US_RTOR = timeout; -} - -/** - * \brief Enable USART interrupts. - * - * \param p_usart Pointer to a USART peripheral. - * \param ul_sources Interrupt sources bit map. - */ -void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources) -{ - p_usart->US_IER = ul_sources; -} - -/** - * \brief Disable USART interrupts. - * - * \param p_usart Pointer to a USART peripheral. - * \param ul_sources Interrupt sources bit map. - */ -void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources) -{ - p_usart->US_IDR = ul_sources; -} - -/** - * \brief Read USART interrupt mask. - * - * \param p_usart Pointer to a USART peripheral. - * - * \return The interrupt mask value. - */ -uint32_t usart_get_interrupt_mask(Usart *p_usart) -{ - return p_usart->US_IMR; -} - -/** - * \brief Get current status. - * - * \param p_usart Pointer to a USART instance. - * - * \return The current USART status. - */ -uint32_t usart_get_status(Usart *p_usart) -{ - return p_usart->US_CSR; -} - -/** - * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR). - * - * \param p_usart Pointer to a USART instance. - */ -void usart_reset_status(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RSTSTA; -} - -/** - * \brief Start transmission of a break. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_start_tx_break(Usart *p_usart) -{ - p_usart->US_CR = US_CR_STTBRK; -} - -/** - * \brief Stop transmission of a break. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_stop_tx_break(Usart *p_usart) -{ - p_usart->US_CR = US_CR_STPBRK; -} - -/** - * \brief Start waiting for a character before clocking the timeout count. - * Reset the status bit TIMEOUT in US_CSR. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_start_rx_timeout(Usart *p_usart) -{ - p_usart->US_CR = US_CR_STTTO; -} - -/** - * \brief In Multidrop mode only, the next character written to the US_THR - * is sent with the address bit set. - * - * \param p_usart Pointer to a USART instance. - * \param ul_addr The address to be sent out. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr) -{ - if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) { - return 1; - } - - p_usart->US_CR = US_CR_SENDA; - - if (usart_write(p_usart, ul_addr)) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Restart the receive timeout. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_restart_rx_timeout(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RETTO; -} - -#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) - -/** - * \brief Drive the pin DTR to 0. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_drive_DTR_pin_low(Usart *p_usart) -{ - p_usart->US_CR = US_CR_DTREN; -} - -/** - * \brief Drive the pin DTR to 1. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_drive_DTR_pin_high(Usart *p_usart) -{ - p_usart->US_CR = US_CR_DTRDIS; -} - -#endif - -/** - * \brief Drive the pin RTS to 0. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_drive_RTS_pin_low(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RTSEN; -} - -/** - * \brief Drive the pin RTS to 1. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_drive_RTS_pin_high(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RTSDIS; -} - -/** - * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_spi_force_chip_select(Usart *p_usart) -{ - p_usart->US_CR = US_CR_FCS; -} - -/** - * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_spi_release_chip_select(Usart *p_usart) -{ - p_usart->US_CR = US_CR_RCS; -} - -/** - * \brief Check if Transmit is Ready. - * Check if data have been loaded in USART_THR and are waiting to be loaded - * into the Transmit Shift Register (TSR). - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 No data is in the Transmit Holding Register. - * \retval 0 There is data in the Transmit Holding Register. - */ -uint32_t usart_is_tx_ready(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_TXRDY) > 0; -} - -/** - * \brief Check if Transmit Holding Register is empty. - * Check if the last data written in USART_THR have been loaded in TSR and the - * last data loaded in TSR have been transmitted. - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 Transmitter is empty. - * \retval 0 Transmitter is not empty. - */ -uint32_t usart_is_tx_empty(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0; -} - -/** - * \brief Check if the received data are ready. - * Check if Data have been received and loaded into USART_RHR. - * - * \param p_usart Pointer to a USART instance. - * - * \retval 1 Some data has been received. - * \retval 0 No data has been received. - */ -uint32_t usart_is_rx_ready(Usart *p_usart) -{ - return (p_usart->US_CSR & US_CSR_RXRDY) > 0; -} - -/** - * \brief Write to USART Transmit Holding Register. - * - * \note Before writing user should check if tx is ready (or empty). - * - * \param p_usart Pointer to a USART instance. - * \param c Data to be sent. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_write(Usart *p_usart, uint32_t c) -{ - if (!(p_usart->US_CSR & US_CSR_TXRDY)) { - return 1; - } - - p_usart->US_THR = US_THR_TXCHR(c); - return 0; -} - -/** - * \brief Write to USART Transmit Holding Register. - * - * \note Before writing user should check if tx is ready (or empty). - * - * \param p_usart Pointer to a USART instance. - * \param c Data to be sent. - * - * \retval 0 on success. - * \retval 1 on failure. - */ -uint32_t usart_putchar(Usart *p_usart, uint32_t c) -{ - while (!(p_usart->US_CSR & US_CSR_TXRDY)) { - } - - p_usart->US_THR = US_THR_TXCHR(c); - - return 0; -} - -/** - * \brief Write one-line string through USART. - * - * \param p_usart Pointer to a USART instance. - * \param string Pointer to one-line string to be sent. - */ -void usart_write_line(Usart *p_usart, const char *string) -{ - while (*string != '\0') { - usart_putchar(p_usart, *string++); - } -} - -/** - * \brief Read from USART Receive Holding Register. - * - * \note Before reading user should check if rx is ready. - * - * \param p_usart Pointer to a USART instance. - * \param c Pointer where the one-byte received data will be stored. - * - * \retval 0 on success. - * \retval 1 if no data is available or errors. - */ -uint32_t usart_read(Usart *p_usart, uint32_t *c) -{ - if (!(p_usart->US_CSR & US_CSR_RXRDY)) { - return 1; - } - - /* Read character */ - *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; - - return 0; -} - -/** - * \brief Read from USART Receive Holding Register. - * Before reading user should check if rx is ready. - * - * \param p_usart Pointer to a USART instance. - * \param c Pointer where the one-byte received data will be stored. - * - * \retval 0 Data has been received. - * \retval 1 on failure. - */ -uint32_t usart_getchar(Usart *p_usart, uint32_t *c) -{ - /* Wait until it's not empty or timeout has reached. */ - while (!(p_usart->US_CSR & US_CSR_RXRDY)) { - } - - /* Read character */ - *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; - - return 0; -} - -#if (SAM3XA || SAM3U) -/** - * \brief Get Transmit address for DMA operation. - * - * \param p_usart Pointer to a USART instance. - * - * \return Transmit address for DMA access. - */ -uint32_t *usart_get_tx_access(Usart *p_usart) -{ - return (uint32_t *)&(p_usart->US_THR); -} - -/** - * \brief Get Receive address for DMA operation. - * - * \param p_usart Pointer to a USART instance. - * - * \return Receive address for DMA access. - */ -uint32_t *usart_get_rx_access(Usart *p_usart) -{ - return (uint32_t *)&(p_usart->US_RHR); -} -#endif - -#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) -/** - * \brief Get USART PDC base address. - * - * \param p_usart Pointer to a UART instance. - * - * \return USART PDC registers base for PDC driver to access. - */ -Pdc *usart_get_pdc_base(Usart *p_usart) -{ - Pdc *p_pdc_base; - - p_pdc_base = (Pdc *)NULL; - -#ifdef PDC_USART - if (p_usart == USART) { - p_pdc_base = PDC_USART; - return p_pdc_base; - } -#endif -#ifdef PDC_USART0 - if (p_usart == USART0) { - p_pdc_base = PDC_USART0; - return p_pdc_base; - } -#endif -#ifdef PDC_USART1 - else if (p_usart == USART1) { - p_pdc_base = PDC_USART1; - return p_pdc_base; - } -#endif -#ifdef PDC_USART2 - else if (p_usart == USART2) { - p_pdc_base = PDC_USART2; - return p_pdc_base; - } -#endif -#ifdef PDC_USART3 - else if (p_usart == USART3) { - p_pdc_base = PDC_USART3; - return p_pdc_base; - } -#endif -#ifdef PDC_USART4 - else if (p_usart == USART4) { - p_pdc_base = PDC_USART4; - return p_pdc_base; - } -#endif -#ifdef PDC_USART5 - else if (p_usart == USART5) { - p_pdc_base = PDC_USART5; - return p_pdc_base; - } -#endif -#ifdef PDC_USART6 - else if (p_usart == USART6) { - p_pdc_base = PDC_USART6; - return p_pdc_base; - } -#endif -#ifdef PDC_USART7 - else if (p_usart == USART7) { - p_pdc_base = PDC_USART7; - return p_pdc_base; - } -#endif - - return p_pdc_base; -} -#endif - -/** - * \brief Enable write protect of USART registers. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_enable_writeprotect(Usart *p_usart) -{ - p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY_PASSWD; -} - -/** - * \brief Disable write protect of USART registers. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_disable_writeprotect(Usart *p_usart) -{ - p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD; -} - -/** - * \brief Get write protect status. - * - * \param p_usart Pointer to a USART instance. - * - * \return 0 if no write protect violation occurred, or 16-bit write protect - * violation source. - */ -uint32_t usart_get_writeprotect_status(Usart *p_usart) -{ - uint32_t reg_value; - - reg_value = p_usart->US_WPSR; - if (reg_value & US_WPSR_WPVS) { - return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos; - } else { - return 0; - } -} - -#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM) - -/** - * \brief Configure the transmitter preamble length when the Manchester - * encode/decode is enabled. - * - * \param p_usart Pointer to a USART instance. - * \param uc_len The transmitter preamble length, which should be 0 ~ 15. - */ -void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len) -{ - p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) | - US_MAN_TX_PL(uc_len); -} - -/** - * \brief Configure the transmitter preamble pattern when the Manchester - * encode/decode is enabled, which should be 0 ~ 3. - * - * \param p_usart Pointer to a USART instance. - * \param uc_pattern 0 if the preamble is composed of '1's; - * 1 if the preamble is composed of '0's; - * 2 if the preamble is composed of '01's; - * 3 if the preamble is composed of '10's. - */ -void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) -{ - p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) | - (uc_pattern << US_MAN_TX_PP_Pos); -} - -/** - * \brief Configure the transmitter Manchester polarity when the Manchester - * encode/decode is enabled. - * - * \param p_usart Pointer to a USART instance. - * \param uc_polarity Indicate the transmitter Manchester polarity, which - * should be 0 or 1. - */ -void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity) -{ - p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) | - (uc_polarity << 12); -} - -/** - * \brief Configure the detected receiver preamble length when the Manchester - * encode/decode is enabled. - * - * \param p_usart Pointer to a USART instance. - * \param uc_len The detected receiver preamble length, which should be 0 ~ 15. - */ -void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len) -{ - p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) | - US_MAN_RX_PL(uc_len); -} - -/** - * \brief Configure the detected receiver preamble pattern when the Manchester - * encode/decode is enabled, which should be 0 ~ 3. - * - * \param p_usart Pointer to a USART instance. - * \param uc_pattern 0 if the preamble is composed of '1's; - * 1 if the preamble is composed of '0's; - * 2 if the preamble is composed of '01's; - * 3 if the preamble is composed of '10's. - */ -void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) -{ - p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) | - (uc_pattern << US_MAN_RX_PP_Pos); -} - -/** - * \brief Configure the receiver Manchester polarity when the Manchester - * encode/decode is enabled. - * - * \param p_usart Pointer to a USART instance. - * \param uc_polarity Indicate the receiver Manchester polarity, which should - * be 0 or 1. - */ -void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity) -{ - p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) | - (uc_polarity << 28); -} - -/** - * \brief Enable drift compensation. - * - * \note The 16X clock mode must be enabled. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_man_enable_drift_compensation(Usart *p_usart) -{ - p_usart->US_MAN |= US_MAN_DRIFT; -} - -/** - * \brief Disable drift compensation. - * - * \param p_usart Pointer to a USART instance. - */ -void usart_man_disable_drift_compensation(Usart *p_usart) -{ - p_usart->US_MAN &= ~US_MAN_DRIFT; -} - -#endif - -#if SAM4L - -uint32_t usart_get_version(Usart *p_usart) -{ - return p_usart->US_VERSION; -} - -#endif - -#if SAMG55 -/** - * \brief Set sleepwalking match mode. - * - * \param p_uart Pointer to a USART instance. - * \param ul_low_value First comparison value for received character. - * \param ul_high_value Second comparison value for received character. - * \param cmpmode ture for start condition, false for flag only. - * \param cmppar ture for parity check, false for no. - */ -void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, - bool cmpmode, bool cmppar, uint8_t ul_high_value) -{ - Assert(ul_low_value <= ul_high_value); - - uint32_t temp = 0; - - if (cmpmode) { - temp |= US_CMPR_CMPMODE_START_CONDITION; - } - - if (cmppar) { - temp |= US_CMPR_CMPPAR; - } - - temp |= US_CMPR_VAL1(ul_low_value); - - temp |= US_CMPR_VAL2(ul_high_value); - - p_uart->US_CMPR= temp; -} -#endif - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.h deleted file mode 100644 index fc43ae9852c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.h +++ /dev/null @@ -1,779 +0,0 @@ -/** - * \file - * - * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver - * for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef USART_H_INCLUDED -#define USART_H_INCLUDED - -#include "compiler.h" - -/** - * \defgroup group_sam_drivers_usart Universal Synchronous Asynchronous Receiver - * Transmitter (USART). - * - * See \ref sam_usart_quickstart. - * - * This is a low-level driver implementation for the SAM Universal - * Synchronous/Asynchronous Receiver/Transmitter. - * - * @{ - */ - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** Clock phase. */ -#define SPI_CPHA (1 << 0) - - /** Clock polarity. */ -#define SPI_CPOL (1 << 1) - - /** SPI mode definition. */ -#define SPI_MODE_0 0 -#define SPI_MODE_1 (SPI_CPHA) -#define SPI_MODE_2 (SPI_CPOL) -#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA) - - /**micro definition for LIN mode of SAMV71*/ -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) -#define US_MR_USART_MODE_LIN_MASTER 0x0A -#define US_MR_USART_MODE_LIN_SLAVE 0x0B -#endif - /* Input parameters when initializing RS232 and similar modes. */ - typedef struct { - /* Set baud rate of the USART (unused in slave modes). */ - uint32_t baudrate; - - /* - * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, - * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or - * US_MR_MODE9. - */ - uint32_t char_length; - - /* - * Parity type, which should be one of the following: US_MR_PAR_EVEN, - * US_MR_PAR_ODD, US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO - * or US_MR_PAR_MULTIDROP. - */ - uint32_t parity_type; - - /* - * Number of stop bits between two characters: US_MR_NBSTOP_1_BIT, - * US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT. - * \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only. - */ - uint32_t stop_bits; - - /* - * Run the channel in test mode, which should be one of following: - * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, - * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. - */ - uint32_t channel_mode; - - /* Filter of IrDA mode, useless in other modes. */ - uint32_t irda_filter; - } sam_usart_opt_t; - - /* Input parameters when initializing ISO7816 mode. */ - typedef struct { - /* Set the frequency of the ISO7816 clock. */ - uint32_t iso7816_hz; - - /* - * The number of ISO7816 clock ticks in every bit period (1 to 2047, - * 0 = disable clock). Baudrate rate = iso7816_hz / fidi_ratio. - */ - uint32_t fidi_ratio; - - /* - * How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or - * US_MR_PAR_ODD for inverse mode. - */ - uint32_t parity_type; - - /* - * Inhibit Non Acknowledge: - * - 0: the NACK is generated; - * - 1: the NACK is not generated. - * - * \note This bit will be used only in ISO7816 mode, protocol T = 0 - * receiver. - */ - uint32_t inhibit_nack; - - /* - * Disable successive NACKs. - * - 0: NACK is sent on the ISO line as soon as a parity error occurs - * in the received character. Successive parity errors are counted up to - * the value in the max_iterations field. These parity errors generate - * a NACK on the ISO line. As soon as this value is reached, no additional - * NACK is sent on the ISO line. The ITERATION flag is asserted. - */ - uint32_t dis_suc_nack; - - /* Max number of repetitions (0 to 7). */ - uint32_t max_iterations; - - /* - * Bit order in transmitted characters: - * - 0: LSB first; - * - 1: MSB first. - */ - uint32_t bit_order; - - /* - * Which protocol is used: - * - 0: T = 0; - * - 1: T = 1. - */ - uint32_t protocol_type; - } usart_iso7816_opt_t; - - /* Input parameters when initializing SPI mode. */ - typedef struct { - /* Set the frequency of the SPI clock (unused in slave mode). */ - uint32_t baudrate; - - /* - * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, - * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or - * US_MR_MODE9. - */ - uint32_t char_length; - - /* - * Which SPI mode to use, which should be one of the following: - * SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3. - */ - uint32_t spi_mode; - - /* - * Run the channel in test mode, which should be one of following: - * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, - * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. - */ - uint32_t channel_mode; - } usart_spi_opt_t; - - void usart_reset(Usart *p_usart); - uint32_t usart_set_async_baudrate(Usart *p_usart, - uint32_t baudrate, uint32_t ul_mck); - uint32_t usart_init_rs232(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); - uint32_t usart_init_hw_handshaking(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); -#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) - uint32_t usart_init_modem(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); -#endif - uint32_t usart_init_sync_master(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); - uint32_t usart_init_sync_slave(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt); - uint32_t usart_init_rs485(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); -#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) - uint32_t usart_init_irda(Usart *p_usart, - const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); -#endif -#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) - uint32_t usart_init_iso7816(Usart *p_usart, - const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck); - void usart_reset_iterations(Usart *p_usart); - void usart_reset_nack(Usart *p_usart); - uint32_t usart_is_rx_buf_end(Usart *p_usart); - uint32_t usart_is_tx_buf_end(Usart *p_usart); - uint32_t usart_is_rx_buf_full(Usart *p_usart); - uint32_t usart_is_tx_buf_empty(Usart *p_usart); - uint8_t usart_get_error_number(Usart *p_usart); -#endif - uint32_t usart_init_spi_master(Usart *p_usart, - const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck); - uint32_t usart_init_spi_slave(Usart *p_usart, - const usart_spi_opt_t *p_usart_opt); -#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) - uint32_t usart_init_lin_master(Usart *p_usart, uint32_t ul_baudrate, - uint32_t ul_mck); - uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, - uint32_t ul_mck); - void usart_lin_abort_tx(Usart *p_usart); - void usart_lin_send_wakeup_signal(Usart *p_usart); - void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action); - void usart_lin_disable_parity(Usart *p_usart); - void usart_lin_enable_parity(Usart *p_usart); - void usart_lin_disable_checksum(Usart *p_usart); - void usart_lin_enable_checksum(Usart *p_usart); - void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type); - void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode); - void usart_lin_disable_frame_slot(Usart *p_usart); - void usart_lin_enable_frame_slot(Usart *p_usart); - void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type); - void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len); - void usart_lin_disable_pdc_mode(Usart *p_usart); - void usart_lin_enable_pdc_mode(Usart *p_usart); - void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id); - uint8_t usart_lin_read_identifier(Usart *p_usart); - uint8_t usart_lin_get_data_length(Usart *usart); -#endif -#if (SAMV71 || SAMV70 || SAME70 || SAMS70) - uint8_t usart_lin_identifier_send_complete(Usart *usart); - uint8_t usart_lin_identifier_reception_complete(Usart *usart); - uint8_t usart_lin_tx_complete(Usart *usart); - uint32_t usart_init_lon(Usart *p_usart, uint32_t ul_baudrate, uint32_t ul_mck); - void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type); - void usart_lon_disable_coll_detection(Usart *p_usart); - void usart_lon_enable_coll_detection(Usart *p_usart); - void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type); - void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type); - void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type); - void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len); - void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len); - void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps); - void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time); - void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time); - void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len); - void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len); - void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb); - uint32_t usart_lon_is_tx_end(Usart *p_usart); - uint32_t usart_lon_is_rx_end(Usart *p_usart); -#endif - void usart_enable_tx(Usart *p_usart); - void usart_disable_tx(Usart *p_usart); - void usart_reset_tx(Usart *p_usart); - void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard); - void usart_enable_rx(Usart *p_usart); - void usart_disable_rx(Usart *p_usart); - void usart_reset_rx(Usart *p_usart); - void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout); - void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources); - void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources); - uint32_t usart_get_interrupt_mask(Usart *p_usart); - uint32_t usart_get_status(Usart *p_usart); - void usart_reset_status(Usart *p_usart); - void usart_start_tx_break(Usart *p_usart); - void usart_stop_tx_break(Usart *p_usart); - void usart_start_rx_timeout(Usart *p_usart); - uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr); - void usart_restart_rx_timeout(Usart *p_usart); -#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) - void usart_drive_DTR_pin_low(Usart *p_usart); - void usart_drive_DTR_pin_high(Usart *p_usart); -#endif - void usart_drive_RTS_pin_low(Usart *p_usart); - void usart_drive_RTS_pin_high(Usart *p_usart); - void usart_spi_force_chip_select(Usart *p_usart); - void usart_spi_release_chip_select(Usart *p_usart); - uint32_t usart_is_tx_ready(Usart *p_usart); - uint32_t usart_is_tx_empty(Usart *p_usart); - uint32_t usart_is_rx_ready(Usart *p_usart); - uint32_t usart_write(Usart *p_usart, uint32_t c); - uint32_t usart_putchar(Usart *p_usart, uint32_t c); - void usart_write_line(Usart *p_usart, const char *string); - uint32_t usart_read(Usart *p_usart, uint32_t *c); - uint32_t usart_getchar(Usart *p_usart, uint32_t *c); -#if (SAM3XA || SAM3U) - uint32_t *usart_get_tx_access(Usart *p_usart); - uint32_t *usart_get_rx_access(Usart *p_usart); -#endif -#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) - Pdc *usart_get_pdc_base(Usart *p_usart); -#endif - void usart_enable_writeprotect(Usart *p_usart); - void usart_disable_writeprotect(Usart *p_usart); - uint32_t usart_get_writeprotect_status(Usart *p_usart); -#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM || SAMV70 || SAMV71 || SAMS70 || SAME70) - void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len); - void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); - void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity); - void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len); - void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); - void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity); - void usart_man_enable_drift_compensation(Usart *p_usart); - void usart_man_disable_drift_compensation(Usart *p_usart); -#endif - -#if SAM4L - uint32_t usart_get_version(Usart *p_usart); -#endif - -#if SAMG55 - void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, - bool cmpmode, bool cmppar, uint8_t ul_high_value); -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -//! @} - -/** - * \page sam_usart_quickstart Quick start guide for the SAM USART module - * - * This is the quick start guide for the \ref group_sam_drivers_usart - * "USART module", with step-by-step instructions on how to configure and - * use the driver in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \note Some SAM devices contain both USART and UART modules, with the latter - * being a subset in functionality of the former but physically separate - * peripherals. UART modules are compatible with the USART driver, but - * only for the functions and modes supported by the base UART driver. - * - * \section usart_use_cases USART use cases - * - \ref usart_basic_use_case - * - \subpage usart_use_case_1 - * - \subpage usart_use_case_2 - * - * \note The USART pins configuration are not included here. Please refer - * the related code in board_init() function. - * - * \section usart_basic_use_case Basic use case - transmit a character - * In this use case, the USART module is configured for: - * - Using USART0 - * - Baudrate: 9600 - * - Character length: 8 bit - * - Parity mode: Disabled - * - Stop bit: None - * - RS232 mode - * - * \section usart_basic_use_case_setup Setup steps - * - * \subsection usart_basic_use_case_setup_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (sysclock)" - * -# \ref ioport_group "Common IOPORT API (ioport)" - * - * \subsection usart_basic_use_case_setup_code Example code - * The following configuration must be added to the project (typically to a - * conf_usart.h file, but it can also be added to your main application file.) - * \code - #define USART_SERIAL USART0 - #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l - #define USART_SERIAL_BAUDRATE 9600 - #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT - #define USART_SERIAL_PARITY US_MR_PAR_NO - #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT -\endcode - * - * Add to application initialization: - * \code - sysclk_init(); - - board_init(); - - const sam_usart_opt_t usart_console_settings = { - USART_SERIAL_BAUDRATE, - USART_SERIAL_CHAR_LENGTH, - USART_SERIAL_PARITY, - USART_SERIAL_STOP_BIT, - US_MR_CHMODE_NORMAL - }; - #if SAM4L - sysclk_enable_peripheral_clock(USART_SERIAL); - #else - sysclk_enable_peripheral_clock(USART_SERIAL_ID); - #endif - usart_init_rs232(USART_SERIAL, &usart_console_settings, - sysclk_get_main_hz()); - usart_enable_tx(USART_SERIAL); - usart_enable_rx(USART_SERIAL); -\endcode - * - * \subsection usart_basic_use_case_setup_flow Workflow - * -# Initialize system clock: - * \code - sysclk_init(); -\endcode - * -# Configure the USART Tx and Rx pins by call the board init function: - * \code - board_init(); -\endcode - * \note Set the following define in conf_board.h file to enable COM port,it will be used in - * board_init() function to set up IOPorts for the USART pins. - * For SAM4L: - * \code - #define CONF_BOARD_COM_PORT -\endcode - * For other SAM devices: - * \code - #define CONF_BOARD_UART_CONSOLE -\endcode - * -# Create USART options struct: - * \code - const sam_usart_opt_t usart_console_settings = { - USART_SERIAL_BAUDRATE, - USART_SERIAL_CHAR_LENGTH, - USART_SERIAL_PARITY, - USART_SERIAL_STOP_BIT, - US_MR_CHMODE_NORMAL - }; -\endcode - * -# Enable the clock to the USART module: - * \code - #if SAM4L - sysclk_enable_peripheral_clock(USART_SERIAL); - #else - sysclk_enable_peripheral_clock(USART_SERIAL_ID); - #endif -\endcode - * -# Initialize the USART module in RS232 mode: - * \code - usart_init_rs232(USART_SERIAL, &usart_console_settings, - sysclk_get_main_hz()); -\endcode - * -# Enable the Rx and Tx modes of the USART module: - * \code - usart_enable_tx(USART_SERIAL); - usart_enable_rx(USART_SERIAL); -\endcode - * - * \section usart_basic_use_case_usage Usage steps - * - * \subsection usart_basic_use_case_usage_code Example code - * Add to application C-file: - * \code - usart_putchar(USART_SERIAL, 'a'); -\endcode - * - * \subsection usart_basic_use_case_usage_flow Workflow - * -# Send an 'a' character via USART - * \code usart_putchar(USART_SERIAL, 'a'); \endcode - */ - -/** - * \page usart_use_case_1 USART receive character and echo back - * - * In this use case, the USART module is configured for: - * - Using USART0 - * - Baudrate: 9600 - * - Character length: 8 bit - * - Parity mode: Disabled - * - Stop bit: None - * - RS232 mode - * - * The use case waits for a received character on the configured USART and - * echoes the character back to the same USART. - * - * \section usart_use_case_1_setup Setup steps - * - * \subsection usart_use_case_1_setup_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (sysclock)" - * -# \ref ioport_group "Common IOPORT API (ioport)" - * - * \subsection usart_use_case_1_setup_code Example code - * The following configuration must be added to the project (typically to a - * conf_usart.h file, but it can also be added to your main application file.): - * \code - #define USART_SERIAL USART0 - #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l - #define USART_SERIAL_BAUDRATE 9600 - #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT - #define USART_SERIAL_PARITY US_MR_PAR_NO - #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT -\endcode - * - * A variable for the received byte must be added: - * \code - uint32_t received_byte; -\endcode - * - * Add to application initialization: - * \code - sysclk_init(); - - board_init(); - - const sam_usart_opt_t usart_console_settings = { - USART_SERIAL_BAUDRATE, - USART_SERIAL_CHAR_LENGTH, - USART_SERIAL_PARITY, - USART_SERIAL_STOP_BIT, - US_MR_CHMODE_NORMAL - }; - - #if SAM4L - sysclk_enable_peripheral_clock(USART_SERIAL); - #else - sysclk_enable_peripheral_clock(USART_SERIAL_ID); - #endif - - usart_init_rs232(USART_SERIAL, &usart_console_settings, - sysclk_get_main_hz()); - usart_enable_tx(USART_SERIAL); - usart_enable_rx(USART_SERIAL); -\endcode - * - * \subsection usart_use_case_1_setup_flow Workflow - * -# Initialize system clock: - * \code - sysclk_init(); -\endcode - * -# Configure the USART Tx and Rx pins by call the board init function: - * \code - board_init(); -\endcode - * \note Set the following define in conf_board.h file to enable COM port,it will be used in - * board_init() function to set up IOPorts for the USART pins. - * For SAM4L: - * \code - #define CONF_BOARD_COM_PORT -\endcode - * For other SAM devices: - * \code - #define CONF_BOARD_UART_CONSOLE -\endcode - * -# Create USART options struct: - * \code - const sam_usart_opt_t usart_console_settings = { - USART_SERIAL_BAUDRATE, - USART_SERIAL_CHAR_LENGTH, - USART_SERIAL_PARITY, - USART_SERIAL_STOP_BIT, - US_MR_CHMODE_NORMAL - }; -\endcode - * -# Enable the clock to the USART module: - * \code - #if SAM4L - sysclk_enable_peripheral_clock(USART_SERIAL); - #else - sysclk_enable_peripheral_clock(USART_SERIAL_ID); - #endif -\endcode - * -# Initialize the USART module in RS232 mode: - * \code - usart_init_rs232(USART_SERIAL, &usart_console_settings, - sysclk_get_main_hz()); -\endcode - * -# Enable the Rx and Tx modes of the USART module: - * \code - usart_enable_tx(USART_SERIAL); - usart_enable_rx(USART_SERIAL); -\endcode - * - * \section usart_use_case_1_usage Usage steps - * - * \subsection usart_use_case_1_usage_code Example code - * Add to, e.g., main loop in application C-file: - * \code - received_byte = usart_getchar(USART_SERIAL); - usart_putchar(USART_SERIAL, received_byte); -\endcode - * - * \subsection usart_use_case_1_usage_flow Workflow - * -# Wait for reception of a character: - * \code usart_getchar(USART_SERIAL, &received_byte); \endcode - * -# Echo the character back: - * \code usart_putchar(USART_SERIAL, received_byte); \endcode - */ - -/** - * \page usart_use_case_2 USART receive character and echo back via interrupts - * - * In this use case, the USART module is configured for: - * - Using USART0 - * - Baudrate: 9600 - * - Character length: 8 bit - * - Parity mode: Disabled - * - Stop bit: None - * - RS232 mode - * - * The use case waits for a received character on the configured USART and - * echoes the character back to the same USART. The character reception is - * performed via an interrupt handler, rather than the polling method used - * in \ref usart_use_case_1. - * - * \section usart_use_case_2_setup Setup steps - * - * \subsection usart_use_case_2_setup_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (sysclock)" - * -# \ref pio_group "Parallel Input/Output Controller (pio)" - * -# \ref pmc_group "Power Management Controller (pmc)" - * - * \subsection usart_use_case_2_setup_code Example code - * The following configuration must be added to the project (typically to a - * conf_usart.h file, but it can also be added to your main application file.): - * \code - #define USART_SERIAL USART0 - #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l - #define USART_SERIAL_ISR_HANDLER USART0_Handler - #define USART_SERIAL_BAUDRATE 9600 - #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT - #define USART_SERIAL_PARITY US_MR_PAR_NO - #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT -\endcode - * - * A variable for the received byte must be added: - * \code - uint32_t received_byte; -\endcode - * - * Add to application initialization: - * \code - sysclk_init(); - - board_init(); - - const sam_usart_opt_t usart_console_settings = { - USART_SERIAL_BAUDRATE, - USART_SERIAL_CHAR_LENGTH, - USART_SERIAL_PARITY, - USART_SERIAL_STOP_BIT, - US_MR_CHMODE_NORMAL - }; - - #if SAM4L - sysclk_enable_peripheral_clock(USART_SERIAL); - #else - sysclk_enable_peripheral_clock(USART_SERIAL_ID); - #endif - - usart_init_rs232(USART_SERIAL, &usart_console_settings, - sysclk_get_main_hz()); - usart_enable_tx(USART_SERIAL); - usart_enable_rx(USART_SERIAL); - - usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); - NVIC_EnableIRQ(USART_SERIAL_IRQ); -\endcode - * - * \subsection usart_use_case_2_setup_flow Workflow - * -# Initialize system clock: - * \code - sysclk_init(); -\endcode - * -# Configure the USART Tx and Rx pins by call the board init function: - * \code - board_init(); -\endcode - * \note Set the following define in conf_board.h file to enable COM port,it will be used in - * board_init() function to set up IOPorts for the USART pins. - * For SAM4L: - * \code - #define CONF_BOARD_COM_PORT -\endcode - * For other SAM devices: - * \code - #define CONF_BOARD_UART_CONSOLE -\endcode - * -# Create USART options struct: - * \code - const sam_usart_opt_t usart_console_settings = { - USART_SERIAL_BAUDRATE, - USART_SERIAL_CHAR_LENGTH, - USART_SERIAL_PARITY, - USART_SERIAL_STOP_BIT, - US_MR_CHMODE_NORMAL - }; -\endcode - * -# Enable the clock to the USART module: - * \code - #if SAM4L - sysclk_enable_peripheral_clock(USART_SERIAL); - #else - sysclk_enable_peripheral_clock(USART_SERIAL_ID); - #endif -\endcode - * -# Initialize the USART module in RS232 mode: - * \code - usart_init_rs232(USART_SERIAL, &usart_console_settings, - sysclk_get_main_hz()); -\endcode - * -# Enable the Rx and Tx modes of the USART module: - * \code - usart_enable_tx(USART_SERIAL); - usart_enable_rx(USART_SERIAL); -\endcode - * -# Enable the USART character reception interrupt, and general interrupts - * for the USART module. - * \code - usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); - NVIC_EnableIRQ(USART_SERIAL_IRQ); -\endcode - * \section usart_use_case_2_usage Usage steps - * - * \subsection usart_use_case_2_usage_code Example code - * Add to your main application C-file the USART interrupt handler: - * \code - void USART_SERIAL_ISR_HANDLER(void) - { - uint32_t dw_status = usart_get_status(USART_SERIAL); - - if (dw_status & US_CSR_RXRDY) { - uint32_t received_byte; - - usart_read(USART_SERIAL, &received_byte); - usart_write(USART_SERIAL, received_byte); - } - } -\endcode - * - * \subsection usart_use_case_2_usage_flow Workflow - * -# When the USART ISR fires, retrieve the USART module interrupt flags: - * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode - * -# Check if the USART Receive Character interrupt has fired: - * \code if (dw_status & US_CSR_RXRDY) \endcode - * -# If a character has been received, fetch it into a temporary variable: - * \code usart_read(USART_SERIAL, &received_byte); \endcode - * -# Echo the character back: - * \code usart_write(USART_SERIAL, received_byte); \endcode - */ - -#endif /* USART_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_api.c deleted file mode 100644 index b6613e4d1c9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "PinNames.h" -#include "gpio_object.h" -#include "gpio_api.h" -#include "compiler.h" -#include "ioport.h" - -extern uint8_t g_sys_init; - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - return (1UL << (pin % 32)); -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - obj->pin = pin; - if (pin == NC) { - return; - } - - ioport_set_pin_dir(pin, IOPORT_DIR_INPUT); - ioport_set_pin_mode(pin, IOPORT_MODE_PULLUP); -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - obj->mode = mode; - switch (mode) { - case PullNone : - ioport_set_pin_mode(obj->pin, IOPORT_MODE_OPEN_DRAIN); - break; - case PullUp: - ioport_set_pin_mode(obj->pin, IOPORT_MODE_PULLUP); - break; - case PullDown: - ioport_set_pin_mode(obj->pin, IOPORT_MODE_PULLDOWN); - break; - } -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - obj->direction = direction; - switch (direction) { - case PIN_INPUT : - ioport_set_pin_dir(obj->pin, IOPORT_DIR_INPUT); - break; - case PIN_OUTPUT: - ioport_set_pin_dir(obj->pin, IOPORT_DIR_OUTPUT); - break; - case PIN_INPUT_OUTPUT: - ioport_set_pin_dir(obj->pin, IOPORT_DIR_OUTPUT); - break; - } -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_irq_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_irq_api.c deleted file mode 100644 index 81dabff2b11..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_irq_api.c +++ /dev/null @@ -1,188 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" - -#include "gpio_irq_api.h" -#include "gpio_api.h" -#include "ioport.h" - -#define IRQ_RISE_POSITION 1 -#define IRQ_FALL_POSITION 2 -#define CHANNEL_NUM 48 -#define MAX_PINS_IN_PORT 32 - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; -extern uint8_t g_sys_init; - -static IRQn_Type pin_to_irq (uint32_t pin); - -void gpio_irq_common_handler(uint32_t port_id) -{ - uint32_t i = 0, status = 0, mask = 0, temp = 0; - gpio_irq_event event; - - Pio* pio_base = arch_ioport_port_to_base(port_id); - mask = pio_base->PIO_IMR; - status = pio_base->PIO_ISR; - status = status & mask; - - for (i = 0; i < MAX_PINS_IN_PORT ; i++) { - temp = (1 << i ); - if (status & temp ) { - if((pio_base->PIO_PDSR) & temp) { - event = IRQ_RISE; - } else { - event = IRQ_FALL; - } - if(irq_handler) { - irq_handler(channel_ids[(port_id * 32) + i], event); - } - } - } -} - -void gpio_irq_porta(void) -{ - gpio_irq_common_handler(IOPORT_PIOA); -} - -void gpio_irq_portb(void) -{ - gpio_irq_common_handler(IOPORT_PIOB); -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - MBED_ASSERT(obj); - if (pin == NC) - return -1; - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t port_id; - uint32_t vector = 0; - uint8_t int_channel = 0; - Pio* pio_base; - - irq_handler = handler; // assuming the usage of these apis in mbed layer only - int_channel = ((pin / 32) * 32) + (pin % 32); /*to get the channel to be used*/ - channel_ids[int_channel] = id; - obj->pin = pin; - port_id = ioport_pin_to_port_id(pin); - pio_base = arch_ioport_port_to_base(port_id); - - ioport_set_pin_dir(pin, IOPORT_DIR_INPUT); /*Pin to be configured input for GPIO Interrupt*/ - ioport_set_pin_mode(pin, IOPORT_MODE_PULLUP); - - irq_n = pin_to_irq(pin); - - switch (port_id) { - /*only 2 ports for SAMG55*/ /*Setting up the vectors*/ - case IOPORT_PIOA : - vector = (uint32_t)gpio_irq_porta; - break; - case IOPORT_PIOB : - vector = (uint32_t)gpio_irq_portb; - break; - } - pio_base->PIO_ISR; /*To read and clear status register*/ - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - MBED_ASSERT(obj); - channel_ids[((obj->pin / 32) * 32) + (obj->pin % 32)] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - MBED_ASSERT(obj); - uint32_t mask = 0; - - Pio* pio_base = arch_ioport_port_to_base(arch_ioport_pin_to_port_id(obj->pin)); - mask = (1 << (obj->pin % 32)); - - if (enable) { - if (event == IRQ_RISE) { - obj->irqmask |= IRQ_RISE_POSITION; - } else if (event == IRQ_FALL) { - obj->irqmask |= IRQ_FALL_POSITION; - } - } else { - - if (event == IRQ_RISE) { - obj->irqmask &= ~IRQ_RISE_POSITION; - } else if (event == IRQ_FALL) { - obj->irqmask &= ~IRQ_FALL_POSITION; - } - } - pio_base->PIO_ISR; /*To read and clear status register*/ - if (obj->irqmask == (IRQ_RISE_POSITION | IRQ_FALL_POSITION)) { /*both edge detection*/ - pio_base->PIO_AIMDR = mask; - pio_base->PIO_IER = mask; - } else if (obj->irqmask == IRQ_RISE_POSITION) { /*rising detection*/ - pio_base->PIO_ESR = mask; - pio_base->PIO_REHLSR = mask; - pio_base->PIO_AIMER = mask; - pio_base->PIO_IER = mask; - } else if (obj->irqmask == IRQ_FALL_POSITION) { /*falling detection*/ - pio_base->PIO_ESR = mask; - pio_base->PIO_FELLSR = mask; - pio_base->PIO_AIMER = mask; - pio_base->PIO_IER = mask; - } else { /*none and disable*/ - pio_base->PIO_IDR = mask; - } -} - -static IRQn_Type pin_to_irq (uint32_t pin) -{ - uint32_t port_id; - IRQn_Type irq_n = (IRQn_Type)0; - port_id = ioport_pin_to_port_id(pin); - - switch (port_id) { - case IOPORT_PIOA : - irq_n = PIOA_IRQn; - break; - case IOPORT_PIOB : - irq_n = PIOB_IRQn; - break; - } - return irq_n; -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - MBED_ASSERT(obj); - NVIC_EnableIRQ(pin_to_irq(obj->pin)); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - MBED_ASSERT(obj); - NVIC_DisableIRQ(pin_to_irq(obj->pin)); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_object.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_object.h deleted file mode 100644 index f57d004c03a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_object.h +++ /dev/null @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "ioport.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint8_t mode; - uint8_t direction; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) - ioport_set_pin_level(obj->pin, IOPORT_PIN_LEVEL_HIGH); - else - ioport_set_pin_level(obj->pin, IOPORT_PIN_LEVEL_LOW); -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return (ioport_get_pin_level(obj->pin) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/i2c_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/i2c_api.c deleted file mode 100644 index 49b8540af79..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/i2c_api.c +++ /dev/null @@ -1,739 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "device.h" -#include "buffer.h" -#include "dma_api.h" -#include "PeripheralPins.h" -#include "twi.h" -#include "pdc.h" -#include "mbed_assert.h" -#include "ioport.h" - -/** - * \defgroup GeneralI2C I2C Configuration Functions - * @{ - */ - -/** TWI Bus Clock 400kHz */ -extern uint8_t g_sys_init; - -#define TWI_CLK (400000u) - -#define ADDR_LENGTH 0 - -#define MAX_I2C 8 - -extern uint32_t twi_mk_addr(const uint8_t *addr, int len); - -void pinmap_find_i2c_info(Twi *sercombase, i2c_t *obj) -{ - if(sercombase==TWI0) { - obj->i2c.flexcom=FLEXCOM0; - obj->i2c.module_number=0; - obj->i2c.pdc =PDC_TWI0; - obj->i2c.irq_type=FLEXCOM0_IRQn; - } else if(sercombase==TWI1) { - obj->i2c.flexcom=FLEXCOM1; - obj->i2c.module_number=1; - obj->i2c.pdc =PDC_TWI1; - obj->i2c.irq_type=FLEXCOM1_IRQn; - } else if(sercombase==TWI2) { - obj->i2c.flexcom=FLEXCOM2; - obj->i2c.module_number=2; - obj->i2c.pdc =PDC_TWI2; - obj->i2c.irq_type=FLEXCOM2_IRQn; - } else if(sercombase==TWI3) { - obj->i2c.flexcom=FLEXCOM3; - obj->i2c.module_number=3; - obj->i2c.pdc =PDC_TWI3; - obj->i2c.irq_type=FLEXCOM3_IRQn; - } else if(sercombase==TWI4) { - obj->i2c.flexcom=FLEXCOM4; - obj->i2c.module_number=4; - obj->i2c.pdc =PDC_TWI4; - obj->i2c.irq_type=FLEXCOM4_IRQn; - } else if(sercombase==TWI5) { - obj->i2c.flexcom=FLEXCOM5; - obj->i2c.module_number=5; - obj->i2c.pdc =PDC_TWI5; - obj->i2c.irq_type=FLEXCOM5_IRQn; - } else if(sercombase==TWI6) { - obj->i2c.flexcom=FLEXCOM6; - obj->i2c.module_number=6; - obj->i2c.pdc =PDC_TWI6; - obj->i2c.irq_type=FLEXCOM6_IRQn; - } else if(sercombase==TWI7) { - obj->i2c.flexcom=FLEXCOM7; - obj->i2c.module_number=7; - obj->i2c.pdc =PDC_TWI7; - obj->i2c.irq_type=FLEXCOM7_IRQn; - } else { - obj->i2c.flexcom=(Flexcom *)NC; - obj->i2c.module_number=0; - obj->i2c.pdc =(Pdc *) NC; - } -} - - -/** Initialize the I2C peripheral. It sets the default parameters for I2C - * peripheral, and configure its specifieds pins. - * @param obj The i2c object - * @param sda The sda pin - * @param scl The scl pin - */ -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - MBED_ASSERT(obj); - MBED_ASSERT(sda !=NC && scl!=NC ); - - if (g_sys_init == 0) { - sysclk_init(); - board_init(); - g_sys_init = 1; - } - - - Twi* sda_base = (Twi*)pinmap_peripheral(sda, PinMap_I2C_SDA); - Twi* scl_base = (Twi*)pinmap_peripheral(scl, PinMap_I2C_SCL); - Twi* I2cBase = (Twi*)pinmap_merge((uint32_t)sda_base, (uint32_t)scl_base); - - MBED_ASSERT(I2cBase !=NC ); - - obj->i2c.i2c_base=I2cBase; - pinmap_find_i2c_info(I2cBase,obj); - - /* Configure I2C pins */ - pin_function(sda, pinmap_find_function(sda, PinMap_I2C_SDA)); - ioport_disable_pin(sda); - - pin_function(scl, pinmap_find_function(scl, PinMap_I2C_SCL)); - ioport_disable_pin(scl); - -#if (SAMG55) - /* Enable the peripheral and set TWI mode. */ - MBED_ASSERT((int)obj->i2c.flexcom!=NC); - flexcom_enable(obj->i2c.flexcom); - flexcom_set_opmode(obj->i2c.flexcom, FLEXCOM_TWI); -#else - /* Enable the peripheral clock for TWI */ - pmc_enable_periph_clk(obj->i2c.i2c_base); -#endif - - twi_options_t twi_options; - twi_options.master_clk=sysclk_get_cpu_hz(); - twi_options.speed=TWI_CLK; - twi_options.smbus = 0; - - twi_master_init(obj->i2c.i2c_base,&twi_options); - - obj->i2c.is_slave=false; - obj->i2c.speed=TWI_CLK; - obj->i2c.master_clk=twi_options.master_clk; -} - -/** Configure the I2C frequency. - * @param obj The i2c object - * @param hz Frequency in Hz - */ -void i2c_frequency(i2c_t *obj, int hz) -{ - MBED_ASSERT(obj); - if(obj->i2c.is_slave) - twi_disable_slave_mode(obj->i2c.i2c_base); - else - twi_disable_master_mode(obj->i2c.i2c_base); - - twi_set_speed(obj->i2c.i2c_base,hz,obj->i2c.master_clk); - - if(obj->i2c.is_slave) - twi_enable_slave_mode(obj->i2c.i2c_base); - else - twi_enable_master_mode(obj->i2c.i2c_base); -} - -/** Send START command. - * @param obj The i2c object - */ -int i2c_start(i2c_t *obj) -{ - MBED_ASSERT(obj); - obj->i2c.i2c_base->TWI_CR = TWI_CR_START; - return 0; -} - -/** Send STOP command. - * @param obj The i2c object - */ -int i2c_stop(i2c_t *obj) -{ - MBED_ASSERT(obj); - obj->i2c.i2c_base->TWI_CR = TWI_CR_STOP; - return 0; -} - - -uint32_t twi_master_read_no_stop(Twi *p_twi, twi_packet_t *p_packet, uint8_t stopena) -{ - uint32_t status; - uint32_t cnt = p_packet->length; - uint8_t *buffer = p_packet->buffer; - uint8_t stop_sent = 0; - uint32_t timeout = TWI_TIMEOUT;; - - /* Check argument */ - if (cnt == 0) { - return TWI_INVALID_ARGUMENT; - } - - /* Set read mode, slave address and 3 internal address byte lengths */ - p_twi->TWI_MMR = 0; - p_twi->TWI_MMR = TWI_MMR_MREAD | TWI_MMR_DADR(p_packet->chip) | - ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) & - TWI_MMR_IADRSZ_Msk); - - /* Send a START condition */ - if ((cnt == 1) && (stopena == 1)) { - p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP; - stop_sent = 1; - } else { - p_twi->TWI_CR = TWI_CR_START; - stop_sent = 0; - } - - while (cnt > 0) { - status = p_twi->TWI_SR; - if (status & TWI_SR_NACK) { - return TWI_RECEIVE_NACK; - } - - if (!timeout--) { - return TWI_ERROR_TIMEOUT; - } - - /* Last byte ? */ - if ((cnt == 1) && (!stop_sent) && (stopena == 1)) { - p_twi->TWI_CR = TWI_CR_STOP; - stop_sent = 1; - } - - if (!(status & TWI_SR_RXRDY)) { - continue; - } - *buffer++ = p_twi->TWI_RHR; - - cnt--; - timeout = TWI_TIMEOUT; - } - if(stopena) { - while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) { - } - } - - p_twi->TWI_SR; - - return TWI_SUCCESS; - -} - - - - - -/** Blocking reading data. - * @param obj The i2c object - * @param address 7-bit address (last bit is 1) - * @param data The buffer for receiving - * @param length Number of bytes to read - * @param stop Stop to be generated after the transfer is done - * @return Number of read bytes - */ -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - MBED_ASSERT(obj); - - twi_packet_t packet; - packet.chip= (address>>1) & 0x7F; - packet.addr_length=ADDR_LENGTH; - packet.buffer=data; - packet.length=length; - - uint8_t status; - status= twi_master_read_no_stop(obj->i2c.i2c_base, &packet, stop); - - if(TWI_SUCCESS==status) - return length; - - return 0; -} - - -uint32_t twi_master_write_no_stop(Twi *p_twi, twi_packet_t *p_packet, uint8_t stopena) -{ - uint32_t status; - uint32_t cnt = p_packet->length; - uint8_t *buffer = p_packet->buffer; - - /* Check argument */ - if (cnt == 0) { - return TWI_INVALID_ARGUMENT; - } - - /* Set write mode, slave address and 3 internal address byte lengths */ - p_twi->TWI_MMR = 0; - p_twi->TWI_MMR = TWI_MMR_DADR(p_packet->chip) | - ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) & - TWI_MMR_IADRSZ_Msk); - - /* Send a START condition */ - if ((cnt == 1) && (stopena == 1)) { - p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP; - } else { - p_twi->TWI_CR = TWI_CR_START; - } - - /* Send all bytes */ - while (cnt > 0) { - status = p_twi->TWI_SR; - if (status & TWI_SR_NACK) { - return TWI_RECEIVE_NACK; - } - - if (!(status & TWI_SR_TXRDY)) { - continue; - } - p_twi->TWI_THR = *buffer++; - - cnt--; - } - - while (1) { - status = p_twi->TWI_SR; - if (status & TWI_SR_NACK) { - return TWI_RECEIVE_NACK; - } - - if (status & TWI_SR_TXRDY) { - break; - } - } - - if (stopena) { - p_twi->TWI_CR = TWI_CR_STOP; - while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)); - } - - return TWI_SUCCESS; -} - - - -/** Blocking sending data. - * @param obj The i2c object - * @param address 7-bit address (last bit is 0) - * @param data The buffer for sending - * @param length Number of bytes to wrte - * @param stop Stop to be generated after the transfer is done - * @return Number of written bytes - */ -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - MBED_ASSERT(obj); - - twi_packet_t packet; - packet.chip= (address>>1) & 0x7F; - packet.addr_length=ADDR_LENGTH; - packet.buffer= (void *)data; - packet.length=length; - - uint8_t status; - status= twi_master_write_no_stop(obj->i2c.i2c_base,&packet, stop); - - if(TWI_SUCCESS==status) - return length; - - return 0; -} - -/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop(). - * @param obj The i2c object - */ -void i2c_reset(i2c_t *obj) -{ - MBED_ASSERT(obj); - twi_reset(obj->i2c.i2c_base); -} - -/** Read one byte. - * @param obj The i2c object - * @param last Acknoledge - * @return The read byte - */ -int i2c_byte_read(i2c_t *obj, int last) -{ - MBED_ASSERT(obj); - if(!last) - twi_enable_slave_nack(obj->i2c.i2c_base); - - return twi_read_byte(obj->i2c.i2c_base); -} - -/** Write one byte. - * @param obj The i2c object - * @param data Byte to be written - * @return 1 if NAK was received, 0 if ACK was received, 2 for timeout. - */ -#define ACK 0 -#define NAK 1 -#define TIMEOUT 2 - -int i2c_byte_write(i2c_t *obj, int data) -{ - MBED_ASSERT(obj); - twi_write_byte(obj->i2c.i2c_base,data); - - uint32_t timeout = TWI_TIMEOUT; - while (timeout--) { - uint32_t status = obj->i2c.i2c_base->TWI_SR; - if (status & TWI_SR_NACK) { - return NAK; - } - - if (status & TWI_SR_TXRDY) { - return ACK; - } - - if (timeout<1) { - return TIMEOUT; - } - } - - return ACK; -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -/**@}*/ - -#if DEVICE_I2CSLAVE - -/** - * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave - * @{ - */ - -/** Configure I2C as slave or master. - * @param obj The I2C object - * @return non-zero if a value is available - */ -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - MBED_ASSERT(obj); - /* Disable TWI interrupts */ - obj->i2c.i2c_base->TWI_IDR = ~0UL; - obj->i2c.i2c_base->TWI_SR; - - /* Reset TWI */ - twi_reset(obj->i2c.i2c_base); - - MBED_ASSERT(obj); - if(enable_slave) - twi_enable_slave_mode(obj->i2c.i2c_base); - else - twi_enable_master_mode(obj->i2c.i2c_base); -} - -/** Check to see if the I2C slave has been addressed. - * @param obj The I2C object - * @return The status - 1 - read addresses, 2 - write to all slaves, - * 3 write addressed, 0 - the slave has not been addressed - */ -int i2c_slave_receive(i2c_t *obj) -{ - uint32_t status = obj->i2c.i2c_base->TWI_SR; - if((status & TWI_SR_SVACC)) { - if(status & TWI_SR_SVREAD) - return 1; - else - return 3; - } - return 0; -} - - -uint32_t twi_slave_read_n(Twi *p_twi, uint8_t *p_data, int length) -{ - uint32_t status, cnt = 0; - - do { - status = p_twi->TWI_SR; - if (status & TWI_SR_SVACC) { - if (!(status & (TWI_SR_GACC| TWI_SR_SVREAD )) && - (status & TWI_SR_RXRDY) - ) { - *p_data++ = (uint8_t) p_twi->TWI_RHR; - cnt++; - if(cnt>=length) break; - } - } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP)) - == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) { - break; - } - } while (1); - - return cnt; -} - -/** Read I2C slave. - * @param obj The I2C object - * @return non-zero if a value is available - */ -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - MBED_ASSERT(obj); - int read= twi_slave_read_n(obj->i2c.i2c_base,(uint8_t *) data,length); - return read; -} - - -uint32_t twi_slave_write_n(Twi *p_twi, uint8_t *p_data, int length) -{ - uint32_t status, cnt = 0; - - do { - status = p_twi->TWI_SR; - if (status & TWI_SR_SVACC) { - if ((status & TWI_SR_SVREAD) && !(status & TWI_SR_GACC) && - (status & TWI_SR_TXRDY)) { - p_twi->TWI_THR = *p_data++; - cnt++; - if(cnt>=length) break; - } - } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP)) - == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) { - break; - } - } while (1); - - return cnt; -} - - -/** Write I2C as slave. - * @param obj The I2C object - * @return non-zero if a value is available - */ -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - MBED_ASSERT(obj); - int write= twi_slave_write_n(obj->i2c.i2c_base, (uint8_t *) data,length); - return write; -} - -/** Configure I2C address. - * @param obj The I2C object - * @param idx Currently not used - * @param address The address to be set - * @param mask Currently not used - */ -void i2c_slave_address(i2c_t *obj, int idx/*not used*/, uint32_t address, uint32_t mask) -{ - MBED_ASSERT(obj); - twi_set_slave_addr(obj->i2c.i2c_base, (address>>1)); -} - -#endif - -/**@}*/ - -#if DEVICE_I2C_ASYNCH - -/** - * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer - * @{ - */ - -/** Start i2c asynchronous transfer. - * @param obj The I2C object - * @param tx The buffer to send - * @param tx_length The number of words to transmit - * @param rx The buffer to receive - * @param rx_length The number of words to receive - * @param address The address to be set - 7bit or 9 bit - * @param stop If true, stop will be generated after the transfer is done - * @param handler The I2C IRQ handler to be set - * @param hint DMA hint usage - */ -#warning "Only DMA async supported by I2C master transfer" - -void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint /*Not Used*/) -{ - uint32_t pdcenable=0; - - if(address) { - twi_packet_t pdc_packet; - pdc_packet.chip=(address>>1) & 0x7F; - pdc_packet.addr_length=ADDR_LENGTH; - - /* Set write mode, slave address and 3 internal address byte lengths */ - obj->i2c.i2c_base->TWI_MMR = 0; - obj->i2c.i2c_base->TWI_MMR = TWI_MMR_DADR(pdc_packet.chip) | - ((pdc_packet.addr_length << TWI_MMR_IADRSZ_Pos) & - TWI_MMR_IADRSZ_Msk); - } - - if(tx) { - pdc_packet_t pdc_packet_tx; - pdc_packet_tx.ul_addr=(uint32_t)tx; - pdc_packet_tx.ul_size=tx_length; - - pdcenable|=PERIPH_PTCR_TXTEN; - /* Configure PDC for data send */ - pdc_tx_init(obj->i2c.pdc, &pdc_packet_tx, NULL); - } - - if(rx) { - obj->i2c.i2c_base->TWI_MMR |= TWI_MMR_MREAD; - pdc_rx_clear_cnt(obj->i2c.pdc); - pdc_packet_t pdc_packet_rx; - pdc_packet_rx.ul_addr=(uint32_t)rx; - pdc_packet_rx.ul_size=rx_length; - pdcenable|=PERIPH_PTCR_RXTEN; - - /* Configure PDC for data receive */ - pdc_rx_init(obj->i2c.pdc, &pdc_packet_rx, NULL); - } - - obj->i2c.dma_usage=hint; - obj->i2c.event=event; - obj->i2c.stop=stop; - obj->i2c.address=address; - - NVIC_ClearPendingIRQ(obj->i2c.irq_type); - NVIC_DisableIRQ(obj->i2c.irq_type); - NVIC_SetVector(obj->i2c.irq_type,handler); - NVIC_EnableIRQ(obj->i2c.irq_type); - - /* Enable TWI IRQ */ - twi_enable_interrupt(obj->i2c.i2c_base, TWI_IER_RXBUFF| TWI_IER_TXBUFE | TWI_IER_UNRE | TWI_IER_OVRE | TWI_IER_PECERR); - - /* Enable PDC transfers */ - pdc_enable_transfer(obj->i2c.pdc, pdcenable ); - -} - -/** The asynchronous IRQ handler - * @param obj The I2C object which holds the transfer information - * @return event flags if a transfer termination condition was met or 0 otherwise. - */ -uint32_t i2c_irq_handler_asynch(i2c_t *obj) -{ - uint32_t event=0; - - if(obj->i2c.stop) { - i2c_stop(obj); - } - - // Data transferred via DMA - if((obj->i2c.i2c_base->TWI_SR & TWI_IER_TXBUFE)) { - twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_TXBUFE | TWI_IDR_UNRE | TWI_IDR_OVRE | TWI_IDR_PECERR); - if(obj->i2c.event | I2C_EVENT_TRANSFER_COMPLETE) - event |=I2C_EVENT_TRANSFER_COMPLETE; - } - - if((obj->i2c.i2c_base->TWI_SR & TWI_IER_RXBUFF)) { - twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_RXBUFF | TWI_IDR_UNRE | TWI_IDR_OVRE | TWI_IDR_PECERR); - if(obj->i2c.event | I2C_EVENT_TRANSFER_COMPLETE) - event |=I2C_EVENT_TRANSFER_COMPLETE; - } - - if(obj->i2c.i2c_base->TWI_SR & TWI_IER_NACK) { - if(obj->i2c.event | I2C_EVENT_TRANSFER_EARLY_NACK) - event |=I2C_EVENT_TRANSFER_EARLY_NACK; - } - - - if((obj->i2c.i2c_base->TWI_SR & TWI_IER_UNRE) || (obj->i2c.i2c_base->TWI_SR & TWI_IER_OVRE) || (obj->i2c.i2c_base->TWI_SR & TWI_IER_PECERR) || (obj->i2c.i2c_base->TWI_SR & TWI_SR_TOUT) ) { - if((obj->i2c.event | I2C_EVENT_ERROR)) - event |=I2C_EVENT_ERROR; - - if(obj->i2c.address) { - uint8_t status= twi_probe(obj->i2c.i2c_base,obj->i2c.address); - if((obj->i2c.event | I2C_EVENT_ERROR_NO_SLAVE) && (status!=TWI_SUCCESS) ) - event |=I2C_EVENT_ERROR_NO_SLAVE; - } - } - - return event; -} - -/** Attempts to determine if I2C peripheral is already in use. - * @param obj The I2C object - * @return non-zero if the I2C module is active or zero if it is not - */ -uint8_t i2c_active(i2c_t *obj) -{ - - if(obj->i2c.i2c_base->TWI_SR & TWI_SR_ENDTX && obj->i2c.i2c_base->TWI_SR & TWI_SR_ENDRX) - return 0; - - return 1; - -} - -/** Abort ongoing asynchronous transaction. - * @param obj The I2C object - */ -void i2c_abort_asynch(i2c_t *obj) -{ - /* Disable PDC transfers */ - pdc_disable_transfer(obj->i2c.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); - - /* Clear PDC buffer receive counter */ - pdc_rx_clear_cnt(obj->i2c.pdc); - - /* Disable I2C IRQ */ - twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_TXBUFE); - twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_RXBUFF); - - /* Disable I2C interrupt */ - NVIC_DisableIRQ(obj->i2c.irq_type); -} - -#endif - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/lp_ticker.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/lp_ticker.c deleted file mode 100644 index 507c44c9504..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/lp_ticker.c +++ /dev/null @@ -1,138 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis.h" -#include -#include "lp_ticker_api.h" -#include "mbed_assert.h" -#include "sleep_api.h" -#include "compiler.h" -#include "sysclk.h" -#include "tc.h" -#include "us_ticker_api.h" - -uint8_t lp_ticker_inited = 0; -extern volatile uint8_t us_ticker_inited; -extern uint8_t g_sys_init; -extern volatile uint32_t overflow32bitcounter; -volatile uint16_t lp_ticker_16bit_counter; -volatile uint16_t lp_ticker_interrupt_counter; -volatile uint16_t lp_ticker_interrupt_offset; -volatile uint32_t lpoverflow32bitcounter = 0; - -#define TICKER_COUNTER_lp TC0 - -#define TICKER_COUNTER_CLK2 ID_TC2 - -#define TICKER_COUNTER_CHANNEL2 2 -#define TICKER_COUNTER_IRQn2 TC2_IRQn -#define TICKER_COUNTER_Handlr2 TC2_Handler - -#define OVERFLOW_16bit_VALUE 0xFFFF - - -void TICKER_COUNTER_Handlr2(void) -{ - uint32_t status=tc_get_status(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2); - uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2); - - if (((status & interrupmask) & TC_IER_CPCS)) { - if(lp_ticker_interrupt_counter) { - lp_ticker_interrupt_counter--; - } else { - if(lp_ticker_interrupt_offset) { - tc_stop(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2); - tc_write_rc(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, (uint32_t)lp_ticker_interrupt_offset); - tc_start(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2); - lp_ticker_interrupt_offset=0; - } else { - lp_ticker_irq_handler(); - } - } - } -} - -void lp_ticker_init(void) -{ - if(lp_ticker_inited) - return; - if (!us_ticker_inited) - us_ticker_init(); - sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK2); - tc_init(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, TC_CMR_TCCLKS_TIMER_CLOCK4); - lp_ticker_inited = 1; -} - -uint32_t lp_ticker_read() -{ - if (!lp_ticker_inited) - lp_ticker_init(); - return us_ticker_read(); -} - -void lp_ticker_set_interrupt(timestamp_t timestamp) -{ - uint32_t cur_time; - uint32_t delta; - - cur_time = lp_ticker_read(); - delta = timestamp - cur_time; - - uint16_t interruptat=0; - - if(delta > OVERFLOW_16bit_VALUE) { - lp_ticker_interrupt_counter= (delta/OVERFLOW_16bit_VALUE) -1; - lp_ticker_interrupt_offset=delta%OVERFLOW_16bit_VALUE; - interruptat=OVERFLOW_16bit_VALUE; - } else { - lp_ticker_interrupt_counter=0; - lp_ticker_interrupt_offset=0; - interruptat=delta; - } - - NVIC_DisableIRQ(TICKER_COUNTER_IRQn2); - - tc_write_rc(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, (uint32_t)interruptat); - - NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn2); - NVIC_SetPriority(TICKER_COUNTER_IRQn2, 0); - NVIC_EnableIRQ(TICKER_COUNTER_IRQn2); - tc_enable_interrupt(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, TC_IDR_CPCS ); - - tc_start(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2); -} - -void lp_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(TICKER_COUNTER_IRQn2); -} - -void lp_ticker_disable_interrupt(void) -{ - tc_stop(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2); - tc_disable_interrupt(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, TC_IDR_CPCS); - NVIC_DisableIRQ(TICKER_COUNTER_IRQn2); -} - -void lp_ticker_clear_interrupt(void) -{ - NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn2); -} - -void lp_ticker_free(void) -{ - -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/objects.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/objects.h deleted file mode 100644 index a306c4f143e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/objects.h +++ /dev/null @@ -1,110 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "gpio_object.h" -#include "serial_platform.h" -#include "adc2.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct waveconfig_t { - /** Internal clock signals selection. */ - uint32_t ul_intclock; - /** Waveform frequency (in Hz). */ - uint16_t us_frequency; - /** Duty cycle in percent (positive).*/ - uint16_t us_dutycycle; -}; - -struct gpio_irq_s { - uint32_t pin; - uint32_t irqmask; -}; - -struct port_s { - PortName port; - uint32_t mask; - uint8_t mode; - uint8_t direction; -}; - -struct serial_s { - UARTName uart; - usart_serial_options_t uart_serial_options; -#if DEVICE_SERIAL_ASYNCH - uint8_t actrec; - uint8_t acttra; - uint32_t events; -#endif -}; - -struct analogin_s { - enum adc_channel_num channel; -}; - -struct pwmout_s { - uint32_t channel; - uint32_t ioline; - uint32_t pin; - uint32_t prescalarindex; - struct waveconfig_t waveconfig; -}; - -struct i2c_s { - Twi * i2c_base; - Flexcom * flexcom; - uint8_t is_slave; - uint8_t module_number; - uint32_t speed; - uint32_t master_clk; - uint32_t address; -#if DEVICE_I2C_ASYNCH - Pdc * pdc; - uint8_t dma_usage; - IRQn_Type irq_type; - uint32_t event; - uint32_t stop; -#endif -}; -struct spi_s { - Spi * spi_base; - Flexcom * flexcom; - uint8_t cs; - uint8_t polarity; - uint8_t phase; - uint32_t transferrate; - uint8_t is_slave; - uint8_t module_number; -#if DEVICE_SPI_ASYNCH - Pdc * pdc; - uint8_t dma_usage; - IRQn_Type irq_type; - uint32_t event; -#endif -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/pinmap.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/pinmap.c deleted file mode 100644 index b85e94dfd64..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/pinmap.c +++ /dev/null @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "cmsis.h" -#include "mbed_assert.h" -#include "compiler.h" - -#include "pinmap.h" -#include "ioport.h" - -/** Change the MUX padding of input pin - * - * Configure the pin for specific module - * @param[in] pin Pin name whose MUX padding is to be changed - * @param[in] function The MUX mode to be selected - * @return void - */ -void pin_function(PinName pin, int function) -{ - MBED_ASSERT(pin != (PinName)NC); - ioport_set_pin_mode(pin, function); -} - -/** Change the pin pull mode - * - * Configure the pin pull mode - * @param[in] pin Pin name whose MUX padding is to be changed - * @param[in] mode Pin pull mode to be set - * @return void - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - if (mode == PullUp) { - ioport_set_pin_mode(pin, IOPORT_MODE_PULLUP); - } else if (mode == PullDown) { - ioport_set_pin_mode(pin, IOPORT_MODE_PULLDOWN); - } else { - ioport_set_pin_mode(pin, IOPORT_MODE_OPEN_DRAIN); - } -} \ No newline at end of file diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/port_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/port_api.c deleted file mode 100644 index e2e33948a46..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/port_api.c +++ /dev/null @@ -1,92 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "ioport.h" - -extern uint8_t g_sys_init; - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - MBED_ASSERT(obj); - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - obj->port = port; - obj->mask = mask; - - switch (dir) { - case PIN_INPUT : - ioport_set_port_dir(port, mask, IOPORT_DIR_INPUT); - break; - case PIN_OUTPUT: - ioport_set_port_dir(port, mask, IOPORT_DIR_OUTPUT); - break; - case PIN_INPUT_OUTPUT: - ioport_set_port_dir(port, mask, IOPORT_DIR_OUTPUT); - break; - } - ioport_set_port_mode(port, mask, IOPORT_MODE_PULLUP); -} - -void port_mode(port_t *obj, PinMode mode) -{ - MBED_ASSERT(obj); - obj->mode = mode; - switch (mode) { - case PullNone : - ioport_set_port_mode(obj->port, obj->mask, IOPORT_MODE_OPEN_DRAIN); - break; - case PullUp: - ioport_set_port_mode(obj->port, obj->mask, IOPORT_MODE_PULLUP); - break; - case PullDown: - ioport_set_port_mode(obj->port, obj->mask, IOPORT_MODE_PULLDOWN); - break; - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - MBED_ASSERT(obj); - obj->direction = dir; - switch (dir) { - case PIN_INPUT : - ioport_set_port_dir(obj->port, obj->mask, IOPORT_DIR_INPUT); - break; - case PIN_OUTPUT: - ioport_set_port_dir(obj->port, obj->mask, IOPORT_DIR_OUTPUT); - break; - case PIN_INPUT_OUTPUT: - ioport_set_port_dir(obj->port, obj->mask, IOPORT_DIR_OUTPUT); - break; - } -} - -void port_write(port_t *obj, int value) -{ - MBED_ASSERT(obj); - ioport_set_port_level(obj->port, obj->mask, value); -} - -int port_read(port_t *obj) -{ - MBED_ASSERT(obj); - return ioport_get_port_level(obj->port, obj->mask); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/pwmout_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/pwmout_api.c deleted file mode 100644 index 19f206a51b1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/pwmout_api.c +++ /dev/null @@ -1,312 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" - -#include "cmsis.h" -#include "tc.h" -#include "sysclk.h" -#include "PeripheralPins.h" - -extern uint8_t g_sys_init; - -/** Use TC Peripheral 0 **/ -#define TC TC0 - -static const uint32_t tc_prescalar[] = { - TC_CMR_TCCLKS_TIMER_CLOCK1, // MCK/2 - TC_CMR_TCCLKS_TIMER_CLOCK2, // MCK/8 - TC_CMR_TCCLKS_TIMER_CLOCK3, // MCK/32 - TC_CMR_TCCLKS_TIMER_CLOCK4, // MCK/128 -}; -static const uint32_t tc_prescalar_divider[] = { - 2, // MCK/2 - 8, // MCK/8 - 32, // MCK/32 - 128 // MCK/128 -}; - -uint32_t getpwmchannelid (uint32_t channel) -{ - switch (channel) { - case 0 : - return ID_TC0; - case 1 : - return ID_TC1; - case 2 : - return ID_TC2; - default : - MBED_ASSERT(false); - break; - } -} - -uint32_t getprescalarindex (uint16_t frequency) -{ - float time_period_ms; - time_period_ms = (1.0 / (float)frequency) * 1000.0; - if (time_period_ms <= 1.0) { - return 0; - } else if ((time_period_ms > 1.0) && (time_period_ms <= 4.0)) { - return 1; - } else if ((time_period_ms > 4.0) && (time_period_ms <= 16.0)) { - return 2; - } else { - return 3; - } -} - -static void setregisterabc (pwmout_t* obj) -{ - uint32_t ra, rb, rc; - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Configure waveform frequency and duty cycle. */ - rc = (sysclk_get_peripheral_bus_hz(TC) / - tc_prescalar_divider[obj->prescalarindex] )/ - obj->waveconfig.us_frequency; - tc_write_rc(TC, obj->channel, rc); - switch (obj->ioline) { - case 0 : - ra = (100 - obj->waveconfig.us_dutycycle) * rc / 100; - if(ra <= 0) ra = 1; /*non zero value only*/ - tc_write_ra(TC, obj->channel, ra); - break; - case 1 : - rb = (100 - obj->waveconfig.us_dutycycle) * rc / 100; - if(rb <= 0) rb = 1; /*non zero value only*/ - tc_write_rb(TC, obj->channel, rb); - break; - default : - MBED_ASSERT(false); - break; - } -} - -void pwmout_inithw(pwmout_t* obj) -{ - uint32_t mode = 0; - /* Configure the PMC to enable the TC module. */ - sysclk_enable_peripheral_clock(getpwmchannelid(obj->channel)); -#if SAMG55 - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_3); - pmc_switch_pck_to_mck(PMC_PCK_3, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_3); -#endif - switch (obj->ioline) { - case 0 : - mode = TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR; /* RA Compare Effect: set */ /* RC Compare Effect: clear */ - break; - case 1 : - mode = TC_CMR_BCPB_SET | TC_CMR_BCPC_CLEAR | TC_CMR_ABETRG; /* RB Compare Effect: set */ /* RC Compare Effect: clear */ /*Change external event selection from TIOB*/ - break; - default : - MBED_ASSERT(false); - break; - } - /* Disable TC TC_CHANNEL_WAVEFORM. */ - tc_stop(TC, obj->channel); - /* Init TC to waveform mode. */ - tc_init(TC, obj->channel, - /* Waveform Clock Selection */ - obj->waveconfig.ul_intclock - | TC_CMR_WAVE /* Waveform mode is enabled */ - | TC_CMR_CPCTRG /* UP mode with automatic trigger on RC Compare */ - | mode - ); -} - -/** Initialize PWM Module - * - * @param[in][out] obj The PWM object to initialize - * @return void - */ -void pwmout_init(pwmout_t* obj, PinName pin) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t ioline = NC; - uint32_t channel = NC; - - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - if(pin != NC) { - pin_function(pin, pinmap_find_function(pin, PinMap_PWM)); - ioport_disable_pin(pin); - } - obj->pin = pin; - - ioline = pinmap_find_function(pin, PinMap_PWM_IO_Line); /*To find out which IO Line is associated with the pin and initialise accordingly*/ /*pinmap_find_function reused to find out iolin used*/ - MBED_ASSERT(ioline != NC); - obj->ioline = ioline; - - channel = pinmap_find_peripheral(pin, PinMap_PWM_IO_Line); /* PinMap_PWM_IO_Line contains channel number and ioline to be used*/ /*pinmap_find_peripheral function reused to find out channel number*/ - MBED_ASSERT(channel != NC); - obj->channel = channel; - obj->waveconfig.us_frequency = 500; - obj->waveconfig.us_dutycycle = 50; - - obj->prescalarindex = getprescalarindex(obj->waveconfig.us_frequency); - obj->waveconfig.ul_intclock = tc_prescalar[obj->prescalarindex]; - pwmout_inithw(obj); - - /*Set the registers a,b,c*/ - setregisterabc(obj); - - /* Enable TC TC_CHANNEL_WAVEFORM. */ - tc_start(TC, channel); -} - -/** Free the PWM Module - * - * @param[in] obj The PWM object to free - * @return void - */ -void pwmout_free(pwmout_t* obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - tc_stop(TC, obj->channel); -} - -/** Set the duty cycle of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] value New duty cycle to be set - * @return void - */ -void pwmout_write(pwmout_t* obj, float value) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - if (value < 0.0f) { - value = 0; - } else if (value > 1.0f) { - value = 1; - } - obj->waveconfig.us_dutycycle = (uint16_t)(value * 100); - tc_stop(TC, obj->channel); - - /*Set the registers a,b,c*/ - setregisterabc(obj); - - /* Enable TC TC_CHANNEL_WAVEFORM. */ - tc_start(TC, obj->channel); -} - -/** Get the duty cycle of PWM Waveform - * - * @param[in] obj The PWM object - * @return Current duty cycle - */ -float pwmout_read(pwmout_t* obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - return (obj->waveconfig.us_dutycycle / 100.0); -} - -/** Set the period of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] seconds New period in seconds - * @return void - */ -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -/** Set the period of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] value New period in milliseconds - * @return void - */ -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -/** Set the period of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] us New period in microseconds - * @return void - */ -void pwmout_period_us(pwmout_t* obj, int us) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - float freq = ( 1.0 / us ) * 1000000.0; - - obj->waveconfig.us_frequency = (uint16_t) freq; - obj->prescalarindex = getprescalarindex(obj->waveconfig.us_frequency); - obj->waveconfig.ul_intclock = tc_prescalar[obj->prescalarindex]; - pwmout_inithw(obj); - - /*Set the registers a,b,c*/ - setregisterabc(obj); - - /* Enable TC TC_CHANNEL_WAVEFORM. */ - tc_start(TC, obj->channel); -} - -/** Set the pulse width of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] seconds New pulse width in seconds - * @return void - */ -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -/** Set the pulse width of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] ms New pulse width in milliseconds - * @return void - */ -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -/** Set the pulse width of PWM Waveform - * - * @param[in] obj The PWM object - * @param[in] us New pulse width in microseconds - * @return void - */ -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - float new_duty = (us / 1000000.0) * (float)obj->waveconfig.us_frequency; - pwmout_write(obj, new_duty); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c deleted file mode 100644 index ebb7042922c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c +++ /dev/null @@ -1,107 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "rtc_api.h" -#include "cmsis.h" -#include "sysclk.h" -#include "rtc.h" -#include "mbed_mktime.h" - -static int rtc_inited = 0; - -extern uint8_t g_sys_init; - -void rtc_init(void) -{ - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - /* Default RTC configuration, 24-hour mode */ - rtc_set_hour_mode(RTC, 0); - rtc_inited = 1; -} - -void rtc_free(void) -{ - /*This is a free running peripheral and cannot be disabled*/ - rtc_inited = 0; -} - - -int rtc_isenabled(void) -{ - return rtc_inited; -} - - -time_t rtc_read(void) -{ - if (!rtc_inited) { - /* Return invalid time for now! */ - return 0; - } - struct tm timeinfo; - uint32_t ul_hour, ul_minute, ul_second; - uint32_t ul_year, ul_month, ul_day, ul_week; - - rtc_get_time(RTC, &ul_hour, &ul_minute, &ul_second); - rtc_get_date(RTC, &ul_year, &ul_month, &ul_day, &ul_week); - - timeinfo.tm_sec = ul_second; - timeinfo.tm_min = ul_minute; - timeinfo.tm_hour = ul_hour; - timeinfo.tm_mday = ul_day; - timeinfo.tm_wday = ul_week; - timeinfo.tm_mon = ul_month; - timeinfo.tm_year = (ul_year - 1900); - - /* Convert to timestamp */ - time_t t; - if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { - return 0; - } - - return t; -} - -void rtc_write(time_t t) -{ - if (!rtc_inited) { - /* Initialize the RTC is not yet initialized */ - rtc_init(); - } - - struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { - return; - } - uint32_t ul_hour, ul_minute, ul_second; - uint32_t ul_year, ul_month, ul_day, ul_week; - - ul_second = timeinfo.tm_sec; - ul_minute = timeinfo.tm_min; - ul_hour = timeinfo.tm_hour; - ul_day = timeinfo.tm_mday; - ul_week = timeinfo.tm_wday; - ul_month = timeinfo.tm_mon; - ul_year = timeinfo.tm_year; - - /* Set the RTC */ - rtc_set_time(RTC, ul_hour, ul_minute, ul_second); - rtc_set_date(RTC, ul_year, ul_month, ul_day, ul_week); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/serial_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/serial_api.c deleted file mode 100644 index 42dbf6eecb9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/serial_api.c +++ /dev/null @@ -1,806 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "mbed_assert.h" -#include "cmsis.h" -#include "serial_api.h" -#include "sysclk.h" -#include "serial_platform.h" -#include "ioport.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "pdc.h" - -#if DEVICE_SERIAL_ASYNCH -#define pUSART_S(obj) obj->serial.uart -#define pSERIAL_S(obj) ((struct serial_s*)&(obj->serial)) -#else -#define pUSART_S(obj) obj->uart -#define pSERIAL_S(obj) ((struct serial_s*)obj) -#endif -#define _USART(obj) ((Usart*)pUSART_S(obj)) -#define USART_NUM 8 - -static uint8_t serial_get_index(serial_t *obj); -static IRQn_Type get_serial_irq_num (serial_t *obj); -static uint32_t get_serial_vector (serial_t *obj); -static uint32_t serial_irq_ids[USART_NUM] = {0}; -static uart_irq_handler irq_handler; -static void uart0_irq(void); -static void uart1_irq(void); -static void uart2_irq(void); -static void uart3_irq(void); -static void uart4_irq(void); -static void uart5_irq(void); -static void uart6_irq(void); -static void uart7_irq(void); - - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -extern uint8_t g_sys_init; - -static int get_usart_clock_id(UARTName peripheral) -{ - int cid; - switch (peripheral) { - case UART_0: - cid = ID_FLEXCOM0; - break; - case UART_1: - cid = ID_FLEXCOM1; - break; - case UART_2: - cid = ID_FLEXCOM2; - break; - case UART_3: - cid = ID_FLEXCOM3; - break; - case UART_4: - cid = ID_FLEXCOM4; - break; - case UART_5: - cid = ID_FLEXCOM5; - break; - case UART_6: - cid = ID_FLEXCOM6; - break; - case UART_7: - cid = ID_FLEXCOM7; - break; - default : - cid = NC; - break; - } - return cid; -} - -static int get_flexcom_id(UARTName peripheral) -{ - int fid; - switch (peripheral) { - case UART_0: - fid = (int)FLEXCOM0; - break; - case UART_1: - fid = (int)FLEXCOM1; - break; - case UART_2: - fid = (int)FLEXCOM2; - break; - case UART_3: - fid = (int)FLEXCOM3; - break; - case UART_4: - fid = (int)FLEXCOM4; - break; - case UART_5: - fid = (int)FLEXCOM5; - break; - case UART_6: - fid = (int)FLEXCOM6; - break; - case UART_7: - fid = (int)FLEXCOM7; - break; - default : - fid = NC; - break; - } - return fid; -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - int clockid = NC, flexcom = NC; - - /*To determine the uart peripheral associated with pins*/ - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - - MBED_ASSERT(uart != (UARTName)NC); - - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - pUSART_S(obj) = uart; - pSERIAL_S(obj)->uart_serial_options.baudrate = (9600UL); - pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_8_BIT; - pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_NO; - pSERIAL_S(obj)->uart_serial_options.stopbits = US_MR_NBSTOP_1_BIT; - pSERIAL_S(obj)->actrec = false; - pSERIAL_S(obj)->acttra = false; - - /* Configure UART pins */ - if(tx != NC) { - pin_function(tx, pinmap_find_function(tx, PinMap_UART_TX)); - ioport_disable_pin(tx); - } - if(rx != NC) { - pin_function(rx, pinmap_find_function(rx, PinMap_UART_RX)); - ioport_disable_pin(rx); - } - clockid = get_usart_clock_id(uart); - if (clockid != NC) { - sysclk_enable_peripheral_clock(clockid); - } - - flexcom = (int)get_flexcom_id(uart); -#if (!SAM4L) -#if (SAMG55) - /* Configure flexcom for usart */ - flexcom_enable((Flexcom* )flexcom); - flexcom_set_opmode((Flexcom* )flexcom, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(clockid); -#endif - /* Configure USART */ - usart_init_rs232((Usart*)uart, (sam_usart_opt_t*)&(pSERIAL_S(obj)->uart_serial_options), - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(clockid); - /* Configure USART */ - usart_init_rs232((Usart*)uart, (sam_usart_opt_t*)&(pSERIAL_S(obj)->uart_serial_options, sysclk_get_peripheral_bus_hz((Usart*)uart)); -#endif - /* Disable rx and tx in case 1 line only required to be configured for usart */ - usart_disable_tx((Usart*)uart); - usart_disable_rx((Usart*)uart); - /* Enable the receiver and transmitter. */ - if(tx != NC) { - usart_enable_tx((Usart*)uart); - } - if(rx != NC) { - usart_enable_rx((Usart*)uart); - } - - if(uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - usart_reset(_USART(obj)); -} - -void serial_baud(serial_t *obj, int baudrate) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT((baudrate == 110) || (baudrate == 150) || (baudrate == 300) || (baudrate == 1200) || - (baudrate == 2400) || (baudrate == 4800) || (baudrate == 9600) || (baudrate == 19200) || (baudrate == 38400) || - (baudrate == 57600) || (baudrate == 115200) || (baudrate == 230400) || (baudrate == 460800) || (baudrate == 921600) ); - uint32_t clockid = 0; - clockid = get_usart_clock_id(pUSART_S(obj)); - if (clockid != (uint32_t)NC) { - sysclk_disable_peripheral_clock(clockid); - } - pSERIAL_S(obj)->uart_serial_options.baudrate = baudrate; - usart_serial_init(_USART(obj), &(pSERIAL_S(obj)->uart_serial_options)); - sysclk_enable_peripheral_clock(clockid); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8)); - - uint32_t clockid = 0; - clockid = get_usart_clock_id(pUSART_S(obj)); - if (clockid != (uint32_t)NC) { - sysclk_disable_peripheral_clock(clockid); - } - - switch(stop_bits) { /*selecting the stop bits*/ - case 1: - pSERIAL_S(obj)->uart_serial_options.stopbits = US_MR_NBSTOP_1_BIT; - break; - case 2: - pSERIAL_S(obj)->uart_serial_options.stopbits = US_MR_NBSTOP_2_BIT; - break; - } - - switch(parity) { /*selecting the parity bits*/ - case ParityNone: - pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_NO; - break; - case ParityOdd: - pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_ODD; - break; - case ParityEven: - pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_EVEN; - break; - case ParityForced1: /*No Hardware Support*/ - MBED_ASSERT(0); - break; - case ParityForced0: /*No Hardware Support*/ - MBED_ASSERT(0); - break; - } - - switch(data_bits) { /*selecting the data bits*/ - case 5: - pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_5_BIT; - break; - case 6: - pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_6_BIT; - break; - case 7: - pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_7_BIT; - break; - case 8: - pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_8_BIT; - break; - } - - usart_serial_init(_USART(obj), &(pSERIAL_S(obj)->uart_serial_options)); - sysclk_enable_peripheral_clock(clockid); -} - -#if DEVICE_SERIAL_FC - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - - if(FlowControlNone == type) { - /* Disable Hardware Handshaking. */ - _USART(obj)->US_MR = (_USART(obj)->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_NORMAL; - return; - } - - /*To determine the uart peripheral associated with pins*/ - UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); - UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); - UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts); - MBED_ASSERT(uart != (UARTName)NC); - - if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) { - /* Configure CTS pin. */ - pin_function(txflow, pinmap_find_function(txflow, PinMap_UART_CTS)); - ioport_disable_pin(txflow); - } - - if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) { - /* Configure CTS pin. */ - pin_function(rxflow, pinmap_find_function(rxflow, PinMap_UART_RTS)); - ioport_disable_pin(rxflow); - } - - /* Set hardware handshaking mode. */ - _USART(obj)->US_MR = (_USART(obj)->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_HW_HANDSHAKING; -} - -#endif //DEVICE_SERIAL_FC - -void serial_break_set(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - _USART(obj)->US_CR = US_CR_STTBRK; - -} - -void serial_break_clear(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - _USART(obj)->US_CR = US_CR_STPBRK; - -} - -void serial_pinout_tx(PinName tx) -{ - pin_function(tx, pinmap_find_function(tx, PinMap_UART_TX)); - ioport_disable_pin(tx); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - irq_handler = handler; - serial_irq_ids[serial_get_index(obj)] = id; -} - -#warning "Interrupt only available for Serial Receive complete. Transmit complete not supported by Controller" - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - vector = get_serial_vector(obj); - irq_n = get_serial_irq_num(obj); - - if (enable) { - switch (irq) { - case RxIrq: - usart_enable_interrupt(_USART(obj), US_IER_RXRDY); - break; - case TxIrq: - break; - } - NVIC_ClearPendingIRQ(irq_n); - NVIC_DisableIRQ(irq_n); - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - } else { - switch (irq) { - case RxIrq: - usart_disable_interrupt(_USART(obj), US_IER_RXRDY); - break; - case TxIrq: - break; - } - NVIC_DisableIRQ(irq_n); - } -} - -static inline void uart_irq(Usart *const usart, uint32_t index) -{ - MBED_ASSERT(usart != (void*)0); - uint32_t mask, status; - /* Read and clear mask. */ - status = usart_get_status(usart); - mask = usart_get_interrupt_mask(usart); - status &= mask; - - if (serial_irq_ids[index] != 0) { - if (status & US_IER_RXRDY) { /*For Receive Complete*/ - if (irq_handler) { - irq_handler(serial_irq_ids[index], RxIrq); - } - } - } -} - -void uart0_irq(void) -{ - uart_irq(USART0, 0); -} - -void uart1_irq(void) -{ - uart_irq(USART1, 1); -} - -void uart2_irq(void) -{ - uart_irq(USART2, 2); -} - -void uart3_irq(void) -{ - uart_irq(USART3, 3); -} - -void uart4_irq(void) -{ - uart_irq(USART4, 4); -} - -void uart5_irq(void) -{ - uart_irq(USART5, 5); -} - -void uart6_irq(void) -{ - uart_irq(USART6, 6); -} - -void uart7_irq(void) -{ - uart_irq(USART7, 7); -} - -static uint8_t serial_get_index(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - switch ((int)pUSART_S(obj)) { - case UART_0: - return 0; - case UART_1: - return 1; - case UART_2: - return 2; - case UART_3: - return 3; - case UART_4: - return 4; - case UART_5: - return 5; - case UART_6: - return 6; - case UART_7: - return 7; - } - return 0; -} - -static uint32_t get_serial_vector (serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t vector = 0; - switch ((int)pUSART_S(obj)) { - case UART_0: - vector = (uint32_t)uart0_irq; - break; - case UART_1: - vector = (uint32_t)uart1_irq; - break; - case UART_2: - vector = (uint32_t)uart2_irq; - break; - case UART_3: - vector = (uint32_t)uart3_irq; - break; - case UART_4: - vector = (uint32_t)uart4_irq; - break; - case UART_5: - vector = (uint32_t)uart5_irq; - break; - case UART_6: - vector = (uint32_t)uart6_irq; - break; - case UART_7: - vector = (uint32_t)uart7_irq; - break; - } - return vector; -} - -IRQn_Type get_serial_irq_num (serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - switch ((int)pUSART_S(obj)) { - case UART_0: - return FLEXCOM0_IRQn; - case UART_1: - return FLEXCOM1_IRQn; - case UART_2: - return FLEXCOM2_IRQn; - case UART_3: - return FLEXCOM3_IRQn; - case UART_4: - return FLEXCOM4_IRQn; - case UART_5: - return FLEXCOM5_IRQn; - case UART_6: - return FLEXCOM6_IRQn; - case UART_7: - return FLEXCOM7_IRQn; - default: - MBED_ASSERT(0); - } - return 0; /*Warning Suppression*/ -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - while (!serial_readable(obj)); - return (int)((_USART(obj)->US_RHR & US_RHR_RXCHR_Msk) & 0xFF); -} - -void serial_putc(serial_t *obj, int c) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - while (!serial_writable(obj)); - _USART(obj)->US_THR = US_THR_TXCHR(c); -} - -int serial_readable(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t status = 1; - if (!(_USART(obj)->US_CSR & US_CSR_RXRDY)) { - status = 0; - } else { - status = 1; - } - return status; -} - -int serial_writable(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t status = 1; - if (!(_USART(obj)->US_CSR & US_CSR_TXRDY)) { - status = 0; - } else { - status = 1; - } - return status; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_UART_RTS; -} - -/************************************************************************************ - * ASYNCHRONOUS HAL * - ************************************************************************************/ - - -#if DEVICE_SERIAL_ASYNCH -/************************************ - * HELPER FUNCTIONS * - ***********************************/ - -void serial_set_char_match(serial_t *obj, uint8_t char_match) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - if (char_match != SERIAL_RESERVED_CHAR_MATCH) { - obj->char_match = char_match; - _USART(obj)->US_CMPR = (char_match & 0xFF); - usart_enable_interrupt(_USART(obj), US_IER_CMP); - } -} - -/************************************ - * TRANSFER FUNCTIONS * - ***********************************/ -int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(tx != (void*)0); - if(tx_length == 0) return 0; - Pdc *pdc_base; - IRQn_Type irq_n = (IRQn_Type)0; - pdc_packet_t packet; - - pSERIAL_S(obj)->acttra = true; /* flag for active transmit transfer */ - - irq_n = get_serial_irq_num(obj); - - /* Get board USART PDC base address and enable transmitter. */ - pdc_base = usart_get_pdc_base(_USART(obj)); - pdc_enable_transfer(pdc_base, PERIPH_PTCR_TXTEN); - - packet.ul_addr = (uint32_t)tx; - packet.ul_size = (uint32_t)tx_length; - - pdc_tx_init(pdc_base, &packet, NULL); - usart_enable_interrupt(_USART(obj), US_IER_TXBUFE); - - NVIC_ClearPendingIRQ(irq_n); - NVIC_DisableIRQ(irq_n); - NVIC_SetVector(irq_n, (uint32_t)handler); - NVIC_EnableIRQ(irq_n); - - return 0; -} - -void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); - if(rx_length == 0) return 0; - Pdc *pdc_base; - IRQn_Type irq_n = (IRQn_Type)0; - pdc_packet_t packet; - - pSERIAL_S(obj)->actrec = true; /* flag for active receive transfer */ - if (event == SERIAL_EVENT_RX_CHARACTER_MATCH) { /* if event is character match alone */ - pSERIAL_S(obj)->events = SERIAL_EVENT_RX_CHARACTER_MATCH; - } - - irq_n = get_serial_irq_num(obj); - - serial_set_char_match(obj, char_match); - - /* Get board USART PDC base address and enable transmitter. */ - pdc_base = usart_get_pdc_base(_USART(obj)); - pdc_enable_transfer(pdc_base, PERIPH_PTCR_RXTEN); - packet.ul_addr = (uint32_t)rx; - packet.ul_size = (uint32_t)rx_length; - pdc_rx_init(pdc_base, &packet, NULL); - - usart_enable_interrupt(_USART(obj), (US_IER_RXBUFF | US_IER_OVRE | US_IER_FRAME | US_IER_PARE)); - - NVIC_ClearPendingIRQ(irq_n); - NVIC_DisableIRQ(irq_n); - NVIC_SetVector(irq_n, (uint32_t)handler); - NVIC_EnableIRQ(irq_n); - -} - -uint8_t serial_tx_active(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - return pSERIAL_S(obj)->acttra; -} - -uint8_t serial_rx_active(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - return pSERIAL_S(obj)->actrec; -} - -int serial_tx_irq_handler_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - serial_tx_abort_asynch(obj); - return SERIAL_EVENT_TX_COMPLETE; -} -int serial_rx_irq_handler_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t ul_status, ulmask; - - /* Read USART Status. */ - ul_status = usart_get_status(_USART(obj)); - ulmask = usart_get_interrupt_mask(_USART(obj)); - ul_status &= ulmask; - - if (ul_status & US_CSR_OVRE) { /* Overrun Error */ - usart_disable_interrupt(_USART(obj), US_IDR_OVRE); - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_OVERFLOW; - } - if (ul_status & US_CSR_FRAME) { /* Framing Error */ - usart_disable_interrupt(_USART(obj), US_IDR_FRAME); - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_FRAMING_ERROR; - } - if (ul_status & US_CSR_PARE) { /* Parity Error */ - usart_disable_interrupt(_USART(obj), US_IDR_PARE); - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_PARITY_ERROR; - } - if ((ul_status & (US_IER_RXBUFF | US_IER_CMP)) == (US_IER_RXBUFF | US_IER_CMP)) { /* Character match in last character in transfer*/ - usart_disable_interrupt(_USART(obj), US_IDR_CMP); - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_COMPLETE|SERIAL_EVENT_RX_CHARACTER_MATCH; - } - if (ul_status & US_IER_CMP) { /* Character match */ - usart_disable_interrupt(_USART(obj), US_IDR_CMP); - if (pSERIAL_S(obj)->events == SERIAL_EVENT_RX_CHARACTER_MATCH) { /*if character match is the only event abort transfer */ - serial_rx_abort_asynch(obj); - } - return SERIAL_EVENT_RX_CHARACTER_MATCH; - } - if (ul_status & US_IER_RXBUFF) { /* Reception Complete */ - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_COMPLETE; - } - return 0; -} - -int serial_irq_handler_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - uint32_t ul_status, ulmask; - - /* Read USART Status. */ - ul_status = usart_get_status(_USART(obj)); - ulmask = usart_get_interrupt_mask(_USART(obj)); - - ul_status &= ulmask; - - if (ul_status & (US_CSR_RXBUFF | US_CSR_OVRE | US_CSR_FRAME | US_CSR_PARE | US_IER_CMP)) { - return serial_rx_irq_handler_asynch(obj); - } - if (ul_status & US_CSR_TXBUFE) { - return serial_tx_irq_handler_asynch(obj); - } - return 0; -} - -void serial_tx_abort_asynch(serial_t *obj) -{ - /* Sanity check arguments */ - MBED_ASSERT(obj); - Pdc *pdc_base; - usart_disable_interrupt(_USART(obj), US_IER_TXBUFE); - pdc_base = usart_get_pdc_base(_USART(obj)); - pdc_disable_transfer(pdc_base, PERIPH_PTCR_TXTEN); - pSERIAL_S(obj)->acttra = false; -} - -void serial_rx_abort_asynch(serial_t *obj) -{ - IRQn_Type irq_n = (IRQn_Type)0; - /* Sanity check arguments */ - MBED_ASSERT(obj); - Pdc *pdc_base; - usart_disable_interrupt(_USART(obj), US_IER_RXBUFF); - pdc_base = usart_get_pdc_base(_USART(obj)); - pdc_disable_transfer(pdc_base, PERIPH_PTCR_RXTEN); - irq_n = get_serial_irq_num(obj); - NVIC_ClearPendingIRQ(irq_n); - NVIC_DisableIRQ(irq_n); - pSERIAL_S(obj)->actrec = false; -} - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/dfll.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/dfll.h deleted file mode 100644 index 95b676d295c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/dfll.h +++ /dev/null @@ -1,402 +0,0 @@ -/** - * \file - * - * \brief DFLL management - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CLK_DFLL_H_INCLUDED -#define CLK_DFLL_H_INCLUDED - -#include -#include "conf_clock.h" - -#if UC3L -# include "uc3l/dfll.h" -#elif SAM4L -# include "sam4l/dfll.h" -#else -# error Unsupported chip type -#endif - -/** - * \ingroup clk_group - * \defgroup dfll_group DFLL Management - * - * A Digital Frequency Locked Loop can be used to generate a highly - * accurate frequency from a slower-running reference clock, in much the - * same way as a PLL. DFLLs typically have shorter startup times and - * less jitter. They can also be used in open-loop mode to generate a - * less accurate frequency without the use of a reference clock. - * - * There may be significant variations between platforms in the support - * for certain features. - * - * \par Example: Setting up DFLL0 with default parameters and dithering enabled - * - * The following example shows how to configure and enable DFLL0 in - * closed-loop mode using the default parameters specified through - * configuration symbols. - * \code - dfll_enable_config_defaults(0); \endcode - * - * To configure and enable DFLL0 in closed-loop mode using the default - * parameters and to enable specific feature like dithering for better accuracy, - * you can use this initialization process. - * \code - struct dfll_config dfllcfg; - - dfll_enable_source(CONFIG_DFLL0_SOURCE); - dfll_config_defaults(&dfllcfg, 0); - dfll_config_enable_dithering(&dfllcfg); - dfll_enable(&dfllcfg, 0); - dfll_wait_for_accurate_lock(0); \endcode - * - * When the last function call returns, DFLL0 is running at a frequency - * which matches the default configuration as accurately as possible. - * Any additional alterations to the default configuration can be added - * at the same place as the call to dfll_config_enable_dithering(), but - * note that the DFLL will never achieve "accurate" lock if dithering is - * disabled. - * - * @{ - */ - -//! \name Chip-specific DFLL characteristics -//@{ -/** - * \def NR_DFLLS - * \brief Number of on-chip DFLLs. - */ -/** - * \def DFLL_MIN_HZ - * \brief Minimum frequency that the DFLL can generate. - */ -/** - * \def DFLL_MAX_HZ - * \brief Maximum frequency that the DFLL can generate. - */ -//@} - -/** - * \typedef dfll_refclk_t - * \brief Type used for identifying a reference clock source for the DFLL. - */ - -//! \name DFLL Configuration -//@{ - -/** - * \struct dfll_config - * \brief Hardware-specific representation of DFLL configuration. - * - * This structure contains one or more device-specific values - * representing the current DFLL configuration. The contents of this - * structure is typically different from platform to platform, and the - * user should not access any fields except through the DFLL - * configuration API. - */ - -/** - * \fn void dfll_config_init_open_loop_mode(struct dfll_config *cfg) - * \brief Configure the DFLL configuration \a cfg for open-loop mode. - * - * \param cfg The DFLL configuration to be initialized. - */ -/** - * \fn void dfll_config_init_closed_loop_mode(struct dfll_config *cfg, - * dfll_refclk_t refclk, uint16_t div, uint16_t mul) - * \brief Configure the DFLL configuration \a cfg for closed-loop mode. - * - * \param cfg The DFLL configuration to be initialized. - * \param refclk The reference clock source. - * \param div Reference clock divider. - * \param mul Multiplier (integer part only). - */ -/** - * \def dfll_config_defaults(cfg, dfll_id) - * \brief Initialize DFLL configuration using default parameters. - * - * After this function returns, \a cfg will contain a configuration - * which will make the DFLL run at (CONFIG_DFLLx_MUL / CONFIG_DFLLx_DIV) - * times the frequency of CONFIG_DFLLx_SOURCE. The default configuration - * will always use closed-loop mode with no fractional multiplier. - * - * \param cfg The DFLL configuration to be initialized. - * \param dfll_id Use defaults for this DFLL. - */ -/** - * \def dfll_get_default_rate(dfll_id) - * \brief Return the default rate in Hz of \a dfll_id. - */ - -/** - * \fn void dfll_config_set_fractional_multiplier(struct dfll_config *cfg, - * uint16_t mul_i, uint16_t mul_f) - * \brief Set a fractional multiplier. - * - * This function has no effect in open-loop mode, and is only available - * on devices which support fractional multipliers. - * - * The fractional part of the multiplier is assumed to be 16 bits. The - * low-level driver will make sure to shift this value to match the - * hardware if necessary. - * - * \param cfg The DFLL configuration to be modified. - * \param mul_i Integer part of multiplier. - * \param mul_f Fractional part of multiplier. - */ -/** - * \fn void dfll_config_enable_dithering(struct dfll_config *cfg) - * \brief Enable dithering for more accurate frequency generation. - * - * The fine LSB input to the VCO is dithered to achieve fractional - * approximation to the correct multiplication ratio. - * - * \param cfg The DFLL configuration to be modified. - */ -/** - * \fn void dfll_config_disable_dithering(struct dfll_config *cfg) - * \brief Disable dithering. - * - * \see dfll_config_enable_dithering() - * - * \param cfg The DFLL configuration to be modified. - */ -/** - * \fn void dfll_config_set_initial_tuning(struct dfll_config *cfg, - * uint16_t coarse, uint16_t fine) - * \brief Set initial VCO tuning. - * - * In open loop mode, this will determine the frequency of the output. - * - * In closed loop mode, this will provide an initial estimate of the VCO - * tuning. While the DFLL will automatically adjust these values to - * match the desired output frequency, careful selection of initial - * values might reduce the time to achieve coarse and fine lock. - * - * \param cfg The DFLL configuration to be modified. - * \param coarse Coarse tuning of the frequency generator. - * \param fine Fine tuning of the frequency generator. - */ -/** - * \fn void dfll_config_set_max_step(struct dfll_config *cfg, - * uint16_t coarse, uint16_t fine) - * \brief Set the maximum VCO tuning step size. - * - * This function has no effect in open-loop mode. - * - * By default, both of these values are set to 50% of their respective - * maximums. It is not recommended to set the values any higher than - * this, but setting them lower might reduce the frequency overshoot at - * the expense of longer time to achieve coarse and/or fine lock. - * - * \param cfg The DFLL configuration to be modified - * \param coarse The maximum step size of the coarse VCO tuning. - * \param fine The maximum step size of the fine VCO tuning. - */ -/** - * \fn void dfll_config_enable_ssg(struct dfll_config *cfg, - * uint16_t amplitude, uint16_t step_size) - * \brief Enable Spread Spectrum Generator. - * - * \param cfg The DFLL configuration to be modified. - * \param amplitude The amplitude of the spread spectrum. - * \param step_size The step size of the spread spectrum. - */ -/** - * \fn void dfll_config_disable_ssg(struct dfll_config *cfg) - * \brief Disable Spread Spectrum Generator. - * - * \param cfg The DFLL configuration to be modified. - */ -//@} - -//! \name Interaction with the DFLL hardware -//@{ -/** - * \fn void dfll_enable_open_loop(const struct dfll_config *cfg, - * unsigned int dfll_id) - * \brief Activate the configuration \a cfg and enable DFLL \a dfll_id - * in open-loop mode. - * - * \pre The configuration in \a cfg must represent an open-loop - * configuration. - * - * \param cfg The configuration to be activated. - * \param dfll_id The ID of the DFLL to be enabled. - */ -/** - * \fn void dfll_enable_closed_loop(const struct dfll_config *cfg, - * unsigned int dfll_id) - * \brief Activate the configuration \a cfg and enable DFLL \a dfll_id - * in closed-loop mode. - * - * \pre The configuration in \a cfg must represent a closed-loop - * configuration. - * - * \param cfg The configuration to be activated. - * \param dfll_id The ID of the DFLL to be enabled. - */ -/** - * \fn void dfll_disable_open_loop(unsigned int dfll_id) - * \brief Disable the DFLL identified by \a dfll_id. - * - * \pre The DFLL must have been enabled in open loop mode. - * - * \param dfll_id The ID of the DFLL to be disabled. - */ -/** - * \fn void dfll_disable_closed_loop(unsigned int dfll_id) - * \brief Disable the DFLL identified by \a dfll_id. - * - * \pre The DFLL must have been enabled in closed loop mode. - * - * \param dfll_id The ID of the DFLL to be disabled. - */ -/** - * \fn bool dfll_is_coarse_locked(unsigned int dfll_id) - * \brief Determine whether or not a DFLL has achieved coarse lock. - * - * \param dfll_id The ID of the DFLL to check. - * - * \retval true The DFLL has determined the final value of the coarse - * VCO tuning value. - * \retval false The DFLL has not yet determined the coarse VCO tuning - * value, or has not been enabled. - */ -/** - * \fn bool dfll_is_fine_locked(unsigned int dfll_id) - * \brief Determine whether or not a DFLL has achieved fine lock. - * - * \param dfll_id The ID of the DFLL to check. - * - * \retval true The DFLL has determined the final value of the fine VCO - * tuning value. - * \retval false The DFLL has not yet determined the fine VCO tuning - * value, or has not been enabled. - */ -/** - * \fn bool dfll_is_accurate_locked(unsigned int dfll_id) - * \brief Determine whether or not a DFLL has achieved accurate lock. - * - * \param dfll_id The ID of the DFLL to check. - * - * \retval true The DFLL has determined the final dithering duty cycle. - * \retval false The DFLL has not yet determined the dithering duty - * cycle, or has not been enabled with dithering enabled. - */ -/** - * \fn void dfll_enable_source(enum dfll_refclk_t src) - * \brief Enable the source of the dfll. - * The source is enabled, if the source is not already running. - * - * \param dfll_source src The ID of the DFLL source to enable. - */ -/** - * \fn void dfll_enable_config_defaults(unsigned int dfll_id) - * \brief Enable the dfll with the default configuration. - * DFLL is enabled, if the DFLL is not already locked. - * - * \param dfll_id The ID of the DFLL to enable. - */ - -/** - * \brief Wait for the DFLL identified by \a dfll_id to achieve coarse - * lock. - * - * \param dfll_id The ID of the DFLL to wait for. - * - * \retval STATUS_OK The DFLL has achieved coarse lock. - * \retval ERR_TIMEOUT Timed out waiting for lock. - */ -static inline int dfll_wait_for_coarse_lock(unsigned int dfll_id) -{ - /* TODO: Add timeout mechanism */ - while (!dfll_is_coarse_locked(dfll_id)) { - /* Do nothing */ - } - - return 0; -} - -/** - * \brief Wait for the DFLL identified by \a dfll_id to achieve fine - * lock. - * - * \param dfll_id The ID of the DFLL to wait for. - * - * \retval STATUS_OK The DFLL has achieved fine lock. - * \retval ERR_TIMEOUT Timed out waiting for lock. - */ -static inline int dfll_wait_for_fine_lock(unsigned int dfll_id) -{ - /* TODO: Add timeout mechanism */ - while (!dfll_is_fine_locked(dfll_id)) { - /* Do nothing */ - } - - return 0; -} - -/** - * \brief Wait for the DFLL identified by \a dfll_id to achieve accurate - * lock. - * - * \param dfll_id The ID of the DFLL to wait for. - * - * \retval STATUS_OK The DFLL has achieved accurate lock. - * \retval ERR_TIMEOUT Timed out waiting for lock. - */ -static inline int dfll_wait_for_accurate_lock(unsigned int dfll_id) -{ - /* TODO: Add timeout mechanism */ - while (!dfll_is_accurate_locked(dfll_id)) { - /* Do nothing */ - } - - return 0; -} - -//@} -//! @} - -#endif /* CLK_DFLL_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/genclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/genclk.h deleted file mode 100644 index 18156b66530..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/genclk.h +++ /dev/null @@ -1,199 +0,0 @@ -/** - * \file - * - * \brief Generic clock management - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CLK_GENCLK_H_INCLUDED -#define CLK_GENCLK_H_INCLUDED - -#include "parts.h" - -#if SAM3S -# include "sam3s/genclk.h" -#elif SAM3U -# include "sam3u/genclk.h" -#elif SAM3N -# include "sam3n/genclk.h" -#elif SAM3XA -# include "sam3x/genclk.h" -#elif SAM4S -# include "sam4s/genclk.h" -#elif SAM4L -# include "sam4l/genclk.h" -#elif SAM4E -# include "sam4e/genclk.h" -#elif SAM4N -# include "sam4n/genclk.h" -#elif SAM4C -# include "sam4c/genclk.h" -#elif SAM4CM -# include "sam4cm/genclk.h" -#elif SAM4CP -# include "sam4cp/genclk.h" -#elif SAMG -# include "samg/genclk.h" -#elif SAMV71 -# include "samv71/genclk.h" -#elif SAMV70 -# include "samv70/genclk.h" -#elif SAME70 -# include "same70/genclk.h" -#elif SAMS70 -# include "sams70/genclk.h" -#elif (UC3A0 || UC3A1) -# include "uc3a0_a1/genclk.h" -#elif UC3A3 -# include "uc3a3_a4/genclk.h" -#elif UC3B -# include "uc3b0_b1/genclk.h" -#elif UC3C -# include "uc3c/genclk.h" -#elif UC3D -# include "uc3d/genclk.h" -#elif UC3L -# include "uc3l/genclk.h" -#else -# error Unsupported chip type -#endif - -/** - * \ingroup clk_group - * \defgroup genclk_group Generic Clock Management - * - * Generic clocks are configurable clocks which run outside the system - * clock domain. They are often connected to peripherals which have an - * asynchronous component running independently of the bus clock, e.g. - * USB controllers, low-power timers and RTCs, etc. - * - * Note that not all platforms have support for generic clocks; on such - * platforms, this API will not be available. - * - * @{ - */ - -/** - * \def GENCLK_DIV_MAX - * \brief Maximum divider supported by the generic clock implementation - */ -/** - * \enum genclk_source - * \brief Generic clock source ID - * - * Each generic clock may be generated from a different clock source. - * These are the available alternatives provided by the chip. - */ - -//! \name Generic clock configuration -//@{ -/** - * \struct genclk_config - * \brief Hardware representation of a set of generic clock parameters - */ -/** - * \fn void genclk_config_defaults(struct genclk_config *cfg, - * unsigned int id) - * \brief Initialize \a cfg to the default configuration for the clock - * identified by \a id. - */ -/** - * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id) - * \brief Read the currently active configuration of the clock - * identified by \a id into \a cfg. - */ -/** - * \fn void genclk_config_write(const struct genclk_config *cfg, - * unsigned int id) - * \brief Activate the configuration \a cfg on the clock identified by - * \a id. - */ -/** - * \fn void genclk_config_set_source(struct genclk_config *cfg, - * enum genclk_source src) - * \brief Select a new source clock \a src in configuration \a cfg. - */ -/** - * \fn void genclk_config_set_divider(struct genclk_config *cfg, - * unsigned int divider) - * \brief Set a new \a divider in configuration \a cfg. - */ -/** - * \fn void genclk_enable_source(enum genclk_source src) - * \brief Enable the source clock \a src used by a generic clock. - */ -//@} - -//! \name Enabling and disabling Generic Clocks -//@{ -/** - * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id) - * \brief Activate the configuration \a cfg on the clock identified by - * \a id and enable it. - */ -/** - * \fn void genclk_disable(unsigned int id) - * \brief Disable the generic clock identified by \a id. - */ -//@} - -/** - * \brief Enable the configuration defined by \a src and \a divider - * for the generic clock identified by \a id. - * - * \param id The ID of the generic clock. - * \param src The source clock of the generic clock. - * \param divider The divider used to generate the generic clock. - */ -static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider) -{ - struct genclk_config gcfg; - - genclk_config_defaults(&gcfg, id); - genclk_enable_source(src); - genclk_config_set_source(&gcfg, src); - genclk_config_set_divider(&gcfg, divider); - genclk_enable(&gcfg, id); -} - -//! @} - -#endif /* CLK_GENCLK_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/osc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/osc.h deleted file mode 100644 index 0cfddd5cdaf..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/osc.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * \brief Oscillator management - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef OSC_H_INCLUDED -#define OSC_H_INCLUDED - -#include "parts.h" -#include "conf_clock.h" - -#if SAM3S -# include "sam3s/osc.h" -#elif SAM3XA -# include "sam3x/osc.h" -#elif SAM3U -# include "sam3u/osc.h" -#elif SAM3N -# include "sam3n/osc.h" -#elif SAM4S -# include "sam4s/osc.h" -#elif SAM4E -# include "sam4e/osc.h" -#elif SAM4C -# include "sam4c/osc.h" -#elif SAM4CM -# include "sam4cm/osc.h" -#elif SAM4CP -# include "sam4cp/osc.h" -#elif SAM4L -# include "sam4l/osc.h" -#elif SAM4N -# include "sam4n/osc.h" -#elif SAMG -# include "samg/osc.h" -#elif SAMV71 -# include "samv71/osc.h" -#elif SAMV70 -# include "samv70/osc.h" -#elif SAME70 -# include "same70/osc.h" -#elif SAMS70 -# include "sams70/osc.h" -#elif (UC3A0 || UC3A1) -# include "uc3a0_a1/osc.h" -#elif UC3A3 -# include "uc3a3_a4/osc.h" -#elif UC3B -# include "uc3b0_b1/osc.h" -#elif UC3C -# include "uc3c/osc.h" -#elif UC3D -# include "uc3d/osc.h" -#elif UC3L -# include "uc3l/osc.h" -#elif XMEGA -# include "xmega/osc.h" -#else -# error Unsupported chip type -#endif - -/** - * \ingroup clk_group - * \defgroup osc_group Oscillator Management - * - * This group contains functions and definitions related to configuring - * and enabling/disabling on-chip oscillators. Internal RC-oscillators, - * external crystal oscillators and external clock generators are - * supported by this module. What all of these have in common is that - * they swing at a fixed, nominal frequency which is normally not - * adjustable. - * - * \par Example: Enabling an oscillator - * - * The following example demonstrates how to enable the external - * oscillator on XMEGA A and wait for it to be ready to use. The - * oscillator identifiers are platform-specific, so while the same - * procedure is used on all platforms, the parameter to osc_enable() - * will be different from device to device. - * \code - osc_enable(OSC_ID_XOSC); - osc_wait_ready(OSC_ID_XOSC); \endcode - * - * \section osc_group_board Board-specific Definitions - * If external oscillators are used, the board code must provide the - * following definitions for each of those: - * - \b BOARD__HZ: The nominal frequency of the oscillator. - * - \b BOARD__STARTUP_US: The startup time of the - * oscillator in microseconds. - * - \b BOARD__TYPE: The type of oscillator connected, i.e. - * whether it's a crystal or external clock, and sometimes what kind - * of crystal it is. The meaning of this value is platform-specific. - * - * @{ - */ - -//! \name Oscillator Management -//@{ -/** - * \fn void osc_enable(uint8_t id) - * \brief Enable oscillator \a id - * - * The startup time and mode value is automatically determined based on - * definitions in the board code. - */ -/** - * \fn void osc_disable(uint8_t id) - * \brief Disable oscillator \a id - */ -/** - * \fn osc_is_ready(uint8_t id) - * \brief Determine whether oscillator \a id is ready. - * \retval true Oscillator \a id is running and ready to use as a clock - * source. - * \retval false Oscillator \a id is not running. - */ -/** - * \fn uint32_t osc_get_rate(uint8_t id) - * \brief Return the frequency of oscillator \a id in Hz - */ - -#ifndef __ASSEMBLY__ - -/** - * \brief Wait until the oscillator identified by \a id is ready - * - * This function will busy-wait for the oscillator identified by \a id - * to become stable and ready to use as a clock source. - * - * \param id A number identifying the oscillator to wait for. - */ -static inline void osc_wait_ready(uint8_t id) -{ - while (!osc_is_ready(id)) { - /* Do nothing */ - } -} - -#endif /* __ASSEMBLY__ */ - -//@} - -//! @} - -#endif /* OSC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/pll.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/pll.h deleted file mode 100644 index b15cfc1daac..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/pll.h +++ /dev/null @@ -1,341 +0,0 @@ -/** - * \file - * - * \brief PLL management - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CLK_PLL_H_INCLUDED -#define CLK_PLL_H_INCLUDED - -#include "parts.h" -#include "conf_clock.h" - -#if SAM3S -# include "sam3s/pll.h" -#elif SAM3XA -# include "sam3x/pll.h" -#elif SAM3U -# include "sam3u/pll.h" -#elif SAM3N -# include "sam3n/pll.h" -#elif SAM4S -# include "sam4s/pll.h" -#elif SAM4E -# include "sam4e/pll.h" -#elif SAM4C -# include "sam4c/pll.h" -#elif SAM4CM -# include "sam4cm/pll.h" -#elif SAM4CP -# include "sam4cp/pll.h" -#elif SAM4L -# include "sam4l/pll.h" -#elif SAM4N -# include "sam4n/pll.h" -#elif SAMG -# include "samg/pll.h" -#elif SAMV71 -# include "samv71/pll.h" -#elif SAMV70 -# include "samv70/pll.h" -#elif SAME70 -# include "same70/pll.h" -#elif SAMS70 -# include "sams70/pll.h" -#elif (UC3A0 || UC3A1) -# include "uc3a0_a1/pll.h" -#elif UC3A3 -# include "uc3a3_a4/pll.h" -#elif UC3B -# include "uc3b0_b1/pll.h" -#elif UC3C -# include "uc3c/pll.h" -#elif UC3D -# include "uc3d/pll.h" -#elif (UC3L0128 || UC3L0256 || UC3L3_L4) -# include "uc3l/pll.h" -#elif XMEGA -# include "xmega/pll.h" -#else -# error Unsupported chip type -#endif - -/** - * \ingroup clk_group - * \defgroup pll_group PLL Management - * - * This group contains functions and definitions related to configuring - * and enabling/disabling on-chip PLLs. A PLL will take an input signal - * (the \em source), optionally divide the frequency by a configurable - * \em divider, and then multiply the frequency by a configurable \em - * multiplier. - * - * Some devices don't support input dividers; specifying any other - * divisor than 1 on these devices will result in an assertion failure. - * Other devices may have various restrictions to the frequency range of - * the input and output signals. - * - * \par Example: Setting up PLL0 with default parameters - * - * The following example shows how to configure and enable PLL0 using - * the default parameters specified using the configuration symbols - * listed above. - * \code - pll_enable_config_defaults(0); \endcode - * - * To configure, enable PLL0 using the default parameters and to disable - * a specific feature like Wide Bandwidth Mode (a UC3A3-specific - * PLL option.), you can use this initialization process. - * \code - struct pll_config pllcfg; - if (pll_is_locked(pll_id)) { - return; // Pll already running - } - pll_enable_source(CONFIG_PLL0_SOURCE); - pll_config_defaults(&pllcfg, 0); - pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE); - pll_enable(&pllcfg, 0); - pll_wait_for_lock(0); \endcode - * - * When the last function call returns, PLL0 is ready to be used as the - * main system clock source. - * - * \section pll_group_config Configuration Symbols - * - * Each PLL has a set of default parameters determined by the following - * configuration symbols in the application's configuration file: - * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the - * input of PLL \a n. Must be one of the values defined by the - * #pll_source enum. - * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL - * \a n. - * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n. - * - * These configuration symbols determine the result of calling - * pll_config_defaults() and pll_get_default_rate(). - * - * @{ - */ - -//! \name Chip-specific PLL characteristics -//@{ -/** - * \def PLL_MAX_STARTUP_CYCLES - * \brief Maximum PLL startup time in number of slow clock cycles - */ -/** - * \def NR_PLLS - * \brief Number of on-chip PLLs - */ - -/** - * \def PLL_MIN_HZ - * \brief Minimum frequency that the PLL can generate - */ -/** - * \def PLL_MAX_HZ - * \brief Maximum frequency that the PLL can generate - */ -/** - * \def PLL_NR_OPTIONS - * \brief Number of PLL option bits - */ -//@} - -/** - * \enum pll_source - * \brief PLL clock source - */ - -//! \name PLL configuration -//@{ - -/** - * \struct pll_config - * \brief Hardware-specific representation of PLL configuration. - * - * This structure contains one or more device-specific values - * representing the current PLL configuration. The contents of this - * structure is typically different from platform to platform, and the - * user should not access any fields except through the PLL - * configuration API. - */ - -/** - * \fn void pll_config_init(struct pll_config *cfg, - * enum pll_source src, unsigned int div, unsigned int mul) - * \brief Initialize PLL configuration from standard parameters. - * - * \note This function may be defined inline because it is assumed to be - * called very few times, and usually with constant parameters. Inlining - * it will in such cases reduce the code size significantly. - * - * \param cfg The PLL configuration to be initialized. - * \param src The oscillator to be used as input to the PLL. - * \param div PLL input divider. - * \param mul PLL loop divider (i.e. multiplier). - * - * \return A configuration which will make the PLL run at - * (\a mul / \a div) times the frequency of \a src - */ -/** - * \def pll_config_defaults(cfg, pll_id) - * \brief Initialize PLL configuration using default parameters. - * - * After this function returns, \a cfg will contain a configuration - * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) - * times the frequency of CONFIG_PLLx_SOURCE. - * - * \param cfg The PLL configuration to be initialized. - * \param pll_id Use defaults for this PLL. - */ -/** - * \def pll_get_default_rate(pll_id) - * \brief Get the default rate in Hz of \a pll_id - */ -/** - * \fn void pll_config_set_option(struct pll_config *cfg, - * unsigned int option) - * \brief Set the PLL option bit \a option in the configuration \a cfg. - * - * \param cfg The PLL configuration to be changed. - * \param option The PLL option bit to be set. - */ -/** - * \fn void pll_config_clear_option(struct pll_config *cfg, - * unsigned int option) - * \brief Clear the PLL option bit \a option in the configuration \a cfg. - * - * \param cfg The PLL configuration to be changed. - * \param option The PLL option bit to be cleared. - */ -/** - * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id) - * \brief Read the currently active configuration of \a pll_id. - * - * \param cfg The configuration object into which to store the currently - * active configuration. - * \param pll_id The ID of the PLL to be accessed. - */ -/** - * \fn void pll_config_write(const struct pll_config *cfg, - * unsigned int pll_id) - * \brief Activate the configuration \a cfg on \a pll_id - * - * \param cfg The configuration object representing the PLL - * configuration to be activated. - * \param pll_id The ID of the PLL to be updated. - */ - -//@} - -//! \name Interaction with the PLL hardware -//@{ -/** - * \fn void pll_enable(const struct pll_config *cfg, - * unsigned int pll_id) - * \brief Activate the configuration \a cfg and enable PLL \a pll_id. - * - * \param cfg The PLL configuration to be activated. - * \param pll_id The ID of the PLL to be enabled. - */ -/** - * \fn void pll_disable(unsigned int pll_id) - * \brief Disable the PLL identified by \a pll_id. - * - * After this function is called, the PLL identified by \a pll_id will - * be disabled. The PLL configuration stored in hardware may be affected - * by this, so if the caller needs to restore the same configuration - * later, it should either do a pll_config_read() before disabling the - * PLL, or remember the last configuration written to the PLL. - * - * \param pll_id The ID of the PLL to be disabled. - */ -/** - * \fn bool pll_is_locked(unsigned int pll_id) - * \brief Determine whether the PLL is locked or not. - * - * \param pll_id The ID of the PLL to check. - * - * \retval true The PLL is locked and ready to use as a clock source - * \retval false The PLL is not yet locked, or has not been enabled. - */ -/** - * \fn void pll_enable_source(enum pll_source src) - * \brief Enable the source of the pll. - * The source is enabled, if the source is not already running. - * - * \param src The ID of the PLL source to enable. - */ -/** - * \fn void pll_enable_config_defaults(unsigned int pll_id) - * \brief Enable the pll with the default configuration. - * PLL is enabled, if the PLL is not already locked. - * - * \param pll_id The ID of the PLL to enable. - */ - -/** - * \brief Wait for PLL \a pll_id to become locked - * - * \todo Use a timeout to avoid waiting forever and hanging the system - * - * \param pll_id The ID of the PLL to wait for. - * - * \retval STATUS_OK The PLL is now locked. - * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. - */ -static inline int pll_wait_for_lock(unsigned int pll_id) -{ - Assert(pll_id < NR_PLLS); - - while (!pll_is_locked(pll_id)) { - /* Do nothing */ - } - - return 0; -} - -//@} -//! @} - -#endif /* CLK_PLL_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/genclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/genclk.h deleted file mode 100644 index 5c9f77f629f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/genclk.h +++ /dev/null @@ -1,292 +0,0 @@ -/** - * \file - * - * \brief Chip-specific generic clock management. - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CHIP_GENCLK_H_INCLUDED -#define CHIP_GENCLK_H_INCLUDED - -#include -#include - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \weakgroup genclk_group - * @{ - */ - -//! \name Programmable Clock Identifiers (PCK) -//@{ -#define GENCLK_PCK_0 0 //!< PCK0 ID -#define GENCLK_PCK_1 1 //!< PCK1 ID -#define GENCLK_PCK_2 2 //!< PCK2 ID -#if SAMG55 -#define GENCLK_PCK_3 3 //!< PCK3 ID -#define GENCLK_PCK_4 4 //!< PCK4 ID -#define GENCLK_PCK_5 5 //!< PCK5 ID -#define GENCLK_PCK_6 6 //!< PCK6 ID -#define GENCLK_PCK_7 7 //!< PCK7 ID -#endif -//@} - -//! \name Programmable Clock Sources (PCK) -//@{ - -enum genclk_source { - GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock - GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock - GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_8M_RC = 3, //!< Internal 8MHz RC oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_16M_RC = 4, //!< Internal 16MHz RC oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_24M_RC = 5, //!< Internal 24MHz RC oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock - GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock -#if SAMG55 - GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock - GENCLK_PCK_SRC_MCK = 10, //!< Use Master Clk as PCK source clock -#else - GENCLK_PCK_SRC_MCK = 9, //!< Use Master Clk as PCK source clock -#endif -}; - -//@} - -//! \name Programmable Clock Prescalers (PCK) -//@{ - -enum genclk_divider { - GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1 - GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2 - GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4 - GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8 - GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16 - GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32 - GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64 -}; - -//@} - -struct genclk_config { - uint32_t ctrl; -}; - -static inline void genclk_config_defaults(struct genclk_config *p_cfg, - uint32_t ul_id) -{ - ul_id = ul_id; - p_cfg->ctrl = 0; -} - -static inline void genclk_config_read(struct genclk_config *p_cfg, - uint32_t ul_id) -{ - p_cfg->ctrl = PMC->PMC_PCK[ul_id]; -} - -static inline void genclk_config_write(const struct genclk_config *p_cfg, - uint32_t ul_id) -{ - PMC->PMC_PCK[ul_id] = p_cfg->ctrl; -} - -//! \name Programmable Clock Source and Prescaler configuration -//@{ - -static inline void genclk_config_set_source(struct genclk_config *p_cfg, - enum genclk_source e_src) -{ - p_cfg->ctrl &= (~PMC_PCK_CSS_Msk); - - switch (e_src) { - case GENCLK_PCK_SRC_SLCK_RC: - case GENCLK_PCK_SRC_SLCK_XTAL: - case GENCLK_PCK_SRC_SLCK_BYPASS: - p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK); - break; - - case GENCLK_PCK_SRC_MAINCK_8M_RC: - case GENCLK_PCK_SRC_MAINCK_16M_RC: - case GENCLK_PCK_SRC_MAINCK_24M_RC: - case GENCLK_PCK_SRC_MAINCK_XTAL: - case GENCLK_PCK_SRC_MAINCK_BYPASS: - p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK); - break; - - case GENCLK_PCK_SRC_PLLACK: - p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK); - break; - -#if SAMG55 - case GENCLK_PCK_SRC_PLLBCK: - p_cfg->ctrl |= (PMC_PCK_CSS_PLLB_CLK); - break; -#endif - - case GENCLK_PCK_SRC_MCK: - p_cfg->ctrl |= (PMC_PCK_CSS_MCK); - break; - } -} - -static inline void genclk_config_set_divider(struct genclk_config *p_cfg, - uint32_t e_divider) -{ - p_cfg->ctrl &= ~PMC_PCK_PRES_Msk; - p_cfg->ctrl |= e_divider; -} - -//@} - -static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id) -{ - PMC->PMC_PCK[ul_id] = p_cfg->ctrl; - pmc_enable_pck(ul_id); -} - -static inline void genclk_disable(uint32_t ul_id) -{ - pmc_disable_pck(ul_id); -} - -static inline void genclk_enable_source(enum genclk_source e_src) -{ - switch (e_src) { - case GENCLK_PCK_SRC_SLCK_RC: - if (!osc_is_ready(OSC_SLCK_32K_RC)) { - osc_enable(OSC_SLCK_32K_RC); - osc_wait_ready(OSC_SLCK_32K_RC); - } - break; - - case GENCLK_PCK_SRC_SLCK_XTAL: - if (!osc_is_ready(OSC_SLCK_32K_XTAL)) { - osc_enable(OSC_SLCK_32K_XTAL); - osc_wait_ready(OSC_SLCK_32K_XTAL); - } - break; - - case GENCLK_PCK_SRC_SLCK_BYPASS: - if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) { - osc_enable(OSC_SLCK_32K_BYPASS); - osc_wait_ready(OSC_SLCK_32K_BYPASS); - } - break; - - case GENCLK_PCK_SRC_MAINCK_8M_RC: - if (!osc_is_ready(OSC_MAINCK_8M_RC)) { - osc_enable(OSC_MAINCK_8M_RC); - osc_wait_ready(OSC_MAINCK_8M_RC); - } - break; - - case GENCLK_PCK_SRC_MAINCK_16M_RC: - if (!osc_is_ready(OSC_MAINCK_16M_RC)) { - osc_enable(OSC_MAINCK_16M_RC); - osc_wait_ready(OSC_MAINCK_16M_RC); - } - break; - - case GENCLK_PCK_SRC_MAINCK_24M_RC: - if (!osc_is_ready(OSC_MAINCK_24M_RC)) { - osc_enable(OSC_MAINCK_24M_RC); - osc_wait_ready(OSC_MAINCK_24M_RC); - } - break; - - case GENCLK_PCK_SRC_MAINCK_XTAL: - if (!osc_is_ready(OSC_MAINCK_XTAL)) { - osc_enable(OSC_MAINCK_XTAL); - osc_wait_ready(OSC_MAINCK_XTAL); - } - break; - - case GENCLK_PCK_SRC_MAINCK_BYPASS: - if (!osc_is_ready(OSC_MAINCK_BYPASS)) { - osc_enable(OSC_MAINCK_BYPASS); - osc_wait_ready(OSC_MAINCK_BYPASS); - } - break; - -#ifdef CONFIG_PLL0_SOURCE - case GENCLK_PCK_SRC_PLLACK: - pll_enable_config_defaults(0); - break; -#endif - -#if SAMG55 -#ifdef CONFIG_PLL1_SOURCE - case GENCLK_PCK_SRC_PLLBCK: - pll_enable_config_defaults(1); - break; -#endif -#endif - - case GENCLK_PCK_SRC_MCK: - break; - - default: - Assert(false); - break; - } -} - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CHIP_GENCLK_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/osc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/osc.h deleted file mode 100644 index c196c685581..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/osc.h +++ /dev/null @@ -1,226 +0,0 @@ -/** - * \file - * - * \brief Chip-specific oscillator management functions. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CHIP_OSC_H_INCLUDED -#define CHIP_OSC_H_INCLUDED - -#include "board.h" -#include "pmc.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \weakgroup osc_group - * @{ - */ - -//! \name Oscillator identifiers -//@{ -#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator. -#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator. -#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator. -#define OSC_MAINCK_8M_RC 3 //!< Internal 8MHz RC oscillator. -#define OSC_MAINCK_16M_RC 4 //!< Internal 16MHz RC oscillator. -#define OSC_MAINCK_24M_RC 5 //!< Internal 24MHz RC oscillator. -#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator. -#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator. -//@} - -//! \name Oscillator clock speed in hertz -//@{ -#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator. -#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator. -#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator. -#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator. -#define OSC_MAINCK_16M_RC_HZ CHIP_FREQ_MAINCK_RC_16MHZ //!< Internal 16MHz RC oscillator. -#define OSC_MAINCK_24M_RC_HZ CHIP_FREQ_MAINCK_RC_24MHZ //!< Internal 24MHz RC oscillator. -#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator. -#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator. -//@} - - static inline void osc_enable(uint32_t ul_id) -{ - switch (ul_id) { - case OSC_SLCK_32K_RC: - break; - - case OSC_SLCK_32K_XTAL: - pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); - break; - - case OSC_SLCK_32K_BYPASS: - pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS); - break; - - - case OSC_MAINCK_8M_RC: - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); - break; - - case OSC_MAINCK_16M_RC: - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_16_MHz); - break; - - case OSC_MAINCK_24M_RC: - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_24_MHz); - break; - - - case OSC_MAINCK_XTAL: - pmc_switch_mainck_to_xtal(PMC_OSC_XTAL, - pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, - OSC_SLCK_32K_RC_HZ)); - break; - - case OSC_MAINCK_BYPASS: - pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS, - pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, - OSC_SLCK_32K_RC_HZ)); - break; - } -} - -static inline void osc_disable(uint32_t ul_id) -{ - switch (ul_id) { - case OSC_SLCK_32K_RC: - case OSC_SLCK_32K_XTAL: - case OSC_SLCK_32K_BYPASS: - break; - - case OSC_MAINCK_8M_RC: - case OSC_MAINCK_16M_RC: - case OSC_MAINCK_24M_RC: - pmc_osc_disable_fastrc(); - break; - - case OSC_MAINCK_XTAL: - pmc_osc_disable_xtal(PMC_OSC_XTAL); - break; - - case OSC_MAINCK_BYPASS: - pmc_osc_disable_xtal(PMC_OSC_BYPASS); - break; - } -} - -static inline bool osc_is_ready(uint32_t ul_id) -{ - switch (ul_id) { - case OSC_SLCK_32K_RC: - return 1; - - case OSC_SLCK_32K_XTAL: - case OSC_SLCK_32K_BYPASS: - return pmc_osc_is_ready_32kxtal(); - - case OSC_MAINCK_8M_RC: - case OSC_MAINCK_16M_RC: - case OSC_MAINCK_24M_RC: - case OSC_MAINCK_XTAL: - case OSC_MAINCK_BYPASS: - return pmc_osc_is_ready_mainck(); - } - - return 0; -} - -static inline uint32_t osc_get_rate(uint32_t ul_id) -{ - switch (ul_id) { - case OSC_SLCK_32K_RC: - return OSC_SLCK_32K_RC_HZ; - -#ifdef BOARD_FREQ_SLCK_XTAL - case OSC_SLCK_32K_XTAL: - return BOARD_FREQ_SLCK_XTAL; -#endif - -#ifdef BOARD_FREQ_SLCK_BYPASS - case OSC_SLCK_32K_BYPASS: - return BOARD_FREQ_SLCK_BYPASS; -#endif - - case OSC_MAINCK_8M_RC: - return OSC_MAINCK_8M_RC_HZ; - - case OSC_MAINCK_16M_RC: - return OSC_MAINCK_16M_RC_HZ; - - case OSC_MAINCK_24M_RC: - return OSC_MAINCK_24M_RC_HZ; - -#ifdef BOARD_FREQ_MAINCK_XTAL - case OSC_MAINCK_XTAL: - return BOARD_FREQ_MAINCK_XTAL; -#endif - -#ifdef BOARD_FREQ_MAINCK_BYPASS - case OSC_MAINCK_BYPASS: - return BOARD_FREQ_MAINCK_BYPASS; -#endif - } - - return 0; -} - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CHIP_OSC_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/pll.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/pll.h deleted file mode 100644 index 7eaaa397886..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/pll.h +++ /dev/null @@ -1,266 +0,0 @@ -/** - * \file - * - * \brief Chip-specific PLL definitions. - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CHIP_PLL_H_INCLUDED -#define CHIP_PLL_H_INCLUDED - -#include - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \weakgroup pll_group - * @{ - */ - -#define PLL_OUTPUT_MIN_HZ 24000000 -#if (SAMG51 || SAMG53) -#define PLL_OUTPUT_MAX_HZ 48000000 -#endif -#if (SAMG54) -#define PLL_OUTPUT_MAX_HZ 96000000 -#endif -#if (SAMG55) -#define PLL_OUTPUT_MAX_HZ 120000000 -#endif - -#define PLL_INPUT_HZ 32768 - -#define NR_PLLS 2 -#define PLLA_ID 0 -#define PLLB_ID 1 - -#define PLL_COUNT 0x3fU - -enum pll_source { - PLL_SRC_SLCK_RC = OSC_SLCK_32K_RC, //!< Internal 32KHz RC oscillator. - PLL_SRC_SLCK_XTAL = OSC_SLCK_32K_XTAL, //!< External 32kHz crystal oscillator. - PLL_NR_SOURCES, //!< Number of PLL sources. -}; - -struct pll_config { - uint32_t ctrl; -}; - -#define pll_get_default_rate(pll_id) \ - ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \ - * CONFIG_PLL##pll_id##_MUL) \ - / CONFIG_PLL##pll_id##_DIV) - -/** - * \note The SAMG PLL hardware interprets mul as mul+1. For readability the hardware mul+1 - * is hidden in this implementation. Use mul as mul effective value. - */ -static inline void pll_config_init(struct pll_config *p_cfg, - enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul) -{ - uint32_t vco_hz; - - Assert(e_src < PLL_NR_SOURCES); - Assert(ul_div < 2); - - /* Calculate internal VCO frequency */ - vco_hz = osc_get_rate(e_src) / ul_div; - - vco_hz *= ul_mul; - Assert(vco_hz >= (PLL_OUTPUT_MIN_HZ - (PLL_OUTPUT_MIN_HZ >> 6))); - Assert(vco_hz <= (PLL_OUTPUT_MAX_HZ + (PLL_OUTPUT_MAX_HZ >> 6))); - - /* PMC hardware will automatically make it mul+1 */ - p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_PLLAEN(ul_div) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT); -} - -#define pll_config_defaults(cfg, pll_id) \ - pll_config_init(cfg, \ - CONFIG_PLL##pll_id##_SOURCE, \ - CONFIG_PLL##pll_id##_DIV, \ - CONFIG_PLL##pll_id##_MUL) - -static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - p_cfg->ctrl = PMC->CKGR_PLLAR; -#if SAMG55 - } else { - p_cfg->ctrl = PMC->CKGR_PLLBR; -#endif - } -} - -static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - pmc_disable_pllack(); // Always stop PLL first! - PMC->CKGR_PLLAR = p_cfg->ctrl; -#if SAMG55 - } else { - pmc_disable_pllbck(); // Always stop PLL first! - PMC->CKGR_PLLBR = p_cfg->ctrl; -#endif - } -} - -static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - pmc_disable_pllack(); // Always stop PLL first! - PMC->CKGR_PLLAR = p_cfg->ctrl; -#if SAMG55 - } else { - pmc_disable_pllbck(); // Always stop PLL first! - PMC->CKGR_PLLBR = p_cfg->ctrl; -#endif - } -} - -/** - * \note This will only disable the selected PLL, not the underlying oscillator (mainck). - */ -static inline void pll_disable(uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - pmc_disable_pllack(); -#if SAMG55 - } else { - pmc_disable_pllbck(); -#endif - } -} - -static inline uint32_t pll_is_locked(uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - return pmc_is_locked_pllack(); -#if SAMG55 - } else if (ul_pll_id == PLLB_ID) { - return pmc_is_locked_pllbck(); -#endif - } else { - return 0; - } -} - -static inline void pll_enable_source(enum pll_source e_src) -{ - switch (e_src) { - case PLL_SRC_SLCK_RC: - case PLL_SRC_SLCK_XTAL: - osc_enable(e_src); - osc_wait_ready(e_src); - break; - - default: - Assert(false); - break; - } -} - -static inline void pll_enable_config_defaults(unsigned int ul_pll_id) -{ - struct pll_config pllcfg; - - if (pll_is_locked(ul_pll_id)) { - return; // Pll already running - } - - switch (ul_pll_id) { -#ifdef CONFIG_PLL0_SOURCE - case 0: - pll_enable_source(CONFIG_PLL0_SOURCE); - pll_config_init(&pllcfg, - CONFIG_PLL0_SOURCE, - CONFIG_PLL0_DIV, - CONFIG_PLL0_MUL); - break; -#endif - -#if SAMG55 -#ifdef CONFIG_PLL1_SOURCE - case 1: - pll_enable_source(CONFIG_PLL1_SOURCE); - pll_config_init(&pllcfg, - CONFIG_PLL1_SOURCE, - CONFIG_PLL1_DIV, - CONFIG_PLL1_MUL); - break; -#endif -#endif - - default: - Assert(false); - break; - } - pll_enable(&pllcfg, ul_pll_id); - while (!pll_is_locked(ul_pll_id)); -} - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CHIP_PLL_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/sysclk.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/sysclk.c deleted file mode 100644 index b831d8f805d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/sysclk.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - * \file - * - * \brief Chip-specific system clock management functions. - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \weakgroup sysclk_group - * @{ - */ - -#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) - /** - * \brief boolean signalling that the sysclk_init is done. - */ - uint32_t sysclk_initialized = 0; -#endif - - /** - * \brief Set system clock prescaler configuration - * - * This function will change the system clock prescaler configuration to - * match the parameters. - * - * \note The parameters to this function are device-specific. - * - * \param cpu_shift The CPU clock will be divided by \f$2^{mck\_pres}\f$ - */ - void sysclk_set_prescalers(uint32_t ul_pres) -{ - pmc_mck_set_prescaler(ul_pres); - SystemCoreClockUpdate(); -} - -/** - * \brief Change the source of the main system clock. - * - * \param src The new system clock source. Must be one of the constants - * from the System Clock Sources section. - */ -void sysclk_set_source(uint32_t ul_src) -{ - switch (ul_src) { - case SYSCLK_SRC_SLCK_RC: - case SYSCLK_SRC_SLCK_XTAL: - case SYSCLK_SRC_SLCK_BYPASS: - pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK); - break; - - case SYSCLK_SRC_MAINCK_8M_RC: - case SYSCLK_SRC_MAINCK_16M_RC: - case SYSCLK_SRC_MAINCK_24M_RC: - case SYSCLK_SRC_MAINCK_XTAL: - case SYSCLK_SRC_MAINCK_BYPASS: - pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK); - break; - - case SYSCLK_SRC_PLLACK: - pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK); - break; - -#if SAMG55 - case SYSCLK_SRC_PLLBCK: - pmc_mck_set_source(PMC_MCKR_CSS_PLLB_CLK); - break; -#endif - } - SystemCoreClockUpdate(); -} - -#if SAMG55 -#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__) -/** - * \brief Enable USB clock. - * - * - * \param pll_id Source of the USB clock. - * \param div Actual clock divisor. Must be superior to 0. - */ -void sysclk_enable_usb(void) -{ - Assert(CONFIG_USBCLK_DIV > 0); - -#ifdef CONFIG_PLL0_SOURCE - if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) { - struct pll_config pllcfg; - - pll_enable_source(CONFIG_PLL0_SOURCE); - pll_config_defaults(&pllcfg, 0); - pll_enable(&pllcfg, 0); - pll_wait_for_lock(0); -#ifdef UHD_ENABLE - pmc_switch_uhpck_to_pllack(CONFIG_USBCLK_DIV - 1); - pmc_enable_uhpck(); -#else - pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1); - pmc_enable_udpck(); -#endif - return; - } -#endif - -#ifdef CONFIG_PLL1_SOURCE - if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL1) { - struct pll_config pllcfg; - - pll_enable_source(CONFIG_PLL1_SOURCE); - pll_config_defaults(&pllcfg, 1); - pll_enable(&pllcfg, 1); - pll_wait_for_lock(1); -#ifdef UHD_ENABLE - pmc_switch_uhpck_to_pllbck(CONFIG_USBCLK_DIV - 1); - pmc_enable_uhpck(); -#else - pmc_switch_udpck_to_pllbck(CONFIG_USBCLK_DIV - 1); - pmc_enable_udpck(); -#endif - return; - } -#endif -} - -/** - * \brief Disable the USB clock. - * - * \note This implementation does not switch off the PLL, it just turns off the USB clock. - */ -void sysclk_disable_usb(void) -{ - pmc_disable_udpck(); -} -#endif // CONFIG_USBCLK_SOURCE -#endif - -void sysclk_init(void) -{ -#if SAMG54 - uint32_t unique_id[32]; - uint32_t trim_value; -#endif - - /* Set flash wait state to max in case the below clock switching. */ - system_init_flash(CHIP_FREQ_CPU_MAX); - - /* Config system clock setting */ - if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { - osc_enable(OSC_SLCK_32K_RC); - osc_wait_ready(OSC_SLCK_32K_RC); - pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { - osc_enable(OSC_SLCK_32K_XTAL); - osc_wait_ready(OSC_SLCK_32K_XTAL); - pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { - osc_enable(OSC_SLCK_32K_BYPASS); - osc_wait_ready(OSC_SLCK_32K_BYPASS); - pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { - /* Already running from SYSCLK_SRC_MAINCK_8M_RC */ - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_16M_RC) { - osc_enable(OSC_MAINCK_16M_RC); - osc_wait_ready(OSC_MAINCK_16M_RC); - pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_24M_RC) { - osc_enable(OSC_MAINCK_24M_RC); - osc_wait_ready(OSC_MAINCK_24M_RC); - pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { - osc_enable(OSC_MAINCK_XTAL); - osc_wait_ready(OSC_MAINCK_XTAL); - pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { - osc_enable(OSC_MAINCK_BYPASS); - osc_wait_ready(OSC_MAINCK_BYPASS); - pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); - } - -#ifdef CONFIG_PLL0_SOURCE - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { - struct pll_config pllcfg; - - pll_enable_source(CONFIG_PLL0_SOURCE); - pll_config_defaults(&pllcfg, 0); - pll_enable(&pllcfg, 0); - pll_wait_for_lock(0); - pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); - } -#endif - -#if SAMG55 -#ifdef CONFIG_PLL1_SOURCE - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLBCK) { - struct pll_config pllcfg; - - pll_enable_source(CONFIG_PLL1_SOURCE); - pll_config_defaults(&pllcfg, 1); - pll_enable(&pllcfg, 1); - pll_wait_for_lock(1); - pmc_switch_mck_to_pllbck(CONFIG_SYSCLK_PRES); - } -#endif -#endif - - /* Update the SystemFrequency variable */ - SystemCoreClockUpdate(); - - /* Set a flash wait state depending on the new cpu frequency */ - system_init_flash(sysclk_get_cpu_hz()); - -#if SAMG54 - /* Set the trim value when system run near 96M */ - if ((SystemCoreClock <= (CHIP_FREQ_CPU_MAX + (CHIP_FREQ_CPU_MAX >> 3))) && - (SystemCoreClock >= (CHIP_FREQ_CPU_MAX - (CHIP_FREQ_CPU_MAX >> 3)))) { - /* Get the trim value from unique ID area */ - efc_perform_read_sequence(EFC, EFC_FCMD_STUI, EFC_FCMD_SPUI, - unique_id, 32); -#ifdef BOARD_VDDIO_18 - trim_value = unique_id[0x10] & 0x000000FF; - supc_set_regulator_trim_user(SUPC, trim_value); -#else - trim_value = unique_id[0x14] & 0x000000FF; - supc_set_regulator_trim_user(SUPC, trim_value); -#endif - } -#endif - -#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) - /* Signal that the internal frequencies are setup */ - sysclk_initialized = 1; -#endif -} - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/sysclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/sysclk.h deleted file mode 100644 index c9a6e4cc736..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/sysclk.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - * \file - * - * \brief Chip-specific system clock management functions. - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CHIP_SYSCLK_H_INCLUDED -#define CHIP_SYSCLK_H_INCLUDED - -#include -#include - -/** - * \page sysclk_quickstart Quick Start Guide for the System Clock Management service (SAMG51) - * - * This is the quick start guide for the \ref sysclk_group "System Clock Management" - * service, with step-by-step instructions on how to configure and use the service for - * specific use cases. - * - * \section sysclk_quickstart_usecases System Clock Management use cases - * - \ref sysclk_quickstart_basic - * - * \section sysclk_quickstart_basic Basic usage of the System Clock Management service - * This section will present a basic use case for the System Clock Management service. - * This use case will configure the main system clock to 100Hz, using an internal PLL - * module to multiply the frequency of a crystal attached to the microcontroller. - * - * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites - * - None - * - * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code - * Add to the application initialization code: - * \code - sysclk_init(); -\endcode - * - * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow - * -# Configure the system clocks according to the settings in conf_clock.h: - * \code sysclk_init(); \endcode - * - * \subsection sysclk_quickstart_use_case_1_example_code Example code - * Add or uncomment the following in your conf_clock.h header file, commenting out all other - * definitions of the same symbol(s): - * \code - #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK - - // Fpll0 = (Fclk * PLL_mul) / PLL_div - #define CONFIG_PLL0_SOURCE PLL_SRC_SCLK_RC - #define CONFIG_PLL0_MUL (1500) - #define CONFIG_PLL0_DIV 1 - - // Fbus = Fsys / BUS_div - #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 -\endcode - * - * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow - * -# Configure the main system clock to use the output of the PLL module as its source: - * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode - * -# Configure the PLL module to use the fast external fast crystal oscillator as its source: - * \code #define CONFIG_PLL0_SOURCE PLL_SRC_SCLK_RC \endcode - * -# Configure the PLL module to multiply the internal 32K RC frequency up to 48MHz: - * \code - #define CONFIG_PLL0_MUL (1500) - #define CONFIG_PLL0_DIV 1 -\endcode - * -# Configure the main clock to run at the full 48MHz, disable scaling of the main system clock speed: - * \code - #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 -\endcode - * \note Some dividers are powers of two, while others are integer division factors. Refer to the - * formulas in the conf_clock.h template commented above each division define. - */ - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - - /** - * \weakgroup sysclk_group - * @{ - */ - -//! \name Configuration Symbols -//@{ - /** - * \def CONFIG_SYSCLK_SOURCE - * \brief Initial/static main system clock source - * - * The main system clock will be configured to use this clock during - * initialization. - */ -#ifndef CONFIG_SYSCLK_SOURCE -# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC -#endif - /** - * \def CONFIG_SYSCLK_PRES - * \brief Initial CPU clock divider (mck) - * - * The MCK will run at - * \f[ - * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz} - * \f] - * after initialization. - */ -#ifndef CONFIG_SYSCLK_PRES -# define CONFIG_SYSCLK_PRES 0 -#endif - -//@} - -//! \name Master Clock Sources (MCK) -//@{ -#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock -#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock -#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock -#define SYSCLK_SRC_MAINCK_8M_RC 3 //!< Internal 8MHz RC oscillator as master source clock -#define SYSCLK_SRC_MAINCK_16M_RC 4 //!< Internal 16MHz RC oscillator as master source clock -#define SYSCLK_SRC_MAINCK_24M_RC 5 //!< Internal 24MHz RC oscillator as master source clock -#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock -#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock -#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock -#if SAMG55 -#define SYSCLK_SRC_PLLBCK 9 //!< Use PLLBCK as master source clock -#endif -//@} - -//! \name Master Clock Prescalers (MCK) -//@{ -#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1 -#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2 -#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4 -#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8 -#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16 -#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32 -#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64 -#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3 -//@} - -#if SAMG55 -//! \name USB Clock Sources -//@{ -#define USBCLK_SRC_PLL0 0 //!< Use PLLA -#define USBCLK_SRC_PLL1 1 //!< Use PLLB -//@} - - /** - * \def CONFIG_USBCLK_SOURCE - * \brief Configuration symbol for the USB generic clock source - * - * Sets the clock source to use for the USB. The source must also be properly - * configured. - * - * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if - * USB is not required. - */ -#ifdef __DOXYGEN__ -# define CONFIG_USBCLK_SOURCE -#endif - - /** - * \def CONFIG_USBCLK_DIV - * \brief Configuration symbol for the USB generic clock divider setting - * - * Sets the clock division for the USB generic clock. If a USB clock source is - * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be - * defined. - */ -#ifdef __DOXYGEN__ -# define CONFIG_USBCLK_DIV -#endif -#endif - - /** - * \name Querying the system clock - * - * The following functions may be used to query the current frequency of - * the system clock and the CPU and bus clocks derived from it. - * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be - * available on all platforms, although some platforms may define - * additional accessors for various chip-internal bus clocks. These are - * usually not intended to be queried directly by generic code. - */ -//@{ - - /** - * \brief Return the current rate in Hz of the main system clock - * - * \todo This function assumes that the main clock source never changes - * once it's been set up, and that PLL0 always runs at the compile-time - * configured default rate. While this is probably the most common - * configuration, which we want to support as a special case for - * performance reasons, we will at some point need to support more - * dynamic setups as well. - */ -#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) - extern uint32_t sysclk_initialized; -#endif - static inline uint32_t sysclk_get_main_hz(void) -{ -#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) - if (!sysclk_initialized ) { - return OSC_MAINCK_8M_RC_HZ; - } -#endif - - /* Config system clock setting */ - if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { - return OSC_SLCK_32K_RC_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { - return OSC_SLCK_32K_XTAL_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { - return OSC_SLCK_32K_BYPASS_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { - return OSC_MAINCK_8M_RC_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_16M_RC) { - return OSC_MAINCK_16M_RC_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_24M_RC) { - return OSC_MAINCK_24M_RC_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { - return OSC_MAINCK_XTAL_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { - return OSC_MAINCK_BYPASS_HZ; - } -#ifdef CONFIG_PLL0_SOURCE - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { - return pll_get_default_rate(0); - } -#endif - -#if SAMG55 -#ifdef CONFIG_PLL1_SOURCE - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLBCK) { - return pll_get_default_rate(1); - } -#endif -#endif - - else { - /* unhandled_case(CONFIG_SYSCLK_SOURCE); */ - return 0; - } -} - -/** - * \brief Return the current rate in Hz of the CPU clock - * - * \todo This function assumes that the CPU always runs at the system - * clock frequency. We want to support at least two more scenarios: - * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus - * clock dividers (which may change at run time). Ditto for all the bus - * clocks. - * - * \return Frequency of the CPU clock, in Hz. - */ -static inline uint32_t sysclk_get_cpu_hz(void) -{ - /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ - /* prescaler, not an immediate value. */ - return sysclk_get_main_hz() / - ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : - (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))); -} - -/** - * \brief Retrieves the current rate in Hz of the peripheral clocks. - * - * \return Frequency of the peripheral clocks, in Hz. - */ -static inline uint32_t sysclk_get_peripheral_hz(void) -{ - /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ - /* prescaler, not an immediate value. */ - return sysclk_get_main_hz() / - ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : - (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))); -} - -/** - * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached - * to the specified peripheral. - * - * \param module Pointer to the module's base address. - * - * \return Frequency of the bus attached to the specified peripheral, in Hz. - */ -static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module) -{ - UNUSED(module); - return sysclk_get_peripheral_hz(); -} -//@} - -//! \name Enabling and disabling synchronous clocks -//@{ - -/** - * \brief Enable a peripheral's clock. - * - * \param ul_id Id (number) of the peripheral clock. - */ -static inline void sysclk_enable_peripheral_clock(uint32_t ul_id) -{ - pmc_enable_periph_clk(ul_id); -} - -/** - * \brief Disable a peripheral's clock. - * - * \param ul_id Id (number) of the peripheral clock. - */ -static inline void sysclk_disable_peripheral_clock(uint32_t ul_id) -{ - pmc_disable_periph_clk(ul_id); -} - -//@} - -//! \name System Clock Source and Prescaler configuration -//@{ - -extern void sysclk_set_prescalers(uint32_t ul_pres); -extern void sysclk_set_source(uint32_t ul_src); - -//@} - -extern void sysclk_enable_usb(void); -extern void sysclk_disable_usb(void); - -extern void sysclk_init(void); - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CHIP_SYSCLK_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/sysclk.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/sysclk.h deleted file mode 100644 index 86e4bf7a247..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/sysclk.h +++ /dev/null @@ -1,194 +0,0 @@ -/** - * \file - * - * \brief System clock management - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSCLK_H_INCLUDED -#define SYSCLK_H_INCLUDED - -#include "parts.h" -#include "conf_clock.h" - -#if SAM3S -# include "sam3s/sysclk.h" -#elif SAM3U -# include "sam3u/sysclk.h" -#elif SAM3N -# include "sam3n/sysclk.h" -#elif SAM3XA -# include "sam3x/sysclk.h" -#elif SAM4S -# include "sam4s/sysclk.h" -#elif SAM4E -# include "sam4e/sysclk.h" -#elif SAM4C -# include "sam4c/sysclk.h" -#elif SAM4CM -# include "sam4cm/sysclk.h" -#elif SAM4CP -# include "sam4cp/sysclk.h" -#elif SAM4L -# include "sam4l/sysclk.h" -#elif SAM4N -# include "sam4n/sysclk.h" -#elif SAMG -# include "samg/sysclk.h" -#elif SAMV71 -# include "samv71/sysclk.h" -#elif SAMV70 -# include "samv70/sysclk.h" -#elif SAME70 -# include "same70/sysclk.h" -#elif SAMS70 -# include "sams70/sysclk.h" -#elif (UC3A0 || UC3A1) -# include "uc3a0_a1/sysclk.h" -#elif UC3A3 -# include "uc3a3_a4/sysclk.h" -#elif UC3B -# include "uc3b0_b1/sysclk.h" -#elif UC3C -# include "uc3c/sysclk.h" -#elif UC3D -# include "uc3d/sysclk.h" -#elif UC3L -# include "uc3l/sysclk.h" -#elif XMEGA -# include "xmega/sysclk.h" -#elif MEGA -# include "mega/sysclk.h" -#else -# error Unsupported chip type -#endif - -/** - * \defgroup clk_group Clock Management - */ - -/** - * \ingroup clk_group - * \defgroup sysclk_group System Clock Management - * - * See \ref sysclk_quickstart. - * - * The sysclk API covers the system clock and all - * clocks derived from it. The system clock is a chip-internal clock on - * which all synchronous clocks, i.e. CPU and bus/peripheral - * clocks, are based. The system clock is typically generated from one - * of a variety of sources, which may include crystal and RC oscillators - * as well as PLLs. The clocks derived from the system clock are - * sometimes also known as synchronous clocks, since they - * always run synchronously with respect to each other, as opposed to - * generic clocks which may run from different oscillators or - * PLLs. - * - * Most applications should simply call sysclk_init() to initialize - * everything related to the system clock and its source (oscillator, - * PLL or DFLL), and leave it at that. More advanced applications, and - * platform-specific drivers, may require additional services from the - * clock system, some of which may be platform-specific. - * - * \section sysclk_group_platform Platform Dependencies - * - * The sysclk API is partially chip- or platform-specific. While all - * platforms provide mostly the same functionality, there are some - * variations around how different bus types and clock tree structures - * are handled. - * - * The following functions are available on all platforms with the same - * parameters and functionality. These functions may be called freely by - * portable applications, drivers and services: - * - sysclk_init() - * - sysclk_set_source() - * - sysclk_get_main_hz() - * - sysclk_get_cpu_hz() - * - sysclk_get_peripheral_bus_hz() - * - * The following functions are available on all platforms, but there may - * be variations in the function signature (i.e. parameters) and - * behavior. These functions are typically called by platform-specific - * parts of drivers, and applications that aren't intended to be - * portable: - * - sysclk_enable_peripheral_clock() - * - sysclk_disable_peripheral_clock() - * - sysclk_enable_module() - * - sysclk_disable_module() - * - sysclk_module_is_enabled() - * - sysclk_set_prescalers() - * - * All other functions should be considered platform-specific. - * Enabling/disabling clocks to specific peripherals as well as - * determining the speed of these clocks should be done by calling - * functions provided by the driver for that peripheral. - * - * @{ - */ - -//! \name System Clock Initialization -//@{ -/** - * \fn void sysclk_init(void) - * \brief Initialize the synchronous clock system. - * - * This function will initialize the system clock and its source. This - * includes: - * - Mask all synchronous clocks except for any clocks which are - * essential for normal operation (for example internal memory - * clocks). - * - Set up the system clock prescalers as specified by the - * application's configuration file. - * - Enable the clock source specified by the application's - * configuration file (oscillator or PLL) and wait for it to become - * stable. - * - Set the main system clock source to the clock specified by the - * application's configuration file. - * - * Since all non-essential peripheral clocks are initially disabled, it - * is the responsibility of the peripheral driver to re-enable any - * clocks that are needed for normal operation. - */ -//@} - -//! @} - -#endif /* SYSCLK_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/delay.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/delay.h deleted file mode 100644 index c845e44bac7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/delay.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * \file - * - * \brief Common Delay Service - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _DELAY_H_ -#define _DELAY_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#if UC3 -# include -#elif XMEGA -# include "xmega/cycle_counter.h" -#elif MEGA -# include "mega/cycle_counter.h" -#elif SAM -# include "sam/cycle_counter.h" -#endif - -/** - * @defgroup group_common_services_delay Busy-Wait Delay Routines - * - * This module provides simple loop-based delay routines for those - * applications requiring a brief wait during execution. Common API - * for UC3, XMEGA, and AVR MEGA. - * - * @{ - */ - -/** - * @def F_CPU - * @brief MCU Clock Frequency (Hertz) - * - * @deprecated - * The \ref F_CPU configuration constant is used for compatibility with the - * \ref group_common_services_delay routines. The common loop-based delay - * routines are designed to use the \ref clk_group modules while anticipating - * support for legacy applications assuming a statically defined clock - * frequency. Applications using a statically configured MCU clock frequency - * can define \ref F_CPU (Hertz), in which case the common delay routines will - * use this value rather than calling sysclk_get_cpu_hz() to get the current - * MCU clock frequency. - */ -#ifndef F_CPU -# define F_CPU sysclk_get_cpu_hz() -#endif - -/** - * @def delay_init - * - * @brief Initialize the delay driver. - * @param fcpu_hz CPU frequency in Hz - * - * @deprecated - * This function is provided for compatibility with ASF applications that - * may not have been updated to configure the system clock via the common - * clock service; e.g. sysclk_init() and a configuration header file are - * used to configure clocks. - * - * The functions in this module call \ref sysclk_get_cpu_hz() function to - * obtain the system clock frequency. - */ -#define delay_init(fcpu_hz) - -/** - * @def delay_s - * @brief Delay in seconds. - * @param delay Delay in seconds - */ -#define delay_s(delay) cpu_delay_ms(1000 * delay, F_CPU) - -/** - * @def delay_ms - * @brief Delay in milliseconds. - * @param delay Delay in milliseconds - */ -#define delay_ms(delay) cpu_delay_ms(delay, F_CPU) - -/** - * @def delay_us - * @brief Delay in microseconds. - * @param delay Delay in microseconds - */ -#define delay_us(delay) cpu_delay_us(delay, F_CPU) - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _DELAY_H_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/sam/cycle_counter.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/sam/cycle_counter.c deleted file mode 100644 index fde183b4ea5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/sam/cycle_counter.c +++ /dev/null @@ -1,61 +0,0 @@ -/** - * \file - * - * \brief ARM functions for busy-wait delay loops - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "cycle_counter.h" - -// Delay loop is put to SRAM so that FWS will not affect delay time -OPTIMIZE_HIGH -RAMFUNC -void portable_delay_cycles(unsigned long n) -{ - UNUSED(n); - - __asm ( - "loop: DMB \n" - "SUBS R0, R0, #1 \n" - "BNE.N loop " - ); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/sam/cycle_counter.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/sam/cycle_counter.h deleted file mode 100644 index 4ac1c6b5833..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/sam/cycle_counter.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief ARM functions for busy-wait delay loops - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _cycle_counter_h_ -#define _cycle_counter_h_ - -#ifdef __cplusplus -extern "C" { -#endif - - -#include - -/** - * @name Convenience functions for busy-wait delay loops - * - * @def delay_cycles - * @brief Delay program execution for a specified number of CPU cycles. - * @param n number of CPU cycles to wait - * - * @def cpu_delay_ms - * @brief Delay program execution for a specified number of milliseconds. - * @param delay number of milliseconds to wait - * @param f_cpu CPU frequency in Hertz - * - * @def cpu_delay_us - * @brief Delay program execution for a specified number of microseconds. - * @param delay number of microseconds to wait - * @param f_cpu CPU frequency in Hertz - * - * @def cpu_ms_2_cy - * @brief Convert milli-seconds into CPU cycles. - * @param ms number of milliseconds - * @param f_cpu CPU frequency in Hertz - * @return the converted number of CPU cycles - * - * @def cpu_us_2_cy - * @brief Convert micro-seconds into CPU cycles. - * @param ms number of microseconds - * @param f_cpu CPU frequency in Hertz - * @return the converted number of CPU cycles - * - * @{ - */ - -/** - * \brief Delay loop to delay n number of cycles - * - * \note The function runs in internal RAM so that flash wait states - * will not affect the delay time. - * - * \param n Number of cycles - */ -void portable_delay_cycles(unsigned long n); - -/* Cortex-M7 is faster than Cortex-M3/M4/M0+ */ -#ifdef __CM7_REV - -# define cpu_ms_2_cy(ms, f_cpu) \ - (((uint64_t)(ms) * (f_cpu) + (uint64_t)(5.932e3 - 1ul)) / (uint64_t)5.932e3) -# define cpu_us_2_cy(us, f_cpu) \ - (((uint64_t)(us) * (f_cpu) + (uint64_t)(5.932e6 - 1ul)) / (uint64_t)5.932e6) - -#else - -# define cpu_ms_2_cy(ms, f_cpu) \ - (((uint64_t)(ms) * (f_cpu) + (uint64_t)(14e3 - 1ul)) / (uint64_t)14e3) -# define cpu_us_2_cy(us, f_cpu) \ - (((uint64_t)(us) * (f_cpu) + (uint64_t)(14e6 - 1ul)) / (uint64_t)14e6) - -#endif - -#define delay_cycles portable_delay_cycles - -#define cpu_delay_ms(delay, f_cpu) delay_cycles(cpu_ms_2_cy(delay, f_cpu)) -#define cpu_delay_us(delay, f_cpu) delay_cycles(cpu_us_2_cy(delay, f_cpu)) -//! @} - - -#ifdef __cplusplus -} -#endif - -#endif /* _cycle_counter_h_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/gpio/gpio.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/gpio/gpio.h deleted file mode 100644 index e062690d8d7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/gpio/gpio.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * \file - * - * \brief Common GPIO API. - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _GPIO_H_ -#define _GPIO_H_ - -#include - -#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) -# include "sam_gpio/sam_gpio.h" -#elif XMEGA -# include "xmega_gpio/xmega_gpio.h" -#elif MEGA || MEGA_RF -# include "mega_gpio/mega_gpio.h" -#else -# error Unsupported chip type -#endif - -/** - * \defgroup gpio_group General Purpose Input/Output - * - * This is the common API for GPIO. Additional features are available - * in the documentation of the specific modules. - * - * \section io_group_platform Platform Dependencies - * - * The following functions are available on all platforms, but there may - * be variations in the function signature (i.e. parameters) and - * behaviour. These functions are typically called by platform-specific - * parts of drivers, and applications that aren't intended to be - * portable: - * - gpio_pin_is_low() - * - gpio_pin_is_high() - * - gpio_set_pin_high() - * - gpio_set_pin_group_high() - * - gpio_set_pin_low() - * - gpio_set_pin_group_low() - * - gpio_toggle_pin() - * - gpio_toggle_pin_group() - * - gpio_configure_pin() - * - gpio_configure_group() - */ - -#endif /* _GPIO_H_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/gpio/sam_gpio/sam_gpio.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/gpio/sam_gpio/sam_gpio.h deleted file mode 100644 index cb5e974f635..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/gpio/sam_gpio/sam_gpio.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * \brief GPIO service for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SAM_GPIO_H_INCLUDED -#define SAM_GPIO_H_INCLUDED - -#include "compiler.h" -#include "pio.h" - -#define gpio_pin_is_low(io_id) \ - (pio_get_pin_value(io_id) ? 0 : 1) - -#define gpio_pin_is_high(io_id) \ - (pio_get_pin_value(io_id) ? 1 : 0) - -#define gpio_set_pin_high(io_id) \ - pio_set_pin_high(io_id) - -#define gpio_set_pin_low(io_id) \ - pio_set_pin_low(io_id) - -#define gpio_toggle_pin(io_id) \ - pio_toggle_pin(io_id) - -#define gpio_configure_pin(io_id,io_flags) \ - pio_configure_pin(io_id,io_flags) - -#define gpio_configure_group(port_id,port_mask,io_flags) \ - pio_configure_pin_group(port_id,port_mask,io_flags) - -#define gpio_set_pin_group_high(port_id,mask) \ - pio_set_pin_group_high(port_id,mask) - -#define gpio_set_pin_group_low(port_id,mask) \ - pio_set_pin_group_low(port_id,mask) - -#define gpio_toggle_pin_group(port_id,mask) \ - pio_toggle_pin_group(port_id,mask) - -#endif /* SAM_GPIO_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/ioport.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/ioport.h deleted file mode 100644 index 5a24ce74401..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/ioport.h +++ /dev/null @@ -1,541 +0,0 @@ -/** - * \file - * - * \brief Common IOPORT service main header file for AVR, UC3 and ARM - * architectures. - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef IOPORT_H -#define IOPORT_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * \defgroup ioport_group Common IOPORT API - * - * See \ref ioport_quickstart. - * - * This is common IOPORT service for GPIO pin configuration and control in a - * standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices. - * - * Port pin control code is optimized for each platform, and should produce - * both compact and fast execution times when used with constant values. - * - * \section dependencies Dependencies - * This driver depends on the following modules: - * - \ref sysclk_group for clock speed and functions. - * @{ - */ - -/** - * \def IOPORT_CREATE_PIN(port, pin) - * \brief Create IOPORT pin number - * - * Create a IOPORT pin number for use with the IOPORT functions. - * - * \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen - * architecture) - * \param pin IOPORT zero-based index of the I/O pin - */ - -/** \brief IOPORT pin directions */ -enum ioport_direction { - IOPORT_DIR_INPUT, /*!< IOPORT input direction */ - IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */ -}; - -/** \brief IOPORT levels */ -enum ioport_value { - IOPORT_PIN_LEVEL_LOW, /*!< IOPORT pin value low */ - IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */ -}; - -#if MEGA_RF -/** \brief IOPORT edge sense modes */ -enum ioport_sense { - IOPORT_SENSE_LEVEL, /*!< IOPORT sense low level */ - IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ - IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ - IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ -}; -#elif SAM && !SAM4L -/** \brief IOPORT edge sense modes */ -enum ioport_sense { - IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ - IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ - IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ - IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */ - IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level */ -}; -#else -enum ioport_sense { - IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ - IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ - IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ -}; -#endif - - -#if XMEGA -# include "xmega/ioport.h" -# if defined(IOPORT_XMEGA_COMPAT) -# include "xmega/ioport_compat.h" -# endif -#elif MEGA -# include "mega/ioport.h" -#elif UC3 -# include "uc3/ioport.h" -#elif SAM -# if SAM4L -# include "sam/ioport_gpio.h" -# elif (SAMD20 | SAMD21) -# include "sam0/ioport.h" -# else -# include "sam/ioport_pio.h" -# endif -#endif - -/** - * \brief Initializes the IOPORT service, ready for use. - * - * This function must be called before using any other functions in the IOPORT - * service. - */ -static inline void ioport_init(void) -{ - arch_ioport_init(); -} - -/** - * \brief Enable an IOPORT pin, based on a pin created with \ref - * IOPORT_CREATE_PIN(). - * - * \param pin IOPORT pin to enable - */ -static inline void ioport_enable_pin(ioport_pin_t pin) -{ - arch_ioport_enable_pin(pin); -} - -/** - * \brief Enable multiple pins in a single IOPORT port. - * - * \param port IOPORT port to enable - * \param mask Mask of pins within the port to enable - */ -static inline void ioport_enable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_enable_port(port, mask); -} - -/** - * \brief Disable IOPORT pin, based on a pin created with \ref - * IOPORT_CREATE_PIN(). - * - * \param pin IOPORT pin to disable - */ -static inline void ioport_disable_pin(ioport_pin_t pin) -{ - arch_ioport_disable_pin(pin); -} - -/** - * \brief Disable multiple pins in a single IOPORT port. - * - * \param port IOPORT port to disable - * \param mask Pin mask of pins to disable - */ -static inline void ioport_disable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_disable_port(port, mask); -} - -/** - * \brief Set multiple pin modes in a single IOPORT port, such as pull-up, - * pull-down, etc. configuration. - * - * \param port IOPORT port to configure - * \param mask Pin mask of pins to configure - * \param mode Mode masks to configure for the specified pins (\ref - * ioport_modes) - */ -static inline void ioport_set_port_mode(ioport_port_t port, - ioport_port_mask_t mask, ioport_mode_t mode) -{ - arch_ioport_set_port_mode(port, mask, mode); -} - -/** - * \brief Set pin mode for one single IOPORT pin. - * - * \param pin IOPORT pin to configure - * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) - */ -static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode) -{ - arch_ioport_set_pin_mode(pin, mode); -} - -/** - * \brief Reset multiple pin modes in a specified IOPORT port to defaults. - * - * \param port IOPORT port to configure - * \param mask Mask of pins whose mode configuration is to be reset - */ -static inline void ioport_reset_port_mode(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_set_port_mode(port, mask, 0); -} - -/** - * \brief Reset pin mode configuration for a single IOPORT pin - * - * \param pin IOPORT pin to configure - */ -static inline void ioport_reset_pin_mode(ioport_pin_t pin) -{ - arch_ioport_set_pin_mode(pin, 0); -} - -/** - * \brief Set I/O direction for a group of pins in a single IOPORT. - * - * \param port IOPORT port to configure - * \param mask Pin mask of pins to configure - * \param dir Direction to set for the specified pins (\ref ioport_direction) - */ -static inline void ioport_set_port_dir(ioport_port_t port, - ioport_port_mask_t mask, enum ioport_direction dir) -{ - arch_ioport_set_port_dir(port, mask, dir); -} - -/** - * \brief Set direction for a single IOPORT pin. - * - * \param pin IOPORT pin to configure - * \param dir Direction to set for the specified pin (\ref ioport_direction) - */ -static inline void ioport_set_pin_dir(ioport_pin_t pin, - enum ioport_direction dir) -{ - arch_ioport_set_pin_dir(pin, dir); -} - -/** - * \brief Set an IOPORT pin to a specified logical value. - * - * \param pin IOPORT pin to configure - * \param level Logical value of the pin - */ -static inline void ioport_set_pin_level(ioport_pin_t pin, bool level) -{ - arch_ioport_set_pin_level(pin, level); -} - -/** - * \brief Set a group of IOPORT pins in a single port to a specified logical - * value. - * - * \param port IOPORT port to write to - * \param mask Pin mask of pins to modify - * \param level Level of the pins to be modified - */ -static inline void ioport_set_port_level(ioport_port_t port, - ioport_port_mask_t mask, ioport_port_mask_t level) -{ - arch_ioport_set_port_level(port, mask, level); -} - -/** - * \brief Get current value of an IOPORT pin, which has been configured as an - * input. - * - * \param pin IOPORT pin to read - * \return Current logical value of the specified pin - */ -static inline bool ioport_get_pin_level(ioport_pin_t pin) -{ - return arch_ioport_get_pin_level(pin); -} - -/** - * \brief Get current value of several IOPORT pins in a single port, which have - * been configured as an inputs. - * - * \param port IOPORT port to read - * \param mask Pin mask of pins to read - * \return Logical levels of the specified pins from the read port, returned as - * a mask. - */ -static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port, - ioport_port_mask_t mask) -{ - return arch_ioport_get_port_level(port, mask); -} - -/** - * \brief Toggle the value of an IOPORT pin, which has previously configured as - * an output. - * - * \param pin IOPORT pin to toggle - */ -static inline void ioport_toggle_pin_level(ioport_pin_t pin) -{ - arch_ioport_toggle_pin_level(pin); -} - -/** - * \brief Toggle the values of several IOPORT pins located in a single port. - * - * \param port IOPORT port to modify - * \param mask Pin mask of pins to toggle - */ -static inline void ioport_toggle_port_level(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_toggle_port_level(port, mask); -} - -/** - * \brief Set the pin sense mode of a single IOPORT pin. - * - * \param pin IOPORT pin to configure - * \param pin_sense Edge to sense for the pin (\ref ioport_sense) - */ -static inline void ioport_set_pin_sense_mode(ioport_pin_t pin, - enum ioport_sense pin_sense) -{ - arch_ioport_set_pin_sense_mode(pin, pin_sense); -} - -/** - * \brief Set the pin sense mode of a multiple IOPORT pins on a single port. - * - * \param port IOPORT port to configure - * \param mask Bitmask if pins whose edge sense is to be configured - * \param pin_sense Edge to sense for the pins (\ref ioport_sense) - */ -static inline void ioport_set_port_sense_mode(ioport_port_t port, - ioport_port_mask_t mask, - enum ioport_sense pin_sense) -{ - arch_ioport_set_port_sense_mode(port, mask, pin_sense); -} - -/** - * \brief Convert a pin ID into a its port ID. - * - * \param pin IOPORT pin ID to convert - * \retval Port ID for the given pin ID - */ -static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin) -{ - return arch_ioport_pin_to_port_id(pin); -} - -/** - * \brief Convert a pin ID into a bitmask mask for the given pin on its port. - * - * \param pin IOPORT pin ID to convert - * \retval Bitmask with a bit set that corresponds to the given pin ID in its port - */ -static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin) -{ - return arch_ioport_pin_to_mask(pin); -} - -/** @} */ - -/** - * \page ioport_quickstart Quick start guide for the common IOPORT service - * - * This is the quick start guide for the \ref ioport_group, with - * step-by-step instructions on how to configure and use the service in a - * selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section ioport_quickstart_basic Basic use case - * In this use case we will configure one IO pin for button input and one for - * LED control. Then it will read the button state and output it on the LED. - * - * \section ioport_quickstart_basic_setup Setup steps - * - * \subsection ioport_quickstart_basic_setup_code Example code - * \code - #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) - #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) - - ioport_init(); - - ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); - ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); - ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); -\endcode - * - * \subsection ioport_quickstart_basic_setup_flow Workflow - * -# It's useful to give the GPIOs symbolic names and this can be done with - * the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a - * button. - * - \code - #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) - #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) -\endcode - * - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names - * differ between architectures: - * - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions - * PORTA, PORTB ... - * - UC3: Most convenient to pick up the device header file pin definition - * and us it directly. E.g.: AVR32_PIN_PB06 - * - SAM: Most convenient to pick up the device header file pin definition - * and us it directly. E.g.: PIO_PA5_IDX
- * \ref IOPORT_CREATE_PIN can also be used with port definitions - * PIOA, PIOB ... - * -# Initialize the ioport service. This typically enables the IO module if - * needed. - * - \code ioport_init(); \endcode - * -# Set the LED GPIO as output: - * - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode - * -# Set the button GPIO as input: - * - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode - * -# Enable pull-up for the button GPIO: - * - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode - * - * \section ioport_quickstart_basic_usage Usage steps - * - * \subsection ioport_quickstart_basic_usage_code Example code - * \code - bool value; - - value = ioport_get_pin_level(MY_BUTTON); - ioport_set_pin_level(MY_LED, value); -\endcode - * - * \subsection ioport_quickstart_basic_usage_flow Workflow - * -# Define a boolean variable for state storage: - * - \code bool value; \endcode - * -# Read out the button level into variable value: - * - \code value = ioport_get_pin_level(MY_BUTTON); \endcode - * -# Set the LED to read out value from the button: - * - \code ioport_set_pin_level(MY_LED, value); \endcode - * - * \section ioport_quickstart_advanced Advanced use cases - * - \subpage ioport_quickstart_use_case_1 : Port access - */ - -/** - * \page ioport_quickstart_use_case_1 Advanced use case doing port access - * - * In this case we will read out the pins from one whole port and write the - * read value to another port. - * - * \section ioport_quickstart_use_case_1_setup Setup steps - * - * \subsection ioport_quickstart_use_case_1_setup_code Example code - * \code - #define IN_PORT IOPORT_PORTA - #define OUT_PORT IOPORT_PORTB - #define MASK 0x00000060 - - ioport_init(); - - ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); - ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); -\endcode - * - * \subsection ioport_quickstart_basic_setup_flow Workflow - * -# It's useful to give the ports symbolic names: - * - \code - #define IN_PORT IOPORT_PORTA - #define OUT_PORT IOPORT_PORTB -\endcode - * - \note The port names differ between architectures: - * - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA, - * IOPORT_PORTB ... - * - UC3: Use the index value of the different IO blocks: 0, 1 ... - * - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB - * ... - * -# Also useful to define a mask for the bits to work with: - * - \code #define MASK 0x00000060 \endcode - * -# Initialize the ioport service. This typically enables the IO module if - * needed. - * - \code ioport_init(); \endcode - * -# Set one of the ports as input: - * - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode - * -# Set the other port as output: - * - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode - * - * \section ioport_quickstart_basic_usage Usage steps - * - * \subsection ioport_quickstart_basic_usage_code Example code - * \code - ioport_port_mask_t value; - - value = ioport_get_port_level(IN_PORT, MASK); - ioport_set_port_level(OUT_PORT, MASK, value); -\endcode - * - * \subsection ioport_quickstart_basic_usage_flow Workflow - * -# Define a variable for port date storage: - * - \code ioport_port_mask_t value; \endcode - * -# Read out from one port: - * - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode - * -# Put the read data out on the other port: - * - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode - */ - -#ifdef __cplusplus -} -#endif - -#endif /* IOPORT_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_gpio.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_gpio.h deleted file mode 100644 index 0401459d37a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_gpio.h +++ /dev/null @@ -1,307 +0,0 @@ -/** - * \file - * - * \brief SAM architecture specific IOPORT service implementation header file. - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef IOPORT_SAM_H -#define IOPORT_SAM_H - -#include - -#define IOPORT_CREATE_PIN(port, pin) ((port) * 32 + (pin)) - -// Aliases -#define IOPORT_GPIOA 0 -#define IOPORT_GPIOB 1 -#define IOPORT_GPIOC 2 -#define IOPORT_GPIOD 3 -#define IOPORT_GPIOE 4 -#define IOPORT_GPIOF 5 - -/** - * \weakgroup ioport_group - * \section ioport_modes IOPORT Modes - * - * For details on these please see the device datasheet. - * - * @{ - */ - -/** \name IOPORT Mode bit definitions */ -/** @{ */ -#define IOPORT_MODE_MUX_MASK (7 << 0) /*!< MUX bits mask */ -#define IOPORT_MODE_MUX_BIT0 (1 << 0) /*!< MUX BIT0 mask */ -#define IOPORT_MODE_MUX_BIT1 (1 << 1) /*!< MUX BIT1 mask */ -#define IOPORT_MODE_MUX_A (0 << 0) /*!< MUX function A */ -#define IOPORT_MODE_MUX_B (1 << 0) /*!< MUX function B */ -#define IOPORT_MODE_MUX_C (2 << 0) /*!< MUX function C */ -#define IOPORT_MODE_MUX_D (3 << 0) /*!< MUX function D */ - -#define IOPORT_MODE_MUX_BIT2 (1 << 2) /*!< MUX BIT2 mask */ -#define IOPORT_MODE_MUX_E (4 << 0) /*!< MUX function E */ -#define IOPORT_MODE_MUX_F (5 << 0) /*!< MUX function F */ -#define IOPORT_MODE_MUX_G (6 << 0) /*!< MUX function G */ -#define IOPORT_MODE_MUX_H (7 << 0) /*!< MUX function H */ - -#define IOPORT_MODE_PULLUP (1 << 3) /*!< Pull-up */ -#define IOPORT_MODE_PULLDOWN (1 << 4) /*!< Pull-down */ -#define IOPORT_MODE_GLITCH_FILTER (1 << 6) /*!< Glitch filter */ -#define IOPORT_MODE_DRIVE_STRENGTH (1 << 7) /*!< Extra drive strength */ -/** @} */ - -/** @} */ - -typedef uint32_t ioport_mode_t; -typedef uint32_t ioport_pin_t; -typedef uint32_t ioport_port_t; -typedef uint32_t ioport_port_mask_t; - -__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin) -{ - return pin >> 5; -} - -__always_inline static volatile GpioPort *arch_ioport_port_to_base( - ioport_port_t port) -{ - return (volatile GpioPort *)(GPIO_ADDR - + port * sizeof(GpioPort)); -} - -__always_inline static volatile GpioPort *arch_ioport_pin_to_base(ioport_pin_t pin) -{ - return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin)); -} - -__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin) -{ - return 1U << (pin & 0x1F); -} - -__always_inline static void arch_ioport_init(void) -{ - sysclk_enable_peripheral_clock(GPIO); -} - -__always_inline static void arch_ioport_enable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->GPIO_GPERS = mask; -} - -__always_inline static void arch_ioport_disable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->GPIO_GPERC = mask; -} - -__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin) -{ - arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin)); -} - -__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin) -{ - arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin)); -} - -__always_inline static void arch_ioport_set_port_mode(ioport_port_t port, - ioport_port_mask_t mask, ioport_mode_t mode) -{ - volatile GpioPort *base = arch_ioport_port_to_base(port); - - if (mode & IOPORT_MODE_PULLUP) { - base->GPIO_PUERS = mask; - } else { - base->GPIO_PUERC = mask; - } - -#ifdef IOPORT_MODE_PULLDOWN - if (mode & IOPORT_MODE_PULLDOWN) { - base->GPIO_PDERS = mask; - } else { - base->GPIO_PDERC = mask; - } -#endif - - if (mode & IOPORT_MODE_GLITCH_FILTER) { - base->GPIO_GFERS = mask; - } else { - base->GPIO_GFERC = mask; - } - -#ifdef IOPORT_MODE_DRIVE_STRENGTH - if (mode & IOPORT_MODE_DRIVE_STRENGTH) { - base->GPIO_ODCR0S = mask; - } else { - base->GPIO_ODCR0C = mask; - } -#endif - - if (mode & IOPORT_MODE_MUX_BIT0) { - base->GPIO_PMR0S = mask; - } else { - base->GPIO_PMR0C = mask; - } - - if (mode & IOPORT_MODE_MUX_BIT1) { - base->GPIO_PMR1S = mask; - } else { - base->GPIO_PMR1C = mask; - } - -#ifdef IOPORT_MODE_MUX_BIT2 - if (mode & IOPORT_MODE_MUX_BIT2) { - base->GPIO_PMR2S = mask; - } else { - base->GPIO_PMR2C = mask; - } -#endif -} - -__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin, - ioport_mode_t mode) -{ - arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin), mode); -} - -__always_inline static void arch_ioport_set_port_dir(ioport_port_t port, - ioport_port_mask_t mask, unsigned char group_direction) -{ - if (group_direction == IOPORT_DIR_OUTPUT) { - arch_ioport_port_to_base(port)->GPIO_ODERS = mask; - // Always disable the Schmitt trigger for output pins. - arch_ioport_port_to_base(port)->GPIO_STERC = mask; - } else if (group_direction == IOPORT_DIR_INPUT) { - arch_ioport_port_to_base(port)->GPIO_ODERC = mask; - // Always enable the Schmitt trigger for input pins. - arch_ioport_port_to_base(port)->GPIO_STERS = mask; - } -} - -__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin, - enum ioport_direction dir) -{ - if (dir == IOPORT_DIR_OUTPUT) { - arch_ioport_pin_to_base(pin)->GPIO_ODERS = arch_ioport_pin_to_mask(pin); - // Always disable the Schmitt trigger for output pins. - arch_ioport_pin_to_base(pin)->GPIO_STERC = arch_ioport_pin_to_mask(pin); - } else if (dir == IOPORT_DIR_INPUT) { - arch_ioport_pin_to_base(pin)->GPIO_ODERC = arch_ioport_pin_to_mask(pin); - // Always enable the Schmitt trigger for input pins. - arch_ioport_pin_to_base(pin)->GPIO_STERS = arch_ioport_pin_to_mask(pin); - } -} - -__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin, - bool level) -{ - if (level) { - arch_ioport_pin_to_base(pin)->GPIO_OVRS = arch_ioport_pin_to_mask(pin); - } else { - arch_ioport_pin_to_base(pin)->GPIO_OVRC = arch_ioport_pin_to_mask(pin); - } -} - -__always_inline static void arch_ioport_set_port_level(ioport_port_t port, - ioport_port_mask_t mask, ioport_port_mask_t level) -{ - volatile GpioPort *base = arch_ioport_port_to_base(port); - if (level) { - base->GPIO_OVRS = mask; - } else { - base->GPIO_OVRC = mask; - } -} - -__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin) -{ - return arch_ioport_pin_to_base(pin)->GPIO_PVR & arch_ioport_pin_to_mask(pin); -} - -__always_inline static ioport_port_mask_t arch_ioport_get_port_level( - ioport_port_t port, ioport_port_mask_t mask) -{ - return arch_ioport_port_to_base(port)->GPIO_PVR & mask; -} - -__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin) -{ - arch_ioport_pin_to_base(pin)->GPIO_OVRT = arch_ioport_pin_to_mask(pin); -} - -__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->GPIO_OVRT = mask; -} - -__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port, - ioport_port_mask_t mask, enum ioport_sense pin_sense) -{ - volatile GpioPort *base = arch_ioport_port_to_base(port); - - if (pin_sense & 0x01) { - base->GPIO_IMR0S = mask; - } else { - base->GPIO_IMR0C = mask; - } - - if (pin_sense & 0x02) { - base->GPIO_IMR1S = mask; - } else { - base->GPIO_IMR1C = mask; - } -} - -__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin, - enum ioport_sense pin_sense) -{ - arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin), pin_sense); -} - -#endif /* IOPORT_SAM_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_pio.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_pio.h deleted file mode 100644 index 372fb7726c6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_pio.h +++ /dev/null @@ -1,380 +0,0 @@ -/** - * \file - * - * \brief SAM architecture specific IOPORT service implementation header file. - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef IOPORT_SAM_H -#define IOPORT_SAM_H - -#include - -#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 32 + (pin)) -#define IOPORT_BASE_ADDRESS (uintptr_t)PIOA -#define IOPORT_PIO_OFFSET ((uintptr_t)PIOB - (uintptr_t)PIOA) - -#define IOPORT_PIOA 0 -#define IOPORT_PIOB 1 -#define IOPORT_PIOC 2 -#define IOPORT_PIOD 3 -#define IOPORT_PIOE 4 -#define IOPORT_PIOF 5 - -/** - * \weakgroup ioport_group - * \section ioport_modes IOPORT Modes - * - * For details on these please see the SAM Manual. - * - * @{ - */ - -/** \name IOPORT Mode bit definitions */ -/** @{ */ -#define IOPORT_MODE_MUX_MASK (0x7 << 0) /*!< MUX bits mask */ -#define IOPORT_MODE_MUX_BIT0 ( 1 << 0) /*!< MUX BIT0 mask */ - -#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 -#define IOPORT_MODE_MUX_BIT1 ( 1 << 1) /*!< MUX BIT1 mask */ -#endif - -#define IOPORT_MODE_MUX_A ( 0 << 0) /*!< MUX function A */ -#define IOPORT_MODE_MUX_B ( 1 << 0) /*!< MUX function B */ - -#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 -#define IOPORT_MODE_MUX_C ( 2 << 0) /*!< MUX function C */ -#define IOPORT_MODE_MUX_D ( 3 << 0) /*!< MUX function D */ -#endif - -#define IOPORT_MODE_PULLUP ( 1 << 3) /*!< Pull-up */ - -#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 -#define IOPORT_MODE_PULLDOWN ( 1 << 4) /*!< Pull-down */ -#endif - -#define IOPORT_MODE_OPEN_DRAIN ( 1 << 5) /*!< Open drain */ - -#define IOPORT_MODE_GLITCH_FILTER ( 1 << 6) /*!< Glitch filter */ -#define IOPORT_MODE_DEBOUNCE ( 1 << 7) /*!< Input debounce */ -/** @} */ - -/** @} */ - -typedef uint32_t ioport_mode_t; -typedef uint32_t ioport_pin_t; -typedef uint32_t ioport_port_t; -typedef uint32_t ioport_port_mask_t; - -__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin) -{ - return pin >> 5; -} - -__always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port) -{ -#if (SAM4C || SAM4CM || SAM4CP) - if (port == IOPORT_PIOC) { - return (Pio *)(uintptr_t)PIOC; -# ifdef ID_PIOD - } else if (port == IOPORT_PIOD) { - return (Pio *)(uintptr_t)PIOD; -# endif - } else { - return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + - (IOPORT_PIO_OFFSET * port)); - } -#else - return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + - (IOPORT_PIO_OFFSET * port)); -#endif -} - -__always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin) -{ - return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin)); -} - -__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin) -{ - return 1U << (pin & 0x1F); -} - -__always_inline static void arch_ioport_init(void) -{ -#ifdef ID_PIOA - sysclk_enable_peripheral_clock(ID_PIOA); -#endif -#ifdef ID_PIOB - sysclk_enable_peripheral_clock(ID_PIOB); -#endif -#ifdef ID_PIOC - sysclk_enable_peripheral_clock(ID_PIOC); -#endif -#ifdef ID_PIOD - sysclk_enable_peripheral_clock(ID_PIOD); -#endif -#ifdef ID_PIOE - sysclk_enable_peripheral_clock(ID_PIOE); -#endif -#ifdef ID_PIOF - sysclk_enable_peripheral_clock(ID_PIOF); -#endif -} - -__always_inline static void arch_ioport_enable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->PIO_PER = mask; -} - -__always_inline static void arch_ioport_disable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->PIO_PDR = mask; -} - -__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin) -{ - arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin)); -} - -__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin) -{ - arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin)); -} - -__always_inline static void arch_ioport_set_port_mode(ioport_port_t port, - ioport_port_mask_t mask, ioport_mode_t mode) -{ - Pio *base = arch_ioport_port_to_base(port); - - if (mode & IOPORT_MODE_PULLUP) { - base->PIO_PUER = mask; - } else { - base->PIO_PUDR = mask; - } - -#if defined(IOPORT_MODE_PULLDOWN) - if (mode & IOPORT_MODE_PULLDOWN) { - base->PIO_PPDER = mask; - } else { - base->PIO_PPDDR = mask; - } -#endif - - if (mode & IOPORT_MODE_OPEN_DRAIN) { - base->PIO_MDER = mask; - } else { - base->PIO_MDDR = mask; - } - - if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) { - base->PIO_IFER = mask; - } else { - base->PIO_IFDR = mask; - } - - if (mode & IOPORT_MODE_DEBOUNCE) { -#if SAM3U || SAM3XA - base->PIO_DIFSR = mask; -#else - base->PIO_IFSCER = mask; -#endif - } else { -#if SAM3U || SAM3XA - base->PIO_SCIFSR = mask; -#else - base->PIO_IFSCDR = mask; -#endif - } - -#if !defined(IOPORT_MODE_MUX_BIT1) - if (mode & IOPORT_MODE_MUX_BIT0) { - base->PIO_ABSR |= mask; - } else { - base->PIO_ABSR &= ~mask; - } -#else - if (mode & IOPORT_MODE_MUX_BIT0) { - base->PIO_ABCDSR[0] |= mask; - } else { - base->PIO_ABCDSR[0] &= ~mask; - } - - if (mode & IOPORT_MODE_MUX_BIT1) { - base->PIO_ABCDSR[1] |= mask; - } else { - base->PIO_ABCDSR[1] &= ~mask; - } -#endif -} - -__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin, - ioport_mode_t mode) -{ - arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin), mode); -} - -__always_inline static void arch_ioport_set_port_dir(ioport_port_t port, - ioport_port_mask_t mask, enum ioport_direction group_direction) -{ - Pio *base = arch_ioport_port_to_base(port); - - if (group_direction == IOPORT_DIR_OUTPUT) { - base->PIO_OER = mask; - } else if (group_direction == IOPORT_DIR_INPUT) { - base->PIO_ODR = mask; - } - - base->PIO_OWER = mask; -} - -__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin, - enum ioport_direction dir) -{ - Pio *base = arch_ioport_pin_to_base(pin); - - if (dir == IOPORT_DIR_OUTPUT) { - base->PIO_OER = arch_ioport_pin_to_mask(pin); - } else if (dir == IOPORT_DIR_INPUT) { - base->PIO_ODR = arch_ioport_pin_to_mask(pin); - } - - base->PIO_OWER = arch_ioport_pin_to_mask(pin); -} - -__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin, - bool level) -{ - Pio *base = arch_ioport_pin_to_base(pin); - - if (level) { - base->PIO_SODR = arch_ioport_pin_to_mask(pin); - } else { - base->PIO_CODR = arch_ioport_pin_to_mask(pin); - } -} - -__always_inline static void arch_ioport_set_port_level(ioport_port_t port, - ioport_port_mask_t mask, ioport_port_mask_t level) -{ - Pio *base = arch_ioport_port_to_base(port); - - base->PIO_SODR = mask & level; - base->PIO_CODR = mask & ~level; -} - -__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin) -{ - return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin); -} - -__always_inline static ioport_port_mask_t arch_ioport_get_port_level( - ioport_port_t port, ioport_port_mask_t mask) -{ - return arch_ioport_port_to_base(port)->PIO_PDSR & mask; -} - -__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin) -{ - Pio *port = arch_ioport_pin_to_base(pin); - ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin); - - if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) { - port->PIO_CODR = mask; - } else { - port->PIO_SODR = mask; - } -} - -__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->PIO_ODSR ^= mask; -} - -__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port, - ioport_port_mask_t mask, enum ioport_sense pin_sense) -{ - Pio *base = arch_ioport_port_to_base(port); - /* AIMMR ELSR FRLHSR - * 0 X X IOPORT_SENSE_BOTHEDGES (Default) - * 1 0 0 IOPORT_SENSE_FALLING - * 1 0 1 IOPORT_SENSE_RISING - * 1 1 0 IOPORT_SENSE_LEVEL_LOW - * 1 1 1 IOPORT_SENSE_LEVEL_HIGH - */ - switch(pin_sense) { - case IOPORT_SENSE_LEVEL_LOW: - base->PIO_LSR = mask; - base->PIO_FELLSR = mask; - break; - case IOPORT_SENSE_LEVEL_HIGH: - base->PIO_LSR = mask; - base->PIO_REHLSR = mask; - break; - case IOPORT_SENSE_FALLING: - base->PIO_ESR = mask; - base->PIO_FELLSR = mask; - break; - case IOPORT_SENSE_RISING: - base->PIO_ESR = mask; - base->PIO_REHLSR = mask; - break; - default: - base->PIO_AIMDR = mask; - return; - } - base->PIO_AIMER = mask; -} - -__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin, - enum ioport_sense pin_sense) -{ - arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin), pin_sense); -} - -#endif /* IOPORT_SAM_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/sam_uart/uart_serial.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/sam_uart/uart_serial.h deleted file mode 100644 index 6e8ef52a353..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/sam_uart/uart_serial.h +++ /dev/null @@ -1,682 +0,0 @@ -/** - * \file - * - * \brief Uart Serial for SAM. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _UART_SERIAL_H_ -#define _UART_SERIAL_H_ - -#include "compiler.h" -#include "sysclk.h" -#if (SAMG55) -#include "flexcom.h" -#endif -#if ((!SAM4L) && (!SAMG55)) -#include "uart.h" -#endif -#include "usart.h" - -/** - * \name Serial Management Configuration - */ -//! @{ -#include "conf_uart_serial.h" - -//! @} - -/** Input parameters when initializing RS232 and similar modes. */ -typedef struct uart_rs232_options { - /** Set baud rate of the USART (unused in slave modes). */ - uint32_t baudrate; - - /** Number of bits to transmit as a character (5-bit to 9-bit). */ - uint32_t charlength; - - /** - * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc, - * USART_PMODE_ODD_gc. - */ - uint32_t paritytype; - - /** 1, 1.5 or 2 stop bits. */ - uint32_t stopbits; - -} usart_rs232_options_t; - -typedef usart_rs232_options_t usart_serial_options_t; - -typedef Usart *usart_if; - -/** - * \brief Initializes the Usart in master mode. - * - * \param p_usart Base address of the USART instance. - * \param opt Options needed to set up RS232 communication (see - * \ref usart_options_t). - */ -static inline void usart_serial_init(usart_if p_usart, - usart_serial_options_t *opt) -{ -#if ((!SAM4L) && (!SAMG55)) - sam_uart_opt_t uart_settings; - uart_settings.ul_mck = sysclk_get_peripheral_hz(); - uart_settings.ul_baudrate = opt->baudrate; - uart_settings.ul_mode = opt->paritytype; -#endif - - sam_usart_opt_t usart_settings; - usart_settings.baudrate = opt->baudrate; - usart_settings.char_length = opt->charlength; - usart_settings.parity_type = opt->paritytype; - usart_settings.stop_bits= opt->stopbits; - usart_settings.channel_mode= US_MR_CHMODE_NORMAL; - -#ifdef UART - if (UART == (Uart*)p_usart) { - sysclk_enable_peripheral_clock(ID_UART); - /* Configure UART */ - uart_init((Uart*)p_usart, &uart_settings); - } -#else -# ifdef UART0 - if (UART0 == (Uart*)p_usart) { - sysclk_enable_peripheral_clock(ID_UART0); - /* Configure UART */ - uart_init((Uart*)p_usart, &uart_settings); - } -# endif -# ifdef UART1 - if (UART1 == (Uart*)p_usart) { - sysclk_enable_peripheral_clock(ID_UART1); - /* Configure UART */ - uart_init((Uart*)p_usart, &uart_settings); - } -# endif -# ifdef UART2 - if (UART2 == (Uart*)p_usart) { - sysclk_enable_peripheral_clock(ID_UART2); - /* Configure UART */ - uart_init((Uart*)p_usart, &uart_settings); - } -# endif -# ifdef UART3 - if (UART3 == (Uart*)p_usart) { - sysclk_enable_peripheral_clock(ID_UART3); - /* Configure UART */ - uart_init((Uart*)p_usart, &uart_settings); - } -# endif -#endif /* ifdef UART */ - - -#ifdef USART - if (USART == p_usart) { -#if (!SAM4L) - sysclk_enable_peripheral_clock(ID_USART); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -#else -# ifdef USART0 - if (USART0 == p_usart) { -#if (!SAM4L) -#if (SAMG55) - flexcom_enable(FLEXCOM0); - flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(ID_USART0); -#endif - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -# endif -# ifdef USART1 - if (USART1 == p_usart) { -#if (!SAM4L) -#if (SAMG55) - flexcom_enable(FLEXCOM1); - flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(ID_USART1); -#endif - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -# endif -# ifdef USART2 - if (USART2 == p_usart) { -#if (!SAM4L) -#if (SAMG55) - flexcom_enable(FLEXCOM2); - flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(ID_USART2); -#endif - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -# endif -# ifdef USART3 - if (USART3 == p_usart) { -#if (!SAM4L) -#if (SAMG55) - flexcom_enable(FLEXCOM3); - flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(ID_USART3); -#endif - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -# endif -# ifdef USART4 - if (USART4 == p_usart) { -#if (!SAM4L) -#if (SAMG55) - flexcom_enable(FLEXCOM4); - flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(ID_USART4); -#endif - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -# endif -# ifdef USART5 - if (USART5 == p_usart) { -#if (!SAM4L) -#if (SAMG55) - flexcom_enable(FLEXCOM5); - flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(ID_USART5); -#endif - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -# endif -# ifdef USART6 - if (USART6 == p_usart) { -#if (!SAM4L) -#if (SAMG55) - flexcom_enable(FLEXCOM6); - flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(ID_USART6); -#endif - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -# endif -# ifdef USART7 - if (USART7 == p_usart) { -#if (!SAM4L) -#if (SAMG55) - flexcom_enable(FLEXCOM7); - flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART); -#else - sysclk_enable_peripheral_clock(ID_USART7); -#endif - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_hz()); -#endif -#if (SAM4L) - sysclk_enable_peripheral_clock(p_usart); - /* Configure USART */ - usart_init_rs232(p_usart, &usart_settings, - sysclk_get_peripheral_bus_hz(p_usart)); -#endif - /* Enable the receiver and transmitter. */ - usart_enable_tx(p_usart); - usart_enable_rx(p_usart); - } -# endif - -#endif /* ifdef USART */ - -} - -/** - * \brief Sends a character with the USART. - * - * \param p_usart Base address of the USART instance. - * \param c Character to write. - * - * \return Status. - * \retval 1 The character was written. - * \retval 0 The function timed out before the USART transmitter became - * ready to send. - */ -static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c) -{ -#ifdef UART - if (UART == (Uart*)p_usart) { - while (uart_write((Uart*)p_usart, c)!=0); - return 1; - } -#else -# ifdef UART0 - if (UART0 == (Uart*)p_usart) { - while (uart_write((Uart*)p_usart, c)!=0); - return 1; - } -# endif -# ifdef UART1 - if (UART1 == (Uart*)p_usart) { - while (uart_write((Uart*)p_usart, c)!=0); - return 1; - } -# endif -# ifdef UART2 - if (UART2 == (Uart*)p_usart) { - while (uart_write((Uart*)p_usart, c)!=0); - return 1; - } -# endif -# ifdef UART3 - if (UART3 == (Uart*)p_usart) { - while (uart_write((Uart*)p_usart, c)!=0); - return 1; - } -# endif -#endif /* ifdef UART */ - - -#ifdef USART - if (USART == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -#else -# ifdef USART0 - if (USART0 == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -# endif -# ifdef USART1 - if (USART1 == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -# endif -# ifdef USART2 - if (USART2 == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -# endif -# ifdef USART3 - if (USART3 == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -# endif -# ifdef USART4 - if (USART4 == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -# endif -# ifdef USART5 - if (USART5 == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -# endif -# ifdef USART6 - if (USART6 == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -# endif -# ifdef USART7 - if (USART7 == p_usart) { - while (usart_write(p_usart, c)!=0); - return 1; - } -# endif -#endif /* ifdef USART */ - - return 0; -} -/** - * \brief Waits until a character is received, and returns it. - * - * \param p_usart Base address of the USART instance. - * \param data Data to read - * - */ -static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data) -{ - uint32_t val = 0; - - /* Avoid Cppcheck Warning */ - UNUSED(val); - -#ifdef UART - if (UART == (Uart*)p_usart) { - while (uart_read((Uart*)p_usart, data)); - } -#else -# ifdef UART0 - if (UART0 == (Uart*)p_usart) { - while (uart_read((Uart*)p_usart, data)); - } -# endif -# ifdef UART1 - if (UART1 == (Uart*)p_usart) { - while (uart_read((Uart*)p_usart, data)); - } -# endif -# ifdef UART2 - if (UART2 == (Uart*)p_usart) { - while (uart_read((Uart*)p_usart, data)); - } -# endif -# ifdef UART3 - if (UART3 == (Uart*)p_usart) { - while (uart_read((Uart*)p_usart, data)); - } -# endif -#endif /* ifdef UART */ - - -#ifdef USART - if (USART == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -#else -# ifdef USART0 - if (USART0 == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -# endif -# ifdef USART1 - if (USART1 == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -# endif -# ifdef USART2 - if (USART2 == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -# endif -# ifdef USART3 - if (USART3 == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -# endif -# ifdef USART4 - if (USART4 == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -# endif -# ifdef USART5 - if (USART5 == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -# endif -# ifdef USART6 - if (USART6 == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -# endif -# ifdef USART7 - if (USART7 == p_usart) { - while (usart_read(p_usart, &val)); - *data = (uint8_t)(val & 0xFF); - } -# endif -#endif /* ifdef USART */ - -} - -/** - * \brief Check if Received data is ready. - * - * \param p_usart Base address of the USART instance. - * - * \retval 1 One data has been received. - * \retval 0 No data has been received. - */ -static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart) -{ -#ifdef UART - if (UART == (Uart*)p_usart) { - return uart_is_rx_ready((Uart*)p_usart); - } -#else -# ifdef UART0 - if (UART0 == (Uart*)p_usart) { - return uart_is_rx_ready((Uart*)p_usart); - } -# endif -# ifdef UART1 - if (UART1 == (Uart*)p_usart) { - return uart_is_rx_ready((Uart*)p_usart); - } -# endif -# ifdef UART2 - if (UART2 == (Uart*)p_usart) { - return uart_is_rx_ready((Uart*)p_usart); - } -# endif -# ifdef UART3 - if (UART3 == (Uart*)p_usart) { - return uart_is_rx_ready((Uart*)p_usart); - } -# endif -#endif /* ifdef UART */ - - -#ifdef USART - if (USART == p_usart) { - return usart_is_rx_ready(p_usart); - } -#else -# ifdef USART0 - if (USART0 == p_usart) { - return usart_is_rx_ready(p_usart); - } -# endif -# ifdef USART1 - if (USART1 == p_usart) { - return usart_is_rx_ready(p_usart); - } -# endif -# ifdef USART2 - if (USART2 == p_usart) { - return usart_is_rx_ready(p_usart); - } -# endif -# ifdef USART3 - if (USART3 == p_usart) { - return usart_is_rx_ready(p_usart); - } -# endif -# ifdef USART4 - if (USART4 == p_usart) { - return usart_is_rx_ready(p_usart); - } -# endif -# ifdef USART5 - if (USART5 == p_usart) { - return usart_is_rx_ready(p_usart); - } -# endif -# ifdef USART6 - if (USART6 == p_usart) { - return usart_is_rx_ready(p_usart); - } -# endif -# ifdef USART7 - if (USART7 == p_usart) { - return usart_is_rx_ready(p_usart); - } -# endif -#endif /* ifdef USART */ - - return 0; -} - -/** - * \brief Send a sequence of bytes to a USART device - * - * \param usart Base address of the USART instance. - * \param data data buffer to write - * \param len Length of data - * - */ -status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, - size_t len); - -/** - * \brief Receive a sequence of bytes to a USART device - * - * \param usart Base address of the USART instance. - * \param data data buffer to write - * \param len Length of data - * - */ -status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, - size_t len); - -#endif /* _UART_SERIAL_H_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/serial_platform.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/serial_platform.h deleted file mode 100644 index 6b52b371641..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/serial_platform.h +++ /dev/null @@ -1,279 +0,0 @@ -/** - * \file - * - * \brief Serial Mode management - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SERIAL_PLATFORM_H_INCLUDED -#define SERIAL_PLATFORM_H_INCLUDED - -#include -#include "status_codes.h" - -/** - * \typedef usart_if - * - * This type can be used independently to refer to USART module for the - * architecture used. It refers to the correct type definition for the - * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3. - */ - -#if XMEGA -# include "xmega_usart/usart_serial.h" -#elif MEGA_RF -# include "megarf_usart/usart_serial.h" -#elif UC3 -# include "uc3_usart/usart_serial.h" -#elif (SAMB) -#include "samb_uart/uart_serial.h" -#elif (SAM0) -#include "sam0_usart/usart_serial.h" -#elif SAM -# include "sam_uart/uart_serial.h" -#else -# error Unsupported chip type -#endif - -/** - * - * \defgroup serial_group Serial Interface (Serial) - * - * See \ref serial_quickstart. - * - * This is the common API for serial interface. Additional features are available - * in the documentation of the specific modules. - * - * \section serial_group_platform Platform Dependencies - * - * The serial API is partially chip- or platform-specific. While all - * platforms provide mostly the same functionality, there are some - * variations around how different bus types and clock tree structures - * are handled. - * - * The following functions are available on all platforms, but there may - * be variations in the function signature (i.e. parameters) and - * behaviour. These functions are typically called by platform-specific - * parts of drivers, and applications that aren't intended to be - * portable: - * - usart_serial_init() - * - usart_serial_putchar() - * - usart_serial_getchar() - * - usart_serial_write_packet() - * - usart_serial_read_packet() - * - * - * @{ - */ - -//! @} - -/** - * \page serial_quickstart Quick start guide for Serial Interface service - * - * This is the quick start guide for the \ref serial_group "Serial Interface module", with - * step-by-step instructions on how to configure and use the serial in a - * selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section serial_use_cases Serial use cases - * - \ref serial_basic_use_case - * - \subpage serial_use_case_1 - * - * \section serial_basic_use_case Basic use case - transmit a character - * In this use case, the serial module is configured for: - * - Using USARTD0 - * - Baudrate: 9600 - * - Character length: 8 bit - * - Parity mode: Disabled - * - Stop bit: None - * - RS232 mode - * - * The use case waits for a received character on the configured USART and - * echoes the character back to the same USART. - * - * \section serial_basic_use_case_setup Setup steps - * - * \subsection serial_basic_use_case_setup_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (sysclk)" - * - * \subsection serial_basic_use_case_setup_code Example code - * The following configuration must be added to the project (typically to a - * conf_uart_serial.h file, but it can also be added to your main application file.) - * - * \note The following takes SAM3X configuration for example, other devices have similar - * configuration, but their parameters may be different, refer to corresponding header files. - * - * \code - #define USART_SERIAL &USARTD0 - #define USART_SERIAL_BAUDRATE 9600 - #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT - #define USART_SERIAL_PARITY US_MR_PAR_NO - #define USART_SERIAL_STOP_BIT false -\endcode - * - * A variable for the received byte must be added: - * \code uint8_t received_byte; \endcode - * - * Add to application initialization: - * \code - sysclk_init(); - - static usart_serial_options_t usart_options = { - .baudrate = USART_SERIAL_BAUDRATE, - .charlength = USART_SERIAL_CHAR_LENGTH, - .paritytype = USART_SERIAL_PARITY, - .stopbits = USART_SERIAL_STOP_BIT - }; - - usart_serial_init(USART_SERIAL, &usart_options); -\endcode - * - * \subsection serial_basic_use_case_setup_flow Workflow - * -# Initialize system clock: - * - \code sysclk_init(); \endcode - * -# Create serial USART options struct: - * - \code - static usart_serial_options_t usart_options = { - .baudrate = USART_SERIAL_BAUDRATE, - .charlength = USART_SERIAL_CHAR_LENGTH, - .paritytype = USART_SERIAL_PARITY, - .stopbits = USART_SERIAL_STOP_BIT - }; -\endcode - * -# Initialize the serial service: - * - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode - * - * \section serial_basic_use_case_usage Usage steps - * - * \subsection serial_basic_use_case_usage_code Example code - * Add to application C-file: - * \code - usart_serial_getchar(USART_SERIAL, &received_byte); - usart_serial_putchar(USART_SERIAL, received_byte); -\endcode - * - * \subsection serial_basic_use_case_usage_flow Workflow - * -# Wait for reception of a character: - * - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode - * -# Echo the character back: - * - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode - */ - -/** - * \page serial_use_case_1 Advanced use case - Send a packet of serial data - * - * In this use case, the USART module is configured for: - * - Using USARTD0 - * - Baudrate: 9600 - * - Character length: 8 bit - * - Parity mode: Disabled - * - Stop bit: None - * - RS232 mode - * - * The use case sends a string of text through the USART. - * - * \section serial_use_case_1_setup Setup steps - * - * \subsection serial_use_case_1_setup_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (sysclk)" - * - * \subsection serial_use_case_1_setup_code Example code - * The following configuration must be added to the project (typically to a - * conf_uart_serial.h file, but it can also be added to your main application file.): - * - * \note The following takes SAM3X configuration for example, other devices have similar - * configuration, but their parameters may be different, refer to corresponding header files. - * - * \code - #define USART_SERIAL &USARTD0 - #define USART_SERIAL_BAUDRATE 9600 - #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT - #define USART_SERIAL_PARITY US_MR_PAR_NO - #define USART_SERIAL_STOP_BIT false -\endcode - * - * Add to application initialization: - * \code - sysclk_init(); - - static usart_serial_options_t usart_options = { - .baudrate = USART_SERIAL_BAUDRATE, - .charlength = USART_SERIAL_CHAR_LENGTH, - .paritytype = USART_SERIAL_PARITY, - .stopbits = USART_SERIAL_STOP_BIT - }; - - usart_serial_init(USART_SERIAL, &usart_options); -\endcode - * - * \subsection serial_use_case_1_setup_flow Workflow - * -# Initialize system clock: - * - \code sysclk_init(); \endcode - * -# Create USART options struct: - * - \code - static usart_serial_options_t usart_options = { - .baudrate = USART_SERIAL_BAUDRATE, - .charlength = USART_SERIAL_CHAR_LENGTH, - .paritytype = USART_SERIAL_PARITY, - .stopbits = USART_SERIAL_STOP_BIT - }; -\endcode - * -# Initialize in RS232 mode: - * - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode - * - * \section serial_use_case_1_usage Usage steps - * - * \subsection serial_use_case_1_usage_code Example code - * Add to, e.g., main loop in application C-file: - * \code - usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); -\endcode - * - * \subsection serial_use_case_1_usage_flow Workflow - * -# Write a string of text to the USART: - * - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode - */ - -#endif /* SERIAL_PLATFORM_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/usart_serial.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/usart_serial.c deleted file mode 100644 index 15117c8e997..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/usart_serial.c +++ /dev/null @@ -1,87 +0,0 @@ -/** - * - * \file - * - * \brief USART Serial driver functions. - * - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "serial_platform.h" - -/** - * \brief Send a sequence of bytes to USART device - * - * \param usart Base address of the USART instance. - * \param data Data buffer to read - * \param len Length of data - * - */ -status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, - size_t len) -{ - while (len) { - usart_serial_putchar(usart, *data); - len--; - data++; - } - return STATUS_OK; -} - - -/** - * \brief Receive a sequence of bytes from USART device - * - * \param usart Base address of the USART instance. - * \param data Data buffer to write - * \param len Length of data - * - */ -status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, - size_t len) -{ - while (len) { - usart_serial_getchar(usart, data); - len--; - data++; - } - return STATUS_OK; -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/module_config/conf_sleepmgr.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/module_config/conf_sleepmgr.h deleted file mode 100644 index 0f6efbc456f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_H -#define CONF_SLEEPMGR_H - -// Sleep manager options -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/sleepmgr.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/sleepmgr.c deleted file mode 100644 index 8531f56163a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/sleepmgr.c +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief SAM3/SAM4 Sleep manager implementation. - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/sleepmgr.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/sleepmgr.h deleted file mode 100644 index c7c31a311a0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/sleepmgr.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - * \file - * - * \brief SAM3/SAM4 Sleep manager implementation. - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SAM_SLEEPMGR_INCLUDED -#define SAM_SLEEPMGR_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include - -/** - * \weakgroup sleepmgr_group - * @{ - */ -#if (SAMG51 || SAMG53 || SAMG54) -enum sleepmgr_mode { - //! Active mode. - SLEEPMGR_ACTIVE = 0, - /*! Wait mode, wakeup fast (in 3ms). - * Potential Wake Up sources: fast startup events */ - SLEEPMGR_WAIT_FAST, - /*! Wait mode. - * Potential Wake Up sources: fast startup events */ - SLEEPMGR_WAIT, - - SLEEPMGR_NR_OF_MODES, -}; - -#else -enum sleepmgr_mode { - //! Active mode. - SLEEPMGR_ACTIVE = 0, - /*! WFE sleep mode. - * Potential Wake Up sources: - * fast startup events (USB, RTC, RTT, WKUPs), - * interrupt, and events. */ - SLEEPMGR_SLEEP_WFE, - /*! WFI sleep mode. - * Potential Wake Up sources: fast startup events and interrupt. */ - SLEEPMGR_SLEEP_WFI, - /*! Wait mode, wakeup fast (in 3ms). - * XTAL is not disabled when sleep. - * Potential Wake Up sources: fast startup events */ - SLEEPMGR_WAIT_FAST, - /*! Wait mode. - * Potential Wake Up sources: fast startup events */ - SLEEPMGR_WAIT, - //! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC. - SLEEPMGR_BACKUP, - - SLEEPMGR_NR_OF_MODES, -}; -#endif - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -//! Sleep mode lock counters -extern uint8_t sleepmgr_locks[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -//! @} - - -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - cpu_irq_disable(); - - // Atomically enable the global interrupts and enter the sleep mode. - pmc_sleep(sleep_mode); -#else - UNUSED(sleep_mode); - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ - -} - -//! @} - -#ifdef __cplusplus -} -#endif - -#endif /* SAM_SLEEPMGR_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sleepmgr.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sleepmgr.h deleted file mode 100644 index 517d90211ae..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sleepmgr.h +++ /dev/null @@ -1,273 +0,0 @@ -/** - * \file - * - * \brief Sleep manager - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SLEEPMGR_H -#define SLEEPMGR_H - -#include -#include - -#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70) -# include "sam/sleepmgr.h" -#elif XMEGA -# include "xmega/sleepmgr.h" -#elif UC3 -# include "uc3/sleepmgr.h" -#elif SAM4L -# include "sam4l/sleepmgr.h" -#elif MEGA -# include "mega/sleepmgr.h" -#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11 || SAMDA1) -# include "samd/sleepmgr.h" -#elif (SAML21 || SAML22) -# include "saml/sleepmgr.h" -#elif (SAMC21) -# include "samc/sleepmgr.h" -#else -# error Unsupported device. -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup sleepmgr_group Sleep manager - * - * The sleep manager is a service for ensuring that the device is not put to - * sleep in deeper sleep modes than the system (e.g., peripheral drivers, - * services or the application) allows at any given time. - * - * It is based on the use of lock counting for the individual sleep modes, and - * will put the device to sleep in the shallowest sleep mode that has a non-zero - * lock count. The drivers/services/application can change these counts by use - * of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode. - * Refer to \ref sleepmgr_mode for a list of the sleep modes available for - * locking, and the device datasheet for information on their effect. - * - * The application must supply the file \ref conf_sleepmgr.h. - * - * For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE - * must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not - * defined, the functions are replaced with dummy functions and no RAM is used. - * - * @{ - */ - -/** - * \def CONFIG_SLEEPMGR_ENABLE - * \brief Configuration symbol for enabling the sleep manager - * - * If this symbol is not defined, the functions of this service are replaced - * with dummy functions. This is useful for reducing code size and execution - * time if the sleep manager is not needed in the application. - * - * This symbol may be defined in \ref conf_sleepmgr.h. - */ -#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE) -# define CONFIG_SLEEPMGR_ENABLE -#endif - -/** - * \enum sleepmgr_mode - * \brief Sleep mode locks - * - * Identifiers for the different sleep mode locks. - */ - -/** - * \brief Initialize the lock counts - * - * Sets all lock counts to 0, except the very last one, which is set to 1. This - * is done to simplify the algorithm for finding the deepest allowable sleep - * mode in \ref sleepmgr_enter_sleep. - */ -static inline void sleepmgr_init(void) -{ -#ifdef CONFIG_SLEEPMGR_ENABLE - uint8_t i; - - for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) { - sleepmgr_locks[i] = 0; - } - sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** - * \brief Increase lock count for a sleep mode - * - * Increases the lock count for \a mode to ensure that the sleep manager does - * not put the device to sleep in the deeper sleep modes. - * - * \param mode Sleep mode to lock. - */ -static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode) -{ -#ifdef CONFIG_SLEEPMGR_ENABLE - irqflags_t flags; - - if(sleepmgr_locks[mode] >= 0xff) { - while (true) { - // Warning: maximum value of sleepmgr_locks buffer is no more than 255. - // Check APP or change the data type to uint16_t. - } - } - - // Enter a critical section - flags = cpu_irq_save(); - - ++sleepmgr_locks[mode]; - - // Leave the critical section - cpu_irq_restore(flags); -#else - UNUSED(mode); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** - * \brief Decrease lock count for a sleep mode - * - * Decreases the lock count for \a mode. If the lock count reaches 0, the sleep - * manager can put the device to sleep in the deeper sleep modes. - * - * \param mode Sleep mode to unlock. - */ -static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode) -{ -#ifdef CONFIG_SLEEPMGR_ENABLE - irqflags_t flags; - - if(sleepmgr_locks[mode] == 0) { - while (true) { - // Warning: minimum value of sleepmgr_locks buffer is no less than 0. - // Check APP. - } - } - - // Enter a critical section - flags = cpu_irq_save(); - - --sleepmgr_locks[mode]; - - // Leave the critical section - cpu_irq_restore(flags); -#else - UNUSED(mode); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** -* \brief Retrieves the deepest allowable sleep mode -* -* Searches through the sleep mode lock counts, starting at the shallowest sleep -* mode, until the first non-zero lock count is found. The deepest allowable -* sleep mode is then returned. -*/ -static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void) -{ - enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE; - -#ifdef CONFIG_SLEEPMGR_ENABLE - uint8_t *lock_ptr = sleepmgr_locks; - - // Find first non-zero lock count, starting with the shallowest modes. - while (!(*lock_ptr)) { - lock_ptr++; - sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1); - } - - // Catch the case where one too many sleepmgr_unlock_mode() call has been - // performed on the deepest sleep mode. - Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES); - -#endif /* CONFIG_SLEEPMGR_ENABLE */ - - return sleep_mode; -} - -/** - * \fn sleepmgr_enter_sleep - * \brief Go to sleep in the deepest allowed mode - * - * Searches through the sleep mode lock counts, starting at the shallowest sleep - * mode, until the first non-zero lock count is found. The device is then put to - * sleep in the sleep mode that corresponds to the lock. - * - * \note This function enables interrupts before going to sleep, and will leave - * them enabled upon return. This also applies if sleep is skipped due to ACTIVE - * mode being locked. - */ - -static inline void sleepmgr_enter_sleep(void) -{ -#ifdef CONFIG_SLEEPMGR_ENABLE - enum sleepmgr_mode sleep_mode; - - cpu_irq_disable(); - - // Find the deepest allowable sleep mode - sleep_mode = sleepmgr_get_sleep_mode(); - // Return right away if first mode (ACTIVE) is locked. - if (sleep_mode==SLEEPMGR_ACTIVE) { - cpu_irq_enable(); - return; - } - // Enter the deepest allowable sleep mode with interrupts enabled - sleepmgr_sleep(sleep_mode); -#else - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - - -//! @} - -#ifdef __cplusplus -} -#endif - -#endif /* SLEEPMGR_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/sleep_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/sleep_api.c deleted file mode 100644 index b21209f7437..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/sleep_api.c +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "sleep_api.h" -#include "sleepmgr.h" - -/** Send the device to sleep - * - * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the - * system clock to the core is stopped until a reset or an interrupt occurs. - * @param[void] void - * @return void - */ -void hal_sleep(void) -{ - enum sleepmgr_mode sleep_mode; - - sleep_mode = SLEEPMGR_SLEEP_WFI; - sleepmgr_sleep(sleep_mode); - -} -/** Send the device to deep sleep - * - * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode - * has the same sleep features as sleep plus it powers down peripherals and clocks. All state - * is still maintained. - * @param[void] void - * @return void - */ -void hal_deepsleep(void) -{ - enum sleepmgr_mode sleep_mode; - - sleep_mode = SLEEPMGR_SLEEP_WFE; - sleepmgr_sleep(sleep_mode); -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/spi_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/spi_api.c deleted file mode 100644 index bb80fd776a1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/spi_api.c +++ /dev/null @@ -1,561 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "device.h" -#include "dma_api.h" -#include "buffer.h" -#include "spi_api.h" -#include "pinmap.h" -#include "spi_driver.h" -#include "PeripheralPins.h" -#include "pdc.h" - - -/* Chip select. */ -#define SPI_CHIP_SEL 0 - -/* Clock polarity. */ -#define SPI_CLK_POLARITY 0 - -/* Clock phase. */ -#define SPI_CLK_PHASE 0 - -/* Last data */ -#define SPI_LAST 0 - - -/* Delay before SPCK. */ -#define SPI_DLYBS 0x40 - -/* Delay between consecutive transfers. */ -#define SPI_DLYBCT 0x10 - -#define MAX_SPI 8 - -/* SPI clock setting (Hz). */ -uint32_t gSPI_clock=500000; - -extern uint8_t g_sys_init; - - - -void pinmap_find_spi_info(Spi *sercombase, spi_t *obj) -{ - if(sercombase==SPI0) { - obj->spi.flexcom=FLEXCOM0; - obj->spi.module_number=0; - obj->spi.pdc =PDC_SPI0; - obj->spi.irq_type=FLEXCOM0_IRQn; - } else if(sercombase==SPI1) { - obj->spi.flexcom=FLEXCOM1; - obj->spi.module_number=1; - obj->spi.pdc =PDC_SPI1; - obj->spi.irq_type=FLEXCOM1_IRQn; - } else if(sercombase==SPI2) { - obj->spi.flexcom=FLEXCOM2; - obj->spi.module_number=2; - obj->spi.pdc =PDC_SPI2; - obj->spi.irq_type=FLEXCOM2_IRQn; - } else if(sercombase==SPI3) { - obj->spi.flexcom=FLEXCOM3; - obj->spi.module_number=3; - obj->spi.pdc =PDC_SPI3; - obj->spi.irq_type=FLEXCOM3_IRQn; - } else if(sercombase==SPI4) { - obj->spi.flexcom=FLEXCOM4; - obj->spi.module_number=4; - obj->spi.pdc =PDC_SPI4; - obj->spi.irq_type=FLEXCOM4_IRQn; - } else if(sercombase==SPI5) { - obj->spi.flexcom=FLEXCOM5; - obj->spi.module_number=5; - obj->spi.pdc =PDC_SPI5; - obj->spi.irq_type=FLEXCOM5_IRQn; - } else if(sercombase==SPI6) { - obj->spi.flexcom=FLEXCOM6; - obj->spi.module_number=6; - obj->spi.pdc =PDC_SPI6; - obj->spi.irq_type=FLEXCOM6_IRQn; - } else if(sercombase==SPI7) { - obj->spi.flexcom=FLEXCOM7; - obj->spi.module_number=7; - obj->spi.pdc =PDC_SPI7; - obj->spi.irq_type=FLEXCOM7_IRQn; - } else { - obj->spi.flexcom=(Flexcom *)NC; - obj->spi.module_number=0; - obj->spi.pdc =(Pdc *) NC; - } -} - -Spi* pinmap_find_sercom(PinName mosi, PinName miso, PinName sclk) -{ - Spi* sercomIndex=(Spi*)pinmap_peripheral (mosi,PinMap_SPI_MOSI); - if(sercomIndex== (Spi*)pinmap_peripheral (miso, PinMap_SPI_MISO) && - sercomIndex == (Spi*)pinmap_peripheral (sclk, PinMap_SPI_SCLK)) - return sercomIndex; - - return (Spi*)NC; -} - - -/** Initialize the SPI peripheral - * - * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral - * @param[out] obj The SPI object to initialize - * @param[in] mosi The pin to use for MOSI - * @param[in] miso The pin to use for MISO - * @param[in] sclk The pin to use for SCLK - * @param[in] ssel The pin to use for SSEL - */ -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel /*Not Used*/) -{ - MBED_ASSERT(obj); - MBED_ASSERT(mosi !=NC && miso!=NC && sclk !=NC ); - - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - - Spi *sercombase = pinmap_find_sercom(mosi,miso,sclk); - MBED_ASSERT(sercombase!=NC); - - pinmap_find_spi_info(sercombase, obj); - MBED_ASSERT(obj->spi.flexcom!=NC); - MBED_ASSERT(obj->spi.pdc!=NC); - - /* Configure SPI pins */ - pin_function(mosi, pinmap_find_function(mosi, PinMap_SPI_MOSI)); - ioport_disable_pin(mosi); - - pin_function(miso, pinmap_find_function(miso, PinMap_SPI_MISO)); - ioport_disable_pin(miso); - - pin_function(sclk, pinmap_find_function(sclk, PinMap_SPI_SCLK)); - ioport_disable_pin(sclk); - -#if (SAMG55) - /* Enable the peripheral and set SPI mode. */ - flexcom_enable(obj->spi.flexcom); - flexcom_set_opmode(obj->spi.flexcom, FLEXCOM_SPI); -#else - /* Configure an SPI peripheral. */ - spi_enable_clock(sercombase); -#endif - spi_disable(sercombase); - spi_reset(sercombase); - spi_set_lastxfer(sercombase); - spi_set_master_mode(sercombase); - spi_disable_mode_fault_detect(sercombase); - spi_set_peripheral_chip_select_value(sercombase, SPI_CHIP_SEL); - spi_set_clock_polarity(sercombase, SPI_CHIP_SEL, SPI_CLK_POLARITY); - spi_set_clock_phase(sercombase, SPI_CHIP_SEL, SPI_CLK_PHASE); - spi_set_bits_per_transfer(sercombase, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT); - spi_set_baudrate_div(sercombase, SPI_CHIP_SEL,(sysclk_get_cpu_hz() / gSPI_clock)); - spi_set_transfer_delay(sercombase, SPI_CHIP_SEL, SPI_DLYBS,SPI_DLYBCT); - - spi_enable(sercombase); - - pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); - - obj->spi.spi_base=sercombase; - obj->spi.cs= SPI_CHIP_SEL; - obj->spi.polarity=SPI_CLK_POLARITY; - obj->spi.phase=SPI_CLK_PHASE; - obj->spi.transferrate=SPI_CSR_BITS_8_BIT; - obj->spi.is_slave=0; -} - -/** Release a SPI object - * - * TODO: spi_free is currently unimplemented - * This will require reference counting at the C++ level to be safe - * - * Return the pins owned by the SPI object to their reset state - * Disable the SPI peripheral - * Disable the SPI clock - * @param[in] obj The SPI object to deinitialize - */ -void spi_free(spi_t *obj) -{ - MBED_ASSERT(obj); - spi_disable(obj->spi.spi_base); - spi_reset(obj->spi.spi_base); - flexcom_disable((Flexcom *)obj->spi.flexcom); -} - -uint32_t get_transfer_rate(int bits) -{ - switch(bits) { - case 8: - return SPI_CSR_BITS_8_BIT; - case 9: - return SPI_CSR_BITS_9_BIT; - case 10: - return SPI_CSR_BITS_10_BIT; - case 11: - return SPI_CSR_BITS_11_BIT; - case 12: - return SPI_CSR_BITS_12_BIT; - case 13: - return SPI_CSR_BITS_13_BIT; - case 14: - return SPI_CSR_BITS_14_BIT; - case 15: - return SPI_CSR_BITS_15_BIT; - case 16: - return SPI_CSR_BITS_16_BIT; - default: - return NC; - } -} - -/** Configure the SPI format - * - * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode - * @param[in,out] obj The SPI object to configure - * @param[in] bits The number of bits per frame - * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) - * @param[in] slave Zero for master mode or non-zero for slave mode - */ -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - uint32_t transferrate= get_transfer_rate(bits); - MBED_ASSERT(transferrate!=NC); - - spi_disable(obj->spi.spi_base); - obj->spi.transferrate=transferrate; - if(slave) { - spi_set_slave_mode(obj->spi.spi_base); - obj->spi.is_slave=1; - } else { - spi_set_master_mode(obj->spi.spi_base); - obj->spi.is_slave=0; - } - spi_set_bits_per_transfer(obj->spi.spi_base, obj->spi.cs, obj->spi.transferrate); - spi_set_clock_phase(obj->spi.spi_base, SPI_CHIP_SEL, (mode & 0x01)); - spi_set_clock_polarity(obj->spi.spi_base, SPI_CHIP_SEL, (mode & 0x02)); - - obj->spi.phase=(mode & 0x01); - obj->spi.polarity=(mode & 0x02); - spi_enable(obj->spi.spi_base); -} - -/** Set the SPI baud rate - * - * Actual frequency may differ from the desired frequency due to available dividers and bus clock - * Configures the SPI peripheral's baud rate - * @param[in,out] obj The SPI object to configure - * @param[in] hz The baud rate in Hz - */ - -void spi_frequency(spi_t *obj, int hz) -{ - spi_disable(obj->spi.spi_base); - int16_t baudrate_div=spi_calc_baudrate_div(hz, sysclk_get_cpu_hz()); - spi_set_baudrate_div(obj->spi.spi_base,obj->spi.cs,(uint8_t)baudrate_div); - spi_enable(obj->spi.spi_base); -} - -/**@}*/ -/** - * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer - * @{ - */ - -/** Write a byte out in master mode and receive a value - * - * @param[in] obj The SPI peripheral to use for sending - * @param[in] value The value to send - * @return Returns the value received during send - */ -int spi_master_write(spi_t *obj, int value) -{ - spi_status_t status=spi_write(obj->spi.spi_base,(uint16_t)value,obj->spi.cs,SPI_LAST); - if(status ==SPI_OK) { - uint16_t data; - status =spi_read(obj->spi.spi_base,&data,&obj->spi.cs); - if(status == SPI_OK) - return data; - } - return 0; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char _write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : _write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -/** Check if a value is available to read - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if a value is available - */ -int spi_slave_receive(spi_t *obj) -{ - if(obj->spi.spi_base->SPI_SR & SPI_SR_RDRF) - return 1; - return 0; -} - -/** Get a received value out of the SPI receive buffer in slave mode - * - * Blocks until a value is available - * @param[in] obj The SPI peripheral to read - * @return The value received - */ -int spi_slave_read(spi_t *obj) -{ - uint16_t data; - spi_status_t status =spi_read(obj->spi.spi_base, &data, &obj->spi.cs); - if(status == SPI_OK) - return data; - return 0; -} - -/** Write a value to the SPI peripheral in slave mode - * - * Blocks until the SPI peripheral can be written to - * @param[in] obj The SPI peripheral to write - * @param[in] value The value to write - */ -void spi_slave_write(spi_t *obj, int value) -{ - spi_write(obj->spi.spi_base,(uint16_t)value,obj->spi.cs,SPI_LAST); -} - -/** Checks if the specified SPI peripheral is in use - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if the peripheral is currently transmitting - */ -int spi_busy(spi_t *obj) -{ - if(obj->spi.spi_base->SPI_SR & SPI_SR_TDRE) //Transmit Data Register Empty - return 0; - return 1; -} - -/** Get the module number - * - * @param[in] obj The SPI peripheral to check - * @return The module number - */ -uint8_t spi_get_module(spi_t *obj) -{ - return obj->spi.module_number; -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - - -/**@}*/ -#if DEVICE_SPI_ASYNCH -/** - * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer - * @{ - */ - -/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff - * - * @param[in] obj The SPI object which holds the transfer information - * @param[in] tx The buffer to send - * @param[in] tx_length The number of words to transmit - * @param[in] rx The buffer to receive - * @param[in] rx_length The number of words to receive - * @param[in] bit_width The bit width of buffer words - * @param[in] event The logical OR of events to be registered - * @param[in] handler SPI interrupt handler - * @param[in] hint A suggestion for how to use DMA with this transfer - */ -#warning "Only DMA async supported by SPI master transfer" - -void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ - uint32_t pdcenable=0; - - if(bit_width) { - uint32_t transferrate= get_transfer_rate(bit_width); - spi_set_bits_per_transfer(obj->spi.spi_base, obj->spi.cs, transferrate); - } - - if(tx) { - pdc_packet_t pdc_packet_tx; - pdc_packet_tx.ul_addr=(uint32_t)tx; - pdc_packet_tx.ul_size=tx_length; - - pdcenable|=PERIPH_PTCR_TXTEN; - /* Configure PDC for data send */ - pdc_tx_init(obj->spi.pdc, &pdc_packet_tx, NULL); - } - - if(rx) { - pdc_rx_clear_cnt(obj->spi.pdc); - pdc_packet_t pdc_packet_rx; - pdc_packet_rx.ul_addr=(uint32_t)rx; - pdc_packet_rx.ul_size=rx_length; - pdcenable|=PERIPH_PTCR_RXTEN; - char *rxbuffer=(char *)rx; - for(uint8_t index=0; indexspi.pdc, &pdc_packet_rx, NULL); - } - - obj->spi.dma_usage=hint; - obj->spi.event=event; - - NVIC_ClearPendingIRQ(obj->spi.irq_type); - NVIC_DisableIRQ(obj->spi.irq_type); - NVIC_SetVector(obj->spi.irq_type,handler); - NVIC_EnableIRQ(obj->spi.irq_type); - - /* Enable SPI IRQ */ - spi_enable_interrupt(obj->spi.spi_base, SPI_IER_RXBUFF| SPI_IER_TXBUFE | SPI_IER_MODF | SPI_IER_OVRES); - - /* Enable PDC transfers */ - pdc_enable_transfer(obj->spi.pdc, pdcenable ); - -} - -/** The asynchronous IRQ handler - * - * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination - * conditions, such as buffer overflows or transfer complete. - * @param[in] obj The SPI object which holds the transfer information - * @return event flags if a transfer termination condition was met or 0 otherwise. - */ -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - uint32_t event=0; - - // Data transferred via DMA - if((obj->spi.spi_base->SPI_SR & SPI_IER_TXBUFE)) { - spi_disable_interrupt(obj->spi.spi_base, SPI_IDR_TXBUFE | SPI_IDR_MODF | SPI_IDR_OVRES); - if(obj->spi.event | SPI_EVENT_COMPLETE) - event |=SPI_EVENT_COMPLETE; - } - - if((obj->spi.spi_base->SPI_SR & SPI_IER_RXBUFF)) { - spi_disable_interrupt(obj->spi.spi_base, SPI_IDR_RXBUFF | SPI_IDR_MODF | SPI_IDR_OVRES); - if(obj->spi.event | SPI_EVENT_COMPLETE) - event |=SPI_EVENT_COMPLETE; - } - - if(obj->spi.spi_base->SPI_SR & SPI_SR_MODF) { - if(obj->spi.event | SPI_EVENT_ERROR) - event |=SPI_EVENT_ERROR; - } - - if(obj->spi.spi_base->SPI_SR & SPI_SR_OVRES) { - if(obj->spi.event | SPI_EVENT_RX_OVERFLOW) - event |=SPI_EVENT_RX_OVERFLOW; - } - - return event; -} - -/** Attempts to determine if the SPI peripheral is already in use. - * - * If a temporary DMA channel has been allocated, peripheral is in use. - * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA - * channel were allocated. - * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check - * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if - * there are any bytes in the FIFOs. - * @param[in] obj The SPI object to check for activity - * @return non-zero if the SPI port is active or zero if it is not. - */ - -uint8_t spi_active(spi_t *obj) -{ - if(obj->spi.spi_base->SPI_SR & SPI_SR_ENDTX && obj->spi.spi_base->SPI_SR & SPI_SR_ENDRX) - return 0; - return 1; -} - -/** Abort an SPI transfer - * - * @param obj The SPI peripheral to stop - */ -void spi_abort_asynch(spi_t *obj) -{ - /* Disable PDC transfers */ - pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); - - /* Clear PDC buffer receive counter */ - pdc_rx_clear_cnt(obj->spi.pdc); - - /* Disable SPI IRQ */ - spi_disable_interrupt(obj->spi.spi_base, SPI_IDR_TXBUFE); - spi_disable_interrupt(obj->spi.spi_base, SPI_IDR_RXBUFF); - - /* Disable SPI interrupt */ - NVIC_DisableIRQ(obj->spi.irq_type); -} - -#endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c deleted file mode 100644 index 8f6d6e65ca5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c +++ /dev/null @@ -1,193 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "cmsis.h" -#include "mbed_assert.h" -#include "compiler.h" -#include "sysclk.h" -#include "tc.h" - -uint8_t us_ticker_inited = 0; -extern uint8_t g_sys_init; -volatile uint16_t us_ticker_16bit_counter; -volatile uint16_t us_ticker_interrupt_counter; -volatile uint16_t us_ticker_interrupt_offset; -volatile uint32_t overflow32bitcounter = 0; - -#define TICKER_COUNTER_uS TC1 - -#define TICKER_COUNTER_CLK0 ID_TC3 -#define TICKER_COUNTER_CLK1 ID_TC4 - -#define TICKER_COUNTER_CHANNEL0 0 -#define TICKER_COUNTER_IRQn0 TC3_IRQn -#define TICKER_COUNTER_Handlr0 TC3_Handler - -#define TICKER_COUNTER_CHANNEL1 1 -#define TICKER_COUNTER_IRQn1 TC4_IRQn -#define TICKER_COUNTER_Handlr1 TC4_Handler - -#define OVERFLOW_16bit_VALUE 0xFFFF - - -void TICKER_COUNTER_Handlr1(void) -{ - uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); - uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); - - if (((status & interrupmask) & TC_IER_CPCS)) { - if(us_ticker_interrupt_counter) { - us_ticker_interrupt_counter--; - } else { - if(us_ticker_interrupt_offset) { - us_ticker_interrupt_offset=0; - tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); - tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)us_ticker_interrupt_offset); - tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); - } else - us_ticker_irq_handler(); - } - } -} - -void TICKER_COUNTER_Handlr0(void) -{ - uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0); - uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0); - - if (((status & interrupmask) & TC_IER_COVFS)) { - us_ticker_16bit_counter++; - if(us_ticker_16bit_counter == 0xFFFF) - overflow32bitcounter++; - } -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - us_ticker_16bit_counter=0; - us_ticker_interrupt_counter=0; - us_ticker_interrupt_offset=0; - - if (g_sys_init == 0) { - sysclk_init(); - system_board_init(); - g_sys_init = 1; - } - - /* Configure the PMC to enable the TC module. */ - sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK0); - sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK1); - -#if SAMG55 - /* Enable PCK output */ - pmc_disable_pck(PMC_PCK_3); - pmc_switch_pck_to_mck(PMC_PCK_3, PMC_PCK_PRES_CLK_1); - pmc_enable_pck(PMC_PCK_3); -#endif - - /* Init TC to Counter mode. */ - tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_CMR_TCCLKS_TIMER_CLOCK4); - tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_CMR_TCCLKS_TIMER_CLOCK4); - - - NVIC_DisableIRQ(TICKER_COUNTER_IRQn0); - - NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn0); - NVIC_SetPriority(TICKER_COUNTER_IRQn0, 0); - NVIC_EnableIRQ(TICKER_COUNTER_IRQn0); - tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_IER_COVFS); - - tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0); -} - - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) - us_ticker_init(); - - uint32_t counter_value=0; - uint16_t tickerbefore=0; - do { - tickerbefore=us_ticker_16bit_counter; - counter_value=tc_read_cv(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0); - } while(tickerbefore!=us_ticker_16bit_counter); - - return counter_value+(OVERFLOW_16bit_VALUE*us_ticker_16bit_counter); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - uint32_t cur_time; - int32_t delta; - - cur_time = us_ticker_read(); - delta = (int32_t)((uint32_t)timestamp - cur_time); - if (delta < 0) { - /* Event already occurred in past */ - us_ticker_irq_handler(); - return; - } - - uint16_t interruptat=0; - - if(delta > OVERFLOW_16bit_VALUE) { - us_ticker_interrupt_counter= (delta/OVERFLOW_16bit_VALUE) -1; - us_ticker_interrupt_offset=delta%OVERFLOW_16bit_VALUE; - interruptat=OVERFLOW_16bit_VALUE; - } else { - us_ticker_interrupt_counter=0; - us_ticker_interrupt_offset=0; - interruptat=delta; - } - - NVIC_DisableIRQ(TICKER_COUNTER_IRQn1); - - tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)interruptat); - - NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1); - NVIC_SetPriority(TICKER_COUNTER_IRQn1, 0); - NVIC_EnableIRQ(TICKER_COUNTER_IRQn1); - tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS ); - - tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(TICKER_COUNTER_IRQn1); -} - -void us_ticker_disable_interrupt(void) -{ - tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); - tc_disable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS); - NVIC_DisableIRQ(TICKER_COUNTER_IRQn1); -} - -void us_ticker_clear_interrupt(void) -{ - NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1); -} - -void us_ticker_free(void) -{ - -} diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_adc.h deleted file mode 100644 index 769e95464e4..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_adc.h +++ /dev/null @@ -1,411 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* Atmel Microcontroller Software Support */ -/* SAM Software Package License */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. */ -/* */ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_ADC_COMPONENT_ -#define _SAMG55_ADC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter */ -/* ============================================================================= */ -/** \addtogroup SAMG55_ADC Analog-to-Digital Converter */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Adc hardware registers */ -typedef struct { - __O uint32_t ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ - __IO uint32_t ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ - __IO uint32_t ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */ - __I uint32_t Reserved1[1]; - __O uint32_t ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ - __O uint32_t ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ - __I uint32_t ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ - __I uint32_t Reserved2[1]; - __I uint32_t ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ - __O uint32_t ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ - __O uint32_t ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ - __I uint32_t ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ - __I uint32_t ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ - __IO uint32_t ADC_LCTMR; /**< \brief (Adc Offset: 0x34) Last Channel Trigger Mode Register */ - __IO uint32_t ADC_LCCWR; /**< \brief (Adc Offset: 0x38) Last Channel Compare Window Register */ - __I uint32_t ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ - __IO uint32_t ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ - __IO uint32_t ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ - __I uint32_t Reserved3[1]; - __IO uint32_t ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ - __I uint32_t ADC_CDR[8]; /**< \brief (Adc Offset: 0x50) Channel Data Register */ - __I uint32_t Reserved4[29]; - __IO uint32_t ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protection Mode Register */ - __I uint32_t ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protection Status Register */ - __I uint32_t Reserved5[5]; - __IO uint32_t ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ - __IO uint32_t ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ - __I uint32_t Reserved6[2]; - __IO uint32_t ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ - __IO uint32_t ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ - __I uint32_t Reserved7[2]; - __O uint32_t ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ - __I uint32_t ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */ -#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */ -#define ADC_CR_CMPRST (0x1u << 4) /**< \brief (ADC_CR) Comparison Restart */ -/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ -#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */ -#define ADC_MR_TRGSEL_Pos 1 -#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) ADTRG External trigger */ -#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA0 Output of the Timer Counter Channel 0 */ -#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA1 Output of the Timer Counter Channel 1 */ -#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA2 Output of the Timer Counter Channel 2 */ -#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) RTCOUT0 */ -#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) RTTINC */ -#define ADC_MR_TRGSEL_ADC_TRIG6 (0x6u << 1) /**< \brief (ADC_MR) RTTEVENT */ -#define ADC_MR_TRGSEL_ADC_TRIG7 (0x7u << 1) /**< \brief (ADC_MR) - */ -#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. */ -#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The wake-up time can be modified by programming FWUP bit. */ -#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */ -#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF between conversions */ -#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is ON between conversions and ADC core is OFF */ -#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */ -#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */ -#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */ -#define ADC_MR_PRESCAL_Pos 8 -#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) -#define ADC_MR_STARTUP_Pos 16 -#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCCLK */ -#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCCLK */ -#define ADC_MR_SETTLING_Pos 20 -#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */ -#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCCLK */ -#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCCLK */ -#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCCLK */ -#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCCLK */ -#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */ -#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, and OFF0 are used for all channels. */ -#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_COR registers. */ -#define ADC_MR_TRACKTIM_Pos 24 -#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */ -#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos))) -#define ADC_MR_TRANSFER_Pos 28 -#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */ -#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos))) -#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */ -#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. */ -#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 register and can be used to convert the same channel several times. */ -/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */ -#define ADC_SEQR1_USCH1_Pos 0 -#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */ -#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos))) -#define ADC_SEQR1_USCH2_Pos 4 -#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */ -#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos))) -#define ADC_SEQR1_USCH3_Pos 8 -#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */ -#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos))) -#define ADC_SEQR1_USCH4_Pos 12 -#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */ -#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos))) -#define ADC_SEQR1_USCH5_Pos 16 -#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */ -#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos))) -#define ADC_SEQR1_USCH6_Pos 20 -#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */ -#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos))) -#define ADC_SEQR1_USCH7_Pos 24 -#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */ -#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos))) -/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ -#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ -#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ -#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ -#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ -#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ -#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ -#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ -/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA_Pos 0 -#define ADC_LCDR_LDATA_Msk (0xffffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */ -#define ADC_LCDR_CHNBOSR_Pos 24 -#define ADC_LCDR_CHNBOSR_Msk (0x1fu << ADC_LCDR_CHNBOSR_Pos) /**< \brief (ADC_LCDR) Channel Number in Oversampling Mode */ -/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_LCCHG (0x1u << 19) /**< \brief (ADC_IER) Last Channel Change Interrupt Enable */ -#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */ -#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ -#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_LCCHG (0x1u << 19) /**< \brief (ADC_IDR) Last Channel Change Interrupt Disable */ -#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */ -#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_LCCHG (0x1u << 19) /**< \brief (ADC_IMR) Last Channel Change Interrupt Mask */ -#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */ -#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ -#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 (automatically set / cleared) */ -#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 (automatically set / cleared) */ -#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 (automatically set / cleared) */ -#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 (automatically set / cleared) */ -#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 (automatically set / cleared) */ -#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 (automatically set / cleared) */ -#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 (automatically set / cleared) */ -#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 (automatically set / cleared) */ -#define ADC_ISR_LCCHG (0x1u << 19) /**< \brief (ADC_ISR) Last Channel Change (cleared on read) */ -#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */ -#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready (automatically set / cleared) */ -#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error (cleared on read) */ -#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Event (cleared on read) */ -#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of Receiver Transfer (automatically set / cleared) */ -#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) Reception Buffer Full (automatically set / cleared) */ -/* -------- ADC_LCTMR : (ADC Offset: 0x34) Last Channel Trigger Mode Register -------- */ -#define ADC_LCTMR_DUALTRIG (0x1u << 0) /**< \brief (ADC_LCTMR) Dual Trigger ON */ -#define ADC_LCTMR_CMPMOD_Pos 4 -#define ADC_LCTMR_CMPMOD_Msk (0x3u << ADC_LCTMR_CMPMOD_Pos) /**< \brief (ADC_LCTMR) Last Channel Comparison Mode */ -#define ADC_LCTMR_CMPMOD_LOW (0x0u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is lower than the low threshold of the window. */ -#define ADC_LCTMR_CMPMOD_HIGH (0x1u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is higher than the high threshold of the window. */ -#define ADC_LCTMR_CMPMOD_IN (0x2u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is in the comparison window. */ -#define ADC_LCTMR_CMPMOD_OUT (0x3u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is out of the comparison window. */ -/* -------- ADC_LCCWR : (ADC Offset: 0x38) Last Channel Compare Window Register -------- */ -#define ADC_LCCWR_LOWTHRES_Pos 0 -#define ADC_LCCWR_LOWTHRES_Msk (0xfffu << ADC_LCCWR_LOWTHRES_Pos) /**< \brief (ADC_LCCWR) Low Threshold */ -#define ADC_LCCWR_LOWTHRES(value) ((ADC_LCCWR_LOWTHRES_Msk & ((value) << ADC_LCCWR_LOWTHRES_Pos))) -#define ADC_LCCWR_HIGHTHRES_Pos 16 -#define ADC_LCCWR_HIGHTHRES_Msk (0xfffu << ADC_LCCWR_HIGHTHRES_Pos) /**< \brief (ADC_LCCWR) High Threshold */ -#define ADC_LCCWR_HIGHTHRES(value) ((ADC_LCCWR_HIGHTHRES_Msk & ((value) << ADC_LCCWR_HIGHTHRES_Pos))) -/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ -#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ -#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ -#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ -#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ -#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ -#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ -#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ -#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ -/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ -#define ADC_EMR_CMPMODE_Pos 0 -#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */ -#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ -#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ -#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */ -#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */ -#define ADC_EMR_CMPTYPE (0x1u << 2) /**< \brief (ADC_EMR) Comparison Type */ -#define ADC_EMR_CMPTYPE_FLAG_ONLY (0x0u << 2) /**< \brief (ADC_EMR) Any conversion is performed and comparison function drives the COMPE flag. */ -#define ADC_EMR_CMPTYPE_START_CONDITION (0x1u << 2) /**< \brief (ADC_EMR) Comparison conditions must be met to start the storage of all conversions until the CMPRST bit is set. */ -#define ADC_EMR_CMPSEL_Pos 4 -#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */ -#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos))) -#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */ -#define ADC_EMR_CMPFILTER_Pos 12 -#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */ -#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos))) -#define ADC_EMR_OSR_Pos 16 -#define ADC_EMR_OSR_Msk (0x7u << ADC_EMR_OSR_Pos) /**< \brief (ADC_EMR) Over Sampling Rate */ -#define ADC_EMR_OSR_NO_AVERAGE (0x0u << 16) /**< \brief (ADC_EMR) No averaging. ADC sample rate is maximum. */ -#define ADC_EMR_OSR_OSR4 (0x1u << 16) /**< \brief (ADC_EMR) 1-bit enhanced resolution by averaging. ADC sample rate divided by 4. */ -#define ADC_EMR_OSR_OSR16 (0x2u << 16) /**< \brief (ADC_EMR) 2-bit enhanced resolution by averaging. ADC sample rate divided by 16. */ -#define ADC_EMR_OSR_OSR64 (0x3u << 16) /**< \brief (ADC_EMR) 3-bit enhanced resolution by averaging. ADC sample rate divided by 64. */ -#define ADC_EMR_OSR_OSR256 (0x4u << 16) /**< \brief (ADC_EMR) 4-bit enhanced resolution by averaging. ADC sample rate divided by 256. */ -#define ADC_EMR_ASTE (0x1u << 20) /**< \brief (ADC_EMR) Averaging on Single Trigger Event */ -#define ADC_EMR_ASTE_MULTI_TRIG_AVERAGE (0x0u << 20) /**< \brief (ADC_EMR) The average requests several trigger events. */ -#define ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE (0x1u << 20) /**< \brief (ADC_EMR) The average requests only one trigger event. */ -#define ADC_EMR_SRCCLK (0x1u << 21) /**< \brief (ADC_EMR) External Clock Selection */ -#define ADC_EMR_SRCCLK_PERIPH_CLK (0x0u << 21) /**< \brief (ADC_EMR) The peripheral clock is the source for the ADC prescaler. */ -#define ADC_EMR_SRCCLK_PMC_PCK (0x1u << 21) /**< \brief (ADC_EMR) PMC PCKx is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock. */ -#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) Tag of the ADC_LCDR */ -/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ -#define ADC_CWR_LOWTHRES_Pos 0 -#define ADC_CWR_LOWTHRES_Msk (0xffffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */ -#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos))) -#define ADC_CWR_HIGHTHRES_Pos 16 -#define ADC_CWR_HIGHTHRES_Msk (0xffffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */ -#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos))) -/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ -#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for Channel 0 */ -#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for Channel 1 */ -#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for Channel 2 */ -#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for Channel 3 */ -#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for Channel 4 */ -#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for Channel 5 */ -#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for Channel 6 */ -#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for Channel 7 */ -#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential Inputs for Channel 0 */ -#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential Inputs for Channel 1 */ -#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential Inputs for Channel 2 */ -#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential Inputs for Channel 3 */ -#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential Inputs for Channel 4 */ -#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential Inputs for Channel 5 */ -#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential Inputs for Channel 6 */ -#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential Inputs for Channel 7 */ -/* -------- ADC_CDR[8] : (ADC Offset: 0x50) Channel Data Register -------- */ -#define ADC_CDR_DATA_Pos 0 -#define ADC_CDR_DATA_Msk (0xffffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[8]) Converted Data */ -/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protection Mode Register -------- */ -#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protection Enable */ -#define ADC_WPMR_WPKEY_Pos 8 -#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protection Key */ -#define ADC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (ADC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ -/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protection Status Register -------- */ -#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protection Violation Status */ -#define ADC_WPSR_WPVSRC_Pos 8 -#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protection Violation Source */ -/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR_Pos 0 -#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */ -#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) -/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR_Pos 0 -#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */ -#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) -/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR_Pos 0 -#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */ -#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) -/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR_Pos 0 -#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */ -#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) -/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -#define ADC_PTCR_RXCBEN (0x1u << 16) /**< \brief (ADC_PTCR) Receiver Circular Buffer Enable */ -#define ADC_PTCR_RXCBDIS (0x1u << 17) /**< \brief (ADC_PTCR) Receiver Circular Buffer Disable */ -#define ADC_PTCR_TXCBEN (0x1u << 18) /**< \brief (ADC_PTCR) Transmitter Circular Buffer Enable */ -#define ADC_PTCR_TXCBDIS (0x1u << 19) /**< \brief (ADC_PTCR) Transmitter Circular Buffer Disable */ -#define ADC_PTCR_ERRCLR (0x1u << 24) /**< \brief (ADC_PTCR) Transfer Bus Error Clear */ -/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ -#define ADC_PTSR_RXCBEN (0x1u << 16) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXCBEN (0x1u << 18) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ -#define ADC_PTSR_ERR (0x1u << 24) /**< \brief (ADC_PTSR) Transfer Bus Error (clear on read) */ - -/*@}*/ - - - -#endif /* _SAMG55_ADC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_chipid.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_chipid.h deleted file mode 100644 index 60d7fa40a2e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_chipid.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_CHIPID_COMPONENT_ -#define _SAMG55_CHIPID_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup SAMG55_CHIPID Chip Identifier */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Chipid hardware registers */ -typedef struct { - __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION_Pos 0 -#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC_Pos 5 -#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ -#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ -#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ -#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ -#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ -#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ -#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ -#define CHIPID_CIDR_NVPSIZ_Pos 8 -#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ -#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_Pos 12 -#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ -#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_Pos 16 -#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ -#define CHIPID_CIDR_ARCH_Pos 20 -#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_ARCH_SAMG55 (0x44u << 20) /**< \brief (CHIPID_CIDR) SAM G55 (49-lead version) */ -#define CHIPID_CIDR_NVPTYP_Pos 28 -#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ -#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ -#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ -#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ -#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ -#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID_Pos 0 -#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - - -#endif /* _SAMG55_CHIPID_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_cmcc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_cmcc.h deleted file mode 100644 index 0d3d1b5da66..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_cmcc.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_CMCC_COMPONENT_ -#define _SAMG55_CMCC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cortex-M Cache Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_CMCC Cortex-M Cache Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Cmcc hardware registers */ -typedef struct { - __I uint32_t CMCC_TYPE; /**< \brief (Cmcc Offset: 0x00) Cache Controller Type Register */ - __IO uint32_t CMCC_CFG; /**< \brief (Cmcc Offset: 0x04) Cache Controller Configuration Register */ - __O uint32_t CMCC_CTRL; /**< \brief (Cmcc Offset: 0x08) Cache Controller Control Register */ - __I uint32_t CMCC_SR; /**< \brief (Cmcc Offset: 0x0C) Cache Controller Status Register */ - __I uint32_t Reserved1[4]; - __O uint32_t CMCC_MAINT0; /**< \brief (Cmcc Offset: 0x20) Cache Controller Maintenance Register 0 */ - __O uint32_t CMCC_MAINT1; /**< \brief (Cmcc Offset: 0x24) Cache Controller Maintenance Register 1 */ - __IO uint32_t CMCC_MCFG; /**< \brief (Cmcc Offset: 0x28) Cache Controller Monitor Configuration Register */ - __IO uint32_t CMCC_MEN; /**< \brief (Cmcc Offset: 0x2C) Cache Controller Monitor Enable Register */ - __O uint32_t CMCC_MCTRL; /**< \brief (Cmcc Offset: 0x30) Cache Controller Monitor Control Register */ - __I uint32_t CMCC_MSR; /**< \brief (Cmcc Offset: 0x34) Cache Controller Monitor Status Register */ -} Cmcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- CMCC_TYPE : (CMCC Offset: 0x00) Cache Controller Type Register -------- */ -#define CMCC_TYPE_AP (0x1u << 0) /**< \brief (CMCC_TYPE) Access Port Access Allowed */ -#define CMCC_TYPE_GCLK (0x1u << 1) /**< \brief (CMCC_TYPE) Dynamic Clock Gating Supported */ -#define CMCC_TYPE_RANDP (0x1u << 2) /**< \brief (CMCC_TYPE) Random Selection Policy Supported */ -#define CMCC_TYPE_LRUP (0x1u << 3) /**< \brief (CMCC_TYPE) Least Recently Used Policy Supported */ -#define CMCC_TYPE_RRP (0x1u << 4) /**< \brief (CMCC_TYPE) Random Selection Policy Supported */ -#define CMCC_TYPE_WAYNUM_Pos 5 -#define CMCC_TYPE_WAYNUM_Msk (0x3u << CMCC_TYPE_WAYNUM_Pos) /**< \brief (CMCC_TYPE) Number of Ways */ -#define CMCC_TYPE_WAYNUM_DMAPPED (0x0u << 5) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY (0x1u << 5) /**< \brief (CMCC_TYPE) 2-way set associative */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY (0x2u << 5) /**< \brief (CMCC_TYPE) 4-way set associative */ -#define CMCC_TYPE_WAYNUM_ARCH8WAY (0x3u << 5) /**< \brief (CMCC_TYPE) 8-way set associative */ -#define CMCC_TYPE_LCKDOWN (0x1u << 7) /**< \brief (CMCC_TYPE) Lockdown Supported */ -#define CMCC_TYPE_CSIZE_Pos 8 -#define CMCC_TYPE_CSIZE_Msk (0x7u << CMCC_TYPE_CSIZE_Pos) /**< \brief (CMCC_TYPE) Data Cache Size */ -#define CMCC_TYPE_CSIZE_CSIZE_1KB (0x0u << 8) /**< \brief (CMCC_TYPE) Data cache size is 1 Kbyte */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB (0x1u << 8) /**< \brief (CMCC_TYPE) Data cache size is 2 Kbytes */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB (0x2u << 8) /**< \brief (CMCC_TYPE) Data cache size is 4 Kbytes */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB (0x3u << 8) /**< \brief (CMCC_TYPE) Data cache size is 8 Kbytes */ -#define CMCC_TYPE_CLSIZE_Pos 11 -#define CMCC_TYPE_CLSIZE_Msk (0x7u << CMCC_TYPE_CLSIZE_Pos) /**< \brief (CMCC_TYPE) Cache LIne Size */ -#define CMCC_TYPE_CLSIZE_CLSIZE_1KB (0x0u << 11) /**< \brief (CMCC_TYPE) Cache line size is 4 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_2KB (0x1u << 11) /**< \brief (CMCC_TYPE) Cache line size is 8 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_4KB (0x2u << 11) /**< \brief (CMCC_TYPE) Cache line size is 16 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8KB (0x3u << 11) /**< \brief (CMCC_TYPE) Cache line size is 32 bytes */ -/* -------- CMCC_CFG : (CMCC Offset: 0x04) Cache Controller Configuration Register -------- */ -#define CMCC_CFG_GCLKDIS (0x1u << 0) /**< \brief (CMCC_CFG) Disable Clock Gating */ -#define CMCC_CFG_ICDIS (0x1u << 1) /**< \brief (CMCC_CFG) */ -#define CMCC_CFG_DCDIS (0x1u << 2) /**< \brief (CMCC_CFG) */ -#define CMCC_CFG_PRGCSIZE_Pos 4 -#define CMCC_CFG_PRGCSIZE_Msk (0x7u << CMCC_CFG_PRGCSIZE_Pos) /**< \brief (CMCC_CFG) */ -#define CMCC_CFG_PRGCSIZE(value) ((CMCC_CFG_PRGCSIZE_Msk & ((value) << CMCC_CFG_PRGCSIZE_Pos))) -/* -------- CMCC_CTRL : (CMCC Offset: 0x08) Cache Controller Control Register -------- */ -#define CMCC_CTRL_CEN (0x1u << 0) /**< \brief (CMCC_CTRL) Cache Controller Enable */ -/* -------- CMCC_SR : (CMCC Offset: 0x0C) Cache Controller Status Register -------- */ -#define CMCC_SR_CSTS (0x1u << 0) /**< \brief (CMCC_SR) Cache Controller Status */ -/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) Cache Controller Maintenance Register 0 -------- */ -#define CMCC_MAINT0_INVALL (0x1u << 0) /**< \brief (CMCC_MAINT0) Cache Controller Invalidate All */ -/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) Cache Controller Maintenance Register 1 -------- */ -#define CMCC_MAINT1_INDEX_Pos 4 -#define CMCC_MAINT1_INDEX_Msk (0x1fu << CMCC_MAINT1_INDEX_Pos) /**< \brief (CMCC_MAINT1) Invalidate Index */ -#define CMCC_MAINT1_INDEX(value) ((CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))) -#define CMCC_MAINT1_WAY_Pos 30 -#define CMCC_MAINT1_WAY_Msk (0x3u << CMCC_MAINT1_WAY_Pos) /**< \brief (CMCC_MAINT1) Invalidate Way */ -#define CMCC_MAINT1_WAY_WAY0 (0x0u << 30) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY1 (0x1u << 30) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY2 (0x2u << 30) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY3 (0x3u << 30) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ -/* -------- CMCC_MCFG : (CMCC Offset: 0x28) Cache Controller Monitor Configuration Register -------- */ -#define CMCC_MCFG_MODE_Pos 0 -#define CMCC_MCFG_MODE_Msk (0x3u << CMCC_MCFG_MODE_Pos) /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ -#define CMCC_MCFG_MODE_CYCLE_COUNT (0x0u << 0) /**< \brief (CMCC_MCFG) Cycle counter */ -#define CMCC_MCFG_MODE_IHIT_COUNT (0x1u << 0) /**< \brief (CMCC_MCFG) Instruction hit counter */ -#define CMCC_MCFG_MODE_DHIT_COUNT (0x2u << 0) /**< \brief (CMCC_MCFG) Data hit counter */ -/* -------- CMCC_MEN : (CMCC Offset: 0x2C) Cache Controller Monitor Enable Register -------- */ -#define CMCC_MEN_MENABLE (0x1u << 0) /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ -/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) Cache Controller Monitor Control Register -------- */ -#define CMCC_MCTRL_SWRST (0x1u << 0) /**< \brief (CMCC_MCTRL) Monitor */ -/* -------- CMCC_MSR : (CMCC Offset: 0x34) Cache Controller Monitor Status Register -------- */ -#define CMCC_MSR_EVENT_CNT_Pos 0 -#define CMCC_MSR_EVENT_CNT_Msk (0xffffffffu << CMCC_MSR_EVENT_CNT_Pos) /**< \brief (CMCC_MSR) Monitor Event Counter */ - -/*@}*/ - -#endif /* _SAMG55_CMCC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_crccu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_crccu.h deleted file mode 100644 index 983ecab4c78..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_crccu.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_CRCCU_COMPONENT_ -#define _SAMG55_CRCCU_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup SAMG55_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Crccu hardware registers */ -typedef struct { - __IO uint32_t CRCCU_DSCR; /**< \brief (Crccu Offset: 0x000) CRCCU Descriptor Base Register */ - __I uint32_t Reserved1[1]; - __O uint32_t CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x008) CRCCU DMA Enable Register */ - __O uint32_t CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x00C) CRCCU DMA Disable Register */ - __I uint32_t CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x010) CRCCU DMA Status Register */ - __O uint32_t CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x014) CRCCU DMA Interrupt Enable Register */ - __O uint32_t CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x018) CRCCU DMA Interrupt Disable Register */ - __I uint32_t CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x001C) CRCCU DMA Interrupt Mask Register */ - __I uint32_t CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x020) CRCCU DMA Interrupt Status Register */ - __I uint32_t Reserved2[4]; - __O uint32_t CRCCU_CR; /**< \brief (Crccu Offset: 0x034) CRCCU Control Register */ - __IO uint32_t CRCCU_MR; /**< \brief (Crccu Offset: 0x038) CRCCU Mode Register */ - __I uint32_t CRCCU_SR; /**< \brief (Crccu Offset: 0x03C) CRCCU Status Register */ - __O uint32_t CRCCU_IER; /**< \brief (Crccu Offset: 0x040) CRCCU Interrupt Enable Register */ - __O uint32_t CRCCU_IDR; /**< \brief (Crccu Offset: 0x044) CRCCU Interrupt Disable Register */ - __I uint32_t CRCCU_IMR; /**< \brief (Crccu Offset: 0x048) CRCCU Interrupt Mask Register */ - __I uint32_t CRCCU_ISR; /**< \brief (Crccu Offset: 0x004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR_Pos 9 -#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos))) -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x00C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE_Pos 2 -#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER_Pos 4 -#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */ -#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos))) -#define CRCCU_MR_BITORDER (0x1u << 17) /**< \brief (CRCCU_MR) Precomputation Bit Swap Operation of the CRC */ -#define CRCCU_MR_BITORDER_MSBFIRST (0x0u << 17) /**< \brief (CRCCU_MR) CRC computation is performed from the most significant bit to the least significant bit */ -#define CRCCU_MR_BITORDER_LSBFIRST (0x1u << 17) /**< \brief (CRCCU_MR) CRC computation is performed from the least significant bit to the most significant bit */ -/* -------- CRCCU_SR : (CRCCU Offset: 0x03C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC_Pos 0 -#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - - -#endif /* _SAMG55_CRCCU_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_efc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_efc.h deleted file mode 100644 index 830eb306e07..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_efc.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_EFC_COMPONENT_ -#define _SAMG55_EFC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_EFC Embedded Flash Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Efc hardware registers */ -typedef struct { - __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ - __I uint32_t Reserved1[53]; - __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ -} Efc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ -#define EEFC_FMR_FWS_Pos 8 -#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) -#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ -#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD_Pos 0 -#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ -#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ -#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ -#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ -#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ -#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ -#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ -#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ -#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ -#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ -#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ -#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ -#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ -#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ -#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ -#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ -#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ -#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ -#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ -#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ -#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ -#define EEFC_FCR_FARG_Pos 8 -#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) -#define EEFC_FCR_FKEY_Pos 24 -#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE_Pos 0 -#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ -/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ -#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ -#define EEFC_WPMR_WPKEY_Pos 8 -#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ -#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ - -/*@}*/ - -#endif /* _SAMG55_EFC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_flexcom.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_flexcom.h deleted file mode 100644 index 4516bb0fcd7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_flexcom.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM_COMPONENT_ -#define _SAMG55_FLEXCOM_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Flexible Serial Communication */ -/* ============================================================================= */ -/** \addtogroup SAMG55_FLEXCOM Flexible Serial Communication */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Flexcom hardware registers */ -typedef struct { - __IO uint32_t FLEXCOM_MR; /**< \brief (Flexcom Offset: 0x0000) FLEXCOM Mode register */ - __I uint32_t Reserved1[3]; - __I uint32_t FLEXCOM_RHR; /**< \brief (Flexcom Offset: 0x0010) FLEXCOM Receive Holding Register */ - __I uint32_t Reserved2[3]; - __IO uint32_t FLEXCOM_THR; /**< \brief (Flexcom Offset: 0x0020) FLEXCOM Transmit Holding Register */ -} Flexcom; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- FLEXCOM_MR : (FLEXCOM Offset: 0x0000) FLEXCOM Mode register -------- */ -#define FLEXCOM_MR_OPMODE_Pos 0 -#define FLEXCOM_MR_OPMODE_Msk (0x3u << FLEXCOM_MR_OPMODE_Pos) /**< \brief (FLEXCOM_MR) FLEXCOM Operating Mode */ -#define FLEXCOM_MR_OPMODE_NO_COM (0x0u << 0) /**< \brief (FLEXCOM_MR) No communication */ -#define FLEXCOM_MR_OPMODE_USART (0x1u << 0) /**< \brief (FLEXCOM_MR) All related USART related protocols are selected (RS232, RS485, ISO7816, LIN,)All SPI/TWI related registers are not accessible and have no impact on IOs. */ -#define FLEXCOM_MR_OPMODE_SPI (0x2u << 0) /**< \brief (FLEXCOM_MR) SPI operating mode is selected.All USART/TWI related registers are not accessible and have no impact on IOs. */ -#define FLEXCOM_MR_OPMODE_TWI (0x3u << 0) /**< \brief (FLEXCOM_MR) All related TWI protocols are selected (TWI, SMBUS). All USART/SPI related registers are not accessible and have no impact on IOs. */ -/* -------- FLEXCOM_RHR : (FLEXCOM Offset: 0x0010) FLEXCOM Receive Holding Register -------- */ -#define FLEXCOM_RHR_RXDATA_Pos 0 -#define FLEXCOM_RHR_RXDATA_Msk (0xffffu << FLEXCOM_RHR_RXDATA_Pos) /**< \brief (FLEXCOM_RHR) Receive Data */ -/* -------- FLEXCOM_THR : (FLEXCOM Offset: 0x0020) FLEXCOM Transmit Holding Register -------- */ -#define FLEXCOM_THR_TXDATA_Pos 0 -#define FLEXCOM_THR_TXDATA_Msk (0xffffu << FLEXCOM_THR_TXDATA_Pos) /**< \brief (FLEXCOM_THR) Transmit Data */ -#define FLEXCOM_THR_TXDATA(value) ((FLEXCOM_THR_TXDATA_Msk & ((value) << FLEXCOM_THR_TXDATA_Pos))) - -/*@}*/ - - -#endif /* _SAMG55_FLEXCOM_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_gpbr.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_gpbr.h deleted file mode 100644 index e296fb1b1d1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_gpbr.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_GPBR_COMPONENT_ -#define _SAMG55_GPBR_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ -/* ============================================================================= */ -/** \addtogroup SAMG55_GPBR General Purpose Backup Registers */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Gpbr hardware registers */ -typedef struct { - __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ -} Gpbr; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ -#define SYS_GPBR_GPBR_VALUE_Pos 0 -#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ -#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) - -/*@}*/ - - -#endif /* _SAMG55_GPBR_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_i2sc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_i2sc.h deleted file mode 100644 index 7c13089448c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_i2sc.h +++ /dev/null @@ -1,246 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_I2SC_COMPONENT_ -#define _SAMG55_I2SC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Inter-IC Sound Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_I2SC Inter-IC Sound Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief I2sc hardware registers */ -typedef struct { - __O uint32_t I2SC_CR; /**< \brief (I2sc Offset: 0x00) Control Register */ - __IO uint32_t I2SC_MR; /**< \brief (I2sc Offset: 0x04) Mode Register */ - __I uint32_t I2SC_SR; /**< \brief (I2sc Offset: 0x08) Status Register */ - __O uint32_t I2SC_SCR; /**< \brief (I2sc Offset: 0x0C) Status Clear Register */ - __O uint32_t I2SC_SSR; /**< \brief (I2sc Offset: 0x10) Status Set Register */ - __O uint32_t I2SC_IER; /**< \brief (I2sc Offset: 0x14) Interrupt Enable Register */ - __O uint32_t I2SC_IDR; /**< \brief (I2sc Offset: 0x18) Interrupt Disable Register */ - __I uint32_t I2SC_IMR; /**< \brief (I2sc Offset: 0x1C) Interrupt Mask Register */ - __I uint32_t I2SC_RHR; /**< \brief (I2sc Offset: 0x20) Receiver Holding Register */ - __O uint32_t I2SC_THR; /**< \brief (I2sc Offset: 0x24) Transmitter Holding Register */ - __I uint32_t Reserved1[54]; - __IO uint32_t I2SC_RPR; /**< \brief (I2sc Offset: 0x100) Receive Pointer Register */ - __IO uint32_t I2SC_RCR; /**< \brief (I2sc Offset: 0x104) Receive Counter Register */ - __IO uint32_t I2SC_TPR; /**< \brief (I2sc Offset: 0x108) Transmit Pointer Register */ - __IO uint32_t I2SC_TCR; /**< \brief (I2sc Offset: 0x10C) Transmit Counter Register */ - __IO uint32_t I2SC_RNPR; /**< \brief (I2sc Offset: 0x110) Receive Next Pointer Register */ - __IO uint32_t I2SC_RNCR; /**< \brief (I2sc Offset: 0x114) Receive Next Counter Register */ - __IO uint32_t I2SC_TNPR; /**< \brief (I2sc Offset: 0x118) Transmit Next Pointer Register */ - __IO uint32_t I2SC_TNCR; /**< \brief (I2sc Offset: 0x11C) Transmit Next Counter Register */ - __O uint32_t I2SC_PTCR; /**< \brief (I2sc Offset: 0x120) Transfer Control Register */ - __I uint32_t I2SC_PTSR; /**< \brief (I2sc Offset: 0x124) Transfer Status Register */ -} I2sc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- I2SC_CR : (I2SC Offset: 0x00) Control Register -------- */ -#define I2SC_CR_RXEN (0x1u << 0) /**< \brief (I2SC_CR) Receiver Enable */ -#define I2SC_CR_RXDIS (0x1u << 1) /**< \brief (I2SC_CR) Receiver Disable */ -#define I2SC_CR_CKEN (0x1u << 2) /**< \brief (I2SC_CR) Clocks Enable */ -#define I2SC_CR_CKDIS (0x1u << 3) /**< \brief (I2SC_CR) Clocks Disable */ -#define I2SC_CR_TXEN (0x1u << 4) /**< \brief (I2SC_CR) Transmitter Enable */ -#define I2SC_CR_TXDIS (0x1u << 5) /**< \brief (I2SC_CR) Transmitter Disable */ -#define I2SC_CR_SWRST (0x1u << 7) /**< \brief (I2SC_CR) Software Reset */ -/* -------- I2SC_MR : (I2SC Offset: 0x04) Mode Register -------- */ -#define I2SC_MR_MODE (0x1u << 0) /**< \brief (I2SC_MR) Inter-IC Sound Controller Mode */ -#define I2SC_MR_MODE_SLAVE (0x0u << 0) /**< \brief (I2SC_MR) I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization. */ -#define I2SC_MR_MODE_MASTER (0x1u << 0) /**< \brief (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if IMCKMODE bit of I2SC_MR is set. */ -#define I2SC_MR_DATALENGTH_Pos 2 -#define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos) /**< \brief (I2SC_MR) Data Word Length */ -#define I2SC_MR_DATALENGTH_32_BITS (0x0u << 2) /**< \brief (I2SC_MR) Data length is set to 32 bits */ -#define I2SC_MR_DATALENGTH_24_BITS (0x1u << 2) /**< \brief (I2SC_MR) Data length is set to 24 bits */ -#define I2SC_MR_DATALENGTH_20_BITS (0x2u << 2) /**< \brief (I2SC_MR) Data length is set to 20 bits */ -#define I2SC_MR_DATALENGTH_18_BITS (0x3u << 2) /**< \brief (I2SC_MR) Data length is set to 18 bits */ -#define I2SC_MR_DATALENGTH_16_BITS (0x4u << 2) /**< \brief (I2SC_MR) Data length is set to 16 bits */ -#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2) /**< \brief (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */ -#define I2SC_MR_DATALENGTH_8_BITS (0x6u << 2) /**< \brief (I2SC_MR) Data length is set to 8 bits */ -#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2) /**< \brief (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */ -#define I2SC_MR_RXMONO (0x1u << 8) /**< \brief (I2SC_MR) Receive Mono */ -#define I2SC_MR_RXDMA (0x1u << 9) /**< \brief (I2SC_MR) Single or Multiple PDC Channels for Receiver */ -#define I2SC_MR_RXLOOP (0x1u << 10) /**< \brief (I2SC_MR) Loop-back Test Mode */ -#define I2SC_MR_TXMONO (0x1u << 12) /**< \brief (I2SC_MR) Transmit Mono */ -#define I2SC_MR_TXDMA (0x1u << 13) /**< \brief (I2SC_MR) Single or Multiple PDC Channels for Transmitter */ -#define I2SC_MR_TXSAME (0x1u << 14) /**< \brief (I2SC_MR) Transmit Data when Underrun */ -#define I2SC_MR_IMCKDIV_Pos 16 -#define I2SC_MR_IMCKDIV_Msk (0x3fu << I2SC_MR_IMCKDIV_Pos) /**< \brief (I2SC_MR) Peripheral Clock to I2SC Master Clock Ratio */ -#define I2SC_MR_IMCKDIV(value) ((I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos))) -#define I2SC_MR_IMCKFS_Pos 24 -#define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos) /**< \brief (I2SC_MR) Master Clock to fs Ratio */ -#define I2SC_MR_IMCKFS_M2SF16 (0x0u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 16 */ -#define I2SC_MR_IMCKFS_M2SF32 (0x1u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 32 */ -#define I2SC_MR_IMCKFS_M2SF48 (0x2u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 48 */ -#define I2SC_MR_IMCKFS_M2SF64 (0x3u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 64 */ -#define I2SC_MR_IMCKFS_M2SF96 (0x5u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 96 */ -#define I2SC_MR_IMCKFS_M2SF128 (0x7u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 128 */ -#define I2SC_MR_IMCKFS_M2SF192 (0xBu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 192 */ -#define I2SC_MR_IMCKFS_M2SF256 (0xFu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 256 */ -#define I2SC_MR_IMCKFS_M2SF384 (0x17u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 384 */ -#define I2SC_MR_IMCKFS_M2SF512 (0x1Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 512 */ -#define I2SC_MR_IMCKFS_M2SF768 (0x2Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 768 */ -#define I2SC_MR_IMCKFS_M2SF1024 (0x3Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1024 */ -#define I2SC_MR_IMCKMODE (0x1u << 30) /**< \brief (I2SC_MR) Master Clock Mode */ -#define I2SC_MR_IWS (0x1u << 31) /**< \brief (I2SC_MR) I2SWS TDM Slot Width */ -/* -------- I2SC_SR : (I2SC Offset: 0x08) Status Register -------- */ -#define I2SC_SR_RXEN (0x1u << 0) /**< \brief (I2SC_SR) Receiver Enabled */ -#define I2SC_SR_RXRDY (0x1u << 1) /**< \brief (I2SC_SR) Receive Ready */ -#define I2SC_SR_RXOR (0x1u << 2) /**< \brief (I2SC_SR) Receive Overrun */ -#define I2SC_SR_ENDRX (0x1u << 3) /**< \brief (I2SC_SR) End of Receiver Transfer */ -#define I2SC_SR_TXEN (0x1u << 4) /**< \brief (I2SC_SR) Transmitter Enabled */ -#define I2SC_SR_TXRDY (0x1u << 5) /**< \brief (I2SC_SR) Transmit Ready */ -#define I2SC_SR_TXUR (0x1u << 6) /**< \brief (I2SC_SR) Transmit Underrun */ -#define I2SC_SR_ENDTX (0x1u << 7) /**< \brief (I2SC_SR) End of Transmitter Transfer */ -#define I2SC_SR_RXORCH_Pos 8 -#define I2SC_SR_RXORCH_Msk (0x3u << I2SC_SR_RXORCH_Pos) /**< \brief (I2SC_SR) Receive Overrun Channel */ -#define I2SC_SR_RXBUFF (0x1u << 19) /**< \brief (I2SC_SR) Receive Buffer Full */ -#define I2SC_SR_TXURCH_Pos 20 -#define I2SC_SR_TXURCH_Msk (0x3u << I2SC_SR_TXURCH_Pos) /**< \brief (I2SC_SR) Transmit Underrun Channel */ -#define I2SC_SR_TXBUFE (0x1u << 31) /**< \brief (I2SC_SR) Transmit Buffer Empty */ -/* -------- I2SC_SCR : (I2SC Offset: 0x0C) Status Clear Register -------- */ -#define I2SC_SCR_RXOR (0x1u << 2) /**< \brief (I2SC_SCR) Receive Overrun Status Clear */ -#define I2SC_SCR_TXUR (0x1u << 6) /**< \brief (I2SC_SCR) Transmit Underrun Status Clear */ -#define I2SC_SCR_RXORCH_Pos 8 -#define I2SC_SCR_RXORCH_Msk (0x3u << I2SC_SCR_RXORCH_Pos) /**< \brief (I2SC_SCR) Receive Overrun Per Channel Status Clear */ -#define I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos))) -#define I2SC_SCR_TXURCH_Pos 20 -#define I2SC_SCR_TXURCH_Msk (0x3u << I2SC_SCR_TXURCH_Pos) /**< \brief (I2SC_SCR) Transmit Underrun Per Channel Status Clear */ -#define I2SC_SCR_TXURCH(value) ((I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos))) -/* -------- I2SC_SSR : (I2SC Offset: 0x10) Status Set Register -------- */ -#define I2SC_SSR_RXOR (0x1u << 2) /**< \brief (I2SC_SSR) Receive Overrun Status Set */ -#define I2SC_SSR_TXUR (0x1u << 6) /**< \brief (I2SC_SSR) Transmit Underrun Status Set */ -#define I2SC_SSR_RXORCH_Pos 8 -#define I2SC_SSR_RXORCH_Msk (0x3u << I2SC_SSR_RXORCH_Pos) /**< \brief (I2SC_SSR) Receive Overrun Per Channel Status Set */ -#define I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos))) -#define I2SC_SSR_TXURCH_Pos 20 -#define I2SC_SSR_TXURCH_Msk (0x3u << I2SC_SSR_TXURCH_Pos) /**< \brief (I2SC_SSR) Transmit Underrun Per Channel Status Set */ -#define I2SC_SSR_TXURCH(value) ((I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos))) -/* -------- I2SC_IER : (I2SC Offset: 0x14) Interrupt Enable Register -------- */ -#define I2SC_IER_RXRDY (0x1u << 1) /**< \brief (I2SC_IER) Receiver Ready Interrupt Enable */ -#define I2SC_IER_RXOR (0x1u << 2) /**< \brief (I2SC_IER) Receiver Overrun Interrupt Enable */ -#define I2SC_IER_ENDRX (0x1u << 3) /**< \brief (I2SC_IER) End of Reception Interrupt Enable */ -#define I2SC_IER_TXRDY (0x1u << 5) /**< \brief (I2SC_IER) Transmit Ready Interrupt Enable */ -#define I2SC_IER_TXUR (0x1u << 6) /**< \brief (I2SC_IER) Transmit Underflow Interrupt Enable */ -#define I2SC_IER_ENDTX (0x1u << 7) /**< \brief (I2SC_IER) End of Transmission Interrupt Enable */ -#define I2SC_IER_RXFULL (0x1u << 19) /**< \brief (I2SC_IER) Receive Buffer Full Interrupt Enable */ -#define I2SC_IER_TXEMPTY (0x1u << 31) /**< \brief (I2SC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- I2SC_IDR : (I2SC Offset: 0x18) Interrupt Disable Register -------- */ -#define I2SC_IDR_RXRDY (0x1u << 1) /**< \brief (I2SC_IDR) Receiver Ready Interrupt Disable */ -#define I2SC_IDR_RXOR (0x1u << 2) /**< \brief (I2SC_IDR) Receiver Overrun Interrupt Disable */ -#define I2SC_IDR_ENDRX (0x1u << 3) /**< \brief (I2SC_IDR) End of Reception Interrupt Disable */ -#define I2SC_IDR_TXRDY (0x1u << 5) /**< \brief (I2SC_IDR) Transmit Ready Interrupt Disable */ -#define I2SC_IDR_TXUR (0x1u << 6) /**< \brief (I2SC_IDR) Transmit Underflow Interrupt Disable */ -#define I2SC_IDR_ENDTX (0x1u << 7) /**< \brief (I2SC_IDR) End of Transmission Interrupt Disable */ -#define I2SC_IDR_RXFULL (0x1u << 19) /**< \brief (I2SC_IDR) Receive Buffer Full Interrupt Disable */ -#define I2SC_IDR_TXEMPTY (0x1u << 31) /**< \brief (I2SC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- I2SC_IMR : (I2SC Offset: 0x1C) Interrupt Mask Register -------- */ -#define I2SC_IMR_RXRDY (0x1u << 1) /**< \brief (I2SC_IMR) Receiver Ready Interrupt Disable */ -#define I2SC_IMR_RXOR (0x1u << 2) /**< \brief (I2SC_IMR) Receiver Overrun Interrupt Disable */ -#define I2SC_IMR_ENDRX (0x1u << 3) /**< \brief (I2SC_IMR) End of Reception Interrupt Disable */ -#define I2SC_IMR_TXRDY (0x1u << 5) /**< \brief (I2SC_IMR) Transmit Ready Interrupt Disable */ -#define I2SC_IMR_TXUR (0x1u << 6) /**< \brief (I2SC_IMR) Transmit Underflow Interrupt Disable */ -#define I2SC_IMR_ENDTX (0x1u << 7) /**< \brief (I2SC_IMR) End of Transmission Interrupt Disable */ -#define I2SC_IMR_RXFULL (0x1u << 19) /**< \brief (I2SC_IMR) Receive Buffer Full Interrupt Disable */ -#define I2SC_IMR_TXEMPTY (0x1u << 31) /**< \brief (I2SC_IMR) Transmit Buffer Empty Interrupt Disable */ -/* -------- I2SC_RHR : (I2SC Offset: 0x20) Receiver Holding Register -------- */ -#define I2SC_RHR_RHR_Pos 0 -#define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos) /**< \brief (I2SC_RHR) Receiver Holding Register */ -/* -------- I2SC_THR : (I2SC Offset: 0x24) Transmitter Holding Register -------- */ -#define I2SC_THR_THR_Pos 0 -#define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos) /**< \brief (I2SC_THR) Transmitter Holding Register */ -#define I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos))) -/* -------- I2SC_RPR : (I2SC Offset: 0x100) Receive Pointer Register -------- */ -#define I2SC_RPR_RXPTR_Pos 0 -#define I2SC_RPR_RXPTR_Msk (0xffffffffu << I2SC_RPR_RXPTR_Pos) /**< \brief (I2SC_RPR) Receive Pointer Register */ -#define I2SC_RPR_RXPTR(value) ((I2SC_RPR_RXPTR_Msk & ((value) << I2SC_RPR_RXPTR_Pos))) -/* -------- I2SC_RCR : (I2SC Offset: 0x104) Receive Counter Register -------- */ -#define I2SC_RCR_RXCTR_Pos 0 -#define I2SC_RCR_RXCTR_Msk (0xffffu << I2SC_RCR_RXCTR_Pos) /**< \brief (I2SC_RCR) Receive Counter Register */ -#define I2SC_RCR_RXCTR(value) ((I2SC_RCR_RXCTR_Msk & ((value) << I2SC_RCR_RXCTR_Pos))) -/* -------- I2SC_TPR : (I2SC Offset: 0x108) Transmit Pointer Register -------- */ -#define I2SC_TPR_TXPTR_Pos 0 -#define I2SC_TPR_TXPTR_Msk (0xffffffffu << I2SC_TPR_TXPTR_Pos) /**< \brief (I2SC_TPR) Transmit Counter Register */ -#define I2SC_TPR_TXPTR(value) ((I2SC_TPR_TXPTR_Msk & ((value) << I2SC_TPR_TXPTR_Pos))) -/* -------- I2SC_TCR : (I2SC Offset: 0x10C) Transmit Counter Register -------- */ -#define I2SC_TCR_TXCTR_Pos 0 -#define I2SC_TCR_TXCTR_Msk (0xffffu << I2SC_TCR_TXCTR_Pos) /**< \brief (I2SC_TCR) Transmit Counter Register */ -#define I2SC_TCR_TXCTR(value) ((I2SC_TCR_TXCTR_Msk & ((value) << I2SC_TCR_TXCTR_Pos))) -/* -------- I2SC_RNPR : (I2SC Offset: 0x110) Receive Next Pointer Register -------- */ -#define I2SC_RNPR_RXNPTR_Pos 0 -#define I2SC_RNPR_RXNPTR_Msk (0xffffffffu << I2SC_RNPR_RXNPTR_Pos) /**< \brief (I2SC_RNPR) Receive Next Pointer */ -#define I2SC_RNPR_RXNPTR(value) ((I2SC_RNPR_RXNPTR_Msk & ((value) << I2SC_RNPR_RXNPTR_Pos))) -/* -------- I2SC_RNCR : (I2SC Offset: 0x114) Receive Next Counter Register -------- */ -#define I2SC_RNCR_RXNCTR_Pos 0 -#define I2SC_RNCR_RXNCTR_Msk (0xffffu << I2SC_RNCR_RXNCTR_Pos) /**< \brief (I2SC_RNCR) Receive Next Counter */ -#define I2SC_RNCR_RXNCTR(value) ((I2SC_RNCR_RXNCTR_Msk & ((value) << I2SC_RNCR_RXNCTR_Pos))) -/* -------- I2SC_TNPR : (I2SC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define I2SC_TNPR_TXNPTR_Pos 0 -#define I2SC_TNPR_TXNPTR_Msk (0xffffffffu << I2SC_TNPR_TXNPTR_Pos) /**< \brief (I2SC_TNPR) Transmit Next Pointer */ -#define I2SC_TNPR_TXNPTR(value) ((I2SC_TNPR_TXNPTR_Msk & ((value) << I2SC_TNPR_TXNPTR_Pos))) -/* -------- I2SC_TNCR : (I2SC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define I2SC_TNCR_TXNCTR_Pos 0 -#define I2SC_TNCR_TXNCTR_Msk (0xffffu << I2SC_TNCR_TXNCTR_Pos) /**< \brief (I2SC_TNCR) Transmit Counter Next */ -#define I2SC_TNCR_TXNCTR(value) ((I2SC_TNCR_TXNCTR_Msk & ((value) << I2SC_TNCR_TXNCTR_Pos))) -/* -------- I2SC_PTCR : (I2SC Offset: 0x120) Transfer Control Register -------- */ -#define I2SC_PTCR_RXTEN (0x1u << 0) /**< \brief (I2SC_PTCR) Receiver Transfer Enable */ -#define I2SC_PTCR_RXTDIS (0x1u << 1) /**< \brief (I2SC_PTCR) Receiver Transfer Disable */ -#define I2SC_PTCR_TXTEN (0x1u << 8) /**< \brief (I2SC_PTCR) Transmitter Transfer Enable */ -#define I2SC_PTCR_TXTDIS (0x1u << 9) /**< \brief (I2SC_PTCR) Transmitter Transfer Disable */ -#define I2SC_PTCR_RXCBEN (0x1u << 16) /**< \brief (I2SC_PTCR) Receiver Circular Buffer Enable */ -#define I2SC_PTCR_RXCBDIS (0x1u << 17) /**< \brief (I2SC_PTCR) Receiver Circular Buffer Disable */ -#define I2SC_PTCR_TXCBEN (0x1u << 18) /**< \brief (I2SC_PTCR) Transmitter Circular Buffer Enable */ -#define I2SC_PTCR_TXCBDIS (0x1u << 19) /**< \brief (I2SC_PTCR) Transmitter Circular Buffer Disable */ -#define I2SC_PTCR_ERRCLR (0x1u << 24) /**< \brief (I2SC_PTCR) Transfer Bus Error Clear */ -/* -------- I2SC_PTSR : (I2SC Offset: 0x124) Transfer Status Register -------- */ -#define I2SC_PTSR_RXTEN (0x1u << 0) /**< \brief (I2SC_PTSR) Receiver Transfer Enable */ -#define I2SC_PTSR_TXTEN (0x1u << 8) /**< \brief (I2SC_PTSR) Transmitter Transfer Enable */ -#define I2SC_PTSR_RXCBEN (0x1u << 16) /**< \brief (I2SC_PTSR) Receiver Transfer Enable */ -#define I2SC_PTSR_TXCBEN (0x1u << 18) /**< \brief (I2SC_PTSR) Transmitter Transfer Enable */ -#define I2SC_PTSR_ERR (0x1u << 24) /**< \brief (I2SC_PTSR) Transfer Bus Error (clear on read) */ - -/*@}*/ - - -#endif /* _SAMG55_I2SC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_matrix.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_matrix.h deleted file mode 100644 index 4fd3330b332..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_matrix.h +++ /dev/null @@ -1,216 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_MATRIX_COMPONENT_ -#define _SAMG55_MATRIX_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup SAMG55_MATRIX AHB Bus Matrix */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Matrix hardware registers */ -typedef struct { - __IO uint32_t MATRIX_MCFG[3]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - __I uint32_t Reserved1[13]; - __IO uint32_t MATRIX_SCFG[4]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - __I uint32_t Reserved2[12]; - __IO uint32_t MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - __I uint32_t Reserved3[1]; - __IO uint32_t MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - __I uint32_t Reserved4[1]; - __IO uint32_t MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - __I uint32_t Reserved5[1]; - __IO uint32_t MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - __I uint32_t Reserved6[1]; - __I uint32_t Reserved7[28]; - __IO uint32_t CCFG_RDMMEM; /**< \brief (Matrix Offset: 0x0110) Embedded Memories Read Margin Values Register */ - __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration Register */ - __IO uint32_t CCFG_DYNCKG; /**< \brief (Matrix Offset: 0x0118) Dynamic Clock Gating Register */ - __IO uint32_t CCFG_I2SCLKSEL; /**< \brief (Matrix Offset: 0x011C) I2S Clock Source Selection Register */ - __IO uint32_t CCFG_USBMR; /**< \brief (Matrix Offset: 0x0120) USB Management Register */ - __I uint32_t Reserved8[48]; - __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protection Mode Register */ - __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protection Status Register */ -} Matrix; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- MATRIX_MCFG[3] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT_Pos 0 -#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[3]) Undefined Length Burst Type */ -#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) -#define MATRIX_MCFG_ULBT_INFINITE (0x0u << 0) /**< \brief (MATRIX_MCFG[3]) No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. */ -#define MATRIX_MCFG_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG[3]) The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. */ -#define MATRIX_MCFG_ULBT_FOUR_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG[3]) The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. */ -#define MATRIX_MCFG_ULBT_EIGHT_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG[3]) The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. */ -#define MATRIX_MCFG_ULBT_SIXTEEN_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG[3]) The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. */ -/* -------- MATRIX_SCFG[4] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 -#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[4]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) -#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 -#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[4]) Default Master Type */ -#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) -#define MATRIX_SCFG_DEFMSTR_TYPE_NO_DEFAULT (0x0u << 16) /**< \brief (MATRIX_SCFG[4]) At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. */ -#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[4]) At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. */ -#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[4]) At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. */ -#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 -#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[4]) Fixed Default Master */ -#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) -#define MATRIX_SCFG_ARBT_Pos 24 -#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[4]) Arbitration Type */ -#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos))) -#define MATRIX_SCFG_ARBT_ROUND_ROBIN (0x0u << 24) /**< \brief (MATRIX_SCFG[4]) Round-robin arbitration */ -#define MATRIX_SCFG_ARBT_FIXED_PRIORITY (0x1u << 24) /**< \brief (MATRIX_SCFG[4]) Fixed priority arbitration */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR_Pos 0 -#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) -#define MATRIX_PRAS0_M1PR_Pos 4 -#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) -#define MATRIX_PRAS0_M2PR_Pos 8 -#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) -#define MATRIX_PRAS0_M3PR_Pos 12 -#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR_Pos 0 -#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) -#define MATRIX_PRAS1_M1PR_Pos 4 -#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) -#define MATRIX_PRAS1_M2PR_Pos 8 -#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) -#define MATRIX_PRAS1_M3PR_Pos 12 -#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR_Pos 0 -#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) -#define MATRIX_PRAS2_M1PR_Pos 4 -#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) -#define MATRIX_PRAS2_M2PR_Pos 8 -#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) -#define MATRIX_PRAS2_M3PR_Pos 12 -#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR_Pos 0 -#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) -#define MATRIX_PRAS3_M1PR_Pos 4 -#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) -#define MATRIX_PRAS3_M2PR_Pos 8 -#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) -#define MATRIX_PRAS3_M3PR_Pos 12 -#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) -/* -------- CCFG_RDMMEM : (MATRIX Offset: 0x0110) Embedded Memories Read Margin Values Register -------- */ -#define CCFG_RDMMEM_READ_MARGIN_ROM_Pos 0 -#define CCFG_RDMMEM_READ_MARGIN_ROM_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_ROM_Pos) /**< \brief (CCFG_RDMMEM) ROM Read Margin Value Selection */ -#define CCFG_RDMMEM_READ_MARGIN_ROM(value) ((CCFG_RDMMEM_READ_MARGIN_ROM_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_ROM_Pos))) -#define CCFG_RDMMEM_READ_MARGIN_DPRAM_Pos 4 -#define CCFG_RDMMEM_READ_MARGIN_DPRAM_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_DPRAM_Pos) /**< \brief (CCFG_RDMMEM) DPRAM Read Margin Value Selection */ -#define CCFG_RDMMEM_READ_MARGIN_DPRAM(value) ((CCFG_RDMMEM_READ_MARGIN_DPRAM_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_DPRAM_Pos))) -#define CCFG_RDMMEM_READ_MARGIN_RAM32k_Pos 8 -#define CCFG_RDMMEM_READ_MARGIN_RAM32k_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_RAM32k_Pos) /**< \brief (CCFG_RDMMEM) RAM32k Read Margin Value Selection */ -#define CCFG_RDMMEM_READ_MARGIN_RAM32k(value) ((CCFG_RDMMEM_READ_MARGIN_RAM32k_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_RAM32k_Pos))) -#define CCFG_RDMMEM_READ_MARGIN_RAM16k_Pos 12 -#define CCFG_RDMMEM_READ_MARGIN_RAM16k_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_RAM16k_Pos) /**< \brief (CCFG_RDMMEM) RAM16k Read Margin Value Selection */ -#define CCFG_RDMMEM_READ_MARGIN_RAM16k(value) ((CCFG_RDMMEM_READ_MARGIN_RAM16k_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_RAM16k_Pos))) -#define CCFG_RDMMEM_READ_MARGIN_RAM8k_Pos 16 -#define CCFG_RDMMEM_READ_MARGIN_RAM8k_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_RAM8k_Pos) /**< \brief (CCFG_RDMMEM) RAM8k Read Margin Value Selection */ -#define CCFG_RDMMEM_READ_MARGIN_RAM8k(value) ((CCFG_RDMMEM_READ_MARGIN_RAM8k_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_RAM8k_Pos))) -#define CCFG_RDMMEM_READ_MARGIN_RAM4k_Pos 20 -#define CCFG_RDMMEM_READ_MARGIN_RAM4k_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_RAM4k_Pos) /**< \brief (CCFG_RDMMEM) RAM4k Read Margin Value Selection */ -#define CCFG_RDMMEM_READ_MARGIN_RAM4k(value) ((CCFG_RDMMEM_READ_MARGIN_RAM4k_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_RAM4k_Pos))) -#define CCFG_RDMMEM_READ_MARGIN_REGFILE0_Pos 24 -#define CCFG_RDMMEM_READ_MARGIN_REGFILE0_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_REGFILE0_Pos) /**< \brief (CCFG_RDMMEM) REGFILE0 Read Margin Value Selection */ -#define CCFG_RDMMEM_READ_MARGIN_REGFILE0(value) ((CCFG_RDMMEM_READ_MARGIN_REGFILE0_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_REGFILE0_Pos))) -#define CCFG_RDMMEM_READ_MARGIN_REGFILE1_Pos 28 -#define CCFG_RDMMEM_READ_MARGIN_REGFILE1_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_REGFILE1_Pos) /**< \brief (CCFG_RDMMEM) REGFILE1 Read Margin Value Selection */ -#define CCFG_RDMMEM_READ_MARGIN_REGFILE1(value) ((CCFG_RDMMEM_READ_MARGIN_REGFILE1_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_REGFILE1_Pos))) -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PA21 or DM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PA22 or DP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_DYNCKG : (MATRIX Offset: 0x0118) Dynamic Clock Gating Register -------- */ -#define CCFG_DYNCKG_MATCKG (0x1u << 0) /**< \brief (CCFG_DYNCKG) MATRIX Dynamic Clock Gating */ -#define CCFG_DYNCKG_BRIDCKG (0x1u << 1) /**< \brief (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable */ -#define CCFG_DYNCKG_EFCCKG (0x1u << 2) /**< \brief (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable */ -/* -------- CCFG_I2SCLKSEL : (MATRIX Offset: 0x011C) I2S Clock Source Selection Register -------- */ -#define CCFG_I2SCLKSEL_CLKSEL0 (0x1u << 0) /**< \brief (CCFG_I2SCLKSEL) I2S0 clock source */ -#define CCFG_I2SCLKSEL_CLKSEL1 (0x1u << 1) /**< \brief (CCFG_I2SCLKSEL) I2S1 clock source */ -/* -------- CCFG_USBMR : (MATRIX Offset: 0x0120) USB Management Register -------- */ -#define CCFG_USBMR_DEVICE (0x1u << 0) /**< \brief (CCFG_USBMR) USB device mode */ -#define CCFG_USBMR_USBHTSSC (0x1u << 1) /**< \brief (CCFG_USBMR) USB Transceiver Suspend Software Control */ -#define CCFG_USBMR_USBHTSC (0x1u << 2) /**< \brief (CCFG_USBMR) USB Host Transceiver Suspend Control */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protection Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ -#define MATRIX_WPMR_WPKEY_Pos 8 -#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ -#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protection Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ -#define MATRIX_WPSR_WPVSRC_Pos 8 -#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ - -/*@}*/ - - -#endif /* _SAMG55_MATRIX_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_mem2mem.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_mem2mem.h deleted file mode 100644 index a7ea4463cba..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_mem2mem.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_MEM2MEM_COMPONENT_ -#define _SAMG55_MEM2MEM_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Memory to Memory */ -/* ============================================================================= */ -/** \addtogroup SAMG55_MEM2MEM Memory to Memory */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Mem2mem hardware registers */ -typedef struct { - __IO uint32_t MEM2MEM_THR; /**< \brief (Mem2mem Offset: 0x00) Memory to Memory Transfer Holding Register */ - __IO uint32_t MEM2MEM_MR; /**< \brief (Mem2mem Offset: 0x04) Memory to Memory Mode Register */ - __O uint32_t MEM2MEM_IER; /**< \brief (Mem2mem Offset: 0x08) Memory to Memory Interrupt Enable Register */ - __O uint32_t MEM2MEM_IDR; /**< \brief (Mem2mem Offset: 0x0C) Memory to Memory Interrupt Disable Register */ - __I uint32_t MEM2MEM_IMR; /**< \brief (Mem2mem Offset: 0x10) Memory to Memory Interrupt Mask Register */ - __I uint32_t MEM2MEM_ISR; /**< \brief (Mem2mem Offset: 0x14) Memory to Memory Interrupt Status Register */ - __I uint32_t Reserved1[58]; - __IO uint32_t MEM2MEM_RPR; /**< \brief (Mem2mem Offset: 0x100) Receive Pointer Register */ - __IO uint32_t MEM2MEM_RCR; /**< \brief (Mem2mem Offset: 0x104) Receive Counter Register */ - __IO uint32_t MEM2MEM_TPR; /**< \brief (Mem2mem Offset: 0x108) Transmit Pointer Register */ - __IO uint32_t MEM2MEM_TCR; /**< \brief (Mem2mem Offset: 0x10C) Transmit Counter Register */ - __IO uint32_t MEM2MEM_RNPR; /**< \brief (Mem2mem Offset: 0x110) Receive Next Pointer Register */ - __IO uint32_t MEM2MEM_RNCR; /**< \brief (Mem2mem Offset: 0x114) Receive Next Counter Register */ - __IO uint32_t MEM2MEM_TNPR; /**< \brief (Mem2mem Offset: 0x118) Transmit Next Pointer Register */ - __IO uint32_t MEM2MEM_TNCR; /**< \brief (Mem2mem Offset: 0x11C) Transmit Next Counter Register */ - __O uint32_t MEM2MEM_PTCR; /**< \brief (Mem2mem Offset: 0x120) Transfer Control Register */ - __I uint32_t MEM2MEM_PTSR; /**< \brief (Mem2mem Offset: 0x124) Transfer Status Register */ -} Mem2mem; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- MEM2MEM_THR : (MEM2MEM Offset: 0x00) Memory to Memory Transfer Holding Register -------- */ -#define MEM2MEM_THR_THDATA_Pos 0 -#define MEM2MEM_THR_THDATA_Msk (0xffffffffu << MEM2MEM_THR_THDATA_Pos) /**< \brief (MEM2MEM_THR) Transfer Holding Data */ -#define MEM2MEM_THR_THDATA(value) ((MEM2MEM_THR_THDATA_Msk & ((value) << MEM2MEM_THR_THDATA_Pos))) -/* -------- MEM2MEM_MR : (MEM2MEM Offset: 0x04) Memory to Memory Mode Register -------- */ -#define MEM2MEM_MR_TSIZE_Pos 0 -#define MEM2MEM_MR_TSIZE_Msk (0x3u << MEM2MEM_MR_TSIZE_Pos) /**< \brief (MEM2MEM_MR) Transfer Size */ -#define MEM2MEM_MR_TSIZE_T_8BIT (0x0u << 0) /**< \brief (MEM2MEM_MR) The buffer size is defined in byte. */ -#define MEM2MEM_MR_TSIZE_T_16BIT (0x1u << 0) /**< \brief (MEM2MEM_MR) The buffer size is defined in half-word (16-bit). */ -#define MEM2MEM_MR_TSIZE_T_32BIT (0x2u << 0) /**< \brief (MEM2MEM_MR) The buffer size is defined in word (32-bit). Default value. */ -/* -------- MEM2MEM_IER : (MEM2MEM Offset: 0x08) Memory to Memory Interrupt Enable Register -------- */ -#define MEM2MEM_IER_RXEND (0x1u << 0) /**< \brief (MEM2MEM_IER) End of Transfer Interrupt Enable */ -#define MEM2MEM_IER_RXBUFF (0x1u << 1) /**< \brief (MEM2MEM_IER) Buffer Full Interrupt Enable */ -/* -------- MEM2MEM_IDR : (MEM2MEM Offset: 0x0C) Memory to Memory Interrupt Disable Register -------- */ -#define MEM2MEM_IDR_RXEND (0x1u << 0) /**< \brief (MEM2MEM_IDR) End of Transfer Interrupt Disable */ -#define MEM2MEM_IDR_RXBUFF (0x1u << 1) /**< \brief (MEM2MEM_IDR) Buffer Full Interrupt Disable */ -/* -------- MEM2MEM_IMR : (MEM2MEM Offset: 0x10) Memory to Memory Interrupt Mask Register -------- */ -#define MEM2MEM_IMR_RXEND (0x1u << 0) /**< \brief (MEM2MEM_IMR) End of Transfer Interrupt Mask */ -#define MEM2MEM_IMR_RXBUFF (0x1u << 1) /**< \brief (MEM2MEM_IMR) Buffer Full Interrupt Mask */ -/* -------- MEM2MEM_ISR : (MEM2MEM Offset: 0x14) Memory to Memory Interrupt Status Register -------- */ -#define MEM2MEM_ISR_RXEND (0x1u << 0) /**< \brief (MEM2MEM_ISR) End of Transfer */ -#define MEM2MEM_ISR_RXBUFF (0x1u << 1) /**< \brief (MEM2MEM_ISR) Buffer Full */ -/* -------- MEM2MEM_RPR : (MEM2MEM Offset: 0x100) Receive Pointer Register -------- */ -#define MEM2MEM_RPR_RXPTR_Pos 0 -#define MEM2MEM_RPR_RXPTR_Msk (0xffffffffu << MEM2MEM_RPR_RXPTR_Pos) /**< \brief (MEM2MEM_RPR) Receive Pointer Register */ -#define MEM2MEM_RPR_RXPTR(value) ((MEM2MEM_RPR_RXPTR_Msk & ((value) << MEM2MEM_RPR_RXPTR_Pos))) -/* -------- MEM2MEM_RCR : (MEM2MEM Offset: 0x104) Receive Counter Register -------- */ -#define MEM2MEM_RCR_RXCTR_Pos 0 -#define MEM2MEM_RCR_RXCTR_Msk (0xffffu << MEM2MEM_RCR_RXCTR_Pos) /**< \brief (MEM2MEM_RCR) Receive Counter Register */ -#define MEM2MEM_RCR_RXCTR(value) ((MEM2MEM_RCR_RXCTR_Msk & ((value) << MEM2MEM_RCR_RXCTR_Pos))) -/* -------- MEM2MEM_TPR : (MEM2MEM Offset: 0x108) Transmit Pointer Register -------- */ -#define MEM2MEM_TPR_TXPTR_Pos 0 -#define MEM2MEM_TPR_TXPTR_Msk (0xffffffffu << MEM2MEM_TPR_TXPTR_Pos) /**< \brief (MEM2MEM_TPR) Transmit Counter Register */ -#define MEM2MEM_TPR_TXPTR(value) ((MEM2MEM_TPR_TXPTR_Msk & ((value) << MEM2MEM_TPR_TXPTR_Pos))) -/* -------- MEM2MEM_TCR : (MEM2MEM Offset: 0x10C) Transmit Counter Register -------- */ -#define MEM2MEM_TCR_TXCTR_Pos 0 -#define MEM2MEM_TCR_TXCTR_Msk (0xffffu << MEM2MEM_TCR_TXCTR_Pos) /**< \brief (MEM2MEM_TCR) Transmit Counter Register */ -#define MEM2MEM_TCR_TXCTR(value) ((MEM2MEM_TCR_TXCTR_Msk & ((value) << MEM2MEM_TCR_TXCTR_Pos))) -/* -------- MEM2MEM_RNPR : (MEM2MEM Offset: 0x110) Receive Next Pointer Register -------- */ -#define MEM2MEM_RNPR_RXNPTR_Pos 0 -#define MEM2MEM_RNPR_RXNPTR_Msk (0xffffffffu << MEM2MEM_RNPR_RXNPTR_Pos) /**< \brief (MEM2MEM_RNPR) Receive Next Pointer */ -#define MEM2MEM_RNPR_RXNPTR(value) ((MEM2MEM_RNPR_RXNPTR_Msk & ((value) << MEM2MEM_RNPR_RXNPTR_Pos))) -/* -------- MEM2MEM_RNCR : (MEM2MEM Offset: 0x114) Receive Next Counter Register -------- */ -#define MEM2MEM_RNCR_RXNCTR_Pos 0 -#define MEM2MEM_RNCR_RXNCTR_Msk (0xffffu << MEM2MEM_RNCR_RXNCTR_Pos) /**< \brief (MEM2MEM_RNCR) Receive Next Counter */ -#define MEM2MEM_RNCR_RXNCTR(value) ((MEM2MEM_RNCR_RXNCTR_Msk & ((value) << MEM2MEM_RNCR_RXNCTR_Pos))) -/* -------- MEM2MEM_TNPR : (MEM2MEM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define MEM2MEM_TNPR_TXNPTR_Pos 0 -#define MEM2MEM_TNPR_TXNPTR_Msk (0xffffffffu << MEM2MEM_TNPR_TXNPTR_Pos) /**< \brief (MEM2MEM_TNPR) Transmit Next Pointer */ -#define MEM2MEM_TNPR_TXNPTR(value) ((MEM2MEM_TNPR_TXNPTR_Msk & ((value) << MEM2MEM_TNPR_TXNPTR_Pos))) -/* -------- MEM2MEM_TNCR : (MEM2MEM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define MEM2MEM_TNCR_TXNCTR_Pos 0 -#define MEM2MEM_TNCR_TXNCTR_Msk (0xffffu << MEM2MEM_TNCR_TXNCTR_Pos) /**< \brief (MEM2MEM_TNCR) Transmit Counter Next */ -#define MEM2MEM_TNCR_TXNCTR(value) ((MEM2MEM_TNCR_TXNCTR_Msk & ((value) << MEM2MEM_TNCR_TXNCTR_Pos))) -/* -------- MEM2MEM_PTCR : (MEM2MEM Offset: 0x120) Transfer Control Register -------- */ -#define MEM2MEM_PTCR_RXTEN (0x1u << 0) /**< \brief (MEM2MEM_PTCR) Receiver Transfer Enable */ -#define MEM2MEM_PTCR_RXTDIS (0x1u << 1) /**< \brief (MEM2MEM_PTCR) Receiver Transfer Disable */ -#define MEM2MEM_PTCR_TXTEN (0x1u << 8) /**< \brief (MEM2MEM_PTCR) Transmitter Transfer Enable */ -#define MEM2MEM_PTCR_TXTDIS (0x1u << 9) /**< \brief (MEM2MEM_PTCR) Transmitter Transfer Disable */ -#define MEM2MEM_PTCR_RXCBEN (0x1u << 16) /**< \brief (MEM2MEM_PTCR) Receiver Circular Buffer Enable */ -#define MEM2MEM_PTCR_RXCBDIS (0x1u << 17) /**< \brief (MEM2MEM_PTCR) Receiver Circular Buffer Disable */ -#define MEM2MEM_PTCR_TXCBEN (0x1u << 18) /**< \brief (MEM2MEM_PTCR) Transmitter Circular Buffer Enable */ -#define MEM2MEM_PTCR_TXCBDIS (0x1u << 19) /**< \brief (MEM2MEM_PTCR) Transmitter Circular Buffer Disable */ -#define MEM2MEM_PTCR_ERRCLR (0x1u << 24) /**< \brief (MEM2MEM_PTCR) Transfer Bus Error Clear */ -/* -------- MEM2MEM_PTSR : (MEM2MEM Offset: 0x124) Transfer Status Register -------- */ -#define MEM2MEM_PTSR_RXTEN (0x1u << 0) /**< \brief (MEM2MEM_PTSR) Receiver Transfer Enable */ -#define MEM2MEM_PTSR_TXTEN (0x1u << 8) /**< \brief (MEM2MEM_PTSR) Transmitter Transfer Enable */ -#define MEM2MEM_PTSR_RXCBEN (0x1u << 16) /**< \brief (MEM2MEM_PTSR) Receiver Transfer Enable */ -#define MEM2MEM_PTSR_TXCBEN (0x1u << 18) /**< \brief (MEM2MEM_PTSR) Transmitter Transfer Enable */ -#define MEM2MEM_PTSR_ERR (0x1u << 24) /**< \brief (MEM2MEM_PTSR) Transfer Bus Error (clear on read) */ - -/*@}*/ - - -#endif /* _SAMG55_MEM2MEM_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pdc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pdc.h deleted file mode 100644 index 115d851624f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pdc.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PDC_COMPONENT_ -#define _SAMG55_PDC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_PDC Peripheral DMA Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Pdc hardware registers */ -typedef struct { - __IO uint32_t PERIPH_RPR; /**< \brief (Pdc Offset: 0x00) Receive Pointer Register */ - __IO uint32_t PERIPH_RCR; /**< \brief (Pdc Offset: 0x04) Receive Counter Register */ - __IO uint32_t PERIPH_TPR; /**< \brief (Pdc Offset: 0x08) Transmit Pointer Register */ - __IO uint32_t PERIPH_TCR; /**< \brief (Pdc Offset: 0x0C) Transmit Counter Register */ - __IO uint32_t PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */ - __IO uint32_t PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */ - __IO uint32_t PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */ - __IO uint32_t PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */ - __O uint32_t PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */ - __I uint32_t PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */ -} Pdc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- PERIPH_RPR : (PDC Offset: 0x00) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR_Pos 0 -#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) -/* -------- PERIPH_RCR : (PDC Offset: 0x04) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR_Pos 0 -#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */ -#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) -/* -------- PERIPH_TPR : (PDC Offset: 0x08) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR_Pos 0 -#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) -/* -------- PERIPH_TCR : (PDC Offset: 0x0C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR_Pos 0 -#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) -/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR_Pos 0 -#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) -/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR_Pos 0 -#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) -/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR_Pos 0 -#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) -/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR_Pos 0 -#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) -/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -#define PERIPH_PTCR_RXCBEN (0x1u << 16) /**< \brief (PERIPH_PTCR) Receiver Circular Buffer Enable */ -#define PERIPH_PTCR_RXCBDIS (0x1u << 17) /**< \brief (PERIPH_PTCR) Receiver Circular Buffer Disable */ -#define PERIPH_PTCR_TXCBEN (0x1u << 18) /**< \brief (PERIPH_PTCR) Transmitter Circular Buffer Enable */ -#define PERIPH_PTCR_TXCBDIS (0x1u << 19) /**< \brief (PERIPH_PTCR) Transmitter Circular Buffer Disable */ -#define PERIPH_PTCR_ERRCLR (0x1u << 24) /**< \brief (PERIPH_PTCR) Transfer Bus Error Clear */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ -#define PERIPH_PTSR_RXCBEN (0x1u << 16) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXCBEN (0x1u << 18) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ -#define PERIPH_PTSR_ERR (0x1u << 24) /**< \brief (PERIPH_PTSR) Transfer Bus Error (clear on read) */ - -/*@}*/ - - -#endif /* _SAMG55_PDC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pdmic.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pdmic.h deleted file mode 100644 index 708f4c57a72..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pdmic.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PDMIC_COMPONENT_ -#define _SAMG55_PDMIC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Density Modulation Interface Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_PDMIC Pulse Density Modulation Interface Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Pdmic hardware registers */ -typedef struct { - __IO uint32_t PDMIC_CR; /**< \brief (Pdmic Offset: 0x00) Control Register */ - __IO uint32_t PDMIC_MR; /**< \brief (Pdmic Offset: 0x04) Mode Register */ - __I uint32_t Reserved1[3]; - __I uint32_t PDMIC_CDR; /**< \brief (Pdmic Offset: 0x14) Converted Data Register */ - __O uint32_t PDMIC_IER; /**< \brief (Pdmic Offset: 0x18) Interrupt Enable Register */ - __O uint32_t PDMIC_IDR; /**< \brief (Pdmic Offset: 0x1C) Interrupt Disable Register */ - __I uint32_t PDMIC_IMR; /**< \brief (Pdmic Offset: 0x20) Interrupt Mask Register */ - __I uint32_t PDMIC_ISR; /**< \brief (Pdmic Offset: 0x24) Interrupt Status Register */ - __I uint32_t Reserved2[12]; - __IO uint32_t PDMIC_DSPR0; /**< \brief (Pdmic Offset: 0x58) DSP Configuration Register 0 */ - __IO uint32_t PDMIC_DSPR1; /**< \brief (Pdmic Offset: 0x5C) DSP Configuration Register 1 */ - __I uint32_t Reserved3[33]; - __IO uint32_t PDMIC_WPMR; /**< \brief (Pdmic Offset: 0xE4) Write Protection Mode Register */ - __I uint32_t PDMIC_WPSR; /**< \brief (Pdmic Offset: 0xE8) Write Protection Status Register */ - __I uint32_t Reserved4[5]; - __IO uint32_t PDMIC_RPR; /**< \brief (Pdmic Offset: 0x100) Receive Pointer Register */ - __IO uint32_t PDMIC_RCR; /**< \brief (Pdmic Offset: 0x104) Receive Counter Register */ - __I uint32_t Reserved5[2]; - __IO uint32_t PDMIC_RNPR; /**< \brief (Pdmic Offset: 0x110) Receive Next Pointer Register */ - __IO uint32_t PDMIC_RNCR; /**< \brief (Pdmic Offset: 0x114) Receive Next Counter Register */ - __I uint32_t Reserved6[2]; - __O uint32_t PDMIC_PTCR; /**< \brief (Pdmic Offset: 0x120) Transfer Control Register */ - __I uint32_t PDMIC_PTSR; /**< \brief (Pdmic Offset: 0x124) Transfer Status Register */ -} Pdmic; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- PDMIC_CR : (PDMIC Offset: 0x00) Control Register -------- */ -#define PDMIC_CR_SWRST (0x1u << 0) /**< \brief (PDMIC_CR) Software Reset */ -#define PDMIC_CR_ENPDM (0x1u << 4) /**< \brief (PDMIC_CR) Enable PDM */ -/* -------- PDMIC_MR : (PDMIC Offset: 0x04) Mode Register -------- */ -#define PDMIC_MR_PRESCAL_Pos 8 -#define PDMIC_MR_PRESCAL_Msk (0x7fu << PDMIC_MR_PRESCAL_Pos) /**< \brief (PDMIC_MR) Prescaler Rate Selection */ -#define PDMIC_MR_PRESCAL(value) ((PDMIC_MR_PRESCAL_Msk & ((value) << PDMIC_MR_PRESCAL_Pos))) -/* -------- PDMIC_CDR : (PDMIC Offset: 0x14) Converted Data Register -------- */ -#define PDMIC_CDR_DATA_Pos 0 -#define PDMIC_CDR_DATA_Msk (0xffffffffu << PDMIC_CDR_DATA_Pos) /**< \brief (PDMIC_CDR) Data Converted */ -/* -------- PDMIC_IER : (PDMIC Offset: 0x18) Interrupt Enable Register -------- */ -#define PDMIC_IER_DRDY (0x1u << 24) /**< \brief (PDMIC_IER) Data Ready Interrupt Enable */ -#define PDMIC_IER_OVRE (0x1u << 25) /**< \brief (PDMIC_IER) Overrun Error Interrupt Enable */ -#define PDMIC_IER_ENDRX (0x1u << 27) /**< \brief (PDMIC_IER) End of Receive Buffer Interrupt Enable */ -#define PDMIC_IER_RXBUFF (0x1u << 28) /**< \brief (PDMIC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- PDMIC_IDR : (PDMIC Offset: 0x1C) Interrupt Disable Register -------- */ -#define PDMIC_IDR_DRDY (0x1u << 24) /**< \brief (PDMIC_IDR) Data Ready Interrupt Disable */ -#define PDMIC_IDR_OVRE (0x1u << 25) /**< \brief (PDMIC_IDR) General Overrun Error Interrupt Disable */ -#define PDMIC_IDR_ENDRX (0x1u << 27) /**< \brief (PDMIC_IDR) End of Receive Buffer Interrupt Disable */ -#define PDMIC_IDR_RXBUFF (0x1u << 28) /**< \brief (PDMIC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- PDMIC_IMR : (PDMIC Offset: 0x20) Interrupt Mask Register -------- */ -#define PDMIC_IMR_DRDY (0x1u << 24) /**< \brief (PDMIC_IMR) Data Ready Interrupt Mask */ -#define PDMIC_IMR_OVRE (0x1u << 25) /**< \brief (PDMIC_IMR) General Overrun Error Interrupt Mask */ -#define PDMIC_IMR_ENDRX (0x1u << 27) /**< \brief (PDMIC_IMR) End of Receive Buffer Interrupt Mask */ -#define PDMIC_IMR_RXBUFF (0x1u << 28) /**< \brief (PDMIC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- PDMIC_ISR : (PDMIC Offset: 0x24) Interrupt Status Register -------- */ -#define PDMIC_ISR_FIFOCNT_Pos 16 -#define PDMIC_ISR_FIFOCNT_Msk (0xffu << PDMIC_ISR_FIFOCNT_Pos) /**< \brief (PDMIC_ISR) FIFO Count */ -#define PDMIC_ISR_DRDY (0x1u << 24) /**< \brief (PDMIC_ISR) Data Ready */ -#define PDMIC_ISR_OVRE (0x1u << 25) /**< \brief (PDMIC_ISR) Overrun Error */ -#define PDMIC_ISR_ENDRX (0x1u << 27) /**< \brief (PDMIC_ISR) End of RX Buffer */ -#define PDMIC_ISR_RXBUFF (0x1u << 28) /**< \brief (PDMIC_ISR) RX Buffer Full */ -/* -------- PDMIC_DSPR0 : (PDMIC Offset: 0x58) DSP Configuration Register 0 -------- */ -#define PDMIC_DSPR0_HPFBYP (0x1u << 1) /**< \brief (PDMIC_DSPR0) High-Pass Filter Bypass */ -#define PDMIC_DSPR0_SINBYP (0x1u << 2) /**< \brief (PDMIC_DSPR0) SINCC Filter Bypass */ -#define PDMIC_DSPR0_SIZE (0x1u << 3) /**< \brief (PDMIC_DSPR0) Data Size */ -#define PDMIC_DSPR0_OSR_Pos 4 -#define PDMIC_DSPR0_OSR_Msk (0x7u << PDMIC_DSPR0_OSR_Pos) /**< \brief (PDMIC_DSPR0) Oversampling Ratio */ -#define PDMIC_DSPR0_OSR_128 (0x0u << 4) /**< \brief (PDMIC_DSPR0) Oversampling ratio is 128 */ -#define PDMIC_DSPR0_OSR_64 (0x1u << 4) /**< \brief (PDMIC_DSPR0) Oversampling ratio is 64 */ -#define PDMIC_DSPR0_SCALE_Pos 8 -#define PDMIC_DSPR0_SCALE_Msk (0xfu << PDMIC_DSPR0_SCALE_Pos) /**< \brief (PDMIC_DSPR0) Data Scale */ -#define PDMIC_DSPR0_SCALE(value) ((PDMIC_DSPR0_SCALE_Msk & ((value) << PDMIC_DSPR0_SCALE_Pos))) -#define PDMIC_DSPR0_SHIFT_Pos 12 -#define PDMIC_DSPR0_SHIFT_Msk (0xfu << PDMIC_DSPR0_SHIFT_Pos) /**< \brief (PDMIC_DSPR0) Data Shift */ -#define PDMIC_DSPR0_SHIFT(value) ((PDMIC_DSPR0_SHIFT_Msk & ((value) << PDMIC_DSPR0_SHIFT_Pos))) -/* -------- PDMIC_DSPR1 : (PDMIC Offset: 0x5C) DSP Configuration Register 1 -------- */ -#define PDMIC_DSPR1_DGAIN_Pos 0 -#define PDMIC_DSPR1_DGAIN_Msk (0x7fffu << PDMIC_DSPR1_DGAIN_Pos) /**< \brief (PDMIC_DSPR1) Gain Correction */ -#define PDMIC_DSPR1_DGAIN(value) ((PDMIC_DSPR1_DGAIN_Msk & ((value) << PDMIC_DSPR1_DGAIN_Pos))) -#define PDMIC_DSPR1_OFFSET_Pos 16 -#define PDMIC_DSPR1_OFFSET_Msk (0xffffu << PDMIC_DSPR1_OFFSET_Pos) /**< \brief (PDMIC_DSPR1) Offset Correction */ -#define PDMIC_DSPR1_OFFSET(value) ((PDMIC_DSPR1_OFFSET_Msk & ((value) << PDMIC_DSPR1_OFFSET_Pos))) -/* -------- PDMIC_WPMR : (PDMIC Offset: 0xE4) Write Protection Mode Register -------- */ -#define PDMIC_WPMR_WPEN (0x1u << 0) /**< \brief (PDMIC_WPMR) Write Protection Enable */ -#define PDMIC_WPMR_WPKEY_Pos 8 -#define PDMIC_WPMR_WPKEY_Msk (0xffffffu << PDMIC_WPMR_WPKEY_Pos) /**< \brief (PDMIC_WPMR) Write Protect Key */ -#define PDMIC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (PDMIC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ -/* -------- PDMIC_WPSR : (PDMIC Offset: 0xE8) Write Protection Status Register -------- */ -#define PDMIC_WPSR_WPVS (0x1u << 0) /**< \brief (PDMIC_WPSR) Write Protection Violation Status */ -#define PDMIC_WPSR_WPVSRC_Pos 8 -#define PDMIC_WPSR_WPVSRC_Msk (0xffffu << PDMIC_WPSR_WPVSRC_Pos) /**< \brief (PDMIC_WPSR) Write Protection Violation Source */ -/* -------- PDMIC_RPR : (PDMIC Offset: 0x100) Receive Pointer Register -------- */ -#define PDMIC_RPR_RXPTR_Pos 0 -#define PDMIC_RPR_RXPTR_Msk (0xffffffffu << PDMIC_RPR_RXPTR_Pos) /**< \brief (PDMIC_RPR) Receive Pointer Register */ -#define PDMIC_RPR_RXPTR(value) ((PDMIC_RPR_RXPTR_Msk & ((value) << PDMIC_RPR_RXPTR_Pos))) -/* -------- PDMIC_RCR : (PDMIC Offset: 0x104) Receive Counter Register -------- */ -#define PDMIC_RCR_RXCTR_Pos 0 -#define PDMIC_RCR_RXCTR_Msk (0xffffu << PDMIC_RCR_RXCTR_Pos) /**< \brief (PDMIC_RCR) Receive Counter Register */ -#define PDMIC_RCR_RXCTR(value) ((PDMIC_RCR_RXCTR_Msk & ((value) << PDMIC_RCR_RXCTR_Pos))) -/* -------- PDMIC_RNPR : (PDMIC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PDMIC_RNPR_RXNPTR_Pos 0 -#define PDMIC_RNPR_RXNPTR_Msk (0xffffffffu << PDMIC_RNPR_RXNPTR_Pos) /**< \brief (PDMIC_RNPR) Receive Next Pointer */ -#define PDMIC_RNPR_RXNPTR(value) ((PDMIC_RNPR_RXNPTR_Msk & ((value) << PDMIC_RNPR_RXNPTR_Pos))) -/* -------- PDMIC_RNCR : (PDMIC Offset: 0x114) Receive Next Counter Register -------- */ -#define PDMIC_RNCR_RXNCTR_Pos 0 -#define PDMIC_RNCR_RXNCTR_Msk (0xffffu << PDMIC_RNCR_RXNCTR_Pos) /**< \brief (PDMIC_RNCR) Receive Next Counter */ -#define PDMIC_RNCR_RXNCTR(value) ((PDMIC_RNCR_RXNCTR_Msk & ((value) << PDMIC_RNCR_RXNCTR_Pos))) -/* -------- PDMIC_PTCR : (PDMIC Offset: 0x120) Transfer Control Register -------- */ -#define PDMIC_PTCR_RXTEN (0x1u << 0) /**< \brief (PDMIC_PTCR) Receiver Transfer Enable */ -#define PDMIC_PTCR_RXTDIS (0x1u << 1) /**< \brief (PDMIC_PTCR) Receiver Transfer Disable */ -#define PDMIC_PTCR_TXTEN (0x1u << 8) /**< \brief (PDMIC_PTCR) Transmitter Transfer Enable */ -#define PDMIC_PTCR_TXTDIS (0x1u << 9) /**< \brief (PDMIC_PTCR) Transmitter Transfer Disable */ -#define PDMIC_PTCR_RXCBEN (0x1u << 16) /**< \brief (PDMIC_PTCR) Receiver Circular Buffer Enable */ -#define PDMIC_PTCR_RXCBDIS (0x1u << 17) /**< \brief (PDMIC_PTCR) Receiver Circular Buffer Disable */ -#define PDMIC_PTCR_TXCBEN (0x1u << 18) /**< \brief (PDMIC_PTCR) Transmitter Circular Buffer Enable */ -#define PDMIC_PTCR_TXCBDIS (0x1u << 19) /**< \brief (PDMIC_PTCR) Transmitter Circular Buffer Disable */ -#define PDMIC_PTCR_ERRCLR (0x1u << 24) /**< \brief (PDMIC_PTCR) Transfer Bus Error Clear */ -/* -------- PDMIC_PTSR : (PDMIC Offset: 0x124) Transfer Status Register -------- */ -#define PDMIC_PTSR_RXTEN (0x1u << 0) /**< \brief (PDMIC_PTSR) Receiver Transfer Enable */ -#define PDMIC_PTSR_TXTEN (0x1u << 8) /**< \brief (PDMIC_PTSR) Transmitter Transfer Enable */ -#define PDMIC_PTSR_RXCBEN (0x1u << 16) /**< \brief (PDMIC_PTSR) Receiver Transfer Enable */ -#define PDMIC_PTSR_TXCBEN (0x1u << 18) /**< \brief (PDMIC_PTSR) Transmitter Transfer Enable */ -#define PDMIC_PTSR_ERR (0x1u << 24) /**< \brief (PDMIC_PTSR) Transfer Bus Error (clear on read) */ - -/*@}*/ - - -#endif /* _SAMG55_PDMIC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pio.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pio.h deleted file mode 100644 index 21b548fdd83..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pio.h +++ /dev/null @@ -1,1555 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PIO_COMPONENT_ -#define _SAMG55_PIO_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_PIO Parallel Input/Output Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Pio hardware registers */ -typedef struct { - __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - __I uint32_t Reserved1[1]; - __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - __I uint32_t Reserved2[1]; - __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - __I uint32_t Reserved3[1]; - __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - __I uint32_t Reserved4[1]; - __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - __I uint32_t Reserved5[1]; - __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - __I uint32_t Reserved6[2]; - __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ - __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ - __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ - __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - __I uint32_t Reserved7[1]; - __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - __I uint32_t Reserved8[1]; - __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ - __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - __I uint32_t Reserved9[1]; - __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - __I uint32_t Reserved10[1]; - __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ - __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ - __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - __I uint32_t Reserved11[2]; - __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ - __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ - __I uint32_t Reserved12[5]; - __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - __I uint32_t Reserved13[3]; - __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0110) I/O Drive Register */ -} Pio; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-Drive Enable */ -#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-Drive Enable */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-Drive Disable */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-Drive Status */ -#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-Drive Status */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ -#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ -#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ -#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ -/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ -#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */ -/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ -#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */ -/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ -#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV_Pos 0 -#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ -#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ -#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ -#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ -#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ -#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ -#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ -#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High-Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ -#define PIO_WPMR_WPKEY_Pos 8 -#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key. */ -#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ -#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ -#define PIO_WPSR_WPVSRC_Pos 8 -#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ -#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ - -/*@}*/ - - -#endif /* _SAMG55_PIO_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pmc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pmc.h deleted file mode 100644 index 3e854d307d8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pmc.h +++ /dev/null @@ -1,593 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PMC_COMPONENT_ -#define _SAMG55_PMC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_PMC Power Management Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Pmc hardware registers */ -typedef struct { - __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - __I uint32_t Reserved1[1]; - __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - __I uint32_t Reserved2[1]; - __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - __IO uint32_t CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ - __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - __I uint32_t Reserved3[1]; - __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - __I uint32_t Reserved4[1]; - __IO uint32_t PMC_PCK[8]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - __I uint32_t Reserved5[26]; - __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ - __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ - __I uint32_t PMC_ADDRSIZE; /**< \brief (Pmc Offset: 0x00EC) Address Size Register */ - __I uint32_t PMC_IPNAME[2]; /**< \brief (Pmc Offset: 0x00F0) IP Name1 Register */ - __I uint32_t PMC_FEATURES; /**< \brief (Pmc Offset: 0x00F8) Features Register */ - __I uint32_t PMC_VERSION; /**< \brief (Pmc Offset: 0x00FC) Version Register */ - __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - __I uint32_t Reserved7[1]; - __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ - __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x114) SleepWalking Enable Register 0 */ - __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x118) SleepWalking Disable Register 0 */ - __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x11C) SleepWalking Status Register 0 */ - __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x120) SleepWalking Activity Status Register 0 */ - __I uint32_t Reserved8[3]; - __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x130) PLL Maximum Multiplier Value Register */ -} Pmc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UHP (0x1u << 6) /**< \brief (PMC_SCER) USB Host Port Clock Enable */ -#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ -#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ -#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ -#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ -#define PMC_SCER_PCK7 (0x1u << 15) /**< \brief (PMC_SCER) Programmable Clock 7 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UHP (0x1u << 6) /**< \brief (PMC_SCDR) USB Host Port Clock Disable */ -#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) */ -#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ -#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ -#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ -#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ -#define PMC_SCDR_PCK7 (0x1u << 15) /**< \brief (PMC_SCDR) Programmable Clock 7 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UHP (0x1u << 6) /**< \brief (PMC_SCSR) USB Host Port Clock Status */ -#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) */ -#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ -#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ -#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ -#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ -#define PMC_SCSR_PCK7 (0x1u << 15) /**< \brief (PMC_SCSR) Programmable Clock 7 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ -#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ -#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ -#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF_Pos 4 -#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCRCF_8_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz (default) */ -#define CKGR_MOR_MOSCRCF_16_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 16 MHz */ -#define CKGR_MOR_MOSCRCF_24_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 24 MHz */ -#define CKGR_MOR_MOSCXTST_Pos 8 -#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) -#define CKGR_MOR_KEY_Pos 16 -#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ -#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ -#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) -#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF_Pos 0 -#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) -#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_PLLAEN_Pos 0 -#define CKGR_PLLAR_PLLAEN_Msk (0xffu << CKGR_PLLAR_PLLAEN_Pos) /**< \brief (CKGR_PLLAR) PLLA Control */ -#define CKGR_PLLAR_PLLAEN(value) ((CKGR_PLLAR_PLLAEN_Msk & ((value) << CKGR_PLLAR_PLLAEN_Pos))) -#define CKGR_PLLAR_PLLACOUNT_Pos 8 -#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) -#define CKGR_PLLAR_MULA_Pos 16 -#define CKGR_PLLAR_MULA_Msk (0x1fffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) -/* -------- CKGR_PLLBR : (PMC Offset: 0x002c) PLLB Register -------- */ -#define CKGR_PLLBR_PLLBEN_Pos 0 -#define CKGR_PLLBR_PLLBEN_Msk (0xffu << CKGR_PLLBR_PLLBEN_Pos) /**< \brief (CKGR_PLLBR) PLLB Control */ -#define CKGR_PLLBR_PLLBEN(value) ((CKGR_PLLBR_PLLBEN_Msk & ((value) << CKGR_PLLBR_PLLBEN_Pos))) -#define CKGR_PLLBR_PLLBCOUNT_Pos 8 -#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */ -#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) -#define CKGR_PLLBR_MULB_Pos 16 -#define CKGR_PLLBR_MULB_Msk (0xfffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ -#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) - -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS_Pos 0 -#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_PRES_Pos 4 -#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ -#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ -#define PMC_USB_USBDIV_Pos 8 -#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ -#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) -/* -------- PMC_PCK[8] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS_Pos 0 -#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ -#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ -#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */ -#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */ -#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ -#define PMC_PCK_PRES_Pos 4 -#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ -#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ -#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ -#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ -#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ -#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ -#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ -#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ -#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ -#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ -#define PMC_IER_PCKRDY7 (0x1u << 15) /**< \brief (PMC_IER) Programmable Clock Ready 7 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ -#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ -#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ -#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ -#define PMC_IDR_PCKRDY7 (0x1u << 15) /**< \brief (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */ -#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY7 (0x1u << 15) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ -#define PMC_FSMR_FLPM_Pos 21 -#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ -#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ -#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in deep-power-down mode when system enters Wait Mode */ -#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) idle mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ -#define PMC_WPMR_WPKEY_Pos 8 -#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ -#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ -#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ -#define PMC_WPSR_WPVSRC_Pos 8 -#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ -/* -------- PMC_ADDRSIZE : (PMC Offset: 0x00EC) Address Size Register -------- */ -#define PMC_ADDRSIZE_ADDRSIZE_Pos 0 -#define PMC_ADDRSIZE_ADDRSIZE_Msk (0xffffu << PMC_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (PMC_ADDRSIZE) Peripheral Bus Address Area Size */ -/* -------- PMC_IPNAME[2] : (PMC Offset: 0x00F0) IP Name1 Register -------- */ -#define PMC_IPNAME_IPNAME_Pos 0 -#define PMC_IPNAME_IPNAME_Msk (0xffffffffu << PMC_IPNAME_IPNAME_Pos) /**< \brief (PMC_IPNAME[2]) IP Name in ASCII Format */ -/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */ -#define PMC_VERSION_VERSION_Pos 0 -#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */ -#define PMC_VERSION_MFN_Pos 16 -#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL8_Pos 0 -#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ -#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) -#define PMC_OCR_SEL8 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ -#define PMC_OCR_CAL16_Pos 8 -#define PMC_OCR_CAL16_Msk (0x7fu << PMC_OCR_CAL16_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 16 MHz */ -#define PMC_OCR_CAL16(value) ((PMC_OCR_CAL16_Msk & ((value) << PMC_OCR_CAL16_Pos))) -#define PMC_OCR_SEL16 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 16 MHz */ -#define PMC_OCR_CAL24_Pos 16 -#define PMC_OCR_CAL24_Msk (0x7fu << PMC_OCR_CAL24_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 24 MHz */ -#define PMC_OCR_CAL24(value) ((PMC_OCR_CAL24_Msk & ((value) << PMC_OCR_CAL24_Pos))) -#define PMC_OCR_SEL24 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 24 MHz */ -/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x114) SleepWalking Enable Register 0 -------- */ -#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ -#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ -/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x118) SleepWalking Disable Register 0 -------- */ -#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ -#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ -/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x11C) SleepWalking Status Register 0 -------- */ -#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ -#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ -/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x120) SleepWalking Activity Status Register 0 -------- */ -#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ -#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ -#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ -#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ -#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ -#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ -#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ -#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ -#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ -#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ -#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ -#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ -#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ -#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ -#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ -#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ -#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ -#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ -#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ -#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ -#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ -#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ -/* -------- PMC_PMMR : (PMC Offset: 0x130) PLL Maximum Multiplier Value Register -------- */ -#define PMC_PMMR_PLLA_MMAX_Pos 0 -#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ -#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) - -/*@}*/ - - -#endif /* _SAMG55_PMC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h deleted file mode 100644 index 987762aa645..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_RSTC_COMPONENT_ -#define _SAMG55_RSTC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_RSTC Reset Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Rstc hardware registers */ -typedef struct { - __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY_Pos 24 -#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ -#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP_Pos 8 -#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ -#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ -#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ -#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ -#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ -#define RSTC_SR_RSTTYP_SLCK_XTAL_RST (0x7u << 8) /**< \brief (RSTC_SR) Slow Crystal Failure Detection fault occured */ -#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_SCKSW (0x1u << 1) /**< \brief (RSTC_MR) Slow Clock Switching */ -#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL_Pos 8 -#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) -#define RSTC_MR_KEY_Pos 24 -#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ -#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ - -/*@}*/ - - -#endif /* _SAMG55_RSTC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rtc.h deleted file mode 100644 index 186195f14b7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rtc.h +++ /dev/null @@ -1,226 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_RTC_COMPONENT_ -#define _SAMG55_RTC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup SAMG55_RTC Real-time Clock */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Rtc hardware registers */ -typedef struct { - __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ - __I uint32_t Reserved1[40]; - __I uint32_t RTC_MSR; /**< \brief (Rtc Offset: 0xD0) Milliseconds Register */ - __I uint32_t Reserved2[4]; - __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ -} Rtc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL_Pos 8 -#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ -#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ -#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ -#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ -#define RTC_CR_CALEVSEL_Pos 16 -#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ -#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ -#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ -#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ -#define RTC_MR_CORRECTION_Pos 8 -#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ -#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) -#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ -#define RTC_MR_OUT0_Pos 16 -#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) All ADC Channel Trigger Event Source Selection */ -#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ -#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ -#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ -#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ -#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ -#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ -#define RTC_MR_OUT1_Pos 20 -#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) ADC Last Channel Trigger Event Source Selection */ -#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ -#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ -#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ -#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ -#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ -#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC_Pos 0 -#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) -#define RTC_TIMR_MIN_Pos 8 -#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) -#define RTC_TIMR_HOUR_Pos 16 -#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) -#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT_Pos 0 -#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) -#define RTC_CALR_YEAR_Pos 8 -#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) -#define RTC_CALR_MONTH_Pos 16 -#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) -#define RTC_CALR_DAY_Pos 21 -#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) -#define RTC_CALR_DATE_Pos 24 -#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ -#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC_Pos 0 -#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) -#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN_Pos 8 -#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) -#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR_Pos 16 -#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) -#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH_Pos 16 -#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) -#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE_Pos 24 -#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) -#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ -#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ -#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ -#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ -#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ -#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ -#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ -#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ -#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ -#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ -#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ -#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ -#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ -#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ -/* -------- RTC_MSR : (RTC Offset: 0xD0) Milliseconds Register -------- */ -#define RTC_MSR_MS_Pos 0 -#define RTC_MSR_MS_Msk (0x3ffu << RTC_MSR_MS_Pos) /**< \brief (RTC_MSR) Number of 1/1024 seconds elapsed within 1 second */ -/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ -#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ -#define RTC_WPMR_WPKEY_Pos 8 -#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ -#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ - -/*@}*/ - - -#endif /* _SAMG55_RTC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rtt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rtt.h deleted file mode 100644 index e922c0fc06d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rtt.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_RTT_COMPONENT_ -#define _SAMG55_RTT_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup SAMG55_RTT Real-time Timer */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Rtt hardware registers */ -typedef struct { - __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ - __IO uint32_t RTT_MODR; /**< \brief (Rtt Offset: 0x10) Modulo Selection Register */ -} Rtt; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES_Pos 0 -#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) -#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ -#define RTT_MR_INC2AEN (0x1u << 21) /**< \brief (RTT_MR) RTTINC2 Alarm Enable */ -#define RTT_MR_EVAEN (0x1u << 22) /**< \brief (RTT_MR) Trigger Event Alarm Enable */ -#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV_Pos 0 -#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ -#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV_Pos 0 -#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status */ -#define RTT_SR_RTTINC2 (0x1u << 2) /**< \brief (RTT_SR) Predefined Number of Prescaler Roll-over Status */ -/* -------- RTT_MODR : (RTT Offset: 0x10) Modulo Selection Register -------- */ -#define RTT_MODR_SELINC2_Pos 0 -#define RTT_MODR_SELINC2_Msk (0x7u << RTT_MODR_SELINC2_Pos) /**< \brief (RTT_MODR) Selection of the 32-bit Counter Modulo to generate RTTINC2 flag */ -#define RTT_MODR_SELINC2_NO_RTTINC2 (0x0u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag never rises */ -#define RTT_MODR_SELINC2_MOD64 (0x1u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 64 equals 0 */ -#define RTT_MODR_SELINC2_MOD128 (0x2u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 128 equals 0 */ -#define RTT_MODR_SELINC2_MOD256 (0x3u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 256 equals 0 */ -#define RTT_MODR_SELINC2_MOD512 (0x4u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 512 equals 0 */ -#define RTT_MODR_SELINC2_MOD1024 (0x5u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 1024 equals 0.Example: If RTPRES=32 then RTTINC2 flag rises once per second if the slow clock is 32.768 kHz. */ -#define RTT_MODR_SELINC2_MOD2048 (0x6u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 2048 equals 0 */ -#define RTT_MODR_SELINC2_MOD4096 (0x7u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 4096 equals 0 */ -#define RTT_MODR_SELTRGEV_Pos 8 -#define RTT_MODR_SELTRGEV_Msk (0x7u << RTT_MODR_SELTRGEV_Pos) /**< \brief (RTT_MODR) Selection of the 32-bit Counter Modulo to generate the trigger event */ -#define RTT_MODR_SELTRGEV_NO_EVENT (0x0u << 8) /**< \brief (RTT_MODR) No event generated */ -#define RTT_MODR_SELTRGEV_MOD2 (0x1u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 2 equals 0 */ -#define RTT_MODR_SELTRGEV_MOD4 (0x2u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 4 equals 0 */ -#define RTT_MODR_SELTRGEV_MOD8 (0x3u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 8 equals 0 */ -#define RTT_MODR_SELTRGEV_MOD16 (0x4u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 16 equals 0 */ -#define RTT_MODR_SELTRGEV_MOD32 (0x5u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 32 equals 0 */ -#define RTT_MODR_SELTRGEV_MOD64 (0x6u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 64 equals 0 */ -#define RTT_MODR_SELTRGEV_MOD128 (0x7u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 128 equals 0 */ - -/*@}*/ - - -#endif /* _SAMG55_RTT_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_spi.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_spi.h deleted file mode 100644 index 8badf149a2a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_spi.h +++ /dev/null @@ -1,269 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI_COMPONENT_ -#define _SAMG55_SPI_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup SAMG55_SPI Serial Peripheral Interface */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Spi hardware registers */ -typedef struct { - __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x000) SPI Control Register */ - __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x004) SPI Mode Register */ - __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x008) SPI Receive Data Register */ - __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x00C) SPI Transmit Data Register */ - __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x010) SPI Status Register */ - __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x014) SPI Interrupt Enable Register */ - __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x018) SPI Interrupt Disable Register */ - __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x01C) SPI Interrupt Mask Register */ - __I uint32_t Reserved1[4]; - __IO uint32_t SPI_CSR[2]; /**< \brief (Spi Offset: 0x030) SPI Chip Select Register */ - __I uint32_t Reserved2[4]; - __IO uint32_t SPI_CMPR; /**< \brief (Spi Offset: 0x048) SPI Comparison Register */ - __I uint32_t Reserved3[38]; - __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0x0E4) SPI Write Protection Mode Register */ - __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0x0E8) SPI Write Protection Status Register */ - __I uint32_t Reserved4[5]; - __IO uint32_t SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - __IO uint32_t SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - __IO uint32_t SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - __IO uint32_t SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - __IO uint32_t SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - __IO uint32_t SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - __IO uint32_t SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - __IO uint32_t SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - __O uint32_t SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - __I uint32_t SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- SPI_CR : (SPI Offset: 0x000) SPI Control Register -------- */ -#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_REQCLR (0x1u << 12) /**< \brief (SPI_CR) Request to Clear the Comparison Trigger */ -#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x004) SPI Mode Register -------- */ -#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_BRSRCCLK (0x1u << 3) /**< \brief (SPI_MR) Bit Rate Source Clock */ -#define SPI_MR_BRSRCCLK_PERIPH_CLK (0x0u << 3) /**< \brief (SPI_MR) The peripheral clock is the source clock for the bit rate generation. */ -#define SPI_MR_BRSRCCLK_PMC_PCK (0x1u << 3) /**< \brief (SPI_MR) PMC PCKx is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. */ -#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_CMPMODE (0x1u << 12) /**< \brief (SPI_MR) Comparison Mode */ -#define SPI_MR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (SPI_MR) Any character is received and comparison function drives CMP flag. */ -#define SPI_MR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (SPI_MR) Comparison condition must be met to start reception of all incoming characters until REQCLR is set. */ -#define SPI_MR_PCS_Pos 16 -#define SPI_MR_PCS_Msk (0x3u << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) -#define SPI_MR_DLYBCS_Pos 24 -#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ -#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) -/* -------- SPI_RDR : (SPI Offset: 0x008) SPI Receive Data Register -------- */ -#define SPI_RDR_RD_Pos 0 -#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS_Pos 16 -#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x00C) SPI Transmit Data Register -------- */ -#define SPI_TDR_TD_Pos 0 -#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) -#define SPI_TDR_PCS_Pos 16 -#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) -#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x010) SPI Status Register -------- */ -#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (automatically set/cleared) */ -#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (automatically set/cleared) */ -#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ -#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ -#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer (automatically set/cleared) */ -#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer (automatically set/cleared) */ -#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full (automatically set/cleared) */ -#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty (automatically set/cleared) */ -#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ -#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (automatically set/cleared) */ -#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (slave mode only) (cleared on read) */ -#define SPI_SR_CMP (0x1u << 11) /**< \brief (SPI_SR) Comparison Status (cleared on read) */ -#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status (automatically set/cleared) */ -/* -------- SPI_IER : (SPI Offset: 0x014) SPI Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -#define SPI_IER_CMP (0x1u << 11) /**< \brief (SPI_IER) Comparison Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x018) SPI Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -#define SPI_IDR_CMP (0x1u << 11) /**< \brief (SPI_IDR) Comparison Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x01C) SPI Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -#define SPI_IMR_CMP (0x1u << 11) /**< \brief (SPI_IMR) Comparison Interrupt Mask */ -/* -------- SPI_CSR[2] : (SPI Offset: 0x030) SPI Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[2]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[2]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[2]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[2]) Chip Select Active After Transfer */ -#define SPI_CSR_BITS_Pos 4 -#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[2]) Bits Per Transfer */ -#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[2]) 8 bits for transfer */ -#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[2]) 9 bits for transfer */ -#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[2]) 10 bits for transfer */ -#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[2]) 11 bits for transfer */ -#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[2]) 12 bits for transfer */ -#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[2]) 13 bits for transfer */ -#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[2]) 14 bits for transfer */ -#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[2]) 15 bits for transfer */ -#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[2]) 16 bits for transfer */ -#define SPI_CSR_SCBR_Pos 8 -#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[2]) Serial Clock Bit Rate */ -#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) -#define SPI_CSR_DLYBS_Pos 16 -#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[2]) Delay Before SPCK */ -#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) -#define SPI_CSR_DLYBCT_Pos 24 -#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[2]) Delay Between Consecutive Transfers */ -#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) -/* -------- SPI_CMPR : (SPI Offset: 0x048) SPI Comparison Register -------- */ -#define SPI_CMPR_VAL1_Pos 0 -#define SPI_CMPR_VAL1_Msk (0xffffu << SPI_CMPR_VAL1_Pos) /**< \brief (SPI_CMPR) First Comparison Value for Received Character */ -#define SPI_CMPR_VAL1(value) ((SPI_CMPR_VAL1_Msk & ((value) << SPI_CMPR_VAL1_Pos))) -#define SPI_CMPR_VAL2_Pos 16 -#define SPI_CMPR_VAL2_Msk (0xffffu << SPI_CMPR_VAL2_Pos) /**< \brief (SPI_CMPR) Second Comparison Value for Received Character */ -#define SPI_CMPR_VAL2(value) ((SPI_CMPR_VAL2_Msk & ((value) << SPI_CMPR_VAL2_Pos))) -/* -------- SPI_WPMR : (SPI Offset: 0x0E4) SPI Write Protection Mode Register -------- */ -#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ -#define SPI_WPMR_WPKEY_Pos 8 -#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protect Key */ -#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ -/* -------- SPI_WPSR : (SPI Offset: 0x0E8) SPI Write Protection Status Register -------- */ -#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ -#define SPI_WPSR_WPVSRC_Pos 8 -#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR_Pos 0 -#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */ -#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos))) -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR_Pos 0 -#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */ -#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos))) -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR_Pos 0 -#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */ -#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos))) -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR_Pos 0 -#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */ -#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos))) -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR_Pos 0 -#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */ -#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos))) -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR_Pos 0 -#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */ -#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos))) -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR_Pos 0 -#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos))) -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR_Pos 0 -#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */ -#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos))) -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -#define SPI_PTCR_RXCBEN (0x1u << 16) /**< \brief (SPI_PTCR) Receiver Circular Buffer Enable */ -#define SPI_PTCR_RXCBDIS (0x1u << 17) /**< \brief (SPI_PTCR) Receiver Circular Buffer Disable */ -#define SPI_PTCR_TXCBEN (0x1u << 18) /**< \brief (SPI_PTCR) Transmitter Circular Buffer Enable */ -#define SPI_PTCR_TXCBDIS (0x1u << 19) /**< \brief (SPI_PTCR) Transmitter Circular Buffer Disable */ -#define SPI_PTCR_ERRCLR (0x1u << 24) /**< \brief (SPI_PTCR) Transfer Bus Error Clear */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ -#define SPI_PTSR_RXCBEN (0x1u << 16) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXCBEN (0x1u << 18) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ -#define SPI_PTSR_ERR (0x1u << 24) /**< \brief (SPI_PTSR) Transfer Bus Error (clear on read) */ - -/*@}*/ - - -#endif /* _SAMG55_SPI_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_supc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_supc.h deleted file mode 100644 index a93d0f6b02b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_supc.h +++ /dev/null @@ -1,343 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SUPC_COMPONENT_ -#define _SAMG55_SUPC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup SAMG55_SUPC Supply Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Supc hardware registers */ -typedef struct { - __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ - __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ - __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ - __I uint32_t Reserved1[1]; - __IO uint32_t SUPC_PWMR; /**< \brief (Supc Offset: 0x1C) Supply Controller Power Mode Register */ -} Supc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, asserts the system reset signal and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY_Pos 24 -#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ -#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation.Always reads as 0. */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH_Pos 0 -#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) -#define SUPC_SMMR_SMSMPL_Pos 8 -#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enables one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enables one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enables one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) POR Core Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) POR Core Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ -#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is selected and put in bypass mode. */ -#define SUPC_MR_CDPSWITCH (0x1u << 21) /**< \brief (SUPC_MR) Cache Data SRAM Power Switch */ -#define SUPC_MR_CDPSWITCH_OFF (0x0u << 21) /**< \brief (SUPC_MR) The cache data SRAM is not powered. */ -#define SUPC_MR_CDPSWITCH_ON (0x1u << 21) /**< \brief (SUPC_MR) The cache data SRAM is powered. */ -#define SUPC_MR_CTPSWITCH (0x1u << 22) /**< \brief (SUPC_MR) Cache Tag SRAM Power Switch */ -#define SUPC_MR_CTPSWITCH_OFF (0x0u << 22) /**< \brief (SUPC_MR) The cache tag SRAM is not powered. */ -#define SUPC_MR_CTPSWITCH_ON (0x1u << 22) /**< \brief (SUPC_MR) The cache tag SRAM is powered. */ -#define SUPC_MR_ONE (0x1u << 23) /**< \brief (SUPC_MR) This bit must always be set to 1. */ -#define SUPC_MR_KEY_Pos 24 -#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ -#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ -#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ -#define SUPC_WUMR_WKUPDBC_Pos 12 -#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ -#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake-up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake-up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 */ -#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 1 */ -#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 2 */ -#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 3 */ -#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 4 */ -#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 5 */ -#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 6 */ -#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 7 */ -#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 8 */ -#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 9 */ -#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 10 */ -#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 11 */ -#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 12 */ -#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 13 */ -#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake-up Input Type 14 */ -#define SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake-up Input Type 15 */ -#define SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status */ -#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock SLCK is generated by the embedded 32 kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock SLCK is generated by the 32 kHz crystal oscillator. */ -#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DISABLED (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS0_ENABLED (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DISABLED (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS1_ENABLED (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DISABLED (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS2_ENABLED (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DISABLED (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS3_ENABLED (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DISABLED (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS4_ENABLED (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DISABLED (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS5_ENABLED (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DISABLED (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS6_ENABLED (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DISABLED (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS7_ENABLED (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DISABLED (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS8_ENABLED (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DISABLED (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS9_ENABLED (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DISABLED (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS10_ENABLED (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DISABLED (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS11_ENABLED (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DISABLED (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS12_ENABLED (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DISABLED (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS13_ENABLED (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DISABLED (0x0u << 30) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS14_ENABLED (0x1u << 30) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DISABLED (0x0u << 31) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS15_ENABLED (0x1u << 31) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -/* -------- SUPC_PWMR : (SUPC Offset: 0x1C) Supply Controller Power Mode Register -------- */ -#define SUPC_PWMR_LPOWERS (0x1u << 0) /**< \brief (SUPC_PWMR) Low Power Value Selection */ -#define SUPC_PWMR_LPOWERS_FACTORY (0x0u << 0) /**< \brief (SUPC_PWMR) The trimming value applied to the regulator when the device is in wait mode. This value is factory-defined. */ -#define SUPC_PWMR_LPOWERS_USER (0x1u << 0) /**< \brief (SUPC_PWMR) The trimming value applied to the regulator is defined by the value programmed in the LPOWERx bits. */ -#define SUPC_PWMR_LPOWER0 (0x1u << 1) /**< \brief (SUPC_PWMR) Low Power Value */ -#define SUPC_PWMR_LPOWER1 (0x1u << 2) /**< \brief (SUPC_PWMR) Low Power Value */ -#define SUPC_PWMR_LPOWER2 (0x1u << 3) /**< \brief (SUPC_PWMR) Low Power Value */ -#define SUPC_PWMR_LPOWER3 (0x1u << 4) /**< \brief (SUPC_PWMR) Low Power Value */ -#define SUPC_PWMR_STUPTIME (0x1u << 7) /**< \brief (SUPC_PWMR) Start-up Time when Resuming from Wait Mode */ -#define SUPC_PWMR_STUPTIME_FAST (0x0u << 7) /**< \brief (SUPC_PWMR) Fast start-up. */ -#define SUPC_PWMR_STUPTIME_SLOW (0x1u << 7) /**< \brief (SUPC_PWMR) Slow start-up. */ -#define SUPC_PWMR_ECPWRS (0x1u << 8) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value Selection */ -#define SUPC_PWMR_ECPWRS_FACTORY (0x0u << 8) /**< \brief (SUPC_PWMR) The trimming value applied to the regulator when the device is in active mode. This value is factory-defined. */ -#define SUPC_PWMR_ECPWRS_USER (0x1u << 8) /**< \brief (SUPC_PWMR) The trimming value applied to the regulator is defined by the value programmed in ECPWRx bits. */ -#define SUPC_PWMR_ECPWR0 (0x1u << 9) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value */ -#define SUPC_PWMR_ECPWR1 (0x1u << 10) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value */ -#define SUPC_PWMR_ECPWR2 (0x1u << 11) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value */ -#define SUPC_PWMR_ECPWR3 (0x1u << 12) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value */ -#define SUPC_PWMR_SRAM0ON (0x1u << 16) /**< \brief (SUPC_PWMR) SRAM Power Control */ -#define SUPC_PWMR_SRAM0ON_OFF (0x0u << 16) /**< \brief (SUPC_PWMR) SRAMx is not powered. */ -#define SUPC_PWMR_SRAM0ON_ON (0x1u << 16) /**< \brief (SUPC_PWMR) SRAMx is powered. */ -#define SUPC_PWMR_SRAM1ON (0x1u << 17) /**< \brief (SUPC_PWMR) SRAM Power Control */ -#define SUPC_PWMR_SRAM1ON_OFF (0x0u << 17) /**< \brief (SUPC_PWMR) SRAMx is not powered. */ -#define SUPC_PWMR_SRAM1ON_ON (0x1u << 17) /**< \brief (SUPC_PWMR) SRAMx is powered. */ -#define SUPC_PWMR_SRAM2ON (0x1u << 18) /**< \brief (SUPC_PWMR) SRAM Power Control */ -#define SUPC_PWMR_SRAM2ON_OFF (0x0u << 18) /**< \brief (SUPC_PWMR) SRAMx is not powered. */ -#define SUPC_PWMR_SRAM2ON_ON (0x1u << 18) /**< \brief (SUPC_PWMR) SRAMx is powered. */ -#define SUPC_PWMR_SRAM3ON (0x1u << 19) /**< \brief (SUPC_PWMR) SRAM Power Control */ -#define SUPC_PWMR_SRAM3ON_OFF (0x0u << 19) /**< \brief (SUPC_PWMR) SRAMx is not powered. */ -#define SUPC_PWMR_SRAM3ON_ON (0x1u << 19) /**< \brief (SUPC_PWMR) SRAMx is powered. */ -#define SUPC_PWMR_SRAM4ON (0x1u << 20) /**< \brief (SUPC_PWMR) SRAM Power Control */ -#define SUPC_PWMR_SRAM4ON_OFF (0x0u << 20) /**< \brief (SUPC_PWMR) SRAMx is not powered. */ -#define SUPC_PWMR_SRAM4ON_ON (0x1u << 20) /**< \brief (SUPC_PWMR) SRAMx is powered. */ -#define SUPC_PWMR_SRAM5ON (0x1u << 21) /**< \brief (SUPC_PWMR) SRAM Power Control */ -#define SUPC_PWMR_SRAM5ON_OFF (0x0u << 21) /**< \brief (SUPC_PWMR) SRAMx is not powered. */ -#define SUPC_PWMR_SRAM5ON_ON (0x1u << 21) /**< \brief (SUPC_PWMR) SRAMx is powered. */ -#define SUPC_PWMR_SRAM6ON (0x1u << 22) /**< \brief (SUPC_PWMR) SRAM Power Control */ -#define SUPC_PWMR_SRAM6ON_OFF (0x0u << 22) /**< \brief (SUPC_PWMR) SRAMx is not powered. */ -#define SUPC_PWMR_SRAM6ON_ON (0x1u << 22) /**< \brief (SUPC_PWMR) SRAMx is powered. */ -#define SUPC_PWMR_DPRAMON (0x1u << 23) /**< \brief (SUPC_PWMR) Dual-port RAM Power Control */ -#define SUPC_PWMR_DPRAMON_OFF (0x0u << 23) /**< \brief (SUPC_PWMR) USB dual-port RAM is not powered. */ -#define SUPC_PWMR_DPRAMON_ON (0x1u << 23) /**< \brief (SUPC_PWMR) USB dual-port RAM is powered. */ -#define SUPC_PWMR_KEY_Pos 24 -#define SUPC_PWMR_KEY_Msk (0xffu << SUPC_PWMR_KEY_Pos) /**< \brief (SUPC_PWMR) Password Key */ -#define SUPC_PWMR_KEY_PASSWD (0x5Au << 24) /**< \brief (SUPC_PWMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ - -/*@}*/ - - -#endif /* _SAMG55_SUPC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_tc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_tc.h deleted file mode 100644 index 00b1f84a1a8..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_tc.h +++ /dev/null @@ -1,328 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TC_COMPONENT_ -#define _SAMG55_TC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup SAMG55_TC Timer Counter */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief TcChannel hardware registers */ -typedef struct { - __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ - __I uint32_t Reserved1[1]; - __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - __I uint32_t Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -#define TCCHANNEL_NUMBER 3 -typedef struct { - TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - __I uint32_t Reserved1[7]; - __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ - __I uint32_t Reserved2[6]; - __IO uint32_t TC_RPR0; /**< \brief (Tc Offset: 0x100) Receive Pointer Register (pdc = 0) */ - __IO uint32_t TC_RCR0; /**< \brief (Tc Offset: 0x104) Receive Counter Register (pdc = 0) */ - __I uint32_t Reserved3[2]; - __IO uint32_t TC_RNPR0; /**< \brief (Tc Offset: 0x110) Receive Next Pointer Register (pdc = 0) */ - __IO uint32_t TC_RNCR0; /**< \brief (Tc Offset: 0x114) Receive Next Counter Register (pdc = 0) */ - __I uint32_t Reserved4[2]; - __O uint32_t TC_PTCR0; /**< \brief (Tc Offset: 0x120) Transfer Control Register (pdc = 0) */ - __I uint32_t TC_PTSR0; /**< \brief (Tc Offset: 0x124) Transfer Status Register (pdc = 0) */ -} Tc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ -#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ -#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ -#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ -/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ -#define TC_CMR_TCCLKS_Pos 0 -#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ -#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) */ -#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) */ -#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) */ -#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) */ -#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) */ -#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ -#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ -#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ -#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ -#define TC_CMR_BURST_Pos 4 -#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ -#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ -#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ -#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ -#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ -#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ -#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ -#define TC_CMR_ETRGEDG_Pos 8 -#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ -#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ -#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ -#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ -#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ -#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ -#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ -#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ -#define TC_CMR_LDRA_Pos 16 -#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ -#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ -#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ -#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ -#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ -#define TC_CMR_LDRB_Pos 18 -#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ -#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ -#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ -#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ -#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ -#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ -#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ -#define TC_CMR_EEVTEDG_Pos 8 -#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ -#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ -#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ -#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ -#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ -#define TC_CMR_EEVT_Pos 10 -#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ -#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ -#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ -#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ -#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ -#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ -#define TC_CMR_WAVSEL_Pos 13 -#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ -#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ -#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ -#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ -#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ -#define TC_CMR_ACPA_Pos 16 -#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ -#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ -#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ -#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_ACPC_Pos 18 -#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ -#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ -#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ -#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_AEEVT_Pos 20 -#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ -#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ -#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ -#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_ASWTRG_Pos 22 -#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ -#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ -#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ -#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_BCPB_Pos 24 -#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ -#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ -#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ -#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_BCPC_Pos 26 -#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ -#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ -#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ -#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_BEEVT_Pos 28 -#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ -#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ -#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ -#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_BSWTRG_Pos 30 -#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ -#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ -#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ -#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ -/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ -#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ -#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ -/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ -#define TC_CV_CV_Pos 0 -#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ -/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ -#define TC_RA_RA_Pos 0 -#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ -#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) -/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ -#define TC_RB_RB_Pos 0 -#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ -#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) -/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ -#define TC_RC_RC_Pos 0 -#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ -#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) -/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ -#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */ -#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */ -#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */ -#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */ -#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */ -#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */ -#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */ -#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */ -#define TC_SR_ENDRX (0x1u << 8) /**< \brief (TC_SR) End of Receiver Transfer */ -#define TC_SR_RXBUFF (0x1u << 9) /**< \brief (TC_SR) Reception Buffer Full */ -#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ -#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ -#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ -/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ -#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ -#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ -#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ -#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ -#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ -#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ -#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ -#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ -#define TC_IER_ENDRX (0x1u << 8) /**< \brief (TC_IER) End of Receiver Transfer */ -#define TC_IER_RXBUFF (0x1u << 9) /**< \brief (TC_IER) Reception Buffer Full */ -/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ -#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ -#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ -#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ -#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ -#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ -#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ -#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ -#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ -#define TC_IDR_ENDRX (0x1u << 8) /**< \brief (TC_IDR) End of Receiver Transfer */ -#define TC_IDR_RXBUFF (0x1u << 9) /**< \brief (TC_IDR) Reception Buffer Full */ -/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ -#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ -#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ -#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ -#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ -#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ -#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ -#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ -#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ -#define TC_IMR_ENDRX (0x1u << 8) /**< \brief (TC_IMR) End of Receiver Transfer */ -#define TC_IMR_RXBUFF (0x1u << 9) /**< \brief (TC_IMR) Reception Buffer Full */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S_Pos 0 -#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ -#define TC_BMR_TC1XC1S_Pos 2 -#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ -#define TC_BMR_TC2XC2S_Pos 4 -#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ -#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ -#define TC_WPMR_WPKEY_Pos 8 -#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ -#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ -/* -------- TC_RPR0 : (TC Offset: 0x100) Receive Pointer Register (pdc = 0) -------- */ -#define TC_RPR0_RXPTR_Pos 0 -#define TC_RPR0_RXPTR_Msk (0xffffffffu << TC_RPR0_RXPTR_Pos) /**< \brief (TC_RPR0) Receive Pointer Register */ -#define TC_RPR0_RXPTR(value) ((TC_RPR0_RXPTR_Msk & ((value) << TC_RPR0_RXPTR_Pos))) -/* -------- TC_RCR0 : (TC Offset: 0x104) Receive Counter Register (pdc = 0) -------- */ -#define TC_RCR0_RXCTR_Pos 0 -#define TC_RCR0_RXCTR_Msk (0xffffu << TC_RCR0_RXCTR_Pos) /**< \brief (TC_RCR0) Receive Counter Register */ -#define TC_RCR0_RXCTR(value) ((TC_RCR0_RXCTR_Msk & ((value) << TC_RCR0_RXCTR_Pos))) -/* -------- TC_RNPR0 : (TC Offset: 0x110) Receive Next Pointer Register (pdc = 0) -------- */ -#define TC_RNPR0_RXNPTR_Pos 0 -#define TC_RNPR0_RXNPTR_Msk (0xffffffffu << TC_RNPR0_RXNPTR_Pos) /**< \brief (TC_RNPR0) Receive Next Pointer */ -#define TC_RNPR0_RXNPTR(value) ((TC_RNPR0_RXNPTR_Msk & ((value) << TC_RNPR0_RXNPTR_Pos))) -/* -------- TC_RNCR0 : (TC Offset: 0x114) Receive Next Counter Register (pdc = 0) -------- */ -#define TC_RNCR0_RXNCTR_Pos 0 -#define TC_RNCR0_RXNCTR_Msk (0xffffu << TC_RNCR0_RXNCTR_Pos) /**< \brief (TC_RNCR0) Receive Next Counter */ -#define TC_RNCR0_RXNCTR(value) ((TC_RNCR0_RXNCTR_Msk & ((value) << TC_RNCR0_RXNCTR_Pos))) -/* -------- TC_PTCR0 : (TC Offset: 0x120) Transfer Control Register (pdc = 0) -------- */ -#define TC_PTCR0_RXTEN (0x1u << 0) /**< \brief (TC_PTCR0) Receiver Transfer Enable */ -#define TC_PTCR0_RXTDIS (0x1u << 1) /**< \brief (TC_PTCR0) Receiver Transfer Disable */ -#define TC_PTCR0_TXTEN (0x1u << 8) /**< \brief (TC_PTCR0) Transmitter Transfer Enable */ -#define TC_PTCR0_TXTDIS (0x1u << 9) /**< \brief (TC_PTCR0) Transmitter Transfer Disable */ -#define TC_PTCR0_RXCBEN (0x1u << 16) /**< \brief (TC_PTCR0) Receiver Circular Buffer Enable */ -#define TC_PTCR0_RXCBDIS (0x1u << 17) /**< \brief (TC_PTCR0) Receiver Circular Buffer Disable */ -#define TC_PTCR0_TXCBEN (0x1u << 18) /**< \brief (TC_PTCR0) Transmitter Circular Buffer Enable */ -#define TC_PTCR0_TXCBDIS (0x1u << 19) /**< \brief (TC_PTCR0) Transmitter Circular Buffer Disable */ -#define TC_PTCR0_ERRCLR (0x1u << 24) /**< \brief (TC_PTCR0) Transfer Bus Error Clear */ -/* -------- TC_PTSR0 : (TC Offset: 0x124) Transfer Status Register (pdc = 0) -------- */ -#define TC_PTSR0_RXTEN (0x1u << 0) /**< \brief (TC_PTSR0) Receiver Transfer Enable */ -#define TC_PTSR0_TXTEN (0x1u << 8) /**< \brief (TC_PTSR0) Transmitter Transfer Enable */ -#define TC_PTSR0_RXCBEN (0x1u << 16) /**< \brief (TC_PTSR0) Receiver Transfer Enable */ -#define TC_PTSR0_TXCBEN (0x1u << 18) /**< \brief (TC_PTSR0) Transmitter Transfer Enable */ -#define TC_PTSR0_ERR (0x1u << 24) /**< \brief (TC_PTSR0) Transfer Bus Error (clear on read) */ - -/*@}*/ - - -#endif /* _SAMG55_TC_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_twi.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_twi.h deleted file mode 100644 index 358a849cf61..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_twi.h +++ /dev/null @@ -1,358 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI_COMPONENT_ -#define _SAMG55_TWI_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two wire Interface */ -/* ============================================================================= */ -/** \addtogroup SAMG55_TWI Two wire Interface */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Twi hardware registers */ -typedef struct { - __O uint32_t TWI_CR; /**< \brief (Twi Offset: 0x000) TWI Control Register */ - __IO uint32_t TWI_MMR; /**< \brief (Twi Offset: 0x004) TWI Master Mode Register */ - __IO uint32_t TWI_SMR; /**< \brief (Twi Offset: 0x008) TWI Slave Mode Register */ - __IO uint32_t TWI_IADR; /**< \brief (Twi Offset: 0x00C) TWI Internal Address Register */ - __IO uint32_t TWI_CWGR; /**< \brief (Twi Offset: 0x010) TWI Clock Waveform Generator Register */ - __I uint32_t Reserved1[3]; - __I uint32_t TWI_SR; /**< \brief (Twi Offset: 0x020) TWI Status Register */ - __O uint32_t TWI_IER; /**< \brief (Twi Offset: 0x024) TWI Interrupt Enable Register */ - __O uint32_t TWI_IDR; /**< \brief (Twi Offset: 0x028) TWI Interrupt Disable Register */ - __I uint32_t TWI_IMR; /**< \brief (Twi Offset: 0x02C) TWI Interrupt Mask Register */ - __I uint32_t TWI_RHR; /**< \brief (Twi Offset: 0x030) TWI Receive Holding Register */ - __O uint32_t TWI_THR; /**< \brief (Twi Offset: 0x034) TWI Transmit Holding Register */ - __IO uint32_t TWI_SMBTR; /**< \brief (Twi Offset: 0x038) TWI SMBus Timing Register */ - __I uint32_t Reserved2[1]; - __IO uint32_t TWI_ACR; /**< \brief (Twi Offset: 0x040) TWI Alternative Command Register */ - __IO uint32_t TWI_FILTR; /**< \brief (Twi Offset: 0x044) TWI Filter Register */ - __I uint32_t Reserved3[1]; - __IO uint32_t TWI_SWMR; /**< \brief (Twi Offset: 0x04C) TWI SleepWalking Matching Register */ - __I uint32_t Reserved4[37]; - __IO uint32_t TWI_WPMR; /**< \brief (Twi Offset: 0x0E4) TWI Write Protection Mode Register */ - __I uint32_t TWI_WPSR; /**< \brief (Twi Offset: 0x0E8) TWI Write Protection Status Register */ - __I uint32_t Reserved5[5]; - __IO uint32_t TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - __IO uint32_t TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - __IO uint32_t TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - __IO uint32_t TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - __IO uint32_t TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - __IO uint32_t TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - __IO uint32_t TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - __IO uint32_t TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - __O uint32_t TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - __I uint32_t TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- TWI_CR : (TWI Offset: 0x000) TWI Control Register -------- */ -#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ -#define TWI_CR_HSEN (0x1u << 8) /**< \brief (TWI_CR) TWI High-Speed Mode Enabled */ -#define TWI_CR_HSDIS (0x1u << 9) /**< \brief (TWI_CR) TWI High-Speed Mode Disabled */ -#define TWI_CR_SMBEN (0x1u << 10) /**< \brief (TWI_CR) SMBus Mode Enabled */ -#define TWI_CR_SMBDIS (0x1u << 11) /**< \brief (TWI_CR) SMBus Mode Disabled */ -#define TWI_CR_PECEN (0x1u << 12) /**< \brief (TWI_CR) Packet Error Checking Enable */ -#define TWI_CR_PECDIS (0x1u << 13) /**< \brief (TWI_CR) Packet Error Checking Disable */ -#define TWI_CR_PECRQ (0x1u << 14) /**< \brief (TWI_CR) PEC Request */ -#define TWI_CR_CLEAR (0x1u << 15) /**< \brief (TWI_CR) Bus CLEAR Command */ -#define TWI_CR_ACMEN (0x1u << 16) /**< \brief (TWI_CR) Alternative Command Mode Enable */ -#define TWI_CR_ACMDIS (0x1u << 17) /**< \brief (TWI_CR) Alternative Command Mode Disable */ -#define TWI_CR_THRCLR (0x1u << 24) /**< \brief (TWI_CR) Transmit Holding Register Clear */ -#define TWI_CR_LOCKCLR (0x1u << 26) /**< \brief (TWI_CR) Lock Clear */ -/* -------- TWI_MMR : (TWI Offset: 0x004) TWI Master Mode Register -------- */ -#define TWI_MMR_IADRSZ_Pos 8 -#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR_Pos 16 -#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ -#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) -/* -------- TWI_SMR : (TWI Offset: 0x008) TWI Slave Mode Register -------- */ -#define TWI_SMR_NACKEN (0x1u << 0) /**< \brief (TWI_SMR) Slave Receiver Data Phase NACK Enable */ -#define TWI_SMR_SMDA (0x1u << 2) /**< \brief (TWI_SMR) SMBus Default Address */ -#define TWI_SMR_SMHH (0x1u << 3) /**< \brief (TWI_SMR) SMBus Host Header */ -#define TWI_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWI_SMR) Clock Wait State Disable */ -#define TWI_SMR_MASK_Pos 8 -#define TWI_SMR_MASK_Msk (0x7fu << TWI_SMR_MASK_Pos) /**< \brief (TWI_SMR) Slave Address Mask */ -#define TWI_SMR_MASK(value) ((TWI_SMR_MASK_Msk & ((value) << TWI_SMR_MASK_Pos))) -#define TWI_SMR_SADR_Pos 16 -#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ -#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) -#define TWI_SMR_SADR1EN (0x1u << 28) /**< \brief (TWI_SMR) Slave Address 1 Enable */ -#define TWI_SMR_SADR2EN (0x1u << 29) /**< \brief (TWI_SMR) Slave Address 2 Enable */ -#define TWI_SMR_SADR3EN (0x1u << 30) /**< \brief (TWI_SMR) Slave Address 3 Enable */ -#define TWI_SMR_DATAMEN (0x1u << 31) /**< \brief (TWI_SMR) Data Matching Enable */ -/* -------- TWI_IADR : (TWI Offset: 0x00C) TWI Internal Address Register -------- */ -#define TWI_IADR_IADR_Pos 0 -#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ -#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) -/* -------- TWI_CWGR : (TWI Offset: 0x010) TWI Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV_Pos 0 -#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) -#define TWI_CWGR_CHDIV_Pos 8 -#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) -#define TWI_CWGR_CKDIV_Pos 16 -#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ -#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) -#define TWI_CWGR_BRSRCCLK (0x1u << 20) /**< \brief (TWI_CWGR) Bit Rate Source Clock */ -#define TWI_CWGR_BRSRCCLK_PERIPH_CLK (0x0u << 20) /**< \brief (TWI_CWGR) The peripheral clock is the source clock for the bit rate generation. */ -#define TWI_CWGR_BRSRCCLK_PMC_PCK (0x1u << 20) /**< \brief (TWI_CWGR) PMC PCKx is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. */ -#define TWI_CWGR_HOLD_Pos 24 -#define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /**< \brief (TWI_CWGR) TWD Hold Time Versus TWCK Falling */ -#define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos))) -/* -------- TWI_SR : (TWI Offset: 0x020) TWI Status Register -------- */ -#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_UNRE (0x1u << 7) /**< \brief (TWI_SR) Underrun Error (clear on read) */ -#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX Buffer */ -#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX Buffer */ -#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -#define TWI_SR_MCACK (0x1u << 16) /**< \brief (TWI_SR) Master Code Acknowledge */ -#define TWI_SR_TOUT (0x1u << 18) /**< \brief (TWI_SR) Timeout Error */ -#define TWI_SR_PECERR (0x1u << 19) /**< \brief (TWI_SR) PEC Error */ -#define TWI_SR_SMBDAM (0x1u << 20) /**< \brief (TWI_SR) SMBus Default Address Match */ -#define TWI_SR_SMBHHM (0x1u << 21) /**< \brief (TWI_SR) SMBus Host Header Address Match */ -#define TWI_SR_LOCK (0x1u << 23) /**< \brief (TWI_SR) TWI Lock due to Frame Errors */ -#define TWI_SR_SCL (0x1u << 24) /**< \brief (TWI_SR) SCL line value */ -#define TWI_SR_SDA (0x1u << 25) /**< \brief (TWI_SR) SDA line value */ -/* -------- TWI_IER : (TWI Offset: 0x024) TWI Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_UNRE (0x1u << 7) /**< \brief (TWI_IER) Underrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -#define TWI_IER_MCACK (0x1u << 16) /**< \brief (TWI_IER) Master Code Acknowledge Interrupt Enable */ -#define TWI_IER_TOUT (0x1u << 18) /**< \brief (TWI_IER) Timeout Error Interrupt Enable */ -#define TWI_IER_PECERR (0x1u << 19) /**< \brief (TWI_IER) PEC Error Interrupt Enable */ -#define TWI_IER_SMBDAM (0x1u << 20) /**< \brief (TWI_IER) SMBus Default Address Match Interrupt Enable */ -#define TWI_IER_SMBHHM (0x1u << 21) /**< \brief (TWI_IER) SMBus Host Header Address Match Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x028) TWI Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_UNRE (0x1u << 7) /**< \brief (TWI_IDR) Underrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define TWI_IDR_MCACK (0x1u << 16) /**< \brief (TWI_IDR) Master Code Acknowledge Interrupt Disable */ -#define TWI_IDR_TOUT (0x1u << 18) /**< \brief (TWI_IDR) Timeout Error Interrupt Disable */ -#define TWI_IDR_PECERR (0x1u << 19) /**< \brief (TWI_IDR) PEC Error Interrupt Disable */ -#define TWI_IDR_SMBDAM (0x1u << 20) /**< \brief (TWI_IDR) SMBus Default Address Match Interrupt Disable */ -#define TWI_IDR_SMBHHM (0x1u << 21) /**< \brief (TWI_IDR) SMBus Host Header Address Match Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x02C) TWI Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_UNRE (0x1u << 7) /**< \brief (TWI_IMR) Underrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define TWI_IMR_MCACK (0x1u << 16) /**< \brief (TWI_IMR) Master Code Acknowledge Interrupt Mask */ -#define TWI_IMR_TOUT (0x1u << 18) /**< \brief (TWI_IMR) Timeout Error Interrupt Mask */ -#define TWI_IMR_PECERR (0x1u << 19) /**< \brief (TWI_IMR) PEC Error Interrupt Mask */ -#define TWI_IMR_SMBDAM (0x1u << 20) /**< \brief (TWI_IMR) SMBus Default Address Match Interrupt Mask */ -#define TWI_IMR_SMBHHM (0x1u << 21) /**< \brief (TWI_IMR) SMBus Host Header Address Match Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x030) TWI Receive Holding Register -------- */ -#define TWI_RHR_RXDATA_Pos 0 -#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x034) TWI Transmit Holding Register -------- */ -#define TWI_THR_TXDATA_Pos 0 -#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) -/* -------- TWI_SMBTR : (TWI Offset: 0x038) TWI SMBus Timing Register -------- */ -#define TWI_SMBTR_PRESC_Pos 0 -#define TWI_SMBTR_PRESC_Msk (0xfu << TWI_SMBTR_PRESC_Pos) /**< \brief (TWI_SMBTR) SMBus Clock Prescaler */ -#define TWI_SMBTR_PRESC(value) ((TWI_SMBTR_PRESC_Msk & ((value) << TWI_SMBTR_PRESC_Pos))) -#define TWI_SMBTR_TLOWS_Pos 8 -#define TWI_SMBTR_TLOWS_Msk (0xffu << TWI_SMBTR_TLOWS_Pos) /**< \brief (TWI_SMBTR) Slave Clock Stretch Maximum Cycles */ -#define TWI_SMBTR_TLOWS(value) ((TWI_SMBTR_TLOWS_Msk & ((value) << TWI_SMBTR_TLOWS_Pos))) -#define TWI_SMBTR_TLOWM_Pos 16 -#define TWI_SMBTR_TLOWM_Msk (0xffu << TWI_SMBTR_TLOWM_Pos) /**< \brief (TWI_SMBTR) Master Clock Stretch Maximum Cycles */ -#define TWI_SMBTR_TLOWM(value) ((TWI_SMBTR_TLOWM_Msk & ((value) << TWI_SMBTR_TLOWM_Pos))) -#define TWI_SMBTR_THMAX_Pos 24 -#define TWI_SMBTR_THMAX_Msk (0xffu << TWI_SMBTR_THMAX_Pos) /**< \brief (TWI_SMBTR) Clock High Maximum Cycles */ -#define TWI_SMBTR_THMAX(value) ((TWI_SMBTR_THMAX_Msk & ((value) << TWI_SMBTR_THMAX_Pos))) -/* -------- TWI_ACR : (TWI Offset: 0x040) TWI Alternative Command Register -------- */ -#define TWI_ACR_DATAL_Pos 0 -#define TWI_ACR_DATAL_Msk (0xffu << TWI_ACR_DATAL_Pos) /**< \brief (TWI_ACR) Data Length */ -#define TWI_ACR_DATAL(value) ((TWI_ACR_DATAL_Msk & ((value) << TWI_ACR_DATAL_Pos))) -#define TWI_ACR_DIR (0x1u << 8) /**< \brief (TWI_ACR) Transfer Direction */ -#define TWI_ACR_PEC (0x1u << 9) /**< \brief (TWI_ACR) PEC Request (SMBus Mode only) */ -#define TWI_ACR_NDATAL_Pos 16 -#define TWI_ACR_NDATAL_Msk (0xffu << TWI_ACR_NDATAL_Pos) /**< \brief (TWI_ACR) Next Data Length */ -#define TWI_ACR_NDATAL(value) ((TWI_ACR_NDATAL_Msk & ((value) << TWI_ACR_NDATAL_Pos))) -#define TWI_ACR_NDIR (0x1u << 24) /**< \brief (TWI_ACR) Next Transfer Direction */ -#define TWI_ACR_NPEC (0x1u << 25) /**< \brief (TWI_ACR) Next PEC Request (SMBus Mode only) */ -/* -------- TWI_FILTR : (TWI Offset: 0x044) TWI Filter Register -------- */ -#define TWI_FILTR_FILT (0x1u << 0) /**< \brief (TWI_FILTR) RX Digital Filter */ -#define TWI_FILTR_PADFEN (0x1u << 1) /**< \brief (TWI_FILTR) PAD Filter Enable */ -#define TWI_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWI_FILTR) PAD Filter Config */ -#define TWI_FILTR_THRES_Pos 8 -#define TWI_FILTR_THRES_Msk (0x7u << TWI_FILTR_THRES_Pos) /**< \brief (TWI_FILTR) Digital Filter Threshold */ -#define TWI_FILTR_THRES(value) ((TWI_FILTR_THRES_Msk & ((value) << TWI_FILTR_THRES_Pos))) -/* -------- TWI_SWMR : (TWI Offset: 0x04C) TWI SleepWalking Matching Register -------- */ -#define TWI_SWMR_SADR1_Pos 0 -#define TWI_SWMR_SADR1_Msk (0x7fu << TWI_SWMR_SADR1_Pos) /**< \brief (TWI_SWMR) Slave Address 1 */ -#define TWI_SWMR_SADR1(value) ((TWI_SWMR_SADR1_Msk & ((value) << TWI_SWMR_SADR1_Pos))) -#define TWI_SWMR_SADR2_Pos 8 -#define TWI_SWMR_SADR2_Msk (0x7fu << TWI_SWMR_SADR2_Pos) /**< \brief (TWI_SWMR) Slave Address 2 */ -#define TWI_SWMR_SADR2(value) ((TWI_SWMR_SADR2_Msk & ((value) << TWI_SWMR_SADR2_Pos))) -#define TWI_SWMR_SADR3_Pos 16 -#define TWI_SWMR_SADR3_Msk (0x7fu << TWI_SWMR_SADR3_Pos) /**< \brief (TWI_SWMR) Slave Address 3 */ -#define TWI_SWMR_SADR3(value) ((TWI_SWMR_SADR3_Msk & ((value) << TWI_SWMR_SADR3_Pos))) -#define TWI_SWMR_DATAM_Pos 24 -#define TWI_SWMR_DATAM_Msk (0xffu << TWI_SWMR_DATAM_Pos) /**< \brief (TWI_SWMR) Data Match */ -#define TWI_SWMR_DATAM(value) ((TWI_SWMR_DATAM_Msk & ((value) << TWI_SWMR_DATAM_Pos))) -/* -------- TWI_WPMR : (TWI Offset: 0x0E4) TWI Write Protection Mode Register -------- */ -#define TWI_WPMR_WPEN (0x1u << 0) /**< \brief (TWI_WPMR) Write Protection Enable */ -#define TWI_WPMR_WPKEY_Pos 8 -#define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /**< \brief (TWI_WPMR) Write Protection Key */ -#define TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ -/* -------- TWI_WPSR : (TWI Offset: 0x0E8) TWI Write Protection Status Register -------- */ -#define TWI_WPSR_WPVS (0x1u << 0) /**< \brief (TWI_WPSR) Write Protect Violation Status */ -#define TWI_WPSR_WPVSRC_Pos 8 -#define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /**< \brief (TWI_WPSR) Write Protection Violation Source */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR_Pos 0 -#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */ -#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR_Pos 0 -#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */ -#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR_Pos 0 -#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */ -#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR_Pos 0 -#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */ -#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR_Pos 0 -#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */ -#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR_Pos 0 -#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */ -#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR_Pos 0 -#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR_Pos 0 -#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */ -#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -#define TWI_PTCR_RXCBEN (0x1u << 16) /**< \brief (TWI_PTCR) Receiver Circular Buffer Enable */ -#define TWI_PTCR_RXCBDIS (0x1u << 17) /**< \brief (TWI_PTCR) Receiver Circular Buffer Disable */ -#define TWI_PTCR_TXCBEN (0x1u << 18) /**< \brief (TWI_PTCR) Transmitter Circular Buffer Enable */ -#define TWI_PTCR_TXCBDIS (0x1u << 19) /**< \brief (TWI_PTCR) Transmitter Circular Buffer Disable */ -#define TWI_PTCR_ERRCLR (0x1u << 24) /**< \brief (TWI_PTCR) Transfer Bus Error Clear */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ -#define TWI_PTSR_RXCBEN (0x1u << 16) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXCBEN (0x1u << 18) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ -#define TWI_PTSR_ERR (0x1u << 24) /**< \brief (TWI_PTSR) Transfer Bus Error (clear on read) */ - -/*@}*/ - - -#endif /* _SAMG55_TWI_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_udp.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_udp.h deleted file mode 100644 index d7607f28f83..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_udp.h +++ /dev/null @@ -1,191 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_UDP_COMPONENT_ -#define _SAMG55_UDP_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup SAMG55_UDP USB Device Port */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Udp hardware registers */ -typedef struct { - __I uint32_t UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - __IO uint32_t UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - __IO uint32_t UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - __I uint32_t Reserved1[1]; - __O uint32_t UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - __O uint32_t UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - __I uint32_t UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - __I uint32_t UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - __O uint32_t UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - __I uint32_t Reserved2[1]; - __IO uint32_t UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - __I uint32_t Reserved3[1]; - __IO uint32_t UDP_CSR[6]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */ - __I uint32_t Reserved4[2]; - __IO uint32_t UDP_FDR[6]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */ - __I uint32_t Reserved5[3]; - __IO uint32_t UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM_Pos 0 -#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD_Pos 0 -#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos))) -#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -/* -------- UDP_CSR[6] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */ -#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[6]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[6]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[6]) Received Setup */ -#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[6]) Stall Sent */ -#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[6]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[6]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[6]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[6]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE_Pos 8 -#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[6]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[6]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[6]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[6]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[6]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[6]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[6]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[6]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[6]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[6]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT_Pos 16 -#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[6]) Number of Bytes Available in the FIFO */ -#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos))) -#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[6]) A CRC error has been detected in an isochronous transfer */ -/* -------- UDP_FDR[6] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */ -#define UDP_FDR_FIFO_DATA_Pos 0 -#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[6]) FIFO Data Value */ -#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos))) -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pull-up On */ - -/*@}*/ - - -#endif /* _SAMG55_UDP_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_uhp.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_uhp.h deleted file mode 100644 index d0ee6dbb5b5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_uhp.h +++ /dev/null @@ -1,253 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_UHP_COMPONENT_ -#define _SAMG55_UHP_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Host Port */ -/* ============================================================================= */ -/** \addtogroup SAMG55_UHP USB Host Port */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Uhp hardware registers */ -typedef struct { - __I uint32_t UHP_HCREVISION; /**< \brief (Uhp Offset: 0x00) OHCI Revision Number Register */ - __IO uint32_t UHP_HCCONTROL; /**< \brief (Uhp Offset: 0x04) HC Operating Mode Register */ - __IO uint32_t UHP_HCCOMMANDSTATUS; /**< \brief (Uhp Offset: 0x08) HC Command and Status Register */ - __IO uint32_t UHP_HCINTERRUPTSTATUS; /**< \brief (Uhp Offset: 0x0C) HC Interrupt and Status Register */ - __IO uint32_t UHP_HCINTERRUPTENABLE; /**< \brief (Uhp Offset: 0x10) HC Interrupt Enable Register */ - __IO uint32_t UHP_HCINTERRUPTDISABLE; /**< \brief (Uhp Offset: 0x14) HC Interrupt Disable Register */ - __IO uint32_t UHP_HCHCCA; /**< \brief (Uhp Offset: 0x18) HC HCCA Address Register */ - __I uint32_t UHP_HCPERIODCURRENTED; /**< \brief (Uhp Offset: 0x1C) HC Current Periodic Register */ - __IO uint32_t UHP_HCCONTROLHEADED; /**< \brief (Uhp Offset: 0x20) HC Head Control Register */ - __IO uint32_t UHP_HCCONTROLCURRENTED; /**< \brief (Uhp Offset: 0x24) HC Current Control Register */ - __IO uint32_t UHP_HCBULKHEADED; /**< \brief (Uhp Offset: 0x28) HC Head Bulk Register */ - __IO uint32_t UHP_HCBULKCURRENTED; /**< \brief (Uhp Offset: 0x2C) HC Current Bulk Register */ - __I uint32_t UHP_HCDONEHEAD; /**< \brief (Uhp Offset: 0x30) HC Head Done Register */ - __IO uint32_t UHP_HCFMINTERVAL; /**< \brief (Uhp Offset: 0x34) HC Frame Interval Register */ - __I uint32_t UHP_HCFMREMAINING; /**< \brief (Uhp Offset: 0x38) HC Frame Remaining Register */ - __I uint32_t UHP_HCFMNUMBER; /**< \brief (Uhp Offset: 0x3C) HC Frame Number Register */ - __IO uint32_t UHP_HCPERIODICSTART; /**< \brief (Uhp Offset: 0x40) HC Periodic Start Register */ - __IO uint32_t UHP_HCLSTHRESHOLD; /**< \brief (Uhp Offset: 0x44) HC Low-Speed Threshold Register */ - __IO uint32_t UHP_HCRHDESCRIPTORA; /**< \brief (Uhp Offset: 0x48) HC Root Hub A Register */ - __IO uint32_t UHP_HCRHDESCRIPTORB; /**< \brief (Uhp Offset: 0x4C) HC Root Hub B Register */ - __IO uint32_t UHP_HCRHSTATUS; /**< \brief (Uhp Offset: 0x50) HC Root Hub Status Register */ - __IO uint32_t UHP_HCRHPORTSTATUS[2]; /**< \brief (Uhp Offset: 0x54) HC Port 1 Status and Control Register */ -} Uhp; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- UHP_HCREVISION : (UHP Offset: 0x00) OHCI Revision Number Register -------- */ -#define UHP_HCREVISION_REV_Pos 0 -#define UHP_HCREVISION_REV_Msk (0xffu << UHP_HCREVISION_REV_Pos) /**< \brief (UHP_HCREVISION) OHCI revision number */ -/* -------- UHP_HCCONTROL : (UHP Offset: 0x04) HC Operating Mode Register -------- */ -#define UHP_HCCONTROL_CBSR_Pos 0 -#define UHP_HCCONTROL_CBSR_Msk (0x3u << UHP_HCCONTROL_CBSR_Pos) /**< \brief (UHP_HCCONTROL) Control/bulk service ratio */ -#define UHP_HCCONTROL_CBSR(value) ((UHP_HCCONTROL_CBSR_Msk & ((value) << UHP_HCCONTROL_CBSR_Pos))) -#define UHP_HCCONTROL_PLE (0x1u << 2) /**< \brief (UHP_HCCONTROL) Periodic list enable */ -#define UHP_HCCONTROL_IE (0x1u << 3) /**< \brief (UHP_HCCONTROL) Isochronous enable */ -#define UHP_HCCONTROL_CLE (0x1u << 4) /**< \brief (UHP_HCCONTROL) Control list enable */ -#define UHP_HCCONTROL_BLE (0x1u << 5) /**< \brief (UHP_HCCONTROL) Bulk list enable */ -#define UHP_HCCONTROL_HCFS_Pos 6 -#define UHP_HCCONTROL_HCFS_Msk (0x3u << UHP_HCCONTROL_HCFS_Pos) /**< \brief (UHP_HCCONTROL) Host controller functional state */ -#define UHP_HCCONTROL_HCFS(value) ((UHP_HCCONTROL_HCFS_Msk & ((value) << UHP_HCCONTROL_HCFS_Pos))) -#define UHP_HCCONTROL_IR (0x1u << 8) /**< \brief (UHP_HCCONTROL) Interrupt routing */ -#define UHP_HCCONTROL_RWC (0x1u << 9) /**< \brief (UHP_HCCONTROL) Remote wake-up connected */ -#define UHP_HCCONTROL_RWE (0x1u << 10) /**< \brief (UHP_HCCONTROL) Remote wake-up enable */ -/* -------- UHP_HCCOMMANDSTATUS : (UHP Offset: 0x08) HC Command and Status Register -------- */ -#define UHP_HCCOMMANDSTATUS_HCR (0x1u << 0) /**< \brief (UHP_HCCOMMANDSTATUS) Host controller reset (read/write) */ -#define UHP_HCCOMMANDSTATUS_CLF (0x1u << 1) /**< \brief (UHP_HCCOMMANDSTATUS) Control list filled (read/write) */ -#define UHP_HCCOMMANDSTATUS_BLF (0x1u << 2) /**< \brief (UHP_HCCOMMANDSTATUS) Bulk list filled (read/write) */ -#define UHP_HCCOMMANDSTATUS_OCR (0x1u << 3) /**< \brief (UHP_HCCOMMANDSTATUS) Ownership change request (read/write) */ -#define UHP_HCCOMMANDSTATUS_SOC_Pos 16 -#define UHP_HCCOMMANDSTATUS_SOC_Msk (0x3u << UHP_HCCOMMANDSTATUS_SOC_Pos) /**< \brief (UHP_HCCOMMANDSTATUS) Scheduling overrun count (read-only) */ -#define UHP_HCCOMMANDSTATUS_SOC(value) ((UHP_HCCOMMANDSTATUS_SOC_Msk & ((value) << UHP_HCCOMMANDSTATUS_SOC_Pos))) -/* -------- UHP_HCINTERRUPTSTATUS : (UHP Offset: 0x0C) HC Interrupt and Status Register -------- */ -#define UHP_HCINTERRUPTSTATUS_SO (0x1u << 0) /**< \brief (UHP_HCINTERRUPTSTATUS) Scheduling overrun (read/write, write '1' to clear) */ -#define UHP_HCINTERRUPTSTATUS_WDH (0x1u << 1) /**< \brief (UHP_HCINTERRUPTSTATUS) Write done head (read/write, write '1' to clear) */ -#define UHP_HCINTERRUPTSTATUS_SF (0x1u << 2) /**< \brief (UHP_HCINTERRUPTSTATUS) Start of frame (read/write, write '1' to clear) */ -#define UHP_HCINTERRUPTSTATUS_RD (0x1u << 3) /**< \brief (UHP_HCINTERRUPTSTATUS) Resume detected (read/write, write '1' to clear) */ -#define UHP_HCINTERRUPTSTATUS_UE (0x1u << 4) /**< \brief (UHP_HCINTERRUPTSTATUS) Unrecoverable error (read/write, write '1' to clear) */ -#define UHP_HCINTERRUPTSTATUS_FNO (0x1u << 5) /**< \brief (UHP_HCINTERRUPTSTATUS) Frame number overflow (read/write, write '1' to clear) */ -#define UHP_HCINTERRUPTSTATUS_RHSC (0x1u << 6) /**< \brief (UHP_HCINTERRUPTSTATUS) Root hub status change (read/write, write '1' to clear) */ -#define UHP_HCINTERRUPTSTATUS_OC (0x1u << 30) /**< \brief (UHP_HCINTERRUPTSTATUS) Ownership change (read-only) */ -/* -------- UHP_HCINTERRUPTENABLE : (UHP Offset: 0x10) HC Interrupt Enable Register -------- */ -#define UHP_HCINTERRUPTENABLE_SO (0x1u << 0) /**< \brief (UHP_HCINTERRUPTENABLE) Scheduling overrun (read/write, write '1' to set) */ -#define UHP_HCINTERRUPTENABLE_WDH (0x1u << 1) /**< \brief (UHP_HCINTERRUPTENABLE) Write done head (read/write, write '1' to set) */ -#define UHP_HCINTERRUPTENABLE_SF (0x1u << 2) /**< \brief (UHP_HCINTERRUPTENABLE) Start of frame (read/write, write '1' to set) */ -#define UHP_HCINTERRUPTENABLE_RD (0x1u << 3) /**< \brief (UHP_HCINTERRUPTENABLE) Resume detected (read/write, write '1' to set) */ -#define UHP_HCINTERRUPTENABLE_UE (0x1u << 4) /**< \brief (UHP_HCINTERRUPTENABLE) Unrecoverable error (read/write, write '1' to set) */ -#define UHP_HCINTERRUPTENABLE_FNO (0x1u << 5) /**< \brief (UHP_HCINTERRUPTENABLE) Frame number overflow (read/write, write '1' to set) */ -#define UHP_HCINTERRUPTENABLE_RHSC (0x1u << 6) /**< \brief (UHP_HCINTERRUPTENABLE) Root hub status change (read/write, write '1' to set) */ -#define UHP_HCINTERRUPTENABLE_OC (0x1u << 30) /**< \brief (UHP_HCINTERRUPTENABLE) Ownership change (read-only) */ -#define UHP_HCINTERRUPTENABLE_MIE (0x1u << 31) /**< \brief (UHP_HCINTERRUPTENABLE) Master interrupt enable (read/write, write '1' to set) */ -/* -------- UHP_HCINTERRUPTDISABLE : (UHP Offset: 0x14) HC Interrupt Disable Register -------- */ -#define UHP_HCINTERRUPTDISABLE_SO (0x1u << 0) /**< \brief (UHP_HCINTERRUPTDISABLE) Scheduling overrun (read/write) */ -#define UHP_HCINTERRUPTDISABLE_WDH (0x1u << 1) /**< \brief (UHP_HCINTERRUPTDISABLE) Write done head (read/write) */ -#define UHP_HCINTERRUPTDISABLE_SF (0x1u << 2) /**< \brief (UHP_HCINTERRUPTDISABLE) Start of frame (read/write) */ -#define UHP_HCINTERRUPTDISABLE_RD (0x1u << 3) /**< \brief (UHP_HCINTERRUPTDISABLE) Resume detected (read/write) */ -#define UHP_HCINTERRUPTDISABLE_UE (0x1u << 4) /**< \brief (UHP_HCINTERRUPTDISABLE) Unrecoverable error (read/write) */ -#define UHP_HCINTERRUPTDISABLE_FNO (0x1u << 5) /**< \brief (UHP_HCINTERRUPTDISABLE) Frame number overflow (read/write) */ -#define UHP_HCINTERRUPTDISABLE_RHSC (0x1u << 6) /**< \brief (UHP_HCINTERRUPTDISABLE) Root hub status change (read/write) */ -#define UHP_HCINTERRUPTDISABLE_OC (0x1u << 30) /**< \brief (UHP_HCINTERRUPTDISABLE) Ownership change (read-only) */ -#define UHP_HCINTERRUPTDISABLE_MIE (0x1u << 31) /**< \brief (UHP_HCINTERRUPTDISABLE) Master interrupt enable (read/write) */ -/* -------- UHP_HCHCCA : (UHP Offset: 0x18) HC HCCA Address Register -------- */ -#define UHP_HCHCCA_HCCA_Pos 8 -#define UHP_HCHCCA_HCCA_Msk (0xffffffu << UHP_HCHCCA_HCCA_Pos) /**< \brief (UHP_HCHCCA) Physical address of the beginning of the HCCA */ -#define UHP_HCHCCA_HCCA(value) ((UHP_HCHCCA_HCCA_Msk & ((value) << UHP_HCHCCA_HCCA_Pos))) -/* -------- UHP_HCPERIODCURRENTED : (UHP Offset: 0x1C) HC Current Periodic Register -------- */ -#define UHP_HCPERIODCURRENTED_PCED_Pos 4 -#define UHP_HCPERIODCURRENTED_PCED_Msk (0xfffffffu << UHP_HCPERIODCURRENTED_PCED_Pos) /**< \brief (UHP_HCPERIODCURRENTED) Physical address of the current ED on the periodic ED list */ -/* -------- UHP_HCCONTROLHEADED : (UHP Offset: 0x20) HC Head Control Register -------- */ -#define UHP_HCCONTROLHEADED_CHED_Pos 4 -#define UHP_HCCONTROLHEADED_CHED_Msk (0xfffffffu << UHP_HCCONTROLHEADED_CHED_Pos) /**< \brief (UHP_HCCONTROLHEADED) Physical address of the head ED on the control ED list */ -#define UHP_HCCONTROLHEADED_CHED(value) ((UHP_HCCONTROLHEADED_CHED_Msk & ((value) << UHP_HCCONTROLHEADED_CHED_Pos))) -/* -------- UHP_HCCONTROLCURRENTED : (UHP Offset: 0x24) HC Current Control Register -------- */ -#define UHP_HCCONTROLCURRENTED_CCED_Pos 4 -#define UHP_HCCONTROLCURRENTED_CCED_Msk (0xfffffffu << UHP_HCCONTROLCURRENTED_CCED_Pos) /**< \brief (UHP_HCCONTROLCURRENTED) Physical address of the current ED on the control ED list */ -#define UHP_HCCONTROLCURRENTED_CCED(value) ((UHP_HCCONTROLCURRENTED_CCED_Msk & ((value) << UHP_HCCONTROLCURRENTED_CCED_Pos))) -/* -------- UHP_HCBULKHEADED : (UHP Offset: 0x28) HC Head Bulk Register -------- */ -#define UHP_HCBULKHEADED_BHED_Pos 4 -#define UHP_HCBULKHEADED_BHED_Msk (0xfffffffu << UHP_HCBULKHEADED_BHED_Pos) /**< \brief (UHP_HCBULKHEADED) Physical address of the head ED on the bulk ED list */ -#define UHP_HCBULKHEADED_BHED(value) ((UHP_HCBULKHEADED_BHED_Msk & ((value) << UHP_HCBULKHEADED_BHED_Pos))) -/* -------- UHP_HCBULKCURRENTED : (UHP Offset: 0x2C) HC Current Bulk Register -------- */ -#define UHP_HCBULKCURRENTED_BCED_Pos 4 -#define UHP_HCBULKCURRENTED_BCED_Msk (0xfffffffu << UHP_HCBULKCURRENTED_BCED_Pos) /**< \brief (UHP_HCBULKCURRENTED) Physical address of the current ED on the bulk ED list */ -#define UHP_HCBULKCURRENTED_BCED(value) ((UHP_HCBULKCURRENTED_BCED_Msk & ((value) << UHP_HCBULKCURRENTED_BCED_Pos))) -/* -------- UHP_HCDONEHEAD : (UHP Offset: 0x30) HC Head Done Register -------- */ -#define UHP_HCDONEHEAD_DH_Pos 4 -#define UHP_HCDONEHEAD_DH_Msk (0xfffffffu << UHP_HCDONEHEAD_DH_Pos) /**< \brief (UHP_HCDONEHEAD) Physical address of the last TD that has added to the done queue */ -/* -------- UHP_HCFMINTERVAL : (UHP Offset: 0x34) HC Frame Interval Register -------- */ -#define UHP_HCFMINTERVAL_FRAMEINTERVAL_Pos 0 -#define UHP_HCFMINTERVAL_FRAMEINTERVAL_Msk (0x3fffu << UHP_HCFMINTERVAL_FRAMEINTERVAL_Pos) /**< \brief (UHP_HCFMINTERVAL) Frame interval */ -#define UHP_HCFMINTERVAL_FRAMEINTERVAL(value) ((UHP_HCFMINTERVAL_FRAMEINTERVAL_Msk & ((value) << UHP_HCFMINTERVAL_FRAMEINTERVAL_Pos))) -#define UHP_HCFMINTERVAL_FSMPS_Pos 16 -#define UHP_HCFMINTERVAL_FSMPS_Msk (0x7fffu << UHP_HCFMINTERVAL_FSMPS_Pos) /**< \brief (UHP_HCFMINTERVAL) Largest data packet */ -#define UHP_HCFMINTERVAL_FSMPS(value) ((UHP_HCFMINTERVAL_FSMPS_Msk & ((value) << UHP_HCFMINTERVAL_FSMPS_Pos))) -#define UHP_HCFMINTERVAL_FIT (0x1u << 31) /**< \brief (UHP_HCFMINTERVAL) Frame interval toggle */ -/* -------- UHP_HCFMREMAINING : (UHP Offset: 0x38) HC Frame Remaining Register -------- */ -#define UHP_HCFMREMAINING_FR_Pos 0 -#define UHP_HCFMREMAINING_FR_Msk (0x3fffu << UHP_HCFMREMAINING_FR_Pos) /**< \brief (UHP_HCFMREMAINING) Frame remaining */ -#define UHP_HCFMREMAINING_FRT (0x1u << 31) /**< \brief (UHP_HCFMREMAINING) Frame remaining toggle */ -/* -------- UHP_HCFMNUMBER : (UHP Offset: 0x3C) HC Frame Number Register -------- */ -#define UHP_HCFMNUMBER_FN_Pos 0 -#define UHP_HCFMNUMBER_FN_Msk (0xffffu << UHP_HCFMNUMBER_FN_Pos) /**< \brief (UHP_HCFMNUMBER) Frame number */ -/* -------- UHP_HCPERIODICSTART : (UHP Offset: 0x40) HC Periodic Start Register -------- */ -#define UHP_HCPERIODICSTART_PS_Pos 0 -#define UHP_HCPERIODICSTART_PS_Msk (0x3fffu << UHP_HCPERIODICSTART_PS_Pos) /**< \brief (UHP_HCPERIODICSTART) Periodic start */ -#define UHP_HCPERIODICSTART_PS(value) ((UHP_HCPERIODICSTART_PS_Msk & ((value) << UHP_HCPERIODICSTART_PS_Pos))) -/* -------- UHP_HCLSTHRESHOLD : (UHP Offset: 0x44) HC Low-Speed Threshold Register -------- */ -#define UHP_HCLSTHRESHOLD_LST_Pos 0 -#define UHP_HCLSTHRESHOLD_LST_Msk (0x3fffu << UHP_HCLSTHRESHOLD_LST_Pos) /**< \brief (UHP_HCLSTHRESHOLD) Low-speed threshold */ -#define UHP_HCLSTHRESHOLD_LST(value) ((UHP_HCLSTHRESHOLD_LST_Msk & ((value) << UHP_HCLSTHRESHOLD_LST_Pos))) -/* -------- UHP_HCRHDESCRIPTORA : (UHP Offset: 0x48) HC Root Hub A Register -------- */ -#define UHP_HCRHDESCRIPTORA_NDP_Pos 0 -#define UHP_HCRHDESCRIPTORA_NDP_Msk (0xffu << UHP_HCRHDESCRIPTORA_NDP_Pos) /**< \brief (UHP_HCRHDESCRIPTORA) Number of downstream ports (read-only) */ -#define UHP_HCRHDESCRIPTORA_NDP(value) ((UHP_HCRHDESCRIPTORA_NDP_Msk & ((value) << UHP_HCRHDESCRIPTORA_NDP_Pos))) -#define UHP_HCRHDESCRIPTORA_PSM (0x1u << 8) /**< \brief (UHP_HCRHDESCRIPTORA) Power switching mode (read/write) */ -#define UHP_HCRHDESCRIPTORA_NPS (0x1u << 9) /**< \brief (UHP_HCRHDESCRIPTORA) No power switching (read/write) */ -#define UHP_HCRHDESCRIPTORA_DT (0x1u << 10) /**< \brief (UHP_HCRHDESCRIPTORA) Device type (read-only) */ -#define UHP_HCRHDESCRIPTORA_OCPM (0x1u << 11) /**< \brief (UHP_HCRHDESCRIPTORA) Overcurrent protection mode (read/write) */ -#define UHP_HCRHDESCRIPTORA_NOCP (0x1u << 12) /**< \brief (UHP_HCRHDESCRIPTORA) No overcurrent protection (read/write) */ -#define UHP_HCRHDESCRIPTORA_POTPG_Pos 24 -#define UHP_HCRHDESCRIPTORA_POTPG_Msk (0xffu << UHP_HCRHDESCRIPTORA_POTPG_Pos) /**< \brief (UHP_HCRHDESCRIPTORA) Power-on to power-good time (read/write) */ -#define UHP_HCRHDESCRIPTORA_POTPG(value) ((UHP_HCRHDESCRIPTORA_POTPG_Msk & ((value) << UHP_HCRHDESCRIPTORA_POTPG_Pos))) -/* -------- UHP_HCRHDESCRIPTORB : (UHP Offset: 0x4C) HC Root Hub B Register -------- */ -#define UHP_HCRHDESCRIPTORB_DR0 (0x1u << 0) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR1 (0x1u << 1) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR2 (0x1u << 2) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR3 (0x1u << 3) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR4 (0x1u << 4) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR5 (0x1u << 5) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR6 (0x1u << 6) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR7 (0x1u << 7) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR8 (0x1u << 8) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR9 (0x1u << 9) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR10 (0x1u << 10) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR11 (0x1u << 11) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR12 (0x1u << 12) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR13 (0x1u << 13) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR14 (0x1u << 14) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_DR15 (0x1u << 15) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM0 (0x1u << 16) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM1 (0x1u << 17) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM2 (0x1u << 18) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM3 (0x1u << 19) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM4 (0x1u << 20) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM5 (0x1u << 21) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM6 (0x1u << 22) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM7 (0x1u << 23) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM8 (0x1u << 24) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM9 (0x1u << 25) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM10 (0x1u << 26) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM11 (0x1u << 27) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM12 (0x1u << 28) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM13 (0x1u << 29) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM14 (0x1u << 30) /**< \brief (UHP_HCRHDESCRIPTORB) */ -#define UHP_HCRHDESCRIPTORB_PPCM15 (0x1u << 31) /**< \brief (UHP_HCRHDESCRIPTORB) */ -/* -------- UHP_HCRHSTATUS : (UHP Offset: 0x50) HC Root Hub Status Register -------- */ -#define UHP_HCRHSTATUS_LPS (0x1u << 0) /**< \brief (UHP_HCRHSTATUS) Local power status (read/write) */ -#define UHP_HCRHSTATUS_OCI (0x1u << 1) /**< \brief (UHP_HCRHSTATUS) Overcurrent indicator (read-only) */ -#define UHP_HCRHSTATUS_DRWE (0x1u << 15) /**< \brief (UHP_HCRHSTATUS) Device remote wake-up enable (read/write) */ -#define UHP_HCRHSTATUS_LPSC (0x1u << 16) /**< \brief (UHP_HCRHSTATUS) Local power status change (read/write) */ -#define UHP_HCRHSTATUS_OCIC (0x1u << 17) /**< \brief (UHP_HCRHSTATUS) Overcurrent indication change (read/write) */ -#define UHP_HCRHSTATUS_CRWE (0x1u << 31) /**< \brief (UHP_HCRHSTATUS) Clear remote wake-up enable (read/write) */ -/* -------- UHP_HCRHPORTSTATUS[2] : (UHP Offset: 0x54) HC Port 1 Status and Control Register -------- */ -#define UHP_HCRHPORTSTATUS_CCS_CPE (0x1u << 0) /**< \brief (UHP_HCRHPORTSTATUS[2]) */ -#define UHP_HCRHPORTSTATUS_PES_SPE (0x1u << 1) /**< \brief (UHP_HCRHPORTSTATUS[2]) */ -#define UHP_HCRHPORTSTATUS_PSS_SPS (0x1u << 2) /**< \brief (UHP_HCRHPORTSTATUS[2]) */ -#define UHP_HCRHPORTSTATUS_POCI_CSS (0x1u << 3) /**< \brief (UHP_HCRHPORTSTATUS[2]) */ -#define UHP_HCRHPORTSTATUS_PRS_SPR (0x1u << 4) /**< \brief (UHP_HCRHPORTSTATUS[2]) */ -#define UHP_HCRHPORTSTATUS_PPS_SPP (0x1u << 8) /**< \brief (UHP_HCRHPORTSTATUS[2]) */ -#define UHP_HCRHPORTSTATUS_LSDA_CPP (0x1u << 9) /**< \brief (UHP_HCRHPORTSTATUS[2]) */ -#define UHP_HCRHPORTSTATUS_CSC (0x1u << 16) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 connect status change (read/write, write '1' to clear) */ -#define UHP_HCRHPORTSTATUS_PESC (0x1u << 17) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 enable status change (read/write, write '1' to clear) */ -#define UHP_HCRHPORTSTATUS_PSSC (0x1u << 18) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 suspend status change (read/write, write '1' to clear) */ -#define UHP_HCRHPORTSTATUS_OCIC (0x1u << 19) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 overcurrent indicator change (read/write) */ -#define UHP_HCRHPORTSTATUS_PRSC (0x1u << 20) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 reset status change (read/write, write '1' to clear) */ - -/*@}*/ - - -#endif /* _SAMG55_UHP_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_usart.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_usart.h deleted file mode 100644 index 8727e5536d0..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_usart.h +++ /dev/null @@ -1,416 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART_COMPONENT_ -#define _SAMG55_USART_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup SAMG55_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Usart hardware registers */ -typedef struct { - __O uint32_t US_CR; /**< \brief (Usart Offset: 0x000) USART Control Register */ - __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x004) USART Mode Register */ - __O uint32_t US_IER; /**< \brief (Usart Offset: 0x008) USART Interrupt Enable Register */ - __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x00C) USART Interrupt Disable Register */ - __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x010) USART Interrupt Mask Register */ - __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x014) USART Channel Status Register */ - __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x018) USART Receive Holding Register */ - __O uint32_t US_THR; /**< \brief (Usart Offset: 0x01C) USART Transmit Holding Register */ - __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x020) USART Baud Rate Generator Register */ - __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x024) USART Receiver Time-out Register */ - __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x028) USART Transmitter Timeguard Register */ - __I uint32_t Reserved1[5]; - __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x040) USART FI DI Ratio Register */ - __I uint32_t US_NER; /**< \brief (Usart Offset: 0x044) USART Number of Errors Register */ - __I uint32_t Reserved2[3]; - __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x054) USART LIN Mode Register */ - __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x058) USART LIN Identifier Register */ - __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x05C) USART LIN Baud Rate Register */ - __I uint32_t Reserved3[12]; - __IO uint32_t US_CMPR; /**< \brief (Usart Offset: 0x090) USART Comparison Register */ - __I uint32_t Reserved4[20]; - __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x0E4) USART Write Protection Mode Register */ - __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x0E8) USART Write Protection Status Register */ - __I uint32_t Reserved5[5]; - __IO uint32_t US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - __IO uint32_t US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - __IO uint32_t US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - __IO uint32_t US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - __IO uint32_t US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - __IO uint32_t US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - __IO uint32_t US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - __IO uint32_t US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - __O uint32_t US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - __I uint32_t US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- US_CR : (USART Offset: 0x000) USART Control Register -------- */ -#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */ -#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */ -#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ -#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ -#define US_CR_REQCLR (0x1u << 28) /**< \brief (US_CR) Request to Clear the Comparison Trigger */ -#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ -#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x004) USART Mode Register -------- */ -#define US_MR_USART_MODE_Pos 0 -#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ -#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ -#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 mode */ -#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ -#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ -#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ -#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN master mode */ -#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave mode */ -#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master mode */ -#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave mode */ -#define US_MR_USCLKS_Pos 4 -#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ -#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock Divided (DIV=8) is selected */ -#define US_MR_USCLKS_PMC_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected.If the SCK pin is driven (CLKO=1), the CD field must be greater than 1. */ -#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) External pin (SCK) is selected */ -#define US_MR_CHRL_Pos 6 -#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ -#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ -#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ -#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ -#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ -#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ -#define US_MR_PAR_Pos 9 -#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ -#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ -#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ -#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ -#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ -#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ -#define US_MR_NBSTOP_Pos 12 -#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ -#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bits (SYNC = 0) or reserved (SYNC = 1) */ -#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ -#define US_MR_CHMODE_Pos 14 -#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ -#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ -#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ -#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ -#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ -#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ -#define US_MR_MAX_ITERATION_Pos 24 -#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ -#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) -#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ -#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ -#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ -#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ -/* -------- US_IER : (USART Offset: 0x008) USART Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Buffer Interrupt Enable (available in all USART modes of operation) */ -#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Buffer Interrupt Enable (available in all USART modes of operation) */ -#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ -#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation) */ -#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Receive Buffer Full Interrupt Enable (available in all USART modes of operation) */ -#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_CMP (0x1u << 22) /**< \brief (US_IER) Comparison Interrupt Enable */ -#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ -#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ -#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ -#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ -#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ -#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ -#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ -#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ -#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ -#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ -#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x00C) USART Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Buffer Interrupt Enable (available in all USART modes of operation) */ -#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Buffer Interrupt Disable (available in all USART modes of operation) */ -#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ -#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ -#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation) */ -#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Receive Buffer Full Interrupt Enable (available in all USART modes of operation) */ -#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_CMP (0x1u << 22) /**< \brief (US_IDR) Comparison Interrupt Disable */ -#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ -#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ -#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ -#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ -#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ -#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ -#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ -#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ -#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ -#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ -#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x010) USART Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Buffer Interrupt Mask (available in all USART modes of operation) */ -#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Buffer Interrupt Mask (available in all USART modes of operation) */ -#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ -#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation) */ -#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Receive Buffer Full Interrupt Mask (available in all USART modes of operation) */ -#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_CMP (0x1u << 22) /**< \brief (US_IMR) Comparison Interrupt Mask */ -#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ -#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ -#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ -#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ -#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ -#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ -#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ -#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ -#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ -#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ -#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x014) USART Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (automatically set / cleared) */ -#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (automatically set / cleared) */ -#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by US_CR.RSTSTA command) */ -#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of RX Buffer (automatically set / cleared) */ -#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of TX Buffer (automatically set / cleared) */ -#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by US_CR.STTTO command) */ -#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (automatically set / cleared) */ -#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by US_CR.RSTIT command) */ -#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) TX Buffer Empty (automatically set / cleared) */ -#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) RX Buffer Full (automatically set / cleared) */ -#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by US_CR.RSTNACK command) */ -#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (clear on read) */ -#define US_CSR_CMP (0x1u << 22) /**< \brief (US_CSR) Comparison Status (cleared by US_CR.RSTSTA command) */ -#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input (automatically set / cleared) */ -#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by US_CR.RSTSTA) */ -#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ -#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by US_CR.RSTSTA command) */ -#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by US_CR.RSTSTA command) */ -/* -------- US_RHR : (USART Offset: 0x018) USART Receive Holding Register -------- */ -#define US_RHR_RXCHR_Pos 0 -#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x01C) USART Transmit Holding Register -------- */ -#define US_THR_TXCHR_Pos 0 -#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) -#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ -/* -------- US_BRGR : (USART Offset: 0x020) USART Baud Rate Generator Register -------- */ -#define US_BRGR_CD_Pos 0 -#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) -#define US_BRGR_FP_Pos 16 -#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ -#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) -/* -------- US_RTOR : (USART Offset: 0x024) USART Receiver Time-out Register -------- */ -#define US_RTOR_TO_Pos 0 -#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ -#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) -/* -------- US_TTGR : (USART Offset: 0x028) USART Transmitter Timeguard Register -------- */ -#define US_TTGR_TG_Pos 0 -#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ -#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) -/* -------- US_FIDI : (USART Offset: 0x040) USART FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO_Pos 0 -#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) -/* -------- US_NER : (USART Offset: 0x044) USART Number of Errors Register -------- */ -#define US_NER_NB_ERRORS_Pos 0 -#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ -/* -------- US_LINMR : (USART Offset: 0x054) USART LIN Mode Register -------- */ -#define US_LINMR_NACT_Pos 0 -#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ -#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ -#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ -#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ -#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ -#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ -#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ -#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ -#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ -#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ -#define US_LINMR_DLC_Pos 8 -#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ -#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) -#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */ -#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ -/* -------- US_LINIR : (USART Offset: 0x058) USART LIN Identifier Register -------- */ -#define US_LINIR_IDCHR_Pos 0 -#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ -#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) -/* -------- US_LINBRR : (USART Offset: 0x05C) USART LIN Baud Rate Register -------- */ -#define US_LINBRR_LINCD_Pos 0 -#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ -#define US_LINBRR_LINFP_Pos 16 -#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ -/* -------- US_CMPR : (USART Offset: 0x090) USART Comparison Register -------- */ -#define US_CMPR_VAL1_Pos 0 -#define US_CMPR_VAL1_Msk (0x1ffu << US_CMPR_VAL1_Pos) /**< \brief (US_CMPR) First Comparison Value for Received Character */ -#define US_CMPR_VAL1(value) ((US_CMPR_VAL1_Msk & ((value) << US_CMPR_VAL1_Pos))) -#define US_CMPR_CMPMODE (0x1u << 12) /**< \brief (US_CMPR) Comparison Mode */ -#define US_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (US_CMPR) Any character is received and comparison function drives CMP flag. */ -#define US_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (US_CMPR) Comparison condition must be met to start reception of all incoming charactersuntil REQCLR is set. */ -#define US_CMPR_CMPPAR (0x1u << 14) /**< \brief (US_CMPR) Compare Parity */ -#define US_CMPR_VAL2_Pos 16 -#define US_CMPR_VAL2_Msk (0x1ffu << US_CMPR_VAL2_Pos) /**< \brief (US_CMPR) Second Comparison Value for Received Character */ -#define US_CMPR_VAL2(value) ((US_CMPR_VAL2_Msk & ((value) << US_CMPR_VAL2_Pos))) -/* -------- US_WPMR : (USART Offset: 0x0E4) USART Write Protection Mode Register -------- */ -#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ -#define US_WPMR_WPKEY_Pos 8 -#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ -#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ -/* -------- US_WPSR : (USART Offset: 0x0E8) USART Write Protection Status Register -------- */ -#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ -#define US_WPSR_WPVSRC_Pos 8 -#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR_Pos 0 -#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */ -#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos))) -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR_Pos 0 -#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */ -#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos))) -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR_Pos 0 -#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */ -#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos))) -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR_Pos 0 -#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */ -#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos))) -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR_Pos 0 -#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */ -#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos))) -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR_Pos 0 -#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */ -#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos))) -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR_Pos 0 -#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */ -#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos))) -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR_Pos 0 -#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */ -#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos))) -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -#define US_PTCR_RXCBEN (0x1u << 16) /**< \brief (US_PTCR) Receiver Circular Buffer Enable */ -#define US_PTCR_RXCBDIS (0x1u << 17) /**< \brief (US_PTCR) Receiver Circular Buffer Disable */ -#define US_PTCR_TXCBEN (0x1u << 18) /**< \brief (US_PTCR) Transmitter Circular Buffer Enable */ -#define US_PTCR_TXCBDIS (0x1u << 19) /**< \brief (US_PTCR) Transmitter Circular Buffer Disable */ -#define US_PTCR_ERRCLR (0x1u << 24) /**< \brief (US_PTCR) Transfer Bus Error Clear */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ -#define US_PTSR_RXCBEN (0x1u << 16) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXCBEN (0x1u << 18) /**< \brief (US_PTSR) Transmitter Transfer Enable */ -#define US_PTSR_ERR (0x1u << 24) /**< \brief (US_PTSR) Transfer Bus Error (clear on read) */ - -/*@}*/ - - -#endif /* _SAMG55_USART_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_wdt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_wdt.h deleted file mode 100644 index 1a4f0e60abd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_wdt.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_WDT_COMPONENT_ -#define _SAMG55_WDT_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup SAMG55_WDT Watchdog Timer */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Wdt hardware registers */ -typedef struct { - __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY_Pos 24 -#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password. */ -#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV_Pos 0 -#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) -#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD_Pos 16 -#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) -#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - - -#endif /* _SAMG55_WDT_COMPONENT_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_adc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_adc.h deleted file mode 100644 index 6f80970c57c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_adc.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_ADC_INSTANCE_ -#define _SAMG55_ADC_INSTANCE_ - -/* ========== Register definition for ADC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_ADC_CR (0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR (0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQR1 (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */ -#define REG_ADC_CHER (0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR (0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR (0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR (0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR (0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_LCTMR (0x40038034U) /**< \brief (ADC) Last Channel Trigger Mode Register */ -#define REG_ADC_LCCWR (0x40038038U) /**< \brief (ADC) Last Channel Compare Window Register */ -#define REG_ADC_OVER (0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR (0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR (0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_COR (0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR (0x40038050U) /**< \brief (ADC) Channel Data Register */ -#define REG_ADC_WPMR (0x400380E4U) /**< \brief (ADC) Write Protection Mode Register */ -#define REG_ADC_WPSR (0x400380E8U) /**< \brief (ADC) Write Protection Status Register */ -#define REG_ADC_RPR (0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR (0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_RNPR (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_PTCR (0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR (0x40038124U) /**< \brief (ADC) Transfer Status Register */ -#else -#define REG_ADC_CR (*(__O uint32_t*)0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR (*(__IO uint32_t*)0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQR1 (*(__IO uint32_t*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */ -#define REG_ADC_CHER (*(__O uint32_t*)0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR (*(__O uint32_t*)0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR (*(__I uint32_t*)0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR (*(__I uint32_t*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER (*(__O uint32_t*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR (*(__O uint32_t*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR (*(__I uint32_t*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR (*(__I uint32_t*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_LCTMR (*(__IO uint32_t*)0x40038034U) /**< \brief (ADC) Last Channel Trigger Mode Register */ -#define REG_ADC_LCCWR (*(__IO uint32_t*)0x40038038U) /**< \brief (ADC) Last Channel Compare Window Register */ -#define REG_ADC_OVER (*(__I uint32_t*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR (*(__IO uint32_t*)0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR (*(__IO uint32_t*)0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_COR (*(__IO uint32_t*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR (*(__I uint32_t*)0x40038050U) /**< \brief (ADC) Channel Data Register */ -#define REG_ADC_WPMR (*(__IO uint32_t*)0x400380E4U) /**< \brief (ADC) Write Protection Mode Register */ -#define REG_ADC_WPSR (*(__I uint32_t*)0x400380E8U) /**< \brief (ADC) Write Protection Status Register */ -#define REG_ADC_RPR (*(__IO uint32_t*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR (*(__IO uint32_t*)0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_RNPR (*(__IO uint32_t*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR (*(__IO uint32_t*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_PTCR (*(__O uint32_t*)0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR (*(__I uint32_t*)0x40038124U) /**< \brief (ADC) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_ADC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_chipid.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_chipid.h deleted file mode 100644 index 8e78ea9d9d1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_chipid.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_CHIPID_INSTANCE_ -#define _SAMG55_CHIPID_INSTANCE_ - -/* ========== Register definition for CHIPID peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -#else -#define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_CHIPID_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_cmcc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_cmcc.h deleted file mode 100644 index 158b7b2d080..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_cmcc.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_CMCC_INSTANCE_ -#define _SAMG55_CMCC_INSTANCE_ - -/* ========== Register definition for CMCC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CMCC_TYPE (0x4003C000U) /**< \brief (CMCC) Cache Controller Type Register */ -#define REG_CMCC_CFG (0x4003C004U) /**< \brief (CMCC) Cache Controller Configuration Register */ -#define REG_CMCC_CTRL (0x4003C008U) /**< \brief (CMCC) Cache Controller Control Register */ -#define REG_CMCC_SR (0x4003C00CU) /**< \brief (CMCC) Cache Controller Status Register */ -#define REG_CMCC_MAINT0 (0x4003C020U) /**< \brief (CMCC) Cache Controller Maintenance Register 0 */ -#define REG_CMCC_MAINT1 (0x4003C024U) /**< \brief (CMCC) Cache Controller Maintenance Register 1 */ -#define REG_CMCC_MCFG (0x4003C028U) /**< \brief (CMCC) Cache Controller Monitor Configuration Register */ -#define REG_CMCC_MEN (0x4003C02CU) /**< \brief (CMCC) Cache Controller Monitor Enable Register */ -#define REG_CMCC_MCTRL (0x4003C030U) /**< \brief (CMCC) Cache Controller Monitor Control Register */ -#define REG_CMCC_MSR (0x4003C034U) /**< \brief (CMCC) Cache Controller Monitor Status Register */ -#else -#define REG_CMCC_TYPE (*(__I uint32_t*)0x4003C000U) /**< \brief (CMCC) Cache Controller Type Register */ -#define REG_CMCC_CFG (*(__IO uint32_t*)0x4003C004U) /**< \brief (CMCC) Cache Controller Configuration Register */ -#define REG_CMCC_CTRL (*(__O uint32_t*)0x4003C008U) /**< \brief (CMCC) Cache Controller Control Register */ -#define REG_CMCC_SR (*(__I uint32_t*)0x4003C00CU) /**< \brief (CMCC) Cache Controller Status Register */ -#define REG_CMCC_MAINT0 (*(__O uint32_t*)0x4003C020U) /**< \brief (CMCC) Cache Controller Maintenance Register 0 */ -#define REG_CMCC_MAINT1 (*(__O uint32_t*)0x4003C024U) /**< \brief (CMCC) Cache Controller Maintenance Register 1 */ -#define REG_CMCC_MCFG (*(__IO uint32_t*)0x4003C028U) /**< \brief (CMCC) Cache Controller Monitor Configuration Register */ -#define REG_CMCC_MEN (*(__IO uint32_t*)0x4003C02CU) /**< \brief (CMCC) Cache Controller Monitor Enable Register */ -#define REG_CMCC_MCTRL (*(__O uint32_t*)0x4003C030U) /**< \brief (CMCC) Cache Controller Monitor Control Register */ -#define REG_CMCC_MSR (*(__I uint32_t*)0x4003C034U) /**< \brief (CMCC) Cache Controller Monitor Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_CMCC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_crccu.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_crccu.h deleted file mode 100644 index 30c8690bf43..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_crccu.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_CRCCU_INSTANCE_ -#define _SAMG55_CRCCU_INSTANCE_ - -/* ========== Register definition for CRCCU peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CRCCU_DSCR (0x40048000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN (0x40048008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS (0x4004800CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR (0x40048010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER (0x40048014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR (0x40048018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR (0x4004801CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR (0x40048020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR (0x40048034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR (0x40048038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR (0x4004803CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER (0x40048040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR (0x40048044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR (0x40048048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR (0x4004804CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -#else -#define REG_CRCCU_DSCR (*(__IO uint32_t*)0x40048000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN (*(__O uint32_t*)0x40048008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS (*(__O uint32_t*)0x4004800CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR (*(__I uint32_t*)0x40048010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER (*(__O uint32_t*)0x40048014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR (*(__O uint32_t*)0x40048018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR (*(__I uint32_t*)0x4004801CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR (*(__I uint32_t*)0x40048020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR (*(__O uint32_t*)0x40048034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR (*(__IO uint32_t*)0x40048038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR (*(__I uint32_t*)0x4004803CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER (*(__O uint32_t*)0x40048040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR (*(__O uint32_t*)0x40048044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR (*(__I uint32_t*)0x40048048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR (*(__I uint32_t*)0x4004804CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_CRCCU_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_efc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_efc.h deleted file mode 100644 index ca00f590ef7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_efc.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_EFC_INSTANCE_ -#define _SAMG55_EFC_INSTANCE_ - -/* ========== Register definition for EFC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -#define REG_EFC_WPMR (0x400E0AE4U) /**< \brief (EFC) Write Protection Mode Register */ -#else -#define REG_EFC_FMR (*(__IO uint32_t*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR (*(__O uint32_t*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR (*(__I uint32_t*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR (*(__I uint32_t*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -#define REG_EFC_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (EFC) Write Protection Mode Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_EFC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom0.h deleted file mode 100644 index d790b969eff..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom0.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM0_INSTANCE_ -#define _SAMG55_FLEXCOM0_INSTANCE_ - -/* ========== Register definition for FLEXCOM0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FLEXCOM0_MR (0x4000C000U) /**< \brief (FLEXCOM0) FLEXCOM Mode register */ -#define REG_FLEXCOM0_RHR (0x4000C010U) /**< \brief (FLEXCOM0) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM0_THR (0x4000C020U) /**< \brief (FLEXCOM0) FLEXCOM Transmit Holding Register */ -#else -#define REG_FLEXCOM0_MR (*(__IO uint32_t*)0x4000C000U) /**< \brief (FLEXCOM0) FLEXCOM Mode register */ -#define REG_FLEXCOM0_RHR (*(__I uint32_t*)0x4000C010U) /**< \brief (FLEXCOM0) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM0_THR (*(__IO uint32_t*)0x4000C020U) /**< \brief (FLEXCOM0) FLEXCOM Transmit Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_FLEXCOM0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom1.h deleted file mode 100644 index 76d53bb52c7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom1.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM1_INSTANCE_ -#define _SAMG55_FLEXCOM1_INSTANCE_ - -/* ========== Register definition for FLEXCOM1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FLEXCOM1_MR (0x40020000U) /**< \brief (FLEXCOM1) FLEXCOM Mode register */ -#define REG_FLEXCOM1_RHR (0x40020010U) /**< \brief (FLEXCOM1) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM1_THR (0x40020020U) /**< \brief (FLEXCOM1) FLEXCOM Transmit Holding Register */ -#else -#define REG_FLEXCOM1_MR (*(__IO uint32_t*)0x40020000U) /**< \brief (FLEXCOM1) FLEXCOM Mode register */ -#define REG_FLEXCOM1_RHR (*(__I uint32_t*)0x40020010U) /**< \brief (FLEXCOM1) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM1_THR (*(__IO uint32_t*)0x40020020U) /**< \brief (FLEXCOM1) FLEXCOM Transmit Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_FLEXCOM1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom2.h deleted file mode 100644 index 6078e4c82f6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom2.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM2_INSTANCE_ -#define _SAMG55_FLEXCOM2_INSTANCE_ - -/* ========== Register definition for FLEXCOM2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FLEXCOM2_MR (0x40024000U) /**< \brief (FLEXCOM2) FLEXCOM Mode register */ -#define REG_FLEXCOM2_RHR (0x40024010U) /**< \brief (FLEXCOM2) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM2_THR (0x40024020U) /**< \brief (FLEXCOM2) FLEXCOM Transmit Holding Register */ -#else -#define REG_FLEXCOM2_MR (*(__IO uint32_t*)0x40024000U) /**< \brief (FLEXCOM2) FLEXCOM Mode register */ -#define REG_FLEXCOM2_RHR (*(__I uint32_t*)0x40024010U) /**< \brief (FLEXCOM2) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM2_THR (*(__IO uint32_t*)0x40024020U) /**< \brief (FLEXCOM2) FLEXCOM Transmit Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_FLEXCOM2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom3.h deleted file mode 100644 index 5655f8437c7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom3.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM3_INSTANCE_ -#define _SAMG55_FLEXCOM3_INSTANCE_ - -/* ========== Register definition for FLEXCOM3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FLEXCOM3_MR (0x40018000U) /**< \brief (FLEXCOM3) FLEXCOM Mode register */ -#define REG_FLEXCOM3_RHR (0x40018010U) /**< \brief (FLEXCOM3) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM3_THR (0x40018020U) /**< \brief (FLEXCOM3) FLEXCOM Transmit Holding Register */ -#else -#define REG_FLEXCOM3_MR (*(__IO uint32_t*)0x40018000U) /**< \brief (FLEXCOM3) FLEXCOM Mode register */ -#define REG_FLEXCOM3_RHR (*(__I uint32_t*)0x40018010U) /**< \brief (FLEXCOM3) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM3_THR (*(__IO uint32_t*)0x40018020U) /**< \brief (FLEXCOM3) FLEXCOM Transmit Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_FLEXCOM3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom4.h deleted file mode 100644 index d7a70058636..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom4.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM4_INSTANCE_ -#define _SAMG55_FLEXCOM4_INSTANCE_ - -/* ========== Register definition for FLEXCOM4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FLEXCOM4_MR (0x4001C000U) /**< \brief (FLEXCOM4) FLEXCOM Mode register */ -#define REG_FLEXCOM4_RHR (0x4001C010U) /**< \brief (FLEXCOM4) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM4_THR (0x4001C020U) /**< \brief (FLEXCOM4) FLEXCOM Transmit Holding Register */ -#else -#define REG_FLEXCOM4_MR (*(__IO uint32_t*)0x4001C000U) /**< \brief (FLEXCOM4) FLEXCOM Mode register */ -#define REG_FLEXCOM4_RHR (*(__I uint32_t*)0x4001C010U) /**< \brief (FLEXCOM4) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM4_THR (*(__IO uint32_t*)0x4001C020U) /**< \brief (FLEXCOM4) FLEXCOM Transmit Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_FLEXCOM4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom5.h deleted file mode 100644 index 445af7cc426..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom5.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM5_INSTANCE_ -#define _SAMG55_FLEXCOM5_INSTANCE_ - -/* ========== Register definition for FLEXCOM5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FLEXCOM5_MR (0x40008000U) /**< \brief (FLEXCOM5) FLEXCOM Mode register */ -#define REG_FLEXCOM5_RHR (0x40008010U) /**< \brief (FLEXCOM5) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM5_THR (0x40008020U) /**< \brief (FLEXCOM5) FLEXCOM Transmit Holding Register */ -#else -#define REG_FLEXCOM5_MR (*(__IO uint32_t*)0x40008000U) /**< \brief (FLEXCOM5) FLEXCOM Mode register */ -#define REG_FLEXCOM5_RHR (*(__I uint32_t*)0x40008010U) /**< \brief (FLEXCOM5) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM5_THR (*(__IO uint32_t*)0x40008020U) /**< \brief (FLEXCOM5) FLEXCOM Transmit Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_FLEXCOM5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom6.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom6.h deleted file mode 100644 index 2aaf656fea7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom6.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM6_INSTANCE_ -#define _SAMG55_FLEXCOM6_INSTANCE_ - -/* ========== Register definition for FLEXCOM6 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FLEXCOM6_MR (0x40040000U) /**< \brief (FLEXCOM6) FLEXCOM Mode register */ -#define REG_FLEXCOM6_RHR (0x40040010U) /**< \brief (FLEXCOM6) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM6_THR (0x40040020U) /**< \brief (FLEXCOM6) FLEXCOM Transmit Holding Register */ -#else -#define REG_FLEXCOM6_MR (*(__IO uint32_t*)0x40040000U) /**< \brief (FLEXCOM6) FLEXCOM Mode register */ -#define REG_FLEXCOM6_RHR (*(__I uint32_t*)0x40040010U) /**< \brief (FLEXCOM6) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM6_THR (*(__IO uint32_t*)0x40040020U) /**< \brief (FLEXCOM6) FLEXCOM Transmit Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_FLEXCOM6_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom7.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom7.h deleted file mode 100644 index b597d52fb85..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom7.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_FLEXCOM7_INSTANCE_ -#define _SAMG55_FLEXCOM7_INSTANCE_ - -/* ========== Register definition for FLEXCOM7 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FLEXCOM7_MR (0x40034000U) /**< \brief (FLEXCOM7) FLEXCOM Mode register */ -#define REG_FLEXCOM7_RHR (0x40034010U) /**< \brief (FLEXCOM7) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM7_THR (0x40034020U) /**< \brief (FLEXCOM7) FLEXCOM Transmit Holding Register */ -#else -#define REG_FLEXCOM7_MR (*(__IO uint32_t*)0x40034000U) /**< \brief (FLEXCOM7) FLEXCOM Mode register */ -#define REG_FLEXCOM7_RHR (*(__I uint32_t*)0x40034010U) /**< \brief (FLEXCOM7) FLEXCOM Receive Holding Register */ -#define REG_FLEXCOM7_THR (*(__IO uint32_t*)0x40034020U) /**< \brief (FLEXCOM7) FLEXCOM Transmit Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_FLEXCOM7_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_gpbr.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_gpbr.h deleted file mode 100644 index 0bc5609e202..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_gpbr.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_GPBR_INSTANCE_ -#define _SAMG55_GPBR_INSTANCE_ - -/* ========== Register definition for GPBR peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_GPBR_GPBR (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */ -#else -#define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_GPBR_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_i2sc0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_i2sc0.h deleted file mode 100644 index 045a694332d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_i2sc0.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_I2SC0_INSTANCE_ -#define _SAMG55_I2SC0_INSTANCE_ - -/* ========== Register definition for I2SC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_I2SC0_CR (0x40000000U) /**< \brief (I2SC0) Control Register */ -#define REG_I2SC0_MR (0x40000004U) /**< \brief (I2SC0) Mode Register */ -#define REG_I2SC0_SR (0x40000008U) /**< \brief (I2SC0) Status Register */ -#define REG_I2SC0_SCR (0x4000000CU) /**< \brief (I2SC0) Status Clear Register */ -#define REG_I2SC0_SSR (0x40000010U) /**< \brief (I2SC0) Status Set Register */ -#define REG_I2SC0_IER (0x40000014U) /**< \brief (I2SC0) Interrupt Enable Register */ -#define REG_I2SC0_IDR (0x40000018U) /**< \brief (I2SC0) Interrupt Disable Register */ -#define REG_I2SC0_IMR (0x4000001CU) /**< \brief (I2SC0) Interrupt Mask Register */ -#define REG_I2SC0_RHR (0x40000020U) /**< \brief (I2SC0) Receiver Holding Register */ -#define REG_I2SC0_THR (0x40000024U) /**< \brief (I2SC0) Transmitter Holding Register */ -#define REG_I2SC0_RPR (0x40000100U) /**< \brief (I2SC0) Receive Pointer Register */ -#define REG_I2SC0_RCR (0x40000104U) /**< \brief (I2SC0) Receive Counter Register */ -#define REG_I2SC0_TPR (0x40000108U) /**< \brief (I2SC0) Transmit Pointer Register */ -#define REG_I2SC0_TCR (0x4000010CU) /**< \brief (I2SC0) Transmit Counter Register */ -#define REG_I2SC0_RNPR (0x40000110U) /**< \brief (I2SC0) Receive Next Pointer Register */ -#define REG_I2SC0_RNCR (0x40000114U) /**< \brief (I2SC0) Receive Next Counter Register */ -#define REG_I2SC0_TNPR (0x40000118U) /**< \brief (I2SC0) Transmit Next Pointer Register */ -#define REG_I2SC0_TNCR (0x4000011CU) /**< \brief (I2SC0) Transmit Next Counter Register */ -#define REG_I2SC0_PTCR (0x40000120U) /**< \brief (I2SC0) Transfer Control Register */ -#define REG_I2SC0_PTSR (0x40000124U) /**< \brief (I2SC0) Transfer Status Register */ -#else -#define REG_I2SC0_CR (*(__O uint32_t*)0x40000000U) /**< \brief (I2SC0) Control Register */ -#define REG_I2SC0_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (I2SC0) Mode Register */ -#define REG_I2SC0_SR (*(__I uint32_t*)0x40000008U) /**< \brief (I2SC0) Status Register */ -#define REG_I2SC0_SCR (*(__O uint32_t*)0x4000000CU) /**< \brief (I2SC0) Status Clear Register */ -#define REG_I2SC0_SSR (*(__O uint32_t*)0x40000010U) /**< \brief (I2SC0) Status Set Register */ -#define REG_I2SC0_IER (*(__O uint32_t*)0x40000014U) /**< \brief (I2SC0) Interrupt Enable Register */ -#define REG_I2SC0_IDR (*(__O uint32_t*)0x40000018U) /**< \brief (I2SC0) Interrupt Disable Register */ -#define REG_I2SC0_IMR (*(__I uint32_t*)0x4000001CU) /**< \brief (I2SC0) Interrupt Mask Register */ -#define REG_I2SC0_RHR (*(__I uint32_t*)0x40000020U) /**< \brief (I2SC0) Receiver Holding Register */ -#define REG_I2SC0_THR (*(__O uint32_t*)0x40000024U) /**< \brief (I2SC0) Transmitter Holding Register */ -#define REG_I2SC0_RPR (*(__IO uint32_t*)0x40000100U) /**< \brief (I2SC0) Receive Pointer Register */ -#define REG_I2SC0_RCR (*(__IO uint32_t*)0x40000104U) /**< \brief (I2SC0) Receive Counter Register */ -#define REG_I2SC0_TPR (*(__IO uint32_t*)0x40000108U) /**< \brief (I2SC0) Transmit Pointer Register */ -#define REG_I2SC0_TCR (*(__IO uint32_t*)0x4000010CU) /**< \brief (I2SC0) Transmit Counter Register */ -#define REG_I2SC0_RNPR (*(__IO uint32_t*)0x40000110U) /**< \brief (I2SC0) Receive Next Pointer Register */ -#define REG_I2SC0_RNCR (*(__IO uint32_t*)0x40000114U) /**< \brief (I2SC0) Receive Next Counter Register */ -#define REG_I2SC0_TNPR (*(__IO uint32_t*)0x40000118U) /**< \brief (I2SC0) Transmit Next Pointer Register */ -#define REG_I2SC0_TNCR (*(__IO uint32_t*)0x4000011CU) /**< \brief (I2SC0) Transmit Next Counter Register */ -#define REG_I2SC0_PTCR (*(__O uint32_t*)0x40000120U) /**< \brief (I2SC0) Transfer Control Register */ -#define REG_I2SC0_PTSR (*(__I uint32_t*)0x40000124U) /**< \brief (I2SC0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_I2SC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_i2sc1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_i2sc1.h deleted file mode 100644 index cad03a75dee..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_i2sc1.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_I2SC1_INSTANCE_ -#define _SAMG55_I2SC1_INSTANCE_ - -/* ========== Register definition for I2SC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_I2SC1_CR (0x40004000U) /**< \brief (I2SC1) Control Register */ -#define REG_I2SC1_MR (0x40004004U) /**< \brief (I2SC1) Mode Register */ -#define REG_I2SC1_SR (0x40004008U) /**< \brief (I2SC1) Status Register */ -#define REG_I2SC1_SCR (0x4000400CU) /**< \brief (I2SC1) Status Clear Register */ -#define REG_I2SC1_SSR (0x40004010U) /**< \brief (I2SC1) Status Set Register */ -#define REG_I2SC1_IER (0x40004014U) /**< \brief (I2SC1) Interrupt Enable Register */ -#define REG_I2SC1_IDR (0x40004018U) /**< \brief (I2SC1) Interrupt Disable Register */ -#define REG_I2SC1_IMR (0x4000401CU) /**< \brief (I2SC1) Interrupt Mask Register */ -#define REG_I2SC1_RHR (0x40004020U) /**< \brief (I2SC1) Receiver Holding Register */ -#define REG_I2SC1_THR (0x40004024U) /**< \brief (I2SC1) Transmitter Holding Register */ -#define REG_I2SC1_RPR (0x40004100U) /**< \brief (I2SC1) Receive Pointer Register */ -#define REG_I2SC1_RCR (0x40004104U) /**< \brief (I2SC1) Receive Counter Register */ -#define REG_I2SC1_TPR (0x40004108U) /**< \brief (I2SC1) Transmit Pointer Register */ -#define REG_I2SC1_TCR (0x4000410CU) /**< \brief (I2SC1) Transmit Counter Register */ -#define REG_I2SC1_RNPR (0x40004110U) /**< \brief (I2SC1) Receive Next Pointer Register */ -#define REG_I2SC1_RNCR (0x40004114U) /**< \brief (I2SC1) Receive Next Counter Register */ -#define REG_I2SC1_TNPR (0x40004118U) /**< \brief (I2SC1) Transmit Next Pointer Register */ -#define REG_I2SC1_TNCR (0x4000411CU) /**< \brief (I2SC1) Transmit Next Counter Register */ -#define REG_I2SC1_PTCR (0x40004120U) /**< \brief (I2SC1) Transfer Control Register */ -#define REG_I2SC1_PTSR (0x40004124U) /**< \brief (I2SC1) Transfer Status Register */ -#else -#define REG_I2SC1_CR (*(__O uint32_t*)0x40004000U) /**< \brief (I2SC1) Control Register */ -#define REG_I2SC1_MR (*(__IO uint32_t*)0x40004004U) /**< \brief (I2SC1) Mode Register */ -#define REG_I2SC1_SR (*(__I uint32_t*)0x40004008U) /**< \brief (I2SC1) Status Register */ -#define REG_I2SC1_SCR (*(__O uint32_t*)0x4000400CU) /**< \brief (I2SC1) Status Clear Register */ -#define REG_I2SC1_SSR (*(__O uint32_t*)0x40004010U) /**< \brief (I2SC1) Status Set Register */ -#define REG_I2SC1_IER (*(__O uint32_t*)0x40004014U) /**< \brief (I2SC1) Interrupt Enable Register */ -#define REG_I2SC1_IDR (*(__O uint32_t*)0x40004018U) /**< \brief (I2SC1) Interrupt Disable Register */ -#define REG_I2SC1_IMR (*(__I uint32_t*)0x4000401CU) /**< \brief (I2SC1) Interrupt Mask Register */ -#define REG_I2SC1_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (I2SC1) Receiver Holding Register */ -#define REG_I2SC1_THR (*(__O uint32_t*)0x40004024U) /**< \brief (I2SC1) Transmitter Holding Register */ -#define REG_I2SC1_RPR (*(__IO uint32_t*)0x40004100U) /**< \brief (I2SC1) Receive Pointer Register */ -#define REG_I2SC1_RCR (*(__IO uint32_t*)0x40004104U) /**< \brief (I2SC1) Receive Counter Register */ -#define REG_I2SC1_TPR (*(__IO uint32_t*)0x40004108U) /**< \brief (I2SC1) Transmit Pointer Register */ -#define REG_I2SC1_TCR (*(__IO uint32_t*)0x4000410CU) /**< \brief (I2SC1) Transmit Counter Register */ -#define REG_I2SC1_RNPR (*(__IO uint32_t*)0x40004110U) /**< \brief (I2SC1) Receive Next Pointer Register */ -#define REG_I2SC1_RNCR (*(__IO uint32_t*)0x40004114U) /**< \brief (I2SC1) Receive Next Counter Register */ -#define REG_I2SC1_TNPR (*(__IO uint32_t*)0x40004118U) /**< \brief (I2SC1) Transmit Next Pointer Register */ -#define REG_I2SC1_TNCR (*(__IO uint32_t*)0x4000411CU) /**< \brief (I2SC1) Transmit Next Counter Register */ -#define REG_I2SC1_PTCR (*(__O uint32_t*)0x40004120U) /**< \brief (I2SC1) Transfer Control Register */ -#define REG_I2SC1_PTSR (*(__I uint32_t*)0x40004124U) /**< \brief (I2SC1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_I2SC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_matrix.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_matrix.h deleted file mode 100644 index 169a65c5ab3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_matrix.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_MATRIX_INSTANCE_ -#define _SAMG55_MATRIX_INSTANCE_ - -/* ========== Register definition for MATRIX peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_CCFG_RDMMEM (0x400E0310U) /**< \brief (MATRIX) Embedded Memories Read Margin Values Register */ -#define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration Register */ -#define REG_CCFG_DYNCKG (0x400E0318U) /**< \brief (MATRIX) Dynamic Clock Gating Register */ -#define REG_CCFG_I2SCLKSEL (0x400E031CU) /**< \brief (MATRIX) I2S Clock Source Selection Register */ -#define REG_CCFG_USBMR (0x400E0320U) /**< \brief (MATRIX) USB Management Register */ -#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protection Mode Register */ -#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protection Status Register */ -#else -#define REG_MATRIX_MCFG (*(__IO uint32_t*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG (*(__IO uint32_t*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_CCFG_RDMMEM (*(__IO uint32_t*)0x400E0310U) /**< \brief (MATRIX) Embedded Memories Read Margin Values Register */ -#define REG_CCFG_SYSIO (*(__IO uint32_t*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration Register */ -#define REG_CCFG_DYNCKG (*(__IO uint32_t*)0x400E0318U) /**< \brief (MATRIX) Dynamic Clock Gating Register */ -#define REG_CCFG_I2SCLKSEL (*(__IO uint32_t*)0x400E031CU) /**< \brief (MATRIX) I2S Clock Source Selection Register */ -#define REG_CCFG_USBMR (*(__IO uint32_t*)0x400E0320U) /**< \brief (MATRIX) USB Management Register */ -#define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400E03E4U) /**< \brief (MATRIX) Write Protection Mode Register */ -#define REG_MATRIX_WPSR (*(__I uint32_t*)0x400E03E8U) /**< \brief (MATRIX) Write Protection Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_MATRIX_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_mem2mem.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_mem2mem.h deleted file mode 100644 index 25d193e0ec5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_mem2mem.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_MEM2MEM_INSTANCE_ -#define _SAMG55_MEM2MEM_INSTANCE_ - -/* ========== Register definition for MEM2MEM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MEM2MEM_THR (0x40028000U) /**< \brief (MEM2MEM) Memory to Memory Transfer Holding Register */ -#define REG_MEM2MEM_MR (0x40028004U) /**< \brief (MEM2MEM) Memory to Memory Mode Register */ -#define REG_MEM2MEM_IER (0x40028008U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Enable Register */ -#define REG_MEM2MEM_IDR (0x4002800CU) /**< \brief (MEM2MEM) Memory to Memory Interrupt Disable Register */ -#define REG_MEM2MEM_IMR (0x40028010U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Mask Register */ -#define REG_MEM2MEM_ISR (0x40028014U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Status Register */ -#define REG_MEM2MEM_RPR (0x40028100U) /**< \brief (MEM2MEM) Receive Pointer Register */ -#define REG_MEM2MEM_RCR (0x40028104U) /**< \brief (MEM2MEM) Receive Counter Register */ -#define REG_MEM2MEM_TPR (0x40028108U) /**< \brief (MEM2MEM) Transmit Pointer Register */ -#define REG_MEM2MEM_TCR (0x4002810CU) /**< \brief (MEM2MEM) Transmit Counter Register */ -#define REG_MEM2MEM_RNPR (0x40028110U) /**< \brief (MEM2MEM) Receive Next Pointer Register */ -#define REG_MEM2MEM_RNCR (0x40028114U) /**< \brief (MEM2MEM) Receive Next Counter Register */ -#define REG_MEM2MEM_TNPR (0x40028118U) /**< \brief (MEM2MEM) Transmit Next Pointer Register */ -#define REG_MEM2MEM_TNCR (0x4002811CU) /**< \brief (MEM2MEM) Transmit Next Counter Register */ -#define REG_MEM2MEM_PTCR (0x40028120U) /**< \brief (MEM2MEM) Transfer Control Register */ -#define REG_MEM2MEM_PTSR (0x40028124U) /**< \brief (MEM2MEM) Transfer Status Register */ -#else -#define REG_MEM2MEM_THR (*(__IO uint32_t*)0x40028000U) /**< \brief (MEM2MEM) Memory to Memory Transfer Holding Register */ -#define REG_MEM2MEM_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (MEM2MEM) Memory to Memory Mode Register */ -#define REG_MEM2MEM_IER (*(__O uint32_t*)0x40028008U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Enable Register */ -#define REG_MEM2MEM_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (MEM2MEM) Memory to Memory Interrupt Disable Register */ -#define REG_MEM2MEM_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Mask Register */ -#define REG_MEM2MEM_ISR (*(__I uint32_t*)0x40028014U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Status Register */ -#define REG_MEM2MEM_RPR (*(__IO uint32_t*)0x40028100U) /**< \brief (MEM2MEM) Receive Pointer Register */ -#define REG_MEM2MEM_RCR (*(__IO uint32_t*)0x40028104U) /**< \brief (MEM2MEM) Receive Counter Register */ -#define REG_MEM2MEM_TPR (*(__IO uint32_t*)0x40028108U) /**< \brief (MEM2MEM) Transmit Pointer Register */ -#define REG_MEM2MEM_TCR (*(__IO uint32_t*)0x4002810CU) /**< \brief (MEM2MEM) Transmit Counter Register */ -#define REG_MEM2MEM_RNPR (*(__IO uint32_t*)0x40028110U) /**< \brief (MEM2MEM) Receive Next Pointer Register */ -#define REG_MEM2MEM_RNCR (*(__IO uint32_t*)0x40028114U) /**< \brief (MEM2MEM) Receive Next Counter Register */ -#define REG_MEM2MEM_TNPR (*(__IO uint32_t*)0x40028118U) /**< \brief (MEM2MEM) Transmit Next Pointer Register */ -#define REG_MEM2MEM_TNCR (*(__IO uint32_t*)0x4002811CU) /**< \brief (MEM2MEM) Transmit Next Counter Register */ -#define REG_MEM2MEM_PTCR (*(__O uint32_t*)0x40028120U) /**< \brief (MEM2MEM) Transfer Control Register */ -#define REG_MEM2MEM_PTSR (*(__I uint32_t*)0x40028124U) /**< \brief (MEM2MEM) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_MEM2MEM_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pdmic0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pdmic0.h deleted file mode 100644 index dde450425bd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pdmic0.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PDMIC0_INSTANCE_ -#define _SAMG55_PDMIC0_INSTANCE_ - -/* ========== Register definition for PDMIC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PDMIC0_CR (0x4002C000U) /**< \brief (PDMIC0) Control Register */ -#define REG_PDMIC0_MR (0x4002C004U) /**< \brief (PDMIC0) Mode Register */ -#define REG_PDMIC0_CDR (0x4002C014U) /**< \brief (PDMIC0) Converted Data Register */ -#define REG_PDMIC0_IER (0x4002C018U) /**< \brief (PDMIC0) Interrupt Enable Register */ -#define REG_PDMIC0_IDR (0x4002C01CU) /**< \brief (PDMIC0) Interrupt Disable Register */ -#define REG_PDMIC0_IMR (0x4002C020U) /**< \brief (PDMIC0) Interrupt Mask Register */ -#define REG_PDMIC0_ISR (0x4002C024U) /**< \brief (PDMIC0) Interrupt Status Register */ -#define REG_PDMIC0_DSPR0 (0x4002C058U) /**< \brief (PDMIC0) DSP Configuration Register 0 */ -#define REG_PDMIC0_DSPR1 (0x4002C05CU) /**< \brief (PDMIC0) DSP Configuration Register 1 */ -#define REG_PDMIC0_WPMR (0x4002C0E4U) /**< \brief (PDMIC0) Write Protection Mode Register */ -#define REG_PDMIC0_WPSR (0x4002C0E8U) /**< \brief (PDMIC0) Write Protection Status Register */ -#define REG_PDMIC0_RPR (0x4002C100U) /**< \brief (PDMIC0) Receive Pointer Register */ -#define REG_PDMIC0_RCR (0x4002C104U) /**< \brief (PDMIC0) Receive Counter Register */ -#define REG_PDMIC0_RNPR (0x4002C110U) /**< \brief (PDMIC0) Receive Next Pointer Register */ -#define REG_PDMIC0_RNCR (0x4002C114U) /**< \brief (PDMIC0) Receive Next Counter Register */ -#define REG_PDMIC0_PTCR (0x4002C120U) /**< \brief (PDMIC0) Transfer Control Register */ -#define REG_PDMIC0_PTSR (0x4002C124U) /**< \brief (PDMIC0) Transfer Status Register */ -#else -#define REG_PDMIC0_CR (*(__IO uint32_t*)0x4002C000U) /**< \brief (PDMIC0) Control Register */ -#define REG_PDMIC0_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (PDMIC0) Mode Register */ -#define REG_PDMIC0_CDR (*(__I uint32_t*)0x4002C014U) /**< \brief (PDMIC0) Converted Data Register */ -#define REG_PDMIC0_IER (*(__O uint32_t*)0x4002C018U) /**< \brief (PDMIC0) Interrupt Enable Register */ -#define REG_PDMIC0_IDR (*(__O uint32_t*)0x4002C01CU) /**< \brief (PDMIC0) Interrupt Disable Register */ -#define REG_PDMIC0_IMR (*(__I uint32_t*)0x4002C020U) /**< \brief (PDMIC0) Interrupt Mask Register */ -#define REG_PDMIC0_ISR (*(__I uint32_t*)0x4002C024U) /**< \brief (PDMIC0) Interrupt Status Register */ -#define REG_PDMIC0_DSPR0 (*(__IO uint32_t*)0x4002C058U) /**< \brief (PDMIC0) DSP Configuration Register 0 */ -#define REG_PDMIC0_DSPR1 (*(__IO uint32_t*)0x4002C05CU) /**< \brief (PDMIC0) DSP Configuration Register 1 */ -#define REG_PDMIC0_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (PDMIC0) Write Protection Mode Register */ -#define REG_PDMIC0_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (PDMIC0) Write Protection Status Register */ -#define REG_PDMIC0_RPR (*(__IO uint32_t*)0x4002C100U) /**< \brief (PDMIC0) Receive Pointer Register */ -#define REG_PDMIC0_RCR (*(__IO uint32_t*)0x4002C104U) /**< \brief (PDMIC0) Receive Counter Register */ -#define REG_PDMIC0_RNPR (*(__IO uint32_t*)0x4002C110U) /**< \brief (PDMIC0) Receive Next Pointer Register */ -#define REG_PDMIC0_RNCR (*(__IO uint32_t*)0x4002C114U) /**< \brief (PDMIC0) Receive Next Counter Register */ -#define REG_PDMIC0_PTCR (*(__O uint32_t*)0x4002C120U) /**< \brief (PDMIC0) Transfer Control Register */ -#define REG_PDMIC0_PTSR (*(__I uint32_t*)0x4002C124U) /**< \brief (PDMIC0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_PDMIC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pdmic1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pdmic1.h deleted file mode 100644 index 2abcfa0f20a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pdmic1.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PDMIC1_INSTANCE_ -#define _SAMG55_PDMIC1_INSTANCE_ - -/* ========== Register definition for PDMIC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PDMIC1_CR (0x40030000U) /**< \brief (PDMIC1) Control Register */ -#define REG_PDMIC1_MR (0x40030004U) /**< \brief (PDMIC1) Mode Register */ -#define REG_PDMIC1_CDR (0x40030014U) /**< \brief (PDMIC1) Converted Data Register */ -#define REG_PDMIC1_IER (0x40030018U) /**< \brief (PDMIC1) Interrupt Enable Register */ -#define REG_PDMIC1_IDR (0x4003001CU) /**< \brief (PDMIC1) Interrupt Disable Register */ -#define REG_PDMIC1_IMR (0x40030020U) /**< \brief (PDMIC1) Interrupt Mask Register */ -#define REG_PDMIC1_ISR (0x40030024U) /**< \brief (PDMIC1) Interrupt Status Register */ -#define REG_PDMIC1_DSPR0 (0x40030058U) /**< \brief (PDMIC1) DSP Configuration Register 0 */ -#define REG_PDMIC1_DSPR1 (0x4003005CU) /**< \brief (PDMIC1) DSP Configuration Register 1 */ -#define REG_PDMIC1_WPMR (0x400300E4U) /**< \brief (PDMIC1) Write Protection Mode Register */ -#define REG_PDMIC1_WPSR (0x400300E8U) /**< \brief (PDMIC1) Write Protection Status Register */ -#define REG_PDMIC1_RPR (0x40030100U) /**< \brief (PDMIC1) Receive Pointer Register */ -#define REG_PDMIC1_RCR (0x40030104U) /**< \brief (PDMIC1) Receive Counter Register */ -#define REG_PDMIC1_RNPR (0x40030110U) /**< \brief (PDMIC1) Receive Next Pointer Register */ -#define REG_PDMIC1_RNCR (0x40030114U) /**< \brief (PDMIC1) Receive Next Counter Register */ -#define REG_PDMIC1_PTCR (0x40030120U) /**< \brief (PDMIC1) Transfer Control Register */ -#define REG_PDMIC1_PTSR (0x40030124U) /**< \brief (PDMIC1) Transfer Status Register */ -#else -#define REG_PDMIC1_CR (*(__IO uint32_t*)0x40030000U) /**< \brief (PDMIC1) Control Register */ -#define REG_PDMIC1_MR (*(__IO uint32_t*)0x40030004U) /**< \brief (PDMIC1) Mode Register */ -#define REG_PDMIC1_CDR (*(__I uint32_t*)0x40030014U) /**< \brief (PDMIC1) Converted Data Register */ -#define REG_PDMIC1_IER (*(__O uint32_t*)0x40030018U) /**< \brief (PDMIC1) Interrupt Enable Register */ -#define REG_PDMIC1_IDR (*(__O uint32_t*)0x4003001CU) /**< \brief (PDMIC1) Interrupt Disable Register */ -#define REG_PDMIC1_IMR (*(__I uint32_t*)0x40030020U) /**< \brief (PDMIC1) Interrupt Mask Register */ -#define REG_PDMIC1_ISR (*(__I uint32_t*)0x40030024U) /**< \brief (PDMIC1) Interrupt Status Register */ -#define REG_PDMIC1_DSPR0 (*(__IO uint32_t*)0x40030058U) /**< \brief (PDMIC1) DSP Configuration Register 0 */ -#define REG_PDMIC1_DSPR1 (*(__IO uint32_t*)0x4003005CU) /**< \brief (PDMIC1) DSP Configuration Register 1 */ -#define REG_PDMIC1_WPMR (*(__IO uint32_t*)0x400300E4U) /**< \brief (PDMIC1) Write Protection Mode Register */ -#define REG_PDMIC1_WPSR (*(__I uint32_t*)0x400300E8U) /**< \brief (PDMIC1) Write Protection Status Register */ -#define REG_PDMIC1_RPR (*(__IO uint32_t*)0x40030100U) /**< \brief (PDMIC1) Receive Pointer Register */ -#define REG_PDMIC1_RCR (*(__IO uint32_t*)0x40030104U) /**< \brief (PDMIC1) Receive Counter Register */ -#define REG_PDMIC1_RNPR (*(__IO uint32_t*)0x40030110U) /**< \brief (PDMIC1) Receive Next Pointer Register */ -#define REG_PDMIC1_RNCR (*(__IO uint32_t*)0x40030114U) /**< \brief (PDMIC1) Receive Next Counter Register */ -#define REG_PDMIC1_PTCR (*(__O uint32_t*)0x40030120U) /**< \brief (PDMIC1) Transfer Control Register */ -#define REG_PDMIC1_PTSR (*(__I uint32_t*)0x40030124U) /**< \brief (PDMIC1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_PDMIC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pioa.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pioa.h deleted file mode 100644 index 27178539d61..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pioa.h +++ /dev/null @@ -1,145 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PIOA_INSTANCE_ -#define _SAMG55_PIOA_INSTANCE_ - -/* ========== Register definition for PIOA peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ -#define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ -#define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ -#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ -#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ -#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ -#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ -#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ -#define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#else -#define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ -#define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ -#define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ -#define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ -#define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ -#define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ -#define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ -#define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ -#define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_PIOA_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_piob.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_piob.h deleted file mode 100644 index f030e165afa..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_piob.h +++ /dev/null @@ -1,145 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PIOB_INSTANCE_ -#define _SAMG55_PIOB_INSTANCE_ - -/* ========== Register definition for PIOB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ -#define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ -#define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ -#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ -#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ -#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ -#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ -#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ -#define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#else -#define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ -#define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ -#define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ -#define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ -#define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ -#define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ -#define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ -#define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ -#define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_PIOB_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pmc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pmc.h deleted file mode 100644 index c5e0984c9ae..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pmc.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_PMC_INSTANCE_ -#define _SAMG55_PMC_INSTANCE_ - -/* ========== Register definition for PMC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_CKGR_PLLBR (0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protection Mode Register */ -#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protection Status Register */ -#define REG_PMC_PCR (0x400E050CU) /**< \brief (PMC) Peripheral Control Register */ -#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -#define REG_PMC_SLPWK_ER0 (0x400E0514U) /**< \brief (PMC) SleepWalking Enable Register 0 */ -#define REG_PMC_SLPWK_DR0 (0x400E0518U) /**< \brief (PMC) SleepWalking Disable Register 0 */ -#define REG_PMC_SLPWK_SR0 (0x400E051CU) /**< \brief (PMC) SleepWalking Status Register 0 */ -#define REG_PMC_SLPWK_ASR0 (0x400E0520U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ -#define REG_PMC_PMMR (0x400E0530U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */ -#else -#define REG_PMC_SCER (*(__O uint32_t*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR (*(__O uint32_t*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR (*(__I uint32_t*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_CKGR_PLLBR (*(__IO uint32_t*)0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB (*(__IO uint32_t*)0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK (*(__IO uint32_t*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER (*(__O uint32_t*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR (*(__O uint32_t*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR (*(__I uint32_t*)0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR (*(__I uint32_t*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR (*(__O uint32_t*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR (*(__IO uint32_t*)0x400E04E4U) /**< \brief (PMC) Write Protection Mode Register */ -#define REG_PMC_WPSR (*(__I uint32_t*)0x400E04E8U) /**< \brief (PMC) Write Protection Status Register */ -#define REG_PMC_PCR (*(__IO uint32_t*)0x400E050CU) /**< \brief (PMC) Peripheral Control Register */ -#define REG_PMC_OCR (*(__IO uint32_t*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -#define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0514U) /**< \brief (PMC) SleepWalking Enable Register 0 */ -#define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0518U) /**< \brief (PMC) SleepWalking Disable Register 0 */ -#define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E051CU) /**< \brief (PMC) SleepWalking Status Register 0 */ -#define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0520U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ -#define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0530U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_PMC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rstc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rstc.h deleted file mode 100644 index 1bb33dd611a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rstc.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_RSTC_INSTANCE_ -#define _SAMG55_RSTC_INSTANCE_ - -/* ========== Register definition for RSTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RSTC_CR (0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR (0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR (0x400E1408U) /**< \brief (RSTC) Mode Register */ -#else -#define REG_RSTC_CR (*(__O uint32_t*)0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR (*(__I uint32_t*)0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR (*(__IO uint32_t*)0x400E1408U) /**< \brief (RSTC) Mode Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_RSTC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rtc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rtc.h deleted file mode 100644 index c146ebc9431..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rtc.h +++ /dev/null @@ -1,81 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_RTC_INSTANCE_ -#define _SAMG55_RTC_INSTANCE_ - -/* ========== Register definition for RTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTC_CR (0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR (0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR (0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR (0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR (0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR (0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER (0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -#define REG_RTC_MSR (0x400E1530U) /**< \brief (RTC) Milliseconds Register */ -#define REG_RTC_WPMR (0x400E1544U) /**< \brief (RTC) Write Protection Mode Register */ -#else -#define REG_RTC_CR (*(__IO uint32_t*)0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR (*(__IO uint32_t*)0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR (*(__IO uint32_t*)0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR (*(__I uint32_t*)0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR (*(__O uint32_t*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER (*(__O uint32_t*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR (*(__O uint32_t*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR (*(__I uint32_t*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER (*(__I uint32_t*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -#define REG_RTC_MSR (*(__I uint32_t*)0x400E1530U) /**< \brief (RTC) Milliseconds Register */ -#define REG_RTC_WPMR (*(__IO uint32_t*)0x400E1544U) /**< \brief (RTC) Write Protection Mode Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_RTC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rtt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rtt.h deleted file mode 100644 index d74795be77f..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rtt.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_RTT_INSTANCE_ -#define _SAMG55_RTT_INSTANCE_ - -/* ========== Register definition for RTT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTT_MR (0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR (0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR (0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR (0x400E143CU) /**< \brief (RTT) Status Register */ -#define REG_RTT_MODR (0x400E1440U) /**< \brief (RTT) Modulo Selection Register */ -#else -#define REG_RTT_MR (*(__IO uint32_t*)0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR (*(__IO uint32_t*)0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR (*(__I uint32_t*)0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR (*(__I uint32_t*)0x400E143CU) /**< \brief (RTT) Status Register */ -#define REG_RTT_MODR (*(__IO uint32_t*)0x400E1440U) /**< \brief (RTT) Modulo Selection Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_RTT_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi0.h deleted file mode 100644 index c993e55db95..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi0.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI0_INSTANCE_ -#define _SAMG55_SPI0_INSTANCE_ - -/* ========== Register definition for SPI0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI0_CR (0x4000C400U) /**< \brief (SPI0) SPI Control Register */ -#define REG_SPI0_MR (0x4000C404U) /**< \brief (SPI0) SPI Mode Register */ -#define REG_SPI0_RDR (0x4000C408U) /**< \brief (SPI0) SPI Receive Data Register */ -#define REG_SPI0_TDR (0x4000C40CU) /**< \brief (SPI0) SPI Transmit Data Register */ -#define REG_SPI0_SR (0x4000C410U) /**< \brief (SPI0) SPI Status Register */ -#define REG_SPI0_IER (0x4000C414U) /**< \brief (SPI0) SPI Interrupt Enable Register */ -#define REG_SPI0_IDR (0x4000C418U) /**< \brief (SPI0) SPI Interrupt Disable Register */ -#define REG_SPI0_IMR (0x4000C41CU) /**< \brief (SPI0) SPI Interrupt Mask Register */ -#define REG_SPI0_CSR (0x4000C430U) /**< \brief (SPI0) SPI Chip Select Register */ -#define REG_SPI0_CMPR (0x4000C448U) /**< \brief (SPI0) SPI Comparison Register */ -#define REG_SPI0_WPMR (0x4000C4E4U) /**< \brief (SPI0) SPI Write Protection Mode Register */ -#define REG_SPI0_WPSR (0x4000C4E8U) /**< \brief (SPI0) SPI Write Protection Status Register */ -#define REG_SPI0_RPR (0x4000C500U) /**< \brief (SPI0) Receive Pointer Register */ -#define REG_SPI0_RCR (0x4000C504U) /**< \brief (SPI0) Receive Counter Register */ -#define REG_SPI0_TPR (0x4000C508U) /**< \brief (SPI0) Transmit Pointer Register */ -#define REG_SPI0_TCR (0x4000C50CU) /**< \brief (SPI0) Transmit Counter Register */ -#define REG_SPI0_RNPR (0x4000C510U) /**< \brief (SPI0) Receive Next Pointer Register */ -#define REG_SPI0_RNCR (0x4000C514U) /**< \brief (SPI0) Receive Next Counter Register */ -#define REG_SPI0_TNPR (0x4000C518U) /**< \brief (SPI0) Transmit Next Pointer Register */ -#define REG_SPI0_TNCR (0x4000C51CU) /**< \brief (SPI0) Transmit Next Counter Register */ -#define REG_SPI0_PTCR (0x4000C520U) /**< \brief (SPI0) Transfer Control Register */ -#define REG_SPI0_PTSR (0x4000C524U) /**< \brief (SPI0) Transfer Status Register */ -#else -#define REG_SPI0_CR (*(__O uint32_t*)0x4000C400U) /**< \brief (SPI0) SPI Control Register */ -#define REG_SPI0_MR (*(__IO uint32_t*)0x4000C404U) /**< \brief (SPI0) SPI Mode Register */ -#define REG_SPI0_RDR (*(__I uint32_t*)0x4000C408U) /**< \brief (SPI0) SPI Receive Data Register */ -#define REG_SPI0_TDR (*(__O uint32_t*)0x4000C40CU) /**< \brief (SPI0) SPI Transmit Data Register */ -#define REG_SPI0_SR (*(__I uint32_t*)0x4000C410U) /**< \brief (SPI0) SPI Status Register */ -#define REG_SPI0_IER (*(__O uint32_t*)0x4000C414U) /**< \brief (SPI0) SPI Interrupt Enable Register */ -#define REG_SPI0_IDR (*(__O uint32_t*)0x4000C418U) /**< \brief (SPI0) SPI Interrupt Disable Register */ -#define REG_SPI0_IMR (*(__I uint32_t*)0x4000C41CU) /**< \brief (SPI0) SPI Interrupt Mask Register */ -#define REG_SPI0_CSR (*(__IO uint32_t*)0x4000C430U) /**< \brief (SPI0) SPI Chip Select Register */ -#define REG_SPI0_CMPR (*(__IO uint32_t*)0x4000C448U) /**< \brief (SPI0) SPI Comparison Register */ -#define REG_SPI0_WPMR (*(__IO uint32_t*)0x4000C4E4U) /**< \brief (SPI0) SPI Write Protection Mode Register */ -#define REG_SPI0_WPSR (*(__I uint32_t*)0x4000C4E8U) /**< \brief (SPI0) SPI Write Protection Status Register */ -#define REG_SPI0_RPR (*(__IO uint32_t*)0x4000C500U) /**< \brief (SPI0) Receive Pointer Register */ -#define REG_SPI0_RCR (*(__IO uint32_t*)0x4000C504U) /**< \brief (SPI0) Receive Counter Register */ -#define REG_SPI0_TPR (*(__IO uint32_t*)0x4000C508U) /**< \brief (SPI0) Transmit Pointer Register */ -#define REG_SPI0_TCR (*(__IO uint32_t*)0x4000C50CU) /**< \brief (SPI0) Transmit Counter Register */ -#define REG_SPI0_RNPR (*(__IO uint32_t*)0x4000C510U) /**< \brief (SPI0) Receive Next Pointer Register */ -#define REG_SPI0_RNCR (*(__IO uint32_t*)0x4000C514U) /**< \brief (SPI0) Receive Next Counter Register */ -#define REG_SPI0_TNPR (*(__IO uint32_t*)0x4000C518U) /**< \brief (SPI0) Transmit Next Pointer Register */ -#define REG_SPI0_TNCR (*(__IO uint32_t*)0x4000C51CU) /**< \brief (SPI0) Transmit Next Counter Register */ -#define REG_SPI0_PTCR (*(__O uint32_t*)0x4000C520U) /**< \brief (SPI0) Transfer Control Register */ -#define REG_SPI0_PTSR (*(__I uint32_t*)0x4000C524U) /**< \brief (SPI0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SPI0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi1.h deleted file mode 100644 index caecbf2d90c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi1.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI1_INSTANCE_ -#define _SAMG55_SPI1_INSTANCE_ - -/* ========== Register definition for SPI1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI1_CR (0x40020400U) /**< \brief (SPI1) SPI Control Register */ -#define REG_SPI1_MR (0x40020404U) /**< \brief (SPI1) SPI Mode Register */ -#define REG_SPI1_RDR (0x40020408U) /**< \brief (SPI1) SPI Receive Data Register */ -#define REG_SPI1_TDR (0x4002040CU) /**< \brief (SPI1) SPI Transmit Data Register */ -#define REG_SPI1_SR (0x40020410U) /**< \brief (SPI1) SPI Status Register */ -#define REG_SPI1_IER (0x40020414U) /**< \brief (SPI1) SPI Interrupt Enable Register */ -#define REG_SPI1_IDR (0x40020418U) /**< \brief (SPI1) SPI Interrupt Disable Register */ -#define REG_SPI1_IMR (0x4002041CU) /**< \brief (SPI1) SPI Interrupt Mask Register */ -#define REG_SPI1_CSR (0x40020430U) /**< \brief (SPI1) SPI Chip Select Register */ -#define REG_SPI1_CMPR (0x40020448U) /**< \brief (SPI1) SPI Comparison Register */ -#define REG_SPI1_WPMR (0x400204E4U) /**< \brief (SPI1) SPI Write Protection Mode Register */ -#define REG_SPI1_WPSR (0x400204E8U) /**< \brief (SPI1) SPI Write Protection Status Register */ -#define REG_SPI1_RPR (0x40020500U) /**< \brief (SPI1) Receive Pointer Register */ -#define REG_SPI1_RCR (0x40020504U) /**< \brief (SPI1) Receive Counter Register */ -#define REG_SPI1_TPR (0x40020508U) /**< \brief (SPI1) Transmit Pointer Register */ -#define REG_SPI1_TCR (0x4002050CU) /**< \brief (SPI1) Transmit Counter Register */ -#define REG_SPI1_RNPR (0x40020510U) /**< \brief (SPI1) Receive Next Pointer Register */ -#define REG_SPI1_RNCR (0x40020514U) /**< \brief (SPI1) Receive Next Counter Register */ -#define REG_SPI1_TNPR (0x40020518U) /**< \brief (SPI1) Transmit Next Pointer Register */ -#define REG_SPI1_TNCR (0x4002051CU) /**< \brief (SPI1) Transmit Next Counter Register */ -#define REG_SPI1_PTCR (0x40020520U) /**< \brief (SPI1) Transfer Control Register */ -#define REG_SPI1_PTSR (0x40020524U) /**< \brief (SPI1) Transfer Status Register */ -#else -#define REG_SPI1_CR (*(__O uint32_t*)0x40020400U) /**< \brief (SPI1) SPI Control Register */ -#define REG_SPI1_MR (*(__IO uint32_t*)0x40020404U) /**< \brief (SPI1) SPI Mode Register */ -#define REG_SPI1_RDR (*(__I uint32_t*)0x40020408U) /**< \brief (SPI1) SPI Receive Data Register */ -#define REG_SPI1_TDR (*(__O uint32_t*)0x4002040CU) /**< \brief (SPI1) SPI Transmit Data Register */ -#define REG_SPI1_SR (*(__I uint32_t*)0x40020410U) /**< \brief (SPI1) SPI Status Register */ -#define REG_SPI1_IER (*(__O uint32_t*)0x40020414U) /**< \brief (SPI1) SPI Interrupt Enable Register */ -#define REG_SPI1_IDR (*(__O uint32_t*)0x40020418U) /**< \brief (SPI1) SPI Interrupt Disable Register */ -#define REG_SPI1_IMR (*(__I uint32_t*)0x4002041CU) /**< \brief (SPI1) SPI Interrupt Mask Register */ -#define REG_SPI1_CSR (*(__IO uint32_t*)0x40020430U) /**< \brief (SPI1) SPI Chip Select Register */ -#define REG_SPI1_CMPR (*(__IO uint32_t*)0x40020448U) /**< \brief (SPI1) SPI Comparison Register */ -#define REG_SPI1_WPMR (*(__IO uint32_t*)0x400204E4U) /**< \brief (SPI1) SPI Write Protection Mode Register */ -#define REG_SPI1_WPSR (*(__I uint32_t*)0x400204E8U) /**< \brief (SPI1) SPI Write Protection Status Register */ -#define REG_SPI1_RPR (*(__IO uint32_t*)0x40020500U) /**< \brief (SPI1) Receive Pointer Register */ -#define REG_SPI1_RCR (*(__IO uint32_t*)0x40020504U) /**< \brief (SPI1) Receive Counter Register */ -#define REG_SPI1_TPR (*(__IO uint32_t*)0x40020508U) /**< \brief (SPI1) Transmit Pointer Register */ -#define REG_SPI1_TCR (*(__IO uint32_t*)0x4002050CU) /**< \brief (SPI1) Transmit Counter Register */ -#define REG_SPI1_RNPR (*(__IO uint32_t*)0x40020510U) /**< \brief (SPI1) Receive Next Pointer Register */ -#define REG_SPI1_RNCR (*(__IO uint32_t*)0x40020514U) /**< \brief (SPI1) Receive Next Counter Register */ -#define REG_SPI1_TNPR (*(__IO uint32_t*)0x40020518U) /**< \brief (SPI1) Transmit Next Pointer Register */ -#define REG_SPI1_TNCR (*(__IO uint32_t*)0x4002051CU) /**< \brief (SPI1) Transmit Next Counter Register */ -#define REG_SPI1_PTCR (*(__O uint32_t*)0x40020520U) /**< \brief (SPI1) Transfer Control Register */ -#define REG_SPI1_PTSR (*(__I uint32_t*)0x40020524U) /**< \brief (SPI1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SPI1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi2.h deleted file mode 100644 index 6e74ea22af1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi2.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI2_INSTANCE_ -#define _SAMG55_SPI2_INSTANCE_ - -/* ========== Register definition for SPI2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI2_CR (0x40024400U) /**< \brief (SPI2) SPI Control Register */ -#define REG_SPI2_MR (0x40024404U) /**< \brief (SPI2) SPI Mode Register */ -#define REG_SPI2_RDR (0x40024408U) /**< \brief (SPI2) SPI Receive Data Register */ -#define REG_SPI2_TDR (0x4002440CU) /**< \brief (SPI2) SPI Transmit Data Register */ -#define REG_SPI2_SR (0x40024410U) /**< \brief (SPI2) SPI Status Register */ -#define REG_SPI2_IER (0x40024414U) /**< \brief (SPI2) SPI Interrupt Enable Register */ -#define REG_SPI2_IDR (0x40024418U) /**< \brief (SPI2) SPI Interrupt Disable Register */ -#define REG_SPI2_IMR (0x4002441CU) /**< \brief (SPI2) SPI Interrupt Mask Register */ -#define REG_SPI2_CSR (0x40024430U) /**< \brief (SPI2) SPI Chip Select Register */ -#define REG_SPI2_CMPR (0x40024448U) /**< \brief (SPI2) SPI Comparison Register */ -#define REG_SPI2_WPMR (0x400244E4U) /**< \brief (SPI2) SPI Write Protection Mode Register */ -#define REG_SPI2_WPSR (0x400244E8U) /**< \brief (SPI2) SPI Write Protection Status Register */ -#define REG_SPI2_RPR (0x40024500U) /**< \brief (SPI2) Receive Pointer Register */ -#define REG_SPI2_RCR (0x40024504U) /**< \brief (SPI2) Receive Counter Register */ -#define REG_SPI2_TPR (0x40024508U) /**< \brief (SPI2) Transmit Pointer Register */ -#define REG_SPI2_TCR (0x4002450CU) /**< \brief (SPI2) Transmit Counter Register */ -#define REG_SPI2_RNPR (0x40024510U) /**< \brief (SPI2) Receive Next Pointer Register */ -#define REG_SPI2_RNCR (0x40024514U) /**< \brief (SPI2) Receive Next Counter Register */ -#define REG_SPI2_TNPR (0x40024518U) /**< \brief (SPI2) Transmit Next Pointer Register */ -#define REG_SPI2_TNCR (0x4002451CU) /**< \brief (SPI2) Transmit Next Counter Register */ -#define REG_SPI2_PTCR (0x40024520U) /**< \brief (SPI2) Transfer Control Register */ -#define REG_SPI2_PTSR (0x40024524U) /**< \brief (SPI2) Transfer Status Register */ -#else -#define REG_SPI2_CR (*(__O uint32_t*)0x40024400U) /**< \brief (SPI2) SPI Control Register */ -#define REG_SPI2_MR (*(__IO uint32_t*)0x40024404U) /**< \brief (SPI2) SPI Mode Register */ -#define REG_SPI2_RDR (*(__I uint32_t*)0x40024408U) /**< \brief (SPI2) SPI Receive Data Register */ -#define REG_SPI2_TDR (*(__O uint32_t*)0x4002440CU) /**< \brief (SPI2) SPI Transmit Data Register */ -#define REG_SPI2_SR (*(__I uint32_t*)0x40024410U) /**< \brief (SPI2) SPI Status Register */ -#define REG_SPI2_IER (*(__O uint32_t*)0x40024414U) /**< \brief (SPI2) SPI Interrupt Enable Register */ -#define REG_SPI2_IDR (*(__O uint32_t*)0x40024418U) /**< \brief (SPI2) SPI Interrupt Disable Register */ -#define REG_SPI2_IMR (*(__I uint32_t*)0x4002441CU) /**< \brief (SPI2) SPI Interrupt Mask Register */ -#define REG_SPI2_CSR (*(__IO uint32_t*)0x40024430U) /**< \brief (SPI2) SPI Chip Select Register */ -#define REG_SPI2_CMPR (*(__IO uint32_t*)0x40024448U) /**< \brief (SPI2) SPI Comparison Register */ -#define REG_SPI2_WPMR (*(__IO uint32_t*)0x400244E4U) /**< \brief (SPI2) SPI Write Protection Mode Register */ -#define REG_SPI2_WPSR (*(__I uint32_t*)0x400244E8U) /**< \brief (SPI2) SPI Write Protection Status Register */ -#define REG_SPI2_RPR (*(__IO uint32_t*)0x40024500U) /**< \brief (SPI2) Receive Pointer Register */ -#define REG_SPI2_RCR (*(__IO uint32_t*)0x40024504U) /**< \brief (SPI2) Receive Counter Register */ -#define REG_SPI2_TPR (*(__IO uint32_t*)0x40024508U) /**< \brief (SPI2) Transmit Pointer Register */ -#define REG_SPI2_TCR (*(__IO uint32_t*)0x4002450CU) /**< \brief (SPI2) Transmit Counter Register */ -#define REG_SPI2_RNPR (*(__IO uint32_t*)0x40024510U) /**< \brief (SPI2) Receive Next Pointer Register */ -#define REG_SPI2_RNCR (*(__IO uint32_t*)0x40024514U) /**< \brief (SPI2) Receive Next Counter Register */ -#define REG_SPI2_TNPR (*(__IO uint32_t*)0x40024518U) /**< \brief (SPI2) Transmit Next Pointer Register */ -#define REG_SPI2_TNCR (*(__IO uint32_t*)0x4002451CU) /**< \brief (SPI2) Transmit Next Counter Register */ -#define REG_SPI2_PTCR (*(__O uint32_t*)0x40024520U) /**< \brief (SPI2) Transfer Control Register */ -#define REG_SPI2_PTSR (*(__I uint32_t*)0x40024524U) /**< \brief (SPI2) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SPI2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi3.h deleted file mode 100644 index 4bebf55e31a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi3.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI3_INSTANCE_ -#define _SAMG55_SPI3_INSTANCE_ - -/* ========== Register definition for SPI3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI3_CR (0x40018400U) /**< \brief (SPI3) SPI Control Register */ -#define REG_SPI3_MR (0x40018404U) /**< \brief (SPI3) SPI Mode Register */ -#define REG_SPI3_RDR (0x40018408U) /**< \brief (SPI3) SPI Receive Data Register */ -#define REG_SPI3_TDR (0x4001840CU) /**< \brief (SPI3) SPI Transmit Data Register */ -#define REG_SPI3_SR (0x40018410U) /**< \brief (SPI3) SPI Status Register */ -#define REG_SPI3_IER (0x40018414U) /**< \brief (SPI3) SPI Interrupt Enable Register */ -#define REG_SPI3_IDR (0x40018418U) /**< \brief (SPI3) SPI Interrupt Disable Register */ -#define REG_SPI3_IMR (0x4001841CU) /**< \brief (SPI3) SPI Interrupt Mask Register */ -#define REG_SPI3_CSR (0x40018430U) /**< \brief (SPI3) SPI Chip Select Register */ -#define REG_SPI3_CMPR (0x40018448U) /**< \brief (SPI3) SPI Comparison Register */ -#define REG_SPI3_WPMR (0x400184E4U) /**< \brief (SPI3) SPI Write Protection Mode Register */ -#define REG_SPI3_WPSR (0x400184E8U) /**< \brief (SPI3) SPI Write Protection Status Register */ -#define REG_SPI3_RPR (0x40018500U) /**< \brief (SPI3) Receive Pointer Register */ -#define REG_SPI3_RCR (0x40018504U) /**< \brief (SPI3) Receive Counter Register */ -#define REG_SPI3_TPR (0x40018508U) /**< \brief (SPI3) Transmit Pointer Register */ -#define REG_SPI3_TCR (0x4001850CU) /**< \brief (SPI3) Transmit Counter Register */ -#define REG_SPI3_RNPR (0x40018510U) /**< \brief (SPI3) Receive Next Pointer Register */ -#define REG_SPI3_RNCR (0x40018514U) /**< \brief (SPI3) Receive Next Counter Register */ -#define REG_SPI3_TNPR (0x40018518U) /**< \brief (SPI3) Transmit Next Pointer Register */ -#define REG_SPI3_TNCR (0x4001851CU) /**< \brief (SPI3) Transmit Next Counter Register */ -#define REG_SPI3_PTCR (0x40018520U) /**< \brief (SPI3) Transfer Control Register */ -#define REG_SPI3_PTSR (0x40018524U) /**< \brief (SPI3) Transfer Status Register */ -#else -#define REG_SPI3_CR (*(__O uint32_t*)0x40018400U) /**< \brief (SPI3) SPI Control Register */ -#define REG_SPI3_MR (*(__IO uint32_t*)0x40018404U) /**< \brief (SPI3) SPI Mode Register */ -#define REG_SPI3_RDR (*(__I uint32_t*)0x40018408U) /**< \brief (SPI3) SPI Receive Data Register */ -#define REG_SPI3_TDR (*(__O uint32_t*)0x4001840CU) /**< \brief (SPI3) SPI Transmit Data Register */ -#define REG_SPI3_SR (*(__I uint32_t*)0x40018410U) /**< \brief (SPI3) SPI Status Register */ -#define REG_SPI3_IER (*(__O uint32_t*)0x40018414U) /**< \brief (SPI3) SPI Interrupt Enable Register */ -#define REG_SPI3_IDR (*(__O uint32_t*)0x40018418U) /**< \brief (SPI3) SPI Interrupt Disable Register */ -#define REG_SPI3_IMR (*(__I uint32_t*)0x4001841CU) /**< \brief (SPI3) SPI Interrupt Mask Register */ -#define REG_SPI3_CSR (*(__IO uint32_t*)0x40018430U) /**< \brief (SPI3) SPI Chip Select Register */ -#define REG_SPI3_CMPR (*(__IO uint32_t*)0x40018448U) /**< \brief (SPI3) SPI Comparison Register */ -#define REG_SPI3_WPMR (*(__IO uint32_t*)0x400184E4U) /**< \brief (SPI3) SPI Write Protection Mode Register */ -#define REG_SPI3_WPSR (*(__I uint32_t*)0x400184E8U) /**< \brief (SPI3) SPI Write Protection Status Register */ -#define REG_SPI3_RPR (*(__IO uint32_t*)0x40018500U) /**< \brief (SPI3) Receive Pointer Register */ -#define REG_SPI3_RCR (*(__IO uint32_t*)0x40018504U) /**< \brief (SPI3) Receive Counter Register */ -#define REG_SPI3_TPR (*(__IO uint32_t*)0x40018508U) /**< \brief (SPI3) Transmit Pointer Register */ -#define REG_SPI3_TCR (*(__IO uint32_t*)0x4001850CU) /**< \brief (SPI3) Transmit Counter Register */ -#define REG_SPI3_RNPR (*(__IO uint32_t*)0x40018510U) /**< \brief (SPI3) Receive Next Pointer Register */ -#define REG_SPI3_RNCR (*(__IO uint32_t*)0x40018514U) /**< \brief (SPI3) Receive Next Counter Register */ -#define REG_SPI3_TNPR (*(__IO uint32_t*)0x40018518U) /**< \brief (SPI3) Transmit Next Pointer Register */ -#define REG_SPI3_TNCR (*(__IO uint32_t*)0x4001851CU) /**< \brief (SPI3) Transmit Next Counter Register */ -#define REG_SPI3_PTCR (*(__O uint32_t*)0x40018520U) /**< \brief (SPI3) Transfer Control Register */ -#define REG_SPI3_PTSR (*(__I uint32_t*)0x40018524U) /**< \brief (SPI3) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SPI3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi4.h deleted file mode 100644 index 1a0d2748348..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi4.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI4_INSTANCE_ -#define _SAMG55_SPI4_INSTANCE_ - -/* ========== Register definition for SPI4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI4_CR (0x4001C400U) /**< \brief (SPI4) SPI Control Register */ -#define REG_SPI4_MR (0x4001C404U) /**< \brief (SPI4) SPI Mode Register */ -#define REG_SPI4_RDR (0x4001C408U) /**< \brief (SPI4) SPI Receive Data Register */ -#define REG_SPI4_TDR (0x4001C40CU) /**< \brief (SPI4) SPI Transmit Data Register */ -#define REG_SPI4_SR (0x4001C410U) /**< \brief (SPI4) SPI Status Register */ -#define REG_SPI4_IER (0x4001C414U) /**< \brief (SPI4) SPI Interrupt Enable Register */ -#define REG_SPI4_IDR (0x4001C418U) /**< \brief (SPI4) SPI Interrupt Disable Register */ -#define REG_SPI4_IMR (0x4001C41CU) /**< \brief (SPI4) SPI Interrupt Mask Register */ -#define REG_SPI4_CSR (0x4001C430U) /**< \brief (SPI4) SPI Chip Select Register */ -#define REG_SPI4_CMPR (0x4001C448U) /**< \brief (SPI4) SPI Comparison Register */ -#define REG_SPI4_WPMR (0x4001C4E4U) /**< \brief (SPI4) SPI Write Protection Mode Register */ -#define REG_SPI4_WPSR (0x4001C4E8U) /**< \brief (SPI4) SPI Write Protection Status Register */ -#define REG_SPI4_RPR (0x4001C500U) /**< \brief (SPI4) Receive Pointer Register */ -#define REG_SPI4_RCR (0x4001C504U) /**< \brief (SPI4) Receive Counter Register */ -#define REG_SPI4_TPR (0x4001C508U) /**< \brief (SPI4) Transmit Pointer Register */ -#define REG_SPI4_TCR (0x4001C50CU) /**< \brief (SPI4) Transmit Counter Register */ -#define REG_SPI4_RNPR (0x4001C510U) /**< \brief (SPI4) Receive Next Pointer Register */ -#define REG_SPI4_RNCR (0x4001C514U) /**< \brief (SPI4) Receive Next Counter Register */ -#define REG_SPI4_TNPR (0x4001C518U) /**< \brief (SPI4) Transmit Next Pointer Register */ -#define REG_SPI4_TNCR (0x4001C51CU) /**< \brief (SPI4) Transmit Next Counter Register */ -#define REG_SPI4_PTCR (0x4001C520U) /**< \brief (SPI4) Transfer Control Register */ -#define REG_SPI4_PTSR (0x4001C524U) /**< \brief (SPI4) Transfer Status Register */ -#else -#define REG_SPI4_CR (*(__O uint32_t*)0x4001C400U) /**< \brief (SPI4) SPI Control Register */ -#define REG_SPI4_MR (*(__IO uint32_t*)0x4001C404U) /**< \brief (SPI4) SPI Mode Register */ -#define REG_SPI4_RDR (*(__I uint32_t*)0x4001C408U) /**< \brief (SPI4) SPI Receive Data Register */ -#define REG_SPI4_TDR (*(__O uint32_t*)0x4001C40CU) /**< \brief (SPI4) SPI Transmit Data Register */ -#define REG_SPI4_SR (*(__I uint32_t*)0x4001C410U) /**< \brief (SPI4) SPI Status Register */ -#define REG_SPI4_IER (*(__O uint32_t*)0x4001C414U) /**< \brief (SPI4) SPI Interrupt Enable Register */ -#define REG_SPI4_IDR (*(__O uint32_t*)0x4001C418U) /**< \brief (SPI4) SPI Interrupt Disable Register */ -#define REG_SPI4_IMR (*(__I uint32_t*)0x4001C41CU) /**< \brief (SPI4) SPI Interrupt Mask Register */ -#define REG_SPI4_CSR (*(__IO uint32_t*)0x4001C430U) /**< \brief (SPI4) SPI Chip Select Register */ -#define REG_SPI4_CMPR (*(__IO uint32_t*)0x4001C448U) /**< \brief (SPI4) SPI Comparison Register */ -#define REG_SPI4_WPMR (*(__IO uint32_t*)0x4001C4E4U) /**< \brief (SPI4) SPI Write Protection Mode Register */ -#define REG_SPI4_WPSR (*(__I uint32_t*)0x4001C4E8U) /**< \brief (SPI4) SPI Write Protection Status Register */ -#define REG_SPI4_RPR (*(__IO uint32_t*)0x4001C500U) /**< \brief (SPI4) Receive Pointer Register */ -#define REG_SPI4_RCR (*(__IO uint32_t*)0x4001C504U) /**< \brief (SPI4) Receive Counter Register */ -#define REG_SPI4_TPR (*(__IO uint32_t*)0x4001C508U) /**< \brief (SPI4) Transmit Pointer Register */ -#define REG_SPI4_TCR (*(__IO uint32_t*)0x4001C50CU) /**< \brief (SPI4) Transmit Counter Register */ -#define REG_SPI4_RNPR (*(__IO uint32_t*)0x4001C510U) /**< \brief (SPI4) Receive Next Pointer Register */ -#define REG_SPI4_RNCR (*(__IO uint32_t*)0x4001C514U) /**< \brief (SPI4) Receive Next Counter Register */ -#define REG_SPI4_TNPR (*(__IO uint32_t*)0x4001C518U) /**< \brief (SPI4) Transmit Next Pointer Register */ -#define REG_SPI4_TNCR (*(__IO uint32_t*)0x4001C51CU) /**< \brief (SPI4) Transmit Next Counter Register */ -#define REG_SPI4_PTCR (*(__O uint32_t*)0x4001C520U) /**< \brief (SPI4) Transfer Control Register */ -#define REG_SPI4_PTSR (*(__I uint32_t*)0x4001C524U) /**< \brief (SPI4) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SPI4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi5.h deleted file mode 100644 index d987ccaa0fc..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi5.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI5_INSTANCE_ -#define _SAMG55_SPI5_INSTANCE_ - -/* ========== Register definition for SPI5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI5_CR (0x40008400U) /**< \brief (SPI5) SPI Control Register */ -#define REG_SPI5_MR (0x40008404U) /**< \brief (SPI5) SPI Mode Register */ -#define REG_SPI5_RDR (0x40008408U) /**< \brief (SPI5) SPI Receive Data Register */ -#define REG_SPI5_TDR (0x4000840CU) /**< \brief (SPI5) SPI Transmit Data Register */ -#define REG_SPI5_SR (0x40008410U) /**< \brief (SPI5) SPI Status Register */ -#define REG_SPI5_IER (0x40008414U) /**< \brief (SPI5) SPI Interrupt Enable Register */ -#define REG_SPI5_IDR (0x40008418U) /**< \brief (SPI5) SPI Interrupt Disable Register */ -#define REG_SPI5_IMR (0x4000841CU) /**< \brief (SPI5) SPI Interrupt Mask Register */ -#define REG_SPI5_CSR (0x40008430U) /**< \brief (SPI5) SPI Chip Select Register */ -#define REG_SPI5_CMPR (0x40008448U) /**< \brief (SPI5) SPI Comparison Register */ -#define REG_SPI5_WPMR (0x400084E4U) /**< \brief (SPI5) SPI Write Protection Mode Register */ -#define REG_SPI5_WPSR (0x400084E8U) /**< \brief (SPI5) SPI Write Protection Status Register */ -#define REG_SPI5_RPR (0x40008500U) /**< \brief (SPI5) Receive Pointer Register */ -#define REG_SPI5_RCR (0x40008504U) /**< \brief (SPI5) Receive Counter Register */ -#define REG_SPI5_TPR (0x40008508U) /**< \brief (SPI5) Transmit Pointer Register */ -#define REG_SPI5_TCR (0x4000850CU) /**< \brief (SPI5) Transmit Counter Register */ -#define REG_SPI5_RNPR (0x40008510U) /**< \brief (SPI5) Receive Next Pointer Register */ -#define REG_SPI5_RNCR (0x40008514U) /**< \brief (SPI5) Receive Next Counter Register */ -#define REG_SPI5_TNPR (0x40008518U) /**< \brief (SPI5) Transmit Next Pointer Register */ -#define REG_SPI5_TNCR (0x4000851CU) /**< \brief (SPI5) Transmit Next Counter Register */ -#define REG_SPI5_PTCR (0x40008520U) /**< \brief (SPI5) Transfer Control Register */ -#define REG_SPI5_PTSR (0x40008524U) /**< \brief (SPI5) Transfer Status Register */ -#else -#define REG_SPI5_CR (*(__O uint32_t*)0x40008400U) /**< \brief (SPI5) SPI Control Register */ -#define REG_SPI5_MR (*(__IO uint32_t*)0x40008404U) /**< \brief (SPI5) SPI Mode Register */ -#define REG_SPI5_RDR (*(__I uint32_t*)0x40008408U) /**< \brief (SPI5) SPI Receive Data Register */ -#define REG_SPI5_TDR (*(__O uint32_t*)0x4000840CU) /**< \brief (SPI5) SPI Transmit Data Register */ -#define REG_SPI5_SR (*(__I uint32_t*)0x40008410U) /**< \brief (SPI5) SPI Status Register */ -#define REG_SPI5_IER (*(__O uint32_t*)0x40008414U) /**< \brief (SPI5) SPI Interrupt Enable Register */ -#define REG_SPI5_IDR (*(__O uint32_t*)0x40008418U) /**< \brief (SPI5) SPI Interrupt Disable Register */ -#define REG_SPI5_IMR (*(__I uint32_t*)0x4000841CU) /**< \brief (SPI5) SPI Interrupt Mask Register */ -#define REG_SPI5_CSR (*(__IO uint32_t*)0x40008430U) /**< \brief (SPI5) SPI Chip Select Register */ -#define REG_SPI5_CMPR (*(__IO uint32_t*)0x40008448U) /**< \brief (SPI5) SPI Comparison Register */ -#define REG_SPI5_WPMR (*(__IO uint32_t*)0x400084E4U) /**< \brief (SPI5) SPI Write Protection Mode Register */ -#define REG_SPI5_WPSR (*(__I uint32_t*)0x400084E8U) /**< \brief (SPI5) SPI Write Protection Status Register */ -#define REG_SPI5_RPR (*(__IO uint32_t*)0x40008500U) /**< \brief (SPI5) Receive Pointer Register */ -#define REG_SPI5_RCR (*(__IO uint32_t*)0x40008504U) /**< \brief (SPI5) Receive Counter Register */ -#define REG_SPI5_TPR (*(__IO uint32_t*)0x40008508U) /**< \brief (SPI5) Transmit Pointer Register */ -#define REG_SPI5_TCR (*(__IO uint32_t*)0x4000850CU) /**< \brief (SPI5) Transmit Counter Register */ -#define REG_SPI5_RNPR (*(__IO uint32_t*)0x40008510U) /**< \brief (SPI5) Receive Next Pointer Register */ -#define REG_SPI5_RNCR (*(__IO uint32_t*)0x40008514U) /**< \brief (SPI5) Receive Next Counter Register */ -#define REG_SPI5_TNPR (*(__IO uint32_t*)0x40008518U) /**< \brief (SPI5) Transmit Next Pointer Register */ -#define REG_SPI5_TNCR (*(__IO uint32_t*)0x4000851CU) /**< \brief (SPI5) Transmit Next Counter Register */ -#define REG_SPI5_PTCR (*(__O uint32_t*)0x40008520U) /**< \brief (SPI5) Transfer Control Register */ -#define REG_SPI5_PTSR (*(__I uint32_t*)0x40008524U) /**< \brief (SPI5) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SPI5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi6.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi6.h deleted file mode 100644 index eb59aca15a9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi6.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI6_INSTANCE_ -#define _SAMG55_SPI6_INSTANCE_ - -/* ========== Register definition for SPI6 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI6_CR (0x40040400U) /**< \brief (SPI6) SPI Control Register */ -#define REG_SPI6_MR (0x40040404U) /**< \brief (SPI6) SPI Mode Register */ -#define REG_SPI6_RDR (0x40040408U) /**< \brief (SPI6) SPI Receive Data Register */ -#define REG_SPI6_TDR (0x4004040CU) /**< \brief (SPI6) SPI Transmit Data Register */ -#define REG_SPI6_SR (0x40040410U) /**< \brief (SPI6) SPI Status Register */ -#define REG_SPI6_IER (0x40040414U) /**< \brief (SPI6) SPI Interrupt Enable Register */ -#define REG_SPI6_IDR (0x40040418U) /**< \brief (SPI6) SPI Interrupt Disable Register */ -#define REG_SPI6_IMR (0x4004041CU) /**< \brief (SPI6) SPI Interrupt Mask Register */ -#define REG_SPI6_CSR (0x40040430U) /**< \brief (SPI6) SPI Chip Select Register */ -#define REG_SPI6_CMPR (0x40040448U) /**< \brief (SPI6) SPI Comparison Register */ -#define REG_SPI6_WPMR (0x400404E4U) /**< \brief (SPI6) SPI Write Protection Mode Register */ -#define REG_SPI6_WPSR (0x400404E8U) /**< \brief (SPI6) SPI Write Protection Status Register */ -#define REG_SPI6_RPR (0x40040500U) /**< \brief (SPI6) Receive Pointer Register */ -#define REG_SPI6_RCR (0x40040504U) /**< \brief (SPI6) Receive Counter Register */ -#define REG_SPI6_TPR (0x40040508U) /**< \brief (SPI6) Transmit Pointer Register */ -#define REG_SPI6_TCR (0x4004050CU) /**< \brief (SPI6) Transmit Counter Register */ -#define REG_SPI6_RNPR (0x40040510U) /**< \brief (SPI6) Receive Next Pointer Register */ -#define REG_SPI6_RNCR (0x40040514U) /**< \brief (SPI6) Receive Next Counter Register */ -#define REG_SPI6_TNPR (0x40040518U) /**< \brief (SPI6) Transmit Next Pointer Register */ -#define REG_SPI6_TNCR (0x4004051CU) /**< \brief (SPI6) Transmit Next Counter Register */ -#define REG_SPI6_PTCR (0x40040520U) /**< \brief (SPI6) Transfer Control Register */ -#define REG_SPI6_PTSR (0x40040524U) /**< \brief (SPI6) Transfer Status Register */ -#else -#define REG_SPI6_CR (*(__O uint32_t*)0x40040400U) /**< \brief (SPI6) SPI Control Register */ -#define REG_SPI6_MR (*(__IO uint32_t*)0x40040404U) /**< \brief (SPI6) SPI Mode Register */ -#define REG_SPI6_RDR (*(__I uint32_t*)0x40040408U) /**< \brief (SPI6) SPI Receive Data Register */ -#define REG_SPI6_TDR (*(__O uint32_t*)0x4004040CU) /**< \brief (SPI6) SPI Transmit Data Register */ -#define REG_SPI6_SR (*(__I uint32_t*)0x40040410U) /**< \brief (SPI6) SPI Status Register */ -#define REG_SPI6_IER (*(__O uint32_t*)0x40040414U) /**< \brief (SPI6) SPI Interrupt Enable Register */ -#define REG_SPI6_IDR (*(__O uint32_t*)0x40040418U) /**< \brief (SPI6) SPI Interrupt Disable Register */ -#define REG_SPI6_IMR (*(__I uint32_t*)0x4004041CU) /**< \brief (SPI6) SPI Interrupt Mask Register */ -#define REG_SPI6_CSR (*(__IO uint32_t*)0x40040430U) /**< \brief (SPI6) SPI Chip Select Register */ -#define REG_SPI6_CMPR (*(__IO uint32_t*)0x40040448U) /**< \brief (SPI6) SPI Comparison Register */ -#define REG_SPI6_WPMR (*(__IO uint32_t*)0x400404E4U) /**< \brief (SPI6) SPI Write Protection Mode Register */ -#define REG_SPI6_WPSR (*(__I uint32_t*)0x400404E8U) /**< \brief (SPI6) SPI Write Protection Status Register */ -#define REG_SPI6_RPR (*(__IO uint32_t*)0x40040500U) /**< \brief (SPI6) Receive Pointer Register */ -#define REG_SPI6_RCR (*(__IO uint32_t*)0x40040504U) /**< \brief (SPI6) Receive Counter Register */ -#define REG_SPI6_TPR (*(__IO uint32_t*)0x40040508U) /**< \brief (SPI6) Transmit Pointer Register */ -#define REG_SPI6_TCR (*(__IO uint32_t*)0x4004050CU) /**< \brief (SPI6) Transmit Counter Register */ -#define REG_SPI6_RNPR (*(__IO uint32_t*)0x40040510U) /**< \brief (SPI6) Receive Next Pointer Register */ -#define REG_SPI6_RNCR (*(__IO uint32_t*)0x40040514U) /**< \brief (SPI6) Receive Next Counter Register */ -#define REG_SPI6_TNPR (*(__IO uint32_t*)0x40040518U) /**< \brief (SPI6) Transmit Next Pointer Register */ -#define REG_SPI6_TNCR (*(__IO uint32_t*)0x4004051CU) /**< \brief (SPI6) Transmit Next Counter Register */ -#define REG_SPI6_PTCR (*(__O uint32_t*)0x40040520U) /**< \brief (SPI6) Transfer Control Register */ -#define REG_SPI6_PTSR (*(__I uint32_t*)0x40040524U) /**< \brief (SPI6) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SPI6_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi7.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi7.h deleted file mode 100644 index 909d85ffa07..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi7.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SPI7_INSTANCE_ -#define _SAMG55_SPI7_INSTANCE_ - -/* ========== Register definition for SPI7 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI7_CR (0x40034400U) /**< \brief (SPI7) SPI Control Register */ -#define REG_SPI7_MR (0x40034404U) /**< \brief (SPI7) SPI Mode Register */ -#define REG_SPI7_RDR (0x40034408U) /**< \brief (SPI7) SPI Receive Data Register */ -#define REG_SPI7_TDR (0x4003440CU) /**< \brief (SPI7) SPI Transmit Data Register */ -#define REG_SPI7_SR (0x40034410U) /**< \brief (SPI7) SPI Status Register */ -#define REG_SPI7_IER (0x40034414U) /**< \brief (SPI7) SPI Interrupt Enable Register */ -#define REG_SPI7_IDR (0x40034418U) /**< \brief (SPI7) SPI Interrupt Disable Register */ -#define REG_SPI7_IMR (0x4003441CU) /**< \brief (SPI7) SPI Interrupt Mask Register */ -#define REG_SPI7_CSR (0x40034430U) /**< \brief (SPI7) SPI Chip Select Register */ -#define REG_SPI7_CMPR (0x40034448U) /**< \brief (SPI7) SPI Comparison Register */ -#define REG_SPI7_WPMR (0x400344E4U) /**< \brief (SPI7) SPI Write Protection Mode Register */ -#define REG_SPI7_WPSR (0x400344E8U) /**< \brief (SPI7) SPI Write Protection Status Register */ -#define REG_SPI7_RPR (0x40034500U) /**< \brief (SPI7) Receive Pointer Register */ -#define REG_SPI7_RCR (0x40034504U) /**< \brief (SPI7) Receive Counter Register */ -#define REG_SPI7_TPR (0x40034508U) /**< \brief (SPI7) Transmit Pointer Register */ -#define REG_SPI7_TCR (0x4003450CU) /**< \brief (SPI7) Transmit Counter Register */ -#define REG_SPI7_RNPR (0x40034510U) /**< \brief (SPI7) Receive Next Pointer Register */ -#define REG_SPI7_RNCR (0x40034514U) /**< \brief (SPI7) Receive Next Counter Register */ -#define REG_SPI7_TNPR (0x40034518U) /**< \brief (SPI7) Transmit Next Pointer Register */ -#define REG_SPI7_TNCR (0x4003451CU) /**< \brief (SPI7) Transmit Next Counter Register */ -#define REG_SPI7_PTCR (0x40034520U) /**< \brief (SPI7) Transfer Control Register */ -#define REG_SPI7_PTSR (0x40034524U) /**< \brief (SPI7) Transfer Status Register */ -#else -#define REG_SPI7_CR (*(__O uint32_t*)0x40034400U) /**< \brief (SPI7) SPI Control Register */ -#define REG_SPI7_MR (*(__IO uint32_t*)0x40034404U) /**< \brief (SPI7) SPI Mode Register */ -#define REG_SPI7_RDR (*(__I uint32_t*)0x40034408U) /**< \brief (SPI7) SPI Receive Data Register */ -#define REG_SPI7_TDR (*(__O uint32_t*)0x4003440CU) /**< \brief (SPI7) SPI Transmit Data Register */ -#define REG_SPI7_SR (*(__I uint32_t*)0x40034410U) /**< \brief (SPI7) SPI Status Register */ -#define REG_SPI7_IER (*(__O uint32_t*)0x40034414U) /**< \brief (SPI7) SPI Interrupt Enable Register */ -#define REG_SPI7_IDR (*(__O uint32_t*)0x40034418U) /**< \brief (SPI7) SPI Interrupt Disable Register */ -#define REG_SPI7_IMR (*(__I uint32_t*)0x4003441CU) /**< \brief (SPI7) SPI Interrupt Mask Register */ -#define REG_SPI7_CSR (*(__IO uint32_t*)0x40034430U) /**< \brief (SPI7) SPI Chip Select Register */ -#define REG_SPI7_CMPR (*(__IO uint32_t*)0x40034448U) /**< \brief (SPI7) SPI Comparison Register */ -#define REG_SPI7_WPMR (*(__IO uint32_t*)0x400344E4U) /**< \brief (SPI7) SPI Write Protection Mode Register */ -#define REG_SPI7_WPSR (*(__I uint32_t*)0x400344E8U) /**< \brief (SPI7) SPI Write Protection Status Register */ -#define REG_SPI7_RPR (*(__IO uint32_t*)0x40034500U) /**< \brief (SPI7) Receive Pointer Register */ -#define REG_SPI7_RCR (*(__IO uint32_t*)0x40034504U) /**< \brief (SPI7) Receive Counter Register */ -#define REG_SPI7_TPR (*(__IO uint32_t*)0x40034508U) /**< \brief (SPI7) Transmit Pointer Register */ -#define REG_SPI7_TCR (*(__IO uint32_t*)0x4003450CU) /**< \brief (SPI7) Transmit Counter Register */ -#define REG_SPI7_RNPR (*(__IO uint32_t*)0x40034510U) /**< \brief (SPI7) Receive Next Pointer Register */ -#define REG_SPI7_RNCR (*(__IO uint32_t*)0x40034514U) /**< \brief (SPI7) Receive Next Counter Register */ -#define REG_SPI7_TNPR (*(__IO uint32_t*)0x40034518U) /**< \brief (SPI7) Transmit Next Pointer Register */ -#define REG_SPI7_TNCR (*(__IO uint32_t*)0x4003451CU) /**< \brief (SPI7) Transmit Next Counter Register */ -#define REG_SPI7_PTCR (*(__O uint32_t*)0x40034520U) /**< \brief (SPI7) Transfer Control Register */ -#define REG_SPI7_PTSR (*(__I uint32_t*)0x40034524U) /**< \brief (SPI7) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SPI7_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_supc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_supc.h deleted file mode 100644 index 8cf5bf53bc3..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_supc.h +++ /dev/null @@ -1,67 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_SUPC_INSTANCE_ -#define _SAMG55_SUPC_INSTANCE_ - -/* ========== Register definition for SUPC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SUPC_CR (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ -#define REG_SUPC_WUIR (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ -#define REG_SUPC_SR (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -#define REG_SUPC_PWMR (0x400E142CU) /**< \brief (SUPC) Supply Controller Power Mode Register */ -#else -#define REG_SUPC_CR (*(__O uint32_t*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR (*(__IO uint32_t*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ -#define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ -#define REG_SUPC_SR (*(__I uint32_t*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -#define REG_SUPC_PWMR (*(__IO uint32_t*)0x400E142CU) /**< \brief (SUPC) Supply Controller Power Mode Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_SUPC_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_tc0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_tc0.h deleted file mode 100644 index a86eb7bd96a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_tc0.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TC0_INSTANCE_ -#define _SAMG55_TC0_INSTANCE_ - -/* ========== Register definition for TC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC0_CCR0 (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_SMMR0 (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC0_CV0 (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_SMMR1 (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC0_CV1 (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_SMMR2 (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC0_CV2 (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR (0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR (0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_WPMR (0x400100E4U) /**< \brief (TC0) Write Protection Mode Register */ -#define REG_TC0_RPR0 (0x40010100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */ -#define REG_TC0_RCR0 (0x40010104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */ -#define REG_TC0_RNPR0 (0x40010110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */ -#define REG_TC0_RNCR0 (0x40010114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */ -#define REG_TC0_PTCR0 (0x40010120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */ -#define REG_TC0_PTSR0 (0x40010124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */ -#else -#define REG_TC0_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC0_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC0_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC0_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC0) Write Protection Mode Register */ -#define REG_TC0_RPR0 (*(__IO uint32_t*)0x40010100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */ -#define REG_TC0_RCR0 (*(__IO uint32_t*)0x40010104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */ -#define REG_TC0_RNPR0 (*(__IO uint32_t*)0x40010110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */ -#define REG_TC0_RNCR0 (*(__IO uint32_t*)0x40010114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */ -#define REG_TC0_PTCR0 (*(__O uint32_t*)0x40010120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */ -#define REG_TC0_PTSR0 (*(__I uint32_t*)0x40010124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TC0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_tc1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_tc1.h deleted file mode 100644 index d481db17cf7..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_tc1.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TC1_INSTANCE_ -#define _SAMG55_TC1_INSTANCE_ - -/* ========== Register definition for TC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC1_CCR0 (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_SMMR0 (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC1_CV0 (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_SMMR1 (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC1_CV1 (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_SMMR2 (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC1_CV2 (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR (0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR (0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_WPMR (0x400140E4U) /**< \brief (TC1) Write Protection Mode Register */ -#else -#define REG_TC1_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC1_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC1_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC1_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC1) Write Protection Mode Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TC1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi0.h deleted file mode 100644 index 70ca64c15fe..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi0.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI0_INSTANCE_ -#define _SAMG55_TWI0_INSTANCE_ - -/* ========== Register definition for TWI0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI0_CR (0x4000C600U) /**< \brief (TWI0) TWI Control Register */ -#define REG_TWI0_MMR (0x4000C604U) /**< \brief (TWI0) TWI Master Mode Register */ -#define REG_TWI0_SMR (0x4000C608U) /**< \brief (TWI0) TWI Slave Mode Register */ -#define REG_TWI0_IADR (0x4000C60CU) /**< \brief (TWI0) TWI Internal Address Register */ -#define REG_TWI0_CWGR (0x4000C610U) /**< \brief (TWI0) TWI Clock Waveform Generator Register */ -#define REG_TWI0_SR (0x4000C620U) /**< \brief (TWI0) TWI Status Register */ -#define REG_TWI0_IER (0x4000C624U) /**< \brief (TWI0) TWI Interrupt Enable Register */ -#define REG_TWI0_IDR (0x4000C628U) /**< \brief (TWI0) TWI Interrupt Disable Register */ -#define REG_TWI0_IMR (0x4000C62CU) /**< \brief (TWI0) TWI Interrupt Mask Register */ -#define REG_TWI0_RHR (0x4000C630U) /**< \brief (TWI0) TWI Receive Holding Register */ -#define REG_TWI0_THR (0x4000C634U) /**< \brief (TWI0) TWI Transmit Holding Register */ -#define REG_TWI0_SMBTR (0x4000C638U) /**< \brief (TWI0) TWI SMBus Timing Register */ -#define REG_TWI0_ACR (0x4000C640U) /**< \brief (TWI0) TWI Alternative Command Register */ -#define REG_TWI0_FILTR (0x4000C644U) /**< \brief (TWI0) TWI Filter Register */ -#define REG_TWI0_SWMR (0x4000C64CU) /**< \brief (TWI0) TWI SleepWalking Matching Register */ -#define REG_TWI0_WPMR (0x4000C6E4U) /**< \brief (TWI0) TWI Write Protection Mode Register */ -#define REG_TWI0_WPSR (0x4000C6E8U) /**< \brief (TWI0) TWI Write Protection Status Register */ -#define REG_TWI0_RPR (0x4000C700U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR (0x4000C704U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR (0x4000C708U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR (0x4000C70CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR (0x4000C710U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR (0x4000C714U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR (0x4000C718U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR (0x4000C71CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR (0x4000C720U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR (0x4000C724U) /**< \brief (TWI0) Transfer Status Register */ -#else -#define REG_TWI0_CR (*(__O uint32_t*)0x4000C600U) /**< \brief (TWI0) TWI Control Register */ -#define REG_TWI0_MMR (*(__IO uint32_t*)0x4000C604U) /**< \brief (TWI0) TWI Master Mode Register */ -#define REG_TWI0_SMR (*(__IO uint32_t*)0x4000C608U) /**< \brief (TWI0) TWI Slave Mode Register */ -#define REG_TWI0_IADR (*(__IO uint32_t*)0x4000C60CU) /**< \brief (TWI0) TWI Internal Address Register */ -#define REG_TWI0_CWGR (*(__IO uint32_t*)0x4000C610U) /**< \brief (TWI0) TWI Clock Waveform Generator Register */ -#define REG_TWI0_SR (*(__I uint32_t*)0x4000C620U) /**< \brief (TWI0) TWI Status Register */ -#define REG_TWI0_IER (*(__O uint32_t*)0x4000C624U) /**< \brief (TWI0) TWI Interrupt Enable Register */ -#define REG_TWI0_IDR (*(__O uint32_t*)0x4000C628U) /**< \brief (TWI0) TWI Interrupt Disable Register */ -#define REG_TWI0_IMR (*(__I uint32_t*)0x4000C62CU) /**< \brief (TWI0) TWI Interrupt Mask Register */ -#define REG_TWI0_RHR (*(__I uint32_t*)0x4000C630U) /**< \brief (TWI0) TWI Receive Holding Register */ -#define REG_TWI0_THR (*(__O uint32_t*)0x4000C634U) /**< \brief (TWI0) TWI Transmit Holding Register */ -#define REG_TWI0_SMBTR (*(__IO uint32_t*)0x4000C638U) /**< \brief (TWI0) TWI SMBus Timing Register */ -#define REG_TWI0_ACR (*(__IO uint32_t*)0x4000C640U) /**< \brief (TWI0) TWI Alternative Command Register */ -#define REG_TWI0_FILTR (*(__IO uint32_t*)0x4000C644U) /**< \brief (TWI0) TWI Filter Register */ -#define REG_TWI0_SWMR (*(__IO uint32_t*)0x4000C64CU) /**< \brief (TWI0) TWI SleepWalking Matching Register */ -#define REG_TWI0_WPMR (*(__IO uint32_t*)0x4000C6E4U) /**< \brief (TWI0) TWI Write Protection Mode Register */ -#define REG_TWI0_WPSR (*(__I uint32_t*)0x4000C6E8U) /**< \brief (TWI0) TWI Write Protection Status Register */ -#define REG_TWI0_RPR (*(__IO uint32_t*)0x4000C700U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR (*(__IO uint32_t*)0x4000C704U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR (*(__IO uint32_t*)0x4000C708U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR (*(__IO uint32_t*)0x4000C70CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR (*(__IO uint32_t*)0x4000C710U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR (*(__IO uint32_t*)0x4000C714U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR (*(__IO uint32_t*)0x4000C718U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR (*(__IO uint32_t*)0x4000C71CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR (*(__O uint32_t*)0x4000C720U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR (*(__I uint32_t*)0x4000C724U) /**< \brief (TWI0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TWI0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi1.h deleted file mode 100644 index c82001baa6b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi1.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI1_INSTANCE_ -#define _SAMG55_TWI1_INSTANCE_ - -/* ========== Register definition for TWI1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI1_CR (0x40020600U) /**< \brief (TWI1) TWI Control Register */ -#define REG_TWI1_MMR (0x40020604U) /**< \brief (TWI1) TWI Master Mode Register */ -#define REG_TWI1_SMR (0x40020608U) /**< \brief (TWI1) TWI Slave Mode Register */ -#define REG_TWI1_IADR (0x4002060CU) /**< \brief (TWI1) TWI Internal Address Register */ -#define REG_TWI1_CWGR (0x40020610U) /**< \brief (TWI1) TWI Clock Waveform Generator Register */ -#define REG_TWI1_SR (0x40020620U) /**< \brief (TWI1) TWI Status Register */ -#define REG_TWI1_IER (0x40020624U) /**< \brief (TWI1) TWI Interrupt Enable Register */ -#define REG_TWI1_IDR (0x40020628U) /**< \brief (TWI1) TWI Interrupt Disable Register */ -#define REG_TWI1_IMR (0x4002062CU) /**< \brief (TWI1) TWI Interrupt Mask Register */ -#define REG_TWI1_RHR (0x40020630U) /**< \brief (TWI1) TWI Receive Holding Register */ -#define REG_TWI1_THR (0x40020634U) /**< \brief (TWI1) TWI Transmit Holding Register */ -#define REG_TWI1_SMBTR (0x40020638U) /**< \brief (TWI1) TWI SMBus Timing Register */ -#define REG_TWI1_ACR (0x40020640U) /**< \brief (TWI1) TWI Alternative Command Register */ -#define REG_TWI1_FILTR (0x40020644U) /**< \brief (TWI1) TWI Filter Register */ -#define REG_TWI1_SWMR (0x4002064CU) /**< \brief (TWI1) TWI SleepWalking Matching Register */ -#define REG_TWI1_WPMR (0x400206E4U) /**< \brief (TWI1) TWI Write Protection Mode Register */ -#define REG_TWI1_WPSR (0x400206E8U) /**< \brief (TWI1) TWI Write Protection Status Register */ -#define REG_TWI1_RPR (0x40020700U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR (0x40020704U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR (0x40020708U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR (0x4002070CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR (0x40020710U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR (0x40020714U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR (0x40020718U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR (0x4002071CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR (0x40020720U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR (0x40020724U) /**< \brief (TWI1) Transfer Status Register */ -#else -#define REG_TWI1_CR (*(__O uint32_t*)0x40020600U) /**< \brief (TWI1) TWI Control Register */ -#define REG_TWI1_MMR (*(__IO uint32_t*)0x40020604U) /**< \brief (TWI1) TWI Master Mode Register */ -#define REG_TWI1_SMR (*(__IO uint32_t*)0x40020608U) /**< \brief (TWI1) TWI Slave Mode Register */ -#define REG_TWI1_IADR (*(__IO uint32_t*)0x4002060CU) /**< \brief (TWI1) TWI Internal Address Register */ -#define REG_TWI1_CWGR (*(__IO uint32_t*)0x40020610U) /**< \brief (TWI1) TWI Clock Waveform Generator Register */ -#define REG_TWI1_SR (*(__I uint32_t*)0x40020620U) /**< \brief (TWI1) TWI Status Register */ -#define REG_TWI1_IER (*(__O uint32_t*)0x40020624U) /**< \brief (TWI1) TWI Interrupt Enable Register */ -#define REG_TWI1_IDR (*(__O uint32_t*)0x40020628U) /**< \brief (TWI1) TWI Interrupt Disable Register */ -#define REG_TWI1_IMR (*(__I uint32_t*)0x4002062CU) /**< \brief (TWI1) TWI Interrupt Mask Register */ -#define REG_TWI1_RHR (*(__I uint32_t*)0x40020630U) /**< \brief (TWI1) TWI Receive Holding Register */ -#define REG_TWI1_THR (*(__O uint32_t*)0x40020634U) /**< \brief (TWI1) TWI Transmit Holding Register */ -#define REG_TWI1_SMBTR (*(__IO uint32_t*)0x40020638U) /**< \brief (TWI1) TWI SMBus Timing Register */ -#define REG_TWI1_ACR (*(__IO uint32_t*)0x40020640U) /**< \brief (TWI1) TWI Alternative Command Register */ -#define REG_TWI1_FILTR (*(__IO uint32_t*)0x40020644U) /**< \brief (TWI1) TWI Filter Register */ -#define REG_TWI1_SWMR (*(__IO uint32_t*)0x4002064CU) /**< \brief (TWI1) TWI SleepWalking Matching Register */ -#define REG_TWI1_WPMR (*(__IO uint32_t*)0x400206E4U) /**< \brief (TWI1) TWI Write Protection Mode Register */ -#define REG_TWI1_WPSR (*(__I uint32_t*)0x400206E8U) /**< \brief (TWI1) TWI Write Protection Status Register */ -#define REG_TWI1_RPR (*(__IO uint32_t*)0x40020700U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR (*(__IO uint32_t*)0x40020704U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR (*(__IO uint32_t*)0x40020708U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR (*(__IO uint32_t*)0x4002070CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR (*(__IO uint32_t*)0x40020710U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR (*(__IO uint32_t*)0x40020714U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR (*(__IO uint32_t*)0x40020718U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR (*(__IO uint32_t*)0x4002071CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR (*(__O uint32_t*)0x40020720U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR (*(__I uint32_t*)0x40020724U) /**< \brief (TWI1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TWI1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi2.h deleted file mode 100644 index 292f3cc9b04..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi2.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI2_INSTANCE_ -#define _SAMG55_TWI2_INSTANCE_ - -/* ========== Register definition for TWI2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI2_CR (0x40024600U) /**< \brief (TWI2) TWI Control Register */ -#define REG_TWI2_MMR (0x40024604U) /**< \brief (TWI2) TWI Master Mode Register */ -#define REG_TWI2_SMR (0x40024608U) /**< \brief (TWI2) TWI Slave Mode Register */ -#define REG_TWI2_IADR (0x4002460CU) /**< \brief (TWI2) TWI Internal Address Register */ -#define REG_TWI2_CWGR (0x40024610U) /**< \brief (TWI2) TWI Clock Waveform Generator Register */ -#define REG_TWI2_SR (0x40024620U) /**< \brief (TWI2) TWI Status Register */ -#define REG_TWI2_IER (0x40024624U) /**< \brief (TWI2) TWI Interrupt Enable Register */ -#define REG_TWI2_IDR (0x40024628U) /**< \brief (TWI2) TWI Interrupt Disable Register */ -#define REG_TWI2_IMR (0x4002462CU) /**< \brief (TWI2) TWI Interrupt Mask Register */ -#define REG_TWI2_RHR (0x40024630U) /**< \brief (TWI2) TWI Receive Holding Register */ -#define REG_TWI2_THR (0x40024634U) /**< \brief (TWI2) TWI Transmit Holding Register */ -#define REG_TWI2_SMBTR (0x40024638U) /**< \brief (TWI2) TWI SMBus Timing Register */ -#define REG_TWI2_ACR (0x40024640U) /**< \brief (TWI2) TWI Alternative Command Register */ -#define REG_TWI2_FILTR (0x40024644U) /**< \brief (TWI2) TWI Filter Register */ -#define REG_TWI2_SWMR (0x4002464CU) /**< \brief (TWI2) TWI SleepWalking Matching Register */ -#define REG_TWI2_WPMR (0x400246E4U) /**< \brief (TWI2) TWI Write Protection Mode Register */ -#define REG_TWI2_WPSR (0x400246E8U) /**< \brief (TWI2) TWI Write Protection Status Register */ -#define REG_TWI2_RPR (0x40024700U) /**< \brief (TWI2) Receive Pointer Register */ -#define REG_TWI2_RCR (0x40024704U) /**< \brief (TWI2) Receive Counter Register */ -#define REG_TWI2_TPR (0x40024708U) /**< \brief (TWI2) Transmit Pointer Register */ -#define REG_TWI2_TCR (0x4002470CU) /**< \brief (TWI2) Transmit Counter Register */ -#define REG_TWI2_RNPR (0x40024710U) /**< \brief (TWI2) Receive Next Pointer Register */ -#define REG_TWI2_RNCR (0x40024714U) /**< \brief (TWI2) Receive Next Counter Register */ -#define REG_TWI2_TNPR (0x40024718U) /**< \brief (TWI2) Transmit Next Pointer Register */ -#define REG_TWI2_TNCR (0x4002471CU) /**< \brief (TWI2) Transmit Next Counter Register */ -#define REG_TWI2_PTCR (0x40024720U) /**< \brief (TWI2) Transfer Control Register */ -#define REG_TWI2_PTSR (0x40024724U) /**< \brief (TWI2) Transfer Status Register */ -#else -#define REG_TWI2_CR (*(__O uint32_t*)0x40024600U) /**< \brief (TWI2) TWI Control Register */ -#define REG_TWI2_MMR (*(__IO uint32_t*)0x40024604U) /**< \brief (TWI2) TWI Master Mode Register */ -#define REG_TWI2_SMR (*(__IO uint32_t*)0x40024608U) /**< \brief (TWI2) TWI Slave Mode Register */ -#define REG_TWI2_IADR (*(__IO uint32_t*)0x4002460CU) /**< \brief (TWI2) TWI Internal Address Register */ -#define REG_TWI2_CWGR (*(__IO uint32_t*)0x40024610U) /**< \brief (TWI2) TWI Clock Waveform Generator Register */ -#define REG_TWI2_SR (*(__I uint32_t*)0x40024620U) /**< \brief (TWI2) TWI Status Register */ -#define REG_TWI2_IER (*(__O uint32_t*)0x40024624U) /**< \brief (TWI2) TWI Interrupt Enable Register */ -#define REG_TWI2_IDR (*(__O uint32_t*)0x40024628U) /**< \brief (TWI2) TWI Interrupt Disable Register */ -#define REG_TWI2_IMR (*(__I uint32_t*)0x4002462CU) /**< \brief (TWI2) TWI Interrupt Mask Register */ -#define REG_TWI2_RHR (*(__I uint32_t*)0x40024630U) /**< \brief (TWI2) TWI Receive Holding Register */ -#define REG_TWI2_THR (*(__O uint32_t*)0x40024634U) /**< \brief (TWI2) TWI Transmit Holding Register */ -#define REG_TWI2_SMBTR (*(__IO uint32_t*)0x40024638U) /**< \brief (TWI2) TWI SMBus Timing Register */ -#define REG_TWI2_ACR (*(__IO uint32_t*)0x40024640U) /**< \brief (TWI2) TWI Alternative Command Register */ -#define REG_TWI2_FILTR (*(__IO uint32_t*)0x40024644U) /**< \brief (TWI2) TWI Filter Register */ -#define REG_TWI2_SWMR (*(__IO uint32_t*)0x4002464CU) /**< \brief (TWI2) TWI SleepWalking Matching Register */ -#define REG_TWI2_WPMR (*(__IO uint32_t*)0x400246E4U) /**< \brief (TWI2) TWI Write Protection Mode Register */ -#define REG_TWI2_WPSR (*(__I uint32_t*)0x400246E8U) /**< \brief (TWI2) TWI Write Protection Status Register */ -#define REG_TWI2_RPR (*(__IO uint32_t*)0x40024700U) /**< \brief (TWI2) Receive Pointer Register */ -#define REG_TWI2_RCR (*(__IO uint32_t*)0x40024704U) /**< \brief (TWI2) Receive Counter Register */ -#define REG_TWI2_TPR (*(__IO uint32_t*)0x40024708U) /**< \brief (TWI2) Transmit Pointer Register */ -#define REG_TWI2_TCR (*(__IO uint32_t*)0x4002470CU) /**< \brief (TWI2) Transmit Counter Register */ -#define REG_TWI2_RNPR (*(__IO uint32_t*)0x40024710U) /**< \brief (TWI2) Receive Next Pointer Register */ -#define REG_TWI2_RNCR (*(__IO uint32_t*)0x40024714U) /**< \brief (TWI2) Receive Next Counter Register */ -#define REG_TWI2_TNPR (*(__IO uint32_t*)0x40024718U) /**< \brief (TWI2) Transmit Next Pointer Register */ -#define REG_TWI2_TNCR (*(__IO uint32_t*)0x4002471CU) /**< \brief (TWI2) Transmit Next Counter Register */ -#define REG_TWI2_PTCR (*(__O uint32_t*)0x40024720U) /**< \brief (TWI2) Transfer Control Register */ -#define REG_TWI2_PTSR (*(__I uint32_t*)0x40024724U) /**< \brief (TWI2) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TWI2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi3.h deleted file mode 100644 index fe9d9cecb7b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi3.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI3_INSTANCE_ -#define _SAMG55_TWI3_INSTANCE_ - -/* ========== Register definition for TWI3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI3_CR (0x40018600U) /**< \brief (TWI3) TWI Control Register */ -#define REG_TWI3_MMR (0x40018604U) /**< \brief (TWI3) TWI Master Mode Register */ -#define REG_TWI3_SMR (0x40018608U) /**< \brief (TWI3) TWI Slave Mode Register */ -#define REG_TWI3_IADR (0x4001860CU) /**< \brief (TWI3) TWI Internal Address Register */ -#define REG_TWI3_CWGR (0x40018610U) /**< \brief (TWI3) TWI Clock Waveform Generator Register */ -#define REG_TWI3_SR (0x40018620U) /**< \brief (TWI3) TWI Status Register */ -#define REG_TWI3_IER (0x40018624U) /**< \brief (TWI3) TWI Interrupt Enable Register */ -#define REG_TWI3_IDR (0x40018628U) /**< \brief (TWI3) TWI Interrupt Disable Register */ -#define REG_TWI3_IMR (0x4001862CU) /**< \brief (TWI3) TWI Interrupt Mask Register */ -#define REG_TWI3_RHR (0x40018630U) /**< \brief (TWI3) TWI Receive Holding Register */ -#define REG_TWI3_THR (0x40018634U) /**< \brief (TWI3) TWI Transmit Holding Register */ -#define REG_TWI3_SMBTR (0x40018638U) /**< \brief (TWI3) TWI SMBus Timing Register */ -#define REG_TWI3_ACR (0x40018640U) /**< \brief (TWI3) TWI Alternative Command Register */ -#define REG_TWI3_FILTR (0x40018644U) /**< \brief (TWI3) TWI Filter Register */ -#define REG_TWI3_SWMR (0x4001864CU) /**< \brief (TWI3) TWI SleepWalking Matching Register */ -#define REG_TWI3_WPMR (0x400186E4U) /**< \brief (TWI3) TWI Write Protection Mode Register */ -#define REG_TWI3_WPSR (0x400186E8U) /**< \brief (TWI3) TWI Write Protection Status Register */ -#define REG_TWI3_RPR (0x40018700U) /**< \brief (TWI3) Receive Pointer Register */ -#define REG_TWI3_RCR (0x40018704U) /**< \brief (TWI3) Receive Counter Register */ -#define REG_TWI3_TPR (0x40018708U) /**< \brief (TWI3) Transmit Pointer Register */ -#define REG_TWI3_TCR (0x4001870CU) /**< \brief (TWI3) Transmit Counter Register */ -#define REG_TWI3_RNPR (0x40018710U) /**< \brief (TWI3) Receive Next Pointer Register */ -#define REG_TWI3_RNCR (0x40018714U) /**< \brief (TWI3) Receive Next Counter Register */ -#define REG_TWI3_TNPR (0x40018718U) /**< \brief (TWI3) Transmit Next Pointer Register */ -#define REG_TWI3_TNCR (0x4001871CU) /**< \brief (TWI3) Transmit Next Counter Register */ -#define REG_TWI3_PTCR (0x40018720U) /**< \brief (TWI3) Transfer Control Register */ -#define REG_TWI3_PTSR (0x40018724U) /**< \brief (TWI3) Transfer Status Register */ -#else -#define REG_TWI3_CR (*(__O uint32_t*)0x40018600U) /**< \brief (TWI3) TWI Control Register */ -#define REG_TWI3_MMR (*(__IO uint32_t*)0x40018604U) /**< \brief (TWI3) TWI Master Mode Register */ -#define REG_TWI3_SMR (*(__IO uint32_t*)0x40018608U) /**< \brief (TWI3) TWI Slave Mode Register */ -#define REG_TWI3_IADR (*(__IO uint32_t*)0x4001860CU) /**< \brief (TWI3) TWI Internal Address Register */ -#define REG_TWI3_CWGR (*(__IO uint32_t*)0x40018610U) /**< \brief (TWI3) TWI Clock Waveform Generator Register */ -#define REG_TWI3_SR (*(__I uint32_t*)0x40018620U) /**< \brief (TWI3) TWI Status Register */ -#define REG_TWI3_IER (*(__O uint32_t*)0x40018624U) /**< \brief (TWI3) TWI Interrupt Enable Register */ -#define REG_TWI3_IDR (*(__O uint32_t*)0x40018628U) /**< \brief (TWI3) TWI Interrupt Disable Register */ -#define REG_TWI3_IMR (*(__I uint32_t*)0x4001862CU) /**< \brief (TWI3) TWI Interrupt Mask Register */ -#define REG_TWI3_RHR (*(__I uint32_t*)0x40018630U) /**< \brief (TWI3) TWI Receive Holding Register */ -#define REG_TWI3_THR (*(__O uint32_t*)0x40018634U) /**< \brief (TWI3) TWI Transmit Holding Register */ -#define REG_TWI3_SMBTR (*(__IO uint32_t*)0x40018638U) /**< \brief (TWI3) TWI SMBus Timing Register */ -#define REG_TWI3_ACR (*(__IO uint32_t*)0x40018640U) /**< \brief (TWI3) TWI Alternative Command Register */ -#define REG_TWI3_FILTR (*(__IO uint32_t*)0x40018644U) /**< \brief (TWI3) TWI Filter Register */ -#define REG_TWI3_SWMR (*(__IO uint32_t*)0x4001864CU) /**< \brief (TWI3) TWI SleepWalking Matching Register */ -#define REG_TWI3_WPMR (*(__IO uint32_t*)0x400186E4U) /**< \brief (TWI3) TWI Write Protection Mode Register */ -#define REG_TWI3_WPSR (*(__I uint32_t*)0x400186E8U) /**< \brief (TWI3) TWI Write Protection Status Register */ -#define REG_TWI3_RPR (*(__IO uint32_t*)0x40018700U) /**< \brief (TWI3) Receive Pointer Register */ -#define REG_TWI3_RCR (*(__IO uint32_t*)0x40018704U) /**< \brief (TWI3) Receive Counter Register */ -#define REG_TWI3_TPR (*(__IO uint32_t*)0x40018708U) /**< \brief (TWI3) Transmit Pointer Register */ -#define REG_TWI3_TCR (*(__IO uint32_t*)0x4001870CU) /**< \brief (TWI3) Transmit Counter Register */ -#define REG_TWI3_RNPR (*(__IO uint32_t*)0x40018710U) /**< \brief (TWI3) Receive Next Pointer Register */ -#define REG_TWI3_RNCR (*(__IO uint32_t*)0x40018714U) /**< \brief (TWI3) Receive Next Counter Register */ -#define REG_TWI3_TNPR (*(__IO uint32_t*)0x40018718U) /**< \brief (TWI3) Transmit Next Pointer Register */ -#define REG_TWI3_TNCR (*(__IO uint32_t*)0x4001871CU) /**< \brief (TWI3) Transmit Next Counter Register */ -#define REG_TWI3_PTCR (*(__O uint32_t*)0x40018720U) /**< \brief (TWI3) Transfer Control Register */ -#define REG_TWI3_PTSR (*(__I uint32_t*)0x40018724U) /**< \brief (TWI3) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TWI3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi4.h deleted file mode 100644 index 34c825fb429..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi4.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI4_INSTANCE_ -#define _SAMG55_TWI4_INSTANCE_ - -/* ========== Register definition for TWI4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI4_CR (0x4001C600U) /**< \brief (TWI4) TWI Control Register */ -#define REG_TWI4_MMR (0x4001C604U) /**< \brief (TWI4) TWI Master Mode Register */ -#define REG_TWI4_SMR (0x4001C608U) /**< \brief (TWI4) TWI Slave Mode Register */ -#define REG_TWI4_IADR (0x4001C60CU) /**< \brief (TWI4) TWI Internal Address Register */ -#define REG_TWI4_CWGR (0x4001C610U) /**< \brief (TWI4) TWI Clock Waveform Generator Register */ -#define REG_TWI4_SR (0x4001C620U) /**< \brief (TWI4) TWI Status Register */ -#define REG_TWI4_IER (0x4001C624U) /**< \brief (TWI4) TWI Interrupt Enable Register */ -#define REG_TWI4_IDR (0x4001C628U) /**< \brief (TWI4) TWI Interrupt Disable Register */ -#define REG_TWI4_IMR (0x4001C62CU) /**< \brief (TWI4) TWI Interrupt Mask Register */ -#define REG_TWI4_RHR (0x4001C630U) /**< \brief (TWI4) TWI Receive Holding Register */ -#define REG_TWI4_THR (0x4001C634U) /**< \brief (TWI4) TWI Transmit Holding Register */ -#define REG_TWI4_SMBTR (0x4001C638U) /**< \brief (TWI4) TWI SMBus Timing Register */ -#define REG_TWI4_ACR (0x4001C640U) /**< \brief (TWI4) TWI Alternative Command Register */ -#define REG_TWI4_FILTR (0x4001C644U) /**< \brief (TWI4) TWI Filter Register */ -#define REG_TWI4_SWMR (0x4001C64CU) /**< \brief (TWI4) TWI SleepWalking Matching Register */ -#define REG_TWI4_WPMR (0x4001C6E4U) /**< \brief (TWI4) TWI Write Protection Mode Register */ -#define REG_TWI4_WPSR (0x4001C6E8U) /**< \brief (TWI4) TWI Write Protection Status Register */ -#define REG_TWI4_RPR (0x4001C700U) /**< \brief (TWI4) Receive Pointer Register */ -#define REG_TWI4_RCR (0x4001C704U) /**< \brief (TWI4) Receive Counter Register */ -#define REG_TWI4_TPR (0x4001C708U) /**< \brief (TWI4) Transmit Pointer Register */ -#define REG_TWI4_TCR (0x4001C70CU) /**< \brief (TWI4) Transmit Counter Register */ -#define REG_TWI4_RNPR (0x4001C710U) /**< \brief (TWI4) Receive Next Pointer Register */ -#define REG_TWI4_RNCR (0x4001C714U) /**< \brief (TWI4) Receive Next Counter Register */ -#define REG_TWI4_TNPR (0x4001C718U) /**< \brief (TWI4) Transmit Next Pointer Register */ -#define REG_TWI4_TNCR (0x4001C71CU) /**< \brief (TWI4) Transmit Next Counter Register */ -#define REG_TWI4_PTCR (0x4001C720U) /**< \brief (TWI4) Transfer Control Register */ -#define REG_TWI4_PTSR (0x4001C724U) /**< \brief (TWI4) Transfer Status Register */ -#else -#define REG_TWI4_CR (*(__O uint32_t*)0x4001C600U) /**< \brief (TWI4) TWI Control Register */ -#define REG_TWI4_MMR (*(__IO uint32_t*)0x4001C604U) /**< \brief (TWI4) TWI Master Mode Register */ -#define REG_TWI4_SMR (*(__IO uint32_t*)0x4001C608U) /**< \brief (TWI4) TWI Slave Mode Register */ -#define REG_TWI4_IADR (*(__IO uint32_t*)0x4001C60CU) /**< \brief (TWI4) TWI Internal Address Register */ -#define REG_TWI4_CWGR (*(__IO uint32_t*)0x4001C610U) /**< \brief (TWI4) TWI Clock Waveform Generator Register */ -#define REG_TWI4_SR (*(__I uint32_t*)0x4001C620U) /**< \brief (TWI4) TWI Status Register */ -#define REG_TWI4_IER (*(__O uint32_t*)0x4001C624U) /**< \brief (TWI4) TWI Interrupt Enable Register */ -#define REG_TWI4_IDR (*(__O uint32_t*)0x4001C628U) /**< \brief (TWI4) TWI Interrupt Disable Register */ -#define REG_TWI4_IMR (*(__I uint32_t*)0x4001C62CU) /**< \brief (TWI4) TWI Interrupt Mask Register */ -#define REG_TWI4_RHR (*(__I uint32_t*)0x4001C630U) /**< \brief (TWI4) TWI Receive Holding Register */ -#define REG_TWI4_THR (*(__O uint32_t*)0x4001C634U) /**< \brief (TWI4) TWI Transmit Holding Register */ -#define REG_TWI4_SMBTR (*(__IO uint32_t*)0x4001C638U) /**< \brief (TWI4) TWI SMBus Timing Register */ -#define REG_TWI4_ACR (*(__IO uint32_t*)0x4001C640U) /**< \brief (TWI4) TWI Alternative Command Register */ -#define REG_TWI4_FILTR (*(__IO uint32_t*)0x4001C644U) /**< \brief (TWI4) TWI Filter Register */ -#define REG_TWI4_SWMR (*(__IO uint32_t*)0x4001C64CU) /**< \brief (TWI4) TWI SleepWalking Matching Register */ -#define REG_TWI4_WPMR (*(__IO uint32_t*)0x4001C6E4U) /**< \brief (TWI4) TWI Write Protection Mode Register */ -#define REG_TWI4_WPSR (*(__I uint32_t*)0x4001C6E8U) /**< \brief (TWI4) TWI Write Protection Status Register */ -#define REG_TWI4_RPR (*(__IO uint32_t*)0x4001C700U) /**< \brief (TWI4) Receive Pointer Register */ -#define REG_TWI4_RCR (*(__IO uint32_t*)0x4001C704U) /**< \brief (TWI4) Receive Counter Register */ -#define REG_TWI4_TPR (*(__IO uint32_t*)0x4001C708U) /**< \brief (TWI4) Transmit Pointer Register */ -#define REG_TWI4_TCR (*(__IO uint32_t*)0x4001C70CU) /**< \brief (TWI4) Transmit Counter Register */ -#define REG_TWI4_RNPR (*(__IO uint32_t*)0x4001C710U) /**< \brief (TWI4) Receive Next Pointer Register */ -#define REG_TWI4_RNCR (*(__IO uint32_t*)0x4001C714U) /**< \brief (TWI4) Receive Next Counter Register */ -#define REG_TWI4_TNPR (*(__IO uint32_t*)0x4001C718U) /**< \brief (TWI4) Transmit Next Pointer Register */ -#define REG_TWI4_TNCR (*(__IO uint32_t*)0x4001C71CU) /**< \brief (TWI4) Transmit Next Counter Register */ -#define REG_TWI4_PTCR (*(__O uint32_t*)0x4001C720U) /**< \brief (TWI4) Transfer Control Register */ -#define REG_TWI4_PTSR (*(__I uint32_t*)0x4001C724U) /**< \brief (TWI4) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TWI4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi5.h deleted file mode 100644 index fee6f5d5d98..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi5.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI5_INSTANCE_ -#define _SAMG55_TWI5_INSTANCE_ - -/* ========== Register definition for TWI5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI5_CR (0x40008600U) /**< \brief (TWI5) TWI Control Register */ -#define REG_TWI5_MMR (0x40008604U) /**< \brief (TWI5) TWI Master Mode Register */ -#define REG_TWI5_SMR (0x40008608U) /**< \brief (TWI5) TWI Slave Mode Register */ -#define REG_TWI5_IADR (0x4000860CU) /**< \brief (TWI5) TWI Internal Address Register */ -#define REG_TWI5_CWGR (0x40008610U) /**< \brief (TWI5) TWI Clock Waveform Generator Register */ -#define REG_TWI5_SR (0x40008620U) /**< \brief (TWI5) TWI Status Register */ -#define REG_TWI5_IER (0x40008624U) /**< \brief (TWI5) TWI Interrupt Enable Register */ -#define REG_TWI5_IDR (0x40008628U) /**< \brief (TWI5) TWI Interrupt Disable Register */ -#define REG_TWI5_IMR (0x4000862CU) /**< \brief (TWI5) TWI Interrupt Mask Register */ -#define REG_TWI5_RHR (0x40008630U) /**< \brief (TWI5) TWI Receive Holding Register */ -#define REG_TWI5_THR (0x40008634U) /**< \brief (TWI5) TWI Transmit Holding Register */ -#define REG_TWI5_SMBTR (0x40008638U) /**< \brief (TWI5) TWI SMBus Timing Register */ -#define REG_TWI5_ACR (0x40008640U) /**< \brief (TWI5) TWI Alternative Command Register */ -#define REG_TWI5_FILTR (0x40008644U) /**< \brief (TWI5) TWI Filter Register */ -#define REG_TWI5_SWMR (0x4000864CU) /**< \brief (TWI5) TWI SleepWalking Matching Register */ -#define REG_TWI5_WPMR (0x400086E4U) /**< \brief (TWI5) TWI Write Protection Mode Register */ -#define REG_TWI5_WPSR (0x400086E8U) /**< \brief (TWI5) TWI Write Protection Status Register */ -#define REG_TWI5_RPR (0x40008700U) /**< \brief (TWI5) Receive Pointer Register */ -#define REG_TWI5_RCR (0x40008704U) /**< \brief (TWI5) Receive Counter Register */ -#define REG_TWI5_TPR (0x40008708U) /**< \brief (TWI5) Transmit Pointer Register */ -#define REG_TWI5_TCR (0x4000870CU) /**< \brief (TWI5) Transmit Counter Register */ -#define REG_TWI5_RNPR (0x40008710U) /**< \brief (TWI5) Receive Next Pointer Register */ -#define REG_TWI5_RNCR (0x40008714U) /**< \brief (TWI5) Receive Next Counter Register */ -#define REG_TWI5_TNPR (0x40008718U) /**< \brief (TWI5) Transmit Next Pointer Register */ -#define REG_TWI5_TNCR (0x4000871CU) /**< \brief (TWI5) Transmit Next Counter Register */ -#define REG_TWI5_PTCR (0x40008720U) /**< \brief (TWI5) Transfer Control Register */ -#define REG_TWI5_PTSR (0x40008724U) /**< \brief (TWI5) Transfer Status Register */ -#else -#define REG_TWI5_CR (*(__O uint32_t*)0x40008600U) /**< \brief (TWI5) TWI Control Register */ -#define REG_TWI5_MMR (*(__IO uint32_t*)0x40008604U) /**< \brief (TWI5) TWI Master Mode Register */ -#define REG_TWI5_SMR (*(__IO uint32_t*)0x40008608U) /**< \brief (TWI5) TWI Slave Mode Register */ -#define REG_TWI5_IADR (*(__IO uint32_t*)0x4000860CU) /**< \brief (TWI5) TWI Internal Address Register */ -#define REG_TWI5_CWGR (*(__IO uint32_t*)0x40008610U) /**< \brief (TWI5) TWI Clock Waveform Generator Register */ -#define REG_TWI5_SR (*(__I uint32_t*)0x40008620U) /**< \brief (TWI5) TWI Status Register */ -#define REG_TWI5_IER (*(__O uint32_t*)0x40008624U) /**< \brief (TWI5) TWI Interrupt Enable Register */ -#define REG_TWI5_IDR (*(__O uint32_t*)0x40008628U) /**< \brief (TWI5) TWI Interrupt Disable Register */ -#define REG_TWI5_IMR (*(__I uint32_t*)0x4000862CU) /**< \brief (TWI5) TWI Interrupt Mask Register */ -#define REG_TWI5_RHR (*(__I uint32_t*)0x40008630U) /**< \brief (TWI5) TWI Receive Holding Register */ -#define REG_TWI5_THR (*(__O uint32_t*)0x40008634U) /**< \brief (TWI5) TWI Transmit Holding Register */ -#define REG_TWI5_SMBTR (*(__IO uint32_t*)0x40008638U) /**< \brief (TWI5) TWI SMBus Timing Register */ -#define REG_TWI5_ACR (*(__IO uint32_t*)0x40008640U) /**< \brief (TWI5) TWI Alternative Command Register */ -#define REG_TWI5_FILTR (*(__IO uint32_t*)0x40008644U) /**< \brief (TWI5) TWI Filter Register */ -#define REG_TWI5_SWMR (*(__IO uint32_t*)0x4000864CU) /**< \brief (TWI5) TWI SleepWalking Matching Register */ -#define REG_TWI5_WPMR (*(__IO uint32_t*)0x400086E4U) /**< \brief (TWI5) TWI Write Protection Mode Register */ -#define REG_TWI5_WPSR (*(__I uint32_t*)0x400086E8U) /**< \brief (TWI5) TWI Write Protection Status Register */ -#define REG_TWI5_RPR (*(__IO uint32_t*)0x40008700U) /**< \brief (TWI5) Receive Pointer Register */ -#define REG_TWI5_RCR (*(__IO uint32_t*)0x40008704U) /**< \brief (TWI5) Receive Counter Register */ -#define REG_TWI5_TPR (*(__IO uint32_t*)0x40008708U) /**< \brief (TWI5) Transmit Pointer Register */ -#define REG_TWI5_TCR (*(__IO uint32_t*)0x4000870CU) /**< \brief (TWI5) Transmit Counter Register */ -#define REG_TWI5_RNPR (*(__IO uint32_t*)0x40008710U) /**< \brief (TWI5) Receive Next Pointer Register */ -#define REG_TWI5_RNCR (*(__IO uint32_t*)0x40008714U) /**< \brief (TWI5) Receive Next Counter Register */ -#define REG_TWI5_TNPR (*(__IO uint32_t*)0x40008718U) /**< \brief (TWI5) Transmit Next Pointer Register */ -#define REG_TWI5_TNCR (*(__IO uint32_t*)0x4000871CU) /**< \brief (TWI5) Transmit Next Counter Register */ -#define REG_TWI5_PTCR (*(__O uint32_t*)0x40008720U) /**< \brief (TWI5) Transfer Control Register */ -#define REG_TWI5_PTSR (*(__I uint32_t*)0x40008724U) /**< \brief (TWI5) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TWI5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi6.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi6.h deleted file mode 100644 index 0d21f83c6c9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi6.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI6_INSTANCE_ -#define _SAMG55_TWI6_INSTANCE_ - -/* ========== Register definition for TWI6 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI6_CR (0x40040600U) /**< \brief (TWI6) TWI Control Register */ -#define REG_TWI6_MMR (0x40040604U) /**< \brief (TWI6) TWI Master Mode Register */ -#define REG_TWI6_SMR (0x40040608U) /**< \brief (TWI6) TWI Slave Mode Register */ -#define REG_TWI6_IADR (0x4004060CU) /**< \brief (TWI6) TWI Internal Address Register */ -#define REG_TWI6_CWGR (0x40040610U) /**< \brief (TWI6) TWI Clock Waveform Generator Register */ -#define REG_TWI6_SR (0x40040620U) /**< \brief (TWI6) TWI Status Register */ -#define REG_TWI6_IER (0x40040624U) /**< \brief (TWI6) TWI Interrupt Enable Register */ -#define REG_TWI6_IDR (0x40040628U) /**< \brief (TWI6) TWI Interrupt Disable Register */ -#define REG_TWI6_IMR (0x4004062CU) /**< \brief (TWI6) TWI Interrupt Mask Register */ -#define REG_TWI6_RHR (0x40040630U) /**< \brief (TWI6) TWI Receive Holding Register */ -#define REG_TWI6_THR (0x40040634U) /**< \brief (TWI6) TWI Transmit Holding Register */ -#define REG_TWI6_SMBTR (0x40040638U) /**< \brief (TWI6) TWI SMBus Timing Register */ -#define REG_TWI6_ACR (0x40040640U) /**< \brief (TWI6) TWI Alternative Command Register */ -#define REG_TWI6_FILTR (0x40040644U) /**< \brief (TWI6) TWI Filter Register */ -#define REG_TWI6_SWMR (0x4004064CU) /**< \brief (TWI6) TWI SleepWalking Matching Register */ -#define REG_TWI6_WPMR (0x400406E4U) /**< \brief (TWI6) TWI Write Protection Mode Register */ -#define REG_TWI6_WPSR (0x400406E8U) /**< \brief (TWI6) TWI Write Protection Status Register */ -#define REG_TWI6_RPR (0x40040700U) /**< \brief (TWI6) Receive Pointer Register */ -#define REG_TWI6_RCR (0x40040704U) /**< \brief (TWI6) Receive Counter Register */ -#define REG_TWI6_TPR (0x40040708U) /**< \brief (TWI6) Transmit Pointer Register */ -#define REG_TWI6_TCR (0x4004070CU) /**< \brief (TWI6) Transmit Counter Register */ -#define REG_TWI6_RNPR (0x40040710U) /**< \brief (TWI6) Receive Next Pointer Register */ -#define REG_TWI6_RNCR (0x40040714U) /**< \brief (TWI6) Receive Next Counter Register */ -#define REG_TWI6_TNPR (0x40040718U) /**< \brief (TWI6) Transmit Next Pointer Register */ -#define REG_TWI6_TNCR (0x4004071CU) /**< \brief (TWI6) Transmit Next Counter Register */ -#define REG_TWI6_PTCR (0x40040720U) /**< \brief (TWI6) Transfer Control Register */ -#define REG_TWI6_PTSR (0x40040724U) /**< \brief (TWI6) Transfer Status Register */ -#else -#define REG_TWI6_CR (*(__O uint32_t*)0x40040600U) /**< \brief (TWI6) TWI Control Register */ -#define REG_TWI6_MMR (*(__IO uint32_t*)0x40040604U) /**< \brief (TWI6) TWI Master Mode Register */ -#define REG_TWI6_SMR (*(__IO uint32_t*)0x40040608U) /**< \brief (TWI6) TWI Slave Mode Register */ -#define REG_TWI6_IADR (*(__IO uint32_t*)0x4004060CU) /**< \brief (TWI6) TWI Internal Address Register */ -#define REG_TWI6_CWGR (*(__IO uint32_t*)0x40040610U) /**< \brief (TWI6) TWI Clock Waveform Generator Register */ -#define REG_TWI6_SR (*(__I uint32_t*)0x40040620U) /**< \brief (TWI6) TWI Status Register */ -#define REG_TWI6_IER (*(__O uint32_t*)0x40040624U) /**< \brief (TWI6) TWI Interrupt Enable Register */ -#define REG_TWI6_IDR (*(__O uint32_t*)0x40040628U) /**< \brief (TWI6) TWI Interrupt Disable Register */ -#define REG_TWI6_IMR (*(__I uint32_t*)0x4004062CU) /**< \brief (TWI6) TWI Interrupt Mask Register */ -#define REG_TWI6_RHR (*(__I uint32_t*)0x40040630U) /**< \brief (TWI6) TWI Receive Holding Register */ -#define REG_TWI6_THR (*(__O uint32_t*)0x40040634U) /**< \brief (TWI6) TWI Transmit Holding Register */ -#define REG_TWI6_SMBTR (*(__IO uint32_t*)0x40040638U) /**< \brief (TWI6) TWI SMBus Timing Register */ -#define REG_TWI6_ACR (*(__IO uint32_t*)0x40040640U) /**< \brief (TWI6) TWI Alternative Command Register */ -#define REG_TWI6_FILTR (*(__IO uint32_t*)0x40040644U) /**< \brief (TWI6) TWI Filter Register */ -#define REG_TWI6_SWMR (*(__IO uint32_t*)0x4004064CU) /**< \brief (TWI6) TWI SleepWalking Matching Register */ -#define REG_TWI6_WPMR (*(__IO uint32_t*)0x400406E4U) /**< \brief (TWI6) TWI Write Protection Mode Register */ -#define REG_TWI6_WPSR (*(__I uint32_t*)0x400406E8U) /**< \brief (TWI6) TWI Write Protection Status Register */ -#define REG_TWI6_RPR (*(__IO uint32_t*)0x40040700U) /**< \brief (TWI6) Receive Pointer Register */ -#define REG_TWI6_RCR (*(__IO uint32_t*)0x40040704U) /**< \brief (TWI6) Receive Counter Register */ -#define REG_TWI6_TPR (*(__IO uint32_t*)0x40040708U) /**< \brief (TWI6) Transmit Pointer Register */ -#define REG_TWI6_TCR (*(__IO uint32_t*)0x4004070CU) /**< \brief (TWI6) Transmit Counter Register */ -#define REG_TWI6_RNPR (*(__IO uint32_t*)0x40040710U) /**< \brief (TWI6) Receive Next Pointer Register */ -#define REG_TWI6_RNCR (*(__IO uint32_t*)0x40040714U) /**< \brief (TWI6) Receive Next Counter Register */ -#define REG_TWI6_TNPR (*(__IO uint32_t*)0x40040718U) /**< \brief (TWI6) Transmit Next Pointer Register */ -#define REG_TWI6_TNCR (*(__IO uint32_t*)0x4004071CU) /**< \brief (TWI6) Transmit Next Counter Register */ -#define REG_TWI6_PTCR (*(__O uint32_t*)0x40040720U) /**< \brief (TWI6) Transfer Control Register */ -#define REG_TWI6_PTSR (*(__I uint32_t*)0x40040724U) /**< \brief (TWI6) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TWI6_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi7.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi7.h deleted file mode 100644 index 208a32375d9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi7.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_TWI7_INSTANCE_ -#define _SAMG55_TWI7_INSTANCE_ - -/* ========== Register definition for TWI7 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI7_CR (0x40034600U) /**< \brief (TWI7) TWI Control Register */ -#define REG_TWI7_MMR (0x40034604U) /**< \brief (TWI7) TWI Master Mode Register */ -#define REG_TWI7_SMR (0x40034608U) /**< \brief (TWI7) TWI Slave Mode Register */ -#define REG_TWI7_IADR (0x4003460CU) /**< \brief (TWI7) TWI Internal Address Register */ -#define REG_TWI7_CWGR (0x40034610U) /**< \brief (TWI7) TWI Clock Waveform Generator Register */ -#define REG_TWI7_SR (0x40034620U) /**< \brief (TWI7) TWI Status Register */ -#define REG_TWI7_IER (0x40034624U) /**< \brief (TWI7) TWI Interrupt Enable Register */ -#define REG_TWI7_IDR (0x40034628U) /**< \brief (TWI7) TWI Interrupt Disable Register */ -#define REG_TWI7_IMR (0x4003462CU) /**< \brief (TWI7) TWI Interrupt Mask Register */ -#define REG_TWI7_RHR (0x40034630U) /**< \brief (TWI7) TWI Receive Holding Register */ -#define REG_TWI7_THR (0x40034634U) /**< \brief (TWI7) TWI Transmit Holding Register */ -#define REG_TWI7_SMBTR (0x40034638U) /**< \brief (TWI7) TWI SMBus Timing Register */ -#define REG_TWI7_ACR (0x40034640U) /**< \brief (TWI7) TWI Alternative Command Register */ -#define REG_TWI7_FILTR (0x40034644U) /**< \brief (TWI7) TWI Filter Register */ -#define REG_TWI7_SWMR (0x4003464CU) /**< \brief (TWI7) TWI SleepWalking Matching Register */ -#define REG_TWI7_WPMR (0x400346E4U) /**< \brief (TWI7) TWI Write Protection Mode Register */ -#define REG_TWI7_WPSR (0x400346E8U) /**< \brief (TWI7) TWI Write Protection Status Register */ -#define REG_TWI7_RPR (0x40034700U) /**< \brief (TWI7) Receive Pointer Register */ -#define REG_TWI7_RCR (0x40034704U) /**< \brief (TWI7) Receive Counter Register */ -#define REG_TWI7_TPR (0x40034708U) /**< \brief (TWI7) Transmit Pointer Register */ -#define REG_TWI7_TCR (0x4003470CU) /**< \brief (TWI7) Transmit Counter Register */ -#define REG_TWI7_RNPR (0x40034710U) /**< \brief (TWI7) Receive Next Pointer Register */ -#define REG_TWI7_RNCR (0x40034714U) /**< \brief (TWI7) Receive Next Counter Register */ -#define REG_TWI7_TNPR (0x40034718U) /**< \brief (TWI7) Transmit Next Pointer Register */ -#define REG_TWI7_TNCR (0x4003471CU) /**< \brief (TWI7) Transmit Next Counter Register */ -#define REG_TWI7_PTCR (0x40034720U) /**< \brief (TWI7) Transfer Control Register */ -#define REG_TWI7_PTSR (0x40034724U) /**< \brief (TWI7) Transfer Status Register */ -#else -#define REG_TWI7_CR (*(__O uint32_t*)0x40034600U) /**< \brief (TWI7) TWI Control Register */ -#define REG_TWI7_MMR (*(__IO uint32_t*)0x40034604U) /**< \brief (TWI7) TWI Master Mode Register */ -#define REG_TWI7_SMR (*(__IO uint32_t*)0x40034608U) /**< \brief (TWI7) TWI Slave Mode Register */ -#define REG_TWI7_IADR (*(__IO uint32_t*)0x4003460CU) /**< \brief (TWI7) TWI Internal Address Register */ -#define REG_TWI7_CWGR (*(__IO uint32_t*)0x40034610U) /**< \brief (TWI7) TWI Clock Waveform Generator Register */ -#define REG_TWI7_SR (*(__I uint32_t*)0x40034620U) /**< \brief (TWI7) TWI Status Register */ -#define REG_TWI7_IER (*(__O uint32_t*)0x40034624U) /**< \brief (TWI7) TWI Interrupt Enable Register */ -#define REG_TWI7_IDR (*(__O uint32_t*)0x40034628U) /**< \brief (TWI7) TWI Interrupt Disable Register */ -#define REG_TWI7_IMR (*(__I uint32_t*)0x4003462CU) /**< \brief (TWI7) TWI Interrupt Mask Register */ -#define REG_TWI7_RHR (*(__I uint32_t*)0x40034630U) /**< \brief (TWI7) TWI Receive Holding Register */ -#define REG_TWI7_THR (*(__O uint32_t*)0x40034634U) /**< \brief (TWI7) TWI Transmit Holding Register */ -#define REG_TWI7_SMBTR (*(__IO uint32_t*)0x40034638U) /**< \brief (TWI7) TWI SMBus Timing Register */ -#define REG_TWI7_ACR (*(__IO uint32_t*)0x40034640U) /**< \brief (TWI7) TWI Alternative Command Register */ -#define REG_TWI7_FILTR (*(__IO uint32_t*)0x40034644U) /**< \brief (TWI7) TWI Filter Register */ -#define REG_TWI7_SWMR (*(__IO uint32_t*)0x4003464CU) /**< \brief (TWI7) TWI SleepWalking Matching Register */ -#define REG_TWI7_WPMR (*(__IO uint32_t*)0x400346E4U) /**< \brief (TWI7) TWI Write Protection Mode Register */ -#define REG_TWI7_WPSR (*(__I uint32_t*)0x400346E8U) /**< \brief (TWI7) TWI Write Protection Status Register */ -#define REG_TWI7_RPR (*(__IO uint32_t*)0x40034700U) /**< \brief (TWI7) Receive Pointer Register */ -#define REG_TWI7_RCR (*(__IO uint32_t*)0x40034704U) /**< \brief (TWI7) Receive Counter Register */ -#define REG_TWI7_TPR (*(__IO uint32_t*)0x40034708U) /**< \brief (TWI7) Transmit Pointer Register */ -#define REG_TWI7_TCR (*(__IO uint32_t*)0x4003470CU) /**< \brief (TWI7) Transmit Counter Register */ -#define REG_TWI7_RNPR (*(__IO uint32_t*)0x40034710U) /**< \brief (TWI7) Receive Next Pointer Register */ -#define REG_TWI7_RNCR (*(__IO uint32_t*)0x40034714U) /**< \brief (TWI7) Receive Next Counter Register */ -#define REG_TWI7_TNPR (*(__IO uint32_t*)0x40034718U) /**< \brief (TWI7) Transmit Next Pointer Register */ -#define REG_TWI7_TNCR (*(__IO uint32_t*)0x4003471CU) /**< \brief (TWI7) Transmit Next Counter Register */ -#define REG_TWI7_PTCR (*(__O uint32_t*)0x40034720U) /**< \brief (TWI7) Transfer Control Register */ -#define REG_TWI7_PTSR (*(__I uint32_t*)0x40034724U) /**< \brief (TWI7) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_TWI7_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_udp.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_udp.h deleted file mode 100644 index 9b809ef0e32..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_udp.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_UDP_INSTANCE_ -#define _SAMG55_UDP_INSTANCE_ - -/* ========== Register definition for UDP peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_UDP_FRM_NUM (0x40044000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT (0x40044004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR (0x40044008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER (0x40044010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR (0x40044014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR (0x40044018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR (0x4004401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR (0x40044020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP (0x40044028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR (0x40044030U) /**< \brief (UDP) Endpoint Control and Status Register */ -#define REG_UDP_FDR (0x40044050U) /**< \brief (UDP) Endpoint FIFO Data Register */ -#define REG_UDP_TXVC (0x40044074U) /**< \brief (UDP) Transceiver Control Register */ -#else -#define REG_UDP_FRM_NUM (*(__I uint32_t*)0x40044000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT (*(__IO uint32_t*)0x40044004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR (*(__IO uint32_t*)0x40044008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER (*(__O uint32_t*)0x40044010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR (*(__O uint32_t*)0x40044014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR (*(__I uint32_t*)0x40044018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR (*(__I uint32_t*)0x4004401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR (*(__O uint32_t*)0x40044020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP (*(__IO uint32_t*)0x40044028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR (*(__IO uint32_t*)0x40044030U) /**< \brief (UDP) Endpoint Control and Status Register */ -#define REG_UDP_FDR (*(__IO uint32_t*)0x40044050U) /**< \brief (UDP) Endpoint FIFO Data Register */ -#define REG_UDP_TXVC (*(__IO uint32_t*)0x40044074U) /**< \brief (UDP) Transceiver Control Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_UDP_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_uhp.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_uhp.h deleted file mode 100644 index d96dc88ef4a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_uhp.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_UHP_INSTANCE_ -#define _SAMG55_UHP_INSTANCE_ - -/* ========== Register definition for UHP peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_UHP_HCREVISION (0x4004C000U) /**< \brief (UHP) OHCI Revision Number Register */ -#define REG_UHP_HCCONTROL (0x4004C004U) /**< \brief (UHP) HC Operating Mode Register */ -#define REG_UHP_HCCOMMANDSTATUS (0x4004C008U) /**< \brief (UHP) HC Command and Status Register */ -#define REG_UHP_HCINTERRUPTSTATUS (0x4004C00CU) /**< \brief (UHP) HC Interrupt and Status Register */ -#define REG_UHP_HCINTERRUPTENABLE (0x4004C010U) /**< \brief (UHP) HC Interrupt Enable Register */ -#define REG_UHP_HCINTERRUPTDISABLE (0x4004C014U) /**< \brief (UHP) HC Interrupt Disable Register */ -#define REG_UHP_HCHCCA (0x4004C018U) /**< \brief (UHP) HC HCCA Address Register */ -#define REG_UHP_HCPERIODCURRENTED (0x4004C01CU) /**< \brief (UHP) HC Current Periodic Register */ -#define REG_UHP_HCCONTROLHEADED (0x4004C020U) /**< \brief (UHP) HC Head Control Register */ -#define REG_UHP_HCCONTROLCURRENTED (0x4004C024U) /**< \brief (UHP) HC Current Control Register */ -#define REG_UHP_HCBULKHEADED (0x4004C028U) /**< \brief (UHP) HC Head Bulk Register */ -#define REG_UHP_HCBULKCURRENTED (0x4004C02CU) /**< \brief (UHP) HC Current Bulk Register */ -#define REG_UHP_HCDONEHEAD (0x4004C030U) /**< \brief (UHP) HC Head Done Register */ -#define REG_UHP_HCFMINTERVAL (0x4004C034U) /**< \brief (UHP) HC Frame Interval Register */ -#define REG_UHP_HCFMREMAINING (0x4004C038U) /**< \brief (UHP) HC Frame Remaining Register */ -#define REG_UHP_HCFMNUMBER (0x4004C03CU) /**< \brief (UHP) HC Frame Number Register */ -#define REG_UHP_HCPERIODICSTART (0x4004C040U) /**< \brief (UHP) HC Periodic Start Register */ -#define REG_UHP_HCLSTHRESHOLD (0x4004C044U) /**< \brief (UHP) HC Low-Speed Threshold Register */ -#define REG_UHP_HCRHDESCRIPTORA (0x4004C048U) /**< \brief (UHP) HC Root Hub A Register */ -#define REG_UHP_HCRHDESCRIPTORB (0x4004C04CU) /**< \brief (UHP) HC Root Hub B Register */ -#define REG_UHP_HCRHSTATUS (0x4004C050U) /**< \brief (UHP) HC Root Hub Status Register */ -#define REG_UHP_HCRHPORTSTATUS (0x4004C054U) /**< \brief (UHP) HC Port 1 Status and Control Register */ -#else -#define REG_UHP_HCREVISION (*(__I uint32_t*)0x4004C000U) /**< \brief (UHP) OHCI Revision Number Register */ -#define REG_UHP_HCCONTROL (*(__IO uint32_t*)0x4004C004U) /**< \brief (UHP) HC Operating Mode Register */ -#define REG_UHP_HCCOMMANDSTATUS (*(__IO uint32_t*)0x4004C008U) /**< \brief (UHP) HC Command and Status Register */ -#define REG_UHP_HCINTERRUPTSTATUS (*(__IO uint32_t*)0x4004C00CU) /**< \brief (UHP) HC Interrupt and Status Register */ -#define REG_UHP_HCINTERRUPTENABLE (*(__IO uint32_t*)0x4004C010U) /**< \brief (UHP) HC Interrupt Enable Register */ -#define REG_UHP_HCINTERRUPTDISABLE (*(__IO uint32_t*)0x4004C014U) /**< \brief (UHP) HC Interrupt Disable Register */ -#define REG_UHP_HCHCCA (*(__IO uint32_t*)0x4004C018U) /**< \brief (UHP) HC HCCA Address Register */ -#define REG_UHP_HCPERIODCURRENTED (*(__I uint32_t*)0x4004C01CU) /**< \brief (UHP) HC Current Periodic Register */ -#define REG_UHP_HCCONTROLHEADED (*(__IO uint32_t*)0x4004C020U) /**< \brief (UHP) HC Head Control Register */ -#define REG_UHP_HCCONTROLCURRENTED (*(__IO uint32_t*)0x4004C024U) /**< \brief (UHP) HC Current Control Register */ -#define REG_UHP_HCBULKHEADED (*(__IO uint32_t*)0x4004C028U) /**< \brief (UHP) HC Head Bulk Register */ -#define REG_UHP_HCBULKCURRENTED (*(__IO uint32_t*)0x4004C02CU) /**< \brief (UHP) HC Current Bulk Register */ -#define REG_UHP_HCDONEHEAD (*(__I uint32_t*)0x4004C030U) /**< \brief (UHP) HC Head Done Register */ -#define REG_UHP_HCFMINTERVAL (*(__IO uint32_t*)0x4004C034U) /**< \brief (UHP) HC Frame Interval Register */ -#define REG_UHP_HCFMREMAINING (*(__I uint32_t*)0x4004C038U) /**< \brief (UHP) HC Frame Remaining Register */ -#define REG_UHP_HCFMNUMBER (*(__I uint32_t*)0x4004C03CU) /**< \brief (UHP) HC Frame Number Register */ -#define REG_UHP_HCPERIODICSTART (*(__IO uint32_t*)0x4004C040U) /**< \brief (UHP) HC Periodic Start Register */ -#define REG_UHP_HCLSTHRESHOLD (*(__IO uint32_t*)0x4004C044U) /**< \brief (UHP) HC Low-Speed Threshold Register */ -#define REG_UHP_HCRHDESCRIPTORA (*(__IO uint32_t*)0x4004C048U) /**< \brief (UHP) HC Root Hub A Register */ -#define REG_UHP_HCRHDESCRIPTORB (*(__IO uint32_t*)0x4004C04CU) /**< \brief (UHP) HC Root Hub B Register */ -#define REG_UHP_HCRHSTATUS (*(__IO uint32_t*)0x4004C050U) /**< \brief (UHP) HC Root Hub Status Register */ -#define REG_UHP_HCRHPORTSTATUS (*(__IO uint32_t*)0x4004C054U) /**< \brief (UHP) HC Port 1 Status and Control Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_UHP_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart0.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart0.h deleted file mode 100644 index 1ca5d272638..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart0.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART0_INSTANCE_ -#define _SAMG55_USART0_INSTANCE_ - -/* ========== Register definition for USART0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART0_CR (0x4000C200U) /**< \brief (USART0) USART Control Register */ -#define REG_USART0_MR (0x4000C204U) /**< \brief (USART0) USART Mode Register */ -#define REG_USART0_IER (0x4000C208U) /**< \brief (USART0) USART Interrupt Enable Register */ -#define REG_USART0_IDR (0x4000C20CU) /**< \brief (USART0) USART Interrupt Disable Register */ -#define REG_USART0_IMR (0x4000C210U) /**< \brief (USART0) USART Interrupt Mask Register */ -#define REG_USART0_CSR (0x4000C214U) /**< \brief (USART0) USART Channel Status Register */ -#define REG_USART0_RHR (0x4000C218U) /**< \brief (USART0) USART Receive Holding Register */ -#define REG_USART0_THR (0x4000C21CU) /**< \brief (USART0) USART Transmit Holding Register */ -#define REG_USART0_BRGR (0x4000C220U) /**< \brief (USART0) USART Baud Rate Generator Register */ -#define REG_USART0_RTOR (0x4000C224U) /**< \brief (USART0) USART Receiver Time-out Register */ -#define REG_USART0_TTGR (0x4000C228U) /**< \brief (USART0) USART Transmitter Timeguard Register */ -#define REG_USART0_FIDI (0x4000C240U) /**< \brief (USART0) USART FI DI Ratio Register */ -#define REG_USART0_NER (0x4000C244U) /**< \brief (USART0) USART Number of Errors Register */ -#define REG_USART0_LINMR (0x4000C254U) /**< \brief (USART0) USART LIN Mode Register */ -#define REG_USART0_LINIR (0x4000C258U) /**< \brief (USART0) USART LIN Identifier Register */ -#define REG_USART0_LINBRR (0x4000C25CU) /**< \brief (USART0) USART LIN Baud Rate Register */ -#define REG_USART0_CMPR (0x4000C290U) /**< \brief (USART0) USART Comparison Register */ -#define REG_USART0_WPMR (0x4000C2E4U) /**< \brief (USART0) USART Write Protection Mode Register */ -#define REG_USART0_WPSR (0x4000C2E8U) /**< \brief (USART0) USART Write Protection Status Register */ -#define REG_USART0_RPR (0x4000C300U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR (0x4000C304U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR (0x4000C308U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR (0x4000C30CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR (0x4000C310U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR (0x4000C314U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR (0x4000C318U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR (0x4000C31CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR (0x4000C320U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR (0x4000C324U) /**< \brief (USART0) Transfer Status Register */ -#else -#define REG_USART0_CR (*(__O uint32_t*)0x4000C200U) /**< \brief (USART0) USART Control Register */ -#define REG_USART0_MR (*(__IO uint32_t*)0x4000C204U) /**< \brief (USART0) USART Mode Register */ -#define REG_USART0_IER (*(__O uint32_t*)0x4000C208U) /**< \brief (USART0) USART Interrupt Enable Register */ -#define REG_USART0_IDR (*(__O uint32_t*)0x4000C20CU) /**< \brief (USART0) USART Interrupt Disable Register */ -#define REG_USART0_IMR (*(__I uint32_t*)0x4000C210U) /**< \brief (USART0) USART Interrupt Mask Register */ -#define REG_USART0_CSR (*(__I uint32_t*)0x4000C214U) /**< \brief (USART0) USART Channel Status Register */ -#define REG_USART0_RHR (*(__I uint32_t*)0x4000C218U) /**< \brief (USART0) USART Receive Holding Register */ -#define REG_USART0_THR (*(__O uint32_t*)0x4000C21CU) /**< \brief (USART0) USART Transmit Holding Register */ -#define REG_USART0_BRGR (*(__IO uint32_t*)0x4000C220U) /**< \brief (USART0) USART Baud Rate Generator Register */ -#define REG_USART0_RTOR (*(__IO uint32_t*)0x4000C224U) /**< \brief (USART0) USART Receiver Time-out Register */ -#define REG_USART0_TTGR (*(__IO uint32_t*)0x4000C228U) /**< \brief (USART0) USART Transmitter Timeguard Register */ -#define REG_USART0_FIDI (*(__IO uint32_t*)0x4000C240U) /**< \brief (USART0) USART FI DI Ratio Register */ -#define REG_USART0_NER (*(__I uint32_t*)0x4000C244U) /**< \brief (USART0) USART Number of Errors Register */ -#define REG_USART0_LINMR (*(__IO uint32_t*)0x4000C254U) /**< \brief (USART0) USART LIN Mode Register */ -#define REG_USART0_LINIR (*(__IO uint32_t*)0x4000C258U) /**< \brief (USART0) USART LIN Identifier Register */ -#define REG_USART0_LINBRR (*(__I uint32_t*)0x4000C25CU) /**< \brief (USART0) USART LIN Baud Rate Register */ -#define REG_USART0_CMPR (*(__IO uint32_t*)0x4000C290U) /**< \brief (USART0) USART Comparison Register */ -#define REG_USART0_WPMR (*(__IO uint32_t*)0x4000C2E4U) /**< \brief (USART0) USART Write Protection Mode Register */ -#define REG_USART0_WPSR (*(__I uint32_t*)0x4000C2E8U) /**< \brief (USART0) USART Write Protection Status Register */ -#define REG_USART0_RPR (*(__IO uint32_t*)0x4000C300U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR (*(__IO uint32_t*)0x4000C304U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR (*(__IO uint32_t*)0x4000C308U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR (*(__IO uint32_t*)0x4000C30CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR (*(__IO uint32_t*)0x4000C310U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR (*(__IO uint32_t*)0x4000C314U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR (*(__IO uint32_t*)0x4000C318U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR (*(__IO uint32_t*)0x4000C31CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR (*(__O uint32_t*)0x4000C320U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR (*(__I uint32_t*)0x4000C324U) /**< \brief (USART0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_USART0_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart1.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart1.h deleted file mode 100644 index e94233ba6bd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart1.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART1_INSTANCE_ -#define _SAMG55_USART1_INSTANCE_ - -/* ========== Register definition for USART1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART1_CR (0x40020200U) /**< \brief (USART1) USART Control Register */ -#define REG_USART1_MR (0x40020204U) /**< \brief (USART1) USART Mode Register */ -#define REG_USART1_IER (0x40020208U) /**< \brief (USART1) USART Interrupt Enable Register */ -#define REG_USART1_IDR (0x4002020CU) /**< \brief (USART1) USART Interrupt Disable Register */ -#define REG_USART1_IMR (0x40020210U) /**< \brief (USART1) USART Interrupt Mask Register */ -#define REG_USART1_CSR (0x40020214U) /**< \brief (USART1) USART Channel Status Register */ -#define REG_USART1_RHR (0x40020218U) /**< \brief (USART1) USART Receive Holding Register */ -#define REG_USART1_THR (0x4002021CU) /**< \brief (USART1) USART Transmit Holding Register */ -#define REG_USART1_BRGR (0x40020220U) /**< \brief (USART1) USART Baud Rate Generator Register */ -#define REG_USART1_RTOR (0x40020224U) /**< \brief (USART1) USART Receiver Time-out Register */ -#define REG_USART1_TTGR (0x40020228U) /**< \brief (USART1) USART Transmitter Timeguard Register */ -#define REG_USART1_FIDI (0x40020240U) /**< \brief (USART1) USART FI DI Ratio Register */ -#define REG_USART1_NER (0x40020244U) /**< \brief (USART1) USART Number of Errors Register */ -#define REG_USART1_LINMR (0x40020254U) /**< \brief (USART1) USART LIN Mode Register */ -#define REG_USART1_LINIR (0x40020258U) /**< \brief (USART1) USART LIN Identifier Register */ -#define REG_USART1_LINBRR (0x4002025CU) /**< \brief (USART1) USART LIN Baud Rate Register */ -#define REG_USART1_CMPR (0x40020290U) /**< \brief (USART1) USART Comparison Register */ -#define REG_USART1_WPMR (0x400202E4U) /**< \brief (USART1) USART Write Protection Mode Register */ -#define REG_USART1_WPSR (0x400202E8U) /**< \brief (USART1) USART Write Protection Status Register */ -#define REG_USART1_RPR (0x40020300U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR (0x40020304U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR (0x40020308U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR (0x4002030CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR (0x40020310U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR (0x40020314U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR (0x40020318U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR (0x4002031CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR (0x40020320U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR (0x40020324U) /**< \brief (USART1) Transfer Status Register */ -#else -#define REG_USART1_CR (*(__O uint32_t*)0x40020200U) /**< \brief (USART1) USART Control Register */ -#define REG_USART1_MR (*(__IO uint32_t*)0x40020204U) /**< \brief (USART1) USART Mode Register */ -#define REG_USART1_IER (*(__O uint32_t*)0x40020208U) /**< \brief (USART1) USART Interrupt Enable Register */ -#define REG_USART1_IDR (*(__O uint32_t*)0x4002020CU) /**< \brief (USART1) USART Interrupt Disable Register */ -#define REG_USART1_IMR (*(__I uint32_t*)0x40020210U) /**< \brief (USART1) USART Interrupt Mask Register */ -#define REG_USART1_CSR (*(__I uint32_t*)0x40020214U) /**< \brief (USART1) USART Channel Status Register */ -#define REG_USART1_RHR (*(__I uint32_t*)0x40020218U) /**< \brief (USART1) USART Receive Holding Register */ -#define REG_USART1_THR (*(__O uint32_t*)0x4002021CU) /**< \brief (USART1) USART Transmit Holding Register */ -#define REG_USART1_BRGR (*(__IO uint32_t*)0x40020220U) /**< \brief (USART1) USART Baud Rate Generator Register */ -#define REG_USART1_RTOR (*(__IO uint32_t*)0x40020224U) /**< \brief (USART1) USART Receiver Time-out Register */ -#define REG_USART1_TTGR (*(__IO uint32_t*)0x40020228U) /**< \brief (USART1) USART Transmitter Timeguard Register */ -#define REG_USART1_FIDI (*(__IO uint32_t*)0x40020240U) /**< \brief (USART1) USART FI DI Ratio Register */ -#define REG_USART1_NER (*(__I uint32_t*)0x40020244U) /**< \brief (USART1) USART Number of Errors Register */ -#define REG_USART1_LINMR (*(__IO uint32_t*)0x40020254U) /**< \brief (USART1) USART LIN Mode Register */ -#define REG_USART1_LINIR (*(__IO uint32_t*)0x40020258U) /**< \brief (USART1) USART LIN Identifier Register */ -#define REG_USART1_LINBRR (*(__I uint32_t*)0x4002025CU) /**< \brief (USART1) USART LIN Baud Rate Register */ -#define REG_USART1_CMPR (*(__IO uint32_t*)0x40020290U) /**< \brief (USART1) USART Comparison Register */ -#define REG_USART1_WPMR (*(__IO uint32_t*)0x400202E4U) /**< \brief (USART1) USART Write Protection Mode Register */ -#define REG_USART1_WPSR (*(__I uint32_t*)0x400202E8U) /**< \brief (USART1) USART Write Protection Status Register */ -#define REG_USART1_RPR (*(__IO uint32_t*)0x40020300U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR (*(__IO uint32_t*)0x40020304U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR (*(__IO uint32_t*)0x40020308U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR (*(__IO uint32_t*)0x4002030CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR (*(__IO uint32_t*)0x40020310U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR (*(__IO uint32_t*)0x40020314U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR (*(__IO uint32_t*)0x40020318U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR (*(__IO uint32_t*)0x4002031CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR (*(__O uint32_t*)0x40020320U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR (*(__I uint32_t*)0x40020324U) /**< \brief (USART1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_USART1_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart2.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart2.h deleted file mode 100644 index 78c45172852..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart2.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART2_INSTANCE_ -#define _SAMG55_USART2_INSTANCE_ - -/* ========== Register definition for USART2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART2_CR (0x40024200U) /**< \brief (USART2) USART Control Register */ -#define REG_USART2_MR (0x40024204U) /**< \brief (USART2) USART Mode Register */ -#define REG_USART2_IER (0x40024208U) /**< \brief (USART2) USART Interrupt Enable Register */ -#define REG_USART2_IDR (0x4002420CU) /**< \brief (USART2) USART Interrupt Disable Register */ -#define REG_USART2_IMR (0x40024210U) /**< \brief (USART2) USART Interrupt Mask Register */ -#define REG_USART2_CSR (0x40024214U) /**< \brief (USART2) USART Channel Status Register */ -#define REG_USART2_RHR (0x40024218U) /**< \brief (USART2) USART Receive Holding Register */ -#define REG_USART2_THR (0x4002421CU) /**< \brief (USART2) USART Transmit Holding Register */ -#define REG_USART2_BRGR (0x40024220U) /**< \brief (USART2) USART Baud Rate Generator Register */ -#define REG_USART2_RTOR (0x40024224U) /**< \brief (USART2) USART Receiver Time-out Register */ -#define REG_USART2_TTGR (0x40024228U) /**< \brief (USART2) USART Transmitter Timeguard Register */ -#define REG_USART2_FIDI (0x40024240U) /**< \brief (USART2) USART FI DI Ratio Register */ -#define REG_USART2_NER (0x40024244U) /**< \brief (USART2) USART Number of Errors Register */ -#define REG_USART2_LINMR (0x40024254U) /**< \brief (USART2) USART LIN Mode Register */ -#define REG_USART2_LINIR (0x40024258U) /**< \brief (USART2) USART LIN Identifier Register */ -#define REG_USART2_LINBRR (0x4002425CU) /**< \brief (USART2) USART LIN Baud Rate Register */ -#define REG_USART2_CMPR (0x40024290U) /**< \brief (USART2) USART Comparison Register */ -#define REG_USART2_WPMR (0x400242E4U) /**< \brief (USART2) USART Write Protection Mode Register */ -#define REG_USART2_WPSR (0x400242E8U) /**< \brief (USART2) USART Write Protection Status Register */ -#define REG_USART2_RPR (0x40024300U) /**< \brief (USART2) Receive Pointer Register */ -#define REG_USART2_RCR (0x40024304U) /**< \brief (USART2) Receive Counter Register */ -#define REG_USART2_TPR (0x40024308U) /**< \brief (USART2) Transmit Pointer Register */ -#define REG_USART2_TCR (0x4002430CU) /**< \brief (USART2) Transmit Counter Register */ -#define REG_USART2_RNPR (0x40024310U) /**< \brief (USART2) Receive Next Pointer Register */ -#define REG_USART2_RNCR (0x40024314U) /**< \brief (USART2) Receive Next Counter Register */ -#define REG_USART2_TNPR (0x40024318U) /**< \brief (USART2) Transmit Next Pointer Register */ -#define REG_USART2_TNCR (0x4002431CU) /**< \brief (USART2) Transmit Next Counter Register */ -#define REG_USART2_PTCR (0x40024320U) /**< \brief (USART2) Transfer Control Register */ -#define REG_USART2_PTSR (0x40024324U) /**< \brief (USART2) Transfer Status Register */ -#else -#define REG_USART2_CR (*(__O uint32_t*)0x40024200U) /**< \brief (USART2) USART Control Register */ -#define REG_USART2_MR (*(__IO uint32_t*)0x40024204U) /**< \brief (USART2) USART Mode Register */ -#define REG_USART2_IER (*(__O uint32_t*)0x40024208U) /**< \brief (USART2) USART Interrupt Enable Register */ -#define REG_USART2_IDR (*(__O uint32_t*)0x4002420CU) /**< \brief (USART2) USART Interrupt Disable Register */ -#define REG_USART2_IMR (*(__I uint32_t*)0x40024210U) /**< \brief (USART2) USART Interrupt Mask Register */ -#define REG_USART2_CSR (*(__I uint32_t*)0x40024214U) /**< \brief (USART2) USART Channel Status Register */ -#define REG_USART2_RHR (*(__I uint32_t*)0x40024218U) /**< \brief (USART2) USART Receive Holding Register */ -#define REG_USART2_THR (*(__O uint32_t*)0x4002421CU) /**< \brief (USART2) USART Transmit Holding Register */ -#define REG_USART2_BRGR (*(__IO uint32_t*)0x40024220U) /**< \brief (USART2) USART Baud Rate Generator Register */ -#define REG_USART2_RTOR (*(__IO uint32_t*)0x40024224U) /**< \brief (USART2) USART Receiver Time-out Register */ -#define REG_USART2_TTGR (*(__IO uint32_t*)0x40024228U) /**< \brief (USART2) USART Transmitter Timeguard Register */ -#define REG_USART2_FIDI (*(__IO uint32_t*)0x40024240U) /**< \brief (USART2) USART FI DI Ratio Register */ -#define REG_USART2_NER (*(__I uint32_t*)0x40024244U) /**< \brief (USART2) USART Number of Errors Register */ -#define REG_USART2_LINMR (*(__IO uint32_t*)0x40024254U) /**< \brief (USART2) USART LIN Mode Register */ -#define REG_USART2_LINIR (*(__IO uint32_t*)0x40024258U) /**< \brief (USART2) USART LIN Identifier Register */ -#define REG_USART2_LINBRR (*(__I uint32_t*)0x4002425CU) /**< \brief (USART2) USART LIN Baud Rate Register */ -#define REG_USART2_CMPR (*(__IO uint32_t*)0x40024290U) /**< \brief (USART2) USART Comparison Register */ -#define REG_USART2_WPMR (*(__IO uint32_t*)0x400242E4U) /**< \brief (USART2) USART Write Protection Mode Register */ -#define REG_USART2_WPSR (*(__I uint32_t*)0x400242E8U) /**< \brief (USART2) USART Write Protection Status Register */ -#define REG_USART2_RPR (*(__IO uint32_t*)0x40024300U) /**< \brief (USART2) Receive Pointer Register */ -#define REG_USART2_RCR (*(__IO uint32_t*)0x40024304U) /**< \brief (USART2) Receive Counter Register */ -#define REG_USART2_TPR (*(__IO uint32_t*)0x40024308U) /**< \brief (USART2) Transmit Pointer Register */ -#define REG_USART2_TCR (*(__IO uint32_t*)0x4002430CU) /**< \brief (USART2) Transmit Counter Register */ -#define REG_USART2_RNPR (*(__IO uint32_t*)0x40024310U) /**< \brief (USART2) Receive Next Pointer Register */ -#define REG_USART2_RNCR (*(__IO uint32_t*)0x40024314U) /**< \brief (USART2) Receive Next Counter Register */ -#define REG_USART2_TNPR (*(__IO uint32_t*)0x40024318U) /**< \brief (USART2) Transmit Next Pointer Register */ -#define REG_USART2_TNCR (*(__IO uint32_t*)0x4002431CU) /**< \brief (USART2) Transmit Next Counter Register */ -#define REG_USART2_PTCR (*(__O uint32_t*)0x40024320U) /**< \brief (USART2) Transfer Control Register */ -#define REG_USART2_PTSR (*(__I uint32_t*)0x40024324U) /**< \brief (USART2) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_USART2_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart3.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart3.h deleted file mode 100644 index baf2514933a..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart3.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART3_INSTANCE_ -#define _SAMG55_USART3_INSTANCE_ - -/* ========== Register definition for USART3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART3_CR (0x40018200U) /**< \brief (USART3) USART Control Register */ -#define REG_USART3_MR (0x40018204U) /**< \brief (USART3) USART Mode Register */ -#define REG_USART3_IER (0x40018208U) /**< \brief (USART3) USART Interrupt Enable Register */ -#define REG_USART3_IDR (0x4001820CU) /**< \brief (USART3) USART Interrupt Disable Register */ -#define REG_USART3_IMR (0x40018210U) /**< \brief (USART3) USART Interrupt Mask Register */ -#define REG_USART3_CSR (0x40018214U) /**< \brief (USART3) USART Channel Status Register */ -#define REG_USART3_RHR (0x40018218U) /**< \brief (USART3) USART Receive Holding Register */ -#define REG_USART3_THR (0x4001821CU) /**< \brief (USART3) USART Transmit Holding Register */ -#define REG_USART3_BRGR (0x40018220U) /**< \brief (USART3) USART Baud Rate Generator Register */ -#define REG_USART3_RTOR (0x40018224U) /**< \brief (USART3) USART Receiver Time-out Register */ -#define REG_USART3_TTGR (0x40018228U) /**< \brief (USART3) USART Transmitter Timeguard Register */ -#define REG_USART3_FIDI (0x40018240U) /**< \brief (USART3) USART FI DI Ratio Register */ -#define REG_USART3_NER (0x40018244U) /**< \brief (USART3) USART Number of Errors Register */ -#define REG_USART3_LINMR (0x40018254U) /**< \brief (USART3) USART LIN Mode Register */ -#define REG_USART3_LINIR (0x40018258U) /**< \brief (USART3) USART LIN Identifier Register */ -#define REG_USART3_LINBRR (0x4001825CU) /**< \brief (USART3) USART LIN Baud Rate Register */ -#define REG_USART3_CMPR (0x40018290U) /**< \brief (USART3) USART Comparison Register */ -#define REG_USART3_WPMR (0x400182E4U) /**< \brief (USART3) USART Write Protection Mode Register */ -#define REG_USART3_WPSR (0x400182E8U) /**< \brief (USART3) USART Write Protection Status Register */ -#define REG_USART3_RPR (0x40018300U) /**< \brief (USART3) Receive Pointer Register */ -#define REG_USART3_RCR (0x40018304U) /**< \brief (USART3) Receive Counter Register */ -#define REG_USART3_TPR (0x40018308U) /**< \brief (USART3) Transmit Pointer Register */ -#define REG_USART3_TCR (0x4001830CU) /**< \brief (USART3) Transmit Counter Register */ -#define REG_USART3_RNPR (0x40018310U) /**< \brief (USART3) Receive Next Pointer Register */ -#define REG_USART3_RNCR (0x40018314U) /**< \brief (USART3) Receive Next Counter Register */ -#define REG_USART3_TNPR (0x40018318U) /**< \brief (USART3) Transmit Next Pointer Register */ -#define REG_USART3_TNCR (0x4001831CU) /**< \brief (USART3) Transmit Next Counter Register */ -#define REG_USART3_PTCR (0x40018320U) /**< \brief (USART3) Transfer Control Register */ -#define REG_USART3_PTSR (0x40018324U) /**< \brief (USART3) Transfer Status Register */ -#else -#define REG_USART3_CR (*(__O uint32_t*)0x40018200U) /**< \brief (USART3) USART Control Register */ -#define REG_USART3_MR (*(__IO uint32_t*)0x40018204U) /**< \brief (USART3) USART Mode Register */ -#define REG_USART3_IER (*(__O uint32_t*)0x40018208U) /**< \brief (USART3) USART Interrupt Enable Register */ -#define REG_USART3_IDR (*(__O uint32_t*)0x4001820CU) /**< \brief (USART3) USART Interrupt Disable Register */ -#define REG_USART3_IMR (*(__I uint32_t*)0x40018210U) /**< \brief (USART3) USART Interrupt Mask Register */ -#define REG_USART3_CSR (*(__I uint32_t*)0x40018214U) /**< \brief (USART3) USART Channel Status Register */ -#define REG_USART3_RHR (*(__I uint32_t*)0x40018218U) /**< \brief (USART3) USART Receive Holding Register */ -#define REG_USART3_THR (*(__O uint32_t*)0x4001821CU) /**< \brief (USART3) USART Transmit Holding Register */ -#define REG_USART3_BRGR (*(__IO uint32_t*)0x40018220U) /**< \brief (USART3) USART Baud Rate Generator Register */ -#define REG_USART3_RTOR (*(__IO uint32_t*)0x40018224U) /**< \brief (USART3) USART Receiver Time-out Register */ -#define REG_USART3_TTGR (*(__IO uint32_t*)0x40018228U) /**< \brief (USART3) USART Transmitter Timeguard Register */ -#define REG_USART3_FIDI (*(__IO uint32_t*)0x40018240U) /**< \brief (USART3) USART FI DI Ratio Register */ -#define REG_USART3_NER (*(__I uint32_t*)0x40018244U) /**< \brief (USART3) USART Number of Errors Register */ -#define REG_USART3_LINMR (*(__IO uint32_t*)0x40018254U) /**< \brief (USART3) USART LIN Mode Register */ -#define REG_USART3_LINIR (*(__IO uint32_t*)0x40018258U) /**< \brief (USART3) USART LIN Identifier Register */ -#define REG_USART3_LINBRR (*(__I uint32_t*)0x4001825CU) /**< \brief (USART3) USART LIN Baud Rate Register */ -#define REG_USART3_CMPR (*(__IO uint32_t*)0x40018290U) /**< \brief (USART3) USART Comparison Register */ -#define REG_USART3_WPMR (*(__IO uint32_t*)0x400182E4U) /**< \brief (USART3) USART Write Protection Mode Register */ -#define REG_USART3_WPSR (*(__I uint32_t*)0x400182E8U) /**< \brief (USART3) USART Write Protection Status Register */ -#define REG_USART3_RPR (*(__IO uint32_t*)0x40018300U) /**< \brief (USART3) Receive Pointer Register */ -#define REG_USART3_RCR (*(__IO uint32_t*)0x40018304U) /**< \brief (USART3) Receive Counter Register */ -#define REG_USART3_TPR (*(__IO uint32_t*)0x40018308U) /**< \brief (USART3) Transmit Pointer Register */ -#define REG_USART3_TCR (*(__IO uint32_t*)0x4001830CU) /**< \brief (USART3) Transmit Counter Register */ -#define REG_USART3_RNPR (*(__IO uint32_t*)0x40018310U) /**< \brief (USART3) Receive Next Pointer Register */ -#define REG_USART3_RNCR (*(__IO uint32_t*)0x40018314U) /**< \brief (USART3) Receive Next Counter Register */ -#define REG_USART3_TNPR (*(__IO uint32_t*)0x40018318U) /**< \brief (USART3) Transmit Next Pointer Register */ -#define REG_USART3_TNCR (*(__IO uint32_t*)0x4001831CU) /**< \brief (USART3) Transmit Next Counter Register */ -#define REG_USART3_PTCR (*(__O uint32_t*)0x40018320U) /**< \brief (USART3) Transfer Control Register */ -#define REG_USART3_PTSR (*(__I uint32_t*)0x40018324U) /**< \brief (USART3) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_USART3_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart4.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart4.h deleted file mode 100644 index 6604240a43b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart4.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART4_INSTANCE_ -#define _SAMG55_USART4_INSTANCE_ - -/* ========== Register definition for USART4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART4_CR (0x4001C200U) /**< \brief (USART4) USART Control Register */ -#define REG_USART4_MR (0x4001C204U) /**< \brief (USART4) USART Mode Register */ -#define REG_USART4_IER (0x4001C208U) /**< \brief (USART4) USART Interrupt Enable Register */ -#define REG_USART4_IDR (0x4001C20CU) /**< \brief (USART4) USART Interrupt Disable Register */ -#define REG_USART4_IMR (0x4001C210U) /**< \brief (USART4) USART Interrupt Mask Register */ -#define REG_USART4_CSR (0x4001C214U) /**< \brief (USART4) USART Channel Status Register */ -#define REG_USART4_RHR (0x4001C218U) /**< \brief (USART4) USART Receive Holding Register */ -#define REG_USART4_THR (0x4001C21CU) /**< \brief (USART4) USART Transmit Holding Register */ -#define REG_USART4_BRGR (0x4001C220U) /**< \brief (USART4) USART Baud Rate Generator Register */ -#define REG_USART4_RTOR (0x4001C224U) /**< \brief (USART4) USART Receiver Time-out Register */ -#define REG_USART4_TTGR (0x4001C228U) /**< \brief (USART4) USART Transmitter Timeguard Register */ -#define REG_USART4_FIDI (0x4001C240U) /**< \brief (USART4) USART FI DI Ratio Register */ -#define REG_USART4_NER (0x4001C244U) /**< \brief (USART4) USART Number of Errors Register */ -#define REG_USART4_LINMR (0x4001C254U) /**< \brief (USART4) USART LIN Mode Register */ -#define REG_USART4_LINIR (0x4001C258U) /**< \brief (USART4) USART LIN Identifier Register */ -#define REG_USART4_LINBRR (0x4001C25CU) /**< \brief (USART4) USART LIN Baud Rate Register */ -#define REG_USART4_CMPR (0x4001C290U) /**< \brief (USART4) USART Comparison Register */ -#define REG_USART4_WPMR (0x4001C2E4U) /**< \brief (USART4) USART Write Protection Mode Register */ -#define REG_USART4_WPSR (0x4001C2E8U) /**< \brief (USART4) USART Write Protection Status Register */ -#define REG_USART4_RPR (0x4001C300U) /**< \brief (USART4) Receive Pointer Register */ -#define REG_USART4_RCR (0x4001C304U) /**< \brief (USART4) Receive Counter Register */ -#define REG_USART4_TPR (0x4001C308U) /**< \brief (USART4) Transmit Pointer Register */ -#define REG_USART4_TCR (0x4001C30CU) /**< \brief (USART4) Transmit Counter Register */ -#define REG_USART4_RNPR (0x4001C310U) /**< \brief (USART4) Receive Next Pointer Register */ -#define REG_USART4_RNCR (0x4001C314U) /**< \brief (USART4) Receive Next Counter Register */ -#define REG_USART4_TNPR (0x4001C318U) /**< \brief (USART4) Transmit Next Pointer Register */ -#define REG_USART4_TNCR (0x4001C31CU) /**< \brief (USART4) Transmit Next Counter Register */ -#define REG_USART4_PTCR (0x4001C320U) /**< \brief (USART4) Transfer Control Register */ -#define REG_USART4_PTSR (0x4001C324U) /**< \brief (USART4) Transfer Status Register */ -#else -#define REG_USART4_CR (*(__O uint32_t*)0x4001C200U) /**< \brief (USART4) USART Control Register */ -#define REG_USART4_MR (*(__IO uint32_t*)0x4001C204U) /**< \brief (USART4) USART Mode Register */ -#define REG_USART4_IER (*(__O uint32_t*)0x4001C208U) /**< \brief (USART4) USART Interrupt Enable Register */ -#define REG_USART4_IDR (*(__O uint32_t*)0x4001C20CU) /**< \brief (USART4) USART Interrupt Disable Register */ -#define REG_USART4_IMR (*(__I uint32_t*)0x4001C210U) /**< \brief (USART4) USART Interrupt Mask Register */ -#define REG_USART4_CSR (*(__I uint32_t*)0x4001C214U) /**< \brief (USART4) USART Channel Status Register */ -#define REG_USART4_RHR (*(__I uint32_t*)0x4001C218U) /**< \brief (USART4) USART Receive Holding Register */ -#define REG_USART4_THR (*(__O uint32_t*)0x4001C21CU) /**< \brief (USART4) USART Transmit Holding Register */ -#define REG_USART4_BRGR (*(__IO uint32_t*)0x4001C220U) /**< \brief (USART4) USART Baud Rate Generator Register */ -#define REG_USART4_RTOR (*(__IO uint32_t*)0x4001C224U) /**< \brief (USART4) USART Receiver Time-out Register */ -#define REG_USART4_TTGR (*(__IO uint32_t*)0x4001C228U) /**< \brief (USART4) USART Transmitter Timeguard Register */ -#define REG_USART4_FIDI (*(__IO uint32_t*)0x4001C240U) /**< \brief (USART4) USART FI DI Ratio Register */ -#define REG_USART4_NER (*(__I uint32_t*)0x4001C244U) /**< \brief (USART4) USART Number of Errors Register */ -#define REG_USART4_LINMR (*(__IO uint32_t*)0x4001C254U) /**< \brief (USART4) USART LIN Mode Register */ -#define REG_USART4_LINIR (*(__IO uint32_t*)0x4001C258U) /**< \brief (USART4) USART LIN Identifier Register */ -#define REG_USART4_LINBRR (*(__I uint32_t*)0x4001C25CU) /**< \brief (USART4) USART LIN Baud Rate Register */ -#define REG_USART4_CMPR (*(__IO uint32_t*)0x4001C290U) /**< \brief (USART4) USART Comparison Register */ -#define REG_USART4_WPMR (*(__IO uint32_t*)0x4001C2E4U) /**< \brief (USART4) USART Write Protection Mode Register */ -#define REG_USART4_WPSR (*(__I uint32_t*)0x4001C2E8U) /**< \brief (USART4) USART Write Protection Status Register */ -#define REG_USART4_RPR (*(__IO uint32_t*)0x4001C300U) /**< \brief (USART4) Receive Pointer Register */ -#define REG_USART4_RCR (*(__IO uint32_t*)0x4001C304U) /**< \brief (USART4) Receive Counter Register */ -#define REG_USART4_TPR (*(__IO uint32_t*)0x4001C308U) /**< \brief (USART4) Transmit Pointer Register */ -#define REG_USART4_TCR (*(__IO uint32_t*)0x4001C30CU) /**< \brief (USART4) Transmit Counter Register */ -#define REG_USART4_RNPR (*(__IO uint32_t*)0x4001C310U) /**< \brief (USART4) Receive Next Pointer Register */ -#define REG_USART4_RNCR (*(__IO uint32_t*)0x4001C314U) /**< \brief (USART4) Receive Next Counter Register */ -#define REG_USART4_TNPR (*(__IO uint32_t*)0x4001C318U) /**< \brief (USART4) Transmit Next Pointer Register */ -#define REG_USART4_TNCR (*(__IO uint32_t*)0x4001C31CU) /**< \brief (USART4) Transmit Next Counter Register */ -#define REG_USART4_PTCR (*(__O uint32_t*)0x4001C320U) /**< \brief (USART4) Transfer Control Register */ -#define REG_USART4_PTSR (*(__I uint32_t*)0x4001C324U) /**< \brief (USART4) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_USART4_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart5.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart5.h deleted file mode 100644 index a61a5b813d6..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart5.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART5_INSTANCE_ -#define _SAMG55_USART5_INSTANCE_ - -/* ========== Register definition for USART5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART5_CR (0x40008200U) /**< \brief (USART5) USART Control Register */ -#define REG_USART5_MR (0x40008204U) /**< \brief (USART5) USART Mode Register */ -#define REG_USART5_IER (0x40008208U) /**< \brief (USART5) USART Interrupt Enable Register */ -#define REG_USART5_IDR (0x4000820CU) /**< \brief (USART5) USART Interrupt Disable Register */ -#define REG_USART5_IMR (0x40008210U) /**< \brief (USART5) USART Interrupt Mask Register */ -#define REG_USART5_CSR (0x40008214U) /**< \brief (USART5) USART Channel Status Register */ -#define REG_USART5_RHR (0x40008218U) /**< \brief (USART5) USART Receive Holding Register */ -#define REG_USART5_THR (0x4000821CU) /**< \brief (USART5) USART Transmit Holding Register */ -#define REG_USART5_BRGR (0x40008220U) /**< \brief (USART5) USART Baud Rate Generator Register */ -#define REG_USART5_RTOR (0x40008224U) /**< \brief (USART5) USART Receiver Time-out Register */ -#define REG_USART5_TTGR (0x40008228U) /**< \brief (USART5) USART Transmitter Timeguard Register */ -#define REG_USART5_FIDI (0x40008240U) /**< \brief (USART5) USART FI DI Ratio Register */ -#define REG_USART5_NER (0x40008244U) /**< \brief (USART5) USART Number of Errors Register */ -#define REG_USART5_LINMR (0x40008254U) /**< \brief (USART5) USART LIN Mode Register */ -#define REG_USART5_LINIR (0x40008258U) /**< \brief (USART5) USART LIN Identifier Register */ -#define REG_USART5_LINBRR (0x4000825CU) /**< \brief (USART5) USART LIN Baud Rate Register */ -#define REG_USART5_CMPR (0x40008290U) /**< \brief (USART5) USART Comparison Register */ -#define REG_USART5_WPMR (0x400082E4U) /**< \brief (USART5) USART Write Protection Mode Register */ -#define REG_USART5_WPSR (0x400082E8U) /**< \brief (USART5) USART Write Protection Status Register */ -#define REG_USART5_RPR (0x40008300U) /**< \brief (USART5) Receive Pointer Register */ -#define REG_USART5_RCR (0x40008304U) /**< \brief (USART5) Receive Counter Register */ -#define REG_USART5_TPR (0x40008308U) /**< \brief (USART5) Transmit Pointer Register */ -#define REG_USART5_TCR (0x4000830CU) /**< \brief (USART5) Transmit Counter Register */ -#define REG_USART5_RNPR (0x40008310U) /**< \brief (USART5) Receive Next Pointer Register */ -#define REG_USART5_RNCR (0x40008314U) /**< \brief (USART5) Receive Next Counter Register */ -#define REG_USART5_TNPR (0x40008318U) /**< \brief (USART5) Transmit Next Pointer Register */ -#define REG_USART5_TNCR (0x4000831CU) /**< \brief (USART5) Transmit Next Counter Register */ -#define REG_USART5_PTCR (0x40008320U) /**< \brief (USART5) Transfer Control Register */ -#define REG_USART5_PTSR (0x40008324U) /**< \brief (USART5) Transfer Status Register */ -#else -#define REG_USART5_CR (*(__O uint32_t*)0x40008200U) /**< \brief (USART5) USART Control Register */ -#define REG_USART5_MR (*(__IO uint32_t*)0x40008204U) /**< \brief (USART5) USART Mode Register */ -#define REG_USART5_IER (*(__O uint32_t*)0x40008208U) /**< \brief (USART5) USART Interrupt Enable Register */ -#define REG_USART5_IDR (*(__O uint32_t*)0x4000820CU) /**< \brief (USART5) USART Interrupt Disable Register */ -#define REG_USART5_IMR (*(__I uint32_t*)0x40008210U) /**< \brief (USART5) USART Interrupt Mask Register */ -#define REG_USART5_CSR (*(__I uint32_t*)0x40008214U) /**< \brief (USART5) USART Channel Status Register */ -#define REG_USART5_RHR (*(__I uint32_t*)0x40008218U) /**< \brief (USART5) USART Receive Holding Register */ -#define REG_USART5_THR (*(__O uint32_t*)0x4000821CU) /**< \brief (USART5) USART Transmit Holding Register */ -#define REG_USART5_BRGR (*(__IO uint32_t*)0x40008220U) /**< \brief (USART5) USART Baud Rate Generator Register */ -#define REG_USART5_RTOR (*(__IO uint32_t*)0x40008224U) /**< \brief (USART5) USART Receiver Time-out Register */ -#define REG_USART5_TTGR (*(__IO uint32_t*)0x40008228U) /**< \brief (USART5) USART Transmitter Timeguard Register */ -#define REG_USART5_FIDI (*(__IO uint32_t*)0x40008240U) /**< \brief (USART5) USART FI DI Ratio Register */ -#define REG_USART5_NER (*(__I uint32_t*)0x40008244U) /**< \brief (USART5) USART Number of Errors Register */ -#define REG_USART5_LINMR (*(__IO uint32_t*)0x40008254U) /**< \brief (USART5) USART LIN Mode Register */ -#define REG_USART5_LINIR (*(__IO uint32_t*)0x40008258U) /**< \brief (USART5) USART LIN Identifier Register */ -#define REG_USART5_LINBRR (*(__I uint32_t*)0x4000825CU) /**< \brief (USART5) USART LIN Baud Rate Register */ -#define REG_USART5_CMPR (*(__IO uint32_t*)0x40008290U) /**< \brief (USART5) USART Comparison Register */ -#define REG_USART5_WPMR (*(__IO uint32_t*)0x400082E4U) /**< \brief (USART5) USART Write Protection Mode Register */ -#define REG_USART5_WPSR (*(__I uint32_t*)0x400082E8U) /**< \brief (USART5) USART Write Protection Status Register */ -#define REG_USART5_RPR (*(__IO uint32_t*)0x40008300U) /**< \brief (USART5) Receive Pointer Register */ -#define REG_USART5_RCR (*(__IO uint32_t*)0x40008304U) /**< \brief (USART5) Receive Counter Register */ -#define REG_USART5_TPR (*(__IO uint32_t*)0x40008308U) /**< \brief (USART5) Transmit Pointer Register */ -#define REG_USART5_TCR (*(__IO uint32_t*)0x4000830CU) /**< \brief (USART5) Transmit Counter Register */ -#define REG_USART5_RNPR (*(__IO uint32_t*)0x40008310U) /**< \brief (USART5) Receive Next Pointer Register */ -#define REG_USART5_RNCR (*(__IO uint32_t*)0x40008314U) /**< \brief (USART5) Receive Next Counter Register */ -#define REG_USART5_TNPR (*(__IO uint32_t*)0x40008318U) /**< \brief (USART5) Transmit Next Pointer Register */ -#define REG_USART5_TNCR (*(__IO uint32_t*)0x4000831CU) /**< \brief (USART5) Transmit Next Counter Register */ -#define REG_USART5_PTCR (*(__O uint32_t*)0x40008320U) /**< \brief (USART5) Transfer Control Register */ -#define REG_USART5_PTSR (*(__I uint32_t*)0x40008324U) /**< \brief (USART5) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_USART5_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart6.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart6.h deleted file mode 100644 index d3fe404a9b1..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart6.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART6_INSTANCE_ -#define _SAMG55_USART6_INSTANCE_ - -/* ========== Register definition for USART6 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART6_CR (0x40040200U) /**< \brief (USART6) USART Control Register */ -#define REG_USART6_MR (0x40040204U) /**< \brief (USART6) USART Mode Register */ -#define REG_USART6_IER (0x40040208U) /**< \brief (USART6) USART Interrupt Enable Register */ -#define REG_USART6_IDR (0x4004020CU) /**< \brief (USART6) USART Interrupt Disable Register */ -#define REG_USART6_IMR (0x40040210U) /**< \brief (USART6) USART Interrupt Mask Register */ -#define REG_USART6_CSR (0x40040214U) /**< \brief (USART6) USART Channel Status Register */ -#define REG_USART6_RHR (0x40040218U) /**< \brief (USART6) USART Receive Holding Register */ -#define REG_USART6_THR (0x4004021CU) /**< \brief (USART6) USART Transmit Holding Register */ -#define REG_USART6_BRGR (0x40040220U) /**< \brief (USART6) USART Baud Rate Generator Register */ -#define REG_USART6_RTOR (0x40040224U) /**< \brief (USART6) USART Receiver Time-out Register */ -#define REG_USART6_TTGR (0x40040228U) /**< \brief (USART6) USART Transmitter Timeguard Register */ -#define REG_USART6_FIDI (0x40040240U) /**< \brief (USART6) USART FI DI Ratio Register */ -#define REG_USART6_NER (0x40040244U) /**< \brief (USART6) USART Number of Errors Register */ -#define REG_USART6_LINMR (0x40040254U) /**< \brief (USART6) USART LIN Mode Register */ -#define REG_USART6_LINIR (0x40040258U) /**< \brief (USART6) USART LIN Identifier Register */ -#define REG_USART6_LINBRR (0x4004025CU) /**< \brief (USART6) USART LIN Baud Rate Register */ -#define REG_USART6_CMPR (0x40040290U) /**< \brief (USART6) USART Comparison Register */ -#define REG_USART6_WPMR (0x400402E4U) /**< \brief (USART6) USART Write Protection Mode Register */ -#define REG_USART6_WPSR (0x400402E8U) /**< \brief (USART6) USART Write Protection Status Register */ -#define REG_USART6_RPR (0x40040300U) /**< \brief (USART6) Receive Pointer Register */ -#define REG_USART6_RCR (0x40040304U) /**< \brief (USART6) Receive Counter Register */ -#define REG_USART6_TPR (0x40040308U) /**< \brief (USART6) Transmit Pointer Register */ -#define REG_USART6_TCR (0x4004030CU) /**< \brief (USART6) Transmit Counter Register */ -#define REG_USART6_RNPR (0x40040310U) /**< \brief (USART6) Receive Next Pointer Register */ -#define REG_USART6_RNCR (0x40040314U) /**< \brief (USART6) Receive Next Counter Register */ -#define REG_USART6_TNPR (0x40040318U) /**< \brief (USART6) Transmit Next Pointer Register */ -#define REG_USART6_TNCR (0x4004031CU) /**< \brief (USART6) Transmit Next Counter Register */ -#define REG_USART6_PTCR (0x40040320U) /**< \brief (USART6) Transfer Control Register */ -#define REG_USART6_PTSR (0x40040324U) /**< \brief (USART6) Transfer Status Register */ -#else -#define REG_USART6_CR (*(__O uint32_t*)0x40040200U) /**< \brief (USART6) USART Control Register */ -#define REG_USART6_MR (*(__IO uint32_t*)0x40040204U) /**< \brief (USART6) USART Mode Register */ -#define REG_USART6_IER (*(__O uint32_t*)0x40040208U) /**< \brief (USART6) USART Interrupt Enable Register */ -#define REG_USART6_IDR (*(__O uint32_t*)0x4004020CU) /**< \brief (USART6) USART Interrupt Disable Register */ -#define REG_USART6_IMR (*(__I uint32_t*)0x40040210U) /**< \brief (USART6) USART Interrupt Mask Register */ -#define REG_USART6_CSR (*(__I uint32_t*)0x40040214U) /**< \brief (USART6) USART Channel Status Register */ -#define REG_USART6_RHR (*(__I uint32_t*)0x40040218U) /**< \brief (USART6) USART Receive Holding Register */ -#define REG_USART6_THR (*(__O uint32_t*)0x4004021CU) /**< \brief (USART6) USART Transmit Holding Register */ -#define REG_USART6_BRGR (*(__IO uint32_t*)0x40040220U) /**< \brief (USART6) USART Baud Rate Generator Register */ -#define REG_USART6_RTOR (*(__IO uint32_t*)0x40040224U) /**< \brief (USART6) USART Receiver Time-out Register */ -#define REG_USART6_TTGR (*(__IO uint32_t*)0x40040228U) /**< \brief (USART6) USART Transmitter Timeguard Register */ -#define REG_USART6_FIDI (*(__IO uint32_t*)0x40040240U) /**< \brief (USART6) USART FI DI Ratio Register */ -#define REG_USART6_NER (*(__I uint32_t*)0x40040244U) /**< \brief (USART6) USART Number of Errors Register */ -#define REG_USART6_LINMR (*(__IO uint32_t*)0x40040254U) /**< \brief (USART6) USART LIN Mode Register */ -#define REG_USART6_LINIR (*(__IO uint32_t*)0x40040258U) /**< \brief (USART6) USART LIN Identifier Register */ -#define REG_USART6_LINBRR (*(__I uint32_t*)0x4004025CU) /**< \brief (USART6) USART LIN Baud Rate Register */ -#define REG_USART6_CMPR (*(__IO uint32_t*)0x40040290U) /**< \brief (USART6) USART Comparison Register */ -#define REG_USART6_WPMR (*(__IO uint32_t*)0x400402E4U) /**< \brief (USART6) USART Write Protection Mode Register */ -#define REG_USART6_WPSR (*(__I uint32_t*)0x400402E8U) /**< \brief (USART6) USART Write Protection Status Register */ -#define REG_USART6_RPR (*(__IO uint32_t*)0x40040300U) /**< \brief (USART6) Receive Pointer Register */ -#define REG_USART6_RCR (*(__IO uint32_t*)0x40040304U) /**< \brief (USART6) Receive Counter Register */ -#define REG_USART6_TPR (*(__IO uint32_t*)0x40040308U) /**< \brief (USART6) Transmit Pointer Register */ -#define REG_USART6_TCR (*(__IO uint32_t*)0x4004030CU) /**< \brief (USART6) Transmit Counter Register */ -#define REG_USART6_RNPR (*(__IO uint32_t*)0x40040310U) /**< \brief (USART6) Receive Next Pointer Register */ -#define REG_USART6_RNCR (*(__IO uint32_t*)0x40040314U) /**< \brief (USART6) Receive Next Counter Register */ -#define REG_USART6_TNPR (*(__IO uint32_t*)0x40040318U) /**< \brief (USART6) Transmit Next Pointer Register */ -#define REG_USART6_TNCR (*(__IO uint32_t*)0x4004031CU) /**< \brief (USART6) Transmit Next Counter Register */ -#define REG_USART6_PTCR (*(__O uint32_t*)0x40040320U) /**< \brief (USART6) Transfer Control Register */ -#define REG_USART6_PTSR (*(__I uint32_t*)0x40040324U) /**< \brief (USART6) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_USART6_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart7.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart7.h deleted file mode 100644 index d998dc1f3ce..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart7.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_USART7_INSTANCE_ -#define _SAMG55_USART7_INSTANCE_ - -/* ========== Register definition for USART7 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART7_CR (0x40034200U) /**< \brief (USART7) USART Control Register */ -#define REG_USART7_MR (0x40034204U) /**< \brief (USART7) USART Mode Register */ -#define REG_USART7_IER (0x40034208U) /**< \brief (USART7) USART Interrupt Enable Register */ -#define REG_USART7_IDR (0x4003420CU) /**< \brief (USART7) USART Interrupt Disable Register */ -#define REG_USART7_IMR (0x40034210U) /**< \brief (USART7) USART Interrupt Mask Register */ -#define REG_USART7_CSR (0x40034214U) /**< \brief (USART7) USART Channel Status Register */ -#define REG_USART7_RHR (0x40034218U) /**< \brief (USART7) USART Receive Holding Register */ -#define REG_USART7_THR (0x4003421CU) /**< \brief (USART7) USART Transmit Holding Register */ -#define REG_USART7_BRGR (0x40034220U) /**< \brief (USART7) USART Baud Rate Generator Register */ -#define REG_USART7_RTOR (0x40034224U) /**< \brief (USART7) USART Receiver Time-out Register */ -#define REG_USART7_TTGR (0x40034228U) /**< \brief (USART7) USART Transmitter Timeguard Register */ -#define REG_USART7_FIDI (0x40034240U) /**< \brief (USART7) USART FI DI Ratio Register */ -#define REG_USART7_NER (0x40034244U) /**< \brief (USART7) USART Number of Errors Register */ -#define REG_USART7_LINMR (0x40034254U) /**< \brief (USART7) USART LIN Mode Register */ -#define REG_USART7_LINIR (0x40034258U) /**< \brief (USART7) USART LIN Identifier Register */ -#define REG_USART7_LINBRR (0x4003425CU) /**< \brief (USART7) USART LIN Baud Rate Register */ -#define REG_USART7_CMPR (0x40034290U) /**< \brief (USART7) USART Comparison Register */ -#define REG_USART7_WPMR (0x400342E4U) /**< \brief (USART7) USART Write Protection Mode Register */ -#define REG_USART7_WPSR (0x400342E8U) /**< \brief (USART7) USART Write Protection Status Register */ -#define REG_USART7_RPR (0x40034300U) /**< \brief (USART7) Receive Pointer Register */ -#define REG_USART7_RCR (0x40034304U) /**< \brief (USART7) Receive Counter Register */ -#define REG_USART7_TPR (0x40034308U) /**< \brief (USART7) Transmit Pointer Register */ -#define REG_USART7_TCR (0x4003430CU) /**< \brief (USART7) Transmit Counter Register */ -#define REG_USART7_RNPR (0x40034310U) /**< \brief (USART7) Receive Next Pointer Register */ -#define REG_USART7_RNCR (0x40034314U) /**< \brief (USART7) Receive Next Counter Register */ -#define REG_USART7_TNPR (0x40034318U) /**< \brief (USART7) Transmit Next Pointer Register */ -#define REG_USART7_TNCR (0x4003431CU) /**< \brief (USART7) Transmit Next Counter Register */ -#define REG_USART7_PTCR (0x40034320U) /**< \brief (USART7) Transfer Control Register */ -#define REG_USART7_PTSR (0x40034324U) /**< \brief (USART7) Transfer Status Register */ -#else -#define REG_USART7_CR (*(__O uint32_t*)0x40034200U) /**< \brief (USART7) USART Control Register */ -#define REG_USART7_MR (*(__IO uint32_t*)0x40034204U) /**< \brief (USART7) USART Mode Register */ -#define REG_USART7_IER (*(__O uint32_t*)0x40034208U) /**< \brief (USART7) USART Interrupt Enable Register */ -#define REG_USART7_IDR (*(__O uint32_t*)0x4003420CU) /**< \brief (USART7) USART Interrupt Disable Register */ -#define REG_USART7_IMR (*(__I uint32_t*)0x40034210U) /**< \brief (USART7) USART Interrupt Mask Register */ -#define REG_USART7_CSR (*(__I uint32_t*)0x40034214U) /**< \brief (USART7) USART Channel Status Register */ -#define REG_USART7_RHR (*(__I uint32_t*)0x40034218U) /**< \brief (USART7) USART Receive Holding Register */ -#define REG_USART7_THR (*(__O uint32_t*)0x4003421CU) /**< \brief (USART7) USART Transmit Holding Register */ -#define REG_USART7_BRGR (*(__IO uint32_t*)0x40034220U) /**< \brief (USART7) USART Baud Rate Generator Register */ -#define REG_USART7_RTOR (*(__IO uint32_t*)0x40034224U) /**< \brief (USART7) USART Receiver Time-out Register */ -#define REG_USART7_TTGR (*(__IO uint32_t*)0x40034228U) /**< \brief (USART7) USART Transmitter Timeguard Register */ -#define REG_USART7_FIDI (*(__IO uint32_t*)0x40034240U) /**< \brief (USART7) USART FI DI Ratio Register */ -#define REG_USART7_NER (*(__I uint32_t*)0x40034244U) /**< \brief (USART7) USART Number of Errors Register */ -#define REG_USART7_LINMR (*(__IO uint32_t*)0x40034254U) /**< \brief (USART7) USART LIN Mode Register */ -#define REG_USART7_LINIR (*(__IO uint32_t*)0x40034258U) /**< \brief (USART7) USART LIN Identifier Register */ -#define REG_USART7_LINBRR (*(__I uint32_t*)0x4003425CU) /**< \brief (USART7) USART LIN Baud Rate Register */ -#define REG_USART7_CMPR (*(__IO uint32_t*)0x40034290U) /**< \brief (USART7) USART Comparison Register */ -#define REG_USART7_WPMR (*(__IO uint32_t*)0x400342E4U) /**< \brief (USART7) USART Write Protection Mode Register */ -#define REG_USART7_WPSR (*(__I uint32_t*)0x400342E8U) /**< \brief (USART7) USART Write Protection Status Register */ -#define REG_USART7_RPR (*(__IO uint32_t*)0x40034300U) /**< \brief (USART7) Receive Pointer Register */ -#define REG_USART7_RCR (*(__IO uint32_t*)0x40034304U) /**< \brief (USART7) Receive Counter Register */ -#define REG_USART7_TPR (*(__IO uint32_t*)0x40034308U) /**< \brief (USART7) Transmit Pointer Register */ -#define REG_USART7_TCR (*(__IO uint32_t*)0x4003430CU) /**< \brief (USART7) Transmit Counter Register */ -#define REG_USART7_RNPR (*(__IO uint32_t*)0x40034310U) /**< \brief (USART7) Receive Next Pointer Register */ -#define REG_USART7_RNCR (*(__IO uint32_t*)0x40034314U) /**< \brief (USART7) Receive Next Counter Register */ -#define REG_USART7_TNPR (*(__IO uint32_t*)0x40034318U) /**< \brief (USART7) Transmit Next Pointer Register */ -#define REG_USART7_TNCR (*(__IO uint32_t*)0x4003431CU) /**< \brief (USART7) Transmit Next Counter Register */ -#define REG_USART7_PTCR (*(__O uint32_t*)0x40034320U) /**< \brief (USART7) Transfer Control Register */ -#define REG_USART7_PTSR (*(__I uint32_t*)0x40034324U) /**< \brief (USART7) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_USART7_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_wdt.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_wdt.h deleted file mode 100644 index 081a2d677d9..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_wdt.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55_WDT_INSTANCE_ -#define _SAMG55_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CR (0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR (0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR (0x400E1458U) /**< \brief (WDT) Status Register */ -#else -#define REG_WDT_CR (*(__O uint32_t*)0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR (*(__IO uint32_t*)0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR (*(__I uint32_t*)0x400E1458U) /**< \brief (WDT) Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAMG55_WDT_INSTANCE_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55g18.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55g18.h deleted file mode 100644 index 9f6689e9e9b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55g18.h +++ /dev/null @@ -1,449 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55G18_PIO_ -#define _SAMG55G18_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for I2SC0 peripheral ========== */ -#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ -#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ -#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ -#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ -#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ -/* ========== Pio definition for I2SC1 peripheral ========== */ -#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ -#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ -#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for SPI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for SPI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for SPI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for SPI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for SPI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for TWI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for TWI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for TWI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for TWI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for TWI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for USART4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for USART5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for USART6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 - -#endif /* _SAMG55G18_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55g19.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55g19.h deleted file mode 100644 index f5f719f5d89..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55g19.h +++ /dev/null @@ -1,449 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55G19_PIO_ -#define _SAMG55G19_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for I2SC0 peripheral ========== */ -#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ -#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ -#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ -#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ -#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ -/* ========== Pio definition for I2SC1 peripheral ========== */ -#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ -#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ -#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for SPI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for SPI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for SPI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for SPI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for SPI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for TWI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for TWI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for TWI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for TWI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for TWI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for USART4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for USART5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for USART6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 - -#endif /* _SAMG55G19_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55j18.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55j18.h deleted file mode 100644 index 40902618e06..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55j18.h +++ /dev/null @@ -1,502 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55J18_PIO_ -#define _SAMG55J18_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for I2SC0 peripheral ========== */ -#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ -#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ -#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ -#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ -#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ -/* ========== Pio definition for I2SC1 peripheral ========== */ -#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ -#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ -#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for SPI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for SPI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for SPI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for SPI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for SPI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for SPI7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for TWI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for TWI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for TWI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for TWI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for TWI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for TWI7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for USART4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for USART5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for USART6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for USART7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 - -#endif /* _SAMG55J18_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55j19.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55j19.h deleted file mode 100644 index 20e11d7ba90..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55j19.h +++ /dev/null @@ -1,502 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55J19_PIO_ -#define _SAMG55J19_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for I2SC0 peripheral ========== */ -#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ -#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ -#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ -#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ -#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ -/* ========== Pio definition for I2SC1 peripheral ========== */ -#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ -#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ -#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for SPI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for SPI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for SPI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for SPI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for SPI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for SPI7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for TWI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for TWI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for TWI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for TWI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for TWI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for TWI7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for USART4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for USART5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for USART6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for USART7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 - -#endif /* _SAMG55J19_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55n19.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55n19.h deleted file mode 100644 index 6cb6c9dbddd..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55n19.h +++ /dev/null @@ -1,502 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55N19_PIO_ -#define _SAMG55N19_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ -#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ -#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for I2SC0 peripheral ========== */ -#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ -#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ -#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ -#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ -#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ -#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ -#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ -/* ========== Pio definition for I2SC1 peripheral ========== */ -#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ -#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ -#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ -#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ -#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for SPI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for SPI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for SPI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for SPI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for SPI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for SPI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for SPI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for SPI7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for TWI2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for TWI3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for TWI4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for TWI5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for TWI6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for TWI7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ -#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ -#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ -#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ -#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ -#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ -#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ -#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ -#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ -#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ -#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ -#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ -#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ -#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ -#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ -#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ -#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ -/* ========== Pio definition for USART4 peripheral ========== */ -#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ -#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ -#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ -#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ -#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ -/* ========== Pio definition for USART5 peripheral ========== */ -#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ -#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ -#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ -#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ -#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ -/* ========== Pio definition for USART6 peripheral ========== */ -#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ -#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ -#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ -#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ -#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ -/* ========== Pio definition for USART7 peripheral ========== */ -#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ -#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ -#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ -#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ -#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PB15_IDX 47 - -#endif /* _SAMG55N19_PIO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55.h deleted file mode 100644 index 2e716eaed17..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _SAMG55_ -#define _SAMG55_ - -#if defined (__SAMG55G18__) -#include "samg55g18.h" -#elif defined (__SAMG55G19__) -#include "samg55g19.h" -#elif defined (__SAMG55J18__) -#include "samg55j18.h" -#elif defined (__SAMG55J19__) -#include "samg55j19.h" -#elif defined (__SAMG55N19__) -#include "samg55n19.h" -#else -#error Library does not support the specified device. -#endif - -#endif /* _SAMG55_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55g18.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55g18.h deleted file mode 100644 index c79d4e48e05..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55g18.h +++ /dev/null @@ -1,721 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55G18_ -#define _SAMG55G18_ - -/** \addtogroup SAMG55G18_definitions SAMG55G18 definitions - This file defines all structures and symbols for SAMG55G18: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAMG55G18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G18_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMG55G18 specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAMG55G18 Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAMG55G18 Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAMG55G18 Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAMG55G18 Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAMG55G18 Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAMG55G18 Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAMG55G18 Enhanced Flash Controller (EFC) */ - USART0_IRQn = 8, /**< 8 SAMG55G18 FLEXCOM0 (USART0) */ - SPI0_IRQn = 8, /**< 8 SAMG55G18 FLEXCOM0 (SPI0) */ - TWI0_IRQn = 8, /**< 8 SAMG55G18 FLEXCOM0 (TWI0) */ - USART1_IRQn = 9, /**< 9 SAMG55G18 FLEXCOM1 (USART1) */ - SPI1_IRQn = 9, /**< 9 SAMG55G18 FLEXCOM1 (SPI1) */ - TWI1_IRQn = 9, /**< 9 SAMG55G18 FLEXCOM1 (TWI1) */ - PIOA_IRQn = 11, /**< 11 SAMG55G18 Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAMG55G18 Parallel I/O Controller B (PIOB) */ - PDMIC0_IRQn = 13, /**< 13 SAMG55G18 PDM 0 (PDMIC0) */ - USART2_IRQn = 14, /**< 14 SAMG55G18 FLEXCOM2 (USART2) */ - SPI2_IRQn = 14, /**< 14 SAMG55G18 FLEXCOM2 (SPI2) */ - TWI2_IRQn = 14, /**< 14 SAMG55G18 FLEXCOM2 (TWI2) */ - MEM2MEM_IRQn = 15, /**< 15 SAMG55G18 MEM2MEM (MEM2MEM) */ - I2SC0_IRQn = 16, /**< 16 SAMG55G18 I2SC0 (I2SC0) */ - I2SC1_IRQn = 17, /**< 17 SAMG55G18 I2SC1 (I2SC1) */ - PDMIC1_IRQn = 18, /**< 18 SAMG55G18 PDM 1 (PDMIC1) */ - USART3_IRQn = 19, /**< 19 SAMG55G18 FLEXCOM3 (USART3) */ - SPI3_IRQn = 19, /**< 19 SAMG55G18 FLEXCOM3 (SPI3) */ - TWI3_IRQn = 19, /**< 19 SAMG55G18 FLEXCOM3 (TWI3) */ - USART4_IRQn = 20, /**< 20 SAMG55G18 FLEXCOM3 (USART4) */ - SPI4_IRQn = 20, /**< 20 SAMG55G18 FLEXCOM3 (SPI4) */ - TWI4_IRQn = 20, /**< 20 SAMG55G18 FLEXCOM3 (TWI4) */ - USART5_IRQn = 21, /**< 21 SAMG55G18 FLEXCOM3 (USART5) */ - SPI5_IRQn = 21, /**< 21 SAMG55G18 FLEXCOM3 (SPI5) */ - TWI5_IRQn = 21, /**< 21 SAMG55G18 FLEXCOM3 (TWI5) */ - USART6_IRQn = 22, /**< 22 SAMG55G18 FLEXCOM3 (USART6) */ - SPI6_IRQn = 22, /**< 22 SAMG55G18 FLEXCOM3 (SPI6) */ - TWI6_IRQn = 22, /**< 22 SAMG55G18 FLEXCOM3 (TWI6) */ - TC0_IRQn = 23, /**< 23 SAMG55G18 Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 SAMG55G18 Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 SAMG55G18 Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 SAMG55G18 Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 SAMG55G18 Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 SAMG55G18 Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 SAMG55G18 Analog To Digital Converter (ADC) */ - ARM_IRQn = 30, /**< 30 SAMG55G18 FPU (ARM) */ - WKUP0_IRQn = 31, /**< 31 SAMG55J18 External interrupt 0 (WKUP0) */ - WKUP1_IRQn = 32, /**< 32 SAMG55J18 External interrupt 1 (WKUP1) */ - WKUP2_IRQn = 33, /**< 33 SAMG55J18 External interrupt 2 (WKUP2) */ - WKUP3_IRQn = 34, /**< 34 SAMG55J18 External interrupt 3 (WKUP3) */ - WKUP4_IRQn = 35, /**< 35 SAMG55J18 External interrupt 4 (WKUP4) */ - WKUP5_IRQn = 36, /**< 36 SAMG55J18 External interrupt 5 (WKUP5) */ - WKUP6_IRQn = 37, /**< 37 SAMG55J18 External interrupt 6 (WKUP6) */ - WKUP7_IRQn = 38, /**< 38 SAMG55J18 External interrupt 7 (WKUP7) */ - WKUP8_IRQn = 39, /**< 39 SAMG55J18 External interrupt 8 (WKUP8) */ - WKUP9_IRQn = 40, /**< 40 SAMG55J18 External interrupt 9 (WKUP9) */ - WKUP10_IRQn = 41, /**< 41 SAMG55J18 External interrupt 10 (WKUP10) */ - WKUP11_IRQn = 42, /**< 42 SAMG55J18 External interrupt 11 (WKUP11) */ - WKUP12_IRQn = 43, /**< 43 SAMG55J18 External interrupt 12 (WKUP12) */ - WKUP13_IRQn = 44, /**< 44 SAMG55J18 External interrupt 13 (WKUP13) */ - WKUP14_IRQn = 45, /**< 45 SAMG55J18 External interrupt 14 (WKUP14) */ - WKUP15_IRQn = 46, /**< 46 SAMG55J18 External interrupt 15 (WKUP15) */ - UHP_IRQn = 47, /**< 47 SAMG55G18 USB OHCI (UHP) */ - UDP_IRQn = 48, /**< 48 SAMG55G18 USB Device FS (UDP) */ - - PERIPH_COUNT_IRQn = 49 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */ - void* pvReserved7; - void* pfnUSART0_Handler; /* 8 FLEXCOM 0 */ - void* pfnSPI0_Handler; /* 8 FLEXCOM 0 */ - void* pfnTWI0_Handler; /* 8 FLEXCOM 0 */ - void* pfnUSART1_Handler; /* 9 FLEXCOM 1 */ - void* pfnSPI1_Handler; /* 9 FLEXCOM 1 */ - void* pfnTWI1_Handler; /* 9 FLEXCOM 1 */ - void* pvReserved10; - void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ - void* pfnPDMIC0_Handler; /* 13 PDM 0 */ - void* pfnUSART2_Handler; /* 14 FLEXCOM 2 */ - void* pfnSPI2_Handler; /* 14 FLEXCOM 2 */ - void* pfnTWI2_Handler; /* 14 FLEXCOM 2 */ - void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */ - void* pfnI2SC0_Handler; /* 16 I2SC0 */ - void* pfnI2SC1_Handler; /* 17 I2SC1 */ - void* pfnPDMIC1_Handler; /* 18 PDM 1 */ - void* pfnUSART3_Handler; /* 19 FLEXCOM 3 */ - void* pfnSPI3_Handler; /* 19 FLEXCOM 3 */ - void* pfnTWI3_Handler; /* 19 FLEXCOM 3 */ - void* pfnUSART4_Handler; /* 20 FLEXCOM 4 */ - void* pfnSPI4_Handler; /* 20 FLEXCOM 4 */ - void* pfnTWI4_Handler; /* 20 FLEXCOM 4 */ - void* pfnUSART5_Handler; /* 21 FLEXCOM 5 */ - void* pfnSPI5_Handler; /* 21 FLEXCOM 5 */ - void* pfnTWI5_Handler; /* 21 FLEXCOM 5 */ - void* pfnUSART6_Handler; /* 22 FLEXCOM 6 */ - void* pfnSPI6_Handler; /* 22 FLEXCOM 6 */ - void* pfnTWI6_Handler; /* 22 FLEXCOM 6 */ - void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ - void* pfnADC_Handler; /* 29 Analog To Digital Converter */ - void* pfnARM_Handler; /* 30 FPU */ - void* pvReserved31; - void* pvReserved32; - void* pvReserved33; - void* pvReserved34; - void* pvReserved35; - void* pvReserved36; - void* pvReserved37; - void* pvReserved38; - void* pvReserved39; - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pvReserved45; - void* pvReserved46; - void* pfnUHP_Handler; /* 47 USB OHCI */ - void* pfnUDP_Handler; /* 48 USB Device FS */ - void* pvReserved49; /* */ - void* pvReserved50; /* */ - void* pvReserved51; /* */ - void* pvReserved52; /* */ - void* pvReserved53; /* */ - void* pvReserved54; /* */ - void* pvReserved55; /* */ - void* pvReserved56; /* */ - void* pvReserved57; /* */ - void* pvReserved58; /* */ - void* pvReserved59; /* */ - void* pvReserved60; /* */ - void* pvReserved61; /* */ - void* pvReserved62; /* */ - void* pvReserved63; /* UHP */ - void* pvReserved64; /* UDP */ - void* pvReserved65; /* CRCCU */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ADC_Handler ( void ); -void ARM_Handler ( void ); -void EFC_Handler ( void ); -void I2SC0_Handler ( void ); -void I2SC1_Handler ( void ); -void MEM2MEM_Handler ( void ); -void PDMIC0_Handler ( void ); -void PDMIC1_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PMC_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SPI0_Handler ( void ); -void SPI1_Handler ( void ); -void SPI2_Handler ( void ); -void SPI3_Handler ( void ); -void SPI4_Handler ( void ); -void SPI5_Handler ( void ); -void SPI6_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TWI0_Handler ( void ); -void TWI1_Handler ( void ); -void TWI2_Handler ( void ); -void TWI3_Handler ( void ); -void TWI4_Handler ( void ); -void TWI5_Handler ( void ); -void TWI6_Handler ( void ); -void UDP_Handler ( void ); -void UHP_Handler ( void ); -void USART0_Handler ( void ); -void USART1_Handler ( void ); -void USART2_Handler ( void ); -void USART3_Handler ( void ); -void USART4_Handler ( void ); -void USART5_Handler ( void ); -void USART6_Handler ( void ); -void WDT_Handler ( void ); - -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0001 /**< SAMG55G18 core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAMG55G18 does provide a MPU */ -#define __FPU_PRESENT 1 /**< SAMG55G18 does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAMG55G18 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samg55.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55G18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G18_api Peripheral Software API */ -/*@{*/ - -#include "comp_adc.h" -#include "comp_chipid.h" -#include "comp_cmcc.h" -#include "comp_crccu.h" -#include "comp_efc.h" -#include "comp_flexcom.h" -#include "comp_gpbr.h" -#include "comp_i2sc.h" -#include "comp_matrix.h" -#include "comp_mem2mem.h" -#include "comp_pdc.h" -#include "comp_pdmic.h" -#include "comp_pio.h" -#include "comp_pmc.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_rtt.h" -#include "comp_spi.h" -#include "comp_supc.h" -#include "comp_tc.h" -#include "comp_twi.h" -#include "comp_twihs.h" -#include "comp_udp.h" -#include "comp_usart.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAMG55G18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G18_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_i2sc0.h" -#include "ins_i2sc1.h" -#include "ins_flexcom5.h" -#include "ins_usart5.h" -#include "ins_spi5.h" -#include "ins_twi5.h" -#include "ins_flexcom0.h" -#include "ins_usart0.h" -#include "ins_spi0.h" -#include "ins_twi0.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_flexcom3.h" -#include "ins_usart3.h" -#include "ins_spi3.h" -#include "ins_twi3.h" -#include "ins_flexcom4.h" -#include "ins_usart4.h" -#include "ins_spi4.h" -#include "ins_twi4.h" -#include "ins_flexcom1.h" -#include "ins_usart1.h" -#include "ins_spi1.h" -#include "ins_twi1.h" -#include "ins_flexcom2.h" -#include "ins_usart2.h" -#include "ins_spi2.h" -#include "ins_twi2.h" -#include "ins_mem2mem.h" -#include "ins_pdmic0.h" -#include "ins_pdmic1.h" -#include "ins_flexcom7.h" -#include "ins_adc.h" -#include "ins_cmcc.h" -#include "ins_flexcom6.h" -#include "ins_usart6.h" -#include "ins_spi6.h" -#include "ins_twi6.h" -#include "ins_udp.h" -#include "ins_crccu.h" -#include "ins_uhp.h" -#include "ins_matrix.h" -#include "ins_pmc.h" -#include "ins_chipid.h" -#include "ins_efc.h" -#include "ins_pioa.h" -#include "ins_piob.h" -#include "ins_rstc.h" -#include "ins_supc.h" -#include "ins_rtt.h" -#include "ins_wdt.h" -#include "ins_rtc.h" -#include "ins_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAMG55G18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G18_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_USART0 ( 8) /**< \brief FLEXCOM 0 (USART0) */ -#define ID_SPI0 ( 8) /**< \brief FLEXCOM 0 (SPI0) */ -#define ID_TWI0 ( 8) /**< \brief FLEXCOM 0 (TWI0) */ -#define ID_USART1 ( 9) /**< \brief FLEXCOM 1 (USART1) */ -#define ID_SPI1 ( 9) /**< \brief FLEXCOM 1 (SPI1) */ -#define ID_TWI1 ( 9) /**< \brief FLEXCOM 1 (TWI1) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */ -#define ID_USART2 (14) /**< \brief FLEXCOM2 (USART2) */ -#define ID_SPI2 (14) /**< \brief FLEXCOM2 (SPI2) */ -#define ID_TWI2 (14) /**< \brief FLEXCOM2 (TWI2) */ -#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */ -#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */ -#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */ -#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */ -#define ID_USART3 (19) /**< \brief FLEXCOM3 (USART3) */ -#define ID_SPI3 (19) /**< \brief FLEXCOM3 (SPI3) */ -#define ID_TWI3 (19) /**< \brief FLEXCOM3 (TWI3) */ -#define ID_USART4 (20) /**< \brief FLEXCOM4 (USART4) */ -#define ID_SPI4 (20) /**< \brief FLEXCOM4 (SPI4) */ -#define ID_TWI4 (20) /**< \brief FLEXCOM4 (TWI4) */ -#define ID_USART5 (21) /**< \brief FLEXCOM5 (USART5) */ -#define ID_SPI5 (21) /**< \brief FLEXCOM5 (SPI5) */ -#define ID_TWI5 (21) /**< \brief FLEXCOM5 (TWI5) */ -#define ID_USART6 (22) /**< \brief FLEXCOM6 (USART6) */ -#define ID_SPI6 (22) /**< \brief FLEXCOM6 (SPI6) */ -#define ID_TWI6 (22) /**< \brief FLEXCOM6 (TWI6) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_ARM (30) /**< \brief FPU (ARM) */ -#define ID_UHP (47) /**< \brief USB OHCI (UHP) */ -#define ID_UDP (48) /**< \brief USB Device FS (UDP) */ -#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */ - -#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAMG55G18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G18_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define FLEXCOM7 (0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */ -#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP (0x4004C000U) /**< \brief (UHP ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ -#else -#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 ((Twihs *)0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define FLEXCOM7 ((Flexcom *)0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */ -#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP ((Uhp *)0x4004C000U) /**< \brief (UHP ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAMG55G18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G18_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio_samg55g18.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAMG55G18 */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x40000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (512u) -#define IFLASH_NB_OF_LOCK_BITS (32u) -#define IRAM_SIZE (0x28000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAMG55G18 */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3E03FUL) -#define CHIP_CIDR (0x244709E0UL) -#define CHIP_EXID (0x0UL) -#define NB_CH_ADC (8UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAMG55G18 */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL) -#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) - - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (5U) - -/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAMG55G18_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55g19.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55g19.h deleted file mode 100644 index 811cf1f8b85..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55g19.h +++ /dev/null @@ -1,662 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55G19_ -#define _SAMG55G19_ - -/** \addtogroup SAMG55G19_definitions SAMG55G19 definitions - This file defines all structures and symbols for SAMG55G19: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAMG55G19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G19_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMG55G19 specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAMG55G19 Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAMG55G19 Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAMG55G19 Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAMG55G19 Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAMG55G19 Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAMG55G19 Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAMG55G19 Enhanced Flash Controller (EFC) */ - FLEXCOM0_IRQn = 8, /**< 8 SAMG55G19 FLEXCOM 0 (FLEXCOM0) */ - FLEXCOM1_IRQn = 9, /**< 9 SAMG55G19 FLEXCOM 1 (FLEXCOM1) */ - PIOA_IRQn = 11, /**< 11 SAMG55G19 Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAMG55G19 Parallel I/O Controller B (PIOB) */ - PDMIC0_IRQn = 13, /**< 13 SAMG55G19 PDM 0 (PDMIC0) */ - FLEXCOM2_IRQn = 14, /**< 14 SAMG55G19 FLEXCOM2 (FLEXCOM2) */ - MEM2MEM_IRQn = 15, /**< 15 SAMG55G19 MEM2MEM (MEM2MEM) */ - I2SC0_IRQn = 16, /**< 16 SAMG55G19 I2SC0 (I2SC0) */ - I2SC1_IRQn = 17, /**< 17 SAMG55G19 I2SC1 (I2SC1) */ - PDMIC1_IRQn = 18, /**< 18 SAMG55G19 PDM 1 (PDMIC1) */ - FLEXCOM3_IRQn = 19, /**< 19 SAMG55G19 FLEXCOM3 (FLEXCOM3) */ - FLEXCOM4_IRQn = 20, /**< 20 SAMG55G19 FLEXCOM4 (FLEXCOM4) */ - FLEXCOM5_IRQn = 21, /**< 21 SAMG55G19 FLEXCOM5 (FLEXCOM5) */ - FLEXCOM6_IRQn = 22, /**< 22 SAMG55G19 FLEXCOM6 (FLEXCOM6) */ - TC0_IRQn = 23, /**< 23 SAMG55G19 Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 SAMG55G19 Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 SAMG55G19 Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 SAMG55G19 Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 SAMG55G19 Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 SAMG55G19 Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 SAMG55G19 Analog To Digital Converter (ADC) */ - ARM_IRQn = 30, /**< 30 SAMG55G19 FPU (ARM) */ - WKUP0_IRQn = 31, /**< 31 SAMG55G19 External interrupt 0 (WKUP0) */ - WKUP1_IRQn = 32, /**< 32 SAMG55G19 External interrupt 1 (WKUP1) */ - WKUP2_IRQn = 33, /**< 33 SAMG55G19 External interrupt 2 (WKUP2) */ - WKUP3_IRQn = 34, /**< 34 SAMG55G19 External interrupt 3 (WKUP3) */ - WKUP4_IRQn = 35, /**< 35 SAMG55G19 External interrupt 4 (WKUP4) */ - WKUP5_IRQn = 36, /**< 36 SAMG55G19 External interrupt 5 (WKUP5) */ - WKUP6_IRQn = 37, /**< 37 SAMG55G19 External interrupt 6 (WKUP6) */ - WKUP7_IRQn = 38, /**< 38 SAMG55G19 External interrupt 7 (WKUP7) */ - WKUP8_IRQn = 39, /**< 39 SAMG55G19 External interrupt 8 (WKUP8) */ - WKUP9_IRQn = 40, /**< 40 SAMG55G19 External interrupt 9 (WKUP9) */ - WKUP10_IRQn = 41, /**< 41 SAMG55G19 External interrupt 10 (WKUP10) */ - WKUP11_IRQn = 42, /**< 42 SAMG55G19 External interrupt 11 (WKUP11) */ - WKUP12_IRQn = 43, /**< 43 SAMG55G19 External interrupt 12 (WKUP12) */ - WKUP13_IRQn = 44, /**< 44 SAMG55G19 External interrupt 13 (WKUP13) */ - WKUP14_IRQn = 45, /**< 45 SAMG55G19 External interrupt 14 (WKUP14) */ - WKUP15_IRQn = 46, /**< 46 SAMG55G19 External interrupt 15 (WKUP15) */ - UHP_IRQn = 47, /**< 47 SAMG55G19 USB OHCI (UHP) */ - UDP_IRQn = 48, /**< 48 SAMG55G19 USB Device FS (UDP) */ - CRCCU_IRQn = 49, /**< 49 SAMG55G19 CRCCU */ - PERIPH_COUNT_IRQn = 50 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */ - void* pvReserved7; - void* pfnFLEXCOM0_Handler; /* 8 FLEXCOM 0 */ - void* pfnFLEXCOM1_Handler; /* 9 FLEXCOM 1 */ - void* pvReserved10; - void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ - void* pfnPDMIC0_Handler; /* 13 PDM 0 */ - void* pfnFLEXCOM2_Handler; /* 14 FLEXCOM 2 */ - void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */ - void* pfnI2SC0_Handler; /* 16 I2SC0 */ - void* pfnI2SC1_Handler; /* 17 I2SC1 */ - void* pfnPDMIC1_Handler; /* 18 PDM 1 */ - void* pfnFLEXCOM3_Handler; /* 19 FLEXCOM 3 */ - void* pfnFLEXCOM4_Handler; /* 20 FLEXCOM 4 */ - void* pfnFLEXCOM5_Handler; /* 21 FLEXCOM 5 */ - void* pfnFLEXCOM6_Handler; /* 22 FLEXCOM 6 */ - void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ - void* pfnADC_Handler; /* 29 Analog To Digital Converter */ - void* pfnARM_Handler; /* 30 FPU */ - void* pvReserved31; - void* pvReserved32; - void* pvReserved33; - void* pvReserved34; - void* pvReserved35; - void* pvReserved36; - void* pvReserved37; - void* pvReserved38; - void* pvReserved39; - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pvReserved45; - void* pvReserved46; - void* pfnUHP_Handler; /* 47 USB OHCI */ - void* pfnUDP_Handler; /* 48 USB Device FS */ - void* pfnCRCCU_Handler; /*49 CRCCU Device */ - void* pvReserved50; /* */ - void* pvReserved51; /* */ - void* pvReserved52; /* */ - void* pvReserved53; /* */ - void* pvReserved54; /* */ - void* pvReserved55; /* */ - void* pvReserved56; /* */ - void* pvReserved57; /* */ - void* pvReserved58; /* */ - void* pvReserved59; /* */ - void* pvReserved60; /* */ - void* pvReserved61; /* */ - void* pvReserved62; /* */ - void* pvReserved63; /* UHP */ - void* pvReserved64; /* UDP */ - void* pvReserved65; /* CRCCU */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ADC_Handler ( void ); -void ARM_Handler ( void ); -void CRCCU_Handler ( void ); -void EFC_Handler ( void ); -void I2SC0_Handler ( void ); -void I2SC1_Handler ( void ); -void MEM2MEM_Handler ( void ); -void PDMIC0_Handler ( void ); -void PDMIC1_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PMC_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void UDP_Handler ( void ); -void UHP_Handler ( void ); -void FLEXCOM0_Handler ( void ); -void FLEXCOM1_Handler ( void ); -void FLEXCOM2_Handler ( void ); -void FLEXCOM3_Handler ( void ); -void FLEXCOM4_Handler ( void ); -void FLEXCOM5_Handler ( void ); -void FLEXCOM6_Handler ( void ); -void WDT_Handler ( void ); -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0001 /**< SAMG55G19 core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAMG55G19 does provide a MPU */ -#define __FPU_PRESENT 1 /**< SAMG55G19 does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAMG55G19 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samg55.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55G19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G19_api Peripheral Software API */ -/*@{*/ - -#include "comp_adc.h" -#include "comp_chipid.h" -#include "comp_cmcc.h" -#include "comp_crccu.h" -#include "comp_efc.h" -#include "comp_flexcom.h" -#include "comp_gpbr.h" -#include "comp_i2sc.h" -#include "comp_matrix.h" -#include "comp_mem2mem.h" -#include "comp_pdc.h" -#include "comp_pdmic.h" -#include "comp_pio.h" -#include "comp_pmc.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_rtt.h" -#include "comp_spi.h" -#include "comp_supc.h" -#include "comp_tc.h" -#include "comp_twi.h" -#include "comp_udp.h" -#include "comp_uhp.h" -#include "comp_usart.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAMG55G19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G19_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_i2sc0.h" -#include "ins_i2sc1.h" -#include "ins_flexcom5.h" -#include "ins_usart5.h" -#include "ins_spi5.h" -#include "ins_twi5.h" -#include "ins_flexcom0.h" -#include "ins_usart0.h" -#include "ins_spi0.h" -#include "ins_twi0.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_flexcom3.h" -#include "ins_usart3.h" -#include "ins_spi3.h" -#include "ins_twi3.h" -#include "ins_flexcom4.h" -#include "ins_usart4.h" -#include "ins_spi4.h" -#include "ins_twi4.h" -#include "ins_flexcom1.h" -#include "ins_usart1.h" -#include "ins_spi1.h" -#include "ins_twi1.h" -#include "ins_flexcom2.h" -#include "ins_usart2.h" -#include "ins_spi2.h" -#include "ins_twi2.h" -#include "ins_mem2mem.h" -#include "ins_pdmic0.h" -#include "ins_pdmic1.h" -#include "ins_adc.h" -#include "ins_cmcc.h" -#include "ins_flexcom6.h" -#include "ins_usart6.h" -#include "ins_spi6.h" -#include "ins_twi6.h" -#include "ins_udp.h" -#include "ins_crccu.h" -#include "ins_uhp.h" -#include "ins_matrix.h" -#include "ins_pmc.h" -#include "ins_chipid.h" -#include "ins_efc.h" -#include "ins_pioa.h" -#include "ins_piob.h" -#include "ins_rstc.h" -#include "ins_supc.h" -#include "ins_rtt.h" -#include "ins_wdt.h" -#include "ins_rtc.h" -#include "ins_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAMG55G19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G19_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_FLEXCOM0 ( 8) /**< \brief FLEXCOM0 */ -#define ID_FLEXCOM1 ( 9) /**< \brief FLEXCOM1 */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */ -#define ID_FLEXCOM2 (14) /**< \brief FLEXCOM2 */ -#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */ -#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */ -#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */ -#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */ -#define ID_FLEXCOM3 (19) /**< \brief FLEXCOM3 */ -#define ID_FLEXCOM4 (20) /**< \brief FLEXCOM4 */ -#define ID_FLEXCOM5 (21) /**< \brief FLEXCOM5 */ -#define ID_FLEXCOM6 (22) /**< \brief FLEXCOM6 */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_ARM (30) /**< \brief FPU (ARM) */ -#define ID_UHP (47) /**< \brief USB OHCI (UHP) */ -#define ID_UDP (48) /**< \brief USB Device FS (UDP) */ -#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */ - -#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAMG55G19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G19_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP (0x20400000U) /**< \brief (UHP ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ -#else -#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 ((Twi *)0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP ((Uhp *)0x20400000U) /**< \brief (UHP ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAMG55G19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55G19_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio_samg55g19.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAMG55G19 */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x80000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (1024u) -#define IFLASH_NB_OF_LOCK_BITS (64u) -#define IRAM_SIZE (0x28000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAMG55G19 */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3E03FUL) -#define CHIP_CIDR (0x24470AE0UL) -#define CHIP_EXID (0x0UL) -#define NB_CH_ADC (8UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAMG55G19 */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL) -#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) - - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (5U) - -/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAMG55G19_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55j18.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55j18.h deleted file mode 100644 index fc1be312f4b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55j18.h +++ /dev/null @@ -1,747 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55J18_ -#define _SAMG55J18_ - -/** \addtogroup SAMG55J18_definitions SAMG55J18 definitions - This file defines all structures and symbols for SAMG55J18: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAMG55J18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J18_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMG55J18 specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAMG55J18 Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAMG55J18 Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAMG55J18 Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAMG55J18 Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAMG55J18 Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAMG55J18 Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAMG55J18 Enhanced Flash Controller (EFC) */ - USART7_IRQn = 7, /**< 7 SAMG55J18 FLEXCOM 7 (USART7) */ - SPI7_IRQn = 7, /**< 7 SAMG55J18 FLEXCOM 7 (SPI7) */ - TWI7_IRQn = 7, /**< 7 SAMG55J18 FLEXCOM 7 (TWI7) */ - USART0_IRQn = 8, /**< 8 SAMG55J18 FLEXCOM 0 (USART0) */ - SPI0_IRQn = 8, /**< 8 SAMG55J18 FLEXCOM 0 (SPI0) */ - TWI0_IRQn = 8, /**< 8 SAMG55J18 FLEXCOM 0 (TWI0) */ - USART1_IRQn = 9, /**< 9 SAMG55J18 FLEXCOM 1 (USART1) */ - SPI1_IRQn = 9, /**< 8 SAMG55J18 FLEXCOM 1 (SPI1) */ - TWI1_IRQn = 9, /**< 8 SAMG55J18 FLEXCOM 1 (TWI1) */ - PIOA_IRQn = 11, /**< 11 SAMG55J18 Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAMG55J18 Parallel I/O Controller B (PIOB) */ - PDMIC0_IRQn = 13, /**< 13 SAMG55J18 PDM 0 (PDMIC0) */ - USART2_IRQn = 14, /**< 14 SAMG55J18 FLEXCOM2 (USART2) */ - SPI2_IRQn = 14, /**< 14 SAMG55J18 FLEXCOM 2 (SPI2) */ - TWI2_IRQn = 14, /**< 14 SAMG55J18 FLEXCOM 2 (TWI2) */ - MEM2MEM_IRQn = 15, /**< 15 SAMG55J18 MEM2MEM (MEM2MEM) */ - I2SC0_IRQn = 16, /**< 16 SAMG55J18 I2SC0 (I2SC0) */ - I2SC1_IRQn = 17, /**< 17 SAMG55J18 I2SC1 (I2SC1) */ - PDMIC1_IRQn = 18, /**< 18 SAMG55J18 PDM 1 (PDMIC1) */ - USART3__IRQn = 19, /**< 19 SAMG55J18 FLEXCOM3 (USART3) */ - SPI3_IRQn = 19, /**< 19 SAMG55J18 FLEXCOM 3 (SPI3) */ - TWI3_IRQn = 19, /**< 19 SAMG55J18 FLEXCOM 3 (TWI3) */ - USART4_IRQn = 20, /**< 20 SAMG55J18 FLEXCOM4 (USART4) */ - SPI4_IRQn = 20, /**< 8 SAMG55J18 FLEXCOM 4 (SPI4) */ - TWI4_IRQn = 20, /**< 8 SAMG55J18 FLEXCOM 4 (TWI4) */ - USART5_IRQn = 21, /**< 21 SAMG55J18 FLEXCOM5 (USART5) */ - SPI5_IRQn = 21, /**< 8 SAMG55J18 FLEXCOM 5 (SPI5) */ - TWI5_IRQn = 21, /**< 8 SAMG55J18 FLEXCOM 5 (TWI5) */ - USART6_IRQn = 22, /**< 22 SAMG55J18 FLEXCOM6 (USART6) */ - SPI6_IRQn = 22, /**< 22 SAMG55J18 FLEXCOM 6 (SPI6) */ - TWI6_IRQn = 22, /**< 22 SAMG55J18 FLEXCOM 6 (TWI6) */ - TC0_IRQn = 23, /**< 23 SAMG55J18 Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 SAMG55J18 Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 SAMG55J18 Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 SAMG55J18 Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 SAMG55J18 Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 SAMG55J18 Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 SAMG55J18 Analog To Digital Converter (ADC) */ - ARM_IRQn = 30, /**< 30 SAMG55J18 FPU (ARM) */ - WKUP0_IRQn = 31, /**< 31 SAMG55J18 External interrupt 0 (WKUP0) */ - WKUP1_IRQn = 32, /**< 32 SAMG55J18 External interrupt 1 (WKUP1) */ - WKUP2_IRQn = 33, /**< 33 SAMG55J18 External interrupt 2 (WKUP2) */ - WKUP3_IRQn = 34, /**< 34 SAMG55J18 External interrupt 3 (WKUP3) */ - WKUP4_IRQn = 35, /**< 35 SAMG55J18 External interrupt 4 (WKUP4) */ - WKUP5_IRQn = 36, /**< 36 SAMG55J18 External interrupt 5 (WKUP5) */ - WKUP6_IRQn = 37, /**< 37 SAMG55J18 External interrupt 6 (WKUP6) */ - WKUP7_IRQn = 38, /**< 38 SAMG55J18 External interrupt 7 (WKUP7) */ - WKUP8_IRQn = 39, /**< 39 SAMG55J18 External interrupt 8 (WKUP8) */ - WKUP9_IRQn = 40, /**< 40 SAMG55J18 External interrupt 9 (WKUP9) */ - WKUP10_IRQn = 41, /**< 41 SAMG55J18 External interrupt 10 (WKUP10) */ - WKUP11_IRQn = 42, /**< 42 SAMG55J18 External interrupt 11 (WKUP11) */ - WKUP12_IRQn = 43, /**< 43 SAMG55J18 External interrupt 12 (WKUP12) */ - WKUP13_IRQn = 44, /**< 44 SAMG55J18 External interrupt 13 (WKUP13) */ - WKUP14_IRQn = 45, /**< 45 SAMG55J18 External interrupt 14 (WKUP14) */ - WKUP15_IRQn = 46, /**< 46 SAMG55J18 External interrupt 15 (WKUP15) */ - UHP_IRQn = 47, /**< 47 SAMG55J18 USB OHCI (UHP) */ - UDP_IRQn = 48, /**< 48 SAMG55J18 USB Device FS (UDP) */ - - PERIPH_COUNT_IRQn = 49 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */ - void* pfnUSART7_Handler; /* USART7 */ - void* pfnSPI7_Handler; /* SPI7 */ - void* pfnTWI7_Handler; /* TWI7 */ - void* pfnUSART0_Handler; /* 8 FLEXCOM 0 */ - void* pfnSPI0_Handler; /* 8 FLEXCOM 0 */ - void* pfnTWI0_Handler; /* 8 FLEXCOM 0 */ - void* pfnUSART1_Handler; /* 9 FLEXCOM 1 */ - void* pfnSPI1_Handler; /* 9 FLEXCOM 1 */ - void* pfnTWI1_Handler; /* 9 FLEXCOM 1 */ - void* pvReserved10; - void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ - void* pfnPDMIC0_Handler; /* 13 PDM 0 */ - void* pfnUSART2_Handler; /* 14 FLEXCOM 2 */ - void* pfnSPI2_Handler; /* 14 FLEXCOM 2 */ - void* pfnTWI2_Handler; /* 14 FLEXCOM 2 */ - void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */ - void* pfnI2SC0_Handler; /* 16 I2SC0 */ - void* pfnI2SC1_Handler; /* 17 I2SC1 */ - void* pfnPDMIC1_Handler; /* 18 PDM 1 */ - void* pfnUSART3_Handler; /* 19 FLEXCOM 3 */ - void* pfnSPI3_Handler; /* 19 FLEXCOM 3 */ - void* pfnTWI3_Handler; /* 19 FLEXCOM 3 */ - void* pfnUSART4_Handler; /* 20 FLEXCOM 4 */ - void* pfnSPI4_Handler; /* 20 FLEXCOM 4 */ - void* pfnTWI4_Handler; /* 20 FLEXCOM 4 */ - void* pfnUSART5_Handler; /* 21 FLEXCOM 5 */ - void* pfnSPI5_Handler; /* 21 FLEXCOM 5 */ - void* pfnTWI5_Handler; /* 21 FLEXCOM 5 */ - void* pfnUSART6_Handler; /* 22 FLEXCOM 6 */ - void* pfnSPI6_Handler; /* 22 FLEXCOM 6 */ - void* pfnTWI6_Handler; /* 22 FLEXCOM 6 */ - void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ - void* pfnADC_Handler; /* 29 Analog To Digital Converter */ - void* pfnARM_Handler; /* 30 FPU */ - void* pvReserved31; - void* pvReserved32; - void* pvReserved33; - void* pvReserved34; - void* pvReserved35; - void* pvReserved36; - void* pvReserved37; - void* pvReserved38; - void* pvReserved39; - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pvReserved45; - void* pvReserved46; - void* pfnUHP_Handler; /* 47 USB OHCI */ - void* pfnUDP_Handler; /* 48 USB Device FS */ - void* pvReserved49; /* */ - void* pvReserved50; /* */ - void* pvReserved51; /* */ - void* pvReserved52; /* */ - void* pvReserved53; /* */ - void* pvReserved54; /* */ - void* pvReserved55; /* */ - void* pvReserved56; /* */ - void* pvReserved57; /* */ - void* pvReserved58; /* */ - void* pvReserved59; /* */ - void* pvReserved60; /* */ - void* pvReserved61; /* */ - void* pvReserved62; /* */ - void* pvReserved63; /* UHP */ - void* pvReserved64; /* UDP */ - void* pvReserved65; /* CRCCU */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ADC_Handler ( void ); -void ARM_Handler ( void ); -void EFC_Handler ( void ); -void I2SC0_Handler ( void ); -void I2SC1_Handler ( void ); -void MEM2MEM_Handler ( void ); -void PDMIC0_Handler ( void ); -void PDMIC1_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PMC_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SPI0_Handler ( void ); -void SPI1_Handler ( void ); -void SPI2_Handler ( void ); -void SPI3_Handler ( void ); -void SPI4_Handler ( void ); -void SPI5_Handler ( void ); -void SPI6_Handler ( void ); -void SPI7_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TWI0_Handler ( void ); -void TWI1_Handler ( void ); -void TWI2_Handler ( void ); -void TWI3_Handler ( void ); -void TWI4_Handler ( void ); -void TWI5_Handler ( void ); -void TWI6_Handler ( void ); -void TWI7_Handler ( void ); -void UDP_Handler ( void ); -void UHP_Handler ( void ); -void USART0_Handler ( void ); -void USART1_Handler ( void ); -void USART2_Handler ( void ); -void USART3_Handler ( void ); -void USART4_Handler ( void ); -void USART5_Handler ( void ); -void USART6_Handler ( void ); -void USART7_Handler ( void ); -void WDT_Handler ( void ); - -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0001 /**< SAMG55J18 core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAMG55J18 does provide a MPU */ -#define __FPU_PRESENT 1 /**< SAMG55J18 does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAMG55J18 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samg55.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55J18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J18_api Peripheral Software API */ -/*@{*/ - -#include "comp_adc.h" -#include "comp_chipid.h" -#include "comp_cmcc.h" -#include "comp_crccu.h" -#include "comp_efc.h" -#include "comp_flexcom.h" -#include "comp_gpbr.h" -#include "comp_i2sc.h" -#include "comp_matrix.h" -#include "comp_mem2mem.h" -#include "comp_pdc.h" -#include "comp_pdmic.h" -#include "comp_pio.h" -#include "comp_pmc.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_rtt.h" -#include "comp_spi.h" -#include "comp_supc.h" -#include "comp_tc.h" -#include "comp_twi.h" -#include "comp_twihs.h" -#include "comp_udp.h" -#include "comp_usart.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAMG55J18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J18_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_i2sc0.h" -#include "ins_i2sc1.h" -#include "ins_flexcom5.h" -#include "ins_usart5.h" -#include "ins_spi5.h" -#include "ins_twi5.h" -#include "ins_flexcom0.h" -#include "ins_usart0.h" -#include "ins_spi0.h" -#include "ins_twi0.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_flexcom3.h" -#include "ins_usart3.h" -#include "ins_spi3.h" -#include "ins_twi3.h" -#include "ins_flexcom4.h" -#include "ins_usart4.h" -#include "ins_spi4.h" -#include "ins_twi4.h" -#include "ins_flexcom1.h" -#include "ins_usart1.h" -#include "ins_spi1.h" -#include "ins_twi1.h" -#include "ins_flexcom2.h" -#include "ins_usart2.h" -#include "ins_spi2.h" -#include "ins_twi2.h" -#include "ins_mem2mem.h" -#include "ins_pdmic0.h" -#include "ins_pdmic1.h" -#include "ins_flexcom7.h" -#include "ins_usart7.h" -#include "ins_spi7.h" -#include "ins_twi7.h" -#include "ins_adc.h" -#include "ins_cmcc.h" -#include "ins_flexcom6.h" -#include "ins_usart6.h" -#include "ins_spi6.h" -#include "ins_twi6.h" -#include "ins_udp.h" -#include "ins_crccu.h" -#include "ins_uhp.h" -#include "ins_matrix.h" -#include "ins_pmc.h" -#include "ins_chipid.h" -#include "ins_efc.h" -#include "ins_pioa.h" -#include "ins_piob.h" -#include "ins_rstc.h" -#include "ins_supc.h" -#include "ins_rtt.h" -#include "ins_wdt.h" -#include "ins_rtc.h" -#include "ins_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAMG55J18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J18_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_USART7 ( 7) /**< \brief FLEXCOM 7 (USART7) */ -#define ID_SPI7 ( 7) /**< \brief FLEXCOM 7 (SPI7) */ -#define ID_TWI7 ( 7) /**< \brief FLEXCOM 7 (TWI7) */ -#define ID_USART0 ( 8) /**< \brief FLEXCOM 0 (USART0) */ -#define ID_SPI0 ( 8) /**< \brief FLEXCOM 0 (SPI0) */ -#define ID_TWI0 ( 8) /**< \brief FLEXCOM 0 (TWI0) */ -#define ID_USART1 ( 9) /**< \brief FLEXCOM 1 (USART1) */ -#define ID_SPI1 ( 9) /**< \brief FLEXCOM 1 (SPI1) */ -#define ID_TWI1 ( 9) /**< \brief FLEXCOM 1 (TWI1) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */ -#define ID_USART2 (14) /**< \brief FLEXCOM2 (USART2) */ -#define ID_SPI2 (14) /**< \brief FLEXCOM2 (SPI2) */ -#define ID_TWI2 (14) /**< \brief FLEXCOM2 (TWI2) */ -#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */ -#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */ -#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */ -#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */ -#define ID_USART3 (19) /**< \brief FLEXCOM3 (USART3) */ -#define ID_SPI3 (19) /**< \brief FLEXCOM3 (SPI3) */ -#define ID_TWI3 (19) /**< \brief FLEXCOM3 (TWI3) */ -#define ID_USART4 (20) /**< \brief FLEXCOM4 (USART4) */ -#define ID_SPI4 (20) /**< \brief FLEXCOM4 (SPI4) */ -#define ID_TWI4 (20) /**< \brief FLEXCOM4 (TWI4) */ -#define ID_USART5 (21) /**< \brief FLEXCOM5 (USART5) */ -#define ID_SPI5 (21) /**< \brief FLEXCOM5 (SPI5) */ -#define ID_TWI5 (21) /**< \brief FLEXCOM5 (TWI5) */ -#define ID_USART6 (22) /**< \brief FLEXCOM6 (USART6) */ -#define ID_SPI6 (22) /**< \brief FLEXCOM6 (SPI6) */ -#define ID_TWI6 (22) /**< \brief FLEXCOM6 (TWI6) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_ARM (30) /**< \brief FPU (ARM) */ -#define ID_UHP (47) /**< \brief USB OHCI (UHP) */ -#define ID_UDP (48) /**< \brief USB Device FS (UDP) */ -#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */ - -#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAMG55J18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J18_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define FLEXCOM7 (0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */ -#define USART7 (0x40034200U) /**< \brief (USART7 ) Base Address */ -#define PDC_USART7 (0x40034300U) /**< \brief (PDC_USART7 ) Base Address */ -#define SPI7 (0x40034400U) /**< \brief (SPI7 ) Base Address */ -#define PDC_SPI7 (0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */ -#define TWI7 (0x40034600U) /**< \brief (TWI7 ) Base Address */ -#define PDC_TWI7 (0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */ -#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP (0x4004C000U) /**< \brief (UHP ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ -#else -#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 ((Twihs *)0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define FLEXCOM7 ((Flexcom *)0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */ -#define USART7 ((Usart *)0x40034200U) /**< \brief (USART7 ) Base Address */ -#define PDC_USART7 ((Pdc *)0x40034300U) /**< \brief (PDC_USART7 ) Base Address */ -#define SPI7 ((Spi *)0x40034400U) /**< \brief (SPI7 ) Base Address */ -#define PDC_SPI7 ((Pdc *)0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */ -#define TWI7 ((Twi *)0x40034600U) /**< \brief (TWI7 ) Base Address */ -#define PDC_TWI7 ((Pdc *)0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */ -#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP ((Uhp *)0x4004C000U) /**< \brief (UHP ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAMG55J18 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J18_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio_samg55j18.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAMG55J18 */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x40000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (512u) -#define IFLASH_NB_OF_LOCK_BITS (32u) -#define IRAM_SIZE (0x28000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAMG55J18 */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3E03FUL) -#define CHIP_CIDR (0x245709E0UL) -#define CHIP_EXID (0x0UL) -#define NB_CH_ADC (8UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAMG55J18 */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL) -#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) - - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (5U) - -/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAMG55J18_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55j19.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55j19.h deleted file mode 100644 index ecf21d9f57b..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55j19.h +++ /dev/null @@ -1,683 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55J19_ -#define _SAMG55J19_ - -/** \addtogroup SAMG55J19_definitions SAMG55J19 definitions - This file defines all structures and symbols for SAMG55J19: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAMG55J19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J19_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMG55J19 specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAMG55J19 Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAMG55J19 Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAMG55J19 Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAMG55J19 Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAMG55J19 Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAMG55J19 Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAMG55J19 Enhanced Flash Controller (EFC) */ - FLEXCOM7_IRQn = 7, /**< 7 SAMG55J19 FLEXCOM 7 (FLEXCOM7) */ - FLEXCOM0_IRQn = 8, /**< 8 SAMG55J19 FLEXCOM 0 (FLEXCOM0) */ - FLEXCOM1_IRQn = 9, /**< 9 SAMG55J19 FLEXCOM 1 (FLEXCOM1) */ - PIOA_IRQn = 11, /**< 11 SAMG55J19 Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAMG55J19 Parallel I/O Controller B (PIOB) */ - PDMIC0_IRQn = 13, /**< 13 SAMG55J19 PDM 0 (PDMIC0) */ - FLEXCOM2_IRQn = 14, /**< 14 SAMG55J19 FLEXCOM2 (FLEXCOM2) */ - MEM2MEM_IRQn = 15, /**< 15 SAMG55J19 MEM2MEM (MEM2MEM) */ - I2SC0_IRQn = 16, /**< 16 SAMG55J19 I2SC0 (I2SC0) */ - I2SC1_IRQn = 17, /**< 17 SAMG55J19 I2SC1 (I2SC1) */ - PDMIC1_IRQn = 18, /**< 18 SAMG55J19 PDM 1 (PDMIC1) */ - FLEXCOM3_IRQn = 19, /**< 19 SAMG55J19 FLEXCOM3 (FLEXCOM3) */ - FLEXCOM4_IRQn = 20, /**< 20 SAMG55J19 FLEXCOM4 (FLEXCOM4) */ - FLEXCOM5_IRQn = 21, /**< 21 SAMG55J19 FLEXCOM5 (FLEXCOM5) */ - FLEXCOM6_IRQn = 22, /**< 22 SAMG55J19 FLEXCOM6 (FLEXCOM6) */ - TC0_IRQn = 23, /**< 23 SAMG55J19 Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 SAMG55J19 Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 SAMG55J19 Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 SAMG55J19 Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 SAMG55J19 Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 SAMG55J19 Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 SAMG55J19 Analog To Digital Converter (ADC) */ - ARM_IRQn = 30, /**< 30 SAMG55J19 FPU (ARM) */ - WKUP0_IRQn = 31, /**< 31 SAMG55J19 External interrupt 0 (WKUP0) */ - WKUP1_IRQn = 32, /**< 32 SAMG55J19 External interrupt 1 (WKUP1) */ - WKUP2_IRQn = 33, /**< 33 SAMG55J19 External interrupt 2 (WKUP2) */ - WKUP3_IRQn = 34, /**< 34 SAMG55J19 External interrupt 3 (WKUP3) */ - WKUP4_IRQn = 35, /**< 35 SAMG55J19 External interrupt 4 (WKUP4) */ - WKUP5_IRQn = 36, /**< 36 SAMG55J19 External interrupt 5 (WKUP5) */ - WKUP6_IRQn = 37, /**< 37 SAMG55J19 External interrupt 6 (WKUP6) */ - WKUP7_IRQn = 38, /**< 38 SAMG55J19 External interrupt 7 (WKUP7) */ - WKUP8_IRQn = 39, /**< 39 SAMG55J19 External interrupt 8 (WKUP8) */ - WKUP9_IRQn = 40, /**< 40 SAMG55J19 External interrupt 9 (WKUP9) */ - WKUP10_IRQn = 41, /**< 41 SAMG55J19 External interrupt 10 (WKUP10) */ - WKUP11_IRQn = 42, /**< 42 SAMG55J19 External interrupt 11 (WKUP11) */ - WKUP12_IRQn = 43, /**< 43 SAMG55J19 External interrupt 12 (WKUP12) */ - WKUP13_IRQn = 44, /**< 44 SAMG55J19 External interrupt 13 (WKUP13) */ - WKUP14_IRQn = 45, /**< 45 SAMG55J19 External interrupt 14 (WKUP14) */ - WKUP15_IRQn = 46, /**< 46 SAMG55J19 External interrupt 15 (WKUP15) */ - UHP_IRQn = 47, /**< 47 SAMG55J19 USB OHCI (UHP) */ - UDP_IRQn = 48, /**< 48 SAMG55J19 USB Device FS (UDP) */ - CRCCU_IRQn = 49, /**< 49 SAMG55G19 CRCCU */ - PERIPH_COUNT_IRQn = 50 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */ - void* pfnFLEXCOM7_Handler; /* FLEXCOM7 */ - void* pfnFLEXCOM0_Handler; /* 8 FLEXCOM 0 */ - void* pfnFLEXCOM1_Handler; /* 9 FLEXCOM 1 */ - void* pvReserved10; - void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ - void* pfnPDMIC0_Handler; /* 13 PDM 0 */ - void* pfnFLEXCOM2_Handler; /* 14 FLEXCOM 2 */ - void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */ - void* pfnI2SC0_Handler; /* 16 I2SC0 */ - void* pfnI2SC1_Handler; /* 17 I2SC1 */ - void* pfnPDMIC1_Handler; /* 18 PDM 1 */ - void* pfnFLEXCOM3_Handler; /* 19 FLEXCOM 3 */ - void* pfnFLEXCOM4_Handler; /* 20 FLEXCOM 4 */ - void* pfnFLEXCOM5_Handler; /* 21 FLEXCOM 5 */ - void* pfnFLEXCOM6_Handler; /* 22 FLEXCOM 6 */ - void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ - void* pfnADC_Handler; /* 29 Analog To Digital Converter */ - void* pfnARM_Handler; /* 30 FPU */ - void* pvReserved31; - void* pvReserved32; - void* pvReserved33; - void* pvReserved34; - void* pvReserved35; - void* pvReserved36; - void* pvReserved37; - void* pvReserved38; - void* pvReserved39; - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pvReserved45; - void* pvReserved46; - void* pfnUHP_Handler; /* 47 USB OHCI */ - void* pfnUDP_Handler; /* 48 USB Device FS */ - void* pfnCRCCU_Handler; /*49 CRCCU Device */ - void* pvReserved50; /* */ - void* pvReserved51; /* */ - void* pvReserved52; /* */ - void* pvReserved53; /* */ - void* pvReserved54; /* */ - void* pvReserved55; /* */ - void* pvReserved56; /* */ - void* pvReserved57; /* */ - void* pvReserved58; /* */ - void* pvReserved59; /* */ - void* pvReserved60; /* */ - void* pvReserved61; /* */ - void* pvReserved62; /* */ - void* pvReserved63; /* UHP */ - void* pvReserved64; /* UDP */ - void* pvReserved65; /* CRCCU */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ADC_Handler ( void ); -void ARM_Handler ( void ); -void CRCCU_Handler ( void ); -void EFC_Handler ( void ); -void I2SC0_Handler ( void ); -void I2SC1_Handler ( void ); -void MEM2MEM_Handler ( void ); -void PDMIC0_Handler ( void ); -void PDMIC1_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PMC_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void UDP_Handler ( void ); -void UHP_Handler ( void ); -void FLEXCOM0_Handler ( void ); -void FLEXCOM1_Handler ( void ); -void FLEXCOM2_Handler ( void ); -void FLEXCOM3_Handler ( void ); -void FLEXCOM4_Handler ( void ); -void FLEXCOM5_Handler ( void ); -void FLEXCOM6_Handler ( void ); -void FLEXCOM7_Handler ( void ); -void WDT_Handler ( void ); -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0001 /**< SAMG55J19 core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAMG55J19 does provide a MPU */ -#define __FPU_PRESENT 1 /**< SAMG55J19 does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAMG55J19 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samg55.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55J19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J19_api Peripheral Software API */ -/*@{*/ - -#include "comp_adc.h" -#include "comp_chipid.h" -#include "comp_cmcc.h" -#include "comp_crccu.h" -#include "comp_efc.h" -#include "comp_flexcom.h" -#include "comp_gpbr.h" -#include "comp_i2sc.h" -#include "comp_matrix.h" -#include "comp_mem2mem.h" -#include "comp_pdc.h" -#include "comp_pdmic.h" -#include "comp_pio.h" -#include "comp_pmc.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_rtt.h" -#include "comp_spi.h" -#include "comp_supc.h" -#include "comp_tc.h" -#include "comp_twi.h" -#include "comp_udp.h" -#include "comp_uhp.h" -#include "comp_usart.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAMG55J19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J19_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_i2sc0.h" -#include "ins_i2sc1.h" -#include "ins_flexcom5.h" -#include "ins_usart5.h" -#include "ins_spi5.h" -#include "ins_twi5.h" -#include "ins_flexcom0.h" -#include "ins_usart0.h" -#include "ins_spi0.h" -#include "ins_twi0.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_flexcom3.h" -#include "ins_usart3.h" -#include "ins_spi3.h" -#include "ins_twi3.h" -#include "ins_flexcom4.h" -#include "ins_usart4.h" -#include "ins_spi4.h" -#include "ins_twi4.h" -#include "ins_flexcom1.h" -#include "ins_usart1.h" -#include "ins_spi1.h" -#include "ins_twi1.h" -#include "ins_flexcom2.h" -#include "ins_usart2.h" -#include "ins_spi2.h" -#include "ins_twi2.h" -#include "ins_mem2mem.h" -#include "ins_pdmic0.h" -#include "ins_pdmic1.h" -#include "ins_flexcom7.h" -#include "ins_usart7.h" -#include "ins_spi7.h" -#include "ins_twi7.h" -#include "ins_adc.h" -#include "ins_cmcc.h" -#include "ins_flexcom6.h" -#include "ins_usart6.h" -#include "ins_spi6.h" -#include "ins_twi6.h" -#include "ins_udp.h" -#include "ins_crccu.h" -#include "ins_uhp.h" -#include "ins_matrix.h" -#include "ins_pmc.h" -#include "ins_chipid.h" -#include "ins_efc.h" -#include "ins_pioa.h" -#include "ins_piob.h" -#include "ins_rstc.h" -#include "ins_supc.h" -#include "ins_rtt.h" -#include "ins_wdt.h" -#include "ins_rtc.h" -#include "ins_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAMG55J19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J19_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_FLEXCOM7 ( 7) /**< \brief FLEXCOM7 */ -#define ID_FLEXCOM0 ( 8) /**< \brief FLEXCOM0 */ -#define ID_FLEXCOM1 ( 9) /**< \brief FLEXCOM1 */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */ -#define ID_FLEXCOM2 (14) /**< \brief FLEXCOM2 */ -#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */ -#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */ -#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */ -#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */ -#define ID_FLEXCOM3 (19) /**< \brief FLEXCOM3 */ -#define ID_FLEXCOM4 (20) /**< \brief FLEXCOM4 */ -#define ID_FLEXCOM5 (21) /**< \brief FLEXCOM5 */ -#define ID_FLEXCOM6 (22) /**< \brief FLEXCOM6 */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_ARM (30) /**< \brief FPU (ARM) */ -#define ID_UHP (47) /**< \brief USB OHCI (UHP) */ -#define ID_UDP (48) /**< \brief USB Device FS (UDP) */ -#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */ - -#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAMG55J19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J19_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define FLEXCOM7 (0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */ -#define USART7 (0x40034200U) /**< \brief (USART7 ) Base Address */ -#define PDC_USART7 (0x40034300U) /**< \brief (PDC_USART7 ) Base Address */ -#define SPI7 (0x40034400U) /**< \brief (SPI7 ) Base Address */ -#define PDC_SPI7 (0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */ -#define TWI7 (0x40034600U) /**< \brief (TWI7 ) Base Address */ -#define PDC_TWI7 (0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */ -#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP (0x20400000U) /**< \brief (UHP ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ -#else -#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 ((Twi *)0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define FLEXCOM7 ((Flexcom *)0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */ -#define USART7 ((Usart *)0x40034200U) /**< \brief (USART7 ) Base Address */ -#define PDC_USART7 ((Pdc *)0x40034300U) /**< \brief (PDC_USART7 ) Base Address */ -#define SPI7 ((Spi *)0x40034400U) /**< \brief (SPI7 ) Base Address */ -#define PDC_SPI7 ((Pdc *)0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */ -#define TWI7 ((Twi *)0x40034600U) /**< \brief (TWI7 ) Base Address */ -#define PDC_TWI7 ((Pdc *)0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */ -#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP ((Uhp *)0x20400000U) /**< \brief (UHP ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAMG55J19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55J19_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio_samg55j19.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAMG55J19 */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x80000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (1024u) -#define IFLASH_NB_OF_LOCK_BITS (64u) -#define IRAM_SIZE (0x28000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAMG55J19 */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3E03FUL) -#define CHIP_CIDR (0x24570AE0UL) -#define CHIP_EXID (0x0UL) -#define NB_CH_ADC (8UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAMG55J19 */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL) -#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) - - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (5U) - -/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAMG55J19_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55n19.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55n19.h deleted file mode 100644 index 570580c97f5..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55n19.h +++ /dev/null @@ -1,747 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMG55N19_ -#define _SAMG55N19_ - -/** \addtogroup SAMG55N19_definitions SAMG55N19 definitions - This file defines all structures and symbols for SAMG55N19: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAMG55N19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55N19_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMG55N19 specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAMG55N19 Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAMG55N19 Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAMG55N19 Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAMG55N19 Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAMG55N19 Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAMG55N19 Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAMG55N19 Enhanced Flash Controller (EFC) */ - USART7_IRQn = 48, /**< 48 SAMG55N19 FLEXCOM 7 (USART7) */ - SPI7_IRQn = 48, /**< 48 SAMG55N19 FLEXCOM 7 (SPI7) */ - TWI7_IRQn = 48, /**< 48 SAMG55N19 FLEXCOM 7 (TWI7) */ - USART0_IRQn = 8, /**< 8 SAMG55 FLEXCOM 0 (USART0) */ - SPI0_IRQn = 8, /**< 8 SAMG55 FLEXCOM 0 (SPI0) */ - TWI0_IRQn = 8, /**< 8 SAMG55 FLEXCOM 0 (TWI0) */ - USART1_IRQn = 9, /**< 9 SAMG55 FLEXCOM 1 (USART1) */ - SPI1_IRQn = 9, /**< 8 SAMG55 FLEXCOM 1 (SPI1) */ - TWI1_IRQn = 9, /**< 8 SAMG55 FLEXCOM 1 (TWI1) */ - PIOA_IRQn = 11, /**< 11 SAMG55N19 Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 SAMG55N19 Parallel I/O Controller B (PIOB) */ - PDMIC0_IRQn = 13, /**< 13 SAMG55N19 PDM 0 (PDMIC0) */ - USART2_IRQn = 14, /**< 14 SAMG55 FLEXCOM2 (USART2) */ - SPI2_IRQn = 14, /**< 14 SAMG55 FLEXCOM 2 (SPI2) */ - TWI2_IRQn = 14, /**< 14 SAMG55 FLEXCOM 2 (TWI2) */ - MEM2MEM_IRQn = 15, /**< 15 SAMG55N19 MEM2MEM (MEM2MEM) */ - I2SC0_IRQn = 16, /**< 16 SAMG55N19 I2SC0 (I2SC0) */ - I2SC1_IRQn = 17, /**< 17 SAMG55N19 I2SC1 (I2SC1) */ - PDMIC1_IRQn = 18, /**< 18 SAMG55N19 PDM 1 (PDMIC1) */ - USART3__IRQn = 19, /**< 19 SAMG55 FLEXCOM3 (USART3) */ - SPI3_IRQn = 19, /**< 19 SAMG55 FLEXCOM 3 (SPI3) */ - TWI3_IRQn = 19, /**< 19 SAMG55 FLEXCOM 3 (TWI3) */ - USART4_IRQn = 20, /**< 20 SAMG55 FLEXCOM4 (USART4) */ - SPI4_IRQn = 20, /**< 8 SAMG55 FLEXCOM 4 (SPI4) */ - TWI4_IRQn = 20, /**< 8 SAMG55 FLEXCOM 4 (TWI4) */ - USART5_IRQn = 21, /**< 21 SAMG55 FLEXCOM5 (USART5) */ - SPI5_IRQn = 21, /**< 8 SAMG55 FLEXCOM 5 (SPI5) */ - TWI5_IRQn = 21, /**< 8 SAMG55 FLEXCOM 5 (TWI5) */ - USART6_IRQn = 22, /**< 22 SAMG55 FLEXCOM6 (USART6) */ - SPI6_IRQn = 22, /**< 22 SAMG55 FLEXCOM 6 (SPI6) */ - TWI6_IRQn = 22, /**< 22 SAMG55 FLEXCOM 6 (TWI6) */ - TC0_IRQn = 23, /**< 23 SAMG55N19 Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 SAMG55N19 Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 SAMG55N19 Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 SAMG55N19 Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 SAMG55N19 Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 SAMG55N19 Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 SAMG55N19 Analog To Digital Converter (ADC) */ - ARM_IRQn = 30, /**< 30 SAMG55N19 FPU (ARM) */ - WKUP0_IRQn = 31, /**< 31 SAMG55 External interrupt 0 (WKUP0) */ - WKUP1_IRQn = 32, /**< 32 SAMG55 External interrupt 1 (WKUP1) */ - WKUP2_IRQn = 33, /**< 33 SAMG55 External interrupt 2 (WKUP2) */ - WKUP3_IRQn = 34, /**< 34 SAMG55 External interrupt 3 (WKUP3) */ - WKUP4_IRQn = 35, /**< 35 SAMG55 External interrupt 4 (WKUP4) */ - WKUP5_IRQn = 36, /**< 36 SAMG55 External interrupt 5 (WKUP5) */ - WKUP6_IRQn = 37, /**< 37 SAMG55 External interrupt 6 (WKUP6) */ - WKUP7_IRQn = 38, /**< 38 SAMG55 External interrupt 7 (WKUP7) */ - WKUP8_IRQn = 39, /**< 39 SAMG55 External interrupt 8 (WKUP8) */ - WKUP9_IRQn = 40, /**< 40 SAMG55 External interrupt 9 (WKUP9) */ - WKUP10_IRQn = 41, /**< 41 SAMG55 External interrupt 10 (WKUP10) */ - WKUP11_IRQn = 42, /**< 42 SAMG55 External interrupt 11 (WKUP11) */ - WKUP12_IRQn = 43, /**< 43 SAMG55 External interrupt 12 (WKUP12) */ - WKUP13_IRQn = 44, /**< 44 SAMG55 External interrupt 13 (WKUP13) */ - WKUP14_IRQn = 45, /**< 45 SAMG55 External interrupt 14 (WKUP14) */ - WKUP15_IRQn = 46, /**< 46 SAMG55 External interrupt 15 (WKUP15) */ - UHP_IRQn = 47, /**< 47 SAMG55N19 USB OHCI (UHP) */ - UDP_IRQn = 48, /**< 48 SAMG55N19 USB Device FS (UDP) */ - - PERIPH_COUNT_IRQn = 49 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors { - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */ - void* pfnUSART7_Handler; /* USART7 */ - void* pfnSPI7_Handler; /* SPI7 */ - void* pfnTWI7_Handler; /* TWI7 */ - void* pfnUSART0_Handler; /* 8 FLEXCOM 0 */ - void* pfnSPI0_Handler; /* 8 FLEXCOM 0 */ - void* pfnTWI0_Handler; /* 8 FLEXCOM 0 */ - void* pfnUSART1_Handler; /* 9 FLEXCOM 1 */ - void* pfnSPI1_Handler; /* 9 FLEXCOM 1 */ - void* pfnTWI1_Handler; /* 9 FLEXCOM 1 */ - void* pvReserved10; - void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ - void* pfnPDMIC0_Handler; /* 13 PDM 0 */ - void* pfnUSART2_Handler; /* 14 FLEXCOM 2 */ - void* pfnSPI2_Handler; /* 14 FLEXCOM 2 */ - void* pfnTWI2_Handler; /* 14 FLEXCOM 2 */ - void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */ - void* pfnI2SC0_Handler; /* 16 I2SC0 */ - void* pfnI2SC1_Handler; /* 17 I2SC1 */ - void* pfnPDMIC1_Handler; /* 18 PDM 1 */ - void* pfnUSART3_Handler; /* 19 FLEXCOM 3 */ - void* pfnSPI3_Handler; /* 19 FLEXCOM 3 */ - void* pfnTWI3_Handler; /* 19 FLEXCOM 3 */ - void* pfnUSART4_Handler; /* 20 FLEXCOM 4 */ - void* pfnSPI4_Handler; /* 20 FLEXCOM 4 */ - void* pfnTWI4_Handler; /* 20 FLEXCOM 4 */ - void* pfnUSART5_Handler; /* 21 FLEXCOM 5 */ - void* pfnSPI5_Handler; /* 21 FLEXCOM 5 */ - void* pfnTWI5_Handler; /* 21 FLEXCOM 5 */ - void* pfnUSART6_Handler; /* 22 FLEXCOM 6 */ - void* pfnSPI6_Handler; /* 22 FLEXCOM 6 */ - void* pfnTWI6_Handler; /* 22 FLEXCOM 6 */ - void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ - void* pfnADC_Handler; /* 29 Analog To Digital Converter */ - void* pfnARM_Handler; /* 30 FPU */ - void* pvReserved31; - void* pvReserved32; - void* pvReserved33; - void* pvReserved34; - void* pvReserved35; - void* pvReserved36; - void* pvReserved37; - void* pvReserved38; - void* pvReserved39; - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pvReserved45; - void* pvReserved46; - void* pfnUHP_Handler; /* 47 USB OHCI */ - void* pfnUDP_Handler; /* 48 USB Device FS */ - void* pvReserved49; /* */ - void* pvReserved50; /* */ - void* pvReserved51; /* */ - void* pvReserved52; /* */ - void* pvReserved53; /* */ - void* pvReserved54; /* */ - void* pvReserved55; /* */ - void* pvReserved56; /* */ - void* pvReserved57; /* */ - void* pvReserved58; /* */ - void* pvReserved59; /* */ - void* pvReserved60; /* */ - void* pvReserved61; /* */ - void* pvReserved62; /* */ - void* pvReserved63; /* UHP */ - void* pvReserved64; /* UDP */ - void* pvReserved65; /* CRCCU */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ADC_Handler ( void ); -void ARM_Handler ( void ); -void EFC_Handler ( void ); -void I2SC0_Handler ( void ); -void I2SC1_Handler ( void ); -void MEM2MEM_Handler ( void ); -void PDMIC0_Handler ( void ); -void PDMIC1_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PMC_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SPI0_Handler ( void ); -void SPI1_Handler ( void ); -void SPI2_Handler ( void ); -void SPI3_Handler ( void ); -void SPI4_Handler ( void ); -void SPI5_Handler ( void ); -void SPI6_Handler ( void ); -void SPI7_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TWI0_Handler ( void ); -void TWI1_Handler ( void ); -void TWI2_Handler ( void ); -void TWI3_Handler ( void ); -void TWI4_Handler ( void ); -void TWI5_Handler ( void ); -void TWI6_Handler ( void ); -void TWI7_Handler ( void ); -void UDP_Handler ( void ); -void UHP_Handler ( void ); -void USART0_Handler ( void ); -void USART1_Handler ( void ); -void USART2_Handler ( void ); -void USART3_Handler ( void ); -void USART4_Handler ( void ); -void USART5_Handler ( void ); -void USART6_Handler ( void ); -void USART7_Handler ( void ); -void WDT_Handler ( void ); - -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0001 /**< SAMG55N19 core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 1 /**< SAMG55N19 does provide a MPU */ -#define __FPU_PRESENT 1 /**< SAMG55N19 does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAMG55N19 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samg55.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55N19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55N19_api Peripheral Software API */ -/*@{*/ - -#include "comp_adc.h" -#include "comp_chipid.h" -#include "comp_cmcc.h" -#include "comp_crccu.h" -#include "comp_efc.h" -#include "comp_flexcom.h" -#include "comp_gpbr.h" -#include "comp_i2sc.h" -#include "comp_matrix.h" -#include "comp_mem2mem.h" -#include "comp_pdc.h" -#include "comp_pdmic.h" -#include "comp_pio.h" -#include "comp_pmc.h" -#include "comp_rstc.h" -#include "comp_rtc.h" -#include "comp_rtt.h" -#include "comp_spi.h" -#include "comp_supc.h" -#include "comp_tc.h" -#include "comp_twi.h" -#include "comp_twihs.h" -#include "comp_udp.h" -#include "comp_usart.h" -#include "comp_wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAMG55N19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55N19_reg Registers Access Definitions */ -/*@{*/ - -#include "ins_i2sc0.h" -#include "ins_i2sc1.h" -#include "ins_flexcom5.h" -#include "ins_usart5.h" -#include "ins_spi5.h" -#include "ins_twi5.h" -#include "ins_flexcom0.h" -#include "ins_usart0.h" -#include "ins_spi0.h" -#include "ins_twi0.h" -#include "ins_tc0.h" -#include "ins_tc1.h" -#include "ins_flexcom3.h" -#include "ins_usart3.h" -#include "ins_spi3.h" -#include "ins_twi3.h" -#include "ins_flexcom4.h" -#include "ins_usart4.h" -#include "ins_spi4.h" -#include "ins_twi4.h" -#include "ins_flexcom1.h" -#include "ins_usart1.h" -#include "ins_spi1.h" -#include "ins_twi1.h" -#include "ins_flexcom2.h" -#include "ins_usart2.h" -#include "ins_spi2.h" -#include "ins_twi2.h" -#include "ins_mem2mem.h" -#include "ins_pdmic0.h" -#include "ins_pdmic1.h" -#include "ins_flexcom7.h" -#include "ins_usart7.h" -#include "ins_spi7.h" -#include "ins_twi7.h" -#include "ins_adc.h" -#include "ins_cmcc.h" -#include "ins_flexcom6.h" -#include "ins_usart6.h" -#include "ins_spi6.h" -#include "ins_twi6.h" -#include "ins_udp.h" -#include "ins_crccu.h" -#include "ins_uhp.h" -#include "ins_matrix.h" -#include "ins_pmc.h" -#include "ins_chipid.h" -#include "ins_efc.h" -#include "ins_pioa.h" -#include "ins_piob.h" -#include "ins_rstc.h" -#include "ins_supc.h" -#include "ins_rtt.h" -#include "ins_wdt.h" -#include "ins_rtc.h" -#include "ins_gpbr.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAMG55N19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55N19_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_USART7 ( 7) /**< \brief FLEXCOM 7 (USART7) */ -#define ID_SPI7 ( 7) /**< \brief FLEXCOM 7 (SPI7) */ -#define ID_TWI7 ( 7) /**< \brief FLEXCOM 7 (TWI7) */ -#define ID_USART0 ( 8) /**< \brief FLEXCOM 0 (USART0) */ -#define ID_SPI0 ( 8) /**< \brief FLEXCOM 0 (SPI0) */ -#define ID_TWI0 ( 8) /**< \brief FLEXCOM 0 (TWI0) */ -#define ID_USART1 ( 9) /**< \brief FLEXCOM 1 (USART1) */ -#define ID_SPI1 ( 9) /**< \brief FLEXCOM 1 (SPI1) */ -#define ID_TWI1 ( 9) /**< \brief FLEXCOM 1 (TWI1) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */ -#define ID_USART2 (14) /**< \brief FLEXCOM2 (USART2) */ -#define ID_SPI2 (14) /**< \brief FLEXCOM2 (SPI2) */ -#define ID_TWI2 (14) /**< \brief FLEXCOM2 (TWI2) */ -#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */ -#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */ -#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */ -#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */ -#define ID_USART3 (19) /**< \brief FLEXCOM3 (USART3) */ -#define ID_SPI3 (19) /**< \brief FLEXCOM3 (SPI3) */ -#define ID_TWI3 (19) /**< \brief FLEXCOM3 (TWI3) */ -#define ID_USART4 (20) /**< \brief FLEXCOM4 (USART4) */ -#define ID_SPI4 (20) /**< \brief FLEXCOM4 (SPI4) */ -#define ID_TWI4 (20) /**< \brief FLEXCOM4 (TWI4) */ -#define ID_USART5 (21) /**< \brief FLEXCOM5 (USART5) */ -#define ID_SPI5 (21) /**< \brief FLEXCOM5 (SPI5) */ -#define ID_TWI5 (21) /**< \brief FLEXCOM5 (TWI5) */ -#define ID_USART6 (22) /**< \brief FLEXCOM6 (USART6) */ -#define ID_SPI6 (22) /**< \brief FLEXCOM6 (SPI6) */ -#define ID_TWI6 (22) /**< \brief FLEXCOM6 (TWI6) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_ARM (30) /**< \brief FPU (ARM) */ -#define ID_UHP (47) /**< \brief USB OHCI (UHP) */ -#define ID_UDP (48) /**< \brief USB Device FS (UDP) */ -#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */ - -#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAMG55N19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55N19_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define FLEXCOM7 (0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */ -#define USART7 (0x40034200U) /**< \brief (USART7 ) Base Address */ -#define PDC_USART7 (0x40034300U) /**< \brief (PDC_USART7 ) Base Address */ -#define SPI7 (0x40034400U) /**< \brief (SPI7 ) Base Address */ -#define PDC_SPI7 (0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */ -#define TWI7 (0x40034600U) /**< \brief (TWI7 ) Base Address */ -#define PDC_TWI7 (0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */ -#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP (0x4004C000U) /**< \brief (UHP ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ -#else -#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */ -#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */ -#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */ -#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */ -#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */ -#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */ -#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */ -#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */ -#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */ -#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */ -#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */ -#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */ -#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */ -#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */ -#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */ -#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ -#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */ -#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */ -#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */ -#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */ -#define TWI3 ((Twihs *)0x40018600U) /**< \brief (TWI3 ) Base Address */ -#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */ -#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */ -#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */ -#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */ -#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */ -#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */ -#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */ -#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */ -#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */ -#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */ -#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */ -#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */ -#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */ -#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */ -#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */ -#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */ -#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */ -#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */ -#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */ -#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */ -#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */ -#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */ -#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */ -#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */ -#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */ -#define FLEXCOM7 ((Flexcom *)0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */ -#define USART7 ((Usart *)0x40034200U) /**< \brief (USART7 ) Base Address */ -#define PDC_USART7 ((Pdc *)0x40034300U) /**< \brief (PDC_USART7 ) Base Address */ -#define SPI7 ((Spi *)0x40034400U) /**< \brief (SPI7 ) Base Address */ -#define PDC_SPI7 ((Pdc *)0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */ -#define TWI7 ((Twi *)0x40034600U) /**< \brief (TWI7 ) Base Address */ -#define PDC_TWI7 ((Pdc *)0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */ -#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */ -#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */ -#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */ -#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */ -#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */ -#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */ -#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */ -#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */ -#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */ -#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */ -#define UHP ((Uhp *)0x4004C000U) /**< \brief (UHP ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAMG55N19 */ -/* ************************************************************************** */ -/** \addtogroup SAMG55N19_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio_samg55n19.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAMG55N19 */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x80000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (1024u) -#define IFLASH_NB_OF_LOCK_BITS (64u) -#define IRAM_SIZE (0x28000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAMG55N19 */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3E03FUL) -#define CHIP_CIDR (0x24670AE0UL) -#define CHIP_EXID (0x0UL) -#define NB_CH_ADC (8UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAMG55N19 */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL) -#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) - - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (5U) - -/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAMG55N19_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/source/system_samg55.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/source/system_samg55.c deleted file mode 100644 index 7365490e109..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/source/system_samg55.c +++ /dev/null @@ -1,179 +0,0 @@ -/** - * \file - * - * \brief Provides the low-level initialization functions that called - * on chip startup. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "system_samg55.h" -#include "samg55.h" - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ - /* @endcond */ - - /* Clock Settings (120MHz) */ -#define SYS_BOARD_PLLAR (CKGR_PLLAR_MULA(0xe4eU) \ - | CKGR_PLLAR_PLLACOUNT(0x3fU) \ - | CKGR_PLLAR_PLLAEN(0x1U)) -#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK) - - /* Key to unlock MOR register */ -#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) - - /* External oscillator definition, to be overriden by application */ -#define CHIP_FREQ_XTAL_12M (12000000UL) - -#if (!defined CHIP_FREQ_XTAL) -# define CHIP_FREQ_XTAL CHIP_FREQ_XTAL_12M -#endif - - uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_8MHZ; - - /** - * \brief Setup the microcontroller system. - * Initialize the System and update the SystemFrequency variable. - */ - void SystemInit(void) -{ - /* Set FWS according to SYS_BOARD_MCKR configuration */ - EFC->EEFC_FMR = EEFC_FMR_FWS(8)|EEFC_FMR_CLOE; - - /* Initialize PLLA */ - PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; - while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { - } - - /* Switch to PLLA */ - PMC->PMC_MCKR = SYS_BOARD_MCKR; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { - } - - SystemCoreClock = CHIP_FREQ_CPU_MAX; -} - -void SystemCoreClockUpdate(void) -{ - /* Determine clock frequency according to clock register values */ - switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) { - case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ - if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) { - SystemCoreClock = CHIP_FREQ_XTAL_32K; - } else { - SystemCoreClock = CHIP_FREQ_SLCK_RC; - } - break; - case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ - if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) { - SystemCoreClock = CHIP_FREQ_XTAL; - } else { - SystemCoreClock = CHIP_FREQ_MAINCK_RC_8MHZ; - - switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_8_MHz: - break; - case CKGR_MOR_MOSCRCF_16_MHz: - SystemCoreClock *= 2U; - break; - case CKGR_MOR_MOSCRCF_24_MHz: - SystemCoreClock *= 3U; - break; - default: - break; - } - } - break; - case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ - if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) { - SystemCoreClock = CHIP_FREQ_XTAL_32K; - } else { - SystemCoreClock = CHIP_FREQ_SLCK_RC; - } - if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) { - SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> - CKGR_PLLAR_MULA_Pos) + 1U); - } - break; - default: - break; - } - - if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) { - SystemCoreClock /= 3U; - } else { - SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos); - } -} - -/** - * Initialize flash. - */ -void system_init_flash(uint32_t ul_clk) -{ - /* Set FWS for embedded Flash access according to operating frequency */ - if (ul_clk < CHIP_FREQ_FWS_0) { - EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE; - } else if (ul_clk < CHIP_FREQ_FWS_1) { - EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE; - } else if (ul_clk < CHIP_FREQ_FWS_2) { - EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE; - } else if (ul_clk < CHIP_FREQ_FWS_3) { - EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE; - } else if (ul_clk < CHIP_FREQ_FWS_4) { - EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE; - } else { - EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE; - } -} - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/* @endcond */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/source/system_samg55.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/source/system_samg55.h deleted file mode 100644 index 0befe15f37c..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/source/system_samg55.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * \file - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SYSTEM_SAMG55_H_INCLUDED -#define SYSTEM_SAMG55_H_INCLUDED - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ - /* @endcond */ - -#include - - extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - - /** - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ - void SystemInit(void); - - /** - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ - void SystemCoreClockUpdate(void); - - /** - * Initialize flash. - */ - void system_init_flash(uint32_t dw_clk); - - /* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/* @endcond */ - -#endif /* SYSTEM_SAMG55_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/compiler.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/compiler.h deleted file mode 100644 index 8687867dabf..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/compiler.h +++ /dev/null @@ -1,1180 +0,0 @@ -/** - * \file - * - * \brief Commonly used includes, types and macros. - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef UTILS_COMPILER_H -#define UTILS_COMPILER_H - -/** - * \defgroup group_sam_utils Compiler abstraction layer and code utilities - * - * Compiler abstraction layer and code utilities for AT91SAM. - * This module provides various abstraction layers and utilities to make code compatible between different compilers. - * - * \{ - */ -#include - -#if (defined __ICCARM__) -# include -#endif - -#include -#include "preprocessor.h" - -#include - -//_____ D E C L A R A T I O N S ____________________________________________ - -#ifndef __ASSEMBLY__ // Not defined for assembling. - -#include -#include -#include -#include - -#ifdef __ICCARM__ -/*! \name Compiler Keywords - * - * Port of some keywords from GCC to IAR Embedded Workbench. - */ -//! @{ -#define __asm__ asm -#define __inline__ inline -#define __volatile__ -//! @} - -#endif - -#define FUNC_PTR void * -/** - * \def UNUSED - * \brief Marking \a v as a unused parameter or value. - */ -#define UNUSED(v) (void)(v) - -/** - * \def unused - * \brief Marking \a v as a unused parameter or value. - */ -#define unused(v) do { (void)(v); } while(0) - -/** - * \def barrier - * \brief Memory barrier - */ -#define barrier() __DMB() - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union - * definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union - * definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - - -/** - * \brief Set aligned boundary. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif (defined __ICCARM__) -# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#endif - -/** - * \brief Set word-aligned boundary. - */ -#if (defined __GNUC__) || defined(__CC_ARM) -#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) -#elif (defined __ICCARM__) -#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) -#endif - -/** - * \def __always_inline - * \brief The function should always be inlined. - * - * This annotation instructs the compiler to ignore its inlining - * heuristics and inline the function no matter how big it thinks it - * becomes. - */ -#if defined(__CC_ARM) -# define __always_inline __forceinline -#elif (defined __GNUC__) -# define __always_inline inline __attribute__((__always_inline__)) -#elif (defined __ICCARM__) -# define __always_inline _Pragma("inline=forced") -#endif - -/** - * \def __no_inline - * \brief The function should not be inlined. - * - * This annotation instructs the compiler to ignore its inlining - * heuristics and not inline the function. - */ -#if defined(__CC_ARM) -# define __no_inline __attribute__((noinline)) -#elif (defined __GNUC__) -# define __no_inline __attribute__((__noinline__)) -#elif (defined __ICCARM__) -# define __no_inline _Pragma("inline=never") -#endif - -/*! \brief This macro is used to test fatal errors. - * - * The macro tests if the expression is false. If it is, a fatal error is - * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO - * is defined, a unit test version of the macro is used, to allow execution - * of further tests after a false expression. - * - * \param expr Expression to evaluate and supposed to be nonzero. - */ -#if defined(_ASSERT_ENABLE_) -# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO) -// Assert() is defined in unit_test/suite.h -# include "unit_test/suite.h" -# else -#undef TEST_SUITE_DEFINE_ASSERT_MACRO -# define Assert(expr) \ - {\ - if (!(expr)) while (true);\ - } -# endif -#else -# define Assert(expr) ((void) 0) -#endif - -/* Define WEAK attribute */ -#if defined ( __CC_ARM ) /* Keil µVision 4 */ -# define WEAK __attribute__ ((weak)) -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define WEAK __weak -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define WEAK __attribute__ ((weak)) -#endif - -/* Define NO_INIT attribute */ -#if defined ( __CC_ARM ) -# define NO_INIT __attribute__((zero_init)) -#elif defined ( __ICCARM__ ) -# define NO_INIT __no_init -#elif defined ( __GNUC__ ) -# define NO_INIT __attribute__((section(".no_init"))) -#endif - -/* Define RAMFUNC attribute */ -#if defined ( __CC_ARM ) /* Keil µVision 4 */ -# define RAMFUNC __attribute__ ((section(".ramfunc"))) -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define RAMFUNC __ramfunc -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define RAMFUNC __attribute__ ((section(".ramfunc"))) -#endif - -/* Define OPTIMIZE_HIGH attribute */ -#if defined ( __CC_ARM ) /* Keil µVision 4 */ -# define OPTIMIZE_HIGH _Pragma("O3") -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define OPTIMIZE_HIGH _Pragma("optimize=high") -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define OPTIMIZE_HIGH __attribute__((optimize(s))) -#endif - -#include "interrupt.h" - -/*! \name Usual Types - */ -//! @{ -typedef unsigned char Bool; //!< Boolean. -#ifndef __cplusplus -#if !defined(__bool_true_false_are_defined) -typedef unsigned char bool; //!< Boolean. -#endif -#endif -typedef int8_t S8 ; //!< 8-bit signed integer. -typedef uint8_t U8 ; //!< 8-bit unsigned integer. -typedef int16_t S16; //!< 16-bit signed integer. -typedef uint16_t U16; //!< 16-bit unsigned integer. -typedef uint16_t le16_t; -typedef uint16_t be16_t; -typedef int32_t S32; //!< 32-bit signed integer. -typedef uint32_t U32; //!< 32-bit unsigned integer. -typedef uint32_t le32_t; -typedef uint32_t be32_t; -typedef int64_t S64; //!< 64-bit signed integer. -typedef uint64_t U64; //!< 64-bit unsigned integer. -typedef float F32; //!< 32-bit floating-point number. -typedef double F64; //!< 64-bit floating-point number. -typedef uint32_t iram_size_t; -//! @} - - -/*! \name Status Types - */ -//! @{ -typedef bool Status_bool_t; //!< Boolean status. -typedef U8 Status_t; //!< 8-bit-coded status. -//! @} - - -/*! \name Aliasing Aggregate Types - */ -//! @{ - -//! 16-bit union. -typedef union { - S16 s16 ; - U16 u16 ; - S8 s8 [2]; - U8 u8 [2]; -} Union16; - -//! 32-bit union. -typedef union { - S32 s32 ; - U32 u32 ; - S16 s16[2]; - U16 u16[2]; - S8 s8 [4]; - U8 u8 [4]; -} Union32; - -//! 64-bit union. -typedef union { - S64 s64 ; - U64 u64 ; - S32 s32[2]; - U32 u32[2]; - S16 s16[4]; - U16 u16[4]; - S8 s8 [8]; - U8 u8 [8]; -} Union64; - -//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. -typedef union { - S64 *s64ptr; - U64 *u64ptr; - S32 *s32ptr; - U32 *u32ptr; - S16 *s16ptr; - U16 *u16ptr; - S8 *s8ptr ; - U8 *u8ptr ; -} UnionPtr; - -//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. -typedef union { - volatile S64 *s64ptr; - volatile U64 *u64ptr; - volatile S32 *s32ptr; - volatile U32 *u32ptr; - volatile S16 *s16ptr; - volatile U16 *u16ptr; - volatile S8 *s8ptr ; - volatile U8 *u8ptr ; -} UnionVPtr; - -//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. -typedef union { - const S64 *s64ptr; - const U64 *u64ptr; - const S32 *s32ptr; - const U32 *u32ptr; - const S16 *s16ptr; - const U16 *u16ptr; - const S8 *s8ptr ; - const U8 *u8ptr ; -} UnionCPtr; - -//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. -typedef union { - const volatile S64 *s64ptr; - const volatile U64 *u64ptr; - const volatile S32 *s32ptr; - const volatile U32 *u32ptr; - const volatile S16 *s16ptr; - const volatile U16 *u16ptr; - const volatile S8 *s8ptr ; - const volatile U8 *u8ptr ; -} UnionCVPtr; - -//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. -typedef struct { - S64 *s64ptr; - U64 *u64ptr; - S32 *s32ptr; - U32 *u32ptr; - S16 *s16ptr; - U16 *u16ptr; - S8 *s8ptr ; - U8 *u8ptr ; -} StructPtr; - -//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. -typedef struct { - volatile S64 *s64ptr; - volatile U64 *u64ptr; - volatile S32 *s32ptr; - volatile U32 *u32ptr; - volatile S16 *s16ptr; - volatile U16 *u16ptr; - volatile S8 *s8ptr ; - volatile U8 *u8ptr ; -} StructVPtr; - -//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. -typedef struct { - const S64 *s64ptr; - const U64 *u64ptr; - const S32 *s32ptr; - const U32 *u32ptr; - const S16 *s16ptr; - const U16 *u16ptr; - const S8 *s8ptr ; - const U8 *u8ptr ; -} StructCPtr; - -//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. -typedef struct { - const volatile S64 *s64ptr; - const volatile U64 *u64ptr; - const volatile S32 *s32ptr; - const volatile U32 *u32ptr; - const volatile S16 *s16ptr; - const volatile U16 *u16ptr; - const volatile S8 *s8ptr ; - const volatile U8 *u8ptr ; -} StructCVPtr; - -//! @} - -#endif // #ifndef __ASSEMBLY__ - -/*! \name Usual Constants - */ -//! @{ -#define DISABLE 0 -#define ENABLE 1 -#ifndef __cplusplus -#if !defined(__bool_true_false_are_defined) -#define false 0 -#define true 1 -#endif -#endif -#define PASS 0 -#define FAIL 1 -#define LOW 0 -#define HIGH 1 -//! @} - - -#ifndef __ASSEMBLY__ // not for assembling. - -//! \name Optimization Control -//@{ - -/** - * \def likely(exp) - * \brief The expression \a exp is likely to be true - */ -#ifndef likely -# define likely(exp) (exp) -#endif - -/** - * \def unlikely(exp) - * \brief The expression \a exp is unlikely to be true - */ -#ifndef unlikely -# define unlikely(exp) (exp) -#endif - -/** - * \def is_constant(exp) - * \brief Determine if an expression evaluates to a constant value. - * - * \param exp Any expression - * - * \return true if \a exp is constant, false otherwise. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define is_constant(exp) __builtin_constant_p(exp) -#else -# define is_constant(exp) (0) -#endif - -//! @} - -/*! \name Bit-Field Handling - */ -//! @{ - -/*! \brief Reads the bits of a value specified by a given bit-mask. - * - * \param value Value to read bits from. - * \param mask Bit-mask indicating bits to read. - * - * \return Read bits. - */ -#define Rd_bits( value, mask) ((value) & (mask)) - -/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue to write bits to. - * \param mask Bit-mask indicating bits to write. - * \param bits Bits to write. - * - * \return Resulting value with written bits. - */ -#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ - ((bits ) & (mask))) - -/*! \brief Tests the bits of a value specified by a given bit-mask. - * - * \param value Value of which to test bits. - * \param mask Bit-mask indicating bits to test. - * - * \return \c 1 if at least one of the tested bits is set, else \c 0. - */ -#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) - -/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue of which to clear bits. - * \param mask Bit-mask indicating bits to clear. - * - * \return Resulting value with cleared bits. - */ -#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) - -/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue of which to set bits. - * \param mask Bit-mask indicating bits to set. - * - * \return Resulting value with set bits. - */ -#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) - -/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue of which to toggle bits. - * \param mask Bit-mask indicating bits to toggle. - * - * \return Resulting value with toggled bits. - */ -#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) - -/*! \brief Reads the bit-field of a value specified by a given bit-mask. - * - * \param value Value to read a bit-field from. - * \param mask Bit-mask indicating the bit-field to read. - * - * \return Read bit-field. - */ -#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) - -/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue to write a bit-field to. - * \param mask Bit-mask indicating the bit-field to write. - * \param bitfield Bit-field to write. - * - * \return Resulting value with written bit-field. - */ -#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) - -//! @} - - -/*! \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - */ -//! @{ - -/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define clz(u) __builtin_clz(u) -#elif (defined __ICCARM__) -# define clz(u) __CLZ(u) -#else -# define clz(u) (((u) == 0) ? 32 : \ - ((u) & (1ul << 31)) ? 0 : \ - ((u) & (1ul << 30)) ? 1 : \ - ((u) & (1ul << 29)) ? 2 : \ - ((u) & (1ul << 28)) ? 3 : \ - ((u) & (1ul << 27)) ? 4 : \ - ((u) & (1ul << 26)) ? 5 : \ - ((u) & (1ul << 25)) ? 6 : \ - ((u) & (1ul << 24)) ? 7 : \ - ((u) & (1ul << 23)) ? 8 : \ - ((u) & (1ul << 22)) ? 9 : \ - ((u) & (1ul << 21)) ? 10 : \ - ((u) & (1ul << 20)) ? 11 : \ - ((u) & (1ul << 19)) ? 12 : \ - ((u) & (1ul << 18)) ? 13 : \ - ((u) & (1ul << 17)) ? 14 : \ - ((u) & (1ul << 16)) ? 15 : \ - ((u) & (1ul << 15)) ? 16 : \ - ((u) & (1ul << 14)) ? 17 : \ - ((u) & (1ul << 13)) ? 18 : \ - ((u) & (1ul << 12)) ? 19 : \ - ((u) & (1ul << 11)) ? 20 : \ - ((u) & (1ul << 10)) ? 21 : \ - ((u) & (1ul << 9)) ? 22 : \ - ((u) & (1ul << 8)) ? 23 : \ - ((u) & (1ul << 7)) ? 24 : \ - ((u) & (1ul << 6)) ? 25 : \ - ((u) & (1ul << 5)) ? 26 : \ - ((u) & (1ul << 4)) ? 27 : \ - ((u) & (1ul << 3)) ? 28 : \ - ((u) & (1ul << 2)) ? 29 : \ - ((u) & (1ul << 1)) ? 30 : \ - 31) -#endif - -/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define ctz(u) __builtin_ctz(u) -#else -# define ctz(u) ((u) & (1ul << 0) ? 0 : \ - (u) & (1ul << 1) ? 1 : \ - (u) & (1ul << 2) ? 2 : \ - (u) & (1ul << 3) ? 3 : \ - (u) & (1ul << 4) ? 4 : \ - (u) & (1ul << 5) ? 5 : \ - (u) & (1ul << 6) ? 6 : \ - (u) & (1ul << 7) ? 7 : \ - (u) & (1ul << 8) ? 8 : \ - (u) & (1ul << 9) ? 9 : \ - (u) & (1ul << 10) ? 10 : \ - (u) & (1ul << 11) ? 11 : \ - (u) & (1ul << 12) ? 12 : \ - (u) & (1ul << 13) ? 13 : \ - (u) & (1ul << 14) ? 14 : \ - (u) & (1ul << 15) ? 15 : \ - (u) & (1ul << 16) ? 16 : \ - (u) & (1ul << 17) ? 17 : \ - (u) & (1ul << 18) ? 18 : \ - (u) & (1ul << 19) ? 19 : \ - (u) & (1ul << 20) ? 20 : \ - (u) & (1ul << 21) ? 21 : \ - (u) & (1ul << 22) ? 22 : \ - (u) & (1ul << 23) ? 23 : \ - (u) & (1ul << 24) ? 24 : \ - (u) & (1ul << 25) ? 25 : \ - (u) & (1ul << 26) ? 26 : \ - (u) & (1ul << 27) ? 27 : \ - (u) & (1ul << 28) ? 28 : \ - (u) & (1ul << 29) ? 29 : \ - (u) & (1ul << 30) ? 30 : \ - (u) & (1ul << 31) ? 31 : \ - 32) -#endif - -//! @} - - -/*! \name Bit Reversing - */ -//! @{ - -/*! \brief Reverses the bits of \a u8. - * - * \param u8 U8 of which to reverse the bits. - * - * \return Value resulting from \a u8 with reversed bits. - */ -#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) - -/*! \brief Reverses the bits of \a u16. - * - * \param u16 U16 of which to reverse the bits. - * - * \return Value resulting from \a u16 with reversed bits. - */ -#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) - -/*! \brief Reverses the bits of \a u32. - * - * \param u32 U32 of which to reverse the bits. - * - * \return Value resulting from \a u32 with reversed bits. - */ -#define bit_reverse32(u32) __RBIT(u32) - -/*! \brief Reverses the bits of \a u64. - * - * \param u64 U64 of which to reverse the bits. - * - * \return Value resulting from \a u64 with reversed bits. - */ -#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\ - ((U64)bit_reverse32((U64)(u64)) << 32))) - -//! @} - - -/*! \name Alignment - */ -//! @{ - -/*! \brief Tests alignment of the number \a val with the \a n boundary. - * - * \param val Input value. - * \param n Boundary. - * - * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. - */ -#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) - -/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. - * - * \param val Input value. - * \param n Boundary. - * - * \return Alignment of the number \a val with respect to the \a n boundary. - */ -#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) - -/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. - * - * \param lval Input/output lvalue. - * \param n Boundary. - * \param alg Alignment. - * - * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. - */ -#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) - -/*! \brief Aligns the number \a val with the upper \a n boundary. - * - * \param val Input value. - * \param n Boundary. - * - * \return Value resulting from the number \a val aligned with the upper \a n boundary. - */ -#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) - -/*! \brief Aligns the number \a val with the lower \a n boundary. - * - * \param val Input value. - * \param n Boundary. - * - * \return Value resulting from the number \a val aligned with the lower \a n boundary. - */ -#define Align_down(val, n ) ( (val) & ~((n) - 1)) - -//! @} - - -/*! \name Mathematics - * - * The same considerations as for clz and ctz apply here but GCC does not - * provide built-in functions to access the assembly instructions abs, min and - * max and it does not produce them by itself in most cases, so two sets of - * macros are defined here: - * - Abs, Min and Max to apply to constant expressions (values known at - * compile time); - * - abs, min and max to apply to non-constant expressions (values unknown at - * compile time), abs is found in stdlib.h. - */ -//! @{ - -/*! \brief Takes the absolute value of \a a. - * - * \param a Input value. - * - * \return Absolute value of \a a. - * - * \note More optimized if only used with values known at compile time. - */ -#define Abs(a) (((a) < 0 ) ? -(a) : (a)) - -/*! \brief Takes the minimal value of \a a and \a b. - * - * \param a Input value. - * \param b Input value. - * - * \return Minimal value of \a a and \a b. - * - * \note More optimized if only used with values known at compile time. - */ -#define Min(a, b) (((a) < (b)) ? (a) : (b)) - -/*! \brief Takes the maximal value of \a a and \a b. - * - * \param a Input value. - * \param b Input value. - * - * \return Maximal value of \a a and \a b. - * - * \note More optimized if only used with values known at compile time. - */ -#define Max(a, b) (((a) > (b)) ? (a) : (b)) - -// abs() is already defined by stdlib.h - -/*! \brief Takes the minimal value of \a a and \a b. - * - * \param a Input value. - * \param b Input value. - * - * \return Minimal value of \a a and \a b. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define min(a, b) Min(a, b) - -/*! \brief Takes the maximal value of \a a and \a b. - * - * \param a Input value. - * \param b Input value. - * - * \return Maximal value of \a a and \a b. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define max(a, b) Max(a, b) - -//! @} - - -/*! \brief Calls the routine at address \a addr. - * - * It generates a long call opcode. - * - * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if - * it is invoked from the CPU supervisor mode. - * - * \param addr Address of the routine to call. - * - * \note It may be used as a long jump opcode in some special cases. - */ -#define Long_call(addr) ((*(void (*)(void))(addr))()) - - -/*! \name MCU Endianism Handling - * ARM is MCU little endianism. - */ -//! @{ -#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. -#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. - -#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. -#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. -#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32. -#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32. -#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32. -#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32. -#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. -#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. -#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. -#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. - -#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. -#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. -#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64. -#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64. -#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64. -#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64. -#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. -#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. -#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. -#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. -#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64. -#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64. -#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64. -#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64. -#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64. -#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64. -#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64. -#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64. -#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. -#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. -#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. -#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. -#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. -#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. -#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. -#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. - -#define BE16(x) Swap16(x) -#define LE16(x) (x) - -#define le16_to_cpu(x) (x) -#define cpu_to_le16(x) (x) -#define LE16_TO_CPU(x) (x) -#define CPU_TO_LE16(x) (x) - -#define be16_to_cpu(x) Swap16(x) -#define cpu_to_be16(x) Swap16(x) -#define BE16_TO_CPU(x) Swap16(x) -#define CPU_TO_BE16(x) Swap16(x) - -#define le32_to_cpu(x) (x) -#define cpu_to_le32(x) (x) -#define LE32_TO_CPU(x) (x) -#define CPU_TO_LE32(x) (x) - -#define be32_to_cpu(x) swap32(x) -#define cpu_to_be32(x) swap32(x) -#define BE32_TO_CPU(x) swap32(x) -#define CPU_TO_BE32(x) swap32(x) -//! @} - - -/*! \name Endianism Conversion - * - * The same considerations as for clz and ctz apply here but GCC's - * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when - * applied to constant expressions, so two sets of macros are defined here: - * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known - * at compile time); - * - swap16, swap32 and swap64 to apply to non-constant expressions (values - * unknown at compile time). - */ -//! @{ - -/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ - ((U16)(u16) << 8))) - -/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ - ((U32)Swap16((U32)(u32)) << 16))) - -/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). - * - * \param u64 U64 of which to toggle the endianism. - * - * \return Value resulting from \a u64 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ - ((U64)Swap32((U64)(u64)) << 32))) - -/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define swap16(u16) Swap16(u16) - -/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#if (defined __GNUC__) -# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32))) -#else -# define swap32(u32) Swap32(u32) -#endif - -/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). - * - * \param u64 U64 of which to toggle the endianism. - * - * \return Value resulting from \a u64 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#if (defined __GNUC__) -# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64))) -#else -# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ - ((U64)swap32((U64)(u64)) << 32))) -#endif - -//! @} - - -/*! \name Target Abstraction - */ -//! @{ - -#define _GLOBEXT_ extern //!< extern storage-class specifier. -#define _CONST_TYPE_ const //!< const type qualifier. -#define _MEM_TYPE_SLOW_ //!< Slow memory type. -#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. -#define _MEM_TYPE_FAST_ //!< Fast memory type. - -typedef U8 Byte; //!< 8-bit unsigned integer. - -#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. -#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. -#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. -#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. - -#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. -#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. -#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. -#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. -#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. -#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. -#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. -#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. - -//! @} - -/** - * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using - * integer arithmetic. - * - * \param a An integer - * \param b Another integer - * - * \return (\a a / \a b) rounded up to the nearest integer. - */ -#define div_ceil(a, b) (((a) + (b) - 1) / (b)) - -#endif // #ifndef __ASSEMBLY__ - - -#if defined(__ICCARM__) -#define SHORTENUM __packed -#elif defined(__GNUC__) -#define SHORTENUM __attribute__((packed)) -#endif - -/* No operation */ -#if defined(__ICCARM__) -#define nop() __no_operation() -#elif defined(__GNUC__) -#define nop() (__NOP()) -#endif - -#define FLASH_DECLARE(x) const x -#define FLASH_EXTERN(x) extern const x -#define PGM_READ_BYTE(x) *(x) -#define PGM_READ_WORD(x) *(x) -#define PGM_READ_DWORD(x) *(x) -#define MEMCPY_ENDIAN memcpy -#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len)) - -/*Defines the Flash Storage for the request and response of MAC*/ -#define CMD_ID_OCTET (0) - -/* Converting of values from CPU endian to little endian. */ -#define CPU_ENDIAN_TO_LE16(x) (x) -#define CPU_ENDIAN_TO_LE32(x) (x) -#define CPU_ENDIAN_TO_LE64(x) (x) - -/* Converting of values from little endian to CPU endian. */ -#define LE16_TO_CPU_ENDIAN(x) (x) -#define LE32_TO_CPU_ENDIAN(x) (x) -#define LE64_TO_CPU_ENDIAN(x) (x) - -/* Converting of constants from little endian to CPU endian. */ -#define CLE16_TO_CPU_ENDIAN(x) (x) -#define CLE32_TO_CPU_ENDIAN(x) (x) -#define CLE64_TO_CPU_ENDIAN(x) (x) - -/* Converting of constants from CPU endian to little endian. */ -#define CCPU_ENDIAN_TO_LE16(x) (x) -#define CCPU_ENDIAN_TO_LE32(x) (x) -#define CCPU_ENDIAN_TO_LE64(x) (x) - -#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src)) -#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src)) - -/** - * @brief Converts a 64-Bit value into a 8 Byte array - * - * @param[in] value 64-Bit value - * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value - * @ingroup apiPalApi - */ -static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) -{ - uint8_t val_index = 0; - - while (val_index < 8) { - data[val_index++] = value & 0xFF; - value = value >> 8; - } -} - -/** - * @brief Converts a 16-Bit value into a 2 Byte array - * - * @param[in] value 16-Bit value - * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value - * @ingroup apiPalApi - */ -static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* Converts a 16-Bit value into a 2 Byte array */ -static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* Converts a 16-Bit value into a 2 Byte array */ -static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* - * @brief Converts a 2 Byte array into a 16-Bit value - * - * @param data Specifies the pointer to the 2 Byte array - * - * @return 16-Bit value - * @ingroup apiPalApi - */ -static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) -{ - return (data[0] | ((uint16_t)data[1] << 8)); -} - -/* Converts a 8 Byte array into a 32-Bit value */ -static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) -{ - union { - uint32_t u32; - uint8_t u8[8]; - } long_addr; - uint8_t index; - for (index = 0; index < 4; index++) { - long_addr.u8[index] = *data++; - } - return long_addr.u32; -} - -/** - * @brief Converts a 8 Byte array into a 64-Bit value - * - * @param data Specifies the pointer to the 8 Byte array - * - * @return 64-Bit value - * @ingroup apiPalApi - */ -static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) -{ - union { - uint64_t u64; - uint8_t u8[8]; - } long_addr; - - uint8_t val_index; - - for (val_index = 0; val_index < 8; val_index++) { - long_addr.u8[val_index] = *data++; - } - - return long_addr.u64; -} -/** - * \} - */ - -#endif /* UTILS_COMPILER_H */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/header_files/io.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/header_files/io.h deleted file mode 100644 index a79c6463103..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/header_files/io.h +++ /dev/null @@ -1,157 +0,0 @@ -/** - * \file - * - * \brief Arch file for SAM. - * - * This file defines common SAM series. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAM_IO_ -#define _SAM_IO_ - -/* SAM3 family */ - -/* SAM3S series */ -#if (SAM3S) -# if (SAM3S8 || SAM3SD8) -# include "sam3s8.h" -# else -# include "sam3s.h" -# endif -#endif - -/* SAM3U series */ -#if (SAM3U) -# include "sam3u.h" -#endif - -/* SAM3N series */ -#if (SAM3N) -# include "sam3n.h" -#endif - -/* SAM3XA series */ -#if (SAM3XA) -# include "sam3xa.h" -#endif - -/* SAM4S series */ -#if (SAM4S) -# include "sam4s.h" -#endif - -/* SAM4L series */ -#if (SAM4L) -# include "sam4l.h" -#endif - -/* SAM4E series */ -#if (SAM4E) -# include "sam4e.h" -#endif - -/* SAM4N series */ -#if (SAM4N) -# include "sam4n.h" -#endif - -/* SAM4C series */ -#if (SAM4C) -# include "sam4c.h" -#endif - -/* SAM4CM series */ -#if (SAM4CM) -# if (SAM4CMP32 || SAM4CMS32) -# include "sam4cm32.h" -# else -# include "sam4cm.h" -# endif -#endif - -/* SAM4CP series */ -#if (SAM4CP) -# include "sam4cp.h" -#endif - -/* SAMG51 series */ -#if (SAMG51) -# include "samg51.h" -#endif - -/* SAMG53 series */ -#if (SAMG53) -# include "samg53.h" -#endif - -/* SAMG54 series */ -#if (SAMG54) -# include "samg54.h" -#endif - -/* SAMG55 series */ -#if (SAMG55) -# include "samg55.h" -#endif - -/* SAMV71 series */ -#if (SAMV71) -# include "samv71.h" -#endif - -/* SAMV70 series */ -#if (SAMV70) -# include "samv70.h" -#endif - -/* SAME70 series */ -#if (SAME70) -# include "same70.h" -#endif - -/* SAMS70 series */ -#if (SAMS70) -# include "sams70.h" -#endif - -#endif /* _SAM_IO_ */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/mrepeat.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/mrepeat.h deleted file mode 100644 index 5a2017be99e..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/mrepeat.h +++ /dev/null @@ -1,339 +0,0 @@ -/** - * \file - * - * \brief Preprocessor macro repeating utils. - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _MREPEAT_H_ -#define _MREPEAT_H_ - -/** - * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat - * - * \ingroup group_sam_utils - * - * \{ - */ - -#include "preprocessor.h" - - -//! Maximal number of repetitions supported by MREPEAT. -#define MREPEAT_LIMIT 256 - -/*! \brief Macro repeat. - * - * This macro represents a horizontal repetition construct. - * - * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. - * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with - * the current repetition number and the auxiliary data argument. - * \param data Auxiliary data passed to macro. - * - * \return macro(0, data) macro(1, data) ... macro(count - 1, data) - */ -#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) - -#define MREPEAT0( macro, data) -#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) -#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) -#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) -#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) -#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) -#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) -#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) -#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) -#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) -#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) -#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) -#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) -#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) -#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) -#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) -#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) -#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) -#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) -#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) -#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) -#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) -#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) -#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) -#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) -#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) -#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) -#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) -#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) -#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) -#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) -#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) -#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) -#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) -#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) -#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) -#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) -#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) -#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) -#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) -#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) -#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) -#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) -#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) -#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) -#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) -#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) -#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) -#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) -#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) -#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) -#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) -#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) -#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) -#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) -#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) -#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) -#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) -#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) -#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) -#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) -#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) -#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) -#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) -#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) -#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) -#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) -#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) -#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) -#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) -#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) -#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) -#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) -#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) -#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) -#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) -#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) -#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) -#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) -#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) -#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) -#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) -#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) -#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) -#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) -#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) -#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) -#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) -#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) -#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) -#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) -#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) -#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) -#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) -#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) -#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) -#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) -#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) -#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) -#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) -#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) -#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) -#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) -#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) -#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) -#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) -#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) -#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) -#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) -#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) -#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) -#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) -#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) -#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) -#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) -#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) -#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) -#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) -#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) -#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) -#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) -#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) -#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) -#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) -#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) -#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) -#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) -#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) -#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) -#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) -#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) -#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) -#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) -#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) -#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) -#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) -#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) -#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) -#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) -#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) -#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) -#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) -#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) -#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) -#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) -#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) -#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) -#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) -#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) -#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) -#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) -#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) -#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) -#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) -#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) -#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) -#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) -#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) -#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) -#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) -#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) -#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) -#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) -#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) -#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) -#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) -#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) -#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) -#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) -#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) -#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) -#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) -#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) -#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) -#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) -#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) -#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) -#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) -#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) -#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) -#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) -#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) -#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) -#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) -#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) -#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) -#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) -#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) -#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) -#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) -#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) -#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) -#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) -#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) -#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) -#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) -#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) -#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) -#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) -#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) -#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) -#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) -#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) -#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) -#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) -#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) -#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) -#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) -#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) -#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) -#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) -#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) -#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) -#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) -#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) -#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) -#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) -#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) -#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) -#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) -#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) -#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) -#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) -#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) -#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) -#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) -#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) -#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) -#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) -#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) -#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) -#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) -#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) -#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) -#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) -#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) -#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) -#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) -#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) -#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) -#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) -#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) -#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) -#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) -#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) -#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) -#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) -#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) -#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) -#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) -#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) -#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) -#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) -#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) -#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) -#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) -#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) - -/** - * \} - */ - -#endif // _MREPEAT_H_ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/preprocessor.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/preprocessor.h deleted file mode 100644 index 184c03ae710..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/preprocessor.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief Preprocessor utils. - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _PREPROCESSOR_H_ -#define _PREPROCESSOR_H_ - -#include "tpaste.h" -#include "stringz.h" -#include "mrepeat.h" - - -#endif // _PREPROCESSOR_H_ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/stringz.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/stringz.h deleted file mode 100644 index b914b734893..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/stringz.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * \file - * - * \brief Preprocessor stringizing utils. - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _STRINGZ_H_ -#define _STRINGZ_H_ - -/** - * \defgroup group_sam_utils_stringz Preprocessor - Stringize - * - * \ingroup group_sam_utils - * - * \{ - */ - -/*! \brief Stringize. - * - * Stringize a preprocessing token, this token being allowed to be \#defined. - * - * May be used only within macros with the token passed as an argument if the token is \#defined. - * - * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) - * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to - * writing "A0". - */ -#define STRINGZ(x) #x - -/*! \brief Absolute stringize. - * - * Stringize a preprocessing token, this token being allowed to be \#defined. - * - * No restriction of use if the token is \#defined. - * - * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is - * equivalent to writing "A0". - */ -#define ASTRINGZ(x) STRINGZ(x) - -/** - * \} - */ - -#endif // _STRINGZ_H_ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/tpaste.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/tpaste.h deleted file mode 100644 index f8ec44a41de..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/tpaste.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - * \file - * - * \brief Preprocessor token pasting utils. - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _TPASTE_H_ -#define _TPASTE_H_ - -/** - * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste - * - * \ingroup group_sam_utils - * - * \{ - */ - -/*! \name Token Paste - * - * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. - * - * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. - * - * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by - * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is - * equivalent to writing U32. - */ -//! @{ -#define TPASTE2( a, b) a##b -#define TPASTE3( a, b, c) a##b##c -#define TPASTE4( a, b, c, d) a##b##c##d -#define TPASTE5( a, b, c, d, e) a##b##c##d##e -#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f -#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g -#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h -#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i -#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j -//! @} - -/*! \name Absolute Token Paste - * - * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. - * - * No restriction of use if the tokens are \#defined. - * - * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined - * as 32 is equivalent to writing U32. - */ -//! @{ -#define ATPASTE2( a, b) TPASTE2( a, b) -#define ATPASTE3( a, b, c) TPASTE3( a, b, c) -#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) -#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) -#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) -#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) -#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) -#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) -#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) -//! @} - -/** - * \} - */ - -#endif // _TPASTE_H_ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/status_codes.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/status_codes.h deleted file mode 100644 index f83167af14d..00000000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/status_codes.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * \file - * - * \brief Status code definitions. - * - * This file defines various status codes returned by functions, - * indicating success or failure as well as what kind of failure. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef STATUS_CODES_H_INCLUDED -#define STATUS_CODES_H_INCLUDED - -/* Note: this is a local workaround to avoid a pre-processor clash due to the - * lwIP macro ERR_TIMEOUT. */ -#if defined(__LWIP_ERR_H__) && defined(ERR_TIMEOUT) -#if (ERR_TIMEOUT != -3) - -/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT - * macro is set to the correct value. Note that it is highly improbable that - * this value ever changes in lwIP. */ -#error ASF developers: check lwip err.h new value for ERR_TIMEOUT -#endif -#undef ERR_TIMEOUT -#endif - -/** - * Status code that may be returned by shell commands and protocol - * implementations. - * - * \note Any change to these status codes and the corresponding - * message strings is strictly forbidden. New codes can be added, - * however, but make sure that any message string tables are updated - * at the same time. - */ -enum status_code { - STATUS_OK = 0, //!< Success - STATUS_ERR_BUSY = 0x19, - STATUS_ERR_DENIED = 0x1C, - STATUS_ERR_TIMEOUT = 0x12, - ERR_IO_ERROR = -1, //!< I/O error - ERR_FLUSHED = -2, //!< Request flushed from queue - ERR_TIMEOUT = -3, //!< Operation timed out - ERR_BAD_DATA = -4, //!< Data integrity check failed - ERR_PROTOCOL = -5, //!< Protocol error - ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device - ERR_NO_MEMORY = -7, //!< Insufficient memory - ERR_INVALID_ARG = -8, //!< Invalid argument - ERR_BAD_ADDRESS = -9, //!< Bad address - ERR_BUSY = -10, //!< Resource is busy - ERR_BAD_FORMAT = -11, //!< Data format not recognized - ERR_NO_TIMER = -12, //!< No timer available - ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running - ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running - ERR_ABORTED = -15, //!< Operation aborted by user - /** - * \brief Operation in progress - * - * This status code is for driver-internal use when an operation - * is currently being performed. - * - * \note Drivers should never return this status code to any - * callers. It is strictly for internal use. - */ - OPERATION_IN_PROGRESS = -128, -}; - -typedef enum status_code status_code_t; - -#if defined(__LWIP_ERR_H__) -#define ERR_TIMEOUT -3 -#endif - -#endif /* STATUS_CODES_H_INCLUDED */ diff --git a/targets/TARGET_Atmel/common/utils/interrupt.h b/targets/TARGET_Atmel/common/utils/interrupt.h deleted file mode 100644 index 9db6f7d55bf..00000000000 --- a/targets/TARGET_Atmel/common/utils/interrupt.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef UTILS_INTERRUPT_H -#define UTILS_INTERRUPT_H - -#include - -#if XMEGA || MEGA || TINY -# include "interrupt/interrupt_avr8.h" -#elif UC3 -# include "interrupt/interrupt_avr32.h" -#elif SAM -# include "interrupt/interrupt_sam_nvic.h" -#else -# error Unsupported device. -#endif - -/** - * \defgroup interrupt_group Global interrupt management - * - * This is a driver for global enabling and disabling of interrupts. - * - * @{ - */ - -#if defined(__DOXYGEN__) -/** - * \def CONFIG_INTERRUPT_FORCE_INTC - * \brief Force usage of the ASF INTC driver - * - * Predefine this symbol when preprocessing to force the use of the ASF INTC driver. - * This is useful to ensure compatibility across compilers and shall be used only when required - * by the application needs. - */ -# define CONFIG_INTERRUPT_FORCE_INTC -#endif - -//! \name Global interrupt flags -//@{ -/** - * \typedef irqflags_t - * \brief Type used for holding state of interrupt flag - */ - -/** - * \def cpu_irq_enable - * \brief Enable interrupts globally - */ - -/** - * \def cpu_irq_disable - * \brief Disable interrupts globally - */ - -/** - * \fn irqflags_t cpu_irq_save(void) - * \brief Get and clear the global interrupt flags - * - * Use in conjunction with \ref cpu_irq_restore. - * - * \return Current state of interrupt flags. - * - * \note This function leaves interrupts disabled. - */ - -/** - * \fn void cpu_irq_restore(irqflags_t flags) - * \brief Restore global interrupt flags - * - * Use in conjunction with \ref cpu_irq_save. - * - * \param flags State to set interrupt flag to. - */ - -/** - * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags) - * \brief Check if interrupts are globally enabled in supplied flags - * - * \param flags Currents state of interrupt flags. - * - * \return True if interrupts are enabled. - */ - -/** - * \def cpu_irq_is_enabled - * \brief Check if interrupts are globally enabled - * - * \return True if interrupts are enabled. - */ -//@} - -//! @} - -/** - * \ingroup interrupt_group - * \defgroup interrupt_deprecated_group Deprecated interrupt definitions - */ - -#endif /* UTILS_INTERRUPT_H */ diff --git a/targets/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c b/targets/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c deleted file mode 100644 index 01026bc327d..00000000000 --- a/targets/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c +++ /dev/null @@ -1,40 +0,0 @@ -#include "interrupt_sam_nvic.h" - -#if !defined(__DOXYGEN__) -/* Deprecated - global flag to determine the global interrupt state. Required by - * QTouch library, however new applications should use cpu_irq_is_enabled() - * which probes the true global interrupt state from the CPU special registers. - */ -volatile bool g_interrupt_enabled = true; -#endif - -void cpu_irq_enter_critical(void) -{ - if (cpu_irq_critical_section_counter == 0) { - if (cpu_irq_is_enabled()) { - cpu_irq_disable(); - cpu_irq_prev_interrupt_state = true; - } else { - /* Make sure the to save the prev state as false */ - cpu_irq_prev_interrupt_state = false; - } - - } - - cpu_irq_critical_section_counter++; -} - -void cpu_irq_leave_critical(void) -{ - /* Check if the user is trying to leave a critical section when not in a critical section */ - Assert(cpu_irq_critical_section_counter > 0); - - cpu_irq_critical_section_counter--; - - /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag - was enabled when entering critical state */ - if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) { - cpu_irq_enable(); - } -} - diff --git a/targets/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h b/targets/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h deleted file mode 100644 index 82570303d44..00000000000 --- a/targets/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h +++ /dev/null @@ -1,143 +0,0 @@ -#ifndef UTILS_INTERRUPT_INTERRUPT_H -#define UTILS_INTERRUPT_INTERRUPT_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \weakgroup interrupt_group - * - * @{ - */ - -/** - * \name Interrupt Service Routine definition - * - * @{ - */ - -/** - * \brief Define service routine - * - * \note For NVIC devices the interrupt service routines are predefined to - * add to vector table in binary generation, so there is no service - * register at run time. The routine collections are in exceptions.h. - * - * Usage: - * \code - ISR(foo_irq_handler) - { - // Function definition - ... - } -\endcode - * - * \param func Name for the function. - */ -# define ISR(func) \ - void func (void) - -/** - * \brief Initialize interrupt vectors - * - * For NVIC the interrupt vectors are put in vector table. So nothing - * to do to initialize them, except defined the vector function with - * right name. - * - * This must be called prior to \ref irq_register_handler. - */ -# define irq_initialize_vectors() \ - do { \ - } while(0) - -/** - * \brief Register handler for interrupt - * - * For NVIC the interrupt vectors are put in vector table. So nothing - * to do to register them, except defined the vector function with - * right name. - * - * Usage: - * \code - irq_initialize_vectors(); - irq_register_handler(foo_irq_handler); -\endcode - * - * \note The function \a func must be defined with the \ref ISR macro. - * \note The functions prototypes can be found in the device exception header - * files (exceptions.h). - */ -# define irq_register_handler(int_num, int_prio) \ - NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ - NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ - NVIC_EnableIRQ( (IRQn_Type)int_num); \ - -//@} - -# define cpu_irq_enable() \ - do { \ - g_interrupt_enabled = true; \ - __DMB(); \ - __enable_irq(); \ - } while (0) -# define cpu_irq_disable() \ - do { \ - __disable_irq(); \ - __DMB(); \ - g_interrupt_enabled = false; \ - } while (0) - -typedef uint32_t irqflags_t; - -#if !defined(__DOXYGEN__) -extern volatile bool g_interrupt_enabled; -#endif - -#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) - -static volatile uint32_t cpu_irq_critical_section_counter; -static volatile bool cpu_irq_prev_interrupt_state; - -static inline irqflags_t cpu_irq_save(void) -{ - irqflags_t flags = cpu_irq_is_enabled(); - cpu_irq_disable(); - return flags; -} - -static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) -{ - return (flags); -} - -static inline void cpu_irq_restore(irqflags_t flags) -{ - if (cpu_irq_is_enabled_flags(flags)) - cpu_irq_enable(); -} - -void cpu_irq_enter_critical(void); -void cpu_irq_leave_critical(void); - -/** - * \weakgroup interrupt_deprecated_group - * @{ - */ - -#define Enable_global_interrupt() cpu_irq_enable() -#define Disable_global_interrupt() cpu_irq_disable() -#define Is_global_interrupt_enabled() cpu_irq_is_enabled() - -//@} - -//@} - -#ifdef __cplusplus -} -#endif - -#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/targets/TARGET_Atmel/common/utils/parts.h b/targets/TARGET_Atmel/common/utils/parts.h deleted file mode 100644 index af392b3aaec..00000000000 --- a/targets/TARGET_Atmel/common/utils/parts.h +++ /dev/null @@ -1,1234 +0,0 @@ -#ifndef ATMEL_PARTS_H -#define ATMEL_PARTS_H - -/** - * \defgroup part_macros_group Atmel part identification macros - * - * This collection of macros identify which series and families that the various - * Atmel parts belong to. These can be used to select part-dependent sections of - * code at compile time. - * - * @{ - */ - -/** - * \name Convenience macros for part checking - * @{ - */ -/* ! Check GCC and IAR part definition for 8-bit AVR */ -#define AVR8_PART_IS_DEFINED(part) \ - (defined(__ ## part ## __) || defined(__AVR_ ## part ## __)) - -/* ! Check GCC and IAR part definition for 32-bit AVR */ -#define AVR32_PART_IS_DEFINED(part) \ - (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __)) - -/* ! Check GCC and IAR part definition for SAM */ -#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __)) -/** @} */ - -/** - * \defgroup uc3_part_macros_group AVR UC3 parts - * @{ - */ - -/** - * \name AVR UC3 A series - * @{ - */ -#define UC3A0 ( \ - AVR32_PART_IS_DEFINED(UC3A0128) || \ - AVR32_PART_IS_DEFINED(UC3A0256) || \ - AVR32_PART_IS_DEFINED(UC3A0512) \ - ) - -#define UC3A1 ( \ - AVR32_PART_IS_DEFINED(UC3A1128) || \ - AVR32_PART_IS_DEFINED(UC3A1256) || \ - AVR32_PART_IS_DEFINED(UC3A1512) \ - ) - -#define UC3A3 ( \ - AVR32_PART_IS_DEFINED(UC3A364) || \ - AVR32_PART_IS_DEFINED(UC3A364S) || \ - AVR32_PART_IS_DEFINED(UC3A3128) || \ - AVR32_PART_IS_DEFINED(UC3A3128S) || \ - AVR32_PART_IS_DEFINED(UC3A3256) || \ - AVR32_PART_IS_DEFINED(UC3A3256S) \ - ) - -#define UC3A4 ( \ - AVR32_PART_IS_DEFINED(UC3A464) || \ - AVR32_PART_IS_DEFINED(UC3A464S) || \ - AVR32_PART_IS_DEFINED(UC3A4128) || \ - AVR32_PART_IS_DEFINED(UC3A4128S) || \ - AVR32_PART_IS_DEFINED(UC3A4256) || \ - AVR32_PART_IS_DEFINED(UC3A4256S) \ - ) -/** @} */ - -/** - * \name AVR UC3 B series - * @{ - */ -#define UC3B0 ( \ - AVR32_PART_IS_DEFINED(UC3B064) || \ - AVR32_PART_IS_DEFINED(UC3B0128) || \ - AVR32_PART_IS_DEFINED(UC3B0256) || \ - AVR32_PART_IS_DEFINED(UC3B0512) \ - ) - -#define UC3B1 ( \ - AVR32_PART_IS_DEFINED(UC3B164) || \ - AVR32_PART_IS_DEFINED(UC3B1128) || \ - AVR32_PART_IS_DEFINED(UC3B1256) || \ - AVR32_PART_IS_DEFINED(UC3B1512) \ - ) -/** @} */ - -/** - * \name AVR UC3 C series - * @{ - */ -#define UC3C0 ( \ - AVR32_PART_IS_DEFINED(UC3C064C) || \ - AVR32_PART_IS_DEFINED(UC3C0128C) || \ - AVR32_PART_IS_DEFINED(UC3C0256C) || \ - AVR32_PART_IS_DEFINED(UC3C0512C) \ - ) - -#define UC3C1 ( \ - AVR32_PART_IS_DEFINED(UC3C164C) || \ - AVR32_PART_IS_DEFINED(UC3C1128C) || \ - AVR32_PART_IS_DEFINED(UC3C1256C) || \ - AVR32_PART_IS_DEFINED(UC3C1512C) \ - ) - -#define UC3C2 ( \ - AVR32_PART_IS_DEFINED(UC3C264C) || \ - AVR32_PART_IS_DEFINED(UC3C2128C) || \ - AVR32_PART_IS_DEFINED(UC3C2256C) || \ - AVR32_PART_IS_DEFINED(UC3C2512C) \ - ) -/** @} */ - -/** - * \name AVR UC3 D series - * @{ - */ -#define UC3D3 ( \ - AVR32_PART_IS_DEFINED(UC64D3) || \ - AVR32_PART_IS_DEFINED(UC128D3) \ - ) - -#define UC3D4 ( \ - AVR32_PART_IS_DEFINED(UC64D4) || \ - AVR32_PART_IS_DEFINED(UC128D4) \ - ) -/** @} */ - -/** - * \name AVR UC3 L series - * @{ - */ -#define UC3L0 ( \ - AVR32_PART_IS_DEFINED(UC3L016) || \ - AVR32_PART_IS_DEFINED(UC3L032) || \ - AVR32_PART_IS_DEFINED(UC3L064) \ - ) - -#define UC3L0128 ( \ - AVR32_PART_IS_DEFINED(UC3L0128) \ - ) - -#define UC3L0256 ( \ - AVR32_PART_IS_DEFINED(UC3L0256) \ - ) - -#define UC3L3 ( \ - AVR32_PART_IS_DEFINED(UC64L3U) || \ - AVR32_PART_IS_DEFINED(UC128L3U) || \ - AVR32_PART_IS_DEFINED(UC256L3U) \ - ) - -#define UC3L4 ( \ - AVR32_PART_IS_DEFINED(UC64L4U) || \ - AVR32_PART_IS_DEFINED(UC128L4U) || \ - AVR32_PART_IS_DEFINED(UC256L4U) \ - ) - -#define UC3L3_L4 (UC3L3 || UC3L4) -/** @} */ - -/** - * \name AVR UC3 families - * @{ - */ -/** AVR UC3 A family */ -#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4) - -/** AVR UC3 B family */ -#define UC3B (UC3B0 || UC3B1) - -/** AVR UC3 C family */ -#define UC3C (UC3C0 || UC3C1 || UC3C2) - -/** AVR UC3 D family */ -#define UC3D (UC3D3 || UC3D4) - -/** AVR UC3 L family */ -#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4) -/** @} */ - -/** AVR UC3 product line */ -#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L) - -/** @} */ - -/** - * \defgroup xmega_part_macros_group AVR XMEGA parts - * @{ - */ - -/** - * \name AVR XMEGA A series - * @{ - */ -#define XMEGA_A1 ( \ - AVR8_PART_IS_DEFINED(ATxmega64A1) || \ - AVR8_PART_IS_DEFINED(ATxmega128A1) \ - ) - -#define XMEGA_A3 ( \ - AVR8_PART_IS_DEFINED(ATxmega64A3) || \ - AVR8_PART_IS_DEFINED(ATxmega128A3) || \ - AVR8_PART_IS_DEFINED(ATxmega192A3) || \ - AVR8_PART_IS_DEFINED(ATxmega256A3) \ - ) - -#define XMEGA_A3B ( \ - AVR8_PART_IS_DEFINED(ATxmega256A3B) \ - ) - -#define XMEGA_A4 ( \ - AVR8_PART_IS_DEFINED(ATxmega16A4) || \ - AVR8_PART_IS_DEFINED(ATxmega32A4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA AU series - * @{ - */ -#define XMEGA_A1U ( \ - AVR8_PART_IS_DEFINED(ATxmega64A1U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A1U) \ - ) - -#define XMEGA_A3U ( \ - AVR8_PART_IS_DEFINED(ATxmega64A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega192A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega256A3U) \ - ) - -#define XMEGA_A3BU ( \ - AVR8_PART_IS_DEFINED(ATxmega256A3BU) \ - ) - -#define XMEGA_A4U ( \ - AVR8_PART_IS_DEFINED(ATxmega16A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega32A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega64A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A4U) \ - ) -/** @} */ - -/** - * \name AVR XMEGA B series - * @{ - */ -#define XMEGA_B1 ( \ - AVR8_PART_IS_DEFINED(ATxmega64B1) || \ - AVR8_PART_IS_DEFINED(ATxmega128B1) \ - ) - -#define XMEGA_B3 ( \ - AVR8_PART_IS_DEFINED(ATxmega64B3) || \ - AVR8_PART_IS_DEFINED(ATxmega128B3) \ - ) -/** @} */ - -/** - * \name AVR XMEGA C series - * @{ - */ -#define XMEGA_C3 ( \ - AVR8_PART_IS_DEFINED(ATxmega384C3) || \ - AVR8_PART_IS_DEFINED(ATxmega256C3) || \ - AVR8_PART_IS_DEFINED(ATxmega192C3) || \ - AVR8_PART_IS_DEFINED(ATxmega128C3) || \ - AVR8_PART_IS_DEFINED(ATxmega64C3) || \ - AVR8_PART_IS_DEFINED(ATxmega32C3) \ - ) - -#define XMEGA_C4 ( \ - AVR8_PART_IS_DEFINED(ATxmega32C4) || \ - AVR8_PART_IS_DEFINED(ATxmega16C4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA D series - * @{ - */ -#define XMEGA_D3 ( \ - AVR8_PART_IS_DEFINED(ATxmega32D3) || \ - AVR8_PART_IS_DEFINED(ATxmega64D3) || \ - AVR8_PART_IS_DEFINED(ATxmega128D3) || \ - AVR8_PART_IS_DEFINED(ATxmega192D3) || \ - AVR8_PART_IS_DEFINED(ATxmega256D3) || \ - AVR8_PART_IS_DEFINED(ATxmega384D3) \ - ) - -#define XMEGA_D4 ( \ - AVR8_PART_IS_DEFINED(ATxmega16D4) || \ - AVR8_PART_IS_DEFINED(ATxmega32D4) || \ - AVR8_PART_IS_DEFINED(ATxmega64D4) || \ - AVR8_PART_IS_DEFINED(ATxmega128D4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA E series - * @{ - */ -#define XMEGA_E5 ( \ - AVR8_PART_IS_DEFINED(ATxmega8E5) || \ - AVR8_PART_IS_DEFINED(ATxmega16E5) || \ - AVR8_PART_IS_DEFINED(ATxmega32E5) \ - ) -/** @} */ - - -/** - * \name AVR XMEGA families - * @{ - */ -/** AVR XMEGA A family */ -#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4) - -/** AVR XMEGA AU family */ -#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U) - -/** AVR XMEGA B family */ -#define XMEGA_B (XMEGA_B1 || XMEGA_B3) - -/** AVR XMEGA C family */ -#define XMEGA_C (XMEGA_C3 || XMEGA_C4) - -/** AVR XMEGA D family */ -#define XMEGA_D (XMEGA_D3 || XMEGA_D4) - -/** AVR XMEGA E family */ -#define XMEGA_E (XMEGA_E5) -/** @} */ - - -/** AVR XMEGA product line */ -#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E) - -/** @} */ - -/** - * \defgroup mega_part_macros_group megaAVR parts - * - * \note These megaAVR groupings are based on the groups in AVR Libc for the - * part header files. They are not names of official megaAVR device series or - * families. - * - * @{ - */ - -/** - * \name ATmegaxx0/xx1 subgroups - * @{ - */ -#define MEGA_XX0 ( \ - AVR8_PART_IS_DEFINED(ATmega640) || \ - AVR8_PART_IS_DEFINED(ATmega1280) || \ - AVR8_PART_IS_DEFINED(ATmega2560) \ - ) - -#define MEGA_XX1 ( \ - AVR8_PART_IS_DEFINED(ATmega1281) || \ - AVR8_PART_IS_DEFINED(ATmega2561) \ - ) -/** @} */ - -/** - * \name megaAVR groups - * @{ - */ -/** ATmegaxx0/xx1 group */ -#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1) - -/** ATmegaxx4 group */ -#define MEGA_XX4 ( \ - AVR8_PART_IS_DEFINED(ATmega164A) || \ - AVR8_PART_IS_DEFINED(ATmega164PA) || \ - AVR8_PART_IS_DEFINED(ATmega324A) || \ - AVR8_PART_IS_DEFINED(ATmega324PA) || \ - AVR8_PART_IS_DEFINED(ATmega644) || \ - AVR8_PART_IS_DEFINED(ATmega644A) || \ - AVR8_PART_IS_DEFINED(ATmega644PA) || \ - AVR8_PART_IS_DEFINED(ATmega1284P) || \ - AVR8_PART_IS_DEFINED(ATmega128RFA1) \ - ) - -/** ATmegaxx4 group */ -#define MEGA_XX4_A ( \ - AVR8_PART_IS_DEFINED(ATmega164A) || \ - AVR8_PART_IS_DEFINED(ATmega164PA) || \ - AVR8_PART_IS_DEFINED(ATmega324A) || \ - AVR8_PART_IS_DEFINED(ATmega324PA) || \ - AVR8_PART_IS_DEFINED(ATmega644A) || \ - AVR8_PART_IS_DEFINED(ATmega644PA) || \ - AVR8_PART_IS_DEFINED(ATmega1284P) \ - ) - -/** ATmegaxx8 group */ -#define MEGA_XX8 ( \ - AVR8_PART_IS_DEFINED(ATmega48) || \ - AVR8_PART_IS_DEFINED(ATmega48A) || \ - AVR8_PART_IS_DEFINED(ATmega48PA) || \ - AVR8_PART_IS_DEFINED(ATmega88) || \ - AVR8_PART_IS_DEFINED(ATmega88A) || \ - AVR8_PART_IS_DEFINED(ATmega88PA) || \ - AVR8_PART_IS_DEFINED(ATmega168) || \ - AVR8_PART_IS_DEFINED(ATmega168A) || \ - AVR8_PART_IS_DEFINED(ATmega168PA) || \ - AVR8_PART_IS_DEFINED(ATmega328) || \ - AVR8_PART_IS_DEFINED(ATmega328P) \ - ) - -/** ATmegaxx8A/P/PA group */ -#define MEGA_XX8_A ( \ - AVR8_PART_IS_DEFINED(ATmega48A) || \ - AVR8_PART_IS_DEFINED(ATmega48PA) || \ - AVR8_PART_IS_DEFINED(ATmega88A) || \ - AVR8_PART_IS_DEFINED(ATmega88PA) || \ - AVR8_PART_IS_DEFINED(ATmega168A) || \ - AVR8_PART_IS_DEFINED(ATmega168PA) || \ - AVR8_PART_IS_DEFINED(ATmega328P) \ - ) - -/** ATmegaxx group */ -#define MEGA_XX ( \ - AVR8_PART_IS_DEFINED(ATmega16) || \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32) || \ - AVR8_PART_IS_DEFINED(ATmega32A) || \ - AVR8_PART_IS_DEFINED(ATmega64) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) - -/** ATmegaxxA/P/PA group */ -#define MEGA_XX_A ( \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32A) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) -/** ATmegaxxRFA1 group */ -#define MEGA_RFA1 ( \ - AVR8_PART_IS_DEFINED(ATmega128RFA1) \ - ) - -/** ATmegaxxRFR2 group */ -#define MEGA_RFR2 ( \ - AVR8_PART_IS_DEFINED(ATmega64RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega128RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega256RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega644RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega2564RFR2) \ - ) - - -/** ATmegaxxRFxx group */ -#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2) - -/** - * \name ATmegaxx_un0/un1/un2 subgroups - * @{ - */ -#define MEGA_XX_UN0 ( \ - AVR8_PART_IS_DEFINED(ATmega16) || \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32) || \ - AVR8_PART_IS_DEFINED(ATmega32A) \ - ) - -/** ATmegaxx group without power reduction and - * And interrupt sense register. - */ -#define MEGA_XX_UN1 ( \ - AVR8_PART_IS_DEFINED(ATmega64) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) - -/** ATmegaxx group without power reduction and - * And interrupt sense register. - */ -#define MEGA_XX_UN2 ( \ - AVR8_PART_IS_DEFINED(ATmega169P) || \ - AVR8_PART_IS_DEFINED(ATmega169PA) || \ - AVR8_PART_IS_DEFINED(ATmega329P) || \ - AVR8_PART_IS_DEFINED(ATmega329PA) \ - ) - -/** Devices added to complete megaAVR offering. - * Please do not use this group symbol as it is not intended - * to be permanent: the devices should be regrouped. - */ -#define MEGA_UNCATEGORIZED ( \ - AVR8_PART_IS_DEFINED(AT90CAN128) || \ - AVR8_PART_IS_DEFINED(AT90CAN32) || \ - AVR8_PART_IS_DEFINED(AT90CAN64) || \ - AVR8_PART_IS_DEFINED(AT90PWM1) || \ - AVR8_PART_IS_DEFINED(AT90PWM216) || \ - AVR8_PART_IS_DEFINED(AT90PWM2B) || \ - AVR8_PART_IS_DEFINED(AT90PWM316) || \ - AVR8_PART_IS_DEFINED(AT90PWM3B) || \ - AVR8_PART_IS_DEFINED(AT90PWM81) || \ - AVR8_PART_IS_DEFINED(AT90USB1286) || \ - AVR8_PART_IS_DEFINED(AT90USB1287) || \ - AVR8_PART_IS_DEFINED(AT90USB162) || \ - AVR8_PART_IS_DEFINED(AT90USB646) || \ - AVR8_PART_IS_DEFINED(AT90USB647) || \ - AVR8_PART_IS_DEFINED(AT90USB82) || \ - AVR8_PART_IS_DEFINED(ATmega1284) || \ - AVR8_PART_IS_DEFINED(ATmega162) || \ - AVR8_PART_IS_DEFINED(ATmega164P) || \ - AVR8_PART_IS_DEFINED(ATmega165A) || \ - AVR8_PART_IS_DEFINED(ATmega165P) || \ - AVR8_PART_IS_DEFINED(ATmega165PA) || \ - AVR8_PART_IS_DEFINED(ATmega168P) || \ - AVR8_PART_IS_DEFINED(ATmega169A) || \ - AVR8_PART_IS_DEFINED(ATmega16M1) || \ - AVR8_PART_IS_DEFINED(ATmega16U2) || \ - AVR8_PART_IS_DEFINED(ATmega16U4) || \ - AVR8_PART_IS_DEFINED(ATmega256RFA2) || \ - AVR8_PART_IS_DEFINED(ATmega324P) || \ - AVR8_PART_IS_DEFINED(ATmega325) || \ - AVR8_PART_IS_DEFINED(ATmega3250) || \ - AVR8_PART_IS_DEFINED(ATmega3250A) || \ - AVR8_PART_IS_DEFINED(ATmega3250P) || \ - AVR8_PART_IS_DEFINED(ATmega3250PA) || \ - AVR8_PART_IS_DEFINED(ATmega325A) || \ - AVR8_PART_IS_DEFINED(ATmega325P) || \ - AVR8_PART_IS_DEFINED(ATmega325PA) || \ - AVR8_PART_IS_DEFINED(ATmega329) || \ - AVR8_PART_IS_DEFINED(ATmega3290) || \ - AVR8_PART_IS_DEFINED(ATmega3290A) || \ - AVR8_PART_IS_DEFINED(ATmega3290P) || \ - AVR8_PART_IS_DEFINED(ATmega3290PA) || \ - AVR8_PART_IS_DEFINED(ATmega329A) || \ - AVR8_PART_IS_DEFINED(ATmega32M1) || \ - AVR8_PART_IS_DEFINED(ATmega32U2) || \ - AVR8_PART_IS_DEFINED(ATmega32U4) || \ - AVR8_PART_IS_DEFINED(ATmega48P) || \ - AVR8_PART_IS_DEFINED(ATmega644P) || \ - AVR8_PART_IS_DEFINED(ATmega645) || \ - AVR8_PART_IS_DEFINED(ATmega6450) || \ - AVR8_PART_IS_DEFINED(ATmega6450A) || \ - AVR8_PART_IS_DEFINED(ATmega6450P) || \ - AVR8_PART_IS_DEFINED(ATmega645A) || \ - AVR8_PART_IS_DEFINED(ATmega645P) || \ - AVR8_PART_IS_DEFINED(ATmega649) || \ - AVR8_PART_IS_DEFINED(ATmega6490) || \ - AVR8_PART_IS_DEFINED(ATmega6490A) || \ - AVR8_PART_IS_DEFINED(ATmega6490P) || \ - AVR8_PART_IS_DEFINED(ATmega649A) || \ - AVR8_PART_IS_DEFINED(ATmega649P) || \ - AVR8_PART_IS_DEFINED(ATmega64M1) || \ - AVR8_PART_IS_DEFINED(ATmega64RFA2) || \ - AVR8_PART_IS_DEFINED(ATmega8) || \ - AVR8_PART_IS_DEFINED(ATmega8515) || \ - AVR8_PART_IS_DEFINED(ATmega8535) || \ - AVR8_PART_IS_DEFINED(ATmega88P) || \ - AVR8_PART_IS_DEFINED(ATmega8A) || \ - AVR8_PART_IS_DEFINED(ATmega8U2) \ - ) - -/** Unspecified group */ -#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \ - MEGA_UNCATEGORIZED) - -/** @} */ - -/** megaAVR product line */ -#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \ - MEGA_UNSPECIFIED) - -/** @} */ - -/** - * \defgroup tiny_part_macros_group tinyAVR parts - * - * @{ - */ - -/** - * \name tinyAVR groups - * @{ - */ - -/** Devices added to complete tinyAVR offering. - * Please do not use this group symbol as it is not intended - * to be permanent: the devices should be regrouped. - */ -#define TINY_UNCATEGORIZED ( \ - AVR8_PART_IS_DEFINED(ATtiny10) || \ - AVR8_PART_IS_DEFINED(ATtiny13) || \ - AVR8_PART_IS_DEFINED(ATtiny13A) || \ - AVR8_PART_IS_DEFINED(ATtiny1634) || \ - AVR8_PART_IS_DEFINED(ATtiny167) || \ - AVR8_PART_IS_DEFINED(ATtiny20) || \ - AVR8_PART_IS_DEFINED(ATtiny2313) || \ - AVR8_PART_IS_DEFINED(ATtiny2313A) || \ - AVR8_PART_IS_DEFINED(ATtiny24) || \ - AVR8_PART_IS_DEFINED(ATtiny24A) || \ - AVR8_PART_IS_DEFINED(ATtiny25) || \ - AVR8_PART_IS_DEFINED(ATtiny26) || \ - AVR8_PART_IS_DEFINED(ATtiny261) || \ - AVR8_PART_IS_DEFINED(ATtiny261A) || \ - AVR8_PART_IS_DEFINED(ATtiny4) || \ - AVR8_PART_IS_DEFINED(ATtiny40) || \ - AVR8_PART_IS_DEFINED(ATtiny4313) || \ - AVR8_PART_IS_DEFINED(ATtiny43U) || \ - AVR8_PART_IS_DEFINED(ATtiny44) || \ - AVR8_PART_IS_DEFINED(ATtiny44A) || \ - AVR8_PART_IS_DEFINED(ATtiny45) || \ - AVR8_PART_IS_DEFINED(ATtiny461) || \ - AVR8_PART_IS_DEFINED(ATtiny461A) || \ - AVR8_PART_IS_DEFINED(ATtiny48) || \ - AVR8_PART_IS_DEFINED(ATtiny5) || \ - AVR8_PART_IS_DEFINED(ATtiny828) || \ - AVR8_PART_IS_DEFINED(ATtiny84) || \ - AVR8_PART_IS_DEFINED(ATtiny84A) || \ - AVR8_PART_IS_DEFINED(ATtiny85) || \ - AVR8_PART_IS_DEFINED(ATtiny861) || \ - AVR8_PART_IS_DEFINED(ATtiny861A) || \ - AVR8_PART_IS_DEFINED(ATtiny87) || \ - AVR8_PART_IS_DEFINED(ATtiny88) || \ - AVR8_PART_IS_DEFINED(ATtiny9) \ - ) - -/** @} */ - -/** tinyAVR product line */ -#define TINY (TINY_UNCATEGORIZED) - -/** @} */ - -/** - * \defgroup sam_part_macros_group SAM parts - * @{ - */ - -/** - * \name SAM3S series - * @{ - */ -#define SAM3S1 ( \ - SAM_PART_IS_DEFINED(SAM3S1A) || \ - SAM_PART_IS_DEFINED(SAM3S1B) || \ - SAM_PART_IS_DEFINED(SAM3S1C) \ - ) - -#define SAM3S2 ( \ - SAM_PART_IS_DEFINED(SAM3S2A) || \ - SAM_PART_IS_DEFINED(SAM3S2B) || \ - SAM_PART_IS_DEFINED(SAM3S2C) \ - ) - -#define SAM3S4 ( \ - SAM_PART_IS_DEFINED(SAM3S4A) || \ - SAM_PART_IS_DEFINED(SAM3S4B) || \ - SAM_PART_IS_DEFINED(SAM3S4C) \ - ) - -#define SAM3S8 ( \ - SAM_PART_IS_DEFINED(SAM3S8B) || \ - SAM_PART_IS_DEFINED(SAM3S8C) \ - ) - -#define SAM3SD8 ( \ - SAM_PART_IS_DEFINED(SAM3SD8B) || \ - SAM_PART_IS_DEFINED(SAM3SD8C) \ - ) -/** @} */ - -/** - * \name SAM3U series - * @{ - */ -#define SAM3U1 ( \ - SAM_PART_IS_DEFINED(SAM3U1C) || \ - SAM_PART_IS_DEFINED(SAM3U1E) \ - ) - -#define SAM3U2 ( \ - SAM_PART_IS_DEFINED(SAM3U2C) || \ - SAM_PART_IS_DEFINED(SAM3U2E) \ - ) - -#define SAM3U4 ( \ - SAM_PART_IS_DEFINED(SAM3U4C) || \ - SAM_PART_IS_DEFINED(SAM3U4E) \ - ) -/** @} */ - -/** - * \name SAM3N series - * @{ - */ -#define SAM3N00 ( \ - SAM_PART_IS_DEFINED(SAM3N00A) || \ - SAM_PART_IS_DEFINED(SAM3N00B) \ - ) - -#define SAM3N0 ( \ - SAM_PART_IS_DEFINED(SAM3N0A) || \ - SAM_PART_IS_DEFINED(SAM3N0B) || \ - SAM_PART_IS_DEFINED(SAM3N0C) \ - ) - -#define SAM3N1 ( \ - SAM_PART_IS_DEFINED(SAM3N1A) || \ - SAM_PART_IS_DEFINED(SAM3N1B) || \ - SAM_PART_IS_DEFINED(SAM3N1C) \ - ) - -#define SAM3N2 ( \ - SAM_PART_IS_DEFINED(SAM3N2A) || \ - SAM_PART_IS_DEFINED(SAM3N2B) || \ - SAM_PART_IS_DEFINED(SAM3N2C) \ - ) - -#define SAM3N4 ( \ - SAM_PART_IS_DEFINED(SAM3N4A) || \ - SAM_PART_IS_DEFINED(SAM3N4B) || \ - SAM_PART_IS_DEFINED(SAM3N4C) \ - ) -/** @} */ - -/** - * \name SAM3X series - * @{ - */ -#define SAM3X4 ( \ - SAM_PART_IS_DEFINED(SAM3X4C) || \ - SAM_PART_IS_DEFINED(SAM3X4E) \ - ) - -#define SAM3X8 ( \ - SAM_PART_IS_DEFINED(SAM3X8C) || \ - SAM_PART_IS_DEFINED(SAM3X8E) || \ - SAM_PART_IS_DEFINED(SAM3X8H) \ - ) -/** @} */ - -/** - * \name SAM3A series - * @{ - */ -#define SAM3A4 ( \ - SAM_PART_IS_DEFINED(SAM3A4C) \ - ) - -#define SAM3A8 ( \ - SAM_PART_IS_DEFINED(SAM3A8C) \ - ) -/** @} */ - -/** - * \name SAM4S series - * @{ - */ -#define SAM4S2 ( \ - SAM_PART_IS_DEFINED(SAM4S2A) || \ - SAM_PART_IS_DEFINED(SAM4S2B) || \ - SAM_PART_IS_DEFINED(SAM4S2C) \ - ) - -#define SAM4S4 ( \ - SAM_PART_IS_DEFINED(SAM4S4A) || \ - SAM_PART_IS_DEFINED(SAM4S4B) || \ - SAM_PART_IS_DEFINED(SAM4S4C) \ - ) - -#define SAM4S8 ( \ - SAM_PART_IS_DEFINED(SAM4S8B) || \ - SAM_PART_IS_DEFINED(SAM4S8C) \ - ) - -#define SAM4S16 ( \ - SAM_PART_IS_DEFINED(SAM4S16B) || \ - SAM_PART_IS_DEFINED(SAM4S16C) \ - ) - -#define SAM4SA16 ( \ - SAM_PART_IS_DEFINED(SAM4SA16B) || \ - SAM_PART_IS_DEFINED(SAM4SA16C) \ - ) - -#define SAM4SD16 ( \ - SAM_PART_IS_DEFINED(SAM4SD16B) || \ - SAM_PART_IS_DEFINED(SAM4SD16C) \ - ) - -#define SAM4SD32 ( \ - SAM_PART_IS_DEFINED(SAM4SD32B) || \ - SAM_PART_IS_DEFINED(SAM4SD32C) \ - ) -/** @} */ - -/** - * \name SAM4L series - * @{ - */ -#define SAM4LS ( \ - SAM_PART_IS_DEFINED(SAM4LS2A) || \ - SAM_PART_IS_DEFINED(SAM4LS2B) || \ - SAM_PART_IS_DEFINED(SAM4LS2C) || \ - SAM_PART_IS_DEFINED(SAM4LS4A) || \ - SAM_PART_IS_DEFINED(SAM4LS4B) || \ - SAM_PART_IS_DEFINED(SAM4LS4C) || \ - SAM_PART_IS_DEFINED(SAM4LS8A) || \ - SAM_PART_IS_DEFINED(SAM4LS8B) || \ - SAM_PART_IS_DEFINED(SAM4LS8C) \ - ) - -#define SAM4LC ( \ - SAM_PART_IS_DEFINED(SAM4LC2A) || \ - SAM_PART_IS_DEFINED(SAM4LC2B) || \ - SAM_PART_IS_DEFINED(SAM4LC2C) || \ - SAM_PART_IS_DEFINED(SAM4LC4A) || \ - SAM_PART_IS_DEFINED(SAM4LC4B) || \ - SAM_PART_IS_DEFINED(SAM4LC4C) || \ - SAM_PART_IS_DEFINED(SAM4LC8A) || \ - SAM_PART_IS_DEFINED(SAM4LC8B) || \ - SAM_PART_IS_DEFINED(SAM4LC8C) \ - ) -/** @} */ - -/** - * \name SAMD20 series - * @{ - */ -#define SAMD20J ( \ - SAM_PART_IS_DEFINED(SAMD20J14) || \ - SAM_PART_IS_DEFINED(SAMD20J15) || \ - SAM_PART_IS_DEFINED(SAMD20J16) || \ - SAM_PART_IS_DEFINED(SAMD20J17) || \ - SAM_PART_IS_DEFINED(SAMD20J18) \ - ) - -#define SAMD20G ( \ - SAM_PART_IS_DEFINED(SAMD20G14) || \ - SAM_PART_IS_DEFINED(SAMD20G15) || \ - SAM_PART_IS_DEFINED(SAMD20G16) || \ - SAM_PART_IS_DEFINED(SAMD20G17) || \ - SAM_PART_IS_DEFINED(SAMD20G17U) || \ - SAM_PART_IS_DEFINED(SAMD20G18) || \ - SAM_PART_IS_DEFINED(SAMD20G18U) \ - ) - -#define SAMD20E ( \ - SAM_PART_IS_DEFINED(SAMD20E14) || \ - SAM_PART_IS_DEFINED(SAMD20E15) || \ - SAM_PART_IS_DEFINED(SAMD20E16) || \ - SAM_PART_IS_DEFINED(SAMD20E17) || \ - SAM_PART_IS_DEFINED(SAMD20E18) || \ - SAM_PART_IS_DEFINED(SAMD20E1F) \ - ) -/** @} */ - -/** - * \name SAMD21 series - * @{ - */ -#define SAMD21J ( \ - SAM_PART_IS_DEFINED(SAMD21J15A) || \ - SAM_PART_IS_DEFINED(SAMD21J16A) || \ - SAM_PART_IS_DEFINED(SAMD21J17A) || \ - SAM_PART_IS_DEFINED(SAMD21J18A) \ - ) - -#define SAMD21G ( \ - SAM_PART_IS_DEFINED(SAMD21G15A) || \ - SAM_PART_IS_DEFINED(SAMD21G16A) || \ - SAM_PART_IS_DEFINED(SAMD21G17A) || \ - SAM_PART_IS_DEFINED(SAMD21G18A) \ - ) - -#define SAMD21E ( \ - SAM_PART_IS_DEFINED(SAMD21E15A) || \ - SAM_PART_IS_DEFINED(SAMD21E16A) || \ - SAM_PART_IS_DEFINED(SAMD21E17A) || \ - SAM_PART_IS_DEFINED(SAMD21E18A) \ - ) -/** @} */ - -/** - * \name SAMR21 series - * @{ - */ -#define SAMR21G ( \ - SAM_PART_IS_DEFINED(SAMR21G16A) || \ - SAM_PART_IS_DEFINED(SAMR21G17A) || \ - SAM_PART_IS_DEFINED(SAMR21G18A) \ - ) - -#define SAMR21E ( \ - SAM_PART_IS_DEFINED(SAMR21E16A) || \ - SAM_PART_IS_DEFINED(SAMR21E17A) || \ - SAM_PART_IS_DEFINED(SAMR21E18A) \ - ) -/** @} */ - -/** - * \name SAMD10 series - * @{ - */ -#define SAMD10C ( \ - SAM_PART_IS_DEFINED(SAMD10C12A) || \ - SAM_PART_IS_DEFINED(SAMD10C13A) || \ - SAM_PART_IS_DEFINED(SAMD10C14A) \ - ) - -#define SAMD10DS ( \ - SAM_PART_IS_DEFINED(SAMD10D12AS) || \ - SAM_PART_IS_DEFINED(SAMD10D13AS) || \ - SAM_PART_IS_DEFINED(SAMD10D14AS) \ - ) - -#define SAMD10DM ( \ - SAM_PART_IS_DEFINED(SAMD10D12AM) || \ - SAM_PART_IS_DEFINED(SAMD10D13AM) || \ - SAM_PART_IS_DEFINED(SAMD10D14AM) \ - ) -/** @} */ - -/** - * \name SAMD11 series - * @{ - */ -#define SAMD11C ( \ - SAM_PART_IS_DEFINED(SAMD11C14A) \ - ) - -#define SAMD11DS ( \ - SAM_PART_IS_DEFINED(SAMD11D14AS) \ - ) - -#define SAMD11DM ( \ - SAM_PART_IS_DEFINED(SAMD11D14AM) \ - ) -/** @} */ - -/** - * \name SAML21 series - * @{ - */ -#define SAML21E ( \ - SAM_PART_IS_DEFINED(SAML21E15A) || \ - SAM_PART_IS_DEFINED(SAML21E16A) || \ - SAM_PART_IS_DEFINED(SAML21E17A) || \ - SAM_PART_IS_DEFINED(SAML21E18A) \ - ) - -#define SAML21G ( \ - SAM_PART_IS_DEFINED(SAML21G16A) || \ - SAM_PART_IS_DEFINED(SAML21G17A) || \ - SAM_PART_IS_DEFINED(SAML21G18A) \ - ) - -#define SAML21J ( \ - SAM_PART_IS_DEFINED(SAML21J16A) || \ - SAM_PART_IS_DEFINED(SAML21J17A) || \ - SAM_PART_IS_DEFINED(SAML21J18A) \ - ) -/** @} */ - -/** - * \name SAM4E series - * @{ - */ -#define SAM4E8 ( \ - SAM_PART_IS_DEFINED(SAM4E8C) || \ - SAM_PART_IS_DEFINED(SAM4E8E) \ - ) - -#define SAM4E16 ( \ - SAM_PART_IS_DEFINED(SAM4E16C) || \ - SAM_PART_IS_DEFINED(SAM4E16E) \ - ) -/** @} */ - -/** - * \name SAM4N series - * @{ - */ -#define SAM4N8 ( \ - SAM_PART_IS_DEFINED(SAM4N8A) || \ - SAM_PART_IS_DEFINED(SAM4N8B) || \ - SAM_PART_IS_DEFINED(SAM4N8C) \ - ) - -#define SAM4N16 ( \ - SAM_PART_IS_DEFINED(SAM4N16B) || \ - SAM_PART_IS_DEFINED(SAM4N16C) \ - ) -/** @} */ - -/** - * \name SAM4C series - * @{ - */ -#define SAM4C8_0 ( \ - SAM_PART_IS_DEFINED(SAM4C8C_0) \ - ) - -#define SAM4C8_1 ( \ - SAM_PART_IS_DEFINED(SAM4C8C_1) \ - ) - -#define SAM4C8 (SAM4C8_0 || SAM4C8_1) - -#define SAM4C16_0 ( \ - SAM_PART_IS_DEFINED(SAM4C16C_0) \ - ) - -#define SAM4C16_1 ( \ - SAM_PART_IS_DEFINED(SAM4C16C_1) \ - ) - -#define SAM4C16 (SAM4C16_0 || SAM4C16_1) - -#define SAM4C32_0 ( \ - SAM_PART_IS_DEFINED(SAM4C32C_0) ||\ - SAM_PART_IS_DEFINED(SAM4C32E_0) \ - ) - -#define SAM4C32_1 ( \ - SAM_PART_IS_DEFINED(SAM4C32C_1) ||\ - SAM_PART_IS_DEFINED(SAM4C32E_1) \ - ) - - -#define SAM4C32 (SAM4C32_0 || SAM4C32_1) - -/** @} */ - -/** - * \name SAM4CM series - * @{ - */ -#define SAM4CMP8_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMP8C_0) \ - ) - -#define SAM4CMP8_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMP8C_1) \ - ) - -#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1) - -#define SAM4CMP16_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMP16C_0) \ - ) - -#define SAM4CMP16_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMP16C_1) \ - ) - -#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1) - -#define SAM4CMP32_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMP32C_0) \ - ) - -#define SAM4CMP32_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMP32C_1) \ - ) - -#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1) - -#define SAM4CMS8_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMS8C_0) \ - ) - -#define SAM4CMS8_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMS8C_1) \ - ) - -#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1) - -#define SAM4CMS16_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMS16C_0) \ - ) - -#define SAM4CMS16_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMS16C_1) \ - ) - -#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1) - -#define SAM4CMS32_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMS32C_0) \ - ) - -#define SAM4CMS32_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMS32C_1) \ - ) - -#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1) - -/** @} */ - -/** - * \name SAM4CP series - * @{ - */ -#define SAM4CP16_0 ( \ - SAM_PART_IS_DEFINED(SAM4CP16B_0) \ - ) - -#define SAM4CP16_1 ( \ - SAM_PART_IS_DEFINED(SAM4CP16B_1) \ - ) - -#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1) -/** @} */ - -/** - * \name SAMG series - * @{ - */ -#define SAMG51 ( \ - SAM_PART_IS_DEFINED(SAMG51G18) \ - ) - -#define SAMG53 ( \ - SAM_PART_IS_DEFINED(SAMG53G19) ||\ - SAM_PART_IS_DEFINED(SAMG53N19) \ - ) - -#define SAMG54 ( \ - SAM_PART_IS_DEFINED(SAMG54G19) ||\ - SAM_PART_IS_DEFINED(SAMG54J19) ||\ - SAM_PART_IS_DEFINED(SAMG54N19) \ - ) - -#define SAMG55 ( \ - SAM_PART_IS_DEFINED(SAMG55G18) ||\ - SAM_PART_IS_DEFINED(SAMG55G19) ||\ - SAM_PART_IS_DEFINED(SAMG55J18) ||\ - SAM_PART_IS_DEFINED(SAMG55J19) ||\ - SAM_PART_IS_DEFINED(SAMG55N19) \ - ) -/** @} */ -/** - * \name SAM families - * @{ - */ -/** SAM3S Family */ -#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8) - -/** SAM3U Family */ -#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4) - -/** SAM3N Family */ -#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4) - -/** SAM3XA Family */ -#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8) - -/** SAM4S Family */ -#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32) - -/** SAM4L Family */ -#define SAM4L (SAM4LS || SAM4LC) - -/** SAMD20 Family */ -#define SAMD20 (SAMD20J || SAMD20G || SAMD20E) - -/** SAMD21 Family */ -#define SAMD21 (SAMD21J || SAMD21G || SAMD21E) - -/** SAMD10 Family */ -#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM) - -/** SAMD11 Family */ -#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM) - -/** SAMD Family */ -#define SAMD (SAMD20 || SAMD21 || SAMD10 || SAMD11) - -/** SAMR21 Family */ -#define SAMR21 (SAMR21G || SAMR21E) - -/** SAML21 Family */ -#define SAML21 (SAML21J || SAML21G || SAML21E) - -/** SAM4E Family */ -#define SAM4E (SAM4E8 || SAM4E16) - -/** SAM4N Family */ -#define SAM4N (SAM4N8 || SAM4N16) - -/** SAM4C Family */ -#define SAM4C_0 (SAM4C8_0 || SAM4C16_0 || SAM4C32_0) -#define SAM4C_1 (SAM4C8_1 || SAM4C16_1 || SAM4C32_1) -#define SAM4C (SAM4C8 || SAM4C16 || SAM4C32) - -/** SAM4CM Family */ -#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || SAM4CMS8_0 || \ - SAM4CMS16_0 || SAM4CMS32_0) -#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || SAM4CMS8_1 || \ - SAM4CMS16_1 || SAM4CMS32_1) -#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || SAM4CMS8 || \ - SAM4CMS16 || SAM4CMS32) - -/** SAM4CP Family */ -#define SAM4CP_0 (SAM4CP16_0) -#define SAM4CP_1 (SAM4CP16_1) -#define SAM4CP (SAM4CP16) - -/** SAMG Family */ -#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55) - -/** SAM0 product line (cortex-m0+) */ -#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21) - -/** @} */ - -/** SAM product line */ -#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \ - SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG) - -/** @} */ - -/** @} */ - -/** @} */ - -#endif /* ATMEL_PARTS_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_adc.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_adc.h deleted file mode 100644 index e3b44fc49fa..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_adc.h +++ /dev/null @@ -1,396 +0,0 @@ -/*! - \file gd32e10x_adc.h - \brief definitions for the ADC - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_ADC_H -#define GD32E10X_ADC_H - -#include "gd32e10x.h" - -/* ADC definitions */ -#define ADC0 ADC_BASE -#define ADC1 (ADC_BASE + 0x400U) - -/* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ -#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ - -/* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx x=0..2 */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3 */ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ -#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ - -/* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ -#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< ADC resolution */ - -/* constants definitions */ -/* adc_stat register value */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - -/* scan mode */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ - -/* inserted channel group convert automatically */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ - -/* ADC sync mode */ -#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ -#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ -#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ -#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ -#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ - -/* adc_ctl1 register value */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ - -/* continuous mode */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -/* external trigger select for regular channel */ -#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< timer 2 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< timer 3 CC3 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< timer 7 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - -/* external trigger mode for inserted channel */ -#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ -#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< timer 1 CC0 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< timer 2 CC3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< timer 3 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ -#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< timer 7 CC3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ - -/* adc_samptx register value */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ -#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ -#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ -#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ -#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ -#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ -#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ -#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - -/* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - -/* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - -/* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - -/* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - -/* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - -/* adc_ovsampctl register value */ -/* ADC resolution */ -#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ -#define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ - -/* oversampling shift */ -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ - -/* oversampling ratio */ -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ - -/* triggered Oversampling */ -#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ - -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ - -/* ADC interrupt */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - -/* function declarations */ -/* initialization config */ -/* reset ADC */ -void adc_deinit(uint32_t adc_periph); -/* configure the ADC sync mode */ -void adc_mode_config(uint32_t mode); -/* enable or disable ADC special function */ -void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); -/* enable ADC interface */ -void adc_enable(uint32_t adc_periph); -/* disable ADC interface */ -void adc_disable(uint32_t adc_periph); -/* ADC calibration and reset calibration */ -void adc_calibration_enable(uint32_t adc_periph); -/* enable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_enable(void); -/* disable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_disable(void); -/* configure ADC resolution */ -void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); -/* configure ADC oversample mode */ -void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio); -/* enable ADC oversample mode */ -void adc_oversample_mode_enable(uint32_t adc_periph); -/* disable ADC oversample mode */ -void adc_oversample_mode_disable(uint32_t adc_periph); - -/* DMA config */ -/* enable DMA request */ -void adc_dma_mode_enable(uint32_t adc_periph); -/* disable DMA request */ -void adc_dma_mode_disable(uint32_t adc_periph); - -/* regular group and inserted group config */ -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); -/* enable ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); - -/* get channel data */ -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); -/* read the last ADC0 and ADC1 conversion result data in sync mode */ -uint32_t adc_sync_mode_convert_value_read(void); - -/* watchdog config */ -/* configure ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); - -/* interrupt & flag functions */ -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); -/* get the bit state of ADCx software start conversion */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); -/* get the bit state of ADCx software inserted channel start conversion */ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); - -#endif /* GD32E10X_ADC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_bkp.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_bkp.h deleted file mode 100644 index 2cc4cce39cd..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_bkp.h +++ /dev/null @@ -1,244 +0,0 @@ -/*! - \file gd32e10x_bkp.h - \brief definitions for the BKP - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_BKP_H -#define GD32E10X_BKP_H - -#include "gd32e10x.h" - -/* BKP definitions */ -#define BKP BKP_BASE /*!< BKP base address */ - -/* registers definitions */ -#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ -#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ -#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ -#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ -#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ -#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ -#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ -#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ -#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ -#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ -#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ -#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ -#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ -#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ -#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ -#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ -#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ -#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ -#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ -#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ -#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ -#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ -#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ -#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ -#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ -#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ -#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ -#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ -#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ -#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ -#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ -#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ -#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ -#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ -#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ -#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ -#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ -#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ -#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ -#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ -#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ -#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ -#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ -#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ -#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ - -/* bits definitions */ -/* BKP_DATA */ -#define BKP_DATA BITS(0,15) /*!< backup data */ - -/* BKP_OCTL */ -#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ -#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ -#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ -#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ -#define BKP_OCTL_CCOSEL BIT(14) /*!< RTC clock output selection */ -#define BKP_OCTL_CALDIR BIT(15) /*!< RTC clock calibration direction */ - -/* BKP_TPCTL */ -#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ -#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ - -/* BKP_TPCS */ -#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ -#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ -#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ -#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ -#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ - -/* constants definitions */ -/* BKP data register number */ -typedef enum { - BKP_DATA_0 = 1, /*!< BKP data register 0 */ - BKP_DATA_1, /*!< BKP data register 1 */ - BKP_DATA_2, /*!< BKP data register 2 */ - BKP_DATA_3, /*!< BKP data register 3 */ - BKP_DATA_4, /*!< BKP data register 4 */ - BKP_DATA_5, /*!< BKP data register 5 */ - BKP_DATA_6, /*!< BKP data register 6 */ - BKP_DATA_7, /*!< BKP data register 7 */ - BKP_DATA_8, /*!< BKP data register 8 */ - BKP_DATA_9, /*!< BKP data register 9 */ - BKP_DATA_10, /*!< BKP data register 10 */ - BKP_DATA_11, /*!< BKP data register 11 */ - BKP_DATA_12, /*!< BKP data register 12 */ - BKP_DATA_13, /*!< BKP data register 13 */ - BKP_DATA_14, /*!< BKP data register 14 */ - BKP_DATA_15, /*!< BKP data register 15 */ - BKP_DATA_16, /*!< BKP data register 16 */ - BKP_DATA_17, /*!< BKP data register 17 */ - BKP_DATA_18, /*!< BKP data register 18 */ - BKP_DATA_19, /*!< BKP data register 19 */ - BKP_DATA_20, /*!< BKP data register 20 */ - BKP_DATA_21, /*!< BKP data register 21 */ - BKP_DATA_22, /*!< BKP data register 22 */ - BKP_DATA_23, /*!< BKP data register 23 */ - BKP_DATA_24, /*!< BKP data register 24 */ - BKP_DATA_25, /*!< BKP data register 25 */ - BKP_DATA_26, /*!< BKP data register 26 */ - BKP_DATA_27, /*!< BKP data register 27 */ - BKP_DATA_28, /*!< BKP data register 28 */ - BKP_DATA_29, /*!< BKP data register 29 */ - BKP_DATA_30, /*!< BKP data register 30 */ - BKP_DATA_31, /*!< BKP data register 31 */ - BKP_DATA_32, /*!< BKP data register 32 */ - BKP_DATA_33, /*!< BKP data register 33 */ - BKP_DATA_34, /*!< BKP data register 34 */ - BKP_DATA_35, /*!< BKP data register 35 */ - BKP_DATA_36, /*!< BKP data register 36 */ - BKP_DATA_37, /*!< BKP data register 37 */ - BKP_DATA_38, /*!< BKP data register 38 */ - BKP_DATA_39, /*!< BKP data register 39 */ - BKP_DATA_40, /*!< BKP data register 40 */ - BKP_DATA_41, /*!< BKP data register 41 */ -} bkp_data_register_enum; - -/* BKP data register */ -#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) -#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) - -/* get data of BKP data register */ -#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) - -/* RTC clock calibration value */ -#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/* RTC output selection */ -#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ -#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)BKP_OCTL_ROSEL) /*!< RTC second pulse is selected as the RTC output */ - -/* RTC clock output selection */ -#define RTC_CLOCK_DIV_64 ((uint16_t)0x0000U) /*!< RTC clock div 64 */ -#define RTC_CLOCK_DIV_1 ((uint16_t)BKP_OCTL_CCOSEL) /*!< RTC clock div 1 */ - -/* RTC clock calibration direction */ -#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */ -#define RTC_CLOCK_SPEED_UP ((uint16_t)BKP_OCTL_CALDIR) /*!< RTC clock speed up */ - -/* tamper pin active level */ -#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ -#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)BKP_TPCTL_TPAL) /*!< the tamper pin is active low */ - -/* tamper flag */ -#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ - -/* tamper interrupt flag */ -#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ - -/* function declarations */ -/* operation functions */ -/* reset BKP registers */ -void bkp_deinit(void); -/* write BKP data register */ -void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); -/* read BKP data register */ -uint16_t bkp_data_read(bkp_data_register_enum register_number); - -/* RTC related functions */ -/* enable RTC clock calibration output */ -void bkp_rtc_calibration_output_enable(void); -/* disable RTC clock calibration output */ -void bkp_rtc_calibration_output_disable(void); -/* enable RTC alarm or second signal output */ -void bkp_rtc_signal_output_enable(void); -/* disable RTC alarm or second signal output */ -void bkp_rtc_signal_output_disable(void); -/* select RTC output */ -void bkp_rtc_output_select(uint16_t outputsel); -/* select RTC clock output */ -void bkp_rtc_clock_output_select(uint16_t clocksel); -/* select RTC clock calibration direction */ -void bkp_rtc_clock_calibration_direction_select(uint16_t direction); -/* set RTC clock calibration value */ -void bkp_rtc_calibration_value_set(uint8_t value); - -/* tamper pin related functions */ -/* enable tamper pin detection */ -void bkp_tamper_detection_enable(void); -/* disable tamper pin detection */ -void bkp_tamper_detection_disable(void); -/* set tamper pin active level */ -void bkp_tamper_active_level_set(uint16_t level); - -/* interrupt & flag functions */ -/* enable tamper interrupt */ -void bkp_interrupt_enable(void); -/* disable tamper interrupt */ -void bkp_interrupt_disable(void); -/* get tamper flag state */ -FlagStatus bkp_flag_get(void); -/* clear tamper flag state */ -void bkp_flag_clear(void); -/* get tamper interrupt flag state */ -FlagStatus bkp_interrupt_flag_get(void); -/* clear tamper interrupt flag state */ -void bkp_interrupt_flag_clear(void); - -#endif /* GD32E10X_BKP_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_can.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_can.h deleted file mode 100644 index 9b0c0125a62..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_can.h +++ /dev/null @@ -1,831 +0,0 @@ -/*! - \file gd32e10x_can.h - \brief definitions for the CAN - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_CAN_H -#define GD32E10X_CAN_H - -#include "gd32e10x.h" - -/* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ - -/* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_FDCTL(canx) REG32((canx) + 0x20U) /*!< CAN FD control register */ -#define CAN_FDSTAT(canx) REG32((canx) + 0x24U) /*!< CAN FD status register */ -#define CAN_FDTDC(canx) REG32((canx) + 0x28U) /*!< CAN FD transmitter delay compensation register */ -#define CAN_DBT(canx) REG32((canx) + 0x2CU) /*!< CAN date bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ - -/* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ - -/* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ - -/* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ - -/* bits definitions */ -/* CAN_CTL */ -#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ -#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ -#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ -#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ -#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ -#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ -#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ -#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ -#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ -#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ - -/* CAN_STAT */ -#define CAN_STAT_IWS BIT(0) /*!< initial working state */ -#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ -#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ -#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ -#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ -#define CAN_STAT_TS BIT(8) /*!< transmitting state */ -#define CAN_STAT_RS BIT(9) /*!< receiving state */ -#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ -#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ - -/* CAN_TSTAT */ -#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ -#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ -#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ -#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ -#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ -#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ -#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ -#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ -#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ -#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ -#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ -#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ -#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ -#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ -#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ -#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ -#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ -#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ -#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ -#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ -#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - -/* CAN_RFIFO0 */ -#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ -#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ -#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - -/* CAN_RFIFO1 */ -#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ -#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ -#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ - -/* CAN_INTEN */ -#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ -#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ -#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ -#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ -#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ -#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ -#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ -#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ -#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ -#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ - -/* CAN_ERR */ -#define CAN_ERR_WERR BIT(0) /*!< warning error */ -#define CAN_ERR_PERR BIT(1) /*!< passive error */ -#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ -#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ -#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ -#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ - -/* CAN_BT */ -#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ -#define CAN_BT_BS1_6_4 BITS(10,12) /*!< bit segment 1 [6:4] */ -#define CAN_BT_BS2_4_3 BITS(13,14) /*!< bit segment 2 [4:3] */ -#define CAN_BT_BS1_3_0 BITS(16,19) /*!< bit segment 1 [3:0] */ -#define CAN_BT_BS2_2_0 BITS(20,22) /*!< bit segment 2 [2:0]*/ -#define CAN_BT_SJW BITS(24,28) /*!< resynchronization jump width */ -#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ -#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - -/* CAN_FDCTL */ -#define CAN_FDCTL_FDEN BIT(0) /*!< FD operation enable */ -#define CAN_FDCTL_PRED BIT(2) /*!< protocol exception event detection disable */ -#define CAN_FDCTL_NISO BIT(3) /*!< ISO/Bosch */ -#define CAN_FDCTL_TDCEN BIT(4) /*!< transmitter delay compensation enable */ -#define CAN_FDCTL_TDCMOD BIT(5) /*!< transmitter delay compensation mode */ -#define CAN_FDCTL_ESIMOD BIT(6) /*!< error state indicator mode */ - -/* CAN_FDSTAT */ -#define CAN_FDSTAT_TDCV BITS(0,6) /*!< transmitter delay compensation value */ -#define CAN_FDSTAT_PRE BIT(16) /*!< protocol exception event */ - -/* CAN_FDTDC */ -#define CAN_FDTDC_TDCF BITS(0,6) /*!< transmitter delay compensation filter */ -#define CAN_FDTDC_TDCO BITS(8,14) /*!< transmitter delay compensation offset */ - -/* CAN_DBT */ -#define CAN_DBT_DBAUDPSC BITS(0,9) /*!< baud rate prescaler */ -#define CAN_DBT_DBS1 BITS(16,19) /*!< bit segment 1 */ -#define CAN_DBT_DBS2 BITS(20,22) /*!< bit segment 2 */ -#define CAN_DBT_DSJW BITS(24,26) /*!< resynchronization jump width */ - -/* CAN_TMIx */ -#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ -#define CAN_TMI_FT BIT(1) /*!< frame type */ -#define CAN_TMI_FF BIT(2) /*!< frame format */ -#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_TMPx */ -#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -#define CAN_TMP_ESI BIT(4) /*!< error status indicator */ -#define CAN_TMP_BRS BIT(5) /*!< bit rate of data switch */ -#define CAN_TMP_FDF BIT(7) /*!< CAN FD frame flag */ -#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ -#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_TMDATA0x */ -#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ -#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ -#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ -#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ - -/* CAN_TMDATA1x */ -#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ -#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ -#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ -#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ - -/* CAN_RFIFOMIx */ -#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ -#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ -#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_RFIFOMPx */ -#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ -#define CAN_RFIFOMP_ESI BIT(4) /*!< error status indicator */ -#define CAN_RFIFOMP_BRS BIT(5) /*!< bit rate of data switch */ -#define CAN_RFIFOMP_FDF BIT(7) /*!< CAN FD frame flag */ -#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ -#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_RFIFOMDATA0x */ -#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ -#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ -#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ -#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ - -/* CAN_RFIFOMDATA1x */ -#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ -#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ -#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ -#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ - -/* CAN_FCTL */ -#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ -#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ - -/* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ - -/* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ - -/* CAN_FAFIFO */ -#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ - -/* CAN_FW */ -#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ - -/* CAN_FxDATAy */ -#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ - -/* consts definitions */ -/* define the CAN bit position and its register index offset */ -#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) -#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) -#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ -#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ -#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ -#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ -#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ - -/* CAN flags */ -typedef enum { - /* flags in TSTAT register */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ - /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ - /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ - /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -} can_flag_enum; - -/* CAN interrupt flags */ -typedef enum { - /* interrupt flags in STAT register */ - CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ - /* interrupt flags in TSTAT register */ - CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ - CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ - CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ -} can_interrupt_flag_enum; - -/* CAN FD transmitter delay compensation parameters struct */ -typedef struct { - uint32_t tdc_mode; /*!< transmitter delay compensation mode */ - uint8_t tdc_filter; /*!< transmitter delay compensation filter */ - uint8_t tdc_offset; /*!< transmitter delay compensation offset */ -} can_fd_tdc_struct; - -/* CAN initiliaze FD frame parameters struct */ -typedef struct { - ControlStatus fd_frame; /*!< FD operation function */ - ControlStatus excp_event_detect; /*!< protocol exception event detection function*/ - ControlStatus delay_compensation; /*!< transmitter delay compensation mode */ - can_fd_tdc_struct *p_delay_compensation; /*!< pointer to the struct of the transmitter delay compensation */ - uint32_t iso_bosch; /*!< ISO/Bosch mode choice */ - uint32_t esi_mode; /*!< error state indicator mode */ - uint8_t data_resync_jump_width; /*!< CAN resynchronization jump width */ - uint8_t data_time_segment_1; /*!< time segment 1 */ - uint8_t data_time_segment_2; /*!< time segment 2 */ - uint16_t data_prescaler; /*!< baudrate prescaler */ -} can_fdframe_struct; - -/* CAN initiliaze parameters struct */ -typedef struct { - uint8_t working_mode; /*!< CAN working mode */ - uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ - uint8_t time_segment_1; /*!< time segment 1 */ - uint8_t time_segment_2; /*!< time segment 2 */ - ControlStatus time_triggered; /*!< time triggered communication mode */ - ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ - ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus auto_retrans; /*!< automatic retransmission mode */ - ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ - ControlStatus trans_fifo_order; /*!< transmit FIFO order */ - uint16_t prescaler; /*!< baudrate prescaler */ -} can_parameter_struct; - -/* CAN transmit message struct */ -typedef struct { - uint32_t tx_sfid; /*!< standard format frame identifier */ - uint32_t tx_efid; /*!< extended format frame identifier */ - uint8_t tx_ff; /*!< format of frame, standard or extended format */ - uint8_t tx_ft; /*!< type of frame, data or remote */ - uint8_t tx_dlen; /*!< data length */ - uint8_t tx_data[64]; /*!< transmit data */ - uint8_t fd_flag; /*!< CAN FD frame flag */ - uint8_t fd_brs; /*!< bit rate of data switch */ - uint8_t fd_esi; /*!< error status indicator */ -} can_trasnmit_message_struct; - -/* CAN receive message struct */ -typedef struct { - uint32_t rx_sfid; /*!< standard format frame identifier */ - uint32_t rx_efid; /*!< extended format frame identifier */ - uint8_t rx_ff; /*!< format of frame, standard or extended format */ - uint8_t rx_ft; /*!< type of frame, data or remote */ - uint8_t rx_dlen; /*!< data length */ - uint8_t rx_data[64]; /*!< receive data */ - uint8_t rx_fi; /*!< filtering index */ - uint8_t fd_flag; /*!< CAN FD frame flag */ - uint8_t fd_brs; /*!< bit rate of data switch */ - uint8_t fd_esi; /*!< error status indicator */ -} can_receive_message_struct; - -/* CAN filter parameters struct */ -typedef struct { - uint16_t filter_list_high; /*!< filter list number high bits*/ - uint16_t filter_list_low; /*!< filter list number low bits */ - uint16_t filter_mask_high; /*!< filter mask number high bits */ - uint16_t filter_mask_low; /*!< filter mask number low bits */ - uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ - uint16_t filter_number; /*!< filter number */ - uint16_t filter_mode; /*!< filter mode, list or mask */ - uint16_t filter_bits; /*!< filter scale */ - ControlStatus filter_enable; /*!< filter work or not */ -} can_filter_parameter_struct; - -/* CAN errors */ -typedef enum { - CAN_ERROR_NONE = 0, /*!< no error */ - CAN_ERROR_FILL, /*!< fill error */ - CAN_ERROR_FORMATE, /*!< format error */ - CAN_ERROR_ACK, /*!< ACK error */ - CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ - CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ - CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG, /*!< software configure */ -} can_error_enum; - -/* transmit states */ -typedef enum { - CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ -} can_transmit_state_enum; - -/* format and fifo states */ -typedef enum { - CAN_STANDARD_FIFO0 = 0, /*!< standard frame and used FIFO0 */ - CAN_STANDARD_FIFO1, /*!< standard frame and used FIFO1 */ - CAN_EXTENDED_FIFO0, /*!< extended frame and used FIFO0 */ - CAN_EXTENDED_FIFO1, /*!< extended frame and used FIFO1 */ -} can_format_fifo_enum; - -typedef enum { - CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ - CAN_FILTER_STRUCT, /* CAN filter parameters struct */ - CAN_FD_FRAME_STRUCT, /* CAN initiliaze FD frame parameters struct */ - CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ - CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ -} can_struct_type_enum; - -/* CAN baudrate prescaler*/ -#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) - -/* CAN bit segment 1*/ -#define BT_BS1(regval) ((BITS(16,19) & ((uint32_t)(regval) << 16)) | (BITS(10,12) & ((uint32_t)(regval) << 6))) -#define BT_DBS1(regval) ((BITS(16,19) & ((uint32_t)(regval) << 16))) - -/* CAN bit segment 2*/ -#define BT_BS2(regval) ((BITS(20,22) & ((uint32_t)(regval) << 20)) | (BITS(13,14) & ((uint32_t)(regval) << 10))) -#define BT_DBS2(regval) ((BITS(20,22)) & ((uint32_t)(regval) << 20)) - -/* CAN resynchronization jump width*/ -#define BT_SJW(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) -#define BT_DSJW(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) - -#define FDTDC_TDCF(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -#define FDTDC_TDCO(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) - -/* CAN communication mode*/ -#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) - -/* CAN FDATA high 16 bits */ -#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) - -/* CAN FDATA low 16 bits */ -#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) - -/* CAN1 filter start bank_number*/ -#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) - -/* CAN transmit mailbox extended identifier*/ -#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) - -/* CAN transmit mailbox standard identifier*/ -#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) - -/* transmit data byte 0 */ -#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 1 */ -#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 2 */ -#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 3 */ -#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* transmit data byte 4 */ -#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 5 */ -#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 6 */ -#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 7 */ -#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* receive mailbox extended identifier*/ -#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) - -/* receive mailbox standrad identifier*/ -#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) - -/* receive data length */ -#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) - -/* the index of the filter by which the frame is passed */ -#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 0 */ -#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 1 */ -#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 2 */ -#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 3 */ -#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* receive data byte 4 */ -#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 5 */ -#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 6 */ -#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 7 */ -#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* error number */ -#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) - -/* transmit error count */ -#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive error count */ -#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* CAN errors */ -#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ - -#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ - -/* CAN communication mode */ -#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ -#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ -#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ -#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ - -/* CAN resynchronisation jump width */ -#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ - -/* CAN time segment 1 */ -#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ -#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ -#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ -#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ -#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ -#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ -#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ -#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ -#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ - -/* CAN time segment 2 */ -#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ - -/* CAN mailbox number */ -#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ -#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ -#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ -#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ - -/* CAN frame format */ -#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ -#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ - -/* CAN receive fifo */ -#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ -#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ - -/* frame number of receive fifo */ -#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ - -#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ -#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ - -/* CAN working mode */ -#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ -#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ -#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ - -/* filter bits */ -#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ -#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ - -/* filter mode */ -#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ -#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ - -/* filter 16 bits mask */ -#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ - -/* frame type */ -#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ -#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ - -#define CAN_ESIMOD_HARDWARE ((uint32_t)0x00000000U) /*!< displays the node error state by hardware */ -#define CAN_ESIMOD_SOFTWARE CAN_FDCTL_ESIMOD /*!< displays the node error state by software */ - -#define CAN_TDCMOD_CALC_AND_OFFSET ((uint32_t)0x00000000U) /*!< measurement and offset */ -#define CAN_TDCMOD_OFFSET CAN_FDCTL_TDCMOD /*!< only offset */ - -#define CAN_FDMOD_ISO ((uint32_t)0x00000000U) /*!< ISO mode */ -#define CAN_FDMOD_BOSCH CAN_FDCTL_NISO /*!< BOSCH mode */ - - -/* CAN FD frame flag */ -#define CAN_FDF_CLASSIC (0U) /*!< classical frames */ -#define CAN_FDF_FDFRAME (1U) /*!< FD frames */ - -/* bit rate of data switch */ -#define CAN_BRS_DISABLE (0U) /*!< bit rate not switch */ -#define CAN_BRS_ENABLE (1U) /*!< the bit rate shall be switched */ - -/* error status indicator */ -#define CAN_ESI_DOMINANT (0U) /*!< transmit the dominant bit in ESI phase */ -#define CAN_ESI_RECESSIVE (1U) /*!< transmit the recessive bit in ESI phase */ - -/* CAN timeout */ -#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ - -/* interrupt enable bits */ -#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ -#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ -#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ -#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ -#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ -#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ -#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ -#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ -#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ -#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ - -/* function declarations */ -/* deinitialize CAN */ -void can_deinit(uint32_t can_periph); -/* initialize CAN struct */ -void can_struct_para_init(can_struct_type_enum type, void *p_struct); -/* initialize CAN */ -#ifdef GD_MBED_USED -ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); -#else -ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); -#endif -/* initialize CAN FD function */ -ErrStatus can_fd_init(uint32_t can_periph, can_fdframe_struct *can_fdframe_init); -/* CAN filter init */ -void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); -/* CAN filter mask mode initialization */ -void can_filter_mask_mode_init(uint32_t id, uint32_t mask, can_format_fifo_enum format_fifo, uint16_t filter_number); -/* CAN frequency configuration */ -ErrStatus can_frequency_set(uint32_t can_periph, uint32_t hz); -/* CAN FD frequency configuration */ -ErrStatus can_fd_frequency_set(uint32_t can_periph, uint32_t hz); -/* CAN communication mode configure */ -ErrStatus can_monitor_mode_set(uint32_t can_periph, uint8_t mode); -/* CAN FD frame function enable */ -void can_fd_function_enable(uint32_t can_periph); -/* CAN FD frame function disable */ -void can_fd_function_disable(uint32_t can_periph); - -/* set can1 fliter start bank number */ -void can1_filter_start_bank(uint8_t start_bank); -/* enable functions */ -/* CAN debug freeze enable */ -void can_debug_freeze_enable(uint32_t can_periph); -/* CAN debug freeze disable */ -void can_debug_freeze_disable(uint32_t can_periph); -/* CAN time trigger mode enable */ -void can_time_trigger_mode_enable(uint32_t can_periph); -/* CAN time trigger mode disable */ -void can_time_trigger_mode_disable(uint32_t can_periph); - -/* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); -/* get CAN transmit state */ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); -/* stop CAN transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); -/* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); -/* CAN release fifo */ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); -/* CAN receive message length */ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); -/* CAN working mode */ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); -/* CAN wakeup from sleep mode */ -ErrStatus can_wakeup(uint32_t can_periph); - -/* CAN get error */ -can_error_enum can_error_get(uint32_t can_periph); -/* get CAN receive error number */ -uint8_t can_receive_error_number_get(uint32_t can_periph); -/* get CAN transmit error number */ -uint8_t can_transmit_error_number_get(uint32_t can_periph); - -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); -/* CAN get flag state */ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); -/* CAN clear flag state */ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag); -/* CAN get interrupt flag state */ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); -/* CAN clear interrupt flag state */ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); - -#endif /* GD32E10X_CAN_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_crc.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_crc.h deleted file mode 100644 index 6628855bd6f..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_crc.h +++ /dev/null @@ -1,81 +0,0 @@ -/*! - \file gd32e10x_crc.h - \brief definitions for the CRC - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_CRC_H -#define GD32E10X_CRC_H - -#include "gd32e10x.h" - -/* CRC definitions */ -#define CRC CRC_BASE - -/* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ - - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ -void crc_data_register_reset(void); -/* read the value of the data register */ -uint32_t crc_data_register_read(void); - -/* read the value of the free data register */ -uint8_t crc_free_data_register_read(void); -/* write data to the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* calculate the CRC value of a 32-bit data */ -uint32_t crc_single_data_calculate(uint32_t sdata); -/* calculate the CRC value of an array of 32-bit values */ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); - -#endif /* GD32E10X_CRC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_ctc.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_ctc.h deleted file mode 100644 index f40c9cab909..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_ctc.h +++ /dev/null @@ -1,186 +0,0 @@ -/*! - \file gd32e10x_ctc.h - \brief definitions for the CTC - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_CTC_H -#define GD32E10X_CTC_H - -#include "gd32e10x.h" - -/* CTC definitions */ -#define CTC CTC_BASE - -/* registers definitions */ -#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ -#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ -#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */ -#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */ - -/* bits definitions */ -/* CTC_CTL0 */ -#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ -#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ -#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ -#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ -#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ -#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ -#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ -#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ - -/* CTC_CTL1 */ -#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ -#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ -#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ -#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ - -/* CTC_STAT */ -#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ -#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ -#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ -#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ -#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ -#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ -#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ -#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ -#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ - -/* CTC_INTC */ -#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ -#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ -#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ -#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ - -/* constants definitions */ -/* hardware automatically trim mode definitions */ -#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ -#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ - -/* reference signal source polarity definitions */ -#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ -#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ - -/* reference signal source selection definitions */ -#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ -#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */ -#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFS_SOF is selected */ - -/* reference signal source prescaler definitions */ -#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ -#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ -#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ -#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ -#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ -#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ -#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ -#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ - -/* CTC interrupt enable definitions */ -#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ -#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ -#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ -#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ - -/* CTC interrupt source definitions */ -#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ -#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ -#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ -#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ -#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ - -/* CTC flag definitions */ -#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ -#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ -#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ -#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ -#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ - -/* function declarations */ -/* reset ctc clock trim controller */ -void ctc_deinit(void); -/* enable CTC trim counter */ -void ctc_counter_enable(void); -/* disable CTC trim counter */ -void ctc_counter_disable(void); - -/* configure the IRC48M trim value */ -void ctc_irc48m_trim_value_config(uint8_t trim_value); -/* generate software reference source sync pulse */ -void ctc_software_refsource_pulse_generate(void); -/* configure hardware automatically trim mode */ -void ctc_hardware_trim_mode_config(uint32_t hardmode); - -/* configure reference signal source polarity */ -void ctc_refsource_polarity_config(uint32_t polarity); -/* select reference signal source */ -void ctc_refsource_signal_select(uint32_t refs); -/* configure reference signal source prescaler */ -void ctc_refsource_prescaler_config(uint32_t prescaler); -/* configure clock trim base limit value */ -void ctc_clock_limit_value_config(uint8_t limit_value); -/* configure CTC counter reload value */ -void ctc_counter_reload_value_config(uint16_t reload_value); - -/* read CTC counter capture value when reference sync pulse occurred */ -uint16_t ctc_counter_capture_value_read(void); -/* read CTC trim counter direction when reference sync pulse occurred */ -FlagStatus ctc_counter_direction_read(void); -/* read CTC counter reload value */ -uint16_t ctc_counter_reload_value_read(void); -/* read the IRC48M trim value */ -uint8_t ctc_irc48m_trim_value_read(void); - -/* interrupt & flag functions */ -/* enable the CTC interrupt */ -void ctc_interrupt_enable(uint32_t interrupt); -/* disable the CTC interrupt */ -void ctc_interrupt_disable(uint32_t interrupt); -/* get CTC interrupt flag */ -FlagStatus ctc_interrupt_flag_get(uint32_t interrupt); -/* clear CTC interrupt flag */ -void ctc_interrupt_flag_clear(uint32_t interrupt); -/* get CTC flag */ -FlagStatus ctc_flag_get(uint32_t flag); -/* clear CTC flag */ -void ctc_flag_clear(uint32_t flag); - -#endif /* GD32E10X_CTC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dac.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dac.h deleted file mode 100644 index 982a1aab368..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dac.h +++ /dev/null @@ -1,246 +0,0 @@ -/*! - \file gd32e10x_dac.h - \brief definitions for the DAC - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_DAC_H -#define GD32E10X_DAC_H - -#include "gd32e10x.h" - -/* DACx(x=0,1) definitions */ -#define DAC DAC_BASE -#define DAC0 0U -#define DAC1 1U - -/* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ - -/* bits definitions */ -/* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ - -/* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - -/* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - -/* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - -/* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - -/* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - -/* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - -/* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - -/* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - -/* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - -/* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - -/* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ - -/* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ - -/* constants definitions */ -/* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - -/* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - -/* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ - -/* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ - -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ - -/* function declarations */ -/* initialization functions */ -/* deinitialize DAC */ -void dac_deinit(void); -/* enable DAC */ -void dac_enable(uint32_t dac_periph); -/* disable DAC */ -void dac_disable(uint32_t dac_periph); -/* enable DAC DMA */ -void dac_dma_enable(uint32_t dac_periph); -/* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); -/* enable DAC output buffer */ -void dac_output_buffer_enable(uint32_t dac_periph); -/* disable DAC output buffer */ -void dac_output_buffer_disable(uint32_t dac_periph); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); - -/* DAC trigger configuration */ -/* enable DAC trigger */ -void dac_trigger_enable(uint32_t dac_periph); -/* disable DAC trigger */ -void dac_trigger_disable(uint32_t dac_periph); -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); -/* enable DAC software trigger */ -void dac_software_trigger_enable(uint32_t dac_periph); -/* disable DAC software trigger */ -void dac_software_trigger_disable(uint32_t dac_periph); - -/* DAC wave mode configuration */ -/* configure DAC wave mode */ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); -/* configure DAC wave bit width */ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); -/* configure DAC LFSR noise mode */ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); -/* configure DAC triangle noise mode */ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); - -/* DAC concurrent mode configuration */ -/* enable DAC concurrent mode */ -void dac_concurrent_enable(void); -/* disable DAC concurrent mode */ -void dac_concurrent_disable(void); -/* enable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_enable(void); -/* disable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_disable(void); -/* enable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_enable(void); -/* disable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_disable(void); -/* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); - -#endif /* GD32E10X_DAC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dbg.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dbg.h deleted file mode 100644 index e6c8d97a58a..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dbg.h +++ /dev/null @@ -1,138 +0,0 @@ -/*! - \file gd32e10x_dbg.h - \brief definitions for the DBG - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_DBG_H -#define GD32E10X_DBG_H - -#include "gd32e10x.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL */ -#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ -#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ -#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ -#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ -#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ -#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ -#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ -#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ -#define DBG_CTL_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */ -#define DBG_CTL_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */ -#define DBG_CTL_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */ -#define DBG_CTL_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */ -#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ -#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ -#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ -#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ -#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ -#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ -#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ - -/* constants definitions */ -#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ - -/* debug hold when core is halted */ -typedef enum { - DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ - DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ - DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ - DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ - DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ - DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ - DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */ - DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ - DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ - DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ - DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ - DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ -} dbg_periph_enum; - -/* DBG_CTL0_TRACE_MODE configurations */ -#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) -#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ -#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ -#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ -#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ - -/* function declarations */ -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -/* enable trace pin assignment */ -void dbg_trace_pin_enable(void); -/* disable trace pin assignment */ -void dbg_trace_pin_disable(void); -/* set trace pin mode */ -void dbg_trace_pin_mode_set(uint32_t trace_mode); - -#endif /* GD32E10X_DBG_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dma.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dma.h deleted file mode 100644 index aabc5f03b51..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_dma.h +++ /dev/null @@ -1,275 +0,0 @@ -/*! - \file gd32e10x_dma.h - \brief definitions for the DMA - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_DMA_H -#define GD32E10X_DMA_H - -#include "gd32e10x.h" - -/* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ - -/* registers definitions */ -#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ -#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ -#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ - -/* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ - -/* DMA_CHxCTL, x=0..6 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - -/* DMA_CHxCNT,x=0..6 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR,x=0..6 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxMADDR,x=0..6 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum { - DMA_CH0 = 0, /*!< DMA channel 0 */ - DMA_CH1, /*!< DMA channel 1 */ - DMA_CH2, /*!< DMA channel 2 */ - DMA_CH3, /*!< DMA channel 3 */ - DMA_CH4, /*!< DMA channel 4 */ - DMA_CH5, /*!< DMA channel 5 */ - DMA_CH6 /*!< DMA channel 6 */ -} dma_channel_enum; - -/* DMA initialize struct */ -typedef struct { - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ -} dma_parameter_struct; - -#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ - -/* DMA_register address */ -#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ - DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ - -/* flag bits */ -#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ -#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ - -/* DMA_CHxCTL register */ -/* interrupt enable bits */ -#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ - -/* transfer direction */ -#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x0000U) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x0001U) /*!< read from memory and write to peripheral */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of peripheral is increasing address mode */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of memory is fixed address mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ - -/* transfer data size of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ -#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ -#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ -#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ - -/* transfer data size of memory */ -#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ -#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ - -/* DMA_CHxCNT register */ -/* transfer counter */ -#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ - -/* function declarations */ -/* DMA deinitialization and initialization functions */ -/* deinitialize DMA a channel registers */ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); -/* initialize the parameters of DMA struct with the default values */ -void dma_struct_para_init(dma_parameter_struct *init_struct); -/* initialize DMA channel */ -#ifdef GD_MBED_USED -void dma_para_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); -#else -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); -#endif -/* enable DMA circulation mode */ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable memory to memory mode */ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable memory to memory mode */ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); - -/* DMA configuration functions */ -/* set DMA peripheral base address */ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set DMA memory base address */ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); -/* configure priority level of DMA channel */ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); -/* configure transfer data size of memory */ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); -/* configure transfer data size of peripheral */ -void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); -/* enable next address increasement algorithm of memory */ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of memory */ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable next address increasement algorithm of peripheral */ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of peripheral */ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); - -/* flag and interrupt functions */ -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the flag of a DMA channel */ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the interrupt flag of a DMA channel */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* enable DMA interrupt */ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); - -#endif /* GD32E10X_DMA_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_exmc.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_exmc.h deleted file mode 100644 index b80573805da..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_exmc.h +++ /dev/null @@ -1,212 +0,0 @@ -/*! - \file gd32e10x_exmc.h - \brief definitions for the EXMC - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_EXMC_H -#define GD32E10X_EXMC_H - -#include "gd32e10x.h" - -/* EXMC definitions */ -#define EXMC (EXMC_BASE) /*!< EXMC register base address */ - -/* registers definitions */ -/* NOR/PSRAM */ -#define EXMC_SNCTL REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register */ - -/* bits definitions */ -/* EXMC_SNCTL */ -#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR region enable */ -#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR region memory address/data multiplexing */ -#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR region memory type */ -#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR region memory data bus width */ -#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ -#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ -#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ -#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ -#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ -#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ -#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ -#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ - -/* EXMC_SNTCFG */ -#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ -#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* EXMC_SNWTCFG */ -#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* constants definitions */ -/* EXMC NOR/SRAM timing initialize struct */ -typedef struct { - uint32_t asyn_access_mode; /*!< asynchronous access mode */ - uint32_t syn_data_latency; /*!< configure the data latency */ - uint32_t syn_clk_division; /*!< configure the clock divide ratio */ - uint32_t bus_latency; /*!< configure the bus latency, the value can be 1 ~ 16, can't be 0 */ - uint32_t asyn_data_setuptime; /*!< configure the data setup time, the value can be 2 ~ 256, can't be 0 */ - uint32_t asyn_address_holdtime; /*!< configure the address hold time, the value can be 2 ~ 16, can't be 0 */ - uint32_t asyn_address_setuptime; /*!< configure the address setup time, the value can be 1 ~ 16, can't be 0 */ -} exmc_norsram_timing_parameter_struct; - -/* EXMC NOR/SRAM initialize struct */ -typedef struct { - uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ - uint32_t extended_mode; /*!< enable or disable the extended mode */ - uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ - uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ - uint32_t memory_write; /*!< enable or disable the write operation */ - uint32_t nwait_config; /*!< NWAIT signal configuration */ - uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ - uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ - uint32_t burst_mode; /*!< enable or disable the burst mode */ - uint32_t databus_width; /*!< specifies the databus width of external memory */ - uint32_t memory_type; /*!< specifies the type of external memory */ - uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct *read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing - parameters for read if the extended mode is used */ - exmc_norsram_timing_parameter_struct *write_timing; /*!< timing parameters for write when the extended mode is used */ -} exmc_norsram_parameter_struct; - -/* CRAM page size */ -#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ -#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ -#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ -#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ -#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ - -/* NOR region memory data bus width */ -#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ -#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ - -/* NOR region memory type */ -#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ -#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ -#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ - -/* asynchronous access mode */ -#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ -#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ -#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ -#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ - -/* data latency for NOR flash */ -#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ -#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ -#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ -#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ -#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ -#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ -#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ -#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ -#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ -#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ -#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ -#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ -#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ -#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ -#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ -#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ - -/* synchronous clock divide ratio */ -#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ - -/* EXMC NOR/SRAM write mode */ -#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ -#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ - -/* EXMC NWAIT signal configuration */ -#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ -#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ - -/* EXMC NWAIT signal polarity configuration */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ -#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ - -/* function declarations */ -/* NOR/SRAM initializtion */ -/* deinitialize EXMC NOR/SRAM bank */ -void exmc_norsram_deinit(void); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct); -/* initialize EXMC NOR/SRAM bank */ -void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct); - -/* NOR/SRAM enable */ -/* enable EXMC NOR/SRAM bank */ -void exmc_norsram_enable(void); -/* disable EXMC NOR/SRAM bank */ -void exmc_norsram_disable(void); - -/* NOR/SRAM configuration */ -/* configure CRAM page size */ -void exmc_norsram_page_size_config(uint32_t page_size); - -#endif /* GD32E10X_EXMC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_exti.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_exti.h deleted file mode 100644 index dc8602385ca..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_exti.h +++ /dev/null @@ -1,246 +0,0 @@ -/*! - \file gd32e10x_exti.h - \brief definitions for the EXTI - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_EXTI_H -#define GD32E10X_EXTI_H - -#include "gd32e10x.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum { - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ -} exti_line_enum; - -/* external interrupt and event */ -typedef enum { - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -} exti_mode_enum; - -/* interrupt trigger mode */ -typedef enum { - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ -} exti_trig_type_enum; - -/* function declarations */ -/* deinitialize the EXTI */ -void exti_deinit(void); -/* enable the configuration of EXTI initialize */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); - -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); - -/* get EXTI lines pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines interrupt pending flag */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines interrupt pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); -/* enable the EXTI software interrupt */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* disable the EXTI software interrupt */ -void exti_software_interrupt_disable(exti_line_enum linex); - -#endif /* GD32E10X_EXTI_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_fmc.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_fmc.h deleted file mode 100644 index c20c04fd24d..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_fmc.h +++ /dev/null @@ -1,337 +0,0 @@ -/*! - \file gd32e10x_fmc.h - \brief definitions for the FMC - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_FMC_H -#define GD32E10X_FMC_H - -#include "gd32e10x.h" - -/* FMC and option bytes definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option bytes base address */ - -/* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ -#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ -#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ -#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ - -#define OB_SPC REG32((OB) + 0x00U) /*!< option bytes security protection register */ -#define OB_USER REG32((OB) + 0x02U) /*!< option bytes user register */ -#define OB_DATA0 REG16((OB) + 0x04U) /*!< option bytes data register 0 */ -#define OB_DATA1 REG16((OB) + 0x06U) /*!< option bytes data register 1 */ -#define OB_WP0 REG32((OB) + 0x08U) /*!< option bytes write protection register 0 */ -#define OB_WP1 REG32((OB) + 0x0AU) /*!< option bytes write protection register 1 */ -#define OB_WP2 REG32((OB) + 0x0CU) /*!< option bytes write protection register 2 */ -#define OB_WP3 REG32((OB) + 0x0EU) /*!< option bytes write protection register 3 */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ -#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */ -#define FMC_WS_ICEN BIT(9) /*!< IBUS cache enable */ -#define FMC_WS_DCEN BIT(10) /*!< DBUS cache enable */ -#define FMC_WS_ICRST BIT(11) /*!< IBUS cache reset */ -#define FMC_WS_DCRST BIT(12) /*!< DBUS cache reset */ -#define FMC_WS_PGW BIT(15) /*!< program width to flash memory */ - -/* FMC_KEY */ -#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ - -/* FMC_STAT */ -#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT_PGAERR BIT(3) /*!< flash program alignment error flag bit */ -#define FMC_STAT_WPERR BIT(4) /*!< erase/program protection error flag bit */ -#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL */ -#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ -#define FMC_CTL_PER BIT(1) /*!< main flash page erase command bit */ -#define FMC_CTL_MER BIT(2) /*!< main flash mass erase command bit */ -#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ -#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ -#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL_LK BIT(7) /*!< FMC_CTL lock bit */ -#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ -#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - -/* FMC_ADDR */ -#define FMC_ADDR_ADDR BITS(0,31) /*!< flash erase/program command address bits */ - -/* FMC_OBSTAT */ -#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ -#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ -#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ -#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ - -/* FMC_WP */ -#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* define the FMC bit position and its register index offset */ -#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) -#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) -#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) - -/* configuration register */ -#define FMC_STAT_REG_OFFSET 0x0CU /*!< status register offset */ -#define FMC_CTL_REG_OFFSET 0x10U /*!< control register offset */ -#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option bytes status register offset */ - -/* fmc state */ -typedef enum { - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_PGAERR, /*!< program alignment error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ -} fmc_state_enum; - -/* FMC interrupt enable */ -typedef enum { - FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ - FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ -} fmc_int_enum; - -/* FMC flags */ -typedef enum { - FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 0U), /*!< FMC busy flag */ - FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 2U), /*!< FMC operation error flag bit */ - FMC_FLAG_PGAERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 3U), /*!< FMC program alignment error flag */ - FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */ - FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */ - FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ -} fmc_flag_enum; - -/* FMC interrupt flags */ -typedef enum { - FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */ - FMC_INT_FLAG_PGAERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 3U, 10U), /*!< FMC program alignment error interrupt flag bit */ - FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */ -} fmc_interrupt_flag_enum; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -/* FMC wait state counter */ -#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -#define FMC_WAIT_STATE_0 WS_WSCNT(0) /*!< FMC 0 wait */ -#define FMC_WAIT_STATE_1 WS_WSCNT(1) /*!< FMC 1 wait */ -#define FMC_WAIT_STATE_2 WS_WSCNT(2) /*!< FMC 2 wait */ -#define FMC_WAIT_STATE_3 WS_WSCNT(3) /*!< FMC 3 wait */ - -/* adc_ctl1 register value */ -#define FMC_PROG_W_64B ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define FMC_PROG_W_32B FMC_WS_PGW /*!< MSB alignment */ - -#define OB_USER_MASK ((uint8_t)0xF8U) /*!< MASK value */ - -/* read protect configure */ -#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ -#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ - -/* OB_SPC */ -#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ -#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ - -/* option bytes software/hardware free watch dog timer */ -#define OB_FWDGT_SOFTWARE ((uint8_t)0x01U) /*!< software free watchdog */ -#define OB_FWDGT_HARDWARE ((uint8_t)0x00U) /*!< hardware free watchdog */ - -/* option bytes reset or not entering deep sleep mode */ -#define OB_DEEPSLEEP_NO_RST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ -#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ - -/* option bytes reset or not entering standby mode */ -#define OB_STDBY_NO_RST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ -#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ - -/* OB_USER */ -#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ -#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ - -/* option byte data address */ -#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */ -#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */ - -/* OB_WP0 */ -#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ - -/* OB_WP1 */ -#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ - -/* OB_WP2 */ -#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ - -/* OB_WP3 */ -#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ - -/* option bytes write protection */ -#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ -#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ -#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ -#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ -#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ -#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ -#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ -#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ -#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ -#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ -#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ -#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ -#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ -#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ -#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ -#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ -#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ -#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ -#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ -#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ -#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ - -/* FMC timeout */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ - -/* function declarations */ -/* FMC main memory programming functions */ -/* set the FMC wait state counter */ -void fmc_wscnt_set(uint32_t wscnt); -/* enable pre-fetch */ -void fmc_prefetch_enable(void); -/* disable pre-fetch */ -void fmc_prefetch_disable(void); -/* enable IBUS cache */ -void fmc_ibus_enable(void); -/* disable IBUS cache */ -void fmc_ibus_disable(void); -/* enable DBUS cache */ -void fmc_dbus_enable(void); -/* disable DBUS cache */ -void fmc_dbus_disable(void); -/* reset IBUS cache */ -void fmc_ibus_reset(void); -/* reset DBUS cache */ -void fmc_dbus_reset(void); -/* set program width to flash memory */ -void fmc_program_width_set(uint32_t pgw); -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* FMC erase page */ -fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC program a double word at the corresponding address */ -fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); -/* FMC program a half word at the corresponding address */ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); - -/* FMC option bytes programming functions */ -/* unlock the option bytes operation */ -void ob_unlock(void); -/* lock the option bytes operation */ -void ob_lock(void); -/* erase the option bytes */ -fmc_state_enum ob_erase(void); -/* enable write protect */ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); -/* configure the option bytes security protection */ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option bytes */ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby); -/* program option bytes data */ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data); -/* get the FMC option bytes user */ -uint8_t ob_user_get(void); -/* get OB_DATA in register FMC_OBSTAT */ -uint16_t ob_data_get(void); -/* get the FMC option bytes write protection */ -uint32_t ob_write_protection_get(void); -/* get option bytes security protection state */ -FlagStatus ob_security_protection_flag_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); -/* check flag is set or not */ -FlagStatus fmc_flag_get(uint32_t flag); -/* clear the FMC flag */ -void fmc_flag_clear(uint32_t flag); -/* get FMC interrupt flag state */ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); -/* clear FMC interrupt flag state */ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); - -#endif /* GD32E10X_FMC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_fwdgt.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_fwdgt.h deleted file mode 100644 index 6af57b8ef42..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_fwdgt.h +++ /dev/null @@ -1,107 +0,0 @@ -/*! - \file gd32e10x_fwdgt.h - \brief definitions for the FWDGT - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_FWDGT_H -#define GD32E10X_FWDGT_H - -#include "gd32e10x.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE - -/* registers definitions */ -#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ - -/* constants definitions */ -/* psc register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ - -/* function declarations */ -/* enable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_enable(void); -/* disable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32E10X_FWDGT_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_gpio.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_gpio.h deleted file mode 100644 index ffde7ebb958..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_gpio.h +++ /dev/null @@ -1,484 +0,0 @@ -/*! - \file gd32e10x_gpio.h - \brief definitions for the GPIO - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_GPIO_H -#define GD32E10X_GPIO_H - -#include "gd32e10x.h" - -/* GPIOx(x=A,B,C,D,E) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOD (GPIO_BASE + 0x00000C00U) -#define GPIOE (GPIO_BASE + 0x00001000U) - -/* AFIO definitions */ -#define AFIO AFIO_BASE - -/* registers definitions */ -/* GPIO registers definitions */ -#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ -#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ -#define GPIOx_SPD(gpiox) REG32((gpiox) + 0x3CU) /*!< GPIO port bit speed register */ - -/* AFIO registers definitions */ -#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ -#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ -#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ -#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ -#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ -#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ -#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ -#define AFIO_CPSCTL REG32(AFIO + 0x20U) /*!< IO compensation control register */ - -/* bits definitions */ -/* GPIO_CTL0 */ -#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ -#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ -#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ -#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ -#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ -#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ -#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ -#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ -#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ -#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ -#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ -#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ -#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ -#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ -#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ -#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ - -/* GPIO_CTL1 */ -#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ -#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ -#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ -#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ -#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ -#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ -#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ -#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ -#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ -#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ -#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ -#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ -#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ -#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ -#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ -#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* GPIO_SPD */ -#define GPIO_SPD_SPD0 BIT(0) /*!< pin 0 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD1 BIT(1) /*!< pin 1 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD2 BIT(2) /*!< pin 2 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD3 BIT(3) /*!< pin 3 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD4 BIT(4) /*!< pin 4 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD5 BIT(5) /*!< pin 5 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD6 BIT(6) /*!< pin 6 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD7 BIT(7) /*!< pin 7 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD8 BIT(8) /*!< pin 8 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD9 BIT(9) /*!< pin 9 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD10 BIT(10) /*!< pin 10 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD11 BIT(11) /*!< pin 11 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD12 BIT(12) /*!< pin 12 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD13 BIT(13) /*!< pin 13 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD14 BIT(14) /*!< pin 14 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ - -/* AFIO_EC */ -#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ -#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ -#define AFIO_EC_EOE BIT(7) /*!< event output enable */ - -/* AFIO_PCF0 */ -/* memory map and bit definitions */ -#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ -#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ -#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ -#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ -#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ -#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ -#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ -#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ -#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ -#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ -#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ -#define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ -#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ -#define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ - -/* AFIO_EXTISS0 */ -#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ -#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ -#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ -#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ - -/* AFIO_EXTISS1 */ -#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ -#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ -#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ -#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ - -/* AFIO_EXTISS2 */ -#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ -#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ -#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ -#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ - -/* AFIO_EXTISS3 */ -#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ -#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ -#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ -#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ - -/* AFIO_PCF1 */ -#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ -#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ -#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ - -/* AFIO_CPSCTL */ -#define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ -#define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* GPIO mode values set */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) -#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) - -/* GPIO mode definitions */ -#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ -#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ -#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ -#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ -#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ -#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ -#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ -#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ - -/* GPIO output max speed value */ -#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ -#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ -#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ -#define GPIO_OSPEED_MAX ((uint8_t)0x04U) /*!< GPIO very high output speed, max speed more than 50MHz */ - -/* GPIO event output port definitions */ -#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ -#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ -#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ -#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ -#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ - -/* GPIO output port source definitions */ -#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ -#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ -#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ -#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ -#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ - -/* GPIO event output pin definitions */ -#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ -#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ -#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ -#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ -#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ -#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ -#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ -#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ -#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ -#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ -#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ -#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ -#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ -#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ -#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ -#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ - -/* GPIO output pin source definitions */ -#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ -#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ -#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ -#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ -#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ -#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ -#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ -#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ -#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ -#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ -#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ -#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ -#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ -#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ -#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ -#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ - -/* AFIO remap */ -#define PCF0_USART2_REMAP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ -#define PCF0_TIMER0_REMAP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ -#define PCF0_TIMER1_REMAP(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ -#define PCF0_TIMER2_REMAP(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ -#define PCF0_CAN_REMAP(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ -#define PCF0_SWJ_CFG(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ -#define PCF1_CTC_REMAP(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ - -/* GPIO remap definitions */ -#define GPIO_SPI0_REMAP AFIO_PCF0_SPI0_REMAP /*!< SPI0 remapping */ -#define GPIO_I2C0_REMAP AFIO_PCF0_I2C0_REMAP /*!< I2C0 remapping */ -#define GPIO_USART0_REMAP AFIO_PCF0_USART0_REMAP /*!< USART0 remapping */ -#define GPIO_USART1_REMAP AFIO_PCF0_USART1_REMAP /*!< USART1 remapping */ -#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140000U | PCF0_USART2_REMAP(1)) /*!< USART2 partial remapping */ -#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140000U | PCF0_USART2_REMAP(3)) /*!< USART2 full remapping */ -#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160000U | PCF0_TIMER0_REMAP(1)) /*!< TIMER0 partial remapping */ -#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x00160000U | PCF0_TIMER0_REMAP(3)) /*!< TIMER0 full remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(1)) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(2)) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(3)) /*!< TIMER1 full remapping */ -#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0000U | PCF0_TIMER2_REMAP(2)) /*!< TIMER2 partial remapping */ -#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0000U | PCF0_TIMER2_REMAP(3)) /*!< TIMER2 full remapping */ -#define GPIO_TIMER3_REMAP AFIO_PCF0_TIMER3_REMAP /*!< TIMER3 remapping */ -#define GPIO_PD01_REMAP AFIO_PCF0_PD01_REMAP /*!< PD01 remapping */ -#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER4CH3_IREMAP >> 16)) /*!< TIMER4 channel3 internal remapping */ -#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGINS_REMAP >> 16)) /*!< ADC 0 external trigger inserted conversion remapping */ -#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGREG_REMAP >> 16)) /*!< ADC 0 external trigger regular conversion remapping */ -#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGINS_REMAP >> 16)) /*!< ADC 1 external trigger inserted conversion remapping */ -#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGREG_REMAP >> 16)) /*!< ADC 1 external trigger regular conversion remapping */ -#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(1) >> 16)) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ -#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(2) >> 16)) /*!< JTAG-DP disabled and SW-DP enabled */ -#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(4) >> 16)) /*!< JTAG-DP disabled and SW-DP disabled */ -#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D0000U | PCF0_CAN_REMAP(2)) /*!< CAN0 partial remapping */ -#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D0000U | PCF0_CAN_REMAP(3)) /*!< CAN0 full remapping */ -#define GPIO_CAN1_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_CAN1_REMAP >> 16)) /*!< CAN1 remapping */ -#define GPIO_SPI2_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_SPI2_REMAP >> 16)) /*!< SPI2 remapping */ -#define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER1ITR0_REMAP >> 16)) /*!< TIMER1 internal trigger 0 remapping */ -#define GPIO_TIMER8_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER8_REMAP) /*!< TIMER8 remapping */ -#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_EXMC_NADV) /*!< EXMC_NADV connect/disconnect */ -#define GPIO_CTC_REMAP0 ((uint32_t)0x801B0000U | PCF1_CTC_REMAP(1)) /*!< CTC remapping(PD15)*/ - -/* I/O compensation cell enable/disable */ -#define GPIO_COMPENSATION_ENABLE AFIO_CPSCTL_CPS_EN /*!< I/O compensation cell is enable */ -#define GPIO_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell is disable */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* reset alternate function I/O(AFIO) */ -void gpio_afio_deinit(void); -/* GPIO parameter initialization */ -#ifdef GD_MBED_USED -void gpio_para_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); -#else -void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); -#endif -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* configure GPIO pin remap */ -void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); - -/* select GPIO pin exti sources */ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); -/* configure GPIO pin event output */ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); -/* enable GPIO pin event output */ -void gpio_event_output_enable(void); -/* disable GPIO pin event output */ -void gpio_event_output_disable(void); - -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -/* configure the I/O compensation cell */ -void gpio_compensation_config(uint32_t compensation); -/* check the I/O compensation cell is ready or not */ -FlagStatus gpio_compensation_flag_get(void); - -#endif /* GD32E10X_GPIO_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_i2c.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_i2c.h deleted file mode 100644 index e54adf7519a..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_i2c.h +++ /dev/null @@ -1,427 +0,0 @@ -/*! - \file gd32e10x_i2c.h - \brief definitions for the I2C - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_I2C_H -#define GD32E10X_I2C_H - -#include "gd32e10x.h" - -/* I2Cx(x=0,1) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ -#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */ -#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ - -/* I2Cx_SAMCS */ -#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ -#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ -#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ -#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ -#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ -#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ -#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ -#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ -#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ -#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ -#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ -#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ - -/* I2Cx_FMPCFG */ -#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ - -/* constants definitions */ -/* define the I2C bit position and its register index offset */ -#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ - -/* I2C flags */ -typedef enum { - /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ - /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ - /* flags in SAMCS register */ - I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ - I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ - I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ - I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ -} i2c_flag_enum; - -/* I2C interrupt flags */ -typedef enum { - /* interrupt flags in CTL1 register */ - I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ - I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ - I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ - I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ - I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ - I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ - I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ - I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ - I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ - I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ - /* interrupt flags in SAMCS register */ - I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ - I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ - I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ - I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ -} i2c_interrupt_flag_enum; - -/* I2C interrupt enable or disable */ -typedef enum { - /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ - /* interrupt in SAMCS register */ - I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */ - I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */ - I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */ - I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */ -} i2c_interrupt_enum; - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ - -/* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ - -/* fast mode plus enable */ -#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ -#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C duty cycle in fast mode or fast mode plus */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ - -/* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ - -#ifdef GD_MBED_USED -#define SLAVE10_FIRST_BYTE(addr10) ((0xF0) | (uint8_t)((addr10 & 0x0300)>>7)) -#define SLAVE10_SECOND_BYTE(addr10) ((uint8_t)(addr10 & 0x00FF)) - -typedef enum { - I2C_MODE_NONE = 0x00U, /*!< I2C device is idle */ - I2C_MODE_MASTER = 0x10U, /*!< I2C device is in Master Mode */ - I2C_MODE_SLAVE = 0x20U /*!< I2C device is in Slave Mode */ -} i2c_mode_enum; - -/* I2C state definitions */ -#define I2C_STATE_MSK ((uint32_t)((OP_STATE_BUSY_TX | OP_STATE_BUSY_RX) & (~(uint32_t)OP_STATE_BUSY))) -#define I2C_STATE_NONE ((uint32_t)(I2C_MODE_NONE)) -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((OP_STATE_BUSY_TX & I2C_STATE_MSK) | I2C_MODE_MASTER)) -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((OP_STATE_BUSY_RX & I2C_STATE_MSK) | I2C_MODE_MASTER)) -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((OP_STATE_BUSY_TX & I2C_STATE_MSK) | I2C_MODE_SLAVE)) -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((OP_STATE_BUSY_RX & I2C_STATE_MSK) | I2C_MODE_SLAVE)) - -#define I2C_FIRST_FRAME 0x00000001U -#define I2C_NEXT_FRAME 0x00000002U -#define I2C_FIRST_AND_LAST_FRAME 0x00000004U -#define I2C_LAST_FRAME 0x00000008U -#define I2C_NO_OPTION_FRAME 0xFFFF0000U - -#define I2C_DIRECTION_RECEIVE 0x00000000U -#define I2C_DIRECTION_TRANSMIT 0x00000001U - -#define I2C_ERROR_NONE 0x00000000U /*!< no error */ -#define I2C_ERROR_BERR 0x00000001U /*!< BERR error */ -#define I2C_ERROR_LOSTARB 0x00000002U /*!< LOSTARB error */ -#define I2C_ERROR_AERR 0x00000004U /*!< AERR error */ -#define I2C_ERROR_OUERR 0x00000008U /*!< OUERR error */ -#define I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ -#define I2C_ERROR_TIMEOUT 0x00000020U /*!< timeout Error */ - -#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< timeout 25 ms */ -#endif - -/* function declarations */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C POAP position */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master sends slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); -/* dual-address mode switch */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); - -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); -/* configure whether next DMA EOT is DMA last transfer or not */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* enable SAM_V interface */ -void i2c_sam_enable(uint32_t i2c_periph); -/* disable SAM_V interface */ -void i2c_sam_disable(uint32_t i2c_periph); -/* enable SAM_V interface timeout detect */ -void i2c_sam_timeout_enable(uint32_t i2c_periph); -/* disable SAM_V interface timeout detect */ -void i2c_sam_timeout_disable(uint32_t i2c_periph); - -/* check I2C flag is set or not */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); - -#endif /* GD32E10X_I2C_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_misc.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_misc.h deleted file mode 100644 index f3eb78b3110..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_misc.h +++ /dev/null @@ -1,94 +0,0 @@ -/*! - \file gd32e10x_misc.h - \brief definitions for the MISC - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_MISC_H -#define GD32E10X_MISC_H - -#include "gd32e10x.h" - -/* constants definitions */ -/* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ - -/* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) - -/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ - -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ - -#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT -#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP -#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND - -/* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ - -/* function declarations */ -/* set the priority group */ -void nvic_priority_group_set(uint32_t nvic_prigroup); - -/* enable NVIC request */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); -/* disable NVIC request */ -void nvic_irq_disable(uint8_t nvic_irq); - -/* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - -/* set the state of the low power mode */ -void system_lowpower_set(uint8_t lowpower_mode); -/* reset the state of the low power mode */ -void system_lowpower_reset(uint8_t lowpower_mode); - -/* set the systick clock source */ -void systick_clksource_set(uint32_t systick_clksource); - -#endif /* GD32E10X_MISC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_pmu.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_pmu.h deleted file mode 100644 index 9ea9ccfc0a9..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_pmu.h +++ /dev/null @@ -1,138 +0,0 @@ -/*! - \file gd32e10x_pmu.h - \brief definitions for the PMU - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_PMU_H -#define GD32E10X_PMU_H - -#include "gd32e10x.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ -#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ - -/* constants definitions */ -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - -/* PMU LDO output voltage select definitions */ -#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -#define PMU_LDOVS_NORMAL CTL_LDOVS(1) /*!< LDO output voltage select normal mode */ -#define PMU_LDOVS_LOW CTL_LDOVS(3) /*!< LDO output voltage select low mode */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* reset PMU registers */ -void pmu_deinit(void); - -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* select LDO output voltage */ -void pmu_ldo_output_select(uint32_t ldo_output); -/* disable PMU lvd */ -void pmu_lvd_disable(void); - -/* set PMU mode */ -/* PMU work at sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); - -/* wakeup pin related functions */ -/* enable PMU wakeup pin */ -void pmu_wakeup_pin_enable(void); -/* disable PMU wakeup pin */ -void pmu_wakeup_pin_disable(void); - -/* backup related functions */ -/* enable write access to the registers in backup domain */ -void pmu_backup_write_enable(void); -/* disable write access to the registers in backup domain */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* clear flag bit */ -void pmu_flag_clear(uint32_t flag_reset); -/* get flag state */ -FlagStatus pmu_flag_get(uint32_t flag); - -#endif /* GD32E10X_PMU_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_rcu.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_rcu.h deleted file mode 100644 index 492e20c0679..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_rcu.h +++ /dev/null @@ -1,818 +0,0 @@ -/*! - \file gd32e10x_rcu.h - \brief definitions for the RCU - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_RCU_H -#define GD32E10X_RCU_H - -#include "gd32e10x.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ -#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ -#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ -#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ -#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ -#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ -#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ -#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ - -/* bits definitions */ -/* RCU_CTL */ -#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ -#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ -#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ -#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ - -/* RCU_CFG0 */ -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ -#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ -#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ -#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ -#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ -#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ -#define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */ - -/* RCU_INT */ -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ -#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ -#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ -#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ -#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ -#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ -#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ -#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ -#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ -#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ -#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ -#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ -#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ -#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ -#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ -#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ -#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ -#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ -#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ -#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ -#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ -#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ -#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ -#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ -#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ -#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ -#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ -#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ -#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ -#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ -#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ -#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ -#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ -#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ -#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ -#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ -#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ - - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ -#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ -#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ -#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ -#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ -#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ -#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ -#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ -#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ -#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ -#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ -#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -/* RCU_AHBRST */ -#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ - -/* RCU_CFG1 */ -#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ -#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ -#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ -#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ -#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ -#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ -#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ -#define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ -#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ - -/* RCU_ADDCTL */ -#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ -#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ -#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ -#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ - -/* RCU_ADDINT */ -#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ -#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ -#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ - -/* RCU_ADDAPB1RST */ -#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ - -/* RCU_ADDAPB1EN */ -#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ - - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -/* peripherals enable */ -#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ -#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ -#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ -#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ - -/* peripherals reset */ -#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ -#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ -#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ -#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ -#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ - -/* clock control */ -#define CTL_REG_OFFSET 0x00U /*!< control register offset */ -#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ -#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ - -/* clock stabilization and stuck interrupt */ -#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ -#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ - -/* configuration register */ -#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ -#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ - -/* peripheral clock enable */ -typedef enum { - /* AHB peripherals */ - RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ - RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ - RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ - RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ - RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ - - /* APB1 peripherals */ - RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ - RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ - RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ - RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ - RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ - - RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ - RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ - - RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ - RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ - RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ - RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ - RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ - RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ - - RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ - RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ - RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ - RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ - RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ - RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ - RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ - - /* APB2 peripherals */ - RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ - RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ - RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ - RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ - RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ - RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ - RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ - RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ - - RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ - RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ - RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ - -} rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum { - /* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ -} rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum { - /* AHB peripherals */ - RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ - - /* APB1 peripherals */ - RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ - RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ - RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ - RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ - RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ - RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ - RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ - RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ - RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ - RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ - RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ - RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ - - RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ - RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ - RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ - RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ - RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ - RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< RTC clock reset */ - - /* APB2 peripherals */ - RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ - RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ - RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ - RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ - RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ - RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ - RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ - RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ - RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ - RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ - -} rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum { - /* clock stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ - RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ - RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ - RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ - /* reset source flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ -} rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum { - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ - RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ - RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ - RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ -} rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum { - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ - RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ - RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ -} rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum { - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ - RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ - RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ - RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ -} rcu_int_enum; - -/* oscillator types */ -typedef enum { - RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ - RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ - RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ - RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ - RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ -} rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum { - CK_SYS = 0, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ -} rcu_clock_freq_enum; - -/* RCU_CFG0 register bit define */ -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC prescaler select */ -#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ -#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ -#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ -#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ -#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ -#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ -#define RCU_CKADC_CKAHB_DIV3 ((uint32_t)0x00000008U) /*!< ADC prescaler select CK_AHB/3 */ -#define RCU_CKADC_CKAHB_DIV5 ((uint32_t)0x00000009U) /*!< ADC prescaler select CK_AHB/5 */ -#define RCU_CKADC_CKAHB_DIV7 ((uint32_t)0x0000000AU) /*!< ADC prescaler select CK_AHB/7 */ -#define RCU_CKADC_CKAHB_DIV9 ((uint32_t)0x0000000BU) /*!< ADC prescaler select CK_AHB/9 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ -#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< HXTAL or IRC48M selected as source clock of PLL */ - -/* PLL clock multiplication factor */ -#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ - -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ - -#define USBPSC_2 RCU_CFG0_USBFSPSC_2 - -/* USBD/USBFS prescaler select */ -#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ -#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ -#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ -#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ -#define RCU_CKUSB_CKPLL_DIV3 (USBPSC_2 |CFG0_USBPSC(0)) /*!< USBFS prescaler select CK_PLL/3.5 */ -#define RCU_CKUSB_CKPLL_DIV3_5 (USBPSC_2 |CFG0_USBPSC(1)) /*!< USBFS prescaler select CK_PLL/3 */ -#define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBFS prescaler select CK_PLL/4 */ - -/* CKOUT0 Clock source selection */ -#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ -#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ -#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ -#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ -#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ -#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ -#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ -#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ -#define RCU_CKOUT0SRC_IRC48M CFG0_CKOUT0SEL(12) /*!< IRC48M clock selected */ -#define RCU_CKOUT0SRC_IRC48M_DIV8 CFG0_CKOUT0SEL(13) /*!< IRC48M/8 clock selected */ - -/* LXTAL drive capability */ -#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) -#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ -#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ -#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ -#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ -#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - -/* PREDV0 division factor */ -#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ -#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ -#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ -#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ -#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ -#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ -#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ -#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ -#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ -#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ -#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ -#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ -#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ -#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ -#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ -#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - -/* PREDV1 division factor */ -#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ -#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ -#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ -#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ -#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ -#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ -#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ -#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ -#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ -#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ -#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ -#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ -#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ -#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ -#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ -#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - -/* PLL1 clock multiplication factor */ -#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ -#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ -#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ -#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ -#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ -#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ -#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ -#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ -#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ - -/* PLL2 clock multiplication factor */ -#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ -#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ -#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ -#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ -#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ -#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ -#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ -#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ -#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ - -/* PREDV0 input clock source selection */ -#define RCU_PREDV0SRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PREDV0 input source clock */ -#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ - -/* I2S1 clock source selection */ -#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ -#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ - -/* I2S2 clock source selection */ -#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ -#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ - -/* PLL input clock source selection */ -#define RCU_PLLPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLL source clock */ -#define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ - -/* deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(3) /*!< core voltage is 1.2V in deep-sleep mode */ - -/* 48MHz clock selection */ -#define RCU_CK48MSRC_CKPLL ((uint32_t)0x00000000U) /*!< use CK_PLL clock */ -#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< select IRC48M clock */ - -/* function declarations */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP domain */ -void rcu_bkp_reset_enable(void); -/* disable the BKP domain reset */ -void rcu_bkp_reset_disable(void); - -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the CK_OUT0 clock source and divider */ -void rcu_ckout0_config(uint32_t ckout0_src); -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); -/* configure the PLL clock source preselection */ -void rcu_pllpresel_config(uint32_t pll_presel); -/* configure the PREDV0 division factor and clock source */ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); -/* configure the PREDV1 division factor */ -void rcu_predv1_config(uint32_t predv1_div); -/* configure the PLL1 clock */ -void rcu_pll1_config(uint32_t pll_mul); -/* configure the PLL2 clock */ -void rcu_pll2_config(uint32_t pll_mul); - -/* configure the ADC division factor */ -void rcu_adc_clock_config(uint32_t adc_psc); -/* configure the USBFS prescaler factor */ -void rcu_usb_clock_config(uint32_t usb_psc); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -/* configure the I2S1 clock source selection */ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source); -/* configure the I2S2 clock source selection */ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source); -/* configure the CK48M clock selection */ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); - - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -/* configure the LXTAL drive capability */ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); -/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); - -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32E10X_RCU_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_rtc.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_rtc.h deleted file mode 100644 index 5b29b24ec35..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_rtc.h +++ /dev/null @@ -1,151 +0,0 @@ -/*! - \file gd32e10x_rtc.h - \brief definitions for the RTC - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_RTC_H -#define GD32E10X_RTC_H - -#include "gd32e10x.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ -#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ -#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ -#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ -#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ -#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ -#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ -#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ -#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ -#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ - -/* bits definitions */ -/* RTC_INTEN */ -#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ -#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ -#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ - -/* RTC_CTL */ -#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ -#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ -#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ -#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ -#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ -#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ - -/* RTC_PSCH */ -#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ - -/* RTC_PSCL */ -#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ - -/* RTC_DIVH */ -#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ - -/* RTC_DIVL */ -#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ - -/* RTC_CNTH */ -#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ - -/* RTC_CNTL */ -#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ - -/* RTC_ALRMH */ -#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ - -/* RTC_ALRML */ -#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ - -/* constants definitions */ -/* RTC interrupt enable or disable definitions */ -#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ -#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ -#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ - -/* RTC interrupt flag definitions */ -#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ - -/* RTC flag definitions */ -#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ -#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ -#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ - -/* function declarations */ -/* initialization functions */ -/* enter RTC configuration mode */ -void rtc_configuration_mode_enter(void); -/* exit RTC configuration mode */ -void rtc_configuration_mode_exit(void); -/* set RTC counter value */ -void rtc_counter_set(uint32_t cnt); -/* set RTC prescaler value */ -void rtc_prescaler_set(uint32_t psc); - -/* operation functions */ -/* wait RTC last write operation finished flag set */ -void rtc_lwoff_wait(void); -/* wait RTC registers synchronized flag set */ -void rtc_register_sync_wait(void); -/* set RTC alarm value */ -void rtc_alarm_config(uint32_t alarm); -/* get RTC counter value */ -uint32_t rtc_counter_get(void); -/* get RTC divider value */ -uint32_t rtc_divider_get(void); - -/* flag & interrupt functions */ -/* get RTC flag status */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear RTC flag status */ -void rtc_flag_clear(uint32_t flag); -/* get RTC interrupt flag status */ -FlagStatus rtc_interrupt_flag_get(uint32_t flag); -/* clear RTC interrupt flag status */ -void rtc_interrupt_flag_clear(uint32_t flag); -/* enable RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disable RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); - -#endif /* GD32E10X_RTC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_spi.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_spi.h deleted file mode 100644 index edbe9db9b12..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_spi.h +++ /dev/null @@ -1,366 +0,0 @@ -/*! - \file gd32e10x_spi.h - \brief definitions for the SPI - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_SPI_H -#define GD32E10X_SPI_H - -#include "gd32e10x.h" - -/* SPIx(x=0,1,2) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE -#define SPI2 (SPI_BASE + 0x00000400U) - -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register(only SPI1) */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ -#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ -#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error bit */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2SPSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* SPI_QCTL(only for SPI1) */ -#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ -#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ -#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ - -/* constants definitions */ -/* SPI and I2S parameter struct definitions */ -typedef struct { - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transtype */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI NSS control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescale factor */ -} spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI frame size */ -#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ -#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock phase and polarity */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescale factor */ -#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ - -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ -#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ - -/* SPI/I2S flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ - -/* function declarations */ -/* SPI/I2S deinitialization and initialization functions */ -/* reset SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct *spi_struct); -/* initialize SPI parameter */ -#ifdef GD_MBED_USED -void spi_para_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); -#else -void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); -#endif -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -/* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); -/* configure I2S prescaler */ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); - -/* NSS functions */ -/* enable SPI NSS output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI NSS output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI NSS pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI NSS pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma); - -/* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); - -/* SPI CRC functions */ -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); - -/* SPI TI mode functions */ -/* enable SPI TI mode */ -void spi_ti_mode_enable(uint32_t spi_periph); -/* disable SPI TI mode */ -void spi_ti_mode_disable(uint32_t spi_periph); - -/* SPI NSS pulse mode functions */ -/* enable SPI NSS pulse mode */ -void spi_nssp_mode_enable(uint32_t spi_periph); -/* disable SPI NSS pulse mode */ -void spi_nssp_mode_disable(uint32_t spi_periph); - -/* quad wire SPI functions */ -/* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); -/* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); -/* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); -/* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); - -/* flag and interrupt functions */ -/* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); -/* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S interrupt status */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -#endif /* GD32E10X_SPI_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_timer.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_timer.h deleted file mode 100644 index 2385b59661f..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_timer.h +++ /dev/null @@ -1,743 +0,0 @@ -/*! - \file gd32e10x_timer.h - \brief definitions for the TIMER - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_TIMER_H -#define GD32E10X_TIMER_H - -#include "gd32e10x.h" - -/* TIMERx(x=0..13) definitions */ -#define TIMER0 (TIMER_BASE + 0x00012C00U) -#define TIMER1 (TIMER_BASE + 0x00000000U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#define TIMER3 (TIMER_BASE + 0x00000800U) -#define TIMER4 (TIMER_BASE + 0x00000C00U) -#define TIMER5 (TIMER_BASE + 0x00001000U) -#define TIMER6 (TIMER_BASE + 0x00001400U) -#define TIMER7 (TIMER_BASE + 0x00013400U) -#define TIMER8 (TIMER_BASE + 0x00014C00U) -#define TIMER9 (TIMER_BASE + 0x00015000U) -#define TIMER10 (TIMER_BASE + 0x00015400U) -#define TIMER11 (TIMER_BASE + 0x00001800U) -#define TIMER12 (TIMER_BASE + 0x00001C00U) -#define TIMER13 (TIMER_BASE + 0x00002000U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ -#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* TIMER_CFG */ -#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ -#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ - -/* constants definitions */ -/* TIMER init parameter struct definitions */ -typedef struct { - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint32_t period; /*!< period value */ - uint16_t clockdivision; /*!< clock division value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -} timer_parameter_struct; - -/* break parameter struct definitions */ -typedef struct { - uint16_t runoffstate; /*!< run mode off-state */ - uint16_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ -} timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct { - uint16_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -} timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct { - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -} timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ -#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ -#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ -#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ -#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ -#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ -#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ -#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ -#define TIMER_INT_FLAG_BRK TIMER_INT_BRK - -/* TIMER flag */ -#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ -#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ -#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel control update flag */ -#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ -#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ -#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ - -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ - - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel n(n=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ - -/* channel enable state */ -#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ - -/* channel complementary output enable state */ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode */ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge(only for TIMER1~TIMER8) */ - -/* TIMER input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel n is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel n is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel n is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ - -/* TIMERx(x=0..4,7..13) write CHxVAL register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ - -/* TIMERx(x=0,7) output value selection */ -#define TIMER_OUTSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< output value selection enable */ -#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ - -/* function declarations */ -/* TIMER timebase */ -/* deinit a timer */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER init parameter struct */ -void timer_struct_para_init(timer_parameter_struct *initpara); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara); -/* enable a timer */ -void timer_enable(uint32_t timer_periph); -/* disable a timer */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); - -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph, uint16_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint32_t update); - -/* TIMER DMA and event */ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* TIMER channel complementary protection */ -/* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct *breakpara); -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* enable or disable TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* enable or disable channel capture/compare control shadow register */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); - -/* TIMER channel output */ -/* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara); -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* initialize TIMER channel input parameter struct */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara); -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); - -/* TIMER master and slave mode */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); - -/* TIMER configure */ -/* configure TIMER write CHxVAL register selection */ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); -/* configure TIMER output value selection */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); - -/* TIMER interrupt and flag */ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flag */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flag */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -#endif /* GD32E10X_TIMER_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_usart.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_usart.h deleted file mode 100644 index 084c0048909..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_usart.h +++ /dev/null @@ -1,470 +0,0 @@ -/*! - \file gd32e10x_usart.h - \brief definitions for the USART - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_USART_H -#define GD32E10X_USART_H - -#include "gd32e10x.h" - -/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ -#define USART1 USART_BASE /*!< USART1 base address */ -#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ -#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ -#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ -#define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */ - -/* registers definitions */ -#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ -#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ -#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ -#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ -#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ -#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ -#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ -#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ -#define USART_CHC(usartx) REG32((usartx) + 0xC0U) /*!< USART coherence control register */ - -/* bits definitions */ -/* USARTx_STAT0 */ -#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT0_TC BIT(6) /*!< transmission complete */ -#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ - -/* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ - -/* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* USARTx_CTL3 */ -#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ -#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ -#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ -#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ -#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ -#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ -#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ - -/* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ - -/* USARTx_STAT1 */ -#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT1_BSY BIT(16) /*!< busy flag */ - -/* USARTx_CHC */ -#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ -#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ - -/* constants definitions */ -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ -#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ - -/* USART flags */ -typedef enum { - /* flags in STAT0 register */ - USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ - /* flags in STAT1 register */ - USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ - /* flags in CHC register */ - USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ -} usart_flag_enum; - -/* USART interrupt flags */ -typedef enum { - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ - /* interrupt flags in CTL3 register */ - USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ - USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ -} usart_interrupt_flag_enum; - -/* USART interrupt enable or disable */ -typedef enum { - /* interrupt in CTL0 register */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ - /* interrupt in CTL3 register */ - USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */ - USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */ -} usart_interrupt_enum; - -/* USART invert configure */ -typedef enum { - /* data bit level inversion */ - USART_DINV_ENABLE, /*!< data bit level inversion */ - USART_DINV_DISABLE, /*!< data bit level not inversion */ - /* TX pin level inversion */ - USART_TXPIN_ENABLE, /*!< TX pin level inversion */ - USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ - /* RX pin level inversion */ - USART_RXPIN_ENABLE, /*!< RX pin level inversion */ - USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ -} usart_invert_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ - -/* USART CK length */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART DMA request for receive configure */ -#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ - -/* USART DMA request for transmission configure */ -#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ - -/* USART RTS configure */ -#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ - -/* USART CTS configure */ -#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* USART data is transmitted/received with the LSB/MSB first */ -#define USART_MSBF_LSB ((uint32_t)0x00000000U) /*!< LSB first */ -#define USART_MSBF_MSB USART_CTL3_MSBF /*!< MSB first */ - -/* USART hardware flow control coherence mode */ -#define USART_RTS_NONE_COHERENCE ((uint32_t)0x00000000U) /*!< nRTS signal equals to the RBNE bit in USART_STAT0 */ -#define USART_RTS_COHERENCE USART_CHC_HCM /*!< nRTS signal is set when the last data bit has been sampled */ - -#ifdef GD_MBED_USED -/* USART error code */ -#define USART_ERROR_CODE_NONE 0U /*!< no error */ -#define USART_ERROR_CODE_PERR BIT(0) /*!< parity error */ -#define USART_ERROR_CODE_NERR BIT(1) /*!< noise error */ -#define USART_ERROR_CODE_FERR BIT(2) /*!< frame error */ -#define USART_ERROR_CODE_ORERR BIT(3) /*!< overrun error */ - -/* USART hardware control configuration */ -#define USART_HWCONTROL_NONE 0U -#define USART_HWCONTROL_RTS USART_RTS_ENABLE -#define USART_HWCONTROL_CTS USART_CTS_ENABLE -#define USART_HWCONTROL_RTS_CTS (USART_RTS_ENABLE | USART_CTS_ENABLE) -#endif - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure USART baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure USART word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure USART stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); -/* enable USART */ -void usart_enable(uint32_t usart_periph); -/* disable USART */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); - -/* USART normal mode communication */ -/* data is transmitted/received with the LSB/MSB first */ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); -/* configure USART inverted */ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); -/* enable receiver timeout */ -void usart_receiver_timeout_enable(uint32_t usart_periph); -/* disable receiver timeout */ -void usart_receiver_timeout_disable(uint32_t usart_periph); -/* configure receiver timeout threshold */ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* multi-processor communication */ -/* configure address of the USART */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); - -/* LIN mode communication */ -/* enable LIN mode */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* disable LIN mode */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); -/* send break frame */ -void usart_send_break(uint32_t usart_periph); - -/* half-duplex communication */ -/* enable half-duplex mode */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* disable half-duplex mode */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* enable CK pin in synchronous mode */ -void usart_synchronous_clock_enable(uint32_t usart_periph); -/* disable CK pin in synchronous mode */ -void usart_synchronous_clock_disable(uint32_t usart_periph); -/* configure usart synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* configure guard time value in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); -/* enable smartcard mode */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* disable smartcard mode */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* enable NACK in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* disable NACK in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* configure smartcard auto-retry number */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* configure block length */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* DMA communication */ -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); - -/* coherence control */ -/* configure hardware flow control coherence mode */ -void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); - -/* flag & interrupt functions */ -/* get flag in STAT0/STAT1 register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT0/STAT1 register */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -/* clear interrupt flag in STAT0/STAT1 register */ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); - -#endif /* GD32E10X_USART_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_wwdgt.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_wwdgt.h deleted file mode 100644 index 9dd8340f323..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Include/gd32e10x_wwdgt.h +++ /dev/null @@ -1,89 +0,0 @@ -/*! - \file gd32e10x_wwdgt.h - \brief definitions for the WWDGT - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_WWDGT_H -#define GD32E10X_WWDGT_H - -#include "gd32e10x.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE - -/* registers definitions */ -#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - -/* constants definitions */ -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); - -#endif /* GD32E10X_WWDGT_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_adc.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_adc.c deleted file mode 100644 index 7dce2fcd296..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_adc.c +++ /dev/null @@ -1,994 +0,0 @@ -/*! - \file gd32e10x_adc.c - \brief ADC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_adc.h" - -/* discontinuous mode macro*/ -#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) - -/* ADC regular channel macro */ -#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) -#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) -#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) -#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) - -/* ADC sampling time macro */ -#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) -#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) -#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) - -/* ADC inserted channel macro */ -#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) -#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) - -/* ADC inserted channel offset macro */ -#define ADC_OFFSET_LENGTH ((uint8_t)3U) -#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) - -/*! - \brief reset ADC - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_deinit(uint32_t adc_periph) -{ - switch (adc_periph) { - case ADC0: - /* reset ADC0 */ - rcu_periph_reset_enable(RCU_ADC0RST); - rcu_periph_reset_disable(RCU_ADC0RST); - break; - case ADC1: - /* reset ADC1 */ - rcu_periph_reset_enable(RCU_ADC1RST); - rcu_periph_reset_disable(RCU_ADC1RST); - break; - default: - break; - } -} - -/*! - \brief configure the ADC sync mode - \param[in] mode: ADC mode - only one parameter can be selected which is shown as below: - \arg ADC_MODE_FREE: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode - \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only - \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only - \param[out] none - \retval none -*/ -void adc_mode_config(uint32_t mode) -{ - ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); - ADC_CTL0(ADC0) |= mode; -} - -/*! - \brief enable or disable ADC special function - \param[in] adc_periph: ADCx,x=0,1 - \param[in] function: the function to config - only one parameter can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) -{ - if (newvalue) { - if (0U != (function & ADC_SCAN_MODE)) { - /* enable scan mode */ - ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; - } - if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { - /* enable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; - } - if (0U != (function & ADC_CONTINUOUS_MODE)) { - /* enable continuous mode */ - ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; - } - } else { - if (0U != (function & ADC_SCAN_MODE)) { - /* disable scan mode */ - ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; - } - if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { - /* disable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; - } - if (0U != (function & ADC_CONTINUOUS_MODE)) { - /* disable continuous mode */ - ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] adc_periph: ADCx,x=0,1 - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) -{ - if (ADC_DATAALIGN_RIGHT != data_alignment) { - /* MSB alignment */ - ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - } else { - /* LSB alignment */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief enable ADC interface - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_enable(uint32_t adc_periph) -{ - if (RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { - /* enable ADC */ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_disable(uint32_t adc_periph) -{ - /* disable ADC */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_calibration_enable(uint32_t adc_periph) -{ - /* reset the selected ADC1 calibration registers */ - ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while (RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { - } - /* enable ADC calibration process */ - ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while (RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { - } -} - -/*! - \brief enable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_enable(void) -{ - /* enable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; -} - -/*! - \brief disable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_disable(void) -{ - /* disable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; -} - -/*! - \brief configure ADC resolution - \param[in] adc_periph: ADCx,x=0,1 - \param[in] resolution: ADC resolution - only one parameter can be selected which is shown as below: - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) -{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES); - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution; -} - -/*! - \brief configure ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1 - \param[in] mode: ADC oversampling mode - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none -*/ -void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio) -{ - if (ADC_OVERSAMPLING_ONE_CONVERT == mode) { - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; - } else { - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); - } - /* config the shift and ratio */ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief enable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; -} - -/*! - \brief disable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_oversample_mode_disable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); -} - -/*! - \brief enable DMA request - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(uint32_t adc_periph) -{ - /* enable DMA request */ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(uint32_t adc_periph) -{ - /* disable DMA request */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief configure ADC discontinuous mode - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) -{ - /* disable discontinuous mode of regular & inserted channel */ - ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - switch (adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* config the number of conversions in discontinuous mode */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - /* enable regular channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - /* enable inserted channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ - default: - break; - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) -{ - switch (adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* configure the length of regular channel group */ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - break; - case ADC_INSERTED_CHANNEL: - /* configure the length of inserted channel group */ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] adc_periph: ADCx,x=0,1 - \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) -{ - uint32_t rsq, sampt; - - /* ADC regular sequence config */ - if (rank < ADC_REGULAR_CHANNEL_RANK_SIX) { - /* the regular group sequence rank is smaller than six */ - rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank)); - ADC_RSQ2(adc_periph) = rsq; - } else if (rank < ADC_REGULAR_CHANNEL_RANK_TWELVE) { - /* the regular group sequence rank is smaller than twelve */ - rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX))); - ADC_RSQ1(adc_periph) = rsq; - } else if (rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN) { - /* the regular group sequence rank is smaller than sixteen */ - rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE))); - ADC_RSQ0(adc_periph) = rsq; - } else { - } - - /* ADC sampling time config */ - if (adc_channel < ADC_CHANNEL_SAMPLE_TEN) { - /* the regular group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)); - ADC_SAMPT1(adc_periph) = sampt; - } else if (adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN) { - /* the regular group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - } else { - } -} - -/*! - \brief configure ADC inserted channel - \param[in] adc_periph: ADCx,x=0,1 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq, sampt; - /* get inserted channel group length */ - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); - /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ - isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH))); - isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)); - ADC_ISQ(adc_periph) = isq; - - /* ADC sampling time config */ - if (adc_channel < ADC_CHANNEL_SAMPLE_TEN) { - /* the inserted group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel); - ADC_SAMPT1(adc_periph) = sampt; - } else if (adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN) { - /* the inserted group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - } else { - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] adc_periph: ADCx,x=0,1 - \param[in] inserted_channel : insert channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 - \param[in] offset : the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); - num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); - - if (num <= ADC_OFFSET_LENGTH) { - /* calculate the offset of the register */ - num = num * ADC_OFFSET_SHIFT_LENGTH; - /* config the offset of the selected channels */ - REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief configure ADC external trigger source - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - only one parameter can be selected which is shown as below: - for regular channel: - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select - \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select - \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11 - \arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: - \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: timer 1 CC0 event select - \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: timer 2 CC3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: timer 3 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select - \arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) -{ - switch (adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* configure ADC regular group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - /* configure ADC inserted group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief enable ADC external trigger - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected which are shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) -{ - if (newvalue) { - if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { - /* enable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; - } - if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { - /* enable ADC inserted channel group external trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; - } - } else { - if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { - /* disable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; - } - if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { - /* disable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; - } - } -} - -/*! - \brief enable ADC software trigger - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected which are shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { - /* enable ADC regular channel group software trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; - } - if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { - /* enable ADC inserted channel group software trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; - } -} - -/*! - \brief read ADC regular group data register - \param[in] adc_periph: ADCx,x=0,1 - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(uint32_t adc_periph) -{ - return (uint16_t)(ADC_RDATA(adc_periph)); -} - -/*! - \brief read ADC inserted group data register - \param[in] adc_periph: ADCx,x=0,1 - \param[in] inserted_channel : insert channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch (inserted_channel) { - case ADC_INSERTED_CHANNEL_0: - /* read the data of channel 0 */ - idata = ADC_IDATA0(adc_periph); - break; - case ADC_INSERTED_CHANNEL_1: - /* read the data of channel 1 */ - idata = ADC_IDATA1(adc_periph); - break; - case ADC_INSERTED_CHANNEL_2: - /* read the data of channel 2 */ - idata = ADC_IDATA2(adc_periph); - break; - case ADC_INSERTED_CHANNEL_3: - /* read the data of channel 3 */ - idata = ADC_IDATA3(adc_periph); - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief read the last ADC0 and ADC1 conversion result data in sync mode - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint32_t adc_sync_mode_convert_value_read(void) -{ - /* return conversion value */ - return ADC_RDATA(ADC0); -} - -/*! - \brief configure ADC analog watchdog single channel - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); - /* analog watchdog channel select */ - ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - /* select the group */ - switch (adc_channel_group) { - case ADC_REGULAR_CHANNEL: - /* regular channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - /* inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* regular and inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] adc_periph: ADCx,x=0,1 - \param[out] none - \retval none -*/ -void adc_watchdog_disable(uint32_t adc_periph) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] adc_periph: ADCx,x=0,1 - \param[in] low_threshold: analog watchdog low threshold,0..4095 - \param[in] high_threshold: analog watchdog high threshold,0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) -{ - ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); - ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); -} - -/*! - \brief get the ADC flag bits - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) -{ - FlagStatus reval = RESET; - if (ADC_STAT(adc_periph) & adc_flag) { - reval = SET; - } - return reval; -} - -/*! - \brief clear the ADC flag bits - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_flag: the adc flag bits - one or more parameters can be selected which are shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); -} - -/*! - \brief get the bit state of ADCx software start conversion - \param[in] adc_periph: ADCx, x=0,1, only one among these parameters can be selected - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if ((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)) { - reval = SET; - } - return reval; -} - -/*! - \brief get the bit state of ADCx software inserted channel start conversion - \param[in] adc_periph: ADCx, x=0,1 only one among these parameters can be selected - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if ((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)) { - reval = SET; - } - return reval; -} - -/*! - \brief get the ADC interrupt bits - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_interrupt: the adc interrupt bits - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - /* check the interrupt bits */ - switch (adc_interrupt) { - case ADC_INT_FLAG_WDE: - /* get the ADC analog watchdog interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if ((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) { - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear the ADC flag - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_interrupt: the adc status flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); -} - -/*! - \brief enable ADC interrupt - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_interrupt: the adc interrupt - one or more parameters can be selected which are shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - /* enable ADC analog watchdog interrupt */ - if (0U != (adc_interrupt & ADC_INT_WDE)) { - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; - } - /* enable ADC end of group conversion interrupt */ - if (0U != (adc_interrupt & ADC_INT_EOC)) { - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; - } - /* enable ADC end of inserted group conversion interrupt */ - if (0U != (adc_interrupt & ADC_INT_EOIC)) { - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; - } -} - -/*! - \brief disable ADC interrupt - \param[in] adc_periph: ADCx,x=0,1 - \param[in] adc_interrupt: the adc interrupt flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - /* disable ADC analog watchdog interrupt */ - if (0U != (adc_interrupt & ADC_INT_WDE)) { - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; - } - /* disable ADC end of group conversion interrupt */ - if (0U != (adc_interrupt & ADC_INT_EOC)) { - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; - } - /* disable ADC end of inserted group conversion interrupt */ - if (0U != (adc_interrupt & ADC_INT_EOIC)) { - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_bkp.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_bkp.c deleted file mode 100644 index e35b2e75eb4..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_bkp.c +++ /dev/null @@ -1,335 +0,0 @@ -/*! - \file gd32e10x_bkp.c - \brief BKP driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_bkp.h" - -/* BKP register bits offset */ -#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U) - -/*! - \brief reset BKP registers - \param[in] none - \param[out] none - \retval none -*/ -void bkp_deinit(void) -{ - /* reset BKP domain register*/ - rcu_bkp_reset_enable(); - rcu_bkp_reset_disable(); -} - -/*! - \brief write BKP data register - \param[in] register_number: refer to bkp_data_register_enum - only one parameter can be selected which is shown as below: - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[in] data: the data to be write in BKP data register - \param[out] none - \retval none -*/ -void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) -{ - if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) { - BKP_DATA10_41(register_number - 1U) = data; - } else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) { - BKP_DATA0_9(register_number - 1U) = data; - } else { - /* illegal parameters */ - } -} - -/*! - \brief read BKP data register - \param[in] register_number: refer to bkp_data_register_enum - only one parameter can be selected which is shown as below: - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[out] none - \retval data of BKP data register -*/ -uint16_t bkp_data_read(bkp_data_register_enum register_number) -{ - uint16_t data = 0U; - - /* get the data from the BKP data register */ - if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) { - data = BKP_DATA10_41(register_number - 1U); - } else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) { - data = BKP_DATA0_9(register_number - 1U); - } else { - /* illegal parameters */ - } - return data; -} - -/*! - \brief enable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; -} - -/*! - \brief disable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; -} - -/*! - \brief enable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; -} - -/*! - \brief disable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; -} - -/*! - \brief select RTC output - \param[in] outputsel: RTC output selection - only one parameter can be selected which is shown as below: - \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output - \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output - \param[out] none - \retval none -*/ -void bkp_rtc_output_select(uint16_t outputsel) -{ - uint16_t ctl = 0U; - - /* configure BKP_OCTL_ROSEL with outputsel */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_ROSEL; - ctl |= outputsel; - BKP_OCTL = ctl; -} - -/*! - \brief select RTC clock output - \param[in] clocksel: RTC clock output selection - only one parameter can be selected which is shown as below: - \arg RTC_CLOCK_DIV_64: RTC clock div 64 - \arg RTC_CLOCK_DIV_1: RTC clock - \param[out] none - \retval none -*/ -void bkp_rtc_clock_output_select(uint16_t clocksel) -{ - uint16_t ctl = 0U; - - /* configure BKP_OCTL_CCOSEL with clocksel */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_CCOSEL; - ctl |= clocksel; - BKP_OCTL = ctl; -} - -/*! - \brief select RTC clock calibration direction - \param[in] direction: RTC clock calibration direction - only one parameter can be selected which is shown as below: - \arg RTC_CLOCK_SLOWED_DOWN: RTC clock slow down - \arg RTC_CLOCK_SPEED_UP: RTC clock speed up - \param[out] none - \retval none -*/ -void bkp_rtc_clock_calibration_direction_select(uint16_t direction) -{ - uint16_t ctl = 0U; - - /* configure BKP_OCTL_CALDIR with direction */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_CALDIR; - ctl |= direction; - BKP_OCTL = ctl; -} - -/*! - \brief set RTC clock calibration value - \param[in] value: RTC clock calibration value - \arg 0x00 - 0x7F - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_value_set(uint8_t value) -{ - uint16_t ctl; - - /* configure BKP_OCTL_RCCV with value */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_RCCV; - ctl |= (uint16_t)OCTL_RCCV(value); - BKP_OCTL = ctl; -} - -/*! - \brief enable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_enable(void) -{ - BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; -} - -/*! - \brief disable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_disable(void) -{ - BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; -} - -/*! - \brief set tamper pin active level - \param[in] level: tamper active level - only one parameter can be selected which is shown as below: - \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high - \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low - \param[out] none - \retval none -*/ -void bkp_tamper_active_level_set(uint16_t level) -{ - uint16_t ctl = 0U; - - /* configure BKP_TPCTL_TPAL with level */ - ctl = BKP_TPCTL; - ctl &= (uint16_t)~BKP_TPCTL_TPAL; - ctl |= level; - BKP_TPCTL = ctl; -} - -/*! - \brief enable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_enable(void) -{ - BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; -} - -/*! - \brief disable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_disable(void) -{ - BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; -} - -/*! - \brief get tamper flag state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_flag_get(void) -{ - if (RESET != (BKP_TPCS & BKP_FLAG_TAMPER)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear tamper flag state - \param[in] none - \param[out] none - \retval none -*/ -void bkp_flag_clear(void) -{ - BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); -} - -/*! - \brief get tamper interrupt flag state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_interrupt_flag_get(void) -{ - if (RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear tamper interrupt flag state - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_flag_clear(void) -{ - BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_can.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_can.c deleted file mode 100644 index 6af479a9b88..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_can.c +++ /dev/null @@ -1,1502 +0,0 @@ -/*! - \file gd32e10x_can.c - \brief CAN driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_can.h" - -#define CAN_ERROR_HANDLE(s) do{}while(1) - -/* BS1[3:0] + 1 + BS2[2:0] + 1 */ -#define DEV_CAN_BT_SEG_MAX 24u -#define DEV_CAN_BT_SEG_MIN 4u - -/* CAN related register mask */ -#define DEV_CAN_BS1_MASK 0x000F0000U -#define DEV_CAN_BS2_MASK 0x00700000U -#define DEV_CAN_BAUDPSC_MASK 0x000003FFU -#define DEV_CAN_SJW_MASK 0x03000000U -/* This table can be used to calculate data length in FD mode */ -const uint8_t g_can_fdlength_table[] = {12, 16, 20, 24, 32, 48, 64}; -/* This table can be used to calculate bit time: timing_pts{BS1[3:0], BS2[2:0]} */ -static const uint32_t timing_pts[23][2] = { - {0x0, 0x0}, /* 2, 50% */ - {0x1, 0x0}, /* 3, 67% */ - {0x2, 0x0}, /* 4, 75% */ - {0x3, 0x0}, /* 5, 80% */ - {0x3, 0x1}, /* 6, 67% */ - {0x4, 0x1}, /* 7, 71% */ - {0x5, 0x1}, /* 8, 75% */ - {0x6, 0x1}, /* 9, 78% */ - {0x6, 0x2}, /* 10, 70% */ - {0x7, 0x2}, /* 11, 73% */ - {0x8, 0x2}, /* 12, 75% */ - {0x9, 0x2}, /* 13, 77% */ - {0x9, 0x3}, /* 14, 71% */ - {0xA, 0x3}, /* 15, 73% */ - {0xB, 0x3}, /* 16, 75% */ - {0xC, 0x3}, /* 17, 76% */ - {0xD, 0x3}, /* 18, 78% */ - {0xD, 0x4}, /* 19, 74% */ - {0xE, 0x4}, /* 20, 75% */ - {0xF, 0x4}, /* 21, 76% */ - {0xF, 0x5}, /* 22, 73% */ - {0xF, 0x6}, /* 23, 70% */ - {0xF, 0x7}, /* 24, 67% */ -}; - -static unsigned int dev_can_baudrate_set(uint32_t freq); - -/*! - \brief deinitialize CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_deinit(uint32_t can_periph) -{ - if (CAN0 == can_periph) { - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - } else { - rcu_periph_reset_enable(RCU_CAN1RST); - rcu_periph_reset_disable(RCU_CAN1RST); - } -} - -/*! - \brief initialize CAN parameter struct with a default value - \param[in] type: the type of CAN parameter struct - only one parameter can be selected which is shown as below: - \arg CAN_INIT_STRUCT: the CAN initial struct - \arg CAN_FILTER_STRUCT: the CAN filter struct - \arg CAN_FD_FRAME_STRUCT: the CAN FD initial struct - \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct - \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct - \param[in] p_struct: the pointer of the specific struct - \param[out] none - \retval none -*/ -void can_struct_para_init(can_struct_type_enum type, void *p_struct) -{ - uint8_t i; - - /* get type of the struct */ - switch (type) { - /* used for can_init() */ - case CAN_INIT_STRUCT: - ((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct *)p_struct)->auto_retrans = DISABLE; - ((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE; - ((can_parameter_struct *)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = DISABLE; - ((can_parameter_struct *)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; - ((can_parameter_struct *)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; - ((can_parameter_struct *)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; - ((can_parameter_struct *)p_struct)->time_triggered = DISABLE; - ((can_parameter_struct *)p_struct)->trans_fifo_order = DISABLE; - ((can_parameter_struct *)p_struct)->working_mode = CAN_NORMAL_MODE; - - break; - /* used for can_filter_init() */ - case CAN_FILTER_STRUCT: - ((can_filter_parameter_struct *)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; - ((can_filter_parameter_struct *)p_struct)->filter_enable = DISABLE; - ((can_filter_parameter_struct *)p_struct)->filter_fifo_number = CAN_FIFO0; - ((can_filter_parameter_struct *)p_struct)->filter_list_high = 0x0000U; - ((can_filter_parameter_struct *)p_struct)->filter_list_low = 0x0000U; - ((can_filter_parameter_struct *)p_struct)->filter_mask_high = 0x0000U; - ((can_filter_parameter_struct *)p_struct)->filter_mask_low = 0x0000U; - ((can_filter_parameter_struct *)p_struct)->filter_mode = CAN_FILTERMODE_MASK; - ((can_filter_parameter_struct *)p_struct)->filter_number = 0U; - - break; - /* used for can_fd_init() */ - case CAN_FD_FRAME_STRUCT: - ((can_fdframe_struct *)p_struct)->data_prescaler = 0x03FFU; - ((can_fdframe_struct *)p_struct)->data_resync_jump_width = 1U - 1U; - ((can_fdframe_struct *)p_struct)->data_time_segment_1 = 3U - 1U; - ((can_fdframe_struct *)p_struct)->data_time_segment_2 = 2U - 1U; - ((can_fdframe_struct *)p_struct)->delay_compensation = DISABLE; - ((can_fdframe_struct *)p_struct)->esi_mode = CAN_ESIMOD_HARDWARE; - ((can_fdframe_struct *)p_struct)->excp_event_detect = ENABLE; - ((can_fdframe_struct *)p_struct)->fd_frame = DISABLE; - ((can_fdframe_struct *)p_struct)->iso_bosch = CAN_FDMOD_ISO; - ((can_fdframe_struct *)p_struct)->p_delay_compensation = 0U; - - break; - /* used for can_message_transmit() */ - case CAN_TX_MESSAGE_STRUCT: - ((can_trasnmit_message_struct *)p_struct)->fd_brs = CAN_BRS_DISABLE; - ((can_trasnmit_message_struct *)p_struct)->fd_esi = CAN_ESI_DOMINANT; - ((can_trasnmit_message_struct *)p_struct)->fd_flag = CAN_FDF_CLASSIC; - - for (i = 0U; i < 64U; i++) { - ((can_trasnmit_message_struct *)p_struct)->tx_data[i] = 0U; - } - - ((can_trasnmit_message_struct *)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct *)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct *)p_struct)->tx_sfid = 0U; - - break; - /* used for can_message_receive() */ - case CAN_RX_MESSAGE_STRUCT: - ((can_receive_message_struct *)p_struct)->fd_brs = CAN_BRS_DISABLE; - ((can_receive_message_struct *)p_struct)->fd_esi = CAN_ESI_DOMINANT; - ((can_receive_message_struct *)p_struct)->fd_flag = CAN_FDF_CLASSIC; - - for (i = 0U; i < 64U; i++) { - ((can_receive_message_struct *)p_struct)->rx_data[i] = 0U; - } - - ((can_receive_message_struct *)p_struct)->rx_dlen = 0U; - ((can_receive_message_struct *)p_struct)->rx_efid = 0U; - ((can_receive_message_struct *)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_receive_message_struct *)p_struct)->rx_fi = 0U; - ((can_receive_message_struct *)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; - ((can_receive_message_struct *)p_struct)->rx_sfid = 0U; - - break; - - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); - } -} - -/*! - \brief initialize CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] can_parameter_init: parameters for CAN initializtion - \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE - \arg resync_jump_width: 0x00 - 0x07 - \arg time_segment_1: 0x00 - 0x7F - \arg time_segment_2: 0x00 - 0x1F - \arg time_triggered: ENABLE or DISABLE - \arg auto_bus_off_recovery: ENABLE or DISABLE - \arg auto_wake_up: ENABLE or DISABLE - \arg auto_retrans: ENABLE or DISABLE - \arg rec_fifo_overwrite: ENABLE or DISABLE - \arg trans_fifo_order: ENABLE or DISABLE - \arg prescaler: 0x0000 - 0x03FF - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -#ifdef GD_MBED_USED -ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) -#else -ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) -#endif -{ - uint32_t timeout = CAN_TIMEOUT; - ErrStatus flag = ERROR; - - /* disable sleep mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - /* enable initialize mode */ - CAN_CTL(can_periph) |= CAN_CTL_IWMOD; - /* wait ACK */ - while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { - timeout--; - } - /* check initialize working success */ - if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { - flag = ERROR; - } else { - /* set the bit timing register */ - CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ - BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ - BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ - BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ - BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); - - /* time trigger communication mode */ - if (ENABLE == can_parameter_init->time_triggered) { - CAN_CTL(can_periph) |= CAN_CTL_TTC; - } else { - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - } - /* automatic bus-off managment */ - if (ENABLE == can_parameter_init->auto_bus_off_recovery) { - CAN_CTL(can_periph) |= CAN_CTL_ABOR; - } else { - CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; - } - /* automatic wakeup mode */ - if (ENABLE == can_parameter_init->auto_wake_up) { - CAN_CTL(can_periph) |= CAN_CTL_AWU; - } else { - CAN_CTL(can_periph) &= ~CAN_CTL_AWU; - } - /* automatic retransmission mode */ - if (ENABLE == can_parameter_init->auto_retrans) { - CAN_CTL(can_periph) &= ~CAN_CTL_ARD; - } else { - CAN_CTL(can_periph) |= CAN_CTL_ARD; - } - /* receive fifo overwrite mode */ - if (ENABLE == can_parameter_init->rec_fifo_overwrite) { - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - } else { - CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } - /* transmit fifo order */ - if (ENABLE == can_parameter_init->trans_fifo_order) { - CAN_CTL(can_periph) |= CAN_CTL_TFO; - } else { - CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } - /* disable initialize mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; - timeout = CAN_TIMEOUT; - /* wait the ACK */ - while ((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { - timeout--; - } - /* check exit initialize mode */ - if (0U != timeout) { - flag = SUCCESS; - } - } - return flag; -} - -/*! - \brief initialize CAN FD function - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] can_fdframe_init: parameters for CAN FD initializtion - \arg fd_frame: ENABLE or DISABLE - \arg excp_event_detect: ENABLE or DISABLE - \arg delay_compensation: ENABLE or DISABLE - \arg p_delay_compensation: the pointer of tdc struct - can_fd_tdc_struct: - tdc_mode: CAN_TDCMOD_CALC_AND_OFFSET or CAN_TDCMOD_OFFSET - tdc_filter: 0x00 - 0x07 - tdc_offset: 0x00 - 0x07 - \arg iso_bosch: CAN_FDMOD_ISO or CAN_FDMOD_BOSCH - \arg esi_mode: CAN_ESIMOD_HARDWARE or CAN_ESIMOD_SOFTWARE - \arg data_resync_jump_width: 0x00 - 0x07 - \arg data_time_segment_1: 0x00 - 0x0F - \arg data_time_segment_2: 0x00 - 0x07 - \arg data_prescaler: 0x0000 - 0x03FF - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_fd_init(uint32_t can_periph, can_fdframe_struct *can_fdframe_init) -{ - uint32_t timeout = CAN_TIMEOUT; - uint32_t tempreg = 0U; - - /* check null pointer */ - if (0 == can_fdframe_init) { - return ERROR; - } - /* disable sleep mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - /* enable initialize mode */ - CAN_CTL(can_periph) |= CAN_CTL_IWMOD; - /* wait ACK */ - while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { - timeout--; - } - /* check initialize working success */ - if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { - return ERROR; - } else { - /* set the data bit timing register */ - CAN_DBT(can_periph) = (BT_DSJW((uint32_t)can_fdframe_init->data_resync_jump_width) | \ - BT_DBS1((uint32_t)can_fdframe_init->data_time_segment_1) | \ - BT_DBS2((uint32_t)can_fdframe_init->data_time_segment_2) | \ - BT_BAUDPSC(((uint32_t)can_fdframe_init->data_prescaler - 1U))); - - tempreg = can_fdframe_init->esi_mode | can_fdframe_init->iso_bosch; - - /* Protocol exception event detection */ - if (ENABLE == can_fdframe_init->excp_event_detect) { - tempreg &= ~CAN_FDCTL_PRED; - } else { - tempreg |= CAN_FDCTL_PRED; - } - - /* Transmitter delay compensation mode */ - if (ENABLE == can_fdframe_init->delay_compensation) { - tempreg |= CAN_FDCTL_TDCEN; - /* p_delay_compensation pointer should be config when TDC mode is enabled */ - if (0 != can_fdframe_init->p_delay_compensation) { - tempreg |= (can_fdframe_init->p_delay_compensation->tdc_mode & CAN_FDCTL_TDCMOD); - CAN_FDTDC(can_periph) = (FDTDC_TDCF(can_fdframe_init->p_delay_compensation->tdc_filter) | FDTDC_TDCO(can_fdframe_init->p_delay_compensation->tdc_offset)); - } else { - return ERROR; - } - } else { - /* Transmitter delay compensation mode is disabled */ - tempreg &= ~CAN_FDCTL_TDCEN; - } - - /* FD operation mode */ - if (ENABLE == can_fdframe_init->fd_frame) { - tempreg |= CAN_FDCTL_FDEN; - } else { - tempreg &= ~CAN_FDCTL_FDEN; - } - CAN_FDCTL(can_periph) = tempreg; - - /* disable initialize mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; - timeout = CAN_TIMEOUT; - /* wait the ACK */ - while ((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { - timeout--; - } - /* check exit initialize mode */ - if (0U == timeout) { - return ERROR; - } - } - - return SUCCESS; -} - -/*! - \brief initialize CAN filter - \param[in] can_filter_parameter_init: struct for CAN filter initialization - \arg filter_list_high: 0x0000 - 0xFFFF - \arg filter_list_low: 0x0000 - 0xFFFF - \arg filter_mask_high: 0x0000 - 0xFFFF - \arg filter_mask_low: 0x0000 - 0xFFFF - \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 - \arg filter_number: 0 - 27 - \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT - \arg filter_enable: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init) -{ - uint32_t val = 0U; - - val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* disable filter */ - CAN_FW(CAN0) &= ~(uint32_t)val; - - /* filter 16 bits */ - if (CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) { - /* set filter 16 bits */ - CAN_FSCFG(CAN0) &= ~(uint32_t)val; - /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); - } - /* filter 32 bits */ - if (CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) { - /* set filter 32 bits */ - CAN_FSCFG(CAN0) |= (uint32_t)val; - /* 32 bits list or first 32 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* 32 bits mask or second 32 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); - } - - /* filter mode */ - if (CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) { - /* mask mode */ - CAN_FMCFG(CAN0) &= ~(uint32_t)val; - } else { - /* list mode */ - CAN_FMCFG(CAN0) |= (uint32_t)val; - } - - /* filter FIFO */ - if (CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) { - /* FIFO0 */ - CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - } else { - /* FIFO1 */ - CAN_FAFIFO(CAN0) |= (uint32_t)val; - } - - /* filter working */ - if (ENABLE == can_filter_parameter_init->filter_enable) { - - CAN_FW(CAN0) |= (uint32_t)val; - } - - /* filter lock enable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief CAN filter mask mode initialization - \param[in] id: extended(11-bits) or standard(29-bits) identifier - \arg 0x00000000 - 0x1FFFFFFF - \param[in] mask: extended(11-bits) or standard(29-bits) identifier mask - \arg 0x00000000 - 0x1FFFFFFF - \param[in] format_fifo: format and fifo states - only one parameter can be selected which is shown as below: - \arg CAN_STANDARD_FIFO0 - \arg CAN_STANDARD_FIFO1 - \arg CAN_EXTENDED_FIFO0 - \arg CAN_EXTENDED_FIFO1 - \param[in] filter_number: filter sequence number - \arg 0x00 - 0x1C - \param[out] none - \retval none -*/ -void can_filter_mask_mode_init(uint32_t id, uint32_t mask, can_format_fifo_enum format_fifo, uint16_t filter_number) -{ - can_filter_parameter_struct can_filter; - - /* Initialize the filter structure */ - can_struct_para_init(CAN_FILTER_STRUCT, &can_filter); - - /* filter config */ - can_filter.filter_number = filter_number; - can_filter.filter_mode = CAN_FILTERMODE_MASK; - can_filter.filter_bits = CAN_FILTERBITS_32BIT; - can_filter.filter_enable = ENABLE; - - switch (format_fifo) { - /* standard FIFO 0 */ - case CAN_STANDARD_FIFO0: - can_filter.filter_fifo_number = CAN_FIFO0; - /* configure SFID[10:0] */ - can_filter.filter_list_high = (uint16_t)id << 5; - can_filter.filter_list_low = 0x0000U; - /* configure SFID[10:0] mask */ - can_filter.filter_mask_high = (uint16_t)mask << 5; - /* both data and remote frames can be received */ - can_filter.filter_mask_low = 0x0000U; - - break; - /* standard FIFO 1 */ - case CAN_STANDARD_FIFO1: - can_filter.filter_fifo_number = CAN_FIFO1; - /* configure SFID[10:0] */ - can_filter.filter_list_high = (uint16_t)id << 5; - can_filter.filter_list_low = 0x0000U; - /* configure SFID[10:0] mask */ - can_filter.filter_mask_high = (uint16_t)mask << 5; - /* both data and remote frames can be received */ - can_filter.filter_mask_low = 0x0000U; - - break; - /* extended FIFO 0 */ - case CAN_EXTENDED_FIFO0: - can_filter.filter_fifo_number = CAN_FIFO0; - /* configure EFID[28:13] */ - can_filter.filter_list_high = (uint16_t)id >> 13; - /* configure EFID[12:0] and frame format bit set */ - can_filter.filter_list_low = (0x00FFU & (uint16_t)(id << 3)) | (1U << 2); - /* configure EFID[28:13] mask */ - can_filter.filter_mask_high = (uint16_t)mask >> 13; - /* configure EFID[12:0] and frame format bit mask */ - /* both data and remote frames can be received */ - can_filter.filter_mask_low = (0x00FFU & (uint16_t)(mask << 3)) | (1U << 2); - - break; - /* extended FIFO 1 */ - case CAN_EXTENDED_FIFO1: - can_filter.filter_fifo_number = CAN_FIFO1; - /* configure EFID[28:13] */ - can_filter.filter_list_high = (uint16_t)id >> 13; - /* configure EFID[12:0] and frame format bit set */ - can_filter.filter_list_low = (0x00FFU & (uint16_t)(id << 3)) | (1U << 2); - /* configure EFID[28:13] mask */ - can_filter.filter_mask_high = (uint16_t)mask >> 13; - /* configure EFID[12:0] and frame format bit mask */ - /* both data and remote frames can be received */ - can_filter.filter_mask_low = (0x00FFU & (uint16_t)(mask << 3)) | (1U << 2); - - break; - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); - } - - can_filter_init(&can_filter); -} - -/*! - \brief CAN baud rate configure in classic mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] hz: frequency, range from 1 to 1000000 Hz - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_frequency_set(uint32_t can_periph, uint32_t hz) -{ - ErrStatus reval = SUCCESS; - uint32_t reg_temp; - /* The maximum baud rate support to 1M */ - if (hz <= 1000000U) { - if (SUCCESS == can_working_mode_set(can_periph, CAN_MODE_INITIALIZE)) { - reg_temp = CAN_BT(can_periph); - reg_temp &= (CAN_BT_LCMOD | CAN_BT_SCMOD); - CAN_BT(can_periph) = reg_temp | dev_can_baudrate_set(hz); - } else { - reval = ERROR; - } - - if (SUCCESS != can_working_mode_set(can_periph, CAN_MODE_NORMAL)) { - reval = ERROR; - } - } else { - reval = ERROR; - } - - return reval; -} - -/*! - \brief CAN baud rate configure in FD mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] hz: frequency - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_fd_frequency_set(uint32_t can_periph, uint32_t hz) -{ - ErrStatus reval = SUCCESS; - - if (SUCCESS == can_working_mode_set(can_periph, CAN_MODE_INITIALIZE)) { - CAN_DBT(can_periph) = dev_can_baudrate_set(hz); - } else { - reval = ERROR; - } - - if (SUCCESS != can_working_mode_set(can_periph, CAN_MODE_NORMAL)) { - reval = ERROR; - } - - return reval; -} - -/*! - \brief CAN communication mode configure - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] mode: communication mode - only one parameter can be selected which is shown as below: - \arg CAN_NORMAL_MODE - \arg CAN_LOOPBACK_MODE - \arg CAN_SILENT_MODE - \arg CAN_SILENT_LOOPBACK_MODE - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_monitor_mode_set(uint32_t can_periph, uint8_t mode) -{ - ErrStatus reval = SUCCESS; - uint32_t timeout = CAN_TIMEOUT; - - if (mode == (mode & CAN_SILENT_LOOPBACK_MODE)) { - /* disable sleep mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); - /* set initialize mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; - /* wait the acknowledge */ - timeout = CAN_TIMEOUT; - while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { - timeout--; - } - - if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { - reval = ERROR; - } else { - CAN_BT(can_periph) &= ~BT_MODE(3); - CAN_BT(can_periph) |= BT_MODE(mode); - - timeout = CAN_TIMEOUT; - /* enter normal mode */ - CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); - /* wait the acknowledge */ - while ((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { - timeout--; - } - if (0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) { - reval = ERROR; - } - } - } else { - reval = ERROR; - } - - return reval; -} - -/*! - \brief CAN FD frame function enable - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_fd_function_enable(uint32_t can_periph) -{ - CAN_FDCTL(can_periph) |= CAN_FDCTL_FDEN; -} - -/*! - \brief CAN FD frame function disable - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_fd_function_disable(uint32_t can_periph) -{ - CAN_FDCTL(can_periph) &= ~CAN_FDCTL_FDEN; -} - -/*! - \brief set CAN1 fliter start bank number - \param[in] start_bank: CAN1 start bank number - only one parameter can be selected which is shown as below: - \arg (1..27) - \param[out] none - \retval none -*/ -void can1_filter_start_bank(uint8_t start_bank) -{ - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* set CAN1 filter start number */ - CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; - CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief enable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_debug_freeze_enable(uint32_t can_periph) -{ - /* set DFZ bit */ - CAN_CTL(can_periph) |= CAN_CTL_DFZ; - if (CAN0 == can_periph) { - dbg_periph_enable(DBG_CAN0_HOLD); - } else { - dbg_periph_enable(DBG_CAN1_HOLD); - } -} - -/*! - \brief disable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_debug_freeze_disable(uint32_t can_periph) -{ - /* set DFZ bit */ - CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; - - if (CAN0 == can_periph) { - dbg_periph_disable(DBG_CAN0_HOLD); - } else { - dbg_periph_disable(DBG_CAN1_HOLD); - } -} - -/*! - \brief enable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_time_trigger_mode_enable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* enable the tcc mode */ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - /* enable time stamp */ - for (mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { - CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; - } -} - -/*! - \brief disable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_time_trigger_mode_disable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* disable the TCC mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - /* reset TSEN bits */ - for (mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; - } -} - -/*! - \brief transmit CAN message - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] transmit_message: struct for CAN transmit message - \arg tx_sfid: 0x00000000 - 0x000007FF - \arg tx_efid: 0x00000000 - 0x1FFFFFFF - \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg tx_dlenc: 1 - 7 - \arg tx_data[]: 0x00 - 0xFF - \param[out] none - \retval mailbox_number -*/ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) -{ - uint8_t mailbox_number = CAN_MAILBOX0; - uint8_t i = 0U; - uint8_t hit = 0U; - uint32_t canfd_en = 0U; - volatile uint32_t p_temp; - uint32_t reg_temp = 0U; - - /* select one empty mailbox */ - if (CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)) { - mailbox_number = CAN_MAILBOX0; - } else if (CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)) { - mailbox_number = CAN_MAILBOX1; - } else if (CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)) { - mailbox_number = CAN_MAILBOX2; - } else { - mailbox_number = CAN_NOMAILBOX; - } - /* return no mailbox empty */ - if (CAN_NOMAILBOX == mailbox_number) { - return CAN_NOMAILBOX; - } - - CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if (CAN_FF_STANDARD == transmit_message->tx_ff) { - /* set transmit mailbox standard identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - } else { - /* set transmit mailbox extended identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); - } - - if (CAN_FDF_CLASSIC == transmit_message->fd_flag) { - /* set the data length */ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; - CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; - /* set the data */ - CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); - CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); - } else { - canfd_en = CAN_FDCTL(can_periph) & CAN_FDCTL_FDEN; - /* check FD funciton has been enabled */ - if (canfd_en) { - if (transmit_message->tx_dlen <= 8U) { - /* set the data length */ - reg_temp |= transmit_message->tx_dlen; - } else { - /* data length greater than 8 */ - for (i = 0U; i < 7U; i++) { - if (transmit_message->tx_dlen == g_can_fdlength_table[i]) { - hit = 1U; - break; - } - } - /* data length is valid */ - if (1U == hit) { - reg_temp |= 9U + i; - } else { - CAN_ERROR_HANDLE("dlen is invalid \r\n"); - } - } - reg_temp |= (((uint32_t)transmit_message->fd_brs << 5U) | ((uint32_t)transmit_message->fd_esi << 4U) | ((uint32_t)transmit_message->fd_flag << 7U)); - CAN_TMP(can_periph, mailbox_number) = reg_temp; - /* set the data */ - i = transmit_message->tx_dlen / 4U; - p_temp = (uint32_t)transmit_message->tx_data; - if (0U == i) { - CAN_TMDATA0(can_periph, mailbox_number) = *(uint32_t *)p_temp; - } else { - for (; i > 0U; i--) { - CAN_TMDATA0(can_periph, mailbox_number) = *(uint32_t *)p_temp; - p_temp = ((uint32_t)((uint32_t)p_temp + 4U)); - } - } - } else { - CAN_ERROR_HANDLE("CAN FD function disabled \r\n"); - } - } - - /* enable transmission */ - CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; - - return mailbox_number; -} - -/*! - \brief get CAN transmit state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOX(x=0,1,2) - \param[out] none - \retval can_transmit_state_enum -*/ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) -{ - can_transmit_state_enum state = CAN_TRANSMIT_FAILED; - uint32_t val = 0U; - - /* check selected mailbox state */ - switch (mailbox_number) { - /* mailbox0 */ - case CAN_MAILBOX0: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); - break; - /* mailbox1 */ - case CAN_MAILBOX1: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); - break; - /* mailbox2 */ - case CAN_MAILBOX2: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); - break; - default: - val = CAN_TRANSMIT_FAILED; - break; - } - - switch (val) { - /* transmit pending */ - case (CAN_STATE_PENDING): - state = CAN_TRANSMIT_PENDING; - break; - /* mailbox0 transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): - state = CAN_TRANSMIT_OK; - break; - /* mailbox1 transmit succeeded */ - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): - state = CAN_TRANSMIT_OK; - break; - /* mailbox2 transmit succeeded */ - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): - state = CAN_TRANSMIT_OK; - break; - /* transmit failed */ - default: - state = CAN_TRANSMIT_FAILED; - break; - } - return state; -} - -/*! - \brief stop CAN transmission - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOXx(x=0,1,2) - \param[out] none - \retval none -*/ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) -{ - if (CAN_MAILBOX0 == mailbox_number) { - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while (CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) { - } - } else if (CAN_MAILBOX1 == mailbox_number) { - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while (CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) { - } - } else if (CAN_MAILBOX2 == mailbox_number) { - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while (CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) { - } - } else { - /* illegal parameters */ - } -} - -/*! - \brief CAN receive message - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - \arg CAN_FIFOx(x=0,1) - \param[out] receive_message: struct for CAN receive message - \arg rx_sfid: 0x00000000 - 0x000007FF - \arg rx_efid: 0x00000000 - 0x1FFFFFFF - \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg rx_dlenc: 1 - 7 - \arg rx_data[]: 0x00 - 0xFF - \arg rx_fi: 0 - 27 - \retval none -*/ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message) -{ - uint32_t canfd_en = 0U; - volatile uint32_t p_temp; - uint32_t data_temp; - uint8_t canfd_recv_cnt = 0U; - uint8_t i; - - /* get the frame format */ - receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if (CAN_FF_STANDARD == receive_message->rx_ff) { - /* get standard identifier */ - receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - } else { - /* get extended identifier */ - receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); - } - - /* get frame type */ - receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* filtering index */ - receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - receive_message->fd_flag = (uint8_t)(CAN_RFIFOMP_FDF & CAN_RFIFOMP(can_periph, fifo_number)); - - if (CAN_FDF_CLASSIC == receive_message->fd_flag) { - /* get recevie data length */ - receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); - /* receive data */ - receive_message->rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message->rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message->rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message->rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message->rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message->rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message->rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message->rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - } else { - canfd_en = CAN_FDCTL(can_periph) & CAN_FDCTL_FDEN; - /* check FD funciton has been enabled */ - if (canfd_en) { - /* get recevie data length */ - canfd_recv_cnt = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); - - if (canfd_recv_cnt <= 8U) { - /* set the data length */ - receive_message->rx_dlen = canfd_recv_cnt; - } else { - receive_message->rx_dlen = g_can_fdlength_table[canfd_recv_cnt - 9U]; - } - - receive_message->fd_brs = (uint8_t)((CAN_RFIFOMP(can_periph, fifo_number) & CAN_RFIFOMP_BRS) >> 5); - receive_message->fd_esi = (uint8_t)((CAN_RFIFOMP(can_periph, fifo_number) & CAN_RFIFOMP_ESI) >> 4); - - /* get the data */ - i = receive_message->rx_dlen / 4U; - p_temp = (uint32_t)(uint32_t)receive_message->rx_data; - if (0U == i) { - data_temp = CAN_RFIFOMDATA0(can_periph, fifo_number); - *(uint32_t *)p_temp = data_temp; - } else { - /* get the data by reading from CAN_RFIFOMDATA0 register*/ - for (; i > 0U; i--) { - data_temp = CAN_RFIFOMDATA0(can_periph, fifo_number); - *(uint32_t *)p_temp = data_temp; - p_temp = ((uint32_t)((uint32_t)p_temp + 4U)); - } - } - } else { - CAN_ERROR_HANDLE("CAN FD function disabled \r\n"); - } - } - - /* release FIFO */ - if (CAN_FIFO0 == fifo_number) { - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - } else { - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - } -} - -/*! - \brief release FIFO0 - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval none -*/ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) -{ - if (CAN_FIFO0 == fifo_number) { - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - } else if (CAN_FIFO1 == fifo_number) { - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - } else { - /* illegal parameters */ - CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); - } -} - -/*! - \brief CAN receive message length - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval message length -*/ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) -{ - uint8_t val = 0U; - - if (CAN_FIFO0 == fifo_number) { - /* FIFO0 */ - val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - } else if (CAN_FIFO1 == fifo_number) { - /* FIFO1 */ - val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - } else { - /* illegal parameters */ - } - return val; -} - -/*! - \brief set CAN working mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] can_working_mode - only one parameter can be selected which is shown as below: - \arg CAN_MODE_INITIALIZE - \arg CAN_MODE_NORMAL - \arg CAN_MODE_SLEEP - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) -{ - ErrStatus flag = ERROR; - /* timeout for IWS or also for SLPWS bits */ - uint32_t timeout = CAN_TIMEOUT; - - if (CAN_MODE_INITIALIZE == working_mode) { - /* disable sleep mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); - /* set initialize mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; - /* wait the acknowledge */ - while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { - timeout--; - } - if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { - flag = ERROR; - } else { - flag = SUCCESS; - } - } else if (CAN_MODE_NORMAL == working_mode) { - /* enter normal mode */ - CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); - /* wait the acknowledge */ - while ((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { - timeout--; - } - if (0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) { - flag = ERROR; - } else { - flag = SUCCESS; - } - } else if (CAN_MODE_SLEEP == working_mode) { - /* disable initialize mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); - /* set sleep mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; - /* wait the acknowledge */ - while ((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) { - timeout--; - } - if (CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { - flag = ERROR; - } else { - flag = SUCCESS; - } - } else { - flag = ERROR; - } - return flag; -} - -/*! - \brief wake up CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_wakeup(uint32_t can_periph) -{ - ErrStatus flag = ERROR; - uint32_t timeout = CAN_TIMEOUT; - - /* wakeup */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while ((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) { - timeout--; - } - /* check state */ - if (0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { - flag = ERROR; - } else { - flag = SUCCESS; - } - return flag; -} - -/*! - \brief get CAN error type - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval can_error_enum - \arg CAN_ERROR_NONE: no error - \arg CAN_ERROR_FILL: fill error - \arg CAN_ERROR_FORMATE: format error - \arg CAN_ERROR_ACK: ACK error - \arg CAN_ERROR_BITRECESSIVE: bit recessive - \arg CAN_ERROR_BITDOMINANTER: bit dominant error - \arg CAN_ERROR_CRC: CRC error - \arg CAN_ERROR_SOFTWARECFG: software configure -*/ -can_error_enum can_error_get(uint32_t can_periph) -{ - can_error_enum error; - error = CAN_ERROR_NONE; - - /* get error type */ - error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); - return error; -} - -/*! - \brief get CAN receive error number - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval error number -*/ -uint8_t can_receive_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - /* get error count */ - val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief get CAN transmit error number - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval error number -*/ -uint8_t can_transmit_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - -/*! - \brief get CAN flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \arg CAN_FLAG_BOERR: bus-off error - \arg CAN_FLAG_PERR: passive error - \arg CAN_FLAG_WERR: warning error - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ - /* get flag and interrupt enable state */ - if (RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear CAN flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \param[out] none - \retval none -*/ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag) -{ - CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); -} - -/*! - \brief get CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - uint32_t ret1 = RESET; - uint32_t ret2 = RESET; - - /* get the staus of interrupt flag */ - ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); - /* get the staus of interrupt enale bit */ - ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); - if (ret1 && ret2) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval none -*/ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag)); -} - -/*! - \brief auto config can baud rate by frequency - \param[in] freq: the frequency of the baud rate - \param[out] none - \retval none -*/ -static unsigned int dev_can_baudrate_set(uint32_t freq) -{ - uint32_t reval; - uint32_t baud_psc; - uint32_t baud_psc_max; - uint32_t temp; - uint32_t bt_reg_config; - uint8_t flag; - uint32_t bits; - - flag = 0U; - /* computes the value that the CAN_BT register needs to be configured */ - /* (BAUDPSC[9:0] + 1) * ((BS1[3:0] + 1) + (BS2[2:0] + 1) + SJW(always 1)) */ - bt_reg_config = (rcu_clock_freq_get(CK_APB1) / freq); - /* BAUDPSC[9:0] minimum value */ - baud_psc = bt_reg_config / DEV_CAN_BT_SEG_MAX; - /* BAUDPSC[9:0] maximum value */ - baud_psc_max = bt_reg_config / DEV_CAN_BT_SEG_MIN; - - while ((!flag) && (baud_psc < baud_psc_max)) { - baud_psc++; - for (bits = 22u; bits > 0u; bits--) { - temp = (bits + 3U) * (baud_psc + 1U); - if (temp == bt_reg_config) { - flag = 1U; - break; - } - } - } - - if (flag) { - reval = ((timing_pts[bits][1] << 20) & DEV_CAN_BS2_MASK) - | ((timing_pts[bits][0] << 16) & DEV_CAN_BS1_MASK) - | ((0U << 24) & DEV_CAN_SJW_MASK) - | ((baud_psc) & DEV_CAN_BAUDPSC_MASK); - } else { - /* CAN_BT register reset value */ - reval = 0x01230000U; - CAN_ERROR_HANDLE("CAN baud rate config fail!! \r\n"); - } - - return reval; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_crc.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_crc.c deleted file mode 100644 index 661b076924d..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_crc.c +++ /dev/null @@ -1,130 +0,0 @@ -/*! - \file gd32e10x_crc.c - \brief CRC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_crc.h" - -#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) -#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) - -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_DATA = CRC_DATA_RESET_VALUE; - CRC_FDATA = CRC_FDATA_RESET_VALUE; - CRC_CTL = (uint32_t)CRC_CTL_RST; -} - -/*! - \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the value of the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the value of the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write data to the free data register - \param[in] free_data: specify 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief calculate the CRC value of a 32-bit data - \param[in] sdata: specified 32-bit data - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_single_data_calculate(uint32_t sdata) -{ - CRC_DATA = sdata; - return (CRC_DATA); -} - -/*! - \brief calculate the CRC value of an array of 32-bit values - \param[in] array: pointer to an array of 32-bit values - \param[in] size: size of the array - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) -{ - uint32_t index; - for (index = 0U; index < size; index++) { - CRC_DATA = array[index]; - } - return (CRC_DATA); -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_ctc.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_ctc.c deleted file mode 100644 index ce9d8aad59f..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_ctc.c +++ /dev/null @@ -1,392 +0,0 @@ -/*! - \file gd32e10x_ctc.c - \brief CTC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_ctc.h" - -#define CTC_FLAG_MASK ((uint32_t)0x00000700U) - -/* CTC register bit offset */ -#define CTC_TRIMVALUE_OFFSET ((uint32_t)8U) -#define CTC_TRIM_VALUE_OFFSET ((uint32_t)8U) -#define CTC_REFCAP_OFFSET ((uint32_t)16U) -#define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U) - -/*! - \brief reset CTC clock trim controller - \param[in] none - \param[out] none - \retval none -*/ -void ctc_deinit(void) -{ - /* reset CTC */ - rcu_periph_reset_enable(RCU_CTCRST); - rcu_periph_reset_disable(RCU_CTCRST); -} - -/*! - \brief enable CTC trim counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_enable(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; -} - -/*! - \brief disable CTC trim counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_disable(void) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); -} - -/*! - \brief configure the IRC48M trim value - \param[in] ctc_trim_value: 8-bit IRC48M trim value - \arg 0x00 - 0x3F - \param[out] none - \retval none -*/ -void ctc_irc48m_trim_value_config(uint8_t trim_value) -{ - /* clear TRIMVALUE bits */ - CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); - /* set TRIMVALUE bits */ - CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); -} - -/*! - \brief generate software reference source sync pulse - \param[in] none - \param[out] none - \retval none -*/ -void ctc_software_refsource_pulse_generate(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; -} - -/*! - \brief configure hardware automatically trim mode - \param[in] hardmode: - only one parameter can be selected which is shown as below: - \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable - \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable - \param[out] none - \retval none -*/ -void ctc_hardware_trim_mode_config(uint32_t hardmode) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); - CTC_CTL0 |= (uint32_t)hardmode; -} - -/*! - \brief configure reference signal source polarity - \param[in] polarity: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge - \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge - \param[out] none - \retval none -*/ -void ctc_refsource_polarity_config(uint32_t polarity) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); - CTC_CTL1 |= (uint32_t)polarity; -} - -/*! - \brief select reference signal source - \param[in] refs: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_GPIO: GPIO is selected - \arg CTC_REFSOURCE_LXTAL: LXTAL is selected - \arg CTC_REFSOURCE_USBSOF: USBFS_SOF is selected - \param[out] none - \retval none -*/ -void ctc_refsource_signal_select(uint32_t refs) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); - CTC_CTL1 |= (uint32_t)refs; -} - -/*! - \brief configure reference signal source prescaler - \param[in] prescaler: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided - \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 - \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 - \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 - \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 - \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 - \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 - \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 - \param[out] none - \retval none -*/ -void ctc_refsource_prescaler_config(uint32_t prescaler) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); - CTC_CTL1 |= (uint32_t)prescaler; -} - -/*! - \brief configure clock trim base limit value - \param[in] limit_value: 8-bit clock trim base limit value - \arg 0x00 - 0xFF - \param[out] none - \retval none -*/ -void ctc_clock_limit_value_config(uint8_t limit_value) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); - CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); -} - -/*! - \brief configure CTC counter reload value - \param[in] reload_value: 16-bit CTC counter reload value - \arg 0x0000 - 0xFFFF - \param[out] none - \retval none -*/ -void ctc_counter_reload_value_config(uint16_t reload_value) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); - CTC_CTL1 |= (uint32_t)reload_value; -} - -/*! - \brief read CTC counter capture value when reference sync pulse occurred - \param[in] none - \param[out] none - \retval the 16-bit CTC counter capture value -*/ -uint16_t ctc_counter_capture_value_read(void) -{ - uint16_t capture_value = 0U; - capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP) >> CTC_REFCAP_OFFSET); - return (capture_value); -} - -/*! - \brief read CTC trim counter direction when reference sync pulse occurred - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - \arg SET: CTC trim counter direction is down-counting - \arg RESET: CTC trim counter direction is up-counting -*/ -FlagStatus ctc_counter_direction_read(void) -{ - if (RESET != (CTC_STAT & CTC_STAT_REFDIR)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief read CTC counter reload value - \param[in] none - \param[out] none - \retval the 16-bit CTC counter reload value -*/ -uint16_t ctc_counter_reload_value_read(void) -{ - uint16_t reload_value = 0U; - reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); - return (reload_value); -} - -/*! - \brief read the IRC48M trim value - \param[in] none - \param[out] none - \retval the 8-bit IRC48M trim value -*/ -uint8_t ctc_irc48m_trim_value_read(void) -{ - uint8_t trim_value = 0U; - trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); - return (trim_value); -} - -/*! - \brief enable the CTC interrupt - \param[in] interrupt: CTC interrupt enable - one or more parameters can be selected which are shown as below: - \arg CTC_INT_CKOK: clock trim OK interrupt enable - \arg CTC_INT_CKWARN: clock trim warning interrupt enable - \arg CTC_INT_ERR: error interrupt enable - \arg CTC_INT_EREF: expect reference interrupt enable - \param[out] none - \retval none -*/ -void ctc_interrupt_enable(uint32_t interrupt) -{ - CTC_CTL0 |= (uint32_t)interrupt; -} - -/*! - \brief disable the CTC interrupt - \param[in] interrupt: CTC interrupt enable source - one or more parameters can be selected which are shown as below: - \arg CTC_INT_CKOK: clock trim OK interrupt enable - \arg CTC_INT_CKWARN: clock trim warning interrupt enable - \arg CTC_INT_ERR: error interrupt enable - \arg CTC_INT_EREF: expect reference interrupt enable - \param[out] none - \retval none -*/ -void ctc_interrupt_disable(uint32_t interrupt) -{ - CTC_CTL0 &= (uint32_t)(~interrupt); -} - -/*! - \brief get CTC interrupt flag - \param[in] interrupt: the CTC interrupt flag - only one parameter can be selected which is shown as below: - \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt - \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ctc_interrupt_flag_get(uint32_t interrupt) -{ - uint32_t intflag = 0U, intenable = 0U; - - /* check whether the interrupt is enabled */ - if (RESET != (interrupt & CTC_FLAG_MASK)) { - intenable = CTC_CTL0 & CTC_CTL0_ERRIE; - } else { - intenable = CTC_CTL0 & interrupt; - } - - /* get interrupt flag status */ - intflag = CTC_STAT & interrupt; - - if (intflag && intenable) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear CTC interrupt flag - \param[in] interrupt: the CTC interrupt flag - only one parameter can be selected which is shown as below: - \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt - \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt - \param[out] none - \retval none -*/ -void ctc_interrupt_flag_clear(uint32_t interrupt) -{ - if (RESET != (interrupt & CTC_FLAG_MASK)) { - CTC_INTC |= CTC_INTC_ERRIC; - } else { - CTC_INTC |= interrupt; - } -} - -/*! - \brief get CTC flag - \param[in] flag: the CTC flag - only one parameter can be selected which is shown as below: - \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag - \arg CTC_FLAG_EREF: expect reference flag - \arg CTC_FLAG_CKERR: clock trim error bit - \arg CTC_FLAG_REFMISS: reference sync pulse miss - \arg CTC_FLAG_TRIMERR: trim value error bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ctc_flag_get(uint32_t flag) -{ - if (RESET != (CTC_STAT & flag)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear CTC flag - \param[in] flag: the CTC flag - only one parameter can be selected which is shown as below: - \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag - \arg CTC_FLAG_EREF: expect reference flag - \arg CTC_FLAG_CKERR: clock trim error bit - \arg CTC_FLAG_REFMISS: reference sync pulse miss - \arg CTC_FLAG_TRIMERR: trim value error bit - \param[out] none - \retval none -*/ -void ctc_flag_clear(uint32_t flag) -{ - if (RESET != (flag & CTC_FLAG_MASK)) { - CTC_INTC |= CTC_INTC_ERRIC; - } else { - CTC_INTC |= flag; - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dac.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dac.c deleted file mode 100644 index eb2eef5a2e3..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dac.c +++ /dev/null @@ -1,557 +0,0 @@ -/*! - \file gd32e10x_dac.c - \brief DAC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_dac.h" - -/* DAC register bit offset */ -#define DAC1_REG_OFFSET ((uint32_t)16U) -#define DH_12BIT_OFFSET ((uint32_t)16U) -#define DH_8BIT_OFFSET ((uint32_t)8U) - -/*! - \brief deinitialize DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_deinit(void) -{ - rcu_periph_reset_enable(RCU_DACRST); - rcu_periph_reset_disable(RCU_DACRST); -} - -/*! - \brief enable DAC - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_enable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_CTL |= DAC_CTL_DEN0; - } else { - DAC_CTL |= DAC_CTL_DEN1; - } -} - -/*! - \brief disable DAC - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_disable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_CTL &= ~DAC_CTL_DEN0; - } else { - DAC_CTL &= ~DAC_CTL_DEN1; - } -} - -/*! - \brief enable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_dma_enable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_CTL |= DAC_CTL_DDMAEN0; - } else { - DAC_CTL |= DAC_CTL_DDMAEN1; - } -} - -/*! - \brief disable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_dma_disable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_CTL &= ~DAC_CTL_DDMAEN0; - } else { - DAC_CTL &= ~DAC_CTL_DDMAEN1; - } -} - -/*! - \brief enable DAC output buffer - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_enable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_CTL &= ~DAC_CTL_DBOFF0; - } else { - DAC_CTL &= ~DAC_CTL_DBOFF1; - } -} - -/*! - \brief disable DAC output buffer - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_disable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_CTL |= DAC_CTL_DBOFF0; - } else { - DAC_CTL |= DAC_CTL_DBOFF1; - } -} - -/*! - \brief get DAC output value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(uint32_t dac_periph) -{ - uint16_t data = 0U; - if (DAC0 == dac_periph) { - /* store the DAC0 output value */ - data = (uint16_t)DAC0_DO; - } else { - /* store the DAC1 output value */ - data = (uint16_t)DAC1_DO; - } - return data; -} - -/*! - \brief set the DAC specified data holding register value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] dac_align - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data: data to be loaded - \param[out] none - \retval none -*/ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) -{ - if (DAC0 == dac_periph) { - switch (dac_align) { - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC0_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC0_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC0_R8DH = data; - break; - default: - break; - } - } else { - switch (dac_align) { - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC1_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC1_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC1_R8DH = data; - break; - default: - break; - } - } -} - -/*! - \brief enable DAC trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_trigger_enable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_CTL |= DAC_CTL_DTEN0; - } else { - DAC_CTL |= DAC_CTL_DTEN1; - } -} - -/*! - \brief disable DAC trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_trigger_disable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_CTL &= ~DAC_CTL_DTEN0; - } else { - DAC_CTL &= ~DAC_CTL_DTEN1; - } -} - -/*! - \brief set DAC trigger source - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] triggersource: external triggers of DAC - only one parameter can be selected which is shown as below: - \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO - \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO - \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO - \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO - \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO - \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO - \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event - \arg DAC_TRIGGER_SOFTWARE: software trigger - \param[out] none - \retval none -*/ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) -{ - if (DAC0 == dac_periph) { - /* configure DAC0 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL0; - DAC_CTL |= triggersource; - } else { - /* configure DAC1 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC software trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \retval none -*/ -void dac_software_trigger_enable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_SWT |= DAC_SWT_SWTR0; - } else { - DAC_SWT |= DAC_SWT_SWTR1; - } -} - -/*! - \brief disable DAC software trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(uint32_t dac_periph) -{ - if (DAC0 == dac_periph) { - DAC_SWT &= ~DAC_SWT_SWTR0; - } else { - DAC_SWT &= ~DAC_SWT_SWTR1; - } -} - -/*! - \brief configure DAC wave mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] wave_mode - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_DISABLE: wave disable - \arg DAC_WAVE_MODE_LFSR: LFSR noise mode - \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode - \param[out] none - \retval none -*/ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) -{ - if (DAC0 == dac_periph) { - /* configure DAC0 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM0; - DAC_CTL |= wave_mode; - } else { - /* configure DAC1 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC wave bit width - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] bit_width - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 - \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 - \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 - \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 - \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 - \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 - \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 - \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 - \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 - \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 - \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 - \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 - \param[out] none - \retval none -*/ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) -{ - if (DAC0 == dac_periph) { - /* configure DAC0 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= bit_width; - } else { - /* configure DAC1 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (bit_width << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC LFSR noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] unmask_bits - only one parameter can be selected which is shown as below: - \arg DAC_LFSR_BIT0: unmask the LFSR bit0 - \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] - \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] - \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] - \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] - \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] - \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] - \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] - \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] - \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] - \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] - \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] - \param[out] none - \retval none -*/ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) -{ - if (DAC0 == dac_periph) { - /* configure DAC0 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= unmask_bits; - } else { - /* configure DAC1 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC triangle noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] amplitude - only one parameter can be selected which is shown as below: - \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 - \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 - \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 - \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 - \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 - \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 - \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 - \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 - \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 - \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 - \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 - \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 - \param[out] none - \retval none -*/ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) -{ - if (DAC0 == dac_periph) { - /* configure DAC0 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= amplitude; - } else { - /* configure DAC1 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (amplitude << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL |= (ctl); -} - -/*! - \brief disable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL &= (~ctl); -} - -/*! - \brief enable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_enable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); -} - -/*! - \brief disable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_disable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT &= (~swt); -} - -/*! - \brief enable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL &= (~ctl); -} - -/*! - \brief disable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL |= (ctl); -} - -/*! - \brief set DAC concurrent mode data holding register value - \param[in] dac_align - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded - \param[out] none - \retval none -*/ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) -{ - uint32_t data = 0U; - switch (dac_align) { - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; - DACC_R8DH = data; - break; - default: - break; - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dbg.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dbg.c deleted file mode 100644 index 2863553dad6..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dbg.c +++ /dev/null @@ -1,152 +0,0 @@ -/*! - \file gd32e10x_dbg.c - \brief DBG driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_dbg.h" - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_CTL |= (uint32_t)dbg_periph; -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_CTL &= ~(uint32_t)dbg_periph; -} - -/*! - \brief enable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_enable(void) -{ - DBG_CTL |= DBG_CTL_TRACE_IOEN; -} - -/*! - \brief disable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_disable(void) -{ - DBG_CTL &= ~DBG_CTL_TRACE_IOEN; -} - -/*! - \brief trace pin mode selection - \param[in] trace_mode: - only one parameter can be selected which is shown as below: - \arg TRACE_MODE_ASYNC: trace pin used for async mode - \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 - \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 - \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 - \param[out] none - \retval none -*/ -void dbg_trace_pin_mode_set(uint32_t trace_mode) -{ - DBG_CTL &= ~DBG_CTL_TRACE_MODE; - DBG_CTL |= trace_mode; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dma.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dma.c deleted file mode 100644 index cbd3de72b6c..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_dma.c +++ /dev/null @@ -1,739 +0,0 @@ -/*! - \file gd32e10x_dma.c - \brief DMA driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_dma.h" - -#define DMA_WRONG_HANDLE while(1){} - -/* check whether peripheral matches channels or not */ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); - -/*! - \brief deinitialize DMA a channel registers - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel is deinitialized - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - /* disable the DMA channel */ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); -} - -/*! - \brief initialize the parameters of DMA struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_struct_para_init(dma_parameter_struct *init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; - init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory_addr = 0U; - init_struct->memory_width = 0U; - init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; - init_struct->number = 0U; - init_struct->direction = DMA_PERIPHERAL_TO_MEMORY; - init_struct->priority = DMA_PRIORITY_LOW; -} - -/*! - \brief initialize DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel is initialized - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] init_struct: the data needed to initialize DMA channel - periph_addr: peripheral base address - periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE - memory_addr: memory base address - memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -#ifdef GD_MBED_USED -void dma_para_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) -#else -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) -#endif -{ - uint32_t ctl; - - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - /* configure peripheral base address */ - DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); - - /* configure peripheral transfer width,memory transfer width and priority */ - ctl = DMA_CHCTL(dma_periph, channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); - ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); - DMA_CHCTL(dma_periph, channelx) = ctl; - - /* configure peripheral increasing mode */ - if (DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; - } else { - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; - } - - /* configure memory increasing mode */ - if (DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; - } else { - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure the direction of data transfer */ - if (DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) { - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; -} - -/*! - \brief disable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; -} - -/*! - \brief enable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief set DMA peripheral base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHPADDR(dma_periph, channelx) = address; -} - -/*! - \brief set DMA memory base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHMADDR(dma_periph, channelx) = address; -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] number: the number of remaining data to be transferred by the DMA - \arg 0x0000-0xFFFF - \param[out] none - \retval none -*/ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - return (uint32_t)DMA_CHCNT(dma_periph, channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] priority: priority level of this channel - only one parameter can be selected which is shown as below: - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] mwidth: transfer data width of memory - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) -{ - uint32_t ctl; - - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= mwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] pwidth: transfer data width of peripheral - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) -{ - uint32_t ctl; - - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= pwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief enable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; -} - -/*! - \brief disable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; -} - -/*! - \brief enable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; -} - -/*! - \brief disable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] direction: specify the direction of data transfer - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - if (DMA_PERIPHERAL_TO_MEMORY == direction) { - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief check DMA flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel to get flag - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - FlagStatus reval; - - /* check whether the flag is set or not */ - if (RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))) { - reval = SET; - } else { - reval = RESET; - } - - return reval; -} - -/*! - \brief clear the flag of a DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - - switch (flag) { - case DMA_INT_FLAG_FTF: - /* check whether the full transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - /* check whether the half transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - /* check whether the error interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; - break; - default: - DMA_WRONG_HANDLE - } - - /* when the interrupt flag is set and enabled, return SET */ - if ((0U != interrupt_flag) && (0U != interrupt_enable)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the interrupt flag of a DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= source; -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~source; -} - -/*! - \brief check whether peripheral matches channels or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specified DMA channel - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) -{ - ErrStatus val = SUCCESS; - - if (DMA1 == dma_periph) { - /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ - if (channelx > DMA_CH4) { - val = ERROR; - } - } - - return val; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_exmc.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_exmc.c deleted file mode 100644 index 6efd98608ba..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_exmc.c +++ /dev/null @@ -1,232 +0,0 @@ -/*! - \file gd32e10x_exmc.c - \brief EXMC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_exmc.h" - -/* EXMC bank0 register reset value */ -#define BANK0_SNCTL_RESET ((uint32_t)0x000030DBU) -#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) -#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) - -/* EXMC register bit offset */ -#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) -#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) -#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) -#define SNCTL_WREN_OFFSET ((uint32_t)12U) -#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) -#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) -#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) - -#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) -#define SNTCFG_DSET_OFFSET ((uint32_t)8U) -#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) - -#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U) -#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U) -#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U) - -/*! - \brief deinitialize EXMC NOR/SRAM bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_norsram_deinit(void) -{ - /* reset the registers */ - EXMC_SNCTL = BANK0_SNCTL_RESET; - - EXMC_SNTCFG = BANK0_SNTCFG_RESET; - EXMC_SNWTCFG = BANK0_SNWTCFG_RESET; -} - -/*! - \brief initialize the struct exmc_norsram_parameter_struct - \param[in] none - \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) -{ - /* configure the structure with default value */ - exmc_norsram_init_struct->address_data_mux = ENABLE; - exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_NOR; - exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B; - exmc_norsram_init_struct->burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; - exmc_norsram_init_struct->wrap_burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; - exmc_norsram_init_struct->memory_write = ENABLE; - exmc_norsram_init_struct->nwait_signal = ENABLE; - exmc_norsram_init_struct->extended_mode = DISABLE; - exmc_norsram_init_struct->asyn_wait = DISABLE; - exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; - - /* read/write timing configure */ - exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; - exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; - exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - - /* write timing configure, when extended mode is used */ - exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; -} - -/*! - \brief initialize EXMC NOR/SRAM bank - \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter - write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE - asyn_wait: ENABLE or DISABLE - nwait_signal: ENABLE or DISABLE - memory_write: ENABLE or DISABLE - nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING - wrap_burst_mode: ENABLE or DISABLE - nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH - burst_mode: ENABLE or DISABLE - databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B - memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR - address_data_mux: ENABLE or DISABLE - read_write_timing: struct exmc_norsram_timing_parameter_struct set the time - write_timing: struct exmc_norsram_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) -{ - uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; - - /* get the register value */ - snctl = EXMC_SNCTL; - - /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_NRMUX | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NREN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | - EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | - EXMC_SNCTL_SYNCWR)); - - snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; - - sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U) & EXMC_SNTCFG_ASET) | - (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD) | - (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET) | - (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT) | - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - - /* nor flash access enable */ - if (EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { - snctl |= (uint32_t)EXMC_SNCTL_NREN; - } - - /* extended mode configure */ - if (ENABLE == exmc_norsram_init_struct->extended_mode) { - snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) | - (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNWTCFG_WAHLD_OFFSET) & EXMC_SNWTCFG_WAHLD) | - (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNWTCFG_WDSET_OFFSET) & EXMC_SNWTCFG_WDSET) | - (((exmc_norsram_init_struct->write_timing->bus_latency - 1U) << SNWTCFG_WBUSLAT_OFFSET) & EXMC_SNWTCFG_WBUSLAT) | - exmc_norsram_init_struct->write_timing->asyn_access_mode; - } else { - snwtcfg = BANK0_SNWTCFG_RESET; - } - - /* configure the registers */ - EXMC_SNCTL = snctl; - EXMC_SNTCFG = sntcfg; - EXMC_SNWTCFG = snwtcfg; -} - -/*! - \brief enable EXMC NOR/PSRAM bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_norsram_enable(void) -{ - EXMC_SNCTL |= (uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief disable EXMC NOR/PSRAM bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_norsram_disable(void) -{ - EXMC_SNCTL &= ~(uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief configure CRAM page size - \param[in] page_size: CRAM page size - only one parameter can be selected which is shown as below: - \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access - \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes - \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes - \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes - \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes - \param[out] none - \retval none -*/ -void exmc_norsram_page_size_config(uint32_t page_size) -{ - /* reset the bits */ - EXMC_SNCTL &= ~EXMC_SNCTL_CPS; - /* set the CPS bits */ - EXMC_SNCTL |= page_size; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_exti.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_exti.c deleted file mode 100644 index 4be4c233c12..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_exti.c +++ /dev/null @@ -1,253 +0,0 @@ -/*! - \file gd32e10x_exti.c - \brief EXTI driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_exti.h" - -/*! - \brief deinitialize the EXTI - \param[in] none - \param[out] none - \retval none -*/ -void exti_deinit(void) -{ - /* reset the value of all the EXTI registers */ - EXTI_INTEN = (uint32_t)0x00000000U; - EXTI_EVEN = (uint32_t)0x00000000U; - EXTI_RTEN = (uint32_t)0x00000000U; - EXTI_FTEN = (uint32_t)0x00000000U; - EXTI_SWIEV = (uint32_t)0x00000000U; -} - -/*! - \brief initialize the EXTI - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling trigger - \arg EXTI_TRIG_BOTH: rising and falling trigger - \param[out] none - \retval none -*/ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t)linex; - EXTI_EVEN &= ~(uint32_t)linex; - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch (mode) { - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t)linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t)linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch (trig_type) { - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t)linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - -/*! - \brief disable the interrupt from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t)linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t)linex; -} - -/*! - \brief get EXTI lines flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if (RESET != (EXTI_PD & (uint32_t)linex)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI lines interrupt flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if ((RESET != flag_left) && (RESET != flag_right)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief enable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t)linex; -} - -/*! - \brief disable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t)linex; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_fmc.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_fmc.c deleted file mode 100644 index 7b8501515fd..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_fmc.c +++ /dev/null @@ -1,865 +0,0 @@ -/*! - \file gd32e10x_fmc.c - \brief FMC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_fmc.h" - -/* FMC register bit offset */ -#define OB_WP1_WP1_OFFSET ((uint32_t)8U) -#define OB_WP2_WP2_OFFSET ((uint32_t)16U) -#define OB_WP3_WP3_OFFSET ((uint32_t)24U) -#define FMC_OBSTAT_USER_OFFSET ((uint32_t)2U) -#define FMC_OBSTAT_DATA_OFFSET ((uint32_t)10U) - -/* return the FMC state */ -static fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ -static fmc_state_enum fmc_ready_wait(uint32_t timeout); - -/*! - \brief set the wait state counter value - \param[in] wscnt:wait state counter value - only one parameter can be selected which is shown as below: - \arg FMC_WAIT_STATE_0: FMC 0 wait - \arg FMC_WAIT_STATE_1: FMC 1 wait - \arg FMC_WAIT_STATE_2: FMC 2 wait - \arg FMC_WAIT_STATE_3: FMC 3 wait - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint32_t wscnt) -{ - uint32_t ws; - - ws = FMC_WS; - /* set the wait state counter value */ - ws &= ~FMC_WS_WSCNT; - FMC_WS = (ws | wscnt); -} - -/*! - \brief enable pre-fetch - \param[in] none - \param[out] none - \retval none -*/ -void fmc_prefetch_enable(void) -{ - FMC_WS |= FMC_WS_PFEN; -} - -/*! - \brief disable pre-fetch - \param[in] none - \param[out] none - \retval none -*/ -void fmc_prefetch_disable(void) -{ - FMC_WS &= ~FMC_WS_PFEN; -} - -/*! - \brief enable IBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_ibus_enable(void) -{ - FMC_WS |= FMC_WS_ICEN; -} - -/*! - \brief disable IBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_ibus_disable(void) -{ - FMC_WS &= ~FMC_WS_ICEN; -} - -/*! - \brief enable DBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_dbus_enable(void) -{ - FMC_WS |= FMC_WS_DCEN; -} - -/*! - \brief disable DBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_dbus_disable(void) -{ - FMC_WS &= ~FMC_WS_DCEN; -} - -/*! - \brief reset IBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_ibus_reset(void) -{ - FMC_WS |= FMC_WS_ICRST; -} - -/*! - \brief reset DBUS cache - \param[in] none - \param[out] none - \retval none -*/ -void fmc_dbus_reset(void) -{ - FMC_WS |= FMC_WS_DCRST; -} - -/*! - \brief set program width to flash memory - \param[in] pgw - only one parameter can be selected which is shown as below: - \arg FMC_PROG_W_32B: 32-bit program width to flash memory - \arg FMC_PROG_W_64B: 64-bit program width to flash memory - \param[out] none - \retval none -*/ -void fmc_program_width_set(uint32_t pgw) -{ - uint32_t ws = 0U; - - /* configure program width to flash memory */ - ws = FMC_WS; - ws &= ~FMC_WS_PGW; - ws |= pgw; - FMC_WS = ws; -} - -/*! - \brief unlock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if (RESET != (FMC_CTL & FMC_CTL_LK)) { - /* write the FMC unlock key */ - FMC_KEY = UNLOCK_KEY0; - FMC_KEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit */ - FMC_CTL |= FMC_CTL_LK; -} - -/*! - \brief erase page - \param[in] page_address: the page address to be erased - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state; - - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if (FMC_READY == fmc_state) { - FMC_CTL |= FMC_CTL_PER; - FMC_ADDR = page_address; - FMC_CTL |= FMC_CTL_START; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL &= ~FMC_CTL_PER; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase whole chip - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if (FMC_READY == fmc_state) { - /* start whole chip erase */ - FMC_CTL |= FMC_CTL_MER; - FMC_CTL |= FMC_CTL_START; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL &= ~FMC_CTL_MER; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a double word at the corresponding address - \param[in] address: address to program - \param[in] data: double word to program - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_READY == fmc_state) { - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - *(__IO uint64_t *)(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_READY == fmc_state) { - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a half word at the corresponding address - \param[in] address: address to program - \param[in] data: halfword to program - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_READY == fmc_state) { - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option bytes operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if (RESET == (FMC_CTL & FMC_CTL_OBWEN)) { - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the option bytes operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OBWEN bit */ - FMC_CTL &= ~FMC_CTL_OBWEN; -} - -/*! - \brief erase the FMC option bytes - unlock the FMC_CTL and option bytes before calling this function - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_erase(void) -{ - uint16_t temp_spc = FMC_NSPC; - uint32_t temp; - - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* check the option bytes security protection value */ - if (RESET != ob_security_protection_flag_get()) { - temp_spc = FMC_USPC; - } - - if (FMC_READY == fmc_state) { - - /* start erase the option bytes */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_READY == fmc_state) { - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - temp = ((uint32_t)temp_spc) | 0xffff0000; - /* no security protection */ - OB_SPC = temp; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if (FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } else { - if (FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected - one or more parameters can be selected which are shown as below: - \arg OB_WP_ALL: write protect all sector - \arg OB_WPx(x=0..31): write protect specify sector - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) -{ - uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; - uint32_t temp1, temp2; - - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - ob_wp = (uint32_t)(~ob_wp); - temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); - temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> OB_WP1_WP1_OFFSET); - temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> OB_WP2_WP2_OFFSET); - temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> OB_WP3_WP3_OFFSET); - - temp1 = (((uint32_t)temp_wp1) << 16) | ((uint32_t)temp_wp0); - temp2 = (((uint32_t)temp_wp3) << 16) | ((uint32_t)temp_wp2); - - if (FMC_READY == fmc_state) { - - /* set the OBPG bit*/ - FMC_CTL |= FMC_CTL_OBPG; - - if (0xFFFFU != temp1) { - OB_WP0 = temp1; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - if (0xFFFFU != temp2) { - OB_WP2 = temp2; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - if (FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection - only one parameter can be selected which is shown as below: - \arg FMC_NSPC: no security protection - \arg FMC_USPC: under security protection - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc) -{ - uint16_t temp_spc; - uint32_t temp; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_READY == fmc_state) { - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_READY == fmc_state) { - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* start the option bytes program */ - FMC_CTL |= FMC_CTL_OBPG; - temp_spc = (uint16_t)ob_spc; - temp = ((uint32_t)temp_spc) | 0xffff0000; - /* config security protection */ - OB_SPC = temp; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } else { - if (FMC_TOERR != fmc_state) { - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC user option bytes - \param[in] ob_fwdgt: option bytes free watchdog value - only one parameter can be selected which is shown as below: - \arg OB_FWDGT_SOFTWARE: software free watchdog - \arg OB_FWDGT_HARDWARE: hardware free watchdog - \param[in] ob_deepsleep: option bytes deepsleep reset value - only one parameter can be selected which is shown as below: - \arg OB_DEEPSLEEP_NO_RST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode - \param[in] ob_stdby:option bytes standby reset value - only one parameter can be selected which is shown as below: - \arg OB_STDBY_NO_RST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby) -{ - fmc_state_enum fmc_state = FMC_READY; - uint8_t temp; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_READY == fmc_state) { - /* set the OBPG bit*/ - FMC_CTL |= FMC_CTL_OBPG; - - temp = ((uint8_t)((uint8_t)((uint8_t)(ob_fwdgt) | ob_deepsleep) | ob_stdby) | (OB_USER_MASK)); - OB_USER = temp; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program option bytes data - \param[in] address: the option bytes address to be programmed - \param[in] data: the byte to be programmed - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error -*/ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_READY == fmc_state) { - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - REG16(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get the FMC user option bytes - \param[in] none - \param[out] none - \retval the FMC user option bytes values -*/ -uint8_t ob_user_get(void) -{ - /* return the FMC user option bytes value */ - return (uint8_t)(FMC_OBSTAT >> FMC_OBSTAT_USER_OFFSET); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data -*/ -uint16_t ob_data_get(void) -{ - return (uint16_t)(FMC_OBSTAT >> FMC_OBSTAT_DATA_OFFSET); -} - -/*! - \brief get the FMC option bytes write protection - \param[in] none - \param[out] none - \retval the FMC write protection option bytes value -*/ -uint32_t ob_write_protection_get(void) -{ - /* return the FMC write protection option bytes value */ - return FMC_WP; -} - -/*! - \brief get the FMC option bytes security protection - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ob_security_protection_flag_get(void) -{ - FlagStatus spc_state = RESET; - - if (RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)) { - spc_state = SET; - } else { - spc_state = RESET; - } - return spc_state; -} - -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_BANK_END: enable FMC end of program interrupt - \arg FMC_INT_BANK_ERR: enable FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: enable FMC end of program interrupt - \arg FMC_INT_ERR: enable FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief check flag is set or not - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BUSY: FMC busy flag bit - \arg FMC_FLAG_PGERR: FMC operation error flag bit - \arg FMC_FLAG_PGAERR: FMC program alignment error flag bit - \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t flag) -{ - if (RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the FMC flag - \param[in] flag: clear FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_PGERR: FMC operation error flag bit - \arg FMC_FLAG_PGAERR: FMC program alignment error flag bit - \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t flag) -{ - FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); -} - -/*! - \brief get FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit - \arg FMC_FLAG_PGAERR: FMC program alignment error flag bit - \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - if (FMC_STAT_REG_OFFSET == FMC_REG_OFFSET_GET(flag)) { - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL & BIT(FMC_BIT_POS1(flag))); - } - - if (ret1 && ret2) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit - \arg FMC_FLAG_PGAERR: FMC program alignment error flag bit - \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag bit - \param[out] none - \retval none -*/ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) -{ - FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); -} - -/*! - \brief get the FMC state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -static fmc_state_enum fmc_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if ((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)) { - fmc_state = FMC_BUSY; - } else { - if ((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)) { - fmc_state = FMC_WPERR; - } else { - if ((uint32_t)0x00U != (FMC_STAT & (FMC_STAT_PGERR))) { - fmc_state = FMC_PGERR; - } else { - if ((uint32_t)0x00U != (FMC_STAT & (FMC_STAT_PGAERR))) { - fmc_state = FMC_PGAERR; - } - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -static fmc_state_enum fmc_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do { - /* get FMC state */ - fmc_state = fmc_state_get(); - timeout--; - } while ((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if (FMC_BUSY == fmc_state) { - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_fwdgt.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_fwdgt.c deleted file mode 100644 index b062532c88d..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_fwdgt.c +++ /dev/null @@ -1,158 +0,0 @@ -/*! - \file gd32e10x_fwdgt.c - \brief FWDGT driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_fwdgt.h" - -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_enable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; -} - -/*! - \brief disable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the PUD flag to be reset */ - do { - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - } while ((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status) { - return ERROR; - } - - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do { - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - } while ((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status) { - return ERROR; - } - - FWDGT_RLD = RLD_RLD(reload_value); - - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - only one parameter can be selected which is shown as below: - \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if (RESET != (FWDGT_STAT & flag)) { - return SET; - } - - return RESET; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_gpio.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_gpio.c deleted file mode 100644 index 61ec2277ef8..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_gpio.c +++ /dev/null @@ -1,547 +0,0 @@ -/*! - \file gd32e10x_gpio.c - \brief GPIO driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_gpio.h" - -#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ -#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ -#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ -#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ -#define PCF_SWJCFG_MASK ((uint32_t)0xF8FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ -#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ -#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ -#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ -#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/ - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch (gpio_periph) { - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOD: - /* reset GPIOD */ - rcu_periph_reset_enable(RCU_GPIODRST); - rcu_periph_reset_disable(RCU_GPIODRST); - break; - case GPIOE: - /* reset GPIOE */ - rcu_periph_reset_enable(RCU_GPIOERST); - rcu_periph_reset_disable(RCU_GPIOERST); - break; - default: - break; - } -} - -/*! - \brief reset alternate function I/O(AFIO) - \param[in] none - \param[out] none - \retval none -*/ -void gpio_afio_deinit(void) -{ - rcu_periph_reset_enable(RCU_AFRST); - rcu_periph_reset_disable(RCU_AFRST); -} - -/*! - \brief GPIO parameter initialization - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] mode: gpio pin mode - only one parameter can be selected which is shown as below: - \arg GPIO_MODE_AIN: analog input mode - \arg GPIO_MODE_IN_FLOATING: floating input mode - \arg GPIO_MODE_IPD: pull-down input mode - \arg GPIO_MODE_IPU: pull-up input mode - \arg GPIO_MODE_OUT_OD: GPIO output with open-drain - \arg GPIO_MODE_OUT_PP: GPIO output with push-pull - \arg GPIO_MODE_AF_OD: AFIO output with open-drain - \arg GPIO_MODE_AF_PP: AFIO output with push-pull - \param[in] speed: gpio output max speed value - only one parameter can be selected which is shown as below: - \arg GPIO_OSPEED_10MHZ: output max speed 10MHz - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \arg GPIO_OSPEED_MAX: output max speed more than 50MHz - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -#ifdef GD_MBED_USED -void gpio_para_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) -#else -void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) -#endif -{ - uint16_t i; - uint32_t temp_mode = 0U; - uint32_t reg = 0U; - - /* GPIO mode configuration */ - temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); - - /* GPIO speed configuration */ - if (((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))) { - /* output mode max speed */ - if (GPIO_OSPEED_MAX == (uint32_t)speed) { - temp_mode |= (uint32_t)0x03U; - /* set the corresponding SPD bit */ - GPIOx_SPD(gpio_periph) |= (uint32_t)pin ; - } else { - /* output mode max speed:10MHz,2MHz,50MHz */ - temp_mode |= (uint32_t)speed; - } - } - - /* configure the eight low port pins with GPIO_CTL0 */ - for (i = 0U; i < 8U; i++) { - if ((1U << i) & pin) { - reg = GPIO_CTL0(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i, temp_mode); - - /* set IPD or IPU */ - if (GPIO_MODE_IPD == mode) { - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - } else { - /* set the corresponding OCTL bit */ - if (GPIO_MODE_IPU == mode) { - GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); - } - } - /* set GPIO_CTL0 register */ - GPIO_CTL0(gpio_periph) = reg; - } - } - /* configure the eight high port pins with GPIO_CTL1 */ - for (i = 8U; i < 16U; i++) { - if ((1U << i) & pin) { - reg = GPIO_CTL1(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i - 8U); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i - 8U, temp_mode); - - /* set IPD or IPU */ - if (GPIO_MODE_IPD == mode) { - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - } else { - /* set the corresponding OCTL bit */ - if (GPIO_MODE_IPU == mode) { - GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); - } - } - /* set GPIO_CTL1 register */ - GPIO_CTL1(gpio_periph) = reg; - } - } -} - -/*! - \brief set GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief reset GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) -{ - if (RESET != bit_value) { - GPIO_BOP(gpio_periph) = (uint32_t)pin; - } else { - GPIO_BC(gpio_periph) = (uint32_t)pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] data: specify the value to be written to the port output data register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph, uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t)data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval input status of gpio pin: SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if ((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief get GPIO port input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[out] none - \retval input status of gpio all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return (uint16_t)(GPIO_ISTAT(gpio_periph)); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval output status of gpio pin: SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if ((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief get GPIO port output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[out] none - \retval output status of gpio all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return ((uint16_t)GPIO_OCTL(gpio_periph)); -} - -/*! - \brief configure GPIO pin remap - \param[in] gpio_remap: select the pin to remap - only one parameter can be selected which are shown as below: - \arg GPIO_SPI0_REMAP: SPI0 remapping - \arg GPIO_I2C0_REMAP: I2C0 remapping - \arg GPIO_USART0_REMAP: USART0 remapping - \arg GPIO_USART1_REMAP: USART1 remapping - \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping - \arg GPIO_USART2_FULL_REMAP: USART2 full remapping - \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping - \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping - \arg GPIO_TIMER1_PARTIAL_REMAP0: TIMER1 partial remapping - \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping - \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping - \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping - \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping - \arg GPIO_TIMER3_REMAP: TIMER3 remapping - \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping - \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping - \arg GPIO_PD01_REMAP: PD01 remapping - \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping - \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping - \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping - \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping - \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping - \arg GPIO_CAN1_REMAP: CAN1 remapping - \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST - \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled - \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled - \arg GPIO_SPI2_REMAP: SPI2 remapping - \arg GPIO_TIMER1ITR0_REMAP: TIMER1 internal trigger 0 remapping - \arg GPIO_TIMER8_REMAP: TIMER8 remapping - \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect - \arg GPIO_CTC_REMAP0: CTC remapping(PD15) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) -{ - uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; - - if (((uint32_t)0x80000000U) == (remap & 0x80000000U)) { - /* get AFIO_PCF1 regiter value */ - temp_reg = AFIO_PCF1; - } else { - /* get AFIO_PCF0 regiter value */ - temp_reg = AFIO_PCF0; - } - - temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; - remap1 = remap & LSB_16BIT_MASK; - - /* judge pin remap type */ - if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) { - temp_reg &= PCF_SWJCFG_MASK; - AFIO_PCF0 &= PCF_SWJCFG_MASK; - } else if (PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)) { - remap2 = ((uint32_t)0x03U) << temp_mask; - temp_reg &= ~remap2; - temp_reg |= ~PCF_SWJCFG_MASK; - } else { - temp_reg &= ~(remap1 << ((remap >> 0x15U) * 0x10U)); - temp_reg |= ~PCF_SWJCFG_MASK; - } - - /* set pin remap value */ - if (DISABLE != newvalue) { - temp_reg |= (remap1 << ((remap >> 0x15U) * 0x10U)); - } - - if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { - /* set AFIO_PCF1 regiter value */ - AFIO_PCF1 = temp_reg; - } else { - /* set AFIO_PCF0 regiter value */ - AFIO_PCF0 = temp_reg; - } -} - -/*! - \brief select GPIO pin exti sources - \param[in] output_port: gpio event output port - only one parameter can be selected which are shown as below: - \arg GPIO_PORT_SOURCE_GPIOA: output port source A - \arg GPIO_PORT_SOURCE_GPIOB: output port source B - \arg GPIO_PORT_SOURCE_GPIOC: output port source C - \arg GPIO_PORT_SOURCE_GPIOD: output port source D - \arg GPIO_PORT_SOURCE_GPIOE: output port source E - \param[in] output_pin: - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_SOURCE_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) -{ - uint32_t source = 0U; - source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); - - /* select EXTI sources */ - if (GPIO_PIN_SOURCE_4 > output_pin) { - /* select EXTI0/EXTI1/EXTI2/EXTI3 */ - AFIO_EXTISS0 &= ~source; - AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } else if (GPIO_PIN_SOURCE_8 > output_pin) { - /* select EXTI4/EXTI5/EXTI6/EXTI7 */ - AFIO_EXTISS1 &= ~source; - AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } else if (GPIO_PIN_SOURCE_12 > output_pin) { - /* select EXTI8/EXTI9/EXTI10/EXTI11 */ - AFIO_EXTISS2 &= ~source; - AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } else { - /* select EXTI12/EXTI13/EXTI14/EXTI15 */ - AFIO_EXTISS3 &= ~source; - AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } -} - -/*! - \brief configure GPIO pin event output - \param[in] output_port: gpio event output port - only one parameter can be selected which are shown as below: - \arg GPIO_EVENT_PORT_GPIOA: event output port A - \arg GPIO_EVENT_PORT_GPIOB: event output port B - \arg GPIO_EVENT_PORT_GPIOC: event output port C - \arg GPIO_EVENT_PORT_GPIOD: event output port D - \arg GPIO_EVENT_PORT_GPIOE: event output port E - \param[in] output_pin: - only one parameter can be selected which are shown as below: - \arg GPIO_EVENT_PIN_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) -{ - uint32_t reg = 0U; - reg = AFIO_EC; - - /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ - reg &= (uint32_t)(~(AFIO_EC_PORT | AFIO_EC_PIN)); - - reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); - reg |= (uint32_t)output_pin; - - AFIO_EC = reg; -} - -/*! - \brief enable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_enable(void) -{ - AFIO_EC |= AFIO_EC_EOE; -} - -/*! - \brief disable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_disable(void) -{ - AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); -} - -/*! - \brief lock GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - GPIO_LOCK(gpio_periph) = (uint32_t)pin; - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} - -/*! - \brief configure the I/O compensation cell - \param[in] compensation: specifies the I/O compensation cell mode - only one parameter can be selected which are shown as below: - \arg GPIO_COMPENSATION_ENABLE: I/O compensation cell is enabled - \arg GPIO_COMPENSATION_DISABLE: I/O compensation cell is disabled - \param[out] none - \retval none -*/ -void gpio_compensation_config(uint32_t compensation) -{ - uint32_t reg; - reg = AFIO_CPSCTL; - - /* reset the AFIO_CPSCTL_CPS_EN bit and set according to gpio_compensation */ - reg &= ~AFIO_CPSCTL_CPS_EN; - AFIO_CPSCTL = (reg | compensation); -} - -/*! - \brief check the I/O compensation cell is ready or not - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus gpio_compensation_flag_get(void) -{ - if (((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)) { - return SET; - } else { - return RESET; - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_i2c.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_i2c.c deleted file mode 100644 index 580c14771a7..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_i2c.c +++ /dev/null @@ -1,791 +0,0 @@ -/*! - \file gd32e10x_i2c.c - \brief I2C driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_i2c.h" - -/* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ -#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ -#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ - -/* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_deinit(uint32_t i2c_periph) -{ - switch (i2c_periph) { - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - and fast mode plus (up to 1MHz) - \param[in] dutycyc: duty cycle in fast mode or fast mode plus - only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 - \param[out] none - \retval none -*/ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1, clkc, freq, risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1 / 1000000U); - if (freq >= I2CCLK_MAX) { - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if (100000U >= clkspeed) { - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1 / 1000000U) + 1U); - if (risetime >= I2CCLK_MAX) { - I2C_RT(i2c_periph) = I2CCLK_MAX; - } else if (risetime <= I2CCLK_MIN) { - I2C_RT(i2c_periph) = I2CCLK_MIN; - } else { - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); - if (clkc < 0x04U) { - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - } else if (400000U >= clkspeed) { - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); - if (I2C_DTCY_2 == dutycyc) { - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - } else { - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if (0U == (clkc & I2C_CKCFG_CLKC)) { - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - } else { - /* fast mode plus, the maximum SCL rise time is 120ns */ - I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)120U) / (uint32_t)1000U) + (uint32_t)1U); - if (I2C_DTCY_2 == dutycyc) { - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - } else { - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - /* enable fast mode */ - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - /* enable I2C fast mode plus */ - I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - addr = addr & I2C_ADDRESS_MASK; - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief SMBus type selection - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] type: - only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host - \param[out] none - \retval none -*/ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if (I2C_SMBUS_HOST == type) { - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - } else { - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - only one parameter can be selected which is shown as below: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - if (I2C_ACK_ENABLE == ack) { - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - } else { - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief configure I2C POAP position - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pos: - only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte - \param[out] none - \retval none -*/ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - /* configure I2C POAP position */ - if (I2C_ACKPOS_NEXT == pos) { - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - } else { - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } -} - -/*! - \brief master sends slave address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none -*/ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) -{ - /* master is a transmitter or a receiver */ - if (I2C_TRANSMITTER == trandirection) { - addr = addr & I2C_TRANSMITTER; - } else { - addr = addr | I2C_RECEIVER; - } - /* send slave address */ - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief dual-address mode switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dualaddr: - only one parameter can be selected which is shown as below: - \arg I2C_DUADEN_DISABLE: disable dual-address mode - \arg I2C_DUADEN_ENABLE: enable dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) -{ - if (I2C_DUADEN_ENABLE == dualaddr) { - I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; - } else { - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); - } -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval data of received -*/ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief enable I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmastate: - only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable - \param[out] none - \retval none -*/ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure whether next DMA EOT is DMA last transfer or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmalast: - only one parameter can be selected which is shown as below: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none -*/ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] stretchpara: - only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled - \param[out] none - \retval none -*/ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SS); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] gcallpara: - only one parameter can be selected which is shown as below: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none -*/ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief software reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] sreset: - only one parameter can be selected which is shown as below: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none -*/ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C PEC calculation on or off - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none -*/ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC - \param[out] none - \retval none -*/ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval PEC value -*/ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); -} - -/*! - \brief I2C issue alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none -*/ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* issue alert through SMBA pin configure*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable or disable I2C ARP protocol in SMBus switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none -*/ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable SAM_V interface - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_enable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; -} - -/*! - \brief disable SAM_V interface - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_disable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); -} - -/*! - \brief enable SAM_V interface timeout detect - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_timeout_enable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; -} - -/*! - \brief disable SAM_V interface timeout detect - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_timeout_disable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); -} - -/*! - \brief check I2C flag is set or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode - \arg I2C_FLAG_TFF: txframe fall flag - \arg I2C_FLAG_TFR: txframe rise flag - \arg I2C_FLAG_RFF: rxframe fall flag - \arg I2C_FLAG_RFR: rxframe rise flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if (RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear I2C flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \arg I2C_FLAG_TFF: txframe fall flag - \arg I2C_FLAG_TFR: txframe rise flag - \arg I2C_FLAG_RFF: rxframe fall flag - \arg I2C_FLAG_RFR: rxframe rise flag - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if (I2C_FLAG_ADDSEND == flag) { - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - } else { - I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief check I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag - \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag - \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag - \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag - \param[out] none - \retval none -*/ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U, bufie; - - /* check BUFIE */ - bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - - /* get the interrupt enable bit status */ - intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - - if ((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { - if (intenable && bufie) { - intenable = 1U; - } else { - intenable = 0U; - } - } - if ((0U != flagstatus) && (0U != intenable)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag - \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag - \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag - \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag - \param[out] none - \retval none -*/ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - if (I2C_INT_FLAG_ADDSEND == int_flag) { - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - } else { - I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_misc.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_misc.c deleted file mode 100644 index c575eaff884..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_misc.c +++ /dev/null @@ -1,186 +0,0 @@ -/*! - \file gd32e10x_misc.c - \brief MISC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_misc.h" - -/*! - \brief set the priority group - \param[in] nvic_prigroup: the NVIC priority group - \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority - \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority - \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority - \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority - \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority - \param[out] none - \retval none -*/ -void nvic_priority_group_set(uint32_t nvic_prigroup) -{ - /* set the priority group value */ - SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; -} - -/*! - \brief enable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set - \param[in] nvic_irq_sub_priority: the subpriority needed to set - \param[out] none - \retval none -*/ -void nvic_irq_enable(uint8_t nvic_irq, - uint8_t nvic_irq_pre_priority, - uint8_t nvic_irq_sub_priority) -{ - uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; - - /* use the priority group value to get the temp_pre and the temp_sub */ - switch ((SCB->AIRCR) & (uint32_t)0x700U) { - case NVIC_PRIGROUP_PRE0_SUB4: - temp_pre = 0U; - temp_sub = 0x4U; - break; - case NVIC_PRIGROUP_PRE1_SUB3: - temp_pre = 1U; - temp_sub = 0x3U; - break; - case NVIC_PRIGROUP_PRE2_SUB2: - temp_pre = 2U; - temp_sub = 0x2U; - break; - case NVIC_PRIGROUP_PRE3_SUB1: - temp_pre = 3U; - temp_sub = 0x1U; - break; - case NVIC_PRIGROUP_PRE4_SUB0: - temp_pre = 4U; - temp_sub = 0x0U; - break; - default: - nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - temp_pre = 2U; - temp_sub = 0x2U; - break; - } - - /* get the temp_priority to fill the NVIC->IP register */ - temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub)); - temp_priority = temp_priority << 0x04U; - NVIC->IP[nvic_irq] = (uint8_t)temp_priority; - - /* enable the selected IRQ */ - NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief disable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void nvic_irq_disable(uint8_t nvic_irq) -{ - /* disable the selected IRQ.*/ - NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address - \arg NVIC_VECTTAB_RAM: RAM base address - \are NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset - \param[out] none - \retval none -*/ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) -{ - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); -} - -/*! - \brief set the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up - by all the enable and disable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_set(uint8_t lowpower_mode) -{ - SCB->SCR |= (uint32_t)lowpower_mode; -} - -/*! - \brief reset the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_reset(uint8_t lowpower_mode) -{ - SCB->SCR &= (~(uint32_t)lowpower_mode); -} - -/*! - \brief set the systick clock source - \param[in] systick_clksource: the systick clock source needed to choose - \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK - \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 - \param[out] none - \retval none -*/ - -void systick_clksource_set(uint32_t systick_clksource) -{ - if (SYSTICK_CLKSOURCE_HCLK == systick_clksource) { - /* set the systick clock source from HCLK */ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } else { - /* set the systick clock source from HCLK/8 */ - SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_pmu.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_pmu.c deleted file mode 100644 index 1549b85fd25..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_pmu.c +++ /dev/null @@ -1,280 +0,0 @@ -/*! - \file gd32e10x_pmu.c - \brief PMU driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_pmu.h" - -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - only one parameter can be selected which is shown as below: - \arg PMU_LVDT_0: voltage threshold is 2.1V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.6V - \arg PMU_LVDT_4: voltage threshold is 2.7V - \arg PMU_LVDT_5: voltage threshold is 2.9V - \arg PMU_LVDT_6: voltage threshold is 3.0V - \arg PMU_LVDT_7: voltage threshold is 3.1V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief select LDO output voltage - this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL - \param[in] ldo_output: - only one parameter can be selected which is shown as below: - \arg PMU_LDOVS_LOW: LDO output voltage select low mode - \arg PMU_LDOVS_NORMAL: LDO output voltage select normal mode - \param[out] none - \retval none -*/ -void pmu_ldo_output_select(uint32_t ldo_output) -{ - PMU_CTL &= ~PMU_CTL_LDOVS; - PMU_CTL |= ldo_output; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* select WFI or WFE command to enter sleep mode */ - if (WFI_CMD == sleepmodecmd) { - __WFI(); - } else { - __WFE(); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo: - only one parameter can be selected which is shown as below: - \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd) -{ - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* select WFI or WFE command to enter deepsleep mode */ - if (WFI_CMD == deepsleepmodecmd) { - __WFI(); - } else { - __SEV(); - __WFE(); - __WFE(); - } - /* reset sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_standbymode(uint8_t standbymodecmd) -{ - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if (WFI_CMD == standbymodecmd) { - __WFI(); - } else { - __WFE(); - } -} - -/*! - \brief enable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(void) -{ - PMU_CS |= PMU_CS_WUPEN; -} - -/*! - \brief disable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(void) -{ - PMU_CS &= ~PMU_CS_WUPEN; -} - -/*! - \brief enable write access to the registers in backup domain - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable write access to the registers in backup domain - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief clear flag bit - \param[in] flag_reset: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_clear(uint32_t flag_reset) -{ - switch (flag_reset) { - case PMU_FLAG_RESET_WAKEUP: - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - break; - case PMU_FLAG_RESET_STANDBY: - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - break; - default: - break; - } -} - -/*! - \brief get flag state - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t flag) -{ - if (RESET != (PMU_CS & flag)) { - return SET; - } else { - return RESET; - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_rcu.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_rcu.c deleted file mode 100644 index d8bb5bcfdeb..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_rcu.c +++ /dev/null @@ -1,1248 +0,0 @@ -/*! - \file gd32e10x_rcu.c - \brief RCU driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_rcu.h" - -/* define clock source */ -#define SEL_IRC8M ((uint16_t)0U) /* IRC8M is selected as CK_SYS */ -#define SEL_HXTAL ((uint16_t)1U) /* HXTAL is selected as CK_SYS */ -#define SEL_PLL ((uint16_t)2U) /* PLL is selected as CK_SYS */ - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU) - -/* ADC clock prescaler offset */ -#define RCU_ADC_PSC_OFFSET ((uint32_t)14U) - -/* RCU IRC8M adjust value mask and offset*/ -#define RCU_IRC8M_ADJUST_MASK ((uint8_t)0x1FU) -#define RCU_IRC8M_ADJUST_OFFSET ((uint32_t)3U) - -/* RCU PLL1 clock multiplication factor offset */ -#define RCU_CFG1_PLL1MF_OFFSET ((uint32_t)8U) -/* RCU PREDV1 division factor offset*/ -#define RCU_CFG1_PREDV1_OFFSET ((uint32_t)4U) - - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - rcu_osci_stab_wait(RCU_IRC8M); - - /* reset CFG0 register */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4 | RCU_CFG0_USBFSPSC_2); - /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - RCU_CTL &= ~RCU_CTL_HXTALBPS; - RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); - - /* reset INT and CFG1 register */ - - RCU_INT = 0x00ff0000U; - RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | - RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL | RCU_CFG1_ADCPSC_3 | - RCU_CFG1_PLLPRESEL); -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock - \arg RCU_AF : alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_USBFS: USBFS clock - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1): ADC clock - \arg RCU_CTC: CTC clock - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock - \arg RCU_AF: alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_USBFS: USBFS clock - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1): ADC clock - \arg RCU_CTC: CTC clock - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_USBFSRST: reset USBFS - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCxRST (x=0,1): reset ADC - \arg RCU_CTCRST: reset CTC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_USBFSRST: reset USBFS - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCxRST (x=0,1): reset ADC - \arg RCU_CTCRST: reset CTC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP domain - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP domain reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - reg &= ~RCU_CFG0_SCS; - RCU_CFG0 = (reg | ck_sys); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source - \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source - \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the AHBPSC bits and set according to ck_ahb */ - reg &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (reg | ck_ahb); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB1PSC and set according to ck_apb1 */ - reg &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (reg | ck_apb1); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB2PSC and set according to ck_apb2 */ - reg &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (reg | ck_apb2); -} - -/*! - \brief configure the CK_OUT0 clock source - \param[in] ckout0_src: CK_OUT0 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUT0SRC_NONE: no clock selected - \arg RCU_CKOUT0SRC_CKSYS: system clock selected - \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected - \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected - \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected - \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected - \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected - \arg RCU_CKOUT0SRC_IRC48M: IRC48M selected - \arg RCU_CKOUT0SRC_IRC48M_DIV8: IRC48M/8 selected - \param[out] none - \retval none -*/ -void rcu_ckout0_config(uint32_t ckout0_src) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the CKOUT0SRC, set according to ckout0_src */ - reg &= ~RCU_CFG0_CKOUT0SEL; - RCU_CFG0 = (reg | ckout0_src); -} - -/*! - \brief configure the main PLL clock - \param[in] pll_src: PLL clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL - \arg RCU_PLLSRC_HXTAL_IRC48M: HXTAL or IRC48M selected as source clock of PLL - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL_MULx (x = 2..14, 16..31, 6.5) - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - - /* PLL clock source and multiplication factor configuration */ - reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - reg |= (pll_src | pll_mul); - - RCU_CFG0 = reg; -} - -/*! - \brief configure the PLL clock source preselection - \param[in] pll_presel: PLL clock source preselection - only one parameter can be selected which is shown as below: - \arg RCU_PLLPRESRC_HXTAL: HXTAL selected as PLL source clock - \arg RCU_PLLPRESRC_IRC48M: CK_PLL selected as PREDV0 input source clock - \param[out] none - \retval none -*/ -void rcu_pllpresel_config(uint32_t pll_presel) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - - /* PLL clock source preselection */ - reg &= ~RCU_CFG1_PLLPRESEL; - reg |= pll_presel; - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PREDV0 division factor and clock source - \param[in] predv0_source: PREDV0 input clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0SRC_HXTAL_IRC48M: HXTAL or IRC48M selected as PREDV0 input source clock - \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock - \param[in] predv0_div: PREDV0 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset PREDV0SEL and PREDV0 bits */ - reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); - /* set the PREDV0SEL and PREDV0 division factor */ - reg |= (predv0_source | predv0_div); - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PREDV1 division factor - \param[in] predv1_div: PREDV1 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV1_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv1_config(uint32_t predv1_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset the PREDV1 bits */ - reg &= ~RCU_CFG1_PREDV1; - /* set the PREDV1 division factor */ - reg |= predv1_div; - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PLL1 clock - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL1_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll1_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL1MF; - RCU_CFG1 |= pll_mul; -} - -/*! - \brief configure the PLL2 clock - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL2_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll2_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL2MF; - RCU_CFG1 |= pll_mul; -} - -/*! - \brief configure the ADC prescaler factor - \param[in] adc_psc: ADC prescaler factor - only one parameter can be selected which is shown as below: - \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 - \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 - \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 - \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 - \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 - \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 - \arg RCU_CKADC_CKAHB_DIV3: ADC prescaler select CK_AHB/3 - \arg RCU_CKADC_CKAHB_DIV5: ADC prescaler select CK_AHB/5 - \arg RCU_CKADC_CKAHB_DIV7: ADC prescaler select CK_AHB/7 - \arg RCU_CKADC_CKAHB_DIV9: ADC prescaler select CK_AHB/9 - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(uint32_t adc_psc) -{ - uint32_t reg0, reg1; - - /* reset the ADCPSC bits */ - reg0 = RCU_CFG0; - reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); - reg1 = RCU_CFG1; - reg1 &= ~RCU_CFG1_ADCPSC_3; - - /* set the ADC prescaler factor */ - switch (adc_psc) { - case RCU_CKADC_CKAPB2_DIV2: - case RCU_CKADC_CKAPB2_DIV4: - case RCU_CKADC_CKAPB2_DIV6: - case RCU_CKADC_CKAPB2_DIV8: - reg0 |= (adc_psc << RCU_ADC_PSC_OFFSET); - break; - - case RCU_CKADC_CKAPB2_DIV12: - case RCU_CKADC_CKAPB2_DIV16: - adc_psc &= ~BIT(2); - reg0 |= ((adc_psc << RCU_ADC_PSC_OFFSET) | RCU_CFG0_ADCPSC_2); - break; - - case RCU_CKADC_CKAHB_DIV3: - case RCU_CKADC_CKAHB_DIV5: - case RCU_CKADC_CKAHB_DIV7: - case RCU_CKADC_CKAHB_DIV9: - adc_psc &= ~BITS(2, 3); - reg0 |= (adc_psc << RCU_ADC_PSC_OFFSET); - reg1 |= RCU_CFG1_ADCPSC_3; - break; - - default: - break; - } - - /* set the register */ - RCU_CFG0 = reg0; - RCU_CFG1 = reg1; -} - -/*! - \brief configure the USBFS prescaler factor - \param[in] adc_div: USB prescaler factor - only one parameter can be selected which is shown as below: - \arg RCU_CKUSB_CKPLL_DIV1_5: USBFS prescaler select CK_PLL/1.5 - \arg RCU_CKUSB_CKPLL_DIV1: USBFS prescaler select CK_PLL/1 - \arg RCU_CKUSB_CKPLL_DIV2_5: USBFS prescaler select CK_PLL/2.5 - \arg RCU_CKUSB_CKPLL_DIV2: USBFS prescaler select CK_PLL/2 - \arg RCU_CKUSB_CKPLL_DIV3: USBFS prescaler select CK_PLL/3 - \arg RCU_CKUSB_CKPLL_DIV3_5: USBFS prescaler select CK_PLL/3.5 - \arg RCU_CKUSB_CKPLL_DIV4: USBFS prescaler select CK_PLL/4 - \param[out] none - \retval none -*/ -void rcu_usb_clock_config(uint32_t usb_psc) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* configure the USBFS prescaler factor */ - reg &= ~RCU_CFG0_USBFSPSC; - - RCU_CFG0 = (reg | usb_psc); -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - uint32_t reg; - - reg = RCU_BDCTL; - /* reset the RTCSRC bits and set according to rtc_clock_source */ - reg &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL = (reg | rtc_clock_source); -} - -/*! - \brief configure the I2S1 clock source selection - \param[in] i2s_clock_source: I2S1 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S1SRC_CKSYS: system clock selected as I2S1 source clock - \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock - \param[out] none - \retval none -*/ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S1SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S1SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} - -/*! - \brief configure the I2S2 clock source selection - \param[in] i2s_clock_source: I2S2 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock - \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock - \param[out] none - \retval none -*/ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S2SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S2SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} - -/*! - \brief configure the CK48M clock source selection - \param[in] ck48m_clock_source: CK48M clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CK48MSRC_CKPLL: CK_PLL selected as CK48M source clock - \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock - \param[out] none - \retval none -*/ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) -{ - uint32_t reg; - - reg = RCU_ADDCTL; - /* reset the CK48MSEL bit and set according to ck48m_clock_source */ - reg &= ~RCU_ADDCTL_CK48MSEL; - RCU_ADDCTL = (reg | ck48m_clock_source); -} - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag - \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval none -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if (RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag - \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if (RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief configure the LXTAL drive capability - \param[in] lxtal_dricap: drive capability of LXTAL - only one parameter can be selected which is shown as below: - \arg RCU_LXTAL_LOWDRI: lower driving capability - \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability - \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability - \arg RCU_LXTAL_HIGHDRI: higher driving capability - \param[out] none - \retval none -*/ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) -{ - uint32_t reg; - - reg = RCU_BDCTL; - - /* reset the LXTALDRI bits and set according to lxtal_dricap */ - reg &= ~RCU_BDCTL_LXTALDRI; - RCU_BDCTL = (reg | lxtal_dricap); -} - -/*! - \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1 - \arg RCU_PLL2_CK: phase locked loop 2 - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - - switch (osci) { - /* wait HXTAL stable */ - case RCU_HXTAL: - while ((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { - reval = SUCCESS; - } - break; - - /* wait LXTAL stable */ - case RCU_LXTAL: - while ((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while ((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC48M stable */ - case RCU_IRC48M: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { - reval = SUCCESS; - } - break; - - /* wait PLL1 stable */ - case RCU_PLL1_CK: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) { - reval = SUCCESS; - } - break; - /* wait PLL2 stable */ - case RCU_PLL2_CK: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) { - reval = SUCCESS; - } - break; - - default: - break; - } - - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1 - \arg RCU_PLL2_CK: phase locked loop 2 - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1 - \arg RCU_PLL2_CK: phase locked loop 2 - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch (osci) { - /* enable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg | RCU_CTL_HXTALBPS); - break; - /* enable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC48M: - case RCU_IRC40K: - case RCU_PLL_CK: - case RCU_PLL1_CK: - case RCU_PLL2_CK: - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch (osci) { - /* disable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); - break; - /* disable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC48M: - case RCU_IRC40K: - case RCU_PLL_CK: - case RCU_PLL1_CK: - case RCU_PLL2_CK: - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \arg 0x00 - 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) -{ - uint32_t reg; - - reg = RCU_CTL; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - reg &= ~RCU_CTL_IRC8MADJ; - RCU_CTL = (reg | ((irc8m_adjval & RCU_IRC8M_ADJUST_MASK) << RCU_IRC8M_ADJUST_OFFSET)); -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws, ck_freq = 0U; - uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; - uint32_t pllsel, pllpresel, predv0sel, pllmf, ck_src, idx, clk_exp; - uint32_t predv0, predv1, pll1mf; - - /* exponent of AHB, APB1 and APB2 clock divider */ - uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch (sws) { - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) { - /* PLL clock source is HXTAL or IRC48M */ - pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); - - if (RCU_PLLPRESRC_HXTAL == pllpresel) { - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - } else { - /* PLL clock source is IRC48 */ - ck_src = IRC48M_VALUE; - } - - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - /* source clock use PLL1 */ - if (RCU_PREDV0SRC_CKPLL1 == predv0sel) { - predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> RCU_CFG1_PREDV1_OFFSET) + 1U; - pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> RCU_CFG1_PLL1MF_OFFSET) + 2U; - if (17U == pll1mf) { - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; - } else { - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE / 2U; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { - pllmf |= 0x10U; - } - if (pllmf < 15U) { - pllmf += 2U; - } else { - pllmf += 1U; - } - cksys_freq = ck_src * pllmf; - if (15U == pllmf) { - cksys_freq = ck_src * 6U + ck_src / 2U; - } - - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch (clock) { - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_rtc.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_rtc.c deleted file mode 100644 index d3a66310e21..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_rtc.c +++ /dev/null @@ -1,276 +0,0 @@ -/*! - \file gd32e10x_rtc.c - \brief RTC driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_rtc.h" - -/* RTC register high / low bits mask */ -#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */ -#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */ - -/* RTC register high bits offset */ -#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U) - -/*! - \brief enter RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_enter(void) -{ - RTC_CTL |= RTC_CTL_CMF; -} - -/*! - \brief exit RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_exit(void) -{ - RTC_CTL &= ~RTC_CTL_CMF; -} - -/*! - \brief set RTC counter value - \param[in] cnt: RTC counter value - \param[out] none - \retval none -*/ -void rtc_counter_set(uint32_t cnt) -{ - rtc_configuration_mode_enter(); - /* set the RTC counter high bits */ - RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET); - /* set the RTC counter low bits */ - RTC_CNTL = (cnt & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief set RTC prescaler value - \param[in] psc: RTC prescaler value - \param[out] none - \retval none -*/ -void rtc_prescaler_set(uint32_t psc) -{ - rtc_configuration_mode_enter(); - /* set the RTC prescaler high bits */ - RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET); - /* set the RTC prescaler low bits */ - RTC_PSCL = (psc & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief wait RTC last write operation finished flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_lwoff_wait(void) -{ - /* loop until LWOFF flag is set */ - while (RESET == (RTC_CTL & RTC_CTL_LWOFF)) { - } -} - -/*! - \brief wait RTC registers synchronized flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_register_sync_wait(void) -{ - /* clear RSYNF flag */ - RTC_CTL &= ~RTC_CTL_RSYNF; - /* loop until RSYNF flag is set */ - while (RESET == (RTC_CTL & RTC_CTL_RSYNF)) { - } -} - -/*! - \brief set RTC alarm value - \param[in] alarm: RTC alarm value - \param[out] none - \retval none -*/ -void rtc_alarm_config(uint32_t alarm) -{ - rtc_configuration_mode_enter(); - /* set the alarm high bits */ - RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET); - /* set the alarm low bits */ - RTC_ALRML = (alarm & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief get RTC counter value - \param[in] none - \param[out] none - \retval RTC counter value -*/ -uint32_t rtc_counter_get(void) -{ - uint32_t temp = 0x0U; - - temp = RTC_CNTL; - temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); - return temp; -} - -/*! - \brief get RTC divider value - \param[in] none - \param[out] none - \retval RTC divider value -*/ -uint32_t rtc_divider_get(void) -{ - uint32_t temp = 0x00U; - - temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); - temp |= RTC_DIVL; - return temp; -} - -/*! - \brief get RTC flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \arg RTC_FLAG_LWOF: last write operation finished flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - if (RESET != (RTC_CTL & flag)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear RTC flag status - \param[in] flag: specify which flag status to clear - one or more parameters can be selected which are shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - /* clear RTC flag */ - RTC_CTL &= ~flag; -} - -/*! - \brief get RTC interrupt flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_interrupt_flag_get(uint32_t flag) -{ - if (RESET != (RTC_CTL & flag)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear RTC interrupt flag status - \param[in] flag: specify which flag status to clear - one or more parameters can be selected which are shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag - \param[out] none - \retval none -*/ -void rtc_interrupt_flag_clear(uint32_t flag) -{ - /* clear RTC interrupt flag */ - RTC_CTL &= ~flag; -} - -/*! - \brief enable RTC interrupt - \param[in] interrupt: specify which interrupt to enbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - RTC_INTEN |= interrupt; -} - -/*! - \brief disable RTC interrupt - \param[in] interrupt: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - RTC_INTEN &= ~interrupt; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_spi.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_spi.c deleted file mode 100644 index 963526f71c8..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_spi.c +++ /dev/null @@ -1,843 +0,0 @@ -/*! - \file gd32e10x_spi.c - \brief SPI driver - - \version 2017-12-26, V1.0.1, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_spi.h" - -/* SPI/I2S parameter initialization mask */ -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ - -/* I2S clock source selection, multiplication and division mask */ -#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ -#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ -#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ -#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ - -/* default value and offset */ -#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /* default value of SPI_I2SPSC register */ -#define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ -#define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ - -/*! - \brief reset SPI and I2S - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch (spi_periph) { - case SPI0: - /* reset SPI0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1 and I2S1 */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - case SPI2: - /* reset SPI2 and I2S2 */ - rcu_periph_reset_enable(RCU_SPI2RST); - rcu_periph_reset_disable(RCU_SPI2RST); - break; - default: - break; - } -} - -/*! - \brief initialize the parameters of SPI struct with the default values - \param[in] spi_struct: SPI parameter stuct - \param[out] none - \retval none -*/ -void spi_struct_para_init(spi_parameter_struct *spi_struct) -{ - /* set the SPI struct with the default values */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; - spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; -} - -/*! - \brief initialize SPI parameter - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval none -*/ -#ifdef GD_MBED_USED -void spi_para_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) -#else -void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) -#endif -{ - uint32_t reg = 0U; - reg = SPI_CTL0(spi_periph); - reg &= SPI_INIT_MASK; - - /* select SPI as master or slave */ - reg |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg |= spi_struct->trans_mode; - /* select SPI frame size */ - reg |= spi_struct->frame_size; - /* select SPI NSS use hardware or software */ - reg |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg |= spi_struct->endian; - /* select SPI polarity and phase */ - reg |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg |= spi_struct->prescale; - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg; - - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - -/*! - \brief initialize I2S parameter - \param[in] spi_periph: SPIx(x=1,2) - \param[in] mode: I2S operation mode - only one parameter can be selected which is shown as below: - \arg I2S_MODE_SLAVETX: I2S slave transmit mode - \arg I2S_MODE_SLAVERX: I2S slave receive mode - \arg I2S_MODE_MASTERTX: I2S master transmit mode - \arg I2S_MODE_MASTERRX: I2S master receive mode - \param[in] standard: I2S standard - only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILLIPS: I2S phillips standard - \arg I2S_STD_MSB: I2S MSB standard - \arg I2S_STD_LSB: I2S LSB standard - \arg I2S_STD_PCMSHORT: I2S PCM short standard - \arg I2S_STD_PCMLONG: I2S PCM long standard - \param[in] ckpl: I2S idle state clock polarity - only one parameter can be selected which is shown as below: - \arg I2S_CKPL_LOW: I2S clock polarity low level - \arg I2S_CKPL_HIGH: I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) -{ - uint32_t reg = 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)mode; - /* select I2S standard */ - reg |= (uint32_t)standard; - /* select I2S polarity */ - reg |= (uint32_t)ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief configure I2S prescaler - \param[in] spi_periph: SPIx(x=1,2) - \param[in] audiosample: I2S audio sample rate - only one parameter can be selected which is shown as below: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] frameformat: I2S data length and channel length - only one parameter can be selected which is shown as below: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: I2S master clock output - only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - - /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; - - /* get the I2S clock source */ - if (SPI1 == ((uint32_t)spi_periph)) { - /* I2S1 clock source selection */ - clks = I2S1_CLOCK_SEL; - } else { - /* I2S2 clock source selection */ - clks = I2S2_CLOCK_SEL; - } - - if (0U != (RCU_CFG1 & clks)) { - /* get RCU PLL2 clock multiplication factor */ - clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); - - if ((clks > 5U) && (clks < 15U)) { - /* multiplier is between 8 and 16 */ - clks += 2U; - } else { - if (15U == clks) { - /* multiplier is 20 */ - clks = 20U; - } - } - - /* get the PREDV1 value */ - i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); - /* calculate I2S clock based on PLL2 and PREDV1 */ - if (0U != (RCU_CFG1_PLLPRESEL & RCU_CFG1)) { - i2sclock = (uint32_t)((IRC48M_VALUE / i2sclock) * clks * 2U); - } else { - i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); - } - } else { - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); - } - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if (I2S_MCKOUT_ENABLE == mckout) { - clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - } else { - if (I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) { - clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample); - } else { - clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample); - } - } - - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if ((i2sdiv < 2U) || (i2sdiv > 255U)) { - i2sdiv = 2U; - i2sof = 0U; - } - - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; -} - -/*! - \brief enable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -/*! - \brief enable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI NSS pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI NSS pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma) -{ - if (SPI_DMA_TRANSMIT == dma) { - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - } else { - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief disable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma) -{ - if (SPI_DMA_TRANSMIT == dma) { - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - } else { - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI/I2S data frame format - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] frame_format: SPI frame size - only one parameter can be selected which is shown as below: - \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits - \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits - \param[out] none - \retval none -*/ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* configure SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= (uint32_t)frame_format; -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - SPI_DATA(spi_periph) = (uint32_t)data; -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - return ((uint16_t)SPI_DATA(spi_periph)); -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \param[out] none - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if (SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { - /* set the transmit-only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - } else { - /* set the receive-only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief set SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc: SPI crc value - only one parameter can be selected which is shown as below: - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) -{ - if (SPI_CRC_TX == crc) { - return ((uint16_t)(SPI_TCRC(spi_periph))); - } else { - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_ti_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; -} - -/*! - \brief disable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_ti_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); -} - -/*! - \brief enable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nssp_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; -} - -/*! - \brief disable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nssp_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); -} - -/*! - \brief enable quad wire SPI - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; -} - -/*! - \brief disable quad wire SPI - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); -} - -/*! - \brief enable quad wire SPI write - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_write_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); -} - -/*! - \brief enable quad wire SPI read - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_read_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; -} - -/*! - \brief enable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_io23_output_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; -} - -/*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_io23_output_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); -} - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) -{ - switch (interrupt) { - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) -{ - switch (interrupt) { - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default: - break; - } -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt flag status - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch (interrupt) { - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE: - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE: - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR: - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR: - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR: - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR: - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI/I2S format error interrupt */ - case SPI_I2S_INT_FLAG_FERR: - reg1 = reg1 & SPI_STAT_FERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default: - break; - } - /* get SPI/I2S interrupt flag status */ - if ((0U != reg1) && (0U != reg2)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] flag: SPI/I2S flag status - one or more parameters can be selected which are shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error interrupt flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if (RESET != (SPI_STAT(spi_periph) & flag)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_timer.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_timer.c deleted file mode 100644 index 6416f492d68..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_timer.c +++ /dev/null @@ -1,2045 +0,0 @@ -/*! - \file gd32e10x_timer.c - \brief TIMER driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_timer.h" - -/* TIMER init parameter mask */ -#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ -#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ -#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ - -/*! - \brief deinit a timer - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch (timer_periph) { - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER1: - /* reset TIMER1 */ - rcu_periph_reset_enable(RCU_TIMER1RST); - rcu_periph_reset_disable(RCU_TIMER1RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; - case TIMER3: - /* reset TIMER3 */ - rcu_periph_reset_enable(RCU_TIMER3RST); - rcu_periph_reset_disable(RCU_TIMER3RST); - break; - case TIMER4: - /* reset TIMER4 */ - rcu_periph_reset_enable(RCU_TIMER4RST); - rcu_periph_reset_disable(RCU_TIMER4RST); - break; - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; - case TIMER6: - /* reset TIMER6 */ - rcu_periph_reset_enable(RCU_TIMER6RST); - rcu_periph_reset_disable(RCU_TIMER6RST); - break; - case TIMER7: - /* reset TIMER7 */ - rcu_periph_reset_enable(RCU_TIMER7RST); - rcu_periph_reset_disable(RCU_TIMER7RST); - break; - case TIMER8: - /* reset TIMER8 */ - rcu_periph_reset_enable(RCU_TIMER8RST); - rcu_periph_reset_disable(RCU_TIMER8RST); - break; - case TIMER9: - /* reset TIMER9 */ - rcu_periph_reset_enable(RCU_TIMER9RST); - rcu_periph_reset_disable(RCU_TIMER9RST); - break; - case TIMER10: - /* reset TIMER10 */ - rcu_periph_reset_enable(RCU_TIMER10RST); - rcu_periph_reset_disable(RCU_TIMER10RST); - break; - case TIMER11: - /* reset TIMER11 */ - rcu_periph_reset_enable(RCU_TIMER11RST); - rcu_periph_reset_disable(RCU_TIMER11RST); - break; - case TIMER12: - /* reset TIMER12 */ - rcu_periph_reset_enable(RCU_TIMER12RST); - rcu_periph_reset_disable(RCU_TIMER12RST); - break; - case TIMER13: - /* reset TIMER13 */ - rcu_periph_reset_enable(RCU_TIMER13RST); - rcu_periph_reset_disable(RCU_TIMER13RST); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none - \retval none -*/ -void timer_struct_para_init(timer_parameter_struct *initpara) -{ - /* initialize the init parameter struct member with the default value */ - initpara->prescaler = 0U; - initpara->alignedmode = TIMER_COUNTER_EDGE; - initpara->counterdirection = TIMER_COUNTER_UP; - initpara->period = 65535U; - initpara->clockdivision = TIMER_CKDIV_DIV1; - initpara->repetitioncounter = 0U; -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock, 0~65535 - alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, - TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN - period: counter auto reload value, 0~65535 - clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value, 0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if ((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) - || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)) { - TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); - } else { - TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if ((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); - } - - if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a timer - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a timer - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] aligned: - only one parameter can be selected which is shown as below: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] prescaler: prescaler value - \param[in] pscreload: prescaler reload mode - only one parameter can be selected which is shown as below: - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if (TIMER_PSC_RELOAD_NOW == pscreload) { - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] repetition: the counter repetition value, 0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] autoreload: the counter auto-reload value - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] counter: the counter value - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0..8,11) - \param[in] spmode: - only one parameter can be selected which is shown as below: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) -{ - if (TIMER_SP_MODE_SINGLE == spmode) { - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - } else if (TIMER_SP_MODE_REPETITIVE == spmode) { - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] update: - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, - or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph, uint32_t update) -{ - if (TIMER_UPDATE_SRC_REGULAR == update) { - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - } else if (TIMER_UPDATE_SRC_GLOBAL == update) { - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - } else { - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: TIMERx(x=0..7) - \param[in] dma: specify which DMA to enable - one or more parameters can be selected which are shown as below: - \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: TIMERxTIMERx(x=0..7) - \param[in] dma: specify which DMA to disbale - one or more parameters can be selected which are shown as below: - \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] dma_request: channel DMA request source selection - only one parameter can be selected which is shown as below: - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) -{ - if (TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - } else if (TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] dma_baseaddr: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..4,7) - \param[in] dma_lenth: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] event: the timer software event generation sources - one or more parameters can be selected which are shown as below: - \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none - \retval none -*/ -void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) -{ - /* initialize the break parameter struct member with the default value */ - breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; - breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; - breakpara->deadtime = 0U; - breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; - breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; - breakpara->protectmode = TIMER_CCHP_PROT_OFF; - breakpara->breakstate = TIMER_BREAK_DISABLE; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | - ((uint32_t)(breakpara->ideloffstate)) | - ((uint32_t)(breakpara->deadtime)) | - ((uint32_t)(breakpara->breakpolarity)) | - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode)) | - ((uint32_t)(breakpara->breakstate))); -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief enable or disable TIMER primary output function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if (ENABLE == newvalue) { - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - } else { - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief enable or disable channel capture/compare control shadow register - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if (ENABLE == newvalue) { - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - } else { - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] ccuctl: channel control shadow register update control - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) -{ - if (TIMER_UPDATECTL_CCU == ccuctl) { - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - } else if (TIMER_UPDATECTL_CCUTRI == ccuctl) { - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - } else { - /* illegal parameters */ - } -} - -/*! - \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none - \retval none -*/ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) -{ - /* initialize the channel output parameter struct member with the default value */ - ocpara->outputstate = TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_DISABLE; - ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; - ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; - ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; - ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - - if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); - } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - - if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); - } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - - if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); - } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocmode: channel output compare mode - only one parameter can be selected which is shown as below: - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM mode 0 - \arg TIMER_OC_MODE_PWM1: PWM mode 1 - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] pulse: channel output pulse value - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocshadow: channel output shadow state - only one parameter can be selected which is shown as below: - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocfast: channel output fast function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] occlear: channel output clear function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocpolarity: channel output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,7)) - \param[in] ocnpolarity: channel complementary output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] state: TIMER channel enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,7)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,7)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,7)) - \param[in] ocnstate: TIMER channel complementary output enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none - \retval none -*/ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) -{ - /* initialize the channel input parameter struct member with the default value */ - icpara->icpolarity = TIMER_IC_POLARITY_RISING; - icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; - icpara->icprescaler = TIMER_IC_PSC_DIV1; - icpara->icfilter = 0U; -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, - TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) - icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, - TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, - TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] prescaler: channel input capture prescaler value - only one parameter can be selected which is shown as below: - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) -{ - switch (channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) -{ - uint32_t count_value = 0U; - - switch (channel) { - case TIMER_CH_0: - /* read TIMER channel 0 capture compare register value */ - count_value = TIMER_CH0CV(timer_periph); - break; - case TIMER_CH_1: - /* read TIMER channel 1 capture compare register value */ - count_value = TIMER_CH1CV(timer_periph); - break; - case TIMER_CH_2: - /* read TIMER channel 2 capture compare register value */ - count_value = TIMER_CH2CV(timer_periph); - break; - case TIMER_CH_3: - /* read TIMER channel 3 capture compare register value */ - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0 - \arg TIMER_CH_1: TIMER channel 1 - \param[in] icpwm: TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, - TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - /* Set channel input polarity */ - if (TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { - icpolarity = TIMER_IC_POLARITY_FALLING; - } else { - icpolarity = TIMER_IC_POLARITY_RISING; - } - /* Set channel input mode selection */ - if (TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { - icselection = TIMER_IC_SELECTION_INDIRECTTI; - } else { - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if (TIMER_CH_0 == channel) { - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - } else { - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] hallmode: - only one parameter can be selected which is shown as below: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) -{ - if (TIMER_HALLINTERFACE_ENABLE == hallmode) { - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - } else if (TIMER_HALLINTERFACE_DISABLE == hallmode) { - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - } else { - /* illegal parameters */ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0..4,7)) - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0..7) - \param[in] outrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] slavemode: - only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 - \arg TIMER_SLAVE_MODE_RESTART: restart mode - \arg TIMER_SLAVE_MODE_PAUSE: pause mode - \arg TIMER_SLAVE_MODE_EVENT: event mode - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0 - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] masterslave: - only one parameter can be selected which is shown as below: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) -{ - if (TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - } else if (TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] decomode: - only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) -{ - /* configure the quadrature decoder mode */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - /* configure input capture selection */ - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - /* configure channel input capture polarity */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph, intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: active low or falling edge active - \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) -{ - if (TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - } else { - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph, extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief configure TIMER write CHxVAL register selection - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] ccsel: - only one parameter can be selected which is shown as below: - \arg TIMER_CHVSEL_DISABLE: no effect - \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored - \param[out] none - \retval none -*/ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) -{ - if (TIMER_CHVSEL_ENABLE == ccsel) { - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - } else if (TIMER_CHVSEL_DISABLE == ccsel) { - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER output value selection - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] outsel: - only one parameter can be selected which is shown as below: - \arg TIMER_OUTSEL_DISABLE: no effect - \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled - \param[out] none - \retval none -*/ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) -{ - if (TIMER_OUTSEL_ENABLE == outsel) { - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - } else if (TIMER_OUTSEL_DISABLE == outsel) { - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; - } else { - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] interrupt: specify which interrupt to enable - one or more parameters can be selected which are shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] interrupt: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if ((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] interrupt: the timer interrupt bits - one or more parameters can be selected which are shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if (RESET != (TIMER_INTF(timer_periph) & flag)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] flag: the timer interrupt flags - one or more parameters can be selected which are shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)flag); -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_usart.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_usart.c deleted file mode 100644 index a43c1a4b0ae..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_usart.c +++ /dev/null @@ -1,931 +0,0 @@ -/*! - \file gd32e10x_usart.c - \brief USART driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_usart.h" - -/* USART register bit offset */ -#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ -#define CTL3_SCRTNUM_OFFSET ((uint32_t)1U) /* bit offset of SCRTNUM in USART_CTL3 */ -#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ - -/*! - \brief reset USART/UART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch (usart_periph) { - case USART0: - /* reset USART0 */ - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - /* reset USART1 */ - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - case USART2: - /* reset USART2 */ - rcu_periph_reset_enable(RCU_USART2RST); - rcu_periph_reset_disable(RCU_USART2RST); - break; - case UART3: - /* reset UART3 */ - rcu_periph_reset_enable(RCU_UART3RST); - rcu_periph_reset_disable(RCU_UART3RST); - break; - case UART4: - /* reset UART4 */ - rcu_periph_reset_enable(RCU_UART4RST); - rcu_periph_reset_disable(RCU_UART4RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; - switch (usart_periph) { - /* get clock frequency */ - case USART0: - /* get USART0 clock */ - uclk = rcu_clock_freq_get(CK_APB2); - break; - case USART1: - /* get USART1 clock */ - uclk = rcu_clock_freq_get(CK_APB1); - break; - case USART2: - /* get USART2 clock */ - uclk = rcu_clock_freq_get(CK_APB1); - break; - case UART3: - /* get UART3 clock */ - uclk = rcu_clock_freq_get(CK_APB1); - break; - case UART4: - /* get UART4 clock */ - uclk = rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - /* oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk + baudval / 2U) / baudval; - intdiv = udiv & 0xfff0U; - fradiv = udiv & 0xfU; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); -} - -/*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] paritycfg: configure USART parity - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* clear USART_CTL0 PM,PCEN bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - /* configure USART stop bits */ - USART_CTL1(usart_periph) |= stblen; -} - -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] txconfig: enable or disable USART transmitter - only one parameter can be selected which is shown as below: - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: disable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_TEN; - ctl |= txconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] rxconfig: enable or disable USART receiver - only one parameter can be selected which is shown as below: - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_REN; - ctl |= rxconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief data is transmitted/received with the LSB/MSB first - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] msbf: LSB/MSB - only one parameter can be selected which is shown as below: - \arg USART_MSBF_LSB: LSB first - \arg USART_MSBF_MSB: MSB first - \param[out] none - \retval none -*/ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL3(usart_periph); - ctl &= ~(USART_CTL3_MSBF); - ctl |= msbf; - /* configure data transmitted/received mode */ - USART_CTL3(usart_periph) = ctl; -} - -/*! - \brief configure USART inversion - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] invertpara: refer to enum usart_invert_enum - only one parameter can be selected which is shown as below: - \arg USART_DINV_ENABLE: data bit level inversion - \arg USART_DINV_DISABLE: data bit level not inversion - \arg USART_TXPIN_ENABLE: TX pin level inversion - \arg USART_TXPIN_DISABLE: TX pin level not inversion - \arg USART_RXPIN_ENABLE: RX pin level inversion - \arg USART_RXPIN_DISABLE: RX pin level not inversion - \param[out] none - \retval none -*/ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) -{ - /* inverted or not the specified siginal */ - switch (invertpara) { - case USART_DINV_ENABLE: - /* data bit level inversion */ - USART_CTL3(usart_periph) |= USART_CTL3_DINV; - break; - case USART_TXPIN_ENABLE: - /* TX pin level inversion */ - USART_CTL3(usart_periph) |= USART_CTL3_TINV; - break; - case USART_RXPIN_ENABLE: - /* RX pin level inversion */ - USART_CTL3(usart_periph) |= USART_CTL3_RINV; - break; - case USART_DINV_DISABLE: - /* data bit level not inversion */ - USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); - break; - case USART_TXPIN_DISABLE: - /* TX pin level not inversion */ - USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); - break; - case USART_RXPIN_DISABLE: - /* RX pin level not inversion */ - USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); - break; - default: - break; - } -} - -/*! - \brief enable receiver timeout of USART - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_enable(uint32_t usart_periph) -{ - USART_CTL3(usart_periph) |= USART_CTL3_RTEN; -} - -/*! - \brief disable receiver timeout of USART - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_disable(uint32_t usart_periph) -{ - USART_CTL3(usart_periph) &= ~(USART_CTL3_RTEN); -} - -/*! - \brief set the receiver timeout threshold of USART - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] rtimeout: 0-0xFFFFFF - \param[out] none - \retval none -*/ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) -{ - USART_RT(usart_periph) &= ~(USART_RT_RT); - USART_RT(usart_periph) |= rtimeout; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] data: data to be transmitted - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); -} - -/*! - \brief configure the address of the USART in wake up by address match mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] addr: address of USART/UART - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); -} - -/*! - \brief receiver in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_RWU; -} - -/*! - \brief receiver in active mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wmethod: two methods be used to enter or exit the mute mode - only one parameter can be selected which is shown as below: - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mask - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmethod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief configure lin break frame length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] lblen: lin break frame length - only one parameter can be selected which is shown as below: - \arg USART_LBLEN_10B: 10 bits - \arg USART_LBLEN_11B: 11 bits - \param[out] none - \retval none -*/ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); -} - -/*! - \brief send break frame - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_send_break(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; -} - -/*! - \brief enable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] clen: CK length - only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame - \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame - \param[in] cph: clock phase - only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin - \arg USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] guat: guard time value, 0-0xFF - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) -{ - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << GP_GUAT_OFFSET)); -} - -/*! - \brief enable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_SCEN; -} - -/*! - \brief disable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); -} - -/*! - \brief enable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_NKEN; -} - -/*! - \brief disable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); -} - -/*! - \brief configure smartcard auto-retry number - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] scrtnum: smartcard auto-retry number - \param[out] none - \retval none -*/ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) -{ - USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); - USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum) << CTL3_SCRTNUM_OFFSET)); -} - -/*! - \brief configure block length in Smartcard T=1 reception - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] bl: block length - \param[out] none - \retval none -*/ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl) -{ - USART_RT(usart_periph) &= ~(USART_RT_BL); - USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << RT_BL_OFFSET)); -} - -/*! - \brief enable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_IREN; -} - -/*! - \brief disable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); -} - -/*! - \brief configure the peripheral clock prescaler in USART IrDA low-power mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] psc: 0x00-0xFF - \param[out] none - \retval none -*/ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) -{ - USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; -} - -/*! - \brief configure IrDA low-power - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] irlp: IrDA low-power or normal - only one parameter can be selected which is shown as below: - \arg USART_IRLP_LOW: low-power - \arg USART_IRLP_NORMAL: normal - \param[out] none - \retval none -*/ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); - USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); -} - -/*! - \brief configure hardware flow control RTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] rtsconfig: enable or disable RTS - only one parameter can be selected which is shown as below: - \arg USART_RTS_ENABLE: enable RTS - \arg USART_RTS_DISABLE: disable RTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_RTSEN; - ctl |= rtsconfig; - /* configure RTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure hardware flow control CTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] ctsconfig: enable or disable CTS - only one parameter can be selected which is shown as below: - \arg USART_CTS_ENABLE: enable CTS - \arg USART_CTS_DISABLE: disable CTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_CTSEN; - ctl |= ctsconfig; - /* configure CTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA reception - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for reception - only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception - \param[out] none - \retval none -*/ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENR; - ctl |= dmacmd; - /* configure DMA reception */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA transmission - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for transmission - only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission - \param[out] none - \retval none -*/ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENT; - ctl |= dmacmd; - /* configure DMA transmission */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure hardware flow control coherence mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] hcm: - \arg USART_RTS_NONE_COHERENCE: nRTS signal equals to the rxne status register - \arg USART_RTS_COHERENCE: nRTS signal is set when the last data bit has been sampled - \param[out] none - \retval none -*/ -void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) -{ - USART_CHC(usart_periph) &= ~(USART_CHC_HCM); - USART_CHC(usart_periph) |= (USART_CHC_HCM & hcm); -} - -/*! - \brief get flag in STAT0/STAT1 register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTS: CTS change flag - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_TBE: transmit data buffer empty - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_IDLE: IDLE frame detected flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_BSY: busy flag - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_RT: receiver timeout flag - \arg USART_FLAG_EPERR: early parity error flag -\param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) -{ - if (RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear flag in STAT0/STAT1 register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTS: CTS change flag - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_RT: receiver timeout flag - \arg USART_FLAG_EPERR: early parity error flag - \param[out] none - \retval none -*/ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) -{ - USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); -} - -/*! - \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum - only one parameter can be selected which is shown as below: - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_RT: interrupt enable bit of receive timeout event - \arg USART_INT_EB: interrupt enable bit of end of block event - \param[out] none - \retval none -*/ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) -{ - USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); -} - -/*! - \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum - only one parameter can be selected which is shown as below: - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_RT: interrupt enable bit of receive timeout event - \arg USART_INT_EB: interrupt enable bit of end of block event - \param[out] none - \retval none -*/ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) -{ - USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); -} - -/*! - \brief get USART interrupt and flag status - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_PERR: parity error interrupt and flag - \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag - \arg USART_INT_FLAG_TC: transmission complete interrupt and flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag - \arg USART_INT_FLAG_CTS: CTS interrupt and flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag - \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag - \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag - \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - /* get the interrupt enable bit status */ - intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - - if ((0U != flagstatus) && (0U != intenable)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear USART interrupt flag in STAT0/STAT1 register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_CTS: CTS change flag - \arg USART_INT_FLAG_LBD: LIN break detected flag - \arg USART_INT_FLAG_TC: transmission complete - \arg USART_INT_FLAG_RBNE: read data buffer not empty - \arg USART_INT_FLAG_EB: end of block flag - \arg USART_INT_FLAG_RT: receiver timeout flag - \param[out] none - \retval none -*/ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) -{ - USART_REG_VAL2(usart_periph, int_flag) &= ~BIT(USART_BIT_POS2(int_flag)); -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_wwdgt.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_wwdgt.c deleted file mode 100644 index 737f5489db0..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/GD32E10x_standard_peripheral/Source/gd32e10x_wwdgt.c +++ /dev/null @@ -1,149 +0,0 @@ -/*! - \file gd32e10x_wwdgt.c - \brief WWDGT driver - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e10x_wwdgt.h" - -/* write value to WWDGT_CTL_CNT bit field */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -/* write value to WWDGT_CFG_WIN bit field */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/*! - \brief reset the window watchdog timer configuration - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_deinit(void) -{ - rcu_periph_reset_enable(RCU_WWDGTRST); - rcu_periph_reset_disable(RCU_WWDGTRST); -} - -/*! - \brief start the window watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_enable(void) -{ - WWDGT_CTL |= WWDGT_CTL_WDGTEN; -} - -/*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00 - 0x7F - \param[out] none - \retval none -*/ -void wwdgt_counter_update(uint16_t counter_value) -{ - uint32_t reg = 0U; - - reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - reg |= CTL_CNT(counter_value); - - WWDGT_CTL = reg; -} - -/*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00 - 0x7F - \param[in] window: 0x00 - 0x7F - \param[in] prescaler: wwdgt prescaler value - only one parameter can be selected which is shown as below: - \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 - \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 - \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 - \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 - \param[out] none - \retval none -*/ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) -{ - uint32_t reg_cfg = 0U, reg_ctl = 0U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = (WWDGT_CFG & (~(WWDGT_CFG_WIN | WWDGT_CFG_PSC))); - reg_ctl = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= CFG_WIN(window); - reg_cfg |= prescaler; - reg_ctl |= CTL_CNT(counter); - - WWDGT_CTL = reg_ctl; - WWDGT_CFG = reg_cfg; -} - -/*! - \brief enable early wakeup interrupt of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_interrupt_enable(void) -{ - WWDGT_CFG |= WWDGT_CFG_EWIE; -} - -/*! - \brief check early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus wwdgt_flag_get(void) -{ - if (RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)) { - return SET; - } - - return RESET; -} - -/*! - \brief clear early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_flag_clear(void) -{ - WWDGT_STAT &= (~WWDGT_STAT_EWIF); -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/PeripheralPins.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/PeripheralPins.h deleted file mode 100644 index 14fe0e8621b..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/PeripheralPins.h +++ /dev/null @@ -1,74 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -extern const int GD_GPIO_REMAP[]; -extern const int GD_GPIO_MODE[]; -extern const int GD_GPIO_SPEED[]; - -/* ADC */ -#ifdef DEVICE_ANALOGIN -extern const PinMap PinMap_ADC[]; -#endif - -/* DAC */ -#ifdef DEVICE_ANALOGOUT -extern const PinMap PinMap_DAC[]; -#endif - -/* I2C */ -#if DEVICE_I2C -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; -#endif - -/* PWM */ -#if DEVICE_PWMOUT -extern const PinMap PinMap_PWM[]; -#endif - -/* SERIAL */ -#ifdef DEVICE_SERIAL -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -#ifdef DEVICE_SERIAL_FC -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; -#endif -#endif - -/* SPI */ -#ifdef DEVICE_SPI -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; -#endif - -/* CAN */ -#ifdef DEVICE_CAN -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; -#endif - -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/PortNames.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/PortNames.h deleted file mode 100644 index 773bed473d1..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/PortNames.h +++ /dev/null @@ -1,36 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PORTA = 0, - PORTB = 1, - PORTC = 2, - PORTD = 3, - PORTE = 4, -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PeripheralNames.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PeripheralNames.h deleted file mode 100644 index 6788b0158ea..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PeripheralNames.h +++ /dev/null @@ -1,84 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_0 = (int)ADC0, - ADC_1 = (int)ADC1 -} ADCName; - -typedef enum { - DAC_0 = (int)DAC, -} DACName; - -typedef enum { - UART_0 = (int)USART0, - UART_1 = (int)USART1, - UART_2 = (int)USART2, - UART_3 = (int)UART3, - UART_4 = (int)UART4 -} UARTName; - -#define STDIO_UART_TX PORTA_2 -#define STDIO_UART_RX PORTA_3 -#define STDIO_UART UART_1 - -typedef enum { - SPI_0 = (int)SPI0, - SPI_1 = (int)SPI1, - SPI_2 = (int)SPI2 -} SPIName; - -typedef enum { - I2C_0 = (int)I2C0, - I2C_1 = (int)I2C1 -} I2CName; - -typedef enum { - PWM_0 = (int)TIMER0, - PWM_1 = (int)TIMER1, - PWM_2 = (int)TIMER2, - PWM_3 = (int)TIMER3, - PWM_4 = (int)TIMER4, - PWM_5 = (int)TIMER7, - PWM_6 = (int)TIMER8, - PWM_7 = (int)TIMER9, - PWM_8 = (int)TIMER10, - PWM_9 = (int)TIMER11, - PWM_10 = (int)TIMER12, - PWM_11 = (int)TIMER13 -} PWMName; - -typedef enum { - CAN_0 = (int)CAN0, - CAN_1 = (int)CAN1 -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PeripheralPins.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PeripheralPins.c deleted file mode 100644 index c4d98941c99..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PeripheralPins.c +++ /dev/null @@ -1,316 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - - -/* void pin_function(PinName pin, int function); - configure the speed, mode,and remap function of pins - the parameter function contains the configuration information,show as below - bit 0:2 gpio mode - bit 3:8 remap - bit 9:10 gpio speed - bit 11:15 adc /timer channel -*/ -const int GD_GPIO_REMAP[] = { - 0x00000000, - GPIO_SPI0_REMAP, /* 1 */ - GPIO_I2C0_REMAP, /* 2 */ - GPIO_USART0_REMAP, /* 3 */ - GPIO_USART1_REMAP, /* 4 */ - GPIO_USART2_PARTIAL_REMAP, /* 5 */ - GPIO_USART2_FULL_REMAP, /* 6 */ - GPIO_TIMER0_PARTIAL_REMAP, /* 7 */ - GPIO_TIMER0_FULL_REMAP, /* 8 */ - GPIO_TIMER1_PARTIAL_REMAP0, /* 9 */ - GPIO_TIMER1_PARTIAL_REMAP1, /* 10 */ - GPIO_TIMER1_FULL_REMAP, /* 11 */ - GPIO_TIMER2_PARTIAL_REMAP, /* 12 */ - GPIO_TIMER2_FULL_REMAP, /* 13 */ - GPIO_TIMER3_REMAP, /* 14 */ - GPIO_PD01_REMAP, /* 15 */ - GPIO_TIMER4CH3_IREMAP, /* 16 */ - GPIO_ADC0_ETRGINS_REMAP, /* 17 */ - GPIO_ADC0_ETRGREG_REMAP, /* 18 */ - GPIO_ADC1_ETRGINS_REMAP, /* 19 */ - GPIO_ADC1_ETRGREG_REMAP, /* 20 */ - GPIO_SWJ_NONJTRST_REMAP, /* 21 */ - GPIO_SWJ_SWDPENABLE_REMAP, /* 22 */ - GPIO_SWJ_DISABLE_REMAP, /* 23 */ - GPIO_CAN0_PARTIAL_REMAP, /* 24 */ - GPIO_CAN0_FULL_REMAP, /* 25 */ - GPIO_CAN1_REMAP, /* 26 */ - GPIO_SPI2_REMAP, /* 27 */ - GPIO_TIMER1ITR0_REMAP, /* 28 */ - GPIO_TIMER8_REMAP, /* 29 */ - GPIO_EXMC_NADV_REMAP, /* 30 */ - GPIO_CTC_REMAP0, /* 31 */ -}; - -/* GPIO MODE */ -const int GD_GPIO_MODE[] = { - GPIO_MODE_AIN, /* 0 */ - GPIO_MODE_IN_FLOATING, /* 1 */ - GPIO_MODE_IPD, /* 2 */ - GPIO_MODE_IPU, /* 3 */ - GPIO_MODE_OUT_OD, /* 4 */ - GPIO_MODE_OUT_PP, /* 5 */ - GPIO_MODE_AF_OD, /* 6 */ - GPIO_MODE_AF_PP, /* 7 */ -}; - -/* GPIO SPEED */ -const int GD_GPIO_SPEED[] = { - GPIO_OSPEED_50MHZ, /* 0 */ - GPIO_OSPEED_10MHZ, /* 1 */ - GPIO_OSPEED_2MHZ, /* 2 */ -}; - -/* ADC PinMap */ -const PinMap PinMap_ADC[] = { - {PORTA_0, ADC_0, 0 | (0 << 11)}, /* ADC0_IN0 */ - {PORTA_1, ADC_0, 0 | (1 << 11)}, /* ADC0_IN1 */ - {PORTA_2, ADC_0, 0 | (2 << 11)}, /* ADC0_IN2 */ - {PORTA_3, ADC_0, 0 | (3 << 11)}, /* ADC0_IN3 */ - {PORTA_4, ADC_0, 0 | (4 << 11)}, /* ADC0_IN4 */ - {PORTA_5, ADC_0, 0 | (5 << 11)}, /* ADC0_IN5 */ - {PORTA_6, ADC_0, 0 | (6 << 11)}, /* ADC0_IN6 */ - {PORTA_7, ADC_0, 0 | (7 << 11)}, /* ADC0_IN7 */ - {PORTB_0, ADC_0, 0 | (8 << 11)}, /* ADC0_IN8 */ - {PORTB_1, ADC_0, 0 | (9 << 11)}, /* ADC0_IN9 */ - {PORTC_0, ADC_0, 0 | (10 << 11)}, /* ADC0_IN10 */ - {PORTC_1, ADC_0, 0 | (11 << 11)}, /* ADC0_IN11 */ - {PORTC_2, ADC_0, 0 | (12 << 11)}, /* ADC0_IN12 */ - {PORTC_3, ADC_0, 0 | (13 << 11)}, /* ADC0_IN13 */ - {PORTC_4, ADC_0, 0 | (14 << 11)}, /* ADC0_IN14 */ - {PORTC_5, ADC_0, 0 | (15 << 11)}, /* ADC0_IN15 */ - {ADC_TEMP, ADC_0, 0 | (16 << 11)}, /* ADC0_IN16 */ - {ADC_VREF, ADC_0, 0 | (17 << 11)}, /* ADC0_IN17 */ - - {PORTA_0_MUL0, ADC_1, 0 | (0 << 11)}, /* ADC1_IN0 */ - {PORTA_1_MUL0, ADC_1, 0 | (1 << 11)}, /* ADC1_IN1 */ - {PORTA_2_MUL0, ADC_1, 0 | (2 << 11)}, /* ADC1_IN2 */ - {PORTA_3_MUL0, ADC_1, 0 | (3 << 11)}, /* ADC1_IN3 */ - {PORTA_4_MUL0, ADC_1, 0 | (4 << 11)}, /* ADC1_IN4 */ - {PORTA_5_MUL0, ADC_1, 0 | (5 << 11)}, /* ADC1_IN5 */ - {PORTA_6_MUL0, ADC_1, 0 | (6 << 11)}, /* ADC1_IN6 */ - {PORTA_7_MUL0, ADC_1, 0 | (7 << 11)}, /* ADC1_IN7 */ - {PORTB_0_MUL0, ADC_1, 0 | (8 << 11)}, /* ADC1_IN8 */ - {PORTB_1_MUL0, ADC_1, 0 | (9 << 11)}, /* ADC1_IN9 */ - {PORTC_0_MUL0, ADC_1, 0 | (10 << 11)}, /* ADC1_IN10 */ - {PORTC_1_MUL0, ADC_1, 0 | (11 << 11)}, /* ADC1_IN11 */ - {PORTC_2_MUL0, ADC_1, 0 | (12 << 11)}, /* ADC1_IN12 */ - {PORTC_3_MUL0, ADC_1, 0 | (13 << 11)}, /* ADC1_IN13 */ - {PORTC_4_MUL0, ADC_1, 0 | (14 << 11)}, /* ADC1_IN14 */ - {PORTC_5_MUL0, ADC_1, 0 | (15 << 11)}, /* ADC1_IN15 */ - {NC, NC, 0} -}; - -/* DAC PinMap */ -const PinMap PinMap_DAC[] = { - {PORTA_4, DAC_0, 0 | (0 << 11)}, /* DAC_OUT0 */ - {PORTA_5, DAC_0, 0 | (1 << 11)}, /* DAC_OUT1 */ - {NC, NC, 0} -}; - - -/* I2C PinMap */ -const PinMap PinMap_I2C_SDA[] = { - {PORTB_7, I2C_0, 6}, - {PORTB_9, I2C_0, 6 | (2 << 3)}, /* GPIO_I2C0_REMAP */ - {PORTB_11, I2C_1, 6}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PORTB_6, I2C_0, 6}, - {PORTB_8, I2C_0, 6 | (2 << 3)}, /* GPIO_I2C0_REMAP */ - {PORTB_10, I2C_1, 6}, - {NC, NC, 0} -}; - -/* PWM PinMap */ -const PinMap PinMap_PWM[] = { - {PORTA_8, PWM_0, 7 | (0 << 11)}, /* TIMER0_CH0 - Default */ - {PORTA_9, PWM_0, 7 | (1 << 11)}, /* TIMER0_CH1 - Default */ - {PORTA_10, PWM_0, 7 | (2 << 11)}, /* TIMER0_CH2 - Default */ - {PORTA_11, PWM_0, 7 | (3 << 11)}, /* TIMER0_CH3 - Default */ - {PORTE_9, PWM_0, 7 | (8 << 3) | (0 << 11)}, /* TIMER0_CH0 - GPIO_TIMER0_FULL_REMAP */ - {PORTE_11, PWM_0, 7 | (8 << 3) | (1 << 11)}, /* TIMER0_CH1 - GPIO_TIMER0_FULL_REMAP */ - {PORTE_13, PWM_0, 7 | (8 << 3) | (2 << 11)}, /* TIMER0_CH2 - GPIO_TIMER0_FULL_REMAP */ - {PORTE_14, PWM_0, 7 | (8 << 3) | (3 << 11)}, /* TIMER0_CH3 - GPIO_TIMER0_FULL_REMAP */ - - {PORTA_0, PWM_1, 7 | (0 << 11)}, /* TIMER1_CH0_ETI - Default */ - {PORTA_1, PWM_1, 7 | (1 << 11)}, /* TIMER1_CH1_ETI - Default */ - {PORTA_2, PWM_1, 7 | (2 << 11)}, /* TIMER1_CH2_ETI - Default */ - {PORTA_3, PWM_1, 7 | (3 << 11)}, /* TIMER1_CH3_ETI - Default */ - {PORTA_15, PWM_1, 7 | (9 << 3) | (0 << 11)}, /* TIMER1_CH0_ETI- GPIO_TIMER1_PARTIAL_REMAP0 */ - {PORTB_3, PWM_1, 7 | (9 << 3) | (1 << 11)}, /* TIMER1_CH1 - GPIO_TIMER1_PARTIAL_REMAP0 */ - {PORTB_10, PWM_1, 7 | (10 << 3) | (2 << 11)}, /* TIMER1_CH2 - GPIO_TIMER1_PARTIAL_REMAP1 */ - {PORTB_11, PWM_1, 7 | (10 << 3) | (3 << 11)}, /* TIMER1_CH3 - GPIO_TIMER1_PARTIAL_REMAP1 */ - {PORTA_15, PWM_1, 7 | (11 << 3) | (0 << 11)}, /* TIMER1_CH0_ETI - GPIO_TIMER1_FULL_REMAP */ - {PORTB_3, PWM_1, 7 | (11 << 3) | (1 << 11)}, /* TIMER1_CH1 - GPIO_TIMER1_FULL_REMAP */ - {PORTB_10, PWM_1, 7 | (11 << 3) | (2 << 11)}, /* TIMER1_CH2 - GPIO_TIMER1_FULL_REMAP */ - {PORTB_11, PWM_1, 7 | (11 << 3) | (3 << 11)}, /* TIMER1_CH3 - GPIO_TIMER1_FULL_REMAP */ - - {PORTA_6, PWM_2, 7 | (0 << 11)}, /* TIMER2_CH0 - Default */ - {PORTA_7, PWM_2, 7 | (1 << 11)}, /* TIMER2_CH1 - Default */ - {PORTB_0, PWM_2, 7 | (2 << 11)}, /* TIMER2_CH2 - Default */ - {PORTB_1, PWM_2, 7 | (3 << 11)}, /* TIMER2_CH3 - Default */ - {PORTB_4, PWM_2, 7 | (12 << 3) | (0 << 11)}, /* TIMER2_CH0 - GPIO_TIMER2_PARTIAL_REMAP */ - {PORTB_5, PWM_2, 7 | (12 << 3) | (1 << 11)}, /* TIMER2_CH1 - GPIO_TIMER2_PARTIAL_REMAP */ - {PORTC_6, PWM_2, 7 | (13 << 3) | (0 << 11)}, /* TIMER2_CH0 - GPIO_TIMER2_FULL_REMAP */ - {PORTC_7, PWM_2, 7 | (13 << 3) | (1 << 11)}, /* TIMER2_CH1 - GPIO_TIMER2_FULL_REMAP */ - {PORTC_8, PWM_2, 7 | (13 << 3) | (2 << 11)}, /* TIMER2_CH2 - GPIO_TIMER2_FULL_REMAP */ - {PORTC_9, PWM_2, 7 | (13 << 3) | (3 << 11)}, /* TIMER2_CH3 - GPIO_TIMER2_FULL_REMAP */ - - {PORTB_6, PWM_3, 7 | (0 << 11)}, /* TIMER3_CH0 - Default */ - {PORTB_7, PWM_3, 7 | (1 << 11)}, /* TIMER3_CH1 - Default */ - {PORTB_8, PWM_3, 7 | (2 << 11)}, /* TIMER3_CH2 - Default */ - {PORTB_9, PWM_3, 7 | (3 << 11)}, /* TIMER3_CH3 - Default */ - {PORTD_12, PWM_3, 7 | (14 << 3) | (0 << 11)}, /* TIMER3_CH0 - GPIO_TIMER3_REMAP */ - {PORTD_13, PWM_3, 7 | (14 << 3) | (1 << 11)}, /* TIMER3_CH1 - GPIO_TIMER3_REMAP */ - {PORTD_14, PWM_3, 7 | (14 << 3) | (2 << 11)}, /* TIMER3_CH2 - GPIO_TIMER3_REMAP */ - {PORTD_15, PWM_3, 7 | (14 << 3) | (3 << 11)}, /* TIMER3_CH3 - GPIO_TIMER3_REMAP */ - - {PORTA_0_MUL0, PWM_4, 7 | (0 << 11)}, /* TIMER4_CH0 - Default */ - {PORTA_1_MUL0, PWM_4, 7 | (1 << 11)}, /* TIMER4_CH1 - Default */ - {PORTA_2_MUL0, PWM_4, 7 | (2 << 11)}, /* TIMER4_CH2 - Default */ - {PORTA_3_MUL0, PWM_4, 7 | (3 << 11)}, /* TIMER4_CH3 - Default */ - - {PORTC_6_MUL0, PWM_5, 7 | (0 << 11)}, /* TIMER7_CH0 - Default */ - {PORTC_7_MUL0, PWM_5, 7 | (1 << 11)}, /* TIMER7_CH1 - Default */ - {PORTC_8_MUL0, PWM_5, 7 | (2 << 11)}, /* TIMER7_CH2 - Default */ - {PORTC_9_MUL0, PWM_5, 7 | (3 << 11)}, /* TIMER7_CH3 - Default */ - - {PORTA_2_MUL1, PWM_6, 7 | (0 << 11)}, /* TIMER8_CH0 - Default */ - {PORTA_3_MUL1, PWM_6, 7 | (1 << 11)}, /* TIMER8_CH1 - Default */ - {PORTE_5, PWM_6, 7 | (29 << 3) | (0 << 11)}, /* TIMER8_CH0 - GPIO_TIMER8_REMAP */ - {PORTE_6, PWM_6, 7 | (29 << 3) | (1 << 11)}, /* TIMER8_CH1 - GPIO_TIMER8_REMAP */ - - {PORTB_8_MUL0, PWM_7, 7 | (0 << 11)}, /* TIMER9_CH0 - Default */ - - {PORTB_9_MUL0, PWM_8, 7 | (0 << 11)}, /* TIMER10_CH0 - Default */ - - {PORTB_14, PWM_9, 7 | (0 << 11)}, /* TIMER11_CH0 - Default */ - {PORTB_15, PWM_9, 7 | (1 << 11)}, /* TIMER11_CH1 - Default */ - - {PORTA_6_MUL0, PWM_10, 7 | (0 << 11)}, /* TIMER12_CH0 - Default */ - - {PORTA_7_MUL0, PWM_11, 7 | (0 << 11)}, /* TIMER13_CH0 - Default */ - - {NC, NC, 0} -}; - -/* USART PinMap */ -const PinMap PinMap_UART_TX[] = { - {PORTA_9, UART_0, 7}, - {PORTB_6, UART_0, 7 | (3 << 3)}, /* GPIO_USART0_TX_REMAP */ - {PORTA_2, UART_1, 7}, - {PORTD_5, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_TX_REMAP */ - {PORTB_10, UART_2, 7}, - {PORTC_10, UART_2, 7 | (5 << 3)}, /* GPIO_USART2_TX_PARTIAL_REMAP */ - {PORTD_8, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_TX_FULL_REMAP */ - {PORTC_10_MUL0, UART_3, 7}, - {PORTC_12, UART_4, 7}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PORTA_10, UART_0, 1}, - {PORTB_7, UART_0, 1 | (3 << 3)}, /* GPIO_USART0_RX_REMAP */ - {PORTA_3, UART_1, 1}, - {PORTD_6, UART_1, 1 | (4 << 3)}, /* GPIO_USART1_RX_REMAP */ - {PORTB_11, UART_2, 1}, - {PORTC_11, UART_2, 1 | (5 << 3)}, /* GPIO_USART2_RX_PARTIAL_REMAP */ - {PORTD_9, UART_2, 1 | (6 << 3)}, /* GPIO_USART2_RX_FULL_REMAP */ - {PORTC_11_MUL0, UART_3, 1}, - {PORTD_2, UART_4, 1}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RTS[] = { - {PORTA_12, UART_0, 7}, - {PORTA_1, UART_1, 7}, - {PORTD_4, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_RTS_REMAP */ - {PORTB_14, UART_2, 7}, - {PORTD_12, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_RTS_FULL_REMAP */ - {NC, NC, 0} -}; - -const PinMap PinMap_UART_CTS[] = { - {PORTA_11, UART_0, 7}, - {PORTA_0, UART_1, 7}, - {PORTD_3, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_CTS_REMAP */ - {PORTB_13, UART_2, 7}, - {PORTD_11, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_CTS_FULL_REMAP */ - {NC, NC, 0} -}; - -/* SPI PinMap */ -const PinMap PinMap_SPI_MOSI[] = { - {PORTA_7, SPI_0, 7}, - {PORTB_5, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ - {PORTB_15, SPI_1, 7}, - {PORTC_12, SPI_2, 7 | (27 << 3)}, /* GPIO_SPI2_REMAP */ - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PORTA_6, SPI_0, 7}, - {PORTB_4, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ - {PORTB_14, SPI_1, 7}, - {PORTC_11, SPI_2, 7 | (27 << 3)}, /* GPIO_SPI2_REMAP */ - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PORTA_5, SPI_0, 7}, - {PORTB_3, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ - {PORTB_13, SPI_1, 7}, - {PORTC_10, SPI_2, 7 | (27 << 3)}, /* GPIO_SPI2_REMAP */ - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PORTA_4, SPI_0, 7}, - {PORTA_15, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ - {PORTB_12, SPI_1, 7}, - {PORTA_4_MUL0, SPI_2, 7 | (27 << 3)}, /* GPIO_SPI2_REMAP */ - {NC, NC, 0} -}; - -/* CAN PinMap */ -const PinMap PinMap_CAN_RD[] = { - {PORTA_11, CAN_0, 3}, - {PORTB_8, CAN_0, 3 | (24 << 3)}, /* GPIO_CAN0_PARTIAL_REMAP */ - {PORTD_0, CAN_0, 3 | (25 << 3)}, /* GPIO_CAN0_FULL_REMAP */ - {PORTB_12, CAN_1, 3}, - {PORTB_5, CAN_1, 3 | (26 << 3)}, /* GPIO_CAN1_REMAP */ - {NC, NC, 0} -}; - -const PinMap PinMap_CAN_TD[] = { - {PORTA_12, CAN_0, 7}, - {PORTB_9, CAN_0, 7 | (24 << 3)}, /* GPIO_CAN0_PARTIAL_REMAP */ - {PORTD_1, CAN_0, 7 | (25 << 3)}, /* GPIO_CAN0_FULL_REMAP */ - {PORTB_13, CAN_1, 7}, - {PORTB_6, CAN_1, 7 | (26 << 3)}, /* GPIO_CAN1_REMAP */ - {NC, NC, 0} -}; - diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PinNames.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PinNames.h deleted file mode 100644 index 2d3da010f09..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/TARGET_GD32E103VB/PinNames.h +++ /dev/null @@ -1,245 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Multiplex GPIO flag*/ -typedef enum { - MUL0 = 0x100, - MUL1 = 0x200, - MUL2 = 0x300, - MUL3 = 0x400 -} MULx; - -typedef enum { - PORTA_0 = 0x00, - PORTA_0_MUL0 = PORTA_0 | MUL0, - PORTA_1 = 0x01, - PORTA_1_MUL0 = PORTA_1 | MUL0, - PORTA_2 = 0x02, - PORTA_2_MUL0 = PORTA_2 | MUL0, - PORTA_2_MUL1 = PORTA_2 | MUL1, - PORTA_3 = 0x03, - PORTA_3_MUL0 = PORTA_3 | MUL0, - PORTA_3_MUL1 = PORTA_3 | MUL1, - PORTA_4 = 0x04, - PORTA_4_MUL0 = PORTA_4 | MUL0, - PORTA_4_MUL1 = PORTA_4 | MUL1, - PORTA_5 = 0x05, - PORTA_5_MUL0 = PORTA_5 | MUL0, - PORTA_6 = 0x06, - PORTA_6_MUL0 = PORTA_6 | MUL0, - PORTA_7 = 0x07, - PORTA_7_MUL0 = PORTA_7 | MUL0, - PORTA_8 = 0x08, - PORTA_9 = 0x09, - PORTA_10 = 0x0A, - PORTA_11 = 0x0B, - PORTA_12 = 0x0C, - PORTA_13 = 0x0D, - PORTA_14 = 0x0E, - PORTA_15 = 0x0F, - - PORTB_0 = 0x10, - PORTB_0_MUL0 = PORTB_0 | MUL0, - PORTB_1 = 0x11, - PORTB_1_MUL0 = PORTB_1 | MUL0, - PORTB_2 = 0x12, - PORTB_3 = 0x13, - PORTB_4 = 0x14, - PORTB_5 = 0x15, - PORTB_6 = 0x16, - PORTB_7 = 0x17, - PORTB_8 = 0x18, - PORTB_8_MUL0 = PORTB_8 | MUL0, - PORTB_9 = 0x19, - PORTB_9_MUL0 = PORTB_9 | MUL0, - PORTB_10 = 0x1A, - PORTB_11 = 0x1B, - PORTB_12 = 0x1C, - PORTB_13 = 0x1D, - PORTB_14 = 0x1E, - PORTB_15 = 0x1F, - - PORTC_0 = 0x20, - PORTC_0_MUL0 = PORTC_0 | MUL0, - PORTC_1 = 0x21, - PORTC_1_MUL0 = PORTC_1 | MUL0, - PORTC_2 = 0x22, - PORTC_2_MUL0 = PORTC_2 | MUL0, - PORTC_3 = 0x23, - PORTC_3_MUL0 = PORTC_3 | MUL0, - PORTC_4 = 0x24, - PORTC_4_MUL0 = PORTC_4 | MUL0, - PORTC_5 = 0x25, - PORTC_5_MUL0 = PORTC_5 | MUL0, - PORTC_6 = 0x26, - PORTC_6_MUL0 = PORTC_6 | MUL0, - PORTC_7 = 0x27, - PORTC_7_MUL0 = PORTC_7 | MUL0, - PORTC_8 = 0x28, - PORTC_8_MUL0 = PORTC_8 | MUL0, - PORTC_9 = 0x29, - PORTC_9_MUL0 = PORTC_9 | MUL0, - PORTC_10 = 0x2A, - PORTC_10_MUL0 = PORTC_10 | MUL0, - PORTC_11 = 0x2B, - PORTC_11_MUL0 = PORTC_11 | MUL0, - PORTC_12 = 0x2C, - PORTC_13 = 0x2D, - PORTC_14 = 0x2E, - PORTC_15 = 0x2F, - - PORTD_0 = 0x30, - PORTD_1 = 0x31, - PORTD_2 = 0x32, - PORTD_3 = 0x33, - PORTD_4 = 0x34, - PORTD_5 = 0x35, - PORTD_6 = 0x36, - PORTD_7 = 0x37, - PORTD_8 = 0x38, - PORTD_9 = 0x39, - PORTD_10 = 0x3A, - PORTD_11 = 0x3B, - PORTD_12 = 0x3C, - PORTD_13 = 0x3D, - PORTD_14 = 0x3E, - PORTD_15 = 0x3F, - - PORTE_0 = 0x40, - PORTE_1 = 0x41, - PORTE_2 = 0x42, - PORTE_3 = 0x43, - PORTE_4 = 0x44, - PORTE_5 = 0x45, - PORTE_6 = 0x46, - PORTE_7 = 0x47, - PORTE_8 = 0x48, - PORTE_9 = 0x49, - PORTE_10 = 0x4A, - PORTE_11 = 0x4B, - PORTE_12 = 0x4C, - PORTE_13 = 0x4D, - PORTE_14 = 0x4E, - PORTE_15 = 0x4F, - - /* ADC internal channels */ - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - - - /* Arduino connector namings */ - A0 = PORTC_0, - A1 = PORTC_1, - A2 = PORTC_2, - A3 = PORTC_3, - A4 = PORTC_4, - A5 = PORTC_5, - D0 = PORTC_11, - D1 = PORTC_10, - D2 = PORTB_12, - D3 = PORTD_12, - D4 = PORTC_8, - D5 = PORTC_7, - D6 = PORTB_0, - D7 = PORTC_12, - D8 = PORTD_13, - D9 = PORTA_8, - D10 = PORTA_1, - D11 = PORTB_15, - D12 = PORTB_14, - D13 = PORTB_13, - D14 = PORTB_9, - D15 = PORTB_8, - - LED1 = PORTA_0, - LED2 = PORTB_1, - LED3 = PORTE_6, - - KEY1 = PORTE_0, - KEY2 = PORTE_1, - - BUTTON1 = KEY1, - BUTTON2 = KEY2, - - SERIAL_TX = PORTA_2, - SERIAL_RX = PORTA_3, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, - - I2C_SCL = D15, - I2C_SDA = D14, - SPI_MOSI = D11, - SPI_MISO = D12, - SPI_SCK = D13, - SPI_CS = D10, - PWM_OUT = D9, - - USB_FS_DM = PORTA_11, - USB_FS_DP = PORTA_12, - USB_FS_ID = PORTA_10, - USB_FS_VBUS = PORTA_9, - - NC = (int)0xFFFFFFFF -} PinName; - -/* BIT[7:4] port number (0=PORTA, 1=PORTB, 2=PORTC, 3=PORTD, 4=PORTE) - BIT[3:0] pin number */ -#define GD_PORT_GET(X) (((uint32_t)(X) >> 4) & 0xF) -#define GD_PIN_GET(X) (((uint32_t)(X) & 0xF)) - -/* Get mode,speed,remap function,channel of GPIO pin */ -#define GD_PIN_MODE_GET(X) (X & 0x07) -#define GD_PIN_SPEED_GET(X) ((X >> 9) & 0x03) -#define GD_PIN_REMAP_GET(X) ((X >> 3) & 0x3F) -#define GD_PIN_CHANNEL_GET(X) ((X >> 11) & 0x1F) - -/* Defines GPIO pin direction */ -typedef enum { - PIN_INPUT = 0, - PIN_OUTPUT -} PinDirection; - -/* Defines mode types of GPIO pin */ -typedef enum { - MODE_AIN = 0, - MODE_IN_FLOATING, - MODE_IPD, - MODE_IPU, - MODE_OUT_OD, - MODE_OUT_PP, - MODE_AF_OD, - MODE_AF_PP, - PullDefault = MODE_IN_FLOATING, - PullUp = MODE_IPU, - PullDown = MODE_IPD, - PullNone = 11 -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/analogin_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/analogin_api.c deleted file mode 100644 index 4c78bb8776c..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/analogin_api.c +++ /dev/null @@ -1,180 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "mbed_error.h" - -#define DEV_ADC_ACCURACY_12BIT 0xFFF -#define DEV_ADC_PRECISION_12TO16(val) ((val << 4)| ((val >> 8) & (uint16_t)0x000F)) -#define AND_NUMBER (0xFF) - -FlagStatus temperature_sample_flag = RESET; - -/** software delay - * - * @param time The time need to delay - */ -static void _delay(uint16_t time) -{ - uint16_t i; - for (i = 0; i < time; i++) { - } -} - -/** Initialize the analogin peripheral - * - * Configures the pin used by analogin. - * @param obj The analogin object to initialize - * @param pin The analogin pin name - */ -void analogin_init(analogin_t *obj, PinName pin) -{ - uint32_t periph; - - MBED_ASSERT(obj); - - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - uint32_t function = pinmap_function(pin, PinMap_ADC); - MBED_ASSERT(function != (uint32_t)NC); - - obj->channel = GD_PIN_CHANNEL_GET(function); - MBED_ASSERT(obj->channel <= ADC_CHANNEL_17); - - periph = obj->adc; - /* save the pin for future use */ - obj->pin = pin; - - /* ADC clock enable and pin number reset */ - switch (periph) { - case ADC0: - rcu_periph_clock_enable(RCU_ADC0); - break; - - case ADC1: - rcu_periph_clock_enable(RCU_ADC1); - /* reset pin number */ - pin = (PinName)(pin & AND_NUMBER); - break; - } - - /* ADC clock cannot be greater than 40M */ - rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV4); - - if ((ADC_CHANNEL_16 == obj->channel)) { - /* ADC Vrefint enable */ - adc_tempsensor_vrefint_enable(); - /* set temperature sample flag */ - temperature_sample_flag = SET; - } - if ((ADC_CHANNEL_17 == obj->channel)) { - /* ADC Vrefint enable */ - adc_tempsensor_vrefint_enable(); - } - - /* when pin >= ADC_TEMP, it indicates that the channel has no external pins */ - if (pin < ADC_TEMP) { - pinmap_pinout(pin, PinMap_ADC); - } - - /* ADC configuration */ - adc_special_function_config(obj->adc, ADC_SCAN_MODE, DISABLE); - adc_special_function_config(obj->adc, ADC_CONTINUOUS_MODE, DISABLE); - /* ADC trigger config */ - adc_external_trigger_source_config(obj->adc, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); - /* ADC mode config */ - adc_mode_config(ADC_MODE_FREE); - /* ADC data alignment config */ - adc_data_alignment_config(obj->adc, ADC_DATAALIGN_RIGHT); - /* ADC channel length config */ - adc_channel_length_config(obj->adc, ADC_REGULAR_CHANNEL, 1); - - if (temperature_sample_flag == SET) { - /* sample temperature needs more time */ - adc_regular_channel_config(obj->adc, 0, obj->channel, ADC_SAMPLETIME_239POINT5); - /* clear temperature sample flag */ - temperature_sample_flag = RESET; - } else { - adc_regular_channel_config(obj->adc, 0, obj->channel, ADC_SAMPLETIME_28POINT5); - } - adc_external_trigger_config(obj->adc, ADC_REGULAR_CHANNEL, ENABLE); - - /* ADC enable */ - adc_enable(obj->adc); - /* wait for ADC to stabilize */ - _delay(500); - adc_calibration_enable(obj->adc); -} - -/** Read the value from analogin pin, represented as an unsigned 16bit value - * - * @param obj The analogin object - * @return An unsigned 16bit value representing the current input voltage - */ -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t reval; - - adc_flag_clear(obj->adc, ADC_FLAG_EOC); - /* start Conversion */ - adc_software_trigger_enable(obj->adc, ADC_REGULAR_CHANNEL); - - while (SET != adc_flag_get(obj->adc, ADC_FLAG_EOC)) { - } - /* ADC actual accuracy is 12 bits */ - reval = adc_regular_data_read(obj->adc); - - reval = DEV_ADC_PRECISION_12TO16(reval); - - return reval; -} - -/** Read the input voltage, represented as a float in the range [0.0, 1.0] - * - * @param obj The analogin object - * @return A floating value representing the current input voltage - */ -float analogin_read(analogin_t *obj) -{ - uint16_t reval; - - adc_flag_clear(obj->adc, ADC_FLAG_EOC); - /* start Conversion */ - adc_software_trigger_enable(obj->adc, ADC_REGULAR_CHANNEL); - /* wait for conversion to complete */ - while (SET != adc_flag_get(obj->adc, ADC_FLAG_EOC)) { - } - /* ADC actual accuracy is 12 bits */ - reval = adc_regular_data_read(obj->adc); - - return (float)reval * (1.0f / (float)DEV_ADC_ACCURACY_12BIT); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif /* DEVICE_ANALOGIN */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/analogout_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/analogout_api.c deleted file mode 100644 index 34e0de20561..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/analogout_api.c +++ /dev/null @@ -1,166 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogout_api.h" -#include "mbed_assert.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -/* 12bit */ -#define DEV_DAC_ACCURACY_12BIT (0xFFF) -#define DEV_DAC_BITS (12) - -/** Initialize the analogout peripheral - * - * Configures the pin used by analogout. - * @param obj The analogout object to initialize - * @param pin The analogout pin name - */ -void analogout_init(dac_t *obj, PinName pin) -{ - /* get the peripheral name from the pin and assign it to the object */ - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(obj->dac != (DACName)NC); - - /* get the pin function and assign the used channel to the object */ - uint32_t function = pinmap_function(pin, PinMap_DAC); - MBED_ASSERT(function != (uint32_t)NC); - - obj->channel = GD_PIN_CHANNEL_GET(function); - MBED_ASSERT(obj->channel <= DAC1); - - /* configure GPIO */ - pinmap_pinout(pin, PinMap_DAC); - - /* save the pin for future use */ - obj->pin = pin; - - /* enable DAC clock */ - rcu_periph_clock_enable(RCU_DAC); - - /* configure DAC */ - dac_wave_mode_config(obj->channel, DAC_WAVE_DISABLE); - dac_trigger_disable(obj->channel); - dac_output_buffer_enable(obj->channel); - analogout_write_u16(obj, 0); -} - -/** Release the analogout object - * - * Note: This is not currently used in the mbed-drivers - * @param obj The analogout object - */ -void analogout_free(dac_t *obj) -{ - /* Reset DAC and disable clock */ - dac_deinit(); - rcu_periph_clock_disable(RCU_DAC); - - /* configure GPIO */ - /* get the pin function and assign the used channel to the object */ - uint32_t function = pinmap_function(obj->pin, PinMap_DAC); - MBED_ASSERT(function != (uint32_t)NC); - - pin_function(obj->pin, function); -} - -/** set the output voltage with specified as a integer - * - * @param obj The analogin object - * @param value The integer-point output voltage to be set - */ -static inline void dev_dac_data_set(dac_t *obj, int value) -{ - dac_data_set(obj->channel, DAC_ALIGN_12B_R, (value & DEV_DAC_ACCURACY_12BIT)); - - dac_enable(obj->channel); - - dac_software_trigger_enable(obj->channel); -} - -/** get the current DAC data - * - * @param obj The analogin object - * @return DAC data - */ -static inline int dev_dac_data_get(dac_t *obj) -{ - return (int)dac_output_value_get(obj->channel); -} - -/** Set the output voltage, specified as a percentage (float) - * - * @param obj The analogin object - * @param value The floating-point output voltage to be set - */ -void analogout_write(dac_t *obj, float value) -{ - if (value < 0.0f) { - /* when the value is less than 0.0, set DAC output date to 0 */ - dev_dac_data_set(obj, 0); - } else if (value > 1.0f) { - /* when the value is more than 1.0, set DAC output date to 0xFFF */ - dev_dac_data_set(obj, (int)DEV_DAC_ACCURACY_12BIT); - } else { - dev_dac_data_set(obj, (int)(value * (float)DEV_DAC_ACCURACY_12BIT)); - } -} - -/** Set the output voltage, specified as unsigned 16-bit - * - * @param obj The analogin object - * @param value The unsigned 16-bit output voltage to be set - */ -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - dev_dac_data_set(obj, value >> (16 - DEV_DAC_BITS)); -} - -/** Read the current voltage value on the pin - * - * @param obj The analogin object - * @return A floating-point value representing the current voltage on the pin, - * measured as a percentage - */ -float analogout_read(dac_t *obj) -{ - uint32_t ret_val = dev_dac_data_get(obj); - return (float)ret_val * (1.0f / (float)DEV_DAC_ACCURACY_12BIT); -} - -/** Read the current voltage value on the pin, as a normalized unsigned 16bit value - * - * @param obj The analogin object - * @return An unsigned 16-bit value representing the current voltage on the pin - */ -uint16_t analogout_read_u16(dac_t *obj) -{ - uint32_t ret_val = dev_dac_data_get(obj); - return (ret_val << 4) | ((ret_val >> 8) & 0x000F); -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} - -#endif /* DEVICE_ANALOGOUT */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/can_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/can_api.c deleted file mode 100644 index 1b7bfe07549..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/can_api.c +++ /dev/null @@ -1,643 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "can_api.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "mbed_error.h" - -#if DEVICE_CAN - -/* BS1[3:0] + 1 + BS2[2:0] + 1 */ -#define DEV_CAN_BT_SEG_MAX 24 -#define DEV_CAN_BT_SEG_MIN 4 - -/* CAN related register mask */ -#define DEV_CAN_BS1_MASK 0x000F0000 -#define DEV_CAN_BS2_MASK 0x00700000 -#define DEV_CAN_BAUDPSC_MASK 0x000003FF -#define DEV_CAN_SJW_MASK 0x03000000 -/* CAN0 interrupt vector number */ -#define CAN0_IRQ_BASE_NUM 19 - -/* CAN1 interrupt vector number */ -#define CAN1_IRQ_BASE_NUM 63 - -static uint32_t can_irq_ids[2] = {0}; -static can_irq_handler irq_callback; - -/** CAN interrupt handle . - * - * @param can_periph CAN0 or CAN1. - * @param id the CANx index . - */ -static void dev_can_irq_handle(uint32_t periph, int id) -{ - uint32_t flag0 = 0, flag1 = 0, flag2 = 0; - - flag0 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF0); - flag1 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF1); - flag2 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF2); - - if (flag0) { - can_flag_clear(periph, CAN_FLAG_MTF0); - } - if (flag1) { - can_flag_clear(periph, CAN_FLAG_MTF1); - } - if (flag2) { - can_flag_clear(periph, CAN_FLAG_MTF2); - } - - /* CAN transmit complete interrupt handle */ - if (flag0 || flag1 || flag2) { - irq_callback(can_irq_ids[id], IRQ_TX); - } - - /* CAN receive complete interrupt handle */ - if (CAN_INTEN_RFNEIE0 == (CAN_INTEN(periph) & CAN_INTEN_RFNEIE0)) { - if (0 != can_receive_message_length_get(periph, CAN_FIFO0)) { - irq_callback(can_irq_ids[id], IRQ_RX); - } - } - - /* CAN error interrupt handle */ - if (SET == can_interrupt_flag_get(periph, CAN_INT_FLAG_ERRIF)) { - /* passive error interrupt handle */ - if (CAN_INTEN_PERRIE == (CAN_INTEN(periph) & CAN_INTEN_PERRIE)) { - if (SET == can_flag_get(periph, CAN_FLAG_PERR)) { - irq_callback(can_irq_ids[id], IRQ_PASSIVE); - } - } - - /* bus-off interrupt handle */ - if (CAN_INTEN_BOIE == (CAN_INTEN(periph) & CAN_INTEN_BOIE)) { - if (SET == can_flag_get(periph, CAN_FLAG_BOERR)) { - irq_callback(can_irq_ids[id], IRQ_BUS); - } - } - - irq_callback(can_irq_ids[id], IRQ_ERROR); - } -} - -/** CAN1 Interrupt Request entry . - * - */ -static void dev_can0_irq_entry(void) -{ - dev_can_irq_handle(CAN0, 0); -} - -/** CAN1 Interrupt Request entry . - * - */ -static void dev_can1_irq_entry(void) -{ - dev_can_irq_handle(CAN1, 1); -} - -/** Config the CAN mode . - * - * @param can_periph CAN0 or CAN1. - * @param mode the mode to be set. - */ -static void dev_can_mode_config(uint32_t can_periph, uint32_t mode) -{ - /* enter the initialization mode, only in initialization mode CAN register can be configured */ - can_working_mode_set(can_periph, CAN_MODE_INITIALIZE); - - CAN_BT(can_periph) &= ~BT_MODE(3); - CAN_BT(can_periph) |= BT_MODE(mode); - - /* enter the normal mode */ - can_working_mode_set(can_periph, CAN_MODE_NORMAL); -} - -/** Config the interrupt . - * - * @param can_periph CAN0 or CAN1. - * @param interrupt The interrupt type. - * @param enable enable or disable. - */ -static void dev_can_interrupt_config(uint32_t can_periph, uint32_t interrupt, uint32_t enable) -{ - if (enable) { - can_interrupt_enable(can_periph, interrupt); - } else { - can_interrupt_disable(can_periph, interrupt); - } -} - -/* This table can be used to calculate bit time -The first value is bit segment 1(BS1[3:0]), the second is bit segment 2(BS2[2:0]) */ -static const int sampling_points[23][2] = { - {0x0, 0x0}, /* 2, 50% */ - {0x1, 0x0}, /* 3, 67% */ - {0x2, 0x0}, /* 4, 75% */ - {0x3, 0x0}, /* 5, 80% */ - {0x3, 0x1}, /* 6, 67% */ - {0x4, 0x1}, /* 7, 71% */ - {0x5, 0x1}, /* 8, 75% */ - {0x6, 0x1}, /* 9, 78% */ - {0x6, 0x2}, /* 10, 70% */ - {0x7, 0x2}, /* 11, 73% */ - {0x8, 0x2}, /* 12, 75% */ - {0x9, 0x2}, /* 13, 77% */ - {0x9, 0x3}, /* 14, 71% */ - {0xA, 0x3}, /* 15, 73% */ - {0xB, 0x3}, /* 16, 75% */ - {0xC, 0x3}, /* 17, 76% */ - {0xD, 0x3}, /* 18, 78% */ - {0xD, 0x4}, /* 19, 74% */ - {0xE, 0x4}, /* 20, 75% */ - {0xF, 0x4}, /* 21, 76% */ - {0xF, 0x5}, /* 22, 73% */ - {0xF, 0x6}, /* 23, 70% */ - {0xF, 0x7}, /* 24, 67% */ -}; - -/** Set the baudrate. - * - * @param freq The frequency value to be set. - * - * @returns - * CAN_BT register value - */ -static unsigned int dev_can_baudrate_set(int freq) -{ - uint32_t reval; - uint16_t baud_psc; - uint16_t baud_psc_max; - uint32_t temp; - uint32_t bt_reg_config; - uint8_t flag; - int bits; - - flag = 0; - - /* computes the value that the CAN_BT register needs to be configured */ - /* (BAUDPSC[9:0] + 1) * ((BS1[3:0] + 1) + (BS2[2:0] + 1) + SJW(always 1)) */ - bt_reg_config = (rcu_clock_freq_get(CK_APB1) / freq); - /* BAUDPSC[9:0] minimum value */ - baud_psc = bt_reg_config / DEV_CAN_BT_SEG_MAX; - /* BAUDPSC[9:0] maximum value */ - baud_psc_max = bt_reg_config / DEV_CAN_BT_SEG_MIN; - - while ((!flag) && (baud_psc < baud_psc_max)) { - baud_psc++; - for (bits = 22; bits > 0; bits--) { - temp = (bits + 3) * (baud_psc + 1); - if (temp == bt_reg_config) { - flag = 1; - break; - } - } - } - - if (flag) { - reval = ((sampling_points[bits][1] << 20) & DEV_CAN_BS2_MASK) - | ((sampling_points[bits][0] << 16) & DEV_CAN_BS1_MASK) - | ((1 << 24) & DEV_CAN_SJW_MASK) - | ((baud_psc << 0) & DEV_CAN_BAUDPSC_MASK); - } else { - /* CAN_BT register reset value */ - reval = 0x01230000; - } - - return reval; -} - -/** init the CAN. - * - */ -void can_init(can_t *obj, PinName rd, PinName td) -{ - can_init_freq(obj, rd, td, 500000); -} - -/** init the CAN frequency. - * - * @param rd receive pin. - * @param td transmit pin. - * @param hz The bus frequency in hertz. - */ -void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) -{ - CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); - CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); - obj->can = (CANName)pinmap_merge(can_rd, can_td); - - MBED_ASSERT((int)obj->can != NC); - - if (obj->can == CAN_0) { - rcu_periph_clock_enable(RCU_CAN0); - can_deinit(obj->can); - obj->index = 0; - } else if (obj->can == CAN_1) { - rcu_periph_clock_enable(RCU_CAN0); - rcu_periph_clock_enable(RCU_CAN1); - can_deinit(obj->can); - obj->index = 1; - } else { - return; - } - - /* Configure the CAN pins */ - pinmap_pinout(rd, PinMap_CAN_RD); - pinmap_pinout(td, PinMap_CAN_TD); - if (rd != NC) { - pin_mode(rd, PullUp); - } - if (td != NC) { - pin_mode(td, PullUp); - } - - dev_can_mode_config(obj->can, CAN_NORMAL_MODE); - - can_frequency(obj, hz); - - if (obj->can == CAN_0) { - can_filter(obj, 0, 0, CANStandard, 0); - } else { - can_filter(obj, 0, 0, CANStandard, 14); - } -} - -/** disable CAN. - * - */ -void can_free(can_t *obj) -{ - can_deinit(obj->can); - - if (obj->can == CAN0) { - rcu_periph_clock_disable(RCU_CAN0); - } - - if (obj->can == CAN1) { - rcu_periph_clock_disable(RCU_CAN1); - } -} - -/** Set the frequency of the CAN interface. - * - * @param hz The bus frequency in hertz. - * - * @returns - * 1 if successful, - * 0 otherwise - */ -int can_frequency(can_t *obj, int hz) -{ - int reval = 0; - - /* The maximum baud rate support to 1M */ - if (hz <= 1000000) { - if (SUCCESS == can_working_mode_set(obj->can, CAN_MODE_INITIALIZE)) { - CAN_BT(obj->can) = dev_can_baudrate_set(hz); - } else { - error("the configuration of can frequency is out of range \r\n"); - } - - if (SUCCESS == can_working_mode_set(obj->can, CAN_MODE_NORMAL)) { - reval = 1; - } else { - reval = 0; - } - } - - return reval; -} - -/** init the interrupt. - * - * @param handler the interrupt callback. - * @param id the CANx index. - */ -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) -{ - irq_callback = handler; - can_irq_ids[obj->index] = id; -} - -/** disable the interrupt. - * - */ -void can_irq_free(can_t *obj) -{ - if (CAN0 == obj->can) { - can_interrupt_disable(obj->can, CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 | \ - CAN_INTEN_PERRIE | CAN_INTEN_BOIE | CAN_INTEN_ERRIE); - } - - if (CAN1 == obj->can) { - can_interrupt_disable(obj->can, CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 | \ - CAN_INTEN_PERRIE | CAN_INTEN_BOIE | CAN_INTEN_ERRIE); - } - - can_irq_ids[obj->index] = 0; -} - -/** Set the interrupt handle. - * - * @param type The interrupt type. - * @param enable enable or disable. - */ -void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) -{ - uint32_t irq_num; - uint32_t vector = 0; - - if (obj->can == CAN_0) { - vector = (uint32_t)dev_can0_irq_entry; - irq_num = CAN0_IRQ_BASE_NUM; - } - - else if (obj->can == CAN_1) { - vector = (uint32_t)dev_can1_irq_entry; - irq_num = CAN1_IRQ_BASE_NUM; - } - - switch (type) { - case IRQ_RX: - dev_can_interrupt_config(obj->can, CAN_INT_RFNE0, enable); - break; - case IRQ_TX: - dev_can_interrupt_config(obj->can, CAN_INT_TME, enable); - irq_num += 1; - break; - case IRQ_ERROR: - dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_ERRN, enable); - irq_num += 3; - break; - case IRQ_PASSIVE: - dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_PERR, enable); - irq_num += 3; - break; - case IRQ_BUS: - dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_BO, enable); - irq_num += 3; - break; - default: - return; - } - - NVIC_SetVector((IRQn_Type)irq_num, vector); - NVIC_EnableIRQ((IRQn_Type)irq_num); -} - -/** Write a CANMessage to the bus. - * - * @param msg The CANMessage to write. - * - * @returns - * 0 if write failed, - * 1 if write was successful - */ -int can_write(can_t *obj, CAN_Message msg, int cc) -{ - can_trasnmit_message_struct transmit_message; - uint32_t i; - - can_struct_para_init(CAN_TX_MESSAGE_STRUCT, &transmit_message); - /* configure frame type: data or remote */ - if (CANData == msg.type) { - transmit_message.tx_ft = CAN_FT_DATA; - } else if (CANRemote == msg.type) { - transmit_message.tx_ft = CAN_FT_REMOTE; - } else { - error("frame type of transmit message is invalid \r\n"); - } - - /* configure frame format: standard or extended */ - if (CANStandard == msg.format) { - transmit_message.tx_ff = CAN_FF_STANDARD; - transmit_message.tx_sfid = msg.id; - } else if (CANExtended == msg.format) { - transmit_message.tx_ff = CAN_FF_EXTENDED; - transmit_message.tx_efid = msg.id; - } else { - error("frame format of transmit message is invalid \r\n"); - } - - transmit_message.tx_dlen = msg.len; - - for (i = 0; i < msg.len; i++) { - transmit_message.tx_data[i] = msg.data[i]; - } - - can_message_transmit(obj->can, &transmit_message); - - return 1; -} - -/** Read a CANMessage from the bus. - * - * @param msg A CANMessage to read to. - * @param handle message filter handle (0 for any message). - * - * @returns - * 0 if no message arrived, - * 1 if message arrived - */ -int can_read(can_t *obj, CAN_Message *msg, int handle) -{ - uint8_t i; - uint8_t fifo_number; - - fifo_number = (uint8_t)handle; - can_receive_message_struct receive_message; - - /* if the frame is not received, retrun 0 */ - if (0 == can_receive_message_length_get(obj->can, CAN_FIFO0)) { - return 0; - } - - can_message_receive(obj->can, fifo_number, &receive_message); - - if (receive_message.rx_ff == CAN_RFIFOMI_FF) { - msg->format = CANExtended; - } else { - msg->format = CANStandard; - } - - if (0 == msg->format) { - msg->id = (uint32_t)0x000007FF & (receive_message.rx_sfid); - } else { - msg->id = (uint32_t)0x1FFFFFFF & (receive_message.rx_efid); - } - - if (receive_message.rx_ft == CAN_RFIFOMI_FT) { - msg->type = CANRemote; - } else { - msg->type = CANData; - } - - msg->len = (uint8_t)receive_message.rx_dlen; - - for (i = 0; i < msg->len; i++) { - msg->data[i] = (uint8_t)receive_message.rx_data[i]; - } - /* If the frame is received successfully, retrun 1 */ - return 1; -} - -/** Change CAN operation to the specified mode. - * - * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest). - * - * @returns - * 0 if mode change failed or unsupported, - * 1 if mode change was successful - */ -int can_mode(can_t *obj, CanMode mode) -{ - switch (mode) { - case MODE_NORMAL: - dev_can_mode_config(obj->can, CAN_NORMAL_MODE); - break; - case MODE_SILENT: - dev_can_mode_config(obj->can, CAN_SILENT_MODE); - break; - case MODE_TEST_GLOBAL: - case MODE_TEST_LOCAL: - dev_can_mode_config(obj->can, CAN_LOOPBACK_MODE); - break; - case MODE_TEST_SILENT: - dev_can_mode_config(obj->can, CAN_SILENT_LOOPBACK_MODE); - break; - default: - return 0; - } - - return 1; -} - -/** Filter out incomming messages. - * - * @param id the id to filter on. - * @param mask the mask applied to the id. - * @param format format to filter on (Default CANAny). - * @param handle message filter handle (Optional). - * - * @returns - * 0 if filter change failed or unsupported, - * new filter handle if successful - */ -int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) -{ - can_filter_parameter_struct can_filter; - - can_filter.filter_number = handle; - can_filter.filter_mode = CAN_FILTERMODE_MASK; - can_filter.filter_bits = CAN_FILTERBITS_32BIT; - can_filter.filter_fifo_number = CAN_FIFO0; - can_filter.filter_enable = ENABLE; - - switch (format) { - case CANStandard: - /* configure SFID[10:0] */ - can_filter.filter_list_high = id << 5; - can_filter.filter_list_low = 0x0; - /* configure SFID[10:0] mask */ - can_filter.filter_mask_high = mask << 5; - /* both data and remote frames can be received */ - can_filter.filter_mask_low = 0x0; - - break; - - case CANExtended: - /* configure EFID[28:13] */ - can_filter.filter_list_high = id >> 13; - /* configure EFID[12:0] and frame format bit set */ - can_filter.filter_list_low = (id << 3) | (1 << 2); - /* configure EFID[28:13] mask */ - can_filter.filter_mask_high = mask >> 13; - /* configure EFID[12:0] and frame format bit mask */ - /* both data and remote frames can be received */ - can_filter.filter_mask_low = (mask << 3) | (1 << 2); - - break; - - case CANAny: - error("CANAny mode is not supported \r\n"); - return 0; - - default: - error("parameter is not supported \r\n"); - return 0; - } - - can_filter_init(&can_filter); - can1_filter_start_bank(handle); - - return handle; -} - -/** Reset CAN interface. - * - * To use after error overflow. - */ -void can_reset(can_t *obj) -{ - can_deinit(obj->can); -} - -/** Detects read errors - Used to detect read overflow errors. - * - * @returns number of read errors - */ -unsigned char can_rderror(can_t *obj) -{ - return can_receive_error_number_get(obj->can); -} - -/** Detects write errors - Used to detect write overflow errors. - * - * @returns number of write errors - */ -unsigned char can_tderror(can_t *obj) -{ - return can_transmit_error_number_get(obj->can); -} - -/** Puts or removes the CAN interface into silent monitoring mode. - * - * @param silent boolean indicating whether to go into silent mode or not. - */ -void can_monitor(can_t *obj, int silent) -{ - if (silent) { - dev_can_mode_config(obj->can, CAN_SILENT_MODE); - } else { - dev_can_mode_config(obj->can, CAN_NORMAL_MODE); - } -} - -const PinMap *can_rd_pinmap() -{ - return PinMap_CAN_TD; -} - -const PinMap *can_td_pinmap() -{ - return PinMap_CAN_RD; -} - -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device.h deleted file mode 100644 index ceedbdd7469..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device.h +++ /dev/null @@ -1,27 +0,0 @@ -/* The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. */ -/* Check the 'features' section of the target description in 'targets.json' for more details. */ -/* mbed Microcontroller Library -* Copyright (c) 2006-2018 ARM Limited -* -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 24 - -#include "objects.h" - -#endif /* MBED_DEVICE_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_MICRO/gd32e103vb.sct b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_MICRO/gd32e103vb.sct deleted file mode 100644 index 44128a0c700..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_MICRO/gd32e103vb.sct +++ /dev/null @@ -1,49 +0,0 @@ -#! armcc -E -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ***** - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x00020000 -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00008000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150) -#define VECTOR_SIZE 0x150 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_MICRO/startup_gd32e10x.S b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_MICRO/startup_gd32e10x.S deleted file mode 100644 index 903cd6fa28a..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_MICRO/startup_gd32e10x.S +++ /dev/null @@ -1,336 +0,0 @@ -;/*! -; \file startup_gd32f30x_cl.S -; \brief start up file -; -; \version 2017-12-26, V1.0.0, firmware for GD32E10x -; \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; 64:EXMC - DCD 0 ; Reserved - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD 0 ; 77:Reserved - DCD 0 ; 78:Reserved - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_CTC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT CAN0_TX_IRQHandler [WEAK] - EXPORT CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] - EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBFS_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] - EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_EWMC_IRQHandler [WEAK] - EXPORT USBFS_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_CTC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -CAN0_TX_IRQHandler -CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_TIMER8_IRQHandler -TIMER0_UP_TIMER9_IRQHandler -TIMER0_TRG_CMT_TIMER10_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBFS_WKUP_IRQHandler -TIMER7_BRK_TIMER11_IRQHandler -TIMER7_UP_TIMER12_IRQHandler -TIMER7_TRG_CMT_TIMER13_IRQHandler -TIMER7_Channel_IRQHandler -EXMC_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_EWMC_IRQHandler -USBFS_IRQHandler - - B . - ENDP - - ALIGN - - END diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_STD/gd32e103vb.sct b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_STD/gd32e103vb.sct deleted file mode 100644 index e65ee253f78..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_STD/gd32e103vb.sct +++ /dev/null @@ -1,36 +0,0 @@ -#! armcc -E -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ***** - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x20000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K) - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150) - RW_IRAM1 (0x20000000+0x150) (0x8000-0x150-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down - } -} - diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_STD/startup_gd32e10x.S b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_STD/startup_gd32e10x.S deleted file mode 100644 index 0ccb137ff34..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_ARM_STD/startup_gd32e10x.S +++ /dev/null @@ -1,335 +0,0 @@ -;/*! -; \file startup_gd32e10x.s -; \brief start up file -; -; \version 2017-12-26, V1.0.0, firmware for GD32E10x -; \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; 64:EXMC - DCD 0 ; Reserved - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD 0 ; 77:Reserved - DCD 0 ; 78:Reserved - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_CTC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT CAN0_TX_IRQHandler [WEAK] - EXPORT CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] - EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBFS_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] - EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_EWMC_IRQHandler [WEAK] - EXPORT USBFS_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_CTC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -CAN0_TX_IRQHandler -CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_TIMER8_IRQHandler -TIMER0_UP_TIMER9_IRQHandler -TIMER0_TRG_CMT_TIMER10_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBFS_WKUP_IRQHandler -TIMER7_BRK_TIMER11_IRQHandler -TIMER7_UP_TIMER12_IRQHandler -TIMER7_TRG_CMT_TIMER13_IRQHandler -TIMER7_Channel_IRQHandler -EXMC_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_EWMC_IRQHandler -USBFS_IRQHandler - - B . - ENDP - - ALIGN - - END diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_GCC_ARM/GD32E103xB.ld b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_GCC_ARM/GD32E103xB.ld deleted file mode 100644 index 6a01b089bda..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_GCC_ARM/GD32E103xB.ld +++ /dev/null @@ -1,136 +0,0 @@ -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 128K -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* specify memory regions */ -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = 0x20000150, LENGTH = 32K - 0x150 -} - -/* define output sections */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* initializes stack on the end of block */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_GCC_ARM/startup_gd32e10x.S b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_GCC_ARM/startup_gd32e10x.S deleted file mode 100644 index 0ed7d02d564..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_GCC_ARM/startup_gd32e10x.S +++ /dev/null @@ -1,408 +0,0 @@ -;/*! -; \file startup_gd32e10x_cl.S -; \brief start up file -; -; \version 2017-12-26, V1.0.0, firmware for GD32E10x -; \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -.syntax unified -.cpu cortex-m4 -.fpu softvfp -.thumb - -.global VecTab -.global Default_Handler - -/* start address of the initialization .data */ -.word _sidata -/* start address of the .data section */ -.word _sdata -/* end address of the .data section */ -.word _edata - -/* reset Handler */ - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* copy the data segment into RAM */ - movs r1, #0 - b DataInit - -CopyData: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -DataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyData - -/* system clock intitialization*/ - bl SystemInit -/* static constructors */ -// bl __libc_init_array -/* jump to application's entry point */ -// bl main - bl _start -/* infinite loop */ - b . - - -.size Reset_Handler, .-Reset_Handler - - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -/* infinite loop */ - b . - .size Default_Handler, .-Default_Handler - - .section .isr_vector,"a",%progbits - .type VecTab, %object - .size VecTab, .-VecTab - - -VecTab: - - .word _estack /* Top of Stack */ - .word Reset_Handler /* 1,Reset Handler */ - .word NMI_Handler /* 2,NMI Handler */ - .word HardFault_Handler /* 3,Hard Fault Handler */ - .word MemManage_Handler /* 4,MPU Fault Handler */ - .word BusFault_Handler /* 5,Bus Fault Handler */ - .word UsageFault_Handler /* 6,Usage Fault Handler */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SVC_Handler /* 11,SVCall Handler */ - .word DebugMon_Handler /* 12,Debug Monitor Handler */ - .word 0 /* Reserved */ - .word PendSV_Handler /* 14,PendSV Handler */ - .word SysTick_Handler /* 15,SysTick Handler */ - /* External Interrupts */ - .word WWDGT_IRQHandler /* 16,Window Watchdog Timer */ - .word LVD_IRQHandler /* 17,LVD through EXTI Line detect */ - .word TAMPER_IRQHandler /* 18,Tamper through EXTI Line detect */ - .word RTC_IRQHandler /* 19,RTC through EXTI Line */ - .word FMC_IRQHandler /* 20,FMC */ - .word RCU_CTC_IRQHandler /* 21,RCU and CTC */ - .word EXTI0_IRQHandler /* 22,EXTI Line 0 */ - .word EXTI1_IRQHandler /* 23,EXTI Line 1 */ - .word EXTI2_IRQHandler /* 24,EXTI Line 2 */ - .word EXTI3_IRQHandler /* 25,EXTI Line 3 */ - .word EXTI4_IRQHandler /* 26,EXTI Line 4 */ - .word DMA0_Channel0_IRQHandler /* 27,DMA0 Channel 0 */ - .word DMA0_Channel1_IRQHandler /* 28,DMA0 Channel 1 */ - .word DMA0_Channel2_IRQHandler /* 29,DMA0 Channel 2 */ - .word DMA0_Channel3_IRQHandler /* 30,DMA0 Channel 3 */ - .word DMA0_Channel4_IRQHandler /* 31,DMA0 Channel 4 */ - .word DMA0_Channel5_IRQHandler /* 32,DMA0 Channel 5 */ - .word DMA0_Channel6_IRQHandler /* 33,DMA0 Channel 6 */ - .word ADC0_1_IRQHandler /* 34,ADC0 and ADC1 */ - .word CAN0_TX_IRQHandler /* 35,CAN0 TX */ - .word CAN0_RX0_IRQHandler /* 36,CAN0 RX0 */ - .word CAN0_RX1_IRQHandler /* 37,CAN0 RX1 */ - .word CAN0_EWMC_IRQHandler /* 38,CAN0 EWMC */ - .word EXTI5_9_IRQHandler /* 39,EXTI5 to EXTI9 */ - .word TIMER0_BRK_TIMER8_IRQHandler /* 40,TIMER0 Break and TIMER8 */ - .word TIMER0_UP_TIMER9_IRQHandler /* 41,TIMER0 Update and TIMER9 */ - .word TIMER0_TRG_CMT_TIMER10_IRQHandler /* 42,TIMER0 Trigger and Commutation and TIMER10 */ - .word TIMER0_Channel_IRQHandler /* 43,TIMER0 Channel Capture Compare */ - .word TIMER1_IRQHandler /* 44,TIMER4 */ - .word TIMER2_IRQHandler /* 45,TIMER2 */ - .word TIMER3_IRQHandler /* 46,TIMER3 */ - .word I2C0_EV_IRQHandler /* 47,I2C0 Event */ - .word I2C0_ER_IRQHandler /* 48,I2C0 Error */ - .word I2C1_EV_IRQHandler /* 49,I2C1 Event */ - .word I2C1_ER_IRQHandler /* 50,I2C1 Error */ - .word SPI0_IRQHandler /* 51,SPI0 */ - .word SPI1_IRQHandler /* 52,SPI1 */ - .word USART0_IRQHandler /* 53,USART0 */ - .word USART1_IRQHandler /* 54,USART1 */ - .word USART2_IRQHandler /* 55,USART2 */ - .word EXTI10_15_IRQHandler /* 56,EXTI10 to EXTI15 */ - .word RTC_Alarm_IRQHandler /* 57,RTC Alarm */ - .word USBFS_WKUP_IRQHandler /* 58,USBFS Wakeup */ - .word TIMER7_BRK_TIMER11_IRQHandler /* 59,TIMER7 Break and TIMER11 */ - .word TIMER7_UP_TIMER12_IRQHandler /* 60:TIMER7 Update and TIMER12 */ - .word TIMER7_TRG_CMT_TIMER13_IRQHandler /* 61:TIMER7 Trigger and Commutation and TIMER13 */ - .word TIMER7_Channel_IRQHandler /* 62,TIMER7 Capture Compare */ - .word 0 /* Reserved */ - .word EXMC_IRQHandler /* 64,EXMC */ - .word 0 /* Reserved */ - .word TIMER4_IRQHandler /* 66,TIMER4 */ - .word SPI2_IRQHandler /* 67,SPI2 */ - .word UART3_IRQHandler /* 68,UART3 */ - .word UART4_IRQHandler /* 69,UART4 */ - .word TIMER5_IRQHandler /* 70,TIMER5 */ - .word TIMER6_IRQHandler /* 71,TIMER6 */ - .word DMA1_Channel0_IRQHandler /* 72,DMA1 Channel0 */ - .word DMA1_Channel1_IRQHandler /* 73,DMA1 Channel1 */ - .word DMA1_Channel2_IRQHandler /* 74,DMA1 Channel2 */ - .word DMA1_Channel3_IRQHandler /* 75,DMA1 Channel3 */ - .word DMA1_Channel4_IRQHandler /* 76,DMA1 Channel4 */ - .word 0 /* 77,Reserved */ - .word 0 /* 78,Reserved */ - .word CAN1_TX_IRQHandler /* 79,CAN1 TX */ - .word CAN1_RX0_IRQHandler /* 80,CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* 81,CAN1 RX1 */ - .word CAN1_EWMC_IRQHandler /* 82,CAN1 EWMC */ - .word USBFS_IRQHandler /* 83,USBFS */ - -/* dummy Exception Handlers */ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDGT_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak LVD_IRQHandler - .thumb_set LVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak RCU_CTC_IRQHandler - .thumb_set RCU_CTC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA0_Channel0_IRQHandler - .thumb_set DMA0_Channel0_IRQHandler,Default_Handler - - .weak DMA0_Channel1_IRQHandler - .thumb_set DMA0_Channel1_IRQHandler,Default_Handler - - .weak DMA0_Channel2_IRQHandler - .thumb_set DMA0_Channel2_IRQHandler,Default_Handler - - .weak DMA0_Channel3_IRQHandler - .thumb_set DMA0_Channel3_IRQHandler,Default_Handler - - .weak DMA0_Channel4_IRQHandler - .thumb_set DMA0_Channel4_IRQHandler,Default_Handler - - .weak DMA0_Channel5_IRQHandler - .thumb_set DMA0_Channel5_IRQHandler,Default_Handler - - .weak DMA0_Channel6_IRQHandler - .thumb_set DMA0_Channel6_IRQHandler,Default_Handler - - .weak ADC0_1_IRQHandler - .thumb_set ADC0_1_IRQHandler,Default_Handler - - .weak CAN0_TX_IRQHandler - .thumb_set CAN0_TX_IRQHandler,Default_Handler - - .weak CAN0_RX0_IRQHandler - .thumb_set CAN0_RX0_IRQHandler,Default_Handler - - .weak CAN0_RX1_IRQHandler - .thumb_set CAN0_RX1_IRQHandler,Default_Handler - - .weak CAN0_EWMC_IRQHandler - .thumb_set CAN0_EWMC_IRQHandler,Default_Handler - - .weak EXTI5_9_IRQHandler - .thumb_set EXTI5_9_IRQHandler,Default_Handler - - .weak TIMER0_BRK_TIMER8_IRQHandler - .thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler - - .weak TIMER0_UP_TIMER9_IRQHandler - .thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler - - .weak TIMER0_TRG_CMT_TIMER10_IRQHandler - .thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler - - .weak TIMER0_Channel_IRQHandler - .thumb_set TIMER0_Channel_IRQHandler,Default_Handler - - .weak TIMER1_IRQHandler - .thumb_set TIMER1_IRQHandler,Default_Handler - - .weak TIMER2_IRQHandler - .thumb_set TIMER2_IRQHandler,Default_Handler - - .weak TIMER3_IRQHandler - .thumb_set TIMER3_IRQHandler,Default_Handler - - .weak I2C0_EV_IRQHandler - .thumb_set I2C0_EV_IRQHandler,Default_Handler - - .weak I2C0_ER_IRQHandler - .thumb_set I2C0_ER_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak SPI0_IRQHandler - .thumb_set SPI0_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART0_IRQHandler - .thumb_set USART0_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI10_15_IRQHandler - .thumb_set EXTI10_15_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USBFS_WKUP_IRQHandler - .thumb_set USBFS_WKUP_IRQHandler,Default_Handler - - .weak TIMER7_BRK_TIMER11_IRQHandler - .thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler - - .weak TIMER7_UP_TIMER12_IRQHandler - .thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler - - .weak TIMER7_TRG_CMT_TIMER13_IRQHandler - .thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler - - .weak TIMER7_Channel_IRQHandler - .thumb_set TIMER7_Channel_IRQHandler,Default_Handler - - .weak EXMC_IRQHandler - .thumb_set EXMC_IRQHandler,Default_Handler - - .weak TIMER4_IRQHandler - .thumb_set TIMER4_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak UART3_IRQHandler - .thumb_set UART3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak TIMER5_IRQHandler - .thumb_set TIMER5_IRQHandler,Default_Handler - - .weak TIMER6_IRQHandler - .thumb_set TIMER6_IRQHandler,Default_Handler - - .weak DMA1_Channel0_IRQHandler - .thumb_set DMA1_Channel0_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_EWMC_IRQHandler - .thumb_set CAN1_EWMC_IRQHandler,Default_Handler - - .weak USBFS_IRQHandler - .thumb_set USBFS_IRQHandler,Default_Handler diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_IAR/gd32e103vb.icf b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_IAR/gd32e103vb.icf deleted file mode 100644 index b92876d0e14..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_IAR/gd32e103vb.icf +++ /dev/null @@ -1,37 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ - -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x20000; } -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; -define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x2000014F; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000150; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; \ No newline at end of file diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_IAR/startup_gd32e10x.S b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_IAR/startup_gd32e10x.S deleted file mode 100644 index 9bbc5e7ae33..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/TOOLCHAIN_IAR/startup_gd32e10x.S +++ /dev/null @@ -1,517 +0,0 @@ -;/*! -; \file startup_gd32f30x_cl.S -; \brief start up file -; -; \version 2017-12-26, V1.0.0, firmware for GD32E10x -; \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Vector Number 1,Reset Handler - - DCD NMI_Handler ; Vector Number 2,NMI Handler - DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler - DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler - DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler - DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; Vector Number 11,SVCall Handler - DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; Vector Number 14,PendSV Handler - DCD SysTick_Handler ; Vector Number 15,SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD 0 ; 63:Reserved - DCD EXMC_IRQHandler ; 64:EXMC - DCD 0 ; 65:Reserved - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD 0 ; 77:Reserved - DCD 0 ; 78:Reserved - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_CTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_CTC_IRQHandler - B RCU_CTC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_TX_IRQHandler - B CAN0_TX_IRQHandler - - PUBWEAK CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX0_IRQHandler - B CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_TIMER8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_TIMER8_IRQHandler - B TIMER0_BRK_TIMER8_IRQHandler - - PUBWEAK TIMER0_UP_TIMER9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_TIMER9_IRQHandler - B TIMER0_UP_TIMER9_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_TIMER10_IRQHandler - B TIMER0_TRG_CMT_TIMER10_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBFS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_WKUP_IRQHandler - B USBFS_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_TIMER11_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_TIMER11_IRQHandler - B TIMER7_BRK_TIMER11_IRQHandler - - PUBWEAK TIMER7_UP_TIMER12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_TIMER12_IRQHandler - B TIMER7_UP_TIMER12_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_TIMER13_IRQHandler - B TIMER7_TRG_CMT_TIMER13_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_EWMC_IRQHandler - B CAN1_EWMC_IRQHandler - - PUBWEAK USBFS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_IRQHandler - B USBFS_IRQHandler - END \ No newline at end of file diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/cmsis.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/cmsis.h deleted file mode 100644 index 2b920cabeb0..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/cmsis.h +++ /dev/null @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * A generic CMSIS include header - - Copyright (c) 2018, GigaDevice Semiconductor Inc. All rights reserved. - - SPDX-License-Identifier: BSD-3-Clause - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "gd32e10x.h" -#include "cmsis_nvic.h" - -#endif /* MBED_CMSIS_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/cmsis_nvic.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/cmsis_nvic.h deleted file mode 100644 index 3cea459539b..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/cmsis_nvic.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 68) /* ARM CORE:16 Vectors; MCU Peripherals:68 Vectors */ -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 - - -#endif /* MBED_CMSIS_NVIC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/gd32e10x.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/gd32e10x.h deleted file mode 100644 index ec94545ff41..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/gd32e10x.h +++ /dev/null @@ -1,283 +0,0 @@ -/*! - \file gd32e10x.h - \brief general definitions for GD32E10x - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_H -#define GD32E10X_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* define GD32E10X */ -#if !defined (GD32E10X) -#define GD32E10X -#endif /* define GD32E10x */ -#if !defined (GD32E10X) -#error "Please select the target GD32E10X device used in your application (in gd32e10x.h file)" -#endif /* undefine GD32E10X tip */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined HXTAL_VALUE -#define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */ -#define HXTAL_VALUE_8M HXTAL_VALUE -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */ -#if !defined (IRC48M_VALUE) -#define IRC48M_VALUE ((uint32_t)48000000) -#endif /* internal 48MHz RC oscillator value */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ -#if !defined (IRC40K_VALUE) -#define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* GD32E10x firmware library version number V1.0 */ -#define __GD32E10x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __GD32E10x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32E10x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32E10x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32E10x_STDPERIPH_VERSION ((__GD32E10x_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32E10x_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32E10x_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32E10x_STDPERIPH_VERSION_RC)) - -/* configuration of the Cortex-M4 processor and core peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< GD32E10x do not provide MPU */ -#define __NVIC_PRIO_BITS 4 /*!< GD32E10x uses 4 bits for the priority levels */ -#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -/* define interrupt number */ -typedef enum IRQn { - /* Cortex-M4 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ - /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ - LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ - RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ - FMC_IRQn = 4, /*!< FMC interrupt */ - RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ - EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ - EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ - EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ - EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ - EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ - DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ - DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ - DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ - DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ - DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ - DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ - DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ - ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ - CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ - TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */ - USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ - TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 67, /*!< USBFS global interrupt */ - -} IRQn_Type; - -/* includes */ -#include "core_cm4.h" -#include "system_gd32e10x.h" -#include - -#define GD_MBED_USED - -#ifdef GD_MBED_USED -typedef enum { - GD_OK = 0x00U, - GD_ERROR = 0x01U, - GD_BUSY = 0x02U, - GD_TIMEOUT = 0x03U -} gd_status_enum; - -typedef enum { - OP_STATE_RESET = 0x00U, - OP_STATE_READY = 0x01U, - OP_STATE_BUSY = 0x02U, - OP_STATE_TIMEOUT = 0x03U, - OP_STATE_ERROR = 0x04U, - OP_STATE_ABORT = 0x05U, - OP_STATE_LISTEN = 0x06U, - - OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */ - OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */ - - OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */ - OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */ - - OP_STATE_BUTT -} operation_state_enum; -#endif - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ -#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ -#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ - -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ -#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ - -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ -#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ -#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ -#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ - -/* advanced peripheral bus 2 memory map */ -#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ -#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ - -/* advanced high performance bus 1 memory map */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ -#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ - -/* define marco USE_STDPERIPH_DRIVER */ -#if !defined USE_STDPERIPH_DRIVER -#define USE_STDPERIPH_DRIVER -#endif -#ifdef USE_STDPERIPH_DRIVER -#include "gd32e10x_libopt.h" -#endif /* USE_STDPERIPH_DRIVER */ - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/gd32e10x_libopt.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/gd32e10x_libopt.h deleted file mode 100644 index 73750c46b18..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/gd32e10x_libopt.h +++ /dev/null @@ -1,64 +0,0 @@ -/*! - \file gd32e10x_libopt.h - \brief library optional for gd32e10x - - \version 2017-12-26, V1.0.0, firmware for GD32E10x - \version 2018-12-20, V1.1.0, firmware for GD32E10x(The version is for mbed) -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E10X_LIBOPT_H -#define GD32E10X_LIBOPT_H - -#include "gd32e10x_rcu.h" -#include "gd32e10x_adc.h" -#include "gd32e10x_can.h" -#include "gd32e10x_crc.h" -#include "gd32e10x_ctc.h" -#include "gd32e10x_dac.h" -#include "gd32e10x_dbg.h" -#include "gd32e10x_dma.h" -#include "gd32e10x_exti.h" -#include "gd32e10x_fmc.h" -#include "gd32e10x_fwdgt.h" -#include "gd32e10x_gpio.h" -#include "gd32e10x_i2c.h" -#include "gd32e10x_pmu.h" -#include "gd32e10x_bkp.h" -#include "gd32e10x_rtc.h" -#include "gd32e10x_spi.h" -#include "gd32e10x_timer.h" -#include "gd32e10x_usart.h" -#include "gd32e10x_wwdgt.h" -#include "gd32e10x_misc.h" -#include "gd32e10x_exmc.h" - -#endif /* GD32E10X_LIBOPT_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/hal_tick.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/hal_tick.h deleted file mode 100644 index 047174ccde5..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/hal_tick.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __HAL_TICK_H -#define __HAL_TICK_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "gd32e10x.h" -#include "cmsis_nvic.h" - -#define TICKER_TIMER TIMER2 -#define TICKER_TIMER_IRQ TIMER2_IRQn -#define TICKER_TIMER_RCU_CLOCK_ENABLE rcu_periph_clock_enable(RCU_TIMER2); -#define TICKER_TIMER_DEBUG_STOP dbg_periph_enable(DBG_TIMER2_HOLD); - -#define TICKER_TIMER_RESET_ENABLE rcu_periph_reset_enable(RCU_TIMER2RST) -#define TICKER_TIMER_RESET_DISABLE rcu_periph_reset_disable(RCU_TIMER2RST) - -/* 16 for 16-bit timer, 32 for 32-bit timer */ -#define TICKER_TIMER_WIDTH_BIT 16 - -/* 0 for CK_APB1, 1 for CK_APB2 */ -#define TICKER_TIMER_CKAPB 1 - -#ifdef __cplusplus -} -#endif - -#endif /* __HAL_TICK_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/system_gd32e10x.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/system_gd32e10x.c deleted file mode 100644 index d5f61a82bfa..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/system_gd32e10x.c +++ /dev/null @@ -1,847 +0,0 @@ -/*! - \file system_gd32e10x.c - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for - GD32E10x Device Series -*/ - -/* - Copyright (c) 2012 ARM LIMITED - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32e10x.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -/* Vector Table base offset */ -#define VECT_TAB_OFFSET 0x00 /* This value must be a multiple of 0x200. */ - -/* select a system clock by uncommenting the following line */ -/* use IRC8M */ -//#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M) -//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) -//#define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000) - -/* use HXTAL(CK_HXTAL = 8M) */ -//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) -//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) -#define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000) - -#define SEL_IRC8M 0x00U -#define SEL_HXTAL 0x01U -#define SEL_PLL 0x02U - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_IRC8M -uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M; -static void system_clock_8m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; -static void system_clock_48m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; -static void system_clock_72m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; -static void system_clock_108m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M; -static void system_clock_120m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; -static void system_clock_hxtal(void); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; -static void system_clock_48m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; -static void system_clock_108m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL; -static void system_clock_120m_hxtal(void); -#endif /* __SYSTEM_CLOCK_IRC8M */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none -*/ -void SystemInit(void) -{ - /* FPU settings */ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* reset the RCU clock configuration to the default reset state */ - /* Set IRC8MEN bit */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* Reset CFG0 and CFG1 registers */ - RCU_CFG0 = 0x00000000U; - RCU_CFG1 = 0x00000000U; - - /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - /* disable all interrupts */ - RCU_INT = 0x00ff0000U; - - /* reset HXTALBPS bit */ - RCU_CTL &= ~(RCU_CTL_HXTALBPS); - - /* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ - system_clock_config(); -} - -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_config(void) -{ -#ifdef __SYSTEM_CLOCK_IRC8M - system_clock_8m_irc8m(); -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) - system_clock_48m_irc8m(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) - system_clock_72m_irc8m(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) - system_clock_108m_irc8m(); -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) - system_clock_120m_irc8m(); - -#elif defined (__SYSTEM_CLOCK_HXTAL) - system_clock_hxtal(); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) - system_clock_48m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) - system_clock_72m_hxtal(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) - system_clock_108m_hxtal(); -#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) - system_clock_120m_hxtal(); -#endif /* __SYSTEM_CLOCK_IRC8M */ -} - -#ifdef __SYSTEM_CLOCK_IRC8M -/*! - \brief configure the system clock to 8M by IRC8M - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_8m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { - while (1) { - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* select IRC8M as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; - - /* wait until IRC8M is selected as system clock */ - while (0U != (RCU_CFG0 & RCU_SCSS_IRC8M)) { - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) -/*! - \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_1; - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL12; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -/*! - \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_2; - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL18; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -/*! - \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3; - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL27; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} - -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) -/*! - \brief configure the system clock to 120M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_120m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3; - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL30; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} - -#elif defined (__SYSTEM_CLOCK_HXTAL) -/*! - \brief configure the system clock to HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { - while (1) { - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while (0 == (RCU_CFG0 & RCU_SCSS_HXTAL)) { - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -/*! - \brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_1; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL12); - - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); -#ifdef HXTAL_VALUE_8M - /* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10); -#elif defined (HXTAL_VALUE_25M) - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); -#endif - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while ((RCU_CTL & RCU_CTL_PLL1STB) == 0) { - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -/*! - \brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_2; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18); - - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); -#ifdef HXTAL_VALUE_8M - /* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10); -#elif defined (HXTAL_VALUE_25M) - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); -#endif - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while ((RCU_CTL & RCU_CTL_PLL1STB) == 0) { - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -/*! - \brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL27); - - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); -#ifdef HXTAL_VALUE_8M - /* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10); -#elif defined (HXTAL_VALUE_25M) - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); -#endif - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while ((RCU_CTL & RCU_CTL_PLL1STB) == 0) { - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} - -#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) -/*! - \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_120m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); - - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); -#ifdef HXTAL_VALUE_8M - /* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10); -#elif defined (HXTAL_VALUE_25M) - /* CK_PREDIV0 = (CK_HXTAL)/5 *8/10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); -#endif - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while ((RCU_CTL & RCU_CTL_PLL1STB) == 0U) { - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} -#endif /* __SYSTEM_CLOCK_IRC8M */ - -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none -*/ -void SystemCoreClockUpdate(void) -{ - uint32_t sws; - uint32_t pllsel, pllpresel, predv0sel, pllmf, ck_src; - uint32_t predv0, predv1, pll1mf; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch (sws) { - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - SystemCoreClock = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) { - /* PLL clock source is HXTAL or IRC48M */ - pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); - - if (RCU_PLLPRESRC_HXTAL == pllpresel) { - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - } else { - /* PLL clock source is IRC48 */ - ck_src = IRC48M_VALUE; - } - - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - /* source clock use PLL1 */ - if (RCU_PREDV0SRC_CKPLL1 == predv0sel) { - predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if (17U == pll1mf) { - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; - } else { - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE / 2U; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { - pllmf |= 0x10U; - } - if (pllmf < 15U) { - pllmf += 2U; - } else { - pllmf += 1U; - } - SystemCoreClock = ck_src * pllmf; - if (15U == pllmf) { - SystemCoreClock = ck_src * 6U + ck_src / 2U; - } - - break; - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } - -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/system_gd32e10x.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/system_gd32e10x.h deleted file mode 100644 index 3d37795f6dd..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/device/system_gd32e10x.h +++ /dev/null @@ -1,58 +0,0 @@ -/*! - \file system_gd32e10x.h - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for - GD32E10x Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32E10X_H -#define SYSTEM_GD32E10X_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit(void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32E10X_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/flash_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/flash_api.c deleted file mode 100644 index eca873bb137..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/flash_api.c +++ /dev/null @@ -1,200 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_api.h" -#include "mbed_critical.h" - -#if DEVICE_FLASH -#include "cmsis.h" - -#define FLASH_SIZE (0x00020000U) -#define FLASH_PAGE_SIZE (0x00000400U) -#define FLASH_START_ADDR (0X08000000U) -#define FLASH_END_ADDR (0x0801FFFFU) -#define WORD_SIZE (4U) - -/* unlock the main FLASH operation - * - * @return 0 for success, -1 for error -*/ -static int32_t flash_unlock(void) -{ - fmc_unlock(); - if (RESET != (FMC_CTL & FMC_CTL_LK)) { - return -1; - } - return 0; -} - -/* lock the main FLASH operation - * - * @return 0 for success, -1 for error -*/ -static int32_t flash_lock(void) -{ - fmc_lock(); - if (RESET == (FMC_CTL & FMC_CTL_LK)) { - return -1; - } - return 0; -} - -/** Initialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_init(flash_t *obj) -{ - return 0; -} - -/** Uninitialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_free(flash_t *obj) -{ - return 0; -} - -/** Erase one sector starting at defined address - * - * The address should be at sector boundary. This function does not do any check for address alignments - * @param obj The flash object - * @param address The sector starting address - * @return 0 for success, -1 for error - */ -int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - int32_t flash_state = 0; - flash_unlock(); - - /* clear FLASH flag */ - fmc_flag_clear(FMC_FLAG_PGERR); - fmc_flag_clear(FMC_FLAG_PGAERR); - fmc_flag_clear(FMC_FLAG_WPERR); - fmc_flag_clear(FMC_FLAG_END); - - /* make sure the address is a right page address */ - if (FMC_READY != fmc_page_erase(address)) { - flash_state = -1; - } - - flash_lock(); - return flash_state; -} - -/** Program pages starting at defined address - * - * The pages should not cross multiple sectors. - * This function does not do any check for address alignments or if size is aligned to a page size. - * @param obj The flash object - * @param address The sector starting address - * @param data The data buffer to be programmed - * @param size The number of bytes to program - * @return 0 for success, -1 for error - */ -int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - uint32_t *p_data; - p_data = (uint32_t *)data; - uint32_t num = 0; - int32_t flash_state = 0; - flash_unlock(); - - /* clear FLASH flag */ - fmc_flag_clear(FMC_FLAG_PGERR); - fmc_flag_clear(FMC_FLAG_PGAERR); - fmc_flag_clear(FMC_FLAG_WPERR); - fmc_flag_clear(FMC_FLAG_END); - - if (size % 4) { - num = size / 4 + 1; - } else { - num = size / 4; - } - for (uint32_t i = 0; i < num; i++) { - - if (FMC_READY != fmc_word_program(address, *(p_data + i))) { - flash_state = -1; - break; - } - address += 4; - } - flash_lock(); - return flash_state; -} - -/** Get sector size - * - * @param obj The flash object - * @param address The sector starting address - * @return The size of a sector - */ -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ - if ((FLASH_START_ADDR > address) || (FLASH_END_ADDR < address)) { - return MBED_FLASH_INVALID_SIZE; - } - return FLASH_PAGE_SIZE; -} - -/** Get page size - * - * The page size defines the writable page size - * @param obj The flash object - * @return The size of a page - */ -uint32_t flash_get_page_size(const flash_t *obj) -{ - return WORD_SIZE; -} - -/** Get start address for the flash region - * - * @param obj The flash object - * @return The start address for the flash region - */ -uint32_t flash_get_start_address(const flash_t *obj) -{ - return FLASH_START_ADDR; -} - -/** Get the flash region size - * - * @param obj The flash object - * @return The flash region size - */ -uint32_t flash_get_size(const flash_t *obj) -{ - return FLASH_SIZE; -} - -/** Get the flash erase value - * - * @param obj The flash object - * @return The flash erase value - */ -uint8_t flash_get_erase_value(const flash_t *obj) -{ - return 0xFF; -} - -#endif /* DEVICE_FLASH */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/gpio_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/gpio_api.c deleted file mode 100644 index c31a1606293..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/gpio_api.c +++ /dev/null @@ -1,151 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gd32e10x_gpio.h" -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern const int GD_GPIO_REMAP[]; -extern const int GD_GPIO_SPEED[]; -extern const int GD_GPIO_MODE[]; - -/* Enable GPIO clock and return GPIO base address */ -uint32_t gpio_clock_enable(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PORTA: - gpio_add = GPIOA; - rcu_periph_clock_enable(RCU_GPIOA); - break; - case PORTB: - gpio_add = GPIOB; - rcu_periph_clock_enable(RCU_GPIOB); - break; - case PORTC: - gpio_add = GPIOC; - rcu_periph_clock_enable(RCU_GPIOC); - break; - case PORTD: - gpio_add = GPIOD; - rcu_periph_clock_enable(RCU_GPIOD); - break; - case PORTE: - gpio_add = GPIOE; - rcu_periph_clock_enable(RCU_GPIOE); - break; - default: - error("port number not exist"); - break; - } - return gpio_add; -} - -/** Set the given pin as GPIO - * - * @param pin The pin to be set as GPIO - * @return The GPIO port mask for this pin - */ -uint32_t gpio_set(PinName pin) -{ - - MBED_ASSERT(pin != (PinName)NC); - pin_function(pin, MODE_IN_FLOATING); - /* return pin mask */ - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); -} - -/** Initialize the GPIO pin - * - * @param obj The GPIO object to initialize - * @param pin The GPIO pin to initialize - */ -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - /* fill struct parameter for future use */ - uint32_t port_index = GD_PORT_GET(pin); - uint32_t gpio = gpio_clock_enable(port_index); - obj->mask = gpio_set(pin); - obj->gpio_periph = gpio; -} - -/** Set the input pin mode - * - * @param obj The GPIO object - * @param mode The pin mode to be set - */ -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -/** Set the output value - * - * @param obj The GPIO object - * @param value The value to be set - */ -void gpio_write(gpio_t *obj, int value) -{ - /* set or reset GPIO pin */ - if (value) { - GPIO_BOP(obj->gpio_periph) = (1 << (uint32_t)GD_PIN_GET(obj->pin)); - } else { - GPIO_BC(obj->gpio_periph) = (1 << (uint32_t)GD_PIN_GET(obj->pin)); - } -} - -/** Read the input value - * - * @param obj The GPIO object - * @return An integer value 1 or 0 - */ -int gpio_read(gpio_t *obj) -{ - /* return state of GPIO pin */ - return ((GPIO_ISTAT(obj->gpio_periph) & obj->mask) ? 1 : 0); -} - -/* Checks if gpio object is connected (pin was not initialized with NC) - * @param pin The pin to be set as GPIO - * @return 0 if port is initialized with NC - **/ -int gpio_is_connected(const gpio_t *obj) -{ - return obj->pin != (PinName)NC; -} - -/** Set the pin direction - * - * @param obj The GPIO object - * @param direction The pin direction to be set - */ -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - - /* config GPIO pin as input or output */ - if (direction == PIN_INPUT) { - gpio_para_init(obj->gpio_periph, GD_GPIO_MODE[MODE_IN_FLOATING], GD_GPIO_SPEED[0], (1 << (uint32_t)GD_PIN_GET(obj->pin))); - } else { - gpio_para_init(obj->gpio_periph, GD_GPIO_MODE[MODE_OUT_PP], GD_GPIO_SPEED[0], (1 << (uint32_t)GD_PIN_GET(obj->pin))); - } -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/gpio_irq_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/gpio_irq_api.c deleted file mode 100644 index c48633977e5..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/gpio_irq_api.c +++ /dev/null @@ -1,330 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) - -extern uint32_t gpio_clock_enable(uint32_t port_idx); -static gpio_irq_handler irq_handler; - -typedef struct { - uint32_t exti_idx; - uint32_t exti_gpiox; /* base address of gpio */ - uint32_t exti_pinx; /* pin number */ -} gpio_exti_info_struct; - -/* EXTI0...EXTI15 */ -static gpio_exti_info_struct exti_info_array[16] = {0}; - -/** handle EXTI interrupt in EXTI0 to EXTI15 - - * @param irq_index the line of EXTI(0~15) - */ -static void exti_handle_interrupt(uint32_t irq_index) -{ - gpio_exti_info_struct *gpio_exti = &exti_info_array[irq_index]; - - /* get the port and pin of EXTI */ - uint32_t gpio = (uint32_t)(gpio_exti->exti_gpiox); - uint32_t pin = (uint32_t)(1 << (gpio_exti->exti_pinx)); - - /* clear interrupt flag */ - if (exti_interrupt_flag_get((exti_line_enum)pin) != RESET) { - exti_interrupt_flag_clear((exti_line_enum)pin); - /* check which edge has generated the irq */ - if ((GPIO_ISTAT(gpio) & pin) == 0) { - irq_handler(gpio_exti->exti_idx, IRQ_FALL); - } else { - irq_handler(gpio_exti->exti_idx, IRQ_RISE); - } - } - -} - -/* EXTI0 interrupt handler */ -static void gpio_irq_exti0(void) -{ - exti_handle_interrupt(0); -} -/* EXTI1 interrupt handler */ -static void gpio_irq_exti1(void) -{ - exti_handle_interrupt(1); -} -/* EXTI2 interrupt handler */ -static void gpio_irq_exti2(void) -{ - exti_handle_interrupt(2); -} -/* EXTI3 interrupt handler */ -static void gpio_irq_exti3(void) -{ - exti_handle_interrupt(3); -} -/* EXTI4 interrupt handler */ -static void gpio_irq_exti4(void) -{ - exti_handle_interrupt(4); -} -/* EXTI5 interrupt handler */ -static void gpio_irq_exti5(void) -{ - exti_handle_interrupt(5); -} -/* EXTI6 interrupt handler */ -static void gpio_irq_exti6(void) -{ - exti_handle_interrupt(6); -} -/* EXTI7 interrupt handler */ -static void gpio_irq_exti7(void) -{ - exti_handle_interrupt(7); -} -/* EXTI8 interrupt handler */ -static void gpio_irq_exti8(void) -{ - exti_handle_interrupt(8); -} -/* EXTI9 interrupt handler */ -static void gpio_irq_exti9(void) -{ - exti_handle_interrupt(9); -} -/* EXTI10 interrupt handler */ -static void gpio_irq_exti10(void) -{ - exti_handle_interrupt(10); -} -/* EXTI11 interrupt handler */ -static void gpio_irq_exti11(void) -{ - exti_handle_interrupt(11); -} -/* EXTI12 interrupt handler */ -static void gpio_irq_exti12(void) -{ - exti_handle_interrupt(12); -} -/* EXTI13 interrupt handler */ -static void gpio_irq_exti13(void) -{ - exti_handle_interrupt(13); -} -/* EXTI14 interrupt handler */ -static void gpio_irq_exti14(void) -{ - exti_handle_interrupt(14); -} -/* EXTI15 interrupt handler */ -static void gpio_irq_exti15(void) -{ - exti_handle_interrupt(15); -} - -/** Initialize the GPIO IRQ pin - * - * @param obj The GPIO object to initialize - * @param pin The GPIO pin name - * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID (id != 0, 0 is reserved) - * @return -1 if pin is NC, 0 otherwise - */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - uint32_t vector = 0; - gpio_exti_info_struct *gpio_exti; - if (pin == NC) { - return -1; - } - - /* Enable AF Clock */ - rcu_periph_clock_enable(RCU_AF); - - uint32_t port_index = GD_PORT_GET(pin); - uint32_t pin_index = GD_PIN_GET(pin); - /* Enable GPIO clock */ - uint32_t gpio_add = gpio_clock_enable(port_index); - - /* fill EXTI information according to pin_index . - eg. use PORTE_9 as EXTI interrupt, the irq type is EXTI5_9_IRQn */ - if (pin_index == 0) { - vector = (uint32_t)&gpio_irq_exti0; - obj->irq_index = 0; - obj->irq_n = EXTI0_IRQn; - } else if (pin_index == 1) { - vector = (uint32_t)&gpio_irq_exti1; - obj->irq_index = 1; - obj->irq_n = EXTI1_IRQn; - } else if (pin_index == 2) { - vector = (uint32_t)&gpio_irq_exti2; - obj->irq_index = 2; - obj->irq_n = EXTI2_IRQn; - } else if (pin_index == 3) { - vector = (uint32_t)&gpio_irq_exti3; - obj->irq_index = 3; - obj->irq_n = EXTI3_IRQn; - } else if (pin_index == 4) { - vector = (uint32_t)&gpio_irq_exti4; - obj->irq_index = 4; - obj->irq_n = EXTI4_IRQn; - } else if (pin_index == 5) { - vector = (uint32_t)&gpio_irq_exti5; - obj->irq_index = 5; - obj->irq_n = EXTI5_9_IRQn; - } else if (pin_index == 6) { - vector = (uint32_t)&gpio_irq_exti6; - obj->irq_index = 6; - obj->irq_n = EXTI5_9_IRQn; - } else if (pin_index == 7) { - vector = (uint32_t)&gpio_irq_exti7; - obj->irq_index = 7; - obj->irq_n = EXTI5_9_IRQn; - } else if (pin_index == 8) { - vector = (uint32_t)&gpio_irq_exti8; - obj->irq_index = 8; - obj->irq_n = EXTI5_9_IRQn; - } else if (pin_index == 9) { - vector = (uint32_t)&gpio_irq_exti9; - obj->irq_index = 9; - obj->irq_n = EXTI5_9_IRQn; - } else if (pin_index == 10) { - vector = (uint32_t)&gpio_irq_exti10; - obj->irq_index = 10; - obj->irq_n = EXTI10_15_IRQn; - } else if (pin_index == 11) { - vector = (uint32_t)&gpio_irq_exti11; - obj->irq_index = 11; - obj->irq_n = EXTI10_15_IRQn; - } else if (pin_index == 12) { - vector = (uint32_t)&gpio_irq_exti12; - obj->irq_index = 12; - obj->irq_n = EXTI10_15_IRQn; - } else if (pin_index == 13) { - vector = (uint32_t)&gpio_irq_exti13; - obj->irq_index = 13; - obj->irq_n = EXTI10_15_IRQn; - } else if (pin_index == 14) { - vector = (uint32_t)&gpio_irq_exti14; - obj->irq_index = 14; - obj->irq_n = EXTI10_15_IRQn; - } else if (pin_index == 15) { - vector = (uint32_t)&gpio_irq_exti15; - obj->irq_index = 15; - obj->irq_n = EXTI10_15_IRQn; - } else { - error("pin not supported for interrupt in.\n"); - return -1; - } - - /* Save informations for future use */ - obj->event = EDGE_NONE; - obj->pin = pin; - - gpio_exti = &exti_info_array[obj->irq_index]; - gpio_exti->exti_idx = id; - gpio_exti->exti_gpiox = gpio_add; - gpio_exti->exti_pinx = pin_index; - - irq_handler = handler; - - /* Enable EXTI interrupt */ - NVIC_SetVector(obj->irq_n, vector); - gpio_irq_enable(obj); - - return 0; -} - -/** Release the GPIO IRQ PIN - * - * @param obj The gpio object - */ -void gpio_irq_free(gpio_irq_t *obj) -{ - gpio_exti_info_struct *gpio_exti = &exti_info_array[obj->irq_index]; - - /* Disable EXTI interrupt */ - gpio_irq_disable(obj); - /* Reset struct of exti information */ - gpio_exti->exti_idx = 0; - gpio_exti->exti_gpiox = 0; - gpio_exti->exti_pinx = 0; -} - -/** Enable/disable pin IRQ event - * - * @param obj The GPIO object - * @param event The GPIO IRQ event - * @param enable The enable flag - */ -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - if (event == IRQ_RISE) { - if (enable) { - exti_init((exti_line_enum)(1 << GD_PIN_GET(obj->pin)), EXTI_INTERRUPT, EXTI_TRIG_RISING); - /* Clear interrupt enable bit, rising/falling bit */ - } else { - EXTI_INTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); - EXTI_RTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); - EXTI_FTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); - } - } - if (event == IRQ_FALL) { - if (enable) { - exti_init((exti_line_enum)(1 << (GD_PIN_GET(obj->pin))), EXTI_INTERRUPT, EXTI_TRIG_FALLING); - /* Clear interrupt enable bit, rising/falling bit */ - } else { - EXTI_INTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); - EXTI_RTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); - EXTI_FTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); - } - } -} - -/** Enable GPIO IRQ - * - * This is target dependent, as it might enable the entire port or just a pin - * @param obj The GPIO object - */ -void gpio_irq_enable(gpio_irq_t *obj) -{ - /* Select EXTI Source */ - gpio_exti_source_select(GD_PORT_GET(obj->pin), GD_PIN_GET(obj->pin)); - exti_interrupt_enable((exti_line_enum)(1 << GD_PIN_GET(obj->pin))); - NVIC_EnableIRQ(obj->irq_n); -} - -/** Disable GPIO IRQ - * - * This is target dependent, as it might disable the entire port or just a pin - * @param obj The GPIO object - */ -void gpio_irq_disable(gpio_irq_t *obj) -{ - /* Clear EXTI line configuration */ - exti_interrupt_disable((exti_line_enum)(1 << GD_PIN_GET(obj->pin))); - NVIC_DisableIRQ(obj->irq_n); - NVIC_ClearPendingIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/i2c_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/i2c_api.c deleted file mode 100644 index b2355b76d8d..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/i2c_api.c +++ /dev/null @@ -1,677 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -#if DEVICE_I2C_ASYNCH -#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) -#else -#define I2C_S(obj) (struct i2c_s *) (obj) -#endif - -#define BUSY_TIMEOUT ((SystemCoreClock / obj_s->freq) * 2 * 10) -#define FLAG_TIMEOUT (0xF0000U) - -/** Reset I2C peripheral by hardware method. Most of the implementation enable RCU reset. - * - * @param obj The I2C object - */ -static void i2c_hw_reset(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - - switch (obj_s->i2c) { - case I2C_0: - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - - case I2C_1: - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - } -} - -/** Initialize the I2C peripheral. It sets the default parameters for I2C - * peripheral, and configures its specifieds pins. - * - * @param obj The I2C object - * @param sda The sda pin - * @param scl The scl pin - */ -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - struct i2c_s *obj_s = I2C_S(obj); - - /* find the I2C by pins */ - uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); - uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj_s->sda = sda; - obj_s->scl = scl; - obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj_s->i2c != (I2CName)NC); - - switch (obj_s->i2c) { - case I2C_0: - /* enable I2C0 clock and configure the pins of I2C0 */ - obj_s->index = 0; - rcu_periph_clock_enable(RCU_I2C0); - - break; - - case I2C_1: - /* enable I2C1 clock and configure the pins of I2C1 */ - obj_s->index = 1; - rcu_periph_clock_enable(RCU_I2C1); - - break; - - default: - break; - } - - /* configure the pins of I2C */ - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - - /* 100 KHz as the default I2C frequence */ - i2c_frequency(obj, 100000); - - obj_s->state = (operation_state_enum)I2C_STATE_NONE; - obj_s->previous_state_mode = I2C_STATE_NONE; - obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; - -#if DEVICE_I2CSLAVE - /* I2C master by default */ - obj_s->slave = 0; -#endif -} - -/** Configure the I2C frequency - * - * @param obj The I2C object - * @param hz Frequency in Hz - */ -void i2c_frequency(i2c_t *obj, int hz) -{ - int timeout; - struct i2c_s *obj_s = I2C_S(obj); - - /* wait until I2C_FLAG_I2CBSY flag is reset */ - timeout = BUSY_TIMEOUT; - while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) && (--timeout != 0)); - - /* reset to clear pending flags */ - i2c_hw_reset(obj); - - /* disable I2C peripheral */ - i2c_disable(obj_s->i2c); - - /* configure I2C frequence */ - i2c_clock_config(obj_s->i2c, hz, I2C_DTCY_2); - - /* configure I2C address mode and slave address */ - i2c_mode_addr_config(obj_s->i2c, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0); - - /* enable I2C peripheral */ - i2c_enable(obj_s->i2c); -} - -/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop() - * - * @param obj The I2C object - */ -void i2c_reset(i2c_t *obj) -{ - i2c_stop(obj); -} - -/** Send START command - * - * @param obj The I2C object - */ -int i2c_start(i2c_t *obj) -{ - int timeout; - struct i2c_s *obj_s = I2C_S(obj); - - /* clear I2C_FLAG_AERR Flag */ - i2c_flag_clear(obj_s->i2c, I2C_FLAG_AERR); - - /* wait until I2C_FLAG_I2CBSY flag is reset */ - timeout = FLAG_TIMEOUT; - while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { - if ((timeout--) == 0) { - return (int)GD_BUSY; - } - } - - /* ensure the i2c has been stopped */ - timeout = FLAG_TIMEOUT; - while ((I2C_CTL0(obj_s->i2c) & I2C_CTL0_STOP) == I2C_CTL0_STOP) { - if ((timeout--) == 0) { - return (int)GD_ERROR; - } - } - - /* generate a START condition */ - i2c_start_on_bus(obj_s->i2c); - - /* ensure the i2c has been started successfully */ - timeout = FLAG_TIMEOUT; - while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { - if ((timeout--) == 0) { - return (int)GD_ERROR; - } - } - - return (int)GD_OK; -} - -/** Send STOP command - * - * @param obj The I2C object - */ -int i2c_stop(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - - /* generate a STOP condition */ - i2c_stop_on_bus(obj_s->i2c); - - /* wait for STOP bit reset */ - while ((I2C_CTL0(obj_s->i2c) & I2C_CTL0_STOP)); - - return 0; -} - -/** Read one byte - * - * @param obj The I2C object - * @param last Acknoledge - * @return The read byte - */ -int i2c_byte_read(i2c_t *obj, int last) -{ - int timeout; - struct i2c_s *obj_s = I2C_S(obj); - - if (last) { - /* disable acknowledge */ - i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); - } else { - /* enable acknowledge */ - i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); - } - - /* wait until the byte is received */ - timeout = FLAG_TIMEOUT; - while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)I2C_DATA(obj_s->i2c); -} - -/** Write one byte - * - * @param obj The I2C object - * @param data Byte to be written - * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout. - */ -int i2c_byte_write(i2c_t *obj, int data) -{ - int timeout; - struct i2c_s *obj_s = I2C_S(obj); - - I2C_DATA(obj_s->i2c) = (uint8_t)data; - - /* wait until the byte is transmitted */ - timeout = FLAG_TIMEOUT; - while (((i2c_flag_get(obj_s->i2c, I2C_FLAG_TBE)) == RESET) && - ((i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)) == RESET)) { - if ((timeout--) == 0) { - return 2; - } - } - - return 1; -} - -/** Blocking reading data - * - * @param obj The I2C object - * @param address 7-bit address (last bit is 1) - * @param data The buffer for receiving - * @param length Number of bytes to read - * @param stop Stop to be generated after the transfer is done - * @return Number of read bytes - */ -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t count = 0U; - int timeout = 0; - - if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || - obj_s->global_trans_option == I2C_LAST_FRAME) { - if (stop) { - obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; - } else { - obj_s->global_trans_option = I2C_FIRST_FRAME; - } - } else if (obj_s->global_trans_option == I2C_FIRST_FRAME || - obj_s->global_trans_option == I2C_NEXT_FRAME) { - if (stop) { - obj_s->global_trans_option = I2C_LAST_FRAME; - } else { - obj_s->global_trans_option = I2C_NEXT_FRAME; - } - } - - if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME) { - /* wait until I2C_FLAG_I2CBSY flag is reset */ - timeout = FLAG_TIMEOUT; - while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { - if ((timeout--) == 0) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - } - } - - if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME || - obj_s->previous_state_mode != I2C_STATE_MASTER_BUSY_RX) { - /* generate a START condition */ - i2c_start_on_bus(obj_s->i2c); - - /* ensure the i2c has been started successfully */ - timeout = FLAG_TIMEOUT; - while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { - if ((timeout--) == 0) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - } - - /* send slave address */ - i2c_master_addressing(obj_s->i2c, address, I2C_RECEIVER); - - if (1 == length) { - /* disable acknowledge */ - i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); - /* send a stop condition to I2C bus*/ - } else if (2 == length) { - /* send a NACK for the next data byte which will be received into the shift register */ - i2c_ackpos_config(obj_s->i2c, I2C_ACKPOS_NEXT); - /* disable acknowledge */ - i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); - } else { - /* enable acknowledge */ - i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); - } - - timeout = 0; - /* wait until I2C_FLAG_ADDSEND flag is set */ - while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { - timeout++; - if (timeout > 100000) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - } - - /* clear ADDSEND */ - i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); - } - - obj_s->state = (operation_state_enum)I2C_STATE_MASTER_BUSY_RX; - - for (count = 0; count < length; count++) { - if (length > 2 && count == length - 3) { - while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)); - i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); - } else if (2 == length && count == 0) { - while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)); - } - - while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)); - data[count] = i2c_data_receive(obj_s->i2c); - } - - obj_s->previous_state_mode = obj_s->state; - - /* if not sequential read, then send stop */ - if (stop) { - i2c_stop(obj); - } - - return count; -} - -/** Blocking sending data - * - * @param obj The I2C object - * @param address 7-bit address (last bit is 0) - * @param data The buffer for sending - * @param length Number of bytes to write - * @param stop Stop to be generated after the transfer is done - * @return - * zero or non-zero - Number of written bytes - * negative - I2C_ERROR_XXX status - */ -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - struct i2c_s *obj_s = I2C_S(obj); - gd_status_enum status = GD_OK; - uint32_t count = 0; - int timeout = 0; - - if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || - obj_s->global_trans_option == I2C_LAST_FRAME) { - if (stop) { - obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; - } else { - obj_s->global_trans_option = I2C_FIRST_FRAME; - } - } else if (obj_s->global_trans_option == I2C_FIRST_FRAME || - obj_s->global_trans_option == I2C_NEXT_FRAME) { - if (stop) { - obj_s->global_trans_option = I2C_LAST_FRAME; - } else { - obj_s->global_trans_option = I2C_NEXT_FRAME; - } - } - - if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME) { - /* wait until I2C_FLAG_I2CBSY flag is reset */ - timeout = FLAG_TIMEOUT; - while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { - if ((timeout--) == 0) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - } - } - - if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME || - obj_s->previous_state_mode != I2C_STATE_MASTER_BUSY_TX) { - /* generate a START condition */ - i2c_start_on_bus(obj_s->i2c); - - /* ensure the i2c has been started successfully */ - timeout = FLAG_TIMEOUT; - while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { - if ((timeout--) == 0) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - } - - /* send slave address */ - i2c_master_addressing(obj_s->i2c, address, I2C_TRANSMITTER); - - timeout = 0; - /* wait until I2C_FLAG_ADDSEND flag is set */ - while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { - timeout++; - if (timeout > 100000) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - } - - /* clear ADDSEND */ - i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); - } - - obj_s->state = (operation_state_enum)I2C_STATE_MASTER_BUSY_TX; - - for (count = 0; count < length; count++) { - status = (gd_status_enum)i2c_byte_write(obj, data[count]); - if (status != 1) { - i2c_stop(obj); - return count; - } - } - - obj_s->previous_state_mode = obj_s->state; - - /* if not sequential write, then send stop */ - if (stop) { - i2c_stop(obj); - } - - return count; -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#if DEVICE_I2CSLAVE - -/** Configure I2C address. - * @param obj The I2C object - * @param idx Currently not used - * @param address The address to be set - * @param mask Currently not used - */ -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - struct i2c_s *obj_s = I2C_S(obj); - - /* disable I2C peripheral */ - i2c_disable(obj_s->i2c); - /* I2C clock configure */ - i2c_clock_config(obj_s->i2c, 100000, I2C_DTCY_2); - /* I2C address configure */ - i2c_mode_addr_config(obj_s->i2c, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, address); - /* enable I2C0 */ - i2c_enable(obj_s->i2c); - /* enable acknowledge */ - i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); -} - -/** Configure I2C as slave or master. - * @param obj The I2C object - * @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive - * @return non-zero if a value is available - */ -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - struct i2c_s *obj_s = I2C_S(obj); - - if (enable_slave) { - obj_s->slave = 1; - } else { - obj_s->slave = 0; - } -} - -/* the same as the definition in I2CSlave.h class I2CSlave */ -#define NoData 0 /* the slave has not been addressed */ -#define ReadAddressed 1 /* the master has requested a read from this slave (slave as transmitter) */ -#define WriteGeneral 2 /* the master is writing to all slave */ -#define WriteAddressed 3 /* the master is writing to this slave (slave as receiver) */ - -/** Check to see if the I2C slave has been addressed. - * @param obj The I2C object - * @return The status - 1 - read addresses, 2 - write to all slaves, - * 3 write addressed, 0 - the slave has not been addressed - */ -int i2c_slave_receive(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - int ret = NoData; - - i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); - - if (i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { - i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); - if (i2c_flag_get(obj_s->i2c, I2C_FLAG_RXGC)) { - ret = WriteGeneral; - } - - if (i2c_flag_get(obj_s->i2c, I2C_FLAG_TRS)) { - ret = ReadAddressed; - } else { - ret = WriteAddressed; - } - } - - i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); - - return (ret); -} - -/** Configure I2C as slave or master. - * @param obj The I2C object - * @param data The buffer for receiving - * @param length Number of bytes to read - * @return non-zero if a value is available - */ -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - struct i2c_s *obj_s = I2C_S(obj); - int count = 0; - int timeout = 0; - - i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); - - /* wait until ADDSEND bit is set */ - while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { - timeout++; - if (timeout > 100000) { - return -1; - } - } - /* clear ADDSEND bit */ - i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); - - while (0 < length) { - /* wait until the RBNE bit is set */ - timeout = 0; - while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)) { - timeout++; - if (timeout > 100000) { - return -1; - } - } - *data = i2c_data_receive(obj_s->i2c); - data++; - length--; - count++; - } - /* wait until the STPDET bit is set */ - timeout = 0; - while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_STPDET)) { - timeout++; - if (timeout > 100) { - return count; - } - } - /* clear the STPDET bit */ - i2c_enable(obj_s->i2c); - - i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); - - return count; -} - -/** Configure I2C as slave or master. - * @param obj The I2C object - * @param data The buffer for sending - * @param length Number of bytes to write - * @return non-zero if a value is available - */ -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - struct i2c_s *obj_s = I2C_S(obj); - int count = 0; - int timeout = 0; - - i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); - /* wait until ADDSEND bit is set */ - while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { - timeout++; - if (timeout > 100000) { - return -1; - } - } - /* clear ADDSEND bit */ - i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); - while (length > 0) { - /* wait until the TBE bit is set */ - timeout = 0; - while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_TBE)) { - timeout++; - if (timeout > 100000) { - return -1; - } - } - i2c_data_transmit(obj_s->i2c, *data); - data++; - length--; - count++; - } - /* the master doesn't acknowledge for the last byte */ - timeout = 0; - while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_AERR)) { - timeout++; - if (timeout > 100000) { - return -1; - } - } - /* clear the bit of AERR */ - i2c_flag_clear(obj_s->i2c, I2C_FLAG_AERR); - /* disable acknowledge */ - i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); - - return count; -} -#endif /* DEVICE_I2CSLAVE */ - -#endif /* DEVICE_I2C */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/mbed_overrides.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/mbed_overrides.c deleted file mode 100644 index 7182028b135..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/mbed_overrides.c +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gd32e10x.h" -#include "cmsis.h" -#include "hal_tick.h" - -int mbed_sdk_inited = 0; - -/*! - \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -#if TICKER_TIMER_WIDTH_BIT == 16 -extern void ticker_16bits_timer_init(void); -#else -extern void ticker_32bits_timer_init(void); -#endif - -/** - * SDK hook for running code before ctors or OS - * - * This is a weak function which can be overridden by a target's - * SDK to allow code to run after ram is initialized but before - * the OS has been started or constructors have run. - * - * Preconditions: - * - Ram is initialized - * - NVIC is setup - */ -/** - * This function is called after RAM initialization and before main. - */ -void mbed_sdk_init() -{ - nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0); - - /* configure 1ms tick */ -#if TICKER_TIMER_WIDTH_BIT == 16 - ticker_16bits_timer_init(); -#else - ticker_32bits_timer_init(); -#endif - - mbed_sdk_inited = 1; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/objects.h b/targets/TARGET_GigaDevice/TARGET_GD32E10X/objects.h deleted file mode 100644 index f2ed68a5212..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/objects.h +++ /dev/null @@ -1,183 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct gpio_s gpio_t; - -struct gpio_s { - uint32_t mask; - PinName pin; - __IO uint32_t gpio_periph; -}; - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -struct analogin_s { - ADCName adc; - PinName pin; - uint8_t channel; -}; - -#if DEVICE_ANALOGOUT -struct dac_s { - DACName dac; - PinName pin; - uint32_t channel; -}; -#endif - -struct can_s { - CANName can; - int index; -}; - -struct pwmout_s { - PWMName pwm; - uint32_t cnt_unit; - uint8_t ch; -}; - -struct serial_s { - /* basic information */ - UARTName uart; - int index; - PinName pin_tx; - PinName pin_rx; - - /* configure information */ - uint32_t baudrate; - uint32_t databits; - uint32_t stopbits; - uint32_t parity; - - /* operating parameters */ - uint16_t rx_size; - uint8_t *tx_buffer_ptr; - uint8_t *rx_buffer_ptr; - __IO uint16_t tx_count; - __IO uint16_t rx_count; - - __IO uint32_t error_code; - __IO operation_state_enum tx_state; - __IO operation_state_enum rx_state; - -#if DEVICE_SERIAL_ASYNCH - uint32_t events; -#endif -#if DEVICE_SERIAL_FC - uint32_t hw_flow_ctl; - PinName pin_rts; - PinName pin_cts; -#endif -}; - -struct spi_s { - spi_parameter_struct spi_struct; - IRQn_Type spi_irq; - SPIName spi; - PinName pin_miso; - PinName pin_mosi; - PinName pin_sclk; - PinName pin_ssel; -}; - -struct i2c_s { - /* basic information */ - I2CName i2c; - uint8_t index; - PinName sda; - PinName scl; - int i2c_inited; /* flag used to indicate whether the i2c has been initialized */ - - /* configure information */ - int freq; /* i2c frequence */ - uint32_t addr_bit_mode; /* 7 bits or 10 bits */ - uint32_t slave_addr0; - uint32_t slave_addr1; - uint16_t transfer_size; - uint8_t *buffer_pointer; - - /* operating parameters */ - __IO operation_state_enum state; - __IO i2c_mode_enum mode; - __IO uint32_t previous_state_mode; - __IO uint32_t i2c_target_dev_addr; - __IO uint32_t event_count; - __IO uint32_t transfer_count; - __IO uint32_t transfer_option; - __IO uint32_t error_code; - - /* I2C DMA information */ - uint32_t tx_dma_periph; - dma_channel_enum tx_dma_channel; - uint32_t rx_dma_periph; - dma_channel_enum rx_dma_channel; - - IRQn_Type event_i2cIRQ; - IRQn_Type error_i2cIRQ; - uint32_t global_trans_option; - volatile uint8_t event; - -#if DEVICE_I2CSLAVE - uint8_t slave; - volatile uint8_t pending_slave_tx_master_rx; - volatile uint8_t pending_slave_rx_maxter_tx; -#endif - -#if DEVICE_I2C_ASYNCH - uint32_t address; - uint8_t stop; - uint8_t available_events; -#endif - -}; -#if DEVICE_FLASH -struct flash_s { - /* nothing to be stored for now */ - uint32_t dummy; -}; -#endif -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/pinmap.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/pinmap.c deleted file mode 100644 index eeed6684202..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/pinmap.c +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -extern uint32_t gpio_clock_enable(uint32_t port_idx); - -extern const int GD_GPIO_REMAP[]; -extern const int GD_GPIO_MODE[]; -extern const int GD_GPIO_SPEED[]; - -static void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pin); - -/** Configure pin (mode, speed, reamp function ) - * - * @param pin gpio pin name - * @param function gpio pin mode, speed, remap function - */ -void pin_function(PinName pin, int function) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t mode = GD_PIN_MODE_GET(function); - uint32_t remap = GD_PIN_REMAP_GET(function); - uint32_t speed = GD_PIN_SPEED_GET(function); - uint32_t port = GD_PORT_GET(pin); - uint32_t gd_pin = 1 << GD_PIN_GET(pin); - - uint32_t gpio = gpio_clock_enable(port); - gpio_para_init(gpio, GD_GPIO_MODE[mode], GD_GPIO_SPEED[speed], gd_pin); - - if (remap != 0) { - rcu_periph_clock_enable(RCU_AF); - gpio_pin_remap_config(GD_GPIO_REMAP[remap], ENABLE); - } -} - -/** Only configure pin mode - * - * @param pin gpio pin name - * @param function gpio pin mode - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t port = GD_PORT_GET(pin); - uint32_t gd_pin = 1 << GD_PIN_GET(pin); - - uint32_t gpio = gpio_clock_enable(port); - if (mode != PullNone) { - gpio_mode_set(gpio, GD_GPIO_MODE[mode], gd_pin); - } -} - -/** configure gpio pin mode - * - * @param gpio_periph gpio port name - * @param mode gpio pin mode - * @param pin gpio pin number - */ -static void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pin) -{ - uint16_t i; - uint32_t temp_mode = 0U; - uint32_t reg = 0U; - - /* GPIO mode configuration */ - temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); - - /* configure the eight low port pins with GPIO_CTL0 */ - for (i = 0U; i < 8U; i++) { - if ((1U << i) & pin) { - reg = GPIO_CTL0(gpio_periph); - - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i, temp_mode); - - /* set IPD or IPU */ - if (GPIO_MODE_IPD == mode) { - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)pin; - } else { - /* set the corresponding OCTL bit */ - if (GPIO_MODE_IPU == mode) { - GPIO_BOP(gpio_periph) = (uint32_t)pin; - } - } - - /* set GPIO_CTL0 register */ - GPIO_CTL0(gpio_periph) = reg; - } - } - /* configure the eight high port pins with GPIO_CTL1 */ - for (i = 8U; i < 16U; i++) { - if ((1U << i) & pin) { - reg = GPIO_CTL1(gpio_periph); - - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i - 8U, temp_mode); - - /* set IPD or IPU */ - if (GPIO_MODE_IPD == mode) { - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)pin; - } else { - /* set the corresponding OCTL bit */ - if (GPIO_MODE_IPU == mode) { - GPIO_BOP(gpio_periph) = (uint32_t)pin; - } - } - - /* set GPIO_CTL1 register */ - GPIO_CTL1(gpio_periph) = reg; - } - } -} - - diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/port_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/port_api.c deleted file mode 100644 index 75f959be15e..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/port_api.c +++ /dev/null @@ -1,120 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t gpio_clock_enable(uint32_t port_idx); - -/** Get the pin name from the port's pin number - * - * @param port The port name - * @param pin_n The pin number within the specified port - * @return The pin name for the port's pin number - * BIT[7:4] port number - BIT[3:0] pin number - */ -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -/** Initilize the port - * - * @param obj The port object to initialize - * @param port The port name - * @param mask The bitmask to identify which bits in the port should be included (0 - ignore) - * @param dir The port direction - */ -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - uint32_t gpio = gpio_clock_enable(port_index); - - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &GPIO_ISTAT(gpio); - obj->reg_out = &GPIO_OCTL(gpio); - - port_dir(obj, dir); -} - -/** Set port direction (in/out) - * - * @param obj The port object - * @param dir The port direction to be set - */ -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { - if (obj->mask & (1 << i)) { - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), MODE_OUT_PP); - } else { - pin_function(port_pin(obj->port, i), MODE_IN_FLOATING); - } - } - } -} - -/** Set the input port mode - * - * @param obj The port object - * @param mode THe port mode to be set - */ -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { - if (obj->mask & (1 << i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -/** Write value to the port - * - * @param obj The port object - * @param value The value to be set - */ -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -/** Read the current value on the port - * - * @param obj The port object - * @return An integer with each bit corresponding to an associated port pin setting - */ -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/pwmout_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/pwmout_api.c deleted file mode 100644 index aa1288424cc..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/pwmout_api.c +++ /dev/null @@ -1,304 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -#define DEV_PWMOUT_APB_MASK 0x00010000U -#define DEV_PWMOUT_APB1 0U -#define DEV_PWMOUT_APB2 1U - -static uint32_t timer_get_clock(uint32_t timer_periph); - -static void dev_pwmout_init(pwmout_t *obj) -{ - timer_oc_parameter_struct timer_ocintpara; - timer_parameter_struct timer_initpara; - - MBED_ASSERT(obj); - uint32_t periph = obj->pwm; - - switch (periph) { - case TIMER0: - rcu_periph_clock_enable(RCU_TIMER0); - break; - - case TIMER1: - rcu_periph_clock_enable(RCU_TIMER1); - break; - - case TIMER2: - rcu_periph_clock_enable(RCU_TIMER2); - break; - - case TIMER3: - rcu_periph_clock_enable(RCU_TIMER3); - break; - - case TIMER4: - rcu_periph_clock_enable(RCU_TIMER4); - break; - - case TIMER7: - rcu_periph_clock_enable(RCU_TIMER7); - break; - case TIMER8: - rcu_periph_clock_enable(RCU_TIMER8); - break; - - case TIMER9: - rcu_periph_clock_enable(RCU_TIMER9); - break; - - case TIMER10: - rcu_periph_clock_enable(RCU_TIMER10); - break; - - case TIMER11: - rcu_periph_clock_enable(RCU_TIMER11); - break; - - case TIMER12: - rcu_periph_clock_enable(RCU_TIMER12); - break; - - case TIMER13: - rcu_periph_clock_enable(RCU_TIMER13); - break; - } - /* configure TIMER base function */ - timer_initpara.prescaler = 119; - timer_initpara.period = 9999; - timer_initpara.clockdivision = 0; - timer_initpara.counterdirection = TIMER_COUNTER_UP; - timer_initpara.alignedmode = TIMER_COUNTER_EDGE; - - timer_init(obj->pwm, &timer_initpara); - - /* configure TIMER channel output function */ - timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; - timer_ocintpara.outputstate = TIMER_CCX_ENABLE; - timer_ocintpara.outputnstate = TIMER_CCXN_ENABLE; - timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; - timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; - timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; - timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_HIGH; - timer_channel_output_config(obj->pwm, obj->ch, &timer_ocintpara); - timer_channel_output_mode_config(obj->pwm, obj->ch, TIMER_OC_MODE_PWM0); - timer_channel_output_fast_config(obj->pwm, obj->ch, TIMER_OC_FAST_DISABLE); - - timer_primary_output_config(obj->pwm, ENABLE); -} - -static uint8_t dev_pwmout_apb_check(uint32_t periph) -{ - uint8_t reval = DEV_PWMOUT_APB1; - - /* check peripherals belongs to APB1 or APB2 */ - if (DEV_PWMOUT_APB_MASK == (periph & DEV_PWMOUT_APB_MASK)) { - reval = DEV_PWMOUT_APB2; - } - - return reval; -} - -void pwmout_init(pwmout_t *obj, PinName pin) -{ - MBED_ASSERT(obj); - - obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(obj->pwm != (PWMName)NC); - - uint32_t function = pinmap_function(pin, PinMap_PWM); - MBED_ASSERT(function != (uint32_t)NC); - obj->ch = GD_PIN_CHANNEL_GET(function); - /* Peripheral initialization */ - dev_pwmout_init(obj); - /* pin function initialization */ - pinmap_pinout(pin, PinMap_PWM); -} - -void pwmout_free(pwmout_t *obj) -{ - timer_channel_output_state_config(obj->pwm, obj->ch, TIMER_CCX_DISABLE); -} - -void pwmout_write(pwmout_t *obj, float value) -{ - uint16_t period; - uint16_t pulse; - - timer_disable(obj->pwm); - /* overflow protection */ - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { - value = 1.0; - } - - period = TIMER_CAR(obj->pwm); - pulse = (uint16_t)(period * value); - - timer_channel_output_pulse_value_config(obj->pwm, obj->ch, pulse); - - timer_enable(obj->pwm); -} - -float pwmout_read(pwmout_t *obj) -{ - float value = 0; - uint16_t period; - uint16_t pulse; - - period = TIMER_CAR(obj->pwm); - - switch (obj->ch) { - case TIMER_CH_0: - pulse = TIMER_CH0CV(obj->pwm); - break; - - case TIMER_CH_1: - pulse = TIMER_CH1CV(obj->pwm); - break; - - case TIMER_CH_2: - pulse = TIMER_CH2CV(obj->pwm); - break; - - case TIMER_CH_3: - pulse = TIMER_CH3CV(obj->pwm); - break; - - default: - error("Error: pwm channel error! \r\n"); - } - - /* calculated waveform duty ratio */ - value = (float)(pulse) / (float)(period); - - if (value > (float)1.0) { - value = (float)1.0; - } - - return value; -} - -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t *obj, int us) -{ - - uint32_t ultemp = 0; - uint32_t timer_clk = 0; - uint32_t period = us - 1; - uint32_t prescaler; - float duty_ratio; - - duty_ratio = pwmout_read(obj); - - timer_disable(obj->pwm); - - timer_clk = timer_get_clock(obj->pwm); - - ultemp = (timer_clk / 1000000); - prescaler = ultemp; - obj->cnt_unit = 1; - - while (period > 0xFFFF) { - obj->cnt_unit = obj->cnt_unit << 1; - period = period >> 1; - prescaler = ultemp * obj->cnt_unit; - } - - if (prescaler > 0xFFFF) { - error("Error: TIMER prescaler value is overflow \r\n"); - } - - timer_autoreload_value_config(obj->pwm, period); - timer_prescaler_config(obj->pwm, prescaler - 1, TIMER_PSC_RELOAD_NOW); - - ultemp = duty_ratio * us; - - pwmout_pulsewidth_us(obj, ultemp); - - timer_enable(obj->pwm); -} - -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - uint32_t pulse; - uint32_t period; - - period = TIMER_CAR(obj->pwm); - pulse = us / obj->cnt_unit; - - if (pulse > period) { - pulse = period; - } - - timer_channel_output_pulse_value_config(obj->pwm, obj->ch, pulse); -} - -static uint32_t timer_get_clock(uint32_t timer_periph) -{ - uint32_t timerclk; - - if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || - (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || (TIMER10 == timer_periph)) { - /* get the current APB2 TIMER clock source */ - if (RCU_APB2_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB2PSC)) { - timerclk = rcu_clock_freq_get(CK_APB2); - } else { - timerclk = rcu_clock_freq_get(CK_APB2) * 2; - } - } else { - /* get the current APB1 TIMER clock source */ - if (RCU_APB1_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB1PSC)) { - timerclk = rcu_clock_freq_get(CK_APB1); - } else { - timerclk = rcu_clock_freq_get(CK_APB1) * 2; - } - } - - return timerclk; -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/rtc_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/rtc_api.c deleted file mode 100644 index 9300125759c..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/rtc_api.c +++ /dev/null @@ -1,114 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#if DEVICE_RTC - -#include "rtc_api.h" - -static uint8_t rtc_init_flag = 0; - -/** Initialize the RTC peripheral - * - * Powerup the RTC in perpetration for access. This function must be called - * before any other RTC functions ares called. This does not change the state - * of the RTC. It just enables access to it. - * - * @note This function is safe to call repeatedly - Tested by ::rtc_init_test - */ -void rtc_init(void) -{ - /* make sure RTC only init once */ - if (rtc_init_flag) { - return; - } - rtc_init_flag = 1; - - /* enable PMU and BKPI clocks */ - rcu_periph_clock_enable(RCU_BKPI); - rcu_periph_clock_enable(RCU_PMU); - /* allow access to BKP domain */ - pmu_backup_write_enable(); - - /* enable LXTAL */ - rcu_osci_on(RCU_LXTAL); - /* wait till LXTAL is ready */ - rcu_osci_stab_wait(RCU_LXTAL); - /* select RCU_LXTAL as RTC clock source */ - rcu_rtc_clock_config(RCU_RTCSRC_LXTAL); - /* enable RTC Clock */ - rcu_periph_clock_enable(RCU_RTC); - - /* wait for RTC registers synchronization */ - rtc_register_sync_wait(); - /* wait until last write operation on RTC registers has finished */ - rtc_lwoff_wait(); - /* set RTC prescaler: set RTC period to 1s */ - rtc_prescaler_set(32767); - /* wait until last write operation on RTC registers has finished */ - rtc_lwoff_wait(); -} - -/** Deinitialize RTC - * - * Powerdown the RTC in preparation for sleep, powerdown or reset. That should only - * affect the CPU domain and not the time keeping logic. - * After this function is called no other RTC functions should be called - * except for ::rtc_init. - */ -void rtc_free(void) -{ -} - -/** Check if the RTC has the time set and is counting - * - * @retval 0 The time reported by the RTC is not valid - * @retval 1 The time has been set the RTC is counting - */ -int rtc_isenabled(void) -{ - if (RESET == (RTC_CTL & RTC_CTL_RSYNF)) { - return 0; - } else { - return 1; - } -} - -/** Get the current time from the RTC peripheral - * - * @return The current time in seconds - * - * @note Some RTCs are not synchronized with the main clock. If - * this is the case with your RTC then you must read the RTC time - * in a loop to prevent reading the wrong time due to a glitch. - * The test ::rtc_glitch_test is intended to catch this bug. - */ -time_t rtc_read(void) -{ - return (rtc_counter_get()); -} - -/** Write the current time in seconds to the RTC peripheral - * - * @param t The current time to be set in seconds. - */ -void rtc_write(time_t t) -{ - rtc_counter_set((uint32_t)t); - rtc_lwoff_wait(); -} - -#endif /* DEVICE_RTC */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/serial_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/serial_api.c deleted file mode 100644 index 6b499d4b289..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/serial_api.c +++ /dev/null @@ -1,1104 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include -#include "PeripheralPins.h" - -#define USART_NUM (5) - -static uint32_t serial_irq_ids[USART_NUM] = {0}; -static rcu_periph_enum usart_clk[USART_NUM] = {RCU_USART0, RCU_USART1, RCU_USART2, RCU_UART3, RCU_UART4}; -static IRQn_Type usart_irq_n[USART_NUM] = {USART0_IRQn, USART1_IRQn, USART2_IRQn, UART3_IRQn, UART4_IRQn}; - -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -#if DEVICE_SERIAL_ASYNCH -#define GET_SERIAL_S(obj) (&((obj)->serial)) -#else -#define GET_SERIAL_S(obj) (obj) -#endif /* DEVICE_SERIAL_ASYNCH */ - -/** Initialize the USART peripheral. - * - * @param obj_s The serial object - */ -static void usart_init(struct serial_s *obj_s) -{ - if (obj_s->index >= USART_NUM) { - return; - } - - /* USART configuration */ - usart_deinit(obj_s->uart); - usart_word_length_set(obj_s->uart, obj_s->databits); - usart_baudrate_set(obj_s->uart, obj_s->baudrate); - usart_stop_bit_set(obj_s->uart, obj_s->stopbits); - usart_parity_config(obj_s->uart, obj_s->parity); -#if DEVICE_SERIAL_FC - if (obj_s->hw_flow_ctl == USART_HWCONTROL_NONE) { - usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_DISABLE); - usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_DISABLE); - } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_RTS) { - usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_DISABLE); - usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_ENABLE); - } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_CTS) { - usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_ENABLE); - usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_DISABLE); - } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_RTS_CTS) { - usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_ENABLE); - usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_ENABLE); - } -#endif /* DEVICE_SERIAL_FC */ - usart_receive_config(obj_s->uart, USART_RECEIVE_ENABLE); - usart_transmit_config(obj_s->uart, USART_TRANSMIT_ENABLE); - usart_enable(obj_s->uart); -} - -/** Initialize the serial peripheral. It sets the default parameters for serial - * peripheral, and configures its specifieds pins. - * - * @param obj The serial object - * @param tx The TX pin name - * @param rx The RX pin name - */ -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - p_obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(p_obj->uart != (UARTName)NC); - - /* enable UART peripheral clock */ - if (p_obj->uart == UART_0) { - p_obj->index = 0; - rcu_periph_clock_enable(usart_clk[p_obj->index]); - } else if (p_obj->uart == UART_1) { - p_obj->index = 1; - rcu_periph_clock_enable(usart_clk[p_obj->index]); - } else if (p_obj->uart == UART_2) { - p_obj->index = 2; - rcu_periph_clock_enable(usart_clk[p_obj->index]); - } else if (p_obj->uart == UART_3) { - p_obj->index = 3; - rcu_periph_clock_enable(usart_clk[p_obj->index]); - } else if (p_obj->uart == UART_4) { - p_obj->index = 4; - rcu_periph_clock_enable(usart_clk[p_obj->index]); - } - - /* configurte the pins */ - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - /* default UART parameters */ - p_obj->baudrate = 9600U; - p_obj->databits = USART_WL_8BIT; - p_obj->stopbits = USART_STB_1BIT; - p_obj->parity = USART_PM_NONE; - -#if DEVICE_SERIAL_FC - p_obj->hw_flow_ctl = USART_HWCONTROL_NONE; -#endif /* DEVICE_SERIAL_FC */ - - p_obj->pin_tx = tx; - p_obj->pin_rx = rx; - - p_obj->tx_state = OP_STATE_BUSY; - p_obj->rx_state = OP_STATE_BUSY; - - usart_init(p_obj); - - p_obj->tx_state = OP_STATE_READY; - p_obj->rx_state = OP_STATE_READY; - - if (p_obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -/** Release the serial peripheral, not currently invoked. It requires further - * resource management. - * - * @param obj The serial object - */ -void serial_free(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - rcu_periph_enum rcu_periph = usart_clk[p_obj->index]; - - /* reset USART and disable clock */ - usart_deinit(p_obj->uart); - rcu_periph_clock_disable(rcu_periph); - - serial_irq_ids[p_obj->index] = 0; - - /* reset the GPIO state */ - pin_function(p_obj->pin_tx, MODE_IN_FLOATING); - pin_function(p_obj->pin_rx, MODE_IN_FLOATING); -} - -/** Configure the baud rate - * - * @param obj The serial object - * @param baudrate The baud rate to be configured - */ -void serial_baud(serial_t *obj, int baudrate) -{ - uint16_t uen_flag = 0U; - struct serial_s *p_obj = GET_SERIAL_S(obj); - - /* store the UEN flag */ - uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; - - /* disable the USART first */ - usart_disable(p_obj->uart); - - usart_baudrate_set(p_obj->uart, baudrate); - - p_obj->baudrate = baudrate; - - /* restore the UEN flag */ - if (RESET != uen_flag) { - usart_enable(p_obj->uart); - } -} - -/** Configure the format. Set the number of bits, parity and the number of stop bits - * - * @param obj The serial object - * @param data_bits The number of data bits - * @param parity The parity - * @param stop_bits The number of stop bits - */ -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - uint16_t uen_flag = 0U; - struct serial_s *p_obj = GET_SERIAL_S(obj); - - /* store the UEN flag */ - uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; - - /* disable the UART clock first */ - usart_disable(p_obj->uart); - - /* configurate the UART parity */ - switch (parity) { - case ParityOdd: - p_obj->parity = USART_PM_ODD; - usart_parity_config(p_obj->uart, USART_PM_ODD); - break; - - case ParityEven: - p_obj->parity = USART_PM_EVEN; - usart_parity_config(p_obj->uart, USART_PM_EVEN); - break; - - case ParityForced0: - case ParityForced1: - default: - p_obj->parity = USART_PM_NONE; - usart_parity_config(p_obj->uart, USART_PM_NONE); - break; - } - - if (p_obj->parity == USART_PM_NONE) { - if (data_bits == 9) { - usart_word_length_set(p_obj->uart, USART_WL_9BIT); - } else if (data_bits == 8) { - usart_word_length_set(p_obj->uart, USART_WL_8BIT); - } else if (data_bits == 7) { - return; - } - } else { - if (data_bits == 9) { - return; - } else if (data_bits == 8) { - usart_word_length_set(p_obj->uart, USART_WL_9BIT); - } else if (data_bits == 7) { - usart_word_length_set(p_obj->uart, USART_WL_8BIT); - } - } - - if (stop_bits == 2) { - usart_stop_bit_set(p_obj->uart, USART_STB_2BIT); - } else { - usart_stop_bit_set(p_obj->uart, USART_STB_1BIT); - } - - /* restore the UEN flag */ - if (RESET != uen_flag) { - usart_enable(p_obj->uart); - } -} - -/** The serial interrupt handler registration - * - * @param obj The serial object - * @param handler The interrupt handler which will be invoked when the interrupt fires - * @param id The SerialBase object - */ -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - irq_handler = handler; - serial_irq_ids[p_obj->index] = id; -} - -/** This function handles USART interrupt handler - * - * @param usart_index The index of UART - * @param usart_periph The UART peripheral - */ -static void usart_irq(int usart_index, uint32_t usart_periph) -{ - if (serial_irq_ids[usart_index] != 0) { - if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_TC) != RESET) { - usart_interrupt_flag_clear(usart_periph, USART_INT_FLAG_TC); - irq_handler(serial_irq_ids[usart_index], TxIrq); - } - - if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_RBNE) != RESET) { - usart_interrupt_flag_clear(usart_periph, USART_INT_FLAG_RBNE); - irq_handler(serial_irq_ids[usart_index], RxIrq); - } - - if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_ERR_ORERR) != RESET) { - /* clear ORERR error flag by reading USART DATA register */ - USART_DATA(usart_periph); - } - - if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_ERR_NERR) != RESET) { - /* clear NERR error flag by reading USART DATA register */ - USART_DATA(usart_periph); - } - - if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_ERR_FERR) != RESET) { - /* clear FERR error flag by reading USART DATA register */ - USART_DATA(usart_periph); - } - - if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_PERR) != RESET) { - /* clear PERR error flag by reading USART DATA register */ - USART_DATA(usart_periph); - } - } -} - -/** This function handles USART0 interrupt handler - * - */ -static void usart0_irq(void) -{ - usart_irq(0, USART0); -} - -/** This function handles USART1 interrupt handler - * - */ -static void usart1_irq(void) -{ - usart_irq(1, USART1); -} - -/** This function handles USART2 interrupt handler - * - */ -static void usart2_irq(void) -{ - usart_irq(2, USART2); -} - -/** This function handles USART3 interrupt handler - * - */ -static void uart3_irq(void) -{ - usart_irq(3, UART3); -} - -/** This function handles USART4 interrupt handler - * - */ -static void uart4_irq(void) -{ - usart_irq(4, UART4); -} - -/** Configure serial interrupt. This function is used for word-approach - * - * @param obj The serial object - * @param irq The serial IRQ type (RX or TX) - * @param enable Set to non-zero to enable events, or zero to disable them - */ -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - if (p_obj->uart == USART0) { - irq_n = USART0_IRQn; - vector = (uint32_t)&usart0_irq; - } else if (p_obj->uart == USART1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&usart1_irq; - } else if (p_obj->uart == USART2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&usart2_irq; - } else if (p_obj->uart == UART3) { - irq_n = UART3_IRQn; - vector = (uint32_t)&uart3_irq; - } else if (p_obj->uart == UART4) { - irq_n = UART4_IRQn; - vector = (uint32_t)&uart4_irq; - } - - if (enable) { - if (irq == RxIrq) { - /* Rx IRQ */ - usart_interrupt_enable(p_obj->uart, USART_INT_RBNE); - } else { - /* Tx IRQ */ - usart_interrupt_enable(p_obj->uart, USART_INT_TBE); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - } else { - if (irq == RxIrq) { - /* Rx IRQ */ - usart_interrupt_disable(p_obj->uart, USART_INT_RBNE); - } else { - /* Tx IRQ */ - usart_interrupt_disable(p_obj->uart, USART_INT_TBE); - } - } -} - -/** Get character. This is a blocking call, waiting for a character - * - * @param obj The serial object - */ -int serial_getc(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - while (!serial_readable(obj)); - return (int)(usart_data_receive(p_obj->uart) & BITS(0, 7 + (p_obj->databits >> 12))); -} - -/** Send a character. This is a blocking call, waiting for a peripheral to be available - * for writing - * - * @param obj The serial object - * @param c The character to be sent - */ -void serial_putc(serial_t *obj, int c) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - while (!serial_writable(obj)); - usart_data_transmit(p_obj->uart, (int)((c) & BITS(0, 7 + (p_obj->databits >> 12)))); -} - -/** Check if the serial peripheral is readable - * - * @param obj The serial object - * @return Non-zero value if a character can be read, 0 if nothing to read - */ -int serial_readable(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - return (usart_flag_get(p_obj->uart, USART_FLAG_RBNE) != RESET) ? 1 : 0; -} - -/** Check if the serial peripheral is writable - * - * @param obj The serial object - * @return Non-zero value if a character can be written, 0 otherwise. - */ -int serial_writable(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - return (usart_flag_get(p_obj->uart, USART_FLAG_TBE) != RESET) ? 1 : 0; -} - -/** Clear the serial peripheral - * - * @param obj The serial object - */ -void serial_clear(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - p_obj->tx_count = 0U; - p_obj->rx_count = 0U; -} - -/** Set the break - * - * @param obj The serial object - */ -void serial_break_set(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - usart_send_break(p_obj->uart); -} - -/** Clear the break - * - * @param obj The serial object - */ -void serial_break_clear(serial_t *obj) -{ - /* do nothing */ -} - -/** Configure the TX pin for UART function. - * - * @param tx The pin name used for TX - */ -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} - -#if DEVICE_SERIAL_ASYNCH -/** - * Enable the serial events - * - * @param obj The serial object - * @param event The events to be configured - */ -static void serial_event_enable(serial_t *obj, int event) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - p_obj->events |= event; - -} - -/** - * Disable the serial events - * - * @param obj The serial object - * @param event The events to be configured - */ -static void serial_event_disable(serial_t *obj, int event) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - p_obj->events &= ~event; -} - -/** - * Preprocess the USART tx interrupt - * - * @param obj_s The serial object - * @param pData Pointer to tx buffer - * @param Size Size of tx buffer - * @return Returns the status - */ -static gd_status_enum usart_tx_interrupt_preprocess(struct serial_s *obj_s, uint8_t *pData, uint16_t Size) -{ - if (obj_s->tx_state == OP_STATE_READY) { - if ((pData == NULL) || (Size == 0U)) { - return GD_ERROR; - } - - obj_s->tx_buffer_ptr = pData; - obj_s->tx_count = Size; - obj_s->error_code = USART_ERROR_CODE_NONE; - obj_s->tx_state = OP_STATE_BUSY_TX; - - usart_interrupt_enable(obj_s->uart, USART_INT_TBE); - - return GD_OK; - } else { - return GD_BUSY; - } -} - -/** - * Preprocess the USART rx interrupt - * - * @param obj_s The serial object - * @param pData Pointer to rx buffer - * @param Size Size of rx buffer - * @return Returns the status - */ -static gd_status_enum usart_rx_interrupt_preprocess(struct serial_s *obj_s, uint8_t *pData, uint16_t Size) -{ - if (obj_s->rx_state == OP_STATE_READY) { - if ((pData == NULL) || (Size == 0U)) { - return GD_ERROR; - } - - obj_s->rx_buffer_ptr = pData; - obj_s->rx_size = Size; - obj_s->rx_count = Size; - obj_s->error_code = USART_ERROR_CODE_NONE; - obj_s->rx_state = OP_STATE_BUSY_RX; - - usart_interrupt_enable(obj_s->uart, USART_INT_PERR); - usart_interrupt_enable(obj_s->uart, USART_INT_ERR); - usart_interrupt_enable(obj_s->uart, USART_INT_RBNE); - - return GD_OK; - } else { - return GD_BUSY; - } -} - -/** Begin asynchronous TX transfer. The used buffer is specified in the serial object, - * tx_buff - * - * @param obj The serial object - * @param tx The transmit buffer - * @param tx_length The number of bytes to transmit - * @param tx_width Deprecated argument - * @param handler The serial handler - * @param event The logical OR of events to be registered - * @param hint A suggestion for how to use DMA with this transfer - * @return Returns number of data transfered, otherwise returns 0 - */ -int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - IRQn_Type irq = usart_irq_n[p_obj->index]; - - if ((tx_length == 0) || (tx_width != 8)) { - return 0; - } - - if (serial_tx_active(obj)) { - /* some transmit is in progress */ - return 0; - } - - obj->tx_buff.buffer = (void *)tx; - obj->tx_buff.length = tx_length; - obj->tx_buff.pos = 0; - - /* disable all events first */ - serial_event_disable(obj, SERIAL_EVENT_TX_ALL); - /* enable the specific event */ - serial_event_enable(obj, event); - - /* enable interrupt */ - /* clear pending IRQ */ - NVIC_ClearPendingIRQ(irq); - /* disable the IRQ first */ - NVIC_DisableIRQ(irq); - /* set the priority and vector */ - NVIC_SetPriority(irq, 1); - NVIC_SetVector(irq, (uint32_t)handler); - /* enable IRQ */ - NVIC_EnableIRQ(irq); - - if (usart_tx_interrupt_preprocess(p_obj, (uint8_t *)tx, tx_length) != GD_OK) { - return 0; - } - - return tx_length; -} - -/** Begin asynchronous RX transfer (enable interrupt for data collecting) - * The used buffer is specified in the serial object - rx_buff - * - * @param obj The serial object - * @param rx The receive buffer - * @param rx_length The number of bytes to receive - * @param rx_width Deprecated argument - * @param handler The serial handler - * @param event The logical OR of events to be registered - * @param handler The serial handler - * @param char_match A character in range 0-254 to be matched - * @param hint A suggestion for how to use DMA with this transfer - */ -void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - IRQn_Type irq = usart_irq_n[p_obj->index]; - - if ((rx_length == 0) || (rx_width != 8)) { - return; - } - - /* disable all events first */ - serial_event_disable(obj, SERIAL_EVENT_RX_ALL); - /* enable the specific event */ - serial_event_enable(obj, event); - - obj->char_match = char_match; - - if (serial_rx_active(obj)) { - /* some reception is in progress */ - return; - } - - obj->rx_buff.buffer = rx; - obj->rx_buff.length = rx_length; - obj->rx_buff.pos = 0; - - /* enable interrupt */ - /* clear pending IRQ */ - NVIC_ClearPendingIRQ(irq); - /* disable the IRQ first */ - NVIC_DisableIRQ(irq); - /* set the priority(higher than Tx) and vector */ - NVIC_SetPriority(irq, 0); - NVIC_SetVector(irq, (uint32_t)handler); - /* enable IRQ */ - NVIC_EnableIRQ(irq); - - usart_rx_interrupt_preprocess(p_obj, (uint8_t *)rx, rx_length); -} - -/** Attempts to determine if the serial peripheral is already in use for TX - * - * @param obj The serial object - * @return Non-zero if the RX transaction is ongoing, 0 otherwise - */ -uint8_t serial_tx_active(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - return ((p_obj->tx_state == OP_STATE_BUSY_TX) ? 1 : 0); -} - -/** Attempts to determine if the serial peripheral is already in use for RX - * - * @param obj The serial object - * @return Non-zero if the RX transaction is ongoing, 0 otherwise - */ -uint8_t serial_rx_active(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - return ((p_obj->rx_state == OP_STATE_BUSY_RX) ? 1 : 0); -} - -/** Handle the serial rx interrupt - * - * @param obj_s The serial object - * @return Returns the status - */ -static gd_status_enum usart_rx_interrupt(struct serial_s *obj_s) -{ - uint16_t *temp; - - if (obj_s->rx_state == OP_STATE_BUSY_RX) { - if (obj_s->databits == USART_WL_9BIT) { - temp = (uint16_t *) obj_s->rx_buffer_ptr; - if (obj_s->parity == USART_PM_NONE) { - /* 9-bit data, none parity bit */ - *temp = (uint16_t)(USART_DATA(obj_s->uart) & (uint16_t)0x01FF); - obj_s->rx_buffer_ptr += 2U; - } else { - /* 9-bit data, with parity bit */ - *temp = (uint16_t)(USART_DATA(obj_s->uart) & (uint16_t)0x00FF); - obj_s->rx_buffer_ptr += 1U; - } - } else { - if (obj_s->parity == USART_PM_NONE) { - /* 8-bit data, none parity bit */ - *obj_s->rx_buffer_ptr++ = (uint8_t)(USART_DATA(obj_s->uart) & (uint8_t)0x00FF); - } else { - /* 8-bit data, with parity bit */ - *obj_s->rx_buffer_ptr++ = (uint8_t)(USART_DATA(obj_s->uart) & (uint8_t)0x007F); - } - } - - if (--obj_s->rx_count == 0U) { - usart_interrupt_disable(obj_s->uart, USART_INT_RBNE); - usart_interrupt_disable(obj_s->uart, USART_INT_PERR); - usart_interrupt_disable(obj_s->uart, USART_INT_ERR); - - obj_s->rx_state = OP_STATE_READY; - } - - return GD_OK; - } else { - return GD_BUSY; - } -} - -/** Handle the serial tx interrupt - * - * @param obj_s The serial object - * @return Returns the status - */ -static gd_status_enum usart_tx_interrupt(struct serial_s *obj_s) -{ - uint16_t *temp; - - if (obj_s->tx_state == OP_STATE_BUSY_TX) { - if (obj_s->databits == USART_WL_9BIT) { - temp = (uint16_t *) obj_s->tx_buffer_ptr; - USART_DATA(obj_s->uart) = (uint16_t)(*temp & (uint16_t)0x01FF); - if (obj_s->parity == USART_PM_NONE) { - obj_s->tx_buffer_ptr += 2U; - } else { - obj_s->tx_buffer_ptr += 1U; - } - } else { - USART_DATA(obj_s->uart) = (uint8_t)(*obj_s->tx_buffer_ptr++ & (uint8_t)0x00FF); - } - - if (--obj_s->tx_count == 0U) { - /* disable USART_INT_TBE interrupt */ - usart_interrupt_disable(obj_s->uart, USART_INT_TBE); - - /* enable USART_INT_TC interrupt */ - usart_interrupt_enable(obj_s->uart, USART_INT_TC); - } - - return GD_OK; - } else { - return GD_BUSY; - } -} - -/** Handle the serial tx complete interrupt - * - * @param obj_s The serial object - */ -static void usart_tx_complete_interrupt(struct serial_s *obj_s) -{ - usart_interrupt_disable(obj_s->uart, USART_INT_TC); - - obj_s->tx_state = OP_STATE_READY; -} - -/** Handle all the serial interrupt request - * - * @param obj_s The serial object - */ -static void usart_irq_handler(struct serial_s *obj_s) -{ - uint32_t err_flags = 0U; - - /* no error occurs */ - err_flags = (USART_STAT0(obj_s->uart) & (uint32_t)(USART_FLAG_PERR | USART_FLAG_FERR | USART_FLAG_ORERR | USART_FLAG_NERR)); - if (err_flags == RESET) { - /* check whether USART is in receiver mode or not */ - if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_RBNE) != RESET) { - usart_rx_interrupt(obj_s); - - return; - } - } - - if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_TBE) != RESET) { - usart_tx_interrupt(obj_s); - return; - } - - if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_TC) != RESET) { - usart_tx_complete_interrupt(obj_s); - return; - } -} - -/** The asynchronous TX and RX handler. - * - * @param obj The serial object - * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0 - */ -int serial_irq_handler_asynch(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - volatile uint8_t i = 0; - volatile int return_val = 0; - uint8_t *p_buf = (uint8_t *)(obj->rx_buff.buffer); - - if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_PERR) != RESET) { - /* clear PERR error flag by reading USART DATA register */ - USART_DATA(p_obj->uart); - - return_val |= (SERIAL_EVENT_RX_PARITY_ERROR & p_obj->events); - p_obj->error_code |= USART_ERROR_CODE_PERR; - } - - if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_ERR_FERR) != RESET) { - /* clear FERR error flag by reading USART DATA register */ - USART_DATA(p_obj->uart); - - return_val |= (SERIAL_EVENT_RX_FRAMING_ERROR & p_obj->events); - p_obj->error_code |= USART_ERROR_CODE_FERR; - } - - if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_ERR_ORERR) != RESET) { - /* clear ORERR error flag by reading USART DATA register */ - USART_DATA(p_obj->uart); - - return_val |= (SERIAL_EVENT_RX_OVERRUN_ERROR & p_obj->events); - p_obj->error_code |= USART_ERROR_CODE_ORERR; - } - - if (return_val & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR | - SERIAL_EVENT_RX_OVERRUN_ERROR)) { - return return_val; - } - - if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_TC) != RESET) { - if ((p_obj->events & SERIAL_EVENT_TX_COMPLETE) != 0) { - return_val |= (SERIAL_EVENT_TX_COMPLETE & p_obj->events); - } - } - - usart_irq_handler(p_obj); - - if (p_obj->rx_size != 0) { - obj->rx_buff.pos = p_obj->rx_size - p_obj->rx_count; - } - - if ((p_obj->rx_count == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { - return_val |= (SERIAL_EVENT_RX_COMPLETE & p_obj->events); - } - - if (p_obj->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { - if (p_buf != NULL) { - for (i = 0; i < obj->rx_buff.pos; i++) { - if (p_buf[i] == obj->char_match) { - obj->rx_buff.pos = i; - return_val |= (SERIAL_EVENT_RX_CHARACTER_MATCH & p_obj->events); - serial_rx_abort_asynch(obj); - break; - } - } - } - } - - return return_val; -} - -/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and - * flushes the TX hardware buffer if TX FIFO is used - * - * @param obj The serial object - */ -void serial_tx_abort_asynch(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - usart_interrupt_disable(p_obj->uart, USART_INT_TC); - usart_interrupt_disable(p_obj->uart, USART_INT_TBE); - - usart_flag_clear(p_obj->uart, USART_FLAG_TC); - - p_obj->tx_count = 0; - p_obj->tx_state = OP_STATE_READY; -} - -/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and - * flushes the RX hardware buffer if RX FIFO is used - * - * @param obj The serial object - */ -void serial_rx_abort_asynch(serial_t *obj) -{ - struct serial_s *p_obj = GET_SERIAL_S(obj); - - /* disable interrupts */ - usart_interrupt_disable(p_obj->uart, USART_INT_RBNE); - usart_interrupt_disable(p_obj->uart, USART_INT_PERR); - usart_interrupt_disable(p_obj->uart, USART_INT_ERR); - - /* clear USART_FLAG_RBNE flag */ - usart_flag_clear(p_obj->uart, USART_FLAG_RBNE); - - /* clear errors flag by reading USART STATx register and then USART DATA register */ - usart_flag_get(p_obj->uart, USART_FLAG_PERR); - usart_flag_get(p_obj->uart, USART_FLAG_FERR); - usart_flag_get(p_obj->uart, USART_FLAG_ORERR); - USART_DATA(p_obj->uart); - - /* reset rx transfer count */ - p_obj->rx_count = 0; - - /* reset rx state */ - p_obj->rx_state = OP_STATE_READY; -} - -#endif /* DEVICE_SERIAL_ASYNCH */ - -#if DEVICE_SERIAL_FC -/** Configure the serial for the flow control. It sets flow control in the hardware - * if a serial peripheral supports it, otherwise software emulation is used. - * - * @param obj The serial object - * @param type The type of the flow control. Look at the available FlowControl types. - * @param rxflow The TX pin name - * @param txflow The RX pin name - */ -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - uint16_t uen_flag = 0U; - struct serial_s *p_obj = GET_SERIAL_S(obj); - - /* store the UEN flag */ - uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; - - UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); - UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); - - p_obj->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); - MBED_ASSERT(p_obj->uart != (UARTName)NC); - - /* disable USART to modify CTS/RTS configuration */ - usart_disable(p_obj->uart); - - if (type == FlowControlNone) { - p_obj->hw_flow_ctl = USART_HWCONTROL_NONE; - usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_DISABLE); - usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_DISABLE); - } - - if (type == FlowControlRTS) { - MBED_ASSERT(uart_rts != (UARTName)NC); - p_obj->hw_flow_ctl = USART_HWCONTROL_RTS; - p_obj->pin_rts = rxflow; - pinmap_pinout(rxflow, PinMap_UART_RTS); - usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_DISABLE); - usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_ENABLE); - } - - if (type == FlowControlCTS) { - MBED_ASSERT(uart_cts != (UARTName)NC); - p_obj->hw_flow_ctl = USART_HWCONTROL_CTS; - p_obj->pin_cts = txflow; - pinmap_pinout(txflow, PinMap_UART_CTS); - usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_DISABLE); - usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_ENABLE); - } - - if (type == FlowControlRTSCTS) { - MBED_ASSERT(uart_rts != (UARTName)NC); - MBED_ASSERT(uart_cts != (UARTName)NC); - p_obj->hw_flow_ctl = USART_HWCONTROL_RTS_CTS; - p_obj->pin_rts = rxflow; - p_obj->pin_cts = txflow; - pinmap_pinout(txflow, PinMap_UART_CTS); - pinmap_pinout(rxflow, PinMap_UART_RTS); - usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_ENABLE); - usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_ENABLE); - } - - /* restore the UEN flag */ - if (RESET != uen_flag) { - usart_enable(p_obj->uart); - } -} - -#endif /* DEVICE_SERIAL_FC */ - -#if DEVICE_SLEEP -/** Check whether the serial is in busy state - * - * @return 0: all the serial is free to use, 1: some serial is in busy in transfer - */ -int serial_busy_state_check(void) -{ -#if defined(USART0) - if ((USART_CTL0(USART0) & USART_CTL0_UEN) && !(USART_STAT0(USART0) & USART_STAT0_TC)) { - return 1; - } -#endif - -#if defined(USART1) - if ((USART_CTL0(USART1) & USART_CTL0_UEN) && !(USART_STAT0(USART1) & USART_STAT0_TC)) { - return 1; - } -#endif - -#if defined(USART2) - if ((USART_CTL0(USART2) & USART_CTL0_UEN) && !(USART_STAT0(USART2) & USART_STAT0_TC)) { - return 1; - } -#endif - -#if defined(UART3) - if ((USART_CTL0(UART3) & USART_CTL0_UEN) && !(USART_STAT0(UART3) & USART_STAT0_TC)) { - return 1; - } -#endif - -#if defined(UART4) - if ((USART_CTL0(UART4) & USART_CTL0_UEN) && !(USART_STAT0(UART4) & USART_STAT0_TC)) { - return 1; - } -#endif - - /* no serial is in busy state */ - return 0; -} -#endif /* DEVICE_SLEEP */ - -#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/sleep.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/sleep.c deleted file mode 100644 index 41f1e66e78f..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/sleep.c +++ /dev/null @@ -1,160 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#if DEVICE_SLEEP - -#include "sleep_api.h" -#include "us_ticker_api.h" -#include "mbed_critical.h" -#include "mbed_error.h" - -extern void ticker_timer_data_save(void); -extern void ticker_timer_data_restore(void); -extern int serial_busy_state_check(void); - -/*! - \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_120m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { - while (1) { - } - } - - FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); - - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); -#ifdef HXTAL_VALUE_8M - /* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10); -#elif defined (HXTAL_VALUE_25M) - /* CK_PREDIV0 = (CK_HXTAL)/5 *8/10 = 4 MHz */ - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); -#endif - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while ((RCU_CTL & RCU_CTL_PLL1STB) == 0U) { - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} - - -/** Send the microcontroller to sleep - * - * The processor is setup ready for sleep, and sent to sleep. In this mode, the - * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates - * dynamic power used by the processor, memory systems and buses. The processor, peripheral and - * memory state are maintained, and the peripherals continue to work and can generate interrupts. - * - * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. - * - * The wake-up time shall be less than 10 us. - * - */ -void hal_sleep(void) -{ - /* Disable Interrupts */ - core_util_critical_section_enter(); - - /* Enter SLEEP mode */ - pmu_to_sleepmode(WFI_CMD); - - /* Enable Interrupts */ - core_util_critical_section_exit(); -} - - -/** Send the microcontroller to deep sleep - * - * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode - * has the same sleep features as sleep plus it powers down peripherals and high frequency clocks. - * All state is still maintained. - * - * The processor can only be woken up by low power ticker, RTC, an external interrupt on a pin or a watchdog timer. - * - * The wake-up time shall be less than 10 ms. - */ -void hal_deepsleep(void) -{ - if (0 != serial_busy_state_check()) { - return; - } - - /* Disable Interrupts */ - core_util_critical_section_enter(); - - ticker_timer_data_save(); - - /* Enter DEEP SLEEP mode */ - rcu_periph_clock_enable(RCU_PMU); - pmu_to_deepsleepmode(PMU_LDO_NORMAL, WFI_CMD); - - /* Reconfigure the PLL after weak up */ - system_clock_120m_hxtal(); - - ticker_timer_data_restore(); - - /* Enable Interrupts */ - core_util_critical_section_exit(); -} - -#endif /* DEVICE_SLEEP */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/spi_api.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/spi_api.c deleted file mode 100644 index 128064523d7..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/spi_api.c +++ /dev/null @@ -1,418 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "mbed_error.h" -#include "spi_api.h" - -#if DEVICE_SPI -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -#define SPI_S(obj) (( struct spi_s *)(obj)) - -/** Get the frequency of SPI clock source - * - * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral - * @param[out] spi_freq The SPI clock source freguency - * @param[in] obj The SPI object - */ -static int dev_spi_clock_source_frequency_get(spi_t *obj) -{ - int spi_freq = 0; - struct spi_s *spiobj = SPI_S(obj); - - switch ((int)spiobj->spi) { - case SPI0: - /* clock source is APB2 */ - spi_freq = rcu_clock_freq_get(CK_APB2); - break; - case SPI1: - /* clock source is APB1 */ - spi_freq = rcu_clock_freq_get(CK_APB1); - break; - case SPI2: - /* clock source is APB1 */ - spi_freq = rcu_clock_freq_get(CK_APB1); - break; - default: - error("SPI clock source frequency get error"); - break; - } - return spi_freq; -} - -/** Initialize the SPI structure - * - * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral - * @param[out] obj The SPI object to initialize - */ -static void dev_spi_struct_init(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - - spi_disable(spiobj->spi); - spi_para_init(spiobj->spi, &obj->spi_struct); - spi_enable(spiobj->spi); -} - -/** Initialize the SPI peripheral - * - * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral - * @param[out] obj The SPI object to initialize - * @param[in] mosi The pin to use for MOSI - * @param[in] miso The pin to use for MISO - * @param[in] sclk The pin to use for SCLK - * @param[in] ssel The pin to use for SSEL - */ -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - struct spi_s *spiobj = SPI_S(obj); - - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - /* return SPIName according to PinName */ - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(spiobj->spi != (SPIName)NC); - - /* Set iqr type */ - if (spiobj->spi == SPI0) { - rcu_periph_clock_enable(RCU_SPI0); - spiobj->spi_irq = SPI0_IRQn; - } - if (spiobj->spi == SPI1) { - rcu_periph_clock_enable(RCU_SPI1); - spiobj->spi_irq = SPI1_IRQn; - } - if (spiobj->spi == SPI2) { - rcu_periph_clock_enable(RCU_SPI2); - spiobj->spi_irq = SPI2_IRQn; - } - - /* config GPIO mode of SPI pins */ - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - spiobj->pin_miso = miso; - spiobj->pin_mosi = mosi; - spiobj->pin_sclk = sclk; - spiobj->pin_ssel = ssel; - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - spiobj->spi_struct.nss = SPI_NSS_HARD; - spi_nss_output_enable(spiobj->spi); - } else { - spiobj->spi_struct.nss = SPI_NSS_SOFT; - } - - spiobj->spi_struct.device_mode = SPI_MASTER; - spiobj->spi_struct.prescale = SPI_PSC_256; - spiobj->spi_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spiobj->spi_struct.frame_size = SPI_FRAMESIZE_8BIT; - spiobj->spi_struct.endian = SPI_ENDIAN_MSB; - - dev_spi_struct_init(obj); -} - -/** Release a SPI object - * - * TODO: spi_free is currently unimplemented - * This will require reference counting at the C++ level to be safe - * - * Return the pins owned by the SPI object to their reset state - * Disable the SPI peripheral - * Disable the SPI clock - * @param[in] obj The SPI object to deinitialize - */ -void spi_free(spi_t *obj) -{ - struct spi_s *spiobj = SPI_S(obj); - spi_disable(spiobj->spi); - - /* Disable and deinit SPI */ - if (spiobj->spi == SPI0) { - spi_i2s_deinit(SPI0); - rcu_periph_clock_disable(RCU_SPI0); - } - if (spiobj->spi == SPI1) { - spi_i2s_deinit(SPI1); - rcu_periph_clock_disable(RCU_SPI1); - } - if (spiobj->spi == SPI2) { - spi_i2s_deinit(SPI2); - rcu_periph_clock_disable(RCU_SPI2); - } - /* Deinit GPIO mode of SPI pins */ - pin_function(spiobj->pin_miso, MODE_IN_FLOATING); - pin_function(spiobj->pin_mosi, MODE_IN_FLOATING); - pin_function(spiobj->pin_sclk, MODE_IN_FLOATING); - if (spiobj->spi_struct.nss != SPI_NSS_SOFT) { - pin_function(spiobj->pin_ssel, MODE_IN_FLOATING); - } -} - -/** Configure the SPI format - * - * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. - * The default bit order is MSB. - * @param[in,out] obj The SPI object to configure - * @param[in] bits The number of bits per frame - * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) - * @param[in] slave Zero for master mode or non-zero for slave mode - */ -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - struct spi_s *spiobj = SPI_S(obj); - - spiobj->spi_struct.frame_size = (bits == 16) ? SPI_FRAMESIZE_16BIT : SPI_FRAMESIZE_8BIT; - /* Config polarity and phase of SPI */ - switch (mode) { - case 0: - spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - break; - case 1: - spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; - break; - case 2: - spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; - break; - default: - spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; - - break; - } - - if (spiobj->spi_struct.nss != SPI_NSS_SOFT) { - if (slave) { - pin_function(spiobj->pin_mosi, MODE_IN_FLOATING); - pin_function(spiobj->pin_sclk, MODE_IN_FLOATING); - pin_function(spiobj->pin_ssel, MODE_IN_FLOATING); - spi_nss_output_disable(spiobj->spi); - } - } - /* Select SPI as master or slave */ - spiobj->spi_struct.device_mode = (slave) ? SPI_SLAVE : SPI_MASTER; - - dev_spi_struct_init(obj); -} - -static const uint16_t baudrate_prescaler_table[] = {SPI_PSC_2, - SPI_PSC_4, - SPI_PSC_8, - SPI_PSC_16, - SPI_PSC_32, - SPI_PSC_64, - SPI_PSC_128, - SPI_PSC_256 - }; - -/** Set the SPI baud rate - * - * Actual frequency may differ from the desired frequency due to available dividers and bus clock - * Configures the SPI peripheral's baud rate - * @param[in,out] obj The SPI object to configure - * @param[in] hz The baud rate in Hz - */ -void spi_frequency(spi_t *obj, int hz) -{ - struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; - uint8_t prescaler_rank = 0; - uint8_t last_index = (sizeof(baudrate_prescaler_table) / sizeof(baudrate_prescaler_table[0])) - 1; - - spi_hz = dev_spi_clock_source_frequency_get(obj) / 2; - - /* Config SPI prescaler according to input frequency*/ - while ((spi_hz > hz) && (prescaler_rank < last_index)) { - spi_hz = spi_hz / 2; - prescaler_rank++; - } - - spiobj->spi_struct.prescale = baudrate_prescaler_table[prescaler_rank]; - dev_spi_struct_init(obj); -} - -/** Write a block out in master mode and receive a value - * - * The total number of bytes sent and received will be the maximum of - * tx_length and rx_length. The bytes written will be padded with the - * value 0xff. - * - * @param[in] obj The SPI peripheral to use for sending - * @param[in] tx_buffer Pointer to the byte-array of data to write to the device - * @param[in] tx_length Number of bytes to write, may be zero - * @param[in] rx_buffer Pointer to the byte-array of data to read from the device - * @param[in] rx_length Number of bytes to read, may be zero - * @param[in] write_fill Default data transmitted while performing a read - * @returns - * The number of bytes written and read from the device. This is - * maximum of tx_length and rx_length. - */ -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - return total; -} - -/** Write a byte out in master mode and receive a value - * - * @param[in] obj The SPI peripheral to use for sending - * @param[in] value The value to send - * @return Returns the value received during send - */ -int spi_master_write(spi_t *obj, int value) -{ - int count = 0; - struct spi_s *spiobj = SPI_S(obj); - - /* wait the SPI transmit buffer is empty */ - while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TBE)) && (count++ < 1000)); - if (count >= 1000) { - return -1; - } else { - spi_i2s_data_transmit(spiobj->spi, value); - } - - count = 0; - /* wait the SPI receive buffer is not empty */ - while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE)) && (count++ < 1000)); - if (count >= 1000) { - return -1; - } else { - return spi_i2s_data_receive(spiobj->spi); - } - -} - -/** Check if a value is available to read - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if a value is available - */ -int spi_slave_receive(spi_t *obj) -{ - int status; - struct spi_s *spiobj = SPI_S(obj); - /* check whether or not the SPI receive buffer is empty */ - status = ((spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE) != RESET) ? 1 : 0); - return status; -} - -/** Get a received value out of the SPI receive buffer in slave mode - * - * Blocks until a value is available - * @param[in] obj The SPI peripheral to read - * @return The value received - */ -int spi_slave_read(spi_t *obj) -{ - int count = 0; - struct spi_s *spiobj = SPI_S(obj); - /* wait the SPI receive buffer is not empty */ - while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE)) && (count++ < 1000)); - if (count >= 1000) { - return -1; - } else { - return spi_i2s_data_receive(spiobj->spi); - } -} - -/** Write a value to the SPI peripheral in slave mode - * - * Blocks until the SPI peripheral can be written to - * @param[in] obj The SPI peripheral to write - * @param[in] value The value to write - */ -void spi_slave_write(spi_t *obj, int value) -{ - struct spi_s *spiobj = SPI_S(obj); - /* wait the SPI transmit buffer is empty */ - while (RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TBE)); - spi_i2s_data_transmit(spiobj->spi, value); -} - -/** Checks if the specified SPI peripheral is in use - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if the peripheral is currently transmitting - */ -int spi_busy(spi_t *obj) -{ - int status; - struct spi_s *spiobj = SPI_S(obj); - /* check whether or not the SPI is busy */ - status = ((spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TRANS) != RESET) ? 1 : 0); - return status; -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32E10X/us_ticker.c b/targets/TARGET_GigaDevice/TARGET_GD32E10X/us_ticker.c deleted file mode 100644 index 57dce4d7581..00000000000 --- a/targets/TARGET_GigaDevice/TARGET_GD32E10X/us_ticker.c +++ /dev/null @@ -1,388 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 GigaDevice Semiconductor Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gd32e10x.h" -#include "us_ticker_api.h" -#include "PeripheralNames.h" -#include "hal_tick.h" - -#if TICKER_TIMER_WIDTH_BIT == 16 -uint32_t time_before; -uint32_t total_elapsed_time; -#endif - -/* this variable is set to 1 at the end of mbed_sdk_init function. -the ticker_read_us() function must not be called until the mbed_sdk_init is terminated */ -extern int mbed_sdk_inited; -uint32_t ticker_timer_cnt; -uint32_t ticker_timer_ch0cv; -uint32_t ticker_timer_dmainten; - -void ticker_timer_init(void); -#if TICKER_TIMER_WIDTH_BIT == 16 -void ticker_16bits_timer_init(void); -#else -void ticker_32bits_timer_init(void); -#endif -void ticker_timer_irq_handler(void); -/* get TIMER clock */ -static uint32_t timer_get_clock(uint32_t timer_periph); -uint32_t ticker_tick_get(void); -void ticker_timer_data_save(void); -void ticker_timer_data_save(void); -void ticker_timer_data_restore(void); - -void ticker_timer_init(void) -{ -#if TICKER_TIMER_WIDTH_BIT == 16 - ticker_16bits_timer_init(); -#else - ticker_32bits_timer_init(); -#endif -} - -/** get tick - * - * @return the tick - */ -uint32_t ticker_tick_get(void) -{ -#if TICKER_TIMER_WIDTH_BIT == 16 - uint32_t new_time; - if (mbed_sdk_inited) { - /* Apply the latest time recorded just before the sdk is inited */ - new_time = ticker_read_us(get_us_ticker_data()) + time_before; - time_before = 0; - return (new_time / 1000); - } else { - /* Prevent small values from subtracting large ones - example: - 0x0010-0xFFEE=FFFF0022 , (0xFFFF-0xFFEE+0x10+1=0x22,1 mean CNT=0 tick) - FFFF0022 & 0xFFFF = 0022 - */ - new_time = us_ticker_read(); - total_elapsed_time += (new_time - time_before) & 0xFFFF; - time_before = new_time; - return (total_elapsed_time / 1000); - } -#else // 32-bit timer - if (mbed_sdk_inited) { - return (ticker_read_us(get_us_ticker_data()) / 1000); - } else { - return (us_ticker_read() / 1000); - } -#endif -} - -/** Get frequency and counter bits of this ticker. - */ -const ticker_info_t *us_ticker_get_info() -{ - static const ticker_info_t info = { - 1000000, - TICKER_TIMER_WIDTH_BIT - }; - return &info; -} - - - -/* config for 32bits TIMER */ -#if TICKER_TIMER_WIDTH_BIT == 16 -/** config the interrupt handler - */ -void ticker_timer_irq_handler(void) -{ - if (SET == timer_interrupt_flag_get(TICKER_TIMER, TIMER_INT_FLAG_CH0)) { - timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); - us_ticker_irq_handler(); - } -} - -/** initialize the TIMER - */ -void ticker_16bits_timer_init(void) -{ - timer_parameter_struct timer_initpara; - uint32_t timer_clk = timer_get_clock(TICKER_TIMER); - - /* enable ticker timer clock */ - TICKER_TIMER_RCU_CLOCK_ENABLE; - - /* reset ticker timer peripheral */ - TICKER_TIMER_RESET_ENABLE; - TICKER_TIMER_RESET_DISABLE; - - /* TICKER_TIMER configuration */ - timer_initpara.prescaler = (uint32_t)(timer_clk / 1000000) - 1;; - timer_initpara.alignedmode = TIMER_COUNTER_EDGE; - timer_initpara.counterdirection = TIMER_COUNTER_UP; - timer_initpara.period = 0xFFFF; - timer_initpara.clockdivision = TIMER_CKDIV_DIV1; - timer_initpara.repetitioncounter = 0; - timer_init(TICKER_TIMER, &timer_initpara); - - /* auto-reload preload disable */ - timer_auto_reload_shadow_disable(TICKER_TIMER); - - /* configure TIMER channel enable state */ - timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); - - /* configure TIMER primary output function */ - timer_primary_output_config(TICKER_TIMER, ENABLE); - - timer_enable(TICKER_TIMER); - - /* Output compare channel 0 interrupt for mbed timeout */ - NVIC_SetVector(TICKER_TIMER_IRQ, (uint32_t)ticker_timer_irq_handler); - NVIC_EnableIRQ(TICKER_TIMER_IRQ); - - /* if define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json or other file, - hold the TICKER_TIMER counter for debug when core halted - */ -#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TICKER_TIMER_DEBUG_STOP) - TICKER_TIMER_DEBUG_STOP; -#endif - - timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); - - /* used by ticker_tick_get() */ - time_before = 0; - total_elapsed_time = 0; -} -/* config for 32bits TIMER */ -#else -/** config the interrupt handler - */ -void ticker_timer_irq_handler(void) -{ - if (SET == timer_interrupt_flag_get(TICKER_TIMER, TIMER_INT_FLAG_CH0)) { - timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); - us_ticker_irq_handler(); - } -} - -/** initialize the TIMER - */ -void ticker_32bits_timer_init(void) -{ - timer_parameter_struct timer_initpara; - uint32_t timer_clk = timer_get_clock(TICKER_TIMER); - - /* enable ticker timer clock */ - TICKER_TIMER_RCU_CLOCK_ENABLE; - - /* reset ticker timer peripheral */ - TICKER_TIMER_RESET_ENABLE; - TICKER_TIMER_RESET_DISABLE; - - /* TICKER_TIMER configuration */ - timer_initpara.prescaler = (uint32_t)(timer_clk / 1000000) - 1;; - timer_initpara.alignedmode = TIMER_COUNTER_EDGE; - timer_initpara.counterdirection = TIMER_COUNTER_UP; - timer_initpara.period = 0xFFFFFFFF; - timer_initpara.clockdivision = TIMER_CKDIV_DIV1; - timer_initpara.repetitioncounter = 0; - timer_init(TICKER_TIMER, &timer_initpara); - - /* auto-reload preload disable */ - timer_auto_reload_shadow_disable(TICKER_TIMER); - - /* configure TIMER channel enable state */ - timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); - - /* configure TIMER primary output function */ - timer_primary_output_config(TICKER_TIMER, ENABLE); - - timer_enable(TICKER_TIMER); - - /* Output compare channel 0 interrupt for mbed timeout */ - NVIC_SetVector(TICKER_TIMER_IRQ, (uint32_t)ticker_timer_irq_handler); - NVIC_EnableIRQ(TICKER_TIMER_IRQ); - - /* if define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json or other file, - hold the TICKER_TIMER counter for debug when core halted - */ -#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TICKER_TIMER_DEBUG_STOP) - TICKER_TIMER_DEBUG_STOP; -#endif - - timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); -} - -#endif /* 16-bit/32-bit timer init */ - -/** Initialize the ticker - * - * Initialize or re-initialize the ticker. This resets all the - * clocking and prescaler registers, along with disabling - * the compare interrupt. - * - * @note Initialization properties tested by ::ticker_init_test - */ -void us_ticker_init(void) -{ - /* TIMER is already initialized in ticker_timer_init() */ - /* disable the TIMER interrupt */ - timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); - /* configure TIMER channel enable state */ - timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); - - /* configure TIMER primary output function */ - timer_primary_output_config(TICKER_TIMER, ENABLE); - - timer_enable(TICKER_TIMER); - -} - -/** Read the current counter - * - * Read the current counter value without performing frequency conversions. - * If no rollover has occurred, the seconds passed since us_ticker_init() - * was called can be found by dividing the ticks returned by this function - * by the frequency returned by ::us_ticker_get_info. - * - * @return The current timer's counter value in ticks - */ -uint32_t us_ticker_read() -{ - /* read TIMER counter value */ - uint32_t count_value = 0U; - count_value = TIMER_CNT(TICKER_TIMER); - return (count_value); -} - -/** Set interrupt for specified timestamp - * - * @param timestamp The time in ticks to be set - * - * @note no special handling needs to be done for times in the past - * as the common timer code will detect this and call - * us_ticker_fire_interrupt() if this is the case - * - * @note calling this function with timestamp of more than the supported - * number of bits returned by ::us_ticker_get_info results in undefined - * behavior. - */ -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - /* configure TIMER channel output pulse value.Only set this value when you interrupt disabled */ - timer_channel_output_pulse_value_config(TICKER_TIMER, TIMER_CH_0, (uint32_t)timestamp); - /* clear TIMER interrupt flag,enable the TIMER interrupt */ - timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); - timer_interrupt_enable(TICKER_TIMER, TIMER_INT_CH0); -} - -/** Set pending interrupt that should be fired right away. - * - * The ticker should be initialized prior calling this function. - */ -void us_ticker_fire_interrupt(void) -{ - /* clear TIMER interrupt flag */ - timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); - /* channel 0 capture or compare event generation immediately,so CH0IF set for interrupt */ - timer_event_software_generate(TICKER_TIMER, TIMER_EVENT_SRC_CH0G); - /* enable the TIMER interrupt */ - timer_interrupt_enable(TICKER_TIMER, TIMER_INT_CH0); -} - -/** Disable us ticker interrupt - */ -void us_ticker_disable_interrupt(void) -{ - /* disable the TIMER interrupt */ - timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); -} - -/** Clear us ticker interrupt - * note: must be called with interrupts disabled function - */ -void us_ticker_clear_interrupt(void) -{ - /* clear TIMER interrupt flag */ - timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); -} - -/** save ticker TIMER data when MCU go to deepsleep -*/ -void ticker_timer_data_save(void) -{ - ticker_timer_cnt = TIMER_CNT(TICKER_TIMER); - ticker_timer_ch0cv = TIMER_CH0CV(TICKER_TIMER); - ticker_timer_dmainten = TIMER_DMAINTEN(TICKER_TIMER); -} - -/** restore ticker TIMER data when MCU go out deepsleep -*/ -void ticker_timer_data_restore(void) -{ - TIMER_CNT(TICKER_TIMER) = ticker_timer_cnt; - TIMER_CH0CV(TICKER_TIMER) = ticker_timer_ch0cv; - TIMER_DMAINTEN(TICKER_TIMER) = ticker_timer_dmainten; -} - -/** Deinitialize the us ticker - * - * Powerdown the us ticker in preparation for sleep, powerdown, or reset. - * - * After this function is called, no other ticker functions should be called - * except us_ticker_init(), calling any function other than init is undefined. - * - * @note This function stops the ticker from counting. - */ -void us_ticker_free(void) -{ - /* configure TIMER channel enable state */ - timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_DISABLE); - /* configure TIMER primary output function */ - timer_primary_output_config(TICKER_TIMER, DISABLE); - /* disable a TIMER */ - timer_disable(TICKER_TIMER); - - us_ticker_disable_interrupt(); -} - -/** get TIMER clock - * @param timer_dev: TIMER device information structrue - the structure is not necessary to be reconfigured after structrue initialization, - the structure parameters altering is automatically configured by core - * @return TIMER clock -*/ -static uint32_t timer_get_clock(uint32_t timer_periph) -{ - uint32_t timerclk; - - if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || - (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || (TIMER10 == timer_periph)) { - /* get the current APB2 TIMER clock source */ - if (RCU_APB2_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB2PSC)) { - timerclk = rcu_clock_freq_get(CK_APB2); - } else { - timerclk = rcu_clock_freq_get(CK_APB2) * 2; - } - } else { - /* get the current APB1 TIMER clock source */ - if (RCU_APB1_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB1PSC)) { - timerclk = rcu_clock_freq_get(CK_APB1); - } else { - timerclk = rcu_clock_freq_get(CK_APB1) * 2; - } - } - - return timerclk; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_VBLUNO51/PinNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_VBLUNO51/PinNames.h deleted file mode 100644 index f9d96300805..00000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_VBLUNO51/PinNames.h +++ /dev/null @@ -1,216 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* - * PinNames for VBLUno51 board - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - //only for mbed test suite - LED1 = p7, - LED2 = p9, - LED3 = p16, - LED4 = p17, - - BUTTON1 = p15, - BUTTON2 = p21, - BUTTON3 = p22, - BUTTON4 = p18, - - // mbed-os interface pins - TX_PIN_NUMBER = p10, - RX_PIN_NUMBER = p11, - RTS_PIN_NUMBER = p12, //not on Jump - CTS_PIN_NUMBER = p13, //not on Jump - - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPIS_PSELMOSI = p24, - SPIS_PSELMISO = p25, - SPIS_PSELSS = p23, - SPIS_PSELSCK = p28, - - SPIS_PSELMOSI1 = p24, - SPIS_PSELMISO1 = p25, - SPIS_PSELSS1 = p23, - SPIS_PSELSCK1 = p28, - - SPIS_PSELMOSI0 = p24, - SPIS_PSELMISO0 = p25, - SPIS_PSELSS0 = p23, - SPIS_PSELSCK0 = p28, - - I2C_SDA = p29, - I2C_SCL = p30, - I2C_SDA0 = p29, - I2C_SCL0 = p30, - I2C_SDA1 = p5, - I2C_SCL1 = p6, - - //Adruino interface pins - D0 = p11, - D1 = p10, - D2 = p20, - D3 = p19, - D4 = p18, - D5 = p17, - D6 = p16, - D7 = p9, - D8 = p21, - D9 = p22, - D10 = p23, - D11 = p24, - D12 = p25, - D13 = p28, - D14 = p1, - D15 = p2, - D16 = p3, - D17 = p4, - D18 = p5, - D19 = p6, - D20 = p29, - D21 = p30, - D22 = p7, - D23 = p15, - D24 = p12, - D25 = p13, - - SS = D10, - MOSI = D11, - MISO = D12, - SCK = D13, - - A0 = D14, - A1 = D15, - A2 = D16, - A3 = D17, - A4 = D18, - A5 = D19, - - SDA0 = D20, - SCL0 = D21, - SDA1 = D18, - SCL1 = D19, - SDA = SDA0, - SCL = SCL0, - - RX = D0, - TX = D1, - RTS = D24, //not on Jump - CTS = D25, //not on Jump - - LED = D22, //not on Jump - BUT = D23, //not on Jump - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_VBLUNO51/device.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_VBLUNO51/device.h deleted file mode 100644 index 2427e752ea9..00000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_VBLUNO51/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_VBLUNO51/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_VBLUNO51/PinNames.h deleted file mode 100644 index 92f2a8a9ffb..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_VBLUNO51/PinNames.h +++ /dev/null @@ -1,214 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* - * PinNames for VBLUno51 board - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - //only for mbed test suite - LED1 = p7, - LED2 = p9, - LED3 = p16, - LED4 = p17, - - BUTTON1 = p15, - BUTTON2 = p21, - BUTTON3 = p22, - BUTTON4 = p18, - - // mbed-os interface pins - TX_PIN_NUMBER = p10, - RX_PIN_NUMBER = p11, - RTS_PIN_NUMBER = p12, //not on Jump - CTS_PIN_NUMBER = p13, //not on Jump - - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPIS_PSELMOSI = p24, - SPIS_PSELMISO = p25, - SPIS_PSELSS = p23, - SPIS_PSELSCK = p28, - - SPIS_PSELMOSI1 = p24, - SPIS_PSELMISO1 = p25, - SPIS_PSELSS1 = p23, - SPIS_PSELSCK1 = p28, - - SPIS_PSELMOSI0 = p24, - SPIS_PSELMISO0 = p25, - SPIS_PSELSS0 = p23, - SPIS_PSELSCK0 = p28, - - I2C_SDA = p29, - I2C_SCL = p30, - I2C_SDA0 = p29, - I2C_SCL0 = p30, - I2C_SDA1 = p5, - I2C_SCL1 = p6, - - //Adruino interface pins - D0 = p11, - D1 = p10, - D2 = p20, - D3 = p19, - D4 = p18, - D5 = p17, - D6 = p16, - D7 = p9, - D8 = p21, - D9 = p22, - D10 = p23, - D11 = p24, - D12 = p25, - D13 = p28, - D14 = p1, - D15 = p2, - D16 = p3, - D17 = p4, - D18 = p5, - D19 = p6, - D20 = p29, - D21 = p30, - D22 = p7, - D23 = p15, - D24 = p12, - D25 = p13, - - SS = D10, - MOSI = D11, - MISO = D12, - SCK = D13, - - A0 = D14, - A1 = D15, - A2 = D16, - A3 = D17, - A4 = D18, - A5 = D19, - - SDA0 = D20, - SCL0 = D21, - SDA1 = D18, - SCL1 = D19, - SDA = SDA0, - SCL = SCL0, - - RX = D0, - TX = D1, - RTS = D24, //not on Jump - CTS = D25, //not on Jump - - LED = D22, //not on Jump - BUT = D23, //not on Jump - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_VBLUNO51/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_VBLUNO51/device.h deleted file mode 100644 index 2427e752ea9..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_VBLUNO51/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_VBLUNO52/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_VBLUNO52/PinNames.h deleted file mode 100644 index 55817dfa49d..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_VBLUNO52/PinNames.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2017 VNG IoT Lab, Vietnam - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* - * PinNames for the VBLUno52 board - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - p31 = 31, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - P0_31 = p31, - - //only for mbed test suite - LED1 = p12, - LED2 = p18, - LED3 = p19, - LED4 = p20, - - //only for mbed test suite - BUTTON1 = p17, - BUTTON2 = p3, - BUTTON3 = p4, - BUTTON4 = p28, - - RX_PIN_NUMBER = p8, - TX_PIN_NUMBER = p6, - CTS_PIN_NUMBER = p7, //not on Header - RTS_PIN_NUMBER = p5, //not on Header - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p13, - SPI_PSELMISO0 = p14, - SPI_PSELSS0 = p11, - SPI_PSELSCK0 = p15, - - SPI_PSELMOSI1 = p13, - SPI_PSELMISO1 = p14, - SPI_PSELSS1 = p11, - SPI_PSELSCK1 = p15, - - SPIS_PSELMOSI = p13, - SPIS_PSELMISO = p14, - SPIS_PSELSS = p11, - SPIS_PSELSCK = p15, - - I2C_SDA = p26, - I2C_SCL = p27, - - I2C_SDA0 = p26, - I2C_SCL0 = p27, - - I2C_SDA1 = p30, - I2C_SCL1 = p31, - - RESET = p21, - - NFC1 = p9, - NFC2 = p10, - - //Adruino interface pins - D0 = p8, - D1 = p6, - D2 = p24, - D3 = p23, - D4 = p22, - D5 = p18, - D6 = p19, - D7 = p20, - - D8 = p9, - D9 = p10, - D10 = p11, - D11 = p13, - D12 = p14, - D13 = p15, - - D14 = p3, - D15 = p4, - D16 = p28, - D17 = p29, - D18 = p30, - D19 = p31, - - D20 = p26, - D21 = p27, - - D22 = p12, - D23 = p17, - - D24 = p5, - D25 = p7, - - A0 = D14, - A1 = D15, - A2 = D16, - A3 = D17, - A4 = D18, - A5 = D19, - - SS = D10, - MOSI = D11, - MISO = D12, - SCK = D13, - - SDA0 = D20, - SCL0 = D21, - SDA1 = D18, - SCL1 = D19, - SDA = SDA0, - SCL = SCL0, - - RX = D0, - TX = D1, - RTS = D24, //not on Header - CTS = D25, //not on Header - - LED = D22, //not on Header - BUT = D23, //not on Header - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_VBLUNO52/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_VBLUNO52/device.h deleted file mode 100644 index 493844b8012..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_VBLUNO52/device.h +++ /dev/null @@ -1,23 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/PeripheralNames.h b/targets/TARGET_RDA/TARGET_UNO_91H/PeripheralNames.h deleted file mode 100644 index 5ea71a1f174..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/PeripheralNames.h +++ /dev/null @@ -1,87 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)RDA_UART0_BASE, - UART_1 = (int)RDA_UART1_BASE -} UARTName; - -typedef enum { - // Make sure GPIO_BASE & 0x1F == 0, store GPIO index at this field when mapping pins - GPIO_0 = (int)RDA_GPIO_BASE -} GPIOName; - -typedef enum { - I2C_0 = (int)RDA_I2C0_BASE -} I2CName; - -typedef enum { - SPI_0 = (int)RDA_SPI0_BASE -} SPIName; - -typedef enum { - I2S_0 = (int)RDA_I2S_BASE -} I2SName; - -typedef enum { - WDT_0 = (int)RDA_WDT_BASE -} WDTName; - -typedef enum { - PWM_0 = 0, - PWM_1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7 -} PWMName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2 -} ADCName; - -typedef enum { - GPADC0_0 = 0, - GPADC0_1 -} GPADCName; - -#define STDIO_UART_TX UART0_TX -#define STDIO_UART_RX UART0_RX -#define STDIO_UART UART_0 - -// Default peripherals -#define MBED_UART0 PA_0, PA_1 -#define MBED_UART1 PB_1, PB_2 -#define MBED_UARTUSB USBTX, USBRX - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/PinNames.h b/targets/TARGET_RDA/TARGET_UNO_91H/PinNames.h deleted file mode 100644 index c50fd4f5567..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/PinNames.h +++ /dev/null @@ -1,180 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 8 - -typedef enum { - PA_0 = (0 << PORT_SHIFT | 0 ), - PA_1 = (0 << PORT_SHIFT | 1 ), - PA_2 = (0 << PORT_SHIFT | 2 ), - PA_3 = (0 << PORT_SHIFT | 3 ), - PA_4 = (0 << PORT_SHIFT | 4 ), - PA_5 = (0 << PORT_SHIFT | 5 ), - PA_6 = (0 << PORT_SHIFT | 6 ), - PA_7 = (0 << PORT_SHIFT | 7 ), - PA_8 = (0 << PORT_SHIFT | 8 ), - PA_9 = (0 << PORT_SHIFT | 9 ), - PB_0 = (1 << PORT_SHIFT | 0 ), - PB_1 = (1 << PORT_SHIFT | 1 ), - PB_2 = (1 << PORT_SHIFT | 2 ), - PB_3 = (1 << PORT_SHIFT | 3 ), - PB_4 = (1 << PORT_SHIFT | 4 ), - PB_5 = (1 << PORT_SHIFT | 5 ), - PB_6 = (1 << PORT_SHIFT | 6 ), - PB_7 = (1 << PORT_SHIFT | 7 ), - PB_8 = (1 << PORT_SHIFT | 8 ), - PB_9 = (1 << PORT_SHIFT | 9 ), - PC_0 = (4 << PORT_SHIFT | 0 ), - PC_1 = (4 << PORT_SHIFT | 1 ), - PC_2 = (4 << PORT_SHIFT | 2 ), - PC_3 = (4 << PORT_SHIFT | 3 ), - PC_4 = (4 << PORT_SHIFT | 4 ), - PC_5 = (4 << PORT_SHIFT | 5 ), - PC_6 = (4 << PORT_SHIFT | 6 ), - PC_7 = (4 << PORT_SHIFT | 7 ), - PC_8 = (4 << PORT_SHIFT | 8 ), - PC_9 = (4 << PORT_SHIFT | 9 ), - PD_0 = (5 << PORT_SHIFT | 0 ), - PD_1 = (5 << PORT_SHIFT | 1 ), - PD_2 = (5 << PORT_SHIFT | 2 ), - PD_3 = (5 << PORT_SHIFT | 3 ), - PD_9 = (5 << PORT_SHIFT | 9 ), // Fake pin for GPADC_VBAT - - UART0_RX = PA_0, - UART0_TX = PA_1, - UART1_RX = PB_1, - UART1_TX = PB_2, - - USBRX = UART0_RX, - USBTX = UART0_TX, - - I2C_SCL = PC_0, - I2C_SDA = PC_1, - - I2S_TX_SD = PB_1, - I2S_TX_WS = PB_2, - I2S_TX_BCLK = PB_3, - I2S_RX_SD = PB_4, - I2S_RX_WS = PB_5, - I2S_RX_BCLK = PB_8, - - GPIO_PIN0 = PB_0, - GPIO_PIN1 = PB_1, - GPIO_PIN2 = PB_2, - GPIO_PIN3 = PB_3, - GPIO_PIN4 = PB_4, - GPIO_PIN5 = PB_5, - GPIO_PIN6 = PB_6, - GPIO_PIN7 = PB_7, - GPIO_PIN8 = PB_8, - GPIO_PIN9 = PB_9, - GPIO_PIN10 = PA_8, - GPIO_PIN11 = PA_9, - GPIO_PIN12 = PC_0, - GPIO_PIN13 = PC_1, - GPIO_PIN14 = PC_2, - GPIO_PIN15 = PC_3, - GPIO_PIN16 = PC_4, - GPIO_PIN17 = PC_5, - GPIO_PIN18 = PC_6, - GPIO_PIN19 = PC_7, - GPIO_PIN20 = PC_8, - GPIO_PIN21 = PC_9, - GPIO_PIN22 = PD_0, - GPIO_PIN23 = PD_1, - GPIO_PIN24 = PD_2, - GPIO_PIN25 = PD_3, - GPIO_PIN26 = PA_0, - GPIO_PIN27 = PA_1, - - // Another pin names for GPIO 14 - 19 - GPIO_PIN14A = PA_2, - GPIO_PIN15A = PA_3, - GPIO_PIN16A = PA_4, - GPIO_PIN17A = PA_5, - GPIO_PIN18A = PA_6, - GPIO_PIN19A = PA_7, - - ADC_PIN0 = PB_6, - ADC_PIN1 = PB_7, - ADC_PIN1A = PB_8, // Another pin name for ADC 1 - ADC_PIN2 = PD_9, - - LED1 = GPIO_PIN21, - LED2 = GPIO_PIN1, - - // Arduino Pin Names - // Analog Ports (A0-A1) - A0 = PB_6, - A1 = PB_8, - // A2 - // A3 - // Digital Pins with "An" name - A4 = PB_2, - A5 = PB_3, - // Digital Port (D0-D7) - D0 = PB_1, - D1 = PB_2, - D2 = PB_3, - D3 = PB_4, - D4 = PB_5, - D5 = PB_7, - D6 = PB_9, - D7 = PC_9, - // Digital Port (D8-D13) - D8 = PB_0, - // D9 - D10 = PD_1, // CS0 - D11 = PD_2, // MOSI - D12 = PD_3, // MISO - D13 = PD_0, // CLK - // GND - // AREF - SDA = PC_1, - D14 = SDA, - SCL = PC_0, - D15 = SCL, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - Repeater = 3, - PullDefault = Repeater, -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/PortNames.h b/targets/TARGET_RDA/TARGET_UNO_91H/PortNames.h deleted file mode 100644 index 94be6aa8b21..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/PortNames.h +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB = 1, - PortC = 4, - PortD = 5 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/analogin_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/analogin_api.c deleted file mode 100644 index 164017bd885..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/analogin_api.c +++ /dev/null @@ -1,98 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" -#include "pinmap.h" - -#include "rda_ccfg_api.h" - -#define ANALOGIN_MEDIAN_FILTER 1 -#define RDA_ADC_RANGE (0x03FFU) - -#if DEVICE_ANALOGIN -static const PinMap PinMap_ADC[] = { - {PB_6, ADC0_0, 0}, - {PB_7, ADC0_1, 0}, - {PB_8, ADC0_1, 0}, - {PD_9, ADC0_2, 0}, - {NC, NC, 0} -}; -static unsigned char adc1_gp = 0U; -static int adc_inited_cnt = 0; - -void analogin_init(analogin_t *obj, PinName pin) -{ - unsigned char gp = (unsigned char)(pin & 0x00FFU); - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - /* Init ADC */ - if (0 == adc_inited_cnt) { - rda_ccfg_adc_init(); - } - adc_inited_cnt++; - if (ADC0_2 == obj->adc) { - return; - } - if ((ADC0_1 == obj->adc) && (0U == adc1_gp)) { - adc1_gp = (2 >= rda_ccfg_hwver()) ? 7U : 8U; - MBED_ASSERT(gp == adc1_gp); - } - rda_ccfg_gp(gp, 0x00U); - rda_ccfg_adc_gp(gp, 0x00U); - rda_ccfg_adc_oenb(obj->adc, 0x01U); - - pinmap_pinout(pin, PinMap_ADC); -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = rda_ccfg_adc_read((unsigned char)(obj->adc)); - return (value); // 10 bit -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = rda_ccfg_adc_read((unsigned char)(obj->adc)); - return (float)value * (1.0f / (float)RDA_ADC_RANGE); -} - -void analogin_free(analogin_t *obj) -{ - unsigned char gp = 6U; - adc_inited_cnt--; - if (0 == adc_inited_cnt) { - rda_ccfg_adc_free(); - } - if (ADC0_2 == obj->adc) { - return; - } - if (ADC0_1 == obj->adc) { - if (0U == adc1_gp) { - return; - } - gp = adc1_gp; - } - rda_ccfg_adc_gp(gp, 0x01U); - rda_ccfg_gp(gp, 0x01U); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif /* DEVICE_ANALOGIN */ diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device.h b/targets/TARGET_RDA/TARGET_UNO_91H/device.h deleted file mode 100644 index 73a02c2e0ed..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5981_nvic_virtual.h b/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5981_nvic_virtual.h deleted file mode 100644 index ec23110ac52..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5981_nvic_virtual.h +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************//** - * @file RDA5981_nvic_virtual.h - * @brief - * @version - * @date - ******************************************************************************/ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __RDA5981_NVIC -#define __RDA5981_NVIC - -//#include "cmsis.h" -//#include -#include "rda_ccfg_api.h" - -extern void rda_wdt_softreset(void); -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __RDA5981_SystemReset(void) -{ - rda_ccfg_perrst(); - rda_ccfg_ckrst () ; - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_VECTRESET_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } - -} - - -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#define NVIC_SystemReset __RDA5981_SystemReset - - -#ifdef __cplusplus -} -#endif - -#endif - - diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5991H.h b/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5991H.h deleted file mode 100644 index 288faada834..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5991H.h +++ /dev/null @@ -1,517 +0,0 @@ -/* Copyright (c) 2019 Unisoc Communications Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __RDA5991H_H__ -#define __RDA5991H_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ - -/****** RDA5991H Specific Interrupt Numbers ******************************************************/ - SPIFLASH_IRQn = 0, /*!< SPI Flash Interrupt */ - PTA_IRQn = 1, /*!< PTA Interrupt */ - SDIO_IRQn = 2, /*!< SDIO Interrupt */ - USBDMA_IRQn = 3, /*!< USBDMA Interrupt */ - USB_IRQn = 4, /*!< USB Interrupt */ - GPIO_IRQn = 5, /*!< GPIO Interrupt */ - TIMER_IRQn = 6, /*!< Timer Interrupt */ - UART0_IRQn = 7, /*!< UART0 Interrupt */ - MACHW_IRQn = 8, /*!< MAC Hardware Interrupt */ - UART1_IRQn = 9, /*!< UART1 Interrupt */ - AHBDMA_IRQn = 10, /*!< AHBDMA Interrupt */ - PSRAM_IRQn = 11, /*!< PSRAM Interrupt */ - SDMMC_IRQn = 12, /*!< SDMMC Interrupt */ - EXIF_IRQn = 13, /*!< EXIF Interrupt */ - I2C_IRQn = 14 /*!< I2C Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_RDA5991H.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control Unit (SCU) ------------------------------------*/ -typedef struct -{ - __IO uint32_t CLKGATE0; /* 0x00 : Clock Gating 0 */ - __IO uint32_t PWRCTRL; /* 0x04 : Power Control */ - __IO uint32_t CLKGATE1; /* 0x08 : Clock Gating 1 */ - __IO uint32_t CLKGATE2; /* 0x0C : Clock Gating 2 */ - __IO uint32_t RESETCTRL; /* 0x10 : Power Control */ - __IO uint32_t CLKGATE3; /* 0x14 : Clock Gating 3 */ - __IO uint32_t CORECFG; /* 0x18 : Core Config */ - __IO uint32_t CPUCFG; /* 0x1C : CPU Config */ - __IO uint32_t FTMRINITVAL; /* 0x20 : Free Timer Initial Value */ - __IO uint32_t FTMRTS; /* 0x24 : Free Timer Timestamp */ - __IO uint32_t CLKGATEBP; /* 0x28 : Clock Gating Bypass */ - uint32_t RESERVED0[2]; - __IO uint32_t PWMCFG; /* 0x34 : PWM Config */ - __IO uint32_t FUN0WAKEVAL; /* 0x38 : SDIO Func0 Wake Val */ - __IO uint32_t FUN1WAKEVAL; /* 0x3C : SDIO Func1 Wake Val */ - __IO uint32_t BOOTJUMPADDR; /* 0x40 : Boot Jump Addr */ - __IO uint32_t SDIOINTVAL; /* 0x44 : SDIO Int Val */ - __IO uint32_t I2SCLKDIV; /* 0x48 : I2S Clock Divider */ - __IO uint32_t BOOTJUMPADDRCFG; /* 0x4C : Boot Jump Addr Config */ - __IO uint32_t FTMRPREVAL; /* 0x50 : Free Timer Prescale Init Val*/ - __IO uint32_t PWROPENCFG; /* 0x54 : Power Open Config */ - __IO uint32_t PWRCLOSECFG; /* 0x58 : Power Close Config */ - } RDA_SCU_TypeDef; - -/*------------- Timer0 (TIM0) ------------------------------------------------*/ -typedef struct -{ - __IO uint32_t LDCNT; /* 0x00 : Timer Load Count Register */ - __I uint32_t CVAL; /* 0x04 : Current Timer Value Register*/ - __IO uint32_t TCTRL; /* 0x08 : Timer Control Register */ - __I uint32_t INTCLR; /* 0x0C : Interrupt Clear Register */ -} RDA_TIM0_TypeDef; - -/*------------- Timer1 (TIM1) ------------------------------------------------*/ -typedef struct -{ - __IO uint32_t TCTRL; /* 0x00 : Timer Control Register */ - uint32_t RESERVED0[2]; - __IO uint32_t LDCNT; /* 0x0C : Timer Load Count Register */ - __I uint32_t CVAL; /* 0x10 : Current Timer Value Register*/ - uint32_t RESERVED1; - __I uint32_t INTCLR; /* 0x18 : Interrupt Clear Register */ -} RDA_TIM1_TypeDef; - -/*------------- Timer Interrupt Status (TIMINTST) ----------------------------*/ -typedef struct -{ - __I uint32_t INTST; /* 0x00 : Timer Int Stat Register */ -} RDA_TIMINTST_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - __IO uint32_t CTRL; /* 0x00 : GPIO Control */ - uint32_t RESERVED0; - __IO uint32_t DOUT; /* 0x08 : GPIO Data Output */ - __IO uint32_t DIN; /* 0x0C : GPIO Data Input */ - __IO uint32_t DIR; /* 0x10 : GPIO Direction */ - __IO uint32_t SLEW0; /* 0x14 : GPIO Slew Config 0 */ - __IO uint32_t SLEWIOMUX; /* 0x18 : GPIO IOMUX Slew Config */ - __IO uint32_t INTCTRL; /* 0x1C : GPIO Interrupt Control */ - __IO uint32_t IFCTRL; /* 0x20 : Interface Control */ - __IO uint32_t SLEW1; /* 0x24 : GPIO Slew Config 1 */ - __IO uint32_t REVID; /* 0x28 : ASIC Reversion ID */ - __IO uint32_t LPOSEL; /* 0x2C : LPO Select */ - uint32_t RESERVED1; - __IO uint32_t INTSEL; /* 0x34 : GPIO Interrupt Select */ - uint32_t RESERVED2; - __IO uint32_t SDIOCFG; /* 0x3C : SDIO Config */ - __IO uint32_t MEMCFG; /* 0x40 : Memory Config */ - __IO uint32_t IOMUXCTRL[8]; /* 0x44 - 0x60 : IOMUX Control */ - __IO uint32_t PCCTRL; /* 0x64 : Pulse Counter Control */ -} RDA_GPIO_TypeDef; - -/*------------- Inter-Integrated Circuit 0 (I2C0) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR0; /* 0x00 : Control Register 0 */ - __I uint32_t SR; /* 0x04 : Status Register */ - __IO uint32_t DR; /* 0x08 : TX/RX Data Register */ - __O uint32_t CMD; /* 0x0C : Command Register */ - __O uint32_t ICR; /* 0x10 : Interrupt Clear Register */ - __IO uint32_t CR1; /* 0x14 : Control Register 1 */ -} RDA_I2C0_TypeDef; - -/*------------- Pulse Width Modulator (PWM) ----------------------------------*/ -typedef struct -{ - __IO uint32_t PWTCFG; /* 0x00 : PWT Config Register */ - __IO uint32_t LPGCFG; /* 0x04 : LPG Config Register */ - __IO uint32_t PWL0CFG; /* 0x08 : PWL0 Config Register */ - __IO uint32_t PWL1CFG; /* 0x0C : PWL1 Config Register */ - __IO uint32_t CLKR; /* 0x10 : Clock Config Register */ -} RDA_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - union { - __I uint32_t RBR; /* 0x00 : UART Receive buffer register */ - __O uint32_t THR; /* 0x00 : UART Transmit holding register */ - __IO uint32_t DLL; /* 0x00 : UART Divisor latch(low) */ - }; - union { - __IO uint32_t DLH; /* 0x04 : UART Divisor latch(high) */ - __IO uint32_t IER; /* 0x04 : UART Interrupt enable register */ - }; - union { - __I uint32_t IIR; /* 0x08 : UART Interrupt id register */ - __O uint32_t FCR; /* 0x08 : UART Fifo control register */ - }; - __IO uint32_t LCR; /* 0x0C : UART Line control register */ - __IO uint32_t MCR; /* 0x10 : UART Moderm control register */ - __I uint32_t LSR; /* 0x14 : UART Line status register */ - __I uint32_t MSR; /* 0x18 : UART Moderm status register */ - __IO uint32_t SCR; /* 0x1C : UART Scratchpad register */ - __I uint32_t FSR; /* 0x20 : UART FIFO status register */ - __IO uint32_t FRR; /* 0x24 : UART FIFO tx/rx trigger resiger */ - __IO uint32_t DL2; /* 0x28 : UART Baud rate adjust register */ - __I uint32_t RESERVED0[4]; - __I uint32_t BAUD; /* 0x3C : UART Auto baud counter */ - __I uint32_t DL_SLOW; /* 0x40 : UART Divisor Adjust when slow clk */ - __I uint32_t DL_FAST; /* 0x44 : UART Divisor Adjust when fast clk */ -} RDA_UART_TypeDef; - -/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ -typedef struct -{ - __IO uint32_t CFG; - __IO uint32_t D0CMD; - __IO uint32_t D1CMD; -} RDA_SPI_TypeDef; - -/*------------- Integrated Interchip Sound (I2S) -----------------------------*/ -typedef struct -{ - __IO uint32_t CFG; - __IO uint32_t DOUTWR; - __I uint32_t DINRD; -} RDA_I2S_TypeDef; - -/*------------- External Interface (EXIF) ------------------------------------*/ -typedef struct -{ - RDA_SPI_TypeDef SPI0; /* 0x00 - 0x08 : SPI0 registers group */ - RDA_I2S_TypeDef I2S; /* 0x0C - 0x14 : I2S registers group */ - __IO uint32_t MISCSTCFG; /* 0x18 : Misc status config register */ - __IO uint32_t SPI1CTRL; /* 0x1C : SPI1 Control register */ - uint32_t RESERVED0[4]; - __IO uint32_t MISCINTCFG; /* 0x30 : Misc int config register */ - __IO uint32_t MBB2W; /* 0x34 : BT to WiFi mailbox register */ - __IO uint32_t MBW2B; /* 0x38 : WiFi to BT mailbox register */ - __IO uint32_t MISCCFG; /* 0x3C : Misc configure register */ - __IO uint32_t PWM0CFG; /* 0x40 : PWM0 configure register */ - __IO uint32_t PWM1CFG; /* 0x44 : PWM1 configure register */ - __IO uint32_t PWM2CFG; /* 0x48 : PWM2 configure register */ - __IO uint32_t PWM3CFG; /* 0x4C : PWM3 configure register */ -} RDA_EXIF_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t WDTCFG; -} RDA_WDT_TypeDef; - -/*------------- Pin Configure (PINCFG) ---------------------------------------*/ -typedef struct -{ - union { - __IO uint32_t IOMUXCTRL[8]; - struct { - __IO uint32_t MUX0; - __IO uint32_t MUX1; - __IO uint32_t MODE0; - __IO uint32_t MODE1; - __IO uint32_t MUX2; - __IO uint32_t MUX3; - __IO uint32_t MODE2; - __IO uint32_t MODE3; - }; - }; -} RDA_PINCFG_TypeDef; - -/*------------- AHB Direct Memory Access (DMA) -------------------------------*/ -typedef struct -{ - __IO uint32_t dma_ctrl; /* 0x00 : DMA ctrl */ - __IO uint32_t dma_src; /* 0x04 : DMA src */ - __IO uint32_t dma_dst; /* 0x08 : DMA dst */ - __IO uint32_t dma_len; /* 0x0c : DMA len */ - __IO uint32_t crc_gen; /* 0x10 : CRC gen */ - __IO uint32_t dma_func_ctrl; /* 0x14 : DMA func ctrl */ - __IO uint32_t aes_key0; /* 0x18 : AES key 0 */ - __IO uint32_t aes_key1; /* 0x1c : AES key 1 */ - __IO uint32_t aes_key2; /* 0x20 : AES key 2 */ - __IO uint32_t aes_key3; /* 0x24 : AES key 2 */ - __IO uint32_t aes_iv0; /* 0x28 : AES iv 0 */ - __IO uint32_t aes_iv1; /* 0x2c : AES iv 1 */ - __IO uint32_t aes_iv2; /* 0x30 : AES iv 2 */ - __IO uint32_t aes_iv3; /* 0x34 : AES iv 2 */ - __IO uint32_t aes_mode; /* 0x38 : AES mode */ - __IO uint32_t cios_ctrl; /* 0x3c : cios ctrl */ - __IO uint32_t cios_reg0; /* 0x40 : cios reg 0 */ - __IO uint32_t crc_init_val; /* 0x44 : CRC init val */ - __IO uint32_t crc_out_xorval; /* 0x48 : CRC out xorval */ - __I uint32_t crc_out_val; /* 0x4c : CRC out val */ - uint32_t RESERVED0[12]; - __IO uint32_t dma_int_out; /* 0x80 : DMA int out */ - __IO uint32_t dma_int_mask; /* 0x84 : DMA int mask */ - uint32_t RESERVED1[478]; - __IO uint32_t cios_data_base; /* 0x800 : CIOS data base */ -} RDA_DMACFG_TypeDef; - -/*------------- Random Number Generator (RNG) --------------------------------*/ -typedef struct -{ - __IO uint32_t TCTRL; /* 0x00 : TRNG ctrl */ - __IO uint32_t PCTRL; /* 0x04 : PRNG ctrl */ - __IO uint32_t PSEED; /* 0x08 : PRNG seed */ - __IO uint32_t PTMRINIT; /* 0x0C : PRNG timer init */ - __I uint32_t PTMR; /* 0x10 : PRNG timer */ - __I uint32_t TD0; /* 0x14 : TRNG data 0 */ - __I uint32_t TD0MSK; /* 0x18 : TRNG data 0 mask */ - __I uint32_t TD1; /* 0x1C : TRNG data 1 */ - __I uint32_t TD1MSK; /* 0x20 : TRNG data 1 mask */ - __I uint32_t PD; /* 0x24 : PRNG data */ - __I uint32_t THC; /* 0x28 : TRNG h/c value */ -} RDA_RNG_TypeDef; - -/*------------- Universal Serial Bus (USB) -------------------------------------------*/ -typedef struct -{ - struct { - __IO uint8_t FUNC_ADDR; /* 0x00: Function Address */ - __IO uint8_t POWER; /* 0x01: Power */ - __IO uint16_t INTRTX; /* 0x02-0x03: IntrTx */ - }; - struct { - __IO uint16_t INTRRX; /* 0x04-0x05: IntrRx */ - __IO uint16_t INTRTXEN; /* 0x06-0x07: IntrTx Enable */ - }; - struct { - __IO uint16_t INTRRXEN; /* 0x08-0x09: IntrRx Enable */ - __IO uint8_t INTR; /* 0x0a: Interrupt */ - __IO uint8_t INTREN; /* 0x0b: Intr Enable */ - }; - struct { - __IO uint16_t FRAMENUM; /* 0x0c-0x0d: Frame Number */ - __IO uint8_t EPIDX; /* 0x0e: Endpoint Index */ - __IO uint8_t TESTMODE; /* 0x0f: Test Mode */ - }; - struct { - __IO uint16_t TXMAXPKTSIZE; /* 0x10-0x11: Tx Max Packet Size */ - union { - __IO uint16_t CSR0; /* 0x12-0x13: CSR0 */ - __IO uint16_t TXCSR; /* 0x12-0x13: CSR0 */ - }; - }; - struct { - __IO uint16_t RXMAXPKTSIZE; /* 0x14-0x15: Rx Max Packet Size */ - __IO uint16_t RXCSR; /* 0x16-0x17: Rx CSR */ - }; - struct { - union { - __IO uint16_t RXCOUNT0; /* 0x18-0x19: Rx Counter of EP0 */ - __IO uint16_t RXCOUNT; /* 0x18-0x19: Rx Counter of Rx EP */ - }; -#if 0 - uint16_t RESERVED0; /* 0x1a-0x1b: reserved */ -#else - /* host mode only */ - __IO uint8_t TXTYPE; /* 0x1a: TxType */ - __IO uint8_t TXINTERVAL; /* 0x1B: TxInterval */ - -#endif - }; - struct { - __IO uint8_t RXTYPE; /* 0x1c: rxtype */ - __IO uint8_t RXINTERVAL; /* 0x1d: rxInterval */ - uint8_t RESERVED1[1]; /* 0x1e: reserved */ - union { - __IO uint8_t CONFIGDATA; /* 0x1f: Data of Core Configuration */ - __IO uint8_t FIFOSIZE; /* 0x1f: Size of Selected TX/RX Fifo */ - }; - }; - __IO uint32_t FIFOs[16]; /* 0x20-0x5F: fifos for Endpoint */ - struct { - __IO uint8_t DEVCTL; /* 0x60: OTG device control */ - uint8_t RESERVED2; /* 0x61: unused */ - __IO uint8_t TXFIFOSZ; /* 0x62: Tx Endpoint FIFO Size */ - __IO uint8_t RXFIFOSZ; /* 0x63: Rx Endpoint FIFO Size */ - }; - struct { - __IO uint16_t TXFIFOADDR; /* 0x64-0x65: Tx Endpoint FIFO Address */ - __IO uint16_t RXFIFOADDR; /* 0x66-0x67: Rx Endpoint FIFO Address */ - }; - union { - __IO uint32_t VCONTROL; /* 0x68-0x6b: UTMI+PHY Vendor Register */ - __IO uint32_t VSTATUS; /* 0x68-0x6b: UTMI+PHY Vendor Register */ - }; - struct { - __IO uint16_t HWVERSION; /* 0x6c-0x6d: Hardware Version Number Register */ - uint16_t RESERVED3; /* 0x6e-0x6f: Unused */ - }; - __IO uint8_t ULPIREG[8]; /* 0x70-0x77: ulpi register, not used */ - struct { - __IO uint8_t EPINFO; /* 0x78: numbers of tx/rx ep */ - __IO uint8_t RAMINFO; /* 0x79: width of RAM and number of DMA channels */ - __IO uint8_t LINKINFO; /* 0x7a: delays to be applied */ - __IO uint8_t VPLEN; /* 0x7b: Duration of the VBus pulsing charge */ - }; - struct { - __IO uint8_t HSEOF; /* 0x7c: Timer buffer available on HS transaction */ - __IO uint8_t FSEOF; /* 0x7d: Timer buffer available on HS transaction */ - __IO uint8_t LSEOF; /* 0x7e: Timer buffer available on HS transaction */ - uint8_t RESERVED4; /* 0x7f: unused */ - }; - uint32_t RESERVED5[3]; /* 0x80-0x8b: unused */ - __IO uint32_t FIFO_CTRL; /* 0x8c: FIFO Control */ - __IO uint32_t ANAREG2; /* 0x90-0x93 */ - uint32_t RESERVED6[91]; /* 0x94-0x1ff: unused */ - struct { - __IO uint8_t DMAINTR; /* 0x200: DMA Interrrupt */ - __IO uint8_t RESERVED7[3]; /* 0x201-0x203: unused; */ - }; - __IO uint32_t DMACTRL0; /* 0x204: channel 0 */ - __IO uint32_t DMAADDR0; /* 0x208: AHB Memory Address channel 0 */ - __IO uint32_t COUNT0; /* 0x20c: DMA Counter for channel 0 */ - - uint32_t RESERVED8; /* 0x210-0x213: unused */ - __IO uint32_t DMACTRL1; /* 0x214: channel 1 */ - __IO uint32_t DMAADDR1; /* 0x218: AHB Memory Address channel 1 */ - __IO uint32_t COUNT1; /* 0x21c: DMA Counter for channel 1 */ - uint8_t RESERVED9[224]; /* 0x220 - 0x2FF: unused */ - __IO uint32_t PKCNT0; /* 0X300: packet count epnum 0 */ - __IO uint32_t PKCNT1; /* 0X304: packet count epnum 1 */ - __IO uint32_t PKCNT2; /* 0X308:packet count epnum 1 */ -}RDA_USB_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -//#define RDA_ICACHE_DISABLE -#define RDA_PARTITION_INDEX 0 - -/* Base addresses */ -#define RDA_ROM_BASE (0x00000000UL) -#define RDA_IRAM_BASE (0x00100000UL) -#define RDA_DRAM_BASE (0x00180000UL) -#define RDA_PSRAM_BASE (0x10000000UL) -#define RDA_FLASH_BASE (0x14000000UL) -#define RDA_ICACHE_BASE (0x18000000UL) -#if (0 == RDA_PARTITION_INDEX) -#define RDA_PADDR_OFST (0x00001000UL) -#elif (1 == RDA_PARTITION_INDEX) -#define RDA_PADDR_OFST (0x0007E000UL) -#else -#error "Not supported" -#endif -#if defined(RDA_ICACHE_DISABLE) -#define RDA_CODE_BASE (RDA_FLASH_BASE + RDA_PADDR_OFST) -#else /* RDA_ICACHE_DISABLE */ -#define RDA_CODE_BASE (RDA_ICACHE_BASE + RDA_PADDR_OFST) -#endif /* RDA_ICACHE_DISABLE */ -#define RDA_PER_BASE (0x40000000UL) -#define RDA_AHB0_BASE (0x40000000UL) -#define RDA_APB_BASE (RDA_AHB0_BASE) -#define RDA_AHB1_BASE (0x40100000UL) -#define RDA_PERBTBND_BASE (0x42000000UL) -#define RDA_CM4_BASE (0xE0000000UL) - -/* APB peripherals */ -#define RDA_SCU_BASE (RDA_APB_BASE + 0x00000) -#define RDA_GPIO_BASE (RDA_APB_BASE + 0x01000) -#define RDA_TIM0_BASE (RDA_APB_BASE + 0x02000) -#define RDA_TIM1_BASE (RDA_APB_BASE + 0x02008) -#define RDA_TIMINTST_BASE (RDA_APB_BASE + 0x02010) -#define RDA_I2C0_BASE (RDA_APB_BASE + 0x03000) - -/* AHB0 peripherals */ -#define RDA_PWM_BASE (RDA_AHB0_BASE + 0x04000) -#define RDA_PSRAMCFG_BASE (RDA_AHB0_BASE + 0x05000) -#define RDA_SDMMC_BASE (RDA_AHB0_BASE + 0x06000) -#define RDA_I2C_BASE (RDA_AHB0_BASE + 0x10000) -#define RDA_TRAP_BASE (RDA_AHB0_BASE + 0x11000) -#define RDA_UART0_BASE (RDA_AHB0_BASE + 0x12000) -#define RDA_EXIF_BASE (RDA_AHB0_BASE + 0x13000) -#define RDA_PA_BASE (RDA_AHB0_BASE + 0x20000) -#define RDA_CE_BASE (RDA_AHB0_BASE + 0x22000) -#define RDA_MON_BASE (RDA_AHB0_BASE + 0x24000) -#define RDA_SDIO_BASE (RDA_AHB0_BASE + 0x30000) -#define RDA_USB_BASE (RDA_AHB0_BASE + 0x31000) - -/* AHB1 peripherals */ -#define RDA_MEMC_BASE (RDA_AHB1_BASE + 0x00000) -#define RDA_UART1_BASE (RDA_AHB1_BASE + 0x80000) -#define RDA_DMACFG_BASE (RDA_AHB1_BASE + 0x81000) -#define RDA_RNG_BASE (RDA_AHB1_BASE + 0x81100) - -/* EXIF peripherals */ -#define RDA_SPI0_BASE (RDA_EXIF_BASE + 0x00000) -#define RDA_I2S_BASE (RDA_EXIF_BASE + 0x0000C) - -/* MISC peripherals */ -#define RDA_WDT_BASE (RDA_SCU_BASE + 0x0000C) -#define RDA_PINCFG_BASE (RDA_GPIO_BASE + 0x00044) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define RDA_SCU ((RDA_SCU_TypeDef *) RDA_SCU_BASE ) -#define RDA_GPIO ((RDA_GPIO_TypeDef *) RDA_GPIO_BASE ) -#define RDA_TIM0 ((RDA_TIM0_TypeDef *) RDA_TIM0_BASE ) -#define RDA_TIM1 ((RDA_TIM1_TypeDef *) RDA_TIM1_BASE ) -#define RDA_TIMINTST ((RDA_TIMINTST_TypeDef *) RDA_TIMINTST_BASE ) -#define RDA_I2C0 ((RDA_I2C0_TypeDef *) RDA_I2C0_BASE ) -#define RDA_PWM ((RDA_PWM_TypeDef *) RDA_PWM_BASE ) -#define RDA_UART0 ((RDA_UART_TypeDef *) RDA_UART0_BASE ) -#define RDA_UART1 ((RDA_UART_TypeDef *) RDA_UART1_BASE ) -#define RDA_SPI0 ((RDA_SPI_TypeDef *) RDA_SPI0_BASE ) -#define RDA_I2S ((RDA_I2S_TypeDef *) RDA_I2S_BASE ) -#define RDA_EXIF ((RDA_EXIF_TypeDef *) RDA_EXIF_BASE ) -#define RDA_WDT ((RDA_WDT_TypeDef *) RDA_WDT_BASE ) -#define RDA_PINCFG ((RDA_PINCFG_TypeDef *) RDA_PINCFG_BASE ) -#define RDA_DMACFG ((RDA_DMACFG_TypeDef *) RDA_DMACFG_BASE ) -#define RDA_RNG ((RDA_RNG_TypeDef *) RDA_RNG_BASE ) -#define RDA_USB ((RDA_USB_TypeDef *) RDA_USB_BASE ) - -#endif /* __RDA5991H_H__ */ diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/TARGET_UNO_91H/RDA5981C.sct b/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/TARGET_UNO_91H/RDA5981C.sct deleted file mode 100644 index a2da33a8dc7..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/TARGET_UNO_91H/RDA5981C.sct +++ /dev/null @@ -1,73 +0,0 @@ -#! armcc -E - -//#define RDA_ICACHE_DISABLE -#define RDA_PARTITION_INDEX 0 - -#define RDA_ROM_BASE (0x00000000) -#define RDA_IRAM_BASE (0x00100000) -#define RDA_IRAM_SIZE (0x00020000) -#define RDA_DRAM_BASE (0x00180000) -#define RDA_DRAM_SIZE (0x00028000) -#define RDA_PSRAM_BASE (0x10000000) -#define RDA_FLASH_BASE (0x14000000) -#define RDA_ICACHE_BASE (0x18000000) -#if (0 == RDA_PARTITION_INDEX) -#define RDA_PADDR_OFST (0x00001000) -#elif (1 == RDA_PARTITION_INDEX) -#define RDA_PADDR_OFST (0x001F5000) -#else -#error "Not supported" -#endif -#if defined(RDA_ICACHE_DISABLE) -#define RDA_CODE_BASE (RDA_FLASH_BASE + RDA_PADDR_OFST) -#else /* RDA_ICACHE_DISABLE */ - -#if !defined(MBED_APP_START) /* MBED_APP_START */ -#define RDA_CODE_BASE (RDA_ICACHE_BASE + RDA_PADDR_OFST) -#else /* MBED_APP_START */ -#define RDA_CODE_BASE (MBED_APP_START) -#endif /* MBED_APP_START */ - -#endif /* RDA_ICACHE_DISABLE */ - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (0x1F4000) -#endif -#define RDA_CODE_SIZE (MBED_APP_SIZE) -#define RDA_AHB1_BASE (0x40100000) -#define RDA_MEMC_BASE (RDA_AHB1_BASE + 0x00000) - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; max code size: RDA_CODE_SIZE -LR_IROM1 RDA_CODE_BASE RDA_CODE_SIZE { ; load region size_region - ER_IROM0 RDA_CODE_BASE RDA_CODE_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(31 vect * 4 bytes) = 8_byte_aligned(0x7C) = 0x80 - ER_IRAMVEC RDA_IRAM_BASE EMPTY 0x80 { ; Reserved for vectors - } - ; IRAM Size: Total(128KB) - Vector(128B) - Stack(1KB) - RW_IRAM1 AlignExpr(+0, 8) (0x20000 - 0x80 - Stack_Size) { - .ANY (+RW +ZI) - } - ARM_LIB_STACK AlignExpr(+0, 8) EMPTY Stack_Size { - } - ARM_LIB_HEAP RDA_DRAM_BASE EMPTY RDA_DRAM_SIZE { - } - RW_IRAM2 RDA_MEMC_BASE 0x18C00 { ; RW data, MACLIB_RAM - .ANY (SECTIONRESERVED1) - } - RW_IRAM3 (RDA_MEMC_BASE + 0x18C00) 0x0C00 { ; RW data, AES_RAM - .ANY (AHB1SMEM0) - } - RW_IRAM4 (RDA_MEMC_BASE + 0x19800) 0x6800 { ; RW data, WLAN RAM - .ANY (AHB1SMEM1) - } -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/startup_RDA5991H.S b/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/startup_RDA5991H.S deleted file mode 100644 index ff07a929600..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/startup_RDA5991H.S +++ /dev/null @@ -1,180 +0,0 @@ -;/***************************************************************************** -; * @file: startup_RDA5991H.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the RDA RDA5991H Device Series -; * @version: V1.02, modified for mbed -; * @date: 07. June 2018 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2009 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| [WEAK] - EXPORT __Vectors - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD SPIFLASH_IRQHandler ; 16: SPI Flash - DCD PTA_IRQHandler ; 17: PTA - DCD SDIO_IRQHandler ; 18: SDIO - DCD USBDMA_IRQHandler ; 19: USB DMA - DCD USB_IRQHandler ; 20: USB - DCD GPIO_IRQHandler ; 21: GPIO - DCD TIMER0_IRQHandler ; 22: Timer0 - DCD UART0_IRQHandler ; 23: UART0 - DCD MACHW_IRQHandler ; 24: MAC Hardware - DCD UART1_IRQHandler ; 25: UART1 - DCD AHBDMA_IRQHandler ; 26: AHB DMA - DCD PSRAM_IRQHandler ; 27: PSRAM - DCD SDMMC_IRQHandler ; 28: SDMMC - DCD EXIF_IRQHandler ; 29: EXIF - DCD I2C_IRQHandler ; 30: I2C - - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT rda_ccfg_boot - IMPORT SystemInit - IMPORT __main - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MSR MSP, R0 - LDR R0, =rda_ccfg_boot - BLX R0 - CMP R0, #0x01 - BNE Soft_Reset - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Soft Reset - -Soft_Reset PROC - MOV R1, #0x04 - LDR R0, [R1] - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT SPIFLASH_IRQHandler [WEAK] - EXPORT PTA_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT USBDMA_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT GPIO_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT MACHW_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT AHBDMA_IRQHandler [WEAK] - EXPORT PSRAM_IRQHandler [WEAK] - EXPORT SDMMC_IRQHandler [WEAK] - EXPORT EXIF_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - -SPIFLASH_IRQHandler -PTA_IRQHandler -SDIO_IRQHandler -USBDMA_IRQHandler -USB_IRQHandler -GPIO_IRQHandler -TIMER0_IRQHandler -UART0_IRQHandler -MACHW_IRQHandler -UART1_IRQHandler -AHBDMA_IRQHandler -PSRAM_IRQHandler -SDMMC_IRQHandler -EXIF_IRQHandler -I2C_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/TARGET_UNO_91H/RDA5981C.ld b/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/TARGET_UNO_91H/RDA5981C.ld deleted file mode 100644 index 78aacad6b73..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/TARGET_UNO_91H/RDA5981C.ld +++ /dev/null @@ -1,207 +0,0 @@ -/* Linker script for mbed RDA5981C */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x18001000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 2000K -#endif - -/* Linker script to configure memory regions. */ -MEMORY -{ - /* If ICache is enable, use virtual flash base address */ - /* Use partition index: 0 */ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - /* Use partition index: 1 */ - /* FLASH (rx) : ORIGIN = 0x181F5000, LENGTH = 2000K */ - - /* If ICache is disable, use real flash base address. Depends on macro: RDA_ICACHE_DISABLE */ - /* Use partition index: 0 */ - /* FLASH (rx) : ORIGIN = 0x14001000, LENGTH = 2000K */ - /* Use partition index: 1 */ - /* FLASH (rx) : ORIGIN = 0x141F5000, LENGTH = 2000K */ - - IRAM (rwx) : ORIGIN = 0x00100080, LENGTH = (128K - 0x80) - DRAM (rwx) : ORIGIN = 0x00180000, LENGTH = 160K - MACLIB_RAM(rwx) : ORIGIN = 0x40100000, LENGTH = 99K - AES_RAM(rwx) : ORIGIN = 0x40118C00, LENGTH = 1K - WLAN_RAM(rwx) : ORIGIN = 0x40119000, LENGTH = 28K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - Image$$RW_IRAM1$$Base = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > IRAM - - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$RW_IRAM1$$ZI$$Limit = . ; - } > IRAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > IRAM - - /* Set stack top to end of IRAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(IRAM) + LENGTH(IRAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __bss_end__, "region IRAM overflowed with stack") - - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(DRAM) + LENGTH(DRAM); - __HeapLimit = .; - } > DRAM - PROVIDE(__sbrk_start = ADDR(.heap)); - PROVIDE(__krbs_start = ADDR(.heap) + SIZEOF(.heap)); - - /* Code can explicitly ask for data to be - placed in these higher RAM banks where - they will be left uninitialized. - */ - .SECTIONRESERVED1 (NOLOAD): - { - Image$$RW_IRAM2$$Base = . ; - *(SECTIONRESERVED1) - Image$$RW_IRAM2$$ZI$$Limit = .; - } > MACLIB_RAM - - .AHB1SMEM0 (NOLOAD): - { - Image$$RW_IRAM3$$Base = . ; - *(AHB1SMEM0) - Image$$RW_IRAM3$$ZI$$Limit = .; - } > AES_RAM - - .AHB1SMEM1 (NOLOAD): - { - Image$$RW_IRAM4$$Base = . ; - *(AHB1SMEM1) - Image$$RW_IRAM4$$ZI$$Limit = .; - } > WLAN_RAM -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/TARGET_UNO_91H/startup_RDA5981C.S b/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/TARGET_UNO_91H/startup_RDA5981C.S deleted file mode 100644 index abcba002929..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/TARGET_UNO_91H/startup_RDA5981C.S +++ /dev/null @@ -1,196 +0,0 @@ -/* File: startup_ARMCM4.s - * Purpose: startup file for Cortex-M3/M4 devices. Should use with - * GNU Tools for ARM Embedded Processors - * Version: V1.1 - * Date: 17 June 2018 - * - * Copyright (C) 2011 ARM Limited. All rights reserved. - * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - */ - .syntax unified - .arch armv7-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x800 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x28000 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long SPIFLASH_IRQHandler /* 16: SPI Flash */ - .long PTA_IRQHandler /* 17: PTA */ - .long SDIO_IRQHandler /* 18: SDIO */ - .long USBDMA_IRQHandler /* 19: USB DMA */ - .long USB_IRQHandler /* 20: USB */ - .long GPIO_IRQHandler /* 21: GPIO */ - .long TIMER0_IRQHandler /* 22: Timer0 */ - .long UART0_IRQHandler /* 23: UART0 */ - .long MACHW_IRQHandler /* 24: MAC Hardware */ - .long UART1_IRQHandler /* 25: UART1 */ - .long AHBDMA_IRQHandler /* 26: AHB DMA */ - .long PSRAM_IRQHandler /* 27: PSRAM */ - .long SDMMC_IRQHandler /* 28: SDMMC */ - .long EXIF_IRQHandler /* 29: EXIF */ - .long I2C_IRQHandler /* 30: I2C */ - - - .size __isr_vector, . - __isr_vector - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * _etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r0, =__StackTop - msr msp, r0 - - ldr r0, =rda_ccfg_boot - blx r0 - cmp r0, #0x01 - bne Soft_Reset - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.Lflash_to_ram_loop: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .Lflash_to_ram_loop - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - -Soft_Reset: - mov r1, #0x04 - ldr r0, [r1] - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler SPIFLASH_IRQHandler - def_irq_default_handler PTA_IRQHandler - def_irq_default_handler SDIO_IRQHandler - def_irq_default_handler USBDMA_IRQHandler - def_irq_default_handler USB_IRQHandler - def_irq_default_handler GPIO_IRQHandler - def_irq_default_handler TIMER0_IRQHandler - def_irq_default_handler UART0_IRQHandler - def_irq_default_handler MACHW_IRQHandler - def_irq_default_handler UART1_IRQHandler - def_irq_default_handler AHBDMA_IRQHandler - def_irq_default_handler PSRAM_IRQHandler - def_irq_default_handler SDMMC_IRQHandler - def_irq_default_handler EXIF_IRQHandler - def_irq_default_handler I2C_IRQHandler - - .end diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_IAR/TARGET_UNO_91H/RDA5981C.icf b/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_IAR/TARGET_UNO_91H/RDA5981C.icf deleted file mode 100644 index 7ed2d7b4e51..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_IAR/TARGET_UNO_91H/RDA5981C.icf +++ /dev/null @@ -1,73 +0,0 @@ -/* Linker file for the IAR Compiler for ARM */ -/* Specials */ -define symbol RDA_ICACHE_DISABLE = 0; -define symbol RDA_PARTITION_INDEX = 0; -/* Memory Regions */ -define symbol RDA_IRAM_BASE = 0x00100000; -define symbol RDA_IRAM_END = 0x0011FFFF; -define symbol RDA_DRAM_BASE = 0x00180000; -define symbol RDA_DRAM_END = 0x001A7FFF; -define symbol RDA_FLASH_BASE = 0x14000000; -define symbol RDA_ICACHE_BASE = 0x18000000; -if (0 == RDA_PARTITION_INDEX) { - define symbol RDA_PADDR_OFST = 0x00001000; -} else { - define symbol RDA_PADDR_OFST = 0x001F5000; -} -if (1 == RDA_ICACHE_DISABLE) { - define symbol RDA_CODE_BASE = RDA_FLASH_BASE + RDA_PADDR_OFST; -} else { - /* MBED_APP_START */ - if (!isdefinedsymbol(MBED_APP_START)) { - define symbol RDA_CODE_BASE = RDA_ICACHE_BASE + RDA_PADDR_OFST; - } else { - define symbol RDA_CODE_BASE = MBED_APP_START; - } -} -define symbol RDA_CODE_END = RDA_CODE_BASE + 0x1F3FFF; -define symbol RDA_AHB1_BASE = 0x40100000; -define symbol RDA_MEMC_BASE = RDA_AHB1_BASE + 0x00000; -define symbol RDA_MEMC_END = RDA_AHB1_BASE + 0x1FFFF; - -define symbol INTVEC_BASE = RDA_CODE_BASE; -define symbol INTVEC_RAM_BASE = RDA_IRAM_BASE; -define symbol I_DATA_BASE = RDA_IRAM_BASE + 0x80; -define symbol I_DATA_END = RDA_IRAM_END; -define symbol D_DATA_BASE = RDA_DRAM_BASE; -define symbol D_DATA_END = RDA_DRAM_END; -define symbol AES_BASE = RDA_MEMC_BASE + 0x18C00; -define symbol AES_END = RDA_MEMC_BASE + 0x197FF; -define symbol WLAN_BASE = RDA_MEMC_BASE + 0x19800; -define symbol WLAN_END = RDA_MEMC_END; - -/* Stack Size & Heap Size*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define symbol CSTACK_SIZE = MBED_BOOT_STACK_SIZE; -define symbol HEAP_SIZE = RDA_DRAM_END - RDA_DRAM_BASE + 1; - -/*Memory regions*/ -define memory mem with size = 4G; -define region ROM_REGION = mem:[from RDA_CODE_BASE to RDA_CODE_END]; -define region IRAM_REGION = mem:[from I_DATA_BASE to I_DATA_END]; -define region DRAM_REGION = mem:[from D_DATA_BASE to D_DATA_END]; -define region AES_REGION = mem:[from AES_BASE to AES_END]; -define region WLAN_REGION = mem:[from WLAN_BASE to WLAN_END]; - -define block CSTACK with alignment = 8, size = CSTACK_SIZE { }; -define block HEAP with alignment = 8, size = HEAP_SIZE { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:INTVEC_BASE { readonly section .intvec }; - -place in ROM_REGION { readonly }; -place in IRAM_REGION { block RW, block ZI, block CSTACK}; -place in DRAM_REGION { block HEAP}; -place in AES_REGION { section AHB1SMEM0 }; -place in WLAN_REGION { section AHB1SMEM1 }; diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_IAR/startup_RDA5991H.S b/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_IAR/startup_RDA5991H.S deleted file mode 100644 index 9711005aebb..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_IAR/startup_RDA5991H.S +++ /dev/null @@ -1,221 +0,0 @@ -;/***************************************************************************** -; * @file: startup_RDA5991H.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the RDA5981x Device Series -; * @version: V1.00 -; * @date: 09. June 2018 -; *---------------------------------------------------------------------------- -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * -; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN rda_ccfg_boot - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD SPIFLASH_IRQHandler - DCD PTA_IRQHandler - DCD SDIO_IRQHandler - DCD USBDMA_IRQHandler - DCD USB_IRQHandler - DCD GPIO_IRQHandler - DCD TIMER0_IRQHandler - DCD UART0_IRQHandler - DCD MACHW_IRQHandler - DCD UART1_IRQHandler - DCD AHBDMA_IRQHandler - DCD PSRAM_IRQHandler - DCD SDMMC_IRQHandler - DCD EXIF_IRQHandler - DCD I2C_IRQHandler -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =sfe(CSTACK) - MSR MSP, R0 - LDR R0, =rda_ccfg_boot - BLX R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SPIFLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPIFLASH_IRQHandler - B SPIFLASH_IRQHandler - - PUBWEAK PTA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PTA_IRQHandler - B PTA_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK USBDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBDMA_IRQHandler - B USBDMA_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK GPIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GPIO_IRQHandler - B GPIO_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK MACHW_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MACHW_IRQHandler - B MACHW_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK AHBDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -AHBDMA_IRQHandler - B AHBDMA_IRQHandler - - PUBWEAK PSRAM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PSRAM_IRQHandler - B PSRAM_IRQHandler - - PUBWEAK SDMMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC_IRQHandler - B SDMMC_IRQHandler - - PUBWEAK EXIF_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXIF_IRQHandler - B EXIF_IRQHandler - - PUBWEAK I2C_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C_IRQHandler - B I2C_IRQHandler - - END diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/cmsis.h b/targets/TARGET_RDA/TARGET_UNO_91H/device/cmsis.h deleted file mode 100644 index c7d420b2de7..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2018 ARM Limited. All rights reserved. - * - * A generic CMSIS include header - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "RDA5991H.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/cmsis_nvic.h b/targets/TARGET_RDA/TARGET_UNO_91H/device/cmsis_nvic.h deleted file mode 100644 index c7138c4071b..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/cmsis_nvic.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2018 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#define NVIC_NUM_VECTORS (16 + 15) -#define NVIC_RAM_VECTOR_ADDRESS (RDA_IRAM_BASE) - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/system_RDA5991H.c b/targets/TARGET_RDA/TARGET_UNO_91H/device/system_RDA5991H.c deleted file mode 100644 index 5e524e249f3..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/system_RDA5991H.c +++ /dev/null @@ -1,191 +0,0 @@ -/**************************************************************************//** - * @file system_RDA5991H.c - * @brief CMSIS Cortex-M4 Device System Source File for - * RDA RDA5991H Device Series - * @version V1.11 - * @date 12. June 2018 - * - * @note - * Copyright (C) 2009-2016 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "RDA5991H.h" - - -/** @addtogroup RDA5991H_System - * @{ - */ - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// Clock Gating Control 0 Register (CLKGATE0) -// DEEPSLEEP: Deep sleep mode enable -// EXIF: EXIF clock gating enable -// -// -// Clock Gating Control 1 Register (CLKGATE1) -// GPIO: GPIO clock gating enable -// I2S: I2S clock gating enable -// PWM: PWM clock gating enable -// TIMER: APB Timer clock gating enable -// PSRAM_PCLK: PSRAM PCLK clock gating enable -// SDMMC: SDMMC clock gating enable -// I2C: I2C clock gating enable -// PSRAM_HCLK: PSRAM HCLK clock gating enable -// -// -// Clock Gating Control 2 Register (CLKGATE2) -// I2SIN: I2SIN clock gating enable -// I2SOUT: I2SOUT clock gating enable -// GSPI: General SPI clock gating enable -// RFSPI: RF SPI clock gating enable -// SLOWFLASH: Slow flash clock gating enable -// -// -// Clock Gating Control 3 Register (CLKGATE3) -// DOZEMODE: Doze mode enable -// CLKMODE: Clock mode enable -// -// -// Clock Core Configure Register (CORECFG) -// HCLK: HCLK config -// CPUCLK: CPU Clock config -// -// -// -*/ - - - -/** @addtogroup RDA5991H_System_Defines RDA5991H System Defines - @{ - */ - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define RDA_SYS_CLK_FREQUENCY_40M ( 40000000UL) -#define RDA_SYS_CLK_FREQUENCY_80M ( 80000000UL) -#define RDA_SYS_CLK_FREQUENCY_160M (160000000UL) -#define RDA_BUS_CLK_FREQUENCY_40M ( 40000000UL) -#define RDA_BUS_CLK_FREQUENCY_80M ( 80000000UL) - - -/** - * @} - */ - - -/** @addtogroup RDA5991H_System_Public_Variables RDA5991H System Public Variables - @{ - */ -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = RDA_SYS_CLK_FREQUENCY_160M; /*!< System Clock Frequency (Core Clock)*/ -uint32_t AHBBusClock = RDA_BUS_CLK_FREQUENCY_80M; /*!< AHB Bus Clock Frequency (Bus Clock)*/ - -/** - * @} - */ - - -/** @addtogroup RDA5991H_System_Public_Functions RDA5991H System Public Functions - @{ - */ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate (void) /* Get Core/Bus Clock Frequency */ -{ - uint32_t val = RDA_SCU->CORECFG; - /* Determine clock frequency according to SCU core config register values */ - switch ((val >> 12) & 0x03UL) { - case 0: - SystemCoreClock = RDA_SYS_CLK_FREQUENCY_40M; - break; - case 1: - SystemCoreClock = RDA_SYS_CLK_FREQUENCY_80M; - break; - case 2: - case 3: - SystemCoreClock = RDA_SYS_CLK_FREQUENCY_160M; - break; - } - - /* Determine clock frequency according to SCU core config register values */ - switch ((val >> 11) & 0x01UL) { - case 0: - AHBBusClock = RDA_BUS_CLK_FREQUENCY_40M; - break; - case 1: - AHBBusClock = RDA_BUS_CLK_FREQUENCY_80M; - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ -#ifndef APPLICATION_ADDR -#define APPLICATION_ADDR RDA_CODE_BASE /* vector table in flash, add support for bootloader jump */ -#endif - SCB->VTOR = APPLICATION_ADDR; - NVIC_SetPriorityGrouping(0x06); /* 1 bit for pre-emption pri */ - - __enable_irq(); -} - -/** - * @} - */ - -/** - * @} - */ diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/device/system_RDA5991H.h b/targets/TARGET_RDA/TARGET_UNO_91H/device/system_RDA5991H.h deleted file mode 100644 index 94648e10732..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/device/system_RDA5991H.h +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** - * @file: system_RDA5991H.h - * @purpose: CMSIS Cortex-M4 Device Peripheral Access Layer Header File - * for the RDA RDA5991H Device Series - * @version: V1.02 - * @date: 07. June 2018 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M3 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_RDA5991H_H -#define __SYSTEM_RDA5991H_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t AHBBusClock; /*!< AHB Bus Clock Frequency (Bus Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_RDA5991H_H */ diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/flash_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/flash_api.c deleted file mode 100644 index bebc45d97c0..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/flash_api.c +++ /dev/null @@ -1,88 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_api.h" -#include "flash_data.h" -#include "mbed_critical.h" - -#ifndef MBED_ROM_SIZE -#define MBED_FLASH_SIZE 0x100000 -#else -//there is 4K BOOTROM at beginning of the flash -#define MBED_FLASH_SIZE MBED_ROM_SIZE -#endif - - -// This file is automagically generated - -// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM -static uint32_t FLASH_ALGO[] = { - 0x4df0e92d, 0x4180f04f, 0x68082400, 0xea322203, 0xbf1c62d0, 0x50c0f040, 0x49cc6008, 0xf0106808, - 0xd1100f40, 0x00c0f040, 0x03086008, 0x68486088, 0x0001f040, 0x20006048, 0x28081c40, 0x6848d3fc, - 0x0f01f010, 0x4dc2d1fb, 0x0835f04f, 0x8000f8c5, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, - 0xf0106928, 0xd17b0f02, 0x6c704eba, 0x007cf420, 0x1010f440, 0x68b06470, 0x2040f440, 0x209f60b0, - 0x20006028, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x69286929, 0x2102b2ca, 0xf04f2705, - 0xf04f0a00, 0x2a400b01, 0xb2c0d123, 0xd9202815, 0xf36f6868, 0xf4402010, 0x60687080, 0xf00060a9, - 0x2031f92b, 0x20006028, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x602fd1fb, 0x1c402000, 0xd3fc2808, - 0xf01068e8, 0xd1fb0f01, 0xf0106928, 0xd1f20f01, 0x6868e021, 0x2010f36f, 0x7000f440, 0xf8c56068, - 0x60a9a008, 0xf908f000, 0xb000f8c5, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x2000602f, - 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x0f01f010, 0x4a88d1f2, 0x444a2100, 0x8000f8c5, - 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x1c496928, 0x6f80f5b1, 0x2401d303, 0xa000f882, - 0xf010e00d, 0xd0e90f02, 0x6968b94c, 0x0001f040, 0x6c706168, 0x00d8f440, 0xf8826470, 0x4620b000, - 0x8df0e8bd, 0x47702000, 0x47702000, 0xf000b510, 0x496ff8c3, 0x60082060, 0x1c402000, 0xd3fc2808, - 0xf01068c8, 0xd1fb0f01, 0x600a2205, 0x1c402000, 0xd3fc2808, 0xf01068c8, 0xd1fb0f01, 0xf0106908, - 0xd1f20f01, 0x68484961, 0x0001f040, 0x20006048, 0x28081c40, 0x6848d3fc, 0x0001f010, 0xbd10d1fb, - 0x4604b510, 0xf898f000, 0x20204959, 0x2004ea40, 0x20006008, 0x28081c40, 0x68c8d3fc, 0x0f01f010, - 0x2205d1fb, 0x2000600a, 0x28081c40, 0x68c8d3fc, 0x0f01f010, 0x6908d1fb, 0x0f01f010, 0x494bd1f2, - 0xf0406848, 0x60480001, 0x1c402000, 0xd3fc2808, 0xf0106848, 0xd1fb0001, 0xe92dbd10, 0xf02005f0, - 0x4845437c, 0x78004448, 0xbf142800, 0x24022432, 0x2c11ea5f, 0x68684d3e, 0x2010f36f, 0x3080f440, - 0xf04f6068, 0xbf1c0100, 0x26052706, 0xf04fd042, 0x20000800, 0xa000f812, 0xa008f8c5, 0x28041c40, - 0x1d12dbf8, 0x0801f108, 0x0f40f1b8, 0x602fdbf1, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, - 0x2000602e, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x0f02f010, 0xea44d0f2, 0x60282003, - 0xf5032000, 0x1c407380, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x2000602e, 0x28081c40, 0x68e8d3fc, - 0x0f01f010, 0x6928d1fb, 0x0f01f010, 0x1c49d1f2, 0xd3bc4561, 0x68484915, 0x0001f040, 0x20006048, - 0x28081c40, 0x6848d3fc, 0x0001f010, 0xe8bdd1fb, 0x477005f0, 0x47704408, 0x2006490d, 0x20006008, - 0x28081c40, 0x68c8d3fc, 0x0f01f010, 0x2205d1fb, 0x2000600a, 0x28081c40, 0x68c8d3fc, 0x0f01f010, - 0x6908d1fb, 0x0f02f010, 0x4770d0f2, 0x40014000, 0x17fff000, 0x40001000, 0x00000004, 0x00000000, - 0x00000000 -}; - -static const flash_algo_t flash_algo_config = { - .init = 0x1, - .uninit = 0x185, - .erase_sector = 0x1e1, - .program_page = 0x23b, - .static_base = 0x35c, - .algo_blob = FLASH_ALGO -}; - -static const sector_info_t sectors_info[] = { - {0x18000000, 0x1000}, -}; - -static const flash_target_config_t flash_target_config = { - .page_size = 0x100, - .flash_start = 0x18001000, - .flash_size = MBED_FLASH_SIZE, - .sectors = sectors_info, - .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t) -}; - -void flash_set_target_config(flash_t *obj) -{ - obj->flash_algo = &flash_algo_config; - obj->target_config = &flash_target_config; -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/gpio_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/gpio_api.c deleted file mode 100644 index e914dceaaa0..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/gpio_api.c +++ /dev/null @@ -1,121 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "rda_ccfg_api.h" - -#define GPIO_PIN_NUM 28 - -static const PinMap PinMap_GPIO[] = { - {PB_0, (GPIO_0 | 0), 0}, - {PB_1, (GPIO_0 | 1), 0}, - {PB_2, (GPIO_0 | 2), 0}, - {PB_3, (GPIO_0 | 3), 0}, - {PB_4, (GPIO_0 | 4), 0}, - {PB_5, (GPIO_0 | 5), 0}, - {PB_6, (GPIO_0 | 6), 0}, - {PB_7, (GPIO_0 | 7), 0}, - {PB_8, (GPIO_0 | 8), 0}, - {PB_9, (GPIO_0 | 9), 0}, - {PA_8, (GPIO_0 | 10), 0}, - {PA_9, (GPIO_0 | 11), 0}, - {PC_0, (GPIO_0 | 12), 1}, - {PC_1, (GPIO_0 | 13), 1}, - {PC_2, (GPIO_0 | 14), 0}, - {PC_3, (GPIO_0 | 15), 0}, - {PC_4, (GPIO_0 | 16), 0}, - {PC_5, (GPIO_0 | 17), 0}, - {PC_6, (GPIO_0 | 18), 0}, - {PC_7, (GPIO_0 | 19), 0}, - {PC_8, (GPIO_0 | 20), 0}, - {PC_9, (GPIO_0 | 21), 0}, - {PD_0, (GPIO_0 | 22), 0}, - {PD_1, (GPIO_0 | 23), 0}, - {PD_2, (GPIO_0 | 24), 0}, - {PD_3, (GPIO_0 | 25), 0}, - {PA_0, (GPIO_0 | 26), 1}, - {PA_1, (GPIO_0 | 27), 1}, - {PA_2, (GPIO_0 | 14), 1}, - {PA_3, (GPIO_0 | 15), 1}, - {PA_4, (GPIO_0 | 16), 1}, - {PA_5, (GPIO_0 | 17), 1}, - {PA_6, (GPIO_0 | 18), 1}, - {PA_7, (GPIO_0 | 19), 1}, - {NC, NC, 0} -}; - -#define PER_BITBAND_ADDR(reg, bit) (uint32_t *)(RDA_PERBTBND_BASE + (((uint32_t)(reg)-RDA_PER_BASE)<<5U) + (((uint32_t)(bit))<<2U)) - -PinName gpio_pinname(int pin_n) -{ - MBED_ASSERT(pin_n < GPIO_PIN_NUM); - return PinMap_GPIO[pin_n].pin; -} - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t func = 0; - uint32_t idx = 0; - - func = pinmap_function(pin, PinMap_GPIO); - idx = pinmap_peripheral(pin, PinMap_GPIO) & 0x001F; - pin_function(pin, func); - - return idx; -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - uint32_t gpio_idx = 0; - - obj->pin = pin; - if (pin == (PinName)NC) - return; - - gpio_idx = gpio_set(pin); - - if ((6U <= gpio_idx) && (9U >= gpio_idx)) { - rda_ccfg_gp((unsigned char)gpio_idx, 0x01U); - } - - obj->reg_out = PER_BITBAND_ADDR(&RDA_GPIO->DOUT, gpio_idx); - obj->reg_in = PER_BITBAND_ADDR(&RDA_GPIO->DIN, gpio_idx); - obj->reg_dir = PER_BITBAND_ADDR(&RDA_GPIO->DIR, gpio_idx); -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - uint32_t dir = 0x00UL; - MBED_ASSERT(obj->pin != (PinName)NC); - if (PIN_INPUT == direction) { - dir = 0x01UL; - } - if (rda_ccfg_hwver() >= 5) { - uint32_t gpio_idx = pinmap_peripheral(obj->pin, PinMap_GPIO) & 0x001F; - /* Since U05, for gpio 2/3/8/14/15/16/17/20/21, 1'b1 means output */ - if (0x00UL != (0x0033C10CUL & (0x01UL << gpio_idx))) { - dir ^= 0x01UL; - } - } - *obj->reg_dir = dir; -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/gpio_irq_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/gpio_irq_api.c deleted file mode 100644 index bee62f6ceaf..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/gpio_irq_api.c +++ /dev/null @@ -1,195 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "cmsis.h" - -#if DEVICE_INTERRUPTIN -#if defined(GPIO_IRQ_DEBUG) -#include "mbed_interface.h" -#endif /* GPIO_IRQ_DEBUG */ - -#define GPIO_PINNUM 28 -#define NONE (uint32_t)NC -#define GPIO_INT_CTRL_REG (RDA_GPIO->INTCTRL) -#define GPIO_INT_SEL_REG (RDA_GPIO->INTSEL) -#define GPIO_DATA_IN_REG (RDA_GPIO->DIN) - -typedef enum { - GPIO_IRQ_CH0, - GPIO_IRQ_CH1, - CHANNEL_NUM -} GPIO_IRQ_IDX_T; - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static uint32_t channel_pinidxs[CHANNEL_NUM] = {0}; -static uint8_t channel_bothedge_flag[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler[CHANNEL_NUM] = {NULL}; - -#if defined(GPIO_IRQ_DEBUG) -static uint32_t exception_cntr; -#endif /* GPIO_IRQ_DEBUG */ - -static GPIO_IRQ_IDX_T gpio_irq_ava_chidx(void) -{ - GPIO_IRQ_IDX_T ret; - for (ret = GPIO_IRQ_CH0; ret < CHANNEL_NUM; ret++) { - if (0 == channel_ids[ret]) - break; - } - return ret; -} - -static uint32_t gpio_irq_pinidx(PinName pin) -{ - uint8_t idx; - const uint32_t pinmap_gpio_irq[GPIO_PINNUM] = { - /* GPIO 0 ~ 13 */ - PB_0, PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PA_8, PA_9, PC_0, PC_1, - /* GPIO 14 ~ 21, Not support interrupt */ - NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, - /* GPIO 22 ~ 27 */ - PD_0, PD_1, PD_2, PD_3, PA_0, PA_1 - }; - - for (idx = 0; idx < GPIO_PINNUM; idx++) { - if (pinmap_gpio_irq[idx] == NONE) { - continue; - } else if (pinmap_gpio_irq[idx] == (uint32_t)pin) { - break; - } - } - - if (GPIO_PINNUM == idx) { - error("The pin cannot generate interrupt"); - } - return idx; -} - -static void handle_interrupt_in(void) -{ - /* Read current interrupt register */ - uint32_t int_ctrl = GPIO_INT_CTRL_REG; - uint32_t din_val = GPIO_DATA_IN_REG; - uint32_t idx; - - if (int_ctrl & (0x01UL << 16)) { - GPIO_INT_CTRL_REG |= (0x01UL << 16); - while (GPIO_INT_CTRL_REG & (0x01UL << 16)); - } - for (idx = GPIO_IRQ_CH0; idx < CHANNEL_NUM; idx++) { - if (int_ctrl & (0x01UL << (21 + idx))) { - gpio_irq_event flagRiseFall_1, flagRiseFall_2; - GPIO_INT_CTRL_REG |= (0x01UL << (17 + idx)); // clear int flag - flagRiseFall_1 = (int_ctrl & (0x01UL << (2 + idx))) ? IRQ_RISE : IRQ_FALL; - flagRiseFall_2 = (din_val & (0x01UL << channel_pinidxs[idx])) ? IRQ_RISE : IRQ_FALL; - if (flagRiseFall_1 == flagRiseFall_2) { - if (channel_bothedge_flag[idx]) { - GPIO_INT_CTRL_REG ^= (0x01UL << (2 + idx)); - } - irq_handler[idx](channel_ids[idx], flagRiseFall_1); -#if defined(GPIO_IRQ_DEBUG) - exception_cntr = 0; -#endif /* GPIO_IRQ_DEBUG */ - } -#if defined(GPIO_IRQ_DEBUG) - else { - exception_cntr++; - if (exception_cntr >= 2) { - exception_cntr = 0; - mbed_error_printf("invalid gpio irq: %d,%d\r\n", (int)flagRiseFall_1, (int)flagRiseFall_2); - } - } -#endif /* GPIO_IRQ_DEBUG */ - } - } -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - uint32_t regval; - - if (pin == NC) return -1; - - obj->ch = (uint16_t)gpio_irq_ava_chidx(); - MBED_ASSERT(CHANNEL_NUM != obj->ch); - - irq_handler[obj->ch] = handler; - - channel_ids[obj->ch] = id; - channel_pinidxs[obj->ch] = gpio_irq_pinidx(pin); - - regval = RDA_GPIO->INTSEL & ~(0x3FFUL << 10); - RDA_GPIO->INTSEL = regval | (0x3FFUL << 10); - - NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in); - NVIC_SetPriority(GPIO_IRQn, 0x1FUL); - NVIC_EnableIRQ(GPIO_IRQn); - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - channel_ids[obj->ch] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t reg_val; - uint16_t intEn; - MBED_ASSERT(1 >= obj->ch); - - if (IRQ_RISE == event) { - obj->flagR = (uint8_t)enable; - } else { - obj->flagF = (uint8_t)enable; - } - if (obj->flagR && obj->flagF) - channel_bothedge_flag[obj->ch] = 1U; - else - channel_bothedge_flag[obj->ch] = 0U; - if (obj->flagR || obj->flagF) - intEn = 1; - else - intEn = 0; - - if (0 == intEn) { - GPIO_INT_CTRL_REG &= ~(0x01UL << (6 + obj->ch)); - } else { - /* Set interrupt select reg */ - reg_val = GPIO_INT_SEL_REG & ~(0x1FUL << (5 * obj->ch)); - GPIO_INT_SEL_REG = reg_val | ((0x1FUL & ((channel_pinidxs[obj->ch] >= 22) ? (channel_pinidxs[obj->ch] - 8) : channel_pinidxs[obj->ch])) << (5 * obj->ch)); - - /* Set interrupt control reg */ - reg_val = GPIO_INT_CTRL_REG & ~(0x01UL << (2 + obj->ch)); - GPIO_INT_CTRL_REG = reg_val | (((0U == channel_bothedge_flag[obj->ch]) && (1U == obj->flagR)) ? (0x01UL << (2 + obj->ch)) : (0x00UL)) - | (0x01UL << (6 + obj->ch)); - } -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(GPIO_IRQn); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(GPIO_IRQn); -} - -#endif /* DEVICE_INTERRUPTIN */ diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/gpio_object.h b/targets/TARGET_RDA/TARGET_UNO_91H/gpio_object.h deleted file mode 100644 index f942bd0865d..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/gpio_object.h +++ /dev/null @@ -1,53 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - __IO uint32_t *reg_dir; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - *obj->reg_out = ((value) ? 1 : 0); -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/mbed_overrides.c b/targets/TARGET_RDA/TARGET_UNO_91H/mbed_overrides.c deleted file mode 100644 index efba2c03c1a..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/mbed_overrides.c +++ /dev/null @@ -1,27 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "cmsis.h" -#include "mbed_error.h" -#include "rda_ccfg_api.h" - -extern void sleep_cal_lpo(unsigned int calms); - -/* This function is called after RAM initialization and before main. */ -void mbed_sdk_init(void) -{ - /* Update the SystemCoreClock variable. */ - SystemCoreClockUpdate(); -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/objects.h b/targets/TARGET_RDA/TARGET_UNO_91H/objects.h deleted file mode 100644 index 80b59b0f79f..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/objects.h +++ /dev/null @@ -1,101 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "gpio_object.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint16_t ch; - uint8_t flagR; - uint8_t flagF; -}; - -struct port_s { - PortName port; - uint32_t mask; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - __IO uint32_t *reg_dir; -}; - -struct pwmout_s { - uint32_t channel; - uint32_t *base_clk_ptr; - uint32_t period_ticks; - uint32_t pulsewidth_ticks; - uint32_t period_ticks_max; - uint32_t period_ticks_min; - PinName pin; - __IO uint32_t *CFGR; -}; - -struct serial_s { - RDA_UART_TypeDef *uart; - int index; -}; - -struct i2s_s { - RDA_I2S_TypeDef *i2s; -}; - -struct wdt_s { - RDA_WDT_TypeDef *wdt; -}; - -struct analogin_s { - ADCName adc; -}; - -struct gpadc_s { - GPADCName ch; - PinName pin; -}; - -#if 0 -struct dac_s { - DACName dac; -}; -#endif - -struct i2c_s { - RDA_I2C0_TypeDef *i2c; -}; - -struct spi_s { - RDA_SPI_TypeDef *spi; - uint8_t bit_ofst[2]; -}; - -struct trng_s { - uint8_t dma_clk_flag; - uint8_t byte_idx; - uint32_t trng_data0; -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/pinmap.c b/targets/TARGET_RDA/TARGET_UNO_91H/pinmap.c deleted file mode 100644 index 04c0286d72a..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/pinmap.c +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "rda_ccfg_api.h" - -void pin_function(PinName pin, int function) -{ - int index = pin >> PORT_SHIFT; - int raw_ofst = pin & 0x00FF; - int offset; - - MBED_ASSERT(pin != (PinName)NC); - - switch (index) { - case 1: - if ((8 == raw_ofst) && (rda_ccfg_hwver() >= 5)) { - function ^= 0x01; - } - break; - case 4: - if (1 < raw_ofst) { - offset = raw_ofst << 1; - RDA_PINCFG->MODE2 &= ~(0x03UL << offset); - } - break; - case 5: - if (2 > raw_ofst) { - offset = (raw_ofst << 1) + 20; - RDA_PINCFG->MODE2 &= ~(0x03UL << offset); - } else { - offset = (raw_ofst << 1) - 4; - RDA_PINCFG->MODE3 &= ~(0x03UL << offset); - } - break; - default: - break; - } - - offset = raw_ofst * 3; - RDA_PINCFG->IOMUXCTRL[index] &= ~(0x07UL << offset); - RDA_PINCFG->IOMUXCTRL[index] |= ((function & 0x07UL) << offset); -} - -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/port_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/port_api.c deleted file mode 100644 index 00f975ba2a4..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/port_api.c +++ /dev/null @@ -1,81 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" - -extern PinName gpio_pinname(int pin_n); - -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)((port << PORT_SHIFT) | pin_n); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t i; - - obj->port = port; - obj->mask = mask; - - obj->reg_out = &RDA_GPIO->DOUT; - obj->reg_in = &RDA_GPIO->DIN; - obj->reg_dir = &RDA_GPIO->DIR; - - // The mode is set per pin: reuse gpio logic - for (i = 0; i < 32; i++) { - if (obj->mask & (1 << i)) { - // For RDA5991H, port0,1,4,5 is about IOMUX, not GPIO number, cannot use port_pin here - //gpio_set(port_pin(obj->port, i)); - gpio_set(gpio_pinname(i)); - } - } - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i = 0; i < 32; i++) { - if (obj->mask & (1 <port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - switch (dir) { - case PIN_INPUT : - *obj->reg_dir |= obj->mask; - break; - case PIN_OUTPUT: - *obj->reg_dir &= ~obj->mask; - break; - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - return (*obj->reg_in & obj->mask); -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/pwmout_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/pwmout_api.c deleted file mode 100644 index 98854a2b6d0..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/pwmout_api.c +++ /dev/null @@ -1,399 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#if DEVICE_PWMOUT -#include "mbed_assert.h" -#include "pwmout_api.h" -#include "gpio_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_interface.h" - -#define PWM_CLK_SRC_20MHZ (20000000) -#define PWM_CLK_SRC_32KHZ (32768) -#define PWM_CLK_IDX_NUM (3) - -#define PWM_CLKGATE_REG (RDA_SCU->CLKGATE1) -#define PWM_CLKSRC_REG (RDA_SCU->PWMCFG) -#define PWM_CLKDIV_REG (RDA_PWM->CLKR) -#define EXIF_PWM_EN_REG (RDA_EXIF->MISCCFG) - -/* PORT ID, PWM ID, Pin function */ -static const PinMap PinMap_PWM[] = { - {PA_0, PWM_6, 4}, - {PA_1, PWM_3, 4}, - {PB_0, PWM_2, 4}, - {PB_1, PWM_7, 4}, - {PB_2, PWM_5, 4}, - {PB_3, PWM_4, 4}, - {PB_8, PWM_0, 4}, - {PC_1, PWM_1, 5}, - {PD_0, PWM_0, 4}, - {PD_1, PWM_1, 4}, - {PD_2, PWM_2, 4}, - {PD_3, PWM_3, 4}, - {NC, NC, 0} -}; - -__IO uint32_t *PWM_MATCH[] = { - &(RDA_EXIF->PWM0CFG), - &(RDA_EXIF->PWM1CFG), - &(RDA_EXIF->PWM2CFG), - &(RDA_EXIF->PWM3CFG), - &( RDA_PWM->PWTCFG ), - &( RDA_PWM->LPGCFG ), - &( RDA_PWM->PWL0CFG), - &( RDA_PWM->PWL1CFG) -}; - -static uint32_t BaseClk_PWM[PWM_CLK_IDX_NUM] = {0UL}; - -static uint8_t is_pwmout_started(pwmout_t* obj); -static void pwmout_start(pwmout_t* obj); -static void pwmout_stop(pwmout_t* obj); -static void pwmout_update_cfgreg(pwmout_t* obj); - -void pwmout_clk_set(pwmout_t *obj, int src, int div) -{ - uint32_t reg_val = 0UL; - uint32_t clk_idx = 0UL, clk_hz = PWM_CLK_SRC_32KHZ >> 1; - PWMName pwm = (PWMName)(obj->channel); - uint32_t divider = (uint32_t)div; - - MBED_ASSERT(PWM_7 >= pwm); - if (PWM_5 == pwm) { - clk_idx = 1; - } else if (PWM_6 <= pwm) { - clk_idx = 2; - } - if (divider > 0x80UL) { // max divider is 128 - divider = 0x80UL; - } - reg_val = PWM_CLKSRC_REG & ~((0x00FFUL << (clk_idx * 8)) | (0x01UL << (24 + clk_idx))); - if (src) { - reg_val |= (0x01UL << (7 + (clk_idx * 8))); - clk_hz = PWM_CLK_SRC_20MHZ >> 1; - } - if (divider) { - reg_val |= ((divider - 0x01UL) << (clk_idx * 8)); - BaseClk_PWM[clk_idx] = clk_hz / divider; - } else { - BaseClk_PWM[clk_idx] = clk_hz; - } - PWM_CLKSRC_REG = reg_val | (0x01UL << (24 + clk_idx)); -} - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - /* determine the channel */ - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - obj->channel = pwm; - obj->CFGR = PWM_MATCH[pwm]; - obj->pin = pin; - - /* Enable PWM Clock-gating */ - PWM_CLKGATE_REG |= (0x01UL << 2); - - /* Init PWM clock source and divider */ - if (PWM_4 >= pwm) { - /* default to 20MHz / 2 */ - pwmout_clk_set(obj, 1, 0); - if (PWM_4 == pwm) { - obj->period_ticks_max = 0x1FF8UL; - obj->period_ticks_min = 0x0008UL; - } else { - obj->period_ticks_max = 0x20000UL; - obj->period_ticks_min = 0x00002UL; - } - obj->base_clk_ptr = &(BaseClk_PWM[0]); - } else if (PWM_5 == pwm) { - /* default to 32KHz / 2 */ - pwmout_clk_set(obj, 0, 0); - obj->period_ticks_max = 0x7000UL; - obj->period_ticks_min = 0x0800UL; - obj->base_clk_ptr = &(BaseClk_PWM[1]); - } else { - /* default to 20MHz / 2 */ - pwmout_clk_set(obj, 1, 0); - //do not need to div - obj->period_ticks_max = 0x0FFUL; // TBD - obj->period_ticks_min = 0x001UL; - obj->base_clk_ptr = &(BaseClk_PWM[2]); - } - - // default to half of max period - if (PWM_5 >= pwm) { - pwmout_period_us(obj, (obj->period_ticks_max * 1e6) / (*(obj->base_clk_ptr)) / 2); - } - //PWM6 PWM7 has no period - pwmout_write (obj, 0.5f); - - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); -} - -void pwmout_free(pwmout_t* obj) -{ - /* Disable PWM Clock-gating */ - PWM_CLKGATE_REG &= ~(0x01UL << 2); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - uint32_t ticks; - - /* Check if already started */ - if (is_pwmout_started(obj)) - pwmout_stop(obj); - - if (value < 0.0f) { - value = 0.0; - } else if (value > 1.0f) { - value = 1.0; - } - - /* Set channel match to percentage */ - if (PWM_5 >= (PWMName)obj->channel) { - ticks = (uint32_t)((float)(obj->period_ticks) * value); - } - else if (PWM_6 <= (PWMName)obj->channel) { - obj->period_ticks = 0xFF; - ticks = (uint32_t)((float)(obj->period_ticks) * value); - } - if (0 == ticks) { - obj->pulsewidth_ticks = 0; - } else { - /* Update Hw reg */ - if (ticks != obj->pulsewidth_ticks) { - obj->pulsewidth_ticks = ticks; - pwmout_update_cfgreg(obj); - } - } - /* Start PWM module */ - pwmout_start(obj); -} - -float pwmout_read(pwmout_t* obj) -{ - float v = (float)(obj->pulsewidth_ticks) / (float)(obj->period_ticks); - return (v > 1.0f) ? (1.0f) : (v); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -/* Set the PWM period, keeping the duty cycle the same. */ -void pwmout_period_us(pwmout_t* obj, int us) -{ - uint32_t ticks; - MBED_ASSERT(PWM_5 >= (PWMName)(obj->channel)); - - /* Check if already started */ - if (is_pwmout_started(obj)) - pwmout_stop(obj); - - /* Calculate number of ticks */ - ticks = (uint64_t)(*(obj->base_clk_ptr)) * us / 1000000; - - if (ticks != obj->period_ticks) { - float duty_ratio; - - /* Preserve the duty ratio */ - if (0 == obj->period_ticks) - duty_ratio = 0.5f; - else - duty_ratio = (float)obj->pulsewidth_ticks / (float)obj->period_ticks; - obj->period_ticks = ticks; - obj->pulsewidth_ticks = (uint32_t)(ticks * duty_ratio); - MBED_ASSERT(obj->period_ticks >= obj->pulsewidth_ticks); - - pwmout_update_cfgreg(obj); - } - - /* Start PWM module */ - pwmout_start(obj); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -/* Set the PWM pulsewidth, keeping the period the same. */ -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - uint32_t ticks; - - MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel)); - - /* Check if already started */ - if (is_pwmout_started(obj)) - pwmout_stop(obj); - - /* Calculate number of ticks */ - ticks = (uint64_t)(*(obj->base_clk_ptr)) * us / 1000000; - - if (ticks != obj->pulsewidth_ticks) { - obj->pulsewidth_ticks = ticks; - MBED_ASSERT(obj->period_ticks >= obj->pulsewidth_ticks); - - pwmout_update_cfgreg(obj); - } - - /* Start PWM module */ - pwmout_start(obj); -} - -static uint8_t is_pwmout_started(pwmout_t* obj) -{ - uint8_t retVal = 0; - uint32_t reg_val; - - MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel)); - - if (PWM_3 >= (PWMName)obj->channel) { - reg_val = (EXIF_PWM_EN_REG >> 8) & 0x0FUL; - if (reg_val & (0x01UL << obj->channel)) - retVal = 1; - } else if (PWM_4 == (PWMName)obj->channel) { - if (*(obj->CFGR) & (0x01UL << 1)) - retVal = 1; - } else if (PWM_5 == (PWMName)obj->channel) { - retVal = 1; - } else { - if (*(obj->CFGR) & (0x01UL << 16)) - retVal = 1; - } - - return retVal; -} - -static void pwmout_start(pwmout_t* obj) -{ - MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel)); - - if (obj->period_ticks == obj->pulsewidth_ticks) { - gpio_t gpio; - gpio_init_out(&gpio, obj->pin); - gpio_write(&gpio, 1); - //mbed_error_printf("100\n"); - } else if (0 == obj->pulsewidth_ticks) { - gpio_t gpio; - gpio_init_out(&gpio, obj->pin); - gpio_write(&gpio, 0); - //mbed_error_printf("0\n"); - } else { - pinmap_pinout(obj->pin, PinMap_PWM); - } - - if (PWM_3 >= (PWMName)obj->channel) { - EXIF_PWM_EN_REG |= (0x01UL << (8 + obj->channel)); - } else if (PWM_4 == (PWMName)obj->channel) { - *(obj->CFGR) |= 0x01UL; - } else if (PWM_5 == (PWMName)obj->channel) { - /* Nothing to be done */ - } else { - *(obj->CFGR) |= (0x01UL << 16); - } -} - -static void pwmout_stop(pwmout_t* obj) -{ - MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel)); - - if (obj->period_ticks == obj->pulsewidth_ticks) { - gpio_t gpio; - gpio_init_out(&gpio, obj->pin); - gpio_write(&gpio, 0); - } - - if (PWM_3 >= (PWMName)obj->channel) { - EXIF_PWM_EN_REG &= ~(0x01UL << (8 + obj->channel)); - } else if (PWM_4 == (PWMName)(obj->channel)) { - *(obj->CFGR) &= ~0x01UL; - } else if (PWM_5 == (PWMName)(obj->channel)) { - /* Nothing to be done */ - } else { - *(obj->CFGR) &= ~(0x01UL << 16); - } -} - -static void pwmout_update_cfgreg(pwmout_t* obj) -{ - int err_code = 0; - if (obj->pulsewidth_ticks < obj->period_ticks_min) { - obj->pulsewidth_ticks = obj->period_ticks_min; - err_code = 1; // too small duty - if (obj->period_ticks < obj->period_ticks_min) { - obj->period_ticks = obj->period_ticks_min; - err_code = 2; // too small duty & period - } - } - if (obj->period_ticks > obj->period_ticks_max) { - obj->period_ticks = obj->period_ticks_max; - err_code = 3; // too large period - if (obj->pulsewidth_ticks > obj->period_ticks_max) { - obj->pulsewidth_ticks = obj->period_ticks_max; - err_code = 4; // too large period & duty - } - } - if (0 != err_code) { - mbed_error_printf("PwmCfgErr:%d\r\n",err_code); - } - if (PWM_3 >= (PWMName)(obj->channel)) { - if (obj->period_ticks == obj->pulsewidth_ticks) { - *(obj->CFGR) = ((obj->pulsewidth_ticks - 1) << 16); - } else { - *(obj->CFGR) = ((obj->period_ticks - obj->pulsewidth_ticks - 1) & 0xFFFFUL) | - ((obj->pulsewidth_ticks - 1) << 16); - } - } else if (PWM_4 == (PWMName)(obj->channel)) { - *(obj->CFGR) = ((obj->pulsewidth_ticks & ~0x07UL) << ( 4 - 3)) | - ((obj->period_ticks & ~0x07UL) << (16 - 3)); - } else if (PWM_5 == (PWMName)(obj->channel)) { - /* TBD */ - uint32_t reg_val = *(obj->CFGR) & ~(0xFUL << 4) & ~(0x7UL << 16); - uint32_t lpg_field_ontime = (0x01UL << 4) & (0xFUL << 4); // to be confirm - uint32_t lpg_field_period = (obj->period_ticks << 4) & (0x7UL << 16); - *(obj->CFGR) = reg_val | lpg_field_ontime | lpg_field_period; - } else if (PWM_6 == (PWMName)(obj->channel)) { - uint32_t reg_val = *(obj->CFGR) & ~(0xFF); - *(obj->CFGR) = reg_val | (obj->pulsewidth_ticks);//1~254 - } else{ - //PWM_7 - uint32_t reg_val = *(obj->CFGR) & ~(0xFF); - *(obj->CFGR) = reg_val | (obj->pulsewidth_ticks);//1~254 - } -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/rda_ccfg_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/rda_ccfg_api.c deleted file mode 100644 index f91a5d03e5d..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/rda_ccfg_api.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "rda_ccfg_api.h" -#include "RDA5991H.h" - -#define CLK_FREQ_40M (0x00U) -#define CLK_FREQ_80M (0x01U) -#define CLK_FREQ_160M (0x02U) -#define ADDR2REG(addr) (*((volatile unsigned int *)(addr))) - -#define RF_SPI_REG ADDR2REG(0x4001301CUL) -#define TRAP_CTRL_REG ADDR2REG(0x40011000UL) -#define TRAP0_SRC_REG ADDR2REG(0x40011004UL) -#define TRAP0_DST_REG ADDR2REG(0x40011024UL) -#define TRAP1_SRC_REG ADDR2REG(0x40011008UL) -#define TRAP1_DST_REG ADDR2REG(0x40011028UL) -#define SPIF_CFG_REG ADDR2REG(0x17FFF014UL) - -#define SYS_CPU_CLK CLK_FREQ_160M -#define AHB_BUS_CLK CLK_FREQ_80M - -extern void core_util_critical_section_enter(void); -extern void core_util_critical_section_exit(void); - -static int ChipHwVersion = 0; - -static inline void wr_rf_usb_reg(unsigned char a, unsigned short d, int isusb) -{ - core_util_critical_section_enter(); - while(RF_SPI_REG & (0x01UL << 31)); - while(RF_SPI_REG & (0x01UL << 31)); - RF_SPI_REG = (unsigned int)d | ((unsigned int)a << 16) | (0x01UL << 25) | ((isusb) ? (0x01UL << 27) : 0x00UL); - core_util_critical_section_exit(); -} - -static inline void rd_rf_usb_reg(unsigned char a, unsigned short *d, int isusb) -{ - core_util_critical_section_enter(); - while(RF_SPI_REG & (0x01UL << 31)); - while(RF_SPI_REG & (0x01UL << 31)); - RF_SPI_REG = ((unsigned int)a << 16) | (0x01UL << 24) | (0x01UL << 25) | ((isusb) ? (0x01UL << 27) : 0x00UL); - __asm volatile ("nop"); - while(RF_SPI_REG & (0x01UL << 31)); - while(RF_SPI_REG & (0x01UL << 31)); - *d = (unsigned short)(RF_SPI_REG & 0xFFFFUL); - core_util_critical_section_exit(); -} - -/* Power down the debug-usage I2C */ -static inline void rda_ccfg_pdi2c(void) -{ - unsigned int val = RDA_PINCFG->MUX2; - if(0x00UL == (val & 0x3FUL)) { - RDA_PINCFG->MUX2 = val | 0x09UL; - } - wr_rf_usb_reg(0xA1, 0x0000, 0); -} - -/* Config CPU & Bus clock */ -static inline void rda_ccfg_ck(void) -{ - unsigned short val = 0U, cfg = 0U; - - cfg = (RDA_SCU->CORECFG >> 11) & 0x07U; - rd_rf_usb_reg(0xA4, &val, 0); - - // If i2c_wakeup_en is already set, do nothing and return - if((val & 0x01U) == 0x00U) { - return; - } - -#if ((SYS_CPU_CLK == CLK_FREQ_160M) && (AHB_BUS_CLK == CLK_FREQ_80M)) - /* HCLK inv */ - if(((CLK_FREQ_40M << 1) | CLK_FREQ_40M) == cfg) { - val |= (0x01U << 12); - } -#endif /* CLK_FREQ_160M && CLK_FREQ_80M */ - /* Config CPU & BUS clock */ - cfg ^= (((SYS_CPU_CLK << 1) | AHB_BUS_CLK) & 0x07U); - val &= ~(0x07U << 9); /* bit[11:10] = 2'b00:40M, 2'b01:80M, 2'b1x:160M */ - val |= (cfg << 9); /* bit[9] = 1'b0:40M, 1'b1:80M */ - val &= ~(0x01U); /* i2c_wakeup_en */ - wr_rf_usb_reg(0xA4, val, 0); -} - -/* Config SPI flash clock */ -static inline void rda_ccfg_spifck(void) -{ - unsigned int val; - __DSB(); - val = SPIF_CFG_REG & ~(0x00FFUL << 8); - SPIF_CFG_REG = val | (0x0004UL << 8); // divider - __DSB(); -} - -/* Handle abort booting */ -static inline int rda_ccfg_abort_hdlr(void) -{ - int ret = 0; - unsigned short val = 0U; - rd_rf_usb_reg(0xA1, &val, 0); - ret = (int)((val >> 2) & 0x01U); - if(ret) { - unsigned short val2 = 0U; - rd_rf_usb_reg(0xB2, &val2, 0); - wr_rf_usb_reg(0xB2, (val2 | (0x01U << 11)), 0); - RDA_GPIO->PCCTRL |= (0x01UL << 31); // set abort flag - for(val = 0; val < 0x00FFU; val++) { // delay - ; - } - wr_rf_usb_reg(0xB2, (val2 & ~(0x01U << 11)), 0); - } - return ret; -} - -/* Power up the always-on timer */ -void rda_ccfg_aontmr(void) -{ - unsigned short val = 0U; - rd_rf_usb_reg(0xA3, &val, 0); - if (0x00U == (val & (0x01U << 12))) { - wr_rf_usb_reg(0xA3, (val | (0x01U << 12)), 0); - } -} - -/* Config clock source of always-on timer */ -void rda_ccfg_aontmr_cksrc(int cksrc) -{ - unsigned short val; - if(0 == cksrc) { // use lpo 32K clk, hw default - wr_rf_usb_reg(0xDD, 0x5100U, 0); - rd_rf_usb_reg(0xD8, &val, 0); - wr_rf_usb_reg(0xD8, (val & ~(0x03U << 14)), 0); - rd_rf_usb_reg(0xA8, &val, 0); - val |= ((0x01U << 10) | (0x01U << 14)); - wr_rf_usb_reg(0xA8, (val & ~(0x01U << 12)), 0); - } else { // use 6m5xtal 32K clk, more accurate - int idx; - wr_rf_usb_reg(0xDD, 0x8100U, 0); - rd_rf_usb_reg(0xD8, &val, 0); - wr_rf_usb_reg(0xD8, (val | (0x01U << 15)), 0); - for(idx = 0; idx < 5; idx++) { // for dealy - rd_rf_usb_reg(0x00, &val, 0); - } - wr_rf_usb_reg(0xDD, 0x9100U, 0); - rd_rf_usb_reg(0xD8, &val, 0); - wr_rf_usb_reg(0xD8, (val | (0x01U << 15) | (0x01U << 14)), 0); - rd_rf_usb_reg(0xA8, &val, 0); - val &= ~((0x01U << 10) | (0x01U << 14)); - wr_rf_usb_reg(0xA8, (val | (0x01U << 12)), 0); - } -} - -/* Config GPIO6 to dig core */ -void rda_ccfg_gp6(unsigned short cfg) -{ - unsigned short val = 0U; - rd_rf_usb_reg(0xCD, &val, 0); - val &= ~(0x01U << 11); - wr_rf_usb_reg(0xCD, (val | ((cfg & 0x01U) << 11)), 0); -} - -/* Config GPIO7 to dig core */ -void rda_ccfg_gp7(unsigned short cfg) -{ - unsigned short val = 0U; - rd_rf_usb_reg(0xB0, &val, 0); - val &= ~(0x01U << 14); - wr_rf_usb_reg(0xB0, (val | ((cfg & 0x01U) << 14)), 0); -} - -/* Config GPIO6/7/8/9 to pmu intf or dig core */ -void rda_ccfg_gp(unsigned char gp, unsigned short cfg) -{ - unsigned short val = 0U; - unsigned char reg = 0xCDU; - const int ofs_lst[4] = {11, 14, 10, 9}; - if((6 > gp) || (9 < gp)) { - return; - } - if(7 == gp) { - reg = 0xB0U; - } - rd_rf_usb_reg(reg, &val, 0); - val &= ~(0x01U << ofs_lst[gp - 6]); - wr_rf_usb_reg(reg, (val | ((cfg & 0x01U) << ofs_lst[gp - 6])), 0); -} - -/* Set some core config when booting */ -int rda_ccfg_boot(void) -{ - int ret = 1; - int abort_flag = rda_ccfg_abort_hdlr(); - if(!abort_flag) { - rda_ccfg_pdi2c(); - } - /*close usb polling*/ - RDA_GPIO->CTRL &= ~(0x01UL << 12); - rda_ccfg_ck(); - /* Set flash clock */ - rda_ccfg_spifck(); - /* Set aon timer clock source */ - rda_ccfg_aontmr_cksrc(1); - return ret; -} - -/* Reset CPU & Bus clock config */ -void rda_ccfg_ckrst(void) -{ - unsigned short val = 0U; - - rd_rf_usb_reg(0xA4, &val, 0); - /* HCLK inv */ - val &= ~(0x01U << 12); - /* Config CPU clock */ - val &= ~(0x03U << 10); - val |= (0x00U << 10); /* 2'b00:40M, 2'b01:80M, 2'b1x:160M */ - /* Config BUS clock */ - val &= ~(0x01U << 9); - val |= (0x00U << 9); /* 1'b0:40M, 1'b1:80M */ - - val |= (0x01U); /* clear i2c_wakeup_en */ - wr_rf_usb_reg(0xA4, val, 0); -} - -/* Reset peripheral module */ -void rda_ccfg_perrst(void) -{ - unsigned int idx = 0x0FUL; - RDA_SCU->RESETCTRL &= ~(0x01UL << 11); // soft_resetn_bb - for (; idx>0; idx--); - RDA_SCU->RESETCTRL |= (0x01UL << 11); -} - -/* Init ADC module */ -void rda_ccfg_adc_init(void) -{ - unsigned short val = 0U; - rd_rf_usb_reg(0xA3, &val, 0); /* adc en */ - wr_rf_usb_reg(0xA3, (val | (0x01U << 3)), 0); - rd_rf_usb_reg(0xD8, &val, 0); /* clk 6p5m en */ - wr_rf_usb_reg(0xD8, (val | (0x01U << 15)), 0); - rd_rf_usb_reg(0xB7, &val, 0); /* clk 26m en */ - wr_rf_usb_reg(0xB7, (val | (0x01U << 14)), 0); -} - -/* Config GPIO6/7/8 pdn or pup for ADC usage */ -void rda_ccfg_adc_gp(unsigned char gp, unsigned short cfg) -{ - unsigned short val = 0U; - const int ofs_lst[3] = {8, 9, 7}; - if((6 > gp) || (8 < gp)) { - return; - } - rd_rf_usb_reg(0xB2, &val, 0); - val &= ~(0x01U << ofs_lst[gp - 6]); - wr_rf_usb_reg(0xB2, (val | ((cfg & 0x01U) << ofs_lst[gp - 6])), 0); -} - -/* Config GPADC oenb, use be config to 1 in either Normal mode or GPADC mode */ -void rda_ccfg_adc_oenb(unsigned char ch, unsigned short cfg) -{ - unsigned short val = 0U; - unsigned char offset = 0U; - int ver = rda_ccfg_hwver(); - - if ((ch > 1) || (cfg > 1)) - return; - - if (0 == ch) { - offset = 2; - } else { - if (ver <= 2) - offset = 3; - else if (ver >= 4) - offset = 1; - } - - rd_rf_usb_reg(0xB0, &val, 0); - val &= ~(0x01U << offset); - val |= (cfg << offset); - wr_rf_usb_reg(0xB0, val, 0); -} - -/* Read ADC value */ -unsigned short rda_ccfg_adc_read(unsigned char ch) -{ - unsigned short val = 0U; - rd_rf_usb_reg(0xB7, &val, 0); /* set vref */ - val &= ~((0x03U) << 12); /* verf 1.7V */ - if(!((2U == ch) && (rda_ccfg_hwver() <= 4))) { - val |= ((0x02U) << 12); /* verf 2.0V */ - } - wr_rf_usb_reg(0xB7, val, 0); - - rd_rf_usb_reg(0xB6, &val, 0); /* channel select */ - val &= ~((0x03U) << 12); - wr_rf_usb_reg(0xB6, (val | ((ch & 0x03U) << 12)), 0); - - rd_rf_usb_reg(0xB6, &val, 0); /* set read en */ - wr_rf_usb_reg(0xB6, (val | (0x01U << 2)), 0); - for(val = 0; val < 0x0FFU; val++) { // delay - ; - } - rd_rf_usb_reg(0xB6, &val, 0); /* clr read en */ - wr_rf_usb_reg(0xB6, (val & ~(0x01U << 2)), 0); - - do { - rd_rf_usb_reg(0xB7, &val, 0); /* finish loop flag */ - } while(0x00U == (val & (0x01U << 10))); - return (val & 0x03FFU); -} - -/* Free ADC module */ -void rda_ccfg_adc_free(void) -{ - unsigned short val = 0U; - rd_rf_usb_reg(0xA3, &val, 0); /* adc disable */ - wr_rf_usb_reg(0xA3, (val & ~(0x01U << 3)), 0); - rd_rf_usb_reg(0xB7, &val, 0); /* clk 26m disable */ - wr_rf_usb_reg(0xB7, (val & ~(0x01U << 14)), 0); -} - -/* Get abort flag */ -int rda_ccfg_abort_flag(void) -{ - int ret = 0; - if(0x00UL != (RDA_GPIO->PCCTRL & (0x01UL << 31))) { - ret = 1; - } - return ret; -} - -/* Set wdt en */ -void rda_ccfg_wdt_en(void) -{ - unsigned short val = 0U; - rd_rf_usb_reg(0xC8, &val, 0); - wr_rf_usb_reg(0xC8, (val | (0x01U << 13)), 0); -} - -unsigned short rf_reg_read(unsigned short addr) -{ - unsigned short val = 0U; - if(addr <= 0x1FF) { - if((((addr & 0xFFU) >= 0xA0) && ((addr & 0xFFU) <= 0xDF)) || - (addr == 0x30U) || (addr == 0x34U) || (addr == 0x35U)) { /* PMU & RF_30H/34H/35H */ - rd_rf_usb_reg((unsigned char)(addr & 0xFFU), &val, 0); - } else { /* RF */ - char isrun = 0; - rd_rf_usb_reg(0x30U, &val, 0); - isrun = (val & 0x01U) ? 1 : 0; - if(isrun) { - wr_rf_usb_reg(0x02U, (0x5000U | addr), 0); - rd_rf_usb_reg(0x34U, &val, 0); - } else { - if(addr & (0x01U << 8)) { - wr_rf_usb_reg(0x3FU, 1, 0); - } - rd_rf_usb_reg((unsigned char)(addr & 0xFFU), &val, 0); - if(addr & (0x01U << 8)) { - wr_rf_usb_reg(0x3FU, 0, 0); - } - } - } - } - return val; -} - -void rf_reg_write(unsigned short addr, unsigned short val) -{ - if(addr <= 0x1FF) { - if((((addr & 0xFFU) >= 0xA0) && ((addr & 0xFFU) <= 0xDF)) || - (addr == 0x30U) || (addr == 0x34U) || (addr == 0x35U)) { /* PMU & RF_30H/34H/35H */ - wr_rf_usb_reg((unsigned char)(addr & 0xFFU), val, 0); - } else { /* RF */ - char isrun = 0; - rd_rf_usb_reg(0x30U, &val, 0); - isrun = (val & 0x01U) ? 1 : 0; - if(isrun) { - wr_rf_usb_reg(0x32U, val, 0); - wr_rf_usb_reg(0x02U, (0x4000U | addr), 0); - } else { - if(addr & (0x01U << 8)) { - wr_rf_usb_reg(0x3FU, 1, 0); - } - wr_rf_usb_reg((unsigned char)(addr & 0xFFU), val, 0); - if(addr & (0x01U << 8)) { - wr_rf_usb_reg(0x3FU, 0, 0); - } - } - } - } -} - -/* Get chip hw version */ -int rda_ccfg_hwver(void) -{ - if(0 == ChipHwVersion) { - ChipHwVersion = (int)((RDA_GPIO->REVID >> 16) & 0xFFUL) + 1; - } - return ChipHwVersion; -} - diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/rda_ccfg_api.h b/targets/TARGET_RDA/TARGET_UNO_91H/rda_ccfg_api.h deleted file mode 100644 index 906f419565f..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/rda_ccfg_api.h +++ /dev/null @@ -1,44 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef RDA_CCFG_API_H -#define RDA_CCFG_API_H - -#ifdef __cplusplus -extern "C" { -#endif - -void rda_ccfg_aontmr(void); -void rda_ccfg_gp6(unsigned short cfg); -void rda_ccfg_gp7(unsigned short cfg); -void rda_ccfg_gp(unsigned char gp, unsigned short cfg); -void rda_ccfg_ckrst(void); -void rda_ccfg_perrst(void); -void rda_ccfg_adc_init(void); -void rda_ccfg_adc_gp(unsigned char gp, unsigned short cfg); -void rda_ccfg_adc_oenb(unsigned char ch, unsigned short cfg); -unsigned short rda_ccfg_adc_read(unsigned char ch); -void rda_ccfg_adc_free(void); -int rda_ccfg_abort_flag(void); -void rda_ccfg_wdt_en(void); -int rda_ccfg_hwver(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/rda_timer_isr.c b/targets/TARGET_RDA/TARGET_UNO_91H/rda_timer_isr.c deleted file mode 100644 index 691f9d45cf2..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/rda_timer_isr.c +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "us_ticker_api.h" - -#define rTIMER_INTSTATE (RDA_TIMINTST->INTST) -#define RDA_TIMER_IRQn (TIMER_IRQn) -#define TIMER0_CONTROL_ENABLE (0x01) - -extern uint32_t us_ticker_soft_int_flag; -extern void us_ticker_irq_callback(); - -static void rda_timer_isr(void) -{ - uint32_t int_status = rTIMER_INTSTATE & 0x000FUL; - - if ((int_status == 0x05) ||((int_status == 0) && (us_ticker_soft_int_flag == 1))){ - us_ticker_irq_callback(); - us_ticker_irq_handler(); - } -} - -void rda_timer_irq_set(void) -{ - NVIC_SetVector(RDA_TIMER_IRQn, (uint32_t)rda_timer_isr); - NVIC_SetPriority(RDA_TIMER_IRQn, 0x1FUL); - NVIC_EnableIRQ(RDA_TIMER_IRQn); -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/serial_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/serial_api.c deleted file mode 100644 index 593ec07ca73..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/serial_api.c +++ /dev/null @@ -1,423 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include "mbed_assert.h" -#include -#include -#include - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "gpio_api.h" - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define UART_NUM 2 - -#define UART_CLKGATE_REG (RDA_SCU->CLKGATE0) - -#define UART1_CLKEN_MASK (0x01UL << 21) -#define RXFIFO_EMPTY_MASK (0x01UL << 0) -#define TXFIFO_FULL_MASK (0x01UL << 19) -#define AFCE_MASK (0x01UL << 5) - -static const PinMap PinMap_UART_TX[] = { - {PA_1, UART_0, 0}, - {PB_2, UART_1, 5}, - {PD_3, UART_1, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PA_0, UART_0, 0}, - {PB_1, UART_1, 5}, - {PD_2, UART_1, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RTS[] = { - {PD_1, UART_1, 2}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_CTS[] = { - {PD_0, UART_1, 2}, - {NC, NC, 0} -}; - -static uart_irq_handler irq_handler[UART_NUM]; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -struct serial_global_data_s { - uint32_t serial_irq_id; - gpio_t sw_rts, sw_cts; - uint8_t count, rx_irq_set_flow, rx_irq_set_api; -}; - -static struct serial_global_data_s uart_data[UART_NUM]; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - - // determine the UART to use - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart != NC); - - switch (uart) { - case UART_0: - obj->index = 0; - break; - case UART_1: - obj->index = 1; - /* Enable clock-gating */ - UART_CLKGATE_REG |= UART1_CLKEN_MASK; - break; - } - - obj->uart = (RDA_UART_TypeDef *)uart; - - // enable fifos and default rx trigger level - obj->uart->FCR = 0 << 0 //FIFO Enable - 0 = Disables, 1 = Enabled - | 0 << 1 // Rx Fifo Reset - | 0 << 2 // Tx Fifo Reset - | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars - - // disable irqs - obj->uart->IER = 0 << 0 // Rx Data available irq enable - | 0 << 1 // Tx Fifo empty irq enable - | 0 << 2; // Rx Line Status irq enable - - obj->uart->MCR = 1 << 8; //select clock - obj->uart->FRR = 0x2001; //tx_trigger = 0x10, rx_trigger = 0x01 - - serial_format(obj, 8, ParityNone, 1); - - // pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - // set rx/tx pins in PullUp mode - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - if ((rx != NC) && (tx != NC)) { - obj->uart->FCR |= 1 << 0; //enable fifo - } - - uart_data[obj->index].sw_rts.pin = NC; - uart_data[obj->index].sw_cts.pin = NC; - serial_set_flow_control(obj, FlowControlNone, NC, NC); - - is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - serial_clear(obj); -} - -void serial_free(serial_t *obj) -{ - uart_data[obj->index].serial_irq_id = 0; -} - -// serial_baud -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) -{ - MBED_ASSERT((int)obj->uart <= UART_1); - - uint32_t baud_divisor; - uint32_t baud_mod; - - baud_divisor = (AHBBusClock / baudrate) >> 4; - baud_mod = (AHBBusClock / baudrate) & 0x0F; - - obj->uart->LCR |= (1 << 7); //enable load devisor register - - obj->uart->DLL = (baud_divisor >> 0) & 0xFF; - obj->uart->DLH = (baud_divisor >> 8) & 0xFF; - obj->uart->DL2 = (baud_mod>>1) + ((baud_mod - (baud_mod>>1))<<4); - - obj->uart->LCR &= ~(1 << 7);// after loading, disable load devisor register - -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); - - stop_bits -= 1; - data_bits -= 5; - - int parity_enable, parity_select; - switch (parity) { - case ParityNone: - parity_enable = 0; - parity_select = 0; - break; - case ParityOdd: - parity_enable = 1; - parity_select = 0; - break; - case ParityEven: - parity_enable = 1; - parity_select = 1; - break; - case ParityForced1: - parity_enable = 1; - parity_select = 2; - break; - case ParityForced0: - parity_enable = 1; - parity_select = 3; - break; - default: - parity_enable = 0; - parity_select = 0; - break; - } - - obj->uart->LCR = (obj->uart->LCR) & - ((~0x3FUL) | - (data_bits << 0) | - (stop_bits << 2) | - (parity_enable << 3) | - (parity_select << 4)); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t iir, uint32_t index, RDA_UART_TypeDef *puart) -{ - SerialIrq irq_type; - switch (iir) { - case 0x02UL: irq_type = TxIrq; break; - case 0x04UL: irq_type = RxIrq; break; - case 0x00UL: iir = puart->MSR; - default: return; - } - - if ((RxIrq == irq_type) && ((NC != uart_data[index].sw_rts.pin) && ((puart->MCR & AFCE_MASK) == 0x00UL))) { - gpio_write(&uart_data[index].sw_rts, 1); - // Disable interrupt if it wasn't enabled by other part of the application - if (!uart_data[index].rx_irq_set_api) - puart->IER &= ~(1 << RxIrq); - } - - if (uart_data[index].serial_irq_id != 0) - if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) - (irq_handler[index])(uart_data[index].serial_irq_id, irq_type); -} - -void uart0_irq(void) -{ - uart_irq((RDA_UART0->IIR & 0x0FUL), 0, (RDA_UART_TypeDef*)RDA_UART0); -} - -void uart1_irq(void) -{ - uart_irq((RDA_UART1->IIR & 0x0FUL), 1, (RDA_UART_TypeDef*)RDA_UART1); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler[obj->index] = handler; - uart_data[obj->index].serial_irq_id = id; -} - -static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case UART_0: - irq_n=UART0_IRQn; - vector = (uint32_t)&uart0_irq; - break; - case UART_1: - irq_n=UART1_IRQn; - vector = (uint32_t)&uart1_irq; - break; - default: - break; - } - - if (enable) { - obj->uart->IER |= 1 << irq; - NVIC_SetVector(irq_n, vector); - NVIC_SetPriority(irq_n, 0x1FUL); - NVIC_EnableIRQ(irq_n); - } - else if ((TxIrq == irq) || - (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - obj->uart->IER &= ~(1 << irq); - all_disabled = (obj->uart->IER & (1 << other_irq)) == 0; - if (all_disabled) - NVIC_DisableIRQ(irq_n); - } - -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - if (RxIrq == irq) - uart_data[obj->index].rx_irq_set_api = enable; - serial_irq_set_internal(obj, irq, enable); -} - -static void serial_flow_irq_set(serial_t *obj, uint32_t enable) -{ - uart_data[obj->index].rx_irq_set_flow = enable; - serial_irq_set_internal(obj, RxIrq, enable); -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) -{ - int data = 0; - while (!serial_readable(obj)); - data = (int)(obj->uart->RBR & 0x00FFUL); - - if (((obj->uart->MCR & AFCE_MASK) == 0x00UL) && (NC != uart_data[obj->index].sw_rts.pin)) { //enable flow control rx - gpio_write(&uart_data[obj->index].sw_rts, 0); - obj->uart->IER |= 1 << RxIrq; - } - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)); - obj->uart->THR = c; -} - -int serial_readable(serial_t *obj) -{ - return (obj->uart->LSR & RXFIFO_EMPTY_MASK); -} - -int serial_writable(serial_t *obj) -{ - int isWritable = 1; - if (obj->index == 0) { - return !(obj->uart->FSR & TXFIFO_FULL_MASK); // uart0 not have flow control - } else { - if (((obj->uart->MCR & AFCE_MASK) == 0x00UL) && (NC != uart_data[obj->index].sw_cts.pin)) //If flow control: writable if CTS low + UART done - isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && !(obj->uart->FSR & TXFIFO_FULL_MASK); - else - isWritable = !(obj->uart->FSR & TXFIFO_FULL_MASK); - return isWritable; - } -} - -void serial_clear(serial_t *obj) -{ - obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled - | 1 << 1 // rx FIFO reset - | 1 << 2; // tx FIFO reset -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - obj->uart->LCR |= (1 << 6); -} - -void serial_break_clear(serial_t *obj) -{ - obj->uart->LCR &= ~(1 << 6); -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - // Only UART1 has hardware flow control on RDA5991H - MBED_ASSERT((rxflow != UART0_RX) && (txflow != UART0_TX)); - - RDA_UART_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)RDA_UART1 ? RDA_UART1 : NULL; - int index = obj->index; - - // First, disable flow control completely - uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC; - serial_flow_irq_set(obj, 0); - if (FlowControlNone == type) { - RDA_GPIO->IFCTRL &= ~(0x01UL << 2); //disable flow control - return; - } - - // Check type(s) of flow control to use - UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS); - UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS); - - if ((UART_1 == uart_cts) && (NULL != uart1)) { - pinmap_pinout(txflow, PinMap_UART_CTS); - gpio_init_in(&uart_data[index].sw_cts, txflow); - } - - if ((UART_1 == uart_rts) && (NULL != uart1)) { - pinmap_pinout(rxflow, PinMap_UART_RTS); - gpio_init_out(&uart_data[index].sw_rts, rxflow); - serial_flow_irq_set(obj, 1); - } - - uart1->MCR = uart1->MCR | AFCE_MASK; //enable auto flow control, in this case we don't have to read and write sw_cts & sw_rts - uart1->FRR = (0x3EUL << 0) | (0x3EUL << 9); //rts/cts fifo trigger - RDA_GPIO->IFCTRL |= 0x01UL << 2; //enable flow control -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/sleep.c b/targets/TARGET_RDA/TARGET_UNO_91H/sleep.c deleted file mode 100644 index 96856652add..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/sleep.c +++ /dev/null @@ -1,54 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "mbed_interface.h" - -#define DEFAULT_PD_BOOTJUMPADDR (0x18001004UL) - -void hal_sleep(void) -{ - - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - // wait for interrupt - __DSB(); - __WFI(); -} - -/* -* The mbed UNO_91H does not support the deepsleep mode -* as a debugger is connected to it (the mbed interface). -* -* We treat a deepsleep() as a normal sleep(). -*/ - -void hal_deepsleep(void) -{ - uint32_t regval, gpio_num = 4; - /* Set pd write_en */ - RDA_SCU->PWRCTRL |= (0x01UL << 8); - regval = RDA_SCU->PWRCTRL | (0x01UL << 3); // gpio wakeup en - regval &= ~(0x0FUL << 9); - regval |= (gpio_num << 9); // set gpio number - RDA_SCU->PWRCTRL = regval & ~(0x01UL << 14); // posedge - RDA_SCU->BOOTJUMPADDRCFG = DEFAULT_PD_BOOTJUMPADDR; - /* Clr pd write_en */ - RDA_SCU->PWRCTRL &= ~(0x01UL << 8); - osDelay(1); - rda_ccfg_ckrst(); - osDelay(1); - RDA_SCU->PWRCTRL |= (0x01UL << 25); // goto low-power mode -} diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/spi_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/spi_api.c deleted file mode 100644 index 498dc4016b3..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/spi_api.c +++ /dev/null @@ -1,325 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#if DEVICE_SPI -#include "mbed_assert.h" -#include - -#include "spi_api.h" -#include "rda_ccfg_api.h" -#include "cmsis.h" -#include "pinmap.h" - -/*------------- Wlan Monitor (WLANMON) ---------------------------------------*/ -typedef struct -{ - __IO uint32_t PHYSEL_3_0; /* 0x00 : PHY select register 0 - 3 */ -} RDA_WLANMON_TypeDef; - -/* - * Macros - */ -#define RDA_MON ((RDA_WLANMON_TypeDef *)RDA_MON_BASE) -#define ENABLE_RDA_SPI_MODE 0 - -#define SPI_CLKGATE_REG (RDA_SCU->CLKGATE2) -#define SPI_MODESEL_REG (RDA_GPIO->CTRL) -#define SPI_PINSEL_REG0 (RDA_GPIO->MEMCFG) -#define SPI_PINSEL_REG1 (RDA_MON->PHYSEL_3_0) -#define SPI_PINSEL_REG2 (RDA_EXIF->MISCCFG) - -/* - * Global Variables - */ -static const PinMap PinMap_SPI_SCLK[] = { - {PB_4, SPI_0, 4}, - {PD_0, SPI_0, 1}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PB_6, SPI_0, 3}, - {PC_0, SPI_0, 6}, - {PD_2, SPI_0, 1}, - {PB_3, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PB_7, SPI_0, 3}, - {PC_1, SPI_0, 6}, - {PD_3, SPI_0, 1}, - {PB_8, SPI_0, 3}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PD_1, SPI_0, 1}, - {PB_5, SPI_0, 4}, - {PA_0, SPI_0, 3}, - {PA_1, SPI_0, 3}, - {NC , NC , 0} -}; - -/* - * Inline Functions - */ -static inline int spi_pin_cs_num(PinName ssel); -static inline void spi_write(spi_t *obj, int value); -static inline int spi_read(spi_t *obj); - -/* - * Functions - */ -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - uint32_t reg_val; - - /* Determine the SPI to use */ - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - obj->spi = (RDA_SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->spi != NC); - - /* Enable power and clocking */ - SPI_CLKGATE_REG |= (0x01UL << 18); - - /* Select 4-wire SPI mode */ - SPI_MODESEL_REG &= ~(0x01UL << 14); - - /* Set Config Reg */ - reg_val = obj->spi->CFG; - -#if ENABLE_RDA_SPI_MODE - /* RDA SPI mode */ - reg_val |= (0x01UL << 2); -#else /* ENABLE_RDA_SPI_MODE */ - /* Normal SPI mode */ - reg_val &= ~(0x01UL << 2); - /* Set read flag */ - reg_val |= (0x01UL << 3); -#endif /* ENABLE_RDA_SPI_MODE */ - - /* Set core cfg for mosi, miso */ - if (PB_6 == mosi) { - rda_ccfg_gp(6U, 0x01U); - } - if (PB_7 == miso) { - rda_ccfg_gp(7U, 0x01U); - } - - /* Config gpio/wlan_mon regs */ - if (PB_3 == mosi) { - SPI_MODESEL_REG &= ~(0x0FUL); - SPI_PINSEL_REG1 &= ~(0x3FUL << 24); - SPI_PINSEL_REG2 &= ~(0x0FUL << 12); - SPI_MODESEL_REG |= (0x0BUL); - SPI_PINSEL_REG1 |= (0x02UL << 24); - SPI_PINSEL_REG2 |= (0x01UL << 12); - } - if (PB_8 == miso) { - SPI_PINSEL_REG0 &= ~(0x01UL << 11); - } - - /* Pin out the SPI pins */ - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - int cs_num = spi_pin_cs_num(ssel); - reg_val &= ~(0x03UL << 23); - reg_val |= (((uint32_t)cs_num & 0x03UL) << 23); - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - obj->spi->CFG = reg_val; -} - -void spi_free(spi_t *obj) -{ - /* Disable SPI clock gating */ - SPI_CLKGATE_REG &= ~(0x01UL << 18); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - uint32_t polarity = (mode & 0x2) ? (0x01UL) : (0x00UL); - uint32_t reg_val; - -#if ENABLE_RDA_SPI_MODE - MBED_ASSERT(((bits >= 4) && (bits <= 64)) && (mode >= 0 && mode <= 3)); -#else /* ENABLE_RDA_SPI_MODE */ - MBED_ASSERT(((bits >= 4) && (bits <= 32)) && (mode >= 0 && mode <= 3)); -#endif /* ENABLE_RDA_SPI_MODE */ - - /* Set number of frame bits and clock phase */ - reg_val = obj->spi->CFG & ~(0x7FUL << 16) & ~(0x01UL << 1); - obj->spi->CFG = reg_val | ((uint32_t)bits << 16) | (polarity << 1); - -#if ENABLE_RDA_SPI_MODE - /* Set bit offset value */ - obj->bit_ofst[0] = 0; - obj->bit_ofst[1] = 0; - if (2 > (bits >> 5)) { - obj->bit_ofst[bits >> 5] = (uint8_t)(32 - (bits & 0x1F)); - } -#else /* ENABLE_RDA_SPI_MODE */ - obj->bit_ofst[0] = (uint8_t)(32 - bits); -#endif /* ENABLE_RDA_SPI_MODE */ -} - -void spi_frequency(spi_t *obj, int hz) -{ - uint32_t clk_rate = ((AHBBusClock / (uint32_t)hz) >> 2) - 1U; - uint32_t reg_val; - - /* Check for valid frequency */ - MBED_ASSERT(clk_rate <= 0x3FUL); - - /* Set clk rate field */ - reg_val = obj->spi->CFG & ~(0x3FUL << 4); - obj->spi->CFG = reg_val | ((clk_rate & 0x3FUL) << 4); -} - -int spi_master_write(spi_t *obj, int value) -{ - spi_write(obj, value); - return spi_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_busy(spi_t *obj) -{ - return (obj->spi->CFG & (0x01UL << 31)) ? (1) : (0); -} - -static inline int spi_pin_cs_num(PinName ssel) -{ - int idx = 0; - while (PinMap_SPI_SSEL[idx].pin != NC) { - if (PinMap_SPI_SSEL[idx].pin == ssel) - return idx; - idx++; - } - return (int)NC; -} - -static inline void spi_write(spi_t *obj, int value) -{ -#if ENABLE_RDA_SPI_MODE - /* Write data register */ - if (obj->bit_ofst[0] != 0) { - obj->spi->D1CMD = (uint32_t)value << obj->bit_ofst[0]; - } else { - obj->spi->D1CMD = (uint32_t)value; - obj->spi->D0CMD = (uint32_t)value << obj->bit_ofst[1]; - } - /* Set write bit & start bit */ - obj->spi->CFG = (obj->spi->CFG & ~(0x01UL << 3)) | 0x01UL; -#else /* ENABLE_RDA_SPI_MODE */ - /* Write data reg */ - if (obj->bit_ofst[0] != 0) { - obj->spi->D1CMD = ((uint32_t)value << obj->bit_ofst[0]) | (0xFFFFFFFFUL >> (32 - obj->bit_ofst[0])); - } else { - obj->spi->D1CMD = (uint32_t)value; - obj->spi->D0CMD = 0xFFFFFFFFUL; - } - /* Set start bit */ - obj->spi->CFG |= 0x01UL; -#endif /* ENABLE_RDA_SPI_MODE */ - __DSB(); - while (spi_busy(obj)); -} - -static inline int spi_read(spi_t *obj) -{ - uint32_t ret_val; - -#if ENABLE_RDA_SPI_MODE - /* Set read bit & start bit */ - obj->spi->CFG |= ((0x01UL << 3) | 0x01UL); - __DSB(); - while (spi_busy(obj)); - /* Read data register */ - if (obj->bit_ofst[0] != 0) { - ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL); - } else { - ret_val = obj->spi->D0CMD; - ret_val = obj->spi->D1CMD & ((0x01UL << (32UL - obj->bit_ofst[1])) - 1UL); - } -#else /* ENABLE_RDA_SPI_MODE */ - /* Read data register */ - ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL); -#endif /* ENABLE_RDA_SPI_MODE */ - return (int)ret_val; -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c b/targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c deleted file mode 100644 index 295db4a6bf2..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Hardware entropy collector for the UNO_91H, using RDA's TRNG - * - * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#if DEVICE_TRNG - -#include "cmsis.h" -#include "trng_api.h" -#include "us_ticker_api.h" - -#define rRNG_CLKGATE (RDA_SCU->CLKGATE0) -#define rRNG_CLKGEN (RDA_DMACFG->dma_func_ctrl) -#define rTRNG_CTRL (RDA_RNG->TCTRL) -#define rPRNG_DATA (RDA_RNG->PD) - -static uint32_t trng_inited = 0; - -/** trng_get_byte - * @brief Get one byte of entropy from the RNG, assuming it is up and running. - * @param obj TRNG obj - * @param pointer to the hardware generated random byte. - */ -static void trng_get_byte(trng_t *obj, unsigned char *byte ) -{ - if (0U == obj->byte_idx) { - uint32_t start_time = us_ticker_read(); - /* Delay for PRNG data ready, generate 4-byte per 32us */ - while ((us_ticker_read() - start_time) <= 32); - } - *byte = (unsigned char)((rPRNG_DATA >> (obj->byte_idx << 3)) & 0x00FFUL); - obj->byte_idx++; - obj->byte_idx &= 0x03U; -} - -void trng_init(trng_t *obj) -{ - uint32_t regval, start_time = 0; - volatile uint32_t count = 10; - - if(trng_inited == 1) - return; - - obj->dma_clk_flag = (uint8_t)((rRNG_CLKGATE >> 18) & 0x01U); - obj->byte_idx = 0; - if (0x00U == obj->dma_clk_flag) { - /* DMA Peripheral clock enable */ - rRNG_CLKGATE |= (0x01UL << 18); - /* dealy after clk en */ - while(count--); - } - /* RNG Engine clock enable */ - rRNG_CLKGEN |= (0x01UL << 30); - /* Set TRNG enable bit, once mode */ - regval = rTRNG_CTRL | ((0x01UL << 4) | (0xFFUL << 16)); - rTRNG_CTRL = regval & ~((0x01UL << 1) | (0x01UL << 2) | (0x01UL << 3)); - - us_ticker_init(); - - /*Entropy data was mixed by TRNG seed and noise, so we add one 32us delay to - ensure all 32 bits of seed is entropy when init and - another delay to update noise data when get data. - */ - - /* Delay for TRNG seed ready */ - start_time = us_ticker_read(); - while ((us_ticker_read() - start_time) <= 32); - - rTRNG_CTRL |= (0x01UL << 0); - - trng_inited = 1; -} - -void trng_free(trng_t *obj) -{ - if(trng_inited == 0) - return; - /* Clear TRNG enable bit */ - rTRNG_CTRL = 0x00UL; - /* RNG Engine clock disable */ - rRNG_CLKGEN &= ~(0x01UL << 30); - if (0x00U == obj->dma_clk_flag) { - /* DMA Peripheral clock disable */ - rRNG_CLKGATE &= ~(0x01UL << 18); - } - trng_inited = 0; -} - -int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) -{ - int ret = 0; - - if(trng_inited != 1) - return -1; - - /* Get Random byte */ - for (uint32_t i = 0; i < length; i++) { - trng_get_byte(obj, output + i); - } - - *output_length = length; - - return ret; -} - -int rda_trng_get_bytes(unsigned char *output, size_t len) -{ - size_t temp; - trng_t trng_obj; - trng_init(&trng_obj); - int ret = trng_get_bytes(&trng_obj, output, len, &temp); - trng_free(&trng_obj); - return ret; -} - -#endif diff --git a/targets/TARGET_RDA/TARGET_UNO_91H/us_ticker.c b/targets/TARGET_RDA/TARGET_UNO_91H/us_ticker.c deleted file mode 100644 index 960389e6af7..00000000000 --- a/targets/TARGET_RDA/TARGET_UNO_91H/us_ticker.c +++ /dev/null @@ -1,236 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "us_ticker_api.h" -#include "rda_ccfg_api.h" -#include "mbed_critical.h" - -#define US_TICKER_TIMER (RDA_TIM0) -#define rTIMER0_CURVAL (RDA_TIM0->CVAL) -#define TIMER0_PRESCALE (8) -#define TIMER0_SHIFTBITS (3) -#define TIMER0_LDCNT_INIT_VAL (0xFFFFFFFF) -#define TIMER0_MAX_COUNT (0x1FFFFFFF) - -#define TIMER0_CONTROL_ENABLE (0x01) -#define TIMER0_CONTROL_MODE (0x02) -#define TIMER0_CONTROL_INT_MSK (0x04) - - -volatile uint32_t us_ticker_clrInt = 0; - -static uint32_t us_ticker_inited = 0; -uint32_t us_ticker_soft_int_flag; -static uint32_t us_ticker_timestamp; -static uint32_t us_ticker_interruptCount; - -extern void rda_timer_irq_set(void); - -void us_ticker_init(void) -{ - if (us_ticker_inited) { - return; - } - - /* Enable apb timer clock */ - RDA_SCU->CLKGATE1 |= (0x01UL << 3); - - /* Set timer mode */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_MODE); - - /* Set period mode */ - RDA_GPIO->REVID |= (0x01UL << 25); - - /* Set timer count */ - US_TICKER_TIMER->LDCNT = TIMER0_LDCNT_INIT_VAL; - - /* Enable timer */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_ENABLE); - - /* mask timer, disable an overflow int */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK); - - rda_timer_irq_set(); - - /* Set us_ticker_inited true, after all settings done */ - us_ticker_inited = 1U; - us_ticker_soft_int_flag = 0; - us_ticker_timestamp = 0; - us_ticker_interruptCount = TIMER0_MAX_COUNT; -} - -uint32_t us_ticker_read(void) -{ - if (!us_ticker_inited) { - return 0 ; - } - - uint32_t tick_readout = 0 ; - - core_util_critical_section_enter(); - uint32_t ticker = rTIMER0_CURVAL >> TIMER0_SHIFTBITS ; - - if (us_ticker_interruptCount > ticker) - tick_readout = (us_ticker_timestamp + us_ticker_interruptCount - ticker) % TIMER0_MAX_COUNT ; - else - tick_readout = (us_ticker_timestamp + TIMER0_MAX_COUNT + us_ticker_interruptCount - ticker) % TIMER0_MAX_COUNT ; - core_util_critical_section_exit(); - - return tick_readout; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - if (!us_ticker_inited) { - return ; - } - - uint32_t tmp_stamp = timestamp % TIMER0_MAX_COUNT ; - - core_util_critical_section_enter(); - us_ticker_timestamp = us_ticker_read() ; - us_ticker_interruptCount = (tmp_stamp > us_ticker_timestamp) ? (tmp_stamp - us_ticker_timestamp):(tmp_stamp + TIMER0_MAX_COUNT - us_ticker_timestamp) ; - - /* Disable timer */ - US_TICKER_TIMER->TCTRL &= (~TIMER0_CONTROL_ENABLE); - - US_TICKER_TIMER->LDCNT = us_ticker_interruptCount << TIMER0_SHIFTBITS ; - - /* Enable timer */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_ENABLE); - - /* Unmask timer, enable an overflow int */ - US_TICKER_TIMER->TCTRL &= (~(TIMER0_CONTROL_INT_MSK)); - core_util_critical_section_exit(); - - return ; -} - -void us_ticker_fire_interrupt(void) -{ - if (!us_ticker_inited) { - return ; - } - - core_util_critical_section_enter(); - us_ticker_soft_int_flag = 1 ; - NVIC_SetPendingIRQ(TIMER_IRQn); - core_util_critical_section_exit(); -} - -void us_ticker_disable_interrupt_help(void) -{ - if (!us_ticker_inited) { - return ; - } - - /* Mask timer, disable an overflow int */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK); -} - -void us_ticker_disable_interrupt(void) -{ - if (!us_ticker_inited) { - return ; - } - - core_util_critical_section_enter(); - /* Mask timer, disable an overflow int */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK); - - us_ticker_timestamp = us_ticker_read(); - us_ticker_interruptCount = TIMER0_MAX_COUNT; - - /* Disable timer */ - US_TICKER_TIMER->TCTRL &= (~TIMER0_CONTROL_ENABLE); - - /* Set timer count */ - US_TICKER_TIMER->LDCNT = TIMER0_LDCNT_INIT_VAL; - - /* Enable timer */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_ENABLE); - - /* mask timer, disable an overflow int */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK); - core_util_critical_section_exit(); -} - -void us_ticker_clear_interrupt(void) -{ - if (!us_ticker_inited) { - return ; - } - - us_ticker_clrInt = US_TICKER_TIMER->INTCLR; -} - -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = - { - 5000000, // 5MHZ - 29 // 29 bit counter - }; - return &info; -} - -void us_ticker_free(void) -{ - if (!us_ticker_inited) { - return ; - } - - core_util_critical_section_enter(); - us_ticker_disable_interrupt_help(); - us_ticker_clear_interrupt(); - - /* Disable timer */ - US_TICKER_TIMER->TCTRL &= (~TIMER0_CONTROL_ENABLE); - - us_ticker_inited = 0; - us_ticker_timestamp = 0 ; - us_ticker_interruptCount = 0 ; - core_util_critical_section_exit(); - - return; -} - -void us_ticker_irq_callback() -{ - - us_ticker_clear_interrupt () ; - - if (us_ticker_soft_int_flag == 1) { - us_ticker_soft_int_flag = 0 ; - return ; - } - - core_util_critical_section_enter(); - /* Check the flag firstly, because following hanlder can change it */ - us_ticker_disable_interrupt_help(); - - /* Disable timer */ - US_TICKER_TIMER->TCTRL &= (~TIMER0_CONTROL_ENABLE); - - US_TICKER_TIMER->LDCNT = TIMER0_LDCNT_INIT_VAL ; - - /* Enable timer */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_ENABLE); - - /* mask timer, disable an overflow int */ - US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK); - - core_util_critical_section_exit(); -} diff --git a/targets/TARGET_RDA/mbed_rtx.h b/targets/TARGET_RDA/mbed_rtx.h deleted file mode 100644 index fbb8830f268..00000000000 --- a/targets/TARGET_RDA/mbed_rtx.h +++ /dev/null @@ -1,53 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - -#include - -#ifndef OS_TASKCNT -#define OS_TASKCNT 14 -#endif -#ifndef OS_MAINSTKSIZE -#define OS_MAINSTKSIZE 256 -#endif -#ifndef OS_CLOCK -#define OS_CLOCK 160000000 -#endif - -#if defined(__ARMCC_VERSION) -extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[]; -extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[]; -#define HEAP_START Image$$ARM_LIB_HEAP$$ZI$$Base -#define HEAP_SIZE Image$$ARM_LIB_HEAP$$ZI$$Length -#elif defined(__GNUC__) -/* No region declarations needed */ -#elif defined(__ICCARM__) -/* No region declarations needed */ -#else -#error "no toolchain defined" -#endif - -#if defined(TARGET_UNO_91H) -/* Stack Pointer */ -#ifndef INITIAL_SP -#define INITIAL_SP (0x120000UL) -//#define INITIAL_SP (0x1A8000UL) -#endif -#endif - -#endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h deleted file mode 100644 index 4ee88ce0d30..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h +++ /dev/null @@ -1,111 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART0, - UART1, - UART2, - UART3, - UART4, - UART5, - UART6, - UART7, -} UARTName; - -typedef enum { - PWM_PWM1A = 0, - PWM_PWM1B, - PWM_PWM1C, - PWM_PWM1D, - PWM_PWM1E, - PWM_PWM1F, - PWM_PWM1G, - PWM_PWM1H, - PWM_PWM2A, - PWM_PWM2B, - PWM_PWM2C, - PWM_PWM2D, - PWM_PWM2E, - PWM_PWM2F, - PWM_PWM2G, - PWM_PWM2H, - PWM_TIOC0A = 0x20, - PWM_TIOC0C, - PWM_TIOC1A, - PWM_TIOC1B, - PWM_TIOC2A, - PWM_TIOC2B, - PWM_TIOC3A, - PWM_TIOC3C, - PWM_TIOC4A, - PWM_TIOC4C, -} PWMName; - -typedef enum { - AN0= 0, - AN1= 1, - AN2= 2, - AN3= 3, - AN4= 4, - AN5= 5, - AN6= 6, - AN7= 7, -} ADCName; - -typedef enum { - SPI_0 = 0, - SPI_1, - SPI_2, - SPI_3, - SPI_4, -} SPIName; - -typedef enum { - I2C_0 = 0, - I2C_1, - I2C_2, - I2C_3, -} I2CName; - -typedef enum { - CAN_0 = 0, - CAN_1, - CAN_2, - CAN_3, - CAN_4, -} CANName; - - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART3 - - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c deleted file mode 100644 index d5fd4b1d922..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c +++ /dev/null @@ -1,540 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************IRQ***************/ -enum { - IRQ0,IRQ1, - IRQ2,IRQ3, - IRQ4,IRQ5, - IRQ6,IRQ7, -} IRQNo; -const PinMap PinMap_IRQ[] = { -#ifdef MAX_PERI - {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4}, - {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8}, - {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4}, - {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4}, - {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4}, - {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4}, - {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, - {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8}, - {NC, NC, 0} -#else - {P9_1, IRQ0, 4}, - {P7_8, IRQ1, 8}, - {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, - {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3}, - {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3}, - {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3}, - {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, - {NC, NC, 0} -#endif -}; - -/************PINMAP***************/ -const PinFunc PIPC_0_tbl[] = { -#ifdef MAX_PERI -// pin func pm - {P4_0 , 2 , -1}, /* TIOC0A */ - {P5_0 , 6 , -1}, /* TIOC0A */ - {P7_0 , 7 , -1}, /* TIOC0A */ - {P4_1 , 2 , -1}, /* TIOC0B */ - {P5_1 , 6 , -1}, /* TIOC0B */ - {P7_1 , 7 , -1}, /* TIOC0B */ - {P4_2 , 2 , -1}, /* TIOC0C */ - {P5_5 , 6 , -1}, /* TIOC0C */ - {P7_2 , 7 , -1}, /* TIOC0C */ - {P4_3 , 2 , -1}, /* TIOC0D */ - {P5_7 , 6 , -1}, /* TIOC0D */ - {P7_3 , 7 , -1}, /* TIOC0D */ - {P2_11 , 5 , -1}, /* TIOC1A */ - {P6_0 , 5 , -1}, /* TIOC1A */ - {P7_4 , 7 , -1}, /* TIOC1A */ - {P8_8 , 5 , -1}, /* TIOC1A */ - {P9_7 , 4 , -1}, /* TIOC1A */ - {P2_12 , 8 , -1}, /* TIOC1B */ - {P5_2 , 6 , -1}, /* TIOC1B */ - {P6_1 , 5 , -1}, /* TIOC1B */ - {P7_5 , 7 , -1}, /* TIOC1B */ - {P8_9 , 5 , -1}, /* TIOC1B */ - {P2_1 , 6 , -1}, /* TIOC2A */ - {P6_2 , 6 , -1}, /* TIOC2A */ - {P7_6 , 7 , -1}, /* TIOC2A */ - {P8_14 , 4 , -1}, /* TIOC2A */ - {P2_2 , 6 , -1}, /* TIOC2B */ - {P6_3 , 6 , -1}, /* TIOC2B */ - {P7_7 , 7 , -1}, /* TIOC2B */ - {P8_15 , 4 , -1}, /* TIOC2B */ - {P3_4 , 6 , -1}, /* TIOC3A */ - {P7_8 , 7 , -1}, /* TIOC3A */ - {P8_10 , 4 , -1}, /* TIOC3A */ - {P3_5 , 6 , -1}, /* TIOC3B */ - {P7_9 , 7 , -1}, /* TIOC3B */ - {P8_11 , 4 , -1}, /* TIOC3B */ - {P3_6 , 6 , -1}, /* TIOC3C */ - {P5_3 , 6 , -1}, /* TIOC3C */ - {P7_10 , 7 , -1}, /* TIOC3C */ - {P8_12 , 4 , -1}, /* TIOC3C */ - {P3_7 , 6 , -1}, /* TIOC3D */ - {P5_4 , 6 , -1}, /* TIOC3D */ - {P7_11 , 7 , -1}, /* TIOC3D */ - {P8_13 , 4 , -1}, /* TIOC3D */ - {P3_8 , 6 , -1}, /* TIOC4A */ - {P4_4 , 3 , -1}, /* TIOC4A */ - {P7_12 , 7 , -1}, /* TIOC4A */ - {P3_9 , 6 , -1}, /* TIOC4B */ - {P4_5 , 3 , -1}, /* TIOC4B */ - {P7_13 , 7 , -1}, /* TIOC4B */ - {P3_10 , 6 , -1}, /* TIOC4C */ - {P4_6 , 3 , -1}, /* TIOC4C */ - {P7_14 , 7 , -1}, /* TIOC4C */ - {P3_11 , 6 , -1}, /* TIOC4D */ - {P4_7 , 3 , -1}, /* TIOC4D */ - {P7_15 , 7 , -1}, /* TIOC4D */ - {P5_7 , 1 , 1 }, /* TXOUT0M */ - {P5_6 , 1 , 1 }, /* TXOUT0P */ - {P5_5 , 1 , 1 }, /* TXOUT1M */ - {P5_4 , 1 , 1 }, /* TXOUT1P */ - {P5_3 , 1 , 1 }, /* TXOUT2M */ - {P5_2 , 1 , 1 }, /* TXOUT2P */ - {P5_1 , 1 , 1 }, /* TXCLKOUTM */ - {P5_0 , 1 , 1 }, /* TXCLKOUTP */ - {P2_11 , 4 , 0 }, /* SSITxD0 */ - {P4_7 , 5 , 0 }, /* SSITxD0 */ - {P7_4 , 6 , 0 }, /* SSITxD1 */ - {P4_15 , 6 , 0 }, /* SSITxD3 */ - {P7_11 , 2 , 0 }, /* SSITxD3 */ - {P2_7 , 4 , 0 }, /* SSITxD5 */ - {P4_11 , 5 , 0 }, /* SSITxD5 */ - {P8_10 , 8 , 0 }, /* SSITxD5 */ - {P3_7 , 8 , 0 }, /* WDTOVF */ - {NC , 0 , -1} -#else - // pin func pm - {P4_0 , 2 , -1}, // TIOC0A - {P5_0 , 6 , -1}, // TIOC0A - {P4_2 , 2 , -1}, // TIOC0C - {P5_5 , 6 , -1}, // TIOC0C - // - {P8_14 , 4 , -1}, // TIOC2A - // - {P8_10 , 4 , -1}, // TIOC3A - {P5_3 , 6 , -1}, // TIOC3C - {P8_12 , 4 , -1}, // TIOC3C - // - {P3_8 , 6 , -1}, // TIOC4A - {P4_4 , 3 , -1}, // TIOC4A - {P3_10 , 6 , -1}, // TIOC4C - {P4_6 , 3 , -1}, // TIOC4C - // - {P5_7 , 1 , 1 }, // TXOUT0M - {P5_6 , 1 , 1 }, // TXOUT0P - {P5_5 , 1 , 1 }, // TXOUT1M - {P5_4 , 1 , 1 }, // TXOUT1P - {P5_3 , 1 , 1 }, // TXOUT2M - {P5_2 , 1 , 1 }, // TXOUT2P - {P5_1 , 1 , 1 }, // TXCLKOUTM - {P5_0 , 1 , 1 }, // TXCLKOUTP - {P4_7 , 5 , 0 }, // SSITxD0 - {P8_10 , 8 , 0 }, // SSITxD5 - {P3_7 , 8 , 0 }, // WDTOVF - {NC , 0 , -1} -#endif -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { -#ifdef MAX_PERI - {P1_8, AN0, 1}, - {P1_9, AN1, 1}, - {P1_10, AN2, 1}, - {P1_11, AN3, 1}, - {P1_12, AN4, 1}, - {P1_13, AN5, 1}, - {P1_14, AN6, 1}, - {P1_15, AN7, 1}, - {NC, NC, 0} -#else - {P1_8, AN0, 1}, - {P1_9, AN1, 1}, - {P1_10, AN2, 1}, - {P1_11, AN3, 1}, - {P1_12, AN4, 1}, - {P1_13, AN5, 1}, - {P1_15, AN7, 1}, - {NC, NC, 0} -#endif -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P1_1 , I2C_0, 1}, - {P1_3 , I2C_1, 1}, - {P1_5 , I2C_2, 1}, - {P1_7 , I2C_3, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P1_0 , I2C_0, 1}, - {P1_2 , I2C_1, 1}, - {P1_4 , I2C_2, 1}, - {P1_6 , I2C_3, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { -#ifdef MAX_PERI - {P2_14 , UART0, 6}, - {P4_9 , UART0, 7}, - {P6_9 , UART0, 5}, - {P2_5 , UART1, 6}, - {P4_12 , UART1, 7}, - {P6_12 , UART1, 5}, - {P9_3 , UART1, 4}, - {P3_0 , UART2, 6}, - {P3_1 , UART2, 4}, - {P4_2 , UART2, 5}, - {P4_14 , UART2, 7}, - {P6_3 , UART2, 7}, - {P8_6 , UART2, 7}, - {P3_5 , UART3, 7}, - {P5_3 , UART3, 5}, - {P6_1 , UART3, 7}, - {P8_8 , UART3, 7}, - {P5_0 , UART4, 5}, - {P7_1 , UART4, 4}, - {P8_14 , UART4, 7}, - {P6_6 , UART5, 5}, - {P8_1 , UART5, 4}, - {P8_13 , UART5, 5}, - {P5_6 , UART6, 5}, - {P6_14 , UART6, 4}, - {P7_4 , UART7, 4}, - {NC , NC , 0} -#else - {P3_0 , UART2, 6}, - {P3_1 , UART2, 4}, - {P4_2 , UART2, 5}, - {P5_3 , UART3, 5}, - {P8_8 , UART3, 7}, - {P5_0 , UART4, 5}, - {P8_14 , UART4, 7}, - {P8_13 , UART5, 5}, - {P5_6 , UART6, 5}, - {NC , NC , 0} -#endif -}; - -const PinMap PinMap_UART_RX[] = { -#ifdef MAX_PERI - {P2_15 , UART0, 6}, - {P4_10 , UART0, 7}, - {P6_10 , UART0, 5}, - {P2_6 , UART1, 6}, - {P4_13 , UART1, 7}, - {P6_13 , UART1, 5}, - {P9_4 , UART1, 4}, - {P3_2 , UART2, 4}, - {P4_3 , UART2, 5}, - {P4_15 , UART2, 7}, - {P6_2 , UART2, 7}, - {P8_4 , UART2, 7}, - {P3_6 , UART3, 7}, - {P5_4 , UART3, 5}, - {P6_0 , UART3, 7}, - {P8_9 , UART3, 7}, - {P5_1 , UART4, 5}, - {P7_2 , UART4, 4}, - {P8_15 , UART4, 7}, - {P6_7 , UART5, 5}, - {P8_2 , UART5, 4}, - {P8_11 , UART5, 5}, - {P5_7 , UART6, 5}, - {P6_15 , UART6, 4}, - {P7_5 , UART7, 4}, - {NC , NC , 0} -#else - {P3_2 , UART2, 4}, - {P4_3 , UART2, 5}, - {P5_4 , UART3, 5}, - {P8_9 , UART3, 7}, - {P5_1 , UART4, 5}, - {P8_15 , UART4, 7}, - {P8_11 , UART5, 5}, - {P5_7 , UART6, 5}, - {NC , NC , 0} -#endif -}; - -const PinMap PinMap_UART_CTS[] = { -#ifdef MAX_PERI - {P2_3 , UART1, 6}, - {P9_5 , UART1, 4}, - {P6_3 , UART5, 5}, - {P7_15 , UART5, 4}, - {P7_6 , UART7, 4}, - {NC , NC , 0} -#else - {NC , NC , 0} -#endif -}; - -const PinMap PinMap_UART_RTS[] = { -#ifdef MAX_PERI - {P2_7 , UART1, 6}, - {P9_6 , UART1, 4}, - {P6_4 , UART5, 5}, - {P8_3 , UART5, 4}, - {P7_7 , UART7, 4}, - {NC , NC , 0} -#else - {NC , NC , 0} -#endif -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { -#ifdef MAX_PERI - {P2_12 , SPI_0, 2}, - {P7_15 , SPI_0, 2}, - {P4_4 , SPI_1, 2}, - {P6_4 , SPI_1, 7}, - {P8_3 , SPI_2, 3}, - {P8_14 , SPI_2, 5}, - {P3_0 , SPI_3, 8}, - {P5_0 , SPI_3, 8}, - {P2_8 , SPI_4, 8}, - {P4_0 , SPI_4, 7}, - {NC , NC , 0} -#else - {P4_4 , SPI_1, 2}, - {P8_14 , SPI_2, 5}, - {P5_0 , SPI_3, 8}, - {P4_0 , SPI_4, 7}, - {NC , NC , 0} -#endif -}; - -const PinMap PinMap_SPI_MOSI[] = { -#ifdef MAX_PERI - {P2_14 , SPI_0, 2}, - {P8_1 , SPI_0, 2}, - {P4_6 , SPI_1, 2}, - {P6_6 , SPI_1, 7}, - {P8_5 , SPI_2, 3}, - {P9_0 , SPI_2, 5}, - {P3_2 , SPI_3, 8}, - {P5_2 , SPI_3, 8}, - {P2_10 , SPI_4, 8}, - {P4_2 , SPI_4, 7}, - {NC , NC , 0} -#else - {P4_6 , SPI_1, 2}, - {P9_0 , SPI_2, 5}, - {P5_2 , SPI_3, 8}, - {P4_2 , SPI_4, 7}, - {NC , NC , 0} -#endif -}; - -const PinMap PinMap_SPI_MISO[] = { -#ifdef MAX_PERI - {P2_15 , SPI_0, 2}, - {P8_2 , SPI_0, 2}, - {P4_7 , SPI_1, 2}, - {P6_7 , SPI_1, 7}, - {P8_6 , SPI_2, 3}, - {P9_1 , SPI_2, 5}, - {P3_3 , SPI_3, 8}, - {P5_3 , SPI_3, 8}, - {P2_11 , SPI_4, 8}, - {P4_3 , SPI_4, 7}, - {NC , NC , 0} -#else - {P4_7 , SPI_1, 2}, - {P9_1 , SPI_2, 5}, - {P5_3 , SPI_3, 8}, - {P4_3 , SPI_4, 7}, - {NC , NC , 0} -#endif -}; - -const PinMap PinMap_SPI_SSEL[] = { -#ifdef MAX_PERI - {P2_13 , SPI_0, 2}, - {P8_0 , SPI_0, 2}, - {P4_5 , SPI_1, 2}, - {P6_5 , SPI_1, 7}, - {P8_4 , SPI_2, 3}, - {P8_15 , SPI_2, 5}, - {P3_1 , SPI_3, 8}, - {P5_1 , SPI_3, 8}, - {P2_9 , SPI_4, 8}, - {P4_1 , SPI_4, 7}, - {NC , NC , 0} -#else - {P4_5 , SPI_1, 2}, - {P8_15 , SPI_2, 5}, - {P5_1 , SPI_3, 8}, - {P4_1 , SPI_4, 7}, - {NC , NC , 0} -#endif -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { -#ifdef MAX_PERI - // TIOC0 A,C - {P4_0 , PWM_TIOC0A, 2}, //TIOC0A - {P5_0 , PWM_TIOC0A, 6}, //TIOC0A - {P7_0 , PWM_TIOC0A, 7}, //TIOC0A - {P4_2 , PWM_TIOC0C, 2}, //TIOC0C - {P5_5 , PWM_TIOC0C, 6}, //TIOC0C - {P7_2 , PWM_TIOC0C, 7}, //TIOC0C - //TIOC1 A - {P2_11 , PWM_TIOC1A, 5}, //TIOC1A - {P6_0 , PWM_TIOC1A, 5}, //TIOC1A - {P7_4 , PWM_TIOC1A, 7}, //TIOC1A - {P8_8 , PWM_TIOC1A, 5}, //TIOC1A - {P9_7 , PWM_TIOC1A, 4}, //TIOC1A - //TIOC2 A - {P2_1 , PWM_TIOC2A, 6}, //TIOC2A - {P6_2 , PWM_TIOC2A, 6}, //TIOC2A - {P7_6 , PWM_TIOC2A, 7}, //TIOC2A - {P8_14 , PWM_TIOC2A, 4}, //TIOC2A - //TIOC3 A,C - {P3_4 , PWM_TIOC3A, 6}, //TIOC3A - {P7_8 , PWM_TIOC3A, 7}, //TIOC3A - {P8_10 , PWM_TIOC3A, 4}, //TIOC3A - {P3_6 , PWM_TIOC3C, 6}, //TIOC3C - {P7_10 , PWM_TIOC3C, 7}, //TIOC3C - {P8_12 , PWM_TIOC3C, 4}, //TIOC3C - //TIOC4 A,C - {P3_8 , PWM_TIOC4A, 6}, //TIOC4A - {P4_4 , PWM_TIOC4A, 3}, //TIOC4A - {P7_12 , PWM_TIOC4A, 7}, //TIOC4A - {P3_10 , PWM_TIOC4C, 6}, //TIOC4C - {P4_6 , PWM_TIOC4C, 3}, //TIOC4C - {P7_14 , PWM_TIOC4C, 7}, //TIOC4C - //PWM1 - {P8_8 , PWM_PWM1A , 6}, //PWM1A - {P8_9 , PWM_PWM1B , 6}, //PWM1B - {P8_10 , PWM_PWM1C , 6}, //PWM1C - {P8_11 , PWM_PWM1D , 6}, //PWM1D - {P8_12 , PWM_PWM1E , 6}, //PWM1E - {P8_13 , PWM_PWM1F , 6}, //PWM1F - {P8_14 , PWM_PWM1G , 6}, //PWM1G - {P8_15 , PWM_PWM1H , 6}, //PWM1H - //PWM2 - {P3_0 , PWM_PWM2A , 7}, //PWM2A - {P3_1 , PWM_PWM2B , 7}, //PWM2B - {P3_2 , PWM_PWM2C , 7}, //PWM2C - {P3_3 , PWM_PWM2D , 7}, //PWM2D - {P4_4 , PWM_PWM2E , 4}, //PWM2E - {P4_5 , PWM_PWM2F , 4}, //PWM2F - {P4_6 , PWM_PWM2G , 4}, //PWM2G - {P4_7 , PWM_PWM2H , 4}, //PWM2H - {NC , NC , 0} -#else - //TIOC0 A,C - {P4_0 , PWM_TIOC0A, 2}, //TIOC0A - {P5_0 , PWM_TIOC0A, 6}, //TIOC0A - {P4_2 , PWM_TIOC0C, 2}, //TIOC0C - {P5_5 , PWM_TIOC0C, 6}, //TIOC0C - //TIOC2 A - {P8_14 , PWM_TIOC2A, 4}, //TIOC2A - //TIOC3 A,C - {P8_10 , PWM_TIOC3A, 4}, //TIOC3A - {P5_3 , PWM_TIOC3C, 6}, //TIOC3C - {P8_12 , PWM_TIOC3C, 4}, //TIOC3C - //TIOC4 A,C - {P3_8 , PWM_TIOC4A, 6}, //TIOC4A - {P4_4 , PWM_TIOC4A, 3}, //TIOC4A - {P3_10 , PWM_TIOC4C, 6}, //TIOC4C - {P4_6 , PWM_TIOC4C, 3}, //TIOC4C - //PWM1 - {P8_10 , PWM_PWM1C , 6}, //PWM1C - {P8_11 , PWM_PWM1D , 6}, //PWM1D - {P8_12 , PWM_PWM1E , 6}, //PWM1E - {P8_13 , PWM_PWM1F , 6}, //PWM1F - {P8_14 , PWM_PWM1G , 6}, //PWM1G - {P8_15 , PWM_PWM1H , 6}, //PWM1H - //PWM2 - {P3_0 , PWM_PWM2A , 7}, //PWM2A - {P3_1 , PWM_PWM2B , 7}, //PWM2B - {P3_2 , PWM_PWM2C , 7}, //PWM2C - {P4_4 , PWM_PWM2E , 4}, //PWM2E - {P4_5 , PWM_PWM2F , 4}, //PWM2F - {P4_6 , PWM_PWM2G , 4}, //PWM2G - {P4_7 , PWM_PWM2H , 4}, //PWM2H - {NC , NC , 0} -#endif -}; - -/************CAN***************/ -const PinMap PinMap_CAN_RD[] = { -#ifdef MAX_PERI - {P7_8 , CAN_0, 4}, - {P9_1 , CAN_0, 3}, - {P1_4 , CAN_1, 3}, - {P5_9 , CAN_1, 5}, - {P7_11 , CAN_1, 4}, - {P4_9 , CAN_2, 6}, - {P6_4 , CAN_2, 3}, - {P7_2 , CAN_2, 5}, - {P2_12 , CAN_3, 5}, - {P4_2 , CAN_3, 4}, - {P1_5 , CAN_4, 3}, - {P2_14 , CAN_4, 5}, - {NC , NC , 0} -#else - {P9_1 , CAN_0, 3}, - {P1_4 , CAN_1, 3}, - {P5_9 , CAN_1, 5}, - {P4_2 , CAN_3, 4}, - {P1_5 , CAN_4, 3}, - {NC , NC , 0} -#endif -}; - -const PinMap PinMap_CAN_TD[] = { -#ifdef MAX_PERI - {P7_9 , CAN_0, 4}, - {P9_0 , CAN_0, 3}, - {P5_10 , CAN_1, 5}, - {P7_10 , CAN_1, 4}, - {P4_8 , CAN_2, 6}, - {P6_5 , CAN_2, 3}, - {P7_3 , CAN_2, 5}, - {P2_13 , CAN_3, 5}, - {P4_3 , CAN_3, 4}, - {P4_11 , CAN_4, 6}, - {P8_10 , CAN_4, 5}, - {NC , NC , 0} -#else - {P9_0 , CAN_0, 3}, - {P5_10 , CAN_1, 5}, - {P4_3 , CAN_3, 4}, - {P8_10 , CAN_4, 5}, - {NC , NC , 0} -#endif -}; - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PinNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PinNames.h deleted file mode 100644 index 51516e1ed34..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PinNames.h +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 4 - -typedef enum { - P0_0 = 0, P0_1, P0_2, P0_3, P0_4, P0_5, - P1_0 = 16, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, - P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, - P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, - P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, - P5_0, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, - P6_0 = 96, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15, - P7_0, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15, - P8_0, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15, - P9_0, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7, - - // mbed Pin Names - LED1 = P7_1, - LED_RED = LED1, - // mbed led alias to keep some test happy, becasue physically they are no LED2,LED3 & LED4 on the board - LED2 = LED1, - LED3 = LED2, - LED4 = LED3, - - I2C_SCL = P1_0, - I2C_SDA = P1_1, - - USBTX = P8_8, - USBRX = P8_9, - - //USER_BUTTON0 = P6_0, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullUp = 0, - PullDown = 3, - PullNone = 2, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f) -#define PINNO(pin) ((pin)&0x0f) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PortNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PortNames.h deleted file mode 100644 index 4dd6a4cae04..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PortNames.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, - Port1 = 1, - Port3 = 3, - Port4 = 4, - Port5 = 5, - Port7 = 7, - Port8 = 8, - Port9 = 9 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h deleted file mode 100644 index 201e6fb008a..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h +++ /dev/null @@ -1,22 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef RESERVED_PINS_H -#define RESERVED_PINS_H - -#define TARGET_RESERVED_PINS {} - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h deleted file mode 100644 index 20024dad869..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h +++ /dev/null @@ -1,37 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -/* ->Take measures about optimization problems of web compiler */ - /* Web compiler has problem that inlining code may not be generated correctly */ - /* when "-O3 -Otime" was specified. */ -#if defined(__CC_ARM) && (__ARMCC_VERSION <= 5040027) -#pragma Ospace -#endif -/* <-Take measures about optimization problems of web compiler */ - -#define TRANSACTION_QUEUE_SIZE_SPI 16 - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#include "objects.h" -#include "dma_api.h" - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c deleted file mode 100644 index ff7b5d66e23..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c +++ /dev/null @@ -1,704 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** -* @file RZ_A1_Init.c -* $Rev: 624 $ -* $Date:: 2013-04-24 13:37:48 +0900#$ -* @brief RZ_A1 Initialize -******************************************************************************/ - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#include "VKRZA1H.h" -#include "RZ_A1_Init.h" -#include "rza_io_regrw.h" -#include "gpio_iobitmask.h" - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - -/****************************************************************************** -Macro definitions -******************************************************************************/ -#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040) -#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040) - -#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) - -#if (defined(TARGET_DEBUG) || !defined(RUN_FROM_SDRAM)) -#define CS2_SDRAM -#endif - -/****************************************************************************** -Imported global variables and functions (from other files) -******************************************************************************/ - -/****************************************************************************** -Exported global variables and functions (to be accessed by other files) -******************************************************************************/ - -/****************************************************************************** -Private global variables and functions -******************************************************************************/ - -static void PORT_Init(void) -{ - /* ==== BSC settings ==== */ - - /* ---- P7_2 : RAS# ---- */ - /* Port initialize */ - RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC72_SHIFT, GPIO_PIBC7_PIBC72); - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC72_SHIFT, GPIO_PBDC7_PBDC72); - RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM72_SHIFT, GPIO_PM7_PM72); - RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC72_SHIFT, GPIO_PMC7_PMC72); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC72_SHIFT, GPIO_PIPC7_PIPC72); - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - /* Bidirectional mode : Disable */ - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC72_SHIFT, GPIO_PBDC7_PBDC72); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC72_SHIFT, GPIO_PFC7_PFC72); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE72_SHIFT, GPIO_PFCE7_PFCE72); - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE72_SHIFT, GPIO_PFCAE7_PFCAE72); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC72_SHIFT, GPIO_PIPC7_PIPC72); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC72_SHIFT, GPIO_PMC7_PMC72); - - /* ---- P7_3 : CAS# ---- */ - /* Port initialize */ - RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC73_SHIFT, GPIO_PIBC7_PIBC73); - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC73_SHIFT, GPIO_PBDC7_PBDC73); - RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM73_SHIFT, GPIO_PM7_PM73); - RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC73_SHIFT, GPIO_PMC7_PMC73); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC73_SHIFT, GPIO_PIPC7_PIPC73); - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - /* Bidirectional mode : Disable */ - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC73_SHIFT, GPIO_PBDC7_PBDC73); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC73_SHIFT, GPIO_PFC7_PFC73); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE73_SHIFT, GPIO_PFCE7_PFCE73); - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE73_SHIFT, GPIO_PFCAE7_PFCAE73); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC73_SHIFT, GPIO_PIPC7_PIPC73); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC73_SHIFT, GPIO_PMC7_PMC73); - - /* ---- P7_4 : CKE ---- */ - /* Port initialize */ - RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC74_SHIFT, GPIO_PIBC7_PIBC74); - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC74_SHIFT, GPIO_PBDC7_PBDC74); - RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM74_SHIFT, GPIO_PM7_PM74); - RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC74_SHIFT, GPIO_PMC7_PMC74); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC74_SHIFT, GPIO_PIPC7_PIPC74); - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - /* Bidirectional mode : Disable */ - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC74_SHIFT, GPIO_PBDC7_PBDC74); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC74_SHIFT, GPIO_PFC7_PFC74); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE74_SHIFT, GPIO_PFCE7_PFCE74); - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE74_SHIFT, GPIO_PFCAE7_PFCAE74); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC74_SHIFT, GPIO_PIPC7_PIPC74); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC74_SHIFT, GPIO_PMC7_PMC74); - - /* ---- P7_5 : RD/WR# ---- */ - /* Port initialize */ - RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC75_SHIFT, GPIO_PIBC7_PIBC75); - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC75_SHIFT, GPIO_PBDC7_PBDC75); - RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM75_SHIFT, GPIO_PM7_PM75); - RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC75_SHIFT, GPIO_PMC7_PMC75); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC75_SHIFT, GPIO_PIPC7_PIPC75); - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - /* Bidirectional mode : Disable */ - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC75_SHIFT, GPIO_PBDC7_PBDC75); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC75_SHIFT, GPIO_PFC7_PFC75); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE75_SHIFT, GPIO_PFCE7_PFCE75); - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE75_SHIFT, GPIO_PFCAE7_PFCAE75); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC75_SHIFT, GPIO_PIPC7_PIPC75); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC75_SHIFT, GPIO_PMC7_PMC75); - - /* ---- P7_6 : DQMLL ---- */ - /* Port initialize */ - RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC76_SHIFT, GPIO_PIBC7_PIBC76); - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC76_SHIFT, GPIO_PBDC7_PBDC76); - RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM76_SHIFT, GPIO_PM7_PM76); - RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC76_SHIFT, GPIO_PMC7_PMC76); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC76_SHIFT, GPIO_PIPC7_PIPC76); - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - /* Bidirectional mode : Disable */ - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC76_SHIFT, GPIO_PBDC7_PBDC76); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC76_SHIFT, GPIO_PFC7_PFC76); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE76_SHIFT, GPIO_PFCE7_PFCE76); - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE76_SHIFT, GPIO_PFCAE7_PFCAE76); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC76_SHIFT, GPIO_PIPC7_PIPC76); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC76_SHIFT, GPIO_PMC7_PMC76); - - /* ---- P7_7 : DQMLU ---- */ - /* Port initialize */ - RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC77_SHIFT, GPIO_PIBC7_PIBC77); - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC77_SHIFT, GPIO_PBDC7_PBDC77); - RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM77_SHIFT, GPIO_PM7_PM77); - RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC77_SHIFT, GPIO_PMC7_PMC77); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC77_SHIFT, GPIO_PIPC7_PIPC77); - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - /* Bidirectional mode : Disable */ - RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC77_SHIFT, GPIO_PBDC7_PBDC77); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC77_SHIFT, GPIO_PFC7_PFC77); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE77_SHIFT, GPIO_PFCE7_PFCE77); - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE77_SHIFT, GPIO_PFCAE7_PFCAE77); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC77_SHIFT, GPIO_PIPC7_PIPC77); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC77_SHIFT, GPIO_PMC7_PMC77); - - /* ---- P5_8 : CS2# ---- */ - /* Port initialize */ - RZA_IO_RegWrite_16(&GPIO.PIBC5, 0, GPIO_PIBC5_PIBC58_SHIFT, GPIO_PIBC5_PIBC58); - RZA_IO_RegWrite_16(&GPIO.PBDC5, 0, GPIO_PBDC5_PBDC58_SHIFT, GPIO_PBDC5_PBDC58); - RZA_IO_RegWrite_16(&GPIO.PM5, 1, GPIO_PM5_PM58_SHIFT, GPIO_PM5_PM58); - RZA_IO_RegWrite_16(&GPIO.PMC5, 0, GPIO_PMC5_PMC58_SHIFT, GPIO_PMC5_PMC58); - RZA_IO_RegWrite_16(&GPIO.PIPC5, 0, GPIO_PIPC5_PIPC58_SHIFT, GPIO_PIPC5_PIPC58); - /* Port mode : Multiplex mode */ - /* Port function setting : 6th multiplex function */ - /* I/O control mode : Peripheral function */ - /* Bidirectional mode : Disable */ - RZA_IO_RegWrite_16(&GPIO.PBDC5, 0, GPIO_PBDC5_PBDC58_SHIFT, GPIO_PBDC5_PBDC58); - RZA_IO_RegWrite_16(&GPIO.PFC5, 1, GPIO_PFC5_PFC58_SHIFT, GPIO_PFC5_PFC58); - RZA_IO_RegWrite_16(&GPIO.PFCE5, 0, GPIO_PFCE5_PFCE58_SHIFT, GPIO_PFCE5_PFCE58); - RZA_IO_RegWrite_16(&GPIO.PFCAE5, 1, GPIO_PFCAE5_PFCAE58_SHIFT, GPIO_PFCAE5_PFCAE58); - RZA_IO_RegWrite_16(&GPIO.PIPC5, 1, GPIO_PIPC5_PIPC58_SHIFT, GPIO_PIPC5_PIPC58); - RZA_IO_RegWrite_16(&GPIO.PMC5, 1, GPIO_PMC5_PMC58_SHIFT, GPIO_PMC5_PMC58); - - /* ---- P7_1 : CS3# ---- */ - /* Port initialize */ -// RZA1_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC71_SHIFT, GPIO_PIBC7_PIBC71); -// RZA1_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC71_SHIFT, GPIO_PBDC7_PBDC71); -// RZA1_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM71_SHIFT, GPIO_PM7_PM71); -// RZA1_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC71_SHIFT, GPIO_PMC7_PMC71); -// RZA1_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC71_SHIFT, GPIO_PIPC7_PIPC71); -// /* Port mode : Multiplex mode */ -// /* Port function setting : 1st multiplex function */ -// /* I/O control mode : Peripheral function */ -// /* Bidirectional mode : Disable */ -// RZA1_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC71_SHIFT, GPIO_PBDC7_PBDC71); -// RZA1_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC71_SHIFT, GPIO_PFC7_PFC71); -// RZA1_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE71_SHIFT, GPIO_PFCE7_PFCE71); -// RZA1_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE71_SHIFT, GPIO_PFCAE7_PFCAE71); -// RZA1_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC71_SHIFT, GPIO_PIPC7_PIPC71); -// RZA1_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC71_SHIFT, GPIO_PMC7_PMC71); -} - -/****************************************************************************** -* Function Name: CS2_PORTInit -* Description : Sets the PORT multiplexed pin to use the CS2 and the CS3 -* : spaces. In this sample code, the PORT setting is executed to -* : use the NOR flash memory in the CS0 and the CS1 spaces. -* Arguments : none -* Return Value : none -******************************************************************************/ -static void CS2_PORTInit(void) -{ - /* ---- P6_0 : D0 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE60_SHIFT, GPIO_PFCAE6_PFCAE60); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE60_SHIFT, GPIO_PFCE6_PFCE60); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC60_SHIFT, GPIO_PFC6_PFC60); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC60_SHIFT, GPIO_PMC6_PMC60); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC60_SHIFT, GPIO_PIPC6_PIPC60); - - /* ---- P6_1 : D1 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE61_SHIFT, GPIO_PFCAE6_PFCAE61); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE61_SHIFT, GPIO_PFCE6_PFCE61); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC61_SHIFT, GPIO_PFC6_PFC61); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC61_SHIFT, GPIO_PMC6_PMC61); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC61_SHIFT, GPIO_PIPC6_PIPC61); - - /* ---- P6_2 : D2 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE62_SHIFT, GPIO_PFCAE6_PFCAE62); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE62_SHIFT, GPIO_PFCE6_PFCE62); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC62_SHIFT, GPIO_PFC6_PFC62); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC62_SHIFT, GPIO_PMC6_PMC62); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC62_SHIFT, GPIO_PIPC6_PIPC62); - - /* ---- P6_3 : D3 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE63_SHIFT, GPIO_PFCAE6_PFCAE63); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE63_SHIFT, GPIO_PFCE6_PFCE63); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC63_SHIFT, GPIO_PFC6_PFC63); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC63_SHIFT, GPIO_PMC6_PMC63); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC63_SHIFT, GPIO_PIPC6_PIPC63); - - /* ---- P6_4 : D4 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE64_SHIFT, GPIO_PFCAE6_PFCAE64); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE64_SHIFT, GPIO_PFCE6_PFCE64); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC64_SHIFT, GPIO_PFC6_PFC64); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC64_SHIFT, GPIO_PMC6_PMC64); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC64_SHIFT, GPIO_PIPC6_PIPC64); - - /* ---- P6_5 : D5 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE65_SHIFT, GPIO_PFCAE6_PFCAE65); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE65_SHIFT, GPIO_PFCE6_PFCE65); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC65_SHIFT, GPIO_PFC6_PFC65); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC65_SHIFT, GPIO_PMC6_PMC65); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC65_SHIFT, GPIO_PIPC6_PIPC65); - - /* ---- P6_6 : D6 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE66_SHIFT, GPIO_PFCAE6_PFCAE66); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE66_SHIFT, GPIO_PFCE6_PFCE66); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC66_SHIFT, GPIO_PFC6_PFC66); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC66_SHIFT, GPIO_PMC6_PMC66); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC66_SHIFT, GPIO_PIPC6_PIPC66); - - /* ---- P6_7 : D7 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE67_SHIFT, GPIO_PFCAE6_PFCAE67); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE67_SHIFT, GPIO_PFCE6_PFCE67); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC67_SHIFT, GPIO_PFC6_PFC67); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC67_SHIFT, GPIO_PMC6_PMC67); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC67_SHIFT, GPIO_PIPC6_PIPC67); - - /* ---- P6_8 : D8 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE68_SHIFT, GPIO_PFCAE6_PFCAE68); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE68_SHIFT, GPIO_PFCE6_PFCE68); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC68_SHIFT, GPIO_PFC6_PFC68); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC68_SHIFT, GPIO_PMC6_PMC68); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC68_SHIFT, GPIO_PIPC6_PIPC68); - - /* ---- P6_9 : D9 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE69_SHIFT, GPIO_PFCAE6_PFCAE69); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE69_SHIFT, GPIO_PFCE6_PFCE69); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC69_SHIFT, GPIO_PFC6_PFC69); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC69_SHIFT, GPIO_PMC6_PMC69); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC69_SHIFT, GPIO_PIPC6_PIPC69); - - /* ---- P6_10 : D10 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE610_SHIFT, GPIO_PFCAE6_PFCAE610); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE610_SHIFT, GPIO_PFCE6_PFCE610); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC610_SHIFT, GPIO_PFC6_PFC610); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC610_SHIFT, GPIO_PMC6_PMC610); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC610_SHIFT, GPIO_PIPC6_PIPC610); - - /* ---- P6_11 : D11 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE611_SHIFT, GPIO_PFCAE6_PFCAE611); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE611_SHIFT, GPIO_PFCE6_PFCE611); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC611_SHIFT, GPIO_PFC6_PFC611); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC611_SHIFT, GPIO_PMC6_PMC611); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC611_SHIFT, GPIO_PIPC6_PIPC611); - - /* ---- P6_12 : D12 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE612_SHIFT, GPIO_PFCAE6_PFCAE612); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE612_SHIFT, GPIO_PFCE6_PFCE612); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC612_SHIFT, GPIO_PFC6_PFC612); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC612_SHIFT, GPIO_PMC6_PMC612); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC612_SHIFT, GPIO_PIPC6_PIPC612); - - /* ---- P6_13 : D13 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE613_SHIFT, GPIO_PFCAE6_PFCAE613); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE613_SHIFT, GPIO_PFCE6_PFCE613); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC613_SHIFT, GPIO_PFC6_PFC613); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC613_SHIFT, GPIO_PMC6_PMC613); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC613_SHIFT, GPIO_PIPC6_PIPC613); - - /* ---- P6_14 : D14 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE614_SHIFT, GPIO_PFCAE6_PFCAE614); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE614_SHIFT, GPIO_PFCE6_PFCE614); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC614_SHIFT, GPIO_PFC6_PFC614); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC614_SHIFT, GPIO_PMC6_PMC614); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC614_SHIFT, GPIO_PIPC6_PIPC614); - - /* ---- P6_15 : D15 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE615_SHIFT, GPIO_PFCAE6_PFCAE615); - RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE615_SHIFT, GPIO_PFCE6_PFCE615); - RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC615_SHIFT, GPIO_PFC6_PFC615); - RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC615_SHIFT, GPIO_PMC6_PMC615); - RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC615_SHIFT, GPIO_PIPC6_PIPC615); - - /* ---- P7_9 : A1 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE79_SHIFT, GPIO_PFCAE7_PFCAE79); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE79_SHIFT, GPIO_PFCE7_PFCE79); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC79_SHIFT, GPIO_PFC7_PFC79); - RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM79_SHIFT, GPIO_PM7_PM79); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC79_SHIFT, GPIO_PMC7_PMC79); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC79_SHIFT, GPIO_PIPC7_PIPC79); - - /* ---- P7_10 : A2 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE710_SHIFT, GPIO_PFCAE7_PFCAE710); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE710_SHIFT, GPIO_PFCE7_PFCE710); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC710_SHIFT, GPIO_PFC7_PFC710); - RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM710_SHIFT, GPIO_PM7_PM710); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC710_SHIFT, GPIO_PMC7_PMC710); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC710_SHIFT, GPIO_PIPC7_PIPC710); - - /* ---- P7_11 : A3 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE711_SHIFT, GPIO_PFCAE7_PFCAE711); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE711_SHIFT, GPIO_PFCE7_PFCE711); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC711_SHIFT, GPIO_PFC7_PFC711); - RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM711_SHIFT, GPIO_PM7_PM711); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC711_SHIFT, GPIO_PMC7_PMC711); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC711_SHIFT, GPIO_PIPC7_PIPC711); - - /* ---- P7_12 : A4 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE712_SHIFT, GPIO_PFCAE7_PFCAE712); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE712_SHIFT, GPIO_PFCE7_PFCE712); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC712_SHIFT, GPIO_PFC7_PFC712); - RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM712_SHIFT, GPIO_PM7_PM712); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC712_SHIFT, GPIO_PMC7_PMC712); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC712_SHIFT, GPIO_PIPC7_PIPC712); - - /* ---- P7_13 : A5 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE713_SHIFT, GPIO_PFCAE7_PFCAE713); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE713_SHIFT, GPIO_PFCE7_PFCE713); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC713_SHIFT, GPIO_PFC7_PFC713); - RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM713_SHIFT, GPIO_PM7_PM713); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC713_SHIFT, GPIO_PMC7_PMC713); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC713_SHIFT, GPIO_PIPC7_PIPC713); - - /* ---- P7_14 : A6 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE714_SHIFT, GPIO_PFCAE7_PFCAE714); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE714_SHIFT, GPIO_PFCE7_PFCE714); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC714_SHIFT, GPIO_PFC7_PFC714); - RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM714_SHIFT, GPIO_PM7_PM714); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC714_SHIFT, GPIO_PMC7_PMC714); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC714_SHIFT, GPIO_PIPC7_PIPC714); - - /* ---- P7_15 : A7 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE715_SHIFT, GPIO_PFCAE7_PFCAE715); - RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE715_SHIFT, GPIO_PFCE7_PFCE715); - RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC715_SHIFT, GPIO_PFC7_PFC715); - RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM715_SHIFT, GPIO_PM7_PM715); - RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC715_SHIFT, GPIO_PMC7_PMC715); - RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC715_SHIFT, GPIO_PIPC7_PIPC715); - - /* ---- P8_0 : A8 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE80_SHIFT, GPIO_PFCAE8_PFCAE80); - RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE80_SHIFT, GPIO_PFCE8_PFCE80); - RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC80_SHIFT, GPIO_PFC8_PFC80); - RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC80_SHIFT, GPIO_PMC8_PMC80); - RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC80_SHIFT, GPIO_PIPC8_PIPC80); - - /* ---- P8_1 : A9 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE81_SHIFT, GPIO_PFCAE8_PFCAE81); - RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE81_SHIFT, GPIO_PFCE8_PFCE81); - RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC81_SHIFT, GPIO_PFC8_PFC81); - RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM81_SHIFT, GPIO_PM8_PM81); - RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC81_SHIFT, GPIO_PMC8_PMC81); - RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC81_SHIFT, GPIO_PIPC8_PIPC81); - - /* ---- P8_2 : A10 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE82_SHIFT, GPIO_PFCAE8_PFCAE82); - RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE82_SHIFT, GPIO_PFCE8_PFCE82); - RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC82_SHIFT, GPIO_PFC8_PFC82); - RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM82_SHIFT, GPIO_PM8_PM82); - RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC82_SHIFT, GPIO_PMC8_PMC82); - RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC82_SHIFT, GPIO_PIPC8_PIPC82); - - /* ---- P8_3 : A11 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE83_SHIFT, GPIO_PFCAE8_PFCAE83); - RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE83_SHIFT, GPIO_PFCE8_PFCE83); - RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC83_SHIFT, GPIO_PFC8_PFC83); - RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM83_SHIFT, GPIO_PM8_PM83); - RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC83_SHIFT, GPIO_PMC8_PMC83); - RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC83_SHIFT, GPIO_PIPC8_PIPC83); - - /* ---- P8_4 : A12 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE84_SHIFT, GPIO_PFCAE8_PFCAE84); - RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE84_SHIFT, GPIO_PFCE8_PFCE84); - RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC84_SHIFT, GPIO_PFC8_PFC84); - RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM84_SHIFT, GPIO_PM8_PM84); - RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC84_SHIFT, GPIO_PMC8_PMC84); - RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC84_SHIFT, GPIO_PIPC8_PIPC84); - - /* ---- P8_5 : A13 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE85_SHIFT, GPIO_PFCAE8_PFCAE85); - RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE85_SHIFT, GPIO_PFCE8_PFCE85); - RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC85_SHIFT, GPIO_PFC8_PFC85); - RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM85_SHIFT, GPIO_PM8_PM85); - RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC85_SHIFT, GPIO_PMC8_PMC85); - RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC85_SHIFT, GPIO_PIPC8_PIPC85); - - /* ---- P8_6 : A14 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE86_SHIFT, GPIO_PFCAE8_PFCAE86); - RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE86_SHIFT, GPIO_PFCE8_PFCE86); - RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC86_SHIFT, GPIO_PFC8_PFC86); - RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM86_SHIFT, GPIO_PM8_PM86); - RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC86_SHIFT, GPIO_PMC8_PMC86); - RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC86_SHIFT, GPIO_PIPC8_PIPC86); - - /* ---- P8_7 : A15 ---- */ - /* Port mode : Multiplex mode */ - /* Port function setting : 1st multiplex function */ - /* I/O control mode : Peripheral function */ - RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE87_SHIFT, GPIO_PFCAE8_PFCAE87); - RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE87_SHIFT, GPIO_PFCE8_PFCE87); - RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC87_SHIFT, GPIO_PFC8_PFC87); - RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM87_SHIFT, GPIO_PM8_PM87); - RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC87_SHIFT, GPIO_PMC8_PMC87); - RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC87_SHIFT, GPIO_PIPC8_PIPC87); -} - - -/****************************************************************************** -* Function Name: Userdef_BSC_CS2Init -* Description : This is the user-defined function called by the R_BSC_Init -* : function. The setting for initialization of the BSC in the CS2 -* : space is required. In this sample code, the setting to use -* : the SDRAM in the CS2 space is executed. Sets the BSC to -* : connect the ISSI IS42S16320B-75 to the CS2 space with 16-bit -* : bus width. -* Arguments : none -* Return Value : none -******************************************************************************/ -static void CS2_BSC_Init(void) -{ - /* ==== CS2BCR settings ==== */ - /* Idle Cycles between Write-read Cycles */ - /* and Write-write Cycles : 0 idle cycles */ - /* Memory type :SDRAM */ - /* Data Bus Size : 16-bit */ - BSC.CS2BCR = 0x00004C00ul; - - /* ==== CS3BCR settings ==== */ - /* SDRAM WORKAROUND - see Note */ - /* Idle Cycles between Write-read Cycles */ - /* and Write-write Cycles : 0 idle cycles */ - /* Memory type :SDRAM */ - /* Data Bus Size : 16-bit */ - BSC.CS3BCR = 0x00004C00ul; - - /* ==== CS2/3WCR settings ==== */ - /* Precharge completion wait cycles: 1 cycle */ - /* Wait cycles between ACTV command */ - /* and READ(A)/WRITE(A) command : 1 cycles */ - /* CAS latency for Area 3 : 2 cycles */ - /* Auto-precharge startup wait cycles : 2 cycles */ - /* Idle cycles from REF command/self-refresh */ - /* Release to ACTV/REF/MRS command : 5 cycles */ - BSC.CS3WCR = 0x00002492ul; - - /* SDRAM WORKAROUND - see Note */ - BSC.CS2WCR = 0x00000480ul; - - /* ==== SDCR settings ==== */ - /* SDRAM WORKAROUND - see Note*/ - /* Row address for Area 2 : 13-bit */ - /* Column Address for Area 2 : 9-bit */ - /* Refresh Control :Refresh */ - /* RMODE :Auto-refresh is performed */ - /* BACTV :Auto-precharge mode */ - /* Row address for Area 3 : 13-bit */ - /* Column Address for Area 3 : 9-bit */ - BSC.SDCR = 0x00110811ul; - - /* ==== RTCOR settings ==== */ - /* 7.8usec / 60nsec */ - /* = 32(0x40)cycles per refresh */ - BSC.RTCOR = 0xA55A0020ul; - - /* ==== RTCSR settings ==== */ - /* initialisation sequence start */ - /* Clock select B-phy/16 */ - /* Refresh count :Once */ - BSC.RTCSR = 0xA55A0010ul; - - - /* ==== SDRAM Mode Register ==== */ - /* Burst read (burst length 1)./Burst write */ - CS2_SDRAM_MODE_16BIT_CAS2_BR_BW = 0; - - /* SDRAM WORKAROUND - see Note */ - CS3_SDRAM_MODE_16BIT_CAS2_BR_BW = 0; - -} - -/**************************************************************************//** -* Function Name: RZ_A1_SetSramWriteEnable -* @brief Initialize Board settings -* -* Description:
-* Set SRAM write enable -* @param none -* @retval none -******************************************************************************/ -void RZ_A1_SetSramWriteEnable(void) -{ - /* Enable SRAM write access */ - CPG.SYSCR3 = 0x0F; - - return; -} - -/**************************************************************************//** -* Function Name: RZ_A1_InitClock -* @brief Initialize Board settings -* -* Description:
-* Initialize Clock -* @param none -* @retval none -******************************************************************************/ -void RZ_A1_InitClock(void) -{ - /* Cancel L2C standby status before clock change */ - L2CREG15_POWER_CTRL = 0x00000001; - - /* Clock settings */ - /* ClockMode0 */ - CPG.FRQCR = 0x1035; /* CPU Clock =399.99MHz */ - CPG.FRQCR2 = 0x0001; /* G Clock =266.66MHz */ - - return; -} - -/**************************************************************************//** -* Function Name: RZ_A1_IsClockMode0 -* @brief Query Clock Mode -* -* Description:
-* Answer ClockMode0 or not -* @param none -* @retval true : clock mode 0 -* @retval false : clock mode 1 -******************************************************************************/ -int RZ_A1_IsClockMode0(void) -{ - /* ClockMode0 */ - return true; -} - -/**************************************************************************//** -* Function Name: RZ_A1_InitBus -* @brief Initialize Bus -* -* Description:
-* Initialize Pin Setting -* @param none -* @retval none -******************************************************************************/ -void RZ_A1_InitBus(void) -{ - /*************************************************************************/ - /* If need Pin Setting before run program, the setting will be wrote here*/ - /*************************************************************************/ -#if defined(CS2_SDRAM) - PORT_Init(); - CS2_PORTInit(); - CS2_BSC_Init(); -#else - return; -#endif -} - -/****************************************************************************** -End of file -******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct deleted file mode 100644 index 59dc0175698..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct +++ /dev/null @@ -1,100 +0,0 @@ -#! armcc -E -I"../" -;************************************************** -; Copyright (c) 2017 ARM Ltd. All rights reserved. -;************************************************** - -; Scatter-file for RTX Example on Versatile Express - -; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. - -#include "mbed_config.h" - -#ifdef RUN_FROM_SDRAM - #define __ROM_BASE 0x08000000 - #define __ROM_SIZE 0x02000000 - #define __VECTOR_BASE 0x08000000 - #define __DATA_BASE +0 ALIGN 0x100000 -#elif defined (RUN_FROM_SRAM) - #define __ROM_BASE 0x200A0000 - #define __ROM_SIZE 0x00960000 - #define __VECTOR_BASE 0x200A0000 - #define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS -#else - #define __ROM_BASE 0x18020000 - #define __ROM_SIZE 0x01FE0000 - #define __VECTOR_BASE 0x18020000 - #define __DATA_BASE 0x20020000 -#endif - -#ifdef RUN_FROM_SDRAM -#define __RAM_BASE 0x08000000 -#define __RAM_SIZE 0x02000000 -#define __NC_RAM_SIZE 0x00200000 -#else -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00A00000 -#define __NC_RAM_SIZE 0x00100000 -#endif -#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE) -#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000) - -#define __UND_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00008000 -#define __ABT_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x0000F000 -#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) - -#define __TTB_BASE 0x20000000 -#define __TTB_SIZE 0x00004000 - -LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM -{ - TTB +0 EMPTY 0x4000 - { } ; Level-1 Translation Table for MMU -} - -LR_IROM1 __ROM_BASE __ROM_SIZE ; load region size_region -{ - VECTORS __VECTOR_BASE FIXED - { - * (RESET, +FIRST) ; Vector table and other startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - } - - RO_DATA +0 - { * (+RO-DATA) } ; Application RO data (.constdata) - - RW_DATA __DATA_BASE - { * (+RW) } ; Application RW data (.data) - - RW_IRAM1 +0 ALIGN 0x10 - { * (+ZI) } ; Application ZI data (.bss) - - ARM_LIB_HEAP +0 - { * (HEAP) } ; Application heap area (HEAP) - - ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down - { } - - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; RAM-NC : Internal non-cached RAM region - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE - { * (NC_DATA) } ; Application RW data Non cached area - - ZI_DATA_NC +0 - { * (NC_BSS) } ; Application ZI data Non cached area -} - -#ifndef RUN_FROM_SDRAM -SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region -{ -} -#else -SRAM 0x200A0000 0x00960000 ; 9.5MB Internal SRAM region (0.5MB SDCARD Bootloader !!!) -{ -} -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S deleted file mode 100644 index b12d54d7255..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S +++ /dev/null @@ -1,151 +0,0 @@ -;/****************************************************************************** -; * @file startup_RZ_A1H.S -; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series -; * -; * @note -; * -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2017 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -__UND_STACK_SIZE EQU 0x00000100 -__SVC_STACK_SIZE EQU 0x00008000 -__ABT_STACK_SIZE EQU 0x00000100 -__FIQ_STACK_SIZE EQU 0x00000100 -__IRQ_STACK_SIZE EQU 0x0000F000 - -USR_MODE EQU 0x10 ; User mode -FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode -IRQ_MODE EQU 0x12 ; Interrupt Request mode -SVC_MODE EQU 0x13 ; Supervisor mode -ABT_MODE EQU 0x17 ; Abort mode -UND_MODE EQU 0x1B ; Undefined Instruction mode -SYS_MODE EQU 0x1F ; System mode - - - PRESERVE8 - ARM - - AREA RESET, CODE, READONLY - -Vectors PROC - EXPORT Vectors - IMPORT Undef_Handler - IMPORT SVC_Handler - IMPORT PAbt_Handler - IMPORT DAbt_Handler - IMPORT IRQ_Handler - IMPORT FIQ_Handler - - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler - - ENDP - - - - AREA |.text|, CODE, READONLY - -Reset_Handler PROC - EXPORT Reset_Handler - IMPORT SystemInit - IMPORT __main - - - ; Mask interrupts - CPSID if - - ; Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - - ; Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register - ISB - - ; Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register - - ; Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - ; Setup Stack for each exceptional mode - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - - ;Enter Undefined Instruction Mode and set its Stack Pointer - CPS #UND_MODE - MOV SP, R0 - SUB R0, R0, #__UND_STACK_SIZE - - ; Enter Abort Mode and set its Stack Pointer - CPS #ABT_MODE - MOV SP, R0 - SUB R0, R0, #__ABT_STACK_SIZE - - ; Enter FIQ Mode and set its Stack Pointer - CPS #FIQ_MODE - MOV SP, R0 - SUB R0, R0, #__FIQ_STACK_SIZE - - ; Enter IRQ Mode and set its Stack Pointer - CPS #IRQ_MODE - MOV SP, R0 - SUB R0, R0, #__IRQ_STACK_SIZE - - ; Enter Supervisor Mode and set its Stack Pointer - CPS #SVC_MODE - MOV SP, R0 - SUB R0, R0, #__SVC_STACK_SIZE - - ; Enter System Mode to complete initialization and enter kernel - CPS #SYS_MODE - MOV SP, R0 - - ; Call SystemInit - IMPORT SystemInit - BL SystemInit - - ; Unmask interrupts - CPSIE if - - ; Call __main - IMPORT __main - BL __main - - ENDP - - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp deleted file mode 100644 index dfa0bc6f1fc..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp +++ /dev/null @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - ******************************************************************************* - * Copyright (c) 2017 ARM Limited. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#include -#endif - -#include -#include - -extern char Image$$ARM_LIB_HEAP$$Base[]; -extern char Image$$ARM_LIB_STACK$$Base[]; - -extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base; - uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base; - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S deleted file mode 100644 index 7bfaa35e51b..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S +++ /dev/null @@ -1,91 +0,0 @@ -;/* -; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; * ----------------------------------------------------------------------------- -; * -; * Project: CMSIS-RTOS RTX -; * Title: Cortex-A Exception handlers -; * -; * ----------------------------------------------------------------------------- -; */ - -MODE_SVC EQU 0x13 - - PRESERVE8 - THUMB - - AREA |.text|, CODE, READONLY - -IRQ_Handler PROC - EXPORT IRQ_Handler [WEAK] - - IMPORT IRQ_GetActiveIRQ - IMPORT IRQ_GetHandler - IMPORT IRQ_EndOfInterrupt - - SUB LR, LR, #4 ; Pre-adjust LR - SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack - CPS #MODE_SVC ; Change to SVC mode - PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers - - MOV R3, SP ; Move SP into R3 - AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment - SUB SP, SP, R3 ; Adjust stack - PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) - - BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 - MOV R4, R0 ; Move interrupt ID to R4 - - BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID - CMP R0, #0 ; Check if handler address is 0 - BEQ IRQ_End ; If 0, end interrupt and return - - CPSIE i ; Re-enable interrupts - BLX R0 ; Call IRQ handler - CPSID i ; Disable interrupts - -IRQ_End - MOV R0, R4 ; Move interrupt ID to R0 - BLX IRQ_EndOfInterrupt ; Signal end of interrupt - - POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) - ADD SP, SP, R3 ; Unadjust stack - - POP {R0-R3, R12, LR} ; Restore stacked APCS registers - RFEFD SP! ; Return from IRQ handler - - ENDP - - -Default_Handler PROC - EXPORT Undef_Handler [WEAK] - EXPORT SVC_Handler [WEAK] - EXPORT PAbt_Handler [WEAK] - EXPORT DAbt_Handler [WEAK] - EXPORT FIQ_Handler [WEAK] - -Undef_Handler -SVC_Handler -PAbt_Handler -DAbt_Handler -FIQ_Handler - - B . - - ENDP - - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld deleted file mode 100644 index e24116c99a7..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld +++ /dev/null @@ -1,241 +0,0 @@ -/* Linker script for mbed VK_RZ_A1H */ - -/* Linker script to configure memory regions. */ -/* -#ifdef RUN_FROM_SDRAM -MEMORY -{ - L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 - RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x01E00000 - RAM_NC (rwx) : ORIGIN = 0x49E00000, LENGTH = 0x00200000 - SRAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00960000 -} -REGION_ALIAS("SFLASH", RAM); -TTBOFFSET = 1M; - -#elif defined (RUN_FROM_SRAM) -MEMORY -{ - L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 - RAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00860000 - RAM_NC (rwx) : ORIGIN = 0x60900000, LENGTH = 0x00100000 - SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000 -} -REGION_ALIAS("SFLASH", RAM); -TTBOFFSET = 1M; -#else -*/ -MEMORY -{ - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000 - SFLASH (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000 - L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 - RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000 - RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000 - SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000 -} -/*#endif*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - - Image$$VECTORS$$Base = .; - KEEP(*(.isr_vector)) - *(SVC_TABLE) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - Image$$VECTORS$$Limit = .; - - Image$$RO_DATA$$Base = .; - *(.rodata*) - Image$$RO_DATA$$Limit = .; - - KEEP(*(.eh_frame*)) - } > SFLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > SFLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > SFLASH - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(8); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__nc_data_start) - LONG (__nc_data_end - __nc_data_start) - __copy_table_end__ = .; - } > SFLASH - - .zero.table : - { - . = ALIGN(8); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__nc_bss_start) - LONG (__nc_bss_end - __nc_bss_start) - __zero_table_end__ = .; - } > SFLASH - - __etext = .; - - .ttb : - { - Image$$TTB$$ZI$$Base = .; - . += 0x00004000; - Image$$TTB$$ZI$$Limit = .; - } > L_TTB - - .data : AT (__etext) - { - Image$$RW_DATA$$Base = .; - __data_start__ = .; - *(vtable) - *(.data*) - Image$$RW_DATA$$Limit = .; - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss ALIGN(0x10): - { - Image$$RW_IRAM1$$Base = .; - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - Image$$RW_IRAM1$$Limit = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - __HeapLimit = __StackLimit; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - __etext2 = __etext + SIZEOF(.data); - .nc_data : AT (__etext2) - { - Image$$RW_DATA_NC$$Base = .; - __nc_data_start = .; - *(NC_DATA) - - . = ALIGN(8); - __nc_data_end = .; - Image$$RW_DATA_NC$$Limit = .; - } > RAM_NC - - .nc_bss (NOLOAD) : - { - Image$$ZI_DATA_NC$$Base = .; - __nc_bss_start = .; - *(NC_BSS) - - . = ALIGN(8); - __nc_bss_end = .; - Image$$ZI_DATA_NC$$Limit = .; - } > RAM_NC -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S deleted file mode 100644 index 0506dd8c686..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S +++ /dev/null @@ -1,242 +0,0 @@ -/* File: startup_ARMCM3.s - * Purpose: startup file for Cortex-M3/M4 devices. Should use with - * GNU Tools for ARM Embedded Processors - * Version: V1.1 - * Date: 17 June 2011 - * - * Copyright (C) 2011 ARM Limited. All rights reserved. - * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - */ - .syntax unified - .extern _start - -@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs - .equ Mode_USR , 0x10 - .equ Mode_FIQ , 0x11 - .equ Mode_IRQ , 0x12 - .equ Mode_SVC , 0x13 - .equ Mode_ABT , 0x17 - .equ Mode_UND , 0x1B - .equ Mode_SYS , 0x1F - - .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled - .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled - .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state - -@ Stack Configuration - - .EQU UND_Stack_Size , 0x00000100 - .EQU SVC_Stack_Size , 0x00008000 - .EQU ABT_Stack_Size , 0x00000100 - .EQU FIQ_Stack_Size , 0x00000100 - .EQU IRQ_Stack_Size , 0x0000F000 - - .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) - - .section .stack - .align 3 - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space ISR_Stack_Size -__initial_sp: - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - -@ Heap Configuration - - .EQU Heap_Size , 0x00080000 - - .section .heap - .align 3 - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long 0xe59ff018 /* 0x00 */ - .long 0xe59ff018 /* 0x04 */ - .long 0xe59ff018 /* 0x08 */ - .long 0xe59ff018 /* 0x0c */ - .long 0xe59ff018 /* 0x10 */ - .long 0xe59ff018 /* 0x14 */ - .long 0xe59ff018 /* 0x18 */ - .long 0xe59ff018 /* 0x1c */ - - .long Reset_Handler /* 0x20 */ - .long Undef_Handler /* 0x24 */ - .long SVC_Handler /* 0x28 */ - .long PAbt_Handler /* 0x2c */ - .long DAbt_Handler /* 0x30 */ - .long 0 /* Reserved */ - .long IRQ_Handler /* IRQ */ - .long FIQ_Handler /* FIQ */ - - - .size __isr_vector, . - __isr_vector - - .text - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - @ Mask interrupts - CPSID if - - @ Put any cores other than 0 to sleep - mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR - ands r0, r0, #3 -goToSleep: - wfine - bne goToSleep - - @ Reset SCTLR Settings - mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register - bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache - bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache - bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU - bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction - bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs - mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register - isb - - @ Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register - -@ Set Vector Base Address Register (VBAR) to point to this application's vector table - ldr r0, =__isr_vector - mcr p15, 0, r0, c12, c0, 0 - -@ Setup Stack for each exceptional mode - ldr r0, =__StackTop - -@ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) - mov sp, r0 - sub r0, r0, #UND_Stack_Size - -@ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit) - mov sp, r0 - sub r0, r0, #ABT_Stack_Size - -@ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit) - mov sp, r0 - sub r0, r0, #FIQ_Stack_Size - -@ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit) - mov sp, r0 - sub r0, r0, #IRQ_Stack_Size - -@ Enter Supervisor Mode and set its Stack Pointer - msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit) - mov sp, r0 - -@ Enter System Mode to complete initialization and enter kernel - msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit) - mov sp, r0 - -@ USR/SYS stack pointer will be set during kernel init - ldr r0, =SystemInit - blx r0 - - @ Unmask interrupts - CPSIE if - -@ data sections copy - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - -@ bss sections clear - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - - ldr r0, =_start - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - - .text - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler Undef_Handler - def_default_handler SVC_Handler - def_default_handler PAbt_Handler - def_default_handler DAbt_Handler - def_default_handler IRQ_Handler - def_default_handler FIQ_Handler - - .END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf deleted file mode 100644 index d00e9df2878..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf +++ /dev/null @@ -1,66 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x18020000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x18020000; -define symbol __ICFEDIT_region_ROM_end__ = 0x19FFFFFF; -define symbol __ICFEDIT_region_TTB_start__ = 0x20000000; -define symbol __ICFEDIT_region_TTB_end__ = 0x2001FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20020000; -define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF; -define symbol __ICFEDIT_region_SDRAM_start__ = 0x08000000; -define symbol __ICFEDIT_region_SDRAM_end__ = 0x09FFFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x00004000; -define symbol __ICFEDIT_size_svcstack__ = 0x00008000; -define symbol __ICFEDIT_size_irqstack__ = 0x00008000; -define symbol __ICFEDIT_size_fiqstack__ = 0x00000100; -define symbol __ICFEDIT_size_undstack__ = 0x00000100; -define symbol __ICFEDIT_size_abtstack__ = 0x00000100; -define symbol __ICFEDIT_size_heap__ = 0x00080000; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF; - -define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60900000; -define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF; - -define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000; -define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF; - -define memory mem with size = 4G; - -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__ to __ICFEDIT_region_SDRAM_end__]; -define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__]; -define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__]; -define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__]; - -define block ROM_FIXED_ORDER with fixed order { ro code, ro data }; -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; -do not initialize { section .retram }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly, block ROM_FIXED_ORDER }; -place in RAM_region { readwrite, - block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, - block UND_STACK, block ABT_STACK, block HEAP }; - -place in RetRAM_region { section .retram }; -place in MirrorRAM_region { section .mirrorram }; -place in MirrorRetRAM_region { section .mirrorretram }; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S deleted file mode 100644 index 521dc5f1167..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S +++ /dev/null @@ -1,218 +0,0 @@ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Part one of the system initialization code, -;; contains low-level -;; initialization. -;; -;; Copyright 2007 IAR Systems. All rights reserved. -;; -;; $Revision: 49919 $ -;; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION CSTACK:DATA:NOROOT(3) - -; -; The module in this file are included in the libraries, and may be -; replaced by any user-defined modules that define the PUBLIC symbol -; __iar_program_start or a user defined start symbol. -; -; To override the cstartup defined in the library, simply add your -; modified version to the workbench project. - - SECTION .intvec:CODE:NOROOT(2) - - PUBLIC __vector_table - PUBLIC __RST_Handler - EXTERN Undef_Handler - EXTERN SVC_Handler - EXTERN PAbt_Handler - EXTERN DAbt_Handler - EXTERN IRQ_Handler - PUBLIC FIQ_Handler - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_table: ; Make this a DATA label, so that stack usage - ; analysis doesn't consider it an uncalled fun - - ARM - - ; All default exception handlers (except reset) are - ; defined as weak symbol definitions. - ; If a handler is defined by the application it will take precedence. - LDR PC,Reset_Addr ; Reset - LDR PC,Undefined_Addr ; Undefined instructions - LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) - LDR PC,Prefetch_Addr ; Prefetch abort - LDR PC,Abort_Addr ; Data abort - DCD 0 ; RESERVED - LDR PC,IRQ_Addr ; IRQ - LDR PC,FIQ_Addr ; FIQ - - DATA - -Reset_Addr: DCD __RST_Handler -Undefined_Addr: DCD Undef_Handler -SWI_Addr: DCD SVC_Handler -Prefetch_Addr: DCD PAbt_Handler -Abort_Addr: DCD DAbt_Handler -IRQ_Addr: DCD IRQ_Handler -FIQ_Addr: DCD FIQ_Handler - - -; -------------------------------------------------- -; ?cstartup -- low-level system initialization code. -; -; After a reset execution starts here, the mode is ARM, supervisor -; with interrupts disabled. -; - - - - SECTION .text:CODE:NOROOT(2) - EXTERN SystemInit - EXTERN __iar_program_start - REQUIRE __vector_table - EXTWEAK __iar_init_core - EXTWEAK __iar_init_vfp - - - ARM - -__RST_Handler: -?cstartup: - -;;; @ Mask interrupts - CPSID if - -;;; @ Put any cores other than 0 to sleep - mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR - ands r0, r0, #3 - -goToSleep: - wfine - bne goToSleep - -;;; @ Reset SCTLR Settings - mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register - bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache - bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache - bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU - bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction - bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs - mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register - isb - -;;; @ Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 ;@ Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) ;@ Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 ;@ Write CP15 Auxiliary Control Register - -;; Set Vector Base Address Register (VBAR) to point to this application's vector table - ldr r0, =__vector_table - mcr p15, 0, r0, c12, c0, 0 - - -; -; Add initialization needed before setup of stackpointers here. -; - -; -; Initialize the stack pointers. -; The pattern below can be used for any of the exception stacks: -; FIQ, IRQ, SVC, ABT, UND, SYS. -; The USR mode uses the same stack as SYS. -; The stack segments must be defined in the linker command file, -; and be declared above. -; - - -; -------------------- -; Mode, correspords to bits 0-5 in CPSR - -#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR - -#define USR_MODE 0x10 ; User mode -#define FIQ_MODE 0x11 ; Fast Interrupt Request mode -#define IRQ_MODE 0x12 ; Interrupt Request mode -#define SVC_MODE 0x13 ; Supervisor mode -#define ABT_MODE 0x17 ; Abort mode -#define UND_MODE 0x1B ; Undefined Instruction mode -#define SYS_MODE 0x1F ; System mode - - MRS r0, cpsr ; Original PSR value - - ;; Set up the SVC stack pointer. - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #SVC_MODE ; Set SVC mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the interrupt stack pointer. - - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the fast interrupt stack pointer. - - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #FIQ_MODE ; Set FIR mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - - ;; Set up the ABT stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #ABT_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(ABT_STACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - - ;; Set up the UDF stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #UND_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(UND_STACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the normal stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #SYS_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(CSTACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - -;;; -; USR/SYS stack pointer will be set during kernel init - ldr r0, =SystemInit - blx r0 - -;;; Continue to __cmain for C-level initialization. - - FUNCALL __RST_Handler, __iar_program_start - B __iar_program_start - -FIQ_Handler: - B . - - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h deleted file mode 100644 index 089284dc1cd..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h +++ /dev/null @@ -1 +0,0 @@ -#include "VK_RZ_A1H.h" diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h deleted file mode 100644 index 701c856fa49..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC1768 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "VKRZA1H.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c deleted file mode 100644 index 1fa680598ca..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c +++ /dev/null @@ -1,43 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2015 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "VKRZA1H.h" -#include "irq_ctrl.h" - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - InterruptHandlerRegister(IRQn, (IRQHandler)vector); -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn); - return vectors; -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h deleted file mode 100644 index faca6ce56c9..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h +++ /dev/null @@ -1,922 +0,0 @@ -/****************************************************************************** - * @file VK_RZ_A1H.h - * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version V1.00 - * @data 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __VK_RZ_A1H_H__ -#define __VK_RZ_A1H_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/****** SGI Interrupts Numbers ****************************************/ - SGI0_IRQn = 0, - SGI1_IRQn = 1, - SGI2_IRQn = 2, - SGI3_IRQn = 3, - SGI4_IRQn = 4, - SGI5_IRQn = 5, - SGI6_IRQn = 6, - SGI7_IRQn = 7, - SGI8_IRQn = 8, - SGI9_IRQn = 9, - SGI10_IRQn = 10, - SGI11_IRQn = 11, - SGI12_IRQn = 12, - SGI13_IRQn = 13, - SGI14_IRQn = 14, - SGI15_IRQn = 15, - -/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ - /* 16 - 578 */ - PMUIRQ0_IRQn = 16, - COMMRX0_IRQn = 17, - COMMTX0_IRQn = 18, - CTIIRQ0_IRQn = 19, - - IRQ0_IRQn = 32, - IRQ1_IRQn = 33, - IRQ2_IRQn = 34, - IRQ3_IRQn = 35, - IRQ4_IRQn = 36, - IRQ5_IRQn = 37, - IRQ6_IRQn = 38, - IRQ7_IRQn = 39, - - PL310ERR_IRQn = 40, - - DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ - DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ - DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ - DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ - DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ - DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ - DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ - DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ - DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ - DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ - DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ - DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ - DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ - DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ - DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ - DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ - DMAERR_IRQn = 57, /*!< DMAC Interrupt */ - - /* 58-72 Reserved */ - - USBI0_IRQn = 73, - USBI1_IRQn = 74, - - S0_VI_VSYNC0_IRQn = 75, - S0_LO_VSYNC0_IRQn = 76, - S0_VSYNCERR0_IRQn = 77, - GR3_VLINE0_IRQn = 78, - S0_VFIELD0_IRQn = 79, - IV1_VBUFERR0_IRQn = 80, - IV3_VBUFERR0_IRQn = 81, - IV5_VBUFERR0_IRQn = 82, - IV6_VBUFERR0_IRQn = 83, - S0_WLINE0_IRQn = 84, - S1_VI_VSYNC0_IRQn = 85, - S1_LO_VSYNC0_IRQn = 86, - S1_VSYNCERR0_IRQn = 87, - S1_VFIELD0_IRQn = 88, - IV2_VBUFERR0_IRQn = 89, - IV4_VBUFERR0_IRQn = 90, - S1_WLINE0_IRQn = 91, - OIR_VI_VSYNC0_IRQn = 92, - OIR_LO_VSYNC0_IRQn = 93, - OIR_VSYNCERR0_IRQn = 94, - OIR_VFIELD0_IRQn = 95, - IV7_VBUFERR0_IRQn = 96, - IV8_VBUFERR0_IRQn = 97, - /* 98 Reserved */ - S0_VI_VSYNC1_IRQn = 99, - S0_LO_VSYNC1_IRQn = 100, - S0_VSYNCERR1_IRQn = 101, - GR3_VLINE1_IRQn = 102, - S0_VFIELD1_IRQn = 103, - IV1_VBUFERR1_IRQn = 104, - IV3_VBUFERR1_IRQn = 105, - IV5_VBUFERR1_IRQn = 106, - IV6_VBUFERR1_IRQn = 107, - S0_WLINE1_IRQn = 108, - S1_VI_VSYNC1_IRQn = 109, - S1_LO_VSYNC1_IRQn = 110, - S1_VSYNCERR1_IRQn = 111, - S1_VFIELD1_IRQn = 112, - IV2_VBUFERR1_IRQn = 113, - IV4_VBUFERR1_IRQn = 114, - S1_WLINE1_IRQn = 115, - OIR_VI_VSYNC1_IRQn = 116, - OIR_LO_VSYNC1_IRQn = 117, - OIR_VSYNCERR1_IRQn = 118, - OIR_VFIELD1_IRQn = 119, - IV7_VBUFERR1_IRQn = 120, - IV8_VBUFERR1_IRQn = 121, - /* Reserved = 122 */ - - IMRDI_IRQn = 123, - IMR2I0_IRQn = 124, - IMR2I1_IRQn = 125, - - JEDI_IRQn = 126, - JDTI_IRQn = 127, - - CMP0_IRQn = 128, - CMP1_IRQn = 129, - - INT0_IRQn = 130, - INT1_IRQn = 131, - INT2_IRQn = 132, - INT3_IRQn = 133, - - OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ - OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ - - CMI_IRQn = 136, - WTOUT_IRQn = 137, - - ITI_IRQn = 138, - - TGI0A_IRQn = 139, - TGI0B_IRQn = 140, - TGI0C_IRQn = 141, - TGI0D_IRQn = 142, - TGI0V_IRQn = 143, - TGI0E_IRQn = 144, - TGI0F_IRQn = 145, - TGI1A_IRQn = 146, - TGI1B_IRQn = 147, - TGI1V_IRQn = 148, - TGI1U_IRQn = 149, - TGI2A_IRQn = 150, - TGI2B_IRQn = 151, - TGI2V_IRQn = 152, - TGI2U_IRQn = 153, - TGI3A_IRQn = 154, - TGI3B_IRQn = 155, - TGI3C_IRQn = 156, - TGI3D_IRQn = 157, - TGI3V_IRQn = 158, - TGI4A_IRQn = 159, - TGI4B_IRQn = 160, - TGI4C_IRQn = 161, - TGI4D_IRQn = 162, - TGI4V_IRQn = 163, - - CMI1_IRQn = 164, - CMI2_IRQn = 165, - - SGDEI0_IRQn = 166, - SGDEI1_IRQn = 167, - SGDEI2_IRQn = 168, - SGDEI3_IRQn = 169, - - ADI_IRQn = 170, - LMTI_IRQn = 171, - - SSII0_IRQn = 172, /*!< SSIF Interrupt */ - SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ - SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ - SSII1_IRQn = 175, /*!< SSIF Interrupt */ - SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ - SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ - SSII2_IRQn = 178, /*!< SSIF Interrupt */ - SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ - SSII3_IRQn = 180, /*!< SSIF Interrupt */ - SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ - SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ - SSII4_IRQn = 183, /*!< SSIF Interrupt */ - SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ - SSII5_IRQn = 185, /*!< SSIF Interrupt */ - SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ - SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ - - SPDIFI_IRQn = 188, - - INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ - INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ - INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ - INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ - INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ - INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ - INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ - INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ - INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ - INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ - INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ - INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ - INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ - INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ - INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ - INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ - INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ - INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ - INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ - INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ - INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ - INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ - INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ - INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ - INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ - INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ - INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ - INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ - INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ - INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ - INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ - INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ - - SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ - SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ - SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ - SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ - SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ - SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ - SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ - SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ - SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ - SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ - SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ - SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ - SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ - SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ - SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ - SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ - SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ - SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ - SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ - SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ - SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ - SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ - SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ - SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ - SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ - SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ - SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ - SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ - SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ - SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ - SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ - SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ - - INTRCANGERR_IRQn = 253, - INTRCANGRECC_IRQn = 254, - INTRCAN0REC_IRQn = 255, - INTRCAN0ERR_IRQn = 256, - INTRCAN0TRX_IRQn = 257, - INTRCAN1REC_IRQn = 258, - INTRCAN1ERR_IRQn = 259, - INTRCAN1TRX_IRQn = 260, - INTRCAN2REC_IRQn = 261, - INTRCAN2ERR_IRQn = 262, - INTRCAN2TRX_IRQn = 263, - INTRCAN3REC_IRQn = 264, - INTRCAN3ERR_IRQn = 265, - INTRCAN3TRX_IRQn = 266, - INTRCAN4REC_IRQn = 267, - INTRCAN4ERR_IRQn = 268, - INTRCAN4TRX_IRQn = 269, - - RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ - RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ - RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ - RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ - RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ - RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ - RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ - RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ - RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ - RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ - RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ - RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ - RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ - RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ - RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ - - IEBBTD_IRQn = 285, - IEBBTERR_IRQn = 286, - IEBBTSTA_IRQn = 287, - IEBBTV_IRQn = 288, - - ISY_IRQn = 289, - IERR_IRQn = 290, - ITARG_IRQn = 291, - ISEC_IRQn = 292, - IBUF_IRQn = 293, - IREADY_IRQn = 294, - - STERB_IRQn = 295, - FLTENDI_IRQn = 296, - FLTREQ0I_IRQn = 297, - FLTREQ1I_IRQn = 298, - - MMC0_IRQn = 299, - MMC1_IRQn = 300, - MMC2_IRQn = 301, - - SCHI0_3_IRQn = 302, - SDHI0_0_IRQn = 303, - SDHI0_1_IRQn = 304, - SCHI1_3_IRQn = 305, - SDHI1_0_IRQn = 306, - SDHI1_1_IRQn = 307, - - ARM_IRQn = 308, - PRD_IRQn = 309, - CUP_IRQn = 310, - - SCUAI0_IRQn = 311, - SCUAI1_IRQn = 312, - SCUFDI0_IRQn = 313, - SCUFDI1_IRQn = 314, - SCUFDI2_IRQn = 315, - SCUFDI3_IRQn = 316, - SCUFUI0_IRQn = 317, - SCUFUI1_IRQn = 318, - SCUFUI2_IRQn = 319, - SCUFUI3_IRQn = 320, - SCUDVI0_IRQn = 321, - SCUDVI1_IRQn = 322, - SCUDVI2_IRQn = 323, - SCUDVI3_IRQn = 324, - - MLB_CINT_IRQn = 325, - MLB_SINT_IRQn = 326, - - DRC10_IRQn = 327, - DRC11_IRQn = 328, - - /* 329-330 Reserved */ - - LINI0_INT_T_IRQn = 331, - LINI0_INT_R_IRQn = 332, - LINI0_INT_S_IRQn = 333, - LINI0_INT_M_IRQn = 334, - LINI1_INT_T_IRQn = 335, - LINI1_INT_R_IRQn = 336, - LINI1_INT_S_IRQn = 337, - LINI1_INT_M_IRQn = 338, - - /* 339-346 Reserved */ - - SCIERI0_IRQn = 347, - SCIRXI0_IRQn = 348, - SCITXI0_IRQn = 349, - SCITEI0_IRQn = 350, - SCIERI1_IRQn = 351, - SCIRXI1_IRQn = 352, - SCITXI1_IRQn = 353, - SCITEI1_IRQn = 354, - - AVBI_DATA = 355, - AVBI_ERROR = 356, - AVBI_MANAGE = 357, - AVBI_MAC = 358, - - ETHERI_IRQn = 359, - - /* 360-363 Reserved */ - - CEUI_IRQn = 364, - - /* 365-380 Reserved */ - - H2XMLB_ERRINT_IRQn = 381, - H2XIC1_ERRINT_IRQn = 382, - X2HPERI1_ERRINT_IRQn = 383, - X2HPERR2_ERRINT_IRQn = 384, - X2HPERR34_ERRINT_IRQn= 385, - X2HPERR5_ERRINT_IRQn = 386, - X2HPERR67_ERRINT_IRQn= 387, - X2HDBGR_ERRINT_IRQn = 388, - X2HBSC_ERRINT_IRQn = 389, - X2HSPI1_ERRINT_IRQn = 390, - X2HSPI2_ERRINT_IRQn = 391, - PRRI_IRQn = 392, - - IFEI0_IRQn = 393, - OFFI0_IRQn = 394, - PFVEI0_IRQn = 395, - IFEI1_IRQn = 396, - OFFI1_IRQn = 397, - PFVEI1_IRQn = 398, - - /* 399-415 Reserved */ - - TINT0_IRQn = 416, - TINT1_IRQn = 417, - TINT2_IRQn = 418, - TINT3_IRQn = 419, - TINT4_IRQn = 420, - TINT5_IRQn = 421, - TINT6_IRQn = 422, - TINT7_IRQn = 423, - TINT8_IRQn = 424, - TINT9_IRQn = 425, - TINT10_IRQn = 426, - TINT11_IRQn = 427, - TINT12_IRQn = 428, - TINT13_IRQn = 429, - TINT14_IRQn = 430, - TINT15_IRQn = 431, - TINT16_IRQn = 432, - TINT17_IRQn = 433, - TINT18_IRQn = 434, - TINT19_IRQn = 435, - TINT20_IRQn = 436, - TINT21_IRQn = 437, - TINT22_IRQn = 438, - TINT23_IRQn = 439, - TINT24_IRQn = 440, - TINT25_IRQn = 441, - TINT26_IRQn = 442, - TINT27_IRQn = 443, - TINT28_IRQn = 444, - TINT29_IRQn = 445, - TINT30_IRQn = 446, - TINT31_IRQn = 447, - TINT32_IRQn = 448, - TINT33_IRQn = 449, - TINT34_IRQn = 450, - TINT35_IRQn = 451, - TINT36_IRQn = 452, - TINT37_IRQn = 453, - TINT38_IRQn = 454, - TINT39_IRQn = 455, - TINT40_IRQn = 456, - TINT41_IRQn = 457, - TINT42_IRQn = 458, - TINT43_IRQn = 459, - TINT44_IRQn = 460, - TINT45_IRQn = 461, - TINT46_IRQn = 462, - TINT47_IRQn = 463, - TINT48_IRQn = 464, - TINT49_IRQn = 465, - TINT50_IRQn = 466, - TINT51_IRQn = 467, - TINT52_IRQn = 468, - TINT53_IRQn = 469, - TINT54_IRQn = 470, - TINT55_IRQn = 471, - TINT56_IRQn = 472, - TINT57_IRQn = 473, - TINT58_IRQn = 474, - TINT59_IRQn = 475, - TINT60_IRQn = 476, - TINT61_IRQn = 477, - TINT62_IRQn = 478, - TINT63_IRQn = 479, - TINT64_IRQn = 480, - TINT65_IRQn = 481, - TINT66_IRQn = 482, - TINT67_IRQn = 483, - TINT68_IRQn = 484, - TINT69_IRQn = 485, - TINT70_IRQn = 486, - TINT71_IRQn = 487, - TINT72_IRQn = 488, - TINT73_IRQn = 489, - TINT74_IRQn = 490, - TINT75_IRQn = 491, - TINT76_IRQn = 492, - TINT77_IRQn = 493, - TINT78_IRQn = 494, - TINT79_IRQn = 495, - TINT80_IRQn = 496, - TINT81_IRQn = 497, - TINT82_IRQn = 498, - TINT83_IRQn = 499, - TINT84_IRQn = 500, - TINT85_IRQn = 501, - TINT86_IRQn = 502, - TINT87_IRQn = 503, - TINT88_IRQn = 504, - TINT89_IRQn = 505, - TINT90_IRQn = 506, - TINT91_IRQn = 507, - TINT92_IRQn = 508, - TINT93_IRQn = 509, - TINT94_IRQn = 510, - TINT95_IRQn = 511, - TINT96_IRQn = 512, - TINT97_IRQn = 513, - TINT98_IRQn = 514, - TINT99_IRQn = 515, - TINT100_IRQn = 516, - TINT101_IRQn = 517, - TINT102_IRQn = 518, - TINT103_IRQn = 519, - TINT104_IRQn = 520, - TINT105_IRQn = 521, - TINT106_IRQn = 522, - TINT107_IRQn = 523, - TINT108_IRQn = 524, - TINT109_IRQn = 525, - TINT110_IRQn = 526, - TINT111_IRQn = 527, - TINT112_IRQn = 528, - TINT113_IRQn = 529, - TINT114_IRQn = 530, - TINT115_IRQn = 531, - TINT116_IRQn = 532, - TINT117_IRQn = 533, - TINT118_IRQn = 534, - TINT119_IRQn = 535, - TINT120_IRQn = 536, - TINT121_IRQn = 537, - TINT122_IRQn = 538, - TINT123_IRQn = 539, - TINT124_IRQn = 540, - TINT125_IRQn = 541, - TINT126_IRQn = 542, - TINT127_IRQn = 543, - TINT128_IRQn = 544, - TINT129_IRQn = 545, - TINT130_IRQn = 546, - TINT131_IRQn = 547, - TINT132_IRQn = 548, - TINT133_IRQn = 549, - TINT134_IRQn = 550, - TINT135_IRQn = 551, - TINT136_IRQn = 552, - TINT137_IRQn = 553, - TINT138_IRQn = 554, - TINT139_IRQn = 555, - TINT140_IRQn = 556, - TINT141_IRQn = 557, - TINT142_IRQn = 558, - TINT143_IRQn = 559, - TINT144_IRQn = 560, - TINT145_IRQn = 561, - TINT146_IRQn = 562, - TINT147_IRQn = 563, - TINT148_IRQn = 564, - TINT149_IRQn = 565, - TINT150_IRQn = 566, - TINT151_IRQn = 567, - TINT152_IRQn = 568, - TINT153_IRQn = 569, - TINT154_IRQn = 570, - TINT155_IRQn = 571, - TINT156_IRQn = 572, - TINT157_IRQn = 573, - TINT158_IRQn = 574, - TINT159_IRQn = 575, - TINT160_IRQn = 576, - TINT161_IRQn = 577, - TINT162_IRQn = 578, - TINT163_IRQn = 579, - TINT164_IRQn = 580, - TINT165_IRQn = 581, - TINT166_IRQn = 582, - TINT167_IRQn = 583, - TINT168_IRQn = 584, - TINT169_IRQn = 585, - TINT170_IRQn = 586 - -} IRQn_Type; - -#define RZ_A1_IRQ_MAX TINT170_IRQn - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ - -#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ -#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ -#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ -#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ -#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ -#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ -#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ -#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ -#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ -#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ -#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ -#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ -#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ -#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ -#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ -#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ -#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ -#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */ -#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE -#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE -#define L2C_310_BASE RZ_A1_PL310_BASE -#define TIMER_BASE RZ_A1_PRIVATE_TIMER - -/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ -#define __CA_REV 0x0000U /*!< Core revision r0p0 */ -#define __CORTEX_A 9U /*!< Cortex-A9 Core */ -#if (__FPU_PRESENT != 1) -#undef __FPU_PRESENT -#define __FPU_PRESENT 1U /* FPU present */ -#endif -#define __GIC_PRESENT 1U /* GIC present */ -#define __TIM_PRESENT 0U /* TIM present */ -#define __L2C_PRESENT 1U /* L2C present */ - -#include "core_ca.h" -#include "nvic_wrapper.h" -#include -#include "iodefine.h" - -/******************************************************************************/ -/* Clock Settings */ -/******************************************************************************/ -/* - * Clock Mode 0 settings - * SW1-4(MD_CLK):ON - * SW1-5(MD_CLKS):ON - * FRQCR=0x1035 - * CLKEN2 = 0b - unstable - * CLKEN[1:0]=01b - Output, Low, Low - * IFC[1:0] =00b - CPU clock is 1/1 PLL clock - * FRQCR2=0x0001 - * GFC[1:0] =01b - Graphic clock is 2/3 bus clock - */ -#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) -#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) -#define CM0_RENESAS_RZ_A1_I_CLK (400000000u) -#define CM0_RENESAS_RZ_A1_G_CLK (266666666u) -#define CM0_RENESAS_RZ_A1_B_CLK (133333333u) -#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) -#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) - -/* - * Clock Mode 1 settings - * SW1-4(MD_CLK):OFF - * SW1-5(MD_CLKS):ON - * FRQCR=0x1335 - * CLKEN2 = 0b - unstable - * CLKEN[1:0]=01b - Output, Low, Low - * IFC[1:0] =11b - CPU clock is 1/3 PLL clock - * FRQCR2=0x0003 - * GFC[1:0] =11b - graphic clock is 1/3 bus clock - */ -#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) -#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) -#define CM1_RENESAS_RZ_A1_I_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_G_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_B_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) -#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) - -/******************************************************************************/ -/* CPG Settings */ -/******************************************************************************/ -#define CPG_FRQCR_SHIFT_CKOEN2 (14) -#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) -#define CPG_FRQCR_SHIFT_CKOEN0 (12) -#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) -#define CPG_FRQCR_SHIFT_IFC (8) -#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) - -#define CPG_FRQCR2_SHIFT_GFC (0) -#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) - - -#define CPG_STBCR1_BIT_STBY (0x80u) -#define CPG_STBCR1_BIT_DEEP (0x40u) -#define CPG_STBCR2_BIT_HIZ (0x80u) -#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ -#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ -#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ -#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ -#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ -#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ -#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ -#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */ -#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ -#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ -#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ -#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ -#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ -#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ -#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ -#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ -#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ -#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ -#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ -#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ -#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ -#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ -#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ -#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ -#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ -#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */ -#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ -#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ -#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ -#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */ -#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */ -#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ -#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ -#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ -#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ -#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */ -#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ -#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ -#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ -#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ -#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ -#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ -#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ -#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ -#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */ -#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ -#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ -#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ -#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ -#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ -#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ -#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ -#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ -#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ -#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ -#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ -#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ -#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ -#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ -#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ -#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ -#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ -#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ -#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ -#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ -#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ -#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ -#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ -#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ -#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ -#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ -#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ -#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */ -#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */ -#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ -#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ -#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ -#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ -#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ -#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ -#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ -#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ -#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ -#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ -#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ -#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ -#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ -#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ -#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ -#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ -#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ -#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ -#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ -#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ -#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ -#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ -#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ -#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */ -#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */ -#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */ -#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */ -#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */ -#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */ -#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */ -#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */ -#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */ -#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */ -#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */ -#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */ -#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */ -#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */ -#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */ -#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */ -#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */ -#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */ -#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */ -#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */ -#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */ -#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */ -#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */ -#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */ -#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */ -#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */ -#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */ -#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */ -#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */ -#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */ -#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */ -#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */ -#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */ -#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */ -#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */ -#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */ -#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */ -#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */ -#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */ -#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */ -#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */ -#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */ -#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */ -#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */ -#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */ -#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */ -#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */ -#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */ -#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */ -#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */ -#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */ -#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */ -#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */ -#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */ -#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */ -#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */ -#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */ -#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */ -#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */ -#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */ -#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */ -#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */ -#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */ -#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */ -#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */ -#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */ -#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */ -#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */ -#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */ -#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */ -#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */ -#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */ -#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */ -#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */ -#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */ - -/******************************************************************************/ -/* GPIO Settings */ -/******************************************************************************/ -#define GPIO_BIT_N0 (1u << 0) -#define GPIO_BIT_N1 (1u << 1) -#define GPIO_BIT_N2 (1u << 2) -#define GPIO_BIT_N3 (1u << 3) -#define GPIO_BIT_N4 (1u << 4) -#define GPIO_BIT_N5 (1u << 5) -#define GPIO_BIT_N6 (1u << 6) -#define GPIO_BIT_N7 (1u << 7) -#define GPIO_BIT_N8 (1u << 8) -#define GPIO_BIT_N9 (1u << 9) -#define GPIO_BIT_N10 (1u << 10) -#define GPIO_BIT_N11 (1u << 11) -#define GPIO_BIT_N12 (1u << 12) -#define GPIO_BIT_N13 (1u << 13) -#define GPIO_BIT_N14 (1u << 14) -#define GPIO_BIT_N15 (1u << 15) - -#define MD_BOOT10_MASK (0x3) - -#define MD_BOOT10_BM0 (0x0) -#define MD_BOOT10_BM1 (0x2) -#define MD_BOOT10_BM3 (0x1) -#define MD_BOOT10_BM4_5 (0x3) - -#define MD_CLK (1u << 2) -#define MD_CLKS (1u << 3) - - -#ifdef __cplusplus -} -#endif - -#endif // __VK_RZ_A1H_H__ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h deleted file mode 100644 index 1f016294b44..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h +++ /dev/null @@ -1,357 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : bsc_iobitmask.h -* $Rev: 1115 $ -* $Date:: 2014-07-09 15:35:02 +0900#$ -* Description : BSC register define header -*******************************************************************************/ -#ifndef BSC_IOBITMASK_H -#define BSC_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -#define BSC_CMNCR_HIZCNT (0x00000001uL) -#define BSC_CMNCR_HIZMEM (0x00000002uL) -#define BSC_CMNCR_DPRTY (0x00000600uL) -#define BSC_CMNCR_AL0 (0x01000000uL) -#define BSC_CMNCR_TL0 (0x10000000uL) - -#define BSC_CS0BCR_BSZ (0x00000600uL) -#define BSC_CS0BCR_TYPE (0x00007000uL) -#define BSC_CS0BCR_IWRRS (0x00070000uL) -#define BSC_CS0BCR_IWRRD (0x00380000uL) -#define BSC_CS0BCR_IWRWS (0x01C00000uL) -#define BSC_CS0BCR_IWRWD (0x0E000000uL) -#define BSC_CS0BCR_IWW (0x70000000uL) - -#define BSC_CS1BCR_BSZ (0x00000600uL) -#define BSC_CS1BCR_TYPE (0x00007000uL) -#define BSC_CS1BCR_IWRRS (0x00070000uL) -#define BSC_CS1BCR_IWRRD (0x00380000uL) -#define BSC_CS1BCR_IWRWS (0x01C00000uL) -#define BSC_CS1BCR_IWRWD (0x0E000000uL) -#define BSC_CS1BCR_IWW (0x70000000uL) - -#define BSC_CS2BCR_BSZ (0x00000600uL) -#define BSC_CS2BCR_TYPE (0x00007000uL) -#define BSC_CS2BCR_IWRRS (0x00070000uL) -#define BSC_CS2BCR_IWRRD (0x00380000uL) -#define BSC_CS2BCR_IWRWS (0x01C00000uL) -#define BSC_CS2BCR_IWRWD (0x0E000000uL) -#define BSC_CS2BCR_IWW (0x70000000uL) - -#define BSC_CS3BCR_BSZ (0x00000600uL) -#define BSC_CS3BCR_TYPE (0x00007000uL) -#define BSC_CS3BCR_IWRRS (0x00070000uL) -#define BSC_CS3BCR_IWRRD (0x00380000uL) -#define BSC_CS3BCR_IWRWS (0x01C00000uL) -#define BSC_CS3BCR_IWRWD (0x0E000000uL) -#define BSC_CS3BCR_IWW (0x70000000uL) - -#define BSC_CS4BCR_BSZ (0x00000600uL) -#define BSC_CS4BCR_TYPE (0x00007000uL) -#define BSC_CS4BCR_IWRRS (0x00070000uL) -#define BSC_CS4BCR_IWRRD (0x00380000uL) -#define BSC_CS4BCR_IWRWS (0x01C00000uL) -#define BSC_CS4BCR_IWRWD (0x0E000000uL) -#define BSC_CS4BCR_IWW (0x70000000uL) - -#define BSC_CS5BCR_BSZ (0x00000600uL) -#define BSC_CS5BCR_TYPE (0x00007000uL) -#define BSC_CS5BCR_IWRRS (0x00070000uL) -#define BSC_CS5BCR_IWRRD (0x00380000uL) -#define BSC_CS5BCR_IWRWS (0x01C00000uL) -#define BSC_CS5BCR_IWRWD (0x0E000000uL) -#define BSC_CS5BCR_IWW (0x70000000uL) - -#define BSC_CS0WCR_NORMAL_HW (0x00000003uL) -#define BSC_CS0WCR_NORMAL_WM (0x00000040uL) -#define BSC_CS0WCR_NORMAL_WR (0x00000780uL) -#define BSC_CS0WCR_NORMAL_SW (0x00001800uL) -#define BSC_CS0WCR_NORMAL_BAS (0x00100000uL) - -#define BSC_CS1WCR_NORMAL_HW (0x00000003uL) -#define BSC_CS1WCR_NORMAL_WM (0x00000040uL) -#define BSC_CS1WCR_NORMAL_WR (0x00000780uL) -#define BSC_CS1WCR_NORMAL_SW (0x00001800uL) -#define BSC_CS1WCR_NORMAL_WW (0x00070000uL) -#define BSC_CS1WCR_NORMAL_BAS (0x00100000uL) - -#define BSC_CS2WCR_NORMAL_WM (0x00000040uL) -#define BSC_CS2WCR_NORMAL_WR (0x00000780uL) -#define BSC_CS2WCR_NORMAL_BAS (0x00100000uL) - -#define BSC_CS3WCR_NORMAL_WM (0x00000040uL) -#define BSC_CS3WCR_NORMAL_WR (0x00000780uL) -#define BSC_CS3WCR_NORMAL_BAS (0x00100000uL) - -#define BSC_CS4WCR_NORMAL_HW (0x00000003uL) -#define BSC_CS4WCR_NORMAL_WM (0x00000040uL) -#define BSC_CS4WCR_NORMAL_WR (0x00000780uL) -#define BSC_CS4WCR_NORMAL_SW (0x00001800uL) -#define BSC_CS4WCR_NORMAL_WW (0x00070000uL) -#define BSC_CS4WCR_NORMAL_BAS (0x00100000uL) - -#define BSC_CS5WCR_NORMAL_HW (0x00000003uL) -#define BSC_CS5WCR_NORMAL_WM (0x00000040uL) -#define BSC_CS5WCR_NORMAL_WR (0x00000780uL) -#define BSC_CS5WCR_NORMAL_SW (0x00001800uL) -#define BSC_CS5WCR_NORMAL_WW (0x00070000uL) -#define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL) -#define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL) - -#define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL) -#define BSC_CS0WCR_BROM_ASY_W (0x00000780uL) -#define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL) -#define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL) - -#define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL) -#define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL) -#define BSC_CS4WCR_BROM_ASY_W (0x00000780uL) -#define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL) -#define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL) -#define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL) - -#define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL) - -#define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL) -#define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL) -#define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL) -#define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL) -#define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL) - -#define BSC_CS0WCR_BROM_SY_WM (0x00000040uL) -#define BSC_CS0WCR_BROM_SY_W (0x00000780uL) -#define BSC_CS0WCR_BROM_SY_BW (0x00030000uL) - -#define BSC_SDCR_A3COL (0x00000003uL) -#define BSC_SDCR_A3ROW (0x00000018uL) -#define BSC_SDCR_BACTV (0x00000100uL) -#define BSC_SDCR_PDOWN (0x00000200uL) -#define BSC_SDCR_RMODE (0x00000400uL) -#define BSC_SDCR_RFSH (0x00000800uL) -#define BSC_SDCR_DEEP (0x00002000uL) -#define BSC_SDCR_A2COL (0x00030000uL) -#define BSC_SDCR_A2ROW (0x00180000uL) - -#define BSC_RTCSR_RRC (0x00000007uL) -#define BSC_RTCSR_CKS (0x00000038uL) -#define BSC_RTCSR_CMIE (0x00000040uL) -#define BSC_RTCSR_CMF (0x00000080uL) - -#define BSC_RTCNT_D (0xFFFFFFFFuL) - -#define BSC_RTCOR_D (0xFFFFFFFFuL) - -#define BSC_TOSCOR0_D (0x0000FFFFuL) - -#define BSC_TOSCOR1_D (0x0000FFFFuL) - -#define BSC_TOSCOR2_D (0x0000FFFFuL) - -#define BSC_TOSCOR3_D (0x0000FFFFuL) - -#define BSC_TOSCOR4_D (0x0000FFFFuL) - -#define BSC_TOSCOR5_D (0x0000FFFFuL) - -#define BSC_TOSTR_CS0TOSTF (0x00000001uL) -#define BSC_TOSTR_CS1TOSTF (0x00000002uL) -#define BSC_TOSTR_CS2TOSTF (0x00000004uL) -#define BSC_TOSTR_CS3TOSTF (0x00000008uL) -#define BSC_TOSTR_CS4TOSTF (0x00000010uL) -#define BSC_TOSTR_CS5TOSTF (0x00000020uL) - -#define BSC_TOENR_CS0TOEN (0x00000001uL) -#define BSC_TOENR_CS1TOEN (0x00000002uL) -#define BSC_TOENR_CS2TOEN (0x00000004uL) -#define BSC_TOENR_CS3TOEN (0x00000008uL) -#define BSC_TOENR_CS4TOEN (0x00000010uL) -#define BSC_TOENR_CS5TOEN (0x00000020uL) - - -/* ==== Shift values for IO registers ==== */ -#define BSC_CMNCR_HIZCNT_SHIFT (0u) -#define BSC_CMNCR_HIZMEM_SHIFT (1u) -#define BSC_CMNCR_DPRTY_SHIFT (9u) -#define BSC_CMNCR_AL0_SHIFT (24u) -#define BSC_CMNCR_TL0_SHIFT (28u) - -#define BSC_CS0BCR_BSZ_SHIFT (9u) -#define BSC_CS0BCR_TYPE_SHIFT (12u) -#define BSC_CS0BCR_IWRRS_SHIFT (16u) -#define BSC_CS0BCR_IWRRD_SHIFT (19u) -#define BSC_CS0BCR_IWRWS_SHIFT (22u) -#define BSC_CS0BCR_IWRWD_SHIFT (25u) -#define BSC_CS0BCR_IWW_SHIFT (28u) - -#define BSC_CS1BCR_BSZ_SHIFT (9u) -#define BSC_CS1BCR_TYPE_SHIFT (12u) -#define BSC_CS1BCR_IWRRS_SHIFT (16u) -#define BSC_CS1BCR_IWRRD_SHIFT (19u) -#define BSC_CS1BCR_IWRWS_SHIFT (22u) -#define BSC_CS1BCR_IWRWD_SHIFT (25u) -#define BSC_CS1BCR_IWW_SHIFT (28u) - -#define BSC_CS2BCR_BSZ_SHIFT (9u) -#define BSC_CS2BCR_TYPE_SHIFT (12u) -#define BSC_CS2BCR_IWRRS_SHIFT (16u) -#define BSC_CS2BCR_IWRRD_SHIFT (19u) -#define BSC_CS2BCR_IWRWS_SHIFT (22u) -#define BSC_CS2BCR_IWRWD_SHIFT (25u) -#define BSC_CS2BCR_IWW_SHIFT (28u) - -#define BSC_CS3BCR_BSZ_SHIFT (9u) -#define BSC_CS3BCR_TYPE_SHIFT (12u) -#define BSC_CS3BCR_IWRRS_SHIFT (16u) -#define BSC_CS3BCR_IWRRD_SHIFT (19u) -#define BSC_CS3BCR_IWRWS_SHIFT (22u) -#define BSC_CS3BCR_IWRWD_SHIFT (25u) -#define BSC_CS3BCR_IWW_SHIFT (28u) - -#define BSC_CS4BCR_BSZ_SHIFT (9u) -#define BSC_CS4BCR_TYPE_SHIFT (12u) -#define BSC_CS4BCR_IWRRS_SHIFT (16u) -#define BSC_CS4BCR_IWRRD_SHIFT (19u) -#define BSC_CS4BCR_IWRWS_SHIFT (22u) -#define BSC_CS4BCR_IWRWD_SHIFT (25u) -#define BSC_CS4BCR_IWW_SHIFT (28u) - -#define BSC_CS5BCR_BSZ_SHIFT (9u) -#define BSC_CS5BCR_TYPE_SHIFT (12u) -#define BSC_CS5BCR_IWRRS_SHIFT (16u) -#define BSC_CS5BCR_IWRRD_SHIFT (19u) -#define BSC_CS5BCR_IWRWS_SHIFT (22u) -#define BSC_CS5BCR_IWRWD_SHIFT (25u) -#define BSC_CS5BCR_IWW_SHIFT (28u) - -#define BSC_CS0WCR_NORMAL_HW_SHIFT (0u) -#define BSC_CS0WCR_NORMAL_WM_SHIFT (6u) -#define BSC_CS0WCR_NORMAL_WR_SHIFT (7u) -#define BSC_CS0WCR_NORMAL_SW_SHIFT (11u) -#define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u) - -#define BSC_CS1WCR_NORMAL_HW_SHIFT (0u) -#define BSC_CS1WCR_NORMAL_WM_SHIFT (6u) -#define BSC_CS1WCR_NORMAL_WR_SHIFT (7u) -#define BSC_CS1WCR_NORMAL_SW_SHIFT (11u) -#define BSC_CS1WCR_NORMAL_WW_SHIFT (16u) -#define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u) - -#define BSC_CS2WCR_NORMAL_WM_SHIFT (6u) -#define BSC_CS2WCR_NORMAL_WR_SHIFT (7u) -#define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u) - -#define BSC_CS3WCR_NORMAL_WM_SHIFT (6u) -#define BSC_CS3WCR_NORMAL_WR_SHIFT (7u) -#define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u) - -#define BSC_CS4WCR_NORMAL_HW_SHIFT (0u) -#define BSC_CS4WCR_NORMAL_WM_SHIFT (6u) -#define BSC_CS4WCR_NORMAL_WR_SHIFT (7u) -#define BSC_CS4WCR_NORMAL_SW_SHIFT (11u) -#define BSC_CS4WCR_NORMAL_WW_SHIFT (16u) -#define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u) - -#define BSC_CS5WCR_NORMAL_HW_SHIFT (0u) -#define BSC_CS5WCR_NORMAL_WM_SHIFT (6u) -#define BSC_CS5WCR_NORMAL_WR_SHIFT (7u) -#define BSC_CS5WCR_NORMAL_SW_SHIFT (11u) -#define BSC_CS5WCR_NORMAL_WW_SHIFT (16u) -#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u) -#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u) - -#define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u) -#define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u) -#define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u) -#define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u) - -#define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u) -#define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u) -#define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u) -#define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u) -#define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u) -#define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u) - -#define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u) - -#define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u) -#define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u) -#define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u) -#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u) -#define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u) - -#define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u) -#define BSC_CS0WCR_BROM_SY_W_SHIFT (7u) -#define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u) - -#define BSC_SDCR_A3COL_SHIFT (0u) -#define BSC_SDCR_A3ROW_SHIFT (3u) -#define BSC_SDCR_BACTV_SHIFT (8u) -#define BSC_SDCR_PDOWN_SHIFT (9u) -#define BSC_SDCR_RMODE_SHIFT (10u) -#define BSC_SDCR_RFSH_SHIFT (11u) -#define BSC_SDCR_DEEP_SHIFT (13u) -#define BSC_SDCR_A2COL_SHIFT (16u) -#define BSC_SDCR_A2ROW_SHIFT (19u) - -#define BSC_RTCSR_RRC_SHIFT (0u) -#define BSC_RTCSR_CKS_SHIFT (3u) -#define BSC_RTCSR_CMIE_SHIFT (6u) -#define BSC_RTCSR_CMF_SHIFT (7u) - -#define BSC_RTCNT_D_SHIFT (0u) - -#define BSC_RTCOR_D_SHIFT (0u) - -#define BSC_TOSCOR0_D_SHIFT (0u) - -#define BSC_TOSCOR1_D_SHIFT (0u) - -#define BSC_TOSCOR2_D_SHIFT (0u) - -#define BSC_TOSCOR3_D_SHIFT (0u) - -#define BSC_TOSCOR4_D_SHIFT (0u) - -#define BSC_TOSCOR5_D_SHIFT (0u) - -#define BSC_TOSTR_CS0TOSTF_SHIFT (0u) -#define BSC_TOSTR_CS1TOSTF_SHIFT (1u) -#define BSC_TOSTR_CS2TOSTF_SHIFT (2u) -#define BSC_TOSTR_CS3TOSTF_SHIFT (3u) -#define BSC_TOSTR_CS4TOSTF_SHIFT (4u) -#define BSC_TOSTR_CS5TOSTF_SHIFT (5u) - -#define BSC_TOENR_CS0TOEN_SHIFT (0u) -#define BSC_TOENR_CS1TOEN_SHIFT (1u) -#define BSC_TOENR_CS2TOEN_SHIFT (2u) -#define BSC_TOENR_CS3TOEN_SHIFT (3u) -#define BSC_TOENR_CS4TOEN_SHIFT (4u) -#define BSC_TOENR_CS5TOEN_SHIFT (5u) - - -#endif /* BSC_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h deleted file mode 100644 index d1a7717f8a8..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h +++ /dev/null @@ -1,461 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : cpg_iobitmask.h -* $Rev: 1115 $ -* $Date:: 2014-07-09 15:35:02 +0900#$ -* Description : CPG register define header -*******************************************************************************/ -#ifndef CPG_IOBITMASK_H -#define CPG_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -#define CPG_FRQCR_IFC (0x0300u) -#define CPG_FRQCR_CKOEN (0x3000u) -#define CPG_FRQCR_CKOEN2 (0x4000u) - -#define CPG_FRQCR2_GFC (0x0003u) - -#define CPG_CPUSTS_ISBUSY (0x10u) - -#define CPG_STBCR1_DEEP (0x40u) -#define CPG_STBCR1_STBY (0x80u) - -#define CPG_STBCR2_MSTP20 (0x01u) -#define CPG_STBCR2_HIZ (0x80u) - -#define CPG_STBREQ1_STBRQ10 (0x01u) -#define CPG_STBREQ1_STBRQ12 (0x04u) -#define CPG_STBREQ1_STBRQ13 (0x08u) -#define CPG_STBREQ1_STBRQ15 (0x20u) - -#define CPG_STBREQ2_STBRQ20 (0x01u) -#define CPG_STBREQ2_STBRQ21 (0x02u) -#define CPG_STBREQ2_STBRQ22 (0x04u) -#define CPG_STBREQ2_STBRQ23 (0x08u) -#define CPG_STBREQ2_STBRQ24 (0x10u) -#define CPG_STBREQ2_STBRQ25 (0x20u) -#define CPG_STBREQ2_STBRQ26 (0x40u) -#define CPG_STBREQ2_STBRQ27 (0x80u) - -#define CPG_STBACK1_STBAK10 (0x01u) -#define CPG_STBACK1_STBAK12 (0x04u) -#define CPG_STBACK1_STBAK13 (0x08u) -#define CPG_STBACK1_STBAK15 (0x20u) - -#define CPG_STBACK2_STBAK20 (0x01u) -#define CPG_STBACK2_STBAK21 (0x02u) -#define CPG_STBACK2_STBAK22 (0x04u) -#define CPG_STBACK2_STBAK23 (0x08u) -#define CPG_STBACK2_STBAK24 (0x10u) -#define CPG_STBACK2_STBAK25 (0x20u) -#define CPG_STBACK2_STBAK26 (0x40u) -#define CPG_STBACK2_STBAK27 (0x80u) - -#define CPG_SYSCR1_VRAME0 (0x01u) -#define CPG_SYSCR1_VRAME1 (0x02u) -#define CPG_SYSCR1_VRAME2 (0x04u) -#define CPG_SYSCR1_VRAME3 (0x08u) -#define CPG_SYSCR1_VRAME4 (0x10u) - -#define CPG_SYSCR2_VRAMWE0 (0x01u) -#define CPG_SYSCR2_VRAMWE1 (0x02u) -#define CPG_SYSCR2_VRAMWE2 (0x04u) -#define CPG_SYSCR2_VRAMWE3 (0x08u) -#define CPG_SYSCR2_VRAMWE4 (0x10u) - -#define CPG_SYSCR3_RRAMWE0 (0x01u) -#define CPG_SYSCR3_RRAMWE1 (0x02u) -#define CPG_SYSCR3_RRAMWE2 (0x04u) -#define CPG_SYSCR3_RRAMWE3 (0x08u) - -#define CPG_STBCR3_MSTP30 (0x01u) -#define CPG_STBCR3_MSTP31 (0x02u) -#define CPG_STBCR3_MSTP32 (0x04u) -#define CPG_STBCR3_MSTP33 (0x08u) -#define CPG_STBCR3_MSTP34 (0x10u) -#define CPG_STBCR3_MSTP35 (0x20u) -#define CPG_STBCR3_MSTP36 (0x40u) -#define CPG_STBCR3_MSTP37 (0x80u) - -#define CPG_STBCR4_MSTP40 (0x01u) -#define CPG_STBCR4_MSTP41 (0x02u) -#define CPG_STBCR4_MSTP42 (0x04u) -#define CPG_STBCR4_MSTP43 (0x08u) -#define CPG_STBCR4_MSTP44 (0x10u) -#define CPG_STBCR4_MSTP45 (0x20u) -#define CPG_STBCR4_MSTP46 (0x40u) -#define CPG_STBCR4_MSTP47 (0x80u) - -#define CPG_STBCR5_MSTP50 (0x01u) -#define CPG_STBCR5_MSTP51 (0x02u) -#define CPG_STBCR5_MSTP52 (0x04u) -#define CPG_STBCR5_MSTP53 (0x08u) -#define CPG_STBCR5_MSTP54 (0x10u) -#define CPG_STBCR5_MSTP55 (0x20u) -#define CPG_STBCR5_MSTP56 (0x40u) -#define CPG_STBCR5_MSTP57 (0x80u) - -#define CPG_STBCR6_MSTP60 (0x01u) -#define CPG_STBCR6_MSTP61 (0x02u) -#define CPG_STBCR6_MSTP62 (0x04u) -#define CPG_STBCR6_MSTP63 (0x08u) -#define CPG_STBCR6_MSTP64 (0x10u) -#define CPG_STBCR6_MSTP65 (0x20u) -#define CPG_STBCR6_MSTP66 (0x40u) -#define CPG_STBCR6_MSTP67 (0x80u) - -#define CPG_STBCR7_MSTP70 (0x01u) -#define CPG_STBCR7_MSTP71 (0x02u) -#define CPG_STBCR7_MSTP73 (0x08u) -#define CPG_STBCR7_MSTP74 (0x10u) -#define CPG_STBCR7_MSTP76 (0x40u) -#define CPG_STBCR7_MSTP77 (0x80u) - -#define CPG_STBCR8_MSTP81 (0x02u) -#define CPG_STBCR8_MSTP82 (0x04u) -#define CPG_STBCR8_MSTP83 (0x08u) -#define CPG_STBCR8_MSTP84 (0x10u) -#define CPG_STBCR8_MSTP85 (0x20u) -#define CPG_STBCR8_MSTP86 (0x40u) -#define CPG_STBCR8_MSTP87 (0x80u) - -#define CPG_STBCR9_MSTP90 (0x01u) -#define CPG_STBCR9_MSTP91 (0x02u) -#define CPG_STBCR9_MSTP92 (0x04u) -#define CPG_STBCR9_MSTP93 (0x08u) -#define CPG_STBCR9_MSTP94 (0x10u) -#define CPG_STBCR9_MSTP95 (0x20u) -#define CPG_STBCR9_MSTP96 (0x40u) -#define CPG_STBCR9_MSTP97 (0x80u) - -#define CPG_STBCR10_MSTP100 (0x01u) -#define CPG_STBCR10_MSTP101 (0x02u) -#define CPG_STBCR10_MSTP102 (0x04u) -#define CPG_STBCR10_MSTP103 (0x08u) -#define CPG_STBCR10_MSTP104 (0x10u) -#define CPG_STBCR10_MSTP105 (0x20u) -#define CPG_STBCR10_MSTP106 (0x40u) -#define CPG_STBCR10_MSTP107 (0x80u) - -#define CPG_STBCR11_MSTP110 (0x01u) -#define CPG_STBCR11_MSTP111 (0x02u) -#define CPG_STBCR11_MSTP112 (0x04u) -#define CPG_STBCR11_MSTP113 (0x08u) -#define CPG_STBCR11_MSTP114 (0x10u) -#define CPG_STBCR11_MSTP115 (0x20u) - -#define CPG_STBCR12_MSTP120 (0x01u) -#define CPG_STBCR12_MSTP121 (0x02u) -#define CPG_STBCR12_MSTP122 (0x04u) -#define CPG_STBCR12_MSTP123 (0x08u) - -#define CPG_STBCR13_MSTP131 (0x02u) -#define CPG_STBCR13_MSTP132 (0x04u) - -#define CPG_SWRSTCR1_SRST11 (0x02u) -#define CPG_SWRSTCR1_SRST12 (0x04u) -#define CPG_SWRSTCR1_SRST13 (0x08u) -#define CPG_SWRSTCR1_SRST14 (0x10u) -#define CPG_SWRSTCR1_SRST15 (0x20u) -#define CPG_SWRSTCR1_SRST16 (0x40u) -#define CPG_SWRSTCR1_AXTALE (0x80u) - -#define CPG_SWRSTCR2_SRST21 (0x02u) - -#define CPG_SWRSTCR3_SRST32 (0x04u) - -#define CPG_RRAMKP_RRAMKP0 (0x01u) -#define CPG_RRAMKP_RRAMKP1 (0x02u) -#define CPG_RRAMKP_RRAMKP2 (0x04u) -#define CPG_RRAMKP_RRAMKP3 (0x08u) - -#define CPG_DSCTR_RAMBOOT (0x40u) -#define CPG_DSCTR_EBUSKEEPE (0x80u) - -#define CPG_DSSSR_P8_2 (0x0001u) -#define CPG_DSSSR_P9_1 (0x0002u) -#define CPG_DSSSR_P2_15 (0x0004u) -#define CPG_DSSSR_P7_8 (0x0008u) -#define CPG_DSSSR_P5_9 (0x0010u) -#define CPG_DSSSR_P6_4 (0x0020u) -#define CPG_DSSSR_RTCAR (0x0040u) -#define CPG_DSSSR_NMI (0x0100u) -#define CPG_DSSSR_P3_3 (0x0200u) -#define CPG_DSSSR_P8_7 (0x0400u) -#define CPG_DSSSR_P2_12 (0x0800u) -#define CPG_DSSSR_P3_1 (0x1000u) -#define CPG_DSSSR_P3_9 (0x2000u) -#define CPG_DSSSR_P6_2 (0x4000u) - -#define CPG_DSESR_P8_2E (0x0001u) -#define CPG_DSESR_P9_1E (0x0002u) -#define CPG_DSESR_P2_15E (0x0004u) -#define CPG_DSESR_P7_8E (0x0008u) -#define CPG_DSESR_P5_9E (0x0010u) -#define CPG_DSESR_P6_4E (0x0020u) -#define CPG_DSESR_NMIE (0x0100u) -#define CPG_DSESR_P3_3E (0x0200u) -#define CPG_DSESR_P8_7E (0x0400u) -#define CPG_DSESR_P2_12E (0x0800u) -#define CPG_DSESR_P3_1E (0x1000u) -#define CPG_DSESR_P3_9E (0x2000u) -#define CPG_DSESR_P6_2E (0x4000u) - -#define CPG_DSFR_P8_2F (0x0001u) -#define CPG_DSFR_P9_1F (0x0002u) -#define CPG_DSFR_P2_15F (0x0004u) -#define CPG_DSFR_P7_8F (0x0008u) -#define CPG_DSFR_P5_9F (0x0010u) -#define CPG_DSFR_P6_4F (0x0020u) -#define CPG_DSFR_RTCARF (0x0040u) -#define CPG_DSFR_NMIF (0x0100u) -#define CPG_DSFR_P3_3F (0x0200u) -#define CPG_DSFR_P8_7F (0x0400u) -#define CPG_DSFR_P2_12F (0x0800u) -#define CPG_DSFR_P3_1F (0x1000u) -#define CPG_DSFR_P3_9F (0x2000u) -#define CPG_DSFR_P6_2F (0x4000u) -#define CPG_DSFR_IOKEEP (0x8000u) - -#define CPG_XTALCTR_GAIN0 (0x01u) -#define CPG_XTALCTR_GAIN1 (0x02u) - - -/* ==== Shift values for IO registers ==== */ -#define CPG_FRQCR_IFC_SHIFT (8u) -#define CPG_FRQCR_CKOEN_SHIFT (12u) -#define CPG_FRQCR_CKOEN2_SHIFT (14u) - -#define CPG_FRQCR2_GFC_SHIFT (0u) - -#define CPG_CPUSTS_ISBUSY_SHIFT (4u) - -#define CPG_STBCR1_DEEP_SHIFT (6u) -#define CPG_STBCR1_STBY_SHIFT (7u) - -#define CPG_STBCR2_MSTP20_SHIFT (0u) -#define CPG_STBCR2_HIZ_SHIFT (7u) - -#define CPG_STBREQ1_STBRQ10_SHIFT (0u) -#define CPG_STBREQ1_STBRQ12_SHIFT (2u) -#define CPG_STBREQ1_STBRQ13_SHIFT (3u) -#define CPG_STBREQ1_STBRQ15_SHIFT (5u) - -#define CPG_STBREQ2_STBRQ20_SHIFT (0u) -#define CPG_STBREQ2_STBRQ21_SHIFT (1u) -#define CPG_STBREQ2_STBRQ22_SHIFT (2u) -#define CPG_STBREQ2_STBRQ23_SHIFT (3u) -#define CPG_STBREQ2_STBRQ24_SHIFT (4u) -#define CPG_STBREQ2_STBRQ25_SHIFT (5u) -#define CPG_STBREQ2_STBRQ26_SHIFT (6u) -#define CPG_STBREQ2_STBRQ27_SHIFT (7u) - -#define CPG_STBACK1_STBAK10_SHIFT (0u) -#define CPG_STBACK1_STBAK12_SHIFT (2u) -#define CPG_STBACK1_STBAK13_SHIFT (3u) -#define CPG_STBACK1_STBAK15_SHIFT (5u) - -#define CPG_STBACK2_STBAK20_SHIFT (0u) -#define CPG_STBACK2_STBAK21_SHIFT (1u) -#define CPG_STBACK2_STBAK22_SHIFT (2u) -#define CPG_STBACK2_STBAK23_SHIFT (3u) -#define CPG_STBACK2_STBAK24_SHIFT (4u) -#define CPG_STBACK2_STBAK25_SHIFT (5u) -#define CPG_STBACK2_STBAK26_SHIFT (6u) -#define CPG_STBACK2_STBAK27_SHIFT (7u) - -#define CPG_SYSCR1_VRAME0_SHIFT (0u) -#define CPG_SYSCR1_VRAME1_SHIFT (1u) -#define CPG_SYSCR1_VRAME2_SHIFT (2u) -#define CPG_SYSCR1_VRAME3_SHIFT (3u) -#define CPG_SYSCR1_VRAME4_SHIFT (4u) - -#define CPG_SYSCR2_VRAMWE0_SHIFT (0u) -#define CPG_SYSCR2_VRAMWE1_SHIFT (1u) -#define CPG_SYSCR2_VRAMWE2_SHIFT (2u) -#define CPG_SYSCR2_VRAMWE3_SHIFT (3u) -#define CPG_SYSCR2_VRAMWE4_SHIFT (4u) - -#define CPG_SYSCR3_RRAMWE0_SHIFT (0u) -#define CPG_SYSCR3_RRAMWE1_SHIFT (1u) -#define CPG_SYSCR3_RRAMWE2_SHIFT (2u) -#define CPG_SYSCR3_RRAMWE3_SHIFT (3u) - -#define CPG_STBCR3_MSTP30_SHIFT (0u) -#define CPG_STBCR3_MSTP31_SHIFT (1u) -#define CPG_STBCR3_MSTP32_SHIFT (2u) -#define CPG_STBCR3_MSTP33_SHIFT (3u) -#define CPG_STBCR3_MSTP34_SHIFT (4u) -#define CPG_STBCR3_MSTP35_SHIFT (5u) -#define CPG_STBCR3_MSTP36_SHIFT (6u) -#define CPG_STBCR3_MSTP37_SHIFT (7u) - -#define CPG_STBCR4_MSTP40_SHIFT (0u) -#define CPG_STBCR4_MSTP41_SHIFT (1u) -#define CPG_STBCR4_MSTP42_SHIFT (2u) -#define CPG_STBCR4_MSTP43_SHIFT (3u) -#define CPG_STBCR4_MSTP44_SHIFT (4u) -#define CPG_STBCR4_MSTP45_SHIFT (5u) -#define CPG_STBCR4_MSTP46_SHIFT (6u) -#define CPG_STBCR4_MSTP47_SHIFT (7u) - -#define CPG_STBCR5_MSTP50_SHIFT (0u) -#define CPG_STBCR5_MSTP51_SHIFT (1u) -#define CPG_STBCR5_MSTP52_SHIFT (2u) -#define CPG_STBCR5_MSTP53_SHIFT (3u) -#define CPG_STBCR5_MSTP54_SHIFT (4u) -#define CPG_STBCR5_MSTP55_SHIFT (5u) -#define CPG_STBCR5_MSTP56_SHIFT (6u) -#define CPG_STBCR5_MSTP57_SHIFT (7u) - -#define CPG_STBCR6_MSTP60_SHIFT (0u) -#define CPG_STBCR6_MSTP61_SHIFT (1u) -#define CPG_STBCR6_MSTP62_SHIFT (2u) -#define CPG_STBCR6_MSTP63_SHIFT (3u) -#define CPG_STBCR6_MSTP64_SHIFT (4u) -#define CPG_STBCR6_MSTP65_SHIFT (5u) -#define CPG_STBCR6_MSTP66_SHIFT (6u) -#define CPG_STBCR6_MSTP67_SHIFT (7u) - -#define CPG_STBCR7_MSTP70_SHIFT (0u) -#define CPG_STBCR7_MSTP71_SHIFT (1u) -#define CPG_STBCR7_MSTP73_SHIFT (3u) -#define CPG_STBCR7_MSTP74_SHIFT (4u) -#define CPG_STBCR7_MSTP76_SHIFT (6u) -#define CPG_STBCR7_MSTP77_SHIFT (7u) - -#define CPG_STBCR8_MSTP81_SHIFT (1u) -#define CPG_STBCR8_MSTP82_SHIFT (2u) -#define CPG_STBCR8_MSTP83_SHIFT (3u) -#define CPG_STBCR8_MSTP84_SHIFT (4u) -#define CPG_STBCR8_MSTP85_SHIFT (5u) -#define CPG_STBCR8_MSTP86_SHIFT (6u) -#define CPG_STBCR8_MSTP87_SHIFT (7u) - -#define CPG_STBCR9_MSTP90_SHIFT (0u) -#define CPG_STBCR9_MSTP91_SHIFT (1u) -#define CPG_STBCR9_MSTP92_SHIFT (2u) -#define CPG_STBCR9_MSTP93_SHIFT (3u) -#define CPG_STBCR9_MSTP94_SHIFT (4u) -#define CPG_STBCR9_MSTP95_SHIFT (5u) -#define CPG_STBCR9_MSTP96_SHIFT (6u) -#define CPG_STBCR9_MSTP97_SHIFT (7u) - -#define CPG_STBCR10_MSTP100_SHIFT (0u) -#define CPG_STBCR10_MSTP101_SHIFT (1u) -#define CPG_STBCR10_MSTP102_SHIFT (2u) -#define CPG_STBCR10_MSTP103_SHIFT (3u) -#define CPG_STBCR10_MSTP104_SHIFT (4u) -#define CPG_STBCR10_MSTP105_SHIFT (5u) -#define CPG_STBCR10_MSTP106_SHIFT (6u) -#define CPG_STBCR10_MSTP107_SHIFT (7u) - -#define CPG_STBCR11_MSTP110_SHIFT (0u) -#define CPG_STBCR11_MSTP111_SHIFT (1u) -#define CPG_STBCR11_MSTP112_SHIFT (2u) -#define CPG_STBCR11_MSTP113_SHIFT (3u) -#define CPG_STBCR11_MSTP114_SHIFT (4u) -#define CPG_STBCR11_MSTP115_SHIFT (5u) - -#define CPG_STBCR12_MSTP120_SHIFT (0u) -#define CPG_STBCR12_MSTP121_SHIFT (1u) -#define CPG_STBCR12_MSTP122_SHIFT (2u) -#define CPG_STBCR12_MSTP123_SHIFT (3u) - -#define CPG_STBCR13_MSTP131_SHIFT (1u) -#define CPG_STBCR13_MSTP132_SHIFT (2u) - -#define CPG_SWRSTCR1_SRST11_SHIFT (1u) -#define CPG_SWRSTCR1_SRST12_SHIFT (2u) -#define CPG_SWRSTCR1_SRST13_SHIFT (3u) -#define CPG_SWRSTCR1_SRST14_SHIFT (4u) -#define CPG_SWRSTCR1_SRST15_SHIFT (5u) -#define CPG_SWRSTCR1_SRST16_SHIFT (6u) -#define CPG_SWRSTCR1_AXTALE_SHIFT (7u) - -#define CPG_SWRSTCR2_SRST21_SHIFT (1u) - -#define CPG_SWRSTCR3_SRST32_SHIFT (2u) - -#define CPG_RRAMKP_RRAMKP0_SHIFT (0u) -#define CPG_RRAMKP_RRAMKP1_SHIFT (1u) -#define CPG_RRAMKP_RRAMKP2_SHIFT (2u) -#define CPG_RRAMKP_RRAMKP3_SHIFT (3u) - -#define CPG_DSCTR_RAMBOOT_SHIFT (6u) -#define CPG_DSCTR_EBUSKEEPE_SHIFT (7u) - -#define CPG_DSSSR_P8_2_SHIFT (0u) -#define CPG_DSSSR_P9_1_SHIFT (1u) -#define CPG_DSSSR_P2_15_SHIFT (2u) -#define CPG_DSSSR_P7_8_SHIFT (3u) -#define CPG_DSSSR_P5_9_SHIFT (4u) -#define CPG_DSSSR_P6_4_SHIFT (5u) -#define CPG_DSSSR_RTCAR_SHIFT (6u) -#define CPG_DSSSR_NMI_SHIFT (8u) -#define CPG_DSSSR_P3_3_SHIFT (9u) -#define CPG_DSSSR_P8_7_SHIFT (10u) -#define CPG_DSSSR_P2_12_SHIFT (11u) -#define CPG_DSSSR_P3_1_SHIFT (12u) -#define CPG_DSSSR_P3_9_SHIFT (13u) -#define CPG_DSSSR_P6_2_SHIFT (14u) - -#define CPG_DSESR_P8_2E_SHIFT (0u) -#define CPG_DSESR_P9_1E_SHIFT (1u) -#define CPG_DSESR_P2_15E_SHIFT (2u) -#define CPG_DSESR_P7_8E_SHIFT (3u) -#define CPG_DSESR_P5_9E_SHIFT (4u) -#define CPG_DSESR_P6_4E_SHIFT (5u) -#define CPG_DSESR_NMIE_SHIFT (8u) -#define CPG_DSESR_P3_3E_SHIFT (9u) -#define CPG_DSESR_P8_7E_SHIFT (10u) -#define CPG_DSESR_P2_12E_SHIFT (11u) -#define CPG_DSESR_P3_1E_SHIFT (12u) -#define CPG_DSESR_P3_9E_SHIFT (13u) -#define CPG_DSESR_P6_2E_SHIFT (14u) - -#define CPG_DSFR_P8_2F_SHIFT (0u) -#define CPG_DSFR_P9_1F_SHIFT (1u) -#define CPG_DSFR_P2_15F_SHIFT (2u) -#define CPG_DSFR_P7_8F_SHIFT (3u) -#define CPG_DSFR_P5_9F_SHIFT (4u) -#define CPG_DSFR_P6_4F_SHIFT (5u) -#define CPG_DSFR_RTCARF_SHIFT (6u) -#define CPG_DSFR_NMIF_SHIFT (8u) -#define CPG_DSFR_P3_3F_SHIFT (9u) -#define CPG_DSFR_P8_7F_SHIFT (10u) -#define CPG_DSFR_P2_12F_SHIFT (11u) -#define CPG_DSFR_P3_1F_SHIFT (12u) -#define CPG_DSFR_P3_9F_SHIFT (13u) -#define CPG_DSFR_P6_2F_SHIFT (14u) -#define CPG_DSFR_IOKEEP_SHIFT (15u) - -#define CPG_XTALCTR_GAIN0_SHIFT (0u) -#define CPG_XTALCTR_GAIN1_SHIFT (1u) - - -#endif /* CPG_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h deleted file mode 100644 index 559a060a527..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h +++ /dev/null @@ -1,2675 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : dmac_iobitmask.h -* $Rev: 1114 $ -* $Date:: 2014-07-09 14:56:39 +0900#$ -* Description : DMAC register define header -*******************************************************************************/ -#ifndef DMAC_IOBITMASK_H -#define DMAC_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -/* ---- DMAC0 ---- */ -#define DMAC0_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC0_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC0_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC0_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC0_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC0_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC0_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC0_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC0_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC0_CHSTAT_n_EN (0x00000001uL) -#define DMAC0_CHSTAT_n_RQST (0x00000002uL) -#define DMAC0_CHSTAT_n_TACT (0x00000004uL) -#define DMAC0_CHSTAT_n_SUS (0x00000008uL) -#define DMAC0_CHSTAT_n_ER (0x00000010uL) -#define DMAC0_CHSTAT_n_END (0x00000020uL) -#define DMAC0_CHSTAT_n_TC (0x00000040uL) -#define DMAC0_CHSTAT_n_SR (0x00000080uL) -#define DMAC0_CHSTAT_n_DL (0x00000100uL) -#define DMAC0_CHSTAT_n_DW (0x00000200uL) -#define DMAC0_CHSTAT_n_DER (0x00000400uL) -#define DMAC0_CHSTAT_n_MODE (0x00000800uL) -#define DMAC0_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC0_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC0_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC0_CHCTRL_n_STG (0x00000004uL) -#define DMAC0_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC0_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC0_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC0_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC0_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC0_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC0_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC0_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC0_CHCFG_n_SEL (0x00000007uL) -#define DMAC0_CHCFG_n_REQD (0x00000008uL) -#define DMAC0_CHCFG_n_LOEN (0x00000010uL) -#define DMAC0_CHCFG_n_HIEN (0x00000020uL) -#define DMAC0_CHCFG_n_LVL (0x00000040uL) -#define DMAC0_CHCFG_n_AM (0x00000700uL) -#define DMAC0_CHCFG_n_SDS (0x0000F000uL) -#define DMAC0_CHCFG_n_DDS (0x000F0000uL) -#define DMAC0_CHCFG_n_SAD (0x00100000uL) -#define DMAC0_CHCFG_n_DAD (0x00200000uL) -#define DMAC0_CHCFG_n_TM (0x00400000uL) -#define DMAC0_CHCFG_n_DEM (0x01000000uL) -#define DMAC0_CHCFG_n_TCM (0x02000000uL) -#define DMAC0_CHCFG_n_SBE (0x08000000uL) -#define DMAC0_CHCFG_n_RSEL (0x10000000uL) -#define DMAC0_CHCFG_n_RSW (0x20000000uL) -#define DMAC0_CHCFG_n_REN (0x40000000uL) -#define DMAC0_CHCFG_n_DMS (0x80000000uL) - -#define DMAC0_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC0_CHEXT_n_SCA (0x000000F0uL) -#define DMAC0_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC0_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC0_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC1 ---- */ -#define DMAC1_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC1_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC1_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC1_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC1_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC1_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC1_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC1_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC1_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC1_CHSTAT_n_EN (0x00000001uL) -#define DMAC1_CHSTAT_n_RQST (0x00000002uL) -#define DMAC1_CHSTAT_n_TACT (0x00000004uL) -#define DMAC1_CHSTAT_n_SUS (0x00000008uL) -#define DMAC1_CHSTAT_n_ER (0x00000010uL) -#define DMAC1_CHSTAT_n_END (0x00000020uL) -#define DMAC1_CHSTAT_n_TC (0x00000040uL) -#define DMAC1_CHSTAT_n_SR (0x00000080uL) -#define DMAC1_CHSTAT_n_DL (0x00000100uL) -#define DMAC1_CHSTAT_n_DW (0x00000200uL) -#define DMAC1_CHSTAT_n_DER (0x00000400uL) -#define DMAC1_CHSTAT_n_MODE (0x00000800uL) -#define DMAC1_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC1_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC1_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC1_CHCTRL_n_STG (0x00000004uL) -#define DMAC1_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC1_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC1_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC1_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC1_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC1_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC1_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC1_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC1_CHCFG_n_SEL (0x00000007uL) -#define DMAC1_CHCFG_n_REQD (0x00000008uL) -#define DMAC1_CHCFG_n_LOEN (0x00000010uL) -#define DMAC1_CHCFG_n_HIEN (0x00000020uL) -#define DMAC1_CHCFG_n_LVL (0x00000040uL) -#define DMAC1_CHCFG_n_AM (0x00000700uL) -#define DMAC1_CHCFG_n_SDS (0x0000F000uL) -#define DMAC1_CHCFG_n_DDS (0x000F0000uL) -#define DMAC1_CHCFG_n_SAD (0x00100000uL) -#define DMAC1_CHCFG_n_DAD (0x00200000uL) -#define DMAC1_CHCFG_n_TM (0x00400000uL) -#define DMAC1_CHCFG_n_DEM (0x01000000uL) -#define DMAC1_CHCFG_n_TCM (0x02000000uL) -#define DMAC1_CHCFG_n_SBE (0x08000000uL) -#define DMAC1_CHCFG_n_RSEL (0x10000000uL) -#define DMAC1_CHCFG_n_RSW (0x20000000uL) -#define DMAC1_CHCFG_n_REN (0x40000000uL) -#define DMAC1_CHCFG_n_DMS (0x80000000uL) - -#define DMAC1_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC1_CHEXT_n_SCA (0x000000F0uL) -#define DMAC1_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC1_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC1_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC2 ---- */ -#define DMAC2_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC2_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC2_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC2_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC2_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC2_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC2_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC2_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC2_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC2_CHSTAT_n_EN (0x00000001uL) -#define DMAC2_CHSTAT_n_RQST (0x00000002uL) -#define DMAC2_CHSTAT_n_TACT (0x00000004uL) -#define DMAC2_CHSTAT_n_SUS (0x00000008uL) -#define DMAC2_CHSTAT_n_ER (0x00000010uL) -#define DMAC2_CHSTAT_n_END (0x00000020uL) -#define DMAC2_CHSTAT_n_TC (0x00000040uL) -#define DMAC2_CHSTAT_n_SR (0x00000080uL) -#define DMAC2_CHSTAT_n_DL (0x00000100uL) -#define DMAC2_CHSTAT_n_DW (0x00000200uL) -#define DMAC2_CHSTAT_n_DER (0x00000400uL) -#define DMAC2_CHSTAT_n_MODE (0x00000800uL) -#define DMAC2_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC2_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC2_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC2_CHCTRL_n_STG (0x00000004uL) -#define DMAC2_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC2_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC2_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC2_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC2_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC2_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC2_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC2_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC2_CHCFG_n_SEL (0x00000007uL) -#define DMAC2_CHCFG_n_REQD (0x00000008uL) -#define DMAC2_CHCFG_n_LOEN (0x00000010uL) -#define DMAC2_CHCFG_n_HIEN (0x00000020uL) -#define DMAC2_CHCFG_n_LVL (0x00000040uL) -#define DMAC2_CHCFG_n_AM (0x00000700uL) -#define DMAC2_CHCFG_n_SDS (0x0000F000uL) -#define DMAC2_CHCFG_n_DDS (0x000F0000uL) -#define DMAC2_CHCFG_n_SAD (0x00100000uL) -#define DMAC2_CHCFG_n_DAD (0x00200000uL) -#define DMAC2_CHCFG_n_TM (0x00400000uL) -#define DMAC2_CHCFG_n_DEM (0x01000000uL) -#define DMAC2_CHCFG_n_TCM (0x02000000uL) -#define DMAC2_CHCFG_n_SBE (0x08000000uL) -#define DMAC2_CHCFG_n_RSEL (0x10000000uL) -#define DMAC2_CHCFG_n_RSW (0x20000000uL) -#define DMAC2_CHCFG_n_REN (0x40000000uL) -#define DMAC2_CHCFG_n_DMS (0x80000000uL) - -#define DMAC2_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC2_CHEXT_n_SCA (0x000000F0uL) -#define DMAC2_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC2_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC2_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC3 ---- */ -#define DMAC3_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC3_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC3_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC3_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC3_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC3_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC3_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC3_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC3_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC3_CHSTAT_n_EN (0x00000001uL) -#define DMAC3_CHSTAT_n_RQST (0x00000002uL) -#define DMAC3_CHSTAT_n_TACT (0x00000004uL) -#define DMAC3_CHSTAT_n_SUS (0x00000008uL) -#define DMAC3_CHSTAT_n_ER (0x00000010uL) -#define DMAC3_CHSTAT_n_END (0x00000020uL) -#define DMAC3_CHSTAT_n_TC (0x00000040uL) -#define DMAC3_CHSTAT_n_SR (0x00000080uL) -#define DMAC3_CHSTAT_n_DL (0x00000100uL) -#define DMAC3_CHSTAT_n_DW (0x00000200uL) -#define DMAC3_CHSTAT_n_DER (0x00000400uL) -#define DMAC3_CHSTAT_n_MODE (0x00000800uL) -#define DMAC3_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC3_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC3_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC3_CHCTRL_n_STG (0x00000004uL) -#define DMAC3_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC3_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC3_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC3_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC3_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC3_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC3_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC3_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC3_CHCFG_n_SEL (0x00000007uL) -#define DMAC3_CHCFG_n_REQD (0x00000008uL) -#define DMAC3_CHCFG_n_LOEN (0x00000010uL) -#define DMAC3_CHCFG_n_HIEN (0x00000020uL) -#define DMAC3_CHCFG_n_LVL (0x00000040uL) -#define DMAC3_CHCFG_n_AM (0x00000700uL) -#define DMAC3_CHCFG_n_SDS (0x0000F000uL) -#define DMAC3_CHCFG_n_DDS (0x000F0000uL) -#define DMAC3_CHCFG_n_SAD (0x00100000uL) -#define DMAC3_CHCFG_n_DAD (0x00200000uL) -#define DMAC3_CHCFG_n_TM (0x00400000uL) -#define DMAC3_CHCFG_n_DEM (0x01000000uL) -#define DMAC3_CHCFG_n_TCM (0x02000000uL) -#define DMAC3_CHCFG_n_SBE (0x08000000uL) -#define DMAC3_CHCFG_n_RSEL (0x10000000uL) -#define DMAC3_CHCFG_n_RSW (0x20000000uL) -#define DMAC3_CHCFG_n_REN (0x40000000uL) -#define DMAC3_CHCFG_n_DMS (0x80000000uL) - -#define DMAC3_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC3_CHEXT_n_SCA (0x000000F0uL) -#define DMAC3_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC3_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC3_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC4 ---- */ -#define DMAC4_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC4_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC4_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC4_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC4_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC4_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC4_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC4_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC4_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC4_CHSTAT_n_EN (0x00000001uL) -#define DMAC4_CHSTAT_n_RQST (0x00000002uL) -#define DMAC4_CHSTAT_n_TACT (0x00000004uL) -#define DMAC4_CHSTAT_n_SUS (0x00000008uL) -#define DMAC4_CHSTAT_n_ER (0x00000010uL) -#define DMAC4_CHSTAT_n_END (0x00000020uL) -#define DMAC4_CHSTAT_n_TC (0x00000040uL) -#define DMAC4_CHSTAT_n_SR (0x00000080uL) -#define DMAC4_CHSTAT_n_DL (0x00000100uL) -#define DMAC4_CHSTAT_n_DW (0x00000200uL) -#define DMAC4_CHSTAT_n_DER (0x00000400uL) -#define DMAC4_CHSTAT_n_MODE (0x00000800uL) -#define DMAC4_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC4_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC4_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC4_CHCTRL_n_STG (0x00000004uL) -#define DMAC4_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC4_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC4_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC4_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC4_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC4_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC4_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC4_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC4_CHCFG_n_SEL (0x00000007uL) -#define DMAC4_CHCFG_n_REQD (0x00000008uL) -#define DMAC4_CHCFG_n_LOEN (0x00000010uL) -#define DMAC4_CHCFG_n_HIEN (0x00000020uL) -#define DMAC4_CHCFG_n_LVL (0x00000040uL) -#define DMAC4_CHCFG_n_AM (0x00000700uL) -#define DMAC4_CHCFG_n_SDS (0x0000F000uL) -#define DMAC4_CHCFG_n_DDS (0x000F0000uL) -#define DMAC4_CHCFG_n_SAD (0x00100000uL) -#define DMAC4_CHCFG_n_DAD (0x00200000uL) -#define DMAC4_CHCFG_n_TM (0x00400000uL) -#define DMAC4_CHCFG_n_DEM (0x01000000uL) -#define DMAC4_CHCFG_n_TCM (0x02000000uL) -#define DMAC4_CHCFG_n_SBE (0x08000000uL) -#define DMAC4_CHCFG_n_RSEL (0x10000000uL) -#define DMAC4_CHCFG_n_RSW (0x20000000uL) -#define DMAC4_CHCFG_n_REN (0x40000000uL) -#define DMAC4_CHCFG_n_DMS (0x80000000uL) - -#define DMAC4_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC4_CHEXT_n_SCA (0x000000F0uL) -#define DMAC4_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC4_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC4_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC5 ---- */ -#define DMAC5_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC5_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC5_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC5_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC5_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC5_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC5_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC5_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC5_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC5_CHSTAT_n_EN (0x00000001uL) -#define DMAC5_CHSTAT_n_RQST (0x00000002uL) -#define DMAC5_CHSTAT_n_TACT (0x00000004uL) -#define DMAC5_CHSTAT_n_SUS (0x00000008uL) -#define DMAC5_CHSTAT_n_ER (0x00000010uL) -#define DMAC5_CHSTAT_n_END (0x00000020uL) -#define DMAC5_CHSTAT_n_TC (0x00000040uL) -#define DMAC5_CHSTAT_n_SR (0x00000080uL) -#define DMAC5_CHSTAT_n_DL (0x00000100uL) -#define DMAC5_CHSTAT_n_DW (0x00000200uL) -#define DMAC5_CHSTAT_n_DER (0x00000400uL) -#define DMAC5_CHSTAT_n_MODE (0x00000800uL) -#define DMAC5_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC5_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC5_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC5_CHCTRL_n_STG (0x00000004uL) -#define DMAC5_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC5_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC5_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC5_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC5_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC5_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC5_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC5_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC5_CHCFG_n_SEL (0x00000007uL) -#define DMAC5_CHCFG_n_REQD (0x00000008uL) -#define DMAC5_CHCFG_n_LOEN (0x00000010uL) -#define DMAC5_CHCFG_n_HIEN (0x00000020uL) -#define DMAC5_CHCFG_n_LVL (0x00000040uL) -#define DMAC5_CHCFG_n_AM (0x00000700uL) -#define DMAC5_CHCFG_n_SDS (0x0000F000uL) -#define DMAC5_CHCFG_n_DDS (0x000F0000uL) -#define DMAC5_CHCFG_n_SAD (0x00100000uL) -#define DMAC5_CHCFG_n_DAD (0x00200000uL) -#define DMAC5_CHCFG_n_TM (0x00400000uL) -#define DMAC5_CHCFG_n_DEM (0x01000000uL) -#define DMAC5_CHCFG_n_TCM (0x02000000uL) -#define DMAC5_CHCFG_n_SBE (0x08000000uL) -#define DMAC5_CHCFG_n_RSEL (0x10000000uL) -#define DMAC5_CHCFG_n_RSW (0x20000000uL) -#define DMAC5_CHCFG_n_REN (0x40000000uL) -#define DMAC5_CHCFG_n_DMS (0x80000000uL) - -#define DMAC5_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC5_CHEXT_n_SCA (0x000000F0uL) -#define DMAC5_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC5_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC5_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC6 ---- */ -#define DMAC6_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC6_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC6_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC6_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC6_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC6_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC6_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC6_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC6_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC6_CHSTAT_n_EN (0x00000001uL) -#define DMAC6_CHSTAT_n_RQST (0x00000002uL) -#define DMAC6_CHSTAT_n_TACT (0x00000004uL) -#define DMAC6_CHSTAT_n_SUS (0x00000008uL) -#define DMAC6_CHSTAT_n_ER (0x00000010uL) -#define DMAC6_CHSTAT_n_END (0x00000020uL) -#define DMAC6_CHSTAT_n_TC (0x00000040uL) -#define DMAC6_CHSTAT_n_SR (0x00000080uL) -#define DMAC6_CHSTAT_n_DL (0x00000100uL) -#define DMAC6_CHSTAT_n_DW (0x00000200uL) -#define DMAC6_CHSTAT_n_DER (0x00000400uL) -#define DMAC6_CHSTAT_n_MODE (0x00000800uL) -#define DMAC6_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC6_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC6_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC6_CHCTRL_n_STG (0x00000004uL) -#define DMAC6_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC6_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC6_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC6_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC6_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC6_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC6_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC6_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC6_CHCFG_n_SEL (0x00000007uL) -#define DMAC6_CHCFG_n_REQD (0x00000008uL) -#define DMAC6_CHCFG_n_LOEN (0x00000010uL) -#define DMAC6_CHCFG_n_HIEN (0x00000020uL) -#define DMAC6_CHCFG_n_LVL (0x00000040uL) -#define DMAC6_CHCFG_n_AM (0x00000700uL) -#define DMAC6_CHCFG_n_SDS (0x0000F000uL) -#define DMAC6_CHCFG_n_DDS (0x000F0000uL) -#define DMAC6_CHCFG_n_SAD (0x00100000uL) -#define DMAC6_CHCFG_n_DAD (0x00200000uL) -#define DMAC6_CHCFG_n_TM (0x00400000uL) -#define DMAC6_CHCFG_n_DEM (0x01000000uL) -#define DMAC6_CHCFG_n_TCM (0x02000000uL) -#define DMAC6_CHCFG_n_SBE (0x08000000uL) -#define DMAC6_CHCFG_n_RSEL (0x10000000uL) -#define DMAC6_CHCFG_n_RSW (0x20000000uL) -#define DMAC6_CHCFG_n_REN (0x40000000uL) -#define DMAC6_CHCFG_n_DMS (0x80000000uL) - -#define DMAC6_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC6_CHEXT_n_SCA (0x000000F0uL) -#define DMAC6_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC6_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC6_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC7 ---- */ -#define DMAC7_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC7_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC7_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC7_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC7_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC7_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC7_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC7_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC7_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC7_CHSTAT_n_EN (0x00000001uL) -#define DMAC7_CHSTAT_n_RQST (0x00000002uL) -#define DMAC7_CHSTAT_n_TACT (0x00000004uL) -#define DMAC7_CHSTAT_n_SUS (0x00000008uL) -#define DMAC7_CHSTAT_n_ER (0x00000010uL) -#define DMAC7_CHSTAT_n_END (0x00000020uL) -#define DMAC7_CHSTAT_n_TC (0x00000040uL) -#define DMAC7_CHSTAT_n_SR (0x00000080uL) -#define DMAC7_CHSTAT_n_DL (0x00000100uL) -#define DMAC7_CHSTAT_n_DW (0x00000200uL) -#define DMAC7_CHSTAT_n_DER (0x00000400uL) -#define DMAC7_CHSTAT_n_MODE (0x00000800uL) -#define DMAC7_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC7_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC7_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC7_CHCTRL_n_STG (0x00000004uL) -#define DMAC7_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC7_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC7_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC7_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC7_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC7_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC7_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC7_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC7_CHCFG_n_SEL (0x00000007uL) -#define DMAC7_CHCFG_n_REQD (0x00000008uL) -#define DMAC7_CHCFG_n_LOEN (0x00000010uL) -#define DMAC7_CHCFG_n_HIEN (0x00000020uL) -#define DMAC7_CHCFG_n_LVL (0x00000040uL) -#define DMAC7_CHCFG_n_AM (0x00000700uL) -#define DMAC7_CHCFG_n_SDS (0x0000F000uL) -#define DMAC7_CHCFG_n_DDS (0x000F0000uL) -#define DMAC7_CHCFG_n_SAD (0x00100000uL) -#define DMAC7_CHCFG_n_DAD (0x00200000uL) -#define DMAC7_CHCFG_n_TM (0x00400000uL) -#define DMAC7_CHCFG_n_DEM (0x01000000uL) -#define DMAC7_CHCFG_n_TCM (0x02000000uL) -#define DMAC7_CHCFG_n_SBE (0x08000000uL) -#define DMAC7_CHCFG_n_RSEL (0x10000000uL) -#define DMAC7_CHCFG_n_RSW (0x20000000uL) -#define DMAC7_CHCFG_n_REN (0x40000000uL) -#define DMAC7_CHCFG_n_DMS (0x80000000uL) - -#define DMAC7_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC7_CHEXT_n_SCA (0x000000F0uL) -#define DMAC7_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC7_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC7_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC0-7 ---- */ -#define DMAC07_DCTRL_0_7_PR (0x00000001uL) -#define DMAC07_DCTRL_0_7_LVINT (0x00000002uL) -#define DMAC07_DCTRL_0_7_LDCA (0x0000003CuL) -#define DMAC07_DCTRL_0_7_LWCA (0x000003C0uL) - -#define DMAC07_DSTAT_EN_0_7_EN0 (0x00000001uL) -#define DMAC07_DSTAT_EN_0_7_EN1 (0x00000002uL) -#define DMAC07_DSTAT_EN_0_7_EN2 (0x00000004uL) -#define DMAC07_DSTAT_EN_0_7_EN3 (0x00000008uL) -#define DMAC07_DSTAT_EN_0_7_EN4 (0x00000010uL) -#define DMAC07_DSTAT_EN_0_7_EN5 (0x00000020uL) -#define DMAC07_DSTAT_EN_0_7_EN6 (0x00000040uL) -#define DMAC07_DSTAT_EN_0_7_EN7 (0x00000080uL) - -#define DMAC07_DSTAT_ER_0_7_ER0 (0x00000001uL) -#define DMAC07_DSTAT_ER_0_7_ER1 (0x00000002uL) -#define DMAC07_DSTAT_ER_0_7_ER2 (0x00000004uL) -#define DMAC07_DSTAT_ER_0_7_ER3 (0x00000008uL) -#define DMAC07_DSTAT_ER_0_7_ER4 (0x00000010uL) -#define DMAC07_DSTAT_ER_0_7_ER5 (0x00000020uL) -#define DMAC07_DSTAT_ER_0_7_ER6 (0x00000040uL) -#define DMAC07_DSTAT_ER_0_7_ER7 (0x00000080uL) - -#define DMAC07_DSTAT_END_0_7_END0 (0x00000001uL) -#define DMAC07_DSTAT_END_0_7_END1 (0x00000002uL) -#define DMAC07_DSTAT_END_0_7_END2 (0x00000004uL) -#define DMAC07_DSTAT_END_0_7_END3 (0x00000008uL) -#define DMAC07_DSTAT_END_0_7_END4 (0x00000010uL) -#define DMAC07_DSTAT_END_0_7_END5 (0x00000020uL) -#define DMAC07_DSTAT_END_0_7_END6 (0x00000040uL) -#define DMAC07_DSTAT_END_0_7_END7 (0x00000080uL) - -#define DMAC07_DSTAT_TC_0_7_TC0 (0x00000001uL) -#define DMAC07_DSTAT_TC_0_7_TC1 (0x00000002uL) -#define DMAC07_DSTAT_TC_0_7_TC2 (0x00000004uL) -#define DMAC07_DSTAT_TC_0_7_TC3 (0x00000008uL) -#define DMAC07_DSTAT_TC_0_7_TC4 (0x00000010uL) -#define DMAC07_DSTAT_TC_0_7_TC5 (0x00000020uL) -#define DMAC07_DSTAT_TC_0_7_TC6 (0x00000040uL) -#define DMAC07_DSTAT_TC_0_7_TC7 (0x00000080uL) - -#define DMAC07_DSTAT_SUS_0_7_SUS0 (0x00000001uL) -#define DMAC07_DSTAT_SUS_0_7_SUS1 (0x00000002uL) -#define DMAC07_DSTAT_SUS_0_7_SUS2 (0x00000004uL) -#define DMAC07_DSTAT_SUS_0_7_SUS3 (0x00000008uL) -#define DMAC07_DSTAT_SUS_0_7_SUS4 (0x00000010uL) -#define DMAC07_DSTAT_SUS_0_7_SUS5 (0x00000020uL) -#define DMAC07_DSTAT_SUS_0_7_SUS6 (0x00000040uL) -#define DMAC07_DSTAT_SUS_0_7_SUS7 (0x00000080uL) - -/* ---- DMAC8 ---- */ -#define DMAC8_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC8_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC8_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC8_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC8_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC8_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC8_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC8_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC8_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC8_CHSTAT_n_EN (0x00000001uL) -#define DMAC8_CHSTAT_n_RQST (0x00000002uL) -#define DMAC8_CHSTAT_n_TACT (0x00000004uL) -#define DMAC8_CHSTAT_n_SUS (0x00000008uL) -#define DMAC8_CHSTAT_n_ER (0x00000010uL) -#define DMAC8_CHSTAT_n_END (0x00000020uL) -#define DMAC8_CHSTAT_n_TC (0x00000040uL) -#define DMAC8_CHSTAT_n_SR (0x00000080uL) -#define DMAC8_CHSTAT_n_DL (0x00000100uL) -#define DMAC8_CHSTAT_n_DW (0x00000200uL) -#define DMAC8_CHSTAT_n_DER (0x00000400uL) -#define DMAC8_CHSTAT_n_MODE (0x00000800uL) -#define DMAC8_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC8_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC8_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC8_CHCTRL_n_STG (0x00000004uL) -#define DMAC8_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC8_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC8_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC8_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC8_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC8_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC8_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC8_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC8_CHCFG_n_SEL (0x00000007uL) -#define DMAC8_CHCFG_n_REQD (0x00000008uL) -#define DMAC8_CHCFG_n_LOEN (0x00000010uL) -#define DMAC8_CHCFG_n_HIEN (0x00000020uL) -#define DMAC8_CHCFG_n_LVL (0x00000040uL) -#define DMAC8_CHCFG_n_AM (0x00000700uL) -#define DMAC8_CHCFG_n_SDS (0x0000F000uL) -#define DMAC8_CHCFG_n_DDS (0x000F0000uL) -#define DMAC8_CHCFG_n_SAD (0x00100000uL) -#define DMAC8_CHCFG_n_DAD (0x00200000uL) -#define DMAC8_CHCFG_n_TM (0x00400000uL) -#define DMAC8_CHCFG_n_DEM (0x01000000uL) -#define DMAC8_CHCFG_n_TCM (0x02000000uL) -#define DMAC8_CHCFG_n_SBE (0x08000000uL) -#define DMAC8_CHCFG_n_RSEL (0x10000000uL) -#define DMAC8_CHCFG_n_RSW (0x20000000uL) -#define DMAC8_CHCFG_n_REN (0x40000000uL) -#define DMAC8_CHCFG_n_DMS (0x80000000uL) - -#define DMAC8_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC8_CHEXT_n_SCA (0x000000F0uL) -#define DMAC8_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC8_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC8_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC9 ---- */ -#define DMAC9_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC9_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC9_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC9_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC9_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC9_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC9_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC9_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC9_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC9_CHSTAT_n_EN (0x00000001uL) -#define DMAC9_CHSTAT_n_RQST (0x00000002uL) -#define DMAC9_CHSTAT_n_TACT (0x00000004uL) -#define DMAC9_CHSTAT_n_SUS (0x00000008uL) -#define DMAC9_CHSTAT_n_ER (0x00000010uL) -#define DMAC9_CHSTAT_n_END (0x00000020uL) -#define DMAC9_CHSTAT_n_TC (0x00000040uL) -#define DMAC9_CHSTAT_n_SR (0x00000080uL) -#define DMAC9_CHSTAT_n_DL (0x00000100uL) -#define DMAC9_CHSTAT_n_DW (0x00000200uL) -#define DMAC9_CHSTAT_n_DER (0x00000400uL) -#define DMAC9_CHSTAT_n_MODE (0x00000800uL) -#define DMAC9_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC9_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC9_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC9_CHCTRL_n_STG (0x00000004uL) -#define DMAC9_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC9_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC9_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC9_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC9_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC9_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC9_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC9_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC9_CHCFG_n_SEL (0x00000007uL) -#define DMAC9_CHCFG_n_REQD (0x00000008uL) -#define DMAC9_CHCFG_n_LOEN (0x00000010uL) -#define DMAC9_CHCFG_n_HIEN (0x00000020uL) -#define DMAC9_CHCFG_n_LVL (0x00000040uL) -#define DMAC9_CHCFG_n_AM (0x00000700uL) -#define DMAC9_CHCFG_n_SDS (0x0000F000uL) -#define DMAC9_CHCFG_n_DDS (0x000F0000uL) -#define DMAC9_CHCFG_n_SAD (0x00100000uL) -#define DMAC9_CHCFG_n_DAD (0x00200000uL) -#define DMAC9_CHCFG_n_TM (0x00400000uL) -#define DMAC9_CHCFG_n_DEM (0x01000000uL) -#define DMAC9_CHCFG_n_TCM (0x02000000uL) -#define DMAC9_CHCFG_n_SBE (0x08000000uL) -#define DMAC9_CHCFG_n_RSEL (0x10000000uL) -#define DMAC9_CHCFG_n_RSW (0x20000000uL) -#define DMAC9_CHCFG_n_REN (0x40000000uL) -#define DMAC9_CHCFG_n_DMS (0x80000000uL) - -#define DMAC9_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC9_CHEXT_n_SCA (0x000000F0uL) -#define DMAC9_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC9_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC9_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC10 ---- */ -#define DMAC10_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC10_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC10_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC10_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC10_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC10_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC10_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC10_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC10_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC10_CHSTAT_n_EN (0x00000001uL) -#define DMAC10_CHSTAT_n_RQST (0x00000002uL) -#define DMAC10_CHSTAT_n_TACT (0x00000004uL) -#define DMAC10_CHSTAT_n_SUS (0x00000008uL) -#define DMAC10_CHSTAT_n_ER (0x00000010uL) -#define DMAC10_CHSTAT_n_END (0x00000020uL) -#define DMAC10_CHSTAT_n_TC (0x00000040uL) -#define DMAC10_CHSTAT_n_SR (0x00000080uL) -#define DMAC10_CHSTAT_n_DL (0x00000100uL) -#define DMAC10_CHSTAT_n_DW (0x00000200uL) -#define DMAC10_CHSTAT_n_DER (0x00000400uL) -#define DMAC10_CHSTAT_n_MODE (0x00000800uL) -#define DMAC10_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC10_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC10_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC10_CHCTRL_n_STG (0x00000004uL) -#define DMAC10_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC10_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC10_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC10_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC10_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC10_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC10_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC10_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC10_CHCFG_n_SEL (0x00000007uL) -#define DMAC10_CHCFG_n_REQD (0x00000008uL) -#define DMAC10_CHCFG_n_LOEN (0x00000010uL) -#define DMAC10_CHCFG_n_HIEN (0x00000020uL) -#define DMAC10_CHCFG_n_LVL (0x00000040uL) -#define DMAC10_CHCFG_n_AM (0x00000700uL) -#define DMAC10_CHCFG_n_SDS (0x0000F000uL) -#define DMAC10_CHCFG_n_DDS (0x000F0000uL) -#define DMAC10_CHCFG_n_SAD (0x00100000uL) -#define DMAC10_CHCFG_n_DAD (0x00200000uL) -#define DMAC10_CHCFG_n_TM (0x00400000uL) -#define DMAC10_CHCFG_n_DEM (0x01000000uL) -#define DMAC10_CHCFG_n_TCM (0x02000000uL) -#define DMAC10_CHCFG_n_SBE (0x08000000uL) -#define DMAC10_CHCFG_n_RSEL (0x10000000uL) -#define DMAC10_CHCFG_n_RSW (0x20000000uL) -#define DMAC10_CHCFG_n_REN (0x40000000uL) -#define DMAC10_CHCFG_n_DMS (0x80000000uL) - -#define DMAC10_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC10_CHEXT_n_SCA (0x000000F0uL) -#define DMAC10_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC10_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC10_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC11 ---- */ -#define DMAC11_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC11_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC11_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC11_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC11_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC11_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC11_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC11_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC11_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC11_CHSTAT_n_EN (0x00000001uL) -#define DMAC11_CHSTAT_n_RQST (0x00000002uL) -#define DMAC11_CHSTAT_n_TACT (0x00000004uL) -#define DMAC11_CHSTAT_n_SUS (0x00000008uL) -#define DMAC11_CHSTAT_n_ER (0x00000010uL) -#define DMAC11_CHSTAT_n_END (0x00000020uL) -#define DMAC11_CHSTAT_n_TC (0x00000040uL) -#define DMAC11_CHSTAT_n_SR (0x00000080uL) -#define DMAC11_CHSTAT_n_DL (0x00000100uL) -#define DMAC11_CHSTAT_n_DW (0x00000200uL) -#define DMAC11_CHSTAT_n_DER (0x00000400uL) -#define DMAC11_CHSTAT_n_MODE (0x00000800uL) -#define DMAC11_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC11_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC11_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC11_CHCTRL_n_STG (0x00000004uL) -#define DMAC11_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC11_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC11_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC11_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC11_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC11_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC11_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC11_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC11_CHCFG_n_SEL (0x00000007uL) -#define DMAC11_CHCFG_n_REQD (0x00000008uL) -#define DMAC11_CHCFG_n_LOEN (0x00000010uL) -#define DMAC11_CHCFG_n_HIEN (0x00000020uL) -#define DMAC11_CHCFG_n_LVL (0x00000040uL) -#define DMAC11_CHCFG_n_AM (0x00000700uL) -#define DMAC11_CHCFG_n_SDS (0x0000F000uL) -#define DMAC11_CHCFG_n_DDS (0x000F0000uL) -#define DMAC11_CHCFG_n_SAD (0x00100000uL) -#define DMAC11_CHCFG_n_DAD (0x00200000uL) -#define DMAC11_CHCFG_n_TM (0x00400000uL) -#define DMAC11_CHCFG_n_DEM (0x01000000uL) -#define DMAC11_CHCFG_n_TCM (0x02000000uL) -#define DMAC11_CHCFG_n_SBE (0x08000000uL) -#define DMAC11_CHCFG_n_RSEL (0x10000000uL) -#define DMAC11_CHCFG_n_RSW (0x20000000uL) -#define DMAC11_CHCFG_n_REN (0x40000000uL) -#define DMAC11_CHCFG_n_DMS (0x80000000uL) - -#define DMAC11_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC11_CHEXT_n_SCA (0x000000F0uL) -#define DMAC11_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC11_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC11_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC12 ---- */ -#define DMAC12_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC12_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC12_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC12_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC12_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC12_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC12_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC12_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC12_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC12_CHSTAT_n_EN (0x00000001uL) -#define DMAC12_CHSTAT_n_RQST (0x00000002uL) -#define DMAC12_CHSTAT_n_TACT (0x00000004uL) -#define DMAC12_CHSTAT_n_SUS (0x00000008uL) -#define DMAC12_CHSTAT_n_ER (0x00000010uL) -#define DMAC12_CHSTAT_n_END (0x00000020uL) -#define DMAC12_CHSTAT_n_TC (0x00000040uL) -#define DMAC12_CHSTAT_n_SR (0x00000080uL) -#define DMAC12_CHSTAT_n_DL (0x00000100uL) -#define DMAC12_CHSTAT_n_DW (0x00000200uL) -#define DMAC12_CHSTAT_n_DER (0x00000400uL) -#define DMAC12_CHSTAT_n_MODE (0x00000800uL) -#define DMAC12_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC12_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC12_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC12_CHCTRL_n_STG (0x00000004uL) -#define DMAC12_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC12_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC12_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC12_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC12_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC12_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC12_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC12_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC12_CHCFG_n_SEL (0x00000007uL) -#define DMAC12_CHCFG_n_REQD (0x00000008uL) -#define DMAC12_CHCFG_n_LOEN (0x00000010uL) -#define DMAC12_CHCFG_n_HIEN (0x00000020uL) -#define DMAC12_CHCFG_n_LVL (0x00000040uL) -#define DMAC12_CHCFG_n_AM (0x00000700uL) -#define DMAC12_CHCFG_n_SDS (0x0000F000uL) -#define DMAC12_CHCFG_n_DDS (0x000F0000uL) -#define DMAC12_CHCFG_n_SAD (0x00100000uL) -#define DMAC12_CHCFG_n_DAD (0x00200000uL) -#define DMAC12_CHCFG_n_TM (0x00400000uL) -#define DMAC12_CHCFG_n_DEM (0x01000000uL) -#define DMAC12_CHCFG_n_TCM (0x02000000uL) -#define DMAC12_CHCFG_n_SBE (0x08000000uL) -#define DMAC12_CHCFG_n_RSEL (0x10000000uL) -#define DMAC12_CHCFG_n_RSW (0x20000000uL) -#define DMAC12_CHCFG_n_REN (0x40000000uL) -#define DMAC12_CHCFG_n_DMS (0x80000000uL) - -#define DMAC12_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC12_CHEXT_n_SCA (0x000000F0uL) -#define DMAC12_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC12_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC12_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC13 ---- */ -#define DMAC13_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC13_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC13_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC13_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC13_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC13_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC13_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC13_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC13_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC13_CHSTAT_n_EN (0x00000001uL) -#define DMAC13_CHSTAT_n_RQST (0x00000002uL) -#define DMAC13_CHSTAT_n_TACT (0x00000004uL) -#define DMAC13_CHSTAT_n_SUS (0x00000008uL) -#define DMAC13_CHSTAT_n_ER (0x00000010uL) -#define DMAC13_CHSTAT_n_END (0x00000020uL) -#define DMAC13_CHSTAT_n_TC (0x00000040uL) -#define DMAC13_CHSTAT_n_SR (0x00000080uL) -#define DMAC13_CHSTAT_n_DL (0x00000100uL) -#define DMAC13_CHSTAT_n_DW (0x00000200uL) -#define DMAC13_CHSTAT_n_DER (0x00000400uL) -#define DMAC13_CHSTAT_n_MODE (0x00000800uL) -#define DMAC13_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC13_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC13_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC13_CHCTRL_n_STG (0x00000004uL) -#define DMAC13_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC13_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC13_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC13_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC13_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC13_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC13_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC13_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC13_CHCFG_n_SEL (0x00000007uL) -#define DMAC13_CHCFG_n_REQD (0x00000008uL) -#define DMAC13_CHCFG_n_LOEN (0x00000010uL) -#define DMAC13_CHCFG_n_HIEN (0x00000020uL) -#define DMAC13_CHCFG_n_LVL (0x00000040uL) -#define DMAC13_CHCFG_n_AM (0x00000700uL) -#define DMAC13_CHCFG_n_SDS (0x0000F000uL) -#define DMAC13_CHCFG_n_DDS (0x000F0000uL) -#define DMAC13_CHCFG_n_SAD (0x00100000uL) -#define DMAC13_CHCFG_n_DAD (0x00200000uL) -#define DMAC13_CHCFG_n_TM (0x00400000uL) -#define DMAC13_CHCFG_n_DEM (0x01000000uL) -#define DMAC13_CHCFG_n_TCM (0x02000000uL) -#define DMAC13_CHCFG_n_SBE (0x08000000uL) -#define DMAC13_CHCFG_n_RSEL (0x10000000uL) -#define DMAC13_CHCFG_n_RSW (0x20000000uL) -#define DMAC13_CHCFG_n_REN (0x40000000uL) -#define DMAC13_CHCFG_n_DMS (0x80000000uL) - -#define DMAC13_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC13_CHEXT_n_SCA (0x000000F0uL) -#define DMAC13_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC13_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC13_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC14 ---- */ -#define DMAC14_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC14_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC14_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC14_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC14_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC14_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC14_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC14_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC14_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC14_CHSTAT_n_EN (0x00000001uL) -#define DMAC14_CHSTAT_n_RQST (0x00000002uL) -#define DMAC14_CHSTAT_n_TACT (0x00000004uL) -#define DMAC14_CHSTAT_n_SUS (0x00000008uL) -#define DMAC14_CHSTAT_n_ER (0x00000010uL) -#define DMAC14_CHSTAT_n_END (0x00000020uL) -#define DMAC14_CHSTAT_n_TC (0x00000040uL) -#define DMAC14_CHSTAT_n_SR (0x00000080uL) -#define DMAC14_CHSTAT_n_DL (0x00000100uL) -#define DMAC14_CHSTAT_n_DW (0x00000200uL) -#define DMAC14_CHSTAT_n_DER (0x00000400uL) -#define DMAC14_CHSTAT_n_MODE (0x00000800uL) -#define DMAC14_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC14_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC14_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC14_CHCTRL_n_STG (0x00000004uL) -#define DMAC14_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC14_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC14_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC14_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC14_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC14_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC14_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC14_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC14_CHCFG_n_SEL (0x00000007uL) -#define DMAC14_CHCFG_n_REQD (0x00000008uL) -#define DMAC14_CHCFG_n_LOEN (0x00000010uL) -#define DMAC14_CHCFG_n_HIEN (0x00000020uL) -#define DMAC14_CHCFG_n_LVL (0x00000040uL) -#define DMAC14_CHCFG_n_AM (0x00000700uL) -#define DMAC14_CHCFG_n_SDS (0x0000F000uL) -#define DMAC14_CHCFG_n_DDS (0x000F0000uL) -#define DMAC14_CHCFG_n_SAD (0x00100000uL) -#define DMAC14_CHCFG_n_DAD (0x00200000uL) -#define DMAC14_CHCFG_n_TM (0x00400000uL) -#define DMAC14_CHCFG_n_DEM (0x01000000uL) -#define DMAC14_CHCFG_n_TCM (0x02000000uL) -#define DMAC14_CHCFG_n_SBE (0x08000000uL) -#define DMAC14_CHCFG_n_RSEL (0x10000000uL) -#define DMAC14_CHCFG_n_RSW (0x20000000uL) -#define DMAC14_CHCFG_n_REN (0x40000000uL) -#define DMAC14_CHCFG_n_DMS (0x80000000uL) - -#define DMAC14_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC14_CHEXT_n_SCA (0x000000F0uL) -#define DMAC14_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC14_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC14_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC15 ---- */ -#define DMAC15_N0SA_n_SA (0xFFFFFFFFuL) - -#define DMAC15_N0DA_n_DA (0xFFFFFFFFuL) - -#define DMAC15_N0TB_n_TB (0xFFFFFFFFuL) - -#define DMAC15_N1SA_n_SA (0xFFFFFFFFuL) - -#define DMAC15_N1DA_n_DA (0xFFFFFFFFuL) - -#define DMAC15_N1TB_n_TB (0xFFFFFFFFuL) - -#define DMAC15_CRSA_n_CRSA (0xFFFFFFFFuL) - -#define DMAC15_CRDA_n_CRDA (0xFFFFFFFFuL) - -#define DMAC15_CRTB_n_CRTB (0xFFFFFFFFuL) - -#define DMAC15_CHSTAT_n_EN (0x00000001uL) -#define DMAC15_CHSTAT_n_RQST (0x00000002uL) -#define DMAC15_CHSTAT_n_TACT (0x00000004uL) -#define DMAC15_CHSTAT_n_SUS (0x00000008uL) -#define DMAC15_CHSTAT_n_ER (0x00000010uL) -#define DMAC15_CHSTAT_n_END (0x00000020uL) -#define DMAC15_CHSTAT_n_TC (0x00000040uL) -#define DMAC15_CHSTAT_n_SR (0x00000080uL) -#define DMAC15_CHSTAT_n_DL (0x00000100uL) -#define DMAC15_CHSTAT_n_DW (0x00000200uL) -#define DMAC15_CHSTAT_n_DER (0x00000400uL) -#define DMAC15_CHSTAT_n_MODE (0x00000800uL) -#define DMAC15_CHSTAT_n_INTMSK (0x00010000uL) - -#define DMAC15_CHCTRL_n_SETEN (0x00000001uL) -#define DMAC15_CHCTRL_n_CLREN (0x00000002uL) -#define DMAC15_CHCTRL_n_STG (0x00000004uL) -#define DMAC15_CHCTRL_n_SWRST (0x00000008uL) -#define DMAC15_CHCTRL_n_CLRRQ (0x00000010uL) -#define DMAC15_CHCTRL_n_CLREND (0x00000020uL) -#define DMAC15_CHCTRL_n_CLRTC (0x00000040uL) -#define DMAC15_CHCTRL_n_SETSUS (0x00000100uL) -#define DMAC15_CHCTRL_n_CLRSUS (0x00000200uL) -#define DMAC15_CHCTRL_n_SETINTMSK (0x00010000uL) -#define DMAC15_CHCTRL_n_CLRINTMSK (0x00020000uL) - -#define DMAC15_CHCFG_n_SEL (0x00000007uL) -#define DMAC15_CHCFG_n_REQD (0x00000008uL) -#define DMAC15_CHCFG_n_LOEN (0x00000010uL) -#define DMAC15_CHCFG_n_HIEN (0x00000020uL) -#define DMAC15_CHCFG_n_LVL (0x00000040uL) -#define DMAC15_CHCFG_n_AM (0x00000700uL) -#define DMAC15_CHCFG_n_SDS (0x0000F000uL) -#define DMAC15_CHCFG_n_DDS (0x000F0000uL) -#define DMAC15_CHCFG_n_SAD (0x00100000uL) -#define DMAC15_CHCFG_n_DAD (0x00200000uL) -#define DMAC15_CHCFG_n_TM (0x00400000uL) -#define DMAC15_CHCFG_n_DEM (0x01000000uL) -#define DMAC15_CHCFG_n_TCM (0x02000000uL) -#define DMAC15_CHCFG_n_SBE (0x08000000uL) -#define DMAC15_CHCFG_n_RSEL (0x10000000uL) -#define DMAC15_CHCFG_n_RSW (0x20000000uL) -#define DMAC15_CHCFG_n_REN (0x40000000uL) -#define DMAC15_CHCFG_n_DMS (0x80000000uL) - -#define DMAC15_CHITVL_n_ITVL (0x0000FFFFuL) - -#define DMAC15_CHEXT_n_SCA (0x000000F0uL) -#define DMAC15_CHEXT_n_DCA (0x0000F000uL) - -#define DMAC15_NXLA_n_NXLA (0xFFFFFFFFuL) - -#define DMAC15_CRLA_n_CRLA (0xFFFFFFFFuL) - -/* ---- DMAC8-15 ---- */ -#define DMAC815_DCTRL_8_15_PR (0x00000001uL) -#define DMAC815_DCTRL_8_15_LVINT (0x00000002uL) -#define DMAC815_DCTRL_8_15_LDCA (0x0000003CuL) -#define DMAC815_DCTRL_8_15_LWCA (0x00003C00uL) - -#define DMAC815_DSTAT_EN_8_15_EN8 (0x00000001uL) -#define DMAC815_DSTAT_EN_8_15_EN9 (0x00000002uL) -#define DMAC815_DSTAT_EN_8_15_EN10 (0x00000004uL) -#define DMAC815_DSTAT_EN_8_15_EN11 (0x00000008uL) -#define DMAC815_DSTAT_EN_8_15_EN12 (0x00000010uL) -#define DMAC815_DSTAT_EN_8_15_EN13 (0x00000020uL) -#define DMAC815_DSTAT_EN_8_15_EN14 (0x00000040uL) -#define DMAC815_DSTAT_EN_8_15_EN15 (0x00000080uL) - -#define DMAC815_DSTAT_ER_8_15_ER8 (0x00000001uL) -#define DMAC815_DSTAT_ER_8_15_ER9 (0x00000002uL) -#define DMAC815_DSTAT_ER_8_15_ER10 (0x00000004uL) -#define DMAC815_DSTAT_ER_8_15_ER11 (0x00000008uL) -#define DMAC815_DSTAT_ER_8_15_ER12 (0x00000010uL) -#define DMAC815_DSTAT_ER_8_15_ER13 (0x00000020uL) -#define DMAC815_DSTAT_ER_8_15_ER14 (0x00000040uL) -#define DMAC815_DSTAT_ER_8_15_ER15 (0x00000080uL) - -#define DMAC815_DSTAT_END_8_15_END8 (0x00000001uL) -#define DMAC815_DSTAT_END_8_15_END9 (0x00000002uL) -#define DMAC815_DSTAT_END_8_15_END10 (0x00000004uL) -#define DMAC815_DSTAT_END_8_15_END11 (0x00000008uL) -#define DMAC815_DSTAT_END_8_15_END12 (0x00000010uL) -#define DMAC815_DSTAT_END_8_15_END13 (0x00000020uL) -#define DMAC815_DSTAT_END_8_15_END14 (0x00000040uL) -#define DMAC815_DSTAT_END_8_15_END15 (0x00000080uL) - -#define DMAC815_DSTAT_TC_8_15_TC8 (0x00000001uL) -#define DMAC815_DSTAT_TC_8_15_TC9 (0x00000002uL) -#define DMAC815_DSTAT_TC_8_15_TC10 (0x00000004uL) -#define DMAC815_DSTAT_TC_8_15_TC11 (0x00000008uL) -#define DMAC815_DSTAT_TC_8_15_TC12 (0x00000010uL) -#define DMAC815_DSTAT_TC_8_15_TC13 (0x00000020uL) -#define DMAC815_DSTAT_TC_8_15_TC14 (0x00000040uL) -#define DMAC815_DSTAT_TC_8_15_TC15 (0x00000080uL) - -#define DMAC815_DSTAT_SUS_8_15_SUS8 (0x00000001uL) -#define DMAC815_DSTAT_SUS_8_15_SUS9 (0x00000002uL) -#define DMAC815_DSTAT_SUS_8_15_SUS10 (0x00000004uL) -#define DMAC815_DSTAT_SUS_8_15_SUS11 (0x00000008uL) -#define DMAC815_DSTAT_SUS_8_15_SUS12 (0x00000010uL) -#define DMAC815_DSTAT_SUS_8_15_SUS13 (0x00000020uL) -#define DMAC815_DSTAT_SUS_8_15_SUS14 (0x00000040uL) -#define DMAC815_DSTAT_SUS_8_15_SUS15 (0x00000080uL) - -/* ---- DMAC0-1 ---- */ -#define DMAC01_DMARS_CH0_RID (0x00000003uL) -#define DMAC01_DMARS_CH0_MID (0x000001FCuL) -#define DMAC01_DMARS_CH1_RID (0x00030000uL) -#define DMAC01_DMARS_CH1_MID (0x01FC0000uL) - -/* ---- DMAC2-3 ---- */ -#define DMAC23_DMARS_CH2_RID (0x00000003uL) -#define DMAC23_DMARS_CH2_MID (0x000001FCuL) -#define DMAC23_DMARS_CH3_RID (0x00030000uL) -#define DMAC23_DMARS_CH3_MID (0x01FC0000uL) - -/* ---- DMAC4-5 ---- */ -#define DMAC45_DMARS_CH4_RID (0x00000003uL) -#define DMAC45_DMARS_CH4_MID (0x000001FCuL) -#define DMAC45_DMARS_CH5_RID (0x00030000uL) -#define DMAC45_DMARS_CH5_MID (0x01FC0000uL) - -/* ---- DMAC6-7 ---- */ -#define DMAC67_DMARS_CH6_RID (0x00000003uL) -#define DMAC67_DMARS_CH6_MID (0x000001FCuL) -#define DMAC67_DMARS_CH7_RID (0x00030000uL) -#define DMAC67_DMARS_CH7_MID (0x01FC0000uL) - -/* ---- DMAC8-9 ---- */ -#define DMAC89_DMARS_CH8_RID (0x00000003uL) -#define DMAC89_DMARS_CH8_MID (0x000001FCuL) -#define DMAC89_DMARS_CH9_RID (0x00030000uL) -#define DMAC89_DMARS_CH9_MID (0x01FC0000uL) - -/* ---- DMAC10-11 ---- */ -#define DMAC1011_DMARS_CH10_RID (0x00000003uL) -#define DMAC1011_DMARS_CH10_MID (0x000001FCuL) -#define DMAC1011_DMARS_CH11_RID (0x00030000uL) -#define DMAC1011_DMARS_CH11_MID (0x01FC0000uL) - -/* ---- DMAC12-13 ---- */ -#define DMAC1213_DMARS_CH12_RID (0x00000003uL) -#define DMAC1213_DMARS_CH12_MID (0x000001FCuL) -#define DMAC1213_DMARS_CH13_RID (0x00030000uL) -#define DMAC1213_DMARS_CH13_MID (0x01FC0000uL) - -/* ---- DMAC14-15 ---- */ -#define DMAC1415_DMARS_CH14_RID (0x00000003uL) -#define DMAC1415_DMARS_CH14_MID (0x000001FCuL) -#define DMAC1415_DMARS_CH15_RID (0x00030000uL) -#define DMAC1415_DMARS_CH15_MID (0x01FC0000uL) - - -/* ==== Shift values for IO registers ==== */ -/* ---- DMAC0 ---- */ -#define DMAC0_N0SA_n_SA_SHIFT (0u) - -#define DMAC0_N0DA_n_DA_SHIFT (0u) - -#define DMAC0_N0TB_n_TB_SHIFT (0u) - -#define DMAC0_N1SA_n_SA_SHIFT (0u) - -#define DMAC0_N1DA_n_DA_SHIFT (0u) - -#define DMAC0_N1TB_n_TB_SHIFT (0u) - -#define DMAC0_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC0_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC0_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC0_CHSTAT_n_EN_SHIFT (0u) -#define DMAC0_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC0_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC0_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC0_CHSTAT_n_ER_SHIFT (4u) -#define DMAC0_CHSTAT_n_END_SHIFT (5u) -#define DMAC0_CHSTAT_n_TC_SHIFT (6u) -#define DMAC0_CHSTAT_n_SR_SHIFT (7u) -#define DMAC0_CHSTAT_n_DL_SHIFT (8u) -#define DMAC0_CHSTAT_n_DW_SHIFT (9u) -#define DMAC0_CHSTAT_n_DER_SHIFT (10u) -#define DMAC0_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC0_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC0_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC0_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC0_CHCTRL_n_STG_SHIFT (2u) -#define DMAC0_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC0_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC0_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC0_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC0_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC0_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC0_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC0_CHCFG_n_SEL_SHIFT (0u) -#define DMAC0_CHCFG_n_REQD_SHIFT (3u) -#define DMAC0_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC0_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC0_CHCFG_n_LVL_SHIFT (6u) -#define DMAC0_CHCFG_n_AM_SHIFT (8u) -#define DMAC0_CHCFG_n_SDS_SHIFT (12u) -#define DMAC0_CHCFG_n_DDS_SHIFT (16u) -#define DMAC0_CHCFG_n_SAD_SHIFT (20u) -#define DMAC0_CHCFG_n_DAD_SHIFT (21u) -#define DMAC0_CHCFG_n_TM_SHIFT (22u) -#define DMAC0_CHCFG_n_DEM_SHIFT (24u) -#define DMAC0_CHCFG_n_TCM_SHIFT (25u) -#define DMAC0_CHCFG_n_SBE_SHIFT (27u) -#define DMAC0_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC0_CHCFG_n_RSW_SHIFT (29u) -#define DMAC0_CHCFG_n_REN_SHIFT (30u) -#define DMAC0_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC0_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC0_CHEXT_n_SCA_SHIFT (4u) -#define DMAC0_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC0_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC0_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC1 ---- */ -#define DMAC1_N0SA_n_SA_SHIFT (0u) - -#define DMAC1_N0DA_n_DA_SHIFT (0u) - -#define DMAC1_N0TB_n_TB_SHIFT (0u) - -#define DMAC1_N1SA_n_SA_SHIFT (0u) - -#define DMAC1_N1DA_n_DA_SHIFT (0u) - -#define DMAC1_N1TB_n_TB_SHIFT (0u) - -#define DMAC1_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC1_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC1_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC1_CHSTAT_n_EN_SHIFT (0u) -#define DMAC1_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC1_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC1_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC1_CHSTAT_n_ER_SHIFT (4u) -#define DMAC1_CHSTAT_n_END_SHIFT (5u) -#define DMAC1_CHSTAT_n_TC_SHIFT (6u) -#define DMAC1_CHSTAT_n_SR_SHIFT (7u) -#define DMAC1_CHSTAT_n_DL_SHIFT (8u) -#define DMAC1_CHSTAT_n_DW_SHIFT (9u) -#define DMAC1_CHSTAT_n_DER_SHIFT (10u) -#define DMAC1_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC1_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC1_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC1_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC1_CHCTRL_n_STG_SHIFT (2u) -#define DMAC1_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC1_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC1_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC1_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC1_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC1_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC1_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC1_CHCFG_n_SEL_SHIFT (0u) -#define DMAC1_CHCFG_n_REQD_SHIFT (3u) -#define DMAC1_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC1_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC1_CHCFG_n_LVL_SHIFT (6u) -#define DMAC1_CHCFG_n_AM_SHIFT (8u) -#define DMAC1_CHCFG_n_SDS_SHIFT (12u) -#define DMAC1_CHCFG_n_DDS_SHIFT (16u) -#define DMAC1_CHCFG_n_SAD_SHIFT (20u) -#define DMAC1_CHCFG_n_DAD_SHIFT (21u) -#define DMAC1_CHCFG_n_TM_SHIFT (22u) -#define DMAC1_CHCFG_n_DEM_SHIFT (24u) -#define DMAC1_CHCFG_n_TCM_SHIFT (25u) -#define DMAC1_CHCFG_n_SBE_SHIFT (27u) -#define DMAC1_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC1_CHCFG_n_RSW_SHIFT (29u) -#define DMAC1_CHCFG_n_REN_SHIFT (30u) -#define DMAC1_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC1_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC1_CHEXT_n_SCA_SHIFT (4u) -#define DMAC1_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC1_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC1_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC2 ---- */ -#define DMAC2_N0SA_n_SA_SHIFT (0u) - -#define DMAC2_N0DA_n_DA_SHIFT (0u) - -#define DMAC2_N0TB_n_TB_SHIFT (0u) - -#define DMAC2_N1SA_n_SA_SHIFT (0u) - -#define DMAC2_N1DA_n_DA_SHIFT (0u) - -#define DMAC2_N1TB_n_TB_SHIFT (0u) - -#define DMAC2_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC2_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC2_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC2_CHSTAT_n_EN_SHIFT (0u) -#define DMAC2_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC2_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC2_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC2_CHSTAT_n_ER_SHIFT (4u) -#define DMAC2_CHSTAT_n_END_SHIFT (5u) -#define DMAC2_CHSTAT_n_TC_SHIFT (6u) -#define DMAC2_CHSTAT_n_SR_SHIFT (7u) -#define DMAC2_CHSTAT_n_DL_SHIFT (8u) -#define DMAC2_CHSTAT_n_DW_SHIFT (9u) -#define DMAC2_CHSTAT_n_DER_SHIFT (10u) -#define DMAC2_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC2_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC2_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC2_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC2_CHCTRL_n_STG_SHIFT (2u) -#define DMAC2_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC2_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC2_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC2_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC2_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC2_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC2_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC2_CHCFG_n_SEL_SHIFT (0u) -#define DMAC2_CHCFG_n_REQD_SHIFT (3u) -#define DMAC2_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC2_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC2_CHCFG_n_LVL_SHIFT (6u) -#define DMAC2_CHCFG_n_AM_SHIFT (8u) -#define DMAC2_CHCFG_n_SDS_SHIFT (12u) -#define DMAC2_CHCFG_n_DDS_SHIFT (16u) -#define DMAC2_CHCFG_n_SAD_SHIFT (20u) -#define DMAC2_CHCFG_n_DAD_SHIFT (21u) -#define DMAC2_CHCFG_n_TM_SHIFT (22u) -#define DMAC2_CHCFG_n_DEM_SHIFT (24u) -#define DMAC2_CHCFG_n_TCM_SHIFT (25u) -#define DMAC2_CHCFG_n_SBE_SHIFT (27u) -#define DMAC2_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC2_CHCFG_n_RSW_SHIFT (29u) -#define DMAC2_CHCFG_n_REN_SHIFT (30u) -#define DMAC2_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC2_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC2_CHEXT_n_SCA_SHIFT (4u) -#define DMAC2_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC2_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC2_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC3 ---- */ -#define DMAC3_N0SA_n_SA_SHIFT (0u) - -#define DMAC3_N0DA_n_DA_SHIFT (0u) - -#define DMAC3_N0TB_n_TB_SHIFT (0u) - -#define DMAC3_N1SA_n_SA_SHIFT (0u) - -#define DMAC3_N1DA_n_DA_SHIFT (0u) - -#define DMAC3_N1TB_n_TB_SHIFT (0u) - -#define DMAC3_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC3_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC3_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC3_CHSTAT_n_EN_SHIFT (0u) -#define DMAC3_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC3_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC3_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC3_CHSTAT_n_ER_SHIFT (4u) -#define DMAC3_CHSTAT_n_END_SHIFT (5u) -#define DMAC3_CHSTAT_n_TC_SHIFT (6u) -#define DMAC3_CHSTAT_n_SR_SHIFT (7u) -#define DMAC3_CHSTAT_n_DL_SHIFT (8u) -#define DMAC3_CHSTAT_n_DW_SHIFT (9u) -#define DMAC3_CHSTAT_n_DER_SHIFT (10u) -#define DMAC3_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC3_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC3_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC3_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC3_CHCTRL_n_STG_SHIFT (2u) -#define DMAC3_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC3_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC3_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC3_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC3_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC3_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC3_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC3_CHCFG_n_SEL_SHIFT (0u) -#define DMAC3_CHCFG_n_REQD_SHIFT (3u) -#define DMAC3_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC3_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC3_CHCFG_n_LVL_SHIFT (6u) -#define DMAC3_CHCFG_n_AM_SHIFT (8u) -#define DMAC3_CHCFG_n_SDS_SHIFT (12u) -#define DMAC3_CHCFG_n_DDS_SHIFT (16u) -#define DMAC3_CHCFG_n_SAD_SHIFT (20u) -#define DMAC3_CHCFG_n_DAD_SHIFT (21u) -#define DMAC3_CHCFG_n_TM_SHIFT (22u) -#define DMAC3_CHCFG_n_DEM_SHIFT (24u) -#define DMAC3_CHCFG_n_TCM_SHIFT (25u) -#define DMAC3_CHCFG_n_SBE_SHIFT (27u) -#define DMAC3_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC3_CHCFG_n_RSW_SHIFT (29u) -#define DMAC3_CHCFG_n_REN_SHIFT (30u) -#define DMAC3_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC3_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC3_CHEXT_n_SCA_SHIFT (4u) -#define DMAC3_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC3_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC3_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC4 ---- */ -#define DMAC4_N0SA_n_SA_SHIFT (0u) - -#define DMAC4_N0DA_n_DA_SHIFT (0u) - -#define DMAC4_N0TB_n_TB_SHIFT (0u) - -#define DMAC4_N1SA_n_SA_SHIFT (0u) - -#define DMAC4_N1DA_n_DA_SHIFT (0u) - -#define DMAC4_N1TB_n_TB_SHIFT (0u) - -#define DMAC4_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC4_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC4_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC4_CHSTAT_n_EN_SHIFT (0u) -#define DMAC4_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC4_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC4_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC4_CHSTAT_n_ER_SHIFT (4u) -#define DMAC4_CHSTAT_n_END_SHIFT (5u) -#define DMAC4_CHSTAT_n_TC_SHIFT (6u) -#define DMAC4_CHSTAT_n_SR_SHIFT (7u) -#define DMAC4_CHSTAT_n_DL_SHIFT (8u) -#define DMAC4_CHSTAT_n_DW_SHIFT (9u) -#define DMAC4_CHSTAT_n_DER_SHIFT (10u) -#define DMAC4_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC4_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC4_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC4_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC4_CHCTRL_n_STG_SHIFT (2u) -#define DMAC4_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC4_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC4_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC4_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC4_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC4_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC4_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC4_CHCFG_n_SEL_SHIFT (0u) -#define DMAC4_CHCFG_n_REQD_SHIFT (3u) -#define DMAC4_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC4_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC4_CHCFG_n_LVL_SHIFT (6u) -#define DMAC4_CHCFG_n_AM_SHIFT (8u) -#define DMAC4_CHCFG_n_SDS_SHIFT (12u) -#define DMAC4_CHCFG_n_DDS_SHIFT (16u) -#define DMAC4_CHCFG_n_SAD_SHIFT (20u) -#define DMAC4_CHCFG_n_DAD_SHIFT (21u) -#define DMAC4_CHCFG_n_TM_SHIFT (22u) -#define DMAC4_CHCFG_n_DEM_SHIFT (24u) -#define DMAC4_CHCFG_n_TCM_SHIFT (25u) -#define DMAC4_CHCFG_n_SBE_SHIFT (27u) -#define DMAC4_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC4_CHCFG_n_RSW_SHIFT (29u) -#define DMAC4_CHCFG_n_REN_SHIFT (30u) -#define DMAC4_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC4_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC4_CHEXT_n_SCA_SHIFT (4u) -#define DMAC4_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC4_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC4_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC5 ---- */ -#define DMAC5_N0SA_n_SA_SHIFT (0u) - -#define DMAC5_N0DA_n_DA_SHIFT (0u) - -#define DMAC5_N0TB_n_TB_SHIFT (0u) - -#define DMAC5_N1SA_n_SA_SHIFT (0u) - -#define DMAC5_N1DA_n_DA_SHIFT (0u) - -#define DMAC5_N1TB_n_TB_SHIFT (0u) - -#define DMAC5_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC5_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC5_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC5_CHSTAT_n_EN_SHIFT (0u) -#define DMAC5_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC5_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC5_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC5_CHSTAT_n_ER_SHIFT (4u) -#define DMAC5_CHSTAT_n_END_SHIFT (5u) -#define DMAC5_CHSTAT_n_TC_SHIFT (6u) -#define DMAC5_CHSTAT_n_SR_SHIFT (7u) -#define DMAC5_CHSTAT_n_DL_SHIFT (8u) -#define DMAC5_CHSTAT_n_DW_SHIFT (9u) -#define DMAC5_CHSTAT_n_DER_SHIFT (10u) -#define DMAC5_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC5_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC5_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC5_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC5_CHCTRL_n_STG_SHIFT (2u) -#define DMAC5_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC5_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC5_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC5_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC5_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC5_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC5_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC5_CHCFG_n_SEL_SHIFT (0u) -#define DMAC5_CHCFG_n_REQD_SHIFT (3u) -#define DMAC5_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC5_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC5_CHCFG_n_LVL_SHIFT (6u) -#define DMAC5_CHCFG_n_AM_SHIFT (8u) -#define DMAC5_CHCFG_n_SDS_SHIFT (12u) -#define DMAC5_CHCFG_n_DDS_SHIFT (16u) -#define DMAC5_CHCFG_n_SAD_SHIFT (20u) -#define DMAC5_CHCFG_n_DAD_SHIFT (21u) -#define DMAC5_CHCFG_n_TM_SHIFT (22u) -#define DMAC5_CHCFG_n_DEM_SHIFT (24u) -#define DMAC5_CHCFG_n_TCM_SHIFT (25u) -#define DMAC5_CHCFG_n_SBE_SHIFT (27u) -#define DMAC5_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC5_CHCFG_n_RSW_SHIFT (29u) -#define DMAC5_CHCFG_n_REN_SHIFT (30u) -#define DMAC5_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC5_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC5_CHEXT_n_SCA_SHIFT (4u) -#define DMAC5_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC5_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC5_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC6 ---- */ -#define DMAC6_N0SA_n_SA_SHIFT (0u) - -#define DMAC6_N0DA_n_DA_SHIFT (0u) - -#define DMAC6_N0TB_n_TB_SHIFT (0u) - -#define DMAC6_N1SA_n_SA_SHIFT (0u) - -#define DMAC6_N1DA_n_DA_SHIFT (0u) - -#define DMAC6_N1TB_n_TB_SHIFT (0u) - -#define DMAC6_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC6_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC6_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC6_CHSTAT_n_EN_SHIFT (0u) -#define DMAC6_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC6_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC6_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC6_CHSTAT_n_ER_SHIFT (4u) -#define DMAC6_CHSTAT_n_END_SHIFT (5u) -#define DMAC6_CHSTAT_n_TC_SHIFT (6u) -#define DMAC6_CHSTAT_n_SR_SHIFT (7u) -#define DMAC6_CHSTAT_n_DL_SHIFT (8u) -#define DMAC6_CHSTAT_n_DW_SHIFT (9u) -#define DMAC6_CHSTAT_n_DER_SHIFT (10u) -#define DMAC6_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC6_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC6_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC6_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC6_CHCTRL_n_STG_SHIFT (2u) -#define DMAC6_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC6_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC6_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC6_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC6_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC6_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC6_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC6_CHCFG_n_SEL_SHIFT (0u) -#define DMAC6_CHCFG_n_REQD_SHIFT (3u) -#define DMAC6_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC6_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC6_CHCFG_n_LVL_SHIFT (6u) -#define DMAC6_CHCFG_n_AM_SHIFT (8u) -#define DMAC6_CHCFG_n_SDS_SHIFT (12u) -#define DMAC6_CHCFG_n_DDS_SHIFT (16u) -#define DMAC6_CHCFG_n_SAD_SHIFT (20u) -#define DMAC6_CHCFG_n_DAD_SHIFT (21u) -#define DMAC6_CHCFG_n_TM_SHIFT (22u) -#define DMAC6_CHCFG_n_DEM_SHIFT (24u) -#define DMAC6_CHCFG_n_TCM_SHIFT (25u) -#define DMAC6_CHCFG_n_SBE_SHIFT (27u) -#define DMAC6_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC6_CHCFG_n_RSW_SHIFT (29u) -#define DMAC6_CHCFG_n_REN_SHIFT (30u) -#define DMAC6_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC6_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC6_CHEXT_n_SCA_SHIFT (4u) -#define DMAC6_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC6_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC6_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC7 ---- */ -#define DMAC7_N0SA_n_SA_SHIFT (0u) - -#define DMAC7_N0DA_n_DA_SHIFT (0u) - -#define DMAC7_N0TB_n_TB_SHIFT (0u) - -#define DMAC7_N1SA_n_SA_SHIFT (0u) - -#define DMAC7_N1DA_n_DA_SHIFT (0u) - -#define DMAC7_N1TB_n_TB_SHIFT (0u) - -#define DMAC7_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC7_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC7_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC7_CHSTAT_n_EN_SHIFT (0u) -#define DMAC7_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC7_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC7_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC7_CHSTAT_n_ER_SHIFT (4u) -#define DMAC7_CHSTAT_n_END_SHIFT (5u) -#define DMAC7_CHSTAT_n_TC_SHIFT (6u) -#define DMAC7_CHSTAT_n_SR_SHIFT (7u) -#define DMAC7_CHSTAT_n_DL_SHIFT (8u) -#define DMAC7_CHSTAT_n_DW_SHIFT (9u) -#define DMAC7_CHSTAT_n_DER_SHIFT (10u) -#define DMAC7_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC7_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC7_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC7_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC7_CHCTRL_n_STG_SHIFT (2u) -#define DMAC7_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC7_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC7_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC7_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC7_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC7_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC7_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC7_CHCFG_n_SEL_SHIFT (0u) -#define DMAC7_CHCFG_n_REQD_SHIFT (3u) -#define DMAC7_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC7_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC7_CHCFG_n_LVL_SHIFT (6u) -#define DMAC7_CHCFG_n_AM_SHIFT (8u) -#define DMAC7_CHCFG_n_SDS_SHIFT (12u) -#define DMAC7_CHCFG_n_DDS_SHIFT (16u) -#define DMAC7_CHCFG_n_SAD_SHIFT (20u) -#define DMAC7_CHCFG_n_DAD_SHIFT (21u) -#define DMAC7_CHCFG_n_TM_SHIFT (22u) -#define DMAC7_CHCFG_n_DEM_SHIFT (24u) -#define DMAC7_CHCFG_n_TCM_SHIFT (25u) -#define DMAC7_CHCFG_n_SBE_SHIFT (27u) -#define DMAC7_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC7_CHCFG_n_RSW_SHIFT (29u) -#define DMAC7_CHCFG_n_REN_SHIFT (30u) -#define DMAC7_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC7_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC7_CHEXT_n_SCA_SHIFT (4u) -#define DMAC7_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC7_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC7_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC0-7 ---- */ -#define DMAC07_DCTRL_0_7_PR_SHIFT (0u) -#define DMAC07_DCTRL_0_7_LVINT_SHIFT (1u) -#define DMAC07_DCTRL_0_7_LDCA_SHIFT (2u) -#define DMAC07_DCTRL_0_7_LWCA_SHIFT (6u) - -#define DMAC07_DSTAT_EN_0_7_EN0_SHIFT (0u) -#define DMAC07_DSTAT_EN_0_7_EN1_SHIFT (1u) -#define DMAC07_DSTAT_EN_0_7_EN2_SHIFT (2u) -#define DMAC07_DSTAT_EN_0_7_EN3_SHIFT (3u) -#define DMAC07_DSTAT_EN_0_7_EN4_SHIFT (4u) -#define DMAC07_DSTAT_EN_0_7_EN5_SHIFT (5u) -#define DMAC07_DSTAT_EN_0_7_EN6_SHIFT (6u) -#define DMAC07_DSTAT_EN_0_7_EN7_SHIFT (7u) - -#define DMAC07_DSTAT_ER_0_7_ER0_SHIFT (0u) -#define DMAC07_DSTAT_ER_0_7_ER1_SHIFT (1u) -#define DMAC07_DSTAT_ER_0_7_ER2_SHIFT (2u) -#define DMAC07_DSTAT_ER_0_7_ER3_SHIFT (3u) -#define DMAC07_DSTAT_ER_0_7_ER4_SHIFT (4u) -#define DMAC07_DSTAT_ER_0_7_ER5_SHIFT (5u) -#define DMAC07_DSTAT_ER_0_7_ER6_SHIFT (6u) -#define DMAC07_DSTAT_ER_0_7_ER7_SHIFT (7u) - -#define DMAC07_DSTAT_END_0_7_END0_SHIFT (0u) -#define DMAC07_DSTAT_END_0_7_END1_SHIFT (1u) -#define DMAC07_DSTAT_END_0_7_END2_SHIFT (2u) -#define DMAC07_DSTAT_END_0_7_END3_SHIFT (3u) -#define DMAC07_DSTAT_END_0_7_END4_SHIFT (4u) -#define DMAC07_DSTAT_END_0_7_END5_SHIFT (5u) -#define DMAC07_DSTAT_END_0_7_END6_SHIFT (6u) -#define DMAC07_DSTAT_END_0_7_END7_SHIFT (7u) - -#define DMAC07_DSTAT_TC_0_7_TC0_SHIFT (0u) -#define DMAC07_DSTAT_TC_0_7_TC1_SHIFT (1u) -#define DMAC07_DSTAT_TC_0_7_TC2_SHIFT (2u) -#define DMAC07_DSTAT_TC_0_7_TC3_SHIFT (3u) -#define DMAC07_DSTAT_TC_0_7_TC4_SHIFT (4u) -#define DMAC07_DSTAT_TC_0_7_TC5_SHIFT (5u) -#define DMAC07_DSTAT_TC_0_7_TC6_SHIFT (6u) -#define DMAC07_DSTAT_TC_0_7_TC7_SHIFT (7u) - -#define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT (0u) -#define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT (1u) -#define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT (2u) -#define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT (3u) -#define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT (4u) -#define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT (5u) -#define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT (6u) -#define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT (7u) - -/* ---- DMAC8 ---- */ -#define DMAC8_N0SA_n_SA_SHIFT (0u) - -#define DMAC8_N0DA_n_DA_SHIFT (0u) - -#define DMAC8_N0TB_n_TB_SHIFT (0u) - -#define DMAC8_N1SA_n_SA_SHIFT (0u) - -#define DMAC8_N1DA_n_DA_SHIFT (0u) - -#define DMAC8_N1TB_n_TB_SHIFT (0u) - -#define DMAC8_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC8_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC8_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC8_CHSTAT_n_EN_SHIFT (0u) -#define DMAC8_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC8_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC8_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC8_CHSTAT_n_ER_SHIFT (4u) -#define DMAC8_CHSTAT_n_END_SHIFT (5u) -#define DMAC8_CHSTAT_n_TC_SHIFT (6u) -#define DMAC8_CHSTAT_n_SR_SHIFT (7u) -#define DMAC8_CHSTAT_n_DL_SHIFT (8u) -#define DMAC8_CHSTAT_n_DW_SHIFT (9u) -#define DMAC8_CHSTAT_n_DER_SHIFT (10u) -#define DMAC8_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC8_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC8_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC8_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC8_CHCTRL_n_STG_SHIFT (2u) -#define DMAC8_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC8_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC8_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC8_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC8_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC8_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC8_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC8_CHCFG_n_SEL_SHIFT (0u) -#define DMAC8_CHCFG_n_REQD_SHIFT (3u) -#define DMAC8_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC8_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC8_CHCFG_n_LVL_SHIFT (6u) -#define DMAC8_CHCFG_n_AM_SHIFT (8u) -#define DMAC8_CHCFG_n_SDS_SHIFT (12u) -#define DMAC8_CHCFG_n_DDS_SHIFT (16u) -#define DMAC8_CHCFG_n_SAD_SHIFT (20u) -#define DMAC8_CHCFG_n_DAD_SHIFT (21u) -#define DMAC8_CHCFG_n_TM_SHIFT (22u) -#define DMAC8_CHCFG_n_DEM_SHIFT (24u) -#define DMAC8_CHCFG_n_TCM_SHIFT (25u) -#define DMAC8_CHCFG_n_SBE_SHIFT (27u) -#define DMAC8_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC8_CHCFG_n_RSW_SHIFT (29u) -#define DMAC8_CHCFG_n_REN_SHIFT (30u) -#define DMAC8_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC8_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC8_CHEXT_n_SCA_SHIFT (4u) -#define DMAC8_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC8_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC8_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC9 ---- */ -#define DMAC9_N0SA_n_SA_SHIFT (0u) - -#define DMAC9_N0DA_n_DA_SHIFT (0u) - -#define DMAC9_N0TB_n_TB_SHIFT (0u) - -#define DMAC9_N1SA_n_SA_SHIFT (0u) - -#define DMAC9_N1DA_n_DA_SHIFT (0u) - -#define DMAC9_N1TB_n_TB_SHIFT (0u) - -#define DMAC9_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC9_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC9_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC9_CHSTAT_n_EN_SHIFT (0u) -#define DMAC9_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC9_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC9_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC9_CHSTAT_n_ER_SHIFT (4u) -#define DMAC9_CHSTAT_n_END_SHIFT (5u) -#define DMAC9_CHSTAT_n_TC_SHIFT (6u) -#define DMAC9_CHSTAT_n_SR_SHIFT (7u) -#define DMAC9_CHSTAT_n_DL_SHIFT (8u) -#define DMAC9_CHSTAT_n_DW_SHIFT (9u) -#define DMAC9_CHSTAT_n_DER_SHIFT (10u) -#define DMAC9_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC9_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC9_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC9_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC9_CHCTRL_n_STG_SHIFT (2u) -#define DMAC9_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC9_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC9_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC9_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC9_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC9_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC9_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC9_CHCFG_n_SEL_SHIFT (0u) -#define DMAC9_CHCFG_n_REQD_SHIFT (3u) -#define DMAC9_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC9_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC9_CHCFG_n_LVL_SHIFT (6u) -#define DMAC9_CHCFG_n_AM_SHIFT (8u) -#define DMAC9_CHCFG_n_SDS_SHIFT (12u) -#define DMAC9_CHCFG_n_DDS_SHIFT (16u) -#define DMAC9_CHCFG_n_SAD_SHIFT (20u) -#define DMAC9_CHCFG_n_DAD_SHIFT (21u) -#define DMAC9_CHCFG_n_TM_SHIFT (22u) -#define DMAC9_CHCFG_n_DEM_SHIFT (24u) -#define DMAC9_CHCFG_n_TCM_SHIFT (25u) -#define DMAC9_CHCFG_n_SBE_SHIFT (27u) -#define DMAC9_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC9_CHCFG_n_RSW_SHIFT (29u) -#define DMAC9_CHCFG_n_REN_SHIFT (30u) -#define DMAC9_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC9_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC9_CHEXT_n_SCA_SHIFT (4u) -#define DMAC9_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC9_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC9_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC10 ---- */ -#define DMAC10_N0SA_n_SA_SHIFT (0u) - -#define DMAC10_N0DA_n_DA_SHIFT (0u) - -#define DMAC10_N0TB_n_TB_SHIFT (0u) - -#define DMAC10_N1SA_n_SA_SHIFT (0u) - -#define DMAC10_N1DA_n_DA_SHIFT (0u) - -#define DMAC10_N1TB_n_TB_SHIFT (0u) - -#define DMAC10_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC10_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC10_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC10_CHSTAT_n_EN_SHIFT (0u) -#define DMAC10_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC10_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC10_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC10_CHSTAT_n_ER_SHIFT (4u) -#define DMAC10_CHSTAT_n_END_SHIFT (5u) -#define DMAC10_CHSTAT_n_TC_SHIFT (6u) -#define DMAC10_CHSTAT_n_SR_SHIFT (7u) -#define DMAC10_CHSTAT_n_DL_SHIFT (8u) -#define DMAC10_CHSTAT_n_DW_SHIFT (9u) -#define DMAC10_CHSTAT_n_DER_SHIFT (10u) -#define DMAC10_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC10_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC10_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC10_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC10_CHCTRL_n_STG_SHIFT (2u) -#define DMAC10_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC10_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC10_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC10_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC10_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC10_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC10_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC10_CHCFG_n_SEL_SHIFT (0u) -#define DMAC10_CHCFG_n_REQD_SHIFT (3u) -#define DMAC10_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC10_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC10_CHCFG_n_LVL_SHIFT (6u) -#define DMAC10_CHCFG_n_AM_SHIFT (8u) -#define DMAC10_CHCFG_n_SDS_SHIFT (12u) -#define DMAC10_CHCFG_n_DDS_SHIFT (16u) -#define DMAC10_CHCFG_n_SAD_SHIFT (20u) -#define DMAC10_CHCFG_n_DAD_SHIFT (21u) -#define DMAC10_CHCFG_n_TM_SHIFT (22u) -#define DMAC10_CHCFG_n_DEM_SHIFT (24u) -#define DMAC10_CHCFG_n_TCM_SHIFT (25u) -#define DMAC10_CHCFG_n_SBE_SHIFT (27u) -#define DMAC10_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC10_CHCFG_n_RSW_SHIFT (29u) -#define DMAC10_CHCFG_n_REN_SHIFT (30u) -#define DMAC10_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC10_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC10_CHEXT_n_SCA_SHIFT (4u) -#define DMAC10_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC10_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC10_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC11 ---- */ -#define DMAC11_N0SA_n_SA_SHIFT (0u) - -#define DMAC11_N0DA_n_DA_SHIFT (0u) - -#define DMAC11_N0TB_n_TB_SHIFT (0u) - -#define DMAC11_N1SA_n_SA_SHIFT (0u) - -#define DMAC11_N1DA_n_DA_SHIFT (0u) - -#define DMAC11_N1TB_n_TB_SHIFT (0u) - -#define DMAC11_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC11_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC11_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC11_CHSTAT_n_EN_SHIFT (0u) -#define DMAC11_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC11_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC11_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC11_CHSTAT_n_ER_SHIFT (4u) -#define DMAC11_CHSTAT_n_END_SHIFT (5u) -#define DMAC11_CHSTAT_n_TC_SHIFT (6u) -#define DMAC11_CHSTAT_n_SR_SHIFT (7u) -#define DMAC11_CHSTAT_n_DL_SHIFT (8u) -#define DMAC11_CHSTAT_n_DW_SHIFT (9u) -#define DMAC11_CHSTAT_n_DER_SHIFT (10u) -#define DMAC11_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC11_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC11_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC11_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC11_CHCTRL_n_STG_SHIFT (2u) -#define DMAC11_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC11_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC11_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC11_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC11_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC11_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC11_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC11_CHCFG_n_SEL_SHIFT (0u) -#define DMAC11_CHCFG_n_REQD_SHIFT (3u) -#define DMAC11_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC11_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC11_CHCFG_n_LVL_SHIFT (6u) -#define DMAC11_CHCFG_n_AM_SHIFT (8u) -#define DMAC11_CHCFG_n_SDS_SHIFT (12u) -#define DMAC11_CHCFG_n_DDS_SHIFT (16u) -#define DMAC11_CHCFG_n_SAD_SHIFT (20u) -#define DMAC11_CHCFG_n_DAD_SHIFT (21u) -#define DMAC11_CHCFG_n_TM_SHIFT (22u) -#define DMAC11_CHCFG_n_DEM_SHIFT (24u) -#define DMAC11_CHCFG_n_TCM_SHIFT (25u) -#define DMAC11_CHCFG_n_SBE_SHIFT (27u) -#define DMAC11_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC11_CHCFG_n_RSW_SHIFT (29u) -#define DMAC11_CHCFG_n_REN_SHIFT (30u) -#define DMAC11_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC11_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC11_CHEXT_n_SCA_SHIFT (4u) -#define DMAC11_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC11_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC11_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC12 ---- */ -#define DMAC12_N0SA_n_SA_SHIFT (0u) - -#define DMAC12_N0DA_n_DA_SHIFT (0u) - -#define DMAC12_N0TB_n_TB_SHIFT (0u) - -#define DMAC12_N1SA_n_SA_SHIFT (0u) - -#define DMAC12_N1DA_n_DA_SHIFT (0u) - -#define DMAC12_N1TB_n_TB_SHIFT (0u) - -#define DMAC12_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC12_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC12_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC12_CHSTAT_n_EN_SHIFT (0u) -#define DMAC12_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC12_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC12_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC12_CHSTAT_n_ER_SHIFT (4u) -#define DMAC12_CHSTAT_n_END_SHIFT (5u) -#define DMAC12_CHSTAT_n_TC_SHIFT (6u) -#define DMAC12_CHSTAT_n_SR_SHIFT (7u) -#define DMAC12_CHSTAT_n_DL_SHIFT (8u) -#define DMAC12_CHSTAT_n_DW_SHIFT (9u) -#define DMAC12_CHSTAT_n_DER_SHIFT (10u) -#define DMAC12_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC12_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC12_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC12_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC12_CHCTRL_n_STG_SHIFT (2u) -#define DMAC12_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC12_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC12_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC12_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC12_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC12_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC12_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC12_CHCFG_n_SEL_SHIFT (0u) -#define DMAC12_CHCFG_n_REQD_SHIFT (3u) -#define DMAC12_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC12_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC12_CHCFG_n_LVL_SHIFT (6u) -#define DMAC12_CHCFG_n_AM_SHIFT (8u) -#define DMAC12_CHCFG_n_SDS_SHIFT (12u) -#define DMAC12_CHCFG_n_DDS_SHIFT (16u) -#define DMAC12_CHCFG_n_SAD_SHIFT (20u) -#define DMAC12_CHCFG_n_DAD_SHIFT (21u) -#define DMAC12_CHCFG_n_TM_SHIFT (22u) -#define DMAC12_CHCFG_n_DEM_SHIFT (24u) -#define DMAC12_CHCFG_n_TCM_SHIFT (25u) -#define DMAC12_CHCFG_n_SBE_SHIFT (27u) -#define DMAC12_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC12_CHCFG_n_RSW_SHIFT (29u) -#define DMAC12_CHCFG_n_REN_SHIFT (30u) -#define DMAC12_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC12_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC12_CHEXT_n_SCA_SHIFT (4u) -#define DMAC12_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC12_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC12_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC13 ---- */ -#define DMAC13_N0SA_n_SA_SHIFT (0u) - -#define DMAC13_N0DA_n_DA_SHIFT (0u) - -#define DMAC13_N0TB_n_TB_SHIFT (0u) - -#define DMAC13_N1SA_n_SA_SHIFT (0u) - -#define DMAC13_N1DA_n_DA_SHIFT (0u) - -#define DMAC13_N1TB_n_TB_SHIFT (0u) - -#define DMAC13_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC13_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC13_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC13_CHSTAT_n_EN_SHIFT (0u) -#define DMAC13_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC13_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC13_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC13_CHSTAT_n_ER_SHIFT (4u) -#define DMAC13_CHSTAT_n_END_SHIFT (5u) -#define DMAC13_CHSTAT_n_TC_SHIFT (6u) -#define DMAC13_CHSTAT_n_SR_SHIFT (7u) -#define DMAC13_CHSTAT_n_DL_SHIFT (8u) -#define DMAC13_CHSTAT_n_DW_SHIFT (9u) -#define DMAC13_CHSTAT_n_DER_SHIFT (10u) -#define DMAC13_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC13_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC13_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC13_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC13_CHCTRL_n_STG_SHIFT (2u) -#define DMAC13_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC13_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC13_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC13_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC13_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC13_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC13_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC13_CHCFG_n_SEL_SHIFT (0u) -#define DMAC13_CHCFG_n_REQD_SHIFT (3u) -#define DMAC13_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC13_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC13_CHCFG_n_LVL_SHIFT (6u) -#define DMAC13_CHCFG_n_AM_SHIFT (8u) -#define DMAC13_CHCFG_n_SDS_SHIFT (12u) -#define DMAC13_CHCFG_n_DDS_SHIFT (16u) -#define DMAC13_CHCFG_n_SAD_SHIFT (20u) -#define DMAC13_CHCFG_n_DAD_SHIFT (21u) -#define DMAC13_CHCFG_n_TM_SHIFT (22u) -#define DMAC13_CHCFG_n_DEM_SHIFT (24u) -#define DMAC13_CHCFG_n_TCM_SHIFT (25u) -#define DMAC13_CHCFG_n_SBE_SHIFT (27u) -#define DMAC13_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC13_CHCFG_n_RSW_SHIFT (29u) -#define DMAC13_CHCFG_n_REN_SHIFT (30u) -#define DMAC13_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC13_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC13_CHEXT_n_SCA_SHIFT (4u) -#define DMAC13_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC13_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC13_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC14 ---- */ -#define DMAC14_N0SA_n_SA_SHIFT (0u) - -#define DMAC14_N0DA_n_DA_SHIFT (0u) - -#define DMAC14_N0TB_n_TB_SHIFT (0u) - -#define DMAC14_N1SA_n_SA_SHIFT (0u) - -#define DMAC14_N1DA_n_DA_SHIFT (0u) - -#define DMAC14_N1TB_n_TB_SHIFT (0u) - -#define DMAC14_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC14_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC14_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC14_CHSTAT_n_EN_SHIFT (0u) -#define DMAC14_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC14_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC14_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC14_CHSTAT_n_ER_SHIFT (4u) -#define DMAC14_CHSTAT_n_END_SHIFT (5u) -#define DMAC14_CHSTAT_n_TC_SHIFT (6u) -#define DMAC14_CHSTAT_n_SR_SHIFT (7u) -#define DMAC14_CHSTAT_n_DL_SHIFT (8u) -#define DMAC14_CHSTAT_n_DW_SHIFT (9u) -#define DMAC14_CHSTAT_n_DER_SHIFT (10u) -#define DMAC14_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC14_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC14_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC14_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC14_CHCTRL_n_STG_SHIFT (2u) -#define DMAC14_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC14_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC14_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC14_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC14_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC14_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC14_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC14_CHCFG_n_SEL_SHIFT (0u) -#define DMAC14_CHCFG_n_REQD_SHIFT (3u) -#define DMAC14_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC14_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC14_CHCFG_n_LVL_SHIFT (6u) -#define DMAC14_CHCFG_n_AM_SHIFT (8u) -#define DMAC14_CHCFG_n_SDS_SHIFT (12u) -#define DMAC14_CHCFG_n_DDS_SHIFT (16u) -#define DMAC14_CHCFG_n_SAD_SHIFT (20u) -#define DMAC14_CHCFG_n_DAD_SHIFT (21u) -#define DMAC14_CHCFG_n_TM_SHIFT (22u) -#define DMAC14_CHCFG_n_DEM_SHIFT (24u) -#define DMAC14_CHCFG_n_TCM_SHIFT (25u) -#define DMAC14_CHCFG_n_SBE_SHIFT (27u) -#define DMAC14_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC14_CHCFG_n_RSW_SHIFT (29u) -#define DMAC14_CHCFG_n_REN_SHIFT (30u) -#define DMAC14_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC14_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC14_CHEXT_n_SCA_SHIFT (4u) -#define DMAC14_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC14_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC14_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC15 ---- */ -#define DMAC15_N0SA_n_SA_SHIFT (0u) - -#define DMAC15_N0DA_n_DA_SHIFT (0u) - -#define DMAC15_N0TB_n_TB_SHIFT (0u) - -#define DMAC15_N1SA_n_SA_SHIFT (0u) - -#define DMAC15_N1DA_n_DA_SHIFT (0u) - -#define DMAC15_N1TB_n_TB_SHIFT (0u) - -#define DMAC15_CRSA_n_CRSA_SHIFT (0u) - -#define DMAC15_CRDA_n_CRDA_SHIFT (0u) - -#define DMAC15_CRTB_n_CRTB_SHIFT (0u) - -#define DMAC15_CHSTAT_n_EN_SHIFT (0u) -#define DMAC15_CHSTAT_n_RQST_SHIFT (1u) -#define DMAC15_CHSTAT_n_TACT_SHIFT (2u) -#define DMAC15_CHSTAT_n_SUS_SHIFT (3u) -#define DMAC15_CHSTAT_n_ER_SHIFT (4u) -#define DMAC15_CHSTAT_n_END_SHIFT (5u) -#define DMAC15_CHSTAT_n_TC_SHIFT (6u) -#define DMAC15_CHSTAT_n_SR_SHIFT (7u) -#define DMAC15_CHSTAT_n_DL_SHIFT (8u) -#define DMAC15_CHSTAT_n_DW_SHIFT (9u) -#define DMAC15_CHSTAT_n_DER_SHIFT (10u) -#define DMAC15_CHSTAT_n_MODE_SHIFT (11u) -#define DMAC15_CHSTAT_n_INTMSK_SHIFT (16u) - -#define DMAC15_CHCTRL_n_SETEN_SHIFT (0u) -#define DMAC15_CHCTRL_n_CLREN_SHIFT (1u) -#define DMAC15_CHCTRL_n_STG_SHIFT (2u) -#define DMAC15_CHCTRL_n_SWRST_SHIFT (3u) -#define DMAC15_CHCTRL_n_CLRRQ_SHIFT (4u) -#define DMAC15_CHCTRL_n_CLREND_SHIFT (5u) -#define DMAC15_CHCTRL_n_CLRTC_SHIFT (6u) -#define DMAC15_CHCTRL_n_SETSUS_SHIFT (8u) -#define DMAC15_CHCTRL_n_CLRSUS_SHIFT (9u) -#define DMAC15_CHCTRL_n_SETINTMSK_SHIFT (16u) -#define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT (17u) - -#define DMAC15_CHCFG_n_SEL_SHIFT (0u) -#define DMAC15_CHCFG_n_REQD_SHIFT (3u) -#define DMAC15_CHCFG_n_LOEN_SHIFT (4u) -#define DMAC15_CHCFG_n_HIEN_SHIFT (5u) -#define DMAC15_CHCFG_n_LVL_SHIFT (6u) -#define DMAC15_CHCFG_n_AM_SHIFT (8u) -#define DMAC15_CHCFG_n_SDS_SHIFT (12u) -#define DMAC15_CHCFG_n_DDS_SHIFT (16u) -#define DMAC15_CHCFG_n_SAD_SHIFT (20u) -#define DMAC15_CHCFG_n_DAD_SHIFT (21u) -#define DMAC15_CHCFG_n_TM_SHIFT (22u) -#define DMAC15_CHCFG_n_DEM_SHIFT (24u) -#define DMAC15_CHCFG_n_TCM_SHIFT (25u) -#define DMAC15_CHCFG_n_SBE_SHIFT (27u) -#define DMAC15_CHCFG_n_RSEL_SHIFT (28u) -#define DMAC15_CHCFG_n_RSW_SHIFT (29u) -#define DMAC15_CHCFG_n_REN_SHIFT (30u) -#define DMAC15_CHCFG_n_DMS_SHIFT (31u) - -#define DMAC15_CHITVL_n_ITVL_SHIFT (0u) - -#define DMAC15_CHEXT_n_SCA_SHIFT (4u) -#define DMAC15_CHEXT_n_DCA_SHIFT (12u) - -#define DMAC15_NXLA_n_NXLA_SHIFT (0u) - -#define DMAC15_CRLA_n_CRLA_SHIFT (0u) - -/* ---- DMAC8-15 ---- */ -#define DMAC815_DCTRL_8_15_PR_SHIFT (0u) -#define DMAC815_DCTRL_8_15_LVINT_SHIFT (1u) -#define DMAC815_DCTRL_8_15_LDCA_SHIFT (2u) -#define DMAC815_DCTRL_8_15_LWCA_SHIFT (10u) - -#define DMAC815_DSTAT_EN_8_15_EN8_SHIFT (0u) -#define DMAC815_DSTAT_EN_8_15_EN9_SHIFT (1u) -#define DMAC815_DSTAT_EN_8_15_EN10_SHIFT (2u) -#define DMAC815_DSTAT_EN_8_15_EN11_SHIFT (3u) -#define DMAC815_DSTAT_EN_8_15_EN12_SHIFT (4u) -#define DMAC815_DSTAT_EN_8_15_EN13_SHIFT (5u) -#define DMAC815_DSTAT_EN_8_15_EN14_SHIFT (6u) -#define DMAC815_DSTAT_EN_8_15_EN15_SHIFT (7u) - -#define DMAC815_DSTAT_ER_8_15_ER8_SHIFT (0u) -#define DMAC815_DSTAT_ER_8_15_ER9_SHIFT (1u) -#define DMAC815_DSTAT_ER_8_15_ER10_SHIFT (2u) -#define DMAC815_DSTAT_ER_8_15_ER11_SHIFT (3u) -#define DMAC815_DSTAT_ER_8_15_ER12_SHIFT (4u) -#define DMAC815_DSTAT_ER_8_15_ER13_SHIFT (5u) -#define DMAC815_DSTAT_ER_8_15_ER14_SHIFT (6u) -#define DMAC815_DSTAT_ER_8_15_ER15_SHIFT (7u) - -#define DMAC815_DSTAT_END_8_15_END8_SHIFT (0u) -#define DMAC815_DSTAT_END_8_15_END9_SHIFT (1u) -#define DMAC815_DSTAT_END_8_15_END10_SHIFT (2u) -#define DMAC815_DSTAT_END_8_15_END11_SHIFT (3u) -#define DMAC815_DSTAT_END_8_15_END12_SHIFT (4u) -#define DMAC815_DSTAT_END_8_15_END13_SHIFT (5u) -#define DMAC815_DSTAT_END_8_15_END14_SHIFT (6u) -#define DMAC815_DSTAT_END_8_15_END15_SHIFT (7u) - -#define DMAC815_DSTAT_TC_8_15_TC8_SHIFT (0u) -#define DMAC815_DSTAT_TC_8_15_TC9_SHIFT (1u) -#define DMAC815_DSTAT_TC_8_15_TC10_SHIFT (2u) -#define DMAC815_DSTAT_TC_8_15_TC11_SHIFT (3u) -#define DMAC815_DSTAT_TC_8_15_TC12_SHIFT (4u) -#define DMAC815_DSTAT_TC_8_15_TC13_SHIFT (5u) -#define DMAC815_DSTAT_TC_8_15_TC14_SHIFT (6u) -#define DMAC815_DSTAT_TC_8_15_TC15_SHIFT (7u) - -#define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT (0u) -#define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT (1u) -#define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT (2u) -#define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT (3u) -#define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT (4u) -#define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT (5u) -#define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT (6u) -#define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT (7u) - -/* ---- DMAC0-1 ---- */ -#define DMAC01_DMARS_CH0_RID_SHIFT (0u) -#define DMAC01_DMARS_CH0_MID_SHIFT (2u) -#define DMAC01_DMARS_CH1_RID_SHIFT (16u) -#define DMAC01_DMARS_CH1_MID_SHIFT (18u) - -/* ---- DMAC2-3 ---- */ -#define DMAC23_DMARS_CH2_RID_SHIFT (0u) -#define DMAC23_DMARS_CH2_MID_SHIFT (2u) -#define DMAC23_DMARS_CH3_RID_SHIFT (16u) -#define DMAC23_DMARS_CH3_MID_SHIFT (18u) - -/* ---- DMAC4-5 ---- */ -#define DMAC45_DMARS_CH4_RID_SHIFT (0u) -#define DMAC45_DMARS_CH4_MID_SHIFT (2u) -#define DMAC45_DMARS_CH5_RID_SHIFT (16u) -#define DMAC45_DMARS_CH5_MID_SHIFT (18u) - -/* ---- DMAC6-7 ---- */ -#define DMAC67_DMARS_CH6_RID_SHIFT (0u) -#define DMAC67_DMARS_CH6_MID_SHIFT (2u) -#define DMAC67_DMARS_CH7_RID_SHIFT (16u) -#define DMAC67_DMARS_CH7_MID_SHIFT (18u) - -/* ---- DMAC8-9 ---- */ -#define DMAC89_DMARS_CH8_RID_SHIFT (0u) -#define DMAC89_DMARS_CH8_MID_SHIFT (2u) -#define DMAC89_DMARS_CH9_RID_SHIFT (16u) -#define DMAC89_DMARS_CH9_MID_SHIFT (18u) - -/* ---- DMAC10-11 ---- */ -#define DMAC1011_DMARS_CH10_RID_SHIFT (0u) -#define DMAC1011_DMARS_CH10_MID_SHIFT (2u) -#define DMAC1011_DMARS_CH11_RID_SHIFT (16u) -#define DMAC1011_DMARS_CH11_MID_SHIFT (18u) - -/* ---- DMAC12-13 ---- */ -#define DMAC1213_DMARS_CH12_RID_SHIFT (0u) -#define DMAC1213_DMARS_CH12_MID_SHIFT (2u) -#define DMAC1213_DMARS_CH13_RID_SHIFT (16u) -#define DMAC1213_DMARS_CH13_MID_SHIFT (18u) - -/* ---- DMAC14-15 ---- */ -#define DMAC1415_DMARS_CH14_RID_SHIFT (0u) -#define DMAC1415_DMARS_CH14_MID_SHIFT (2u) -#define DMAC1415_DMARS_CH15_RID_SHIFT (16u) -#define DMAC1415_DMARS_CH15_MID_SHIFT (18u) - - -#endif /* DMAC_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h deleted file mode 100644 index 94ba619540c..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h +++ /dev/null @@ -1,5793 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : gpio_iobitmask.h -* $Rev: 1115 $ -* $Date:: 2014-07-09 15:35:02 +0900#$ -* Description : General purpose I/O ports register define header -*******************************************************************************/ -#ifndef GPIO_IOBITMASK_H -#define GPIO_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -/* ---- P0 ---- */ -#define GPIO_PPR0_PPR00 (0x0001u) -#define GPIO_PPR0_PPR01 (0x0002u) -#define GPIO_PPR0_PPR02 (0x0004u) -#define GPIO_PPR0_PPR03 (0x0008u) -#define GPIO_PPR0_PPR04 (0x0010u) -#define GPIO_PPR0_PPR05 (0x0020u) - -#define GPIO_PMC0_PMC04 (0x0010u) -#define GPIO_PMC0_PMC05 (0x0020u) - -#define GPIO_PMCSR0_PMCSR04 (0x00000010uL) -#define GPIO_PMCSR0_PMCSR05 (0x00000020uL) - -#define GPIO_PIBC0_PIBC00 (0x0001u) -#define GPIO_PIBC0_PIBC01 (0x0002u) -#define GPIO_PIBC0_PIBC02 (0x0004u) -#define GPIO_PIBC0_PIBC03 (0x0008u) -#define GPIO_PIBC0_PIBC04 (0x0010u) -#define GPIO_PIBC0_PIBC05 (0x0020u) - -/* ---- P1 ---- */ -#define GPIO_P1_P10 (0x0001u) -#define GPIO_P1_P11 (0x0002u) -#define GPIO_P1_P12 (0x0004u) -#define GPIO_P1_P13 (0x0008u) -#define GPIO_P1_P14 (0x0010u) -#define GPIO_P1_P15 (0x0020u) -#define GPIO_P1_P16 (0x0040u) -#define GPIO_P1_P17 (0x0080u) - -#define GPIO_PSR1_PSR10 (0x00000001uL) -#define GPIO_PSR1_PSR11 (0x00000002uL) -#define GPIO_PSR1_PSR12 (0x00000004uL) -#define GPIO_PSR1_PSR13 (0x00000008uL) -#define GPIO_PSR1_PSR14 (0x00000010uL) -#define GPIO_PSR1_PSR15 (0x00000020uL) -#define GPIO_PSR1_PSR16 (0x00000040uL) -#define GPIO_PSR1_PSR17 (0x00000080uL) -#define GPIO_PSR1_PSR116 (0x00010000uL) -#define GPIO_PSR1_PSR117 (0x00020000uL) -#define GPIO_PSR1_PSR118 (0x00040000uL) -#define GPIO_PSR1_PSR119 (0x00080000uL) -#define GPIO_PSR1_PSR120 (0x00100000uL) -#define GPIO_PSR1_PSR121 (0x00200000uL) -#define GPIO_PSR1_PSR122 (0x00400000uL) -#define GPIO_PSR1_PSR123 (0x00800000uL) - -#define GPIO_PPR1_PPR10 (0x0001u) -#define GPIO_PPR1_PPR11 (0x0002u) -#define GPIO_PPR1_PPR12 (0x0004u) -#define GPIO_PPR1_PPR13 (0x0008u) -#define GPIO_PPR1_PPR14 (0x0010u) -#define GPIO_PPR1_PPR15 (0x0020u) -#define GPIO_PPR1_PPR16 (0x0040u) -#define GPIO_PPR1_PPR17 (0x0080u) -#define GPIO_PPR1_PPR18 (0x0100u) -#define GPIO_PPR1_PPR19 (0x0200u) -#define GPIO_PPR1_PPR110 (0x0400u) -#define GPIO_PPR1_PPR111 (0x0800u) -#define GPIO_PPR1_PPR112 (0x1000u) -#define GPIO_PPR1_PPR113 (0x2000u) -#define GPIO_PPR1_PPR114 (0x4000u) -#define GPIO_PPR1_PPR115 (0x8000u) - -#define GPIO_PM1_PM10 (0x0001u) -#define GPIO_PM1_PM11 (0x0002u) -#define GPIO_PM1_PM12 (0x0004u) -#define GPIO_PM1_PM13 (0x0008u) -#define GPIO_PM1_PM14 (0x0010u) -#define GPIO_PM1_PM15 (0x0020u) -#define GPIO_PM1_PM16 (0x0040u) -#define GPIO_PM1_PM17 (0x0080u) - -#define GPIO_PMC1_PMC10 (0x0001u) -#define GPIO_PMC1_PMC11 (0x0002u) -#define GPIO_PMC1_PMC12 (0x0004u) -#define GPIO_PMC1_PMC13 (0x0008u) -#define GPIO_PMC1_PMC14 (0x0010u) -#define GPIO_PMC1_PMC15 (0x0020u) -#define GPIO_PMC1_PMC16 (0x0040u) -#define GPIO_PMC1_PMC17 (0x0080u) -#define GPIO_PMC1_PMC18 (0x0100u) -#define GPIO_PMC1_PMC19 (0x0200u) -#define GPIO_PMC1_PMC110 (0x0400u) -#define GPIO_PMC1_PMC111 (0x0800u) -#define GPIO_PMC1_PMC112 (0x1000u) -#define GPIO_PMC1_PMC113 (0x2000u) -#define GPIO_PMC1_PMC114 (0x4000u) -#define GPIO_PMC1_PMC115 (0x8000u) - -#define GPIO_PFC1_PFC10 (0x0001u) -#define GPIO_PFC1_PFC11 (0x0002u) -#define GPIO_PFC1_PFC12 (0x0004u) -#define GPIO_PFC1_PFC13 (0x0008u) -#define GPIO_PFC1_PFC14 (0x0010u) -#define GPIO_PFC1_PFC15 (0x0020u) -#define GPIO_PFC1_PFC16 (0x0040u) -#define GPIO_PFC1_PFC17 (0x0080u) -#define GPIO_PFC1_PFC18 (0x0100u) -#define GPIO_PFC1_PFC19 (0x0200u) -#define GPIO_PFC1_PFC110 (0x0400u) -#define GPIO_PFC1_PFC111 (0x0800u) -#define GPIO_PFC1_PFC112 (0x1000u) -#define GPIO_PFC1_PFC113 (0x2000u) -#define GPIO_PFC1_PFC114 (0x4000u) -#define GPIO_PFC1_PFC115 (0x8000u) - -#define GPIO_PFCE1_PFCE10 (0x0001u) -#define GPIO_PFCE1_PFCE11 (0x0002u) -#define GPIO_PFCE1_PFCE12 (0x0004u) -#define GPIO_PFCE1_PFCE13 (0x0008u) -#define GPIO_PFCE1_PFCE14 (0x0010u) -#define GPIO_PFCE1_PFCE15 (0x0020u) -#define GPIO_PFCE1_PFCE16 (0x0040u) -#define GPIO_PFCE1_PFCE17 (0x0080u) -#define GPIO_PFCE1_PFCE18 (0x0100u) -#define GPIO_PFCE1_PFCE19 (0x0200u) -#define GPIO_PFCE1_PFCE110 (0x0400u) -#define GPIO_PFCE1_PFCE111 (0x0800u) -#define GPIO_PFCE1_PFCE112 (0x1000u) -#define GPIO_PFCE1_PFCE113 (0x2000u) -#define GPIO_PFCE1_PFCE114 (0x4000u) -#define GPIO_PFCE1_PFCE115 (0x8000u) - -#define GPIO_PNOT1_PNOT10 (0x0001u) -#define GPIO_PNOT1_PNOT11 (0x0002u) -#define GPIO_PNOT1_PNOT12 (0x0004u) -#define GPIO_PNOT1_PNOT13 (0x0008u) -#define GPIO_PNOT1_PNOT14 (0x0010u) -#define GPIO_PNOT1_PNOT15 (0x0020u) -#define GPIO_PNOT1_PNOT16 (0x0040u) -#define GPIO_PNOT1_PNOT17 (0x0080u) - -#define GPIO_PMSR1_PMSR10 (0x00000001uL) -#define GPIO_PMSR1_PMSR11 (0x00000002uL) -#define GPIO_PMSR1_PMSR12 (0x00000004uL) -#define GPIO_PMSR1_PMSR13 (0x00000008uL) -#define GPIO_PMSR1_PMSR14 (0x00000010uL) -#define GPIO_PMSR1_PMSR15 (0x00000020uL) -#define GPIO_PMSR1_PMSR16 (0x00000040uL) -#define GPIO_PMSR1_PMSR17 (0x00000080uL) -#define GPIO_PMSR1_PMSR116 (0x00010000uL) -#define GPIO_PMSR1_PMSR117 (0x00020000uL) -#define GPIO_PMSR1_PMSR118 (0x00040000uL) -#define GPIO_PMSR1_PMSR119 (0x00080000uL) -#define GPIO_PMSR1_PMSR120 (0x00100000uL) -#define GPIO_PMSR1_PMSR121 (0x00200000uL) -#define GPIO_PMSR1_PMSR122 (0x00400000uL) -#define GPIO_PMSR1_PMSR123 (0x00800000uL) - -#define GPIO_PMCSR1_PMCSR10 (0x00000001uL) -#define GPIO_PMCSR1_PMCSR11 (0x00000002uL) -#define GPIO_PMCSR1_PMCSR12 (0x00000004uL) -#define GPIO_PMCSR1_PMCSR13 (0x00000008uL) -#define GPIO_PMCSR1_PMCSR14 (0x00000010uL) -#define GPIO_PMCSR1_PMCSR15 (0x00000020uL) -#define GPIO_PMCSR1_PMCSR16 (0x00000040uL) -#define GPIO_PMCSR1_PMCSR17 (0x00000080uL) -#define GPIO_PMCSR1_PMCSR116 (0x00010000uL) -#define GPIO_PMCSR1_PMCSR117 (0x00020000uL) -#define GPIO_PMCSR1_PMCSR118 (0x00040000uL) -#define GPIO_PMCSR1_PMCSR119 (0x00080000uL) -#define GPIO_PMCSR1_PMCSR120 (0x00100000uL) -#define GPIO_PMCSR1_PMCSR121 (0x00200000uL) -#define GPIO_PMCSR1_PMCSR122 (0x00400000uL) -#define GPIO_PMCSR1_PMCSR123 (0x00800000uL) - -#define GPIO_PFCAE1_PFCAE10 (0x0001u) -#define GPIO_PFCAE1_PFCAE11 (0x0002u) -#define GPIO_PFCAE1_PFCAE12 (0x0004u) -#define GPIO_PFCAE1_PFCAE13 (0x0008u) -#define GPIO_PFCAE1_PFCAE14 (0x0010u) -#define GPIO_PFCAE1_PFCAE15 (0x0020u) -#define GPIO_PFCAE1_PFCAE16 (0x0040u) -#define GPIO_PFCAE1_PFCAE17 (0x0080u) -#define GPIO_PFCAE1_PFCAE18 (0x0100u) -#define GPIO_PFCAE1_PFCAE19 (0x0200u) -#define GPIO_PFCAE1_PFCAE110 (0x0400u) -#define GPIO_PFCAE1_PFCAE111 (0x0800u) -#define GPIO_PFCAE1_PFCAE112 (0x1000u) -#define GPIO_PFCAE1_PFCAE113 (0x2000u) -#define GPIO_PFCAE1_PFCAE114 (0x4000u) -#define GPIO_PFCAE1_PFCAE115 (0x8000u) - -#define GPIO_PIBC1_PIBC10 (0x0001u) -#define GPIO_PIBC1_PIBC11 (0x0002u) -#define GPIO_PIBC1_PIBC12 (0x0004u) -#define GPIO_PIBC1_PIBC13 (0x0008u) -#define GPIO_PIBC1_PIBC14 (0x0010u) -#define GPIO_PIBC1_PIBC15 (0x0020u) -#define GPIO_PIBC1_PIBC16 (0x0040u) -#define GPIO_PIBC1_PIBC17 (0x0080u) -#define GPIO_PIBC1_PIBC18 (0x0100u) -#define GPIO_PIBC1_PIBC19 (0x0200u) -#define GPIO_PIBC1_PIBC110 (0x0400u) -#define GPIO_PIBC1_PIBC111 (0x0800u) -#define GPIO_PIBC1_PIBC112 (0x1000u) -#define GPIO_PIBC1_PIBC113 (0x2000u) -#define GPIO_PIBC1_PIBC114 (0x4000u) -#define GPIO_PIBC1_PIBC115 (0x8000u) - -#define GPIO_PBDC1_PBDC10 (0x0001u) -#define GPIO_PBDC1_PBDC11 (0x0002u) -#define GPIO_PBDC1_PBDC12 (0x0004u) -#define GPIO_PBDC1_PBDC13 (0x0008u) -#define GPIO_PBDC1_PBDC14 (0x0010u) -#define GPIO_PBDC1_PBDC15 (0x0020u) -#define GPIO_PBDC1_PBDC16 (0x0040u) -#define GPIO_PBDC1_PBDC17 (0x0080u) -#define GPIO_PBDC1_PBDC18 (0x0100u) -#define GPIO_PBDC1_PBDC19 (0x0200u) -#define GPIO_PBDC1_PBDC110 (0x0400u) -#define GPIO_PBDC1_PBDC111 (0x0800u) -#define GPIO_PBDC1_PBDC112 (0x1000u) -#define GPIO_PBDC1_PBDC113 (0x2000u) -#define GPIO_PBDC1_PBDC114 (0x4000u) -#define GPIO_PBDC1_PBDC115 (0x8000u) - -#define GPIO_PIPC1_PIPC10 (0x0001u) -#define GPIO_PIPC1_PIPC11 (0x0002u) -#define GPIO_PIPC1_PIPC12 (0x0004u) -#define GPIO_PIPC1_PIPC13 (0x0008u) -#define GPIO_PIPC1_PIPC14 (0x0010u) -#define GPIO_PIPC1_PIPC15 (0x0020u) -#define GPIO_PIPC1_PIPC16 (0x0040u) -#define GPIO_PIPC1_PIPC17 (0x0080u) - -/* ---- P2 ---- */ -#define GPIO_P2_P20 (0x0001u) -#define GPIO_P2_P21 (0x0002u) -#define GPIO_P2_P22 (0x0004u) -#define GPIO_P2_P23 (0x0008u) -#define GPIO_P2_P24 (0x0010u) -#define GPIO_P2_P25 (0x0020u) -#define GPIO_P2_P26 (0x0040u) -#define GPIO_P2_P27 (0x0080u) -#define GPIO_P2_P28 (0x0100u) -#define GPIO_P2_P29 (0x0200u) -#define GPIO_P2_P210 (0x0400u) -#define GPIO_P2_P211 (0x0800u) -#define GPIO_P2_P212 (0x1000u) -#define GPIO_P2_P213 (0x2000u) -#define GPIO_P2_P214 (0x4000u) -#define GPIO_P2_P215 (0x8000u) - -#define GPIO_PSR2_PSR20 (0x00000001uL) -#define GPIO_PSR2_PSR21 (0x00000002uL) -#define GPIO_PSR2_PSR22 (0x00000004uL) -#define GPIO_PSR2_PSR23 (0x00000008uL) -#define GPIO_PSR2_PSR24 (0x00000010uL) -#define GPIO_PSR2_PSR25 (0x00000020uL) -#define GPIO_PSR2_PSR26 (0x00000040uL) -#define GPIO_PSR2_PSR27 (0x00000080uL) -#define GPIO_PSR2_PSR28 (0x00000100uL) -#define GPIO_PSR2_PSR29 (0x00000200uL) -#define GPIO_PSR2_PSR210 (0x00000400uL) -#define GPIO_PSR2_PSR211 (0x00000800uL) -#define GPIO_PSR2_PSR212 (0x00001000uL) -#define GPIO_PSR2_PSR213 (0x00002000uL) -#define GPIO_PSR2_PSR214 (0x00004000uL) -#define GPIO_PSR2_PSR215 (0x00008000uL) -#define GPIO_PSR2_PSR216 (0x00010000uL) -#define GPIO_PSR2_PSR217 (0x00020000uL) -#define GPIO_PSR2_PSR218 (0x00040000uL) -#define GPIO_PSR2_PSR219 (0x00080000uL) -#define GPIO_PSR2_PSR220 (0x00100000uL) -#define GPIO_PSR2_PSR221 (0x00200000uL) -#define GPIO_PSR2_PSR222 (0x00400000uL) -#define GPIO_PSR2_PSR223 (0x00800000uL) -#define GPIO_PSR2_PSR224 (0x01000000uL) -#define GPIO_PSR2_PSR225 (0x02000000uL) -#define GPIO_PSR2_PSR226 (0x04000000uL) -#define GPIO_PSR2_PSR227 (0x08000000uL) -#define GPIO_PSR2_PSR228 (0x10000000uL) -#define GPIO_PSR2_PSR229 (0x20000000uL) -#define GPIO_PSR2_PSR230 (0x40000000uL) -#define GPIO_PSR2_PSR231 (0x80000000uL) - -#define GPIO_PPR2_PPR20 (0x0001u) -#define GPIO_PPR2_PPR21 (0x0002u) -#define GPIO_PPR2_PPR22 (0x0004u) -#define GPIO_PPR2_PPR23 (0x0008u) -#define GPIO_PPR2_PPR24 (0x0010u) -#define GPIO_PPR2_PPR25 (0x0020u) -#define GPIO_PPR2_PPR26 (0x0040u) -#define GPIO_PPR2_PPR27 (0x0080u) -#define GPIO_PPR2_PPR28 (0x0100u) -#define GPIO_PPR2_PPR29 (0x0200u) -#define GPIO_PPR2_PPR210 (0x0400u) -#define GPIO_PPR2_PPR211 (0x0800u) -#define GPIO_PPR2_PPR212 (0x1000u) -#define GPIO_PPR2_PPR213 (0x2000u) -#define GPIO_PPR2_PPR214 (0x4000u) -#define GPIO_PPR2_PPR215 (0x8000u) - -#define GPIO_PM2_PM20 (0x0001u) -#define GPIO_PM2_PM21 (0x0002u) -#define GPIO_PM2_PM22 (0x0004u) -#define GPIO_PM2_PM23 (0x0008u) -#define GPIO_PM2_PM24 (0x0010u) -#define GPIO_PM2_PM25 (0x0020u) -#define GPIO_PM2_PM26 (0x0040u) -#define GPIO_PM2_PM27 (0x0080u) -#define GPIO_PM2_PM28 (0x0100u) -#define GPIO_PM2_PM29 (0x0200u) -#define GPIO_PM2_PM210 (0x0400u) -#define GPIO_PM2_PM211 (0x0800u) -#define GPIO_PM2_PM212 (0x1000u) -#define GPIO_PM2_PM213 (0x2000u) -#define GPIO_PM2_PM214 (0x4000u) -#define GPIO_PM2_PM215 (0x8000u) - -#define GPIO_PMC2_PMC20 (0x0001u) -#define GPIO_PMC2_PMC21 (0x0002u) -#define GPIO_PMC2_PMC22 (0x0004u) -#define GPIO_PMC2_PMC23 (0x0008u) -#define GPIO_PMC2_PMC24 (0x0010u) -#define GPIO_PMC2_PMC25 (0x0020u) -#define GPIO_PMC2_PMC26 (0x0040u) -#define GPIO_PMC2_PMC27 (0x0080u) -#define GPIO_PMC2_PMC28 (0x0100u) -#define GPIO_PMC2_PMC29 (0x0200u) -#define GPIO_PMC2_PMC210 (0x0400u) -#define GPIO_PMC2_PMC211 (0x0800u) -#define GPIO_PMC2_PMC212 (0x1000u) -#define GPIO_PMC2_PMC213 (0x2000u) -#define GPIO_PMC2_PMC214 (0x4000u) -#define GPIO_PMC2_PMC215 (0x8000u) - -#define GPIO_PFC2_PFC20 (0x0001u) -#define GPIO_PFC2_PFC21 (0x0002u) -#define GPIO_PFC2_PFC22 (0x0004u) -#define GPIO_PFC2_PFC23 (0x0008u) -#define GPIO_PFC2_PFC24 (0x0010u) -#define GPIO_PFC2_PFC25 (0x0020u) -#define GPIO_PFC2_PFC26 (0x0040u) -#define GPIO_PFC2_PFC27 (0x0080u) -#define GPIO_PFC2_PFC28 (0x0100u) -#define GPIO_PFC2_PFC29 (0x0200u) -#define GPIO_PFC2_PFC210 (0x0400u) -#define GPIO_PFC2_PFC211 (0x0800u) -#define GPIO_PFC2_PFC212 (0x1000u) -#define GPIO_PFC2_PFC213 (0x2000u) -#define GPIO_PFC2_PFC214 (0x4000u) -#define GPIO_PFC2_PFC215 (0x8000u) - -#define GPIO_PFCE2_PFCE20 (0x0001u) -#define GPIO_PFCE2_PFCE21 (0x0002u) -#define GPIO_PFCE2_PFCE22 (0x0004u) -#define GPIO_PFCE2_PFCE23 (0x0008u) -#define GPIO_PFCE2_PFCE24 (0x0010u) -#define GPIO_PFCE2_PFCE25 (0x0020u) -#define GPIO_PFCE2_PFCE26 (0x0040u) -#define GPIO_PFCE2_PFCE27 (0x0080u) -#define GPIO_PFCE2_PFCE28 (0x0100u) -#define GPIO_PFCE2_PFCE29 (0x0200u) -#define GPIO_PFCE2_PFCE210 (0x0400u) -#define GPIO_PFCE2_PFCE211 (0x0800u) -#define GPIO_PFCE2_PFCE212 (0x1000u) -#define GPIO_PFCE2_PFCE213 (0x2000u) -#define GPIO_PFCE2_PFCE214 (0x4000u) -#define GPIO_PFCE2_PFCE215 (0x8000u) - -#define GPIO_PNOT2_PNOT20 (0x0001u) -#define GPIO_PNOT2_PNOT21 (0x0002u) -#define GPIO_PNOT2_PNOT22 (0x0004u) -#define GPIO_PNOT2_PNOT23 (0x0008u) -#define GPIO_PNOT2_PNOT24 (0x0010u) -#define GPIO_PNOT2_PNOT25 (0x0020u) -#define GPIO_PNOT2_PNOT26 (0x0040u) -#define GPIO_PNOT2_PNOT27 (0x0080u) -#define GPIO_PNOT2_PNOT28 (0x0100u) -#define GPIO_PNOT2_PNOT29 (0x0200u) -#define GPIO_PNOT2_PNOT210 (0x0400u) -#define GPIO_PNOT2_PNOT211 (0x0800u) -#define GPIO_PNOT2_PNOT212 (0x1000u) -#define GPIO_PNOT2_PNOT213 (0x2000u) -#define GPIO_PNOT2_PNOT214 (0x4000u) -#define GPIO_PNOT2_PNOT215 (0x8000u) - -#define GPIO_PMSR2_PMSR20 (0x00000001uL) -#define GPIO_PMSR2_PMSR21 (0x00000002uL) -#define GPIO_PMSR2_PMSR22 (0x00000004uL) -#define GPIO_PMSR2_PMSR23 (0x00000008uL) -#define GPIO_PMSR2_PMSR24 (0x00000010uL) -#define GPIO_PMSR2_PMSR25 (0x00000020uL) -#define GPIO_PMSR2_PMSR26 (0x00000040uL) -#define GPIO_PMSR2_PMSR27 (0x00000080uL) -#define GPIO_PMSR2_PMSR28 (0x00000100uL) -#define GPIO_PMSR2_PMSR29 (0x00000200uL) -#define GPIO_PMSR2_PMSR210 (0x00000400uL) -#define GPIO_PMSR2_PMSR211 (0x00000800uL) -#define GPIO_PMSR2_PMSR212 (0x00001000uL) -#define GPIO_PMSR2_PMSR213 (0x00002000uL) -#define GPIO_PMSR2_PMSR214 (0x00004000uL) -#define GPIO_PMSR2_PMSR215 (0x00008000uL) -#define GPIO_PMSR2_PMSR216 (0x00010000uL) -#define GPIO_PMSR2_PMSR217 (0x00020000uL) -#define GPIO_PMSR2_PMSR218 (0x00040000uL) -#define GPIO_PMSR2_PMSR219 (0x00080000uL) -#define GPIO_PMSR2_PMSR220 (0x00100000uL) -#define GPIO_PMSR2_PMSR221 (0x00200000uL) -#define GPIO_PMSR2_PMSR222 (0x00400000uL) -#define GPIO_PMSR2_PMSR223 (0x00800000uL) -#define GPIO_PMSR2_PMSR224 (0x01000000uL) -#define GPIO_PMSR2_PMSR225 (0x02000000uL) -#define GPIO_PMSR2_PMSR226 (0x04000000uL) -#define GPIO_PMSR2_PMSR227 (0x08000000uL) -#define GPIO_PMSR2_PMSR228 (0x10000000uL) -#define GPIO_PMSR2_PMSR229 (0x20000000uL) -#define GPIO_PMSR2_PMSR230 (0x40000000uL) -#define GPIO_PMSR2_PMSR231 (0x80000000uL) - -#define GPIO_PMCSR2_PMCSR20 (0x00000001uL) -#define GPIO_PMCSR2_PMCSR21 (0x00000002uL) -#define GPIO_PMCSR2_PMCSR22 (0x00000004uL) -#define GPIO_PMCSR2_PMCSR23 (0x00000008uL) -#define GPIO_PMCSR2_PMCSR24 (0x00000010uL) -#define GPIO_PMCSR2_PMCSR25 (0x00000020uL) -#define GPIO_PMCSR2_PMCSR26 (0x00000040uL) -#define GPIO_PMCSR2_PMCSR27 (0x00000080uL) -#define GPIO_PMCSR2_PMCSR28 (0x00000100uL) -#define GPIO_PMCSR2_PMCSR29 (0x00000200uL) -#define GPIO_PMCSR2_PMCSR210 (0x00000400uL) -#define GPIO_PMCSR2_PMCSR211 (0x00000800uL) -#define GPIO_PMCSR2_PMCSR212 (0x00001000uL) -#define GPIO_PMCSR2_PMCSR213 (0x00002000uL) -#define GPIO_PMCSR2_PMCSR214 (0x00004000uL) -#define GPIO_PMCSR2_PMCSR215 (0x00008000uL) -#define GPIO_PMCSR2_PMCSR216 (0x00010000uL) -#define GPIO_PMCSR2_PMCSR217 (0x00020000uL) -#define GPIO_PMCSR2_PMCSR218 (0x00040000uL) -#define GPIO_PMCSR2_PMCSR219 (0x00080000uL) -#define GPIO_PMCSR2_PMCSR220 (0x00100000uL) -#define GPIO_PMCSR2_PMCSR221 (0x00200000uL) -#define GPIO_PMCSR2_PMCSR222 (0x00400000uL) -#define GPIO_PMCSR2_PMCSR223 (0x00800000uL) -#define GPIO_PMCSR2_PMCSR224 (0x01000000uL) -#define GPIO_PMCSR2_PMCSR225 (0x02000000uL) -#define GPIO_PMCSR2_PMCSR226 (0x04000000uL) -#define GPIO_PMCSR2_PMCSR227 (0x08000000uL) -#define GPIO_PMCSR2_PMCSR228 (0x10000000uL) -#define GPIO_PMCSR2_PMCSR229 (0x20000000uL) -#define GPIO_PMCSR2_PMCSR230 (0x40000000uL) -#define GPIO_PMCSR2_PMCSR231 (0x80000000uL) - -#define GPIO_PFCAE2_PFCAE20 (0x0001u) -#define GPIO_PFCAE2_PFCAE21 (0x0002u) -#define GPIO_PFCAE2_PFCAE22 (0x0004u) -#define GPIO_PFCAE2_PFCAE23 (0x0008u) -#define GPIO_PFCAE2_PFCAE24 (0x0010u) -#define GPIO_PFCAE2_PFCAE25 (0x0020u) -#define GPIO_PFCAE2_PFCAE26 (0x0040u) -#define GPIO_PFCAE2_PFCAE27 (0x0080u) -#define GPIO_PFCAE2_PFCAE28 (0x0100u) -#define GPIO_PFCAE2_PFCAE29 (0x0200u) -#define GPIO_PFCAE2_PFCAE210 (0x0400u) -#define GPIO_PFCAE2_PFCAE211 (0x0800u) -#define GPIO_PFCAE2_PFCAE212 (0x1000u) -#define GPIO_PFCAE2_PFCAE213 (0x2000u) -#define GPIO_PFCAE2_PFCAE214 (0x4000u) -#define GPIO_PFCAE2_PFCAE215 (0x8000u) - -#define GPIO_PIBC2_PIBC20 (0x0001u) -#define GPIO_PIBC2_PIBC21 (0x0002u) -#define GPIO_PIBC2_PIBC22 (0x0004u) -#define GPIO_PIBC2_PIBC23 (0x0008u) -#define GPIO_PIBC2_PIBC24 (0x0010u) -#define GPIO_PIBC2_PIBC25 (0x0020u) -#define GPIO_PIBC2_PIBC26 (0x0040u) -#define GPIO_PIBC2_PIBC27 (0x0080u) -#define GPIO_PIBC2_PIBC28 (0x0100u) -#define GPIO_PIBC2_PIBC29 (0x0200u) -#define GPIO_PIBC2_PIBC210 (0x0400u) -#define GPIO_PIBC2_PIBC211 (0x0800u) -#define GPIO_PIBC2_PIBC212 (0x1000u) -#define GPIO_PIBC2_PIBC213 (0x2000u) -#define GPIO_PIBC2_PIBC214 (0x4000u) -#define GPIO_PIBC2_PIBC215 (0x8000u) - -#define GPIO_PBDC2_PBDC20 (0x0001u) -#define GPIO_PBDC2_PBDC21 (0x0002u) -#define GPIO_PBDC2_PBDC22 (0x0004u) -#define GPIO_PBDC2_PBDC23 (0x0008u) -#define GPIO_PBDC2_PBDC24 (0x0010u) -#define GPIO_PBDC2_PBDC25 (0x0020u) -#define GPIO_PBDC2_PBDC26 (0x0040u) -#define GPIO_PBDC2_PBDC27 (0x0080u) -#define GPIO_PBDC2_PBDC28 (0x0100u) -#define GPIO_PBDC2_PBDC29 (0x0200u) -#define GPIO_PBDC2_PBDC210 (0x0400u) -#define GPIO_PBDC2_PBDC211 (0x0800u) -#define GPIO_PBDC2_PBDC212 (0x1000u) -#define GPIO_PBDC2_PBDC213 (0x2000u) -#define GPIO_PBDC2_PBDC214 (0x4000u) -#define GPIO_PBDC2_PBDC215 (0x8000u) - -#define GPIO_PIPC2_PIPC20 (0x0001u) -#define GPIO_PIPC2_PIPC21 (0x0002u) -#define GPIO_PIPC2_PIPC22 (0x0004u) -#define GPIO_PIPC2_PIPC23 (0x0008u) -#define GPIO_PIPC2_PIPC24 (0x0010u) -#define GPIO_PIPC2_PIPC25 (0x0020u) -#define GPIO_PIPC2_PIPC26 (0x0040u) -#define GPIO_PIPC2_PIPC27 (0x0080u) -#define GPIO_PIPC2_PIPC28 (0x0100u) -#define GPIO_PIPC2_PIPC29 (0x0200u) -#define GPIO_PIPC2_PIPC210 (0x0400u) -#define GPIO_PIPC2_PIPC211 (0x0800u) -#define GPIO_PIPC2_PIPC212 (0x1000u) -#define GPIO_PIPC2_PIPC213 (0x2000u) -#define GPIO_PIPC2_PIPC214 (0x4000u) -#define GPIO_PIPC2_PIPC215 (0x8000u) - -/* ---- P3 ---- */ -#define GPIO_P3_P30 (0x0001u) -#define GPIO_P3_P31 (0x0002u) -#define GPIO_P3_P32 (0x0004u) -#define GPIO_P3_P33 (0x0008u) -#define GPIO_P3_P34 (0x0010u) -#define GPIO_P3_P35 (0x0020u) -#define GPIO_P3_P36 (0x0040u) -#define GPIO_P3_P37 (0x0080u) -#define GPIO_P3_P38 (0x0100u) -#define GPIO_P3_P39 (0x0200u) -#define GPIO_P3_P310 (0x0400u) -#define GPIO_P3_P311 (0x0800u) -#define GPIO_P3_P312 (0x1000u) -#define GPIO_P3_P313 (0x2000u) -#define GPIO_P3_P314 (0x4000u) -#define GPIO_P3_P315 (0x8000u) - -#define GPIO_PSR3_PSR30 (0x00000001uL) -#define GPIO_PSR3_PSR31 (0x00000002uL) -#define GPIO_PSR3_PSR32 (0x00000004uL) -#define GPIO_PSR3_PSR33 (0x00000008uL) -#define GPIO_PSR3_PSR34 (0x00000010uL) -#define GPIO_PSR3_PSR35 (0x00000020uL) -#define GPIO_PSR3_PSR36 (0x00000040uL) -#define GPIO_PSR3_PSR37 (0x00000080uL) -#define GPIO_PSR3_PSR38 (0x00000100uL) -#define GPIO_PSR3_PSR39 (0x00000200uL) -#define GPIO_PSR3_PSR310 (0x00000400uL) -#define GPIO_PSR3_PSR311 (0x00000800uL) -#define GPIO_PSR3_PSR312 (0x00001000uL) -#define GPIO_PSR3_PSR313 (0x00002000uL) -#define GPIO_PSR3_PSR314 (0x00004000uL) -#define GPIO_PSR3_PSR315 (0x00008000uL) -#define GPIO_PSR3_PSR316 (0x00010000uL) -#define GPIO_PSR3_PSR317 (0x00020000uL) -#define GPIO_PSR3_PSR318 (0x00040000uL) -#define GPIO_PSR3_PSR319 (0x00080000uL) -#define GPIO_PSR3_PSR320 (0x00100000uL) -#define GPIO_PSR3_PSR321 (0x00200000uL) -#define GPIO_PSR3_PSR322 (0x00400000uL) -#define GPIO_PSR3_PSR323 (0x00800000uL) -#define GPIO_PSR3_PSR324 (0x01000000uL) -#define GPIO_PSR3_PSR325 (0x02000000uL) -#define GPIO_PSR3_PSR326 (0x04000000uL) -#define GPIO_PSR3_PSR327 (0x08000000uL) -#define GPIO_PSR3_PSR328 (0x10000000uL) -#define GPIO_PSR3_PSR329 (0x20000000uL) -#define GPIO_PSR3_PSR330 (0x40000000uL) -#define GPIO_PSR3_PSR331 (0x80000000uL) - -#define GPIO_PPR3_PPR30 (0x0001u) -#define GPIO_PPR3_PPR31 (0x0002u) -#define GPIO_PPR3_PPR32 (0x0004u) -#define GPIO_PPR3_PPR33 (0x0008u) -#define GPIO_PPR3_PPR34 (0x0010u) -#define GPIO_PPR3_PPR35 (0x0020u) -#define GPIO_PPR3_PPR36 (0x0040u) -#define GPIO_PPR3_PPR37 (0x0080u) -#define GPIO_PPR3_PPR38 (0x0100u) -#define GPIO_PPR3_PPR39 (0x0200u) -#define GPIO_PPR3_PPR310 (0x0400u) -#define GPIO_PPR3_PPR311 (0x0800u) -#define GPIO_PPR3_PPR312 (0x1000u) -#define GPIO_PPR3_PPR313 (0x2000u) -#define GPIO_PPR3_PPR314 (0x4000u) -#define GPIO_PPR3_PPR315 (0x8000u) - -#define GPIO_PM3_PM30 (0x0001u) -#define GPIO_PM3_PM31 (0x0002u) -#define GPIO_PM3_PM32 (0x0004u) -#define GPIO_PM3_PM33 (0x0008u) -#define GPIO_PM3_PM34 (0x0010u) -#define GPIO_PM3_PM35 (0x0020u) -#define GPIO_PM3_PM36 (0x0040u) -#define GPIO_PM3_PM37 (0x0080u) -#define GPIO_PM3_PM38 (0x0100u) -#define GPIO_PM3_PM39 (0x0200u) -#define GPIO_PM3_PM310 (0x0400u) -#define GPIO_PM3_PM311 (0x0800u) -#define GPIO_PM3_PM312 (0x1000u) -#define GPIO_PM3_PM313 (0x2000u) -#define GPIO_PM3_PM314 (0x4000u) -#define GPIO_PM3_PM315 (0x8000u) - -#define GPIO_PMC3_PMC30 (0x0001u) -#define GPIO_PMC3_PMC31 (0x0002u) -#define GPIO_PMC3_PMC32 (0x0004u) -#define GPIO_PMC3_PMC33 (0x0008u) -#define GPIO_PMC3_PMC34 (0x0010u) -#define GPIO_PMC3_PMC35 (0x0020u) -#define GPIO_PMC3_PMC36 (0x0040u) -#define GPIO_PMC3_PMC37 (0x0080u) -#define GPIO_PMC3_PMC38 (0x0100u) -#define GPIO_PMC3_PMC39 (0x0200u) -#define GPIO_PMC3_PMC310 (0x0400u) -#define GPIO_PMC3_PMC311 (0x0800u) -#define GPIO_PMC3_PMC312 (0x1000u) -#define GPIO_PMC3_PMC313 (0x2000u) -#define GPIO_PMC3_PMC314 (0x4000u) -#define GPIO_PMC3_PMC315 (0x8000u) - -#define GPIO_PFC3_PFC30 (0x0001u) -#define GPIO_PFC3_PFC31 (0x0002u) -#define GPIO_PFC3_PFC32 (0x0004u) -#define GPIO_PFC3_PFC33 (0x0008u) -#define GPIO_PFC3_PFC34 (0x0010u) -#define GPIO_PFC3_PFC35 (0x0020u) -#define GPIO_PFC3_PFC36 (0x0040u) -#define GPIO_PFC3_PFC37 (0x0080u) -#define GPIO_PFC3_PFC38 (0x0100u) -#define GPIO_PFC3_PFC39 (0x0200u) -#define GPIO_PFC3_PFC310 (0x0400u) -#define GPIO_PFC3_PFC311 (0x0800u) -#define GPIO_PFC3_PFC312 (0x1000u) -#define GPIO_PFC3_PFC313 (0x2000u) -#define GPIO_PFC3_PFC314 (0x4000u) -#define GPIO_PFC3_PFC315 (0x8000u) - -#define GPIO_PFCE3_PFCE30 (0x0001u) -#define GPIO_PFCE3_PFCE31 (0x0002u) -#define GPIO_PFCE3_PFCE32 (0x0004u) -#define GPIO_PFCE3_PFCE33 (0x0008u) -#define GPIO_PFCE3_PFCE34 (0x0010u) -#define GPIO_PFCE3_PFCE35 (0x0020u) -#define GPIO_PFCE3_PFCE36 (0x0040u) -#define GPIO_PFCE3_PFCE37 (0x0080u) -#define GPIO_PFCE3_PFCE38 (0x0100u) -#define GPIO_PFCE3_PFCE39 (0x0200u) -#define GPIO_PFCE3_PFCE310 (0x0400u) -#define GPIO_PFCE3_PFCE311 (0x0800u) -#define GPIO_PFCE3_PFCE312 (0x1000u) -#define GPIO_PFCE3_PFCE313 (0x2000u) -#define GPIO_PFCE3_PFCE314 (0x4000u) -#define GPIO_PFCE3_PFCE315 (0x8000u) - -#define GPIO_PNOT3_PNOT30 (0x0001u) -#define GPIO_PNOT3_PNOT31 (0x0002u) -#define GPIO_PNOT3_PNOT32 (0x0004u) -#define GPIO_PNOT3_PNOT33 (0x0008u) -#define GPIO_PNOT3_PNOT34 (0x0010u) -#define GPIO_PNOT3_PNOT35 (0x0020u) -#define GPIO_PNOT3_PNOT36 (0x0040u) -#define GPIO_PNOT3_PNOT37 (0x0080u) -#define GPIO_PNOT3_PNOT38 (0x0100u) -#define GPIO_PNOT3_PNOT39 (0x0200u) -#define GPIO_PNOT3_PNOT310 (0x0400u) -#define GPIO_PNOT3_PNOT311 (0x0800u) -#define GPIO_PNOT3_PNOT312 (0x1000u) -#define GPIO_PNOT3_PNOT313 (0x2000u) -#define GPIO_PNOT3_PNOT314 (0x4000u) -#define GPIO_PNOT3_PNOT315 (0x8000u) - -#define GPIO_PMSR3_PMSR30 (0x00000001uL) -#define GPIO_PMSR3_PMSR31 (0x00000002uL) -#define GPIO_PMSR3_PMSR32 (0x00000004uL) -#define GPIO_PMSR3_PMSR33 (0x00000008uL) -#define GPIO_PMSR3_PMSR34 (0x00000010uL) -#define GPIO_PMSR3_PMSR35 (0x00000020uL) -#define GPIO_PMSR3_PMSR36 (0x00000040uL) -#define GPIO_PMSR3_PMSR37 (0x00000080uL) -#define GPIO_PMSR3_PMSR38 (0x00000100uL) -#define GPIO_PMSR3_PMSR39 (0x00000200uL) -#define GPIO_PMSR3_PMSR310 (0x00000400uL) -#define GPIO_PMSR3_PMSR311 (0x00000800uL) -#define GPIO_PMSR3_PMSR312 (0x00001000uL) -#define GPIO_PMSR3_PMSR313 (0x00002000uL) -#define GPIO_PMSR3_PMSR314 (0x00004000uL) -#define GPIO_PMSR3_PMSR315 (0x00008000uL) -#define GPIO_PMSR3_PMSR316 (0x00010000uL) -#define GPIO_PMSR3_PMSR317 (0x00020000uL) -#define GPIO_PMSR3_PMSR318 (0x00040000uL) -#define GPIO_PMSR3_PMSR319 (0x00080000uL) -#define GPIO_PMSR3_PMSR320 (0x00100000uL) -#define GPIO_PMSR3_PMSR321 (0x00200000uL) -#define GPIO_PMSR3_PMSR322 (0x00400000uL) -#define GPIO_PMSR3_PMSR323 (0x00800000uL) -#define GPIO_PMSR3_PMSR324 (0x01000000uL) -#define GPIO_PMSR3_PMSR325 (0x02000000uL) -#define GPIO_PMSR3_PMSR326 (0x04000000uL) -#define GPIO_PMSR3_PMSR327 (0x08000000uL) -#define GPIO_PMSR3_PMSR328 (0x10000000uL) -#define GPIO_PMSR3_PMSR329 (0x20000000uL) -#define GPIO_PMSR3_PMSR330 (0x40000000uL) -#define GPIO_PMSR3_PMSR331 (0x80000000uL) - -#define GPIO_PMCSR3_PMCSR30 (0x00000001uL) -#define GPIO_PMCSR3_PMCSR31 (0x00000002uL) -#define GPIO_PMCSR3_PMCSR32 (0x00000004uL) -#define GPIO_PMCSR3_PMCSR33 (0x00000008uL) -#define GPIO_PMCSR3_PMCSR34 (0x00000010uL) -#define GPIO_PMCSR3_PMCSR35 (0x00000020uL) -#define GPIO_PMCSR3_PMCSR36 (0x00000040uL) -#define GPIO_PMCSR3_PMCSR37 (0x00000080uL) -#define GPIO_PMCSR3_PMCSR38 (0x00000100uL) -#define GPIO_PMCSR3_PMCSR39 (0x00000200uL) -#define GPIO_PMCSR3_PMCSR310 (0x00000400uL) -#define GPIO_PMCSR3_PMCSR311 (0x00000800uL) -#define GPIO_PMCSR3_PMCSR312 (0x00001000uL) -#define GPIO_PMCSR3_PMCSR313 (0x00002000uL) -#define GPIO_PMCSR3_PMCSR314 (0x00004000uL) -#define GPIO_PMCSR3_PMCSR315 (0x00008000uL) -#define GPIO_PMCSR3_PMCSR316 (0x00010000uL) -#define GPIO_PMCSR3_PMCSR317 (0x00020000uL) -#define GPIO_PMCSR3_PMCSR318 (0x00040000uL) -#define GPIO_PMCSR3_PMCSR319 (0x00080000uL) -#define GPIO_PMCSR3_PMCSR320 (0x00100000uL) -#define GPIO_PMCSR3_PMCSR321 (0x00200000uL) -#define GPIO_PMCSR3_PMCSR322 (0x00400000uL) -#define GPIO_PMCSR3_PMCSR323 (0x00800000uL) -#define GPIO_PMCSR3_PMCSR324 (0x01000000uL) -#define GPIO_PMCSR3_PMCSR325 (0x02000000uL) -#define GPIO_PMCSR3_PMCSR326 (0x04000000uL) -#define GPIO_PMCSR3_PMCSR327 (0x08000000uL) -#define GPIO_PMCSR3_PMCSR328 (0x10000000uL) -#define GPIO_PMCSR3_PMCSR329 (0x20000000uL) -#define GPIO_PMCSR3_PMCSR330 (0x40000000uL) -#define GPIO_PMCSR3_PMCSR331 (0x80000000uL) - -#define GPIO_PFCAE3_PFCAE30 (0x0001u) -#define GPIO_PFCAE3_PFCAE31 (0x0002u) -#define GPIO_PFCAE3_PFCAE32 (0x0004u) -#define GPIO_PFCAE3_PFCAE33 (0x0008u) -#define GPIO_PFCAE3_PFCAE34 (0x0010u) -#define GPIO_PFCAE3_PFCAE35 (0x0020u) -#define GPIO_PFCAE3_PFCAE36 (0x0040u) -#define GPIO_PFCAE3_PFCAE37 (0x0080u) -#define GPIO_PFCAE3_PFCAE38 (0x0100u) -#define GPIO_PFCAE3_PFCAE39 (0x0200u) -#define GPIO_PFCAE3_PFCAE310 (0x0400u) -#define GPIO_PFCAE3_PFCAE311 (0x0800u) -#define GPIO_PFCAE3_PFCAE312 (0x1000u) -#define GPIO_PFCAE3_PFCAE313 (0x2000u) -#define GPIO_PFCAE3_PFCAE314 (0x4000u) -#define GPIO_PFCAE3_PFCAE315 (0x8000u) - -#define GPIO_PIBC3_PIBC30 (0x0001u) -#define GPIO_PIBC3_PIBC31 (0x0002u) -#define GPIO_PIBC3_PIBC32 (0x0004u) -#define GPIO_PIBC3_PIBC33 (0x0008u) -#define GPIO_PIBC3_PIBC34 (0x0010u) -#define GPIO_PIBC3_PIBC35 (0x0020u) -#define GPIO_PIBC3_PIBC36 (0x0040u) -#define GPIO_PIBC3_PIBC37 (0x0080u) -#define GPIO_PIBC3_PIBC38 (0x0100u) -#define GPIO_PIBC3_PIBC39 (0x0200u) -#define GPIO_PIBC3_PIBC310 (0x0400u) -#define GPIO_PIBC3_PIBC311 (0x0800u) -#define GPIO_PIBC3_PIBC312 (0x1000u) -#define GPIO_PIBC3_PIBC313 (0x2000u) -#define GPIO_PIBC3_PIBC314 (0x4000u) -#define GPIO_PIBC3_PIBC315 (0x8000u) - -#define GPIO_PBDC3_PBDC30 (0x0001u) -#define GPIO_PBDC3_PBDC31 (0x0002u) -#define GPIO_PBDC3_PBDC32 (0x0004u) -#define GPIO_PBDC3_PBDC33 (0x0008u) -#define GPIO_PBDC3_PBDC34 (0x0010u) -#define GPIO_PBDC3_PBDC35 (0x0020u) -#define GPIO_PBDC3_PBDC36 (0x0040u) -#define GPIO_PBDC3_PBDC37 (0x0080u) -#define GPIO_PBDC3_PBDC38 (0x0100u) -#define GPIO_PBDC3_PBDC39 (0x0200u) -#define GPIO_PBDC3_PBDC310 (0x0400u) -#define GPIO_PBDC3_PBDC311 (0x0800u) -#define GPIO_PBDC3_PBDC312 (0x1000u) -#define GPIO_PBDC3_PBDC313 (0x2000u) -#define GPIO_PBDC3_PBDC314 (0x4000u) -#define GPIO_PBDC3_PBDC315 (0x8000u) - -#define GPIO_PIPC3_PIPC30 (0x0001u) -#define GPIO_PIPC3_PIPC31 (0x0002u) -#define GPIO_PIPC3_PIPC32 (0x0004u) -#define GPIO_PIPC3_PIPC33 (0x0008u) -#define GPIO_PIPC3_PIPC34 (0x0010u) -#define GPIO_PIPC3_PIPC35 (0x0020u) -#define GPIO_PIPC3_PIPC36 (0x0040u) -#define GPIO_PIPC3_PIPC37 (0x0080u) -#define GPIO_PIPC3_PIPC38 (0x0100u) -#define GPIO_PIPC3_PIPC39 (0x0200u) -#define GPIO_PIPC3_PIPC310 (0x0400u) -#define GPIO_PIPC3_PIPC311 (0x0800u) -#define GPIO_PIPC3_PIPC312 (0x1000u) -#define GPIO_PIPC3_PIPC313 (0x2000u) -#define GPIO_PIPC3_PIPC314 (0x4000u) -#define GPIO_PIPC3_PIPC315 (0x8000u) - -/* ---- P4 ---- */ -#define GPIO_P4_P40 (0x0001u) -#define GPIO_P4_P41 (0x0002u) -#define GPIO_P4_P42 (0x0004u) -#define GPIO_P4_P43 (0x0008u) -#define GPIO_P4_P44 (0x0010u) -#define GPIO_P4_P45 (0x0020u) -#define GPIO_P4_P46 (0x0040u) -#define GPIO_P4_P47 (0x0080u) -#define GPIO_P4_P48 (0x0100u) -#define GPIO_P4_P49 (0x0200u) -#define GPIO_P4_P410 (0x0400u) -#define GPIO_P4_P411 (0x0800u) -#define GPIO_P4_P412 (0x1000u) -#define GPIO_P4_P413 (0x2000u) -#define GPIO_P4_P414 (0x4000u) -#define GPIO_P4_P415 (0x8000u) - -#define GPIO_PSR4_PSR40 (0x00000001uL) -#define GPIO_PSR4_PSR41 (0x00000002uL) -#define GPIO_PSR4_PSR42 (0x00000004uL) -#define GPIO_PSR4_PSR43 (0x00000008uL) -#define GPIO_PSR4_PSR44 (0x00000010uL) -#define GPIO_PSR4_PSR45 (0x00000020uL) -#define GPIO_PSR4_PSR46 (0x00000040uL) -#define GPIO_PSR4_PSR47 (0x00000080uL) -#define GPIO_PSR4_PSR48 (0x00000100uL) -#define GPIO_PSR4_PSR49 (0x00000200uL) -#define GPIO_PSR4_PSR410 (0x00000400uL) -#define GPIO_PSR4_PSR411 (0x00000800uL) -#define GPIO_PSR4_PSR412 (0x00001000uL) -#define GPIO_PSR4_PSR413 (0x00002000uL) -#define GPIO_PSR4_PSR414 (0x00004000uL) -#define GPIO_PSR4_PSR415 (0x00008000uL) -#define GPIO_PSR4_PSR416 (0x00010000uL) -#define GPIO_PSR4_PSR417 (0x00020000uL) -#define GPIO_PSR4_PSR418 (0x00040000uL) -#define GPIO_PSR4_PSR419 (0x00080000uL) -#define GPIO_PSR4_PSR420 (0x00100000uL) -#define GPIO_PSR4_PSR421 (0x00200000uL) -#define GPIO_PSR4_PSR422 (0x00400000uL) -#define GPIO_PSR4_PSR423 (0x00800000uL) -#define GPIO_PSR4_PSR424 (0x01000000uL) -#define GPIO_PSR4_PSR425 (0x02000000uL) -#define GPIO_PSR4_PSR426 (0x04000000uL) -#define GPIO_PSR4_PSR427 (0x08000000uL) -#define GPIO_PSR4_PSR428 (0x10000000uL) -#define GPIO_PSR4_PSR429 (0x20000000uL) -#define GPIO_PSR4_PSR430 (0x40000000uL) -#define GPIO_PSR4_PSR431 (0x80000000uL) - -#define GPIO_PPR4_PPR40 (0x0001u) -#define GPIO_PPR4_PPR41 (0x0002u) -#define GPIO_PPR4_PPR42 (0x0004u) -#define GPIO_PPR4_PPR43 (0x0008u) -#define GPIO_PPR4_PPR44 (0x0010u) -#define GPIO_PPR4_PPR45 (0x0020u) -#define GPIO_PPR4_PPR46 (0x0040u) -#define GPIO_PPR4_PPR47 (0x0080u) -#define GPIO_PPR4_PPR48 (0x0100u) -#define GPIO_PPR4_PPR49 (0x0200u) -#define GPIO_PPR4_PPR410 (0x0400u) -#define GPIO_PPR4_PPR411 (0x0800u) -#define GPIO_PPR4_PPR412 (0x1000u) -#define GPIO_PPR4_PPR413 (0x2000u) -#define GPIO_PPR4_PPR414 (0x4000u) -#define GPIO_PPR4_PPR415 (0x8000u) - -#define GPIO_PM4_PM40 (0x0001u) -#define GPIO_PM4_PM41 (0x0002u) -#define GPIO_PM4_PM42 (0x0004u) -#define GPIO_PM4_PM43 (0x0008u) -#define GPIO_PM4_PM44 (0x0010u) -#define GPIO_PM4_PM45 (0x0020u) -#define GPIO_PM4_PM46 (0x0040u) -#define GPIO_PM4_PM47 (0x0080u) -#define GPIO_PM4_PM48 (0x0100u) -#define GPIO_PM4_PM49 (0x0200u) -#define GPIO_PM4_PM410 (0x0400u) -#define GPIO_PM4_PM411 (0x0800u) -#define GPIO_PM4_PM412 (0x1000u) -#define GPIO_PM4_PM413 (0x2000u) -#define GPIO_PM4_PM414 (0x4000u) -#define GPIO_PM4_PM415 (0x8000u) - -#define GPIO_PMC4_PMC40 (0x0001u) -#define GPIO_PMC4_PMC41 (0x0002u) -#define GPIO_PMC4_PMC42 (0x0004u) -#define GPIO_PMC4_PMC43 (0x0008u) -#define GPIO_PMC4_PMC44 (0x0010u) -#define GPIO_PMC4_PMC45 (0x0020u) -#define GPIO_PMC4_PMC46 (0x0040u) -#define GPIO_PMC4_PMC47 (0x0080u) -#define GPIO_PMC4_PMC48 (0x0100u) -#define GPIO_PMC4_PMC49 (0x0200u) -#define GPIO_PMC4_PMC410 (0x0400u) -#define GPIO_PMC4_PMC411 (0x0800u) -#define GPIO_PMC4_PMC412 (0x1000u) -#define GPIO_PMC4_PMC413 (0x2000u) -#define GPIO_PMC4_PMC414 (0x4000u) -#define GPIO_PMC4_PMC415 (0x8000u) - -#define GPIO_PFC4_PFC40 (0x0001u) -#define GPIO_PFC4_PFC41 (0x0002u) -#define GPIO_PFC4_PFC42 (0x0004u) -#define GPIO_PFC4_PFC43 (0x0008u) -#define GPIO_PFC4_PFC44 (0x0010u) -#define GPIO_PFC4_PFC45 (0x0020u) -#define GPIO_PFC4_PFC46 (0x0040u) -#define GPIO_PFC4_PFC47 (0x0080u) -#define GPIO_PFC4_PFC48 (0x0100u) -#define GPIO_PFC4_PFC49 (0x0200u) -#define GPIO_PFC4_PFC410 (0x0400u) -#define GPIO_PFC4_PFC411 (0x0800u) -#define GPIO_PFC4_PFC412 (0x1000u) -#define GPIO_PFC4_PFC413 (0x2000u) -#define GPIO_PFC4_PFC414 (0x4000u) -#define GPIO_PFC4_PFC415 (0x8000u) - -#define GPIO_PFCE4_PFCE40 (0x0001u) -#define GPIO_PFCE4_PFCE41 (0x0002u) -#define GPIO_PFCE4_PFCE42 (0x0004u) -#define GPIO_PFCE4_PFCE43 (0x0008u) -#define GPIO_PFCE4_PFCE44 (0x0010u) -#define GPIO_PFCE4_PFCE45 (0x0020u) -#define GPIO_PFCE4_PFCE46 (0x0040u) -#define GPIO_PFCE4_PFCE47 (0x0080u) -#define GPIO_PFCE4_PFCE48 (0x0100u) -#define GPIO_PFCE4_PFCE49 (0x0200u) -#define GPIO_PFCE4_PFCE410 (0x0400u) -#define GPIO_PFCE4_PFCE411 (0x0800u) -#define GPIO_PFCE4_PFCE412 (0x1000u) -#define GPIO_PFCE4_PFCE413 (0x2000u) -#define GPIO_PFCE4_PFCE414 (0x4000u) -#define GPIO_PFCE4_PFCE415 (0x8000u) - -#define GPIO_PNOT4_PNOT40 (0x0001u) -#define GPIO_PNOT4_PNOT41 (0x0002u) -#define GPIO_PNOT4_PNOT42 (0x0004u) -#define GPIO_PNOT4_PNOT43 (0x0008u) -#define GPIO_PNOT4_PNOT44 (0x0010u) -#define GPIO_PNOT4_PNOT45 (0x0020u) -#define GPIO_PNOT4_PNOT46 (0x0040u) -#define GPIO_PNOT4_PNOT47 (0x0080u) -#define GPIO_PNOT4_PNOT48 (0x0100u) -#define GPIO_PNOT4_PNOT49 (0x0200u) -#define GPIO_PNOT4_PNOT410 (0x0400u) -#define GPIO_PNOT4_PNOT411 (0x0800u) -#define GPIO_PNOT4_PNOT412 (0x1000u) -#define GPIO_PNOT4_PNOT413 (0x2000u) -#define GPIO_PNOT4_PNOT414 (0x4000u) -#define GPIO_PNOT4_PNOT415 (0x8000u) - -#define GPIO_PMSR4_PMSR40 (0x00000001uL) -#define GPIO_PMSR4_PMSR41 (0x00000002uL) -#define GPIO_PMSR4_PMSR42 (0x00000004uL) -#define GPIO_PMSR4_PMSR43 (0x00000008uL) -#define GPIO_PMSR4_PMSR44 (0x00000010uL) -#define GPIO_PMSR4_PMSR45 (0x00000020uL) -#define GPIO_PMSR4_PMSR46 (0x00000040uL) -#define GPIO_PMSR4_PMSR47 (0x00000080uL) -#define GPIO_PMSR4_PMSR48 (0x00000100uL) -#define GPIO_PMSR4_PMSR49 (0x00000200uL) -#define GPIO_PMSR4_PMSR410 (0x00000400uL) -#define GPIO_PMSR4_PMSR411 (0x00000800uL) -#define GPIO_PMSR4_PMSR412 (0x00001000uL) -#define GPIO_PMSR4_PMSR413 (0x00002000uL) -#define GPIO_PMSR4_PMSR414 (0x00004000uL) -#define GPIO_PMSR4_PMSR415 (0x00008000uL) -#define GPIO_PMSR4_PMSR416 (0x00010000uL) -#define GPIO_PMSR4_PMSR417 (0x00020000uL) -#define GPIO_PMSR4_PMSR418 (0x00040000uL) -#define GPIO_PMSR4_PMSR419 (0x00080000uL) -#define GPIO_PMSR4_PMSR420 (0x00100000uL) -#define GPIO_PMSR4_PMSR421 (0x00200000uL) -#define GPIO_PMSR4_PMSR422 (0x00400000uL) -#define GPIO_PMSR4_PMSR423 (0x00800000uL) -#define GPIO_PMSR4_PMSR424 (0x01000000uL) -#define GPIO_PMSR4_PMSR425 (0x02000000uL) -#define GPIO_PMSR4_PMSR426 (0x04000000uL) -#define GPIO_PMSR4_PMSR427 (0x08000000uL) -#define GPIO_PMSR4_PMSR428 (0x10000000uL) -#define GPIO_PMSR4_PMSR429 (0x20000000uL) -#define GPIO_PMSR4_PMSR430 (0x40000000uL) -#define GPIO_PMSR4_PMSR431 (0x80000000uL) - -#define GPIO_PMCSR4_PMCSR40 (0x00000001uL) -#define GPIO_PMCSR4_PMCSR41 (0x00000002uL) -#define GPIO_PMCSR4_PMCSR42 (0x00000004uL) -#define GPIO_PMCSR4_PMCSR43 (0x00000008uL) -#define GPIO_PMCSR4_PMCSR44 (0x00000010uL) -#define GPIO_PMCSR4_PMCSR45 (0x00000020uL) -#define GPIO_PMCSR4_PMCSR46 (0x00000040uL) -#define GPIO_PMCSR4_PMCSR47 (0x00000080uL) -#define GPIO_PMCSR4_PMCSR48 (0x00000100uL) -#define GPIO_PMCSR4_PMCSR49 (0x00000200uL) -#define GPIO_PMCSR4_PMCSR410 (0x00000400uL) -#define GPIO_PMCSR4_PMCSR411 (0x00000800uL) -#define GPIO_PMCSR4_PMCSR412 (0x00001000uL) -#define GPIO_PMCSR4_PMCSR413 (0x00002000uL) -#define GPIO_PMCSR4_PMCSR414 (0x00004000uL) -#define GPIO_PMCSR4_PMCSR415 (0x00008000uL) -#define GPIO_PMCSR4_PMCSR416 (0x00010000uL) -#define GPIO_PMCSR4_PMCSR417 (0x00020000uL) -#define GPIO_PMCSR4_PMCSR418 (0x00040000uL) -#define GPIO_PMCSR4_PMCSR419 (0x00080000uL) -#define GPIO_PMCSR4_PMCSR420 (0x00100000uL) -#define GPIO_PMCSR4_PMCSR421 (0x00200000uL) -#define GPIO_PMCSR4_PMCSR422 (0x00400000uL) -#define GPIO_PMCSR4_PMCSR423 (0x00800000uL) -#define GPIO_PMCSR4_PMCSR424 (0x01000000uL) -#define GPIO_PMCSR4_PMCSR425 (0x02000000uL) -#define GPIO_PMCSR4_PMCSR426 (0x04000000uL) -#define GPIO_PMCSR4_PMCSR427 (0x08000000uL) -#define GPIO_PMCSR4_PMCSR428 (0x10000000uL) -#define GPIO_PMCSR4_PMCSR429 (0x20000000uL) -#define GPIO_PMCSR4_PMCSR430 (0x40000000uL) -#define GPIO_PMCSR4_PMCSR431 (0x80000000uL) - -#define GPIO_PFCAE4_PFCAE40 (0x0001u) -#define GPIO_PFCAE4_PFCAE41 (0x0002u) -#define GPIO_PFCAE4_PFCAE42 (0x0004u) -#define GPIO_PFCAE4_PFCAE43 (0x0008u) -#define GPIO_PFCAE4_PFCAE44 (0x0010u) -#define GPIO_PFCAE4_PFCAE45 (0x0020u) -#define GPIO_PFCAE4_PFCAE46 (0x0040u) -#define GPIO_PFCAE4_PFCAE47 (0x0080u) -#define GPIO_PFCAE4_PFCAE48 (0x0100u) -#define GPIO_PFCAE4_PFCAE49 (0x0200u) -#define GPIO_PFCAE4_PFCAE410 (0x0400u) -#define GPIO_PFCAE4_PFCAE411 (0x0800u) -#define GPIO_PFCAE4_PFCAE412 (0x1000u) -#define GPIO_PFCAE4_PFCAE413 (0x2000u) -#define GPIO_PFCAE4_PFCAE414 (0x4000u) -#define GPIO_PFCAE4_PFCAE415 (0x8000u) - -#define GPIO_PIBC4_PIBC40 (0x0001u) -#define GPIO_PIBC4_PIBC41 (0x0002u) -#define GPIO_PIBC4_PIBC42 (0x0004u) -#define GPIO_PIBC4_PIBC43 (0x0008u) -#define GPIO_PIBC4_PIBC44 (0x0010u) -#define GPIO_PIBC4_PIBC45 (0x0020u) -#define GPIO_PIBC4_PIBC46 (0x0040u) -#define GPIO_PIBC4_PIBC47 (0x0080u) -#define GPIO_PIBC4_PIBC48 (0x0100u) -#define GPIO_PIBC4_PIBC49 (0x0200u) -#define GPIO_PIBC4_PIBC410 (0x0400u) -#define GPIO_PIBC4_PIBC411 (0x0800u) -#define GPIO_PIBC4_PIBC412 (0x1000u) -#define GPIO_PIBC4_PIBC413 (0x2000u) -#define GPIO_PIBC4_PIBC414 (0x4000u) -#define GPIO_PIBC4_PIBC415 (0x8000u) - -#define GPIO_PBDC4_PBDC40 (0x0001u) -#define GPIO_PBDC4_PBDC41 (0x0002u) -#define GPIO_PBDC4_PBDC42 (0x0004u) -#define GPIO_PBDC4_PBDC43 (0x0008u) -#define GPIO_PBDC4_PBDC44 (0x0010u) -#define GPIO_PBDC4_PBDC45 (0x0020u) -#define GPIO_PBDC4_PBDC46 (0x0040u) -#define GPIO_PBDC4_PBDC47 (0x0080u) -#define GPIO_PBDC4_PBDC48 (0x0100u) -#define GPIO_PBDC4_PBDC49 (0x0200u) -#define GPIO_PBDC4_PBDC410 (0x0400u) -#define GPIO_PBDC4_PBDC411 (0x0800u) -#define GPIO_PBDC4_PBDC412 (0x1000u) -#define GPIO_PBDC4_PBDC413 (0x2000u) -#define GPIO_PBDC4_PBDC414 (0x4000u) -#define GPIO_PBDC4_PBDC415 (0x8000u) - -#define GPIO_PIPC4_PIPC40 (0x0001u) -#define GPIO_PIPC4_PIPC41 (0x0002u) -#define GPIO_PIPC4_PIPC42 (0x0004u) -#define GPIO_PIPC4_PIPC43 (0x0008u) -#define GPIO_PIPC4_PIPC44 (0x0010u) -#define GPIO_PIPC4_PIPC45 (0x0020u) -#define GPIO_PIPC4_PIPC46 (0x0040u) -#define GPIO_PIPC4_PIPC47 (0x0080u) -#define GPIO_PIPC4_PIPC48 (0x0100u) -#define GPIO_PIPC4_PIPC49 (0x0200u) -#define GPIO_PIPC4_PIPC410 (0x0400u) -#define GPIO_PIPC4_PIPC411 (0x0800u) -#define GPIO_PIPC4_PIPC412 (0x1000u) -#define GPIO_PIPC4_PIPC413 (0x2000u) -#define GPIO_PIPC4_PIPC414 (0x4000u) -#define GPIO_PIPC4_PIPC415 (0x8000u) - -/* ---- P5 ---- */ -#define GPIO_P5_P50 (0x0001u) -#define GPIO_P5_P51 (0x0002u) -#define GPIO_P5_P52 (0x0004u) -#define GPIO_P5_P53 (0x0008u) -#define GPIO_P5_P54 (0x0010u) -#define GPIO_P5_P55 (0x0020u) -#define GPIO_P5_P56 (0x0040u) -#define GPIO_P5_P57 (0x0080u) -#define GPIO_P5_P58 (0x0100u) -#define GPIO_P5_P59 (0x0200u) -#define GPIO_P5_P510 (0x0400u) - -#define GPIO_PSR5_PSR50 (0x00000001uL) -#define GPIO_PSR5_PSR51 (0x00000002uL) -#define GPIO_PSR5_PSR52 (0x00000004uL) -#define GPIO_PSR5_PSR53 (0x00000008uL) -#define GPIO_PSR5_PSR54 (0x00000010uL) -#define GPIO_PSR5_PSR55 (0x00000020uL) -#define GPIO_PSR5_PSR56 (0x00000040uL) -#define GPIO_PSR5_PSR57 (0x00000080uL) -#define GPIO_PSR5_PSR58 (0x00000100uL) -#define GPIO_PSR5_PSR59 (0x00000200uL) -#define GPIO_PSR5_PSR510 (0x00000400uL) -#define GPIO_PSR5_PSR516 (0x00010000uL) -#define GPIO_PSR5_PSR517 (0x00020000uL) -#define GPIO_PSR5_PSR518 (0x00040000uL) -#define GPIO_PSR5_PSR519 (0x00080000uL) -#define GPIO_PSR5_PSR520 (0x00100000uL) -#define GPIO_PSR5_PSR521 (0x00200000uL) -#define GPIO_PSR5_PSR522 (0x00400000uL) -#define GPIO_PSR5_PSR523 (0x00800000uL) -#define GPIO_PSR5_PSR524 (0x01000000uL) -#define GPIO_PSR5_PSR525 (0x02000000uL) -#define GPIO_PSR5_PSR526 (0x04000000uL) - -#define GPIO_PPR5_PPR50 (0x0001u) -#define GPIO_PPR5_PPR51 (0x0002u) -#define GPIO_PPR5_PPR52 (0x0004u) -#define GPIO_PPR5_PPR53 (0x0008u) -#define GPIO_PPR5_PPR54 (0x0010u) -#define GPIO_PPR5_PPR55 (0x0020u) -#define GPIO_PPR5_PPR56 (0x0040u) -#define GPIO_PPR5_PPR57 (0x0080u) -#define GPIO_PPR5_PPR58 (0x0100u) -#define GPIO_PPR5_PPR59 (0x0200u) -#define GPIO_PPR5_PPR510 (0x0400u) - -#define GPIO_PM5_PM50 (0x0001u) -#define GPIO_PM5_PM51 (0x0002u) -#define GPIO_PM5_PM52 (0x0004u) -#define GPIO_PM5_PM53 (0x0008u) -#define GPIO_PM5_PM54 (0x0010u) -#define GPIO_PM5_PM55 (0x0020u) -#define GPIO_PM5_PM56 (0x0040u) -#define GPIO_PM5_PM57 (0x0080u) -#define GPIO_PM5_PM58 (0x0100u) -#define GPIO_PM5_PM59 (0x0200u) -#define GPIO_PM5_PM510 (0x0400u) - -#define GPIO_PMC5_PMC50 (0x0001u) -#define GPIO_PMC5_PMC51 (0x0002u) -#define GPIO_PMC5_PMC52 (0x0004u) -#define GPIO_PMC5_PMC53 (0x0008u) -#define GPIO_PMC5_PMC54 (0x0010u) -#define GPIO_PMC5_PMC55 (0x0020u) -#define GPIO_PMC5_PMC56 (0x0040u) -#define GPIO_PMC5_PMC57 (0x0080u) -#define GPIO_PMC5_PMC58 (0x0100u) -#define GPIO_PMC5_PMC59 (0x0200u) -#define GPIO_PMC5_PMC510 (0x0400u) - -#define GPIO_PFC5_PFC50 (0x0001u) -#define GPIO_PFC5_PFC51 (0x0002u) -#define GPIO_PFC5_PFC52 (0x0004u) -#define GPIO_PFC5_PFC53 (0x0008u) -#define GPIO_PFC5_PFC54 (0x0010u) -#define GPIO_PFC5_PFC55 (0x0020u) -#define GPIO_PFC5_PFC56 (0x0040u) -#define GPIO_PFC5_PFC57 (0x0080u) -#define GPIO_PFC5_PFC58 (0x0100u) -#define GPIO_PFC5_PFC59 (0x0200u) -#define GPIO_PFC5_PFC510 (0x0400u) - -#define GPIO_PFCE5_PFCE50 (0x0001u) -#define GPIO_PFCE5_PFCE51 (0x0002u) -#define GPIO_PFCE5_PFCE52 (0x0004u) -#define GPIO_PFCE5_PFCE53 (0x0008u) -#define GPIO_PFCE5_PFCE54 (0x0010u) -#define GPIO_PFCE5_PFCE55 (0x0020u) -#define GPIO_PFCE5_PFCE56 (0x0040u) -#define GPIO_PFCE5_PFCE57 (0x0080u) -#define GPIO_PFCE5_PFCE58 (0x0100u) -#define GPIO_PFCE5_PFCE59 (0x0200u) -#define GPIO_PFCE5_PFCE510 (0x0400u) - -#define GPIO_PNOT5_PNOT50 (0x0001u) -#define GPIO_PNOT5_PNOT51 (0x0002u) -#define GPIO_PNOT5_PNOT52 (0x0004u) -#define GPIO_PNOT5_PNOT53 (0x0008u) -#define GPIO_PNOT5_PNOT54 (0x0010u) -#define GPIO_PNOT5_PNOT55 (0x0020u) -#define GPIO_PNOT5_PNOT56 (0x0040u) -#define GPIO_PNOT5_PNOT57 (0x0080u) -#define GPIO_PNOT5_PNOT58 (0x0100u) -#define GPIO_PNOT5_PNOT59 (0x0200u) -#define GPIO_PNOT5_PNOT510 (0x0400u) - -#define GPIO_PMSR5_PMSR50 (0x00000001uL) -#define GPIO_PMSR5_PMSR51 (0x00000002uL) -#define GPIO_PMSR5_PMSR52 (0x00000004uL) -#define GPIO_PMSR5_PMSR53 (0x00000008uL) -#define GPIO_PMSR5_PMSR54 (0x00000010uL) -#define GPIO_PMSR5_PMSR55 (0x00000020uL) -#define GPIO_PMSR5_PMSR56 (0x00000040uL) -#define GPIO_PMSR5_PMSR57 (0x00000080uL) -#define GPIO_PMSR5_PMSR58 (0x00000100uL) -#define GPIO_PMSR5_PMSR59 (0x00000200uL) -#define GPIO_PMSR5_PMSR510 (0x00000400uL) -#define GPIO_PMSR5_PMSR516 (0x00010000uL) -#define GPIO_PMSR5_PMSR517 (0x00020000uL) -#define GPIO_PMSR5_PMSR518 (0x00040000uL) -#define GPIO_PMSR5_PMSR519 (0x00080000uL) -#define GPIO_PMSR5_PMSR520 (0x00100000uL) -#define GPIO_PMSR5_PMSR521 (0x00200000uL) -#define GPIO_PMSR5_PMSR522 (0x00400000uL) -#define GPIO_PMSR5_PMSR523 (0x00800000uL) -#define GPIO_PMSR5_PMSR524 (0x01000000uL) -#define GPIO_PMSR5_PMSR525 (0x02000000uL) -#define GPIO_PMSR5_PMSR526 (0x04000000uL) - -#define GPIO_PMCSR5_PMCSR50 (0x00000001uL) -#define GPIO_PMCSR5_PMCSR51 (0x00000002uL) -#define GPIO_PMCSR5_PMCSR52 (0x00000004uL) -#define GPIO_PMCSR5_PMCSR53 (0x00000008uL) -#define GPIO_PMCSR5_PMCSR54 (0x00000010uL) -#define GPIO_PMCSR5_PMCSR55 (0x00000020uL) -#define GPIO_PMCSR5_PMCSR56 (0x00000040uL) -#define GPIO_PMCSR5_PMCSR57 (0x00000080uL) -#define GPIO_PMCSR5_PMCSR58 (0x00000100uL) -#define GPIO_PMCSR5_PMCSR59 (0x00000200uL) -#define GPIO_PMCSR5_PMCSR510 (0x00000400uL) -#define GPIO_PMCSR5_PMCSR516 (0x00010000uL) -#define GPIO_PMCSR5_PMCSR517 (0x00020000uL) -#define GPIO_PMCSR5_PMCSR518 (0x00040000uL) -#define GPIO_PMCSR5_PMCSR519 (0x00080000uL) -#define GPIO_PMCSR5_PMCSR520 (0x00100000uL) -#define GPIO_PMCSR5_PMCSR521 (0x00200000uL) -#define GPIO_PMCSR5_PMCSR522 (0x00400000uL) -#define GPIO_PMCSR5_PMCSR523 (0x00800000uL) -#define GPIO_PMCSR5_PMCSR524 (0x01000000uL) -#define GPIO_PMCSR5_PMCSR525 (0x02000000uL) -#define GPIO_PMCSR5_PMCSR526 (0x04000000uL) - -#define GPIO_PFCAE5_PFCAE50 (0x0001u) -#define GPIO_PFCAE5_PFCAE51 (0x0002u) -#define GPIO_PFCAE5_PFCAE52 (0x0004u) -#define GPIO_PFCAE5_PFCAE53 (0x0008u) -#define GPIO_PFCAE5_PFCAE54 (0x0010u) -#define GPIO_PFCAE5_PFCAE55 (0x0020u) -#define GPIO_PFCAE5_PFCAE56 (0x0040u) -#define GPIO_PFCAE5_PFCAE57 (0x0080u) -#define GPIO_PFCAE5_PFCAE58 (0x0100u) -#define GPIO_PFCAE5_PFCAE59 (0x0200u) -#define GPIO_PFCAE5_PFCAE510 (0x0400u) - -#define GPIO_PIBC5_PIBC50 (0x0001u) -#define GPIO_PIBC5_PIBC51 (0x0002u) -#define GPIO_PIBC5_PIBC52 (0x0004u) -#define GPIO_PIBC5_PIBC53 (0x0008u) -#define GPIO_PIBC5_PIBC54 (0x0010u) -#define GPIO_PIBC5_PIBC55 (0x0020u) -#define GPIO_PIBC5_PIBC56 (0x0040u) -#define GPIO_PIBC5_PIBC57 (0x0080u) -#define GPIO_PIBC5_PIBC58 (0x0100u) -#define GPIO_PIBC5_PIBC59 (0x0200u) -#define GPIO_PIBC5_PIBC510 (0x0400u) - -#define GPIO_PBDC5_PBDC50 (0x0001u) -#define GPIO_PBDC5_PBDC51 (0x0002u) -#define GPIO_PBDC5_PBDC52 (0x0004u) -#define GPIO_PBDC5_PBDC53 (0x0008u) -#define GPIO_PBDC5_PBDC54 (0x0010u) -#define GPIO_PBDC5_PBDC55 (0x0020u) -#define GPIO_PBDC5_PBDC56 (0x0040u) -#define GPIO_PBDC5_PBDC57 (0x0080u) -#define GPIO_PBDC5_PBDC58 (0x0100u) -#define GPIO_PBDC5_PBDC59 (0x0200u) -#define GPIO_PBDC5_PBDC510 (0x0400u) - -#define GPIO_PIPC5_PIPC50 (0x0001u) -#define GPIO_PIPC5_PIPC51 (0x0002u) -#define GPIO_PIPC5_PIPC52 (0x0004u) -#define GPIO_PIPC5_PIPC53 (0x0008u) -#define GPIO_PIPC5_PIPC54 (0x0010u) -#define GPIO_PIPC5_PIPC55 (0x0020u) -#define GPIO_PIPC5_PIPC56 (0x0040u) -#define GPIO_PIPC5_PIPC57 (0x0080u) -#define GPIO_PIPC5_PIPC58 (0x0100u) -#define GPIO_PIPC5_PIPC59 (0x0200u) -#define GPIO_PIPC5_PIPC510 (0x0400u) - -/* ---- P6 ---- */ -#define GPIO_P6_P60 (0x0001u) -#define GPIO_P6_P61 (0x0002u) -#define GPIO_P6_P62 (0x0004u) -#define GPIO_P6_P63 (0x0008u) -#define GPIO_P6_P64 (0x0010u) -#define GPIO_P6_P65 (0x0020u) -#define GPIO_P6_P66 (0x0040u) -#define GPIO_P6_P67 (0x0080u) -#define GPIO_P6_P68 (0x0100u) -#define GPIO_P6_P69 (0x0200u) -#define GPIO_P6_P610 (0x0400u) -#define GPIO_P6_P611 (0x0800u) -#define GPIO_P6_P612 (0x1000u) -#define GPIO_P6_P613 (0x2000u) -#define GPIO_P6_P614 (0x4000u) -#define GPIO_P6_P615 (0x8000u) - -#define GPIO_PSR6_PSR60 (0x00000001uL) -#define GPIO_PSR6_PSR61 (0x00000002uL) -#define GPIO_PSR6_PSR62 (0x00000004uL) -#define GPIO_PSR6_PSR63 (0x00000008uL) -#define GPIO_PSR6_PSR64 (0x00000010uL) -#define GPIO_PSR6_PSR65 (0x00000020uL) -#define GPIO_PSR6_PSR66 (0x00000040uL) -#define GPIO_PSR6_PSR67 (0x00000080uL) -#define GPIO_PSR6_PSR68 (0x00000100uL) -#define GPIO_PSR6_PSR69 (0x00000200uL) -#define GPIO_PSR6_PSR610 (0x00000400uL) -#define GPIO_PSR6_PSR611 (0x00000800uL) -#define GPIO_PSR6_PSR612 (0x00001000uL) -#define GPIO_PSR6_PSR613 (0x00002000uL) -#define GPIO_PSR6_PSR614 (0x00004000uL) -#define GPIO_PSR6_PSR615 (0x00008000uL) -#define GPIO_PSR6_PSR616 (0x00010000uL) -#define GPIO_PSR6_PSR617 (0x00020000uL) -#define GPIO_PSR6_PSR618 (0x00040000uL) -#define GPIO_PSR6_PSR619 (0x00080000uL) -#define GPIO_PSR6_PSR620 (0x00100000uL) -#define GPIO_PSR6_PSR621 (0x00200000uL) -#define GPIO_PSR6_PSR622 (0x00400000uL) -#define GPIO_PSR6_PSR623 (0x00800000uL) -#define GPIO_PSR6_PSR624 (0x01000000uL) -#define GPIO_PSR6_PSR625 (0x02000000uL) -#define GPIO_PSR6_PSR626 (0x04000000uL) -#define GPIO_PSR6_PSR627 (0x08000000uL) -#define GPIO_PSR6_PSR628 (0x10000000uL) -#define GPIO_PSR6_PSR629 (0x20000000uL) -#define GPIO_PSR6_PSR630 (0x40000000uL) -#define GPIO_PSR6_PSR631 (0x80000000uL) - -#define GPIO_PPR6_PPR60 (0x0001u) -#define GPIO_PPR6_PPR61 (0x0002u) -#define GPIO_PPR6_PPR62 (0x0004u) -#define GPIO_PPR6_PPR63 (0x0008u) -#define GPIO_PPR6_PPR64 (0x0010u) -#define GPIO_PPR6_PPR65 (0x0020u) -#define GPIO_PPR6_PPR66 (0x0040u) -#define GPIO_PPR6_PPR67 (0x0080u) -#define GPIO_PPR6_PPR68 (0x0100u) -#define GPIO_PPR6_PPR69 (0x0200u) -#define GPIO_PPR6_PPR610 (0x0400u) -#define GPIO_PPR6_PPR611 (0x0800u) -#define GPIO_PPR6_PPR612 (0x1000u) -#define GPIO_PPR6_PPR613 (0x2000u) -#define GPIO_PPR6_PPR614 (0x4000u) -#define GPIO_PPR6_PPR615 (0x8000u) - -#define GPIO_PM6_PM60 (0x0001u) -#define GPIO_PM6_PM61 (0x0002u) -#define GPIO_PM6_PM62 (0x0004u) -#define GPIO_PM6_PM63 (0x0008u) -#define GPIO_PM6_PM64 (0x0010u) -#define GPIO_PM6_PM65 (0x0020u) -#define GPIO_PM6_PM66 (0x0040u) -#define GPIO_PM6_PM67 (0x0080u) -#define GPIO_PM6_PM68 (0x0100u) -#define GPIO_PM6_PM69 (0x0200u) -#define GPIO_PM6_PM610 (0x0400u) -#define GPIO_PM6_PM611 (0x0800u) -#define GPIO_PM6_PM612 (0x1000u) -#define GPIO_PM6_PM613 (0x2000u) -#define GPIO_PM6_PM614 (0x4000u) -#define GPIO_PM6_PM615 (0x8000u) - -#define GPIO_PMC6_PMC60 (0x0001u) -#define GPIO_PMC6_PMC61 (0x0002u) -#define GPIO_PMC6_PMC62 (0x0004u) -#define GPIO_PMC6_PMC63 (0x0008u) -#define GPIO_PMC6_PMC64 (0x0010u) -#define GPIO_PMC6_PMC65 (0x0020u) -#define GPIO_PMC6_PMC66 (0x0040u) -#define GPIO_PMC6_PMC67 (0x0080u) -#define GPIO_PMC6_PMC68 (0x0100u) -#define GPIO_PMC6_PMC69 (0x0200u) -#define GPIO_PMC6_PMC610 (0x0400u) -#define GPIO_PMC6_PMC611 (0x0800u) -#define GPIO_PMC6_PMC612 (0x1000u) -#define GPIO_PMC6_PMC613 (0x2000u) -#define GPIO_PMC6_PMC614 (0x4000u) -#define GPIO_PMC6_PMC615 (0x8000u) - -#define GPIO_PFC6_PFC60 (0x0001u) -#define GPIO_PFC6_PFC61 (0x0002u) -#define GPIO_PFC6_PFC62 (0x0004u) -#define GPIO_PFC6_PFC63 (0x0008u) -#define GPIO_PFC6_PFC64 (0x0010u) -#define GPIO_PFC6_PFC65 (0x0020u) -#define GPIO_PFC6_PFC66 (0x0040u) -#define GPIO_PFC6_PFC67 (0x0080u) -#define GPIO_PFC6_PFC68 (0x0100u) -#define GPIO_PFC6_PFC69 (0x0200u) -#define GPIO_PFC6_PFC610 (0x0400u) -#define GPIO_PFC6_PFC611 (0x0800u) -#define GPIO_PFC6_PFC612 (0x1000u) -#define GPIO_PFC6_PFC613 (0x2000u) -#define GPIO_PFC6_PFC614 (0x4000u) -#define GPIO_PFC6_PFC615 (0x8000u) - -#define GPIO_PFCE6_PFCE60 (0x0001u) -#define GPIO_PFCE6_PFCE61 (0x0002u) -#define GPIO_PFCE6_PFCE62 (0x0004u) -#define GPIO_PFCE6_PFCE63 (0x0008u) -#define GPIO_PFCE6_PFCE64 (0x0010u) -#define GPIO_PFCE6_PFCE65 (0x0020u) -#define GPIO_PFCE6_PFCE66 (0x0040u) -#define GPIO_PFCE6_PFCE67 (0x0080u) -#define GPIO_PFCE6_PFCE68 (0x0100u) -#define GPIO_PFCE6_PFCE69 (0x0200u) -#define GPIO_PFCE6_PFCE610 (0x0400u) -#define GPIO_PFCE6_PFCE611 (0x0800u) -#define GPIO_PFCE6_PFCE612 (0x1000u) -#define GPIO_PFCE6_PFCE613 (0x2000u) -#define GPIO_PFCE6_PFCE614 (0x4000u) -#define GPIO_PFCE6_PFCE615 (0x8000u) - -#define GPIO_PNOT6_PNOT60 (0x0001u) -#define GPIO_PNOT6_PNOT61 (0x0002u) -#define GPIO_PNOT6_PNOT62 (0x0004u) -#define GPIO_PNOT6_PNOT63 (0x0008u) -#define GPIO_PNOT6_PNOT64 (0x0010u) -#define GPIO_PNOT6_PNOT65 (0x0020u) -#define GPIO_PNOT6_PNOT66 (0x0040u) -#define GPIO_PNOT6_PNOT67 (0x0080u) -#define GPIO_PNOT6_PNOT68 (0x0100u) -#define GPIO_PNOT6_PNOT69 (0x0200u) -#define GPIO_PNOT6_PNOT610 (0x0400u) -#define GPIO_PNOT6_PNOT611 (0x0800u) -#define GPIO_PNOT6_PNOT612 (0x1000u) -#define GPIO_PNOT6_PNOT613 (0x2000u) -#define GPIO_PNOT6_PNOT614 (0x4000u) -#define GPIO_PNOT6_PNOT615 (0x8000u) - -#define GPIO_PMSR6_PMSR60 (0x00000001uL) -#define GPIO_PMSR6_PMSR61 (0x00000002uL) -#define GPIO_PMSR6_PMSR62 (0x00000004uL) -#define GPIO_PMSR6_PMSR63 (0x00000008uL) -#define GPIO_PMSR6_PMSR64 (0x00000010uL) -#define GPIO_PMSR6_PMSR65 (0x00000020uL) -#define GPIO_PMSR6_PMSR66 (0x00000040uL) -#define GPIO_PMSR6_PMSR67 (0x00000080uL) -#define GPIO_PMSR6_PMSR68 (0x00000100uL) -#define GPIO_PMSR6_PMSR69 (0x00000200uL) -#define GPIO_PMSR6_PMSR610 (0x00000400uL) -#define GPIO_PMSR6_PMSR611 (0x00000800uL) -#define GPIO_PMSR6_PMSR612 (0x00001000uL) -#define GPIO_PMSR6_PMSR613 (0x00002000uL) -#define GPIO_PMSR6_PMSR614 (0x00004000uL) -#define GPIO_PMSR6_PMSR615 (0x00008000uL) -#define GPIO_PMSR6_PMSR616 (0x00010000uL) -#define GPIO_PMSR6_PMSR617 (0x00020000uL) -#define GPIO_PMSR6_PMSR618 (0x00040000uL) -#define GPIO_PMSR6_PMSR619 (0x00080000uL) -#define GPIO_PMSR6_PMSR620 (0x00100000uL) -#define GPIO_PMSR6_PMSR621 (0x00200000uL) -#define GPIO_PMSR6_PMSR622 (0x00400000uL) -#define GPIO_PMSR6_PMSR623 (0x00800000uL) -#define GPIO_PMSR6_PMSR624 (0x01000000uL) -#define GPIO_PMSR6_PMSR625 (0x02000000uL) -#define GPIO_PMSR6_PMSR626 (0x04000000uL) -#define GPIO_PMSR6_PMSR627 (0x08000000uL) -#define GPIO_PMSR6_PMSR628 (0x10000000uL) -#define GPIO_PMSR6_PMSR629 (0x20000000uL) -#define GPIO_PMSR6_PMSR630 (0x40000000uL) -#define GPIO_PMSR6_PMSR631 (0x80000000uL) - -#define GPIO_PMCSR6_PMCSR60 (0x00000001uL) -#define GPIO_PMCSR6_PMCSR61 (0x00000002uL) -#define GPIO_PMCSR6_PMCSR62 (0x00000004uL) -#define GPIO_PMCSR6_PMCSR63 (0x00000008uL) -#define GPIO_PMCSR6_PMCSR64 (0x00000010uL) -#define GPIO_PMCSR6_PMCSR65 (0x00000020uL) -#define GPIO_PMCSR6_PMCSR66 (0x00000040uL) -#define GPIO_PMCSR6_PMCSR67 (0x00000080uL) -#define GPIO_PMCSR6_PMCSR68 (0x00000100uL) -#define GPIO_PMCSR6_PMCSR69 (0x00000200uL) -#define GPIO_PMCSR6_PMCSR610 (0x00000400uL) -#define GPIO_PMCSR6_PMCSR611 (0x00000800uL) -#define GPIO_PMCSR6_PMCSR612 (0x00001000uL) -#define GPIO_PMCSR6_PMCSR613 (0x00002000uL) -#define GPIO_PMCSR6_PMCSR614 (0x00004000uL) -#define GPIO_PMCSR6_PMCSR615 (0x00008000uL) -#define GPIO_PMCSR6_PMCSR616 (0x00010000uL) -#define GPIO_PMCSR6_PMCSR617 (0x00020000uL) -#define GPIO_PMCSR6_PMCSR618 (0x00040000uL) -#define GPIO_PMCSR6_PMCSR619 (0x00080000uL) -#define GPIO_PMCSR6_PMCSR620 (0x00100000uL) -#define GPIO_PMCSR6_PMCSR621 (0x00200000uL) -#define GPIO_PMCSR6_PMCSR622 (0x00400000uL) -#define GPIO_PMCSR6_PMCSR623 (0x00800000uL) -#define GPIO_PMCSR6_PMCSR624 (0x01000000uL) -#define GPIO_PMCSR6_PMCSR625 (0x02000000uL) -#define GPIO_PMCSR6_PMCSR626 (0x04000000uL) -#define GPIO_PMCSR6_PMCSR627 (0x08000000uL) -#define GPIO_PMCSR6_PMCSR628 (0x10000000uL) -#define GPIO_PMCSR6_PMCSR629 (0x20000000uL) -#define GPIO_PMCSR6_PMCSR630 (0x40000000uL) -#define GPIO_PMCSR6_PMCSR631 (0x80000000uL) - -#define GPIO_PFCAE6_PFCAE60 (0x0001u) -#define GPIO_PFCAE6_PFCAE61 (0x0002u) -#define GPIO_PFCAE6_PFCAE62 (0x0004u) -#define GPIO_PFCAE6_PFCAE63 (0x0008u) -#define GPIO_PFCAE6_PFCAE64 (0x0010u) -#define GPIO_PFCAE6_PFCAE65 (0x0020u) -#define GPIO_PFCAE6_PFCAE66 (0x0040u) -#define GPIO_PFCAE6_PFCAE67 (0x0080u) -#define GPIO_PFCAE6_PFCAE68 (0x0100u) -#define GPIO_PFCAE6_PFCAE69 (0x0200u) -#define GPIO_PFCAE6_PFCAE610 (0x0400u) -#define GPIO_PFCAE6_PFCAE611 (0x0800u) -#define GPIO_PFCAE6_PFCAE612 (0x1000u) -#define GPIO_PFCAE6_PFCAE613 (0x2000u) -#define GPIO_PFCAE6_PFCAE614 (0x4000u) -#define GPIO_PFCAE6_PFCAE615 (0x8000u) - -#define GPIO_PIBC6_PIBC60 (0x0001u) -#define GPIO_PIBC6_PIBC61 (0x0002u) -#define GPIO_PIBC6_PIBC62 (0x0004u) -#define GPIO_PIBC6_PIBC63 (0x0008u) -#define GPIO_PIBC6_PIBC64 (0x0010u) -#define GPIO_PIBC6_PIBC65 (0x0020u) -#define GPIO_PIBC6_PIBC66 (0x0040u) -#define GPIO_PIBC6_PIBC67 (0x0080u) -#define GPIO_PIBC6_PIBC68 (0x0100u) -#define GPIO_PIBC6_PIBC69 (0x0200u) -#define GPIO_PIBC6_PIBC610 (0x0400u) -#define GPIO_PIBC6_PIBC611 (0x0800u) -#define GPIO_PIBC6_PIBC612 (0x1000u) -#define GPIO_PIBC6_PIBC613 (0x2000u) -#define GPIO_PIBC6_PIBC614 (0x4000u) -#define GPIO_PIBC6_PIBC615 (0x8000u) - -#define GPIO_PBDC6_PBDC60 (0x0001u) -#define GPIO_PBDC6_PBDC61 (0x0002u) -#define GPIO_PBDC6_PBDC62 (0x0004u) -#define GPIO_PBDC6_PBDC63 (0x0008u) -#define GPIO_PBDC6_PBDC64 (0x0010u) -#define GPIO_PBDC6_PBDC65 (0x0020u) -#define GPIO_PBDC6_PBDC66 (0x0040u) -#define GPIO_PBDC6_PBDC67 (0x0080u) -#define GPIO_PBDC6_PBDC68 (0x0100u) -#define GPIO_PBDC6_PBDC69 (0x0200u) -#define GPIO_PBDC6_PBDC610 (0x0400u) -#define GPIO_PBDC6_PBDC611 (0x0800u) -#define GPIO_PBDC6_PBDC612 (0x1000u) -#define GPIO_PBDC6_PBDC613 (0x2000u) -#define GPIO_PBDC6_PBDC614 (0x4000u) -#define GPIO_PBDC6_PBDC615 (0x8000u) - -#define GPIO_PIPC6_PIPC60 (0x0001u) -#define GPIO_PIPC6_PIPC61 (0x0002u) -#define GPIO_PIPC6_PIPC62 (0x0004u) -#define GPIO_PIPC6_PIPC63 (0x0008u) -#define GPIO_PIPC6_PIPC64 (0x0010u) -#define GPIO_PIPC6_PIPC65 (0x0020u) -#define GPIO_PIPC6_PIPC66 (0x0040u) -#define GPIO_PIPC6_PIPC67 (0x0080u) -#define GPIO_PIPC6_PIPC68 (0x0100u) -#define GPIO_PIPC6_PIPC69 (0x0200u) -#define GPIO_PIPC6_PIPC610 (0x0400u) -#define GPIO_PIPC6_PIPC611 (0x0800u) -#define GPIO_PIPC6_PIPC612 (0x1000u) -#define GPIO_PIPC6_PIPC613 (0x2000u) -#define GPIO_PIPC6_PIPC614 (0x4000u) -#define GPIO_PIPC6_PIPC615 (0x8000u) - -/* ---- P7 ---- */ -#define GPIO_P7_P70 (0x0001u) -#define GPIO_P7_P71 (0x0002u) -#define GPIO_P7_P72 (0x0004u) -#define GPIO_P7_P73 (0x0008u) -#define GPIO_P7_P74 (0x0010u) -#define GPIO_P7_P75 (0x0020u) -#define GPIO_P7_P76 (0x0040u) -#define GPIO_P7_P77 (0x0080u) -#define GPIO_P7_P78 (0x0100u) -#define GPIO_P7_P79 (0x0200u) -#define GPIO_P7_P710 (0x0400u) -#define GPIO_P7_P711 (0x0800u) -#define GPIO_P7_P712 (0x1000u) -#define GPIO_P7_P713 (0x2000u) -#define GPIO_P7_P714 (0x4000u) -#define GPIO_P7_P715 (0x8000u) - -#define GPIO_PSR7_PSR70 (0x00000001uL) -#define GPIO_PSR7_PSR71 (0x00000002uL) -#define GPIO_PSR7_PSR72 (0x00000004uL) -#define GPIO_PSR7_PSR73 (0x00000008uL) -#define GPIO_PSR7_PSR74 (0x00000010uL) -#define GPIO_PSR7_PSR75 (0x00000020uL) -#define GPIO_PSR7_PSR76 (0x00000040uL) -#define GPIO_PSR7_PSR77 (0x00000080uL) -#define GPIO_PSR7_PSR78 (0x00000100uL) -#define GPIO_PSR7_PSR79 (0x00000200uL) -#define GPIO_PSR7_PSR710 (0x00000400uL) -#define GPIO_PSR7_PSR711 (0x00000800uL) -#define GPIO_PSR7_PSR712 (0x00001000uL) -#define GPIO_PSR7_PSR713 (0x00002000uL) -#define GPIO_PSR7_PSR714 (0x00004000uL) -#define GPIO_PSR7_PSR715 (0x00008000uL) -#define GPIO_PSR7_PSR716 (0x00010000uL) -#define GPIO_PSR7_PSR717 (0x00020000uL) -#define GPIO_PSR7_PSR718 (0x00040000uL) -#define GPIO_PSR7_PSR719 (0x00080000uL) -#define GPIO_PSR7_PSR720 (0x00100000uL) -#define GPIO_PSR7_PSR721 (0x00200000uL) -#define GPIO_PSR7_PSR722 (0x00400000uL) -#define GPIO_PSR7_PSR723 (0x00800000uL) -#define GPIO_PSR7_PSR724 (0x01000000uL) -#define GPIO_PSR7_PSR725 (0x02000000uL) -#define GPIO_PSR7_PSR726 (0x04000000uL) -#define GPIO_PSR7_PSR727 (0x08000000uL) -#define GPIO_PSR7_PSR728 (0x10000000uL) -#define GPIO_PSR7_PSR729 (0x20000000uL) -#define GPIO_PSR7_PSR730 (0x40000000uL) -#define GPIO_PSR7_PSR731 (0x80000000uL) - -#define GPIO_PPR7_PPR70 (0x0001u) -#define GPIO_PPR7_PPR71 (0x0002u) -#define GPIO_PPR7_PPR72 (0x0004u) -#define GPIO_PPR7_PPR73 (0x0008u) -#define GPIO_PPR7_PPR74 (0x0010u) -#define GPIO_PPR7_PPR75 (0x0020u) -#define GPIO_PPR7_PPR76 (0x0040u) -#define GPIO_PPR7_PPR77 (0x0080u) -#define GPIO_PPR7_PPR78 (0x0100u) -#define GPIO_PPR7_PPR79 (0x0200u) -#define GPIO_PPR7_PPR710 (0x0400u) -#define GPIO_PPR7_PPR711 (0x0800u) -#define GPIO_PPR7_PPR712 (0x1000u) -#define GPIO_PPR7_PPR713 (0x2000u) -#define GPIO_PPR7_PPR714 (0x4000u) -#define GPIO_PPR7_PPR715 (0x8000u) - -#define GPIO_PM7_PM70 (0x0001u) -#define GPIO_PM7_PM71 (0x0002u) -#define GPIO_PM7_PM72 (0x0004u) -#define GPIO_PM7_PM73 (0x0008u) -#define GPIO_PM7_PM74 (0x0010u) -#define GPIO_PM7_PM75 (0x0020u) -#define GPIO_PM7_PM76 (0x0040u) -#define GPIO_PM7_PM77 (0x0080u) -#define GPIO_PM7_PM78 (0x0100u) -#define GPIO_PM7_PM79 (0x0200u) -#define GPIO_PM7_PM710 (0x0400u) -#define GPIO_PM7_PM711 (0x0800u) -#define GPIO_PM7_PM712 (0x1000u) -#define GPIO_PM7_PM713 (0x2000u) -#define GPIO_PM7_PM714 (0x4000u) -#define GPIO_PM7_PM715 (0x8000u) - -#define GPIO_PMC7_PMC70 (0x0001u) -#define GPIO_PMC7_PMC71 (0x0002u) -#define GPIO_PMC7_PMC72 (0x0004u) -#define GPIO_PMC7_PMC73 (0x0008u) -#define GPIO_PMC7_PMC74 (0x0010u) -#define GPIO_PMC7_PMC75 (0x0020u) -#define GPIO_PMC7_PMC76 (0x0040u) -#define GPIO_PMC7_PMC77 (0x0080u) -#define GPIO_PMC7_PMC78 (0x0100u) -#define GPIO_PMC7_PMC79 (0x0200u) -#define GPIO_PMC7_PMC710 (0x0400u) -#define GPIO_PMC7_PMC711 (0x0800u) -#define GPIO_PMC7_PMC712 (0x1000u) -#define GPIO_PMC7_PMC713 (0x2000u) -#define GPIO_PMC7_PMC714 (0x4000u) -#define GPIO_PMC7_PMC715 (0x8000u) - -#define GPIO_PFC7_PFC70 (0x0001u) -#define GPIO_PFC7_PFC71 (0x0002u) -#define GPIO_PFC7_PFC72 (0x0004u) -#define GPIO_PFC7_PFC73 (0x0008u) -#define GPIO_PFC7_PFC74 (0x0010u) -#define GPIO_PFC7_PFC75 (0x0020u) -#define GPIO_PFC7_PFC76 (0x0040u) -#define GPIO_PFC7_PFC77 (0x0080u) -#define GPIO_PFC7_PFC78 (0x0100u) -#define GPIO_PFC7_PFC79 (0x0200u) -#define GPIO_PFC7_PFC710 (0x0400u) -#define GPIO_PFC7_PFC711 (0x0800u) -#define GPIO_PFC7_PFC712 (0x1000u) -#define GPIO_PFC7_PFC713 (0x2000u) -#define GPIO_PFC7_PFC714 (0x4000u) -#define GPIO_PFC7_PFC715 (0x8000u) - -#define GPIO_PFCE7_PFCE70 (0x0001u) -#define GPIO_PFCE7_PFCE71 (0x0002u) -#define GPIO_PFCE7_PFCE72 (0x0004u) -#define GPIO_PFCE7_PFCE73 (0x0008u) -#define GPIO_PFCE7_PFCE74 (0x0010u) -#define GPIO_PFCE7_PFCE75 (0x0020u) -#define GPIO_PFCE7_PFCE76 (0x0040u) -#define GPIO_PFCE7_PFCE77 (0x0080u) -#define GPIO_PFCE7_PFCE78 (0x0100u) -#define GPIO_PFCE7_PFCE79 (0x0200u) -#define GPIO_PFCE7_PFCE710 (0x0400u) -#define GPIO_PFCE7_PFCE711 (0x0800u) -#define GPIO_PFCE7_PFCE712 (0x1000u) -#define GPIO_PFCE7_PFCE713 (0x2000u) -#define GPIO_PFCE7_PFCE714 (0x4000u) -#define GPIO_PFCE7_PFCE715 (0x8000u) - -#define GPIO_PNOT7_PNOT70 (0x0001u) -#define GPIO_PNOT7_PNOT71 (0x0002u) -#define GPIO_PNOT7_PNOT72 (0x0004u) -#define GPIO_PNOT7_PNOT73 (0x0008u) -#define GPIO_PNOT7_PNOT74 (0x0010u) -#define GPIO_PNOT7_PNOT75 (0x0020u) -#define GPIO_PNOT7_PNOT76 (0x0040u) -#define GPIO_PNOT7_PNOT77 (0x0080u) -#define GPIO_PNOT7_PNOT78 (0x0100u) -#define GPIO_PNOT7_PNOT79 (0x0200u) -#define GPIO_PNOT7_PNOT710 (0x0400u) -#define GPIO_PNOT7_PNOT711 (0x0800u) -#define GPIO_PNOT7_PNOT712 (0x1000u) -#define GPIO_PNOT7_PNOT713 (0x2000u) -#define GPIO_PNOT7_PNOT714 (0x4000u) -#define GPIO_PNOT7_PNOT715 (0x8000u) - -#define GPIO_PMSR7_PMSR70 (0x00000001uL) -#define GPIO_PMSR7_PMSR71 (0x00000002uL) -#define GPIO_PMSR7_PMSR72 (0x00000004uL) -#define GPIO_PMSR7_PMSR73 (0x00000008uL) -#define GPIO_PMSR7_PMSR74 (0x00000010uL) -#define GPIO_PMSR7_PMSR75 (0x00000020uL) -#define GPIO_PMSR7_PMSR76 (0x00000040uL) -#define GPIO_PMSR7_PMSR77 (0x00000080uL) -#define GPIO_PMSR7_PMSR78 (0x00000100uL) -#define GPIO_PMSR7_PMSR79 (0x00000200uL) -#define GPIO_PMSR7_PMSR710 (0x00000400uL) -#define GPIO_PMSR7_PMSR711 (0x00000800uL) -#define GPIO_PMSR7_PMSR712 (0x00001000uL) -#define GPIO_PMSR7_PMSR713 (0x00002000uL) -#define GPIO_PMSR7_PMSR714 (0x00004000uL) -#define GPIO_PMSR7_PMSR715 (0x00008000uL) -#define GPIO_PMSR7_PMSR716 (0x00010000uL) -#define GPIO_PMSR7_PMSR717 (0x00020000uL) -#define GPIO_PMSR7_PMSR718 (0x00040000uL) -#define GPIO_PMSR7_PMSR719 (0x00080000uL) -#define GPIO_PMSR7_PMSR720 (0x00100000uL) -#define GPIO_PMSR7_PMSR721 (0x00200000uL) -#define GPIO_PMSR7_PMSR722 (0x00400000uL) -#define GPIO_PMSR7_PMSR723 (0x00800000uL) -#define GPIO_PMSR7_PMSR724 (0x01000000uL) -#define GPIO_PMSR7_PMSR725 (0x02000000uL) -#define GPIO_PMSR7_PMSR726 (0x04000000uL) -#define GPIO_PMSR7_PMSR727 (0x08000000uL) -#define GPIO_PMSR7_PMSR728 (0x10000000uL) -#define GPIO_PMSR7_PMSR729 (0x20000000uL) -#define GPIO_PMSR7_PMSR730 (0x40000000uL) -#define GPIO_PMSR7_PMSR731 (0x80000000uL) - -#define GPIO_PMCSR7_PMCSR70 (0x00000001uL) -#define GPIO_PMCSR7_PMCSR71 (0x00000002uL) -#define GPIO_PMCSR7_PMCSR72 (0x00000004uL) -#define GPIO_PMCSR7_PMCSR73 (0x00000008uL) -#define GPIO_PMCSR7_PMCSR74 (0x00000010uL) -#define GPIO_PMCSR7_PMCSR75 (0x00000020uL) -#define GPIO_PMCSR7_PMCSR76 (0x00000040uL) -#define GPIO_PMCSR7_PMCSR77 (0x00000080uL) -#define GPIO_PMCSR7_PMCSR78 (0x00000100uL) -#define GPIO_PMCSR7_PMCSR79 (0x00000200uL) -#define GPIO_PMCSR7_PMCSR710 (0x00000400uL) -#define GPIO_PMCSR7_PMCSR711 (0x00000800uL) -#define GPIO_PMCSR7_PMCSR712 (0x00001000uL) -#define GPIO_PMCSR7_PMCSR713 (0x00002000uL) -#define GPIO_PMCSR7_PMCSR714 (0x00004000uL) -#define GPIO_PMCSR7_PMCSR715 (0x00008000uL) -#define GPIO_PMCSR7_PMCSR716 (0x00010000uL) -#define GPIO_PMCSR7_PMCSR717 (0x00020000uL) -#define GPIO_PMCSR7_PMCSR718 (0x00040000uL) -#define GPIO_PMCSR7_PMCSR719 (0x00080000uL) -#define GPIO_PMCSR7_PMCSR720 (0x00100000uL) -#define GPIO_PMCSR7_PMCSR721 (0x00200000uL) -#define GPIO_PMCSR7_PMCSR722 (0x00400000uL) -#define GPIO_PMCSR7_PMCSR723 (0x00800000uL) -#define GPIO_PMCSR7_PMCSR724 (0x01000000uL) -#define GPIO_PMCSR7_PMCSR725 (0x02000000uL) -#define GPIO_PMCSR7_PMCSR726 (0x04000000uL) -#define GPIO_PMCSR7_PMCSR727 (0x08000000uL) -#define GPIO_PMCSR7_PMCSR728 (0x10000000uL) -#define GPIO_PMCSR7_PMCSR729 (0x20000000uL) -#define GPIO_PMCSR7_PMCSR730 (0x40000000uL) -#define GPIO_PMCSR7_PMCSR731 (0x80000000uL) - -#define GPIO_PFCAE7_PFCAE70 (0x0001u) -#define GPIO_PFCAE7_PFCAE71 (0x0002u) -#define GPIO_PFCAE7_PFCAE72 (0x0004u) -#define GPIO_PFCAE7_PFCAE73 (0x0008u) -#define GPIO_PFCAE7_PFCAE74 (0x0010u) -#define GPIO_PFCAE7_PFCAE75 (0x0020u) -#define GPIO_PFCAE7_PFCAE76 (0x0040u) -#define GPIO_PFCAE7_PFCAE77 (0x0080u) -#define GPIO_PFCAE7_PFCAE78 (0x0100u) -#define GPIO_PFCAE7_PFCAE79 (0x0200u) -#define GPIO_PFCAE7_PFCAE710 (0x0400u) -#define GPIO_PFCAE7_PFCAE711 (0x0800u) -#define GPIO_PFCAE7_PFCAE712 (0x1000u) -#define GPIO_PFCAE7_PFCAE713 (0x2000u) -#define GPIO_PFCAE7_PFCAE714 (0x4000u) -#define GPIO_PFCAE7_PFCAE715 (0x8000u) - -#define GPIO_PIBC7_PIBC70 (0x0001u) -#define GPIO_PIBC7_PIBC71 (0x0002u) -#define GPIO_PIBC7_PIBC72 (0x0004u) -#define GPIO_PIBC7_PIBC73 (0x0008u) -#define GPIO_PIBC7_PIBC74 (0x0010u) -#define GPIO_PIBC7_PIBC75 (0x0020u) -#define GPIO_PIBC7_PIBC76 (0x0040u) -#define GPIO_PIBC7_PIBC77 (0x0080u) -#define GPIO_PIBC7_PIBC78 (0x0100u) -#define GPIO_PIBC7_PIBC79 (0x0200u) -#define GPIO_PIBC7_PIBC710 (0x0400u) -#define GPIO_PIBC7_PIBC711 (0x0800u) -#define GPIO_PIBC7_PIBC712 (0x1000u) -#define GPIO_PIBC7_PIBC713 (0x2000u) -#define GPIO_PIBC7_PIBC714 (0x4000u) -#define GPIO_PIBC7_PIBC715 (0x8000u) - -#define GPIO_PBDC7_PBDC70 (0x0001u) -#define GPIO_PBDC7_PBDC71 (0x0002u) -#define GPIO_PBDC7_PBDC72 (0x0004u) -#define GPIO_PBDC7_PBDC73 (0x0008u) -#define GPIO_PBDC7_PBDC74 (0x0010u) -#define GPIO_PBDC7_PBDC75 (0x0020u) -#define GPIO_PBDC7_PBDC76 (0x0040u) -#define GPIO_PBDC7_PBDC77 (0x0080u) -#define GPIO_PBDC7_PBDC78 (0x0100u) -#define GPIO_PBDC7_PBDC79 (0x0200u) -#define GPIO_PBDC7_PBDC710 (0x0400u) -#define GPIO_PBDC7_PBDC711 (0x0800u) -#define GPIO_PBDC7_PBDC712 (0x1000u) -#define GPIO_PBDC7_PBDC713 (0x2000u) -#define GPIO_PBDC7_PBDC714 (0x4000u) -#define GPIO_PBDC7_PBDC715 (0x8000u) - -#define GPIO_PIPC7_PIPC70 (0x0001u) -#define GPIO_PIPC7_PIPC71 (0x0002u) -#define GPIO_PIPC7_PIPC72 (0x0004u) -#define GPIO_PIPC7_PIPC73 (0x0008u) -#define GPIO_PIPC7_PIPC74 (0x0010u) -#define GPIO_PIPC7_PIPC75 (0x0020u) -#define GPIO_PIPC7_PIPC76 (0x0040u) -#define GPIO_PIPC7_PIPC77 (0x0080u) -#define GPIO_PIPC7_PIPC78 (0x0100u) -#define GPIO_PIPC7_PIPC79 (0x0200u) -#define GPIO_PIPC7_PIPC710 (0x0400u) -#define GPIO_PIPC7_PIPC711 (0x0800u) -#define GPIO_PIPC7_PIPC712 (0x1000u) -#define GPIO_PIPC7_PIPC713 (0x2000u) -#define GPIO_PIPC7_PIPC714 (0x4000u) -#define GPIO_PIPC7_PIPC715 (0x8000u) - -/* ---- P8 ---- */ -#define GPIO_P8_P80 (0x0001u) -#define GPIO_P8_P81 (0x0002u) -#define GPIO_P8_P82 (0x0004u) -#define GPIO_P8_P83 (0x0008u) -#define GPIO_P8_P84 (0x0010u) -#define GPIO_P8_P85 (0x0020u) -#define GPIO_P8_P86 (0x0040u) -#define GPIO_P8_P87 (0x0080u) -#define GPIO_P8_P88 (0x0100u) -#define GPIO_P8_P89 (0x0200u) -#define GPIO_P8_P810 (0x0400u) -#define GPIO_P8_P811 (0x0800u) -#define GPIO_P8_P812 (0x1000u) -#define GPIO_P8_P813 (0x2000u) -#define GPIO_P8_P814 (0x4000u) -#define GPIO_P8_P815 (0x8000u) - -#define GPIO_PSR8_PSR80 (0x00000001uL) -#define GPIO_PSR8_PSR81 (0x00000002uL) -#define GPIO_PSR8_PSR82 (0x00000004uL) -#define GPIO_PSR8_PSR83 (0x00000008uL) -#define GPIO_PSR8_PSR84 (0x00000010uL) -#define GPIO_PSR8_PSR85 (0x00000020uL) -#define GPIO_PSR8_PSR86 (0x00000040uL) -#define GPIO_PSR8_PSR87 (0x00000080uL) -#define GPIO_PSR8_PSR88 (0x00000100uL) -#define GPIO_PSR8_PSR89 (0x00000200uL) -#define GPIO_PSR8_PSR810 (0x00000400uL) -#define GPIO_PSR8_PSR811 (0x00000800uL) -#define GPIO_PSR8_PSR812 (0x00001000uL) -#define GPIO_PSR8_PSR813 (0x00002000uL) -#define GPIO_PSR8_PSR814 (0x00004000uL) -#define GPIO_PSR8_PSR815 (0x00008000uL) -#define GPIO_PSR8_PSR816 (0x00010000uL) -#define GPIO_PSR8_PSR817 (0x00020000uL) -#define GPIO_PSR8_PSR818 (0x00040000uL) -#define GPIO_PSR8_PSR819 (0x00080000uL) -#define GPIO_PSR8_PSR820 (0x00100000uL) -#define GPIO_PSR8_PSR821 (0x00200000uL) -#define GPIO_PSR8_PSR822 (0x00400000uL) -#define GPIO_PSR8_PSR823 (0x00800000uL) -#define GPIO_PSR8_PSR824 (0x01000000uL) -#define GPIO_PSR8_PSR825 (0x02000000uL) -#define GPIO_PSR8_PSR826 (0x04000000uL) -#define GPIO_PSR8_PSR827 (0x08000000uL) -#define GPIO_PSR8_PSR828 (0x10000000uL) -#define GPIO_PSR8_PSR829 (0x20000000uL) -#define GPIO_PSR8_PSR830 (0x40000000uL) -#define GPIO_PSR8_PSR831 (0x80000000uL) - -#define GPIO_PPR8_PPR80 (0x0001u) -#define GPIO_PPR8_PPR81 (0x0002u) -#define GPIO_PPR8_PPR82 (0x0004u) -#define GPIO_PPR8_PPR83 (0x0008u) -#define GPIO_PPR8_PPR84 (0x0010u) -#define GPIO_PPR8_PPR85 (0x0020u) -#define GPIO_PPR8_PPR86 (0x0040u) -#define GPIO_PPR8_PPR87 (0x0080u) -#define GPIO_PPR8_PPR88 (0x0100u) -#define GPIO_PPR8_PPR89 (0x0200u) -#define GPIO_PPR8_PPR810 (0x0400u) -#define GPIO_PPR8_PPR811 (0x0800u) -#define GPIO_PPR8_PPR812 (0x1000u) -#define GPIO_PPR8_PPR813 (0x2000u) -#define GPIO_PPR8_PPR814 (0x4000u) -#define GPIO_PPR8_PPR815 (0x8000u) - -#define GPIO_PM8_PM80 (0x0001u) -#define GPIO_PM8_PM81 (0x0002u) -#define GPIO_PM8_PM82 (0x0004u) -#define GPIO_PM8_PM83 (0x0008u) -#define GPIO_PM8_PM84 (0x0010u) -#define GPIO_PM8_PM85 (0x0020u) -#define GPIO_PM8_PM86 (0x0040u) -#define GPIO_PM8_PM87 (0x0080u) -#define GPIO_PM8_PM88 (0x0100u) -#define GPIO_PM8_PM89 (0x0200u) -#define GPIO_PM8_PM810 (0x0400u) -#define GPIO_PM8_PM811 (0x0800u) -#define GPIO_PM8_PM812 (0x1000u) -#define GPIO_PM8_PM813 (0x2000u) -#define GPIO_PM8_PM814 (0x4000u) -#define GPIO_PM8_PM815 (0x8000u) - -#define GPIO_PMC8_PMC80 (0x0001u) -#define GPIO_PMC8_PMC81 (0x0002u) -#define GPIO_PMC8_PMC82 (0x0004u) -#define GPIO_PMC8_PMC83 (0x0008u) -#define GPIO_PMC8_PMC84 (0x0010u) -#define GPIO_PMC8_PMC85 (0x0020u) -#define GPIO_PMC8_PMC86 (0x0040u) -#define GPIO_PMC8_PMC87 (0x0080u) -#define GPIO_PMC8_PMC88 (0x0100u) -#define GPIO_PMC8_PMC89 (0x0200u) -#define GPIO_PMC8_PMC810 (0x0400u) -#define GPIO_PMC8_PMC811 (0x0800u) -#define GPIO_PMC8_PMC812 (0x1000u) -#define GPIO_PMC8_PMC813 (0x2000u) -#define GPIO_PMC8_PMC814 (0x4000u) -#define GPIO_PMC8_PMC815 (0x8000u) - -#define GPIO_PFC8_PFC80 (0x0001u) -#define GPIO_PFC8_PFC81 (0x0002u) -#define GPIO_PFC8_PFC82 (0x0004u) -#define GPIO_PFC8_PFC83 (0x0008u) -#define GPIO_PFC8_PFC84 (0x0010u) -#define GPIO_PFC8_PFC85 (0x0020u) -#define GPIO_PFC8_PFC86 (0x0040u) -#define GPIO_PFC8_PFC87 (0x0080u) -#define GPIO_PFC8_PFC88 (0x0100u) -#define GPIO_PFC8_PFC89 (0x0200u) -#define GPIO_PFC8_PFC810 (0x0400u) -#define GPIO_PFC8_PFC811 (0x0800u) -#define GPIO_PFC8_PFC812 (0x1000u) -#define GPIO_PFC8_PFC813 (0x2000u) -#define GPIO_PFC8_PFC814 (0x4000u) -#define GPIO_PFC8_PFC815 (0x8000u) - -#define GPIO_PFCE8_PFCE80 (0x0001u) -#define GPIO_PFCE8_PFCE81 (0x0002u) -#define GPIO_PFCE8_PFCE82 (0x0004u) -#define GPIO_PFCE8_PFCE83 (0x0008u) -#define GPIO_PFCE8_PFCE84 (0x0010u) -#define GPIO_PFCE8_PFCE85 (0x0020u) -#define GPIO_PFCE8_PFCE86 (0x0040u) -#define GPIO_PFCE8_PFCE87 (0x0080u) -#define GPIO_PFCE8_PFCE88 (0x0100u) -#define GPIO_PFCE8_PFCE89 (0x0200u) -#define GPIO_PFCE8_PFCE810 (0x0400u) -#define GPIO_PFCE8_PFCE811 (0x0800u) -#define GPIO_PFCE8_PFCE812 (0x1000u) -#define GPIO_PFCE8_PFCE813 (0x2000u) -#define GPIO_PFCE8_PFCE814 (0x4000u) -#define GPIO_PFCE8_PFCE815 (0x8000u) - -#define GPIO_PNOT8_PNOT80 (0x0001u) -#define GPIO_PNOT8_PNOT81 (0x0002u) -#define GPIO_PNOT8_PNOT82 (0x0004u) -#define GPIO_PNOT8_PNOT83 (0x0008u) -#define GPIO_PNOT8_PNOT84 (0x0010u) -#define GPIO_PNOT8_PNOT85 (0x0020u) -#define GPIO_PNOT8_PNOT86 (0x0040u) -#define GPIO_PNOT8_PNOT87 (0x0080u) -#define GPIO_PNOT8_PNOT88 (0x0100u) -#define GPIO_PNOT8_PNOT89 (0x0200u) -#define GPIO_PNOT8_PNOT810 (0x0400u) -#define GPIO_PNOT8_PNOT811 (0x0800u) -#define GPIO_PNOT8_PNOT812 (0x1000u) -#define GPIO_PNOT8_PNOT813 (0x2000u) -#define GPIO_PNOT8_PNOT814 (0x4000u) -#define GPIO_PNOT8_PNOT815 (0x8000u) - -#define GPIO_PMSR8_PMSR80 (0x00000001uL) -#define GPIO_PMSR8_PMSR81 (0x00000002uL) -#define GPIO_PMSR8_PMSR82 (0x00000004uL) -#define GPIO_PMSR8_PMSR83 (0x00000008uL) -#define GPIO_PMSR8_PMSR84 (0x00000010uL) -#define GPIO_PMSR8_PMSR85 (0x00000020uL) -#define GPIO_PMSR8_PMSR86 (0x00000040uL) -#define GPIO_PMSR8_PMSR87 (0x00000080uL) -#define GPIO_PMSR8_PMSR88 (0x00000100uL) -#define GPIO_PMSR8_PMSR89 (0x00000200uL) -#define GPIO_PMSR8_PMSR810 (0x00000400uL) -#define GPIO_PMSR8_PMSR811 (0x00000800uL) -#define GPIO_PMSR8_PMSR812 (0x00001000uL) -#define GPIO_PMSR8_PMSR813 (0x00002000uL) -#define GPIO_PMSR8_PMSR814 (0x00004000uL) -#define GPIO_PMSR8_PMSR815 (0x00008000uL) -#define GPIO_PMSR8_PMSR816 (0x00010000uL) -#define GPIO_PMSR8_PMSR817 (0x00020000uL) -#define GPIO_PMSR8_PMSR818 (0x00040000uL) -#define GPIO_PMSR8_PMSR819 (0x00080000uL) -#define GPIO_PMSR8_PMSR820 (0x00100000uL) -#define GPIO_PMSR8_PMSR821 (0x00200000uL) -#define GPIO_PMSR8_PMSR822 (0x00400000uL) -#define GPIO_PMSR8_PMSR823 (0x00800000uL) -#define GPIO_PMSR8_PMSR824 (0x01000000uL) -#define GPIO_PMSR8_PMSR825 (0x02000000uL) -#define GPIO_PMSR8_PMSR826 (0x04000000uL) -#define GPIO_PMSR8_PMSR827 (0x08000000uL) -#define GPIO_PMSR8_PMSR828 (0x10000000uL) -#define GPIO_PMSR8_PMSR829 (0x20000000uL) -#define GPIO_PMSR8_PMSR830 (0x40000000uL) -#define GPIO_PMSR8_PMSR831 (0x80000000uL) - -#define GPIO_PMCSR8_PMCSR80 (0x00000001uL) -#define GPIO_PMCSR8_PMCSR81 (0x00000002uL) -#define GPIO_PMCSR8_PMCSR82 (0x00000004uL) -#define GPIO_PMCSR8_PMCSR83 (0x00000008uL) -#define GPIO_PMCSR8_PMCSR84 (0x00000010uL) -#define GPIO_PMCSR8_PMCSR85 (0x00000020uL) -#define GPIO_PMCSR8_PMCSR86 (0x00000040uL) -#define GPIO_PMCSR8_PMCSR87 (0x00000080uL) -#define GPIO_PMCSR8_PMCSR88 (0x00000100uL) -#define GPIO_PMCSR8_PMCSR89 (0x00000200uL) -#define GPIO_PMCSR8_PMCSR810 (0x00000400uL) -#define GPIO_PMCSR8_PMCSR811 (0x00000800uL) -#define GPIO_PMCSR8_PMCSR812 (0x00001000uL) -#define GPIO_PMCSR8_PMCSR813 (0x00002000uL) -#define GPIO_PMCSR8_PMCSR814 (0x00004000uL) -#define GPIO_PMCSR8_PMCSR815 (0x00008000uL) -#define GPIO_PMCSR8_PMCSR816 (0x00010000uL) -#define GPIO_PMCSR8_PMCSR817 (0x00020000uL) -#define GPIO_PMCSR8_PMCSR818 (0x00040000uL) -#define GPIO_PMCSR8_PMCSR819 (0x00080000uL) -#define GPIO_PMCSR8_PMCSR820 (0x00100000uL) -#define GPIO_PMCSR8_PMCSR821 (0x00200000uL) -#define GPIO_PMCSR8_PMCSR822 (0x00400000uL) -#define GPIO_PMCSR8_PMCSR823 (0x00800000uL) -#define GPIO_PMCSR8_PMCSR824 (0x01000000uL) -#define GPIO_PMCSR8_PMCSR825 (0x02000000uL) -#define GPIO_PMCSR8_PMCSR826 (0x04000000uL) -#define GPIO_PMCSR8_PMCSR827 (0x08000000uL) -#define GPIO_PMCSR8_PMCSR828 (0x10000000uL) -#define GPIO_PMCSR8_PMCSR829 (0x20000000uL) -#define GPIO_PMCSR8_PMCSR830 (0x40000000uL) -#define GPIO_PMCSR8_PMCSR831 (0x80000000uL) - -#define GPIO_PFCAE8_PFCAE80 (0x0001u) -#define GPIO_PFCAE8_PFCAE81 (0x0002u) -#define GPIO_PFCAE8_PFCAE82 (0x0004u) -#define GPIO_PFCAE8_PFCAE83 (0x0008u) -#define GPIO_PFCAE8_PFCAE84 (0x0010u) -#define GPIO_PFCAE8_PFCAE85 (0x0020u) -#define GPIO_PFCAE8_PFCAE86 (0x0040u) -#define GPIO_PFCAE8_PFCAE87 (0x0080u) -#define GPIO_PFCAE8_PFCAE88 (0x0100u) -#define GPIO_PFCAE8_PFCAE89 (0x0200u) -#define GPIO_PFCAE8_PFCAE810 (0x0400u) -#define GPIO_PFCAE8_PFCAE811 (0x0800u) -#define GPIO_PFCAE8_PFCAE812 (0x1000u) -#define GPIO_PFCAE8_PFCAE813 (0x2000u) -#define GPIO_PFCAE8_PFCAE814 (0x4000u) -#define GPIO_PFCAE8_PFCAE815 (0x8000u) - -#define GPIO_PIBC8_PIBC80 (0x0001u) -#define GPIO_PIBC8_PIBC81 (0x0002u) -#define GPIO_PIBC8_PIBC82 (0x0004u) -#define GPIO_PIBC8_PIBC83 (0x0008u) -#define GPIO_PIBC8_PIBC84 (0x0010u) -#define GPIO_PIBC8_PIBC85 (0x0020u) -#define GPIO_PIBC8_PIBC86 (0x0040u) -#define GPIO_PIBC8_PIBC87 (0x0080u) -#define GPIO_PIBC8_PIBC88 (0x0100u) -#define GPIO_PIBC8_PIBC89 (0x0200u) -#define GPIO_PIBC8_PIBC810 (0x0400u) -#define GPIO_PIBC8_PIBC811 (0x0800u) -#define GPIO_PIBC8_PIBC812 (0x1000u) -#define GPIO_PIBC8_PIBC813 (0x2000u) -#define GPIO_PIBC8_PIBC814 (0x4000u) -#define GPIO_PIBC8_PIBC815 (0x8000u) - -#define GPIO_PBDC8_PBDC80 (0x0001u) -#define GPIO_PBDC8_PBDC81 (0x0002u) -#define GPIO_PBDC8_PBDC82 (0x0004u) -#define GPIO_PBDC8_PBDC83 (0x0008u) -#define GPIO_PBDC8_PBDC84 (0x0010u) -#define GPIO_PBDC8_PBDC85 (0x0020u) -#define GPIO_PBDC8_PBDC86 (0x0040u) -#define GPIO_PBDC8_PBDC87 (0x0080u) -#define GPIO_PBDC8_PBDC88 (0x0100u) -#define GPIO_PBDC8_PBDC89 (0x0200u) -#define GPIO_PBDC8_PBDC810 (0x0400u) -#define GPIO_PBDC8_PBDC811 (0x0800u) -#define GPIO_PBDC8_PBDC812 (0x1000u) -#define GPIO_PBDC8_PBDC813 (0x2000u) -#define GPIO_PBDC8_PBDC814 (0x4000u) -#define GPIO_PBDC8_PBDC815 (0x8000u) - -#define GPIO_PIPC8_PIPC80 (0x0001u) -#define GPIO_PIPC8_PIPC81 (0x0002u) -#define GPIO_PIPC8_PIPC82 (0x0004u) -#define GPIO_PIPC8_PIPC83 (0x0008u) -#define GPIO_PIPC8_PIPC84 (0x0010u) -#define GPIO_PIPC8_PIPC85 (0x0020u) -#define GPIO_PIPC8_PIPC86 (0x0040u) -#define GPIO_PIPC8_PIPC87 (0x0080u) -#define GPIO_PIPC8_PIPC88 (0x0100u) -#define GPIO_PIPC8_PIPC89 (0x0200u) -#define GPIO_PIPC8_PIPC810 (0x0400u) -#define GPIO_PIPC8_PIPC811 (0x0800u) -#define GPIO_PIPC8_PIPC812 (0x1000u) -#define GPIO_PIPC8_PIPC813 (0x2000u) -#define GPIO_PIPC8_PIPC814 (0x4000u) -#define GPIO_PIPC8_PIPC815 (0x8000u) - -/* ---- P9 ---- */ -#define GPIO_P9_P90 (0x0001u) -#define GPIO_P9_P91 (0x0002u) -#define GPIO_P9_P92 (0x0004u) -#define GPIO_P9_P93 (0x0008u) -#define GPIO_P9_P94 (0x0010u) -#define GPIO_P9_P95 (0x0020u) -#define GPIO_P9_P96 (0x0040u) -#define GPIO_P9_P97 (0x0080u) - -#define GPIO_PSR9_PSR90 (0x00000001uL) -#define GPIO_PSR9_PSR91 (0x00000002uL) -#define GPIO_PSR9_PSR92 (0x00000004uL) -#define GPIO_PSR9_PSR93 (0x00000008uL) -#define GPIO_PSR9_PSR94 (0x00000010uL) -#define GPIO_PSR9_PSR95 (0x00000020uL) -#define GPIO_PSR9_PSR96 (0x00000040uL) -#define GPIO_PSR9_PSR97 (0x00000080uL) -#define GPIO_PSR9_PSR916 (0x00010000uL) -#define GPIO_PSR9_PSR917 (0x00020000uL) -#define GPIO_PSR9_PSR918 (0x00040000uL) -#define GPIO_PSR9_PSR919 (0x00080000uL) -#define GPIO_PSR9_PSR920 (0x00100000uL) -#define GPIO_PSR9_PSR921 (0x00200000uL) -#define GPIO_PSR9_PSR922 (0x00400000uL) -#define GPIO_PSR9_PSR923 (0x00800000uL) - -#define GPIO_PPR9_PPR90 (0x0001u) -#define GPIO_PPR9_PPR91 (0x0002u) -#define GPIO_PPR9_PPR92 (0x0004u) -#define GPIO_PPR9_PPR93 (0x0008u) -#define GPIO_PPR9_PPR94 (0x0010u) -#define GPIO_PPR9_PPR95 (0x0020u) -#define GPIO_PPR9_PPR96 (0x0040u) -#define GPIO_PPR9_PPR97 (0x0080u) - -#define GPIO_PM9_PM90 (0x0001u) -#define GPIO_PM9_PM91 (0x0002u) -#define GPIO_PM9_PM92 (0x0004u) -#define GPIO_PM9_PM93 (0x0008u) -#define GPIO_PM9_PM94 (0x0010u) -#define GPIO_PM9_PM95 (0x0020u) -#define GPIO_PM9_PM96 (0x0040u) -#define GPIO_PM9_PM97 (0x0080u) - -#define GPIO_PMC9_PMC90 (0x0001u) -#define GPIO_PMC9_PMC91 (0x0002u) -#define GPIO_PMC9_PMC92 (0x0004u) -#define GPIO_PMC9_PMC93 (0x0008u) -#define GPIO_PMC9_PMC94 (0x0010u) -#define GPIO_PMC9_PMC95 (0x0020u) -#define GPIO_PMC9_PMC96 (0x0040u) -#define GPIO_PMC9_PMC97 (0x0080u) - -#define GPIO_PFC9_PFC90 (0x0001u) -#define GPIO_PFC9_PFC91 (0x0002u) -#define GPIO_PFC9_PFC92 (0x0004u) -#define GPIO_PFC9_PFC93 (0x0008u) -#define GPIO_PFC9_PFC94 (0x0010u) -#define GPIO_PFC9_PFC95 (0x0020u) -#define GPIO_PFC9_PFC96 (0x0040u) -#define GPIO_PFC9_PFC97 (0x0080u) - -#define GPIO_PFCE9_PFCE90 (0x0001u) -#define GPIO_PFCE9_PFCE91 (0x0002u) -#define GPIO_PFCE9_PFCE92 (0x0004u) -#define GPIO_PFCE9_PFCE93 (0x0008u) -#define GPIO_PFCE9_PFCE94 (0x0010u) -#define GPIO_PFCE9_PFCE95 (0x0020u) -#define GPIO_PFCE9_PFCE96 (0x0040u) -#define GPIO_PFCE9_PFCE97 (0x0080u) - -#define GPIO_PNOT9_PNOT90 (0x0001u) -#define GPIO_PNOT9_PNOT91 (0x0002u) -#define GPIO_PNOT9_PNOT92 (0x0004u) -#define GPIO_PNOT9_PNOT93 (0x0008u) -#define GPIO_PNOT9_PNOT94 (0x0010u) -#define GPIO_PNOT9_PNOT95 (0x0020u) -#define GPIO_PNOT9_PNOT96 (0x0040u) -#define GPIO_PNOT9_PNOT97 (0x0080u) - -#define GPIO_PMSR9_PMSR90 (0x00000001uL) -#define GPIO_PMSR9_PMSR91 (0x00000002uL) -#define GPIO_PMSR9_PMSR92 (0x00000004uL) -#define GPIO_PMSR9_PMSR93 (0x00000008uL) -#define GPIO_PMSR9_PMSR94 (0x00000010uL) -#define GPIO_PMSR9_PMSR95 (0x00000020uL) -#define GPIO_PMSR9_PMSR96 (0x00000040uL) -#define GPIO_PMSR9_PMSR97 (0x00000080uL) -#define GPIO_PMSR9_PMSR916 (0x00010000uL) -#define GPIO_PMSR9_PMSR917 (0x00020000uL) -#define GPIO_PMSR9_PMSR918 (0x00040000uL) -#define GPIO_PMSR9_PMSR919 (0x00080000uL) -#define GPIO_PMSR9_PMSR920 (0x00100000uL) -#define GPIO_PMSR9_PMSR921 (0x00200000uL) -#define GPIO_PMSR9_PMSR922 (0x00400000uL) -#define GPIO_PMSR9_PMSR923 (0x00800000uL) - -#define GPIO_PMCSR9_PMCSR90 (0x00000001uL) -#define GPIO_PMCSR9_PMCSR91 (0x00000002uL) -#define GPIO_PMCSR9_PMCSR92 (0x00000004uL) -#define GPIO_PMCSR9_PMCSR93 (0x00000008uL) -#define GPIO_PMCSR9_PMCSR94 (0x00000010uL) -#define GPIO_PMCSR9_PMCSR95 (0x00000020uL) -#define GPIO_PMCSR9_PMCSR96 (0x00000040uL) -#define GPIO_PMCSR9_PMCSR97 (0x00000080uL) -#define GPIO_PMCSR9_PMCSR916 (0x00010000uL) -#define GPIO_PMCSR9_PMCSR917 (0x00020000uL) -#define GPIO_PMCSR9_PMCSR918 (0x00040000uL) -#define GPIO_PMCSR9_PMCSR919 (0x00080000uL) -#define GPIO_PMCSR9_PMCSR920 (0x00100000uL) -#define GPIO_PMCSR9_PMCSR921 (0x00200000uL) -#define GPIO_PMCSR9_PMCSR922 (0x00400000uL) -#define GPIO_PMCSR9_PMCSR923 (0x00800000uL) - -#define GPIO_PFCAE9_PFCAE90 (0x0001u) -#define GPIO_PFCAE9_PFCAE91 (0x0002u) -#define GPIO_PFCAE9_PFCAE92 (0x0004u) -#define GPIO_PFCAE9_PFCAE93 (0x0008u) -#define GPIO_PFCAE9_PFCAE94 (0x0010u) -#define GPIO_PFCAE9_PFCAE95 (0x0020u) -#define GPIO_PFCAE9_PFCAE96 (0x0040u) -#define GPIO_PFCAE9_PFCAE97 (0x0080u) - -#define GPIO_PIBC9_PIBC90 (0x0001u) -#define GPIO_PIBC9_PIBC91 (0x0002u) -#define GPIO_PIBC9_PIBC92 (0x0004u) -#define GPIO_PIBC9_PIBC93 (0x0008u) -#define GPIO_PIBC9_PIBC94 (0x0010u) -#define GPIO_PIBC9_PIBC95 (0x0020u) -#define GPIO_PIBC9_PIBC96 (0x0040u) -#define GPIO_PIBC9_PIBC97 (0x0080u) - -#define GPIO_PBDC9_PBDC90 (0x0001u) -#define GPIO_PBDC9_PBDC91 (0x0002u) -#define GPIO_PBDC9_PBDC92 (0x0004u) -#define GPIO_PBDC9_PBDC93 (0x0008u) -#define GPIO_PBDC9_PBDC94 (0x0010u) -#define GPIO_PBDC9_PBDC95 (0x0020u) -#define GPIO_PBDC9_PBDC96 (0x0040u) -#define GPIO_PBDC9_PBDC97 (0x0080u) - -#define GPIO_PIPC9_PIPC90 (0x0001u) -#define GPIO_PIPC9_PIPC91 (0x0002u) -#define GPIO_PIPC9_PIPC92 (0x0004u) -#define GPIO_PIPC9_PIPC93 (0x0008u) -#define GPIO_PIPC9_PIPC94 (0x0010u) -#define GPIO_PIPC9_PIPC95 (0x0020u) -#define GPIO_PIPC9_PIPC96 (0x0040u) -#define GPIO_PIPC9_PIPC97 (0x0080u) - -/* ---- P10 ---- */ -#define GPIO_P10_P100 (0x0001u) -#define GPIO_P10_P101 (0x0002u) -#define GPIO_P10_P102 (0x0004u) -#define GPIO_P10_P103 (0x0008u) -#define GPIO_P10_P104 (0x0010u) -#define GPIO_P10_P105 (0x0020u) -#define GPIO_P10_P106 (0x0040u) -#define GPIO_P10_P107 (0x0080u) -#define GPIO_P10_P108 (0x0100u) -#define GPIO_P10_P109 (0x0200u) -#define GPIO_P10_P1010 (0x0400u) -#define GPIO_P10_P1011 (0x0800u) -#define GPIO_P10_P1012 (0x1000u) -#define GPIO_P10_P1013 (0x2000u) -#define GPIO_P10_P1014 (0x4000u) -#define GPIO_P10_P1015 (0x8000u) - -#define GPIO_PSR10_PSR100 (0x00000001uL) -#define GPIO_PSR10_PSR101 (0x00000002uL) -#define GPIO_PSR10_PSR102 (0x00000004uL) -#define GPIO_PSR10_PSR103 (0x00000008uL) -#define GPIO_PSR10_PSR104 (0x00000010uL) -#define GPIO_PSR10_PSR105 (0x00000020uL) -#define GPIO_PSR10_PSR106 (0x00000040uL) -#define GPIO_PSR10_PSR107 (0x00000080uL) -#define GPIO_PSR10_PSR108 (0x00000100uL) -#define GPIO_PSR10_PSR109 (0x00000200uL) -#define GPIO_PSR10_PSR1010 (0x00000400uL) -#define GPIO_PSR10_PSR1011 (0x00000800uL) -#define GPIO_PSR10_PSR1012 (0x00001000uL) -#define GPIO_PSR10_PSR1013 (0x00002000uL) -#define GPIO_PSR10_PSR1014 (0x00004000uL) -#define GPIO_PSR10_PSR1015 (0x00008000uL) -#define GPIO_PSR10_PSR1016 (0x00010000uL) -#define GPIO_PSR10_PSR1017 (0x00020000uL) -#define GPIO_PSR10_PSR1018 (0x00040000uL) -#define GPIO_PSR10_PSR1019 (0x00080000uL) -#define GPIO_PSR10_PSR1020 (0x00100000uL) -#define GPIO_PSR10_PSR1021 (0x00200000uL) -#define GPIO_PSR10_PSR1022 (0x00400000uL) -#define GPIO_PSR10_PSR1023 (0x00800000uL) -#define GPIO_PSR10_PSR1024 (0x01000000uL) -#define GPIO_PSR10_PSR1025 (0x02000000uL) -#define GPIO_PSR10_PSR1026 (0x04000000uL) -#define GPIO_PSR10_PSR1027 (0x08000000uL) -#define GPIO_PSR10_PSR1028 (0x10000000uL) -#define GPIO_PSR10_PSR1029 (0x20000000uL) -#define GPIO_PSR10_PSR1030 (0x40000000uL) -#define GPIO_PSR10_PSR1031 (0x80000000uL) - -#define GPIO_PPR10_PPR100 (0x0001u) -#define GPIO_PPR10_PPR101 (0x0002u) -#define GPIO_PPR10_PPR102 (0x0004u) -#define GPIO_PPR10_PPR103 (0x0008u) -#define GPIO_PPR10_PPR104 (0x0010u) -#define GPIO_PPR10_PPR105 (0x0020u) -#define GPIO_PPR10_PPR106 (0x0040u) -#define GPIO_PPR10_PPR107 (0x0080u) -#define GPIO_PPR10_PPR108 (0x0100u) -#define GPIO_PPR10_PPR109 (0x0200u) -#define GPIO_PPR10_PPR1010 (0x0400u) -#define GPIO_PPR10_PPR1011 (0x0800u) -#define GPIO_PPR10_PPR1012 (0x1000u) -#define GPIO_PPR10_PPR1013 (0x2000u) -#define GPIO_PPR10_PPR1014 (0x4000u) -#define GPIO_PPR10_PPR1015 (0x8000u) - -#define GPIO_PM10_PM100 (0x0001u) -#define GPIO_PM10_PM101 (0x0002u) -#define GPIO_PM10_PM102 (0x0004u) -#define GPIO_PM10_PM103 (0x0008u) -#define GPIO_PM10_PM104 (0x0010u) -#define GPIO_PM10_PM105 (0x0020u) -#define GPIO_PM10_PM106 (0x0040u) -#define GPIO_PM10_PM107 (0x0080u) -#define GPIO_PM10_PM108 (0x0100u) -#define GPIO_PM10_PM109 (0x0200u) -#define GPIO_PM10_PM1010 (0x0400u) -#define GPIO_PM10_PM1011 (0x0800u) -#define GPIO_PM10_PM1012 (0x1000u) -#define GPIO_PM10_PM1013 (0x2000u) -#define GPIO_PM10_PM1014 (0x4000u) -#define GPIO_PM10_PM1015 (0x8000u) - -#define GPIO_PMC10_PMC100 (0x0001u) -#define GPIO_PMC10_PMC101 (0x0002u) -#define GPIO_PMC10_PMC102 (0x0004u) -#define GPIO_PMC10_PMC103 (0x0008u) -#define GPIO_PMC10_PMC104 (0x0010u) -#define GPIO_PMC10_PMC105 (0x0020u) -#define GPIO_PMC10_PMC106 (0x0040u) -#define GPIO_PMC10_PMC107 (0x0080u) -#define GPIO_PMC10_PMC108 (0x0100u) -#define GPIO_PMC10_PMC109 (0x0200u) -#define GPIO_PMC10_PMC1010 (0x0400u) -#define GPIO_PMC10_PMC1011 (0x0800u) -#define GPIO_PMC10_PMC1012 (0x1000u) -#define GPIO_PMC10_PMC1013 (0x2000u) -#define GPIO_PMC10_PMC1014 (0x4000u) -#define GPIO_PMC10_PMC1015 (0x8000u) - -#define GPIO_PFC10_PFC100 (0x0001u) -#define GPIO_PFC10_PFC101 (0x0002u) -#define GPIO_PFC10_PFC102 (0x0004u) -#define GPIO_PFC10_PFC103 (0x0008u) -#define GPIO_PFC10_PFC104 (0x0010u) -#define GPIO_PFC10_PFC105 (0x0020u) -#define GPIO_PFC10_PFC106 (0x0040u) -#define GPIO_PFC10_PFC107 (0x0080u) -#define GPIO_PFC10_PFC108 (0x0100u) -#define GPIO_PFC10_PFC109 (0x0200u) -#define GPIO_PFC10_PFC1010 (0x0400u) -#define GPIO_PFC10_PFC1011 (0x0800u) -#define GPIO_PFC10_PFC1012 (0x1000u) -#define GPIO_PFC10_PFC1013 (0x2000u) -#define GPIO_PFC10_PFC1014 (0x4000u) -#define GPIO_PFC10_PFC1015 (0x8000u) - -#define GPIO_PFCE10_PFCE100 (0x0001u) -#define GPIO_PFCE10_PFCE101 (0x0002u) -#define GPIO_PFCE10_PFCE102 (0x0004u) -#define GPIO_PFCE10_PFCE103 (0x0008u) -#define GPIO_PFCE10_PFCE104 (0x0010u) -#define GPIO_PFCE10_PFCE105 (0x0020u) -#define GPIO_PFCE10_PFCE106 (0x0040u) -#define GPIO_PFCE10_PFCE107 (0x0080u) -#define GPIO_PFCE10_PFCE108 (0x0100u) -#define GPIO_PFCE10_PFCE109 (0x0200u) -#define GPIO_PFCE10_PFCE1010 (0x0400u) -#define GPIO_PFCE10_PFCE1011 (0x0800u) -#define GPIO_PFCE10_PFCE1012 (0x1000u) -#define GPIO_PFCE10_PFCE1013 (0x2000u) -#define GPIO_PFCE10_PFCE1014 (0x4000u) -#define GPIO_PFCE10_PFCE1015 (0x8000u) - -#define GPIO_PNOT10_PNOT100 (0x0001u) -#define GPIO_PNOT10_PNOT101 (0x0002u) -#define GPIO_PNOT10_PNOT102 (0x0004u) -#define GPIO_PNOT10_PNOT103 (0x0008u) -#define GPIO_PNOT10_PNOT104 (0x0010u) -#define GPIO_PNOT10_PNOT105 (0x0020u) -#define GPIO_PNOT10_PNOT106 (0x0040u) -#define GPIO_PNOT10_PNOT107 (0x0080u) -#define GPIO_PNOT10_PNOT108 (0x0100u) -#define GPIO_PNOT10_PNOT109 (0x0200u) -#define GPIO_PNOT10_PNOT1010 (0x0400u) -#define GPIO_PNOT10_PNOT1011 (0x0800u) -#define GPIO_PNOT10_PNOT1012 (0x1000u) -#define GPIO_PNOT10_PNOT1013 (0x2000u) -#define GPIO_PNOT10_PNOT1014 (0x4000u) -#define GPIO_PNOT10_PNOT1015 (0x8000u) - -#define GPIO_PMSR10_PMSR100 (0x00000001uL) -#define GPIO_PMSR10_PMSR101 (0x00000002uL) -#define GPIO_PMSR10_PMSR102 (0x00000004uL) -#define GPIO_PMSR10_PMSR103 (0x00000008uL) -#define GPIO_PMSR10_PMSR104 (0x00000010uL) -#define GPIO_PMSR10_PMSR105 (0x00000020uL) -#define GPIO_PMSR10_PMSR106 (0x00000040uL) -#define GPIO_PMSR10_PMSR107 (0x00000080uL) -#define GPIO_PMSR10_PMSR108 (0x00000100uL) -#define GPIO_PMSR10_PMSR109 (0x00000200uL) -#define GPIO_PMSR10_PMSR1010 (0x00000400uL) -#define GPIO_PMSR10_PMSR1011 (0x00000800uL) -#define GPIO_PMSR10_PMSR1012 (0x00001000uL) -#define GPIO_PMSR10_PMSR1013 (0x00002000uL) -#define GPIO_PMSR10_PMSR1014 (0x00004000uL) -#define GPIO_PMSR10_PMSR1015 (0x00008000uL) -#define GPIO_PMSR10_PMSR1016 (0x00010000uL) -#define GPIO_PMSR10_PMSR1017 (0x00020000uL) -#define GPIO_PMSR10_PMSR1018 (0x00040000uL) -#define GPIO_PMSR10_PMSR1019 (0x00080000uL) -#define GPIO_PMSR10_PMSR1020 (0x00100000uL) -#define GPIO_PMSR10_PMSR1021 (0x00200000uL) -#define GPIO_PMSR10_PMSR1022 (0x00400000uL) -#define GPIO_PMSR10_PMSR1023 (0x00800000uL) -#define GPIO_PMSR10_PMSR1024 (0x01000000uL) -#define GPIO_PMSR10_PMSR1025 (0x02000000uL) -#define GPIO_PMSR10_PMSR1026 (0x04000000uL) -#define GPIO_PMSR10_PMSR1027 (0x08000000uL) -#define GPIO_PMSR10_PMSR1028 (0x10000000uL) -#define GPIO_PMSR10_PMSR1029 (0x20000000uL) -#define GPIO_PMSR10_PMSR1030 (0x40000000uL) -#define GPIO_PMSR10_PMSR1031 (0x80000000uL) - -#define GPIO_PMCSR10_PMCSR100 (0x00000001uL) -#define GPIO_PMCSR10_PMCSR101 (0x00000002uL) -#define GPIO_PMCSR10_PMCSR102 (0x00000004uL) -#define GPIO_PMCSR10_PMCSR103 (0x00000008uL) -#define GPIO_PMCSR10_PMCSR104 (0x00000010uL) -#define GPIO_PMCSR10_PMCSR105 (0x00000020uL) -#define GPIO_PMCSR10_PMCSR106 (0x00000040uL) -#define GPIO_PMCSR10_PMCSR107 (0x00000080uL) -#define GPIO_PMCSR10_PMCSR108 (0x00000100uL) -#define GPIO_PMCSR10_PMCSR109 (0x00000200uL) -#define GPIO_PMCSR10_PMCSR1010 (0x00000400uL) -#define GPIO_PMCSR10_PMCSR1011 (0x00000800uL) -#define GPIO_PMCSR10_PMCSR1012 (0x00001000uL) -#define GPIO_PMCSR10_PMCSR1013 (0x00002000uL) -#define GPIO_PMCSR10_PMCSR1014 (0x00004000uL) -#define GPIO_PMCSR10_PMCSR1015 (0x00008000uL) -#define GPIO_PMCSR10_PMCSR1016 (0x00010000uL) -#define GPIO_PMCSR10_PMCSR1017 (0x00020000uL) -#define GPIO_PMCSR10_PMCSR1018 (0x00040000uL) -#define GPIO_PMCSR10_PMCSR1019 (0x00080000uL) -#define GPIO_PMCSR10_PMCSR1020 (0x00100000uL) -#define GPIO_PMCSR10_PMCSR1021 (0x00200000uL) -#define GPIO_PMCSR10_PMCSR1022 (0x00400000uL) -#define GPIO_PMCSR10_PMCSR1023 (0x00800000uL) -#define GPIO_PMCSR10_PMCSR1024 (0x01000000uL) -#define GPIO_PMCSR10_PMCSR1025 (0x02000000uL) -#define GPIO_PMCSR10_PMCSR1026 (0x04000000uL) -#define GPIO_PMCSR10_PMCSR1027 (0x08000000uL) -#define GPIO_PMCSR10_PMCSR1028 (0x10000000uL) -#define GPIO_PMCSR10_PMCSR1029 (0x20000000uL) -#define GPIO_PMCSR10_PMCSR1030 (0x40000000uL) -#define GPIO_PMCSR10_PMCSR1031 (0x80000000uL) - -#define GPIO_PFCAE10_PFCAE100 (0x0001u) -#define GPIO_PFCAE10_PFCAE101 (0x0002u) -#define GPIO_PFCAE10_PFCAE102 (0x0004u) -#define GPIO_PFCAE10_PFCAE103 (0x0008u) -#define GPIO_PFCAE10_PFCAE104 (0x0010u) -#define GPIO_PFCAE10_PFCAE105 (0x0020u) -#define GPIO_PFCAE10_PFCAE106 (0x0040u) -#define GPIO_PFCAE10_PFCAE107 (0x0080u) -#define GPIO_PFCAE10_PFCAE108 (0x0100u) -#define GPIO_PFCAE10_PFCAE109 (0x0200u) -#define GPIO_PFCAE10_PFCAE1010 (0x0400u) -#define GPIO_PFCAE10_PFCAE1011 (0x0800u) -#define GPIO_PFCAE10_PFCAE1012 (0x1000u) -#define GPIO_PFCAE10_PFCAE1013 (0x2000u) -#define GPIO_PFCAE10_PFCAE1014 (0x4000u) -#define GPIO_PFCAE10_PFCAE1015 (0x8000u) - -#define GPIO_PIBC10_PIBC100 (0x0001u) -#define GPIO_PIBC10_PIBC101 (0x0002u) -#define GPIO_PIBC10_PIBC102 (0x0004u) -#define GPIO_PIBC10_PIBC103 (0x0008u) -#define GPIO_PIBC10_PIBC104 (0x0010u) -#define GPIO_PIBC10_PIBC105 (0x0020u) -#define GPIO_PIBC10_PIBC106 (0x0040u) -#define GPIO_PIBC10_PIBC107 (0x0080u) -#define GPIO_PIBC10_PIBC108 (0x0100u) -#define GPIO_PIBC10_PIBC109 (0x0200u) -#define GPIO_PIBC10_PIBC1010 (0x0400u) -#define GPIO_PIBC10_PIBC1011 (0x0800u) -#define GPIO_PIBC10_PIBC1012 (0x1000u) -#define GPIO_PIBC10_PIBC1013 (0x2000u) -#define GPIO_PIBC10_PIBC1014 (0x4000u) -#define GPIO_PIBC10_PIBC1015 (0x8000u) - -#define GPIO_PBDC10_PBDC100 (0x0001u) -#define GPIO_PBDC10_PBDC101 (0x0002u) -#define GPIO_PBDC10_PBDC102 (0x0004u) -#define GPIO_PBDC10_PBDC103 (0x0008u) -#define GPIO_PBDC10_PBDC104 (0x0010u) -#define GPIO_PBDC10_PBDC105 (0x0020u) -#define GPIO_PBDC10_PBDC106 (0x0040u) -#define GPIO_PBDC10_PBDC107 (0x0080u) -#define GPIO_PBDC10_PBDC108 (0x0100u) -#define GPIO_PBDC10_PBDC109 (0x0200u) -#define GPIO_PBDC10_PBDC1010 (0x0400u) -#define GPIO_PBDC10_PBDC1011 (0x0800u) -#define GPIO_PBDC10_PBDC1012 (0x1000u) -#define GPIO_PBDC10_PBDC1013 (0x2000u) -#define GPIO_PBDC10_PBDC1014 (0x4000u) -#define GPIO_PBDC10_PBDC1015 (0x8000u) - -#define GPIO_PIPC10_PIPC100 (0x0001u) -#define GPIO_PIPC10_PIPC101 (0x0002u) -#define GPIO_PIPC10_PIPC102 (0x0004u) -#define GPIO_PIPC10_PIPC103 (0x0008u) -#define GPIO_PIPC10_PIPC104 (0x0010u) -#define GPIO_PIPC10_PIPC105 (0x0020u) -#define GPIO_PIPC10_PIPC106 (0x0040u) -#define GPIO_PIPC10_PIPC107 (0x0080u) -#define GPIO_PIPC10_PIPC108 (0x0100u) -#define GPIO_PIPC10_PIPC109 (0x0200u) -#define GPIO_PIPC10_PIPC1010 (0x0400u) -#define GPIO_PIPC10_PIPC1011 (0x0800u) -#define GPIO_PIPC10_PIPC1012 (0x1000u) -#define GPIO_PIPC10_PIPC1013 (0x2000u) -#define GPIO_PIPC10_PIPC1014 (0x4000u) -#define GPIO_PIPC10_PIPC1015 (0x8000u) - -/* ---- P11 ---- */ -#define GPIO_P11_P110 (0x0001u) -#define GPIO_P11_P111 (0x0002u) -#define GPIO_P11_P112 (0x0004u) -#define GPIO_P11_P113 (0x0008u) -#define GPIO_P11_P114 (0x0010u) -#define GPIO_P11_P115 (0x0020u) -#define GPIO_P11_P116 (0x0040u) -#define GPIO_P11_P117 (0x0080u) -#define GPIO_P11_P118 (0x0100u) -#define GPIO_P11_P119 (0x0200u) -#define GPIO_P11_P1110 (0x0400u) -#define GPIO_P11_P1111 (0x0800u) -#define GPIO_P11_P1112 (0x1000u) -#define GPIO_P11_P1113 (0x2000u) -#define GPIO_P11_P1114 (0x4000u) -#define GPIO_P11_P1115 (0x8000u) - -#define GPIO_PSR11_PSR110 (0x00000001uL) -#define GPIO_PSR11_PSR111 (0x00000002uL) -#define GPIO_PSR11_PSR112 (0x00000004uL) -#define GPIO_PSR11_PSR113 (0x00000008uL) -#define GPIO_PSR11_PSR114 (0x00000010uL) -#define GPIO_PSR11_PSR115 (0x00000020uL) -#define GPIO_PSR11_PSR116 (0x00000040uL) -#define GPIO_PSR11_PSR117 (0x00000080uL) -#define GPIO_PSR11_PSR118 (0x00000100uL) -#define GPIO_PSR11_PSR119 (0x00000200uL) -#define GPIO_PSR11_PSR1110 (0x00000400uL) -#define GPIO_PSR11_PSR1111 (0x00000800uL) -#define GPIO_PSR11_PSR1112 (0x00001000uL) -#define GPIO_PSR11_PSR1113 (0x00002000uL) -#define GPIO_PSR11_PSR1114 (0x00004000uL) -#define GPIO_PSR11_PSR1115 (0x00008000uL) -#define GPIO_PSR11_PSR1116 (0x00010000uL) -#define GPIO_PSR11_PSR1117 (0x00020000uL) -#define GPIO_PSR11_PSR1118 (0x00040000uL) -#define GPIO_PSR11_PSR1119 (0x00080000uL) -#define GPIO_PSR11_PSR1120 (0x00100000uL) -#define GPIO_PSR11_PSR1121 (0x00200000uL) -#define GPIO_PSR11_PSR1122 (0x00400000uL) -#define GPIO_PSR11_PSR1123 (0x00800000uL) -#define GPIO_PSR11_PSR1124 (0x01000000uL) -#define GPIO_PSR11_PSR1125 (0x02000000uL) -#define GPIO_PSR11_PSR1126 (0x04000000uL) -#define GPIO_PSR11_PSR1127 (0x08000000uL) -#define GPIO_PSR11_PSR1128 (0x10000000uL) -#define GPIO_PSR11_PSR1129 (0x20000000uL) -#define GPIO_PSR11_PSR1130 (0x40000000uL) -#define GPIO_PSR11_PSR1131 (0x80000000uL) - -#define GPIO_PPR11_PPR110 (0x0001u) -#define GPIO_PPR11_PPR111 (0x0002u) -#define GPIO_PPR11_PPR112 (0x0004u) -#define GPIO_PPR11_PPR113 (0x0008u) -#define GPIO_PPR11_PPR114 (0x0010u) -#define GPIO_PPR11_PPR115 (0x0020u) -#define GPIO_PPR11_PPR116 (0x0040u) -#define GPIO_PPR11_PPR117 (0x0080u) -#define GPIO_PPR11_PPR118 (0x0100u) -#define GPIO_PPR11_PPR119 (0x0200u) -#define GPIO_PPR11_PPR1110 (0x0400u) -#define GPIO_PPR11_PPR1111 (0x0800u) -#define GPIO_PPR11_PPR1112 (0x1000u) -#define GPIO_PPR11_PPR1113 (0x2000u) -#define GPIO_PPR11_PPR1114 (0x4000u) -#define GPIO_PPR11_PPR1115 (0x8000u) - -#define GPIO_PM11_PM110 (0x0001u) -#define GPIO_PM11_PM111 (0x0002u) -#define GPIO_PM11_PM112 (0x0004u) -#define GPIO_PM11_PM113 (0x0008u) -#define GPIO_PM11_PM114 (0x0010u) -#define GPIO_PM11_PM115 (0x0020u) -#define GPIO_PM11_PM116 (0x0040u) -#define GPIO_PM11_PM117 (0x0080u) -#define GPIO_PM11_PM118 (0x0100u) -#define GPIO_PM11_PM119 (0x0200u) -#define GPIO_PM11_PM1110 (0x0400u) -#define GPIO_PM11_PM1111 (0x0800u) -#define GPIO_PM11_PM1112 (0x1000u) -#define GPIO_PM11_PM1113 (0x2000u) -#define GPIO_PM11_PM1114 (0x4000u) -#define GPIO_PM11_PM1115 (0x8000u) - -#define GPIO_PMC11_PMC110 (0x0001u) -#define GPIO_PMC11_PMC111 (0x0002u) -#define GPIO_PMC11_PMC112 (0x0004u) -#define GPIO_PMC11_PMC113 (0x0008u) -#define GPIO_PMC11_PMC114 (0x0010u) -#define GPIO_PMC11_PMC115 (0x0020u) -#define GPIO_PMC11_PMC116 (0x0040u) -#define GPIO_PMC11_PMC117 (0x0080u) -#define GPIO_PMC11_PMC118 (0x0100u) -#define GPIO_PMC11_PMC119 (0x0200u) -#define GPIO_PMC11_PMC1110 (0x0400u) -#define GPIO_PMC11_PMC1111 (0x0800u) -#define GPIO_PMC11_PMC1112 (0x1000u) -#define GPIO_PMC11_PMC1113 (0x2000u) -#define GPIO_PMC11_PMC1114 (0x4000u) -#define GPIO_PMC11_PMC1115 (0x8000u) - -#define GPIO_PFC11_PFC110 (0x0001u) -#define GPIO_PFC11_PFC111 (0x0002u) -#define GPIO_PFC11_PFC112 (0x0004u) -#define GPIO_PFC11_PFC113 (0x0008u) -#define GPIO_PFC11_PFC114 (0x0010u) -#define GPIO_PFC11_PFC115 (0x0020u) -#define GPIO_PFC11_PFC116 (0x0040u) -#define GPIO_PFC11_PFC117 (0x0080u) -#define GPIO_PFC11_PFC118 (0x0100u) -#define GPIO_PFC11_PFC119 (0x0200u) -#define GPIO_PFC11_PFC1110 (0x0400u) -#define GPIO_PFC11_PFC1111 (0x0800u) -#define GPIO_PFC11_PFC1112 (0x1000u) -#define GPIO_PFC11_PFC1113 (0x2000u) -#define GPIO_PFC11_PFC1114 (0x4000u) -#define GPIO_PFC11_PFC1115 (0x8000u) - -#define GPIO_PFCE11_PFCE110 (0x0001u) -#define GPIO_PFCE11_PFCE111 (0x0002u) -#define GPIO_PFCE11_PFCE112 (0x0004u) -#define GPIO_PFCE11_PFCE113 (0x0008u) -#define GPIO_PFCE11_PFCE114 (0x0010u) -#define GPIO_PFCE11_PFCE115 (0x0020u) -#define GPIO_PFCE11_PFCE116 (0x0040u) -#define GPIO_PFCE11_PFCE117 (0x0080u) -#define GPIO_PFCE11_PFCE118 (0x0100u) -#define GPIO_PFCE11_PFCE119 (0x0200u) -#define GPIO_PFCE11_PFCE1110 (0x0400u) -#define GPIO_PFCE11_PFCE1111 (0x0800u) -#define GPIO_PFCE11_PFCE1112 (0x1000u) -#define GPIO_PFCE11_PFCE1113 (0x2000u) -#define GPIO_PFCE11_PFCE1114 (0x4000u) -#define GPIO_PFCE11_PFCE1115 (0x8000u) - -#define GPIO_PNOT11_PNOT110 (0x0001u) -#define GPIO_PNOT11_PNOT111 (0x0002u) -#define GPIO_PNOT11_PNOT112 (0x0004u) -#define GPIO_PNOT11_PNOT113 (0x0008u) -#define GPIO_PNOT11_PNOT114 (0x0010u) -#define GPIO_PNOT11_PNOT115 (0x0020u) -#define GPIO_PNOT11_PNOT116 (0x0040u) -#define GPIO_PNOT11_PNOT117 (0x0080u) -#define GPIO_PNOT11_PNOT118 (0x0100u) -#define GPIO_PNOT11_PNOT119 (0x0200u) -#define GPIO_PNOT11_PNOT1110 (0x0400u) -#define GPIO_PNOT11_PNOT1111 (0x0800u) -#define GPIO_PNOT11_PNOT1112 (0x1000u) -#define GPIO_PNOT11_PNOT1113 (0x2000u) -#define GPIO_PNOT11_PNOT1114 (0x4000u) -#define GPIO_PNOT11_PNOT1115 (0x8000u) - -#define GPIO_PMSR11_PMSR110 (0x00000001uL) -#define GPIO_PMSR11_PMSR111 (0x00000002uL) -#define GPIO_PMSR11_PMSR112 (0x00000004uL) -#define GPIO_PMSR11_PMSR113 (0x00000008uL) -#define GPIO_PMSR11_PMSR114 (0x00000010uL) -#define GPIO_PMSR11_PMSR115 (0x00000020uL) -#define GPIO_PMSR11_PMSR116 (0x00000040uL) -#define GPIO_PMSR11_PMSR117 (0x00000080uL) -#define GPIO_PMSR11_PMSR118 (0x00000100uL) -#define GPIO_PMSR11_PMSR119 (0x00000200uL) -#define GPIO_PMSR11_PMSR1110 (0x00000400uL) -#define GPIO_PMSR11_PMSR1111 (0x00000800uL) -#define GPIO_PMSR11_PMSR1112 (0x00001000uL) -#define GPIO_PMSR11_PMSR1113 (0x00002000uL) -#define GPIO_PMSR11_PMSR1114 (0x00004000uL) -#define GPIO_PMSR11_PMSR1115 (0x00008000uL) -#define GPIO_PMSR11_PMSR1116 (0x00010000uL) -#define GPIO_PMSR11_PMSR1117 (0x00020000uL) -#define GPIO_PMSR11_PMSR1118 (0x00040000uL) -#define GPIO_PMSR11_PMSR1119 (0x00080000uL) -#define GPIO_PMSR11_PMSR1120 (0x00100000uL) -#define GPIO_PMSR11_PMSR1121 (0x00200000uL) -#define GPIO_PMSR11_PMSR1122 (0x00400000uL) -#define GPIO_PMSR11_PMSR1123 (0x00800000uL) -#define GPIO_PMSR11_PMSR1124 (0x01000000uL) -#define GPIO_PMSR11_PMSR1125 (0x02000000uL) -#define GPIO_PMSR11_PMSR1126 (0x04000000uL) -#define GPIO_PMSR11_PMSR1127 (0x08000000uL) -#define GPIO_PMSR11_PMSR1128 (0x10000000uL) -#define GPIO_PMSR11_PMSR1129 (0x20000000uL) -#define GPIO_PMSR11_PMSR1130 (0x40000000uL) -#define GPIO_PMSR11_PMSR1131 (0x80000000uL) - -#define GPIO_PMCSR11_PMCSR110 (0x00000001uL) -#define GPIO_PMCSR11_PMCSR111 (0x00000002uL) -#define GPIO_PMCSR11_PMCSR112 (0x00000004uL) -#define GPIO_PMCSR11_PMCSR113 (0x00000008uL) -#define GPIO_PMCSR11_PMCSR114 (0x00000010uL) -#define GPIO_PMCSR11_PMCSR115 (0x00000020uL) -#define GPIO_PMCSR11_PMCSR116 (0x00000040uL) -#define GPIO_PMCSR11_PMCSR117 (0x00000080uL) -#define GPIO_PMCSR11_PMCSR118 (0x00000100uL) -#define GPIO_PMCSR11_PMCSR119 (0x00000200uL) -#define GPIO_PMCSR11_PMCSR1110 (0x00000400uL) -#define GPIO_PMCSR11_PMCSR1111 (0x00000800uL) -#define GPIO_PMCSR11_PMCSR1112 (0x00001000uL) -#define GPIO_PMCSR11_PMCSR1113 (0x00002000uL) -#define GPIO_PMCSR11_PMCSR1114 (0x00004000uL) -#define GPIO_PMCSR11_PMCSR1115 (0x00008000uL) -#define GPIO_PMCSR11_PMCSR1116 (0x00010000uL) -#define GPIO_PMCSR11_PMCSR1117 (0x00020000uL) -#define GPIO_PMCSR11_PMCSR1118 (0x00040000uL) -#define GPIO_PMCSR11_PMCSR1119 (0x00080000uL) -#define GPIO_PMCSR11_PMCSR1120 (0x00100000uL) -#define GPIO_PMCSR11_PMCSR1121 (0x00200000uL) -#define GPIO_PMCSR11_PMCSR1122 (0x00400000uL) -#define GPIO_PMCSR11_PMCSR1123 (0x00800000uL) -#define GPIO_PMCSR11_PMCSR1124 (0x01000000uL) -#define GPIO_PMCSR11_PMCSR1125 (0x02000000uL) -#define GPIO_PMCSR11_PMCSR1126 (0x04000000uL) -#define GPIO_PMCSR11_PMCSR1127 (0x08000000uL) -#define GPIO_PMCSR11_PMCSR1128 (0x10000000uL) -#define GPIO_PMCSR11_PMCSR1129 (0x20000000uL) -#define GPIO_PMCSR11_PMCSR1130 (0x40000000uL) -#define GPIO_PMCSR11_PMCSR1131 (0x80000000uL) - -#define GPIO_PFCAE11_PFCAE110 (0x0001u) -#define GPIO_PFCAE11_PFCAE111 (0x0002u) -#define GPIO_PFCAE11_PFCAE112 (0x0004u) -#define GPIO_PFCAE11_PFCAE113 (0x0008u) -#define GPIO_PFCAE11_PFCAE114 (0x0010u) -#define GPIO_PFCAE11_PFCAE115 (0x0020u) -#define GPIO_PFCAE11_PFCAE116 (0x0040u) -#define GPIO_PFCAE11_PFCAE117 (0x0080u) -#define GPIO_PFCAE11_PFCAE118 (0x0100u) -#define GPIO_PFCAE11_PFCAE119 (0x0200u) -#define GPIO_PFCAE11_PFCAE1110 (0x0400u) -#define GPIO_PFCAE11_PFCAE1111 (0x0800u) -#define GPIO_PFCAE11_PFCAE1112 (0x1000u) -#define GPIO_PFCAE11_PFCAE1113 (0x2000u) -#define GPIO_PFCAE11_PFCAE1114 (0x4000u) -#define GPIO_PFCAE11_PFCAE1115 (0x8000u) - -#define GPIO_PIBC11_PIBC110 (0x0001u) -#define GPIO_PIBC11_PIBC111 (0x0002u) -#define GPIO_PIBC11_PIBC112 (0x0004u) -#define GPIO_PIBC11_PIBC113 (0x0008u) -#define GPIO_PIBC11_PIBC114 (0x0010u) -#define GPIO_PIBC11_PIBC115 (0x0020u) -#define GPIO_PIBC11_PIBC116 (0x0040u) -#define GPIO_PIBC11_PIBC117 (0x0080u) -#define GPIO_PIBC11_PIBC118 (0x0100u) -#define GPIO_PIBC11_PIBC119 (0x0200u) -#define GPIO_PIBC11_PIBC1110 (0x0400u) -#define GPIO_PIBC11_PIBC1111 (0x0800u) -#define GPIO_PIBC11_PIBC1112 (0x1000u) -#define GPIO_PIBC11_PIBC1113 (0x2000u) -#define GPIO_PIBC11_PIBC1114 (0x4000u) -#define GPIO_PIBC11_PIBC1115 (0x8000u) - -#define GPIO_PBDC11_PBDC110 (0x0001u) -#define GPIO_PBDC11_PBDC111 (0x0002u) -#define GPIO_PBDC11_PBDC112 (0x0004u) -#define GPIO_PBDC11_PBDC113 (0x0008u) -#define GPIO_PBDC11_PBDC114 (0x0010u) -#define GPIO_PBDC11_PBDC115 (0x0020u) -#define GPIO_PBDC11_PBDC116 (0x0040u) -#define GPIO_PBDC11_PBDC117 (0x0080u) -#define GPIO_PBDC11_PBDC118 (0x0100u) -#define GPIO_PBDC11_PBDC119 (0x0200u) -#define GPIO_PBDC11_PBDC1110 (0x0400u) -#define GPIO_PBDC11_PBDC1111 (0x0800u) -#define GPIO_PBDC11_PBDC1112 (0x1000u) -#define GPIO_PBDC11_PBDC1113 (0x2000u) -#define GPIO_PBDC11_PBDC1114 (0x4000u) -#define GPIO_PBDC11_PBDC1115 (0x8000u) - -#define GPIO_PIPC11_PIPC110 (0x0001u) -#define GPIO_PIPC11_PIPC111 (0x0002u) -#define GPIO_PIPC11_PIPC112 (0x0004u) -#define GPIO_PIPC11_PIPC113 (0x0008u) -#define GPIO_PIPC11_PIPC114 (0x0010u) -#define GPIO_PIPC11_PIPC115 (0x0020u) -#define GPIO_PIPC11_PIPC116 (0x0040u) -#define GPIO_PIPC11_PIPC117 (0x0080u) -#define GPIO_PIPC11_PIPC118 (0x0100u) -#define GPIO_PIPC11_PIPC119 (0x0200u) -#define GPIO_PIPC11_PIPC1110 (0x0400u) -#define GPIO_PIPC11_PIPC1111 (0x0800u) -#define GPIO_PIPC11_PIPC1112 (0x1000u) -#define GPIO_PIPC11_PIPC1113 (0x2000u) -#define GPIO_PIPC11_PIPC1114 (0x4000u) -#define GPIO_PIPC11_PIPC1115 (0x8000u) - - -/* ==== Shift values for IO registers ==== */ -/* ---- P0 ---- */ -#define GPIO_PPR0_PPR00_SHIFT (0u) -#define GPIO_PPR0_PPR01_SHIFT (1u) -#define GPIO_PPR0_PPR02_SHIFT (2u) -#define GPIO_PPR0_PPR03_SHIFT (3u) -#define GPIO_PPR0_PPR04_SHIFT (4u) -#define GPIO_PPR0_PPR05_SHIFT (5u) - -#define GPIO_PMC0_PMC04_SHIFT (4u) -#define GPIO_PMC0_PMC05_SHIFT (5u) - -#define GPIO_PMCSR0_PMCSR04_SHIFT (4u) -#define GPIO_PMCSR0_PMCSR05_SHIFT (5u) - -#define GPIO_PIBC0_PIBC00_SHIFT (0u) -#define GPIO_PIBC0_PIBC01_SHIFT (1u) -#define GPIO_PIBC0_PIBC02_SHIFT (2u) -#define GPIO_PIBC0_PIBC03_SHIFT (3u) -#define GPIO_PIBC0_PIBC04_SHIFT (4u) -#define GPIO_PIBC0_PIBC05_SHIFT (5u) - -/* ---- P1 ---- */ -#define GPIO_P1_P10_SHIFT (0u) -#define GPIO_P1_P11_SHIFT (1u) -#define GPIO_P1_P12_SHIFT (2u) -#define GPIO_P1_P13_SHIFT (3u) -#define GPIO_P1_P14_SHIFT (4u) -#define GPIO_P1_P15_SHIFT (5u) -#define GPIO_P1_P16_SHIFT (6u) -#define GPIO_P1_P17_SHIFT (7u) - -#define GPIO_PSR1_PSR10_SHIFT (0u) -#define GPIO_PSR1_PSR11_SHIFT (1u) -#define GPIO_PSR1_PSR12_SHIFT (2u) -#define GPIO_PSR1_PSR13_SHIFT (3u) -#define GPIO_PSR1_PSR14_SHIFT (4u) -#define GPIO_PSR1_PSR15_SHIFT (5u) -#define GPIO_PSR1_PSR16_SHIFT (6u) -#define GPIO_PSR1_PSR17_SHIFT (7u) -#define GPIO_PSR1_PSR116_SHIFT (16u) -#define GPIO_PSR1_PSR117_SHIFT (17u) -#define GPIO_PSR1_PSR118_SHIFT (18u) -#define GPIO_PSR1_PSR119_SHIFT (19u) -#define GPIO_PSR1_PSR120_SHIFT (20u) -#define GPIO_PSR1_PSR121_SHIFT (21u) -#define GPIO_PSR1_PSR122_SHIFT (22u) -#define GPIO_PSR1_PSR123_SHIFT (23u) - -#define GPIO_PPR1_PPR10_SHIFT (0u) -#define GPIO_PPR1_PPR11_SHIFT (1u) -#define GPIO_PPR1_PPR12_SHIFT (2u) -#define GPIO_PPR1_PPR13_SHIFT (3u) -#define GPIO_PPR1_PPR14_SHIFT (4u) -#define GPIO_PPR1_PPR15_SHIFT (5u) -#define GPIO_PPR1_PPR16_SHIFT (6u) -#define GPIO_PPR1_PPR17_SHIFT (7u) -#define GPIO_PPR1_PPR18_SHIFT (8u) -#define GPIO_PPR1_PPR19_SHIFT (9u) -#define GPIO_PPR1_PPR110_SHIFT (10u) -#define GPIO_PPR1_PPR111_SHIFT (11u) -#define GPIO_PPR1_PPR112_SHIFT (12u) -#define GPIO_PPR1_PPR113_SHIFT (13u) -#define GPIO_PPR1_PPR114_SHIFT (14u) -#define GPIO_PPR1_PPR115_SHIFT (15u) - -#define GPIO_PM1_PM10_SHIFT (0u) -#define GPIO_PM1_PM11_SHIFT (1u) -#define GPIO_PM1_PM12_SHIFT (2u) -#define GPIO_PM1_PM13_SHIFT (3u) -#define GPIO_PM1_PM14_SHIFT (4u) -#define GPIO_PM1_PM15_SHIFT (5u) -#define GPIO_PM1_PM16_SHIFT (6u) -#define GPIO_PM1_PM17_SHIFT (7u) - -#define GPIO_PMC1_PMC10_SHIFT (0u) -#define GPIO_PMC1_PMC11_SHIFT (1u) -#define GPIO_PMC1_PMC12_SHIFT (2u) -#define GPIO_PMC1_PMC13_SHIFT (3u) -#define GPIO_PMC1_PMC14_SHIFT (4u) -#define GPIO_PMC1_PMC15_SHIFT (5u) -#define GPIO_PMC1_PMC16_SHIFT (6u) -#define GPIO_PMC1_PMC17_SHIFT (7u) -#define GPIO_PMC1_PMC18_SHIFT (8u) -#define GPIO_PMC1_PMC19_SHIFT (9u) -#define GPIO_PMC1_PMC110_SHIFT (10u) -#define GPIO_PMC1_PMC111_SHIFT (11u) -#define GPIO_PMC1_PMC112_SHIFT (12u) -#define GPIO_PMC1_PMC113_SHIFT (13u) -#define GPIO_PMC1_PMC114_SHIFT (14u) -#define GPIO_PMC1_PMC115_SHIFT (15u) - -#define GPIO_PFC1_PFC10_SHIFT (0u) -#define GPIO_PFC1_PFC11_SHIFT (1u) -#define GPIO_PFC1_PFC12_SHIFT (2u) -#define GPIO_PFC1_PFC13_SHIFT (3u) -#define GPIO_PFC1_PFC14_SHIFT (4u) -#define GPIO_PFC1_PFC15_SHIFT (5u) -#define GPIO_PFC1_PFC16_SHIFT (6u) -#define GPIO_PFC1_PFC17_SHIFT (7u) -#define GPIO_PFC1_PFC18_SHIFT (8u) -#define GPIO_PFC1_PFC19_SHIFT (9u) -#define GPIO_PFC1_PFC110_SHIFT (10u) -#define GPIO_PFC1_PFC111_SHIFT (11u) -#define GPIO_PFC1_PFC112_SHIFT (12u) -#define GPIO_PFC1_PFC113_SHIFT (13u) -#define GPIO_PFC1_PFC114_SHIFT (14u) -#define GPIO_PFC1_PFC115_SHIFT (15u) - -#define GPIO_PFCE1_PFCE10_SHIFT (0u) -#define GPIO_PFCE1_PFCE11_SHIFT (1u) -#define GPIO_PFCE1_PFCE12_SHIFT (2u) -#define GPIO_PFCE1_PFCE13_SHIFT (3u) -#define GPIO_PFCE1_PFCE14_SHIFT (4u) -#define GPIO_PFCE1_PFCE15_SHIFT (5u) -#define GPIO_PFCE1_PFCE16_SHIFT (6u) -#define GPIO_PFCE1_PFCE17_SHIFT (7u) -#define GPIO_PFCE1_PFCE18_SHIFT (8u) -#define GPIO_PFCE1_PFCE19_SHIFT (9u) -#define GPIO_PFCE1_PFCE110_SHIFT (10u) -#define GPIO_PFCE1_PFCE111_SHIFT (11u) -#define GPIO_PFCE1_PFCE112_SHIFT (12u) -#define GPIO_PFCE1_PFCE113_SHIFT (13u) -#define GPIO_PFCE1_PFCE114_SHIFT (14u) -#define GPIO_PFCE1_PFCE115_SHIFT (15u) - -#define GPIO_PNOT1_PNOT10_SHIFT (0u) -#define GPIO_PNOT1_PNOT11_SHIFT (1u) -#define GPIO_PNOT1_PNOT12_SHIFT (2u) -#define GPIO_PNOT1_PNOT13_SHIFT (3u) -#define GPIO_PNOT1_PNOT14_SHIFT (4u) -#define GPIO_PNOT1_PNOT15_SHIFT (5u) -#define GPIO_PNOT1_PNOT16_SHIFT (6u) -#define GPIO_PNOT1_PNOT17_SHIFT (7u) - -#define GPIO_PMSR1_PMSR10_SHIFT (0u) -#define GPIO_PMSR1_PMSR11_SHIFT (1u) -#define GPIO_PMSR1_PMSR12_SHIFT (2u) -#define GPIO_PMSR1_PMSR13_SHIFT (3u) -#define GPIO_PMSR1_PMSR14_SHIFT (4u) -#define GPIO_PMSR1_PMSR15_SHIFT (5u) -#define GPIO_PMSR1_PMSR16_SHIFT (6u) -#define GPIO_PMSR1_PMSR17_SHIFT (7u) -#define GPIO_PMSR1_PMSR116_SHIFT (16u) -#define GPIO_PMSR1_PMSR117_SHIFT (17u) -#define GPIO_PMSR1_PMSR118_SHIFT (18u) -#define GPIO_PMSR1_PMSR119_SHIFT (19u) -#define GPIO_PMSR1_PMSR120_SHIFT (20u) -#define GPIO_PMSR1_PMSR121_SHIFT (21u) -#define GPIO_PMSR1_PMSR122_SHIFT (22u) -#define GPIO_PMSR1_PMSR123_SHIFT (23u) - -#define GPIO_PMCSR1_PMCSR10_SHIFT (0u) -#define GPIO_PMCSR1_PMCSR11_SHIFT (1u) -#define GPIO_PMCSR1_PMCSR12_SHIFT (2u) -#define GPIO_PMCSR1_PMCSR13_SHIFT (3u) -#define GPIO_PMCSR1_PMCSR14_SHIFT (4u) -#define GPIO_PMCSR1_PMCSR15_SHIFT (5u) -#define GPIO_PMCSR1_PMCSR16_SHIFT (6u) -#define GPIO_PMCSR1_PMCSR17_SHIFT (7u) -#define GPIO_PMCSR1_PMCSR116_SHIFT (16u) -#define GPIO_PMCSR1_PMCSR117_SHIFT (17u) -#define GPIO_PMCSR1_PMCSR118_SHIFT (18u) -#define GPIO_PMCSR1_PMCSR119_SHIFT (19u) -#define GPIO_PMCSR1_PMCSR120_SHIFT (20u) -#define GPIO_PMCSR1_PMCSR121_SHIFT (21u) -#define GPIO_PMCSR1_PMCSR122_SHIFT (22u) -#define GPIO_PMCSR1_PMCSR123_SHIFT (23u) - -#define GPIO_PFCAE1_PFCAE10_SHIFT (0u) -#define GPIO_PFCAE1_PFCAE11_SHIFT (1u) -#define GPIO_PFCAE1_PFCAE12_SHIFT (2u) -#define GPIO_PFCAE1_PFCAE13_SHIFT (3u) -#define GPIO_PFCAE1_PFCAE14_SHIFT (4u) -#define GPIO_PFCAE1_PFCAE15_SHIFT (5u) -#define GPIO_PFCAE1_PFCAE16_SHIFT (6u) -#define GPIO_PFCAE1_PFCAE17_SHIFT (7u) -#define GPIO_PFCAE1_PFCAE18_SHIFT (8u) -#define GPIO_PFCAE1_PFCAE19_SHIFT (9u) -#define GPIO_PFCAE1_PFCAE110_SHIFT (10u) -#define GPIO_PFCAE1_PFCAE111_SHIFT (11u) -#define GPIO_PFCAE1_PFCAE112_SHIFT (12u) -#define GPIO_PFCAE1_PFCAE113_SHIFT (13u) -#define GPIO_PFCAE1_PFCAE114_SHIFT (14u) -#define GPIO_PFCAE1_PFCAE115_SHIFT (15u) - -#define GPIO_PIBC1_PIBC10_SHIFT (0u) -#define GPIO_PIBC1_PIBC11_SHIFT (1u) -#define GPIO_PIBC1_PIBC12_SHIFT (2u) -#define GPIO_PIBC1_PIBC13_SHIFT (3u) -#define GPIO_PIBC1_PIBC14_SHIFT (4u) -#define GPIO_PIBC1_PIBC15_SHIFT (5u) -#define GPIO_PIBC1_PIBC16_SHIFT (6u) -#define GPIO_PIBC1_PIBC17_SHIFT (7u) -#define GPIO_PIBC1_PIBC18_SHIFT (8u) -#define GPIO_PIBC1_PIBC19_SHIFT (9u) -#define GPIO_PIBC1_PIBC110_SHIFT (10u) -#define GPIO_PIBC1_PIBC111_SHIFT (11u) -#define GPIO_PIBC1_PIBC112_SHIFT (12u) -#define GPIO_PIBC1_PIBC113_SHIFT (13u) -#define GPIO_PIBC1_PIBC114_SHIFT (14u) -#define GPIO_PIBC1_PIBC115_SHIFT (15u) - -#define GPIO_PBDC1_PBDC10_SHIFT (0u) -#define GPIO_PBDC1_PBDC11_SHIFT (1u) -#define GPIO_PBDC1_PBDC12_SHIFT (2u) -#define GPIO_PBDC1_PBDC13_SHIFT (3u) -#define GPIO_PBDC1_PBDC14_SHIFT (4u) -#define GPIO_PBDC1_PBDC15_SHIFT (5u) -#define GPIO_PBDC1_PBDC16_SHIFT (6u) -#define GPIO_PBDC1_PBDC17_SHIFT (7u) -#define GPIO_PBDC1_PBDC18_SHIFT (8u) -#define GPIO_PBDC1_PBDC19_SHIFT (9u) -#define GPIO_PBDC1_PBDC110_SHIFT (10u) -#define GPIO_PBDC1_PBDC111_SHIFT (11u) -#define GPIO_PBDC1_PBDC112_SHIFT (12u) -#define GPIO_PBDC1_PBDC113_SHIFT (13u) -#define GPIO_PBDC1_PBDC114_SHIFT (14u) -#define GPIO_PBDC1_PBDC115_SHIFT (15u) - -#define GPIO_PIPC1_PIPC10_SHIFT (0u) -#define GPIO_PIPC1_PIPC11_SHIFT (1u) -#define GPIO_PIPC1_PIPC12_SHIFT (2u) -#define GPIO_PIPC1_PIPC13_SHIFT (3u) -#define GPIO_PIPC1_PIPC14_SHIFT (4u) -#define GPIO_PIPC1_PIPC15_SHIFT (5u) -#define GPIO_PIPC1_PIPC16_SHIFT (6u) -#define GPIO_PIPC1_PIPC17_SHIFT (7u) - -/* ---- P2 ---- */ -#define GPIO_P2_P20_SHIFT (0u) -#define GPIO_P2_P21_SHIFT (1u) -#define GPIO_P2_P22_SHIFT (2u) -#define GPIO_P2_P23_SHIFT (3u) -#define GPIO_P2_P24_SHIFT (4u) -#define GPIO_P2_P25_SHIFT (5u) -#define GPIO_P2_P26_SHIFT (6u) -#define GPIO_P2_P27_SHIFT (7u) -#define GPIO_P2_P28_SHIFT (8u) -#define GPIO_P2_P29_SHIFT (9u) -#define GPIO_P2_P210_SHIFT (10u) -#define GPIO_P2_P211_SHIFT (11u) -#define GPIO_P2_P212_SHIFT (12u) -#define GPIO_P2_P213_SHIFT (13u) -#define GPIO_P2_P214_SHIFT (14u) -#define GPIO_P2_P215_SHIFT (15u) - -#define GPIO_PSR2_PSR20_SHIFT (0u) -#define GPIO_PSR2_PSR21_SHIFT (1u) -#define GPIO_PSR2_PSR22_SHIFT (2u) -#define GPIO_PSR2_PSR23_SHIFT (3u) -#define GPIO_PSR2_PSR24_SHIFT (4u) -#define GPIO_PSR2_PSR25_SHIFT (5u) -#define GPIO_PSR2_PSR26_SHIFT (6u) -#define GPIO_PSR2_PSR27_SHIFT (7u) -#define GPIO_PSR2_PSR28_SHIFT (8u) -#define GPIO_PSR2_PSR29_SHIFT (9u) -#define GPIO_PSR2_PSR210_SHIFT (10u) -#define GPIO_PSR2_PSR211_SHIFT (11u) -#define GPIO_PSR2_PSR212_SHIFT (12u) -#define GPIO_PSR2_PSR213_SHIFT (13u) -#define GPIO_PSR2_PSR214_SHIFT (14u) -#define GPIO_PSR2_PSR215_SHIFT (15u) -#define GPIO_PSR2_PSR216_SHIFT (16u) -#define GPIO_PSR2_PSR217_SHIFT (17u) -#define GPIO_PSR2_PSR218_SHIFT (18u) -#define GPIO_PSR2_PSR219_SHIFT (19u) -#define GPIO_PSR2_PSR220_SHIFT (20u) -#define GPIO_PSR2_PSR221_SHIFT (21u) -#define GPIO_PSR2_PSR222_SHIFT (22u) -#define GPIO_PSR2_PSR223_SHIFT (23u) -#define GPIO_PSR2_PSR224_SHIFT (24u) -#define GPIO_PSR2_PSR225_SHIFT (25u) -#define GPIO_PSR2_PSR226_SHIFT (26u) -#define GPIO_PSR2_PSR227_SHIFT (27u) -#define GPIO_PSR2_PSR228_SHIFT (28u) -#define GPIO_PSR2_PSR229_SHIFT (29u) -#define GPIO_PSR2_PSR230_SHIFT (30u) -#define GPIO_PSR2_PSR231_SHIFT (31u) - -#define GPIO_PPR2_PPR20_SHIFT (0u) -#define GPIO_PPR2_PPR21_SHIFT (1u) -#define GPIO_PPR2_PPR22_SHIFT (2u) -#define GPIO_PPR2_PPR23_SHIFT (3u) -#define GPIO_PPR2_PPR24_SHIFT (4u) -#define GPIO_PPR2_PPR25_SHIFT (5u) -#define GPIO_PPR2_PPR26_SHIFT (6u) -#define GPIO_PPR2_PPR27_SHIFT (7u) -#define GPIO_PPR2_PPR28_SHIFT (8u) -#define GPIO_PPR2_PPR29_SHIFT (9u) -#define GPIO_PPR2_PPR210_SHIFT (10u) -#define GPIO_PPR2_PPR211_SHIFT (11u) -#define GPIO_PPR2_PPR212_SHIFT (12u) -#define GPIO_PPR2_PPR213_SHIFT (13u) -#define GPIO_PPR2_PPR214_SHIFT (14u) -#define GPIO_PPR2_PPR215_SHIFT (15u) - -#define GPIO_PM2_PM20_SHIFT (0u) -#define GPIO_PM2_PM21_SHIFT (1u) -#define GPIO_PM2_PM22_SHIFT (2u) -#define GPIO_PM2_PM23_SHIFT (3u) -#define GPIO_PM2_PM24_SHIFT (4u) -#define GPIO_PM2_PM25_SHIFT (5u) -#define GPIO_PM2_PM26_SHIFT (6u) -#define GPIO_PM2_PM27_SHIFT (7u) -#define GPIO_PM2_PM28_SHIFT (8u) -#define GPIO_PM2_PM29_SHIFT (9u) -#define GPIO_PM2_PM210_SHIFT (10u) -#define GPIO_PM2_PM211_SHIFT (11u) -#define GPIO_PM2_PM212_SHIFT (12u) -#define GPIO_PM2_PM213_SHIFT (13u) -#define GPIO_PM2_PM214_SHIFT (14u) -#define GPIO_PM2_PM215_SHIFT (15u) - -#define GPIO_PMC2_PMC20_SHIFT (0u) -#define GPIO_PMC2_PMC21_SHIFT (1u) -#define GPIO_PMC2_PMC22_SHIFT (2u) -#define GPIO_PMC2_PMC23_SHIFT (3u) -#define GPIO_PMC2_PMC24_SHIFT (4u) -#define GPIO_PMC2_PMC25_SHIFT (5u) -#define GPIO_PMC2_PMC26_SHIFT (6u) -#define GPIO_PMC2_PMC27_SHIFT (7u) -#define GPIO_PMC2_PMC28_SHIFT (8u) -#define GPIO_PMC2_PMC29_SHIFT (9u) -#define GPIO_PMC2_PMC210_SHIFT (10u) -#define GPIO_PMC2_PMC211_SHIFT (11u) -#define GPIO_PMC2_PMC212_SHIFT (12u) -#define GPIO_PMC2_PMC213_SHIFT (13u) -#define GPIO_PMC2_PMC214_SHIFT (14u) -#define GPIO_PMC2_PMC215_SHIFT (15u) - -#define GPIO_PFC2_PFC20_SHIFT (0u) -#define GPIO_PFC2_PFC21_SHIFT (1u) -#define GPIO_PFC2_PFC22_SHIFT (2u) -#define GPIO_PFC2_PFC23_SHIFT (3u) -#define GPIO_PFC2_PFC24_SHIFT (4u) -#define GPIO_PFC2_PFC25_SHIFT (5u) -#define GPIO_PFC2_PFC26_SHIFT (6u) -#define GPIO_PFC2_PFC27_SHIFT (7u) -#define GPIO_PFC2_PFC28_SHIFT (8u) -#define GPIO_PFC2_PFC29_SHIFT (9u) -#define GPIO_PFC2_PFC210_SHIFT (10u) -#define GPIO_PFC2_PFC211_SHIFT (11u) -#define GPIO_PFC2_PFC212_SHIFT (12u) -#define GPIO_PFC2_PFC213_SHIFT (13u) -#define GPIO_PFC2_PFC214_SHIFT (14u) -#define GPIO_PFC2_PFC215_SHIFT (15u) - -#define GPIO_PFCE2_PFCE20_SHIFT (0u) -#define GPIO_PFCE2_PFCE21_SHIFT (1u) -#define GPIO_PFCE2_PFCE22_SHIFT (2u) -#define GPIO_PFCE2_PFCE23_SHIFT (3u) -#define GPIO_PFCE2_PFCE24_SHIFT (4u) -#define GPIO_PFCE2_PFCE25_SHIFT (5u) -#define GPIO_PFCE2_PFCE26_SHIFT (6u) -#define GPIO_PFCE2_PFCE27_SHIFT (7u) -#define GPIO_PFCE2_PFCE28_SHIFT (8u) -#define GPIO_PFCE2_PFCE29_SHIFT (9u) -#define GPIO_PFCE2_PFCE210_SHIFT (10u) -#define GPIO_PFCE2_PFCE211_SHIFT (11u) -#define GPIO_PFCE2_PFCE212_SHIFT (12u) -#define GPIO_PFCE2_PFCE213_SHIFT (13u) -#define GPIO_PFCE2_PFCE214_SHIFT (14u) -#define GPIO_PFCE2_PFCE215_SHIFT (15u) - -#define GPIO_PNOT2_PNOT20_SHIFT (0u) -#define GPIO_PNOT2_PNOT21_SHIFT (1u) -#define GPIO_PNOT2_PNOT22_SHIFT (2u) -#define GPIO_PNOT2_PNOT23_SHIFT (3u) -#define GPIO_PNOT2_PNOT24_SHIFT (4u) -#define GPIO_PNOT2_PNOT25_SHIFT (5u) -#define GPIO_PNOT2_PNOT26_SHIFT (6u) -#define GPIO_PNOT2_PNOT27_SHIFT (7u) -#define GPIO_PNOT2_PNOT28_SHIFT (8u) -#define GPIO_PNOT2_PNOT29_SHIFT (9u) -#define GPIO_PNOT2_PNOT210_SHIFT (10u) -#define GPIO_PNOT2_PNOT211_SHIFT (11u) -#define GPIO_PNOT2_PNOT212_SHIFT (12u) -#define GPIO_PNOT2_PNOT213_SHIFT (13u) -#define GPIO_PNOT2_PNOT214_SHIFT (14u) -#define GPIO_PNOT2_PNOT215_SHIFT (15u) - -#define GPIO_PMSR2_PMSR20_SHIFT (0u) -#define GPIO_PMSR2_PMSR21_SHIFT (1u) -#define GPIO_PMSR2_PMSR22_SHIFT (2u) -#define GPIO_PMSR2_PMSR23_SHIFT (3u) -#define GPIO_PMSR2_PMSR24_SHIFT (4u) -#define GPIO_PMSR2_PMSR25_SHIFT (5u) -#define GPIO_PMSR2_PMSR26_SHIFT (6u) -#define GPIO_PMSR2_PMSR27_SHIFT (7u) -#define GPIO_PMSR2_PMSR28_SHIFT (8u) -#define GPIO_PMSR2_PMSR29_SHIFT (9u) -#define GPIO_PMSR2_PMSR210_SHIFT (10u) -#define GPIO_PMSR2_PMSR211_SHIFT (11u) -#define GPIO_PMSR2_PMSR212_SHIFT (12u) -#define GPIO_PMSR2_PMSR213_SHIFT (13u) -#define GPIO_PMSR2_PMSR214_SHIFT (14u) -#define GPIO_PMSR2_PMSR215_SHIFT (15u) -#define GPIO_PMSR2_PMSR216_SHIFT (16u) -#define GPIO_PMSR2_PMSR217_SHIFT (17u) -#define GPIO_PMSR2_PMSR218_SHIFT (18u) -#define GPIO_PMSR2_PMSR219_SHIFT (19u) -#define GPIO_PMSR2_PMSR220_SHIFT (20u) -#define GPIO_PMSR2_PMSR221_SHIFT (21u) -#define GPIO_PMSR2_PMSR222_SHIFT (22u) -#define GPIO_PMSR2_PMSR223_SHIFT (23u) -#define GPIO_PMSR2_PMSR224_SHIFT (24u) -#define GPIO_PMSR2_PMSR225_SHIFT (25u) -#define GPIO_PMSR2_PMSR226_SHIFT (26u) -#define GPIO_PMSR2_PMSR227_SHIFT (27u) -#define GPIO_PMSR2_PMSR228_SHIFT (28u) -#define GPIO_PMSR2_PMSR229_SHIFT (29u) -#define GPIO_PMSR2_PMSR230_SHIFT (30u) -#define GPIO_PMSR2_PMSR231_SHIFT (31u) - -#define GPIO_PMCSR2_PMCSR20_SHIFT (0u) -#define GPIO_PMCSR2_PMCSR21_SHIFT (1u) -#define GPIO_PMCSR2_PMCSR22_SHIFT (2u) -#define GPIO_PMCSR2_PMCSR23_SHIFT (3u) -#define GPIO_PMCSR2_PMCSR24_SHIFT (4u) -#define GPIO_PMCSR2_PMCSR25_SHIFT (5u) -#define GPIO_PMCSR2_PMCSR26_SHIFT (6u) -#define GPIO_PMCSR2_PMCSR27_SHIFT (7u) -#define GPIO_PMCSR2_PMCSR28_SHIFT (8u) -#define GPIO_PMCSR2_PMCSR29_SHIFT (9u) -#define GPIO_PMCSR2_PMCSR210_SHIFT (10u) -#define GPIO_PMCSR2_PMCSR211_SHIFT (11u) -#define GPIO_PMCSR2_PMCSR212_SHIFT (12u) -#define GPIO_PMCSR2_PMCSR213_SHIFT (13u) -#define GPIO_PMCSR2_PMCSR214_SHIFT (14u) -#define GPIO_PMCSR2_PMCSR215_SHIFT (15u) -#define GPIO_PMCSR2_PMCSR216_SHIFT (16u) -#define GPIO_PMCSR2_PMCSR217_SHIFT (17u) -#define GPIO_PMCSR2_PMCSR218_SHIFT (18u) -#define GPIO_PMCSR2_PMCSR219_SHIFT (19u) -#define GPIO_PMCSR2_PMCSR220_SHIFT (20u) -#define GPIO_PMCSR2_PMCSR221_SHIFT (21u) -#define GPIO_PMCSR2_PMCSR222_SHIFT (22u) -#define GPIO_PMCSR2_PMCSR223_SHIFT (23u) -#define GPIO_PMCSR2_PMCSR224_SHIFT (24u) -#define GPIO_PMCSR2_PMCSR225_SHIFT (25u) -#define GPIO_PMCSR2_PMCSR226_SHIFT (26u) -#define GPIO_PMCSR2_PMCSR227_SHIFT (27u) -#define GPIO_PMCSR2_PMCSR228_SHIFT (28u) -#define GPIO_PMCSR2_PMCSR229_SHIFT (29u) -#define GPIO_PMCSR2_PMCSR230_SHIFT (30u) -#define GPIO_PMCSR2_PMCSR231_SHIFT (31u) - -#define GPIO_PFCAE2_PFCAE20_SHIFT (0u) -#define GPIO_PFCAE2_PFCAE21_SHIFT (1u) -#define GPIO_PFCAE2_PFCAE22_SHIFT (2u) -#define GPIO_PFCAE2_PFCAE23_SHIFT (3u) -#define GPIO_PFCAE2_PFCAE24_SHIFT (4u) -#define GPIO_PFCAE2_PFCAE25_SHIFT (5u) -#define GPIO_PFCAE2_PFCAE26_SHIFT (6u) -#define GPIO_PFCAE2_PFCAE27_SHIFT (7u) -#define GPIO_PFCAE2_PFCAE28_SHIFT (8u) -#define GPIO_PFCAE2_PFCAE29_SHIFT (9u) -#define GPIO_PFCAE2_PFCAE210_SHIFT (10u) -#define GPIO_PFCAE2_PFCAE211_SHIFT (11u) -#define GPIO_PFCAE2_PFCAE212_SHIFT (12u) -#define GPIO_PFCAE2_PFCAE213_SHIFT (13u) -#define GPIO_PFCAE2_PFCAE214_SHIFT (14u) -#define GPIO_PFCAE2_PFCAE215_SHIFT (15u) - -#define GPIO_PIBC2_PIBC20_SHIFT (0u) -#define GPIO_PIBC2_PIBC21_SHIFT (1u) -#define GPIO_PIBC2_PIBC22_SHIFT (2u) -#define GPIO_PIBC2_PIBC23_SHIFT (3u) -#define GPIO_PIBC2_PIBC24_SHIFT (4u) -#define GPIO_PIBC2_PIBC25_SHIFT (5u) -#define GPIO_PIBC2_PIBC26_SHIFT (6u) -#define GPIO_PIBC2_PIBC27_SHIFT (7u) -#define GPIO_PIBC2_PIBC28_SHIFT (8u) -#define GPIO_PIBC2_PIBC29_SHIFT (9u) -#define GPIO_PIBC2_PIBC210_SHIFT (10u) -#define GPIO_PIBC2_PIBC211_SHIFT (11u) -#define GPIO_PIBC2_PIBC212_SHIFT (12u) -#define GPIO_PIBC2_PIBC213_SHIFT (13u) -#define GPIO_PIBC2_PIBC214_SHIFT (14u) -#define GPIO_PIBC2_PIBC215_SHIFT (15u) - -#define GPIO_PBDC2_PBDC20_SHIFT (0u) -#define GPIO_PBDC2_PBDC21_SHIFT (1u) -#define GPIO_PBDC2_PBDC22_SHIFT (2u) -#define GPIO_PBDC2_PBDC23_SHIFT (3u) -#define GPIO_PBDC2_PBDC24_SHIFT (4u) -#define GPIO_PBDC2_PBDC25_SHIFT (5u) -#define GPIO_PBDC2_PBDC26_SHIFT (6u) -#define GPIO_PBDC2_PBDC27_SHIFT (7u) -#define GPIO_PBDC2_PBDC28_SHIFT (8u) -#define GPIO_PBDC2_PBDC29_SHIFT (9u) -#define GPIO_PBDC2_PBDC210_SHIFT (10u) -#define GPIO_PBDC2_PBDC211_SHIFT (11u) -#define GPIO_PBDC2_PBDC212_SHIFT (12u) -#define GPIO_PBDC2_PBDC213_SHIFT (13u) -#define GPIO_PBDC2_PBDC214_SHIFT (14u) -#define GPIO_PBDC2_PBDC215_SHIFT (15u) - -#define GPIO_PIPC2_PIPC20_SHIFT (0u) -#define GPIO_PIPC2_PIPC21_SHIFT (1u) -#define GPIO_PIPC2_PIPC22_SHIFT (2u) -#define GPIO_PIPC2_PIPC23_SHIFT (3u) -#define GPIO_PIPC2_PIPC24_SHIFT (4u) -#define GPIO_PIPC2_PIPC25_SHIFT (5u) -#define GPIO_PIPC2_PIPC26_SHIFT (6u) -#define GPIO_PIPC2_PIPC27_SHIFT (7u) -#define GPIO_PIPC2_PIPC28_SHIFT (8u) -#define GPIO_PIPC2_PIPC29_SHIFT (9u) -#define GPIO_PIPC2_PIPC210_SHIFT (10u) -#define GPIO_PIPC2_PIPC211_SHIFT (11u) -#define GPIO_PIPC2_PIPC212_SHIFT (12u) -#define GPIO_PIPC2_PIPC213_SHIFT (13u) -#define GPIO_PIPC2_PIPC214_SHIFT (14u) -#define GPIO_PIPC2_PIPC215_SHIFT (15u) - -/* ---- P3 ---- */ -#define GPIO_P3_P30_SHIFT (0u) -#define GPIO_P3_P31_SHIFT (1u) -#define GPIO_P3_P32_SHIFT (2u) -#define GPIO_P3_P33_SHIFT (3u) -#define GPIO_P3_P34_SHIFT (4u) -#define GPIO_P3_P35_SHIFT (5u) -#define GPIO_P3_P36_SHIFT (6u) -#define GPIO_P3_P37_SHIFT (7u) -#define GPIO_P3_P38_SHIFT (8u) -#define GPIO_P3_P39_SHIFT (9u) -#define GPIO_P3_P310_SHIFT (10u) -#define GPIO_P3_P311_SHIFT (11u) -#define GPIO_P3_P312_SHIFT (12u) -#define GPIO_P3_P313_SHIFT (13u) -#define GPIO_P3_P314_SHIFT (14u) -#define GPIO_P3_P315_SHIFT (15u) - -#define GPIO_PSR3_PSR30_SHIFT (0u) -#define GPIO_PSR3_PSR31_SHIFT (1u) -#define GPIO_PSR3_PSR32_SHIFT (2u) -#define GPIO_PSR3_PSR33_SHIFT (3u) -#define GPIO_PSR3_PSR34_SHIFT (4u) -#define GPIO_PSR3_PSR35_SHIFT (5u) -#define GPIO_PSR3_PSR36_SHIFT (6u) -#define GPIO_PSR3_PSR37_SHIFT (7u) -#define GPIO_PSR3_PSR38_SHIFT (8u) -#define GPIO_PSR3_PSR39_SHIFT (9u) -#define GPIO_PSR3_PSR310_SHIFT (10u) -#define GPIO_PSR3_PSR311_SHIFT (11u) -#define GPIO_PSR3_PSR312_SHIFT (12u) -#define GPIO_PSR3_PSR313_SHIFT (13u) -#define GPIO_PSR3_PSR314_SHIFT (14u) -#define GPIO_PSR3_PSR315_SHIFT (15u) -#define GPIO_PSR3_PSR316_SHIFT (16u) -#define GPIO_PSR3_PSR317_SHIFT (17u) -#define GPIO_PSR3_PSR318_SHIFT (18u) -#define GPIO_PSR3_PSR319_SHIFT (19u) -#define GPIO_PSR3_PSR320_SHIFT (20u) -#define GPIO_PSR3_PSR321_SHIFT (21u) -#define GPIO_PSR3_PSR322_SHIFT (22u) -#define GPIO_PSR3_PSR323_SHIFT (23u) -#define GPIO_PSR3_PSR324_SHIFT (24u) -#define GPIO_PSR3_PSR325_SHIFT (25u) -#define GPIO_PSR3_PSR326_SHIFT (26u) -#define GPIO_PSR3_PSR327_SHIFT (27u) -#define GPIO_PSR3_PSR328_SHIFT (28u) -#define GPIO_PSR3_PSR329_SHIFT (29u) -#define GPIO_PSR3_PSR330_SHIFT (30u) -#define GPIO_PSR3_PSR331_SHIFT (31u) - -#define GPIO_PPR3_PPR30_SHIFT (0u) -#define GPIO_PPR3_PPR31_SHIFT (1u) -#define GPIO_PPR3_PPR32_SHIFT (2u) -#define GPIO_PPR3_PPR33_SHIFT (3u) -#define GPIO_PPR3_PPR34_SHIFT (4u) -#define GPIO_PPR3_PPR35_SHIFT (5u) -#define GPIO_PPR3_PPR36_SHIFT (6u) -#define GPIO_PPR3_PPR37_SHIFT (7u) -#define GPIO_PPR3_PPR38_SHIFT (8u) -#define GPIO_PPR3_PPR39_SHIFT (9u) -#define GPIO_PPR3_PPR310_SHIFT (10u) -#define GPIO_PPR3_PPR311_SHIFT (11u) -#define GPIO_PPR3_PPR312_SHIFT (12u) -#define GPIO_PPR3_PPR313_SHIFT (13u) -#define GPIO_PPR3_PPR314_SHIFT (14u) -#define GPIO_PPR3_PPR315_SHIFT (15u) - -#define GPIO_PM3_PM30_SHIFT (0u) -#define GPIO_PM3_PM31_SHIFT (1u) -#define GPIO_PM3_PM32_SHIFT (2u) -#define GPIO_PM3_PM33_SHIFT (3u) -#define GPIO_PM3_PM34_SHIFT (4u) -#define GPIO_PM3_PM35_SHIFT (5u) -#define GPIO_PM3_PM36_SHIFT (6u) -#define GPIO_PM3_PM37_SHIFT (7u) -#define GPIO_PM3_PM38_SHIFT (8u) -#define GPIO_PM3_PM39_SHIFT (9u) -#define GPIO_PM3_PM310_SHIFT (10u) -#define GPIO_PM3_PM311_SHIFT (11u) -#define GPIO_PM3_PM312_SHIFT (12u) -#define GPIO_PM3_PM313_SHIFT (13u) -#define GPIO_PM3_PM314_SHIFT (14u) -#define GPIO_PM3_PM315_SHIFT (15u) - -#define GPIO_PMC3_PMC30_SHIFT (0u) -#define GPIO_PMC3_PMC31_SHIFT (1u) -#define GPIO_PMC3_PMC32_SHIFT (2u) -#define GPIO_PMC3_PMC33_SHIFT (3u) -#define GPIO_PMC3_PMC34_SHIFT (4u) -#define GPIO_PMC3_PMC35_SHIFT (5u) -#define GPIO_PMC3_PMC36_SHIFT (6u) -#define GPIO_PMC3_PMC37_SHIFT (7u) -#define GPIO_PMC3_PMC38_SHIFT (8u) -#define GPIO_PMC3_PMC39_SHIFT (9u) -#define GPIO_PMC3_PMC310_SHIFT (10u) -#define GPIO_PMC3_PMC311_SHIFT (11u) -#define GPIO_PMC3_PMC312_SHIFT (12u) -#define GPIO_PMC3_PMC313_SHIFT (13u) -#define GPIO_PMC3_PMC314_SHIFT (14u) -#define GPIO_PMC3_PMC315_SHIFT (15u) - -#define GPIO_PFC3_PFC30_SHIFT (0u) -#define GPIO_PFC3_PFC31_SHIFT (1u) -#define GPIO_PFC3_PFC32_SHIFT (2u) -#define GPIO_PFC3_PFC33_SHIFT (3u) -#define GPIO_PFC3_PFC34_SHIFT (4u) -#define GPIO_PFC3_PFC35_SHIFT (5u) -#define GPIO_PFC3_PFC36_SHIFT (6u) -#define GPIO_PFC3_PFC37_SHIFT (7u) -#define GPIO_PFC3_PFC38_SHIFT (8u) -#define GPIO_PFC3_PFC39_SHIFT (9u) -#define GPIO_PFC3_PFC310_SHIFT (10u) -#define GPIO_PFC3_PFC311_SHIFT (11u) -#define GPIO_PFC3_PFC312_SHIFT (12u) -#define GPIO_PFC3_PFC313_SHIFT (13u) -#define GPIO_PFC3_PFC314_SHIFT (14u) -#define GPIO_PFC3_PFC315_SHIFT (15u) - -#define GPIO_PFCE3_PFCE30_SHIFT (0u) -#define GPIO_PFCE3_PFCE31_SHIFT (1u) -#define GPIO_PFCE3_PFCE32_SHIFT (2u) -#define GPIO_PFCE3_PFCE33_SHIFT (3u) -#define GPIO_PFCE3_PFCE34_SHIFT (4u) -#define GPIO_PFCE3_PFCE35_SHIFT (5u) -#define GPIO_PFCE3_PFCE36_SHIFT (6u) -#define GPIO_PFCE3_PFCE37_SHIFT (7u) -#define GPIO_PFCE3_PFCE38_SHIFT (8u) -#define GPIO_PFCE3_PFCE39_SHIFT (9u) -#define GPIO_PFCE3_PFCE310_SHIFT (10u) -#define GPIO_PFCE3_PFCE311_SHIFT (11u) -#define GPIO_PFCE3_PFCE312_SHIFT (12u) -#define GPIO_PFCE3_PFCE313_SHIFT (13u) -#define GPIO_PFCE3_PFCE314_SHIFT (14u) -#define GPIO_PFCE3_PFCE315_SHIFT (15u) - -#define GPIO_PNOT3_PNOT30_SHIFT (0u) -#define GPIO_PNOT3_PNOT31_SHIFT (1u) -#define GPIO_PNOT3_PNOT32_SHIFT (2u) -#define GPIO_PNOT3_PNOT33_SHIFT (3u) -#define GPIO_PNOT3_PNOT34_SHIFT (4u) -#define GPIO_PNOT3_PNOT35_SHIFT (5u) -#define GPIO_PNOT3_PNOT36_SHIFT (6u) -#define GPIO_PNOT3_PNOT37_SHIFT (7u) -#define GPIO_PNOT3_PNOT38_SHIFT (8u) -#define GPIO_PNOT3_PNOT39_SHIFT (9u) -#define GPIO_PNOT3_PNOT310_SHIFT (10u) -#define GPIO_PNOT3_PNOT311_SHIFT (11u) -#define GPIO_PNOT3_PNOT312_SHIFT (12u) -#define GPIO_PNOT3_PNOT313_SHIFT (13u) -#define GPIO_PNOT3_PNOT314_SHIFT (14u) -#define GPIO_PNOT3_PNOT315_SHIFT (15u) - -#define GPIO_PMSR3_PMSR30_SHIFT (0u) -#define GPIO_PMSR3_PMSR31_SHIFT (1u) -#define GPIO_PMSR3_PMSR32_SHIFT (2u) -#define GPIO_PMSR3_PMSR33_SHIFT (3u) -#define GPIO_PMSR3_PMSR34_SHIFT (4u) -#define GPIO_PMSR3_PMSR35_SHIFT (5u) -#define GPIO_PMSR3_PMSR36_SHIFT (6u) -#define GPIO_PMSR3_PMSR37_SHIFT (7u) -#define GPIO_PMSR3_PMSR38_SHIFT (8u) -#define GPIO_PMSR3_PMSR39_SHIFT (9u) -#define GPIO_PMSR3_PMSR310_SHIFT (10u) -#define GPIO_PMSR3_PMSR311_SHIFT (11u) -#define GPIO_PMSR3_PMSR312_SHIFT (12u) -#define GPIO_PMSR3_PMSR313_SHIFT (13u) -#define GPIO_PMSR3_PMSR314_SHIFT (14u) -#define GPIO_PMSR3_PMSR315_SHIFT (15u) -#define GPIO_PMSR3_PMSR316_SHIFT (16u) -#define GPIO_PMSR3_PMSR317_SHIFT (17u) -#define GPIO_PMSR3_PMSR318_SHIFT (18u) -#define GPIO_PMSR3_PMSR319_SHIFT (19u) -#define GPIO_PMSR3_PMSR320_SHIFT (20u) -#define GPIO_PMSR3_PMSR321_SHIFT (21u) -#define GPIO_PMSR3_PMSR322_SHIFT (22u) -#define GPIO_PMSR3_PMSR323_SHIFT (23u) -#define GPIO_PMSR3_PMSR324_SHIFT (24u) -#define GPIO_PMSR3_PMSR325_SHIFT (25u) -#define GPIO_PMSR3_PMSR326_SHIFT (26u) -#define GPIO_PMSR3_PMSR327_SHIFT (27u) -#define GPIO_PMSR3_PMSR328_SHIFT (28u) -#define GPIO_PMSR3_PMSR329_SHIFT (29u) -#define GPIO_PMSR3_PMSR330_SHIFT (30u) -#define GPIO_PMSR3_PMSR331_SHIFT (31u) - -#define GPIO_PMCSR3_PMCSR30_SHIFT (0u) -#define GPIO_PMCSR3_PMCSR31_SHIFT (1u) -#define GPIO_PMCSR3_PMCSR32_SHIFT (2u) -#define GPIO_PMCSR3_PMCSR33_SHIFT (3u) -#define GPIO_PMCSR3_PMCSR34_SHIFT (4u) -#define GPIO_PMCSR3_PMCSR35_SHIFT (5u) -#define GPIO_PMCSR3_PMCSR36_SHIFT (6u) -#define GPIO_PMCSR3_PMCSR37_SHIFT (7u) -#define GPIO_PMCSR3_PMCSR38_SHIFT (8u) -#define GPIO_PMCSR3_PMCSR39_SHIFT (9u) -#define GPIO_PMCSR3_PMCSR310_SHIFT (10u) -#define GPIO_PMCSR3_PMCSR311_SHIFT (11u) -#define GPIO_PMCSR3_PMCSR312_SHIFT (12u) -#define GPIO_PMCSR3_PMCSR313_SHIFT (13u) -#define GPIO_PMCSR3_PMCSR314_SHIFT (14u) -#define GPIO_PMCSR3_PMCSR315_SHIFT (15u) -#define GPIO_PMCSR3_PMCSR316_SHIFT (16u) -#define GPIO_PMCSR3_PMCSR317_SHIFT (17u) -#define GPIO_PMCSR3_PMCSR318_SHIFT (18u) -#define GPIO_PMCSR3_PMCSR319_SHIFT (19u) -#define GPIO_PMCSR3_PMCSR320_SHIFT (20u) -#define GPIO_PMCSR3_PMCSR321_SHIFT (21u) -#define GPIO_PMCSR3_PMCSR322_SHIFT (22u) -#define GPIO_PMCSR3_PMCSR323_SHIFT (23u) -#define GPIO_PMCSR3_PMCSR324_SHIFT (24u) -#define GPIO_PMCSR3_PMCSR325_SHIFT (25u) -#define GPIO_PMCSR3_PMCSR326_SHIFT (26u) -#define GPIO_PMCSR3_PMCSR327_SHIFT (27u) -#define GPIO_PMCSR3_PMCSR328_SHIFT (28u) -#define GPIO_PMCSR3_PMCSR329_SHIFT (29u) -#define GPIO_PMCSR3_PMCSR330_SHIFT (30u) -#define GPIO_PMCSR3_PMCSR331_SHIFT (31u) - -#define GPIO_PFCAE3_PFCAE30_SHIFT (0u) -#define GPIO_PFCAE3_PFCAE31_SHIFT (1u) -#define GPIO_PFCAE3_PFCAE32_SHIFT (2u) -#define GPIO_PFCAE3_PFCAE33_SHIFT (3u) -#define GPIO_PFCAE3_PFCAE34_SHIFT (4u) -#define GPIO_PFCAE3_PFCAE35_SHIFT (5u) -#define GPIO_PFCAE3_PFCAE36_SHIFT (6u) -#define GPIO_PFCAE3_PFCAE37_SHIFT (7u) -#define GPIO_PFCAE3_PFCAE38_SHIFT (8u) -#define GPIO_PFCAE3_PFCAE39_SHIFT (9u) -#define GPIO_PFCAE3_PFCAE310_SHIFT (10u) -#define GPIO_PFCAE3_PFCAE311_SHIFT (11u) -#define GPIO_PFCAE3_PFCAE312_SHIFT (12u) -#define GPIO_PFCAE3_PFCAE313_SHIFT (13u) -#define GPIO_PFCAE3_PFCAE314_SHIFT (14u) -#define GPIO_PFCAE3_PFCAE315_SHIFT (15u) - -#define GPIO_PIBC3_PIBC30_SHIFT (0u) -#define GPIO_PIBC3_PIBC31_SHIFT (1u) -#define GPIO_PIBC3_PIBC32_SHIFT (2u) -#define GPIO_PIBC3_PIBC33_SHIFT (3u) -#define GPIO_PIBC3_PIBC34_SHIFT (4u) -#define GPIO_PIBC3_PIBC35_SHIFT (5u) -#define GPIO_PIBC3_PIBC36_SHIFT (6u) -#define GPIO_PIBC3_PIBC37_SHIFT (7u) -#define GPIO_PIBC3_PIBC38_SHIFT (8u) -#define GPIO_PIBC3_PIBC39_SHIFT (9u) -#define GPIO_PIBC3_PIBC310_SHIFT (10u) -#define GPIO_PIBC3_PIBC311_SHIFT (11u) -#define GPIO_PIBC3_PIBC312_SHIFT (12u) -#define GPIO_PIBC3_PIBC313_SHIFT (13u) -#define GPIO_PIBC3_PIBC314_SHIFT (14u) -#define GPIO_PIBC3_PIBC315_SHIFT (15u) - -#define GPIO_PBDC3_PBDC30_SHIFT (0u) -#define GPIO_PBDC3_PBDC31_SHIFT (1u) -#define GPIO_PBDC3_PBDC32_SHIFT (2u) -#define GPIO_PBDC3_PBDC33_SHIFT (3u) -#define GPIO_PBDC3_PBDC34_SHIFT (4u) -#define GPIO_PBDC3_PBDC35_SHIFT (5u) -#define GPIO_PBDC3_PBDC36_SHIFT (6u) -#define GPIO_PBDC3_PBDC37_SHIFT (7u) -#define GPIO_PBDC3_PBDC38_SHIFT (8u) -#define GPIO_PBDC3_PBDC39_SHIFT (9u) -#define GPIO_PBDC3_PBDC310_SHIFT (10u) -#define GPIO_PBDC3_PBDC311_SHIFT (11u) -#define GPIO_PBDC3_PBDC312_SHIFT (12u) -#define GPIO_PBDC3_PBDC313_SHIFT (13u) -#define GPIO_PBDC3_PBDC314_SHIFT (14u) -#define GPIO_PBDC3_PBDC315_SHIFT (15u) - -#define GPIO_PIPC3_PIPC30_SHIFT (0u) -#define GPIO_PIPC3_PIPC31_SHIFT (1u) -#define GPIO_PIPC3_PIPC32_SHIFT (2u) -#define GPIO_PIPC3_PIPC33_SHIFT (3u) -#define GPIO_PIPC3_PIPC34_SHIFT (4u) -#define GPIO_PIPC3_PIPC35_SHIFT (5u) -#define GPIO_PIPC3_PIPC36_SHIFT (6u) -#define GPIO_PIPC3_PIPC37_SHIFT (7u) -#define GPIO_PIPC3_PIPC38_SHIFT (8u) -#define GPIO_PIPC3_PIPC39_SHIFT (9u) -#define GPIO_PIPC3_PIPC310_SHIFT (10u) -#define GPIO_PIPC3_PIPC311_SHIFT (11u) -#define GPIO_PIPC3_PIPC312_SHIFT (12u) -#define GPIO_PIPC3_PIPC313_SHIFT (13u) -#define GPIO_PIPC3_PIPC314_SHIFT (14u) -#define GPIO_PIPC3_PIPC315_SHIFT (15u) - -/* ---- P4 ---- */ -#define GPIO_P4_P40_SHIFT (0u) -#define GPIO_P4_P41_SHIFT (1u) -#define GPIO_P4_P42_SHIFT (2u) -#define GPIO_P4_P43_SHIFT (3u) -#define GPIO_P4_P44_SHIFT (4u) -#define GPIO_P4_P45_SHIFT (5u) -#define GPIO_P4_P46_SHIFT (6u) -#define GPIO_P4_P47_SHIFT (7u) -#define GPIO_P4_P48_SHIFT (8u) -#define GPIO_P4_P49_SHIFT (9u) -#define GPIO_P4_P410_SHIFT (10u) -#define GPIO_P4_P411_SHIFT (11u) -#define GPIO_P4_P412_SHIFT (12u) -#define GPIO_P4_P413_SHIFT (13u) -#define GPIO_P4_P414_SHIFT (14u) -#define GPIO_P4_P415_SHIFT (15u) - -#define GPIO_PSR4_PSR40_SHIFT (0u) -#define GPIO_PSR4_PSR41_SHIFT (1u) -#define GPIO_PSR4_PSR42_SHIFT (2u) -#define GPIO_PSR4_PSR43_SHIFT (3u) -#define GPIO_PSR4_PSR44_SHIFT (4u) -#define GPIO_PSR4_PSR45_SHIFT (5u) -#define GPIO_PSR4_PSR46_SHIFT (6u) -#define GPIO_PSR4_PSR47_SHIFT (7u) -#define GPIO_PSR4_PSR48_SHIFT (8u) -#define GPIO_PSR4_PSR49_SHIFT (9u) -#define GPIO_PSR4_PSR410_SHIFT (10u) -#define GPIO_PSR4_PSR411_SHIFT (11u) -#define GPIO_PSR4_PSR412_SHIFT (12u) -#define GPIO_PSR4_PSR413_SHIFT (13u) -#define GPIO_PSR4_PSR414_SHIFT (14u) -#define GPIO_PSR4_PSR415_SHIFT (15u) -#define GPIO_PSR4_PSR416_SHIFT (16u) -#define GPIO_PSR4_PSR417_SHIFT (17u) -#define GPIO_PSR4_PSR418_SHIFT (18u) -#define GPIO_PSR4_PSR419_SHIFT (19u) -#define GPIO_PSR4_PSR420_SHIFT (20u) -#define GPIO_PSR4_PSR421_SHIFT (21u) -#define GPIO_PSR4_PSR422_SHIFT (22u) -#define GPIO_PSR4_PSR423_SHIFT (23u) -#define GPIO_PSR4_PSR424_SHIFT (24u) -#define GPIO_PSR4_PSR425_SHIFT (25u) -#define GPIO_PSR4_PSR426_SHIFT (26u) -#define GPIO_PSR4_PSR427_SHIFT (27u) -#define GPIO_PSR4_PSR428_SHIFT (28u) -#define GPIO_PSR4_PSR429_SHIFT (29u) -#define GPIO_PSR4_PSR430_SHIFT (30u) -#define GPIO_PSR4_PSR431_SHIFT (31u) - -#define GPIO_PPR4_PPR40_SHIFT (0u) -#define GPIO_PPR4_PPR41_SHIFT (1u) -#define GPIO_PPR4_PPR42_SHIFT (2u) -#define GPIO_PPR4_PPR43_SHIFT (3u) -#define GPIO_PPR4_PPR44_SHIFT (4u) -#define GPIO_PPR4_PPR45_SHIFT (5u) -#define GPIO_PPR4_PPR46_SHIFT (6u) -#define GPIO_PPR4_PPR47_SHIFT (7u) -#define GPIO_PPR4_PPR48_SHIFT (8u) -#define GPIO_PPR4_PPR49_SHIFT (9u) -#define GPIO_PPR4_PPR410_SHIFT (10u) -#define GPIO_PPR4_PPR411_SHIFT (11u) -#define GPIO_PPR4_PPR412_SHIFT (12u) -#define GPIO_PPR4_PPR413_SHIFT (13u) -#define GPIO_PPR4_PPR414_SHIFT (14u) -#define GPIO_PPR4_PPR415_SHIFT (15u) - -#define GPIO_PM4_PM40_SHIFT (0u) -#define GPIO_PM4_PM41_SHIFT (1u) -#define GPIO_PM4_PM42_SHIFT (2u) -#define GPIO_PM4_PM43_SHIFT (3u) -#define GPIO_PM4_PM44_SHIFT (4u) -#define GPIO_PM4_PM45_SHIFT (5u) -#define GPIO_PM4_PM46_SHIFT (6u) -#define GPIO_PM4_PM47_SHIFT (7u) -#define GPIO_PM4_PM48_SHIFT (8u) -#define GPIO_PM4_PM49_SHIFT (9u) -#define GPIO_PM4_PM410_SHIFT (10u) -#define GPIO_PM4_PM411_SHIFT (11u) -#define GPIO_PM4_PM412_SHIFT (12u) -#define GPIO_PM4_PM413_SHIFT (13u) -#define GPIO_PM4_PM414_SHIFT (14u) -#define GPIO_PM4_PM415_SHIFT (15u) - -#define GPIO_PMC4_PMC40_SHIFT (0u) -#define GPIO_PMC4_PMC41_SHIFT (1u) -#define GPIO_PMC4_PMC42_SHIFT (2u) -#define GPIO_PMC4_PMC43_SHIFT (3u) -#define GPIO_PMC4_PMC44_SHIFT (4u) -#define GPIO_PMC4_PMC45_SHIFT (5u) -#define GPIO_PMC4_PMC46_SHIFT (6u) -#define GPIO_PMC4_PMC47_SHIFT (7u) -#define GPIO_PMC4_PMC48_SHIFT (8u) -#define GPIO_PMC4_PMC49_SHIFT (9u) -#define GPIO_PMC4_PMC410_SHIFT (10u) -#define GPIO_PMC4_PMC411_SHIFT (11u) -#define GPIO_PMC4_PMC412_SHIFT (12u) -#define GPIO_PMC4_PMC413_SHIFT (13u) -#define GPIO_PMC4_PMC414_SHIFT (14u) -#define GPIO_PMC4_PMC415_SHIFT (15u) - -#define GPIO_PFC4_PFC40_SHIFT (0u) -#define GPIO_PFC4_PFC41_SHIFT (1u) -#define GPIO_PFC4_PFC42_SHIFT (2u) -#define GPIO_PFC4_PFC43_SHIFT (3u) -#define GPIO_PFC4_PFC44_SHIFT (4u) -#define GPIO_PFC4_PFC45_SHIFT (5u) -#define GPIO_PFC4_PFC46_SHIFT (6u) -#define GPIO_PFC4_PFC47_SHIFT (7u) -#define GPIO_PFC4_PFC48_SHIFT (8u) -#define GPIO_PFC4_PFC49_SHIFT (9u) -#define GPIO_PFC4_PFC410_SHIFT (10u) -#define GPIO_PFC4_PFC411_SHIFT (11u) -#define GPIO_PFC4_PFC412_SHIFT (12u) -#define GPIO_PFC4_PFC413_SHIFT (13u) -#define GPIO_PFC4_PFC414_SHIFT (14u) -#define GPIO_PFC4_PFC415_SHIFT (15u) - -#define GPIO_PFCE4_PFCE40_SHIFT (0u) -#define GPIO_PFCE4_PFCE41_SHIFT (1u) -#define GPIO_PFCE4_PFCE42_SHIFT (2u) -#define GPIO_PFCE4_PFCE43_SHIFT (3u) -#define GPIO_PFCE4_PFCE44_SHIFT (4u) -#define GPIO_PFCE4_PFCE45_SHIFT (5u) -#define GPIO_PFCE4_PFCE46_SHIFT (6u) -#define GPIO_PFCE4_PFCE47_SHIFT (7u) -#define GPIO_PFCE4_PFCE48_SHIFT (8u) -#define GPIO_PFCE4_PFCE49_SHIFT (9u) -#define GPIO_PFCE4_PFCE410_SHIFT (10u) -#define GPIO_PFCE4_PFCE411_SHIFT (11u) -#define GPIO_PFCE4_PFCE412_SHIFT (12u) -#define GPIO_PFCE4_PFCE413_SHIFT (13u) -#define GPIO_PFCE4_PFCE414_SHIFT (14u) -#define GPIO_PFCE4_PFCE415_SHIFT (15u) - -#define GPIO_PNOT4_PNOT40_SHIFT (0u) -#define GPIO_PNOT4_PNOT41_SHIFT (1u) -#define GPIO_PNOT4_PNOT42_SHIFT (2u) -#define GPIO_PNOT4_PNOT43_SHIFT (3u) -#define GPIO_PNOT4_PNOT44_SHIFT (4u) -#define GPIO_PNOT4_PNOT45_SHIFT (5u) -#define GPIO_PNOT4_PNOT46_SHIFT (6u) -#define GPIO_PNOT4_PNOT47_SHIFT (7u) -#define GPIO_PNOT4_PNOT48_SHIFT (8u) -#define GPIO_PNOT4_PNOT49_SHIFT (9u) -#define GPIO_PNOT4_PNOT410_SHIFT (10u) -#define GPIO_PNOT4_PNOT411_SHIFT (11u) -#define GPIO_PNOT4_PNOT412_SHIFT (12u) -#define GPIO_PNOT4_PNOT413_SHIFT (13u) -#define GPIO_PNOT4_PNOT414_SHIFT (14u) -#define GPIO_PNOT4_PNOT415_SHIFT (15u) - -#define GPIO_PMSR4_PMSR40_SHIFT (0u) -#define GPIO_PMSR4_PMSR41_SHIFT (1u) -#define GPIO_PMSR4_PMSR42_SHIFT (2u) -#define GPIO_PMSR4_PMSR43_SHIFT (3u) -#define GPIO_PMSR4_PMSR44_SHIFT (4u) -#define GPIO_PMSR4_PMSR45_SHIFT (5u) -#define GPIO_PMSR4_PMSR46_SHIFT (6u) -#define GPIO_PMSR4_PMSR47_SHIFT (7u) -#define GPIO_PMSR4_PMSR48_SHIFT (8u) -#define GPIO_PMSR4_PMSR49_SHIFT (9u) -#define GPIO_PMSR4_PMSR410_SHIFT (10u) -#define GPIO_PMSR4_PMSR411_SHIFT (11u) -#define GPIO_PMSR4_PMSR412_SHIFT (12u) -#define GPIO_PMSR4_PMSR413_SHIFT (13u) -#define GPIO_PMSR4_PMSR414_SHIFT (14u) -#define GPIO_PMSR4_PMSR415_SHIFT (15u) -#define GPIO_PMSR4_PMSR416_SHIFT (16u) -#define GPIO_PMSR4_PMSR417_SHIFT (17u) -#define GPIO_PMSR4_PMSR418_SHIFT (18u) -#define GPIO_PMSR4_PMSR419_SHIFT (19u) -#define GPIO_PMSR4_PMSR420_SHIFT (20u) -#define GPIO_PMSR4_PMSR421_SHIFT (21u) -#define GPIO_PMSR4_PMSR422_SHIFT (22u) -#define GPIO_PMSR4_PMSR423_SHIFT (23u) -#define GPIO_PMSR4_PMSR424_SHIFT (24u) -#define GPIO_PMSR4_PMSR425_SHIFT (25u) -#define GPIO_PMSR4_PMSR426_SHIFT (26u) -#define GPIO_PMSR4_PMSR427_SHIFT (27u) -#define GPIO_PMSR4_PMSR428_SHIFT (28u) -#define GPIO_PMSR4_PMSR429_SHIFT (29u) -#define GPIO_PMSR4_PMSR430_SHIFT (30u) -#define GPIO_PMSR4_PMSR431_SHIFT (31u) - -#define GPIO_PMCSR4_PMCSR40_SHIFT (0u) -#define GPIO_PMCSR4_PMCSR41_SHIFT (1u) -#define GPIO_PMCSR4_PMCSR42_SHIFT (2u) -#define GPIO_PMCSR4_PMCSR43_SHIFT (3u) -#define GPIO_PMCSR4_PMCSR44_SHIFT (4u) -#define GPIO_PMCSR4_PMCSR45_SHIFT (5u) -#define GPIO_PMCSR4_PMCSR46_SHIFT (6u) -#define GPIO_PMCSR4_PMCSR47_SHIFT (7u) -#define GPIO_PMCSR4_PMCSR48_SHIFT (8u) -#define GPIO_PMCSR4_PMCSR49_SHIFT (9u) -#define GPIO_PMCSR4_PMCSR410_SHIFT (10u) -#define GPIO_PMCSR4_PMCSR411_SHIFT (11u) -#define GPIO_PMCSR4_PMCSR412_SHIFT (12u) -#define GPIO_PMCSR4_PMCSR413_SHIFT (13u) -#define GPIO_PMCSR4_PMCSR414_SHIFT (14u) -#define GPIO_PMCSR4_PMCSR415_SHIFT (15u) -#define GPIO_PMCSR4_PMCSR416_SHIFT (16u) -#define GPIO_PMCSR4_PMCSR417_SHIFT (17u) -#define GPIO_PMCSR4_PMCSR418_SHIFT (18u) -#define GPIO_PMCSR4_PMCSR419_SHIFT (19u) -#define GPIO_PMCSR4_PMCSR420_SHIFT (20u) -#define GPIO_PMCSR4_PMCSR421_SHIFT (21u) -#define GPIO_PMCSR4_PMCSR422_SHIFT (22u) -#define GPIO_PMCSR4_PMCSR423_SHIFT (23u) -#define GPIO_PMCSR4_PMCSR424_SHIFT (24u) -#define GPIO_PMCSR4_PMCSR425_SHIFT (25u) -#define GPIO_PMCSR4_PMCSR426_SHIFT (26u) -#define GPIO_PMCSR4_PMCSR427_SHIFT (27u) -#define GPIO_PMCSR4_PMCSR428_SHIFT (28u) -#define GPIO_PMCSR4_PMCSR429_SHIFT (29u) -#define GPIO_PMCSR4_PMCSR430_SHIFT (30u) -#define GPIO_PMCSR4_PMCSR431_SHIFT (31u) - -#define GPIO_PFCAE4_PFCAE40_SHIFT (0u) -#define GPIO_PFCAE4_PFCAE41_SHIFT (1u) -#define GPIO_PFCAE4_PFCAE42_SHIFT (2u) -#define GPIO_PFCAE4_PFCAE43_SHIFT (3u) -#define GPIO_PFCAE4_PFCAE44_SHIFT (4u) -#define GPIO_PFCAE4_PFCAE45_SHIFT (5u) -#define GPIO_PFCAE4_PFCAE46_SHIFT (6u) -#define GPIO_PFCAE4_PFCAE47_SHIFT (7u) -#define GPIO_PFCAE4_PFCAE48_SHIFT (8u) -#define GPIO_PFCAE4_PFCAE49_SHIFT (9u) -#define GPIO_PFCAE4_PFCAE410_SHIFT (10u) -#define GPIO_PFCAE4_PFCAE411_SHIFT (11u) -#define GPIO_PFCAE4_PFCAE412_SHIFT (12u) -#define GPIO_PFCAE4_PFCAE413_SHIFT (13u) -#define GPIO_PFCAE4_PFCAE414_SHIFT (14u) -#define GPIO_PFCAE4_PFCAE415_SHIFT (15u) - -#define GPIO_PIBC4_PIBC40_SHIFT (0u) -#define GPIO_PIBC4_PIBC41_SHIFT (1u) -#define GPIO_PIBC4_PIBC42_SHIFT (2u) -#define GPIO_PIBC4_PIBC43_SHIFT (3u) -#define GPIO_PIBC4_PIBC44_SHIFT (4u) -#define GPIO_PIBC4_PIBC45_SHIFT (5u) -#define GPIO_PIBC4_PIBC46_SHIFT (6u) -#define GPIO_PIBC4_PIBC47_SHIFT (7u) -#define GPIO_PIBC4_PIBC48_SHIFT (8u) -#define GPIO_PIBC4_PIBC49_SHIFT (9u) -#define GPIO_PIBC4_PIBC410_SHIFT (10u) -#define GPIO_PIBC4_PIBC411_SHIFT (11u) -#define GPIO_PIBC4_PIBC412_SHIFT (12u) -#define GPIO_PIBC4_PIBC413_SHIFT (13u) -#define GPIO_PIBC4_PIBC414_SHIFT (14u) -#define GPIO_PIBC4_PIBC415_SHIFT (15u) - -#define GPIO_PBDC4_PBDC40_SHIFT (0u) -#define GPIO_PBDC4_PBDC41_SHIFT (1u) -#define GPIO_PBDC4_PBDC42_SHIFT (2u) -#define GPIO_PBDC4_PBDC43_SHIFT (3u) -#define GPIO_PBDC4_PBDC44_SHIFT (4u) -#define GPIO_PBDC4_PBDC45_SHIFT (5u) -#define GPIO_PBDC4_PBDC46_SHIFT (6u) -#define GPIO_PBDC4_PBDC47_SHIFT (7u) -#define GPIO_PBDC4_PBDC48_SHIFT (8u) -#define GPIO_PBDC4_PBDC49_SHIFT (9u) -#define GPIO_PBDC4_PBDC410_SHIFT (10u) -#define GPIO_PBDC4_PBDC411_SHIFT (11u) -#define GPIO_PBDC4_PBDC412_SHIFT (12u) -#define GPIO_PBDC4_PBDC413_SHIFT (13u) -#define GPIO_PBDC4_PBDC414_SHIFT (14u) -#define GPIO_PBDC4_PBDC415_SHIFT (15u) - -#define GPIO_PIPC4_PIPC40_SHIFT (0u) -#define GPIO_PIPC4_PIPC41_SHIFT (1u) -#define GPIO_PIPC4_PIPC42_SHIFT (2u) -#define GPIO_PIPC4_PIPC43_SHIFT (3u) -#define GPIO_PIPC4_PIPC44_SHIFT (4u) -#define GPIO_PIPC4_PIPC45_SHIFT (5u) -#define GPIO_PIPC4_PIPC46_SHIFT (6u) -#define GPIO_PIPC4_PIPC47_SHIFT (7u) -#define GPIO_PIPC4_PIPC48_SHIFT (8u) -#define GPIO_PIPC4_PIPC49_SHIFT (9u) -#define GPIO_PIPC4_PIPC410_SHIFT (10u) -#define GPIO_PIPC4_PIPC411_SHIFT (11u) -#define GPIO_PIPC4_PIPC412_SHIFT (12u) -#define GPIO_PIPC4_PIPC413_SHIFT (13u) -#define GPIO_PIPC4_PIPC414_SHIFT (14u) -#define GPIO_PIPC4_PIPC415_SHIFT (15u) - -/* ---- P5 ---- */ -#define GPIO_P5_P50_SHIFT (0u) -#define GPIO_P5_P51_SHIFT (1u) -#define GPIO_P5_P52_SHIFT (2u) -#define GPIO_P5_P53_SHIFT (3u) -#define GPIO_P5_P54_SHIFT (4u) -#define GPIO_P5_P55_SHIFT (5u) -#define GPIO_P5_P56_SHIFT (6u) -#define GPIO_P5_P57_SHIFT (7u) -#define GPIO_P5_P58_SHIFT (8u) -#define GPIO_P5_P59_SHIFT (9u) -#define GPIO_P5_P510_SHIFT (10u) - -#define GPIO_PSR5_PSR50_SHIFT (0u) -#define GPIO_PSR5_PSR51_SHIFT (1u) -#define GPIO_PSR5_PSR52_SHIFT (2u) -#define GPIO_PSR5_PSR53_SHIFT (3u) -#define GPIO_PSR5_PSR54_SHIFT (4u) -#define GPIO_PSR5_PSR55_SHIFT (5u) -#define GPIO_PSR5_PSR56_SHIFT (6u) -#define GPIO_PSR5_PSR57_SHIFT (7u) -#define GPIO_PSR5_PSR58_SHIFT (8u) -#define GPIO_PSR5_PSR59_SHIFT (9u) -#define GPIO_PSR5_PSR510_SHIFT (10u) -#define GPIO_PSR5_PSR516_SHIFT (16u) -#define GPIO_PSR5_PSR517_SHIFT (17u) -#define GPIO_PSR5_PSR518_SHIFT (18u) -#define GPIO_PSR5_PSR519_SHIFT (19u) -#define GPIO_PSR5_PSR520_SHIFT (20u) -#define GPIO_PSR5_PSR521_SHIFT (21u) -#define GPIO_PSR5_PSR522_SHIFT (22u) -#define GPIO_PSR5_PSR523_SHIFT (23u) -#define GPIO_PSR5_PSR524_SHIFT (24u) -#define GPIO_PSR5_PSR525_SHIFT (25u) -#define GPIO_PSR5_PSR526_SHIFT (26u) - -#define GPIO_PPR5_PPR50_SHIFT (0u) -#define GPIO_PPR5_PPR51_SHIFT (1u) -#define GPIO_PPR5_PPR52_SHIFT (2u) -#define GPIO_PPR5_PPR53_SHIFT (3u) -#define GPIO_PPR5_PPR54_SHIFT (4u) -#define GPIO_PPR5_PPR55_SHIFT (5u) -#define GPIO_PPR5_PPR56_SHIFT (6u) -#define GPIO_PPR5_PPR57_SHIFT (7u) -#define GPIO_PPR5_PPR58_SHIFT (8u) -#define GPIO_PPR5_PPR59_SHIFT (9u) -#define GPIO_PPR5_PPR510_SHIFT (10u) - -#define GPIO_PM5_PM50_SHIFT (0u) -#define GPIO_PM5_PM51_SHIFT (1u) -#define GPIO_PM5_PM52_SHIFT (2u) -#define GPIO_PM5_PM53_SHIFT (3u) -#define GPIO_PM5_PM54_SHIFT (4u) -#define GPIO_PM5_PM55_SHIFT (5u) -#define GPIO_PM5_PM56_SHIFT (6u) -#define GPIO_PM5_PM57_SHIFT (7u) -#define GPIO_PM5_PM58_SHIFT (8u) -#define GPIO_PM5_PM59_SHIFT (9u) -#define GPIO_PM5_PM510_SHIFT (10u) - -#define GPIO_PMC5_PMC50_SHIFT (0u) -#define GPIO_PMC5_PMC51_SHIFT (1u) -#define GPIO_PMC5_PMC52_SHIFT (2u) -#define GPIO_PMC5_PMC53_SHIFT (3u) -#define GPIO_PMC5_PMC54_SHIFT (4u) -#define GPIO_PMC5_PMC55_SHIFT (5u) -#define GPIO_PMC5_PMC56_SHIFT (6u) -#define GPIO_PMC5_PMC57_SHIFT (7u) -#define GPIO_PMC5_PMC58_SHIFT (8u) -#define GPIO_PMC5_PMC59_SHIFT (9u) -#define GPIO_PMC5_PMC510_SHIFT (10u) - -#define GPIO_PFC5_PFC50_SHIFT (0u) -#define GPIO_PFC5_PFC51_SHIFT (1u) -#define GPIO_PFC5_PFC52_SHIFT (2u) -#define GPIO_PFC5_PFC53_SHIFT (3u) -#define GPIO_PFC5_PFC54_SHIFT (4u) -#define GPIO_PFC5_PFC55_SHIFT (5u) -#define GPIO_PFC5_PFC56_SHIFT (6u) -#define GPIO_PFC5_PFC57_SHIFT (7u) -#define GPIO_PFC5_PFC58_SHIFT (8u) -#define GPIO_PFC5_PFC59_SHIFT (9u) -#define GPIO_PFC5_PFC510_SHIFT (10u) - -#define GPIO_PFCE5_PFCE50_SHIFT (0u) -#define GPIO_PFCE5_PFCE51_SHIFT (1u) -#define GPIO_PFCE5_PFCE52_SHIFT (2u) -#define GPIO_PFCE5_PFCE53_SHIFT (3u) -#define GPIO_PFCE5_PFCE54_SHIFT (4u) -#define GPIO_PFCE5_PFCE55_SHIFT (5u) -#define GPIO_PFCE5_PFCE56_SHIFT (6u) -#define GPIO_PFCE5_PFCE57_SHIFT (7u) -#define GPIO_PFCE5_PFCE58_SHIFT (8u) -#define GPIO_PFCE5_PFCE59_SHIFT (9u) -#define GPIO_PFCE5_PFCE510_SHIFT (10u) - -#define GPIO_PNOT5_PNOT50_SHIFT (0u) -#define GPIO_PNOT5_PNOT51_SHIFT (1u) -#define GPIO_PNOT5_PNOT52_SHIFT (2u) -#define GPIO_PNOT5_PNOT53_SHIFT (3u) -#define GPIO_PNOT5_PNOT54_SHIFT (4u) -#define GPIO_PNOT5_PNOT55_SHIFT (5u) -#define GPIO_PNOT5_PNOT56_SHIFT (6u) -#define GPIO_PNOT5_PNOT57_SHIFT (7u) -#define GPIO_PNOT5_PNOT58_SHIFT (8u) -#define GPIO_PNOT5_PNOT59_SHIFT (9u) -#define GPIO_PNOT5_PNOT510_SHIFT (10u) - -#define GPIO_PMSR5_PMSR50_SHIFT (0u) -#define GPIO_PMSR5_PMSR51_SHIFT (1u) -#define GPIO_PMSR5_PMSR52_SHIFT (2u) -#define GPIO_PMSR5_PMSR53_SHIFT (3u) -#define GPIO_PMSR5_PMSR54_SHIFT (4u) -#define GPIO_PMSR5_PMSR55_SHIFT (5u) -#define GPIO_PMSR5_PMSR56_SHIFT (6u) -#define GPIO_PMSR5_PMSR57_SHIFT (7u) -#define GPIO_PMSR5_PMSR58_SHIFT (8u) -#define GPIO_PMSR5_PMSR59_SHIFT (9u) -#define GPIO_PMSR5_PMSR510_SHIFT (10u) -#define GPIO_PMSR5_PMSR516_SHIFT (16u) -#define GPIO_PMSR5_PMSR517_SHIFT (17u) -#define GPIO_PMSR5_PMSR518_SHIFT (18u) -#define GPIO_PMSR5_PMSR519_SHIFT (19u) -#define GPIO_PMSR5_PMSR520_SHIFT (20u) -#define GPIO_PMSR5_PMSR521_SHIFT (21u) -#define GPIO_PMSR5_PMSR522_SHIFT (22u) -#define GPIO_PMSR5_PMSR523_SHIFT (23u) -#define GPIO_PMSR5_PMSR524_SHIFT (24u) -#define GPIO_PMSR5_PMSR525_SHIFT (25u) -#define GPIO_PMSR5_PMSR526_SHIFT (26u) - -#define GPIO_PMCSR5_PMCSR50_SHIFT (0u) -#define GPIO_PMCSR5_PMCSR51_SHIFT (1u) -#define GPIO_PMCSR5_PMCSR52_SHIFT (2u) -#define GPIO_PMCSR5_PMCSR53_SHIFT (3u) -#define GPIO_PMCSR5_PMCSR54_SHIFT (4u) -#define GPIO_PMCSR5_PMCSR55_SHIFT (5u) -#define GPIO_PMCSR5_PMCSR56_SHIFT (6u) -#define GPIO_PMCSR5_PMCSR57_SHIFT (7u) -#define GPIO_PMCSR5_PMCSR58_SHIFT (8u) -#define GPIO_PMCSR5_PMCSR59_SHIFT (9u) -#define GPIO_PMCSR5_PMCSR510_SHIFT (10u) -#define GPIO_PMCSR5_PMCSR516_SHIFT (16u) -#define GPIO_PMCSR5_PMCSR517_SHIFT (17u) -#define GPIO_PMCSR5_PMCSR518_SHIFT (18u) -#define GPIO_PMCSR5_PMCSR519_SHIFT (19u) -#define GPIO_PMCSR5_PMCSR520_SHIFT (20u) -#define GPIO_PMCSR5_PMCSR521_SHIFT (21u) -#define GPIO_PMCSR5_PMCSR522_SHIFT (22u) -#define GPIO_PMCSR5_PMCSR523_SHIFT (23u) -#define GPIO_PMCSR5_PMCSR524_SHIFT (24u) -#define GPIO_PMCSR5_PMCSR525_SHIFT (25u) -#define GPIO_PMCSR5_PMCSR526_SHIFT (26u) - -#define GPIO_PFCAE5_PFCAE50_SHIFT (0u) -#define GPIO_PFCAE5_PFCAE51_SHIFT (1u) -#define GPIO_PFCAE5_PFCAE52_SHIFT (2u) -#define GPIO_PFCAE5_PFCAE53_SHIFT (3u) -#define GPIO_PFCAE5_PFCAE54_SHIFT (4u) -#define GPIO_PFCAE5_PFCAE55_SHIFT (5u) -#define GPIO_PFCAE5_PFCAE56_SHIFT (6u) -#define GPIO_PFCAE5_PFCAE57_SHIFT (7u) -#define GPIO_PFCAE5_PFCAE58_SHIFT (8u) -#define GPIO_PFCAE5_PFCAE59_SHIFT (9u) -#define GPIO_PFCAE5_PFCAE510_SHIFT (10u) - -#define GPIO_PIBC5_PIBC50_SHIFT (0u) -#define GPIO_PIBC5_PIBC51_SHIFT (1u) -#define GPIO_PIBC5_PIBC52_SHIFT (2u) -#define GPIO_PIBC5_PIBC53_SHIFT (3u) -#define GPIO_PIBC5_PIBC54_SHIFT (4u) -#define GPIO_PIBC5_PIBC55_SHIFT (5u) -#define GPIO_PIBC5_PIBC56_SHIFT (6u) -#define GPIO_PIBC5_PIBC57_SHIFT (7u) -#define GPIO_PIBC5_PIBC58_SHIFT (8u) -#define GPIO_PIBC5_PIBC59_SHIFT (9u) -#define GPIO_PIBC5_PIBC510_SHIFT (10u) - -#define GPIO_PBDC5_PBDC50_SHIFT (0u) -#define GPIO_PBDC5_PBDC51_SHIFT (1u) -#define GPIO_PBDC5_PBDC52_SHIFT (2u) -#define GPIO_PBDC5_PBDC53_SHIFT (3u) -#define GPIO_PBDC5_PBDC54_SHIFT (4u) -#define GPIO_PBDC5_PBDC55_SHIFT (5u) -#define GPIO_PBDC5_PBDC56_SHIFT (6u) -#define GPIO_PBDC5_PBDC57_SHIFT (7u) -#define GPIO_PBDC5_PBDC58_SHIFT (8u) -#define GPIO_PBDC5_PBDC59_SHIFT (9u) -#define GPIO_PBDC5_PBDC510_SHIFT (10u) - -#define GPIO_PIPC5_PIPC50_SHIFT (0u) -#define GPIO_PIPC5_PIPC51_SHIFT (1u) -#define GPIO_PIPC5_PIPC52_SHIFT (2u) -#define GPIO_PIPC5_PIPC53_SHIFT (3u) -#define GPIO_PIPC5_PIPC54_SHIFT (4u) -#define GPIO_PIPC5_PIPC55_SHIFT (5u) -#define GPIO_PIPC5_PIPC56_SHIFT (6u) -#define GPIO_PIPC5_PIPC57_SHIFT (7u) -#define GPIO_PIPC5_PIPC58_SHIFT (8u) -#define GPIO_PIPC5_PIPC59_SHIFT (9u) -#define GPIO_PIPC5_PIPC510_SHIFT (10u) - -/* ---- P6 ---- */ -#define GPIO_P6_P60_SHIFT (0u) -#define GPIO_P6_P61_SHIFT (1u) -#define GPIO_P6_P62_SHIFT (2u) -#define GPIO_P6_P63_SHIFT (3u) -#define GPIO_P6_P64_SHIFT (4u) -#define GPIO_P6_P65_SHIFT (5u) -#define GPIO_P6_P66_SHIFT (6u) -#define GPIO_P6_P67_SHIFT (7u) -#define GPIO_P6_P68_SHIFT (8u) -#define GPIO_P6_P69_SHIFT (9u) -#define GPIO_P6_P610_SHIFT (10u) -#define GPIO_P6_P611_SHIFT (11u) -#define GPIO_P6_P612_SHIFT (12u) -#define GPIO_P6_P613_SHIFT (13u) -#define GPIO_P6_P614_SHIFT (14u) -#define GPIO_P6_P615_SHIFT (15u) - -#define GPIO_PSR6_PSR60_SHIFT (0u) -#define GPIO_PSR6_PSR61_SHIFT (1u) -#define GPIO_PSR6_PSR62_SHIFT (2u) -#define GPIO_PSR6_PSR63_SHIFT (3u) -#define GPIO_PSR6_PSR64_SHIFT (4u) -#define GPIO_PSR6_PSR65_SHIFT (5u) -#define GPIO_PSR6_PSR66_SHIFT (6u) -#define GPIO_PSR6_PSR67_SHIFT (7u) -#define GPIO_PSR6_PSR68_SHIFT (8u) -#define GPIO_PSR6_PSR69_SHIFT (9u) -#define GPIO_PSR6_PSR610_SHIFT (10u) -#define GPIO_PSR6_PSR611_SHIFT (11u) -#define GPIO_PSR6_PSR612_SHIFT (12u) -#define GPIO_PSR6_PSR613_SHIFT (13u) -#define GPIO_PSR6_PSR614_SHIFT (14u) -#define GPIO_PSR6_PSR615_SHIFT (15u) -#define GPIO_PSR6_PSR616_SHIFT (16u) -#define GPIO_PSR6_PSR617_SHIFT (17u) -#define GPIO_PSR6_PSR618_SHIFT (18u) -#define GPIO_PSR6_PSR619_SHIFT (19u) -#define GPIO_PSR6_PSR620_SHIFT (20u) -#define GPIO_PSR6_PSR621_SHIFT (21u) -#define GPIO_PSR6_PSR622_SHIFT (22u) -#define GPIO_PSR6_PSR623_SHIFT (23u) -#define GPIO_PSR6_PSR624_SHIFT (24u) -#define GPIO_PSR6_PSR625_SHIFT (25u) -#define GPIO_PSR6_PSR626_SHIFT (26u) -#define GPIO_PSR6_PSR627_SHIFT (27u) -#define GPIO_PSR6_PSR628_SHIFT (28u) -#define GPIO_PSR6_PSR629_SHIFT (29u) -#define GPIO_PSR6_PSR630_SHIFT (30u) -#define GPIO_PSR6_PSR631_SHIFT (31u) - -#define GPIO_PPR6_PPR60_SHIFT (0u) -#define GPIO_PPR6_PPR61_SHIFT (1u) -#define GPIO_PPR6_PPR62_SHIFT (2u) -#define GPIO_PPR6_PPR63_SHIFT (3u) -#define GPIO_PPR6_PPR64_SHIFT (4u) -#define GPIO_PPR6_PPR65_SHIFT (5u) -#define GPIO_PPR6_PPR66_SHIFT (6u) -#define GPIO_PPR6_PPR67_SHIFT (7u) -#define GPIO_PPR6_PPR68_SHIFT (8u) -#define GPIO_PPR6_PPR69_SHIFT (9u) -#define GPIO_PPR6_PPR610_SHIFT (10u) -#define GPIO_PPR6_PPR611_SHIFT (11u) -#define GPIO_PPR6_PPR612_SHIFT (12u) -#define GPIO_PPR6_PPR613_SHIFT (13u) -#define GPIO_PPR6_PPR614_SHIFT (14u) -#define GPIO_PPR6_PPR615_SHIFT (15u) - -#define GPIO_PM6_PM60_SHIFT (0u) -#define GPIO_PM6_PM61_SHIFT (1u) -#define GPIO_PM6_PM62_SHIFT (2u) -#define GPIO_PM6_PM63_SHIFT (3u) -#define GPIO_PM6_PM64_SHIFT (4u) -#define GPIO_PM6_PM65_SHIFT (5u) -#define GPIO_PM6_PM66_SHIFT (6u) -#define GPIO_PM6_PM67_SHIFT (7u) -#define GPIO_PM6_PM68_SHIFT (8u) -#define GPIO_PM6_PM69_SHIFT (9u) -#define GPIO_PM6_PM610_SHIFT (10u) -#define GPIO_PM6_PM611_SHIFT (11u) -#define GPIO_PM6_PM612_SHIFT (12u) -#define GPIO_PM6_PM613_SHIFT (13u) -#define GPIO_PM6_PM614_SHIFT (14u) -#define GPIO_PM6_PM615_SHIFT (15u) - -#define GPIO_PMC6_PMC60_SHIFT (0u) -#define GPIO_PMC6_PMC61_SHIFT (1u) -#define GPIO_PMC6_PMC62_SHIFT (2u) -#define GPIO_PMC6_PMC63_SHIFT (3u) -#define GPIO_PMC6_PMC64_SHIFT (4u) -#define GPIO_PMC6_PMC65_SHIFT (5u) -#define GPIO_PMC6_PMC66_SHIFT (6u) -#define GPIO_PMC6_PMC67_SHIFT (7u) -#define GPIO_PMC6_PMC68_SHIFT (8u) -#define GPIO_PMC6_PMC69_SHIFT (9u) -#define GPIO_PMC6_PMC610_SHIFT (10u) -#define GPIO_PMC6_PMC611_SHIFT (11u) -#define GPIO_PMC6_PMC612_SHIFT (12u) -#define GPIO_PMC6_PMC613_SHIFT (13u) -#define GPIO_PMC6_PMC614_SHIFT (14u) -#define GPIO_PMC6_PMC615_SHIFT (15u) - -#define GPIO_PFC6_PFC60_SHIFT (0u) -#define GPIO_PFC6_PFC61_SHIFT (1u) -#define GPIO_PFC6_PFC62_SHIFT (2u) -#define GPIO_PFC6_PFC63_SHIFT (3u) -#define GPIO_PFC6_PFC64_SHIFT (4u) -#define GPIO_PFC6_PFC65_SHIFT (5u) -#define GPIO_PFC6_PFC66_SHIFT (6u) -#define GPIO_PFC6_PFC67_SHIFT (7u) -#define GPIO_PFC6_PFC68_SHIFT (8u) -#define GPIO_PFC6_PFC69_SHIFT (9u) -#define GPIO_PFC6_PFC610_SHIFT (10u) -#define GPIO_PFC6_PFC611_SHIFT (11u) -#define GPIO_PFC6_PFC612_SHIFT (12u) -#define GPIO_PFC6_PFC613_SHIFT (13u) -#define GPIO_PFC6_PFC614_SHIFT (14u) -#define GPIO_PFC6_PFC615_SHIFT (15u) - -#define GPIO_PFCE6_PFCE60_SHIFT (0u) -#define GPIO_PFCE6_PFCE61_SHIFT (1u) -#define GPIO_PFCE6_PFCE62_SHIFT (2u) -#define GPIO_PFCE6_PFCE63_SHIFT (3u) -#define GPIO_PFCE6_PFCE64_SHIFT (4u) -#define GPIO_PFCE6_PFCE65_SHIFT (5u) -#define GPIO_PFCE6_PFCE66_SHIFT (6u) -#define GPIO_PFCE6_PFCE67_SHIFT (7u) -#define GPIO_PFCE6_PFCE68_SHIFT (8u) -#define GPIO_PFCE6_PFCE69_SHIFT (9u) -#define GPIO_PFCE6_PFCE610_SHIFT (10u) -#define GPIO_PFCE6_PFCE611_SHIFT (11u) -#define GPIO_PFCE6_PFCE612_SHIFT (12u) -#define GPIO_PFCE6_PFCE613_SHIFT (13u) -#define GPIO_PFCE6_PFCE614_SHIFT (14u) -#define GPIO_PFCE6_PFCE615_SHIFT (15u) - -#define GPIO_PNOT6_PNOT60_SHIFT (0u) -#define GPIO_PNOT6_PNOT61_SHIFT (1u) -#define GPIO_PNOT6_PNOT62_SHIFT (2u) -#define GPIO_PNOT6_PNOT63_SHIFT (3u) -#define GPIO_PNOT6_PNOT64_SHIFT (4u) -#define GPIO_PNOT6_PNOT65_SHIFT (5u) -#define GPIO_PNOT6_PNOT66_SHIFT (6u) -#define GPIO_PNOT6_PNOT67_SHIFT (7u) -#define GPIO_PNOT6_PNOT68_SHIFT (8u) -#define GPIO_PNOT6_PNOT69_SHIFT (9u) -#define GPIO_PNOT6_PNOT610_SHIFT (10u) -#define GPIO_PNOT6_PNOT611_SHIFT (11u) -#define GPIO_PNOT6_PNOT612_SHIFT (12u) -#define GPIO_PNOT6_PNOT613_SHIFT (13u) -#define GPIO_PNOT6_PNOT614_SHIFT (14u) -#define GPIO_PNOT6_PNOT615_SHIFT (15u) - -#define GPIO_PMSR6_PMSR60_SHIFT (0u) -#define GPIO_PMSR6_PMSR61_SHIFT (1u) -#define GPIO_PMSR6_PMSR62_SHIFT (2u) -#define GPIO_PMSR6_PMSR63_SHIFT (3u) -#define GPIO_PMSR6_PMSR64_SHIFT (4u) -#define GPIO_PMSR6_PMSR65_SHIFT (5u) -#define GPIO_PMSR6_PMSR66_SHIFT (6u) -#define GPIO_PMSR6_PMSR67_SHIFT (7u) -#define GPIO_PMSR6_PMSR68_SHIFT (8u) -#define GPIO_PMSR6_PMSR69_SHIFT (9u) -#define GPIO_PMSR6_PMSR610_SHIFT (10u) -#define GPIO_PMSR6_PMSR611_SHIFT (11u) -#define GPIO_PMSR6_PMSR612_SHIFT (12u) -#define GPIO_PMSR6_PMSR613_SHIFT (13u) -#define GPIO_PMSR6_PMSR614_SHIFT (14u) -#define GPIO_PMSR6_PMSR615_SHIFT (15u) -#define GPIO_PMSR6_PMSR616_SHIFT (16u) -#define GPIO_PMSR6_PMSR617_SHIFT (17u) -#define GPIO_PMSR6_PMSR618_SHIFT (18u) -#define GPIO_PMSR6_PMSR619_SHIFT (19u) -#define GPIO_PMSR6_PMSR620_SHIFT (20u) -#define GPIO_PMSR6_PMSR621_SHIFT (21u) -#define GPIO_PMSR6_PMSR622_SHIFT (22u) -#define GPIO_PMSR6_PMSR623_SHIFT (23u) -#define GPIO_PMSR6_PMSR624_SHIFT (24u) -#define GPIO_PMSR6_PMSR625_SHIFT (25u) -#define GPIO_PMSR6_PMSR626_SHIFT (26u) -#define GPIO_PMSR6_PMSR627_SHIFT (27u) -#define GPIO_PMSR6_PMSR628_SHIFT (28u) -#define GPIO_PMSR6_PMSR629_SHIFT (29u) -#define GPIO_PMSR6_PMSR630_SHIFT (30u) -#define GPIO_PMSR6_PMSR631_SHIFT (31u) - -#define GPIO_PMCSR6_PMCSR60_SHIFT (0u) -#define GPIO_PMCSR6_PMCSR61_SHIFT (1u) -#define GPIO_PMCSR6_PMCSR62_SHIFT (2u) -#define GPIO_PMCSR6_PMCSR63_SHIFT (3u) -#define GPIO_PMCSR6_PMCSR64_SHIFT (4u) -#define GPIO_PMCSR6_PMCSR65_SHIFT (5u) -#define GPIO_PMCSR6_PMCSR66_SHIFT (6u) -#define GPIO_PMCSR6_PMCSR67_SHIFT (7u) -#define GPIO_PMCSR6_PMCSR68_SHIFT (8u) -#define GPIO_PMCSR6_PMCSR69_SHIFT (9u) -#define GPIO_PMCSR6_PMCSR610_SHIFT (10u) -#define GPIO_PMCSR6_PMCSR611_SHIFT (11u) -#define GPIO_PMCSR6_PMCSR612_SHIFT (12u) -#define GPIO_PMCSR6_PMCSR613_SHIFT (13u) -#define GPIO_PMCSR6_PMCSR614_SHIFT (14u) -#define GPIO_PMCSR6_PMCSR615_SHIFT (15u) -#define GPIO_PMCSR6_PMCSR616_SHIFT (16u) -#define GPIO_PMCSR6_PMCSR617_SHIFT (17u) -#define GPIO_PMCSR6_PMCSR618_SHIFT (18u) -#define GPIO_PMCSR6_PMCSR619_SHIFT (19u) -#define GPIO_PMCSR6_PMCSR620_SHIFT (20u) -#define GPIO_PMCSR6_PMCSR621_SHIFT (21u) -#define GPIO_PMCSR6_PMCSR622_SHIFT (22u) -#define GPIO_PMCSR6_PMCSR623_SHIFT (23u) -#define GPIO_PMCSR6_PMCSR624_SHIFT (24u) -#define GPIO_PMCSR6_PMCSR625_SHIFT (25u) -#define GPIO_PMCSR6_PMCSR626_SHIFT (26u) -#define GPIO_PMCSR6_PMCSR627_SHIFT (27u) -#define GPIO_PMCSR6_PMCSR628_SHIFT (28u) -#define GPIO_PMCSR6_PMCSR629_SHIFT (29u) -#define GPIO_PMCSR6_PMCSR630_SHIFT (30u) -#define GPIO_PMCSR6_PMCSR631_SHIFT (31u) - -#define GPIO_PFCAE6_PFCAE60_SHIFT (0u) -#define GPIO_PFCAE6_PFCAE61_SHIFT (1u) -#define GPIO_PFCAE6_PFCAE62_SHIFT (2u) -#define GPIO_PFCAE6_PFCAE63_SHIFT (3u) -#define GPIO_PFCAE6_PFCAE64_SHIFT (4u) -#define GPIO_PFCAE6_PFCAE65_SHIFT (5u) -#define GPIO_PFCAE6_PFCAE66_SHIFT (6u) -#define GPIO_PFCAE6_PFCAE67_SHIFT (7u) -#define GPIO_PFCAE6_PFCAE68_SHIFT (8u) -#define GPIO_PFCAE6_PFCAE69_SHIFT (9u) -#define GPIO_PFCAE6_PFCAE610_SHIFT (10u) -#define GPIO_PFCAE6_PFCAE611_SHIFT (11u) -#define GPIO_PFCAE6_PFCAE612_SHIFT (12u) -#define GPIO_PFCAE6_PFCAE613_SHIFT (13u) -#define GPIO_PFCAE6_PFCAE614_SHIFT (14u) -#define GPIO_PFCAE6_PFCAE615_SHIFT (15u) - -#define GPIO_PIBC6_PIBC60_SHIFT (0u) -#define GPIO_PIBC6_PIBC61_SHIFT (1u) -#define GPIO_PIBC6_PIBC62_SHIFT (2u) -#define GPIO_PIBC6_PIBC63_SHIFT (3u) -#define GPIO_PIBC6_PIBC64_SHIFT (4u) -#define GPIO_PIBC6_PIBC65_SHIFT (5u) -#define GPIO_PIBC6_PIBC66_SHIFT (6u) -#define GPIO_PIBC6_PIBC67_SHIFT (7u) -#define GPIO_PIBC6_PIBC68_SHIFT (8u) -#define GPIO_PIBC6_PIBC69_SHIFT (9u) -#define GPIO_PIBC6_PIBC610_SHIFT (10u) -#define GPIO_PIBC6_PIBC611_SHIFT (11u) -#define GPIO_PIBC6_PIBC612_SHIFT (12u) -#define GPIO_PIBC6_PIBC613_SHIFT (13u) -#define GPIO_PIBC6_PIBC614_SHIFT (14u) -#define GPIO_PIBC6_PIBC615_SHIFT (15u) - -#define GPIO_PBDC6_PBDC60_SHIFT (0u) -#define GPIO_PBDC6_PBDC61_SHIFT (1u) -#define GPIO_PBDC6_PBDC62_SHIFT (2u) -#define GPIO_PBDC6_PBDC63_SHIFT (3u) -#define GPIO_PBDC6_PBDC64_SHIFT (4u) -#define GPIO_PBDC6_PBDC65_SHIFT (5u) -#define GPIO_PBDC6_PBDC66_SHIFT (6u) -#define GPIO_PBDC6_PBDC67_SHIFT (7u) -#define GPIO_PBDC6_PBDC68_SHIFT (8u) -#define GPIO_PBDC6_PBDC69_SHIFT (9u) -#define GPIO_PBDC6_PBDC610_SHIFT (10u) -#define GPIO_PBDC6_PBDC611_SHIFT (11u) -#define GPIO_PBDC6_PBDC612_SHIFT (12u) -#define GPIO_PBDC6_PBDC613_SHIFT (13u) -#define GPIO_PBDC6_PBDC614_SHIFT (14u) -#define GPIO_PBDC6_PBDC615_SHIFT (15u) - -#define GPIO_PIPC6_PIPC60_SHIFT (0u) -#define GPIO_PIPC6_PIPC61_SHIFT (1u) -#define GPIO_PIPC6_PIPC62_SHIFT (2u) -#define GPIO_PIPC6_PIPC63_SHIFT (3u) -#define GPIO_PIPC6_PIPC64_SHIFT (4u) -#define GPIO_PIPC6_PIPC65_SHIFT (5u) -#define GPIO_PIPC6_PIPC66_SHIFT (6u) -#define GPIO_PIPC6_PIPC67_SHIFT (7u) -#define GPIO_PIPC6_PIPC68_SHIFT (8u) -#define GPIO_PIPC6_PIPC69_SHIFT (9u) -#define GPIO_PIPC6_PIPC610_SHIFT (10u) -#define GPIO_PIPC6_PIPC611_SHIFT (11u) -#define GPIO_PIPC6_PIPC612_SHIFT (12u) -#define GPIO_PIPC6_PIPC613_SHIFT (13u) -#define GPIO_PIPC6_PIPC614_SHIFT (14u) -#define GPIO_PIPC6_PIPC615_SHIFT (15u) - -/* ---- P7 ---- */ -#define GPIO_P7_P70_SHIFT (0u) -#define GPIO_P7_P71_SHIFT (1u) -#define GPIO_P7_P72_SHIFT (2u) -#define GPIO_P7_P73_SHIFT (3u) -#define GPIO_P7_P74_SHIFT (4u) -#define GPIO_P7_P75_SHIFT (5u) -#define GPIO_P7_P76_SHIFT (6u) -#define GPIO_P7_P77_SHIFT (7u) -#define GPIO_P7_P78_SHIFT (8u) -#define GPIO_P7_P79_SHIFT (9u) -#define GPIO_P7_P710_SHIFT (10u) -#define GPIO_P7_P711_SHIFT (11u) -#define GPIO_P7_P712_SHIFT (12u) -#define GPIO_P7_P713_SHIFT (13u) -#define GPIO_P7_P714_SHIFT (14u) -#define GPIO_P7_P715_SHIFT (15u) - -#define GPIO_PSR7_PSR70_SHIFT (0u) -#define GPIO_PSR7_PSR71_SHIFT (1u) -#define GPIO_PSR7_PSR72_SHIFT (2u) -#define GPIO_PSR7_PSR73_SHIFT (3u) -#define GPIO_PSR7_PSR74_SHIFT (4u) -#define GPIO_PSR7_PSR75_SHIFT (5u) -#define GPIO_PSR7_PSR76_SHIFT (6u) -#define GPIO_PSR7_PSR77_SHIFT (7u) -#define GPIO_PSR7_PSR78_SHIFT (8u) -#define GPIO_PSR7_PSR79_SHIFT (9u) -#define GPIO_PSR7_PSR710_SHIFT (10u) -#define GPIO_PSR7_PSR711_SHIFT (11u) -#define GPIO_PSR7_PSR712_SHIFT (12u) -#define GPIO_PSR7_PSR713_SHIFT (13u) -#define GPIO_PSR7_PSR714_SHIFT (14u) -#define GPIO_PSR7_PSR715_SHIFT (15u) -#define GPIO_PSR7_PSR716_SHIFT (16u) -#define GPIO_PSR7_PSR717_SHIFT (17u) -#define GPIO_PSR7_PSR718_SHIFT (18u) -#define GPIO_PSR7_PSR719_SHIFT (19u) -#define GPIO_PSR7_PSR720_SHIFT (20u) -#define GPIO_PSR7_PSR721_SHIFT (21u) -#define GPIO_PSR7_PSR722_SHIFT (22u) -#define GPIO_PSR7_PSR723_SHIFT (23u) -#define GPIO_PSR7_PSR724_SHIFT (24u) -#define GPIO_PSR7_PSR725_SHIFT (25u) -#define GPIO_PSR7_PSR726_SHIFT (26u) -#define GPIO_PSR7_PSR727_SHIFT (27u) -#define GPIO_PSR7_PSR728_SHIFT (28u) -#define GPIO_PSR7_PSR729_SHIFT (29u) -#define GPIO_PSR7_PSR730_SHIFT (30u) -#define GPIO_PSR7_PSR731_SHIFT (31u) - -#define GPIO_PPR7_PPR70_SHIFT (0u) -#define GPIO_PPR7_PPR71_SHIFT (1u) -#define GPIO_PPR7_PPR72_SHIFT (2u) -#define GPIO_PPR7_PPR73_SHIFT (3u) -#define GPIO_PPR7_PPR74_SHIFT (4u) -#define GPIO_PPR7_PPR75_SHIFT (5u) -#define GPIO_PPR7_PPR76_SHIFT (6u) -#define GPIO_PPR7_PPR77_SHIFT (7u) -#define GPIO_PPR7_PPR78_SHIFT (8u) -#define GPIO_PPR7_PPR79_SHIFT (9u) -#define GPIO_PPR7_PPR710_SHIFT (10u) -#define GPIO_PPR7_PPR711_SHIFT (11u) -#define GPIO_PPR7_PPR712_SHIFT (12u) -#define GPIO_PPR7_PPR713_SHIFT (13u) -#define GPIO_PPR7_PPR714_SHIFT (14u) -#define GPIO_PPR7_PPR715_SHIFT (15u) - -#define GPIO_PM7_PM70_SHIFT (0u) -#define GPIO_PM7_PM71_SHIFT (1u) -#define GPIO_PM7_PM72_SHIFT (2u) -#define GPIO_PM7_PM73_SHIFT (3u) -#define GPIO_PM7_PM74_SHIFT (4u) -#define GPIO_PM7_PM75_SHIFT (5u) -#define GPIO_PM7_PM76_SHIFT (6u) -#define GPIO_PM7_PM77_SHIFT (7u) -#define GPIO_PM7_PM78_SHIFT (8u) -#define GPIO_PM7_PM79_SHIFT (9u) -#define GPIO_PM7_PM710_SHIFT (10u) -#define GPIO_PM7_PM711_SHIFT (11u) -#define GPIO_PM7_PM712_SHIFT (12u) -#define GPIO_PM7_PM713_SHIFT (13u) -#define GPIO_PM7_PM714_SHIFT (14u) -#define GPIO_PM7_PM715_SHIFT (15u) - -#define GPIO_PMC7_PMC70_SHIFT (0u) -#define GPIO_PMC7_PMC71_SHIFT (1u) -#define GPIO_PMC7_PMC72_SHIFT (2u) -#define GPIO_PMC7_PMC73_SHIFT (3u) -#define GPIO_PMC7_PMC74_SHIFT (4u) -#define GPIO_PMC7_PMC75_SHIFT (5u) -#define GPIO_PMC7_PMC76_SHIFT (6u) -#define GPIO_PMC7_PMC77_SHIFT (7u) -#define GPIO_PMC7_PMC78_SHIFT (8u) -#define GPIO_PMC7_PMC79_SHIFT (9u) -#define GPIO_PMC7_PMC710_SHIFT (10u) -#define GPIO_PMC7_PMC711_SHIFT (11u) -#define GPIO_PMC7_PMC712_SHIFT (12u) -#define GPIO_PMC7_PMC713_SHIFT (13u) -#define GPIO_PMC7_PMC714_SHIFT (14u) -#define GPIO_PMC7_PMC715_SHIFT (15u) - -#define GPIO_PFC7_PFC70_SHIFT (0u) -#define GPIO_PFC7_PFC71_SHIFT (1u) -#define GPIO_PFC7_PFC72_SHIFT (2u) -#define GPIO_PFC7_PFC73_SHIFT (3u) -#define GPIO_PFC7_PFC74_SHIFT (4u) -#define GPIO_PFC7_PFC75_SHIFT (5u) -#define GPIO_PFC7_PFC76_SHIFT (6u) -#define GPIO_PFC7_PFC77_SHIFT (7u) -#define GPIO_PFC7_PFC78_SHIFT (8u) -#define GPIO_PFC7_PFC79_SHIFT (9u) -#define GPIO_PFC7_PFC710_SHIFT (10u) -#define GPIO_PFC7_PFC711_SHIFT (11u) -#define GPIO_PFC7_PFC712_SHIFT (12u) -#define GPIO_PFC7_PFC713_SHIFT (13u) -#define GPIO_PFC7_PFC714_SHIFT (14u) -#define GPIO_PFC7_PFC715_SHIFT (15u) - -#define GPIO_PFCE7_PFCE70_SHIFT (0u) -#define GPIO_PFCE7_PFCE71_SHIFT (1u) -#define GPIO_PFCE7_PFCE72_SHIFT (2u) -#define GPIO_PFCE7_PFCE73_SHIFT (3u) -#define GPIO_PFCE7_PFCE74_SHIFT (4u) -#define GPIO_PFCE7_PFCE75_SHIFT (5u) -#define GPIO_PFCE7_PFCE76_SHIFT (6u) -#define GPIO_PFCE7_PFCE77_SHIFT (7u) -#define GPIO_PFCE7_PFCE78_SHIFT (8u) -#define GPIO_PFCE7_PFCE79_SHIFT (9u) -#define GPIO_PFCE7_PFCE710_SHIFT (10u) -#define GPIO_PFCE7_PFCE711_SHIFT (11u) -#define GPIO_PFCE7_PFCE712_SHIFT (12u) -#define GPIO_PFCE7_PFCE713_SHIFT (13u) -#define GPIO_PFCE7_PFCE714_SHIFT (14u) -#define GPIO_PFCE7_PFCE715_SHIFT (15u) - -#define GPIO_PNOT7_PNOT70_SHIFT (0u) -#define GPIO_PNOT7_PNOT71_SHIFT (1u) -#define GPIO_PNOT7_PNOT72_SHIFT (2u) -#define GPIO_PNOT7_PNOT73_SHIFT (3u) -#define GPIO_PNOT7_PNOT74_SHIFT (4u) -#define GPIO_PNOT7_PNOT75_SHIFT (5u) -#define GPIO_PNOT7_PNOT76_SHIFT (6u) -#define GPIO_PNOT7_PNOT77_SHIFT (7u) -#define GPIO_PNOT7_PNOT78_SHIFT (8u) -#define GPIO_PNOT7_PNOT79_SHIFT (9u) -#define GPIO_PNOT7_PNOT710_SHIFT (10u) -#define GPIO_PNOT7_PNOT711_SHIFT (11u) -#define GPIO_PNOT7_PNOT712_SHIFT (12u) -#define GPIO_PNOT7_PNOT713_SHIFT (13u) -#define GPIO_PNOT7_PNOT714_SHIFT (14u) -#define GPIO_PNOT7_PNOT715_SHIFT (15u) - -#define GPIO_PMSR7_PMSR70_SHIFT (0u) -#define GPIO_PMSR7_PMSR71_SHIFT (1u) -#define GPIO_PMSR7_PMSR72_SHIFT (2u) -#define GPIO_PMSR7_PMSR73_SHIFT (3u) -#define GPIO_PMSR7_PMSR74_SHIFT (4u) -#define GPIO_PMSR7_PMSR75_SHIFT (5u) -#define GPIO_PMSR7_PMSR76_SHIFT (6u) -#define GPIO_PMSR7_PMSR77_SHIFT (7u) -#define GPIO_PMSR7_PMSR78_SHIFT (8u) -#define GPIO_PMSR7_PMSR79_SHIFT (9u) -#define GPIO_PMSR7_PMSR710_SHIFT (10u) -#define GPIO_PMSR7_PMSR711_SHIFT (11u) -#define GPIO_PMSR7_PMSR712_SHIFT (12u) -#define GPIO_PMSR7_PMSR713_SHIFT (13u) -#define GPIO_PMSR7_PMSR714_SHIFT (14u) -#define GPIO_PMSR7_PMSR715_SHIFT (15u) -#define GPIO_PMSR7_PMSR716_SHIFT (16u) -#define GPIO_PMSR7_PMSR717_SHIFT (17u) -#define GPIO_PMSR7_PMSR718_SHIFT (18u) -#define GPIO_PMSR7_PMSR719_SHIFT (19u) -#define GPIO_PMSR7_PMSR720_SHIFT (20u) -#define GPIO_PMSR7_PMSR721_SHIFT (21u) -#define GPIO_PMSR7_PMSR722_SHIFT (22u) -#define GPIO_PMSR7_PMSR723_SHIFT (23u) -#define GPIO_PMSR7_PMSR724_SHIFT (24u) -#define GPIO_PMSR7_PMSR725_SHIFT (25u) -#define GPIO_PMSR7_PMSR726_SHIFT (26u) -#define GPIO_PMSR7_PMSR727_SHIFT (27u) -#define GPIO_PMSR7_PMSR728_SHIFT (28u) -#define GPIO_PMSR7_PMSR729_SHIFT (29u) -#define GPIO_PMSR7_PMSR730_SHIFT (30u) -#define GPIO_PMSR7_PMSR731_SHIFT (31u) - -#define GPIO_PMCSR7_PMCSR70_SHIFT (0u) -#define GPIO_PMCSR7_PMCSR71_SHIFT (1u) -#define GPIO_PMCSR7_PMCSR72_SHIFT (2u) -#define GPIO_PMCSR7_PMCSR73_SHIFT (3u) -#define GPIO_PMCSR7_PMCSR74_SHIFT (4u) -#define GPIO_PMCSR7_PMCSR75_SHIFT (5u) -#define GPIO_PMCSR7_PMCSR76_SHIFT (6u) -#define GPIO_PMCSR7_PMCSR77_SHIFT (7u) -#define GPIO_PMCSR7_PMCSR78_SHIFT (8u) -#define GPIO_PMCSR7_PMCSR79_SHIFT (9u) -#define GPIO_PMCSR7_PMCSR710_SHIFT (10u) -#define GPIO_PMCSR7_PMCSR711_SHIFT (11u) -#define GPIO_PMCSR7_PMCSR712_SHIFT (12u) -#define GPIO_PMCSR7_PMCSR713_SHIFT (13u) -#define GPIO_PMCSR7_PMCSR714_SHIFT (14u) -#define GPIO_PMCSR7_PMCSR715_SHIFT (15u) -#define GPIO_PMCSR7_PMCSR716_SHIFT (16u) -#define GPIO_PMCSR7_PMCSR717_SHIFT (17u) -#define GPIO_PMCSR7_PMCSR718_SHIFT (18u) -#define GPIO_PMCSR7_PMCSR719_SHIFT (19u) -#define GPIO_PMCSR7_PMCSR720_SHIFT (20u) -#define GPIO_PMCSR7_PMCSR721_SHIFT (21u) -#define GPIO_PMCSR7_PMCSR722_SHIFT (22u) -#define GPIO_PMCSR7_PMCSR723_SHIFT (23u) -#define GPIO_PMCSR7_PMCSR724_SHIFT (24u) -#define GPIO_PMCSR7_PMCSR725_SHIFT (25u) -#define GPIO_PMCSR7_PMCSR726_SHIFT (26u) -#define GPIO_PMCSR7_PMCSR727_SHIFT (27u) -#define GPIO_PMCSR7_PMCSR728_SHIFT (28u) -#define GPIO_PMCSR7_PMCSR729_SHIFT (29u) -#define GPIO_PMCSR7_PMCSR730_SHIFT (30u) -#define GPIO_PMCSR7_PMCSR731_SHIFT (31u) - -#define GPIO_PFCAE7_PFCAE70_SHIFT (0u) -#define GPIO_PFCAE7_PFCAE71_SHIFT (1u) -#define GPIO_PFCAE7_PFCAE72_SHIFT (2u) -#define GPIO_PFCAE7_PFCAE73_SHIFT (3u) -#define GPIO_PFCAE7_PFCAE74_SHIFT (4u) -#define GPIO_PFCAE7_PFCAE75_SHIFT (5u) -#define GPIO_PFCAE7_PFCAE76_SHIFT (6u) -#define GPIO_PFCAE7_PFCAE77_SHIFT (7u) -#define GPIO_PFCAE7_PFCAE78_SHIFT (8u) -#define GPIO_PFCAE7_PFCAE79_SHIFT (9u) -#define GPIO_PFCAE7_PFCAE710_SHIFT (10u) -#define GPIO_PFCAE7_PFCAE711_SHIFT (11u) -#define GPIO_PFCAE7_PFCAE712_SHIFT (12u) -#define GPIO_PFCAE7_PFCAE713_SHIFT (13u) -#define GPIO_PFCAE7_PFCAE714_SHIFT (14u) -#define GPIO_PFCAE7_PFCAE715_SHIFT (15u) - -#define GPIO_PIBC7_PIBC70_SHIFT (0u) -#define GPIO_PIBC7_PIBC71_SHIFT (1u) -#define GPIO_PIBC7_PIBC72_SHIFT (2u) -#define GPIO_PIBC7_PIBC73_SHIFT (3u) -#define GPIO_PIBC7_PIBC74_SHIFT (4u) -#define GPIO_PIBC7_PIBC75_SHIFT (5u) -#define GPIO_PIBC7_PIBC76_SHIFT (6u) -#define GPIO_PIBC7_PIBC77_SHIFT (7u) -#define GPIO_PIBC7_PIBC78_SHIFT (8u) -#define GPIO_PIBC7_PIBC79_SHIFT (9u) -#define GPIO_PIBC7_PIBC710_SHIFT (10u) -#define GPIO_PIBC7_PIBC711_SHIFT (11u) -#define GPIO_PIBC7_PIBC712_SHIFT (12u) -#define GPIO_PIBC7_PIBC713_SHIFT (13u) -#define GPIO_PIBC7_PIBC714_SHIFT (14u) -#define GPIO_PIBC7_PIBC715_SHIFT (15u) - -#define GPIO_PBDC7_PBDC70_SHIFT (0u) -#define GPIO_PBDC7_PBDC71_SHIFT (1u) -#define GPIO_PBDC7_PBDC72_SHIFT (2u) -#define GPIO_PBDC7_PBDC73_SHIFT (3u) -#define GPIO_PBDC7_PBDC74_SHIFT (4u) -#define GPIO_PBDC7_PBDC75_SHIFT (5u) -#define GPIO_PBDC7_PBDC76_SHIFT (6u) -#define GPIO_PBDC7_PBDC77_SHIFT (7u) -#define GPIO_PBDC7_PBDC78_SHIFT (8u) -#define GPIO_PBDC7_PBDC79_SHIFT (9u) -#define GPIO_PBDC7_PBDC710_SHIFT (10u) -#define GPIO_PBDC7_PBDC711_SHIFT (11u) -#define GPIO_PBDC7_PBDC712_SHIFT (12u) -#define GPIO_PBDC7_PBDC713_SHIFT (13u) -#define GPIO_PBDC7_PBDC714_SHIFT (14u) -#define GPIO_PBDC7_PBDC715_SHIFT (15u) - -#define GPIO_PIPC7_PIPC70_SHIFT (0u) -#define GPIO_PIPC7_PIPC71_SHIFT (1u) -#define GPIO_PIPC7_PIPC72_SHIFT (2u) -#define GPIO_PIPC7_PIPC73_SHIFT (3u) -#define GPIO_PIPC7_PIPC74_SHIFT (4u) -#define GPIO_PIPC7_PIPC75_SHIFT (5u) -#define GPIO_PIPC7_PIPC76_SHIFT (6u) -#define GPIO_PIPC7_PIPC77_SHIFT (7u) -#define GPIO_PIPC7_PIPC78_SHIFT (8u) -#define GPIO_PIPC7_PIPC79_SHIFT (9u) -#define GPIO_PIPC7_PIPC710_SHIFT (10u) -#define GPIO_PIPC7_PIPC711_SHIFT (11u) -#define GPIO_PIPC7_PIPC712_SHIFT (12u) -#define GPIO_PIPC7_PIPC713_SHIFT (13u) -#define GPIO_PIPC7_PIPC714_SHIFT (14u) -#define GPIO_PIPC7_PIPC715_SHIFT (15u) - -/* ---- P8 ---- */ -#define GPIO_P8_P80_SHIFT (0u) -#define GPIO_P8_P81_SHIFT (1u) -#define GPIO_P8_P82_SHIFT (2u) -#define GPIO_P8_P83_SHIFT (3u) -#define GPIO_P8_P84_SHIFT (4u) -#define GPIO_P8_P85_SHIFT (5u) -#define GPIO_P8_P86_SHIFT (6u) -#define GPIO_P8_P87_SHIFT (7u) -#define GPIO_P8_P88_SHIFT (8u) -#define GPIO_P8_P89_SHIFT (9u) -#define GPIO_P8_P810_SHIFT (10u) -#define GPIO_P8_P811_SHIFT (11u) -#define GPIO_P8_P812_SHIFT (12u) -#define GPIO_P8_P813_SHIFT (13u) -#define GPIO_P8_P814_SHIFT (14u) -#define GPIO_P8_P815_SHIFT (15u) - -#define GPIO_PSR8_PSR80_SHIFT (0u) -#define GPIO_PSR8_PSR81_SHIFT (1u) -#define GPIO_PSR8_PSR82_SHIFT (2u) -#define GPIO_PSR8_PSR83_SHIFT (3u) -#define GPIO_PSR8_PSR84_SHIFT (4u) -#define GPIO_PSR8_PSR85_SHIFT (5u) -#define GPIO_PSR8_PSR86_SHIFT (6u) -#define GPIO_PSR8_PSR87_SHIFT (7u) -#define GPIO_PSR8_PSR88_SHIFT (8u) -#define GPIO_PSR8_PSR89_SHIFT (9u) -#define GPIO_PSR8_PSR810_SHIFT (10u) -#define GPIO_PSR8_PSR811_SHIFT (11u) -#define GPIO_PSR8_PSR812_SHIFT (12u) -#define GPIO_PSR8_PSR813_SHIFT (13u) -#define GPIO_PSR8_PSR814_SHIFT (14u) -#define GPIO_PSR8_PSR815_SHIFT (15u) -#define GPIO_PSR8_PSR816_SHIFT (16u) -#define GPIO_PSR8_PSR817_SHIFT (17u) -#define GPIO_PSR8_PSR818_SHIFT (18u) -#define GPIO_PSR8_PSR819_SHIFT (19u) -#define GPIO_PSR8_PSR820_SHIFT (20u) -#define GPIO_PSR8_PSR821_SHIFT (21u) -#define GPIO_PSR8_PSR822_SHIFT (22u) -#define GPIO_PSR8_PSR823_SHIFT (23u) -#define GPIO_PSR8_PSR824_SHIFT (24u) -#define GPIO_PSR8_PSR825_SHIFT (25u) -#define GPIO_PSR8_PSR826_SHIFT (26u) -#define GPIO_PSR8_PSR827_SHIFT (27u) -#define GPIO_PSR8_PSR828_SHIFT (28u) -#define GPIO_PSR8_PSR829_SHIFT (29u) -#define GPIO_PSR8_PSR830_SHIFT (30u) -#define GPIO_PSR8_PSR831_SHIFT (31u) - -#define GPIO_PPR8_PPR80_SHIFT (0u) -#define GPIO_PPR8_PPR81_SHIFT (1u) -#define GPIO_PPR8_PPR82_SHIFT (2u) -#define GPIO_PPR8_PPR83_SHIFT (3u) -#define GPIO_PPR8_PPR84_SHIFT (4u) -#define GPIO_PPR8_PPR85_SHIFT (5u) -#define GPIO_PPR8_PPR86_SHIFT (6u) -#define GPIO_PPR8_PPR87_SHIFT (7u) -#define GPIO_PPR8_PPR88_SHIFT (8u) -#define GPIO_PPR8_PPR89_SHIFT (9u) -#define GPIO_PPR8_PPR810_SHIFT (10u) -#define GPIO_PPR8_PPR811_SHIFT (11u) -#define GPIO_PPR8_PPR812_SHIFT (12u) -#define GPIO_PPR8_PPR813_SHIFT (13u) -#define GPIO_PPR8_PPR814_SHIFT (14u) -#define GPIO_PPR8_PPR815_SHIFT (15u) - -#define GPIO_PM8_PM80_SHIFT (0u) -#define GPIO_PM8_PM81_SHIFT (1u) -#define GPIO_PM8_PM82_SHIFT (2u) -#define GPIO_PM8_PM83_SHIFT (3u) -#define GPIO_PM8_PM84_SHIFT (4u) -#define GPIO_PM8_PM85_SHIFT (5u) -#define GPIO_PM8_PM86_SHIFT (6u) -#define GPIO_PM8_PM87_SHIFT (7u) -#define GPIO_PM8_PM88_SHIFT (8u) -#define GPIO_PM8_PM89_SHIFT (9u) -#define GPIO_PM8_PM810_SHIFT (10u) -#define GPIO_PM8_PM811_SHIFT (11u) -#define GPIO_PM8_PM812_SHIFT (12u) -#define GPIO_PM8_PM813_SHIFT (13u) -#define GPIO_PM8_PM814_SHIFT (14u) -#define GPIO_PM8_PM815_SHIFT (15u) - -#define GPIO_PMC8_PMC80_SHIFT (0u) -#define GPIO_PMC8_PMC81_SHIFT (1u) -#define GPIO_PMC8_PMC82_SHIFT (2u) -#define GPIO_PMC8_PMC83_SHIFT (3u) -#define GPIO_PMC8_PMC84_SHIFT (4u) -#define GPIO_PMC8_PMC85_SHIFT (5u) -#define GPIO_PMC8_PMC86_SHIFT (6u) -#define GPIO_PMC8_PMC87_SHIFT (7u) -#define GPIO_PMC8_PMC88_SHIFT (8u) -#define GPIO_PMC8_PMC89_SHIFT (9u) -#define GPIO_PMC8_PMC810_SHIFT (10u) -#define GPIO_PMC8_PMC811_SHIFT (11u) -#define GPIO_PMC8_PMC812_SHIFT (12u) -#define GPIO_PMC8_PMC813_SHIFT (13u) -#define GPIO_PMC8_PMC814_SHIFT (14u) -#define GPIO_PMC8_PMC815_SHIFT (15u) - -#define GPIO_PFC8_PFC80_SHIFT (0u) -#define GPIO_PFC8_PFC81_SHIFT (1u) -#define GPIO_PFC8_PFC82_SHIFT (2u) -#define GPIO_PFC8_PFC83_SHIFT (3u) -#define GPIO_PFC8_PFC84_SHIFT (4u) -#define GPIO_PFC8_PFC85_SHIFT (5u) -#define GPIO_PFC8_PFC86_SHIFT (6u) -#define GPIO_PFC8_PFC87_SHIFT (7u) -#define GPIO_PFC8_PFC88_SHIFT (8u) -#define GPIO_PFC8_PFC89_SHIFT (9u) -#define GPIO_PFC8_PFC810_SHIFT (10u) -#define GPIO_PFC8_PFC811_SHIFT (11u) -#define GPIO_PFC8_PFC812_SHIFT (12u) -#define GPIO_PFC8_PFC813_SHIFT (13u) -#define GPIO_PFC8_PFC814_SHIFT (14u) -#define GPIO_PFC8_PFC815_SHIFT (15u) - -#define GPIO_PFCE8_PFCE80_SHIFT (0u) -#define GPIO_PFCE8_PFCE81_SHIFT (1u) -#define GPIO_PFCE8_PFCE82_SHIFT (2u) -#define GPIO_PFCE8_PFCE83_SHIFT (3u) -#define GPIO_PFCE8_PFCE84_SHIFT (4u) -#define GPIO_PFCE8_PFCE85_SHIFT (5u) -#define GPIO_PFCE8_PFCE86_SHIFT (6u) -#define GPIO_PFCE8_PFCE87_SHIFT (7u) -#define GPIO_PFCE8_PFCE88_SHIFT (8u) -#define GPIO_PFCE8_PFCE89_SHIFT (9u) -#define GPIO_PFCE8_PFCE810_SHIFT (10u) -#define GPIO_PFCE8_PFCE811_SHIFT (11u) -#define GPIO_PFCE8_PFCE812_SHIFT (12u) -#define GPIO_PFCE8_PFCE813_SHIFT (13u) -#define GPIO_PFCE8_PFCE814_SHIFT (14u) -#define GPIO_PFCE8_PFCE815_SHIFT (15u) - -#define GPIO_PNOT8_PNOT80_SHIFT (0u) -#define GPIO_PNOT8_PNOT81_SHIFT (1u) -#define GPIO_PNOT8_PNOT82_SHIFT (2u) -#define GPIO_PNOT8_PNOT83_SHIFT (3u) -#define GPIO_PNOT8_PNOT84_SHIFT (4u) -#define GPIO_PNOT8_PNOT85_SHIFT (5u) -#define GPIO_PNOT8_PNOT86_SHIFT (6u) -#define GPIO_PNOT8_PNOT87_SHIFT (7u) -#define GPIO_PNOT8_PNOT88_SHIFT (8u) -#define GPIO_PNOT8_PNOT89_SHIFT (9u) -#define GPIO_PNOT8_PNOT810_SHIFT (10u) -#define GPIO_PNOT8_PNOT811_SHIFT (11u) -#define GPIO_PNOT8_PNOT812_SHIFT (12u) -#define GPIO_PNOT8_PNOT813_SHIFT (13u) -#define GPIO_PNOT8_PNOT814_SHIFT (14u) -#define GPIO_PNOT8_PNOT815_SHIFT (15u) - -#define GPIO_PMSR8_PMSR80_SHIFT (0u) -#define GPIO_PMSR8_PMSR81_SHIFT (1u) -#define GPIO_PMSR8_PMSR82_SHIFT (2u) -#define GPIO_PMSR8_PMSR83_SHIFT (3u) -#define GPIO_PMSR8_PMSR84_SHIFT (4u) -#define GPIO_PMSR8_PMSR85_SHIFT (5u) -#define GPIO_PMSR8_PMSR86_SHIFT (6u) -#define GPIO_PMSR8_PMSR87_SHIFT (7u) -#define GPIO_PMSR8_PMSR88_SHIFT (8u) -#define GPIO_PMSR8_PMSR89_SHIFT (9u) -#define GPIO_PMSR8_PMSR810_SHIFT (10u) -#define GPIO_PMSR8_PMSR811_SHIFT (11u) -#define GPIO_PMSR8_PMSR812_SHIFT (12u) -#define GPIO_PMSR8_PMSR813_SHIFT (13u) -#define GPIO_PMSR8_PMSR814_SHIFT (14u) -#define GPIO_PMSR8_PMSR815_SHIFT (15u) -#define GPIO_PMSR8_PMSR816_SHIFT (16u) -#define GPIO_PMSR8_PMSR817_SHIFT (17u) -#define GPIO_PMSR8_PMSR818_SHIFT (18u) -#define GPIO_PMSR8_PMSR819_SHIFT (19u) -#define GPIO_PMSR8_PMSR820_SHIFT (20u) -#define GPIO_PMSR8_PMSR821_SHIFT (21u) -#define GPIO_PMSR8_PMSR822_SHIFT (22u) -#define GPIO_PMSR8_PMSR823_SHIFT (23u) -#define GPIO_PMSR8_PMSR824_SHIFT (24u) -#define GPIO_PMSR8_PMSR825_SHIFT (25u) -#define GPIO_PMSR8_PMSR826_SHIFT (26u) -#define GPIO_PMSR8_PMSR827_SHIFT (27u) -#define GPIO_PMSR8_PMSR828_SHIFT (28u) -#define GPIO_PMSR8_PMSR829_SHIFT (29u) -#define GPIO_PMSR8_PMSR830_SHIFT (30u) -#define GPIO_PMSR8_PMSR831_SHIFT (31u) - -#define GPIO_PMCSR8_PMCSR80_SHIFT (0u) -#define GPIO_PMCSR8_PMCSR81_SHIFT (1u) -#define GPIO_PMCSR8_PMCSR82_SHIFT (2u) -#define GPIO_PMCSR8_PMCSR83_SHIFT (3u) -#define GPIO_PMCSR8_PMCSR84_SHIFT (4u) -#define GPIO_PMCSR8_PMCSR85_SHIFT (5u) -#define GPIO_PMCSR8_PMCSR86_SHIFT (6u) -#define GPIO_PMCSR8_PMCSR87_SHIFT (7u) -#define GPIO_PMCSR8_PMCSR88_SHIFT (8u) -#define GPIO_PMCSR8_PMCSR89_SHIFT (9u) -#define GPIO_PMCSR8_PMCSR810_SHIFT (10u) -#define GPIO_PMCSR8_PMCSR811_SHIFT (11u) -#define GPIO_PMCSR8_PMCSR812_SHIFT (12u) -#define GPIO_PMCSR8_PMCSR813_SHIFT (13u) -#define GPIO_PMCSR8_PMCSR814_SHIFT (14u) -#define GPIO_PMCSR8_PMCSR815_SHIFT (15u) -#define GPIO_PMCSR8_PMCSR816_SHIFT (16u) -#define GPIO_PMCSR8_PMCSR817_SHIFT (17u) -#define GPIO_PMCSR8_PMCSR818_SHIFT (18u) -#define GPIO_PMCSR8_PMCSR819_SHIFT (19u) -#define GPIO_PMCSR8_PMCSR820_SHIFT (20u) -#define GPIO_PMCSR8_PMCSR821_SHIFT (21u) -#define GPIO_PMCSR8_PMCSR822_SHIFT (22u) -#define GPIO_PMCSR8_PMCSR823_SHIFT (23u) -#define GPIO_PMCSR8_PMCSR824_SHIFT (24u) -#define GPIO_PMCSR8_PMCSR825_SHIFT (25u) -#define GPIO_PMCSR8_PMCSR826_SHIFT (26u) -#define GPIO_PMCSR8_PMCSR827_SHIFT (27u) -#define GPIO_PMCSR8_PMCSR828_SHIFT (28u) -#define GPIO_PMCSR8_PMCSR829_SHIFT (29u) -#define GPIO_PMCSR8_PMCSR830_SHIFT (30u) -#define GPIO_PMCSR8_PMCSR831_SHIFT (31u) - -#define GPIO_PFCAE8_PFCAE80_SHIFT (0u) -#define GPIO_PFCAE8_PFCAE81_SHIFT (1u) -#define GPIO_PFCAE8_PFCAE82_SHIFT (2u) -#define GPIO_PFCAE8_PFCAE83_SHIFT (3u) -#define GPIO_PFCAE8_PFCAE84_SHIFT (4u) -#define GPIO_PFCAE8_PFCAE85_SHIFT (5u) -#define GPIO_PFCAE8_PFCAE86_SHIFT (6u) -#define GPIO_PFCAE8_PFCAE87_SHIFT (7u) -#define GPIO_PFCAE8_PFCAE88_SHIFT (8u) -#define GPIO_PFCAE8_PFCAE89_SHIFT (9u) -#define GPIO_PFCAE8_PFCAE810_SHIFT (10u) -#define GPIO_PFCAE8_PFCAE811_SHIFT (11u) -#define GPIO_PFCAE8_PFCAE812_SHIFT (12u) -#define GPIO_PFCAE8_PFCAE813_SHIFT (13u) -#define GPIO_PFCAE8_PFCAE814_SHIFT (14u) -#define GPIO_PFCAE8_PFCAE815_SHIFT (15u) - -#define GPIO_PIBC8_PIBC80_SHIFT (0u) -#define GPIO_PIBC8_PIBC81_SHIFT (1u) -#define GPIO_PIBC8_PIBC82_SHIFT (2u) -#define GPIO_PIBC8_PIBC83_SHIFT (3u) -#define GPIO_PIBC8_PIBC84_SHIFT (4u) -#define GPIO_PIBC8_PIBC85_SHIFT (5u) -#define GPIO_PIBC8_PIBC86_SHIFT (6u) -#define GPIO_PIBC8_PIBC87_SHIFT (7u) -#define GPIO_PIBC8_PIBC88_SHIFT (8u) -#define GPIO_PIBC8_PIBC89_SHIFT (9u) -#define GPIO_PIBC8_PIBC810_SHIFT (10u) -#define GPIO_PIBC8_PIBC811_SHIFT (11u) -#define GPIO_PIBC8_PIBC812_SHIFT (12u) -#define GPIO_PIBC8_PIBC813_SHIFT (13u) -#define GPIO_PIBC8_PIBC814_SHIFT (14u) -#define GPIO_PIBC8_PIBC815_SHIFT (15u) - -#define GPIO_PBDC8_PBDC80_SHIFT (0u) -#define GPIO_PBDC8_PBDC81_SHIFT (1u) -#define GPIO_PBDC8_PBDC82_SHIFT (2u) -#define GPIO_PBDC8_PBDC83_SHIFT (3u) -#define GPIO_PBDC8_PBDC84_SHIFT (4u) -#define GPIO_PBDC8_PBDC85_SHIFT (5u) -#define GPIO_PBDC8_PBDC86_SHIFT (6u) -#define GPIO_PBDC8_PBDC87_SHIFT (7u) -#define GPIO_PBDC8_PBDC88_SHIFT (8u) -#define GPIO_PBDC8_PBDC89_SHIFT (9u) -#define GPIO_PBDC8_PBDC810_SHIFT (10u) -#define GPIO_PBDC8_PBDC811_SHIFT (11u) -#define GPIO_PBDC8_PBDC812_SHIFT (12u) -#define GPIO_PBDC8_PBDC813_SHIFT (13u) -#define GPIO_PBDC8_PBDC814_SHIFT (14u) -#define GPIO_PBDC8_PBDC815_SHIFT (15u) - -#define GPIO_PIPC8_PIPC80_SHIFT (0u) -#define GPIO_PIPC8_PIPC81_SHIFT (1u) -#define GPIO_PIPC8_PIPC82_SHIFT (2u) -#define GPIO_PIPC8_PIPC83_SHIFT (3u) -#define GPIO_PIPC8_PIPC84_SHIFT (4u) -#define GPIO_PIPC8_PIPC85_SHIFT (5u) -#define GPIO_PIPC8_PIPC86_SHIFT (6u) -#define GPIO_PIPC8_PIPC87_SHIFT (7u) -#define GPIO_PIPC8_PIPC88_SHIFT (8u) -#define GPIO_PIPC8_PIPC89_SHIFT (9u) -#define GPIO_PIPC8_PIPC810_SHIFT (10u) -#define GPIO_PIPC8_PIPC811_SHIFT (11u) -#define GPIO_PIPC8_PIPC812_SHIFT (12u) -#define GPIO_PIPC8_PIPC813_SHIFT (13u) -#define GPIO_PIPC8_PIPC814_SHIFT (14u) -#define GPIO_PIPC8_PIPC815_SHIFT (15u) - -/* ---- P9 ---- */ -#define GPIO_P9_P90_SHIFT (0u) -#define GPIO_P9_P91_SHIFT (1u) -#define GPIO_P9_P92_SHIFT (2u) -#define GPIO_P9_P93_SHIFT (3u) -#define GPIO_P9_P94_SHIFT (4u) -#define GPIO_P9_P95_SHIFT (5u) -#define GPIO_P9_P96_SHIFT (6u) -#define GPIO_P9_P97_SHIFT (7u) - -#define GPIO_PSR9_PSR90_SHIFT (0u) -#define GPIO_PSR9_PSR91_SHIFT (1u) -#define GPIO_PSR9_PSR92_SHIFT (2u) -#define GPIO_PSR9_PSR93_SHIFT (3u) -#define GPIO_PSR9_PSR94_SHIFT (4u) -#define GPIO_PSR9_PSR95_SHIFT (5u) -#define GPIO_PSR9_PSR96_SHIFT (6u) -#define GPIO_PSR9_PSR97_SHIFT (7u) -#define GPIO_PSR9_PSR916_SHIFT (16u) -#define GPIO_PSR9_PSR917_SHIFT (17u) -#define GPIO_PSR9_PSR918_SHIFT (18u) -#define GPIO_PSR9_PSR919_SHIFT (19u) -#define GPIO_PSR9_PSR920_SHIFT (20u) -#define GPIO_PSR9_PSR921_SHIFT (21u) -#define GPIO_PSR9_PSR922_SHIFT (22u) -#define GPIO_PSR9_PSR923_SHIFT (23u) - -#define GPIO_PPR9_PPR90_SHIFT (0u) -#define GPIO_PPR9_PPR91_SHIFT (1u) -#define GPIO_PPR9_PPR92_SHIFT (2u) -#define GPIO_PPR9_PPR93_SHIFT (3u) -#define GPIO_PPR9_PPR94_SHIFT (4u) -#define GPIO_PPR9_PPR95_SHIFT (5u) -#define GPIO_PPR9_PPR96_SHIFT (6u) -#define GPIO_PPR9_PPR97_SHIFT (7u) - -#define GPIO_PM9_PM90_SHIFT (0u) -#define GPIO_PM9_PM91_SHIFT (1u) -#define GPIO_PM9_PM92_SHIFT (2u) -#define GPIO_PM9_PM93_SHIFT (3u) -#define GPIO_PM9_PM94_SHIFT (4u) -#define GPIO_PM9_PM95_SHIFT (5u) -#define GPIO_PM9_PM96_SHIFT (6u) -#define GPIO_PM9_PM97_SHIFT (7u) - -#define GPIO_PMC9_PMC90_SHIFT (0u) -#define GPIO_PMC9_PMC91_SHIFT (1u) -#define GPIO_PMC9_PMC92_SHIFT (2u) -#define GPIO_PMC9_PMC93_SHIFT (3u) -#define GPIO_PMC9_PMC94_SHIFT (4u) -#define GPIO_PMC9_PMC95_SHIFT (5u) -#define GPIO_PMC9_PMC96_SHIFT (6u) -#define GPIO_PMC9_PMC97_SHIFT (7u) - -#define GPIO_PFC9_PFC90_SHIFT (0u) -#define GPIO_PFC9_PFC91_SHIFT (1u) -#define GPIO_PFC9_PFC92_SHIFT (2u) -#define GPIO_PFC9_PFC93_SHIFT (3u) -#define GPIO_PFC9_PFC94_SHIFT (4u) -#define GPIO_PFC9_PFC95_SHIFT (5u) -#define GPIO_PFC9_PFC96_SHIFT (6u) -#define GPIO_PFC9_PFC97_SHIFT (7u) - -#define GPIO_PFCE9_PFCE90_SHIFT (0u) -#define GPIO_PFCE9_PFCE91_SHIFT (1u) -#define GPIO_PFCE9_PFCE92_SHIFT (2u) -#define GPIO_PFCE9_PFCE93_SHIFT (3u) -#define GPIO_PFCE9_PFCE94_SHIFT (4u) -#define GPIO_PFCE9_PFCE95_SHIFT (5u) -#define GPIO_PFCE9_PFCE96_SHIFT (6u) -#define GPIO_PFCE9_PFCE97_SHIFT (7u) - -#define GPIO_PNOT9_PNOT90_SHIFT (0u) -#define GPIO_PNOT9_PNOT91_SHIFT (1u) -#define GPIO_PNOT9_PNOT92_SHIFT (2u) -#define GPIO_PNOT9_PNOT93_SHIFT (3u) -#define GPIO_PNOT9_PNOT94_SHIFT (4u) -#define GPIO_PNOT9_PNOT95_SHIFT (5u) -#define GPIO_PNOT9_PNOT96_SHIFT (6u) -#define GPIO_PNOT9_PNOT97_SHIFT (7u) - -#define GPIO_PMSR9_PMSR90_SHIFT (0u) -#define GPIO_PMSR9_PMSR91_SHIFT (1u) -#define GPIO_PMSR9_PMSR92_SHIFT (2u) -#define GPIO_PMSR9_PMSR93_SHIFT (3u) -#define GPIO_PMSR9_PMSR94_SHIFT (4u) -#define GPIO_PMSR9_PMSR95_SHIFT (5u) -#define GPIO_PMSR9_PMSR96_SHIFT (6u) -#define GPIO_PMSR9_PMSR97_SHIFT (7u) -#define GPIO_PMSR9_PMSR916_SHIFT (16u) -#define GPIO_PMSR9_PMSR917_SHIFT (17u) -#define GPIO_PMSR9_PMSR918_SHIFT (18u) -#define GPIO_PMSR9_PMSR919_SHIFT (19u) -#define GPIO_PMSR9_PMSR920_SHIFT (20u) -#define GPIO_PMSR9_PMSR921_SHIFT (21u) -#define GPIO_PMSR9_PMSR922_SHIFT (22u) -#define GPIO_PMSR9_PMSR923_SHIFT (23u) - -#define GPIO_PMCSR9_PMCSR90_SHIFT (0u) -#define GPIO_PMCSR9_PMCSR91_SHIFT (1u) -#define GPIO_PMCSR9_PMCSR92_SHIFT (2u) -#define GPIO_PMCSR9_PMCSR93_SHIFT (3u) -#define GPIO_PMCSR9_PMCSR94_SHIFT (4u) -#define GPIO_PMCSR9_PMCSR95_SHIFT (5u) -#define GPIO_PMCSR9_PMCSR96_SHIFT (6u) -#define GPIO_PMCSR9_PMCSR97_SHIFT (7u) -#define GPIO_PMCSR9_PMCSR916_SHIFT (16u) -#define GPIO_PMCSR9_PMCSR917_SHIFT (17u) -#define GPIO_PMCSR9_PMCSR918_SHIFT (18u) -#define GPIO_PMCSR9_PMCSR919_SHIFT (19u) -#define GPIO_PMCSR9_PMCSR920_SHIFT (20u) -#define GPIO_PMCSR9_PMCSR921_SHIFT (21u) -#define GPIO_PMCSR9_PMCSR922_SHIFT (22u) -#define GPIO_PMCSR9_PMCSR923_SHIFT (23u) - -#define GPIO_PFCAE9_PFCAE90_SHIFT (0u) -#define GPIO_PFCAE9_PFCAE91_SHIFT (1u) -#define GPIO_PFCAE9_PFCAE92_SHIFT (2u) -#define GPIO_PFCAE9_PFCAE93_SHIFT (3u) -#define GPIO_PFCAE9_PFCAE94_SHIFT (4u) -#define GPIO_PFCAE9_PFCAE95_SHIFT (5u) -#define GPIO_PFCAE9_PFCAE96_SHIFT (6u) -#define GPIO_PFCAE9_PFCAE97_SHIFT (7u) - -#define GPIO_PIBC9_PIBC90_SHIFT (0u) -#define GPIO_PIBC9_PIBC91_SHIFT (1u) -#define GPIO_PIBC9_PIBC92_SHIFT (2u) -#define GPIO_PIBC9_PIBC93_SHIFT (3u) -#define GPIO_PIBC9_PIBC94_SHIFT (4u) -#define GPIO_PIBC9_PIBC95_SHIFT (5u) -#define GPIO_PIBC9_PIBC96_SHIFT (6u) -#define GPIO_PIBC9_PIBC97_SHIFT (7u) - -#define GPIO_PBDC9_PBDC90_SHIFT (0u) -#define GPIO_PBDC9_PBDC91_SHIFT (1u) -#define GPIO_PBDC9_PBDC92_SHIFT (2u) -#define GPIO_PBDC9_PBDC93_SHIFT (3u) -#define GPIO_PBDC9_PBDC94_SHIFT (4u) -#define GPIO_PBDC9_PBDC95_SHIFT (5u) -#define GPIO_PBDC9_PBDC96_SHIFT (6u) -#define GPIO_PBDC9_PBDC97_SHIFT (7u) - -#define GPIO_PIPC9_PIPC90_SHIFT (0u) -#define GPIO_PIPC9_PIPC91_SHIFT (1u) -#define GPIO_PIPC9_PIPC92_SHIFT (2u) -#define GPIO_PIPC9_PIPC93_SHIFT (3u) -#define GPIO_PIPC9_PIPC94_SHIFT (4u) -#define GPIO_PIPC9_PIPC95_SHIFT (5u) -#define GPIO_PIPC9_PIPC96_SHIFT (6u) -#define GPIO_PIPC9_PIPC97_SHIFT (7u) - -/* ---- P10 ---- */ -#define GPIO_P10_P100_SHIFT (0u) -#define GPIO_P10_P101_SHIFT (1u) -#define GPIO_P10_P102_SHIFT (2u) -#define GPIO_P10_P103_SHIFT (3u) -#define GPIO_P10_P104_SHIFT (4u) -#define GPIO_P10_P105_SHIFT (5u) -#define GPIO_P10_P106_SHIFT (6u) -#define GPIO_P10_P107_SHIFT (7u) -#define GPIO_P10_P108_SHIFT (8u) -#define GPIO_P10_P109_SHIFT (9u) -#define GPIO_P10_P1010_SHIFT (10u) -#define GPIO_P10_P1011_SHIFT (11u) -#define GPIO_P10_P1012_SHIFT (12u) -#define GPIO_P10_P1013_SHIFT (13u) -#define GPIO_P10_P1014_SHIFT (14u) -#define GPIO_P10_P1015_SHIFT (15u) - -#define GPIO_PSR10_PSR100_SHIFT (0u) -#define GPIO_PSR10_PSR101_SHIFT (1u) -#define GPIO_PSR10_PSR102_SHIFT (2u) -#define GPIO_PSR10_PSR103_SHIFT (3u) -#define GPIO_PSR10_PSR104_SHIFT (4u) -#define GPIO_PSR10_PSR105_SHIFT (5u) -#define GPIO_PSR10_PSR106_SHIFT (6u) -#define GPIO_PSR10_PSR107_SHIFT (7u) -#define GPIO_PSR10_PSR108_SHIFT (8u) -#define GPIO_PSR10_PSR109_SHIFT (9u) -#define GPIO_PSR10_PSR1010_SHIFT (10u) -#define GPIO_PSR10_PSR1011_SHIFT (11u) -#define GPIO_PSR10_PSR1012_SHIFT (12u) -#define GPIO_PSR10_PSR1013_SHIFT (13u) -#define GPIO_PSR10_PSR1014_SHIFT (14u) -#define GPIO_PSR10_PSR1015_SHIFT (15u) -#define GPIO_PSR10_PSR1016_SHIFT (16u) -#define GPIO_PSR10_PSR1017_SHIFT (17u) -#define GPIO_PSR10_PSR1018_SHIFT (18u) -#define GPIO_PSR10_PSR1019_SHIFT (19u) -#define GPIO_PSR10_PSR1020_SHIFT (20u) -#define GPIO_PSR10_PSR1021_SHIFT (21u) -#define GPIO_PSR10_PSR1022_SHIFT (22u) -#define GPIO_PSR10_PSR1023_SHIFT (23u) -#define GPIO_PSR10_PSR1024_SHIFT (24u) -#define GPIO_PSR10_PSR1025_SHIFT (25u) -#define GPIO_PSR10_PSR1026_SHIFT (26u) -#define GPIO_PSR10_PSR1027_SHIFT (27u) -#define GPIO_PSR10_PSR1028_SHIFT (28u) -#define GPIO_PSR10_PSR1029_SHIFT (29u) -#define GPIO_PSR10_PSR1030_SHIFT (30u) -#define GPIO_PSR10_PSR1031_SHIFT (31u) - -#define GPIO_PPR10_PPR100_SHIFT (0u) -#define GPIO_PPR10_PPR101_SHIFT (1u) -#define GPIO_PPR10_PPR102_SHIFT (2u) -#define GPIO_PPR10_PPR103_SHIFT (3u) -#define GPIO_PPR10_PPR104_SHIFT (4u) -#define GPIO_PPR10_PPR105_SHIFT (5u) -#define GPIO_PPR10_PPR106_SHIFT (6u) -#define GPIO_PPR10_PPR107_SHIFT (7u) -#define GPIO_PPR10_PPR108_SHIFT (8u) -#define GPIO_PPR10_PPR109_SHIFT (9u) -#define GPIO_PPR10_PPR1010_SHIFT (10u) -#define GPIO_PPR10_PPR1011_SHIFT (11u) -#define GPIO_PPR10_PPR1012_SHIFT (12u) -#define GPIO_PPR10_PPR1013_SHIFT (13u) -#define GPIO_PPR10_PPR1014_SHIFT (14u) -#define GPIO_PPR10_PPR1015_SHIFT (15u) - -#define GPIO_PM10_PM100_SHIFT (0u) -#define GPIO_PM10_PM101_SHIFT (1u) -#define GPIO_PM10_PM102_SHIFT (2u) -#define GPIO_PM10_PM103_SHIFT (3u) -#define GPIO_PM10_PM104_SHIFT (4u) -#define GPIO_PM10_PM105_SHIFT (5u) -#define GPIO_PM10_PM106_SHIFT (6u) -#define GPIO_PM10_PM107_SHIFT (7u) -#define GPIO_PM10_PM108_SHIFT (8u) -#define GPIO_PM10_PM109_SHIFT (9u) -#define GPIO_PM10_PM1010_SHIFT (10u) -#define GPIO_PM10_PM1011_SHIFT (11u) -#define GPIO_PM10_PM1012_SHIFT (12u) -#define GPIO_PM10_PM1013_SHIFT (13u) -#define GPIO_PM10_PM1014_SHIFT (14u) -#define GPIO_PM10_PM1015_SHIFT (15u) - -#define GPIO_PMC10_PMC100_SHIFT (0u) -#define GPIO_PMC10_PMC101_SHIFT (1u) -#define GPIO_PMC10_PMC102_SHIFT (2u) -#define GPIO_PMC10_PMC103_SHIFT (3u) -#define GPIO_PMC10_PMC104_SHIFT (4u) -#define GPIO_PMC10_PMC105_SHIFT (5u) -#define GPIO_PMC10_PMC106_SHIFT (6u) -#define GPIO_PMC10_PMC107_SHIFT (7u) -#define GPIO_PMC10_PMC108_SHIFT (8u) -#define GPIO_PMC10_PMC109_SHIFT (9u) -#define GPIO_PMC10_PMC1010_SHIFT (10u) -#define GPIO_PMC10_PMC1011_SHIFT (11u) -#define GPIO_PMC10_PMC1012_SHIFT (12u) -#define GPIO_PMC10_PMC1013_SHIFT (13u) -#define GPIO_PMC10_PMC1014_SHIFT (14u) -#define GPIO_PMC10_PMC1015_SHIFT (15u) - -#define GPIO_PFC10_PFC100_SHIFT (0u) -#define GPIO_PFC10_PFC101_SHIFT (1u) -#define GPIO_PFC10_PFC102_SHIFT (2u) -#define GPIO_PFC10_PFC103_SHIFT (3u) -#define GPIO_PFC10_PFC104_SHIFT (4u) -#define GPIO_PFC10_PFC105_SHIFT (5u) -#define GPIO_PFC10_PFC106_SHIFT (6u) -#define GPIO_PFC10_PFC107_SHIFT (7u) -#define GPIO_PFC10_PFC108_SHIFT (8u) -#define GPIO_PFC10_PFC109_SHIFT (9u) -#define GPIO_PFC10_PFC1010_SHIFT (10u) -#define GPIO_PFC10_PFC1011_SHIFT (11u) -#define GPIO_PFC10_PFC1012_SHIFT (12u) -#define GPIO_PFC10_PFC1013_SHIFT (13u) -#define GPIO_PFC10_PFC1014_SHIFT (14u) -#define GPIO_PFC10_PFC1015_SHIFT (15u) - -#define GPIO_PFCE10_PFCE100_SHIFT (0u) -#define GPIO_PFCE10_PFCE101_SHIFT (1u) -#define GPIO_PFCE10_PFCE102_SHIFT (2u) -#define GPIO_PFCE10_PFCE103_SHIFT (3u) -#define GPIO_PFCE10_PFCE104_SHIFT (4u) -#define GPIO_PFCE10_PFCE105_SHIFT (5u) -#define GPIO_PFCE10_PFCE106_SHIFT (6u) -#define GPIO_PFCE10_PFCE107_SHIFT (7u) -#define GPIO_PFCE10_PFCE108_SHIFT (8u) -#define GPIO_PFCE10_PFCE109_SHIFT (9u) -#define GPIO_PFCE10_PFCE1010_SHIFT (10u) -#define GPIO_PFCE10_PFCE1011_SHIFT (11u) -#define GPIO_PFCE10_PFCE1012_SHIFT (12u) -#define GPIO_PFCE10_PFCE1013_SHIFT (13u) -#define GPIO_PFCE10_PFCE1014_SHIFT (14u) -#define GPIO_PFCE10_PFCE1015_SHIFT (15u) - -#define GPIO_PNOT10_PNOT100_SHIFT (0u) -#define GPIO_PNOT10_PNOT101_SHIFT (1u) -#define GPIO_PNOT10_PNOT102_SHIFT (2u) -#define GPIO_PNOT10_PNOT103_SHIFT (3u) -#define GPIO_PNOT10_PNOT104_SHIFT (4u) -#define GPIO_PNOT10_PNOT105_SHIFT (5u) -#define GPIO_PNOT10_PNOT106_SHIFT (6u) -#define GPIO_PNOT10_PNOT107_SHIFT (7u) -#define GPIO_PNOT10_PNOT108_SHIFT (8u) -#define GPIO_PNOT10_PNOT109_SHIFT (9u) -#define GPIO_PNOT10_PNOT1010_SHIFT (10u) -#define GPIO_PNOT10_PNOT1011_SHIFT (11u) -#define GPIO_PNOT10_PNOT1012_SHIFT (12u) -#define GPIO_PNOT10_PNOT1013_SHIFT (13u) -#define GPIO_PNOT10_PNOT1014_SHIFT (14u) -#define GPIO_PNOT10_PNOT1015_SHIFT (15u) - -#define GPIO_PMSR10_PMSR100_SHIFT (0u) -#define GPIO_PMSR10_PMSR101_SHIFT (1u) -#define GPIO_PMSR10_PMSR102_SHIFT (2u) -#define GPIO_PMSR10_PMSR103_SHIFT (3u) -#define GPIO_PMSR10_PMSR104_SHIFT (4u) -#define GPIO_PMSR10_PMSR105_SHIFT (5u) -#define GPIO_PMSR10_PMSR106_SHIFT (6u) -#define GPIO_PMSR10_PMSR107_SHIFT (7u) -#define GPIO_PMSR10_PMSR108_SHIFT (8u) -#define GPIO_PMSR10_PMSR109_SHIFT (9u) -#define GPIO_PMSR10_PMSR1010_SHIFT (10u) -#define GPIO_PMSR10_PMSR1011_SHIFT (11u) -#define GPIO_PMSR10_PMSR1012_SHIFT (12u) -#define GPIO_PMSR10_PMSR1013_SHIFT (13u) -#define GPIO_PMSR10_PMSR1014_SHIFT (14u) -#define GPIO_PMSR10_PMSR1015_SHIFT (15u) -#define GPIO_PMSR10_PMSR1016_SHIFT (16u) -#define GPIO_PMSR10_PMSR1017_SHIFT (17u) -#define GPIO_PMSR10_PMSR1018_SHIFT (18u) -#define GPIO_PMSR10_PMSR1019_SHIFT (19u) -#define GPIO_PMSR10_PMSR1020_SHIFT (20u) -#define GPIO_PMSR10_PMSR1021_SHIFT (21u) -#define GPIO_PMSR10_PMSR1022_SHIFT (22u) -#define GPIO_PMSR10_PMSR1023_SHIFT (23u) -#define GPIO_PMSR10_PMSR1024_SHIFT (24u) -#define GPIO_PMSR10_PMSR1025_SHIFT (25u) -#define GPIO_PMSR10_PMSR1026_SHIFT (26u) -#define GPIO_PMSR10_PMSR1027_SHIFT (27u) -#define GPIO_PMSR10_PMSR1028_SHIFT (28u) -#define GPIO_PMSR10_PMSR1029_SHIFT (29u) -#define GPIO_PMSR10_PMSR1030_SHIFT (30u) -#define GPIO_PMSR10_PMSR1031_SHIFT (31u) - -#define GPIO_PMCSR10_PMCSR100_SHIFT (0u) -#define GPIO_PMCSR10_PMCSR101_SHIFT (1u) -#define GPIO_PMCSR10_PMCSR102_SHIFT (2u) -#define GPIO_PMCSR10_PMCSR103_SHIFT (3u) -#define GPIO_PMCSR10_PMCSR104_SHIFT (4u) -#define GPIO_PMCSR10_PMCSR105_SHIFT (5u) -#define GPIO_PMCSR10_PMCSR106_SHIFT (6u) -#define GPIO_PMCSR10_PMCSR107_SHIFT (7u) -#define GPIO_PMCSR10_PMCSR108_SHIFT (8u) -#define GPIO_PMCSR10_PMCSR109_SHIFT (9u) -#define GPIO_PMCSR10_PMCSR1010_SHIFT (10u) -#define GPIO_PMCSR10_PMCSR1011_SHIFT (11u) -#define GPIO_PMCSR10_PMCSR1012_SHIFT (12u) -#define GPIO_PMCSR10_PMCSR1013_SHIFT (13u) -#define GPIO_PMCSR10_PMCSR1014_SHIFT (14u) -#define GPIO_PMCSR10_PMCSR1015_SHIFT (15u) -#define GPIO_PMCSR10_PMCSR1016_SHIFT (16u) -#define GPIO_PMCSR10_PMCSR1017_SHIFT (17u) -#define GPIO_PMCSR10_PMCSR1018_SHIFT (18u) -#define GPIO_PMCSR10_PMCSR1019_SHIFT (19u) -#define GPIO_PMCSR10_PMCSR1020_SHIFT (20u) -#define GPIO_PMCSR10_PMCSR1021_SHIFT (21u) -#define GPIO_PMCSR10_PMCSR1022_SHIFT (22u) -#define GPIO_PMCSR10_PMCSR1023_SHIFT (23u) -#define GPIO_PMCSR10_PMCSR1024_SHIFT (24u) -#define GPIO_PMCSR10_PMCSR1025_SHIFT (25u) -#define GPIO_PMCSR10_PMCSR1026_SHIFT (26u) -#define GPIO_PMCSR10_PMCSR1027_SHIFT (27u) -#define GPIO_PMCSR10_PMCSR1028_SHIFT (28u) -#define GPIO_PMCSR10_PMCSR1029_SHIFT (29u) -#define GPIO_PMCSR10_PMCSR1030_SHIFT (30u) -#define GPIO_PMCSR10_PMCSR1031_SHIFT (31u) - -#define GPIO_PFCAE10_PFCAE100_SHIFT (0u) -#define GPIO_PFCAE10_PFCAE101_SHIFT (1u) -#define GPIO_PFCAE10_PFCAE102_SHIFT (2u) -#define GPIO_PFCAE10_PFCAE103_SHIFT (3u) -#define GPIO_PFCAE10_PFCAE104_SHIFT (4u) -#define GPIO_PFCAE10_PFCAE105_SHIFT (5u) -#define GPIO_PFCAE10_PFCAE106_SHIFT (6u) -#define GPIO_PFCAE10_PFCAE107_SHIFT (7u) -#define GPIO_PFCAE10_PFCAE108_SHIFT (8u) -#define GPIO_PFCAE10_PFCAE109_SHIFT (9u) -#define GPIO_PFCAE10_PFCAE1010_SHIFT (10u) -#define GPIO_PFCAE10_PFCAE1011_SHIFT (11u) -#define GPIO_PFCAE10_PFCAE1012_SHIFT (12u) -#define GPIO_PFCAE10_PFCAE1013_SHIFT (13u) -#define GPIO_PFCAE10_PFCAE1014_SHIFT (14u) -#define GPIO_PFCAE10_PFCAE1015_SHIFT (15u) - -#define GPIO_PIBC10_PIBC100_SHIFT (0u) -#define GPIO_PIBC10_PIBC101_SHIFT (1u) -#define GPIO_PIBC10_PIBC102_SHIFT (2u) -#define GPIO_PIBC10_PIBC103_SHIFT (3u) -#define GPIO_PIBC10_PIBC104_SHIFT (4u) -#define GPIO_PIBC10_PIBC105_SHIFT (5u) -#define GPIO_PIBC10_PIBC106_SHIFT (6u) -#define GPIO_PIBC10_PIBC107_SHIFT (7u) -#define GPIO_PIBC10_PIBC108_SHIFT (8u) -#define GPIO_PIBC10_PIBC109_SHIFT (9u) -#define GPIO_PIBC10_PIBC1010_SHIFT (10u) -#define GPIO_PIBC10_PIBC1011_SHIFT (11u) -#define GPIO_PIBC10_PIBC1012_SHIFT (12u) -#define GPIO_PIBC10_PIBC1013_SHIFT (13u) -#define GPIO_PIBC10_PIBC1014_SHIFT (14u) -#define GPIO_PIBC10_PIBC1015_SHIFT (15u) - -#define GPIO_PBDC10_PBDC100_SHIFT (0u) -#define GPIO_PBDC10_PBDC101_SHIFT (1u) -#define GPIO_PBDC10_PBDC102_SHIFT (2u) -#define GPIO_PBDC10_PBDC103_SHIFT (3u) -#define GPIO_PBDC10_PBDC104_SHIFT (4u) -#define GPIO_PBDC10_PBDC105_SHIFT (5u) -#define GPIO_PBDC10_PBDC106_SHIFT (6u) -#define GPIO_PBDC10_PBDC107_SHIFT (7u) -#define GPIO_PBDC10_PBDC108_SHIFT (8u) -#define GPIO_PBDC10_PBDC109_SHIFT (9u) -#define GPIO_PBDC10_PBDC1010_SHIFT (10u) -#define GPIO_PBDC10_PBDC1011_SHIFT (11u) -#define GPIO_PBDC10_PBDC1012_SHIFT (12u) -#define GPIO_PBDC10_PBDC1013_SHIFT (13u) -#define GPIO_PBDC10_PBDC1014_SHIFT (14u) -#define GPIO_PBDC10_PBDC1015_SHIFT (15u) - -#define GPIO_PIPC10_PIPC100_SHIFT (0u) -#define GPIO_PIPC10_PIPC101_SHIFT (1u) -#define GPIO_PIPC10_PIPC102_SHIFT (2u) -#define GPIO_PIPC10_PIPC103_SHIFT (3u) -#define GPIO_PIPC10_PIPC104_SHIFT (4u) -#define GPIO_PIPC10_PIPC105_SHIFT (5u) -#define GPIO_PIPC10_PIPC106_SHIFT (6u) -#define GPIO_PIPC10_PIPC107_SHIFT (7u) -#define GPIO_PIPC10_PIPC108_SHIFT (8u) -#define GPIO_PIPC10_PIPC109_SHIFT (9u) -#define GPIO_PIPC10_PIPC1010_SHIFT (10u) -#define GPIO_PIPC10_PIPC1011_SHIFT (11u) -#define GPIO_PIPC10_PIPC1012_SHIFT (12u) -#define GPIO_PIPC10_PIPC1013_SHIFT (13u) -#define GPIO_PIPC10_PIPC1014_SHIFT (14u) -#define GPIO_PIPC10_PIPC1015_SHIFT (15u) - -/* ---- P11 ---- */ -#define GPIO_P11_P110_SHIFT (0u) -#define GPIO_P11_P111_SHIFT (1u) -#define GPIO_P11_P112_SHIFT (2u) -#define GPIO_P11_P113_SHIFT (3u) -#define GPIO_P11_P114_SHIFT (4u) -#define GPIO_P11_P115_SHIFT (5u) -#define GPIO_P11_P116_SHIFT (6u) -#define GPIO_P11_P117_SHIFT (7u) -#define GPIO_P11_P118_SHIFT (8u) -#define GPIO_P11_P119_SHIFT (9u) -#define GPIO_P11_P1110_SHIFT (10u) -#define GPIO_P11_P1111_SHIFT (11u) -#define GPIO_P11_P1112_SHIFT (12u) -#define GPIO_P11_P1113_SHIFT (13u) -#define GPIO_P11_P1114_SHIFT (14u) -#define GPIO_P11_P1115_SHIFT (15u) - -#define GPIO_PSR11_PSR110_SHIFT (0u) -#define GPIO_PSR11_PSR111_SHIFT (1u) -#define GPIO_PSR11_PSR112_SHIFT (2u) -#define GPIO_PSR11_PSR113_SHIFT (3u) -#define GPIO_PSR11_PSR114_SHIFT (4u) -#define GPIO_PSR11_PSR115_SHIFT (5u) -#define GPIO_PSR11_PSR116_SHIFT (6u) -#define GPIO_PSR11_PSR117_SHIFT (7u) -#define GPIO_PSR11_PSR118_SHIFT (8u) -#define GPIO_PSR11_PSR119_SHIFT (9u) -#define GPIO_PSR11_PSR1110_SHIFT (10u) -#define GPIO_PSR11_PSR1111_SHIFT (11u) -#define GPIO_PSR11_PSR1112_SHIFT (12u) -#define GPIO_PSR11_PSR1113_SHIFT (13u) -#define GPIO_PSR11_PSR1114_SHIFT (14u) -#define GPIO_PSR11_PSR1115_SHIFT (15u) -#define GPIO_PSR11_PSR1116_SHIFT (16u) -#define GPIO_PSR11_PSR1117_SHIFT (17u) -#define GPIO_PSR11_PSR1118_SHIFT (18u) -#define GPIO_PSR11_PSR1119_SHIFT (19u) -#define GPIO_PSR11_PSR1120_SHIFT (20u) -#define GPIO_PSR11_PSR1121_SHIFT (21u) -#define GPIO_PSR11_PSR1122_SHIFT (22u) -#define GPIO_PSR11_PSR1123_SHIFT (23u) -#define GPIO_PSR11_PSR1124_SHIFT (24u) -#define GPIO_PSR11_PSR1125_SHIFT (25u) -#define GPIO_PSR11_PSR1126_SHIFT (26u) -#define GPIO_PSR11_PSR1127_SHIFT (27u) -#define GPIO_PSR11_PSR1128_SHIFT (28u) -#define GPIO_PSR11_PSR1129_SHIFT (29u) -#define GPIO_PSR11_PSR1130_SHIFT (30u) -#define GPIO_PSR11_PSR1131_SHIFT (31u) - -#define GPIO_PPR11_PPR110_SHIFT (0u) -#define GPIO_PPR11_PPR111_SHIFT (1u) -#define GPIO_PPR11_PPR112_SHIFT (2u) -#define GPIO_PPR11_PPR113_SHIFT (3u) -#define GPIO_PPR11_PPR114_SHIFT (4u) -#define GPIO_PPR11_PPR115_SHIFT (5u) -#define GPIO_PPR11_PPR116_SHIFT (6u) -#define GPIO_PPR11_PPR117_SHIFT (7u) -#define GPIO_PPR11_PPR118_SHIFT (8u) -#define GPIO_PPR11_PPR119_SHIFT (9u) -#define GPIO_PPR11_PPR1110_SHIFT (10u) -#define GPIO_PPR11_PPR1111_SHIFT (11u) -#define GPIO_PPR11_PPR1112_SHIFT (12u) -#define GPIO_PPR11_PPR1113_SHIFT (13u) -#define GPIO_PPR11_PPR1114_SHIFT (14u) -#define GPIO_PPR11_PPR1115_SHIFT (15u) - -#define GPIO_PM11_PM110_SHIFT (0u) -#define GPIO_PM11_PM111_SHIFT (1u) -#define GPIO_PM11_PM112_SHIFT (2u) -#define GPIO_PM11_PM113_SHIFT (3u) -#define GPIO_PM11_PM114_SHIFT (4u) -#define GPIO_PM11_PM115_SHIFT (5u) -#define GPIO_PM11_PM116_SHIFT (6u) -#define GPIO_PM11_PM117_SHIFT (7u) -#define GPIO_PM11_PM118_SHIFT (8u) -#define GPIO_PM11_PM119_SHIFT (9u) -#define GPIO_PM11_PM1110_SHIFT (10u) -#define GPIO_PM11_PM1111_SHIFT (11u) -#define GPIO_PM11_PM1112_SHIFT (12u) -#define GPIO_PM11_PM1113_SHIFT (13u) -#define GPIO_PM11_PM1114_SHIFT (14u) -#define GPIO_PM11_PM1115_SHIFT (15u) - -#define GPIO_PMC11_PMC110_SHIFT (0u) -#define GPIO_PMC11_PMC111_SHIFT (1u) -#define GPIO_PMC11_PMC112_SHIFT (2u) -#define GPIO_PMC11_PMC113_SHIFT (3u) -#define GPIO_PMC11_PMC114_SHIFT (4u) -#define GPIO_PMC11_PMC115_SHIFT (5u) -#define GPIO_PMC11_PMC116_SHIFT (6u) -#define GPIO_PMC11_PMC117_SHIFT (7u) -#define GPIO_PMC11_PMC118_SHIFT (8u) -#define GPIO_PMC11_PMC119_SHIFT (9u) -#define GPIO_PMC11_PMC1110_SHIFT (10u) -#define GPIO_PMC11_PMC1111_SHIFT (11u) -#define GPIO_PMC11_PMC1112_SHIFT (12u) -#define GPIO_PMC11_PMC1113_SHIFT (13u) -#define GPIO_PMC11_PMC1114_SHIFT (14u) -#define GPIO_PMC11_PMC1115_SHIFT (15u) - -#define GPIO_PFC11_PFC110_SHIFT (0u) -#define GPIO_PFC11_PFC111_SHIFT (1u) -#define GPIO_PFC11_PFC112_SHIFT (2u) -#define GPIO_PFC11_PFC113_SHIFT (3u) -#define GPIO_PFC11_PFC114_SHIFT (4u) -#define GPIO_PFC11_PFC115_SHIFT (5u) -#define GPIO_PFC11_PFC116_SHIFT (6u) -#define GPIO_PFC11_PFC117_SHIFT (7u) -#define GPIO_PFC11_PFC118_SHIFT (8u) -#define GPIO_PFC11_PFC119_SHIFT (9u) -#define GPIO_PFC11_PFC1110_SHIFT (10u) -#define GPIO_PFC11_PFC1111_SHIFT (11u) -#define GPIO_PFC11_PFC1112_SHIFT (12u) -#define GPIO_PFC11_PFC1113_SHIFT (13u) -#define GPIO_PFC11_PFC1114_SHIFT (14u) -#define GPIO_PFC11_PFC1115_SHIFT (15u) - -#define GPIO_PFCE11_PFCE110_SHIFT (0u) -#define GPIO_PFCE11_PFCE111_SHIFT (1u) -#define GPIO_PFCE11_PFCE112_SHIFT (2u) -#define GPIO_PFCE11_PFCE113_SHIFT (3u) -#define GPIO_PFCE11_PFCE114_SHIFT (4u) -#define GPIO_PFCE11_PFCE115_SHIFT (5u) -#define GPIO_PFCE11_PFCE116_SHIFT (6u) -#define GPIO_PFCE11_PFCE117_SHIFT (7u) -#define GPIO_PFCE11_PFCE118_SHIFT (8u) -#define GPIO_PFCE11_PFCE119_SHIFT (9u) -#define GPIO_PFCE11_PFCE1110_SHIFT (10u) -#define GPIO_PFCE11_PFCE1111_SHIFT (11u) -#define GPIO_PFCE11_PFCE1112_SHIFT (12u) -#define GPIO_PFCE11_PFCE1113_SHIFT (13u) -#define GPIO_PFCE11_PFCE1114_SHIFT (14u) -#define GPIO_PFCE11_PFCE1115_SHIFT (15u) - -#define GPIO_PNOT11_PNOT110_SHIFT (0u) -#define GPIO_PNOT11_PNOT111_SHIFT (1u) -#define GPIO_PNOT11_PNOT112_SHIFT (2u) -#define GPIO_PNOT11_PNOT113_SHIFT (3u) -#define GPIO_PNOT11_PNOT114_SHIFT (4u) -#define GPIO_PNOT11_PNOT115_SHIFT (5u) -#define GPIO_PNOT11_PNOT116_SHIFT (6u) -#define GPIO_PNOT11_PNOT117_SHIFT (7u) -#define GPIO_PNOT11_PNOT118_SHIFT (8u) -#define GPIO_PNOT11_PNOT119_SHIFT (9u) -#define GPIO_PNOT11_PNOT1110_SHIFT (10u) -#define GPIO_PNOT11_PNOT1111_SHIFT (11u) -#define GPIO_PNOT11_PNOT1112_SHIFT (12u) -#define GPIO_PNOT11_PNOT1113_SHIFT (13u) -#define GPIO_PNOT11_PNOT1114_SHIFT (14u) -#define GPIO_PNOT11_PNOT1115_SHIFT (15u) - -#define GPIO_PMSR11_PMSR110_SHIFT (0u) -#define GPIO_PMSR11_PMSR111_SHIFT (1u) -#define GPIO_PMSR11_PMSR112_SHIFT (2u) -#define GPIO_PMSR11_PMSR113_SHIFT (3u) -#define GPIO_PMSR11_PMSR114_SHIFT (4u) -#define GPIO_PMSR11_PMSR115_SHIFT (5u) -#define GPIO_PMSR11_PMSR116_SHIFT (6u) -#define GPIO_PMSR11_PMSR117_SHIFT (7u) -#define GPIO_PMSR11_PMSR118_SHIFT (8u) -#define GPIO_PMSR11_PMSR119_SHIFT (9u) -#define GPIO_PMSR11_PMSR1110_SHIFT (10u) -#define GPIO_PMSR11_PMSR1111_SHIFT (11u) -#define GPIO_PMSR11_PMSR1112_SHIFT (12u) -#define GPIO_PMSR11_PMSR1113_SHIFT (13u) -#define GPIO_PMSR11_PMSR1114_SHIFT (14u) -#define GPIO_PMSR11_PMSR1115_SHIFT (15u) -#define GPIO_PMSR11_PMSR1116_SHIFT (16u) -#define GPIO_PMSR11_PMSR1117_SHIFT (17u) -#define GPIO_PMSR11_PMSR1118_SHIFT (18u) -#define GPIO_PMSR11_PMSR1119_SHIFT (19u) -#define GPIO_PMSR11_PMSR1120_SHIFT (20u) -#define GPIO_PMSR11_PMSR1121_SHIFT (21u) -#define GPIO_PMSR11_PMSR1122_SHIFT (22u) -#define GPIO_PMSR11_PMSR1123_SHIFT (23u) -#define GPIO_PMSR11_PMSR1124_SHIFT (24u) -#define GPIO_PMSR11_PMSR1125_SHIFT (25u) -#define GPIO_PMSR11_PMSR1126_SHIFT (26u) -#define GPIO_PMSR11_PMSR1127_SHIFT (27u) -#define GPIO_PMSR11_PMSR1128_SHIFT (28u) -#define GPIO_PMSR11_PMSR1129_SHIFT (29u) -#define GPIO_PMSR11_PMSR1130_SHIFT (30u) -#define GPIO_PMSR11_PMSR1131_SHIFT (31u) - -#define GPIO_PMCSR11_PMCSR110_SHIFT (0u) -#define GPIO_PMCSR11_PMCSR111_SHIFT (1u) -#define GPIO_PMCSR11_PMCSR112_SHIFT (2u) -#define GPIO_PMCSR11_PMCSR113_SHIFT (3u) -#define GPIO_PMCSR11_PMCSR114_SHIFT (4u) -#define GPIO_PMCSR11_PMCSR115_SHIFT (5u) -#define GPIO_PMCSR11_PMCSR116_SHIFT (6u) -#define GPIO_PMCSR11_PMCSR117_SHIFT (7u) -#define GPIO_PMCSR11_PMCSR118_SHIFT (8u) -#define GPIO_PMCSR11_PMCSR119_SHIFT (9u) -#define GPIO_PMCSR11_PMCSR1110_SHIFT (10u) -#define GPIO_PMCSR11_PMCSR1111_SHIFT (11u) -#define GPIO_PMCSR11_PMCSR1112_SHIFT (12u) -#define GPIO_PMCSR11_PMCSR1113_SHIFT (13u) -#define GPIO_PMCSR11_PMCSR1114_SHIFT (14u) -#define GPIO_PMCSR11_PMCSR1115_SHIFT (15u) -#define GPIO_PMCSR11_PMCSR1116_SHIFT (16u) -#define GPIO_PMCSR11_PMCSR1117_SHIFT (17u) -#define GPIO_PMCSR11_PMCSR1118_SHIFT (18u) -#define GPIO_PMCSR11_PMCSR1119_SHIFT (19u) -#define GPIO_PMCSR11_PMCSR1120_SHIFT (20u) -#define GPIO_PMCSR11_PMCSR1121_SHIFT (21u) -#define GPIO_PMCSR11_PMCSR1122_SHIFT (22u) -#define GPIO_PMCSR11_PMCSR1123_SHIFT (23u) -#define GPIO_PMCSR11_PMCSR1124_SHIFT (24u) -#define GPIO_PMCSR11_PMCSR1125_SHIFT (25u) -#define GPIO_PMCSR11_PMCSR1126_SHIFT (26u) -#define GPIO_PMCSR11_PMCSR1127_SHIFT (27u) -#define GPIO_PMCSR11_PMCSR1128_SHIFT (28u) -#define GPIO_PMCSR11_PMCSR1129_SHIFT (29u) -#define GPIO_PMCSR11_PMCSR1130_SHIFT (30u) -#define GPIO_PMCSR11_PMCSR1131_SHIFT (31u) - -#define GPIO_PFCAE11_PFCAE110_SHIFT (0u) -#define GPIO_PFCAE11_PFCAE111_SHIFT (1u) -#define GPIO_PFCAE11_PFCAE112_SHIFT (2u) -#define GPIO_PFCAE11_PFCAE113_SHIFT (3u) -#define GPIO_PFCAE11_PFCAE114_SHIFT (4u) -#define GPIO_PFCAE11_PFCAE115_SHIFT (5u) -#define GPIO_PFCAE11_PFCAE116_SHIFT (6u) -#define GPIO_PFCAE11_PFCAE117_SHIFT (7u) -#define GPIO_PFCAE11_PFCAE118_SHIFT (8u) -#define GPIO_PFCAE11_PFCAE119_SHIFT (9u) -#define GPIO_PFCAE11_PFCAE1110_SHIFT (10u) -#define GPIO_PFCAE11_PFCAE1111_SHIFT (11u) -#define GPIO_PFCAE11_PFCAE1112_SHIFT (12u) -#define GPIO_PFCAE11_PFCAE1113_SHIFT (13u) -#define GPIO_PFCAE11_PFCAE1114_SHIFT (14u) -#define GPIO_PFCAE11_PFCAE1115_SHIFT (15u) - -#define GPIO_PIBC11_PIBC110_SHIFT (0u) -#define GPIO_PIBC11_PIBC111_SHIFT (1u) -#define GPIO_PIBC11_PIBC112_SHIFT (2u) -#define GPIO_PIBC11_PIBC113_SHIFT (3u) -#define GPIO_PIBC11_PIBC114_SHIFT (4u) -#define GPIO_PIBC11_PIBC115_SHIFT (5u) -#define GPIO_PIBC11_PIBC116_SHIFT (6u) -#define GPIO_PIBC11_PIBC117_SHIFT (7u) -#define GPIO_PIBC11_PIBC118_SHIFT (8u) -#define GPIO_PIBC11_PIBC119_SHIFT (9u) -#define GPIO_PIBC11_PIBC1110_SHIFT (10u) -#define GPIO_PIBC11_PIBC1111_SHIFT (11u) -#define GPIO_PIBC11_PIBC1112_SHIFT (12u) -#define GPIO_PIBC11_PIBC1113_SHIFT (13u) -#define GPIO_PIBC11_PIBC1114_SHIFT (14u) -#define GPIO_PIBC11_PIBC1115_SHIFT (15u) - -#define GPIO_PBDC11_PBDC110_SHIFT (0u) -#define GPIO_PBDC11_PBDC111_SHIFT (1u) -#define GPIO_PBDC11_PBDC112_SHIFT (2u) -#define GPIO_PBDC11_PBDC113_SHIFT (3u) -#define GPIO_PBDC11_PBDC114_SHIFT (4u) -#define GPIO_PBDC11_PBDC115_SHIFT (5u) -#define GPIO_PBDC11_PBDC116_SHIFT (6u) -#define GPIO_PBDC11_PBDC117_SHIFT (7u) -#define GPIO_PBDC11_PBDC118_SHIFT (8u) -#define GPIO_PBDC11_PBDC119_SHIFT (9u) -#define GPIO_PBDC11_PBDC1110_SHIFT (10u) -#define GPIO_PBDC11_PBDC1111_SHIFT (11u) -#define GPIO_PBDC11_PBDC1112_SHIFT (12u) -#define GPIO_PBDC11_PBDC1113_SHIFT (13u) -#define GPIO_PBDC11_PBDC1114_SHIFT (14u) -#define GPIO_PBDC11_PBDC1115_SHIFT (15u) - -#define GPIO_PIPC11_PIPC110_SHIFT (0u) -#define GPIO_PIPC11_PIPC111_SHIFT (1u) -#define GPIO_PIPC11_PIPC112_SHIFT (2u) -#define GPIO_PIPC11_PIPC113_SHIFT (3u) -#define GPIO_PIPC11_PIPC114_SHIFT (4u) -#define GPIO_PIPC11_PIPC115_SHIFT (5u) -#define GPIO_PIPC11_PIPC116_SHIFT (6u) -#define GPIO_PIPC11_PIPC117_SHIFT (7u) -#define GPIO_PIPC11_PIPC118_SHIFT (8u) -#define GPIO_PIPC11_PIPC119_SHIFT (9u) -#define GPIO_PIPC11_PIPC1110_SHIFT (10u) -#define GPIO_PIPC11_PIPC1111_SHIFT (11u) -#define GPIO_PIPC11_PIPC1112_SHIFT (12u) -#define GPIO_PIPC11_PIPC1113_SHIFT (13u) -#define GPIO_PIPC11_PIPC1114_SHIFT (14u) -#define GPIO_PIPC11_PIPC1115_SHIFT (15u) - - -#endif /* GPIO_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h deleted file mode 100644 index e1b95cb265c..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h +++ /dev/null @@ -1,11236 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : intc_iobitmask.h -* $Rev: 1115 $ -* $Date:: 2014-07-09 15:35:02 +0900#$ -* Description : INTC register define header -*******************************************************************************/ -#ifndef INTC_IOBITMASK_H -#define INTC_IOBITMASK_H - -/* ==== Mask values for IO registers ==== */ -#define INTC_ICDDCR_Enable (0x00000001uL) - -#define INTC_ICDICTR_ITLinesNumber (0x0000001FuL) -#define INTC_ICDICTR_CPUNumber (0x000000E0uL) -#define INTC_ICDICTR_SecurityExtn (0x00000400uL) -#define INTC_ICDICTR_LSPI (0x0000F800uL) - -#define INTC_ICDIIDR_Implementer (0x00000FFFuL) -#define INTC_ICDIIDR_Revision (0x0000F000uL) -#define INTC_ICDIIDR_Variant (0x000F0000uL) -#define INTC_ICDIIDR_ProductID (0xFF000000uL) - -#define INTC_ICDISR0_SW0 (0x00000001uL) -#define INTC_ICDISR0_SW1 (0x00000002uL) -#define INTC_ICDISR0_SW2 (0x00000004uL) -#define INTC_ICDISR0_SW3 (0x00000008uL) -#define INTC_ICDISR0_SW4 (0x00000010uL) -#define INTC_ICDISR0_SW5 (0x00000020uL) -#define INTC_ICDISR0_SW6 (0x00000040uL) -#define INTC_ICDISR0_SW7 (0x00000080uL) -#define INTC_ICDISR0_SW8 (0x00000100uL) -#define INTC_ICDISR0_SW9 (0x00000200uL) -#define INTC_ICDISR0_SW10 (0x00000400uL) -#define INTC_ICDISR0_SW11 (0x00000800uL) -#define INTC_ICDISR0_SW12 (0x00001000uL) -#define INTC_ICDISR0_SW13 (0x00002000uL) -#define INTC_ICDISR0_SW14 (0x00004000uL) -#define INTC_ICDISR0_SW15 (0x00008000uL) -#define INTC_ICDISR0_PMUIRQ0 (0x00010000uL) -#define INTC_ICDISR0_COMMRX0 (0x00020000uL) -#define INTC_ICDISR0_COMMTX0 (0x00040000uL) -#define INTC_ICDISR0_CTIIRQ0 (0x00080000uL) - -#define INTC_ICDISR1_IRQ0 (0x00000001uL) -#define INTC_ICDISR1_IRQ1 (0x00000002uL) -#define INTC_ICDISR1_IRQ2 (0x00000004uL) -#define INTC_ICDISR1_IRQ3 (0x00000008uL) -#define INTC_ICDISR1_IRQ4 (0x00000010uL) -#define INTC_ICDISR1_IRQ5 (0x00000020uL) -#define INTC_ICDISR1_IRQ6 (0x00000040uL) -#define INTC_ICDISR1_IRQ7 (0x00000080uL) -#define INTC_ICDISR1_PL310ERR (0x00000100uL) -#define INTC_ICDISR1_DMAINT0 (0x00000200uL) -#define INTC_ICDISR1_DMAINT1 (0x00000400uL) -#define INTC_ICDISR1_DMAINT2 (0x00000800uL) -#define INTC_ICDISR1_DMAINT3 (0x00001000uL) -#define INTC_ICDISR1_DMAINT4 (0x00002000uL) -#define INTC_ICDISR1_DMAINT5 (0x00004000uL) -#define INTC_ICDISR1_DMAINT6 (0x00008000uL) -#define INTC_ICDISR1_DMAINT7 (0x00010000uL) -#define INTC_ICDISR1_DMAINT8 (0x00020000uL) -#define INTC_ICDISR1_DMAINT9 (0x00040000uL) -#define INTC_ICDISR1_DMAINT10 (0x00080000uL) -#define INTC_ICDISR1_DMAINT11 (0x00100000uL) -#define INTC_ICDISR1_DMAINT12 (0x00200000uL) -#define INTC_ICDISR1_DMAINT13 (0x00400000uL) -#define INTC_ICDISR1_DMAINT14 (0x00800000uL) -#define INTC_ICDISR1_DMAINT15 (0x01000000uL) -#define INTC_ICDISR1_DMAERR (0x02000000uL) - -#define INTC_ICDISR2_USBI0 (0x00000200uL) -#define INTC_ICDISR2_USBI1 (0x00000400uL) -#define INTC_ICDISR2_S0_VI_VSYNC0 (0x00000800uL) -#define INTC_ICDISR2_S0_LO_VSYNC0 (0x00001000uL) -#define INTC_ICDISR2_S0_VSYNCERR0 (0x00002000uL) -#define INTC_ICDISR2_GR3_VLINE0 (0x00004000uL) -#define INTC_ICDISR2_S0_VFIELD0 (0x00008000uL) -#define INTC_ICDISR2_IV1_VBUFERR0 (0x00010000uL) -#define INTC_ICDISR2_IV3_VBUFERR0 (0x00020000uL) -#define INTC_ICDISR2_IV5_VBUFERR0 (0x00040000uL) -#define INTC_ICDISR2_IV6_VBUFERR0 (0x00080000uL) -#define INTC_ICDISR2_S0_WLINE0 (0x00100000uL) -#define INTC_ICDISR2_S1_VI_VSYNC0 (0x00200000uL) -#define INTC_ICDISR2_S1_LO_VSYNC0 (0x00400000uL) -#define INTC_ICDISR2_S1_VSYNCERR0 (0x00800000uL) -#define INTC_ICDISR2_S1_VFIELD0 (0x01000000uL) -#define INTC_ICDISR2_IV2_VBUFERR0 (0x02000000uL) -#define INTC_ICDISR2_IV4_VBUFERR0 (0x04000000uL) -#define INTC_ICDISR2_S1_WLINE0 (0x08000000uL) -#define INTC_ICDISR2_OIR_VI_VSYNC0 (0x10000000uL) -#define INTC_ICDISR2_OIR_LO_VSYNC0 (0x20000000uL) -#define INTC_ICDISR2_OIR_VSYNCERR0 (0x40000000uL) -#define INTC_ICDISR2_OIR_VFIELD0 (0x80000000uL) - -#define INTC_ICDISR3_IV7_VBUFERR0 (0x00000001uL) -#define INTC_ICDISR3_IV8_VBUFERR0 (0x00000002uL) -#define INTC_ICDISR3_S0_VI_VSYNC1 (0x00000008uL) -#define INTC_ICDISR3_S0_LO_VSYNC1 (0x00000010uL) -#define INTC_ICDISR3_S0_VSYNCERR1 (0x00000020uL) -#define INTC_ICDISR3_GR3_VLINE1 (0x00000040uL) -#define INTC_ICDISR3_S0_VFIELD1 (0x00000080uL) -#define INTC_ICDISR3_IV1_VBUFERR1 (0x00000100uL) -#define INTC_ICDISR3_IV3_VBUFERR1 (0x00000200uL) -#define INTC_ICDISR3_IV5_VBUFERR1 (0x00000400uL) -#define INTC_ICDISR3_IV6_VBUFERR1 (0x00000800uL) -#define INTC_ICDISR3_S0_WLINE1 (0x00001000uL) -#define INTC_ICDISR3_S1_VI_VSYNC1 (0x00002000uL) -#define INTC_ICDISR3_S1_LO_VSYNC1 (0x00004000uL) -#define INTC_ICDISR3_S1_VSYNCERR1 (0x00008000uL) -#define INTC_ICDISR3_S1_VFIELD1 (0x00010000uL) -#define INTC_ICDISR3_IV2_VBUFERR1 (0x00020000uL) -#define INTC_ICDISR3_IV4_VBUFERR1 (0x00040000uL) -#define INTC_ICDISR3_S1_WLINE1 (0x00080000uL) -#define INTC_ICDISR3_OIR_VI_VSYNC1 (0x00100000uL) -#define INTC_ICDISR3_OIR_LO_VSYNC1 (0x00200000uL) -#define INTC_ICDISR3_OIR_VLINE1 (0x00400000uL) -#define INTC_ICDISR3_OIR_VFIELD1 (0x00800000uL) -#define INTC_ICDISR3_IV7_VBUFERR1 (0x01000000uL) -#define INTC_ICDISR3_IV8_VBUFERR1 (0x02000000uL) -#define INTC_ICDISR3_IMRDI (0x08000000uL) -#define INTC_ICDISR3_IMR2I0 (0x10000000uL) -#define INTC_ICDISR3_IMR2I1 (0x20000000uL) -#define INTC_ICDISR3_JEDI (0x40000000uL) -#define INTC_ICDISR3_JDTI (0x80000000uL) - -#define INTC_ICDISR4_CMP0 (0x00000001uL) -#define INTC_ICDISR4_CMP1 (0x00000002uL) -#define INTC_ICDISR4_INT0 (0x00000004uL) -#define INTC_ICDISR4_INT1 (0x00000008uL) -#define INTC_ICDISR4_INT2 (0x00000010uL) -#define INTC_ICDISR4_INT3 (0x00000020uL) -#define INTC_ICDISR4_OSTM0TINT (0x00000040uL) -#define INTC_ICDISR4_OSTM1TINT (0x00000080uL) -#define INTC_ICDISR4_CMI (0x00000100uL) -#define INTC_ICDISR4_WTOUT (0x00000200uL) -#define INTC_ICDISR4_ITI (0x00000400uL) -#define INTC_ICDISR4_TGI0A (0x00000800uL) -#define INTC_ICDISR4_TGI0B (0x00001000uL) -#define INTC_ICDISR4_TGI0C (0x00002000uL) -#define INTC_ICDISR4_TGI0D (0x00004000uL) -#define INTC_ICDISR4_TGI0V (0x00008000uL) -#define INTC_ICDISR4_TGI0E (0x00010000uL) -#define INTC_ICDISR4_TGI0F (0x00020000uL) -#define INTC_ICDISR4_TGI1A (0x00040000uL) -#define INTC_ICDISR4_TGI1B (0x00080000uL) -#define INTC_ICDISR4_TGI1V (0x00100000uL) -#define INTC_ICDISR4_TGI1U (0x00200000uL) -#define INTC_ICDISR4_TGI2A (0x00400000uL) -#define INTC_ICDISR4_TGI2B (0x00800000uL) -#define INTC_ICDISR4_TGI2V (0x01000000uL) -#define INTC_ICDISR4_TGI2U (0x02000000uL) -#define INTC_ICDISR4_TGI3A (0x04000000uL) -#define INTC_ICDISR4_TGI3B (0x08000000uL) -#define INTC_ICDISR4_TGI3C (0x10000000uL) -#define INTC_ICDISR4_TGI3D (0x20000000uL) -#define INTC_ICDISR4_TGI3V (0x40000000uL) -#define INTC_ICDISR4_TGI4A (0x80000000uL) - -#define INTC_ICDISR5_TGI4B (0x00000001uL) -#define INTC_ICDISR5_TGI4C (0x00000002uL) -#define INTC_ICDISR5_TGI4D (0x00000004uL) -#define INTC_ICDISR5_TGI4V (0x00000008uL) -#define INTC_ICDISR5_CMI1 (0x00000010uL) -#define INTC_ICDISR5_CMI2 (0x00000020uL) -#define INTC_ICDISR5_SGDEI0 (0x00000040uL) -#define INTC_ICDISR5_SGDEI1 (0x00000080uL) -#define INTC_ICDISR5_SGDEI2 (0x00000100uL) -#define INTC_ICDISR5_SGDEI3 (0x00000200uL) -#define INTC_ICDISR5_ADI (0x00000400uL) -#define INTC_ICDISR5_LMTI (0x00000800uL) -#define INTC_ICDISR5_SSII0 (0x00001000uL) -#define INTC_ICDISR5_SSIRXI0 (0x00002000uL) -#define INTC_ICDISR5_SSITXI0 (0x00004000uL) -#define INTC_ICDISR5_SSII1 (0x00008000uL) -#define INTC_ICDISR5_SSIRXI1 (0x00010000uL) -#define INTC_ICDISR5_SSITXI1 (0x00020000uL) -#define INTC_ICDISR5_SSII2 (0x00040000uL) -#define INTC_ICDISR5_SSIRTI2 (0x00080000uL) -#define INTC_ICDISR5_SSII3 (0x00100000uL) -#define INTC_ICDISR5_SSIRXI3 (0x00200000uL) -#define INTC_ICDISR5_SSITXI3 (0x00400000uL) -#define INTC_ICDISR5_SSII4 (0x00800000uL) -#define INTC_ICDISR5_SSIRTI4 (0x01000000uL) -#define INTC_ICDISR5_SSII5 (0x02000000uL) -#define INTC_ICDISR5_SSIRXI5 (0x04000000uL) -#define INTC_ICDISR5_SSITXI5 (0x08000000uL) -#define INTC_ICDISR5_SPDIFI (0x10000000uL) -#define INTC_ICDISR5_INTIICTEI0 (0x20000000uL) -#define INTC_ICDISR5_INTIICRI0 (0x40000000uL) -#define INTC_ICDISR5_INTIICTI0 (0x80000000uL) - -#define INTC_ICDISR6_INTIICSPI0 (0x00000001uL) -#define INTC_ICDISR6_INTIICSTI0 (0x00000002uL) -#define INTC_ICDISR6_INTIICNAKI0 (0x00000004uL) -#define INTC_ICDISR6_INTIICALI0 (0x00000008uL) -#define INTC_ICDISR6_INTIICTMOI0 (0x00000010uL) -#define INTC_ICDISR6_INTIICTEI1 (0x00000020uL) -#define INTC_ICDISR6_INTIICRI1 (0x00000040uL) -#define INTC_ICDISR6_INTIICTI1 (0x00000080uL) -#define INTC_ICDISR6_INTIICSPI1 (0x00000100uL) -#define INTC_ICDISR6_INTIICSTI1 (0x00000200uL) -#define INTC_ICDISR6_INTIICNAKI1 (0x00000400uL) -#define INTC_ICDISR6_INTIICALI1 (0x00000800uL) -#define INTC_ICDISR6_INTIICTMOI1 (0x00001000uL) -#define INTC_ICDISR6_INTIICTEI2 (0x00002000uL) -#define INTC_ICDISR6_INTIICRI2 (0x00004000uL) -#define INTC_ICDISR6_INTIICTI2 (0x00008000uL) -#define INTC_ICDISR6_INTIICSPI2 (0x00010000uL) -#define INTC_ICDISR6_INTIICSTI2 (0x00020000uL) -#define INTC_ICDISR6_INTIICNAKI2 (0x00040000uL) -#define INTC_ICDISR6_INTIICALI2 (0x00080000uL) -#define INTC_ICDISR6_INTIICTMOI2 (0x00100000uL) -#define INTC_ICDISR6_INTIICTEI3 (0x00200000uL) -#define INTC_ICDISR6_INTIICRI3 (0x00400000uL) -#define INTC_ICDISR6_INTIICTI3 (0x00800000uL) -#define INTC_ICDISR6_INTIICSPI3 (0x01000000uL) -#define INTC_ICDISR6_INTIICSTI3 (0x02000000uL) -#define INTC_ICDISR6_INTIICNAKI3 (0x04000000uL) -#define INTC_ICDISR6_INTIICALI3 (0x08000000uL) -#define INTC_ICDISR6_INTIICTMOI3 (0x10000000uL) -#define INTC_ICDISR6_BRI0 (0x20000000uL) -#define INTC_ICDISR6_ERI0 (0x40000000uL) -#define INTC_ICDISR6_RXI0 (0x80000000uL) - -#define INTC_ICDISR7_TXI0 (0x00000001uL) -#define INTC_ICDISR7_BRI1 (0x00000002uL) -#define INTC_ICDISR7_ERI1 (0x00000004uL) -#define INTC_ICDISR7_RXI1 (0x00000008uL) -#define INTC_ICDISR7_TXI1 (0x00000010uL) -#define INTC_ICDISR7_BRI2 (0x00000020uL) -#define INTC_ICDISR7_ERI2 (0x00000040uL) -#define INTC_ICDISR7_RXI2 (0x00000080uL) -#define INTC_ICDISR7_TXI2 (0x00000100uL) -#define INTC_ICDISR7_BRI3 (0x00000200uL) -#define INTC_ICDISR7_ERI3 (0x00000400uL) -#define INTC_ICDISR7_RXI3 (0x00000800uL) -#define INTC_ICDISR7_TXI3 (0x00001000uL) -#define INTC_ICDISR7_BRI4 (0x00002000uL) -#define INTC_ICDISR7_ERI4 (0x00004000uL) -#define INTC_ICDISR7_RXI4 (0x00008000uL) -#define INTC_ICDISR7_TXI4 (0x00010000uL) -#define INTC_ICDISR7_BRI5 (0x00020000uL) -#define INTC_ICDISR7_ERI5 (0x00040000uL) -#define INTC_ICDISR7_RXI5 (0x00080000uL) -#define INTC_ICDISR7_TXI5 (0x00100000uL) -#define INTC_ICDISR7_BRI6 (0x00200000uL) -#define INTC_ICDISR7_ERI6 (0x00400000uL) -#define INTC_ICDISR7_RXI6 (0x00800000uL) -#define INTC_ICDISR7_TXI6 (0x01000000uL) -#define INTC_ICDISR7_BRI7 (0x02000000uL) -#define INTC_ICDISR7_ERI7 (0x04000000uL) -#define INTC_ICDISR7_RXI7 (0x08000000uL) -#define INTC_ICDISR7_TXI7 (0x10000000uL) -#define INTC_ICDISR7_INTRCANGERR (0x20000000uL) -#define INTC_ICDISR7_INTRCANGRECC (0x40000000uL) -#define INTC_ICDISR7_INTRCAN0REC (0x80000000uL) - -#define INTC_ICDISR8_INTRCAN0ERR (0x00000001uL) -#define INTC_ICDISR8_INTRCAN0TRX (0x00000002uL) -#define INTC_ICDISR8_INTRCAN1REC (0x00000004uL) -#define INTC_ICDISR8_INTRCAN1ERR (0x00000008uL) -#define INTC_ICDISR8_INTRCAN1TRX (0x00000010uL) -#define INTC_ICDISR8_INTRCAN2REC (0x00000020uL) -#define INTC_ICDISR8_INTRCAN2ERR (0x00000040uL) -#define INTC_ICDISR8_INTRCAN2TRX (0x00000080uL) -#define INTC_ICDISR8_INTRCAN3REC (0x00000100uL) -#define INTC_ICDISR8_INTRCAN3ERR (0x00000200uL) -#define INTC_ICDISR8_INTRCAN3TRX (0x00000400uL) -#define INTC_ICDISR8_INTRCAN4REC (0x00000800uL) -#define INTC_ICDISR8_INTRCAN4ERR (0x00001000uL) -#define INTC_ICDISR8_INTRCAN4TRX (0x00002000uL) -#define INTC_ICDISR8_SPEI0 (0x00004000uL) -#define INTC_ICDISR8_SPRI0 (0x00008000uL) -#define INTC_ICDISR8_SPTI0 (0x00010000uL) -#define INTC_ICDISR8_SPEI1 (0x00020000uL) -#define INTC_ICDISR8_SPRI1 (0x00040000uL) -#define INTC_ICDISR8_SPTI1 (0x00080000uL) -#define INTC_ICDISR8_SPEI2 (0x00100000uL) -#define INTC_ICDISR8_SPRI2 (0x00200000uL) -#define INTC_ICDISR8_SPTI2 (0x00400000uL) -#define INTC_ICDISR8_SPEI3 (0x00800000uL) -#define INTC_ICDISR8_SPRI3 (0x01000000uL) -#define INTC_ICDISR8_SPTI3 (0x02000000uL) -#define INTC_ICDISR8_SPEI4 (0x04000000uL) -#define INTC_ICDISR8_SPRI4 (0x08000000uL) -#define INTC_ICDISR8_SPTI4 (0x10000000uL) -#define INTC_ICDISR8_IEBBTD (0x20000000uL) -#define INTC_ICDISR8_IEBBTERR (0x40000000uL) -#define INTC_ICDISR8_IEBBTSTA (0x80000000uL) - -#define INTC_ICDISR9_IEBBTV (0x00000001uL) -#define INTC_ICDISR9_ISY (0x00000002uL) -#define INTC_ICDISR9_IERR (0x00000004uL) -#define INTC_ICDISR9_ITARG (0x00000008uL) -#define INTC_ICDISR9_ISEC (0x00000010uL) -#define INTC_ICDISR9_IBUF (0x00000020uL) -#define INTC_ICDISR9_IREADY (0x00000040uL) -#define INTC_ICDISR9_FLSTE (0x00000080uL) -#define INTC_ICDISR9_FLTENDI (0x00000100uL) -#define INTC_ICDISR9_FLTREQ0I (0x00000200uL) -#define INTC_ICDISR9_FLTREQ1I (0x00000400uL) -#define INTC_ICDISR9_MMC0 (0x00000800uL) -#define INTC_ICDISR9_MMC1 (0x00001000uL) -#define INTC_ICDISR9_MMC2 (0x00002000uL) -#define INTC_ICDISR9_SDHI0_3 (0x00004000uL) -#define INTC_ICDISR9_SDHI0_0 (0x00008000uL) -#define INTC_ICDISR9_SDHI0_1 (0x00010000uL) -#define INTC_ICDISR9_SDHI1_3 (0x00020000uL) -#define INTC_ICDISR9_SDHI1_0 (0x00040000uL) -#define INTC_ICDISR9_SDHI1_1 (0x00080000uL) -#define INTC_ICDISR9_ARM (0x00100000uL) -#define INTC_ICDISR9_PRD (0x00200000uL) -#define INTC_ICDISR9_CUP (0x00400000uL) -#define INTC_ICDISR9_SCUAI0 (0x00800000uL) -#define INTC_ICDISR9_SCUAI1 (0x01000000uL) -#define INTC_ICDISR9_SCUFDI0 (0x02000000uL) -#define INTC_ICDISR9_SCUFDI1 (0x04000000uL) -#define INTC_ICDISR9_SCUFDI2 (0x08000000uL) -#define INTC_ICDISR9_SCUFDI3 (0x10000000uL) -#define INTC_ICDISR9_SCUFUI0 (0x20000000uL) -#define INTC_ICDISR9_SCUFUI1 (0x40000000uL) -#define INTC_ICDISR9_SCUFUI2 (0x80000000uL) - -#define INTC_ICDISR10_SCUFUI3 (0x00000001uL) -#define INTC_ICDISR10_SCUDVI0 (0x00000002uL) -#define INTC_ICDISR10_SCUDVI1 (0x00000004uL) -#define INTC_ICDISR10_SCUDVI2 (0x00000008uL) -#define INTC_ICDISR10_SCUDVI3 (0x00000010uL) -#define INTC_ICDISR10_MLB_CINT (0x00000020uL) -#define INTC_ICDISR10_MLB_SINT (0x00000040uL) -#define INTC_ICDISR10_DRC0 (0x00000080uL) -#define INTC_ICDISR10_DRC1 (0x00000100uL) -#define INTC_ICDISR10_LINI0_INT_T (0x00000800uL) -#define INTC_ICDISR10_LINI0_INT_R (0x00001000uL) -#define INTC_ICDISR10_LINI0_INT_S (0x00002000uL) -#define INTC_ICDISR10_LINI0_INT_M (0x00004000uL) -#define INTC_ICDISR10_LINI1_INT_T (0x00008000uL) -#define INTC_ICDISR10_LINI1_INT_R (0x00010000uL) -#define INTC_ICDISR10_LINI1_INT_S (0x00020000uL) -#define INTC_ICDISR10_LINI1_INT_M (0x00040000uL) -#define INTC_ICDISR10_ERI0 (0x08000000uL) -#define INTC_ICDISR10_RXI0 (0x10000000uL) -#define INTC_ICDISR10_TXI0 (0x20000000uL) -#define INTC_ICDISR10_TEI0 (0x40000000uL) -#define INTC_ICDISR10_ERI1 (0x80000000uL) - -#define INTC_ICDISR11_RXI1 (0x00000001uL) -#define INTC_ICDISR11_TXI1 (0x00000002uL) -#define INTC_ICDISR11_TEI1 (0x00000004uL) -#define INTC_ICDISR11_AVBI_DATA (0x00000008uL) -#define INTC_ICDISR11_AVBI_ERROR (0x00000010uL) -#define INTC_ICDISR11_AVBI_MANAGE (0x00000020uL) -#define INTC_ICDISR11_AVBI_MAC (0x00000040uL) -#define INTC_ICDISR11_ETHERI (0x00000080uL) -#define INTC_ICDISR11_CEUI (0x00001000uL) -#define INTC_ICDISR11_H2XMLB_ERRINT (0x20000000uL) -#define INTC_ICDISR11_H2XIC1_ERRINT (0x40000000uL) -#define INTC_ICDISR11_X2HPERI1_ERRINT (0x80000000uL) - -#define INTC_ICDISR12_X2HPERI2_ERRINT (0x00000001uL) -#define INTC_ICDISR12_X2HPERI34_ERRINT (0x00000002uL) -#define INTC_ICDISR12_X2HPERI5_ERRINT (0x00000004uL) -#define INTC_ICDISR12_X2HPERI67_ERRINT (0x00000008uL) -#define INTC_ICDISR12_X2HDBGR_ERRINT (0x00000010uL) -#define INTC_ICDISR12_X2HBSC_ERRINT (0x00000020uL) -#define INTC_ICDISR12_X2HSPI1_ERRINT (0x00000040uL) -#define INTC_ICDISR12_X2HSPI2_ERRINT (0x00000080uL) -#define INTC_ICDISR12_PRRI (0x00000100uL) -#define INTC_ICDISR12_IFEI0 (0x00000200uL) -#define INTC_ICDISR12_OFFI0 (0x00000400uL) -#define INTC_ICDISR12_PFVEI0 (0x00000800uL) -#define INTC_ICDISR12_IFEI1 (0x00001000uL) -#define INTC_ICDISR12_OFFI1 (0x00002000uL) -#define INTC_ICDISR12_PFVEI1 (0x00004000uL) - -#define INTC_ICDISR13_TINT0 (0x00000001uL) -#define INTC_ICDISR13_TINT1 (0x00000002uL) -#define INTC_ICDISR13_TINT2 (0x00000004uL) -#define INTC_ICDISR13_TINT3 (0x00000008uL) -#define INTC_ICDISR13_TINT4 (0x00000010uL) -#define INTC_ICDISR13_TINT5 (0x00000020uL) -#define INTC_ICDISR13_TINT6 (0x00000040uL) -#define INTC_ICDISR13_TINT7 (0x00000080uL) -#define INTC_ICDISR13_TINT8 (0x00000100uL) -#define INTC_ICDISR13_TINT9 (0x00000200uL) -#define INTC_ICDISR13_TINT10 (0x00000400uL) -#define INTC_ICDISR13_TINT11 (0x00000800uL) -#define INTC_ICDISR13_TINT12 (0x00001000uL) -#define INTC_ICDISR13_TINT13 (0x00002000uL) -#define INTC_ICDISR13_TINT14 (0x00004000uL) -#define INTC_ICDISR13_TINT15 (0x00008000uL) -#define INTC_ICDISR13_TINT16 (0x00010000uL) -#define INTC_ICDISR13_TINT17 (0x00020000uL) -#define INTC_ICDISR13_TINT18 (0x00040000uL) -#define INTC_ICDISR13_TINT19 (0x00080000uL) -#define INTC_ICDISR13_TINT20 (0x00100000uL) -#define INTC_ICDISR13_TINT21 (0x00200000uL) -#define INTC_ICDISR13_TINT22 (0x00400000uL) -#define INTC_ICDISR13_TINT23 (0x00800000uL) -#define INTC_ICDISR13_TINT24 (0x01000000uL) -#define INTC_ICDISR13_TINT25 (0x02000000uL) -#define INTC_ICDISR13_TINT26 (0x04000000uL) -#define INTC_ICDISR13_TINT27 (0x08000000uL) -#define INTC_ICDISR13_TINT28 (0x10000000uL) -#define INTC_ICDISR13_TINT29 (0x20000000uL) -#define INTC_ICDISR13_TINT30 (0x40000000uL) -#define INTC_ICDISR13_TINT31 (0x80000000uL) - -#define INTC_ICDISR14_TINT32 (0x00000001uL) -#define INTC_ICDISR14_TINT33 (0x00000002uL) -#define INTC_ICDISR14_TINT34 (0x00000004uL) -#define INTC_ICDISR14_TINT35 (0x00000008uL) -#define INTC_ICDISR14_TINT36 (0x00000010uL) -#define INTC_ICDISR14_TINT37 (0x00000020uL) -#define INTC_ICDISR14_TINT38 (0x00000040uL) -#define INTC_ICDISR14_TINT39 (0x00000080uL) -#define INTC_ICDISR14_TINT40 (0x00000100uL) -#define INTC_ICDISR14_TINT41 (0x00000200uL) -#define INTC_ICDISR14_TINT42 (0x00000400uL) -#define INTC_ICDISR14_TINT43 (0x00000800uL) -#define INTC_ICDISR14_TINT44 (0x00001000uL) -#define INTC_ICDISR14_TINT45 (0x00002000uL) -#define INTC_ICDISR14_TINT46 (0x00004000uL) -#define INTC_ICDISR14_TINT47 (0x00008000uL) -#define INTC_ICDISR14_TINT48 (0x00010000uL) -#define INTC_ICDISR14_TINT49 (0x00020000uL) -#define INTC_ICDISR14_TINT50 (0x00040000uL) -#define INTC_ICDISR14_TINT51 (0x00080000uL) -#define INTC_ICDISR14_TINT52 (0x00100000uL) -#define INTC_ICDISR14_TINT53 (0x00200000uL) -#define INTC_ICDISR14_TINT54 (0x00400000uL) -#define INTC_ICDISR14_TINT55 (0x00800000uL) -#define INTC_ICDISR14_TINT56 (0x01000000uL) -#define INTC_ICDISR14_TINT57 (0x02000000uL) -#define INTC_ICDISR14_TINT58 (0x04000000uL) -#define INTC_ICDISR14_TINT59 (0x08000000uL) -#define INTC_ICDISR14_TINT60 (0x10000000uL) -#define INTC_ICDISR14_TINT61 (0x20000000uL) -#define INTC_ICDISR14_TINT62 (0x40000000uL) -#define INTC_ICDISR14_TINT63 (0x80000000uL) - -#define INTC_ICDISR15_TINT64 (0x00000001uL) -#define INTC_ICDISR15_TINT65 (0x00000002uL) -#define INTC_ICDISR15_TINT66 (0x00000004uL) -#define INTC_ICDISR15_TINT67 (0x00000008uL) -#define INTC_ICDISR15_TINT68 (0x00000010uL) -#define INTC_ICDISR15_TINT69 (0x00000020uL) -#define INTC_ICDISR15_TINT70 (0x00000040uL) -#define INTC_ICDISR15_TINT71 (0x00000080uL) -#define INTC_ICDISR15_TINT72 (0x00000100uL) -#define INTC_ICDISR15_TINT73 (0x00000200uL) -#define INTC_ICDISR15_TINT74 (0x00000400uL) -#define INTC_ICDISR15_TINT75 (0x00000800uL) -#define INTC_ICDISR15_TINT76 (0x00001000uL) -#define INTC_ICDISR15_TINT77 (0x00002000uL) -#define INTC_ICDISR15_TINT78 (0x00004000uL) -#define INTC_ICDISR15_TINT79 (0x00008000uL) -#define INTC_ICDISR15_TINT80 (0x00010000uL) -#define INTC_ICDISR15_TINT81 (0x00020000uL) -#define INTC_ICDISR15_TINT82 (0x00040000uL) -#define INTC_ICDISR15_TINT83 (0x00080000uL) -#define INTC_ICDISR15_TINT84 (0x00100000uL) -#define INTC_ICDISR15_TINT85 (0x00200000uL) -#define INTC_ICDISR15_TINT86 (0x00400000uL) -#define INTC_ICDISR15_TINT87 (0x00800000uL) -#define INTC_ICDISR15_TINT88 (0x01000000uL) -#define INTC_ICDISR15_TINT89 (0x02000000uL) -#define INTC_ICDISR15_TINT90 (0x04000000uL) -#define INTC_ICDISR15_TINT91 (0x08000000uL) -#define INTC_ICDISR15_TINT92 (0x10000000uL) -#define INTC_ICDISR15_TINT93 (0x20000000uL) -#define INTC_ICDISR15_TINT94 (0x40000000uL) -#define INTC_ICDISR15_TINT95 (0x80000000uL) - -#define INTC_ICDISR16_TINT96 (0x00000001uL) -#define INTC_ICDISR16_TINT97 (0x00000002uL) -#define INTC_ICDISR16_TINT98 (0x00000004uL) -#define INTC_ICDISR16_TINT99 (0x00000008uL) -#define INTC_ICDISR16_TINT100 (0x00000010uL) -#define INTC_ICDISR16_TINT101 (0x00000020uL) -#define INTC_ICDISR16_TINT102 (0x00000040uL) -#define INTC_ICDISR16_TINT103 (0x00000080uL) -#define INTC_ICDISR16_TINT104 (0x00000100uL) -#define INTC_ICDISR16_TINT105 (0x00000200uL) -#define INTC_ICDISR16_TINT106 (0x00000400uL) -#define INTC_ICDISR16_TINT107 (0x00000800uL) -#define INTC_ICDISR16_TINT108 (0x00001000uL) -#define INTC_ICDISR16_TINT109 (0x00002000uL) -#define INTC_ICDISR16_TINT110 (0x00004000uL) -#define INTC_ICDISR16_TINT111 (0x00008000uL) -#define INTC_ICDISR16_TINT112 (0x00010000uL) -#define INTC_ICDISR16_TINT113 (0x00020000uL) -#define INTC_ICDISR16_TINT114 (0x00040000uL) -#define INTC_ICDISR16_TINT115 (0x00080000uL) -#define INTC_ICDISR16_TINT116 (0x00100000uL) -#define INTC_ICDISR16_TINT117 (0x00200000uL) -#define INTC_ICDISR16_TINT118 (0x00400000uL) -#define INTC_ICDISR16_TINT119 (0x00800000uL) -#define INTC_ICDISR16_TINT120 (0x01000000uL) -#define INTC_ICDISR16_TINT121 (0x02000000uL) -#define INTC_ICDISR16_TINT122 (0x04000000uL) -#define INTC_ICDISR16_TINT123 (0x08000000uL) -#define INTC_ICDISR16_TINT124 (0x10000000uL) -#define INTC_ICDISR16_TINT125 (0x20000000uL) -#define INTC_ICDISR16_TINT126 (0x40000000uL) -#define INTC_ICDISR16_TINT127 (0x80000000uL) - -#define INTC_ICDISR17_TINT128 (0x00000001uL) -#define INTC_ICDISR17_TINT129 (0x00000002uL) -#define INTC_ICDISR17_TINT130 (0x00000004uL) -#define INTC_ICDISR17_TINT131 (0x00000008uL) -#define INTC_ICDISR17_TINT132 (0x00000010uL) -#define INTC_ICDISR17_TINT133 (0x00000020uL) -#define INTC_ICDISR17_TINT134 (0x00000040uL) -#define INTC_ICDISR17_TINT135 (0x00000080uL) -#define INTC_ICDISR17_TINT136 (0x00000100uL) -#define INTC_ICDISR17_TINT137 (0x00000200uL) -#define INTC_ICDISR17_TINT138 (0x00000400uL) -#define INTC_ICDISR17_TINT139 (0x00000800uL) -#define INTC_ICDISR17_TINT140 (0x00001000uL) -#define INTC_ICDISR17_TINT141 (0x00002000uL) -#define INTC_ICDISR17_TINT142 (0x00004000uL) -#define INTC_ICDISR17_TINT143 (0x00008000uL) -#define INTC_ICDISR17_TINT144 (0x00010000uL) -#define INTC_ICDISR17_TINT145 (0x00020000uL) -#define INTC_ICDISR17_TINT146 (0x00040000uL) -#define INTC_ICDISR17_TINT147 (0x00080000uL) -#define INTC_ICDISR17_TINT148 (0x00100000uL) -#define INTC_ICDISR17_TINT149 (0x00200000uL) -#define INTC_ICDISR17_TINT150 (0x00400000uL) -#define INTC_ICDISR17_TINT151 (0x00800000uL) -#define INTC_ICDISR17_TINT152 (0x01000000uL) -#define INTC_ICDISR17_TINT153 (0x02000000uL) -#define INTC_ICDISR17_TINT154 (0x04000000uL) -#define INTC_ICDISR17_TINT155 (0x08000000uL) -#define INTC_ICDISR17_TINT156 (0x10000000uL) -#define INTC_ICDISR17_TINT157 (0x20000000uL) -#define INTC_ICDISR17_TINT158 (0x40000000uL) -#define INTC_ICDISR17_TINT159 (0x80000000uL) - -#define INTC_ICDISR18_TINT160 (0x00000001uL) -#define INTC_ICDISR18_TINT161 (0x00000002uL) -#define INTC_ICDISR18_TINT162 (0x00000004uL) -#define INTC_ICDISR18_TINT163 (0x00000008uL) -#define INTC_ICDISR18_TINT164 (0x00000010uL) -#define INTC_ICDISR18_TINT165 (0x00000020uL) -#define INTC_ICDISR18_TINT166 (0x00000040uL) -#define INTC_ICDISR18_TINT167 (0x00000080uL) -#define INTC_ICDISR18_TINT168 (0x00000100uL) -#define INTC_ICDISR18_TINT169 (0x00000200uL) -#define INTC_ICDISR18_TINT170 (0x00000400uL) - -#define INTC_ICDISER0_SW0 (0x00000001uL) -#define INTC_ICDISER0_SW1 (0x00000002uL) -#define INTC_ICDISER0_SW2 (0x00000004uL) -#define INTC_ICDISER0_SW3 (0x00000008uL) -#define INTC_ICDISER0_SW4 (0x00000010uL) -#define INTC_ICDISER0_SW5 (0x00000020uL) -#define INTC_ICDISER0_SW6 (0x00000040uL) -#define INTC_ICDISER0_SW7 (0x00000080uL) -#define INTC_ICDISER0_SW8 (0x00000100uL) -#define INTC_ICDISER0_SW9 (0x00000200uL) -#define INTC_ICDISER0_SW10 (0x00000400uL) -#define INTC_ICDISER0_SW11 (0x00000800uL) -#define INTC_ICDISER0_SW12 (0x00001000uL) -#define INTC_ICDISER0_SW13 (0x00002000uL) -#define INTC_ICDISER0_SW14 (0x00004000uL) -#define INTC_ICDISER0_SW15 (0x00008000uL) -#define INTC_ICDISER0_PMUIRQ0 (0x00010000uL) -#define INTC_ICDISER0_COMMRX0 (0x00020000uL) -#define INTC_ICDISER0_COMMTX0 (0x00040000uL) -#define INTC_ICDISER0_CTIIRQ0 (0x00080000uL) - -#define INTC_ICDISER1_IRQ0 (0x00000001uL) -#define INTC_ICDISER1_IRQ1 (0x00000002uL) -#define INTC_ICDISER1_IRQ2 (0x00000004uL) -#define INTC_ICDISER1_IRQ3 (0x00000008uL) -#define INTC_ICDISER1_IRQ4 (0x00000010uL) -#define INTC_ICDISER1_IRQ5 (0x00000020uL) -#define INTC_ICDISER1_IRQ6 (0x00000040uL) -#define INTC_ICDISER1_IRQ7 (0x00000080uL) -#define INTC_ICDISER1_PL310ERR (0x00000100uL) -#define INTC_ICDISER1_DMAINT0 (0x00000200uL) -#define INTC_ICDISER1_DMAINT1 (0x00000400uL) -#define INTC_ICDISER1_DMAINT2 (0x00000800uL) -#define INTC_ICDISER1_DMAINT3 (0x00001000uL) -#define INTC_ICDISER1_DMAINT4 (0x00002000uL) -#define INTC_ICDISER1_DMAINT5 (0x00004000uL) -#define INTC_ICDISER1_DMAINT6 (0x00008000uL) -#define INTC_ICDISER1_DMAINT7 (0x00010000uL) -#define INTC_ICDISER1_DMAINT8 (0x00020000uL) -#define INTC_ICDISER1_DMAINT9 (0x00040000uL) -#define INTC_ICDISER1_DMAINT10 (0x00080000uL) -#define INTC_ICDISER1_DMAINT11 (0x00100000uL) -#define INTC_ICDISER1_DMAINT12 (0x00200000uL) -#define INTC_ICDISER1_DMAINT13 (0x00400000uL) -#define INTC_ICDISER1_DMAINT14 (0x00800000uL) -#define INTC_ICDISER1_DMAINT15 (0x01000000uL) -#define INTC_ICDISER1_DMAERR (0x02000000uL) - -#define INTC_ICDISER2_USBI0 (0x00000200uL) -#define INTC_ICDISER2_USBI1 (0x00000400uL) -#define INTC_ICDISER2_S0_VI_VSYNC0 (0x00000800uL) -#define INTC_ICDISER2_S0_LO_VSYNC0 (0x00001000uL) -#define INTC_ICDISER2_S0_VSYNCERR0 (0x00002000uL) -#define INTC_ICDISER2_GR3_VLINE0 (0x00004000uL) -#define INTC_ICDISER2_S0_VFIELD0 (0x00008000uL) -#define INTC_ICDISER2_IV1_VBUFERR0 (0x00010000uL) -#define INTC_ICDISER2_IV3_VBUFERR0 (0x00020000uL) -#define INTC_ICDISER2_IV5_VBUFERR0 (0x00040000uL) -#define INTC_ICDISER2_IV6_VBUFERR0 (0x00080000uL) -#define INTC_ICDISER2_S0_WLINE0 (0x00100000uL) -#define INTC_ICDISER2_S1_VI_VSYNC0 (0x00200000uL) -#define INTC_ICDISER2_S1_LO_VSYNC0 (0x00400000uL) -#define INTC_ICDISER2_S1_VSYNCERR0 (0x00800000uL) -#define INTC_ICDISER2_S1_VFIELD0 (0x01000000uL) -#define INTC_ICDISER2_IV2_VBUFERR0 (0x02000000uL) -#define INTC_ICDISER2_IV4_VBUFERR0 (0x04000000uL) -#define INTC_ICDISER2_S1_WLINE0 (0x08000000uL) -#define INTC_ICDISER2_OIR_VI_VSYNC0 (0x10000000uL) -#define INTC_ICDISER2_OIR_LO_VSYNC0 (0x20000000uL) -#define INTC_ICDISER2_OIR_VSYNCERR0 (0x40000000uL) -#define INTC_ICDISER2_OIR_VFIELD0 (0x80000000uL) - -#define INTC_ICDISER3_IV7_VBUFERR0 (0x00000001uL) -#define INTC_ICDISER3_IV8_VBUFERR0 (0x00000002uL) -#define INTC_ICDISER3_S0_VI_VSYNC1 (0x00000008uL) -#define INTC_ICDISER3_S0_LO_VSYNC1 (0x00000010uL) -#define INTC_ICDISER3_S0_VSYNCERR1 (0x00000020uL) -#define INTC_ICDISER3_GR3_VLINE1 (0x00000040uL) -#define INTC_ICDISER3_S0_VFIELD1 (0x00000080uL) -#define INTC_ICDISER3_IV1_VBUFERR1 (0x00000100uL) -#define INTC_ICDISER3_IV3_VBUFERR1 (0x00000200uL) -#define INTC_ICDISER3_IV5_VBUFERR1 (0x00000400uL) -#define INTC_ICDISER3_IV6_VBUFERR1 (0x00000800uL) -#define INTC_ICDISER3_S0_WLINE1 (0x00001000uL) -#define INTC_ICDISER3_S1_VI_VSYNC1 (0x00002000uL) -#define INTC_ICDISER3_S1_LO_VSYNC1 (0x00004000uL) -#define INTC_ICDISER3_S1_VSYNCERR1 (0x00008000uL) -#define INTC_ICDISER3_S1_VFIELD1 (0x00010000uL) -#define INTC_ICDISER3_IV2_VBUFERR1 (0x00020000uL) -#define INTC_ICDISER3_IV4_VBUFERR1 (0x00040000uL) -#define INTC_ICDISER3_S1_WLINE1 (0x00080000uL) -#define INTC_ICDISER3_OIR_VI_VSYNC1 (0x00100000uL) -#define INTC_ICDISER3_OIR_LO_VSYNC1 (0x00200000uL) -#define INTC_ICDISER3_OIR_VLINE1 (0x00400000uL) -#define INTC_ICDISER3_OIR_VFIELD1 (0x00800000uL) -#define INTC_ICDISER3_IV7_VBUFERR1 (0x01000000uL) -#define INTC_ICDISER3_IV8_VBUFERR1 (0x02000000uL) -#define INTC_ICDISER3_IMRDI (0x08000000uL) -#define INTC_ICDISER3_IMR2I0 (0x10000000uL) -#define INTC_ICDISER3_IMR2I1 (0x20000000uL) -#define INTC_ICDISER3_JEDI (0x40000000uL) -#define INTC_ICDISER3_JDTI (0x80000000uL) - -#define INTC_ICDISER4_CMP0 (0x00000001uL) -#define INTC_ICDISER4_CMP1 (0x00000002uL) -#define INTC_ICDISER4_INT0 (0x00000004uL) -#define INTC_ICDISER4_INT1 (0x00000008uL) -#define INTC_ICDISER4_INT2 (0x00000010uL) -#define INTC_ICDISER4_INT3 (0x00000020uL) -#define INTC_ICDISER4_OSTM0TINT (0x00000040uL) -#define INTC_ICDISER4_OSTM1TINT (0x00000080uL) -#define INTC_ICDISER4_CMI (0x00000100uL) -#define INTC_ICDISER4_WTOUT (0x00000200uL) -#define INTC_ICDISER4_ITI (0x00000400uL) -#define INTC_ICDISER4_TGI0A (0x00000800uL) -#define INTC_ICDISER4_TGI0B (0x00001000uL) -#define INTC_ICDISER4_TGI0C (0x00002000uL) -#define INTC_ICDISER4_TGI0D (0x00004000uL) -#define INTC_ICDISER4_TGI0V (0x00008000uL) -#define INTC_ICDISER4_TGI0E (0x00010000uL) -#define INTC_ICDISER4_TGI0F (0x00020000uL) -#define INTC_ICDISER4_TGI1A (0x00040000uL) -#define INTC_ICDISER4_TGI1B (0x00080000uL) -#define INTC_ICDISER4_TGI1V (0x00100000uL) -#define INTC_ICDISER4_TGI1U (0x00200000uL) -#define INTC_ICDISER4_TGI2A (0x00400000uL) -#define INTC_ICDISER4_TGI2B (0x00800000uL) -#define INTC_ICDISER4_TGI2V (0x01000000uL) -#define INTC_ICDISER4_TGI2U (0x02000000uL) -#define INTC_ICDISER4_TGI3A (0x04000000uL) -#define INTC_ICDISER4_TGI3B (0x08000000uL) -#define INTC_ICDISER4_TGI3C (0x10000000uL) -#define INTC_ICDISER4_TGI3D (0x20000000uL) -#define INTC_ICDISER4_TGI3V (0x40000000uL) -#define INTC_ICDISER4_TGI4A (0x80000000uL) - -#define INTC_ICDISER5_TGI4B (0x00000001uL) -#define INTC_ICDISER5_TGI4C (0x00000002uL) -#define INTC_ICDISER5_TGI4D (0x00000004uL) -#define INTC_ICDISER5_TGI4V (0x00000008uL) -#define INTC_ICDISER5_CMI1 (0x00000010uL) -#define INTC_ICDISER5_CMI2 (0x00000020uL) -#define INTC_ICDISER5_SGDEI0 (0x00000040uL) -#define INTC_ICDISER5_SGDEI1 (0x00000080uL) -#define INTC_ICDISER5_SGDEI2 (0x00000100uL) -#define INTC_ICDISER5_SGDEI3 (0x00000200uL) -#define INTC_ICDISER5_ADI (0x00000400uL) -#define INTC_ICDISER5_LMTI (0x00000800uL) -#define INTC_ICDISER5_SSII0 (0x00001000uL) -#define INTC_ICDISER5_SSIRXI0 (0x00002000uL) -#define INTC_ICDISER5_SSITXI0 (0x00004000uL) -#define INTC_ICDISER5_SSII1 (0x00008000uL) -#define INTC_ICDISER5_SSIRXI1 (0x00010000uL) -#define INTC_ICDISER5_SSITXI1 (0x00020000uL) -#define INTC_ICDISER5_SSII2 (0x00040000uL) -#define INTC_ICDISER5_SSIRTI2 (0x00080000uL) -#define INTC_ICDISER5_SSII3 (0x00100000uL) -#define INTC_ICDISER5_SSIRXI3 (0x00200000uL) -#define INTC_ICDISER5_SSITXI3 (0x00400000uL) -#define INTC_ICDISER5_SSII4 (0x00800000uL) -#define INTC_ICDISER5_SSIRTI4 (0x01000000uL) -#define INTC_ICDISER5_SSII5 (0x02000000uL) -#define INTC_ICDISER5_SSIRXI5 (0x04000000uL) -#define INTC_ICDISER5_SSITXI5 (0x08000000uL) -#define INTC_ICDISER5_SPDIFI (0x10000000uL) -#define INTC_ICDISER5_INTIICTEI0 (0x20000000uL) -#define INTC_ICDISER5_INTIICRI0 (0x40000000uL) -#define INTC_ICDISER5_INTIICTI0 (0x80000000uL) - -#define INTC_ICDISER6_INTIICSPI0 (0x00000001uL) -#define INTC_ICDISER6_INTIICSTI0 (0x00000002uL) -#define INTC_ICDISER6_INTIICNAKI0 (0x00000004uL) -#define INTC_ICDISER6_INTIICALI0 (0x00000008uL) -#define INTC_ICDISER6_INTIICTMOI0 (0x00000010uL) -#define INTC_ICDISER6_INTIICTEI1 (0x00000020uL) -#define INTC_ICDISER6_INTIICRI1 (0x00000040uL) -#define INTC_ICDISER6_INTIICTI1 (0x00000080uL) -#define INTC_ICDISER6_INTIICSPI1 (0x00000100uL) -#define INTC_ICDISER6_INTIICSTI1 (0x00000200uL) -#define INTC_ICDISER6_INTIICNAKI1 (0x00000400uL) -#define INTC_ICDISER6_INTIICALI1 (0x00000800uL) -#define INTC_ICDISER6_INTIICTMOI1 (0x00001000uL) -#define INTC_ICDISER6_INTIICTEI2 (0x00002000uL) -#define INTC_ICDISER6_INTIICRI2 (0x00004000uL) -#define INTC_ICDISER6_INTIICTI2 (0x00008000uL) -#define INTC_ICDISER6_INTIICSPI2 (0x00010000uL) -#define INTC_ICDISER6_INTIICSTI2 (0x00020000uL) -#define INTC_ICDISER6_INTIICNAKI2 (0x00040000uL) -#define INTC_ICDISER6_INTIICALI2 (0x00080000uL) -#define INTC_ICDISER6_INTIICTMOI2 (0x00100000uL) -#define INTC_ICDISER6_INTIICTEI3 (0x00200000uL) -#define INTC_ICDISER6_INTIICRI3 (0x00400000uL) -#define INTC_ICDISER6_INTIICTI3 (0x00800000uL) -#define INTC_ICDISER6_INTIICSPI3 (0x01000000uL) -#define INTC_ICDISER6_INTIICSTI3 (0x02000000uL) -#define INTC_ICDISER6_INTIICNAKI3 (0x04000000uL) -#define INTC_ICDISER6_INTIICALI3 (0x08000000uL) -#define INTC_ICDISER6_INTIICTMOI3 (0x10000000uL) -#define INTC_ICDISER6_BRI0 (0x20000000uL) -#define INTC_ICDISER6_ERI0 (0x40000000uL) -#define INTC_ICDISER6_RXI0 (0x80000000uL) - -#define INTC_ICDISER7_TXI0 (0x00000001uL) -#define INTC_ICDISER7_BRI1 (0x00000002uL) -#define INTC_ICDISER7_ERI1 (0x00000004uL) -#define INTC_ICDISER7_RXI1 (0x00000008uL) -#define INTC_ICDISER7_TXI1 (0x00000010uL) -#define INTC_ICDISER7_BRI2 (0x00000020uL) -#define INTC_ICDISER7_ERI2 (0x00000040uL) -#define INTC_ICDISER7_RXI2 (0x00000080uL) -#define INTC_ICDISER7_TXI2 (0x00000100uL) -#define INTC_ICDISER7_BRI3 (0x00000200uL) -#define INTC_ICDISER7_ERI3 (0x00000400uL) -#define INTC_ICDISER7_RXI3 (0x00000800uL) -#define INTC_ICDISER7_TXI3 (0x00001000uL) -#define INTC_ICDISER7_BRI4 (0x00002000uL) -#define INTC_ICDISER7_ERI4 (0x00004000uL) -#define INTC_ICDISER7_RXI4 (0x00008000uL) -#define INTC_ICDISER7_TXI4 (0x00010000uL) -#define INTC_ICDISER7_BRI5 (0x00020000uL) -#define INTC_ICDISER7_ERI5 (0x00040000uL) -#define INTC_ICDISER7_RXI5 (0x00080000uL) -#define INTC_ICDISER7_TXI5 (0x00100000uL) -#define INTC_ICDISER7_BRI6 (0x00200000uL) -#define INTC_ICDISER7_ERI6 (0x00400000uL) -#define INTC_ICDISER7_RXI6 (0x00800000uL) -#define INTC_ICDISER7_TXI6 (0x01000000uL) -#define INTC_ICDISER7_BRI7 (0x02000000uL) -#define INTC_ICDISER7_ERI7 (0x04000000uL) -#define INTC_ICDISER7_RXI7 (0x08000000uL) -#define INTC_ICDISER7_TXI7 (0x10000000uL) -#define INTC_ICDISER7_INTRCANGERR (0x20000000uL) -#define INTC_ICDISER7_INTRCANGRECC (0x40000000uL) -#define INTC_ICDISER7_INTRCAN0REC (0x80000000uL) - -#define INTC_ICDISER8_INTRCAN0ERR (0x00000001uL) -#define INTC_ICDISER8_INTRCAN0TRX (0x00000002uL) -#define INTC_ICDISER8_INTRCAN1REC (0x00000004uL) -#define INTC_ICDISER8_INTRCAN1ERR (0x00000008uL) -#define INTC_ICDISER8_INTRCAN1TRX (0x00000010uL) -#define INTC_ICDISER8_INTRCAN2REC (0x00000020uL) -#define INTC_ICDISER8_INTRCAN2ERR (0x00000040uL) -#define INTC_ICDISER8_INTRCAN2TRX (0x00000080uL) -#define INTC_ICDISER8_INTRCAN3REC (0x00000100uL) -#define INTC_ICDISER8_INTRCAN3ERR (0x00000200uL) -#define INTC_ICDISER8_INTRCAN3TRX (0x00000400uL) -#define INTC_ICDISER8_INTRCAN4REC (0x00000800uL) -#define INTC_ICDISER8_INTRCAN4ERR (0x00001000uL) -#define INTC_ICDISER8_INTRCAN4TRX (0x00002000uL) -#define INTC_ICDISER8_SPEI0 (0x00004000uL) -#define INTC_ICDISER8_SPRI0 (0x00008000uL) -#define INTC_ICDISER8_SPTI0 (0x00010000uL) -#define INTC_ICDISER8_SPEI1 (0x00020000uL) -#define INTC_ICDISER8_SPRI1 (0x00040000uL) -#define INTC_ICDISER8_SPTI1 (0x00080000uL) -#define INTC_ICDISER8_SPEI2 (0x00100000uL) -#define INTC_ICDISER8_SPRI2 (0x00200000uL) -#define INTC_ICDISER8_SPTI2 (0x00400000uL) -#define INTC_ICDISER8_SPEI3 (0x00800000uL) -#define INTC_ICDISER8_SPRI3 (0x01000000uL) -#define INTC_ICDISER8_SPTI3 (0x02000000uL) -#define INTC_ICDISER8_SPEI4 (0x04000000uL) -#define INTC_ICDISER8_SPRI4 (0x08000000uL) -#define INTC_ICDISER8_SPTI4 (0x10000000uL) -#define INTC_ICDISER8_IEBBTD (0x20000000uL) -#define INTC_ICDISER8_IEBBTERR (0x40000000uL) -#define INTC_ICDISER8_IEBBTSTA (0x80000000uL) - -#define INTC_ICDISER9_IEBBTV (0x00000001uL) -#define INTC_ICDISER9_ISY (0x00000002uL) -#define INTC_ICDISER9_IERR (0x00000004uL) -#define INTC_ICDISER9_ITARG (0x00000008uL) -#define INTC_ICDISER9_ISEC (0x00000010uL) -#define INTC_ICDISER9_IBUF (0x00000020uL) -#define INTC_ICDISER9_IREADY (0x00000040uL) -#define INTC_ICDISER9_FLSTE (0x00000080uL) -#define INTC_ICDISER9_FLTENDI (0x00000100uL) -#define INTC_ICDISER9_FLTREQ0I (0x00000200uL) -#define INTC_ICDISER9_FLTREQ1I (0x00000400uL) -#define INTC_ICDISER9_MMC0 (0x00000800uL) -#define INTC_ICDISER9_MMC1 (0x00001000uL) -#define INTC_ICDISER9_MMC2 (0x00002000uL) -#define INTC_ICDISER9_SDHI0_3 (0x00004000uL) -#define INTC_ICDISER9_SDHI0_0 (0x00008000uL) -#define INTC_ICDISER9_SDHI0_1 (0x00010000uL) -#define INTC_ICDISER9_SDHI1_3 (0x00020000uL) -#define INTC_ICDISER9_SDHI1_0 (0x00040000uL) -#define INTC_ICDISER9_SDHI1_1 (0x00080000uL) -#define INTC_ICDISER9_ARM (0x00100000uL) -#define INTC_ICDISER9_PRD (0x00200000uL) -#define INTC_ICDISER9_CUP (0x00400000uL) -#define INTC_ICDISER9_SCUAI0 (0x00800000uL) -#define INTC_ICDISER9_SCUAI1 (0x01000000uL) -#define INTC_ICDISER9_SCUFDI0 (0x02000000uL) -#define INTC_ICDISER9_SCUFDI1 (0x04000000uL) -#define INTC_ICDISER9_SCUFDI2 (0x08000000uL) -#define INTC_ICDISER9_SCUFDI3 (0x10000000uL) -#define INTC_ICDISER9_SCUFUI0 (0x20000000uL) -#define INTC_ICDISER9_SCUFUI1 (0x40000000uL) -#define INTC_ICDISER9_SCUFUI2 (0x80000000uL) - -#define INTC_ICDISER10_SCUFUI3 (0x00000001uL) -#define INTC_ICDISER10_SCUDVI0 (0x00000002uL) -#define INTC_ICDISER10_SCUDVI1 (0x00000004uL) -#define INTC_ICDISER10_SCUDVI2 (0x00000008uL) -#define INTC_ICDISER10_SCUDVI3 (0x00000010uL) -#define INTC_ICDISER10_MLB_CINT (0x00000020uL) -#define INTC_ICDISER10_MLB_SINT (0x00000040uL) -#define INTC_ICDISER10_DRC0 (0x00000080uL) -#define INTC_ICDISER10_DRC1 (0x00000100uL) -#define INTC_ICDISER10_LINI0_INT_T (0x00000800uL) -#define INTC_ICDISER10_LINI0_INT_R (0x00001000uL) -#define INTC_ICDISER10_LINI0_INT_S (0x00002000uL) -#define INTC_ICDISER10_LINI0_INT_M (0x00004000uL) -#define INTC_ICDISER10_LINI1_INT_T (0x00008000uL) -#define INTC_ICDISER10_LINI1_INT_R (0x00010000uL) -#define INTC_ICDISER10_LINI1_INT_S (0x00020000uL) -#define INTC_ICDISER10_LINI1_INT_M (0x00040000uL) -#define INTC_ICDISER10_ERI0 (0x08000000uL) -#define INTC_ICDISER10_RXI0 (0x10000000uL) -#define INTC_ICDISER10_TXI0 (0x20000000uL) -#define INTC_ICDISER10_TEI0 (0x40000000uL) -#define INTC_ICDISER10_ERI1 (0x80000000uL) - -#define INTC_ICDISER11_RXI1 (0x00000001uL) -#define INTC_ICDISER11_TXI1 (0x00000002uL) -#define INTC_ICDISER11_TEI1 (0x00000004uL) -#define INTC_ICDISER11_AVBI_DATA (0x00000008uL) -#define INTC_ICDISER11_AVBI_ERROR (0x00000010uL) -#define INTC_ICDISER11_AVBI_MANAGE (0x00000020uL) -#define INTC_ICDISER11_AVBI_MAC (0x00000040uL) -#define INTC_ICDISER11_ETHERI (0x00000080uL) -#define INTC_ICDISER11_CEUI (0x00001000uL) -#define INTC_ICDISER11_H2XMLB_ERRINT (0x20000000uL) -#define INTC_ICDISER11_H2XIC1_ERRINT (0x40000000uL) -#define INTC_ICDISER11_X2HPERI1_ERRINT (0x80000000uL) - -#define INTC_ICDISER12_X2HPERI2_ERRINT (0x00000001uL) -#define INTC_ICDISER12_X2HPERI34_ERRINT (0x00000002uL) -#define INTC_ICDISER12_X2HPERI5_ERRINT (0x00000004uL) -#define INTC_ICDISER12_X2HPERI67_ERRINT (0x00000008uL) -#define INTC_ICDISER12_X2HDBGR_ERRINT (0x00000010uL) -#define INTC_ICDISER12_X2HBSC_ERRINT (0x00000020uL) -#define INTC_ICDISER12_X2HSPI1_ERRINT (0x00000040uL) -#define INTC_ICDISER12_X2HSPI2_ERRINT (0x00000080uL) -#define INTC_ICDISER12_PRRI (0x00000100uL) -#define INTC_ICDISER12_IFEI0 (0x00000200uL) -#define INTC_ICDISER12_OFFI0 (0x00000400uL) -#define INTC_ICDISER12_PFVEI0 (0x00000800uL) -#define INTC_ICDISER12_IFEI1 (0x00001000uL) -#define INTC_ICDISER12_OFFI1 (0x00002000uL) -#define INTC_ICDISER12_PFVEI1 (0x00004000uL) - -#define INTC_ICDISER13_TINT0 (0x00000001uL) -#define INTC_ICDISER13_TINT1 (0x00000002uL) -#define INTC_ICDISER13_TINT2 (0x00000004uL) -#define INTC_ICDISER13_TINT3 (0x00000008uL) -#define INTC_ICDISER13_TINT4 (0x00000010uL) -#define INTC_ICDISER13_TINT5 (0x00000020uL) -#define INTC_ICDISER13_TINT6 (0x00000040uL) -#define INTC_ICDISER13_TINT7 (0x00000080uL) -#define INTC_ICDISER13_TINT8 (0x00000100uL) -#define INTC_ICDISER13_TINT9 (0x00000200uL) -#define INTC_ICDISER13_TINT10 (0x00000400uL) -#define INTC_ICDISER13_TINT11 (0x00000800uL) -#define INTC_ICDISER13_TINT12 (0x00001000uL) -#define INTC_ICDISER13_TINT13 (0x00002000uL) -#define INTC_ICDISER13_TINT14 (0x00004000uL) -#define INTC_ICDISER13_TINT15 (0x00008000uL) -#define INTC_ICDISER13_TINT16 (0x00010000uL) -#define INTC_ICDISER13_TINT17 (0x00020000uL) -#define INTC_ICDISER13_TINT18 (0x00040000uL) -#define INTC_ICDISER13_TINT19 (0x00080000uL) -#define INTC_ICDISER13_TINT20 (0x00100000uL) -#define INTC_ICDISER13_TINT21 (0x00200000uL) -#define INTC_ICDISER13_TINT22 (0x00400000uL) -#define INTC_ICDISER13_TINT23 (0x00800000uL) -#define INTC_ICDISER13_TINT24 (0x01000000uL) -#define INTC_ICDISER13_TINT25 (0x02000000uL) -#define INTC_ICDISER13_TINT26 (0x04000000uL) -#define INTC_ICDISER13_TINT27 (0x08000000uL) -#define INTC_ICDISER13_TINT28 (0x10000000uL) -#define INTC_ICDISER13_TINT29 (0x20000000uL) -#define INTC_ICDISER13_TINT30 (0x40000000uL) -#define INTC_ICDISER13_TINT31 (0x80000000uL) - -#define INTC_ICDISER14_TINT32 (0x00000001uL) -#define INTC_ICDISER14_TINT33 (0x00000002uL) -#define INTC_ICDISER14_TINT34 (0x00000004uL) -#define INTC_ICDISER14_TINT35 (0x00000008uL) -#define INTC_ICDISER14_TINT36 (0x00000010uL) -#define INTC_ICDISER14_TINT37 (0x00000020uL) -#define INTC_ICDISER14_TINT38 (0x00000040uL) -#define INTC_ICDISER14_TINT39 (0x00000080uL) -#define INTC_ICDISER14_TINT40 (0x00000100uL) -#define INTC_ICDISER14_TINT41 (0x00000200uL) -#define INTC_ICDISER14_TINT42 (0x00000400uL) -#define INTC_ICDISER14_TINT43 (0x00000800uL) -#define INTC_ICDISER14_TINT44 (0x00001000uL) -#define INTC_ICDISER14_TINT45 (0x00002000uL) -#define INTC_ICDISER14_TINT46 (0x00004000uL) -#define INTC_ICDISER14_TINT47 (0x00008000uL) -#define INTC_ICDISER14_TINT48 (0x00010000uL) -#define INTC_ICDISER14_TINT49 (0x00020000uL) -#define INTC_ICDISER14_TINT50 (0x00040000uL) -#define INTC_ICDISER14_TINT51 (0x00080000uL) -#define INTC_ICDISER14_TINT52 (0x00100000uL) -#define INTC_ICDISER14_TINT53 (0x00200000uL) -#define INTC_ICDISER14_TINT54 (0x00400000uL) -#define INTC_ICDISER14_TINT55 (0x00800000uL) -#define INTC_ICDISER14_TINT56 (0x01000000uL) -#define INTC_ICDISER14_TINT57 (0x02000000uL) -#define INTC_ICDISER14_TINT58 (0x04000000uL) -#define INTC_ICDISER14_TINT59 (0x08000000uL) -#define INTC_ICDISER14_TINT60 (0x10000000uL) -#define INTC_ICDISER14_TINT61 (0x20000000uL) -#define INTC_ICDISER14_TINT62 (0x40000000uL) -#define INTC_ICDISER14_TINT63 (0x80000000uL) - -#define INTC_ICDISER15_TINT64 (0x00000001uL) -#define INTC_ICDISER15_TINT65 (0x00000002uL) -#define INTC_ICDISER15_TINT66 (0x00000004uL) -#define INTC_ICDISER15_TINT67 (0x00000008uL) -#define INTC_ICDISER15_TINT68 (0x00000010uL) -#define INTC_ICDISER15_TINT69 (0x00000020uL) -#define INTC_ICDISER15_TINT70 (0x00000040uL) -#define INTC_ICDISER15_TINT71 (0x00000080uL) -#define INTC_ICDISER15_TINT72 (0x00000100uL) -#define INTC_ICDISER15_TINT73 (0x00000200uL) -#define INTC_ICDISER15_TINT74 (0x00000400uL) -#define INTC_ICDISER15_TINT75 (0x00000800uL) -#define INTC_ICDISER15_TINT76 (0x00001000uL) -#define INTC_ICDISER15_TINT77 (0x00002000uL) -#define INTC_ICDISER15_TINT78 (0x00004000uL) -#define INTC_ICDISER15_TINT79 (0x00008000uL) -#define INTC_ICDISER15_TINT80 (0x00010000uL) -#define INTC_ICDISER15_TINT81 (0x00020000uL) -#define INTC_ICDISER15_TINT82 (0x00040000uL) -#define INTC_ICDISER15_TINT83 (0x00080000uL) -#define INTC_ICDISER15_TINT84 (0x00100000uL) -#define INTC_ICDISER15_TINT85 (0x00200000uL) -#define INTC_ICDISER15_TINT86 (0x00400000uL) -#define INTC_ICDISER15_TINT87 (0x00800000uL) -#define INTC_ICDISER15_TINT88 (0x01000000uL) -#define INTC_ICDISER15_TINT89 (0x02000000uL) -#define INTC_ICDISER15_TINT90 (0x04000000uL) -#define INTC_ICDISER15_TINT91 (0x08000000uL) -#define INTC_ICDISER15_TINT92 (0x10000000uL) -#define INTC_ICDISER15_TINT93 (0x20000000uL) -#define INTC_ICDISER15_TINT94 (0x40000000uL) -#define INTC_ICDISER15_TINT95 (0x80000000uL) - -#define INTC_ICDISER16_TINT96 (0x00000001uL) -#define INTC_ICDISER16_TINT97 (0x00000002uL) -#define INTC_ICDISER16_TINT98 (0x00000004uL) -#define INTC_ICDISER16_TINT99 (0x00000008uL) -#define INTC_ICDISER16_TINT100 (0x00000010uL) -#define INTC_ICDISER16_TINT101 (0x00000020uL) -#define INTC_ICDISER16_TINT102 (0x00000040uL) -#define INTC_ICDISER16_TINT103 (0x00000080uL) -#define INTC_ICDISER16_TINT104 (0x00000100uL) -#define INTC_ICDISER16_TINT105 (0x00000200uL) -#define INTC_ICDISER16_TINT106 (0x00000400uL) -#define INTC_ICDISER16_TINT107 (0x00000800uL) -#define INTC_ICDISER16_TINT108 (0x00001000uL) -#define INTC_ICDISER16_TINT109 (0x00002000uL) -#define INTC_ICDISER16_TINT110 (0x00004000uL) -#define INTC_ICDISER16_TINT111 (0x00008000uL) -#define INTC_ICDISER16_TINT112 (0x00010000uL) -#define INTC_ICDISER16_TINT113 (0x00020000uL) -#define INTC_ICDISER16_TINT114 (0x00040000uL) -#define INTC_ICDISER16_TINT115 (0x00080000uL) -#define INTC_ICDISER16_TINT116 (0x00100000uL) -#define INTC_ICDISER16_TINT117 (0x00200000uL) -#define INTC_ICDISER16_TINT118 (0x00400000uL) -#define INTC_ICDISER16_TINT119 (0x00800000uL) -#define INTC_ICDISER16_TINT120 (0x01000000uL) -#define INTC_ICDISER16_TINT121 (0x02000000uL) -#define INTC_ICDISER16_TINT122 (0x04000000uL) -#define INTC_ICDISER16_TINT123 (0x08000000uL) -#define INTC_ICDISER16_TINT124 (0x10000000uL) -#define INTC_ICDISER16_TINT125 (0x20000000uL) -#define INTC_ICDISER16_TINT126 (0x40000000uL) -#define INTC_ICDISER16_TINT127 (0x80000000uL) - -#define INTC_ICDISER17_TINT128 (0x00000001uL) -#define INTC_ICDISER17_TINT129 (0x00000002uL) -#define INTC_ICDISER17_TINT130 (0x00000004uL) -#define INTC_ICDISER17_TINT131 (0x00000008uL) -#define INTC_ICDISER17_TINT132 (0x00000010uL) -#define INTC_ICDISER17_TINT133 (0x00000020uL) -#define INTC_ICDISER17_TINT134 (0x00000040uL) -#define INTC_ICDISER17_TINT135 (0x00000080uL) -#define INTC_ICDISER17_TINT136 (0x00000100uL) -#define INTC_ICDISER17_TINT137 (0x00000200uL) -#define INTC_ICDISER17_TINT138 (0x00000400uL) -#define INTC_ICDISER17_TINT139 (0x00000800uL) -#define INTC_ICDISER17_TINT140 (0x00001000uL) -#define INTC_ICDISER17_TINT141 (0x00002000uL) -#define INTC_ICDISER17_TINT142 (0x00004000uL) -#define INTC_ICDISER17_TINT143 (0x00008000uL) -#define INTC_ICDISER17_TINT144 (0x00010000uL) -#define INTC_ICDISER17_TINT145 (0x00020000uL) -#define INTC_ICDISER17_TINT146 (0x00040000uL) -#define INTC_ICDISER17_TINT147 (0x00080000uL) -#define INTC_ICDISER17_TINT148 (0x00100000uL) -#define INTC_ICDISER17_TINT149 (0x00200000uL) -#define INTC_ICDISER17_TINT150 (0x00400000uL) -#define INTC_ICDISER17_TINT151 (0x00800000uL) -#define INTC_ICDISER17_TINT152 (0x01000000uL) -#define INTC_ICDISER17_TINT153 (0x02000000uL) -#define INTC_ICDISER17_TINT154 (0x04000000uL) -#define INTC_ICDISER17_TINT155 (0x08000000uL) -#define INTC_ICDISER17_TINT156 (0x10000000uL) -#define INTC_ICDISER17_TINT157 (0x20000000uL) -#define INTC_ICDISER17_TINT158 (0x40000000uL) -#define INTC_ICDISER17_TINT159 (0x80000000uL) - -#define INTC_ICDISER18_TINT160 (0x00000001uL) -#define INTC_ICDISER18_TINT161 (0x00000002uL) -#define INTC_ICDISER18_TINT162 (0x00000004uL) -#define INTC_ICDISER18_TINT163 (0x00000008uL) -#define INTC_ICDISER18_TINT164 (0x00000010uL) -#define INTC_ICDISER18_TINT165 (0x00000020uL) -#define INTC_ICDISER18_TINT166 (0x00000040uL) -#define INTC_ICDISER18_TINT167 (0x00000080uL) -#define INTC_ICDISER18_TINT168 (0x00000100uL) -#define INTC_ICDISER18_TINT169 (0x00000200uL) -#define INTC_ICDISER18_TINT170 (0x00000400uL) - -#define INTC_ICDICER0_SW0 (0x00000001uL) -#define INTC_ICDICER0_SW1 (0x00000002uL) -#define INTC_ICDICER0_SW2 (0x00000004uL) -#define INTC_ICDICER0_SW3 (0x00000008uL) -#define INTC_ICDICER0_SW4 (0x00000010uL) -#define INTC_ICDICER0_SW5 (0x00000020uL) -#define INTC_ICDICER0_SW6 (0x00000040uL) -#define INTC_ICDICER0_SW7 (0x00000080uL) -#define INTC_ICDICER0_SW8 (0x00000100uL) -#define INTC_ICDICER0_SW9 (0x00000200uL) -#define INTC_ICDICER0_SW10 (0x00000400uL) -#define INTC_ICDICER0_SW11 (0x00000800uL) -#define INTC_ICDICER0_SW12 (0x00001000uL) -#define INTC_ICDICER0_SW13 (0x00002000uL) -#define INTC_ICDICER0_SW14 (0x00004000uL) -#define INTC_ICDICER0_SW15 (0x00008000uL) -#define INTC_ICDICER0_PMUIRQ0 (0x00010000uL) -#define INTC_ICDICER0_COMMRX0 (0x00020000uL) -#define INTC_ICDICER0_COMMTX0 (0x00040000uL) -#define INTC_ICDICER0_CTIIRQ0 (0x00080000uL) - -#define INTC_ICDICER1_IRQ0 (0x00000001uL) -#define INTC_ICDICER1_IRQ1 (0x00000002uL) -#define INTC_ICDICER1_IRQ2 (0x00000004uL) -#define INTC_ICDICER1_IRQ3 (0x00000008uL) -#define INTC_ICDICER1_IRQ4 (0x00000010uL) -#define INTC_ICDICER1_IRQ5 (0x00000020uL) -#define INTC_ICDICER1_IRQ6 (0x00000040uL) -#define INTC_ICDICER1_IRQ7 (0x00000080uL) -#define INTC_ICDICER1_PL310ERR (0x00000100uL) -#define INTC_ICDICER1_DMAINT0 (0x00000200uL) -#define INTC_ICDICER1_DMAINT1 (0x00000400uL) -#define INTC_ICDICER1_DMAINT2 (0x00000800uL) -#define INTC_ICDICER1_DMAINT3 (0x00001000uL) -#define INTC_ICDICER1_DMAINT4 (0x00002000uL) -#define INTC_ICDICER1_DMAINT5 (0x00004000uL) -#define INTC_ICDICER1_DMAINT6 (0x00008000uL) -#define INTC_ICDICER1_DMAINT7 (0x00010000uL) -#define INTC_ICDICER1_DMAINT8 (0x00020000uL) -#define INTC_ICDICER1_DMAINT9 (0x00040000uL) -#define INTC_ICDICER1_DMAINT10 (0x00080000uL) -#define INTC_ICDICER1_DMAINT11 (0x00100000uL) -#define INTC_ICDICER1_DMAINT12 (0x00200000uL) -#define INTC_ICDICER1_DMAINT13 (0x00400000uL) -#define INTC_ICDICER1_DMAINT14 (0x00800000uL) -#define INTC_ICDICER1_DMAINT15 (0x01000000uL) -#define INTC_ICDICER1_DMAERR (0x02000000uL) - -#define INTC_ICDICER2_USBI0 (0x00000200uL) -#define INTC_ICDICER2_USBI1 (0x00000400uL) -#define INTC_ICDICER2_S0_VI_VSYNC0 (0x00000800uL) -#define INTC_ICDICER2_S0_LO_VSYNC0 (0x00001000uL) -#define INTC_ICDICER2_S0_VSYNCERR0 (0x00002000uL) -#define INTC_ICDICER2_GR3_VLINE0 (0x00004000uL) -#define INTC_ICDICER2_S0_VFIELD0 (0x00008000uL) -#define INTC_ICDICER2_IV1_VBUFERR0 (0x00010000uL) -#define INTC_ICDICER2_IV3_VBUFERR0 (0x00020000uL) -#define INTC_ICDICER2_IV5_VBUFERR0 (0x00040000uL) -#define INTC_ICDICER2_IV6_VBUFERR0 (0x00080000uL) -#define INTC_ICDICER2_S0_WLINE0 (0x00100000uL) -#define INTC_ICDICER2_S1_VI_VSYNC0 (0x00200000uL) -#define INTC_ICDICER2_S1_LO_VSYNC0 (0x00400000uL) -#define INTC_ICDICER2_S1_VSYNCERR0 (0x00800000uL) -#define INTC_ICDICER2_S1_VFIELD0 (0x01000000uL) -#define INTC_ICDICER2_IV2_VBUFERR0 (0x02000000uL) -#define INTC_ICDICER2_IV4_VBUFERR0 (0x04000000uL) -#define INTC_ICDICER2_S1_WLINE0 (0x08000000uL) -#define INTC_ICDICER2_OIR_VI_VSYNC0 (0x10000000uL) -#define INTC_ICDICER2_OIR_LO_VSYNC0 (0x20000000uL) -#define INTC_ICDICER2_OIR_VSYNCERR0 (0x40000000uL) -#define INTC_ICDICER2_OIR_VFIELD0 (0x80000000uL) - -#define INTC_ICDICER3_IV7_VBUFERR0 (0x00000001uL) -#define INTC_ICDICER3_IV8_VBUFERR0 (0x00000002uL) -#define INTC_ICDICER3_S0_VI_VSYNC1 (0x00000008uL) -#define INTC_ICDICER3_S0_LO_VSYNC1 (0x00000010uL) -#define INTC_ICDICER3_S0_VSYNCERR1 (0x00000020uL) -#define INTC_ICDICER3_GR3_VLINE1 (0x00000040uL) -#define INTC_ICDICER3_S0_VFIELD1 (0x00000080uL) -#define INTC_ICDICER3_IV1_VBUFERR1 (0x00000100uL) -#define INTC_ICDICER3_IV3_VBUFERR1 (0x00000200uL) -#define INTC_ICDICER3_IV5_VBUFERR1 (0x00000400uL) -#define INTC_ICDICER3_IV6_VBUFERR1 (0x00000800uL) -#define INTC_ICDICER3_S0_WLINE1 (0x00001000uL) -#define INTC_ICDICER3_S1_VI_VSYNC1 (0x00002000uL) -#define INTC_ICDICER3_S1_LO_VSYNC1 (0x00004000uL) -#define INTC_ICDICER3_S1_VSYNCERR1 (0x00008000uL) -#define INTC_ICDICER3_S1_VFIELD1 (0x00010000uL) -#define INTC_ICDICER3_IV2_VBUFERR1 (0x00020000uL) -#define INTC_ICDICER3_IV4_VBUFERR1 (0x00040000uL) -#define INTC_ICDICER3_S1_WLINE1 (0x00080000uL) -#define INTC_ICDICER3_OIR_VI_VSYNC1 (0x00100000uL) -#define INTC_ICDICER3_OIR_LO_VSYNC1 (0x00200000uL) -#define INTC_ICDICER3_OIR_VLINE1 (0x00400000uL) -#define INTC_ICDICER3_OIR_VFIELD1 (0x00800000uL) -#define INTC_ICDICER3_IV7_VBUFERR1 (0x01000000uL) -#define INTC_ICDICER3_IV8_VBUFERR1 (0x02000000uL) -#define INTC_ICDICER3_IMRDI (0x08000000uL) -#define INTC_ICDICER3_IMR2I0 (0x10000000uL) -#define INTC_ICDICER3_IMR2I1 (0x20000000uL) -#define INTC_ICDICER3_JEDI (0x40000000uL) -#define INTC_ICDICER3_JDTI (0x80000000uL) - -#define INTC_ICDICER4_CMP0 (0x00000001uL) -#define INTC_ICDICER4_CMP1 (0x00000002uL) -#define INTC_ICDICER4_INT0 (0x00000004uL) -#define INTC_ICDICER4_INT1 (0x00000008uL) -#define INTC_ICDICER4_INT2 (0x00000010uL) -#define INTC_ICDICER4_INT3 (0x00000020uL) -#define INTC_ICDICER4_OSTM0TINT (0x00000040uL) -#define INTC_ICDICER4_OSTM1TINT (0x00000080uL) -#define INTC_ICDICER4_CMI (0x00000100uL) -#define INTC_ICDICER4_WTOUT (0x00000200uL) -#define INTC_ICDICER4_ITI (0x00000400uL) -#define INTC_ICDICER4_TGI0A (0x00000800uL) -#define INTC_ICDICER4_TGI0B (0x00001000uL) -#define INTC_ICDICER4_TGI0C (0x00002000uL) -#define INTC_ICDICER4_TGI0D (0x00004000uL) -#define INTC_ICDICER4_TGI0V (0x00008000uL) -#define INTC_ICDICER4_TGI0E (0x00010000uL) -#define INTC_ICDICER4_TGI0F (0x00020000uL) -#define INTC_ICDICER4_TGI1A (0x00040000uL) -#define INTC_ICDICER4_TGI1B (0x00080000uL) -#define INTC_ICDICER4_TGI1V (0x00100000uL) -#define INTC_ICDICER4_TGI1U (0x00200000uL) -#define INTC_ICDICER4_TGI2A (0x00400000uL) -#define INTC_ICDICER4_TGI2B (0x00800000uL) -#define INTC_ICDICER4_TGI2V (0x01000000uL) -#define INTC_ICDICER4_TGI2U (0x02000000uL) -#define INTC_ICDICER4_TGI3A (0x04000000uL) -#define INTC_ICDICER4_TGI3B (0x08000000uL) -#define INTC_ICDICER4_TGI3C (0x10000000uL) -#define INTC_ICDICER4_TGI3D (0x20000000uL) -#define INTC_ICDICER4_TGI3V (0x40000000uL) -#define INTC_ICDICER4_TGI4A (0x80000000uL) - -#define INTC_ICDICER5_TGI4B (0x00000001uL) -#define INTC_ICDICER5_TGI4C (0x00000002uL) -#define INTC_ICDICER5_TGI4D (0x00000004uL) -#define INTC_ICDICER5_TGI4V (0x00000008uL) -#define INTC_ICDICER5_CMI1 (0x00000010uL) -#define INTC_ICDICER5_CMI2 (0x00000020uL) -#define INTC_ICDICER5_SGDEI0 (0x00000040uL) -#define INTC_ICDICER5_SGDEI1 (0x00000080uL) -#define INTC_ICDICER5_SGDEI2 (0x00000100uL) -#define INTC_ICDICER5_SGDEI3 (0x00000200uL) -#define INTC_ICDICER5_ADI (0x00000400uL) -#define INTC_ICDICER5_LMTI (0x00000800uL) -#define INTC_ICDICER5_SSII0 (0x00001000uL) -#define INTC_ICDICER5_SSIRXI0 (0x00002000uL) -#define INTC_ICDICER5_SSITXI0 (0x00004000uL) -#define INTC_ICDICER5_SSII1 (0x00008000uL) -#define INTC_ICDICER5_SSIRXI1 (0x00010000uL) -#define INTC_ICDICER5_SSITXI1 (0x00020000uL) -#define INTC_ICDICER5_SSII2 (0x00040000uL) -#define INTC_ICDICER5_SSIRTI2 (0x00080000uL) -#define INTC_ICDICER5_SSII3 (0x00100000uL) -#define INTC_ICDICER5_SSIRXI3 (0x00200000uL) -#define INTC_ICDICER5_SSITXI3 (0x00400000uL) -#define INTC_ICDICER5_SSII4 (0x00800000uL) -#define INTC_ICDICER5_SSIRTI4 (0x01000000uL) -#define INTC_ICDICER5_SSII5 (0x02000000uL) -#define INTC_ICDICER5_SSIRXI5 (0x04000000uL) -#define INTC_ICDICER5_SSITXI5 (0x08000000uL) -#define INTC_ICDICER5_SPDIFI (0x10000000uL) -#define INTC_ICDICER5_INTIICTEI0 (0x20000000uL) -#define INTC_ICDICER5_INTIICRI0 (0x40000000uL) -#define INTC_ICDICER5_INTIICTI0 (0x80000000uL) - -#define INTC_ICDICER6_INTIICSPI0 (0x00000001uL) -#define INTC_ICDICER6_INTIICSTI0 (0x00000002uL) -#define INTC_ICDICER6_INTIICNAKI0 (0x00000004uL) -#define INTC_ICDICER6_INTIICALI0 (0x00000008uL) -#define INTC_ICDICER6_INTIICTMOI0 (0x00000010uL) -#define INTC_ICDICER6_INTIICTEI1 (0x00000020uL) -#define INTC_ICDICER6_INTIICRI1 (0x00000040uL) -#define INTC_ICDICER6_INTIICTI1 (0x00000080uL) -#define INTC_ICDICER6_INTIICSPI1 (0x00000100uL) -#define INTC_ICDICER6_INTIICSTI1 (0x00000200uL) -#define INTC_ICDICER6_INTIICNAKI1 (0x00000400uL) -#define INTC_ICDICER6_INTIICALI1 (0x00000800uL) -#define INTC_ICDICER6_INTIICTMOI1 (0x00001000uL) -#define INTC_ICDICER6_INTIICTEI2 (0x00002000uL) -#define INTC_ICDICER6_INTIICRI2 (0x00004000uL) -#define INTC_ICDICER6_INTIICTI2 (0x00008000uL) -#define INTC_ICDICER6_INTIICSPI2 (0x00010000uL) -#define INTC_ICDICER6_INTIICSTI2 (0x00020000uL) -#define INTC_ICDICER6_INTIICNAKI2 (0x00040000uL) -#define INTC_ICDICER6_INTIICALI2 (0x00080000uL) -#define INTC_ICDICER6_INTIICTMOI2 (0x00100000uL) -#define INTC_ICDICER6_INTIICTEI3 (0x00200000uL) -#define INTC_ICDICER6_INTIICRI3 (0x00400000uL) -#define INTC_ICDICER6_INTIICTI3 (0x00800000uL) -#define INTC_ICDICER6_INTIICSPI3 (0x01000000uL) -#define INTC_ICDICER6_INTIICSTI3 (0x02000000uL) -#define INTC_ICDICER6_INTIICNAKI3 (0x04000000uL) -#define INTC_ICDICER6_INTIICALI3 (0x08000000uL) -#define INTC_ICDICER6_INTIICTMOI3 (0x10000000uL) -#define INTC_ICDICER6_BRI0 (0x20000000uL) -#define INTC_ICDICER6_ERI0 (0x40000000uL) -#define INTC_ICDICER6_RXI0 (0x80000000uL) - -#define INTC_ICDICER7_TXI0 (0x00000001uL) -#define INTC_ICDICER7_BRI1 (0x00000002uL) -#define INTC_ICDICER7_ERI1 (0x00000004uL) -#define INTC_ICDICER7_RXI1 (0x00000008uL) -#define INTC_ICDICER7_TXI1 (0x00000010uL) -#define INTC_ICDICER7_BRI2 (0x00000020uL) -#define INTC_ICDICER7_ERI2 (0x00000040uL) -#define INTC_ICDICER7_RXI2 (0x00000080uL) -#define INTC_ICDICER7_TXI2 (0x00000100uL) -#define INTC_ICDICER7_BRI3 (0x00000200uL) -#define INTC_ICDICER7_ERI3 (0x00000400uL) -#define INTC_ICDICER7_RXI3 (0x00000800uL) -#define INTC_ICDICER7_TXI3 (0x00001000uL) -#define INTC_ICDICER7_BRI4 (0x00002000uL) -#define INTC_ICDICER7_ERI4 (0x00004000uL) -#define INTC_ICDICER7_RXI4 (0x00008000uL) -#define INTC_ICDICER7_TXI4 (0x00010000uL) -#define INTC_ICDICER7_BRI5 (0x00020000uL) -#define INTC_ICDICER7_ERI5 (0x00040000uL) -#define INTC_ICDICER7_RXI5 (0x00080000uL) -#define INTC_ICDICER7_TXI5 (0x00100000uL) -#define INTC_ICDICER7_BRI6 (0x00200000uL) -#define INTC_ICDICER7_ERI6 (0x00400000uL) -#define INTC_ICDICER7_RXI6 (0x00800000uL) -#define INTC_ICDICER7_TXI6 (0x01000000uL) -#define INTC_ICDICER7_BRI7 (0x02000000uL) -#define INTC_ICDICER7_ERI7 (0x04000000uL) -#define INTC_ICDICER7_RXI7 (0x08000000uL) -#define INTC_ICDICER7_TXI7 (0x10000000uL) -#define INTC_ICDICER7_INTRCANGERR (0x20000000uL) -#define INTC_ICDICER7_INTRCANGRECC (0x40000000uL) -#define INTC_ICDICER7_INTRCAN0REC (0x80000000uL) - -#define INTC_ICDICER8_INTRCAN0ERR (0x00000001uL) -#define INTC_ICDICER8_INTRCAN0TRX (0x00000002uL) -#define INTC_ICDICER8_INTRCAN1REC (0x00000004uL) -#define INTC_ICDICER8_INTRCAN1ERR (0x00000008uL) -#define INTC_ICDICER8_INTRCAN1TRX (0x00000010uL) -#define INTC_ICDICER8_INTRCAN2REC (0x00000020uL) -#define INTC_ICDICER8_INTRCAN2ERR (0x00000040uL) -#define INTC_ICDICER8_INTRCAN2TRX (0x00000080uL) -#define INTC_ICDICER8_INTRCAN3REC (0x00000100uL) -#define INTC_ICDICER8_INTRCAN3ERR (0x00000200uL) -#define INTC_ICDICER8_INTRCAN3TRX (0x00000400uL) -#define INTC_ICDICER8_INTRCAN4REC (0x00000800uL) -#define INTC_ICDICER8_INTRCAN4ERR (0x00001000uL) -#define INTC_ICDICER8_INTRCAN4TRX (0x00002000uL) -#define INTC_ICDICER8_SPEI0 (0x00004000uL) -#define INTC_ICDICER8_SPRI0 (0x00008000uL) -#define INTC_ICDICER8_SPTI0 (0x00010000uL) -#define INTC_ICDICER8_SPEI1 (0x00020000uL) -#define INTC_ICDICER8_SPRI1 (0x00040000uL) -#define INTC_ICDICER8_SPTI1 (0x00080000uL) -#define INTC_ICDICER8_SPEI2 (0x00100000uL) -#define INTC_ICDICER8_SPRI2 (0x00200000uL) -#define INTC_ICDICER8_SPTI2 (0x00400000uL) -#define INTC_ICDICER8_SPEI3 (0x00800000uL) -#define INTC_ICDICER8_SPRI3 (0x01000000uL) -#define INTC_ICDICER8_SPTI3 (0x02000000uL) -#define INTC_ICDICER8_SPEI4 (0x04000000uL) -#define INTC_ICDICER8_SPRI4 (0x08000000uL) -#define INTC_ICDICER8_SPTI4 (0x10000000uL) -#define INTC_ICDICER8_IEBBTD (0x20000000uL) -#define INTC_ICDICER8_IEBBTERR (0x40000000uL) -#define INTC_ICDICER8_IEBBTSTA (0x80000000uL) - -#define INTC_ICDICER9_IEBBTV (0x00000001uL) -#define INTC_ICDICER9_ISY (0x00000002uL) -#define INTC_ICDICER9_IERR (0x00000004uL) -#define INTC_ICDICER9_ITARG (0x00000008uL) -#define INTC_ICDICER9_ISEC (0x00000010uL) -#define INTC_ICDICER9_IBUF (0x00000020uL) -#define INTC_ICDICER9_IREADY (0x00000040uL) -#define INTC_ICDICER9_FLSTE (0x00000080uL) -#define INTC_ICDICER9_FLTENDI (0x00000100uL) -#define INTC_ICDICER9_FLTREQ0I (0x00000200uL) -#define INTC_ICDICER9_FLTREQ1I (0x00000400uL) -#define INTC_ICDICER9_MMC0 (0x00000800uL) -#define INTC_ICDICER9_MMC1 (0x00001000uL) -#define INTC_ICDICER9_MMC2 (0x00002000uL) -#define INTC_ICDICER9_SDHI0_3 (0x00004000uL) -#define INTC_ICDICER9_SDHI0_0 (0x00008000uL) -#define INTC_ICDICER9_SDHI0_1 (0x00010000uL) -#define INTC_ICDICER9_SDHI1_3 (0x00020000uL) -#define INTC_ICDICER9_SDHI1_0 (0x00040000uL) -#define INTC_ICDICER9_SDHI1_1 (0x00080000uL) -#define INTC_ICDICER9_ARM (0x00100000uL) -#define INTC_ICDICER9_PRD (0x00200000uL) -#define INTC_ICDICER9_CUP (0x00400000uL) -#define INTC_ICDICER9_SCUAI0 (0x00800000uL) -#define INTC_ICDICER9_SCUAI1 (0x01000000uL) -#define INTC_ICDICER9_SCUFDI0 (0x02000000uL) -#define INTC_ICDICER9_SCUFDI1 (0x04000000uL) -#define INTC_ICDICER9_SCUFDI2 (0x08000000uL) -#define INTC_ICDICER9_SCUFDI3 (0x10000000uL) -#define INTC_ICDICER9_SCUFUI0 (0x20000000uL) -#define INTC_ICDICER9_SCUFUI1 (0x40000000uL) -#define INTC_ICDICER9_SCUFUI2 (0x80000000uL) - -#define INTC_ICDICER10_SCUFUI3 (0x00000001uL) -#define INTC_ICDICER10_SCUDVI0 (0x00000002uL) -#define INTC_ICDICER10_SCUDVI1 (0x00000004uL) -#define INTC_ICDICER10_SCUDVI2 (0x00000008uL) -#define INTC_ICDICER10_SCUDVI3 (0x00000010uL) -#define INTC_ICDICER10_MLB_CINT (0x00000020uL) -#define INTC_ICDICER10_MLB_SINT (0x00000040uL) -#define INTC_ICDICER10_DRC0 (0x00000080uL) -#define INTC_ICDICER10_DRC1 (0x00000100uL) -#define INTC_ICDICER10_LINI0_INT_T (0x00000800uL) -#define INTC_ICDICER10_LINI0_INT_R (0x00001000uL) -#define INTC_ICDICER10_LINI0_INT_S (0x00002000uL) -#define INTC_ICDICER10_LINI0_INT_M (0x00004000uL) -#define INTC_ICDICER10_LINI1_INT_T (0x00008000uL) -#define INTC_ICDICER10_LINI1_INT_R (0x00010000uL) -#define INTC_ICDICER10_LINI1_INT_S (0x00020000uL) -#define INTC_ICDICER10_LINI1_INT_M (0x00040000uL) -#define INTC_ICDICER10_ERI0 (0x08000000uL) -#define INTC_ICDICER10_RXI0 (0x10000000uL) -#define INTC_ICDICER10_TXI0 (0x20000000uL) -#define INTC_ICDICER10_TEI0 (0x40000000uL) -#define INTC_ICDICER10_ERI1 (0x80000000uL) - -#define INTC_ICDICER11_RXI1 (0x00000001uL) -#define INTC_ICDICER11_TXI1 (0x00000002uL) -#define INTC_ICDICER11_TEI1 (0x00000004uL) -#define INTC_ICDICER11_AVBI_DATA (0x00000008uL) -#define INTC_ICDICER11_AVBI_ERROR (0x00000010uL) -#define INTC_ICDICER11_AVBI_MANAGE (0x00000020uL) -#define INTC_ICDICER11_AVBI_MAC (0x00000040uL) -#define INTC_ICDICER11_ETHERI (0x00000080uL) -#define INTC_ICDICER11_CEUI (0x00001000uL) -#define INTC_ICDICER11_H2XMLB_ERRINT (0x20000000uL) -#define INTC_ICDICER11_H2XIC1_ERRINT (0x40000000uL) -#define INTC_ICDICER11_X2HPERI1_ERRINT (0x80000000uL) - -#define INTC_ICDICER12_X2HPERI2_ERRINT (0x00000001uL) -#define INTC_ICDICER12_X2HPERI34_ERRINT (0x00000002uL) -#define INTC_ICDICER12_X2HPERI5_ERRINT (0x00000004uL) -#define INTC_ICDICER12_X2HPERI67_ERRINT (0x00000008uL) -#define INTC_ICDICER12_X2HDBGR_ERRINT (0x00000010uL) -#define INTC_ICDICER12_X2HBSC_ERRINT (0x00000020uL) -#define INTC_ICDICER12_X2HSPI1_ERRINT (0x00000040uL) -#define INTC_ICDICER12_X2HSPI2_ERRINT (0x00000080uL) -#define INTC_ICDICER12_PRRI (0x00000100uL) -#define INTC_ICDICER12_IFEI0 (0x00000200uL) -#define INTC_ICDICER12_OFFI0 (0x00000400uL) -#define INTC_ICDICER12_PFVEI0 (0x00000800uL) -#define INTC_ICDICER12_IFEI1 (0x00001000uL) -#define INTC_ICDICER12_OFFI1 (0x00002000uL) -#define INTC_ICDICER12_PFVEI1 (0x00004000uL) - -#define INTC_ICDICER13_TINT0 (0x00000001uL) -#define INTC_ICDICER13_TINT1 (0x00000002uL) -#define INTC_ICDICER13_TINT2 (0x00000004uL) -#define INTC_ICDICER13_TINT3 (0x00000008uL) -#define INTC_ICDICER13_TINT4 (0x00000010uL) -#define INTC_ICDICER13_TINT5 (0x00000020uL) -#define INTC_ICDICER13_TINT6 (0x00000040uL) -#define INTC_ICDICER13_TINT7 (0x00000080uL) -#define INTC_ICDICER13_TINT8 (0x00000100uL) -#define INTC_ICDICER13_TINT9 (0x00000200uL) -#define INTC_ICDICER13_TINT10 (0x00000400uL) -#define INTC_ICDICER13_TINT11 (0x00000800uL) -#define INTC_ICDICER13_TINT12 (0x00001000uL) -#define INTC_ICDICER13_TINT13 (0x00002000uL) -#define INTC_ICDICER13_TINT14 (0x00004000uL) -#define INTC_ICDICER13_TINT15 (0x00008000uL) -#define INTC_ICDICER13_TINT16 (0x00010000uL) -#define INTC_ICDICER13_TINT17 (0x00020000uL) -#define INTC_ICDICER13_TINT18 (0x00040000uL) -#define INTC_ICDICER13_TINT19 (0x00080000uL) -#define INTC_ICDICER13_TINT20 (0x00100000uL) -#define INTC_ICDICER13_TINT21 (0x00200000uL) -#define INTC_ICDICER13_TINT22 (0x00400000uL) -#define INTC_ICDICER13_TINT23 (0x00800000uL) -#define INTC_ICDICER13_TINT24 (0x01000000uL) -#define INTC_ICDICER13_TINT25 (0x02000000uL) -#define INTC_ICDICER13_TINT26 (0x04000000uL) -#define INTC_ICDICER13_TINT27 (0x08000000uL) -#define INTC_ICDICER13_TINT28 (0x10000000uL) -#define INTC_ICDICER13_TINT29 (0x20000000uL) -#define INTC_ICDICER13_TINT30 (0x40000000uL) -#define INTC_ICDICER13_TINT31 (0x80000000uL) - -#define INTC_ICDICER14_TINT32 (0x00000001uL) -#define INTC_ICDICER14_TINT33 (0x00000002uL) -#define INTC_ICDICER14_TINT34 (0x00000004uL) -#define INTC_ICDICER14_TINT35 (0x00000008uL) -#define INTC_ICDICER14_TINT36 (0x00000010uL) -#define INTC_ICDICER14_TINT37 (0x00000020uL) -#define INTC_ICDICER14_TINT38 (0x00000040uL) -#define INTC_ICDICER14_TINT39 (0x00000080uL) -#define INTC_ICDICER14_TINT40 (0x00000100uL) -#define INTC_ICDICER14_TINT41 (0x00000200uL) -#define INTC_ICDICER14_TINT42 (0x00000400uL) -#define INTC_ICDICER14_TINT43 (0x00000800uL) -#define INTC_ICDICER14_TINT44 (0x00001000uL) -#define INTC_ICDICER14_TINT45 (0x00002000uL) -#define INTC_ICDICER14_TINT46 (0x00004000uL) -#define INTC_ICDICER14_TINT47 (0x00008000uL) -#define INTC_ICDICER14_TINT48 (0x00010000uL) -#define INTC_ICDICER14_TINT49 (0x00020000uL) -#define INTC_ICDICER14_TINT50 (0x00040000uL) -#define INTC_ICDICER14_TINT51 (0x00080000uL) -#define INTC_ICDICER14_TINT52 (0x00100000uL) -#define INTC_ICDICER14_TINT53 (0x00200000uL) -#define INTC_ICDICER14_TINT54 (0x00400000uL) -#define INTC_ICDICER14_TINT55 (0x00800000uL) -#define INTC_ICDICER14_TINT56 (0x01000000uL) -#define INTC_ICDICER14_TINT57 (0x02000000uL) -#define INTC_ICDICER14_TINT58 (0x04000000uL) -#define INTC_ICDICER14_TINT59 (0x08000000uL) -#define INTC_ICDICER14_TINT60 (0x10000000uL) -#define INTC_ICDICER14_TINT61 (0x20000000uL) -#define INTC_ICDICER14_TINT62 (0x40000000uL) -#define INTC_ICDICER14_TINT63 (0x80000000uL) - -#define INTC_ICDICER15_TINT64 (0x00000001uL) -#define INTC_ICDICER15_TINT65 (0x00000002uL) -#define INTC_ICDICER15_TINT66 (0x00000004uL) -#define INTC_ICDICER15_TINT67 (0x00000008uL) -#define INTC_ICDICER15_TINT68 (0x00000010uL) -#define INTC_ICDICER15_TINT69 (0x00000020uL) -#define INTC_ICDICER15_TINT70 (0x00000040uL) -#define INTC_ICDICER15_TINT71 (0x00000080uL) -#define INTC_ICDICER15_TINT72 (0x00000100uL) -#define INTC_ICDICER15_TINT73 (0x00000200uL) -#define INTC_ICDICER15_TINT74 (0x00000400uL) -#define INTC_ICDICER15_TINT75 (0x00000800uL) -#define INTC_ICDICER15_TINT76 (0x00001000uL) -#define INTC_ICDICER15_TINT77 (0x00002000uL) -#define INTC_ICDICER15_TINT78 (0x00004000uL) -#define INTC_ICDICER15_TINT79 (0x00008000uL) -#define INTC_ICDICER15_TINT80 (0x00010000uL) -#define INTC_ICDICER15_TINT81 (0x00020000uL) -#define INTC_ICDICER15_TINT82 (0x00040000uL) -#define INTC_ICDICER15_TINT83 (0x00080000uL) -#define INTC_ICDICER15_TINT84 (0x00100000uL) -#define INTC_ICDICER15_TINT85 (0x00200000uL) -#define INTC_ICDICER15_TINT86 (0x00400000uL) -#define INTC_ICDICER15_TINT87 (0x00800000uL) -#define INTC_ICDICER15_TINT88 (0x01000000uL) -#define INTC_ICDICER15_TINT89 (0x02000000uL) -#define INTC_ICDICER15_TINT90 (0x04000000uL) -#define INTC_ICDICER15_TINT91 (0x08000000uL) -#define INTC_ICDICER15_TINT92 (0x10000000uL) -#define INTC_ICDICER15_TINT93 (0x20000000uL) -#define INTC_ICDICER15_TINT94 (0x40000000uL) -#define INTC_ICDICER15_TINT95 (0x80000000uL) - -#define INTC_ICDICER16_TINT96 (0x00000001uL) -#define INTC_ICDICER16_TINT97 (0x00000002uL) -#define INTC_ICDICER16_TINT98 (0x00000004uL) -#define INTC_ICDICER16_TINT99 (0x00000008uL) -#define INTC_ICDICER16_TINT100 (0x00000010uL) -#define INTC_ICDICER16_TINT101 (0x00000020uL) -#define INTC_ICDICER16_TINT102 (0x00000040uL) -#define INTC_ICDICER16_TINT103 (0x00000080uL) -#define INTC_ICDICER16_TINT104 (0x00000100uL) -#define INTC_ICDICER16_TINT105 (0x00000200uL) -#define INTC_ICDICER16_TINT106 (0x00000400uL) -#define INTC_ICDICER16_TINT107 (0x00000800uL) -#define INTC_ICDICER16_TINT108 (0x00001000uL) -#define INTC_ICDICER16_TINT109 (0x00002000uL) -#define INTC_ICDICER16_TINT110 (0x00004000uL) -#define INTC_ICDICER16_TINT111 (0x00008000uL) -#define INTC_ICDICER16_TINT112 (0x00010000uL) -#define INTC_ICDICER16_TINT113 (0x00020000uL) -#define INTC_ICDICER16_TINT114 (0x00040000uL) -#define INTC_ICDICER16_TINT115 (0x00080000uL) -#define INTC_ICDICER16_TINT116 (0x00100000uL) -#define INTC_ICDICER16_TINT117 (0x00200000uL) -#define INTC_ICDICER16_TINT118 (0x00400000uL) -#define INTC_ICDICER16_TINT119 (0x00800000uL) -#define INTC_ICDICER16_TINT120 (0x01000000uL) -#define INTC_ICDICER16_TINT121 (0x02000000uL) -#define INTC_ICDICER16_TINT122 (0x04000000uL) -#define INTC_ICDICER16_TINT123 (0x08000000uL) -#define INTC_ICDICER16_TINT124 (0x10000000uL) -#define INTC_ICDICER16_TINT125 (0x20000000uL) -#define INTC_ICDICER16_TINT126 (0x40000000uL) -#define INTC_ICDICER16_TINT127 (0x80000000uL) - -#define INTC_ICDICER17_TINT128 (0x00000001uL) -#define INTC_ICDICER17_TINT129 (0x00000002uL) -#define INTC_ICDICER17_TINT130 (0x00000004uL) -#define INTC_ICDICER17_TINT131 (0x00000008uL) -#define INTC_ICDICER17_TINT132 (0x00000010uL) -#define INTC_ICDICER17_TINT133 (0x00000020uL) -#define INTC_ICDICER17_TINT134 (0x00000040uL) -#define INTC_ICDICER17_TINT135 (0x00000080uL) -#define INTC_ICDICER17_TINT136 (0x00000100uL) -#define INTC_ICDICER17_TINT137 (0x00000200uL) -#define INTC_ICDICER17_TINT138 (0x00000400uL) -#define INTC_ICDICER17_TINT139 (0x00000800uL) -#define INTC_ICDICER17_TINT140 (0x00001000uL) -#define INTC_ICDICER17_TINT141 (0x00002000uL) -#define INTC_ICDICER17_TINT142 (0x00004000uL) -#define INTC_ICDICER17_TINT143 (0x00008000uL) -#define INTC_ICDICER17_TINT144 (0x00010000uL) -#define INTC_ICDICER17_TINT145 (0x00020000uL) -#define INTC_ICDICER17_TINT146 (0x00040000uL) -#define INTC_ICDICER17_TINT147 (0x00080000uL) -#define INTC_ICDICER17_TINT148 (0x00100000uL) -#define INTC_ICDICER17_TINT149 (0x00200000uL) -#define INTC_ICDICER17_TINT150 (0x00400000uL) -#define INTC_ICDICER17_TINT151 (0x00800000uL) -#define INTC_ICDICER17_TINT152 (0x01000000uL) -#define INTC_ICDICER17_TINT153 (0x02000000uL) -#define INTC_ICDICER17_TINT154 (0x04000000uL) -#define INTC_ICDICER17_TINT155 (0x08000000uL) -#define INTC_ICDICER17_TINT156 (0x10000000uL) -#define INTC_ICDICER17_TINT157 (0x20000000uL) -#define INTC_ICDICER17_TINT158 (0x40000000uL) -#define INTC_ICDICER17_TINT159 (0x80000000uL) - -#define INTC_ICDICER18_TINT160 (0x00000001uL) -#define INTC_ICDICER18_TINT161 (0x00000002uL) -#define INTC_ICDICER18_TINT162 (0x00000004uL) -#define INTC_ICDICER18_TINT163 (0x00000008uL) -#define INTC_ICDICER18_TINT164 (0x00000010uL) -#define INTC_ICDICER18_TINT165 (0x00000020uL) -#define INTC_ICDICER18_TINT166 (0x00000040uL) -#define INTC_ICDICER18_TINT167 (0x00000080uL) -#define INTC_ICDICER18_TINT168 (0x00000100uL) -#define INTC_ICDICER18_TINT169 (0x00000200uL) -#define INTC_ICDICER18_TINT170 (0x00000400uL) - -#define INTC_ICDISPR0_SW0 (0x00000001uL) -#define INTC_ICDISPR0_SW1 (0x00000002uL) -#define INTC_ICDISPR0_SW2 (0x00000004uL) -#define INTC_ICDISPR0_SW3 (0x00000008uL) -#define INTC_ICDISPR0_SW4 (0x00000010uL) -#define INTC_ICDISPR0_SW5 (0x00000020uL) -#define INTC_ICDISPR0_SW6 (0x00000040uL) -#define INTC_ICDISPR0_SW7 (0x00000080uL) -#define INTC_ICDISPR0_SW8 (0x00000100uL) -#define INTC_ICDISPR0_SW9 (0x00000200uL) -#define INTC_ICDISPR0_SW10 (0x00000400uL) -#define INTC_ICDISPR0_SW11 (0x00000800uL) -#define INTC_ICDISPR0_SW12 (0x00001000uL) -#define INTC_ICDISPR0_SW13 (0x00002000uL) -#define INTC_ICDISPR0_SW14 (0x00004000uL) -#define INTC_ICDISPR0_SW15 (0x00008000uL) -#define INTC_ICDISPR0_PMUIRQ0 (0x00010000uL) -#define INTC_ICDISPR0_COMMRX0 (0x00020000uL) -#define INTC_ICDISPR0_COMMTX0 (0x00040000uL) -#define INTC_ICDISPR0_CTIIRQ0 (0x00080000uL) - -#define INTC_ICDISPR1_IRQ0 (0x00000001uL) -#define INTC_ICDISPR1_IRQ1 (0x00000002uL) -#define INTC_ICDISPR1_IRQ2 (0x00000004uL) -#define INTC_ICDISPR1_IRQ3 (0x00000008uL) -#define INTC_ICDISPR1_IRQ4 (0x00000010uL) -#define INTC_ICDISPR1_IRQ5 (0x00000020uL) -#define INTC_ICDISPR1_IRQ6 (0x00000040uL) -#define INTC_ICDISPR1_IRQ7 (0x00000080uL) -#define INTC_ICDISPR1_PL310ERR (0x00000100uL) -#define INTC_ICDISPR1_DMAINT0 (0x00000200uL) -#define INTC_ICDISPR1_DMAINT1 (0x00000400uL) -#define INTC_ICDISPR1_DMAINT2 (0x00000800uL) -#define INTC_ICDISPR1_DMAINT3 (0x00001000uL) -#define INTC_ICDISPR1_DMAINT4 (0x00002000uL) -#define INTC_ICDISPR1_DMAINT5 (0x00004000uL) -#define INTC_ICDISPR1_DMAINT6 (0x00008000uL) -#define INTC_ICDISPR1_DMAINT7 (0x00010000uL) -#define INTC_ICDISPR1_DMAINT8 (0x00020000uL) -#define INTC_ICDISPR1_DMAINT9 (0x00040000uL) -#define INTC_ICDISPR1_DMAINT10 (0x00080000uL) -#define INTC_ICDISPR1_DMAINT11 (0x00100000uL) -#define INTC_ICDISPR1_DMAINT12 (0x00200000uL) -#define INTC_ICDISPR1_DMAINT13 (0x00400000uL) -#define INTC_ICDISPR1_DMAINT14 (0x00800000uL) -#define INTC_ICDISPR1_DMAINT15 (0x01000000uL) -#define INTC_ICDISPR1_DMAERR (0x02000000uL) - -#define INTC_ICDISPR2_USBI0 (0x00000200uL) -#define INTC_ICDISPR2_USBI1 (0x00000400uL) -#define INTC_ICDISPR2_S0_VI_VSYNC0 (0x00000800uL) -#define INTC_ICDISPR2_S0_LO_VSYNC0 (0x00001000uL) -#define INTC_ICDISPR2_S0_VSYNCERR0 (0x00002000uL) -#define INTC_ICDISPR2_GR3_VLINE0 (0x00004000uL) -#define INTC_ICDISPR2_S0_VFIELD0 (0x00008000uL) -#define INTC_ICDISPR2_IV1_VBUFERR0 (0x00010000uL) -#define INTC_ICDISPR2_IV3_VBUFERR0 (0x00020000uL) -#define INTC_ICDISPR2_IV5_VBUFERR0 (0x00040000uL) -#define INTC_ICDISPR2_IV6_VBUFERR0 (0x00080000uL) -#define INTC_ICDISPR2_S0_WLINE0 (0x00100000uL) -#define INTC_ICDISPR2_S1_VI_VSYNC0 (0x00200000uL) -#define INTC_ICDISPR2_S1_LO_VSYNC0 (0x00400000uL) -#define INTC_ICDISPR2_S1_VSYNCERR0 (0x00800000uL) -#define INTC_ICDISPR2_S1_VFIELD0 (0x01000000uL) -#define INTC_ICDISPR2_IV2_VBUFERR0 (0x02000000uL) -#define INTC_ICDISPR2_IV4_VBUFERR0 (0x04000000uL) -#define INTC_ICDISPR2_S1_WLINE0 (0x08000000uL) -#define INTC_ICDISPR2_OIR_VI_VSYNC0 (0x10000000uL) -#define INTC_ICDISPR2_OIR_LO_VSYNC0 (0x20000000uL) -#define INTC_ICDISPR2_OIR_VSYNCERR0 (0x40000000uL) -#define INTC_ICDISPR2_OIR_VFIELD0 (0x80000000uL) - -#define INTC_ICDISPR3_IV7_VBUFERR0 (0x00000001uL) -#define INTC_ICDISPR3_IV8_VBUFERR0 (0x00000002uL) -#define INTC_ICDISPR3_S0_VI_VSYNC1 (0x00000008uL) -#define INTC_ICDISPR3_S0_LO_VSYNC1 (0x00000010uL) -#define INTC_ICDISPR3_S0_VSYNCERR1 (0x00000020uL) -#define INTC_ICDISPR3_GR3_VLINE1 (0x00000040uL) -#define INTC_ICDISPR3_S0_VFIELD1 (0x00000080uL) -#define INTC_ICDISPR3_IV1_VBUFERR1 (0x00000100uL) -#define INTC_ICDISPR3_IV3_VBUFERR1 (0x00000200uL) -#define INTC_ICDISPR3_IV5_VBUFERR1 (0x00000400uL) -#define INTC_ICDISPR3_IV6_VBUFERR1 (0x00000800uL) -#define INTC_ICDISPR3_S0_WLINE1 (0x00001000uL) -#define INTC_ICDISPR3_S1_VI_VSYNC1 (0x00002000uL) -#define INTC_ICDISPR3_S1_LO_VSYNC1 (0x00004000uL) -#define INTC_ICDISPR3_S1_VSYNCERR1 (0x00008000uL) -#define INTC_ICDISPR3_S1_VFIELD1 (0x00010000uL) -#define INTC_ICDISPR3_IV2_VBUFERR1 (0x00020000uL) -#define INTC_ICDISPR3_IV4_VBUFERR1 (0x00040000uL) -#define INTC_ICDISPR3_S1_WLINE1 (0x00080000uL) -#define INTC_ICDISPR3_OIR_VI_VSYNC1 (0x00100000uL) -#define INTC_ICDISPR3_OIR_LO_VSYNC1 (0x00200000uL) -#define INTC_ICDISPR3_OIR_VLINE1 (0x00400000uL) -#define INTC_ICDISPR3_OIR_VFIELD1 (0x00800000uL) -#define INTC_ICDISPR3_IV7_VBUFERR1 (0x01000000uL) -#define INTC_ICDISPR3_IV8_VBUFERR1 (0x02000000uL) -#define INTC_ICDISPR3_IMRDI (0x08000000uL) -#define INTC_ICDISPR3_IMR2I0 (0x10000000uL) -#define INTC_ICDISPR3_IMR2I1 (0x20000000uL) -#define INTC_ICDISPR3_JEDI (0x40000000uL) -#define INTC_ICDISPR3_JDTI (0x80000000uL) - -#define INTC_ICDISPR4_CMP0 (0x00000001uL) -#define INTC_ICDISPR4_CMP1 (0x00000002uL) -#define INTC_ICDISPR4_INT0 (0x00000004uL) -#define INTC_ICDISPR4_INT1 (0x00000008uL) -#define INTC_ICDISPR4_INT2 (0x00000010uL) -#define INTC_ICDISPR4_INT3 (0x00000020uL) -#define INTC_ICDISPR4_OSTM0TINT (0x00000040uL) -#define INTC_ICDISPR4_OSTM1TINT (0x00000080uL) -#define INTC_ICDISPR4_CMI (0x00000100uL) -#define INTC_ICDISPR4_WTOUT (0x00000200uL) -#define INTC_ICDISPR4_ITI (0x00000400uL) -#define INTC_ICDISPR4_TGI0A (0x00000800uL) -#define INTC_ICDISPR4_TGI0B (0x00001000uL) -#define INTC_ICDISPR4_TGI0C (0x00002000uL) -#define INTC_ICDISPR4_TGI0D (0x00004000uL) -#define INTC_ICDISPR4_TGI0V (0x00008000uL) -#define INTC_ICDISPR4_TGI0E (0x00010000uL) -#define INTC_ICDISPR4_TGI0F (0x00020000uL) -#define INTC_ICDISPR4_TGI1A (0x00040000uL) -#define INTC_ICDISPR4_TGI1B (0x00080000uL) -#define INTC_ICDISPR4_TGI1V (0x00100000uL) -#define INTC_ICDISPR4_TGI1U (0x00200000uL) -#define INTC_ICDISPR4_TGI2A (0x00400000uL) -#define INTC_ICDISPR4_TGI2B (0x00800000uL) -#define INTC_ICDISPR4_TGI2V (0x01000000uL) -#define INTC_ICDISPR4_TGI2U (0x02000000uL) -#define INTC_ICDISPR4_TGI3A (0x04000000uL) -#define INTC_ICDISPR4_TGI3B (0x08000000uL) -#define INTC_ICDISPR4_TGI3C (0x10000000uL) -#define INTC_ICDISPR4_TGI3D (0x20000000uL) -#define INTC_ICDISPR4_TGI3V (0x40000000uL) -#define INTC_ICDISPR4_TGI4A (0x80000000uL) - -#define INTC_ICDISPR5_TGI4B (0x00000001uL) -#define INTC_ICDISPR5_TGI4C (0x00000002uL) -#define INTC_ICDISPR5_TGI4D (0x00000004uL) -#define INTC_ICDISPR5_TGI4V (0x00000008uL) -#define INTC_ICDISPR5_CMI1 (0x00000010uL) -#define INTC_ICDISPR5_CMI2 (0x00000020uL) -#define INTC_ICDISPR5_SGDEI0 (0x00000040uL) -#define INTC_ICDISPR5_SGDEI1 (0x00000080uL) -#define INTC_ICDISPR5_SGDEI2 (0x00000100uL) -#define INTC_ICDISPR5_SGDEI3 (0x00000200uL) -#define INTC_ICDISPR5_ADI (0x00000400uL) -#define INTC_ICDISPR5_LMTI (0x00000800uL) -#define INTC_ICDISPR5_SSII0 (0x00001000uL) -#define INTC_ICDISPR5_SSIRXI0 (0x00002000uL) -#define INTC_ICDISPR5_SSITXI0 (0x00004000uL) -#define INTC_ICDISPR5_SSII1 (0x00008000uL) -#define INTC_ICDISPR5_SSIRXI1 (0x00010000uL) -#define INTC_ICDISPR5_SSITXI1 (0x00020000uL) -#define INTC_ICDISPR5_SSII2 (0x00040000uL) -#define INTC_ICDISPR5_SSIRTI2 (0x00080000uL) -#define INTC_ICDISPR5_SSII3 (0x00100000uL) -#define INTC_ICDISPR5_SSIRXI3 (0x00200000uL) -#define INTC_ICDISPR5_SSITXI3 (0x00400000uL) -#define INTC_ICDISPR5_SSII4 (0x00800000uL) -#define INTC_ICDISPR5_SSIRTI4 (0x01000000uL) -#define INTC_ICDISPR5_SSII5 (0x02000000uL) -#define INTC_ICDISPR5_SSIRXI5 (0x04000000uL) -#define INTC_ICDISPR5_SSITXI5 (0x08000000uL) -#define INTC_ICDISPR5_SPDIFI (0x10000000uL) -#define INTC_ICDISPR5_INTIICTEI0 (0x20000000uL) -#define INTC_ICDISPR5_INTIICRI0 (0x40000000uL) -#define INTC_ICDISPR5_INTIICTI0 (0x80000000uL) - -#define INTC_ICDISPR6_INTIICSPI0 (0x00000001uL) -#define INTC_ICDISPR6_INTIICSTI0 (0x00000002uL) -#define INTC_ICDISPR6_INTIICNAKI0 (0x00000004uL) -#define INTC_ICDISPR6_INTIICALI0 (0x00000008uL) -#define INTC_ICDISPR6_INTIICTMOI0 (0x00000010uL) -#define INTC_ICDISPR6_INTIICTEI1 (0x00000020uL) -#define INTC_ICDISPR6_INTIICRI1 (0x00000040uL) -#define INTC_ICDISPR6_INTIICTI1 (0x00000080uL) -#define INTC_ICDISPR6_INTIICSPI1 (0x00000100uL) -#define INTC_ICDISPR6_INTIICSTI1 (0x00000200uL) -#define INTC_ICDISPR6_INTIICNAKI1 (0x00000400uL) -#define INTC_ICDISPR6_INTIICALI1 (0x00000800uL) -#define INTC_ICDISPR6_INTIICTMOI1 (0x00001000uL) -#define INTC_ICDISPR6_INTIICTEI2 (0x00002000uL) -#define INTC_ICDISPR6_INTIICRI2 (0x00004000uL) -#define INTC_ICDISPR6_INTIICTI2 (0x00008000uL) -#define INTC_ICDISPR6_INTIICSPI2 (0x00010000uL) -#define INTC_ICDISPR6_INTIICSTI2 (0x00020000uL) -#define INTC_ICDISPR6_INTIICNAKI2 (0x00040000uL) -#define INTC_ICDISPR6_INTIICALI2 (0x00080000uL) -#define INTC_ICDISPR6_INTIICTMOI2 (0x00100000uL) -#define INTC_ICDISPR6_INTIICTEI3 (0x00200000uL) -#define INTC_ICDISPR6_INTIICRI3 (0x00400000uL) -#define INTC_ICDISPR6_INTIICTI3 (0x00800000uL) -#define INTC_ICDISPR6_INTIICSPI3 (0x01000000uL) -#define INTC_ICDISPR6_INTIICSTI3 (0x02000000uL) -#define INTC_ICDISPR6_INTIICNAKI3 (0x04000000uL) -#define INTC_ICDISPR6_INTIICALI3 (0x08000000uL) -#define INTC_ICDISPR6_INTIICTMOI3 (0x10000000uL) -#define INTC_ICDISPR6_BRI0 (0x20000000uL) -#define INTC_ICDISPR6_ERI0 (0x40000000uL) -#define INTC_ICDISPR6_RXI0 (0x80000000uL) - -#define INTC_ICDISPR7_TXI0 (0x00000001uL) -#define INTC_ICDISPR7_BRI1 (0x00000002uL) -#define INTC_ICDISPR7_ERI1 (0x00000004uL) -#define INTC_ICDISPR7_RXI1 (0x00000008uL) -#define INTC_ICDISPR7_TXI1 (0x00000010uL) -#define INTC_ICDISPR7_BRI2 (0x00000020uL) -#define INTC_ICDISPR7_ERI2 (0x00000040uL) -#define INTC_ICDISPR7_RXI2 (0x00000080uL) -#define INTC_ICDISPR7_TXI2 (0x00000100uL) -#define INTC_ICDISPR7_BRI3 (0x00000200uL) -#define INTC_ICDISPR7_ERI3 (0x00000400uL) -#define INTC_ICDISPR7_RXI3 (0x00000800uL) -#define INTC_ICDISPR7_TXI3 (0x00001000uL) -#define INTC_ICDISPR7_BRI4 (0x00002000uL) -#define INTC_ICDISPR7_ERI4 (0x00004000uL) -#define INTC_ICDISPR7_RXI4 (0x00008000uL) -#define INTC_ICDISPR7_TXI4 (0x00010000uL) -#define INTC_ICDISPR7_BRI5 (0x00020000uL) -#define INTC_ICDISPR7_ERI5 (0x00040000uL) -#define INTC_ICDISPR7_RXI5 (0x00080000uL) -#define INTC_ICDISPR7_TXI5 (0x00100000uL) -#define INTC_ICDISPR7_BRI6 (0x00200000uL) -#define INTC_ICDISPR7_ERI6 (0x00400000uL) -#define INTC_ICDISPR7_RXI6 (0x00800000uL) -#define INTC_ICDISPR7_TXI6 (0x01000000uL) -#define INTC_ICDISPR7_BRI7 (0x02000000uL) -#define INTC_ICDISPR7_ERI7 (0x04000000uL) -#define INTC_ICDISPR7_RXI7 (0x08000000uL) -#define INTC_ICDISPR7_TXI7 (0x10000000uL) -#define INTC_ICDISPR7_INTRCANGERR (0x20000000uL) -#define INTC_ICDISPR7_INTRCANGRECC (0x40000000uL) -#define INTC_ICDISPR7_INTRCAN0REC (0x80000000uL) - -#define INTC_ICDISPR8_INTRCAN0ERR (0x00000001uL) -#define INTC_ICDISPR8_INTRCAN0TRX (0x00000002uL) -#define INTC_ICDISPR8_INTRCAN1REC (0x00000004uL) -#define INTC_ICDISPR8_INTRCAN1ERR (0x00000008uL) -#define INTC_ICDISPR8_INTRCAN1TRX (0x00000010uL) -#define INTC_ICDISPR8_INTRCAN2REC (0x00000020uL) -#define INTC_ICDISPR8_INTRCAN2ERR (0x00000040uL) -#define INTC_ICDISPR8_INTRCAN2TRX (0x00000080uL) -#define INTC_ICDISPR8_INTRCAN3REC (0x00000100uL) -#define INTC_ICDISPR8_INTRCAN3ERR (0x00000200uL) -#define INTC_ICDISPR8_INTRCAN3TRX (0x00000400uL) -#define INTC_ICDISPR8_INTRCAN4REC (0x00000800uL) -#define INTC_ICDISPR8_INTRCAN4ERR (0x00001000uL) -#define INTC_ICDISPR8_INTRCAN4TRX (0x00002000uL) -#define INTC_ICDISPR8_SPEI0 (0x00004000uL) -#define INTC_ICDISPR8_SPRI0 (0x00008000uL) -#define INTC_ICDISPR8_SPTI0 (0x00010000uL) -#define INTC_ICDISPR8_SPEI1 (0x00020000uL) -#define INTC_ICDISPR8_SPRI1 (0x00040000uL) -#define INTC_ICDISPR8_SPTI1 (0x00080000uL) -#define INTC_ICDISPR8_SPEI2 (0x00100000uL) -#define INTC_ICDISPR8_SPRI2 (0x00200000uL) -#define INTC_ICDISPR8_SPTI2 (0x00400000uL) -#define INTC_ICDISPR8_SPEI3 (0x00800000uL) -#define INTC_ICDISPR8_SPRI3 (0x01000000uL) -#define INTC_ICDISPR8_SPTI3 (0x02000000uL) -#define INTC_ICDISPR8_SPEI4 (0x04000000uL) -#define INTC_ICDISPR8_SPRI4 (0x08000000uL) -#define INTC_ICDISPR8_SPTI4 (0x10000000uL) -#define INTC_ICDISPR8_IEBBTD (0x20000000uL) -#define INTC_ICDISPR8_IEBBTERR (0x40000000uL) -#define INTC_ICDISPR8_IEBBTSTA (0x80000000uL) - -#define INTC_ICDISPR9_IEBBTV (0x00000001uL) -#define INTC_ICDISPR9_ISY (0x00000002uL) -#define INTC_ICDISPR9_IERR (0x00000004uL) -#define INTC_ICDISPR9_ITARG (0x00000008uL) -#define INTC_ICDISPR9_ISEC (0x00000010uL) -#define INTC_ICDISPR9_IBUF (0x00000020uL) -#define INTC_ICDISPR9_IREADY (0x00000040uL) -#define INTC_ICDISPR9_FLSTE (0x00000080uL) -#define INTC_ICDISPR9_FLTENDI (0x00000100uL) -#define INTC_ICDISPR9_FLTREQ0I (0x00000200uL) -#define INTC_ICDISPR9_FLTREQ1I (0x00000400uL) -#define INTC_ICDISPR9_MMC0 (0x00000800uL) -#define INTC_ICDISPR9_MMC1 (0x00001000uL) -#define INTC_ICDISPR9_MMC2 (0x00002000uL) -#define INTC_ICDISPR9_SDHI0_3 (0x00004000uL) -#define INTC_ICDISPR9_SDHI0_0 (0x00008000uL) -#define INTC_ICDISPR9_SDHI0_1 (0x00010000uL) -#define INTC_ICDISPR9_SDHI1_3 (0x00020000uL) -#define INTC_ICDISPR9_SDHI1_0 (0x00040000uL) -#define INTC_ICDISPR9_SDHI1_1 (0x00080000uL) -#define INTC_ICDISPR9_ARM (0x00100000uL) -#define INTC_ICDISPR9_PRD (0x00200000uL) -#define INTC_ICDISPR9_CUP (0x00400000uL) -#define INTC_ICDISPR9_SCUAI0 (0x00800000uL) -#define INTC_ICDISPR9_SCUAI1 (0x01000000uL) -#define INTC_ICDISPR9_SCUFDI0 (0x02000000uL) -#define INTC_ICDISPR9_SCUFDI1 (0x04000000uL) -#define INTC_ICDISPR9_SCUFDI2 (0x08000000uL) -#define INTC_ICDISPR9_SCUFDI3 (0x10000000uL) -#define INTC_ICDISPR9_SCUFUI0 (0x20000000uL) -#define INTC_ICDISPR9_SCUFUI1 (0x40000000uL) -#define INTC_ICDISPR9_SCUFUI2 (0x80000000uL) - -#define INTC_ICDISPR10_SCUFUI3 (0x00000001uL) -#define INTC_ICDISPR10_SCUDVI0 (0x00000002uL) -#define INTC_ICDISPR10_SCUDVI1 (0x00000004uL) -#define INTC_ICDISPR10_SCUDVI2 (0x00000008uL) -#define INTC_ICDISPR10_SCUDVI3 (0x00000010uL) -#define INTC_ICDISPR10_MLB_CINT (0x00000020uL) -#define INTC_ICDISPR10_MLB_SINT (0x00000040uL) -#define INTC_ICDISPR10_DRC0 (0x00000080uL) -#define INTC_ICDISPR10_DRC1 (0x00000100uL) -#define INTC_ICDISPR10_LINI0_INT_T (0x00000800uL) -#define INTC_ICDISPR10_LINI0_INT_R (0x00001000uL) -#define INTC_ICDISPR10_LINI0_INT_S (0x00002000uL) -#define INTC_ICDISPR10_LINI0_INT_M (0x00004000uL) -#define INTC_ICDISPR10_LINI1_INT_T (0x00008000uL) -#define INTC_ICDISPR10_LINI1_INT_R (0x00010000uL) -#define INTC_ICDISPR10_LINI1_INT_S (0x00020000uL) -#define INTC_ICDISPR10_LINI1_INT_M (0x00040000uL) -#define INTC_ICDISPR10_ERI0 (0x08000000uL) -#define INTC_ICDISPR10_RXI0 (0x10000000uL) -#define INTC_ICDISPR10_TXI0 (0x20000000uL) -#define INTC_ICDISPR10_TEI0 (0x40000000uL) -#define INTC_ICDISPR10_ERI1 (0x80000000uL) - -#define INTC_ICDISPR11_RXI1 (0x00000001uL) -#define INTC_ICDISPR11_TXI1 (0x00000002uL) -#define INTC_ICDISPR11_TEI1 (0x00000004uL) -#define INTC_ICDISPR11_AVBI_DATA (0x00000008uL) -#define INTC_ICDISPR11_AVBI_ERROR (0x00000010uL) -#define INTC_ICDISPR11_AVBI_MANAGE (0x00000020uL) -#define INTC_ICDISPR11_AVBI_MAC (0x00000040uL) -#define INTC_ICDISPR11_ETHERI (0x00000080uL) -#define INTC_ICDISPR11_CEUI (0x00001000uL) -#define INTC_ICDISPR11_H2XMLB_ERRINT (0x20000000uL) -#define INTC_ICDISPR11_H2XIC1_ERRINT (0x40000000uL) -#define INTC_ICDISPR11_X2HPERI1_ERRINT (0x80000000uL) - -#define INTC_ICDISPR12_X2HPERI2_ERRINT (0x00000001uL) -#define INTC_ICDISPR12_X2HPERI34_ERRINT (0x00000002uL) -#define INTC_ICDISPR12_X2HPERI5_ERRINT (0x00000004uL) -#define INTC_ICDISPR12_X2HPERI67_ERRINT (0x00000008uL) -#define INTC_ICDISPR12_X2HDBGR_ERRINT (0x00000010uL) -#define INTC_ICDISPR12_X2HBSC_ERRINT (0x00000020uL) -#define INTC_ICDISPR12_X2HSPI1_ERRINT (0x00000040uL) -#define INTC_ICDISPR12_X2HSPI2_ERRINT (0x00000080uL) -#define INTC_ICDISPR12_PRRI (0x00000100uL) -#define INTC_ICDISPR12_IFEI0 (0x00000200uL) -#define INTC_ICDISPR12_OFFI0 (0x00000400uL) -#define INTC_ICDISPR12_PFVEI0 (0x00000800uL) -#define INTC_ICDISPR12_IFEI1 (0x00001000uL) -#define INTC_ICDISPR12_OFFI1 (0x00002000uL) -#define INTC_ICDISPR12_PFVEI1 (0x00004000uL) - -#define INTC_ICDISPR13_TINT0 (0x00000001uL) -#define INTC_ICDISPR13_TINT1 (0x00000002uL) -#define INTC_ICDISPR13_TINT2 (0x00000004uL) -#define INTC_ICDISPR13_TINT3 (0x00000008uL) -#define INTC_ICDISPR13_TINT4 (0x00000010uL) -#define INTC_ICDISPR13_TINT5 (0x00000020uL) -#define INTC_ICDISPR13_TINT6 (0x00000040uL) -#define INTC_ICDISPR13_TINT7 (0x00000080uL) -#define INTC_ICDISPR13_TINT8 (0x00000100uL) -#define INTC_ICDISPR13_TINT9 (0x00000200uL) -#define INTC_ICDISPR13_TINT10 (0x00000400uL) -#define INTC_ICDISPR13_TINT11 (0x00000800uL) -#define INTC_ICDISPR13_TINT12 (0x00001000uL) -#define INTC_ICDISPR13_TINT13 (0x00002000uL) -#define INTC_ICDISPR13_TINT14 (0x00004000uL) -#define INTC_ICDISPR13_TINT15 (0x00008000uL) -#define INTC_ICDISPR13_TINT16 (0x00010000uL) -#define INTC_ICDISPR13_TINT17 (0x00020000uL) -#define INTC_ICDISPR13_TINT18 (0x00040000uL) -#define INTC_ICDISPR13_TINT19 (0x00080000uL) -#define INTC_ICDISPR13_TINT20 (0x00100000uL) -#define INTC_ICDISPR13_TINT21 (0x00200000uL) -#define INTC_ICDISPR13_TINT22 (0x00400000uL) -#define INTC_ICDISPR13_TINT23 (0x00800000uL) -#define INTC_ICDISPR13_TINT24 (0x01000000uL) -#define INTC_ICDISPR13_TINT25 (0x02000000uL) -#define INTC_ICDISPR13_TINT26 (0x04000000uL) -#define INTC_ICDISPR13_TINT27 (0x08000000uL) -#define INTC_ICDISPR13_TINT28 (0x10000000uL) -#define INTC_ICDISPR13_TINT29 (0x20000000uL) -#define INTC_ICDISPR13_TINT30 (0x40000000uL) -#define INTC_ICDISPR13_TINT31 (0x80000000uL) - -#define INTC_ICDISPR14_TINT32 (0x00000001uL) -#define INTC_ICDISPR14_TINT33 (0x00000002uL) -#define INTC_ICDISPR14_TINT34 (0x00000004uL) -#define INTC_ICDISPR14_TINT35 (0x00000008uL) -#define INTC_ICDISPR14_TINT36 (0x00000010uL) -#define INTC_ICDISPR14_TINT37 (0x00000020uL) -#define INTC_ICDISPR14_TINT38 (0x00000040uL) -#define INTC_ICDISPR14_TINT39 (0x00000080uL) -#define INTC_ICDISPR14_TINT40 (0x00000100uL) -#define INTC_ICDISPR14_TINT41 (0x00000200uL) -#define INTC_ICDISPR14_TINT42 (0x00000400uL) -#define INTC_ICDISPR14_TINT43 (0x00000800uL) -#define INTC_ICDISPR14_TINT44 (0x00001000uL) -#define INTC_ICDISPR14_TINT45 (0x00002000uL) -#define INTC_ICDISPR14_TINT46 (0x00004000uL) -#define INTC_ICDISPR14_TINT47 (0x00008000uL) -#define INTC_ICDISPR14_TINT48 (0x00010000uL) -#define INTC_ICDISPR14_TINT49 (0x00020000uL) -#define INTC_ICDISPR14_TINT50 (0x00040000uL) -#define INTC_ICDISPR14_TINT51 (0x00080000uL) -#define INTC_ICDISPR14_TINT52 (0x00100000uL) -#define INTC_ICDISPR14_TINT53 (0x00200000uL) -#define INTC_ICDISPR14_TINT54 (0x00400000uL) -#define INTC_ICDISPR14_TINT55 (0x00800000uL) -#define INTC_ICDISPR14_TINT56 (0x01000000uL) -#define INTC_ICDISPR14_TINT57 (0x02000000uL) -#define INTC_ICDISPR14_TINT58 (0x04000000uL) -#define INTC_ICDISPR14_TINT59 (0x08000000uL) -#define INTC_ICDISPR14_TINT60 (0x10000000uL) -#define INTC_ICDISPR14_TINT61 (0x20000000uL) -#define INTC_ICDISPR14_TINT62 (0x40000000uL) -#define INTC_ICDISPR14_TINT63 (0x80000000uL) - -#define INTC_ICDISPR15_TINT64 (0x00000001uL) -#define INTC_ICDISPR15_TINT65 (0x00000002uL) -#define INTC_ICDISPR15_TINT66 (0x00000004uL) -#define INTC_ICDISPR15_TINT67 (0x00000008uL) -#define INTC_ICDISPR15_TINT68 (0x00000010uL) -#define INTC_ICDISPR15_TINT69 (0x00000020uL) -#define INTC_ICDISPR15_TINT70 (0x00000040uL) -#define INTC_ICDISPR15_TINT71 (0x00000080uL) -#define INTC_ICDISPR15_TINT72 (0x00000100uL) -#define INTC_ICDISPR15_TINT73 (0x00000200uL) -#define INTC_ICDISPR15_TINT74 (0x00000400uL) -#define INTC_ICDISPR15_TINT75 (0x00000800uL) -#define INTC_ICDISPR15_TINT76 (0x00001000uL) -#define INTC_ICDISPR15_TINT77 (0x00002000uL) -#define INTC_ICDISPR15_TINT78 (0x00004000uL) -#define INTC_ICDISPR15_TINT79 (0x00008000uL) -#define INTC_ICDISPR15_TINT80 (0x00010000uL) -#define INTC_ICDISPR15_TINT81 (0x00020000uL) -#define INTC_ICDISPR15_TINT82 (0x00040000uL) -#define INTC_ICDISPR15_TINT83 (0x00080000uL) -#define INTC_ICDISPR15_TINT84 (0x00100000uL) -#define INTC_ICDISPR15_TINT85 (0x00200000uL) -#define INTC_ICDISPR15_TINT86 (0x00400000uL) -#define INTC_ICDISPR15_TINT87 (0x00800000uL) -#define INTC_ICDISPR15_TINT88 (0x01000000uL) -#define INTC_ICDISPR15_TINT89 (0x02000000uL) -#define INTC_ICDISPR15_TINT90 (0x04000000uL) -#define INTC_ICDISPR15_TINT91 (0x08000000uL) -#define INTC_ICDISPR15_TINT92 (0x10000000uL) -#define INTC_ICDISPR15_TINT93 (0x20000000uL) -#define INTC_ICDISPR15_TINT94 (0x40000000uL) -#define INTC_ICDISPR15_TINT95 (0x80000000uL) - -#define INTC_ICDISPR16_TINT96 (0x00000001uL) -#define INTC_ICDISPR16_TINT97 (0x00000002uL) -#define INTC_ICDISPR16_TINT98 (0x00000004uL) -#define INTC_ICDISPR16_TINT99 (0x00000008uL) -#define INTC_ICDISPR16_TINT100 (0x00000010uL) -#define INTC_ICDISPR16_TINT101 (0x00000020uL) -#define INTC_ICDISPR16_TINT102 (0x00000040uL) -#define INTC_ICDISPR16_TINT103 (0x00000080uL) -#define INTC_ICDISPR16_TINT104 (0x00000100uL) -#define INTC_ICDISPR16_TINT105 (0x00000200uL) -#define INTC_ICDISPR16_TINT106 (0x00000400uL) -#define INTC_ICDISPR16_TINT107 (0x00000800uL) -#define INTC_ICDISPR16_TINT108 (0x00001000uL) -#define INTC_ICDISPR16_TINT109 (0x00002000uL) -#define INTC_ICDISPR16_TINT110 (0x00004000uL) -#define INTC_ICDISPR16_TINT111 (0x00008000uL) -#define INTC_ICDISPR16_TINT112 (0x00010000uL) -#define INTC_ICDISPR16_TINT113 (0x00020000uL) -#define INTC_ICDISPR16_TINT114 (0x00040000uL) -#define INTC_ICDISPR16_TINT115 (0x00080000uL) -#define INTC_ICDISPR16_TINT116 (0x00100000uL) -#define INTC_ICDISPR16_TINT117 (0x00200000uL) -#define INTC_ICDISPR16_TINT118 (0x00400000uL) -#define INTC_ICDISPR16_TINT119 (0x00800000uL) -#define INTC_ICDISPR16_TINT120 (0x01000000uL) -#define INTC_ICDISPR16_TINT121 (0x02000000uL) -#define INTC_ICDISPR16_TINT122 (0x04000000uL) -#define INTC_ICDISPR16_TINT123 (0x08000000uL) -#define INTC_ICDISPR16_TINT124 (0x10000000uL) -#define INTC_ICDISPR16_TINT125 (0x20000000uL) -#define INTC_ICDISPR16_TINT126 (0x40000000uL) -#define INTC_ICDISPR16_TINT127 (0x80000000uL) - -#define INTC_ICDISPR17_TINT128 (0x00000001uL) -#define INTC_ICDISPR17_TINT129 (0x00000002uL) -#define INTC_ICDISPR17_TINT130 (0x00000004uL) -#define INTC_ICDISPR17_TINT131 (0x00000008uL) -#define INTC_ICDISPR17_TINT132 (0x00000010uL) -#define INTC_ICDISPR17_TINT133 (0x00000020uL) -#define INTC_ICDISPR17_TINT134 (0x00000040uL) -#define INTC_ICDISPR17_TINT135 (0x00000080uL) -#define INTC_ICDISPR17_TINT136 (0x00000100uL) -#define INTC_ICDISPR17_TINT137 (0x00000200uL) -#define INTC_ICDISPR17_TINT138 (0x00000400uL) -#define INTC_ICDISPR17_TINT139 (0x00000800uL) -#define INTC_ICDISPR17_TINT140 (0x00001000uL) -#define INTC_ICDISPR17_TINT141 (0x00002000uL) -#define INTC_ICDISPR17_TINT142 (0x00004000uL) -#define INTC_ICDISPR17_TINT143 (0x00008000uL) -#define INTC_ICDISPR17_TINT144 (0x00010000uL) -#define INTC_ICDISPR17_TINT145 (0x00020000uL) -#define INTC_ICDISPR17_TINT146 (0x00040000uL) -#define INTC_ICDISPR17_TINT147 (0x00080000uL) -#define INTC_ICDISPR17_TINT148 (0x00100000uL) -#define INTC_ICDISPR17_TINT149 (0x00200000uL) -#define INTC_ICDISPR17_TINT150 (0x00400000uL) -#define INTC_ICDISPR17_TINT151 (0x00800000uL) -#define INTC_ICDISPR17_TINT152 (0x01000000uL) -#define INTC_ICDISPR17_TINT153 (0x02000000uL) -#define INTC_ICDISPR17_TINT154 (0x04000000uL) -#define INTC_ICDISPR17_TINT155 (0x08000000uL) -#define INTC_ICDISPR17_TINT156 (0x10000000uL) -#define INTC_ICDISPR17_TINT157 (0x20000000uL) -#define INTC_ICDISPR17_TINT158 (0x40000000uL) -#define INTC_ICDISPR17_TINT159 (0x80000000uL) - -#define INTC_ICDISPR18_TINT160 (0x00000001uL) -#define INTC_ICDISPR18_TINT161 (0x00000002uL) -#define INTC_ICDISPR18_TINT162 (0x00000004uL) -#define INTC_ICDISPR18_TINT163 (0x00000008uL) -#define INTC_ICDISPR18_TINT164 (0x00000010uL) -#define INTC_ICDISPR18_TINT165 (0x00000020uL) -#define INTC_ICDISPR18_TINT166 (0x00000040uL) -#define INTC_ICDISPR18_TINT167 (0x00000080uL) -#define INTC_ICDISPR18_TINT168 (0x00000100uL) -#define INTC_ICDISPR18_TINT169 (0x00000200uL) -#define INTC_ICDISPR18_TINT170 (0x00000400uL) - -#define INTC_ICDICPR0_SW0 (0x00000001uL) -#define INTC_ICDICPR0_SW1 (0x00000002uL) -#define INTC_ICDICPR0_SW2 (0x00000004uL) -#define INTC_ICDICPR0_SW3 (0x00000008uL) -#define INTC_ICDICPR0_SW4 (0x00000010uL) -#define INTC_ICDICPR0_SW5 (0x00000020uL) -#define INTC_ICDICPR0_SW6 (0x00000040uL) -#define INTC_ICDICPR0_SW7 (0x00000080uL) -#define INTC_ICDICPR0_SW8 (0x00000100uL) -#define INTC_ICDICPR0_SW9 (0x00000200uL) -#define INTC_ICDICPR0_SW10 (0x00000400uL) -#define INTC_ICDICPR0_SW11 (0x00000800uL) -#define INTC_ICDICPR0_SW12 (0x00001000uL) -#define INTC_ICDICPR0_SW13 (0x00002000uL) -#define INTC_ICDICPR0_SW14 (0x00004000uL) -#define INTC_ICDICPR0_SW15 (0x00008000uL) -#define INTC_ICDICPR0_PMUIRQ0 (0x00010000uL) -#define INTC_ICDICPR0_COMMRX0 (0x00020000uL) -#define INTC_ICDICPR0_COMMTX0 (0x00040000uL) -#define INTC_ICDICPR0_CTIIRQ0 (0x00080000uL) - -#define INTC_ICDICPR1_IRQ0 (0x00000001uL) -#define INTC_ICDICPR1_IRQ1 (0x00000002uL) -#define INTC_ICDICPR1_IRQ2 (0x00000004uL) -#define INTC_ICDICPR1_IRQ3 (0x00000008uL) -#define INTC_ICDICPR1_IRQ4 (0x00000010uL) -#define INTC_ICDICPR1_IRQ5 (0x00000020uL) -#define INTC_ICDICPR1_IRQ6 (0x00000040uL) -#define INTC_ICDICPR1_IRQ7 (0x00000080uL) -#define INTC_ICDICPR1_PL310ERR (0x00000100uL) -#define INTC_ICDICPR1_DMAINT0 (0x00000200uL) -#define INTC_ICDICPR1_DMAINT1 (0x00000400uL) -#define INTC_ICDICPR1_DMAINT2 (0x00000800uL) -#define INTC_ICDICPR1_DMAINT3 (0x00001000uL) -#define INTC_ICDICPR1_DMAINT4 (0x00002000uL) -#define INTC_ICDICPR1_DMAINT5 (0x00004000uL) -#define INTC_ICDICPR1_DMAINT6 (0x00008000uL) -#define INTC_ICDICPR1_DMAINT7 (0x00010000uL) -#define INTC_ICDICPR1_DMAINT8 (0x00020000uL) -#define INTC_ICDICPR1_DMAINT9 (0x00040000uL) -#define INTC_ICDICPR1_DMAINT10 (0x00080000uL) -#define INTC_ICDICPR1_DMAINT11 (0x00100000uL) -#define INTC_ICDICPR1_DMAINT12 (0x00200000uL) -#define INTC_ICDICPR1_DMAINT13 (0x00400000uL) -#define INTC_ICDICPR1_DMAINT14 (0x00800000uL) -#define INTC_ICDICPR1_DMAINT15 (0x01000000uL) -#define INTC_ICDICPR1_DMAERR (0x02000000uL) - -#define INTC_ICDICPR2_USBI0 (0x00000200uL) -#define INTC_ICDICPR2_USBI1 (0x00000400uL) -#define INTC_ICDICPR2_S0_VI_VSYNC0 (0x00000800uL) -#define INTC_ICDICPR2_S0_LO_VSYNC0 (0x00001000uL) -#define INTC_ICDICPR2_S0_VSYNCERR0 (0x00002000uL) -#define INTC_ICDICPR2_GR3_VLINE0 (0x00004000uL) -#define INTC_ICDICPR2_S0_VFIELD0 (0x00008000uL) -#define INTC_ICDICPR2_IV1_VBUFERR0 (0x00010000uL) -#define INTC_ICDICPR2_IV3_VBUFERR0 (0x00020000uL) -#define INTC_ICDICPR2_IV5_VBUFERR0 (0x00040000uL) -#define INTC_ICDICPR2_IV6_VBUFERR0 (0x00080000uL) -#define INTC_ICDICPR2_S0_WLINE0 (0x00100000uL) -#define INTC_ICDICPR2_S1_VI_VSYNC0 (0x00200000uL) -#define INTC_ICDICPR2_S1_LO_VSYNC0 (0x00400000uL) -#define INTC_ICDICPR2_S1_VSYNCERR0 (0x00800000uL) -#define INTC_ICDICPR2_S1_VFIELD0 (0x01000000uL) -#define INTC_ICDICPR2_IV2_VBUFERR0 (0x02000000uL) -#define INTC_ICDICPR2_IV4_VBUFERR0 (0x04000000uL) -#define INTC_ICDICPR2_S1_WLINE0 (0x08000000uL) -#define INTC_ICDICPR2_OIR_VI_VSYNC0 (0x10000000uL) -#define INTC_ICDICPR2_OIR_LO_VSYNC0 (0x20000000uL) -#define INTC_ICDICPR2_OIR_VSYNCERR0 (0x40000000uL) -#define INTC_ICDICPR2_OIR_VFIELD0 (0x80000000uL) - -#define INTC_ICDICPR3_IV7_VBUFERR0 (0x00000001uL) -#define INTC_ICDICPR3_IV8_VBUFERR0 (0x00000002uL) -#define INTC_ICDICPR3_S0_VI_VSYNC1 (0x00000008uL) -#define INTC_ICDICPR3_S0_LO_VSYNC1 (0x00000010uL) -#define INTC_ICDICPR3_S0_VSYNCERR1 (0x00000020uL) -#define INTC_ICDICPR3_GR3_VLINE1 (0x00000040uL) -#define INTC_ICDICPR3_S0_VFIELD1 (0x00000080uL) -#define INTC_ICDICPR3_IV1_VBUFERR1 (0x00000100uL) -#define INTC_ICDICPR3_IV3_VBUFERR1 (0x00000200uL) -#define INTC_ICDICPR3_IV5_VBUFERR1 (0x00000400uL) -#define INTC_ICDICPR3_IV6_VBUFERR1 (0x00000800uL) -#define INTC_ICDICPR3_S0_WLINE1 (0x00001000uL) -#define INTC_ICDICPR3_S1_VI_VSYNC1 (0x00002000uL) -#define INTC_ICDICPR3_S1_LO_VSYNC1 (0x00004000uL) -#define INTC_ICDICPR3_S1_VSYNCERR1 (0x00008000uL) -#define INTC_ICDICPR3_S1_VFIELD1 (0x00010000uL) -#define INTC_ICDICPR3_IV2_VBUFERR1 (0x00020000uL) -#define INTC_ICDICPR3_IV4_VBUFERR1 (0x00040000uL) -#define INTC_ICDICPR3_S1_WLINE1 (0x00080000uL) -#define INTC_ICDICPR3_OIR_VI_VSYNC1 (0x00100000uL) -#define INTC_ICDICPR3_OIR_LO_VSYNC1 (0x00200000uL) -#define INTC_ICDICPR3_OIR_VLINE1 (0x00400000uL) -#define INTC_ICDICPR3_OIR_VFIELD1 (0x00800000uL) -#define INTC_ICDICPR3_IV7_VBUFERR1 (0x01000000uL) -#define INTC_ICDICPR3_IV8_VBUFERR1 (0x02000000uL) -#define INTC_ICDICPR3_IMRDI (0x08000000uL) -#define INTC_ICDICPR3_IMR2I0 (0x10000000uL) -#define INTC_ICDICPR3_IMR2I1 (0x20000000uL) -#define INTC_ICDICPR3_JEDI (0x40000000uL) -#define INTC_ICDICPR3_JDTI (0x80000000uL) - -#define INTC_ICDICPR4_CMP0 (0x00000001uL) -#define INTC_ICDICPR4_CMP1 (0x00000002uL) -#define INTC_ICDICPR4_INT0 (0x00000004uL) -#define INTC_ICDICPR4_INT1 (0x00000008uL) -#define INTC_ICDICPR4_INT2 (0x00000010uL) -#define INTC_ICDICPR4_INT3 (0x00000020uL) -#define INTC_ICDICPR4_OSTM0TINT (0x00000040uL) -#define INTC_ICDICPR4_OSTM1TINT (0x00000080uL) -#define INTC_ICDICPR4_CMI (0x00000100uL) -#define INTC_ICDICPR4_WTOUT (0x00000200uL) -#define INTC_ICDICPR4_ITI (0x00000400uL) -#define INTC_ICDICPR4_TGI0A (0x00000800uL) -#define INTC_ICDICPR4_TGI0B (0x00001000uL) -#define INTC_ICDICPR4_TGI0C (0x00002000uL) -#define INTC_ICDICPR4_TGI0D (0x00004000uL) -#define INTC_ICDICPR4_TGI0V (0x00008000uL) -#define INTC_ICDICPR4_TGI0E (0x00010000uL) -#define INTC_ICDICPR4_TGI0F (0x00020000uL) -#define INTC_ICDICPR4_TGI1A (0x00040000uL) -#define INTC_ICDICPR4_TGI1B (0x00080000uL) -#define INTC_ICDICPR4_TGI1V (0x00100000uL) -#define INTC_ICDICPR4_TGI1U (0x00200000uL) -#define INTC_ICDICPR4_TGI2A (0x00400000uL) -#define INTC_ICDICPR4_TGI2B (0x00800000uL) -#define INTC_ICDICPR4_TGI2V (0x01000000uL) -#define INTC_ICDICPR4_TGI2U (0x02000000uL) -#define INTC_ICDICPR4_TGI3A (0x04000000uL) -#define INTC_ICDICPR4_TGI3B (0x08000000uL) -#define INTC_ICDICPR4_TGI3C (0x10000000uL) -#define INTC_ICDICPR4_TGI3D (0x20000000uL) -#define INTC_ICDICPR4_TGI3V (0x40000000uL) -#define INTC_ICDICPR4_TGI4A (0x80000000uL) - -#define INTC_ICDICPR5_TGI4B (0x00000001uL) -#define INTC_ICDICPR5_TGI4C (0x00000002uL) -#define INTC_ICDICPR5_TGI4D (0x00000004uL) -#define INTC_ICDICPR5_TGI4V (0x00000008uL) -#define INTC_ICDICPR5_CMI1 (0x00000010uL) -#define INTC_ICDICPR5_CMI2 (0x00000020uL) -#define INTC_ICDICPR5_SGDEI0 (0x00000040uL) -#define INTC_ICDICPR5_SGDEI1 (0x00000080uL) -#define INTC_ICDICPR5_SGDEI2 (0x00000100uL) -#define INTC_ICDICPR5_SGDEI3 (0x00000200uL) -#define INTC_ICDICPR5_ADI (0x00000400uL) -#define INTC_ICDICPR5_LMTI (0x00000800uL) -#define INTC_ICDICPR5_SSII0 (0x00001000uL) -#define INTC_ICDICPR5_SSIRXI0 (0x00002000uL) -#define INTC_ICDICPR5_SSITXI0 (0x00004000uL) -#define INTC_ICDICPR5_SSII1 (0x00008000uL) -#define INTC_ICDICPR5_SSIRXI1 (0x00010000uL) -#define INTC_ICDICPR5_SSITXI1 (0x00020000uL) -#define INTC_ICDICPR5_SSII2 (0x00040000uL) -#define INTC_ICDICPR5_SSIRTI2 (0x00080000uL) -#define INTC_ICDICPR5_SSII3 (0x00100000uL) -#define INTC_ICDICPR5_SSIRXI3 (0x00200000uL) -#define INTC_ICDICPR5_SSITXI3 (0x00400000uL) -#define INTC_ICDICPR5_SSII4 (0x00800000uL) -#define INTC_ICDICPR5_SSIRTI4 (0x01000000uL) -#define INTC_ICDICPR5_SSII5 (0x02000000uL) -#define INTC_ICDICPR5_SSIRXI5 (0x04000000uL) -#define INTC_ICDICPR5_SSITXI5 (0x08000000uL) -#define INTC_ICDICPR5_SPDIFI (0x10000000uL) -#define INTC_ICDICPR5_INTIICTEI0 (0x20000000uL) -#define INTC_ICDICPR5_INTIICRI0 (0x40000000uL) -#define INTC_ICDICPR5_INTIICTI0 (0x80000000uL) - -#define INTC_ICDICPR6_INTIICSPI0 (0x00000001uL) -#define INTC_ICDICPR6_INTIICSTI0 (0x00000002uL) -#define INTC_ICDICPR6_INTIICNAKI0 (0x00000004uL) -#define INTC_ICDICPR6_INTIICALI0 (0x00000008uL) -#define INTC_ICDICPR6_INTIICTMOI0 (0x00000010uL) -#define INTC_ICDICPR6_INTIICTEI1 (0x00000020uL) -#define INTC_ICDICPR6_INTIICRI1 (0x00000040uL) -#define INTC_ICDICPR6_INTIICTI1 (0x00000080uL) -#define INTC_ICDICPR6_INTIICSPI1 (0x00000100uL) -#define INTC_ICDICPR6_INTIICSTI1 (0x00000200uL) -#define INTC_ICDICPR6_INTIICNAKI1 (0x00000400uL) -#define INTC_ICDICPR6_INTIICALI1 (0x00000800uL) -#define INTC_ICDICPR6_INTIICTMOI1 (0x00001000uL) -#define INTC_ICDICPR6_INTIICTEI2 (0x00002000uL) -#define INTC_ICDICPR6_INTIICRI2 (0x00004000uL) -#define INTC_ICDICPR6_INTIICTI2 (0x00008000uL) -#define INTC_ICDICPR6_INTIICSPI2 (0x00010000uL) -#define INTC_ICDICPR6_INTIICSTI2 (0x00020000uL) -#define INTC_ICDICPR6_INTIICNAKI2 (0x00040000uL) -#define INTC_ICDICPR6_INTIICALI2 (0x00080000uL) -#define INTC_ICDICPR6_INTIICTMOI2 (0x00100000uL) -#define INTC_ICDICPR6_INTIICTEI3 (0x00200000uL) -#define INTC_ICDICPR6_INTIICRI3 (0x00400000uL) -#define INTC_ICDICPR6_INTIICTI3 (0x00800000uL) -#define INTC_ICDICPR6_INTIICSPI3 (0x01000000uL) -#define INTC_ICDICPR6_INTIICSTI3 (0x02000000uL) -#define INTC_ICDICPR6_INTIICNAKI3 (0x04000000uL) -#define INTC_ICDICPR6_INTIICALI3 (0x08000000uL) -#define INTC_ICDICPR6_INTIICTMOI3 (0x10000000uL) -#define INTC_ICDICPR6_BRI0 (0x20000000uL) -#define INTC_ICDICPR6_ERI0 (0x40000000uL) -#define INTC_ICDICPR6_RXI0 (0x80000000uL) - -#define INTC_ICDICPR7_TXI0 (0x00000001uL) -#define INTC_ICDICPR7_BRI1 (0x00000002uL) -#define INTC_ICDICPR7_ERI1 (0x00000004uL) -#define INTC_ICDICPR7_RXI1 (0x00000008uL) -#define INTC_ICDICPR7_TXI1 (0x00000010uL) -#define INTC_ICDICPR7_BRI2 (0x00000020uL) -#define INTC_ICDICPR7_ERI2 (0x00000040uL) -#define INTC_ICDICPR7_RXI2 (0x00000080uL) -#define INTC_ICDICPR7_TXI2 (0x00000100uL) -#define INTC_ICDICPR7_BRI3 (0x00000200uL) -#define INTC_ICDICPR7_ERI3 (0x00000400uL) -#define INTC_ICDICPR7_RXI3 (0x00000800uL) -#define INTC_ICDICPR7_TXI3 (0x00001000uL) -#define INTC_ICDICPR7_BRI4 (0x00002000uL) -#define INTC_ICDICPR7_ERI4 (0x00004000uL) -#define INTC_ICDICPR7_RXI4 (0x00008000uL) -#define INTC_ICDICPR7_TXI4 (0x00010000uL) -#define INTC_ICDICPR7_BRI5 (0x00020000uL) -#define INTC_ICDICPR7_ERI5 (0x00040000uL) -#define INTC_ICDICPR7_RXI5 (0x00080000uL) -#define INTC_ICDICPR7_TXI5 (0x00100000uL) -#define INTC_ICDICPR7_BRI6 (0x00200000uL) -#define INTC_ICDICPR7_ERI6 (0x00400000uL) -#define INTC_ICDICPR7_RXI6 (0x00800000uL) -#define INTC_ICDICPR7_TXI6 (0x01000000uL) -#define INTC_ICDICPR7_BRI7 (0x02000000uL) -#define INTC_ICDICPR7_ERI7 (0x04000000uL) -#define INTC_ICDICPR7_RXI7 (0x08000000uL) -#define INTC_ICDICPR7_TXI7 (0x10000000uL) -#define INTC_ICDICPR7_INTRCANGERR (0x20000000uL) -#define INTC_ICDICPR7_INTRCANGRECC (0x40000000uL) -#define INTC_ICDICPR7_INTRCAN0REC (0x80000000uL) - -#define INTC_ICDICPR8_INTRCAN0ERR (0x00000001uL) -#define INTC_ICDICPR8_INTRCAN0TRX (0x00000002uL) -#define INTC_ICDICPR8_INTRCAN1REC (0x00000004uL) -#define INTC_ICDICPR8_INTRCAN1ERR (0x00000008uL) -#define INTC_ICDICPR8_INTRCAN1TRX (0x00000010uL) -#define INTC_ICDICPR8_INTRCAN2REC (0x00000020uL) -#define INTC_ICDICPR8_INTRCAN2ERR (0x00000040uL) -#define INTC_ICDICPR8_INTRCAN2TRX (0x00000080uL) -#define INTC_ICDICPR8_INTRCAN3REC (0x00000100uL) -#define INTC_ICDICPR8_INTRCAN3ERR (0x00000200uL) -#define INTC_ICDICPR8_INTRCAN3TRX (0x00000400uL) -#define INTC_ICDICPR8_INTRCAN4REC (0x00000800uL) -#define INTC_ICDICPR8_INTRCAN4ERR (0x00001000uL) -#define INTC_ICDICPR8_INTRCAN4TRX (0x00002000uL) -#define INTC_ICDICPR8_SPEI0 (0x00004000uL) -#define INTC_ICDICPR8_SPRI0 (0x00008000uL) -#define INTC_ICDICPR8_SPTI0 (0x00010000uL) -#define INTC_ICDICPR8_SPEI1 (0x00020000uL) -#define INTC_ICDICPR8_SPRI1 (0x00040000uL) -#define INTC_ICDICPR8_SPTI1 (0x00080000uL) -#define INTC_ICDICPR8_SPEI2 (0x00100000uL) -#define INTC_ICDICPR8_SPRI2 (0x00200000uL) -#define INTC_ICDICPR8_SPTI2 (0x00400000uL) -#define INTC_ICDICPR8_SPEI3 (0x00800000uL) -#define INTC_ICDICPR8_SPRI3 (0x01000000uL) -#define INTC_ICDICPR8_SPTI3 (0x02000000uL) -#define INTC_ICDICPR8_SPEI4 (0x04000000uL) -#define INTC_ICDICPR8_SPRI4 (0x08000000uL) -#define INTC_ICDICPR8_SPTI4 (0x10000000uL) -#define INTC_ICDICPR8_IEBBTD (0x20000000uL) -#define INTC_ICDICPR8_IEBBTERR (0x40000000uL) -#define INTC_ICDICPR8_IEBBTSTA (0x80000000uL) - -#define INTC_ICDICPR9_IEBBTV (0x00000001uL) -#define INTC_ICDICPR9_ISY (0x00000002uL) -#define INTC_ICDICPR9_IERR (0x00000004uL) -#define INTC_ICDICPR9_ITARG (0x00000008uL) -#define INTC_ICDICPR9_ISEC (0x00000010uL) -#define INTC_ICDICPR9_IBUF (0x00000020uL) -#define INTC_ICDICPR9_IREADY (0x00000040uL) -#define INTC_ICDICPR9_FLSTE (0x00000080uL) -#define INTC_ICDICPR9_FLTENDI (0x00000100uL) -#define INTC_ICDICPR9_FLTREQ0I (0x00000200uL) -#define INTC_ICDICPR9_FLTREQ1I (0x00000400uL) -#define INTC_ICDICPR9_MMC0 (0x00000800uL) -#define INTC_ICDICPR9_MMC1 (0x00001000uL) -#define INTC_ICDICPR9_MMC2 (0x00002000uL) -#define INTC_ICDICPR9_SDHI0_3 (0x00004000uL) -#define INTC_ICDICPR9_SDHI0_0 (0x00008000uL) -#define INTC_ICDICPR9_SDHI0_1 (0x00010000uL) -#define INTC_ICDICPR9_SDHI1_3 (0x00020000uL) -#define INTC_ICDICPR9_SDHI1_0 (0x00040000uL) -#define INTC_ICDICPR9_SDHI1_1 (0x00080000uL) -#define INTC_ICDICPR9_ARM (0x00100000uL) -#define INTC_ICDICPR9_PRD (0x00200000uL) -#define INTC_ICDICPR9_CUP (0x00400000uL) -#define INTC_ICDICPR9_SCUAI0 (0x00800000uL) -#define INTC_ICDICPR9_SCUAI1 (0x01000000uL) -#define INTC_ICDICPR9_SCUFDI0 (0x02000000uL) -#define INTC_ICDICPR9_SCUFDI1 (0x04000000uL) -#define INTC_ICDICPR9_SCUFDI2 (0x08000000uL) -#define INTC_ICDICPR9_SCUFDI3 (0x10000000uL) -#define INTC_ICDICPR9_SCUFUI0 (0x20000000uL) -#define INTC_ICDICPR9_SCUFUI1 (0x40000000uL) -#define INTC_ICDICPR9_SCUFUI2 (0x80000000uL) - -#define INTC_ICDICPR10_SCUFUI3 (0x00000001uL) -#define INTC_ICDICPR10_SCUDVI0 (0x00000002uL) -#define INTC_ICDICPR10_SCUDVI1 (0x00000004uL) -#define INTC_ICDICPR10_SCUDVI2 (0x00000008uL) -#define INTC_ICDICPR10_SCUDVI3 (0x00000010uL) -#define INTC_ICDICPR10_MLB_CINT (0x00000020uL) -#define INTC_ICDICPR10_MLB_SINT (0x00000040uL) -#define INTC_ICDICPR10_DRC0 (0x00000080uL) -#define INTC_ICDICPR10_DRC1 (0x00000100uL) -#define INTC_ICDICPR10_LINI0_INT_T (0x00000800uL) -#define INTC_ICDICPR10_LINI0_INT_R (0x00001000uL) -#define INTC_ICDICPR10_LINI0_INT_S (0x00002000uL) -#define INTC_ICDICPR10_LINI0_INT_M (0x00004000uL) -#define INTC_ICDICPR10_LINI1_INT_T (0x00008000uL) -#define INTC_ICDICPR10_LINI1_INT_R (0x00010000uL) -#define INTC_ICDICPR10_LINI1_INT_S (0x00020000uL) -#define INTC_ICDICPR10_LINI1_INT_M (0x00040000uL) -#define INTC_ICDICPR10_ERI0 (0x08000000uL) -#define INTC_ICDICPR10_RXI0 (0x10000000uL) -#define INTC_ICDICPR10_TXI0 (0x20000000uL) -#define INTC_ICDICPR10_TEI0 (0x40000000uL) -#define INTC_ICDICPR10_ERI1 (0x80000000uL) - -#define INTC_ICDICPR11_RXI1 (0x00000001uL) -#define INTC_ICDICPR11_TXI1 (0x00000002uL) -#define INTC_ICDICPR11_TEI1 (0x00000004uL) -#define INTC_ICDICPR11_AVBI_DATA (0x00000008uL) -#define INTC_ICDICPR11_AVBI_ERROR (0x00000010uL) -#define INTC_ICDICPR11_AVBI_MANAGE (0x00000020uL) -#define INTC_ICDICPR11_AVBI_MAC (0x00000040uL) -#define INTC_ICDICPR11_ETHERI (0x00000080uL) -#define INTC_ICDICPR11_CEUI (0x00001000uL) -#define INTC_ICDICPR11_H2XMLB_ERRINT (0x20000000uL) -#define INTC_ICDICPR11_H2XIC1_ERRINT (0x40000000uL) -#define INTC_ICDICPR11_X2HPERI1_ERRINT (0x80000000uL) - -#define INTC_ICDICPR12_X2HPERI2_ERRINT (0x00000001uL) -#define INTC_ICDICPR12_X2HPERI34_ERRINT (0x00000002uL) -#define INTC_ICDICPR12_X2HPERI5_ERRINT (0x00000004uL) -#define INTC_ICDICPR12_X2HPERI67_ERRINT (0x00000008uL) -#define INTC_ICDICPR12_X2HDBGR_ERRINT (0x00000010uL) -#define INTC_ICDICPR12_X2HBSC_ERRINT (0x00000020uL) -#define INTC_ICDICPR12_X2HSPI1_ERRINT (0x00000040uL) -#define INTC_ICDICPR12_X2HSPI2_ERRINT (0x00000080uL) -#define INTC_ICDICPR12_PRRI (0x00000100uL) -#define INTC_ICDICPR12_IFEI0 (0x00000200uL) -#define INTC_ICDICPR12_OFFI0 (0x00000400uL) -#define INTC_ICDICPR12_PFVEI0 (0x00000800uL) -#define INTC_ICDICPR12_IFEI1 (0x00001000uL) -#define INTC_ICDICPR12_OFFI1 (0x00002000uL) -#define INTC_ICDICPR12_PFVEI1 (0x00004000uL) - -#define INTC_ICDICPR13_TINT0 (0x00000001uL) -#define INTC_ICDICPR13_TINT1 (0x00000002uL) -#define INTC_ICDICPR13_TINT2 (0x00000004uL) -#define INTC_ICDICPR13_TINT3 (0x00000008uL) -#define INTC_ICDICPR13_TINT4 (0x00000010uL) -#define INTC_ICDICPR13_TINT5 (0x00000020uL) -#define INTC_ICDICPR13_TINT6 (0x00000040uL) -#define INTC_ICDICPR13_TINT7 (0x00000080uL) -#define INTC_ICDICPR13_TINT8 (0x00000100uL) -#define INTC_ICDICPR13_TINT9 (0x00000200uL) -#define INTC_ICDICPR13_TINT10 (0x00000400uL) -#define INTC_ICDICPR13_TINT11 (0x00000800uL) -#define INTC_ICDICPR13_TINT12 (0x00001000uL) -#define INTC_ICDICPR13_TINT13 (0x00002000uL) -#define INTC_ICDICPR13_TINT14 (0x00004000uL) -#define INTC_ICDICPR13_TINT15 (0x00008000uL) -#define INTC_ICDICPR13_TINT16 (0x00010000uL) -#define INTC_ICDICPR13_TINT17 (0x00020000uL) -#define INTC_ICDICPR13_TINT18 (0x00040000uL) -#define INTC_ICDICPR13_TINT19 (0x00080000uL) -#define INTC_ICDICPR13_TINT20 (0x00100000uL) -#define INTC_ICDICPR13_TINT21 (0x00200000uL) -#define INTC_ICDICPR13_TINT22 (0x00400000uL) -#define INTC_ICDICPR13_TINT23 (0x00800000uL) -#define INTC_ICDICPR13_TINT24 (0x01000000uL) -#define INTC_ICDICPR13_TINT25 (0x02000000uL) -#define INTC_ICDICPR13_TINT26 (0x04000000uL) -#define INTC_ICDICPR13_TINT27 (0x08000000uL) -#define INTC_ICDICPR13_TINT28 (0x10000000uL) -#define INTC_ICDICPR13_TINT29 (0x20000000uL) -#define INTC_ICDICPR13_TINT30 (0x40000000uL) -#define INTC_ICDICPR13_TINT31 (0x80000000uL) - -#define INTC_ICDICPR14_TINT32 (0x00000001uL) -#define INTC_ICDICPR14_TINT33 (0x00000002uL) -#define INTC_ICDICPR14_TINT34 (0x00000004uL) -#define INTC_ICDICPR14_TINT35 (0x00000008uL) -#define INTC_ICDICPR14_TINT36 (0x00000010uL) -#define INTC_ICDICPR14_TINT37 (0x00000020uL) -#define INTC_ICDICPR14_TINT38 (0x00000040uL) -#define INTC_ICDICPR14_TINT39 (0x00000080uL) -#define INTC_ICDICPR14_TINT40 (0x00000100uL) -#define INTC_ICDICPR14_TINT41 (0x00000200uL) -#define INTC_ICDICPR14_TINT42 (0x00000400uL) -#define INTC_ICDICPR14_TINT43 (0x00000800uL) -#define INTC_ICDICPR14_TINT44 (0x00001000uL) -#define INTC_ICDICPR14_TINT45 (0x00002000uL) -#define INTC_ICDICPR14_TINT46 (0x00004000uL) -#define INTC_ICDICPR14_TINT47 (0x00008000uL) -#define INTC_ICDICPR14_TINT48 (0x00010000uL) -#define INTC_ICDICPR14_TINT49 (0x00020000uL) -#define INTC_ICDICPR14_TINT50 (0x00040000uL) -#define INTC_ICDICPR14_TINT51 (0x00080000uL) -#define INTC_ICDICPR14_TINT52 (0x00100000uL) -#define INTC_ICDICPR14_TINT53 (0x00200000uL) -#define INTC_ICDICPR14_TINT54 (0x00400000uL) -#define INTC_ICDICPR14_TINT55 (0x00800000uL) -#define INTC_ICDICPR14_TINT56 (0x01000000uL) -#define INTC_ICDICPR14_TINT57 (0x02000000uL) -#define INTC_ICDICPR14_TINT58 (0x04000000uL) -#define INTC_ICDICPR14_TINT59 (0x08000000uL) -#define INTC_ICDICPR14_TINT60 (0x10000000uL) -#define INTC_ICDICPR14_TINT61 (0x20000000uL) -#define INTC_ICDICPR14_TINT62 (0x40000000uL) -#define INTC_ICDICPR14_TINT63 (0x80000000uL) - -#define INTC_ICDICPR15_TINT64 (0x00000001uL) -#define INTC_ICDICPR15_TINT65 (0x00000002uL) -#define INTC_ICDICPR15_TINT66 (0x00000004uL) -#define INTC_ICDICPR15_TINT67 (0x00000008uL) -#define INTC_ICDICPR15_TINT68 (0x00000010uL) -#define INTC_ICDICPR15_TINT69 (0x00000020uL) -#define INTC_ICDICPR15_TINT70 (0x00000040uL) -#define INTC_ICDICPR15_TINT71 (0x00000080uL) -#define INTC_ICDICPR15_TINT72 (0x00000100uL) -#define INTC_ICDICPR15_TINT73 (0x00000200uL) -#define INTC_ICDICPR15_TINT74 (0x00000400uL) -#define INTC_ICDICPR15_TINT75 (0x00000800uL) -#define INTC_ICDICPR15_TINT76 (0x00001000uL) -#define INTC_ICDICPR15_TINT77 (0x00002000uL) -#define INTC_ICDICPR15_TINT78 (0x00004000uL) -#define INTC_ICDICPR15_TINT79 (0x00008000uL) -#define INTC_ICDICPR15_TINT80 (0x00010000uL) -#define INTC_ICDICPR15_TINT81 (0x00020000uL) -#define INTC_ICDICPR15_TINT82 (0x00040000uL) -#define INTC_ICDICPR15_TINT83 (0x00080000uL) -#define INTC_ICDICPR15_TINT84 (0x00100000uL) -#define INTC_ICDICPR15_TINT85 (0x00200000uL) -#define INTC_ICDICPR15_TINT86 (0x00400000uL) -#define INTC_ICDICPR15_TINT87 (0x00800000uL) -#define INTC_ICDICPR15_TINT88 (0x01000000uL) -#define INTC_ICDICPR15_TINT89 (0x02000000uL) -#define INTC_ICDICPR15_TINT90 (0x04000000uL) -#define INTC_ICDICPR15_TINT91 (0x08000000uL) -#define INTC_ICDICPR15_TINT92 (0x10000000uL) -#define INTC_ICDICPR15_TINT93 (0x20000000uL) -#define INTC_ICDICPR15_TINT94 (0x40000000uL) -#define INTC_ICDICPR15_TINT95 (0x80000000uL) - -#define INTC_ICDICPR16_TINT96 (0x00000001uL) -#define INTC_ICDICPR16_TINT97 (0x00000002uL) -#define INTC_ICDICPR16_TINT98 (0x00000004uL) -#define INTC_ICDICPR16_TINT99 (0x00000008uL) -#define INTC_ICDICPR16_TINT100 (0x00000010uL) -#define INTC_ICDICPR16_TINT101 (0x00000020uL) -#define INTC_ICDICPR16_TINT102 (0x00000040uL) -#define INTC_ICDICPR16_TINT103 (0x00000080uL) -#define INTC_ICDICPR16_TINT104 (0x00000100uL) -#define INTC_ICDICPR16_TINT105 (0x00000200uL) -#define INTC_ICDICPR16_TINT106 (0x00000400uL) -#define INTC_ICDICPR16_TINT107 (0x00000800uL) -#define INTC_ICDICPR16_TINT108 (0x00001000uL) -#define INTC_ICDICPR16_TINT109 (0x00002000uL) -#define INTC_ICDICPR16_TINT110 (0x00004000uL) -#define INTC_ICDICPR16_TINT111 (0x00008000uL) -#define INTC_ICDICPR16_TINT112 (0x00010000uL) -#define INTC_ICDICPR16_TINT113 (0x00020000uL) -#define INTC_ICDICPR16_TINT114 (0x00040000uL) -#define INTC_ICDICPR16_TINT115 (0x00080000uL) -#define INTC_ICDICPR16_TINT116 (0x00100000uL) -#define INTC_ICDICPR16_TINT117 (0x00200000uL) -#define INTC_ICDICPR16_TINT118 (0x00400000uL) -#define INTC_ICDICPR16_TINT119 (0x00800000uL) -#define INTC_ICDICPR16_TINT120 (0x01000000uL) -#define INTC_ICDICPR16_TINT121 (0x02000000uL) -#define INTC_ICDICPR16_TINT122 (0x04000000uL) -#define INTC_ICDICPR16_TINT123 (0x08000000uL) -#define INTC_ICDICPR16_TINT124 (0x10000000uL) -#define INTC_ICDICPR16_TINT125 (0x20000000uL) -#define INTC_ICDICPR16_TINT126 (0x40000000uL) -#define INTC_ICDICPR16_TINT127 (0x80000000uL) - -#define INTC_ICDICPR17_TINT128 (0x00000001uL) -#define INTC_ICDICPR17_TINT129 (0x00000002uL) -#define INTC_ICDICPR17_TINT130 (0x00000004uL) -#define INTC_ICDICPR17_TINT131 (0x00000008uL) -#define INTC_ICDICPR17_TINT132 (0x00000010uL) -#define INTC_ICDICPR17_TINT133 (0x00000020uL) -#define INTC_ICDICPR17_TINT134 (0x00000040uL) -#define INTC_ICDICPR17_TINT135 (0x00000080uL) -#define INTC_ICDICPR17_TINT136 (0x00000100uL) -#define INTC_ICDICPR17_TINT137 (0x00000200uL) -#define INTC_ICDICPR17_TINT138 (0x00000400uL) -#define INTC_ICDICPR17_TINT139 (0x00000800uL) -#define INTC_ICDICPR17_TINT140 (0x00001000uL) -#define INTC_ICDICPR17_TINT141 (0x00002000uL) -#define INTC_ICDICPR17_TINT142 (0x00004000uL) -#define INTC_ICDICPR17_TINT143 (0x00008000uL) -#define INTC_ICDICPR17_TINT144 (0x00010000uL) -#define INTC_ICDICPR17_TINT145 (0x00020000uL) -#define INTC_ICDICPR17_TINT146 (0x00040000uL) -#define INTC_ICDICPR17_TINT147 (0x00080000uL) -#define INTC_ICDICPR17_TINT148 (0x00100000uL) -#define INTC_ICDICPR17_TINT149 (0x00200000uL) -#define INTC_ICDICPR17_TINT150 (0x00400000uL) -#define INTC_ICDICPR17_TINT151 (0x00800000uL) -#define INTC_ICDICPR17_TINT152 (0x01000000uL) -#define INTC_ICDICPR17_TINT153 (0x02000000uL) -#define INTC_ICDICPR17_TINT154 (0x04000000uL) -#define INTC_ICDICPR17_TINT155 (0x08000000uL) -#define INTC_ICDICPR17_TINT156 (0x10000000uL) -#define INTC_ICDICPR17_TINT157 (0x20000000uL) -#define INTC_ICDICPR17_TINT158 (0x40000000uL) -#define INTC_ICDICPR17_TINT159 (0x80000000uL) - -#define INTC_ICDICPR18_TINT160 (0x00000001uL) -#define INTC_ICDICPR18_TINT161 (0x00000002uL) -#define INTC_ICDICPR18_TINT162 (0x00000004uL) -#define INTC_ICDICPR18_TINT163 (0x00000008uL) -#define INTC_ICDICPR18_TINT164 (0x00000010uL) -#define INTC_ICDICPR18_TINT165 (0x00000020uL) -#define INTC_ICDICPR18_TINT166 (0x00000040uL) -#define INTC_ICDICPR18_TINT167 (0x00000080uL) -#define INTC_ICDICPR18_TINT168 (0x00000100uL) -#define INTC_ICDICPR18_TINT169 (0x00000200uL) -#define INTC_ICDICPR18_TINT170 (0x00000400uL) - -#define INTC_ICDABR0_SW0 (0x00000001uL) -#define INTC_ICDABR0_SW1 (0x00000002uL) -#define INTC_ICDABR0_SW2 (0x00000004uL) -#define INTC_ICDABR0_SW3 (0x00000008uL) -#define INTC_ICDABR0_SW4 (0x00000010uL) -#define INTC_ICDABR0_SW5 (0x00000020uL) -#define INTC_ICDABR0_SW6 (0x00000040uL) -#define INTC_ICDABR0_SW7 (0x00000080uL) -#define INTC_ICDABR0_SW8 (0x00000100uL) -#define INTC_ICDABR0_SW9 (0x00000200uL) -#define INTC_ICDABR0_SW10 (0x00000400uL) -#define INTC_ICDABR0_SW11 (0x00000800uL) -#define INTC_ICDABR0_SW12 (0x00001000uL) -#define INTC_ICDABR0_SW13 (0x00002000uL) -#define INTC_ICDABR0_SW14 (0x00004000uL) -#define INTC_ICDABR0_SW15 (0x00008000uL) -#define INTC_ICDABR0_PMUIRQ0 (0x00010000uL) -#define INTC_ICDABR0_COMMRX0 (0x00020000uL) -#define INTC_ICDABR0_COMMTX0 (0x00040000uL) -#define INTC_ICDABR0_CTIIRQ0 (0x00080000uL) - -#define INTC_ICDABR1_IRQ0 (0x00000001uL) -#define INTC_ICDABR1_IRQ1 (0x00000002uL) -#define INTC_ICDABR1_IRQ2 (0x00000004uL) -#define INTC_ICDABR1_IRQ3 (0x00000008uL) -#define INTC_ICDABR1_IRQ4 (0x00000010uL) -#define INTC_ICDABR1_IRQ5 (0x00000020uL) -#define INTC_ICDABR1_IRQ6 (0x00000040uL) -#define INTC_ICDABR1_IRQ7 (0x00000080uL) -#define INTC_ICDABR1_PL310ERR (0x00000100uL) -#define INTC_ICDABR1_DMAINT0 (0x00000200uL) -#define INTC_ICDABR1_DMAINT1 (0x00000400uL) -#define INTC_ICDABR1_DMAINT2 (0x00000800uL) -#define INTC_ICDABR1_DMAINT3 (0x00001000uL) -#define INTC_ICDABR1_DMAINT4 (0x00002000uL) -#define INTC_ICDABR1_DMAINT5 (0x00004000uL) -#define INTC_ICDABR1_DMAINT6 (0x00008000uL) -#define INTC_ICDABR1_DMAINT7 (0x00010000uL) -#define INTC_ICDABR1_DMAINT8 (0x00020000uL) -#define INTC_ICDABR1_DMAINT9 (0x00040000uL) -#define INTC_ICDABR1_DMAINT10 (0x00080000uL) -#define INTC_ICDABR1_DMAINT11 (0x00100000uL) -#define INTC_ICDABR1_DMAINT12 (0x00200000uL) -#define INTC_ICDABR1_DMAINT13 (0x00400000uL) -#define INTC_ICDABR1_DMAINT14 (0x00800000uL) -#define INTC_ICDABR1_DMAINT15 (0x01000000uL) -#define INTC_ICDABR1_DMAERR (0x02000000uL) - -#define INTC_ICDABR2_USBI0 (0x00000200uL) -#define INTC_ICDABR2_USBI1 (0x00000400uL) -#define INTC_ICDABR2_S0_VI_VSYNC0 (0x00000800uL) -#define INTC_ICDABR2_S0_LO_VSYNC0 (0x00001000uL) -#define INTC_ICDABR2_S0_VSYNCERR0 (0x00002000uL) -#define INTC_ICDABR2_GR3_VLINE0 (0x00004000uL) -#define INTC_ICDABR2_S0_VFIELD0 (0x00008000uL) -#define INTC_ICDABR2_IV1_VBUFERR0 (0x00010000uL) -#define INTC_ICDABR2_IV3_VBUFERR0 (0x00020000uL) -#define INTC_ICDABR2_IV5_VBUFERR0 (0x00040000uL) -#define INTC_ICDABR2_IV6_VBUFERR0 (0x00080000uL) -#define INTC_ICDABR2_S0_WLINE0 (0x00100000uL) -#define INTC_ICDABR2_S1_VI_VSYNC0 (0x00200000uL) -#define INTC_ICDABR2_S1_LO_VSYNC0 (0x00400000uL) -#define INTC_ICDABR2_S1_VSYNCERR0 (0x00800000uL) -#define INTC_ICDABR2_S1_VFIELD0 (0x01000000uL) -#define INTC_ICDABR2_IV2_VBUFERR0 (0x02000000uL) -#define INTC_ICDABR2_IV4_VBUFERR0 (0x04000000uL) -#define INTC_ICDABR2_S1_WLINE0 (0x08000000uL) -#define INTC_ICDABR2_OIR_VI_VSYNC0 (0x10000000uL) -#define INTC_ICDABR2_OIR_LO_VSYNC0 (0x20000000uL) -#define INTC_ICDABR2_OIR_VSYNCERR0 (0x40000000uL) -#define INTC_ICDABR2_OIR_VFIELD0 (0x80000000uL) - -#define INTC_ICDABR3_IV7_VBUFERR0 (0x00000001uL) -#define INTC_ICDABR3_IV8_VBUFERR0 (0x00000002uL) -#define INTC_ICDABR3_S0_VI_VSYNC1 (0x00000008uL) -#define INTC_ICDABR3_S0_LO_VSYNC1 (0x00000010uL) -#define INTC_ICDABR3_S0_VSYNCERR1 (0x00000020uL) -#define INTC_ICDABR3_GR3_VLINE1 (0x00000040uL) -#define INTC_ICDABR3_S0_VFIELD1 (0x00000080uL) -#define INTC_ICDABR3_IV1_VBUFERR1 (0x00000100uL) -#define INTC_ICDABR3_IV3_VBUFERR1 (0x00000200uL) -#define INTC_ICDABR3_IV5_VBUFERR1 (0x00000400uL) -#define INTC_ICDABR3_IV6_VBUFERR1 (0x00000800uL) -#define INTC_ICDABR3_S0_WLINE1 (0x00001000uL) -#define INTC_ICDABR3_S1_VI_VSYNC1 (0x00002000uL) -#define INTC_ICDABR3_S1_LO_VSYNC1 (0x00004000uL) -#define INTC_ICDABR3_S1_VSYNCERR1 (0x00008000uL) -#define INTC_ICDABR3_S1_VFIELD1 (0x00010000uL) -#define INTC_ICDABR3_IV2_VBUFERR1 (0x00020000uL) -#define INTC_ICDABR3_IV4_VBUFERR1 (0x00040000uL) -#define INTC_ICDABR3_S1_WLINE1 (0x00080000uL) -#define INTC_ICDABR3_OIR_VI_VSYNC1 (0x00100000uL) -#define INTC_ICDABR3_OIR_LO_VSYNC1 (0x00200000uL) -#define INTC_ICDABR3_OIR_VLINE1 (0x00400000uL) -#define INTC_ICDABR3_OIR_VFIELD1 (0x00800000uL) -#define INTC_ICDABR3_IV7_VBUFERR1 (0x01000000uL) -#define INTC_ICDABR3_IV8_VBUFERR1 (0x02000000uL) -#define INTC_ICDABR3_IMRDI (0x08000000uL) -#define INTC_ICDABR3_IMR2I0 (0x10000000uL) -#define INTC_ICDABR3_IMR2I1 (0x20000000uL) -#define INTC_ICDABR3_JEDI (0x40000000uL) -#define INTC_ICDABR3_JDTI (0x80000000uL) - -#define INTC_ICDABR4_CMP0 (0x00000001uL) -#define INTC_ICDABR4_CMP1 (0x00000002uL) -#define INTC_ICDABR4_INT0 (0x00000004uL) -#define INTC_ICDABR4_INT1 (0x00000008uL) -#define INTC_ICDABR4_INT2 (0x00000010uL) -#define INTC_ICDABR4_INT3 (0x00000020uL) -#define INTC_ICDABR4_OSTM0TINT (0x00000040uL) -#define INTC_ICDABR4_OSTM1TINT (0x00000080uL) -#define INTC_ICDABR4_CMI (0x00000100uL) -#define INTC_ICDABR4_WTOUT (0x00000200uL) -#define INTC_ICDABR4_ITI (0x00000400uL) -#define INTC_ICDABR4_TGI0A (0x00000800uL) -#define INTC_ICDABR4_TGI0B (0x00001000uL) -#define INTC_ICDABR4_TGI0C (0x00002000uL) -#define INTC_ICDABR4_TGI0D (0x00004000uL) -#define INTC_ICDABR4_TGI0V (0x00008000uL) -#define INTC_ICDABR4_TGI0E (0x00010000uL) -#define INTC_ICDABR4_TGI0F (0x00020000uL) -#define INTC_ICDABR4_TGI1A (0x00040000uL) -#define INTC_ICDABR4_TGI1B (0x00080000uL) -#define INTC_ICDABR4_TGI1V (0x00100000uL) -#define INTC_ICDABR4_TGI1U (0x00200000uL) -#define INTC_ICDABR4_TGI2A (0x00400000uL) -#define INTC_ICDABR4_TGI2B (0x00800000uL) -#define INTC_ICDABR4_TGI2V (0x01000000uL) -#define INTC_ICDABR4_TGI2U (0x02000000uL) -#define INTC_ICDABR4_TGI3A (0x04000000uL) -#define INTC_ICDABR4_TGI3B (0x08000000uL) -#define INTC_ICDABR4_TGI3C (0x10000000uL) -#define INTC_ICDABR4_TGI3D (0x20000000uL) -#define INTC_ICDABR4_TGI3V (0x40000000uL) -#define INTC_ICDABR4_TGI4A (0x80000000uL) - -#define INTC_ICDABR5_TGI4B (0x00000001uL) -#define INTC_ICDABR5_TGI4C (0x00000002uL) -#define INTC_ICDABR5_TGI4D (0x00000004uL) -#define INTC_ICDABR5_TGI4V (0x00000008uL) -#define INTC_ICDABR5_CMI1 (0x00000010uL) -#define INTC_ICDABR5_CMI2 (0x00000020uL) -#define INTC_ICDABR5_SGDEI0 (0x00000040uL) -#define INTC_ICDABR5_SGDEI1 (0x00000080uL) -#define INTC_ICDABR5_SGDEI2 (0x00000100uL) -#define INTC_ICDABR5_SGDEI3 (0x00000200uL) -#define INTC_ICDABR5_ADI (0x00000400uL) -#define INTC_ICDABR5_LMTI (0x00000800uL) -#define INTC_ICDABR5_SSII0 (0x00001000uL) -#define INTC_ICDABR5_SSIRXI0 (0x00002000uL) -#define INTC_ICDABR5_SSITXI0 (0x00004000uL) -#define INTC_ICDABR5_SSII1 (0x00008000uL) -#define INTC_ICDABR5_SSIRXI1 (0x00010000uL) -#define INTC_ICDABR5_SSITXI1 (0x00020000uL) -#define INTC_ICDABR5_SSII2 (0x00040000uL) -#define INTC_ICDABR5_SSIRTI2 (0x00080000uL) -#define INTC_ICDABR5_SSII3 (0x00100000uL) -#define INTC_ICDABR5_SSIRXI3 (0x00200000uL) -#define INTC_ICDABR5_SSITXI3 (0x00400000uL) -#define INTC_ICDABR5_SSII4 (0x00800000uL) -#define INTC_ICDABR5_SSIRTI4 (0x01000000uL) -#define INTC_ICDABR5_SSII5 (0x02000000uL) -#define INTC_ICDABR5_SSIRXI5 (0x04000000uL) -#define INTC_ICDABR5_SSITXI5 (0x08000000uL) -#define INTC_ICDABR5_SPDIFI (0x10000000uL) -#define INTC_ICDABR5_INTIICTEI0 (0x20000000uL) -#define INTC_ICDABR5_INTIICRI0 (0x40000000uL) -#define INTC_ICDABR5_INTIICTI0 (0x80000000uL) - -#define INTC_ICDABR6_INTIICSPI0 (0x00000001uL) -#define INTC_ICDABR6_INTIICSTI0 (0x00000002uL) -#define INTC_ICDABR6_INTIICNAKI0 (0x00000004uL) -#define INTC_ICDABR6_INTIICALI0 (0x00000008uL) -#define INTC_ICDABR6_INTIICTMOI0 (0x00000010uL) -#define INTC_ICDABR6_INTIICTEI1 (0x00000020uL) -#define INTC_ICDABR6_INTIICRI1 (0x00000040uL) -#define INTC_ICDABR6_INTIICTI1 (0x00000080uL) -#define INTC_ICDABR6_INTIICSPI1 (0x00000100uL) -#define INTC_ICDABR6_INTIICSTI1 (0x00000200uL) -#define INTC_ICDABR6_INTIICNAKI1 (0x00000400uL) -#define INTC_ICDABR6_INTIICALI1 (0x00000800uL) -#define INTC_ICDABR6_INTIICTMOI1 (0x00001000uL) -#define INTC_ICDABR6_INTIICTEI2 (0x00002000uL) -#define INTC_ICDABR6_INTIICRI2 (0x00004000uL) -#define INTC_ICDABR6_INTIICTI2 (0x00008000uL) -#define INTC_ICDABR6_INTIICSPI2 (0x00010000uL) -#define INTC_ICDABR6_INTIICSTI2 (0x00020000uL) -#define INTC_ICDABR6_INTIICNAKI2 (0x00040000uL) -#define INTC_ICDABR6_INTIICALI2 (0x00080000uL) -#define INTC_ICDABR6_INTIICTMOI2 (0x00100000uL) -#define INTC_ICDABR6_INTIICTEI3 (0x00200000uL) -#define INTC_ICDABR6_INTIICRI3 (0x00400000uL) -#define INTC_ICDABR6_INTIICTI3 (0x00800000uL) -#define INTC_ICDABR6_INTIICSPI3 (0x01000000uL) -#define INTC_ICDABR6_INTIICSTI3 (0x02000000uL) -#define INTC_ICDABR6_INTIICNAKI3 (0x04000000uL) -#define INTC_ICDABR6_INTIICALI3 (0x08000000uL) -#define INTC_ICDABR6_INTIICTMOI3 (0x10000000uL) -#define INTC_ICDABR6_BRI0 (0x20000000uL) -#define INTC_ICDABR6_ERI0 (0x40000000uL) -#define INTC_ICDABR6_RXI0 (0x80000000uL) - -#define INTC_ICDABR7_TXI0 (0x00000001uL) -#define INTC_ICDABR7_BRI1 (0x00000002uL) -#define INTC_ICDABR7_ERI1 (0x00000004uL) -#define INTC_ICDABR7_RXI1 (0x00000008uL) -#define INTC_ICDABR7_TXI1 (0x00000010uL) -#define INTC_ICDABR7_BRI2 (0x00000020uL) -#define INTC_ICDABR7_ERI2 (0x00000040uL) -#define INTC_ICDABR7_RXI2 (0x00000080uL) -#define INTC_ICDABR7_TXI2 (0x00000100uL) -#define INTC_ICDABR7_BRI3 (0x00000200uL) -#define INTC_ICDABR7_ERI3 (0x00000400uL) -#define INTC_ICDABR7_RXI3 (0x00000800uL) -#define INTC_ICDABR7_TXI3 (0x00001000uL) -#define INTC_ICDABR7_BRI4 (0x00002000uL) -#define INTC_ICDABR7_ERI4 (0x00004000uL) -#define INTC_ICDABR7_RXI4 (0x00008000uL) -#define INTC_ICDABR7_TXI4 (0x00010000uL) -#define INTC_ICDABR7_BRI5 (0x00020000uL) -#define INTC_ICDABR7_ERI5 (0x00040000uL) -#define INTC_ICDABR7_RXI5 (0x00080000uL) -#define INTC_ICDABR7_TXI5 (0x00100000uL) -#define INTC_ICDABR7_BRI6 (0x00200000uL) -#define INTC_ICDABR7_ERI6 (0x00400000uL) -#define INTC_ICDABR7_RXI6 (0x00800000uL) -#define INTC_ICDABR7_TXI6 (0x01000000uL) -#define INTC_ICDABR7_BRI7 (0x02000000uL) -#define INTC_ICDABR7_ERI7 (0x04000000uL) -#define INTC_ICDABR7_RXI7 (0x08000000uL) -#define INTC_ICDABR7_TXI7 (0x10000000uL) -#define INTC_ICDABR7_INTRCANGERR (0x20000000uL) -#define INTC_ICDABR7_INTRCANGRECC (0x40000000uL) -#define INTC_ICDABR7_INTRCAN0REC (0x80000000uL) - -#define INTC_ICDABR8_INTRCAN0ERR (0x00000001uL) -#define INTC_ICDABR8_INTRCAN0TRX (0x00000002uL) -#define INTC_ICDABR8_INTRCAN1REC (0x00000004uL) -#define INTC_ICDABR8_INTRCAN1ERR (0x00000008uL) -#define INTC_ICDABR8_INTRCAN1TRX (0x00000010uL) -#define INTC_ICDABR8_INTRCAN2REC (0x00000020uL) -#define INTC_ICDABR8_INTRCAN2ERR (0x00000040uL) -#define INTC_ICDABR8_INTRCAN2TRX (0x00000080uL) -#define INTC_ICDABR8_INTRCAN3REC (0x00000100uL) -#define INTC_ICDABR8_INTRCAN3ERR (0x00000200uL) -#define INTC_ICDABR8_INTRCAN3TRX (0x00000400uL) -#define INTC_ICDABR8_INTRCAN4REC (0x00000800uL) -#define INTC_ICDABR8_INTRCAN4ERR (0x00001000uL) -#define INTC_ICDABR8_INTRCAN4TRX (0x00002000uL) -#define INTC_ICDABR8_SPEI0 (0x00004000uL) -#define INTC_ICDABR8_SPRI0 (0x00008000uL) -#define INTC_ICDABR8_SPTI0 (0x00010000uL) -#define INTC_ICDABR8_SPEI1 (0x00020000uL) -#define INTC_ICDABR8_SPRI1 (0x00040000uL) -#define INTC_ICDABR8_SPTI1 (0x00080000uL) -#define INTC_ICDABR8_SPEI2 (0x00100000uL) -#define INTC_ICDABR8_SPRI2 (0x00200000uL) -#define INTC_ICDABR8_SPTI2 (0x00400000uL) -#define INTC_ICDABR8_SPEI3 (0x00800000uL) -#define INTC_ICDABR8_SPRI3 (0x01000000uL) -#define INTC_ICDABR8_SPTI3 (0x02000000uL) -#define INTC_ICDABR8_SPEI4 (0x04000000uL) -#define INTC_ICDABR8_SPRI4 (0x08000000uL) -#define INTC_ICDABR8_SPTI4 (0x10000000uL) -#define INTC_ICDABR8_IEBBTD (0x20000000uL) -#define INTC_ICDABR8_IEBBTERR (0x40000000uL) -#define INTC_ICDABR8_IEBBTSTA (0x80000000uL) - -#define INTC_ICDABR9_IEBBTV (0x00000001uL) -#define INTC_ICDABR9_ISY (0x00000002uL) -#define INTC_ICDABR9_IERR (0x00000004uL) -#define INTC_ICDABR9_ITARG (0x00000008uL) -#define INTC_ICDABR9_ISEC (0x00000010uL) -#define INTC_ICDABR9_IBUF (0x00000020uL) -#define INTC_ICDABR9_IREADY (0x00000040uL) -#define INTC_ICDABR9_FLSTE (0x00000080uL) -#define INTC_ICDABR9_FLTENDI (0x00000100uL) -#define INTC_ICDABR9_FLTREQ0I (0x00000200uL) -#define INTC_ICDABR9_FLTREQ1I (0x00000400uL) -#define INTC_ICDABR9_MMC0 (0x00000800uL) -#define INTC_ICDABR9_MMC1 (0x00001000uL) -#define INTC_ICDABR9_MMC2 (0x00002000uL) -#define INTC_ICDABR9_SDHI0_3 (0x00004000uL) -#define INTC_ICDABR9_SDHI0_0 (0x00008000uL) -#define INTC_ICDABR9_SDHI0_1 (0x00010000uL) -#define INTC_ICDABR9_SDHI1_3 (0x00020000uL) -#define INTC_ICDABR9_SDHI1_0 (0x00040000uL) -#define INTC_ICDABR9_SDHI1_1 (0x00080000uL) -#define INTC_ICDABR9_ARM (0x00100000uL) -#define INTC_ICDABR9_PRD (0x00200000uL) -#define INTC_ICDABR9_CUP (0x00400000uL) -#define INTC_ICDABR9_SCUAI0 (0x00800000uL) -#define INTC_ICDABR9_SCUAI1 (0x01000000uL) -#define INTC_ICDABR9_SCUFDI0 (0x02000000uL) -#define INTC_ICDABR9_SCUFDI1 (0x04000000uL) -#define INTC_ICDABR9_SCUFDI2 (0x08000000uL) -#define INTC_ICDABR9_SCUFDI3 (0x10000000uL) -#define INTC_ICDABR9_SCUFUI0 (0x20000000uL) -#define INTC_ICDABR9_SCUFUI1 (0x40000000uL) -#define INTC_ICDABR9_SCUFUI2 (0x80000000uL) - -#define INTC_ICDABR10_SCUFUI3 (0x00000001uL) -#define INTC_ICDABR10_SCUDVI0 (0x00000002uL) -#define INTC_ICDABR10_SCUDVI1 (0x00000004uL) -#define INTC_ICDABR10_SCUDVI2 (0x00000008uL) -#define INTC_ICDABR10_SCUDVI3 (0x00000010uL) -#define INTC_ICDABR10_MLB_CINT (0x00000020uL) -#define INTC_ICDABR10_MLB_SINT (0x00000040uL) -#define INTC_ICDABR10_DRC0 (0x00000080uL) -#define INTC_ICDABR10_DRC1 (0x00000100uL) -#define INTC_ICDABR10_LINI0_INT_T (0x00000800uL) -#define INTC_ICDABR10_LINI0_INT_R (0x00001000uL) -#define INTC_ICDABR10_LINI0_INT_S (0x00002000uL) -#define INTC_ICDABR10_LINI0_INT_M (0x00004000uL) -#define INTC_ICDABR10_LINI1_INT_T (0x00008000uL) -#define INTC_ICDABR10_LINI1_INT_R (0x00010000uL) -#define INTC_ICDABR10_LINI1_INT_S (0x00020000uL) -#define INTC_ICDABR10_LINI1_INT_M (0x00040000uL) -#define INTC_ICDABR10_ERI0 (0x08000000uL) -#define INTC_ICDABR10_RXI0 (0x10000000uL) -#define INTC_ICDABR10_TXI0 (0x20000000uL) -#define INTC_ICDABR10_TEI0 (0x40000000uL) -#define INTC_ICDABR10_ERI1 (0x80000000uL) - -#define INTC_ICDABR11_RXI1 (0x00000001uL) -#define INTC_ICDABR11_TXI1 (0x00000002uL) -#define INTC_ICDABR11_TEI1 (0x00000004uL) -#define INTC_ICDABR11_AVBI_DATA (0x00000008uL) -#define INTC_ICDABR11_AVBI_ERROR (0x00000010uL) -#define INTC_ICDABR11_AVBI_MANAGE (0x00000020uL) -#define INTC_ICDABR11_AVBI_MAC (0x00000040uL) -#define INTC_ICDABR11_ETHERI (0x00000080uL) -#define INTC_ICDABR11_CEUI (0x00001000uL) -#define INTC_ICDABR11_H2XMLB_ERRINT (0x20000000uL) -#define INTC_ICDABR11_H2XIC1_ERRINT (0x40000000uL) -#define INTC_ICDABR11_X2HPERI1_ERRINT (0x80000000uL) - -#define INTC_ICDABR12_X2HPERI2_ERRINT (0x00000001uL) -#define INTC_ICDABR12_X2HPERI34_ERRINT (0x00000002uL) -#define INTC_ICDABR12_X2HPERI5_ERRINT (0x00000004uL) -#define INTC_ICDABR12_X2HPERI67_ERRINT (0x00000008uL) -#define INTC_ICDABR12_X2HDBGR_ERRINT (0x00000010uL) -#define INTC_ICDABR12_X2HBSC_ERRINT (0x00000020uL) -#define INTC_ICDABR12_X2HSPI1_ERRINT (0x00000040uL) -#define INTC_ICDABR12_X2HSPI2_ERRINT (0x00000080uL) -#define INTC_ICDABR12_PRRI (0x00000100uL) -#define INTC_ICDABR12_IFEI0 (0x00000200uL) -#define INTC_ICDABR12_OFFI0 (0x00000400uL) -#define INTC_ICDABR12_PFVEI0 (0x00000800uL) -#define INTC_ICDABR12_IFEI1 (0x00001000uL) -#define INTC_ICDABR12_OFFI1 (0x00002000uL) -#define INTC_ICDABR12_PFVEI1 (0x00004000uL) - -#define INTC_ICDABR13_TINT0 (0x00000001uL) -#define INTC_ICDABR13_TINT1 (0x00000002uL) -#define INTC_ICDABR13_TINT2 (0x00000004uL) -#define INTC_ICDABR13_TINT3 (0x00000008uL) -#define INTC_ICDABR13_TINT4 (0x00000010uL) -#define INTC_ICDABR13_TINT5 (0x00000020uL) -#define INTC_ICDABR13_TINT6 (0x00000040uL) -#define INTC_ICDABR13_TINT7 (0x00000080uL) -#define INTC_ICDABR13_TINT8 (0x00000100uL) -#define INTC_ICDABR13_TINT9 (0x00000200uL) -#define INTC_ICDABR13_TINT10 (0x00000400uL) -#define INTC_ICDABR13_TINT11 (0x00000800uL) -#define INTC_ICDABR13_TINT12 (0x00001000uL) -#define INTC_ICDABR13_TINT13 (0x00002000uL) -#define INTC_ICDABR13_TINT14 (0x00004000uL) -#define INTC_ICDABR13_TINT15 (0x00008000uL) -#define INTC_ICDABR13_TINT16 (0x00010000uL) -#define INTC_ICDABR13_TINT17 (0x00020000uL) -#define INTC_ICDABR13_TINT18 (0x00040000uL) -#define INTC_ICDABR13_TINT19 (0x00080000uL) -#define INTC_ICDABR13_TINT20 (0x00100000uL) -#define INTC_ICDABR13_TINT21 (0x00200000uL) -#define INTC_ICDABR13_TINT22 (0x00400000uL) -#define INTC_ICDABR13_TINT23 (0x00800000uL) -#define INTC_ICDABR13_TINT24 (0x01000000uL) -#define INTC_ICDABR13_TINT25 (0x02000000uL) -#define INTC_ICDABR13_TINT26 (0x04000000uL) -#define INTC_ICDABR13_TINT27 (0x08000000uL) -#define INTC_ICDABR13_TINT28 (0x10000000uL) -#define INTC_ICDABR13_TINT29 (0x20000000uL) -#define INTC_ICDABR13_TINT30 (0x40000000uL) -#define INTC_ICDABR13_TINT31 (0x80000000uL) - -#define INTC_ICDABR14_TINT32 (0x00000001uL) -#define INTC_ICDABR14_TINT33 (0x00000002uL) -#define INTC_ICDABR14_TINT34 (0x00000004uL) -#define INTC_ICDABR14_TINT35 (0x00000008uL) -#define INTC_ICDABR14_TINT36 (0x00000010uL) -#define INTC_ICDABR14_TINT37 (0x00000020uL) -#define INTC_ICDABR14_TINT38 (0x00000040uL) -#define INTC_ICDABR14_TINT39 (0x00000080uL) -#define INTC_ICDABR14_TINT40 (0x00000100uL) -#define INTC_ICDABR14_TINT41 (0x00000200uL) -#define INTC_ICDABR14_TINT42 (0x00000400uL) -#define INTC_ICDABR14_TINT43 (0x00000800uL) -#define INTC_ICDABR14_TINT44 (0x00001000uL) -#define INTC_ICDABR14_TINT45 (0x00002000uL) -#define INTC_ICDABR14_TINT46 (0x00004000uL) -#define INTC_ICDABR14_TINT47 (0x00008000uL) -#define INTC_ICDABR14_TINT48 (0x00010000uL) -#define INTC_ICDABR14_TINT49 (0x00020000uL) -#define INTC_ICDABR14_TINT50 (0x00040000uL) -#define INTC_ICDABR14_TINT51 (0x00080000uL) -#define INTC_ICDABR14_TINT52 (0x00100000uL) -#define INTC_ICDABR14_TINT53 (0x00200000uL) -#define INTC_ICDABR14_TINT54 (0x00400000uL) -#define INTC_ICDABR14_TINT55 (0x00800000uL) -#define INTC_ICDABR14_TINT56 (0x01000000uL) -#define INTC_ICDABR14_TINT57 (0x02000000uL) -#define INTC_ICDABR14_TINT58 (0x04000000uL) -#define INTC_ICDABR14_TINT59 (0x08000000uL) -#define INTC_ICDABR14_TINT60 (0x10000000uL) -#define INTC_ICDABR14_TINT61 (0x20000000uL) -#define INTC_ICDABR14_TINT62 (0x40000000uL) -#define INTC_ICDABR14_TINT63 (0x80000000uL) - -#define INTC_ICDABR15_TINT64 (0x00000001uL) -#define INTC_ICDABR15_TINT65 (0x00000002uL) -#define INTC_ICDABR15_TINT66 (0x00000004uL) -#define INTC_ICDABR15_TINT67 (0x00000008uL) -#define INTC_ICDABR15_TINT68 (0x00000010uL) -#define INTC_ICDABR15_TINT69 (0x00000020uL) -#define INTC_ICDABR15_TINT70 (0x00000040uL) -#define INTC_ICDABR15_TINT71 (0x00000080uL) -#define INTC_ICDABR15_TINT72 (0x00000100uL) -#define INTC_ICDABR15_TINT73 (0x00000200uL) -#define INTC_ICDABR15_TINT74 (0x00000400uL) -#define INTC_ICDABR15_TINT75 (0x00000800uL) -#define INTC_ICDABR15_TINT76 (0x00001000uL) -#define INTC_ICDABR15_TINT77 (0x00002000uL) -#define INTC_ICDABR15_TINT78 (0x00004000uL) -#define INTC_ICDABR15_TINT79 (0x00008000uL) -#define INTC_ICDABR15_TINT80 (0x00010000uL) -#define INTC_ICDABR15_TINT81 (0x00020000uL) -#define INTC_ICDABR15_TINT82 (0x00040000uL) -#define INTC_ICDABR15_TINT83 (0x00080000uL) -#define INTC_ICDABR15_TINT84 (0x00100000uL) -#define INTC_ICDABR15_TINT85 (0x00200000uL) -#define INTC_ICDABR15_TINT86 (0x00400000uL) -#define INTC_ICDABR15_TINT87 (0x00800000uL) -#define INTC_ICDABR15_TINT88 (0x01000000uL) -#define INTC_ICDABR15_TINT89 (0x02000000uL) -#define INTC_ICDABR15_TINT90 (0x04000000uL) -#define INTC_ICDABR15_TINT91 (0x08000000uL) -#define INTC_ICDABR15_TINT92 (0x10000000uL) -#define INTC_ICDABR15_TINT93 (0x20000000uL) -#define INTC_ICDABR15_TINT94 (0x40000000uL) -#define INTC_ICDABR15_TINT95 (0x80000000uL) - -#define INTC_ICDABR16_TINT96 (0x00000001uL) -#define INTC_ICDABR16_TINT97 (0x00000002uL) -#define INTC_ICDABR16_TINT98 (0x00000004uL) -#define INTC_ICDABR16_TINT99 (0x00000008uL) -#define INTC_ICDABR16_TINT100 (0x00000010uL) -#define INTC_ICDABR16_TINT101 (0x00000020uL) -#define INTC_ICDABR16_TINT102 (0x00000040uL) -#define INTC_ICDABR16_TINT103 (0x00000080uL) -#define INTC_ICDABR16_TINT104 (0x00000100uL) -#define INTC_ICDABR16_TINT105 (0x00000200uL) -#define INTC_ICDABR16_TINT106 (0x00000400uL) -#define INTC_ICDABR16_TINT107 (0x00000800uL) -#define INTC_ICDABR16_TINT108 (0x00001000uL) -#define INTC_ICDABR16_TINT109 (0x00002000uL) -#define INTC_ICDABR16_TINT110 (0x00004000uL) -#define INTC_ICDABR16_TINT111 (0x00008000uL) -#define INTC_ICDABR16_TINT112 (0x00010000uL) -#define INTC_ICDABR16_TINT113 (0x00020000uL) -#define INTC_ICDABR16_TINT114 (0x00040000uL) -#define INTC_ICDABR16_TINT115 (0x00080000uL) -#define INTC_ICDABR16_TINT116 (0x00100000uL) -#define INTC_ICDABR16_TINT117 (0x00200000uL) -#define INTC_ICDABR16_TINT118 (0x00400000uL) -#define INTC_ICDABR16_TINT119 (0x00800000uL) -#define INTC_ICDABR16_TINT120 (0x01000000uL) -#define INTC_ICDABR16_TINT121 (0x02000000uL) -#define INTC_ICDABR16_TINT122 (0x04000000uL) -#define INTC_ICDABR16_TINT123 (0x08000000uL) -#define INTC_ICDABR16_TINT124 (0x10000000uL) -#define INTC_ICDABR16_TINT125 (0x20000000uL) -#define INTC_ICDABR16_TINT126 (0x40000000uL) -#define INTC_ICDABR16_TINT127 (0x80000000uL) - -#define INTC_ICDABR17_TINT128 (0x00000001uL) -#define INTC_ICDABR17_TINT129 (0x00000002uL) -#define INTC_ICDABR17_TINT130 (0x00000004uL) -#define INTC_ICDABR17_TINT131 (0x00000008uL) -#define INTC_ICDABR17_TINT132 (0x00000010uL) -#define INTC_ICDABR17_TINT133 (0x00000020uL) -#define INTC_ICDABR17_TINT134 (0x00000040uL) -#define INTC_ICDABR17_TINT135 (0x00000080uL) -#define INTC_ICDABR17_TINT136 (0x00000100uL) -#define INTC_ICDABR17_TINT137 (0x00000200uL) -#define INTC_ICDABR17_TINT138 (0x00000400uL) -#define INTC_ICDABR17_TINT139 (0x00000800uL) -#define INTC_ICDABR17_TINT140 (0x00001000uL) -#define INTC_ICDABR17_TINT141 (0x00002000uL) -#define INTC_ICDABR17_TINT142 (0x00004000uL) -#define INTC_ICDABR17_TINT143 (0x00008000uL) -#define INTC_ICDABR17_TINT144 (0x00010000uL) -#define INTC_ICDABR17_TINT145 (0x00020000uL) -#define INTC_ICDABR17_TINT146 (0x00040000uL) -#define INTC_ICDABR17_TINT147 (0x00080000uL) -#define INTC_ICDABR17_TINT148 (0x00100000uL) -#define INTC_ICDABR17_TINT149 (0x00200000uL) -#define INTC_ICDABR17_TINT150 (0x00400000uL) -#define INTC_ICDABR17_TINT151 (0x00800000uL) -#define INTC_ICDABR17_TINT152 (0x01000000uL) -#define INTC_ICDABR17_TINT153 (0x02000000uL) -#define INTC_ICDABR17_TINT154 (0x04000000uL) -#define INTC_ICDABR17_TINT155 (0x08000000uL) -#define INTC_ICDABR17_TINT156 (0x10000000uL) -#define INTC_ICDABR17_TINT157 (0x20000000uL) -#define INTC_ICDABR17_TINT158 (0x40000000uL) -#define INTC_ICDABR17_TINT159 (0x80000000uL) - -#define INTC_ICDABR18_TINT160 (0x00000001uL) -#define INTC_ICDABR18_TINT161 (0x00000002uL) -#define INTC_ICDABR18_TINT162 (0x00000004uL) -#define INTC_ICDABR18_TINT163 (0x00000008uL) -#define INTC_ICDABR18_TINT164 (0x00000010uL) -#define INTC_ICDABR18_TINT165 (0x00000020uL) -#define INTC_ICDABR18_TINT166 (0x00000040uL) -#define INTC_ICDABR18_TINT167 (0x00000080uL) -#define INTC_ICDABR18_TINT168 (0x00000100uL) -#define INTC_ICDABR18_TINT169 (0x00000200uL) -#define INTC_ICDABR18_TINT170 (0x00000400uL) - -#define INTC_ICDIPR0_SW0 (0x000000FFuL) -#define INTC_ICDIPR0_SW1 (0x0000FF00uL) -#define INTC_ICDIPR0_SW2 (0x00FF0000uL) -#define INTC_ICDIPR0_SW3 (0xFF000000uL) - -#define INTC_ICDIPR1_SW4 (0x000000FFuL) -#define INTC_ICDIPR1_SW5 (0x0000FF00uL) -#define INTC_ICDIPR1_SW6 (0x00FF0000uL) -#define INTC_ICDIPR1_SW7 (0xFF000000uL) - -#define INTC_ICDIPR2_SW8 (0x000000FFuL) -#define INTC_ICDIPR2_SW9 (0x0000FF00uL) -#define INTC_ICDIPR2_SW10 (0x00FF0000uL) -#define INTC_ICDIPR2_SW11 (0xFF000000uL) - -#define INTC_ICDIPR3_SW12 (0x000000FFuL) -#define INTC_ICDIPR3_SW13 (0x0000FF00uL) -#define INTC_ICDIPR3_SW14 (0x00FF0000uL) -#define INTC_ICDIPR3_SW15 (0xFF000000uL) - -#define INTC_ICDIPR4_PMUIRQ0 (0x000000FFuL) -#define INTC_ICDIPR4_COMMRX0 (0x0000FF00uL) -#define INTC_ICDIPR4_COMMTX0 (0x00FF0000uL) -#define INTC_ICDIPR4_CTIIRQ0 (0xFF000000uL) - -#define INTC_ICDIPR8_IRQ0 (0x000000FFuL) -#define INTC_ICDIPR8_IRQ1 (0x0000FF00uL) -#define INTC_ICDIPR8_IRQ2 (0x00FF0000uL) -#define INTC_ICDIPR8_IRQ3 (0xFF000000uL) - -#define INTC_ICDIPR9_IRQ4 (0x000000FFuL) -#define INTC_ICDIPR9_IRQ5 (0x0000FF00uL) -#define INTC_ICDIPR9_IRQ6 (0x00FF0000uL) -#define INTC_ICDIPR9_IRQ7 (0xFF000000uL) - -#define INTC_ICDIPR10_PL310ERR (0x000000FFuL) -#define INTC_ICDIPR10_DMAINT0 (0x0000FF00uL) -#define INTC_ICDIPR10_DMAINT1 (0x00FF0000uL) -#define INTC_ICDIPR10_DMAINT2 (0xFF000000uL) - -#define INTC_ICDIPR11_DMAINT3 (0x000000FFuL) -#define INTC_ICDIPR11_DMAINT4 (0x0000FF00uL) -#define INTC_ICDIPR11_DMAINT5 (0x00FF0000uL) -#define INTC_ICDIPR11_DMAINT6 (0xFF000000uL) - -#define INTC_ICDIPR12_DMAINT7 (0x000000FFuL) -#define INTC_ICDIPR12_DMAINT8 (0x0000FF00uL) -#define INTC_ICDIPR12_DMAINT9 (0x00FF0000uL) -#define INTC_ICDIPR12_DMAINT10 (0xFF000000uL) - -#define INTC_ICDIPR13_DMAINT11 (0x000000FFuL) -#define INTC_ICDIPR13_DMAINT12 (0x0000FF00uL) -#define INTC_ICDIPR13_DMAINT13 (0x00FF0000uL) -#define INTC_ICDIPR13_DMAINT14 (0xFF000000uL) - -#define INTC_ICDIPR14_DMAINT15 (0x000000FFuL) -#define INTC_ICDIPR14_DMAERR (0x0000FF00uL) - -#define INTC_ICDIPR18_USBI0 (0x0000FF00uL) -#define INTC_ICDIPR18_USBI1 (0x00FF0000uL) -#define INTC_ICDIPR18_S0_VI_VSYNC0 (0xFF000000uL) - -#define INTC_ICDIPR19_S0_LO_VSYNC0 (0x000000FFuL) -#define INTC_ICDIPR19_S0_VSYNCERR0 (0x0000FF00uL) -#define INTC_ICDIPR19_GR3_VLINE0 (0x00FF0000uL) -#define INTC_ICDIPR19_S0_VFIELD0 (0xFF000000uL) - -#define INTC_ICDIPR20_IV1_VBUFERR0 (0x000000FFuL) -#define INTC_ICDIPR20_IV3_VBUFERR0 (0x0000FF00uL) -#define INTC_ICDIPR20_IV5_VBUFERR0 (0x00FF0000uL) -#define INTC_ICDIPR20_IV6_VBUFERR0 (0xFF000000uL) - -#define INTC_ICDIPR21_S0_WLINE0 (0x000000FFuL) -#define INTC_ICDIPR21_S1_VI_VSYNC0 (0x0000FF00uL) -#define INTC_ICDIPR21_S1_LO_VSYNC0 (0x00FF0000uL) -#define INTC_ICDIPR21_S1_VSYNCERR0 (0xFF000000uL) - -#define INTC_ICDIPR22_S1_VFIELD0 (0x000000FFuL) -#define INTC_ICDIPR22_IV2_VBUFERR0 (0x0000FF00uL) -#define INTC_ICDIPR22_IV4_VBUFERR0 (0x00FF0000uL) -#define INTC_ICDIPR22_S1_WLINE0 (0xFF000000uL) - -#define INTC_ICDIPR23_OIR_VI_VSYNC0 (0x000000FFuL) -#define INTC_ICDIPR23_OIR_LO_VSYNC0 (0x0000FF00uL) -#define INTC_ICDIPR23_OIR_VSYNCERR0 (0x00FF0000uL) -#define INTC_ICDIPR23_OIR_VFIELD0 (0xFF000000uL) - -#define INTC_ICDIPR24_IV7_VBUFERR0 (0x000000FFuL) -#define INTC_ICDIPR24_IV8_VBUFERR0 (0x0000FF00uL) -#define INTC_ICDIPR24_S0_VI_VSYNC1 (0xFF000000uL) - -#define INTC_ICDIPR25_S0_LO_VSYNC1 (0x000000FFuL) -#define INTC_ICDIPR25_S0_VSYNCERR1 (0x0000FF00uL) -#define INTC_ICDIPR25_GR3_VLINE1 (0x00FF0000uL) -#define INTC_ICDIPR25_S0_VFIELD1 (0xFF000000uL) - -#define INTC_ICDIPR26_IV1_VBUFERR1 (0x000000FFuL) -#define INTC_ICDIPR26_IV3_VBUFERR1 (0x0000FF00uL) -#define INTC_ICDIPR26_IV5_VBUFERR1 (0x00FF0000uL) -#define INTC_ICDIPR26_IV6_VBUFERR1 (0xFF000000uL) - -#define INTC_ICDIPR27_S0_WLINE1 (0x000000FFuL) -#define INTC_ICDIPR27_S1_VI_VSYNC1 (0x0000FF00uL) -#define INTC_ICDIPR27_S1_LO_VSYNC1 (0x00FF0000uL) -#define INTC_ICDIPR27_S1_VSYNCERR1 (0xFF000000uL) - -#define INTC_ICDIPR28_S1_VFIELD1 (0x000000FFuL) -#define INTC_ICDIPR28_IV2_VBUFERR1 (0x0000FF00uL) -#define INTC_ICDIPR28_IV4_VBUFERR1 (0x00FF0000uL) -#define INTC_ICDIPR28_S1_WLINE1 (0xFF000000uL) - -#define INTC_ICDIPR29_OIR_VI_VSYNC1 (0x000000FFuL) -#define INTC_ICDIPR29_OIR_LO_VSYNC1 (0x0000FF00uL) -#define INTC_ICDIPR29_OIR_VLINE1 (0x00FF0000uL) -#define INTC_ICDIPR29_OIR_VFIELD1 (0xFF000000uL) - -#define INTC_ICDIPR30_IV7_VBUFERR1 (0x000000FFuL) -#define INTC_ICDIPR30_IV8_VBUFERR1 (0x0000FF00uL) -#define INTC_ICDIPR30_IMRDI (0xFF000000uL) - -#define INTC_ICDIPR31_IMR2I0 (0x000000FFuL) -#define INTC_ICDIPR31_IMR2I1 (0x0000FF00uL) -#define INTC_ICDIPR31_JEDI (0x00FF0000uL) -#define INTC_ICDIPR31_JDTI (0xFF000000uL) - -#define INTC_ICDIPR32_CMP0 (0x000000FFuL) -#define INTC_ICDIPR32_CMP1 (0x0000FF00uL) -#define INTC_ICDIPR32_INT0 (0x00FF0000uL) -#define INTC_ICDIPR32_INT1 (0xFF000000uL) - -#define INTC_ICDIPR33_INT2 (0x000000FFuL) -#define INTC_ICDIPR33_INT3 (0x0000FF00uL) -#define INTC_ICDIPR33_OSTM0TINT (0x00FF0000uL) -#define INTC_ICDIPR33_OSTM1TINT (0xFF000000uL) - -#define INTC_ICDIPR34_CMI (0x000000FFuL) -#define INTC_ICDIPR34_WTOUT (0x0000FF00uL) -#define INTC_ICDIPR34_ITI (0x00FF0000uL) -#define INTC_ICDIPR34_TGI0A (0xFF000000uL) - -#define INTC_ICDIPR35_TGI0B (0x000000FFuL) -#define INTC_ICDIPR35_TGI0C (0x0000FF00uL) -#define INTC_ICDIPR35_TGI0D (0x00FF0000uL) -#define INTC_ICDIPR35_TGI0V (0xFF000000uL) - -#define INTC_ICDIPR36_TGI0E (0x000000FFuL) -#define INTC_ICDIPR36_TGI0F (0x0000FF00uL) -#define INTC_ICDIPR36_TGI1A (0x00FF0000uL) -#define INTC_ICDIPR36_TGI1B (0xFF000000uL) - -#define INTC_ICDIPR37_TGI1V (0x000000FFuL) -#define INTC_ICDIPR37_TGI1U (0x0000FF00uL) -#define INTC_ICDIPR37_TGI2A (0x00FF0000uL) -#define INTC_ICDIPR37_TGI2B (0xFF000000uL) - -#define INTC_ICDIPR38_TGI2V (0x000000FFuL) -#define INTC_ICDIPR38_TGI2U (0x0000FF00uL) -#define INTC_ICDIPR38_TGI3A (0x00FF0000uL) -#define INTC_ICDIPR38_TGI3B (0xFF000000uL) - -#define INTC_ICDIPR39_TGI3C (0x000000FFuL) -#define INTC_ICDIPR39_TGI3D (0x0000FF00uL) -#define INTC_ICDIPR39_TGI3V (0x00FF0000uL) -#define INTC_ICDIPR39_TGI4A (0xFF000000uL) - -#define INTC_ICDIPR40_TGI4B (0x000000FFuL) -#define INTC_ICDIPR40_TGI4C (0x0000FF00uL) -#define INTC_ICDIPR40_TGI4D (0x00FF0000uL) -#define INTC_ICDIPR40_TGI4V (0xFF000000uL) - -#define INTC_ICDIPR41_CMI1 (0x000000FFuL) -#define INTC_ICDIPR41_CMI2 (0x0000FF00uL) -#define INTC_ICDIPR41_SGDEI0 (0x00FF0000uL) -#define INTC_ICDIPR41_SGDEI1 (0xFF000000uL) - -#define INTC_ICDIPR42_SGDEI2 (0x000000FFuL) -#define INTC_ICDIPR42_SGDEI3 (0x0000FF00uL) -#define INTC_ICDIPR42_ADI (0x00FF0000uL) -#define INTC_ICDIPR42_LMTI (0xFF000000uL) - -#define INTC_ICDIPR43_SSII0 (0x000000FFuL) -#define INTC_ICDIPR43_SSIRXI0 (0x0000FF00uL) -#define INTC_ICDIPR43_SSITXI0 (0x00FF0000uL) -#define INTC_ICDIPR43_SSII1 (0xFF000000uL) - -#define INTC_ICDIPR44_SSIRXI1 (0x000000FFuL) -#define INTC_ICDIPR44_SSITXI1 (0x0000FF00uL) -#define INTC_ICDIPR44_SSII2 (0x00FF0000uL) -#define INTC_ICDIPR44_SSIRTI2 (0xFF000000uL) - -#define INTC_ICDIPR45_SSII3 (0x000000FFuL) -#define INTC_ICDIPR45_SSIRXI3 (0x0000FF00uL) -#define INTC_ICDIPR45_SSITXI3 (0x00FF0000uL) -#define INTC_ICDIPR45_SSII4 (0xFF000000uL) - -#define INTC_ICDIPR46_SSIRTI4 (0x000000FFuL) -#define INTC_ICDIPR46_SSII5 (0x0000FF00uL) -#define INTC_ICDIPR46_SSIRXI5 (0x00FF0000uL) -#define INTC_ICDIPR46_SSITXI5 (0xFF000000uL) - -#define INTC_ICDIPR47_SPDIFI (0x000000FFuL) -#define INTC_ICDIPR47_INTIICTEI0 (0x0000FF00uL) -#define INTC_ICDIPR47_INTIICRI0 (0x00FF0000uL) -#define INTC_ICDIPR47_INTIICTI0 (0xFF000000uL) - -#define INTC_ICDIPR48_INTIICSPI0 (0x000000FFuL) -#define INTC_ICDIPR48_INTIICSTI0 (0x0000FF00uL) -#define INTC_ICDIPR48_INTIICNAKI0 (0x00FF0000uL) -#define INTC_ICDIPR48_INTIICALI0 (0xFF000000uL) - -#define INTC_ICDIPR49_INTIICTMOI0 (0x000000FFuL) -#define INTC_ICDIPR49_INTIICTEI1 (0x0000FF00uL) -#define INTC_ICDIPR49_INTIICRI1 (0x00FF0000uL) -#define INTC_ICDIPR49_INTIICTI1 (0xFF000000uL) - -#define INTC_ICDIPR50_INTIICSPI1 (0x000000FFuL) -#define INTC_ICDIPR50_INTIICSTI1 (0x0000FF00uL) -#define INTC_ICDIPR50_INTIICNAKI1 (0x00FF0000uL) -#define INTC_ICDIPR50_INTIICALI1 (0xFF000000uL) - -#define INTC_ICDIPR51_INTIICTMOI1 (0x000000FFuL) -#define INTC_ICDIPR51_INTIICTEI2 (0x0000FF00uL) -#define INTC_ICDIPR51_INTIICRI2 (0x00FF0000uL) -#define INTC_ICDIPR51_INTIICTI2 (0xFF000000uL) - -#define INTC_ICDIPR52_INTIICSPI2 (0x000000FFuL) -#define INTC_ICDIPR52_INTIICSTI2 (0x0000FF00uL) -#define INTC_ICDIPR52_INTIICNAKI2 (0x00FF0000uL) -#define INTC_ICDIPR52_INTIICALI2 (0xFF000000uL) - -#define INTC_ICDIPR53_INTIICTMOI2 (0x000000FFuL) -#define INTC_ICDIPR53_INTIICTEI3 (0x0000FF00uL) -#define INTC_ICDIPR53_INTIICRI3 (0x00FF0000uL) -#define INTC_ICDIPR53_INTIICTI3 (0xFF000000uL) - -#define INTC_ICDIPR54_INTIICSPI3 (0x000000FFuL) -#define INTC_ICDIPR54_INTIICSTI3 (0x0000FF00uL) -#define INTC_ICDIPR54_INTIICNAKI3 (0x00FF0000uL) -#define INTC_ICDIPR54_INTIICALI3 (0xFF000000uL) - -#define INTC_ICDIPR55_INTIICTMOI3 (0x000000FFuL) -#define INTC_ICDIPR55_BRI0 (0x0000FF00uL) -#define INTC_ICDIPR55_ERI0 (0x00FF0000uL) -#define INTC_ICDIPR55_RXI0 (0xFF000000uL) - -#define INTC_ICDIPR56_TXI0 (0x000000FFuL) -#define INTC_ICDIPR56_BRI1 (0x0000FF00uL) -#define INTC_ICDIPR56_ERI1 (0x00FF0000uL) -#define INTC_ICDIPR56_RXI1 (0xFF000000uL) - -#define INTC_ICDIPR57_TXI1 (0x000000FFuL) -#define INTC_ICDIPR57_BRI2 (0x0000FF00uL) -#define INTC_ICDIPR57_ERI2 (0x00FF0000uL) -#define INTC_ICDIPR57_RXI2 (0xFF000000uL) - -#define INTC_ICDIPR58_TXI2 (0x000000FFuL) -#define INTC_ICDIPR58_BRI3 (0x0000FF00uL) -#define INTC_ICDIPR58_ERI3 (0x00FF0000uL) -#define INTC_ICDIPR58_RXI3 (0xFF000000uL) - -#define INTC_ICDIPR59_TXI3 (0x000000FFuL) -#define INTC_ICDIPR59_BRI4 (0x0000FF00uL) -#define INTC_ICDIPR59_ERI4 (0x00FF0000uL) -#define INTC_ICDIPR59_RXI4 (0xFF000000uL) - -#define INTC_ICDIPR60_TXI4 (0x000000FFuL) -#define INTC_ICDIPR60_BRI5 (0x0000FF00uL) -#define INTC_ICDIPR60_ERI5 (0x00FF0000uL) -#define INTC_ICDIPR60_RXI5 (0xFF000000uL) - -#define INTC_ICDIPR61_TXI5 (0x000000FFuL) -#define INTC_ICDIPR61_BRI6 (0x0000FF00uL) -#define INTC_ICDIPR61_ERI6 (0x00FF0000uL) -#define INTC_ICDIPR61_RXI6 (0xFF000000uL) - -#define INTC_ICDIPR62_TXI6 (0x000000FFuL) -#define INTC_ICDIPR62_BRI7 (0x0000FF00uL) -#define INTC_ICDIPR62_ERI7 (0x00FF0000uL) -#define INTC_ICDIPR62_RXI7 (0xFF000000uL) - -#define INTC_ICDIPR63_TXI7 (0x000000FFuL) -#define INTC_ICDIPR63_INTRCANGERR (0x0000FF00uL) -#define INTC_ICDIPR63_INTRCANGRECC (0x00FF0000uL) -#define INTC_ICDIPR63_INTRCAN0REC (0xFF000000uL) - -#define INTC_ICDIPR64_INTRCAN0ERR (0x000000FFuL) -#define INTC_ICDIPR64_INTRCAN0TRX (0x0000FF00uL) -#define INTC_ICDIPR64_INTRCAN1REC (0x00FF0000uL) -#define INTC_ICDIPR64_INTRCAN1ERR (0xFF000000uL) - -#define INTC_ICDIPR65_INTRCAN1TRX (0x000000FFuL) -#define INTC_ICDIPR65_INTRCAN2REC (0x0000FF00uL) -#define INTC_ICDIPR65_INTRCAN2ERR (0x00FF0000uL) -#define INTC_ICDIPR65_INTRCAN2TRX (0xFF000000uL) - -#define INTC_ICDIPR66_INTRCAN3REC (0x000000FFuL) -#define INTC_ICDIPR66_INTRCAN3ERR (0x0000FF00uL) -#define INTC_ICDIPR66_INTRCAN3TRX (0x00FF0000uL) -#define INTC_ICDIPR66_INTRCAN4REC (0xFF000000uL) - -#define INTC_ICDIPR67_INTRCAN4ERR (0x000000FFuL) -#define INTC_ICDIPR67_INTRCAN4TRX (0x0000FF00uL) -#define INTC_ICDIPR67_SPEI0 (0x00FF0000uL) -#define INTC_ICDIPR67_SPRI0 (0xFF000000uL) - -#define INTC_ICDIPR68_SPTI0 (0x000000FFuL) -#define INTC_ICDIPR68_SPEI1 (0x0000FF00uL) -#define INTC_ICDIPR68_SPRI1 (0x00FF0000uL) -#define INTC_ICDIPR68_SPTI1 (0xFF000000uL) - -#define INTC_ICDIPR69_SPEI2 (0x000000FFuL) -#define INTC_ICDIPR69_SPRI2 (0x0000FF00uL) -#define INTC_ICDIPR69_SPTI2 (0x00FF0000uL) -#define INTC_ICDIPR69_SPEI3 (0xFF000000uL) - -#define INTC_ICDIPR70_SPRI3 (0x000000FFuL) -#define INTC_ICDIPR70_SPTI3 (0x0000FF00uL) -#define INTC_ICDIPR70_SPEI4 (0x00FF0000uL) -#define INTC_ICDIPR70_SPRI4 (0xFF000000uL) - -#define INTC_ICDIPR71_SPTI4 (0x000000FFuL) -#define INTC_ICDIPR71_IEBBTD (0x0000FF00uL) -#define INTC_ICDIPR71_IEBBTERR (0x00FF0000uL) -#define INTC_ICDIPR71_IEBBTSTA (0xFF000000uL) - -#define INTC_ICDIPR72_IEBBTV (0x000000FFuL) -#define INTC_ICDIPR72_ISY (0x0000FF00uL) -#define INTC_ICDIPR72_IERR (0x00FF0000uL) -#define INTC_ICDIPR72_ITARG (0xFF000000uL) - -#define INTC_ICDIPR73_ISEC (0x000000FFuL) -#define INTC_ICDIPR73_IBUF (0x0000FF00uL) -#define INTC_ICDIPR73_IREADY (0x00FF0000uL) -#define INTC_ICDIPR73_FLSTE (0xFF000000uL) - -#define INTC_ICDIPR74_FLTENDI (0x000000FFuL) -#define INTC_ICDIPR74_FLTREQ0I (0x0000FF00uL) -#define INTC_ICDIPR74_FLTREQ1I (0x00FF0000uL) -#define INTC_ICDIPR74_MMC0 (0xFF000000uL) - -#define INTC_ICDIPR75_MMC1 (0x000000FFuL) -#define INTC_ICDIPR75_MMC2 (0x0000FF00uL) -#define INTC_ICDIPR75_SDHI0_3 (0x00FF0000uL) -#define INTC_ICDIPR75_SDHI0_0 (0xFF000000uL) - -#define INTC_ICDIPR76_SDHI0_1 (0x000000FFuL) -#define INTC_ICDIPR76_SDHI1_3 (0x0000FF00uL) -#define INTC_ICDIPR76_SDHI1_0 (0x00FF0000uL) -#define INTC_ICDIPR76_SDHI1_1 (0xFF000000uL) - -#define INTC_ICDIPR77_ARM (0x000000FFuL) -#define INTC_ICDIPR77_PRD (0x0000FF00uL) -#define INTC_ICDIPR77_CUP (0x00FF0000uL) -#define INTC_ICDIPR77_SCUAI0 (0xFF000000uL) - -#define INTC_ICDIPR78_SCUAI1 (0x000000FFuL) -#define INTC_ICDIPR78_SCUFDI0 (0x0000FF00uL) -#define INTC_ICDIPR78_SCUFDI1 (0x00FF0000uL) -#define INTC_ICDIPR78_SCUFDI2 (0xFF000000uL) - -#define INTC_ICDIPR79_SCUFDI3 (0x000000FFuL) -#define INTC_ICDIPR79_SCUFUI0 (0x0000FF00uL) -#define INTC_ICDIPR79_SCUFUI1 (0x00FF0000uL) -#define INTC_ICDIPR79_SCUFUI2 (0xFF000000uL) - -#define INTC_ICDIPR80_SCUFUI3 (0x000000FFuL) -#define INTC_ICDIPR80_SCUDVI0 (0x0000FF00uL) -#define INTC_ICDIPR80_SCUDVI1 (0x00FF0000uL) -#define INTC_ICDIPR80_SCUDVI2 (0xFF000000uL) - -#define INTC_ICDIPR81_SCUDVI3 (0x000000FFuL) -#define INTC_ICDIPR81_MLB_CINT (0x0000FF00uL) -#define INTC_ICDIPR81_MLB_SINT (0x00FF0000uL) -#define INTC_ICDIPR81_DRC0 (0xFF000000uL) - -#define INTC_ICDIPR82_DRC1 (0x000000FFuL) -#define INTC_ICDIPR82_LINI0_INT_T (0xFF000000uL) - -#define INTC_ICDIPR83_LINI0_INT_R (0x000000FFuL) -#define INTC_ICDIPR83_LINI0_INT_S (0x0000FF00uL) -#define INTC_ICDIPR83_LINI0_INT_M (0x00FF0000uL) -#define INTC_ICDIPR83_LINI1_INT_T (0xFF000000uL) - -#define INTC_ICDIPR84_LINI1_INT_R (0x000000FFuL) -#define INTC_ICDIPR84_LINI1_INT_S (0x0000FF00uL) -#define INTC_ICDIPR84_LINI1_INT_M (0x00FF0000uL) - -#define INTC_ICDIPR86_ERI0 (0xFF000000uL) - -#define INTC_ICDIPR87_RXI0 (0x000000FFuL) -#define INTC_ICDIPR87_TXI0 (0x0000FF00uL) -#define INTC_ICDIPR87_TEI0 (0x00FF0000uL) -#define INTC_ICDIPR87_ERI1 (0xFF000000uL) - -#define INTC_ICDIPR88_RXI1 (0x000000FFuL) -#define INTC_ICDIPR88_TXI1 (0x0000FF00uL) -#define INTC_ICDIPR88_TEI1 (0x00FF0000uL) -#define INTC_ICDIPR88_AVBI_DATA (0xFF000000uL) - -#define INTC_ICDIPR89_AVBI_ERROR (0x000000FFuL) -#define INTC_ICDIPR89_AVBI_MANAGE (0x0000FF00uL) -#define INTC_ICDIPR89_AVBI_MAC (0x00FF0000uL) -#define INTC_ICDIPR89_ETHERI (0xFF000000uL) - -#define INTC_ICDIPR91_CEUI (0x000000FFuL) - -#define INTC_ICDIPR95_H2XMLB_ERRINT (0x0000FF00uL) -#define INTC_ICDIPR95_H2XIC1_ERRINT (0x00FF0000uL) -#define INTC_ICDIPR95_X2HPERI1_ERRINT (0xFF000000uL) - -#define INTC_ICDIPR96_X2HPERI2_ERRINT (0x000000FFuL) -#define INTC_ICDIPR96_X2HPERI34_ERRINT (0x0000FF00uL) -#define INTC_ICDIPR96_X2HPERI5_ERRINT (0x00FF0000uL) -#define INTC_ICDIPR96_X2HPERI67_ERRINT (0xFF000000uL) - -#define INTC_ICDIPR97_X2HDBGR_ERRINT (0x000000FFuL) -#define INTC_ICDIPR97_X2HBSC_ERRINT (0x0000FF00uL) -#define INTC_ICDIPR97_X2HSPI1_ERRINT (0x00FF0000uL) -#define INTC_ICDIPR97_X2HSPI2_ERRINT (0xFF000000uL) - -#define INTC_ICDIPR98_PRRI (0x000000FFuL) -#define INTC_ICDIPR98_IFEI0 (0x0000FF00uL) -#define INTC_ICDIPR98_OFFI0 (0x00FF0000uL) -#define INTC_ICDIPR98_PFVEI0 (0xFF000000uL) - -#define INTC_ICDIPR99_IFEI1 (0x000000FFuL) -#define INTC_ICDIPR99_OFFI1 (0x0000FF00uL) -#define INTC_ICDIPR99_PFVEI1 (0x00FF0000uL) - -#define INTC_ICDIPR104_TINT0 (0x000000FFuL) -#define INTC_ICDIPR104_TINT1 (0x0000FF00uL) -#define INTC_ICDIPR104_TINT2 (0x00FF0000uL) -#define INTC_ICDIPR104_TINT3 (0xFF000000uL) - -#define INTC_ICDIPR105_TINT4 (0x000000FFuL) -#define INTC_ICDIPR105_TINT5 (0x0000FF00uL) -#define INTC_ICDIPR105_TINT6 (0x00FF0000uL) -#define INTC_ICDIPR105_TINT7 (0xFF000000uL) - -#define INTC_ICDIPR106_TINT8 (0x000000FFuL) -#define INTC_ICDIPR106_TINT9 (0x0000FF00uL) -#define INTC_ICDIPR106_TINT10 (0x00FF0000uL) -#define INTC_ICDIPR106_TINT11 (0xFF000000uL) - -#define INTC_ICDIPR107_TINT12 (0x000000FFuL) -#define INTC_ICDIPR107_TINT13 (0x0000FF00uL) -#define INTC_ICDIPR107_TINT14 (0x00FF0000uL) -#define INTC_ICDIPR107_TINT15 (0xFF000000uL) - -#define INTC_ICDIPR108_TINT16 (0x000000FFuL) -#define INTC_ICDIPR108_TINT17 (0x0000FF00uL) -#define INTC_ICDIPR108_TINT18 (0x00FF0000uL) -#define INTC_ICDIPR108_TINT19 (0xFF000000uL) - -#define INTC_ICDIPR109_TINT20 (0x000000FFuL) -#define INTC_ICDIPR109_TINT21 (0x0000FF00uL) -#define INTC_ICDIPR109_TINT22 (0x00FF0000uL) -#define INTC_ICDIPR109_TINT23 (0xFF000000uL) - -#define INTC_ICDIPR110_TINT24 (0x000000FFuL) -#define INTC_ICDIPR110_TINT25 (0x0000FF00uL) -#define INTC_ICDIPR110_TINT26 (0x00FF0000uL) -#define INTC_ICDIPR110_TINT27 (0xFF000000uL) - -#define INTC_ICDIPR111_TINT28 (0x000000FFuL) -#define INTC_ICDIPR111_TINT29 (0x0000FF00uL) -#define INTC_ICDIPR111_TINT30 (0x00FF0000uL) -#define INTC_ICDIPR111_TINT31 (0xFF000000uL) - -#define INTC_ICDIPR112_TINT32 (0x000000FFuL) -#define INTC_ICDIPR112_TINT33 (0x0000FF00uL) -#define INTC_ICDIPR112_TINT34 (0x00FF0000uL) -#define INTC_ICDIPR112_TINT35 (0xFF000000uL) - -#define INTC_ICDIPR113_TINT36 (0x000000FFuL) -#define INTC_ICDIPR113_TINT37 (0x0000FF00uL) -#define INTC_ICDIPR113_TINT38 (0x00FF0000uL) -#define INTC_ICDIPR113_TINT39 (0xFF000000uL) - -#define INTC_ICDIPR114_TINT40 (0x000000FFuL) -#define INTC_ICDIPR114_TINT41 (0x0000FF00uL) -#define INTC_ICDIPR114_TINT42 (0x00FF0000uL) -#define INTC_ICDIPR114_TINT43 (0xFF000000uL) - -#define INTC_ICDIPR115_TINT44 (0x000000FFuL) -#define INTC_ICDIPR115_TINT45 (0x0000FF00uL) -#define INTC_ICDIPR115_TINT46 (0x00FF0000uL) -#define INTC_ICDIPR115_TINT47 (0xFF000000uL) - -#define INTC_ICDIPR116_TINT48 (0x000000FFuL) -#define INTC_ICDIPR116_TINT49 (0x0000FF00uL) -#define INTC_ICDIPR116_TINT50 (0x00FF0000uL) -#define INTC_ICDIPR116_TINT51 (0xFF000000uL) - -#define INTC_ICDIPR117_TINT52 (0x000000FFuL) -#define INTC_ICDIPR117_TINT53 (0x0000FF00uL) -#define INTC_ICDIPR117_TINT54 (0x00FF0000uL) -#define INTC_ICDIPR117_TINT55 (0xFF000000uL) - -#define INTC_ICDIPR118_TINT56 (0x000000FFuL) -#define INTC_ICDIPR118_TINT57 (0x0000FF00uL) -#define INTC_ICDIPR118_TINT58 (0x00FF0000uL) -#define INTC_ICDIPR118_TINT59 (0xFF000000uL) - -#define INTC_ICDIPR119_TINT60 (0x000000FFuL) -#define INTC_ICDIPR119_TINT61 (0x0000FF00uL) -#define INTC_ICDIPR119_TINT62 (0x00FF0000uL) -#define INTC_ICDIPR119_TINT63 (0xFF000000uL) - -#define INTC_ICDIPR120_TINT64 (0x000000FFuL) -#define INTC_ICDIPR120_TINT65 (0x0000FF00uL) -#define INTC_ICDIPR120_TINT66 (0x00FF0000uL) -#define INTC_ICDIPR120_TINT67 (0xFF000000uL) - -#define INTC_ICDIPR121_TINT68 (0x000000FFuL) -#define INTC_ICDIPR121_TINT69 (0x0000FF00uL) -#define INTC_ICDIPR121_TINT70 (0x00FF0000uL) -#define INTC_ICDIPR121_TINT71 (0xFF000000uL) - -#define INTC_ICDIPR122_TINT72 (0x000000FFuL) -#define INTC_ICDIPR122_TINT73 (0x0000FF00uL) -#define INTC_ICDIPR122_TINT74 (0x00FF0000uL) -#define INTC_ICDIPR122_TINT75 (0xFF000000uL) - -#define INTC_ICDIPR123_TINT76 (0x000000FFuL) -#define INTC_ICDIPR123_TINT77 (0x0000FF00uL) -#define INTC_ICDIPR123_TINT78 (0x00FF0000uL) -#define INTC_ICDIPR123_TINT79 (0xFF000000uL) - -#define INTC_ICDIPR124_TINT80 (0x000000FFuL) -#define INTC_ICDIPR124_TINT81 (0x0000FF00uL) -#define INTC_ICDIPR124_TINT82 (0x00FF0000uL) -#define INTC_ICDIPR124_TINT83 (0xFF000000uL) - -#define INTC_ICDIPR125_TINT84 (0x000000FFuL) -#define INTC_ICDIPR125_TINT85 (0x0000FF00uL) -#define INTC_ICDIPR125_TINT86 (0x00FF0000uL) -#define INTC_ICDIPR125_TINT87 (0xFF000000uL) - -#define INTC_ICDIPR126_TINT88 (0x000000FFuL) -#define INTC_ICDIPR126_TINT89 (0x0000FF00uL) -#define INTC_ICDIPR126_TINT90 (0x00FF0000uL) -#define INTC_ICDIPR126_TINT91 (0xFF000000uL) - -#define INTC_ICDIPR127_TINT92 (0x000000FFuL) -#define INTC_ICDIPR127_TINT93 (0x0000FF00uL) -#define INTC_ICDIPR127_TINT94 (0x00FF0000uL) -#define INTC_ICDIPR127_TINT95 (0xFF000000uL) - -#define INTC_ICDIPR128_TINT96 (0x000000FFuL) -#define INTC_ICDIPR128_TINT97 (0x0000FF00uL) -#define INTC_ICDIPR128_TINT98 (0x00FF0000uL) -#define INTC_ICDIPR128_TINT99 (0xFF000000uL) - -#define INTC_ICDIPR129_TINT100 (0x000000FFuL) -#define INTC_ICDIPR129_TINT101 (0x0000FF00uL) -#define INTC_ICDIPR129_TINT102 (0x00FF0000uL) -#define INTC_ICDIPR129_TINT103 (0xFF000000uL) - -#define INTC_ICDIPR130_TINT104 (0x000000FFuL) -#define INTC_ICDIPR130_TINT105 (0x0000FF00uL) -#define INTC_ICDIPR130_TINT106 (0x00FF0000uL) -#define INTC_ICDIPR130_TINT107 (0xFF000000uL) - -#define INTC_ICDIPR131_TINT108 (0x000000FFuL) -#define INTC_ICDIPR131_TINT109 (0x0000FF00uL) -#define INTC_ICDIPR131_TINT110 (0x00FF0000uL) -#define INTC_ICDIPR131_TINT111 (0xFF000000uL) - -#define INTC_ICDIPR132_TINT112 (0x000000FFuL) -#define INTC_ICDIPR132_TINT113 (0x0000FF00uL) -#define INTC_ICDIPR132_TINT114 (0x00FF0000uL) -#define INTC_ICDIPR132_TINT115 (0xFF000000uL) - -#define INTC_ICDIPR133_TINT116 (0x000000FFuL) -#define INTC_ICDIPR133_TINT117 (0x0000FF00uL) -#define INTC_ICDIPR133_TINT118 (0x00FF0000uL) -#define INTC_ICDIPR133_TINT119 (0xFF000000uL) - -#define INTC_ICDIPR134_TINT120 (0x000000FFuL) -#define INTC_ICDIPR134_TINT121 (0x0000FF00uL) -#define INTC_ICDIPR134_TINT122 (0x00FF0000uL) -#define INTC_ICDIPR134_TINT123 (0xFF000000uL) - -#define INTC_ICDIPR135_TINT124 (0x000000FFuL) -#define INTC_ICDIPR135_TINT125 (0x0000FF00uL) -#define INTC_ICDIPR135_TINT126 (0x00FF0000uL) -#define INTC_ICDIPR135_TINT127 (0xFF000000uL) - -#define INTC_ICDIPR136_TINT128 (0x000000FFuL) -#define INTC_ICDIPR136_TINT129 (0x0000FF00uL) -#define INTC_ICDIPR136_TINT130 (0x00FF0000uL) -#define INTC_ICDIPR136_TINT131 (0xFF000000uL) - -#define INTC_ICDIPR137_TINT132 (0x000000FFuL) -#define INTC_ICDIPR137_TINT133 (0x0000FF00uL) -#define INTC_ICDIPR137_TINT134 (0x00FF0000uL) -#define INTC_ICDIPR137_TINT135 (0xFF000000uL) - -#define INTC_ICDIPR138_TINT136 (0x000000FFuL) -#define INTC_ICDIPR138_TINT137 (0x0000FF00uL) -#define INTC_ICDIPR138_TINT138 (0x00FF0000uL) -#define INTC_ICDIPR138_TINT139 (0xFF000000uL) - -#define INTC_ICDIPR139_TINT140 (0x000000FFuL) -#define INTC_ICDIPR139_TINT141 (0x0000FF00uL) -#define INTC_ICDIPR139_TINT142 (0x00FF0000uL) -#define INTC_ICDIPR139_TINT143 (0xFF000000uL) - -#define INTC_ICDIPR140_TINT144 (0x000000FFuL) -#define INTC_ICDIPR140_TINT145 (0x0000FF00uL) -#define INTC_ICDIPR140_TINT146 (0x00FF0000uL) -#define INTC_ICDIPR140_TINT147 (0xFF000000uL) - -#define INTC_ICDIPR141_TINT148 (0x000000FFuL) -#define INTC_ICDIPR141_TINT149 (0x0000FF00uL) -#define INTC_ICDIPR141_TINT150 (0x00FF0000uL) -#define INTC_ICDIPR141_TINT151 (0xFF000000uL) - -#define INTC_ICDIPR142_TINT152 (0x000000FFuL) -#define INTC_ICDIPR142_TINT153 (0x0000FF00uL) -#define INTC_ICDIPR142_TINT154 (0x00FF0000uL) -#define INTC_ICDIPR142_TINT155 (0xFF000000uL) - -#define INTC_ICDIPR143_TINT156 (0x000000FFuL) -#define INTC_ICDIPR143_TINT157 (0x0000FF00uL) -#define INTC_ICDIPR143_TINT158 (0x00FF0000uL) -#define INTC_ICDIPR143_TINT159 (0xFF000000uL) - -#define INTC_ICDIPR144_TINT160 (0x000000FFuL) -#define INTC_ICDIPR144_TINT161 (0x0000FF00uL) -#define INTC_ICDIPR144_TINT162 (0x00FF0000uL) -#define INTC_ICDIPR144_TINT163 (0xFF000000uL) - -#define INTC_ICDIPR145_TINT164 (0x000000FFuL) -#define INTC_ICDIPR145_TINT165 (0x0000FF00uL) -#define INTC_ICDIPR145_TINT166 (0x00FF0000uL) -#define INTC_ICDIPR145_TINT167 (0xFF000000uL) - -#define INTC_ICDIPR146_TINT168 (0x000000FFuL) -#define INTC_ICDIPR146_TINT169 (0x0000FF00uL) -#define INTC_ICDIPR146_TINT170 (0x00FF0000uL) - -#define INTC_ICDIPTR0_SW0 (0x000000FFuL) -#define INTC_ICDIPTR0_SW1 (0x0000FF00uL) -#define INTC_ICDIPTR0_SW2 (0x00FF0000uL) -#define INTC_ICDIPTR0_SW3 (0xFF000000uL) - -#define INTC_ICDIPTR1_SW4 (0x000000FFuL) -#define INTC_ICDIPTR1_SW5 (0x0000FF00uL) -#define INTC_ICDIPTR1_SW6 (0x00FF0000uL) -#define INTC_ICDIPTR1_SW7 (0xFF000000uL) - -#define INTC_ICDIPTR2_SW8 (0x000000FFuL) -#define INTC_ICDIPTR2_SW9 (0x0000FF00uL) -#define INTC_ICDIPTR2_SW10 (0x00FF0000uL) -#define INTC_ICDIPTR2_SW11 (0xFF000000uL) - -#define INTC_ICDIPTR3_SW12 (0x000000FFuL) -#define INTC_ICDIPTR3_SW13 (0x0000FF00uL) -#define INTC_ICDIPTR3_SW14 (0x00FF0000uL) -#define INTC_ICDIPTR3_SW15 (0xFF000000uL) - -#define INTC_ICDIPTR4_PMUIRQ0 (0x000000FFuL) -#define INTC_ICDIPTR4_COMMRX0 (0x0000FF00uL) -#define INTC_ICDIPTR4_COMMTX0 (0x00FF0000uL) -#define INTC_ICDIPTR4_CTIIRQ0 (0xFF000000uL) - -#define INTC_ICDIPTR8_IRQ0 (0x000000FFuL) -#define INTC_ICDIPTR8_IRQ1 (0x0000FF00uL) -#define INTC_ICDIPTR8_IRQ2 (0x00FF0000uL) -#define INTC_ICDIPTR8_IRQ3 (0xFF000000uL) - -#define INTC_ICDIPTR9_IRQ4 (0x000000FFuL) -#define INTC_ICDIPTR9_IRQ5 (0x0000FF00uL) -#define INTC_ICDIPTR9_IRQ6 (0x00FF0000uL) -#define INTC_ICDIPTR9_IRQ7 (0xFF000000uL) - -#define INTC_ICDIPTR10_PL310ERR (0x000000FFuL) -#define INTC_ICDIPTR10_DMAINT0 (0x0000FF00uL) -#define INTC_ICDIPTR10_DMAINT1 (0x00FF0000uL) -#define INTC_ICDIPTR10_DMAINT2 (0xFF000000uL) - -#define INTC_ICDIPTR11_DMAINT3 (0x000000FFuL) -#define INTC_ICDIPTR11_DMAINT4 (0x0000FF00uL) -#define INTC_ICDIPTR11_DMAINT5 (0x00FF0000uL) -#define INTC_ICDIPTR11_DMAINT6 (0xFF000000uL) - -#define INTC_ICDIPTR12_DMAINT7 (0x000000FFuL) -#define INTC_ICDIPTR12_DMAINT8 (0x0000FF00uL) -#define INTC_ICDIPTR12_DMAINT9 (0x00FF0000uL) -#define INTC_ICDIPTR12_DMAINT10 (0xFF000000uL) - -#define INTC_ICDIPTR13_DMAINT11 (0x000000FFuL) -#define INTC_ICDIPTR13_DMAINT12 (0x0000FF00uL) -#define INTC_ICDIPTR13_DMAINT13 (0x00FF0000uL) -#define INTC_ICDIPTR13_DMAINT14 (0xFF000000uL) - -#define INTC_ICDIPTR14_DMAINT15 (0x000000FFuL) -#define INTC_ICDIPTR14_DMAERR (0x0000FF00uL) - -#define INTC_ICDIPTR18_USBI0 (0x0000FF00uL) -#define INTC_ICDIPTR18_USBI1 (0x00FF0000uL) -#define INTC_ICDIPTR18_S0_VI_VSYNC0 (0xFF000000uL) - -#define INTC_ICDIPTR19_S0_LO_VSYNC0 (0x000000FFuL) -#define INTC_ICDIPTR19_S0_VSYNCERR0 (0x0000FF00uL) -#define INTC_ICDIPTR19_GR3_VLINE0 (0x00FF0000uL) -#define INTC_ICDIPTR19_S0_VFIELD0 (0xFF000000uL) - -#define INTC_ICDIPTR20_IV1_VBUFERR0 (0x000000FFuL) -#define INTC_ICDIPTR20_IV3_VBUFERR0 (0x0000FF00uL) -#define INTC_ICDIPTR20_IV5_VBUFERR0 (0x00FF0000uL) -#define INTC_ICDIPTR20_IV6_VBUFERR0 (0xFF000000uL) - -#define INTC_ICDIPTR21_S0_WLINE0 (0x000000FFuL) -#define INTC_ICDIPTR21_S1_VI_VSYNC0 (0x0000FF00uL) -#define INTC_ICDIPTR21_S1_LO_VSYNC0 (0x00FF0000uL) -#define INTC_ICDIPTR21_S1_VSYNCERR0 (0xFF000000uL) - -#define INTC_ICDIPTR22_S1_VFIELD0 (0x000000FFuL) -#define INTC_ICDIPTR22_IV2_VBUFERR0 (0x0000FF00uL) -#define INTC_ICDIPTR22_IV4_VBUFERR0 (0x00FF0000uL) -#define INTC_ICDIPTR22_S1_WLINE0 (0xFF000000uL) - -#define INTC_ICDIPTR23_OIR_VI_VSYNC0 (0x000000FFuL) -#define INTC_ICDIPTR23_OIR_LO_VSYNC0 (0x0000FF00uL) -#define INTC_ICDIPTR23_OIR_VSYNCERR0 (0x00FF0000uL) -#define INTC_ICDIPTR23_OIR_VFIELD0 (0xFF000000uL) - -#define INTC_ICDIPTR24_IV7_VBUFERR0 (0x000000FFuL) -#define INTC_ICDIPTR24_IV8_VBUFERR0 (0x0000FF00uL) -#define INTC_ICDIPTR24_S0_VI_VSYNC1 (0xFF000000uL) - -#define INTC_ICDIPTR25_S0_LO_VSYNC1 (0x000000FFuL) -#define INTC_ICDIPTR25_S0_VSYNCERR1 (0x0000FF00uL) -#define INTC_ICDIPTR25_GR3_VLINE1 (0x00FF0000uL) -#define INTC_ICDIPTR25_S0_VFIELD1 (0xFF000000uL) - -#define INTC_ICDIPTR26_IV1_VBUFERR1 (0x000000FFuL) -#define INTC_ICDIPTR26_IV3_VBUFERR1 (0x0000FF00uL) -#define INTC_ICDIPTR26_IV5_VBUFERR1 (0x00FF0000uL) -#define INTC_ICDIPTR26_IV6_VBUFERR1 (0xFF000000uL) - -#define INTC_ICDIPTR27_S0_WLINE1 (0x000000FFuL) -#define INTC_ICDIPTR27_S1_VI_VSYNC1 (0x0000FF00uL) -#define INTC_ICDIPTR27_S1_LO_VSYNC1 (0x00FF0000uL) -#define INTC_ICDIPTR27_S1_VSYNCERR1 (0xFF000000uL) - -#define INTC_ICDIPTR28_S1_VFIELD1 (0x000000FFuL) -#define INTC_ICDIPTR28_IV2_VBUFERR1 (0x0000FF00uL) -#define INTC_ICDIPTR28_IV4_VBUFERR1 (0x00FF0000uL) -#define INTC_ICDIPTR28_S1_WLINE1 (0xFF000000uL) - -#define INTC_ICDIPTR29_OIR_VI_VSYNC1 (0x000000FFuL) -#define INTC_ICDIPTR29_OIR_LO_VSYNC1 (0x0000FF00uL) -#define INTC_ICDIPTR29_OIR_VLINE1 (0x00FF0000uL) -#define INTC_ICDIPTR29_OIR_VFIELD1 (0xFF000000uL) - -#define INTC_ICDIPTR30_IV7_VBUFERR1 (0x000000FFuL) -#define INTC_ICDIPTR30_IV8_VBUFERR1 (0x0000FF00uL) -#define INTC_ICDIPTR30_IMRDI (0xFF000000uL) - -#define INTC_ICDIPTR31_IMR2I0 (0x000000FFuL) -#define INTC_ICDIPTR31_IMR2I1 (0x0000FF00uL) -#define INTC_ICDIPTR31_JEDI (0x00FF0000uL) -#define INTC_ICDIPTR31_JDTI (0xFF000000uL) - -#define INTC_ICDIPTR32_CMP0 (0x000000FFuL) -#define INTC_ICDIPTR32_CMP1 (0x0000FF00uL) -#define INTC_ICDIPTR32_INT0 (0x00FF0000uL) -#define INTC_ICDIPTR32_INT1 (0xFF000000uL) - -#define INTC_ICDIPTR33_INT2 (0x000000FFuL) -#define INTC_ICDIPTR33_INT3 (0x0000FF00uL) -#define INTC_ICDIPTR33_OSTM0TINT (0x00FF0000uL) -#define INTC_ICDIPTR33_OSTM1TINT (0xFF000000uL) - -#define INTC_ICDIPTR34_CMI (0x000000FFuL) -#define INTC_ICDIPTR34_WTOUT (0x0000FF00uL) -#define INTC_ICDIPTR34_ITI (0x00FF0000uL) -#define INTC_ICDIPTR34_TGI0A (0xFF000000uL) - -#define INTC_ICDIPTR35_TGI0B (0x000000FFuL) -#define INTC_ICDIPTR35_TGI0C (0x0000FF00uL) -#define INTC_ICDIPTR35_TGI0D (0x00FF0000uL) -#define INTC_ICDIPTR35_TGI0V (0xFF000000uL) - -#define INTC_ICDIPTR36_TGI0E (0x000000FFuL) -#define INTC_ICDIPTR36_TGI0F (0x0000FF00uL) -#define INTC_ICDIPTR36_TGI1A (0x00FF0000uL) -#define INTC_ICDIPTR36_TGI1B (0xFF000000uL) - -#define INTC_ICDIPTR37_TGI1V (0x000000FFuL) -#define INTC_ICDIPTR37_TGI1U (0x0000FF00uL) -#define INTC_ICDIPTR37_TGI2A (0x00FF0000uL) -#define INTC_ICDIPTR37_TGI2B (0xFF000000uL) - -#define INTC_ICDIPTR38_TGI2V (0x000000FFuL) -#define INTC_ICDIPTR38_TGI2U (0x0000FF00uL) -#define INTC_ICDIPTR38_TGI3A (0x00FF0000uL) -#define INTC_ICDIPTR38_TGI3B (0xFF000000uL) - -#define INTC_ICDIPTR39_TGI3C (0x000000FFuL) -#define INTC_ICDIPTR39_TGI3D (0x0000FF00uL) -#define INTC_ICDIPTR39_TGI3V (0x00FF0000uL) -#define INTC_ICDIPTR39_TGI4A (0xFF000000uL) - -#define INTC_ICDIPTR40_TGI4B (0x000000FFuL) -#define INTC_ICDIPTR40_TGI4C (0x0000FF00uL) -#define INTC_ICDIPTR40_TGI4D (0x00FF0000uL) -#define INTC_ICDIPTR40_TGI4V (0xFF000000uL) - -#define INTC_ICDIPTR41_CMI1 (0x000000FFuL) -#define INTC_ICDIPTR41_CMI2 (0x0000FF00uL) -#define INTC_ICDIPTR41_SGDEI0 (0x00FF0000uL) -#define INTC_ICDIPTR41_SGDEI1 (0xFF000000uL) - -#define INTC_ICDIPTR42_SGDEI2 (0x000000FFuL) -#define INTC_ICDIPTR42_SGDEI3 (0x0000FF00uL) -#define INTC_ICDIPTR42_ADI (0x00FF0000uL) -#define INTC_ICDIPTR42_LMTI (0xFF000000uL) - -#define INTC_ICDIPTR43_SSII0 (0x000000FFuL) -#define INTC_ICDIPTR43_SSIRXI0 (0x0000FF00uL) -#define INTC_ICDIPTR43_SSITXI0 (0x00FF0000uL) -#define INTC_ICDIPTR43_SSII1 (0xFF000000uL) - -#define INTC_ICDIPTR44_SSIRXI1 (0x000000FFuL) -#define INTC_ICDIPTR44_SSITXI1 (0x0000FF00uL) -#define INTC_ICDIPTR44_SSII2 (0x00FF0000uL) -#define INTC_ICDIPTR44_SSIRTI2 (0xFF000000uL) - -#define INTC_ICDIPTR45_SSII3 (0x000000FFuL) -#define INTC_ICDIPTR45_SSIRXI3 (0x0000FF00uL) -#define INTC_ICDIPTR45_SSITXI3 (0x00FF0000uL) -#define INTC_ICDIPTR45_SSII4 (0xFF000000uL) - -#define INTC_ICDIPTR46_SSIRTI4 (0x000000FFuL) -#define INTC_ICDIPTR46_SSII5 (0x0000FF00uL) -#define INTC_ICDIPTR46_SSIRXI5 (0x00FF0000uL) -#define INTC_ICDIPTR46_SSITXI5 (0xFF000000uL) - -#define INTC_ICDIPTR47_SPDIFI (0x000000FFuL) -#define INTC_ICDIPTR47_INTIICTEI0 (0x0000FF00uL) -#define INTC_ICDIPTR47_INTIICRI0 (0x00FF0000uL) -#define INTC_ICDIPTR47_INTIICTI0 (0xFF000000uL) - -#define INTC_ICDIPTR48_INTIICSPI0 (0x000000FFuL) -#define INTC_ICDIPTR48_INTIICSTI0 (0x0000FF00uL) -#define INTC_ICDIPTR48_INTIICNAKI0 (0x00FF0000uL) -#define INTC_ICDIPTR48_INTIICALI0 (0xFF000000uL) - -#define INTC_ICDIPTR49_INTIICTMOI0 (0x000000FFuL) -#define INTC_ICDIPTR49_INTIICTEI1 (0x0000FF00uL) -#define INTC_ICDIPTR49_INTIICRI1 (0x00FF0000uL) -#define INTC_ICDIPTR49_INTIICTI1 (0xFF000000uL) - -#define INTC_ICDIPTR50_INTIICSPI1 (0x000000FFuL) -#define INTC_ICDIPTR50_INTIICSTI1 (0x0000FF00uL) -#define INTC_ICDIPTR50_INTIICNAKI1 (0x00FF0000uL) -#define INTC_ICDIPTR50_INTIICALI1 (0xFF000000uL) - -#define INTC_ICDIPTR51_INTIICTMOI1 (0x000000FFuL) -#define INTC_ICDIPTR51_INTIICTEI2 (0x0000FF00uL) -#define INTC_ICDIPTR51_INTIICRI2 (0x00FF0000uL) -#define INTC_ICDIPTR51_INTIICTI2 (0xFF000000uL) - -#define INTC_ICDIPTR52_INTIICSPI2 (0x000000FFuL) -#define INTC_ICDIPTR52_INTIICSTI2 (0x0000FF00uL) -#define INTC_ICDIPTR52_INTIICNAKI2 (0x00FF0000uL) -#define INTC_ICDIPTR52_INTIICALI2 (0xFF000000uL) - -#define INTC_ICDIPTR53_INTIICTMOI2 (0x000000FFuL) -#define INTC_ICDIPTR53_INTIICTEI3 (0x0000FF00uL) -#define INTC_ICDIPTR53_INTIICRI3 (0x00FF0000uL) -#define INTC_ICDIPTR53_INTIICTI3 (0xFF000000uL) - -#define INTC_ICDIPTR54_INTIICSPI3 (0x000000FFuL) -#define INTC_ICDIPTR54_INTIICSTI3 (0x0000FF00uL) -#define INTC_ICDIPTR54_INTIICNAKI3 (0x00FF0000uL) -#define INTC_ICDIPTR54_INTIICALI3 (0xFF000000uL) - -#define INTC_ICDIPTR55_INTIICTMOI3 (0x000000FFuL) -#define INTC_ICDIPTR55_BRI0 (0x0000FF00uL) -#define INTC_ICDIPTR55_ERI0 (0x00FF0000uL) -#define INTC_ICDIPTR55_RXI0 (0xFF000000uL) - -#define INTC_ICDIPTR56_TXI0 (0x000000FFuL) -#define INTC_ICDIPTR56_BRI1 (0x0000FF00uL) -#define INTC_ICDIPTR56_ERI1 (0x00FF0000uL) -#define INTC_ICDIPTR56_RXI1 (0xFF000000uL) - -#define INTC_ICDIPTR57_TXI1 (0x000000FFuL) -#define INTC_ICDIPTR57_BRI2 (0x0000FF00uL) -#define INTC_ICDIPTR57_ERI2 (0x00FF0000uL) -#define INTC_ICDIPTR57_RXI2 (0xFF000000uL) - -#define INTC_ICDIPTR58_TXI2 (0x000000FFuL) -#define INTC_ICDIPTR58_BRI3 (0x0000FF00uL) -#define INTC_ICDIPTR58_ERI3 (0x00FF0000uL) -#define INTC_ICDIPTR58_RXI3 (0xFF000000uL) - -#define INTC_ICDIPTR59_TXI3 (0x000000FFuL) -#define INTC_ICDIPTR59_BRI4 (0x0000FF00uL) -#define INTC_ICDIPTR59_ERI4 (0x00FF0000uL) -#define INTC_ICDIPTR59_RXI4 (0xFF000000uL) - -#define INTC_ICDIPTR60_TXI4 (0x000000FFuL) -#define INTC_ICDIPTR60_BRI5 (0x0000FF00uL) -#define INTC_ICDIPTR60_ERI5 (0x00FF0000uL) -#define INTC_ICDIPTR60_RXI5 (0xFF000000uL) - -#define INTC_ICDIPTR61_TXI5 (0x000000FFuL) -#define INTC_ICDIPTR61_BRI6 (0x0000FF00uL) -#define INTC_ICDIPTR61_ERI6 (0x00FF0000uL) -#define INTC_ICDIPTR61_RXI6 (0xFF000000uL) - -#define INTC_ICDIPTR62_TXI6 (0x000000FFuL) -#define INTC_ICDIPTR62_BRI7 (0x0000FF00uL) -#define INTC_ICDIPTR62_ERI7 (0x00FF0000uL) -#define INTC_ICDIPTR62_RXI7 (0xFF000000uL) - -#define INTC_ICDIPTR63_TXI7 (0x000000FFuL) -#define INTC_ICDIPTR63_INTRCANGERR (0x0000FF00uL) -#define INTC_ICDIPTR63_INTRCANGRECC (0x00FF0000uL) -#define INTC_ICDIPTR63_INTRCAN0REC (0xFF000000uL) - -#define INTC_ICDIPTR64_INTRCAN0ERR (0x000000FFuL) -#define INTC_ICDIPTR64_INTRCAN0TRX (0x0000FF00uL) -#define INTC_ICDIPTR64_INTRCAN1REC (0x00FF0000uL) -#define INTC_ICDIPTR64_INTRCAN1ERR (0xFF000000uL) - -#define INTC_ICDIPTR65_INTRCAN1TRX (0x000000FFuL) -#define INTC_ICDIPTR65_INTRCAN2REC (0x0000FF00uL) -#define INTC_ICDIPTR65_INTRCAN2ERR (0x00FF0000uL) -#define INTC_ICDIPTR65_INTRCAN2TRX (0xFF000000uL) - -#define INTC_ICDIPTR66_INTRCAN3REC (0x000000FFuL) -#define INTC_ICDIPTR66_INTRCAN3ERR (0x0000FF00uL) -#define INTC_ICDIPTR66_INTRCAN3TRX (0x00FF0000uL) -#define INTC_ICDIPTR66_INTRCAN4REC (0xFF000000uL) - -#define INTC_ICDIPTR67_INTRCAN4ERR (0x000000FFuL) -#define INTC_ICDIPTR67_INTRCAN4TRX (0x0000FF00uL) -#define INTC_ICDIPTR67_SPEI0 (0x00FF0000uL) -#define INTC_ICDIPTR67_SPRI0 (0xFF000000uL) - -#define INTC_ICDIPTR68_SPTI0 (0x000000FFuL) -#define INTC_ICDIPTR68_SPEI1 (0x0000FF00uL) -#define INTC_ICDIPTR68_SPRI1 (0x00FF0000uL) -#define INTC_ICDIPTR68_SPTI1 (0xFF000000uL) - -#define INTC_ICDIPTR69_SPEI2 (0x000000FFuL) -#define INTC_ICDIPTR69_SPRI2 (0x0000FF00uL) -#define INTC_ICDIPTR69_SPTI2 (0x00FF0000uL) -#define INTC_ICDIPTR69_SPEI3 (0xFF000000uL) - -#define INTC_ICDIPTR70_SPRI3 (0x000000FFuL) -#define INTC_ICDIPTR70_SPTI3 (0x0000FF00uL) -#define INTC_ICDIPTR70_SPEI4 (0x00FF0000uL) -#define INTC_ICDIPTR70_SPRI4 (0xFF000000uL) - -#define INTC_ICDIPTR71_SPTI4 (0x000000FFuL) -#define INTC_ICDIPTR71_IEBBTD (0x0000FF00uL) -#define INTC_ICDIPTR71_IEBBTERR (0x00FF0000uL) -#define INTC_ICDIPTR71_IEBBTSTA (0xFF000000uL) - -#define INTC_ICDIPTR72_IEBBTV (0x000000FFuL) -#define INTC_ICDIPTR72_ISY (0x0000FF00uL) -#define INTC_ICDIPTR72_IERR (0x00FF0000uL) -#define INTC_ICDIPTR72_ITARG (0xFF000000uL) - -#define INTC_ICDIPTR73_ISEC (0x000000FFuL) -#define INTC_ICDIPTR73_IBUF (0x0000FF00uL) -#define INTC_ICDIPTR73_IREADY (0x00FF0000uL) -#define INTC_ICDIPTR73_FLSTE (0xFF000000uL) - -#define INTC_ICDIPTR74_FLTENDI (0x000000FFuL) -#define INTC_ICDIPTR74_FLTREQ0I (0x0000FF00uL) -#define INTC_ICDIPTR74_FLTREQ1I (0x00FF0000uL) -#define INTC_ICDIPTR74_MMC0 (0xFF000000uL) - -#define INTC_ICDIPTR75_MMC1 (0x000000FFuL) -#define INTC_ICDIPTR75_MMC2 (0x0000FF00uL) -#define INTC_ICDIPTR75_SDHI0_3 (0x00FF0000uL) -#define INTC_ICDIPTR75_SDHI0_0 (0xFF000000uL) - -#define INTC_ICDIPTR76_SDHI0_1 (0x000000FFuL) -#define INTC_ICDIPTR76_SDHI1_3 (0x0000FF00uL) -#define INTC_ICDIPTR76_SDHI1_0 (0x00FF0000uL) -#define INTC_ICDIPTR76_SDHI1_1 (0xFF000000uL) - -#define INTC_ICDIPTR77_ARM (0x000000FFuL) -#define INTC_ICDIPTR77_PRD (0x0000FF00uL) -#define INTC_ICDIPTR77_CUP (0x00FF0000uL) -#define INTC_ICDIPTR77_SCUAI0 (0xFF000000uL) - -#define INTC_ICDIPTR78_SCUAI1 (0x000000FFuL) -#define INTC_ICDIPTR78_SCUFDI0 (0x0000FF00uL) -#define INTC_ICDIPTR78_SCUFDI1 (0x00FF0000uL) -#define INTC_ICDIPTR78_SCUFDI2 (0xFF000000uL) - -#define INTC_ICDIPTR79_SCUFDI3 (0x000000FFuL) -#define INTC_ICDIPTR79_SCUFUI0 (0x0000FF00uL) -#define INTC_ICDIPTR79_SCUFUI1 (0x00FF0000uL) -#define INTC_ICDIPTR79_SCUFUI2 (0xFF000000uL) - -#define INTC_ICDIPTR80_SCUFUI3 (0x000000FFuL) -#define INTC_ICDIPTR80_SCUDVI0 (0x0000FF00uL) -#define INTC_ICDIPTR80_SCUDVI1 (0x00FF0000uL) -#define INTC_ICDIPTR80_SCUDVI2 (0xFF000000uL) - -#define INTC_ICDIPTR81_SCUDVI3 (0x000000FFuL) -#define INTC_ICDIPTR81_MLB_CINT (0x0000FF00uL) -#define INTC_ICDIPTR81_MLB_SINT (0x00FF0000uL) -#define INTC_ICDIPTR81_DRC0 (0xFF000000uL) - -#define INTC_ICDIPTR82_DRC1 (0x000000FFuL) -#define INTC_ICDIPTR82_LINI0_INT_T (0xFF000000uL) - -#define INTC_ICDIPTR83_LINI0_INT_R (0x000000FFuL) -#define INTC_ICDIPTR83_LINI0_INT_S (0x0000FF00uL) -#define INTC_ICDIPTR83_LINI0_INT_M (0x00FF0000uL) -#define INTC_ICDIPTR83_LINI1_INT_T (0xFF000000uL) - -#define INTC_ICDIPTR84_LINI1_INT_R (0x000000FFuL) -#define INTC_ICDIPTR84_LINI1_INT_S (0x0000FF00uL) -#define INTC_ICDIPTR84_LINI1_INT_M (0x00FF0000uL) - -#define INTC_ICDIPTR86_ERI0 (0xFF000000uL) - -#define INTC_ICDIPTR87_RXI0 (0x000000FFuL) -#define INTC_ICDIPTR87_TXI0 (0x0000FF00uL) -#define INTC_ICDIPTR87_TEI0 (0x00FF0000uL) -#define INTC_ICDIPTR87_ERI1 (0xFF000000uL) - -#define INTC_ICDIPTR88_RXI1 (0x000000FFuL) -#define INTC_ICDIPTR88_TXI1 (0x0000FF00uL) -#define INTC_ICDIPTR88_TEI1 (0x00FF0000uL) -#define INTC_ICDIPTR88_AVBI_DATA (0xFF000000uL) - -#define INTC_ICDIPTR89_AVBI_ERROR (0x000000FFuL) -#define INTC_ICDIPTR89_AVBI_MANAGE (0x0000FF00uL) -#define INTC_ICDIPTR89_AVBI_MAC (0x00FF0000uL) -#define INTC_ICDIPTR89_ETHERI (0xFF000000uL) - -#define INTC_ICDIPTR91_CEUI (0x000000FFuL) - -#define INTC_ICDIPTR95_H2XMLB_ERRINT (0x0000FF00uL) -#define INTC_ICDIPTR95_H2XIC1_ERRINT (0x00FF0000uL) -#define INTC_ICDIPTR95_X2HPERI1_ERRINT (0xFF000000uL) - -#define INTC_ICDIPTR96_X2HPERI2_ERRINT (0x000000FFuL) -#define INTC_ICDIPTR96_X2HPERI34_ERRINT (0x0000FF00uL) -#define INTC_ICDIPTR96_X2HPERI5_ERRINT (0x00FF0000uL) -#define INTC_ICDIPTR96_X2HPERI67_ERRINT (0xFF000000uL) - -#define INTC_ICDIPTR97_X2HDBGR_ERRINT (0x000000FFuL) -#define INTC_ICDIPTR97_X2HBSC_ERRINT (0x0000FF00uL) -#define INTC_ICDIPTR97_X2HSPI1_ERRINT (0x00FF0000uL) -#define INTC_ICDIPTR97_X2HSPI2_ERRINT (0xFF000000uL) - -#define INTC_ICDIPTR98_PRRI (0x000000FFuL) -#define INTC_ICDIPTR98_IFEI0 (0x0000FF00uL) -#define INTC_ICDIPTR98_OFFI0 (0x00FF0000uL) -#define INTC_ICDIPTR98_PFVEI0 (0xFF000000uL) - -#define INTC_ICDIPTR99_IFEI1 (0x000000FFuL) -#define INTC_ICDIPTR99_OFFI1 (0x0000FF00uL) -#define INTC_ICDIPTR99_PFVEI1 (0x00FF0000uL) - -#define INTC_ICDIPTR104_TINT0 (0x000000FFuL) -#define INTC_ICDIPTR104_TINT1 (0x0000FF00uL) -#define INTC_ICDIPTR104_TINT2 (0x00FF0000uL) -#define INTC_ICDIPTR104_TINT3 (0xFF000000uL) - -#define INTC_ICDIPTR105_TINT4 (0x000000FFuL) -#define INTC_ICDIPTR105_TINT5 (0x0000FF00uL) -#define INTC_ICDIPTR105_TINT6 (0x00FF0000uL) -#define INTC_ICDIPTR105_TINT7 (0xFF000000uL) - -#define INTC_ICDIPTR106_TINT8 (0x000000FFuL) -#define INTC_ICDIPTR106_TINT9 (0x0000FF00uL) -#define INTC_ICDIPTR106_TINT10 (0x00FF0000uL) -#define INTC_ICDIPTR106_TINT11 (0xFF000000uL) - -#define INTC_ICDIPTR107_TINT12 (0x000000FFuL) -#define INTC_ICDIPTR107_TINT13 (0x0000FF00uL) -#define INTC_ICDIPTR107_TINT14 (0x00FF0000uL) -#define INTC_ICDIPTR107_TINT15 (0xFF000000uL) - -#define INTC_ICDIPTR108_TINT16 (0x000000FFuL) -#define INTC_ICDIPTR108_TINT17 (0x0000FF00uL) -#define INTC_ICDIPTR108_TINT18 (0x00FF0000uL) -#define INTC_ICDIPTR108_TINT19 (0xFF000000uL) - -#define INTC_ICDIPTR109_TINT20 (0x000000FFuL) -#define INTC_ICDIPTR109_TINT21 (0x0000FF00uL) -#define INTC_ICDIPTR109_TINT22 (0x00FF0000uL) -#define INTC_ICDIPTR109_TINT23 (0xFF000000uL) - -#define INTC_ICDIPTR110_TINT24 (0x000000FFuL) -#define INTC_ICDIPTR110_TINT25 (0x0000FF00uL) -#define INTC_ICDIPTR110_TINT26 (0x00FF0000uL) -#define INTC_ICDIPTR110_TINT27 (0xFF000000uL) - -#define INTC_ICDIPTR111_TINT28 (0x000000FFuL) -#define INTC_ICDIPTR111_TINT29 (0x0000FF00uL) -#define INTC_ICDIPTR111_TINT30 (0x00FF0000uL) -#define INTC_ICDIPTR111_TINT31 (0xFF000000uL) - -#define INTC_ICDIPTR112_TINT32 (0x000000FFuL) -#define INTC_ICDIPTR112_TINT33 (0x0000FF00uL) -#define INTC_ICDIPTR112_TINT34 (0x00FF0000uL) -#define INTC_ICDIPTR112_TINT35 (0xFF000000uL) - -#define INTC_ICDIPTR113_TINT36 (0x000000FFuL) -#define INTC_ICDIPTR113_TINT37 (0x0000FF00uL) -#define INTC_ICDIPTR113_TINT38 (0x00FF0000uL) -#define INTC_ICDIPTR113_TINT39 (0xFF000000uL) - -#define INTC_ICDIPTR114_TINT40 (0x000000FFuL) -#define INTC_ICDIPTR114_TINT41 (0x0000FF00uL) -#define INTC_ICDIPTR114_TINT42 (0x00FF0000uL) -#define INTC_ICDIPTR114_TINT43 (0xFF000000uL) - -#define INTC_ICDIPTR115_TINT44 (0x000000FFuL) -#define INTC_ICDIPTR115_TINT45 (0x0000FF00uL) -#define INTC_ICDIPTR115_TINT46 (0x00FF0000uL) -#define INTC_ICDIPTR115_TINT47 (0xFF000000uL) - -#define INTC_ICDIPTR116_TINT48 (0x000000FFuL) -#define INTC_ICDIPTR116_TINT49 (0x0000FF00uL) -#define INTC_ICDIPTR116_TINT50 (0x00FF0000uL) -#define INTC_ICDIPTR116_TINT51 (0xFF000000uL) - -#define INTC_ICDIPTR117_TINT52 (0x000000FFuL) -#define INTC_ICDIPTR117_TINT53 (0x0000FF00uL) -#define INTC_ICDIPTR117_TINT54 (0x00FF0000uL) -#define INTC_ICDIPTR117_TINT55 (0xFF000000uL) - -#define INTC_ICDIPTR118_TINT56 (0x000000FFuL) -#define INTC_ICDIPTR118_TINT57 (0x0000FF00uL) -#define INTC_ICDIPTR118_TINT58 (0x00FF0000uL) -#define INTC_ICDIPTR118_TINT59 (0xFF000000uL) - -#define INTC_ICDIPTR119_TINT60 (0x000000FFuL) -#define INTC_ICDIPTR119_TINT61 (0x0000FF00uL) -#define INTC_ICDIPTR119_TINT62 (0x00FF0000uL) -#define INTC_ICDIPTR119_TINT63 (0xFF000000uL) - -#define INTC_ICDIPTR120_TINT64 (0x000000FFuL) -#define INTC_ICDIPTR120_TINT65 (0x0000FF00uL) -#define INTC_ICDIPTR120_TINT66 (0x00FF0000uL) -#define INTC_ICDIPTR120_TINT67 (0xFF000000uL) - -#define INTC_ICDIPTR121_TINT68 (0x000000FFuL) -#define INTC_ICDIPTR121_TINT69 (0x0000FF00uL) -#define INTC_ICDIPTR121_TINT70 (0x00FF0000uL) -#define INTC_ICDIPTR121_TINT71 (0xFF000000uL) - -#define INTC_ICDIPTR122_TINT72 (0x000000FFuL) -#define INTC_ICDIPTR122_TINT73 (0x0000FF00uL) -#define INTC_ICDIPTR122_TINT74 (0x00FF0000uL) -#define INTC_ICDIPTR122_TINT75 (0xFF000000uL) - -#define INTC_ICDIPTR123_TINT76 (0x000000FFuL) -#define INTC_ICDIPTR123_TINT77 (0x0000FF00uL) -#define INTC_ICDIPTR123_TINT78 (0x00FF0000uL) -#define INTC_ICDIPTR123_TINT79 (0xFF000000uL) - -#define INTC_ICDIPTR124_TINT80 (0x000000FFuL) -#define INTC_ICDIPTR124_TINT81 (0x0000FF00uL) -#define INTC_ICDIPTR124_TINT82 (0x00FF0000uL) -#define INTC_ICDIPTR124_TINT83 (0xFF000000uL) - -#define INTC_ICDIPTR125_TINT84 (0x000000FFuL) -#define INTC_ICDIPTR125_TINT85 (0x0000FF00uL) -#define INTC_ICDIPTR125_TINT86 (0x00FF0000uL) -#define INTC_ICDIPTR125_TINT87 (0xFF000000uL) - -#define INTC_ICDIPTR126_TINT88 (0x000000FFuL) -#define INTC_ICDIPTR126_TINT89 (0x0000FF00uL) -#define INTC_ICDIPTR126_TINT90 (0x00FF0000uL) -#define INTC_ICDIPTR126_TINT91 (0xFF000000uL) - -#define INTC_ICDIPTR127_TINT92 (0x000000FFuL) -#define INTC_ICDIPTR127_TINT93 (0x0000FF00uL) -#define INTC_ICDIPTR127_TINT94 (0x00FF0000uL) -#define INTC_ICDIPTR127_TINT95 (0xFF000000uL) - -#define INTC_ICDIPTR128_TINT96 (0x000000FFuL) -#define INTC_ICDIPTR128_TINT97 (0x0000FF00uL) -#define INTC_ICDIPTR128_TINT98 (0x00FF0000uL) -#define INTC_ICDIPTR128_TINT99 (0xFF000000uL) - -#define INTC_ICDIPTR129_TINT100 (0x000000FFuL) -#define INTC_ICDIPTR129_TINT101 (0x0000FF00uL) -#define INTC_ICDIPTR129_TINT102 (0x00FF0000uL) -#define INTC_ICDIPTR129_TINT103 (0xFF000000uL) - -#define INTC_ICDIPTR130_TINT104 (0x000000FFuL) -#define INTC_ICDIPTR130_TINT105 (0x0000FF00uL) -#define INTC_ICDIPTR130_TINT106 (0x00FF0000uL) -#define INTC_ICDIPTR130_TINT107 (0xFF000000uL) - -#define INTC_ICDIPTR131_TINT108 (0x000000FFuL) -#define INTC_ICDIPTR131_TINT109 (0x0000FF00uL) -#define INTC_ICDIPTR131_TINT110 (0x00FF0000uL) -#define INTC_ICDIPTR131_TINT111 (0xFF000000uL) - -#define INTC_ICDIPTR132_TINT112 (0x000000FFuL) -#define INTC_ICDIPTR132_TINT113 (0x0000FF00uL) -#define INTC_ICDIPTR132_TINT114 (0x00FF0000uL) -#define INTC_ICDIPTR132_TINT115 (0xFF000000uL) - -#define INTC_ICDIPTR133_TINT116 (0x000000FFuL) -#define INTC_ICDIPTR133_TINT117 (0x0000FF00uL) -#define INTC_ICDIPTR133_TINT118 (0x00FF0000uL) -#define INTC_ICDIPTR133_TINT119 (0xFF000000uL) - -#define INTC_ICDIPTR134_TINT120 (0x000000FFuL) -#define INTC_ICDIPTR134_TINT121 (0x0000FF00uL) -#define INTC_ICDIPTR134_TINT122 (0x00FF0000uL) -#define INTC_ICDIPTR134_TINT123 (0xFF000000uL) - -#define INTC_ICDIPTR135_TINT124 (0x000000FFuL) -#define INTC_ICDIPTR135_TINT125 (0x0000FF00uL) -#define INTC_ICDIPTR135_TINT126 (0x00FF0000uL) -#define INTC_ICDIPTR135_TINT127 (0xFF000000uL) - -#define INTC_ICDIPTR136_TINT128 (0x000000FFuL) -#define INTC_ICDIPTR136_TINT129 (0x0000FF00uL) -#define INTC_ICDIPTR136_TINT130 (0x00FF0000uL) -#define INTC_ICDIPTR136_TINT131 (0xFF000000uL) - -#define INTC_ICDIPTR137_TINT132 (0x000000FFuL) -#define INTC_ICDIPTR137_TINT133 (0x0000FF00uL) -#define INTC_ICDIPTR137_TINT134 (0x00FF0000uL) -#define INTC_ICDIPTR137_TINT135 (0xFF000000uL) - -#define INTC_ICDIPTR138_TINT136 (0x000000FFuL) -#define INTC_ICDIPTR138_TINT137 (0x0000FF00uL) -#define INTC_ICDIPTR138_TINT138 (0x00FF0000uL) -#define INTC_ICDIPTR138_TINT139 (0xFF000000uL) - -#define INTC_ICDIPTR139_TINT140 (0x000000FFuL) -#define INTC_ICDIPTR139_TINT141 (0x0000FF00uL) -#define INTC_ICDIPTR139_TINT142 (0x00FF0000uL) -#define INTC_ICDIPTR139_TINT143 (0xFF000000uL) - -#define INTC_ICDIPTR140_TINT144 (0x000000FFuL) -#define INTC_ICDIPTR140_TINT145 (0x0000FF00uL) -#define INTC_ICDIPTR140_TINT146 (0x00FF0000uL) -#define INTC_ICDIPTR140_TINT147 (0xFF000000uL) - -#define INTC_ICDIPTR141_TINT148 (0x000000FFuL) -#define INTC_ICDIPTR141_TINT149 (0x0000FF00uL) -#define INTC_ICDIPTR141_TINT150 (0x00FF0000uL) -#define INTC_ICDIPTR141_TINT151 (0xFF000000uL) - -#define INTC_ICDIPTR142_TINT152 (0x000000FFuL) -#define INTC_ICDIPTR142_TINT153 (0x0000FF00uL) -#define INTC_ICDIPTR142_TINT154 (0x00FF0000uL) -#define INTC_ICDIPTR142_TINT155 (0xFF000000uL) - -#define INTC_ICDIPTR143_TINT156 (0x000000FFuL) -#define INTC_ICDIPTR143_TINT157 (0x0000FF00uL) -#define INTC_ICDIPTR143_TINT158 (0x00FF0000uL) -#define INTC_ICDIPTR143_TINT159 (0xFF000000uL) - -#define INTC_ICDIPTR144_TINT160 (0x000000FFuL) -#define INTC_ICDIPTR144_TINT161 (0x0000FF00uL) -#define INTC_ICDIPTR144_TINT162 (0x00FF0000uL) -#define INTC_ICDIPTR144_TINT163 (0xFF000000uL) - -#define INTC_ICDIPTR145_TINT164 (0x000000FFuL) -#define INTC_ICDIPTR145_TINT165 (0x0000FF00uL) -#define INTC_ICDIPTR145_TINT166 (0x00FF0000uL) -#define INTC_ICDIPTR145_TINT167 (0xFF000000uL) - -#define INTC_ICDIPTR146_TINT168 (0x000000FFuL) -#define INTC_ICDIPTR146_TINT169 (0x0000FF00uL) -#define INTC_ICDIPTR146_TINT170 (0x00FF0000uL) - -#define INTC_ICDICFR0_SW0_0 (0x00000001uL) -#define INTC_ICDICFR0_SW0_1 (0x00000002uL) -#define INTC_ICDICFR0_SW1_0 (0x00000004uL) -#define INTC_ICDICFR0_SW1_1 (0x00000008uL) -#define INTC_ICDICFR0_SW2_0 (0x00000010uL) -#define INTC_ICDICFR0_SW2_1 (0x00000020uL) -#define INTC_ICDICFR0_SW3_0 (0x00000040uL) -#define INTC_ICDICFR0_SW3_1 (0x00000080uL) -#define INTC_ICDICFR0_SW4_0 (0x00000100uL) -#define INTC_ICDICFR0_SW4_1 (0x00000200uL) -#define INTC_ICDICFR0_SW5_0 (0x00000400uL) -#define INTC_ICDICFR0_SW5_1 (0x00000800uL) -#define INTC_ICDICFR0_SW6_0 (0x00001000uL) -#define INTC_ICDICFR0_SW6_1 (0x00002000uL) -#define INTC_ICDICFR0_SW7_0 (0x00004000uL) -#define INTC_ICDICFR0_SW7_1 (0x00008000uL) -#define INTC_ICDICFR0_SW8_0 (0x00010000uL) -#define INTC_ICDICFR0_SW8_1 (0x00020000uL) -#define INTC_ICDICFR0_SW9_0 (0x00040000uL) -#define INTC_ICDICFR0_SW9_1 (0x00080000uL) -#define INTC_ICDICFR0_SW10_0 (0x00100000uL) -#define INTC_ICDICFR0_SW10_1 (0x00200000uL) -#define INTC_ICDICFR0_SW11_0 (0x00400000uL) -#define INTC_ICDICFR0_SW11_1 (0x00800000uL) -#define INTC_ICDICFR0_SW12_0 (0x01000000uL) -#define INTC_ICDICFR0_SW12_1 (0x02000000uL) -#define INTC_ICDICFR0_SW13_0 (0x04000000uL) -#define INTC_ICDICFR0_SW13_1 (0x08000000uL) -#define INTC_ICDICFR0_SW14_0 (0x10000000uL) -#define INTC_ICDICFR0_SW14_1 (0x20000000uL) -#define INTC_ICDICFR0_SW15_0 (0x40000000uL) -#define INTC_ICDICFR0_SW15_1 (0x80000000uL) - -#define INTC_ICDICFR1_PMUIRQ0_0 (0x00000001uL) -#define INTC_ICDICFR1_PMUIRQ0_1 (0x00000002uL) -#define INTC_ICDICFR1_COMMRX0_0 (0x00000004uL) -#define INTC_ICDICFR1_COMMRX0_1 (0x00000008uL) -#define INTC_ICDICFR1_COMMTX0_0 (0x00000010uL) -#define INTC_ICDICFR1_COMMTX0_1 (0x00000020uL) -#define INTC_ICDICFR1_CTIIRQ0_0 (0x00000040uL) -#define INTC_ICDICFR1_CTIIRQ0_1 (0x00000080uL) - -#define INTC_ICDICFR2_IRQ0_0 (0x00000001uL) -#define INTC_ICDICFR2_IRQ0_1 (0x00000002uL) -#define INTC_ICDICFR2_IRQ1_0 (0x00000004uL) -#define INTC_ICDICFR2_IRQ1_1 (0x00000008uL) -#define INTC_ICDICFR2_IRQ2_0 (0x00000010uL) -#define INTC_ICDICFR2_IRQ2_1 (0x00000020uL) -#define INTC_ICDICFR2_IRQ3_0 (0x00000040uL) -#define INTC_ICDICFR2_IRQ3_1 (0x00000080uL) -#define INTC_ICDICFR2_IRQ4_0 (0x00000100uL) -#define INTC_ICDICFR2_IRQ4_1 (0x00000200uL) -#define INTC_ICDICFR2_IRQ5_0 (0x00000400uL) -#define INTC_ICDICFR2_IRQ5_1 (0x00000800uL) -#define INTC_ICDICFR2_IRQ6_0 (0x00001000uL) -#define INTC_ICDICFR2_IRQ6_1 (0x00002000uL) -#define INTC_ICDICFR2_IRQ7_0 (0x00004000uL) -#define INTC_ICDICFR2_IRQ7_1 (0x00008000uL) -#define INTC_ICDICFR2_PL310ERR_0 (0x00010000uL) -#define INTC_ICDICFR2_PL310ERR_1 (0x00020000uL) -#define INTC_ICDICFR2_DMAINT0_0 (0x00040000uL) -#define INTC_ICDICFR2_DMAINT0_1 (0x00080000uL) -#define INTC_ICDICFR2_DMAINT1_0 (0x00100000uL) -#define INTC_ICDICFR2_DMAINT1_1 (0x00200000uL) -#define INTC_ICDICFR2_DMAINT2_0 (0x00400000uL) -#define INTC_ICDICFR2_DMAINT2_1 (0x00800000uL) -#define INTC_ICDICFR2_DMAINT3_0 (0x01000000uL) -#define INTC_ICDICFR2_DMAINT3_1 (0x02000000uL) -#define INTC_ICDICFR2_DMAINT4_0 (0x04000000uL) -#define INTC_ICDICFR2_DMAINT4_1 (0x08000000uL) -#define INTC_ICDICFR2_DMAINT5_0 (0x10000000uL) -#define INTC_ICDICFR2_DMAINT5_1 (0x20000000uL) -#define INTC_ICDICFR2_DMAINT6_0 (0x40000000uL) -#define INTC_ICDICFR2_DMAINT6_1 (0x80000000uL) - -#define INTC_ICDICFR3_DMAINT7_0 (0x00000001uL) -#define INTC_ICDICFR3_DMAINT7_1 (0x00000002uL) -#define INTC_ICDICFR3_DMAINT8_0 (0x00000004uL) -#define INTC_ICDICFR3_DMAINT8_1 (0x00000008uL) -#define INTC_ICDICFR3_DMAINT9_0 (0x00000010uL) -#define INTC_ICDICFR3_DMAINT9_1 (0x00000020uL) -#define INTC_ICDICFR3_DMAINT10_0 (0x00000040uL) -#define INTC_ICDICFR3_DMAINT10_1 (0x00000080uL) -#define INTC_ICDICFR3_DMAINT11_0 (0x00000100uL) -#define INTC_ICDICFR3_DMAINT11_1 (0x00000200uL) -#define INTC_ICDICFR3_DMAINT12_0 (0x00000400uL) -#define INTC_ICDICFR3_DMAINT12_1 (0x00000800uL) -#define INTC_ICDICFR3_DMAINT13_0 (0x00001000uL) -#define INTC_ICDICFR3_DMAINT13_1 (0x00002000uL) -#define INTC_ICDICFR3_DMAINT14_0 (0x00004000uL) -#define INTC_ICDICFR3_DMAINT14_1 (0x00008000uL) -#define INTC_ICDICFR3_DMAINT15_0 (0x00010000uL) -#define INTC_ICDICFR3_DMAINT15_1 (0x00020000uL) -#define INTC_ICDICFR3_DMAERR_0 (0x00040000uL) -#define INTC_ICDICFR3_DMAERR_1 (0x00080000uL) - -#define INTC_ICDICFR4_USBI0_0 (0x00040000uL) -#define INTC_ICDICFR4_USBI0_1 (0x00080000uL) -#define INTC_ICDICFR4_USBI1_0 (0x00100000uL) -#define INTC_ICDICFR4_USBI1_1 (0x00200000uL) -#define INTC_ICDICFR4_S0_VI_VSYNC0_0 (0x00400000uL) -#define INTC_ICDICFR4_S0_VI_VSYNC0_1 (0x00800000uL) -#define INTC_ICDICFR4_S0_LO_VSYNC0_0 (0x01000000uL) -#define INTC_ICDICFR4_S0_LO_VSYNC0_1 (0x02000000uL) -#define INTC_ICDICFR4_S0_VSYNCERR0_0 (0x04000000uL) -#define INTC_ICDICFR4_S0_VSYNCERR0_1 (0x08000000uL) -#define INTC_ICDICFR4_GR3_VLINE0_0 (0x10000000uL) -#define INTC_ICDICFR4_GR3_VLINE0_1 (0x20000000uL) -#define INTC_ICDICFR4_S0_VFIELD0_0 (0x40000000uL) -#define INTC_ICDICFR4_S0_VFIELD0_1 (0x80000000uL) - -#define INTC_ICDICFR5_IV1_VBUFERR0_0 (0x00000001uL) -#define INTC_ICDICFR5_IV1_VBUFERR0_1 (0x00000002uL) -#define INTC_ICDICFR5_IV3_VBUFERR0_0 (0x00000004uL) -#define INTC_ICDICFR5_IV3_VBUFERR0_1 (0x00000008uL) -#define INTC_ICDICFR5_IV5_VBUFERR0_0 (0x00000010uL) -#define INTC_ICDICFR5_IV5_VBUFERR0_1 (0x00000020uL) -#define INTC_ICDICFR5_IV6_VBUFERR0_0 (0x00000040uL) -#define INTC_ICDICFR5_IV6_VBUFERR0_1 (0x00000080uL) -#define INTC_ICDICFR5_S0_WLINE0_0 (0x00000100uL) -#define INTC_ICDICFR5_S0_WLINE0_1 (0x00000200uL) -#define INTC_ICDICFR5_S1_VI_VSYNC0_0 (0x00000400uL) -#define INTC_ICDICFR5_S1_VI_VSYNC0_1 (0x00000800uL) -#define INTC_ICDICFR5_S1_LO_VSYNC0_0 (0x00001000uL) -#define INTC_ICDICFR5_S1_LO_VSYNC0_1 (0x00002000uL) -#define INTC_ICDICFR5_S1_VSYNCERR0_0 (0x00004000uL) -#define INTC_ICDICFR5_S1_VSYNCERR0_1 (0x00008000uL) -#define INTC_ICDICFR5_S1_VFIELD0_0 (0x00010000uL) -#define INTC_ICDICFR5_S1_VFIELD0_1 (0x00020000uL) -#define INTC_ICDICFR5_IV2_VBUFERR0_0 (0x00040000uL) -#define INTC_ICDICFR5_IV2_VBUFERR0_1 (0x00080000uL) -#define INTC_ICDICFR5_IV4_VBUFERR0_0 (0x00100000uL) -#define INTC_ICDICFR5_IV4_VBUFERR0_1 (0x00200000uL) -#define INTC_ICDICFR5_S1_WLINE0_0 (0x00400000uL) -#define INTC_ICDICFR5_S1_WLINE0_1 (0x00800000uL) -#define INTC_ICDICFR5_OIR_VI_VSYNC0_0 (0x01000000uL) -#define INTC_ICDICFR5_OIR_VI_VSYNC0_1 (0x02000000uL) -#define INTC_ICDICFR5_OIR_LO_VSYNC0_0 (0x04000000uL) -#define INTC_ICDICFR5_OIR_LO_VSYNC0_1 (0x08000000uL) -#define INTC_ICDICFR5_OIR_VSYNCERR0_0 (0x10000000uL) -#define INTC_ICDICFR5_OIR_VSYNCERR0_1 (0x20000000uL) -#define INTC_ICDICFR5_OIR_VFIELD0_0 (0x40000000uL) -#define INTC_ICDICFR5_OIR_VFIELD0_1 (0x80000000uL) - -#define INTC_ICDICFR6_IV7_VBUFERR0_0 (0x00000001uL) -#define INTC_ICDICFR6_IV7_VBUFERR0_1 (0x00000002uL) -#define INTC_ICDICFR6_IV8_VBUFERR0_0 (0x00000004uL) -#define INTC_ICDICFR6_IV8_VBUFERR0_1 (0x00000008uL) -#define INTC_ICDICFR6_S0_VI_VSYNC1_0 (0x00000040uL) -#define INTC_ICDICFR6_S0_VI_VSYNC1_1 (0x00000080uL) -#define INTC_ICDICFR6_S0_LO_VSYNC1_0 (0x00000100uL) -#define INTC_ICDICFR6_S0_LO_VSYNC1_1 (0x00000200uL) -#define INTC_ICDICFR6_S0_VSYNCERR1_0 (0x00000400uL) -#define INTC_ICDICFR6_S0_VSYNCERR1_1 (0x00000800uL) -#define INTC_ICDICFR6_GR3_VLINE1_0 (0x00001000uL) -#define INTC_ICDICFR6_GR3_VLINE1_1 (0x00002000uL) -#define INTC_ICDICFR6_S0_VFIELD1_0 (0x00004000uL) -#define INTC_ICDICFR6_S0_VFIELD1_1 (0x00008000uL) -#define INTC_ICDICFR6_IV1_VBUFERR1_0 (0x00010000uL) -#define INTC_ICDICFR6_IV1_VBUFERR1_1 (0x00020000uL) -#define INTC_ICDICFR6_IV3_VBUFERR1_0 (0x00040000uL) -#define INTC_ICDICFR6_IV3_VBUFERR1_1 (0x00080000uL) -#define INTC_ICDICFR6_IV5_VBUFERR1_0 (0x00100000uL) -#define INTC_ICDICFR6_IV5_VBUFERR1_1 (0x00200000uL) -#define INTC_ICDICFR6_IV6_VBUFERR1_0 (0x00400000uL) -#define INTC_ICDICFR6_IV6_VBUFERR1_1 (0x00800000uL) -#define INTC_ICDICFR6_S0_WLINE1_0 (0x01000000uL) -#define INTC_ICDICFR6_S0_WLINE1_1 (0x02000000uL) -#define INTC_ICDICFR6_S1_VI_VSYNC1_0 (0x04000000uL) -#define INTC_ICDICFR6_S1_VI_VSYNC1_1 (0x08000000uL) -#define INTC_ICDICFR6_S1_LO_VSYNC1_0 (0x10000000uL) -#define INTC_ICDICFR6_S1_LO_VSYNC1_1 (0x20000000uL) -#define INTC_ICDICFR6_S1_VSYNCERR1_0 (0x40000000uL) -#define INTC_ICDICFR6_S1_VSYNCERR1_1 (0x80000000uL) - -#define INTC_ICDICFR7_S1_VFIELD1_0 (0x00000001uL) -#define INTC_ICDICFR7_S1_VFIELD1_1 (0x00000002uL) -#define INTC_ICDICFR7_IV2_VBUFERR1_0 (0x00000004uL) -#define INTC_ICDICFR7_IV2_VBUFERR1_1 (0x00000008uL) -#define INTC_ICDICFR7_IV4_VBUFERR1_0 (0x00000010uL) -#define INTC_ICDICFR7_IV4_VBUFERR1_1 (0x00000020uL) -#define INTC_ICDICFR7_S1_WLINE1_0 (0x00000040uL) -#define INTC_ICDICFR7_S1_WLINE1_1 (0x00000080uL) -#define INTC_ICDICFR7_OIR_VI_VSYNC1_0 (0x00000100uL) -#define INTC_ICDICFR7_OIR_VI_VSYNC1_1 (0x00000200uL) -#define INTC_ICDICFR7_OIR_LO_VSYNC1_0 (0x00000400uL) -#define INTC_ICDICFR7_OIR_LO_VSYNC1_1 (0x00000800uL) -#define INTC_ICDICFR7_OIR_VLINE1_0 (0x00001000uL) -#define INTC_ICDICFR7_OIR_VLINE1_1 (0x00002000uL) -#define INTC_ICDICFR7_OIR_VFIELD1_0 (0x00004000uL) -#define INTC_ICDICFR7_OIR_VFIELD1_1 (0x00008000uL) -#define INTC_ICDICFR7_IV7_VBUFERR1_0 (0x00010000uL) -#define INTC_ICDICFR7_IV7_VBUFERR1_1 (0x00020000uL) -#define INTC_ICDICFR7_IV8_VBUFERR1_0 (0x00040000uL) -#define INTC_ICDICFR7_IV8_VBUFERR1_1 (0x00080000uL) -#define INTC_ICDICFR7_IMRDI_0 (0x00400000uL) -#define INTC_ICDICFR7_IMRDI_1 (0x00800000uL) -#define INTC_ICDICFR7_IMR2I0_0 (0x01000000uL) -#define INTC_ICDICFR7_IMR2I0_1 (0x02000000uL) -#define INTC_ICDICFR7_IMR2I1_0 (0x04000000uL) -#define INTC_ICDICFR7_IMR2I1_1 (0x08000000uL) -#define INTC_ICDICFR7_JEDI_0 (0x10000000uL) -#define INTC_ICDICFR7_JEDI_1 (0x20000000uL) -#define INTC_ICDICFR7_JDTI_0 (0x40000000uL) -#define INTC_ICDICFR7_JDTI_1 (0x80000000uL) - -#define INTC_ICDICFR8_CMP0_0 (0x00000001uL) -#define INTC_ICDICFR8_CMP0_1 (0x00000002uL) -#define INTC_ICDICFR8_CMP1_0 (0x00000004uL) -#define INTC_ICDICFR8_CMP1_1 (0x00000008uL) -#define INTC_ICDICFR8_INT0_0 (0x00000010uL) -#define INTC_ICDICFR8_INT0_1 (0x00000020uL) -#define INTC_ICDICFR8_INT1_0 (0x00000040uL) -#define INTC_ICDICFR8_INT1_1 (0x00000080uL) -#define INTC_ICDICFR8_INT2_0 (0x00000100uL) -#define INTC_ICDICFR8_INT2_1 (0x00000200uL) -#define INTC_ICDICFR8_INT3_0 (0x00000400uL) -#define INTC_ICDICFR8_INT3_1 (0x00000800uL) -#define INTC_ICDICFR8_OSTM0TINT_0 (0x00001000uL) -#define INTC_ICDICFR8_OSTM0TINT_1 (0x00002000uL) -#define INTC_ICDICFR8_OSTM1TINT_0 (0x00004000uL) -#define INTC_ICDICFR8_OSTM1TINT_1 (0x00008000uL) -#define INTC_ICDICFR8_CMI_0 (0x00010000uL) -#define INTC_ICDICFR8_CMI_1 (0x00020000uL) -#define INTC_ICDICFR8_WTOUT_0 (0x00040000uL) -#define INTC_ICDICFR8_WTOUT_1 (0x00080000uL) -#define INTC_ICDICFR8_ITI_0 (0x00100000uL) -#define INTC_ICDICFR8_ITI_1 (0x00200000uL) -#define INTC_ICDICFR8_TGI0A_0 (0x00400000uL) -#define INTC_ICDICFR8_TGI0A_1 (0x00800000uL) -#define INTC_ICDICFR8_TGI0B_0 (0x01000000uL) -#define INTC_ICDICFR8_TGI0B_1 (0x02000000uL) -#define INTC_ICDICFR8_TGI0C_0 (0x04000000uL) -#define INTC_ICDICFR8_TGI0C_1 (0x08000000uL) -#define INTC_ICDICFR8_TGI0D_0 (0x10000000uL) -#define INTC_ICDICFR8_TGI0D_1 (0x20000000uL) -#define INTC_ICDICFR8_TGI0V_0 (0x40000000uL) -#define INTC_ICDICFR8_TGI0V_1 (0x80000000uL) - -#define INTC_ICDICFR9_TGI0E_0 (0x00000001uL) -#define INTC_ICDICFR9_TGI0E_1 (0x00000002uL) -#define INTC_ICDICFR9_TGI0F_0 (0x00000004uL) -#define INTC_ICDICFR9_TGI0F_1 (0x00000008uL) -#define INTC_ICDICFR9_TGI1A_0 (0x00000010uL) -#define INTC_ICDICFR9_TGI1A_1 (0x00000020uL) -#define INTC_ICDICFR9_TGI1B_0 (0x00000040uL) -#define INTC_ICDICFR9_TGI1B_1 (0x00000080uL) -#define INTC_ICDICFR9_TGI1V_0 (0x00000100uL) -#define INTC_ICDICFR9_TGI1V_1 (0x00000200uL) -#define INTC_ICDICFR9_TGI1U_0 (0x00000400uL) -#define INTC_ICDICFR9_TGI1U_1 (0x00000800uL) -#define INTC_ICDICFR9_TGI2A_0 (0x00001000uL) -#define INTC_ICDICFR9_TGI2A_1 (0x00002000uL) -#define INTC_ICDICFR9_TGI2B_0 (0x00004000uL) -#define INTC_ICDICFR9_TGI2B_1 (0x00008000uL) -#define INTC_ICDICFR9_TGI2V_0 (0x00010000uL) -#define INTC_ICDICFR9_TGI2V_1 (0x00020000uL) -#define INTC_ICDICFR9_TGI2U_0 (0x00040000uL) -#define INTC_ICDICFR9_TGI2U_1 (0x00080000uL) -#define INTC_ICDICFR9_TGI3A_0 (0x00100000uL) -#define INTC_ICDICFR9_TGI3A_1 (0x00200000uL) -#define INTC_ICDICFR9_TGI3B_0 (0x00400000uL) -#define INTC_ICDICFR9_TGI3B_1 (0x00800000uL) -#define INTC_ICDICFR9_TGI3C_0 (0x01000000uL) -#define INTC_ICDICFR9_TGI3C_1 (0x02000000uL) -#define INTC_ICDICFR9_TGI3D_0 (0x04000000uL) -#define INTC_ICDICFR9_TGI3D_1 (0x08000000uL) -#define INTC_ICDICFR9_TGI3V_0 (0x10000000uL) -#define INTC_ICDICFR9_TGI3V_1 (0x20000000uL) -#define INTC_ICDICFR9_TGI4A_0 (0x40000000uL) -#define INTC_ICDICFR9_TGI4A_1 (0x80000000uL) - -#define INTC_ICDICFR10_TGI4B_0 (0x00000001uL) -#define INTC_ICDICFR10_TGI4B_1 (0x00000002uL) -#define INTC_ICDICFR10_TGI4C_0 (0x00000004uL) -#define INTC_ICDICFR10_TGI4C_1 (0x00000008uL) -#define INTC_ICDICFR10_TGI4D_0 (0x00000010uL) -#define INTC_ICDICFR10_TGI4D_1 (0x00000020uL) -#define INTC_ICDICFR10_TGI4V_0 (0x00000040uL) -#define INTC_ICDICFR10_TGI4V_1 (0x00000080uL) -#define INTC_ICDICFR10_CMI1_0 (0x00000100uL) -#define INTC_ICDICFR10_CMI1_1 (0x00000200uL) -#define INTC_ICDICFR10_CMI2_0 (0x00000400uL) -#define INTC_ICDICFR10_CMI2_1 (0x00000800uL) -#define INTC_ICDICFR10_SGDEI0_0 (0x00001000uL) -#define INTC_ICDICFR10_SGDEI0_1 (0x00002000uL) -#define INTC_ICDICFR10_SGDEI1_0 (0x00004000uL) -#define INTC_ICDICFR10_SGDEI1_1 (0x00008000uL) -#define INTC_ICDICFR10_SGDEI2_0 (0x00010000uL) -#define INTC_ICDICFR10_SGDEI2_1 (0x00020000uL) -#define INTC_ICDICFR10_SGDEI3_0 (0x00040000uL) -#define INTC_ICDICFR10_SGDEI3_1 (0x00080000uL) -#define INTC_ICDICFR10_ADI_0 (0x00100000uL) -#define INTC_ICDICFR10_ADI_1 (0x00200000uL) -#define INTC_ICDICFR10_LMTI_0 (0x00400000uL) -#define INTC_ICDICFR10_LMTI_1 (0x00800000uL) -#define INTC_ICDICFR10_SSII0_0 (0x01000000uL) -#define INTC_ICDICFR10_SSII0_1 (0x02000000uL) -#define INTC_ICDICFR10_SSIRXI0_0 (0x04000000uL) -#define INTC_ICDICFR10_SSIRXI0_1 (0x08000000uL) -#define INTC_ICDICFR10_SSITXI0_0 (0x10000000uL) -#define INTC_ICDICFR10_SSITXI0_1 (0x20000000uL) -#define INTC_ICDICFR10_SSII1_0 (0x40000000uL) -#define INTC_ICDICFR10_SSII1_1 (0x80000000uL) - -#define INTC_ICDICFR11_SSIRXI1_0 (0x00000001uL) -#define INTC_ICDICFR11_SSIRXI1_1 (0x00000002uL) -#define INTC_ICDICFR11_SSITXI1_0 (0x00000004uL) -#define INTC_ICDICFR11_SSITXI1_1 (0x00000008uL) -#define INTC_ICDICFR11_SSII2_0 (0x00000010uL) -#define INTC_ICDICFR11_SSII2_1 (0x00000020uL) -#define INTC_ICDICFR11_SSIRTI2_0 (0x00000040uL) -#define INTC_ICDICFR11_SSIRTI2_1 (0x00000080uL) -#define INTC_ICDICFR11_SSII3_0 (0x00000100uL) -#define INTC_ICDICFR11_SSII3_1 (0x00000200uL) -#define INTC_ICDICFR11_SSIRXI3_0 (0x00000400uL) -#define INTC_ICDICFR11_SSIRXI3_1 (0x00000800uL) -#define INTC_ICDICFR11_SSITXI3_0 (0x00001000uL) -#define INTC_ICDICFR11_SSITXI3_1 (0x00002000uL) -#define INTC_ICDICFR11_SSII4_0 (0x00004000uL) -#define INTC_ICDICFR11_SSII4_1 (0x00008000uL) -#define INTC_ICDICFR11_SSIRTI4_0 (0x00010000uL) -#define INTC_ICDICFR11_SSIRTI4_1 (0x00020000uL) -#define INTC_ICDICFR11_SSII5_0 (0x00040000uL) -#define INTC_ICDICFR11_SSII5_1 (0x00080000uL) -#define INTC_ICDICFR11_SSIRXI5_0 (0x00100000uL) -#define INTC_ICDICFR11_SSIRXI5_1 (0x00200000uL) -#define INTC_ICDICFR11_SSITXI5_0 (0x00400000uL) -#define INTC_ICDICFR11_SSITXI5_1 (0x00800000uL) -#define INTC_ICDICFR11_SPDIFI_0 (0x01000000uL) -#define INTC_ICDICFR11_SPDIFI_1 (0x02000000uL) -#define INTC_ICDICFR11_INTIICTEI0_0 (0x04000000uL) -#define INTC_ICDICFR11_INTIICTEI0_1 (0x08000000uL) -#define INTC_ICDICFR11_INTIICRI0_0 (0x10000000uL) -#define INTC_ICDICFR11_INTIICRI0_1 (0x20000000uL) -#define INTC_ICDICFR11_INTIICTI0_0 (0x40000000uL) -#define INTC_ICDICFR11_INTIICTI0_1 (0x80000000uL) - -#define INTC_ICDICFR12_INTIICSPI0_0 (0x00000001uL) -#define INTC_ICDICFR12_INTIICSPI0_1 (0x00000002uL) -#define INTC_ICDICFR12_INTIICSTI0_0 (0x00000004uL) -#define INTC_ICDICFR12_INTIICSTI0_1 (0x00000008uL) -#define INTC_ICDICFR12_INTIICNAKI0_0 (0x00000010uL) -#define INTC_ICDICFR12_INTIICNAKI0_1 (0x00000020uL) -#define INTC_ICDICFR12_INTIICALI0_0 (0x00000040uL) -#define INTC_ICDICFR12_INTIICALI0_1 (0x00000080uL) -#define INTC_ICDICFR12_INTIICTMOI0_0 (0x00000100uL) -#define INTC_ICDICFR12_INTIICTMOI0_1 (0x00000200uL) -#define INTC_ICDICFR12_INTIICTEI1_0 (0x00000400uL) -#define INTC_ICDICFR12_INTIICTEI1_1 (0x00000800uL) -#define INTC_ICDICFR12_INTIICRI1_0 (0x00001000uL) -#define INTC_ICDICFR12_INTIICRI1_1 (0x00002000uL) -#define INTC_ICDICFR12_INTIICTI1_0 (0x00004000uL) -#define INTC_ICDICFR12_INTIICTI1_1 (0x00008000uL) -#define INTC_ICDICFR12_INTIICSPI1_0 (0x00010000uL) -#define INTC_ICDICFR12_INTIICSPI1_1 (0x00020000uL) -#define INTC_ICDICFR12_INTIICSTI1_0 (0x00040000uL) -#define INTC_ICDICFR12_INTIICSTI1_1 (0x00080000uL) -#define INTC_ICDICFR12_INTIICNAKI1_0 (0x00100000uL) -#define INTC_ICDICFR12_INTIICNAKI1_1 (0x00200000uL) -#define INTC_ICDICFR12_INTIICALI1_0 (0x00400000uL) -#define INTC_ICDICFR12_INTIICALI1_1 (0x00800000uL) -#define INTC_ICDICFR12_INTIICTMOI1_0 (0x01000000uL) -#define INTC_ICDICFR12_INTIICTMOI1_1 (0x02000000uL) -#define INTC_ICDICFR12_INTIICTEI2_0 (0x04000000uL) -#define INTC_ICDICFR12_INTIICTEI2_1 (0x08000000uL) -#define INTC_ICDICFR12_INTIICRI2_0 (0x10000000uL) -#define INTC_ICDICFR12_INTIICRI2_1 (0x20000000uL) -#define INTC_ICDICFR12_INTIICTI2_0 (0x40000000uL) -#define INTC_ICDICFR12_INTIICTI2_1 (0x80000000uL) - -#define INTC_ICDICFR13_INTIICSPI2_0 (0x00000001uL) -#define INTC_ICDICFR13_INTIICSPI2_1 (0x00000002uL) -#define INTC_ICDICFR13_INTIICSTI2_0 (0x00000004uL) -#define INTC_ICDICFR13_INTIICSTI2_1 (0x00000008uL) -#define INTC_ICDICFR13_INTIICNAKI2_0 (0x00000010uL) -#define INTC_ICDICFR13_INTIICNAKI2_1 (0x00000020uL) -#define INTC_ICDICFR13_INTIICALI2_0 (0x00000040uL) -#define INTC_ICDICFR13_INTIICALI2_1 (0x00000080uL) -#define INTC_ICDICFR13_INTIICTMOI2_0 (0x00000100uL) -#define INTC_ICDICFR13_INTIICTMOI2_1 (0x00000200uL) -#define INTC_ICDICFR13_INTIICTEI3_0 (0x00000400uL) -#define INTC_ICDICFR13_INTIICTEI3_1 (0x00000800uL) -#define INTC_ICDICFR13_INTIICRI3_0 (0x00001000uL) -#define INTC_ICDICFR13_INTIICRI3_1 (0x00002000uL) -#define INTC_ICDICFR13_INTIICTI3_0 (0x00004000uL) -#define INTC_ICDICFR13_INTIICTI3_1 (0x00008000uL) -#define INTC_ICDICFR13_INTIICSPI3_0 (0x00010000uL) -#define INTC_ICDICFR13_INTIICSPI3_1 (0x00020000uL) -#define INTC_ICDICFR13_INTIICSTI3_0 (0x00040000uL) -#define INTC_ICDICFR13_INTIICSTI3_1 (0x00080000uL) -#define INTC_ICDICFR13_INTIICNAKI3_0 (0x00100000uL) -#define INTC_ICDICFR13_INTIICNAKI3_1 (0x00200000uL) -#define INTC_ICDICFR13_INTIICALI3_0 (0x00400000uL) -#define INTC_ICDICFR13_INTIICALI3_1 (0x00800000uL) -#define INTC_ICDICFR13_INTIICTMOI3_0 (0x01000000uL) -#define INTC_ICDICFR13_INTIICTMOI3_1 (0x02000000uL) -#define INTC_ICDICFR13_BRI0_0 (0x04000000uL) -#define INTC_ICDICFR13_BRI0_1 (0x08000000uL) -#define INTC_ICDICFR13_ERI0_0 (0x10000000uL) -#define INTC_ICDICFR13_ERI0_1 (0x20000000uL) -#define INTC_ICDICFR13_RXI0_0 (0x40000000uL) -#define INTC_ICDICFR13_RXI0_1 (0x80000000uL) - -#define INTC_ICDICFR14_TXI0_0 (0x00000001uL) -#define INTC_ICDICFR14_TXI0_1 (0x00000002uL) -#define INTC_ICDICFR14_BRI1_0 (0x00000004uL) -#define INTC_ICDICFR14_BRI1_1 (0x00000008uL) -#define INTC_ICDICFR14_ERI1_0 (0x00000010uL) -#define INTC_ICDICFR14_ERI1_1 (0x00000020uL) -#define INTC_ICDICFR14_RXI1_0 (0x00000040uL) -#define INTC_ICDICFR14_RXI1_1 (0x00000080uL) -#define INTC_ICDICFR14_TXI1_0 (0x00000100uL) -#define INTC_ICDICFR14_TXI1_1 (0x00000200uL) -#define INTC_ICDICFR14_BRI2_0 (0x00000400uL) -#define INTC_ICDICFR14_BRI2_1 (0x00000800uL) -#define INTC_ICDICFR14_ERI2_0 (0x00001000uL) -#define INTC_ICDICFR14_ERI2_1 (0x00002000uL) -#define INTC_ICDICFR14_RXI2_0 (0x00004000uL) -#define INTC_ICDICFR14_RXI2_1 (0x00008000uL) -#define INTC_ICDICFR14_TXI2_0 (0x00010000uL) -#define INTC_ICDICFR14_TXI2_1 (0x00020000uL) -#define INTC_ICDICFR14_BRI3_0 (0x00040000uL) -#define INTC_ICDICFR14_BRI3_1 (0x00080000uL) -#define INTC_ICDICFR14_ERI3_0 (0x00100000uL) -#define INTC_ICDICFR14_ERI3_1 (0x00200000uL) -#define INTC_ICDICFR14_RXI3_0 (0x00400000uL) -#define INTC_ICDICFR14_RXI3_1 (0x00800000uL) -#define INTC_ICDICFR14_TXI3_0 (0x01000000uL) -#define INTC_ICDICFR14_TXI3_1 (0x02000000uL) -#define INTC_ICDICFR14_BRI4_0 (0x04000000uL) -#define INTC_ICDICFR14_BRI4_1 (0x08000000uL) -#define INTC_ICDICFR14_ERI4_0 (0x10000000uL) -#define INTC_ICDICFR14_ERI4_1 (0x20000000uL) -#define INTC_ICDICFR14_RXI4_0 (0x40000000uL) -#define INTC_ICDICFR14_RXI4_1 (0x80000000uL) - -#define INTC_ICDICFR15_TXI4_0 (0x00000001uL) -#define INTC_ICDICFR15_TXI4_1 (0x00000002uL) -#define INTC_ICDICFR15_BRI5_0 (0x00000004uL) -#define INTC_ICDICFR15_BRI5_1 (0x00000008uL) -#define INTC_ICDICFR15_ERI5_0 (0x00000010uL) -#define INTC_ICDICFR15_ERI5_1 (0x00000020uL) -#define INTC_ICDICFR15_RXI5_0 (0x00000040uL) -#define INTC_ICDICFR15_RXI5_1 (0x00000080uL) -#define INTC_ICDICFR15_TXI5_0 (0x00000100uL) -#define INTC_ICDICFR15_TXI5_1 (0x00000200uL) -#define INTC_ICDICFR15_BRI6_0 (0x00000400uL) -#define INTC_ICDICFR15_BRI6_1 (0x00000800uL) -#define INTC_ICDICFR15_ERI6_0 (0x00001000uL) -#define INTC_ICDICFR15_ERI6_1 (0x00002000uL) -#define INTC_ICDICFR15_RXI6_0 (0x00004000uL) -#define INTC_ICDICFR15_RXI6_1 (0x00008000uL) -#define INTC_ICDICFR15_TXI6_0 (0x00010000uL) -#define INTC_ICDICFR15_TXI6_1 (0x00020000uL) -#define INTC_ICDICFR15_BRI7_0 (0x00040000uL) -#define INTC_ICDICFR15_BRI7_1 (0x00080000uL) -#define INTC_ICDICFR15_ERI7_0 (0x00100000uL) -#define INTC_ICDICFR15_ERI7_1 (0x00200000uL) -#define INTC_ICDICFR15_RXI7_0 (0x00400000uL) -#define INTC_ICDICFR15_RXI7_1 (0x00800000uL) -#define INTC_ICDICFR15_TXI7_0 (0x01000000uL) -#define INTC_ICDICFR15_TXI7_1 (0x02000000uL) -#define INTC_ICDICFR15_INTRCANGERR_0 (0x04000000uL) -#define INTC_ICDICFR15_INTRCANGERR_1 (0x08000000uL) -#define INTC_ICDICFR15_INTRCANGRECC_0 (0x10000000uL) -#define INTC_ICDICFR15_INTRCANGRECC_1 (0x20000000uL) -#define INTC_ICDICFR15_INTRCAN0REC_0 (0x40000000uL) -#define INTC_ICDICFR15_INTRCAN0REC_1 (0x80000000uL) - -#define INTC_ICDICFR16_INTRCAN0ERR_0 (0x00000001uL) -#define INTC_ICDICFR16_INTRCAN0ERR_1 (0x00000002uL) -#define INTC_ICDICFR16_INTRCAN0TRX_0 (0x00000004uL) -#define INTC_ICDICFR16_INTRCAN0TRX_1 (0x00000008uL) -#define INTC_ICDICFR16_INTRCAN1REC_0 (0x00000010uL) -#define INTC_ICDICFR16_INTRCAN1REC_1 (0x00000020uL) -#define INTC_ICDICFR16_INTRCAN1ERR_0 (0x00000040uL) -#define INTC_ICDICFR16_INTRCAN1ERR_1 (0x00000080uL) -#define INTC_ICDICFR16_INTRCAN1TRX_0 (0x00000100uL) -#define INTC_ICDICFR16_INTRCAN1TRX_1 (0x00000200uL) -#define INTC_ICDICFR16_INTRCAN2REC_0 (0x00000400uL) -#define INTC_ICDICFR16_INTRCAN2REC_1 (0x00000800uL) -#define INTC_ICDICFR16_INTRCAN2ERR_0 (0x00001000uL) -#define INTC_ICDICFR16_INTRCAN2ERR_1 (0x00002000uL) -#define INTC_ICDICFR16_INTRCAN2TRX_0 (0x00004000uL) -#define INTC_ICDICFR16_INTRCAN2TRX_1 (0x00008000uL) -#define INTC_ICDICFR16_INTRCAN3REC_0 (0x00010000uL) -#define INTC_ICDICFR16_INTRCAN3REC_1 (0x00020000uL) -#define INTC_ICDICFR16_INTRCAN3ERR_0 (0x00040000uL) -#define INTC_ICDICFR16_INTRCAN3ERR_1 (0x00080000uL) -#define INTC_ICDICFR16_INTRCAN3TRX_0 (0x00100000uL) -#define INTC_ICDICFR16_INTRCAN3TRX_1 (0x00200000uL) -#define INTC_ICDICFR16_INTRCAN4REC_0 (0x00400000uL) -#define INTC_ICDICFR16_INTRCAN4REC_1 (0x00800000uL) -#define INTC_ICDICFR16_INTRCAN4ERR_0 (0x01000000uL) -#define INTC_ICDICFR16_INTRCAN4ERR_1 (0x02000000uL) -#define INTC_ICDICFR16_INTRCAN4TRX_0 (0x04000000uL) -#define INTC_ICDICFR16_INTRCAN4TRX_1 (0x08000000uL) -#define INTC_ICDICFR16_SPEI0_0 (0x10000000uL) -#define INTC_ICDICFR16_SPEI0_1 (0x20000000uL) -#define INTC_ICDICFR16_SPRI0_0 (0x40000000uL) -#define INTC_ICDICFR16_SPRI0_1 (0x80000000uL) - -#define INTC_ICDICFR17_SPTI0_0 (0x00000001uL) -#define INTC_ICDICFR17_SPTI0_1 (0x00000002uL) -#define INTC_ICDICFR17_SPEI1_0 (0x00000004uL) -#define INTC_ICDICFR17_SPEI1_1 (0x00000008uL) -#define INTC_ICDICFR17_SPRI1_0 (0x00000010uL) -#define INTC_ICDICFR17_SPRI1_1 (0x00000020uL) -#define INTC_ICDICFR17_SPTI1_0 (0x00000040uL) -#define INTC_ICDICFR17_SPTI1_1 (0x00000080uL) -#define INTC_ICDICFR17_SPEI2_0 (0x00000100uL) -#define INTC_ICDICFR17_SPEI2_1 (0x00000200uL) -#define INTC_ICDICFR17_SPRI2_0 (0x00000400uL) -#define INTC_ICDICFR17_SPRI2_1 (0x00000800uL) -#define INTC_ICDICFR17_SPTI2_0 (0x00001000uL) -#define INTC_ICDICFR17_SPTI2_1 (0x00002000uL) -#define INTC_ICDICFR17_SPEI3_0 (0x00004000uL) -#define INTC_ICDICFR17_SPEI3_1 (0x00008000uL) -#define INTC_ICDICFR17_SPRI3_0 (0x00010000uL) -#define INTC_ICDICFR17_SPRI3_1 (0x00020000uL) -#define INTC_ICDICFR17_SPTI3_0 (0x00040000uL) -#define INTC_ICDICFR17_SPTI3_1 (0x00080000uL) -#define INTC_ICDICFR17_SPEI4_0 (0x00100000uL) -#define INTC_ICDICFR17_SPEI4_1 (0x00200000uL) -#define INTC_ICDICFR17_SPRI4_0 (0x00400000uL) -#define INTC_ICDICFR17_SPRI4_1 (0x00800000uL) -#define INTC_ICDICFR17_SPTI4_0 (0x01000000uL) -#define INTC_ICDICFR17_SPTI4_1 (0x02000000uL) -#define INTC_ICDICFR17_IEBBTD_0 (0x04000000uL) -#define INTC_ICDICFR17_IEBBTD_1 (0x08000000uL) -#define INTC_ICDICFR17_IEBBTERR_0 (0x10000000uL) -#define INTC_ICDICFR17_IEBBTERR_1 (0x20000000uL) -#define INTC_ICDICFR17_IEBBTSTA_0 (0x40000000uL) -#define INTC_ICDICFR17_IEBBTSTA_1 (0x80000000uL) - -#define INTC_ICDICFR18_IEBBTV_0 (0x00000001uL) -#define INTC_ICDICFR18_IEBBTV_1 (0x00000002uL) -#define INTC_ICDICFR18_ISY_0 (0x00000004uL) -#define INTC_ICDICFR18_ISY_1 (0x00000008uL) -#define INTC_ICDICFR18_IERR_0 (0x00000010uL) -#define INTC_ICDICFR18_IERR_1 (0x00000020uL) -#define INTC_ICDICFR18_ITARG_0 (0x00000040uL) -#define INTC_ICDICFR18_ITARG_1 (0x00000080uL) -#define INTC_ICDICFR18_ISEC_0 (0x00000100uL) -#define INTC_ICDICFR18_ISEC_1 (0x00000200uL) -#define INTC_ICDICFR18_IBUF_0 (0x00000400uL) -#define INTC_ICDICFR18_IBUF_1 (0x00000800uL) -#define INTC_ICDICFR18_IREADY_0 (0x00001000uL) -#define INTC_ICDICFR18_IREADY_1 (0x00002000uL) -#define INTC_ICDICFR18_FLSTE_0 (0x00004000uL) -#define INTC_ICDICFR18_FLSTE_1 (0x00008000uL) -#define INTC_ICDICFR18_FLTENDI_0 (0x00010000uL) -#define INTC_ICDICFR18_FLTENDI_1 (0x00020000uL) -#define INTC_ICDICFR18_FLTREQ0I_0 (0x00040000uL) -#define INTC_ICDICFR18_FLTREQ0I_1 (0x00080000uL) -#define INTC_ICDICFR18_FLTREQ1I_0 (0x00100000uL) -#define INTC_ICDICFR18_FLTREQ1I_1 (0x00200000uL) -#define INTC_ICDICFR18_MMC0_0 (0x00400000uL) -#define INTC_ICDICFR18_MMC0_1 (0x00800000uL) -#define INTC_ICDICFR18_MMC1_0 (0x01000000uL) -#define INTC_ICDICFR18_MMC1_1 (0x02000000uL) -#define INTC_ICDICFR18_MMC2_0 (0x04000000uL) -#define INTC_ICDICFR18_MMC2_1 (0x08000000uL) -#define INTC_ICDICFR18_SDHI0_3_0 (0x10000000uL) -#define INTC_ICDICFR18_SDHI0_3_1 (0x20000000uL) -#define INTC_ICDICFR18_SDHI0_0_0 (0x40000000uL) -#define INTC_ICDICFR18_SDHI0_0_1 (0x80000000uL) - -#define INTC_ICDICFR19_SDHI0_1_0 (0x00000001uL) -#define INTC_ICDICFR19_SDHI0_1_1 (0x00000002uL) -#define INTC_ICDICFR19_SDHI1_3_0 (0x00000004uL) -#define INTC_ICDICFR19_SDHI1_3_1 (0x00000008uL) -#define INTC_ICDICFR19_SDHI1_0_0 (0x00000010uL) -#define INTC_ICDICFR19_SDHI1_0_1 (0x00000020uL) -#define INTC_ICDICFR19_SDHI1_1_0 (0x00000040uL) -#define INTC_ICDICFR19_SDHI1_1_1 (0x00000080uL) -#define INTC_ICDICFR19_ARM_0 (0x00000100uL) -#define INTC_ICDICFR19_ARM_1 (0x00000200uL) -#define INTC_ICDICFR19_PRD_0 (0x00000400uL) -#define INTC_ICDICFR19_PRD_1 (0x00000800uL) -#define INTC_ICDICFR19_CUP_0 (0x00001000uL) -#define INTC_ICDICFR19_CUP_1 (0x00002000uL) -#define INTC_ICDICFR19_SCUAI0_0 (0x00004000uL) -#define INTC_ICDICFR19_SCUAI0_1 (0x00008000uL) -#define INTC_ICDICFR19_SCUAI1_0 (0x00010000uL) -#define INTC_ICDICFR19_SCUAI1_1 (0x00020000uL) -#define INTC_ICDICFR19_SCUFDI0_0 (0x00040000uL) -#define INTC_ICDICFR19_SCUFDI0_1 (0x00080000uL) -#define INTC_ICDICFR19_SCUFDI1_0 (0x00100000uL) -#define INTC_ICDICFR19_SCUFDI1_1 (0x00200000uL) -#define INTC_ICDICFR19_SCUFDI2_0 (0x00400000uL) -#define INTC_ICDICFR19_SCUFDI2_1 (0x00800000uL) -#define INTC_ICDICFR19_SCUFDI3_0 (0x01000000uL) -#define INTC_ICDICFR19_SCUFDI3_1 (0x02000000uL) -#define INTC_ICDICFR19_SCUFUI0_0 (0x04000000uL) -#define INTC_ICDICFR19_SCUFUI0_1 (0x08000000uL) -#define INTC_ICDICFR19_SCUFUI1_0 (0x10000000uL) -#define INTC_ICDICFR19_SCUFUI1_1 (0x20000000uL) -#define INTC_ICDICFR19_SCUFUI2_0 (0x40000000uL) -#define INTC_ICDICFR19_SCUFUI2_1 (0x80000000uL) - -#define INTC_ICDICFR20_SCUFUI3_0 (0x00000001uL) -#define INTC_ICDICFR20_SCUFUI3_1 (0x00000002uL) -#define INTC_ICDICFR20_SCUDVI0_0 (0x00000004uL) -#define INTC_ICDICFR20_SCUDVI0_1 (0x00000008uL) -#define INTC_ICDICFR20_SCUDVI1_0 (0x00000010uL) -#define INTC_ICDICFR20_SCUDVI1_1 (0x00000020uL) -#define INTC_ICDICFR20_SCUDVI2_0 (0x00000040uL) -#define INTC_ICDICFR20_SCUDVI2_1 (0x00000080uL) -#define INTC_ICDICFR20_SCUDVI3_0 (0x00000100uL) -#define INTC_ICDICFR20_SCUDVI3_1 (0x00000200uL) -#define INTC_ICDICFR20_MLB_CINT_0 (0x00000400uL) -#define INTC_ICDICFR20_MLB_CINT_1 (0x00000800uL) -#define INTC_ICDICFR20_MLB_SINT_0 (0x00001000uL) -#define INTC_ICDICFR20_MLB_SINT_1 (0x00002000uL) -#define INTC_ICDICFR20_DRC0_0 (0x00004000uL) -#define INTC_ICDICFR20_DRC0_1 (0x00008000uL) -#define INTC_ICDICFR20_DRC1_0 (0x00010000uL) -#define INTC_ICDICFR20_DRC1_1 (0x00020000uL) -#define INTC_ICDICFR20_LINI0_INT_T_0 (0x00400000uL) -#define INTC_ICDICFR20_LINI0_INT_T_1 (0x00800000uL) -#define INTC_ICDICFR20_LINI0_INT_R_0 (0x01000000uL) -#define INTC_ICDICFR20_LINI0_INT_R_1 (0x02000000uL) -#define INTC_ICDICFR20_LINI0_INT_S_0 (0x04000000uL) -#define INTC_ICDICFR20_LINI0_INT_S_1 (0x08000000uL) -#define INTC_ICDICFR20_LINI0_INT_M_0 (0x10000000uL) -#define INTC_ICDICFR20_LINI0_INT_M_1 (0x20000000uL) -#define INTC_ICDICFR20_LINI1_INT_T_0 (0x40000000uL) -#define INTC_ICDICFR20_LINI1_INT_T_1 (0x80000000uL) - -#define INTC_ICDICFR21_LINI1_INT_R_0 (0x00000001uL) -#define INTC_ICDICFR21_LINI1_INT_R_1 (0x00000002uL) -#define INTC_ICDICFR21_LINI1_INT_S_0 (0x00000004uL) -#define INTC_ICDICFR21_LINI1_INT_S_1 (0x00000008uL) -#define INTC_ICDICFR21_LINI1_INT_M_0 (0x00000010uL) -#define INTC_ICDICFR21_LINI1_INT_M_1 (0x00000020uL) -#define INTC_ICDICFR21_ERI0_0 (0x00400000uL) -#define INTC_ICDICFR21_ERI0_1 (0x00800000uL) -#define INTC_ICDICFR21_RXI0_0 (0x01000000uL) -#define INTC_ICDICFR21_RXI0_1 (0x02000000uL) -#define INTC_ICDICFR21_TXI0_0 (0x04000000uL) -#define INTC_ICDICFR21_TXI0_1 (0x08000000uL) -#define INTC_ICDICFR21_TEI0_0 (0x10000000uL) -#define INTC_ICDICFR21_TEI0_1 (0x20000000uL) -#define INTC_ICDICFR21_ERI1_0 (0x40000000uL) -#define INTC_ICDICFR21_ERI1_1 (0x80000000uL) - -#define INTC_ICDICFR22_RXI1_0 (0x00000001uL) -#define INTC_ICDICFR22_RXI1_1 (0x00000002uL) -#define INTC_ICDICFR22_TXI1_0 (0x00000004uL) -#define INTC_ICDICFR22_TXI1_1 (0x00000008uL) -#define INTC_ICDICFR22_TEI1_0 (0x00000010uL) -#define INTC_ICDICFR22_TEI1_1 (0x00000020uL) -#define INTC_ICDICFR22_AVBI_DATA_0 (0x00000040uL) -#define INTC_ICDICFR22_AVBI_DATA_1 (0x00000080uL) -#define INTC_ICDICFR22_AVBI_ERROR_0 (0x00000100uL) -#define INTC_ICDICFR22_AVBI_ERROR_1 (0x00000200uL) -#define INTC_ICDICFR22_AVBI_MANAGE_0 (0x00000400uL) -#define INTC_ICDICFR22_AVBI_MANAGE_1 (0x00000800uL) -#define INTC_ICDICFR22_AVBI_MAC_0 (0x00001000uL) -#define INTC_ICDICFR22_AVBI_MAC_1 (0x00002000uL) -#define INTC_ICDICFR22_ETHERI_0 (0x00004000uL) -#define INTC_ICDICFR22_ETHERI_1 (0x00008000uL) -#define INTC_ICDICFR22_CEUI_0 (0x01000000uL) -#define INTC_ICDICFR22_CEUI_1 (0x02000000uL) - -#define INTC_ICDICFR23_H2XMLB_ERRINT_0 (0x04000000uL) -#define INTC_ICDICFR23_H2XMLB_ERRINT_1 (0x08000000uL) -#define INTC_ICDICFR23_H2XIC1_ERRINT_0 (0x10000000uL) -#define INTC_ICDICFR23_H2XIC1_ERRINT_1 (0x20000000uL) -#define INTC_ICDICFR23_X2HPERI1_ERRINT_0 (0x40000000uL) -#define INTC_ICDICFR23_X2HPERI1_ERRINT_1 (0x80000000uL) - -#define INTC_ICDICFR24_X2HPERI2_ERRINT_0 (0x00000001uL) -#define INTC_ICDICFR24_X2HPERI2_ERRINT_1 (0x00000002uL) -#define INTC_ICDICFR24_X2HPERI34_ERRINT_0 (0x00000004uL) -#define INTC_ICDICFR24_X2HPERI34_ERRINT_1 (0x00000008uL) -#define INTC_ICDICFR24_X2HPERI5_ERRINT_0 (0x00000010uL) -#define INTC_ICDICFR24_X2HPERI5_ERRINT_1 (0x00000020uL) -#define INTC_ICDICFR24_X2HPERI67_ERRINT_0 (0x00000040uL) -#define INTC_ICDICFR24_X2HPERI67_ERRINT_1 (0x00000080uL) -#define INTC_ICDICFR24_X2HDBGR_ERRINT_0 (0x00000100uL) -#define INTC_ICDICFR24_X2HDBGR_ERRINT_1 (0x00000200uL) -#define INTC_ICDICFR24_X2HBSC_ERRINT_0 (0x00000400uL) -#define INTC_ICDICFR24_X2HBSC_ERRINT_1 (0x00000800uL) -#define INTC_ICDICFR24_X2HSPI1_ERRINT_0 (0x00001000uL) -#define INTC_ICDICFR24_X2HSPI1_ERRINT_1 (0x00002000uL) -#define INTC_ICDICFR24_X2HSPI2_ERRINT_0 (0x00004000uL) -#define INTC_ICDICFR24_X2HSPI2_ERRINT_1 (0x00008000uL) -#define INTC_ICDICFR24_PRRI_0 (0x00010000uL) -#define INTC_ICDICFR24_PRRI_1 (0x00020000uL) -#define INTC_ICDICFR24_IFEI0_0 (0x00040000uL) -#define INTC_ICDICFR24_IFEI0_1 (0x00080000uL) -#define INTC_ICDICFR24_OFFI0_0 (0x00100000uL) -#define INTC_ICDICFR24_OFFI0_1 (0x00200000uL) -#define INTC_ICDICFR24_PFVEI0_0 (0x00400000uL) -#define INTC_ICDICFR24_PFVEI0_1 (0x00800000uL) -#define INTC_ICDICFR24_IFEI1_0 (0x01000000uL) -#define INTC_ICDICFR24_IFEI1_1 (0x02000000uL) -#define INTC_ICDICFR24_OFFI1_0 (0x04000000uL) -#define INTC_ICDICFR24_OFFI1_1 (0x08000000uL) -#define INTC_ICDICFR24_PFVEI1_0 (0x10000000uL) -#define INTC_ICDICFR24_PFVEI1_1 (0x20000000uL) - -#define INTC_ICDICFR26_TINT0_0 (0x00000001uL) -#define INTC_ICDICFR26_TINT0_1 (0x00000002uL) -#define INTC_ICDICFR26_TINT1_0 (0x00000004uL) -#define INTC_ICDICFR26_TINT1_1 (0x00000008uL) -#define INTC_ICDICFR26_TINT2_0 (0x00000010uL) -#define INTC_ICDICFR26_TINT2_1 (0x00000020uL) -#define INTC_ICDICFR26_TINT3_0 (0x00000040uL) -#define INTC_ICDICFR26_TINT3_1 (0x00000080uL) -#define INTC_ICDICFR26_TINT4_0 (0x00000100uL) -#define INTC_ICDICFR26_TINT4_1 (0x00000200uL) -#define INTC_ICDICFR26_TINT5_0 (0x00000400uL) -#define INTC_ICDICFR26_TINT5_1 (0x00000800uL) -#define INTC_ICDICFR26_TINT6_0 (0x00001000uL) -#define INTC_ICDICFR26_TINT6_1 (0x00002000uL) -#define INTC_ICDICFR26_TINT7_0 (0x00004000uL) -#define INTC_ICDICFR26_TINT7_1 (0x00008000uL) -#define INTC_ICDICFR26_TINT8_0 (0x00010000uL) -#define INTC_ICDICFR26_TINT8_1 (0x00020000uL) -#define INTC_ICDICFR26_TINT9_0 (0x00040000uL) -#define INTC_ICDICFR26_TINT9_1 (0x00080000uL) -#define INTC_ICDICFR26_TINT10_0 (0x00100000uL) -#define INTC_ICDICFR26_TINT10_1 (0x00200000uL) -#define INTC_ICDICFR26_TINT11_0 (0x00400000uL) -#define INTC_ICDICFR26_TINT11_1 (0x00800000uL) -#define INTC_ICDICFR26_TINT12_0 (0x01000000uL) -#define INTC_ICDICFR26_TINT12_1 (0x02000000uL) -#define INTC_ICDICFR26_TINT13_0 (0x04000000uL) -#define INTC_ICDICFR26_TINT13_1 (0x08000000uL) -#define INTC_ICDICFR26_TINT14_0 (0x10000000uL) -#define INTC_ICDICFR26_TINT14_1 (0x20000000uL) -#define INTC_ICDICFR26_TINT15_0 (0x40000000uL) -#define INTC_ICDICFR26_TINT15_1 (0x80000000uL) - -#define INTC_ICDICFR27_TINT16_0 (0x00000001uL) -#define INTC_ICDICFR27_TINT16_1 (0x00000002uL) -#define INTC_ICDICFR27_TINT17_0 (0x00000004uL) -#define INTC_ICDICFR27_TINT17_1 (0x00000008uL) -#define INTC_ICDICFR27_TINT18_0 (0x00000010uL) -#define INTC_ICDICFR27_TINT18_1 (0x00000020uL) -#define INTC_ICDICFR27_TINT19_0 (0x00000040uL) -#define INTC_ICDICFR27_TINT19_1 (0x00000080uL) -#define INTC_ICDICFR27_TINT20_0 (0x00000100uL) -#define INTC_ICDICFR27_TINT20_1 (0x00000200uL) -#define INTC_ICDICFR27_TINT21_0 (0x00000400uL) -#define INTC_ICDICFR27_TINT21_1 (0x00000800uL) -#define INTC_ICDICFR27_TINT22_0 (0x00001000uL) -#define INTC_ICDICFR27_TINT22_1 (0x00002000uL) -#define INTC_ICDICFR27_TINT23_0 (0x00004000uL) -#define INTC_ICDICFR27_TINT23_1 (0x00008000uL) -#define INTC_ICDICFR27_TINT24_0 (0x00010000uL) -#define INTC_ICDICFR27_TINT24_1 (0x00020000uL) -#define INTC_ICDICFR27_TINT25_0 (0x00040000uL) -#define INTC_ICDICFR27_TINT25_1 (0x00080000uL) -#define INTC_ICDICFR27_TINT26_0 (0x00100000uL) -#define INTC_ICDICFR27_TINT26_1 (0x00200000uL) -#define INTC_ICDICFR27_TINT27_0 (0x00400000uL) -#define INTC_ICDICFR27_TINT27_1 (0x00800000uL) -#define INTC_ICDICFR27_TINT28_0 (0x01000000uL) -#define INTC_ICDICFR27_TINT28_1 (0x02000000uL) -#define INTC_ICDICFR27_TINT29_0 (0x04000000uL) -#define INTC_ICDICFR27_TINT29_1 (0x08000000uL) -#define INTC_ICDICFR27_TINT30_0 (0x10000000uL) -#define INTC_ICDICFR27_TINT30_1 (0x20000000uL) -#define INTC_ICDICFR27_TINT31_0 (0x40000000uL) -#define INTC_ICDICFR27_TINT31_1 (0x80000000uL) - -#define INTC_ICDICFR28_TINT32_0 (0x00000001uL) -#define INTC_ICDICFR28_TINT32_1 (0x00000002uL) -#define INTC_ICDICFR28_TINT33_0 (0x00000004uL) -#define INTC_ICDICFR28_TINT33_1 (0x00000008uL) -#define INTC_ICDICFR28_TINT34_0 (0x00000010uL) -#define INTC_ICDICFR28_TINT34_1 (0x00000020uL) -#define INTC_ICDICFR28_TINT35_0 (0x00000040uL) -#define INTC_ICDICFR28_TINT35_1 (0x00000080uL) -#define INTC_ICDICFR28_TINT36_0 (0x00000100uL) -#define INTC_ICDICFR28_TINT36_1 (0x00000200uL) -#define INTC_ICDICFR28_TINT37_0 (0x00000400uL) -#define INTC_ICDICFR28_TINT37_1 (0x00000800uL) -#define INTC_ICDICFR28_TINT38_0 (0x00001000uL) -#define INTC_ICDICFR28_TINT38_1 (0x00002000uL) -#define INTC_ICDICFR28_TINT39_0 (0x00004000uL) -#define INTC_ICDICFR28_TINT39_1 (0x00008000uL) -#define INTC_ICDICFR28_TINT40_0 (0x00010000uL) -#define INTC_ICDICFR28_TINT40_1 (0x00020000uL) -#define INTC_ICDICFR28_TINT41_0 (0x00040000uL) -#define INTC_ICDICFR28_TINT41_1 (0x00080000uL) -#define INTC_ICDICFR28_TINT42_0 (0x00100000uL) -#define INTC_ICDICFR28_TINT42_1 (0x00200000uL) -#define INTC_ICDICFR28_TINT43_0 (0x00400000uL) -#define INTC_ICDICFR28_TINT43_1 (0x00800000uL) -#define INTC_ICDICFR28_TINT44_0 (0x01000000uL) -#define INTC_ICDICFR28_TINT44_1 (0x02000000uL) -#define INTC_ICDICFR28_TINT45_0 (0x04000000uL) -#define INTC_ICDICFR28_TINT45_1 (0x08000000uL) -#define INTC_ICDICFR28_TINT46_0 (0x10000000uL) -#define INTC_ICDICFR28_TINT46_1 (0x20000000uL) -#define INTC_ICDICFR28_TINT47_0 (0x40000000uL) -#define INTC_ICDICFR28_TINT47_1 (0x80000000uL) - -#define INTC_ICDICFR29_TINT48_0 (0x00000001uL) -#define INTC_ICDICFR29_TINT48_1 (0x00000002uL) -#define INTC_ICDICFR29_TINT49_0 (0x00000004uL) -#define INTC_ICDICFR29_TINT49_1 (0x00000008uL) -#define INTC_ICDICFR29_TINT50_0 (0x00000010uL) -#define INTC_ICDICFR29_TINT50_1 (0x00000020uL) -#define INTC_ICDICFR29_TINT51_0 (0x00000040uL) -#define INTC_ICDICFR29_TINT51_1 (0x00000080uL) -#define INTC_ICDICFR29_TINT52_0 (0x00000100uL) -#define INTC_ICDICFR29_TINT52_1 (0x00000200uL) -#define INTC_ICDICFR29_TINT53_0 (0x00000400uL) -#define INTC_ICDICFR29_TINT53_1 (0x00000800uL) -#define INTC_ICDICFR29_TINT54_0 (0x00001000uL) -#define INTC_ICDICFR29_TINT54_1 (0x00002000uL) -#define INTC_ICDICFR29_TINT55_0 (0x00004000uL) -#define INTC_ICDICFR29_TINT55_1 (0x00008000uL) -#define INTC_ICDICFR29_TINT56_0 (0x00010000uL) -#define INTC_ICDICFR29_TINT56_1 (0x00020000uL) -#define INTC_ICDICFR29_TINT57_0 (0x00040000uL) -#define INTC_ICDICFR29_TINT57_1 (0x00080000uL) -#define INTC_ICDICFR29_TINT58_0 (0x00100000uL) -#define INTC_ICDICFR29_TINT58_1 (0x00200000uL) -#define INTC_ICDICFR29_TINT59_0 (0x00400000uL) -#define INTC_ICDICFR29_TINT59_1 (0x00800000uL) -#define INTC_ICDICFR29_TINT60_0 (0x01000000uL) -#define INTC_ICDICFR29_TINT60_1 (0x02000000uL) -#define INTC_ICDICFR29_TINT61_0 (0x04000000uL) -#define INTC_ICDICFR29_TINT61_1 (0x08000000uL) -#define INTC_ICDICFR29_TINT62_0 (0x10000000uL) -#define INTC_ICDICFR29_TINT62_1 (0x20000000uL) -#define INTC_ICDICFR29_TINT63_0 (0x40000000uL) -#define INTC_ICDICFR29_TINT63_1 (0x80000000uL) - -#define INTC_ICDICFR30_TINT64_0 (0x00000001uL) -#define INTC_ICDICFR30_TINT64_1 (0x00000002uL) -#define INTC_ICDICFR30_TINT65_0 (0x00000004uL) -#define INTC_ICDICFR30_TINT65_1 (0x00000008uL) -#define INTC_ICDICFR30_TINT66_0 (0x00000010uL) -#define INTC_ICDICFR30_TINT66_1 (0x00000020uL) -#define INTC_ICDICFR30_TINT67_0 (0x00000040uL) -#define INTC_ICDICFR30_TINT67_1 (0x00000080uL) -#define INTC_ICDICFR30_TINT68_0 (0x00000100uL) -#define INTC_ICDICFR30_TINT68_1 (0x00000200uL) -#define INTC_ICDICFR30_TINT69_0 (0x00000400uL) -#define INTC_ICDICFR30_TINT69_1 (0x00000800uL) -#define INTC_ICDICFR30_TINT70_0 (0x00001000uL) -#define INTC_ICDICFR30_TINT70_1 (0x00002000uL) -#define INTC_ICDICFR30_TINT71_0 (0x00004000uL) -#define INTC_ICDICFR30_TINT71_1 (0x00008000uL) -#define INTC_ICDICFR30_TINT72_0 (0x00010000uL) -#define INTC_ICDICFR30_TINT72_1 (0x00020000uL) -#define INTC_ICDICFR30_TINT73_0 (0x00040000uL) -#define INTC_ICDICFR30_TINT73_1 (0x00080000uL) -#define INTC_ICDICFR30_TINT74_0 (0x00100000uL) -#define INTC_ICDICFR30_TINT74_1 (0x00200000uL) -#define INTC_ICDICFR30_TINT75_0 (0x00400000uL) -#define INTC_ICDICFR30_TINT75_1 (0x00800000uL) -#define INTC_ICDICFR30_TINT76_0 (0x01000000uL) -#define INTC_ICDICFR30_TINT76_1 (0x02000000uL) -#define INTC_ICDICFR30_TINT77_0 (0x04000000uL) -#define INTC_ICDICFR30_TINT77_1 (0x08000000uL) -#define INTC_ICDICFR30_TINT78_0 (0x10000000uL) -#define INTC_ICDICFR30_TINT78_1 (0x20000000uL) -#define INTC_ICDICFR30_TINT79_0 (0x40000000uL) -#define INTC_ICDICFR30_TINT79_1 (0x80000000uL) - -#define INTC_ICDICFR31_TINT80_0 (0x00000001uL) -#define INTC_ICDICFR31_TINT80_1 (0x00000002uL) -#define INTC_ICDICFR31_TINT81_0 (0x00000004uL) -#define INTC_ICDICFR31_TINT81_1 (0x00000008uL) -#define INTC_ICDICFR31_TINT82_0 (0x00000010uL) -#define INTC_ICDICFR31_TINT82_1 (0x00000020uL) -#define INTC_ICDICFR31_TINT83_0 (0x00000040uL) -#define INTC_ICDICFR31_TINT83_1 (0x00000080uL) -#define INTC_ICDICFR31_TINT84_0 (0x00000100uL) -#define INTC_ICDICFR31_TINT84_1 (0x00000200uL) -#define INTC_ICDICFR31_TINT85_0 (0x00000400uL) -#define INTC_ICDICFR31_TINT85_1 (0x00000800uL) -#define INTC_ICDICFR31_TINT86_0 (0x00001000uL) -#define INTC_ICDICFR31_TINT86_1 (0x00002000uL) -#define INTC_ICDICFR31_TINT87_0 (0x00004000uL) -#define INTC_ICDICFR31_TINT87_1 (0x00008000uL) -#define INTC_ICDICFR31_TINT88_0 (0x00010000uL) -#define INTC_ICDICFR31_TINT88_1 (0x00020000uL) -#define INTC_ICDICFR31_TINT89_0 (0x00040000uL) -#define INTC_ICDICFR31_TINT89_1 (0x00080000uL) -#define INTC_ICDICFR31_TINT90_0 (0x00100000uL) -#define INTC_ICDICFR31_TINT90_1 (0x00200000uL) -#define INTC_ICDICFR31_TINT91_0 (0x00400000uL) -#define INTC_ICDICFR31_TINT91_1 (0x00800000uL) -#define INTC_ICDICFR31_TINT92_0 (0x01000000uL) -#define INTC_ICDICFR31_TINT92_1 (0x02000000uL) -#define INTC_ICDICFR31_TINT93_0 (0x04000000uL) -#define INTC_ICDICFR31_TINT93_1 (0x08000000uL) -#define INTC_ICDICFR31_TINT94_0 (0x10000000uL) -#define INTC_ICDICFR31_TINT94_1 (0x20000000uL) -#define INTC_ICDICFR31_TINT95_0 (0x40000000uL) -#define INTC_ICDICFR31_TINT95_1 (0x80000000uL) - -#define INTC_ICDICFR32_TINT96_0 (0x00000001uL) -#define INTC_ICDICFR32_TINT96_1 (0x00000002uL) -#define INTC_ICDICFR32_TINT97_0 (0x00000004uL) -#define INTC_ICDICFR32_TINT97_1 (0x00000008uL) -#define INTC_ICDICFR32_TINT98_0 (0x00000010uL) -#define INTC_ICDICFR32_TINT98_1 (0x00000020uL) -#define INTC_ICDICFR32_TINT99_0 (0x00000040uL) -#define INTC_ICDICFR32_TINT99_1 (0x00000080uL) -#define INTC_ICDICFR32_TINT100_0 (0x00000100uL) -#define INTC_ICDICFR32_TINT100_1 (0x00000200uL) -#define INTC_ICDICFR32_TINT101_0 (0x00000400uL) -#define INTC_ICDICFR32_TINT101_1 (0x00000800uL) -#define INTC_ICDICFR32_TINT102_0 (0x00001000uL) -#define INTC_ICDICFR32_TINT102_1 (0x00002000uL) -#define INTC_ICDICFR32_TINT103_0 (0x00004000uL) -#define INTC_ICDICFR32_TINT103_1 (0x00008000uL) -#define INTC_ICDICFR32_TINT104_0 (0x00010000uL) -#define INTC_ICDICFR32_TINT104_1 (0x00020000uL) -#define INTC_ICDICFR32_TINT105_0 (0x00040000uL) -#define INTC_ICDICFR32_TINT105_1 (0x00080000uL) -#define INTC_ICDICFR32_TINT106_0 (0x00100000uL) -#define INTC_ICDICFR32_TINT106_1 (0x00200000uL) -#define INTC_ICDICFR32_TINT107_0 (0x00400000uL) -#define INTC_ICDICFR32_TINT107_1 (0x00800000uL) -#define INTC_ICDICFR32_TINT108_0 (0x01000000uL) -#define INTC_ICDICFR32_TINT108_1 (0x02000000uL) -#define INTC_ICDICFR32_TINT109_0 (0x04000000uL) -#define INTC_ICDICFR32_TINT109_1 (0x08000000uL) -#define INTC_ICDICFR32_TINT110_0 (0x10000000uL) -#define INTC_ICDICFR32_TINT110_1 (0x20000000uL) -#define INTC_ICDICFR32_TINT111_0 (0x40000000uL) -#define INTC_ICDICFR32_TINT111_1 (0x80000000uL) - -#define INTC_ICDICFR33_TINT112_0 (0x00000001uL) -#define INTC_ICDICFR33_TINT112_1 (0x00000002uL) -#define INTC_ICDICFR33_TINT113_0 (0x00000004uL) -#define INTC_ICDICFR33_TINT113_1 (0x00000008uL) -#define INTC_ICDICFR33_TINT114_0 (0x00000010uL) -#define INTC_ICDICFR33_TINT114_1 (0x00000020uL) -#define INTC_ICDICFR33_TINT115_0 (0x00000040uL) -#define INTC_ICDICFR33_TINT115_1 (0x00000080uL) -#define INTC_ICDICFR33_TINT116_0 (0x00000100uL) -#define INTC_ICDICFR33_TINT116_1 (0x00000200uL) -#define INTC_ICDICFR33_TINT117_0 (0x00000400uL) -#define INTC_ICDICFR33_TINT117_1 (0x00000800uL) -#define INTC_ICDICFR33_TINT118_0 (0x00001000uL) -#define INTC_ICDICFR33_TINT118_1 (0x00002000uL) -#define INTC_ICDICFR33_TINT119_0 (0x00004000uL) -#define INTC_ICDICFR33_TINT119_1 (0x00008000uL) -#define INTC_ICDICFR33_TINT120_0 (0x00010000uL) -#define INTC_ICDICFR33_TINT120_1 (0x00020000uL) -#define INTC_ICDICFR33_TINT121_0 (0x00040000uL) -#define INTC_ICDICFR33_TINT121_1 (0x00080000uL) -#define INTC_ICDICFR33_TINT122_0 (0x00100000uL) -#define INTC_ICDICFR33_TINT122_1 (0x00200000uL) -#define INTC_ICDICFR33_TINT123_0 (0x00400000uL) -#define INTC_ICDICFR33_TINT123_1 (0x00800000uL) -#define INTC_ICDICFR33_TINT124_0 (0x01000000uL) -#define INTC_ICDICFR33_TINT124_1 (0x02000000uL) -#define INTC_ICDICFR33_TINT125_0 (0x04000000uL) -#define INTC_ICDICFR33_TINT125_1 (0x08000000uL) -#define INTC_ICDICFR33_TINT126_0 (0x10000000uL) -#define INTC_ICDICFR33_TINT126_1 (0x20000000uL) -#define INTC_ICDICFR33_TINT127_0 (0x40000000uL) -#define INTC_ICDICFR33_TINT127_1 (0x80000000uL) - -#define INTC_ICDICFR34_TINT128_0 (0x00000001uL) -#define INTC_ICDICFR34_TINT128_1 (0x00000002uL) -#define INTC_ICDICFR34_TINT129_0 (0x00000004uL) -#define INTC_ICDICFR34_TINT129_1 (0x00000008uL) -#define INTC_ICDICFR34_TINT130_0 (0x00000010uL) -#define INTC_ICDICFR34_TINT130_1 (0x00000020uL) -#define INTC_ICDICFR34_TINT131_0 (0x00000040uL) -#define INTC_ICDICFR34_TINT131_1 (0x00000080uL) -#define INTC_ICDICFR34_TINT132_0 (0x00000100uL) -#define INTC_ICDICFR34_TINT132_1 (0x00000200uL) -#define INTC_ICDICFR34_TINT133_0 (0x00000400uL) -#define INTC_ICDICFR34_TINT133_1 (0x00000800uL) -#define INTC_ICDICFR34_TINT134_0 (0x00001000uL) -#define INTC_ICDICFR34_TINT134_1 (0x00002000uL) -#define INTC_ICDICFR34_TINT135_0 (0x00004000uL) -#define INTC_ICDICFR34_TINT135_1 (0x00008000uL) -#define INTC_ICDICFR34_TINT136_0 (0x00010000uL) -#define INTC_ICDICFR34_TINT136_1 (0x00020000uL) -#define INTC_ICDICFR34_TINT137_0 (0x00040000uL) -#define INTC_ICDICFR34_TINT137_1 (0x00080000uL) -#define INTC_ICDICFR34_TINT138_0 (0x00100000uL) -#define INTC_ICDICFR34_TINT138_1 (0x00200000uL) -#define INTC_ICDICFR34_TINT139_0 (0x00400000uL) -#define INTC_ICDICFR34_TINT139_1 (0x00800000uL) -#define INTC_ICDICFR34_TINT140_0 (0x01000000uL) -#define INTC_ICDICFR34_TINT140_1 (0x02000000uL) -#define INTC_ICDICFR34_TINT141_0 (0x04000000uL) -#define INTC_ICDICFR34_TINT141_1 (0x08000000uL) -#define INTC_ICDICFR34_TINT142_0 (0x10000000uL) -#define INTC_ICDICFR34_TINT142_1 (0x20000000uL) -#define INTC_ICDICFR34_TINT143_0 (0x40000000uL) -#define INTC_ICDICFR34_TINT143_1 (0x80000000uL) - -#define INTC_ICDICFR35_TINT144_0 (0x00000001uL) -#define INTC_ICDICFR35_TINT144_1 (0x00000002uL) -#define INTC_ICDICFR35_TINT145_0 (0x00000004uL) -#define INTC_ICDICFR35_TINT145_1 (0x00000008uL) -#define INTC_ICDICFR35_TINT146_0 (0x00000010uL) -#define INTC_ICDICFR35_TINT146_1 (0x00000020uL) -#define INTC_ICDICFR35_TINT147_0 (0x00000040uL) -#define INTC_ICDICFR35_TINT147_1 (0x00000080uL) -#define INTC_ICDICFR35_TINT148_0 (0x00000100uL) -#define INTC_ICDICFR35_TINT148_1 (0x00000200uL) -#define INTC_ICDICFR35_TINT149_0 (0x00000400uL) -#define INTC_ICDICFR35_TINT149_1 (0x00000800uL) -#define INTC_ICDICFR35_TINT150_0 (0x00001000uL) -#define INTC_ICDICFR35_TINT150_1 (0x00002000uL) -#define INTC_ICDICFR35_TINT151_0 (0x00004000uL) -#define INTC_ICDICFR35_TINT151_1 (0x00008000uL) -#define INTC_ICDICFR35_TINT152_0 (0x00010000uL) -#define INTC_ICDICFR35_TINT152_1 (0x00020000uL) -#define INTC_ICDICFR35_TINT153_0 (0x00040000uL) -#define INTC_ICDICFR35_TINT153_1 (0x00080000uL) -#define INTC_ICDICFR35_TINT154_0 (0x00100000uL) -#define INTC_ICDICFR35_TINT154_1 (0x00200000uL) -#define INTC_ICDICFR35_TINT155_0 (0x00400000uL) -#define INTC_ICDICFR35_TINT155_1 (0x00800000uL) -#define INTC_ICDICFR35_TINT156_0 (0x01000000uL) -#define INTC_ICDICFR35_TINT156_1 (0x02000000uL) -#define INTC_ICDICFR35_TINT157_0 (0x04000000uL) -#define INTC_ICDICFR35_TINT157_1 (0x08000000uL) -#define INTC_ICDICFR35_TINT158_0 (0x10000000uL) -#define INTC_ICDICFR35_TINT158_1 (0x20000000uL) -#define INTC_ICDICFR35_TINT159_0 (0x40000000uL) -#define INTC_ICDICFR35_TINT159_1 (0x80000000uL) - -#define INTC_ICDICFR36_TINT160_0 (0x00000001uL) -#define INTC_ICDICFR36_TINT160_1 (0x00000002uL) -#define INTC_ICDICFR36_TINT161_0 (0x00000004uL) -#define INTC_ICDICFR36_TINT161_1 (0x00000008uL) -#define INTC_ICDICFR36_TINT162_0 (0x00000010uL) -#define INTC_ICDICFR36_TINT162_1 (0x00000020uL) -#define INTC_ICDICFR36_TINT163_0 (0x00000040uL) -#define INTC_ICDICFR36_TINT163_1 (0x00000080uL) -#define INTC_ICDICFR36_TINT164_0 (0x00000100uL) -#define INTC_ICDICFR36_TINT164_1 (0x00000200uL) -#define INTC_ICDICFR36_TINT165_0 (0x00000400uL) -#define INTC_ICDICFR36_TINT165_1 (0x00000800uL) -#define INTC_ICDICFR36_TINT166_0 (0x00001000uL) -#define INTC_ICDICFR36_TINT166_1 (0x00002000uL) -#define INTC_ICDICFR36_TINT167_0 (0x00004000uL) -#define INTC_ICDICFR36_TINT167_1 (0x00008000uL) -#define INTC_ICDICFR36_TINT168_0 (0x00010000uL) -#define INTC_ICDICFR36_TINT168_1 (0x00020000uL) -#define INTC_ICDICFR36_TINT169_0 (0x00040000uL) -#define INTC_ICDICFR36_TINT169_1 (0x00080000uL) -#define INTC_ICDICFR36_TINT170_0 (0x00100000uL) -#define INTC_ICDICFR36_TINT170_1 (0x00200000uL) - -#define INTC_ICDSGIR_SGIINTID (0x0000000FuL) -#define INTC_ICDSGIR_SATT (0x00008000uL) -#define INTC_ICDSGIR_CPUTargetList (0x00FF0000uL) -#define INTC_ICDSGIR_TargetListFilter (0x03000000uL) - -#define INTC_ICCICR_EnableS (0x00000001uL) -#define INTC_ICCICR_EnableNS (0x00000002uL) -#define INTC_ICCICR_AckCtl (0x00000004uL) -#define INTC_ICCICR_FIQEn (0x00000008uL) -#define INTC_ICCICR_SBPR (0x00000010uL) - -#define INTC_ICCPMR_Priority (0x000000FFuL) - -#define INTC_ICCBPR_Binarypoint (0x00000007uL) - -#define INTC_ICCIAR_ACKINTID (0x000003FFuL) -#define INTC_ICCIAR_CPUID (0x00001C00uL) - -#define INTC_ICCEOIR_EOIINTID (0x000003FFuL) -#define INTC_ICCEOIR_CPUID (0x00001C00uL) - -#define INTC_ICCRPR_Priority (0x000000FFuL) - -#define INTC_ICCHPIR_PENDINTID (0x000003FFuL) -#define INTC_ICCHPIR_CPUID (0x00001C00uL) - -#define INTC_ICCABPR_Binarypoint (0x00000007uL) - -#define INTC_ICCIIDR_Implementer (0x00000FFFuL) -#define INTC_ICCIIDR_Revision (0x0000F000uL) -#define INTC_ICCIIDR_Architecture_version (0x000F0000uL) -#define INTC_ICCIIDR_ProductID (0xFFF00000uL) - -#define INTC_ICR0_NMIF (0x0002u) -#define INTC_ICR0_NMIE (0x0100u) -#define INTC_ICR0_NMIL (0x8000u) - -#define INTC_ICR1_IRQ00S (0x0001u) -#define INTC_ICR1_IRQ01S (0x0002u) -#define INTC_ICR1_IRQ10S (0x0004u) -#define INTC_ICR1_IRQ11S (0x0008u) -#define INTC_ICR1_IRQ20S (0x0010u) -#define INTC_ICR1_IRQ21S (0x0020u) -#define INTC_ICR1_IRQ30S (0x0040u) -#define INTC_ICR1_IRQ31S (0x0080u) -#define INTC_ICR1_IRQ40S (0x0100u) -#define INTC_ICR1_IRQ41S (0x0200u) -#define INTC_ICR1_IRQ50S (0x0400u) -#define INTC_ICR1_IRQ51S (0x0800u) -#define INTC_ICR1_IRQ60S (0x1000u) -#define INTC_ICR1_IRQ61S (0x2000u) -#define INTC_ICR1_IRQ70S (0x4000u) -#define INTC_ICR1_IRQ71S (0x8000u) - -#define INTC_IRQRR_IRQ0F (0x0001u) -#define INTC_IRQRR_IRQ1F (0x0002u) -#define INTC_IRQRR_IRQ2F (0x0004u) -#define INTC_IRQRR_IRQ3F (0x0008u) -#define INTC_IRQRR_IRQ4F (0x0010u) -#define INTC_IRQRR_IRQ5F (0x0020u) -#define INTC_IRQRR_IRQ6F (0x0040u) -#define INTC_IRQRR_IRQ7F (0x0080u) - - -/* ==== Shift values for IO registers ==== */ -#define INTC_ICDDCR_Enable_SHIFT (0u) - -#define INTC_ICDICTR_ITLinesNumber_SHIFT (0u) -#define INTC_ICDICTR_CPUNumber_SHIFT (5u) -#define INTC_ICDICTR_SecurityExtn_SHIFT (10u) -#define INTC_ICDICTR_LSPI_SHIFT (11u) - -#define INTC_ICDIIDR_Implementer_SHIFT (0u) -#define INTC_ICDIIDR_Revision_SHIFT (12u) -#define INTC_ICDIIDR_Variant_SHIFT (16u) -#define INTC_ICDIIDR_ProductID_SHIFT (24u) - -#define INTC_ICDISR0_SW0_SHIFT (0u) -#define INTC_ICDISR0_SW1_SHIFT (1u) -#define INTC_ICDISR0_SW2_SHIFT (2u) -#define INTC_ICDISR0_SW3_SHIFT (3u) -#define INTC_ICDISR0_SW4_SHIFT (4u) -#define INTC_ICDISR0_SW5_SHIFT (5u) -#define INTC_ICDISR0_SW6_SHIFT (6u) -#define INTC_ICDISR0_SW7_SHIFT (7u) -#define INTC_ICDISR0_SW8_SHIFT (8u) -#define INTC_ICDISR0_SW9_SHIFT (9u) -#define INTC_ICDISR0_SW10_SHIFT (10u) -#define INTC_ICDISR0_SW11_SHIFT (11u) -#define INTC_ICDISR0_SW12_SHIFT (12u) -#define INTC_ICDISR0_SW13_SHIFT (13u) -#define INTC_ICDISR0_SW14_SHIFT (14u) -#define INTC_ICDISR0_SW15_SHIFT (15u) -#define INTC_ICDISR0_PMUIRQ0_SHIFT (16u) -#define INTC_ICDISR0_COMMRX0_SHIFT (17u) -#define INTC_ICDISR0_COMMTX0_SHIFT (18u) -#define INTC_ICDISR0_CTIIRQ0_SHIFT (19u) - -#define INTC_ICDISR1_IRQ0_SHIFT (0u) -#define INTC_ICDISR1_IRQ1_SHIFT (1u) -#define INTC_ICDISR1_IRQ2_SHIFT (2u) -#define INTC_ICDISR1_IRQ3_SHIFT (3u) -#define INTC_ICDISR1_IRQ4_SHIFT (4u) -#define INTC_ICDISR1_IRQ5_SHIFT (5u) -#define INTC_ICDISR1_IRQ6_SHIFT (6u) -#define INTC_ICDISR1_IRQ7_SHIFT (7u) -#define INTC_ICDISR1_PL310ERR_SHIFT (8u) -#define INTC_ICDISR1_DMAINT0_SHIFT (9u) -#define INTC_ICDISR1_DMAINT1_SHIFT (10u) -#define INTC_ICDISR1_DMAINT2_SHIFT (11u) -#define INTC_ICDISR1_DMAINT3_SHIFT (12u) -#define INTC_ICDISR1_DMAINT4_SHIFT (13u) -#define INTC_ICDISR1_DMAINT5_SHIFT (14u) -#define INTC_ICDISR1_DMAINT6_SHIFT (15u) -#define INTC_ICDISR1_DMAINT7_SHIFT (16u) -#define INTC_ICDISR1_DMAINT8_SHIFT (17u) -#define INTC_ICDISR1_DMAINT9_SHIFT (18u) -#define INTC_ICDISR1_DMAINT10_SHIFT (19u) -#define INTC_ICDISR1_DMAINT11_SHIFT (20u) -#define INTC_ICDISR1_DMAINT12_SHIFT (21u) -#define INTC_ICDISR1_DMAINT13_SHIFT (22u) -#define INTC_ICDISR1_DMAINT14_SHIFT (23u) -#define INTC_ICDISR1_DMAINT15_SHIFT (24u) -#define INTC_ICDISR1_DMAERR_SHIFT (25u) - -#define INTC_ICDISR2_USBI0_SHIFT (9u) -#define INTC_ICDISR2_USBI1_SHIFT (10u) -#define INTC_ICDISR2_S0_VI_VSYNC0_SHIFT (11u) -#define INTC_ICDISR2_S0_LO_VSYNC0_SHIFT (12u) -#define INTC_ICDISR2_S0_VSYNCERR0_SHIFT (13u) -#define INTC_ICDISR2_GR3_VLINE0_SHIFT (14u) -#define INTC_ICDISR2_S0_VFIELD0_SHIFT (15u) -#define INTC_ICDISR2_IV1_VBUFERR0_SHIFT (16u) -#define INTC_ICDISR2_IV3_VBUFERR0_SHIFT (17u) -#define INTC_ICDISR2_IV5_VBUFERR0_SHIFT (18u) -#define INTC_ICDISR2_IV6_VBUFERR0_SHIFT (19u) -#define INTC_ICDISR2_S0_WLINE0_SHIFT (20u) -#define INTC_ICDISR2_S1_VI_VSYNC0_SHIFT (21u) -#define INTC_ICDISR2_S1_LO_VSYNC0_SHIFT (22u) -#define INTC_ICDISR2_S1_VSYNCERR0_SHIFT (23u) -#define INTC_ICDISR2_S1_VFIELD0_SHIFT (24u) -#define INTC_ICDISR2_IV2_VBUFERR0_SHIFT (25u) -#define INTC_ICDISR2_IV4_VBUFERR0_SHIFT (26u) -#define INTC_ICDISR2_S1_WLINE0_SHIFT (27u) -#define INTC_ICDISR2_OIR_VI_VSYNC0_SHIFT (28u) -#define INTC_ICDISR2_OIR_LO_VSYNC0_SHIFT (29u) -#define INTC_ICDISR2_OIR_VSYNCERR0_SHIFT (30u) -#define INTC_ICDISR2_OIR_VFIELD0_SHIFT (31u) - -#define INTC_ICDISR3_IV7_VBUFERR0_SHIFT (0u) -#define INTC_ICDISR3_IV8_VBUFERR0_SHIFT (1u) -#define INTC_ICDISR3_S0_VI_VSYNC1_SHIFT (3u) -#define INTC_ICDISR3_S0_LO_VSYNC1_SHIFT (4u) -#define INTC_ICDISR3_S0_VSYNCERR1_SHIFT (5u) -#define INTC_ICDISR3_GR3_VLINE1_SHIFT (6u) -#define INTC_ICDISR3_S0_VFIELD1_SHIFT (7u) -#define INTC_ICDISR3_IV1_VBUFERR1_SHIFT (8u) -#define INTC_ICDISR3_IV3_VBUFERR1_SHIFT (9u) -#define INTC_ICDISR3_IV5_VBUFERR1_SHIFT (10u) -#define INTC_ICDISR3_IV6_VBUFERR1_SHIFT (11u) -#define INTC_ICDISR3_S0_WLINE1_SHIFT (12u) -#define INTC_ICDISR3_S1_VI_VSYNC1_SHIFT (13u) -#define INTC_ICDISR3_S1_LO_VSYNC1_SHIFT (14u) -#define INTC_ICDISR3_S1_VSYNCERR1_SHIFT (15u) -#define INTC_ICDISR3_S1_VFIELD1_SHIFT (16u) -#define INTC_ICDISR3_IV2_VBUFERR1_SHIFT (17u) -#define INTC_ICDISR3_IV4_VBUFERR1_SHIFT (18u) -#define INTC_ICDISR3_S1_WLINE1_SHIFT (19u) -#define INTC_ICDISR3_OIR_VI_VSYNC1_SHIFT (20u) -#define INTC_ICDISR3_OIR_LO_VSYNC1_SHIFT (21u) -#define INTC_ICDISR3_OIR_VLINE1_SHIFT (22u) -#define INTC_ICDISR3_OIR_VFIELD1_SHIFT (23u) -#define INTC_ICDISR3_IV7_VBUFERR1_SHIFT (24u) -#define INTC_ICDISR3_IV8_VBUFERR1_SHIFT (25u) -#define INTC_ICDISR3_IMRDI_SHIFT (27u) -#define INTC_ICDISR3_IMR2I0_SHIFT (28u) -#define INTC_ICDISR3_IMR2I1_SHIFT (29u) -#define INTC_ICDISR3_JEDI_SHIFT (30u) -#define INTC_ICDISR3_JDTI_SHIFT (31u) - -#define INTC_ICDISR4_CMP0_SHIFT (0u) -#define INTC_ICDISR4_CMP1_SHIFT (1u) -#define INTC_ICDISR4_INT0_SHIFT (2u) -#define INTC_ICDISR4_INT1_SHIFT (3u) -#define INTC_ICDISR4_INT2_SHIFT (4u) -#define INTC_ICDISR4_INT3_SHIFT (5u) -#define INTC_ICDISR4_OSTM0TINT_SHIFT (6u) -#define INTC_ICDISR4_OSTM1TINT_SHIFT (7u) -#define INTC_ICDISR4_CMI_SHIFT (8u) -#define INTC_ICDISR4_WTOUT_SHIFT (9u) -#define INTC_ICDISR4_ITI_SHIFT (10u) -#define INTC_ICDISR4_TGI0A_SHIFT (11u) -#define INTC_ICDISR4_TGI0B_SHIFT (12u) -#define INTC_ICDISR4_TGI0C_SHIFT (13u) -#define INTC_ICDISR4_TGI0D_SHIFT (14u) -#define INTC_ICDISR4_TGI0V_SHIFT (15u) -#define INTC_ICDISR4_TGI0E_SHIFT (16u) -#define INTC_ICDISR4_TGI0F_SHIFT (17u) -#define INTC_ICDISR4_TGI1A_SHIFT (18u) -#define INTC_ICDISR4_TGI1B_SHIFT (19u) -#define INTC_ICDISR4_TGI1V_SHIFT (20u) -#define INTC_ICDISR4_TGI1U_SHIFT (21u) -#define INTC_ICDISR4_TGI2A_SHIFT (22u) -#define INTC_ICDISR4_TGI2B_SHIFT (23u) -#define INTC_ICDISR4_TGI2V_SHIFT (24u) -#define INTC_ICDISR4_TGI2U_SHIFT (25u) -#define INTC_ICDISR4_TGI3A_SHIFT (26u) -#define INTC_ICDISR4_TGI3B_SHIFT (27u) -#define INTC_ICDISR4_TGI3C_SHIFT (28u) -#define INTC_ICDISR4_TGI3D_SHIFT (29u) -#define INTC_ICDISR4_TGI3V_SHIFT (30u) -#define INTC_ICDISR4_TGI4A_SHIFT (31u) - -#define INTC_ICDISR5_TGI4B_SHIFT (0u) -#define INTC_ICDISR5_TGI4C_SHIFT (1u) -#define INTC_ICDISR5_TGI4D_SHIFT (2u) -#define INTC_ICDISR5_TGI4V_SHIFT (3u) -#define INTC_ICDISR5_CMI1_SHIFT (4u) -#define INTC_ICDISR5_CMI2_SHIFT (5u) -#define INTC_ICDISR5_SGDEI0_SHIFT (6u) -#define INTC_ICDISR5_SGDEI1_SHIFT (7u) -#define INTC_ICDISR5_SGDEI2_SHIFT (8u) -#define INTC_ICDISR5_SGDEI3_SHIFT (9u) -#define INTC_ICDISR5_ADI_SHIFT (10u) -#define INTC_ICDISR5_LMTI_SHIFT (11u) -#define INTC_ICDISR5_SSII0_SHIFT (12u) -#define INTC_ICDISR5_SSIRXI0_SHIFT (13u) -#define INTC_ICDISR5_SSITXI0_SHIFT (14u) -#define INTC_ICDISR5_SSII1_SHIFT (15u) -#define INTC_ICDISR5_SSIRXI1_SHIFT (16u) -#define INTC_ICDISR5_SSITXI1_SHIFT (17u) -#define INTC_ICDISR5_SSII2_SHIFT (18u) -#define INTC_ICDISR5_SSIRTI2_SHIFT (19u) -#define INTC_ICDISR5_SSII3_SHIFT (20u) -#define INTC_ICDISR5_SSIRXI3_SHIFT (21u) -#define INTC_ICDISR5_SSITXI3_SHIFT (22u) -#define INTC_ICDISR5_SSII4_SHIFT (23u) -#define INTC_ICDISR5_SSIRTI4_SHIFT (24u) -#define INTC_ICDISR5_SSII5_SHIFT (25u) -#define INTC_ICDISR5_SSIRXI5_SHIFT (26u) -#define INTC_ICDISR5_SSITXI5_SHIFT (27u) -#define INTC_ICDISR5_SPDIFI_SHIFT (28u) -#define INTC_ICDISR5_INTIICTEI0_SHIFT (29u) -#define INTC_ICDISR5_INTIICRI0_SHIFT (30u) -#define INTC_ICDISR5_INTIICTI0_SHIFT (31u) - -#define INTC_ICDISR6_INTIICSPI0_SHIFT (0u) -#define INTC_ICDISR6_INTIICSTI0_SHIFT (1u) -#define INTC_ICDISR6_INTIICNAKI0_SHIFT (2u) -#define INTC_ICDISR6_INTIICALI0_SHIFT (3u) -#define INTC_ICDISR6_INTIICTMOI0_SHIFT (4u) -#define INTC_ICDISR6_INTIICTEI1_SHIFT (5u) -#define INTC_ICDISR6_INTIICRI1_SHIFT (6u) -#define INTC_ICDISR6_INTIICTI1_SHIFT (7u) -#define INTC_ICDISR6_INTIICSPI1_SHIFT (8u) -#define INTC_ICDISR6_INTIICSTI1_SHIFT (9u) -#define INTC_ICDISR6_INTIICNAKI1_SHIFT (10u) -#define INTC_ICDISR6_INTIICALI1_SHIFT (11u) -#define INTC_ICDISR6_INTIICTMOI1_SHIFT (12u) -#define INTC_ICDISR6_INTIICTEI2_SHIFT (13u) -#define INTC_ICDISR6_INTIICRI2_SHIFT (14u) -#define INTC_ICDISR6_INTIICTI2_SHIFT (15u) -#define INTC_ICDISR6_INTIICSPI2_SHIFT (16u) -#define INTC_ICDISR6_INTIICSTI2_SHIFT (17u) -#define INTC_ICDISR6_INTIICNAKI2_SHIFT (18u) -#define INTC_ICDISR6_INTIICALI2_SHIFT (19u) -#define INTC_ICDISR6_INTIICTMOI2_SHIFT (20u) -#define INTC_ICDISR6_INTIICTEI3_SHIFT (21u) -#define INTC_ICDISR6_INTIICRI3_SHIFT (22u) -#define INTC_ICDISR6_INTIICTI3_SHIFT (23u) -#define INTC_ICDISR6_INTIICSPI3_SHIFT (24u) -#define INTC_ICDISR6_INTIICSTI3_SHIFT (25u) -#define INTC_ICDISR6_INTIICNAKI3_SHIFT (26u) -#define INTC_ICDISR6_INTIICALI3_SHIFT (27u) -#define INTC_ICDISR6_INTIICTMOI3_SHIFT (28u) -#define INTC_ICDISR6_BRI0_SHIFT (29u) -#define INTC_ICDISR6_ERI0_SHIFT (30u) -#define INTC_ICDISR6_RXI0_SHIFT (31u) - -#define INTC_ICDISR7_TXI0_SHIFT (0u) -#define INTC_ICDISR7_BRI1_SHIFT (1u) -#define INTC_ICDISR7_ERI1_SHIFT (2u) -#define INTC_ICDISR7_RXI1_SHIFT (3u) -#define INTC_ICDISR7_TXI1_SHIFT (4u) -#define INTC_ICDISR7_BRI2_SHIFT (5u) -#define INTC_ICDISR7_ERI2_SHIFT (6u) -#define INTC_ICDISR7_RXI2_SHIFT (7u) -#define INTC_ICDISR7_TXI2_SHIFT (8u) -#define INTC_ICDISR7_BRI3_SHIFT (9u) -#define INTC_ICDISR7_ERI3_SHIFT (10u) -#define INTC_ICDISR7_RXI3_SHIFT (11u) -#define INTC_ICDISR7_TXI3_SHIFT (12u) -#define INTC_ICDISR7_BRI4_SHIFT (13u) -#define INTC_ICDISR7_ERI4_SHIFT (14u) -#define INTC_ICDISR7_RXI4_SHIFT (15u) -#define INTC_ICDISR7_TXI4_SHIFT (16u) -#define INTC_ICDISR7_BRI5_SHIFT (17u) -#define INTC_ICDISR7_ERI5_SHIFT (18u) -#define INTC_ICDISR7_RXI5_SHIFT (19u) -#define INTC_ICDISR7_TXI5_SHIFT (20u) -#define INTC_ICDISR7_BRI6_SHIFT (21u) -#define INTC_ICDISR7_ERI6_SHIFT (22u) -#define INTC_ICDISR7_RXI6_SHIFT (23u) -#define INTC_ICDISR7_TXI6_SHIFT (24u) -#define INTC_ICDISR7_BRI7_SHIFT (25u) -#define INTC_ICDISR7_ERI7_SHIFT (26u) -#define INTC_ICDISR7_RXI7_SHIFT (27u) -#define INTC_ICDISR7_TXI7_SHIFT (28u) -#define INTC_ICDISR7_INTRCANGERR_SHIFT (29u) -#define INTC_ICDISR7_INTRCANGRECC_SHIFT (30u) -#define INTC_ICDISR7_INTRCAN0REC_SHIFT (31u) - -#define INTC_ICDISR8_INTRCAN0ERR_SHIFT (0u) -#define INTC_ICDISR8_INTRCAN0TRX_SHIFT (1u) -#define INTC_ICDISR8_INTRCAN1REC_SHIFT (2u) -#define INTC_ICDISR8_INTRCAN1ERR_SHIFT (3u) -#define INTC_ICDISR8_INTRCAN1TRX_SHIFT (4u) -#define INTC_ICDISR8_INTRCAN2REC_SHIFT (5u) -#define INTC_ICDISR8_INTRCAN2ERR_SHIFT (6u) -#define INTC_ICDISR8_INTRCAN2TRX_SHIFT (7u) -#define INTC_ICDISR8_INTRCAN3REC_SHIFT (8u) -#define INTC_ICDISR8_INTRCAN3ERR_SHIFT (9u) -#define INTC_ICDISR8_INTRCAN3TRX_SHIFT (10u) -#define INTC_ICDISR8_INTRCAN4REC_SHIFT (11u) -#define INTC_ICDISR8_INTRCAN4ERR_SHIFT (12u) -#define INTC_ICDISR8_INTRCAN4TRX_SHIFT (13u) -#define INTC_ICDISR8_SPEI0_SHIFT (14u) -#define INTC_ICDISR8_SPRI0_SHIFT (15u) -#define INTC_ICDISR8_SPTI0_SHIFT (16u) -#define INTC_ICDISR8_SPEI1_SHIFT (17u) -#define INTC_ICDISR8_SPRI1_SHIFT (18u) -#define INTC_ICDISR8_SPTI1_SHIFT (19u) -#define INTC_ICDISR8_SPEI2_SHIFT (20u) -#define INTC_ICDISR8_SPRI2_SHIFT (21u) -#define INTC_ICDISR8_SPTI2_SHIFT (22u) -#define INTC_ICDISR8_SPEI3_SHIFT (23u) -#define INTC_ICDISR8_SPRI3_SHIFT (24u) -#define INTC_ICDISR8_SPTI3_SHIFT (25u) -#define INTC_ICDISR8_SPEI4_SHIFT (26u) -#define INTC_ICDISR8_SPRI4_SHIFT (27u) -#define INTC_ICDISR8_SPTI4_SHIFT (28u) -#define INTC_ICDISR8_IEBBTD_SHIFT (29u) -#define INTC_ICDISR8_IEBBTERR_SHIFT (30u) -#define INTC_ICDISR8_IEBBTSTA_SHIFT (31u) - -#define INTC_ICDISR9_IEBBTV_SHIFT (0u) -#define INTC_ICDISR9_ISY_SHIFT (1u) -#define INTC_ICDISR9_IERR_SHIFT (2u) -#define INTC_ICDISR9_ITARG_SHIFT (3u) -#define INTC_ICDISR9_ISEC_SHIFT (4u) -#define INTC_ICDISR9_IBUF_SHIFT (5u) -#define INTC_ICDISR9_IREADY_SHIFT (6u) -#define INTC_ICDISR9_FLSTE_SHIFT (7u) -#define INTC_ICDISR9_FLTENDI_SHIFT (8u) -#define INTC_ICDISR9_FLTREQ0I_SHIFT (9u) -#define INTC_ICDISR9_FLTREQ1I_SHIFT (10u) -#define INTC_ICDISR9_MMC0_SHIFT (11u) -#define INTC_ICDISR9_MMC1_SHIFT (12u) -#define INTC_ICDISR9_MMC2_SHIFT (13u) -#define INTC_ICDISR9_SDHI0_3_SHIFT (14u) -#define INTC_ICDISR9_SDHI0_0_SHIFT (15u) -#define INTC_ICDISR9_SDHI0_1_SHIFT (16u) -#define INTC_ICDISR9_SDHI1_3_SHIFT (17u) -#define INTC_ICDISR9_SDHI1_0_SHIFT (18u) -#define INTC_ICDISR9_SDHI1_1_SHIFT (19u) -#define INTC_ICDISR9_ARM_SHIFT (20u) -#define INTC_ICDISR9_PRD_SHIFT (21u) -#define INTC_ICDISR9_CUP_SHIFT (22u) -#define INTC_ICDISR9_SCUAI0_SHIFT (23u) -#define INTC_ICDISR9_SCUAI1_SHIFT (24u) -#define INTC_ICDISR9_SCUFDI0_SHIFT (25u) -#define INTC_ICDISR9_SCUFDI1_SHIFT (26u) -#define INTC_ICDISR9_SCUFDI2_SHIFT (27u) -#define INTC_ICDISR9_SCUFDI3_SHIFT (28u) -#define INTC_ICDISR9_SCUFUI0_SHIFT (29u) -#define INTC_ICDISR9_SCUFUI1_SHIFT (30u) -#define INTC_ICDISR9_SCUFUI2_SHIFT (31u) - -#define INTC_ICDISR10_SCUFUI3_SHIFT (0u) -#define INTC_ICDISR10_SCUDVI0_SHIFT (1u) -#define INTC_ICDISR10_SCUDVI1_SHIFT (2u) -#define INTC_ICDISR10_SCUDVI2_SHIFT (3u) -#define INTC_ICDISR10_SCUDVI3_SHIFT (4u) -#define INTC_ICDISR10_MLB_CINT_SHIFT (5u) -#define INTC_ICDISR10_MLB_SINT_SHIFT (6u) -#define INTC_ICDISR10_DRC0_SHIFT (7u) -#define INTC_ICDISR10_DRC1_SHIFT (8u) -#define INTC_ICDISR10_LINI0_INT_T_SHIFT (11u) -#define INTC_ICDISR10_LINI0_INT_R_SHIFT (12u) -#define INTC_ICDISR10_LINI0_INT_S_SHIFT (13u) -#define INTC_ICDISR10_LINI0_INT_M_SHIFT (14u) -#define INTC_ICDISR10_LINI1_INT_T_SHIFT (15u) -#define INTC_ICDISR10_LINI1_INT_R_SHIFT (16u) -#define INTC_ICDISR10_LINI1_INT_S_SHIFT (17u) -#define INTC_ICDISR10_LINI1_INT_M_SHIFT (18u) -#define INTC_ICDISR10_ERI0_SHIFT (27u) -#define INTC_ICDISR10_RXI0_SHIFT (28u) -#define INTC_ICDISR10_TXI0_SHIFT (29u) -#define INTC_ICDISR10_TEI0_SHIFT (30u) -#define INTC_ICDISR10_ERI1_SHIFT (31u) - -#define INTC_ICDISR11_RXI1_SHIFT (0u) -#define INTC_ICDISR11_TXI1_SHIFT (1u) -#define INTC_ICDISR11_TEI1_SHIFT (2u) -#define INTC_ICDISR11_AVBI_DATA_SHIFT (3u) -#define INTC_ICDISR11_AVBI_ERROR_SHIFT (4u) -#define INTC_ICDISR11_AVBI_MANAGE_SHIFT (5u) -#define INTC_ICDISR11_AVBI_MAC_SHIFT (6u) -#define INTC_ICDISR11_ETHERI_SHIFT (7u) -#define INTC_ICDISR11_CEUI_SHIFT (12u) -#define INTC_ICDISR11_H2XMLB_ERRINT_SHIFT (29u) -#define INTC_ICDISR11_H2XIC1_ERRINT_SHIFT (30u) -#define INTC_ICDISR11_X2HPERI1_ERRINT_SHIFT (31u) - -#define INTC_ICDISR12_X2HPERI2_ERRINT_SHIFT (0u) -#define INTC_ICDISR12_X2HPERI34_ERRINT_SHIFT (1u) -#define INTC_ICDISR12_X2HPERI5_ERRINT_SHIFT (2u) -#define INTC_ICDISR12_X2HPERI67_ERRINT_SHIFT (3u) -#define INTC_ICDISR12_X2HDBGR_ERRINT_SHIFT (4u) -#define INTC_ICDISR12_X2HBSC_ERRINT_SHIFT (5u) -#define INTC_ICDISR12_X2HSPI1_ERRINT_SHIFT (6u) -#define INTC_ICDISR12_X2HSPI2_ERRINT_SHIFT (7u) -#define INTC_ICDISR12_PRRI_SHIFT (8u) -#define INTC_ICDISR12_IFEI0_SHIFT (9u) -#define INTC_ICDISR12_OFFI0_SHIFT (10u) -#define INTC_ICDISR12_PFVEI0_SHIFT (11u) -#define INTC_ICDISR12_IFEI1_SHIFT (12u) -#define INTC_ICDISR12_OFFI1_SHIFT (13u) -#define INTC_ICDISR12_PFVEI1_SHIFT (14u) - -#define INTC_ICDISR13_TINT0_SHIFT (0u) -#define INTC_ICDISR13_TINT1_SHIFT (1u) -#define INTC_ICDISR13_TINT2_SHIFT (2u) -#define INTC_ICDISR13_TINT3_SHIFT (3u) -#define INTC_ICDISR13_TINT4_SHIFT (4u) -#define INTC_ICDISR13_TINT5_SHIFT (5u) -#define INTC_ICDISR13_TINT6_SHIFT (6u) -#define INTC_ICDISR13_TINT7_SHIFT (7u) -#define INTC_ICDISR13_TINT8_SHIFT (8u) -#define INTC_ICDISR13_TINT9_SHIFT (9u) -#define INTC_ICDISR13_TINT10_SHIFT (10u) -#define INTC_ICDISR13_TINT11_SHIFT (11u) -#define INTC_ICDISR13_TINT12_SHIFT (12u) -#define INTC_ICDISR13_TINT13_SHIFT (13u) -#define INTC_ICDISR13_TINT14_SHIFT (14u) -#define INTC_ICDISR13_TINT15_SHIFT (15u) -#define INTC_ICDISR13_TINT16_SHIFT (16u) -#define INTC_ICDISR13_TINT17_SHIFT (17u) -#define INTC_ICDISR13_TINT18_SHIFT (18u) -#define INTC_ICDISR13_TINT19_SHIFT (19u) -#define INTC_ICDISR13_TINT20_SHIFT (20u) -#define INTC_ICDISR13_TINT21_SHIFT (21u) -#define INTC_ICDISR13_TINT22_SHIFT (22u) -#define INTC_ICDISR13_TINT23_SHIFT (23u) -#define INTC_ICDISR13_TINT24_SHIFT (24u) -#define INTC_ICDISR13_TINT25_SHIFT (25u) -#define INTC_ICDISR13_TINT26_SHIFT (26u) -#define INTC_ICDISR13_TINT27_SHIFT (27u) -#define INTC_ICDISR13_TINT28_SHIFT (28u) -#define INTC_ICDISR13_TINT29_SHIFT (29u) -#define INTC_ICDISR13_TINT30_SHIFT (30u) -#define INTC_ICDISR13_TINT31_SHIFT (31u) - -#define INTC_ICDISR14_TINT32_SHIFT (0u) -#define INTC_ICDISR14_TINT33_SHIFT (1u) -#define INTC_ICDISR14_TINT34_SHIFT (2u) -#define INTC_ICDISR14_TINT35_SHIFT (3u) -#define INTC_ICDISR14_TINT36_SHIFT (4u) -#define INTC_ICDISR14_TINT37_SHIFT (5u) -#define INTC_ICDISR14_TINT38_SHIFT (6u) -#define INTC_ICDISR14_TINT39_SHIFT (7u) -#define INTC_ICDISR14_TINT40_SHIFT (8u) -#define INTC_ICDISR14_TINT41_SHIFT (9u) -#define INTC_ICDISR14_TINT42_SHIFT (10u) -#define INTC_ICDISR14_TINT43_SHIFT (11u) -#define INTC_ICDISR14_TINT44_SHIFT (12u) -#define INTC_ICDISR14_TINT45_SHIFT (13u) -#define INTC_ICDISR14_TINT46_SHIFT (14u) -#define INTC_ICDISR14_TINT47_SHIFT (15u) -#define INTC_ICDISR14_TINT48_SHIFT (16u) -#define INTC_ICDISR14_TINT49_SHIFT (17u) -#define INTC_ICDISR14_TINT50_SHIFT (18u) -#define INTC_ICDISR14_TINT51_SHIFT (19u) -#define INTC_ICDISR14_TINT52_SHIFT (20u) -#define INTC_ICDISR14_TINT53_SHIFT (21u) -#define INTC_ICDISR14_TINT54_SHIFT (22u) -#define INTC_ICDISR14_TINT55_SHIFT (23u) -#define INTC_ICDISR14_TINT56_SHIFT (24u) -#define INTC_ICDISR14_TINT57_SHIFT (25u) -#define INTC_ICDISR14_TINT58_SHIFT (26u) -#define INTC_ICDISR14_TINT59_SHIFT (27u) -#define INTC_ICDISR14_TINT60_SHIFT (28u) -#define INTC_ICDISR14_TINT61_SHIFT (29u) -#define INTC_ICDISR14_TINT62_SHIFT (30u) -#define INTC_ICDISR14_TINT63_SHIFT (31u) - -#define INTC_ICDISR15_TINT64_SHIFT (0u) -#define INTC_ICDISR15_TINT65_SHIFT (1u) -#define INTC_ICDISR15_TINT66_SHIFT (2u) -#define INTC_ICDISR15_TINT67_SHIFT (3u) -#define INTC_ICDISR15_TINT68_SHIFT (4u) -#define INTC_ICDISR15_TINT69_SHIFT (5u) -#define INTC_ICDISR15_TINT70_SHIFT (6u) -#define INTC_ICDISR15_TINT71_SHIFT (7u) -#define INTC_ICDISR15_TINT72_SHIFT (8u) -#define INTC_ICDISR15_TINT73_SHIFT (9u) -#define INTC_ICDISR15_TINT74_SHIFT (10u) -#define INTC_ICDISR15_TINT75_SHIFT (11u) -#define INTC_ICDISR15_TINT76_SHIFT (12u) -#define INTC_ICDISR15_TINT77_SHIFT (13u) -#define INTC_ICDISR15_TINT78_SHIFT (14u) -#define INTC_ICDISR15_TINT79_SHIFT (15u) -#define INTC_ICDISR15_TINT80_SHIFT (16u) -#define INTC_ICDISR15_TINT81_SHIFT (17u) -#define INTC_ICDISR15_TINT82_SHIFT (18u) -#define INTC_ICDISR15_TINT83_SHIFT (19u) -#define INTC_ICDISR15_TINT84_SHIFT (20u) -#define INTC_ICDISR15_TINT85_SHIFT (21u) -#define INTC_ICDISR15_TINT86_SHIFT (22u) -#define INTC_ICDISR15_TINT87_SHIFT (23u) -#define INTC_ICDISR15_TINT88_SHIFT (24u) -#define INTC_ICDISR15_TINT89_SHIFT (25u) -#define INTC_ICDISR15_TINT90_SHIFT (26u) -#define INTC_ICDISR15_TINT91_SHIFT (27u) -#define INTC_ICDISR15_TINT92_SHIFT (28u) -#define INTC_ICDISR15_TINT93_SHIFT (29u) -#define INTC_ICDISR15_TINT94_SHIFT (30u) -#define INTC_ICDISR15_TINT95_SHIFT (31u) - -#define INTC_ICDISR16_TINT96_SHIFT (0u) -#define INTC_ICDISR16_TINT97_SHIFT (1u) -#define INTC_ICDISR16_TINT98_SHIFT (2u) -#define INTC_ICDISR16_TINT99_SHIFT (3u) -#define INTC_ICDISR16_TINT100_SHIFT (4u) -#define INTC_ICDISR16_TINT101_SHIFT (5u) -#define INTC_ICDISR16_TINT102_SHIFT (6u) -#define INTC_ICDISR16_TINT103_SHIFT (7u) -#define INTC_ICDISR16_TINT104_SHIFT (8u) -#define INTC_ICDISR16_TINT105_SHIFT (9u) -#define INTC_ICDISR16_TINT106_SHIFT (10u) -#define INTC_ICDISR16_TINT107_SHIFT (11u) -#define INTC_ICDISR16_TINT108_SHIFT (12u) -#define INTC_ICDISR16_TINT109_SHIFT (13u) -#define INTC_ICDISR16_TINT110_SHIFT (14u) -#define INTC_ICDISR16_TINT111_SHIFT (15u) -#define INTC_ICDISR16_TINT112_SHIFT (16u) -#define INTC_ICDISR16_TINT113_SHIFT (17u) -#define INTC_ICDISR16_TINT114_SHIFT (18u) -#define INTC_ICDISR16_TINT115_SHIFT (19u) -#define INTC_ICDISR16_TINT116_SHIFT (20u) -#define INTC_ICDISR16_TINT117_SHIFT (21u) -#define INTC_ICDISR16_TINT118_SHIFT (22u) -#define INTC_ICDISR16_TINT119_SHIFT (23u) -#define INTC_ICDISR16_TINT120_SHIFT (24u) -#define INTC_ICDISR16_TINT121_SHIFT (25u) -#define INTC_ICDISR16_TINT122_SHIFT (26u) -#define INTC_ICDISR16_TINT123_SHIFT (27u) -#define INTC_ICDISR16_TINT124_SHIFT (28u) -#define INTC_ICDISR16_TINT125_SHIFT (29u) -#define INTC_ICDISR16_TINT126_SHIFT (30u) -#define INTC_ICDISR16_TINT127_SHIFT (31u) - -#define INTC_ICDISR17_TINT128_SHIFT (0u) -#define INTC_ICDISR17_TINT129_SHIFT (1u) -#define INTC_ICDISR17_TINT130_SHIFT (2u) -#define INTC_ICDISR17_TINT131_SHIFT (3u) -#define INTC_ICDISR17_TINT132_SHIFT (4u) -#define INTC_ICDISR17_TINT133_SHIFT (5u) -#define INTC_ICDISR17_TINT134_SHIFT (6u) -#define INTC_ICDISR17_TINT135_SHIFT (7u) -#define INTC_ICDISR17_TINT136_SHIFT (8u) -#define INTC_ICDISR17_TINT137_SHIFT (9u) -#define INTC_ICDISR17_TINT138_SHIFT (10u) -#define INTC_ICDISR17_TINT139_SHIFT (11u) -#define INTC_ICDISR17_TINT140_SHIFT (12u) -#define INTC_ICDISR17_TINT141_SHIFT (13u) -#define INTC_ICDISR17_TINT142_SHIFT (14u) -#define INTC_ICDISR17_TINT143_SHIFT (15u) -#define INTC_ICDISR17_TINT144_SHIFT (16u) -#define INTC_ICDISR17_TINT145_SHIFT (17u) -#define INTC_ICDISR17_TINT146_SHIFT (18u) -#define INTC_ICDISR17_TINT147_SHIFT (19u) -#define INTC_ICDISR17_TINT148_SHIFT (20u) -#define INTC_ICDISR17_TINT149_SHIFT (21u) -#define INTC_ICDISR17_TINT150_SHIFT (22u) -#define INTC_ICDISR17_TINT151_SHIFT (23u) -#define INTC_ICDISR17_TINT152_SHIFT (24u) -#define INTC_ICDISR17_TINT153_SHIFT (25u) -#define INTC_ICDISR17_TINT154_SHIFT (26u) -#define INTC_ICDISR17_TINT155_SHIFT (27u) -#define INTC_ICDISR17_TINT156_SHIFT (28u) -#define INTC_ICDISR17_TINT157_SHIFT (29u) -#define INTC_ICDISR17_TINT158_SHIFT (30u) -#define INTC_ICDISR17_TINT159_SHIFT (31u) - -#define INTC_ICDISR18_TINT160_SHIFT (0u) -#define INTC_ICDISR18_TINT161_SHIFT (1u) -#define INTC_ICDISR18_TINT162_SHIFT (2u) -#define INTC_ICDISR18_TINT163_SHIFT (3u) -#define INTC_ICDISR18_TINT164_SHIFT (4u) -#define INTC_ICDISR18_TINT165_SHIFT (5u) -#define INTC_ICDISR18_TINT166_SHIFT (6u) -#define INTC_ICDISR18_TINT167_SHIFT (7u) -#define INTC_ICDISR18_TINT168_SHIFT (8u) -#define INTC_ICDISR18_TINT169_SHIFT (9u) -#define INTC_ICDISR18_TINT170_SHIFT (10u) - -#define INTC_ICDISER0_SW0_SHIFT (0u) -#define INTC_ICDISER0_SW1_SHIFT (1u) -#define INTC_ICDISER0_SW2_SHIFT (2u) -#define INTC_ICDISER0_SW3_SHIFT (3u) -#define INTC_ICDISER0_SW4_SHIFT (4u) -#define INTC_ICDISER0_SW5_SHIFT (5u) -#define INTC_ICDISER0_SW6_SHIFT (6u) -#define INTC_ICDISER0_SW7_SHIFT (7u) -#define INTC_ICDISER0_SW8_SHIFT (8u) -#define INTC_ICDISER0_SW9_SHIFT (9u) -#define INTC_ICDISER0_SW10_SHIFT (10u) -#define INTC_ICDISER0_SW11_SHIFT (11u) -#define INTC_ICDISER0_SW12_SHIFT (12u) -#define INTC_ICDISER0_SW13_SHIFT (13u) -#define INTC_ICDISER0_SW14_SHIFT (14u) -#define INTC_ICDISER0_SW15_SHIFT (15u) -#define INTC_ICDISER0_PMUIRQ0_SHIFT (16u) -#define INTC_ICDISER0_COMMRX0_SHIFT (17u) -#define INTC_ICDISER0_COMMTX0_SHIFT (18u) -#define INTC_ICDISER0_CTIIRQ0_SHIFT (19u) - -#define INTC_ICDISER1_IRQ0_SHIFT (0u) -#define INTC_ICDISER1_IRQ1_SHIFT (1u) -#define INTC_ICDISER1_IRQ2_SHIFT (2u) -#define INTC_ICDISER1_IRQ3_SHIFT (3u) -#define INTC_ICDISER1_IRQ4_SHIFT (4u) -#define INTC_ICDISER1_IRQ5_SHIFT (5u) -#define INTC_ICDISER1_IRQ6_SHIFT (6u) -#define INTC_ICDISER1_IRQ7_SHIFT (7u) -#define INTC_ICDISER1_PL310ERR_SHIFT (8u) -#define INTC_ICDISER1_DMAINT0_SHIFT (9u) -#define INTC_ICDISER1_DMAINT1_SHIFT (10u) -#define INTC_ICDISER1_DMAINT2_SHIFT (11u) -#define INTC_ICDISER1_DMAINT3_SHIFT (12u) -#define INTC_ICDISER1_DMAINT4_SHIFT (13u) -#define INTC_ICDISER1_DMAINT5_SHIFT (14u) -#define INTC_ICDISER1_DMAINT6_SHIFT (15u) -#define INTC_ICDISER1_DMAINT7_SHIFT (16u) -#define INTC_ICDISER1_DMAINT8_SHIFT (17u) -#define INTC_ICDISER1_DMAINT9_SHIFT (18u) -#define INTC_ICDISER1_DMAINT10_SHIFT (19u) -#define INTC_ICDISER1_DMAINT11_SHIFT (20u) -#define INTC_ICDISER1_DMAINT12_SHIFT (21u) -#define INTC_ICDISER1_DMAINT13_SHIFT (22u) -#define INTC_ICDISER1_DMAINT14_SHIFT (23u) -#define INTC_ICDISER1_DMAINT15_SHIFT (24u) -#define INTC_ICDISER1_DMAERR_SHIFT (25u) - -#define INTC_ICDISER2_USBI0_SHIFT (9u) -#define INTC_ICDISER2_USBI1_SHIFT (10u) -#define INTC_ICDISER2_S0_VI_VSYNC0_SHIFT (11u) -#define INTC_ICDISER2_S0_LO_VSYNC0_SHIFT (12u) -#define INTC_ICDISER2_S0_VSYNCERR0_SHIFT (13u) -#define INTC_ICDISER2_GR3_VLINE0_SHIFT (14u) -#define INTC_ICDISER2_S0_VFIELD0_SHIFT (15u) -#define INTC_ICDISER2_IV1_VBUFERR0_SHIFT (16u) -#define INTC_ICDISER2_IV3_VBUFERR0_SHIFT (17u) -#define INTC_ICDISER2_IV5_VBUFERR0_SHIFT (18u) -#define INTC_ICDISER2_IV6_VBUFERR0_SHIFT (19u) -#define INTC_ICDISER2_S0_WLINE0_SHIFT (20u) -#define INTC_ICDISER2_S1_VI_VSYNC0_SHIFT (21u) -#define INTC_ICDISER2_S1_LO_VSYNC0_SHIFT (22u) -#define INTC_ICDISER2_S1_VSYNCERR0_SHIFT (23u) -#define INTC_ICDISER2_S1_VFIELD0_SHIFT (24u) -#define INTC_ICDISER2_IV2_VBUFERR0_SHIFT (25u) -#define INTC_ICDISER2_IV4_VBUFERR0_SHIFT (26u) -#define INTC_ICDISER2_S1_WLINE0_SHIFT (27u) -#define INTC_ICDISER2_OIR_VI_VSYNC0_SHIFT (28u) -#define INTC_ICDISER2_OIR_LO_VSYNC0_SHIFT (29u) -#define INTC_ICDISER2_OIR_VSYNCERR0_SHIFT (30u) -#define INTC_ICDISER2_OIR_VFIELD0_SHIFT (31u) - -#define INTC_ICDISER3_IV7_VBUFERR0_SHIFT (0u) -#define INTC_ICDISER3_IV8_VBUFERR0_SHIFT (1u) -#define INTC_ICDISER3_S0_VI_VSYNC1_SHIFT (3u) -#define INTC_ICDISER3_S0_LO_VSYNC1_SHIFT (4u) -#define INTC_ICDISER3_S0_VSYNCERR1_SHIFT (5u) -#define INTC_ICDISER3_GR3_VLINE1_SHIFT (6u) -#define INTC_ICDISER3_S0_VFIELD1_SHIFT (7u) -#define INTC_ICDISER3_IV1_VBUFERR1_SHIFT (8u) -#define INTC_ICDISER3_IV3_VBUFERR1_SHIFT (9u) -#define INTC_ICDISER3_IV5_VBUFERR1_SHIFT (10u) -#define INTC_ICDISER3_IV6_VBUFERR1_SHIFT (11u) -#define INTC_ICDISER3_S0_WLINE1_SHIFT (12u) -#define INTC_ICDISER3_S1_VI_VSYNC1_SHIFT (13u) -#define INTC_ICDISER3_S1_LO_VSYNC1_SHIFT (14u) -#define INTC_ICDISER3_S1_VSYNCERR1_SHIFT (15u) -#define INTC_ICDISER3_S1_VFIELD1_SHIFT (16u) -#define INTC_ICDISER3_IV2_VBUFERR1_SHIFT (17u) -#define INTC_ICDISER3_IV4_VBUFERR1_SHIFT (18u) -#define INTC_ICDISER3_S1_WLINE1_SHIFT (19u) -#define INTC_ICDISER3_OIR_VI_VSYNC1_SHIFT (20u) -#define INTC_ICDISER3_OIR_LO_VSYNC1_SHIFT (21u) -#define INTC_ICDISER3_OIR_VLINE1_SHIFT (22u) -#define INTC_ICDISER3_OIR_VFIELD1_SHIFT (23u) -#define INTC_ICDISER3_IV7_VBUFERR1_SHIFT (24u) -#define INTC_ICDISER3_IV8_VBUFERR1_SHIFT (25u) -#define INTC_ICDISER3_IMRDI_SHIFT (27u) -#define INTC_ICDISER3_IMR2I0_SHIFT (28u) -#define INTC_ICDISER3_IMR2I1_SHIFT (29u) -#define INTC_ICDISER3_JEDI_SHIFT (30u) -#define INTC_ICDISER3_JDTI_SHIFT (31u) - -#define INTC_ICDISER4_CMP0_SHIFT (0u) -#define INTC_ICDISER4_CMP1_SHIFT (1u) -#define INTC_ICDISER4_INT0_SHIFT (2u) -#define INTC_ICDISER4_INT1_SHIFT (3u) -#define INTC_ICDISER4_INT2_SHIFT (4u) -#define INTC_ICDISER4_INT3_SHIFT (5u) -#define INTC_ICDISER4_OSTM0TINT_SHIFT (6u) -#define INTC_ICDISER4_OSTM1TINT_SHIFT (7u) -#define INTC_ICDISER4_CMI_SHIFT (8u) -#define INTC_ICDISER4_WTOUT_SHIFT (9u) -#define INTC_ICDISER4_ITI_SHIFT (10u) -#define INTC_ICDISER4_TGI0A_SHIFT (11u) -#define INTC_ICDISER4_TGI0B_SHIFT (12u) -#define INTC_ICDISER4_TGI0C_SHIFT (13u) -#define INTC_ICDISER4_TGI0D_SHIFT (14u) -#define INTC_ICDISER4_TGI0V_SHIFT (15u) -#define INTC_ICDISER4_TGI0E_SHIFT (16u) -#define INTC_ICDISER4_TGI0F_SHIFT (17u) -#define INTC_ICDISER4_TGI1A_SHIFT (18u) -#define INTC_ICDISER4_TGI1B_SHIFT (19u) -#define INTC_ICDISER4_TGI1V_SHIFT (20u) -#define INTC_ICDISER4_TGI1U_SHIFT (21u) -#define INTC_ICDISER4_TGI2A_SHIFT (22u) -#define INTC_ICDISER4_TGI2B_SHIFT (23u) -#define INTC_ICDISER4_TGI2V_SHIFT (24u) -#define INTC_ICDISER4_TGI2U_SHIFT (25u) -#define INTC_ICDISER4_TGI3A_SHIFT (26u) -#define INTC_ICDISER4_TGI3B_SHIFT (27u) -#define INTC_ICDISER4_TGI3C_SHIFT (28u) -#define INTC_ICDISER4_TGI3D_SHIFT (29u) -#define INTC_ICDISER4_TGI3V_SHIFT (30u) -#define INTC_ICDISER4_TGI4A_SHIFT (31u) - -#define INTC_ICDISER5_TGI4B_SHIFT (0u) -#define INTC_ICDISER5_TGI4C_SHIFT (1u) -#define INTC_ICDISER5_TGI4D_SHIFT (2u) -#define INTC_ICDISER5_TGI4V_SHIFT (3u) -#define INTC_ICDISER5_CMI1_SHIFT (4u) -#define INTC_ICDISER5_CMI2_SHIFT (5u) -#define INTC_ICDISER5_SGDEI0_SHIFT (6u) -#define INTC_ICDISER5_SGDEI1_SHIFT (7u) -#define INTC_ICDISER5_SGDEI2_SHIFT (8u) -#define INTC_ICDISER5_SGDEI3_SHIFT (9u) -#define INTC_ICDISER5_ADI_SHIFT (10u) -#define INTC_ICDISER5_LMTI_SHIFT (11u) -#define INTC_ICDISER5_SSII0_SHIFT (12u) -#define INTC_ICDISER5_SSIRXI0_SHIFT (13u) -#define INTC_ICDISER5_SSITXI0_SHIFT (14u) -#define INTC_ICDISER5_SSII1_SHIFT (15u) -#define INTC_ICDISER5_SSIRXI1_SHIFT (16u) -#define INTC_ICDISER5_SSITXI1_SHIFT (17u) -#define INTC_ICDISER5_SSII2_SHIFT (18u) -#define INTC_ICDISER5_SSIRTI2_SHIFT (19u) -#define INTC_ICDISER5_SSII3_SHIFT (20u) -#define INTC_ICDISER5_SSIRXI3_SHIFT (21u) -#define INTC_ICDISER5_SSITXI3_SHIFT (22u) -#define INTC_ICDISER5_SSII4_SHIFT (23u) -#define INTC_ICDISER5_SSIRTI4_SHIFT (24u) -#define INTC_ICDISER5_SSII5_SHIFT (25u) -#define INTC_ICDISER5_SSIRXI5_SHIFT (26u) -#define INTC_ICDISER5_SSITXI5_SHIFT (27u) -#define INTC_ICDISER5_SPDIFI_SHIFT (28u) -#define INTC_ICDISER5_INTIICTEI0_SHIFT (29u) -#define INTC_ICDISER5_INTIICRI0_SHIFT (30u) -#define INTC_ICDISER5_INTIICTI0_SHIFT (31u) - -#define INTC_ICDISER6_INTIICSPI0_SHIFT (0u) -#define INTC_ICDISER6_INTIICSTI0_SHIFT (1u) -#define INTC_ICDISER6_INTIICNAKI0_SHIFT (2u) -#define INTC_ICDISER6_INTIICALI0_SHIFT (3u) -#define INTC_ICDISER6_INTIICTMOI0_SHIFT (4u) -#define INTC_ICDISER6_INTIICTEI1_SHIFT (5u) -#define INTC_ICDISER6_INTIICRI1_SHIFT (6u) -#define INTC_ICDISER6_INTIICTI1_SHIFT (7u) -#define INTC_ICDISER6_INTIICSPI1_SHIFT (8u) -#define INTC_ICDISER6_INTIICSTI1_SHIFT (9u) -#define INTC_ICDISER6_INTIICNAKI1_SHIFT (10u) -#define INTC_ICDISER6_INTIICALI1_SHIFT (11u) -#define INTC_ICDISER6_INTIICTMOI1_SHIFT (12u) -#define INTC_ICDISER6_INTIICTEI2_SHIFT (13u) -#define INTC_ICDISER6_INTIICRI2_SHIFT (14u) -#define INTC_ICDISER6_INTIICTI2_SHIFT (15u) -#define INTC_ICDISER6_INTIICSPI2_SHIFT (16u) -#define INTC_ICDISER6_INTIICSTI2_SHIFT (17u) -#define INTC_ICDISER6_INTIICNAKI2_SHIFT (18u) -#define INTC_ICDISER6_INTIICALI2_SHIFT (19u) -#define INTC_ICDISER6_INTIICTMOI2_SHIFT (20u) -#define INTC_ICDISER6_INTIICTEI3_SHIFT (21u) -#define INTC_ICDISER6_INTIICRI3_SHIFT (22u) -#define INTC_ICDISER6_INTIICTI3_SHIFT (23u) -#define INTC_ICDISER6_INTIICSPI3_SHIFT (24u) -#define INTC_ICDISER6_INTIICSTI3_SHIFT (25u) -#define INTC_ICDISER6_INTIICNAKI3_SHIFT (26u) -#define INTC_ICDISER6_INTIICALI3_SHIFT (27u) -#define INTC_ICDISER6_INTIICTMOI3_SHIFT (28u) -#define INTC_ICDISER6_BRI0_SHIFT (29u) -#define INTC_ICDISER6_ERI0_SHIFT (30u) -#define INTC_ICDISER6_RXI0_SHIFT (31u) - -#define INTC_ICDISER7_TXI0_SHIFT (0u) -#define INTC_ICDISER7_BRI1_SHIFT (1u) -#define INTC_ICDISER7_ERI1_SHIFT (2u) -#define INTC_ICDISER7_RXI1_SHIFT (3u) -#define INTC_ICDISER7_TXI1_SHIFT (4u) -#define INTC_ICDISER7_BRI2_SHIFT (5u) -#define INTC_ICDISER7_ERI2_SHIFT (6u) -#define INTC_ICDISER7_RXI2_SHIFT (7u) -#define INTC_ICDISER7_TXI2_SHIFT (8u) -#define INTC_ICDISER7_BRI3_SHIFT (9u) -#define INTC_ICDISER7_ERI3_SHIFT (10u) -#define INTC_ICDISER7_RXI3_SHIFT (11u) -#define INTC_ICDISER7_TXI3_SHIFT (12u) -#define INTC_ICDISER7_BRI4_SHIFT (13u) -#define INTC_ICDISER7_ERI4_SHIFT (14u) -#define INTC_ICDISER7_RXI4_SHIFT (15u) -#define INTC_ICDISER7_TXI4_SHIFT (16u) -#define INTC_ICDISER7_BRI5_SHIFT (17u) -#define INTC_ICDISER7_ERI5_SHIFT (18u) -#define INTC_ICDISER7_RXI5_SHIFT (19u) -#define INTC_ICDISER7_TXI5_SHIFT (20u) -#define INTC_ICDISER7_BRI6_SHIFT (21u) -#define INTC_ICDISER7_ERI6_SHIFT (22u) -#define INTC_ICDISER7_RXI6_SHIFT (23u) -#define INTC_ICDISER7_TXI6_SHIFT (24u) -#define INTC_ICDISER7_BRI7_SHIFT (25u) -#define INTC_ICDISER7_ERI7_SHIFT (26u) -#define INTC_ICDISER7_RXI7_SHIFT (27u) -#define INTC_ICDISER7_TXI7_SHIFT (28u) -#define INTC_ICDISER7_INTRCANGERR_SHIFT (29u) -#define INTC_ICDISER7_INTRCANGRECC_SHIFT (30u) -#define INTC_ICDISER7_INTRCAN0REC_SHIFT (31u) - -#define INTC_ICDISER8_INTRCAN0ERR_SHIFT (0u) -#define INTC_ICDISER8_INTRCAN0TRX_SHIFT (1u) -#define INTC_ICDISER8_INTRCAN1REC_SHIFT (2u) -#define INTC_ICDISER8_INTRCAN1ERR_SHIFT (3u) -#define INTC_ICDISER8_INTRCAN1TRX_SHIFT (4u) -#define INTC_ICDISER8_INTRCAN2REC_SHIFT (5u) -#define INTC_ICDISER8_INTRCAN2ERR_SHIFT (6u) -#define INTC_ICDISER8_INTRCAN2TRX_SHIFT (7u) -#define INTC_ICDISER8_INTRCAN3REC_SHIFT (8u) -#define INTC_ICDISER8_INTRCAN3ERR_SHIFT (9u) -#define INTC_ICDISER8_INTRCAN3TRX_SHIFT (10u) -#define INTC_ICDISER8_INTRCAN4REC_SHIFT (11u) -#define INTC_ICDISER8_INTRCAN4ERR_SHIFT (12u) -#define INTC_ICDISER8_INTRCAN4TRX_SHIFT (13u) -#define INTC_ICDISER8_SPEI0_SHIFT (14u) -#define INTC_ICDISER8_SPRI0_SHIFT (15u) -#define INTC_ICDISER8_SPTI0_SHIFT (16u) -#define INTC_ICDISER8_SPEI1_SHIFT (17u) -#define INTC_ICDISER8_SPRI1_SHIFT (18u) -#define INTC_ICDISER8_SPTI1_SHIFT (19u) -#define INTC_ICDISER8_SPEI2_SHIFT (20u) -#define INTC_ICDISER8_SPRI2_SHIFT (21u) -#define INTC_ICDISER8_SPTI2_SHIFT (22u) -#define INTC_ICDISER8_SPEI3_SHIFT (23u) -#define INTC_ICDISER8_SPRI3_SHIFT (24u) -#define INTC_ICDISER8_SPTI3_SHIFT (25u) -#define INTC_ICDISER8_SPEI4_SHIFT (26u) -#define INTC_ICDISER8_SPRI4_SHIFT (27u) -#define INTC_ICDISER8_SPTI4_SHIFT (28u) -#define INTC_ICDISER8_IEBBTD_SHIFT (29u) -#define INTC_ICDISER8_IEBBTERR_SHIFT (30u) -#define INTC_ICDISER8_IEBBTSTA_SHIFT (31u) - -#define INTC_ICDISER9_IEBBTV_SHIFT (0u) -#define INTC_ICDISER9_ISY_SHIFT (1u) -#define INTC_ICDISER9_IERR_SHIFT (2u) -#define INTC_ICDISER9_ITARG_SHIFT (3u) -#define INTC_ICDISER9_ISEC_SHIFT (4u) -#define INTC_ICDISER9_IBUF_SHIFT (5u) -#define INTC_ICDISER9_IREADY_SHIFT (6u) -#define INTC_ICDISER9_FLSTE_SHIFT (7u) -#define INTC_ICDISER9_FLTENDI_SHIFT (8u) -#define INTC_ICDISER9_FLTREQ0I_SHIFT (9u) -#define INTC_ICDISER9_FLTREQ1I_SHIFT (10u) -#define INTC_ICDISER9_MMC0_SHIFT (11u) -#define INTC_ICDISER9_MMC1_SHIFT (12u) -#define INTC_ICDISER9_MMC2_SHIFT (13u) -#define INTC_ICDISER9_SDHI0_3_SHIFT (14u) -#define INTC_ICDISER9_SDHI0_0_SHIFT (15u) -#define INTC_ICDISER9_SDHI0_1_SHIFT (16u) -#define INTC_ICDISER9_SDHI1_3_SHIFT (17u) -#define INTC_ICDISER9_SDHI1_0_SHIFT (18u) -#define INTC_ICDISER9_SDHI1_1_SHIFT (19u) -#define INTC_ICDISER9_ARM_SHIFT (20u) -#define INTC_ICDISER9_PRD_SHIFT (21u) -#define INTC_ICDISER9_CUP_SHIFT (22u) -#define INTC_ICDISER9_SCUAI0_SHIFT (23u) -#define INTC_ICDISER9_SCUAI1_SHIFT (24u) -#define INTC_ICDISER9_SCUFDI0_SHIFT (25u) -#define INTC_ICDISER9_SCUFDI1_SHIFT (26u) -#define INTC_ICDISER9_SCUFDI2_SHIFT (27u) -#define INTC_ICDISER9_SCUFDI3_SHIFT (28u) -#define INTC_ICDISER9_SCUFUI0_SHIFT (29u) -#define INTC_ICDISER9_SCUFUI1_SHIFT (30u) -#define INTC_ICDISER9_SCUFUI2_SHIFT (31u) - -#define INTC_ICDISER10_SCUFUI3_SHIFT (0u) -#define INTC_ICDISER10_SCUDVI0_SHIFT (1u) -#define INTC_ICDISER10_SCUDVI1_SHIFT (2u) -#define INTC_ICDISER10_SCUDVI2_SHIFT (3u) -#define INTC_ICDISER10_SCUDVI3_SHIFT (4u) -#define INTC_ICDISER10_MLB_CINT_SHIFT (5u) -#define INTC_ICDISER10_MLB_SINT_SHIFT (6u) -#define INTC_ICDISER10_DRC0_SHIFT (7u) -#define INTC_ICDISER10_DRC1_SHIFT (8u) -#define INTC_ICDISER10_LINI0_INT_T_SHIFT (11u) -#define INTC_ICDISER10_LINI0_INT_R_SHIFT (12u) -#define INTC_ICDISER10_LINI0_INT_S_SHIFT (13u) -#define INTC_ICDISER10_LINI0_INT_M_SHIFT (14u) -#define INTC_ICDISER10_LINI1_INT_T_SHIFT (15u) -#define INTC_ICDISER10_LINI1_INT_R_SHIFT (16u) -#define INTC_ICDISER10_LINI1_INT_S_SHIFT (17u) -#define INTC_ICDISER10_LINI1_INT_M_SHIFT (18u) -#define INTC_ICDISER10_ERI0_SHIFT (27u) -#define INTC_ICDISER10_RXI0_SHIFT (28u) -#define INTC_ICDISER10_TXI0_SHIFT (29u) -#define INTC_ICDISER10_TEI0_SHIFT (30u) -#define INTC_ICDISER10_ERI1_SHIFT (31u) - -#define INTC_ICDISER11_RXI1_SHIFT (0u) -#define INTC_ICDISER11_TXI1_SHIFT (1u) -#define INTC_ICDISER11_TEI1_SHIFT (2u) -#define INTC_ICDISER11_AVBI_DATA_SHIFT (3u) -#define INTC_ICDISER11_AVBI_ERROR_SHIFT (4u) -#define INTC_ICDISER11_AVBI_MANAGE_SHIFT (5u) -#define INTC_ICDISER11_AVBI_MAC_SHIFT (6u) -#define INTC_ICDISER11_ETHERI_SHIFT (7u) -#define INTC_ICDISER11_CEUI_SHIFT (12u) -#define INTC_ICDISER11_H2XMLB_ERRINT_SHIFT (29u) -#define INTC_ICDISER11_H2XIC1_ERRINT_SHIFT (30u) -#define INTC_ICDISER11_X2HPERI1_ERRINT_SHIFT (31u) - -#define INTC_ICDISER12_X2HPERI2_ERRINT_SHIFT (0u) -#define INTC_ICDISER12_X2HPERI34_ERRINT_SHIFT (1u) -#define INTC_ICDISER12_X2HPERI5_ERRINT_SHIFT (2u) -#define INTC_ICDISER12_X2HPERI67_ERRINT_SHIFT (3u) -#define INTC_ICDISER12_X2HDBGR_ERRINT_SHIFT (4u) -#define INTC_ICDISER12_X2HBSC_ERRINT_SHIFT (5u) -#define INTC_ICDISER12_X2HSPI1_ERRINT_SHIFT (6u) -#define INTC_ICDISER12_X2HSPI2_ERRINT_SHIFT (7u) -#define INTC_ICDISER12_PRRI_SHIFT (8u) -#define INTC_ICDISER12_IFEI0_SHIFT (9u) -#define INTC_ICDISER12_OFFI0_SHIFT (10u) -#define INTC_ICDISER12_PFVEI0_SHIFT (11u) -#define INTC_ICDISER12_IFEI1_SHIFT (12u) -#define INTC_ICDISER12_OFFI1_SHIFT (13u) -#define INTC_ICDISER12_PFVEI1_SHIFT (14u) - -#define INTC_ICDISER13_TINT0_SHIFT (0u) -#define INTC_ICDISER13_TINT1_SHIFT (1u) -#define INTC_ICDISER13_TINT2_SHIFT (2u) -#define INTC_ICDISER13_TINT3_SHIFT (3u) -#define INTC_ICDISER13_TINT4_SHIFT (4u) -#define INTC_ICDISER13_TINT5_SHIFT (5u) -#define INTC_ICDISER13_TINT6_SHIFT (6u) -#define INTC_ICDISER13_TINT7_SHIFT (7u) -#define INTC_ICDISER13_TINT8_SHIFT (8u) -#define INTC_ICDISER13_TINT9_SHIFT (9u) -#define INTC_ICDISER13_TINT10_SHIFT (10u) -#define INTC_ICDISER13_TINT11_SHIFT (11u) -#define INTC_ICDISER13_TINT12_SHIFT (12u) -#define INTC_ICDISER13_TINT13_SHIFT (13u) -#define INTC_ICDISER13_TINT14_SHIFT (14u) -#define INTC_ICDISER13_TINT15_SHIFT (15u) -#define INTC_ICDISER13_TINT16_SHIFT (16u) -#define INTC_ICDISER13_TINT17_SHIFT (17u) -#define INTC_ICDISER13_TINT18_SHIFT (18u) -#define INTC_ICDISER13_TINT19_SHIFT (19u) -#define INTC_ICDISER13_TINT20_SHIFT (20u) -#define INTC_ICDISER13_TINT21_SHIFT (21u) -#define INTC_ICDISER13_TINT22_SHIFT (22u) -#define INTC_ICDISER13_TINT23_SHIFT (23u) -#define INTC_ICDISER13_TINT24_SHIFT (24u) -#define INTC_ICDISER13_TINT25_SHIFT (25u) -#define INTC_ICDISER13_TINT26_SHIFT (26u) -#define INTC_ICDISER13_TINT27_SHIFT (27u) -#define INTC_ICDISER13_TINT28_SHIFT (28u) -#define INTC_ICDISER13_TINT29_SHIFT (29u) -#define INTC_ICDISER13_TINT30_SHIFT (30u) -#define INTC_ICDISER13_TINT31_SHIFT (31u) - -#define INTC_ICDISER14_TINT32_SHIFT (0u) -#define INTC_ICDISER14_TINT33_SHIFT (1u) -#define INTC_ICDISER14_TINT34_SHIFT (2u) -#define INTC_ICDISER14_TINT35_SHIFT (3u) -#define INTC_ICDISER14_TINT36_SHIFT (4u) -#define INTC_ICDISER14_TINT37_SHIFT (5u) -#define INTC_ICDISER14_TINT38_SHIFT (6u) -#define INTC_ICDISER14_TINT39_SHIFT (7u) -#define INTC_ICDISER14_TINT40_SHIFT (8u) -#define INTC_ICDISER14_TINT41_SHIFT (9u) -#define INTC_ICDISER14_TINT42_SHIFT (10u) -#define INTC_ICDISER14_TINT43_SHIFT (11u) -#define INTC_ICDISER14_TINT44_SHIFT (12u) -#define INTC_ICDISER14_TINT45_SHIFT (13u) -#define INTC_ICDISER14_TINT46_SHIFT (14u) -#define INTC_ICDISER14_TINT47_SHIFT (15u) -#define INTC_ICDISER14_TINT48_SHIFT (16u) -#define INTC_ICDISER14_TINT49_SHIFT (17u) -#define INTC_ICDISER14_TINT50_SHIFT (18u) -#define INTC_ICDISER14_TINT51_SHIFT (19u) -#define INTC_ICDISER14_TINT52_SHIFT (20u) -#define INTC_ICDISER14_TINT53_SHIFT (21u) -#define INTC_ICDISER14_TINT54_SHIFT (22u) -#define INTC_ICDISER14_TINT55_SHIFT (23u) -#define INTC_ICDISER14_TINT56_SHIFT (24u) -#define INTC_ICDISER14_TINT57_SHIFT (25u) -#define INTC_ICDISER14_TINT58_SHIFT (26u) -#define INTC_ICDISER14_TINT59_SHIFT (27u) -#define INTC_ICDISER14_TINT60_SHIFT (28u) -#define INTC_ICDISER14_TINT61_SHIFT (29u) -#define INTC_ICDISER14_TINT62_SHIFT (30u) -#define INTC_ICDISER14_TINT63_SHIFT (31u) - -#define INTC_ICDISER15_TINT64_SHIFT (0u) -#define INTC_ICDISER15_TINT65_SHIFT (1u) -#define INTC_ICDISER15_TINT66_SHIFT (2u) -#define INTC_ICDISER15_TINT67_SHIFT (3u) -#define INTC_ICDISER15_TINT68_SHIFT (4u) -#define INTC_ICDISER15_TINT69_SHIFT (5u) -#define INTC_ICDISER15_TINT70_SHIFT (6u) -#define INTC_ICDISER15_TINT71_SHIFT (7u) -#define INTC_ICDISER15_TINT72_SHIFT (8u) -#define INTC_ICDISER15_TINT73_SHIFT (9u) -#define INTC_ICDISER15_TINT74_SHIFT (10u) -#define INTC_ICDISER15_TINT75_SHIFT (11u) -#define INTC_ICDISER15_TINT76_SHIFT (12u) -#define INTC_ICDISER15_TINT77_SHIFT (13u) -#define INTC_ICDISER15_TINT78_SHIFT (14u) -#define INTC_ICDISER15_TINT79_SHIFT (15u) -#define INTC_ICDISER15_TINT80_SHIFT (16u) -#define INTC_ICDISER15_TINT81_SHIFT (17u) -#define INTC_ICDISER15_TINT82_SHIFT (18u) -#define INTC_ICDISER15_TINT83_SHIFT (19u) -#define INTC_ICDISER15_TINT84_SHIFT (20u) -#define INTC_ICDISER15_TINT85_SHIFT (21u) -#define INTC_ICDISER15_TINT86_SHIFT (22u) -#define INTC_ICDISER15_TINT87_SHIFT (23u) -#define INTC_ICDISER15_TINT88_SHIFT (24u) -#define INTC_ICDISER15_TINT89_SHIFT (25u) -#define INTC_ICDISER15_TINT90_SHIFT (26u) -#define INTC_ICDISER15_TINT91_SHIFT (27u) -#define INTC_ICDISER15_TINT92_SHIFT (28u) -#define INTC_ICDISER15_TINT93_SHIFT (29u) -#define INTC_ICDISER15_TINT94_SHIFT (30u) -#define INTC_ICDISER15_TINT95_SHIFT (31u) - -#define INTC_ICDISER16_TINT96_SHIFT (0u) -#define INTC_ICDISER16_TINT97_SHIFT (1u) -#define INTC_ICDISER16_TINT98_SHIFT (2u) -#define INTC_ICDISER16_TINT99_SHIFT (3u) -#define INTC_ICDISER16_TINT100_SHIFT (4u) -#define INTC_ICDISER16_TINT101_SHIFT (5u) -#define INTC_ICDISER16_TINT102_SHIFT (6u) -#define INTC_ICDISER16_TINT103_SHIFT (7u) -#define INTC_ICDISER16_TINT104_SHIFT (8u) -#define INTC_ICDISER16_TINT105_SHIFT (9u) -#define INTC_ICDISER16_TINT106_SHIFT (10u) -#define INTC_ICDISER16_TINT107_SHIFT (11u) -#define INTC_ICDISER16_TINT108_SHIFT (12u) -#define INTC_ICDISER16_TINT109_SHIFT (13u) -#define INTC_ICDISER16_TINT110_SHIFT (14u) -#define INTC_ICDISER16_TINT111_SHIFT (15u) -#define INTC_ICDISER16_TINT112_SHIFT (16u) -#define INTC_ICDISER16_TINT113_SHIFT (17u) -#define INTC_ICDISER16_TINT114_SHIFT (18u) -#define INTC_ICDISER16_TINT115_SHIFT (19u) -#define INTC_ICDISER16_TINT116_SHIFT (20u) -#define INTC_ICDISER16_TINT117_SHIFT (21u) -#define INTC_ICDISER16_TINT118_SHIFT (22u) -#define INTC_ICDISER16_TINT119_SHIFT (23u) -#define INTC_ICDISER16_TINT120_SHIFT (24u) -#define INTC_ICDISER16_TINT121_SHIFT (25u) -#define INTC_ICDISER16_TINT122_SHIFT (26u) -#define INTC_ICDISER16_TINT123_SHIFT (27u) -#define INTC_ICDISER16_TINT124_SHIFT (28u) -#define INTC_ICDISER16_TINT125_SHIFT (29u) -#define INTC_ICDISER16_TINT126_SHIFT (30u) -#define INTC_ICDISER16_TINT127_SHIFT (31u) - -#define INTC_ICDISER17_TINT128_SHIFT (0u) -#define INTC_ICDISER17_TINT129_SHIFT (1u) -#define INTC_ICDISER17_TINT130_SHIFT (2u) -#define INTC_ICDISER17_TINT131_SHIFT (3u) -#define INTC_ICDISER17_TINT132_SHIFT (4u) -#define INTC_ICDISER17_TINT133_SHIFT (5u) -#define INTC_ICDISER17_TINT134_SHIFT (6u) -#define INTC_ICDISER17_TINT135_SHIFT (7u) -#define INTC_ICDISER17_TINT136_SHIFT (8u) -#define INTC_ICDISER17_TINT137_SHIFT (9u) -#define INTC_ICDISER17_TINT138_SHIFT (10u) -#define INTC_ICDISER17_TINT139_SHIFT (11u) -#define INTC_ICDISER17_TINT140_SHIFT (12u) -#define INTC_ICDISER17_TINT141_SHIFT (13u) -#define INTC_ICDISER17_TINT142_SHIFT (14u) -#define INTC_ICDISER17_TINT143_SHIFT (15u) -#define INTC_ICDISER17_TINT144_SHIFT (16u) -#define INTC_ICDISER17_TINT145_SHIFT (17u) -#define INTC_ICDISER17_TINT146_SHIFT (18u) -#define INTC_ICDISER17_TINT147_SHIFT (19u) -#define INTC_ICDISER17_TINT148_SHIFT (20u) -#define INTC_ICDISER17_TINT149_SHIFT (21u) -#define INTC_ICDISER17_TINT150_SHIFT (22u) -#define INTC_ICDISER17_TINT151_SHIFT (23u) -#define INTC_ICDISER17_TINT152_SHIFT (24u) -#define INTC_ICDISER17_TINT153_SHIFT (25u) -#define INTC_ICDISER17_TINT154_SHIFT (26u) -#define INTC_ICDISER17_TINT155_SHIFT (27u) -#define INTC_ICDISER17_TINT156_SHIFT (28u) -#define INTC_ICDISER17_TINT157_SHIFT (29u) -#define INTC_ICDISER17_TINT158_SHIFT (30u) -#define INTC_ICDISER17_TINT159_SHIFT (31u) - -#define INTC_ICDISER18_TINT160_SHIFT (0u) -#define INTC_ICDISER18_TINT161_SHIFT (1u) -#define INTC_ICDISER18_TINT162_SHIFT (2u) -#define INTC_ICDISER18_TINT163_SHIFT (3u) -#define INTC_ICDISER18_TINT164_SHIFT (4u) -#define INTC_ICDISER18_TINT165_SHIFT (5u) -#define INTC_ICDISER18_TINT166_SHIFT (6u) -#define INTC_ICDISER18_TINT167_SHIFT (7u) -#define INTC_ICDISER18_TINT168_SHIFT (8u) -#define INTC_ICDISER18_TINT169_SHIFT (9u) -#define INTC_ICDISER18_TINT170_SHIFT (10u) - -#define INTC_ICDICER0_SW0_SHIFT (0u) -#define INTC_ICDICER0_SW1_SHIFT (1u) -#define INTC_ICDICER0_SW2_SHIFT (2u) -#define INTC_ICDICER0_SW3_SHIFT (3u) -#define INTC_ICDICER0_SW4_SHIFT (4u) -#define INTC_ICDICER0_SW5_SHIFT (5u) -#define INTC_ICDICER0_SW6_SHIFT (6u) -#define INTC_ICDICER0_SW7_SHIFT (7u) -#define INTC_ICDICER0_SW8_SHIFT (8u) -#define INTC_ICDICER0_SW9_SHIFT (9u) -#define INTC_ICDICER0_SW10_SHIFT (10u) -#define INTC_ICDICER0_SW11_SHIFT (11u) -#define INTC_ICDICER0_SW12_SHIFT (12u) -#define INTC_ICDICER0_SW13_SHIFT (13u) -#define INTC_ICDICER0_SW14_SHIFT (14u) -#define INTC_ICDICER0_SW15_SHIFT (15u) -#define INTC_ICDICER0_PMUIRQ0_SHIFT (16u) -#define INTC_ICDICER0_COMMRX0_SHIFT (17u) -#define INTC_ICDICER0_COMMTX0_SHIFT (18u) -#define INTC_ICDICER0_CTIIRQ0_SHIFT (19u) - -#define INTC_ICDICER1_IRQ0_SHIFT (0u) -#define INTC_ICDICER1_IRQ1_SHIFT (1u) -#define INTC_ICDICER1_IRQ2_SHIFT (2u) -#define INTC_ICDICER1_IRQ3_SHIFT (3u) -#define INTC_ICDICER1_IRQ4_SHIFT (4u) -#define INTC_ICDICER1_IRQ5_SHIFT (5u) -#define INTC_ICDICER1_IRQ6_SHIFT (6u) -#define INTC_ICDICER1_IRQ7_SHIFT (7u) -#define INTC_ICDICER1_PL310ERR_SHIFT (8u) -#define INTC_ICDICER1_DMAINT0_SHIFT (9u) -#define INTC_ICDICER1_DMAINT1_SHIFT (10u) -#define INTC_ICDICER1_DMAINT2_SHIFT (11u) -#define INTC_ICDICER1_DMAINT3_SHIFT (12u) -#define INTC_ICDICER1_DMAINT4_SHIFT (13u) -#define INTC_ICDICER1_DMAINT5_SHIFT (14u) -#define INTC_ICDICER1_DMAINT6_SHIFT (15u) -#define INTC_ICDICER1_DMAINT7_SHIFT (16u) -#define INTC_ICDICER1_DMAINT8_SHIFT (17u) -#define INTC_ICDICER1_DMAINT9_SHIFT (18u) -#define INTC_ICDICER1_DMAINT10_SHIFT (19u) -#define INTC_ICDICER1_DMAINT11_SHIFT (20u) -#define INTC_ICDICER1_DMAINT12_SHIFT (21u) -#define INTC_ICDICER1_DMAINT13_SHIFT (22u) -#define INTC_ICDICER1_DMAINT14_SHIFT (23u) -#define INTC_ICDICER1_DMAINT15_SHIFT (24u) -#define INTC_ICDICER1_DMAERR_SHIFT (25u) - -#define INTC_ICDICER2_USBI0_SHIFT (9u) -#define INTC_ICDICER2_USBI1_SHIFT (10u) -#define INTC_ICDICER2_S0_VI_VSYNC0_SHIFT (11u) -#define INTC_ICDICER2_S0_LO_VSYNC0_SHIFT (12u) -#define INTC_ICDICER2_S0_VSYNCERR0_SHIFT (13u) -#define INTC_ICDICER2_GR3_VLINE0_SHIFT (14u) -#define INTC_ICDICER2_S0_VFIELD0_SHIFT (15u) -#define INTC_ICDICER2_IV1_VBUFERR0_SHIFT (16u) -#define INTC_ICDICER2_IV3_VBUFERR0_SHIFT (17u) -#define INTC_ICDICER2_IV5_VBUFERR0_SHIFT (18u) -#define INTC_ICDICER2_IV6_VBUFERR0_SHIFT (19u) -#define INTC_ICDICER2_S0_WLINE0_SHIFT (20u) -#define INTC_ICDICER2_S1_VI_VSYNC0_SHIFT (21u) -#define INTC_ICDICER2_S1_LO_VSYNC0_SHIFT (22u) -#define INTC_ICDICER2_S1_VSYNCERR0_SHIFT (23u) -#define INTC_ICDICER2_S1_VFIELD0_SHIFT (24u) -#define INTC_ICDICER2_IV2_VBUFERR0_SHIFT (25u) -#define INTC_ICDICER2_IV4_VBUFERR0_SHIFT (26u) -#define INTC_ICDICER2_S1_WLINE0_SHIFT (27u) -#define INTC_ICDICER2_OIR_VI_VSYNC0_SHIFT (28u) -#define INTC_ICDICER2_OIR_LO_VSYNC0_SHIFT (29u) -#define INTC_ICDICER2_OIR_VSYNCERR0_SHIFT (30u) -#define INTC_ICDICER2_OIR_VFIELD0_SHIFT (31u) - -#define INTC_ICDICER3_IV7_VBUFERR0_SHIFT (0u) -#define INTC_ICDICER3_IV8_VBUFERR0_SHIFT (1u) -#define INTC_ICDICER3_S0_VI_VSYNC1_SHIFT (3u) -#define INTC_ICDICER3_S0_LO_VSYNC1_SHIFT (4u) -#define INTC_ICDICER3_S0_VSYNCERR1_SHIFT (5u) -#define INTC_ICDICER3_GR3_VLINE1_SHIFT (6u) -#define INTC_ICDICER3_S0_VFIELD1_SHIFT (7u) -#define INTC_ICDICER3_IV1_VBUFERR1_SHIFT (8u) -#define INTC_ICDICER3_IV3_VBUFERR1_SHIFT (9u) -#define INTC_ICDICER3_IV5_VBUFERR1_SHIFT (10u) -#define INTC_ICDICER3_IV6_VBUFERR1_SHIFT (11u) -#define INTC_ICDICER3_S0_WLINE1_SHIFT (12u) -#define INTC_ICDICER3_S1_VI_VSYNC1_SHIFT (13u) -#define INTC_ICDICER3_S1_LO_VSYNC1_SHIFT (14u) -#define INTC_ICDICER3_S1_VSYNCERR1_SHIFT (15u) -#define INTC_ICDICER3_S1_VFIELD1_SHIFT (16u) -#define INTC_ICDICER3_IV2_VBUFERR1_SHIFT (17u) -#define INTC_ICDICER3_IV4_VBUFERR1_SHIFT (18u) -#define INTC_ICDICER3_S1_WLINE1_SHIFT (19u) -#define INTC_ICDICER3_OIR_VI_VSYNC1_SHIFT (20u) -#define INTC_ICDICER3_OIR_LO_VSYNC1_SHIFT (21u) -#define INTC_ICDICER3_OIR_VLINE1_SHIFT (22u) -#define INTC_ICDICER3_OIR_VFIELD1_SHIFT (23u) -#define INTC_ICDICER3_IV7_VBUFERR1_SHIFT (24u) -#define INTC_ICDICER3_IV8_VBUFERR1_SHIFT (25u) -#define INTC_ICDICER3_IMRDI_SHIFT (27u) -#define INTC_ICDICER3_IMR2I0_SHIFT (28u) -#define INTC_ICDICER3_IMR2I1_SHIFT (29u) -#define INTC_ICDICER3_JEDI_SHIFT (30u) -#define INTC_ICDICER3_JDTI_SHIFT (31u) - -#define INTC_ICDICER4_CMP0_SHIFT (0u) -#define INTC_ICDICER4_CMP1_SHIFT (1u) -#define INTC_ICDICER4_INT0_SHIFT (2u) -#define INTC_ICDICER4_INT1_SHIFT (3u) -#define INTC_ICDICER4_INT2_SHIFT (4u) -#define INTC_ICDICER4_INT3_SHIFT (5u) -#define INTC_ICDICER4_OSTM0TINT_SHIFT (6u) -#define INTC_ICDICER4_OSTM1TINT_SHIFT (7u) -#define INTC_ICDICER4_CMI_SHIFT (8u) -#define INTC_ICDICER4_WTOUT_SHIFT (9u) -#define INTC_ICDICER4_ITI_SHIFT (10u) -#define INTC_ICDICER4_TGI0A_SHIFT (11u) -#define INTC_ICDICER4_TGI0B_SHIFT (12u) -#define INTC_ICDICER4_TGI0C_SHIFT (13u) -#define INTC_ICDICER4_TGI0D_SHIFT (14u) -#define INTC_ICDICER4_TGI0V_SHIFT (15u) -#define INTC_ICDICER4_TGI0E_SHIFT (16u) -#define INTC_ICDICER4_TGI0F_SHIFT (17u) -#define INTC_ICDICER4_TGI1A_SHIFT (18u) -#define INTC_ICDICER4_TGI1B_SHIFT (19u) -#define INTC_ICDICER4_TGI1V_SHIFT (20u) -#define INTC_ICDICER4_TGI1U_SHIFT (21u) -#define INTC_ICDICER4_TGI2A_SHIFT (22u) -#define INTC_ICDICER4_TGI2B_SHIFT (23u) -#define INTC_ICDICER4_TGI2V_SHIFT (24u) -#define INTC_ICDICER4_TGI2U_SHIFT (25u) -#define INTC_ICDICER4_TGI3A_SHIFT (26u) -#define INTC_ICDICER4_TGI3B_SHIFT (27u) -#define INTC_ICDICER4_TGI3C_SHIFT (28u) -#define INTC_ICDICER4_TGI3D_SHIFT (29u) -#define INTC_ICDICER4_TGI3V_SHIFT (30u) -#define INTC_ICDICER4_TGI4A_SHIFT (31u) - -#define INTC_ICDICER5_TGI4B_SHIFT (0u) -#define INTC_ICDICER5_TGI4C_SHIFT (1u) -#define INTC_ICDICER5_TGI4D_SHIFT (2u) -#define INTC_ICDICER5_TGI4V_SHIFT (3u) -#define INTC_ICDICER5_CMI1_SHIFT (4u) -#define INTC_ICDICER5_CMI2_SHIFT (5u) -#define INTC_ICDICER5_SGDEI0_SHIFT (6u) -#define INTC_ICDICER5_SGDEI1_SHIFT (7u) -#define INTC_ICDICER5_SGDEI2_SHIFT (8u) -#define INTC_ICDICER5_SGDEI3_SHIFT (9u) -#define INTC_ICDICER5_ADI_SHIFT (10u) -#define INTC_ICDICER5_LMTI_SHIFT (11u) -#define INTC_ICDICER5_SSII0_SHIFT (12u) -#define INTC_ICDICER5_SSIRXI0_SHIFT (13u) -#define INTC_ICDICER5_SSITXI0_SHIFT (14u) -#define INTC_ICDICER5_SSII1_SHIFT (15u) -#define INTC_ICDICER5_SSIRXI1_SHIFT (16u) -#define INTC_ICDICER5_SSITXI1_SHIFT (17u) -#define INTC_ICDICER5_SSII2_SHIFT (18u) -#define INTC_ICDICER5_SSIRTI2_SHIFT (19u) -#define INTC_ICDICER5_SSII3_SHIFT (20u) -#define INTC_ICDICER5_SSIRXI3_SHIFT (21u) -#define INTC_ICDICER5_SSITXI3_SHIFT (22u) -#define INTC_ICDICER5_SSII4_SHIFT (23u) -#define INTC_ICDICER5_SSIRTI4_SHIFT (24u) -#define INTC_ICDICER5_SSII5_SHIFT (25u) -#define INTC_ICDICER5_SSIRXI5_SHIFT (26u) -#define INTC_ICDICER5_SSITXI5_SHIFT (27u) -#define INTC_ICDICER5_SPDIFI_SHIFT (28u) -#define INTC_ICDICER5_INTIICTEI0_SHIFT (29u) -#define INTC_ICDICER5_INTIICRI0_SHIFT (30u) -#define INTC_ICDICER5_INTIICTI0_SHIFT (31u) - -#define INTC_ICDICER6_INTIICSPI0_SHIFT (0u) -#define INTC_ICDICER6_INTIICSTI0_SHIFT (1u) -#define INTC_ICDICER6_INTIICNAKI0_SHIFT (2u) -#define INTC_ICDICER6_INTIICALI0_SHIFT (3u) -#define INTC_ICDICER6_INTIICTMOI0_SHIFT (4u) -#define INTC_ICDICER6_INTIICTEI1_SHIFT (5u) -#define INTC_ICDICER6_INTIICRI1_SHIFT (6u) -#define INTC_ICDICER6_INTIICTI1_SHIFT (7u) -#define INTC_ICDICER6_INTIICSPI1_SHIFT (8u) -#define INTC_ICDICER6_INTIICSTI1_SHIFT (9u) -#define INTC_ICDICER6_INTIICNAKI1_SHIFT (10u) -#define INTC_ICDICER6_INTIICALI1_SHIFT (11u) -#define INTC_ICDICER6_INTIICTMOI1_SHIFT (12u) -#define INTC_ICDICER6_INTIICTEI2_SHIFT (13u) -#define INTC_ICDICER6_INTIICRI2_SHIFT (14u) -#define INTC_ICDICER6_INTIICTI2_SHIFT (15u) -#define INTC_ICDICER6_INTIICSPI2_SHIFT (16u) -#define INTC_ICDICER6_INTIICSTI2_SHIFT (17u) -#define INTC_ICDICER6_INTIICNAKI2_SHIFT (18u) -#define INTC_ICDICER6_INTIICALI2_SHIFT (19u) -#define INTC_ICDICER6_INTIICTMOI2_SHIFT (20u) -#define INTC_ICDICER6_INTIICTEI3_SHIFT (21u) -#define INTC_ICDICER6_INTIICRI3_SHIFT (22u) -#define INTC_ICDICER6_INTIICTI3_SHIFT (23u) -#define INTC_ICDICER6_INTIICSPI3_SHIFT (24u) -#define INTC_ICDICER6_INTIICSTI3_SHIFT (25u) -#define INTC_ICDICER6_INTIICNAKI3_SHIFT (26u) -#define INTC_ICDICER6_INTIICALI3_SHIFT (27u) -#define INTC_ICDICER6_INTIICTMOI3_SHIFT (28u) -#define INTC_ICDICER6_BRI0_SHIFT (29u) -#define INTC_ICDICER6_ERI0_SHIFT (30u) -#define INTC_ICDICER6_RXI0_SHIFT (31u) - -#define INTC_ICDICER7_TXI0_SHIFT (0u) -#define INTC_ICDICER7_BRI1_SHIFT (1u) -#define INTC_ICDICER7_ERI1_SHIFT (2u) -#define INTC_ICDICER7_RXI1_SHIFT (3u) -#define INTC_ICDICER7_TXI1_SHIFT (4u) -#define INTC_ICDICER7_BRI2_SHIFT (5u) -#define INTC_ICDICER7_ERI2_SHIFT (6u) -#define INTC_ICDICER7_RXI2_SHIFT (7u) -#define INTC_ICDICER7_TXI2_SHIFT (8u) -#define INTC_ICDICER7_BRI3_SHIFT (9u) -#define INTC_ICDICER7_ERI3_SHIFT (10u) -#define INTC_ICDICER7_RXI3_SHIFT (11u) -#define INTC_ICDICER7_TXI3_SHIFT (12u) -#define INTC_ICDICER7_BRI4_SHIFT (13u) -#define INTC_ICDICER7_ERI4_SHIFT (14u) -#define INTC_ICDICER7_RXI4_SHIFT (15u) -#define INTC_ICDICER7_TXI4_SHIFT (16u) -#define INTC_ICDICER7_BRI5_SHIFT (17u) -#define INTC_ICDICER7_ERI5_SHIFT (18u) -#define INTC_ICDICER7_RXI5_SHIFT (19u) -#define INTC_ICDICER7_TXI5_SHIFT (20u) -#define INTC_ICDICER7_BRI6_SHIFT (21u) -#define INTC_ICDICER7_ERI6_SHIFT (22u) -#define INTC_ICDICER7_RXI6_SHIFT (23u) -#define INTC_ICDICER7_TXI6_SHIFT (24u) -#define INTC_ICDICER7_BRI7_SHIFT (25u) -#define INTC_ICDICER7_ERI7_SHIFT (26u) -#define INTC_ICDICER7_RXI7_SHIFT (27u) -#define INTC_ICDICER7_TXI7_SHIFT (28u) -#define INTC_ICDICER7_INTRCANGERR_SHIFT (29u) -#define INTC_ICDICER7_INTRCANGRECC_SHIFT (30u) -#define INTC_ICDICER7_INTRCAN0REC_SHIFT (31u) - -#define INTC_ICDICER8_INTRCAN0ERR_SHIFT (0u) -#define INTC_ICDICER8_INTRCAN0TRX_SHIFT (1u) -#define INTC_ICDICER8_INTRCAN1REC_SHIFT (2u) -#define INTC_ICDICER8_INTRCAN1ERR_SHIFT (3u) -#define INTC_ICDICER8_INTRCAN1TRX_SHIFT (4u) -#define INTC_ICDICER8_INTRCAN2REC_SHIFT (5u) -#define INTC_ICDICER8_INTRCAN2ERR_SHIFT (6u) -#define INTC_ICDICER8_INTRCAN2TRX_SHIFT (7u) -#define INTC_ICDICER8_INTRCAN3REC_SHIFT (8u) -#define INTC_ICDICER8_INTRCAN3ERR_SHIFT (9u) -#define INTC_ICDICER8_INTRCAN3TRX_SHIFT (10u) -#define INTC_ICDICER8_INTRCAN4REC_SHIFT (11u) -#define INTC_ICDICER8_INTRCAN4ERR_SHIFT (12u) -#define INTC_ICDICER8_INTRCAN4TRX_SHIFT (13u) -#define INTC_ICDICER8_SPEI0_SHIFT (14u) -#define INTC_ICDICER8_SPRI0_SHIFT (15u) -#define INTC_ICDICER8_SPTI0_SHIFT (16u) -#define INTC_ICDICER8_SPEI1_SHIFT (17u) -#define INTC_ICDICER8_SPRI1_SHIFT (18u) -#define INTC_ICDICER8_SPTI1_SHIFT (19u) -#define INTC_ICDICER8_SPEI2_SHIFT (20u) -#define INTC_ICDICER8_SPRI2_SHIFT (21u) -#define INTC_ICDICER8_SPTI2_SHIFT (22u) -#define INTC_ICDICER8_SPEI3_SHIFT (23u) -#define INTC_ICDICER8_SPRI3_SHIFT (24u) -#define INTC_ICDICER8_SPTI3_SHIFT (25u) -#define INTC_ICDICER8_SPEI4_SHIFT (26u) -#define INTC_ICDICER8_SPRI4_SHIFT (27u) -#define INTC_ICDICER8_SPTI4_SHIFT (28u) -#define INTC_ICDICER8_IEBBTD_SHIFT (29u) -#define INTC_ICDICER8_IEBBTERR_SHIFT (30u) -#define INTC_ICDICER8_IEBBTSTA_SHIFT (31u) - -#define INTC_ICDICER9_IEBBTV_SHIFT (0u) -#define INTC_ICDICER9_ISY_SHIFT (1u) -#define INTC_ICDICER9_IERR_SHIFT (2u) -#define INTC_ICDICER9_ITARG_SHIFT (3u) -#define INTC_ICDICER9_ISEC_SHIFT (4u) -#define INTC_ICDICER9_IBUF_SHIFT (5u) -#define INTC_ICDICER9_IREADY_SHIFT (6u) -#define INTC_ICDICER9_FLSTE_SHIFT (7u) -#define INTC_ICDICER9_FLTENDI_SHIFT (8u) -#define INTC_ICDICER9_FLTREQ0I_SHIFT (9u) -#define INTC_ICDICER9_FLTREQ1I_SHIFT (10u) -#define INTC_ICDICER9_MMC0_SHIFT (11u) -#define INTC_ICDICER9_MMC1_SHIFT (12u) -#define INTC_ICDICER9_MMC2_SHIFT (13u) -#define INTC_ICDICER9_SDHI0_3_SHIFT (14u) -#define INTC_ICDICER9_SDHI0_0_SHIFT (15u) -#define INTC_ICDICER9_SDHI0_1_SHIFT (16u) -#define INTC_ICDICER9_SDHI1_3_SHIFT (17u) -#define INTC_ICDICER9_SDHI1_0_SHIFT (18u) -#define INTC_ICDICER9_SDHI1_1_SHIFT (19u) -#define INTC_ICDICER9_ARM_SHIFT (20u) -#define INTC_ICDICER9_PRD_SHIFT (21u) -#define INTC_ICDICER9_CUP_SHIFT (22u) -#define INTC_ICDICER9_SCUAI0_SHIFT (23u) -#define INTC_ICDICER9_SCUAI1_SHIFT (24u) -#define INTC_ICDICER9_SCUFDI0_SHIFT (25u) -#define INTC_ICDICER9_SCUFDI1_SHIFT (26u) -#define INTC_ICDICER9_SCUFDI2_SHIFT (27u) -#define INTC_ICDICER9_SCUFDI3_SHIFT (28u) -#define INTC_ICDICER9_SCUFUI0_SHIFT (29u) -#define INTC_ICDICER9_SCUFUI1_SHIFT (30u) -#define INTC_ICDICER9_SCUFUI2_SHIFT (31u) - -#define INTC_ICDICER10_SCUFUI3_SHIFT (0u) -#define INTC_ICDICER10_SCUDVI0_SHIFT (1u) -#define INTC_ICDICER10_SCUDVI1_SHIFT (2u) -#define INTC_ICDICER10_SCUDVI2_SHIFT (3u) -#define INTC_ICDICER10_SCUDVI3_SHIFT (4u) -#define INTC_ICDICER10_MLB_CINT_SHIFT (5u) -#define INTC_ICDICER10_MLB_SINT_SHIFT (6u) -#define INTC_ICDICER10_DRC0_SHIFT (7u) -#define INTC_ICDICER10_DRC1_SHIFT (8u) -#define INTC_ICDICER10_LINI0_INT_T_SHIFT (11u) -#define INTC_ICDICER10_LINI0_INT_R_SHIFT (12u) -#define INTC_ICDICER10_LINI0_INT_S_SHIFT (13u) -#define INTC_ICDICER10_LINI0_INT_M_SHIFT (14u) -#define INTC_ICDICER10_LINI1_INT_T_SHIFT (15u) -#define INTC_ICDICER10_LINI1_INT_R_SHIFT (16u) -#define INTC_ICDICER10_LINI1_INT_S_SHIFT (17u) -#define INTC_ICDICER10_LINI1_INT_M_SHIFT (18u) -#define INTC_ICDICER10_ERI0_SHIFT (27u) -#define INTC_ICDICER10_RXI0_SHIFT (28u) -#define INTC_ICDICER10_TXI0_SHIFT (29u) -#define INTC_ICDICER10_TEI0_SHIFT (30u) -#define INTC_ICDICER10_ERI1_SHIFT (31u) - -#define INTC_ICDICER11_RXI1_SHIFT (0u) -#define INTC_ICDICER11_TXI1_SHIFT (1u) -#define INTC_ICDICER11_TEI1_SHIFT (2u) -#define INTC_ICDICER11_AVBI_DATA_SHIFT (3u) -#define INTC_ICDICER11_AVBI_ERROR_SHIFT (4u) -#define INTC_ICDICER11_AVBI_MANAGE_SHIFT (5u) -#define INTC_ICDICER11_AVBI_MAC_SHIFT (6u) -#define INTC_ICDICER11_ETHERI_SHIFT (7u) -#define INTC_ICDICER11_CEUI_SHIFT (12u) -#define INTC_ICDICER11_H2XMLB_ERRINT_SHIFT (29u) -#define INTC_ICDICER11_H2XIC1_ERRINT_SHIFT (30u) -#define INTC_ICDICER11_X2HPERI1_ERRINT_SHIFT (31u) - -#define INTC_ICDICER12_X2HPERI2_ERRINT_SHIFT (0u) -#define INTC_ICDICER12_X2HPERI34_ERRINT_SHIFT (1u) -#define INTC_ICDICER12_X2HPERI5_ERRINT_SHIFT (2u) -#define INTC_ICDICER12_X2HPERI67_ERRINT_SHIFT (3u) -#define INTC_ICDICER12_X2HDBGR_ERRINT_SHIFT (4u) -#define INTC_ICDICER12_X2HBSC_ERRINT_SHIFT (5u) -#define INTC_ICDICER12_X2HSPI1_ERRINT_SHIFT (6u) -#define INTC_ICDICER12_X2HSPI2_ERRINT_SHIFT (7u) -#define INTC_ICDICER12_PRRI_SHIFT (8u) -#define INTC_ICDICER12_IFEI0_SHIFT (9u) -#define INTC_ICDICER12_OFFI0_SHIFT (10u) -#define INTC_ICDICER12_PFVEI0_SHIFT (11u) -#define INTC_ICDICER12_IFEI1_SHIFT (12u) -#define INTC_ICDICER12_OFFI1_SHIFT (13u) -#define INTC_ICDICER12_PFVEI1_SHIFT (14u) - -#define INTC_ICDICER13_TINT0_SHIFT (0u) -#define INTC_ICDICER13_TINT1_SHIFT (1u) -#define INTC_ICDICER13_TINT2_SHIFT (2u) -#define INTC_ICDICER13_TINT3_SHIFT (3u) -#define INTC_ICDICER13_TINT4_SHIFT (4u) -#define INTC_ICDICER13_TINT5_SHIFT (5u) -#define INTC_ICDICER13_TINT6_SHIFT (6u) -#define INTC_ICDICER13_TINT7_SHIFT (7u) -#define INTC_ICDICER13_TINT8_SHIFT (8u) -#define INTC_ICDICER13_TINT9_SHIFT (9u) -#define INTC_ICDICER13_TINT10_SHIFT (10u) -#define INTC_ICDICER13_TINT11_SHIFT (11u) -#define INTC_ICDICER13_TINT12_SHIFT (12u) -#define INTC_ICDICER13_TINT13_SHIFT (13u) -#define INTC_ICDICER13_TINT14_SHIFT (14u) -#define INTC_ICDICER13_TINT15_SHIFT (15u) -#define INTC_ICDICER13_TINT16_SHIFT (16u) -#define INTC_ICDICER13_TINT17_SHIFT (17u) -#define INTC_ICDICER13_TINT18_SHIFT (18u) -#define INTC_ICDICER13_TINT19_SHIFT (19u) -#define INTC_ICDICER13_TINT20_SHIFT (20u) -#define INTC_ICDICER13_TINT21_SHIFT (21u) -#define INTC_ICDICER13_TINT22_SHIFT (22u) -#define INTC_ICDICER13_TINT23_SHIFT (23u) -#define INTC_ICDICER13_TINT24_SHIFT (24u) -#define INTC_ICDICER13_TINT25_SHIFT (25u) -#define INTC_ICDICER13_TINT26_SHIFT (26u) -#define INTC_ICDICER13_TINT27_SHIFT (27u) -#define INTC_ICDICER13_TINT28_SHIFT (28u) -#define INTC_ICDICER13_TINT29_SHIFT (29u) -#define INTC_ICDICER13_TINT30_SHIFT (30u) -#define INTC_ICDICER13_TINT31_SHIFT (31u) - -#define INTC_ICDICER14_TINT32_SHIFT (0u) -#define INTC_ICDICER14_TINT33_SHIFT (1u) -#define INTC_ICDICER14_TINT34_SHIFT (2u) -#define INTC_ICDICER14_TINT35_SHIFT (3u) -#define INTC_ICDICER14_TINT36_SHIFT (4u) -#define INTC_ICDICER14_TINT37_SHIFT (5u) -#define INTC_ICDICER14_TINT38_SHIFT (6u) -#define INTC_ICDICER14_TINT39_SHIFT (7u) -#define INTC_ICDICER14_TINT40_SHIFT (8u) -#define INTC_ICDICER14_TINT41_SHIFT (9u) -#define INTC_ICDICER14_TINT42_SHIFT (10u) -#define INTC_ICDICER14_TINT43_SHIFT (11u) -#define INTC_ICDICER14_TINT44_SHIFT (12u) -#define INTC_ICDICER14_TINT45_SHIFT (13u) -#define INTC_ICDICER14_TINT46_SHIFT (14u) -#define INTC_ICDICER14_TINT47_SHIFT (15u) -#define INTC_ICDICER14_TINT48_SHIFT (16u) -#define INTC_ICDICER14_TINT49_SHIFT (17u) -#define INTC_ICDICER14_TINT50_SHIFT (18u) -#define INTC_ICDICER14_TINT51_SHIFT (19u) -#define INTC_ICDICER14_TINT52_SHIFT (20u) -#define INTC_ICDICER14_TINT53_SHIFT (21u) -#define INTC_ICDICER14_TINT54_SHIFT (22u) -#define INTC_ICDICER14_TINT55_SHIFT (23u) -#define INTC_ICDICER14_TINT56_SHIFT (24u) -#define INTC_ICDICER14_TINT57_SHIFT (25u) -#define INTC_ICDICER14_TINT58_SHIFT (26u) -#define INTC_ICDICER14_TINT59_SHIFT (27u) -#define INTC_ICDICER14_TINT60_SHIFT (28u) -#define INTC_ICDICER14_TINT61_SHIFT (29u) -#define INTC_ICDICER14_TINT62_SHIFT (30u) -#define INTC_ICDICER14_TINT63_SHIFT (31u) - -#define INTC_ICDICER15_TINT64_SHIFT (0u) -#define INTC_ICDICER15_TINT65_SHIFT (1u) -#define INTC_ICDICER15_TINT66_SHIFT (2u) -#define INTC_ICDICER15_TINT67_SHIFT (3u) -#define INTC_ICDICER15_TINT68_SHIFT (4u) -#define INTC_ICDICER15_TINT69_SHIFT (5u) -#define INTC_ICDICER15_TINT70_SHIFT (6u) -#define INTC_ICDICER15_TINT71_SHIFT (7u) -#define INTC_ICDICER15_TINT72_SHIFT (8u) -#define INTC_ICDICER15_TINT73_SHIFT (9u) -#define INTC_ICDICER15_TINT74_SHIFT (10u) -#define INTC_ICDICER15_TINT75_SHIFT (11u) -#define INTC_ICDICER15_TINT76_SHIFT (12u) -#define INTC_ICDICER15_TINT77_SHIFT (13u) -#define INTC_ICDICER15_TINT78_SHIFT (14u) -#define INTC_ICDICER15_TINT79_SHIFT (15u) -#define INTC_ICDICER15_TINT80_SHIFT (16u) -#define INTC_ICDICER15_TINT81_SHIFT (17u) -#define INTC_ICDICER15_TINT82_SHIFT (18u) -#define INTC_ICDICER15_TINT83_SHIFT (19u) -#define INTC_ICDICER15_TINT84_SHIFT (20u) -#define INTC_ICDICER15_TINT85_SHIFT (21u) -#define INTC_ICDICER15_TINT86_SHIFT (22u) -#define INTC_ICDICER15_TINT87_SHIFT (23u) -#define INTC_ICDICER15_TINT88_SHIFT (24u) -#define INTC_ICDICER15_TINT89_SHIFT (25u) -#define INTC_ICDICER15_TINT90_SHIFT (26u) -#define INTC_ICDICER15_TINT91_SHIFT (27u) -#define INTC_ICDICER15_TINT92_SHIFT (28u) -#define INTC_ICDICER15_TINT93_SHIFT (29u) -#define INTC_ICDICER15_TINT94_SHIFT (30u) -#define INTC_ICDICER15_TINT95_SHIFT (31u) - -#define INTC_ICDICER16_TINT96_SHIFT (0u) -#define INTC_ICDICER16_TINT97_SHIFT (1u) -#define INTC_ICDICER16_TINT98_SHIFT (2u) -#define INTC_ICDICER16_TINT99_SHIFT (3u) -#define INTC_ICDICER16_TINT100_SHIFT (4u) -#define INTC_ICDICER16_TINT101_SHIFT (5u) -#define INTC_ICDICER16_TINT102_SHIFT (6u) -#define INTC_ICDICER16_TINT103_SHIFT (7u) -#define INTC_ICDICER16_TINT104_SHIFT (8u) -#define INTC_ICDICER16_TINT105_SHIFT (9u) -#define INTC_ICDICER16_TINT106_SHIFT (10u) -#define INTC_ICDICER16_TINT107_SHIFT (11u) -#define INTC_ICDICER16_TINT108_SHIFT (12u) -#define INTC_ICDICER16_TINT109_SHIFT (13u) -#define INTC_ICDICER16_TINT110_SHIFT (14u) -#define INTC_ICDICER16_TINT111_SHIFT (15u) -#define INTC_ICDICER16_TINT112_SHIFT (16u) -#define INTC_ICDICER16_TINT113_SHIFT (17u) -#define INTC_ICDICER16_TINT114_SHIFT (18u) -#define INTC_ICDICER16_TINT115_SHIFT (19u) -#define INTC_ICDICER16_TINT116_SHIFT (20u) -#define INTC_ICDICER16_TINT117_SHIFT (21u) -#define INTC_ICDICER16_TINT118_SHIFT (22u) -#define INTC_ICDICER16_TINT119_SHIFT (23u) -#define INTC_ICDICER16_TINT120_SHIFT (24u) -#define INTC_ICDICER16_TINT121_SHIFT (25u) -#define INTC_ICDICER16_TINT122_SHIFT (26u) -#define INTC_ICDICER16_TINT123_SHIFT (27u) -#define INTC_ICDICER16_TINT124_SHIFT (28u) -#define INTC_ICDICER16_TINT125_SHIFT (29u) -#define INTC_ICDICER16_TINT126_SHIFT (30u) -#define INTC_ICDICER16_TINT127_SHIFT (31u) - -#define INTC_ICDICER17_TINT128_SHIFT (0u) -#define INTC_ICDICER17_TINT129_SHIFT (1u) -#define INTC_ICDICER17_TINT130_SHIFT (2u) -#define INTC_ICDICER17_TINT131_SHIFT (3u) -#define INTC_ICDICER17_TINT132_SHIFT (4u) -#define INTC_ICDICER17_TINT133_SHIFT (5u) -#define INTC_ICDICER17_TINT134_SHIFT (6u) -#define INTC_ICDICER17_TINT135_SHIFT (7u) -#define INTC_ICDICER17_TINT136_SHIFT (8u) -#define INTC_ICDICER17_TINT137_SHIFT (9u) -#define INTC_ICDICER17_TINT138_SHIFT (10u) -#define INTC_ICDICER17_TINT139_SHIFT (11u) -#define INTC_ICDICER17_TINT140_SHIFT (12u) -#define INTC_ICDICER17_TINT141_SHIFT (13u) -#define INTC_ICDICER17_TINT142_SHIFT (14u) -#define INTC_ICDICER17_TINT143_SHIFT (15u) -#define INTC_ICDICER17_TINT144_SHIFT (16u) -#define INTC_ICDICER17_TINT145_SHIFT (17u) -#define INTC_ICDICER17_TINT146_SHIFT (18u) -#define INTC_ICDICER17_TINT147_SHIFT (19u) -#define INTC_ICDICER17_TINT148_SHIFT (20u) -#define INTC_ICDICER17_TINT149_SHIFT (21u) -#define INTC_ICDICER17_TINT150_SHIFT (22u) -#define INTC_ICDICER17_TINT151_SHIFT (23u) -#define INTC_ICDICER17_TINT152_SHIFT (24u) -#define INTC_ICDICER17_TINT153_SHIFT (25u) -#define INTC_ICDICER17_TINT154_SHIFT (26u) -#define INTC_ICDICER17_TINT155_SHIFT (27u) -#define INTC_ICDICER17_TINT156_SHIFT (28u) -#define INTC_ICDICER17_TINT157_SHIFT (29u) -#define INTC_ICDICER17_TINT158_SHIFT (30u) -#define INTC_ICDICER17_TINT159_SHIFT (31u) - -#define INTC_ICDICER18_TINT160_SHIFT (0u) -#define INTC_ICDICER18_TINT161_SHIFT (1u) -#define INTC_ICDICER18_TINT162_SHIFT (2u) -#define INTC_ICDICER18_TINT163_SHIFT (3u) -#define INTC_ICDICER18_TINT164_SHIFT (4u) -#define INTC_ICDICER18_TINT165_SHIFT (5u) -#define INTC_ICDICER18_TINT166_SHIFT (6u) -#define INTC_ICDICER18_TINT167_SHIFT (7u) -#define INTC_ICDICER18_TINT168_SHIFT (8u) -#define INTC_ICDICER18_TINT169_SHIFT (9u) -#define INTC_ICDICER18_TINT170_SHIFT (10u) - -#define INTC_ICDISPR0_SW0_SHIFT (0u) -#define INTC_ICDISPR0_SW1_SHIFT (1u) -#define INTC_ICDISPR0_SW2_SHIFT (2u) -#define INTC_ICDISPR0_SW3_SHIFT (3u) -#define INTC_ICDISPR0_SW4_SHIFT (4u) -#define INTC_ICDISPR0_SW5_SHIFT (5u) -#define INTC_ICDISPR0_SW6_SHIFT (6u) -#define INTC_ICDISPR0_SW7_SHIFT (7u) -#define INTC_ICDISPR0_SW8_SHIFT (8u) -#define INTC_ICDISPR0_SW9_SHIFT (9u) -#define INTC_ICDISPR0_SW10_SHIFT (10u) -#define INTC_ICDISPR0_SW11_SHIFT (11u) -#define INTC_ICDISPR0_SW12_SHIFT (12u) -#define INTC_ICDISPR0_SW13_SHIFT (13u) -#define INTC_ICDISPR0_SW14_SHIFT (14u) -#define INTC_ICDISPR0_SW15_SHIFT (15u) -#define INTC_ICDISPR0_PMUIRQ0_SHIFT (16u) -#define INTC_ICDISPR0_COMMRX0_SHIFT (17u) -#define INTC_ICDISPR0_COMMTX0_SHIFT (18u) -#define INTC_ICDISPR0_CTIIRQ0_SHIFT (19u) - -#define INTC_ICDISPR1_IRQ0_SHIFT (0u) -#define INTC_ICDISPR1_IRQ1_SHIFT (1u) -#define INTC_ICDISPR1_IRQ2_SHIFT (2u) -#define INTC_ICDISPR1_IRQ3_SHIFT (3u) -#define INTC_ICDISPR1_IRQ4_SHIFT (4u) -#define INTC_ICDISPR1_IRQ5_SHIFT (5u) -#define INTC_ICDISPR1_IRQ6_SHIFT (6u) -#define INTC_ICDISPR1_IRQ7_SHIFT (7u) -#define INTC_ICDISPR1_PL310ERR_SHIFT (8u) -#define INTC_ICDISPR1_DMAINT0_SHIFT (9u) -#define INTC_ICDISPR1_DMAINT1_SHIFT (10u) -#define INTC_ICDISPR1_DMAINT2_SHIFT (11u) -#define INTC_ICDISPR1_DMAINT3_SHIFT (12u) -#define INTC_ICDISPR1_DMAINT4_SHIFT (13u) -#define INTC_ICDISPR1_DMAINT5_SHIFT (14u) -#define INTC_ICDISPR1_DMAINT6_SHIFT (15u) -#define INTC_ICDISPR1_DMAINT7_SHIFT (16u) -#define INTC_ICDISPR1_DMAINT8_SHIFT (17u) -#define INTC_ICDISPR1_DMAINT9_SHIFT (18u) -#define INTC_ICDISPR1_DMAINT10_SHIFT (19u) -#define INTC_ICDISPR1_DMAINT11_SHIFT (20u) -#define INTC_ICDISPR1_DMAINT12_SHIFT (21u) -#define INTC_ICDISPR1_DMAINT13_SHIFT (22u) -#define INTC_ICDISPR1_DMAINT14_SHIFT (23u) -#define INTC_ICDISPR1_DMAINT15_SHIFT (24u) -#define INTC_ICDISPR1_DMAERR_SHIFT (25u) - -#define INTC_ICDISPR2_USBI0_SHIFT (9u) -#define INTC_ICDISPR2_USBI1_SHIFT (10u) -#define INTC_ICDISPR2_S0_VI_VSYNC0_SHIFT (11u) -#define INTC_ICDISPR2_S0_LO_VSYNC0_SHIFT (12u) -#define INTC_ICDISPR2_S0_VSYNCERR0_SHIFT (13u) -#define INTC_ICDISPR2_GR3_VLINE0_SHIFT (14u) -#define INTC_ICDISPR2_S0_VFIELD0_SHIFT (15u) -#define INTC_ICDISPR2_IV1_VBUFERR0_SHIFT (16u) -#define INTC_ICDISPR2_IV3_VBUFERR0_SHIFT (17u) -#define INTC_ICDISPR2_IV5_VBUFERR0_SHIFT (18u) -#define INTC_ICDISPR2_IV6_VBUFERR0_SHIFT (19u) -#define INTC_ICDISPR2_S0_WLINE0_SHIFT (20u) -#define INTC_ICDISPR2_S1_VI_VSYNC0_SHIFT (21u) -#define INTC_ICDISPR2_S1_LO_VSYNC0_SHIFT (22u) -#define INTC_ICDISPR2_S1_VSYNCERR0_SHIFT (23u) -#define INTC_ICDISPR2_S1_VFIELD0_SHIFT (24u) -#define INTC_ICDISPR2_IV2_VBUFERR0_SHIFT (25u) -#define INTC_ICDISPR2_IV4_VBUFERR0_SHIFT (26u) -#define INTC_ICDISPR2_S1_WLINE0_SHIFT (27u) -#define INTC_ICDISPR2_OIR_VI_VSYNC0_SHIFT (28u) -#define INTC_ICDISPR2_OIR_LO_VSYNC0_SHIFT (29u) -#define INTC_ICDISPR2_OIR_VSYNCERR0_SHIFT (30u) -#define INTC_ICDISPR2_OIR_VFIELD0_SHIFT (31u) - -#define INTC_ICDISPR3_IV7_VBUFERR0_SHIFT (0u) -#define INTC_ICDISPR3_IV8_VBUFERR0_SHIFT (1u) -#define INTC_ICDISPR3_S0_VI_VSYNC1_SHIFT (3u) -#define INTC_ICDISPR3_S0_LO_VSYNC1_SHIFT (4u) -#define INTC_ICDISPR3_S0_VSYNCERR1_SHIFT (5u) -#define INTC_ICDISPR3_GR3_VLINE1_SHIFT (6u) -#define INTC_ICDISPR3_S0_VFIELD1_SHIFT (7u) -#define INTC_ICDISPR3_IV1_VBUFERR1_SHIFT (8u) -#define INTC_ICDISPR3_IV3_VBUFERR1_SHIFT (9u) -#define INTC_ICDISPR3_IV5_VBUFERR1_SHIFT (10u) -#define INTC_ICDISPR3_IV6_VBUFERR1_SHIFT (11u) -#define INTC_ICDISPR3_S0_WLINE1_SHIFT (12u) -#define INTC_ICDISPR3_S1_VI_VSYNC1_SHIFT (13u) -#define INTC_ICDISPR3_S1_LO_VSYNC1_SHIFT (14u) -#define INTC_ICDISPR3_S1_VSYNCERR1_SHIFT (15u) -#define INTC_ICDISPR3_S1_VFIELD1_SHIFT (16u) -#define INTC_ICDISPR3_IV2_VBUFERR1_SHIFT (17u) -#define INTC_ICDISPR3_IV4_VBUFERR1_SHIFT (18u) -#define INTC_ICDISPR3_S1_WLINE1_SHIFT (19u) -#define INTC_ICDISPR3_OIR_VI_VSYNC1_SHIFT (20u) -#define INTC_ICDISPR3_OIR_LO_VSYNC1_SHIFT (21u) -#define INTC_ICDISPR3_OIR_VLINE1_SHIFT (22u) -#define INTC_ICDISPR3_OIR_VFIELD1_SHIFT (23u) -#define INTC_ICDISPR3_IV7_VBUFERR1_SHIFT (24u) -#define INTC_ICDISPR3_IV8_VBUFERR1_SHIFT (25u) -#define INTC_ICDISPR3_IMRDI_SHIFT (27u) -#define INTC_ICDISPR3_IMR2I0_SHIFT (28u) -#define INTC_ICDISPR3_IMR2I1_SHIFT (29u) -#define INTC_ICDISPR3_JEDI_SHIFT (30u) -#define INTC_ICDISPR3_JDTI_SHIFT (31u) - -#define INTC_ICDISPR4_CMP0_SHIFT (0u) -#define INTC_ICDISPR4_CMP1_SHIFT (1u) -#define INTC_ICDISPR4_INT0_SHIFT (2u) -#define INTC_ICDISPR4_INT1_SHIFT (3u) -#define INTC_ICDISPR4_INT2_SHIFT (4u) -#define INTC_ICDISPR4_INT3_SHIFT (5u) -#define INTC_ICDISPR4_OSTM0TINT_SHIFT (6u) -#define INTC_ICDISPR4_OSTM1TINT_SHIFT (7u) -#define INTC_ICDISPR4_CMI_SHIFT (8u) -#define INTC_ICDISPR4_WTOUT_SHIFT (9u) -#define INTC_ICDISPR4_ITI_SHIFT (10u) -#define INTC_ICDISPR4_TGI0A_SHIFT (11u) -#define INTC_ICDISPR4_TGI0B_SHIFT (12u) -#define INTC_ICDISPR4_TGI0C_SHIFT (13u) -#define INTC_ICDISPR4_TGI0D_SHIFT (14u) -#define INTC_ICDISPR4_TGI0V_SHIFT (15u) -#define INTC_ICDISPR4_TGI0E_SHIFT (16u) -#define INTC_ICDISPR4_TGI0F_SHIFT (17u) -#define INTC_ICDISPR4_TGI1A_SHIFT (18u) -#define INTC_ICDISPR4_TGI1B_SHIFT (19u) -#define INTC_ICDISPR4_TGI1V_SHIFT (20u) -#define INTC_ICDISPR4_TGI1U_SHIFT (21u) -#define INTC_ICDISPR4_TGI2A_SHIFT (22u) -#define INTC_ICDISPR4_TGI2B_SHIFT (23u) -#define INTC_ICDISPR4_TGI2V_SHIFT (24u) -#define INTC_ICDISPR4_TGI2U_SHIFT (25u) -#define INTC_ICDISPR4_TGI3A_SHIFT (26u) -#define INTC_ICDISPR4_TGI3B_SHIFT (27u) -#define INTC_ICDISPR4_TGI3C_SHIFT (28u) -#define INTC_ICDISPR4_TGI3D_SHIFT (29u) -#define INTC_ICDISPR4_TGI3V_SHIFT (30u) -#define INTC_ICDISPR4_TGI4A_SHIFT (31u) - -#define INTC_ICDISPR5_TGI4B_SHIFT (0u) -#define INTC_ICDISPR5_TGI4C_SHIFT (1u) -#define INTC_ICDISPR5_TGI4D_SHIFT (2u) -#define INTC_ICDISPR5_TGI4V_SHIFT (3u) -#define INTC_ICDISPR5_CMI1_SHIFT (4u) -#define INTC_ICDISPR5_CMI2_SHIFT (5u) -#define INTC_ICDISPR5_SGDEI0_SHIFT (6u) -#define INTC_ICDISPR5_SGDEI1_SHIFT (7u) -#define INTC_ICDISPR5_SGDEI2_SHIFT (8u) -#define INTC_ICDISPR5_SGDEI3_SHIFT (9u) -#define INTC_ICDISPR5_ADI_SHIFT (10u) -#define INTC_ICDISPR5_LMTI_SHIFT (11u) -#define INTC_ICDISPR5_SSII0_SHIFT (12u) -#define INTC_ICDISPR5_SSIRXI0_SHIFT (13u) -#define INTC_ICDISPR5_SSITXI0_SHIFT (14u) -#define INTC_ICDISPR5_SSII1_SHIFT (15u) -#define INTC_ICDISPR5_SSIRXI1_SHIFT (16u) -#define INTC_ICDISPR5_SSITXI1_SHIFT (17u) -#define INTC_ICDISPR5_SSII2_SHIFT (18u) -#define INTC_ICDISPR5_SSIRTI2_SHIFT (19u) -#define INTC_ICDISPR5_SSII3_SHIFT (20u) -#define INTC_ICDISPR5_SSIRXI3_SHIFT (21u) -#define INTC_ICDISPR5_SSITXI3_SHIFT (22u) -#define INTC_ICDISPR5_SSII4_SHIFT (23u) -#define INTC_ICDISPR5_SSIRTI4_SHIFT (24u) -#define INTC_ICDISPR5_SSII5_SHIFT (25u) -#define INTC_ICDISPR5_SSIRXI5_SHIFT (26u) -#define INTC_ICDISPR5_SSITXI5_SHIFT (27u) -#define INTC_ICDISPR5_SPDIFI_SHIFT (28u) -#define INTC_ICDISPR5_INTIICTEI0_SHIFT (29u) -#define INTC_ICDISPR5_INTIICRI0_SHIFT (30u) -#define INTC_ICDISPR5_INTIICTI0_SHIFT (31u) - -#define INTC_ICDISPR6_INTIICSPI0_SHIFT (0u) -#define INTC_ICDISPR6_INTIICSTI0_SHIFT (1u) -#define INTC_ICDISPR6_INTIICNAKI0_SHIFT (2u) -#define INTC_ICDISPR6_INTIICALI0_SHIFT (3u) -#define INTC_ICDISPR6_INTIICTMOI0_SHIFT (4u) -#define INTC_ICDISPR6_INTIICTEI1_SHIFT (5u) -#define INTC_ICDISPR6_INTIICRI1_SHIFT (6u) -#define INTC_ICDISPR6_INTIICTI1_SHIFT (7u) -#define INTC_ICDISPR6_INTIICSPI1_SHIFT (8u) -#define INTC_ICDISPR6_INTIICSTI1_SHIFT (9u) -#define INTC_ICDISPR6_INTIICNAKI1_SHIFT (10u) -#define INTC_ICDISPR6_INTIICALI1_SHIFT (11u) -#define INTC_ICDISPR6_INTIICTMOI1_SHIFT (12u) -#define INTC_ICDISPR6_INTIICTEI2_SHIFT (13u) -#define INTC_ICDISPR6_INTIICRI2_SHIFT (14u) -#define INTC_ICDISPR6_INTIICTI2_SHIFT (15u) -#define INTC_ICDISPR6_INTIICSPI2_SHIFT (16u) -#define INTC_ICDISPR6_INTIICSTI2_SHIFT (17u) -#define INTC_ICDISPR6_INTIICNAKI2_SHIFT (18u) -#define INTC_ICDISPR6_INTIICALI2_SHIFT (19u) -#define INTC_ICDISPR6_INTIICTMOI2_SHIFT (20u) -#define INTC_ICDISPR6_INTIICTEI3_SHIFT (21u) -#define INTC_ICDISPR6_INTIICRI3_SHIFT (22u) -#define INTC_ICDISPR6_INTIICTI3_SHIFT (23u) -#define INTC_ICDISPR6_INTIICSPI3_SHIFT (24u) -#define INTC_ICDISPR6_INTIICSTI3_SHIFT (25u) -#define INTC_ICDISPR6_INTIICNAKI3_SHIFT (26u) -#define INTC_ICDISPR6_INTIICALI3_SHIFT (27u) -#define INTC_ICDISPR6_INTIICTMOI3_SHIFT (28u) -#define INTC_ICDISPR6_BRI0_SHIFT (29u) -#define INTC_ICDISPR6_ERI0_SHIFT (30u) -#define INTC_ICDISPR6_RXI0_SHIFT (31u) - -#define INTC_ICDISPR7_TXI0_SHIFT (0u) -#define INTC_ICDISPR7_BRI1_SHIFT (1u) -#define INTC_ICDISPR7_ERI1_SHIFT (2u) -#define INTC_ICDISPR7_RXI1_SHIFT (3u) -#define INTC_ICDISPR7_TXI1_SHIFT (4u) -#define INTC_ICDISPR7_BRI2_SHIFT (5u) -#define INTC_ICDISPR7_ERI2_SHIFT (6u) -#define INTC_ICDISPR7_RXI2_SHIFT (7u) -#define INTC_ICDISPR7_TXI2_SHIFT (8u) -#define INTC_ICDISPR7_BRI3_SHIFT (9u) -#define INTC_ICDISPR7_ERI3_SHIFT (10u) -#define INTC_ICDISPR7_RXI3_SHIFT (11u) -#define INTC_ICDISPR7_TXI3_SHIFT (12u) -#define INTC_ICDISPR7_BRI4_SHIFT (13u) -#define INTC_ICDISPR7_ERI4_SHIFT (14u) -#define INTC_ICDISPR7_RXI4_SHIFT (15u) -#define INTC_ICDISPR7_TXI4_SHIFT (16u) -#define INTC_ICDISPR7_BRI5_SHIFT (17u) -#define INTC_ICDISPR7_ERI5_SHIFT (18u) -#define INTC_ICDISPR7_RXI5_SHIFT (19u) -#define INTC_ICDISPR7_TXI5_SHIFT (20u) -#define INTC_ICDISPR7_BRI6_SHIFT (21u) -#define INTC_ICDISPR7_ERI6_SHIFT (22u) -#define INTC_ICDISPR7_RXI6_SHIFT (23u) -#define INTC_ICDISPR7_TXI6_SHIFT (24u) -#define INTC_ICDISPR7_BRI7_SHIFT (25u) -#define INTC_ICDISPR7_ERI7_SHIFT (26u) -#define INTC_ICDISPR7_RXI7_SHIFT (27u) -#define INTC_ICDISPR7_TXI7_SHIFT (28u) -#define INTC_ICDISPR7_INTRCANGERR_SHIFT (29u) -#define INTC_ICDISPR7_INTRCANGRECC_SHIFT (30u) -#define INTC_ICDISPR7_INTRCAN0REC_SHIFT (31u) - -#define INTC_ICDISPR8_INTRCAN0ERR_SHIFT (0u) -#define INTC_ICDISPR8_INTRCAN0TRX_SHIFT (1u) -#define INTC_ICDISPR8_INTRCAN1REC_SHIFT (2u) -#define INTC_ICDISPR8_INTRCAN1ERR_SHIFT (3u) -#define INTC_ICDISPR8_INTRCAN1TRX_SHIFT (4u) -#define INTC_ICDISPR8_INTRCAN2REC_SHIFT (5u) -#define INTC_ICDISPR8_INTRCAN2ERR_SHIFT (6u) -#define INTC_ICDISPR8_INTRCAN2TRX_SHIFT (7u) -#define INTC_ICDISPR8_INTRCAN3REC_SHIFT (8u) -#define INTC_ICDISPR8_INTRCAN3ERR_SHIFT (9u) -#define INTC_ICDISPR8_INTRCAN3TRX_SHIFT (10u) -#define INTC_ICDISPR8_INTRCAN4REC_SHIFT (11u) -#define INTC_ICDISPR8_INTRCAN4ERR_SHIFT (12u) -#define INTC_ICDISPR8_INTRCAN4TRX_SHIFT (13u) -#define INTC_ICDISPR8_SPEI0_SHIFT (14u) -#define INTC_ICDISPR8_SPRI0_SHIFT (15u) -#define INTC_ICDISPR8_SPTI0_SHIFT (16u) -#define INTC_ICDISPR8_SPEI1_SHIFT (17u) -#define INTC_ICDISPR8_SPRI1_SHIFT (18u) -#define INTC_ICDISPR8_SPTI1_SHIFT (19u) -#define INTC_ICDISPR8_SPEI2_SHIFT (20u) -#define INTC_ICDISPR8_SPRI2_SHIFT (21u) -#define INTC_ICDISPR8_SPTI2_SHIFT (22u) -#define INTC_ICDISPR8_SPEI3_SHIFT (23u) -#define INTC_ICDISPR8_SPRI3_SHIFT (24u) -#define INTC_ICDISPR8_SPTI3_SHIFT (25u) -#define INTC_ICDISPR8_SPEI4_SHIFT (26u) -#define INTC_ICDISPR8_SPRI4_SHIFT (27u) -#define INTC_ICDISPR8_SPTI4_SHIFT (28u) -#define INTC_ICDISPR8_IEBBTD_SHIFT (29u) -#define INTC_ICDISPR8_IEBBTERR_SHIFT (30u) -#define INTC_ICDISPR8_IEBBTSTA_SHIFT (31u) - -#define INTC_ICDISPR9_IEBBTV_SHIFT (0u) -#define INTC_ICDISPR9_ISY_SHIFT (1u) -#define INTC_ICDISPR9_IERR_SHIFT (2u) -#define INTC_ICDISPR9_ITARG_SHIFT (3u) -#define INTC_ICDISPR9_ISEC_SHIFT (4u) -#define INTC_ICDISPR9_IBUF_SHIFT (5u) -#define INTC_ICDISPR9_IREADY_SHIFT (6u) -#define INTC_ICDISPR9_FLSTE_SHIFT (7u) -#define INTC_ICDISPR9_FLTENDI_SHIFT (8u) -#define INTC_ICDISPR9_FLTREQ0I_SHIFT (9u) -#define INTC_ICDISPR9_FLTREQ1I_SHIFT (10u) -#define INTC_ICDISPR9_MMC0_SHIFT (11u) -#define INTC_ICDISPR9_MMC1_SHIFT (12u) -#define INTC_ICDISPR9_MMC2_SHIFT (13u) -#define INTC_ICDISPR9_SDHI0_3_SHIFT (14u) -#define INTC_ICDISPR9_SDHI0_0_SHIFT (15u) -#define INTC_ICDISPR9_SDHI0_1_SHIFT (16u) -#define INTC_ICDISPR9_SDHI1_3_SHIFT (17u) -#define INTC_ICDISPR9_SDHI1_0_SHIFT (18u) -#define INTC_ICDISPR9_SDHI1_1_SHIFT (19u) -#define INTC_ICDISPR9_ARM_SHIFT (20u) -#define INTC_ICDISPR9_PRD_SHIFT (21u) -#define INTC_ICDISPR9_CUP_SHIFT (22u) -#define INTC_ICDISPR9_SCUAI0_SHIFT (23u) -#define INTC_ICDISPR9_SCUAI1_SHIFT (24u) -#define INTC_ICDISPR9_SCUFDI0_SHIFT (25u) -#define INTC_ICDISPR9_SCUFDI1_SHIFT (26u) -#define INTC_ICDISPR9_SCUFDI2_SHIFT (27u) -#define INTC_ICDISPR9_SCUFDI3_SHIFT (28u) -#define INTC_ICDISPR9_SCUFUI0_SHIFT (29u) -#define INTC_ICDISPR9_SCUFUI1_SHIFT (30u) -#define INTC_ICDISPR9_SCUFUI2_SHIFT (31u) - -#define INTC_ICDISPR10_SCUFUI3_SHIFT (0u) -#define INTC_ICDISPR10_SCUDVI0_SHIFT (1u) -#define INTC_ICDISPR10_SCUDVI1_SHIFT (2u) -#define INTC_ICDISPR10_SCUDVI2_SHIFT (3u) -#define INTC_ICDISPR10_SCUDVI3_SHIFT (4u) -#define INTC_ICDISPR10_MLB_CINT_SHIFT (5u) -#define INTC_ICDISPR10_MLB_SINT_SHIFT (6u) -#define INTC_ICDISPR10_DRC0_SHIFT (7u) -#define INTC_ICDISPR10_DRC1_SHIFT (8u) -#define INTC_ICDISPR10_LINI0_INT_T_SHIFT (11u) -#define INTC_ICDISPR10_LINI0_INT_R_SHIFT (12u) -#define INTC_ICDISPR10_LINI0_INT_S_SHIFT (13u) -#define INTC_ICDISPR10_LINI0_INT_M_SHIFT (14u) -#define INTC_ICDISPR10_LINI1_INT_T_SHIFT (15u) -#define INTC_ICDISPR10_LINI1_INT_R_SHIFT (16u) -#define INTC_ICDISPR10_LINI1_INT_S_SHIFT (17u) -#define INTC_ICDISPR10_LINI1_INT_M_SHIFT (18u) -#define INTC_ICDISPR10_ERI0_SHIFT (27u) -#define INTC_ICDISPR10_RXI0_SHIFT (28u) -#define INTC_ICDISPR10_TXI0_SHIFT (29u) -#define INTC_ICDISPR10_TEI0_SHIFT (30u) -#define INTC_ICDISPR10_ERI1_SHIFT (31u) - -#define INTC_ICDISPR11_RXI1_SHIFT (0u) -#define INTC_ICDISPR11_TXI1_SHIFT (1u) -#define INTC_ICDISPR11_TEI1_SHIFT (2u) -#define INTC_ICDISPR11_AVBI_DATA_SHIFT (3u) -#define INTC_ICDISPR11_AVBI_ERROR_SHIFT (4u) -#define INTC_ICDISPR11_AVBI_MANAGE_SHIFT (5u) -#define INTC_ICDISPR11_AVBI_MAC_SHIFT (6u) -#define INTC_ICDISPR11_ETHERI_SHIFT (7u) -#define INTC_ICDISPR11_CEUI_SHIFT (12u) -#define INTC_ICDISPR11_H2XMLB_ERRINT_SHIFT (29u) -#define INTC_ICDISPR11_H2XIC1_ERRINT_SHIFT (30u) -#define INTC_ICDISPR11_X2HPERI1_ERRINT_SHIFT (31u) - -#define INTC_ICDISPR12_X2HPERI2_ERRINT_SHIFT (0u) -#define INTC_ICDISPR12_X2HPERI34_ERRINT_SHIFT (1u) -#define INTC_ICDISPR12_X2HPERI5_ERRINT_SHIFT (2u) -#define INTC_ICDISPR12_X2HPERI67_ERRINT_SHIFT (3u) -#define INTC_ICDISPR12_X2HDBGR_ERRINT_SHIFT (4u) -#define INTC_ICDISPR12_X2HBSC_ERRINT_SHIFT (5u) -#define INTC_ICDISPR12_X2HSPI1_ERRINT_SHIFT (6u) -#define INTC_ICDISPR12_X2HSPI2_ERRINT_SHIFT (7u) -#define INTC_ICDISPR12_PRRI_SHIFT (8u) -#define INTC_ICDISPR12_IFEI0_SHIFT (9u) -#define INTC_ICDISPR12_OFFI0_SHIFT (10u) -#define INTC_ICDISPR12_PFVEI0_SHIFT (11u) -#define INTC_ICDISPR12_IFEI1_SHIFT (12u) -#define INTC_ICDISPR12_OFFI1_SHIFT (13u) -#define INTC_ICDISPR12_PFVEI1_SHIFT (14u) - -#define INTC_ICDISPR13_TINT0_SHIFT (0u) -#define INTC_ICDISPR13_TINT1_SHIFT (1u) -#define INTC_ICDISPR13_TINT2_SHIFT (2u) -#define INTC_ICDISPR13_TINT3_SHIFT (3u) -#define INTC_ICDISPR13_TINT4_SHIFT (4u) -#define INTC_ICDISPR13_TINT5_SHIFT (5u) -#define INTC_ICDISPR13_TINT6_SHIFT (6u) -#define INTC_ICDISPR13_TINT7_SHIFT (7u) -#define INTC_ICDISPR13_TINT8_SHIFT (8u) -#define INTC_ICDISPR13_TINT9_SHIFT (9u) -#define INTC_ICDISPR13_TINT10_SHIFT (10u) -#define INTC_ICDISPR13_TINT11_SHIFT (11u) -#define INTC_ICDISPR13_TINT12_SHIFT (12u) -#define INTC_ICDISPR13_TINT13_SHIFT (13u) -#define INTC_ICDISPR13_TINT14_SHIFT (14u) -#define INTC_ICDISPR13_TINT15_SHIFT (15u) -#define INTC_ICDISPR13_TINT16_SHIFT (16u) -#define INTC_ICDISPR13_TINT17_SHIFT (17u) -#define INTC_ICDISPR13_TINT18_SHIFT (18u) -#define INTC_ICDISPR13_TINT19_SHIFT (19u) -#define INTC_ICDISPR13_TINT20_SHIFT (20u) -#define INTC_ICDISPR13_TINT21_SHIFT (21u) -#define INTC_ICDISPR13_TINT22_SHIFT (22u) -#define INTC_ICDISPR13_TINT23_SHIFT (23u) -#define INTC_ICDISPR13_TINT24_SHIFT (24u) -#define INTC_ICDISPR13_TINT25_SHIFT (25u) -#define INTC_ICDISPR13_TINT26_SHIFT (26u) -#define INTC_ICDISPR13_TINT27_SHIFT (27u) -#define INTC_ICDISPR13_TINT28_SHIFT (28u) -#define INTC_ICDISPR13_TINT29_SHIFT (29u) -#define INTC_ICDISPR13_TINT30_SHIFT (30u) -#define INTC_ICDISPR13_TINT31_SHIFT (31u) - -#define INTC_ICDISPR14_TINT32_SHIFT (0u) -#define INTC_ICDISPR14_TINT33_SHIFT (1u) -#define INTC_ICDISPR14_TINT34_SHIFT (2u) -#define INTC_ICDISPR14_TINT35_SHIFT (3u) -#define INTC_ICDISPR14_TINT36_SHIFT (4u) -#define INTC_ICDISPR14_TINT37_SHIFT (5u) -#define INTC_ICDISPR14_TINT38_SHIFT (6u) -#define INTC_ICDISPR14_TINT39_SHIFT (7u) -#define INTC_ICDISPR14_TINT40_SHIFT (8u) -#define INTC_ICDISPR14_TINT41_SHIFT (9u) -#define INTC_ICDISPR14_TINT42_SHIFT (10u) -#define INTC_ICDISPR14_TINT43_SHIFT (11u) -#define INTC_ICDISPR14_TINT44_SHIFT (12u) -#define INTC_ICDISPR14_TINT45_SHIFT (13u) -#define INTC_ICDISPR14_TINT46_SHIFT (14u) -#define INTC_ICDISPR14_TINT47_SHIFT (15u) -#define INTC_ICDISPR14_TINT48_SHIFT (16u) -#define INTC_ICDISPR14_TINT49_SHIFT (17u) -#define INTC_ICDISPR14_TINT50_SHIFT (18u) -#define INTC_ICDISPR14_TINT51_SHIFT (19u) -#define INTC_ICDISPR14_TINT52_SHIFT (20u) -#define INTC_ICDISPR14_TINT53_SHIFT (21u) -#define INTC_ICDISPR14_TINT54_SHIFT (22u) -#define INTC_ICDISPR14_TINT55_SHIFT (23u) -#define INTC_ICDISPR14_TINT56_SHIFT (24u) -#define INTC_ICDISPR14_TINT57_SHIFT (25u) -#define INTC_ICDISPR14_TINT58_SHIFT (26u) -#define INTC_ICDISPR14_TINT59_SHIFT (27u) -#define INTC_ICDISPR14_TINT60_SHIFT (28u) -#define INTC_ICDISPR14_TINT61_SHIFT (29u) -#define INTC_ICDISPR14_TINT62_SHIFT (30u) -#define INTC_ICDISPR14_TINT63_SHIFT (31u) - -#define INTC_ICDISPR15_TINT64_SHIFT (0u) -#define INTC_ICDISPR15_TINT65_SHIFT (1u) -#define INTC_ICDISPR15_TINT66_SHIFT (2u) -#define INTC_ICDISPR15_TINT67_SHIFT (3u) -#define INTC_ICDISPR15_TINT68_SHIFT (4u) -#define INTC_ICDISPR15_TINT69_SHIFT (5u) -#define INTC_ICDISPR15_TINT70_SHIFT (6u) -#define INTC_ICDISPR15_TINT71_SHIFT (7u) -#define INTC_ICDISPR15_TINT72_SHIFT (8u) -#define INTC_ICDISPR15_TINT73_SHIFT (9u) -#define INTC_ICDISPR15_TINT74_SHIFT (10u) -#define INTC_ICDISPR15_TINT75_SHIFT (11u) -#define INTC_ICDISPR15_TINT76_SHIFT (12u) -#define INTC_ICDISPR15_TINT77_SHIFT (13u) -#define INTC_ICDISPR15_TINT78_SHIFT (14u) -#define INTC_ICDISPR15_TINT79_SHIFT (15u) -#define INTC_ICDISPR15_TINT80_SHIFT (16u) -#define INTC_ICDISPR15_TINT81_SHIFT (17u) -#define INTC_ICDISPR15_TINT82_SHIFT (18u) -#define INTC_ICDISPR15_TINT83_SHIFT (19u) -#define INTC_ICDISPR15_TINT84_SHIFT (20u) -#define INTC_ICDISPR15_TINT85_SHIFT (21u) -#define INTC_ICDISPR15_TINT86_SHIFT (22u) -#define INTC_ICDISPR15_TINT87_SHIFT (23u) -#define INTC_ICDISPR15_TINT88_SHIFT (24u) -#define INTC_ICDISPR15_TINT89_SHIFT (25u) -#define INTC_ICDISPR15_TINT90_SHIFT (26u) -#define INTC_ICDISPR15_TINT91_SHIFT (27u) -#define INTC_ICDISPR15_TINT92_SHIFT (28u) -#define INTC_ICDISPR15_TINT93_SHIFT (29u) -#define INTC_ICDISPR15_TINT94_SHIFT (30u) -#define INTC_ICDISPR15_TINT95_SHIFT (31u) - -#define INTC_ICDISPR16_TINT96_SHIFT (0u) -#define INTC_ICDISPR16_TINT97_SHIFT (1u) -#define INTC_ICDISPR16_TINT98_SHIFT (2u) -#define INTC_ICDISPR16_TINT99_SHIFT (3u) -#define INTC_ICDISPR16_TINT100_SHIFT (4u) -#define INTC_ICDISPR16_TINT101_SHIFT (5u) -#define INTC_ICDISPR16_TINT102_SHIFT (6u) -#define INTC_ICDISPR16_TINT103_SHIFT (7u) -#define INTC_ICDISPR16_TINT104_SHIFT (8u) -#define INTC_ICDISPR16_TINT105_SHIFT (9u) -#define INTC_ICDISPR16_TINT106_SHIFT (10u) -#define INTC_ICDISPR16_TINT107_SHIFT (11u) -#define INTC_ICDISPR16_TINT108_SHIFT (12u) -#define INTC_ICDISPR16_TINT109_SHIFT (13u) -#define INTC_ICDISPR16_TINT110_SHIFT (14u) -#define INTC_ICDISPR16_TINT111_SHIFT (15u) -#define INTC_ICDISPR16_TINT112_SHIFT (16u) -#define INTC_ICDISPR16_TINT113_SHIFT (17u) -#define INTC_ICDISPR16_TINT114_SHIFT (18u) -#define INTC_ICDISPR16_TINT115_SHIFT (19u) -#define INTC_ICDISPR16_TINT116_SHIFT (20u) -#define INTC_ICDISPR16_TINT117_SHIFT (21u) -#define INTC_ICDISPR16_TINT118_SHIFT (22u) -#define INTC_ICDISPR16_TINT119_SHIFT (23u) -#define INTC_ICDISPR16_TINT120_SHIFT (24u) -#define INTC_ICDISPR16_TINT121_SHIFT (25u) -#define INTC_ICDISPR16_TINT122_SHIFT (26u) -#define INTC_ICDISPR16_TINT123_SHIFT (27u) -#define INTC_ICDISPR16_TINT124_SHIFT (28u) -#define INTC_ICDISPR16_TINT125_SHIFT (29u) -#define INTC_ICDISPR16_TINT126_SHIFT (30u) -#define INTC_ICDISPR16_TINT127_SHIFT (31u) - -#define INTC_ICDISPR17_TINT128_SHIFT (0u) -#define INTC_ICDISPR17_TINT129_SHIFT (1u) -#define INTC_ICDISPR17_TINT130_SHIFT (2u) -#define INTC_ICDISPR17_TINT131_SHIFT (3u) -#define INTC_ICDISPR17_TINT132_SHIFT (4u) -#define INTC_ICDISPR17_TINT133_SHIFT (5u) -#define INTC_ICDISPR17_TINT134_SHIFT (6u) -#define INTC_ICDISPR17_TINT135_SHIFT (7u) -#define INTC_ICDISPR17_TINT136_SHIFT (8u) -#define INTC_ICDISPR17_TINT137_SHIFT (9u) -#define INTC_ICDISPR17_TINT138_SHIFT (10u) -#define INTC_ICDISPR17_TINT139_SHIFT (11u) -#define INTC_ICDISPR17_TINT140_SHIFT (12u) -#define INTC_ICDISPR17_TINT141_SHIFT (13u) -#define INTC_ICDISPR17_TINT142_SHIFT (14u) -#define INTC_ICDISPR17_TINT143_SHIFT (15u) -#define INTC_ICDISPR17_TINT144_SHIFT (16u) -#define INTC_ICDISPR17_TINT145_SHIFT (17u) -#define INTC_ICDISPR17_TINT146_SHIFT (18u) -#define INTC_ICDISPR17_TINT147_SHIFT (19u) -#define INTC_ICDISPR17_TINT148_SHIFT (20u) -#define INTC_ICDISPR17_TINT149_SHIFT (21u) -#define INTC_ICDISPR17_TINT150_SHIFT (22u) -#define INTC_ICDISPR17_TINT151_SHIFT (23u) -#define INTC_ICDISPR17_TINT152_SHIFT (24u) -#define INTC_ICDISPR17_TINT153_SHIFT (25u) -#define INTC_ICDISPR17_TINT154_SHIFT (26u) -#define INTC_ICDISPR17_TINT155_SHIFT (27u) -#define INTC_ICDISPR17_TINT156_SHIFT (28u) -#define INTC_ICDISPR17_TINT157_SHIFT (29u) -#define INTC_ICDISPR17_TINT158_SHIFT (30u) -#define INTC_ICDISPR17_TINT159_SHIFT (31u) - -#define INTC_ICDISPR18_TINT160_SHIFT (0u) -#define INTC_ICDISPR18_TINT161_SHIFT (1u) -#define INTC_ICDISPR18_TINT162_SHIFT (2u) -#define INTC_ICDISPR18_TINT163_SHIFT (3u) -#define INTC_ICDISPR18_TINT164_SHIFT (4u) -#define INTC_ICDISPR18_TINT165_SHIFT (5u) -#define INTC_ICDISPR18_TINT166_SHIFT (6u) -#define INTC_ICDISPR18_TINT167_SHIFT (7u) -#define INTC_ICDISPR18_TINT168_SHIFT (8u) -#define INTC_ICDISPR18_TINT169_SHIFT (9u) -#define INTC_ICDISPR18_TINT170_SHIFT (10u) - -#define INTC_ICDICPR0_SW0_SHIFT (0u) -#define INTC_ICDICPR0_SW1_SHIFT (1u) -#define INTC_ICDICPR0_SW2_SHIFT (2u) -#define INTC_ICDICPR0_SW3_SHIFT (3u) -#define INTC_ICDICPR0_SW4_SHIFT (4u) -#define INTC_ICDICPR0_SW5_SHIFT (5u) -#define INTC_ICDICPR0_SW6_SHIFT (6u) -#define INTC_ICDICPR0_SW7_SHIFT (7u) -#define INTC_ICDICPR0_SW8_SHIFT (8u) -#define INTC_ICDICPR0_SW9_SHIFT (9u) -#define INTC_ICDICPR0_SW10_SHIFT (10u) -#define INTC_ICDICPR0_SW11_SHIFT (11u) -#define INTC_ICDICPR0_SW12_SHIFT (12u) -#define INTC_ICDICPR0_SW13_SHIFT (13u) -#define INTC_ICDICPR0_SW14_SHIFT (14u) -#define INTC_ICDICPR0_SW15_SHIFT (15u) -#define INTC_ICDICPR0_PMUIRQ0_SHIFT (16u) -#define INTC_ICDICPR0_COMMRX0_SHIFT (17u) -#define INTC_ICDICPR0_COMMTX0_SHIFT (18u) -#define INTC_ICDICPR0_CTIIRQ0_SHIFT (19u) - -#define INTC_ICDICPR1_IRQ0_SHIFT (0u) -#define INTC_ICDICPR1_IRQ1_SHIFT (1u) -#define INTC_ICDICPR1_IRQ2_SHIFT (2u) -#define INTC_ICDICPR1_IRQ3_SHIFT (3u) -#define INTC_ICDICPR1_IRQ4_SHIFT (4u) -#define INTC_ICDICPR1_IRQ5_SHIFT (5u) -#define INTC_ICDICPR1_IRQ6_SHIFT (6u) -#define INTC_ICDICPR1_IRQ7_SHIFT (7u) -#define INTC_ICDICPR1_PL310ERR_SHIFT (8u) -#define INTC_ICDICPR1_DMAINT0_SHIFT (9u) -#define INTC_ICDICPR1_DMAINT1_SHIFT (10u) -#define INTC_ICDICPR1_DMAINT2_SHIFT (11u) -#define INTC_ICDICPR1_DMAINT3_SHIFT (12u) -#define INTC_ICDICPR1_DMAINT4_SHIFT (13u) -#define INTC_ICDICPR1_DMAINT5_SHIFT (14u) -#define INTC_ICDICPR1_DMAINT6_SHIFT (15u) -#define INTC_ICDICPR1_DMAINT7_SHIFT (16u) -#define INTC_ICDICPR1_DMAINT8_SHIFT (17u) -#define INTC_ICDICPR1_DMAINT9_SHIFT (18u) -#define INTC_ICDICPR1_DMAINT10_SHIFT (19u) -#define INTC_ICDICPR1_DMAINT11_SHIFT (20u) -#define INTC_ICDICPR1_DMAINT12_SHIFT (21u) -#define INTC_ICDICPR1_DMAINT13_SHIFT (22u) -#define INTC_ICDICPR1_DMAINT14_SHIFT (23u) -#define INTC_ICDICPR1_DMAINT15_SHIFT (24u) -#define INTC_ICDICPR1_DMAERR_SHIFT (25u) - -#define INTC_ICDICPR2_USBI0_SHIFT (9u) -#define INTC_ICDICPR2_USBI1_SHIFT (10u) -#define INTC_ICDICPR2_S0_VI_VSYNC0_SHIFT (11u) -#define INTC_ICDICPR2_S0_LO_VSYNC0_SHIFT (12u) -#define INTC_ICDICPR2_S0_VSYNCERR0_SHIFT (13u) -#define INTC_ICDICPR2_GR3_VLINE0_SHIFT (14u) -#define INTC_ICDICPR2_S0_VFIELD0_SHIFT (15u) -#define INTC_ICDICPR2_IV1_VBUFERR0_SHIFT (16u) -#define INTC_ICDICPR2_IV3_VBUFERR0_SHIFT (17u) -#define INTC_ICDICPR2_IV5_VBUFERR0_SHIFT (18u) -#define INTC_ICDICPR2_IV6_VBUFERR0_SHIFT (19u) -#define INTC_ICDICPR2_S0_WLINE0_SHIFT (20u) -#define INTC_ICDICPR2_S1_VI_VSYNC0_SHIFT (21u) -#define INTC_ICDICPR2_S1_LO_VSYNC0_SHIFT (22u) -#define INTC_ICDICPR2_S1_VSYNCERR0_SHIFT (23u) -#define INTC_ICDICPR2_S1_VFIELD0_SHIFT (24u) -#define INTC_ICDICPR2_IV2_VBUFERR0_SHIFT (25u) -#define INTC_ICDICPR2_IV4_VBUFERR0_SHIFT (26u) -#define INTC_ICDICPR2_S1_WLINE0_SHIFT (27u) -#define INTC_ICDICPR2_OIR_VI_VSYNC0_SHIFT (28u) -#define INTC_ICDICPR2_OIR_LO_VSYNC0_SHIFT (29u) -#define INTC_ICDICPR2_OIR_VSYNCERR0_SHIFT (30u) -#define INTC_ICDICPR2_OIR_VFIELD0_SHIFT (31u) - -#define INTC_ICDICPR3_IV7_VBUFERR0_SHIFT (0u) -#define INTC_ICDICPR3_IV8_VBUFERR0_SHIFT (1u) -#define INTC_ICDICPR3_S0_VI_VSYNC1_SHIFT (3u) -#define INTC_ICDICPR3_S0_LO_VSYNC1_SHIFT (4u) -#define INTC_ICDICPR3_S0_VSYNCERR1_SHIFT (5u) -#define INTC_ICDICPR3_GR3_VLINE1_SHIFT (6u) -#define INTC_ICDICPR3_S0_VFIELD1_SHIFT (7u) -#define INTC_ICDICPR3_IV1_VBUFERR1_SHIFT (8u) -#define INTC_ICDICPR3_IV3_VBUFERR1_SHIFT (9u) -#define INTC_ICDICPR3_IV5_VBUFERR1_SHIFT (10u) -#define INTC_ICDICPR3_IV6_VBUFERR1_SHIFT (11u) -#define INTC_ICDICPR3_S0_WLINE1_SHIFT (12u) -#define INTC_ICDICPR3_S1_VI_VSYNC1_SHIFT (13u) -#define INTC_ICDICPR3_S1_LO_VSYNC1_SHIFT (14u) -#define INTC_ICDICPR3_S1_VSYNCERR1_SHIFT (15u) -#define INTC_ICDICPR3_S1_VFIELD1_SHIFT (16u) -#define INTC_ICDICPR3_IV2_VBUFERR1_SHIFT (17u) -#define INTC_ICDICPR3_IV4_VBUFERR1_SHIFT (18u) -#define INTC_ICDICPR3_S1_WLINE1_SHIFT (19u) -#define INTC_ICDICPR3_OIR_VI_VSYNC1_SHIFT (20u) -#define INTC_ICDICPR3_OIR_LO_VSYNC1_SHIFT (21u) -#define INTC_ICDICPR3_OIR_VLINE1_SHIFT (22u) -#define INTC_ICDICPR3_OIR_VFIELD1_SHIFT (23u) -#define INTC_ICDICPR3_IV7_VBUFERR1_SHIFT (24u) -#define INTC_ICDICPR3_IV8_VBUFERR1_SHIFT (25u) -#define INTC_ICDICPR3_IMRDI_SHIFT (27u) -#define INTC_ICDICPR3_IMR2I0_SHIFT (28u) -#define INTC_ICDICPR3_IMR2I1_SHIFT (29u) -#define INTC_ICDICPR3_JEDI_SHIFT (30u) -#define INTC_ICDICPR3_JDTI_SHIFT (31u) - -#define INTC_ICDICPR4_CMP0_SHIFT (0u) -#define INTC_ICDICPR4_CMP1_SHIFT (1u) -#define INTC_ICDICPR4_INT0_SHIFT (2u) -#define INTC_ICDICPR4_INT1_SHIFT (3u) -#define INTC_ICDICPR4_INT2_SHIFT (4u) -#define INTC_ICDICPR4_INT3_SHIFT (5u) -#define INTC_ICDICPR4_OSTM0TINT_SHIFT (6u) -#define INTC_ICDICPR4_OSTM1TINT_SHIFT (7u) -#define INTC_ICDICPR4_CMI_SHIFT (8u) -#define INTC_ICDICPR4_WTOUT_SHIFT (9u) -#define INTC_ICDICPR4_ITI_SHIFT (10u) -#define INTC_ICDICPR4_TGI0A_SHIFT (11u) -#define INTC_ICDICPR4_TGI0B_SHIFT (12u) -#define INTC_ICDICPR4_TGI0C_SHIFT (13u) -#define INTC_ICDICPR4_TGI0D_SHIFT (14u) -#define INTC_ICDICPR4_TGI0V_SHIFT (15u) -#define INTC_ICDICPR4_TGI0E_SHIFT (16u) -#define INTC_ICDICPR4_TGI0F_SHIFT (17u) -#define INTC_ICDICPR4_TGI1A_SHIFT (18u) -#define INTC_ICDICPR4_TGI1B_SHIFT (19u) -#define INTC_ICDICPR4_TGI1V_SHIFT (20u) -#define INTC_ICDICPR4_TGI1U_SHIFT (21u) -#define INTC_ICDICPR4_TGI2A_SHIFT (22u) -#define INTC_ICDICPR4_TGI2B_SHIFT (23u) -#define INTC_ICDICPR4_TGI2V_SHIFT (24u) -#define INTC_ICDICPR4_TGI2U_SHIFT (25u) -#define INTC_ICDICPR4_TGI3A_SHIFT (26u) -#define INTC_ICDICPR4_TGI3B_SHIFT (27u) -#define INTC_ICDICPR4_TGI3C_SHIFT (28u) -#define INTC_ICDICPR4_TGI3D_SHIFT (29u) -#define INTC_ICDICPR4_TGI3V_SHIFT (30u) -#define INTC_ICDICPR4_TGI4A_SHIFT (31u) - -#define INTC_ICDICPR5_TGI4B_SHIFT (0u) -#define INTC_ICDICPR5_TGI4C_SHIFT (1u) -#define INTC_ICDICPR5_TGI4D_SHIFT (2u) -#define INTC_ICDICPR5_TGI4V_SHIFT (3u) -#define INTC_ICDICPR5_CMI1_SHIFT (4u) -#define INTC_ICDICPR5_CMI2_SHIFT (5u) -#define INTC_ICDICPR5_SGDEI0_SHIFT (6u) -#define INTC_ICDICPR5_SGDEI1_SHIFT (7u) -#define INTC_ICDICPR5_SGDEI2_SHIFT (8u) -#define INTC_ICDICPR5_SGDEI3_SHIFT (9u) -#define INTC_ICDICPR5_ADI_SHIFT (10u) -#define INTC_ICDICPR5_LMTI_SHIFT (11u) -#define INTC_ICDICPR5_SSII0_SHIFT (12u) -#define INTC_ICDICPR5_SSIRXI0_SHIFT (13u) -#define INTC_ICDICPR5_SSITXI0_SHIFT (14u) -#define INTC_ICDICPR5_SSII1_SHIFT (15u) -#define INTC_ICDICPR5_SSIRXI1_SHIFT (16u) -#define INTC_ICDICPR5_SSITXI1_SHIFT (17u) -#define INTC_ICDICPR5_SSII2_SHIFT (18u) -#define INTC_ICDICPR5_SSIRTI2_SHIFT (19u) -#define INTC_ICDICPR5_SSII3_SHIFT (20u) -#define INTC_ICDICPR5_SSIRXI3_SHIFT (21u) -#define INTC_ICDICPR5_SSITXI3_SHIFT (22u) -#define INTC_ICDICPR5_SSII4_SHIFT (23u) -#define INTC_ICDICPR5_SSIRTI4_SHIFT (24u) -#define INTC_ICDICPR5_SSII5_SHIFT (25u) -#define INTC_ICDICPR5_SSIRXI5_SHIFT (26u) -#define INTC_ICDICPR5_SSITXI5_SHIFT (27u) -#define INTC_ICDICPR5_SPDIFI_SHIFT (28u) -#define INTC_ICDICPR5_INTIICTEI0_SHIFT (29u) -#define INTC_ICDICPR5_INTIICRI0_SHIFT (30u) -#define INTC_ICDICPR5_INTIICTI0_SHIFT (31u) - -#define INTC_ICDICPR6_INTIICSPI0_SHIFT (0u) -#define INTC_ICDICPR6_INTIICSTI0_SHIFT (1u) -#define INTC_ICDICPR6_INTIICNAKI0_SHIFT (2u) -#define INTC_ICDICPR6_INTIICALI0_SHIFT (3u) -#define INTC_ICDICPR6_INTIICTMOI0_SHIFT (4u) -#define INTC_ICDICPR6_INTIICTEI1_SHIFT (5u) -#define INTC_ICDICPR6_INTIICRI1_SHIFT (6u) -#define INTC_ICDICPR6_INTIICTI1_SHIFT (7u) -#define INTC_ICDICPR6_INTIICSPI1_SHIFT (8u) -#define INTC_ICDICPR6_INTIICSTI1_SHIFT (9u) -#define INTC_ICDICPR6_INTIICNAKI1_SHIFT (10u) -#define INTC_ICDICPR6_INTIICALI1_SHIFT (11u) -#define INTC_ICDICPR6_INTIICTMOI1_SHIFT (12u) -#define INTC_ICDICPR6_INTIICTEI2_SHIFT (13u) -#define INTC_ICDICPR6_INTIICRI2_SHIFT (14u) -#define INTC_ICDICPR6_INTIICTI2_SHIFT (15u) -#define INTC_ICDICPR6_INTIICSPI2_SHIFT (16u) -#define INTC_ICDICPR6_INTIICSTI2_SHIFT (17u) -#define INTC_ICDICPR6_INTIICNAKI2_SHIFT (18u) -#define INTC_ICDICPR6_INTIICALI2_SHIFT (19u) -#define INTC_ICDICPR6_INTIICTMOI2_SHIFT (20u) -#define INTC_ICDICPR6_INTIICTEI3_SHIFT (21u) -#define INTC_ICDICPR6_INTIICRI3_SHIFT (22u) -#define INTC_ICDICPR6_INTIICTI3_SHIFT (23u) -#define INTC_ICDICPR6_INTIICSPI3_SHIFT (24u) -#define INTC_ICDICPR6_INTIICSTI3_SHIFT (25u) -#define INTC_ICDICPR6_INTIICNAKI3_SHIFT (26u) -#define INTC_ICDICPR6_INTIICALI3_SHIFT (27u) -#define INTC_ICDICPR6_INTIICTMOI3_SHIFT (28u) -#define INTC_ICDICPR6_BRI0_SHIFT (29u) -#define INTC_ICDICPR6_ERI0_SHIFT (30u) -#define INTC_ICDICPR6_RXI0_SHIFT (31u) - -#define INTC_ICDICPR7_TXI0_SHIFT (0u) -#define INTC_ICDICPR7_BRI1_SHIFT (1u) -#define INTC_ICDICPR7_ERI1_SHIFT (2u) -#define INTC_ICDICPR7_RXI1_SHIFT (3u) -#define INTC_ICDICPR7_TXI1_SHIFT (4u) -#define INTC_ICDICPR7_BRI2_SHIFT (5u) -#define INTC_ICDICPR7_ERI2_SHIFT (6u) -#define INTC_ICDICPR7_RXI2_SHIFT (7u) -#define INTC_ICDICPR7_TXI2_SHIFT (8u) -#define INTC_ICDICPR7_BRI3_SHIFT (9u) -#define INTC_ICDICPR7_ERI3_SHIFT (10u) -#define INTC_ICDICPR7_RXI3_SHIFT (11u) -#define INTC_ICDICPR7_TXI3_SHIFT (12u) -#define INTC_ICDICPR7_BRI4_SHIFT (13u) -#define INTC_ICDICPR7_ERI4_SHIFT (14u) -#define INTC_ICDICPR7_RXI4_SHIFT (15u) -#define INTC_ICDICPR7_TXI4_SHIFT (16u) -#define INTC_ICDICPR7_BRI5_SHIFT (17u) -#define INTC_ICDICPR7_ERI5_SHIFT (18u) -#define INTC_ICDICPR7_RXI5_SHIFT (19u) -#define INTC_ICDICPR7_TXI5_SHIFT (20u) -#define INTC_ICDICPR7_BRI6_SHIFT (21u) -#define INTC_ICDICPR7_ERI6_SHIFT (22u) -#define INTC_ICDICPR7_RXI6_SHIFT (23u) -#define INTC_ICDICPR7_TXI6_SHIFT (24u) -#define INTC_ICDICPR7_BRI7_SHIFT (25u) -#define INTC_ICDICPR7_ERI7_SHIFT (26u) -#define INTC_ICDICPR7_RXI7_SHIFT (27u) -#define INTC_ICDICPR7_TXI7_SHIFT (28u) -#define INTC_ICDICPR7_INTRCANGERR_SHIFT (29u) -#define INTC_ICDICPR7_INTRCANGRECC_SHIFT (30u) -#define INTC_ICDICPR7_INTRCAN0REC_SHIFT (31u) - -#define INTC_ICDICPR8_INTRCAN0ERR_SHIFT (0u) -#define INTC_ICDICPR8_INTRCAN0TRX_SHIFT (1u) -#define INTC_ICDICPR8_INTRCAN1REC_SHIFT (2u) -#define INTC_ICDICPR8_INTRCAN1ERR_SHIFT (3u) -#define INTC_ICDICPR8_INTRCAN1TRX_SHIFT (4u) -#define INTC_ICDICPR8_INTRCAN2REC_SHIFT (5u) -#define INTC_ICDICPR8_INTRCAN2ERR_SHIFT (6u) -#define INTC_ICDICPR8_INTRCAN2TRX_SHIFT (7u) -#define INTC_ICDICPR8_INTRCAN3REC_SHIFT (8u) -#define INTC_ICDICPR8_INTRCAN3ERR_SHIFT (9u) -#define INTC_ICDICPR8_INTRCAN3TRX_SHIFT (10u) -#define INTC_ICDICPR8_INTRCAN4REC_SHIFT (11u) -#define INTC_ICDICPR8_INTRCAN4ERR_SHIFT (12u) -#define INTC_ICDICPR8_INTRCAN4TRX_SHIFT (13u) -#define INTC_ICDICPR8_SPEI0_SHIFT (14u) -#define INTC_ICDICPR8_SPRI0_SHIFT (15u) -#define INTC_ICDICPR8_SPTI0_SHIFT (16u) -#define INTC_ICDICPR8_SPEI1_SHIFT (17u) -#define INTC_ICDICPR8_SPRI1_SHIFT (18u) -#define INTC_ICDICPR8_SPTI1_SHIFT (19u) -#define INTC_ICDICPR8_SPEI2_SHIFT (20u) -#define INTC_ICDICPR8_SPRI2_SHIFT (21u) -#define INTC_ICDICPR8_SPTI2_SHIFT (22u) -#define INTC_ICDICPR8_SPEI3_SHIFT (23u) -#define INTC_ICDICPR8_SPRI3_SHIFT (24u) -#define INTC_ICDICPR8_SPTI3_SHIFT (25u) -#define INTC_ICDICPR8_SPEI4_SHIFT (26u) -#define INTC_ICDICPR8_SPRI4_SHIFT (27u) -#define INTC_ICDICPR8_SPTI4_SHIFT (28u) -#define INTC_ICDICPR8_IEBBTD_SHIFT (29u) -#define INTC_ICDICPR8_IEBBTERR_SHIFT (30u) -#define INTC_ICDICPR8_IEBBTSTA_SHIFT (31u) - -#define INTC_ICDICPR9_IEBBTV_SHIFT (0u) -#define INTC_ICDICPR9_ISY_SHIFT (1u) -#define INTC_ICDICPR9_IERR_SHIFT (2u) -#define INTC_ICDICPR9_ITARG_SHIFT (3u) -#define INTC_ICDICPR9_ISEC_SHIFT (4u) -#define INTC_ICDICPR9_IBUF_SHIFT (5u) -#define INTC_ICDICPR9_IREADY_SHIFT (6u) -#define INTC_ICDICPR9_FLSTE_SHIFT (7u) -#define INTC_ICDICPR9_FLTENDI_SHIFT (8u) -#define INTC_ICDICPR9_FLTREQ0I_SHIFT (9u) -#define INTC_ICDICPR9_FLTREQ1I_SHIFT (10u) -#define INTC_ICDICPR9_MMC0_SHIFT (11u) -#define INTC_ICDICPR9_MMC1_SHIFT (12u) -#define INTC_ICDICPR9_MMC2_SHIFT (13u) -#define INTC_ICDICPR9_SDHI0_3_SHIFT (14u) -#define INTC_ICDICPR9_SDHI0_0_SHIFT (15u) -#define INTC_ICDICPR9_SDHI0_1_SHIFT (16u) -#define INTC_ICDICPR9_SDHI1_3_SHIFT (17u) -#define INTC_ICDICPR9_SDHI1_0_SHIFT (18u) -#define INTC_ICDICPR9_SDHI1_1_SHIFT (19u) -#define INTC_ICDICPR9_ARM_SHIFT (20u) -#define INTC_ICDICPR9_PRD_SHIFT (21u) -#define INTC_ICDICPR9_CUP_SHIFT (22u) -#define INTC_ICDICPR9_SCUAI0_SHIFT (23u) -#define INTC_ICDICPR9_SCUAI1_SHIFT (24u) -#define INTC_ICDICPR9_SCUFDI0_SHIFT (25u) -#define INTC_ICDICPR9_SCUFDI1_SHIFT (26u) -#define INTC_ICDICPR9_SCUFDI2_SHIFT (27u) -#define INTC_ICDICPR9_SCUFDI3_SHIFT (28u) -#define INTC_ICDICPR9_SCUFUI0_SHIFT (29u) -#define INTC_ICDICPR9_SCUFUI1_SHIFT (30u) -#define INTC_ICDICPR9_SCUFUI2_SHIFT (31u) - -#define INTC_ICDICPR10_SCUFUI3_SHIFT (0u) -#define INTC_ICDICPR10_SCUDVI0_SHIFT (1u) -#define INTC_ICDICPR10_SCUDVI1_SHIFT (2u) -#define INTC_ICDICPR10_SCUDVI2_SHIFT (3u) -#define INTC_ICDICPR10_SCUDVI3_SHIFT (4u) -#define INTC_ICDICPR10_MLB_CINT_SHIFT (5u) -#define INTC_ICDICPR10_MLB_SINT_SHIFT (6u) -#define INTC_ICDICPR10_DRC0_SHIFT (7u) -#define INTC_ICDICPR10_DRC1_SHIFT (8u) -#define INTC_ICDICPR10_LINI0_INT_T_SHIFT (11u) -#define INTC_ICDICPR10_LINI0_INT_R_SHIFT (12u) -#define INTC_ICDICPR10_LINI0_INT_S_SHIFT (13u) -#define INTC_ICDICPR10_LINI0_INT_M_SHIFT (14u) -#define INTC_ICDICPR10_LINI1_INT_T_SHIFT (15u) -#define INTC_ICDICPR10_LINI1_INT_R_SHIFT (16u) -#define INTC_ICDICPR10_LINI1_INT_S_SHIFT (17u) -#define INTC_ICDICPR10_LINI1_INT_M_SHIFT (18u) -#define INTC_ICDICPR10_ERI0_SHIFT (27u) -#define INTC_ICDICPR10_RXI0_SHIFT (28u) -#define INTC_ICDICPR10_TXI0_SHIFT (29u) -#define INTC_ICDICPR10_TEI0_SHIFT (30u) -#define INTC_ICDICPR10_ERI1_SHIFT (31u) - -#define INTC_ICDICPR11_RXI1_SHIFT (0u) -#define INTC_ICDICPR11_TXI1_SHIFT (1u) -#define INTC_ICDICPR11_TEI1_SHIFT (2u) -#define INTC_ICDICPR11_AVBI_DATA_SHIFT (3u) -#define INTC_ICDICPR11_AVBI_ERROR_SHIFT (4u) -#define INTC_ICDICPR11_AVBI_MANAGE_SHIFT (5u) -#define INTC_ICDICPR11_AVBI_MAC_SHIFT (6u) -#define INTC_ICDICPR11_ETHERI_SHIFT (7u) -#define INTC_ICDICPR11_CEUI_SHIFT (12u) -#define INTC_ICDICPR11_H2XMLB_ERRINT_SHIFT (29u) -#define INTC_ICDICPR11_H2XIC1_ERRINT_SHIFT (30u) -#define INTC_ICDICPR11_X2HPERI1_ERRINT_SHIFT (31u) - -#define INTC_ICDICPR12_X2HPERI2_ERRINT_SHIFT (0u) -#define INTC_ICDICPR12_X2HPERI34_ERRINT_SHIFT (1u) -#define INTC_ICDICPR12_X2HPERI5_ERRINT_SHIFT (2u) -#define INTC_ICDICPR12_X2HPERI67_ERRINT_SHIFT (3u) -#define INTC_ICDICPR12_X2HDBGR_ERRINT_SHIFT (4u) -#define INTC_ICDICPR12_X2HBSC_ERRINT_SHIFT (5u) -#define INTC_ICDICPR12_X2HSPI1_ERRINT_SHIFT (6u) -#define INTC_ICDICPR12_X2HSPI2_ERRINT_SHIFT (7u) -#define INTC_ICDICPR12_PRRI_SHIFT (8u) -#define INTC_ICDICPR12_IFEI0_SHIFT (9u) -#define INTC_ICDICPR12_OFFI0_SHIFT (10u) -#define INTC_ICDICPR12_PFVEI0_SHIFT (11u) -#define INTC_ICDICPR12_IFEI1_SHIFT (12u) -#define INTC_ICDICPR12_OFFI1_SHIFT (13u) -#define INTC_ICDICPR12_PFVEI1_SHIFT (14u) - -#define INTC_ICDICPR13_TINT0_SHIFT (0u) -#define INTC_ICDICPR13_TINT1_SHIFT (1u) -#define INTC_ICDICPR13_TINT2_SHIFT (2u) -#define INTC_ICDICPR13_TINT3_SHIFT (3u) -#define INTC_ICDICPR13_TINT4_SHIFT (4u) -#define INTC_ICDICPR13_TINT5_SHIFT (5u) -#define INTC_ICDICPR13_TINT6_SHIFT (6u) -#define INTC_ICDICPR13_TINT7_SHIFT (7u) -#define INTC_ICDICPR13_TINT8_SHIFT (8u) -#define INTC_ICDICPR13_TINT9_SHIFT (9u) -#define INTC_ICDICPR13_TINT10_SHIFT (10u) -#define INTC_ICDICPR13_TINT11_SHIFT (11u) -#define INTC_ICDICPR13_TINT12_SHIFT (12u) -#define INTC_ICDICPR13_TINT13_SHIFT (13u) -#define INTC_ICDICPR13_TINT14_SHIFT (14u) -#define INTC_ICDICPR13_TINT15_SHIFT (15u) -#define INTC_ICDICPR13_TINT16_SHIFT (16u) -#define INTC_ICDICPR13_TINT17_SHIFT (17u) -#define INTC_ICDICPR13_TINT18_SHIFT (18u) -#define INTC_ICDICPR13_TINT19_SHIFT (19u) -#define INTC_ICDICPR13_TINT20_SHIFT (20u) -#define INTC_ICDICPR13_TINT21_SHIFT (21u) -#define INTC_ICDICPR13_TINT22_SHIFT (22u) -#define INTC_ICDICPR13_TINT23_SHIFT (23u) -#define INTC_ICDICPR13_TINT24_SHIFT (24u) -#define INTC_ICDICPR13_TINT25_SHIFT (25u) -#define INTC_ICDICPR13_TINT26_SHIFT (26u) -#define INTC_ICDICPR13_TINT27_SHIFT (27u) -#define INTC_ICDICPR13_TINT28_SHIFT (28u) -#define INTC_ICDICPR13_TINT29_SHIFT (29u) -#define INTC_ICDICPR13_TINT30_SHIFT (30u) -#define INTC_ICDICPR13_TINT31_SHIFT (31u) - -#define INTC_ICDICPR14_TINT32_SHIFT (0u) -#define INTC_ICDICPR14_TINT33_SHIFT (1u) -#define INTC_ICDICPR14_TINT34_SHIFT (2u) -#define INTC_ICDICPR14_TINT35_SHIFT (3u) -#define INTC_ICDICPR14_TINT36_SHIFT (4u) -#define INTC_ICDICPR14_TINT37_SHIFT (5u) -#define INTC_ICDICPR14_TINT38_SHIFT (6u) -#define INTC_ICDICPR14_TINT39_SHIFT (7u) -#define INTC_ICDICPR14_TINT40_SHIFT (8u) -#define INTC_ICDICPR14_TINT41_SHIFT (9u) -#define INTC_ICDICPR14_TINT42_SHIFT (10u) -#define INTC_ICDICPR14_TINT43_SHIFT (11u) -#define INTC_ICDICPR14_TINT44_SHIFT (12u) -#define INTC_ICDICPR14_TINT45_SHIFT (13u) -#define INTC_ICDICPR14_TINT46_SHIFT (14u) -#define INTC_ICDICPR14_TINT47_SHIFT (15u) -#define INTC_ICDICPR14_TINT48_SHIFT (16u) -#define INTC_ICDICPR14_TINT49_SHIFT (17u) -#define INTC_ICDICPR14_TINT50_SHIFT (18u) -#define INTC_ICDICPR14_TINT51_SHIFT (19u) -#define INTC_ICDICPR14_TINT52_SHIFT (20u) -#define INTC_ICDICPR14_TINT53_SHIFT (21u) -#define INTC_ICDICPR14_TINT54_SHIFT (22u) -#define INTC_ICDICPR14_TINT55_SHIFT (23u) -#define INTC_ICDICPR14_TINT56_SHIFT (24u) -#define INTC_ICDICPR14_TINT57_SHIFT (25u) -#define INTC_ICDICPR14_TINT58_SHIFT (26u) -#define INTC_ICDICPR14_TINT59_SHIFT (27u) -#define INTC_ICDICPR14_TINT60_SHIFT (28u) -#define INTC_ICDICPR14_TINT61_SHIFT (29u) -#define INTC_ICDICPR14_TINT62_SHIFT (30u) -#define INTC_ICDICPR14_TINT63_SHIFT (31u) - -#define INTC_ICDICPR15_TINT64_SHIFT (0u) -#define INTC_ICDICPR15_TINT65_SHIFT (1u) -#define INTC_ICDICPR15_TINT66_SHIFT (2u) -#define INTC_ICDICPR15_TINT67_SHIFT (3u) -#define INTC_ICDICPR15_TINT68_SHIFT (4u) -#define INTC_ICDICPR15_TINT69_SHIFT (5u) -#define INTC_ICDICPR15_TINT70_SHIFT (6u) -#define INTC_ICDICPR15_TINT71_SHIFT (7u) -#define INTC_ICDICPR15_TINT72_SHIFT (8u) -#define INTC_ICDICPR15_TINT73_SHIFT (9u) -#define INTC_ICDICPR15_TINT74_SHIFT (10u) -#define INTC_ICDICPR15_TINT75_SHIFT (11u) -#define INTC_ICDICPR15_TINT76_SHIFT (12u) -#define INTC_ICDICPR15_TINT77_SHIFT (13u) -#define INTC_ICDICPR15_TINT78_SHIFT (14u) -#define INTC_ICDICPR15_TINT79_SHIFT (15u) -#define INTC_ICDICPR15_TINT80_SHIFT (16u) -#define INTC_ICDICPR15_TINT81_SHIFT (17u) -#define INTC_ICDICPR15_TINT82_SHIFT (18u) -#define INTC_ICDICPR15_TINT83_SHIFT (19u) -#define INTC_ICDICPR15_TINT84_SHIFT (20u) -#define INTC_ICDICPR15_TINT85_SHIFT (21u) -#define INTC_ICDICPR15_TINT86_SHIFT (22u) -#define INTC_ICDICPR15_TINT87_SHIFT (23u) -#define INTC_ICDICPR15_TINT88_SHIFT (24u) -#define INTC_ICDICPR15_TINT89_SHIFT (25u) -#define INTC_ICDICPR15_TINT90_SHIFT (26u) -#define INTC_ICDICPR15_TINT91_SHIFT (27u) -#define INTC_ICDICPR15_TINT92_SHIFT (28u) -#define INTC_ICDICPR15_TINT93_SHIFT (29u) -#define INTC_ICDICPR15_TINT94_SHIFT (30u) -#define INTC_ICDICPR15_TINT95_SHIFT (31u) - -#define INTC_ICDICPR16_TINT96_SHIFT (0u) -#define INTC_ICDICPR16_TINT97_SHIFT (1u) -#define INTC_ICDICPR16_TINT98_SHIFT (2u) -#define INTC_ICDICPR16_TINT99_SHIFT (3u) -#define INTC_ICDICPR16_TINT100_SHIFT (4u) -#define INTC_ICDICPR16_TINT101_SHIFT (5u) -#define INTC_ICDICPR16_TINT102_SHIFT (6u) -#define INTC_ICDICPR16_TINT103_SHIFT (7u) -#define INTC_ICDICPR16_TINT104_SHIFT (8u) -#define INTC_ICDICPR16_TINT105_SHIFT (9u) -#define INTC_ICDICPR16_TINT106_SHIFT (10u) -#define INTC_ICDICPR16_TINT107_SHIFT (11u) -#define INTC_ICDICPR16_TINT108_SHIFT (12u) -#define INTC_ICDICPR16_TINT109_SHIFT (13u) -#define INTC_ICDICPR16_TINT110_SHIFT (14u) -#define INTC_ICDICPR16_TINT111_SHIFT (15u) -#define INTC_ICDICPR16_TINT112_SHIFT (16u) -#define INTC_ICDICPR16_TINT113_SHIFT (17u) -#define INTC_ICDICPR16_TINT114_SHIFT (18u) -#define INTC_ICDICPR16_TINT115_SHIFT (19u) -#define INTC_ICDICPR16_TINT116_SHIFT (20u) -#define INTC_ICDICPR16_TINT117_SHIFT (21u) -#define INTC_ICDICPR16_TINT118_SHIFT (22u) -#define INTC_ICDICPR16_TINT119_SHIFT (23u) -#define INTC_ICDICPR16_TINT120_SHIFT (24u) -#define INTC_ICDICPR16_TINT121_SHIFT (25u) -#define INTC_ICDICPR16_TINT122_SHIFT (26u) -#define INTC_ICDICPR16_TINT123_SHIFT (27u) -#define INTC_ICDICPR16_TINT124_SHIFT (28u) -#define INTC_ICDICPR16_TINT125_SHIFT (29u) -#define INTC_ICDICPR16_TINT126_SHIFT (30u) -#define INTC_ICDICPR16_TINT127_SHIFT (31u) - -#define INTC_ICDICPR17_TINT128_SHIFT (0u) -#define INTC_ICDICPR17_TINT129_SHIFT (1u) -#define INTC_ICDICPR17_TINT130_SHIFT (2u) -#define INTC_ICDICPR17_TINT131_SHIFT (3u) -#define INTC_ICDICPR17_TINT132_SHIFT (4u) -#define INTC_ICDICPR17_TINT133_SHIFT (5u) -#define INTC_ICDICPR17_TINT134_SHIFT (6u) -#define INTC_ICDICPR17_TINT135_SHIFT (7u) -#define INTC_ICDICPR17_TINT136_SHIFT (8u) -#define INTC_ICDICPR17_TINT137_SHIFT (9u) -#define INTC_ICDICPR17_TINT138_SHIFT (10u) -#define INTC_ICDICPR17_TINT139_SHIFT (11u) -#define INTC_ICDICPR17_TINT140_SHIFT (12u) -#define INTC_ICDICPR17_TINT141_SHIFT (13u) -#define INTC_ICDICPR17_TINT142_SHIFT (14u) -#define INTC_ICDICPR17_TINT143_SHIFT (15u) -#define INTC_ICDICPR17_TINT144_SHIFT (16u) -#define INTC_ICDICPR17_TINT145_SHIFT (17u) -#define INTC_ICDICPR17_TINT146_SHIFT (18u) -#define INTC_ICDICPR17_TINT147_SHIFT (19u) -#define INTC_ICDICPR17_TINT148_SHIFT (20u) -#define INTC_ICDICPR17_TINT149_SHIFT (21u) -#define INTC_ICDICPR17_TINT150_SHIFT (22u) -#define INTC_ICDICPR17_TINT151_SHIFT (23u) -#define INTC_ICDICPR17_TINT152_SHIFT (24u) -#define INTC_ICDICPR17_TINT153_SHIFT (25u) -#define INTC_ICDICPR17_TINT154_SHIFT (26u) -#define INTC_ICDICPR17_TINT155_SHIFT (27u) -#define INTC_ICDICPR17_TINT156_SHIFT (28u) -#define INTC_ICDICPR17_TINT157_SHIFT (29u) -#define INTC_ICDICPR17_TINT158_SHIFT (30u) -#define INTC_ICDICPR17_TINT159_SHIFT (31u) - -#define INTC_ICDICPR18_TINT160_SHIFT (0u) -#define INTC_ICDICPR18_TINT161_SHIFT (1u) -#define INTC_ICDICPR18_TINT162_SHIFT (2u) -#define INTC_ICDICPR18_TINT163_SHIFT (3u) -#define INTC_ICDICPR18_TINT164_SHIFT (4u) -#define INTC_ICDICPR18_TINT165_SHIFT (5u) -#define INTC_ICDICPR18_TINT166_SHIFT (6u) -#define INTC_ICDICPR18_TINT167_SHIFT (7u) -#define INTC_ICDICPR18_TINT168_SHIFT (8u) -#define INTC_ICDICPR18_TINT169_SHIFT (9u) -#define INTC_ICDICPR18_TINT170_SHIFT (10u) - -#define INTC_ICDABR0_SW0_SHIFT (0u) -#define INTC_ICDABR0_SW1_SHIFT (1u) -#define INTC_ICDABR0_SW2_SHIFT (2u) -#define INTC_ICDABR0_SW3_SHIFT (3u) -#define INTC_ICDABR0_SW4_SHIFT (4u) -#define INTC_ICDABR0_SW5_SHIFT (5u) -#define INTC_ICDABR0_SW6_SHIFT (6u) -#define INTC_ICDABR0_SW7_SHIFT (7u) -#define INTC_ICDABR0_SW8_SHIFT (8u) -#define INTC_ICDABR0_SW9_SHIFT (9u) -#define INTC_ICDABR0_SW10_SHIFT (10u) -#define INTC_ICDABR0_SW11_SHIFT (11u) -#define INTC_ICDABR0_SW12_SHIFT (12u) -#define INTC_ICDABR0_SW13_SHIFT (13u) -#define INTC_ICDABR0_SW14_SHIFT (14u) -#define INTC_ICDABR0_SW15_SHIFT (15u) -#define INTC_ICDABR0_PMUIRQ0_SHIFT (16u) -#define INTC_ICDABR0_COMMRX0_SHIFT (17u) -#define INTC_ICDABR0_COMMTX0_SHIFT (18u) -#define INTC_ICDABR0_CTIIRQ0_SHIFT (19u) - -#define INTC_ICDABR1_IRQ0_SHIFT (0u) -#define INTC_ICDABR1_IRQ1_SHIFT (1u) -#define INTC_ICDABR1_IRQ2_SHIFT (2u) -#define INTC_ICDABR1_IRQ3_SHIFT (3u) -#define INTC_ICDABR1_IRQ4_SHIFT (4u) -#define INTC_ICDABR1_IRQ5_SHIFT (5u) -#define INTC_ICDABR1_IRQ6_SHIFT (6u) -#define INTC_ICDABR1_IRQ7_SHIFT (7u) -#define INTC_ICDABR1_PL310ERR_SHIFT (8u) -#define INTC_ICDABR1_DMAINT0_SHIFT (9u) -#define INTC_ICDABR1_DMAINT1_SHIFT (10u) -#define INTC_ICDABR1_DMAINT2_SHIFT (11u) -#define INTC_ICDABR1_DMAINT3_SHIFT (12u) -#define INTC_ICDABR1_DMAINT4_SHIFT (13u) -#define INTC_ICDABR1_DMAINT5_SHIFT (14u) -#define INTC_ICDABR1_DMAINT6_SHIFT (15u) -#define INTC_ICDABR1_DMAINT7_SHIFT (16u) -#define INTC_ICDABR1_DMAINT8_SHIFT (17u) -#define INTC_ICDABR1_DMAINT9_SHIFT (18u) -#define INTC_ICDABR1_DMAINT10_SHIFT (19u) -#define INTC_ICDABR1_DMAINT11_SHIFT (20u) -#define INTC_ICDABR1_DMAINT12_SHIFT (21u) -#define INTC_ICDABR1_DMAINT13_SHIFT (22u) -#define INTC_ICDABR1_DMAINT14_SHIFT (23u) -#define INTC_ICDABR1_DMAINT15_SHIFT (24u) -#define INTC_ICDABR1_DMAERR_SHIFT (25u) - -#define INTC_ICDABR2_USBI0_SHIFT (9u) -#define INTC_ICDABR2_USBI1_SHIFT (10u) -#define INTC_ICDABR2_S0_VI_VSYNC0_SHIFT (11u) -#define INTC_ICDABR2_S0_LO_VSYNC0_SHIFT (12u) -#define INTC_ICDABR2_S0_VSYNCERR0_SHIFT (13u) -#define INTC_ICDABR2_GR3_VLINE0_SHIFT (14u) -#define INTC_ICDABR2_S0_VFIELD0_SHIFT (15u) -#define INTC_ICDABR2_IV1_VBUFERR0_SHIFT (16u) -#define INTC_ICDABR2_IV3_VBUFERR0_SHIFT (17u) -#define INTC_ICDABR2_IV5_VBUFERR0_SHIFT (18u) -#define INTC_ICDABR2_IV6_VBUFERR0_SHIFT (19u) -#define INTC_ICDABR2_S0_WLINE0_SHIFT (20u) -#define INTC_ICDABR2_S1_VI_VSYNC0_SHIFT (21u) -#define INTC_ICDABR2_S1_LO_VSYNC0_SHIFT (22u) -#define INTC_ICDABR2_S1_VSYNCERR0_SHIFT (23u) -#define INTC_ICDABR2_S1_VFIELD0_SHIFT (24u) -#define INTC_ICDABR2_IV2_VBUFERR0_SHIFT (25u) -#define INTC_ICDABR2_IV4_VBUFERR0_SHIFT (26u) -#define INTC_ICDABR2_S1_WLINE0_SHIFT (27u) -#define INTC_ICDABR2_OIR_VI_VSYNC0_SHIFT (28u) -#define INTC_ICDABR2_OIR_LO_VSYNC0_SHIFT (29u) -#define INTC_ICDABR2_OIR_VSYNCERR0_SHIFT (30u) -#define INTC_ICDABR2_OIR_VFIELD0_SHIFT (31u) - -#define INTC_ICDABR3_IV7_VBUFERR0_SHIFT (0u) -#define INTC_ICDABR3_IV8_VBUFERR0_SHIFT (1u) -#define INTC_ICDABR3_S0_VI_VSYNC1_SHIFT (3u) -#define INTC_ICDABR3_S0_LO_VSYNC1_SHIFT (4u) -#define INTC_ICDABR3_S0_VSYNCERR1_SHIFT (5u) -#define INTC_ICDABR3_GR3_VLINE1_SHIFT (6u) -#define INTC_ICDABR3_S0_VFIELD1_SHIFT (7u) -#define INTC_ICDABR3_IV1_VBUFERR1_SHIFT (8u) -#define INTC_ICDABR3_IV3_VBUFERR1_SHIFT (9u) -#define INTC_ICDABR3_IV5_VBUFERR1_SHIFT (10u) -#define INTC_ICDABR3_IV6_VBUFERR1_SHIFT (11u) -#define INTC_ICDABR3_S0_WLINE1_SHIFT (12u) -#define INTC_ICDABR3_S1_VI_VSYNC1_SHIFT (13u) -#define INTC_ICDABR3_S1_LO_VSYNC1_SHIFT (14u) -#define INTC_ICDABR3_S1_VSYNCERR1_SHIFT (15u) -#define INTC_ICDABR3_S1_VFIELD1_SHIFT (16u) -#define INTC_ICDABR3_IV2_VBUFERR1_SHIFT (17u) -#define INTC_ICDABR3_IV4_VBUFERR1_SHIFT (18u) -#define INTC_ICDABR3_S1_WLINE1_SHIFT (19u) -#define INTC_ICDABR3_OIR_VI_VSYNC1_SHIFT (20u) -#define INTC_ICDABR3_OIR_LO_VSYNC1_SHIFT (21u) -#define INTC_ICDABR3_OIR_VLINE1_SHIFT (22u) -#define INTC_ICDABR3_OIR_VFIELD1_SHIFT (23u) -#define INTC_ICDABR3_IV7_VBUFERR1_SHIFT (24u) -#define INTC_ICDABR3_IV8_VBUFERR1_SHIFT (25u) -#define INTC_ICDABR3_IMRDI_SHIFT (27u) -#define INTC_ICDABR3_IMR2I0_SHIFT (28u) -#define INTC_ICDABR3_IMR2I1_SHIFT (29u) -#define INTC_ICDABR3_JEDI_SHIFT (30u) -#define INTC_ICDABR3_JDTI_SHIFT (31u) - -#define INTC_ICDABR4_CMP0_SHIFT (0u) -#define INTC_ICDABR4_CMP1_SHIFT (1u) -#define INTC_ICDABR4_INT0_SHIFT (2u) -#define INTC_ICDABR4_INT1_SHIFT (3u) -#define INTC_ICDABR4_INT2_SHIFT (4u) -#define INTC_ICDABR4_INT3_SHIFT (5u) -#define INTC_ICDABR4_OSTM0TINT_SHIFT (6u) -#define INTC_ICDABR4_OSTM1TINT_SHIFT (7u) -#define INTC_ICDABR4_CMI_SHIFT (8u) -#define INTC_ICDABR4_WTOUT_SHIFT (9u) -#define INTC_ICDABR4_ITI_SHIFT (10u) -#define INTC_ICDABR4_TGI0A_SHIFT (11u) -#define INTC_ICDABR4_TGI0B_SHIFT (12u) -#define INTC_ICDABR4_TGI0C_SHIFT (13u) -#define INTC_ICDABR4_TGI0D_SHIFT (14u) -#define INTC_ICDABR4_TGI0V_SHIFT (15u) -#define INTC_ICDABR4_TGI0E_SHIFT (16u) -#define INTC_ICDABR4_TGI0F_SHIFT (17u) -#define INTC_ICDABR4_TGI1A_SHIFT (18u) -#define INTC_ICDABR4_TGI1B_SHIFT (19u) -#define INTC_ICDABR4_TGI1V_SHIFT (20u) -#define INTC_ICDABR4_TGI1U_SHIFT (21u) -#define INTC_ICDABR4_TGI2A_SHIFT (22u) -#define INTC_ICDABR4_TGI2B_SHIFT (23u) -#define INTC_ICDABR4_TGI2V_SHIFT (24u) -#define INTC_ICDABR4_TGI2U_SHIFT (25u) -#define INTC_ICDABR4_TGI3A_SHIFT (26u) -#define INTC_ICDABR4_TGI3B_SHIFT (27u) -#define INTC_ICDABR4_TGI3C_SHIFT (28u) -#define INTC_ICDABR4_TGI3D_SHIFT (29u) -#define INTC_ICDABR4_TGI3V_SHIFT (30u) -#define INTC_ICDABR4_TGI4A_SHIFT (31u) - -#define INTC_ICDABR5_TGI4B_SHIFT (0u) -#define INTC_ICDABR5_TGI4C_SHIFT (1u) -#define INTC_ICDABR5_TGI4D_SHIFT (2u) -#define INTC_ICDABR5_TGI4V_SHIFT (3u) -#define INTC_ICDABR5_CMI1_SHIFT (4u) -#define INTC_ICDABR5_CMI2_SHIFT (5u) -#define INTC_ICDABR5_SGDEI0_SHIFT (6u) -#define INTC_ICDABR5_SGDEI1_SHIFT (7u) -#define INTC_ICDABR5_SGDEI2_SHIFT (8u) -#define INTC_ICDABR5_SGDEI3_SHIFT (9u) -#define INTC_ICDABR5_ADI_SHIFT (10u) -#define INTC_ICDABR5_LMTI_SHIFT (11u) -#define INTC_ICDABR5_SSII0_SHIFT (12u) -#define INTC_ICDABR5_SSIRXI0_SHIFT (13u) -#define INTC_ICDABR5_SSITXI0_SHIFT (14u) -#define INTC_ICDABR5_SSII1_SHIFT (15u) -#define INTC_ICDABR5_SSIRXI1_SHIFT (16u) -#define INTC_ICDABR5_SSITXI1_SHIFT (17u) -#define INTC_ICDABR5_SSII2_SHIFT (18u) -#define INTC_ICDABR5_SSIRTI2_SHIFT (19u) -#define INTC_ICDABR5_SSII3_SHIFT (20u) -#define INTC_ICDABR5_SSIRXI3_SHIFT (21u) -#define INTC_ICDABR5_SSITXI3_SHIFT (22u) -#define INTC_ICDABR5_SSII4_SHIFT (23u) -#define INTC_ICDABR5_SSIRTI4_SHIFT (24u) -#define INTC_ICDABR5_SSII5_SHIFT (25u) -#define INTC_ICDABR5_SSIRXI5_SHIFT (26u) -#define INTC_ICDABR5_SSITXI5_SHIFT (27u) -#define INTC_ICDABR5_SPDIFI_SHIFT (28u) -#define INTC_ICDABR5_INTIICTEI0_SHIFT (29u) -#define INTC_ICDABR5_INTIICRI0_SHIFT (30u) -#define INTC_ICDABR5_INTIICTI0_SHIFT (31u) - -#define INTC_ICDABR6_INTIICSPI0_SHIFT (0u) -#define INTC_ICDABR6_INTIICSTI0_SHIFT (1u) -#define INTC_ICDABR6_INTIICNAKI0_SHIFT (2u) -#define INTC_ICDABR6_INTIICALI0_SHIFT (3u) -#define INTC_ICDABR6_INTIICTMOI0_SHIFT (4u) -#define INTC_ICDABR6_INTIICTEI1_SHIFT (5u) -#define INTC_ICDABR6_INTIICRI1_SHIFT (6u) -#define INTC_ICDABR6_INTIICTI1_SHIFT (7u) -#define INTC_ICDABR6_INTIICSPI1_SHIFT (8u) -#define INTC_ICDABR6_INTIICSTI1_SHIFT (9u) -#define INTC_ICDABR6_INTIICNAKI1_SHIFT (10u) -#define INTC_ICDABR6_INTIICALI1_SHIFT (11u) -#define INTC_ICDABR6_INTIICTMOI1_SHIFT (12u) -#define INTC_ICDABR6_INTIICTEI2_SHIFT (13u) -#define INTC_ICDABR6_INTIICRI2_SHIFT (14u) -#define INTC_ICDABR6_INTIICTI2_SHIFT (15u) -#define INTC_ICDABR6_INTIICSPI2_SHIFT (16u) -#define INTC_ICDABR6_INTIICSTI2_SHIFT (17u) -#define INTC_ICDABR6_INTIICNAKI2_SHIFT (18u) -#define INTC_ICDABR6_INTIICALI2_SHIFT (19u) -#define INTC_ICDABR6_INTIICTMOI2_SHIFT (20u) -#define INTC_ICDABR6_INTIICTEI3_SHIFT (21u) -#define INTC_ICDABR6_INTIICRI3_SHIFT (22u) -#define INTC_ICDABR6_INTIICTI3_SHIFT (23u) -#define INTC_ICDABR6_INTIICSPI3_SHIFT (24u) -#define INTC_ICDABR6_INTIICSTI3_SHIFT (25u) -#define INTC_ICDABR6_INTIICNAKI3_SHIFT (26u) -#define INTC_ICDABR6_INTIICALI3_SHIFT (27u) -#define INTC_ICDABR6_INTIICTMOI3_SHIFT (28u) -#define INTC_ICDABR6_BRI0_SHIFT (29u) -#define INTC_ICDABR6_ERI0_SHIFT (30u) -#define INTC_ICDABR6_RXI0_SHIFT (31u) - -#define INTC_ICDABR7_TXI0_SHIFT (0u) -#define INTC_ICDABR7_BRI1_SHIFT (1u) -#define INTC_ICDABR7_ERI1_SHIFT (2u) -#define INTC_ICDABR7_RXI1_SHIFT (3u) -#define INTC_ICDABR7_TXI1_SHIFT (4u) -#define INTC_ICDABR7_BRI2_SHIFT (5u) -#define INTC_ICDABR7_ERI2_SHIFT (6u) -#define INTC_ICDABR7_RXI2_SHIFT (7u) -#define INTC_ICDABR7_TXI2_SHIFT (8u) -#define INTC_ICDABR7_BRI3_SHIFT (9u) -#define INTC_ICDABR7_ERI3_SHIFT (10u) -#define INTC_ICDABR7_RXI3_SHIFT (11u) -#define INTC_ICDABR7_TXI3_SHIFT (12u) -#define INTC_ICDABR7_BRI4_SHIFT (13u) -#define INTC_ICDABR7_ERI4_SHIFT (14u) -#define INTC_ICDABR7_RXI4_SHIFT (15u) -#define INTC_ICDABR7_TXI4_SHIFT (16u) -#define INTC_ICDABR7_BRI5_SHIFT (17u) -#define INTC_ICDABR7_ERI5_SHIFT (18u) -#define INTC_ICDABR7_RXI5_SHIFT (19u) -#define INTC_ICDABR7_TXI5_SHIFT (20u) -#define INTC_ICDABR7_BRI6_SHIFT (21u) -#define INTC_ICDABR7_ERI6_SHIFT (22u) -#define INTC_ICDABR7_RXI6_SHIFT (23u) -#define INTC_ICDABR7_TXI6_SHIFT (24u) -#define INTC_ICDABR7_BRI7_SHIFT (25u) -#define INTC_ICDABR7_ERI7_SHIFT (26u) -#define INTC_ICDABR7_RXI7_SHIFT (27u) -#define INTC_ICDABR7_TXI7_SHIFT (28u) -#define INTC_ICDABR7_INTRCANGERR_SHIFT (29u) -#define INTC_ICDABR7_INTRCANGRECC_SHIFT (30u) -#define INTC_ICDABR7_INTRCAN0REC_SHIFT (31u) - -#define INTC_ICDABR8_INTRCAN0ERR_SHIFT (0u) -#define INTC_ICDABR8_INTRCAN0TRX_SHIFT (1u) -#define INTC_ICDABR8_INTRCAN1REC_SHIFT (2u) -#define INTC_ICDABR8_INTRCAN1ERR_SHIFT (3u) -#define INTC_ICDABR8_INTRCAN1TRX_SHIFT (4u) -#define INTC_ICDABR8_INTRCAN2REC_SHIFT (5u) -#define INTC_ICDABR8_INTRCAN2ERR_SHIFT (6u) -#define INTC_ICDABR8_INTRCAN2TRX_SHIFT (7u) -#define INTC_ICDABR8_INTRCAN3REC_SHIFT (8u) -#define INTC_ICDABR8_INTRCAN3ERR_SHIFT (9u) -#define INTC_ICDABR8_INTRCAN3TRX_SHIFT (10u) -#define INTC_ICDABR8_INTRCAN4REC_SHIFT (11u) -#define INTC_ICDABR8_INTRCAN4ERR_SHIFT (12u) -#define INTC_ICDABR8_INTRCAN4TRX_SHIFT (13u) -#define INTC_ICDABR8_SPEI0_SHIFT (14u) -#define INTC_ICDABR8_SPRI0_SHIFT (15u) -#define INTC_ICDABR8_SPTI0_SHIFT (16u) -#define INTC_ICDABR8_SPEI1_SHIFT (17u) -#define INTC_ICDABR8_SPRI1_SHIFT (18u) -#define INTC_ICDABR8_SPTI1_SHIFT (19u) -#define INTC_ICDABR8_SPEI2_SHIFT (20u) -#define INTC_ICDABR8_SPRI2_SHIFT (21u) -#define INTC_ICDABR8_SPTI2_SHIFT (22u) -#define INTC_ICDABR8_SPEI3_SHIFT (23u) -#define INTC_ICDABR8_SPRI3_SHIFT (24u) -#define INTC_ICDABR8_SPTI3_SHIFT (25u) -#define INTC_ICDABR8_SPEI4_SHIFT (26u) -#define INTC_ICDABR8_SPRI4_SHIFT (27u) -#define INTC_ICDABR8_SPTI4_SHIFT (28u) -#define INTC_ICDABR8_IEBBTD_SHIFT (29u) -#define INTC_ICDABR8_IEBBTERR_SHIFT (30u) -#define INTC_ICDABR8_IEBBTSTA_SHIFT (31u) - -#define INTC_ICDABR9_IEBBTV_SHIFT (0u) -#define INTC_ICDABR9_ISY_SHIFT (1u) -#define INTC_ICDABR9_IERR_SHIFT (2u) -#define INTC_ICDABR9_ITARG_SHIFT (3u) -#define INTC_ICDABR9_ISEC_SHIFT (4u) -#define INTC_ICDABR9_IBUF_SHIFT (5u) -#define INTC_ICDABR9_IREADY_SHIFT (6u) -#define INTC_ICDABR9_FLSTE_SHIFT (7u) -#define INTC_ICDABR9_FLTENDI_SHIFT (8u) -#define INTC_ICDABR9_FLTREQ0I_SHIFT (9u) -#define INTC_ICDABR9_FLTREQ1I_SHIFT (10u) -#define INTC_ICDABR9_MMC0_SHIFT (11u) -#define INTC_ICDABR9_MMC1_SHIFT (12u) -#define INTC_ICDABR9_MMC2_SHIFT (13u) -#define INTC_ICDABR9_SDHI0_3_SHIFT (14u) -#define INTC_ICDABR9_SDHI0_0_SHIFT (15u) -#define INTC_ICDABR9_SDHI0_1_SHIFT (16u) -#define INTC_ICDABR9_SDHI1_3_SHIFT (17u) -#define INTC_ICDABR9_SDHI1_0_SHIFT (18u) -#define INTC_ICDABR9_SDHI1_1_SHIFT (19u) -#define INTC_ICDABR9_ARM_SHIFT (20u) -#define INTC_ICDABR9_PRD_SHIFT (21u) -#define INTC_ICDABR9_CUP_SHIFT (22u) -#define INTC_ICDABR9_SCUAI0_SHIFT (23u) -#define INTC_ICDABR9_SCUAI1_SHIFT (24u) -#define INTC_ICDABR9_SCUFDI0_SHIFT (25u) -#define INTC_ICDABR9_SCUFDI1_SHIFT (26u) -#define INTC_ICDABR9_SCUFDI2_SHIFT (27u) -#define INTC_ICDABR9_SCUFDI3_SHIFT (28u) -#define INTC_ICDABR9_SCUFUI0_SHIFT (29u) -#define INTC_ICDABR9_SCUFUI1_SHIFT (30u) -#define INTC_ICDABR9_SCUFUI2_SHIFT (31u) - -#define INTC_ICDABR10_SCUFUI3_SHIFT (0u) -#define INTC_ICDABR10_SCUDVI0_SHIFT (1u) -#define INTC_ICDABR10_SCUDVI1_SHIFT (2u) -#define INTC_ICDABR10_SCUDVI2_SHIFT (3u) -#define INTC_ICDABR10_SCUDVI3_SHIFT (4u) -#define INTC_ICDABR10_MLB_CINT_SHIFT (5u) -#define INTC_ICDABR10_MLB_SINT_SHIFT (6u) -#define INTC_ICDABR10_DRC0_SHIFT (7u) -#define INTC_ICDABR10_DRC1_SHIFT (8u) -#define INTC_ICDABR10_LINI0_INT_T_SHIFT (11u) -#define INTC_ICDABR10_LINI0_INT_R_SHIFT (12u) -#define INTC_ICDABR10_LINI0_INT_S_SHIFT (13u) -#define INTC_ICDABR10_LINI0_INT_M_SHIFT (14u) -#define INTC_ICDABR10_LINI1_INT_T_SHIFT (15u) -#define INTC_ICDABR10_LINI1_INT_R_SHIFT (16u) -#define INTC_ICDABR10_LINI1_INT_S_SHIFT (17u) -#define INTC_ICDABR10_LINI1_INT_M_SHIFT (18u) -#define INTC_ICDABR10_ERI0_SHIFT (27u) -#define INTC_ICDABR10_RXI0_SHIFT (28u) -#define INTC_ICDABR10_TXI0_SHIFT (29u) -#define INTC_ICDABR10_TEI0_SHIFT (30u) -#define INTC_ICDABR10_ERI1_SHIFT (31u) - -#define INTC_ICDABR11_RXI1_SHIFT (0u) -#define INTC_ICDABR11_TXI1_SHIFT (1u) -#define INTC_ICDABR11_TEI1_SHIFT (2u) -#define INTC_ICDABR11_AVBI_DATA_SHIFT (3u) -#define INTC_ICDABR11_AVBI_ERROR_SHIFT (4u) -#define INTC_ICDABR11_AVBI_MANAGE_SHIFT (5u) -#define INTC_ICDABR11_AVBI_MAC_SHIFT (6u) -#define INTC_ICDABR11_ETHERI_SHIFT (7u) -#define INTC_ICDABR11_CEUI_SHIFT (12u) -#define INTC_ICDABR11_H2XMLB_ERRINT_SHIFT (29u) -#define INTC_ICDABR11_H2XIC1_ERRINT_SHIFT (30u) -#define INTC_ICDABR11_X2HPERI1_ERRINT_SHIFT (31u) - -#define INTC_ICDABR12_X2HPERI2_ERRINT_SHIFT (0u) -#define INTC_ICDABR12_X2HPERI34_ERRINT_SHIFT (1u) -#define INTC_ICDABR12_X2HPERI5_ERRINT_SHIFT (2u) -#define INTC_ICDABR12_X2HPERI67_ERRINT_SHIFT (3u) -#define INTC_ICDABR12_X2HDBGR_ERRINT_SHIFT (4u) -#define INTC_ICDABR12_X2HBSC_ERRINT_SHIFT (5u) -#define INTC_ICDABR12_X2HSPI1_ERRINT_SHIFT (6u) -#define INTC_ICDABR12_X2HSPI2_ERRINT_SHIFT (7u) -#define INTC_ICDABR12_PRRI_SHIFT (8u) -#define INTC_ICDABR12_IFEI0_SHIFT (9u) -#define INTC_ICDABR12_OFFI0_SHIFT (10u) -#define INTC_ICDABR12_PFVEI0_SHIFT (11u) -#define INTC_ICDABR12_IFEI1_SHIFT (12u) -#define INTC_ICDABR12_OFFI1_SHIFT (13u) -#define INTC_ICDABR12_PFVEI1_SHIFT (14u) - -#define INTC_ICDABR13_TINT0_SHIFT (0u) -#define INTC_ICDABR13_TINT1_SHIFT (1u) -#define INTC_ICDABR13_TINT2_SHIFT (2u) -#define INTC_ICDABR13_TINT3_SHIFT (3u) -#define INTC_ICDABR13_TINT4_SHIFT (4u) -#define INTC_ICDABR13_TINT5_SHIFT (5u) -#define INTC_ICDABR13_TINT6_SHIFT (6u) -#define INTC_ICDABR13_TINT7_SHIFT (7u) -#define INTC_ICDABR13_TINT8_SHIFT (8u) -#define INTC_ICDABR13_TINT9_SHIFT (9u) -#define INTC_ICDABR13_TINT10_SHIFT (10u) -#define INTC_ICDABR13_TINT11_SHIFT (11u) -#define INTC_ICDABR13_TINT12_SHIFT (12u) -#define INTC_ICDABR13_TINT13_SHIFT (13u) -#define INTC_ICDABR13_TINT14_SHIFT (14u) -#define INTC_ICDABR13_TINT15_SHIFT (15u) -#define INTC_ICDABR13_TINT16_SHIFT (16u) -#define INTC_ICDABR13_TINT17_SHIFT (17u) -#define INTC_ICDABR13_TINT18_SHIFT (18u) -#define INTC_ICDABR13_TINT19_SHIFT (19u) -#define INTC_ICDABR13_TINT20_SHIFT (20u) -#define INTC_ICDABR13_TINT21_SHIFT (21u) -#define INTC_ICDABR13_TINT22_SHIFT (22u) -#define INTC_ICDABR13_TINT23_SHIFT (23u) -#define INTC_ICDABR13_TINT24_SHIFT (24u) -#define INTC_ICDABR13_TINT25_SHIFT (25u) -#define INTC_ICDABR13_TINT26_SHIFT (26u) -#define INTC_ICDABR13_TINT27_SHIFT (27u) -#define INTC_ICDABR13_TINT28_SHIFT (28u) -#define INTC_ICDABR13_TINT29_SHIFT (29u) -#define INTC_ICDABR13_TINT30_SHIFT (30u) -#define INTC_ICDABR13_TINT31_SHIFT (31u) - -#define INTC_ICDABR14_TINT32_SHIFT (0u) -#define INTC_ICDABR14_TINT33_SHIFT (1u) -#define INTC_ICDABR14_TINT34_SHIFT (2u) -#define INTC_ICDABR14_TINT35_SHIFT (3u) -#define INTC_ICDABR14_TINT36_SHIFT (4u) -#define INTC_ICDABR14_TINT37_SHIFT (5u) -#define INTC_ICDABR14_TINT38_SHIFT (6u) -#define INTC_ICDABR14_TINT39_SHIFT (7u) -#define INTC_ICDABR14_TINT40_SHIFT (8u) -#define INTC_ICDABR14_TINT41_SHIFT (9u) -#define INTC_ICDABR14_TINT42_SHIFT (10u) -#define INTC_ICDABR14_TINT43_SHIFT (11u) -#define INTC_ICDABR14_TINT44_SHIFT (12u) -#define INTC_ICDABR14_TINT45_SHIFT (13u) -#define INTC_ICDABR14_TINT46_SHIFT (14u) -#define INTC_ICDABR14_TINT47_SHIFT (15u) -#define INTC_ICDABR14_TINT48_SHIFT (16u) -#define INTC_ICDABR14_TINT49_SHIFT (17u) -#define INTC_ICDABR14_TINT50_SHIFT (18u) -#define INTC_ICDABR14_TINT51_SHIFT (19u) -#define INTC_ICDABR14_TINT52_SHIFT (20u) -#define INTC_ICDABR14_TINT53_SHIFT (21u) -#define INTC_ICDABR14_TINT54_SHIFT (22u) -#define INTC_ICDABR14_TINT55_SHIFT (23u) -#define INTC_ICDABR14_TINT56_SHIFT (24u) -#define INTC_ICDABR14_TINT57_SHIFT (25u) -#define INTC_ICDABR14_TINT58_SHIFT (26u) -#define INTC_ICDABR14_TINT59_SHIFT (27u) -#define INTC_ICDABR14_TINT60_SHIFT (28u) -#define INTC_ICDABR14_TINT61_SHIFT (29u) -#define INTC_ICDABR14_TINT62_SHIFT (30u) -#define INTC_ICDABR14_TINT63_SHIFT (31u) - -#define INTC_ICDABR15_TINT64_SHIFT (0u) -#define INTC_ICDABR15_TINT65_SHIFT (1u) -#define INTC_ICDABR15_TINT66_SHIFT (2u) -#define INTC_ICDABR15_TINT67_SHIFT (3u) -#define INTC_ICDABR15_TINT68_SHIFT (4u) -#define INTC_ICDABR15_TINT69_SHIFT (5u) -#define INTC_ICDABR15_TINT70_SHIFT (6u) -#define INTC_ICDABR15_TINT71_SHIFT (7u) -#define INTC_ICDABR15_TINT72_SHIFT (8u) -#define INTC_ICDABR15_TINT73_SHIFT (9u) -#define INTC_ICDABR15_TINT74_SHIFT (10u) -#define INTC_ICDABR15_TINT75_SHIFT (11u) -#define INTC_ICDABR15_TINT76_SHIFT (12u) -#define INTC_ICDABR15_TINT77_SHIFT (13u) -#define INTC_ICDABR15_TINT78_SHIFT (14u) -#define INTC_ICDABR15_TINT79_SHIFT (15u) -#define INTC_ICDABR15_TINT80_SHIFT (16u) -#define INTC_ICDABR15_TINT81_SHIFT (17u) -#define INTC_ICDABR15_TINT82_SHIFT (18u) -#define INTC_ICDABR15_TINT83_SHIFT (19u) -#define INTC_ICDABR15_TINT84_SHIFT (20u) -#define INTC_ICDABR15_TINT85_SHIFT (21u) -#define INTC_ICDABR15_TINT86_SHIFT (22u) -#define INTC_ICDABR15_TINT87_SHIFT (23u) -#define INTC_ICDABR15_TINT88_SHIFT (24u) -#define INTC_ICDABR15_TINT89_SHIFT (25u) -#define INTC_ICDABR15_TINT90_SHIFT (26u) -#define INTC_ICDABR15_TINT91_SHIFT (27u) -#define INTC_ICDABR15_TINT92_SHIFT (28u) -#define INTC_ICDABR15_TINT93_SHIFT (29u) -#define INTC_ICDABR15_TINT94_SHIFT (30u) -#define INTC_ICDABR15_TINT95_SHIFT (31u) - -#define INTC_ICDABR16_TINT96_SHIFT (0u) -#define INTC_ICDABR16_TINT97_SHIFT (1u) -#define INTC_ICDABR16_TINT98_SHIFT (2u) -#define INTC_ICDABR16_TINT99_SHIFT (3u) -#define INTC_ICDABR16_TINT100_SHIFT (4u) -#define INTC_ICDABR16_TINT101_SHIFT (5u) -#define INTC_ICDABR16_TINT102_SHIFT (6u) -#define INTC_ICDABR16_TINT103_SHIFT (7u) -#define INTC_ICDABR16_TINT104_SHIFT (8u) -#define INTC_ICDABR16_TINT105_SHIFT (9u) -#define INTC_ICDABR16_TINT106_SHIFT (10u) -#define INTC_ICDABR16_TINT107_SHIFT (11u) -#define INTC_ICDABR16_TINT108_SHIFT (12u) -#define INTC_ICDABR16_TINT109_SHIFT (13u) -#define INTC_ICDABR16_TINT110_SHIFT (14u) -#define INTC_ICDABR16_TINT111_SHIFT (15u) -#define INTC_ICDABR16_TINT112_SHIFT (16u) -#define INTC_ICDABR16_TINT113_SHIFT (17u) -#define INTC_ICDABR16_TINT114_SHIFT (18u) -#define INTC_ICDABR16_TINT115_SHIFT (19u) -#define INTC_ICDABR16_TINT116_SHIFT (20u) -#define INTC_ICDABR16_TINT117_SHIFT (21u) -#define INTC_ICDABR16_TINT118_SHIFT (22u) -#define INTC_ICDABR16_TINT119_SHIFT (23u) -#define INTC_ICDABR16_TINT120_SHIFT (24u) -#define INTC_ICDABR16_TINT121_SHIFT (25u) -#define INTC_ICDABR16_TINT122_SHIFT (26u) -#define INTC_ICDABR16_TINT123_SHIFT (27u) -#define INTC_ICDABR16_TINT124_SHIFT (28u) -#define INTC_ICDABR16_TINT125_SHIFT (29u) -#define INTC_ICDABR16_TINT126_SHIFT (30u) -#define INTC_ICDABR16_TINT127_SHIFT (31u) - -#define INTC_ICDABR17_TINT128_SHIFT (0u) -#define INTC_ICDABR17_TINT129_SHIFT (1u) -#define INTC_ICDABR17_TINT130_SHIFT (2u) -#define INTC_ICDABR17_TINT131_SHIFT (3u) -#define INTC_ICDABR17_TINT132_SHIFT (4u) -#define INTC_ICDABR17_TINT133_SHIFT (5u) -#define INTC_ICDABR17_TINT134_SHIFT (6u) -#define INTC_ICDABR17_TINT135_SHIFT (7u) -#define INTC_ICDABR17_TINT136_SHIFT (8u) -#define INTC_ICDABR17_TINT137_SHIFT (9u) -#define INTC_ICDABR17_TINT138_SHIFT (10u) -#define INTC_ICDABR17_TINT139_SHIFT (11u) -#define INTC_ICDABR17_TINT140_SHIFT (12u) -#define INTC_ICDABR17_TINT141_SHIFT (13u) -#define INTC_ICDABR17_TINT142_SHIFT (14u) -#define INTC_ICDABR17_TINT143_SHIFT (15u) -#define INTC_ICDABR17_TINT144_SHIFT (16u) -#define INTC_ICDABR17_TINT145_SHIFT (17u) -#define INTC_ICDABR17_TINT146_SHIFT (18u) -#define INTC_ICDABR17_TINT147_SHIFT (19u) -#define INTC_ICDABR17_TINT148_SHIFT (20u) -#define INTC_ICDABR17_TINT149_SHIFT (21u) -#define INTC_ICDABR17_TINT150_SHIFT (22u) -#define INTC_ICDABR17_TINT151_SHIFT (23u) -#define INTC_ICDABR17_TINT152_SHIFT (24u) -#define INTC_ICDABR17_TINT153_SHIFT (25u) -#define INTC_ICDABR17_TINT154_SHIFT (26u) -#define INTC_ICDABR17_TINT155_SHIFT (27u) -#define INTC_ICDABR17_TINT156_SHIFT (28u) -#define INTC_ICDABR17_TINT157_SHIFT (29u) -#define INTC_ICDABR17_TINT158_SHIFT (30u) -#define INTC_ICDABR17_TINT159_SHIFT (31u) - -#define INTC_ICDABR18_TINT160_SHIFT (0u) -#define INTC_ICDABR18_TINT161_SHIFT (1u) -#define INTC_ICDABR18_TINT162_SHIFT (2u) -#define INTC_ICDABR18_TINT163_SHIFT (3u) -#define INTC_ICDABR18_TINT164_SHIFT (4u) -#define INTC_ICDABR18_TINT165_SHIFT (5u) -#define INTC_ICDABR18_TINT166_SHIFT (6u) -#define INTC_ICDABR18_TINT167_SHIFT (7u) -#define INTC_ICDABR18_TINT168_SHIFT (8u) -#define INTC_ICDABR18_TINT169_SHIFT (9u) -#define INTC_ICDABR18_TINT170_SHIFT (10u) - -#define INTC_ICDIPR0_SW0_SHIFT (0u) -#define INTC_ICDIPR0_SW1_SHIFT (8u) -#define INTC_ICDIPR0_SW2_SHIFT (16u) -#define INTC_ICDIPR0_SW3_SHIFT (24u) - -#define INTC_ICDIPR1_SW4_SHIFT (0u) -#define INTC_ICDIPR1_SW5_SHIFT (8u) -#define INTC_ICDIPR1_SW6_SHIFT (16u) -#define INTC_ICDIPR1_SW7_SHIFT (24u) - -#define INTC_ICDIPR2_SW8_SHIFT (0u) -#define INTC_ICDIPR2_SW9_SHIFT (8u) -#define INTC_ICDIPR2_SW10_SHIFT (16u) -#define INTC_ICDIPR2_SW11_SHIFT (24u) - -#define INTC_ICDIPR3_SW12_SHIFT (0u) -#define INTC_ICDIPR3_SW13_SHIFT (8u) -#define INTC_ICDIPR3_SW14_SHIFT (16u) -#define INTC_ICDIPR3_SW15_SHIFT (24u) - -#define INTC_ICDIPR4_PMUIRQ0_SHIFT (0u) -#define INTC_ICDIPR4_COMMRX0_SHIFT (8u) -#define INTC_ICDIPR4_COMMTX0_SHIFT (16u) -#define INTC_ICDIPR4_CTIIRQ0_SHIFT (24u) - -#define INTC_ICDIPR8_IRQ0_SHIFT (0u) -#define INTC_ICDIPR8_IRQ1_SHIFT (8u) -#define INTC_ICDIPR8_IRQ2_SHIFT (16u) -#define INTC_ICDIPR8_IRQ3_SHIFT (24u) - -#define INTC_ICDIPR9_IRQ4_SHIFT (0u) -#define INTC_ICDIPR9_IRQ5_SHIFT (8u) -#define INTC_ICDIPR9_IRQ6_SHIFT (16u) -#define INTC_ICDIPR9_IRQ7_SHIFT (24u) - -#define INTC_ICDIPR10_PL310ERR_SHIFT (0u) -#define INTC_ICDIPR10_DMAINT0_SHIFT (8u) -#define INTC_ICDIPR10_DMAINT1_SHIFT (16u) -#define INTC_ICDIPR10_DMAINT2_SHIFT (24u) - -#define INTC_ICDIPR11_DMAINT3_SHIFT (0u) -#define INTC_ICDIPR11_DMAINT4_SHIFT (8u) -#define INTC_ICDIPR11_DMAINT5_SHIFT (16u) -#define INTC_ICDIPR11_DMAINT6_SHIFT (24u) - -#define INTC_ICDIPR12_DMAINT7_SHIFT (0u) -#define INTC_ICDIPR12_DMAINT8_SHIFT (8u) -#define INTC_ICDIPR12_DMAINT9_SHIFT (16u) -#define INTC_ICDIPR12_DMAINT10_SHIFT (24u) - -#define INTC_ICDIPR13_DMAINT11_SHIFT (0u) -#define INTC_ICDIPR13_DMAINT12_SHIFT (8u) -#define INTC_ICDIPR13_DMAINT13_SHIFT (16u) -#define INTC_ICDIPR13_DMAINT14_SHIFT (24u) - -#define INTC_ICDIPR14_DMAINT15_SHIFT (0u) -#define INTC_ICDIPR14_DMAERR_SHIFT (8u) - -#define INTC_ICDIPR18_USBI0_SHIFT (8u) -#define INTC_ICDIPR18_USBI1_SHIFT (16u) -#define INTC_ICDIPR18_S0_VI_VSYNC0_SHIFT (24u) - -#define INTC_ICDIPR19_S0_LO_VSYNC0_SHIFT (0u) -#define INTC_ICDIPR19_S0_VSYNCERR0_SHIFT (8u) -#define INTC_ICDIPR19_GR3_VLINE0_SHIFT (16u) -#define INTC_ICDIPR19_S0_VFIELD0_SHIFT (24u) - -#define INTC_ICDIPR20_IV1_VBUFERR0_SHIFT (0u) -#define INTC_ICDIPR20_IV3_VBUFERR0_SHIFT (8u) -#define INTC_ICDIPR20_IV5_VBUFERR0_SHIFT (16u) -#define INTC_ICDIPR20_IV6_VBUFERR0_SHIFT (24u) - -#define INTC_ICDIPR21_S0_WLINE0_SHIFT (0u) -#define INTC_ICDIPR21_S1_VI_VSYNC0_SHIFT (8u) -#define INTC_ICDIPR21_S1_LO_VSYNC0_SHIFT (16u) -#define INTC_ICDIPR21_S1_VSYNCERR0_SHIFT (24u) - -#define INTC_ICDIPR22_S1_VFIELD0_SHIFT (0u) -#define INTC_ICDIPR22_IV2_VBUFERR0_SHIFT (8u) -#define INTC_ICDIPR22_IV4_VBUFERR0_SHIFT (16u) -#define INTC_ICDIPR22_S1_WLINE0_SHIFT (24u) - -#define INTC_ICDIPR23_OIR_VI_VSYNC0_SHIFT (0u) -#define INTC_ICDIPR23_OIR_LO_VSYNC0_SHIFT (8u) -#define INTC_ICDIPR23_OIR_VSYNCERR0_SHIFT (16u) -#define INTC_ICDIPR23_OIR_VFIELD0_SHIFT (24u) - -#define INTC_ICDIPR24_IV7_VBUFERR0_SHIFT (0u) -#define INTC_ICDIPR24_IV8_VBUFERR0_SHIFT (8u) -#define INTC_ICDIPR24_S0_VI_VSYNC1_SHIFT (24u) - -#define INTC_ICDIPR25_S0_LO_VSYNC1_SHIFT (0u) -#define INTC_ICDIPR25_S0_VSYNCERR1_SHIFT (8u) -#define INTC_ICDIPR25_GR3_VLINE1_SHIFT (16u) -#define INTC_ICDIPR25_S0_VFIELD1_SHIFT (24u) - -#define INTC_ICDIPR26_IV1_VBUFERR1_SHIFT (0u) -#define INTC_ICDIPR26_IV3_VBUFERR1_SHIFT (8u) -#define INTC_ICDIPR26_IV5_VBUFERR1_SHIFT (16u) -#define INTC_ICDIPR26_IV6_VBUFERR1_SHIFT (24u) - -#define INTC_ICDIPR27_S0_WLINE1_SHIFT (0u) -#define INTC_ICDIPR27_S1_VI_VSYNC1_SHIFT (8u) -#define INTC_ICDIPR27_S1_LO_VSYNC1_SHIFT (16u) -#define INTC_ICDIPR27_S1_VSYNCERR1_SHIFT (24u) - -#define INTC_ICDIPR28_S1_VFIELD1_SHIFT (0u) -#define INTC_ICDIPR28_IV2_VBUFERR1_SHIFT (8u) -#define INTC_ICDIPR28_IV4_VBUFERR1_SHIFT (16u) -#define INTC_ICDIPR28_S1_WLINE1_SHIFT (24u) - -#define INTC_ICDIPR29_OIR_VI_VSYNC1_SHIFT (0u) -#define INTC_ICDIPR29_OIR_LO_VSYNC1_SHIFT (8u) -#define INTC_ICDIPR29_OIR_VLINE1_SHIFT (16u) -#define INTC_ICDIPR29_OIR_VFIELD1_SHIFT (24u) - -#define INTC_ICDIPR30_IV7_VBUFERR1_SHIFT (0u) -#define INTC_ICDIPR30_IV8_VBUFERR1_SHIFT (8u) -#define INTC_ICDIPR30_IMRDI_SHIFT (24u) - -#define INTC_ICDIPR31_IMR2I0_SHIFT (0u) -#define INTC_ICDIPR31_IMR2I1_SHIFT (8u) -#define INTC_ICDIPR31_JEDI_SHIFT (16u) -#define INTC_ICDIPR31_JDTI_SHIFT (24u) - -#define INTC_ICDIPR32_CMP0_SHIFT (0u) -#define INTC_ICDIPR32_CMP1_SHIFT (8u) -#define INTC_ICDIPR32_INT0_SHIFT (16u) -#define INTC_ICDIPR32_INT1_SHIFT (24u) - -#define INTC_ICDIPR33_INT2_SHIFT (0u) -#define INTC_ICDIPR33_INT3_SHIFT (8u) -#define INTC_ICDIPR33_OSTM0TINT_SHIFT (16u) -#define INTC_ICDIPR33_OSTM1TINT_SHIFT (24u) - -#define INTC_ICDIPR34_CMI_SHIFT (0u) -#define INTC_ICDIPR34_WTOUT_SHIFT (8u) -#define INTC_ICDIPR34_ITI_SHIFT (16u) -#define INTC_ICDIPR34_TGI0A_SHIFT (24u) - -#define INTC_ICDIPR35_TGI0B_SHIFT (0u) -#define INTC_ICDIPR35_TGI0C_SHIFT (8u) -#define INTC_ICDIPR35_TGI0D_SHIFT (16u) -#define INTC_ICDIPR35_TGI0V_SHIFT (24u) - -#define INTC_ICDIPR36_TGI0E_SHIFT (0u) -#define INTC_ICDIPR36_TGI0F_SHIFT (8u) -#define INTC_ICDIPR36_TGI1A_SHIFT (16u) -#define INTC_ICDIPR36_TGI1B_SHIFT (24u) - -#define INTC_ICDIPR37_TGI1V_SHIFT (0u) -#define INTC_ICDIPR37_TGI1U_SHIFT (8u) -#define INTC_ICDIPR37_TGI2A_SHIFT (16u) -#define INTC_ICDIPR37_TGI2B_SHIFT (24u) - -#define INTC_ICDIPR38_TGI2V_SHIFT (0u) -#define INTC_ICDIPR38_TGI2U_SHIFT (8u) -#define INTC_ICDIPR38_TGI3A_SHIFT (16u) -#define INTC_ICDIPR38_TGI3B_SHIFT (24u) - -#define INTC_ICDIPR39_TGI3C_SHIFT (0u) -#define INTC_ICDIPR39_TGI3D_SHIFT (8u) -#define INTC_ICDIPR39_TGI3V_SHIFT (16u) -#define INTC_ICDIPR39_TGI4A_SHIFT (24u) - -#define INTC_ICDIPR40_TGI4B_SHIFT (0u) -#define INTC_ICDIPR40_TGI4C_SHIFT (8u) -#define INTC_ICDIPR40_TGI4D_SHIFT (16u) -#define INTC_ICDIPR40_TGI4V_SHIFT (24u) - -#define INTC_ICDIPR41_CMI1_SHIFT (0u) -#define INTC_ICDIPR41_CMI2_SHIFT (8u) -#define INTC_ICDIPR41_SGDEI0_SHIFT (16u) -#define INTC_ICDIPR41_SGDEI1_SHIFT (24u) - -#define INTC_ICDIPR42_SGDEI2_SHIFT (0u) -#define INTC_ICDIPR42_SGDEI3_SHIFT (8u) -#define INTC_ICDIPR42_ADI_SHIFT (16u) -#define INTC_ICDIPR42_LMTI_SHIFT (24u) - -#define INTC_ICDIPR43_SSII0_SHIFT (0u) -#define INTC_ICDIPR43_SSIRXI0_SHIFT (8u) -#define INTC_ICDIPR43_SSITXI0_SHIFT (16u) -#define INTC_ICDIPR43_SSII1_SHIFT (24u) - -#define INTC_ICDIPR44_SSIRXI1_SHIFT (0u) -#define INTC_ICDIPR44_SSITXI1_SHIFT (8u) -#define INTC_ICDIPR44_SSII2_SHIFT (16u) -#define INTC_ICDIPR44_SSIRTI2_SHIFT (24u) - -#define INTC_ICDIPR45_SSII3_SHIFT (0u) -#define INTC_ICDIPR45_SSIRXI3_SHIFT (8u) -#define INTC_ICDIPR45_SSITXI3_SHIFT (16u) -#define INTC_ICDIPR45_SSII4_SHIFT (24u) - -#define INTC_ICDIPR46_SSIRTI4_SHIFT (0u) -#define INTC_ICDIPR46_SSII5_SHIFT (8u) -#define INTC_ICDIPR46_SSIRXI5_SHIFT (16u) -#define INTC_ICDIPR46_SSITXI5_SHIFT (24u) - -#define INTC_ICDIPR47_SPDIFI_SHIFT (0u) -#define INTC_ICDIPR47_INTIICTEI0_SHIFT (8u) -#define INTC_ICDIPR47_INTIICRI0_SHIFT (16u) -#define INTC_ICDIPR47_INTIICTI0_SHIFT (24u) - -#define INTC_ICDIPR48_INTIICSPI0_SHIFT (0u) -#define INTC_ICDIPR48_INTIICSTI0_SHIFT (8u) -#define INTC_ICDIPR48_INTIICNAKI0_SHIFT (16u) -#define INTC_ICDIPR48_INTIICALI0_SHIFT (24u) - -#define INTC_ICDIPR49_INTIICTMOI0_SHIFT (0u) -#define INTC_ICDIPR49_INTIICTEI1_SHIFT (8u) -#define INTC_ICDIPR49_INTIICRI1_SHIFT (16u) -#define INTC_ICDIPR49_INTIICTI1_SHIFT (24u) - -#define INTC_ICDIPR50_INTIICSPI1_SHIFT (0u) -#define INTC_ICDIPR50_INTIICSTI1_SHIFT (8u) -#define INTC_ICDIPR50_INTIICNAKI1_SHIFT (16u) -#define INTC_ICDIPR50_INTIICALI1_SHIFT (24u) - -#define INTC_ICDIPR51_INTIICTMOI1_SHIFT (0u) -#define INTC_ICDIPR51_INTIICTEI2_SHIFT (8u) -#define INTC_ICDIPR51_INTIICRI2_SHIFT (16u) -#define INTC_ICDIPR51_INTIICTI2_SHIFT (24u) - -#define INTC_ICDIPR52_INTIICSPI2_SHIFT (0u) -#define INTC_ICDIPR52_INTIICSTI2_SHIFT (8u) -#define INTC_ICDIPR52_INTIICNAKI2_SHIFT (16u) -#define INTC_ICDIPR52_INTIICALI2_SHIFT (24u) - -#define INTC_ICDIPR53_INTIICTMOI2_SHIFT (0u) -#define INTC_ICDIPR53_INTIICTEI3_SHIFT (8u) -#define INTC_ICDIPR53_INTIICRI3_SHIFT (16u) -#define INTC_ICDIPR53_INTIICTI3_SHIFT (24u) - -#define INTC_ICDIPR54_INTIICSPI3_SHIFT (0u) -#define INTC_ICDIPR54_INTIICSTI3_SHIFT (8u) -#define INTC_ICDIPR54_INTIICNAKI3_SHIFT (16u) -#define INTC_ICDIPR54_INTIICALI3_SHIFT (24u) - -#define INTC_ICDIPR55_INTIICTMOI3_SHIFT (0u) -#define INTC_ICDIPR55_BRI0_SHIFT (8u) -#define INTC_ICDIPR55_ERI0_SHIFT (16u) -#define INTC_ICDIPR55_RXI0_SHIFT (24u) - -#define INTC_ICDIPR56_TXI0_SHIFT (0u) -#define INTC_ICDIPR56_BRI1_SHIFT (8u) -#define INTC_ICDIPR56_ERI1_SHIFT (16u) -#define INTC_ICDIPR56_RXI1_SHIFT (24u) - -#define INTC_ICDIPR57_TXI1_SHIFT (0u) -#define INTC_ICDIPR57_BRI2_SHIFT (8u) -#define INTC_ICDIPR57_ERI2_SHIFT (16u) -#define INTC_ICDIPR57_RXI2_SHIFT (24u) - -#define INTC_ICDIPR58_TXI2_SHIFT (0u) -#define INTC_ICDIPR58_BRI3_SHIFT (8u) -#define INTC_ICDIPR58_ERI3_SHIFT (16u) -#define INTC_ICDIPR58_RXI3_SHIFT (24u) - -#define INTC_ICDIPR59_TXI3_SHIFT (0u) -#define INTC_ICDIPR59_BRI4_SHIFT (8u) -#define INTC_ICDIPR59_ERI4_SHIFT (16u) -#define INTC_ICDIPR59_RXI4_SHIFT (24u) - -#define INTC_ICDIPR60_TXI4_SHIFT (0u) -#define INTC_ICDIPR60_BRI5_SHIFT (8u) -#define INTC_ICDIPR60_ERI5_SHIFT (16u) -#define INTC_ICDIPR60_RXI5_SHIFT (24u) - -#define INTC_ICDIPR61_TXI5_SHIFT (0u) -#define INTC_ICDIPR61_BRI6_SHIFT (8u) -#define INTC_ICDIPR61_ERI6_SHIFT (16u) -#define INTC_ICDIPR61_RXI6_SHIFT (24u) - -#define INTC_ICDIPR62_TXI6_SHIFT (0u) -#define INTC_ICDIPR62_BRI7_SHIFT (8u) -#define INTC_ICDIPR62_ERI7_SHIFT (16u) -#define INTC_ICDIPR62_RXI7_SHIFT (24u) - -#define INTC_ICDIPR63_TXI7_SHIFT (0u) -#define INTC_ICDIPR63_INTRCANGERR_SHIFT (8u) -#define INTC_ICDIPR63_INTRCANGRECC_SHIFT (16u) -#define INTC_ICDIPR63_INTRCAN0REC_SHIFT (24u) - -#define INTC_ICDIPR64_INTRCAN0ERR_SHIFT (0u) -#define INTC_ICDIPR64_INTRCAN0TRX_SHIFT (8u) -#define INTC_ICDIPR64_INTRCAN1REC_SHIFT (16u) -#define INTC_ICDIPR64_INTRCAN1ERR_SHIFT (24u) - -#define INTC_ICDIPR65_INTRCAN1TRX_SHIFT (0u) -#define INTC_ICDIPR65_INTRCAN2REC_SHIFT (8u) -#define INTC_ICDIPR65_INTRCAN2ERR_SHIFT (16u) -#define INTC_ICDIPR65_INTRCAN2TRX_SHIFT (24u) - -#define INTC_ICDIPR66_INTRCAN3REC_SHIFT (0u) -#define INTC_ICDIPR66_INTRCAN3ERR_SHIFT (8u) -#define INTC_ICDIPR66_INTRCAN3TRX_SHIFT (16u) -#define INTC_ICDIPR66_INTRCAN4REC_SHIFT (24u) - -#define INTC_ICDIPR67_INTRCAN4ERR_SHIFT (0u) -#define INTC_ICDIPR67_INTRCAN4TRX_SHIFT (8u) -#define INTC_ICDIPR67_SPEI0_SHIFT (16u) -#define INTC_ICDIPR67_SPRI0_SHIFT (24u) - -#define INTC_ICDIPR68_SPTI0_SHIFT (0u) -#define INTC_ICDIPR68_SPEI1_SHIFT (8u) -#define INTC_ICDIPR68_SPRI1_SHIFT (16u) -#define INTC_ICDIPR68_SPTI1_SHIFT (24u) - -#define INTC_ICDIPR69_SPEI2_SHIFT (0u) -#define INTC_ICDIPR69_SPRI2_SHIFT (8u) -#define INTC_ICDIPR69_SPTI2_SHIFT (16u) -#define INTC_ICDIPR69_SPEI3_SHIFT (24u) - -#define INTC_ICDIPR70_SPRI3_SHIFT (0u) -#define INTC_ICDIPR70_SPTI3_SHIFT (8u) -#define INTC_ICDIPR70_SPEI4_SHIFT (16u) -#define INTC_ICDIPR70_SPRI4_SHIFT (24u) - -#define INTC_ICDIPR71_SPTI4_SHIFT (0u) -#define INTC_ICDIPR71_IEBBTD_SHIFT (8u) -#define INTC_ICDIPR71_IEBBTERR_SHIFT (16u) -#define INTC_ICDIPR71_IEBBTSTA_SHIFT (24u) - -#define INTC_ICDIPR72_IEBBTV_SHIFT (0u) -#define INTC_ICDIPR72_ISY_SHIFT (8u) -#define INTC_ICDIPR72_IERR_SHIFT (16u) -#define INTC_ICDIPR72_ITARG_SHIFT (24u) - -#define INTC_ICDIPR73_ISEC_SHIFT (0u) -#define INTC_ICDIPR73_IBUF_SHIFT (8u) -#define INTC_ICDIPR73_IREADY_SHIFT (16u) -#define INTC_ICDIPR73_FLSTE_SHIFT (24u) - -#define INTC_ICDIPR74_FLTENDI_SHIFT (0u) -#define INTC_ICDIPR74_FLTREQ0I_SHIFT (8u) -#define INTC_ICDIPR74_FLTREQ1I_SHIFT (16u) -#define INTC_ICDIPR74_MMC0_SHIFT (24u) - -#define INTC_ICDIPR75_MMC1_SHIFT (0u) -#define INTC_ICDIPR75_MMC2_SHIFT (8u) -#define INTC_ICDIPR75_SDHI0_3_SHIFT (16u) -#define INTC_ICDIPR75_SDHI0_0_SHIFT (24u) - -#define INTC_ICDIPR76_SDHI0_1_SHIFT (0u) -#define INTC_ICDIPR76_SDHI1_3_SHIFT (8u) -#define INTC_ICDIPR76_SDHI1_0_SHIFT (16u) -#define INTC_ICDIPR76_SDHI1_1_SHIFT (24u) - -#define INTC_ICDIPR77_ARM_SHIFT (0u) -#define INTC_ICDIPR77_PRD_SHIFT (8u) -#define INTC_ICDIPR77_CUP_SHIFT (16u) -#define INTC_ICDIPR77_SCUAI0_SHIFT (24u) - -#define INTC_ICDIPR78_SCUAI1_SHIFT (0u) -#define INTC_ICDIPR78_SCUFDI0_SHIFT (8u) -#define INTC_ICDIPR78_SCUFDI1_SHIFT (16u) -#define INTC_ICDIPR78_SCUFDI2_SHIFT (24u) - -#define INTC_ICDIPR79_SCUFDI3_SHIFT (0u) -#define INTC_ICDIPR79_SCUFUI0_SHIFT (8u) -#define INTC_ICDIPR79_SCUFUI1_SHIFT (16u) -#define INTC_ICDIPR79_SCUFUI2_SHIFT (24u) - -#define INTC_ICDIPR80_SCUFUI3_SHIFT (0u) -#define INTC_ICDIPR80_SCUDVI0_SHIFT (8u) -#define INTC_ICDIPR80_SCUDVI1_SHIFT (16u) -#define INTC_ICDIPR80_SCUDVI2_SHIFT (24u) - -#define INTC_ICDIPR81_SCUDVI3_SHIFT (0u) -#define INTC_ICDIPR81_MLB_CINT_SHIFT (8u) -#define INTC_ICDIPR81_MLB_SINT_SHIFT (16u) -#define INTC_ICDIPR81_DRC0_SHIFT (24u) - -#define INTC_ICDIPR82_DRC1_SHIFT (0u) -#define INTC_ICDIPR82_LINI0_INT_T_SHIFT (24u) - -#define INTC_ICDIPR83_LINI0_INT_R_SHIFT (0u) -#define INTC_ICDIPR83_LINI0_INT_S_SHIFT (8u) -#define INTC_ICDIPR83_LINI0_INT_M_SHIFT (16u) -#define INTC_ICDIPR83_LINI1_INT_T_SHIFT (24u) - -#define INTC_ICDIPR84_LINI1_INT_R_SHIFT (0u) -#define INTC_ICDIPR84_LINI1_INT_S_SHIFT (8u) -#define INTC_ICDIPR84_LINI1_INT_M_SHIFT (16u) - -#define INTC_ICDIPR86_ERI0_SHIFT (24u) - -#define INTC_ICDIPR87_RXI0_SHIFT (0u) -#define INTC_ICDIPR87_TXI0_SHIFT (8u) -#define INTC_ICDIPR87_TEI0_SHIFT (16u) -#define INTC_ICDIPR87_ERI1_SHIFT (24u) - -#define INTC_ICDIPR88_RXI1_SHIFT (0u) -#define INTC_ICDIPR88_TXI1_SHIFT (8u) -#define INTC_ICDIPR88_TEI1_SHIFT (16u) -#define INTC_ICDIPR88_AVBI_DATA_SHIFT (24u) - -#define INTC_ICDIPR89_AVBI_ERROR_SHIFT (0u) -#define INTC_ICDIPR89_AVBI_MANAGE_SHIFT (8u) -#define INTC_ICDIPR89_AVBI_MAC_SHIFT (16u) -#define INTC_ICDIPR89_ETHERI_SHIFT (24u) - -#define INTC_ICDIPR91_CEUI_SHIFT (0u) - -#define INTC_ICDIPR95_H2XMLB_ERRINT_SHIFT (8u) -#define INTC_ICDIPR95_H2XIC1_ERRINT_SHIFT (16u) -#define INTC_ICDIPR95_X2HPERI1_ERRINT_SHIFT (24u) - -#define INTC_ICDIPR96_X2HPERI2_ERRINT_SHIFT (0u) -#define INTC_ICDIPR96_X2HPERI34_ERRINT_SHIFT (8u) -#define INTC_ICDIPR96_X2HPERI5_ERRINT_SHIFT (16u) -#define INTC_ICDIPR96_X2HPERI67_ERRINT_SHIFT (24u) - -#define INTC_ICDIPR97_X2HDBGR_ERRINT_SHIFT (0u) -#define INTC_ICDIPR97_X2HBSC_ERRINT_SHIFT (8u) -#define INTC_ICDIPR97_X2HSPI1_ERRINT_SHIFT (16u) -#define INTC_ICDIPR97_X2HSPI2_ERRINT_SHIFT (24u) - -#define INTC_ICDIPR98_PRRI_SHIFT (0u) -#define INTC_ICDIPR98_IFEI0_SHIFT (8u) -#define INTC_ICDIPR98_OFFI0_SHIFT (16u) -#define INTC_ICDIPR98_PFVEI0_SHIFT (24u) - -#define INTC_ICDIPR99_IFEI1_SHIFT (0u) -#define INTC_ICDIPR99_OFFI1_SHIFT (8u) -#define INTC_ICDIPR99_PFVEI1_SHIFT (16u) - -#define INTC_ICDIPR104_TINT0_SHIFT (0u) -#define INTC_ICDIPR104_TINT1_SHIFT (8u) -#define INTC_ICDIPR104_TINT2_SHIFT (16u) -#define INTC_ICDIPR104_TINT3_SHIFT (24u) - -#define INTC_ICDIPR105_TINT4_SHIFT (0u) -#define INTC_ICDIPR105_TINT5_SHIFT (8u) -#define INTC_ICDIPR105_TINT6_SHIFT (16u) -#define INTC_ICDIPR105_TINT7_SHIFT (24u) - -#define INTC_ICDIPR106_TINT8_SHIFT (0u) -#define INTC_ICDIPR106_TINT9_SHIFT (8u) -#define INTC_ICDIPR106_TINT10_SHIFT (16u) -#define INTC_ICDIPR106_TINT11_SHIFT (24u) - -#define INTC_ICDIPR107_TINT12_SHIFT (0u) -#define INTC_ICDIPR107_TINT13_SHIFT (8u) -#define INTC_ICDIPR107_TINT14_SHIFT (16u) -#define INTC_ICDIPR107_TINT15_SHIFT (24u) - -#define INTC_ICDIPR108_TINT16_SHIFT (0u) -#define INTC_ICDIPR108_TINT17_SHIFT (8u) -#define INTC_ICDIPR108_TINT18_SHIFT (16u) -#define INTC_ICDIPR108_TINT19_SHIFT (24u) - -#define INTC_ICDIPR109_TINT20_SHIFT (0u) -#define INTC_ICDIPR109_TINT21_SHIFT (8u) -#define INTC_ICDIPR109_TINT22_SHIFT (16u) -#define INTC_ICDIPR109_TINT23_SHIFT (24u) - -#define INTC_ICDIPR110_TINT24_SHIFT (0u) -#define INTC_ICDIPR110_TINT25_SHIFT (8u) -#define INTC_ICDIPR110_TINT26_SHIFT (16u) -#define INTC_ICDIPR110_TINT27_SHIFT (24u) - -#define INTC_ICDIPR111_TINT28_SHIFT (0u) -#define INTC_ICDIPR111_TINT29_SHIFT (8u) -#define INTC_ICDIPR111_TINT30_SHIFT (16u) -#define INTC_ICDIPR111_TINT31_SHIFT (24u) - -#define INTC_ICDIPR112_TINT32_SHIFT (0u) -#define INTC_ICDIPR112_TINT33_SHIFT (8u) -#define INTC_ICDIPR112_TINT34_SHIFT (16u) -#define INTC_ICDIPR112_TINT35_SHIFT (24u) - -#define INTC_ICDIPR113_TINT36_SHIFT (0u) -#define INTC_ICDIPR113_TINT37_SHIFT (8u) -#define INTC_ICDIPR113_TINT38_SHIFT (16u) -#define INTC_ICDIPR113_TINT39_SHIFT (24u) - -#define INTC_ICDIPR114_TINT40_SHIFT (0u) -#define INTC_ICDIPR114_TINT41_SHIFT (8u) -#define INTC_ICDIPR114_TINT42_SHIFT (16u) -#define INTC_ICDIPR114_TINT43_SHIFT (24u) - -#define INTC_ICDIPR115_TINT44_SHIFT (0u) -#define INTC_ICDIPR115_TINT45_SHIFT (8u) -#define INTC_ICDIPR115_TINT46_SHIFT (16u) -#define INTC_ICDIPR115_TINT47_SHIFT (24u) - -#define INTC_ICDIPR116_TINT48_SHIFT (0u) -#define INTC_ICDIPR116_TINT49_SHIFT (8u) -#define INTC_ICDIPR116_TINT50_SHIFT (16u) -#define INTC_ICDIPR116_TINT51_SHIFT (24u) - -#define INTC_ICDIPR117_TINT52_SHIFT (0u) -#define INTC_ICDIPR117_TINT53_SHIFT (8u) -#define INTC_ICDIPR117_TINT54_SHIFT (16u) -#define INTC_ICDIPR117_TINT55_SHIFT (24u) - -#define INTC_ICDIPR118_TINT56_SHIFT (0u) -#define INTC_ICDIPR118_TINT57_SHIFT (8u) -#define INTC_ICDIPR118_TINT58_SHIFT (16u) -#define INTC_ICDIPR118_TINT59_SHIFT (24u) - -#define INTC_ICDIPR119_TINT60_SHIFT (0u) -#define INTC_ICDIPR119_TINT61_SHIFT (8u) -#define INTC_ICDIPR119_TINT62_SHIFT (16u) -#define INTC_ICDIPR119_TINT63_SHIFT (24u) - -#define INTC_ICDIPR120_TINT64_SHIFT (0u) -#define INTC_ICDIPR120_TINT65_SHIFT (8u) -#define INTC_ICDIPR120_TINT66_SHIFT (16u) -#define INTC_ICDIPR120_TINT67_SHIFT (24u) - -#define INTC_ICDIPR121_TINT68_SHIFT (0u) -#define INTC_ICDIPR121_TINT69_SHIFT (8u) -#define INTC_ICDIPR121_TINT70_SHIFT (16u) -#define INTC_ICDIPR121_TINT71_SHIFT (24u) - -#define INTC_ICDIPR122_TINT72_SHIFT (0u) -#define INTC_ICDIPR122_TINT73_SHIFT (8u) -#define INTC_ICDIPR122_TINT74_SHIFT (16u) -#define INTC_ICDIPR122_TINT75_SHIFT (24u) - -#define INTC_ICDIPR123_TINT76_SHIFT (0u) -#define INTC_ICDIPR123_TINT77_SHIFT (8u) -#define INTC_ICDIPR123_TINT78_SHIFT (16u) -#define INTC_ICDIPR123_TINT79_SHIFT (24u) - -#define INTC_ICDIPR124_TINT80_SHIFT (0u) -#define INTC_ICDIPR124_TINT81_SHIFT (8u) -#define INTC_ICDIPR124_TINT82_SHIFT (16u) -#define INTC_ICDIPR124_TINT83_SHIFT (24u) - -#define INTC_ICDIPR125_TINT84_SHIFT (0u) -#define INTC_ICDIPR125_TINT85_SHIFT (8u) -#define INTC_ICDIPR125_TINT86_SHIFT (16u) -#define INTC_ICDIPR125_TINT87_SHIFT (24u) - -#define INTC_ICDIPR126_TINT88_SHIFT (0u) -#define INTC_ICDIPR126_TINT89_SHIFT (8u) -#define INTC_ICDIPR126_TINT90_SHIFT (16u) -#define INTC_ICDIPR126_TINT91_SHIFT (24u) - -#define INTC_ICDIPR127_TINT92_SHIFT (0u) -#define INTC_ICDIPR127_TINT93_SHIFT (8u) -#define INTC_ICDIPR127_TINT94_SHIFT (16u) -#define INTC_ICDIPR127_TINT95_SHIFT (24u) - -#define INTC_ICDIPR128_TINT96_SHIFT (0u) -#define INTC_ICDIPR128_TINT97_SHIFT (8u) -#define INTC_ICDIPR128_TINT98_SHIFT (16u) -#define INTC_ICDIPR128_TINT99_SHIFT (24u) - -#define INTC_ICDIPR129_TINT100_SHIFT (0u) -#define INTC_ICDIPR129_TINT101_SHIFT (8u) -#define INTC_ICDIPR129_TINT102_SHIFT (16u) -#define INTC_ICDIPR129_TINT103_SHIFT (24u) - -#define INTC_ICDIPR130_TINT104_SHIFT (0u) -#define INTC_ICDIPR130_TINT105_SHIFT (8u) -#define INTC_ICDIPR130_TINT106_SHIFT (16u) -#define INTC_ICDIPR130_TINT107_SHIFT (24u) - -#define INTC_ICDIPR131_TINT108_SHIFT (0u) -#define INTC_ICDIPR131_TINT109_SHIFT (8u) -#define INTC_ICDIPR131_TINT110_SHIFT (16u) -#define INTC_ICDIPR131_TINT111_SHIFT (24u) - -#define INTC_ICDIPR132_TINT112_SHIFT (0u) -#define INTC_ICDIPR132_TINT113_SHIFT (8u) -#define INTC_ICDIPR132_TINT114_SHIFT (16u) -#define INTC_ICDIPR132_TINT115_SHIFT (24u) - -#define INTC_ICDIPR133_TINT116_SHIFT (0u) -#define INTC_ICDIPR133_TINT117_SHIFT (8u) -#define INTC_ICDIPR133_TINT118_SHIFT (16u) -#define INTC_ICDIPR133_TINT119_SHIFT (24u) - -#define INTC_ICDIPR134_TINT120_SHIFT (0u) -#define INTC_ICDIPR134_TINT121_SHIFT (8u) -#define INTC_ICDIPR134_TINT122_SHIFT (16u) -#define INTC_ICDIPR134_TINT123_SHIFT (24u) - -#define INTC_ICDIPR135_TINT124_SHIFT (0u) -#define INTC_ICDIPR135_TINT125_SHIFT (8u) -#define INTC_ICDIPR135_TINT126_SHIFT (16u) -#define INTC_ICDIPR135_TINT127_SHIFT (24u) - -#define INTC_ICDIPR136_TINT128_SHIFT (0u) -#define INTC_ICDIPR136_TINT129_SHIFT (8u) -#define INTC_ICDIPR136_TINT130_SHIFT (16u) -#define INTC_ICDIPR136_TINT131_SHIFT (24u) - -#define INTC_ICDIPR137_TINT132_SHIFT (0u) -#define INTC_ICDIPR137_TINT133_SHIFT (8u) -#define INTC_ICDIPR137_TINT134_SHIFT (16u) -#define INTC_ICDIPR137_TINT135_SHIFT (24u) - -#define INTC_ICDIPR138_TINT136_SHIFT (0u) -#define INTC_ICDIPR138_TINT137_SHIFT (8u) -#define INTC_ICDIPR138_TINT138_SHIFT (16u) -#define INTC_ICDIPR138_TINT139_SHIFT (24u) - -#define INTC_ICDIPR139_TINT140_SHIFT (0u) -#define INTC_ICDIPR139_TINT141_SHIFT (8u) -#define INTC_ICDIPR139_TINT142_SHIFT (16u) -#define INTC_ICDIPR139_TINT143_SHIFT (24u) - -#define INTC_ICDIPR140_TINT144_SHIFT (0u) -#define INTC_ICDIPR140_TINT145_SHIFT (8u) -#define INTC_ICDIPR140_TINT146_SHIFT (16u) -#define INTC_ICDIPR140_TINT147_SHIFT (24u) - -#define INTC_ICDIPR141_TINT148_SHIFT (0u) -#define INTC_ICDIPR141_TINT149_SHIFT (8u) -#define INTC_ICDIPR141_TINT150_SHIFT (16u) -#define INTC_ICDIPR141_TINT151_SHIFT (24u) - -#define INTC_ICDIPR142_TINT152_SHIFT (0u) -#define INTC_ICDIPR142_TINT153_SHIFT (8u) -#define INTC_ICDIPR142_TINT154_SHIFT (16u) -#define INTC_ICDIPR142_TINT155_SHIFT (24u) - -#define INTC_ICDIPR143_TINT156_SHIFT (0u) -#define INTC_ICDIPR143_TINT157_SHIFT (8u) -#define INTC_ICDIPR143_TINT158_SHIFT (16u) -#define INTC_ICDIPR143_TINT159_SHIFT (24u) - -#define INTC_ICDIPR144_TINT160_SHIFT (0u) -#define INTC_ICDIPR144_TINT161_SHIFT (8u) -#define INTC_ICDIPR144_TINT162_SHIFT (16u) -#define INTC_ICDIPR144_TINT163_SHIFT (24u) - -#define INTC_ICDIPR145_TINT164_SHIFT (0u) -#define INTC_ICDIPR145_TINT165_SHIFT (8u) -#define INTC_ICDIPR145_TINT166_SHIFT (16u) -#define INTC_ICDIPR145_TINT167_SHIFT (24u) - -#define INTC_ICDIPR146_TINT168_SHIFT (0u) -#define INTC_ICDIPR146_TINT169_SHIFT (8u) -#define INTC_ICDIPR146_TINT170_SHIFT (16u) - -#define INTC_ICDIPTR0_SW0_SHIFT (0u) -#define INTC_ICDIPTR0_SW1_SHIFT (8u) -#define INTC_ICDIPTR0_SW2_SHIFT (16u) -#define INTC_ICDIPTR0_SW3_SHIFT (24u) - -#define INTC_ICDIPTR1_SW4_SHIFT (0u) -#define INTC_ICDIPTR1_SW5_SHIFT (8u) -#define INTC_ICDIPTR1_SW6_SHIFT (16u) -#define INTC_ICDIPTR1_SW7_SHIFT (24u) - -#define INTC_ICDIPTR2_SW8_SHIFT (0u) -#define INTC_ICDIPTR2_SW9_SHIFT (8u) -#define INTC_ICDIPTR2_SW10_SHIFT (16u) -#define INTC_ICDIPTR2_SW11_SHIFT (24u) - -#define INTC_ICDIPTR3_SW12_SHIFT (0u) -#define INTC_ICDIPTR3_SW13_SHIFT (8u) -#define INTC_ICDIPTR3_SW14_SHIFT (16u) -#define INTC_ICDIPTR3_SW15_SHIFT (24u) - -#define INTC_ICDIPTR4_PMUIRQ0_SHIFT (0u) -#define INTC_ICDIPTR4_COMMRX0_SHIFT (8u) -#define INTC_ICDIPTR4_COMMTX0_SHIFT (16u) -#define INTC_ICDIPTR4_CTIIRQ0_SHIFT (24u) - -#define INTC_ICDIPTR8_IRQ0_SHIFT (0u) -#define INTC_ICDIPTR8_IRQ1_SHIFT (8u) -#define INTC_ICDIPTR8_IRQ2_SHIFT (16u) -#define INTC_ICDIPTR8_IRQ3_SHIFT (24u) - -#define INTC_ICDIPTR9_IRQ4_SHIFT (0u) -#define INTC_ICDIPTR9_IRQ5_SHIFT (8u) -#define INTC_ICDIPTR9_IRQ6_SHIFT (16u) -#define INTC_ICDIPTR9_IRQ7_SHIFT (24u) - -#define INTC_ICDIPTR10_PL310ERR_SHIFT (0u) -#define INTC_ICDIPTR10_DMAINT0_SHIFT (8u) -#define INTC_ICDIPTR10_DMAINT1_SHIFT (16u) -#define INTC_ICDIPTR10_DMAINT2_SHIFT (24u) - -#define INTC_ICDIPTR11_DMAINT3_SHIFT (0u) -#define INTC_ICDIPTR11_DMAINT4_SHIFT (8u) -#define INTC_ICDIPTR11_DMAINT5_SHIFT (16u) -#define INTC_ICDIPTR11_DMAINT6_SHIFT (24u) - -#define INTC_ICDIPTR12_DMAINT7_SHIFT (0u) -#define INTC_ICDIPTR12_DMAINT8_SHIFT (8u) -#define INTC_ICDIPTR12_DMAINT9_SHIFT (16u) -#define INTC_ICDIPTR12_DMAINT10_SHIFT (24u) - -#define INTC_ICDIPTR13_DMAINT11_SHIFT (0u) -#define INTC_ICDIPTR13_DMAINT12_SHIFT (8u) -#define INTC_ICDIPTR13_DMAINT13_SHIFT (16u) -#define INTC_ICDIPTR13_DMAINT14_SHIFT (24u) - -#define INTC_ICDIPTR14_DMAINT15_SHIFT (0u) -#define INTC_ICDIPTR14_DMAERR_SHIFT (8u) - -#define INTC_ICDIPTR18_USBI0_SHIFT (8u) -#define INTC_ICDIPTR18_USBI1_SHIFT (16u) -#define INTC_ICDIPTR18_S0_VI_VSYNC0_SHIFT (24u) - -#define INTC_ICDIPTR19_S0_LO_VSYNC0_SHIFT (0u) -#define INTC_ICDIPTR19_S0_VSYNCERR0_SHIFT (8u) -#define INTC_ICDIPTR19_GR3_VLINE0_SHIFT (16u) -#define INTC_ICDIPTR19_S0_VFIELD0_SHIFT (24u) - -#define INTC_ICDIPTR20_IV1_VBUFERR0_SHIFT (0u) -#define INTC_ICDIPTR20_IV3_VBUFERR0_SHIFT (8u) -#define INTC_ICDIPTR20_IV5_VBUFERR0_SHIFT (16u) -#define INTC_ICDIPTR20_IV6_VBUFERR0_SHIFT (24u) - -#define INTC_ICDIPTR21_S0_WLINE0_SHIFT (0u) -#define INTC_ICDIPTR21_S1_VI_VSYNC0_SHIFT (8u) -#define INTC_ICDIPTR21_S1_LO_VSYNC0_SHIFT (16u) -#define INTC_ICDIPTR21_S1_VSYNCERR0_SHIFT (24u) - -#define INTC_ICDIPTR22_S1_VFIELD0_SHIFT (0u) -#define INTC_ICDIPTR22_IV2_VBUFERR0_SHIFT (8u) -#define INTC_ICDIPTR22_IV4_VBUFERR0_SHIFT (16u) -#define INTC_ICDIPTR22_S1_WLINE0_SHIFT (24u) - -#define INTC_ICDIPTR23_OIR_VI_VSYNC0_SHIFT (0u) -#define INTC_ICDIPTR23_OIR_LO_VSYNC0_SHIFT (8u) -#define INTC_ICDIPTR23_OIR_VSYNCERR0_SHIFT (16u) -#define INTC_ICDIPTR23_OIR_VFIELD0_SHIFT (24u) - -#define INTC_ICDIPTR24_IV7_VBUFERR0_SHIFT (0u) -#define INTC_ICDIPTR24_IV8_VBUFERR0_SHIFT (8u) -#define INTC_ICDIPTR24_S0_VI_VSYNC1_SHIFT (24u) - -#define INTC_ICDIPTR25_S0_LO_VSYNC1_SHIFT (0u) -#define INTC_ICDIPTR25_S0_VSYNCERR1_SHIFT (8u) -#define INTC_ICDIPTR25_GR3_VLINE1_SHIFT (16u) -#define INTC_ICDIPTR25_S0_VFIELD1_SHIFT (24u) - -#define INTC_ICDIPTR26_IV1_VBUFERR1_SHIFT (0u) -#define INTC_ICDIPTR26_IV3_VBUFERR1_SHIFT (8u) -#define INTC_ICDIPTR26_IV5_VBUFERR1_SHIFT (16u) -#define INTC_ICDIPTR26_IV6_VBUFERR1_SHIFT (24u) - -#define INTC_ICDIPTR27_S0_WLINE1_SHIFT (0u) -#define INTC_ICDIPTR27_S1_VI_VSYNC1_SHIFT (8u) -#define INTC_ICDIPTR27_S1_LO_VSYNC1_SHIFT (16u) -#define INTC_ICDIPTR27_S1_VSYNCERR1_SHIFT (24u) - -#define INTC_ICDIPTR28_S1_VFIELD1_SHIFT (0u) -#define INTC_ICDIPTR28_IV2_VBUFERR1_SHIFT (8u) -#define INTC_ICDIPTR28_IV4_VBUFERR1_SHIFT (16u) -#define INTC_ICDIPTR28_S1_WLINE1_SHIFT (24u) - -#define INTC_ICDIPTR29_OIR_VI_VSYNC1_SHIFT (0u) -#define INTC_ICDIPTR29_OIR_LO_VSYNC1_SHIFT (8u) -#define INTC_ICDIPTR29_OIR_VLINE1_SHIFT (16u) -#define INTC_ICDIPTR29_OIR_VFIELD1_SHIFT (24u) - -#define INTC_ICDIPTR30_IV7_VBUFERR1_SHIFT (0u) -#define INTC_ICDIPTR30_IV8_VBUFERR1_SHIFT (8u) -#define INTC_ICDIPTR30_IMRDI_SHIFT (24u) - -#define INTC_ICDIPTR31_IMR2I0_SHIFT (0u) -#define INTC_ICDIPTR31_IMR2I1_SHIFT (8u) -#define INTC_ICDIPTR31_JEDI_SHIFT (16u) -#define INTC_ICDIPTR31_JDTI_SHIFT (24u) - -#define INTC_ICDIPTR32_CMP0_SHIFT (0u) -#define INTC_ICDIPTR32_CMP1_SHIFT (8u) -#define INTC_ICDIPTR32_INT0_SHIFT (16u) -#define INTC_ICDIPTR32_INT1_SHIFT (24u) - -#define INTC_ICDIPTR33_INT2_SHIFT (0u) -#define INTC_ICDIPTR33_INT3_SHIFT (8u) -#define INTC_ICDIPTR33_OSTM0TINT_SHIFT (16u) -#define INTC_ICDIPTR33_OSTM1TINT_SHIFT (24u) - -#define INTC_ICDIPTR34_CMI_SHIFT (0u) -#define INTC_ICDIPTR34_WTOUT_SHIFT (8u) -#define INTC_ICDIPTR34_ITI_SHIFT (16u) -#define INTC_ICDIPTR34_TGI0A_SHIFT (24u) - -#define INTC_ICDIPTR35_TGI0B_SHIFT (0u) -#define INTC_ICDIPTR35_TGI0C_SHIFT (8u) -#define INTC_ICDIPTR35_TGI0D_SHIFT (16u) -#define INTC_ICDIPTR35_TGI0V_SHIFT (24u) - -#define INTC_ICDIPTR36_TGI0E_SHIFT (0u) -#define INTC_ICDIPTR36_TGI0F_SHIFT (8u) -#define INTC_ICDIPTR36_TGI1A_SHIFT (16u) -#define INTC_ICDIPTR36_TGI1B_SHIFT (24u) - -#define INTC_ICDIPTR37_TGI1V_SHIFT (0u) -#define INTC_ICDIPTR37_TGI1U_SHIFT (8u) -#define INTC_ICDIPTR37_TGI2A_SHIFT (16u) -#define INTC_ICDIPTR37_TGI2B_SHIFT (24u) - -#define INTC_ICDIPTR38_TGI2V_SHIFT (0u) -#define INTC_ICDIPTR38_TGI2U_SHIFT (8u) -#define INTC_ICDIPTR38_TGI3A_SHIFT (16u) -#define INTC_ICDIPTR38_TGI3B_SHIFT (24u) - -#define INTC_ICDIPTR39_TGI3C_SHIFT (0u) -#define INTC_ICDIPTR39_TGI3D_SHIFT (8u) -#define INTC_ICDIPTR39_TGI3V_SHIFT (16u) -#define INTC_ICDIPTR39_TGI4A_SHIFT (24u) - -#define INTC_ICDIPTR40_TGI4B_SHIFT (0u) -#define INTC_ICDIPTR40_TGI4C_SHIFT (8u) -#define INTC_ICDIPTR40_TGI4D_SHIFT (16u) -#define INTC_ICDIPTR40_TGI4V_SHIFT (24u) - -#define INTC_ICDIPTR41_CMI1_SHIFT (0u) -#define INTC_ICDIPTR41_CMI2_SHIFT (8u) -#define INTC_ICDIPTR41_SGDEI0_SHIFT (16u) -#define INTC_ICDIPTR41_SGDEI1_SHIFT (24u) - -#define INTC_ICDIPTR42_SGDEI2_SHIFT (0u) -#define INTC_ICDIPTR42_SGDEI3_SHIFT (8u) -#define INTC_ICDIPTR42_ADI_SHIFT (16u) -#define INTC_ICDIPTR42_LMTI_SHIFT (24u) - -#define INTC_ICDIPTR43_SSII0_SHIFT (0u) -#define INTC_ICDIPTR43_SSIRXI0_SHIFT (8u) -#define INTC_ICDIPTR43_SSITXI0_SHIFT (16u) -#define INTC_ICDIPTR43_SSII1_SHIFT (24u) - -#define INTC_ICDIPTR44_SSIRXI1_SHIFT (0u) -#define INTC_ICDIPTR44_SSITXI1_SHIFT (8u) -#define INTC_ICDIPTR44_SSII2_SHIFT (16u) -#define INTC_ICDIPTR44_SSIRTI2_SHIFT (24u) - -#define INTC_ICDIPTR45_SSII3_SHIFT (0u) -#define INTC_ICDIPTR45_SSIRXI3_SHIFT (8u) -#define INTC_ICDIPTR45_SSITXI3_SHIFT (16u) -#define INTC_ICDIPTR45_SSII4_SHIFT (24u) - -#define INTC_ICDIPTR46_SSIRTI4_SHIFT (0u) -#define INTC_ICDIPTR46_SSII5_SHIFT (8u) -#define INTC_ICDIPTR46_SSIRXI5_SHIFT (16u) -#define INTC_ICDIPTR46_SSITXI5_SHIFT (24u) - -#define INTC_ICDIPTR47_SPDIFI_SHIFT (0u) -#define INTC_ICDIPTR47_INTIICTEI0_SHIFT (8u) -#define INTC_ICDIPTR47_INTIICRI0_SHIFT (16u) -#define INTC_ICDIPTR47_INTIICTI0_SHIFT (24u) - -#define INTC_ICDIPTR48_INTIICSPI0_SHIFT (0u) -#define INTC_ICDIPTR48_INTIICSTI0_SHIFT (8u) -#define INTC_ICDIPTR48_INTIICNAKI0_SHIFT (16u) -#define INTC_ICDIPTR48_INTIICALI0_SHIFT (24u) - -#define INTC_ICDIPTR49_INTIICTMOI0_SHIFT (0u) -#define INTC_ICDIPTR49_INTIICTEI1_SHIFT (8u) -#define INTC_ICDIPTR49_INTIICRI1_SHIFT (16u) -#define INTC_ICDIPTR49_INTIICTI1_SHIFT (24u) - -#define INTC_ICDIPTR50_INTIICSPI1_SHIFT (0u) -#define INTC_ICDIPTR50_INTIICSTI1_SHIFT (8u) -#define INTC_ICDIPTR50_INTIICNAKI1_SHIFT (16u) -#define INTC_ICDIPTR50_INTIICALI1_SHIFT (24u) - -#define INTC_ICDIPTR51_INTIICTMOI1_SHIFT (0u) -#define INTC_ICDIPTR51_INTIICTEI2_SHIFT (8u) -#define INTC_ICDIPTR51_INTIICRI2_SHIFT (16u) -#define INTC_ICDIPTR51_INTIICTI2_SHIFT (24u) - -#define INTC_ICDIPTR52_INTIICSPI2_SHIFT (0u) -#define INTC_ICDIPTR52_INTIICSTI2_SHIFT (8u) -#define INTC_ICDIPTR52_INTIICNAKI2_SHIFT (16u) -#define INTC_ICDIPTR52_INTIICALI2_SHIFT (24u) - -#define INTC_ICDIPTR53_INTIICTMOI2_SHIFT (0u) -#define INTC_ICDIPTR53_INTIICTEI3_SHIFT (8u) -#define INTC_ICDIPTR53_INTIICRI3_SHIFT (16u) -#define INTC_ICDIPTR53_INTIICTI3_SHIFT (24u) - -#define INTC_ICDIPTR54_INTIICSPI3_SHIFT (0u) -#define INTC_ICDIPTR54_INTIICSTI3_SHIFT (8u) -#define INTC_ICDIPTR54_INTIICNAKI3_SHIFT (16u) -#define INTC_ICDIPTR54_INTIICALI3_SHIFT (24u) - -#define INTC_ICDIPTR55_INTIICTMOI3_SHIFT (0u) -#define INTC_ICDIPTR55_BRI0_SHIFT (8u) -#define INTC_ICDIPTR55_ERI0_SHIFT (16u) -#define INTC_ICDIPTR55_RXI0_SHIFT (24u) - -#define INTC_ICDIPTR56_TXI0_SHIFT (0u) -#define INTC_ICDIPTR56_BRI1_SHIFT (8u) -#define INTC_ICDIPTR56_ERI1_SHIFT (16u) -#define INTC_ICDIPTR56_RXI1_SHIFT (24u) - -#define INTC_ICDIPTR57_TXI1_SHIFT (0u) -#define INTC_ICDIPTR57_BRI2_SHIFT (8u) -#define INTC_ICDIPTR57_ERI2_SHIFT (16u) -#define INTC_ICDIPTR57_RXI2_SHIFT (24u) - -#define INTC_ICDIPTR58_TXI2_SHIFT (0u) -#define INTC_ICDIPTR58_BRI3_SHIFT (8u) -#define INTC_ICDIPTR58_ERI3_SHIFT (16u) -#define INTC_ICDIPTR58_RXI3_SHIFT (24u) - -#define INTC_ICDIPTR59_TXI3_SHIFT (0u) -#define INTC_ICDIPTR59_BRI4_SHIFT (8u) -#define INTC_ICDIPTR59_ERI4_SHIFT (16u) -#define INTC_ICDIPTR59_RXI4_SHIFT (24u) - -#define INTC_ICDIPTR60_TXI4_SHIFT (0u) -#define INTC_ICDIPTR60_BRI5_SHIFT (8u) -#define INTC_ICDIPTR60_ERI5_SHIFT (16u) -#define INTC_ICDIPTR60_RXI5_SHIFT (24u) - -#define INTC_ICDIPTR61_TXI5_SHIFT (0u) -#define INTC_ICDIPTR61_BRI6_SHIFT (8u) -#define INTC_ICDIPTR61_ERI6_SHIFT (16u) -#define INTC_ICDIPTR61_RXI6_SHIFT (24u) - -#define INTC_ICDIPTR62_TXI6_SHIFT (0u) -#define INTC_ICDIPTR62_BRI7_SHIFT (8u) -#define INTC_ICDIPTR62_ERI7_SHIFT (16u) -#define INTC_ICDIPTR62_RXI7_SHIFT (24u) - -#define INTC_ICDIPTR63_TXI7_SHIFT (0u) -#define INTC_ICDIPTR63_INTRCANGERR_SHIFT (8u) -#define INTC_ICDIPTR63_INTRCANGRECC_SHIFT (16u) -#define INTC_ICDIPTR63_INTRCAN0REC_SHIFT (24u) - -#define INTC_ICDIPTR64_INTRCAN0ERR_SHIFT (0u) -#define INTC_ICDIPTR64_INTRCAN0TRX_SHIFT (8u) -#define INTC_ICDIPTR64_INTRCAN1REC_SHIFT (16u) -#define INTC_ICDIPTR64_INTRCAN1ERR_SHIFT (24u) - -#define INTC_ICDIPTR65_INTRCAN1TRX_SHIFT (0u) -#define INTC_ICDIPTR65_INTRCAN2REC_SHIFT (8u) -#define INTC_ICDIPTR65_INTRCAN2ERR_SHIFT (16u) -#define INTC_ICDIPTR65_INTRCAN2TRX_SHIFT (24u) - -#define INTC_ICDIPTR66_INTRCAN3REC_SHIFT (0u) -#define INTC_ICDIPTR66_INTRCAN3ERR_SHIFT (8u) -#define INTC_ICDIPTR66_INTRCAN3TRX_SHIFT (16u) -#define INTC_ICDIPTR66_INTRCAN4REC_SHIFT (24u) - -#define INTC_ICDIPTR67_INTRCAN4ERR_SHIFT (0u) -#define INTC_ICDIPTR67_INTRCAN4TRX_SHIFT (8u) -#define INTC_ICDIPTR67_SPEI0_SHIFT (16u) -#define INTC_ICDIPTR67_SPRI0_SHIFT (24u) - -#define INTC_ICDIPTR68_SPTI0_SHIFT (0u) -#define INTC_ICDIPTR68_SPEI1_SHIFT (8u) -#define INTC_ICDIPTR68_SPRI1_SHIFT (16u) -#define INTC_ICDIPTR68_SPTI1_SHIFT (24u) - -#define INTC_ICDIPTR69_SPEI2_SHIFT (0u) -#define INTC_ICDIPTR69_SPRI2_SHIFT (8u) -#define INTC_ICDIPTR69_SPTI2_SHIFT (16u) -#define INTC_ICDIPTR69_SPEI3_SHIFT (24u) - -#define INTC_ICDIPTR70_SPRI3_SHIFT (0u) -#define INTC_ICDIPTR70_SPTI3_SHIFT (8u) -#define INTC_ICDIPTR70_SPEI4_SHIFT (16u) -#define INTC_ICDIPTR70_SPRI4_SHIFT (24u) - -#define INTC_ICDIPTR71_SPTI4_SHIFT (0u) -#define INTC_ICDIPTR71_IEBBTD_SHIFT (8u) -#define INTC_ICDIPTR71_IEBBTERR_SHIFT (16u) -#define INTC_ICDIPTR71_IEBBTSTA_SHIFT (24u) - -#define INTC_ICDIPTR72_IEBBTV_SHIFT (0u) -#define INTC_ICDIPTR72_ISY_SHIFT (8u) -#define INTC_ICDIPTR72_IERR_SHIFT (16u) -#define INTC_ICDIPTR72_ITARG_SHIFT (24u) - -#define INTC_ICDIPTR73_ISEC_SHIFT (0u) -#define INTC_ICDIPTR73_IBUF_SHIFT (8u) -#define INTC_ICDIPTR73_IREADY_SHIFT (16u) -#define INTC_ICDIPTR73_FLSTE_SHIFT (24u) - -#define INTC_ICDIPTR74_FLTENDI_SHIFT (0u) -#define INTC_ICDIPTR74_FLTREQ0I_SHIFT (8u) -#define INTC_ICDIPTR74_FLTREQ1I_SHIFT (16u) -#define INTC_ICDIPTR74_MMC0_SHIFT (24u) - -#define INTC_ICDIPTR75_MMC1_SHIFT (0u) -#define INTC_ICDIPTR75_MMC2_SHIFT (8u) -#define INTC_ICDIPTR75_SDHI0_3_SHIFT (16u) -#define INTC_ICDIPTR75_SDHI0_0_SHIFT (24u) - -#define INTC_ICDIPTR76_SDHI0_1_SHIFT (0u) -#define INTC_ICDIPTR76_SDHI1_3_SHIFT (8u) -#define INTC_ICDIPTR76_SDHI1_0_SHIFT (16u) -#define INTC_ICDIPTR76_SDHI1_1_SHIFT (24u) - -#define INTC_ICDIPTR77_ARM_SHIFT (0u) -#define INTC_ICDIPTR77_PRD_SHIFT (8u) -#define INTC_ICDIPTR77_CUP_SHIFT (16u) -#define INTC_ICDIPTR77_SCUAI0_SHIFT (24u) - -#define INTC_ICDIPTR78_SCUAI1_SHIFT (0u) -#define INTC_ICDIPTR78_SCUFDI0_SHIFT (8u) -#define INTC_ICDIPTR78_SCUFDI1_SHIFT (16u) -#define INTC_ICDIPTR78_SCUFDI2_SHIFT (24u) - -#define INTC_ICDIPTR79_SCUFDI3_SHIFT (0u) -#define INTC_ICDIPTR79_SCUFUI0_SHIFT (8u) -#define INTC_ICDIPTR79_SCUFUI1_SHIFT (16u) -#define INTC_ICDIPTR79_SCUFUI2_SHIFT (24u) - -#define INTC_ICDIPTR80_SCUFUI3_SHIFT (0u) -#define INTC_ICDIPTR80_SCUDVI0_SHIFT (8u) -#define INTC_ICDIPTR80_SCUDVI1_SHIFT (16u) -#define INTC_ICDIPTR80_SCUDVI2_SHIFT (24u) - -#define INTC_ICDIPTR81_SCUDVI3_SHIFT (0u) -#define INTC_ICDIPTR81_MLB_CINT_SHIFT (8u) -#define INTC_ICDIPTR81_MLB_SINT_SHIFT (16u) -#define INTC_ICDIPTR81_DRC0_SHIFT (24u) - -#define INTC_ICDIPTR82_DRC1_SHIFT (0u) -#define INTC_ICDIPTR82_LINI0_INT_T_SHIFT (24u) - -#define INTC_ICDIPTR83_LINI0_INT_R_SHIFT (0u) -#define INTC_ICDIPTR83_LINI0_INT_S_SHIFT (8u) -#define INTC_ICDIPTR83_LINI0_INT_M_SHIFT (16u) -#define INTC_ICDIPTR83_LINI1_INT_T_SHIFT (24u) - -#define INTC_ICDIPTR84_LINI1_INT_R_SHIFT (0u) -#define INTC_ICDIPTR84_LINI1_INT_S_SHIFT (8u) -#define INTC_ICDIPTR84_LINI1_INT_M_SHIFT (16u) - -#define INTC_ICDIPTR86_ERI0_SHIFT (24u) - -#define INTC_ICDIPTR87_RXI0_SHIFT (0u) -#define INTC_ICDIPTR87_TXI0_SHIFT (8u) -#define INTC_ICDIPTR87_TEI0_SHIFT (16u) -#define INTC_ICDIPTR87_ERI1_SHIFT (24u) - -#define INTC_ICDIPTR88_RXI1_SHIFT (0u) -#define INTC_ICDIPTR88_TXI1_SHIFT (8u) -#define INTC_ICDIPTR88_TEI1_SHIFT (16u) -#define INTC_ICDIPTR88_AVBI_DATA_SHIFT (24u) - -#define INTC_ICDIPTR89_AVBI_ERROR_SHIFT (0u) -#define INTC_ICDIPTR89_AVBI_MANAGE_SHIFT (8u) -#define INTC_ICDIPTR89_AVBI_MAC_SHIFT (16u) -#define INTC_ICDIPTR89_ETHERI_SHIFT (24u) - -#define INTC_ICDIPTR91_CEUI_SHIFT (0u) - -#define INTC_ICDIPTR95_H2XMLB_ERRINT_SHIFT (8u) -#define INTC_ICDIPTR95_H2XIC1_ERRINT_SHIFT (16u) -#define INTC_ICDIPTR95_X2HPERI1_ERRINT_SHIFT (24u) - -#define INTC_ICDIPTR96_X2HPERI2_ERRINT_SHIFT (0u) -#define INTC_ICDIPTR96_X2HPERI34_ERRINT_SHIFT (8u) -#define INTC_ICDIPTR96_X2HPERI5_ERRINT_SHIFT (16u) -#define INTC_ICDIPTR96_X2HPERI67_ERRINT_SHIFT (24u) - -#define INTC_ICDIPTR97_X2HDBGR_ERRINT_SHIFT (0u) -#define INTC_ICDIPTR97_X2HBSC_ERRINT_SHIFT (8u) -#define INTC_ICDIPTR97_X2HSPI1_ERRINT_SHIFT (16u) -#define INTC_ICDIPTR97_X2HSPI2_ERRINT_SHIFT (24u) - -#define INTC_ICDIPTR98_PRRI_SHIFT (0u) -#define INTC_ICDIPTR98_IFEI0_SHIFT (8u) -#define INTC_ICDIPTR98_OFFI0_SHIFT (16u) -#define INTC_ICDIPTR98_PFVEI0_SHIFT (24u) - -#define INTC_ICDIPTR99_IFEI1_SHIFT (0u) -#define INTC_ICDIPTR99_OFFI1_SHIFT (8u) -#define INTC_ICDIPTR99_PFVEI1_SHIFT (16u) - -#define INTC_ICDIPTR104_TINT0_SHIFT (0u) -#define INTC_ICDIPTR104_TINT1_SHIFT (8u) -#define INTC_ICDIPTR104_TINT2_SHIFT (16u) -#define INTC_ICDIPTR104_TINT3_SHIFT (24u) - -#define INTC_ICDIPTR105_TINT4_SHIFT (0u) -#define INTC_ICDIPTR105_TINT5_SHIFT (8u) -#define INTC_ICDIPTR105_TINT6_SHIFT (16u) -#define INTC_ICDIPTR105_TINT7_SHIFT (24u) - -#define INTC_ICDIPTR106_TINT8_SHIFT (0u) -#define INTC_ICDIPTR106_TINT9_SHIFT (8u) -#define INTC_ICDIPTR106_TINT10_SHIFT (16u) -#define INTC_ICDIPTR106_TINT11_SHIFT (24u) - -#define INTC_ICDIPTR107_TINT12_SHIFT (0u) -#define INTC_ICDIPTR107_TINT13_SHIFT (8u) -#define INTC_ICDIPTR107_TINT14_SHIFT (16u) -#define INTC_ICDIPTR107_TINT15_SHIFT (24u) - -#define INTC_ICDIPTR108_TINT16_SHIFT (0u) -#define INTC_ICDIPTR108_TINT17_SHIFT (8u) -#define INTC_ICDIPTR108_TINT18_SHIFT (16u) -#define INTC_ICDIPTR108_TINT19_SHIFT (24u) - -#define INTC_ICDIPTR109_TINT20_SHIFT (0u) -#define INTC_ICDIPTR109_TINT21_SHIFT (8u) -#define INTC_ICDIPTR109_TINT22_SHIFT (16u) -#define INTC_ICDIPTR109_TINT23_SHIFT (24u) - -#define INTC_ICDIPTR110_TINT24_SHIFT (0u) -#define INTC_ICDIPTR110_TINT25_SHIFT (8u) -#define INTC_ICDIPTR110_TINT26_SHIFT (16u) -#define INTC_ICDIPTR110_TINT27_SHIFT (24u) - -#define INTC_ICDIPTR111_TINT28_SHIFT (0u) -#define INTC_ICDIPTR111_TINT29_SHIFT (8u) -#define INTC_ICDIPTR111_TINT30_SHIFT (16u) -#define INTC_ICDIPTR111_TINT31_SHIFT (24u) - -#define INTC_ICDIPTR112_TINT32_SHIFT (0u) -#define INTC_ICDIPTR112_TINT33_SHIFT (8u) -#define INTC_ICDIPTR112_TINT34_SHIFT (16u) -#define INTC_ICDIPTR112_TINT35_SHIFT (24u) - -#define INTC_ICDIPTR113_TINT36_SHIFT (0u) -#define INTC_ICDIPTR113_TINT37_SHIFT (8u) -#define INTC_ICDIPTR113_TINT38_SHIFT (16u) -#define INTC_ICDIPTR113_TINT39_SHIFT (24u) - -#define INTC_ICDIPTR114_TINT40_SHIFT (0u) -#define INTC_ICDIPTR114_TINT41_SHIFT (8u) -#define INTC_ICDIPTR114_TINT42_SHIFT (16u) -#define INTC_ICDIPTR114_TINT43_SHIFT (24u) - -#define INTC_ICDIPTR115_TINT44_SHIFT (0u) -#define INTC_ICDIPTR115_TINT45_SHIFT (8u) -#define INTC_ICDIPTR115_TINT46_SHIFT (16u) -#define INTC_ICDIPTR115_TINT47_SHIFT (24u) - -#define INTC_ICDIPTR116_TINT48_SHIFT (0u) -#define INTC_ICDIPTR116_TINT49_SHIFT (8u) -#define INTC_ICDIPTR116_TINT50_SHIFT (16u) -#define INTC_ICDIPTR116_TINT51_SHIFT (24u) - -#define INTC_ICDIPTR117_TINT52_SHIFT (0u) -#define INTC_ICDIPTR117_TINT53_SHIFT (8u) -#define INTC_ICDIPTR117_TINT54_SHIFT (16u) -#define INTC_ICDIPTR117_TINT55_SHIFT (24u) - -#define INTC_ICDIPTR118_TINT56_SHIFT (0u) -#define INTC_ICDIPTR118_TINT57_SHIFT (8u) -#define INTC_ICDIPTR118_TINT58_SHIFT (16u) -#define INTC_ICDIPTR118_TINT59_SHIFT (24u) - -#define INTC_ICDIPTR119_TINT60_SHIFT (0u) -#define INTC_ICDIPTR119_TINT61_SHIFT (8u) -#define INTC_ICDIPTR119_TINT62_SHIFT (16u) -#define INTC_ICDIPTR119_TINT63_SHIFT (24u) - -#define INTC_ICDIPTR120_TINT64_SHIFT (0u) -#define INTC_ICDIPTR120_TINT65_SHIFT (8u) -#define INTC_ICDIPTR120_TINT66_SHIFT (16u) -#define INTC_ICDIPTR120_TINT67_SHIFT (24u) - -#define INTC_ICDIPTR121_TINT68_SHIFT (0u) -#define INTC_ICDIPTR121_TINT69_SHIFT (8u) -#define INTC_ICDIPTR121_TINT70_SHIFT (16u) -#define INTC_ICDIPTR121_TINT71_SHIFT (24u) - -#define INTC_ICDIPTR122_TINT72_SHIFT (0u) -#define INTC_ICDIPTR122_TINT73_SHIFT (8u) -#define INTC_ICDIPTR122_TINT74_SHIFT (16u) -#define INTC_ICDIPTR122_TINT75_SHIFT (24u) - -#define INTC_ICDIPTR123_TINT76_SHIFT (0u) -#define INTC_ICDIPTR123_TINT77_SHIFT (8u) -#define INTC_ICDIPTR123_TINT78_SHIFT (16u) -#define INTC_ICDIPTR123_TINT79_SHIFT (24u) - -#define INTC_ICDIPTR124_TINT80_SHIFT (0u) -#define INTC_ICDIPTR124_TINT81_SHIFT (8u) -#define INTC_ICDIPTR124_TINT82_SHIFT (16u) -#define INTC_ICDIPTR124_TINT83_SHIFT (24u) - -#define INTC_ICDIPTR125_TINT84_SHIFT (0u) -#define INTC_ICDIPTR125_TINT85_SHIFT (8u) -#define INTC_ICDIPTR125_TINT86_SHIFT (16u) -#define INTC_ICDIPTR125_TINT87_SHIFT (24u) - -#define INTC_ICDIPTR126_TINT88_SHIFT (0u) -#define INTC_ICDIPTR126_TINT89_SHIFT (8u) -#define INTC_ICDIPTR126_TINT90_SHIFT (16u) -#define INTC_ICDIPTR126_TINT91_SHIFT (24u) - -#define INTC_ICDIPTR127_TINT92_SHIFT (0u) -#define INTC_ICDIPTR127_TINT93_SHIFT (8u) -#define INTC_ICDIPTR127_TINT94_SHIFT (16u) -#define INTC_ICDIPTR127_TINT95_SHIFT (24u) - -#define INTC_ICDIPTR128_TINT96_SHIFT (0u) -#define INTC_ICDIPTR128_TINT97_SHIFT (8u) -#define INTC_ICDIPTR128_TINT98_SHIFT (16u) -#define INTC_ICDIPTR128_TINT99_SHIFT (24u) - -#define INTC_ICDIPTR129_TINT100_SHIFT (0u) -#define INTC_ICDIPTR129_TINT101_SHIFT (8u) -#define INTC_ICDIPTR129_TINT102_SHIFT (16u) -#define INTC_ICDIPTR129_TINT103_SHIFT (24u) - -#define INTC_ICDIPTR130_TINT104_SHIFT (0u) -#define INTC_ICDIPTR130_TINT105_SHIFT (8u) -#define INTC_ICDIPTR130_TINT106_SHIFT (16u) -#define INTC_ICDIPTR130_TINT107_SHIFT (24u) - -#define INTC_ICDIPTR131_TINT108_SHIFT (0u) -#define INTC_ICDIPTR131_TINT109_SHIFT (8u) -#define INTC_ICDIPTR131_TINT110_SHIFT (16u) -#define INTC_ICDIPTR131_TINT111_SHIFT (24u) - -#define INTC_ICDIPTR132_TINT112_SHIFT (0u) -#define INTC_ICDIPTR132_TINT113_SHIFT (8u) -#define INTC_ICDIPTR132_TINT114_SHIFT (16u) -#define INTC_ICDIPTR132_TINT115_SHIFT (24u) - -#define INTC_ICDIPTR133_TINT116_SHIFT (0u) -#define INTC_ICDIPTR133_TINT117_SHIFT (8u) -#define INTC_ICDIPTR133_TINT118_SHIFT (16u) -#define INTC_ICDIPTR133_TINT119_SHIFT (24u) - -#define INTC_ICDIPTR134_TINT120_SHIFT (0u) -#define INTC_ICDIPTR134_TINT121_SHIFT (8u) -#define INTC_ICDIPTR134_TINT122_SHIFT (16u) -#define INTC_ICDIPTR134_TINT123_SHIFT (24u) - -#define INTC_ICDIPTR135_TINT124_SHIFT (0u) -#define INTC_ICDIPTR135_TINT125_SHIFT (8u) -#define INTC_ICDIPTR135_TINT126_SHIFT (16u) -#define INTC_ICDIPTR135_TINT127_SHIFT (24u) - -#define INTC_ICDIPTR136_TINT128_SHIFT (0u) -#define INTC_ICDIPTR136_TINT129_SHIFT (8u) -#define INTC_ICDIPTR136_TINT130_SHIFT (16u) -#define INTC_ICDIPTR136_TINT131_SHIFT (24u) - -#define INTC_ICDIPTR137_TINT132_SHIFT (0u) -#define INTC_ICDIPTR137_TINT133_SHIFT (8u) -#define INTC_ICDIPTR137_TINT134_SHIFT (16u) -#define INTC_ICDIPTR137_TINT135_SHIFT (24u) - -#define INTC_ICDIPTR138_TINT136_SHIFT (0u) -#define INTC_ICDIPTR138_TINT137_SHIFT (8u) -#define INTC_ICDIPTR138_TINT138_SHIFT (16u) -#define INTC_ICDIPTR138_TINT139_SHIFT (24u) - -#define INTC_ICDIPTR139_TINT140_SHIFT (0u) -#define INTC_ICDIPTR139_TINT141_SHIFT (8u) -#define INTC_ICDIPTR139_TINT142_SHIFT (16u) -#define INTC_ICDIPTR139_TINT143_SHIFT (24u) - -#define INTC_ICDIPTR140_TINT144_SHIFT (0u) -#define INTC_ICDIPTR140_TINT145_SHIFT (8u) -#define INTC_ICDIPTR140_TINT146_SHIFT (16u) -#define INTC_ICDIPTR140_TINT147_SHIFT (24u) - -#define INTC_ICDIPTR141_TINT148_SHIFT (0u) -#define INTC_ICDIPTR141_TINT149_SHIFT (8u) -#define INTC_ICDIPTR141_TINT150_SHIFT (16u) -#define INTC_ICDIPTR141_TINT151_SHIFT (24u) - -#define INTC_ICDIPTR142_TINT152_SHIFT (0u) -#define INTC_ICDIPTR142_TINT153_SHIFT (8u) -#define INTC_ICDIPTR142_TINT154_SHIFT (16u) -#define INTC_ICDIPTR142_TINT155_SHIFT (24u) - -#define INTC_ICDIPTR143_TINT156_SHIFT (0u) -#define INTC_ICDIPTR143_TINT157_SHIFT (8u) -#define INTC_ICDIPTR143_TINT158_SHIFT (16u) -#define INTC_ICDIPTR143_TINT159_SHIFT (24u) - -#define INTC_ICDIPTR144_TINT160_SHIFT (0u) -#define INTC_ICDIPTR144_TINT161_SHIFT (8u) -#define INTC_ICDIPTR144_TINT162_SHIFT (16u) -#define INTC_ICDIPTR144_TINT163_SHIFT (24u) - -#define INTC_ICDIPTR145_TINT164_SHIFT (0u) -#define INTC_ICDIPTR145_TINT165_SHIFT (8u) -#define INTC_ICDIPTR145_TINT166_SHIFT (16u) -#define INTC_ICDIPTR145_TINT167_SHIFT (24u) - -#define INTC_ICDIPTR146_TINT168_SHIFT (0u) -#define INTC_ICDIPTR146_TINT169_SHIFT (8u) -#define INTC_ICDIPTR146_TINT170_SHIFT (16u) - -#define INTC_ICDICFR0_SW0_0_SHIFT (0u) -#define INTC_ICDICFR0_SW0_1_SHIFT (1u) -#define INTC_ICDICFR0_SW1_0_SHIFT (2u) -#define INTC_ICDICFR0_SW1_1_SHIFT (3u) -#define INTC_ICDICFR0_SW2_0_SHIFT (4u) -#define INTC_ICDICFR0_SW2_1_SHIFT (5u) -#define INTC_ICDICFR0_SW3_0_SHIFT (6u) -#define INTC_ICDICFR0_SW3_1_SHIFT (7u) -#define INTC_ICDICFR0_SW4_0_SHIFT (8u) -#define INTC_ICDICFR0_SW4_1_SHIFT (9u) -#define INTC_ICDICFR0_SW5_0_SHIFT (10u) -#define INTC_ICDICFR0_SW5_1_SHIFT (11u) -#define INTC_ICDICFR0_SW6_0_SHIFT (12u) -#define INTC_ICDICFR0_SW6_1_SHIFT (13u) -#define INTC_ICDICFR0_SW7_0_SHIFT (14u) -#define INTC_ICDICFR0_SW7_1_SHIFT (15u) -#define INTC_ICDICFR0_SW8_0_SHIFT (16u) -#define INTC_ICDICFR0_SW8_1_SHIFT (17u) -#define INTC_ICDICFR0_SW9_0_SHIFT (18u) -#define INTC_ICDICFR0_SW9_1_SHIFT (19u) -#define INTC_ICDICFR0_SW10_0_SHIFT (20u) -#define INTC_ICDICFR0_SW10_1_SHIFT (21u) -#define INTC_ICDICFR0_SW11_0_SHIFT (22u) -#define INTC_ICDICFR0_SW11_1_SHIFT (23u) -#define INTC_ICDICFR0_SW12_0_SHIFT (24u) -#define INTC_ICDICFR0_SW12_1_SHIFT (25u) -#define INTC_ICDICFR0_SW13_0_SHIFT (26u) -#define INTC_ICDICFR0_SW13_1_SHIFT (27u) -#define INTC_ICDICFR0_SW14_0_SHIFT (28u) -#define INTC_ICDICFR0_SW14_1_SHIFT (29u) -#define INTC_ICDICFR0_SW15_0_SHIFT (30u) -#define INTC_ICDICFR0_SW15_1_SHIFT (31u) - -#define INTC_ICDICFR1_PMUIRQ0_0_SHIFT (0u) -#define INTC_ICDICFR1_PMUIRQ0_1_SHIFT (1u) -#define INTC_ICDICFR1_COMMRX0_0_SHIFT (2u) -#define INTC_ICDICFR1_COMMRX0_1_SHIFT (3u) -#define INTC_ICDICFR1_COMMTX0_0_SHIFT (4u) -#define INTC_ICDICFR1_COMMTX0_1_SHIFT (5u) -#define INTC_ICDICFR1_CTIIRQ0_0_SHIFT (6u) -#define INTC_ICDICFR1_CTIIRQ0_1_SHIFT (7u) - -#define INTC_ICDICFR2_IRQ0_0_SHIFT (0u) -#define INTC_ICDICFR2_IRQ0_1_SHIFT (1u) -#define INTC_ICDICFR2_IRQ1_0_SHIFT (2u) -#define INTC_ICDICFR2_IRQ1_1_SHIFT (3u) -#define INTC_ICDICFR2_IRQ2_0_SHIFT (4u) -#define INTC_ICDICFR2_IRQ2_1_SHIFT (5u) -#define INTC_ICDICFR2_IRQ3_0_SHIFT (6u) -#define INTC_ICDICFR2_IRQ3_1_SHIFT (7u) -#define INTC_ICDICFR2_IRQ4_0_SHIFT (8u) -#define INTC_ICDICFR2_IRQ4_1_SHIFT (9u) -#define INTC_ICDICFR2_IRQ5_0_SHIFT (10u) -#define INTC_ICDICFR2_IRQ5_1_SHIFT (11u) -#define INTC_ICDICFR2_IRQ6_0_SHIFT (12u) -#define INTC_ICDICFR2_IRQ6_1_SHIFT (13u) -#define INTC_ICDICFR2_IRQ7_0_SHIFT (14u) -#define INTC_ICDICFR2_IRQ7_1_SHIFT (15u) -#define INTC_ICDICFR2_PL310ERR_0_SHIFT (16u) -#define INTC_ICDICFR2_PL310ERR_1_SHIFT (17u) -#define INTC_ICDICFR2_DMAINT0_0_SHIFT (18u) -#define INTC_ICDICFR2_DMAINT0_1_SHIFT (19u) -#define INTC_ICDICFR2_DMAINT1_0_SHIFT (20u) -#define INTC_ICDICFR2_DMAINT1_1_SHIFT (21u) -#define INTC_ICDICFR2_DMAINT2_0_SHIFT (22u) -#define INTC_ICDICFR2_DMAINT2_1_SHIFT (23u) -#define INTC_ICDICFR2_DMAINT3_0_SHIFT (24u) -#define INTC_ICDICFR2_DMAINT3_1_SHIFT (25u) -#define INTC_ICDICFR2_DMAINT4_0_SHIFT (26u) -#define INTC_ICDICFR2_DMAINT4_1_SHIFT (27u) -#define INTC_ICDICFR2_DMAINT5_0_SHIFT (28u) -#define INTC_ICDICFR2_DMAINT5_1_SHIFT (29u) -#define INTC_ICDICFR2_DMAINT6_0_SHIFT (30u) -#define INTC_ICDICFR2_DMAINT6_1_SHIFT (31u) - -#define INTC_ICDICFR3_DMAINT7_0_SHIFT (0u) -#define INTC_ICDICFR3_DMAINT7_1_SHIFT (1u) -#define INTC_ICDICFR3_DMAINT8_0_SHIFT (2u) -#define INTC_ICDICFR3_DMAINT8_1_SHIFT (3u) -#define INTC_ICDICFR3_DMAINT9_0_SHIFT (4u) -#define INTC_ICDICFR3_DMAINT9_1_SHIFT (5u) -#define INTC_ICDICFR3_DMAINT10_0_SHIFT (6u) -#define INTC_ICDICFR3_DMAINT10_1_SHIFT (7u) -#define INTC_ICDICFR3_DMAINT11_0_SHIFT (8u) -#define INTC_ICDICFR3_DMAINT11_1_SHIFT (9u) -#define INTC_ICDICFR3_DMAINT12_0_SHIFT (10u) -#define INTC_ICDICFR3_DMAINT12_1_SHIFT (11u) -#define INTC_ICDICFR3_DMAINT13_0_SHIFT (12u) -#define INTC_ICDICFR3_DMAINT13_1_SHIFT (13u) -#define INTC_ICDICFR3_DMAINT14_0_SHIFT (14u) -#define INTC_ICDICFR3_DMAINT14_1_SHIFT (15u) -#define INTC_ICDICFR3_DMAINT15_0_SHIFT (16u) -#define INTC_ICDICFR3_DMAINT15_1_SHIFT (17u) -#define INTC_ICDICFR3_DMAERR_0_SHIFT (18u) -#define INTC_ICDICFR3_DMAERR_1_SHIFT (19u) - -#define INTC_ICDICFR4_USBI0_0_SHIFT (18u) -#define INTC_ICDICFR4_USBI0_1_SHIFT (19u) -#define INTC_ICDICFR4_USBI1_0_SHIFT (20u) -#define INTC_ICDICFR4_USBI1_1_SHIFT (21u) -#define INTC_ICDICFR4_S0_VI_VSYNC0_0_SHIFT (22u) -#define INTC_ICDICFR4_S0_VI_VSYNC0_1_SHIFT (23u) -#define INTC_ICDICFR4_S0_LO_VSYNC0_0_SHIFT (24u) -#define INTC_ICDICFR4_S0_LO_VSYNC0_1_SHIFT (25u) -#define INTC_ICDICFR4_S0_VSYNCERR0_0_SHIFT (26u) -#define INTC_ICDICFR4_S0_VSYNCERR0_1_SHIFT (27u) -#define INTC_ICDICFR4_GR3_VLINE0_0_SHIFT (28u) -#define INTC_ICDICFR4_GR3_VLINE0_1_SHIFT (29u) -#define INTC_ICDICFR4_S0_VFIELD0_0_SHIFT (30u) -#define INTC_ICDICFR4_S0_VFIELD0_1_SHIFT (31u) - -#define INTC_ICDICFR5_IV1_VBUFERR0_0_SHIFT (0u) -#define INTC_ICDICFR5_IV1_VBUFERR0_1_SHIFT (1u) -#define INTC_ICDICFR5_IV3_VBUFERR0_0_SHIFT (2u) -#define INTC_ICDICFR5_IV3_VBUFERR0_1_SHIFT (3u) -#define INTC_ICDICFR5_IV5_VBUFERR0_0_SHIFT (4u) -#define INTC_ICDICFR5_IV5_VBUFERR0_1_SHIFT (5u) -#define INTC_ICDICFR5_IV6_VBUFERR0_0_SHIFT (6u) -#define INTC_ICDICFR5_IV6_VBUFERR0_1_SHIFT (7u) -#define INTC_ICDICFR5_S0_WLINE0_0_SHIFT (8u) -#define INTC_ICDICFR5_S0_WLINE0_1_SHIFT (9u) -#define INTC_ICDICFR5_S1_VI_VSYNC0_0_SHIFT (10u) -#define INTC_ICDICFR5_S1_VI_VSYNC0_1_SHIFT (11u) -#define INTC_ICDICFR5_S1_LO_VSYNC0_0_SHIFT (12u) -#define INTC_ICDICFR5_S1_LO_VSYNC0_1_SHIFT (13u) -#define INTC_ICDICFR5_S1_VSYNCERR0_0_SHIFT (14u) -#define INTC_ICDICFR5_S1_VSYNCERR0_1_SHIFT (15u) -#define INTC_ICDICFR5_S1_VFIELD0_0_SHIFT (16u) -#define INTC_ICDICFR5_S1_VFIELD0_1_SHIFT (17u) -#define INTC_ICDICFR5_IV2_VBUFERR0_0_SHIFT (18u) -#define INTC_ICDICFR5_IV2_VBUFERR0_1_SHIFT (19u) -#define INTC_ICDICFR5_IV4_VBUFERR0_0_SHIFT (20u) -#define INTC_ICDICFR5_IV4_VBUFERR0_1_SHIFT (21u) -#define INTC_ICDICFR5_S1_WLINE0_0_SHIFT (22u) -#define INTC_ICDICFR5_S1_WLINE0_1_SHIFT (23u) -#define INTC_ICDICFR5_OIR_VI_VSYNC0_0_SHIFT (24u) -#define INTC_ICDICFR5_OIR_VI_VSYNC0_1_SHIFT (25u) -#define INTC_ICDICFR5_OIR_LO_VSYNC0_0_SHIFT (26u) -#define INTC_ICDICFR5_OIR_LO_VSYNC0_1_SHIFT (27u) -#define INTC_ICDICFR5_OIR_VSYNCERR0_0_SHIFT (28u) -#define INTC_ICDICFR5_OIR_VSYNCERR0_1_SHIFT (29u) -#define INTC_ICDICFR5_OIR_VFIELD0_0_SHIFT (30u) -#define INTC_ICDICFR5_OIR_VFIELD0_1_SHIFT (31u) - -#define INTC_ICDICFR6_IV7_VBUFERR0_0_SHIFT (0u) -#define INTC_ICDICFR6_IV7_VBUFERR0_1_SHIFT (1u) -#define INTC_ICDICFR6_IV8_VBUFERR0_0_SHIFT (2u) -#define INTC_ICDICFR6_IV8_VBUFERR0_1_SHIFT (3u) -#define INTC_ICDICFR6_S0_VI_VSYNC1_0_SHIFT (6u) -#define INTC_ICDICFR6_S0_VI_VSYNC1_1_SHIFT (7u) -#define INTC_ICDICFR6_S0_LO_VSYNC1_0_SHIFT (8u) -#define INTC_ICDICFR6_S0_LO_VSYNC1_1_SHIFT (9u) -#define INTC_ICDICFR6_S0_VSYNCERR1_0_SHIFT (10u) -#define INTC_ICDICFR6_S0_VSYNCERR1_1_SHIFT (11u) -#define INTC_ICDICFR6_GR3_VLINE1_0_SHIFT (12u) -#define INTC_ICDICFR6_GR3_VLINE1_1_SHIFT (13u) -#define INTC_ICDICFR6_S0_VFIELD1_0_SHIFT (14u) -#define INTC_ICDICFR6_S0_VFIELD1_1_SHIFT (15u) -#define INTC_ICDICFR6_IV1_VBUFERR1_0_SHIFT (16u) -#define INTC_ICDICFR6_IV1_VBUFERR1_1_SHIFT (17u) -#define INTC_ICDICFR6_IV3_VBUFERR1_0_SHIFT (18u) -#define INTC_ICDICFR6_IV3_VBUFERR1_1_SHIFT (19u) -#define INTC_ICDICFR6_IV5_VBUFERR1_0_SHIFT (20u) -#define INTC_ICDICFR6_IV5_VBUFERR1_1_SHIFT (21u) -#define INTC_ICDICFR6_IV6_VBUFERR1_0_SHIFT (22u) -#define INTC_ICDICFR6_IV6_VBUFERR1_1_SHIFT (23u) -#define INTC_ICDICFR6_S0_WLINE1_0_SHIFT (24u) -#define INTC_ICDICFR6_S0_WLINE1_1_SHIFT (25u) -#define INTC_ICDICFR6_S1_VI_VSYNC1_0_SHIFT (26u) -#define INTC_ICDICFR6_S1_VI_VSYNC1_1_SHIFT (27u) -#define INTC_ICDICFR6_S1_LO_VSYNC1_0_SHIFT (28u) -#define INTC_ICDICFR6_S1_LO_VSYNC1_1_SHIFT (29u) -#define INTC_ICDICFR6_S1_VSYNCERR1_0_SHIFT (30u) -#define INTC_ICDICFR6_S1_VSYNCERR1_1_SHIFT (31u) - -#define INTC_ICDICFR7_S1_VFIELD1_0_SHIFT (0u) -#define INTC_ICDICFR7_S1_VFIELD1_1_SHIFT (1u) -#define INTC_ICDICFR7_IV2_VBUFERR1_0_SHIFT (2u) -#define INTC_ICDICFR7_IV2_VBUFERR1_1_SHIFT (3u) -#define INTC_ICDICFR7_IV4_VBUFERR1_0_SHIFT (4u) -#define INTC_ICDICFR7_IV4_VBUFERR1_1_SHIFT (5u) -#define INTC_ICDICFR7_S1_WLINE1_0_SHIFT (6u) -#define INTC_ICDICFR7_S1_WLINE1_1_SHIFT (7u) -#define INTC_ICDICFR7_OIR_VI_VSYNC1_0_SHIFT (8u) -#define INTC_ICDICFR7_OIR_VI_VSYNC1_1_SHIFT (9u) -#define INTC_ICDICFR7_OIR_LO_VSYNC1_0_SHIFT (10u) -#define INTC_ICDICFR7_OIR_LO_VSYNC1_1_SHIFT (11u) -#define INTC_ICDICFR7_OIR_VLINE1_0_SHIFT (12u) -#define INTC_ICDICFR7_OIR_VLINE1_1_SHIFT (13u) -#define INTC_ICDICFR7_OIR_VFIELD1_0_SHIFT (14u) -#define INTC_ICDICFR7_OIR_VFIELD1_1_SHIFT (15u) -#define INTC_ICDICFR7_IV7_VBUFERR1_0_SHIFT (16u) -#define INTC_ICDICFR7_IV7_VBUFERR1_1_SHIFT (17u) -#define INTC_ICDICFR7_IV8_VBUFERR1_0_SHIFT (18u) -#define INTC_ICDICFR7_IV8_VBUFERR1_1_SHIFT (19u) -#define INTC_ICDICFR7_IMRDI_0_SHIFT (22u) -#define INTC_ICDICFR7_IMRDI_1_SHIFT (23u) -#define INTC_ICDICFR7_IMR2I0_0_SHIFT (24u) -#define INTC_ICDICFR7_IMR2I0_1_SHIFT (25u) -#define INTC_ICDICFR7_IMR2I1_0_SHIFT (26u) -#define INTC_ICDICFR7_IMR2I1_1_SHIFT (27u) -#define INTC_ICDICFR7_JEDI_0_SHIFT (28u) -#define INTC_ICDICFR7_JEDI_1_SHIFT (29u) -#define INTC_ICDICFR7_JDTI_0_SHIFT (30u) -#define INTC_ICDICFR7_JDTI_1_SHIFT (31u) - -#define INTC_ICDICFR8_CMP0_0_SHIFT (0u) -#define INTC_ICDICFR8_CMP0_1_SHIFT (1u) -#define INTC_ICDICFR8_CMP1_0_SHIFT (2u) -#define INTC_ICDICFR8_CMP1_1_SHIFT (3u) -#define INTC_ICDICFR8_INT0_0_SHIFT (4u) -#define INTC_ICDICFR8_INT0_1_SHIFT (5u) -#define INTC_ICDICFR8_INT1_0_SHIFT (6u) -#define INTC_ICDICFR8_INT1_1_SHIFT (7u) -#define INTC_ICDICFR8_INT2_0_SHIFT (8u) -#define INTC_ICDICFR8_INT2_1_SHIFT (9u) -#define INTC_ICDICFR8_INT3_0_SHIFT (10u) -#define INTC_ICDICFR8_INT3_1_SHIFT (11u) -#define INTC_ICDICFR8_OSTM0TINT_0_SHIFT (12u) -#define INTC_ICDICFR8_OSTM0TINT_1_SHIFT (13u) -#define INTC_ICDICFR8_OSTM1TINT_0_SHIFT (14u) -#define INTC_ICDICFR8_OSTM1TINT_1_SHIFT (15u) -#define INTC_ICDICFR8_CMI_0_SHIFT (16u) -#define INTC_ICDICFR8_CMI_1_SHIFT (17u) -#define INTC_ICDICFR8_WTOUT_0_SHIFT (18u) -#define INTC_ICDICFR8_WTOUT_1_SHIFT (19u) -#define INTC_ICDICFR8_ITI_0_SHIFT (20u) -#define INTC_ICDICFR8_ITI_1_SHIFT (21u) -#define INTC_ICDICFR8_TGI0A_0_SHIFT (22u) -#define INTC_ICDICFR8_TGI0A_1_SHIFT (23u) -#define INTC_ICDICFR8_TGI0B_0_SHIFT (24u) -#define INTC_ICDICFR8_TGI0B_1_SHIFT (25u) -#define INTC_ICDICFR8_TGI0C_0_SHIFT (26u) -#define INTC_ICDICFR8_TGI0C_1_SHIFT (27u) -#define INTC_ICDICFR8_TGI0D_0_SHIFT (28u) -#define INTC_ICDICFR8_TGI0D_1_SHIFT (29u) -#define INTC_ICDICFR8_TGI0V_0_SHIFT (30u) -#define INTC_ICDICFR8_TGI0V_1_SHIFT (31u) - -#define INTC_ICDICFR9_TGI0E_0_SHIFT (0u) -#define INTC_ICDICFR9_TGI0E_1_SHIFT (1u) -#define INTC_ICDICFR9_TGI0F_0_SHIFT (2u) -#define INTC_ICDICFR9_TGI0F_1_SHIFT (3u) -#define INTC_ICDICFR9_TGI1A_0_SHIFT (4u) -#define INTC_ICDICFR9_TGI1A_1_SHIFT (5u) -#define INTC_ICDICFR9_TGI1B_0_SHIFT (6u) -#define INTC_ICDICFR9_TGI1B_1_SHIFT (7u) -#define INTC_ICDICFR9_TGI1V_0_SHIFT (8u) -#define INTC_ICDICFR9_TGI1V_1_SHIFT (9u) -#define INTC_ICDICFR9_TGI1U_0_SHIFT (10u) -#define INTC_ICDICFR9_TGI1U_1_SHIFT (11u) -#define INTC_ICDICFR9_TGI2A_0_SHIFT (12u) -#define INTC_ICDICFR9_TGI2A_1_SHIFT (13u) -#define INTC_ICDICFR9_TGI2B_0_SHIFT (14u) -#define INTC_ICDICFR9_TGI2B_1_SHIFT (15u) -#define INTC_ICDICFR9_TGI2V_0_SHIFT (16u) -#define INTC_ICDICFR9_TGI2V_1_SHIFT (17u) -#define INTC_ICDICFR9_TGI2U_0_SHIFT (18u) -#define INTC_ICDICFR9_TGI2U_1_SHIFT (19u) -#define INTC_ICDICFR9_TGI3A_0_SHIFT (20u) -#define INTC_ICDICFR9_TGI3A_1_SHIFT (21u) -#define INTC_ICDICFR9_TGI3B_0_SHIFT (22u) -#define INTC_ICDICFR9_TGI3B_1_SHIFT (23u) -#define INTC_ICDICFR9_TGI3C_0_SHIFT (24u) -#define INTC_ICDICFR9_TGI3C_1_SHIFT (25u) -#define INTC_ICDICFR9_TGI3D_0_SHIFT (26u) -#define INTC_ICDICFR9_TGI3D_1_SHIFT (27u) -#define INTC_ICDICFR9_TGI3V_0_SHIFT (28u) -#define INTC_ICDICFR9_TGI3V_1_SHIFT (29u) -#define INTC_ICDICFR9_TGI4A_0_SHIFT (30u) -#define INTC_ICDICFR9_TGI4A_1_SHIFT (31u) - -#define INTC_ICDICFR10_TGI4B_0_SHIFT (0u) -#define INTC_ICDICFR10_TGI4B_1_SHIFT (1u) -#define INTC_ICDICFR10_TGI4C_0_SHIFT (2u) -#define INTC_ICDICFR10_TGI4C_1_SHIFT (3u) -#define INTC_ICDICFR10_TGI4D_0_SHIFT (4u) -#define INTC_ICDICFR10_TGI4D_1_SHIFT (5u) -#define INTC_ICDICFR10_TGI4V_0_SHIFT (6u) -#define INTC_ICDICFR10_TGI4V_1_SHIFT (7u) -#define INTC_ICDICFR10_CMI1_0_SHIFT (8u) -#define INTC_ICDICFR10_CMI1_1_SHIFT (9u) -#define INTC_ICDICFR10_CMI2_0_SHIFT (10u) -#define INTC_ICDICFR10_CMI2_1_SHIFT (11u) -#define INTC_ICDICFR10_SGDEI0_0_SHIFT (12u) -#define INTC_ICDICFR10_SGDEI0_1_SHIFT (13u) -#define INTC_ICDICFR10_SGDEI1_0_SHIFT (14u) -#define INTC_ICDICFR10_SGDEI1_1_SHIFT (15u) -#define INTC_ICDICFR10_SGDEI2_0_SHIFT (16u) -#define INTC_ICDICFR10_SGDEI2_1_SHIFT (17u) -#define INTC_ICDICFR10_SGDEI3_0_SHIFT (18u) -#define INTC_ICDICFR10_SGDEI3_1_SHIFT (19u) -#define INTC_ICDICFR10_ADI_0_SHIFT (20u) -#define INTC_ICDICFR10_ADI_1_SHIFT (21u) -#define INTC_ICDICFR10_LMTI_0_SHIFT (22u) -#define INTC_ICDICFR10_LMTI_1_SHIFT (23u) -#define INTC_ICDICFR10_SSII0_0_SHIFT (24u) -#define INTC_ICDICFR10_SSII0_1_SHIFT (25u) -#define INTC_ICDICFR10_SSIRXI0_0_SHIFT (26u) -#define INTC_ICDICFR10_SSIRXI0_1_SHIFT (27u) -#define INTC_ICDICFR10_SSITXI0_0_SHIFT (28u) -#define INTC_ICDICFR10_SSITXI0_1_SHIFT (29u) -#define INTC_ICDICFR10_SSII1_0_SHIFT (30u) -#define INTC_ICDICFR10_SSII1_1_SHIFT (31u) - -#define INTC_ICDICFR11_SSIRXI1_0_SHIFT (0u) -#define INTC_ICDICFR11_SSIRXI1_1_SHIFT (1u) -#define INTC_ICDICFR11_SSITXI1_0_SHIFT (2u) -#define INTC_ICDICFR11_SSITXI1_1_SHIFT (3u) -#define INTC_ICDICFR11_SSII2_0_SHIFT (4u) -#define INTC_ICDICFR11_SSII2_1_SHIFT (5u) -#define INTC_ICDICFR11_SSIRTI2_0_SHIFT (6u) -#define INTC_ICDICFR11_SSIRTI2_1_SHIFT (7u) -#define INTC_ICDICFR11_SSII3_0_SHIFT (8u) -#define INTC_ICDICFR11_SSII3_1_SHIFT (9u) -#define INTC_ICDICFR11_SSIRXI3_0_SHIFT (10u) -#define INTC_ICDICFR11_SSIRXI3_1_SHIFT (11u) -#define INTC_ICDICFR11_SSITXI3_0_SHIFT (12u) -#define INTC_ICDICFR11_SSITXI3_1_SHIFT (13u) -#define INTC_ICDICFR11_SSII4_0_SHIFT (14u) -#define INTC_ICDICFR11_SSII4_1_SHIFT (15u) -#define INTC_ICDICFR11_SSIRTI4_0_SHIFT (16u) -#define INTC_ICDICFR11_SSIRTI4_1_SHIFT (17u) -#define INTC_ICDICFR11_SSII5_0_SHIFT (18u) -#define INTC_ICDICFR11_SSII5_1_SHIFT (19u) -#define INTC_ICDICFR11_SSIRXI5_0_SHIFT (20u) -#define INTC_ICDICFR11_SSIRXI5_1_SHIFT (21u) -#define INTC_ICDICFR11_SSITXI5_0_SHIFT (22u) -#define INTC_ICDICFR11_SSITXI5_1_SHIFT (23u) -#define INTC_ICDICFR11_SPDIFI_0_SHIFT (24u) -#define INTC_ICDICFR11_SPDIFI_1_SHIFT (25u) -#define INTC_ICDICFR11_INTIICTEI0_0_SHIFT (26u) -#define INTC_ICDICFR11_INTIICTEI0_1_SHIFT (27u) -#define INTC_ICDICFR11_INTIICRI0_0_SHIFT (28u) -#define INTC_ICDICFR11_INTIICRI0_1_SHIFT (29u) -#define INTC_ICDICFR11_INTIICTI0_0_SHIFT (30u) -#define INTC_ICDICFR11_INTIICTI0_1_SHIFT (31u) - -#define INTC_ICDICFR12_INTIICSPI0_0_SHIFT (0u) -#define INTC_ICDICFR12_INTIICSPI0_1_SHIFT (1u) -#define INTC_ICDICFR12_INTIICSTI0_0_SHIFT (2u) -#define INTC_ICDICFR12_INTIICSTI0_1_SHIFT (3u) -#define INTC_ICDICFR12_INTIICNAKI0_0_SHIFT (4u) -#define INTC_ICDICFR12_INTIICNAKI0_1_SHIFT (5u) -#define INTC_ICDICFR12_INTIICALI0_0_SHIFT (6u) -#define INTC_ICDICFR12_INTIICALI0_1_SHIFT (7u) -#define INTC_ICDICFR12_INTIICTMOI0_0_SHIFT (8u) -#define INTC_ICDICFR12_INTIICTMOI0_1_SHIFT (9u) -#define INTC_ICDICFR12_INTIICTEI1_0_SHIFT (10u) -#define INTC_ICDICFR12_INTIICTEI1_1_SHIFT (11u) -#define INTC_ICDICFR12_INTIICRI1_0_SHIFT (12u) -#define INTC_ICDICFR12_INTIICRI1_1_SHIFT (13u) -#define INTC_ICDICFR12_INTIICTI1_0_SHIFT (14u) -#define INTC_ICDICFR12_INTIICTI1_1_SHIFT (15u) -#define INTC_ICDICFR12_INTIICSPI1_0_SHIFT (16u) -#define INTC_ICDICFR12_INTIICSPI1_1_SHIFT (17u) -#define INTC_ICDICFR12_INTIICSTI1_0_SHIFT (18u) -#define INTC_ICDICFR12_INTIICSTI1_1_SHIFT (19u) -#define INTC_ICDICFR12_INTIICNAKI1_0_SHIFT (20u) -#define INTC_ICDICFR12_INTIICNAKI1_1_SHIFT (21u) -#define INTC_ICDICFR12_INTIICALI1_0_SHIFT (22u) -#define INTC_ICDICFR12_INTIICALI1_1_SHIFT (23u) -#define INTC_ICDICFR12_INTIICTMOI1_0_SHIFT (24u) -#define INTC_ICDICFR12_INTIICTMOI1_1_SHIFT (25u) -#define INTC_ICDICFR12_INTIICTEI2_0_SHIFT (26u) -#define INTC_ICDICFR12_INTIICTEI2_1_SHIFT (27u) -#define INTC_ICDICFR12_INTIICRI2_0_SHIFT (28u) -#define INTC_ICDICFR12_INTIICRI2_1_SHIFT (29u) -#define INTC_ICDICFR12_INTIICTI2_0_SHIFT (30u) -#define INTC_ICDICFR12_INTIICTI2_1_SHIFT (31u) - -#define INTC_ICDICFR13_INTIICSPI2_0_SHIFT (0u) -#define INTC_ICDICFR13_INTIICSPI2_1_SHIFT (1u) -#define INTC_ICDICFR13_INTIICSTI2_0_SHIFT (2u) -#define INTC_ICDICFR13_INTIICSTI2_1_SHIFT (3u) -#define INTC_ICDICFR13_INTIICNAKI2_0_SHIFT (4u) -#define INTC_ICDICFR13_INTIICNAKI2_1_SHIFT (5u) -#define INTC_ICDICFR13_INTIICALI2_0_SHIFT (6u) -#define INTC_ICDICFR13_INTIICALI2_1_SHIFT (7u) -#define INTC_ICDICFR13_INTIICTMOI2_0_SHIFT (8u) -#define INTC_ICDICFR13_INTIICTMOI2_1_SHIFT (9u) -#define INTC_ICDICFR13_INTIICTEI3_0_SHIFT (10u) -#define INTC_ICDICFR13_INTIICTEI3_1_SHIFT (11u) -#define INTC_ICDICFR13_INTIICRI3_0_SHIFT (12u) -#define INTC_ICDICFR13_INTIICRI3_1_SHIFT (13u) -#define INTC_ICDICFR13_INTIICTI3_0_SHIFT (14u) -#define INTC_ICDICFR13_INTIICTI3_1_SHIFT (15u) -#define INTC_ICDICFR13_INTIICSPI3_0_SHIFT (16u) -#define INTC_ICDICFR13_INTIICSPI3_1_SHIFT (17u) -#define INTC_ICDICFR13_INTIICSTI3_0_SHIFT (18u) -#define INTC_ICDICFR13_INTIICSTI3_1_SHIFT (19u) -#define INTC_ICDICFR13_INTIICNAKI3_0_SHIFT (20u) -#define INTC_ICDICFR13_INTIICNAKI3_1_SHIFT (21u) -#define INTC_ICDICFR13_INTIICALI3_0_SHIFT (22u) -#define INTC_ICDICFR13_INTIICALI3_1_SHIFT (23u) -#define INTC_ICDICFR13_INTIICTMOI3_0_SHIFT (24u) -#define INTC_ICDICFR13_INTIICTMOI3_1_SHIFT (25u) -#define INTC_ICDICFR13_BRI0_0_SHIFT (26u) -#define INTC_ICDICFR13_BRI0_1_SHIFT (27u) -#define INTC_ICDICFR13_ERI0_0_SHIFT (28u) -#define INTC_ICDICFR13_ERI0_1_SHIFT (29u) -#define INTC_ICDICFR13_RXI0_0_SHIFT (30u) -#define INTC_ICDICFR13_RXI0_1_SHIFT (31u) - -#define INTC_ICDICFR14_TXI0_0_SHIFT (0u) -#define INTC_ICDICFR14_TXI0_1_SHIFT (1u) -#define INTC_ICDICFR14_BRI1_0_SHIFT (2u) -#define INTC_ICDICFR14_BRI1_1_SHIFT (3u) -#define INTC_ICDICFR14_ERI1_0_SHIFT (4u) -#define INTC_ICDICFR14_ERI1_1_SHIFT (5u) -#define INTC_ICDICFR14_RXI1_0_SHIFT (6u) -#define INTC_ICDICFR14_RXI1_1_SHIFT (7u) -#define INTC_ICDICFR14_TXI1_0_SHIFT (8u) -#define INTC_ICDICFR14_TXI1_1_SHIFT (9u) -#define INTC_ICDICFR14_BRI2_0_SHIFT (10u) -#define INTC_ICDICFR14_BRI2_1_SHIFT (11u) -#define INTC_ICDICFR14_ERI2_0_SHIFT (12u) -#define INTC_ICDICFR14_ERI2_1_SHIFT (13u) -#define INTC_ICDICFR14_RXI2_0_SHIFT (14u) -#define INTC_ICDICFR14_RXI2_1_SHIFT (15u) -#define INTC_ICDICFR14_TXI2_0_SHIFT (16u) -#define INTC_ICDICFR14_TXI2_1_SHIFT (17u) -#define INTC_ICDICFR14_BRI3_0_SHIFT (18u) -#define INTC_ICDICFR14_BRI3_1_SHIFT (19u) -#define INTC_ICDICFR14_ERI3_0_SHIFT (20u) -#define INTC_ICDICFR14_ERI3_1_SHIFT (21u) -#define INTC_ICDICFR14_RXI3_0_SHIFT (22u) -#define INTC_ICDICFR14_RXI3_1_SHIFT (23u) -#define INTC_ICDICFR14_TXI3_0_SHIFT (24u) -#define INTC_ICDICFR14_TXI3_1_SHIFT (25u) -#define INTC_ICDICFR14_BRI4_0_SHIFT (26u) -#define INTC_ICDICFR14_BRI4_1_SHIFT (27u) -#define INTC_ICDICFR14_ERI4_0_SHIFT (28u) -#define INTC_ICDICFR14_ERI4_1_SHIFT (29u) -#define INTC_ICDICFR14_RXI4_0_SHIFT (30u) -#define INTC_ICDICFR14_RXI4_1_SHIFT (31u) - -#define INTC_ICDICFR15_TXI4_0_SHIFT (0u) -#define INTC_ICDICFR15_TXI4_1_SHIFT (1u) -#define INTC_ICDICFR15_BRI5_0_SHIFT (2u) -#define INTC_ICDICFR15_BRI5_1_SHIFT (3u) -#define INTC_ICDICFR15_ERI5_0_SHIFT (4u) -#define INTC_ICDICFR15_ERI5_1_SHIFT (5u) -#define INTC_ICDICFR15_RXI5_0_SHIFT (6u) -#define INTC_ICDICFR15_RXI5_1_SHIFT (7u) -#define INTC_ICDICFR15_TXI5_0_SHIFT (8u) -#define INTC_ICDICFR15_TXI5_1_SHIFT (9u) -#define INTC_ICDICFR15_BRI6_0_SHIFT (10u) -#define INTC_ICDICFR15_BRI6_1_SHIFT (11u) -#define INTC_ICDICFR15_ERI6_0_SHIFT (12u) -#define INTC_ICDICFR15_ERI6_1_SHIFT (13u) -#define INTC_ICDICFR15_RXI6_0_SHIFT (14u) -#define INTC_ICDICFR15_RXI6_1_SHIFT (15u) -#define INTC_ICDICFR15_TXI6_0_SHIFT (16u) -#define INTC_ICDICFR15_TXI6_1_SHIFT (17u) -#define INTC_ICDICFR15_BRI7_0_SHIFT (18u) -#define INTC_ICDICFR15_BRI7_1_SHIFT (19u) -#define INTC_ICDICFR15_ERI7_0_SHIFT (20u) -#define INTC_ICDICFR15_ERI7_1_SHIFT (21u) -#define INTC_ICDICFR15_RXI7_0_SHIFT (22u) -#define INTC_ICDICFR15_RXI7_1_SHIFT (23u) -#define INTC_ICDICFR15_TXI7_0_SHIFT (24u) -#define INTC_ICDICFR15_TXI7_1_SHIFT (25u) -#define INTC_ICDICFR15_INTRCANGERR_0_SHIFT (26u) -#define INTC_ICDICFR15_INTRCANGERR_1_SHIFT (27u) -#define INTC_ICDICFR15_INTRCANGRECC_0_SHIFT (28u) -#define INTC_ICDICFR15_INTRCANGRECC_1_SHIFT (29u) -#define INTC_ICDICFR15_INTRCAN0REC_0_SHIFT (30u) -#define INTC_ICDICFR15_INTRCAN0REC_1_SHIFT (31u) - -#define INTC_ICDICFR16_INTRCAN0ERR_0_SHIFT (0u) -#define INTC_ICDICFR16_INTRCAN0ERR_1_SHIFT (1u) -#define INTC_ICDICFR16_INTRCAN0TRX_0_SHIFT (2u) -#define INTC_ICDICFR16_INTRCAN0TRX_1_SHIFT (3u) -#define INTC_ICDICFR16_INTRCAN1REC_0_SHIFT (4u) -#define INTC_ICDICFR16_INTRCAN1REC_1_SHIFT (5u) -#define INTC_ICDICFR16_INTRCAN1ERR_0_SHIFT (6u) -#define INTC_ICDICFR16_INTRCAN1ERR_1_SHIFT (7u) -#define INTC_ICDICFR16_INTRCAN1TRX_0_SHIFT (8u) -#define INTC_ICDICFR16_INTRCAN1TRX_1_SHIFT (9u) -#define INTC_ICDICFR16_INTRCAN2REC_0_SHIFT (10u) -#define INTC_ICDICFR16_INTRCAN2REC_1_SHIFT (11u) -#define INTC_ICDICFR16_INTRCAN2ERR_0_SHIFT (12u) -#define INTC_ICDICFR16_INTRCAN2ERR_1_SHIFT (13u) -#define INTC_ICDICFR16_INTRCAN2TRX_0_SHIFT (14u) -#define INTC_ICDICFR16_INTRCAN2TRX_1_SHIFT (15u) -#define INTC_ICDICFR16_INTRCAN3REC_0_SHIFT (16u) -#define INTC_ICDICFR16_INTRCAN3REC_1_SHIFT (17u) -#define INTC_ICDICFR16_INTRCAN3ERR_0_SHIFT (18u) -#define INTC_ICDICFR16_INTRCAN3ERR_1_SHIFT (19u) -#define INTC_ICDICFR16_INTRCAN3TRX_0_SHIFT (20u) -#define INTC_ICDICFR16_INTRCAN3TRX_1_SHIFT (21u) -#define INTC_ICDICFR16_INTRCAN4REC_0_SHIFT (22u) -#define INTC_ICDICFR16_INTRCAN4REC_1_SHIFT (23u) -#define INTC_ICDICFR16_INTRCAN4ERR_0_SHIFT (24u) -#define INTC_ICDICFR16_INTRCAN4ERR_1_SHIFT (25u) -#define INTC_ICDICFR16_INTRCAN4TRX_0_SHIFT (26u) -#define INTC_ICDICFR16_INTRCAN4TRX_1_SHIFT (27u) -#define INTC_ICDICFR16_SPEI0_0_SHIFT (28u) -#define INTC_ICDICFR16_SPEI0_1_SHIFT (29u) -#define INTC_ICDICFR16_SPRI0_0_SHIFT (30u) -#define INTC_ICDICFR16_SPRI0_1_SHIFT (31u) - -#define INTC_ICDICFR17_SPTI0_0_SHIFT (0u) -#define INTC_ICDICFR17_SPTI0_1_SHIFT (1u) -#define INTC_ICDICFR17_SPEI1_0_SHIFT (2u) -#define INTC_ICDICFR17_SPEI1_1_SHIFT (3u) -#define INTC_ICDICFR17_SPRI1_0_SHIFT (4u) -#define INTC_ICDICFR17_SPRI1_1_SHIFT (5u) -#define INTC_ICDICFR17_SPTI1_0_SHIFT (6u) -#define INTC_ICDICFR17_SPTI1_1_SHIFT (7u) -#define INTC_ICDICFR17_SPEI2_0_SHIFT (8u) -#define INTC_ICDICFR17_SPEI2_1_SHIFT (9u) -#define INTC_ICDICFR17_SPRI2_0_SHIFT (10u) -#define INTC_ICDICFR17_SPRI2_1_SHIFT (11u) -#define INTC_ICDICFR17_SPTI2_0_SHIFT (12u) -#define INTC_ICDICFR17_SPTI2_1_SHIFT (13u) -#define INTC_ICDICFR17_SPEI3_0_SHIFT (14u) -#define INTC_ICDICFR17_SPEI3_1_SHIFT (15u) -#define INTC_ICDICFR17_SPRI3_0_SHIFT (16u) -#define INTC_ICDICFR17_SPRI3_1_SHIFT (17u) -#define INTC_ICDICFR17_SPTI3_0_SHIFT (18u) -#define INTC_ICDICFR17_SPTI3_1_SHIFT (19u) -#define INTC_ICDICFR17_SPEI4_0_SHIFT (20u) -#define INTC_ICDICFR17_SPEI4_1_SHIFT (21u) -#define INTC_ICDICFR17_SPRI4_0_SHIFT (22u) -#define INTC_ICDICFR17_SPRI4_1_SHIFT (23u) -#define INTC_ICDICFR17_SPTI4_0_SHIFT (24u) -#define INTC_ICDICFR17_SPTI4_1_SHIFT (25u) -#define INTC_ICDICFR17_IEBBTD_0_SHIFT (26u) -#define INTC_ICDICFR17_IEBBTD_1_SHIFT (27u) -#define INTC_ICDICFR17_IEBBTERR_0_SHIFT (28u) -#define INTC_ICDICFR17_IEBBTERR_1_SHIFT (29u) -#define INTC_ICDICFR17_IEBBTSTA_0_SHIFT (30u) -#define INTC_ICDICFR17_IEBBTSTA_1_SHIFT (31u) - -#define INTC_ICDICFR18_IEBBTV_0_SHIFT (0u) -#define INTC_ICDICFR18_IEBBTV_1_SHIFT (1u) -#define INTC_ICDICFR18_ISY_0_SHIFT (2u) -#define INTC_ICDICFR18_ISY_1_SHIFT (3u) -#define INTC_ICDICFR18_IERR_0_SHIFT (4u) -#define INTC_ICDICFR18_IERR_1_SHIFT (5u) -#define INTC_ICDICFR18_ITARG_0_SHIFT (6u) -#define INTC_ICDICFR18_ITARG_1_SHIFT (7u) -#define INTC_ICDICFR18_ISEC_0_SHIFT (8u) -#define INTC_ICDICFR18_ISEC_1_SHIFT (9u) -#define INTC_ICDICFR18_IBUF_0_SHIFT (10u) -#define INTC_ICDICFR18_IBUF_1_SHIFT (11u) -#define INTC_ICDICFR18_IREADY_0_SHIFT (12u) -#define INTC_ICDICFR18_IREADY_1_SHIFT (13u) -#define INTC_ICDICFR18_FLSTE_0_SHIFT (14u) -#define INTC_ICDICFR18_FLSTE_1_SHIFT (15u) -#define INTC_ICDICFR18_FLTENDI_0_SHIFT (16u) -#define INTC_ICDICFR18_FLTENDI_1_SHIFT (17u) -#define INTC_ICDICFR18_FLTREQ0I_0_SHIFT (18u) -#define INTC_ICDICFR18_FLTREQ0I_1_SHIFT (19u) -#define INTC_ICDICFR18_FLTREQ1I_0_SHIFT (20u) -#define INTC_ICDICFR18_FLTREQ1I_1_SHIFT (21u) -#define INTC_ICDICFR18_MMC0_0_SHIFT (22u) -#define INTC_ICDICFR18_MMC0_1_SHIFT (23u) -#define INTC_ICDICFR18_MMC1_0_SHIFT (24u) -#define INTC_ICDICFR18_MMC1_1_SHIFT (25u) -#define INTC_ICDICFR18_MMC2_0_SHIFT (26u) -#define INTC_ICDICFR18_MMC2_1_SHIFT (27u) -#define INTC_ICDICFR18_SDHI0_3_0_SHIFT (28u) -#define INTC_ICDICFR18_SDHI0_3_1_SHIFT (29u) -#define INTC_ICDICFR18_SDHI0_0_0_SHIFT (30u) -#define INTC_ICDICFR18_SDHI0_0_1_SHIFT (31u) - -#define INTC_ICDICFR19_SDHI0_1_0_SHIFT (0u) -#define INTC_ICDICFR19_SDHI0_1_1_SHIFT (1u) -#define INTC_ICDICFR19_SDHI1_3_0_SHIFT (2u) -#define INTC_ICDICFR19_SDHI1_3_1_SHIFT (3u) -#define INTC_ICDICFR19_SDHI1_0_0_SHIFT (4u) -#define INTC_ICDICFR19_SDHI1_0_1_SHIFT (5u) -#define INTC_ICDICFR19_SDHI1_1_0_SHIFT (6u) -#define INTC_ICDICFR19_SDHI1_1_1_SHIFT (7u) -#define INTC_ICDICFR19_ARM_0_SHIFT (8u) -#define INTC_ICDICFR19_ARM_1_SHIFT (9u) -#define INTC_ICDICFR19_PRD_0_SHIFT (10u) -#define INTC_ICDICFR19_PRD_1_SHIFT (11u) -#define INTC_ICDICFR19_CUP_0_SHIFT (12u) -#define INTC_ICDICFR19_CUP_1_SHIFT (13u) -#define INTC_ICDICFR19_SCUAI0_0_SHIFT (14u) -#define INTC_ICDICFR19_SCUAI0_1_SHIFT (15u) -#define INTC_ICDICFR19_SCUAI1_0_SHIFT (16u) -#define INTC_ICDICFR19_SCUAI1_1_SHIFT (17u) -#define INTC_ICDICFR19_SCUFDI0_0_SHIFT (18u) -#define INTC_ICDICFR19_SCUFDI0_1_SHIFT (19u) -#define INTC_ICDICFR19_SCUFDI1_0_SHIFT (20u) -#define INTC_ICDICFR19_SCUFDI1_1_SHIFT (21u) -#define INTC_ICDICFR19_SCUFDI2_0_SHIFT (22u) -#define INTC_ICDICFR19_SCUFDI2_1_SHIFT (23u) -#define INTC_ICDICFR19_SCUFDI3_0_SHIFT (24u) -#define INTC_ICDICFR19_SCUFDI3_1_SHIFT (25u) -#define INTC_ICDICFR19_SCUFUI0_0_SHIFT (26u) -#define INTC_ICDICFR19_SCUFUI0_1_SHIFT (27u) -#define INTC_ICDICFR19_SCUFUI1_0_SHIFT (28u) -#define INTC_ICDICFR19_SCUFUI1_1_SHIFT (29u) -#define INTC_ICDICFR19_SCUFUI2_0_SHIFT (30u) -#define INTC_ICDICFR19_SCUFUI2_1_SHIFT (31u) - -#define INTC_ICDICFR20_SCUFUI3_0_SHIFT (0u) -#define INTC_ICDICFR20_SCUFUI3_1_SHIFT (1u) -#define INTC_ICDICFR20_SCUDVI0_0_SHIFT (2u) -#define INTC_ICDICFR20_SCUDVI0_1_SHIFT (3u) -#define INTC_ICDICFR20_SCUDVI1_0_SHIFT (4u) -#define INTC_ICDICFR20_SCUDVI1_1_SHIFT (5u) -#define INTC_ICDICFR20_SCUDVI2_0_SHIFT (6u) -#define INTC_ICDICFR20_SCUDVI2_1_SHIFT (7u) -#define INTC_ICDICFR20_SCUDVI3_0_SHIFT (8u) -#define INTC_ICDICFR20_SCUDVI3_1_SHIFT (9u) -#define INTC_ICDICFR20_MLB_CINT_0_SHIFT (10u) -#define INTC_ICDICFR20_MLB_CINT_1_SHIFT (11u) -#define INTC_ICDICFR20_MLB_SINT_0_SHIFT (12u) -#define INTC_ICDICFR20_MLB_SINT_1_SHIFT (13u) -#define INTC_ICDICFR20_DRC0_0_SHIFT (14u) -#define INTC_ICDICFR20_DRC0_1_SHIFT (15u) -#define INTC_ICDICFR20_DRC1_0_SHIFT (16u) -#define INTC_ICDICFR20_DRC1_1_SHIFT (17u) -#define INTC_ICDICFR20_LINI0_INT_T_0_SHIFT (22u) -#define INTC_ICDICFR20_LINI0_INT_T_1_SHIFT (23u) -#define INTC_ICDICFR20_LINI0_INT_R_0_SHIFT (24u) -#define INTC_ICDICFR20_LINI0_INT_R_1_SHIFT (25u) -#define INTC_ICDICFR20_LINI0_INT_S_0_SHIFT (26u) -#define INTC_ICDICFR20_LINI0_INT_S_1_SHIFT (27u) -#define INTC_ICDICFR20_LINI0_INT_M_0_SHIFT (28u) -#define INTC_ICDICFR20_LINI0_INT_M_1_SHIFT (29u) -#define INTC_ICDICFR20_LINI1_INT_T_0_SHIFT (30u) -#define INTC_ICDICFR20_LINI1_INT_T_1_SHIFT (31u) - -#define INTC_ICDICFR21_LINI1_INT_R_0_SHIFT (0u) -#define INTC_ICDICFR21_LINI1_INT_R_1_SHIFT (1u) -#define INTC_ICDICFR21_LINI1_INT_S_0_SHIFT (2u) -#define INTC_ICDICFR21_LINI1_INT_S_1_SHIFT (3u) -#define INTC_ICDICFR21_LINI1_INT_M_0_SHIFT (4u) -#define INTC_ICDICFR21_LINI1_INT_M_1_SHIFT (5u) -#define INTC_ICDICFR21_ERI0_0_SHIFT (22u) -#define INTC_ICDICFR21_ERI0_1_SHIFT (23u) -#define INTC_ICDICFR21_RXI0_0_SHIFT (24u) -#define INTC_ICDICFR21_RXI0_1_SHIFT (25u) -#define INTC_ICDICFR21_TXI0_0_SHIFT (26u) -#define INTC_ICDICFR21_TXI0_1_SHIFT (27u) -#define INTC_ICDICFR21_TEI0_0_SHIFT (28u) -#define INTC_ICDICFR21_TEI0_1_SHIFT (29u) -#define INTC_ICDICFR21_ERI1_0_SHIFT (30u) -#define INTC_ICDICFR21_ERI1_1_SHIFT (31u) - -#define INTC_ICDICFR22_RXI1_0_SHIFT (0u) -#define INTC_ICDICFR22_RXI1_1_SHIFT (1u) -#define INTC_ICDICFR22_TXI1_0_SHIFT (2u) -#define INTC_ICDICFR22_TXI1_1_SHIFT (3u) -#define INTC_ICDICFR22_TEI1_0_SHIFT (4u) -#define INTC_ICDICFR22_TEI1_1_SHIFT (5u) -#define INTC_ICDICFR22_AVBI_DATA_0_SHIFT (6u) -#define INTC_ICDICFR22_AVBI_DATA_1_SHIFT (7u) -#define INTC_ICDICFR22_AVBI_ERROR_0_SHIFT (8u) -#define INTC_ICDICFR22_AVBI_ERROR_1_SHIFT (9u) -#define INTC_ICDICFR22_AVBI_MANAGE_0_SHIFT (10u) -#define INTC_ICDICFR22_AVBI_MANAGE_1_SHIFT (11u) -#define INTC_ICDICFR22_AVBI_MAC_0_SHIFT (12u) -#define INTC_ICDICFR22_AVBI_MAC_1_SHIFT (13u) -#define INTC_ICDICFR22_ETHERI_0_SHIFT (14u) -#define INTC_ICDICFR22_ETHERI_1_SHIFT (15u) -#define INTC_ICDICFR22_CEUI_0_SHIFT (24u) -#define INTC_ICDICFR22_CEUI_1_SHIFT (25u) - -#define INTC_ICDICFR23_H2XMLB_ERRINT_0_SHIFT (26u) -#define INTC_ICDICFR23_H2XMLB_ERRINT_1_SHIFT (27u) -#define INTC_ICDICFR23_H2XIC1_ERRINT_0_SHIFT (28u) -#define INTC_ICDICFR23_H2XIC1_ERRINT_1_SHIFT (29u) -#define INTC_ICDICFR23_X2HPERI1_ERRINT_0_SHIFT (30u) -#define INTC_ICDICFR23_X2HPERI1_ERRINT_1_SHIFT (31u) - -#define INTC_ICDICFR24_X2HPERI2_ERRINT_0_SHIFT (0u) -#define INTC_ICDICFR24_X2HPERI2_ERRINT_1_SHIFT (1u) -#define INTC_ICDICFR24_X2HPERI34_ERRINT_0_SHIFT (2u) -#define INTC_ICDICFR24_X2HPERI34_ERRINT_1_SHIFT (3u) -#define INTC_ICDICFR24_X2HPERI5_ERRINT_0_SHIFT (4u) -#define INTC_ICDICFR24_X2HPERI5_ERRINT_1_SHIFT (5u) -#define INTC_ICDICFR24_X2HPERI67_ERRINT_0_SHIFT (6u) -#define INTC_ICDICFR24_X2HPERI67_ERRINT_1_SHIFT (7u) -#define INTC_ICDICFR24_X2HDBGR_ERRINT_0_SHIFT (8u) -#define INTC_ICDICFR24_X2HDBGR_ERRINT_1_SHIFT (9u) -#define INTC_ICDICFR24_X2HBSC_ERRINT_0_SHIFT (10u) -#define INTC_ICDICFR24_X2HBSC_ERRINT_1_SHIFT (11u) -#define INTC_ICDICFR24_X2HSPI1_ERRINT_0_SHIFT (12u) -#define INTC_ICDICFR24_X2HSPI1_ERRINT_1_SHIFT (13u) -#define INTC_ICDICFR24_X2HSPI2_ERRINT_0_SHIFT (14u) -#define INTC_ICDICFR24_X2HSPI2_ERRINT_1_SHIFT (15u) -#define INTC_ICDICFR24_PRRI_0_SHIFT (16u) -#define INTC_ICDICFR24_PRRI_1_SHIFT (17u) -#define INTC_ICDICFR24_IFEI0_0_SHIFT (18u) -#define INTC_ICDICFR24_IFEI0_1_SHIFT (19u) -#define INTC_ICDICFR24_OFFI0_0_SHIFT (20u) -#define INTC_ICDICFR24_OFFI0_1_SHIFT (21u) -#define INTC_ICDICFR24_PFVEI0_0_SHIFT (22u) -#define INTC_ICDICFR24_PFVEI0_1_SHIFT (23u) -#define INTC_ICDICFR24_IFEI1_0_SHIFT (24u) -#define INTC_ICDICFR24_IFEI1_1_SHIFT (25u) -#define INTC_ICDICFR24_OFFI1_0_SHIFT (26u) -#define INTC_ICDICFR24_OFFI1_1_SHIFT (27u) -#define INTC_ICDICFR24_PFVEI1_0_SHIFT (28u) -#define INTC_ICDICFR24_PFVEI1_1_SHIFT (29u) - -#define INTC_ICDICFR26_TINT0_0_SHIFT (0u) -#define INTC_ICDICFR26_TINT0_1_SHIFT (1u) -#define INTC_ICDICFR26_TINT1_0_SHIFT (2u) -#define INTC_ICDICFR26_TINT1_1_SHIFT (3u) -#define INTC_ICDICFR26_TINT2_0_SHIFT (4u) -#define INTC_ICDICFR26_TINT2_1_SHIFT (5u) -#define INTC_ICDICFR26_TINT3_0_SHIFT (6u) -#define INTC_ICDICFR26_TINT3_1_SHIFT (7u) -#define INTC_ICDICFR26_TINT4_0_SHIFT (8u) -#define INTC_ICDICFR26_TINT4_1_SHIFT (9u) -#define INTC_ICDICFR26_TINT5_0_SHIFT (10u) -#define INTC_ICDICFR26_TINT5_1_SHIFT (11u) -#define INTC_ICDICFR26_TINT6_0_SHIFT (12u) -#define INTC_ICDICFR26_TINT6_1_SHIFT (13u) -#define INTC_ICDICFR26_TINT7_0_SHIFT (14u) -#define INTC_ICDICFR26_TINT7_1_SHIFT (15u) -#define INTC_ICDICFR26_TINT8_0_SHIFT (16u) -#define INTC_ICDICFR26_TINT8_1_SHIFT (17u) -#define INTC_ICDICFR26_TINT9_0_SHIFT (18u) -#define INTC_ICDICFR26_TINT9_1_SHIFT (19u) -#define INTC_ICDICFR26_TINT10_0_SHIFT (20u) -#define INTC_ICDICFR26_TINT10_1_SHIFT (21u) -#define INTC_ICDICFR26_TINT11_0_SHIFT (22u) -#define INTC_ICDICFR26_TINT11_1_SHIFT (23u) -#define INTC_ICDICFR26_TINT12_0_SHIFT (24u) -#define INTC_ICDICFR26_TINT12_1_SHIFT (25u) -#define INTC_ICDICFR26_TINT13_0_SHIFT (26u) -#define INTC_ICDICFR26_TINT13_1_SHIFT (27u) -#define INTC_ICDICFR26_TINT14_0_SHIFT (28u) -#define INTC_ICDICFR26_TINT14_1_SHIFT (29u) -#define INTC_ICDICFR26_TINT15_0_SHIFT (30u) -#define INTC_ICDICFR26_TINT15_1_SHIFT (31u) - -#define INTC_ICDICFR27_TINT16_0_SHIFT (0u) -#define INTC_ICDICFR27_TINT16_1_SHIFT (1u) -#define INTC_ICDICFR27_TINT17_0_SHIFT (2u) -#define INTC_ICDICFR27_TINT17_1_SHIFT (3u) -#define INTC_ICDICFR27_TINT18_0_SHIFT (4u) -#define INTC_ICDICFR27_TINT18_1_SHIFT (5u) -#define INTC_ICDICFR27_TINT19_0_SHIFT (6u) -#define INTC_ICDICFR27_TINT19_1_SHIFT (7u) -#define INTC_ICDICFR27_TINT20_0_SHIFT (8u) -#define INTC_ICDICFR27_TINT20_1_SHIFT (9u) -#define INTC_ICDICFR27_TINT21_0_SHIFT (10u) -#define INTC_ICDICFR27_TINT21_1_SHIFT (11u) -#define INTC_ICDICFR27_TINT22_0_SHIFT (12u) -#define INTC_ICDICFR27_TINT22_1_SHIFT (13u) -#define INTC_ICDICFR27_TINT23_0_SHIFT (14u) -#define INTC_ICDICFR27_TINT23_1_SHIFT (15u) -#define INTC_ICDICFR27_TINT24_0_SHIFT (16u) -#define INTC_ICDICFR27_TINT24_1_SHIFT (17u) -#define INTC_ICDICFR27_TINT25_0_SHIFT (18u) -#define INTC_ICDICFR27_TINT25_1_SHIFT (19u) -#define INTC_ICDICFR27_TINT26_0_SHIFT (20u) -#define INTC_ICDICFR27_TINT26_1_SHIFT (21u) -#define INTC_ICDICFR27_TINT27_0_SHIFT (22u) -#define INTC_ICDICFR27_TINT27_1_SHIFT (23u) -#define INTC_ICDICFR27_TINT28_0_SHIFT (24u) -#define INTC_ICDICFR27_TINT28_1_SHIFT (25u) -#define INTC_ICDICFR27_TINT29_0_SHIFT (26u) -#define INTC_ICDICFR27_TINT29_1_SHIFT (27u) -#define INTC_ICDICFR27_TINT30_0_SHIFT (28u) -#define INTC_ICDICFR27_TINT30_1_SHIFT (29u) -#define INTC_ICDICFR27_TINT31_0_SHIFT (30u) -#define INTC_ICDICFR27_TINT31_1_SHIFT (31u) - -#define INTC_ICDICFR28_TINT32_0_SHIFT (0u) -#define INTC_ICDICFR28_TINT32_1_SHIFT (1u) -#define INTC_ICDICFR28_TINT33_0_SHIFT (2u) -#define INTC_ICDICFR28_TINT33_1_SHIFT (3u) -#define INTC_ICDICFR28_TINT34_0_SHIFT (4u) -#define INTC_ICDICFR28_TINT34_1_SHIFT (5u) -#define INTC_ICDICFR28_TINT35_0_SHIFT (6u) -#define INTC_ICDICFR28_TINT35_1_SHIFT (7u) -#define INTC_ICDICFR28_TINT36_0_SHIFT (8u) -#define INTC_ICDICFR28_TINT36_1_SHIFT (9u) -#define INTC_ICDICFR28_TINT37_0_SHIFT (10u) -#define INTC_ICDICFR28_TINT37_1_SHIFT (11u) -#define INTC_ICDICFR28_TINT38_0_SHIFT (12u) -#define INTC_ICDICFR28_TINT38_1_SHIFT (13u) -#define INTC_ICDICFR28_TINT39_0_SHIFT (14u) -#define INTC_ICDICFR28_TINT39_1_SHIFT (15u) -#define INTC_ICDICFR28_TINT40_0_SHIFT (16u) -#define INTC_ICDICFR28_TINT40_1_SHIFT (17u) -#define INTC_ICDICFR28_TINT41_0_SHIFT (18u) -#define INTC_ICDICFR28_TINT41_1_SHIFT (19u) -#define INTC_ICDICFR28_TINT42_0_SHIFT (20u) -#define INTC_ICDICFR28_TINT42_1_SHIFT (21u) -#define INTC_ICDICFR28_TINT43_0_SHIFT (22u) -#define INTC_ICDICFR28_TINT43_1_SHIFT (23u) -#define INTC_ICDICFR28_TINT44_0_SHIFT (24u) -#define INTC_ICDICFR28_TINT44_1_SHIFT (25u) -#define INTC_ICDICFR28_TINT45_0_SHIFT (26u) -#define INTC_ICDICFR28_TINT45_1_SHIFT (27u) -#define INTC_ICDICFR28_TINT46_0_SHIFT (28u) -#define INTC_ICDICFR28_TINT46_1_SHIFT (29u) -#define INTC_ICDICFR28_TINT47_0_SHIFT (30u) -#define INTC_ICDICFR28_TINT47_1_SHIFT (31u) - -#define INTC_ICDICFR29_TINT48_0_SHIFT (0u) -#define INTC_ICDICFR29_TINT48_1_SHIFT (1u) -#define INTC_ICDICFR29_TINT49_0_SHIFT (2u) -#define INTC_ICDICFR29_TINT49_1_SHIFT (3u) -#define INTC_ICDICFR29_TINT50_0_SHIFT (4u) -#define INTC_ICDICFR29_TINT50_1_SHIFT (5u) -#define INTC_ICDICFR29_TINT51_0_SHIFT (6u) -#define INTC_ICDICFR29_TINT51_1_SHIFT (7u) -#define INTC_ICDICFR29_TINT52_0_SHIFT (8u) -#define INTC_ICDICFR29_TINT52_1_SHIFT (9u) -#define INTC_ICDICFR29_TINT53_0_SHIFT (10u) -#define INTC_ICDICFR29_TINT53_1_SHIFT (11u) -#define INTC_ICDICFR29_TINT54_0_SHIFT (12u) -#define INTC_ICDICFR29_TINT54_1_SHIFT (13u) -#define INTC_ICDICFR29_TINT55_0_SHIFT (14u) -#define INTC_ICDICFR29_TINT55_1_SHIFT (15u) -#define INTC_ICDICFR29_TINT56_0_SHIFT (16u) -#define INTC_ICDICFR29_TINT56_1_SHIFT (17u) -#define INTC_ICDICFR29_TINT57_0_SHIFT (18u) -#define INTC_ICDICFR29_TINT57_1_SHIFT (19u) -#define INTC_ICDICFR29_TINT58_0_SHIFT (20u) -#define INTC_ICDICFR29_TINT58_1_SHIFT (21u) -#define INTC_ICDICFR29_TINT59_0_SHIFT (22u) -#define INTC_ICDICFR29_TINT59_1_SHIFT (23u) -#define INTC_ICDICFR29_TINT60_0_SHIFT (24u) -#define INTC_ICDICFR29_TINT60_1_SHIFT (25u) -#define INTC_ICDICFR29_TINT61_0_SHIFT (26u) -#define INTC_ICDICFR29_TINT61_1_SHIFT (27u) -#define INTC_ICDICFR29_TINT62_0_SHIFT (28u) -#define INTC_ICDICFR29_TINT62_1_SHIFT (29u) -#define INTC_ICDICFR29_TINT63_0_SHIFT (30u) -#define INTC_ICDICFR29_TINT63_1_SHIFT (31u) - -#define INTC_ICDICFR30_TINT64_0_SHIFT (0u) -#define INTC_ICDICFR30_TINT64_1_SHIFT (1u) -#define INTC_ICDICFR30_TINT65_0_SHIFT (2u) -#define INTC_ICDICFR30_TINT65_1_SHIFT (3u) -#define INTC_ICDICFR30_TINT66_0_SHIFT (4u) -#define INTC_ICDICFR30_TINT66_1_SHIFT (5u) -#define INTC_ICDICFR30_TINT67_0_SHIFT (6u) -#define INTC_ICDICFR30_TINT67_1_SHIFT (7u) -#define INTC_ICDICFR30_TINT68_0_SHIFT (8u) -#define INTC_ICDICFR30_TINT68_1_SHIFT (9u) -#define INTC_ICDICFR30_TINT69_0_SHIFT (10u) -#define INTC_ICDICFR30_TINT69_1_SHIFT (11u) -#define INTC_ICDICFR30_TINT70_0_SHIFT (12u) -#define INTC_ICDICFR30_TINT70_1_SHIFT (13u) -#define INTC_ICDICFR30_TINT71_0_SHIFT (14u) -#define INTC_ICDICFR30_TINT71_1_SHIFT (15u) -#define INTC_ICDICFR30_TINT72_0_SHIFT (16u) -#define INTC_ICDICFR30_TINT72_1_SHIFT (17u) -#define INTC_ICDICFR30_TINT73_0_SHIFT (18u) -#define INTC_ICDICFR30_TINT73_1_SHIFT (19u) -#define INTC_ICDICFR30_TINT74_0_SHIFT (20u) -#define INTC_ICDICFR30_TINT74_1_SHIFT (21u) -#define INTC_ICDICFR30_TINT75_0_SHIFT (22u) -#define INTC_ICDICFR30_TINT75_1_SHIFT (23u) -#define INTC_ICDICFR30_TINT76_0_SHIFT (24u) -#define INTC_ICDICFR30_TINT76_1_SHIFT (25u) -#define INTC_ICDICFR30_TINT77_0_SHIFT (26u) -#define INTC_ICDICFR30_TINT77_1_SHIFT (27u) -#define INTC_ICDICFR30_TINT78_0_SHIFT (28u) -#define INTC_ICDICFR30_TINT78_1_SHIFT (29u) -#define INTC_ICDICFR30_TINT79_0_SHIFT (30u) -#define INTC_ICDICFR30_TINT79_1_SHIFT (31u) - -#define INTC_ICDICFR31_TINT80_0_SHIFT (0u) -#define INTC_ICDICFR31_TINT80_1_SHIFT (1u) -#define INTC_ICDICFR31_TINT81_0_SHIFT (2u) -#define INTC_ICDICFR31_TINT81_1_SHIFT (3u) -#define INTC_ICDICFR31_TINT82_0_SHIFT (4u) -#define INTC_ICDICFR31_TINT82_1_SHIFT (5u) -#define INTC_ICDICFR31_TINT83_0_SHIFT (6u) -#define INTC_ICDICFR31_TINT83_1_SHIFT (7u) -#define INTC_ICDICFR31_TINT84_0_SHIFT (8u) -#define INTC_ICDICFR31_TINT84_1_SHIFT (9u) -#define INTC_ICDICFR31_TINT85_0_SHIFT (10u) -#define INTC_ICDICFR31_TINT85_1_SHIFT (11u) -#define INTC_ICDICFR31_TINT86_0_SHIFT (12u) -#define INTC_ICDICFR31_TINT86_1_SHIFT (13u) -#define INTC_ICDICFR31_TINT87_0_SHIFT (14u) -#define INTC_ICDICFR31_TINT87_1_SHIFT (15u) -#define INTC_ICDICFR31_TINT88_0_SHIFT (16u) -#define INTC_ICDICFR31_TINT88_1_SHIFT (17u) -#define INTC_ICDICFR31_TINT89_0_SHIFT (18u) -#define INTC_ICDICFR31_TINT89_1_SHIFT (19u) -#define INTC_ICDICFR31_TINT90_0_SHIFT (20u) -#define INTC_ICDICFR31_TINT90_1_SHIFT (21u) -#define INTC_ICDICFR31_TINT91_0_SHIFT (22u) -#define INTC_ICDICFR31_TINT91_1_SHIFT (23u) -#define INTC_ICDICFR31_TINT92_0_SHIFT (24u) -#define INTC_ICDICFR31_TINT92_1_SHIFT (25u) -#define INTC_ICDICFR31_TINT93_0_SHIFT (26u) -#define INTC_ICDICFR31_TINT93_1_SHIFT (27u) -#define INTC_ICDICFR31_TINT94_0_SHIFT (28u) -#define INTC_ICDICFR31_TINT94_1_SHIFT (29u) -#define INTC_ICDICFR31_TINT95_0_SHIFT (30u) -#define INTC_ICDICFR31_TINT95_1_SHIFT (31u) - -#define INTC_ICDICFR32_TINT96_0_SHIFT (0u) -#define INTC_ICDICFR32_TINT96_1_SHIFT (1u) -#define INTC_ICDICFR32_TINT97_0_SHIFT (2u) -#define INTC_ICDICFR32_TINT97_1_SHIFT (3u) -#define INTC_ICDICFR32_TINT98_0_SHIFT (4u) -#define INTC_ICDICFR32_TINT98_1_SHIFT (5u) -#define INTC_ICDICFR32_TINT99_0_SHIFT (6u) -#define INTC_ICDICFR32_TINT99_1_SHIFT (7u) -#define INTC_ICDICFR32_TINT100_0_SHIFT (8u) -#define INTC_ICDICFR32_TINT100_1_SHIFT (9u) -#define INTC_ICDICFR32_TINT101_0_SHIFT (10u) -#define INTC_ICDICFR32_TINT101_1_SHIFT (11u) -#define INTC_ICDICFR32_TINT102_0_SHIFT (12u) -#define INTC_ICDICFR32_TINT102_1_SHIFT (13u) -#define INTC_ICDICFR32_TINT103_0_SHIFT (14u) -#define INTC_ICDICFR32_TINT103_1_SHIFT (15u) -#define INTC_ICDICFR32_TINT104_0_SHIFT (16u) -#define INTC_ICDICFR32_TINT104_1_SHIFT (17u) -#define INTC_ICDICFR32_TINT105_0_SHIFT (18u) -#define INTC_ICDICFR32_TINT105_1_SHIFT (19u) -#define INTC_ICDICFR32_TINT106_0_SHIFT (20u) -#define INTC_ICDICFR32_TINT106_1_SHIFT (21u) -#define INTC_ICDICFR32_TINT107_0_SHIFT (22u) -#define INTC_ICDICFR32_TINT107_1_SHIFT (23u) -#define INTC_ICDICFR32_TINT108_0_SHIFT (24u) -#define INTC_ICDICFR32_TINT108_1_SHIFT (25u) -#define INTC_ICDICFR32_TINT109_0_SHIFT (26u) -#define INTC_ICDICFR32_TINT109_1_SHIFT (27u) -#define INTC_ICDICFR32_TINT110_0_SHIFT (28u) -#define INTC_ICDICFR32_TINT110_1_SHIFT (29u) -#define INTC_ICDICFR32_TINT111_0_SHIFT (30u) -#define INTC_ICDICFR32_TINT111_1_SHIFT (31u) - -#define INTC_ICDICFR33_TINT112_0_SHIFT (0u) -#define INTC_ICDICFR33_TINT112_1_SHIFT (1u) -#define INTC_ICDICFR33_TINT113_0_SHIFT (2u) -#define INTC_ICDICFR33_TINT113_1_SHIFT (3u) -#define INTC_ICDICFR33_TINT114_0_SHIFT (4u) -#define INTC_ICDICFR33_TINT114_1_SHIFT (5u) -#define INTC_ICDICFR33_TINT115_0_SHIFT (6u) -#define INTC_ICDICFR33_TINT115_1_SHIFT (7u) -#define INTC_ICDICFR33_TINT116_0_SHIFT (8u) -#define INTC_ICDICFR33_TINT116_1_SHIFT (9u) -#define INTC_ICDICFR33_TINT117_0_SHIFT (10u) -#define INTC_ICDICFR33_TINT117_1_SHIFT (11u) -#define INTC_ICDICFR33_TINT118_0_SHIFT (12u) -#define INTC_ICDICFR33_TINT118_1_SHIFT (13u) -#define INTC_ICDICFR33_TINT119_0_SHIFT (14u) -#define INTC_ICDICFR33_TINT119_1_SHIFT (15u) -#define INTC_ICDICFR33_TINT120_0_SHIFT (16u) -#define INTC_ICDICFR33_TINT120_1_SHIFT (17u) -#define INTC_ICDICFR33_TINT121_0_SHIFT (18u) -#define INTC_ICDICFR33_TINT121_1_SHIFT (19u) -#define INTC_ICDICFR33_TINT122_0_SHIFT (20u) -#define INTC_ICDICFR33_TINT122_1_SHIFT (21u) -#define INTC_ICDICFR33_TINT123_0_SHIFT (22u) -#define INTC_ICDICFR33_TINT123_1_SHIFT (23u) -#define INTC_ICDICFR33_TINT124_0_SHIFT (24u) -#define INTC_ICDICFR33_TINT124_1_SHIFT (25u) -#define INTC_ICDICFR33_TINT125_0_SHIFT (26u) -#define INTC_ICDICFR33_TINT125_1_SHIFT (27u) -#define INTC_ICDICFR33_TINT126_0_SHIFT (28u) -#define INTC_ICDICFR33_TINT126_1_SHIFT (29u) -#define INTC_ICDICFR33_TINT127_0_SHIFT (30u) -#define INTC_ICDICFR33_TINT127_1_SHIFT (31u) - -#define INTC_ICDICFR34_TINT128_0_SHIFT (0u) -#define INTC_ICDICFR34_TINT128_1_SHIFT (1u) -#define INTC_ICDICFR34_TINT129_0_SHIFT (2u) -#define INTC_ICDICFR34_TINT129_1_SHIFT (3u) -#define INTC_ICDICFR34_TINT130_0_SHIFT (4u) -#define INTC_ICDICFR34_TINT130_1_SHIFT (5u) -#define INTC_ICDICFR34_TINT131_0_SHIFT (6u) -#define INTC_ICDICFR34_TINT131_1_SHIFT (7u) -#define INTC_ICDICFR34_TINT132_0_SHIFT (8u) -#define INTC_ICDICFR34_TINT132_1_SHIFT (9u) -#define INTC_ICDICFR34_TINT133_0_SHIFT (10u) -#define INTC_ICDICFR34_TINT133_1_SHIFT (11u) -#define INTC_ICDICFR34_TINT134_0_SHIFT (12u) -#define INTC_ICDICFR34_TINT134_1_SHIFT (13u) -#define INTC_ICDICFR34_TINT135_0_SHIFT (14u) -#define INTC_ICDICFR34_TINT135_1_SHIFT (15u) -#define INTC_ICDICFR34_TINT136_0_SHIFT (16u) -#define INTC_ICDICFR34_TINT136_1_SHIFT (17u) -#define INTC_ICDICFR34_TINT137_0_SHIFT (18u) -#define INTC_ICDICFR34_TINT137_1_SHIFT (19u) -#define INTC_ICDICFR34_TINT138_0_SHIFT (20u) -#define INTC_ICDICFR34_TINT138_1_SHIFT (21u) -#define INTC_ICDICFR34_TINT139_0_SHIFT (22u) -#define INTC_ICDICFR34_TINT139_1_SHIFT (23u) -#define INTC_ICDICFR34_TINT140_0_SHIFT (24u) -#define INTC_ICDICFR34_TINT140_1_SHIFT (25u) -#define INTC_ICDICFR34_TINT141_0_SHIFT (26u) -#define INTC_ICDICFR34_TINT141_1_SHIFT (27u) -#define INTC_ICDICFR34_TINT142_0_SHIFT (28u) -#define INTC_ICDICFR34_TINT142_1_SHIFT (29u) -#define INTC_ICDICFR34_TINT143_0_SHIFT (30u) -#define INTC_ICDICFR34_TINT143_1_SHIFT (31u) - -#define INTC_ICDICFR35_TINT144_0_SHIFT (0u) -#define INTC_ICDICFR35_TINT144_1_SHIFT (1u) -#define INTC_ICDICFR35_TINT145_0_SHIFT (2u) -#define INTC_ICDICFR35_TINT145_1_SHIFT (3u) -#define INTC_ICDICFR35_TINT146_0_SHIFT (4u) -#define INTC_ICDICFR35_TINT146_1_SHIFT (5u) -#define INTC_ICDICFR35_TINT147_0_SHIFT (6u) -#define INTC_ICDICFR35_TINT147_1_SHIFT (7u) -#define INTC_ICDICFR35_TINT148_0_SHIFT (8u) -#define INTC_ICDICFR35_TINT148_1_SHIFT (9u) -#define INTC_ICDICFR35_TINT149_0_SHIFT (10u) -#define INTC_ICDICFR35_TINT149_1_SHIFT (11u) -#define INTC_ICDICFR35_TINT150_0_SHIFT (12u) -#define INTC_ICDICFR35_TINT150_1_SHIFT (13u) -#define INTC_ICDICFR35_TINT151_0_SHIFT (14u) -#define INTC_ICDICFR35_TINT151_1_SHIFT (15u) -#define INTC_ICDICFR35_TINT152_0_SHIFT (16u) -#define INTC_ICDICFR35_TINT152_1_SHIFT (17u) -#define INTC_ICDICFR35_TINT153_0_SHIFT (18u) -#define INTC_ICDICFR35_TINT153_1_SHIFT (19u) -#define INTC_ICDICFR35_TINT154_0_SHIFT (20u) -#define INTC_ICDICFR35_TINT154_1_SHIFT (21u) -#define INTC_ICDICFR35_TINT155_0_SHIFT (22u) -#define INTC_ICDICFR35_TINT155_1_SHIFT (23u) -#define INTC_ICDICFR35_TINT156_0_SHIFT (24u) -#define INTC_ICDICFR35_TINT156_1_SHIFT (25u) -#define INTC_ICDICFR35_TINT157_0_SHIFT (26u) -#define INTC_ICDICFR35_TINT157_1_SHIFT (27u) -#define INTC_ICDICFR35_TINT158_0_SHIFT (28u) -#define INTC_ICDICFR35_TINT158_1_SHIFT (29u) -#define INTC_ICDICFR35_TINT159_0_SHIFT (30u) -#define INTC_ICDICFR35_TINT159_1_SHIFT (31u) - -#define INTC_ICDICFR36_TINT160_0_SHIFT (0u) -#define INTC_ICDICFR36_TINT160_1_SHIFT (1u) -#define INTC_ICDICFR36_TINT161_0_SHIFT (2u) -#define INTC_ICDICFR36_TINT161_1_SHIFT (3u) -#define INTC_ICDICFR36_TINT162_0_SHIFT (4u) -#define INTC_ICDICFR36_TINT162_1_SHIFT (5u) -#define INTC_ICDICFR36_TINT163_0_SHIFT (6u) -#define INTC_ICDICFR36_TINT163_1_SHIFT (7u) -#define INTC_ICDICFR36_TINT164_0_SHIFT (8u) -#define INTC_ICDICFR36_TINT164_1_SHIFT (9u) -#define INTC_ICDICFR36_TINT165_0_SHIFT (10u) -#define INTC_ICDICFR36_TINT165_1_SHIFT (11u) -#define INTC_ICDICFR36_TINT166_0_SHIFT (12u) -#define INTC_ICDICFR36_TINT166_1_SHIFT (13u) -#define INTC_ICDICFR36_TINT167_0_SHIFT (14u) -#define INTC_ICDICFR36_TINT167_1_SHIFT (15u) -#define INTC_ICDICFR36_TINT168_0_SHIFT (16u) -#define INTC_ICDICFR36_TINT168_1_SHIFT (17u) -#define INTC_ICDICFR36_TINT169_0_SHIFT (18u) -#define INTC_ICDICFR36_TINT169_1_SHIFT (19u) -#define INTC_ICDICFR36_TINT170_0_SHIFT (20u) -#define INTC_ICDICFR36_TINT170_1_SHIFT (21u) - -#define INTC_ICDSGIR_SGIINTID_SHIFT (0u) -#define INTC_ICDSGIR_SATT_SHIFT (15u) -#define INTC_ICDSGIR_CPUTargetList_SHIFT (16u) -#define INTC_ICDSGIR_TargetListFilter_SHIFT (24u) - -#define INTC_ICCICR_EnableS_SHIFT (0u) -#define INTC_ICCICR_EnableNS_SHIFT (1u) -#define INTC_ICCICR_AckCtl_SHIFT (2u) -#define INTC_ICCICR_FIQEn_SHIFT (3u) -#define INTC_ICCICR_SBPR_SHIFT (4u) - -#define INTC_ICCPMR_Priority_SHIFT (0u) - -#define INTC_ICCBPR_Binarypoint_SHIFT (0u) - -#define INTC_ICCIAR_ACKINTID_SHIFT (0u) -#define INTC_ICCIAR_CPUID_SHIFT (10u) - -#define INTC_ICCEOIR_EOIINTID_SHIFT (0u) -#define INTC_ICCEOIR_CPUID_SHIFT (10u) - -#define INTC_ICCRPR_Priority_SHIFT (0u) - -#define INTC_ICCHPIR_PENDINTID_SHIFT (0u) -#define INTC_ICCHPIR_CPUID_SHIFT (10u) - -#define INTC_ICCABPR_Binarypoint_SHIFT (0u) - -#define INTC_ICCIIDR_Implementer_SHIFT (0u) -#define INTC_ICCIIDR_Revision_SHIFT (12u) -#define INTC_ICCIIDR_Architecture_version_SHIFT (16u) -#define INTC_ICCIIDR_ProductID_SHIFT (20u) - -#define INTC_ICR0_NMIF_SHIFT (1u) -#define INTC_ICR0_NMIE_SHIFT (8u) -#define INTC_ICR0_NMIL_SHIFT (15u) - -#define INTC_ICR1_IRQ00S_SHIFT (0u) -#define INTC_ICR1_IRQ01S_SHIFT (1u) -#define INTC_ICR1_IRQ10S_SHIFT (2u) -#define INTC_ICR1_IRQ11S_SHIFT (3u) -#define INTC_ICR1_IRQ20S_SHIFT (4u) -#define INTC_ICR1_IRQ21S_SHIFT (5u) -#define INTC_ICR1_IRQ30S_SHIFT (6u) -#define INTC_ICR1_IRQ31S_SHIFT (7u) -#define INTC_ICR1_IRQ40S_SHIFT (8u) -#define INTC_ICR1_IRQ41S_SHIFT (9u) -#define INTC_ICR1_IRQ50S_SHIFT (10u) -#define INTC_ICR1_IRQ51S_SHIFT (11u) -#define INTC_ICR1_IRQ60S_SHIFT (12u) -#define INTC_ICR1_IRQ61S_SHIFT (13u) -#define INTC_ICR1_IRQ70S_SHIFT (14u) -#define INTC_ICR1_IRQ71S_SHIFT (15u) - -#define INTC_IRQRR_IRQ0F_SHIFT (0u) -#define INTC_IRQRR_IRQ1F_SHIFT (1u) -#define INTC_IRQRR_IRQ2F_SHIFT (2u) -#define INTC_IRQRR_IRQ3F_SHIFT (3u) -#define INTC_IRQRR_IRQ4F_SHIFT (4u) -#define INTC_IRQRR_IRQ5F_SHIFT (5u) -#define INTC_IRQRR_IRQ6F_SHIFT (6u) -#define INTC_IRQRR_IRQ7F_SHIFT (7u) - - -#endif /* INTC_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h deleted file mode 100644 index eea92773f49..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h +++ /dev/null @@ -1,462 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : mtu2_iobitmask.h -* $Rev: 1138 $ -* $Date:: 2014-08-08 11:03:56 +0900#$ -* Description : MTU2 register define header -*******************************************************************************/ -#ifndef MTU2_IOBITMASK_H -#define MTU2_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -#define MTU2_TCR_n_TPSC (0x07u) -#define MTU2_TCR_n_CKEG (0x18u) -#define MTU2_TCR_n_CCLR (0xE0u) - -#define MTU2_TMDR_n_MD (0x0Fu) - -#define MTU2_TIOR_2_IOA (0x0Fu) -#define MTU2_TIOR_2_IOB (0xF0u) - -#define MTU2_TIER_n_TGIEA (0x01u) -#define MTU2_TIER_n_TGIEB (0x02u) -#define MTU2_TIER_n_TCIEV (0x10u) -#define MTU2_TIER_2_TCIEU (0x20u) -#define MTU2_TIER_n_TTGE (0x80u) - -#define MTU2_TSR_n_TGFA (0x01u) -#define MTU2_TSR_n_TGFB (0x02u) -#define MTU2_TSR_n_TCFV (0x10u) -#define MTU2_TSR_2_TCFU (0x20u) -#define MTU2_TSR_2_TCFD (0x80u) - -#define MTU2_TCNT_n_D (0xFFFFu) - -#define MTU2_TGRA_n_D (0xFFFFu) - -#define MTU2_TGRB_n_D (0xFFFFu) - -#define MTU2_TMDR_3_BFA (0x10u) -#define MTU2_TMDR_3_BFB (0x20u) - -#define MTU2_TMDR_4_BFA (0x10u) -#define MTU2_TMDR_4_BFB (0x20u) - -#define MTU2_TIORH_3_IOA (0x0Fu) -#define MTU2_TIORH_3_IOB (0xF0u) - -#define MTU2_TIORL_3_IOC (0x0Fu) -#define MTU2_TIORL_3_IOD (0xF0u) - -#define MTU2_TIORH_4_IOA (0x0Fu) -#define MTU2_TIORH_4_IOB (0xF0u) - -#define MTU2_TIORL_4_IOC (0x0Fu) -#define MTU2_TIORL_4_IOD (0xF0u) - -#define MTU2_TIER_3_TGIEC (0x04u) -#define MTU2_TIER_3_TGIED (0x08u) - -#define MTU2_TIER_4_TGIEC (0x04u) -#define MTU2_TIER_4_TGIED (0x08u) -#define MTU2_TIER_4_TTGE2 (0x40u) - -#define MTU2_TOER_OE3B (0x01u) -#define MTU2_TOER_OE4A (0x02u) -#define MTU2_TOER_OE4B (0x04u) -#define MTU2_TOER_OE3D (0x08u) -#define MTU2_TOER_OE4C (0x10u) -#define MTU2_TOER_OE4D (0x20u) - -#define MTU2_TGCR_UF (0x01u) -#define MTU2_TGCR_VF (0x02u) -#define MTU2_TGCR_WF (0x04u) -#define MTU2_TGCR_FB (0x08u) -#define MTU2_TGCR_P (0x10u) -#define MTU2_TGCR_N (0x20u) -#define MTU2_TGCR_BDC (0x40u) - -#define MTU2_TOCR1_OLSP (0x01u) -#define MTU2_TOCR1_OLSN (0x02u) -#define MTU2_TOCR1_TOCS (0x04u) -#define MTU2_TOCR1_TOCL (0x08u) -#define MTU2_TOCR1_PSYE (0x40u) - -#define MTU2_TOCR2_OLS1P (0x01u) -#define MTU2_TOCR2_OLS1N (0x02u) -#define MTU2_TOCR2_OLS2P (0x04u) -#define MTU2_TOCR2_OLS2N (0x08u) -#define MTU2_TOCR2_OLS3P (0x10u) -#define MTU2_TOCR2_OLS3N (0x20u) -#define MTU2_TOCR2_BF (0xC0u) - -#define MTU2_TCDR_D (0xFFFFu) - -#define MTU2_TDDR_D (0xFFFFu) - -#define MTU2_TCNTS_D (0xFFFFu) - -#define MTU2_TCBR_D (0xFFFFu) - -#define MTU2_TGRC_3_D (0xFFFFu) - -#define MTU2_TGRD_3_D (0xFFFFu) - -#define MTU2_TGRC_4_D (0xFFFFu) - -#define MTU2_TGRD_4_D (0xFFFFu) - -#define MTU2_TSR_3_TGFC (0x04u) -#define MTU2_TSR_3_TGFD (0x08u) -#define MTU2_TSR_3_TCFD (0x80u) - -#define MTU2_TSR_4_TGFC (0x04u) -#define MTU2_TSR_4_TGFD (0x08u) -#define MTU2_TSR_4_TCFD (0x80u) - -#define MTU2_TITCR_4VCOR (0x07u) -#define MTU2_TITCR_T4VEN (0x08u) -#define MTU2_TITCR_3ACOR (0x70u) -#define MTU2_TITCR_T3AEN (0x80u) - -#define MTU2_TITCNT_4VCNT (0x07u) -#define MTU2_TITCNT_3ACNT (0x70u) - -#define MTU2_TBTER_BTE (0x03u) - -#define MTU2_TDER_TDER (0x01u) - -#define MTU2_TOLBR_OLS1P (0x01u) -#define MTU2_TOLBR_OLS1N (0x02u) -#define MTU2_TOLBR_OLS2P (0x04u) -#define MTU2_TOLBR_OLS2N (0x08u) -#define MTU2_TOLBR_OLS3P (0x10u) -#define MTU2_TOLBR_OLS3N (0x20u) - -#define MTU2_TBTM_3_TTSA (0x01u) -#define MTU2_TBTM_3_TTSB (0x02u) - -#define MTU2_TBTM_4_TTSA (0x01u) -#define MTU2_TBTM_4_TTSB (0x02u) - -#define MTU2_TADCR_ITB4VE (0x0001u) -#define MTU2_TADCR_ITB3AE (0x0002u) -#define MTU2_TADCR_ITA4VE (0x0004u) -#define MTU2_TADCR_ITA3AE (0x0008u) -#define MTU2_TADCR_DT4BE (0x0010u) -#define MTU2_TADCR_UT4BE (0x0020u) -#define MTU2_TADCR_DT4AE (0x0040u) -#define MTU2_TADCR_UT4AE (0x0080u) -#define MTU2_TADCR_BF (0xC000u) - -#define MTU2_TADCORA_4_D (0xFFFFu) - -#define MTU2_TADCORB_4_D (0xFFFFu) - -#define MTU2_TADCOBRA_4_D (0xFFFFu) - -#define MTU2_TADCOBRB_4_D (0xFFFFu) - -#define MTU2_TWCR_WRE (0x01u) -#define MTU2_TWCR_CCE (0x80u) - -#define MTU2_TSTR_CST0 (0x01u) -#define MTU2_TSTR_CST1 (0x02u) -#define MTU2_TSTR_CST2 (0x04u) -#define MTU2_TSTR_CST3 (0x40u) -#define MTU2_TSTR_CST4 (0x80u) - -#define MTU2_TSYR_SYNC0 (0x01u) -#define MTU2_TSYR_SYNC1 (0x02u) -#define MTU2_TSYR_SYNC2 (0x04u) -#define MTU2_TSYR_SYNC3 (0x40u) -#define MTU2_TSYR_SYNC4 (0x80u) - -#define MTU2_TRWER_RWE (0x01u) - -#define MTU2_TMDR_0_BFA (0x10u) -#define MTU2_TMDR_0_BFB (0x20u) -#define MTU2_TMDR_0_BFE (0x40u) - -#define MTU2_TIORH_0_IOA (0x0Fu) -#define MTU2_TIORH_0_IOB (0xF0u) - -#define MTU2_TIORL_0_IOC (0x0Fu) -#define MTU2_TIORL_0_IOD (0xF0u) - -#define MTU2_TIER_0_TGIEC (0x04u) -#define MTU2_TIER_0_TGIED (0x08u) - -#define MTU2_TSR_0_TGFC (0x04u) -#define MTU2_TSR_0_TGFD (0x08u) - -#define MTU2_TGRC_0_D (0xFFFFu) - -#define MTU2_TGRD_0_D (0xFFFFu) - -#define MTU2_TGRE_0_D (0xFFFFu) - -#define MTU2_TGRF_0_D (0xFFFFu) - -#define MTU2_TIER2_0_TGIEE (0x01u) -#define MTU2_TIER2_0_TGIEF (0x02u) - -#define MTU2_TSR2_0_TGFE (0x01u) -#define MTU2_TSR2_0_TGFF (0x02u) - -#define MTU2_TBTM_0_TTSA (0x01u) -#define MTU2_TBTM_0_TTSB (0x02u) -#define MTU2_TBTM_0_TTSE (0x04u) - -#define MTU2_TIOR_1_IOA (0x0Fu) -#define MTU2_TIOR_1_IOB (0xF0u) - -#define MTU2_TIER_1_TCIEU (0x20u) - -#define MTU2_TSR_1_TCFU (0x20u) -#define MTU2_TSR_1_TCFD (0x80u) - -#define MTU2_TICCR_I1AE (0x01u) -#define MTU2_TICCR_I1BE (0x02u) -#define MTU2_TICCR_I2AE (0x04u) -#define MTU2_TICCR_I2BE (0x08u) - - -/* ==== Shift values for IO registers ==== */ -#define MTU2_TCR_n_TPSC_SHIFT (0u) -#define MTU2_TCR_n_CKEG_SHIFT (3u) -#define MTU2_TCR_n_CCLR_SHIFT (5u) - -#define MTU2_TMDR_n_MD_SHIFT (0u) - -#define MTU2_TIOR_2_IOA_SHIFT (0u) -#define MTU2_TIOR_2_IOB_SHIFT (4u) - -#define MTU2_TIER_n_TGIEA_SHIFT (0u) -#define MTU2_TIER_n_TGIEB_SHIFT (1u) -#define MTU2_TIER_n_TCIEV_SHIFT (4u) -#define MTU2_TIER_2_TCIEU_SHIFT (5u) -#define MTU2_TIER_n_TTGE_SHIFT (7u) - -#define MTU2_TSR_n_TGFA_SHIFT (0u) -#define MTU2_TSR_n_TGFB_SHIFT (1u) -#define MTU2_TSR_n_TCFV_SHIFT (4u) -#define MTU2_TSR_2_TCFU_SHIFT (5u) -#define MTU2_TSR_2_TCFD_SHIFT (7u) - -#define MTU2_TCNT_n_D_SHIFT (0u) - -#define MTU2_TGRA_n_D_SHIFT (0u) - -#define MTU2_TGRB_n_D_SHIFT (0u) - -#define MTU2_TMDR_3_BFA_SHIFT (4u) -#define MTU2_TMDR_3_BFB_SHIFT (5u) - -#define MTU2_TMDR_4_BFA_SHIFT (4u) -#define MTU2_TMDR_4_BFB_SHIFT (5u) - -#define MTU2_TIORH_3_IOA_SHIFT (0u) -#define MTU2_TIORH_3_IOB_SHIFT (4u) - -#define MTU2_TIORL_3_IOC_SHIFT (0u) -#define MTU2_TIORL_3_IOD_SHIFT (4u) - -#define MTU2_TIORH_4_IOA_SHIFT (0u) -#define MTU2_TIORH_4_IOB_SHIFT (4u) - -#define MTU2_TIORL_4_IOC_SHIFT (0u) -#define MTU2_TIORL_4_IOD_SHIFT (4u) - -#define MTU2_TIER_3_TGIEC_SHIFT (2u) -#define MTU2_TIER_3_TGIED_SHIFT (3u) - -#define MTU2_TIER_4_TGIEC_SHIFT (2u) -#define MTU2_TIER_4_TGIED_SHIFT (3u) -#define MTU2_TIER_4_TTGE2_SHIFT (6u) - -#define MTU2_TOER_OE3B_SHIFT (0u) -#define MTU2_TOER_OE4A_SHIFT (1u) -#define MTU2_TOER_OE4B_SHIFT (2u) -#define MTU2_TOER_OE3D_SHIFT (3u) -#define MTU2_TOER_OE4C_SHIFT (4u) -#define MTU2_TOER_OE4D_SHIFT (5u) - -#define MTU2_TGCR_UF_SHIFT (0u) -#define MTU2_TGCR_VF_SHIFT (1u) -#define MTU2_TGCR_WF_SHIFT (2u) -#define MTU2_TGCR_FB_SHIFT (3u) -#define MTU2_TGCR_P_SHIFT (4u) -#define MTU2_TGCR_N_SHIFT (5u) -#define MTU2_TGCR_BDC_SHIFT (6u) - -#define MTU2_TOCR1_OLSP_SHIFT (0u) -#define MTU2_TOCR1_OLSN_SHIFT (1u) -#define MTU2_TOCR1_TOCS_SHIFT (2u) -#define MTU2_TOCR1_TOCL_SHIFT (3u) -#define MTU2_TOCR1_PSYE_SHIFT (6u) - -#define MTU2_TOCR2_OLS1P_SHIFT (0u) -#define MTU2_TOCR2_OLS1N_SHIFT (1u) -#define MTU2_TOCR2_OLS2P_SHIFT (2u) -#define MTU2_TOCR2_OLS2N_SHIFT (3u) -#define MTU2_TOCR2_OLS3P_SHIFT (4u) -#define MTU2_TOCR2_OLS3N_SHIFT (5u) -#define MTU2_TOCR2_BF_SHIFT (6u) - -#define MTU2_TCDR_D_SHIFT (0u) - -#define MTU2_TDDR_D_SHIFT (0u) - -#define MTU2_TCNTS_D_SHIFT (0u) - -#define MTU2_TCBR_D_SHIFT (0u) - -#define MTU2_TGRC_3_D_SHIFT (0u) - -#define MTU2_TGRD_3_D_SHIFT (0u) - -#define MTU2_TGRC_4_D_SHIFT (0u) - -#define MTU2_TGRD_4_D_SHIFT (0u) - -#define MTU2_TSR_3_TGFC_SHIFT (2u) -#define MTU2_TSR_3_TGFD_SHIFT (3u) -#define MTU2_TSR_3_TCFD_SHIFT (7u) - -#define MTU2_TSR_4_TGFC_SHIFT (2u) -#define MTU2_TSR_4_TGFD_SHIFT (3u) -#define MTU2_TSR_4_TCFD_SHIFT (7u) - -#define MTU2_TITCR_4VCOR_SHIFT (0u) -#define MTU2_TITCR_T4VEN_SHIFT (3u) -#define MTU2_TITCR_3ACOR_SHIFT (4u) -#define MTU2_TITCR_T3AEN_SHIFT (7u) - -#define MTU2_TITCNT_4VCNT_SHIFT (0u) -#define MTU2_TITCNT_3ACNT_SHIFT (4u) - -#define MTU2_TBTER_BTE_SHIFT (0u) - -#define MTU2_TDER_TDER_SHIFT (0u) - -#define MTU2_TOLBR_OLS1P_SHIFT (0u) -#define MTU2_TOLBR_OLS1N_SHIFT (1u) -#define MTU2_TOLBR_OLS2P_SHIFT (2u) -#define MTU2_TOLBR_OLS2N_SHIFT (3u) -#define MTU2_TOLBR_OLS3P_SHIFT (4u) -#define MTU2_TOLBR_OLS3N_SHIFT (5u) - -#define MTU2_TBTM_3_TTSA_SHIFT (0u) -#define MTU2_TBTM_3_TTSB_SHIFT (1u) - -#define MTU2_TBTM_4_TTSA_SHIFT (0u) -#define MTU2_TBTM_4_TTSB_SHIFT (1u) - -#define MTU2_TADCR_ITB4VE_SHIFT (0u) -#define MTU2_TADCR_ITB3AE_SHIFT (1u) -#define MTU2_TADCR_ITA4VE_SHIFT (2u) -#define MTU2_TADCR_ITA3AE_SHIFT (3u) -#define MTU2_TADCR_DT4BE_SHIFT (4u) -#define MTU2_TADCR_UT4BE_SHIFT (5u) -#define MTU2_TADCR_DT4AE_SHIFT (6u) -#define MTU2_TADCR_UT4AE_SHIFT (7u) -#define MTU2_TADCR_BF_SHIFT (14u) - -#define MTU2_TADCORA_4_D_SHIFT (0u) - -#define MTU2_TADCORB_4_D_SHIFT (0u) - -#define MTU2_TADCOBRA_4_D_SHIFT (0u) - -#define MTU2_TADCOBRB_4_D_SHIFT (0u) - -#define MTU2_TWCR_WRE_SHIFT (0u) -#define MTU2_TWCR_CCE_SHIFT (7u) - -#define MTU2_TSTR_CST0_SHIFT (0u) -#define MTU2_TSTR_CST1_SHIFT (1u) -#define MTU2_TSTR_CST2_SHIFT (2u) -#define MTU2_TSTR_CST3_SHIFT (6u) -#define MTU2_TSTR_CST4_SHIFT (7u) - -#define MTU2_TSYR_SYNC0_SHIFT (0u) -#define MTU2_TSYR_SYNC1_SHIFT (1u) -#define MTU2_TSYR_SYNC2_SHIFT (2u) -#define MTU2_TSYR_SYNC3_SHIFT (6u) -#define MTU2_TSYR_SYNC4_SHIFT (7u) - -#define MTU2_TRWER_RWE_SHIFT (0u) - -#define MTU2_TMDR_0_BFA_SHIFT (4u) -#define MTU2_TMDR_0_BFB_SHIFT (5u) -#define MTU2_TMDR_0_BFE_SHIFT (6u) - -#define MTU2_TIORH_0_IOA_SHIFT (0u) -#define MTU2_TIORH_0_IOB_SHIFT (4u) - -#define MTU2_TIORL_0_IOC_SHIFT (0u) -#define MTU2_TIORL_0_IOD_SHIFT (4u) - -#define MTU2_TIER_0_TGIEC_SHIFT (2u) -#define MTU2_TIER_0_TGIED_SHIFT (3u) - -#define MTU2_TSR_0_TGFC_SHIFT (2u) -#define MTU2_TSR_0_TGFD_SHIFT (3u) - -#define MTU2_TGRC_0_D_SHIFT (0u) - -#define MTU2_TGRD_0_D_SHIFT (0u) - -#define MTU2_TGRE_0_D_SHIFT (0u) - -#define MTU2_TGRF_0_D_SHIFT (0u) - -#define MTU2_TIER2_0_TGIEE_SHIFT (0u) -#define MTU2_TIER2_0_TGIEF_SHIFT (1u) - -#define MTU2_TSR2_0_TGFE_SHIFT (0u) -#define MTU2_TSR2_0_TGFF_SHIFT (1u) - -#define MTU2_TBTM_0_TTSA_SHIFT (0u) -#define MTU2_TBTM_0_TTSB_SHIFT (1u) -#define MTU2_TBTM_0_TTSE_SHIFT (2u) - -#define MTU2_TIOR_1_IOA_SHIFT (0u) -#define MTU2_TIOR_1_IOB_SHIFT (4u) - -#define MTU2_TIER_1_TCIEU_SHIFT (5u) - -#define MTU2_TSR_1_TCFU_SHIFT (5u) -#define MTU2_TSR_1_TCFD_SHIFT (7u) - -#define MTU2_TICCR_I1AE_SHIFT (0u) -#define MTU2_TICCR_I1BE_SHIFT (1u) -#define MTU2_TICCR_I2AE_SHIFT (2u) -#define MTU2_TICCR_I2BE_SHIFT (3u) - - -#endif /* MTU2_IOBITMASK_H */ -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h deleted file mode 100644 index 418bca70a43..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h +++ /dev/null @@ -1,123 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : ostm_iobitmask.h -* $Rev: 1115 $ -* $Date:: 2014-07-09 15:35:02 +0900#$ -* Description : OSTM register define header -*******************************************************************************/ -#ifndef OSTM_IOBITMASK_H -#define OSTM_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -/* ---- OSTM0 ---- */ -#define OSTM0_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) - -#define OSTM0_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) - -#define OSTM0_OSTMnTE_OSTMnTE (0x01u) - -#define OSTM0_OSTMnTS_OSTMnTS (0x01u) - -#define OSTM0_OSTMnTT_OSTMnTT (0x01u) - -#define OSTM0_OSTMnCTL_MD0 (0x00000001uL) -#define OSTM0_OSTMnCTL_MD1 (0x00000002uL) - -/* ---- OSTM1 ---- */ -#define OSTM1_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) - -#define OSTM1_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) - -#define OSTM1_OSTMnTE_OSTMnTE (0x01u) - -#define OSTM1_OSTMnTS_OSTMnTS (0x01u) - -#define OSTM1_OSTMnTT_OSTMnTT (0x01u) - -#define OSTM1_OSTMnCTL_MD0 (0x00000001uL) -#define OSTM1_OSTMnCTL_MD1 (0x00000002uL) - -/* ---- OSTMn ---- */ -#define OSTMn_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) - -#define OSTMn_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) - -#define OSTMn_OSTMnTE_OSTMnTE (0x01u) - -#define OSTMn_OSTMnTS_OSTMnTS (0x01u) - -#define OSTMn_OSTMnTT_OSTMnTT (0x01u) - -#define OSTMn_OSTMnCTL_MD0 (0x00000001uL) -#define OSTMn_OSTMnCTL_MD1 (0x00000002uL) - - -/* ==== Shift values for IO registers ==== */ -/* ---- OSTM0 ---- */ -#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT (0u) - -#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT (0u) - -#define OSTM0_OSTMnTE_OSTMnTE_SHIFT (0u) - -#define OSTM0_OSTMnTS_OSTMnTS_SHIFT (0u) - -#define OSTM0_OSTMnTT_OSTMnTT_SHIFT (0u) - -#define OSTM0_OSTMnCTL_MD0_SHIFT (0u) -#define OSTM0_OSTMnCTL_MD1_SHIFT (1u) - -/* ---- OSTM1 ---- */ -#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT (0u) - -#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT (0u) - -#define OSTM1_OSTMnTE_OSTMnTE_SHIFT (0u) - -#define OSTM1_OSTMnTS_OSTMnTS_SHIFT (0u) - -#define OSTM1_OSTMnTT_OSTMnTT_SHIFT (0u) - -#define OSTM1_OSTMnCTL_MD0_SHIFT (0u) -#define OSTM1_OSTMnCTL_MD1_SHIFT (1u) - -/* ---- OSTMn ---- */ -#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT (0u) - -#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT (0u) - -#define OSTMn_OSTMnTE_OSTMnTE_SHIFT (0u) - -#define OSTMn_OSTMnTS_OSTMnTS_SHIFT (0u) - -#define OSTMn_OSTMnTT_OSTMnTT_SHIFT (0u) - -#define OSTMn_OSTMnCTL_MD0_SHIFT (0u) -#define OSTMn_OSTMnCTL_MD1_SHIFT (1u) - - -#endif /* OSTM_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h deleted file mode 100644 index 8a2a8713342..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h +++ /dev/null @@ -1,231 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : riic_iobitmask.h -* $Rev: 1114 $ -* $Date:: 2014-07-09 14:56:39 +0900#$ -* Description : RIIC register define header -*******************************************************************************/ -#ifndef RIIC_IOBITMASK_H -#define RIIC_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -#define RIICn_RIICnCR1_SDAI (0x01u) -#define RIICn_RIICnCR1_SCLI (0x02u) -#define RIICn_RIICnCR1_SDAO (0x04u) -#define RIICn_RIICnCR1_SCLO (0x08u) -#define RIICn_RIICnCR1_SOWP (0x10u) -#define RIICn_RIICnCR1_CLO (0x20u) -#define RIICn_RIICnCR1_IICRST (0x40u) -#define RIICn_RIICnCR1_ICE (0x80u) - -#define RIICn_RIICnCR2_ST (0x02u) -#define RIICn_RIICnCR2_RS (0x04u) -#define RIICn_RIICnCR2_SP (0x08u) -#define RIICn_RIICnCR2_TRS (0x20u) -#define RIICn_RIICnCR2_MST (0x40u) -#define RIICn_RIICnCR2_BBSY (0x80u) - -#define RIICn_RIICnMR1_BC (0x07u) -#define RIICn_RIICnMR1_BCWP (0x08u) -#define RIICn_RIICnMR1_CKS (0x70u) -#define RIICn_RIICnMR1_MTWP (0x80u) - -#define RIICn_RIICnMR2_TMOS (0x01u) -#define RIICn_RIICnMR2_TMOL (0x02u) -#define RIICn_RIICnMR2_TMOH (0x04u) -#define RIICn_RIICnMR2_SDDL (0x70u) -#define RIICn_RIICnMR2_DLCS (0x80u) - -#define RIICn_RIICnMR3_NF (0x03u) -#define RIICn_RIICnMR3_ACKBR (0x04u) -#define RIICn_RIICnMR3_ACKBT (0x08u) -#define RIICn_RIICnMR3_ACKWP (0x10u) -#define RIICn_RIICnMR3_RDRFS (0x20u) -#define RIICn_RIICnMR3_WAIT (0x40u) -#define RIICn_RIICnMR3_SMBS (0x80u) - -#define RIICn_RIICnFER_TMOE (0x01u) -#define RIICn_RIICnFER_MALE (0x02u) -#define RIICn_RIICnFER_NALE (0x04u) -#define RIICn_RIICnFER_SALE (0x08u) -#define RIICn_RIICnFER_NACKE (0x10u) -#define RIICn_RIICnFER_NFE (0x20u) -#define RIICn_RIICnFER_SCLE (0x40u) -#define RIICn_RIICnFER_FMPE (0x80u) - -#define RIICn_RIICnSER_SAR0E (0x01u) -#define RIICn_RIICnSER_SAR1E (0x02u) -#define RIICn_RIICnSER_SAR2E (0x04u) -#define RIICn_RIICnSER_GCAE (0x08u) -#define RIICn_RIICnSER_DIDE (0x20u) -#define RIICn_RIICnSER_HOAE (0x80u) - -#define RIICn_RIICnIER_TMOIE (0x01u) -#define RIICn_RIICnIER_ALIE (0x02u) -#define RIICn_RIICnIER_STIE (0x04u) -#define RIICn_RIICnIER_SPIE (0x08u) -#define RIICn_RIICnIER_NAKIE (0x10u) -#define RIICn_RIICnIER_RIE (0x20u) -#define RIICn_RIICnIER_TEIE (0x40u) -#define RIICn_RIICnIER_TIE (0x80u) - -#define RIICn_RIICnSR1_AAS0 (0x01u) -#define RIICn_RIICnSR1_AAS1 (0x02u) -#define RIICn_RIICnSR1_AAS2 (0x04u) -#define RIICn_RIICnSR1_GCA (0x08u) -#define RIICn_RIICnSR1_DID (0x20u) -#define RIICn_RIICnSR1_HOA (0x80u) - -#define RIICn_RIICnSR2_TMOF (0x01u) -#define RIICn_RIICnSR2_AL (0x02u) -#define RIICn_RIICnSR2_START (0x04u) -#define RIICn_RIICnSR2_STOP (0x08u) -#define RIICn_RIICnSR2_NACKF (0x10u) -#define RIICn_RIICnSR2_RDRF (0x20u) -#define RIICn_RIICnSR2_TEND (0x40u) -#define RIICn_RIICnSR2_TDRE (0x80u) - -#define RIICn_RIICnSAR0_SVA0 (0x0001u) -#define RIICn_RIICnSAR0_SVA (0x03FEu) -#define RIICn_RIICnSAR0_FSy (0x8000u) - -#define RIICn_RIICnSAR1_SVA0 (0x0001u) -#define RIICn_RIICnSAR1_SVA (0x03FEu) -#define RIICn_RIICnSAR1_FSy (0x8000u) - -#define RIICn_RIICnSAR2_SVA0 (0x0001u) -#define RIICn_RIICnSAR2_SVA (0x03FEu) -#define RIICn_RIICnSAR2_FSy (0x8000u) - -#define RIICn_RIICnBRL_BRL (0x1Fu) - -#define RIICn_RIICnBRH_BRH (0x1Fu) - -#define RIICn_RIICnDRT_DRT (0xFFu) - -#define RIICn_RIICnDRR_DRR (0xFFu) - - -/* ==== Shift values for IO registers ==== */ -#define RIICn_RIICnCR1_SDAI_SHIFT (0u) -#define RIICn_RIICnCR1_SCLI_SHIFT (1u) -#define RIICn_RIICnCR1_SDAO_SHIFT (2u) -#define RIICn_RIICnCR1_SCLO_SHIFT (3u) -#define RIICn_RIICnCR1_SOWP_SHIFT (4u) -#define RIICn_RIICnCR1_CLO_SHIFT (5u) -#define RIICn_RIICnCR1_IICRST_SHIFT (6u) -#define RIICn_RIICnCR1_ICE_SHIFT (7u) - -#define RIICn_RIICnCR2_ST_SHIFT (1u) -#define RIICn_RIICnCR2_RS_SHIFT (2u) -#define RIICn_RIICnCR2_SP_SHIFT (3u) -#define RIICn_RIICnCR2_TRS_SHIFT (5u) -#define RIICn_RIICnCR2_MST_SHIFT (6u) -#define RIICn_RIICnCR2_BBSY_SHIFT (7u) - -#define RIICn_RIICnMR1_BC_SHIFT (0u) -#define RIICn_RIICnMR1_BCWP_SHIFT (3u) -#define RIICn_RIICnMR1_CKS_SHIFT (4u) -#define RIICn_RIICnMR1_MTWP_SHIFT (7u) - -#define RIICn_RIICnMR2_TMOS_SHIFT (0u) -#define RIICn_RIICnMR2_TMOL_SHIFT (1u) -#define RIICn_RIICnMR2_TMOH_SHIFT (2u) -#define RIICn_RIICnMR2_SDDL_SHIFT (4u) -#define RIICn_RIICnMR2_DLCS_SHIFT (7u) - -#define RIICn_RIICnMR3_NF_SHIFT (0u) -#define RIICn_RIICnMR3_ACKBR_SHIFT (2u) -#define RIICn_RIICnMR3_ACKBT_SHIFT (3u) -#define RIICn_RIICnMR3_ACKWP_SHIFT (4u) -#define RIICn_RIICnMR3_RDRFS_SHIFT (5u) -#define RIICn_RIICnMR3_WAIT_SHIFT (6u) -#define RIICn_RIICnMR3_SMBS_SHIFT (7u) - -#define RIICn_RIICnFER_TMOE_SHIFT (0u) -#define RIICn_RIICnFER_MALE_SHIFT (1u) -#define RIICn_RIICnFER_NALE_SHIFT (2u) -#define RIICn_RIICnFER_SALE_SHIFT (3u) -#define RIICn_RIICnFER_NACKE_SHIFT (4u) -#define RIICn_RIICnFER_NFE_SHIFT (5u) -#define RIICn_RIICnFER_SCLE_SHIFT (6u) -#define RIICn_RIICnFER_FMPE_SHIFT (7u) - -#define RIICn_RIICnSER_SAR0E_SHIFT (0u) -#define RIICn_RIICnSER_SAR1E_SHIFT (1u) -#define RIICn_RIICnSER_SAR2E_SHIFT (2u) -#define RIICn_RIICnSER_GCAE_SHIFT (3u) -#define RIICn_RIICnSER_DIDE_SHIFT (5u) -#define RIICn_RIICnSER_HOAE_SHIFT (7u) - -#define RIICn_RIICnIER_TMOIE_SHIFT (0u) -#define RIICn_RIICnIER_ALIE_SHIFT (1u) -#define RIICn_RIICnIER_STIE_SHIFT (2u) -#define RIICn_RIICnIER_SPIE_SHIFT (3u) -#define RIICn_RIICnIER_NAKIE_SHIFT (4u) -#define RIICn_RIICnIER_RIE_SHIFT (5u) -#define RIICn_RIICnIER_TEIE_SHIFT (6u) -#define RIICn_RIICnIER_TIE_SHIFT (7u) - -#define RIICn_RIICnSR1_AAS0_SHIFT (0u) -#define RIICn_RIICnSR1_AAS1_SHIFT (1u) -#define RIICn_RIICnSR1_AAS2_SHIFT (2u) -#define RIICn_RIICnSR1_GCA_SHIFT (3u) -#define RIICn_RIICnSR1_DID_SHIFT (5u) -#define RIICn_RIICnSR1_HOA_SHIFT (7u) - -#define RIICn_RIICnSR2_TMOF_SHIFT (0u) -#define RIICn_RIICnSR2_AL_SHIFT (1u) -#define RIICn_RIICnSR2_START_SHIFT (2u) -#define RIICn_RIICnSR2_STOP_SHIFT (3u) -#define RIICn_RIICnSR2_NACKF_SHIFT (4u) -#define RIICn_RIICnSR2_RDRF_SHIFT (5u) -#define RIICn_RIICnSR2_TEND_SHIFT (6u) -#define RIICn_RIICnSR2_TDRE_SHIFT (7u) - -#define RIICn_RIICnSAR0_SVA0_SHIFT (0u) -#define RIICn_RIICnSAR0_SVA_SHIFT (1u) -#define RIICn_RIICnSAR0_FSy_SHIFT (15u) - -#define RIICn_RIICnSAR1_SVA0_SHIFT (0u) -#define RIICn_RIICnSAR1_SVA_SHIFT (1u) -#define RIICn_RIICnSAR1_FSy_SHIFT (15u) - -#define RIICn_RIICnSAR2_SVA0_SHIFT (0u) -#define RIICn_RIICnSAR2_SVA_SHIFT (1u) -#define RIICn_RIICnSAR2_FSy_SHIFT (15u) - -#define RIICn_RIICnBRL_BRL_SHIFT (0u) - -#define RIICn_RIICnBRH_BRH_SHIFT (0u) - -#define RIICn_RIICnDRT_DRT_SHIFT (0u) - -#define RIICn_RIICnDRR_DRR_SHIFT (0u) - - -#endif /* RIIC_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h deleted file mode 100644 index ca1ba2e8ad7..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h +++ /dev/null @@ -1,215 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rspi_iobitmask.h -* $Rev: 1114 $ -* $Date:: 2014-07-09 14:56:39 +0900#$ -* Description : Renesas Serial Peripheral Interface register define header -*******************************************************************************/ -#ifndef RSPI_IOBITMASK_H -#define RSPI_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -#define RSPIn_SPCR_MODFEN (0x04u) -#define RSPIn_SPCR_MSTR (0x08u) -#define RSPIn_SPCR_SPEIE (0x10u) -#define RSPIn_SPCR_SPTIE (0x20u) -#define RSPIn_SPCR_SPE (0x40u) -#define RSPIn_SPCR_SPRIE (0x80u) - -#define RSPIn_SSLP_SSL0P (0x01u) - -#define RSPIn_SPPCR_SPLP (0x01u) -#define RSPIn_SPPCR_MOIFV (0x10u) -#define RSPIn_SPPCR_MOIFE (0x20u) - -#define RSPIn_SPSR_OVRF (0x01u) -#define RSPIn_SPSR_MODF (0x04u) -#define RSPIn_SPSR_SPTEF (0x20u) -#define RSPIn_SPSR_TEND (0x40u) -#define RSPIn_SPSR_SPRF (0x80u) - -#define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL) - -#define RSPIn_SPDR_UINT16 (0xFFFFu) - -#define RSPIn_SPDR_UINT8 (0xFFu) - -#define RSPIn_SPSCR_SPSLN (0x03u) - -#define RSPIn_SPSSR_SPCP (0x03u) - -#define RSPIn_SPBR_SPR (0xFFu) - -#define RSPIn_SPDCR_SPLW (0x60u) -#define RSPIn_SPDCR_TXDMY (0x80u) - -#define RSPIn_SPCKD_SCKDL (0x07u) - -#define RSPIn_SSLND_SLNDL (0x07u) - -#define RSPIn_SPND_SPNDL (0x07u) - -#define RSPIn_SPCMD0_CPHA (0x0001u) -#define RSPIn_SPCMD0_CPOL (0x0002u) -#define RSPIn_SPCMD0_BRDV (0x000Cu) -#define RSPIn_SPCMD0_SSLKP (0x0080u) -#define RSPIn_SPCMD0_SPB (0x0F00u) -#define RSPIn_SPCMD0_LSBF (0x1000u) -#define RSPIn_SPCMD0_SPNDEN (0x2000u) -#define RSPIn_SPCMD0_SLNDEN (0x4000u) -#define RSPIn_SPCMD0_SCKDEN (0x8000u) - -#define RSPIn_SPCMD1_CPHA (0x0001u) -#define RSPIn_SPCMD1_CPOL (0x0002u) -#define RSPIn_SPCMD1_BRDV (0x000Cu) -#define RSPIn_SPCMD1_SSLKP (0x0080u) -#define RSPIn_SPCMD1_SPB (0x0F00u) -#define RSPIn_SPCMD1_LSBF (0x1000u) -#define RSPIn_SPCMD1_SPNDEN (0x2000u) -#define RSPIn_SPCMD1_SLNDEN (0x4000u) -#define RSPIn_SPCMD1_SCKDEN (0x8000u) - -#define RSPIn_SPCMD2_CPHA (0x0001u) -#define RSPIn_SPCMD2_CPOL (0x0002u) -#define RSPIn_SPCMD2_BRDV (0x000Cu) -#define RSPIn_SPCMD2_SSLKP (0x0080u) -#define RSPIn_SPCMD2_SPB (0x0F00u) -#define RSPIn_SPCMD2_LSBF (0x1000u) -#define RSPIn_SPCMD2_SPNDEN (0x2000u) -#define RSPIn_SPCMD2_SLNDEN (0x4000u) -#define RSPIn_SPCMD2_SCKDEN (0x8000u) - -#define RSPIn_SPCMD3_CPHA (0x0001u) -#define RSPIn_SPCMD3_CPOL (0x0002u) -#define RSPIn_SPCMD3_BRDV (0x000Cu) -#define RSPIn_SPCMD3_SSLKP (0x0080u) -#define RSPIn_SPCMD3_SPB (0x0F00u) -#define RSPIn_SPCMD3_LSBF (0x1000u) -#define RSPIn_SPCMD3_SPNDEN (0x2000u) -#define RSPIn_SPCMD3_SLNDEN (0x4000u) -#define RSPIn_SPCMD3_SCKDEN (0x8000u) - -#define RSPIn_SPBFCR_RXTRG (0x07u) -#define RSPIn_SPBFCR_TXTRG (0x30u) -#define RSPIn_SPBFCR_RXRST (0x40u) -#define RSPIn_SPBFCR_TXRST (0x80u) - -#define RSPIn_SPBFDR_R (0x003Fu) -#define RSPIn_SPBFDR_T (0x0F00u) - - -/* ==== Shift values for IO registers ==== */ -#define RSPIn_SPCR_MODFEN_SHIFT (2u) -#define RSPIn_SPCR_MSTR_SHIFT (3u) -#define RSPIn_SPCR_SPEIE_SHIFT (4u) -#define RSPIn_SPCR_SPTIE_SHIFT (5u) -#define RSPIn_SPCR_SPE_SHIFT (6u) -#define RSPIn_SPCR_SPRIE_SHIFT (7u) - -#define RSPIn_SSLP_SSL0P_SHIFT (0u) - -#define RSPIn_SPPCR_SPLP_SHIFT (0u) -#define RSPIn_SPPCR_MOIFV_SHIFT (4u) -#define RSPIn_SPPCR_MOIFE_SHIFT (5u) - -#define RSPIn_SPSR_OVRF_SHIFT (0u) -#define RSPIn_SPSR_MODF_SHIFT (2u) -#define RSPIn_SPSR_SPTEF_SHIFT (5u) -#define RSPIn_SPSR_TEND_SHIFT (6u) -#define RSPIn_SPSR_SPRF_SHIFT (7u) - -#define RSPIn_SPDR_UINT32_SHIFT (0u) - -#define RSPIn_SPDR_UINT16_SHIFT (0u) - -#define RSPIn_SPDR_UINT8_SHIFT (0u) - -#define RSPIn_SPSCR_SPSLN_SHIFT (0u) - -#define RSPIn_SPSSR_SPCP_SHIFT (0u) - -#define RSPIn_SPBR_SPR_SHIFT (0u) - -#define RSPIn_SPDCR_SPLW_SHIFT (5u) -#define RSPIn_SPDCR_TXDMY_SHIFT (7u) - -#define RSPIn_SPCKD_SCKDL_SHIFT (0u) - -#define RSPIn_SSLND_SLNDL_SHIFT (0u) - -#define RSPIn_SPND_SPNDL_SHIFT (0u) - -#define RSPIn_SPCMD0_CPHA_SHIFT (0u) -#define RSPIn_SPCMD0_CPOL_SHIFT (1u) -#define RSPIn_SPCMD0_BRDV_SHIFT (2u) -#define RSPIn_SPCMD0_SSLKP_SHIFT (7u) -#define RSPIn_SPCMD0_SPB_SHIFT (8u) -#define RSPIn_SPCMD0_LSBF_SHIFT (12u) -#define RSPIn_SPCMD0_SPNDEN_SHIFT (13u) -#define RSPIn_SPCMD0_SLNDEN_SHIFT (14u) -#define RSPIn_SPCMD0_SCKDEN_SHIFT (15u) - -#define RSPIn_SPCMD1_CPHA_SHIFT (0u) -#define RSPIn_SPCMD1_CPOL_SHIFT (1u) -#define RSPIn_SPCMD1_BRDV_SHIFT (2u) -#define RSPIn_SPCMD1_SSLKP_SHIFT (7u) -#define RSPIn_SPCMD1_SPB_SHIFT (8u) -#define RSPIn_SPCMD1_LSBF_SHIFT (12u) -#define RSPIn_SPCMD1_SPNDEN_SHIFT (13u) -#define RSPIn_SPCMD1_SLNDEN_SHIFT (14u) -#define RSPIn_SPCMD1_SCKDEN_SHIFT (15u) - -#define RSPIn_SPCMD2_CPHA_SHIFT (0u) -#define RSPIn_SPCMD2_CPOL_SHIFT (1u) -#define RSPIn_SPCMD2_BRDV_SHIFT (2u) -#define RSPIn_SPCMD2_SSLKP_SHIFT (7u) -#define RSPIn_SPCMD2_SPB_SHIFT (8u) -#define RSPIn_SPCMD2_LSBF_SHIFT (12u) -#define RSPIn_SPCMD2_SPNDEN_SHIFT (13u) -#define RSPIn_SPCMD2_SLNDEN_SHIFT (14u) -#define RSPIn_SPCMD2_SCKDEN_SHIFT (15u) - -#define RSPIn_SPCMD3_CPHA_SHIFT (0u) -#define RSPIn_SPCMD3_CPOL_SHIFT (1u) -#define RSPIn_SPCMD3_BRDV_SHIFT (2u) -#define RSPIn_SPCMD3_SSLKP_SHIFT (7u) -#define RSPIn_SPCMD3_SPB_SHIFT (8u) -#define RSPIn_SPCMD3_LSBF_SHIFT (12u) -#define RSPIn_SPCMD3_SPNDEN_SHIFT (13u) -#define RSPIn_SPCMD3_SLNDEN_SHIFT (14u) -#define RSPIn_SPCMD3_SCKDEN_SHIFT (15u) - -#define RSPIn_SPBFCR_RXTRG_SHIFT (0u) -#define RSPIn_SPBFCR_TXTRG_SHIFT (4u) -#define RSPIn_SPBFCR_RXRST_SHIFT (6u) -#define RSPIn_SPBFCR_TXRST_SHIFT (7u) - -#define RSPIn_SPBFDR_R_SHIFT (0u) -#define RSPIn_SPBFDR_T_SHIFT (8u) - - -#endif /* RSPI_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h deleted file mode 100644 index a545d6b4ab2..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h +++ /dev/null @@ -1,1065 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : scif_iobitmask.h -* $Rev: 1115 $ -* $Date:: 2014-07-09 15:35:02 +0900#$ -* Description : SCIF register define header -*******************************************************************************/ -#ifndef SCIF_IOBITMASK_H -#define SCIF_IOBITMASK_H - - -/* ==== Mask values for IO registers ==== */ -/* ---- SCIF0 ---- */ -#define SCIF0_SCSMR_CKS (0x0003u) -#define SCIF0_SCSMR_STOP (0x0008u) -#define SCIF0_SCSMR_OE (0x0010u) -#define SCIF0_SCSMR_PE (0x0020u) -#define SCIF0_SCSMR_CHR (0x0040u) -#define SCIF0_SCSMR_CA (0x0080u) - -#define SCIF0_SCBRR_D (0xFFu) - -#define SCIF0_SCSCR_CKE (0x0003u) -#define SCIF0_SCSCR_REIE (0x0008u) -#define SCIF0_SCSCR_RE (0x0010u) -#define SCIF0_SCSCR_TE (0x0020u) -#define SCIF0_SCSCR_RIE (0x0040u) -#define SCIF0_SCSCR_TIE (0x0080u) - -#define SCIF0_SCFTDR_D (0xFFu) - -#define SCIF0_SCFSR_DR (0x0001u) -#define SCIF0_SCFSR_RDF (0x0002u) -#define SCIF0_SCFSR_PER (0x0004u) -#define SCIF0_SCFSR_FER (0x0008u) -#define SCIF0_SCFSR_BRK (0x0010u) -#define SCIF0_SCFSR_TDFE (0x0020u) -#define SCIF0_SCFSR_TEND (0x0040u) -#define SCIF0_SCFSR_ER (0x0080u) -#define SCIF0_SCFSR_FERN (0x0F00u) -#define SCIF0_SCFSR_PERN (0xF000u) - -#define SCIF0_SCFRDR_D (0xFFu) - -#define SCIF0_SCFCR_LOOP (0x0001u) -#define SCIF0_SCFCR_RFRST (0x0002u) -#define SCIF0_SCFCR_TFRST (0x0004u) -#define SCIF0_SCFCR_MCE (0x0008u) -#define SCIF0_SCFCR_TTRG (0x0030u) -#define SCIF0_SCFCR_RTRG (0x00C0u) -#define SCIF0_SCFCR_RSTRG (0x0700u) - -#define SCIF0_SCFDR_R (0x001Fu) -#define SCIF0_SCFDR_T (0x1F00u) - -#define SCIF0_SCSPTR_SPB2DT (0x0001u) -#define SCIF0_SCSPTR_SPB2IO (0x0002u) -#define SCIF0_SCSPTR_SCKDT (0x0004u) -#define SCIF0_SCSPTR_SCKIO (0x0008u) -#define SCIF0_SCSPTR_CTSDT (0x0010u) -#define SCIF0_SCSPTR_CTSIO (0x0020u) -#define SCIF0_SCSPTR_RTSDT (0x0040u) -#define SCIF0_SCSPTR_RTSIO (0x0080u) - -#define SCIF0_SCLSR_ORER (0x0001u) - -#define SCIF0_SCEMR_ABCS (0x0001u) -#define SCIF0_SCEMR_BGDM (0x0080u) - -/* ---- SCIF1 ---- */ -#define SCIF1_SCSMR_CKS (0x0003u) -#define SCIF1_SCSMR_STOP (0x0008u) -#define SCIF1_SCSMR_OE (0x0010u) -#define SCIF1_SCSMR_PE (0x0020u) -#define SCIF1_SCSMR_CHR (0x0040u) -#define SCIF1_SCSMR_CA (0x0080u) - -#define SCIF1_SCBRR_D (0xFFu) - -#define SCIF1_SCSCR_CKE (0x0003u) -#define SCIF1_SCSCR_REIE (0x0008u) -#define SCIF1_SCSCR_RE (0x0010u) -#define SCIF1_SCSCR_TE (0x0020u) -#define SCIF1_SCSCR_RIE (0x0040u) -#define SCIF1_SCSCR_TIE (0x0080u) - -#define SCIF1_SCFTDR_D (0xFFu) - -#define SCIF1_SCFSR_DR (0x0001u) -#define SCIF1_SCFSR_RDF (0x0002u) -#define SCIF1_SCFSR_PER (0x0004u) -#define SCIF1_SCFSR_FER (0x0008u) -#define SCIF1_SCFSR_BRK (0x0010u) -#define SCIF1_SCFSR_TDFE (0x0020u) -#define SCIF1_SCFSR_TEND (0x0040u) -#define SCIF1_SCFSR_ER (0x0080u) -#define SCIF1_SCFSR_FERN (0x0F00u) -#define SCIF1_SCFSR_PERN (0xF000u) - -#define SCIF1_SCFRDR_D (0xFFu) - -#define SCIF1_SCFCR_LOOP (0x0001u) -#define SCIF1_SCFCR_RFRST (0x0002u) -#define SCIF1_SCFCR_TFRST (0x0004u) -#define SCIF1_SCFCR_MCE (0x0008u) -#define SCIF1_SCFCR_TTRG (0x0030u) -#define SCIF1_SCFCR_RTRG (0x00C0u) -#define SCIF1_SCFCR_RSTRG (0x0700u) - -#define SCIF1_SCFDR_R (0x001Fu) -#define SCIF1_SCFDR_T (0x1F00u) - -#define SCIF1_SCSPTR_SPB2DT (0x0001u) -#define SCIF1_SCSPTR_SPB2IO (0x0002u) -#define SCIF1_SCSPTR_SCKDT (0x0004u) -#define SCIF1_SCSPTR_SCKIO (0x0008u) -#define SCIF1_SCSPTR_CTSDT (0x0010u) -#define SCIF1_SCSPTR_CTSIO (0x0020u) -#define SCIF1_SCSPTR_RTSDT (0x0040u) -#define SCIF1_SCSPTR_RTSIO (0x0080u) - -#define SCIF1_SCLSR_ORER (0x0001u) - -#define SCIF1_SCEMR_ABCS (0x0001u) -#define SCIF1_SCEMR_BGDM (0x0080u) - -/* ---- SCIF2 ---- */ -#define SCIF2_SCSMR_CKS (0x0003u) -#define SCIF2_SCSMR_STOP (0x0008u) -#define SCIF2_SCSMR_OE (0x0010u) -#define SCIF2_SCSMR_PE (0x0020u) -#define SCIF2_SCSMR_CHR (0x0040u) -#define SCIF2_SCSMR_CA (0x0080u) - -#define SCIF2_SCBRR_D (0xFFu) - -#define SCIF2_SCSCR_CKE (0x0003u) -#define SCIF2_SCSCR_REIE (0x0008u) -#define SCIF2_SCSCR_RE (0x0010u) -#define SCIF2_SCSCR_TE (0x0020u) -#define SCIF2_SCSCR_RIE (0x0040u) -#define SCIF2_SCSCR_TIE (0x0080u) - -#define SCIF2_SCFTDR_D (0xFFu) - -#define SCIF2_SCFSR_DR (0x0001u) -#define SCIF2_SCFSR_RDF (0x0002u) -#define SCIF2_SCFSR_PER (0x0004u) -#define SCIF2_SCFSR_FER (0x0008u) -#define SCIF2_SCFSR_BRK (0x0010u) -#define SCIF2_SCFSR_TDFE (0x0020u) -#define SCIF2_SCFSR_TEND (0x0040u) -#define SCIF2_SCFSR_ER (0x0080u) -#define SCIF2_SCFSR_FERN (0x0F00u) -#define SCIF2_SCFSR_PERN (0xF000u) - -#define SCIF2_SCFRDR_D (0xFFu) - -#define SCIF2_SCFCR_LOOP (0x0001u) -#define SCIF2_SCFCR_RFRST (0x0002u) -#define SCIF2_SCFCR_TFRST (0x0004u) -#define SCIF2_SCFCR_MCE (0x0008u) -#define SCIF2_SCFCR_TTRG (0x0030u) -#define SCIF2_SCFCR_RTRG (0x00C0u) -#define SCIF2_SCFCR_RSTRG (0x0700u) - -#define SCIF2_SCFDR_R (0x001Fu) -#define SCIF2_SCFDR_T (0x1F00u) - -#define SCIF2_SCSPTR_SPB2DT (0x0001u) -#define SCIF2_SCSPTR_SPB2IO (0x0002u) -#define SCIF2_SCSPTR_SCKDT (0x0004u) -#define SCIF2_SCSPTR_SCKIO (0x0008u) -#define SCIF2_SCSPTR_CTSDT (0x0010u) -#define SCIF2_SCSPTR_CTSIO (0x0020u) -#define SCIF2_SCSPTR_RTSDT (0x0040u) -#define SCIF2_SCSPTR_RTSIO (0x0080u) - -#define SCIF2_SCLSR_ORER (0x0001u) - -#define SCIF2_SCEMR_ABCS (0x0001u) -#define SCIF2_SCEMR_BGDM (0x0080u) - -/* ---- SCIF3 ---- */ -#define SCIF3_SCSMR_CKS (0x0003u) -#define SCIF3_SCSMR_STOP (0x0008u) -#define SCIF3_SCSMR_OE (0x0010u) -#define SCIF3_SCSMR_PE (0x0020u) -#define SCIF3_SCSMR_CHR (0x0040u) -#define SCIF3_SCSMR_CA (0x0080u) - -#define SCIF3_SCBRR_D (0xFFu) - -#define SCIF3_SCSCR_CKE (0x0003u) -#define SCIF3_SCSCR_REIE (0x0008u) -#define SCIF3_SCSCR_RE (0x0010u) -#define SCIF3_SCSCR_TE (0x0020u) -#define SCIF3_SCSCR_RIE (0x0040u) -#define SCIF3_SCSCR_TIE (0x0080u) - -#define SCIF3_SCFTDR_D (0xFFu) - -#define SCIF3_SCFSR_DR (0x0001u) -#define SCIF3_SCFSR_RDF (0x0002u) -#define SCIF3_SCFSR_PER (0x0004u) -#define SCIF3_SCFSR_FER (0x0008u) -#define SCIF3_SCFSR_BRK (0x0010u) -#define SCIF3_SCFSR_TDFE (0x0020u) -#define SCIF3_SCFSR_TEND (0x0040u) -#define SCIF3_SCFSR_ER (0x0080u) -#define SCIF3_SCFSR_FERN (0x0F00u) -#define SCIF3_SCFSR_PERN (0xF000u) - -#define SCIF3_SCFRDR_D (0xFFu) - -#define SCIF3_SCFCR_LOOP (0x0001u) -#define SCIF3_SCFCR_RFRST (0x0002u) -#define SCIF3_SCFCR_TFRST (0x0004u) -#define SCIF3_SCFCR_MCE (0x0008u) -#define SCIF3_SCFCR_TTRG (0x0030u) -#define SCIF3_SCFCR_RTRG (0x00C0u) -#define SCIF3_SCFCR_RSTRG (0x0700u) - -#define SCIF3_SCFDR_R (0x001Fu) -#define SCIF3_SCFDR_T (0x1F00u) - -#define SCIF3_SCSPTR_SPB2DT (0x0001u) -#define SCIF3_SCSPTR_SPB2IO (0x0002u) -#define SCIF3_SCSPTR_SCKDT (0x0004u) -#define SCIF3_SCSPTR_SCKIO (0x0008u) -#define SCIF3_SCSPTR_CTSDT (0x0010u) -#define SCIF3_SCSPTR_CTSIO (0x0020u) -#define SCIF3_SCSPTR_RTSDT (0x0040u) -#define SCIF3_SCSPTR_RTSIO (0x0080u) - -#define SCIF3_SCLSR_ORER (0x0001u) - -#define SCIF3_SCEMR_ABCS (0x0001u) -#define SCIF3_SCEMR_BGDM (0x0080u) - -/* ---- SCIF4 ---- */ -#define SCIF4_SCSMR_CKS (0x0003u) -#define SCIF4_SCSMR_STOP (0x0008u) -#define SCIF4_SCSMR_OE (0x0010u) -#define SCIF4_SCSMR_PE (0x0020u) -#define SCIF4_SCSMR_CHR (0x0040u) -#define SCIF4_SCSMR_CA (0x0080u) - -#define SCIF4_SCBRR_D (0xFFu) - -#define SCIF4_SCSCR_CKE (0x0003u) -#define SCIF4_SCSCR_REIE (0x0008u) -#define SCIF4_SCSCR_RE (0x0010u) -#define SCIF4_SCSCR_TE (0x0020u) -#define SCIF4_SCSCR_RIE (0x0040u) -#define SCIF4_SCSCR_TIE (0x0080u) - -#define SCIF4_SCFTDR_D (0xFFu) - -#define SCIF4_SCFSR_DR (0x0001u) -#define SCIF4_SCFSR_RDF (0x0002u) -#define SCIF4_SCFSR_PER (0x0004u) -#define SCIF4_SCFSR_FER (0x0008u) -#define SCIF4_SCFSR_BRK (0x0010u) -#define SCIF4_SCFSR_TDFE (0x0020u) -#define SCIF4_SCFSR_TEND (0x0040u) -#define SCIF4_SCFSR_ER (0x0080u) -#define SCIF4_SCFSR_FERN (0x0F00u) -#define SCIF4_SCFSR_PERN (0xF000u) - -#define SCIF4_SCFRDR_D (0xFFu) - -#define SCIF4_SCFCR_LOOP (0x0001u) -#define SCIF4_SCFCR_RFRST (0x0002u) -#define SCIF4_SCFCR_TFRST (0x0004u) -#define SCIF4_SCFCR_MCE (0x0008u) -#define SCIF4_SCFCR_TTRG (0x0030u) -#define SCIF4_SCFCR_RTRG (0x00C0u) -#define SCIF4_SCFCR_RSTRG (0x0700u) - -#define SCIF4_SCFDR_R (0x001Fu) -#define SCIF4_SCFDR_T (0x1F00u) - -#define SCIF4_SCSPTR_SPB2DT (0x0001u) -#define SCIF4_SCSPTR_SPB2IO (0x0002u) -#define SCIF4_SCSPTR_SCKDT (0x0004u) -#define SCIF4_SCSPTR_SCKIO (0x0008u) -#define SCIF4_SCSPTR_CTSDT (0x0010u) -#define SCIF4_SCSPTR_CTSIO (0x0020u) -#define SCIF4_SCSPTR_RTSDT (0x0040u) -#define SCIF4_SCSPTR_RTSIO (0x0080u) - -#define SCIF4_SCLSR_ORER (0x0001u) - -#define SCIF4_SCEMR_ABCS (0x0001u) -#define SCIF4_SCEMR_BGDM (0x0080u) - -/* ---- SCIF5 ---- */ -#define SCIF5_SCSMR_CKS (0x0003u) -#define SCIF5_SCSMR_STOP (0x0008u) -#define SCIF5_SCSMR_OE (0x0010u) -#define SCIF5_SCSMR_PE (0x0020u) -#define SCIF5_SCSMR_CHR (0x0040u) -#define SCIF5_SCSMR_CA (0x0080u) - -#define SCIF5_SCBRR_D (0xFFu) - -#define SCIF5_SCSCR_CKE (0x0003u) -#define SCIF5_SCSCR_REIE (0x0008u) -#define SCIF5_SCSCR_RE (0x0010u) -#define SCIF5_SCSCR_TE (0x0020u) -#define SCIF5_SCSCR_RIE (0x0040u) -#define SCIF5_SCSCR_TIE (0x0080u) - -#define SCIF5_SCFTDR_D (0xFFu) - -#define SCIF5_SCFSR_DR (0x0001u) -#define SCIF5_SCFSR_RDF (0x0002u) -#define SCIF5_SCFSR_PER (0x0004u) -#define SCIF5_SCFSR_FER (0x0008u) -#define SCIF5_SCFSR_BRK (0x0010u) -#define SCIF5_SCFSR_TDFE (0x0020u) -#define SCIF5_SCFSR_TEND (0x0040u) -#define SCIF5_SCFSR_ER (0x0080u) -#define SCIF5_SCFSR_FERN (0x0F00u) -#define SCIF5_SCFSR_PERN (0xF000u) - -#define SCIF5_SCFRDR_D (0xFFu) - -#define SCIF5_SCFCR_LOOP (0x0001u) -#define SCIF5_SCFCR_RFRST (0x0002u) -#define SCIF5_SCFCR_TFRST (0x0004u) -#define SCIF5_SCFCR_MCE (0x0008u) -#define SCIF5_SCFCR_TTRG (0x0030u) -#define SCIF5_SCFCR_RTRG (0x00C0u) -#define SCIF5_SCFCR_RSTRG (0x0700u) - -#define SCIF5_SCFDR_R (0x001Fu) -#define SCIF5_SCFDR_T (0x1F00u) - -#define SCIF5_SCSPTR_SPB2DT (0x0001u) -#define SCIF5_SCSPTR_SPB2IO (0x0002u) -#define SCIF5_SCSPTR_SCKDT (0x0004u) -#define SCIF5_SCSPTR_SCKIO (0x0008u) -#define SCIF5_SCSPTR_CTSDT (0x0010u) -#define SCIF5_SCSPTR_CTSIO (0x0020u) -#define SCIF5_SCSPTR_RTSDT (0x0040u) -#define SCIF5_SCSPTR_RTSIO (0x0080u) - -#define SCIF5_SCLSR_ORER (0x0001u) - -#define SCIF5_SCEMR_ABCS (0x0001u) -#define SCIF5_SCEMR_BGDM (0x0080u) - -/* ---- SCIF6 ---- */ -#define SCIF6_SCSMR_CKS (0x0003u) -#define SCIF6_SCSMR_STOP (0x0008u) -#define SCIF6_SCSMR_OE (0x0010u) -#define SCIF6_SCSMR_PE (0x0020u) -#define SCIF6_SCSMR_CHR (0x0040u) -#define SCIF6_SCSMR_CA (0x0080u) - -#define SCIF6_SCBRR_D (0xFFu) - -#define SCIF6_SCSCR_CKE (0x0003u) -#define SCIF6_SCSCR_REIE (0x0008u) -#define SCIF6_SCSCR_RE (0x0010u) -#define SCIF6_SCSCR_TE (0x0020u) -#define SCIF6_SCSCR_RIE (0x0040u) -#define SCIF6_SCSCR_TIE (0x0080u) - -#define SCIF6_SCFTDR_D (0xFFu) - -#define SCIF6_SCFSR_DR (0x0001u) -#define SCIF6_SCFSR_RDF (0x0002u) -#define SCIF6_SCFSR_PER (0x0004u) -#define SCIF6_SCFSR_FER (0x0008u) -#define SCIF6_SCFSR_BRK (0x0010u) -#define SCIF6_SCFSR_TDFE (0x0020u) -#define SCIF6_SCFSR_TEND (0x0040u) -#define SCIF6_SCFSR_ER (0x0080u) -#define SCIF6_SCFSR_FERN (0x0F00u) -#define SCIF6_SCFSR_PERN (0xF000u) - -#define SCIF6_SCFRDR_D (0xFFu) - -#define SCIF6_SCFCR_LOOP (0x0001u) -#define SCIF6_SCFCR_RFRST (0x0002u) -#define SCIF6_SCFCR_TFRST (0x0004u) -#define SCIF6_SCFCR_MCE (0x0008u) -#define SCIF6_SCFCR_TTRG (0x0030u) -#define SCIF6_SCFCR_RTRG (0x00C0u) -#define SCIF6_SCFCR_RSTRG (0x0700u) - -#define SCIF6_SCFDR_R (0x001Fu) -#define SCIF6_SCFDR_T (0x1F00u) - -#define SCIF6_SCSPTR_SPB2DT (0x0001u) -#define SCIF6_SCSPTR_SPB2IO (0x0002u) -#define SCIF6_SCSPTR_SCKDT (0x0004u) -#define SCIF6_SCSPTR_SCKIO (0x0008u) -#define SCIF6_SCSPTR_CTSDT (0x0010u) -#define SCIF6_SCSPTR_CTSIO (0x0020u) -#define SCIF6_SCSPTR_RTSDT (0x0040u) -#define SCIF6_SCSPTR_RTSIO (0x0080u) - -#define SCIF6_SCLSR_ORER (0x0001u) - -#define SCIF6_SCEMR_ABCS (0x0001u) -#define SCIF6_SCEMR_BGDM (0x0080u) - -/* ---- SCIF7 ---- */ -#define SCIF7_SCSMR_CKS (0x0003u) -#define SCIF7_SCSMR_STOP (0x0008u) -#define SCIF7_SCSMR_OE (0x0010u) -#define SCIF7_SCSMR_PE (0x0020u) -#define SCIF7_SCSMR_CHR (0x0040u) -#define SCIF7_SCSMR_CA (0x0080u) - -#define SCIF7_SCBRR_D (0xFFu) - -#define SCIF7_SCSCR_CKE (0x0003u) -#define SCIF7_SCSCR_REIE (0x0008u) -#define SCIF7_SCSCR_RE (0x0010u) -#define SCIF7_SCSCR_TE (0x0020u) -#define SCIF7_SCSCR_RIE (0x0040u) -#define SCIF7_SCSCR_TIE (0x0080u) - -#define SCIF7_SCFTDR_D (0xFFu) - -#define SCIF7_SCFSR_DR (0x0001u) -#define SCIF7_SCFSR_RDF (0x0002u) -#define SCIF7_SCFSR_PER (0x0004u) -#define SCIF7_SCFSR_FER (0x0008u) -#define SCIF7_SCFSR_BRK (0x0010u) -#define SCIF7_SCFSR_TDFE (0x0020u) -#define SCIF7_SCFSR_TEND (0x0040u) -#define SCIF7_SCFSR_ER (0x0080u) -#define SCIF7_SCFSR_FERN (0x0F00u) -#define SCIF7_SCFSR_PERN (0xF000u) - -#define SCIF7_SCFRDR_D (0xFFu) - -#define SCIF7_SCFCR_LOOP (0x0001u) -#define SCIF7_SCFCR_RFRST (0x0002u) -#define SCIF7_SCFCR_TFRST (0x0004u) -#define SCIF7_SCFCR_MCE (0x0008u) -#define SCIF7_SCFCR_TTRG (0x0030u) -#define SCIF7_SCFCR_RTRG (0x00C0u) -#define SCIF7_SCFCR_RSTRG (0x0700u) - -#define SCIF7_SCFDR_R (0x001Fu) -#define SCIF7_SCFDR_T (0x1F00u) - -#define SCIF7_SCSPTR_SPB2DT (0x0001u) -#define SCIF7_SCSPTR_SPB2IO (0x0002u) -#define SCIF7_SCSPTR_SCKDT (0x0004u) -#define SCIF7_SCSPTR_SCKIO (0x0008u) -#define SCIF7_SCSPTR_CTSDT (0x0010u) -#define SCIF7_SCSPTR_CTSIO (0x0020u) -#define SCIF7_SCSPTR_RTSDT (0x0040u) -#define SCIF7_SCSPTR_RTSIO (0x0080u) - -#define SCIF7_SCLSR_ORER (0x0001u) - -#define SCIF7_SCEMR_ABCS (0x0001u) -#define SCIF7_SCEMR_BGDM (0x0080u) - -/* ---- SCIFn ---- */ -#define SCIFn_SCSMR_CKS (0x0003u) -#define SCIFn_SCSMR_STOP (0x0008u) -#define SCIFn_SCSMR_OE (0x0010u) -#define SCIFn_SCSMR_PE (0x0020u) -#define SCIFn_SCSMR_CHR (0x0040u) -#define SCIFn_SCSMR_CA (0x0080u) - -#define SCIFn_SCBRR_D (0xFFu) - -#define SCIFn_SCSCR_CKE (0x0003u) -#define SCIFn_SCSCR_REIE (0x0008u) -#define SCIFn_SCSCR_RE (0x0010u) -#define SCIFn_SCSCR_TE (0x0020u) -#define SCIFn_SCSCR_RIE (0x0040u) -#define SCIFn_SCSCR_TIE (0x0080u) - -#define SCIFn_SCFTDR_D (0xFFu) - -#define SCIFn_SCFSR_DR (0x0001u) -#define SCIFn_SCFSR_RDF (0x0002u) -#define SCIFn_SCFSR_PER (0x0004u) -#define SCIFn_SCFSR_FER (0x0008u) -#define SCIFn_SCFSR_BRK (0x0010u) -#define SCIFn_SCFSR_TDFE (0x0020u) -#define SCIFn_SCFSR_TEND (0x0040u) -#define SCIFn_SCFSR_ER (0x0080u) -#define SCIFn_SCFSR_FERN (0x0F00u) -#define SCIFn_SCFSR_PERN (0xF000u) - -#define SCIFn_SCFRDR_D (0xFFu) - -#define SCIFn_SCFCR_LOOP (0x0001u) -#define SCIFn_SCFCR_RFRST (0x0002u) -#define SCIFn_SCFCR_TFRST (0x0004u) -#define SCIFn_SCFCR_MCE (0x0008u) -#define SCIFn_SCFCR_TTRG (0x0030u) -#define SCIFn_SCFCR_RTRG (0x00C0u) -#define SCIFn_SCFCR_RSTRG (0x0700u) - -#define SCIFn_SCFDR_R (0x001Fu) -#define SCIFn_SCFDR_T (0x1F00u) - -#define SCIFn_SCSPTR_SPB2DT (0x0001u) -#define SCIFn_SCSPTR_SPB2IO (0x0002u) -#define SCIFn_SCSPTR_SCKDT (0x0004u) -#define SCIFn_SCSPTR_SCKIO (0x0008u) -#define SCIFn_SCSPTR_CTSDT (0x0010u) -#define SCIFn_SCSPTR_CTSIO (0x0020u) -#define SCIFn_SCSPTR_RTSDT (0x0040u) -#define SCIFn_SCSPTR_RTSIO (0x0080u) - -#define SCIFn_SCLSR_ORER (0x0001u) - -#define SCIFn_SCEMR_ABCS (0x0001u) -#define SCIFn_SCEMR_BGDM (0x0080u) - - -/* ==== Shift values for IO registers ==== */ -/* ---- SCIF0 ---- */ -#define SCIF0_SCSMR_CKS_SHIFT (0u) -#define SCIF0_SCSMR_STOP_SHIFT (3u) -#define SCIF0_SCSMR_OE_SHIFT (4u) -#define SCIF0_SCSMR_PE_SHIFT (5u) -#define SCIF0_SCSMR_CHR_SHIFT (6u) -#define SCIF0_SCSMR_CA_SHIFT (7u) - -#define SCIF0_SCBRR_D_SHIFT (0u) - -#define SCIF0_SCSCR_CKE_SHIFT (0u) -#define SCIF0_SCSCR_REIE_SHIFT (3u) -#define SCIF0_SCSCR_RE_SHIFT (4u) -#define SCIF0_SCSCR_TE_SHIFT (5u) -#define SCIF0_SCSCR_RIE_SHIFT (6u) -#define SCIF0_SCSCR_TIE_SHIFT (7u) - -#define SCIF0_SCFTDR_D_SHIFT (0u) - -#define SCIF0_SCFSR_DR_SHIFT (0u) -#define SCIF0_SCFSR_RDF_SHIFT (1u) -#define SCIF0_SCFSR_PER_SHIFT (2u) -#define SCIF0_SCFSR_FER_SHIFT (3u) -#define SCIF0_SCFSR_BRK_SHIFT (4u) -#define SCIF0_SCFSR_TDFE_SHIFT (5u) -#define SCIF0_SCFSR_TEND_SHIFT (6u) -#define SCIF0_SCFSR_ER_SHIFT (7u) -#define SCIF0_SCFSR_FERN_SHIFT (8u) -#define SCIF0_SCFSR_PERN_SHIFT (12u) - -#define SCIF0_SCFRDR_D_SHIFT (0u) - -#define SCIF0_SCFCR_LOOP_SHIFT (0u) -#define SCIF0_SCFCR_RFRST_SHIFT (1u) -#define SCIF0_SCFCR_TFRST_SHIFT (2u) -#define SCIF0_SCFCR_MCE_SHIFT (3u) -#define SCIF0_SCFCR_TTRG_SHIFT (4u) -#define SCIF0_SCFCR_RTRG_SHIFT (6u) -#define SCIF0_SCFCR_RSTRG_SHIFT (8u) - -#define SCIF0_SCFDR_R_SHIFT (0u) -#define SCIF0_SCFDR_T_SHIFT (8u) - -#define SCIF0_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIF0_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIF0_SCSPTR_SCKDT_SHIFT (2u) -#define SCIF0_SCSPTR_SCKIO_SHIFT (3u) -#define SCIF0_SCSPTR_CTSDT_SHIFT (4u) -#define SCIF0_SCSPTR_CTSIO_SHIFT (5u) -#define SCIF0_SCSPTR_RTSDT_SHIFT (6u) -#define SCIF0_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIF0_SCLSR_ORER_SHIFT (0u) - -#define SCIF0_SCEMR_ABCS_SHIFT (0u) -#define SCIF0_SCEMR_BGDM_SHIFT (7u) - -/* ---- SCIF1 ---- */ -#define SCIF1_SCSMR_CKS_SHIFT (0u) -#define SCIF1_SCSMR_STOP_SHIFT (3u) -#define SCIF1_SCSMR_OE_SHIFT (4u) -#define SCIF1_SCSMR_PE_SHIFT (5u) -#define SCIF1_SCSMR_CHR_SHIFT (6u) -#define SCIF1_SCSMR_CA_SHIFT (7u) - -#define SCIF1_SCBRR_D_SHIFT (0u) - -#define SCIF1_SCSCR_CKE_SHIFT (0u) -#define SCIF1_SCSCR_REIE_SHIFT (3u) -#define SCIF1_SCSCR_RE_SHIFT (4u) -#define SCIF1_SCSCR_TE_SHIFT (5u) -#define SCIF1_SCSCR_RIE_SHIFT (6u) -#define SCIF1_SCSCR_TIE_SHIFT (7u) - -#define SCIF1_SCFTDR_D_SHIFT (0u) - -#define SCIF1_SCFSR_DR_SHIFT (0u) -#define SCIF1_SCFSR_RDF_SHIFT (1u) -#define SCIF1_SCFSR_PER_SHIFT (2u) -#define SCIF1_SCFSR_FER_SHIFT (3u) -#define SCIF1_SCFSR_BRK_SHIFT (4u) -#define SCIF1_SCFSR_TDFE_SHIFT (5u) -#define SCIF1_SCFSR_TEND_SHIFT (6u) -#define SCIF1_SCFSR_ER_SHIFT (7u) -#define SCIF1_SCFSR_FERN_SHIFT (8u) -#define SCIF1_SCFSR_PERN_SHIFT (12u) - -#define SCIF1_SCFRDR_D_SHIFT (0u) - -#define SCIF1_SCFCR_LOOP_SHIFT (0u) -#define SCIF1_SCFCR_RFRST_SHIFT (1u) -#define SCIF1_SCFCR_TFRST_SHIFT (2u) -#define SCIF1_SCFCR_MCE_SHIFT (3u) -#define SCIF1_SCFCR_TTRG_SHIFT (4u) -#define SCIF1_SCFCR_RTRG_SHIFT (6u) -#define SCIF1_SCFCR_RSTRG_SHIFT (8u) - -#define SCIF1_SCFDR_R_SHIFT (0u) -#define SCIF1_SCFDR_T_SHIFT (8u) - -#define SCIF1_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIF1_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIF1_SCSPTR_SCKDT_SHIFT (2u) -#define SCIF1_SCSPTR_SCKIO_SHIFT (3u) -#define SCIF1_SCSPTR_CTSDT_SHIFT (4u) -#define SCIF1_SCSPTR_CTSIO_SHIFT (5u) -#define SCIF1_SCSPTR_RTSDT_SHIFT (6u) -#define SCIF1_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIF1_SCLSR_ORER_SHIFT (0u) - -#define SCIF1_SCEMR_ABCS_SHIFT (0u) -#define SCIF1_SCEMR_BGDM_SHIFT (7u) - -/* ---- SCIF2 ---- */ -#define SCIF2_SCSMR_CKS_SHIFT (0u) -#define SCIF2_SCSMR_STOP_SHIFT (3u) -#define SCIF2_SCSMR_OE_SHIFT (4u) -#define SCIF2_SCSMR_PE_SHIFT (5u) -#define SCIF2_SCSMR_CHR_SHIFT (6u) -#define SCIF2_SCSMR_CA_SHIFT (7u) - -#define SCIF2_SCBRR_D_SHIFT (0u) - -#define SCIF2_SCSCR_CKE_SHIFT (0u) -#define SCIF2_SCSCR_REIE_SHIFT (3u) -#define SCIF2_SCSCR_RE_SHIFT (4u) -#define SCIF2_SCSCR_TE_SHIFT (5u) -#define SCIF2_SCSCR_RIE_SHIFT (6u) -#define SCIF2_SCSCR_TIE_SHIFT (7u) - -#define SCIF2_SCFTDR_D_SHIFT (0u) - -#define SCIF2_SCFSR_DR_SHIFT (0u) -#define SCIF2_SCFSR_RDF_SHIFT (1u) -#define SCIF2_SCFSR_PER_SHIFT (2u) -#define SCIF2_SCFSR_FER_SHIFT (3u) -#define SCIF2_SCFSR_BRK_SHIFT (4u) -#define SCIF2_SCFSR_TDFE_SHIFT (5u) -#define SCIF2_SCFSR_TEND_SHIFT (6u) -#define SCIF2_SCFSR_ER_SHIFT (7u) -#define SCIF2_SCFSR_FERN_SHIFT (8u) -#define SCIF2_SCFSR_PERN_SHIFT (12u) - -#define SCIF2_SCFRDR_D_SHIFT (0u) - -#define SCIF2_SCFCR_LOOP_SHIFT (0u) -#define SCIF2_SCFCR_RFRST_SHIFT (1u) -#define SCIF2_SCFCR_TFRST_SHIFT (2u) -#define SCIF2_SCFCR_MCE_SHIFT (3u) -#define SCIF2_SCFCR_TTRG_SHIFT (4u) -#define SCIF2_SCFCR_RTRG_SHIFT (6u) -#define SCIF2_SCFCR_RSTRG_SHIFT (8u) - -#define SCIF2_SCFDR_R_SHIFT (0u) -#define SCIF2_SCFDR_T_SHIFT (8u) - -#define SCIF2_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIF2_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIF2_SCSPTR_SCKDT_SHIFT (2u) -#define SCIF2_SCSPTR_SCKIO_SHIFT (3u) -#define SCIF2_SCSPTR_CTSDT_SHIFT (4u) -#define SCIF2_SCSPTR_CTSIO_SHIFT (5u) -#define SCIF2_SCSPTR_RTSDT_SHIFT (6u) -#define SCIF2_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIF2_SCLSR_ORER_SHIFT (0u) - -#define SCIF2_SCEMR_ABCS_SHIFT (0u) -#define SCIF2_SCEMR_BGDM_SHIFT (7u) - -/* ---- SCIF3 ---- */ -#define SCIF3_SCSMR_CKS_SHIFT (0u) -#define SCIF3_SCSMR_STOP_SHIFT (3u) -#define SCIF3_SCSMR_OE_SHIFT (4u) -#define SCIF3_SCSMR_PE_SHIFT (5u) -#define SCIF3_SCSMR_CHR_SHIFT (6u) -#define SCIF3_SCSMR_CA_SHIFT (7u) - -#define SCIF3_SCBRR_D_SHIFT (0u) - -#define SCIF3_SCSCR_CKE_SHIFT (0u) -#define SCIF3_SCSCR_REIE_SHIFT (3u) -#define SCIF3_SCSCR_RE_SHIFT (4u) -#define SCIF3_SCSCR_TE_SHIFT (5u) -#define SCIF3_SCSCR_RIE_SHIFT (6u) -#define SCIF3_SCSCR_TIE_SHIFT (7u) - -#define SCIF3_SCFTDR_D_SHIFT (0u) - -#define SCIF3_SCFSR_DR_SHIFT (0u) -#define SCIF3_SCFSR_RDF_SHIFT (1u) -#define SCIF3_SCFSR_PER_SHIFT (2u) -#define SCIF3_SCFSR_FER_SHIFT (3u) -#define SCIF3_SCFSR_BRK_SHIFT (4u) -#define SCIF3_SCFSR_TDFE_SHIFT (5u) -#define SCIF3_SCFSR_TEND_SHIFT (6u) -#define SCIF3_SCFSR_ER_SHIFT (7u) -#define SCIF3_SCFSR_FERN_SHIFT (8u) -#define SCIF3_SCFSR_PERN_SHIFT (12u) - -#define SCIF3_SCFRDR_D_SHIFT (0u) - -#define SCIF3_SCFCR_LOOP_SHIFT (0u) -#define SCIF3_SCFCR_RFRST_SHIFT (1u) -#define SCIF3_SCFCR_TFRST_SHIFT (2u) -#define SCIF3_SCFCR_MCE_SHIFT (3u) -#define SCIF3_SCFCR_TTRG_SHIFT (4u) -#define SCIF3_SCFCR_RTRG_SHIFT (6u) -#define SCIF3_SCFCR_RSTRG_SHIFT (8u) - -#define SCIF3_SCFDR_R_SHIFT (0u) -#define SCIF3_SCFDR_T_SHIFT (8u) - -#define SCIF3_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIF3_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIF3_SCSPTR_SCKDT_SHIFT (2u) -#define SCIF3_SCSPTR_SCKIO_SHIFT (3u) -#define SCIF3_SCSPTR_CTSDT_SHIFT (4u) -#define SCIF3_SCSPTR_CTSIO_SHIFT (5u) -#define SCIF3_SCSPTR_RTSDT_SHIFT (6u) -#define SCIF3_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIF3_SCLSR_ORER_SHIFT (0u) - -#define SCIF3_SCEMR_ABCS_SHIFT (0u) -#define SCIF3_SCEMR_BGDM_SHIFT (7u) - -/* ---- SCIF4 ---- */ -#define SCIF4_SCSMR_CKS_SHIFT (0u) -#define SCIF4_SCSMR_STOP_SHIFT (3u) -#define SCIF4_SCSMR_OE_SHIFT (4u) -#define SCIF4_SCSMR_PE_SHIFT (5u) -#define SCIF4_SCSMR_CHR_SHIFT (6u) -#define SCIF4_SCSMR_CA_SHIFT (7u) - -#define SCIF4_SCBRR_D_SHIFT (0u) - -#define SCIF4_SCSCR_CKE_SHIFT (0u) -#define SCIF4_SCSCR_REIE_SHIFT (3u) -#define SCIF4_SCSCR_RE_SHIFT (4u) -#define SCIF4_SCSCR_TE_SHIFT (5u) -#define SCIF4_SCSCR_RIE_SHIFT (6u) -#define SCIF4_SCSCR_TIE_SHIFT (7u) - -#define SCIF4_SCFTDR_D_SHIFT (0u) - -#define SCIF4_SCFSR_DR_SHIFT (0u) -#define SCIF4_SCFSR_RDF_SHIFT (1u) -#define SCIF4_SCFSR_PER_SHIFT (2u) -#define SCIF4_SCFSR_FER_SHIFT (3u) -#define SCIF4_SCFSR_BRK_SHIFT (4u) -#define SCIF4_SCFSR_TDFE_SHIFT (5u) -#define SCIF4_SCFSR_TEND_SHIFT (6u) -#define SCIF4_SCFSR_ER_SHIFT (7u) -#define SCIF4_SCFSR_FERN_SHIFT (8u) -#define SCIF4_SCFSR_PERN_SHIFT (12u) - -#define SCIF4_SCFRDR_D_SHIFT (0u) - -#define SCIF4_SCFCR_LOOP_SHIFT (0u) -#define SCIF4_SCFCR_RFRST_SHIFT (1u) -#define SCIF4_SCFCR_TFRST_SHIFT (2u) -#define SCIF4_SCFCR_MCE_SHIFT (3u) -#define SCIF4_SCFCR_TTRG_SHIFT (4u) -#define SCIF4_SCFCR_RTRG_SHIFT (6u) -#define SCIF4_SCFCR_RSTRG_SHIFT (8u) - -#define SCIF4_SCFDR_R_SHIFT (0u) -#define SCIF4_SCFDR_T_SHIFT (8u) - -#define SCIF4_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIF4_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIF4_SCSPTR_SCKDT_SHIFT (2u) -#define SCIF4_SCSPTR_SCKIO_SHIFT (3u) -#define SCIF4_SCSPTR_CTSDT_SHIFT (4u) -#define SCIF4_SCSPTR_CTSIO_SHIFT (5u) -#define SCIF4_SCSPTR_RTSDT_SHIFT (6u) -#define SCIF4_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIF4_SCLSR_ORER_SHIFT (0u) - -#define SCIF4_SCEMR_ABCS_SHIFT (0u) -#define SCIF4_SCEMR_BGDM_SHIFT (7u) - -/* ---- SCIF5 ---- */ -#define SCIF5_SCSMR_CKS_SHIFT (0u) -#define SCIF5_SCSMR_STOP_SHIFT (3u) -#define SCIF5_SCSMR_OE_SHIFT (4u) -#define SCIF5_SCSMR_PE_SHIFT (5u) -#define SCIF5_SCSMR_CHR_SHIFT (6u) -#define SCIF5_SCSMR_CA_SHIFT (7u) - -#define SCIF5_SCBRR_D_SHIFT (0u) - -#define SCIF5_SCSCR_CKE_SHIFT (0u) -#define SCIF5_SCSCR_REIE_SHIFT (3u) -#define SCIF5_SCSCR_RE_SHIFT (4u) -#define SCIF5_SCSCR_TE_SHIFT (5u) -#define SCIF5_SCSCR_RIE_SHIFT (6u) -#define SCIF5_SCSCR_TIE_SHIFT (7u) - -#define SCIF5_SCFTDR_D_SHIFT (0u) - -#define SCIF5_SCFSR_DR_SHIFT (0u) -#define SCIF5_SCFSR_RDF_SHIFT (1u) -#define SCIF5_SCFSR_PER_SHIFT (2u) -#define SCIF5_SCFSR_FER_SHIFT (3u) -#define SCIF5_SCFSR_BRK_SHIFT (4u) -#define SCIF5_SCFSR_TDFE_SHIFT (5u) -#define SCIF5_SCFSR_TEND_SHIFT (6u) -#define SCIF5_SCFSR_ER_SHIFT (7u) -#define SCIF5_SCFSR_FERN_SHIFT (8u) -#define SCIF5_SCFSR_PERN_SHIFT (12u) - -#define SCIF5_SCFRDR_D_SHIFT (0u) - -#define SCIF5_SCFCR_LOOP_SHIFT (0u) -#define SCIF5_SCFCR_RFRST_SHIFT (1u) -#define SCIF5_SCFCR_TFRST_SHIFT (2u) -#define SCIF5_SCFCR_MCE_SHIFT (3u) -#define SCIF5_SCFCR_TTRG_SHIFT (4u) -#define SCIF5_SCFCR_RTRG_SHIFT (6u) -#define SCIF5_SCFCR_RSTRG_SHIFT (8u) - -#define SCIF5_SCFDR_R_SHIFT (0u) -#define SCIF5_SCFDR_T_SHIFT (8u) - -#define SCIF5_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIF5_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIF5_SCSPTR_SCKDT_SHIFT (2u) -#define SCIF5_SCSPTR_SCKIO_SHIFT (3u) -#define SCIF5_SCSPTR_CTSDT_SHIFT (4u) -#define SCIF5_SCSPTR_CTSIO_SHIFT (5u) -#define SCIF5_SCSPTR_RTSDT_SHIFT (6u) -#define SCIF5_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIF5_SCLSR_ORER_SHIFT (0u) - -#define SCIF5_SCEMR_ABCS_SHIFT (0u) -#define SCIF5_SCEMR_BGDM_SHIFT (7u) - -/* ---- SCIF6 ---- */ -#define SCIF6_SCSMR_CKS_SHIFT (0u) -#define SCIF6_SCSMR_STOP_SHIFT (3u) -#define SCIF6_SCSMR_OE_SHIFT (4u) -#define SCIF6_SCSMR_PE_SHIFT (5u) -#define SCIF6_SCSMR_CHR_SHIFT (6u) -#define SCIF6_SCSMR_CA_SHIFT (7u) - -#define SCIF6_SCBRR_D_SHIFT (0u) - -#define SCIF6_SCSCR_CKE_SHIFT (0u) -#define SCIF6_SCSCR_REIE_SHIFT (3u) -#define SCIF6_SCSCR_RE_SHIFT (4u) -#define SCIF6_SCSCR_TE_SHIFT (5u) -#define SCIF6_SCSCR_RIE_SHIFT (6u) -#define SCIF6_SCSCR_TIE_SHIFT (7u) - -#define SCIF6_SCFTDR_D_SHIFT (0u) - -#define SCIF6_SCFSR_DR_SHIFT (0u) -#define SCIF6_SCFSR_RDF_SHIFT (1u) -#define SCIF6_SCFSR_PER_SHIFT (2u) -#define SCIF6_SCFSR_FER_SHIFT (3u) -#define SCIF6_SCFSR_BRK_SHIFT (4u) -#define SCIF6_SCFSR_TDFE_SHIFT (5u) -#define SCIF6_SCFSR_TEND_SHIFT (6u) -#define SCIF6_SCFSR_ER_SHIFT (7u) -#define SCIF6_SCFSR_FERN_SHIFT (8u) -#define SCIF6_SCFSR_PERN_SHIFT (12u) - -#define SCIF6_SCFRDR_D_SHIFT (0u) - -#define SCIF6_SCFCR_LOOP_SHIFT (0u) -#define SCIF6_SCFCR_RFRST_SHIFT (1u) -#define SCIF6_SCFCR_TFRST_SHIFT (2u) -#define SCIF6_SCFCR_MCE_SHIFT (3u) -#define SCIF6_SCFCR_TTRG_SHIFT (4u) -#define SCIF6_SCFCR_RTRG_SHIFT (6u) -#define SCIF6_SCFCR_RSTRG_SHIFT (8u) - -#define SCIF6_SCFDR_R_SHIFT (0u) -#define SCIF6_SCFDR_T_SHIFT (8u) - -#define SCIF6_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIF6_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIF6_SCSPTR_SCKDT_SHIFT (2u) -#define SCIF6_SCSPTR_SCKIO_SHIFT (3u) -#define SCIF6_SCSPTR_CTSDT_SHIFT (4u) -#define SCIF6_SCSPTR_CTSIO_SHIFT (5u) -#define SCIF6_SCSPTR_RTSDT_SHIFT (6u) -#define SCIF6_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIF6_SCLSR_ORER_SHIFT (0u) - -#define SCIF6_SCEMR_ABCS_SHIFT (0u) -#define SCIF6_SCEMR_BGDM_SHIFT (7u) - -/* ---- SCIF7 ---- */ -#define SCIF7_SCSMR_CKS_SHIFT (0u) -#define SCIF7_SCSMR_STOP_SHIFT (3u) -#define SCIF7_SCSMR_OE_SHIFT (4u) -#define SCIF7_SCSMR_PE_SHIFT (5u) -#define SCIF7_SCSMR_CHR_SHIFT (6u) -#define SCIF7_SCSMR_CA_SHIFT (7u) - -#define SCIF7_SCBRR_D_SHIFT (0u) - -#define SCIF7_SCSCR_CKE_SHIFT (0u) -#define SCIF7_SCSCR_REIE_SHIFT (3u) -#define SCIF7_SCSCR_RE_SHIFT (4u) -#define SCIF7_SCSCR_TE_SHIFT (5u) -#define SCIF7_SCSCR_RIE_SHIFT (6u) -#define SCIF7_SCSCR_TIE_SHIFT (7u) - -#define SCIF7_SCFTDR_D_SHIFT (0u) - -#define SCIF7_SCFSR_DR_SHIFT (0u) -#define SCIF7_SCFSR_RDF_SHIFT (1u) -#define SCIF7_SCFSR_PER_SHIFT (2u) -#define SCIF7_SCFSR_FER_SHIFT (3u) -#define SCIF7_SCFSR_BRK_SHIFT (4u) -#define SCIF7_SCFSR_TDFE_SHIFT (5u) -#define SCIF7_SCFSR_TEND_SHIFT (6u) -#define SCIF7_SCFSR_ER_SHIFT (7u) -#define SCIF7_SCFSR_FERN_SHIFT (8u) -#define SCIF7_SCFSR_PERN_SHIFT (12u) - -#define SCIF7_SCFRDR_D_SHIFT (0u) - -#define SCIF7_SCFCR_LOOP_SHIFT (0u) -#define SCIF7_SCFCR_RFRST_SHIFT (1u) -#define SCIF7_SCFCR_TFRST_SHIFT (2u) -#define SCIF7_SCFCR_MCE_SHIFT (3u) -#define SCIF7_SCFCR_TTRG_SHIFT (4u) -#define SCIF7_SCFCR_RTRG_SHIFT (6u) -#define SCIF7_SCFCR_RSTRG_SHIFT (8u) - -#define SCIF7_SCFDR_R_SHIFT (0u) -#define SCIF7_SCFDR_T_SHIFT (8u) - -#define SCIF7_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIF7_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIF7_SCSPTR_SCKDT_SHIFT (2u) -#define SCIF7_SCSPTR_SCKIO_SHIFT (3u) -#define SCIF7_SCSPTR_CTSDT_SHIFT (4u) -#define SCIF7_SCSPTR_CTSIO_SHIFT (5u) -#define SCIF7_SCSPTR_RTSDT_SHIFT (6u) -#define SCIF7_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIF7_SCLSR_ORER_SHIFT (0u) - -#define SCIF7_SCEMR_ABCS_SHIFT (0u) -#define SCIF7_SCEMR_BGDM_SHIFT (7u) - -/* ---- SCIFn ---- */ -#define SCIFn_SCSMR_CKS_SHIFT (0u) -#define SCIFn_SCSMR_STOP_SHIFT (3u) -#define SCIFn_SCSMR_OE_SHIFT (4u) -#define SCIFn_SCSMR_PE_SHIFT (5u) -#define SCIFn_SCSMR_CHR_SHIFT (6u) -#define SCIFn_SCSMR_CA_SHIFT (7u) - -#define SCIFn_SCBRR_D_SHIFT (0u) - -#define SCIFn_SCSCR_CKE_SHIFT (0u) -#define SCIFn_SCSCR_REIE_SHIFT (3u) -#define SCIFn_SCSCR_RE_SHIFT (4u) -#define SCIFn_SCSCR_TE_SHIFT (5u) -#define SCIFn_SCSCR_RIE_SHIFT (6u) -#define SCIFn_SCSCR_TIE_SHIFT (7u) - -#define SCIFn_SCFTDR_D_SHIFT (0u) - -#define SCIFn_SCFSR_DR_SHIFT (0u) -#define SCIFn_SCFSR_RDF_SHIFT (1u) -#define SCIFn_SCFSR_PER_SHIFT (2u) -#define SCIFn_SCFSR_FER_SHIFT (3u) -#define SCIFn_SCFSR_BRK_SHIFT (4u) -#define SCIFn_SCFSR_TDFE_SHIFT (5u) -#define SCIFn_SCFSR_TEND_SHIFT (6u) -#define SCIFn_SCFSR_ER_SHIFT (7u) -#define SCIFn_SCFSR_FERN_SHIFT (8u) -#define SCIFn_SCFSR_PERN_SHIFT (12u) - -#define SCIFn_SCFRDR_D_SHIFT (0u) - -#define SCIFn_SCFCR_LOOP_SHIFT (0u) -#define SCIFn_SCFCR_RFRST_SHIFT (1u) -#define SCIFn_SCFCR_TFRST_SHIFT (2u) -#define SCIFn_SCFCR_MCE_SHIFT (3u) -#define SCIFn_SCFCR_TTRG_SHIFT (4u) -#define SCIFn_SCFCR_RTRG_SHIFT (6u) -#define SCIFn_SCFCR_RSTRG_SHIFT (8u) - -#define SCIFn_SCFDR_R_SHIFT (0u) -#define SCIFn_SCFDR_T_SHIFT (8u) - -#define SCIFn_SCSPTR_SPB2DT_SHIFT (0u) -#define SCIFn_SCSPTR_SPB2IO_SHIFT (1u) -#define SCIFn_SCSPTR_SCKDT_SHIFT (2u) -#define SCIFn_SCSPTR_SCKIO_SHIFT (3u) -#define SCIFn_SCSPTR_CTSDT_SHIFT (4u) -#define SCIFn_SCSPTR_CTSIO_SHIFT (5u) -#define SCIFn_SCSPTR_RTSDT_SHIFT (6u) -#define SCIFn_SCSPTR_RTSIO_SHIFT (7u) - -#define SCIFn_SCLSR_ORER_SHIFT (0u) - -#define SCIFn_SCEMR_ABCS_SHIFT (0u) -#define SCIFn_SCEMR_BGDM_SHIFT (7u) - - -#endif /* SCIF_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h deleted file mode 100644 index cd671e699c7..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h +++ /dev/null @@ -1,731 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb_iobitmask.h -* $Rev: 1116 $ -* $Date:: 2014-07-09 16:29:19 +0900#$ -* Description : USB register define header -*******************************************************************************/ -#ifndef USB_IOBITMASK_H -#define USB_IOBITMASK_H - -/*==============================================*/ -/* SYSCFG */ -/*==============================================*/ -#define USB_SYSCFG_USBE (0x0001u) -#define USB_SYSCFG_UPLLE (0x0002u) -#define USB_SYSCFG_UCKSEL (0x0004u) -/* #define USB_SYSCFG_RESERVED1 (0x0008u) */ -#define USB_SYSCFG_DPRPU (0x0010u) -#define USB_SYSCFG_DRPD (0x0020u) -#define USB_SYSCFG_DCFM (0x0040u) -#define USB_SYSCFG_HSE (0x0080u) -/* #define USB_SYSCFG_RESERVED2 (0xFF00u) */ - -#define USB_SYSCFG_USBE_SHIFT (0) -#define USB_SYSCFG_UPLLE_SHIFT (1) -#define USB_SYSCFG_UCKSEL_SHIFT (2) -/* #define USB_SYSCFG_RESERVED1_SHIFT (3) */ -#define USB_SYSCFG_DPRPU_SHIFT (4) -#define USB_SYSCFG_DRPD_SHIFT (5) -#define USB_SYSCFG_DCFM_SHIFT (6) -#define USB_SYSCFG_HSE_SHIFT (7) -/* #define USB_SYSCFG_RESERVED2_SHIFT (8) */ - -/*==============================================*/ -/* BUSWAIT */ -/*==============================================*/ -#define USB_BUSWAIT_BWAIT (0x003Fu) - -#define USB_BUSWAIT_BWAIT_SHIFT (0) - -/*==============================================*/ -/* SYSSTS0 */ -/*==============================================*/ -#define USB_SYSSTS0_LNST (0x0003u) -#define USB_SYSSTS0_SOFEA (0x0020u) -#define USB_SYSSTS0_HTACT (0x0040u) - -#define USB_SYSSTS0_LNST_SHIFT (0) -#define USB_SYSSTS0_SOFEA_SHIFT (5) -#define USB_SYSSTS0_HTACT_SHIFT (6) - -/*==============================================*/ -/* DVSTCTR0 */ -/*==============================================*/ -#define USB_DVSTCTR0_RHST (0x0007u) -/* #define USB_DVSTCTR0_RESERVED (0x0008u) */ -#define USB_DVSTCTR0_UACT (0x0010u) -#define USB_DVSTCTR0_RESUME (0x0020u) -#define USB_DVSTCTR0_USBRST (0x0040u) -#define USB_DVSTCTR0_RWUPE (0x0080u) -#define USB_DVSTCTR0_WKUP (0x0100u) - -#define USB_DVSTCTR0_RHST_SHIFT (0) -/* #define USB_DVSTCTR0_RESERVED_SHIFT (3) */ -#define USB_DVSTCTR0_UACT_SHIFT (4) -#define USB_DVSTCTR0_RESUME_SHIFT (5) -#define USB_DVSTCTR0_USBRST_SHIFT (6) -#define USB_DVSTCTR0_RWUPE_SHIFT (7) -#define USB_DVSTCTR0_WKUP_SHIFT (8) - -/*==============================================*/ -/* TESTMODE */ -/*==============================================*/ -#define USB_TESTMODE_UTST (0x000Fu) -/* #define USB_TESTMODE_RESERVED (0xFFF0u) */ - -#define USB_TESTMODE_UTST_SHIFT (0) -/* #define USB_TESTMODE_RESERVED_SHIFT (4) */ - -/*==============================================*/ -/* DnFBCFG */ -/*==============================================*/ -/* #define USB_DnFBCFG_RESERVED1 (0x000Fu) */ -#define USB_DnFBCFG_TENDE (0x0010u) -/* #define USB_DnFBCFG_RESERVED2 (0x0FE0u) */ -#define USB_DnFBCFG_DFACC (0x3000u) -/* #define USB_DnFBCFG_RESERVED3 (0xC000u) */ - -/* #define USB_DnFBCFG_RESERVED1_SHIFT (0) */ -#define USB_DnFBCFG_TENDE_SHIFT (4) -/* #define USB_DnFBCFG_RESERVED2_SHIFT (5) */ -#define USB_DnFBCFG_DFACC_SHIFT (12) -/* #define USB_DnFBCFG_RESERVED3_SHIFT (14) */ - -/*==============================================*/ -/* CFIFO */ -/*==============================================*/ -#define USB_CFIFO_FIFOPORT (0xFFFFFFFFuL) - -#define USB_CFIFO_FIFOPORT_SHIFT (0) - -/*==============================================*/ -/* DnFIFO */ -/*==============================================*/ -#define USB_DnFIFO_FIFOPORT (0xFFFFFFFFuL) - -#define USB_DnFIFO_FIFOPORT_SHIFT (0) - -/*==============================================*/ -/* CFIFOSEL */ -/*==============================================*/ -#define USB_CFIFOSEL_CURPIPE (0x000Fu) -/* #define USB_CFIFOSEL_RESERVED1 (0x0010u) */ -#define USB_CFIFOSEL_ISEL_ (0x0020u) -/* #define USB_CFIFOSEL_RESERVED2 (0x00C0u) */ -#define USB_CFIFOSEL_BIGEND (0x0100u) -/* #define USB_CFIFOSEL_RESERVED3 (0x0200u) */ -#define USB_CFIFOSEL_MBW (0x0C00u) -/* #define USB_CFIFOSEL_RESERVED4 (0x3000u) */ -#define USB_CFIFOSEL_REW (0x4000u) -#define USB_CFIFOSEL_RCNT (0x8000u) - -#define USB_CFIFOSEL_CURPIPE_SHIFT (0) -/* #define USB_CFIFOSEL_RESERVED1_SHIFT (4) */ -#define USB_CFIFOSEL_ISEL_SHIFT_ (5) -/* #define USB_CFIFOSEL_RESERVED2_SHIFT (6) */ -#define USB_CFIFOSEL_BIGEND_SHIFT (8) -/* #define USB_CFIFOSEL_RESERVED3_SHIFT (9) */ -#define USB_CFIFOSEL_MBW_SHIFT (10) -/* #define USB_CFIFOSEL_RESERVED4_SHIFT (12) */ -#define USB_CFIFOSEL_REW_SHIFT (14) -#define USB_CFIFOSEL_RCNT_SHIFT (15) - -/*==============================================*/ -/* DnFIFOSEL */ -/*==============================================*/ -#define USB_DnFIFOSEL_CURPIPE (0x000Fu) -/* #define USB_DnFIFOSEL_RESERVED1 (0x00F0u) */ -#define USB_DnFIFOSEL_BIGEND (0x0100u) -/* #define USB_DnFIFOSEL_RESERVED2 (0x0200u) */ -#define USB_DnFIFOSEL_MBW (0x0C00u) -#define USB_DnFIFOSEL_DREQE (0x1000u) -#define USB_DnFIFOSEL_DCLRM (0x2000u) -#define USB_DnFIFOSEL_REW (0x4000u) -#define USB_DnFIFOSEL_RCNT (0x8000u) - -#define USB_DnFIFOSEL_CURPIPE_SHIFT (0) -/* #define USB_DnFIFOSEL_RESERVED1_SHIFT (4) */ -#define USB_DnFIFOSEL_BIGEND_SHIFT (8) -/* #define USB_DnFIFOSEL_RESERVED2_SHIFT (9) */ -#define USB_DnFIFOSEL_MBW_SHIFT (10) -#define USB_DnFIFOSEL_DREQE_SHIFT (12) -#define USB_DnFIFOSEL_DCLRM_SHIFT (13) -#define USB_DnFIFOSEL_REW_SHIFT (14) -#define USB_DnFIFOSEL_RCNT_SHIFT (15) - -/*==============================================*/ -/* CFIFOCTR */ -/*==============================================*/ -#define USB_CFIFOCTR_DTLN (0x0FFFu) -/* #define USB_CFIFOCTR_RESERVED (0x1000u) */ -#define USB_CFIFOCTR_FRDY (0x2000u) -#define USB_CFIFOCTR_BCLR (0x4000u) -#define USB_CFIFOCTR_BVAL (0x8000u) - -#define USB_CFIFOCTR_DTLN_SHIFT (0) -/* #define USB_CFIFOCTR_RESERVED_SHIFT (12) */ -#define USB_CFIFOCTR_FRDY_SHIFT (13) -#define USB_CFIFOCTR_BCLR_SHIFT (14) -#define USB_CFIFOCTR_BVAL_SHIFT (15) - -/*==============================================*/ -/* DnFIFOCTR */ -/*==============================================*/ -#define USB_DnFIFOCTR_DTLN (0x0FFFu) -/* #define USB_DnFIFOCTR_RESERVED (0x1000u) */ -#define USB_DnFIFOCTR_FRDY (0x2000u) -#define USB_DnFIFOCTR_BCLR (0x4000u) -#define USB_DnFIFOCTR_BVAL (0x8000u) - -#define USB_DnFIFOCTR_DTLN_SHIFT (0) -/* #define USB_DnFIFOCTR_RESERVED_SHIFT (12) */ -#define USB_DnFIFOCTR_FRDY_SHIFT (13) -#define USB_DnFIFOCTR_BCLR_SHIFT (14) -#define USB_DnFIFOCTR_BVAL_SHIFT (15) - -/*==============================================*/ -/* INTENB0 */ -/*==============================================*/ -/* #define USB_INTENB0_RESERVED (0x00FFu) */ -#define USB_INTENB0_BRDYE (0x0100u) -#define USB_INTENB0_NRDYE (0x0200u) -#define USB_INTENB0_BEMPE (0x0400u) -#define USB_INTENB0_CTRE (0x0800u) -#define USB_INTENB0_DVSE (0x1000u) -#define USB_INTENB0_SOFE (0x2000u) -#define USB_INTENB0_RSME (0x4000u) -#define USB_INTENB0_VBSE (0x8000u) - -/* #define USB_INTENB0_RESERVED_SHIFT (0) */ -#define USB_INTENB0_BRDYE_SHIFT (8) -#define USB_INTENB0_NRDYE_SHIFT (9) -#define USB_INTENB0_BEMPE_SHIFT (10) -#define USB_INTENB0_CTRE_SHIFT (11) -#define USB_INTENB0_DVSE_SHIFT (12) -#define USB_INTENB0_SOFE_SHIFT (13) -#define USB_INTENB0_RSME_SHIFT (14) -#define USB_INTENB0_VBSE_SHIFT (15) - -/*==============================================*/ -/* INTENB1 */ -/*==============================================*/ -/* #define USB_INTENB1_RESERVED1 (0x000Fu) */ -#define USB_INTENB1_SACKE (0x0010u) -#define USB_INTENB1_SIGNE (0x0020u) -#define USB_INTENB1_EOFERRE (0x0040u) -/* #define USB_INTENB1_RESERVED2 (0x0780u) */ -#define USB_INTENB1_ATTCHE (0x0800u) -#define USB_INTENB1_DTCHE (0x1000u) -/* #define USB_INTENB1_RESERVED3 (0x2000u) */ -#define USB_INTENB1_BCHGE (0x4000u) -/* #define USB_INTENB1_RESERVED4 (0x8000u) */ - -/* #define USB_INTENB1_RESERVED1_SHIFT (0) */ -#define USB_INTENB1_SACKE_SHIFT (4) -#define USB_INTENB1_SIGNE_SHIFT (5) -#define USB_INTENB1_EOFERRE_SHIFT (6) -/* #define USB_INTENB1_RESERVED2_SHIFT (7) */ -#define USB_INTENB1_ATTCHE_SHIFT (11) -#define USB_INTENB1_DTCHE_SHIFT (12) -/* #define USB_INTENB1_RESERVED3_SHIFT (13) */ -#define USB_INTENB1_BCHGE_SHIFT (14) -/* #define USB_INTENB1_RESERVED4_SHIFT (15) */ - -/*==============================================*/ -/* BRDYENB */ -/*==============================================*/ -#define USB_BRDYENB (0xFFFFu) - -#define USB_BRDYENB_SHIFT (0) - -/*==============================================*/ -/* NRDYENB */ -/*==============================================*/ -#define USB_NRDYENB (0xFFFFu) - -#define USB_NRDYENB_SHIFT (0) - -/*==============================================*/ -/* BEMPENB */ -/*==============================================*/ -#define USB_BEMPENB (0xFFFFu) - -#define USB_BEMPENB_SHIFT (0) - -/*==============================================*/ -/* SOFCFG */ -/*==============================================*/ -/* #define USB_SOFCFG_RESERVED1 (0x003Fu) */ -#define USB_SOFCFG_BRDYM (0x0040u) -/* #define USB_SOFCFG_RESERVED2 (0x0080u) */ -#define USB_SOFCFG_TRNENSEL (0x0100u) -/* #define USB_SOFCFG_RESERVED3 (0xFE00u) */ - -/* #define USB_SOFCFG_RESERVED1_SHIFT (0) */ -#define USB_SOFCFG_BRDYM_SHIFT (6) -/* #define USB_SOFCFG_RESERVED2_SHIFT (7) */ -#define USB_SOFCFG_TRNENSEL_SHIFT (8) -/* #define USB_SOFCFG_RESERVED3_SHIFT (9) */ - -/*==============================================*/ -/* INTSTS0 */ -/*==============================================*/ -#define USB_INTSTS0_CTSQ (0x0007u) -#define USB_INTSTS0_VALID (0x0008u) -#define USB_INTSTS0_DVSQ (0x0070u) -#define USB_INTSTS0_VBSTS (0x0080u) -#define USB_INTSTS0_BRDY (0x0100u) -#define USB_INTSTS0_NRDY (0x0200u) -#define USB_INTSTS0_BEMP (0x0400u) -#define USB_INTSTS0_CTRT (0x0800u) -#define USB_INTSTS0_DVST (0x1000u) -#define USB_INTSTS0_SOFR (0x2000u) -#define USB_INTSTS0_RESM (0x4000u) -#define USB_INTSTS0_VBINT (0x8000u) - -#define USB_INTSTS0_CTSQ_SHIFT (0) -#define USB_INTSTS0_VALID_SHIFT (3) -#define USB_INTSTS0_DVSQ_SHIFT (4) -#define USB_INTSTS0_VBSTS_SHIFT (7) -#define USB_INTSTS0_BRDY_SHIFT (8) -#define USB_INTSTS0_NRDY_SHIFT (9) -#define USB_INTSTS0_BEMP_SHIFT (10) -#define USB_INTSTS0_CTRT_SHIFT (11) -#define USB_INTSTS0_DVST_SHIFT (12) -#define USB_INTSTS0_SOFR_SHIFT (13) -#define USB_INTSTS0_RESM_SHIFT (14) -#define USB_INTSTS0_VBINT_SHIFT (15) - -/*==============================================*/ -/* INTSTS1 */ -/*==============================================*/ -/* #define USB_INTSTS1_RESERVED1 (0x000Fu) */ -#define USB_INTSTS1_SACK (0x0010u) -#define USB_INTSTS1_SIGN (0x0020u) -#define USB_INTSTS1_EOFERR (0x0040u) -/* #define USB_INTSTS1_RESERVED2 (0x0780u) */ -#define USB_INTSTS1_ATTCH (0x0800u) -#define USB_INTSTS1_DTCH (0x1000u) -/* #define USB_INTSTS1_RESERVED3 (0x2000u) */ -#define USB_INTSTS1_BCHG (0x4000u) -/* #define USB_INTSTS1_RESERVED4 (0x8000u) */ - -/* #define USB_INTSTS1_RESERVED1_SHIFT (0) */ -#define USB_INTSTS1_SACK_SHIFT (4) -#define USB_INTSTS1_SIGN_SHIFT (5) -#define USB_INTSTS1_EOFERR_SHIFT (6) -/* #define USB_INTSTS1_RESERVED2_SHIFT (7) */ -#define USB_INTSTS1_ATTCH_SHIFT (11) -#define USB_INTSTS1_DTCH_SHIFT (12) -/* #define USB_INTSTS1_RESERVED3_SHIFT (13) */ -#define USB_INTSTS1_BCHG_SHIFT (14) -/* #define USB_INTSTS1_RESERVED4_SHIFT (15) */ - -/*==============================================*/ -/* BRDYSTS */ -/*==============================================*/ -#define USB_BRDYSTS (0xFFFFu) - -#define USB_BRDYSTS_SHIFT (0) - -/*==============================================*/ -/* NRDYSTS */ -/*==============================================*/ -#define USB_NRDYSTS (0xFFFFu) - -#define USB_NRDYSTS_SHIFT (0) - -/*==============================================*/ -/* BEMPSTS */ -/*==============================================*/ -#define USB_BEMPSTS (0xFFFFu) - -#define USB_BEMPSTS_SHIFT (0) - -/*==============================================*/ -/* FRMNUM */ -/*==============================================*/ -#define USB_FRMNUM_FRNM (0x07FFu) -/* #define USB_FRMNUM_RESERVED (0x3800u) */ -#define USB_FRMNUM_CRCE (0x4000u) -#define USB_FRMNUM_OVRN (0x8000u) - -#define USB_FRMNUM_FRNM_SHIFT (0) -/* #define USB_FRMNUM_RESERVED_SHIFT (11) */ -#define USB_FRMNUM_CRCE_SHIFT (14) -#define USB_FRMNUM_OVRN_SHIFT (15) - -/*==============================================*/ -/* UFRMNUM */ -/*==============================================*/ -#define USB_UFRMNUM_UFRNM (0x0007u) -/* #define USB_UFRMNUM_RESERVED (0xFFF8u) */ - -#define USB_UFRMNUM_UFRNM_SHIFT (0) -/* #define USB_UFRMNUM_RESERVED_SHIFT (3) */ - -/*==============================================*/ -/* USBADDR */ -/*==============================================*/ -#define USB_USBADDR_USBADDR (0x007Fu) -/* #define USB_USBADDR_RESERVED (0xFF80u) */ - -#define USB_USBADDR_USBADDR_SHIFT (0) -/* #define USB_USBADDR_RESERVED_SHIFT (7) */ - -/*==============================================*/ -/* USBREQ */ -/*==============================================*/ -#define USB_USBREQ_BMREQUESTTYPE (0x00FFu) -#define USB_USBREQ_BREQUEST (0xFF00u) - -#define USB_USBREQ_BMREQUESTTYPE_SHIFT (0) -#define USB_USBREQ_BREQUEST_SHIFT (8) - -/*==============================================*/ -/* USBVAL */ -/*==============================================*/ -#define USB_USBVAL (0xFFFFu) - -#define USB_USBVAL_SHIFT (0) - -/*==============================================*/ -/* USBINDX */ -/*==============================================*/ -#define USB_USBINDX (0xFFFFu) - -#define USB_USBINDX_SHIFT (0) - -/*==============================================*/ -/* USBLENG */ -/*==============================================*/ -#define USB_USBLENG (0xFFFFu) - -#define USB_USBLENG_SHIFT (0) - -/*==============================================*/ -/* DCPCFG */ -/*==============================================*/ -/* #define USB_DCPCFG_RESERVED1 (0x000Fu) */ -#define USB_DCPCFG_DIR (0x0010u) -/* #define USB_DCPCFG_RESERVED2 (0x0060u) */ -#define USB_DCPCFG_SHTNAK (0x0080u) -#define USB_DCPCFG_CNTMD (0x0100u) -/* #define USB_DCPCFG_RESERVED3 (0xFE00u) */ - -/* #define USB_DCPCFG_RESERVED1_SHIFT (0) */ -#define USB_DCPCFG_DIR_SHIFT (4) -/* #define USB_DCPCFG_RESERVED2_SHIFT (5) */ -#define USB_DCPCFG_SHTNK_SHIFT (7) -#define USB_DCPCFG_CNTMD_SHIFT (8) -/* #define USB_DCPCFG_RESERVED3 (9) */ - -/*==============================================*/ -/* DCPMAXP */ -/*==============================================*/ -#define USB_DCPMAXP_MXPS (0x007Fu) -/* #define USB_DCPMAXP_RESERVED (0x0F80u) */ -#define USB_DCPMAXP_DEVSEL (0xF000u) - -#define USB_DCPMAXP_MXPS_SHIFT (0) -/* #define USB_DCPMAXP_RESERVED_SHIFT (7) */ -#define USB_DCPMAXP_DEVSEL_SHIFT (12) - -/*==============================================*/ -/* DCPCTR */ -/*==============================================*/ -#define USB_DCPCTR_PID (0x0003u) -#define USB_DCPCTR_CCPL (0x0004u) -/* #define USB_DCPCTR_RESERVED1 (0x0008u) */ -#define USB_DCPCTR_PINGE (0x0010u) -#define USB_DCPCTR_PBUSY (0x0020u) -#define USB_DCPCTR_SQMON (0x0040u) -#define USB_DCPCTR_SQSET (0x0080u) -#define USB_DCPCTR_SQCLR (0x0100u) -/* #define USB_DCPCTR_RESERVED2 (0x0600u) */ -#define USB_DCPCTR_SUREQCLR (0x0800u) -#define USB_DCPCTR_CSSTS (0x1000u) -#define USB_DCPCTR_CSCLR (0x2000u) -#define USB_DCPCTR_SUREQ (0x4000u) -#define USB_DCPCTR_BSTS (0x8000u) - -#define USB_DCPCTR_PID_SHIFT (0) -#define USB_DCPCTR_CCPL_SHIFT (2) -/* #define USB_DCPCTR_RESERVED1_SHIFT (3) */ -#define USB_DCPCTR_PINGE_SHIFT (4) -#define USB_DCPCTR_PBUSY_SHIFT (5) -#define USB_DCPCTR_SQMON_SHIFT (6) -#define USB_DCPCTR_SQSET_SHIFT (7) -#define USB_DCPCTR_SQCLR_SHIFT (8) -/* #define USB_DCPCTR_RESERVED2_SHIFT (9) */ -#define USB_DCPCTR_SUREQCLR_SHIFT (11) -#define USB_DCPCTR_CSSTS_SHIFT (12) -#define USB_DCPCTR_CSCLR_SHIFT (13) -#define USB_DCPCTR_SUREQ_SHIFT (14) -#define USB_DCPCTR_BSTS_SHIFT (15) - -/*==============================================*/ -/* PIPESEL */ -/*==============================================*/ -#define USB_PIPESEL_PIPESEL (0x000Fu) -/* #define USB_PIPESEL_RESERVED (0xFFF0u) */ - -#define USB_PIPESEL_PIPESEL_SHIFT (0) -/* #define USB_PIPESEL_RESERVED_SHIFT (4) */ - -/*==============================================*/ -/* PIPECFG */ -/*==============================================*/ -#define USB_PIPECFG_EPNUM (0x000Fu) -#define USB_PIPECFG_DIR (0x0010u) -/* #define USB_PIPECFG_RESERVED1 (0x0060u) */ -#define USB_PIPECFG_SHTNAK (0x0080u) -#define USB_PIPECFG_CNTMD (0x0100u) -#define USB_PIPECFG_DBLB (0x0200u) -#define USB_PIPECFG_BFRE (0x0400u) -/* #define USB_PIPECFG_RESERVED2 (0x3800u) */ -#define USB_PIPECFG_TYPE (0xC000u) - -#define USB_PIPECFG_EPNUM_SHIFT (0) -#define USB_PIPECFG_DIR_SHIFT (4) -/* #define USB_PIPECFG_RESERVED1_SHIFT (5) */ -#define USB_PIPECFG_SHTNAK_SHIFT (7) -#define USB_PIPECFG_CNTMD_SHIFT (8) -#define USB_PIPECFG_DBLB_SHIFT (9) -#define USB_PIPECFG_BFRE_SHIFT (10) -/* #define USB_PIPECFG_RESERVED2_SHIFT (11) */ -#define USB_PIPECFG_TYPE_SHIFT (14) - -/*==============================================*/ -/* PIPEBUF */ -/*==============================================*/ -#define USB_PIPEBUF_BUFNMB (0x00FFu) -/* #define USB_PIPEBUF_RESERVED1 (0x0300u) */ -#define USB_PIPEBUF_BUFSIZE (0x7C00u) -/* #define USB_PIPEBUF_RESERVED2 (0x8000u) */ - -#define USB_PIPEBUF_BUFNMB_SHIFT (0) -/* #define USB_PIPEBUF_RESERVED1_SHIFT (8) */ -#define USB_PIPEBUF_BUFSIZE_SHIFT (10) -/* #define USB_PIPEBUF_RESERVED2_SHIFT (15) */ - -/*==============================================*/ -/* PIPEMAXP */ -/*==============================================*/ -#define USB_PIPEMAXP_MXPS (0x07FFu) -/* #define USB_PIPEMAXP_RESERVED (0x0800u) */ -#define USB_PIPEMAXP_DEVSEL (0xF000u) - -#define USB_PIPEMAXP_MXPS_SHIFT (0) -/* #define USB_PIPEMAXP_RESERVED_SHIFT (11) */ -#define USB_PIPEMAXP_DEVSEL_SHIFT (12) - -/*==============================================*/ -/* PIPEPERI */ -/*==============================================*/ -#define USB_PIPEPERI_IITV (0x0007u) -/* #define USB_PIPEPERI_RESERVED1 (0x0FF8u) */ -#define USB_PIPEPERI_IFIS (0x1000u) -/* #define USB_PIPEPERI_RESERVED2 (0xE000u) */ - -#define USB_PIPEPERI_IITV_SHIFT (0) -/* #define USB_PIPEPERI_RESERVED1_SHIFT (3) */ -#define USB_PIPEPERI_IFIS_SHIFT (12) -/* #define USB_PIPEPERI_RESERVED2_SHIFT (13) */ - -/*==============================================*/ -/* PIPEnCTR_1_5 */ -/*==============================================*/ -#define USB_PIPEnCTR_1_5_PID (0x0003u) -/* #define USB_PIPEnCTR_1_5_RESERVED1 (0x001Cu) */ -#define USB_PIPEnCTR_1_5_PBUSY (0x0020u) -#define USB_PIPEnCTR_1_5_SQMON (0x0040u) -#define USB_PIPEnCTR_1_5_SQSET (0x0080u) -#define USB_PIPEnCTR_1_5_SQCLR (0x0100u) -#define USB_PIPEnCTR_1_5_ACLRM (0x0200u) -#define USB_PIPEnCTR_1_5_ATREPM (0x0400u) -/* #define USB_PIPEnCTR_1_5_RESERVED2 (0x0800u) */ -#define USB_PIPEnCTR_1_5_CSSTS (0x1000u) -#define USB_PIPEnCTR_1_5_CSCLR (0x2000u) -#define USB_PIPEnCTR_1_5_INBUFM (0x4000u) -#define USB_PIPEnCTR_1_5_BSTS (0x8000u) - -#define USB_PIPEnCTR_1_5_PID_SHIFT (0) -/* #define USB_PIPEnCTR_1_5_RESERVED1_SHIFT (2) */ -#define USB_PIPEnCTR_1_5_PBUSY_SHIFT (5) -#define USB_PIPEnCTR_1_5_SQMON_SHIFT (6) -#define USB_PIPEnCTR_1_5_SQSET_SHIFT (7) -#define USB_PIPEnCTR_1_5_SQCLR_SHIFT (8) -#define USB_PIPEnCTR_1_5_ACLRM_SHIFT (9) -#define USB_PIPEnCTR_1_5_ATREPM_SHIFT (10) -/* #define USB_PIPEnCTR_1_5_RESERVED2_SHIFT (11) */ -#define USB_PIPEnCTR_1_5_CSSTS_SHIFT (12) -#define USB_PIPEnCTR_1_5_CSCLR_SHIFT (13) -#define USB_PIPEnCTR_1_5_INBUFM_SHIFT (14) -#define USB_PIPEnCTR_1_5_BSTS_SHIFT (15) - -/*==============================================*/ -/* PIPEnCTR_6_8 */ -/*==============================================*/ -#define USB_PIPEnCTR_6_8_PID (0x0003u) -/* #define USB_PIPEnCTR_6_8_RESERVED1 (0x001Cu) */ -#define USB_PIPEnCTR_6_8_PBUSY (0x0020u) -#define USB_PIPEnCTR_6_8_SQMON (0x0040u) -#define USB_PIPEnCTR_6_8_SQSET (0x0080u) -#define USB_PIPEnCTR_6_8_SQCLR (0x0100u) -#define USB_PIPEnCTR_6_8_ACLRM (0x0200u) -/* #define USB_PIPEnCTR_6_8_RESERVED2 (0x0C00u) */ -#define USB_PIPEnCTR_6_8_CSSTS (0x1000u) -#define USB_PIPEnCTR_6_8_CSCLR (0x2000u) -/* #define USB_PIPEnCTR_6_8_RESERVED3 (0x4000u) */ -#define USB_PIPEnCTR_6_8_BSTS (0x8000u) - -#define USB_PIPEnCTR_6_8_PID_SHIFT (0) -/* #define USB_PIPEnCTR_6_8_RESERVED1_SHIFT (2) */ -#define USB_PIPEnCTR_6_8_PBUSY_SHIFT (5) -#define USB_PIPEnCTR_6_8_SQMON_SHIFT (6) -#define USB_PIPEnCTR_6_8_SQSET_SHIFT (7) -#define USB_PIPEnCTR_6_8_SQCLR_SHIFT (8) -#define USB_PIPEnCTR_6_8_ACLRM_SHIFT (9) -/* #define USB_PIPEnCTR_6_8_RESERVED2_SHIFT (10) */ -#define USB_PIPEnCTR_6_8_CSSTS_SHIFT (12) -#define USB_PIPEnCTR_6_8_CSCLR_SHIFT (13) -/* #define USB_PIPEnCTR_6_8_RESERVED3_SHIFT (14) */ -#define USB_PIPEnCTR_6_8_BSTS_SHIFT (15) - -/*==============================================*/ -/* PIPEnCTR_9 */ -/*==============================================*/ -#define USB_PIPEnCTR_9_PID (0x0003u) -/* #define USB_PIPEnCTR_9_RESERVED1 (0x001Cu) */ -#define USB_PIPEnCTR_9_PBUSY (0x0020u) -#define USB_PIPEnCTR_9_SQMON (0x0040u) -#define USB_PIPEnCTR_9_SQSET (0x0080u) -#define USB_PIPEnCTR_9_SQCLR (0x0100u) -#define USB_PIPEnCTR_9_ACLRM (0x0200u) -#define USB_PIPEnCTR_9_ATREPM (0x0400u) -/* #define USB_PIPEnCTR_9_RESERVED2 (0x0800u) */ -#define USB_PIPEnCTR_9_CSSTS (0x1000u) -#define USB_PIPEnCTR_9_CSCLR (0x2000u) -#define USB_PIPEnCTR_9_INBUFM (0x4000u) -#define USB_PIPEnCTR_9_BSTS (0x8000u) - -#define USB_PIPEnCTR_9_PID_SHIFT (0) -/* #define USB_PIPEnCTR_9_RESERVED1_SHIFT (2) */ -#define USB_PIPEnCTR_9_PBUSY_SHIFT (5) -#define USB_PIPEnCTR_9_SQMON_SHIFT (6) -#define USB_PIPEnCTR_9_SQSET_SHIFT (7) -#define USB_PIPEnCTR_9_SQCLR_SHIFT (8) -#define USB_PIPEnCTR_9_ACLRM_SHIFT (9) -#define USB_PIPEnCTR_9_ATREPM_SHIFT (10) -/* #define USB_PIPEnCTR_9_RESERVED2_SHIFT (11) */ -#define USB_PIPEnCTR_9_CSSTS_SHIFT (12) -#define USB_PIPEnCTR_9_CSCLR_SHIFT (13) -#define USB_PIPEnCTR_9_INBUFM_SHIFT (14) -#define USB_PIPEnCTR_9_BSTS_SHIFT (15) - -/*==============================================*/ -/* PIPEnCTR_A_F */ -/*==============================================*/ -#define USB_PIPEnCTR_A_F_PID (0x0003u) -/* #define USB_PIPEnCTR_A_F_RESERVED1 (0x001Cu) */ -#define USB_PIPEnCTR_A_F_PBUSY (0x0020u) -#define USB_PIPEnCTR_A_F_SQMON (0x0040u) -#define USB_PIPEnCTR_A_F_SQSET (0x0080u) -#define USB_PIPEnCTR_A_F_SQCLR (0x0100u) -#define USB_PIPEnCTR_A_F_ACLRM (0x0200u) -#define USB_PIPEnCTR_A_F_ATREPM (0x0400u) -/* #define USB_PIPEnCTR_A_F_RESERVED2 (0x3800u) */ -#define USB_PIPEnCTR_A_F_INBUFM (0x4000u) -#define USB_PIPEnCTR_A_F_BSTS (0x8000u) - -#define USB_PIPEnCTR_A_F_PID_SHIFT (0) -/* #define USB_PIPEnCTR_A_F_RESERVED1_SHIFT (2) */ -#define USB_PIPEnCTR_A_F_PBUSY_SHIFT (5) -#define USB_PIPEnCTR_A_F_SQMON_SHIFT (6) -#define USB_PIPEnCTR_A_F_SQSET_SHIFT (7) -#define USB_PIPEnCTR_A_F_SQCLR_SHIFT (8) -#define USB_PIPEnCTR_A_F_ACLRM_SHIFT (9) -#define USB_PIPEnCTR_A_F_ATREPM_SHIFT (10) -/* #define USB_PIPEnCTR_A_F_RESERVED2_SHIFT (11) */ -#define USB_PIPEnCTR_A_F_INBUFM_SHIFT (14) -#define USB_PIPEnCTR_A_F_BSTS_SHIFT (15) - -/*==============================================*/ -/* PIPEnTRE */ -/*==============================================*/ -/* #define USB_PIPEnTRE_RESERVED1 (0x00FFu) */ -#define USB_PIPEnTRE_TRCLR (0x0100u) -#define USB_PIPEnTRE_TRENB (0x0200u) -/* #define USB_PIPEnTRE_RESERVED2 (0xFC00u) */ - -/* #define USB_PIPEnTRE_RESERVED1_SHIFT (0) */ -#define USB_PIPEnTRE_TRCLR_SHIFT (8) -#define USB_PIPEnTRE_TRENB_SHIFT (9) -/* #define USB_PIPEnTRE_RESERVED2_SHIFT (10) */ - -/*==============================================*/ -/* PIPEnTRN */ -/*==============================================*/ -#define USB_PIPEnTRN (0xFFFFu) - -#define USB_PIPEnTRN_SHIFT (0) - -/*==============================================*/ -/* DEVADDn */ -/*==============================================*/ -/* #define USB_DEVADDn_RESERVED1 (0x003Fu) */ -#define USB_DEVADDn_USBSPD (0x00C0u) -#define USB_DEVADDn_HUBPORT (0x0700u) -#define USB_DEVADDn_UPPHUB (0x7800u) -/* #define USB_DEVADDn_RESERVED2 (0x8000u) */ - -/* #define USB_DEVADDn_RESERVED1_SHIFT (0) */ -#define USB_DEVADDn_USBSPD_SHIFT (6) -#define USB_DEVADDn_HUBPORT_SHIFT (8) -#define USB_DEVADDn_UPPHUB_SHIFT (11) -/* #define USB_DEVADDn_RESERVED2_SHIFT (15) */ - -/*==============================================*/ -/* SUSPMODE */ -/*==============================================*/ -/* #define USB_SUSPMODE_RESERVED1 (0x3FFFu) */ -#define USB_SUSPMODE_SUSPM (0x4000u) -/* #define USB_SUSPMODE_RESERVED2 (0x8000u) */ - -/* #define USB_SUSPMODE_RESERVED1_SHIFT (0) */ -#define USB_SUSPMODE_SUSPM_SHIFT (14) -/* #define USB_SUSPMODE_RESERVED2_SHIFT (15) */ - -/*==============================================*/ -/* DnFIFOBm */ -/*==============================================*/ -#define USB_DnFIFOBm (0xFFFFu) - -#define USB_DnFIFOBm_SHIFT (0) - -#endif /* USB_IOBITMASK_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h deleted file mode 100644 index d01d74b0e69..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h +++ /dev/null @@ -1,73 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef R7S721000_IODEFINE_H -#define R7S721000_IODEFINE_H - -#include "iodefines/iodefine_typedef.h" /* (V2.00h) */ - -#include "iodefines/adc_iodefine.h" /* (V2.00h) */ -#include "iodefines/bsc_iodefine.h" /* (V2.00h) */ -#include "iodefines/ceu_iodefine.h" /* (V2.00h) */ -#include "iodefines/cpg_iodefine.h" /* (V2.00h) */ -#include "iodefines/disc_iodefine.h" /* (V2.00h) */ -#include "iodefines/dmac_iodefine.h" /* (V2.00h) */ -#include "iodefines/dvdec_iodefine.h" /* (V2.00h) */ -#include "iodefines/ether_iodefine.h" /* (V2.00h) */ -#include "iodefines/flctl_iodefine.h" /* (V2.00h) */ -#include "iodefines/gpio_iodefine.h" /* (V2.00h) */ -#include "iodefines/ieb_iodefine.h" /* (V2.00h) */ -#include "iodefines/inb_iodefine.h" /* (V2.00h) */ -#include "iodefines/intc_iodefine.h" /* (V2.00h) */ -#include "iodefines/irda_iodefine.h" /* (V2.00h) */ -#include "iodefines/jcu_iodefine.h" /* (V2.00h) */ -#include "iodefines/l2c_iodefine.h" /* (V2.00h) */ -#include "iodefines/lin_iodefine.h" /* (V2.00h) */ -#include "iodefines/lvds_iodefine.h" /* (V2.00h) */ -#include "iodefines/mlb_iodefine.h" /* (V2.00h) */ -#include "iodefines/mmc_iodefine.h" /* (V2.00h) */ -#include "iodefines/mtu2_iodefine.h" /* (V2.00h) */ -#include "iodefines/ostm_iodefine.h" /* (V2.00h) */ -#include "iodefines/pfv_iodefine.h" /* (V2.00h) */ -#include "iodefines/pwm_iodefine.h" /* (V2.00h) */ -#include "iodefines/riic_iodefine.h" /* (V2.00h) */ -#include "iodefines/romdec_iodefine.h" /* (V2.00h) */ -#include "iodefines/rscan0_iodefine.h" /* (V2.00h) */ -#include "iodefines/rspi_iodefine.h" /* (V2.00h) */ -#include "iodefines/rtc_iodefine.h" /* (V2.00h) */ -#include "iodefines/scif_iodefine.h" /* (V2.00h) */ -#include "iodefines/scim_iodefine.h" /* (V2.00h) */ -#include "iodefines/scux_iodefine.h" /* (V2.00h) */ -#include "iodefines/sdg_iodefine.h" /* (V2.00h) */ -#include "iodefines/spdif_iodefine.h" /* (V2.00h) */ -#include "iodefines/spibsc_iodefine.h" /* (V2.00h) */ -#include "iodefines/ssif_iodefine.h" /* (V2.00h) */ -#include "iodefines/usb20_iodefine.h" /* (V2.00h) */ -#include "iodefines/vdc5_iodefine.h" /* (V2.00h) */ -#include "iodefines/wdt_iodefine.h" /* (V2.00h) */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h deleted file mode 100644 index a16183efcc9..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h +++ /dev/null @@ -1,107 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : adc_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef ADC_IODEFINE_H -#define ADC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ - - -#define ADCADDRA (ADC.ADDRA) -#define ADCADDRB (ADC.ADDRB) -#define ADCADDRC (ADC.ADDRC) -#define ADCADDRD (ADC.ADDRD) -#define ADCADDRE (ADC.ADDRE) -#define ADCADDRF (ADC.ADDRF) -#define ADCADDRG (ADC.ADDRG) -#define ADCADDRH (ADC.ADDRH) -#define ADCADCMPHA (ADC.ADCMPHA) -#define ADCADCMPLA (ADC.ADCMPLA) -#define ADCADCMPHB (ADC.ADCMPHB) -#define ADCADCMPLB (ADC.ADCMPLB) -#define ADCADCMPHC (ADC.ADCMPHC) -#define ADCADCMPLC (ADC.ADCMPLC) -#define ADCADCMPHD (ADC.ADCMPHD) -#define ADCADCMPLD (ADC.ADCMPLD) -#define ADCADCMPHE (ADC.ADCMPHE) -#define ADCADCMPLE (ADC.ADCMPLE) -#define ADCADCMPHF (ADC.ADCMPHF) -#define ADCADCMPLF (ADC.ADCMPLF) -#define ADCADCMPHG (ADC.ADCMPHG) -#define ADCADCMPLG (ADC.ADCMPLG) -#define ADCADCMPHH (ADC.ADCMPHH) -#define ADCADCMPLH (ADC.ADCMPLH) -#define ADCADCSR (ADC.ADCSR) -#define ADCADCMPER (ADC.ADCMPER) -#define ADCADCMPSR (ADC.ADCMPSR) - - -typedef struct st_adc -{ - /* ADC */ - volatile uint16_t ADDRA; /* ADDRA */ - volatile uint16_t ADDRB; /* ADDRB */ - volatile uint16_t ADDRC; /* ADDRC */ - volatile uint16_t ADDRD; /* ADDRD */ - volatile uint16_t ADDRE; /* ADDRE */ - volatile uint16_t ADDRF; /* ADDRF */ - volatile uint16_t ADDRG; /* ADDRG */ - volatile uint16_t ADDRH; /* ADDRH */ - volatile uint8_t dummy32[16]; /* */ - volatile uint16_t ADCMPHA; /* ADCMPHA */ - volatile uint16_t ADCMPLA; /* ADCMPLA */ - volatile uint16_t ADCMPHB; /* ADCMPHB */ - volatile uint16_t ADCMPLB; /* ADCMPLB */ - volatile uint16_t ADCMPHC; /* ADCMPHC */ - volatile uint16_t ADCMPLC; /* ADCMPLC */ - volatile uint16_t ADCMPHD; /* ADCMPHD */ - volatile uint16_t ADCMPLD; /* ADCMPLD */ - volatile uint16_t ADCMPHE; /* ADCMPHE */ - volatile uint16_t ADCMPLE; /* ADCMPLE */ - volatile uint16_t ADCMPHF; /* ADCMPHF */ - volatile uint16_t ADCMPLF; /* ADCMPLF */ - volatile uint16_t ADCMPHG; /* ADCMPHG */ - volatile uint16_t ADCMPLG; /* ADCMPLG */ - volatile uint16_t ADCMPHH; /* ADCMPHH */ - volatile uint16_t ADCMPLH; /* ADCMPLH */ - volatile uint8_t dummy33[32]; /* */ - volatile uint16_t ADCSR; /* ADCSR */ - volatile uint16_t ADCMPER; /* ADCMPER */ - volatile uint16_t ADCMPSR; /* ADCMPSR */ -} r_io_adc_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h deleted file mode 100644 index 6665787ee7d..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h +++ /dev/null @@ -1,115 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : bsc_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef BSC_IODEFINE_H -#define BSC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ - - -#define BSCCMNCR (BSC.CMNCR) -#define BSCCS0BCR (BSC.CS0BCR) -#define BSCCS1BCR (BSC.CS1BCR) -#define BSCCS2BCR (BSC.CS2BCR) -#define BSCCS3BCR (BSC.CS3BCR) -#define BSCCS4BCR (BSC.CS4BCR) -#define BSCCS5BCR (BSC.CS5BCR) -#define BSCCS0WCR (BSC.CS0WCR) -#define BSCCS1WCR (BSC.CS1WCR) -#define BSCCS2WCR (BSC.CS2WCR) -#define BSCCS3WCR (BSC.CS3WCR) -#define BSCCS4WCR (BSC.CS4WCR) -#define BSCCS5WCR (BSC.CS5WCR) -#define BSCSDCR (BSC.SDCR) -#define BSCRTCSR (BSC.RTCSR) -#define BSCRTCNT (BSC.RTCNT) -#define BSCRTCOR (BSC.RTCOR) -#define BSCTOSCOR0 (BSC.TOSCOR0) -#define BSCTOSCOR1 (BSC.TOSCOR1) -#define BSCTOSCOR2 (BSC.TOSCOR2) -#define BSCTOSCOR3 (BSC.TOSCOR3) -#define BSCTOSCOR4 (BSC.TOSCOR4) -#define BSCTOSCOR5 (BSC.TOSCOR5) -#define BSCTOSTR (BSC.TOSTR) -#define BSCTOENR (BSC.TOENR) - -#define BSC_CSnBCR_COUNT (6) -#define BSC_CSnWCR_COUNT (6) -#define BSC_TOSCORn_COUNT (6) - - -typedef struct st_bsc -{ - /* BSC */ - volatile uint32_t CMNCR; /* CMNCR */ - -/* #define BSC_CSnBCR_COUNT (6) */ - volatile uint32_t CS0BCR; /* CS0BCR */ - volatile uint32_t CS1BCR; /* CS1BCR */ - volatile uint32_t CS2BCR; /* CS2BCR */ - volatile uint32_t CS3BCR; /* CS3BCR */ - volatile uint32_t CS4BCR; /* CS4BCR */ - volatile uint32_t CS5BCR; /* CS5BCR */ - volatile uint8_t dummy4[12]; /* */ - -/* #define BSC_CSnWCR_COUNT (6) */ - volatile uint32_t CS0WCR; /* CS0WCR */ - volatile uint32_t CS1WCR; /* CS1WCR */ - volatile uint32_t CS2WCR; /* CS2WCR */ - volatile uint32_t CS3WCR; /* CS3WCR */ - volatile uint32_t CS4WCR; /* CS4WCR */ - volatile uint32_t CS5WCR; /* CS5WCR */ - volatile uint8_t dummy5[12]; /* */ - volatile uint32_t SDCR; /* SDCR */ - volatile uint32_t RTCSR; /* RTCSR */ - volatile uint32_t RTCNT; /* RTCNT */ - volatile uint32_t RTCOR; /* RTCOR */ - volatile uint8_t dummy6[4]; /* */ - -/* #define BSC_TOSCORn_COUNT (6) */ - volatile uint32_t TOSCOR0; /* TOSCOR0 */ - volatile uint32_t TOSCOR1; /* TOSCOR1 */ - volatile uint32_t TOSCOR2; /* TOSCOR2 */ - volatile uint32_t TOSCOR3; /* TOSCOR3 */ - volatile uint32_t TOSCOR4; /* TOSCOR4 */ - volatile uint32_t TOSCOR5; /* TOSCOR5 */ - volatile uint8_t dummy7[8]; /* */ - volatile uint32_t TOSTR; /* TOSTR */ - volatile uint32_t TOENR; /* TOENR */ -} r_io_bsc_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h deleted file mode 100644 index a970bfd807a..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h +++ /dev/null @@ -1,295 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : ceu_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef CEU_IODEFINE_H -#define CEU_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ - - -/* Start of channel array defines of CEU */ - -/* Channel array defines of CEUn */ -/*(Sample) value = CEUn[ channel ]->CAMOR; */ -#define CEUn_COUNT (3) -#define CEUn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - (volatile struct st_ceu_n*)&CEU_A, \ - (volatile struct st_ceu_n*)&CEU_B, \ - (volatile struct st_ceu_n*)&CEU_M \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ -#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ -#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ - -/* End of channel array defines of CEU */ - - -#define CEUCAPSR (CEU.CAPSR) -#define CEUCAPCR (CEU.CAPCR) -#define CEUCAMCR (CEU.CAMCR) -#define CEUCMCYR (CEU.CMCYR) -#define CEUCAMOR_A (CEU.CAMOR_A) -#define CEUCAPWR_A (CEU.CAPWR_A) -#define CEUCAIFR (CEU.CAIFR) -#define CEUCRCNTR (CEU.CRCNTR) -#define CEUCRCMPR (CEU.CRCMPR) -#define CEUCFLCR_A (CEU.CFLCR_A) -#define CEUCFSZR_A (CEU.CFSZR_A) -#define CEUCDWDR_A (CEU.CDWDR_A) -#define CEUCDAYR_A (CEU.CDAYR_A) -#define CEUCDACR_A (CEU.CDACR_A) -#define CEUCDBYR_A (CEU.CDBYR_A) -#define CEUCDBCR_A (CEU.CDBCR_A) -#define CEUCBDSR_A (CEU.CBDSR_A) -#define CEUCFWCR (CEU.CFWCR) -#define CEUCLFCR_A (CEU.CLFCR_A) -#define CEUCDOCR_A (CEU.CDOCR_A) -#define CEUCEIER (CEU.CEIER) -#define CEUCETCR (CEU.CETCR) -#define CEUCSTSR (CEU.CSTSR) -#define CEUCDSSR (CEU.CDSSR) -#define CEUCDAYR2_A (CEU.CDAYR2_A) -#define CEUCDACR2_A (CEU.CDACR2_A) -#define CEUCDBYR2_A (CEU.CDBYR2_A) -#define CEUCDBCR2_A (CEU.CDBCR2_A) -#define CEUCAMOR_B (CEU.CAMOR_B) -#define CEUCAPWR_B (CEU.CAPWR_B) -#define CEUCFLCR_B (CEU.CFLCR_B) -#define CEUCFSZR_B (CEU.CFSZR_B) -#define CEUCDWDR_B (CEU.CDWDR_B) -#define CEUCDAYR_B (CEU.CDAYR_B) -#define CEUCDACR_B (CEU.CDACR_B) -#define CEUCDBYR_B (CEU.CDBYR_B) -#define CEUCDBCR_B (CEU.CDBCR_B) -#define CEUCBDSR_B (CEU.CBDSR_B) -#define CEUCLFCR_B (CEU.CLFCR_B) -#define CEUCDOCR_B (CEU.CDOCR_B) -#define CEUCDAYR2_B (CEU.CDAYR2_B) -#define CEUCDACR2_B (CEU.CDACR2_B) -#define CEUCDBYR2_B (CEU.CDBYR2_B) -#define CEUCDBCR2_B (CEU.CDBCR2_B) -#define CEUCAMOR_M (CEU.CAMOR_M) -#define CEUCAPWR_M (CEU.CAPWR_M) -#define CEUCFLCR_M (CEU.CFLCR_M) -#define CEUCFSZR_M (CEU.CFSZR_M) -#define CEUCDWDR_M (CEU.CDWDR_M) -#define CEUCDAYR_M (CEU.CDAYR_M) -#define CEUCDACR_M (CEU.CDACR_M) -#define CEUCDBYR_M (CEU.CDBYR_M) -#define CEUCDBCR_M (CEU.CDBCR_M) -#define CEUCBDSR_M (CEU.CBDSR_M) -#define CEUCLFCR_M (CEU.CLFCR_M) -#define CEUCDOCR_M (CEU.CDOCR_M) -#define CEUCDAYR2_M (CEU.CDAYR2_M) -#define CEUCDACR2_M (CEU.CDACR2_M) -#define CEUCDBYR2_M (CEU.CDBYR2_M) -#define CEUCDBCR2_M (CEU.CDBCR2_M) - - -typedef struct st_ceu -{ - /* CEU */ - -/* start of struct st_ceu_n */ - volatile uint32_t CAPSR; /* CAPSR */ - volatile uint32_t CAPCR; /* CAPCR */ - volatile uint32_t CAMCR; /* CAMCR */ - volatile uint32_t CMCYR; /* CMCYR */ - volatile uint32_t CAMOR_A; /* CAMOR_A */ - volatile uint32_t CAPWR_A; /* CAPWR_A */ - volatile uint32_t CAIFR; /* CAIFR */ - volatile uint8_t dummy305[12]; /* */ - volatile uint32_t CRCNTR; /* CRCNTR */ - volatile uint32_t CRCMPR; /* CRCMPR */ - volatile uint32_t CFLCR_A; /* CFLCR_A */ - volatile uint32_t CFSZR_A; /* CFSZR_A */ - volatile uint32_t CDWDR_A; /* CDWDR_A */ - volatile uint32_t CDAYR_A; /* CDAYR_A */ - volatile uint32_t CDACR_A; /* CDACR_A */ - volatile uint32_t CDBYR_A; /* CDBYR_A */ - volatile uint32_t CDBCR_A; /* CDBCR_A */ - volatile uint32_t CBDSR_A; /* CBDSR_A */ - volatile uint8_t dummy306[12]; /* */ - volatile uint32_t CFWCR; /* CFWCR */ - volatile uint32_t CLFCR_A; /* CLFCR_A */ - volatile uint32_t CDOCR_A; /* CDOCR_A */ - volatile uint8_t dummy307[8]; /* */ - volatile uint32_t CEIER; /* CEIER */ - volatile uint32_t CETCR; /* CETCR */ - volatile uint8_t dummy308[4]; /* */ - volatile uint32_t CSTSR; /* CSTSR */ - volatile uint8_t dummy309[4]; /* */ - volatile uint32_t CDSSR; /* CDSSR */ - volatile uint8_t dummy310[8]; /* */ - volatile uint32_t CDAYR2_A; /* CDAYR2_A */ - volatile uint32_t CDACR2_A; /* CDACR2_A */ - volatile uint32_t CDBYR2_A; /* CDBYR2_A */ - volatile uint32_t CDBCR2_A; /* CDBCR2_A */ - -/* end of struct st_ceu_n */ - volatile uint8_t dummy3110[3936]; /* */ - -/* start of struct st_ceu_n */ - volatile uint8_t dummy3111[4]; /* */ - volatile uint8_t dummy3112[4]; /* */ - volatile uint8_t dummy3113[4]; /* */ - volatile uint8_t dummy3114[4]; /* */ - volatile uint32_t CAMOR_B; /* CAMOR_B */ - volatile uint32_t CAPWR_B; /* CAPWR_B */ - volatile uint8_t dummy3120[4]; /* */ - volatile uint8_t dummy3121[12]; /* */ - volatile uint8_t dummy3122[4]; /* */ - volatile uint8_t dummy3123[4]; /* */ - volatile uint32_t CFLCR_B; /* CFLCR_B */ - volatile uint32_t CFSZR_B; /* CFSZR_B */ - volatile uint32_t CDWDR_B; /* CDWDR_B */ - volatile uint32_t CDAYR_B; /* CDAYR_B */ - volatile uint32_t CDACR_B; /* CDACR_B */ - volatile uint32_t CDBYR_B; /* CDBYR_B */ - volatile uint32_t CDBCR_B; /* CDBCR_B */ - volatile uint32_t CBDSR_B; /* CBDSR_B */ - volatile uint8_t dummy3130[12]; /* */ - volatile uint8_t dummy3131[4]; /* */ - volatile uint32_t CLFCR_B; /* CLFCR_B */ - volatile uint32_t CDOCR_B; /* CDOCR_B */ - volatile uint8_t dummy3140[8]; /* */ - volatile uint8_t dummy3141[4]; /* */ - volatile uint8_t dummy3142[4]; /* */ - volatile uint8_t dummy3143[4]; /* */ - volatile uint8_t dummy3144[4]; /* */ - volatile uint8_t dummy3145[4]; /* */ - volatile uint8_t dummy3146[4]; /* */ - volatile uint8_t dummy3147[8]; /* */ - volatile uint32_t CDAYR2_B; /* CDAYR2_B */ - volatile uint32_t CDACR2_B; /* CDACR2_B */ - volatile uint32_t CDBYR2_B; /* CDBYR2_B */ - volatile uint32_t CDBCR2_B; /* CDBCR2_B */ - -/* end of struct st_ceu_n */ - volatile uint8_t dummy3150[3936]; /* */ - -/* start of struct st_ceu_n */ - volatile uint8_t dummy3151[4]; /* */ - volatile uint8_t dummy3152[4]; /* */ - volatile uint8_t dummy3153[4]; /* */ - volatile uint8_t dummy3154[4]; /* */ - volatile uint32_t CAMOR_M; /* CAMOR_M */ - volatile uint32_t CAPWR_M; /* CAPWR_M */ - volatile uint8_t dummy3160[4]; /* */ - volatile uint8_t dummy3161[12]; /* */ - volatile uint8_t dummy3162[4]; /* */ - volatile uint8_t dummy3163[4]; /* */ - volatile uint32_t CFLCR_M; /* CFLCR_M */ - volatile uint32_t CFSZR_M; /* CFSZR_M */ - volatile uint32_t CDWDR_M; /* CDWDR_M */ - volatile uint32_t CDAYR_M; /* CDAYR_M */ - volatile uint32_t CDACR_M; /* CDACR_M */ - volatile uint32_t CDBYR_M; /* CDBYR_M */ - volatile uint32_t CDBCR_M; /* CDBCR_M */ - volatile uint32_t CBDSR_M; /* CBDSR_M */ - volatile uint8_t dummy3170[12]; /* */ - volatile uint8_t dummy3171[4]; /* */ - volatile uint32_t CLFCR_M; /* CLFCR_M */ - volatile uint32_t CDOCR_M; /* CDOCR_M */ - volatile uint8_t dummy3180[8]; /* */ - volatile uint8_t dummy3181[4]; /* */ - volatile uint8_t dummy3182[4]; /* */ - volatile uint8_t dummy3183[4]; /* */ - volatile uint8_t dummy3184[4]; /* */ - volatile uint8_t dummy3185[4]; /* */ - volatile uint8_t dummy3186[4]; /* */ - volatile uint8_t dummy3187[8]; /* */ - volatile uint32_t CDAYR2_M; /* CDAYR2_M */ - volatile uint32_t CDACR2_M; /* CDACR2_M */ - volatile uint32_t CDBYR2_M; /* CDBYR2_M */ - volatile uint32_t CDBCR2_M; /* CDBCR2_M */ - -/* end of struct st_ceu_n */ -} r_io_ceu_t; - - -typedef struct st_ceu_n -{ - - volatile uint32_t not_common1; /* */ - volatile uint32_t not_common2; /* */ - volatile uint32_t not_common3; /* */ - volatile uint32_t not_common4; /* */ - volatile uint32_t CAMOR; /* CAMOR */ - volatile uint32_t CAPWR; /* CAPWR */ - volatile uint32_t not_common5; /* */ - volatile uint8_t dummy322[12]; /* */ - volatile uint32_t not_common6; /* */ - volatile uint32_t not_common7; /* */ - volatile uint32_t CFLCR; /* CFLCR */ - volatile uint32_t CFSZR; /* CFSZR */ - volatile uint32_t CDWDR; /* CDWDR */ - volatile uint32_t CDAYR; /* CDAYR */ - volatile uint32_t CDACR; /* CDACR */ - volatile uint32_t CDBYR; /* CDBYR */ - volatile uint32_t CDBCR; /* CDBCR */ - volatile uint32_t CBDSR; /* CBDSR */ - volatile uint8_t dummy323[12]; /* */ - volatile uint32_t not_common8; /* */ - volatile uint32_t CLFCR; /* CLFCR */ - volatile uint32_t CDOCR; /* CDOCR */ - volatile uint8_t dummy324[8]; /* */ - volatile uint32_t not_common9; /* */ - volatile uint32_t not_common10; /* */ - volatile uint8_t dummy325[4]; /* */ - volatile uint32_t not_common11; /* */ - volatile uint8_t dummy326[4]; /* */ - volatile uint32_t not_common12; /* */ - volatile uint8_t dummy327[8]; /* */ - volatile uint32_t CDAYR2; /* CDAYR2 */ - volatile uint32_t CDACR2; /* CDACR2 */ - volatile uint32_t CDBYR2; /* CDBYR2 */ - volatile uint32_t CDBCR2; /* CDBCR2 */ -} r_io_ceu_n_t; - - -/* Channel array defines of CEUn (2)*/ -#ifdef DECLARE_CEUn_CHANNELS -volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - CEUn_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_CEUn_CHANNELS */ -/* End of channel array defines of CEUn (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h deleted file mode 100644 index 6260ad010e8..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h +++ /dev/null @@ -1,307 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : cpg_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef CPG_IODEFINE_H -#define CPG_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ - - -/* Start of channel array defines of CPG */ - -/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */ -/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ -#define CPG_FROM_SWRSTCR1_ARRAY_COUNT (3) -#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ -#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ -#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ - - -/* Channel array defines of CPG_FROM_STBCR3_ARRAY */ -/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ -#define CPG_FROM_STBCR3_ARRAY_COUNT (10) -#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ - &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ -#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ -#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ -#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ -#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ -#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ -#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ -#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ -#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ -#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ - - -/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */ -/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ -#define CPG_FROM_SYSCR1_ARRAY_COUNT (3) -#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ -#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ -#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ - -/* End of channel array defines of CPG */ - - -#define CPGFRQCR (CPG.FRQCR) -#define CPGFRQCR2 (CPG.FRQCR2) -#define CPGCPUSTS (CPG.CPUSTS) -#define CPGSTBCR1 (CPG.STBCR1) -#define CPGSTBCR2 (CPG.STBCR2) -#define CPGSTBREQ1 (CPG.STBREQ1) -#define CPGSTBREQ2 (CPG.STBREQ2) -#define CPGSTBACK1 (CPG.STBACK1) -#define CPGSTBACK2 (CPG.STBACK2) -#define CPGSYSCR1 (CPG.SYSCR1) -#define CPGSYSCR2 (CPG.SYSCR2) -#define CPGSYSCR3 (CPG.SYSCR3) -#define CPGSTBCR3 (CPG.STBCR3) -#define CPGSTBCR4 (CPG.STBCR4) -#define CPGSTBCR5 (CPG.STBCR5) -#define CPGSTBCR6 (CPG.STBCR6) -#define CPGSTBCR7 (CPG.STBCR7) -#define CPGSTBCR8 (CPG.STBCR8) -#define CPGSTBCR9 (CPG.STBCR9) -#define CPGSTBCR10 (CPG.STBCR10) -#define CPGSTBCR11 (CPG.STBCR11) -#define CPGSTBCR12 (CPG.STBCR12) -#define CPGSWRSTCR1 (CPG.SWRSTCR1) -#define CPGSWRSTCR2 (CPG.SWRSTCR2) -#define CPGSWRSTCR3 (CPG.SWRSTCR3) -#define CPGSTBCR13 (CPG.STBCR13) -#define CPGRRAMKP (CPG.RRAMKP) -#define CPGDSCTR (CPG.DSCTR) -#define CPGDSSSR (CPG.DSSSR) -#define CPGDSESR (CPG.DSESR) -#define CPGDSFR (CPG.DSFR) -#define CPGXTALCTR (CPG.XTALCTR) - - -typedef struct st_cpg -{ - /* CPG */ - volatile uint16_t FRQCR; /* FRQCR */ - volatile uint8_t dummy319[2]; /* */ - volatile uint16_t FRQCR2; /* FRQCR2 */ - volatile uint8_t dummy320[2]; /* */ - volatile uint8_t CPUSTS; /* CPUSTS */ - volatile uint8_t dummy321[7]; /* */ - volatile uint8_t STBCR1; /* STBCR1 */ - volatile uint8_t dummy322[3]; /* */ - volatile uint8_t STBCR2; /* STBCR2 */ - volatile uint8_t dummy323[11]; /* */ - volatile uint8_t STBREQ1; /* STBREQ1 */ - volatile uint8_t dummy324[3]; /* */ - volatile uint8_t STBREQ2; /* STBREQ2 */ - volatile uint8_t dummy325[11]; /* */ - volatile uint8_t STBACK1; /* STBACK1 */ - volatile uint8_t dummy326[3]; /* */ - volatile uint8_t STBACK2; /* STBACK2 */ - volatile uint8_t dummy327[955]; /* */ - -/* start of struct st_cpg_from_syscr1 */ - volatile uint8_t SYSCR1; /* SYSCR1 */ - volatile uint8_t dummy328[3]; /* */ - -/* end of struct st_cpg_from_syscr1 */ - -/* start of struct st_cpg_from_syscr1 */ - volatile uint8_t SYSCR2; /* SYSCR2 */ - volatile uint8_t dummy329[3]; /* */ - -/* end of struct st_cpg_from_syscr1 */ - -/* start of struct st_cpg_from_syscr1 */ - volatile uint8_t SYSCR3; /* SYSCR3 */ - volatile uint8_t dummy3300[3]; /* */ - -/* end of struct st_cpg_from_syscr1 */ - volatile uint8_t dummy3301[20]; /* */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR3; /* STBCR3 */ - volatile uint8_t dummy331[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR4; /* STBCR4 */ - volatile uint8_t dummy332[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR5; /* STBCR5 */ - volatile uint8_t dummy333[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR6; /* STBCR6 */ - volatile uint8_t dummy334[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR7; /* STBCR7 */ - volatile uint8_t dummy335[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR8; /* STBCR8 */ - volatile uint8_t dummy336[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR9; /* STBCR9 */ - volatile uint8_t dummy337[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR10; /* STBCR10 */ - volatile uint8_t dummy338[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR11; /* STBCR11 */ - volatile uint8_t dummy339[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - -/* start of struct st_cpg_from_stbcr3 */ - volatile uint8_t STBCR12; /* STBCR12 */ - volatile uint8_t dummy3400[3]; /* */ - -/* end of struct st_cpg_from_stbcr3 */ - volatile uint8_t dummy3401[24]; /* */ - -/* start of struct st_cpg_from_swrstcr1 */ - volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ - volatile uint8_t dummy341[3]; /* */ - -/* end of struct st_cpg_from_swrstcr1 */ - -/* start of struct st_cpg_from_swrstcr1 */ - volatile uint8_t SWRSTCR2; /* SWRSTCR2 */ - volatile uint8_t dummy342[3]; /* */ - -/* end of struct st_cpg_from_swrstcr1 */ - -/* start of struct st_cpg_from_swrstcr1 */ - volatile uint8_t SWRSTCR3; /* SWRSTCR3 */ - volatile uint8_t dummy3430[3]; /* */ - -/* end of struct st_cpg_from_swrstcr1 */ - volatile uint8_t dummy3431[4]; /* */ - volatile uint8_t STBCR13; /* STBCR13 */ - volatile uint8_t dummy344[70543]; /* */ - volatile uint8_t RRAMKP; /* RRAMKP */ - volatile uint8_t dummy345[1]; /* */ - volatile uint8_t DSCTR; /* DSCTR */ - volatile uint8_t dummy346[1]; /* */ - volatile uint16_t DSSSR; /* DSSSR */ - volatile uint16_t DSESR; /* DSESR */ - volatile uint16_t DSFR; /* DSFR */ - volatile uint8_t dummy347[6]; /* */ - volatile uint8_t XTALCTR; /* XTALCTR */ -} r_io_cpg_t; - - -typedef struct st_cpg_from_syscr1 -{ - - volatile uint8_t SYSCR1; /* SYSCR1 */ - volatile uint8_t dummy1[3]; /* */ -} r_io_cpg_from_syscr1_t; - - -typedef struct st_cpg_from_stbcr3 -{ - - volatile uint8_t STBCR3; /* STBCR3 */ - volatile uint8_t dummy1[3]; /* */ -} r_io_cpg_from_stbcr3_t; - - -typedef struct st_cpg_from_swrstcr1 -{ - - volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ - volatile uint8_t dummy1[3]; /* */ -} r_io_cpg_from_swrstcr1_t; - - -/* Channel array defines of CPG (2)*/ -#ifdef DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS -volatile struct st_cpg_from_swrstcr1* CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */ - -#ifdef DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS -volatile struct st_cpg_from_stbcr3* CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */ - -#ifdef DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS -volatile struct st_cpg_from_syscr1* CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */ -/* End of channel array defines of CPG (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h deleted file mode 100644 index dd2abd5e75c..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h +++ /dev/null @@ -1,112 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : disc_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef DISC_IODEFINE_H -#define DISC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ -#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ - - -/* Start of channel array defines of DISC */ - -/* Channel array defines of DISC */ -/*(Sample) value = DISC[ channel ]->DOCMCR; */ -#define DISC_COUNT (2) -#define DISC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DISC0, &DISC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of DISC */ - - -#define DISC0DOCMCR (DISC0.DOCMCR) -#define DISC0DOCMSTR (DISC0.DOCMSTR) -#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR) -#define DISC0DOCMIENR (DISC0.DOCMIENR) -#define DISC0DOCMPMR (DISC0.DOCMPMR) -#define DISC0DOCMECRCR (DISC0.DOCMECRCR) -#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR) -#define DISC0DOCMSPXR (DISC0.DOCMSPXR) -#define DISC0DOCMSPYR (DISC0.DOCMSPYR) -#define DISC0DOCMSZXR (DISC0.DOCMSZXR) -#define DISC0DOCMSZYR (DISC0.DOCMSZYR) -#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR) -#define DISC1DOCMCR (DISC1.DOCMCR) -#define DISC1DOCMSTR (DISC1.DOCMSTR) -#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR) -#define DISC1DOCMIENR (DISC1.DOCMIENR) -#define DISC1DOCMPMR (DISC1.DOCMPMR) -#define DISC1DOCMECRCR (DISC1.DOCMECRCR) -#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR) -#define DISC1DOCMSPXR (DISC1.DOCMSPXR) -#define DISC1DOCMSPYR (DISC1.DOCMSPYR) -#define DISC1DOCMSZXR (DISC1.DOCMSZXR) -#define DISC1DOCMSZYR (DISC1.DOCMSZYR) -#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR) - - -typedef struct st_disc -{ - /* DISC */ - volatile uint32_t DOCMCR; /* DOCMCR */ - volatile uint32_t DOCMSTR; /* DOCMSTR */ - volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */ - volatile uint32_t DOCMIENR; /* DOCMIENR */ - volatile uint8_t dummy1[4]; /* */ - volatile uint32_t DOCMPMR; /* DOCMPMR */ - volatile uint32_t DOCMECRCR; /* DOCMECRCR */ - volatile uint32_t DOCMCCRCR; /* DOCMCCRCR */ - volatile uint32_t DOCMSPXR; /* DOCMSPXR */ - volatile uint32_t DOCMSPYR; /* DOCMSPYR */ - volatile uint32_t DOCMSZXR; /* DOCMSZXR */ - volatile uint32_t DOCMSZYR; /* DOCMSZYR */ - volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */ -} r_io_disc_t; - - -/* Channel array defines of DISC (2)*/ -#ifdef DECLARE_DISC_CHANNELS -volatile struct st_disc* DISC[ DISC_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - DISC_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_DISC_CHANNELS */ -/* End of channel array defines of DISC (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h deleted file mode 100644 index a6d6865f866..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h +++ /dev/null @@ -1,807 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : dmac_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef DMAC_IODEFINE_H -#define DMAC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - - - -/* Channel array defines of DMACmm */ -#define DMACmm_COUNT (8) -#define DMACmm_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ -#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ -#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ -#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ -#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ -#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ -#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ -#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ - - -/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ -#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */ - - -/* Start of channel array defines of DMAC */ - -/* Channel array defines of DMACn */ -/*(Sample) value = DMACn[ channel ]->N0SA_n; */ -#define DMACn_COUNT (16) -#define DMACn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \ - &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */ -#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */ -#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */ -#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */ -#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */ -#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */ -#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */ -#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */ -#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */ -#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */ -#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */ -#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */ -#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */ -#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */ -#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */ -#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */ - - -/* Channel array defines of DMACnn */ -/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */ -#define DMACnn_COUNT (2) -#define DMACnn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DMAC07, &DMAC815 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */ -#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */ - -/* End of channel array defines of DMAC */ - - -#define DMACN0SA_0 (DMAC.N0SA_0) -#define DMACN0DA_0 (DMAC.N0DA_0) -#define DMACN0TB_0 (DMAC.N0TB_0) -#define DMACN1SA_0 (DMAC.N1SA_0) -#define DMACN1DA_0 (DMAC.N1DA_0) -#define DMACN1TB_0 (DMAC.N1TB_0) -#define DMACCRSA_0 (DMAC.CRSA_0) -#define DMACCRDA_0 (DMAC.CRDA_0) -#define DMACCRTB_0 (DMAC.CRTB_0) -#define DMACCHSTAT_0 (DMAC.CHSTAT_0) -#define DMACCHCTRL_0 (DMAC.CHCTRL_0) -#define DMACCHCFG_0 (DMAC.CHCFG_0) -#define DMACCHITVL_0 (DMAC.CHITVL_0) -#define DMACCHEXT_0 (DMAC.CHEXT_0) -#define DMACNXLA_0 (DMAC.NXLA_0) -#define DMACCRLA_0 (DMAC.CRLA_0) -#define DMACN0SA_1 (DMAC.N0SA_1) -#define DMACN0DA_1 (DMAC.N0DA_1) -#define DMACN0TB_1 (DMAC.N0TB_1) -#define DMACN1SA_1 (DMAC.N1SA_1) -#define DMACN1DA_1 (DMAC.N1DA_1) -#define DMACN1TB_1 (DMAC.N1TB_1) -#define DMACCRSA_1 (DMAC.CRSA_1) -#define DMACCRDA_1 (DMAC.CRDA_1) -#define DMACCRTB_1 (DMAC.CRTB_1) -#define DMACCHSTAT_1 (DMAC.CHSTAT_1) -#define DMACCHCTRL_1 (DMAC.CHCTRL_1) -#define DMACCHCFG_1 (DMAC.CHCFG_1) -#define DMACCHITVL_1 (DMAC.CHITVL_1) -#define DMACCHEXT_1 (DMAC.CHEXT_1) -#define DMACNXLA_1 (DMAC.NXLA_1) -#define DMACCRLA_1 (DMAC.CRLA_1) -#define DMACN0SA_2 (DMAC.N0SA_2) -#define DMACN0DA_2 (DMAC.N0DA_2) -#define DMACN0TB_2 (DMAC.N0TB_2) -#define DMACN1SA_2 (DMAC.N1SA_2) -#define DMACN1DA_2 (DMAC.N1DA_2) -#define DMACN1TB_2 (DMAC.N1TB_2) -#define DMACCRSA_2 (DMAC.CRSA_2) -#define DMACCRDA_2 (DMAC.CRDA_2) -#define DMACCRTB_2 (DMAC.CRTB_2) -#define DMACCHSTAT_2 (DMAC.CHSTAT_2) -#define DMACCHCTRL_2 (DMAC.CHCTRL_2) -#define DMACCHCFG_2 (DMAC.CHCFG_2) -#define DMACCHITVL_2 (DMAC.CHITVL_2) -#define DMACCHEXT_2 (DMAC.CHEXT_2) -#define DMACNXLA_2 (DMAC.NXLA_2) -#define DMACCRLA_2 (DMAC.CRLA_2) -#define DMACN0SA_3 (DMAC.N0SA_3) -#define DMACN0DA_3 (DMAC.N0DA_3) -#define DMACN0TB_3 (DMAC.N0TB_3) -#define DMACN1SA_3 (DMAC.N1SA_3) -#define DMACN1DA_3 (DMAC.N1DA_3) -#define DMACN1TB_3 (DMAC.N1TB_3) -#define DMACCRSA_3 (DMAC.CRSA_3) -#define DMACCRDA_3 (DMAC.CRDA_3) -#define DMACCRTB_3 (DMAC.CRTB_3) -#define DMACCHSTAT_3 (DMAC.CHSTAT_3) -#define DMACCHCTRL_3 (DMAC.CHCTRL_3) -#define DMACCHCFG_3 (DMAC.CHCFG_3) -#define DMACCHITVL_3 (DMAC.CHITVL_3) -#define DMACCHEXT_3 (DMAC.CHEXT_3) -#define DMACNXLA_3 (DMAC.NXLA_3) -#define DMACCRLA_3 (DMAC.CRLA_3) -#define DMACN0SA_4 (DMAC.N0SA_4) -#define DMACN0DA_4 (DMAC.N0DA_4) -#define DMACN0TB_4 (DMAC.N0TB_4) -#define DMACN1SA_4 (DMAC.N1SA_4) -#define DMACN1DA_4 (DMAC.N1DA_4) -#define DMACN1TB_4 (DMAC.N1TB_4) -#define DMACCRSA_4 (DMAC.CRSA_4) -#define DMACCRDA_4 (DMAC.CRDA_4) -#define DMACCRTB_4 (DMAC.CRTB_4) -#define DMACCHSTAT_4 (DMAC.CHSTAT_4) -#define DMACCHCTRL_4 (DMAC.CHCTRL_4) -#define DMACCHCFG_4 (DMAC.CHCFG_4) -#define DMACCHITVL_4 (DMAC.CHITVL_4) -#define DMACCHEXT_4 (DMAC.CHEXT_4) -#define DMACNXLA_4 (DMAC.NXLA_4) -#define DMACCRLA_4 (DMAC.CRLA_4) -#define DMACN0SA_5 (DMAC.N0SA_5) -#define DMACN0DA_5 (DMAC.N0DA_5) -#define DMACN0TB_5 (DMAC.N0TB_5) -#define DMACN1SA_5 (DMAC.N1SA_5) -#define DMACN1DA_5 (DMAC.N1DA_5) -#define DMACN1TB_5 (DMAC.N1TB_5) -#define DMACCRSA_5 (DMAC.CRSA_5) -#define DMACCRDA_5 (DMAC.CRDA_5) -#define DMACCRTB_5 (DMAC.CRTB_5) -#define DMACCHSTAT_5 (DMAC.CHSTAT_5) -#define DMACCHCTRL_5 (DMAC.CHCTRL_5) -#define DMACCHCFG_5 (DMAC.CHCFG_5) -#define DMACCHITVL_5 (DMAC.CHITVL_5) -#define DMACCHEXT_5 (DMAC.CHEXT_5) -#define DMACNXLA_5 (DMAC.NXLA_5) -#define DMACCRLA_5 (DMAC.CRLA_5) -#define DMACN0SA_6 (DMAC.N0SA_6) -#define DMACN0DA_6 (DMAC.N0DA_6) -#define DMACN0TB_6 (DMAC.N0TB_6) -#define DMACN1SA_6 (DMAC.N1SA_6) -#define DMACN1DA_6 (DMAC.N1DA_6) -#define DMACN1TB_6 (DMAC.N1TB_6) -#define DMACCRSA_6 (DMAC.CRSA_6) -#define DMACCRDA_6 (DMAC.CRDA_6) -#define DMACCRTB_6 (DMAC.CRTB_6) -#define DMACCHSTAT_6 (DMAC.CHSTAT_6) -#define DMACCHCTRL_6 (DMAC.CHCTRL_6) -#define DMACCHCFG_6 (DMAC.CHCFG_6) -#define DMACCHITVL_6 (DMAC.CHITVL_6) -#define DMACCHEXT_6 (DMAC.CHEXT_6) -#define DMACNXLA_6 (DMAC.NXLA_6) -#define DMACCRLA_6 (DMAC.CRLA_6) -#define DMACN0SA_7 (DMAC.N0SA_7) -#define DMACN0DA_7 (DMAC.N0DA_7) -#define DMACN0TB_7 (DMAC.N0TB_7) -#define DMACN1SA_7 (DMAC.N1SA_7) -#define DMACN1DA_7 (DMAC.N1DA_7) -#define DMACN1TB_7 (DMAC.N1TB_7) -#define DMACCRSA_7 (DMAC.CRSA_7) -#define DMACCRDA_7 (DMAC.CRDA_7) -#define DMACCRTB_7 (DMAC.CRTB_7) -#define DMACCHSTAT_7 (DMAC.CHSTAT_7) -#define DMACCHCTRL_7 (DMAC.CHCTRL_7) -#define DMACCHCFG_7 (DMAC.CHCFG_7) -#define DMACCHITVL_7 (DMAC.CHITVL_7) -#define DMACCHEXT_7 (DMAC.CHEXT_7) -#define DMACNXLA_7 (DMAC.NXLA_7) -#define DMACCRLA_7 (DMAC.CRLA_7) -#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7) -#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7) -#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7) -#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7) -#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7) -#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7) -#define DMACN0SA_8 (DMAC.N0SA_8) -#define DMACN0DA_8 (DMAC.N0DA_8) -#define DMACN0TB_8 (DMAC.N0TB_8) -#define DMACN1SA_8 (DMAC.N1SA_8) -#define DMACN1DA_8 (DMAC.N1DA_8) -#define DMACN1TB_8 (DMAC.N1TB_8) -#define DMACCRSA_8 (DMAC.CRSA_8) -#define DMACCRDA_8 (DMAC.CRDA_8) -#define DMACCRTB_8 (DMAC.CRTB_8) -#define DMACCHSTAT_8 (DMAC.CHSTAT_8) -#define DMACCHCTRL_8 (DMAC.CHCTRL_8) -#define DMACCHCFG_8 (DMAC.CHCFG_8) -#define DMACCHITVL_8 (DMAC.CHITVL_8) -#define DMACCHEXT_8 (DMAC.CHEXT_8) -#define DMACNXLA_8 (DMAC.NXLA_8) -#define DMACCRLA_8 (DMAC.CRLA_8) -#define DMACN0SA_9 (DMAC.N0SA_9) -#define DMACN0DA_9 (DMAC.N0DA_9) -#define DMACN0TB_9 (DMAC.N0TB_9) -#define DMACN1SA_9 (DMAC.N1SA_9) -#define DMACN1DA_9 (DMAC.N1DA_9) -#define DMACN1TB_9 (DMAC.N1TB_9) -#define DMACCRSA_9 (DMAC.CRSA_9) -#define DMACCRDA_9 (DMAC.CRDA_9) -#define DMACCRTB_9 (DMAC.CRTB_9) -#define DMACCHSTAT_9 (DMAC.CHSTAT_9) -#define DMACCHCTRL_9 (DMAC.CHCTRL_9) -#define DMACCHCFG_9 (DMAC.CHCFG_9) -#define DMACCHITVL_9 (DMAC.CHITVL_9) -#define DMACCHEXT_9 (DMAC.CHEXT_9) -#define DMACNXLA_9 (DMAC.NXLA_9) -#define DMACCRLA_9 (DMAC.CRLA_9) -#define DMACN0SA_10 (DMAC.N0SA_10) -#define DMACN0DA_10 (DMAC.N0DA_10) -#define DMACN0TB_10 (DMAC.N0TB_10) -#define DMACN1SA_10 (DMAC.N1SA_10) -#define DMACN1DA_10 (DMAC.N1DA_10) -#define DMACN1TB_10 (DMAC.N1TB_10) -#define DMACCRSA_10 (DMAC.CRSA_10) -#define DMACCRDA_10 (DMAC.CRDA_10) -#define DMACCRTB_10 (DMAC.CRTB_10) -#define DMACCHSTAT_10 (DMAC.CHSTAT_10) -#define DMACCHCTRL_10 (DMAC.CHCTRL_10) -#define DMACCHCFG_10 (DMAC.CHCFG_10) -#define DMACCHITVL_10 (DMAC.CHITVL_10) -#define DMACCHEXT_10 (DMAC.CHEXT_10) -#define DMACNXLA_10 (DMAC.NXLA_10) -#define DMACCRLA_10 (DMAC.CRLA_10) -#define DMACN0SA_11 (DMAC.N0SA_11) -#define DMACN0DA_11 (DMAC.N0DA_11) -#define DMACN0TB_11 (DMAC.N0TB_11) -#define DMACN1SA_11 (DMAC.N1SA_11) -#define DMACN1DA_11 (DMAC.N1DA_11) -#define DMACN1TB_11 (DMAC.N1TB_11) -#define DMACCRSA_11 (DMAC.CRSA_11) -#define DMACCRDA_11 (DMAC.CRDA_11) -#define DMACCRTB_11 (DMAC.CRTB_11) -#define DMACCHSTAT_11 (DMAC.CHSTAT_11) -#define DMACCHCTRL_11 (DMAC.CHCTRL_11) -#define DMACCHCFG_11 (DMAC.CHCFG_11) -#define DMACCHITVL_11 (DMAC.CHITVL_11) -#define DMACCHEXT_11 (DMAC.CHEXT_11) -#define DMACNXLA_11 (DMAC.NXLA_11) -#define DMACCRLA_11 (DMAC.CRLA_11) -#define DMACN0SA_12 (DMAC.N0SA_12) -#define DMACN0DA_12 (DMAC.N0DA_12) -#define DMACN0TB_12 (DMAC.N0TB_12) -#define DMACN1SA_12 (DMAC.N1SA_12) -#define DMACN1DA_12 (DMAC.N1DA_12) -#define DMACN1TB_12 (DMAC.N1TB_12) -#define DMACCRSA_12 (DMAC.CRSA_12) -#define DMACCRDA_12 (DMAC.CRDA_12) -#define DMACCRTB_12 (DMAC.CRTB_12) -#define DMACCHSTAT_12 (DMAC.CHSTAT_12) -#define DMACCHCTRL_12 (DMAC.CHCTRL_12) -#define DMACCHCFG_12 (DMAC.CHCFG_12) -#define DMACCHITVL_12 (DMAC.CHITVL_12) -#define DMACCHEXT_12 (DMAC.CHEXT_12) -#define DMACNXLA_12 (DMAC.NXLA_12) -#define DMACCRLA_12 (DMAC.CRLA_12) -#define DMACN0SA_13 (DMAC.N0SA_13) -#define DMACN0DA_13 (DMAC.N0DA_13) -#define DMACN0TB_13 (DMAC.N0TB_13) -#define DMACN1SA_13 (DMAC.N1SA_13) -#define DMACN1DA_13 (DMAC.N1DA_13) -#define DMACN1TB_13 (DMAC.N1TB_13) -#define DMACCRSA_13 (DMAC.CRSA_13) -#define DMACCRDA_13 (DMAC.CRDA_13) -#define DMACCRTB_13 (DMAC.CRTB_13) -#define DMACCHSTAT_13 (DMAC.CHSTAT_13) -#define DMACCHCTRL_13 (DMAC.CHCTRL_13) -#define DMACCHCFG_13 (DMAC.CHCFG_13) -#define DMACCHITVL_13 (DMAC.CHITVL_13) -#define DMACCHEXT_13 (DMAC.CHEXT_13) -#define DMACNXLA_13 (DMAC.NXLA_13) -#define DMACCRLA_13 (DMAC.CRLA_13) -#define DMACN0SA_14 (DMAC.N0SA_14) -#define DMACN0DA_14 (DMAC.N0DA_14) -#define DMACN0TB_14 (DMAC.N0TB_14) -#define DMACN1SA_14 (DMAC.N1SA_14) -#define DMACN1DA_14 (DMAC.N1DA_14) -#define DMACN1TB_14 (DMAC.N1TB_14) -#define DMACCRSA_14 (DMAC.CRSA_14) -#define DMACCRDA_14 (DMAC.CRDA_14) -#define DMACCRTB_14 (DMAC.CRTB_14) -#define DMACCHSTAT_14 (DMAC.CHSTAT_14) -#define DMACCHCTRL_14 (DMAC.CHCTRL_14) -#define DMACCHCFG_14 (DMAC.CHCFG_14) -#define DMACCHITVL_14 (DMAC.CHITVL_14) -#define DMACCHEXT_14 (DMAC.CHEXT_14) -#define DMACNXLA_14 (DMAC.NXLA_14) -#define DMACCRLA_14 (DMAC.CRLA_14) -#define DMACN0SA_15 (DMAC.N0SA_15) -#define DMACN0DA_15 (DMAC.N0DA_15) -#define DMACN0TB_15 (DMAC.N0TB_15) -#define DMACN1SA_15 (DMAC.N1SA_15) -#define DMACN1DA_15 (DMAC.N1DA_15) -#define DMACN1TB_15 (DMAC.N1TB_15) -#define DMACCRSA_15 (DMAC.CRSA_15) -#define DMACCRDA_15 (DMAC.CRDA_15) -#define DMACCRTB_15 (DMAC.CRTB_15) -#define DMACCHSTAT_15 (DMAC.CHSTAT_15) -#define DMACCHCTRL_15 (DMAC.CHCTRL_15) -#define DMACCHCFG_15 (DMAC.CHCFG_15) -#define DMACCHITVL_15 (DMAC.CHITVL_15) -#define DMACCHEXT_15 (DMAC.CHEXT_15) -#define DMACNXLA_15 (DMAC.NXLA_15) -#define DMACCRLA_15 (DMAC.CRLA_15) -#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15) -#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15) -#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15) -#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15) -#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15) -#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15) -#define DMACDMARS0 (DMAC.DMARS0) -#define DMACDMARS1 (DMAC.DMARS1) -#define DMACDMARS2 (DMAC.DMARS2) -#define DMACDMARS3 (DMAC.DMARS3) -#define DMACDMARS4 (DMAC.DMARS4) -#define DMACDMARS5 (DMAC.DMARS5) -#define DMACDMARS6 (DMAC.DMARS6) -#define DMACDMARS7 (DMAC.DMARS7) - - -typedef struct st_dmars_mm -{ - - volatile uint32_t DMARS; /* DMARS */ -} r_io_dmars_mm_t; - - -typedef struct st_dmac -{ - /* DMAC */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_0; /* N0SA_0 */ - volatile uint32_t N0DA_0; /* N0DA_0 */ - volatile uint32_t N0TB_0; /* N0TB_0 */ - volatile uint32_t N1SA_0; /* N1SA_0 */ - volatile uint32_t N1DA_0; /* N1DA_0 */ - volatile uint32_t N1TB_0; /* N1TB_0 */ - volatile uint32_t CRSA_0; /* CRSA_0 */ - volatile uint32_t CRDA_0; /* CRDA_0 */ - volatile uint32_t CRTB_0; /* CRTB_0 */ - volatile uint32_t CHSTAT_0; /* CHSTAT_0 */ - volatile uint32_t CHCTRL_0; /* CHCTRL_0 */ - volatile uint32_t CHCFG_0; /* CHCFG_0 */ - volatile uint32_t CHITVL_0; /* CHITVL_0 */ - volatile uint32_t CHEXT_0; /* CHEXT_0 */ - volatile uint32_t NXLA_0; /* NXLA_0 */ - volatile uint32_t CRLA_0; /* CRLA_0 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_1; /* N0SA_1 */ - volatile uint32_t N0DA_1; /* N0DA_1 */ - volatile uint32_t N0TB_1; /* N0TB_1 */ - volatile uint32_t N1SA_1; /* N1SA_1 */ - volatile uint32_t N1DA_1; /* N1DA_1 */ - volatile uint32_t N1TB_1; /* N1TB_1 */ - volatile uint32_t CRSA_1; /* CRSA_1 */ - volatile uint32_t CRDA_1; /* CRDA_1 */ - volatile uint32_t CRTB_1; /* CRTB_1 */ - volatile uint32_t CHSTAT_1; /* CHSTAT_1 */ - volatile uint32_t CHCTRL_1; /* CHCTRL_1 */ - volatile uint32_t CHCFG_1; /* CHCFG_1 */ - volatile uint32_t CHITVL_1; /* CHITVL_1 */ - volatile uint32_t CHEXT_1; /* CHEXT_1 */ - volatile uint32_t NXLA_1; /* NXLA_1 */ - volatile uint32_t CRLA_1; /* CRLA_1 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_2; /* N0SA_2 */ - volatile uint32_t N0DA_2; /* N0DA_2 */ - volatile uint32_t N0TB_2; /* N0TB_2 */ - volatile uint32_t N1SA_2; /* N1SA_2 */ - volatile uint32_t N1DA_2; /* N1DA_2 */ - volatile uint32_t N1TB_2; /* N1TB_2 */ - volatile uint32_t CRSA_2; /* CRSA_2 */ - volatile uint32_t CRDA_2; /* CRDA_2 */ - volatile uint32_t CRTB_2; /* CRTB_2 */ - volatile uint32_t CHSTAT_2; /* CHSTAT_2 */ - volatile uint32_t CHCTRL_2; /* CHCTRL_2 */ - volatile uint32_t CHCFG_2; /* CHCFG_2 */ - volatile uint32_t CHITVL_2; /* CHITVL_2 */ - volatile uint32_t CHEXT_2; /* CHEXT_2 */ - volatile uint32_t NXLA_2; /* NXLA_2 */ - volatile uint32_t CRLA_2; /* CRLA_2 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_3; /* N0SA_3 */ - volatile uint32_t N0DA_3; /* N0DA_3 */ - volatile uint32_t N0TB_3; /* N0TB_3 */ - volatile uint32_t N1SA_3; /* N1SA_3 */ - volatile uint32_t N1DA_3; /* N1DA_3 */ - volatile uint32_t N1TB_3; /* N1TB_3 */ - volatile uint32_t CRSA_3; /* CRSA_3 */ - volatile uint32_t CRDA_3; /* CRDA_3 */ - volatile uint32_t CRTB_3; /* CRTB_3 */ - volatile uint32_t CHSTAT_3; /* CHSTAT_3 */ - volatile uint32_t CHCTRL_3; /* CHCTRL_3 */ - volatile uint32_t CHCFG_3; /* CHCFG_3 */ - volatile uint32_t CHITVL_3; /* CHITVL_3 */ - volatile uint32_t CHEXT_3; /* CHEXT_3 */ - volatile uint32_t NXLA_3; /* NXLA_3 */ - volatile uint32_t CRLA_3; /* CRLA_3 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_4; /* N0SA_4 */ - volatile uint32_t N0DA_4; /* N0DA_4 */ - volatile uint32_t N0TB_4; /* N0TB_4 */ - volatile uint32_t N1SA_4; /* N1SA_4 */ - volatile uint32_t N1DA_4; /* N1DA_4 */ - volatile uint32_t N1TB_4; /* N1TB_4 */ - volatile uint32_t CRSA_4; /* CRSA_4 */ - volatile uint32_t CRDA_4; /* CRDA_4 */ - volatile uint32_t CRTB_4; /* CRTB_4 */ - volatile uint32_t CHSTAT_4; /* CHSTAT_4 */ - volatile uint32_t CHCTRL_4; /* CHCTRL_4 */ - volatile uint32_t CHCFG_4; /* CHCFG_4 */ - volatile uint32_t CHITVL_4; /* CHITVL_4 */ - volatile uint32_t CHEXT_4; /* CHEXT_4 */ - volatile uint32_t NXLA_4; /* NXLA_4 */ - volatile uint32_t CRLA_4; /* CRLA_4 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_5; /* N0SA_5 */ - volatile uint32_t N0DA_5; /* N0DA_5 */ - volatile uint32_t N0TB_5; /* N0TB_5 */ - volatile uint32_t N1SA_5; /* N1SA_5 */ - volatile uint32_t N1DA_5; /* N1DA_5 */ - volatile uint32_t N1TB_5; /* N1TB_5 */ - volatile uint32_t CRSA_5; /* CRSA_5 */ - volatile uint32_t CRDA_5; /* CRDA_5 */ - volatile uint32_t CRTB_5; /* CRTB_5 */ - volatile uint32_t CHSTAT_5; /* CHSTAT_5 */ - volatile uint32_t CHCTRL_5; /* CHCTRL_5 */ - volatile uint32_t CHCFG_5; /* CHCFG_5 */ - volatile uint32_t CHITVL_5; /* CHITVL_5 */ - volatile uint32_t CHEXT_5; /* CHEXT_5 */ - volatile uint32_t NXLA_5; /* NXLA_5 */ - volatile uint32_t CRLA_5; /* CRLA_5 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_6; /* N0SA_6 */ - volatile uint32_t N0DA_6; /* N0DA_6 */ - volatile uint32_t N0TB_6; /* N0TB_6 */ - volatile uint32_t N1SA_6; /* N1SA_6 */ - volatile uint32_t N1DA_6; /* N1DA_6 */ - volatile uint32_t N1TB_6; /* N1TB_6 */ - volatile uint32_t CRSA_6; /* CRSA_6 */ - volatile uint32_t CRDA_6; /* CRDA_6 */ - volatile uint32_t CRTB_6; /* CRTB_6 */ - volatile uint32_t CHSTAT_6; /* CHSTAT_6 */ - volatile uint32_t CHCTRL_6; /* CHCTRL_6 */ - volatile uint32_t CHCFG_6; /* CHCFG_6 */ - volatile uint32_t CHITVL_6; /* CHITVL_6 */ - volatile uint32_t CHEXT_6; /* CHEXT_6 */ - volatile uint32_t NXLA_6; /* NXLA_6 */ - volatile uint32_t CRLA_6; /* CRLA_6 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_7; /* N0SA_7 */ - volatile uint32_t N0DA_7; /* N0DA_7 */ - volatile uint32_t N0TB_7; /* N0TB_7 */ - volatile uint32_t N1SA_7; /* N1SA_7 */ - volatile uint32_t N1DA_7; /* N1DA_7 */ - volatile uint32_t N1TB_7; /* N1TB_7 */ - volatile uint32_t CRSA_7; /* CRSA_7 */ - volatile uint32_t CRDA_7; /* CRDA_7 */ - volatile uint32_t CRTB_7; /* CRTB_7 */ - volatile uint32_t CHSTAT_7; /* CHSTAT_7 */ - volatile uint32_t CHCTRL_7; /* CHCTRL_7 */ - volatile uint32_t CHCFG_7; /* CHCFG_7 */ - volatile uint32_t CHITVL_7; /* CHITVL_7 */ - volatile uint32_t CHEXT_7; /* CHEXT_7 */ - volatile uint32_t NXLA_7; /* NXLA_7 */ - volatile uint32_t CRLA_7; /* CRLA_7 */ - -/* end of struct st_dmac_n */ - volatile uint8_t dummy187[256]; /* */ - -/* start of struct st_dmaccommon_n */ - volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ - volatile uint8_t dummy188[12]; /* */ - volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ - volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ - volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ - volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ - volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ - -/* end of struct st_dmaccommon_n */ - volatile uint8_t dummy189[220]; /* */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_8; /* N0SA_8 */ - volatile uint32_t N0DA_8; /* N0DA_8 */ - volatile uint32_t N0TB_8; /* N0TB_8 */ - volatile uint32_t N1SA_8; /* N1SA_8 */ - volatile uint32_t N1DA_8; /* N1DA_8 */ - volatile uint32_t N1TB_8; /* N1TB_8 */ - volatile uint32_t CRSA_8; /* CRSA_8 */ - volatile uint32_t CRDA_8; /* CRDA_8 */ - volatile uint32_t CRTB_8; /* CRTB_8 */ - volatile uint32_t CHSTAT_8; /* CHSTAT_8 */ - volatile uint32_t CHCTRL_8; /* CHCTRL_8 */ - volatile uint32_t CHCFG_8; /* CHCFG_8 */ - volatile uint32_t CHITVL_8; /* CHITVL_8 */ - volatile uint32_t CHEXT_8; /* CHEXT_8 */ - volatile uint32_t NXLA_8; /* NXLA_8 */ - volatile uint32_t CRLA_8; /* CRLA_8 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_9; /* N0SA_9 */ - volatile uint32_t N0DA_9; /* N0DA_9 */ - volatile uint32_t N0TB_9; /* N0TB_9 */ - volatile uint32_t N1SA_9; /* N1SA_9 */ - volatile uint32_t N1DA_9; /* N1DA_9 */ - volatile uint32_t N1TB_9; /* N1TB_9 */ - volatile uint32_t CRSA_9; /* CRSA_9 */ - volatile uint32_t CRDA_9; /* CRDA_9 */ - volatile uint32_t CRTB_9; /* CRTB_9 */ - volatile uint32_t CHSTAT_9; /* CHSTAT_9 */ - volatile uint32_t CHCTRL_9; /* CHCTRL_9 */ - volatile uint32_t CHCFG_9; /* CHCFG_9 */ - volatile uint32_t CHITVL_9; /* CHITVL_9 */ - volatile uint32_t CHEXT_9; /* CHEXT_9 */ - volatile uint32_t NXLA_9; /* NXLA_9 */ - volatile uint32_t CRLA_9; /* CRLA_9 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_10; /* N0SA_10 */ - volatile uint32_t N0DA_10; /* N0DA_10 */ - volatile uint32_t N0TB_10; /* N0TB_10 */ - volatile uint32_t N1SA_10; /* N1SA_10 */ - volatile uint32_t N1DA_10; /* N1DA_10 */ - volatile uint32_t N1TB_10; /* N1TB_10 */ - volatile uint32_t CRSA_10; /* CRSA_10 */ - volatile uint32_t CRDA_10; /* CRDA_10 */ - volatile uint32_t CRTB_10; /* CRTB_10 */ - volatile uint32_t CHSTAT_10; /* CHSTAT_10 */ - volatile uint32_t CHCTRL_10; /* CHCTRL_10 */ - volatile uint32_t CHCFG_10; /* CHCFG_10 */ - volatile uint32_t CHITVL_10; /* CHITVL_10 */ - volatile uint32_t CHEXT_10; /* CHEXT_10 */ - volatile uint32_t NXLA_10; /* NXLA_10 */ - volatile uint32_t CRLA_10; /* CRLA_10 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_11; /* N0SA_11 */ - volatile uint32_t N0DA_11; /* N0DA_11 */ - volatile uint32_t N0TB_11; /* N0TB_11 */ - volatile uint32_t N1SA_11; /* N1SA_11 */ - volatile uint32_t N1DA_11; /* N1DA_11 */ - volatile uint32_t N1TB_11; /* N1TB_11 */ - volatile uint32_t CRSA_11; /* CRSA_11 */ - volatile uint32_t CRDA_11; /* CRDA_11 */ - volatile uint32_t CRTB_11; /* CRTB_11 */ - volatile uint32_t CHSTAT_11; /* CHSTAT_11 */ - volatile uint32_t CHCTRL_11; /* CHCTRL_11 */ - volatile uint32_t CHCFG_11; /* CHCFG_11 */ - volatile uint32_t CHITVL_11; /* CHITVL_11 */ - volatile uint32_t CHEXT_11; /* CHEXT_11 */ - volatile uint32_t NXLA_11; /* NXLA_11 */ - volatile uint32_t CRLA_11; /* CRLA_11 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_12; /* N0SA_12 */ - volatile uint32_t N0DA_12; /* N0DA_12 */ - volatile uint32_t N0TB_12; /* N0TB_12 */ - volatile uint32_t N1SA_12; /* N1SA_12 */ - volatile uint32_t N1DA_12; /* N1DA_12 */ - volatile uint32_t N1TB_12; /* N1TB_12 */ - volatile uint32_t CRSA_12; /* CRSA_12 */ - volatile uint32_t CRDA_12; /* CRDA_12 */ - volatile uint32_t CRTB_12; /* CRTB_12 */ - volatile uint32_t CHSTAT_12; /* CHSTAT_12 */ - volatile uint32_t CHCTRL_12; /* CHCTRL_12 */ - volatile uint32_t CHCFG_12; /* CHCFG_12 */ - volatile uint32_t CHITVL_12; /* CHITVL_12 */ - volatile uint32_t CHEXT_12; /* CHEXT_12 */ - volatile uint32_t NXLA_12; /* NXLA_12 */ - volatile uint32_t CRLA_12; /* CRLA_12 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_13; /* N0SA_13 */ - volatile uint32_t N0DA_13; /* N0DA_13 */ - volatile uint32_t N0TB_13; /* N0TB_13 */ - volatile uint32_t N1SA_13; /* N1SA_13 */ - volatile uint32_t N1DA_13; /* N1DA_13 */ - volatile uint32_t N1TB_13; /* N1TB_13 */ - volatile uint32_t CRSA_13; /* CRSA_13 */ - volatile uint32_t CRDA_13; /* CRDA_13 */ - volatile uint32_t CRTB_13; /* CRTB_13 */ - volatile uint32_t CHSTAT_13; /* CHSTAT_13 */ - volatile uint32_t CHCTRL_13; /* CHCTRL_13 */ - volatile uint32_t CHCFG_13; /* CHCFG_13 */ - volatile uint32_t CHITVL_13; /* CHITVL_13 */ - volatile uint32_t CHEXT_13; /* CHEXT_13 */ - volatile uint32_t NXLA_13; /* NXLA_13 */ - volatile uint32_t CRLA_13; /* CRLA_13 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_14; /* N0SA_14 */ - volatile uint32_t N0DA_14; /* N0DA_14 */ - volatile uint32_t N0TB_14; /* N0TB_14 */ - volatile uint32_t N1SA_14; /* N1SA_14 */ - volatile uint32_t N1DA_14; /* N1DA_14 */ - volatile uint32_t N1TB_14; /* N1TB_14 */ - volatile uint32_t CRSA_14; /* CRSA_14 */ - volatile uint32_t CRDA_14; /* CRDA_14 */ - volatile uint32_t CRTB_14; /* CRTB_14 */ - volatile uint32_t CHSTAT_14; /* CHSTAT_14 */ - volatile uint32_t CHCTRL_14; /* CHCTRL_14 */ - volatile uint32_t CHCFG_14; /* CHCFG_14 */ - volatile uint32_t CHITVL_14; /* CHITVL_14 */ - volatile uint32_t CHEXT_14; /* CHEXT_14 */ - volatile uint32_t NXLA_14; /* NXLA_14 */ - volatile uint32_t CRLA_14; /* CRLA_14 */ - -/* end of struct st_dmac_n */ - -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_15; /* N0SA_15 */ - volatile uint32_t N0DA_15; /* N0DA_15 */ - volatile uint32_t N0TB_15; /* N0TB_15 */ - volatile uint32_t N1SA_15; /* N1SA_15 */ - volatile uint32_t N1DA_15; /* N1DA_15 */ - volatile uint32_t N1TB_15; /* N1TB_15 */ - volatile uint32_t CRSA_15; /* CRSA_15 */ - volatile uint32_t CRDA_15; /* CRDA_15 */ - volatile uint32_t CRTB_15; /* CRTB_15 */ - volatile uint32_t CHSTAT_15; /* CHSTAT_15 */ - volatile uint32_t CHCTRL_15; /* CHCTRL_15 */ - volatile uint32_t CHCFG_15; /* CHCFG_15 */ - volatile uint32_t CHITVL_15; /* CHITVL_15 */ - volatile uint32_t CHEXT_15; /* CHEXT_15 */ - volatile uint32_t NXLA_15; /* NXLA_15 */ - volatile uint32_t CRLA_15; /* CRLA_15 */ - -/* end of struct st_dmac_n */ - volatile uint8_t dummy190[256]; /* */ - -/* start of struct st_dmaccommon_n */ - volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ - volatile uint8_t dummy191[12]; /* */ - volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */ - volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */ - volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ - volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ - volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ - -/* end of struct st_dmaccommon_n */ - volatile uint8_t dummy192[350095580]; /* */ - volatile uint32_t DMARS0; /* DMARS0 */ - volatile uint32_t DMARS1; /* DMARS1 */ - volatile uint32_t DMARS2; /* DMARS2 */ - volatile uint32_t DMARS3; /* DMARS3 */ - volatile uint32_t DMARS4; /* DMARS4 */ - volatile uint32_t DMARS5; /* DMARS5 */ - volatile uint32_t DMARS6; /* DMARS6 */ - volatile uint32_t DMARS7; /* DMARS7 */ -} r_io_dmac_t; - - -typedef struct st_dmaccommon_n -{ - - volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ - volatile uint8_t dummy1[12]; /* */ - volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ - volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ - volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ - volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ - volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ -} r_io_dmaccommon_n_t; - - -typedef struct st_dmac_n -{ - - volatile uint32_t N0SA_n; /* N0SA_n */ - volatile uint32_t N0DA_n; /* N0DA_n */ - volatile uint32_t N0TB_n; /* N0TB_n */ - volatile uint32_t N1SA_n; /* N1SA_n */ - volatile uint32_t N1DA_n; /* N1DA_n */ - volatile uint32_t N1TB_n; /* N1TB_n */ - volatile uint32_t CRSA_n; /* CRSA_n */ - volatile uint32_t CRDA_n; /* CRDA_n */ - volatile uint32_t CRTB_n; /* CRTB_n */ - volatile uint32_t CHSTAT_n; /* CHSTAT_n */ - volatile uint32_t CHCTRL_n; /* CHCTRL_n */ - volatile uint32_t CHCFG_n; /* CHCFG_n */ - volatile uint32_t CHITVL_n; /* CHITVL_n */ - volatile uint32_t CHEXT_n; /* CHEXT_n */ - volatile uint32_t NXLA_n; /* NXLA_n */ - volatile uint32_t CRLA_n; /* CRLA_n */ -} r_io_dmac_n_t; - - -/* Channel array defines of DMAC (2)*/ -#ifdef DECLARE_DMACmm_CHANNELS -volatile struct st_dmars_mm* DMACmm[ DMACmm_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - DMACmm_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_DMACmm_CHANNELS */ - -#ifdef DECLARE_DMACn_CHANNELS -volatile struct st_dmac_n* DMACn[ DMACn_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - DMACn_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_DMACn_CHANNELS */ - -#ifdef DECLARE_DMACnn_CHANNELS -volatile struct st_dmaccommon_n* DMACnn[ DMACnn_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - DMACnn_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_DMACnn_CHANNELS */ -/* End of channel array defines of DMAC (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h deleted file mode 100644 index 54bd656227e..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h +++ /dev/null @@ -1,441 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : dvdec_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef DVDEC_IODEFINE_H -#define DVDEC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ -#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ - - -/* Start of channel array defines of DVDEC */ - -/* Channel array defines of DVDEC */ -/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ -#define DVDEC_COUNT (2) -#define DVDEC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DVDEC0, &DVDEC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of DVDEC */ - - -#define ADCCR1_1 (DVDEC1.ADCCR1) -#define TGCR1_1 (DVDEC1.TGCR1) -#define TGCR2_1 (DVDEC1.TGCR2) -#define TGCR3_1 (DVDEC1.TGCR3) -#define SYNSCR1_1 (DVDEC1.SYNSCR1) -#define SYNSCR2_1 (DVDEC1.SYNSCR2) -#define SYNSCR3_1 (DVDEC1.SYNSCR3) -#define SYNSCR4_1 (DVDEC1.SYNSCR4) -#define SYNSCR5_1 (DVDEC1.SYNSCR5) -#define HAFCCR1_1 (DVDEC1.HAFCCR1) -#define HAFCCR2_1 (DVDEC1.HAFCCR2) -#define HAFCCR3_1 (DVDEC1.HAFCCR3) -#define VCDWCR1_1 (DVDEC1.VCDWCR1) -#define DCPCR1_1 (DVDEC1.DCPCR1) -#define DCPCR2_1 (DVDEC1.DCPCR2) -#define DCPCR3_1 (DVDEC1.DCPCR3) -#define DCPCR4_1 (DVDEC1.DCPCR4) -#define DCPCR5_1 (DVDEC1.DCPCR5) -#define DCPCR6_1 (DVDEC1.DCPCR6) -#define DCPCR7_1 (DVDEC1.DCPCR7) -#define DCPCR8_1 (DVDEC1.DCPCR8) -#define NSDCR_1 (DVDEC1.NSDCR) -#define BTLCR_1 (DVDEC1.BTLCR) -#define BTGPCR_1 (DVDEC1.BTGPCR) -#define ACCCR1_1 (DVDEC1.ACCCR1) -#define ACCCR2_1 (DVDEC1.ACCCR2) -#define ACCCR3_1 (DVDEC1.ACCCR3) -#define TINTCR_1 (DVDEC1.TINTCR) -#define YCDCR_1 (DVDEC1.YCDCR) -#define AGCCR1_1 (DVDEC1.AGCCR1) -#define AGCCR2_1 (DVDEC1.AGCCR2) -#define PKLIMITCR_1 (DVDEC1.PKLIMITCR) -#define RGORCR1_1 (DVDEC1.RGORCR1) -#define RGORCR2_1 (DVDEC1.RGORCR2) -#define RGORCR3_1 (DVDEC1.RGORCR3) -#define RGORCR4_1 (DVDEC1.RGORCR4) -#define RGORCR5_1 (DVDEC1.RGORCR5) -#define RGORCR6_1 (DVDEC1.RGORCR6) -#define RGORCR7_1 (DVDEC1.RGORCR7) -#define AFCPFCR_1 (DVDEC1.AFCPFCR) -#define RUPDCR_1 (DVDEC1.RUPDCR) -#define VSYNCSR_1 (DVDEC1.VSYNCSR) -#define HSYNCSR_1 (DVDEC1.HSYNCSR) -#define DCPSR1_1 (DVDEC1.DCPSR1) -#define DCPSR2_1 (DVDEC1.DCPSR2) -#define NSDSR_1 (DVDEC1.NSDSR) -#define CROMASR1_1 (DVDEC1.CROMASR1) -#define CROMASR2_1 (DVDEC1.CROMASR2) -#define SYNCSSR_1 (DVDEC1.SYNCSSR) -#define AGCCSR1_1 (DVDEC1.AGCCSR1) -#define AGCCSR2_1 (DVDEC1.AGCCSR2) -#define YCSCR3_1 (DVDEC1.YCSCR3) -#define YCSCR4_1 (DVDEC1.YCSCR4) -#define YCSCR5_1 (DVDEC1.YCSCR5) -#define YCSCR6_1 (DVDEC1.YCSCR6) -#define YCSCR7_1 (DVDEC1.YCSCR7) -#define YCSCR8_1 (DVDEC1.YCSCR8) -#define YCSCR9_1 (DVDEC1.YCSCR9) -#define YCSCR11_1 (DVDEC1.YCSCR11) -#define YCSCR12_1 (DVDEC1.YCSCR12) -#define DCPCR9_1 (DVDEC1.DCPCR9) -#define YCTWA_F0_1 (DVDEC1.YCTWA_F0) -#define YCTWA_F1_1 (DVDEC1.YCTWA_F1) -#define YCTWA_F2_1 (DVDEC1.YCTWA_F2) -#define YCTWA_F3_1 (DVDEC1.YCTWA_F3) -#define YCTWA_F4_1 (DVDEC1.YCTWA_F4) -#define YCTWA_F5_1 (DVDEC1.YCTWA_F5) -#define YCTWA_F6_1 (DVDEC1.YCTWA_F6) -#define YCTWA_F7_1 (DVDEC1.YCTWA_F7) -#define YCTWA_F8_1 (DVDEC1.YCTWA_F8) -#define YCTWB_F0_1 (DVDEC1.YCTWB_F0) -#define YCTWB_F1_1 (DVDEC1.YCTWB_F1) -#define YCTWB_F2_1 (DVDEC1.YCTWB_F2) -#define YCTWB_F3_1 (DVDEC1.YCTWB_F3) -#define YCTWB_F4_1 (DVDEC1.YCTWB_F4) -#define YCTWB_F5_1 (DVDEC1.YCTWB_F5) -#define YCTWB_F6_1 (DVDEC1.YCTWB_F6) -#define YCTWB_F7_1 (DVDEC1.YCTWB_F7) -#define YCTWB_F8_1 (DVDEC1.YCTWB_F8) -#define YCTNA_F0_1 (DVDEC1.YCTNA_F0) -#define YCTNA_F1_1 (DVDEC1.YCTNA_F1) -#define YCTNA_F2_1 (DVDEC1.YCTNA_F2) -#define YCTNA_F3_1 (DVDEC1.YCTNA_F3) -#define YCTNA_F4_1 (DVDEC1.YCTNA_F4) -#define YCTNA_F5_1 (DVDEC1.YCTNA_F5) -#define YCTNA_F6_1 (DVDEC1.YCTNA_F6) -#define YCTNA_F7_1 (DVDEC1.YCTNA_F7) -#define YCTNA_F8_1 (DVDEC1.YCTNA_F8) -#define YCTNB_F0_1 (DVDEC1.YCTNB_F0) -#define YCTNB_F1_1 (DVDEC1.YCTNB_F1) -#define YCTNB_F2_1 (DVDEC1.YCTNB_F2) -#define YCTNB_F3_1 (DVDEC1.YCTNB_F3) -#define YCTNB_F4_1 (DVDEC1.YCTNB_F4) -#define YCTNB_F5_1 (DVDEC1.YCTNB_F5) -#define YCTNB_F6_1 (DVDEC1.YCTNB_F6) -#define YCTNB_F7_1 (DVDEC1.YCTNB_F7) -#define YCTNB_F8_1 (DVDEC1.YCTNB_F8) -#define YGAINCR_1 (DVDEC1.YGAINCR) -#define CBGAINCR_1 (DVDEC1.CBGAINCR) -#define CRGAINCR_1 (DVDEC1.CRGAINCR) -#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE) -#define PGACR_1 (DVDEC1.PGACR) -#define ADCCR2_1 (DVDEC1.ADCCR2) -#define ADCCR1_0 (DVDEC0.ADCCR1) -#define TGCR1_0 (DVDEC0.TGCR1) -#define TGCR2_0 (DVDEC0.TGCR2) -#define TGCR3_0 (DVDEC0.TGCR3) -#define SYNSCR1_0 (DVDEC0.SYNSCR1) -#define SYNSCR2_0 (DVDEC0.SYNSCR2) -#define SYNSCR3_0 (DVDEC0.SYNSCR3) -#define SYNSCR4_0 (DVDEC0.SYNSCR4) -#define SYNSCR5_0 (DVDEC0.SYNSCR5) -#define HAFCCR1_0 (DVDEC0.HAFCCR1) -#define HAFCCR2_0 (DVDEC0.HAFCCR2) -#define HAFCCR3_0 (DVDEC0.HAFCCR3) -#define VCDWCR1_0 (DVDEC0.VCDWCR1) -#define DCPCR1_0 (DVDEC0.DCPCR1) -#define DCPCR2_0 (DVDEC0.DCPCR2) -#define DCPCR3_0 (DVDEC0.DCPCR3) -#define DCPCR4_0 (DVDEC0.DCPCR4) -#define DCPCR5_0 (DVDEC0.DCPCR5) -#define DCPCR6_0 (DVDEC0.DCPCR6) -#define DCPCR7_0 (DVDEC0.DCPCR7) -#define DCPCR8_0 (DVDEC0.DCPCR8) -#define NSDCR_0 (DVDEC0.NSDCR) -#define BTLCR_0 (DVDEC0.BTLCR) -#define BTGPCR_0 (DVDEC0.BTGPCR) -#define ACCCR1_0 (DVDEC0.ACCCR1) -#define ACCCR2_0 (DVDEC0.ACCCR2) -#define ACCCR3_0 (DVDEC0.ACCCR3) -#define TINTCR_0 (DVDEC0.TINTCR) -#define YCDCR_0 (DVDEC0.YCDCR) -#define AGCCR1_0 (DVDEC0.AGCCR1) -#define AGCCR2_0 (DVDEC0.AGCCR2) -#define PKLIMITCR_0 (DVDEC0.PKLIMITCR) -#define RGORCR1_0 (DVDEC0.RGORCR1) -#define RGORCR2_0 (DVDEC0.RGORCR2) -#define RGORCR3_0 (DVDEC0.RGORCR3) -#define RGORCR4_0 (DVDEC0.RGORCR4) -#define RGORCR5_0 (DVDEC0.RGORCR5) -#define RGORCR6_0 (DVDEC0.RGORCR6) -#define RGORCR7_0 (DVDEC0.RGORCR7) -#define AFCPFCR_0 (DVDEC0.AFCPFCR) -#define RUPDCR_0 (DVDEC0.RUPDCR) -#define VSYNCSR_0 (DVDEC0.VSYNCSR) -#define HSYNCSR_0 (DVDEC0.HSYNCSR) -#define DCPSR1_0 (DVDEC0.DCPSR1) -#define DCPSR2_0 (DVDEC0.DCPSR2) -#define NSDSR_0 (DVDEC0.NSDSR) -#define CROMASR1_0 (DVDEC0.CROMASR1) -#define CROMASR2_0 (DVDEC0.CROMASR2) -#define SYNCSSR_0 (DVDEC0.SYNCSSR) -#define AGCCSR1_0 (DVDEC0.AGCCSR1) -#define AGCCSR2_0 (DVDEC0.AGCCSR2) -#define YCSCR3_0 (DVDEC0.YCSCR3) -#define YCSCR4_0 (DVDEC0.YCSCR4) -#define YCSCR5_0 (DVDEC0.YCSCR5) -#define YCSCR6_0 (DVDEC0.YCSCR6) -#define YCSCR7_0 (DVDEC0.YCSCR7) -#define YCSCR8_0 (DVDEC0.YCSCR8) -#define YCSCR9_0 (DVDEC0.YCSCR9) -#define YCSCR11_0 (DVDEC0.YCSCR11) -#define YCSCR12_0 (DVDEC0.YCSCR12) -#define DCPCR9_0 (DVDEC0.DCPCR9) -#define YCTWA_F0_0 (DVDEC0.YCTWA_F0) -#define YCTWA_F1_0 (DVDEC0.YCTWA_F1) -#define YCTWA_F2_0 (DVDEC0.YCTWA_F2) -#define YCTWA_F3_0 (DVDEC0.YCTWA_F3) -#define YCTWA_F4_0 (DVDEC0.YCTWA_F4) -#define YCTWA_F5_0 (DVDEC0.YCTWA_F5) -#define YCTWA_F6_0 (DVDEC0.YCTWA_F6) -#define YCTWA_F7_0 (DVDEC0.YCTWA_F7) -#define YCTWA_F8_0 (DVDEC0.YCTWA_F8) -#define YCTWB_F0_0 (DVDEC0.YCTWB_F0) -#define YCTWB_F1_0 (DVDEC0.YCTWB_F1) -#define YCTWB_F2_0 (DVDEC0.YCTWB_F2) -#define YCTWB_F3_0 (DVDEC0.YCTWB_F3) -#define YCTWB_F4_0 (DVDEC0.YCTWB_F4) -#define YCTWB_F5_0 (DVDEC0.YCTWB_F5) -#define YCTWB_F6_0 (DVDEC0.YCTWB_F6) -#define YCTWB_F7_0 (DVDEC0.YCTWB_F7) -#define YCTWB_F8_0 (DVDEC0.YCTWB_F8) -#define YCTNA_F0_0 (DVDEC0.YCTNA_F0) -#define YCTNA_F1_0 (DVDEC0.YCTNA_F1) -#define YCTNA_F2_0 (DVDEC0.YCTNA_F2) -#define YCTNA_F3_0 (DVDEC0.YCTNA_F3) -#define YCTNA_F4_0 (DVDEC0.YCTNA_F4) -#define YCTNA_F5_0 (DVDEC0.YCTNA_F5) -#define YCTNA_F6_0 (DVDEC0.YCTNA_F6) -#define YCTNA_F7_0 (DVDEC0.YCTNA_F7) -#define YCTNA_F8_0 (DVDEC0.YCTNA_F8) -#define YCTNB_F0_0 (DVDEC0.YCTNB_F0) -#define YCTNB_F1_0 (DVDEC0.YCTNB_F1) -#define YCTNB_F2_0 (DVDEC0.YCTNB_F2) -#define YCTNB_F3_0 (DVDEC0.YCTNB_F3) -#define YCTNB_F4_0 (DVDEC0.YCTNB_F4) -#define YCTNB_F5_0 (DVDEC0.YCTNB_F5) -#define YCTNB_F6_0 (DVDEC0.YCTNB_F6) -#define YCTNB_F7_0 (DVDEC0.YCTNB_F7) -#define YCTNB_F8_0 (DVDEC0.YCTNB_F8) -#define YGAINCR_0 (DVDEC0.YGAINCR) -#define CBGAINCR_0 (DVDEC0.CBGAINCR) -#define CRGAINCR_0 (DVDEC0.CRGAINCR) -#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE) -#define PGACR_0 (DVDEC0.PGACR) -#define ADCCR2_0 (DVDEC0.ADCCR2) - -#define DVDEC_TGCRn_COUNT (3) -#define DVDEC_SYNSCRn_COUNT (5) -#define DVDEC_HAFCCRn_COUNT (3) -#define DVDEC_DCPCRn_COUNT (8) -#define DVDEC_ACCCRn_COUNT (3) -#define DVDEC_AGCCRn_COUNT (2) -#define DVDEC_RGORCRn_COUNT (7) -#define DVDEC_DCPSRn_COUNT (2) -#define DVDEC_CROMASRn_COUNT (2) -#define DVDEC_AGCCSRn_COUNT (2) -#define DVDEC_YCSCRn_COUNT (7) -#define DVDEC_YCTWA_Fn_COUNT (9) -#define DVDEC_YCTWB_Fn_COUNT (9) -#define DVDEC_YCTNA_Fn_COUNT (9) -#define DVDEC_YCTNB_Fn_COUNT (9) - - -typedef struct st_dvdec -{ - /* DVDEC */ - volatile uint16_t ADCCR1; /* ADCCR1 */ - volatile uint8_t dummy1[4]; /* */ - -/* #define DVDEC_TGCRn_COUNT (3) */ - volatile uint16_t TGCR1; /* TGCR1 */ - volatile uint16_t TGCR2; /* TGCR2 */ - volatile uint16_t TGCR3; /* TGCR3 */ - volatile uint8_t dummy2[6]; /* */ - -/* #define DVDEC_SYNSCRn_COUNT (5) */ - volatile uint16_t SYNSCR1; /* SYNSCR1 */ - volatile uint16_t SYNSCR2; /* SYNSCR2 */ - volatile uint16_t SYNSCR3; /* SYNSCR3 */ - volatile uint16_t SYNSCR4; /* SYNSCR4 */ - volatile uint16_t SYNSCR5; /* SYNSCR5 */ - -/* #define DVDEC_HAFCCRn_COUNT (3) */ - volatile uint16_t HAFCCR1; /* HAFCCR1 */ - volatile uint16_t HAFCCR2; /* HAFCCR2 */ - volatile uint16_t HAFCCR3; /* HAFCCR3 */ - volatile uint16_t VCDWCR1; /* VCDWCR1 */ - volatile uint8_t dummy3[4]; /* */ - -/* #define DVDEC_DCPCRn_COUNT (8) */ - volatile uint16_t DCPCR1; /* DCPCR1 */ - volatile uint16_t DCPCR2; /* DCPCR2 */ - volatile uint16_t DCPCR3; /* DCPCR3 */ - volatile uint16_t DCPCR4; /* DCPCR4 */ - volatile uint16_t DCPCR5; /* DCPCR5 */ - volatile uint16_t DCPCR6; /* DCPCR6 */ - volatile uint16_t DCPCR7; /* DCPCR7 */ - volatile uint16_t DCPCR8; /* DCPCR8 */ - volatile uint16_t NSDCR; /* NSDCR */ - volatile uint16_t BTLCR; /* BTLCR */ - volatile uint16_t BTGPCR; /* BTGPCR */ - -/* #define DVDEC_ACCCRn_COUNT (3) */ - volatile uint16_t ACCCR1; /* ACCCR1 */ - volatile uint16_t ACCCR2; /* ACCCR2 */ - volatile uint16_t ACCCR3; /* ACCCR3 */ - volatile uint16_t TINTCR; /* TINTCR */ - volatile uint16_t YCDCR; /* YCDCR */ - -/* #define DVDEC_AGCCRn_COUNT (2) */ - volatile uint16_t AGCCR1; /* AGCCR1 */ - volatile uint16_t AGCCR2; /* AGCCR2 */ - volatile uint16_t PKLIMITCR; /* PKLIMITCR */ - -/* #define DVDEC_RGORCRn_COUNT (7) */ - volatile uint16_t RGORCR1; /* RGORCR1 */ - volatile uint16_t RGORCR2; /* RGORCR2 */ - volatile uint16_t RGORCR3; /* RGORCR3 */ - volatile uint16_t RGORCR4; /* RGORCR4 */ - volatile uint16_t RGORCR5; /* RGORCR5 */ - volatile uint16_t RGORCR6; /* RGORCR6 */ - volatile uint16_t RGORCR7; /* RGORCR7 */ - volatile uint8_t dummy4[24]; /* */ - volatile uint16_t AFCPFCR; /* AFCPFCR */ - volatile uint16_t RUPDCR; /* RUPDCR */ - volatile uint16_t VSYNCSR; /* VSYNCSR */ - volatile uint16_t HSYNCSR; /* HSYNCSR */ - -/* #define DVDEC_DCPSRn_COUNT (2) */ - volatile uint16_t DCPSR1; /* DCPSR1 */ - volatile uint16_t DCPSR2; /* DCPSR2 */ - volatile uint8_t dummy5[4]; /* */ - volatile uint16_t NSDSR; /* NSDSR */ - -/* #define DVDEC_CROMASRn_COUNT (2) */ - volatile uint16_t CROMASR1; /* CROMASR1 */ - volatile uint16_t CROMASR2; /* CROMASR2 */ - volatile uint16_t SYNCSSR; /* SYNCSSR */ - -/* #define DVDEC_AGCCSRn_COUNT (2) */ - volatile uint16_t AGCCSR1; /* AGCCSR1 */ - volatile uint16_t AGCCSR2; /* AGCCSR2 */ - volatile uint8_t dummy6[108]; /* */ - -/* #define DVDEC_YCSCRn_COUNT (7) */ - volatile uint16_t YCSCR3; /* YCSCR3 */ - volatile uint16_t YCSCR4; /* YCSCR4 */ - volatile uint16_t YCSCR5; /* YCSCR5 */ - volatile uint16_t YCSCR6; /* YCSCR6 */ - volatile uint16_t YCSCR7; /* YCSCR7 */ - volatile uint16_t YCSCR8; /* YCSCR8 */ - volatile uint16_t YCSCR9; /* YCSCR9 */ - volatile uint8_t dummy7[2]; /* */ - volatile uint16_t YCSCR11; /* YCSCR11 */ - volatile uint16_t YCSCR12; /* YCSCR12 */ - volatile uint8_t dummy8[104]; /* */ - volatile uint16_t DCPCR9; /* DCPCR9 */ - volatile uint8_t dummy9[16]; /* */ - -/* #define DVDEC_YCTWA_Fn_COUNT (9) */ - volatile uint16_t YCTWA_F0; /* YCTWA_F0 */ - volatile uint16_t YCTWA_F1; /* YCTWA_F1 */ - volatile uint16_t YCTWA_F2; /* YCTWA_F2 */ - volatile uint16_t YCTWA_F3; /* YCTWA_F3 */ - volatile uint16_t YCTWA_F4; /* YCTWA_F4 */ - volatile uint16_t YCTWA_F5; /* YCTWA_F5 */ - volatile uint16_t YCTWA_F6; /* YCTWA_F6 */ - volatile uint16_t YCTWA_F7; /* YCTWA_F7 */ - volatile uint16_t YCTWA_F8; /* YCTWA_F8 */ - -/* #define DVDEC_YCTWB_Fn_COUNT (9) */ - volatile uint16_t YCTWB_F0; /* YCTWB_F0 */ - volatile uint16_t YCTWB_F1; /* YCTWB_F1 */ - volatile uint16_t YCTWB_F2; /* YCTWB_F2 */ - volatile uint16_t YCTWB_F3; /* YCTWB_F3 */ - volatile uint16_t YCTWB_F4; /* YCTWB_F4 */ - volatile uint16_t YCTWB_F5; /* YCTWB_F5 */ - volatile uint16_t YCTWB_F6; /* YCTWB_F6 */ - volatile uint16_t YCTWB_F7; /* YCTWB_F7 */ - volatile uint16_t YCTWB_F8; /* YCTWB_F8 */ - -/* #define DVDEC_YCTNA_Fn_COUNT (9) */ - volatile uint16_t YCTNA_F0; /* YCTNA_F0 */ - volatile uint16_t YCTNA_F1; /* YCTNA_F1 */ - volatile uint16_t YCTNA_F2; /* YCTNA_F2 */ - volatile uint16_t YCTNA_F3; /* YCTNA_F3 */ - volatile uint16_t YCTNA_F4; /* YCTNA_F4 */ - volatile uint16_t YCTNA_F5; /* YCTNA_F5 */ - volatile uint16_t YCTNA_F6; /* YCTNA_F6 */ - volatile uint16_t YCTNA_F7; /* YCTNA_F7 */ - volatile uint16_t YCTNA_F8; /* YCTNA_F8 */ - -/* #define DVDEC_YCTNB_Fn_COUNT (9) */ - volatile uint16_t YCTNB_F0; /* YCTNB_F0 */ - volatile uint16_t YCTNB_F1; /* YCTNB_F1 */ - volatile uint16_t YCTNB_F2; /* YCTNB_F2 */ - volatile uint16_t YCTNB_F3; /* YCTNB_F3 */ - volatile uint16_t YCTNB_F4; /* YCTNB_F4 */ - volatile uint16_t YCTNB_F5; /* YCTNB_F5 */ - volatile uint16_t YCTNB_F6; /* YCTNB_F6 */ - volatile uint16_t YCTNB_F7; /* YCTNB_F7 */ - volatile uint16_t YCTNB_F8; /* YCTNB_F8 */ - volatile uint8_t dummy10[38]; /* */ - volatile uint16_t YGAINCR; /* YGAINCR */ - volatile uint16_t CBGAINCR; /* CBGAINCR */ - volatile uint16_t CRGAINCR; /* CRGAINCR */ - volatile uint8_t dummy11[122]; /* */ - volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */ - volatile uint16_t PGACR; /* PGACR */ - volatile uint16_t ADCCR2; /* ADCCR2 */ -} r_io_dvdec_t; - - -/* Channel array defines of DVDEC (2)*/ -#ifdef DECLARE_DVDEC_CHANNELS -volatile struct st_dvdec* DVDEC[ DVDEC_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - DVDEC_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_DVDEC_CHANNELS */ -/* End of channel array defines of DVDEC (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h deleted file mode 100644 index fef3000ff96..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h +++ /dev/null @@ -1,509 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : ether_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef ETHER_IODEFINE_H -#define ETHER_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ - - -/* Start of channel array defines of ETHER */ - -/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ -/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ -#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT (32) -#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ - ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ - ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ - ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ -#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ -#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ -#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ -#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ -#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ -#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ -#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ -#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ -#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ -#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ -#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ -#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ -#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ -#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ -#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ -#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ -#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ -#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ -#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ -#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ -#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ -#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ -#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ -#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ -#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ -#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ -#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ -#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ -#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ -#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ -#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ - -/* End of channel array defines of ETHER */ - - -#define ETHEREDSR0 (ETHER.EDSR0) -#define ETHERTDLAR0 (ETHER.TDLAR0) -#define ETHERTDFAR0 (ETHER.TDFAR0) -#define ETHERTDFXR0 (ETHER.TDFXR0) -#define ETHERTDFFR0 (ETHER.TDFFR0) -#define ETHERRDLAR0 (ETHER.RDLAR0) -#define ETHERRDFAR0 (ETHER.RDFAR0) -#define ETHERRDFXR0 (ETHER.RDFXR0) -#define ETHERRDFFR0 (ETHER.RDFFR0) -#define ETHEREDMR0 (ETHER.EDMR0) -#define ETHEREDTRR0 (ETHER.EDTRR0) -#define ETHEREDRRR0 (ETHER.EDRRR0) -#define ETHEREESR0 (ETHER.EESR0) -#define ETHEREESIPR0 (ETHER.EESIPR0) -#define ETHERTRSCER0 (ETHER.TRSCER0) -#define ETHERRMFCR0 (ETHER.RMFCR0) -#define ETHERTFTR0 (ETHER.TFTR0) -#define ETHERFDR0 (ETHER.FDR0) -#define ETHERRMCR0 (ETHER.RMCR0) -#define ETHERRPADIR0 (ETHER.RPADIR0) -#define ETHERFCFTR0 (ETHER.FCFTR0) -#define ETHERCSMR (ETHER.CSMR) -#define ETHERCSSBM (ETHER.CSSBM) -#define ETHERCSSMR (ETHER.CSSMR) -#define ETHERECMR0 (ETHER.ECMR0) -#define ETHERRFLR0 (ETHER.RFLR0) -#define ETHERECSR0 (ETHER.ECSR0) -#define ETHERECSIPR0 (ETHER.ECSIPR0) -#define ETHERPIR0 (ETHER.PIR0) -#define ETHERAPR0 (ETHER.APR0) -#define ETHERMPR0 (ETHER.MPR0) -#define ETHERPFTCR0 (ETHER.PFTCR0) -#define ETHERPFRCR0 (ETHER.PFRCR0) -#define ETHERTPAUSER0 (ETHER.TPAUSER0) -#define ETHERMAHR0 (ETHER.MAHR0) -#define ETHERMALR0 (ETHER.MALR0) -#define ETHERCEFCR0 (ETHER.CEFCR0) -#define ETHERFRECR0 (ETHER.FRECR0) -#define ETHERTSFRCR0 (ETHER.TSFRCR0) -#define ETHERTLFRCR0 (ETHER.TLFRCR0) -#define ETHERRFCR0 (ETHER.RFCR0) -#define ETHERMAFCR0 (ETHER.MAFCR0) -#define ETHERARSTR (ETHER.ARSTR) -#define ETHERTSU_CTRST (ETHER.TSU_CTRST) -#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0) -#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY) -#define ETHERTSU_TEN (ETHER.TSU_TEN) -#define ETHERTXNLCR0 (ETHER.TXNLCR0) -#define ETHERTXALCR0 (ETHER.TXALCR0) -#define ETHERRXNLCR0 (ETHER.RXNLCR0) -#define ETHERRXALCR0 (ETHER.RXALCR0) -#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0) -#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0) -#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1) -#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1) -#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2) -#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2) -#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3) -#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3) -#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4) -#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4) -#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5) -#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5) -#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6) -#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6) -#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7) -#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7) -#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8) -#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8) -#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9) -#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9) -#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10) -#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10) -#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11) -#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11) -#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12) -#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12) -#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13) -#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13) -#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14) -#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14) -#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15) -#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15) -#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16) -#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16) -#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17) -#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17) -#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18) -#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18) -#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19) -#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19) -#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20) -#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20) -#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21) -#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21) -#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22) -#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22) -#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23) -#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23) -#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24) -#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24) -#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25) -#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25) -#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26) -#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26) -#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27) -#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27) -#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28) -#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28) -#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29) -#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29) -#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30) -#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30) -#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31) -#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31) - - -typedef struct st_ether -{ - /* ETHER */ - volatile uint32_t EDSR0; /* EDSR0 */ - volatile uint8_t dummy207[12]; /* */ - volatile uint32_t TDLAR0; /* TDLAR0 */ - volatile uint32_t TDFAR0; /* TDFAR0 */ - volatile uint32_t TDFXR0; /* TDFXR0 */ - volatile uint32_t TDFFR0; /* TDFFR0 */ - volatile uint8_t dummy208[16]; /* */ - volatile uint32_t RDLAR0; /* RDLAR0 */ - volatile uint32_t RDFAR0; /* RDFAR0 */ - volatile uint32_t RDFXR0; /* RDFXR0 */ - volatile uint32_t RDFFR0; /* RDFFR0 */ - volatile uint8_t dummy209[960]; /* */ - volatile uint32_t EDMR0; /* EDMR0 */ - volatile uint8_t dummy210[4]; /* */ - volatile uint32_t EDTRR0; /* EDTRR0 */ - volatile uint8_t dummy211[4]; /* */ - volatile uint32_t EDRRR0; /* EDRRR0 */ - volatile uint8_t dummy212[20]; /* */ - volatile uint32_t EESR0; /* EESR0 */ - volatile uint8_t dummy213[4]; /* */ - volatile uint32_t EESIPR0; /* EESIPR0 */ - volatile uint8_t dummy214[4]; /* */ - volatile uint32_t TRSCER0; /* TRSCER0 */ - volatile uint8_t dummy215[4]; /* */ - volatile uint32_t RMFCR0; /* RMFCR0 */ - volatile uint8_t dummy216[4]; /* */ - volatile uint32_t TFTR0; /* TFTR0 */ - volatile uint8_t dummy217[4]; /* */ - volatile uint32_t FDR0; /* FDR0 */ - volatile uint8_t dummy218[4]; /* */ - volatile uint32_t RMCR0; /* RMCR0 */ - volatile uint8_t dummy219[4]; /* */ - volatile uint32_t RPADIR0; /* RPADIR0 */ - volatile uint8_t dummy220[4]; /* */ - volatile uint32_t FCFTR0; /* FCFTR0 */ - volatile uint8_t dummy221[120]; /* */ - volatile uint32_t CSMR; /* CSMR */ - volatile uint32_t CSSBM; /* CSSBM */ - volatile uint32_t CSSMR; /* CSSMR */ - volatile uint8_t dummy222[16]; /* */ - volatile uint32_t ECMR0; /* ECMR0 */ - volatile uint8_t dummy223[4]; /* */ - volatile uint32_t RFLR0; /* RFLR0 */ - volatile uint8_t dummy224[4]; /* */ - volatile uint32_t ECSR0; /* ECSR0 */ - volatile uint8_t dummy225[4]; /* */ - volatile uint32_t ECSIPR0; /* ECSIPR0 */ - volatile uint8_t dummy226[4]; /* */ - volatile uint32_t PIR0; /* PIR0 */ - volatile uint8_t dummy227[48]; /* */ - volatile uint32_t APR0; /* APR0 */ - volatile uint32_t MPR0; /* MPR0 */ - volatile uint32_t PFTCR0; /* PFTCR0 */ - volatile uint32_t PFRCR0; /* PFRCR0 */ - volatile uint32_t TPAUSER0; /* TPAUSER0 */ - volatile uint8_t dummy228[88]; /* */ - volatile uint32_t MAHR0; /* MAHR0 */ - volatile uint8_t dummy229[4]; /* */ - volatile uint32_t MALR0; /* MALR0 */ - volatile uint8_t dummy230[372]; /* */ - volatile uint32_t CEFCR0; /* CEFCR0 */ - volatile uint8_t dummy231[4]; /* */ - volatile uint32_t FRECR0; /* FRECR0 */ - volatile uint8_t dummy232[4]; /* */ - volatile uint32_t TSFRCR0; /* TSFRCR0 */ - volatile uint8_t dummy233[4]; /* */ - volatile uint32_t TLFRCR0; /* TLFRCR0 */ - volatile uint8_t dummy234[4]; /* */ - volatile uint32_t RFCR0; /* RFCR0 */ - volatile uint8_t dummy235[20]; /* */ - volatile uint32_t MAFCR0; /* MAFCR0 */ - volatile uint8_t dummy236[4228]; /* */ - volatile uint32_t ARSTR; /* ARSTR */ - volatile uint32_t TSU_CTRST; /* TSU_CTRST */ - volatile uint8_t dummy237[80]; /* */ - volatile uint32_t TSU_VTAG0; /* TSU_VTAG0 */ - volatile uint8_t dummy238[4]; /* */ - volatile uint32_t TSU_ADSBSY; /* TSU_ADSBSY */ - volatile uint32_t TSU_TEN; /* TSU_TEN */ - volatile uint8_t dummy239[24]; /* */ - volatile uint32_t TXNLCR0; /* TXNLCR0 */ - volatile uint32_t TXALCR0; /* TXALCR0 */ - volatile uint32_t RXNLCR0; /* RXNLCR0 */ - volatile uint32_t RXALCR0; /* RXALCR0 */ - volatile uint8_t dummy240[112]; /* */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ - volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */ - volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */ - volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */ - volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */ - volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */ - volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */ - volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */ - volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */ - volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */ - volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */ - volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */ - volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */ - volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */ - volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */ - volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */ - volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */ - volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */ - volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */ - volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */ - volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */ - volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */ - volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */ - volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */ - volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */ - volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */ - volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */ - volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */ - volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */ - volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */ - volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */ - volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */ - -/* end of struct st_ether_from_tsu_adrh0 */ - -/* start of struct st_ether_from_tsu_adrh0 */ - volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */ - volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */ - -/* end of struct st_ether_from_tsu_adrh0 */ -} r_io_ether_t; - - -typedef struct st_ether_from_tsu_adrh0 -{ - - volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ - volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ -} r_io_ether_from_tsu_adrh0_t; - - -/* Channel array defines of ETHER (2)*/ -#ifdef DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS -volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */ -/* End of channel array defines of ETHER (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h deleted file mode 100644 index 0e88e0cad28..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h +++ /dev/null @@ -1,78 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : flctl_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef FLCTL_IODEFINE_H -#define FLCTL_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ - - -#define FLCTLFLCMNCR (FLCTL.FLCMNCR) -#define FLCTLFLCMDCR (FLCTL.FLCMDCR) -#define FLCTLFLCMCDR (FLCTL.FLCMCDR) -#define FLCTLFLADR (FLCTL.FLADR) -#define FLCTLFLDATAR (FLCTL.FLDATAR) -#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR) -#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR) -#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR) -#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT) -#define FLCTLFLTRCR (FLCTL.FLTRCR) -#define FLCTLFLADR2 (FLCTL.FLADR2) -#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO) - - -typedef struct st_flctl -{ - /* FLCTL */ - volatile uint32_t FLCMNCR; /* FLCMNCR */ - volatile uint32_t FLCMDCR; /* FLCMDCR */ - volatile uint32_t FLCMCDR; /* FLCMCDR */ - volatile uint32_t FLADR; /* FLADR */ - volatile uint32_t FLDATAR; /* FLDATAR */ - volatile uint32_t FLDTCNTR; /* FLDTCNTR */ - volatile uint32_t FLINTDMACR; /* FLINTDMACR */ - volatile uint32_t FLBSYTMR; /* FLBSYTMR */ - volatile uint32_t FLBSYCNT; /* FLBSYCNT */ - volatile uint8_t dummy555[8]; /* */ - volatile uint8_t FLTRCR; /* FLTRCR */ - volatile uint8_t dummy556[15]; /* */ - volatile uint32_t FLADR2; /* FLADR2 */ - volatile uint8_t dummy557[16]; /* */ - volatile uint32_t FLDTFIFO; /* FLDTFIFO */ -} r_io_flctl_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h deleted file mode 100644 index 05c30ecdf54..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h +++ /dev/null @@ -1,1431 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : gpio_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef GPIO_IODEFINE_H -#define GPIO_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */ - - -/* Start of channel array defines of GPIO */ - -/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */ -/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */ -#define GPIO_FROM_PIPC1_ARRAY_COUNT (11) -#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \ - &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */ -#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */ -#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */ -#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */ -#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */ -#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */ -#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */ -#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */ -#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */ -#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */ -#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */ - - -/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */ -/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */ -#define GPIO_FROM_PBDC1_ARRAY_COUNT (11) -#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \ - &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */ -#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */ -#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */ -#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */ -#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */ -#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */ -#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */ -#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */ -#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */ -#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */ -#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */ - - -/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */ -/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */ -#define GPIO_FROM_PIBC1_ARRAY_COUNT (12) -#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \ - &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */ -#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */ -#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */ -#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */ -#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */ -#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */ -#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */ -#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */ -#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */ -#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */ -#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */ -#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */ - - -/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */ -/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */ -#define GPIO_FROM_PFCAE1_ARRAY_COUNT (11) -#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \ - &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */ -#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */ -#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */ -#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */ -#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */ -#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */ -#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */ -#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */ -#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */ -#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */ -#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */ - - -/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */ -/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */ -#define GPIO_FROM_PNOT1_ARRAY_COUNT (11) -#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \ - &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */ -#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */ -#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */ -#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */ -#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */ -#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */ -#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */ -#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */ -#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */ -#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */ -#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */ - - -/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */ -/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */ -#define GPIO_FROM_PFCE1_ARRAY_COUNT (11) -#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \ - &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */ -#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */ -#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */ -#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */ -#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */ -#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */ -#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */ -#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */ -#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */ -#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */ -#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */ - - -/* Channel array defines of GPIO_FROM_PFC1_ARRAY */ -/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */ -#define GPIO_FROM_PFC1_ARRAY_COUNT (11) -#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \ - &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */ -#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */ -#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */ -#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */ -#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */ -#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */ -#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */ -#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */ -#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */ -#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */ -#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */ - - -/* Channel array defines of GPIO_FROM_PMC0_ARRAY */ -/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */ -#define GPIO_FROM_PMC0_ARRAY_COUNT (12) -#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \ - &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */ -#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */ -#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */ -#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */ -#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */ -#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */ -#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */ -#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */ -#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */ -#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */ -#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */ -#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */ - - -/* Channel array defines of GPIO_FROM_PM1_ARRAY */ -/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */ -#define GPIO_FROM_PM1_ARRAY_COUNT (11) -#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \ - &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */ -#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */ -#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */ -#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */ -#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */ -#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */ -#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */ -#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */ -#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */ -#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10) /* GPIO_FROM_PM10 */ -#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */ - - -/* Channel array defines of GPIO_FROM_PPR0_ARRAY */ -/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */ -#define GPIO_FROM_PPR0_ARRAY_COUNT (12) -#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \ - &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */ -#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */ -#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */ -#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */ -#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */ -#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */ -#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */ -#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */ -#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */ -#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */ -#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */ -#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */ - - -/* Channel array defines of GPIO_FROM_P1_ARRAY */ -/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */ -#define GPIO_FROM_P1_ARRAY_COUNT (11) -#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \ - &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */ -#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */ -#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */ -#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */ -#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */ -#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */ -#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */ -#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */ -#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */ -#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */ -#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */ - -/* End of channel array defines of GPIO */ - - -#define GPIOP1 (GPIO.P1) -#define GPIOP2 (GPIO.P2) -#define GPIOP3 (GPIO.P3) -#define GPIOP4 (GPIO.P4) -#define GPIOP5 (GPIO.P5) -#define GPIOP6 (GPIO.P6) -#define GPIOP7 (GPIO.P7) -#define GPIOP8 (GPIO.P8) -#define GPIOP9 (GPIO.P9) -#define GPIOP10 (GPIO.P10) -#define GPIOP11 (GPIO.P11) -#define GPIOPSR1 (GPIO.PSR1) -#define GPIOPSR2 (GPIO.PSR2) -#define GPIOPSR3 (GPIO.PSR3) -#define GPIOPSR4 (GPIO.PSR4) -#define GPIOPSR5 (GPIO.PSR5) -#define GPIOPSR6 (GPIO.PSR6) -#define GPIOPSR7 (GPIO.PSR7) -#define GPIOPSR8 (GPIO.PSR8) -#define GPIOPSR9 (GPIO.PSR9) -#define GPIOPSR10 (GPIO.PSR10) -#define GPIOPSR11 (GPIO.PSR11) -#define GPIOPPR0 (GPIO.PPR0) -#define GPIOPPR1 (GPIO.PPR1) -#define GPIOPPR2 (GPIO.PPR2) -#define GPIOPPR3 (GPIO.PPR3) -#define GPIOPPR4 (GPIO.PPR4) -#define GPIOPPR5 (GPIO.PPR5) -#define GPIOPPR6 (GPIO.PPR6) -#define GPIOPPR7 (GPIO.PPR7) -#define GPIOPPR8 (GPIO.PPR8) -#define GPIOPPR9 (GPIO.PPR9) -#define GPIOPPR10 (GPIO.PPR10) -#define GPIOPPR11 (GPIO.PPR11) -#define GPIOPM1 (GPIO.PM1) -#define GPIOPM2 (GPIO.PM2) -#define GPIOPM3 (GPIO.PM3) -#define GPIOPM4 (GPIO.PM4) -#define GPIOPM5 (GPIO.PM5) -#define GPIOPM6 (GPIO.PM6) -#define GPIOPM7 (GPIO.PM7) -#define GPIOPM8 (GPIO.PM8) -#define GPIOPM9 (GPIO.PM9) -#define GPIOPM10 (GPIO.PM10) -#define GPIOPM11 (GPIO.PM11) -#define GPIOPMC0 (GPIO.PMC0) -#define GPIOPMC1 (GPIO.PMC1) -#define GPIOPMC2 (GPIO.PMC2) -#define GPIOPMC3 (GPIO.PMC3) -#define GPIOPMC4 (GPIO.PMC4) -#define GPIOPMC5 (GPIO.PMC5) -#define GPIOPMC6 (GPIO.PMC6) -#define GPIOPMC7 (GPIO.PMC7) -#define GPIOPMC8 (GPIO.PMC8) -#define GPIOPMC9 (GPIO.PMC9) -#define GPIOPMC10 (GPIO.PMC10) -#define GPIOPMC11 (GPIO.PMC11) -#define GPIOPFC1 (GPIO.PFC1) -#define GPIOPFC2 (GPIO.PFC2) -#define GPIOPFC3 (GPIO.PFC3) -#define GPIOPFC4 (GPIO.PFC4) -#define GPIOPFC5 (GPIO.PFC5) -#define GPIOPFC6 (GPIO.PFC6) -#define GPIOPFC7 (GPIO.PFC7) -#define GPIOPFC8 (GPIO.PFC8) -#define GPIOPFC9 (GPIO.PFC9) -#define GPIOPFC10 (GPIO.PFC10) -#define GPIOPFC11 (GPIO.PFC11) -#define GPIOPFCE1 (GPIO.PFCE1) -#define GPIOPFCE2 (GPIO.PFCE2) -#define GPIOPFCE3 (GPIO.PFCE3) -#define GPIOPFCE4 (GPIO.PFCE4) -#define GPIOPFCE5 (GPIO.PFCE5) -#define GPIOPFCE6 (GPIO.PFCE6) -#define GPIOPFCE7 (GPIO.PFCE7) -#define GPIOPFCE8 (GPIO.PFCE8) -#define GPIOPFCE9 (GPIO.PFCE9) -#define GPIOPFCE10 (GPIO.PFCE10) -#define GPIOPFCE11 (GPIO.PFCE11) -#define GPIOPNOT1 (GPIO.PNOT1) -#define GPIOPNOT2 (GPIO.PNOT2) -#define GPIOPNOT3 (GPIO.PNOT3) -#define GPIOPNOT4 (GPIO.PNOT4) -#define GPIOPNOT5 (GPIO.PNOT5) -#define GPIOPNOT6 (GPIO.PNOT6) -#define GPIOPNOT7 (GPIO.PNOT7) -#define GPIOPNOT8 (GPIO.PNOT8) -#define GPIOPNOT9 (GPIO.PNOT9) -#define GPIOPNOT10 (GPIO.PNOT10) -#define GPIOPNOT11 (GPIO.PNOT11) -#define GPIOPMSR1 (GPIO.PMSR1) -#define GPIOPMSR2 (GPIO.PMSR2) -#define GPIOPMSR3 (GPIO.PMSR3) -#define GPIOPMSR4 (GPIO.PMSR4) -#define GPIOPMSR5 (GPIO.PMSR5) -#define GPIOPMSR6 (GPIO.PMSR6) -#define GPIOPMSR7 (GPIO.PMSR7) -#define GPIOPMSR8 (GPIO.PMSR8) -#define GPIOPMSR9 (GPIO.PMSR9) -#define GPIOPMSR10 (GPIO.PMSR10) -#define GPIOPMSR11 (GPIO.PMSR11) -#define GPIOPMCSR0 (GPIO.PMCSR0) -#define GPIOPMCSR1 (GPIO.PMCSR1) -#define GPIOPMCSR2 (GPIO.PMCSR2) -#define GPIOPMCSR3 (GPIO.PMCSR3) -#define GPIOPMCSR4 (GPIO.PMCSR4) -#define GPIOPMCSR5 (GPIO.PMCSR5) -#define GPIOPMCSR6 (GPIO.PMCSR6) -#define GPIOPMCSR7 (GPIO.PMCSR7) -#define GPIOPMCSR8 (GPIO.PMCSR8) -#define GPIOPMCSR9 (GPIO.PMCSR9) -#define GPIOPMCSR10 (GPIO.PMCSR10) -#define GPIOPMCSR11 (GPIO.PMCSR11) -#define GPIOPFCAE1 (GPIO.PFCAE1) -#define GPIOPFCAE2 (GPIO.PFCAE2) -#define GPIOPFCAE3 (GPIO.PFCAE3) -#define GPIOPFCAE4 (GPIO.PFCAE4) -#define GPIOPFCAE5 (GPIO.PFCAE5) -#define GPIOPFCAE6 (GPIO.PFCAE6) -#define GPIOPFCAE7 (GPIO.PFCAE7) -#define GPIOPFCAE8 (GPIO.PFCAE8) -#define GPIOPFCAE9 (GPIO.PFCAE9) -#define GPIOPFCAE10 (GPIO.PFCAE10) -#define GPIOPFCAE11 (GPIO.PFCAE11) -#define GPIOSNCR (GPIO.SNCR) -#define GPIOPIBC0 (GPIO.PIBC0) -#define GPIOPIBC1 (GPIO.PIBC1) -#define GPIOPIBC2 (GPIO.PIBC2) -#define GPIOPIBC3 (GPIO.PIBC3) -#define GPIOPIBC4 (GPIO.PIBC4) -#define GPIOPIBC5 (GPIO.PIBC5) -#define GPIOPIBC6 (GPIO.PIBC6) -#define GPIOPIBC7 (GPIO.PIBC7) -#define GPIOPIBC8 (GPIO.PIBC8) -#define GPIOPIBC9 (GPIO.PIBC9) -#define GPIOPIBC10 (GPIO.PIBC10) -#define GPIOPIBC11 (GPIO.PIBC11) -#define GPIOPBDC1 (GPIO.PBDC1) -#define GPIOPBDC2 (GPIO.PBDC2) -#define GPIOPBDC3 (GPIO.PBDC3) -#define GPIOPBDC4 (GPIO.PBDC4) -#define GPIOPBDC5 (GPIO.PBDC5) -#define GPIOPBDC6 (GPIO.PBDC6) -#define GPIOPBDC7 (GPIO.PBDC7) -#define GPIOPBDC8 (GPIO.PBDC8) -#define GPIOPBDC9 (GPIO.PBDC9) -#define GPIOPBDC10 (GPIO.PBDC10) -#define GPIOPBDC11 (GPIO.PBDC11) -#define GPIOPIPC1 (GPIO.PIPC1) -#define GPIOPIPC2 (GPIO.PIPC2) -#define GPIOPIPC3 (GPIO.PIPC3) -#define GPIOPIPC4 (GPIO.PIPC4) -#define GPIOPIPC5 (GPIO.PIPC5) -#define GPIOPIPC6 (GPIO.PIPC6) -#define GPIOPIPC7 (GPIO.PIPC7) -#define GPIOPIPC8 (GPIO.PIPC8) -#define GPIOPIPC9 (GPIO.PIPC9) -#define GPIOPIPC10 (GPIO.PIPC10) -#define GPIOPIPC11 (GPIO.PIPC11) -#define GPIOJPPR0 (GPIO.JPPR0) -#define GPIOJPMC0 (GPIO.JPMC0) -#define GPIOJPMCSR0 (GPIO.JPMCSR0) -#define GPIOJPIBC0 (GPIO.JPIBC0) - -#define GPIO_PSRn_COUNT (11) -#define GPIO_PMSRn_COUNT (11) -#define GPIO_PMCSRn_COUNT (12) - - -typedef struct st_gpio -{ - /* GPIO */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P1; /* P1 */ - volatile uint8_t dummy348[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P2; /* P2 */ - volatile uint8_t dummy349[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P3; /* P3 */ - volatile uint8_t dummy350[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P4; /* P4 */ - volatile uint8_t dummy351[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P5; /* P5 */ - volatile uint8_t dummy352[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P6; /* P6 */ - volatile uint8_t dummy353[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P7; /* P7 */ - volatile uint8_t dummy354[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P8; /* P8 */ - volatile uint8_t dummy355[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P9; /* P9 */ - volatile uint8_t dummy356[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P10; /* P10 */ - volatile uint8_t dummy357[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P11; /* P11 */ - volatile uint8_t dummy3580[2]; /* */ - -/* end of struct st_gpio_from_p1 */ - volatile uint8_t dummy3581[212]; /* */ - -/* #define GPIO_PSRn_COUNT (11) */ - volatile uint32_t PSR1; /* PSR1 */ - volatile uint32_t PSR2; /* PSR2 */ - volatile uint32_t PSR3; /* PSR3 */ - volatile uint32_t PSR4; /* PSR4 */ - volatile uint32_t PSR5; /* PSR5 */ - volatile uint32_t PSR6; /* PSR6 */ - volatile uint32_t PSR7; /* PSR7 */ - volatile uint32_t PSR8; /* PSR8 */ - volatile uint32_t PSR9; /* PSR9 */ - volatile uint32_t PSR10; /* PSR10 */ - volatile uint32_t PSR11; /* PSR11 */ - volatile uint8_t dummy359[208]; /* */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR0; /* PPR0 */ - volatile uint8_t dummy360[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR1; /* PPR1 */ - volatile uint8_t dummy361[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR2; /* PPR2 */ - volatile uint8_t dummy362[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR3; /* PPR3 */ - volatile uint8_t dummy363[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR4; /* PPR4 */ - volatile uint8_t dummy364[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR5; /* PPR5 */ - volatile uint8_t dummy365[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR6; /* PPR6 */ - volatile uint8_t dummy366[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR7; /* PPR7 */ - volatile uint8_t dummy367[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR8; /* PPR8 */ - volatile uint8_t dummy368[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR9; /* PPR9 */ - volatile uint8_t dummy369[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR10; /* PPR10 */ - volatile uint8_t dummy370[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR11; /* PPR11 */ - volatile uint8_t dummy3710[2]; /* */ - -/* end of struct st_gpio_from_ppr0 */ - volatile uint8_t dummy3711[212]; /* */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM1; /* PM1 */ - volatile uint8_t dummy372[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM2; /* PM2 */ - volatile uint8_t dummy373[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM3; /* PM3 */ - volatile uint8_t dummy374[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM4; /* PM4 */ - volatile uint8_t dummy375[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM5; /* PM5 */ - volatile uint8_t dummy376[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM6; /* PM6 */ - volatile uint8_t dummy377[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM7; /* PM7 */ - volatile uint8_t dummy378[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM8; /* PM8 */ - volatile uint8_t dummy379[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM9; /* PM9 */ - volatile uint8_t dummy380[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM10; /* PM10 */ - volatile uint8_t dummy381[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM11; /* PM11 */ - volatile uint8_t dummy3820[2]; /* */ - -/* end of struct st_gpio_from_pm1 */ - volatile uint8_t dummy3821[208]; /* */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC0; /* PMC0 */ - volatile uint8_t dummy383[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC1; /* PMC1 */ - volatile uint8_t dummy384[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC2; /* PMC2 */ - volatile uint8_t dummy385[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC3; /* PMC3 */ - volatile uint8_t dummy386[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC4; /* PMC4 */ - volatile uint8_t dummy387[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC5; /* PMC5 */ - volatile uint8_t dummy388[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC6; /* PMC6 */ - volatile uint8_t dummy389[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC7; /* PMC7 */ - volatile uint8_t dummy390[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC8; /* PMC8 */ - volatile uint8_t dummy391[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC9; /* PMC9 */ - volatile uint8_t dummy392[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC10; /* PMC10 */ - volatile uint8_t dummy393[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC11; /* PMC11 */ - volatile uint8_t dummy3940[2]; /* */ - -/* end of struct st_gpio_from_pmc0 */ - volatile uint8_t dummy3941[212]; /* */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC1; /* PFC1 */ - volatile uint8_t dummy395[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC2; /* PFC2 */ - volatile uint8_t dummy396[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC3; /* PFC3 */ - volatile uint8_t dummy397[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC4; /* PFC4 */ - volatile uint8_t dummy398[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC5; /* PFC5 */ - volatile uint8_t dummy399[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC6; /* PFC6 */ - volatile uint8_t dummy400[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC7; /* PFC7 */ - volatile uint8_t dummy401[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC8; /* PFC8 */ - volatile uint8_t dummy402[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC9; /* PFC9 */ - volatile uint8_t dummy403[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC10; /* PFC10 */ - volatile uint8_t dummy404[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC11; /* PFC11 */ - volatile uint8_t dummy4050[2]; /* */ - -/* end of struct st_gpio_from_pfc1 */ - volatile uint8_t dummy4051[212]; /* */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE1; /* PFCE1 */ - volatile uint8_t dummy406[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE2; /* PFCE2 */ - volatile uint8_t dummy407[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE3; /* PFCE3 */ - volatile uint8_t dummy408[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE4; /* PFCE4 */ - volatile uint8_t dummy409[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE5; /* PFCE5 */ - volatile uint8_t dummy410[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE6; /* PFCE6 */ - volatile uint8_t dummy411[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE7; /* PFCE7 */ - volatile uint8_t dummy412[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE8; /* PFCE8 */ - volatile uint8_t dummy413[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE9; /* PFCE9 */ - volatile uint8_t dummy414[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE10; /* PFCE10 */ - volatile uint8_t dummy415[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE11; /* PFCE11 */ - volatile uint8_t dummy4160[2]; /* */ - -/* end of struct st_gpio_from_pfce1 */ - volatile uint8_t dummy4161[212]; /* */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT1; /* PNOT1 */ - volatile uint8_t dummy417[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT2; /* PNOT2 */ - volatile uint8_t dummy418[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT3; /* PNOT3 */ - volatile uint8_t dummy419[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT4; /* PNOT4 */ - volatile uint8_t dummy420[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT5; /* PNOT5 */ - volatile uint8_t dummy421[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT6; /* PNOT6 */ - volatile uint8_t dummy422[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT7; /* PNOT7 */ - volatile uint8_t dummy423[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT8; /* PNOT8 */ - volatile uint8_t dummy424[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT9; /* PNOT9 */ - volatile uint8_t dummy425[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT10; /* PNOT10 */ - volatile uint8_t dummy426[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT11; /* PNOT11 */ - volatile uint8_t dummy4270[2]; /* */ - -/* end of struct st_gpio_from_pnot1 */ - volatile uint8_t dummy4271[212]; /* */ - -/* #define GPIO_PMSRn_COUNT (11) */ - volatile uint32_t PMSR1; /* PMSR1 */ - volatile uint32_t PMSR2; /* PMSR2 */ - volatile uint32_t PMSR3; /* PMSR3 */ - volatile uint32_t PMSR4; /* PMSR4 */ - volatile uint32_t PMSR5; /* PMSR5 */ - volatile uint32_t PMSR6; /* PMSR6 */ - volatile uint32_t PMSR7; /* PMSR7 */ - volatile uint32_t PMSR8; /* PMSR8 */ - volatile uint32_t PMSR9; /* PMSR9 */ - volatile uint32_t PMSR10; /* PMSR10 */ - volatile uint32_t PMSR11; /* PMSR11 */ - volatile uint8_t dummy428[208]; /* */ - -/* #define GPIO_PMCSRn_COUNT (12) */ - volatile uint32_t PMCSR0; /* PMCSR0 */ - volatile uint32_t PMCSR1; /* PMCSR1 */ - volatile uint32_t PMCSR2; /* PMCSR2 */ - volatile uint32_t PMCSR3; /* PMCSR3 */ - volatile uint32_t PMCSR4; /* PMCSR4 */ - volatile uint32_t PMCSR5; /* PMCSR5 */ - volatile uint32_t PMCSR6; /* PMCSR6 */ - volatile uint32_t PMCSR7; /* PMCSR7 */ - volatile uint32_t PMCSR8; /* PMCSR8 */ - volatile uint32_t PMCSR9; /* PMCSR9 */ - volatile uint32_t PMCSR10; /* PMCSR10 */ - volatile uint32_t PMCSR11; /* PMCSR11 */ - volatile uint8_t dummy429[212]; /* */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE1; /* PFCAE1 */ - volatile uint8_t dummy430[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE2; /* PFCAE2 */ - volatile uint8_t dummy431[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE3; /* PFCAE3 */ - volatile uint8_t dummy432[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE4; /* PFCAE4 */ - volatile uint8_t dummy433[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE5; /* PFCAE5 */ - volatile uint8_t dummy434[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE6; /* PFCAE6 */ - volatile uint8_t dummy435[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE7; /* PFCAE7 */ - volatile uint8_t dummy436[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE8; /* PFCAE8 */ - volatile uint8_t dummy437[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE9; /* PFCAE9 */ - volatile uint8_t dummy438[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE10; /* PFCAE10 */ - volatile uint8_t dummy439[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE11; /* PFCAE11 */ - volatile uint8_t dummy4400[2]; /* */ - -/* end of struct st_gpio_from_pfcae1 */ - volatile uint8_t dummy4401[464]; /* */ - volatile uint32_t SNCR; /* SNCR */ - volatile uint8_t dummy441[13308]; /* */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC0; /* PIBC0 */ - volatile uint8_t dummy442[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC1; /* PIBC1 */ - volatile uint8_t dummy443[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC2; /* PIBC2 */ - volatile uint8_t dummy444[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC3; /* PIBC3 */ - volatile uint8_t dummy445[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC4; /* PIBC4 */ - volatile uint8_t dummy446[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC5; /* PIBC5 */ - volatile uint8_t dummy447[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC6; /* PIBC6 */ - volatile uint8_t dummy448[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC7; /* PIBC7 */ - volatile uint8_t dummy449[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC8; /* PIBC8 */ - volatile uint8_t dummy450[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC9; /* PIBC9 */ - volatile uint8_t dummy451[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC10; /* PIBC10 */ - volatile uint8_t dummy452[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC11; /* PIBC11 */ - volatile uint8_t dummy4530[2]; /* */ - -/* end of struct st_gpio_from_pibc1 */ - volatile uint8_t dummy4531[212]; /* */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC1; /* PBDC1 */ - volatile uint8_t dummy454[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC2; /* PBDC2 */ - volatile uint8_t dummy455[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC3; /* PBDC3 */ - volatile uint8_t dummy456[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC4; /* PBDC4 */ - volatile uint8_t dummy457[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC5; /* PBDC5 */ - volatile uint8_t dummy458[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC6; /* PBDC6 */ - volatile uint8_t dummy459[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC7; /* PBDC7 */ - volatile uint8_t dummy460[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC8; /* PBDC8 */ - volatile uint8_t dummy461[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC9; /* PBDC9 */ - volatile uint8_t dummy462[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC10; /* PBDC10 */ - volatile uint8_t dummy463[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC11; /* PBDC11 */ - volatile uint8_t dummy4640[2]; /* */ - -/* end of struct st_gpio_from_pbdc1 */ - volatile uint8_t dummy4641[212]; /* */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC1; /* PIPC1 */ - volatile uint8_t dummy465[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC2; /* PIPC2 */ - volatile uint8_t dummy466[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC3; /* PIPC3 */ - volatile uint8_t dummy467[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC4; /* PIPC4 */ - volatile uint8_t dummy468[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC5; /* PIPC5 */ - volatile uint8_t dummy469[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC6; /* PIPC6 */ - volatile uint8_t dummy470[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC7; /* PIPC7 */ - volatile uint8_t dummy471[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC8; /* PIPC8 */ - volatile uint8_t dummy472[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC9; /* PIPC9 */ - volatile uint8_t dummy473[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC10; /* PIPC10 */ - volatile uint8_t dummy474[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC11; /* PIPC11 */ - volatile uint8_t dummy4750[2]; /* */ - -/* end of struct st_gpio_from_pipc1 */ - volatile uint8_t dummy4751[2288]; /* */ - volatile uint16_t JPPR0; /* JPPR0 */ - volatile uint8_t dummy476[30]; /* */ - volatile uint16_t JPMC0; /* JPMC0 */ - volatile uint8_t dummy477[78]; /* */ - volatile uint32_t JPMCSR0; /* JPMCSR0 */ - volatile uint8_t dummy478[876]; /* */ - volatile uint16_t JPIBC0; /* JPIBC0 */ -} r_io_gpio_t; - - -typedef struct st_gpio_from_p1 -{ - - volatile uint16_t P1; /* P1 */ - volatile uint8_t dummy1[3]; /* */ -} r_io_gpio_from_p1_t; - - -typedef struct st_gpio_from_ppr0 -{ - - volatile uint16_t PPR0; /* PPR0 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_ppr0_t; - - -typedef struct st_gpio_from_pm1 -{ - - volatile uint16_t PM1; /* PM1 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pm1_t; - - -typedef struct st_gpio_from_pmc0 -{ - - volatile uint16_t PMC0; /* PMC0 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pmc0_t; - - -typedef struct st_gpio_from_pfc1 -{ - - volatile uint16_t PFC1; /* PFC1 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pfc1_t; - - -typedef struct st_gpio_from_pfce1 -{ - - volatile uint16_t PFCE1; /* PFCE1 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pfce1_t; - - -typedef struct st_gpio_from_pnot1 -{ - - volatile uint16_t PNOT1; /* PNOT1 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pnot1_t; - - -typedef struct st_gpio_from_pfcae1 -{ - - volatile uint16_t PFCAE1; /* PFCAE1 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pfcae1_t; - - -typedef struct st_gpio_from_pibc1 -{ - - volatile uint16_t PIBC1; /* PIBC1 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pibc1_t; - - -typedef struct st_gpio_from_pbdc1 -{ - - volatile uint16_t PBDC1; /* PBDC1 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pbdc1_t; - - -typedef struct st_gpio_from_pipc1 -{ - - volatile uint16_t PIPC1; /* PIPC1 */ - volatile uint8_t dummy1[2]; /* */ -} r_io_gpio_from_pipc1_t; - - -/* Channel array defines of GPIO (2)*/ -#ifdef DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS -volatile struct st_gpio_from_pipc1* GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS -volatile struct st_gpio_from_pbdc1* GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS -volatile struct st_gpio_from_pibc1* GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS -volatile struct st_gpio_from_pfcae1* GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS -volatile struct st_gpio_from_pnot1* GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS -volatile struct st_gpio_from_pfce1* GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS -volatile struct st_gpio_from_pfc1* GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS -volatile struct st_gpio_from_pmc0* GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS -volatile struct st_gpio_from_pm1* GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PM1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS -volatile struct st_gpio_from_ppr0* GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */ - -#ifdef DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS -volatile struct st_gpio_from_p1* GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - GPIO_FROM_P1_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */ -/* End of channel array defines of GPIO (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h deleted file mode 100644 index 5dee5fab31b..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h +++ /dev/null @@ -1,128 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : ieb_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef IEB_IODEFINE_H -#define IEB_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ - - -#define IEBB0BCR (IEB.B0BCR) -#define IEBB0PSR (IEB.B0PSR) -#define IEBB0UAR (IEB.B0UAR) -#define IEBB0SAR (IEB.B0SAR) -#define IEBB0PAR (IEB.B0PAR) -#define IEBB0RSA (IEB.B0RSA) -#define IEBB0CDR (IEB.B0CDR) -#define IEBB0TCD (IEB.B0TCD) -#define IEBB0RCD (IEB.B0RCD) -#define IEBB0DLR (IEB.B0DLR) -#define IEBB0TDL (IEB.B0TDL) -#define IEBB0RDL (IEB.B0RDL) -#define IEBB0CKS (IEB.B0CKS) -#define IEBB0TMS (IEB.B0TMS) -#define IEBB0PCR (IEB.B0PCR) -#define IEBB0BSR (IEB.B0BSR) -#define IEBB0SSR (IEB.B0SSR) -#define IEBB0USR (IEB.B0USR) -#define IEBB0ISR (IEB.B0ISR) -#define IEBB0ESR (IEB.B0ESR) -#define IEBB0FSR (IEB.B0FSR) -#define IEBB0SCR (IEB.B0SCR) -#define IEBB0CCR (IEB.B0CCR) -#define IEBB0STC0 (IEB.B0STC0) -#define IEBB0STC1 (IEB.B0STC1) -#define IEBB0DR (IEB.B0DR) - - -typedef struct st_ieb -{ - /* IEB */ - volatile uint8_t B0BCR; /* B0BCR */ - volatile uint8_t dummy495[3]; /* */ - volatile uint8_t B0PSR; /* B0PSR */ - volatile uint8_t dummy496[3]; /* */ - volatile uint16_t B0UAR; /* B0UAR */ - volatile uint8_t dummy497[2]; /* */ - volatile uint16_t B0SAR; /* B0SAR */ - volatile uint8_t dummy498[2]; /* */ - volatile uint16_t B0PAR; /* B0PAR */ - volatile uint8_t dummy499[2]; /* */ - volatile uint16_t B0RSA; /* B0RSA */ - volatile uint8_t dummy500[2]; /* */ - volatile uint8_t B0CDR; /* B0CDR */ - volatile uint8_t dummy501[3]; /* */ - volatile uint8_t B0TCD; /* B0TCD */ - volatile uint8_t dummy502[3]; /* */ - volatile uint8_t B0RCD; /* B0RCD */ - volatile uint8_t dummy503[3]; /* */ - volatile uint8_t B0DLR; /* B0DLR */ - volatile uint8_t dummy504[3]; /* */ - volatile uint8_t B0TDL; /* B0TDL */ - volatile uint8_t dummy505[3]; /* */ - volatile uint8_t B0RDL; /* B0RDL */ - volatile uint8_t dummy506[3]; /* */ - volatile uint8_t B0CKS; /* B0CKS */ - volatile uint8_t dummy507[3]; /* */ - volatile uint8_t B0TMS; /* B0TMS */ - volatile uint8_t dummy508[3]; /* */ - volatile uint8_t B0PCR; /* B0PCR */ - volatile uint8_t dummy509[3]; /* */ - volatile uint16_t B0BSR; /* B0BSR */ - volatile uint8_t dummy510[2]; /* */ - volatile uint8_t B0SSR; /* B0SSR */ - volatile uint8_t dummy511[3]; /* */ - volatile uint8_t B0USR; /* B0USR */ - volatile uint8_t dummy512[3]; /* */ - volatile uint8_t B0ISR; /* B0ISR */ - volatile uint8_t dummy513[3]; /* */ - volatile uint8_t B0ESR; /* B0ESR */ - volatile uint8_t dummy514[3]; /* */ - volatile uint8_t B0FSR; /* B0FSR */ - volatile uint8_t dummy515[3]; /* */ - volatile uint8_t B0SCR; /* B0SCR */ - volatile uint8_t dummy516[3]; /* */ - volatile uint8_t B0CCR; /* B0CCR */ - volatile uint8_t dummy517[3]; /* */ - volatile uint8_t B0STC0; /* B0STC0 */ - volatile uint8_t dummy518[3]; /* */ - volatile uint8_t B0STC1; /* B0STC1 */ - volatile uint8_t dummy519[3]; /* */ - volatile uint8_t B0DR; /* B0DR */ -} r_io_ieb_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h deleted file mode 100644 index ea148b05d49..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h +++ /dev/null @@ -1,112 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : inb_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef INB_IODEFINE_H -#define INB_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ - - -#define INBRMPR (INB.RMPR) -#define INBAXIBUSCTL0 (INB.AXIBUSCTL0) -#define INBAXIBUSCTL1 (INB.AXIBUSCTL1) -#define INBAXIBUSCTL2 (INB.AXIBUSCTL2) -#define INBAXIBUSCTL3 (INB.AXIBUSCTL3) -#define INBAXIBUSCTL4 (INB.AXIBUSCTL4) -#define INBAXIBUSCTL5 (INB.AXIBUSCTL5) -#define INBAXIBUSCTL6 (INB.AXIBUSCTL6) -#define INBAXIBUSCTL7 (INB.AXIBUSCTL7) -#define INBAXIBUSCTL8 (INB.AXIBUSCTL8) -#define INBAXIBUSCTL9 (INB.AXIBUSCTL9) -#define INBAXIBUSCTL10 (INB.AXIBUSCTL10) -#define INBAXIRERRCTL0 (INB.AXIRERRCTL0) -#define INBAXIRERRCTL1 (INB.AXIRERRCTL1) -#define INBAXIRERRCTL2 (INB.AXIRERRCTL2) -#define INBAXIRERRCTL3 (INB.AXIRERRCTL3) -#define INBAXIRERRST0 (INB.AXIRERRST0) -#define INBAXIRERRST1 (INB.AXIRERRST1) -#define INBAXIRERRST2 (INB.AXIRERRST2) -#define INBAXIRERRST3 (INB.AXIRERRST3) -#define INBAXIRERRCLR0 (INB.AXIRERRCLR0) -#define INBAXIRERRCLR1 (INB.AXIRERRCLR1) -#define INBAXIRERRCLR2 (INB.AXIRERRCLR2) -#define INBAXIRERRCLR3 (INB.AXIRERRCLR3) - -#define INB_AXIBUSCTLn_COUNT (11) -#define INB_AXIRERRCTLn_COUNT (4) -#define INB_AXIRERRSTn_COUNT (4) -#define INB_AXIRERRCLRn_COUNT (4) - - -typedef struct st_inb -{ - /* INB */ - volatile uint32_t RMPR; /* RMPR */ - -/* #define INB_AXIBUSCTLn_COUNT (11) */ - volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */ - volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */ - volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */ - volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */ - volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */ - volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */ - volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */ - volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */ - volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */ - volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */ - volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */ - -/* #define INB_AXIRERRCTLn_COUNT (4) */ - volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */ - volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */ - volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */ - volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */ - -/* #define INB_AXIRERRSTn_COUNT (4) */ - volatile uint32_t AXIRERRST0; /* AXIRERRST0 */ - volatile uint32_t AXIRERRST1; /* AXIRERRST1 */ - volatile uint32_t AXIRERRST2; /* AXIRERRST2 */ - volatile uint32_t AXIRERRST3; /* AXIRERRST3 */ - -/* #define INB_AXIRERRCLRn_COUNT (4) */ - volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */ - volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */ - volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */ - volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */ -} r_io_inb_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h deleted file mode 100644 index 6ee9ea1bab3..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h +++ /dev/null @@ -1,1054 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : intc_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef INTC_IODEFINE_H -#define INTC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ - - -#define INTCICDDCR (INTC.ICDDCR) -#define INTCICDICTR (INTC.ICDICTR) -#define INTCICDIIDR (INTC.ICDIIDR) -#define INTCICDISR0 (INTC.ICDISR0) -#define INTCICDISR1 (INTC.ICDISR1) -#define INTCICDISR2 (INTC.ICDISR2) -#define INTCICDISR3 (INTC.ICDISR3) -#define INTCICDISR4 (INTC.ICDISR4) -#define INTCICDISR5 (INTC.ICDISR5) -#define INTCICDISR6 (INTC.ICDISR6) -#define INTCICDISR7 (INTC.ICDISR7) -#define INTCICDISR8 (INTC.ICDISR8) -#define INTCICDISR9 (INTC.ICDISR9) -#define INTCICDISR10 (INTC.ICDISR10) -#define INTCICDISR11 (INTC.ICDISR11) -#define INTCICDISR12 (INTC.ICDISR12) -#define INTCICDISR13 (INTC.ICDISR13) -#define INTCICDISR14 (INTC.ICDISR14) -#define INTCICDISR15 (INTC.ICDISR15) -#define INTCICDISR16 (INTC.ICDISR16) -#define INTCICDISR17 (INTC.ICDISR17) -#define INTCICDISR18 (INTC.ICDISR18) -#define INTCICDISER0 (INTC.ICDISER0) -#define INTCICDISER1 (INTC.ICDISER1) -#define INTCICDISER2 (INTC.ICDISER2) -#define INTCICDISER3 (INTC.ICDISER3) -#define INTCICDISER4 (INTC.ICDISER4) -#define INTCICDISER5 (INTC.ICDISER5) -#define INTCICDISER6 (INTC.ICDISER6) -#define INTCICDISER7 (INTC.ICDISER7) -#define INTCICDISER8 (INTC.ICDISER8) -#define INTCICDISER9 (INTC.ICDISER9) -#define INTCICDISER10 (INTC.ICDISER10) -#define INTCICDISER11 (INTC.ICDISER11) -#define INTCICDISER12 (INTC.ICDISER12) -#define INTCICDISER13 (INTC.ICDISER13) -#define INTCICDISER14 (INTC.ICDISER14) -#define INTCICDISER15 (INTC.ICDISER15) -#define INTCICDISER16 (INTC.ICDISER16) -#define INTCICDISER17 (INTC.ICDISER17) -#define INTCICDISER18 (INTC.ICDISER18) -#define INTCICDICER0 (INTC.ICDICER0) -#define INTCICDICER1 (INTC.ICDICER1) -#define INTCICDICER2 (INTC.ICDICER2) -#define INTCICDICER3 (INTC.ICDICER3) -#define INTCICDICER4 (INTC.ICDICER4) -#define INTCICDICER5 (INTC.ICDICER5) -#define INTCICDICER6 (INTC.ICDICER6) -#define INTCICDICER7 (INTC.ICDICER7) -#define INTCICDICER8 (INTC.ICDICER8) -#define INTCICDICER9 (INTC.ICDICER9) -#define INTCICDICER10 (INTC.ICDICER10) -#define INTCICDICER11 (INTC.ICDICER11) -#define INTCICDICER12 (INTC.ICDICER12) -#define INTCICDICER13 (INTC.ICDICER13) -#define INTCICDICER14 (INTC.ICDICER14) -#define INTCICDICER15 (INTC.ICDICER15) -#define INTCICDICER16 (INTC.ICDICER16) -#define INTCICDICER17 (INTC.ICDICER17) -#define INTCICDICER18 (INTC.ICDICER18) -#define INTCICDISPR0 (INTC.ICDISPR0) -#define INTCICDISPR1 (INTC.ICDISPR1) -#define INTCICDISPR2 (INTC.ICDISPR2) -#define INTCICDISPR3 (INTC.ICDISPR3) -#define INTCICDISPR4 (INTC.ICDISPR4) -#define INTCICDISPR5 (INTC.ICDISPR5) -#define INTCICDISPR6 (INTC.ICDISPR6) -#define INTCICDISPR7 (INTC.ICDISPR7) -#define INTCICDISPR8 (INTC.ICDISPR8) -#define INTCICDISPR9 (INTC.ICDISPR9) -#define INTCICDISPR10 (INTC.ICDISPR10) -#define INTCICDISPR11 (INTC.ICDISPR11) -#define INTCICDISPR12 (INTC.ICDISPR12) -#define INTCICDISPR13 (INTC.ICDISPR13) -#define INTCICDISPR14 (INTC.ICDISPR14) -#define INTCICDISPR15 (INTC.ICDISPR15) -#define INTCICDISPR16 (INTC.ICDISPR16) -#define INTCICDISPR17 (INTC.ICDISPR17) -#define INTCICDISPR18 (INTC.ICDISPR18) -#define INTCICDICPR0 (INTC.ICDICPR0) -#define INTCICDICPR1 (INTC.ICDICPR1) -#define INTCICDICPR2 (INTC.ICDICPR2) -#define INTCICDICPR3 (INTC.ICDICPR3) -#define INTCICDICPR4 (INTC.ICDICPR4) -#define INTCICDICPR5 (INTC.ICDICPR5) -#define INTCICDICPR6 (INTC.ICDICPR6) -#define INTCICDICPR7 (INTC.ICDICPR7) -#define INTCICDICPR8 (INTC.ICDICPR8) -#define INTCICDICPR9 (INTC.ICDICPR9) -#define INTCICDICPR10 (INTC.ICDICPR10) -#define INTCICDICPR11 (INTC.ICDICPR11) -#define INTCICDICPR12 (INTC.ICDICPR12) -#define INTCICDICPR13 (INTC.ICDICPR13) -#define INTCICDICPR14 (INTC.ICDICPR14) -#define INTCICDICPR15 (INTC.ICDICPR15) -#define INTCICDICPR16 (INTC.ICDICPR16) -#define INTCICDICPR17 (INTC.ICDICPR17) -#define INTCICDICPR18 (INTC.ICDICPR18) -#define INTCICDABR0 (INTC.ICDABR0) -#define INTCICDABR1 (INTC.ICDABR1) -#define INTCICDABR2 (INTC.ICDABR2) -#define INTCICDABR3 (INTC.ICDABR3) -#define INTCICDABR4 (INTC.ICDABR4) -#define INTCICDABR5 (INTC.ICDABR5) -#define INTCICDABR6 (INTC.ICDABR6) -#define INTCICDABR7 (INTC.ICDABR7) -#define INTCICDABR8 (INTC.ICDABR8) -#define INTCICDABR9 (INTC.ICDABR9) -#define INTCICDABR10 (INTC.ICDABR10) -#define INTCICDABR11 (INTC.ICDABR11) -#define INTCICDABR12 (INTC.ICDABR12) -#define INTCICDABR13 (INTC.ICDABR13) -#define INTCICDABR14 (INTC.ICDABR14) -#define INTCICDABR15 (INTC.ICDABR15) -#define INTCICDABR16 (INTC.ICDABR16) -#define INTCICDABR17 (INTC.ICDABR17) -#define INTCICDABR18 (INTC.ICDABR18) -#define INTCICDIPR0 (INTC.ICDIPR0) -#define INTCICDIPR1 (INTC.ICDIPR1) -#define INTCICDIPR2 (INTC.ICDIPR2) -#define INTCICDIPR3 (INTC.ICDIPR3) -#define INTCICDIPR4 (INTC.ICDIPR4) -#define INTCICDIPR5 (INTC.ICDIPR5) -#define INTCICDIPR6 (INTC.ICDIPR6) -#define INTCICDIPR7 (INTC.ICDIPR7) -#define INTCICDIPR8 (INTC.ICDIPR8) -#define INTCICDIPR9 (INTC.ICDIPR9) -#define INTCICDIPR10 (INTC.ICDIPR10) -#define INTCICDIPR11 (INTC.ICDIPR11) -#define INTCICDIPR12 (INTC.ICDIPR12) -#define INTCICDIPR13 (INTC.ICDIPR13) -#define INTCICDIPR14 (INTC.ICDIPR14) -#define INTCICDIPR15 (INTC.ICDIPR15) -#define INTCICDIPR16 (INTC.ICDIPR16) -#define INTCICDIPR17 (INTC.ICDIPR17) -#define INTCICDIPR18 (INTC.ICDIPR18) -#define INTCICDIPR19 (INTC.ICDIPR19) -#define INTCICDIPR20 (INTC.ICDIPR20) -#define INTCICDIPR21 (INTC.ICDIPR21) -#define INTCICDIPR22 (INTC.ICDIPR22) -#define INTCICDIPR23 (INTC.ICDIPR23) -#define INTCICDIPR24 (INTC.ICDIPR24) -#define INTCICDIPR25 (INTC.ICDIPR25) -#define INTCICDIPR26 (INTC.ICDIPR26) -#define INTCICDIPR27 (INTC.ICDIPR27) -#define INTCICDIPR28 (INTC.ICDIPR28) -#define INTCICDIPR29 (INTC.ICDIPR29) -#define INTCICDIPR30 (INTC.ICDIPR30) -#define INTCICDIPR31 (INTC.ICDIPR31) -#define INTCICDIPR32 (INTC.ICDIPR32) -#define INTCICDIPR33 (INTC.ICDIPR33) -#define INTCICDIPR34 (INTC.ICDIPR34) -#define INTCICDIPR35 (INTC.ICDIPR35) -#define INTCICDIPR36 (INTC.ICDIPR36) -#define INTCICDIPR37 (INTC.ICDIPR37) -#define INTCICDIPR38 (INTC.ICDIPR38) -#define INTCICDIPR39 (INTC.ICDIPR39) -#define INTCICDIPR40 (INTC.ICDIPR40) -#define INTCICDIPR41 (INTC.ICDIPR41) -#define INTCICDIPR42 (INTC.ICDIPR42) -#define INTCICDIPR43 (INTC.ICDIPR43) -#define INTCICDIPR44 (INTC.ICDIPR44) -#define INTCICDIPR45 (INTC.ICDIPR45) -#define INTCICDIPR46 (INTC.ICDIPR46) -#define INTCICDIPR47 (INTC.ICDIPR47) -#define INTCICDIPR48 (INTC.ICDIPR48) -#define INTCICDIPR49 (INTC.ICDIPR49) -#define INTCICDIPR50 (INTC.ICDIPR50) -#define INTCICDIPR51 (INTC.ICDIPR51) -#define INTCICDIPR52 (INTC.ICDIPR52) -#define INTCICDIPR53 (INTC.ICDIPR53) -#define INTCICDIPR54 (INTC.ICDIPR54) -#define INTCICDIPR55 (INTC.ICDIPR55) -#define INTCICDIPR56 (INTC.ICDIPR56) -#define INTCICDIPR57 (INTC.ICDIPR57) -#define INTCICDIPR58 (INTC.ICDIPR58) -#define INTCICDIPR59 (INTC.ICDIPR59) -#define INTCICDIPR60 (INTC.ICDIPR60) -#define INTCICDIPR61 (INTC.ICDIPR61) -#define INTCICDIPR62 (INTC.ICDIPR62) -#define INTCICDIPR63 (INTC.ICDIPR63) -#define INTCICDIPR64 (INTC.ICDIPR64) -#define INTCICDIPR65 (INTC.ICDIPR65) -#define INTCICDIPR66 (INTC.ICDIPR66) -#define INTCICDIPR67 (INTC.ICDIPR67) -#define INTCICDIPR68 (INTC.ICDIPR68) -#define INTCICDIPR69 (INTC.ICDIPR69) -#define INTCICDIPR70 (INTC.ICDIPR70) -#define INTCICDIPR71 (INTC.ICDIPR71) -#define INTCICDIPR72 (INTC.ICDIPR72) -#define INTCICDIPR73 (INTC.ICDIPR73) -#define INTCICDIPR74 (INTC.ICDIPR74) -#define INTCICDIPR75 (INTC.ICDIPR75) -#define INTCICDIPR76 (INTC.ICDIPR76) -#define INTCICDIPR77 (INTC.ICDIPR77) -#define INTCICDIPR78 (INTC.ICDIPR78) -#define INTCICDIPR79 (INTC.ICDIPR79) -#define INTCICDIPR80 (INTC.ICDIPR80) -#define INTCICDIPR81 (INTC.ICDIPR81) -#define INTCICDIPR82 (INTC.ICDIPR82) -#define INTCICDIPR83 (INTC.ICDIPR83) -#define INTCICDIPR84 (INTC.ICDIPR84) -#define INTCICDIPR85 (INTC.ICDIPR85) -#define INTCICDIPR86 (INTC.ICDIPR86) -#define INTCICDIPR87 (INTC.ICDIPR87) -#define INTCICDIPR88 (INTC.ICDIPR88) -#define INTCICDIPR89 (INTC.ICDIPR89) -#define INTCICDIPR90 (INTC.ICDIPR90) -#define INTCICDIPR91 (INTC.ICDIPR91) -#define INTCICDIPR92 (INTC.ICDIPR92) -#define INTCICDIPR93 (INTC.ICDIPR93) -#define INTCICDIPR94 (INTC.ICDIPR94) -#define INTCICDIPR95 (INTC.ICDIPR95) -#define INTCICDIPR96 (INTC.ICDIPR96) -#define INTCICDIPR97 (INTC.ICDIPR97) -#define INTCICDIPR98 (INTC.ICDIPR98) -#define INTCICDIPR99 (INTC.ICDIPR99) -#define INTCICDIPR100 (INTC.ICDIPR100) -#define INTCICDIPR101 (INTC.ICDIPR101) -#define INTCICDIPR102 (INTC.ICDIPR102) -#define INTCICDIPR103 (INTC.ICDIPR103) -#define INTCICDIPR104 (INTC.ICDIPR104) -#define INTCICDIPR105 (INTC.ICDIPR105) -#define INTCICDIPR106 (INTC.ICDIPR106) -#define INTCICDIPR107 (INTC.ICDIPR107) -#define INTCICDIPR108 (INTC.ICDIPR108) -#define INTCICDIPR109 (INTC.ICDIPR109) -#define INTCICDIPR110 (INTC.ICDIPR110) -#define INTCICDIPR111 (INTC.ICDIPR111) -#define INTCICDIPR112 (INTC.ICDIPR112) -#define INTCICDIPR113 (INTC.ICDIPR113) -#define INTCICDIPR114 (INTC.ICDIPR114) -#define INTCICDIPR115 (INTC.ICDIPR115) -#define INTCICDIPR116 (INTC.ICDIPR116) -#define INTCICDIPR117 (INTC.ICDIPR117) -#define INTCICDIPR118 (INTC.ICDIPR118) -#define INTCICDIPR119 (INTC.ICDIPR119) -#define INTCICDIPR120 (INTC.ICDIPR120) -#define INTCICDIPR121 (INTC.ICDIPR121) -#define INTCICDIPR122 (INTC.ICDIPR122) -#define INTCICDIPR123 (INTC.ICDIPR123) -#define INTCICDIPR124 (INTC.ICDIPR124) -#define INTCICDIPR125 (INTC.ICDIPR125) -#define INTCICDIPR126 (INTC.ICDIPR126) -#define INTCICDIPR127 (INTC.ICDIPR127) -#define INTCICDIPR128 (INTC.ICDIPR128) -#define INTCICDIPR129 (INTC.ICDIPR129) -#define INTCICDIPR130 (INTC.ICDIPR130) -#define INTCICDIPR131 (INTC.ICDIPR131) -#define INTCICDIPR132 (INTC.ICDIPR132) -#define INTCICDIPR133 (INTC.ICDIPR133) -#define INTCICDIPR134 (INTC.ICDIPR134) -#define INTCICDIPR135 (INTC.ICDIPR135) -#define INTCICDIPR136 (INTC.ICDIPR136) -#define INTCICDIPR137 (INTC.ICDIPR137) -#define INTCICDIPR138 (INTC.ICDIPR138) -#define INTCICDIPR139 (INTC.ICDIPR139) -#define INTCICDIPR140 (INTC.ICDIPR140) -#define INTCICDIPR141 (INTC.ICDIPR141) -#define INTCICDIPR142 (INTC.ICDIPR142) -#define INTCICDIPR143 (INTC.ICDIPR143) -#define INTCICDIPR144 (INTC.ICDIPR144) -#define INTCICDIPR145 (INTC.ICDIPR145) -#define INTCICDIPR146 (INTC.ICDIPR146) -#define INTCICDIPTR0 (INTC.ICDIPTR0) -#define INTCICDIPTR1 (INTC.ICDIPTR1) -#define INTCICDIPTR2 (INTC.ICDIPTR2) -#define INTCICDIPTR3 (INTC.ICDIPTR3) -#define INTCICDIPTR4 (INTC.ICDIPTR4) -#define INTCICDIPTR5 (INTC.ICDIPTR5) -#define INTCICDIPTR6 (INTC.ICDIPTR6) -#define INTCICDIPTR7 (INTC.ICDIPTR7) -#define INTCICDIPTR8 (INTC.ICDIPTR8) -#define INTCICDIPTR9 (INTC.ICDIPTR9) -#define INTCICDIPTR10 (INTC.ICDIPTR10) -#define INTCICDIPTR11 (INTC.ICDIPTR11) -#define INTCICDIPTR12 (INTC.ICDIPTR12) -#define INTCICDIPTR13 (INTC.ICDIPTR13) -#define INTCICDIPTR14 (INTC.ICDIPTR14) -#define INTCICDIPTR15 (INTC.ICDIPTR15) -#define INTCICDIPTR16 (INTC.ICDIPTR16) -#define INTCICDIPTR17 (INTC.ICDIPTR17) -#define INTCICDIPTR18 (INTC.ICDIPTR18) -#define INTCICDIPTR19 (INTC.ICDIPTR19) -#define INTCICDIPTR20 (INTC.ICDIPTR20) -#define INTCICDIPTR21 (INTC.ICDIPTR21) -#define INTCICDIPTR22 (INTC.ICDIPTR22) -#define INTCICDIPTR23 (INTC.ICDIPTR23) -#define INTCICDIPTR24 (INTC.ICDIPTR24) -#define INTCICDIPTR25 (INTC.ICDIPTR25) -#define INTCICDIPTR26 (INTC.ICDIPTR26) -#define INTCICDIPTR27 (INTC.ICDIPTR27) -#define INTCICDIPTR28 (INTC.ICDIPTR28) -#define INTCICDIPTR29 (INTC.ICDIPTR29) -#define INTCICDIPTR30 (INTC.ICDIPTR30) -#define INTCICDIPTR31 (INTC.ICDIPTR31) -#define INTCICDIPTR32 (INTC.ICDIPTR32) -#define INTCICDIPTR33 (INTC.ICDIPTR33) -#define INTCICDIPTR34 (INTC.ICDIPTR34) -#define INTCICDIPTR35 (INTC.ICDIPTR35) -#define INTCICDIPTR36 (INTC.ICDIPTR36) -#define INTCICDIPTR37 (INTC.ICDIPTR37) -#define INTCICDIPTR38 (INTC.ICDIPTR38) -#define INTCICDIPTR39 (INTC.ICDIPTR39) -#define INTCICDIPTR40 (INTC.ICDIPTR40) -#define INTCICDIPTR41 (INTC.ICDIPTR41) -#define INTCICDIPTR42 (INTC.ICDIPTR42) -#define INTCICDIPTR43 (INTC.ICDIPTR43) -#define INTCICDIPTR44 (INTC.ICDIPTR44) -#define INTCICDIPTR45 (INTC.ICDIPTR45) -#define INTCICDIPTR46 (INTC.ICDIPTR46) -#define INTCICDIPTR47 (INTC.ICDIPTR47) -#define INTCICDIPTR48 (INTC.ICDIPTR48) -#define INTCICDIPTR49 (INTC.ICDIPTR49) -#define INTCICDIPTR50 (INTC.ICDIPTR50) -#define INTCICDIPTR51 (INTC.ICDIPTR51) -#define INTCICDIPTR52 (INTC.ICDIPTR52) -#define INTCICDIPTR53 (INTC.ICDIPTR53) -#define INTCICDIPTR54 (INTC.ICDIPTR54) -#define INTCICDIPTR55 (INTC.ICDIPTR55) -#define INTCICDIPTR56 (INTC.ICDIPTR56) -#define INTCICDIPTR57 (INTC.ICDIPTR57) -#define INTCICDIPTR58 (INTC.ICDIPTR58) -#define INTCICDIPTR59 (INTC.ICDIPTR59) -#define INTCICDIPTR60 (INTC.ICDIPTR60) -#define INTCICDIPTR61 (INTC.ICDIPTR61) -#define INTCICDIPTR62 (INTC.ICDIPTR62) -#define INTCICDIPTR63 (INTC.ICDIPTR63) -#define INTCICDIPTR64 (INTC.ICDIPTR64) -#define INTCICDIPTR65 (INTC.ICDIPTR65) -#define INTCICDIPTR66 (INTC.ICDIPTR66) -#define INTCICDIPTR67 (INTC.ICDIPTR67) -#define INTCICDIPTR68 (INTC.ICDIPTR68) -#define INTCICDIPTR69 (INTC.ICDIPTR69) -#define INTCICDIPTR70 (INTC.ICDIPTR70) -#define INTCICDIPTR71 (INTC.ICDIPTR71) -#define INTCICDIPTR72 (INTC.ICDIPTR72) -#define INTCICDIPTR73 (INTC.ICDIPTR73) -#define INTCICDIPTR74 (INTC.ICDIPTR74) -#define INTCICDIPTR75 (INTC.ICDIPTR75) -#define INTCICDIPTR76 (INTC.ICDIPTR76) -#define INTCICDIPTR77 (INTC.ICDIPTR77) -#define INTCICDIPTR78 (INTC.ICDIPTR78) -#define INTCICDIPTR79 (INTC.ICDIPTR79) -#define INTCICDIPTR80 (INTC.ICDIPTR80) -#define INTCICDIPTR81 (INTC.ICDIPTR81) -#define INTCICDIPTR82 (INTC.ICDIPTR82) -#define INTCICDIPTR83 (INTC.ICDIPTR83) -#define INTCICDIPTR84 (INTC.ICDIPTR84) -#define INTCICDIPTR85 (INTC.ICDIPTR85) -#define INTCICDIPTR86 (INTC.ICDIPTR86) -#define INTCICDIPTR87 (INTC.ICDIPTR87) -#define INTCICDIPTR88 (INTC.ICDIPTR88) -#define INTCICDIPTR89 (INTC.ICDIPTR89) -#define INTCICDIPTR90 (INTC.ICDIPTR90) -#define INTCICDIPTR91 (INTC.ICDIPTR91) -#define INTCICDIPTR92 (INTC.ICDIPTR92) -#define INTCICDIPTR93 (INTC.ICDIPTR93) -#define INTCICDIPTR94 (INTC.ICDIPTR94) -#define INTCICDIPTR95 (INTC.ICDIPTR95) -#define INTCICDIPTR96 (INTC.ICDIPTR96) -#define INTCICDIPTR97 (INTC.ICDIPTR97) -#define INTCICDIPTR98 (INTC.ICDIPTR98) -#define INTCICDIPTR99 (INTC.ICDIPTR99) -#define INTCICDIPTR100 (INTC.ICDIPTR100) -#define INTCICDIPTR101 (INTC.ICDIPTR101) -#define INTCICDIPTR102 (INTC.ICDIPTR102) -#define INTCICDIPTR103 (INTC.ICDIPTR103) -#define INTCICDIPTR104 (INTC.ICDIPTR104) -#define INTCICDIPTR105 (INTC.ICDIPTR105) -#define INTCICDIPTR106 (INTC.ICDIPTR106) -#define INTCICDIPTR107 (INTC.ICDIPTR107) -#define INTCICDIPTR108 (INTC.ICDIPTR108) -#define INTCICDIPTR109 (INTC.ICDIPTR109) -#define INTCICDIPTR110 (INTC.ICDIPTR110) -#define INTCICDIPTR111 (INTC.ICDIPTR111) -#define INTCICDIPTR112 (INTC.ICDIPTR112) -#define INTCICDIPTR113 (INTC.ICDIPTR113) -#define INTCICDIPTR114 (INTC.ICDIPTR114) -#define INTCICDIPTR115 (INTC.ICDIPTR115) -#define INTCICDIPTR116 (INTC.ICDIPTR116) -#define INTCICDIPTR117 (INTC.ICDIPTR117) -#define INTCICDIPTR118 (INTC.ICDIPTR118) -#define INTCICDIPTR119 (INTC.ICDIPTR119) -#define INTCICDIPTR120 (INTC.ICDIPTR120) -#define INTCICDIPTR121 (INTC.ICDIPTR121) -#define INTCICDIPTR122 (INTC.ICDIPTR122) -#define INTCICDIPTR123 (INTC.ICDIPTR123) -#define INTCICDIPTR124 (INTC.ICDIPTR124) -#define INTCICDIPTR125 (INTC.ICDIPTR125) -#define INTCICDIPTR126 (INTC.ICDIPTR126) -#define INTCICDIPTR127 (INTC.ICDIPTR127) -#define INTCICDIPTR128 (INTC.ICDIPTR128) -#define INTCICDIPTR129 (INTC.ICDIPTR129) -#define INTCICDIPTR130 (INTC.ICDIPTR130) -#define INTCICDIPTR131 (INTC.ICDIPTR131) -#define INTCICDIPTR132 (INTC.ICDIPTR132) -#define INTCICDIPTR133 (INTC.ICDIPTR133) -#define INTCICDIPTR134 (INTC.ICDIPTR134) -#define INTCICDIPTR135 (INTC.ICDIPTR135) -#define INTCICDIPTR136 (INTC.ICDIPTR136) -#define INTCICDIPTR137 (INTC.ICDIPTR137) -#define INTCICDIPTR138 (INTC.ICDIPTR138) -#define INTCICDIPTR139 (INTC.ICDIPTR139) -#define INTCICDIPTR140 (INTC.ICDIPTR140) -#define INTCICDIPTR141 (INTC.ICDIPTR141) -#define INTCICDIPTR142 (INTC.ICDIPTR142) -#define INTCICDIPTR143 (INTC.ICDIPTR143) -#define INTCICDIPTR144 (INTC.ICDIPTR144) -#define INTCICDIPTR145 (INTC.ICDIPTR145) -#define INTCICDIPTR146 (INTC.ICDIPTR146) -#define INTCICDICFR0 (INTC.ICDICFR0) -#define INTCICDICFR1 (INTC.ICDICFR1) -#define INTCICDICFR2 (INTC.ICDICFR2) -#define INTCICDICFR3 (INTC.ICDICFR3) -#define INTCICDICFR4 (INTC.ICDICFR4) -#define INTCICDICFR5 (INTC.ICDICFR5) -#define INTCICDICFR6 (INTC.ICDICFR6) -#define INTCICDICFR7 (INTC.ICDICFR7) -#define INTCICDICFR8 (INTC.ICDICFR8) -#define INTCICDICFR9 (INTC.ICDICFR9) -#define INTCICDICFR10 (INTC.ICDICFR10) -#define INTCICDICFR11 (INTC.ICDICFR11) -#define INTCICDICFR12 (INTC.ICDICFR12) -#define INTCICDICFR13 (INTC.ICDICFR13) -#define INTCICDICFR14 (INTC.ICDICFR14) -#define INTCICDICFR15 (INTC.ICDICFR15) -#define INTCICDICFR16 (INTC.ICDICFR16) -#define INTCICDICFR17 (INTC.ICDICFR17) -#define INTCICDICFR18 (INTC.ICDICFR18) -#define INTCICDICFR19 (INTC.ICDICFR19) -#define INTCICDICFR20 (INTC.ICDICFR20) -#define INTCICDICFR21 (INTC.ICDICFR21) -#define INTCICDICFR22 (INTC.ICDICFR22) -#define INTCICDICFR23 (INTC.ICDICFR23) -#define INTCICDICFR24 (INTC.ICDICFR24) -#define INTCICDICFR25 (INTC.ICDICFR25) -#define INTCICDICFR26 (INTC.ICDICFR26) -#define INTCICDICFR27 (INTC.ICDICFR27) -#define INTCICDICFR28 (INTC.ICDICFR28) -#define INTCICDICFR29 (INTC.ICDICFR29) -#define INTCICDICFR30 (INTC.ICDICFR30) -#define INTCICDICFR31 (INTC.ICDICFR31) -#define INTCICDICFR32 (INTC.ICDICFR32) -#define INTCICDICFR33 (INTC.ICDICFR33) -#define INTCICDICFR34 (INTC.ICDICFR34) -#define INTCICDICFR35 (INTC.ICDICFR35) -#define INTCICDICFR36 (INTC.ICDICFR36) -#define INTCPPI_STATUS (INTC.PPI_STATUS) -#define INTCSPI_STATUS0 (INTC.SPI_STATUS0) -#define INTCSPI_STATUS1 (INTC.SPI_STATUS1) -#define INTCSPI_STATUS2 (INTC.SPI_STATUS2) -#define INTCSPI_STATUS3 (INTC.SPI_STATUS3) -#define INTCSPI_STATUS4 (INTC.SPI_STATUS4) -#define INTCSPI_STATUS5 (INTC.SPI_STATUS5) -#define INTCSPI_STATUS6 (INTC.SPI_STATUS6) -#define INTCSPI_STATUS7 (INTC.SPI_STATUS7) -#define INTCSPI_STATUS8 (INTC.SPI_STATUS8) -#define INTCSPI_STATUS9 (INTC.SPI_STATUS9) -#define INTCSPI_STATUS10 (INTC.SPI_STATUS10) -#define INTCSPI_STATUS11 (INTC.SPI_STATUS11) -#define INTCSPI_STATUS12 (INTC.SPI_STATUS12) -#define INTCSPI_STATUS13 (INTC.SPI_STATUS13) -#define INTCSPI_STATUS14 (INTC.SPI_STATUS14) -#define INTCSPI_STATUS15 (INTC.SPI_STATUS15) -#define INTCSPI_STATUS16 (INTC.SPI_STATUS16) -#define INTCICDSGIR (INTC.ICDSGIR) -#define INTCICCICR (INTC.ICCICR) -#define INTCICCPMR (INTC.ICCPMR) -#define INTCICCBPR (INTC.ICCBPR) -#define INTCICCIAR (INTC.ICCIAR) -#define INTCICCEOIR (INTC.ICCEOIR) -#define INTCICCRPR (INTC.ICCRPR) -#define INTCICCHPIR (INTC.ICCHPIR) -#define INTCICCABPR (INTC.ICCABPR) -#define INTCICCIIDR (INTC.ICCIIDR) -#define INTCICR0 (INTC.ICR0) -#define INTCICR1 (INTC.ICR1) -#define INTCIRQRR (INTC.IRQRR) - -#define INTC_ICDISR0_COUNT (19) -#define INTC_ICDISER0_COUNT (19) -#define INTC_ICDICER0_COUNT (19) -#define INTC_ICDISPR0_COUNT (19) -#define INTC_ICDICPR0_COUNT (19) -#define INTC_ICDABR0_COUNT (19) -#define INTC_ICDIPR0_COUNT (147) -#define INTC_ICDIPTR0_COUNT (147) -#define INTC_ICDICFR0_COUNT (37) -#define INTC_SPI_STATUS0_COUNT (17) - - -typedef struct st_intc -{ - /* INTC */ - volatile uint32_t ICDDCR; /* ICDDCR */ - volatile uint32_t ICDICTR; /* ICDICTR */ - volatile uint32_t ICDIIDR; /* ICDIIDR */ - volatile uint8_t dummy193[116]; /* */ - -/* #define INTC_ICDISR0_COUNT (19) */ - volatile uint32_t ICDISR0; /* ICDISR0 */ - volatile uint32_t ICDISR1; /* ICDISR1 */ - volatile uint32_t ICDISR2; /* ICDISR2 */ - volatile uint32_t ICDISR3; /* ICDISR3 */ - volatile uint32_t ICDISR4; /* ICDISR4 */ - volatile uint32_t ICDISR5; /* ICDISR5 */ - volatile uint32_t ICDISR6; /* ICDISR6 */ - volatile uint32_t ICDISR7; /* ICDISR7 */ - volatile uint32_t ICDISR8; /* ICDISR8 */ - volatile uint32_t ICDISR9; /* ICDISR9 */ - volatile uint32_t ICDISR10; /* ICDISR10 */ - volatile uint32_t ICDISR11; /* ICDISR11 */ - volatile uint32_t ICDISR12; /* ICDISR12 */ - volatile uint32_t ICDISR13; /* ICDISR13 */ - volatile uint32_t ICDISR14; /* ICDISR14 */ - volatile uint32_t ICDISR15; /* ICDISR15 */ - volatile uint32_t ICDISR16; /* ICDISR16 */ - volatile uint32_t ICDISR17; /* ICDISR17 */ - volatile uint32_t ICDISR18; /* ICDISR18 */ - volatile uint8_t dummy194[52]; /* */ - -/* #define INTC_ICDISER0_COUNT (19) */ - volatile uint32_t ICDISER0; /* ICDISER0 */ - volatile uint32_t ICDISER1; /* ICDISER1 */ - volatile uint32_t ICDISER2; /* ICDISER2 */ - volatile uint32_t ICDISER3; /* ICDISER3 */ - volatile uint32_t ICDISER4; /* ICDISER4 */ - volatile uint32_t ICDISER5; /* ICDISER5 */ - volatile uint32_t ICDISER6; /* ICDISER6 */ - volatile uint32_t ICDISER7; /* ICDISER7 */ - volatile uint32_t ICDISER8; /* ICDISER8 */ - volatile uint32_t ICDISER9; /* ICDISER9 */ - volatile uint32_t ICDISER10; /* ICDISER10 */ - volatile uint32_t ICDISER11; /* ICDISER11 */ - volatile uint32_t ICDISER12; /* ICDISER12 */ - volatile uint32_t ICDISER13; /* ICDISER13 */ - volatile uint32_t ICDISER14; /* ICDISER14 */ - volatile uint32_t ICDISER15; /* ICDISER15 */ - volatile uint32_t ICDISER16; /* ICDISER16 */ - volatile uint32_t ICDISER17; /* ICDISER17 */ - volatile uint32_t ICDISER18; /* ICDISER18 */ - volatile uint8_t dummy195[52]; /* */ - -/* #define INTC_ICDICER0_COUNT (19) */ - volatile uint32_t ICDICER0; /* ICDICER0 */ - volatile uint32_t ICDICER1; /* ICDICER1 */ - volatile uint32_t ICDICER2; /* ICDICER2 */ - volatile uint32_t ICDICER3; /* ICDICER3 */ - volatile uint32_t ICDICER4; /* ICDICER4 */ - volatile uint32_t ICDICER5; /* ICDICER5 */ - volatile uint32_t ICDICER6; /* ICDICER6 */ - volatile uint32_t ICDICER7; /* ICDICER7 */ - volatile uint32_t ICDICER8; /* ICDICER8 */ - volatile uint32_t ICDICER9; /* ICDICER9 */ - volatile uint32_t ICDICER10; /* ICDICER10 */ - volatile uint32_t ICDICER11; /* ICDICER11 */ - volatile uint32_t ICDICER12; /* ICDICER12 */ - volatile uint32_t ICDICER13; /* ICDICER13 */ - volatile uint32_t ICDICER14; /* ICDICER14 */ - volatile uint32_t ICDICER15; /* ICDICER15 */ - volatile uint32_t ICDICER16; /* ICDICER16 */ - volatile uint32_t ICDICER17; /* ICDICER17 */ - volatile uint32_t ICDICER18; /* ICDICER18 */ - volatile uint8_t dummy196[52]; /* */ - -/* #define INTC_ICDISPR0_COUNT (19) */ - volatile uint32_t ICDISPR0; /* ICDISPR0 */ - volatile uint32_t ICDISPR1; /* ICDISPR1 */ - volatile uint32_t ICDISPR2; /* ICDISPR2 */ - volatile uint32_t ICDISPR3; /* ICDISPR3 */ - volatile uint32_t ICDISPR4; /* ICDISPR4 */ - volatile uint32_t ICDISPR5; /* ICDISPR5 */ - volatile uint32_t ICDISPR6; /* ICDISPR6 */ - volatile uint32_t ICDISPR7; /* ICDISPR7 */ - volatile uint32_t ICDISPR8; /* ICDISPR8 */ - volatile uint32_t ICDISPR9; /* ICDISPR9 */ - volatile uint32_t ICDISPR10; /* ICDISPR10 */ - volatile uint32_t ICDISPR11; /* ICDISPR11 */ - volatile uint32_t ICDISPR12; /* ICDISPR12 */ - volatile uint32_t ICDISPR13; /* ICDISPR13 */ - volatile uint32_t ICDISPR14; /* ICDISPR14 */ - volatile uint32_t ICDISPR15; /* ICDISPR15 */ - volatile uint32_t ICDISPR16; /* ICDISPR16 */ - volatile uint32_t ICDISPR17; /* ICDISPR17 */ - volatile uint32_t ICDISPR18; /* ICDISPR18 */ - volatile uint8_t dummy197[52]; /* */ - -/* #define INTC_ICDICPR0_COUNT (19) */ - volatile uint32_t ICDICPR0; /* ICDICPR0 */ - volatile uint32_t ICDICPR1; /* ICDICPR1 */ - volatile uint32_t ICDICPR2; /* ICDICPR2 */ - volatile uint32_t ICDICPR3; /* ICDICPR3 */ - volatile uint32_t ICDICPR4; /* ICDICPR4 */ - volatile uint32_t ICDICPR5; /* ICDICPR5 */ - volatile uint32_t ICDICPR6; /* ICDICPR6 */ - volatile uint32_t ICDICPR7; /* ICDICPR7 */ - volatile uint32_t ICDICPR8; /* ICDICPR8 */ - volatile uint32_t ICDICPR9; /* ICDICPR9 */ - volatile uint32_t ICDICPR10; /* ICDICPR10 */ - volatile uint32_t ICDICPR11; /* ICDICPR11 */ - volatile uint32_t ICDICPR12; /* ICDICPR12 */ - volatile uint32_t ICDICPR13; /* ICDICPR13 */ - volatile uint32_t ICDICPR14; /* ICDICPR14 */ - volatile uint32_t ICDICPR15; /* ICDICPR15 */ - volatile uint32_t ICDICPR16; /* ICDICPR16 */ - volatile uint32_t ICDICPR17; /* ICDICPR17 */ - volatile uint32_t ICDICPR18; /* ICDICPR18 */ - volatile uint8_t dummy198[52]; /* */ - -/* #define INTC_ICDABR0_COUNT (19) */ - volatile uint32_t ICDABR0; /* ICDABR0 */ - volatile uint32_t ICDABR1; /* ICDABR1 */ - volatile uint32_t ICDABR2; /* ICDABR2 */ - volatile uint32_t ICDABR3; /* ICDABR3 */ - volatile uint32_t ICDABR4; /* ICDABR4 */ - volatile uint32_t ICDABR5; /* ICDABR5 */ - volatile uint32_t ICDABR6; /* ICDABR6 */ - volatile uint32_t ICDABR7; /* ICDABR7 */ - volatile uint32_t ICDABR8; /* ICDABR8 */ - volatile uint32_t ICDABR9; /* ICDABR9 */ - volatile uint32_t ICDABR10; /* ICDABR10 */ - volatile uint32_t ICDABR11; /* ICDABR11 */ - volatile uint32_t ICDABR12; /* ICDABR12 */ - volatile uint32_t ICDABR13; /* ICDABR13 */ - volatile uint32_t ICDABR14; /* ICDABR14 */ - volatile uint32_t ICDABR15; /* ICDABR15 */ - volatile uint32_t ICDABR16; /* ICDABR16 */ - volatile uint32_t ICDABR17; /* ICDABR17 */ - volatile uint32_t ICDABR18; /* ICDABR18 */ - volatile uint8_t dummy199[180]; /* */ - -/* #define INTC_ICDIPR0_COUNT (147) */ - volatile uint32_t ICDIPR0; /* ICDIPR0 */ - volatile uint32_t ICDIPR1; /* ICDIPR1 */ - volatile uint32_t ICDIPR2; /* ICDIPR2 */ - volatile uint32_t ICDIPR3; /* ICDIPR3 */ - volatile uint32_t ICDIPR4; /* ICDIPR4 */ - volatile uint32_t ICDIPR5; /* ICDIPR5 */ - volatile uint32_t ICDIPR6; /* ICDIPR6 */ - volatile uint32_t ICDIPR7; /* ICDIPR7 */ - volatile uint32_t ICDIPR8; /* ICDIPR8 */ - volatile uint32_t ICDIPR9; /* ICDIPR9 */ - volatile uint32_t ICDIPR10; /* ICDIPR10 */ - volatile uint32_t ICDIPR11; /* ICDIPR11 */ - volatile uint32_t ICDIPR12; /* ICDIPR12 */ - volatile uint32_t ICDIPR13; /* ICDIPR13 */ - volatile uint32_t ICDIPR14; /* ICDIPR14 */ - volatile uint32_t ICDIPR15; /* ICDIPR15 */ - volatile uint32_t ICDIPR16; /* ICDIPR16 */ - volatile uint32_t ICDIPR17; /* ICDIPR17 */ - volatile uint32_t ICDIPR18; /* ICDIPR18 */ - volatile uint32_t ICDIPR19; /* ICDIPR19 */ - volatile uint32_t ICDIPR20; /* ICDIPR20 */ - volatile uint32_t ICDIPR21; /* ICDIPR21 */ - volatile uint32_t ICDIPR22; /* ICDIPR22 */ - volatile uint32_t ICDIPR23; /* ICDIPR23 */ - volatile uint32_t ICDIPR24; /* ICDIPR24 */ - volatile uint32_t ICDIPR25; /* ICDIPR25 */ - volatile uint32_t ICDIPR26; /* ICDIPR26 */ - volatile uint32_t ICDIPR27; /* ICDIPR27 */ - volatile uint32_t ICDIPR28; /* ICDIPR28 */ - volatile uint32_t ICDIPR29; /* ICDIPR29 */ - volatile uint32_t ICDIPR30; /* ICDIPR30 */ - volatile uint32_t ICDIPR31; /* ICDIPR31 */ - volatile uint32_t ICDIPR32; /* ICDIPR32 */ - volatile uint32_t ICDIPR33; /* ICDIPR33 */ - volatile uint32_t ICDIPR34; /* ICDIPR34 */ - volatile uint32_t ICDIPR35; /* ICDIPR35 */ - volatile uint32_t ICDIPR36; /* ICDIPR36 */ - volatile uint32_t ICDIPR37; /* ICDIPR37 */ - volatile uint32_t ICDIPR38; /* ICDIPR38 */ - volatile uint32_t ICDIPR39; /* ICDIPR39 */ - volatile uint32_t ICDIPR40; /* ICDIPR40 */ - volatile uint32_t ICDIPR41; /* ICDIPR41 */ - volatile uint32_t ICDIPR42; /* ICDIPR42 */ - volatile uint32_t ICDIPR43; /* ICDIPR43 */ - volatile uint32_t ICDIPR44; /* ICDIPR44 */ - volatile uint32_t ICDIPR45; /* ICDIPR45 */ - volatile uint32_t ICDIPR46; /* ICDIPR46 */ - volatile uint32_t ICDIPR47; /* ICDIPR47 */ - volatile uint32_t ICDIPR48; /* ICDIPR48 */ - volatile uint32_t ICDIPR49; /* ICDIPR49 */ - volatile uint32_t ICDIPR50; /* ICDIPR50 */ - volatile uint32_t ICDIPR51; /* ICDIPR51 */ - volatile uint32_t ICDIPR52; /* ICDIPR52 */ - volatile uint32_t ICDIPR53; /* ICDIPR53 */ - volatile uint32_t ICDIPR54; /* ICDIPR54 */ - volatile uint32_t ICDIPR55; /* ICDIPR55 */ - volatile uint32_t ICDIPR56; /* ICDIPR56 */ - volatile uint32_t ICDIPR57; /* ICDIPR57 */ - volatile uint32_t ICDIPR58; /* ICDIPR58 */ - volatile uint32_t ICDIPR59; /* ICDIPR59 */ - volatile uint32_t ICDIPR60; /* ICDIPR60 */ - volatile uint32_t ICDIPR61; /* ICDIPR61 */ - volatile uint32_t ICDIPR62; /* ICDIPR62 */ - volatile uint32_t ICDIPR63; /* ICDIPR63 */ - volatile uint32_t ICDIPR64; /* ICDIPR64 */ - volatile uint32_t ICDIPR65; /* ICDIPR65 */ - volatile uint32_t ICDIPR66; /* ICDIPR66 */ - volatile uint32_t ICDIPR67; /* ICDIPR67 */ - volatile uint32_t ICDIPR68; /* ICDIPR68 */ - volatile uint32_t ICDIPR69; /* ICDIPR69 */ - volatile uint32_t ICDIPR70; /* ICDIPR70 */ - volatile uint32_t ICDIPR71; /* ICDIPR71 */ - volatile uint32_t ICDIPR72; /* ICDIPR72 */ - volatile uint32_t ICDIPR73; /* ICDIPR73 */ - volatile uint32_t ICDIPR74; /* ICDIPR74 */ - volatile uint32_t ICDIPR75; /* ICDIPR75 */ - volatile uint32_t ICDIPR76; /* ICDIPR76 */ - volatile uint32_t ICDIPR77; /* ICDIPR77 */ - volatile uint32_t ICDIPR78; /* ICDIPR78 */ - volatile uint32_t ICDIPR79; /* ICDIPR79 */ - volatile uint32_t ICDIPR80; /* ICDIPR80 */ - volatile uint32_t ICDIPR81; /* ICDIPR81 */ - volatile uint32_t ICDIPR82; /* ICDIPR82 */ - volatile uint32_t ICDIPR83; /* ICDIPR83 */ - volatile uint32_t ICDIPR84; /* ICDIPR84 */ - volatile uint32_t ICDIPR85; /* ICDIPR85 */ - volatile uint32_t ICDIPR86; /* ICDIPR86 */ - volatile uint32_t ICDIPR87; /* ICDIPR87 */ - volatile uint32_t ICDIPR88; /* ICDIPR88 */ - volatile uint32_t ICDIPR89; /* ICDIPR89 */ - volatile uint32_t ICDIPR90; /* ICDIPR90 */ - volatile uint32_t ICDIPR91; /* ICDIPR91 */ - volatile uint32_t ICDIPR92; /* ICDIPR92 */ - volatile uint32_t ICDIPR93; /* ICDIPR93 */ - volatile uint32_t ICDIPR94; /* ICDIPR94 */ - volatile uint32_t ICDIPR95; /* ICDIPR95 */ - volatile uint32_t ICDIPR96; /* ICDIPR96 */ - volatile uint32_t ICDIPR97; /* ICDIPR97 */ - volatile uint32_t ICDIPR98; /* ICDIPR98 */ - volatile uint32_t ICDIPR99; /* ICDIPR99 */ - volatile uint32_t ICDIPR100; /* ICDIPR100 */ - volatile uint32_t ICDIPR101; /* ICDIPR101 */ - volatile uint32_t ICDIPR102; /* ICDIPR102 */ - volatile uint32_t ICDIPR103; /* ICDIPR103 */ - volatile uint32_t ICDIPR104; /* ICDIPR104 */ - volatile uint32_t ICDIPR105; /* ICDIPR105 */ - volatile uint32_t ICDIPR106; /* ICDIPR106 */ - volatile uint32_t ICDIPR107; /* ICDIPR107 */ - volatile uint32_t ICDIPR108; /* ICDIPR108 */ - volatile uint32_t ICDIPR109; /* ICDIPR109 */ - volatile uint32_t ICDIPR110; /* ICDIPR110 */ - volatile uint32_t ICDIPR111; /* ICDIPR111 */ - volatile uint32_t ICDIPR112; /* ICDIPR112 */ - volatile uint32_t ICDIPR113; /* ICDIPR113 */ - volatile uint32_t ICDIPR114; /* ICDIPR114 */ - volatile uint32_t ICDIPR115; /* ICDIPR115 */ - volatile uint32_t ICDIPR116; /* ICDIPR116 */ - volatile uint32_t ICDIPR117; /* ICDIPR117 */ - volatile uint32_t ICDIPR118; /* ICDIPR118 */ - volatile uint32_t ICDIPR119; /* ICDIPR119 */ - volatile uint32_t ICDIPR120; /* ICDIPR120 */ - volatile uint32_t ICDIPR121; /* ICDIPR121 */ - volatile uint32_t ICDIPR122; /* ICDIPR122 */ - volatile uint32_t ICDIPR123; /* ICDIPR123 */ - volatile uint32_t ICDIPR124; /* ICDIPR124 */ - volatile uint32_t ICDIPR125; /* ICDIPR125 */ - volatile uint32_t ICDIPR126; /* ICDIPR126 */ - volatile uint32_t ICDIPR127; /* ICDIPR127 */ - volatile uint32_t ICDIPR128; /* ICDIPR128 */ - volatile uint32_t ICDIPR129; /* ICDIPR129 */ - volatile uint32_t ICDIPR130; /* ICDIPR130 */ - volatile uint32_t ICDIPR131; /* ICDIPR131 */ - volatile uint32_t ICDIPR132; /* ICDIPR132 */ - volatile uint32_t ICDIPR133; /* ICDIPR133 */ - volatile uint32_t ICDIPR134; /* ICDIPR134 */ - volatile uint32_t ICDIPR135; /* ICDIPR135 */ - volatile uint32_t ICDIPR136; /* ICDIPR136 */ - volatile uint32_t ICDIPR137; /* ICDIPR137 */ - volatile uint32_t ICDIPR138; /* ICDIPR138 */ - volatile uint32_t ICDIPR139; /* ICDIPR139 */ - volatile uint32_t ICDIPR140; /* ICDIPR140 */ - volatile uint32_t ICDIPR141; /* ICDIPR141 */ - volatile uint32_t ICDIPR142; /* ICDIPR142 */ - volatile uint32_t ICDIPR143; /* ICDIPR143 */ - volatile uint32_t ICDIPR144; /* ICDIPR144 */ - volatile uint32_t ICDIPR145; /* ICDIPR145 */ - volatile uint32_t ICDIPR146; /* ICDIPR146 */ - volatile uint8_t dummy200[436]; /* */ - -/* #define INTC_ICDIPTR0_COUNT (147) */ - volatile uint32_t ICDIPTR0; /* ICDIPTR0 */ - volatile uint32_t ICDIPTR1; /* ICDIPTR1 */ - volatile uint32_t ICDIPTR2; /* ICDIPTR2 */ - volatile uint32_t ICDIPTR3; /* ICDIPTR3 */ - volatile uint32_t ICDIPTR4; /* ICDIPTR4 */ - volatile uint32_t ICDIPTR5; /* ICDIPTR5 */ - volatile uint32_t ICDIPTR6; /* ICDIPTR6 */ - volatile uint32_t ICDIPTR7; /* ICDIPTR7 */ - volatile uint32_t ICDIPTR8; /* ICDIPTR8 */ - volatile uint32_t ICDIPTR9; /* ICDIPTR9 */ - volatile uint32_t ICDIPTR10; /* ICDIPTR10 */ - volatile uint32_t ICDIPTR11; /* ICDIPTR11 */ - volatile uint32_t ICDIPTR12; /* ICDIPTR12 */ - volatile uint32_t ICDIPTR13; /* ICDIPTR13 */ - volatile uint32_t ICDIPTR14; /* ICDIPTR14 */ - volatile uint32_t ICDIPTR15; /* ICDIPTR15 */ - volatile uint32_t ICDIPTR16; /* ICDIPTR16 */ - volatile uint32_t ICDIPTR17; /* ICDIPTR17 */ - volatile uint32_t ICDIPTR18; /* ICDIPTR18 */ - volatile uint32_t ICDIPTR19; /* ICDIPTR19 */ - volatile uint32_t ICDIPTR20; /* ICDIPTR20 */ - volatile uint32_t ICDIPTR21; /* ICDIPTR21 */ - volatile uint32_t ICDIPTR22; /* ICDIPTR22 */ - volatile uint32_t ICDIPTR23; /* ICDIPTR23 */ - volatile uint32_t ICDIPTR24; /* ICDIPTR24 */ - volatile uint32_t ICDIPTR25; /* ICDIPTR25 */ - volatile uint32_t ICDIPTR26; /* ICDIPTR26 */ - volatile uint32_t ICDIPTR27; /* ICDIPTR27 */ - volatile uint32_t ICDIPTR28; /* ICDIPTR28 */ - volatile uint32_t ICDIPTR29; /* ICDIPTR29 */ - volatile uint32_t ICDIPTR30; /* ICDIPTR30 */ - volatile uint32_t ICDIPTR31; /* ICDIPTR31 */ - volatile uint32_t ICDIPTR32; /* ICDIPTR32 */ - volatile uint32_t ICDIPTR33; /* ICDIPTR33 */ - volatile uint32_t ICDIPTR34; /* ICDIPTR34 */ - volatile uint32_t ICDIPTR35; /* ICDIPTR35 */ - volatile uint32_t ICDIPTR36; /* ICDIPTR36 */ - volatile uint32_t ICDIPTR37; /* ICDIPTR37 */ - volatile uint32_t ICDIPTR38; /* ICDIPTR38 */ - volatile uint32_t ICDIPTR39; /* ICDIPTR39 */ - volatile uint32_t ICDIPTR40; /* ICDIPTR40 */ - volatile uint32_t ICDIPTR41; /* ICDIPTR41 */ - volatile uint32_t ICDIPTR42; /* ICDIPTR42 */ - volatile uint32_t ICDIPTR43; /* ICDIPTR43 */ - volatile uint32_t ICDIPTR44; /* ICDIPTR44 */ - volatile uint32_t ICDIPTR45; /* ICDIPTR45 */ - volatile uint32_t ICDIPTR46; /* ICDIPTR46 */ - volatile uint32_t ICDIPTR47; /* ICDIPTR47 */ - volatile uint32_t ICDIPTR48; /* ICDIPTR48 */ - volatile uint32_t ICDIPTR49; /* ICDIPTR49 */ - volatile uint32_t ICDIPTR50; /* ICDIPTR50 */ - volatile uint32_t ICDIPTR51; /* ICDIPTR51 */ - volatile uint32_t ICDIPTR52; /* ICDIPTR52 */ - volatile uint32_t ICDIPTR53; /* ICDIPTR53 */ - volatile uint32_t ICDIPTR54; /* ICDIPTR54 */ - volatile uint32_t ICDIPTR55; /* ICDIPTR55 */ - volatile uint32_t ICDIPTR56; /* ICDIPTR56 */ - volatile uint32_t ICDIPTR57; /* ICDIPTR57 */ - volatile uint32_t ICDIPTR58; /* ICDIPTR58 */ - volatile uint32_t ICDIPTR59; /* ICDIPTR59 */ - volatile uint32_t ICDIPTR60; /* ICDIPTR60 */ - volatile uint32_t ICDIPTR61; /* ICDIPTR61 */ - volatile uint32_t ICDIPTR62; /* ICDIPTR62 */ - volatile uint32_t ICDIPTR63; /* ICDIPTR63 */ - volatile uint32_t ICDIPTR64; /* ICDIPTR64 */ - volatile uint32_t ICDIPTR65; /* ICDIPTR65 */ - volatile uint32_t ICDIPTR66; /* ICDIPTR66 */ - volatile uint32_t ICDIPTR67; /* ICDIPTR67 */ - volatile uint32_t ICDIPTR68; /* ICDIPTR68 */ - volatile uint32_t ICDIPTR69; /* ICDIPTR69 */ - volatile uint32_t ICDIPTR70; /* ICDIPTR70 */ - volatile uint32_t ICDIPTR71; /* ICDIPTR71 */ - volatile uint32_t ICDIPTR72; /* ICDIPTR72 */ - volatile uint32_t ICDIPTR73; /* ICDIPTR73 */ - volatile uint32_t ICDIPTR74; /* ICDIPTR74 */ - volatile uint32_t ICDIPTR75; /* ICDIPTR75 */ - volatile uint32_t ICDIPTR76; /* ICDIPTR76 */ - volatile uint32_t ICDIPTR77; /* ICDIPTR77 */ - volatile uint32_t ICDIPTR78; /* ICDIPTR78 */ - volatile uint32_t ICDIPTR79; /* ICDIPTR79 */ - volatile uint32_t ICDIPTR80; /* ICDIPTR80 */ - volatile uint32_t ICDIPTR81; /* ICDIPTR81 */ - volatile uint32_t ICDIPTR82; /* ICDIPTR82 */ - volatile uint32_t ICDIPTR83; /* ICDIPTR83 */ - volatile uint32_t ICDIPTR84; /* ICDIPTR84 */ - volatile uint32_t ICDIPTR85; /* ICDIPTR85 */ - volatile uint32_t ICDIPTR86; /* ICDIPTR86 */ - volatile uint32_t ICDIPTR87; /* ICDIPTR87 */ - volatile uint32_t ICDIPTR88; /* ICDIPTR88 */ - volatile uint32_t ICDIPTR89; /* ICDIPTR89 */ - volatile uint32_t ICDIPTR90; /* ICDIPTR90 */ - volatile uint32_t ICDIPTR91; /* ICDIPTR91 */ - volatile uint32_t ICDIPTR92; /* ICDIPTR92 */ - volatile uint32_t ICDIPTR93; /* ICDIPTR93 */ - volatile uint32_t ICDIPTR94; /* ICDIPTR94 */ - volatile uint32_t ICDIPTR95; /* ICDIPTR95 */ - volatile uint32_t ICDIPTR96; /* ICDIPTR96 */ - volatile uint32_t ICDIPTR97; /* ICDIPTR97 */ - volatile uint32_t ICDIPTR98; /* ICDIPTR98 */ - volatile uint32_t ICDIPTR99; /* ICDIPTR99 */ - volatile uint32_t ICDIPTR100; /* ICDIPTR100 */ - volatile uint32_t ICDIPTR101; /* ICDIPTR101 */ - volatile uint32_t ICDIPTR102; /* ICDIPTR102 */ - volatile uint32_t ICDIPTR103; /* ICDIPTR103 */ - volatile uint32_t ICDIPTR104; /* ICDIPTR104 */ - volatile uint32_t ICDIPTR105; /* ICDIPTR105 */ - volatile uint32_t ICDIPTR106; /* ICDIPTR106 */ - volatile uint32_t ICDIPTR107; /* ICDIPTR107 */ - volatile uint32_t ICDIPTR108; /* ICDIPTR108 */ - volatile uint32_t ICDIPTR109; /* ICDIPTR109 */ - volatile uint32_t ICDIPTR110; /* ICDIPTR110 */ - volatile uint32_t ICDIPTR111; /* ICDIPTR111 */ - volatile uint32_t ICDIPTR112; /* ICDIPTR112 */ - volatile uint32_t ICDIPTR113; /* ICDIPTR113 */ - volatile uint32_t ICDIPTR114; /* ICDIPTR114 */ - volatile uint32_t ICDIPTR115; /* ICDIPTR115 */ - volatile uint32_t ICDIPTR116; /* ICDIPTR116 */ - volatile uint32_t ICDIPTR117; /* ICDIPTR117 */ - volatile uint32_t ICDIPTR118; /* ICDIPTR118 */ - volatile uint32_t ICDIPTR119; /* ICDIPTR119 */ - volatile uint32_t ICDIPTR120; /* ICDIPTR120 */ - volatile uint32_t ICDIPTR121; /* ICDIPTR121 */ - volatile uint32_t ICDIPTR122; /* ICDIPTR122 */ - volatile uint32_t ICDIPTR123; /* ICDIPTR123 */ - volatile uint32_t ICDIPTR124; /* ICDIPTR124 */ - volatile uint32_t ICDIPTR125; /* ICDIPTR125 */ - volatile uint32_t ICDIPTR126; /* ICDIPTR126 */ - volatile uint32_t ICDIPTR127; /* ICDIPTR127 */ - volatile uint32_t ICDIPTR128; /* ICDIPTR128 */ - volatile uint32_t ICDIPTR129; /* ICDIPTR129 */ - volatile uint32_t ICDIPTR130; /* ICDIPTR130 */ - volatile uint32_t ICDIPTR131; /* ICDIPTR131 */ - volatile uint32_t ICDIPTR132; /* ICDIPTR132 */ - volatile uint32_t ICDIPTR133; /* ICDIPTR133 */ - volatile uint32_t ICDIPTR134; /* ICDIPTR134 */ - volatile uint32_t ICDIPTR135; /* ICDIPTR135 */ - volatile uint32_t ICDIPTR136; /* ICDIPTR136 */ - volatile uint32_t ICDIPTR137; /* ICDIPTR137 */ - volatile uint32_t ICDIPTR138; /* ICDIPTR138 */ - volatile uint32_t ICDIPTR139; /* ICDIPTR139 */ - volatile uint32_t ICDIPTR140; /* ICDIPTR140 */ - volatile uint32_t ICDIPTR141; /* ICDIPTR141 */ - volatile uint32_t ICDIPTR142; /* ICDIPTR142 */ - volatile uint32_t ICDIPTR143; /* ICDIPTR143 */ - volatile uint32_t ICDIPTR144; /* ICDIPTR144 */ - volatile uint32_t ICDIPTR145; /* ICDIPTR145 */ - volatile uint32_t ICDIPTR146; /* ICDIPTR146 */ - volatile uint8_t dummy201[436]; /* */ - -/* #define INTC_ICDICFR0_COUNT (37) */ - volatile uint32_t ICDICFR0; /* ICDICFR0 */ - volatile uint32_t ICDICFR1; /* ICDICFR1 */ - volatile uint32_t ICDICFR2; /* ICDICFR2 */ - volatile uint32_t ICDICFR3; /* ICDICFR3 */ - volatile uint32_t ICDICFR4; /* ICDICFR4 */ - volatile uint32_t ICDICFR5; /* ICDICFR5 */ - volatile uint32_t ICDICFR6; /* ICDICFR6 */ - volatile uint32_t ICDICFR7; /* ICDICFR7 */ - volatile uint32_t ICDICFR8; /* ICDICFR8 */ - volatile uint32_t ICDICFR9; /* ICDICFR9 */ - volatile uint32_t ICDICFR10; /* ICDICFR10 */ - volatile uint32_t ICDICFR11; /* ICDICFR11 */ - volatile uint32_t ICDICFR12; /* ICDICFR12 */ - volatile uint32_t ICDICFR13; /* ICDICFR13 */ - volatile uint32_t ICDICFR14; /* ICDICFR14 */ - volatile uint32_t ICDICFR15; /* ICDICFR15 */ - volatile uint32_t ICDICFR16; /* ICDICFR16 */ - volatile uint32_t ICDICFR17; /* ICDICFR17 */ - volatile uint32_t ICDICFR18; /* ICDICFR18 */ - volatile uint32_t ICDICFR19; /* ICDICFR19 */ - volatile uint32_t ICDICFR20; /* ICDICFR20 */ - volatile uint32_t ICDICFR21; /* ICDICFR21 */ - volatile uint32_t ICDICFR22; /* ICDICFR22 */ - volatile uint32_t ICDICFR23; /* ICDICFR23 */ - volatile uint32_t ICDICFR24; /* ICDICFR24 */ - volatile uint32_t ICDICFR25; /* ICDICFR25 */ - volatile uint32_t ICDICFR26; /* ICDICFR26 */ - volatile uint32_t ICDICFR27; /* ICDICFR27 */ - volatile uint32_t ICDICFR28; /* ICDICFR28 */ - volatile uint32_t ICDICFR29; /* ICDICFR29 */ - volatile uint32_t ICDICFR30; /* ICDICFR30 */ - volatile uint32_t ICDICFR31; /* ICDICFR31 */ - volatile uint32_t ICDICFR32; /* ICDICFR32 */ - volatile uint32_t ICDICFR33; /* ICDICFR33 */ - volatile uint32_t ICDICFR34; /* ICDICFR34 */ - volatile uint32_t ICDICFR35; /* ICDICFR35 */ - volatile uint32_t ICDICFR36; /* ICDICFR36 */ - volatile uint8_t dummy202[108]; /* */ - volatile uint32_t PPI_STATUS; /* PPI_STATUS */ - -/* #define INTC_SPI_STATUS0_COUNT (17) */ - volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */ - volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */ - volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */ - volatile uint32_t SPI_STATUS3; /* SPI_STATUS3 */ - volatile uint32_t SPI_STATUS4; /* SPI_STATUS4 */ - volatile uint32_t SPI_STATUS5; /* SPI_STATUS5 */ - volatile uint32_t SPI_STATUS6; /* SPI_STATUS6 */ - volatile uint32_t SPI_STATUS7; /* SPI_STATUS7 */ - volatile uint32_t SPI_STATUS8; /* SPI_STATUS8 */ - volatile uint32_t SPI_STATUS9; /* SPI_STATUS9 */ - volatile uint32_t SPI_STATUS10; /* SPI_STATUS10 */ - volatile uint32_t SPI_STATUS11; /* SPI_STATUS11 */ - volatile uint32_t SPI_STATUS12; /* SPI_STATUS12 */ - volatile uint32_t SPI_STATUS13; /* SPI_STATUS13 */ - volatile uint32_t SPI_STATUS14; /* SPI_STATUS14 */ - volatile uint32_t SPI_STATUS15; /* SPI_STATUS15 */ - volatile uint32_t SPI_STATUS16; /* SPI_STATUS16 */ - volatile uint8_t dummy203[440]; /* */ - volatile uint32_t ICDSGIR; /* ICDSGIR */ - volatile uint8_t dummy204[252]; /* */ - volatile uint32_t ICCICR; /* ICCICR */ - volatile uint32_t ICCPMR; /* ICCPMR */ - volatile uint32_t ICCBPR; /* ICCBPR */ - volatile uint32_t ICCIAR; /* ICCIAR */ - volatile uint32_t ICCEOIR; /* ICCEOIR */ - volatile uint32_t ICCRPR; /* ICCRPR */ - volatile uint32_t ICCHPIR; /* ICCHPIR */ - volatile uint32_t ICCABPR; /* ICCABPR */ - volatile uint8_t dummy205[220]; /* */ - volatile uint32_t ICCIIDR; /* ICCIIDR */ - volatile uint8_t dummy206[350148352]; /* */ - volatile uint16_t ICR0; /* ICR0 */ - volatile uint16_t ICR1; /* ICR1 */ - volatile uint16_t IRQRR; /* IRQRR */ -} r_io_intc_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h deleted file mode 100644 index 434b9319330..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h +++ /dev/null @@ -1,118 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : iodefine_typedef.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef IODEFINE_TYPEDEF_H -#define IODEFINE_TYPEDEF_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -/* Shared types and macros for iodefine.h */ - -/*********************************************************************** -* Macro: IODEFINE_H_VERSION -************************************************************************/ -#define IODEFINE_H_VERSION (200) - - -/*********************************************************************** -* Enum: iodefine_byte_select_t -* -* R_IO_L - Low 16bit or Low 8 bit -* R_IO_H - High 16bit or Low 8 bit -* R_IO_LL - Low 8 bit -* R_IO_LH - Middle Low 8 bit -* R_IO_HL - Middle High 8 bit -* R_IO_HH - High 8 bit -************************************************************************/ -typedef enum iodefine_byte_select_t -{ - R_IO_L = 0, R_IO_H = 1, - R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3, - L = 0, H = 1, - LL= 0, LH = 1, HL = 2, HH = 3 -} iodefine_byte_select_t; - - -/*********************************************************************** -* Type: iodefine_reg32_t -* 32/16/8 bit access register -* -* - Padding : sizeof(iodefine_reg32_t) == 4 -* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 -* &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 -* - Endian : Independent (Same as CPU endian as register endian) -* - Bit-Order : Independent -************************************************************************/ -typedef union iodefine_reg32_t -{ - volatile uint32_t UINT32; /* 32-bit Access */ - volatile uint16_t UINT16[2]; /* 16-bit Access */ - volatile uint8_t UINT8[4]; /* 8-bit Access */ -} iodefine_reg32_t; - - -/*********************************************************************** -* Type: iodefine_reg32_16_t -* 32/16 bit access register -* -* - Padding : sizeof(iodefine_reg32_16_t) == 4 -* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 -* - Endian : Independent (Same as CPU endian as register endian) -* - Bit-Order : Independent -************************************************************************/ -typedef union iodefine_reg32_16_t -{ - volatile uint32_t UINT32; /* 32-bit Access */ - volatile uint16_t UINT16[2]; /* 16-bit Access */ -} iodefine_reg32_16_t; - - -/*********************************************************************** -* Type: iodefine_reg16_8_t -* 16/8 bit access register -* -* - Padding : sizeof(iodefine_reg16_8_t) == 2 -* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 -* - Endian : Independent (Same as CPU endian as register endian) -* - Bit-Order : Independent -************************************************************************/ -typedef union iodefine_reg16_8_t -{ - volatile uint16_t UINT16; /* 16-bit Access */ - volatile uint8_t UINT8[2]; /* 8-bit Access */ -} iodefine_reg16_8_t; - - -/* End of shared types and macros for iodefine.h */ -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h deleted file mode 100644 index eb5d8421389..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : irda_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef IRDA_IODEFINE_H -#define IRDA_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */ - - -#define IRDAIRCR (IRDA.IRCR) - - -typedef struct st_irda -{ - /* IRDA */ - volatile uint8_t IRCR; /* IRCR */ -} r_io_irda_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h deleted file mode 100644 index de1db5846aa..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h +++ /dev/null @@ -1,197 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : jcu_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef JCU_IODEFINE_H -#define JCU_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ - - -/* Start of channel array defines of JCU */ - -/* Channel array defines of JCU_JCQTBL0 */ -/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ -#define JCU_JCQTBL0_COUNT (4) -#define JCU_JCQTBL0_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ -#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ -#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ -#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ - -/* End of channel array defines of JCU */ - - -#define JCUJCMOD (JCU.JCMOD) -#define JCUJCCMD (JCU.JCCMD) -#define JCUJCQTN (JCU.JCQTN) -#define JCUJCHTN (JCU.JCHTN) -#define JCUJCDRIU (JCU.JCDRIU) -#define JCUJCDRID (JCU.JCDRID) -#define JCUJCVSZU (JCU.JCVSZU) -#define JCUJCVSZD (JCU.JCVSZD) -#define JCUJCHSZU (JCU.JCHSZU) -#define JCUJCHSZD (JCU.JCHSZD) -#define JCUJCDTCU (JCU.JCDTCU) -#define JCUJCDTCM (JCU.JCDTCM) -#define JCUJCDTCD (JCU.JCDTCD) -#define JCUJINTE0 (JCU.JINTE0) -#define JCUJINTS0 (JCU.JINTS0) -#define JCUJCDERR (JCU.JCDERR) -#define JCUJCRST (JCU.JCRST) -#define JCUJIFECNT (JCU.JIFECNT) -#define JCUJIFESA (JCU.JIFESA) -#define JCUJIFESOFST (JCU.JIFESOFST) -#define JCUJIFEDA (JCU.JIFEDA) -#define JCUJIFESLC (JCU.JIFESLC) -#define JCUJIFEDDC (JCU.JIFEDDC) -#define JCUJIFDCNT (JCU.JIFDCNT) -#define JCUJIFDSA (JCU.JIFDSA) -#define JCUJIFDDOFST (JCU.JIFDDOFST) -#define JCUJIFDDA (JCU.JIFDDA) -#define JCUJIFDSDC (JCU.JIFDSDC) -#define JCUJIFDDLC (JCU.JIFDDLC) -#define JCUJIFDADT (JCU.JIFDADT) -#define JCUJINTE1 (JCU.JINTE1) -#define JCUJINTS1 (JCU.JINTS1) -#define JCUJIFESVSZ (JCU.JIFESVSZ) -#define JCUJIFESHSZ (JCU.JIFESHSZ) -#define JCUJCQTBL0 (JCU.JCQTBL0) -#define JCUJCQTBL1 (JCU.JCQTBL1) -#define JCUJCQTBL2 (JCU.JCQTBL2) -#define JCUJCQTBL3 (JCU.JCQTBL3) -#define JCUJCHTBD0 (JCU.JCHTBD0) -#define JCUJCHTBA0 (JCU.JCHTBA0) -#define JCUJCHTBD1 (JCU.JCHTBD1) -#define JCUJCHTBA1 (JCU.JCHTBA1) - - -typedef struct st_jcu -{ - /* JCU */ - volatile uint8_t JCMOD; /* JCMOD */ - volatile uint8_t JCCMD; /* JCCMD */ - volatile uint8_t dummy145[1]; /* */ - volatile uint8_t JCQTN; /* JCQTN */ - volatile uint8_t JCHTN; /* JCHTN */ - volatile uint8_t JCDRIU; /* JCDRIU */ - volatile uint8_t JCDRID; /* JCDRID */ - volatile uint8_t JCVSZU; /* JCVSZU */ - volatile uint8_t JCVSZD; /* JCVSZD */ - volatile uint8_t JCHSZU; /* JCHSZU */ - volatile uint8_t JCHSZD; /* JCHSZD */ - volatile uint8_t JCDTCU; /* JCDTCU */ - volatile uint8_t JCDTCM; /* JCDTCM */ - volatile uint8_t JCDTCD; /* JCDTCD */ - volatile uint8_t JINTE0; /* JINTE0 */ - volatile uint8_t JINTS0; /* JINTS0 */ - volatile uint8_t JCDERR; /* JCDERR */ - volatile uint8_t JCRST; /* JCRST */ - volatile uint8_t dummy146[46]; /* */ - volatile uint32_t JIFECNT; /* JIFECNT */ - volatile uint32_t JIFESA; /* JIFESA */ - volatile uint32_t JIFESOFST; /* JIFESOFST */ - volatile uint32_t JIFEDA; /* JIFEDA */ - volatile uint32_t JIFESLC; /* JIFESLC */ - volatile uint32_t JIFEDDC; /* JIFEDDC */ - volatile uint32_t JIFDCNT; /* JIFDCNT */ - volatile uint32_t JIFDSA; /* JIFDSA */ - volatile uint32_t JIFDDOFST; /* JIFDDOFST */ - volatile uint32_t JIFDDA; /* JIFDDA */ - volatile uint32_t JIFDSDC; /* JIFDSDC */ - volatile uint32_t JIFDDLC; /* JIFDDLC */ - volatile uint32_t JIFDADT; /* JIFDADT */ - volatile uint8_t dummy147[24]; /* */ - volatile uint32_t JINTE1; /* JINTE1 */ - volatile uint32_t JINTS1; /* JINTS1 */ - volatile uint32_t JIFESVSZ; /* JIFESVSZ */ - volatile uint32_t JIFESHSZ; /* JIFESHSZ */ - volatile uint8_t dummy148[100]; /* */ - -/* start of struct st_jcu_from_jcqtbl0 */ - volatile uint8_t JCQTBL0; /* JCQTBL0 */ - volatile uint8_t dummy149[63]; /* */ - -/* end of struct st_jcu_from_jcqtbl0 */ - -/* start of struct st_jcu_from_jcqtbl0 */ - volatile uint8_t JCQTBL1; /* JCQTBL1 */ - volatile uint8_t dummy150[63]; /* */ - -/* end of struct st_jcu_from_jcqtbl0 */ - -/* start of struct st_jcu_from_jcqtbl0 */ - volatile uint8_t JCQTBL2; /* JCQTBL2 */ - volatile uint8_t dummy151[63]; /* */ - -/* end of struct st_jcu_from_jcqtbl0 */ - -/* start of struct st_jcu_from_jcqtbl0 */ - volatile uint8_t JCQTBL3; /* JCQTBL3 */ - volatile uint8_t dummy152[63]; /* */ - -/* end of struct st_jcu_from_jcqtbl0 */ - volatile uint8_t JCHTBD0; /* JCHTBD0 */ - volatile uint8_t dummy153[31]; /* */ - volatile uint8_t JCHTBA0; /* JCHTBA0 */ - volatile uint8_t dummy154[223]; /* */ - volatile uint8_t JCHTBD1; /* JCHTBD1 */ - volatile uint8_t dummy155[31]; /* */ - volatile uint8_t JCHTBA1; /* JCHTBA1 */ -} r_io_jcu_t; - - -typedef struct st_jcu_from_jcqtbl0 -{ - - volatile uint8_t JCQTBL0; /* JCQTBL0 */ - volatile uint8_t dummy1[63]; /* */ -} r_io_jcu_from_jcqtbl0_t; - - -/* Channel array defines of JCU (2)*/ -#ifdef DECLARE_JCU_JCQTBL0_CHANNELS -volatile struct st_jcu_from_jcqtbl0* JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - JCU_JCQTBL0_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_JCU_JCQTBL0_CHANNELS */ -/* End of channel array defines of JCU (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h deleted file mode 100644 index 76604a953ff..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h +++ /dev/null @@ -1,231 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : l2c_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef L2C_IODEFINE_H -#define L2C_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ - - -/* Start of channel array defines of L2C */ - -/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ -/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ -#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8) -#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ -#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ -#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ -#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ -#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ -#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ -#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ -#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ - -/* End of channel array defines of L2C */ - - -#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID) -#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE) -#define L2CREG1_CONTROL (L2C.REG1_CONTROL) -#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL) -#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL) -#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL) -#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL) -#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG) -#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG) -#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1) -#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0) -#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK) -#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS) -#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS) -#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR) -#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC) -#define L2CREG7_INV_PA (L2C.REG7_INV_PA) -#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY) -#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA) -#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX) -#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY) -#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA) -#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX) -#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY) -#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0) -#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0) -#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1) -#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1) -#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2) -#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2) -#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3) -#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3) -#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4) -#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4) -#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5) -#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5) -#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6) -#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6) -#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7) -#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7) -#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN) -#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY) -#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START) -#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END) -#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL) -#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL) -#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL) - - -typedef struct st_l2c -{ - /* L2C */ - volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */ - volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */ - volatile uint8_t dummy8[248]; /* */ - volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */ - volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */ - volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */ - volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */ - volatile uint8_t dummy9[240]; /* */ - volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */ - volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */ - volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */ - volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */ - volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */ - volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */ - volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */ - volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */ - volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */ - volatile uint8_t dummy10[1292]; /* */ - volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */ - volatile uint8_t dummy11[60]; /* */ - volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */ - volatile uint8_t dummy12[8]; /* */ - volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */ - volatile uint8_t dummy13[48]; /* */ - volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */ - volatile uint8_t dummy14[4]; /* */ - volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */ - volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */ - volatile uint8_t dummy15[48]; /* */ - volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */ - volatile uint8_t dummy16[4]; /* */ - volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */ - volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */ - volatile uint8_t dummy17[256]; /* */ - -/* start of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ - volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ - -/* end of struct st_l2c_from_reg9_d_lockdown0 */ - -/* start of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */ - volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */ - -/* end of struct st_l2c_from_reg9_d_lockdown0 */ - -/* start of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */ - volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */ - -/* end of struct st_l2c_from_reg9_d_lockdown0 */ - -/* start of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */ - volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */ - -/* end of struct st_l2c_from_reg9_d_lockdown0 */ - -/* start of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */ - volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */ - -/* end of struct st_l2c_from_reg9_d_lockdown0 */ - -/* start of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */ - volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */ - -/* end of struct st_l2c_from_reg9_d_lockdown0 */ - -/* start of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */ - volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */ - -/* end of struct st_l2c_from_reg9_d_lockdown0 */ - -/* start of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */ - volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */ - -/* end of struct st_l2c_from_reg9_d_lockdown0 */ - volatile uint8_t dummy18[16]; /* */ - volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */ - volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */ - volatile uint8_t dummy19[680]; /* */ - volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */ - volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */ - volatile uint8_t dummy20[824]; /* */ - volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */ - volatile uint8_t dummy21[28]; /* */ - volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */ - volatile uint8_t dummy22[28]; /* */ - volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */ -} r_io_l2c_t; - - -typedef struct st_l2c_from_reg9_d_lockdown0 -{ - - volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ - volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ -} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */; - - -/* Channel array defines of L2C (2)*/ -#ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS -volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */ -/* End of channel array defines of L2C (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h deleted file mode 100644 index 6c0fcc08774..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h +++ /dev/null @@ -1,161 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : lin_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef LIN_IODEFINE_H -#define LIN_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ -#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ - - -/* Start of channel array defines of LIN */ - -/* Channel array defines of LIN */ -/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ -#define LIN_COUNT (2) -#define LIN_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &LIN0, &LIN1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of LIN */ - - -#define LIN0RLN30LWBR (LIN0.RLN3nLWBR) -#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0) -#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1) -#define LIN0RLN30LSTC (LIN0.RLN3nLSTC) -#define LIN0RLN30LMD (LIN0.RLN3nLMD) -#define LIN0RLN30LBFC (LIN0.RLN3nLBFC) -#define LIN0RLN30LSC (LIN0.RLN3nLSC) -#define LIN0RLN30LWUP (LIN0.RLN3nLWUP) -#define LIN0RLN30LIE (LIN0.RLN3nLIE) -#define LIN0RLN30LEDE (LIN0.RLN3nLEDE) -#define LIN0RLN30LCUC (LIN0.RLN3nLCUC) -#define LIN0RLN30LTRC (LIN0.RLN3nLTRC) -#define LIN0RLN30LMST (LIN0.RLN3nLMST) -#define LIN0RLN30LST (LIN0.RLN3nLST) -#define LIN0RLN30LEST (LIN0.RLN3nLEST) -#define LIN0RLN30LDFC (LIN0.RLN3nLDFC) -#define LIN0RLN30LIDB (LIN0.RLN3nLIDB) -#define LIN0RLN30LCBR (LIN0.RLN3nLCBR) -#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1) -#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2) -#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3) -#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4) -#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5) -#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6) -#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7) -#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8) -#define LIN1RLN31LWBR (LIN1.RLN3nLWBR) -#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0) -#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1) -#define LIN1RLN31LSTC (LIN1.RLN3nLSTC) -#define LIN1RLN31LMD (LIN1.RLN3nLMD) -#define LIN1RLN31LBFC (LIN1.RLN3nLBFC) -#define LIN1RLN31LSC (LIN1.RLN3nLSC) -#define LIN1RLN31LWUP (LIN1.RLN3nLWUP) -#define LIN1RLN31LIE (LIN1.RLN3nLIE) -#define LIN1RLN31LEDE (LIN1.RLN3nLEDE) -#define LIN1RLN31LCUC (LIN1.RLN3nLCUC) -#define LIN1RLN31LTRC (LIN1.RLN3nLTRC) -#define LIN1RLN31LMST (LIN1.RLN3nLMST) -#define LIN1RLN31LST (LIN1.RLN3nLST) -#define LIN1RLN31LEST (LIN1.RLN3nLEST) -#define LIN1RLN31LDFC (LIN1.RLN3nLDFC) -#define LIN1RLN31LIDB (LIN1.RLN3nLIDB) -#define LIN1RLN31LCBR (LIN1.RLN3nLCBR) -#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1) -#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2) -#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3) -#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4) -#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5) -#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6) -#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7) -#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8) - -#define LIN_LDBn_COUNT (8) - - -typedef struct st_lin -{ - /* LIN */ - volatile uint8_t dummy1[1]; /* */ - volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */ - volatile uint8_t RLN3nLBRP0; /* RLN3nLBRP0 */ - volatile uint8_t RLN3nLBRP1; /* RLN3nLBRP1 */ - volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */ - volatile uint8_t dummy2[3]; /* */ - volatile uint8_t RLN3nLMD; /* RLN3nLMD */ - volatile uint8_t RLN3nLBFC; /* RLN3nLBFC */ - volatile uint8_t RLN3nLSC; /* RLN3nLSC */ - volatile uint8_t RLN3nLWUP; /* RLN3nLWUP */ - volatile uint8_t RLN3nLIE; /* RLN3nLIE */ - volatile uint8_t RLN3nLEDE; /* RLN3nLEDE */ - volatile uint8_t RLN3nLCUC; /* RLN3nLCUC */ - volatile uint8_t dummy3[1]; /* */ - volatile uint8_t RLN3nLTRC; /* RLN3nLTRC */ - volatile uint8_t RLN3nLMST; /* RLN3nLMST */ - volatile uint8_t RLN3nLST; /* RLN3nLST */ - volatile uint8_t RLN3nLEST; /* RLN3nLEST */ - volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */ - volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */ - volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */ - volatile uint8_t dummy4[1]; /* */ - -/* #define LIN_LDBn_COUNT (8) */ - volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */ - volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */ - volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */ - volatile uint8_t RLN3nLDBR4; /* RLN3nLDBR4 */ - volatile uint8_t RLN3nLDBR5; /* RLN3nLDBR5 */ - volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */ - volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */ - volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */ -} r_io_lin_t; - - -/* Channel array defines of LIN (2)*/ -#ifdef DECLARE_LIN_CHANNELS -volatile struct st_lin* LIN[ LIN_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - LIN_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_LIN_CHANNELS */ -/* End of channel array defines of LIN (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h deleted file mode 100644 index c32caa6952f..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h +++ /dev/null @@ -1,63 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : lvds_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef LVDS_IODEFINE_H -#define LVDS_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ - - -#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE) -#define LVDSLVDSFCL (LVDS.LVDSFCL) -#define LVDSLCLKSELR (LVDS.LCLKSELR) -#define LVDSLPLLSETR (LVDS.LPLLSETR) -#define LVDSLPHYACC (LVDS.LPHYACC) - - -typedef struct st_lvds -{ - /* LVDS */ - volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */ - volatile uint32_t LVDSFCL; /* LVDSFCL */ - volatile uint8_t dummy608[24]; /* */ - volatile uint32_t LCLKSELR; /* LCLKSELR */ - volatile uint32_t LPLLSETR; /* LPLLSETR */ - volatile uint8_t dummy609[4]; /* */ - volatile uint32_t LPHYACC; /* LPHYACC */ -} r_io_lvds_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h deleted file mode 100644 index d06c7670891..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h +++ /dev/null @@ -1,579 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : mlb_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef MLB_IODEFINE_H -#define MLB_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */ - - -/* Start of channel array defines of MLB */ - -/* Channel array defines of MLB_FROM_CECR0_ARRAY */ -/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */ -#define MLB_FROM_CECR0_ARRAY_COUNT (31) -#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \ - &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \ - &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \ - &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */ -#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */ -#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */ -#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */ -#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */ -#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */ -#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */ -#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */ -#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */ -#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */ -#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */ -#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */ -#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */ -#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */ -#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */ -#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */ -#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */ -#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */ -#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */ -#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */ -#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */ -#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */ -#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */ -#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */ -#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */ -#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */ -#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */ -#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */ -#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */ -#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */ -#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */ - -/* End of channel array defines of MLB */ - - -#define MLBDCCR (MLB.DCCR) -#define MLBSSCR (MLB.SSCR) -#define MLBSDCR (MLB.SDCR) -#define MLBSMCR (MLB.SMCR) -#define MLBVCCR (MLB.VCCR) -#define MLBSBCR (MLB.SBCR) -#define MLBABCR (MLB.ABCR) -#define MLBCBCR (MLB.CBCR) -#define MLBIBCR (MLB.IBCR) -#define MLBCICR (MLB.CICR) -#define MLBCECR0 (MLB.CECR0) -#define MLBCSCR0 (MLB.CSCR0) -#define MLBCCBCR0 (MLB.CCBCR0) -#define MLBCNBCR0 (MLB.CNBCR0) -#define MLBCECR1 (MLB.CECR1) -#define MLBCSCR1 (MLB.CSCR1) -#define MLBCCBCR1 (MLB.CCBCR1) -#define MLBCNBCR1 (MLB.CNBCR1) -#define MLBCECR2 (MLB.CECR2) -#define MLBCSCR2 (MLB.CSCR2) -#define MLBCCBCR2 (MLB.CCBCR2) -#define MLBCNBCR2 (MLB.CNBCR2) -#define MLBCECR3 (MLB.CECR3) -#define MLBCSCR3 (MLB.CSCR3) -#define MLBCCBCR3 (MLB.CCBCR3) -#define MLBCNBCR3 (MLB.CNBCR3) -#define MLBCECR4 (MLB.CECR4) -#define MLBCSCR4 (MLB.CSCR4) -#define MLBCCBCR4 (MLB.CCBCR4) -#define MLBCNBCR4 (MLB.CNBCR4) -#define MLBCECR5 (MLB.CECR5) -#define MLBCSCR5 (MLB.CSCR5) -#define MLBCCBCR5 (MLB.CCBCR5) -#define MLBCNBCR5 (MLB.CNBCR5) -#define MLBCECR6 (MLB.CECR6) -#define MLBCSCR6 (MLB.CSCR6) -#define MLBCCBCR6 (MLB.CCBCR6) -#define MLBCNBCR6 (MLB.CNBCR6) -#define MLBCECR7 (MLB.CECR7) -#define MLBCSCR7 (MLB.CSCR7) -#define MLBCCBCR7 (MLB.CCBCR7) -#define MLBCNBCR7 (MLB.CNBCR7) -#define MLBCECR8 (MLB.CECR8) -#define MLBCSCR8 (MLB.CSCR8) -#define MLBCCBCR8 (MLB.CCBCR8) -#define MLBCNBCR8 (MLB.CNBCR8) -#define MLBCECR9 (MLB.CECR9) -#define MLBCSCR9 (MLB.CSCR9) -#define MLBCCBCR9 (MLB.CCBCR9) -#define MLBCNBCR9 (MLB.CNBCR9) -#define MLBCECR10 (MLB.CECR10) -#define MLBCSCR10 (MLB.CSCR10) -#define MLBCCBCR10 (MLB.CCBCR10) -#define MLBCNBCR10 (MLB.CNBCR10) -#define MLBCECR11 (MLB.CECR11) -#define MLBCSCR11 (MLB.CSCR11) -#define MLBCCBCR11 (MLB.CCBCR11) -#define MLBCNBCR11 (MLB.CNBCR11) -#define MLBCECR12 (MLB.CECR12) -#define MLBCSCR12 (MLB.CSCR12) -#define MLBCCBCR12 (MLB.CCBCR12) -#define MLBCNBCR12 (MLB.CNBCR12) -#define MLBCECR13 (MLB.CECR13) -#define MLBCSCR13 (MLB.CSCR13) -#define MLBCCBCR13 (MLB.CCBCR13) -#define MLBCNBCR13 (MLB.CNBCR13) -#define MLBCECR14 (MLB.CECR14) -#define MLBCSCR14 (MLB.CSCR14) -#define MLBCCBCR14 (MLB.CCBCR14) -#define MLBCNBCR14 (MLB.CNBCR14) -#define MLBCECR15 (MLB.CECR15) -#define MLBCSCR15 (MLB.CSCR15) -#define MLBCCBCR15 (MLB.CCBCR15) -#define MLBCNBCR15 (MLB.CNBCR15) -#define MLBCECR16 (MLB.CECR16) -#define MLBCSCR16 (MLB.CSCR16) -#define MLBCCBCR16 (MLB.CCBCR16) -#define MLBCNBCR16 (MLB.CNBCR16) -#define MLBCECR17 (MLB.CECR17) -#define MLBCSCR17 (MLB.CSCR17) -#define MLBCCBCR17 (MLB.CCBCR17) -#define MLBCNBCR17 (MLB.CNBCR17) -#define MLBCECR18 (MLB.CECR18) -#define MLBCSCR18 (MLB.CSCR18) -#define MLBCCBCR18 (MLB.CCBCR18) -#define MLBCNBCR18 (MLB.CNBCR18) -#define MLBCECR19 (MLB.CECR19) -#define MLBCSCR19 (MLB.CSCR19) -#define MLBCCBCR19 (MLB.CCBCR19) -#define MLBCNBCR19 (MLB.CNBCR19) -#define MLBCECR20 (MLB.CECR20) -#define MLBCSCR20 (MLB.CSCR20) -#define MLBCCBCR20 (MLB.CCBCR20) -#define MLBCNBCR20 (MLB.CNBCR20) -#define MLBCECR21 (MLB.CECR21) -#define MLBCSCR21 (MLB.CSCR21) -#define MLBCCBCR21 (MLB.CCBCR21) -#define MLBCNBCR21 (MLB.CNBCR21) -#define MLBCECR22 (MLB.CECR22) -#define MLBCSCR22 (MLB.CSCR22) -#define MLBCCBCR22 (MLB.CCBCR22) -#define MLBCNBCR22 (MLB.CNBCR22) -#define MLBCECR23 (MLB.CECR23) -#define MLBCSCR23 (MLB.CSCR23) -#define MLBCCBCR23 (MLB.CCBCR23) -#define MLBCNBCR23 (MLB.CNBCR23) -#define MLBCECR24 (MLB.CECR24) -#define MLBCSCR24 (MLB.CSCR24) -#define MLBCCBCR24 (MLB.CCBCR24) -#define MLBCNBCR24 (MLB.CNBCR24) -#define MLBCECR25 (MLB.CECR25) -#define MLBCSCR25 (MLB.CSCR25) -#define MLBCCBCR25 (MLB.CCBCR25) -#define MLBCNBCR25 (MLB.CNBCR25) -#define MLBCECR26 (MLB.CECR26) -#define MLBCSCR26 (MLB.CSCR26) -#define MLBCCBCR26 (MLB.CCBCR26) -#define MLBCNBCR26 (MLB.CNBCR26) -#define MLBCECR27 (MLB.CECR27) -#define MLBCSCR27 (MLB.CSCR27) -#define MLBCCBCR27 (MLB.CCBCR27) -#define MLBCNBCR27 (MLB.CNBCR27) -#define MLBCECR28 (MLB.CECR28) -#define MLBCSCR28 (MLB.CSCR28) -#define MLBCCBCR28 (MLB.CCBCR28) -#define MLBCNBCR28 (MLB.CNBCR28) -#define MLBCECR29 (MLB.CECR29) -#define MLBCSCR29 (MLB.CSCR29) -#define MLBCCBCR29 (MLB.CCBCR29) -#define MLBCNBCR29 (MLB.CNBCR29) -#define MLBCECR30 (MLB.CECR30) -#define MLBCSCR30 (MLB.CSCR30) -#define MLBCCBCR30 (MLB.CCBCR30) -#define MLBCNBCR30 (MLB.CNBCR30) -#define MLBLCBCR0 (MLB.LCBCR0) -#define MLBLCBCR1 (MLB.LCBCR1) -#define MLBLCBCR2 (MLB.LCBCR2) -#define MLBLCBCR3 (MLB.LCBCR3) -#define MLBLCBCR4 (MLB.LCBCR4) -#define MLBLCBCR5 (MLB.LCBCR5) -#define MLBLCBCR6 (MLB.LCBCR6) -#define MLBLCBCR7 (MLB.LCBCR7) -#define MLBLCBCR8 (MLB.LCBCR8) -#define MLBLCBCR9 (MLB.LCBCR9) -#define MLBLCBCR10 (MLB.LCBCR10) -#define MLBLCBCR11 (MLB.LCBCR11) -#define MLBLCBCR12 (MLB.LCBCR12) -#define MLBLCBCR13 (MLB.LCBCR13) -#define MLBLCBCR14 (MLB.LCBCR14) -#define MLBLCBCR15 (MLB.LCBCR15) -#define MLBLCBCR16 (MLB.LCBCR16) -#define MLBLCBCR17 (MLB.LCBCR17) -#define MLBLCBCR18 (MLB.LCBCR18) -#define MLBLCBCR19 (MLB.LCBCR19) -#define MLBLCBCR20 (MLB.LCBCR20) -#define MLBLCBCR21 (MLB.LCBCR21) -#define MLBLCBCR22 (MLB.LCBCR22) -#define MLBLCBCR23 (MLB.LCBCR23) -#define MLBLCBCR24 (MLB.LCBCR24) -#define MLBLCBCR25 (MLB.LCBCR25) -#define MLBLCBCR26 (MLB.LCBCR26) -#define MLBLCBCR27 (MLB.LCBCR27) -#define MLBLCBCR28 (MLB.LCBCR28) -#define MLBLCBCR29 (MLB.LCBCR29) -#define MLBLCBCR30 (MLB.LCBCR30) - -#define MLB_LCBCR0_COUNT (31) - - -typedef struct st_mlb -{ - /* MLB */ - volatile uint32_t DCCR; /* DCCR */ - volatile uint32_t SSCR; /* SSCR */ - volatile uint32_t SDCR; /* SDCR */ - volatile uint32_t SMCR; /* SMCR */ - volatile uint8_t dummy156[12]; /* */ - volatile uint32_t VCCR; /* VCCR */ - volatile uint32_t SBCR; /* SBCR */ - volatile uint32_t ABCR; /* ABCR */ - volatile uint32_t CBCR; /* CBCR */ - volatile uint32_t IBCR; /* IBCR */ - volatile uint32_t CICR; /* CICR */ - volatile uint8_t dummy157[12]; /* */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR0; /* CECR0 */ - volatile uint32_t CSCR0; /* CSCR0 */ - volatile uint32_t CCBCR0; /* CCBCR0 */ - volatile uint32_t CNBCR0; /* CNBCR0 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR1; /* CECR1 */ - volatile uint32_t CSCR1; /* CSCR1 */ - volatile uint32_t CCBCR1; /* CCBCR1 */ - volatile uint32_t CNBCR1; /* CNBCR1 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR2; /* CECR2 */ - volatile uint32_t CSCR2; /* CSCR2 */ - volatile uint32_t CCBCR2; /* CCBCR2 */ - volatile uint32_t CNBCR2; /* CNBCR2 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR3; /* CECR3 */ - volatile uint32_t CSCR3; /* CSCR3 */ - volatile uint32_t CCBCR3; /* CCBCR3 */ - volatile uint32_t CNBCR3; /* CNBCR3 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR4; /* CECR4 */ - volatile uint32_t CSCR4; /* CSCR4 */ - volatile uint32_t CCBCR4; /* CCBCR4 */ - volatile uint32_t CNBCR4; /* CNBCR4 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR5; /* CECR5 */ - volatile uint32_t CSCR5; /* CSCR5 */ - volatile uint32_t CCBCR5; /* CCBCR5 */ - volatile uint32_t CNBCR5; /* CNBCR5 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR6; /* CECR6 */ - volatile uint32_t CSCR6; /* CSCR6 */ - volatile uint32_t CCBCR6; /* CCBCR6 */ - volatile uint32_t CNBCR6; /* CNBCR6 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR7; /* CECR7 */ - volatile uint32_t CSCR7; /* CSCR7 */ - volatile uint32_t CCBCR7; /* CCBCR7 */ - volatile uint32_t CNBCR7; /* CNBCR7 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR8; /* CECR8 */ - volatile uint32_t CSCR8; /* CSCR8 */ - volatile uint32_t CCBCR8; /* CCBCR8 */ - volatile uint32_t CNBCR8; /* CNBCR8 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR9; /* CECR9 */ - volatile uint32_t CSCR9; /* CSCR9 */ - volatile uint32_t CCBCR9; /* CCBCR9 */ - volatile uint32_t CNBCR9; /* CNBCR9 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR10; /* CECR10 */ - volatile uint32_t CSCR10; /* CSCR10 */ - volatile uint32_t CCBCR10; /* CCBCR10 */ - volatile uint32_t CNBCR10; /* CNBCR10 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR11; /* CECR11 */ - volatile uint32_t CSCR11; /* CSCR11 */ - volatile uint32_t CCBCR11; /* CCBCR11 */ - volatile uint32_t CNBCR11; /* CNBCR11 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR12; /* CECR12 */ - volatile uint32_t CSCR12; /* CSCR12 */ - volatile uint32_t CCBCR12; /* CCBCR12 */ - volatile uint32_t CNBCR12; /* CNBCR12 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR13; /* CECR13 */ - volatile uint32_t CSCR13; /* CSCR13 */ - volatile uint32_t CCBCR13; /* CCBCR13 */ - volatile uint32_t CNBCR13; /* CNBCR13 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR14; /* CECR14 */ - volatile uint32_t CSCR14; /* CSCR14 */ - volatile uint32_t CCBCR14; /* CCBCR14 */ - volatile uint32_t CNBCR14; /* CNBCR14 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR15; /* CECR15 */ - volatile uint32_t CSCR15; /* CSCR15 */ - volatile uint32_t CCBCR15; /* CCBCR15 */ - volatile uint32_t CNBCR15; /* CNBCR15 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR16; /* CECR16 */ - volatile uint32_t CSCR16; /* CSCR16 */ - volatile uint32_t CCBCR16; /* CCBCR16 */ - volatile uint32_t CNBCR16; /* CNBCR16 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR17; /* CECR17 */ - volatile uint32_t CSCR17; /* CSCR17 */ - volatile uint32_t CCBCR17; /* CCBCR17 */ - volatile uint32_t CNBCR17; /* CNBCR17 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR18; /* CECR18 */ - volatile uint32_t CSCR18; /* CSCR18 */ - volatile uint32_t CCBCR18; /* CCBCR18 */ - volatile uint32_t CNBCR18; /* CNBCR18 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR19; /* CECR19 */ - volatile uint32_t CSCR19; /* CSCR19 */ - volatile uint32_t CCBCR19; /* CCBCR19 */ - volatile uint32_t CNBCR19; /* CNBCR19 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR20; /* CECR20 */ - volatile uint32_t CSCR20; /* CSCR20 */ - volatile uint32_t CCBCR20; /* CCBCR20 */ - volatile uint32_t CNBCR20; /* CNBCR20 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR21; /* CECR21 */ - volatile uint32_t CSCR21; /* CSCR21 */ - volatile uint32_t CCBCR21; /* CCBCR21 */ - volatile uint32_t CNBCR21; /* CNBCR21 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR22; /* CECR22 */ - volatile uint32_t CSCR22; /* CSCR22 */ - volatile uint32_t CCBCR22; /* CCBCR22 */ - volatile uint32_t CNBCR22; /* CNBCR22 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR23; /* CECR23 */ - volatile uint32_t CSCR23; /* CSCR23 */ - volatile uint32_t CCBCR23; /* CCBCR23 */ - volatile uint32_t CNBCR23; /* CNBCR23 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR24; /* CECR24 */ - volatile uint32_t CSCR24; /* CSCR24 */ - volatile uint32_t CCBCR24; /* CCBCR24 */ - volatile uint32_t CNBCR24; /* CNBCR24 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR25; /* CECR25 */ - volatile uint32_t CSCR25; /* CSCR25 */ - volatile uint32_t CCBCR25; /* CCBCR25 */ - volatile uint32_t CNBCR25; /* CNBCR25 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR26; /* CECR26 */ - volatile uint32_t CSCR26; /* CSCR26 */ - volatile uint32_t CCBCR26; /* CCBCR26 */ - volatile uint32_t CNBCR26; /* CNBCR26 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR27; /* CECR27 */ - volatile uint32_t CSCR27; /* CSCR27 */ - volatile uint32_t CCBCR27; /* CCBCR27 */ - volatile uint32_t CNBCR27; /* CNBCR27 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR28; /* CECR28 */ - volatile uint32_t CSCR28; /* CSCR28 */ - volatile uint32_t CCBCR28; /* CCBCR28 */ - volatile uint32_t CNBCR28; /* CNBCR28 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR29; /* CECR29 */ - volatile uint32_t CSCR29; /* CSCR29 */ - volatile uint32_t CCBCR29; /* CCBCR29 */ - volatile uint32_t CNBCR29; /* CNBCR29 */ - -/* end of struct st_mlb_from_cecr0 */ - -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR30; /* CECR30 */ - volatile uint32_t CSCR30; /* CSCR30 */ - volatile uint32_t CCBCR30; /* CCBCR30 */ - volatile uint32_t CNBCR30; /* CNBCR30 */ - -/* end of struct st_mlb_from_cecr0 */ - volatile uint8_t dummy158[80]; /* */ - -/* #define MLB_LCBCR0_COUNT (31) */ - volatile uint32_t LCBCR0; /* LCBCR0 */ - volatile uint32_t LCBCR1; /* LCBCR1 */ - volatile uint32_t LCBCR2; /* LCBCR2 */ - volatile uint32_t LCBCR3; /* LCBCR3 */ - volatile uint32_t LCBCR4; /* LCBCR4 */ - volatile uint32_t LCBCR5; /* LCBCR5 */ - volatile uint32_t LCBCR6; /* LCBCR6 */ - volatile uint32_t LCBCR7; /* LCBCR7 */ - volatile uint32_t LCBCR8; /* LCBCR8 */ - volatile uint32_t LCBCR9; /* LCBCR9 */ - volatile uint32_t LCBCR10; /* LCBCR10 */ - volatile uint32_t LCBCR11; /* LCBCR11 */ - volatile uint32_t LCBCR12; /* LCBCR12 */ - volatile uint32_t LCBCR13; /* LCBCR13 */ - volatile uint32_t LCBCR14; /* LCBCR14 */ - volatile uint32_t LCBCR15; /* LCBCR15 */ - volatile uint32_t LCBCR16; /* LCBCR16 */ - volatile uint32_t LCBCR17; /* LCBCR17 */ - volatile uint32_t LCBCR18; /* LCBCR18 */ - volatile uint32_t LCBCR19; /* LCBCR19 */ - volatile uint32_t LCBCR20; /* LCBCR20 */ - volatile uint32_t LCBCR21; /* LCBCR21 */ - volatile uint32_t LCBCR22; /* LCBCR22 */ - volatile uint32_t LCBCR23; /* LCBCR23 */ - volatile uint32_t LCBCR24; /* LCBCR24 */ - volatile uint32_t LCBCR25; /* LCBCR25 */ - volatile uint32_t LCBCR26; /* LCBCR26 */ - volatile uint32_t LCBCR27; /* LCBCR27 */ - volatile uint32_t LCBCR28; /* LCBCR28 */ - volatile uint32_t LCBCR29; /* LCBCR29 */ - volatile uint32_t LCBCR30; /* LCBCR30 */ -} r_io_mlb_t; - - -typedef struct st_mlb_from_cecr0 -{ - - volatile uint32_t CECR0; /* CECR0 */ - volatile uint32_t CSCR0; /* CSCR0 */ - volatile uint32_t CCBCR0; /* CCBCR0 */ - volatile uint32_t CNBCR0; /* CNBCR0 */ -} r_io_mlb_from_cecr0_t; - - -/* Channel array defines of MLB (2)*/ -#ifdef DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS -volatile struct st_mlb_from_cecr0* MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - MLB_FROM_CECR0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */ -/* End of channel array defines of MLB (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h deleted file mode 100644 index cccfd79f66c..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h +++ /dev/null @@ -1,104 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : mmc_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef MMC_IODEFINE_H -#define MMC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ - - -#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH) -#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL) -#define MMCCE_ARG (MMC.CE_ARG) -#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12) -#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL) -#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET) -#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL) -#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC) -#define MMCCE_RESP3 (MMC.CE_RESP3) -#define MMCCE_RESP2 (MMC.CE_RESP2) -#define MMCCE_RESP1 (MMC.CE_RESP1) -#define MMCCE_RESP0 (MMC.CE_RESP0) -#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12) -#define MMCCE_DATA (MMC.CE_DATA) -#define MMCCE_INT (MMC.CE_INT) -#define MMCCE_INT_EN (MMC.CE_INT_EN) -#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1) -#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2) -#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE) -#define MMCCE_DETECT (MMC.CE_DETECT) -#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE) -#define MMCCE_VERSION (MMC.CE_VERSION) - -#define MMC_CE_RESPn_COUNT (4) - - -typedef struct st_mmc -{ - /* MMC */ - volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */ - volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */ - volatile uint8_t dummy182[4]; /* */ - volatile uint32_t CE_ARG; /* CE_ARG */ - volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */ - volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */ - volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */ - volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */ - volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */ - -/* #define MMC_CE_RESPn_COUNT (4) */ - volatile uint32_t CE_RESP3; /* CE_RESP3 */ - volatile uint32_t CE_RESP2; /* CE_RESP2 */ - volatile uint32_t CE_RESP1; /* CE_RESP1 */ - volatile uint32_t CE_RESP0; /* CE_RESP0 */ - volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */ - volatile uint32_t CE_DATA; /* CE_DATA */ - volatile uint8_t dummy183[8]; /* */ - volatile uint32_t CE_INT; /* CE_INT */ - volatile uint32_t CE_INT_EN; /* CE_INT_EN */ - volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */ - volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */ - volatile uint8_t dummy184[12]; /* */ - volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */ - volatile uint8_t dummy185[16]; /* */ - volatile uint32_t CE_DETECT; /* CE_DETECT */ - volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */ - volatile uint8_t dummy186[4]; /* */ - volatile uint32_t CE_VERSION; /* CE_VERSION */ -} r_io_mmc_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h deleted file mode 100644 index 9e3248029f5..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h +++ /dev/null @@ -1,226 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : mtu2_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef MTU2_IODEFINE_H -#define MTU2_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ - - -#define MTU2TCR_2 (MTU2.TCR_2) -#define MTU2TMDR_2 (MTU2.TMDR_2) -#define MTU2TIOR_2 (MTU2.TIOR_2) -#define MTU2TIER_2 (MTU2.TIER_2) -#define MTU2TSR_2 (MTU2.TSR_2) -#define MTU2TCNT_2 (MTU2.TCNT_2) -#define MTU2TGRA_2 (MTU2.TGRA_2) -#define MTU2TGRB_2 (MTU2.TGRB_2) -#define MTU2TCR_3 (MTU2.TCR_3) -#define MTU2TCR_4 (MTU2.TCR_4) -#define MTU2TMDR_3 (MTU2.TMDR_3) -#define MTU2TMDR_4 (MTU2.TMDR_4) -#define MTU2TIORH_3 (MTU2.TIORH_3) -#define MTU2TIORL_3 (MTU2.TIORL_3) -#define MTU2TIORH_4 (MTU2.TIORH_4) -#define MTU2TIORL_4 (MTU2.TIORL_4) -#define MTU2TIER_3 (MTU2.TIER_3) -#define MTU2TIER_4 (MTU2.TIER_4) -#define MTU2TOER (MTU2.TOER) -#define MTU2TGCR (MTU2.TGCR) -#define MTU2TOCR1 (MTU2.TOCR1) -#define MTU2TOCR2 (MTU2.TOCR2) -#define MTU2TCNT_3 (MTU2.TCNT_3) -#define MTU2TCNT_4 (MTU2.TCNT_4) -#define MTU2TCDR (MTU2.TCDR) -#define MTU2TDDR (MTU2.TDDR) -#define MTU2TGRA_3 (MTU2.TGRA_3) -#define MTU2TGRB_3 (MTU2.TGRB_3) -#define MTU2TGRA_4 (MTU2.TGRA_4) -#define MTU2TGRB_4 (MTU2.TGRB_4) -#define MTU2TCNTS (MTU2.TCNTS) -#define MTU2TCBR (MTU2.TCBR) -#define MTU2TGRC_3 (MTU2.TGRC_3) -#define MTU2TGRD_3 (MTU2.TGRD_3) -#define MTU2TGRC_4 (MTU2.TGRC_4) -#define MTU2TGRD_4 (MTU2.TGRD_4) -#define MTU2TSR_3 (MTU2.TSR_3) -#define MTU2TSR_4 (MTU2.TSR_4) -#define MTU2TITCR (MTU2.TITCR) -#define MTU2TITCNT (MTU2.TITCNT) -#define MTU2TBTER (MTU2.TBTER) -#define MTU2TDER (MTU2.TDER) -#define MTU2TOLBR (MTU2.TOLBR) -#define MTU2TBTM_3 (MTU2.TBTM_3) -#define MTU2TBTM_4 (MTU2.TBTM_4) -#define MTU2TADCR (MTU2.TADCR) -#define MTU2TADCORA_4 (MTU2.TADCORA_4) -#define MTU2TADCORB_4 (MTU2.TADCORB_4) -#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4) -#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4) -#define MTU2TWCR (MTU2.TWCR) -#define MTU2TSTR (MTU2.TSTR) -#define MTU2TSYR (MTU2.TSYR) -#define MTU2TRWER (MTU2.TRWER) -#define MTU2TCR_0 (MTU2.TCR_0) -#define MTU2TMDR_0 (MTU2.TMDR_0) -#define MTU2TIORH_0 (MTU2.TIORH_0) -#define MTU2TIORL_0 (MTU2.TIORL_0) -#define MTU2TIER_0 (MTU2.TIER_0) -#define MTU2TSR_0 (MTU2.TSR_0) -#define MTU2TCNT_0 (MTU2.TCNT_0) -#define MTU2TGRA_0 (MTU2.TGRA_0) -#define MTU2TGRB_0 (MTU2.TGRB_0) -#define MTU2TGRC_0 (MTU2.TGRC_0) -#define MTU2TGRD_0 (MTU2.TGRD_0) -#define MTU2TGRE_0 (MTU2.TGRE_0) -#define MTU2TGRF_0 (MTU2.TGRF_0) -#define MTU2TIER2_0 (MTU2.TIER2_0) -#define MTU2TSR2_0 (MTU2.TSR2_0) -#define MTU2TBTM_0 (MTU2.TBTM_0) -#define MTU2TCR_1 (MTU2.TCR_1) -#define MTU2TMDR_1 (MTU2.TMDR_1) -#define MTU2TIOR_1 (MTU2.TIOR_1) -#define MTU2TIER_1 (MTU2.TIER_1) -#define MTU2TSR_1 (MTU2.TSR_1) -#define MTU2TCNT_1 (MTU2.TCNT_1) -#define MTU2TGRA_1 (MTU2.TGRA_1) -#define MTU2TGRB_1 (MTU2.TGRB_1) -#define MTU2TICCR (MTU2.TICCR) - - -typedef struct st_mtu2 -{ - /* MTU2 */ - volatile uint8_t TCR_2; /* TCR_2 */ - volatile uint8_t TMDR_2; /* TMDR_2 */ - volatile uint8_t TIOR_2; /* TIOR_2 */ - volatile uint8_t dummy520[1]; /* */ - volatile uint8_t TIER_2; /* TIER_2 */ - volatile uint8_t TSR_2; /* TSR_2 */ - volatile uint16_t TCNT_2; /* TCNT_2 */ - volatile uint16_t TGRA_2; /* TGRA_2 */ - volatile uint16_t TGRB_2; /* TGRB_2 */ - volatile uint8_t dummy521[500]; /* */ - volatile uint8_t TCR_3; /* TCR_3 */ - volatile uint8_t TCR_4; /* TCR_4 */ - volatile uint8_t TMDR_3; /* TMDR_3 */ - volatile uint8_t TMDR_4; /* TMDR_4 */ - volatile uint8_t TIORH_3; /* TIORH_3 */ - volatile uint8_t TIORL_3; /* TIORL_3 */ - volatile uint8_t TIORH_4; /* TIORH_4 */ - volatile uint8_t TIORL_4; /* TIORL_4 */ - volatile uint8_t TIER_3; /* TIER_3 */ - volatile uint8_t TIER_4; /* TIER_4 */ - volatile uint8_t TOER; /* TOER */ - volatile uint8_t dummy522[2]; /* */ - volatile uint8_t TGCR; /* TGCR */ - volatile uint8_t TOCR1; /* TOCR1 */ - volatile uint8_t TOCR2; /* TOCR2 */ - volatile uint16_t TCNT_3; /* TCNT_3 */ - volatile uint16_t TCNT_4; /* TCNT_4 */ - volatile uint16_t TCDR; /* TCDR */ - volatile uint16_t TDDR; /* TDDR */ - volatile uint16_t TGRA_3; /* TGRA_3 */ - volatile uint16_t TGRB_3; /* TGRB_3 */ - volatile uint16_t TGRA_4; /* TGRA_4 */ - volatile uint16_t TGRB_4; /* TGRB_4 */ - volatile uint16_t TCNTS; /* TCNTS */ - volatile uint16_t TCBR; /* TCBR */ - volatile uint16_t TGRC_3; /* TGRC_3 */ - volatile uint16_t TGRD_3; /* TGRD_3 */ - volatile uint16_t TGRC_4; /* TGRC_4 */ - volatile uint16_t TGRD_4; /* TGRD_4 */ - volatile uint8_t TSR_3; /* TSR_3 */ - volatile uint8_t TSR_4; /* TSR_4 */ - volatile uint8_t dummy523[2]; /* */ - volatile uint8_t TITCR; /* TITCR */ - volatile uint8_t TITCNT; /* TITCNT */ - volatile uint8_t TBTER; /* TBTER */ - volatile uint8_t dummy524[1]; /* */ - volatile uint8_t TDER; /* TDER */ - volatile uint8_t dummy525[1]; /* */ - volatile uint8_t TOLBR; /* TOLBR */ - volatile uint8_t dummy526[1]; /* */ - volatile uint8_t TBTM_3; /* TBTM_3 */ - volatile uint8_t TBTM_4; /* TBTM_4 */ - volatile uint8_t dummy527[6]; /* */ - volatile uint16_t TADCR; /* TADCR */ - volatile uint8_t dummy528[2]; /* */ - volatile uint16_t TADCORA_4; /* TADCORA_4 */ - volatile uint16_t TADCORB_4; /* TADCORB_4 */ - volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */ - volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */ - volatile uint8_t dummy529[20]; /* */ - volatile uint8_t TWCR; /* TWCR */ - volatile uint8_t dummy530[31]; /* */ - volatile uint8_t TSTR; /* TSTR */ - volatile uint8_t TSYR; /* TSYR */ - volatile uint8_t dummy531[2]; /* */ - volatile uint8_t TRWER; /* TRWER */ - volatile uint8_t dummy532[123]; /* */ - volatile uint8_t TCR_0; /* TCR_0 */ - volatile uint8_t TMDR_0; /* TMDR_0 */ - volatile uint8_t TIORH_0; /* TIORH_0 */ - volatile uint8_t TIORL_0; /* TIORL_0 */ - volatile uint8_t TIER_0; /* TIER_0 */ - volatile uint8_t TSR_0; /* TSR_0 */ - volatile uint16_t TCNT_0; /* TCNT_0 */ - volatile uint16_t TGRA_0; /* TGRA_0 */ - volatile uint16_t TGRB_0; /* TGRB_0 */ - volatile uint16_t TGRC_0; /* TGRC_0 */ - volatile uint16_t TGRD_0; /* TGRD_0 */ - volatile uint8_t dummy533[16]; /* */ - volatile uint16_t TGRE_0; /* TGRE_0 */ - volatile uint16_t TGRF_0; /* TGRF_0 */ - volatile uint8_t TIER2_0; /* TIER2_0 */ - volatile uint8_t TSR2_0; /* TSR2_0 */ - volatile uint8_t TBTM_0; /* TBTM_0 */ - volatile uint8_t dummy534[89]; /* */ - volatile uint8_t TCR_1; /* TCR_1 */ - volatile uint8_t TMDR_1; /* TMDR_1 */ - volatile uint8_t TIOR_1; /* TIOR_1 */ - volatile uint8_t dummy535[1]; /* */ - volatile uint8_t TIER_1; /* TIER_1 */ - volatile uint8_t TSR_1; /* TSR_1 */ - volatile uint16_t TCNT_1; /* TCNT_1 */ - volatile uint16_t TGRA_1; /* TGRA_1 */ - volatile uint16_t TGRB_1; /* TGRB_1 */ - volatile uint8_t dummy536[4]; /* */ - volatile uint8_t TICCR; /* TICCR */ -} r_io_mtu2_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h deleted file mode 100644 index f246dd37731..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h +++ /dev/null @@ -1,97 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : ostm_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef OSTM_IODEFINE_H -#define OSTM_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ -#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ - - -/* Start of channel array defines of OSTM */ - -/* Channel array defines of OSTM */ -/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ -#define OSTM_COUNT (2) -#define OSTM_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &OSTM0, &OSTM1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of OSTM */ - - -#define OSTM0CMP (OSTM0.OSTMnCMP) -#define OSTM0CNT (OSTM0.OSTMnCNT) -#define OSTM0TE (OSTM0.OSTMnTE) -#define OSTM0TS (OSTM0.OSTMnTS) -#define OSTM0TT (OSTM0.OSTMnTT) -#define OSTM0CTL (OSTM0.OSTMnCTL) -#define OSTM1CMP (OSTM1.OSTMnCMP) -#define OSTM1CNT (OSTM1.OSTMnCNT) -#define OSTM1TE (OSTM1.OSTMnTE) -#define OSTM1TS (OSTM1.OSTMnTS) -#define OSTM1TT (OSTM1.OSTMnTT) -#define OSTM1CTL (OSTM1.OSTMnCTL) - - -typedef struct st_ostm -{ - /* OSTM */ - volatile uint32_t OSTMnCMP; /* OSTMnCMP */ - volatile uint32_t OSTMnCNT; /* OSTMnCNT */ - volatile uint8_t dummy1[8]; /* */ - volatile uint8_t OSTMnTE; /* OSTMnTE */ - volatile uint8_t dummy2[3]; /* */ - volatile uint8_t OSTMnTS; /* OSTMnTS */ - volatile uint8_t dummy3[3]; /* */ - volatile uint8_t OSTMnTT; /* OSTMnTT */ - volatile uint8_t dummy4[7]; /* */ - volatile uint8_t OSTMnCTL; /* OSTMnCTL */ -} r_io_ostm_t; - - -/* Channel array defines of OSTM (2)*/ -#ifdef DECLARE_OSTM_CHANNELS -volatile struct st_ostm* OSTM[ OSTM_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - OSTM_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_OSTM_CHANNELS */ -/* End of channel array defines of OSTM (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h deleted file mode 100644 index e62a51cca31..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h +++ /dev/null @@ -1,174 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : pfv_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef PFV_IODEFINE_H -#define PFV_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ -#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ - - -/* Start of channel array defines of PFV */ - -/* Channel array defines of PFV */ -/*(Sample) value = PFV[ channel ]->PFVCR; */ -#define PFV_COUNT (2) -#define PFV_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &PFV0, &PFV1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of PFV */ - - -#define PFV0PFVCR (PFV0.PFVCR) -#define PFV0PFVICR (PFV0.PFVICR) -#define PFV0PFVISR (PFV0.PFVISR) -#define PFV0PFVID0 (PFV0.PFVID0) -#define PFV0PFVID1 (PFV0.PFVID1) -#define PFV0PFVID2 (PFV0.PFVID2) -#define PFV0PFVID3 (PFV0.PFVID3) -#define PFV0PFVID4 (PFV0.PFVID4) -#define PFV0PFVID5 (PFV0.PFVID5) -#define PFV0PFVID6 (PFV0.PFVID6) -#define PFV0PFVID7 (PFV0.PFVID7) -#define PFV0PFVOD0 (PFV0.PFVOD0) -#define PFV0PFVOD1 (PFV0.PFVOD1) -#define PFV0PFVOD2 (PFV0.PFVOD2) -#define PFV0PFVOD3 (PFV0.PFVOD3) -#define PFV0PFVOD4 (PFV0.PFVOD4) -#define PFV0PFVOD5 (PFV0.PFVOD5) -#define PFV0PFVOD6 (PFV0.PFVOD6) -#define PFV0PFVOD7 (PFV0.PFVOD7) -#define PFV0PFVIFSR (PFV0.PFVIFSR) -#define PFV0PFVOFSR (PFV0.PFVOFSR) -#define PFV0PFVACR (PFV0.PFVACR) -#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE) -#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0) -#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1) -#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0) -#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1) -#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0) -#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1) -#define PFV0PFVSZR (PFV0.PFVSZR) -#define PFV1PFVCR (PFV1.PFVCR) -#define PFV1PFVICR (PFV1.PFVICR) -#define PFV1PFVISR (PFV1.PFVISR) -#define PFV1PFVID0 (PFV1.PFVID0) -#define PFV1PFVID1 (PFV1.PFVID1) -#define PFV1PFVID2 (PFV1.PFVID2) -#define PFV1PFVID3 (PFV1.PFVID3) -#define PFV1PFVID4 (PFV1.PFVID4) -#define PFV1PFVID5 (PFV1.PFVID5) -#define PFV1PFVID6 (PFV1.PFVID6) -#define PFV1PFVID7 (PFV1.PFVID7) -#define PFV1PFVOD0 (PFV1.PFVOD0) -#define PFV1PFVOD1 (PFV1.PFVOD1) -#define PFV1PFVOD2 (PFV1.PFVOD2) -#define PFV1PFVOD3 (PFV1.PFVOD3) -#define PFV1PFVOD4 (PFV1.PFVOD4) -#define PFV1PFVOD5 (PFV1.PFVOD5) -#define PFV1PFVOD6 (PFV1.PFVOD6) -#define PFV1PFVOD7 (PFV1.PFVOD7) -#define PFV1PFVIFSR (PFV1.PFVIFSR) -#define PFV1PFVOFSR (PFV1.PFVOFSR) -#define PFV1PFVACR (PFV1.PFVACR) -#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE) -#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0) -#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1) -#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0) -#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1) -#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0) -#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1) -#define PFV1PFVSZR (PFV1.PFVSZR) - -#define PFVID_COUNT (8) -#define PFVOD_COUNT (8) - - -typedef struct st_pfv -{ - /* PFV */ - volatile uint32_t PFVCR; /* PFVCR */ - volatile uint32_t PFVICR; /* PFVICR */ - volatile uint32_t PFVISR; /* PFVISR */ - volatile uint8_t dummy1[20]; /* */ - -/* #define PFVID_COUNT (8) */ - volatile uint32_t PFVID0; /* PFVID0 */ - volatile uint32_t PFVID1; /* PFVID1 */ - volatile uint32_t PFVID2; /* PFVID2 */ - volatile uint32_t PFVID3; /* PFVID3 */ - volatile uint32_t PFVID4; /* PFVID4 */ - volatile uint32_t PFVID5; /* PFVID5 */ - volatile uint32_t PFVID6; /* PFVID6 */ - volatile uint32_t PFVID7; /* PFVID7 */ - -/* #define PFVOD_COUNT (8) */ - volatile uint32_t PFVOD0; /* PFVOD0 */ - volatile uint32_t PFVOD1; /* PFVOD1 */ - volatile uint32_t PFVOD2; /* PFVOD2 */ - volatile uint32_t PFVOD3; /* PFVOD3 */ - volatile uint32_t PFVOD4; /* PFVOD4 */ - volatile uint32_t PFVOD5; /* PFVOD5 */ - volatile uint32_t PFVOD6; /* PFVOD6 */ - volatile uint32_t PFVOD7; /* PFVOD7 */ - volatile uint8_t dummy2[4]; /* */ - volatile uint32_t PFVIFSR; /* PFVIFSR */ - volatile uint32_t PFVOFSR; /* PFVOFSR */ - volatile uint32_t PFVACR; /* PFVACR */ - volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */ - volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */ - volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */ - volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */ - volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */ - volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */ - volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */ - volatile uint32_t PFVSZR; /* PFVSZR */ -} r_io_pfv_t; - - -/* Channel array defines of PFV (2)*/ -#ifdef DECLARE_PFV_CHANNELS -volatile struct st_pfv* PFV[ PFV_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - PFV_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_PFV_CHANNELS */ -/* End of channel array defines of PFV (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h deleted file mode 100644 index 128b1099d86..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h +++ /dev/null @@ -1,135 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : pwm_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef PWM_IODEFINE_H -#define PWM_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */ - - -/* Start of channel array defines of PWM */ - -/* Channel array defines of PWMn */ -/*(Sample) value = PWMn[ channel ]->PWCR_1; */ -#define PWMn_COUNT (2) -#define PWMn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &PWM1, &PWM2 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */ -#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */ - -/* End of channel array defines of PWM */ - - -#define PWMPWBTCR (PWM.PWBTCR) -#define PWMPWCR_1 (PWM.PWCR_1) -#define PWMPWPR_1 (PWM.PWPR_1) -#define PWMPWCYR_1 (PWM.PWCYR_1) -#define PWMPWBFR_1A (PWM.PWBFR_1A) -#define PWMPWBFR_1C (PWM.PWBFR_1C) -#define PWMPWBFR_1E (PWM.PWBFR_1E) -#define PWMPWBFR_1G (PWM.PWBFR_1G) -#define PWMPWCR_2 (PWM.PWCR_2) -#define PWMPWPR_2 (PWM.PWPR_2) -#define PWMPWCYR_2 (PWM.PWCYR_2) -#define PWMPWBFR_2A (PWM.PWBFR_2A) -#define PWMPWBFR_2C (PWM.PWBFR_2C) -#define PWMPWBFR_2E (PWM.PWBFR_2E) -#define PWMPWBFR_2G (PWM.PWBFR_2G) - - -typedef struct st_pwm -{ - /* PWM */ - volatile uint8_t dummy559[2]; /* */ - volatile uint8_t PWBTCR; /* PWBTCR */ - volatile uint8_t dummy560[217]; /* */ - -/* start of struct st_pwm_common */ - volatile uint8_t PWCR_1; /* PWCR_1 */ - volatile uint8_t dummy561[3]; /* */ - volatile uint8_t PWPR_1; /* PWPR_1 */ - volatile uint8_t dummy562[1]; /* */ - volatile uint16_t PWCYR_1; /* PWCYR_1 */ - volatile uint16_t PWBFR_1A; /* PWBFR_1A */ - volatile uint16_t PWBFR_1C; /* PWBFR_1C */ - volatile uint16_t PWBFR_1E; /* PWBFR_1E */ - volatile uint16_t PWBFR_1G; /* PWBFR_1G */ - -/* end of struct st_pwm_common */ - -/* start of struct st_pwm_common */ - volatile uint8_t PWCR_2; /* PWCR_2 */ - volatile uint8_t dummy563[3]; /* */ - volatile uint8_t PWPR_2; /* PWPR_2 */ - volatile uint8_t dummy564[1]; /* */ - volatile uint16_t PWCYR_2; /* PWCYR_2 */ - volatile uint16_t PWBFR_2A; /* PWBFR_2A */ - volatile uint16_t PWBFR_2C; /* PWBFR_2C */ - volatile uint16_t PWBFR_2E; /* PWBFR_2E */ - volatile uint16_t PWBFR_2G; /* PWBFR_2G */ - -/* end of struct st_pwm_common */ -} r_io_pwm_t; - - -typedef struct st_pwm_common -{ - - volatile uint8_t PWCR_1; /* PWCR_1 */ - volatile uint8_t dummy562[3]; /* */ - volatile uint8_t PWPR_1; /* PWPR_1 */ - volatile uint8_t dummy563[1]; /* */ - volatile uint16_t PWCYR_1; /* PWCYR_1 */ - volatile uint16_t PWBFR_1A; /* PWBFR_1A */ - volatile uint16_t PWBFR_1C; /* PWBFR_1C */ - volatile uint16_t PWBFR_1E; /* PWBFR_1E */ - volatile uint16_t PWBFR_1G; /* PWBFR_1G */ -} r_io_pwm_common_t; - - -/* Channel array defines of PWMn (2)*/ -#ifdef DECLARE_PWMn_CHANNELS -volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - PWMn_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_PWMn_CHANNELS */ -/* End of channel array defines of PWMn (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h deleted file mode 100644 index 8fd2be68db8..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h +++ /dev/null @@ -1,584 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : riic_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef RIIC_IODEFINE_H -#define RIIC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */ -#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */ -#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */ -#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */ - - -/* Start of channel array defines of RIIC */ - -/* Channel array defines of RIIC */ -/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */ -#define RIIC_COUNT (4) -#define RIIC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RIIC0, &RIIC1, &RIIC2, &RIIC3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of RIIC */ - - -#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32) -#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L]) -#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL]) -#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH]) -#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H]) -#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL]) -#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH]) -#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32) -#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L]) -#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL]) -#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH]) -#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H]) -#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL]) -#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH]) -#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32) -#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L]) -#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL]) -#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH]) -#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H]) -#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL]) -#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH]) -#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32) -#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L]) -#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL]) -#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH]) -#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H]) -#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL]) -#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH]) -#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32) -#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L]) -#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL]) -#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH]) -#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H]) -#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL]) -#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH]) -#define RIIC0FER (RIIC0.RIICnFER.UINT32) -#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L]) -#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL]) -#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH]) -#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H]) -#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL]) -#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH]) -#define RIIC0SER (RIIC0.RIICnSER.UINT32) -#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L]) -#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL]) -#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH]) -#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H]) -#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL]) -#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH]) -#define RIIC0IER (RIIC0.RIICnIER.UINT32) -#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L]) -#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL]) -#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH]) -#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H]) -#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL]) -#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH]) -#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32) -#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L]) -#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL]) -#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH]) -#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H]) -#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL]) -#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH]) -#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32) -#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L]) -#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL]) -#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH]) -#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H]) -#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL]) -#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH]) -#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32) -#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L]) -#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL]) -#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH]) -#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H]) -#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL]) -#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH]) -#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32) -#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L]) -#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL]) -#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH]) -#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H]) -#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL]) -#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH]) -#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32) -#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L]) -#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL]) -#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH]) -#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H]) -#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL]) -#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH]) -#define RIIC0BRL (RIIC0.RIICnBRL.UINT32) -#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L]) -#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL]) -#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH]) -#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H]) -#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL]) -#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH]) -#define RIIC0BRH (RIIC0.RIICnBRH.UINT32) -#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L]) -#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL]) -#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH]) -#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H]) -#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL]) -#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH]) -#define RIIC0DRT (RIIC0.RIICnDRT.UINT32) -#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L]) -#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL]) -#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH]) -#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H]) -#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL]) -#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH]) -#define RIIC0DRR (RIIC0.RIICnDRR.UINT32) -#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L]) -#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL]) -#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH]) -#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H]) -#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL]) -#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH]) -#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32) -#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L]) -#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL]) -#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH]) -#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H]) -#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL]) -#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH]) -#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32) -#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L]) -#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL]) -#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH]) -#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H]) -#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL]) -#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH]) -#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32) -#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L]) -#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL]) -#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH]) -#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H]) -#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL]) -#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH]) -#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32) -#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L]) -#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL]) -#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH]) -#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H]) -#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL]) -#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH]) -#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32) -#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L]) -#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL]) -#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH]) -#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H]) -#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL]) -#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH]) -#define RIIC1FER (RIIC1.RIICnFER.UINT32) -#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L]) -#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL]) -#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH]) -#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H]) -#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL]) -#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH]) -#define RIIC1SER (RIIC1.RIICnSER.UINT32) -#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L]) -#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL]) -#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH]) -#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H]) -#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL]) -#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH]) -#define RIIC1IER (RIIC1.RIICnIER.UINT32) -#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L]) -#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL]) -#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH]) -#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H]) -#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL]) -#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH]) -#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32) -#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L]) -#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL]) -#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH]) -#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H]) -#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL]) -#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH]) -#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32) -#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L]) -#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL]) -#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH]) -#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H]) -#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL]) -#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH]) -#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32) -#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L]) -#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL]) -#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH]) -#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H]) -#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL]) -#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH]) -#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32) -#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L]) -#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL]) -#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH]) -#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H]) -#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL]) -#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH]) -#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32) -#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L]) -#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL]) -#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH]) -#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H]) -#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL]) -#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH]) -#define RIIC1BRL (RIIC1.RIICnBRL.UINT32) -#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L]) -#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL]) -#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH]) -#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H]) -#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL]) -#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH]) -#define RIIC1BRH (RIIC1.RIICnBRH.UINT32) -#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L]) -#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL]) -#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH]) -#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H]) -#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL]) -#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH]) -#define RIIC1DRT (RIIC1.RIICnDRT.UINT32) -#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L]) -#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL]) -#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH]) -#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H]) -#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL]) -#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH]) -#define RIIC1DRR (RIIC1.RIICnDRR.UINT32) -#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L]) -#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL]) -#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH]) -#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H]) -#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL]) -#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH]) -#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32) -#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L]) -#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL]) -#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH]) -#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H]) -#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL]) -#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH]) -#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32) -#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L]) -#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL]) -#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH]) -#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H]) -#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL]) -#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH]) -#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32) -#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L]) -#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL]) -#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH]) -#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H]) -#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL]) -#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH]) -#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32) -#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L]) -#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL]) -#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH]) -#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H]) -#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL]) -#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH]) -#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32) -#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L]) -#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL]) -#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH]) -#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H]) -#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL]) -#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH]) -#define RIIC2FER (RIIC2.RIICnFER.UINT32) -#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L]) -#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL]) -#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH]) -#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H]) -#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL]) -#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH]) -#define RIIC2SER (RIIC2.RIICnSER.UINT32) -#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L]) -#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL]) -#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH]) -#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H]) -#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL]) -#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH]) -#define RIIC2IER (RIIC2.RIICnIER.UINT32) -#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L]) -#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL]) -#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH]) -#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H]) -#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL]) -#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH]) -#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32) -#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L]) -#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL]) -#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH]) -#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H]) -#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL]) -#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH]) -#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32) -#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L]) -#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL]) -#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH]) -#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H]) -#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL]) -#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH]) -#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32) -#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L]) -#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL]) -#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH]) -#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H]) -#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL]) -#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH]) -#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32) -#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L]) -#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL]) -#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH]) -#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H]) -#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL]) -#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH]) -#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32) -#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L]) -#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL]) -#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH]) -#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H]) -#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL]) -#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH]) -#define RIIC2BRL (RIIC2.RIICnBRL.UINT32) -#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L]) -#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL]) -#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH]) -#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H]) -#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL]) -#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH]) -#define RIIC2BRH (RIIC2.RIICnBRH.UINT32) -#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L]) -#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL]) -#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH]) -#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H]) -#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL]) -#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH]) -#define RIIC2DRT (RIIC2.RIICnDRT.UINT32) -#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L]) -#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL]) -#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH]) -#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H]) -#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL]) -#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH]) -#define RIIC2DRR (RIIC2.RIICnDRR.UINT32) -#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L]) -#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL]) -#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH]) -#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H]) -#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL]) -#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH]) -#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32) -#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L]) -#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL]) -#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH]) -#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H]) -#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL]) -#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH]) -#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32) -#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L]) -#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL]) -#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH]) -#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H]) -#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL]) -#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH]) -#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32) -#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L]) -#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL]) -#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH]) -#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H]) -#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL]) -#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH]) -#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32) -#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L]) -#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL]) -#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH]) -#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H]) -#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL]) -#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH]) -#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32) -#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L]) -#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL]) -#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH]) -#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H]) -#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL]) -#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH]) -#define RIIC3FER (RIIC3.RIICnFER.UINT32) -#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L]) -#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL]) -#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH]) -#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H]) -#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL]) -#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH]) -#define RIIC3SER (RIIC3.RIICnSER.UINT32) -#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L]) -#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL]) -#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH]) -#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H]) -#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL]) -#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH]) -#define RIIC3IER (RIIC3.RIICnIER.UINT32) -#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L]) -#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL]) -#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH]) -#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H]) -#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL]) -#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH]) -#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32) -#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L]) -#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL]) -#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH]) -#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H]) -#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL]) -#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH]) -#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32) -#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L]) -#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL]) -#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH]) -#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H]) -#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL]) -#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH]) -#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32) -#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L]) -#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL]) -#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH]) -#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H]) -#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL]) -#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH]) -#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32) -#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L]) -#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL]) -#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH]) -#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H]) -#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL]) -#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH]) -#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32) -#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L]) -#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL]) -#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH]) -#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H]) -#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL]) -#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH]) -#define RIIC3BRL (RIIC3.RIICnBRL.UINT32) -#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L]) -#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL]) -#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH]) -#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H]) -#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL]) -#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH]) -#define RIIC3BRH (RIIC3.RIICnBRH.UINT32) -#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L]) -#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL]) -#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH]) -#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H]) -#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL]) -#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH]) -#define RIIC3DRT (RIIC3.RIICnDRT.UINT32) -#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L]) -#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL]) -#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH]) -#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H]) -#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL]) -#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH]) -#define RIIC3DRR (RIIC3.RIICnDRR.UINT32) -#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L]) -#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL]) -#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH]) -#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H]) -#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL]) -#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH]) - -#define RIICnCRm_COUNT (2) -#define RIICnMRm_COUNT (3) -#define RIICnSRm_COUNT (2) -#define RIICnSARm_COUNT (3) - - -typedef struct st_riic -{ - /* RIIC */ - -/* #define RIICnCRm_COUNT (2) */ - union iodefine_reg32_t RIICnCR1; /* RIICnCR1 */ - union iodefine_reg32_t RIICnCR2; /* RIICnCR2 */ - -/* #define RIICnMRm_COUNT (3) */ - union iodefine_reg32_t RIICnMR1; /* RIICnMR1 */ - union iodefine_reg32_t RIICnMR2; /* RIICnMR2 */ - union iodefine_reg32_t RIICnMR3; /* RIICnMR3 */ - union iodefine_reg32_t RIICnFER; /* RIICnFER */ - union iodefine_reg32_t RIICnSER; /* RIICnSER */ - union iodefine_reg32_t RIICnIER; /* RIICnIER */ - -/* #define RIICnSRm_COUNT (2) */ - union iodefine_reg32_t RIICnSR1; /* RIICnSR1 */ - union iodefine_reg32_t RIICnSR2; /* RIICnSR2 */ - -/* #define RIICnSARm_COUNT (3) */ - union iodefine_reg32_t RIICnSAR0; /* RIICnSAR0 */ - union iodefine_reg32_t RIICnSAR1; /* RIICnSAR1 */ - union iodefine_reg32_t RIICnSAR2; /* RIICnSAR2 */ - union iodefine_reg32_t RIICnBRL; /* RIICnBRL */ - union iodefine_reg32_t RIICnBRH; /* RIICnBRH */ - union iodefine_reg32_t RIICnDRT; /* RIICnDRT */ - union iodefine_reg32_t RIICnDRR; /* RIICnDRR */ - -} r_io_riic_t; - - -/* Channel array defines of RIIC (2)*/ -#ifdef DECLARE_RIIC_CHANNELS -volatile struct st_riic* RIIC[ RIIC_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - RIIC_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_RIIC_CHANNELS */ -/* End of channel array defines of RIIC (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h deleted file mode 100644 index 7d6a207693d..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h +++ /dev/null @@ -1,194 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : romdec_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef ROMDEC_IODEFINE_H -#define ROMDEC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ - - -#define ROMDECCROMEN (ROMDEC.CROMEN) -#define ROMDECCROMSY0 (ROMDEC.CROMSY0) -#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0) -#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1) -#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3) -#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4) -#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5) -#define ROMDECCROMST0 (ROMDEC.CROMST0) -#define ROMDECCROMST1 (ROMDEC.CROMST1) -#define ROMDECCROMST3 (ROMDEC.CROMST3) -#define ROMDECCROMST4 (ROMDEC.CROMST4) -#define ROMDECCROMST5 (ROMDEC.CROMST5) -#define ROMDECCROMST6 (ROMDEC.CROMST6) -#define ROMDECCBUFST0 (ROMDEC.CBUFST0) -#define ROMDECCBUFST1 (ROMDEC.CBUFST1) -#define ROMDECCBUFST2 (ROMDEC.CBUFST2) -#define ROMDECHEAD00 (ROMDEC.HEAD00) -#define ROMDECHEAD01 (ROMDEC.HEAD01) -#define ROMDECHEAD02 (ROMDEC.HEAD02) -#define ROMDECHEAD03 (ROMDEC.HEAD03) -#define ROMDECSHEAD00 (ROMDEC.SHEAD00) -#define ROMDECSHEAD01 (ROMDEC.SHEAD01) -#define ROMDECSHEAD02 (ROMDEC.SHEAD02) -#define ROMDECSHEAD03 (ROMDEC.SHEAD03) -#define ROMDECSHEAD04 (ROMDEC.SHEAD04) -#define ROMDECSHEAD05 (ROMDEC.SHEAD05) -#define ROMDECSHEAD06 (ROMDEC.SHEAD06) -#define ROMDECSHEAD07 (ROMDEC.SHEAD07) -#define ROMDECHEAD20 (ROMDEC.HEAD20) -#define ROMDECHEAD21 (ROMDEC.HEAD21) -#define ROMDECHEAD22 (ROMDEC.HEAD22) -#define ROMDECHEAD23 (ROMDEC.HEAD23) -#define ROMDECSHEAD20 (ROMDEC.SHEAD20) -#define ROMDECSHEAD21 (ROMDEC.SHEAD21) -#define ROMDECSHEAD22 (ROMDEC.SHEAD22) -#define ROMDECSHEAD23 (ROMDEC.SHEAD23) -#define ROMDECSHEAD24 (ROMDEC.SHEAD24) -#define ROMDECSHEAD25 (ROMDEC.SHEAD25) -#define ROMDECSHEAD26 (ROMDEC.SHEAD26) -#define ROMDECSHEAD27 (ROMDEC.SHEAD27) -#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0) -#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1) -#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2) -#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3) -#define ROMDECCROMST0M (ROMDEC.CROMST0M) -#define ROMDECROMDECRST (ROMDEC.ROMDECRST) -#define ROMDECRSTSTAT (ROMDEC.RSTSTAT) -#define ROMDECSSI (ROMDEC.SSI) -#define ROMDECINTHOLD (ROMDEC.INTHOLD) -#define ROMDECINHINT (ROMDEC.INHINT) -#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0) -#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2) -#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0) - -#define ROMDEC_CROMCTL0_COUNT (2) -#define ROMDEC_CROMST0_COUNT (2) -#define ROMDEC_CBUFST0_COUNT (3) -#define ROMDEC_HEAD00_COUNT (4) -#define ROMDEC_SHEAD00_COUNT (8) -#define ROMDEC_HEAD20_COUNT (4) -#define ROMDEC_SHEAD20_COUNT (8) -#define ROMDEC_CBUFCTL0_COUNT (4) -#define ROMDEC_STRMDIN0_COUNT (2) - - -typedef struct st_romdec -{ - /* ROMDEC */ - volatile uint8_t CROMEN; /* CROMEN */ - volatile uint8_t CROMSY0; /* CROMSY0 */ - -/* #define ROMDEC_CROMCTL0_COUNT (2) */ - volatile uint8_t CROMCTL0; /* CROMCTL0 */ - volatile uint8_t CROMCTL1; /* CROMCTL1 */ - volatile uint8_t dummy23[1]; /* */ - volatile uint8_t CROMCTL3; /* CROMCTL3 */ - volatile uint8_t CROMCTL4; /* CROMCTL4 */ - volatile uint8_t CROMCTL5; /* CROMCTL5 */ - -/* #define ROMDEC_CROMST0_COUNT (2) */ - volatile uint8_t CROMST0; /* CROMST0 */ - volatile uint8_t CROMST1; /* CROMST1 */ - volatile uint8_t dummy24[1]; /* */ - volatile uint8_t CROMST3; /* CROMST3 */ - volatile uint8_t CROMST4; /* CROMST4 */ - volatile uint8_t CROMST5; /* CROMST5 */ - volatile uint8_t CROMST6; /* CROMST6 */ - volatile uint8_t dummy25[5]; /* */ - -/* #define ROMDEC_CBUFST0_COUNT (3) */ - volatile uint8_t CBUFST0; /* CBUFST0 */ - volatile uint8_t CBUFST1; /* CBUFST1 */ - volatile uint8_t CBUFST2; /* CBUFST2 */ - volatile uint8_t dummy26[1]; /* */ - -/* #define ROMDEC_HEAD00_COUNT (4) */ - volatile uint8_t HEAD00; /* HEAD00 */ - volatile uint8_t HEAD01; /* HEAD01 */ - volatile uint8_t HEAD02; /* HEAD02 */ - volatile uint8_t HEAD03; /* HEAD03 */ - -/* #define ROMDEC_SHEAD00_COUNT (8) */ - volatile uint8_t SHEAD00; /* SHEAD00 */ - volatile uint8_t SHEAD01; /* SHEAD01 */ - volatile uint8_t SHEAD02; /* SHEAD02 */ - volatile uint8_t SHEAD03; /* SHEAD03 */ - volatile uint8_t SHEAD04; /* SHEAD04 */ - volatile uint8_t SHEAD05; /* SHEAD05 */ - volatile uint8_t SHEAD06; /* SHEAD06 */ - volatile uint8_t SHEAD07; /* SHEAD07 */ - -/* #define ROMDEC_HEAD20_COUNT (4) */ - volatile uint8_t HEAD20; /* HEAD20 */ - volatile uint8_t HEAD21; /* HEAD21 */ - volatile uint8_t HEAD22; /* HEAD22 */ - volatile uint8_t HEAD23; /* HEAD23 */ - -/* #define ROMDEC_SHEAD20_COUNT (8) */ - volatile uint8_t SHEAD20; /* SHEAD20 */ - volatile uint8_t SHEAD21; /* SHEAD21 */ - volatile uint8_t SHEAD22; /* SHEAD22 */ - volatile uint8_t SHEAD23; /* SHEAD23 */ - volatile uint8_t SHEAD24; /* SHEAD24 */ - volatile uint8_t SHEAD25; /* SHEAD25 */ - volatile uint8_t SHEAD26; /* SHEAD26 */ - volatile uint8_t SHEAD27; /* SHEAD27 */ - volatile uint8_t dummy27[16]; /* */ - -/* #define ROMDEC_CBUFCTL0_COUNT (4) */ - volatile uint8_t CBUFCTL0; /* CBUFCTL0 */ - volatile uint8_t CBUFCTL1; /* CBUFCTL1 */ - volatile uint8_t CBUFCTL2; /* CBUFCTL2 */ - volatile uint8_t CBUFCTL3; /* CBUFCTL3 */ - volatile uint8_t dummy28[1]; /* */ - volatile uint8_t CROMST0M; /* CROMST0M */ - volatile uint8_t dummy29[186]; /* */ - volatile uint8_t ROMDECRST; /* ROMDECRST */ - volatile uint8_t RSTSTAT; /* RSTSTAT */ - volatile uint8_t SSI; /* SSI */ - volatile uint8_t dummy30[5]; /* */ - volatile uint8_t INTHOLD; /* INTHOLD */ - volatile uint8_t INHINT; /* INHINT */ - volatile uint8_t dummy31[246]; /* */ - -/* #define ROMDEC_STRMDIN0_COUNT (2) */ - volatile uint16_t STRMDIN0; /* STRMDIN0 */ - volatile uint16_t STRMDIN2; /* STRMDIN2 */ - volatile uint16_t STRMDOUT0; /* STRMDOUT0 */ -} r_io_romdec_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h deleted file mode 100644 index 38bc282098a..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h +++ /dev/null @@ -1,9346 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rscan0_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef RSCAN0_IODEFINE_H -#define RSCAN0_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */ - - -/* Start of channel array defines of RSCAN0 */ - -/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */ -/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */ -#define RSCAN_FROM_RSCAN0_CFIDm_COUNT (15) -#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \ - &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */ -#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */ -#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */ -#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */ -#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */ -#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */ -#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */ -#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */ -#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */ -#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */ -#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */ -#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */ -#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */ -#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */ -#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */ - - -/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */ -/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */ -#define RSCAN_FROM_RSCAN0_TMIDp_COUNT (80) -#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \ - &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \ - &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \ - &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \ - &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \ - &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \ - &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \ - &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \ - &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \ - &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */ -#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */ -#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */ -#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */ -#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */ -#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */ -#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */ -#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */ -#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */ -#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */ -#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */ -#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */ -#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */ -#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */ -#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */ -#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */ -#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */ -#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */ -#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */ -#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */ -#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */ -#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */ -#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */ -#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */ -#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */ -#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */ -#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */ -#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */ -#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */ -#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */ -#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */ -#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */ -#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */ -#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */ -#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */ -#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */ -#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */ -#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */ -#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */ -#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */ -#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */ -#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */ -#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */ -#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */ -#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */ -#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */ -#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */ -#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */ -#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */ -#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */ -#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */ -#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */ -#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */ -#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */ -#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */ -#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */ -#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */ -#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */ -#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */ -#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */ -#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */ -#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */ -#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */ -#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */ -#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */ -#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */ -#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */ -#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */ -#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */ -#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */ -#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */ -#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */ -#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */ -#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */ -#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */ -#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */ -#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */ -#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */ -#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */ -#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */ - - -/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */ -/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */ -#define RSCAN_FROM_RSCAN0_RFIDm_COUNT (8) -#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */ -#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */ -#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */ -#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */ -#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */ -#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */ -#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */ -#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */ - - -/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */ -/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */ -#define RSCAN_FROM_RSCAN0_RMIDp_COUNT (80) -#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \ - &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \ - &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \ - &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \ - &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \ - &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \ - &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \ - &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \ - &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \ - &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */ -#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */ -#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */ -#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */ -#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */ -#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */ -#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */ -#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */ -#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */ -#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */ -#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */ -#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */ -#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */ -#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */ -#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */ -#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */ -#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */ -#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */ -#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */ -#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */ -#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */ -#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */ -#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */ -#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */ -#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */ -#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */ -#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */ -#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */ -#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */ -#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */ -#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */ -#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */ -#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */ -#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */ -#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */ -#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */ -#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */ -#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */ -#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */ -#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */ -#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */ -#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */ -#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */ -#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */ -#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */ -#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */ -#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */ -#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */ -#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */ -#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */ -#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */ -#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */ -#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */ -#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */ -#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */ -#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */ -#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */ -#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */ -#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */ -#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */ -#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */ -#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */ -#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */ -#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */ -#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */ -#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */ -#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */ -#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */ -#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */ -#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */ -#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */ -#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */ -#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */ -#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */ -#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */ -#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */ -#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */ -#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */ -#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */ -#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */ - - -/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */ -/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */ -#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT (16) -#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \ - &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */ -#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */ -#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */ -#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */ -#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */ -#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */ -#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */ -#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */ -#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */ -#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */ -#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */ -#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */ -#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */ -#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */ -#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */ -#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */ - - -/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */ -/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */ -#define RSCAN_FROM_RSCAN0_CnCFG_COUNT (5) -#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */ -#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */ -#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */ -#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */ -#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */ - -/* End of channel array defines of RSCAN0 */ - - -#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32) -#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L]) -#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL]) -#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH]) -#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H]) -#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL]) -#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH]) -#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32) -#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L]) -#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL]) -#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH]) -#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H]) -#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL]) -#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH]) -#define RSCAN0C0STS (RSCAN0.C0STS.UINT32) -#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L]) -#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL]) -#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH]) -#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H]) -#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL]) -#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH]) -#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32) -#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L]) -#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL]) -#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH]) -#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H]) -#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL]) -#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH]) -#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32) -#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L]) -#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL]) -#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH]) -#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H]) -#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL]) -#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH]) -#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32) -#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L]) -#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL]) -#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH]) -#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H]) -#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL]) -#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH]) -#define RSCAN0C1STS (RSCAN0.C1STS.UINT32) -#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L]) -#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL]) -#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH]) -#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H]) -#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL]) -#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH]) -#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32) -#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L]) -#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL]) -#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH]) -#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H]) -#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL]) -#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH]) -#define RSCAN0C2CFG (RSCAN0.C2CFG.UINT32) -#define RSCAN0C2CFGL (RSCAN0.C2CFG.UINT16[R_IO_L]) -#define RSCAN0C2CFGLL (RSCAN0.C2CFG.UINT8[R_IO_LL]) -#define RSCAN0C2CFGLH (RSCAN0.C2CFG.UINT8[R_IO_LH]) -#define RSCAN0C2CFGH (RSCAN0.C2CFG.UINT16[R_IO_H]) -#define RSCAN0C2CFGHL (RSCAN0.C2CFG.UINT8[R_IO_HL]) -#define RSCAN0C2CFGHH (RSCAN0.C2CFG.UINT8[R_IO_HH]) -#define RSCAN0C2CTR (RSCAN0.C2CTR.UINT32) -#define RSCAN0C2CTRL (RSCAN0.C2CTR.UINT16[R_IO_L]) -#define RSCAN0C2CTRLL (RSCAN0.C2CTR.UINT8[R_IO_LL]) -#define RSCAN0C2CTRLH (RSCAN0.C2CTR.UINT8[R_IO_LH]) -#define RSCAN0C2CTRH (RSCAN0.C2CTR.UINT16[R_IO_H]) -#define RSCAN0C2CTRHL (RSCAN0.C2CTR.UINT8[R_IO_HL]) -#define RSCAN0C2CTRHH (RSCAN0.C2CTR.UINT8[R_IO_HH]) -#define RSCAN0C2STS (RSCAN0.C2STS.UINT32) -#define RSCAN0C2STSL (RSCAN0.C2STS.UINT16[R_IO_L]) -#define RSCAN0C2STSLL (RSCAN0.C2STS.UINT8[R_IO_LL]) -#define RSCAN0C2STSLH (RSCAN0.C2STS.UINT8[R_IO_LH]) -#define RSCAN0C2STSH (RSCAN0.C2STS.UINT16[R_IO_H]) -#define RSCAN0C2STSHL (RSCAN0.C2STS.UINT8[R_IO_HL]) -#define RSCAN0C2STSHH (RSCAN0.C2STS.UINT8[R_IO_HH]) -#define RSCAN0C2ERFL (RSCAN0.C2ERFL.UINT32) -#define RSCAN0C2ERFLL (RSCAN0.C2ERFL.UINT16[R_IO_L]) -#define RSCAN0C2ERFLLL (RSCAN0.C2ERFL.UINT8[R_IO_LL]) -#define RSCAN0C2ERFLLH (RSCAN0.C2ERFL.UINT8[R_IO_LH]) -#define RSCAN0C2ERFLH (RSCAN0.C2ERFL.UINT16[R_IO_H]) -#define RSCAN0C2ERFLHL (RSCAN0.C2ERFL.UINT8[R_IO_HL]) -#define RSCAN0C2ERFLHH (RSCAN0.C2ERFL.UINT8[R_IO_HH]) -#define RSCAN0C3CFG (RSCAN0.C3CFG.UINT32) -#define RSCAN0C3CFGL (RSCAN0.C3CFG.UINT16[R_IO_L]) -#define RSCAN0C3CFGLL (RSCAN0.C3CFG.UINT8[R_IO_LL]) -#define RSCAN0C3CFGLH (RSCAN0.C3CFG.UINT8[R_IO_LH]) -#define RSCAN0C3CFGH (RSCAN0.C3CFG.UINT16[R_IO_H]) -#define RSCAN0C3CFGHL (RSCAN0.C3CFG.UINT8[R_IO_HL]) -#define RSCAN0C3CFGHH (RSCAN0.C3CFG.UINT8[R_IO_HH]) -#define RSCAN0C3CTR (RSCAN0.C3CTR.UINT32) -#define RSCAN0C3CTRL (RSCAN0.C3CTR.UINT16[R_IO_L]) -#define RSCAN0C3CTRLL (RSCAN0.C3CTR.UINT8[R_IO_LL]) -#define RSCAN0C3CTRLH (RSCAN0.C3CTR.UINT8[R_IO_LH]) -#define RSCAN0C3CTRH (RSCAN0.C3CTR.UINT16[R_IO_H]) -#define RSCAN0C3CTRHL (RSCAN0.C3CTR.UINT8[R_IO_HL]) -#define RSCAN0C3CTRHH (RSCAN0.C3CTR.UINT8[R_IO_HH]) -#define RSCAN0C3STS (RSCAN0.C3STS.UINT32) -#define RSCAN0C3STSL (RSCAN0.C3STS.UINT16[R_IO_L]) -#define RSCAN0C3STSLL (RSCAN0.C3STS.UINT8[R_IO_LL]) -#define RSCAN0C3STSLH (RSCAN0.C3STS.UINT8[R_IO_LH]) -#define RSCAN0C3STSH (RSCAN0.C3STS.UINT16[R_IO_H]) -#define RSCAN0C3STSHL (RSCAN0.C3STS.UINT8[R_IO_HL]) -#define RSCAN0C3STSHH (RSCAN0.C3STS.UINT8[R_IO_HH]) -#define RSCAN0C3ERFL (RSCAN0.C3ERFL.UINT32) -#define RSCAN0C3ERFLL (RSCAN0.C3ERFL.UINT16[R_IO_L]) -#define RSCAN0C3ERFLLL (RSCAN0.C3ERFL.UINT8[R_IO_LL]) -#define RSCAN0C3ERFLLH (RSCAN0.C3ERFL.UINT8[R_IO_LH]) -#define RSCAN0C3ERFLH (RSCAN0.C3ERFL.UINT16[R_IO_H]) -#define RSCAN0C3ERFLHL (RSCAN0.C3ERFL.UINT8[R_IO_HL]) -#define RSCAN0C3ERFLHH (RSCAN0.C3ERFL.UINT8[R_IO_HH]) -#define RSCAN0C4CFG (RSCAN0.C4CFG.UINT32) -#define RSCAN0C4CFGL (RSCAN0.C4CFG.UINT16[R_IO_L]) -#define RSCAN0C4CFGLL (RSCAN0.C4CFG.UINT8[R_IO_LL]) -#define RSCAN0C4CFGLH (RSCAN0.C4CFG.UINT8[R_IO_LH]) -#define RSCAN0C4CFGH (RSCAN0.C4CFG.UINT16[R_IO_H]) -#define RSCAN0C4CFGHL (RSCAN0.C4CFG.UINT8[R_IO_HL]) -#define RSCAN0C4CFGHH (RSCAN0.C4CFG.UINT8[R_IO_HH]) -#define RSCAN0C4CTR (RSCAN0.C4CTR.UINT32) -#define RSCAN0C4CTRL (RSCAN0.C4CTR.UINT16[R_IO_L]) -#define RSCAN0C4CTRLL (RSCAN0.C4CTR.UINT8[R_IO_LL]) -#define RSCAN0C4CTRLH (RSCAN0.C4CTR.UINT8[R_IO_LH]) -#define RSCAN0C4CTRH (RSCAN0.C4CTR.UINT16[R_IO_H]) -#define RSCAN0C4CTRHL (RSCAN0.C4CTR.UINT8[R_IO_HL]) -#define RSCAN0C4CTRHH (RSCAN0.C4CTR.UINT8[R_IO_HH]) -#define RSCAN0C4STS (RSCAN0.C4STS.UINT32) -#define RSCAN0C4STSL (RSCAN0.C4STS.UINT16[R_IO_L]) -#define RSCAN0C4STSLL (RSCAN0.C4STS.UINT8[R_IO_LL]) -#define RSCAN0C4STSLH (RSCAN0.C4STS.UINT8[R_IO_LH]) -#define RSCAN0C4STSH (RSCAN0.C4STS.UINT16[R_IO_H]) -#define RSCAN0C4STSHL (RSCAN0.C4STS.UINT8[R_IO_HL]) -#define RSCAN0C4STSHH (RSCAN0.C4STS.UINT8[R_IO_HH]) -#define RSCAN0C4ERFL (RSCAN0.C4ERFL.UINT32) -#define RSCAN0C4ERFLL (RSCAN0.C4ERFL.UINT16[R_IO_L]) -#define RSCAN0C4ERFLLL (RSCAN0.C4ERFL.UINT8[R_IO_LL]) -#define RSCAN0C4ERFLLH (RSCAN0.C4ERFL.UINT8[R_IO_LH]) -#define RSCAN0C4ERFLH (RSCAN0.C4ERFL.UINT16[R_IO_H]) -#define RSCAN0C4ERFLHL (RSCAN0.C4ERFL.UINT8[R_IO_HL]) -#define RSCAN0C4ERFLHH (RSCAN0.C4ERFL.UINT8[R_IO_HH]) -#define RSCAN0GCFG (RSCAN0.GCFG.UINT32) -#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L]) -#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL]) -#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH]) -#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H]) -#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL]) -#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH]) -#define RSCAN0GCTR (RSCAN0.GCTR.UINT32) -#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L]) -#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL]) -#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH]) -#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H]) -#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL]) -#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH]) -#define RSCAN0GSTS (RSCAN0.GSTS.UINT32) -#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L]) -#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL]) -#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH]) -#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H]) -#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL]) -#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH]) -#define RSCAN0GERFL (RSCAN0.GERFL.UINT32) -#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L]) -#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL]) -#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH]) -#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H]) -#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL]) -#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH]) -#define RSCAN0GTSC (RSCAN0.GTSC.UINT32) -#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L]) -#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H]) -#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32) -#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L]) -#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL]) -#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH]) -#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H]) -#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL]) -#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH]) -#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32) -#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L]) -#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL]) -#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH]) -#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H]) -#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL]) -#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH]) -#define RSCAN0GAFLCFG1 (RSCAN0.GAFLCFG1.UINT32) -#define RSCAN0GAFLCFG1L (RSCAN0.GAFLCFG1.UINT16[R_IO_L]) -#define RSCAN0GAFLCFG1LL (RSCAN0.GAFLCFG1.UINT8[R_IO_LL]) -#define RSCAN0GAFLCFG1LH (RSCAN0.GAFLCFG1.UINT8[R_IO_LH]) -#define RSCAN0GAFLCFG1H (RSCAN0.GAFLCFG1.UINT16[R_IO_H]) -#define RSCAN0GAFLCFG1HL (RSCAN0.GAFLCFG1.UINT8[R_IO_HL]) -#define RSCAN0GAFLCFG1HH (RSCAN0.GAFLCFG1.UINT8[R_IO_HH]) -#define RSCAN0RMNB (RSCAN0.RMNB.UINT32) -#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L]) -#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL]) -#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH]) -#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H]) -#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL]) -#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH]) -#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32) -#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L]) -#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL]) -#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH]) -#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H]) -#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL]) -#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH]) -#define RSCAN0RMND1 (RSCAN0.RMND1.UINT32) -#define RSCAN0RMND1L (RSCAN0.RMND1.UINT16[R_IO_L]) -#define RSCAN0RMND1LL (RSCAN0.RMND1.UINT8[R_IO_LL]) -#define RSCAN0RMND1LH (RSCAN0.RMND1.UINT8[R_IO_LH]) -#define RSCAN0RMND1H (RSCAN0.RMND1.UINT16[R_IO_H]) -#define RSCAN0RMND1HL (RSCAN0.RMND1.UINT8[R_IO_HL]) -#define RSCAN0RMND1HH (RSCAN0.RMND1.UINT8[R_IO_HH]) -#define RSCAN0RMND2 (RSCAN0.RMND2.UINT32) -#define RSCAN0RMND2L (RSCAN0.RMND2.UINT16[R_IO_L]) -#define RSCAN0RMND2LL (RSCAN0.RMND2.UINT8[R_IO_LL]) -#define RSCAN0RMND2LH (RSCAN0.RMND2.UINT8[R_IO_LH]) -#define RSCAN0RMND2H (RSCAN0.RMND2.UINT16[R_IO_H]) -#define RSCAN0RMND2HL (RSCAN0.RMND2.UINT8[R_IO_HL]) -#define RSCAN0RMND2HH (RSCAN0.RMND2.UINT8[R_IO_HH]) -#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32) -#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L]) -#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL]) -#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH]) -#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H]) -#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL]) -#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH]) -#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32) -#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L]) -#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL]) -#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH]) -#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H]) -#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL]) -#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH]) -#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32) -#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L]) -#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL]) -#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH]) -#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H]) -#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL]) -#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH]) -#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32) -#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L]) -#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL]) -#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH]) -#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H]) -#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL]) -#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH]) -#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32) -#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L]) -#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL]) -#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH]) -#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H]) -#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL]) -#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH]) -#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32) -#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L]) -#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL]) -#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH]) -#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H]) -#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL]) -#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH]) -#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32) -#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L]) -#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL]) -#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH]) -#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H]) -#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL]) -#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH]) -#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32) -#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L]) -#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL]) -#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH]) -#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H]) -#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL]) -#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH]) -#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32) -#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L]) -#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL]) -#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH]) -#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H]) -#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL]) -#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH]) -#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32) -#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L]) -#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL]) -#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH]) -#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H]) -#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL]) -#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH]) -#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32) -#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L]) -#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL]) -#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH]) -#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H]) -#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL]) -#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH]) -#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32) -#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L]) -#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL]) -#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH]) -#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H]) -#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL]) -#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH]) -#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32) -#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L]) -#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL]) -#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH]) -#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H]) -#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL]) -#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH]) -#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32) -#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L]) -#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL]) -#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH]) -#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H]) -#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL]) -#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH]) -#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32) -#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L]) -#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL]) -#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH]) -#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H]) -#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL]) -#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH]) -#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32) -#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L]) -#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL]) -#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH]) -#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H]) -#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL]) -#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH]) -#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32) -#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L]) -#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL]) -#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH]) -#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H]) -#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL]) -#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH]) -#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32) -#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L]) -#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL]) -#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH]) -#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H]) -#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL]) -#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH]) -#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32) -#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L]) -#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL]) -#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH]) -#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H]) -#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL]) -#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH]) -#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32) -#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L]) -#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL]) -#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH]) -#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H]) -#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL]) -#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH]) -#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32) -#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L]) -#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL]) -#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH]) -#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H]) -#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL]) -#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH]) -#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32) -#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L]) -#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL]) -#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH]) -#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H]) -#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL]) -#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH]) -#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32) -#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L]) -#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL]) -#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH]) -#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H]) -#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL]) -#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH]) -#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32) -#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L]) -#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL]) -#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH]) -#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H]) -#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL]) -#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH]) -#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32) -#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L]) -#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL]) -#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH]) -#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H]) -#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL]) -#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH]) -#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32) -#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L]) -#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL]) -#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH]) -#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H]) -#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL]) -#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH]) -#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32) -#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L]) -#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL]) -#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH]) -#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H]) -#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL]) -#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH]) -#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32) -#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L]) -#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL]) -#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH]) -#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H]) -#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL]) -#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH]) -#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32) -#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L]) -#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL]) -#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH]) -#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H]) -#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL]) -#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH]) -#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32) -#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L]) -#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL]) -#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH]) -#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H]) -#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL]) -#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH]) -#define RSCAN0CFCC6 (RSCAN0.CFCC6.UINT32) -#define RSCAN0CFCC6L (RSCAN0.CFCC6.UINT16[R_IO_L]) -#define RSCAN0CFCC6LL (RSCAN0.CFCC6.UINT8[R_IO_LL]) -#define RSCAN0CFCC6LH (RSCAN0.CFCC6.UINT8[R_IO_LH]) -#define RSCAN0CFCC6H (RSCAN0.CFCC6.UINT16[R_IO_H]) -#define RSCAN0CFCC6HL (RSCAN0.CFCC6.UINT8[R_IO_HL]) -#define RSCAN0CFCC6HH (RSCAN0.CFCC6.UINT8[R_IO_HH]) -#define RSCAN0CFCC7 (RSCAN0.CFCC7.UINT32) -#define RSCAN0CFCC7L (RSCAN0.CFCC7.UINT16[R_IO_L]) -#define RSCAN0CFCC7LL (RSCAN0.CFCC7.UINT8[R_IO_LL]) -#define RSCAN0CFCC7LH (RSCAN0.CFCC7.UINT8[R_IO_LH]) -#define RSCAN0CFCC7H (RSCAN0.CFCC7.UINT16[R_IO_H]) -#define RSCAN0CFCC7HL (RSCAN0.CFCC7.UINT8[R_IO_HL]) -#define RSCAN0CFCC7HH (RSCAN0.CFCC7.UINT8[R_IO_HH]) -#define RSCAN0CFCC8 (RSCAN0.CFCC8.UINT32) -#define RSCAN0CFCC8L (RSCAN0.CFCC8.UINT16[R_IO_L]) -#define RSCAN0CFCC8LL (RSCAN0.CFCC8.UINT8[R_IO_LL]) -#define RSCAN0CFCC8LH (RSCAN0.CFCC8.UINT8[R_IO_LH]) -#define RSCAN0CFCC8H (RSCAN0.CFCC8.UINT16[R_IO_H]) -#define RSCAN0CFCC8HL (RSCAN0.CFCC8.UINT8[R_IO_HL]) -#define RSCAN0CFCC8HH (RSCAN0.CFCC8.UINT8[R_IO_HH]) -#define RSCAN0CFCC9 (RSCAN0.CFCC9.UINT32) -#define RSCAN0CFCC9L (RSCAN0.CFCC9.UINT16[R_IO_L]) -#define RSCAN0CFCC9LL (RSCAN0.CFCC9.UINT8[R_IO_LL]) -#define RSCAN0CFCC9LH (RSCAN0.CFCC9.UINT8[R_IO_LH]) -#define RSCAN0CFCC9H (RSCAN0.CFCC9.UINT16[R_IO_H]) -#define RSCAN0CFCC9HL (RSCAN0.CFCC9.UINT8[R_IO_HL]) -#define RSCAN0CFCC9HH (RSCAN0.CFCC9.UINT8[R_IO_HH]) -#define RSCAN0CFCC10 (RSCAN0.CFCC10.UINT32) -#define RSCAN0CFCC10L (RSCAN0.CFCC10.UINT16[R_IO_L]) -#define RSCAN0CFCC10LL (RSCAN0.CFCC10.UINT8[R_IO_LL]) -#define RSCAN0CFCC10LH (RSCAN0.CFCC10.UINT8[R_IO_LH]) -#define RSCAN0CFCC10H (RSCAN0.CFCC10.UINT16[R_IO_H]) -#define RSCAN0CFCC10HL (RSCAN0.CFCC10.UINT8[R_IO_HL]) -#define RSCAN0CFCC10HH (RSCAN0.CFCC10.UINT8[R_IO_HH]) -#define RSCAN0CFCC11 (RSCAN0.CFCC11.UINT32) -#define RSCAN0CFCC11L (RSCAN0.CFCC11.UINT16[R_IO_L]) -#define RSCAN0CFCC11LL (RSCAN0.CFCC11.UINT8[R_IO_LL]) -#define RSCAN0CFCC11LH (RSCAN0.CFCC11.UINT8[R_IO_LH]) -#define RSCAN0CFCC11H (RSCAN0.CFCC11.UINT16[R_IO_H]) -#define RSCAN0CFCC11HL (RSCAN0.CFCC11.UINT8[R_IO_HL]) -#define RSCAN0CFCC11HH (RSCAN0.CFCC11.UINT8[R_IO_HH]) -#define RSCAN0CFCC12 (RSCAN0.CFCC12.UINT32) -#define RSCAN0CFCC12L (RSCAN0.CFCC12.UINT16[R_IO_L]) -#define RSCAN0CFCC12LL (RSCAN0.CFCC12.UINT8[R_IO_LL]) -#define RSCAN0CFCC12LH (RSCAN0.CFCC12.UINT8[R_IO_LH]) -#define RSCAN0CFCC12H (RSCAN0.CFCC12.UINT16[R_IO_H]) -#define RSCAN0CFCC12HL (RSCAN0.CFCC12.UINT8[R_IO_HL]) -#define RSCAN0CFCC12HH (RSCAN0.CFCC12.UINT8[R_IO_HH]) -#define RSCAN0CFCC13 (RSCAN0.CFCC13.UINT32) -#define RSCAN0CFCC13L (RSCAN0.CFCC13.UINT16[R_IO_L]) -#define RSCAN0CFCC13LL (RSCAN0.CFCC13.UINT8[R_IO_LL]) -#define RSCAN0CFCC13LH (RSCAN0.CFCC13.UINT8[R_IO_LH]) -#define RSCAN0CFCC13H (RSCAN0.CFCC13.UINT16[R_IO_H]) -#define RSCAN0CFCC13HL (RSCAN0.CFCC13.UINT8[R_IO_HL]) -#define RSCAN0CFCC13HH (RSCAN0.CFCC13.UINT8[R_IO_HH]) -#define RSCAN0CFCC14 (RSCAN0.CFCC14.UINT32) -#define RSCAN0CFCC14L (RSCAN0.CFCC14.UINT16[R_IO_L]) -#define RSCAN0CFCC14LL (RSCAN0.CFCC14.UINT8[R_IO_LL]) -#define RSCAN0CFCC14LH (RSCAN0.CFCC14.UINT8[R_IO_LH]) -#define RSCAN0CFCC14H (RSCAN0.CFCC14.UINT16[R_IO_H]) -#define RSCAN0CFCC14HL (RSCAN0.CFCC14.UINT8[R_IO_HL]) -#define RSCAN0CFCC14HH (RSCAN0.CFCC14.UINT8[R_IO_HH]) -#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32) -#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L]) -#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL]) -#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH]) -#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H]) -#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL]) -#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH]) -#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32) -#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L]) -#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL]) -#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH]) -#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H]) -#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL]) -#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH]) -#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32) -#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L]) -#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL]) -#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH]) -#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H]) -#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL]) -#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH]) -#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32) -#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L]) -#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL]) -#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH]) -#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H]) -#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL]) -#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH]) -#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32) -#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L]) -#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL]) -#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH]) -#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H]) -#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL]) -#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH]) -#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32) -#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L]) -#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL]) -#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH]) -#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H]) -#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL]) -#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH]) -#define RSCAN0CFSTS6 (RSCAN0.CFSTS6.UINT32) -#define RSCAN0CFSTS6L (RSCAN0.CFSTS6.UINT16[R_IO_L]) -#define RSCAN0CFSTS6LL (RSCAN0.CFSTS6.UINT8[R_IO_LL]) -#define RSCAN0CFSTS6LH (RSCAN0.CFSTS6.UINT8[R_IO_LH]) -#define RSCAN0CFSTS6H (RSCAN0.CFSTS6.UINT16[R_IO_H]) -#define RSCAN0CFSTS6HL (RSCAN0.CFSTS6.UINT8[R_IO_HL]) -#define RSCAN0CFSTS6HH (RSCAN0.CFSTS6.UINT8[R_IO_HH]) -#define RSCAN0CFSTS7 (RSCAN0.CFSTS7.UINT32) -#define RSCAN0CFSTS7L (RSCAN0.CFSTS7.UINT16[R_IO_L]) -#define RSCAN0CFSTS7LL (RSCAN0.CFSTS7.UINT8[R_IO_LL]) -#define RSCAN0CFSTS7LH (RSCAN0.CFSTS7.UINT8[R_IO_LH]) -#define RSCAN0CFSTS7H (RSCAN0.CFSTS7.UINT16[R_IO_H]) -#define RSCAN0CFSTS7HL (RSCAN0.CFSTS7.UINT8[R_IO_HL]) -#define RSCAN0CFSTS7HH (RSCAN0.CFSTS7.UINT8[R_IO_HH]) -#define RSCAN0CFSTS8 (RSCAN0.CFSTS8.UINT32) -#define RSCAN0CFSTS8L (RSCAN0.CFSTS8.UINT16[R_IO_L]) -#define RSCAN0CFSTS8LL (RSCAN0.CFSTS8.UINT8[R_IO_LL]) -#define RSCAN0CFSTS8LH (RSCAN0.CFSTS8.UINT8[R_IO_LH]) -#define RSCAN0CFSTS8H (RSCAN0.CFSTS8.UINT16[R_IO_H]) -#define RSCAN0CFSTS8HL (RSCAN0.CFSTS8.UINT8[R_IO_HL]) -#define RSCAN0CFSTS8HH (RSCAN0.CFSTS8.UINT8[R_IO_HH]) -#define RSCAN0CFSTS9 (RSCAN0.CFSTS9.UINT32) -#define RSCAN0CFSTS9L (RSCAN0.CFSTS9.UINT16[R_IO_L]) -#define RSCAN0CFSTS9LL (RSCAN0.CFSTS9.UINT8[R_IO_LL]) -#define RSCAN0CFSTS9LH (RSCAN0.CFSTS9.UINT8[R_IO_LH]) -#define RSCAN0CFSTS9H (RSCAN0.CFSTS9.UINT16[R_IO_H]) -#define RSCAN0CFSTS9HL (RSCAN0.CFSTS9.UINT8[R_IO_HL]) -#define RSCAN0CFSTS9HH (RSCAN0.CFSTS9.UINT8[R_IO_HH]) -#define RSCAN0CFSTS10 (RSCAN0.CFSTS10.UINT32) -#define RSCAN0CFSTS10L (RSCAN0.CFSTS10.UINT16[R_IO_L]) -#define RSCAN0CFSTS10LL (RSCAN0.CFSTS10.UINT8[R_IO_LL]) -#define RSCAN0CFSTS10LH (RSCAN0.CFSTS10.UINT8[R_IO_LH]) -#define RSCAN0CFSTS10H (RSCAN0.CFSTS10.UINT16[R_IO_H]) -#define RSCAN0CFSTS10HL (RSCAN0.CFSTS10.UINT8[R_IO_HL]) -#define RSCAN0CFSTS10HH (RSCAN0.CFSTS10.UINT8[R_IO_HH]) -#define RSCAN0CFSTS11 (RSCAN0.CFSTS11.UINT32) -#define RSCAN0CFSTS11L (RSCAN0.CFSTS11.UINT16[R_IO_L]) -#define RSCAN0CFSTS11LL (RSCAN0.CFSTS11.UINT8[R_IO_LL]) -#define RSCAN0CFSTS11LH (RSCAN0.CFSTS11.UINT8[R_IO_LH]) -#define RSCAN0CFSTS11H (RSCAN0.CFSTS11.UINT16[R_IO_H]) -#define RSCAN0CFSTS11HL (RSCAN0.CFSTS11.UINT8[R_IO_HL]) -#define RSCAN0CFSTS11HH (RSCAN0.CFSTS11.UINT8[R_IO_HH]) -#define RSCAN0CFSTS12 (RSCAN0.CFSTS12.UINT32) -#define RSCAN0CFSTS12L (RSCAN0.CFSTS12.UINT16[R_IO_L]) -#define RSCAN0CFSTS12LL (RSCAN0.CFSTS12.UINT8[R_IO_LL]) -#define RSCAN0CFSTS12LH (RSCAN0.CFSTS12.UINT8[R_IO_LH]) -#define RSCAN0CFSTS12H (RSCAN0.CFSTS12.UINT16[R_IO_H]) -#define RSCAN0CFSTS12HL (RSCAN0.CFSTS12.UINT8[R_IO_HL]) -#define RSCAN0CFSTS12HH (RSCAN0.CFSTS12.UINT8[R_IO_HH]) -#define RSCAN0CFSTS13 (RSCAN0.CFSTS13.UINT32) -#define RSCAN0CFSTS13L (RSCAN0.CFSTS13.UINT16[R_IO_L]) -#define RSCAN0CFSTS13LL (RSCAN0.CFSTS13.UINT8[R_IO_LL]) -#define RSCAN0CFSTS13LH (RSCAN0.CFSTS13.UINT8[R_IO_LH]) -#define RSCAN0CFSTS13H (RSCAN0.CFSTS13.UINT16[R_IO_H]) -#define RSCAN0CFSTS13HL (RSCAN0.CFSTS13.UINT8[R_IO_HL]) -#define RSCAN0CFSTS13HH (RSCAN0.CFSTS13.UINT8[R_IO_HH]) -#define RSCAN0CFSTS14 (RSCAN0.CFSTS14.UINT32) -#define RSCAN0CFSTS14L (RSCAN0.CFSTS14.UINT16[R_IO_L]) -#define RSCAN0CFSTS14LL (RSCAN0.CFSTS14.UINT8[R_IO_LL]) -#define RSCAN0CFSTS14LH (RSCAN0.CFSTS14.UINT8[R_IO_LH]) -#define RSCAN0CFSTS14H (RSCAN0.CFSTS14.UINT16[R_IO_H]) -#define RSCAN0CFSTS14HL (RSCAN0.CFSTS14.UINT8[R_IO_HL]) -#define RSCAN0CFSTS14HH (RSCAN0.CFSTS14.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32) -#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L]) -#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H]) -#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32) -#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L]) -#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H]) -#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32) -#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L]) -#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H]) -#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32) -#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L]) -#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H]) -#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32) -#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L]) -#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H]) -#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32) -#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L]) -#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H]) -#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR6 (RSCAN0.CFPCTR6.UINT32) -#define RSCAN0CFPCTR6L (RSCAN0.CFPCTR6.UINT16[R_IO_L]) -#define RSCAN0CFPCTR6LL (RSCAN0.CFPCTR6.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR6LH (RSCAN0.CFPCTR6.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR6H (RSCAN0.CFPCTR6.UINT16[R_IO_H]) -#define RSCAN0CFPCTR6HL (RSCAN0.CFPCTR6.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR6HH (RSCAN0.CFPCTR6.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR7 (RSCAN0.CFPCTR7.UINT32) -#define RSCAN0CFPCTR7L (RSCAN0.CFPCTR7.UINT16[R_IO_L]) -#define RSCAN0CFPCTR7LL (RSCAN0.CFPCTR7.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR7LH (RSCAN0.CFPCTR7.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR7H (RSCAN0.CFPCTR7.UINT16[R_IO_H]) -#define RSCAN0CFPCTR7HL (RSCAN0.CFPCTR7.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR7HH (RSCAN0.CFPCTR7.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR8 (RSCAN0.CFPCTR8.UINT32) -#define RSCAN0CFPCTR8L (RSCAN0.CFPCTR8.UINT16[R_IO_L]) -#define RSCAN0CFPCTR8LL (RSCAN0.CFPCTR8.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR8LH (RSCAN0.CFPCTR8.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR8H (RSCAN0.CFPCTR8.UINT16[R_IO_H]) -#define RSCAN0CFPCTR8HL (RSCAN0.CFPCTR8.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR8HH (RSCAN0.CFPCTR8.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR9 (RSCAN0.CFPCTR9.UINT32) -#define RSCAN0CFPCTR9L (RSCAN0.CFPCTR9.UINT16[R_IO_L]) -#define RSCAN0CFPCTR9LL (RSCAN0.CFPCTR9.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR9LH (RSCAN0.CFPCTR9.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR9H (RSCAN0.CFPCTR9.UINT16[R_IO_H]) -#define RSCAN0CFPCTR9HL (RSCAN0.CFPCTR9.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR9HH (RSCAN0.CFPCTR9.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR10 (RSCAN0.CFPCTR10.UINT32) -#define RSCAN0CFPCTR10L (RSCAN0.CFPCTR10.UINT16[R_IO_L]) -#define RSCAN0CFPCTR10LL (RSCAN0.CFPCTR10.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR10LH (RSCAN0.CFPCTR10.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR10H (RSCAN0.CFPCTR10.UINT16[R_IO_H]) -#define RSCAN0CFPCTR10HL (RSCAN0.CFPCTR10.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR10HH (RSCAN0.CFPCTR10.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR11 (RSCAN0.CFPCTR11.UINT32) -#define RSCAN0CFPCTR11L (RSCAN0.CFPCTR11.UINT16[R_IO_L]) -#define RSCAN0CFPCTR11LL (RSCAN0.CFPCTR11.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR11LH (RSCAN0.CFPCTR11.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR11H (RSCAN0.CFPCTR11.UINT16[R_IO_H]) -#define RSCAN0CFPCTR11HL (RSCAN0.CFPCTR11.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR11HH (RSCAN0.CFPCTR11.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR12 (RSCAN0.CFPCTR12.UINT32) -#define RSCAN0CFPCTR12L (RSCAN0.CFPCTR12.UINT16[R_IO_L]) -#define RSCAN0CFPCTR12LL (RSCAN0.CFPCTR12.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR12LH (RSCAN0.CFPCTR12.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR12H (RSCAN0.CFPCTR12.UINT16[R_IO_H]) -#define RSCAN0CFPCTR12HL (RSCAN0.CFPCTR12.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR12HH (RSCAN0.CFPCTR12.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR13 (RSCAN0.CFPCTR13.UINT32) -#define RSCAN0CFPCTR13L (RSCAN0.CFPCTR13.UINT16[R_IO_L]) -#define RSCAN0CFPCTR13LL (RSCAN0.CFPCTR13.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR13LH (RSCAN0.CFPCTR13.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR13H (RSCAN0.CFPCTR13.UINT16[R_IO_H]) -#define RSCAN0CFPCTR13HL (RSCAN0.CFPCTR13.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR13HH (RSCAN0.CFPCTR13.UINT8[R_IO_HH]) -#define RSCAN0CFPCTR14 (RSCAN0.CFPCTR14.UINT32) -#define RSCAN0CFPCTR14L (RSCAN0.CFPCTR14.UINT16[R_IO_L]) -#define RSCAN0CFPCTR14LL (RSCAN0.CFPCTR14.UINT8[R_IO_LL]) -#define RSCAN0CFPCTR14LH (RSCAN0.CFPCTR14.UINT8[R_IO_LH]) -#define RSCAN0CFPCTR14H (RSCAN0.CFPCTR14.UINT16[R_IO_H]) -#define RSCAN0CFPCTR14HL (RSCAN0.CFPCTR14.UINT8[R_IO_HL]) -#define RSCAN0CFPCTR14HH (RSCAN0.CFPCTR14.UINT8[R_IO_HH]) -#define RSCAN0FESTS (RSCAN0.FESTS.UINT32) -#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L]) -#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL]) -#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH]) -#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H]) -#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL]) -#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH]) -#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32) -#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L]) -#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL]) -#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH]) -#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H]) -#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL]) -#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH]) -#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32) -#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L]) -#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL]) -#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH]) -#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H]) -#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL]) -#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH]) -#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32) -#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L]) -#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL]) -#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH]) -#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H]) -#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL]) -#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH]) -#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32) -#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L]) -#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL]) -#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH]) -#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H]) -#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL]) -#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH]) -#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32) -#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L]) -#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL]) -#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH]) -#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H]) -#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL]) -#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH]) -#define RSCAN0TMC0 (RSCAN0.TMC0) -#define RSCAN0TMC1 (RSCAN0.TMC1) -#define RSCAN0TMC2 (RSCAN0.TMC2) -#define RSCAN0TMC3 (RSCAN0.TMC3) -#define RSCAN0TMC4 (RSCAN0.TMC4) -#define RSCAN0TMC5 (RSCAN0.TMC5) -#define RSCAN0TMC6 (RSCAN0.TMC6) -#define RSCAN0TMC7 (RSCAN0.TMC7) -#define RSCAN0TMC8 (RSCAN0.TMC8) -#define RSCAN0TMC9 (RSCAN0.TMC9) -#define RSCAN0TMC10 (RSCAN0.TMC10) -#define RSCAN0TMC11 (RSCAN0.TMC11) -#define RSCAN0TMC12 (RSCAN0.TMC12) -#define RSCAN0TMC13 (RSCAN0.TMC13) -#define RSCAN0TMC14 (RSCAN0.TMC14) -#define RSCAN0TMC15 (RSCAN0.TMC15) -#define RSCAN0TMC16 (RSCAN0.TMC16) -#define RSCAN0TMC17 (RSCAN0.TMC17) -#define RSCAN0TMC18 (RSCAN0.TMC18) -#define RSCAN0TMC19 (RSCAN0.TMC19) -#define RSCAN0TMC20 (RSCAN0.TMC20) -#define RSCAN0TMC21 (RSCAN0.TMC21) -#define RSCAN0TMC22 (RSCAN0.TMC22) -#define RSCAN0TMC23 (RSCAN0.TMC23) -#define RSCAN0TMC24 (RSCAN0.TMC24) -#define RSCAN0TMC25 (RSCAN0.TMC25) -#define RSCAN0TMC26 (RSCAN0.TMC26) -#define RSCAN0TMC27 (RSCAN0.TMC27) -#define RSCAN0TMC28 (RSCAN0.TMC28) -#define RSCAN0TMC29 (RSCAN0.TMC29) -#define RSCAN0TMC30 (RSCAN0.TMC30) -#define RSCAN0TMC31 (RSCAN0.TMC31) -#define RSCAN0TMC32 (RSCAN0.TMC32) -#define RSCAN0TMC33 (RSCAN0.TMC33) -#define RSCAN0TMC34 (RSCAN0.TMC34) -#define RSCAN0TMC35 (RSCAN0.TMC35) -#define RSCAN0TMC36 (RSCAN0.TMC36) -#define RSCAN0TMC37 (RSCAN0.TMC37) -#define RSCAN0TMC38 (RSCAN0.TMC38) -#define RSCAN0TMC39 (RSCAN0.TMC39) -#define RSCAN0TMC40 (RSCAN0.TMC40) -#define RSCAN0TMC41 (RSCAN0.TMC41) -#define RSCAN0TMC42 (RSCAN0.TMC42) -#define RSCAN0TMC43 (RSCAN0.TMC43) -#define RSCAN0TMC44 (RSCAN0.TMC44) -#define RSCAN0TMC45 (RSCAN0.TMC45) -#define RSCAN0TMC46 (RSCAN0.TMC46) -#define RSCAN0TMC47 (RSCAN0.TMC47) -#define RSCAN0TMC48 (RSCAN0.TMC48) -#define RSCAN0TMC49 (RSCAN0.TMC49) -#define RSCAN0TMC50 (RSCAN0.TMC50) -#define RSCAN0TMC51 (RSCAN0.TMC51) -#define RSCAN0TMC52 (RSCAN0.TMC52) -#define RSCAN0TMC53 (RSCAN0.TMC53) -#define RSCAN0TMC54 (RSCAN0.TMC54) -#define RSCAN0TMC55 (RSCAN0.TMC55) -#define RSCAN0TMC56 (RSCAN0.TMC56) -#define RSCAN0TMC57 (RSCAN0.TMC57) -#define RSCAN0TMC58 (RSCAN0.TMC58) -#define RSCAN0TMC59 (RSCAN0.TMC59) -#define RSCAN0TMC60 (RSCAN0.TMC60) -#define RSCAN0TMC61 (RSCAN0.TMC61) -#define RSCAN0TMC62 (RSCAN0.TMC62) -#define RSCAN0TMC63 (RSCAN0.TMC63) -#define RSCAN0TMC64 (RSCAN0.TMC64) -#define RSCAN0TMC65 (RSCAN0.TMC65) -#define RSCAN0TMC66 (RSCAN0.TMC66) -#define RSCAN0TMC67 (RSCAN0.TMC67) -#define RSCAN0TMC68 (RSCAN0.TMC68) -#define RSCAN0TMC69 (RSCAN0.TMC69) -#define RSCAN0TMC70 (RSCAN0.TMC70) -#define RSCAN0TMC71 (RSCAN0.TMC71) -#define RSCAN0TMC72 (RSCAN0.TMC72) -#define RSCAN0TMC73 (RSCAN0.TMC73) -#define RSCAN0TMC74 (RSCAN0.TMC74) -#define RSCAN0TMC75 (RSCAN0.TMC75) -#define RSCAN0TMC76 (RSCAN0.TMC76) -#define RSCAN0TMC77 (RSCAN0.TMC77) -#define RSCAN0TMC78 (RSCAN0.TMC78) -#define RSCAN0TMC79 (RSCAN0.TMC79) -#define RSCAN0TMSTS0 (RSCAN0.TMSTS0) -#define RSCAN0TMSTS1 (RSCAN0.TMSTS1) -#define RSCAN0TMSTS2 (RSCAN0.TMSTS2) -#define RSCAN0TMSTS3 (RSCAN0.TMSTS3) -#define RSCAN0TMSTS4 (RSCAN0.TMSTS4) -#define RSCAN0TMSTS5 (RSCAN0.TMSTS5) -#define RSCAN0TMSTS6 (RSCAN0.TMSTS6) -#define RSCAN0TMSTS7 (RSCAN0.TMSTS7) -#define RSCAN0TMSTS8 (RSCAN0.TMSTS8) -#define RSCAN0TMSTS9 (RSCAN0.TMSTS9) -#define RSCAN0TMSTS10 (RSCAN0.TMSTS10) -#define RSCAN0TMSTS11 (RSCAN0.TMSTS11) -#define RSCAN0TMSTS12 (RSCAN0.TMSTS12) -#define RSCAN0TMSTS13 (RSCAN0.TMSTS13) -#define RSCAN0TMSTS14 (RSCAN0.TMSTS14) -#define RSCAN0TMSTS15 (RSCAN0.TMSTS15) -#define RSCAN0TMSTS16 (RSCAN0.TMSTS16) -#define RSCAN0TMSTS17 (RSCAN0.TMSTS17) -#define RSCAN0TMSTS18 (RSCAN0.TMSTS18) -#define RSCAN0TMSTS19 (RSCAN0.TMSTS19) -#define RSCAN0TMSTS20 (RSCAN0.TMSTS20) -#define RSCAN0TMSTS21 (RSCAN0.TMSTS21) -#define RSCAN0TMSTS22 (RSCAN0.TMSTS22) -#define RSCAN0TMSTS23 (RSCAN0.TMSTS23) -#define RSCAN0TMSTS24 (RSCAN0.TMSTS24) -#define RSCAN0TMSTS25 (RSCAN0.TMSTS25) -#define RSCAN0TMSTS26 (RSCAN0.TMSTS26) -#define RSCAN0TMSTS27 (RSCAN0.TMSTS27) -#define RSCAN0TMSTS28 (RSCAN0.TMSTS28) -#define RSCAN0TMSTS29 (RSCAN0.TMSTS29) -#define RSCAN0TMSTS30 (RSCAN0.TMSTS30) -#define RSCAN0TMSTS31 (RSCAN0.TMSTS31) -#define RSCAN0TMSTS32 (RSCAN0.TMSTS32) -#define RSCAN0TMSTS33 (RSCAN0.TMSTS33) -#define RSCAN0TMSTS34 (RSCAN0.TMSTS34) -#define RSCAN0TMSTS35 (RSCAN0.TMSTS35) -#define RSCAN0TMSTS36 (RSCAN0.TMSTS36) -#define RSCAN0TMSTS37 (RSCAN0.TMSTS37) -#define RSCAN0TMSTS38 (RSCAN0.TMSTS38) -#define RSCAN0TMSTS39 (RSCAN0.TMSTS39) -#define RSCAN0TMSTS40 (RSCAN0.TMSTS40) -#define RSCAN0TMSTS41 (RSCAN0.TMSTS41) -#define RSCAN0TMSTS42 (RSCAN0.TMSTS42) -#define RSCAN0TMSTS43 (RSCAN0.TMSTS43) -#define RSCAN0TMSTS44 (RSCAN0.TMSTS44) -#define RSCAN0TMSTS45 (RSCAN0.TMSTS45) -#define RSCAN0TMSTS46 (RSCAN0.TMSTS46) -#define RSCAN0TMSTS47 (RSCAN0.TMSTS47) -#define RSCAN0TMSTS48 (RSCAN0.TMSTS48) -#define RSCAN0TMSTS49 (RSCAN0.TMSTS49) -#define RSCAN0TMSTS50 (RSCAN0.TMSTS50) -#define RSCAN0TMSTS51 (RSCAN0.TMSTS51) -#define RSCAN0TMSTS52 (RSCAN0.TMSTS52) -#define RSCAN0TMSTS53 (RSCAN0.TMSTS53) -#define RSCAN0TMSTS54 (RSCAN0.TMSTS54) -#define RSCAN0TMSTS55 (RSCAN0.TMSTS55) -#define RSCAN0TMSTS56 (RSCAN0.TMSTS56) -#define RSCAN0TMSTS57 (RSCAN0.TMSTS57) -#define RSCAN0TMSTS58 (RSCAN0.TMSTS58) -#define RSCAN0TMSTS59 (RSCAN0.TMSTS59) -#define RSCAN0TMSTS60 (RSCAN0.TMSTS60) -#define RSCAN0TMSTS61 (RSCAN0.TMSTS61) -#define RSCAN0TMSTS62 (RSCAN0.TMSTS62) -#define RSCAN0TMSTS63 (RSCAN0.TMSTS63) -#define RSCAN0TMSTS64 (RSCAN0.TMSTS64) -#define RSCAN0TMSTS65 (RSCAN0.TMSTS65) -#define RSCAN0TMSTS66 (RSCAN0.TMSTS66) -#define RSCAN0TMSTS67 (RSCAN0.TMSTS67) -#define RSCAN0TMSTS68 (RSCAN0.TMSTS68) -#define RSCAN0TMSTS69 (RSCAN0.TMSTS69) -#define RSCAN0TMSTS70 (RSCAN0.TMSTS70) -#define RSCAN0TMSTS71 (RSCAN0.TMSTS71) -#define RSCAN0TMSTS72 (RSCAN0.TMSTS72) -#define RSCAN0TMSTS73 (RSCAN0.TMSTS73) -#define RSCAN0TMSTS74 (RSCAN0.TMSTS74) -#define RSCAN0TMSTS75 (RSCAN0.TMSTS75) -#define RSCAN0TMSTS76 (RSCAN0.TMSTS76) -#define RSCAN0TMSTS77 (RSCAN0.TMSTS77) -#define RSCAN0TMSTS78 (RSCAN0.TMSTS78) -#define RSCAN0TMSTS79 (RSCAN0.TMSTS79) -#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32) -#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L]) -#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL]) -#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH]) -#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H]) -#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL]) -#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH]) -#define RSCAN0TMTRSTS1 (RSCAN0.TMTRSTS1.UINT32) -#define RSCAN0TMTRSTS1L (RSCAN0.TMTRSTS1.UINT16[R_IO_L]) -#define RSCAN0TMTRSTS1LL (RSCAN0.TMTRSTS1.UINT8[R_IO_LL]) -#define RSCAN0TMTRSTS1LH (RSCAN0.TMTRSTS1.UINT8[R_IO_LH]) -#define RSCAN0TMTRSTS1H (RSCAN0.TMTRSTS1.UINT16[R_IO_H]) -#define RSCAN0TMTRSTS1HL (RSCAN0.TMTRSTS1.UINT8[R_IO_HL]) -#define RSCAN0TMTRSTS1HH (RSCAN0.TMTRSTS1.UINT8[R_IO_HH]) -#define RSCAN0TMTRSTS2 (RSCAN0.TMTRSTS2.UINT32) -#define RSCAN0TMTRSTS2L (RSCAN0.TMTRSTS2.UINT16[R_IO_L]) -#define RSCAN0TMTRSTS2LL (RSCAN0.TMTRSTS2.UINT8[R_IO_LL]) -#define RSCAN0TMTRSTS2LH (RSCAN0.TMTRSTS2.UINT8[R_IO_LH]) -#define RSCAN0TMTRSTS2H (RSCAN0.TMTRSTS2.UINT16[R_IO_H]) -#define RSCAN0TMTRSTS2HL (RSCAN0.TMTRSTS2.UINT8[R_IO_HL]) -#define RSCAN0TMTRSTS2HH (RSCAN0.TMTRSTS2.UINT8[R_IO_HH]) -#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32) -#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L]) -#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL]) -#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH]) -#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H]) -#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL]) -#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH]) -#define RSCAN0TMTARSTS1 (RSCAN0.TMTARSTS1.UINT32) -#define RSCAN0TMTARSTS1L (RSCAN0.TMTARSTS1.UINT16[R_IO_L]) -#define RSCAN0TMTARSTS1LL (RSCAN0.TMTARSTS1.UINT8[R_IO_LL]) -#define RSCAN0TMTARSTS1LH (RSCAN0.TMTARSTS1.UINT8[R_IO_LH]) -#define RSCAN0TMTARSTS1H (RSCAN0.TMTARSTS1.UINT16[R_IO_H]) -#define RSCAN0TMTARSTS1HL (RSCAN0.TMTARSTS1.UINT8[R_IO_HL]) -#define RSCAN0TMTARSTS1HH (RSCAN0.TMTARSTS1.UINT8[R_IO_HH]) -#define RSCAN0TMTARSTS2 (RSCAN0.TMTARSTS2.UINT32) -#define RSCAN0TMTARSTS2L (RSCAN0.TMTARSTS2.UINT16[R_IO_L]) -#define RSCAN0TMTARSTS2LL (RSCAN0.TMTARSTS2.UINT8[R_IO_LL]) -#define RSCAN0TMTARSTS2LH (RSCAN0.TMTARSTS2.UINT8[R_IO_LH]) -#define RSCAN0TMTARSTS2H (RSCAN0.TMTARSTS2.UINT16[R_IO_H]) -#define RSCAN0TMTARSTS2HL (RSCAN0.TMTARSTS2.UINT8[R_IO_HL]) -#define RSCAN0TMTARSTS2HH (RSCAN0.TMTARSTS2.UINT8[R_IO_HH]) -#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32) -#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L]) -#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL]) -#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH]) -#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H]) -#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL]) -#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH]) -#define RSCAN0TMTCSTS1 (RSCAN0.TMTCSTS1.UINT32) -#define RSCAN0TMTCSTS1L (RSCAN0.TMTCSTS1.UINT16[R_IO_L]) -#define RSCAN0TMTCSTS1LL (RSCAN0.TMTCSTS1.UINT8[R_IO_LL]) -#define RSCAN0TMTCSTS1LH (RSCAN0.TMTCSTS1.UINT8[R_IO_LH]) -#define RSCAN0TMTCSTS1H (RSCAN0.TMTCSTS1.UINT16[R_IO_H]) -#define RSCAN0TMTCSTS1HL (RSCAN0.TMTCSTS1.UINT8[R_IO_HL]) -#define RSCAN0TMTCSTS1HH (RSCAN0.TMTCSTS1.UINT8[R_IO_HH]) -#define RSCAN0TMTCSTS2 (RSCAN0.TMTCSTS2.UINT32) -#define RSCAN0TMTCSTS2L (RSCAN0.TMTCSTS2.UINT16[R_IO_L]) -#define RSCAN0TMTCSTS2LL (RSCAN0.TMTCSTS2.UINT8[R_IO_LL]) -#define RSCAN0TMTCSTS2LH (RSCAN0.TMTCSTS2.UINT8[R_IO_LH]) -#define RSCAN0TMTCSTS2H (RSCAN0.TMTCSTS2.UINT16[R_IO_H]) -#define RSCAN0TMTCSTS2HL (RSCAN0.TMTCSTS2.UINT8[R_IO_HL]) -#define RSCAN0TMTCSTS2HH (RSCAN0.TMTCSTS2.UINT8[R_IO_HH]) -#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32) -#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L]) -#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL]) -#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH]) -#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H]) -#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL]) -#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH]) -#define RSCAN0TMTASTS1 (RSCAN0.TMTASTS1.UINT32) -#define RSCAN0TMTASTS1L (RSCAN0.TMTASTS1.UINT16[R_IO_L]) -#define RSCAN0TMTASTS1LL (RSCAN0.TMTASTS1.UINT8[R_IO_LL]) -#define RSCAN0TMTASTS1LH (RSCAN0.TMTASTS1.UINT8[R_IO_LH]) -#define RSCAN0TMTASTS1H (RSCAN0.TMTASTS1.UINT16[R_IO_H]) -#define RSCAN0TMTASTS1HL (RSCAN0.TMTASTS1.UINT8[R_IO_HL]) -#define RSCAN0TMTASTS1HH (RSCAN0.TMTASTS1.UINT8[R_IO_HH]) -#define RSCAN0TMTASTS2 (RSCAN0.TMTASTS2.UINT32) -#define RSCAN0TMTASTS2L (RSCAN0.TMTASTS2.UINT16[R_IO_L]) -#define RSCAN0TMTASTS2LL (RSCAN0.TMTASTS2.UINT8[R_IO_LL]) -#define RSCAN0TMTASTS2LH (RSCAN0.TMTASTS2.UINT8[R_IO_LH]) -#define RSCAN0TMTASTS2H (RSCAN0.TMTASTS2.UINT16[R_IO_H]) -#define RSCAN0TMTASTS2HL (RSCAN0.TMTASTS2.UINT8[R_IO_HL]) -#define RSCAN0TMTASTS2HH (RSCAN0.TMTASTS2.UINT8[R_IO_HH]) -#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32) -#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L]) -#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL]) -#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH]) -#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H]) -#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL]) -#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH]) -#define RSCAN0TMIEC1 (RSCAN0.TMIEC1.UINT32) -#define RSCAN0TMIEC1L (RSCAN0.TMIEC1.UINT16[R_IO_L]) -#define RSCAN0TMIEC1LL (RSCAN0.TMIEC1.UINT8[R_IO_LL]) -#define RSCAN0TMIEC1LH (RSCAN0.TMIEC1.UINT8[R_IO_LH]) -#define RSCAN0TMIEC1H (RSCAN0.TMIEC1.UINT16[R_IO_H]) -#define RSCAN0TMIEC1HL (RSCAN0.TMIEC1.UINT8[R_IO_HL]) -#define RSCAN0TMIEC1HH (RSCAN0.TMIEC1.UINT8[R_IO_HH]) -#define RSCAN0TMIEC2 (RSCAN0.TMIEC2.UINT32) -#define RSCAN0TMIEC2L (RSCAN0.TMIEC2.UINT16[R_IO_L]) -#define RSCAN0TMIEC2LL (RSCAN0.TMIEC2.UINT8[R_IO_LL]) -#define RSCAN0TMIEC2LH (RSCAN0.TMIEC2.UINT8[R_IO_LH]) -#define RSCAN0TMIEC2H (RSCAN0.TMIEC2.UINT16[R_IO_H]) -#define RSCAN0TMIEC2HL (RSCAN0.TMIEC2.UINT8[R_IO_HL]) -#define RSCAN0TMIEC2HH (RSCAN0.TMIEC2.UINT8[R_IO_HH]) -#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32) -#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L]) -#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL]) -#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH]) -#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H]) -#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL]) -#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH]) -#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32) -#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L]) -#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL]) -#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH]) -#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H]) -#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL]) -#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH]) -#define RSCAN0TXQCC2 (RSCAN0.TXQCC2.UINT32) -#define RSCAN0TXQCC2L (RSCAN0.TXQCC2.UINT16[R_IO_L]) -#define RSCAN0TXQCC2LL (RSCAN0.TXQCC2.UINT8[R_IO_LL]) -#define RSCAN0TXQCC2LH (RSCAN0.TXQCC2.UINT8[R_IO_LH]) -#define RSCAN0TXQCC2H (RSCAN0.TXQCC2.UINT16[R_IO_H]) -#define RSCAN0TXQCC2HL (RSCAN0.TXQCC2.UINT8[R_IO_HL]) -#define RSCAN0TXQCC2HH (RSCAN0.TXQCC2.UINT8[R_IO_HH]) -#define RSCAN0TXQCC3 (RSCAN0.TXQCC3.UINT32) -#define RSCAN0TXQCC3L (RSCAN0.TXQCC3.UINT16[R_IO_L]) -#define RSCAN0TXQCC3LL (RSCAN0.TXQCC3.UINT8[R_IO_LL]) -#define RSCAN0TXQCC3LH (RSCAN0.TXQCC3.UINT8[R_IO_LH]) -#define RSCAN0TXQCC3H (RSCAN0.TXQCC3.UINT16[R_IO_H]) -#define RSCAN0TXQCC3HL (RSCAN0.TXQCC3.UINT8[R_IO_HL]) -#define RSCAN0TXQCC3HH (RSCAN0.TXQCC3.UINT8[R_IO_HH]) -#define RSCAN0TXQCC4 (RSCAN0.TXQCC4.UINT32) -#define RSCAN0TXQCC4L (RSCAN0.TXQCC4.UINT16[R_IO_L]) -#define RSCAN0TXQCC4LL (RSCAN0.TXQCC4.UINT8[R_IO_LL]) -#define RSCAN0TXQCC4LH (RSCAN0.TXQCC4.UINT8[R_IO_LH]) -#define RSCAN0TXQCC4H (RSCAN0.TXQCC4.UINT16[R_IO_H]) -#define RSCAN0TXQCC4HL (RSCAN0.TXQCC4.UINT8[R_IO_HL]) -#define RSCAN0TXQCC4HH (RSCAN0.TXQCC4.UINT8[R_IO_HH]) -#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32) -#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L]) -#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL]) -#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH]) -#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H]) -#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL]) -#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH]) -#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32) -#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L]) -#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL]) -#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH]) -#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H]) -#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL]) -#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH]) -#define RSCAN0TXQSTS2 (RSCAN0.TXQSTS2.UINT32) -#define RSCAN0TXQSTS2L (RSCAN0.TXQSTS2.UINT16[R_IO_L]) -#define RSCAN0TXQSTS2LL (RSCAN0.TXQSTS2.UINT8[R_IO_LL]) -#define RSCAN0TXQSTS2LH (RSCAN0.TXQSTS2.UINT8[R_IO_LH]) -#define RSCAN0TXQSTS2H (RSCAN0.TXQSTS2.UINT16[R_IO_H]) -#define RSCAN0TXQSTS2HL (RSCAN0.TXQSTS2.UINT8[R_IO_HL]) -#define RSCAN0TXQSTS2HH (RSCAN0.TXQSTS2.UINT8[R_IO_HH]) -#define RSCAN0TXQSTS3 (RSCAN0.TXQSTS3.UINT32) -#define RSCAN0TXQSTS3L (RSCAN0.TXQSTS3.UINT16[R_IO_L]) -#define RSCAN0TXQSTS3LL (RSCAN0.TXQSTS3.UINT8[R_IO_LL]) -#define RSCAN0TXQSTS3LH (RSCAN0.TXQSTS3.UINT8[R_IO_LH]) -#define RSCAN0TXQSTS3H (RSCAN0.TXQSTS3.UINT16[R_IO_H]) -#define RSCAN0TXQSTS3HL (RSCAN0.TXQSTS3.UINT8[R_IO_HL]) -#define RSCAN0TXQSTS3HH (RSCAN0.TXQSTS3.UINT8[R_IO_HH]) -#define RSCAN0TXQSTS4 (RSCAN0.TXQSTS4.UINT32) -#define RSCAN0TXQSTS4L (RSCAN0.TXQSTS4.UINT16[R_IO_L]) -#define RSCAN0TXQSTS4LL (RSCAN0.TXQSTS4.UINT8[R_IO_LL]) -#define RSCAN0TXQSTS4LH (RSCAN0.TXQSTS4.UINT8[R_IO_LH]) -#define RSCAN0TXQSTS4H (RSCAN0.TXQSTS4.UINT16[R_IO_H]) -#define RSCAN0TXQSTS4HL (RSCAN0.TXQSTS4.UINT8[R_IO_HL]) -#define RSCAN0TXQSTS4HH (RSCAN0.TXQSTS4.UINT8[R_IO_HH]) -#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32) -#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L]) -#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL]) -#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH]) -#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H]) -#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL]) -#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH]) -#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32) -#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L]) -#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL]) -#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH]) -#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H]) -#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL]) -#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH]) -#define RSCAN0TXQPCTR2 (RSCAN0.TXQPCTR2.UINT32) -#define RSCAN0TXQPCTR2L (RSCAN0.TXQPCTR2.UINT16[R_IO_L]) -#define RSCAN0TXQPCTR2LL (RSCAN0.TXQPCTR2.UINT8[R_IO_LL]) -#define RSCAN0TXQPCTR2LH (RSCAN0.TXQPCTR2.UINT8[R_IO_LH]) -#define RSCAN0TXQPCTR2H (RSCAN0.TXQPCTR2.UINT16[R_IO_H]) -#define RSCAN0TXQPCTR2HL (RSCAN0.TXQPCTR2.UINT8[R_IO_HL]) -#define RSCAN0TXQPCTR2HH (RSCAN0.TXQPCTR2.UINT8[R_IO_HH]) -#define RSCAN0TXQPCTR3 (RSCAN0.TXQPCTR3.UINT32) -#define RSCAN0TXQPCTR3L (RSCAN0.TXQPCTR3.UINT16[R_IO_L]) -#define RSCAN0TXQPCTR3LL (RSCAN0.TXQPCTR3.UINT8[R_IO_LL]) -#define RSCAN0TXQPCTR3LH (RSCAN0.TXQPCTR3.UINT8[R_IO_LH]) -#define RSCAN0TXQPCTR3H (RSCAN0.TXQPCTR3.UINT16[R_IO_H]) -#define RSCAN0TXQPCTR3HL (RSCAN0.TXQPCTR3.UINT8[R_IO_HL]) -#define RSCAN0TXQPCTR3HH (RSCAN0.TXQPCTR3.UINT8[R_IO_HH]) -#define RSCAN0TXQPCTR4 (RSCAN0.TXQPCTR4.UINT32) -#define RSCAN0TXQPCTR4L (RSCAN0.TXQPCTR4.UINT16[R_IO_L]) -#define RSCAN0TXQPCTR4LL (RSCAN0.TXQPCTR4.UINT8[R_IO_LL]) -#define RSCAN0TXQPCTR4LH (RSCAN0.TXQPCTR4.UINT8[R_IO_LH]) -#define RSCAN0TXQPCTR4H (RSCAN0.TXQPCTR4.UINT16[R_IO_H]) -#define RSCAN0TXQPCTR4HL (RSCAN0.TXQPCTR4.UINT8[R_IO_HL]) -#define RSCAN0TXQPCTR4HH (RSCAN0.TXQPCTR4.UINT8[R_IO_HH]) -#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32) -#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L]) -#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL]) -#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH]) -#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H]) -#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL]) -#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH]) -#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32) -#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L]) -#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL]) -#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH]) -#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H]) -#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL]) -#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH]) -#define RSCAN0THLCC2 (RSCAN0.THLCC2.UINT32) -#define RSCAN0THLCC2L (RSCAN0.THLCC2.UINT16[R_IO_L]) -#define RSCAN0THLCC2LL (RSCAN0.THLCC2.UINT8[R_IO_LL]) -#define RSCAN0THLCC2LH (RSCAN0.THLCC2.UINT8[R_IO_LH]) -#define RSCAN0THLCC2H (RSCAN0.THLCC2.UINT16[R_IO_H]) -#define RSCAN0THLCC2HL (RSCAN0.THLCC2.UINT8[R_IO_HL]) -#define RSCAN0THLCC2HH (RSCAN0.THLCC2.UINT8[R_IO_HH]) -#define RSCAN0THLCC3 (RSCAN0.THLCC3.UINT32) -#define RSCAN0THLCC3L (RSCAN0.THLCC3.UINT16[R_IO_L]) -#define RSCAN0THLCC3LL (RSCAN0.THLCC3.UINT8[R_IO_LL]) -#define RSCAN0THLCC3LH (RSCAN0.THLCC3.UINT8[R_IO_LH]) -#define RSCAN0THLCC3H (RSCAN0.THLCC3.UINT16[R_IO_H]) -#define RSCAN0THLCC3HL (RSCAN0.THLCC3.UINT8[R_IO_HL]) -#define RSCAN0THLCC3HH (RSCAN0.THLCC3.UINT8[R_IO_HH]) -#define RSCAN0THLCC4 (RSCAN0.THLCC4.UINT32) -#define RSCAN0THLCC4L (RSCAN0.THLCC4.UINT16[R_IO_L]) -#define RSCAN0THLCC4LL (RSCAN0.THLCC4.UINT8[R_IO_LL]) -#define RSCAN0THLCC4LH (RSCAN0.THLCC4.UINT8[R_IO_LH]) -#define RSCAN0THLCC4H (RSCAN0.THLCC4.UINT16[R_IO_H]) -#define RSCAN0THLCC4HL (RSCAN0.THLCC4.UINT8[R_IO_HL]) -#define RSCAN0THLCC4HH (RSCAN0.THLCC4.UINT8[R_IO_HH]) -#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32) -#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L]) -#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL]) -#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH]) -#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H]) -#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL]) -#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH]) -#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32) -#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L]) -#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL]) -#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH]) -#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H]) -#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL]) -#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH]) -#define RSCAN0THLSTS2 (RSCAN0.THLSTS2.UINT32) -#define RSCAN0THLSTS2L (RSCAN0.THLSTS2.UINT16[R_IO_L]) -#define RSCAN0THLSTS2LL (RSCAN0.THLSTS2.UINT8[R_IO_LL]) -#define RSCAN0THLSTS2LH (RSCAN0.THLSTS2.UINT8[R_IO_LH]) -#define RSCAN0THLSTS2H (RSCAN0.THLSTS2.UINT16[R_IO_H]) -#define RSCAN0THLSTS2HL (RSCAN0.THLSTS2.UINT8[R_IO_HL]) -#define RSCAN0THLSTS2HH (RSCAN0.THLSTS2.UINT8[R_IO_HH]) -#define RSCAN0THLSTS3 (RSCAN0.THLSTS3.UINT32) -#define RSCAN0THLSTS3L (RSCAN0.THLSTS3.UINT16[R_IO_L]) -#define RSCAN0THLSTS3LL (RSCAN0.THLSTS3.UINT8[R_IO_LL]) -#define RSCAN0THLSTS3LH (RSCAN0.THLSTS3.UINT8[R_IO_LH]) -#define RSCAN0THLSTS3H (RSCAN0.THLSTS3.UINT16[R_IO_H]) -#define RSCAN0THLSTS3HL (RSCAN0.THLSTS3.UINT8[R_IO_HL]) -#define RSCAN0THLSTS3HH (RSCAN0.THLSTS3.UINT8[R_IO_HH]) -#define RSCAN0THLSTS4 (RSCAN0.THLSTS4.UINT32) -#define RSCAN0THLSTS4L (RSCAN0.THLSTS4.UINT16[R_IO_L]) -#define RSCAN0THLSTS4LL (RSCAN0.THLSTS4.UINT8[R_IO_LL]) -#define RSCAN0THLSTS4LH (RSCAN0.THLSTS4.UINT8[R_IO_LH]) -#define RSCAN0THLSTS4H (RSCAN0.THLSTS4.UINT16[R_IO_H]) -#define RSCAN0THLSTS4HL (RSCAN0.THLSTS4.UINT8[R_IO_HL]) -#define RSCAN0THLSTS4HH (RSCAN0.THLSTS4.UINT8[R_IO_HH]) -#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32) -#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L]) -#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL]) -#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH]) -#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H]) -#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL]) -#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH]) -#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32) -#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L]) -#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL]) -#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH]) -#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H]) -#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL]) -#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH]) -#define RSCAN0THLPCTR2 (RSCAN0.THLPCTR2.UINT32) -#define RSCAN0THLPCTR2L (RSCAN0.THLPCTR2.UINT16[R_IO_L]) -#define RSCAN0THLPCTR2LL (RSCAN0.THLPCTR2.UINT8[R_IO_LL]) -#define RSCAN0THLPCTR2LH (RSCAN0.THLPCTR2.UINT8[R_IO_LH]) -#define RSCAN0THLPCTR2H (RSCAN0.THLPCTR2.UINT16[R_IO_H]) -#define RSCAN0THLPCTR2HL (RSCAN0.THLPCTR2.UINT8[R_IO_HL]) -#define RSCAN0THLPCTR2HH (RSCAN0.THLPCTR2.UINT8[R_IO_HH]) -#define RSCAN0THLPCTR3 (RSCAN0.THLPCTR3.UINT32) -#define RSCAN0THLPCTR3L (RSCAN0.THLPCTR3.UINT16[R_IO_L]) -#define RSCAN0THLPCTR3LL (RSCAN0.THLPCTR3.UINT8[R_IO_LL]) -#define RSCAN0THLPCTR3LH (RSCAN0.THLPCTR3.UINT8[R_IO_LH]) -#define RSCAN0THLPCTR3H (RSCAN0.THLPCTR3.UINT16[R_IO_H]) -#define RSCAN0THLPCTR3HL (RSCAN0.THLPCTR3.UINT8[R_IO_HL]) -#define RSCAN0THLPCTR3HH (RSCAN0.THLPCTR3.UINT8[R_IO_HH]) -#define RSCAN0THLPCTR4 (RSCAN0.THLPCTR4.UINT32) -#define RSCAN0THLPCTR4L (RSCAN0.THLPCTR4.UINT16[R_IO_L]) -#define RSCAN0THLPCTR4LL (RSCAN0.THLPCTR4.UINT8[R_IO_LL]) -#define RSCAN0THLPCTR4LH (RSCAN0.THLPCTR4.UINT8[R_IO_LH]) -#define RSCAN0THLPCTR4H (RSCAN0.THLPCTR4.UINT16[R_IO_H]) -#define RSCAN0THLPCTR4HL (RSCAN0.THLPCTR4.UINT8[R_IO_HL]) -#define RSCAN0THLPCTR4HH (RSCAN0.THLPCTR4.UINT8[R_IO_HH]) -#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32) -#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L]) -#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL]) -#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH]) -#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H]) -#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL]) -#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH]) -#define RSCAN0GTINTSTS1 (RSCAN0.GTINTSTS1.UINT32) -#define RSCAN0GTINTSTS1L (RSCAN0.GTINTSTS1.UINT16[R_IO_L]) -#define RSCAN0GTINTSTS1LL (RSCAN0.GTINTSTS1.UINT8[R_IO_LL]) -#define RSCAN0GTINTSTS1LH (RSCAN0.GTINTSTS1.UINT8[R_IO_LH]) -#define RSCAN0GTINTSTS1H (RSCAN0.GTINTSTS1.UINT16[R_IO_H]) -#define RSCAN0GTINTSTS1HL (RSCAN0.GTINTSTS1.UINT8[R_IO_HL]) -#define RSCAN0GTINTSTS1HH (RSCAN0.GTINTSTS1.UINT8[R_IO_HH]) -#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32) -#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L]) -#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL]) -#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH]) -#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H]) -#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL]) -#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH]) -#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32) -#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L]) -#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL]) -#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH]) -#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H]) -#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL]) -#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH]) -#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32) -#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L]) -#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H]) -#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32) -#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L]) -#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL]) -#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH]) -#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H]) -#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL]) -#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH]) -#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32) -#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L]) -#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL]) -#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH]) -#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H]) -#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL]) -#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH]) -#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32) -#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L]) -#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL]) -#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH]) -#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H]) -#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL]) -#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH]) -#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32) -#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L]) -#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL]) -#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH]) -#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H]) -#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL]) -#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH]) -#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32) -#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L]) -#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL]) -#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH]) -#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H]) -#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL]) -#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH]) -#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32) -#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L]) -#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL]) -#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH]) -#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H]) -#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL]) -#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH]) -#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32) -#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L]) -#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL]) -#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH]) -#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H]) -#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL]) -#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH]) -#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32) -#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L]) -#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL]) -#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH]) -#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H]) -#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL]) -#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH]) -#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32) -#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L]) -#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL]) -#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH]) -#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H]) -#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL]) -#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH]) -#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32) -#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L]) -#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL]) -#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH]) -#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H]) -#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL]) -#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH]) -#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32) -#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L]) -#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL]) -#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH]) -#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H]) -#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL]) -#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH]) -#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32) -#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L]) -#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL]) -#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH]) -#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H]) -#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL]) -#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH]) -#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32) -#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L]) -#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL]) -#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH]) -#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H]) -#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL]) -#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH]) -#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32) -#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L]) -#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL]) -#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH]) -#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H]) -#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL]) -#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH]) -#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32) -#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L]) -#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL]) -#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH]) -#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H]) -#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL]) -#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH]) -#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32) -#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L]) -#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL]) -#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH]) -#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H]) -#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL]) -#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH]) -#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32) -#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L]) -#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL]) -#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH]) -#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H]) -#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL]) -#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH]) -#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32) -#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L]) -#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL]) -#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH]) -#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H]) -#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL]) -#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH]) -#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32) -#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L]) -#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL]) -#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH]) -#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H]) -#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL]) -#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH]) -#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32) -#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L]) -#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL]) -#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH]) -#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H]) -#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL]) -#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH]) -#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32) -#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L]) -#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL]) -#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH]) -#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H]) -#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL]) -#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH]) -#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32) -#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L]) -#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL]) -#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH]) -#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H]) -#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL]) -#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH]) -#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32) -#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L]) -#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL]) -#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH]) -#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H]) -#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL]) -#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH]) -#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32) -#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L]) -#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL]) -#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH]) -#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H]) -#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL]) -#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH]) -#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32) -#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L]) -#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL]) -#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH]) -#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H]) -#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL]) -#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH]) -#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32) -#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L]) -#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL]) -#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH]) -#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H]) -#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL]) -#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH]) -#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32) -#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L]) -#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL]) -#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH]) -#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H]) -#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL]) -#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH]) -#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32) -#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L]) -#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL]) -#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH]) -#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H]) -#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL]) -#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH]) -#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32) -#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L]) -#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL]) -#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH]) -#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H]) -#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL]) -#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH]) -#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32) -#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L]) -#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL]) -#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH]) -#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H]) -#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL]) -#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH]) -#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32) -#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L]) -#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL]) -#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH]) -#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H]) -#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL]) -#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH]) -#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32) -#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L]) -#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL]) -#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH]) -#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H]) -#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL]) -#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH]) -#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32) -#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L]) -#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL]) -#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH]) -#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H]) -#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL]) -#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH]) -#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32) -#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L]) -#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL]) -#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH]) -#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H]) -#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL]) -#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH]) -#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32) -#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L]) -#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL]) -#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH]) -#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H]) -#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL]) -#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH]) -#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32) -#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L]) -#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL]) -#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH]) -#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H]) -#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL]) -#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH]) -#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32) -#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L]) -#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL]) -#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH]) -#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H]) -#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL]) -#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH]) -#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32) -#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L]) -#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL]) -#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH]) -#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H]) -#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL]) -#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH]) -#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32) -#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L]) -#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL]) -#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH]) -#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H]) -#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL]) -#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH]) -#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32) -#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L]) -#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL]) -#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH]) -#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H]) -#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL]) -#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH]) -#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32) -#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L]) -#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL]) -#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH]) -#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H]) -#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL]) -#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH]) -#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32) -#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L]) -#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL]) -#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH]) -#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H]) -#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL]) -#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH]) -#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32) -#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L]) -#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL]) -#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH]) -#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H]) -#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL]) -#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH]) -#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32) -#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L]) -#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL]) -#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH]) -#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H]) -#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL]) -#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH]) -#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32) -#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L]) -#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL]) -#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH]) -#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H]) -#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL]) -#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH]) -#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32) -#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L]) -#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL]) -#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH]) -#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H]) -#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL]) -#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH]) -#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32) -#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L]) -#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL]) -#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH]) -#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H]) -#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL]) -#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH]) -#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32) -#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L]) -#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL]) -#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH]) -#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H]) -#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL]) -#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH]) -#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32) -#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L]) -#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL]) -#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH]) -#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H]) -#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL]) -#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH]) -#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32) -#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L]) -#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL]) -#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH]) -#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H]) -#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL]) -#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH]) -#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32) -#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L]) -#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL]) -#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH]) -#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H]) -#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL]) -#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH]) -#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32) -#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L]) -#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL]) -#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH]) -#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H]) -#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL]) -#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH]) -#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32) -#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L]) -#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL]) -#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH]) -#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H]) -#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL]) -#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH]) -#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32) -#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L]) -#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL]) -#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH]) -#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H]) -#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL]) -#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH]) -#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32) -#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L]) -#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL]) -#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH]) -#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H]) -#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL]) -#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH]) -#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32) -#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L]) -#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL]) -#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH]) -#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H]) -#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL]) -#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH]) -#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32) -#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L]) -#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL]) -#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH]) -#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H]) -#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL]) -#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH]) -#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32) -#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L]) -#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL]) -#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH]) -#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H]) -#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL]) -#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH]) -#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32) -#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L]) -#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL]) -#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH]) -#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H]) -#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL]) -#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH]) -#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32) -#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L]) -#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL]) -#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH]) -#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H]) -#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL]) -#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH]) -#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32) -#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L]) -#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL]) -#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH]) -#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H]) -#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL]) -#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH]) -#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32) -#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L]) -#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL]) -#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH]) -#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H]) -#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL]) -#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH]) -#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32) -#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L]) -#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL]) -#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH]) -#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H]) -#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL]) -#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH]) -#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32) -#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L]) -#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL]) -#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH]) -#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H]) -#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL]) -#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH]) -#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32) -#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L]) -#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL]) -#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH]) -#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H]) -#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL]) -#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH]) -#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32) -#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L]) -#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL]) -#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH]) -#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H]) -#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL]) -#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH]) -#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32) -#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L]) -#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL]) -#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH]) -#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H]) -#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL]) -#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH]) -#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32) -#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L]) -#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL]) -#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH]) -#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H]) -#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL]) -#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH]) -#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32) -#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L]) -#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL]) -#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH]) -#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H]) -#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL]) -#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH]) -#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32) -#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L]) -#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL]) -#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH]) -#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H]) -#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL]) -#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH]) -#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32) -#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L]) -#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL]) -#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH]) -#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H]) -#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL]) -#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH]) -#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32) -#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L]) -#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL]) -#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH]) -#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H]) -#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL]) -#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH]) -#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32) -#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L]) -#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL]) -#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH]) -#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H]) -#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL]) -#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH]) -#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32) -#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L]) -#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL]) -#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH]) -#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H]) -#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL]) -#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH]) -#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32) -#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L]) -#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL]) -#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH]) -#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H]) -#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL]) -#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH]) -#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32) -#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L]) -#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL]) -#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH]) -#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H]) -#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL]) -#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH]) -#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32) -#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L]) -#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL]) -#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH]) -#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H]) -#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL]) -#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH]) -#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32) -#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L]) -#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL]) -#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH]) -#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H]) -#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL]) -#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH]) -#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32) -#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L]) -#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL]) -#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH]) -#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H]) -#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL]) -#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH]) -#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32) -#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L]) -#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL]) -#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH]) -#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H]) -#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL]) -#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH]) -#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32) -#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L]) -#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL]) -#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH]) -#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H]) -#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL]) -#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH]) -#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32) -#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L]) -#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL]) -#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH]) -#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H]) -#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL]) -#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH]) -#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32) -#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L]) -#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL]) -#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH]) -#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H]) -#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL]) -#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH]) -#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32) -#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L]) -#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL]) -#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH]) -#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H]) -#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL]) -#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH]) -#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32) -#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L]) -#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL]) -#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH]) -#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H]) -#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL]) -#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH]) -#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32) -#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L]) -#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL]) -#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH]) -#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H]) -#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL]) -#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH]) -#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32) -#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L]) -#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL]) -#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH]) -#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H]) -#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL]) -#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH]) -#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32) -#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L]) -#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL]) -#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH]) -#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H]) -#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL]) -#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH]) -#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32) -#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L]) -#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL]) -#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH]) -#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H]) -#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL]) -#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH]) -#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32) -#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L]) -#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL]) -#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH]) -#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H]) -#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL]) -#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH]) -#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32) -#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L]) -#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL]) -#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH]) -#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H]) -#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL]) -#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH]) -#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32) -#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L]) -#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL]) -#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH]) -#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H]) -#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL]) -#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH]) -#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32) -#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L]) -#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL]) -#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH]) -#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H]) -#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL]) -#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH]) -#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32) -#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L]) -#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL]) -#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH]) -#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H]) -#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL]) -#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH]) -#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32) -#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L]) -#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL]) -#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH]) -#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H]) -#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL]) -#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH]) -#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32) -#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L]) -#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL]) -#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH]) -#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H]) -#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL]) -#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH]) -#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32) -#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L]) -#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL]) -#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH]) -#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H]) -#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL]) -#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH]) -#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32) -#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L]) -#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL]) -#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH]) -#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H]) -#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL]) -#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH]) -#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32) -#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L]) -#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL]) -#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH]) -#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H]) -#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL]) -#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH]) -#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32) -#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L]) -#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL]) -#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH]) -#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H]) -#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL]) -#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH]) -#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32) -#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L]) -#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL]) -#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH]) -#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H]) -#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL]) -#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH]) -#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32) -#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L]) -#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL]) -#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH]) -#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H]) -#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL]) -#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH]) -#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32) -#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L]) -#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL]) -#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH]) -#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H]) -#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL]) -#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH]) -#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32) -#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L]) -#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL]) -#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH]) -#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H]) -#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL]) -#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH]) -#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32) -#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L]) -#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL]) -#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH]) -#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H]) -#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL]) -#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH]) -#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32) -#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L]) -#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL]) -#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH]) -#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H]) -#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL]) -#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH]) -#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32) -#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L]) -#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL]) -#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH]) -#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H]) -#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL]) -#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH]) -#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32) -#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L]) -#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL]) -#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH]) -#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H]) -#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL]) -#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH]) -#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32) -#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L]) -#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL]) -#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH]) -#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H]) -#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL]) -#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH]) -#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32) -#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L]) -#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL]) -#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH]) -#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H]) -#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL]) -#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH]) -#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32) -#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L]) -#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL]) -#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH]) -#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H]) -#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL]) -#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH]) -#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32) -#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L]) -#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL]) -#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH]) -#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H]) -#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL]) -#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH]) -#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32) -#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L]) -#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL]) -#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH]) -#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H]) -#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL]) -#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH]) -#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32) -#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L]) -#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL]) -#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH]) -#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H]) -#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL]) -#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH]) -#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32) -#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L]) -#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL]) -#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH]) -#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H]) -#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL]) -#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH]) -#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32) -#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L]) -#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL]) -#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH]) -#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H]) -#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL]) -#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH]) -#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32) -#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L]) -#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL]) -#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH]) -#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H]) -#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL]) -#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH]) -#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32) -#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L]) -#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL]) -#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH]) -#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H]) -#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL]) -#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH]) -#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32) -#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L]) -#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL]) -#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH]) -#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H]) -#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL]) -#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH]) -#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32) -#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L]) -#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL]) -#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH]) -#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H]) -#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL]) -#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH]) -#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32) -#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L]) -#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL]) -#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH]) -#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H]) -#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL]) -#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH]) -#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32) -#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L]) -#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL]) -#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH]) -#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H]) -#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL]) -#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH]) -#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32) -#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L]) -#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL]) -#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH]) -#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H]) -#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL]) -#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH]) -#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32) -#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L]) -#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL]) -#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH]) -#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H]) -#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL]) -#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH]) -#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32) -#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L]) -#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL]) -#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH]) -#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H]) -#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL]) -#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH]) -#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32) -#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L]) -#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL]) -#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH]) -#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H]) -#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL]) -#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH]) -#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32) -#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L]) -#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL]) -#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH]) -#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H]) -#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL]) -#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH]) -#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32) -#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L]) -#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL]) -#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH]) -#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H]) -#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL]) -#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH]) -#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32) -#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L]) -#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL]) -#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH]) -#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H]) -#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL]) -#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH]) -#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32) -#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L]) -#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL]) -#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH]) -#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H]) -#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL]) -#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH]) -#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32) -#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L]) -#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL]) -#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH]) -#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H]) -#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL]) -#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH]) -#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32) -#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L]) -#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL]) -#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH]) -#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H]) -#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL]) -#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH]) -#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32) -#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L]) -#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL]) -#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH]) -#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H]) -#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL]) -#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH]) -#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32) -#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L]) -#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL]) -#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH]) -#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H]) -#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL]) -#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH]) -#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32) -#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L]) -#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL]) -#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH]) -#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H]) -#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL]) -#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH]) -#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32) -#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L]) -#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL]) -#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH]) -#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H]) -#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL]) -#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH]) -#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32) -#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L]) -#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL]) -#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH]) -#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H]) -#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL]) -#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH]) -#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32) -#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L]) -#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL]) -#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH]) -#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H]) -#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL]) -#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH]) -#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32) -#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L]) -#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL]) -#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH]) -#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H]) -#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL]) -#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH]) -#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32) -#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L]) -#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL]) -#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH]) -#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H]) -#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL]) -#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH]) -#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32) -#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L]) -#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL]) -#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH]) -#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H]) -#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL]) -#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH]) -#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32) -#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L]) -#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL]) -#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH]) -#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H]) -#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL]) -#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH]) -#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32) -#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L]) -#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL]) -#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH]) -#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H]) -#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL]) -#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH]) -#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32) -#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L]) -#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL]) -#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH]) -#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H]) -#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL]) -#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH]) -#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32) -#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L]) -#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL]) -#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH]) -#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H]) -#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL]) -#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH]) -#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32) -#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L]) -#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL]) -#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH]) -#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H]) -#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL]) -#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH]) -#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32) -#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L]) -#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL]) -#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH]) -#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H]) -#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL]) -#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH]) -#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32) -#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L]) -#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL]) -#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH]) -#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H]) -#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL]) -#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH]) -#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32) -#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L]) -#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL]) -#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH]) -#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H]) -#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL]) -#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH]) -#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32) -#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L]) -#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL]) -#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH]) -#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H]) -#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL]) -#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH]) -#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32) -#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L]) -#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL]) -#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH]) -#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H]) -#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL]) -#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH]) -#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32) -#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L]) -#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL]) -#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH]) -#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H]) -#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL]) -#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH]) -#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32) -#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L]) -#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL]) -#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH]) -#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H]) -#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL]) -#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH]) -#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32) -#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L]) -#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL]) -#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH]) -#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H]) -#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL]) -#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH]) -#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32) -#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L]) -#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL]) -#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH]) -#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H]) -#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL]) -#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH]) -#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32) -#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L]) -#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL]) -#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH]) -#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H]) -#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL]) -#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH]) -#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32) -#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L]) -#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL]) -#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH]) -#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H]) -#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL]) -#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH]) -#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32) -#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L]) -#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL]) -#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH]) -#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H]) -#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL]) -#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH]) -#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32) -#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L]) -#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL]) -#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH]) -#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H]) -#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL]) -#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH]) -#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32) -#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L]) -#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL]) -#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH]) -#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H]) -#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL]) -#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH]) -#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32) -#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L]) -#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL]) -#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH]) -#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H]) -#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL]) -#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH]) -#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32) -#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L]) -#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL]) -#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH]) -#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H]) -#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL]) -#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH]) -#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32) -#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L]) -#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL]) -#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH]) -#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H]) -#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL]) -#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH]) -#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32) -#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L]) -#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL]) -#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH]) -#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H]) -#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL]) -#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH]) -#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32) -#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L]) -#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL]) -#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH]) -#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H]) -#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL]) -#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH]) -#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32) -#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L]) -#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL]) -#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH]) -#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H]) -#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL]) -#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH]) -#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32) -#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L]) -#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL]) -#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH]) -#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H]) -#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL]) -#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH]) -#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32) -#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L]) -#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL]) -#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH]) -#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H]) -#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL]) -#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH]) -#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32) -#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L]) -#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL]) -#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH]) -#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H]) -#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL]) -#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH]) -#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32) -#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L]) -#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL]) -#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH]) -#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H]) -#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL]) -#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH]) -#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32) -#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L]) -#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL]) -#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH]) -#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H]) -#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL]) -#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH]) -#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32) -#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L]) -#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL]) -#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH]) -#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H]) -#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL]) -#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH]) -#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32) -#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L]) -#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL]) -#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH]) -#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H]) -#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL]) -#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH]) -#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32) -#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L]) -#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL]) -#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH]) -#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H]) -#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL]) -#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH]) -#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32) -#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L]) -#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL]) -#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH]) -#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H]) -#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL]) -#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH]) -#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32) -#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L]) -#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL]) -#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH]) -#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H]) -#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL]) -#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH]) -#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32) -#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L]) -#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL]) -#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH]) -#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H]) -#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL]) -#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH]) -#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32) -#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L]) -#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL]) -#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH]) -#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H]) -#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL]) -#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH]) -#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32) -#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L]) -#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL]) -#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH]) -#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H]) -#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL]) -#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH]) -#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32) -#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L]) -#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL]) -#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH]) -#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H]) -#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL]) -#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH]) -#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32) -#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L]) -#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL]) -#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH]) -#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H]) -#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL]) -#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH]) -#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32) -#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L]) -#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL]) -#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH]) -#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H]) -#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL]) -#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH]) -#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32) -#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L]) -#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL]) -#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH]) -#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H]) -#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL]) -#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH]) -#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32) -#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L]) -#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL]) -#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH]) -#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H]) -#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL]) -#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH]) -#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32) -#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L]) -#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL]) -#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH]) -#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H]) -#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL]) -#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH]) -#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32) -#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L]) -#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL]) -#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH]) -#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H]) -#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL]) -#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH]) -#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32) -#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L]) -#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL]) -#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH]) -#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H]) -#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL]) -#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH]) -#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32) -#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L]) -#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL]) -#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH]) -#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H]) -#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL]) -#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH]) -#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32) -#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L]) -#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL]) -#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH]) -#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H]) -#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL]) -#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH]) -#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32) -#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L]) -#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL]) -#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH]) -#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H]) -#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL]) -#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH]) -#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32) -#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L]) -#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL]) -#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH]) -#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H]) -#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL]) -#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH]) -#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32) -#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L]) -#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL]) -#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH]) -#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H]) -#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL]) -#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH]) -#define RSCAN0RMID32 (RSCAN0.RMID32.UINT32) -#define RSCAN0RMID32L (RSCAN0.RMID32.UINT16[R_IO_L]) -#define RSCAN0RMID32LL (RSCAN0.RMID32.UINT8[R_IO_LL]) -#define RSCAN0RMID32LH (RSCAN0.RMID32.UINT8[R_IO_LH]) -#define RSCAN0RMID32H (RSCAN0.RMID32.UINT16[R_IO_H]) -#define RSCAN0RMID32HL (RSCAN0.RMID32.UINT8[R_IO_HL]) -#define RSCAN0RMID32HH (RSCAN0.RMID32.UINT8[R_IO_HH]) -#define RSCAN0RMPTR32 (RSCAN0.RMPTR32.UINT32) -#define RSCAN0RMPTR32L (RSCAN0.RMPTR32.UINT16[R_IO_L]) -#define RSCAN0RMPTR32LL (RSCAN0.RMPTR32.UINT8[R_IO_LL]) -#define RSCAN0RMPTR32LH (RSCAN0.RMPTR32.UINT8[R_IO_LH]) -#define RSCAN0RMPTR32H (RSCAN0.RMPTR32.UINT16[R_IO_H]) -#define RSCAN0RMPTR32HL (RSCAN0.RMPTR32.UINT8[R_IO_HL]) -#define RSCAN0RMPTR32HH (RSCAN0.RMPTR32.UINT8[R_IO_HH]) -#define RSCAN0RMDF032 (RSCAN0.RMDF032.UINT32) -#define RSCAN0RMDF032L (RSCAN0.RMDF032.UINT16[R_IO_L]) -#define RSCAN0RMDF032LL (RSCAN0.RMDF032.UINT8[R_IO_LL]) -#define RSCAN0RMDF032LH (RSCAN0.RMDF032.UINT8[R_IO_LH]) -#define RSCAN0RMDF032H (RSCAN0.RMDF032.UINT16[R_IO_H]) -#define RSCAN0RMDF032HL (RSCAN0.RMDF032.UINT8[R_IO_HL]) -#define RSCAN0RMDF032HH (RSCAN0.RMDF032.UINT8[R_IO_HH]) -#define RSCAN0RMDF132 (RSCAN0.RMDF132.UINT32) -#define RSCAN0RMDF132L (RSCAN0.RMDF132.UINT16[R_IO_L]) -#define RSCAN0RMDF132LL (RSCAN0.RMDF132.UINT8[R_IO_LL]) -#define RSCAN0RMDF132LH (RSCAN0.RMDF132.UINT8[R_IO_LH]) -#define RSCAN0RMDF132H (RSCAN0.RMDF132.UINT16[R_IO_H]) -#define RSCAN0RMDF132HL (RSCAN0.RMDF132.UINT8[R_IO_HL]) -#define RSCAN0RMDF132HH (RSCAN0.RMDF132.UINT8[R_IO_HH]) -#define RSCAN0RMID33 (RSCAN0.RMID33.UINT32) -#define RSCAN0RMID33L (RSCAN0.RMID33.UINT16[R_IO_L]) -#define RSCAN0RMID33LL (RSCAN0.RMID33.UINT8[R_IO_LL]) -#define RSCAN0RMID33LH (RSCAN0.RMID33.UINT8[R_IO_LH]) -#define RSCAN0RMID33H (RSCAN0.RMID33.UINT16[R_IO_H]) -#define RSCAN0RMID33HL (RSCAN0.RMID33.UINT8[R_IO_HL]) -#define RSCAN0RMID33HH (RSCAN0.RMID33.UINT8[R_IO_HH]) -#define RSCAN0RMPTR33 (RSCAN0.RMPTR33.UINT32) -#define RSCAN0RMPTR33L (RSCAN0.RMPTR33.UINT16[R_IO_L]) -#define RSCAN0RMPTR33LL (RSCAN0.RMPTR33.UINT8[R_IO_LL]) -#define RSCAN0RMPTR33LH (RSCAN0.RMPTR33.UINT8[R_IO_LH]) -#define RSCAN0RMPTR33H (RSCAN0.RMPTR33.UINT16[R_IO_H]) -#define RSCAN0RMPTR33HL (RSCAN0.RMPTR33.UINT8[R_IO_HL]) -#define RSCAN0RMPTR33HH (RSCAN0.RMPTR33.UINT8[R_IO_HH]) -#define RSCAN0RMDF033 (RSCAN0.RMDF033.UINT32) -#define RSCAN0RMDF033L (RSCAN0.RMDF033.UINT16[R_IO_L]) -#define RSCAN0RMDF033LL (RSCAN0.RMDF033.UINT8[R_IO_LL]) -#define RSCAN0RMDF033LH (RSCAN0.RMDF033.UINT8[R_IO_LH]) -#define RSCAN0RMDF033H (RSCAN0.RMDF033.UINT16[R_IO_H]) -#define RSCAN0RMDF033HL (RSCAN0.RMDF033.UINT8[R_IO_HL]) -#define RSCAN0RMDF033HH (RSCAN0.RMDF033.UINT8[R_IO_HH]) -#define RSCAN0RMDF133 (RSCAN0.RMDF133.UINT32) -#define RSCAN0RMDF133L (RSCAN0.RMDF133.UINT16[R_IO_L]) -#define RSCAN0RMDF133LL (RSCAN0.RMDF133.UINT8[R_IO_LL]) -#define RSCAN0RMDF133LH (RSCAN0.RMDF133.UINT8[R_IO_LH]) -#define RSCAN0RMDF133H (RSCAN0.RMDF133.UINT16[R_IO_H]) -#define RSCAN0RMDF133HL (RSCAN0.RMDF133.UINT8[R_IO_HL]) -#define RSCAN0RMDF133HH (RSCAN0.RMDF133.UINT8[R_IO_HH]) -#define RSCAN0RMID34 (RSCAN0.RMID34.UINT32) -#define RSCAN0RMID34L (RSCAN0.RMID34.UINT16[R_IO_L]) -#define RSCAN0RMID34LL (RSCAN0.RMID34.UINT8[R_IO_LL]) -#define RSCAN0RMID34LH (RSCAN0.RMID34.UINT8[R_IO_LH]) -#define RSCAN0RMID34H (RSCAN0.RMID34.UINT16[R_IO_H]) -#define RSCAN0RMID34HL (RSCAN0.RMID34.UINT8[R_IO_HL]) -#define RSCAN0RMID34HH (RSCAN0.RMID34.UINT8[R_IO_HH]) -#define RSCAN0RMPTR34 (RSCAN0.RMPTR34.UINT32) -#define RSCAN0RMPTR34L (RSCAN0.RMPTR34.UINT16[R_IO_L]) -#define RSCAN0RMPTR34LL (RSCAN0.RMPTR34.UINT8[R_IO_LL]) -#define RSCAN0RMPTR34LH (RSCAN0.RMPTR34.UINT8[R_IO_LH]) -#define RSCAN0RMPTR34H (RSCAN0.RMPTR34.UINT16[R_IO_H]) -#define RSCAN0RMPTR34HL (RSCAN0.RMPTR34.UINT8[R_IO_HL]) -#define RSCAN0RMPTR34HH (RSCAN0.RMPTR34.UINT8[R_IO_HH]) -#define RSCAN0RMDF034 (RSCAN0.RMDF034.UINT32) -#define RSCAN0RMDF034L (RSCAN0.RMDF034.UINT16[R_IO_L]) -#define RSCAN0RMDF034LL (RSCAN0.RMDF034.UINT8[R_IO_LL]) -#define RSCAN0RMDF034LH (RSCAN0.RMDF034.UINT8[R_IO_LH]) -#define RSCAN0RMDF034H (RSCAN0.RMDF034.UINT16[R_IO_H]) -#define RSCAN0RMDF034HL (RSCAN0.RMDF034.UINT8[R_IO_HL]) -#define RSCAN0RMDF034HH (RSCAN0.RMDF034.UINT8[R_IO_HH]) -#define RSCAN0RMDF134 (RSCAN0.RMDF134.UINT32) -#define RSCAN0RMDF134L (RSCAN0.RMDF134.UINT16[R_IO_L]) -#define RSCAN0RMDF134LL (RSCAN0.RMDF134.UINT8[R_IO_LL]) -#define RSCAN0RMDF134LH (RSCAN0.RMDF134.UINT8[R_IO_LH]) -#define RSCAN0RMDF134H (RSCAN0.RMDF134.UINT16[R_IO_H]) -#define RSCAN0RMDF134HL (RSCAN0.RMDF134.UINT8[R_IO_HL]) -#define RSCAN0RMDF134HH (RSCAN0.RMDF134.UINT8[R_IO_HH]) -#define RSCAN0RMID35 (RSCAN0.RMID35.UINT32) -#define RSCAN0RMID35L (RSCAN0.RMID35.UINT16[R_IO_L]) -#define RSCAN0RMID35LL (RSCAN0.RMID35.UINT8[R_IO_LL]) -#define RSCAN0RMID35LH (RSCAN0.RMID35.UINT8[R_IO_LH]) -#define RSCAN0RMID35H (RSCAN0.RMID35.UINT16[R_IO_H]) -#define RSCAN0RMID35HL (RSCAN0.RMID35.UINT8[R_IO_HL]) -#define RSCAN0RMID35HH (RSCAN0.RMID35.UINT8[R_IO_HH]) -#define RSCAN0RMPTR35 (RSCAN0.RMPTR35.UINT32) -#define RSCAN0RMPTR35L (RSCAN0.RMPTR35.UINT16[R_IO_L]) -#define RSCAN0RMPTR35LL (RSCAN0.RMPTR35.UINT8[R_IO_LL]) -#define RSCAN0RMPTR35LH (RSCAN0.RMPTR35.UINT8[R_IO_LH]) -#define RSCAN0RMPTR35H (RSCAN0.RMPTR35.UINT16[R_IO_H]) -#define RSCAN0RMPTR35HL (RSCAN0.RMPTR35.UINT8[R_IO_HL]) -#define RSCAN0RMPTR35HH (RSCAN0.RMPTR35.UINT8[R_IO_HH]) -#define RSCAN0RMDF035 (RSCAN0.RMDF035.UINT32) -#define RSCAN0RMDF035L (RSCAN0.RMDF035.UINT16[R_IO_L]) -#define RSCAN0RMDF035LL (RSCAN0.RMDF035.UINT8[R_IO_LL]) -#define RSCAN0RMDF035LH (RSCAN0.RMDF035.UINT8[R_IO_LH]) -#define RSCAN0RMDF035H (RSCAN0.RMDF035.UINT16[R_IO_H]) -#define RSCAN0RMDF035HL (RSCAN0.RMDF035.UINT8[R_IO_HL]) -#define RSCAN0RMDF035HH (RSCAN0.RMDF035.UINT8[R_IO_HH]) -#define RSCAN0RMDF135 (RSCAN0.RMDF135.UINT32) -#define RSCAN0RMDF135L (RSCAN0.RMDF135.UINT16[R_IO_L]) -#define RSCAN0RMDF135LL (RSCAN0.RMDF135.UINT8[R_IO_LL]) -#define RSCAN0RMDF135LH (RSCAN0.RMDF135.UINT8[R_IO_LH]) -#define RSCAN0RMDF135H (RSCAN0.RMDF135.UINT16[R_IO_H]) -#define RSCAN0RMDF135HL (RSCAN0.RMDF135.UINT8[R_IO_HL]) -#define RSCAN0RMDF135HH (RSCAN0.RMDF135.UINT8[R_IO_HH]) -#define RSCAN0RMID36 (RSCAN0.RMID36.UINT32) -#define RSCAN0RMID36L (RSCAN0.RMID36.UINT16[R_IO_L]) -#define RSCAN0RMID36LL (RSCAN0.RMID36.UINT8[R_IO_LL]) -#define RSCAN0RMID36LH (RSCAN0.RMID36.UINT8[R_IO_LH]) -#define RSCAN0RMID36H (RSCAN0.RMID36.UINT16[R_IO_H]) -#define RSCAN0RMID36HL (RSCAN0.RMID36.UINT8[R_IO_HL]) -#define RSCAN0RMID36HH (RSCAN0.RMID36.UINT8[R_IO_HH]) -#define RSCAN0RMPTR36 (RSCAN0.RMPTR36.UINT32) -#define RSCAN0RMPTR36L (RSCAN0.RMPTR36.UINT16[R_IO_L]) -#define RSCAN0RMPTR36LL (RSCAN0.RMPTR36.UINT8[R_IO_LL]) -#define RSCAN0RMPTR36LH (RSCAN0.RMPTR36.UINT8[R_IO_LH]) -#define RSCAN0RMPTR36H (RSCAN0.RMPTR36.UINT16[R_IO_H]) -#define RSCAN0RMPTR36HL (RSCAN0.RMPTR36.UINT8[R_IO_HL]) -#define RSCAN0RMPTR36HH (RSCAN0.RMPTR36.UINT8[R_IO_HH]) -#define RSCAN0RMDF036 (RSCAN0.RMDF036.UINT32) -#define RSCAN0RMDF036L (RSCAN0.RMDF036.UINT16[R_IO_L]) -#define RSCAN0RMDF036LL (RSCAN0.RMDF036.UINT8[R_IO_LL]) -#define RSCAN0RMDF036LH (RSCAN0.RMDF036.UINT8[R_IO_LH]) -#define RSCAN0RMDF036H (RSCAN0.RMDF036.UINT16[R_IO_H]) -#define RSCAN0RMDF036HL (RSCAN0.RMDF036.UINT8[R_IO_HL]) -#define RSCAN0RMDF036HH (RSCAN0.RMDF036.UINT8[R_IO_HH]) -#define RSCAN0RMDF136 (RSCAN0.RMDF136.UINT32) -#define RSCAN0RMDF136L (RSCAN0.RMDF136.UINT16[R_IO_L]) -#define RSCAN0RMDF136LL (RSCAN0.RMDF136.UINT8[R_IO_LL]) -#define RSCAN0RMDF136LH (RSCAN0.RMDF136.UINT8[R_IO_LH]) -#define RSCAN0RMDF136H (RSCAN0.RMDF136.UINT16[R_IO_H]) -#define RSCAN0RMDF136HL (RSCAN0.RMDF136.UINT8[R_IO_HL]) -#define RSCAN0RMDF136HH (RSCAN0.RMDF136.UINT8[R_IO_HH]) -#define RSCAN0RMID37 (RSCAN0.RMID37.UINT32) -#define RSCAN0RMID37L (RSCAN0.RMID37.UINT16[R_IO_L]) -#define RSCAN0RMID37LL (RSCAN0.RMID37.UINT8[R_IO_LL]) -#define RSCAN0RMID37LH (RSCAN0.RMID37.UINT8[R_IO_LH]) -#define RSCAN0RMID37H (RSCAN0.RMID37.UINT16[R_IO_H]) -#define RSCAN0RMID37HL (RSCAN0.RMID37.UINT8[R_IO_HL]) -#define RSCAN0RMID37HH (RSCAN0.RMID37.UINT8[R_IO_HH]) -#define RSCAN0RMPTR37 (RSCAN0.RMPTR37.UINT32) -#define RSCAN0RMPTR37L (RSCAN0.RMPTR37.UINT16[R_IO_L]) -#define RSCAN0RMPTR37LL (RSCAN0.RMPTR37.UINT8[R_IO_LL]) -#define RSCAN0RMPTR37LH (RSCAN0.RMPTR37.UINT8[R_IO_LH]) -#define RSCAN0RMPTR37H (RSCAN0.RMPTR37.UINT16[R_IO_H]) -#define RSCAN0RMPTR37HL (RSCAN0.RMPTR37.UINT8[R_IO_HL]) -#define RSCAN0RMPTR37HH (RSCAN0.RMPTR37.UINT8[R_IO_HH]) -#define RSCAN0RMDF037 (RSCAN0.RMDF037.UINT32) -#define RSCAN0RMDF037L (RSCAN0.RMDF037.UINT16[R_IO_L]) -#define RSCAN0RMDF037LL (RSCAN0.RMDF037.UINT8[R_IO_LL]) -#define RSCAN0RMDF037LH (RSCAN0.RMDF037.UINT8[R_IO_LH]) -#define RSCAN0RMDF037H (RSCAN0.RMDF037.UINT16[R_IO_H]) -#define RSCAN0RMDF037HL (RSCAN0.RMDF037.UINT8[R_IO_HL]) -#define RSCAN0RMDF037HH (RSCAN0.RMDF037.UINT8[R_IO_HH]) -#define RSCAN0RMDF137 (RSCAN0.RMDF137.UINT32) -#define RSCAN0RMDF137L (RSCAN0.RMDF137.UINT16[R_IO_L]) -#define RSCAN0RMDF137LL (RSCAN0.RMDF137.UINT8[R_IO_LL]) -#define RSCAN0RMDF137LH (RSCAN0.RMDF137.UINT8[R_IO_LH]) -#define RSCAN0RMDF137H (RSCAN0.RMDF137.UINT16[R_IO_H]) -#define RSCAN0RMDF137HL (RSCAN0.RMDF137.UINT8[R_IO_HL]) -#define RSCAN0RMDF137HH (RSCAN0.RMDF137.UINT8[R_IO_HH]) -#define RSCAN0RMID38 (RSCAN0.RMID38.UINT32) -#define RSCAN0RMID38L (RSCAN0.RMID38.UINT16[R_IO_L]) -#define RSCAN0RMID38LL (RSCAN0.RMID38.UINT8[R_IO_LL]) -#define RSCAN0RMID38LH (RSCAN0.RMID38.UINT8[R_IO_LH]) -#define RSCAN0RMID38H (RSCAN0.RMID38.UINT16[R_IO_H]) -#define RSCAN0RMID38HL (RSCAN0.RMID38.UINT8[R_IO_HL]) -#define RSCAN0RMID38HH (RSCAN0.RMID38.UINT8[R_IO_HH]) -#define RSCAN0RMPTR38 (RSCAN0.RMPTR38.UINT32) -#define RSCAN0RMPTR38L (RSCAN0.RMPTR38.UINT16[R_IO_L]) -#define RSCAN0RMPTR38LL (RSCAN0.RMPTR38.UINT8[R_IO_LL]) -#define RSCAN0RMPTR38LH (RSCAN0.RMPTR38.UINT8[R_IO_LH]) -#define RSCAN0RMPTR38H (RSCAN0.RMPTR38.UINT16[R_IO_H]) -#define RSCAN0RMPTR38HL (RSCAN0.RMPTR38.UINT8[R_IO_HL]) -#define RSCAN0RMPTR38HH (RSCAN0.RMPTR38.UINT8[R_IO_HH]) -#define RSCAN0RMDF038 (RSCAN0.RMDF038.UINT32) -#define RSCAN0RMDF038L (RSCAN0.RMDF038.UINT16[R_IO_L]) -#define RSCAN0RMDF038LL (RSCAN0.RMDF038.UINT8[R_IO_LL]) -#define RSCAN0RMDF038LH (RSCAN0.RMDF038.UINT8[R_IO_LH]) -#define RSCAN0RMDF038H (RSCAN0.RMDF038.UINT16[R_IO_H]) -#define RSCAN0RMDF038HL (RSCAN0.RMDF038.UINT8[R_IO_HL]) -#define RSCAN0RMDF038HH (RSCAN0.RMDF038.UINT8[R_IO_HH]) -#define RSCAN0RMDF138 (RSCAN0.RMDF138.UINT32) -#define RSCAN0RMDF138L (RSCAN0.RMDF138.UINT16[R_IO_L]) -#define RSCAN0RMDF138LL (RSCAN0.RMDF138.UINT8[R_IO_LL]) -#define RSCAN0RMDF138LH (RSCAN0.RMDF138.UINT8[R_IO_LH]) -#define RSCAN0RMDF138H (RSCAN0.RMDF138.UINT16[R_IO_H]) -#define RSCAN0RMDF138HL (RSCAN0.RMDF138.UINT8[R_IO_HL]) -#define RSCAN0RMDF138HH (RSCAN0.RMDF138.UINT8[R_IO_HH]) -#define RSCAN0RMID39 (RSCAN0.RMID39.UINT32) -#define RSCAN0RMID39L (RSCAN0.RMID39.UINT16[R_IO_L]) -#define RSCAN0RMID39LL (RSCAN0.RMID39.UINT8[R_IO_LL]) -#define RSCAN0RMID39LH (RSCAN0.RMID39.UINT8[R_IO_LH]) -#define RSCAN0RMID39H (RSCAN0.RMID39.UINT16[R_IO_H]) -#define RSCAN0RMID39HL (RSCAN0.RMID39.UINT8[R_IO_HL]) -#define RSCAN0RMID39HH (RSCAN0.RMID39.UINT8[R_IO_HH]) -#define RSCAN0RMPTR39 (RSCAN0.RMPTR39.UINT32) -#define RSCAN0RMPTR39L (RSCAN0.RMPTR39.UINT16[R_IO_L]) -#define RSCAN0RMPTR39LL (RSCAN0.RMPTR39.UINT8[R_IO_LL]) -#define RSCAN0RMPTR39LH (RSCAN0.RMPTR39.UINT8[R_IO_LH]) -#define RSCAN0RMPTR39H (RSCAN0.RMPTR39.UINT16[R_IO_H]) -#define RSCAN0RMPTR39HL (RSCAN0.RMPTR39.UINT8[R_IO_HL]) -#define RSCAN0RMPTR39HH (RSCAN0.RMPTR39.UINT8[R_IO_HH]) -#define RSCAN0RMDF039 (RSCAN0.RMDF039.UINT32) -#define RSCAN0RMDF039L (RSCAN0.RMDF039.UINT16[R_IO_L]) -#define RSCAN0RMDF039LL (RSCAN0.RMDF039.UINT8[R_IO_LL]) -#define RSCAN0RMDF039LH (RSCAN0.RMDF039.UINT8[R_IO_LH]) -#define RSCAN0RMDF039H (RSCAN0.RMDF039.UINT16[R_IO_H]) -#define RSCAN0RMDF039HL (RSCAN0.RMDF039.UINT8[R_IO_HL]) -#define RSCAN0RMDF039HH (RSCAN0.RMDF039.UINT8[R_IO_HH]) -#define RSCAN0RMDF139 (RSCAN0.RMDF139.UINT32) -#define RSCAN0RMDF139L (RSCAN0.RMDF139.UINT16[R_IO_L]) -#define RSCAN0RMDF139LL (RSCAN0.RMDF139.UINT8[R_IO_LL]) -#define RSCAN0RMDF139LH (RSCAN0.RMDF139.UINT8[R_IO_LH]) -#define RSCAN0RMDF139H (RSCAN0.RMDF139.UINT16[R_IO_H]) -#define RSCAN0RMDF139HL (RSCAN0.RMDF139.UINT8[R_IO_HL]) -#define RSCAN0RMDF139HH (RSCAN0.RMDF139.UINT8[R_IO_HH]) -#define RSCAN0RMID40 (RSCAN0.RMID40.UINT32) -#define RSCAN0RMID40L (RSCAN0.RMID40.UINT16[R_IO_L]) -#define RSCAN0RMID40LL (RSCAN0.RMID40.UINT8[R_IO_LL]) -#define RSCAN0RMID40LH (RSCAN0.RMID40.UINT8[R_IO_LH]) -#define RSCAN0RMID40H (RSCAN0.RMID40.UINT16[R_IO_H]) -#define RSCAN0RMID40HL (RSCAN0.RMID40.UINT8[R_IO_HL]) -#define RSCAN0RMID40HH (RSCAN0.RMID40.UINT8[R_IO_HH]) -#define RSCAN0RMPTR40 (RSCAN0.RMPTR40.UINT32) -#define RSCAN0RMPTR40L (RSCAN0.RMPTR40.UINT16[R_IO_L]) -#define RSCAN0RMPTR40LL (RSCAN0.RMPTR40.UINT8[R_IO_LL]) -#define RSCAN0RMPTR40LH (RSCAN0.RMPTR40.UINT8[R_IO_LH]) -#define RSCAN0RMPTR40H (RSCAN0.RMPTR40.UINT16[R_IO_H]) -#define RSCAN0RMPTR40HL (RSCAN0.RMPTR40.UINT8[R_IO_HL]) -#define RSCAN0RMPTR40HH (RSCAN0.RMPTR40.UINT8[R_IO_HH]) -#define RSCAN0RMDF040 (RSCAN0.RMDF040.UINT32) -#define RSCAN0RMDF040L (RSCAN0.RMDF040.UINT16[R_IO_L]) -#define RSCAN0RMDF040LL (RSCAN0.RMDF040.UINT8[R_IO_LL]) -#define RSCAN0RMDF040LH (RSCAN0.RMDF040.UINT8[R_IO_LH]) -#define RSCAN0RMDF040H (RSCAN0.RMDF040.UINT16[R_IO_H]) -#define RSCAN0RMDF040HL (RSCAN0.RMDF040.UINT8[R_IO_HL]) -#define RSCAN0RMDF040HH (RSCAN0.RMDF040.UINT8[R_IO_HH]) -#define RSCAN0RMDF140 (RSCAN0.RMDF140.UINT32) -#define RSCAN0RMDF140L (RSCAN0.RMDF140.UINT16[R_IO_L]) -#define RSCAN0RMDF140LL (RSCAN0.RMDF140.UINT8[R_IO_LL]) -#define RSCAN0RMDF140LH (RSCAN0.RMDF140.UINT8[R_IO_LH]) -#define RSCAN0RMDF140H (RSCAN0.RMDF140.UINT16[R_IO_H]) -#define RSCAN0RMDF140HL (RSCAN0.RMDF140.UINT8[R_IO_HL]) -#define RSCAN0RMDF140HH (RSCAN0.RMDF140.UINT8[R_IO_HH]) -#define RSCAN0RMID41 (RSCAN0.RMID41.UINT32) -#define RSCAN0RMID41L (RSCAN0.RMID41.UINT16[R_IO_L]) -#define RSCAN0RMID41LL (RSCAN0.RMID41.UINT8[R_IO_LL]) -#define RSCAN0RMID41LH (RSCAN0.RMID41.UINT8[R_IO_LH]) -#define RSCAN0RMID41H (RSCAN0.RMID41.UINT16[R_IO_H]) -#define RSCAN0RMID41HL (RSCAN0.RMID41.UINT8[R_IO_HL]) -#define RSCAN0RMID41HH (RSCAN0.RMID41.UINT8[R_IO_HH]) -#define RSCAN0RMPTR41 (RSCAN0.RMPTR41.UINT32) -#define RSCAN0RMPTR41L (RSCAN0.RMPTR41.UINT16[R_IO_L]) -#define RSCAN0RMPTR41LL (RSCAN0.RMPTR41.UINT8[R_IO_LL]) -#define RSCAN0RMPTR41LH (RSCAN0.RMPTR41.UINT8[R_IO_LH]) -#define RSCAN0RMPTR41H (RSCAN0.RMPTR41.UINT16[R_IO_H]) -#define RSCAN0RMPTR41HL (RSCAN0.RMPTR41.UINT8[R_IO_HL]) -#define RSCAN0RMPTR41HH (RSCAN0.RMPTR41.UINT8[R_IO_HH]) -#define RSCAN0RMDF041 (RSCAN0.RMDF041.UINT32) -#define RSCAN0RMDF041L (RSCAN0.RMDF041.UINT16[R_IO_L]) -#define RSCAN0RMDF041LL (RSCAN0.RMDF041.UINT8[R_IO_LL]) -#define RSCAN0RMDF041LH (RSCAN0.RMDF041.UINT8[R_IO_LH]) -#define RSCAN0RMDF041H (RSCAN0.RMDF041.UINT16[R_IO_H]) -#define RSCAN0RMDF041HL (RSCAN0.RMDF041.UINT8[R_IO_HL]) -#define RSCAN0RMDF041HH (RSCAN0.RMDF041.UINT8[R_IO_HH]) -#define RSCAN0RMDF141 (RSCAN0.RMDF141.UINT32) -#define RSCAN0RMDF141L (RSCAN0.RMDF141.UINT16[R_IO_L]) -#define RSCAN0RMDF141LL (RSCAN0.RMDF141.UINT8[R_IO_LL]) -#define RSCAN0RMDF141LH (RSCAN0.RMDF141.UINT8[R_IO_LH]) -#define RSCAN0RMDF141H (RSCAN0.RMDF141.UINT16[R_IO_H]) -#define RSCAN0RMDF141HL (RSCAN0.RMDF141.UINT8[R_IO_HL]) -#define RSCAN0RMDF141HH (RSCAN0.RMDF141.UINT8[R_IO_HH]) -#define RSCAN0RMID42 (RSCAN0.RMID42.UINT32) -#define RSCAN0RMID42L (RSCAN0.RMID42.UINT16[R_IO_L]) -#define RSCAN0RMID42LL (RSCAN0.RMID42.UINT8[R_IO_LL]) -#define RSCAN0RMID42LH (RSCAN0.RMID42.UINT8[R_IO_LH]) -#define RSCAN0RMID42H (RSCAN0.RMID42.UINT16[R_IO_H]) -#define RSCAN0RMID42HL (RSCAN0.RMID42.UINT8[R_IO_HL]) -#define RSCAN0RMID42HH (RSCAN0.RMID42.UINT8[R_IO_HH]) -#define RSCAN0RMPTR42 (RSCAN0.RMPTR42.UINT32) -#define RSCAN0RMPTR42L (RSCAN0.RMPTR42.UINT16[R_IO_L]) -#define RSCAN0RMPTR42LL (RSCAN0.RMPTR42.UINT8[R_IO_LL]) -#define RSCAN0RMPTR42LH (RSCAN0.RMPTR42.UINT8[R_IO_LH]) -#define RSCAN0RMPTR42H (RSCAN0.RMPTR42.UINT16[R_IO_H]) -#define RSCAN0RMPTR42HL (RSCAN0.RMPTR42.UINT8[R_IO_HL]) -#define RSCAN0RMPTR42HH (RSCAN0.RMPTR42.UINT8[R_IO_HH]) -#define RSCAN0RMDF042 (RSCAN0.RMDF042.UINT32) -#define RSCAN0RMDF042L (RSCAN0.RMDF042.UINT16[R_IO_L]) -#define RSCAN0RMDF042LL (RSCAN0.RMDF042.UINT8[R_IO_LL]) -#define RSCAN0RMDF042LH (RSCAN0.RMDF042.UINT8[R_IO_LH]) -#define RSCAN0RMDF042H (RSCAN0.RMDF042.UINT16[R_IO_H]) -#define RSCAN0RMDF042HL (RSCAN0.RMDF042.UINT8[R_IO_HL]) -#define RSCAN0RMDF042HH (RSCAN0.RMDF042.UINT8[R_IO_HH]) -#define RSCAN0RMDF142 (RSCAN0.RMDF142.UINT32) -#define RSCAN0RMDF142L (RSCAN0.RMDF142.UINT16[R_IO_L]) -#define RSCAN0RMDF142LL (RSCAN0.RMDF142.UINT8[R_IO_LL]) -#define RSCAN0RMDF142LH (RSCAN0.RMDF142.UINT8[R_IO_LH]) -#define RSCAN0RMDF142H (RSCAN0.RMDF142.UINT16[R_IO_H]) -#define RSCAN0RMDF142HL (RSCAN0.RMDF142.UINT8[R_IO_HL]) -#define RSCAN0RMDF142HH (RSCAN0.RMDF142.UINT8[R_IO_HH]) -#define RSCAN0RMID43 (RSCAN0.RMID43.UINT32) -#define RSCAN0RMID43L (RSCAN0.RMID43.UINT16[R_IO_L]) -#define RSCAN0RMID43LL (RSCAN0.RMID43.UINT8[R_IO_LL]) -#define RSCAN0RMID43LH (RSCAN0.RMID43.UINT8[R_IO_LH]) -#define RSCAN0RMID43H (RSCAN0.RMID43.UINT16[R_IO_H]) -#define RSCAN0RMID43HL (RSCAN0.RMID43.UINT8[R_IO_HL]) -#define RSCAN0RMID43HH (RSCAN0.RMID43.UINT8[R_IO_HH]) -#define RSCAN0RMPTR43 (RSCAN0.RMPTR43.UINT32) -#define RSCAN0RMPTR43L (RSCAN0.RMPTR43.UINT16[R_IO_L]) -#define RSCAN0RMPTR43LL (RSCAN0.RMPTR43.UINT8[R_IO_LL]) -#define RSCAN0RMPTR43LH (RSCAN0.RMPTR43.UINT8[R_IO_LH]) -#define RSCAN0RMPTR43H (RSCAN0.RMPTR43.UINT16[R_IO_H]) -#define RSCAN0RMPTR43HL (RSCAN0.RMPTR43.UINT8[R_IO_HL]) -#define RSCAN0RMPTR43HH (RSCAN0.RMPTR43.UINT8[R_IO_HH]) -#define RSCAN0RMDF043 (RSCAN0.RMDF043.UINT32) -#define RSCAN0RMDF043L (RSCAN0.RMDF043.UINT16[R_IO_L]) -#define RSCAN0RMDF043LL (RSCAN0.RMDF043.UINT8[R_IO_LL]) -#define RSCAN0RMDF043LH (RSCAN0.RMDF043.UINT8[R_IO_LH]) -#define RSCAN0RMDF043H (RSCAN0.RMDF043.UINT16[R_IO_H]) -#define RSCAN0RMDF043HL (RSCAN0.RMDF043.UINT8[R_IO_HL]) -#define RSCAN0RMDF043HH (RSCAN0.RMDF043.UINT8[R_IO_HH]) -#define RSCAN0RMDF143 (RSCAN0.RMDF143.UINT32) -#define RSCAN0RMDF143L (RSCAN0.RMDF143.UINT16[R_IO_L]) -#define RSCAN0RMDF143LL (RSCAN0.RMDF143.UINT8[R_IO_LL]) -#define RSCAN0RMDF143LH (RSCAN0.RMDF143.UINT8[R_IO_LH]) -#define RSCAN0RMDF143H (RSCAN0.RMDF143.UINT16[R_IO_H]) -#define RSCAN0RMDF143HL (RSCAN0.RMDF143.UINT8[R_IO_HL]) -#define RSCAN0RMDF143HH (RSCAN0.RMDF143.UINT8[R_IO_HH]) -#define RSCAN0RMID44 (RSCAN0.RMID44.UINT32) -#define RSCAN0RMID44L (RSCAN0.RMID44.UINT16[R_IO_L]) -#define RSCAN0RMID44LL (RSCAN0.RMID44.UINT8[R_IO_LL]) -#define RSCAN0RMID44LH (RSCAN0.RMID44.UINT8[R_IO_LH]) -#define RSCAN0RMID44H (RSCAN0.RMID44.UINT16[R_IO_H]) -#define RSCAN0RMID44HL (RSCAN0.RMID44.UINT8[R_IO_HL]) -#define RSCAN0RMID44HH (RSCAN0.RMID44.UINT8[R_IO_HH]) -#define RSCAN0RMPTR44 (RSCAN0.RMPTR44.UINT32) -#define RSCAN0RMPTR44L (RSCAN0.RMPTR44.UINT16[R_IO_L]) -#define RSCAN0RMPTR44LL (RSCAN0.RMPTR44.UINT8[R_IO_LL]) -#define RSCAN0RMPTR44LH (RSCAN0.RMPTR44.UINT8[R_IO_LH]) -#define RSCAN0RMPTR44H (RSCAN0.RMPTR44.UINT16[R_IO_H]) -#define RSCAN0RMPTR44HL (RSCAN0.RMPTR44.UINT8[R_IO_HL]) -#define RSCAN0RMPTR44HH (RSCAN0.RMPTR44.UINT8[R_IO_HH]) -#define RSCAN0RMDF044 (RSCAN0.RMDF044.UINT32) -#define RSCAN0RMDF044L (RSCAN0.RMDF044.UINT16[R_IO_L]) -#define RSCAN0RMDF044LL (RSCAN0.RMDF044.UINT8[R_IO_LL]) -#define RSCAN0RMDF044LH (RSCAN0.RMDF044.UINT8[R_IO_LH]) -#define RSCAN0RMDF044H (RSCAN0.RMDF044.UINT16[R_IO_H]) -#define RSCAN0RMDF044HL (RSCAN0.RMDF044.UINT8[R_IO_HL]) -#define RSCAN0RMDF044HH (RSCAN0.RMDF044.UINT8[R_IO_HH]) -#define RSCAN0RMDF144 (RSCAN0.RMDF144.UINT32) -#define RSCAN0RMDF144L (RSCAN0.RMDF144.UINT16[R_IO_L]) -#define RSCAN0RMDF144LL (RSCAN0.RMDF144.UINT8[R_IO_LL]) -#define RSCAN0RMDF144LH (RSCAN0.RMDF144.UINT8[R_IO_LH]) -#define RSCAN0RMDF144H (RSCAN0.RMDF144.UINT16[R_IO_H]) -#define RSCAN0RMDF144HL (RSCAN0.RMDF144.UINT8[R_IO_HL]) -#define RSCAN0RMDF144HH (RSCAN0.RMDF144.UINT8[R_IO_HH]) -#define RSCAN0RMID45 (RSCAN0.RMID45.UINT32) -#define RSCAN0RMID45L (RSCAN0.RMID45.UINT16[R_IO_L]) -#define RSCAN0RMID45LL (RSCAN0.RMID45.UINT8[R_IO_LL]) -#define RSCAN0RMID45LH (RSCAN0.RMID45.UINT8[R_IO_LH]) -#define RSCAN0RMID45H (RSCAN0.RMID45.UINT16[R_IO_H]) -#define RSCAN0RMID45HL (RSCAN0.RMID45.UINT8[R_IO_HL]) -#define RSCAN0RMID45HH (RSCAN0.RMID45.UINT8[R_IO_HH]) -#define RSCAN0RMPTR45 (RSCAN0.RMPTR45.UINT32) -#define RSCAN0RMPTR45L (RSCAN0.RMPTR45.UINT16[R_IO_L]) -#define RSCAN0RMPTR45LL (RSCAN0.RMPTR45.UINT8[R_IO_LL]) -#define RSCAN0RMPTR45LH (RSCAN0.RMPTR45.UINT8[R_IO_LH]) -#define RSCAN0RMPTR45H (RSCAN0.RMPTR45.UINT16[R_IO_H]) -#define RSCAN0RMPTR45HL (RSCAN0.RMPTR45.UINT8[R_IO_HL]) -#define RSCAN0RMPTR45HH (RSCAN0.RMPTR45.UINT8[R_IO_HH]) -#define RSCAN0RMDF045 (RSCAN0.RMDF045.UINT32) -#define RSCAN0RMDF045L (RSCAN0.RMDF045.UINT16[R_IO_L]) -#define RSCAN0RMDF045LL (RSCAN0.RMDF045.UINT8[R_IO_LL]) -#define RSCAN0RMDF045LH (RSCAN0.RMDF045.UINT8[R_IO_LH]) -#define RSCAN0RMDF045H (RSCAN0.RMDF045.UINT16[R_IO_H]) -#define RSCAN0RMDF045HL (RSCAN0.RMDF045.UINT8[R_IO_HL]) -#define RSCAN0RMDF045HH (RSCAN0.RMDF045.UINT8[R_IO_HH]) -#define RSCAN0RMDF145 (RSCAN0.RMDF145.UINT32) -#define RSCAN0RMDF145L (RSCAN0.RMDF145.UINT16[R_IO_L]) -#define RSCAN0RMDF145LL (RSCAN0.RMDF145.UINT8[R_IO_LL]) -#define RSCAN0RMDF145LH (RSCAN0.RMDF145.UINT8[R_IO_LH]) -#define RSCAN0RMDF145H (RSCAN0.RMDF145.UINT16[R_IO_H]) -#define RSCAN0RMDF145HL (RSCAN0.RMDF145.UINT8[R_IO_HL]) -#define RSCAN0RMDF145HH (RSCAN0.RMDF145.UINT8[R_IO_HH]) -#define RSCAN0RMID46 (RSCAN0.RMID46.UINT32) -#define RSCAN0RMID46L (RSCAN0.RMID46.UINT16[R_IO_L]) -#define RSCAN0RMID46LL (RSCAN0.RMID46.UINT8[R_IO_LL]) -#define RSCAN0RMID46LH (RSCAN0.RMID46.UINT8[R_IO_LH]) -#define RSCAN0RMID46H (RSCAN0.RMID46.UINT16[R_IO_H]) -#define RSCAN0RMID46HL (RSCAN0.RMID46.UINT8[R_IO_HL]) -#define RSCAN0RMID46HH (RSCAN0.RMID46.UINT8[R_IO_HH]) -#define RSCAN0RMPTR46 (RSCAN0.RMPTR46.UINT32) -#define RSCAN0RMPTR46L (RSCAN0.RMPTR46.UINT16[R_IO_L]) -#define RSCAN0RMPTR46LL (RSCAN0.RMPTR46.UINT8[R_IO_LL]) -#define RSCAN0RMPTR46LH (RSCAN0.RMPTR46.UINT8[R_IO_LH]) -#define RSCAN0RMPTR46H (RSCAN0.RMPTR46.UINT16[R_IO_H]) -#define RSCAN0RMPTR46HL (RSCAN0.RMPTR46.UINT8[R_IO_HL]) -#define RSCAN0RMPTR46HH (RSCAN0.RMPTR46.UINT8[R_IO_HH]) -#define RSCAN0RMDF046 (RSCAN0.RMDF046.UINT32) -#define RSCAN0RMDF046L (RSCAN0.RMDF046.UINT16[R_IO_L]) -#define RSCAN0RMDF046LL (RSCAN0.RMDF046.UINT8[R_IO_LL]) -#define RSCAN0RMDF046LH (RSCAN0.RMDF046.UINT8[R_IO_LH]) -#define RSCAN0RMDF046H (RSCAN0.RMDF046.UINT16[R_IO_H]) -#define RSCAN0RMDF046HL (RSCAN0.RMDF046.UINT8[R_IO_HL]) -#define RSCAN0RMDF046HH (RSCAN0.RMDF046.UINT8[R_IO_HH]) -#define RSCAN0RMDF146 (RSCAN0.RMDF146.UINT32) -#define RSCAN0RMDF146L (RSCAN0.RMDF146.UINT16[R_IO_L]) -#define RSCAN0RMDF146LL (RSCAN0.RMDF146.UINT8[R_IO_LL]) -#define RSCAN0RMDF146LH (RSCAN0.RMDF146.UINT8[R_IO_LH]) -#define RSCAN0RMDF146H (RSCAN0.RMDF146.UINT16[R_IO_H]) -#define RSCAN0RMDF146HL (RSCAN0.RMDF146.UINT8[R_IO_HL]) -#define RSCAN0RMDF146HH (RSCAN0.RMDF146.UINT8[R_IO_HH]) -#define RSCAN0RMID47 (RSCAN0.RMID47.UINT32) -#define RSCAN0RMID47L (RSCAN0.RMID47.UINT16[R_IO_L]) -#define RSCAN0RMID47LL (RSCAN0.RMID47.UINT8[R_IO_LL]) -#define RSCAN0RMID47LH (RSCAN0.RMID47.UINT8[R_IO_LH]) -#define RSCAN0RMID47H (RSCAN0.RMID47.UINT16[R_IO_H]) -#define RSCAN0RMID47HL (RSCAN0.RMID47.UINT8[R_IO_HL]) -#define RSCAN0RMID47HH (RSCAN0.RMID47.UINT8[R_IO_HH]) -#define RSCAN0RMPTR47 (RSCAN0.RMPTR47.UINT32) -#define RSCAN0RMPTR47L (RSCAN0.RMPTR47.UINT16[R_IO_L]) -#define RSCAN0RMPTR47LL (RSCAN0.RMPTR47.UINT8[R_IO_LL]) -#define RSCAN0RMPTR47LH (RSCAN0.RMPTR47.UINT8[R_IO_LH]) -#define RSCAN0RMPTR47H (RSCAN0.RMPTR47.UINT16[R_IO_H]) -#define RSCAN0RMPTR47HL (RSCAN0.RMPTR47.UINT8[R_IO_HL]) -#define RSCAN0RMPTR47HH (RSCAN0.RMPTR47.UINT8[R_IO_HH]) -#define RSCAN0RMDF047 (RSCAN0.RMDF047.UINT32) -#define RSCAN0RMDF047L (RSCAN0.RMDF047.UINT16[R_IO_L]) -#define RSCAN0RMDF047LL (RSCAN0.RMDF047.UINT8[R_IO_LL]) -#define RSCAN0RMDF047LH (RSCAN0.RMDF047.UINT8[R_IO_LH]) -#define RSCAN0RMDF047H (RSCAN0.RMDF047.UINT16[R_IO_H]) -#define RSCAN0RMDF047HL (RSCAN0.RMDF047.UINT8[R_IO_HL]) -#define RSCAN0RMDF047HH (RSCAN0.RMDF047.UINT8[R_IO_HH]) -#define RSCAN0RMDF147 (RSCAN0.RMDF147.UINT32) -#define RSCAN0RMDF147L (RSCAN0.RMDF147.UINT16[R_IO_L]) -#define RSCAN0RMDF147LL (RSCAN0.RMDF147.UINT8[R_IO_LL]) -#define RSCAN0RMDF147LH (RSCAN0.RMDF147.UINT8[R_IO_LH]) -#define RSCAN0RMDF147H (RSCAN0.RMDF147.UINT16[R_IO_H]) -#define RSCAN0RMDF147HL (RSCAN0.RMDF147.UINT8[R_IO_HL]) -#define RSCAN0RMDF147HH (RSCAN0.RMDF147.UINT8[R_IO_HH]) -#define RSCAN0RMID48 (RSCAN0.RMID48.UINT32) -#define RSCAN0RMID48L (RSCAN0.RMID48.UINT16[R_IO_L]) -#define RSCAN0RMID48LL (RSCAN0.RMID48.UINT8[R_IO_LL]) -#define RSCAN0RMID48LH (RSCAN0.RMID48.UINT8[R_IO_LH]) -#define RSCAN0RMID48H (RSCAN0.RMID48.UINT16[R_IO_H]) -#define RSCAN0RMID48HL (RSCAN0.RMID48.UINT8[R_IO_HL]) -#define RSCAN0RMID48HH (RSCAN0.RMID48.UINT8[R_IO_HH]) -#define RSCAN0RMPTR48 (RSCAN0.RMPTR48.UINT32) -#define RSCAN0RMPTR48L (RSCAN0.RMPTR48.UINT16[R_IO_L]) -#define RSCAN0RMPTR48LL (RSCAN0.RMPTR48.UINT8[R_IO_LL]) -#define RSCAN0RMPTR48LH (RSCAN0.RMPTR48.UINT8[R_IO_LH]) -#define RSCAN0RMPTR48H (RSCAN0.RMPTR48.UINT16[R_IO_H]) -#define RSCAN0RMPTR48HL (RSCAN0.RMPTR48.UINT8[R_IO_HL]) -#define RSCAN0RMPTR48HH (RSCAN0.RMPTR48.UINT8[R_IO_HH]) -#define RSCAN0RMDF048 (RSCAN0.RMDF048.UINT32) -#define RSCAN0RMDF048L (RSCAN0.RMDF048.UINT16[R_IO_L]) -#define RSCAN0RMDF048LL (RSCAN0.RMDF048.UINT8[R_IO_LL]) -#define RSCAN0RMDF048LH (RSCAN0.RMDF048.UINT8[R_IO_LH]) -#define RSCAN0RMDF048H (RSCAN0.RMDF048.UINT16[R_IO_H]) -#define RSCAN0RMDF048HL (RSCAN0.RMDF048.UINT8[R_IO_HL]) -#define RSCAN0RMDF048HH (RSCAN0.RMDF048.UINT8[R_IO_HH]) -#define RSCAN0RMDF148 (RSCAN0.RMDF148.UINT32) -#define RSCAN0RMDF148L (RSCAN0.RMDF148.UINT16[R_IO_L]) -#define RSCAN0RMDF148LL (RSCAN0.RMDF148.UINT8[R_IO_LL]) -#define RSCAN0RMDF148LH (RSCAN0.RMDF148.UINT8[R_IO_LH]) -#define RSCAN0RMDF148H (RSCAN0.RMDF148.UINT16[R_IO_H]) -#define RSCAN0RMDF148HL (RSCAN0.RMDF148.UINT8[R_IO_HL]) -#define RSCAN0RMDF148HH (RSCAN0.RMDF148.UINT8[R_IO_HH]) -#define RSCAN0RMID49 (RSCAN0.RMID49.UINT32) -#define RSCAN0RMID49L (RSCAN0.RMID49.UINT16[R_IO_L]) -#define RSCAN0RMID49LL (RSCAN0.RMID49.UINT8[R_IO_LL]) -#define RSCAN0RMID49LH (RSCAN0.RMID49.UINT8[R_IO_LH]) -#define RSCAN0RMID49H (RSCAN0.RMID49.UINT16[R_IO_H]) -#define RSCAN0RMID49HL (RSCAN0.RMID49.UINT8[R_IO_HL]) -#define RSCAN0RMID49HH (RSCAN0.RMID49.UINT8[R_IO_HH]) -#define RSCAN0RMPTR49 (RSCAN0.RMPTR49.UINT32) -#define RSCAN0RMPTR49L (RSCAN0.RMPTR49.UINT16[R_IO_L]) -#define RSCAN0RMPTR49LL (RSCAN0.RMPTR49.UINT8[R_IO_LL]) -#define RSCAN0RMPTR49LH (RSCAN0.RMPTR49.UINT8[R_IO_LH]) -#define RSCAN0RMPTR49H (RSCAN0.RMPTR49.UINT16[R_IO_H]) -#define RSCAN0RMPTR49HL (RSCAN0.RMPTR49.UINT8[R_IO_HL]) -#define RSCAN0RMPTR49HH (RSCAN0.RMPTR49.UINT8[R_IO_HH]) -#define RSCAN0RMDF049 (RSCAN0.RMDF049.UINT32) -#define RSCAN0RMDF049L (RSCAN0.RMDF049.UINT16[R_IO_L]) -#define RSCAN0RMDF049LL (RSCAN0.RMDF049.UINT8[R_IO_LL]) -#define RSCAN0RMDF049LH (RSCAN0.RMDF049.UINT8[R_IO_LH]) -#define RSCAN0RMDF049H (RSCAN0.RMDF049.UINT16[R_IO_H]) -#define RSCAN0RMDF049HL (RSCAN0.RMDF049.UINT8[R_IO_HL]) -#define RSCAN0RMDF049HH (RSCAN0.RMDF049.UINT8[R_IO_HH]) -#define RSCAN0RMDF149 (RSCAN0.RMDF149.UINT32) -#define RSCAN0RMDF149L (RSCAN0.RMDF149.UINT16[R_IO_L]) -#define RSCAN0RMDF149LL (RSCAN0.RMDF149.UINT8[R_IO_LL]) -#define RSCAN0RMDF149LH (RSCAN0.RMDF149.UINT8[R_IO_LH]) -#define RSCAN0RMDF149H (RSCAN0.RMDF149.UINT16[R_IO_H]) -#define RSCAN0RMDF149HL (RSCAN0.RMDF149.UINT8[R_IO_HL]) -#define RSCAN0RMDF149HH (RSCAN0.RMDF149.UINT8[R_IO_HH]) -#define RSCAN0RMID50 (RSCAN0.RMID50.UINT32) -#define RSCAN0RMID50L (RSCAN0.RMID50.UINT16[R_IO_L]) -#define RSCAN0RMID50LL (RSCAN0.RMID50.UINT8[R_IO_LL]) -#define RSCAN0RMID50LH (RSCAN0.RMID50.UINT8[R_IO_LH]) -#define RSCAN0RMID50H (RSCAN0.RMID50.UINT16[R_IO_H]) -#define RSCAN0RMID50HL (RSCAN0.RMID50.UINT8[R_IO_HL]) -#define RSCAN0RMID50HH (RSCAN0.RMID50.UINT8[R_IO_HH]) -#define RSCAN0RMPTR50 (RSCAN0.RMPTR50.UINT32) -#define RSCAN0RMPTR50L (RSCAN0.RMPTR50.UINT16[R_IO_L]) -#define RSCAN0RMPTR50LL (RSCAN0.RMPTR50.UINT8[R_IO_LL]) -#define RSCAN0RMPTR50LH (RSCAN0.RMPTR50.UINT8[R_IO_LH]) -#define RSCAN0RMPTR50H (RSCAN0.RMPTR50.UINT16[R_IO_H]) -#define RSCAN0RMPTR50HL (RSCAN0.RMPTR50.UINT8[R_IO_HL]) -#define RSCAN0RMPTR50HH (RSCAN0.RMPTR50.UINT8[R_IO_HH]) -#define RSCAN0RMDF050 (RSCAN0.RMDF050.UINT32) -#define RSCAN0RMDF050L (RSCAN0.RMDF050.UINT16[R_IO_L]) -#define RSCAN0RMDF050LL (RSCAN0.RMDF050.UINT8[R_IO_LL]) -#define RSCAN0RMDF050LH (RSCAN0.RMDF050.UINT8[R_IO_LH]) -#define RSCAN0RMDF050H (RSCAN0.RMDF050.UINT16[R_IO_H]) -#define RSCAN0RMDF050HL (RSCAN0.RMDF050.UINT8[R_IO_HL]) -#define RSCAN0RMDF050HH (RSCAN0.RMDF050.UINT8[R_IO_HH]) -#define RSCAN0RMDF150 (RSCAN0.RMDF150.UINT32) -#define RSCAN0RMDF150L (RSCAN0.RMDF150.UINT16[R_IO_L]) -#define RSCAN0RMDF150LL (RSCAN0.RMDF150.UINT8[R_IO_LL]) -#define RSCAN0RMDF150LH (RSCAN0.RMDF150.UINT8[R_IO_LH]) -#define RSCAN0RMDF150H (RSCAN0.RMDF150.UINT16[R_IO_H]) -#define RSCAN0RMDF150HL (RSCAN0.RMDF150.UINT8[R_IO_HL]) -#define RSCAN0RMDF150HH (RSCAN0.RMDF150.UINT8[R_IO_HH]) -#define RSCAN0RMID51 (RSCAN0.RMID51.UINT32) -#define RSCAN0RMID51L (RSCAN0.RMID51.UINT16[R_IO_L]) -#define RSCAN0RMID51LL (RSCAN0.RMID51.UINT8[R_IO_LL]) -#define RSCAN0RMID51LH (RSCAN0.RMID51.UINT8[R_IO_LH]) -#define RSCAN0RMID51H (RSCAN0.RMID51.UINT16[R_IO_H]) -#define RSCAN0RMID51HL (RSCAN0.RMID51.UINT8[R_IO_HL]) -#define RSCAN0RMID51HH (RSCAN0.RMID51.UINT8[R_IO_HH]) -#define RSCAN0RMPTR51 (RSCAN0.RMPTR51.UINT32) -#define RSCAN0RMPTR51L (RSCAN0.RMPTR51.UINT16[R_IO_L]) -#define RSCAN0RMPTR51LL (RSCAN0.RMPTR51.UINT8[R_IO_LL]) -#define RSCAN0RMPTR51LH (RSCAN0.RMPTR51.UINT8[R_IO_LH]) -#define RSCAN0RMPTR51H (RSCAN0.RMPTR51.UINT16[R_IO_H]) -#define RSCAN0RMPTR51HL (RSCAN0.RMPTR51.UINT8[R_IO_HL]) -#define RSCAN0RMPTR51HH (RSCAN0.RMPTR51.UINT8[R_IO_HH]) -#define RSCAN0RMDF051 (RSCAN0.RMDF051.UINT32) -#define RSCAN0RMDF051L (RSCAN0.RMDF051.UINT16[R_IO_L]) -#define RSCAN0RMDF051LL (RSCAN0.RMDF051.UINT8[R_IO_LL]) -#define RSCAN0RMDF051LH (RSCAN0.RMDF051.UINT8[R_IO_LH]) -#define RSCAN0RMDF051H (RSCAN0.RMDF051.UINT16[R_IO_H]) -#define RSCAN0RMDF051HL (RSCAN0.RMDF051.UINT8[R_IO_HL]) -#define RSCAN0RMDF051HH (RSCAN0.RMDF051.UINT8[R_IO_HH]) -#define RSCAN0RMDF151 (RSCAN0.RMDF151.UINT32) -#define RSCAN0RMDF151L (RSCAN0.RMDF151.UINT16[R_IO_L]) -#define RSCAN0RMDF151LL (RSCAN0.RMDF151.UINT8[R_IO_LL]) -#define RSCAN0RMDF151LH (RSCAN0.RMDF151.UINT8[R_IO_LH]) -#define RSCAN0RMDF151H (RSCAN0.RMDF151.UINT16[R_IO_H]) -#define RSCAN0RMDF151HL (RSCAN0.RMDF151.UINT8[R_IO_HL]) -#define RSCAN0RMDF151HH (RSCAN0.RMDF151.UINT8[R_IO_HH]) -#define RSCAN0RMID52 (RSCAN0.RMID52.UINT32) -#define RSCAN0RMID52L (RSCAN0.RMID52.UINT16[R_IO_L]) -#define RSCAN0RMID52LL (RSCAN0.RMID52.UINT8[R_IO_LL]) -#define RSCAN0RMID52LH (RSCAN0.RMID52.UINT8[R_IO_LH]) -#define RSCAN0RMID52H (RSCAN0.RMID52.UINT16[R_IO_H]) -#define RSCAN0RMID52HL (RSCAN0.RMID52.UINT8[R_IO_HL]) -#define RSCAN0RMID52HH (RSCAN0.RMID52.UINT8[R_IO_HH]) -#define RSCAN0RMPTR52 (RSCAN0.RMPTR52.UINT32) -#define RSCAN0RMPTR52L (RSCAN0.RMPTR52.UINT16[R_IO_L]) -#define RSCAN0RMPTR52LL (RSCAN0.RMPTR52.UINT8[R_IO_LL]) -#define RSCAN0RMPTR52LH (RSCAN0.RMPTR52.UINT8[R_IO_LH]) -#define RSCAN0RMPTR52H (RSCAN0.RMPTR52.UINT16[R_IO_H]) -#define RSCAN0RMPTR52HL (RSCAN0.RMPTR52.UINT8[R_IO_HL]) -#define RSCAN0RMPTR52HH (RSCAN0.RMPTR52.UINT8[R_IO_HH]) -#define RSCAN0RMDF052 (RSCAN0.RMDF052.UINT32) -#define RSCAN0RMDF052L (RSCAN0.RMDF052.UINT16[R_IO_L]) -#define RSCAN0RMDF052LL (RSCAN0.RMDF052.UINT8[R_IO_LL]) -#define RSCAN0RMDF052LH (RSCAN0.RMDF052.UINT8[R_IO_LH]) -#define RSCAN0RMDF052H (RSCAN0.RMDF052.UINT16[R_IO_H]) -#define RSCAN0RMDF052HL (RSCAN0.RMDF052.UINT8[R_IO_HL]) -#define RSCAN0RMDF052HH (RSCAN0.RMDF052.UINT8[R_IO_HH]) -#define RSCAN0RMDF152 (RSCAN0.RMDF152.UINT32) -#define RSCAN0RMDF152L (RSCAN0.RMDF152.UINT16[R_IO_L]) -#define RSCAN0RMDF152LL (RSCAN0.RMDF152.UINT8[R_IO_LL]) -#define RSCAN0RMDF152LH (RSCAN0.RMDF152.UINT8[R_IO_LH]) -#define RSCAN0RMDF152H (RSCAN0.RMDF152.UINT16[R_IO_H]) -#define RSCAN0RMDF152HL (RSCAN0.RMDF152.UINT8[R_IO_HL]) -#define RSCAN0RMDF152HH (RSCAN0.RMDF152.UINT8[R_IO_HH]) -#define RSCAN0RMID53 (RSCAN0.RMID53.UINT32) -#define RSCAN0RMID53L (RSCAN0.RMID53.UINT16[R_IO_L]) -#define RSCAN0RMID53LL (RSCAN0.RMID53.UINT8[R_IO_LL]) -#define RSCAN0RMID53LH (RSCAN0.RMID53.UINT8[R_IO_LH]) -#define RSCAN0RMID53H (RSCAN0.RMID53.UINT16[R_IO_H]) -#define RSCAN0RMID53HL (RSCAN0.RMID53.UINT8[R_IO_HL]) -#define RSCAN0RMID53HH (RSCAN0.RMID53.UINT8[R_IO_HH]) -#define RSCAN0RMPTR53 (RSCAN0.RMPTR53.UINT32) -#define RSCAN0RMPTR53L (RSCAN0.RMPTR53.UINT16[R_IO_L]) -#define RSCAN0RMPTR53LL (RSCAN0.RMPTR53.UINT8[R_IO_LL]) -#define RSCAN0RMPTR53LH (RSCAN0.RMPTR53.UINT8[R_IO_LH]) -#define RSCAN0RMPTR53H (RSCAN0.RMPTR53.UINT16[R_IO_H]) -#define RSCAN0RMPTR53HL (RSCAN0.RMPTR53.UINT8[R_IO_HL]) -#define RSCAN0RMPTR53HH (RSCAN0.RMPTR53.UINT8[R_IO_HH]) -#define RSCAN0RMDF053 (RSCAN0.RMDF053.UINT32) -#define RSCAN0RMDF053L (RSCAN0.RMDF053.UINT16[R_IO_L]) -#define RSCAN0RMDF053LL (RSCAN0.RMDF053.UINT8[R_IO_LL]) -#define RSCAN0RMDF053LH (RSCAN0.RMDF053.UINT8[R_IO_LH]) -#define RSCAN0RMDF053H (RSCAN0.RMDF053.UINT16[R_IO_H]) -#define RSCAN0RMDF053HL (RSCAN0.RMDF053.UINT8[R_IO_HL]) -#define RSCAN0RMDF053HH (RSCAN0.RMDF053.UINT8[R_IO_HH]) -#define RSCAN0RMDF153 (RSCAN0.RMDF153.UINT32) -#define RSCAN0RMDF153L (RSCAN0.RMDF153.UINT16[R_IO_L]) -#define RSCAN0RMDF153LL (RSCAN0.RMDF153.UINT8[R_IO_LL]) -#define RSCAN0RMDF153LH (RSCAN0.RMDF153.UINT8[R_IO_LH]) -#define RSCAN0RMDF153H (RSCAN0.RMDF153.UINT16[R_IO_H]) -#define RSCAN0RMDF153HL (RSCAN0.RMDF153.UINT8[R_IO_HL]) -#define RSCAN0RMDF153HH (RSCAN0.RMDF153.UINT8[R_IO_HH]) -#define RSCAN0RMID54 (RSCAN0.RMID54.UINT32) -#define RSCAN0RMID54L (RSCAN0.RMID54.UINT16[R_IO_L]) -#define RSCAN0RMID54LL (RSCAN0.RMID54.UINT8[R_IO_LL]) -#define RSCAN0RMID54LH (RSCAN0.RMID54.UINT8[R_IO_LH]) -#define RSCAN0RMID54H (RSCAN0.RMID54.UINT16[R_IO_H]) -#define RSCAN0RMID54HL (RSCAN0.RMID54.UINT8[R_IO_HL]) -#define RSCAN0RMID54HH (RSCAN0.RMID54.UINT8[R_IO_HH]) -#define RSCAN0RMPTR54 (RSCAN0.RMPTR54.UINT32) -#define RSCAN0RMPTR54L (RSCAN0.RMPTR54.UINT16[R_IO_L]) -#define RSCAN0RMPTR54LL (RSCAN0.RMPTR54.UINT8[R_IO_LL]) -#define RSCAN0RMPTR54LH (RSCAN0.RMPTR54.UINT8[R_IO_LH]) -#define RSCAN0RMPTR54H (RSCAN0.RMPTR54.UINT16[R_IO_H]) -#define RSCAN0RMPTR54HL (RSCAN0.RMPTR54.UINT8[R_IO_HL]) -#define RSCAN0RMPTR54HH (RSCAN0.RMPTR54.UINT8[R_IO_HH]) -#define RSCAN0RMDF054 (RSCAN0.RMDF054.UINT32) -#define RSCAN0RMDF054L (RSCAN0.RMDF054.UINT16[R_IO_L]) -#define RSCAN0RMDF054LL (RSCAN0.RMDF054.UINT8[R_IO_LL]) -#define RSCAN0RMDF054LH (RSCAN0.RMDF054.UINT8[R_IO_LH]) -#define RSCAN0RMDF054H (RSCAN0.RMDF054.UINT16[R_IO_H]) -#define RSCAN0RMDF054HL (RSCAN0.RMDF054.UINT8[R_IO_HL]) -#define RSCAN0RMDF054HH (RSCAN0.RMDF054.UINT8[R_IO_HH]) -#define RSCAN0RMDF154 (RSCAN0.RMDF154.UINT32) -#define RSCAN0RMDF154L (RSCAN0.RMDF154.UINT16[R_IO_L]) -#define RSCAN0RMDF154LL (RSCAN0.RMDF154.UINT8[R_IO_LL]) -#define RSCAN0RMDF154LH (RSCAN0.RMDF154.UINT8[R_IO_LH]) -#define RSCAN0RMDF154H (RSCAN0.RMDF154.UINT16[R_IO_H]) -#define RSCAN0RMDF154HL (RSCAN0.RMDF154.UINT8[R_IO_HL]) -#define RSCAN0RMDF154HH (RSCAN0.RMDF154.UINT8[R_IO_HH]) -#define RSCAN0RMID55 (RSCAN0.RMID55.UINT32) -#define RSCAN0RMID55L (RSCAN0.RMID55.UINT16[R_IO_L]) -#define RSCAN0RMID55LL (RSCAN0.RMID55.UINT8[R_IO_LL]) -#define RSCAN0RMID55LH (RSCAN0.RMID55.UINT8[R_IO_LH]) -#define RSCAN0RMID55H (RSCAN0.RMID55.UINT16[R_IO_H]) -#define RSCAN0RMID55HL (RSCAN0.RMID55.UINT8[R_IO_HL]) -#define RSCAN0RMID55HH (RSCAN0.RMID55.UINT8[R_IO_HH]) -#define RSCAN0RMPTR55 (RSCAN0.RMPTR55.UINT32) -#define RSCAN0RMPTR55L (RSCAN0.RMPTR55.UINT16[R_IO_L]) -#define RSCAN0RMPTR55LL (RSCAN0.RMPTR55.UINT8[R_IO_LL]) -#define RSCAN0RMPTR55LH (RSCAN0.RMPTR55.UINT8[R_IO_LH]) -#define RSCAN0RMPTR55H (RSCAN0.RMPTR55.UINT16[R_IO_H]) -#define RSCAN0RMPTR55HL (RSCAN0.RMPTR55.UINT8[R_IO_HL]) -#define RSCAN0RMPTR55HH (RSCAN0.RMPTR55.UINT8[R_IO_HH]) -#define RSCAN0RMDF055 (RSCAN0.RMDF055.UINT32) -#define RSCAN0RMDF055L (RSCAN0.RMDF055.UINT16[R_IO_L]) -#define RSCAN0RMDF055LL (RSCAN0.RMDF055.UINT8[R_IO_LL]) -#define RSCAN0RMDF055LH (RSCAN0.RMDF055.UINT8[R_IO_LH]) -#define RSCAN0RMDF055H (RSCAN0.RMDF055.UINT16[R_IO_H]) -#define RSCAN0RMDF055HL (RSCAN0.RMDF055.UINT8[R_IO_HL]) -#define RSCAN0RMDF055HH (RSCAN0.RMDF055.UINT8[R_IO_HH]) -#define RSCAN0RMDF155 (RSCAN0.RMDF155.UINT32) -#define RSCAN0RMDF155L (RSCAN0.RMDF155.UINT16[R_IO_L]) -#define RSCAN0RMDF155LL (RSCAN0.RMDF155.UINT8[R_IO_LL]) -#define RSCAN0RMDF155LH (RSCAN0.RMDF155.UINT8[R_IO_LH]) -#define RSCAN0RMDF155H (RSCAN0.RMDF155.UINT16[R_IO_H]) -#define RSCAN0RMDF155HL (RSCAN0.RMDF155.UINT8[R_IO_HL]) -#define RSCAN0RMDF155HH (RSCAN0.RMDF155.UINT8[R_IO_HH]) -#define RSCAN0RMID56 (RSCAN0.RMID56.UINT32) -#define RSCAN0RMID56L (RSCAN0.RMID56.UINT16[R_IO_L]) -#define RSCAN0RMID56LL (RSCAN0.RMID56.UINT8[R_IO_LL]) -#define RSCAN0RMID56LH (RSCAN0.RMID56.UINT8[R_IO_LH]) -#define RSCAN0RMID56H (RSCAN0.RMID56.UINT16[R_IO_H]) -#define RSCAN0RMID56HL (RSCAN0.RMID56.UINT8[R_IO_HL]) -#define RSCAN0RMID56HH (RSCAN0.RMID56.UINT8[R_IO_HH]) -#define RSCAN0RMPTR56 (RSCAN0.RMPTR56.UINT32) -#define RSCAN0RMPTR56L (RSCAN0.RMPTR56.UINT16[R_IO_L]) -#define RSCAN0RMPTR56LL (RSCAN0.RMPTR56.UINT8[R_IO_LL]) -#define RSCAN0RMPTR56LH (RSCAN0.RMPTR56.UINT8[R_IO_LH]) -#define RSCAN0RMPTR56H (RSCAN0.RMPTR56.UINT16[R_IO_H]) -#define RSCAN0RMPTR56HL (RSCAN0.RMPTR56.UINT8[R_IO_HL]) -#define RSCAN0RMPTR56HH (RSCAN0.RMPTR56.UINT8[R_IO_HH]) -#define RSCAN0RMDF056 (RSCAN0.RMDF056.UINT32) -#define RSCAN0RMDF056L (RSCAN0.RMDF056.UINT16[R_IO_L]) -#define RSCAN0RMDF056LL (RSCAN0.RMDF056.UINT8[R_IO_LL]) -#define RSCAN0RMDF056LH (RSCAN0.RMDF056.UINT8[R_IO_LH]) -#define RSCAN0RMDF056H (RSCAN0.RMDF056.UINT16[R_IO_H]) -#define RSCAN0RMDF056HL (RSCAN0.RMDF056.UINT8[R_IO_HL]) -#define RSCAN0RMDF056HH (RSCAN0.RMDF056.UINT8[R_IO_HH]) -#define RSCAN0RMDF156 (RSCAN0.RMDF156.UINT32) -#define RSCAN0RMDF156L (RSCAN0.RMDF156.UINT16[R_IO_L]) -#define RSCAN0RMDF156LL (RSCAN0.RMDF156.UINT8[R_IO_LL]) -#define RSCAN0RMDF156LH (RSCAN0.RMDF156.UINT8[R_IO_LH]) -#define RSCAN0RMDF156H (RSCAN0.RMDF156.UINT16[R_IO_H]) -#define RSCAN0RMDF156HL (RSCAN0.RMDF156.UINT8[R_IO_HL]) -#define RSCAN0RMDF156HH (RSCAN0.RMDF156.UINT8[R_IO_HH]) -#define RSCAN0RMID57 (RSCAN0.RMID57.UINT32) -#define RSCAN0RMID57L (RSCAN0.RMID57.UINT16[R_IO_L]) -#define RSCAN0RMID57LL (RSCAN0.RMID57.UINT8[R_IO_LL]) -#define RSCAN0RMID57LH (RSCAN0.RMID57.UINT8[R_IO_LH]) -#define RSCAN0RMID57H (RSCAN0.RMID57.UINT16[R_IO_H]) -#define RSCAN0RMID57HL (RSCAN0.RMID57.UINT8[R_IO_HL]) -#define RSCAN0RMID57HH (RSCAN0.RMID57.UINT8[R_IO_HH]) -#define RSCAN0RMPTR57 (RSCAN0.RMPTR57.UINT32) -#define RSCAN0RMPTR57L (RSCAN0.RMPTR57.UINT16[R_IO_L]) -#define RSCAN0RMPTR57LL (RSCAN0.RMPTR57.UINT8[R_IO_LL]) -#define RSCAN0RMPTR57LH (RSCAN0.RMPTR57.UINT8[R_IO_LH]) -#define RSCAN0RMPTR57H (RSCAN0.RMPTR57.UINT16[R_IO_H]) -#define RSCAN0RMPTR57HL (RSCAN0.RMPTR57.UINT8[R_IO_HL]) -#define RSCAN0RMPTR57HH (RSCAN0.RMPTR57.UINT8[R_IO_HH]) -#define RSCAN0RMDF057 (RSCAN0.RMDF057.UINT32) -#define RSCAN0RMDF057L (RSCAN0.RMDF057.UINT16[R_IO_L]) -#define RSCAN0RMDF057LL (RSCAN0.RMDF057.UINT8[R_IO_LL]) -#define RSCAN0RMDF057LH (RSCAN0.RMDF057.UINT8[R_IO_LH]) -#define RSCAN0RMDF057H (RSCAN0.RMDF057.UINT16[R_IO_H]) -#define RSCAN0RMDF057HL (RSCAN0.RMDF057.UINT8[R_IO_HL]) -#define RSCAN0RMDF057HH (RSCAN0.RMDF057.UINT8[R_IO_HH]) -#define RSCAN0RMDF157 (RSCAN0.RMDF157.UINT32) -#define RSCAN0RMDF157L (RSCAN0.RMDF157.UINT16[R_IO_L]) -#define RSCAN0RMDF157LL (RSCAN0.RMDF157.UINT8[R_IO_LL]) -#define RSCAN0RMDF157LH (RSCAN0.RMDF157.UINT8[R_IO_LH]) -#define RSCAN0RMDF157H (RSCAN0.RMDF157.UINT16[R_IO_H]) -#define RSCAN0RMDF157HL (RSCAN0.RMDF157.UINT8[R_IO_HL]) -#define RSCAN0RMDF157HH (RSCAN0.RMDF157.UINT8[R_IO_HH]) -#define RSCAN0RMID58 (RSCAN0.RMID58.UINT32) -#define RSCAN0RMID58L (RSCAN0.RMID58.UINT16[R_IO_L]) -#define RSCAN0RMID58LL (RSCAN0.RMID58.UINT8[R_IO_LL]) -#define RSCAN0RMID58LH (RSCAN0.RMID58.UINT8[R_IO_LH]) -#define RSCAN0RMID58H (RSCAN0.RMID58.UINT16[R_IO_H]) -#define RSCAN0RMID58HL (RSCAN0.RMID58.UINT8[R_IO_HL]) -#define RSCAN0RMID58HH (RSCAN0.RMID58.UINT8[R_IO_HH]) -#define RSCAN0RMPTR58 (RSCAN0.RMPTR58.UINT32) -#define RSCAN0RMPTR58L (RSCAN0.RMPTR58.UINT16[R_IO_L]) -#define RSCAN0RMPTR58LL (RSCAN0.RMPTR58.UINT8[R_IO_LL]) -#define RSCAN0RMPTR58LH (RSCAN0.RMPTR58.UINT8[R_IO_LH]) -#define RSCAN0RMPTR58H (RSCAN0.RMPTR58.UINT16[R_IO_H]) -#define RSCAN0RMPTR58HL (RSCAN0.RMPTR58.UINT8[R_IO_HL]) -#define RSCAN0RMPTR58HH (RSCAN0.RMPTR58.UINT8[R_IO_HH]) -#define RSCAN0RMDF058 (RSCAN0.RMDF058.UINT32) -#define RSCAN0RMDF058L (RSCAN0.RMDF058.UINT16[R_IO_L]) -#define RSCAN0RMDF058LL (RSCAN0.RMDF058.UINT8[R_IO_LL]) -#define RSCAN0RMDF058LH (RSCAN0.RMDF058.UINT8[R_IO_LH]) -#define RSCAN0RMDF058H (RSCAN0.RMDF058.UINT16[R_IO_H]) -#define RSCAN0RMDF058HL (RSCAN0.RMDF058.UINT8[R_IO_HL]) -#define RSCAN0RMDF058HH (RSCAN0.RMDF058.UINT8[R_IO_HH]) -#define RSCAN0RMDF158 (RSCAN0.RMDF158.UINT32) -#define RSCAN0RMDF158L (RSCAN0.RMDF158.UINT16[R_IO_L]) -#define RSCAN0RMDF158LL (RSCAN0.RMDF158.UINT8[R_IO_LL]) -#define RSCAN0RMDF158LH (RSCAN0.RMDF158.UINT8[R_IO_LH]) -#define RSCAN0RMDF158H (RSCAN0.RMDF158.UINT16[R_IO_H]) -#define RSCAN0RMDF158HL (RSCAN0.RMDF158.UINT8[R_IO_HL]) -#define RSCAN0RMDF158HH (RSCAN0.RMDF158.UINT8[R_IO_HH]) -#define RSCAN0RMID59 (RSCAN0.RMID59.UINT32) -#define RSCAN0RMID59L (RSCAN0.RMID59.UINT16[R_IO_L]) -#define RSCAN0RMID59LL (RSCAN0.RMID59.UINT8[R_IO_LL]) -#define RSCAN0RMID59LH (RSCAN0.RMID59.UINT8[R_IO_LH]) -#define RSCAN0RMID59H (RSCAN0.RMID59.UINT16[R_IO_H]) -#define RSCAN0RMID59HL (RSCAN0.RMID59.UINT8[R_IO_HL]) -#define RSCAN0RMID59HH (RSCAN0.RMID59.UINT8[R_IO_HH]) -#define RSCAN0RMPTR59 (RSCAN0.RMPTR59.UINT32) -#define RSCAN0RMPTR59L (RSCAN0.RMPTR59.UINT16[R_IO_L]) -#define RSCAN0RMPTR59LL (RSCAN0.RMPTR59.UINT8[R_IO_LL]) -#define RSCAN0RMPTR59LH (RSCAN0.RMPTR59.UINT8[R_IO_LH]) -#define RSCAN0RMPTR59H (RSCAN0.RMPTR59.UINT16[R_IO_H]) -#define RSCAN0RMPTR59HL (RSCAN0.RMPTR59.UINT8[R_IO_HL]) -#define RSCAN0RMPTR59HH (RSCAN0.RMPTR59.UINT8[R_IO_HH]) -#define RSCAN0RMDF059 (RSCAN0.RMDF059.UINT32) -#define RSCAN0RMDF059L (RSCAN0.RMDF059.UINT16[R_IO_L]) -#define RSCAN0RMDF059LL (RSCAN0.RMDF059.UINT8[R_IO_LL]) -#define RSCAN0RMDF059LH (RSCAN0.RMDF059.UINT8[R_IO_LH]) -#define RSCAN0RMDF059H (RSCAN0.RMDF059.UINT16[R_IO_H]) -#define RSCAN0RMDF059HL (RSCAN0.RMDF059.UINT8[R_IO_HL]) -#define RSCAN0RMDF059HH (RSCAN0.RMDF059.UINT8[R_IO_HH]) -#define RSCAN0RMDF159 (RSCAN0.RMDF159.UINT32) -#define RSCAN0RMDF159L (RSCAN0.RMDF159.UINT16[R_IO_L]) -#define RSCAN0RMDF159LL (RSCAN0.RMDF159.UINT8[R_IO_LL]) -#define RSCAN0RMDF159LH (RSCAN0.RMDF159.UINT8[R_IO_LH]) -#define RSCAN0RMDF159H (RSCAN0.RMDF159.UINT16[R_IO_H]) -#define RSCAN0RMDF159HL (RSCAN0.RMDF159.UINT8[R_IO_HL]) -#define RSCAN0RMDF159HH (RSCAN0.RMDF159.UINT8[R_IO_HH]) -#define RSCAN0RMID60 (RSCAN0.RMID60.UINT32) -#define RSCAN0RMID60L (RSCAN0.RMID60.UINT16[R_IO_L]) -#define RSCAN0RMID60LL (RSCAN0.RMID60.UINT8[R_IO_LL]) -#define RSCAN0RMID60LH (RSCAN0.RMID60.UINT8[R_IO_LH]) -#define RSCAN0RMID60H (RSCAN0.RMID60.UINT16[R_IO_H]) -#define RSCAN0RMID60HL (RSCAN0.RMID60.UINT8[R_IO_HL]) -#define RSCAN0RMID60HH (RSCAN0.RMID60.UINT8[R_IO_HH]) -#define RSCAN0RMPTR60 (RSCAN0.RMPTR60.UINT32) -#define RSCAN0RMPTR60L (RSCAN0.RMPTR60.UINT16[R_IO_L]) -#define RSCAN0RMPTR60LL (RSCAN0.RMPTR60.UINT8[R_IO_LL]) -#define RSCAN0RMPTR60LH (RSCAN0.RMPTR60.UINT8[R_IO_LH]) -#define RSCAN0RMPTR60H (RSCAN0.RMPTR60.UINT16[R_IO_H]) -#define RSCAN0RMPTR60HL (RSCAN0.RMPTR60.UINT8[R_IO_HL]) -#define RSCAN0RMPTR60HH (RSCAN0.RMPTR60.UINT8[R_IO_HH]) -#define RSCAN0RMDF060 (RSCAN0.RMDF060.UINT32) -#define RSCAN0RMDF060L (RSCAN0.RMDF060.UINT16[R_IO_L]) -#define RSCAN0RMDF060LL (RSCAN0.RMDF060.UINT8[R_IO_LL]) -#define RSCAN0RMDF060LH (RSCAN0.RMDF060.UINT8[R_IO_LH]) -#define RSCAN0RMDF060H (RSCAN0.RMDF060.UINT16[R_IO_H]) -#define RSCAN0RMDF060HL (RSCAN0.RMDF060.UINT8[R_IO_HL]) -#define RSCAN0RMDF060HH (RSCAN0.RMDF060.UINT8[R_IO_HH]) -#define RSCAN0RMDF160 (RSCAN0.RMDF160.UINT32) -#define RSCAN0RMDF160L (RSCAN0.RMDF160.UINT16[R_IO_L]) -#define RSCAN0RMDF160LL (RSCAN0.RMDF160.UINT8[R_IO_LL]) -#define RSCAN0RMDF160LH (RSCAN0.RMDF160.UINT8[R_IO_LH]) -#define RSCAN0RMDF160H (RSCAN0.RMDF160.UINT16[R_IO_H]) -#define RSCAN0RMDF160HL (RSCAN0.RMDF160.UINT8[R_IO_HL]) -#define RSCAN0RMDF160HH (RSCAN0.RMDF160.UINT8[R_IO_HH]) -#define RSCAN0RMID61 (RSCAN0.RMID61.UINT32) -#define RSCAN0RMID61L (RSCAN0.RMID61.UINT16[R_IO_L]) -#define RSCAN0RMID61LL (RSCAN0.RMID61.UINT8[R_IO_LL]) -#define RSCAN0RMID61LH (RSCAN0.RMID61.UINT8[R_IO_LH]) -#define RSCAN0RMID61H (RSCAN0.RMID61.UINT16[R_IO_H]) -#define RSCAN0RMID61HL (RSCAN0.RMID61.UINT8[R_IO_HL]) -#define RSCAN0RMID61HH (RSCAN0.RMID61.UINT8[R_IO_HH]) -#define RSCAN0RMPTR61 (RSCAN0.RMPTR61.UINT32) -#define RSCAN0RMPTR61L (RSCAN0.RMPTR61.UINT16[R_IO_L]) -#define RSCAN0RMPTR61LL (RSCAN0.RMPTR61.UINT8[R_IO_LL]) -#define RSCAN0RMPTR61LH (RSCAN0.RMPTR61.UINT8[R_IO_LH]) -#define RSCAN0RMPTR61H (RSCAN0.RMPTR61.UINT16[R_IO_H]) -#define RSCAN0RMPTR61HL (RSCAN0.RMPTR61.UINT8[R_IO_HL]) -#define RSCAN0RMPTR61HH (RSCAN0.RMPTR61.UINT8[R_IO_HH]) -#define RSCAN0RMDF061 (RSCAN0.RMDF061.UINT32) -#define RSCAN0RMDF061L (RSCAN0.RMDF061.UINT16[R_IO_L]) -#define RSCAN0RMDF061LL (RSCAN0.RMDF061.UINT8[R_IO_LL]) -#define RSCAN0RMDF061LH (RSCAN0.RMDF061.UINT8[R_IO_LH]) -#define RSCAN0RMDF061H (RSCAN0.RMDF061.UINT16[R_IO_H]) -#define RSCAN0RMDF061HL (RSCAN0.RMDF061.UINT8[R_IO_HL]) -#define RSCAN0RMDF061HH (RSCAN0.RMDF061.UINT8[R_IO_HH]) -#define RSCAN0RMDF161 (RSCAN0.RMDF161.UINT32) -#define RSCAN0RMDF161L (RSCAN0.RMDF161.UINT16[R_IO_L]) -#define RSCAN0RMDF161LL (RSCAN0.RMDF161.UINT8[R_IO_LL]) -#define RSCAN0RMDF161LH (RSCAN0.RMDF161.UINT8[R_IO_LH]) -#define RSCAN0RMDF161H (RSCAN0.RMDF161.UINT16[R_IO_H]) -#define RSCAN0RMDF161HL (RSCAN0.RMDF161.UINT8[R_IO_HL]) -#define RSCAN0RMDF161HH (RSCAN0.RMDF161.UINT8[R_IO_HH]) -#define RSCAN0RMID62 (RSCAN0.RMID62.UINT32) -#define RSCAN0RMID62L (RSCAN0.RMID62.UINT16[R_IO_L]) -#define RSCAN0RMID62LL (RSCAN0.RMID62.UINT8[R_IO_LL]) -#define RSCAN0RMID62LH (RSCAN0.RMID62.UINT8[R_IO_LH]) -#define RSCAN0RMID62H (RSCAN0.RMID62.UINT16[R_IO_H]) -#define RSCAN0RMID62HL (RSCAN0.RMID62.UINT8[R_IO_HL]) -#define RSCAN0RMID62HH (RSCAN0.RMID62.UINT8[R_IO_HH]) -#define RSCAN0RMPTR62 (RSCAN0.RMPTR62.UINT32) -#define RSCAN0RMPTR62L (RSCAN0.RMPTR62.UINT16[R_IO_L]) -#define RSCAN0RMPTR62LL (RSCAN0.RMPTR62.UINT8[R_IO_LL]) -#define RSCAN0RMPTR62LH (RSCAN0.RMPTR62.UINT8[R_IO_LH]) -#define RSCAN0RMPTR62H (RSCAN0.RMPTR62.UINT16[R_IO_H]) -#define RSCAN0RMPTR62HL (RSCAN0.RMPTR62.UINT8[R_IO_HL]) -#define RSCAN0RMPTR62HH (RSCAN0.RMPTR62.UINT8[R_IO_HH]) -#define RSCAN0RMDF062 (RSCAN0.RMDF062.UINT32) -#define RSCAN0RMDF062L (RSCAN0.RMDF062.UINT16[R_IO_L]) -#define RSCAN0RMDF062LL (RSCAN0.RMDF062.UINT8[R_IO_LL]) -#define RSCAN0RMDF062LH (RSCAN0.RMDF062.UINT8[R_IO_LH]) -#define RSCAN0RMDF062H (RSCAN0.RMDF062.UINT16[R_IO_H]) -#define RSCAN0RMDF062HL (RSCAN0.RMDF062.UINT8[R_IO_HL]) -#define RSCAN0RMDF062HH (RSCAN0.RMDF062.UINT8[R_IO_HH]) -#define RSCAN0RMDF162 (RSCAN0.RMDF162.UINT32) -#define RSCAN0RMDF162L (RSCAN0.RMDF162.UINT16[R_IO_L]) -#define RSCAN0RMDF162LL (RSCAN0.RMDF162.UINT8[R_IO_LL]) -#define RSCAN0RMDF162LH (RSCAN0.RMDF162.UINT8[R_IO_LH]) -#define RSCAN0RMDF162H (RSCAN0.RMDF162.UINT16[R_IO_H]) -#define RSCAN0RMDF162HL (RSCAN0.RMDF162.UINT8[R_IO_HL]) -#define RSCAN0RMDF162HH (RSCAN0.RMDF162.UINT8[R_IO_HH]) -#define RSCAN0RMID63 (RSCAN0.RMID63.UINT32) -#define RSCAN0RMID63L (RSCAN0.RMID63.UINT16[R_IO_L]) -#define RSCAN0RMID63LL (RSCAN0.RMID63.UINT8[R_IO_LL]) -#define RSCAN0RMID63LH (RSCAN0.RMID63.UINT8[R_IO_LH]) -#define RSCAN0RMID63H (RSCAN0.RMID63.UINT16[R_IO_H]) -#define RSCAN0RMID63HL (RSCAN0.RMID63.UINT8[R_IO_HL]) -#define RSCAN0RMID63HH (RSCAN0.RMID63.UINT8[R_IO_HH]) -#define RSCAN0RMPTR63 (RSCAN0.RMPTR63.UINT32) -#define RSCAN0RMPTR63L (RSCAN0.RMPTR63.UINT16[R_IO_L]) -#define RSCAN0RMPTR63LL (RSCAN0.RMPTR63.UINT8[R_IO_LL]) -#define RSCAN0RMPTR63LH (RSCAN0.RMPTR63.UINT8[R_IO_LH]) -#define RSCAN0RMPTR63H (RSCAN0.RMPTR63.UINT16[R_IO_H]) -#define RSCAN0RMPTR63HL (RSCAN0.RMPTR63.UINT8[R_IO_HL]) -#define RSCAN0RMPTR63HH (RSCAN0.RMPTR63.UINT8[R_IO_HH]) -#define RSCAN0RMDF063 (RSCAN0.RMDF063.UINT32) -#define RSCAN0RMDF063L (RSCAN0.RMDF063.UINT16[R_IO_L]) -#define RSCAN0RMDF063LL (RSCAN0.RMDF063.UINT8[R_IO_LL]) -#define RSCAN0RMDF063LH (RSCAN0.RMDF063.UINT8[R_IO_LH]) -#define RSCAN0RMDF063H (RSCAN0.RMDF063.UINT16[R_IO_H]) -#define RSCAN0RMDF063HL (RSCAN0.RMDF063.UINT8[R_IO_HL]) -#define RSCAN0RMDF063HH (RSCAN0.RMDF063.UINT8[R_IO_HH]) -#define RSCAN0RMDF163 (RSCAN0.RMDF163.UINT32) -#define RSCAN0RMDF163L (RSCAN0.RMDF163.UINT16[R_IO_L]) -#define RSCAN0RMDF163LL (RSCAN0.RMDF163.UINT8[R_IO_LL]) -#define RSCAN0RMDF163LH (RSCAN0.RMDF163.UINT8[R_IO_LH]) -#define RSCAN0RMDF163H (RSCAN0.RMDF163.UINT16[R_IO_H]) -#define RSCAN0RMDF163HL (RSCAN0.RMDF163.UINT8[R_IO_HL]) -#define RSCAN0RMDF163HH (RSCAN0.RMDF163.UINT8[R_IO_HH]) -#define RSCAN0RMID64 (RSCAN0.RMID64.UINT32) -#define RSCAN0RMID64L (RSCAN0.RMID64.UINT16[R_IO_L]) -#define RSCAN0RMID64LL (RSCAN0.RMID64.UINT8[R_IO_LL]) -#define RSCAN0RMID64LH (RSCAN0.RMID64.UINT8[R_IO_LH]) -#define RSCAN0RMID64H (RSCAN0.RMID64.UINT16[R_IO_H]) -#define RSCAN0RMID64HL (RSCAN0.RMID64.UINT8[R_IO_HL]) -#define RSCAN0RMID64HH (RSCAN0.RMID64.UINT8[R_IO_HH]) -#define RSCAN0RMPTR64 (RSCAN0.RMPTR64.UINT32) -#define RSCAN0RMPTR64L (RSCAN0.RMPTR64.UINT16[R_IO_L]) -#define RSCAN0RMPTR64LL (RSCAN0.RMPTR64.UINT8[R_IO_LL]) -#define RSCAN0RMPTR64LH (RSCAN0.RMPTR64.UINT8[R_IO_LH]) -#define RSCAN0RMPTR64H (RSCAN0.RMPTR64.UINT16[R_IO_H]) -#define RSCAN0RMPTR64HL (RSCAN0.RMPTR64.UINT8[R_IO_HL]) -#define RSCAN0RMPTR64HH (RSCAN0.RMPTR64.UINT8[R_IO_HH]) -#define RSCAN0RMDF064 (RSCAN0.RMDF064.UINT32) -#define RSCAN0RMDF064L (RSCAN0.RMDF064.UINT16[R_IO_L]) -#define RSCAN0RMDF064LL (RSCAN0.RMDF064.UINT8[R_IO_LL]) -#define RSCAN0RMDF064LH (RSCAN0.RMDF064.UINT8[R_IO_LH]) -#define RSCAN0RMDF064H (RSCAN0.RMDF064.UINT16[R_IO_H]) -#define RSCAN0RMDF064HL (RSCAN0.RMDF064.UINT8[R_IO_HL]) -#define RSCAN0RMDF064HH (RSCAN0.RMDF064.UINT8[R_IO_HH]) -#define RSCAN0RMDF164 (RSCAN0.RMDF164.UINT32) -#define RSCAN0RMDF164L (RSCAN0.RMDF164.UINT16[R_IO_L]) -#define RSCAN0RMDF164LL (RSCAN0.RMDF164.UINT8[R_IO_LL]) -#define RSCAN0RMDF164LH (RSCAN0.RMDF164.UINT8[R_IO_LH]) -#define RSCAN0RMDF164H (RSCAN0.RMDF164.UINT16[R_IO_H]) -#define RSCAN0RMDF164HL (RSCAN0.RMDF164.UINT8[R_IO_HL]) -#define RSCAN0RMDF164HH (RSCAN0.RMDF164.UINT8[R_IO_HH]) -#define RSCAN0RMID65 (RSCAN0.RMID65.UINT32) -#define RSCAN0RMID65L (RSCAN0.RMID65.UINT16[R_IO_L]) -#define RSCAN0RMID65LL (RSCAN0.RMID65.UINT8[R_IO_LL]) -#define RSCAN0RMID65LH (RSCAN0.RMID65.UINT8[R_IO_LH]) -#define RSCAN0RMID65H (RSCAN0.RMID65.UINT16[R_IO_H]) -#define RSCAN0RMID65HL (RSCAN0.RMID65.UINT8[R_IO_HL]) -#define RSCAN0RMID65HH (RSCAN0.RMID65.UINT8[R_IO_HH]) -#define RSCAN0RMPTR65 (RSCAN0.RMPTR65.UINT32) -#define RSCAN0RMPTR65L (RSCAN0.RMPTR65.UINT16[R_IO_L]) -#define RSCAN0RMPTR65LL (RSCAN0.RMPTR65.UINT8[R_IO_LL]) -#define RSCAN0RMPTR65LH (RSCAN0.RMPTR65.UINT8[R_IO_LH]) -#define RSCAN0RMPTR65H (RSCAN0.RMPTR65.UINT16[R_IO_H]) -#define RSCAN0RMPTR65HL (RSCAN0.RMPTR65.UINT8[R_IO_HL]) -#define RSCAN0RMPTR65HH (RSCAN0.RMPTR65.UINT8[R_IO_HH]) -#define RSCAN0RMDF065 (RSCAN0.RMDF065.UINT32) -#define RSCAN0RMDF065L (RSCAN0.RMDF065.UINT16[R_IO_L]) -#define RSCAN0RMDF065LL (RSCAN0.RMDF065.UINT8[R_IO_LL]) -#define RSCAN0RMDF065LH (RSCAN0.RMDF065.UINT8[R_IO_LH]) -#define RSCAN0RMDF065H (RSCAN0.RMDF065.UINT16[R_IO_H]) -#define RSCAN0RMDF065HL (RSCAN0.RMDF065.UINT8[R_IO_HL]) -#define RSCAN0RMDF065HH (RSCAN0.RMDF065.UINT8[R_IO_HH]) -#define RSCAN0RMDF165 (RSCAN0.RMDF165.UINT32) -#define RSCAN0RMDF165L (RSCAN0.RMDF165.UINT16[R_IO_L]) -#define RSCAN0RMDF165LL (RSCAN0.RMDF165.UINT8[R_IO_LL]) -#define RSCAN0RMDF165LH (RSCAN0.RMDF165.UINT8[R_IO_LH]) -#define RSCAN0RMDF165H (RSCAN0.RMDF165.UINT16[R_IO_H]) -#define RSCAN0RMDF165HL (RSCAN0.RMDF165.UINT8[R_IO_HL]) -#define RSCAN0RMDF165HH (RSCAN0.RMDF165.UINT8[R_IO_HH]) -#define RSCAN0RMID66 (RSCAN0.RMID66.UINT32) -#define RSCAN0RMID66L (RSCAN0.RMID66.UINT16[R_IO_L]) -#define RSCAN0RMID66LL (RSCAN0.RMID66.UINT8[R_IO_LL]) -#define RSCAN0RMID66LH (RSCAN0.RMID66.UINT8[R_IO_LH]) -#define RSCAN0RMID66H (RSCAN0.RMID66.UINT16[R_IO_H]) -#define RSCAN0RMID66HL (RSCAN0.RMID66.UINT8[R_IO_HL]) -#define RSCAN0RMID66HH (RSCAN0.RMID66.UINT8[R_IO_HH]) -#define RSCAN0RMPTR66 (RSCAN0.RMPTR66.UINT32) -#define RSCAN0RMPTR66L (RSCAN0.RMPTR66.UINT16[R_IO_L]) -#define RSCAN0RMPTR66LL (RSCAN0.RMPTR66.UINT8[R_IO_LL]) -#define RSCAN0RMPTR66LH (RSCAN0.RMPTR66.UINT8[R_IO_LH]) -#define RSCAN0RMPTR66H (RSCAN0.RMPTR66.UINT16[R_IO_H]) -#define RSCAN0RMPTR66HL (RSCAN0.RMPTR66.UINT8[R_IO_HL]) -#define RSCAN0RMPTR66HH (RSCAN0.RMPTR66.UINT8[R_IO_HH]) -#define RSCAN0RMDF066 (RSCAN0.RMDF066.UINT32) -#define RSCAN0RMDF066L (RSCAN0.RMDF066.UINT16[R_IO_L]) -#define RSCAN0RMDF066LL (RSCAN0.RMDF066.UINT8[R_IO_LL]) -#define RSCAN0RMDF066LH (RSCAN0.RMDF066.UINT8[R_IO_LH]) -#define RSCAN0RMDF066H (RSCAN0.RMDF066.UINT16[R_IO_H]) -#define RSCAN0RMDF066HL (RSCAN0.RMDF066.UINT8[R_IO_HL]) -#define RSCAN0RMDF066HH (RSCAN0.RMDF066.UINT8[R_IO_HH]) -#define RSCAN0RMDF166 (RSCAN0.RMDF166.UINT32) -#define RSCAN0RMDF166L (RSCAN0.RMDF166.UINT16[R_IO_L]) -#define RSCAN0RMDF166LL (RSCAN0.RMDF166.UINT8[R_IO_LL]) -#define RSCAN0RMDF166LH (RSCAN0.RMDF166.UINT8[R_IO_LH]) -#define RSCAN0RMDF166H (RSCAN0.RMDF166.UINT16[R_IO_H]) -#define RSCAN0RMDF166HL (RSCAN0.RMDF166.UINT8[R_IO_HL]) -#define RSCAN0RMDF166HH (RSCAN0.RMDF166.UINT8[R_IO_HH]) -#define RSCAN0RMID67 (RSCAN0.RMID67.UINT32) -#define RSCAN0RMID67L (RSCAN0.RMID67.UINT16[R_IO_L]) -#define RSCAN0RMID67LL (RSCAN0.RMID67.UINT8[R_IO_LL]) -#define RSCAN0RMID67LH (RSCAN0.RMID67.UINT8[R_IO_LH]) -#define RSCAN0RMID67H (RSCAN0.RMID67.UINT16[R_IO_H]) -#define RSCAN0RMID67HL (RSCAN0.RMID67.UINT8[R_IO_HL]) -#define RSCAN0RMID67HH (RSCAN0.RMID67.UINT8[R_IO_HH]) -#define RSCAN0RMPTR67 (RSCAN0.RMPTR67.UINT32) -#define RSCAN0RMPTR67L (RSCAN0.RMPTR67.UINT16[R_IO_L]) -#define RSCAN0RMPTR67LL (RSCAN0.RMPTR67.UINT8[R_IO_LL]) -#define RSCAN0RMPTR67LH (RSCAN0.RMPTR67.UINT8[R_IO_LH]) -#define RSCAN0RMPTR67H (RSCAN0.RMPTR67.UINT16[R_IO_H]) -#define RSCAN0RMPTR67HL (RSCAN0.RMPTR67.UINT8[R_IO_HL]) -#define RSCAN0RMPTR67HH (RSCAN0.RMPTR67.UINT8[R_IO_HH]) -#define RSCAN0RMDF067 (RSCAN0.RMDF067.UINT32) -#define RSCAN0RMDF067L (RSCAN0.RMDF067.UINT16[R_IO_L]) -#define RSCAN0RMDF067LL (RSCAN0.RMDF067.UINT8[R_IO_LL]) -#define RSCAN0RMDF067LH (RSCAN0.RMDF067.UINT8[R_IO_LH]) -#define RSCAN0RMDF067H (RSCAN0.RMDF067.UINT16[R_IO_H]) -#define RSCAN0RMDF067HL (RSCAN0.RMDF067.UINT8[R_IO_HL]) -#define RSCAN0RMDF067HH (RSCAN0.RMDF067.UINT8[R_IO_HH]) -#define RSCAN0RMDF167 (RSCAN0.RMDF167.UINT32) -#define RSCAN0RMDF167L (RSCAN0.RMDF167.UINT16[R_IO_L]) -#define RSCAN0RMDF167LL (RSCAN0.RMDF167.UINT8[R_IO_LL]) -#define RSCAN0RMDF167LH (RSCAN0.RMDF167.UINT8[R_IO_LH]) -#define RSCAN0RMDF167H (RSCAN0.RMDF167.UINT16[R_IO_H]) -#define RSCAN0RMDF167HL (RSCAN0.RMDF167.UINT8[R_IO_HL]) -#define RSCAN0RMDF167HH (RSCAN0.RMDF167.UINT8[R_IO_HH]) -#define RSCAN0RMID68 (RSCAN0.RMID68.UINT32) -#define RSCAN0RMID68L (RSCAN0.RMID68.UINT16[R_IO_L]) -#define RSCAN0RMID68LL (RSCAN0.RMID68.UINT8[R_IO_LL]) -#define RSCAN0RMID68LH (RSCAN0.RMID68.UINT8[R_IO_LH]) -#define RSCAN0RMID68H (RSCAN0.RMID68.UINT16[R_IO_H]) -#define RSCAN0RMID68HL (RSCAN0.RMID68.UINT8[R_IO_HL]) -#define RSCAN0RMID68HH (RSCAN0.RMID68.UINT8[R_IO_HH]) -#define RSCAN0RMPTR68 (RSCAN0.RMPTR68.UINT32) -#define RSCAN0RMPTR68L (RSCAN0.RMPTR68.UINT16[R_IO_L]) -#define RSCAN0RMPTR68LL (RSCAN0.RMPTR68.UINT8[R_IO_LL]) -#define RSCAN0RMPTR68LH (RSCAN0.RMPTR68.UINT8[R_IO_LH]) -#define RSCAN0RMPTR68H (RSCAN0.RMPTR68.UINT16[R_IO_H]) -#define RSCAN0RMPTR68HL (RSCAN0.RMPTR68.UINT8[R_IO_HL]) -#define RSCAN0RMPTR68HH (RSCAN0.RMPTR68.UINT8[R_IO_HH]) -#define RSCAN0RMDF068 (RSCAN0.RMDF068.UINT32) -#define RSCAN0RMDF068L (RSCAN0.RMDF068.UINT16[R_IO_L]) -#define RSCAN0RMDF068LL (RSCAN0.RMDF068.UINT8[R_IO_LL]) -#define RSCAN0RMDF068LH (RSCAN0.RMDF068.UINT8[R_IO_LH]) -#define RSCAN0RMDF068H (RSCAN0.RMDF068.UINT16[R_IO_H]) -#define RSCAN0RMDF068HL (RSCAN0.RMDF068.UINT8[R_IO_HL]) -#define RSCAN0RMDF068HH (RSCAN0.RMDF068.UINT8[R_IO_HH]) -#define RSCAN0RMDF168 (RSCAN0.RMDF168.UINT32) -#define RSCAN0RMDF168L (RSCAN0.RMDF168.UINT16[R_IO_L]) -#define RSCAN0RMDF168LL (RSCAN0.RMDF168.UINT8[R_IO_LL]) -#define RSCAN0RMDF168LH (RSCAN0.RMDF168.UINT8[R_IO_LH]) -#define RSCAN0RMDF168H (RSCAN0.RMDF168.UINT16[R_IO_H]) -#define RSCAN0RMDF168HL (RSCAN0.RMDF168.UINT8[R_IO_HL]) -#define RSCAN0RMDF168HH (RSCAN0.RMDF168.UINT8[R_IO_HH]) -#define RSCAN0RMID69 (RSCAN0.RMID69.UINT32) -#define RSCAN0RMID69L (RSCAN0.RMID69.UINT16[R_IO_L]) -#define RSCAN0RMID69LL (RSCAN0.RMID69.UINT8[R_IO_LL]) -#define RSCAN0RMID69LH (RSCAN0.RMID69.UINT8[R_IO_LH]) -#define RSCAN0RMID69H (RSCAN0.RMID69.UINT16[R_IO_H]) -#define RSCAN0RMID69HL (RSCAN0.RMID69.UINT8[R_IO_HL]) -#define RSCAN0RMID69HH (RSCAN0.RMID69.UINT8[R_IO_HH]) -#define RSCAN0RMPTR69 (RSCAN0.RMPTR69.UINT32) -#define RSCAN0RMPTR69L (RSCAN0.RMPTR69.UINT16[R_IO_L]) -#define RSCAN0RMPTR69LL (RSCAN0.RMPTR69.UINT8[R_IO_LL]) -#define RSCAN0RMPTR69LH (RSCAN0.RMPTR69.UINT8[R_IO_LH]) -#define RSCAN0RMPTR69H (RSCAN0.RMPTR69.UINT16[R_IO_H]) -#define RSCAN0RMPTR69HL (RSCAN0.RMPTR69.UINT8[R_IO_HL]) -#define RSCAN0RMPTR69HH (RSCAN0.RMPTR69.UINT8[R_IO_HH]) -#define RSCAN0RMDF069 (RSCAN0.RMDF069.UINT32) -#define RSCAN0RMDF069L (RSCAN0.RMDF069.UINT16[R_IO_L]) -#define RSCAN0RMDF069LL (RSCAN0.RMDF069.UINT8[R_IO_LL]) -#define RSCAN0RMDF069LH (RSCAN0.RMDF069.UINT8[R_IO_LH]) -#define RSCAN0RMDF069H (RSCAN0.RMDF069.UINT16[R_IO_H]) -#define RSCAN0RMDF069HL (RSCAN0.RMDF069.UINT8[R_IO_HL]) -#define RSCAN0RMDF069HH (RSCAN0.RMDF069.UINT8[R_IO_HH]) -#define RSCAN0RMDF169 (RSCAN0.RMDF169.UINT32) -#define RSCAN0RMDF169L (RSCAN0.RMDF169.UINT16[R_IO_L]) -#define RSCAN0RMDF169LL (RSCAN0.RMDF169.UINT8[R_IO_LL]) -#define RSCAN0RMDF169LH (RSCAN0.RMDF169.UINT8[R_IO_LH]) -#define RSCAN0RMDF169H (RSCAN0.RMDF169.UINT16[R_IO_H]) -#define RSCAN0RMDF169HL (RSCAN0.RMDF169.UINT8[R_IO_HL]) -#define RSCAN0RMDF169HH (RSCAN0.RMDF169.UINT8[R_IO_HH]) -#define RSCAN0RMID70 (RSCAN0.RMID70.UINT32) -#define RSCAN0RMID70L (RSCAN0.RMID70.UINT16[R_IO_L]) -#define RSCAN0RMID70LL (RSCAN0.RMID70.UINT8[R_IO_LL]) -#define RSCAN0RMID70LH (RSCAN0.RMID70.UINT8[R_IO_LH]) -#define RSCAN0RMID70H (RSCAN0.RMID70.UINT16[R_IO_H]) -#define RSCAN0RMID70HL (RSCAN0.RMID70.UINT8[R_IO_HL]) -#define RSCAN0RMID70HH (RSCAN0.RMID70.UINT8[R_IO_HH]) -#define RSCAN0RMPTR70 (RSCAN0.RMPTR70.UINT32) -#define RSCAN0RMPTR70L (RSCAN0.RMPTR70.UINT16[R_IO_L]) -#define RSCAN0RMPTR70LL (RSCAN0.RMPTR70.UINT8[R_IO_LL]) -#define RSCAN0RMPTR70LH (RSCAN0.RMPTR70.UINT8[R_IO_LH]) -#define RSCAN0RMPTR70H (RSCAN0.RMPTR70.UINT16[R_IO_H]) -#define RSCAN0RMPTR70HL (RSCAN0.RMPTR70.UINT8[R_IO_HL]) -#define RSCAN0RMPTR70HH (RSCAN0.RMPTR70.UINT8[R_IO_HH]) -#define RSCAN0RMDF070 (RSCAN0.RMDF070.UINT32) -#define RSCAN0RMDF070L (RSCAN0.RMDF070.UINT16[R_IO_L]) -#define RSCAN0RMDF070LL (RSCAN0.RMDF070.UINT8[R_IO_LL]) -#define RSCAN0RMDF070LH (RSCAN0.RMDF070.UINT8[R_IO_LH]) -#define RSCAN0RMDF070H (RSCAN0.RMDF070.UINT16[R_IO_H]) -#define RSCAN0RMDF070HL (RSCAN0.RMDF070.UINT8[R_IO_HL]) -#define RSCAN0RMDF070HH (RSCAN0.RMDF070.UINT8[R_IO_HH]) -#define RSCAN0RMDF170 (RSCAN0.RMDF170.UINT32) -#define RSCAN0RMDF170L (RSCAN0.RMDF170.UINT16[R_IO_L]) -#define RSCAN0RMDF170LL (RSCAN0.RMDF170.UINT8[R_IO_LL]) -#define RSCAN0RMDF170LH (RSCAN0.RMDF170.UINT8[R_IO_LH]) -#define RSCAN0RMDF170H (RSCAN0.RMDF170.UINT16[R_IO_H]) -#define RSCAN0RMDF170HL (RSCAN0.RMDF170.UINT8[R_IO_HL]) -#define RSCAN0RMDF170HH (RSCAN0.RMDF170.UINT8[R_IO_HH]) -#define RSCAN0RMID71 (RSCAN0.RMID71.UINT32) -#define RSCAN0RMID71L (RSCAN0.RMID71.UINT16[R_IO_L]) -#define RSCAN0RMID71LL (RSCAN0.RMID71.UINT8[R_IO_LL]) -#define RSCAN0RMID71LH (RSCAN0.RMID71.UINT8[R_IO_LH]) -#define RSCAN0RMID71H (RSCAN0.RMID71.UINT16[R_IO_H]) -#define RSCAN0RMID71HL (RSCAN0.RMID71.UINT8[R_IO_HL]) -#define RSCAN0RMID71HH (RSCAN0.RMID71.UINT8[R_IO_HH]) -#define RSCAN0RMPTR71 (RSCAN0.RMPTR71.UINT32) -#define RSCAN0RMPTR71L (RSCAN0.RMPTR71.UINT16[R_IO_L]) -#define RSCAN0RMPTR71LL (RSCAN0.RMPTR71.UINT8[R_IO_LL]) -#define RSCAN0RMPTR71LH (RSCAN0.RMPTR71.UINT8[R_IO_LH]) -#define RSCAN0RMPTR71H (RSCAN0.RMPTR71.UINT16[R_IO_H]) -#define RSCAN0RMPTR71HL (RSCAN0.RMPTR71.UINT8[R_IO_HL]) -#define RSCAN0RMPTR71HH (RSCAN0.RMPTR71.UINT8[R_IO_HH]) -#define RSCAN0RMDF071 (RSCAN0.RMDF071.UINT32) -#define RSCAN0RMDF071L (RSCAN0.RMDF071.UINT16[R_IO_L]) -#define RSCAN0RMDF071LL (RSCAN0.RMDF071.UINT8[R_IO_LL]) -#define RSCAN0RMDF071LH (RSCAN0.RMDF071.UINT8[R_IO_LH]) -#define RSCAN0RMDF071H (RSCAN0.RMDF071.UINT16[R_IO_H]) -#define RSCAN0RMDF071HL (RSCAN0.RMDF071.UINT8[R_IO_HL]) -#define RSCAN0RMDF071HH (RSCAN0.RMDF071.UINT8[R_IO_HH]) -#define RSCAN0RMDF171 (RSCAN0.RMDF171.UINT32) -#define RSCAN0RMDF171L (RSCAN0.RMDF171.UINT16[R_IO_L]) -#define RSCAN0RMDF171LL (RSCAN0.RMDF171.UINT8[R_IO_LL]) -#define RSCAN0RMDF171LH (RSCAN0.RMDF171.UINT8[R_IO_LH]) -#define RSCAN0RMDF171H (RSCAN0.RMDF171.UINT16[R_IO_H]) -#define RSCAN0RMDF171HL (RSCAN0.RMDF171.UINT8[R_IO_HL]) -#define RSCAN0RMDF171HH (RSCAN0.RMDF171.UINT8[R_IO_HH]) -#define RSCAN0RMID72 (RSCAN0.RMID72.UINT32) -#define RSCAN0RMID72L (RSCAN0.RMID72.UINT16[R_IO_L]) -#define RSCAN0RMID72LL (RSCAN0.RMID72.UINT8[R_IO_LL]) -#define RSCAN0RMID72LH (RSCAN0.RMID72.UINT8[R_IO_LH]) -#define RSCAN0RMID72H (RSCAN0.RMID72.UINT16[R_IO_H]) -#define RSCAN0RMID72HL (RSCAN0.RMID72.UINT8[R_IO_HL]) -#define RSCAN0RMID72HH (RSCAN0.RMID72.UINT8[R_IO_HH]) -#define RSCAN0RMPTR72 (RSCAN0.RMPTR72.UINT32) -#define RSCAN0RMPTR72L (RSCAN0.RMPTR72.UINT16[R_IO_L]) -#define RSCAN0RMPTR72LL (RSCAN0.RMPTR72.UINT8[R_IO_LL]) -#define RSCAN0RMPTR72LH (RSCAN0.RMPTR72.UINT8[R_IO_LH]) -#define RSCAN0RMPTR72H (RSCAN0.RMPTR72.UINT16[R_IO_H]) -#define RSCAN0RMPTR72HL (RSCAN0.RMPTR72.UINT8[R_IO_HL]) -#define RSCAN0RMPTR72HH (RSCAN0.RMPTR72.UINT8[R_IO_HH]) -#define RSCAN0RMDF072 (RSCAN0.RMDF072.UINT32) -#define RSCAN0RMDF072L (RSCAN0.RMDF072.UINT16[R_IO_L]) -#define RSCAN0RMDF072LL (RSCAN0.RMDF072.UINT8[R_IO_LL]) -#define RSCAN0RMDF072LH (RSCAN0.RMDF072.UINT8[R_IO_LH]) -#define RSCAN0RMDF072H (RSCAN0.RMDF072.UINT16[R_IO_H]) -#define RSCAN0RMDF072HL (RSCAN0.RMDF072.UINT8[R_IO_HL]) -#define RSCAN0RMDF072HH (RSCAN0.RMDF072.UINT8[R_IO_HH]) -#define RSCAN0RMDF172 (RSCAN0.RMDF172.UINT32) -#define RSCAN0RMDF172L (RSCAN0.RMDF172.UINT16[R_IO_L]) -#define RSCAN0RMDF172LL (RSCAN0.RMDF172.UINT8[R_IO_LL]) -#define RSCAN0RMDF172LH (RSCAN0.RMDF172.UINT8[R_IO_LH]) -#define RSCAN0RMDF172H (RSCAN0.RMDF172.UINT16[R_IO_H]) -#define RSCAN0RMDF172HL (RSCAN0.RMDF172.UINT8[R_IO_HL]) -#define RSCAN0RMDF172HH (RSCAN0.RMDF172.UINT8[R_IO_HH]) -#define RSCAN0RMID73 (RSCAN0.RMID73.UINT32) -#define RSCAN0RMID73L (RSCAN0.RMID73.UINT16[R_IO_L]) -#define RSCAN0RMID73LL (RSCAN0.RMID73.UINT8[R_IO_LL]) -#define RSCAN0RMID73LH (RSCAN0.RMID73.UINT8[R_IO_LH]) -#define RSCAN0RMID73H (RSCAN0.RMID73.UINT16[R_IO_H]) -#define RSCAN0RMID73HL (RSCAN0.RMID73.UINT8[R_IO_HL]) -#define RSCAN0RMID73HH (RSCAN0.RMID73.UINT8[R_IO_HH]) -#define RSCAN0RMPTR73 (RSCAN0.RMPTR73.UINT32) -#define RSCAN0RMPTR73L (RSCAN0.RMPTR73.UINT16[R_IO_L]) -#define RSCAN0RMPTR73LL (RSCAN0.RMPTR73.UINT8[R_IO_LL]) -#define RSCAN0RMPTR73LH (RSCAN0.RMPTR73.UINT8[R_IO_LH]) -#define RSCAN0RMPTR73H (RSCAN0.RMPTR73.UINT16[R_IO_H]) -#define RSCAN0RMPTR73HL (RSCAN0.RMPTR73.UINT8[R_IO_HL]) -#define RSCAN0RMPTR73HH (RSCAN0.RMPTR73.UINT8[R_IO_HH]) -#define RSCAN0RMDF073 (RSCAN0.RMDF073.UINT32) -#define RSCAN0RMDF073L (RSCAN0.RMDF073.UINT16[R_IO_L]) -#define RSCAN0RMDF073LL (RSCAN0.RMDF073.UINT8[R_IO_LL]) -#define RSCAN0RMDF073LH (RSCAN0.RMDF073.UINT8[R_IO_LH]) -#define RSCAN0RMDF073H (RSCAN0.RMDF073.UINT16[R_IO_H]) -#define RSCAN0RMDF073HL (RSCAN0.RMDF073.UINT8[R_IO_HL]) -#define RSCAN0RMDF073HH (RSCAN0.RMDF073.UINT8[R_IO_HH]) -#define RSCAN0RMDF173 (RSCAN0.RMDF173.UINT32) -#define RSCAN0RMDF173L (RSCAN0.RMDF173.UINT16[R_IO_L]) -#define RSCAN0RMDF173LL (RSCAN0.RMDF173.UINT8[R_IO_LL]) -#define RSCAN0RMDF173LH (RSCAN0.RMDF173.UINT8[R_IO_LH]) -#define RSCAN0RMDF173H (RSCAN0.RMDF173.UINT16[R_IO_H]) -#define RSCAN0RMDF173HL (RSCAN0.RMDF173.UINT8[R_IO_HL]) -#define RSCAN0RMDF173HH (RSCAN0.RMDF173.UINT8[R_IO_HH]) -#define RSCAN0RMID74 (RSCAN0.RMID74.UINT32) -#define RSCAN0RMID74L (RSCAN0.RMID74.UINT16[R_IO_L]) -#define RSCAN0RMID74LL (RSCAN0.RMID74.UINT8[R_IO_LL]) -#define RSCAN0RMID74LH (RSCAN0.RMID74.UINT8[R_IO_LH]) -#define RSCAN0RMID74H (RSCAN0.RMID74.UINT16[R_IO_H]) -#define RSCAN0RMID74HL (RSCAN0.RMID74.UINT8[R_IO_HL]) -#define RSCAN0RMID74HH (RSCAN0.RMID74.UINT8[R_IO_HH]) -#define RSCAN0RMPTR74 (RSCAN0.RMPTR74.UINT32) -#define RSCAN0RMPTR74L (RSCAN0.RMPTR74.UINT16[R_IO_L]) -#define RSCAN0RMPTR74LL (RSCAN0.RMPTR74.UINT8[R_IO_LL]) -#define RSCAN0RMPTR74LH (RSCAN0.RMPTR74.UINT8[R_IO_LH]) -#define RSCAN0RMPTR74H (RSCAN0.RMPTR74.UINT16[R_IO_H]) -#define RSCAN0RMPTR74HL (RSCAN0.RMPTR74.UINT8[R_IO_HL]) -#define RSCAN0RMPTR74HH (RSCAN0.RMPTR74.UINT8[R_IO_HH]) -#define RSCAN0RMDF074 (RSCAN0.RMDF074.UINT32) -#define RSCAN0RMDF074L (RSCAN0.RMDF074.UINT16[R_IO_L]) -#define RSCAN0RMDF074LL (RSCAN0.RMDF074.UINT8[R_IO_LL]) -#define RSCAN0RMDF074LH (RSCAN0.RMDF074.UINT8[R_IO_LH]) -#define RSCAN0RMDF074H (RSCAN0.RMDF074.UINT16[R_IO_H]) -#define RSCAN0RMDF074HL (RSCAN0.RMDF074.UINT8[R_IO_HL]) -#define RSCAN0RMDF074HH (RSCAN0.RMDF074.UINT8[R_IO_HH]) -#define RSCAN0RMDF174 (RSCAN0.RMDF174.UINT32) -#define RSCAN0RMDF174L (RSCAN0.RMDF174.UINT16[R_IO_L]) -#define RSCAN0RMDF174LL (RSCAN0.RMDF174.UINT8[R_IO_LL]) -#define RSCAN0RMDF174LH (RSCAN0.RMDF174.UINT8[R_IO_LH]) -#define RSCAN0RMDF174H (RSCAN0.RMDF174.UINT16[R_IO_H]) -#define RSCAN0RMDF174HL (RSCAN0.RMDF174.UINT8[R_IO_HL]) -#define RSCAN0RMDF174HH (RSCAN0.RMDF174.UINT8[R_IO_HH]) -#define RSCAN0RMID75 (RSCAN0.RMID75.UINT32) -#define RSCAN0RMID75L (RSCAN0.RMID75.UINT16[R_IO_L]) -#define RSCAN0RMID75LL (RSCAN0.RMID75.UINT8[R_IO_LL]) -#define RSCAN0RMID75LH (RSCAN0.RMID75.UINT8[R_IO_LH]) -#define RSCAN0RMID75H (RSCAN0.RMID75.UINT16[R_IO_H]) -#define RSCAN0RMID75HL (RSCAN0.RMID75.UINT8[R_IO_HL]) -#define RSCAN0RMID75HH (RSCAN0.RMID75.UINT8[R_IO_HH]) -#define RSCAN0RMPTR75 (RSCAN0.RMPTR75.UINT32) -#define RSCAN0RMPTR75L (RSCAN0.RMPTR75.UINT16[R_IO_L]) -#define RSCAN0RMPTR75LL (RSCAN0.RMPTR75.UINT8[R_IO_LL]) -#define RSCAN0RMPTR75LH (RSCAN0.RMPTR75.UINT8[R_IO_LH]) -#define RSCAN0RMPTR75H (RSCAN0.RMPTR75.UINT16[R_IO_H]) -#define RSCAN0RMPTR75HL (RSCAN0.RMPTR75.UINT8[R_IO_HL]) -#define RSCAN0RMPTR75HH (RSCAN0.RMPTR75.UINT8[R_IO_HH]) -#define RSCAN0RMDF075 (RSCAN0.RMDF075.UINT32) -#define RSCAN0RMDF075L (RSCAN0.RMDF075.UINT16[R_IO_L]) -#define RSCAN0RMDF075LL (RSCAN0.RMDF075.UINT8[R_IO_LL]) -#define RSCAN0RMDF075LH (RSCAN0.RMDF075.UINT8[R_IO_LH]) -#define RSCAN0RMDF075H (RSCAN0.RMDF075.UINT16[R_IO_H]) -#define RSCAN0RMDF075HL (RSCAN0.RMDF075.UINT8[R_IO_HL]) -#define RSCAN0RMDF075HH (RSCAN0.RMDF075.UINT8[R_IO_HH]) -#define RSCAN0RMDF175 (RSCAN0.RMDF175.UINT32) -#define RSCAN0RMDF175L (RSCAN0.RMDF175.UINT16[R_IO_L]) -#define RSCAN0RMDF175LL (RSCAN0.RMDF175.UINT8[R_IO_LL]) -#define RSCAN0RMDF175LH (RSCAN0.RMDF175.UINT8[R_IO_LH]) -#define RSCAN0RMDF175H (RSCAN0.RMDF175.UINT16[R_IO_H]) -#define RSCAN0RMDF175HL (RSCAN0.RMDF175.UINT8[R_IO_HL]) -#define RSCAN0RMDF175HH (RSCAN0.RMDF175.UINT8[R_IO_HH]) -#define RSCAN0RMID76 (RSCAN0.RMID76.UINT32) -#define RSCAN0RMID76L (RSCAN0.RMID76.UINT16[R_IO_L]) -#define RSCAN0RMID76LL (RSCAN0.RMID76.UINT8[R_IO_LL]) -#define RSCAN0RMID76LH (RSCAN0.RMID76.UINT8[R_IO_LH]) -#define RSCAN0RMID76H (RSCAN0.RMID76.UINT16[R_IO_H]) -#define RSCAN0RMID76HL (RSCAN0.RMID76.UINT8[R_IO_HL]) -#define RSCAN0RMID76HH (RSCAN0.RMID76.UINT8[R_IO_HH]) -#define RSCAN0RMPTR76 (RSCAN0.RMPTR76.UINT32) -#define RSCAN0RMPTR76L (RSCAN0.RMPTR76.UINT16[R_IO_L]) -#define RSCAN0RMPTR76LL (RSCAN0.RMPTR76.UINT8[R_IO_LL]) -#define RSCAN0RMPTR76LH (RSCAN0.RMPTR76.UINT8[R_IO_LH]) -#define RSCAN0RMPTR76H (RSCAN0.RMPTR76.UINT16[R_IO_H]) -#define RSCAN0RMPTR76HL (RSCAN0.RMPTR76.UINT8[R_IO_HL]) -#define RSCAN0RMPTR76HH (RSCAN0.RMPTR76.UINT8[R_IO_HH]) -#define RSCAN0RMDF076 (RSCAN0.RMDF076.UINT32) -#define RSCAN0RMDF076L (RSCAN0.RMDF076.UINT16[R_IO_L]) -#define RSCAN0RMDF076LL (RSCAN0.RMDF076.UINT8[R_IO_LL]) -#define RSCAN0RMDF076LH (RSCAN0.RMDF076.UINT8[R_IO_LH]) -#define RSCAN0RMDF076H (RSCAN0.RMDF076.UINT16[R_IO_H]) -#define RSCAN0RMDF076HL (RSCAN0.RMDF076.UINT8[R_IO_HL]) -#define RSCAN0RMDF076HH (RSCAN0.RMDF076.UINT8[R_IO_HH]) -#define RSCAN0RMDF176 (RSCAN0.RMDF176.UINT32) -#define RSCAN0RMDF176L (RSCAN0.RMDF176.UINT16[R_IO_L]) -#define RSCAN0RMDF176LL (RSCAN0.RMDF176.UINT8[R_IO_LL]) -#define RSCAN0RMDF176LH (RSCAN0.RMDF176.UINT8[R_IO_LH]) -#define RSCAN0RMDF176H (RSCAN0.RMDF176.UINT16[R_IO_H]) -#define RSCAN0RMDF176HL (RSCAN0.RMDF176.UINT8[R_IO_HL]) -#define RSCAN0RMDF176HH (RSCAN0.RMDF176.UINT8[R_IO_HH]) -#define RSCAN0RMID77 (RSCAN0.RMID77.UINT32) -#define RSCAN0RMID77L (RSCAN0.RMID77.UINT16[R_IO_L]) -#define RSCAN0RMID77LL (RSCAN0.RMID77.UINT8[R_IO_LL]) -#define RSCAN0RMID77LH (RSCAN0.RMID77.UINT8[R_IO_LH]) -#define RSCAN0RMID77H (RSCAN0.RMID77.UINT16[R_IO_H]) -#define RSCAN0RMID77HL (RSCAN0.RMID77.UINT8[R_IO_HL]) -#define RSCAN0RMID77HH (RSCAN0.RMID77.UINT8[R_IO_HH]) -#define RSCAN0RMPTR77 (RSCAN0.RMPTR77.UINT32) -#define RSCAN0RMPTR77L (RSCAN0.RMPTR77.UINT16[R_IO_L]) -#define RSCAN0RMPTR77LL (RSCAN0.RMPTR77.UINT8[R_IO_LL]) -#define RSCAN0RMPTR77LH (RSCAN0.RMPTR77.UINT8[R_IO_LH]) -#define RSCAN0RMPTR77H (RSCAN0.RMPTR77.UINT16[R_IO_H]) -#define RSCAN0RMPTR77HL (RSCAN0.RMPTR77.UINT8[R_IO_HL]) -#define RSCAN0RMPTR77HH (RSCAN0.RMPTR77.UINT8[R_IO_HH]) -#define RSCAN0RMDF077 (RSCAN0.RMDF077.UINT32) -#define RSCAN0RMDF077L (RSCAN0.RMDF077.UINT16[R_IO_L]) -#define RSCAN0RMDF077LL (RSCAN0.RMDF077.UINT8[R_IO_LL]) -#define RSCAN0RMDF077LH (RSCAN0.RMDF077.UINT8[R_IO_LH]) -#define RSCAN0RMDF077H (RSCAN0.RMDF077.UINT16[R_IO_H]) -#define RSCAN0RMDF077HL (RSCAN0.RMDF077.UINT8[R_IO_HL]) -#define RSCAN0RMDF077HH (RSCAN0.RMDF077.UINT8[R_IO_HH]) -#define RSCAN0RMDF177 (RSCAN0.RMDF177.UINT32) -#define RSCAN0RMDF177L (RSCAN0.RMDF177.UINT16[R_IO_L]) -#define RSCAN0RMDF177LL (RSCAN0.RMDF177.UINT8[R_IO_LL]) -#define RSCAN0RMDF177LH (RSCAN0.RMDF177.UINT8[R_IO_LH]) -#define RSCAN0RMDF177H (RSCAN0.RMDF177.UINT16[R_IO_H]) -#define RSCAN0RMDF177HL (RSCAN0.RMDF177.UINT8[R_IO_HL]) -#define RSCAN0RMDF177HH (RSCAN0.RMDF177.UINT8[R_IO_HH]) -#define RSCAN0RMID78 (RSCAN0.RMID78.UINT32) -#define RSCAN0RMID78L (RSCAN0.RMID78.UINT16[R_IO_L]) -#define RSCAN0RMID78LL (RSCAN0.RMID78.UINT8[R_IO_LL]) -#define RSCAN0RMID78LH (RSCAN0.RMID78.UINT8[R_IO_LH]) -#define RSCAN0RMID78H (RSCAN0.RMID78.UINT16[R_IO_H]) -#define RSCAN0RMID78HL (RSCAN0.RMID78.UINT8[R_IO_HL]) -#define RSCAN0RMID78HH (RSCAN0.RMID78.UINT8[R_IO_HH]) -#define RSCAN0RMPTR78 (RSCAN0.RMPTR78.UINT32) -#define RSCAN0RMPTR78L (RSCAN0.RMPTR78.UINT16[R_IO_L]) -#define RSCAN0RMPTR78LL (RSCAN0.RMPTR78.UINT8[R_IO_LL]) -#define RSCAN0RMPTR78LH (RSCAN0.RMPTR78.UINT8[R_IO_LH]) -#define RSCAN0RMPTR78H (RSCAN0.RMPTR78.UINT16[R_IO_H]) -#define RSCAN0RMPTR78HL (RSCAN0.RMPTR78.UINT8[R_IO_HL]) -#define RSCAN0RMPTR78HH (RSCAN0.RMPTR78.UINT8[R_IO_HH]) -#define RSCAN0RMDF078 (RSCAN0.RMDF078.UINT32) -#define RSCAN0RMDF078L (RSCAN0.RMDF078.UINT16[R_IO_L]) -#define RSCAN0RMDF078LL (RSCAN0.RMDF078.UINT8[R_IO_LL]) -#define RSCAN0RMDF078LH (RSCAN0.RMDF078.UINT8[R_IO_LH]) -#define RSCAN0RMDF078H (RSCAN0.RMDF078.UINT16[R_IO_H]) -#define RSCAN0RMDF078HL (RSCAN0.RMDF078.UINT8[R_IO_HL]) -#define RSCAN0RMDF078HH (RSCAN0.RMDF078.UINT8[R_IO_HH]) -#define RSCAN0RMDF178 (RSCAN0.RMDF178.UINT32) -#define RSCAN0RMDF178L (RSCAN0.RMDF178.UINT16[R_IO_L]) -#define RSCAN0RMDF178LL (RSCAN0.RMDF178.UINT8[R_IO_LL]) -#define RSCAN0RMDF178LH (RSCAN0.RMDF178.UINT8[R_IO_LH]) -#define RSCAN0RMDF178H (RSCAN0.RMDF178.UINT16[R_IO_H]) -#define RSCAN0RMDF178HL (RSCAN0.RMDF178.UINT8[R_IO_HL]) -#define RSCAN0RMDF178HH (RSCAN0.RMDF178.UINT8[R_IO_HH]) -#define RSCAN0RMID79 (RSCAN0.RMID79.UINT32) -#define RSCAN0RMID79L (RSCAN0.RMID79.UINT16[R_IO_L]) -#define RSCAN0RMID79LL (RSCAN0.RMID79.UINT8[R_IO_LL]) -#define RSCAN0RMID79LH (RSCAN0.RMID79.UINT8[R_IO_LH]) -#define RSCAN0RMID79H (RSCAN0.RMID79.UINT16[R_IO_H]) -#define RSCAN0RMID79HL (RSCAN0.RMID79.UINT8[R_IO_HL]) -#define RSCAN0RMID79HH (RSCAN0.RMID79.UINT8[R_IO_HH]) -#define RSCAN0RMPTR79 (RSCAN0.RMPTR79.UINT32) -#define RSCAN0RMPTR79L (RSCAN0.RMPTR79.UINT16[R_IO_L]) -#define RSCAN0RMPTR79LL (RSCAN0.RMPTR79.UINT8[R_IO_LL]) -#define RSCAN0RMPTR79LH (RSCAN0.RMPTR79.UINT8[R_IO_LH]) -#define RSCAN0RMPTR79H (RSCAN0.RMPTR79.UINT16[R_IO_H]) -#define RSCAN0RMPTR79HL (RSCAN0.RMPTR79.UINT8[R_IO_HL]) -#define RSCAN0RMPTR79HH (RSCAN0.RMPTR79.UINT8[R_IO_HH]) -#define RSCAN0RMDF079 (RSCAN0.RMDF079.UINT32) -#define RSCAN0RMDF079L (RSCAN0.RMDF079.UINT16[R_IO_L]) -#define RSCAN0RMDF079LL (RSCAN0.RMDF079.UINT8[R_IO_LL]) -#define RSCAN0RMDF079LH (RSCAN0.RMDF079.UINT8[R_IO_LH]) -#define RSCAN0RMDF079H (RSCAN0.RMDF079.UINT16[R_IO_H]) -#define RSCAN0RMDF079HL (RSCAN0.RMDF079.UINT8[R_IO_HL]) -#define RSCAN0RMDF079HH (RSCAN0.RMDF079.UINT8[R_IO_HH]) -#define RSCAN0RMDF179 (RSCAN0.RMDF179.UINT32) -#define RSCAN0RMDF179L (RSCAN0.RMDF179.UINT16[R_IO_L]) -#define RSCAN0RMDF179LL (RSCAN0.RMDF179.UINT8[R_IO_LL]) -#define RSCAN0RMDF179LH (RSCAN0.RMDF179.UINT8[R_IO_LH]) -#define RSCAN0RMDF179H (RSCAN0.RMDF179.UINT16[R_IO_H]) -#define RSCAN0RMDF179HL (RSCAN0.RMDF179.UINT8[R_IO_HL]) -#define RSCAN0RMDF179HH (RSCAN0.RMDF179.UINT8[R_IO_HH]) -#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32) -#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L]) -#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL]) -#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH]) -#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H]) -#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL]) -#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH]) -#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32) -#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L]) -#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL]) -#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH]) -#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H]) -#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL]) -#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH]) -#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32) -#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L]) -#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL]) -#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH]) -#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H]) -#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL]) -#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH]) -#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32) -#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L]) -#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL]) -#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH]) -#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H]) -#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL]) -#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH]) -#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32) -#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L]) -#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL]) -#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH]) -#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H]) -#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL]) -#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH]) -#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32) -#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L]) -#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL]) -#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH]) -#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H]) -#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL]) -#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH]) -#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32) -#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L]) -#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL]) -#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH]) -#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H]) -#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL]) -#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH]) -#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32) -#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L]) -#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL]) -#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH]) -#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H]) -#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL]) -#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH]) -#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32) -#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L]) -#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL]) -#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH]) -#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H]) -#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL]) -#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH]) -#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32) -#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L]) -#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL]) -#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH]) -#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H]) -#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL]) -#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH]) -#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32) -#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L]) -#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL]) -#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH]) -#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H]) -#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL]) -#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH]) -#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32) -#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L]) -#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL]) -#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH]) -#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H]) -#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL]) -#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH]) -#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32) -#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L]) -#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL]) -#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH]) -#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H]) -#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL]) -#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH]) -#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32) -#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L]) -#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL]) -#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH]) -#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H]) -#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL]) -#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH]) -#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32) -#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L]) -#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL]) -#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH]) -#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H]) -#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL]) -#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH]) -#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32) -#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L]) -#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL]) -#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH]) -#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H]) -#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL]) -#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH]) -#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32) -#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L]) -#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL]) -#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH]) -#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H]) -#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL]) -#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH]) -#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32) -#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L]) -#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL]) -#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH]) -#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H]) -#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL]) -#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH]) -#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32) -#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L]) -#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL]) -#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH]) -#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H]) -#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL]) -#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH]) -#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32) -#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L]) -#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL]) -#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH]) -#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H]) -#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL]) -#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH]) -#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32) -#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L]) -#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL]) -#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH]) -#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H]) -#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL]) -#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH]) -#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32) -#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L]) -#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL]) -#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH]) -#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H]) -#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL]) -#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH]) -#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32) -#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L]) -#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL]) -#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH]) -#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H]) -#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL]) -#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH]) -#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32) -#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L]) -#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL]) -#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH]) -#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H]) -#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL]) -#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH]) -#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32) -#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L]) -#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL]) -#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH]) -#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H]) -#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL]) -#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH]) -#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32) -#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L]) -#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL]) -#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH]) -#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H]) -#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL]) -#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH]) -#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32) -#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L]) -#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL]) -#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH]) -#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H]) -#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL]) -#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH]) -#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32) -#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L]) -#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL]) -#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH]) -#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H]) -#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL]) -#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH]) -#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32) -#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L]) -#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL]) -#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH]) -#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H]) -#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL]) -#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH]) -#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32) -#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L]) -#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL]) -#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH]) -#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H]) -#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL]) -#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH]) -#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32) -#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L]) -#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL]) -#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH]) -#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H]) -#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL]) -#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH]) -#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32) -#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L]) -#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL]) -#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH]) -#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H]) -#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL]) -#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH]) -#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32) -#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L]) -#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL]) -#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH]) -#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H]) -#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL]) -#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH]) -#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32) -#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L]) -#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL]) -#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH]) -#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H]) -#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL]) -#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH]) -#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32) -#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L]) -#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL]) -#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH]) -#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H]) -#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL]) -#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH]) -#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32) -#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L]) -#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL]) -#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH]) -#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H]) -#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL]) -#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH]) -#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32) -#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L]) -#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL]) -#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH]) -#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H]) -#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL]) -#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH]) -#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32) -#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L]) -#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL]) -#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH]) -#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H]) -#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL]) -#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH]) -#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32) -#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L]) -#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL]) -#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH]) -#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H]) -#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL]) -#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH]) -#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32) -#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L]) -#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL]) -#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH]) -#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H]) -#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL]) -#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH]) -#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32) -#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L]) -#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL]) -#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH]) -#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H]) -#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL]) -#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH]) -#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32) -#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L]) -#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL]) -#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH]) -#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H]) -#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL]) -#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH]) -#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32) -#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L]) -#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL]) -#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH]) -#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H]) -#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL]) -#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH]) -#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32) -#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L]) -#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL]) -#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH]) -#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H]) -#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL]) -#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH]) -#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32) -#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L]) -#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL]) -#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH]) -#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H]) -#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL]) -#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH]) -#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32) -#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L]) -#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL]) -#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH]) -#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H]) -#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL]) -#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH]) -#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32) -#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L]) -#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL]) -#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH]) -#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H]) -#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL]) -#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH]) -#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32) -#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L]) -#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL]) -#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH]) -#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H]) -#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL]) -#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH]) -#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32) -#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L]) -#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL]) -#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH]) -#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H]) -#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL]) -#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH]) -#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32) -#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L]) -#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL]) -#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH]) -#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H]) -#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL]) -#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH]) -#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32) -#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L]) -#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL]) -#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH]) -#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H]) -#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL]) -#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH]) -#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32) -#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L]) -#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL]) -#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH]) -#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H]) -#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL]) -#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH]) -#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32) -#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L]) -#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL]) -#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH]) -#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H]) -#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL]) -#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH]) -#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32) -#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L]) -#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL]) -#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH]) -#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H]) -#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL]) -#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH]) -#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32) -#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L]) -#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL]) -#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH]) -#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H]) -#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL]) -#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH]) -#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32) -#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L]) -#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL]) -#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH]) -#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H]) -#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL]) -#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH]) -#define RSCAN0CFID6 (RSCAN0.CFID6.UINT32) -#define RSCAN0CFID6L (RSCAN0.CFID6.UINT16[R_IO_L]) -#define RSCAN0CFID6LL (RSCAN0.CFID6.UINT8[R_IO_LL]) -#define RSCAN0CFID6LH (RSCAN0.CFID6.UINT8[R_IO_LH]) -#define RSCAN0CFID6H (RSCAN0.CFID6.UINT16[R_IO_H]) -#define RSCAN0CFID6HL (RSCAN0.CFID6.UINT8[R_IO_HL]) -#define RSCAN0CFID6HH (RSCAN0.CFID6.UINT8[R_IO_HH]) -#define RSCAN0CFPTR6 (RSCAN0.CFPTR6.UINT32) -#define RSCAN0CFPTR6L (RSCAN0.CFPTR6.UINT16[R_IO_L]) -#define RSCAN0CFPTR6LL (RSCAN0.CFPTR6.UINT8[R_IO_LL]) -#define RSCAN0CFPTR6LH (RSCAN0.CFPTR6.UINT8[R_IO_LH]) -#define RSCAN0CFPTR6H (RSCAN0.CFPTR6.UINT16[R_IO_H]) -#define RSCAN0CFPTR6HL (RSCAN0.CFPTR6.UINT8[R_IO_HL]) -#define RSCAN0CFPTR6HH (RSCAN0.CFPTR6.UINT8[R_IO_HH]) -#define RSCAN0CFDF06 (RSCAN0.CFDF06.UINT32) -#define RSCAN0CFDF06L (RSCAN0.CFDF06.UINT16[R_IO_L]) -#define RSCAN0CFDF06LL (RSCAN0.CFDF06.UINT8[R_IO_LL]) -#define RSCAN0CFDF06LH (RSCAN0.CFDF06.UINT8[R_IO_LH]) -#define RSCAN0CFDF06H (RSCAN0.CFDF06.UINT16[R_IO_H]) -#define RSCAN0CFDF06HL (RSCAN0.CFDF06.UINT8[R_IO_HL]) -#define RSCAN0CFDF06HH (RSCAN0.CFDF06.UINT8[R_IO_HH]) -#define RSCAN0CFDF16 (RSCAN0.CFDF16.UINT32) -#define RSCAN0CFDF16L (RSCAN0.CFDF16.UINT16[R_IO_L]) -#define RSCAN0CFDF16LL (RSCAN0.CFDF16.UINT8[R_IO_LL]) -#define RSCAN0CFDF16LH (RSCAN0.CFDF16.UINT8[R_IO_LH]) -#define RSCAN0CFDF16H (RSCAN0.CFDF16.UINT16[R_IO_H]) -#define RSCAN0CFDF16HL (RSCAN0.CFDF16.UINT8[R_IO_HL]) -#define RSCAN0CFDF16HH (RSCAN0.CFDF16.UINT8[R_IO_HH]) -#define RSCAN0CFID7 (RSCAN0.CFID7.UINT32) -#define RSCAN0CFID7L (RSCAN0.CFID7.UINT16[R_IO_L]) -#define RSCAN0CFID7LL (RSCAN0.CFID7.UINT8[R_IO_LL]) -#define RSCAN0CFID7LH (RSCAN0.CFID7.UINT8[R_IO_LH]) -#define RSCAN0CFID7H (RSCAN0.CFID7.UINT16[R_IO_H]) -#define RSCAN0CFID7HL (RSCAN0.CFID7.UINT8[R_IO_HL]) -#define RSCAN0CFID7HH (RSCAN0.CFID7.UINT8[R_IO_HH]) -#define RSCAN0CFPTR7 (RSCAN0.CFPTR7.UINT32) -#define RSCAN0CFPTR7L (RSCAN0.CFPTR7.UINT16[R_IO_L]) -#define RSCAN0CFPTR7LL (RSCAN0.CFPTR7.UINT8[R_IO_LL]) -#define RSCAN0CFPTR7LH (RSCAN0.CFPTR7.UINT8[R_IO_LH]) -#define RSCAN0CFPTR7H (RSCAN0.CFPTR7.UINT16[R_IO_H]) -#define RSCAN0CFPTR7HL (RSCAN0.CFPTR7.UINT8[R_IO_HL]) -#define RSCAN0CFPTR7HH (RSCAN0.CFPTR7.UINT8[R_IO_HH]) -#define RSCAN0CFDF07 (RSCAN0.CFDF07.UINT32) -#define RSCAN0CFDF07L (RSCAN0.CFDF07.UINT16[R_IO_L]) -#define RSCAN0CFDF07LL (RSCAN0.CFDF07.UINT8[R_IO_LL]) -#define RSCAN0CFDF07LH (RSCAN0.CFDF07.UINT8[R_IO_LH]) -#define RSCAN0CFDF07H (RSCAN0.CFDF07.UINT16[R_IO_H]) -#define RSCAN0CFDF07HL (RSCAN0.CFDF07.UINT8[R_IO_HL]) -#define RSCAN0CFDF07HH (RSCAN0.CFDF07.UINT8[R_IO_HH]) -#define RSCAN0CFDF17 (RSCAN0.CFDF17.UINT32) -#define RSCAN0CFDF17L (RSCAN0.CFDF17.UINT16[R_IO_L]) -#define RSCAN0CFDF17LL (RSCAN0.CFDF17.UINT8[R_IO_LL]) -#define RSCAN0CFDF17LH (RSCAN0.CFDF17.UINT8[R_IO_LH]) -#define RSCAN0CFDF17H (RSCAN0.CFDF17.UINT16[R_IO_H]) -#define RSCAN0CFDF17HL (RSCAN0.CFDF17.UINT8[R_IO_HL]) -#define RSCAN0CFDF17HH (RSCAN0.CFDF17.UINT8[R_IO_HH]) -#define RSCAN0CFID8 (RSCAN0.CFID8.UINT32) -#define RSCAN0CFID8L (RSCAN0.CFID8.UINT16[R_IO_L]) -#define RSCAN0CFID8LL (RSCAN0.CFID8.UINT8[R_IO_LL]) -#define RSCAN0CFID8LH (RSCAN0.CFID8.UINT8[R_IO_LH]) -#define RSCAN0CFID8H (RSCAN0.CFID8.UINT16[R_IO_H]) -#define RSCAN0CFID8HL (RSCAN0.CFID8.UINT8[R_IO_HL]) -#define RSCAN0CFID8HH (RSCAN0.CFID8.UINT8[R_IO_HH]) -#define RSCAN0CFPTR8 (RSCAN0.CFPTR8.UINT32) -#define RSCAN0CFPTR8L (RSCAN0.CFPTR8.UINT16[R_IO_L]) -#define RSCAN0CFPTR8LL (RSCAN0.CFPTR8.UINT8[R_IO_LL]) -#define RSCAN0CFPTR8LH (RSCAN0.CFPTR8.UINT8[R_IO_LH]) -#define RSCAN0CFPTR8H (RSCAN0.CFPTR8.UINT16[R_IO_H]) -#define RSCAN0CFPTR8HL (RSCAN0.CFPTR8.UINT8[R_IO_HL]) -#define RSCAN0CFPTR8HH (RSCAN0.CFPTR8.UINT8[R_IO_HH]) -#define RSCAN0CFDF08 (RSCAN0.CFDF08.UINT32) -#define RSCAN0CFDF08L (RSCAN0.CFDF08.UINT16[R_IO_L]) -#define RSCAN0CFDF08LL (RSCAN0.CFDF08.UINT8[R_IO_LL]) -#define RSCAN0CFDF08LH (RSCAN0.CFDF08.UINT8[R_IO_LH]) -#define RSCAN0CFDF08H (RSCAN0.CFDF08.UINT16[R_IO_H]) -#define RSCAN0CFDF08HL (RSCAN0.CFDF08.UINT8[R_IO_HL]) -#define RSCAN0CFDF08HH (RSCAN0.CFDF08.UINT8[R_IO_HH]) -#define RSCAN0CFDF18 (RSCAN0.CFDF18.UINT32) -#define RSCAN0CFDF18L (RSCAN0.CFDF18.UINT16[R_IO_L]) -#define RSCAN0CFDF18LL (RSCAN0.CFDF18.UINT8[R_IO_LL]) -#define RSCAN0CFDF18LH (RSCAN0.CFDF18.UINT8[R_IO_LH]) -#define RSCAN0CFDF18H (RSCAN0.CFDF18.UINT16[R_IO_H]) -#define RSCAN0CFDF18HL (RSCAN0.CFDF18.UINT8[R_IO_HL]) -#define RSCAN0CFDF18HH (RSCAN0.CFDF18.UINT8[R_IO_HH]) -#define RSCAN0CFID9 (RSCAN0.CFID9.UINT32) -#define RSCAN0CFID9L (RSCAN0.CFID9.UINT16[R_IO_L]) -#define RSCAN0CFID9LL (RSCAN0.CFID9.UINT8[R_IO_LL]) -#define RSCAN0CFID9LH (RSCAN0.CFID9.UINT8[R_IO_LH]) -#define RSCAN0CFID9H (RSCAN0.CFID9.UINT16[R_IO_H]) -#define RSCAN0CFID9HL (RSCAN0.CFID9.UINT8[R_IO_HL]) -#define RSCAN0CFID9HH (RSCAN0.CFID9.UINT8[R_IO_HH]) -#define RSCAN0CFPTR9 (RSCAN0.CFPTR9.UINT32) -#define RSCAN0CFPTR9L (RSCAN0.CFPTR9.UINT16[R_IO_L]) -#define RSCAN0CFPTR9LL (RSCAN0.CFPTR9.UINT8[R_IO_LL]) -#define RSCAN0CFPTR9LH (RSCAN0.CFPTR9.UINT8[R_IO_LH]) -#define RSCAN0CFPTR9H (RSCAN0.CFPTR9.UINT16[R_IO_H]) -#define RSCAN0CFPTR9HL (RSCAN0.CFPTR9.UINT8[R_IO_HL]) -#define RSCAN0CFPTR9HH (RSCAN0.CFPTR9.UINT8[R_IO_HH]) -#define RSCAN0CFDF09 (RSCAN0.CFDF09.UINT32) -#define RSCAN0CFDF09L (RSCAN0.CFDF09.UINT16[R_IO_L]) -#define RSCAN0CFDF09LL (RSCAN0.CFDF09.UINT8[R_IO_LL]) -#define RSCAN0CFDF09LH (RSCAN0.CFDF09.UINT8[R_IO_LH]) -#define RSCAN0CFDF09H (RSCAN0.CFDF09.UINT16[R_IO_H]) -#define RSCAN0CFDF09HL (RSCAN0.CFDF09.UINT8[R_IO_HL]) -#define RSCAN0CFDF09HH (RSCAN0.CFDF09.UINT8[R_IO_HH]) -#define RSCAN0CFDF19 (RSCAN0.CFDF19.UINT32) -#define RSCAN0CFDF19L (RSCAN0.CFDF19.UINT16[R_IO_L]) -#define RSCAN0CFDF19LL (RSCAN0.CFDF19.UINT8[R_IO_LL]) -#define RSCAN0CFDF19LH (RSCAN0.CFDF19.UINT8[R_IO_LH]) -#define RSCAN0CFDF19H (RSCAN0.CFDF19.UINT16[R_IO_H]) -#define RSCAN0CFDF19HL (RSCAN0.CFDF19.UINT8[R_IO_HL]) -#define RSCAN0CFDF19HH (RSCAN0.CFDF19.UINT8[R_IO_HH]) -#define RSCAN0CFID10 (RSCAN0.CFID10.UINT32) -#define RSCAN0CFID10L (RSCAN0.CFID10.UINT16[R_IO_L]) -#define RSCAN0CFID10LL (RSCAN0.CFID10.UINT8[R_IO_LL]) -#define RSCAN0CFID10LH (RSCAN0.CFID10.UINT8[R_IO_LH]) -#define RSCAN0CFID10H (RSCAN0.CFID10.UINT16[R_IO_H]) -#define RSCAN0CFID10HL (RSCAN0.CFID10.UINT8[R_IO_HL]) -#define RSCAN0CFID10HH (RSCAN0.CFID10.UINT8[R_IO_HH]) -#define RSCAN0CFPTR10 (RSCAN0.CFPTR10.UINT32) -#define RSCAN0CFPTR10L (RSCAN0.CFPTR10.UINT16[R_IO_L]) -#define RSCAN0CFPTR10LL (RSCAN0.CFPTR10.UINT8[R_IO_LL]) -#define RSCAN0CFPTR10LH (RSCAN0.CFPTR10.UINT8[R_IO_LH]) -#define RSCAN0CFPTR10H (RSCAN0.CFPTR10.UINT16[R_IO_H]) -#define RSCAN0CFPTR10HL (RSCAN0.CFPTR10.UINT8[R_IO_HL]) -#define RSCAN0CFPTR10HH (RSCAN0.CFPTR10.UINT8[R_IO_HH]) -#define RSCAN0CFDF010 (RSCAN0.CFDF010.UINT32) -#define RSCAN0CFDF010L (RSCAN0.CFDF010.UINT16[R_IO_L]) -#define RSCAN0CFDF010LL (RSCAN0.CFDF010.UINT8[R_IO_LL]) -#define RSCAN0CFDF010LH (RSCAN0.CFDF010.UINT8[R_IO_LH]) -#define RSCAN0CFDF010H (RSCAN0.CFDF010.UINT16[R_IO_H]) -#define RSCAN0CFDF010HL (RSCAN0.CFDF010.UINT8[R_IO_HL]) -#define RSCAN0CFDF010HH (RSCAN0.CFDF010.UINT8[R_IO_HH]) -#define RSCAN0CFDF110 (RSCAN0.CFDF110.UINT32) -#define RSCAN0CFDF110L (RSCAN0.CFDF110.UINT16[R_IO_L]) -#define RSCAN0CFDF110LL (RSCAN0.CFDF110.UINT8[R_IO_LL]) -#define RSCAN0CFDF110LH (RSCAN0.CFDF110.UINT8[R_IO_LH]) -#define RSCAN0CFDF110H (RSCAN0.CFDF110.UINT16[R_IO_H]) -#define RSCAN0CFDF110HL (RSCAN0.CFDF110.UINT8[R_IO_HL]) -#define RSCAN0CFDF110HH (RSCAN0.CFDF110.UINT8[R_IO_HH]) -#define RSCAN0CFID11 (RSCAN0.CFID11.UINT32) -#define RSCAN0CFID11L (RSCAN0.CFID11.UINT16[R_IO_L]) -#define RSCAN0CFID11LL (RSCAN0.CFID11.UINT8[R_IO_LL]) -#define RSCAN0CFID11LH (RSCAN0.CFID11.UINT8[R_IO_LH]) -#define RSCAN0CFID11H (RSCAN0.CFID11.UINT16[R_IO_H]) -#define RSCAN0CFID11HL (RSCAN0.CFID11.UINT8[R_IO_HL]) -#define RSCAN0CFID11HH (RSCAN0.CFID11.UINT8[R_IO_HH]) -#define RSCAN0CFPTR11 (RSCAN0.CFPTR11.UINT32) -#define RSCAN0CFPTR11L (RSCAN0.CFPTR11.UINT16[R_IO_L]) -#define RSCAN0CFPTR11LL (RSCAN0.CFPTR11.UINT8[R_IO_LL]) -#define RSCAN0CFPTR11LH (RSCAN0.CFPTR11.UINT8[R_IO_LH]) -#define RSCAN0CFPTR11H (RSCAN0.CFPTR11.UINT16[R_IO_H]) -#define RSCAN0CFPTR11HL (RSCAN0.CFPTR11.UINT8[R_IO_HL]) -#define RSCAN0CFPTR11HH (RSCAN0.CFPTR11.UINT8[R_IO_HH]) -#define RSCAN0CFDF011 (RSCAN0.CFDF011.UINT32) -#define RSCAN0CFDF011L (RSCAN0.CFDF011.UINT16[R_IO_L]) -#define RSCAN0CFDF011LL (RSCAN0.CFDF011.UINT8[R_IO_LL]) -#define RSCAN0CFDF011LH (RSCAN0.CFDF011.UINT8[R_IO_LH]) -#define RSCAN0CFDF011H (RSCAN0.CFDF011.UINT16[R_IO_H]) -#define RSCAN0CFDF011HL (RSCAN0.CFDF011.UINT8[R_IO_HL]) -#define RSCAN0CFDF011HH (RSCAN0.CFDF011.UINT8[R_IO_HH]) -#define RSCAN0CFDF111 (RSCAN0.CFDF111.UINT32) -#define RSCAN0CFDF111L (RSCAN0.CFDF111.UINT16[R_IO_L]) -#define RSCAN0CFDF111LL (RSCAN0.CFDF111.UINT8[R_IO_LL]) -#define RSCAN0CFDF111LH (RSCAN0.CFDF111.UINT8[R_IO_LH]) -#define RSCAN0CFDF111H (RSCAN0.CFDF111.UINT16[R_IO_H]) -#define RSCAN0CFDF111HL (RSCAN0.CFDF111.UINT8[R_IO_HL]) -#define RSCAN0CFDF111HH (RSCAN0.CFDF111.UINT8[R_IO_HH]) -#define RSCAN0CFID12 (RSCAN0.CFID12.UINT32) -#define RSCAN0CFID12L (RSCAN0.CFID12.UINT16[R_IO_L]) -#define RSCAN0CFID12LL (RSCAN0.CFID12.UINT8[R_IO_LL]) -#define RSCAN0CFID12LH (RSCAN0.CFID12.UINT8[R_IO_LH]) -#define RSCAN0CFID12H (RSCAN0.CFID12.UINT16[R_IO_H]) -#define RSCAN0CFID12HL (RSCAN0.CFID12.UINT8[R_IO_HL]) -#define RSCAN0CFID12HH (RSCAN0.CFID12.UINT8[R_IO_HH]) -#define RSCAN0CFPTR12 (RSCAN0.CFPTR12.UINT32) -#define RSCAN0CFPTR12L (RSCAN0.CFPTR12.UINT16[R_IO_L]) -#define RSCAN0CFPTR12LL (RSCAN0.CFPTR12.UINT8[R_IO_LL]) -#define RSCAN0CFPTR12LH (RSCAN0.CFPTR12.UINT8[R_IO_LH]) -#define RSCAN0CFPTR12H (RSCAN0.CFPTR12.UINT16[R_IO_H]) -#define RSCAN0CFPTR12HL (RSCAN0.CFPTR12.UINT8[R_IO_HL]) -#define RSCAN0CFPTR12HH (RSCAN0.CFPTR12.UINT8[R_IO_HH]) -#define RSCAN0CFDF012 (RSCAN0.CFDF012.UINT32) -#define RSCAN0CFDF012L (RSCAN0.CFDF012.UINT16[R_IO_L]) -#define RSCAN0CFDF012LL (RSCAN0.CFDF012.UINT8[R_IO_LL]) -#define RSCAN0CFDF012LH (RSCAN0.CFDF012.UINT8[R_IO_LH]) -#define RSCAN0CFDF012H (RSCAN0.CFDF012.UINT16[R_IO_H]) -#define RSCAN0CFDF012HL (RSCAN0.CFDF012.UINT8[R_IO_HL]) -#define RSCAN0CFDF012HH (RSCAN0.CFDF012.UINT8[R_IO_HH]) -#define RSCAN0CFDF112 (RSCAN0.CFDF112.UINT32) -#define RSCAN0CFDF112L (RSCAN0.CFDF112.UINT16[R_IO_L]) -#define RSCAN0CFDF112LL (RSCAN0.CFDF112.UINT8[R_IO_LL]) -#define RSCAN0CFDF112LH (RSCAN0.CFDF112.UINT8[R_IO_LH]) -#define RSCAN0CFDF112H (RSCAN0.CFDF112.UINT16[R_IO_H]) -#define RSCAN0CFDF112HL (RSCAN0.CFDF112.UINT8[R_IO_HL]) -#define RSCAN0CFDF112HH (RSCAN0.CFDF112.UINT8[R_IO_HH]) -#define RSCAN0CFID13 (RSCAN0.CFID13.UINT32) -#define RSCAN0CFID13L (RSCAN0.CFID13.UINT16[R_IO_L]) -#define RSCAN0CFID13LL (RSCAN0.CFID13.UINT8[R_IO_LL]) -#define RSCAN0CFID13LH (RSCAN0.CFID13.UINT8[R_IO_LH]) -#define RSCAN0CFID13H (RSCAN0.CFID13.UINT16[R_IO_H]) -#define RSCAN0CFID13HL (RSCAN0.CFID13.UINT8[R_IO_HL]) -#define RSCAN0CFID13HH (RSCAN0.CFID13.UINT8[R_IO_HH]) -#define RSCAN0CFPTR13 (RSCAN0.CFPTR13.UINT32) -#define RSCAN0CFPTR13L (RSCAN0.CFPTR13.UINT16[R_IO_L]) -#define RSCAN0CFPTR13LL (RSCAN0.CFPTR13.UINT8[R_IO_LL]) -#define RSCAN0CFPTR13LH (RSCAN0.CFPTR13.UINT8[R_IO_LH]) -#define RSCAN0CFPTR13H (RSCAN0.CFPTR13.UINT16[R_IO_H]) -#define RSCAN0CFPTR13HL (RSCAN0.CFPTR13.UINT8[R_IO_HL]) -#define RSCAN0CFPTR13HH (RSCAN0.CFPTR13.UINT8[R_IO_HH]) -#define RSCAN0CFDF013 (RSCAN0.CFDF013.UINT32) -#define RSCAN0CFDF013L (RSCAN0.CFDF013.UINT16[R_IO_L]) -#define RSCAN0CFDF013LL (RSCAN0.CFDF013.UINT8[R_IO_LL]) -#define RSCAN0CFDF013LH (RSCAN0.CFDF013.UINT8[R_IO_LH]) -#define RSCAN0CFDF013H (RSCAN0.CFDF013.UINT16[R_IO_H]) -#define RSCAN0CFDF013HL (RSCAN0.CFDF013.UINT8[R_IO_HL]) -#define RSCAN0CFDF013HH (RSCAN0.CFDF013.UINT8[R_IO_HH]) -#define RSCAN0CFDF113 (RSCAN0.CFDF113.UINT32) -#define RSCAN0CFDF113L (RSCAN0.CFDF113.UINT16[R_IO_L]) -#define RSCAN0CFDF113LL (RSCAN0.CFDF113.UINT8[R_IO_LL]) -#define RSCAN0CFDF113LH (RSCAN0.CFDF113.UINT8[R_IO_LH]) -#define RSCAN0CFDF113H (RSCAN0.CFDF113.UINT16[R_IO_H]) -#define RSCAN0CFDF113HL (RSCAN0.CFDF113.UINT8[R_IO_HL]) -#define RSCAN0CFDF113HH (RSCAN0.CFDF113.UINT8[R_IO_HH]) -#define RSCAN0CFID14 (RSCAN0.CFID14.UINT32) -#define RSCAN0CFID14L (RSCAN0.CFID14.UINT16[R_IO_L]) -#define RSCAN0CFID14LL (RSCAN0.CFID14.UINT8[R_IO_LL]) -#define RSCAN0CFID14LH (RSCAN0.CFID14.UINT8[R_IO_LH]) -#define RSCAN0CFID14H (RSCAN0.CFID14.UINT16[R_IO_H]) -#define RSCAN0CFID14HL (RSCAN0.CFID14.UINT8[R_IO_HL]) -#define RSCAN0CFID14HH (RSCAN0.CFID14.UINT8[R_IO_HH]) -#define RSCAN0CFPTR14 (RSCAN0.CFPTR14.UINT32) -#define RSCAN0CFPTR14L (RSCAN0.CFPTR14.UINT16[R_IO_L]) -#define RSCAN0CFPTR14LL (RSCAN0.CFPTR14.UINT8[R_IO_LL]) -#define RSCAN0CFPTR14LH (RSCAN0.CFPTR14.UINT8[R_IO_LH]) -#define RSCAN0CFPTR14H (RSCAN0.CFPTR14.UINT16[R_IO_H]) -#define RSCAN0CFPTR14HL (RSCAN0.CFPTR14.UINT8[R_IO_HL]) -#define RSCAN0CFPTR14HH (RSCAN0.CFPTR14.UINT8[R_IO_HH]) -#define RSCAN0CFDF014 (RSCAN0.CFDF014.UINT32) -#define RSCAN0CFDF014L (RSCAN0.CFDF014.UINT16[R_IO_L]) -#define RSCAN0CFDF014LL (RSCAN0.CFDF014.UINT8[R_IO_LL]) -#define RSCAN0CFDF014LH (RSCAN0.CFDF014.UINT8[R_IO_LH]) -#define RSCAN0CFDF014H (RSCAN0.CFDF014.UINT16[R_IO_H]) -#define RSCAN0CFDF014HL (RSCAN0.CFDF014.UINT8[R_IO_HL]) -#define RSCAN0CFDF014HH (RSCAN0.CFDF014.UINT8[R_IO_HH]) -#define RSCAN0CFDF114 (RSCAN0.CFDF114.UINT32) -#define RSCAN0CFDF114L (RSCAN0.CFDF114.UINT16[R_IO_L]) -#define RSCAN0CFDF114LL (RSCAN0.CFDF114.UINT8[R_IO_LL]) -#define RSCAN0CFDF114LH (RSCAN0.CFDF114.UINT8[R_IO_LH]) -#define RSCAN0CFDF114H (RSCAN0.CFDF114.UINT16[R_IO_H]) -#define RSCAN0CFDF114HL (RSCAN0.CFDF114.UINT8[R_IO_HL]) -#define RSCAN0CFDF114HH (RSCAN0.CFDF114.UINT8[R_IO_HH]) -#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32) -#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L]) -#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL]) -#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH]) -#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H]) -#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL]) -#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH]) -#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32) -#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L]) -#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL]) -#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH]) -#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H]) -#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL]) -#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH]) -#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32) -#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L]) -#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL]) -#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH]) -#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H]) -#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL]) -#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH]) -#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32) -#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L]) -#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL]) -#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH]) -#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H]) -#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL]) -#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH]) -#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32) -#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L]) -#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL]) -#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH]) -#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H]) -#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL]) -#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH]) -#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32) -#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L]) -#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL]) -#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH]) -#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H]) -#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL]) -#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH]) -#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32) -#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L]) -#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL]) -#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH]) -#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H]) -#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL]) -#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH]) -#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32) -#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L]) -#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL]) -#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH]) -#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H]) -#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL]) -#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH]) -#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32) -#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L]) -#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL]) -#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH]) -#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H]) -#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL]) -#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH]) -#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32) -#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L]) -#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL]) -#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH]) -#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H]) -#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL]) -#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH]) -#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32) -#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L]) -#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL]) -#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH]) -#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H]) -#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL]) -#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH]) -#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32) -#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L]) -#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL]) -#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH]) -#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H]) -#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL]) -#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH]) -#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32) -#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L]) -#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL]) -#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH]) -#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H]) -#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL]) -#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH]) -#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32) -#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L]) -#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL]) -#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH]) -#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H]) -#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL]) -#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH]) -#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32) -#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L]) -#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL]) -#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH]) -#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H]) -#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL]) -#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH]) -#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32) -#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L]) -#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL]) -#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH]) -#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H]) -#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL]) -#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH]) -#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32) -#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L]) -#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL]) -#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH]) -#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H]) -#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL]) -#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH]) -#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32) -#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L]) -#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL]) -#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH]) -#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H]) -#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL]) -#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH]) -#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32) -#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L]) -#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL]) -#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH]) -#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H]) -#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL]) -#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH]) -#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32) -#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L]) -#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL]) -#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH]) -#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H]) -#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL]) -#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH]) -#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32) -#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L]) -#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL]) -#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH]) -#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H]) -#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL]) -#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH]) -#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32) -#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L]) -#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL]) -#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH]) -#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H]) -#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL]) -#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH]) -#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32) -#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L]) -#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL]) -#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH]) -#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H]) -#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL]) -#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH]) -#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32) -#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L]) -#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL]) -#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH]) -#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H]) -#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL]) -#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH]) -#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32) -#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L]) -#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL]) -#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH]) -#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H]) -#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL]) -#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH]) -#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32) -#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L]) -#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL]) -#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH]) -#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H]) -#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL]) -#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH]) -#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32) -#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L]) -#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL]) -#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH]) -#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H]) -#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL]) -#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH]) -#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32) -#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L]) -#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL]) -#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH]) -#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H]) -#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL]) -#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH]) -#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32) -#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L]) -#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL]) -#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH]) -#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H]) -#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL]) -#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH]) -#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32) -#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L]) -#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL]) -#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH]) -#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H]) -#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL]) -#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH]) -#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32) -#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L]) -#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL]) -#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH]) -#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H]) -#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL]) -#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH]) -#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32) -#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L]) -#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL]) -#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH]) -#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H]) -#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL]) -#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH]) -#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32) -#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L]) -#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL]) -#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH]) -#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H]) -#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL]) -#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH]) -#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32) -#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L]) -#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL]) -#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH]) -#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H]) -#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL]) -#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH]) -#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32) -#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L]) -#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL]) -#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH]) -#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H]) -#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL]) -#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH]) -#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32) -#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L]) -#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL]) -#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH]) -#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H]) -#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL]) -#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH]) -#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32) -#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L]) -#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL]) -#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH]) -#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H]) -#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL]) -#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH]) -#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32) -#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L]) -#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL]) -#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH]) -#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H]) -#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL]) -#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH]) -#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32) -#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L]) -#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL]) -#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH]) -#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H]) -#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL]) -#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH]) -#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32) -#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L]) -#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL]) -#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH]) -#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H]) -#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL]) -#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH]) -#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32) -#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L]) -#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL]) -#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH]) -#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H]) -#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL]) -#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH]) -#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32) -#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L]) -#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL]) -#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH]) -#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H]) -#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL]) -#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH]) -#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32) -#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L]) -#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL]) -#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH]) -#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H]) -#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL]) -#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH]) -#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32) -#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L]) -#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL]) -#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH]) -#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H]) -#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL]) -#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH]) -#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32) -#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L]) -#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL]) -#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH]) -#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H]) -#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL]) -#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH]) -#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32) -#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L]) -#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL]) -#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH]) -#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H]) -#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL]) -#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH]) -#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32) -#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L]) -#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL]) -#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH]) -#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H]) -#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL]) -#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH]) -#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32) -#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L]) -#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL]) -#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH]) -#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H]) -#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL]) -#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH]) -#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32) -#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L]) -#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL]) -#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH]) -#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H]) -#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL]) -#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH]) -#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32) -#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L]) -#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL]) -#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH]) -#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H]) -#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL]) -#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH]) -#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32) -#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L]) -#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL]) -#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH]) -#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H]) -#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL]) -#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH]) -#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32) -#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L]) -#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL]) -#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH]) -#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H]) -#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL]) -#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH]) -#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32) -#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L]) -#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL]) -#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH]) -#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H]) -#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL]) -#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH]) -#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32) -#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L]) -#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL]) -#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH]) -#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H]) -#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL]) -#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH]) -#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32) -#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L]) -#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL]) -#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH]) -#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H]) -#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL]) -#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH]) -#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32) -#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L]) -#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL]) -#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH]) -#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H]) -#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL]) -#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH]) -#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32) -#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L]) -#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL]) -#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH]) -#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H]) -#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL]) -#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH]) -#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32) -#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L]) -#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL]) -#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH]) -#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H]) -#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL]) -#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH]) -#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32) -#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L]) -#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL]) -#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH]) -#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H]) -#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL]) -#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH]) -#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32) -#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L]) -#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL]) -#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH]) -#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H]) -#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL]) -#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH]) -#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32) -#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L]) -#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL]) -#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH]) -#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H]) -#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL]) -#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH]) -#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32) -#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L]) -#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL]) -#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH]) -#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H]) -#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL]) -#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH]) -#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32) -#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L]) -#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL]) -#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH]) -#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H]) -#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL]) -#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH]) -#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32) -#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L]) -#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL]) -#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH]) -#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H]) -#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL]) -#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH]) -#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32) -#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L]) -#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL]) -#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH]) -#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H]) -#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL]) -#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH]) -#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32) -#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L]) -#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL]) -#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH]) -#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H]) -#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL]) -#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH]) -#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32) -#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L]) -#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL]) -#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH]) -#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H]) -#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL]) -#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH]) -#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32) -#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L]) -#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL]) -#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH]) -#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H]) -#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL]) -#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH]) -#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32) -#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L]) -#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL]) -#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH]) -#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H]) -#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL]) -#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH]) -#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32) -#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L]) -#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL]) -#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH]) -#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H]) -#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL]) -#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH]) -#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32) -#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L]) -#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL]) -#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH]) -#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H]) -#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL]) -#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH]) -#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32) -#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L]) -#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL]) -#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH]) -#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H]) -#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL]) -#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH]) -#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32) -#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L]) -#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL]) -#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH]) -#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H]) -#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL]) -#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH]) -#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32) -#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L]) -#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL]) -#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH]) -#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H]) -#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL]) -#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH]) -#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32) -#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L]) -#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL]) -#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH]) -#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H]) -#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL]) -#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH]) -#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32) -#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L]) -#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL]) -#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH]) -#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H]) -#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL]) -#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH]) -#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32) -#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L]) -#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL]) -#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH]) -#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H]) -#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL]) -#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH]) -#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32) -#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L]) -#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL]) -#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH]) -#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H]) -#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL]) -#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH]) -#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32) -#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L]) -#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL]) -#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH]) -#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H]) -#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL]) -#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH]) -#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32) -#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L]) -#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL]) -#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH]) -#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H]) -#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL]) -#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH]) -#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32) -#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L]) -#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL]) -#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH]) -#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H]) -#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL]) -#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH]) -#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32) -#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L]) -#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL]) -#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH]) -#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H]) -#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL]) -#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH]) -#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32) -#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L]) -#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL]) -#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH]) -#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H]) -#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL]) -#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH]) -#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32) -#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L]) -#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL]) -#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH]) -#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H]) -#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL]) -#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH]) -#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32) -#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L]) -#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL]) -#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH]) -#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H]) -#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL]) -#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH]) -#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32) -#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L]) -#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL]) -#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH]) -#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H]) -#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL]) -#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH]) -#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32) -#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L]) -#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL]) -#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH]) -#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H]) -#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL]) -#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH]) -#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32) -#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L]) -#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL]) -#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH]) -#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H]) -#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL]) -#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH]) -#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32) -#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L]) -#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL]) -#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH]) -#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H]) -#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL]) -#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH]) -#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32) -#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L]) -#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL]) -#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH]) -#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H]) -#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL]) -#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH]) -#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32) -#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L]) -#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL]) -#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH]) -#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H]) -#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL]) -#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH]) -#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32) -#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L]) -#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL]) -#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH]) -#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H]) -#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL]) -#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH]) -#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32) -#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L]) -#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL]) -#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH]) -#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H]) -#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL]) -#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH]) -#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32) -#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L]) -#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL]) -#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH]) -#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H]) -#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL]) -#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH]) -#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32) -#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L]) -#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL]) -#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH]) -#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H]) -#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL]) -#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH]) -#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32) -#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L]) -#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL]) -#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH]) -#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H]) -#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL]) -#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH]) -#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32) -#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L]) -#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL]) -#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH]) -#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H]) -#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL]) -#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH]) -#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32) -#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L]) -#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL]) -#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH]) -#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H]) -#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL]) -#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH]) -#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32) -#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L]) -#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL]) -#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH]) -#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H]) -#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL]) -#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH]) -#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32) -#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L]) -#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL]) -#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH]) -#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H]) -#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL]) -#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH]) -#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32) -#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L]) -#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL]) -#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH]) -#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H]) -#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL]) -#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH]) -#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32) -#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L]) -#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL]) -#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH]) -#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H]) -#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL]) -#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH]) -#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32) -#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L]) -#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL]) -#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH]) -#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H]) -#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL]) -#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH]) -#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32) -#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L]) -#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL]) -#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH]) -#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H]) -#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL]) -#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH]) -#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32) -#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L]) -#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL]) -#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH]) -#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H]) -#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL]) -#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH]) -#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32) -#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L]) -#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL]) -#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH]) -#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H]) -#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL]) -#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH]) -#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32) -#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L]) -#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL]) -#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH]) -#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H]) -#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL]) -#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH]) -#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32) -#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L]) -#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL]) -#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH]) -#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H]) -#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL]) -#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH]) -#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32) -#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L]) -#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL]) -#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH]) -#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H]) -#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL]) -#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH]) -#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32) -#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L]) -#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL]) -#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH]) -#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H]) -#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL]) -#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH]) -#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32) -#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L]) -#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL]) -#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH]) -#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H]) -#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL]) -#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH]) -#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32) -#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L]) -#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL]) -#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH]) -#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H]) -#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL]) -#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH]) -#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32) -#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L]) -#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL]) -#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH]) -#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H]) -#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL]) -#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH]) -#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32) -#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L]) -#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL]) -#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH]) -#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H]) -#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL]) -#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH]) -#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32) -#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L]) -#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL]) -#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH]) -#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H]) -#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL]) -#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH]) -#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32) -#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L]) -#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL]) -#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH]) -#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H]) -#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL]) -#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH]) -#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32) -#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L]) -#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL]) -#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH]) -#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H]) -#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL]) -#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH]) -#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32) -#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L]) -#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL]) -#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH]) -#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H]) -#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL]) -#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH]) -#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32) -#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L]) -#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL]) -#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH]) -#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H]) -#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL]) -#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH]) -#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32) -#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L]) -#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL]) -#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH]) -#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H]) -#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL]) -#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH]) -#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32) -#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L]) -#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL]) -#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH]) -#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H]) -#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL]) -#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH]) -#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32) -#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L]) -#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL]) -#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH]) -#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H]) -#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL]) -#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH]) -#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32) -#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L]) -#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL]) -#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH]) -#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H]) -#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL]) -#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH]) -#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32) -#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L]) -#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL]) -#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH]) -#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H]) -#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL]) -#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH]) -#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32) -#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L]) -#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL]) -#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH]) -#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H]) -#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL]) -#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH]) -#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32) -#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L]) -#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL]) -#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH]) -#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H]) -#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL]) -#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH]) -#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32) -#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L]) -#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL]) -#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH]) -#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H]) -#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL]) -#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH]) -#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32) -#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L]) -#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL]) -#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH]) -#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H]) -#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL]) -#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH]) -#define RSCAN0TMID32 (RSCAN0.TMID32.UINT32) -#define RSCAN0TMID32L (RSCAN0.TMID32.UINT16[R_IO_L]) -#define RSCAN0TMID32LL (RSCAN0.TMID32.UINT8[R_IO_LL]) -#define RSCAN0TMID32LH (RSCAN0.TMID32.UINT8[R_IO_LH]) -#define RSCAN0TMID32H (RSCAN0.TMID32.UINT16[R_IO_H]) -#define RSCAN0TMID32HL (RSCAN0.TMID32.UINT8[R_IO_HL]) -#define RSCAN0TMID32HH (RSCAN0.TMID32.UINT8[R_IO_HH]) -#define RSCAN0TMPTR32 (RSCAN0.TMPTR32.UINT32) -#define RSCAN0TMPTR32L (RSCAN0.TMPTR32.UINT16[R_IO_L]) -#define RSCAN0TMPTR32LL (RSCAN0.TMPTR32.UINT8[R_IO_LL]) -#define RSCAN0TMPTR32LH (RSCAN0.TMPTR32.UINT8[R_IO_LH]) -#define RSCAN0TMPTR32H (RSCAN0.TMPTR32.UINT16[R_IO_H]) -#define RSCAN0TMPTR32HL (RSCAN0.TMPTR32.UINT8[R_IO_HL]) -#define RSCAN0TMPTR32HH (RSCAN0.TMPTR32.UINT8[R_IO_HH]) -#define RSCAN0TMDF032 (RSCAN0.TMDF032.UINT32) -#define RSCAN0TMDF032L (RSCAN0.TMDF032.UINT16[R_IO_L]) -#define RSCAN0TMDF032LL (RSCAN0.TMDF032.UINT8[R_IO_LL]) -#define RSCAN0TMDF032LH (RSCAN0.TMDF032.UINT8[R_IO_LH]) -#define RSCAN0TMDF032H (RSCAN0.TMDF032.UINT16[R_IO_H]) -#define RSCAN0TMDF032HL (RSCAN0.TMDF032.UINT8[R_IO_HL]) -#define RSCAN0TMDF032HH (RSCAN0.TMDF032.UINT8[R_IO_HH]) -#define RSCAN0TMDF132 (RSCAN0.TMDF132.UINT32) -#define RSCAN0TMDF132L (RSCAN0.TMDF132.UINT16[R_IO_L]) -#define RSCAN0TMDF132LL (RSCAN0.TMDF132.UINT8[R_IO_LL]) -#define RSCAN0TMDF132LH (RSCAN0.TMDF132.UINT8[R_IO_LH]) -#define RSCAN0TMDF132H (RSCAN0.TMDF132.UINT16[R_IO_H]) -#define RSCAN0TMDF132HL (RSCAN0.TMDF132.UINT8[R_IO_HL]) -#define RSCAN0TMDF132HH (RSCAN0.TMDF132.UINT8[R_IO_HH]) -#define RSCAN0TMID33 (RSCAN0.TMID33.UINT32) -#define RSCAN0TMID33L (RSCAN0.TMID33.UINT16[R_IO_L]) -#define RSCAN0TMID33LL (RSCAN0.TMID33.UINT8[R_IO_LL]) -#define RSCAN0TMID33LH (RSCAN0.TMID33.UINT8[R_IO_LH]) -#define RSCAN0TMID33H (RSCAN0.TMID33.UINT16[R_IO_H]) -#define RSCAN0TMID33HL (RSCAN0.TMID33.UINT8[R_IO_HL]) -#define RSCAN0TMID33HH (RSCAN0.TMID33.UINT8[R_IO_HH]) -#define RSCAN0TMPTR33 (RSCAN0.TMPTR33.UINT32) -#define RSCAN0TMPTR33L (RSCAN0.TMPTR33.UINT16[R_IO_L]) -#define RSCAN0TMPTR33LL (RSCAN0.TMPTR33.UINT8[R_IO_LL]) -#define RSCAN0TMPTR33LH (RSCAN0.TMPTR33.UINT8[R_IO_LH]) -#define RSCAN0TMPTR33H (RSCAN0.TMPTR33.UINT16[R_IO_H]) -#define RSCAN0TMPTR33HL (RSCAN0.TMPTR33.UINT8[R_IO_HL]) -#define RSCAN0TMPTR33HH (RSCAN0.TMPTR33.UINT8[R_IO_HH]) -#define RSCAN0TMDF033 (RSCAN0.TMDF033.UINT32) -#define RSCAN0TMDF033L (RSCAN0.TMDF033.UINT16[R_IO_L]) -#define RSCAN0TMDF033LL (RSCAN0.TMDF033.UINT8[R_IO_LL]) -#define RSCAN0TMDF033LH (RSCAN0.TMDF033.UINT8[R_IO_LH]) -#define RSCAN0TMDF033H (RSCAN0.TMDF033.UINT16[R_IO_H]) -#define RSCAN0TMDF033HL (RSCAN0.TMDF033.UINT8[R_IO_HL]) -#define RSCAN0TMDF033HH (RSCAN0.TMDF033.UINT8[R_IO_HH]) -#define RSCAN0TMDF133 (RSCAN0.TMDF133.UINT32) -#define RSCAN0TMDF133L (RSCAN0.TMDF133.UINT16[R_IO_L]) -#define RSCAN0TMDF133LL (RSCAN0.TMDF133.UINT8[R_IO_LL]) -#define RSCAN0TMDF133LH (RSCAN0.TMDF133.UINT8[R_IO_LH]) -#define RSCAN0TMDF133H (RSCAN0.TMDF133.UINT16[R_IO_H]) -#define RSCAN0TMDF133HL (RSCAN0.TMDF133.UINT8[R_IO_HL]) -#define RSCAN0TMDF133HH (RSCAN0.TMDF133.UINT8[R_IO_HH]) -#define RSCAN0TMID34 (RSCAN0.TMID34.UINT32) -#define RSCAN0TMID34L (RSCAN0.TMID34.UINT16[R_IO_L]) -#define RSCAN0TMID34LL (RSCAN0.TMID34.UINT8[R_IO_LL]) -#define RSCAN0TMID34LH (RSCAN0.TMID34.UINT8[R_IO_LH]) -#define RSCAN0TMID34H (RSCAN0.TMID34.UINT16[R_IO_H]) -#define RSCAN0TMID34HL (RSCAN0.TMID34.UINT8[R_IO_HL]) -#define RSCAN0TMID34HH (RSCAN0.TMID34.UINT8[R_IO_HH]) -#define RSCAN0TMPTR34 (RSCAN0.TMPTR34.UINT32) -#define RSCAN0TMPTR34L (RSCAN0.TMPTR34.UINT16[R_IO_L]) -#define RSCAN0TMPTR34LL (RSCAN0.TMPTR34.UINT8[R_IO_LL]) -#define RSCAN0TMPTR34LH (RSCAN0.TMPTR34.UINT8[R_IO_LH]) -#define RSCAN0TMPTR34H (RSCAN0.TMPTR34.UINT16[R_IO_H]) -#define RSCAN0TMPTR34HL (RSCAN0.TMPTR34.UINT8[R_IO_HL]) -#define RSCAN0TMPTR34HH (RSCAN0.TMPTR34.UINT8[R_IO_HH]) -#define RSCAN0TMDF034 (RSCAN0.TMDF034.UINT32) -#define RSCAN0TMDF034L (RSCAN0.TMDF034.UINT16[R_IO_L]) -#define RSCAN0TMDF034LL (RSCAN0.TMDF034.UINT8[R_IO_LL]) -#define RSCAN0TMDF034LH (RSCAN0.TMDF034.UINT8[R_IO_LH]) -#define RSCAN0TMDF034H (RSCAN0.TMDF034.UINT16[R_IO_H]) -#define RSCAN0TMDF034HL (RSCAN0.TMDF034.UINT8[R_IO_HL]) -#define RSCAN0TMDF034HH (RSCAN0.TMDF034.UINT8[R_IO_HH]) -#define RSCAN0TMDF134 (RSCAN0.TMDF134.UINT32) -#define RSCAN0TMDF134L (RSCAN0.TMDF134.UINT16[R_IO_L]) -#define RSCAN0TMDF134LL (RSCAN0.TMDF134.UINT8[R_IO_LL]) -#define RSCAN0TMDF134LH (RSCAN0.TMDF134.UINT8[R_IO_LH]) -#define RSCAN0TMDF134H (RSCAN0.TMDF134.UINT16[R_IO_H]) -#define RSCAN0TMDF134HL (RSCAN0.TMDF134.UINT8[R_IO_HL]) -#define RSCAN0TMDF134HH (RSCAN0.TMDF134.UINT8[R_IO_HH]) -#define RSCAN0TMID35 (RSCAN0.TMID35.UINT32) -#define RSCAN0TMID35L (RSCAN0.TMID35.UINT16[R_IO_L]) -#define RSCAN0TMID35LL (RSCAN0.TMID35.UINT8[R_IO_LL]) -#define RSCAN0TMID35LH (RSCAN0.TMID35.UINT8[R_IO_LH]) -#define RSCAN0TMID35H (RSCAN0.TMID35.UINT16[R_IO_H]) -#define RSCAN0TMID35HL (RSCAN0.TMID35.UINT8[R_IO_HL]) -#define RSCAN0TMID35HH (RSCAN0.TMID35.UINT8[R_IO_HH]) -#define RSCAN0TMPTR35 (RSCAN0.TMPTR35.UINT32) -#define RSCAN0TMPTR35L (RSCAN0.TMPTR35.UINT16[R_IO_L]) -#define RSCAN0TMPTR35LL (RSCAN0.TMPTR35.UINT8[R_IO_LL]) -#define RSCAN0TMPTR35LH (RSCAN0.TMPTR35.UINT8[R_IO_LH]) -#define RSCAN0TMPTR35H (RSCAN0.TMPTR35.UINT16[R_IO_H]) -#define RSCAN0TMPTR35HL (RSCAN0.TMPTR35.UINT8[R_IO_HL]) -#define RSCAN0TMPTR35HH (RSCAN0.TMPTR35.UINT8[R_IO_HH]) -#define RSCAN0TMDF035 (RSCAN0.TMDF035.UINT32) -#define RSCAN0TMDF035L (RSCAN0.TMDF035.UINT16[R_IO_L]) -#define RSCAN0TMDF035LL (RSCAN0.TMDF035.UINT8[R_IO_LL]) -#define RSCAN0TMDF035LH (RSCAN0.TMDF035.UINT8[R_IO_LH]) -#define RSCAN0TMDF035H (RSCAN0.TMDF035.UINT16[R_IO_H]) -#define RSCAN0TMDF035HL (RSCAN0.TMDF035.UINT8[R_IO_HL]) -#define RSCAN0TMDF035HH (RSCAN0.TMDF035.UINT8[R_IO_HH]) -#define RSCAN0TMDF135 (RSCAN0.TMDF135.UINT32) -#define RSCAN0TMDF135L (RSCAN0.TMDF135.UINT16[R_IO_L]) -#define RSCAN0TMDF135LL (RSCAN0.TMDF135.UINT8[R_IO_LL]) -#define RSCAN0TMDF135LH (RSCAN0.TMDF135.UINT8[R_IO_LH]) -#define RSCAN0TMDF135H (RSCAN0.TMDF135.UINT16[R_IO_H]) -#define RSCAN0TMDF135HL (RSCAN0.TMDF135.UINT8[R_IO_HL]) -#define RSCAN0TMDF135HH (RSCAN0.TMDF135.UINT8[R_IO_HH]) -#define RSCAN0TMID36 (RSCAN0.TMID36.UINT32) -#define RSCAN0TMID36L (RSCAN0.TMID36.UINT16[R_IO_L]) -#define RSCAN0TMID36LL (RSCAN0.TMID36.UINT8[R_IO_LL]) -#define RSCAN0TMID36LH (RSCAN0.TMID36.UINT8[R_IO_LH]) -#define RSCAN0TMID36H (RSCAN0.TMID36.UINT16[R_IO_H]) -#define RSCAN0TMID36HL (RSCAN0.TMID36.UINT8[R_IO_HL]) -#define RSCAN0TMID36HH (RSCAN0.TMID36.UINT8[R_IO_HH]) -#define RSCAN0TMPTR36 (RSCAN0.TMPTR36.UINT32) -#define RSCAN0TMPTR36L (RSCAN0.TMPTR36.UINT16[R_IO_L]) -#define RSCAN0TMPTR36LL (RSCAN0.TMPTR36.UINT8[R_IO_LL]) -#define RSCAN0TMPTR36LH (RSCAN0.TMPTR36.UINT8[R_IO_LH]) -#define RSCAN0TMPTR36H (RSCAN0.TMPTR36.UINT16[R_IO_H]) -#define RSCAN0TMPTR36HL (RSCAN0.TMPTR36.UINT8[R_IO_HL]) -#define RSCAN0TMPTR36HH (RSCAN0.TMPTR36.UINT8[R_IO_HH]) -#define RSCAN0TMDF036 (RSCAN0.TMDF036.UINT32) -#define RSCAN0TMDF036L (RSCAN0.TMDF036.UINT16[R_IO_L]) -#define RSCAN0TMDF036LL (RSCAN0.TMDF036.UINT8[R_IO_LL]) -#define RSCAN0TMDF036LH (RSCAN0.TMDF036.UINT8[R_IO_LH]) -#define RSCAN0TMDF036H (RSCAN0.TMDF036.UINT16[R_IO_H]) -#define RSCAN0TMDF036HL (RSCAN0.TMDF036.UINT8[R_IO_HL]) -#define RSCAN0TMDF036HH (RSCAN0.TMDF036.UINT8[R_IO_HH]) -#define RSCAN0TMDF136 (RSCAN0.TMDF136.UINT32) -#define RSCAN0TMDF136L (RSCAN0.TMDF136.UINT16[R_IO_L]) -#define RSCAN0TMDF136LL (RSCAN0.TMDF136.UINT8[R_IO_LL]) -#define RSCAN0TMDF136LH (RSCAN0.TMDF136.UINT8[R_IO_LH]) -#define RSCAN0TMDF136H (RSCAN0.TMDF136.UINT16[R_IO_H]) -#define RSCAN0TMDF136HL (RSCAN0.TMDF136.UINT8[R_IO_HL]) -#define RSCAN0TMDF136HH (RSCAN0.TMDF136.UINT8[R_IO_HH]) -#define RSCAN0TMID37 (RSCAN0.TMID37.UINT32) -#define RSCAN0TMID37L (RSCAN0.TMID37.UINT16[R_IO_L]) -#define RSCAN0TMID37LL (RSCAN0.TMID37.UINT8[R_IO_LL]) -#define RSCAN0TMID37LH (RSCAN0.TMID37.UINT8[R_IO_LH]) -#define RSCAN0TMID37H (RSCAN0.TMID37.UINT16[R_IO_H]) -#define RSCAN0TMID37HL (RSCAN0.TMID37.UINT8[R_IO_HL]) -#define RSCAN0TMID37HH (RSCAN0.TMID37.UINT8[R_IO_HH]) -#define RSCAN0TMPTR37 (RSCAN0.TMPTR37.UINT32) -#define RSCAN0TMPTR37L (RSCAN0.TMPTR37.UINT16[R_IO_L]) -#define RSCAN0TMPTR37LL (RSCAN0.TMPTR37.UINT8[R_IO_LL]) -#define RSCAN0TMPTR37LH (RSCAN0.TMPTR37.UINT8[R_IO_LH]) -#define RSCAN0TMPTR37H (RSCAN0.TMPTR37.UINT16[R_IO_H]) -#define RSCAN0TMPTR37HL (RSCAN0.TMPTR37.UINT8[R_IO_HL]) -#define RSCAN0TMPTR37HH (RSCAN0.TMPTR37.UINT8[R_IO_HH]) -#define RSCAN0TMDF037 (RSCAN0.TMDF037.UINT32) -#define RSCAN0TMDF037L (RSCAN0.TMDF037.UINT16[R_IO_L]) -#define RSCAN0TMDF037LL (RSCAN0.TMDF037.UINT8[R_IO_LL]) -#define RSCAN0TMDF037LH (RSCAN0.TMDF037.UINT8[R_IO_LH]) -#define RSCAN0TMDF037H (RSCAN0.TMDF037.UINT16[R_IO_H]) -#define RSCAN0TMDF037HL (RSCAN0.TMDF037.UINT8[R_IO_HL]) -#define RSCAN0TMDF037HH (RSCAN0.TMDF037.UINT8[R_IO_HH]) -#define RSCAN0TMDF137 (RSCAN0.TMDF137.UINT32) -#define RSCAN0TMDF137L (RSCAN0.TMDF137.UINT16[R_IO_L]) -#define RSCAN0TMDF137LL (RSCAN0.TMDF137.UINT8[R_IO_LL]) -#define RSCAN0TMDF137LH (RSCAN0.TMDF137.UINT8[R_IO_LH]) -#define RSCAN0TMDF137H (RSCAN0.TMDF137.UINT16[R_IO_H]) -#define RSCAN0TMDF137HL (RSCAN0.TMDF137.UINT8[R_IO_HL]) -#define RSCAN0TMDF137HH (RSCAN0.TMDF137.UINT8[R_IO_HH]) -#define RSCAN0TMID38 (RSCAN0.TMID38.UINT32) -#define RSCAN0TMID38L (RSCAN0.TMID38.UINT16[R_IO_L]) -#define RSCAN0TMID38LL (RSCAN0.TMID38.UINT8[R_IO_LL]) -#define RSCAN0TMID38LH (RSCAN0.TMID38.UINT8[R_IO_LH]) -#define RSCAN0TMID38H (RSCAN0.TMID38.UINT16[R_IO_H]) -#define RSCAN0TMID38HL (RSCAN0.TMID38.UINT8[R_IO_HL]) -#define RSCAN0TMID38HH (RSCAN0.TMID38.UINT8[R_IO_HH]) -#define RSCAN0TMPTR38 (RSCAN0.TMPTR38.UINT32) -#define RSCAN0TMPTR38L (RSCAN0.TMPTR38.UINT16[R_IO_L]) -#define RSCAN0TMPTR38LL (RSCAN0.TMPTR38.UINT8[R_IO_LL]) -#define RSCAN0TMPTR38LH (RSCAN0.TMPTR38.UINT8[R_IO_LH]) -#define RSCAN0TMPTR38H (RSCAN0.TMPTR38.UINT16[R_IO_H]) -#define RSCAN0TMPTR38HL (RSCAN0.TMPTR38.UINT8[R_IO_HL]) -#define RSCAN0TMPTR38HH (RSCAN0.TMPTR38.UINT8[R_IO_HH]) -#define RSCAN0TMDF038 (RSCAN0.TMDF038.UINT32) -#define RSCAN0TMDF038L (RSCAN0.TMDF038.UINT16[R_IO_L]) -#define RSCAN0TMDF038LL (RSCAN0.TMDF038.UINT8[R_IO_LL]) -#define RSCAN0TMDF038LH (RSCAN0.TMDF038.UINT8[R_IO_LH]) -#define RSCAN0TMDF038H (RSCAN0.TMDF038.UINT16[R_IO_H]) -#define RSCAN0TMDF038HL (RSCAN0.TMDF038.UINT8[R_IO_HL]) -#define RSCAN0TMDF038HH (RSCAN0.TMDF038.UINT8[R_IO_HH]) -#define RSCAN0TMDF138 (RSCAN0.TMDF138.UINT32) -#define RSCAN0TMDF138L (RSCAN0.TMDF138.UINT16[R_IO_L]) -#define RSCAN0TMDF138LL (RSCAN0.TMDF138.UINT8[R_IO_LL]) -#define RSCAN0TMDF138LH (RSCAN0.TMDF138.UINT8[R_IO_LH]) -#define RSCAN0TMDF138H (RSCAN0.TMDF138.UINT16[R_IO_H]) -#define RSCAN0TMDF138HL (RSCAN0.TMDF138.UINT8[R_IO_HL]) -#define RSCAN0TMDF138HH (RSCAN0.TMDF138.UINT8[R_IO_HH]) -#define RSCAN0TMID39 (RSCAN0.TMID39.UINT32) -#define RSCAN0TMID39L (RSCAN0.TMID39.UINT16[R_IO_L]) -#define RSCAN0TMID39LL (RSCAN0.TMID39.UINT8[R_IO_LL]) -#define RSCAN0TMID39LH (RSCAN0.TMID39.UINT8[R_IO_LH]) -#define RSCAN0TMID39H (RSCAN0.TMID39.UINT16[R_IO_H]) -#define RSCAN0TMID39HL (RSCAN0.TMID39.UINT8[R_IO_HL]) -#define RSCAN0TMID39HH (RSCAN0.TMID39.UINT8[R_IO_HH]) -#define RSCAN0TMPTR39 (RSCAN0.TMPTR39.UINT32) -#define RSCAN0TMPTR39L (RSCAN0.TMPTR39.UINT16[R_IO_L]) -#define RSCAN0TMPTR39LL (RSCAN0.TMPTR39.UINT8[R_IO_LL]) -#define RSCAN0TMPTR39LH (RSCAN0.TMPTR39.UINT8[R_IO_LH]) -#define RSCAN0TMPTR39H (RSCAN0.TMPTR39.UINT16[R_IO_H]) -#define RSCAN0TMPTR39HL (RSCAN0.TMPTR39.UINT8[R_IO_HL]) -#define RSCAN0TMPTR39HH (RSCAN0.TMPTR39.UINT8[R_IO_HH]) -#define RSCAN0TMDF039 (RSCAN0.TMDF039.UINT32) -#define RSCAN0TMDF039L (RSCAN0.TMDF039.UINT16[R_IO_L]) -#define RSCAN0TMDF039LL (RSCAN0.TMDF039.UINT8[R_IO_LL]) -#define RSCAN0TMDF039LH (RSCAN0.TMDF039.UINT8[R_IO_LH]) -#define RSCAN0TMDF039H (RSCAN0.TMDF039.UINT16[R_IO_H]) -#define RSCAN0TMDF039HL (RSCAN0.TMDF039.UINT8[R_IO_HL]) -#define RSCAN0TMDF039HH (RSCAN0.TMDF039.UINT8[R_IO_HH]) -#define RSCAN0TMDF139 (RSCAN0.TMDF139.UINT32) -#define RSCAN0TMDF139L (RSCAN0.TMDF139.UINT16[R_IO_L]) -#define RSCAN0TMDF139LL (RSCAN0.TMDF139.UINT8[R_IO_LL]) -#define RSCAN0TMDF139LH (RSCAN0.TMDF139.UINT8[R_IO_LH]) -#define RSCAN0TMDF139H (RSCAN0.TMDF139.UINT16[R_IO_H]) -#define RSCAN0TMDF139HL (RSCAN0.TMDF139.UINT8[R_IO_HL]) -#define RSCAN0TMDF139HH (RSCAN0.TMDF139.UINT8[R_IO_HH]) -#define RSCAN0TMID40 (RSCAN0.TMID40.UINT32) -#define RSCAN0TMID40L (RSCAN0.TMID40.UINT16[R_IO_L]) -#define RSCAN0TMID40LL (RSCAN0.TMID40.UINT8[R_IO_LL]) -#define RSCAN0TMID40LH (RSCAN0.TMID40.UINT8[R_IO_LH]) -#define RSCAN0TMID40H (RSCAN0.TMID40.UINT16[R_IO_H]) -#define RSCAN0TMID40HL (RSCAN0.TMID40.UINT8[R_IO_HL]) -#define RSCAN0TMID40HH (RSCAN0.TMID40.UINT8[R_IO_HH]) -#define RSCAN0TMPTR40 (RSCAN0.TMPTR40.UINT32) -#define RSCAN0TMPTR40L (RSCAN0.TMPTR40.UINT16[R_IO_L]) -#define RSCAN0TMPTR40LL (RSCAN0.TMPTR40.UINT8[R_IO_LL]) -#define RSCAN0TMPTR40LH (RSCAN0.TMPTR40.UINT8[R_IO_LH]) -#define RSCAN0TMPTR40H (RSCAN0.TMPTR40.UINT16[R_IO_H]) -#define RSCAN0TMPTR40HL (RSCAN0.TMPTR40.UINT8[R_IO_HL]) -#define RSCAN0TMPTR40HH (RSCAN0.TMPTR40.UINT8[R_IO_HH]) -#define RSCAN0TMDF040 (RSCAN0.TMDF040.UINT32) -#define RSCAN0TMDF040L (RSCAN0.TMDF040.UINT16[R_IO_L]) -#define RSCAN0TMDF040LL (RSCAN0.TMDF040.UINT8[R_IO_LL]) -#define RSCAN0TMDF040LH (RSCAN0.TMDF040.UINT8[R_IO_LH]) -#define RSCAN0TMDF040H (RSCAN0.TMDF040.UINT16[R_IO_H]) -#define RSCAN0TMDF040HL (RSCAN0.TMDF040.UINT8[R_IO_HL]) -#define RSCAN0TMDF040HH (RSCAN0.TMDF040.UINT8[R_IO_HH]) -#define RSCAN0TMDF140 (RSCAN0.TMDF140.UINT32) -#define RSCAN0TMDF140L (RSCAN0.TMDF140.UINT16[R_IO_L]) -#define RSCAN0TMDF140LL (RSCAN0.TMDF140.UINT8[R_IO_LL]) -#define RSCAN0TMDF140LH (RSCAN0.TMDF140.UINT8[R_IO_LH]) -#define RSCAN0TMDF140H (RSCAN0.TMDF140.UINT16[R_IO_H]) -#define RSCAN0TMDF140HL (RSCAN0.TMDF140.UINT8[R_IO_HL]) -#define RSCAN0TMDF140HH (RSCAN0.TMDF140.UINT8[R_IO_HH]) -#define RSCAN0TMID41 (RSCAN0.TMID41.UINT32) -#define RSCAN0TMID41L (RSCAN0.TMID41.UINT16[R_IO_L]) -#define RSCAN0TMID41LL (RSCAN0.TMID41.UINT8[R_IO_LL]) -#define RSCAN0TMID41LH (RSCAN0.TMID41.UINT8[R_IO_LH]) -#define RSCAN0TMID41H (RSCAN0.TMID41.UINT16[R_IO_H]) -#define RSCAN0TMID41HL (RSCAN0.TMID41.UINT8[R_IO_HL]) -#define RSCAN0TMID41HH (RSCAN0.TMID41.UINT8[R_IO_HH]) -#define RSCAN0TMPTR41 (RSCAN0.TMPTR41.UINT32) -#define RSCAN0TMPTR41L (RSCAN0.TMPTR41.UINT16[R_IO_L]) -#define RSCAN0TMPTR41LL (RSCAN0.TMPTR41.UINT8[R_IO_LL]) -#define RSCAN0TMPTR41LH (RSCAN0.TMPTR41.UINT8[R_IO_LH]) -#define RSCAN0TMPTR41H (RSCAN0.TMPTR41.UINT16[R_IO_H]) -#define RSCAN0TMPTR41HL (RSCAN0.TMPTR41.UINT8[R_IO_HL]) -#define RSCAN0TMPTR41HH (RSCAN0.TMPTR41.UINT8[R_IO_HH]) -#define RSCAN0TMDF041 (RSCAN0.TMDF041.UINT32) -#define RSCAN0TMDF041L (RSCAN0.TMDF041.UINT16[R_IO_L]) -#define RSCAN0TMDF041LL (RSCAN0.TMDF041.UINT8[R_IO_LL]) -#define RSCAN0TMDF041LH (RSCAN0.TMDF041.UINT8[R_IO_LH]) -#define RSCAN0TMDF041H (RSCAN0.TMDF041.UINT16[R_IO_H]) -#define RSCAN0TMDF041HL (RSCAN0.TMDF041.UINT8[R_IO_HL]) -#define RSCAN0TMDF041HH (RSCAN0.TMDF041.UINT8[R_IO_HH]) -#define RSCAN0TMDF141 (RSCAN0.TMDF141.UINT32) -#define RSCAN0TMDF141L (RSCAN0.TMDF141.UINT16[R_IO_L]) -#define RSCAN0TMDF141LL (RSCAN0.TMDF141.UINT8[R_IO_LL]) -#define RSCAN0TMDF141LH (RSCAN0.TMDF141.UINT8[R_IO_LH]) -#define RSCAN0TMDF141H (RSCAN0.TMDF141.UINT16[R_IO_H]) -#define RSCAN0TMDF141HL (RSCAN0.TMDF141.UINT8[R_IO_HL]) -#define RSCAN0TMDF141HH (RSCAN0.TMDF141.UINT8[R_IO_HH]) -#define RSCAN0TMID42 (RSCAN0.TMID42.UINT32) -#define RSCAN0TMID42L (RSCAN0.TMID42.UINT16[R_IO_L]) -#define RSCAN0TMID42LL (RSCAN0.TMID42.UINT8[R_IO_LL]) -#define RSCAN0TMID42LH (RSCAN0.TMID42.UINT8[R_IO_LH]) -#define RSCAN0TMID42H (RSCAN0.TMID42.UINT16[R_IO_H]) -#define RSCAN0TMID42HL (RSCAN0.TMID42.UINT8[R_IO_HL]) -#define RSCAN0TMID42HH (RSCAN0.TMID42.UINT8[R_IO_HH]) -#define RSCAN0TMPTR42 (RSCAN0.TMPTR42.UINT32) -#define RSCAN0TMPTR42L (RSCAN0.TMPTR42.UINT16[R_IO_L]) -#define RSCAN0TMPTR42LL (RSCAN0.TMPTR42.UINT8[R_IO_LL]) -#define RSCAN0TMPTR42LH (RSCAN0.TMPTR42.UINT8[R_IO_LH]) -#define RSCAN0TMPTR42H (RSCAN0.TMPTR42.UINT16[R_IO_H]) -#define RSCAN0TMPTR42HL (RSCAN0.TMPTR42.UINT8[R_IO_HL]) -#define RSCAN0TMPTR42HH (RSCAN0.TMPTR42.UINT8[R_IO_HH]) -#define RSCAN0TMDF042 (RSCAN0.TMDF042.UINT32) -#define RSCAN0TMDF042L (RSCAN0.TMDF042.UINT16[R_IO_L]) -#define RSCAN0TMDF042LL (RSCAN0.TMDF042.UINT8[R_IO_LL]) -#define RSCAN0TMDF042LH (RSCAN0.TMDF042.UINT8[R_IO_LH]) -#define RSCAN0TMDF042H (RSCAN0.TMDF042.UINT16[R_IO_H]) -#define RSCAN0TMDF042HL (RSCAN0.TMDF042.UINT8[R_IO_HL]) -#define RSCAN0TMDF042HH (RSCAN0.TMDF042.UINT8[R_IO_HH]) -#define RSCAN0TMDF142 (RSCAN0.TMDF142.UINT32) -#define RSCAN0TMDF142L (RSCAN0.TMDF142.UINT16[R_IO_L]) -#define RSCAN0TMDF142LL (RSCAN0.TMDF142.UINT8[R_IO_LL]) -#define RSCAN0TMDF142LH (RSCAN0.TMDF142.UINT8[R_IO_LH]) -#define RSCAN0TMDF142H (RSCAN0.TMDF142.UINT16[R_IO_H]) -#define RSCAN0TMDF142HL (RSCAN0.TMDF142.UINT8[R_IO_HL]) -#define RSCAN0TMDF142HH (RSCAN0.TMDF142.UINT8[R_IO_HH]) -#define RSCAN0TMID43 (RSCAN0.TMID43.UINT32) -#define RSCAN0TMID43L (RSCAN0.TMID43.UINT16[R_IO_L]) -#define RSCAN0TMID43LL (RSCAN0.TMID43.UINT8[R_IO_LL]) -#define RSCAN0TMID43LH (RSCAN0.TMID43.UINT8[R_IO_LH]) -#define RSCAN0TMID43H (RSCAN0.TMID43.UINT16[R_IO_H]) -#define RSCAN0TMID43HL (RSCAN0.TMID43.UINT8[R_IO_HL]) -#define RSCAN0TMID43HH (RSCAN0.TMID43.UINT8[R_IO_HH]) -#define RSCAN0TMPTR43 (RSCAN0.TMPTR43.UINT32) -#define RSCAN0TMPTR43L (RSCAN0.TMPTR43.UINT16[R_IO_L]) -#define RSCAN0TMPTR43LL (RSCAN0.TMPTR43.UINT8[R_IO_LL]) -#define RSCAN0TMPTR43LH (RSCAN0.TMPTR43.UINT8[R_IO_LH]) -#define RSCAN0TMPTR43H (RSCAN0.TMPTR43.UINT16[R_IO_H]) -#define RSCAN0TMPTR43HL (RSCAN0.TMPTR43.UINT8[R_IO_HL]) -#define RSCAN0TMPTR43HH (RSCAN0.TMPTR43.UINT8[R_IO_HH]) -#define RSCAN0TMDF043 (RSCAN0.TMDF043.UINT32) -#define RSCAN0TMDF043L (RSCAN0.TMDF043.UINT16[R_IO_L]) -#define RSCAN0TMDF043LL (RSCAN0.TMDF043.UINT8[R_IO_LL]) -#define RSCAN0TMDF043LH (RSCAN0.TMDF043.UINT8[R_IO_LH]) -#define RSCAN0TMDF043H (RSCAN0.TMDF043.UINT16[R_IO_H]) -#define RSCAN0TMDF043HL (RSCAN0.TMDF043.UINT8[R_IO_HL]) -#define RSCAN0TMDF043HH (RSCAN0.TMDF043.UINT8[R_IO_HH]) -#define RSCAN0TMDF143 (RSCAN0.TMDF143.UINT32) -#define RSCAN0TMDF143L (RSCAN0.TMDF143.UINT16[R_IO_L]) -#define RSCAN0TMDF143LL (RSCAN0.TMDF143.UINT8[R_IO_LL]) -#define RSCAN0TMDF143LH (RSCAN0.TMDF143.UINT8[R_IO_LH]) -#define RSCAN0TMDF143H (RSCAN0.TMDF143.UINT16[R_IO_H]) -#define RSCAN0TMDF143HL (RSCAN0.TMDF143.UINT8[R_IO_HL]) -#define RSCAN0TMDF143HH (RSCAN0.TMDF143.UINT8[R_IO_HH]) -#define RSCAN0TMID44 (RSCAN0.TMID44.UINT32) -#define RSCAN0TMID44L (RSCAN0.TMID44.UINT16[R_IO_L]) -#define RSCAN0TMID44LL (RSCAN0.TMID44.UINT8[R_IO_LL]) -#define RSCAN0TMID44LH (RSCAN0.TMID44.UINT8[R_IO_LH]) -#define RSCAN0TMID44H (RSCAN0.TMID44.UINT16[R_IO_H]) -#define RSCAN0TMID44HL (RSCAN0.TMID44.UINT8[R_IO_HL]) -#define RSCAN0TMID44HH (RSCAN0.TMID44.UINT8[R_IO_HH]) -#define RSCAN0TMPTR44 (RSCAN0.TMPTR44.UINT32) -#define RSCAN0TMPTR44L (RSCAN0.TMPTR44.UINT16[R_IO_L]) -#define RSCAN0TMPTR44LL (RSCAN0.TMPTR44.UINT8[R_IO_LL]) -#define RSCAN0TMPTR44LH (RSCAN0.TMPTR44.UINT8[R_IO_LH]) -#define RSCAN0TMPTR44H (RSCAN0.TMPTR44.UINT16[R_IO_H]) -#define RSCAN0TMPTR44HL (RSCAN0.TMPTR44.UINT8[R_IO_HL]) -#define RSCAN0TMPTR44HH (RSCAN0.TMPTR44.UINT8[R_IO_HH]) -#define RSCAN0TMDF044 (RSCAN0.TMDF044.UINT32) -#define RSCAN0TMDF044L (RSCAN0.TMDF044.UINT16[R_IO_L]) -#define RSCAN0TMDF044LL (RSCAN0.TMDF044.UINT8[R_IO_LL]) -#define RSCAN0TMDF044LH (RSCAN0.TMDF044.UINT8[R_IO_LH]) -#define RSCAN0TMDF044H (RSCAN0.TMDF044.UINT16[R_IO_H]) -#define RSCAN0TMDF044HL (RSCAN0.TMDF044.UINT8[R_IO_HL]) -#define RSCAN0TMDF044HH (RSCAN0.TMDF044.UINT8[R_IO_HH]) -#define RSCAN0TMDF144 (RSCAN0.TMDF144.UINT32) -#define RSCAN0TMDF144L (RSCAN0.TMDF144.UINT16[R_IO_L]) -#define RSCAN0TMDF144LL (RSCAN0.TMDF144.UINT8[R_IO_LL]) -#define RSCAN0TMDF144LH (RSCAN0.TMDF144.UINT8[R_IO_LH]) -#define RSCAN0TMDF144H (RSCAN0.TMDF144.UINT16[R_IO_H]) -#define RSCAN0TMDF144HL (RSCAN0.TMDF144.UINT8[R_IO_HL]) -#define RSCAN0TMDF144HH (RSCAN0.TMDF144.UINT8[R_IO_HH]) -#define RSCAN0TMID45 (RSCAN0.TMID45.UINT32) -#define RSCAN0TMID45L (RSCAN0.TMID45.UINT16[R_IO_L]) -#define RSCAN0TMID45LL (RSCAN0.TMID45.UINT8[R_IO_LL]) -#define RSCAN0TMID45LH (RSCAN0.TMID45.UINT8[R_IO_LH]) -#define RSCAN0TMID45H (RSCAN0.TMID45.UINT16[R_IO_H]) -#define RSCAN0TMID45HL (RSCAN0.TMID45.UINT8[R_IO_HL]) -#define RSCAN0TMID45HH (RSCAN0.TMID45.UINT8[R_IO_HH]) -#define RSCAN0TMPTR45 (RSCAN0.TMPTR45.UINT32) -#define RSCAN0TMPTR45L (RSCAN0.TMPTR45.UINT16[R_IO_L]) -#define RSCAN0TMPTR45LL (RSCAN0.TMPTR45.UINT8[R_IO_LL]) -#define RSCAN0TMPTR45LH (RSCAN0.TMPTR45.UINT8[R_IO_LH]) -#define RSCAN0TMPTR45H (RSCAN0.TMPTR45.UINT16[R_IO_H]) -#define RSCAN0TMPTR45HL (RSCAN0.TMPTR45.UINT8[R_IO_HL]) -#define RSCAN0TMPTR45HH (RSCAN0.TMPTR45.UINT8[R_IO_HH]) -#define RSCAN0TMDF045 (RSCAN0.TMDF045.UINT32) -#define RSCAN0TMDF045L (RSCAN0.TMDF045.UINT16[R_IO_L]) -#define RSCAN0TMDF045LL (RSCAN0.TMDF045.UINT8[R_IO_LL]) -#define RSCAN0TMDF045LH (RSCAN0.TMDF045.UINT8[R_IO_LH]) -#define RSCAN0TMDF045H (RSCAN0.TMDF045.UINT16[R_IO_H]) -#define RSCAN0TMDF045HL (RSCAN0.TMDF045.UINT8[R_IO_HL]) -#define RSCAN0TMDF045HH (RSCAN0.TMDF045.UINT8[R_IO_HH]) -#define RSCAN0TMDF145 (RSCAN0.TMDF145.UINT32) -#define RSCAN0TMDF145L (RSCAN0.TMDF145.UINT16[R_IO_L]) -#define RSCAN0TMDF145LL (RSCAN0.TMDF145.UINT8[R_IO_LL]) -#define RSCAN0TMDF145LH (RSCAN0.TMDF145.UINT8[R_IO_LH]) -#define RSCAN0TMDF145H (RSCAN0.TMDF145.UINT16[R_IO_H]) -#define RSCAN0TMDF145HL (RSCAN0.TMDF145.UINT8[R_IO_HL]) -#define RSCAN0TMDF145HH (RSCAN0.TMDF145.UINT8[R_IO_HH]) -#define RSCAN0TMID46 (RSCAN0.TMID46.UINT32) -#define RSCAN0TMID46L (RSCAN0.TMID46.UINT16[R_IO_L]) -#define RSCAN0TMID46LL (RSCAN0.TMID46.UINT8[R_IO_LL]) -#define RSCAN0TMID46LH (RSCAN0.TMID46.UINT8[R_IO_LH]) -#define RSCAN0TMID46H (RSCAN0.TMID46.UINT16[R_IO_H]) -#define RSCAN0TMID46HL (RSCAN0.TMID46.UINT8[R_IO_HL]) -#define RSCAN0TMID46HH (RSCAN0.TMID46.UINT8[R_IO_HH]) -#define RSCAN0TMPTR46 (RSCAN0.TMPTR46.UINT32) -#define RSCAN0TMPTR46L (RSCAN0.TMPTR46.UINT16[R_IO_L]) -#define RSCAN0TMPTR46LL (RSCAN0.TMPTR46.UINT8[R_IO_LL]) -#define RSCAN0TMPTR46LH (RSCAN0.TMPTR46.UINT8[R_IO_LH]) -#define RSCAN0TMPTR46H (RSCAN0.TMPTR46.UINT16[R_IO_H]) -#define RSCAN0TMPTR46HL (RSCAN0.TMPTR46.UINT8[R_IO_HL]) -#define RSCAN0TMPTR46HH (RSCAN0.TMPTR46.UINT8[R_IO_HH]) -#define RSCAN0TMDF046 (RSCAN0.TMDF046.UINT32) -#define RSCAN0TMDF046L (RSCAN0.TMDF046.UINT16[R_IO_L]) -#define RSCAN0TMDF046LL (RSCAN0.TMDF046.UINT8[R_IO_LL]) -#define RSCAN0TMDF046LH (RSCAN0.TMDF046.UINT8[R_IO_LH]) -#define RSCAN0TMDF046H (RSCAN0.TMDF046.UINT16[R_IO_H]) -#define RSCAN0TMDF046HL (RSCAN0.TMDF046.UINT8[R_IO_HL]) -#define RSCAN0TMDF046HH (RSCAN0.TMDF046.UINT8[R_IO_HH]) -#define RSCAN0TMDF146 (RSCAN0.TMDF146.UINT32) -#define RSCAN0TMDF146L (RSCAN0.TMDF146.UINT16[R_IO_L]) -#define RSCAN0TMDF146LL (RSCAN0.TMDF146.UINT8[R_IO_LL]) -#define RSCAN0TMDF146LH (RSCAN0.TMDF146.UINT8[R_IO_LH]) -#define RSCAN0TMDF146H (RSCAN0.TMDF146.UINT16[R_IO_H]) -#define RSCAN0TMDF146HL (RSCAN0.TMDF146.UINT8[R_IO_HL]) -#define RSCAN0TMDF146HH (RSCAN0.TMDF146.UINT8[R_IO_HH]) -#define RSCAN0TMID47 (RSCAN0.TMID47.UINT32) -#define RSCAN0TMID47L (RSCAN0.TMID47.UINT16[R_IO_L]) -#define RSCAN0TMID47LL (RSCAN0.TMID47.UINT8[R_IO_LL]) -#define RSCAN0TMID47LH (RSCAN0.TMID47.UINT8[R_IO_LH]) -#define RSCAN0TMID47H (RSCAN0.TMID47.UINT16[R_IO_H]) -#define RSCAN0TMID47HL (RSCAN0.TMID47.UINT8[R_IO_HL]) -#define RSCAN0TMID47HH (RSCAN0.TMID47.UINT8[R_IO_HH]) -#define RSCAN0TMPTR47 (RSCAN0.TMPTR47.UINT32) -#define RSCAN0TMPTR47L (RSCAN0.TMPTR47.UINT16[R_IO_L]) -#define RSCAN0TMPTR47LL (RSCAN0.TMPTR47.UINT8[R_IO_LL]) -#define RSCAN0TMPTR47LH (RSCAN0.TMPTR47.UINT8[R_IO_LH]) -#define RSCAN0TMPTR47H (RSCAN0.TMPTR47.UINT16[R_IO_H]) -#define RSCAN0TMPTR47HL (RSCAN0.TMPTR47.UINT8[R_IO_HL]) -#define RSCAN0TMPTR47HH (RSCAN0.TMPTR47.UINT8[R_IO_HH]) -#define RSCAN0TMDF047 (RSCAN0.TMDF047.UINT32) -#define RSCAN0TMDF047L (RSCAN0.TMDF047.UINT16[R_IO_L]) -#define RSCAN0TMDF047LL (RSCAN0.TMDF047.UINT8[R_IO_LL]) -#define RSCAN0TMDF047LH (RSCAN0.TMDF047.UINT8[R_IO_LH]) -#define RSCAN0TMDF047H (RSCAN0.TMDF047.UINT16[R_IO_H]) -#define RSCAN0TMDF047HL (RSCAN0.TMDF047.UINT8[R_IO_HL]) -#define RSCAN0TMDF047HH (RSCAN0.TMDF047.UINT8[R_IO_HH]) -#define RSCAN0TMDF147 (RSCAN0.TMDF147.UINT32) -#define RSCAN0TMDF147L (RSCAN0.TMDF147.UINT16[R_IO_L]) -#define RSCAN0TMDF147LL (RSCAN0.TMDF147.UINT8[R_IO_LL]) -#define RSCAN0TMDF147LH (RSCAN0.TMDF147.UINT8[R_IO_LH]) -#define RSCAN0TMDF147H (RSCAN0.TMDF147.UINT16[R_IO_H]) -#define RSCAN0TMDF147HL (RSCAN0.TMDF147.UINT8[R_IO_HL]) -#define RSCAN0TMDF147HH (RSCAN0.TMDF147.UINT8[R_IO_HH]) -#define RSCAN0TMID48 (RSCAN0.TMID48.UINT32) -#define RSCAN0TMID48L (RSCAN0.TMID48.UINT16[R_IO_L]) -#define RSCAN0TMID48LL (RSCAN0.TMID48.UINT8[R_IO_LL]) -#define RSCAN0TMID48LH (RSCAN0.TMID48.UINT8[R_IO_LH]) -#define RSCAN0TMID48H (RSCAN0.TMID48.UINT16[R_IO_H]) -#define RSCAN0TMID48HL (RSCAN0.TMID48.UINT8[R_IO_HL]) -#define RSCAN0TMID48HH (RSCAN0.TMID48.UINT8[R_IO_HH]) -#define RSCAN0TMPTR48 (RSCAN0.TMPTR48.UINT32) -#define RSCAN0TMPTR48L (RSCAN0.TMPTR48.UINT16[R_IO_L]) -#define RSCAN0TMPTR48LL (RSCAN0.TMPTR48.UINT8[R_IO_LL]) -#define RSCAN0TMPTR48LH (RSCAN0.TMPTR48.UINT8[R_IO_LH]) -#define RSCAN0TMPTR48H (RSCAN0.TMPTR48.UINT16[R_IO_H]) -#define RSCAN0TMPTR48HL (RSCAN0.TMPTR48.UINT8[R_IO_HL]) -#define RSCAN0TMPTR48HH (RSCAN0.TMPTR48.UINT8[R_IO_HH]) -#define RSCAN0TMDF048 (RSCAN0.TMDF048.UINT32) -#define RSCAN0TMDF048L (RSCAN0.TMDF048.UINT16[R_IO_L]) -#define RSCAN0TMDF048LL (RSCAN0.TMDF048.UINT8[R_IO_LL]) -#define RSCAN0TMDF048LH (RSCAN0.TMDF048.UINT8[R_IO_LH]) -#define RSCAN0TMDF048H (RSCAN0.TMDF048.UINT16[R_IO_H]) -#define RSCAN0TMDF048HL (RSCAN0.TMDF048.UINT8[R_IO_HL]) -#define RSCAN0TMDF048HH (RSCAN0.TMDF048.UINT8[R_IO_HH]) -#define RSCAN0TMDF148 (RSCAN0.TMDF148.UINT32) -#define RSCAN0TMDF148L (RSCAN0.TMDF148.UINT16[R_IO_L]) -#define RSCAN0TMDF148LL (RSCAN0.TMDF148.UINT8[R_IO_LL]) -#define RSCAN0TMDF148LH (RSCAN0.TMDF148.UINT8[R_IO_LH]) -#define RSCAN0TMDF148H (RSCAN0.TMDF148.UINT16[R_IO_H]) -#define RSCAN0TMDF148HL (RSCAN0.TMDF148.UINT8[R_IO_HL]) -#define RSCAN0TMDF148HH (RSCAN0.TMDF148.UINT8[R_IO_HH]) -#define RSCAN0TMID49 (RSCAN0.TMID49.UINT32) -#define RSCAN0TMID49L (RSCAN0.TMID49.UINT16[R_IO_L]) -#define RSCAN0TMID49LL (RSCAN0.TMID49.UINT8[R_IO_LL]) -#define RSCAN0TMID49LH (RSCAN0.TMID49.UINT8[R_IO_LH]) -#define RSCAN0TMID49H (RSCAN0.TMID49.UINT16[R_IO_H]) -#define RSCAN0TMID49HL (RSCAN0.TMID49.UINT8[R_IO_HL]) -#define RSCAN0TMID49HH (RSCAN0.TMID49.UINT8[R_IO_HH]) -#define RSCAN0TMPTR49 (RSCAN0.TMPTR49.UINT32) -#define RSCAN0TMPTR49L (RSCAN0.TMPTR49.UINT16[R_IO_L]) -#define RSCAN0TMPTR49LL (RSCAN0.TMPTR49.UINT8[R_IO_LL]) -#define RSCAN0TMPTR49LH (RSCAN0.TMPTR49.UINT8[R_IO_LH]) -#define RSCAN0TMPTR49H (RSCAN0.TMPTR49.UINT16[R_IO_H]) -#define RSCAN0TMPTR49HL (RSCAN0.TMPTR49.UINT8[R_IO_HL]) -#define RSCAN0TMPTR49HH (RSCAN0.TMPTR49.UINT8[R_IO_HH]) -#define RSCAN0TMDF049 (RSCAN0.TMDF049.UINT32) -#define RSCAN0TMDF049L (RSCAN0.TMDF049.UINT16[R_IO_L]) -#define RSCAN0TMDF049LL (RSCAN0.TMDF049.UINT8[R_IO_LL]) -#define RSCAN0TMDF049LH (RSCAN0.TMDF049.UINT8[R_IO_LH]) -#define RSCAN0TMDF049H (RSCAN0.TMDF049.UINT16[R_IO_H]) -#define RSCAN0TMDF049HL (RSCAN0.TMDF049.UINT8[R_IO_HL]) -#define RSCAN0TMDF049HH (RSCAN0.TMDF049.UINT8[R_IO_HH]) -#define RSCAN0TMDF149 (RSCAN0.TMDF149.UINT32) -#define RSCAN0TMDF149L (RSCAN0.TMDF149.UINT16[R_IO_L]) -#define RSCAN0TMDF149LL (RSCAN0.TMDF149.UINT8[R_IO_LL]) -#define RSCAN0TMDF149LH (RSCAN0.TMDF149.UINT8[R_IO_LH]) -#define RSCAN0TMDF149H (RSCAN0.TMDF149.UINT16[R_IO_H]) -#define RSCAN0TMDF149HL (RSCAN0.TMDF149.UINT8[R_IO_HL]) -#define RSCAN0TMDF149HH (RSCAN0.TMDF149.UINT8[R_IO_HH]) -#define RSCAN0TMID50 (RSCAN0.TMID50.UINT32) -#define RSCAN0TMID50L (RSCAN0.TMID50.UINT16[R_IO_L]) -#define RSCAN0TMID50LL (RSCAN0.TMID50.UINT8[R_IO_LL]) -#define RSCAN0TMID50LH (RSCAN0.TMID50.UINT8[R_IO_LH]) -#define RSCAN0TMID50H (RSCAN0.TMID50.UINT16[R_IO_H]) -#define RSCAN0TMID50HL (RSCAN0.TMID50.UINT8[R_IO_HL]) -#define RSCAN0TMID50HH (RSCAN0.TMID50.UINT8[R_IO_HH]) -#define RSCAN0TMPTR50 (RSCAN0.TMPTR50.UINT32) -#define RSCAN0TMPTR50L (RSCAN0.TMPTR50.UINT16[R_IO_L]) -#define RSCAN0TMPTR50LL (RSCAN0.TMPTR50.UINT8[R_IO_LL]) -#define RSCAN0TMPTR50LH (RSCAN0.TMPTR50.UINT8[R_IO_LH]) -#define RSCAN0TMPTR50H (RSCAN0.TMPTR50.UINT16[R_IO_H]) -#define RSCAN0TMPTR50HL (RSCAN0.TMPTR50.UINT8[R_IO_HL]) -#define RSCAN0TMPTR50HH (RSCAN0.TMPTR50.UINT8[R_IO_HH]) -#define RSCAN0TMDF050 (RSCAN0.TMDF050.UINT32) -#define RSCAN0TMDF050L (RSCAN0.TMDF050.UINT16[R_IO_L]) -#define RSCAN0TMDF050LL (RSCAN0.TMDF050.UINT8[R_IO_LL]) -#define RSCAN0TMDF050LH (RSCAN0.TMDF050.UINT8[R_IO_LH]) -#define RSCAN0TMDF050H (RSCAN0.TMDF050.UINT16[R_IO_H]) -#define RSCAN0TMDF050HL (RSCAN0.TMDF050.UINT8[R_IO_HL]) -#define RSCAN0TMDF050HH (RSCAN0.TMDF050.UINT8[R_IO_HH]) -#define RSCAN0TMDF150 (RSCAN0.TMDF150.UINT32) -#define RSCAN0TMDF150L (RSCAN0.TMDF150.UINT16[R_IO_L]) -#define RSCAN0TMDF150LL (RSCAN0.TMDF150.UINT8[R_IO_LL]) -#define RSCAN0TMDF150LH (RSCAN0.TMDF150.UINT8[R_IO_LH]) -#define RSCAN0TMDF150H (RSCAN0.TMDF150.UINT16[R_IO_H]) -#define RSCAN0TMDF150HL (RSCAN0.TMDF150.UINT8[R_IO_HL]) -#define RSCAN0TMDF150HH (RSCAN0.TMDF150.UINT8[R_IO_HH]) -#define RSCAN0TMID51 (RSCAN0.TMID51.UINT32) -#define RSCAN0TMID51L (RSCAN0.TMID51.UINT16[R_IO_L]) -#define RSCAN0TMID51LL (RSCAN0.TMID51.UINT8[R_IO_LL]) -#define RSCAN0TMID51LH (RSCAN0.TMID51.UINT8[R_IO_LH]) -#define RSCAN0TMID51H (RSCAN0.TMID51.UINT16[R_IO_H]) -#define RSCAN0TMID51HL (RSCAN0.TMID51.UINT8[R_IO_HL]) -#define RSCAN0TMID51HH (RSCAN0.TMID51.UINT8[R_IO_HH]) -#define RSCAN0TMPTR51 (RSCAN0.TMPTR51.UINT32) -#define RSCAN0TMPTR51L (RSCAN0.TMPTR51.UINT16[R_IO_L]) -#define RSCAN0TMPTR51LL (RSCAN0.TMPTR51.UINT8[R_IO_LL]) -#define RSCAN0TMPTR51LH (RSCAN0.TMPTR51.UINT8[R_IO_LH]) -#define RSCAN0TMPTR51H (RSCAN0.TMPTR51.UINT16[R_IO_H]) -#define RSCAN0TMPTR51HL (RSCAN0.TMPTR51.UINT8[R_IO_HL]) -#define RSCAN0TMPTR51HH (RSCAN0.TMPTR51.UINT8[R_IO_HH]) -#define RSCAN0TMDF051 (RSCAN0.TMDF051.UINT32) -#define RSCAN0TMDF051L (RSCAN0.TMDF051.UINT16[R_IO_L]) -#define RSCAN0TMDF051LL (RSCAN0.TMDF051.UINT8[R_IO_LL]) -#define RSCAN0TMDF051LH (RSCAN0.TMDF051.UINT8[R_IO_LH]) -#define RSCAN0TMDF051H (RSCAN0.TMDF051.UINT16[R_IO_H]) -#define RSCAN0TMDF051HL (RSCAN0.TMDF051.UINT8[R_IO_HL]) -#define RSCAN0TMDF051HH (RSCAN0.TMDF051.UINT8[R_IO_HH]) -#define RSCAN0TMDF151 (RSCAN0.TMDF151.UINT32) -#define RSCAN0TMDF151L (RSCAN0.TMDF151.UINT16[R_IO_L]) -#define RSCAN0TMDF151LL (RSCAN0.TMDF151.UINT8[R_IO_LL]) -#define RSCAN0TMDF151LH (RSCAN0.TMDF151.UINT8[R_IO_LH]) -#define RSCAN0TMDF151H (RSCAN0.TMDF151.UINT16[R_IO_H]) -#define RSCAN0TMDF151HL (RSCAN0.TMDF151.UINT8[R_IO_HL]) -#define RSCAN0TMDF151HH (RSCAN0.TMDF151.UINT8[R_IO_HH]) -#define RSCAN0TMID52 (RSCAN0.TMID52.UINT32) -#define RSCAN0TMID52L (RSCAN0.TMID52.UINT16[R_IO_L]) -#define RSCAN0TMID52LL (RSCAN0.TMID52.UINT8[R_IO_LL]) -#define RSCAN0TMID52LH (RSCAN0.TMID52.UINT8[R_IO_LH]) -#define RSCAN0TMID52H (RSCAN0.TMID52.UINT16[R_IO_H]) -#define RSCAN0TMID52HL (RSCAN0.TMID52.UINT8[R_IO_HL]) -#define RSCAN0TMID52HH (RSCAN0.TMID52.UINT8[R_IO_HH]) -#define RSCAN0TMPTR52 (RSCAN0.TMPTR52.UINT32) -#define RSCAN0TMPTR52L (RSCAN0.TMPTR52.UINT16[R_IO_L]) -#define RSCAN0TMPTR52LL (RSCAN0.TMPTR52.UINT8[R_IO_LL]) -#define RSCAN0TMPTR52LH (RSCAN0.TMPTR52.UINT8[R_IO_LH]) -#define RSCAN0TMPTR52H (RSCAN0.TMPTR52.UINT16[R_IO_H]) -#define RSCAN0TMPTR52HL (RSCAN0.TMPTR52.UINT8[R_IO_HL]) -#define RSCAN0TMPTR52HH (RSCAN0.TMPTR52.UINT8[R_IO_HH]) -#define RSCAN0TMDF052 (RSCAN0.TMDF052.UINT32) -#define RSCAN0TMDF052L (RSCAN0.TMDF052.UINT16[R_IO_L]) -#define RSCAN0TMDF052LL (RSCAN0.TMDF052.UINT8[R_IO_LL]) -#define RSCAN0TMDF052LH (RSCAN0.TMDF052.UINT8[R_IO_LH]) -#define RSCAN0TMDF052H (RSCAN0.TMDF052.UINT16[R_IO_H]) -#define RSCAN0TMDF052HL (RSCAN0.TMDF052.UINT8[R_IO_HL]) -#define RSCAN0TMDF052HH (RSCAN0.TMDF052.UINT8[R_IO_HH]) -#define RSCAN0TMDF152 (RSCAN0.TMDF152.UINT32) -#define RSCAN0TMDF152L (RSCAN0.TMDF152.UINT16[R_IO_L]) -#define RSCAN0TMDF152LL (RSCAN0.TMDF152.UINT8[R_IO_LL]) -#define RSCAN0TMDF152LH (RSCAN0.TMDF152.UINT8[R_IO_LH]) -#define RSCAN0TMDF152H (RSCAN0.TMDF152.UINT16[R_IO_H]) -#define RSCAN0TMDF152HL (RSCAN0.TMDF152.UINT8[R_IO_HL]) -#define RSCAN0TMDF152HH (RSCAN0.TMDF152.UINT8[R_IO_HH]) -#define RSCAN0TMID53 (RSCAN0.TMID53.UINT32) -#define RSCAN0TMID53L (RSCAN0.TMID53.UINT16[R_IO_L]) -#define RSCAN0TMID53LL (RSCAN0.TMID53.UINT8[R_IO_LL]) -#define RSCAN0TMID53LH (RSCAN0.TMID53.UINT8[R_IO_LH]) -#define RSCAN0TMID53H (RSCAN0.TMID53.UINT16[R_IO_H]) -#define RSCAN0TMID53HL (RSCAN0.TMID53.UINT8[R_IO_HL]) -#define RSCAN0TMID53HH (RSCAN0.TMID53.UINT8[R_IO_HH]) -#define RSCAN0TMPTR53 (RSCAN0.TMPTR53.UINT32) -#define RSCAN0TMPTR53L (RSCAN0.TMPTR53.UINT16[R_IO_L]) -#define RSCAN0TMPTR53LL (RSCAN0.TMPTR53.UINT8[R_IO_LL]) -#define RSCAN0TMPTR53LH (RSCAN0.TMPTR53.UINT8[R_IO_LH]) -#define RSCAN0TMPTR53H (RSCAN0.TMPTR53.UINT16[R_IO_H]) -#define RSCAN0TMPTR53HL (RSCAN0.TMPTR53.UINT8[R_IO_HL]) -#define RSCAN0TMPTR53HH (RSCAN0.TMPTR53.UINT8[R_IO_HH]) -#define RSCAN0TMDF053 (RSCAN0.TMDF053.UINT32) -#define RSCAN0TMDF053L (RSCAN0.TMDF053.UINT16[R_IO_L]) -#define RSCAN0TMDF053LL (RSCAN0.TMDF053.UINT8[R_IO_LL]) -#define RSCAN0TMDF053LH (RSCAN0.TMDF053.UINT8[R_IO_LH]) -#define RSCAN0TMDF053H (RSCAN0.TMDF053.UINT16[R_IO_H]) -#define RSCAN0TMDF053HL (RSCAN0.TMDF053.UINT8[R_IO_HL]) -#define RSCAN0TMDF053HH (RSCAN0.TMDF053.UINT8[R_IO_HH]) -#define RSCAN0TMDF153 (RSCAN0.TMDF153.UINT32) -#define RSCAN0TMDF153L (RSCAN0.TMDF153.UINT16[R_IO_L]) -#define RSCAN0TMDF153LL (RSCAN0.TMDF153.UINT8[R_IO_LL]) -#define RSCAN0TMDF153LH (RSCAN0.TMDF153.UINT8[R_IO_LH]) -#define RSCAN0TMDF153H (RSCAN0.TMDF153.UINT16[R_IO_H]) -#define RSCAN0TMDF153HL (RSCAN0.TMDF153.UINT8[R_IO_HL]) -#define RSCAN0TMDF153HH (RSCAN0.TMDF153.UINT8[R_IO_HH]) -#define RSCAN0TMID54 (RSCAN0.TMID54.UINT32) -#define RSCAN0TMID54L (RSCAN0.TMID54.UINT16[R_IO_L]) -#define RSCAN0TMID54LL (RSCAN0.TMID54.UINT8[R_IO_LL]) -#define RSCAN0TMID54LH (RSCAN0.TMID54.UINT8[R_IO_LH]) -#define RSCAN0TMID54H (RSCAN0.TMID54.UINT16[R_IO_H]) -#define RSCAN0TMID54HL (RSCAN0.TMID54.UINT8[R_IO_HL]) -#define RSCAN0TMID54HH (RSCAN0.TMID54.UINT8[R_IO_HH]) -#define RSCAN0TMPTR54 (RSCAN0.TMPTR54.UINT32) -#define RSCAN0TMPTR54L (RSCAN0.TMPTR54.UINT16[R_IO_L]) -#define RSCAN0TMPTR54LL (RSCAN0.TMPTR54.UINT8[R_IO_LL]) -#define RSCAN0TMPTR54LH (RSCAN0.TMPTR54.UINT8[R_IO_LH]) -#define RSCAN0TMPTR54H (RSCAN0.TMPTR54.UINT16[R_IO_H]) -#define RSCAN0TMPTR54HL (RSCAN0.TMPTR54.UINT8[R_IO_HL]) -#define RSCAN0TMPTR54HH (RSCAN0.TMPTR54.UINT8[R_IO_HH]) -#define RSCAN0TMDF054 (RSCAN0.TMDF054.UINT32) -#define RSCAN0TMDF054L (RSCAN0.TMDF054.UINT16[R_IO_L]) -#define RSCAN0TMDF054LL (RSCAN0.TMDF054.UINT8[R_IO_LL]) -#define RSCAN0TMDF054LH (RSCAN0.TMDF054.UINT8[R_IO_LH]) -#define RSCAN0TMDF054H (RSCAN0.TMDF054.UINT16[R_IO_H]) -#define RSCAN0TMDF054HL (RSCAN0.TMDF054.UINT8[R_IO_HL]) -#define RSCAN0TMDF054HH (RSCAN0.TMDF054.UINT8[R_IO_HH]) -#define RSCAN0TMDF154 (RSCAN0.TMDF154.UINT32) -#define RSCAN0TMDF154L (RSCAN0.TMDF154.UINT16[R_IO_L]) -#define RSCAN0TMDF154LL (RSCAN0.TMDF154.UINT8[R_IO_LL]) -#define RSCAN0TMDF154LH (RSCAN0.TMDF154.UINT8[R_IO_LH]) -#define RSCAN0TMDF154H (RSCAN0.TMDF154.UINT16[R_IO_H]) -#define RSCAN0TMDF154HL (RSCAN0.TMDF154.UINT8[R_IO_HL]) -#define RSCAN0TMDF154HH (RSCAN0.TMDF154.UINT8[R_IO_HH]) -#define RSCAN0TMID55 (RSCAN0.TMID55.UINT32) -#define RSCAN0TMID55L (RSCAN0.TMID55.UINT16[R_IO_L]) -#define RSCAN0TMID55LL (RSCAN0.TMID55.UINT8[R_IO_LL]) -#define RSCAN0TMID55LH (RSCAN0.TMID55.UINT8[R_IO_LH]) -#define RSCAN0TMID55H (RSCAN0.TMID55.UINT16[R_IO_H]) -#define RSCAN0TMID55HL (RSCAN0.TMID55.UINT8[R_IO_HL]) -#define RSCAN0TMID55HH (RSCAN0.TMID55.UINT8[R_IO_HH]) -#define RSCAN0TMPTR55 (RSCAN0.TMPTR55.UINT32) -#define RSCAN0TMPTR55L (RSCAN0.TMPTR55.UINT16[R_IO_L]) -#define RSCAN0TMPTR55LL (RSCAN0.TMPTR55.UINT8[R_IO_LL]) -#define RSCAN0TMPTR55LH (RSCAN0.TMPTR55.UINT8[R_IO_LH]) -#define RSCAN0TMPTR55H (RSCAN0.TMPTR55.UINT16[R_IO_H]) -#define RSCAN0TMPTR55HL (RSCAN0.TMPTR55.UINT8[R_IO_HL]) -#define RSCAN0TMPTR55HH (RSCAN0.TMPTR55.UINT8[R_IO_HH]) -#define RSCAN0TMDF055 (RSCAN0.TMDF055.UINT32) -#define RSCAN0TMDF055L (RSCAN0.TMDF055.UINT16[R_IO_L]) -#define RSCAN0TMDF055LL (RSCAN0.TMDF055.UINT8[R_IO_LL]) -#define RSCAN0TMDF055LH (RSCAN0.TMDF055.UINT8[R_IO_LH]) -#define RSCAN0TMDF055H (RSCAN0.TMDF055.UINT16[R_IO_H]) -#define RSCAN0TMDF055HL (RSCAN0.TMDF055.UINT8[R_IO_HL]) -#define RSCAN0TMDF055HH (RSCAN0.TMDF055.UINT8[R_IO_HH]) -#define RSCAN0TMDF155 (RSCAN0.TMDF155.UINT32) -#define RSCAN0TMDF155L (RSCAN0.TMDF155.UINT16[R_IO_L]) -#define RSCAN0TMDF155LL (RSCAN0.TMDF155.UINT8[R_IO_LL]) -#define RSCAN0TMDF155LH (RSCAN0.TMDF155.UINT8[R_IO_LH]) -#define RSCAN0TMDF155H (RSCAN0.TMDF155.UINT16[R_IO_H]) -#define RSCAN0TMDF155HL (RSCAN0.TMDF155.UINT8[R_IO_HL]) -#define RSCAN0TMDF155HH (RSCAN0.TMDF155.UINT8[R_IO_HH]) -#define RSCAN0TMID56 (RSCAN0.TMID56.UINT32) -#define RSCAN0TMID56L (RSCAN0.TMID56.UINT16[R_IO_L]) -#define RSCAN0TMID56LL (RSCAN0.TMID56.UINT8[R_IO_LL]) -#define RSCAN0TMID56LH (RSCAN0.TMID56.UINT8[R_IO_LH]) -#define RSCAN0TMID56H (RSCAN0.TMID56.UINT16[R_IO_H]) -#define RSCAN0TMID56HL (RSCAN0.TMID56.UINT8[R_IO_HL]) -#define RSCAN0TMID56HH (RSCAN0.TMID56.UINT8[R_IO_HH]) -#define RSCAN0TMPTR56 (RSCAN0.TMPTR56.UINT32) -#define RSCAN0TMPTR56L (RSCAN0.TMPTR56.UINT16[R_IO_L]) -#define RSCAN0TMPTR56LL (RSCAN0.TMPTR56.UINT8[R_IO_LL]) -#define RSCAN0TMPTR56LH (RSCAN0.TMPTR56.UINT8[R_IO_LH]) -#define RSCAN0TMPTR56H (RSCAN0.TMPTR56.UINT16[R_IO_H]) -#define RSCAN0TMPTR56HL (RSCAN0.TMPTR56.UINT8[R_IO_HL]) -#define RSCAN0TMPTR56HH (RSCAN0.TMPTR56.UINT8[R_IO_HH]) -#define RSCAN0TMDF056 (RSCAN0.TMDF056.UINT32) -#define RSCAN0TMDF056L (RSCAN0.TMDF056.UINT16[R_IO_L]) -#define RSCAN0TMDF056LL (RSCAN0.TMDF056.UINT8[R_IO_LL]) -#define RSCAN0TMDF056LH (RSCAN0.TMDF056.UINT8[R_IO_LH]) -#define RSCAN0TMDF056H (RSCAN0.TMDF056.UINT16[R_IO_H]) -#define RSCAN0TMDF056HL (RSCAN0.TMDF056.UINT8[R_IO_HL]) -#define RSCAN0TMDF056HH (RSCAN0.TMDF056.UINT8[R_IO_HH]) -#define RSCAN0TMDF156 (RSCAN0.TMDF156.UINT32) -#define RSCAN0TMDF156L (RSCAN0.TMDF156.UINT16[R_IO_L]) -#define RSCAN0TMDF156LL (RSCAN0.TMDF156.UINT8[R_IO_LL]) -#define RSCAN0TMDF156LH (RSCAN0.TMDF156.UINT8[R_IO_LH]) -#define RSCAN0TMDF156H (RSCAN0.TMDF156.UINT16[R_IO_H]) -#define RSCAN0TMDF156HL (RSCAN0.TMDF156.UINT8[R_IO_HL]) -#define RSCAN0TMDF156HH (RSCAN0.TMDF156.UINT8[R_IO_HH]) -#define RSCAN0TMID57 (RSCAN0.TMID57.UINT32) -#define RSCAN0TMID57L (RSCAN0.TMID57.UINT16[R_IO_L]) -#define RSCAN0TMID57LL (RSCAN0.TMID57.UINT8[R_IO_LL]) -#define RSCAN0TMID57LH (RSCAN0.TMID57.UINT8[R_IO_LH]) -#define RSCAN0TMID57H (RSCAN0.TMID57.UINT16[R_IO_H]) -#define RSCAN0TMID57HL (RSCAN0.TMID57.UINT8[R_IO_HL]) -#define RSCAN0TMID57HH (RSCAN0.TMID57.UINT8[R_IO_HH]) -#define RSCAN0TMPTR57 (RSCAN0.TMPTR57.UINT32) -#define RSCAN0TMPTR57L (RSCAN0.TMPTR57.UINT16[R_IO_L]) -#define RSCAN0TMPTR57LL (RSCAN0.TMPTR57.UINT8[R_IO_LL]) -#define RSCAN0TMPTR57LH (RSCAN0.TMPTR57.UINT8[R_IO_LH]) -#define RSCAN0TMPTR57H (RSCAN0.TMPTR57.UINT16[R_IO_H]) -#define RSCAN0TMPTR57HL (RSCAN0.TMPTR57.UINT8[R_IO_HL]) -#define RSCAN0TMPTR57HH (RSCAN0.TMPTR57.UINT8[R_IO_HH]) -#define RSCAN0TMDF057 (RSCAN0.TMDF057.UINT32) -#define RSCAN0TMDF057L (RSCAN0.TMDF057.UINT16[R_IO_L]) -#define RSCAN0TMDF057LL (RSCAN0.TMDF057.UINT8[R_IO_LL]) -#define RSCAN0TMDF057LH (RSCAN0.TMDF057.UINT8[R_IO_LH]) -#define RSCAN0TMDF057H (RSCAN0.TMDF057.UINT16[R_IO_H]) -#define RSCAN0TMDF057HL (RSCAN0.TMDF057.UINT8[R_IO_HL]) -#define RSCAN0TMDF057HH (RSCAN0.TMDF057.UINT8[R_IO_HH]) -#define RSCAN0TMDF157 (RSCAN0.TMDF157.UINT32) -#define RSCAN0TMDF157L (RSCAN0.TMDF157.UINT16[R_IO_L]) -#define RSCAN0TMDF157LL (RSCAN0.TMDF157.UINT8[R_IO_LL]) -#define RSCAN0TMDF157LH (RSCAN0.TMDF157.UINT8[R_IO_LH]) -#define RSCAN0TMDF157H (RSCAN0.TMDF157.UINT16[R_IO_H]) -#define RSCAN0TMDF157HL (RSCAN0.TMDF157.UINT8[R_IO_HL]) -#define RSCAN0TMDF157HH (RSCAN0.TMDF157.UINT8[R_IO_HH]) -#define RSCAN0TMID58 (RSCAN0.TMID58.UINT32) -#define RSCAN0TMID58L (RSCAN0.TMID58.UINT16[R_IO_L]) -#define RSCAN0TMID58LL (RSCAN0.TMID58.UINT8[R_IO_LL]) -#define RSCAN0TMID58LH (RSCAN0.TMID58.UINT8[R_IO_LH]) -#define RSCAN0TMID58H (RSCAN0.TMID58.UINT16[R_IO_H]) -#define RSCAN0TMID58HL (RSCAN0.TMID58.UINT8[R_IO_HL]) -#define RSCAN0TMID58HH (RSCAN0.TMID58.UINT8[R_IO_HH]) -#define RSCAN0TMPTR58 (RSCAN0.TMPTR58.UINT32) -#define RSCAN0TMPTR58L (RSCAN0.TMPTR58.UINT16[R_IO_L]) -#define RSCAN0TMPTR58LL (RSCAN0.TMPTR58.UINT8[R_IO_LL]) -#define RSCAN0TMPTR58LH (RSCAN0.TMPTR58.UINT8[R_IO_LH]) -#define RSCAN0TMPTR58H (RSCAN0.TMPTR58.UINT16[R_IO_H]) -#define RSCAN0TMPTR58HL (RSCAN0.TMPTR58.UINT8[R_IO_HL]) -#define RSCAN0TMPTR58HH (RSCAN0.TMPTR58.UINT8[R_IO_HH]) -#define RSCAN0TMDF058 (RSCAN0.TMDF058.UINT32) -#define RSCAN0TMDF058L (RSCAN0.TMDF058.UINT16[R_IO_L]) -#define RSCAN0TMDF058LL (RSCAN0.TMDF058.UINT8[R_IO_LL]) -#define RSCAN0TMDF058LH (RSCAN0.TMDF058.UINT8[R_IO_LH]) -#define RSCAN0TMDF058H (RSCAN0.TMDF058.UINT16[R_IO_H]) -#define RSCAN0TMDF058HL (RSCAN0.TMDF058.UINT8[R_IO_HL]) -#define RSCAN0TMDF058HH (RSCAN0.TMDF058.UINT8[R_IO_HH]) -#define RSCAN0TMDF158 (RSCAN0.TMDF158.UINT32) -#define RSCAN0TMDF158L (RSCAN0.TMDF158.UINT16[R_IO_L]) -#define RSCAN0TMDF158LL (RSCAN0.TMDF158.UINT8[R_IO_LL]) -#define RSCAN0TMDF158LH (RSCAN0.TMDF158.UINT8[R_IO_LH]) -#define RSCAN0TMDF158H (RSCAN0.TMDF158.UINT16[R_IO_H]) -#define RSCAN0TMDF158HL (RSCAN0.TMDF158.UINT8[R_IO_HL]) -#define RSCAN0TMDF158HH (RSCAN0.TMDF158.UINT8[R_IO_HH]) -#define RSCAN0TMID59 (RSCAN0.TMID59.UINT32) -#define RSCAN0TMID59L (RSCAN0.TMID59.UINT16[R_IO_L]) -#define RSCAN0TMID59LL (RSCAN0.TMID59.UINT8[R_IO_LL]) -#define RSCAN0TMID59LH (RSCAN0.TMID59.UINT8[R_IO_LH]) -#define RSCAN0TMID59H (RSCAN0.TMID59.UINT16[R_IO_H]) -#define RSCAN0TMID59HL (RSCAN0.TMID59.UINT8[R_IO_HL]) -#define RSCAN0TMID59HH (RSCAN0.TMID59.UINT8[R_IO_HH]) -#define RSCAN0TMPTR59 (RSCAN0.TMPTR59.UINT32) -#define RSCAN0TMPTR59L (RSCAN0.TMPTR59.UINT16[R_IO_L]) -#define RSCAN0TMPTR59LL (RSCAN0.TMPTR59.UINT8[R_IO_LL]) -#define RSCAN0TMPTR59LH (RSCAN0.TMPTR59.UINT8[R_IO_LH]) -#define RSCAN0TMPTR59H (RSCAN0.TMPTR59.UINT16[R_IO_H]) -#define RSCAN0TMPTR59HL (RSCAN0.TMPTR59.UINT8[R_IO_HL]) -#define RSCAN0TMPTR59HH (RSCAN0.TMPTR59.UINT8[R_IO_HH]) -#define RSCAN0TMDF059 (RSCAN0.TMDF059.UINT32) -#define RSCAN0TMDF059L (RSCAN0.TMDF059.UINT16[R_IO_L]) -#define RSCAN0TMDF059LL (RSCAN0.TMDF059.UINT8[R_IO_LL]) -#define RSCAN0TMDF059LH (RSCAN0.TMDF059.UINT8[R_IO_LH]) -#define RSCAN0TMDF059H (RSCAN0.TMDF059.UINT16[R_IO_H]) -#define RSCAN0TMDF059HL (RSCAN0.TMDF059.UINT8[R_IO_HL]) -#define RSCAN0TMDF059HH (RSCAN0.TMDF059.UINT8[R_IO_HH]) -#define RSCAN0TMDF159 (RSCAN0.TMDF159.UINT32) -#define RSCAN0TMDF159L (RSCAN0.TMDF159.UINT16[R_IO_L]) -#define RSCAN0TMDF159LL (RSCAN0.TMDF159.UINT8[R_IO_LL]) -#define RSCAN0TMDF159LH (RSCAN0.TMDF159.UINT8[R_IO_LH]) -#define RSCAN0TMDF159H (RSCAN0.TMDF159.UINT16[R_IO_H]) -#define RSCAN0TMDF159HL (RSCAN0.TMDF159.UINT8[R_IO_HL]) -#define RSCAN0TMDF159HH (RSCAN0.TMDF159.UINT8[R_IO_HH]) -#define RSCAN0TMID60 (RSCAN0.TMID60.UINT32) -#define RSCAN0TMID60L (RSCAN0.TMID60.UINT16[R_IO_L]) -#define RSCAN0TMID60LL (RSCAN0.TMID60.UINT8[R_IO_LL]) -#define RSCAN0TMID60LH (RSCAN0.TMID60.UINT8[R_IO_LH]) -#define RSCAN0TMID60H (RSCAN0.TMID60.UINT16[R_IO_H]) -#define RSCAN0TMID60HL (RSCAN0.TMID60.UINT8[R_IO_HL]) -#define RSCAN0TMID60HH (RSCAN0.TMID60.UINT8[R_IO_HH]) -#define RSCAN0TMPTR60 (RSCAN0.TMPTR60.UINT32) -#define RSCAN0TMPTR60L (RSCAN0.TMPTR60.UINT16[R_IO_L]) -#define RSCAN0TMPTR60LL (RSCAN0.TMPTR60.UINT8[R_IO_LL]) -#define RSCAN0TMPTR60LH (RSCAN0.TMPTR60.UINT8[R_IO_LH]) -#define RSCAN0TMPTR60H (RSCAN0.TMPTR60.UINT16[R_IO_H]) -#define RSCAN0TMPTR60HL (RSCAN0.TMPTR60.UINT8[R_IO_HL]) -#define RSCAN0TMPTR60HH (RSCAN0.TMPTR60.UINT8[R_IO_HH]) -#define RSCAN0TMDF060 (RSCAN0.TMDF060.UINT32) -#define RSCAN0TMDF060L (RSCAN0.TMDF060.UINT16[R_IO_L]) -#define RSCAN0TMDF060LL (RSCAN0.TMDF060.UINT8[R_IO_LL]) -#define RSCAN0TMDF060LH (RSCAN0.TMDF060.UINT8[R_IO_LH]) -#define RSCAN0TMDF060H (RSCAN0.TMDF060.UINT16[R_IO_H]) -#define RSCAN0TMDF060HL (RSCAN0.TMDF060.UINT8[R_IO_HL]) -#define RSCAN0TMDF060HH (RSCAN0.TMDF060.UINT8[R_IO_HH]) -#define RSCAN0TMDF160 (RSCAN0.TMDF160.UINT32) -#define RSCAN0TMDF160L (RSCAN0.TMDF160.UINT16[R_IO_L]) -#define RSCAN0TMDF160LL (RSCAN0.TMDF160.UINT8[R_IO_LL]) -#define RSCAN0TMDF160LH (RSCAN0.TMDF160.UINT8[R_IO_LH]) -#define RSCAN0TMDF160H (RSCAN0.TMDF160.UINT16[R_IO_H]) -#define RSCAN0TMDF160HL (RSCAN0.TMDF160.UINT8[R_IO_HL]) -#define RSCAN0TMDF160HH (RSCAN0.TMDF160.UINT8[R_IO_HH]) -#define RSCAN0TMID61 (RSCAN0.TMID61.UINT32) -#define RSCAN0TMID61L (RSCAN0.TMID61.UINT16[R_IO_L]) -#define RSCAN0TMID61LL (RSCAN0.TMID61.UINT8[R_IO_LL]) -#define RSCAN0TMID61LH (RSCAN0.TMID61.UINT8[R_IO_LH]) -#define RSCAN0TMID61H (RSCAN0.TMID61.UINT16[R_IO_H]) -#define RSCAN0TMID61HL (RSCAN0.TMID61.UINT8[R_IO_HL]) -#define RSCAN0TMID61HH (RSCAN0.TMID61.UINT8[R_IO_HH]) -#define RSCAN0TMPTR61 (RSCAN0.TMPTR61.UINT32) -#define RSCAN0TMPTR61L (RSCAN0.TMPTR61.UINT16[R_IO_L]) -#define RSCAN0TMPTR61LL (RSCAN0.TMPTR61.UINT8[R_IO_LL]) -#define RSCAN0TMPTR61LH (RSCAN0.TMPTR61.UINT8[R_IO_LH]) -#define RSCAN0TMPTR61H (RSCAN0.TMPTR61.UINT16[R_IO_H]) -#define RSCAN0TMPTR61HL (RSCAN0.TMPTR61.UINT8[R_IO_HL]) -#define RSCAN0TMPTR61HH (RSCAN0.TMPTR61.UINT8[R_IO_HH]) -#define RSCAN0TMDF061 (RSCAN0.TMDF061.UINT32) -#define RSCAN0TMDF061L (RSCAN0.TMDF061.UINT16[R_IO_L]) -#define RSCAN0TMDF061LL (RSCAN0.TMDF061.UINT8[R_IO_LL]) -#define RSCAN0TMDF061LH (RSCAN0.TMDF061.UINT8[R_IO_LH]) -#define RSCAN0TMDF061H (RSCAN0.TMDF061.UINT16[R_IO_H]) -#define RSCAN0TMDF061HL (RSCAN0.TMDF061.UINT8[R_IO_HL]) -#define RSCAN0TMDF061HH (RSCAN0.TMDF061.UINT8[R_IO_HH]) -#define RSCAN0TMDF161 (RSCAN0.TMDF161.UINT32) -#define RSCAN0TMDF161L (RSCAN0.TMDF161.UINT16[R_IO_L]) -#define RSCAN0TMDF161LL (RSCAN0.TMDF161.UINT8[R_IO_LL]) -#define RSCAN0TMDF161LH (RSCAN0.TMDF161.UINT8[R_IO_LH]) -#define RSCAN0TMDF161H (RSCAN0.TMDF161.UINT16[R_IO_H]) -#define RSCAN0TMDF161HL (RSCAN0.TMDF161.UINT8[R_IO_HL]) -#define RSCAN0TMDF161HH (RSCAN0.TMDF161.UINT8[R_IO_HH]) -#define RSCAN0TMID62 (RSCAN0.TMID62.UINT32) -#define RSCAN0TMID62L (RSCAN0.TMID62.UINT16[R_IO_L]) -#define RSCAN0TMID62LL (RSCAN0.TMID62.UINT8[R_IO_LL]) -#define RSCAN0TMID62LH (RSCAN0.TMID62.UINT8[R_IO_LH]) -#define RSCAN0TMID62H (RSCAN0.TMID62.UINT16[R_IO_H]) -#define RSCAN0TMID62HL (RSCAN0.TMID62.UINT8[R_IO_HL]) -#define RSCAN0TMID62HH (RSCAN0.TMID62.UINT8[R_IO_HH]) -#define RSCAN0TMPTR62 (RSCAN0.TMPTR62.UINT32) -#define RSCAN0TMPTR62L (RSCAN0.TMPTR62.UINT16[R_IO_L]) -#define RSCAN0TMPTR62LL (RSCAN0.TMPTR62.UINT8[R_IO_LL]) -#define RSCAN0TMPTR62LH (RSCAN0.TMPTR62.UINT8[R_IO_LH]) -#define RSCAN0TMPTR62H (RSCAN0.TMPTR62.UINT16[R_IO_H]) -#define RSCAN0TMPTR62HL (RSCAN0.TMPTR62.UINT8[R_IO_HL]) -#define RSCAN0TMPTR62HH (RSCAN0.TMPTR62.UINT8[R_IO_HH]) -#define RSCAN0TMDF062 (RSCAN0.TMDF062.UINT32) -#define RSCAN0TMDF062L (RSCAN0.TMDF062.UINT16[R_IO_L]) -#define RSCAN0TMDF062LL (RSCAN0.TMDF062.UINT8[R_IO_LL]) -#define RSCAN0TMDF062LH (RSCAN0.TMDF062.UINT8[R_IO_LH]) -#define RSCAN0TMDF062H (RSCAN0.TMDF062.UINT16[R_IO_H]) -#define RSCAN0TMDF062HL (RSCAN0.TMDF062.UINT8[R_IO_HL]) -#define RSCAN0TMDF062HH (RSCAN0.TMDF062.UINT8[R_IO_HH]) -#define RSCAN0TMDF162 (RSCAN0.TMDF162.UINT32) -#define RSCAN0TMDF162L (RSCAN0.TMDF162.UINT16[R_IO_L]) -#define RSCAN0TMDF162LL (RSCAN0.TMDF162.UINT8[R_IO_LL]) -#define RSCAN0TMDF162LH (RSCAN0.TMDF162.UINT8[R_IO_LH]) -#define RSCAN0TMDF162H (RSCAN0.TMDF162.UINT16[R_IO_H]) -#define RSCAN0TMDF162HL (RSCAN0.TMDF162.UINT8[R_IO_HL]) -#define RSCAN0TMDF162HH (RSCAN0.TMDF162.UINT8[R_IO_HH]) -#define RSCAN0TMID63 (RSCAN0.TMID63.UINT32) -#define RSCAN0TMID63L (RSCAN0.TMID63.UINT16[R_IO_L]) -#define RSCAN0TMID63LL (RSCAN0.TMID63.UINT8[R_IO_LL]) -#define RSCAN0TMID63LH (RSCAN0.TMID63.UINT8[R_IO_LH]) -#define RSCAN0TMID63H (RSCAN0.TMID63.UINT16[R_IO_H]) -#define RSCAN0TMID63HL (RSCAN0.TMID63.UINT8[R_IO_HL]) -#define RSCAN0TMID63HH (RSCAN0.TMID63.UINT8[R_IO_HH]) -#define RSCAN0TMPTR63 (RSCAN0.TMPTR63.UINT32) -#define RSCAN0TMPTR63L (RSCAN0.TMPTR63.UINT16[R_IO_L]) -#define RSCAN0TMPTR63LL (RSCAN0.TMPTR63.UINT8[R_IO_LL]) -#define RSCAN0TMPTR63LH (RSCAN0.TMPTR63.UINT8[R_IO_LH]) -#define RSCAN0TMPTR63H (RSCAN0.TMPTR63.UINT16[R_IO_H]) -#define RSCAN0TMPTR63HL (RSCAN0.TMPTR63.UINT8[R_IO_HL]) -#define RSCAN0TMPTR63HH (RSCAN0.TMPTR63.UINT8[R_IO_HH]) -#define RSCAN0TMDF063 (RSCAN0.TMDF063.UINT32) -#define RSCAN0TMDF063L (RSCAN0.TMDF063.UINT16[R_IO_L]) -#define RSCAN0TMDF063LL (RSCAN0.TMDF063.UINT8[R_IO_LL]) -#define RSCAN0TMDF063LH (RSCAN0.TMDF063.UINT8[R_IO_LH]) -#define RSCAN0TMDF063H (RSCAN0.TMDF063.UINT16[R_IO_H]) -#define RSCAN0TMDF063HL (RSCAN0.TMDF063.UINT8[R_IO_HL]) -#define RSCAN0TMDF063HH (RSCAN0.TMDF063.UINT8[R_IO_HH]) -#define RSCAN0TMDF163 (RSCAN0.TMDF163.UINT32) -#define RSCAN0TMDF163L (RSCAN0.TMDF163.UINT16[R_IO_L]) -#define RSCAN0TMDF163LL (RSCAN0.TMDF163.UINT8[R_IO_LL]) -#define RSCAN0TMDF163LH (RSCAN0.TMDF163.UINT8[R_IO_LH]) -#define RSCAN0TMDF163H (RSCAN0.TMDF163.UINT16[R_IO_H]) -#define RSCAN0TMDF163HL (RSCAN0.TMDF163.UINT8[R_IO_HL]) -#define RSCAN0TMDF163HH (RSCAN0.TMDF163.UINT8[R_IO_HH]) -#define RSCAN0TMID64 (RSCAN0.TMID64.UINT32) -#define RSCAN0TMID64L (RSCAN0.TMID64.UINT16[R_IO_L]) -#define RSCAN0TMID64LL (RSCAN0.TMID64.UINT8[R_IO_LL]) -#define RSCAN0TMID64LH (RSCAN0.TMID64.UINT8[R_IO_LH]) -#define RSCAN0TMID64H (RSCAN0.TMID64.UINT16[R_IO_H]) -#define RSCAN0TMID64HL (RSCAN0.TMID64.UINT8[R_IO_HL]) -#define RSCAN0TMID64HH (RSCAN0.TMID64.UINT8[R_IO_HH]) -#define RSCAN0TMPTR64 (RSCAN0.TMPTR64.UINT32) -#define RSCAN0TMPTR64L (RSCAN0.TMPTR64.UINT16[R_IO_L]) -#define RSCAN0TMPTR64LL (RSCAN0.TMPTR64.UINT8[R_IO_LL]) -#define RSCAN0TMPTR64LH (RSCAN0.TMPTR64.UINT8[R_IO_LH]) -#define RSCAN0TMPTR64H (RSCAN0.TMPTR64.UINT16[R_IO_H]) -#define RSCAN0TMPTR64HL (RSCAN0.TMPTR64.UINT8[R_IO_HL]) -#define RSCAN0TMPTR64HH (RSCAN0.TMPTR64.UINT8[R_IO_HH]) -#define RSCAN0TMDF064 (RSCAN0.TMDF064.UINT32) -#define RSCAN0TMDF064L (RSCAN0.TMDF064.UINT16[R_IO_L]) -#define RSCAN0TMDF064LL (RSCAN0.TMDF064.UINT8[R_IO_LL]) -#define RSCAN0TMDF064LH (RSCAN0.TMDF064.UINT8[R_IO_LH]) -#define RSCAN0TMDF064H (RSCAN0.TMDF064.UINT16[R_IO_H]) -#define RSCAN0TMDF064HL (RSCAN0.TMDF064.UINT8[R_IO_HL]) -#define RSCAN0TMDF064HH (RSCAN0.TMDF064.UINT8[R_IO_HH]) -#define RSCAN0TMDF164 (RSCAN0.TMDF164.UINT32) -#define RSCAN0TMDF164L (RSCAN0.TMDF164.UINT16[R_IO_L]) -#define RSCAN0TMDF164LL (RSCAN0.TMDF164.UINT8[R_IO_LL]) -#define RSCAN0TMDF164LH (RSCAN0.TMDF164.UINT8[R_IO_LH]) -#define RSCAN0TMDF164H (RSCAN0.TMDF164.UINT16[R_IO_H]) -#define RSCAN0TMDF164HL (RSCAN0.TMDF164.UINT8[R_IO_HL]) -#define RSCAN0TMDF164HH (RSCAN0.TMDF164.UINT8[R_IO_HH]) -#define RSCAN0TMID65 (RSCAN0.TMID65.UINT32) -#define RSCAN0TMID65L (RSCAN0.TMID65.UINT16[R_IO_L]) -#define RSCAN0TMID65LL (RSCAN0.TMID65.UINT8[R_IO_LL]) -#define RSCAN0TMID65LH (RSCAN0.TMID65.UINT8[R_IO_LH]) -#define RSCAN0TMID65H (RSCAN0.TMID65.UINT16[R_IO_H]) -#define RSCAN0TMID65HL (RSCAN0.TMID65.UINT8[R_IO_HL]) -#define RSCAN0TMID65HH (RSCAN0.TMID65.UINT8[R_IO_HH]) -#define RSCAN0TMPTR65 (RSCAN0.TMPTR65.UINT32) -#define RSCAN0TMPTR65L (RSCAN0.TMPTR65.UINT16[R_IO_L]) -#define RSCAN0TMPTR65LL (RSCAN0.TMPTR65.UINT8[R_IO_LL]) -#define RSCAN0TMPTR65LH (RSCAN0.TMPTR65.UINT8[R_IO_LH]) -#define RSCAN0TMPTR65H (RSCAN0.TMPTR65.UINT16[R_IO_H]) -#define RSCAN0TMPTR65HL (RSCAN0.TMPTR65.UINT8[R_IO_HL]) -#define RSCAN0TMPTR65HH (RSCAN0.TMPTR65.UINT8[R_IO_HH]) -#define RSCAN0TMDF065 (RSCAN0.TMDF065.UINT32) -#define RSCAN0TMDF065L (RSCAN0.TMDF065.UINT16[R_IO_L]) -#define RSCAN0TMDF065LL (RSCAN0.TMDF065.UINT8[R_IO_LL]) -#define RSCAN0TMDF065LH (RSCAN0.TMDF065.UINT8[R_IO_LH]) -#define RSCAN0TMDF065H (RSCAN0.TMDF065.UINT16[R_IO_H]) -#define RSCAN0TMDF065HL (RSCAN0.TMDF065.UINT8[R_IO_HL]) -#define RSCAN0TMDF065HH (RSCAN0.TMDF065.UINT8[R_IO_HH]) -#define RSCAN0TMDF165 (RSCAN0.TMDF165.UINT32) -#define RSCAN0TMDF165L (RSCAN0.TMDF165.UINT16[R_IO_L]) -#define RSCAN0TMDF165LL (RSCAN0.TMDF165.UINT8[R_IO_LL]) -#define RSCAN0TMDF165LH (RSCAN0.TMDF165.UINT8[R_IO_LH]) -#define RSCAN0TMDF165H (RSCAN0.TMDF165.UINT16[R_IO_H]) -#define RSCAN0TMDF165HL (RSCAN0.TMDF165.UINT8[R_IO_HL]) -#define RSCAN0TMDF165HH (RSCAN0.TMDF165.UINT8[R_IO_HH]) -#define RSCAN0TMID66 (RSCAN0.TMID66.UINT32) -#define RSCAN0TMID66L (RSCAN0.TMID66.UINT16[R_IO_L]) -#define RSCAN0TMID66LL (RSCAN0.TMID66.UINT8[R_IO_LL]) -#define RSCAN0TMID66LH (RSCAN0.TMID66.UINT8[R_IO_LH]) -#define RSCAN0TMID66H (RSCAN0.TMID66.UINT16[R_IO_H]) -#define RSCAN0TMID66HL (RSCAN0.TMID66.UINT8[R_IO_HL]) -#define RSCAN0TMID66HH (RSCAN0.TMID66.UINT8[R_IO_HH]) -#define RSCAN0TMPTR66 (RSCAN0.TMPTR66.UINT32) -#define RSCAN0TMPTR66L (RSCAN0.TMPTR66.UINT16[R_IO_L]) -#define RSCAN0TMPTR66LL (RSCAN0.TMPTR66.UINT8[R_IO_LL]) -#define RSCAN0TMPTR66LH (RSCAN0.TMPTR66.UINT8[R_IO_LH]) -#define RSCAN0TMPTR66H (RSCAN0.TMPTR66.UINT16[R_IO_H]) -#define RSCAN0TMPTR66HL (RSCAN0.TMPTR66.UINT8[R_IO_HL]) -#define RSCAN0TMPTR66HH (RSCAN0.TMPTR66.UINT8[R_IO_HH]) -#define RSCAN0TMDF066 (RSCAN0.TMDF066.UINT32) -#define RSCAN0TMDF066L (RSCAN0.TMDF066.UINT16[R_IO_L]) -#define RSCAN0TMDF066LL (RSCAN0.TMDF066.UINT8[R_IO_LL]) -#define RSCAN0TMDF066LH (RSCAN0.TMDF066.UINT8[R_IO_LH]) -#define RSCAN0TMDF066H (RSCAN0.TMDF066.UINT16[R_IO_H]) -#define RSCAN0TMDF066HL (RSCAN0.TMDF066.UINT8[R_IO_HL]) -#define RSCAN0TMDF066HH (RSCAN0.TMDF066.UINT8[R_IO_HH]) -#define RSCAN0TMDF166 (RSCAN0.TMDF166.UINT32) -#define RSCAN0TMDF166L (RSCAN0.TMDF166.UINT16[R_IO_L]) -#define RSCAN0TMDF166LL (RSCAN0.TMDF166.UINT8[R_IO_LL]) -#define RSCAN0TMDF166LH (RSCAN0.TMDF166.UINT8[R_IO_LH]) -#define RSCAN0TMDF166H (RSCAN0.TMDF166.UINT16[R_IO_H]) -#define RSCAN0TMDF166HL (RSCAN0.TMDF166.UINT8[R_IO_HL]) -#define RSCAN0TMDF166HH (RSCAN0.TMDF166.UINT8[R_IO_HH]) -#define RSCAN0TMID67 (RSCAN0.TMID67.UINT32) -#define RSCAN0TMID67L (RSCAN0.TMID67.UINT16[R_IO_L]) -#define RSCAN0TMID67LL (RSCAN0.TMID67.UINT8[R_IO_LL]) -#define RSCAN0TMID67LH (RSCAN0.TMID67.UINT8[R_IO_LH]) -#define RSCAN0TMID67H (RSCAN0.TMID67.UINT16[R_IO_H]) -#define RSCAN0TMID67HL (RSCAN0.TMID67.UINT8[R_IO_HL]) -#define RSCAN0TMID67HH (RSCAN0.TMID67.UINT8[R_IO_HH]) -#define RSCAN0TMPTR67 (RSCAN0.TMPTR67.UINT32) -#define RSCAN0TMPTR67L (RSCAN0.TMPTR67.UINT16[R_IO_L]) -#define RSCAN0TMPTR67LL (RSCAN0.TMPTR67.UINT8[R_IO_LL]) -#define RSCAN0TMPTR67LH (RSCAN0.TMPTR67.UINT8[R_IO_LH]) -#define RSCAN0TMPTR67H (RSCAN0.TMPTR67.UINT16[R_IO_H]) -#define RSCAN0TMPTR67HL (RSCAN0.TMPTR67.UINT8[R_IO_HL]) -#define RSCAN0TMPTR67HH (RSCAN0.TMPTR67.UINT8[R_IO_HH]) -#define RSCAN0TMDF067 (RSCAN0.TMDF067.UINT32) -#define RSCAN0TMDF067L (RSCAN0.TMDF067.UINT16[R_IO_L]) -#define RSCAN0TMDF067LL (RSCAN0.TMDF067.UINT8[R_IO_LL]) -#define RSCAN0TMDF067LH (RSCAN0.TMDF067.UINT8[R_IO_LH]) -#define RSCAN0TMDF067H (RSCAN0.TMDF067.UINT16[R_IO_H]) -#define RSCAN0TMDF067HL (RSCAN0.TMDF067.UINT8[R_IO_HL]) -#define RSCAN0TMDF067HH (RSCAN0.TMDF067.UINT8[R_IO_HH]) -#define RSCAN0TMDF167 (RSCAN0.TMDF167.UINT32) -#define RSCAN0TMDF167L (RSCAN0.TMDF167.UINT16[R_IO_L]) -#define RSCAN0TMDF167LL (RSCAN0.TMDF167.UINT8[R_IO_LL]) -#define RSCAN0TMDF167LH (RSCAN0.TMDF167.UINT8[R_IO_LH]) -#define RSCAN0TMDF167H (RSCAN0.TMDF167.UINT16[R_IO_H]) -#define RSCAN0TMDF167HL (RSCAN0.TMDF167.UINT8[R_IO_HL]) -#define RSCAN0TMDF167HH (RSCAN0.TMDF167.UINT8[R_IO_HH]) -#define RSCAN0TMID68 (RSCAN0.TMID68.UINT32) -#define RSCAN0TMID68L (RSCAN0.TMID68.UINT16[R_IO_L]) -#define RSCAN0TMID68LL (RSCAN0.TMID68.UINT8[R_IO_LL]) -#define RSCAN0TMID68LH (RSCAN0.TMID68.UINT8[R_IO_LH]) -#define RSCAN0TMID68H (RSCAN0.TMID68.UINT16[R_IO_H]) -#define RSCAN0TMID68HL (RSCAN0.TMID68.UINT8[R_IO_HL]) -#define RSCAN0TMID68HH (RSCAN0.TMID68.UINT8[R_IO_HH]) -#define RSCAN0TMPTR68 (RSCAN0.TMPTR68.UINT32) -#define RSCAN0TMPTR68L (RSCAN0.TMPTR68.UINT16[R_IO_L]) -#define RSCAN0TMPTR68LL (RSCAN0.TMPTR68.UINT8[R_IO_LL]) -#define RSCAN0TMPTR68LH (RSCAN0.TMPTR68.UINT8[R_IO_LH]) -#define RSCAN0TMPTR68H (RSCAN0.TMPTR68.UINT16[R_IO_H]) -#define RSCAN0TMPTR68HL (RSCAN0.TMPTR68.UINT8[R_IO_HL]) -#define RSCAN0TMPTR68HH (RSCAN0.TMPTR68.UINT8[R_IO_HH]) -#define RSCAN0TMDF068 (RSCAN0.TMDF068.UINT32) -#define RSCAN0TMDF068L (RSCAN0.TMDF068.UINT16[R_IO_L]) -#define RSCAN0TMDF068LL (RSCAN0.TMDF068.UINT8[R_IO_LL]) -#define RSCAN0TMDF068LH (RSCAN0.TMDF068.UINT8[R_IO_LH]) -#define RSCAN0TMDF068H (RSCAN0.TMDF068.UINT16[R_IO_H]) -#define RSCAN0TMDF068HL (RSCAN0.TMDF068.UINT8[R_IO_HL]) -#define RSCAN0TMDF068HH (RSCAN0.TMDF068.UINT8[R_IO_HH]) -#define RSCAN0TMDF168 (RSCAN0.TMDF168.UINT32) -#define RSCAN0TMDF168L (RSCAN0.TMDF168.UINT16[R_IO_L]) -#define RSCAN0TMDF168LL (RSCAN0.TMDF168.UINT8[R_IO_LL]) -#define RSCAN0TMDF168LH (RSCAN0.TMDF168.UINT8[R_IO_LH]) -#define RSCAN0TMDF168H (RSCAN0.TMDF168.UINT16[R_IO_H]) -#define RSCAN0TMDF168HL (RSCAN0.TMDF168.UINT8[R_IO_HL]) -#define RSCAN0TMDF168HH (RSCAN0.TMDF168.UINT8[R_IO_HH]) -#define RSCAN0TMID69 (RSCAN0.TMID69.UINT32) -#define RSCAN0TMID69L (RSCAN0.TMID69.UINT16[R_IO_L]) -#define RSCAN0TMID69LL (RSCAN0.TMID69.UINT8[R_IO_LL]) -#define RSCAN0TMID69LH (RSCAN0.TMID69.UINT8[R_IO_LH]) -#define RSCAN0TMID69H (RSCAN0.TMID69.UINT16[R_IO_H]) -#define RSCAN0TMID69HL (RSCAN0.TMID69.UINT8[R_IO_HL]) -#define RSCAN0TMID69HH (RSCAN0.TMID69.UINT8[R_IO_HH]) -#define RSCAN0TMPTR69 (RSCAN0.TMPTR69.UINT32) -#define RSCAN0TMPTR69L (RSCAN0.TMPTR69.UINT16[R_IO_L]) -#define RSCAN0TMPTR69LL (RSCAN0.TMPTR69.UINT8[R_IO_LL]) -#define RSCAN0TMPTR69LH (RSCAN0.TMPTR69.UINT8[R_IO_LH]) -#define RSCAN0TMPTR69H (RSCAN0.TMPTR69.UINT16[R_IO_H]) -#define RSCAN0TMPTR69HL (RSCAN0.TMPTR69.UINT8[R_IO_HL]) -#define RSCAN0TMPTR69HH (RSCAN0.TMPTR69.UINT8[R_IO_HH]) -#define RSCAN0TMDF069 (RSCAN0.TMDF069.UINT32) -#define RSCAN0TMDF069L (RSCAN0.TMDF069.UINT16[R_IO_L]) -#define RSCAN0TMDF069LL (RSCAN0.TMDF069.UINT8[R_IO_LL]) -#define RSCAN0TMDF069LH (RSCAN0.TMDF069.UINT8[R_IO_LH]) -#define RSCAN0TMDF069H (RSCAN0.TMDF069.UINT16[R_IO_H]) -#define RSCAN0TMDF069HL (RSCAN0.TMDF069.UINT8[R_IO_HL]) -#define RSCAN0TMDF069HH (RSCAN0.TMDF069.UINT8[R_IO_HH]) -#define RSCAN0TMDF169 (RSCAN0.TMDF169.UINT32) -#define RSCAN0TMDF169L (RSCAN0.TMDF169.UINT16[R_IO_L]) -#define RSCAN0TMDF169LL (RSCAN0.TMDF169.UINT8[R_IO_LL]) -#define RSCAN0TMDF169LH (RSCAN0.TMDF169.UINT8[R_IO_LH]) -#define RSCAN0TMDF169H (RSCAN0.TMDF169.UINT16[R_IO_H]) -#define RSCAN0TMDF169HL (RSCAN0.TMDF169.UINT8[R_IO_HL]) -#define RSCAN0TMDF169HH (RSCAN0.TMDF169.UINT8[R_IO_HH]) -#define RSCAN0TMID70 (RSCAN0.TMID70.UINT32) -#define RSCAN0TMID70L (RSCAN0.TMID70.UINT16[R_IO_L]) -#define RSCAN0TMID70LL (RSCAN0.TMID70.UINT8[R_IO_LL]) -#define RSCAN0TMID70LH (RSCAN0.TMID70.UINT8[R_IO_LH]) -#define RSCAN0TMID70H (RSCAN0.TMID70.UINT16[R_IO_H]) -#define RSCAN0TMID70HL (RSCAN0.TMID70.UINT8[R_IO_HL]) -#define RSCAN0TMID70HH (RSCAN0.TMID70.UINT8[R_IO_HH]) -#define RSCAN0TMPTR70 (RSCAN0.TMPTR70.UINT32) -#define RSCAN0TMPTR70L (RSCAN0.TMPTR70.UINT16[R_IO_L]) -#define RSCAN0TMPTR70LL (RSCAN0.TMPTR70.UINT8[R_IO_LL]) -#define RSCAN0TMPTR70LH (RSCAN0.TMPTR70.UINT8[R_IO_LH]) -#define RSCAN0TMPTR70H (RSCAN0.TMPTR70.UINT16[R_IO_H]) -#define RSCAN0TMPTR70HL (RSCAN0.TMPTR70.UINT8[R_IO_HL]) -#define RSCAN0TMPTR70HH (RSCAN0.TMPTR70.UINT8[R_IO_HH]) -#define RSCAN0TMDF070 (RSCAN0.TMDF070.UINT32) -#define RSCAN0TMDF070L (RSCAN0.TMDF070.UINT16[R_IO_L]) -#define RSCAN0TMDF070LL (RSCAN0.TMDF070.UINT8[R_IO_LL]) -#define RSCAN0TMDF070LH (RSCAN0.TMDF070.UINT8[R_IO_LH]) -#define RSCAN0TMDF070H (RSCAN0.TMDF070.UINT16[R_IO_H]) -#define RSCAN0TMDF070HL (RSCAN0.TMDF070.UINT8[R_IO_HL]) -#define RSCAN0TMDF070HH (RSCAN0.TMDF070.UINT8[R_IO_HH]) -#define RSCAN0TMDF170 (RSCAN0.TMDF170.UINT32) -#define RSCAN0TMDF170L (RSCAN0.TMDF170.UINT16[R_IO_L]) -#define RSCAN0TMDF170LL (RSCAN0.TMDF170.UINT8[R_IO_LL]) -#define RSCAN0TMDF170LH (RSCAN0.TMDF170.UINT8[R_IO_LH]) -#define RSCAN0TMDF170H (RSCAN0.TMDF170.UINT16[R_IO_H]) -#define RSCAN0TMDF170HL (RSCAN0.TMDF170.UINT8[R_IO_HL]) -#define RSCAN0TMDF170HH (RSCAN0.TMDF170.UINT8[R_IO_HH]) -#define RSCAN0TMID71 (RSCAN0.TMID71.UINT32) -#define RSCAN0TMID71L (RSCAN0.TMID71.UINT16[R_IO_L]) -#define RSCAN0TMID71LL (RSCAN0.TMID71.UINT8[R_IO_LL]) -#define RSCAN0TMID71LH (RSCAN0.TMID71.UINT8[R_IO_LH]) -#define RSCAN0TMID71H (RSCAN0.TMID71.UINT16[R_IO_H]) -#define RSCAN0TMID71HL (RSCAN0.TMID71.UINT8[R_IO_HL]) -#define RSCAN0TMID71HH (RSCAN0.TMID71.UINT8[R_IO_HH]) -#define RSCAN0TMPTR71 (RSCAN0.TMPTR71.UINT32) -#define RSCAN0TMPTR71L (RSCAN0.TMPTR71.UINT16[R_IO_L]) -#define RSCAN0TMPTR71LL (RSCAN0.TMPTR71.UINT8[R_IO_LL]) -#define RSCAN0TMPTR71LH (RSCAN0.TMPTR71.UINT8[R_IO_LH]) -#define RSCAN0TMPTR71H (RSCAN0.TMPTR71.UINT16[R_IO_H]) -#define RSCAN0TMPTR71HL (RSCAN0.TMPTR71.UINT8[R_IO_HL]) -#define RSCAN0TMPTR71HH (RSCAN0.TMPTR71.UINT8[R_IO_HH]) -#define RSCAN0TMDF071 (RSCAN0.TMDF071.UINT32) -#define RSCAN0TMDF071L (RSCAN0.TMDF071.UINT16[R_IO_L]) -#define RSCAN0TMDF071LL (RSCAN0.TMDF071.UINT8[R_IO_LL]) -#define RSCAN0TMDF071LH (RSCAN0.TMDF071.UINT8[R_IO_LH]) -#define RSCAN0TMDF071H (RSCAN0.TMDF071.UINT16[R_IO_H]) -#define RSCAN0TMDF071HL (RSCAN0.TMDF071.UINT8[R_IO_HL]) -#define RSCAN0TMDF071HH (RSCAN0.TMDF071.UINT8[R_IO_HH]) -#define RSCAN0TMDF171 (RSCAN0.TMDF171.UINT32) -#define RSCAN0TMDF171L (RSCAN0.TMDF171.UINT16[R_IO_L]) -#define RSCAN0TMDF171LL (RSCAN0.TMDF171.UINT8[R_IO_LL]) -#define RSCAN0TMDF171LH (RSCAN0.TMDF171.UINT8[R_IO_LH]) -#define RSCAN0TMDF171H (RSCAN0.TMDF171.UINT16[R_IO_H]) -#define RSCAN0TMDF171HL (RSCAN0.TMDF171.UINT8[R_IO_HL]) -#define RSCAN0TMDF171HH (RSCAN0.TMDF171.UINT8[R_IO_HH]) -#define RSCAN0TMID72 (RSCAN0.TMID72.UINT32) -#define RSCAN0TMID72L (RSCAN0.TMID72.UINT16[R_IO_L]) -#define RSCAN0TMID72LL (RSCAN0.TMID72.UINT8[R_IO_LL]) -#define RSCAN0TMID72LH (RSCAN0.TMID72.UINT8[R_IO_LH]) -#define RSCAN0TMID72H (RSCAN0.TMID72.UINT16[R_IO_H]) -#define RSCAN0TMID72HL (RSCAN0.TMID72.UINT8[R_IO_HL]) -#define RSCAN0TMID72HH (RSCAN0.TMID72.UINT8[R_IO_HH]) -#define RSCAN0TMPTR72 (RSCAN0.TMPTR72.UINT32) -#define RSCAN0TMPTR72L (RSCAN0.TMPTR72.UINT16[R_IO_L]) -#define RSCAN0TMPTR72LL (RSCAN0.TMPTR72.UINT8[R_IO_LL]) -#define RSCAN0TMPTR72LH (RSCAN0.TMPTR72.UINT8[R_IO_LH]) -#define RSCAN0TMPTR72H (RSCAN0.TMPTR72.UINT16[R_IO_H]) -#define RSCAN0TMPTR72HL (RSCAN0.TMPTR72.UINT8[R_IO_HL]) -#define RSCAN0TMPTR72HH (RSCAN0.TMPTR72.UINT8[R_IO_HH]) -#define RSCAN0TMDF072 (RSCAN0.TMDF072.UINT32) -#define RSCAN0TMDF072L (RSCAN0.TMDF072.UINT16[R_IO_L]) -#define RSCAN0TMDF072LL (RSCAN0.TMDF072.UINT8[R_IO_LL]) -#define RSCAN0TMDF072LH (RSCAN0.TMDF072.UINT8[R_IO_LH]) -#define RSCAN0TMDF072H (RSCAN0.TMDF072.UINT16[R_IO_H]) -#define RSCAN0TMDF072HL (RSCAN0.TMDF072.UINT8[R_IO_HL]) -#define RSCAN0TMDF072HH (RSCAN0.TMDF072.UINT8[R_IO_HH]) -#define RSCAN0TMDF172 (RSCAN0.TMDF172.UINT32) -#define RSCAN0TMDF172L (RSCAN0.TMDF172.UINT16[R_IO_L]) -#define RSCAN0TMDF172LL (RSCAN0.TMDF172.UINT8[R_IO_LL]) -#define RSCAN0TMDF172LH (RSCAN0.TMDF172.UINT8[R_IO_LH]) -#define RSCAN0TMDF172H (RSCAN0.TMDF172.UINT16[R_IO_H]) -#define RSCAN0TMDF172HL (RSCAN0.TMDF172.UINT8[R_IO_HL]) -#define RSCAN0TMDF172HH (RSCAN0.TMDF172.UINT8[R_IO_HH]) -#define RSCAN0TMID73 (RSCAN0.TMID73.UINT32) -#define RSCAN0TMID73L (RSCAN0.TMID73.UINT16[R_IO_L]) -#define RSCAN0TMID73LL (RSCAN0.TMID73.UINT8[R_IO_LL]) -#define RSCAN0TMID73LH (RSCAN0.TMID73.UINT8[R_IO_LH]) -#define RSCAN0TMID73H (RSCAN0.TMID73.UINT16[R_IO_H]) -#define RSCAN0TMID73HL (RSCAN0.TMID73.UINT8[R_IO_HL]) -#define RSCAN0TMID73HH (RSCAN0.TMID73.UINT8[R_IO_HH]) -#define RSCAN0TMPTR73 (RSCAN0.TMPTR73.UINT32) -#define RSCAN0TMPTR73L (RSCAN0.TMPTR73.UINT16[R_IO_L]) -#define RSCAN0TMPTR73LL (RSCAN0.TMPTR73.UINT8[R_IO_LL]) -#define RSCAN0TMPTR73LH (RSCAN0.TMPTR73.UINT8[R_IO_LH]) -#define RSCAN0TMPTR73H (RSCAN0.TMPTR73.UINT16[R_IO_H]) -#define RSCAN0TMPTR73HL (RSCAN0.TMPTR73.UINT8[R_IO_HL]) -#define RSCAN0TMPTR73HH (RSCAN0.TMPTR73.UINT8[R_IO_HH]) -#define RSCAN0TMDF073 (RSCAN0.TMDF073.UINT32) -#define RSCAN0TMDF073L (RSCAN0.TMDF073.UINT16[R_IO_L]) -#define RSCAN0TMDF073LL (RSCAN0.TMDF073.UINT8[R_IO_LL]) -#define RSCAN0TMDF073LH (RSCAN0.TMDF073.UINT8[R_IO_LH]) -#define RSCAN0TMDF073H (RSCAN0.TMDF073.UINT16[R_IO_H]) -#define RSCAN0TMDF073HL (RSCAN0.TMDF073.UINT8[R_IO_HL]) -#define RSCAN0TMDF073HH (RSCAN0.TMDF073.UINT8[R_IO_HH]) -#define RSCAN0TMDF173 (RSCAN0.TMDF173.UINT32) -#define RSCAN0TMDF173L (RSCAN0.TMDF173.UINT16[R_IO_L]) -#define RSCAN0TMDF173LL (RSCAN0.TMDF173.UINT8[R_IO_LL]) -#define RSCAN0TMDF173LH (RSCAN0.TMDF173.UINT8[R_IO_LH]) -#define RSCAN0TMDF173H (RSCAN0.TMDF173.UINT16[R_IO_H]) -#define RSCAN0TMDF173HL (RSCAN0.TMDF173.UINT8[R_IO_HL]) -#define RSCAN0TMDF173HH (RSCAN0.TMDF173.UINT8[R_IO_HH]) -#define RSCAN0TMID74 (RSCAN0.TMID74.UINT32) -#define RSCAN0TMID74L (RSCAN0.TMID74.UINT16[R_IO_L]) -#define RSCAN0TMID74LL (RSCAN0.TMID74.UINT8[R_IO_LL]) -#define RSCAN0TMID74LH (RSCAN0.TMID74.UINT8[R_IO_LH]) -#define RSCAN0TMID74H (RSCAN0.TMID74.UINT16[R_IO_H]) -#define RSCAN0TMID74HL (RSCAN0.TMID74.UINT8[R_IO_HL]) -#define RSCAN0TMID74HH (RSCAN0.TMID74.UINT8[R_IO_HH]) -#define RSCAN0TMPTR74 (RSCAN0.TMPTR74.UINT32) -#define RSCAN0TMPTR74L (RSCAN0.TMPTR74.UINT16[R_IO_L]) -#define RSCAN0TMPTR74LL (RSCAN0.TMPTR74.UINT8[R_IO_LL]) -#define RSCAN0TMPTR74LH (RSCAN0.TMPTR74.UINT8[R_IO_LH]) -#define RSCAN0TMPTR74H (RSCAN0.TMPTR74.UINT16[R_IO_H]) -#define RSCAN0TMPTR74HL (RSCAN0.TMPTR74.UINT8[R_IO_HL]) -#define RSCAN0TMPTR74HH (RSCAN0.TMPTR74.UINT8[R_IO_HH]) -#define RSCAN0TMDF074 (RSCAN0.TMDF074.UINT32) -#define RSCAN0TMDF074L (RSCAN0.TMDF074.UINT16[R_IO_L]) -#define RSCAN0TMDF074LL (RSCAN0.TMDF074.UINT8[R_IO_LL]) -#define RSCAN0TMDF074LH (RSCAN0.TMDF074.UINT8[R_IO_LH]) -#define RSCAN0TMDF074H (RSCAN0.TMDF074.UINT16[R_IO_H]) -#define RSCAN0TMDF074HL (RSCAN0.TMDF074.UINT8[R_IO_HL]) -#define RSCAN0TMDF074HH (RSCAN0.TMDF074.UINT8[R_IO_HH]) -#define RSCAN0TMDF174 (RSCAN0.TMDF174.UINT32) -#define RSCAN0TMDF174L (RSCAN0.TMDF174.UINT16[R_IO_L]) -#define RSCAN0TMDF174LL (RSCAN0.TMDF174.UINT8[R_IO_LL]) -#define RSCAN0TMDF174LH (RSCAN0.TMDF174.UINT8[R_IO_LH]) -#define RSCAN0TMDF174H (RSCAN0.TMDF174.UINT16[R_IO_H]) -#define RSCAN0TMDF174HL (RSCAN0.TMDF174.UINT8[R_IO_HL]) -#define RSCAN0TMDF174HH (RSCAN0.TMDF174.UINT8[R_IO_HH]) -#define RSCAN0TMID75 (RSCAN0.TMID75.UINT32) -#define RSCAN0TMID75L (RSCAN0.TMID75.UINT16[R_IO_L]) -#define RSCAN0TMID75LL (RSCAN0.TMID75.UINT8[R_IO_LL]) -#define RSCAN0TMID75LH (RSCAN0.TMID75.UINT8[R_IO_LH]) -#define RSCAN0TMID75H (RSCAN0.TMID75.UINT16[R_IO_H]) -#define RSCAN0TMID75HL (RSCAN0.TMID75.UINT8[R_IO_HL]) -#define RSCAN0TMID75HH (RSCAN0.TMID75.UINT8[R_IO_HH]) -#define RSCAN0TMPTR75 (RSCAN0.TMPTR75.UINT32) -#define RSCAN0TMPTR75L (RSCAN0.TMPTR75.UINT16[R_IO_L]) -#define RSCAN0TMPTR75LL (RSCAN0.TMPTR75.UINT8[R_IO_LL]) -#define RSCAN0TMPTR75LH (RSCAN0.TMPTR75.UINT8[R_IO_LH]) -#define RSCAN0TMPTR75H (RSCAN0.TMPTR75.UINT16[R_IO_H]) -#define RSCAN0TMPTR75HL (RSCAN0.TMPTR75.UINT8[R_IO_HL]) -#define RSCAN0TMPTR75HH (RSCAN0.TMPTR75.UINT8[R_IO_HH]) -#define RSCAN0TMDF075 (RSCAN0.TMDF075.UINT32) -#define RSCAN0TMDF075L (RSCAN0.TMDF075.UINT16[R_IO_L]) -#define RSCAN0TMDF075LL (RSCAN0.TMDF075.UINT8[R_IO_LL]) -#define RSCAN0TMDF075LH (RSCAN0.TMDF075.UINT8[R_IO_LH]) -#define RSCAN0TMDF075H (RSCAN0.TMDF075.UINT16[R_IO_H]) -#define RSCAN0TMDF075HL (RSCAN0.TMDF075.UINT8[R_IO_HL]) -#define RSCAN0TMDF075HH (RSCAN0.TMDF075.UINT8[R_IO_HH]) -#define RSCAN0TMDF175 (RSCAN0.TMDF175.UINT32) -#define RSCAN0TMDF175L (RSCAN0.TMDF175.UINT16[R_IO_L]) -#define RSCAN0TMDF175LL (RSCAN0.TMDF175.UINT8[R_IO_LL]) -#define RSCAN0TMDF175LH (RSCAN0.TMDF175.UINT8[R_IO_LH]) -#define RSCAN0TMDF175H (RSCAN0.TMDF175.UINT16[R_IO_H]) -#define RSCAN0TMDF175HL (RSCAN0.TMDF175.UINT8[R_IO_HL]) -#define RSCAN0TMDF175HH (RSCAN0.TMDF175.UINT8[R_IO_HH]) -#define RSCAN0TMID76 (RSCAN0.TMID76.UINT32) -#define RSCAN0TMID76L (RSCAN0.TMID76.UINT16[R_IO_L]) -#define RSCAN0TMID76LL (RSCAN0.TMID76.UINT8[R_IO_LL]) -#define RSCAN0TMID76LH (RSCAN0.TMID76.UINT8[R_IO_LH]) -#define RSCAN0TMID76H (RSCAN0.TMID76.UINT16[R_IO_H]) -#define RSCAN0TMID76HL (RSCAN0.TMID76.UINT8[R_IO_HL]) -#define RSCAN0TMID76HH (RSCAN0.TMID76.UINT8[R_IO_HH]) -#define RSCAN0TMPTR76 (RSCAN0.TMPTR76.UINT32) -#define RSCAN0TMPTR76L (RSCAN0.TMPTR76.UINT16[R_IO_L]) -#define RSCAN0TMPTR76LL (RSCAN0.TMPTR76.UINT8[R_IO_LL]) -#define RSCAN0TMPTR76LH (RSCAN0.TMPTR76.UINT8[R_IO_LH]) -#define RSCAN0TMPTR76H (RSCAN0.TMPTR76.UINT16[R_IO_H]) -#define RSCAN0TMPTR76HL (RSCAN0.TMPTR76.UINT8[R_IO_HL]) -#define RSCAN0TMPTR76HH (RSCAN0.TMPTR76.UINT8[R_IO_HH]) -#define RSCAN0TMDF076 (RSCAN0.TMDF076.UINT32) -#define RSCAN0TMDF076L (RSCAN0.TMDF076.UINT16[R_IO_L]) -#define RSCAN0TMDF076LL (RSCAN0.TMDF076.UINT8[R_IO_LL]) -#define RSCAN0TMDF076LH (RSCAN0.TMDF076.UINT8[R_IO_LH]) -#define RSCAN0TMDF076H (RSCAN0.TMDF076.UINT16[R_IO_H]) -#define RSCAN0TMDF076HL (RSCAN0.TMDF076.UINT8[R_IO_HL]) -#define RSCAN0TMDF076HH (RSCAN0.TMDF076.UINT8[R_IO_HH]) -#define RSCAN0TMDF176 (RSCAN0.TMDF176.UINT32) -#define RSCAN0TMDF176L (RSCAN0.TMDF176.UINT16[R_IO_L]) -#define RSCAN0TMDF176LL (RSCAN0.TMDF176.UINT8[R_IO_LL]) -#define RSCAN0TMDF176LH (RSCAN0.TMDF176.UINT8[R_IO_LH]) -#define RSCAN0TMDF176H (RSCAN0.TMDF176.UINT16[R_IO_H]) -#define RSCAN0TMDF176HL (RSCAN0.TMDF176.UINT8[R_IO_HL]) -#define RSCAN0TMDF176HH (RSCAN0.TMDF176.UINT8[R_IO_HH]) -#define RSCAN0TMID77 (RSCAN0.TMID77.UINT32) -#define RSCAN0TMID77L (RSCAN0.TMID77.UINT16[R_IO_L]) -#define RSCAN0TMID77LL (RSCAN0.TMID77.UINT8[R_IO_LL]) -#define RSCAN0TMID77LH (RSCAN0.TMID77.UINT8[R_IO_LH]) -#define RSCAN0TMID77H (RSCAN0.TMID77.UINT16[R_IO_H]) -#define RSCAN0TMID77HL (RSCAN0.TMID77.UINT8[R_IO_HL]) -#define RSCAN0TMID77HH (RSCAN0.TMID77.UINT8[R_IO_HH]) -#define RSCAN0TMPTR77 (RSCAN0.TMPTR77.UINT32) -#define RSCAN0TMPTR77L (RSCAN0.TMPTR77.UINT16[R_IO_L]) -#define RSCAN0TMPTR77LL (RSCAN0.TMPTR77.UINT8[R_IO_LL]) -#define RSCAN0TMPTR77LH (RSCAN0.TMPTR77.UINT8[R_IO_LH]) -#define RSCAN0TMPTR77H (RSCAN0.TMPTR77.UINT16[R_IO_H]) -#define RSCAN0TMPTR77HL (RSCAN0.TMPTR77.UINT8[R_IO_HL]) -#define RSCAN0TMPTR77HH (RSCAN0.TMPTR77.UINT8[R_IO_HH]) -#define RSCAN0TMDF077 (RSCAN0.TMDF077.UINT32) -#define RSCAN0TMDF077L (RSCAN0.TMDF077.UINT16[R_IO_L]) -#define RSCAN0TMDF077LL (RSCAN0.TMDF077.UINT8[R_IO_LL]) -#define RSCAN0TMDF077LH (RSCAN0.TMDF077.UINT8[R_IO_LH]) -#define RSCAN0TMDF077H (RSCAN0.TMDF077.UINT16[R_IO_H]) -#define RSCAN0TMDF077HL (RSCAN0.TMDF077.UINT8[R_IO_HL]) -#define RSCAN0TMDF077HH (RSCAN0.TMDF077.UINT8[R_IO_HH]) -#define RSCAN0TMDF177 (RSCAN0.TMDF177.UINT32) -#define RSCAN0TMDF177L (RSCAN0.TMDF177.UINT16[R_IO_L]) -#define RSCAN0TMDF177LL (RSCAN0.TMDF177.UINT8[R_IO_LL]) -#define RSCAN0TMDF177LH (RSCAN0.TMDF177.UINT8[R_IO_LH]) -#define RSCAN0TMDF177H (RSCAN0.TMDF177.UINT16[R_IO_H]) -#define RSCAN0TMDF177HL (RSCAN0.TMDF177.UINT8[R_IO_HL]) -#define RSCAN0TMDF177HH (RSCAN0.TMDF177.UINT8[R_IO_HH]) -#define RSCAN0TMID78 (RSCAN0.TMID78.UINT32) -#define RSCAN0TMID78L (RSCAN0.TMID78.UINT16[R_IO_L]) -#define RSCAN0TMID78LL (RSCAN0.TMID78.UINT8[R_IO_LL]) -#define RSCAN0TMID78LH (RSCAN0.TMID78.UINT8[R_IO_LH]) -#define RSCAN0TMID78H (RSCAN0.TMID78.UINT16[R_IO_H]) -#define RSCAN0TMID78HL (RSCAN0.TMID78.UINT8[R_IO_HL]) -#define RSCAN0TMID78HH (RSCAN0.TMID78.UINT8[R_IO_HH]) -#define RSCAN0TMPTR78 (RSCAN0.TMPTR78.UINT32) -#define RSCAN0TMPTR78L (RSCAN0.TMPTR78.UINT16[R_IO_L]) -#define RSCAN0TMPTR78LL (RSCAN0.TMPTR78.UINT8[R_IO_LL]) -#define RSCAN0TMPTR78LH (RSCAN0.TMPTR78.UINT8[R_IO_LH]) -#define RSCAN0TMPTR78H (RSCAN0.TMPTR78.UINT16[R_IO_H]) -#define RSCAN0TMPTR78HL (RSCAN0.TMPTR78.UINT8[R_IO_HL]) -#define RSCAN0TMPTR78HH (RSCAN0.TMPTR78.UINT8[R_IO_HH]) -#define RSCAN0TMDF078 (RSCAN0.TMDF078.UINT32) -#define RSCAN0TMDF078L (RSCAN0.TMDF078.UINT16[R_IO_L]) -#define RSCAN0TMDF078LL (RSCAN0.TMDF078.UINT8[R_IO_LL]) -#define RSCAN0TMDF078LH (RSCAN0.TMDF078.UINT8[R_IO_LH]) -#define RSCAN0TMDF078H (RSCAN0.TMDF078.UINT16[R_IO_H]) -#define RSCAN0TMDF078HL (RSCAN0.TMDF078.UINT8[R_IO_HL]) -#define RSCAN0TMDF078HH (RSCAN0.TMDF078.UINT8[R_IO_HH]) -#define RSCAN0TMDF178 (RSCAN0.TMDF178.UINT32) -#define RSCAN0TMDF178L (RSCAN0.TMDF178.UINT16[R_IO_L]) -#define RSCAN0TMDF178LL (RSCAN0.TMDF178.UINT8[R_IO_LL]) -#define RSCAN0TMDF178LH (RSCAN0.TMDF178.UINT8[R_IO_LH]) -#define RSCAN0TMDF178H (RSCAN0.TMDF178.UINT16[R_IO_H]) -#define RSCAN0TMDF178HL (RSCAN0.TMDF178.UINT8[R_IO_HL]) -#define RSCAN0TMDF178HH (RSCAN0.TMDF178.UINT8[R_IO_HH]) -#define RSCAN0TMID79 (RSCAN0.TMID79.UINT32) -#define RSCAN0TMID79L (RSCAN0.TMID79.UINT16[R_IO_L]) -#define RSCAN0TMID79LL (RSCAN0.TMID79.UINT8[R_IO_LL]) -#define RSCAN0TMID79LH (RSCAN0.TMID79.UINT8[R_IO_LH]) -#define RSCAN0TMID79H (RSCAN0.TMID79.UINT16[R_IO_H]) -#define RSCAN0TMID79HL (RSCAN0.TMID79.UINT8[R_IO_HL]) -#define RSCAN0TMID79HH (RSCAN0.TMID79.UINT8[R_IO_HH]) -#define RSCAN0TMPTR79 (RSCAN0.TMPTR79.UINT32) -#define RSCAN0TMPTR79L (RSCAN0.TMPTR79.UINT16[R_IO_L]) -#define RSCAN0TMPTR79LL (RSCAN0.TMPTR79.UINT8[R_IO_LL]) -#define RSCAN0TMPTR79LH (RSCAN0.TMPTR79.UINT8[R_IO_LH]) -#define RSCAN0TMPTR79H (RSCAN0.TMPTR79.UINT16[R_IO_H]) -#define RSCAN0TMPTR79HL (RSCAN0.TMPTR79.UINT8[R_IO_HL]) -#define RSCAN0TMPTR79HH (RSCAN0.TMPTR79.UINT8[R_IO_HH]) -#define RSCAN0TMDF079 (RSCAN0.TMDF079.UINT32) -#define RSCAN0TMDF079L (RSCAN0.TMDF079.UINT16[R_IO_L]) -#define RSCAN0TMDF079LL (RSCAN0.TMDF079.UINT8[R_IO_LL]) -#define RSCAN0TMDF079LH (RSCAN0.TMDF079.UINT8[R_IO_LH]) -#define RSCAN0TMDF079H (RSCAN0.TMDF079.UINT16[R_IO_H]) -#define RSCAN0TMDF079HL (RSCAN0.TMDF079.UINT8[R_IO_HL]) -#define RSCAN0TMDF079HH (RSCAN0.TMDF079.UINT8[R_IO_HH]) -#define RSCAN0TMDF179 (RSCAN0.TMDF179.UINT32) -#define RSCAN0TMDF179L (RSCAN0.TMDF179.UINT16[R_IO_L]) -#define RSCAN0TMDF179LL (RSCAN0.TMDF179.UINT8[R_IO_LL]) -#define RSCAN0TMDF179LH (RSCAN0.TMDF179.UINT8[R_IO_LH]) -#define RSCAN0TMDF179H (RSCAN0.TMDF179.UINT16[R_IO_H]) -#define RSCAN0TMDF179HL (RSCAN0.TMDF179.UINT8[R_IO_HL]) -#define RSCAN0TMDF179HH (RSCAN0.TMDF179.UINT8[R_IO_HH]) -#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32) -#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L]) -#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL]) -#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH]) -#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H]) -#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL]) -#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH]) -#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32) -#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L]) -#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL]) -#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH]) -#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H]) -#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL]) -#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH]) -#define RSCAN0THLACC2 (RSCAN0.THLACC2.UINT32) -#define RSCAN0THLACC2L (RSCAN0.THLACC2.UINT16[R_IO_L]) -#define RSCAN0THLACC2LL (RSCAN0.THLACC2.UINT8[R_IO_LL]) -#define RSCAN0THLACC2LH (RSCAN0.THLACC2.UINT8[R_IO_LH]) -#define RSCAN0THLACC2H (RSCAN0.THLACC2.UINT16[R_IO_H]) -#define RSCAN0THLACC2HL (RSCAN0.THLACC2.UINT8[R_IO_HL]) -#define RSCAN0THLACC2HH (RSCAN0.THLACC2.UINT8[R_IO_HH]) -#define RSCAN0THLACC3 (RSCAN0.THLACC3.UINT32) -#define RSCAN0THLACC3L (RSCAN0.THLACC3.UINT16[R_IO_L]) -#define RSCAN0THLACC3LL (RSCAN0.THLACC3.UINT8[R_IO_LL]) -#define RSCAN0THLACC3LH (RSCAN0.THLACC3.UINT8[R_IO_LH]) -#define RSCAN0THLACC3H (RSCAN0.THLACC3.UINT16[R_IO_H]) -#define RSCAN0THLACC3HL (RSCAN0.THLACC3.UINT8[R_IO_HL]) -#define RSCAN0THLACC3HH (RSCAN0.THLACC3.UINT8[R_IO_HH]) -#define RSCAN0THLACC4 (RSCAN0.THLACC4.UINT32) -#define RSCAN0THLACC4L (RSCAN0.THLACC4.UINT16[R_IO_L]) -#define RSCAN0THLACC4LL (RSCAN0.THLACC4.UINT8[R_IO_LL]) -#define RSCAN0THLACC4LH (RSCAN0.THLACC4.UINT8[R_IO_LH]) -#define RSCAN0THLACC4H (RSCAN0.THLACC4.UINT16[R_IO_H]) -#define RSCAN0THLACC4HL (RSCAN0.THLACC4.UINT8[R_IO_HL]) -#define RSCAN0THLACC4HH (RSCAN0.THLACC4.UINT8[R_IO_HH]) - -#define RSCAN0_GAFLCFG0_COUNT (2) -#define RSCAN0_RMND0_COUNT (3) -#define RSCAN0_RFCC0_COUNT (8) -#define RSCAN0_RFSTS0_COUNT (8) -#define RSCAN0_RFPCTR0_COUNT (8) -#define RSCAN0_CFCC0_COUNT (15) -#define RSCAN0_CFSTS0_COUNT (15) -#define RSCAN0_CFPCTR0_COUNT (15) -#define RSCAN0_TMC0_COUNT (80) -#define RSCAN0_TMSTS0_COUNT (80) -#define RSCAN0_TMTRSTS0_COUNT (3) -#define RSCAN0_TMTARSTS0_COUNT (3) -#define RSCAN0_TMTCSTS0_COUNT (3) -#define RSCAN0_TMTASTS0_COUNT (3) -#define RSCAN0_TMIEC0_COUNT (3) -#define RSCAN0_TXQCC0_COUNT (5) -#define RSCAN0_TXQSTS0_COUNT (5) -#define RSCAN0_TXQPCTR0_COUNT (5) -#define RSCAN0_THLCC0_COUNT (5) -#define RSCAN0_THLSTS0_COUNT (5) -#define RSCAN0_THLPCTR0_COUNT (5) -#define RSCAN0_GTINTSTS0_COUNT (2) -#define RSCAN0_THLACC0_COUNT (5) - - -typedef struct st_rscan0 -{ - /* RSCAN0 */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C0CFG; /* C0CFG */ - union iodefine_reg32_t C0CTR; /* C0CTR */ - union iodefine_reg32_t C0STS; /* C0STS */ - union iodefine_reg32_t C0ERFL; /* C0ERFL */ - -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C1CFG; /* C1CFG */ - union iodefine_reg32_t C1CTR; /* C1CTR */ - union iodefine_reg32_t C1STS; /* C1STS */ - union iodefine_reg32_t C1ERFL; /* C1ERFL */ - -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C2CFG; /* C2CFG */ - union iodefine_reg32_t C2CTR; /* C2CTR */ - union iodefine_reg32_t C2STS; /* C2STS */ - union iodefine_reg32_t C2ERFL; /* C2ERFL */ - -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C3CFG; /* C3CFG */ - union iodefine_reg32_t C3CTR; /* C3CTR */ - union iodefine_reg32_t C3STS; /* C3STS */ - union iodefine_reg32_t C3ERFL; /* C3ERFL */ - -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C4CFG; /* C4CFG */ - union iodefine_reg32_t C4CTR; /* C4CTR */ - union iodefine_reg32_t C4STS; /* C4STS */ - union iodefine_reg32_t C4ERFL; /* C4ERFL */ - -/* end of struct st_rscan_from_rscan0cncfg */ - - volatile uint8_t dummy159[52]; /* */ - union iodefine_reg32_t GCFG; /* GCFG */ - union iodefine_reg32_t GCTR; /* GCTR */ - union iodefine_reg32_t GSTS; /* GSTS */ - union iodefine_reg32_t GERFL; /* GERFL */ - union iodefine_reg32_16_t GTSC; /* GTSC */ - union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ - -/* #define RSCAN0_GAFLCFG0_COUNT (2) */ - union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ - union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ - union iodefine_reg32_t RMNB; /* RMNB */ - -/* #define RSCAN0_RMND0_COUNT (3) */ - union iodefine_reg32_t RMND0; /* RMND0 */ - union iodefine_reg32_t RMND1; /* RMND1 */ - union iodefine_reg32_t RMND2; /* RMND2 */ - - volatile uint8_t dummy160[4]; /* */ - -/* #define RSCAN0_RFCC0_COUNT (8) */ - union iodefine_reg32_t RFCC0; /* RFCC0 */ - union iodefine_reg32_t RFCC1; /* RFCC1 */ - union iodefine_reg32_t RFCC2; /* RFCC2 */ - union iodefine_reg32_t RFCC3; /* RFCC3 */ - union iodefine_reg32_t RFCC4; /* RFCC4 */ - union iodefine_reg32_t RFCC5; /* RFCC5 */ - union iodefine_reg32_t RFCC6; /* RFCC6 */ - union iodefine_reg32_t RFCC7; /* RFCC7 */ - -/* #define RSCAN0_RFSTS0_COUNT (8) */ - union iodefine_reg32_t RFSTS0; /* RFSTS0 */ - union iodefine_reg32_t RFSTS1; /* RFSTS1 */ - union iodefine_reg32_t RFSTS2; /* RFSTS2 */ - union iodefine_reg32_t RFSTS3; /* RFSTS3 */ - union iodefine_reg32_t RFSTS4; /* RFSTS4 */ - union iodefine_reg32_t RFSTS5; /* RFSTS5 */ - union iodefine_reg32_t RFSTS6; /* RFSTS6 */ - union iodefine_reg32_t RFSTS7; /* RFSTS7 */ - -/* #define RSCAN0_RFPCTR0_COUNT (8) */ - union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ - union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ - union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ - union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ - union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ - union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ - union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ - union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ - -/* #define RSCAN0_CFCC0_COUNT (15) */ - union iodefine_reg32_t CFCC0; /* CFCC0 */ - union iodefine_reg32_t CFCC1; /* CFCC1 */ - union iodefine_reg32_t CFCC2; /* CFCC2 */ - union iodefine_reg32_t CFCC3; /* CFCC3 */ - union iodefine_reg32_t CFCC4; /* CFCC4 */ - union iodefine_reg32_t CFCC5; /* CFCC5 */ - union iodefine_reg32_t CFCC6; /* CFCC6 */ - union iodefine_reg32_t CFCC7; /* CFCC7 */ - union iodefine_reg32_t CFCC8; /* CFCC8 */ - union iodefine_reg32_t CFCC9; /* CFCC9 */ - union iodefine_reg32_t CFCC10; /* CFCC10 */ - union iodefine_reg32_t CFCC11; /* CFCC11 */ - union iodefine_reg32_t CFCC12; /* CFCC12 */ - union iodefine_reg32_t CFCC13; /* CFCC13 */ - union iodefine_reg32_t CFCC14; /* CFCC14 */ - - volatile uint8_t dummy161[36]; /* */ - -/* #define RSCAN0_CFSTS0_COUNT (15) */ - union iodefine_reg32_t CFSTS0; /* CFSTS0 */ - union iodefine_reg32_t CFSTS1; /* CFSTS1 */ - union iodefine_reg32_t CFSTS2; /* CFSTS2 */ - union iodefine_reg32_t CFSTS3; /* CFSTS3 */ - union iodefine_reg32_t CFSTS4; /* CFSTS4 */ - union iodefine_reg32_t CFSTS5; /* CFSTS5 */ - union iodefine_reg32_t CFSTS6; /* CFSTS6 */ - union iodefine_reg32_t CFSTS7; /* CFSTS7 */ - union iodefine_reg32_t CFSTS8; /* CFSTS8 */ - union iodefine_reg32_t CFSTS9; /* CFSTS9 */ - union iodefine_reg32_t CFSTS10; /* CFSTS10 */ - union iodefine_reg32_t CFSTS11; /* CFSTS11 */ - union iodefine_reg32_t CFSTS12; /* CFSTS12 */ - union iodefine_reg32_t CFSTS13; /* CFSTS13 */ - union iodefine_reg32_t CFSTS14; /* CFSTS14 */ - - volatile uint8_t dummy162[36]; /* */ - -/* #define RSCAN0_CFPCTR0_COUNT (15) */ - union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ - union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ - union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ - union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ - union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ - union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ - union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ - union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ - union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ - union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ - union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ - union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ - union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ - union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ - union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ - - volatile uint8_t dummy163[36]; /* */ - union iodefine_reg32_t FESTS; /* FESTS */ - union iodefine_reg32_t FFSTS; /* FFSTS */ - union iodefine_reg32_t FMSTS; /* FMSTS */ - union iodefine_reg32_t RFISTS; /* RFISTS */ - union iodefine_reg32_t CFRISTS; /* CFRISTS */ - union iodefine_reg32_t CFTISTS; /* CFTISTS */ - - -/* #define RSCAN0_TMC0_COUNT (80) */ - volatile uint8_t TMC0; /* TMC0 */ - volatile uint8_t TMC1; /* TMC1 */ - volatile uint8_t TMC2; /* TMC2 */ - volatile uint8_t TMC3; /* TMC3 */ - volatile uint8_t TMC4; /* TMC4 */ - volatile uint8_t TMC5; /* TMC5 */ - volatile uint8_t TMC6; /* TMC6 */ - volatile uint8_t TMC7; /* TMC7 */ - volatile uint8_t TMC8; /* TMC8 */ - volatile uint8_t TMC9; /* TMC9 */ - volatile uint8_t TMC10; /* TMC10 */ - volatile uint8_t TMC11; /* TMC11 */ - volatile uint8_t TMC12; /* TMC12 */ - volatile uint8_t TMC13; /* TMC13 */ - volatile uint8_t TMC14; /* TMC14 */ - volatile uint8_t TMC15; /* TMC15 */ - volatile uint8_t TMC16; /* TMC16 */ - volatile uint8_t TMC17; /* TMC17 */ - volatile uint8_t TMC18; /* TMC18 */ - volatile uint8_t TMC19; /* TMC19 */ - volatile uint8_t TMC20; /* TMC20 */ - volatile uint8_t TMC21; /* TMC21 */ - volatile uint8_t TMC22; /* TMC22 */ - volatile uint8_t TMC23; /* TMC23 */ - volatile uint8_t TMC24; /* TMC24 */ - volatile uint8_t TMC25; /* TMC25 */ - volatile uint8_t TMC26; /* TMC26 */ - volatile uint8_t TMC27; /* TMC27 */ - volatile uint8_t TMC28; /* TMC28 */ - volatile uint8_t TMC29; /* TMC29 */ - volatile uint8_t TMC30; /* TMC30 */ - volatile uint8_t TMC31; /* TMC31 */ - volatile uint8_t TMC32; /* TMC32 */ - volatile uint8_t TMC33; /* TMC33 */ - volatile uint8_t TMC34; /* TMC34 */ - volatile uint8_t TMC35; /* TMC35 */ - volatile uint8_t TMC36; /* TMC36 */ - volatile uint8_t TMC37; /* TMC37 */ - volatile uint8_t TMC38; /* TMC38 */ - volatile uint8_t TMC39; /* TMC39 */ - volatile uint8_t TMC40; /* TMC40 */ - volatile uint8_t TMC41; /* TMC41 */ - volatile uint8_t TMC42; /* TMC42 */ - volatile uint8_t TMC43; /* TMC43 */ - volatile uint8_t TMC44; /* TMC44 */ - volatile uint8_t TMC45; /* TMC45 */ - volatile uint8_t TMC46; /* TMC46 */ - volatile uint8_t TMC47; /* TMC47 */ - volatile uint8_t TMC48; /* TMC48 */ - volatile uint8_t TMC49; /* TMC49 */ - volatile uint8_t TMC50; /* TMC50 */ - volatile uint8_t TMC51; /* TMC51 */ - volatile uint8_t TMC52; /* TMC52 */ - volatile uint8_t TMC53; /* TMC53 */ - volatile uint8_t TMC54; /* TMC54 */ - volatile uint8_t TMC55; /* TMC55 */ - volatile uint8_t TMC56; /* TMC56 */ - volatile uint8_t TMC57; /* TMC57 */ - volatile uint8_t TMC58; /* TMC58 */ - volatile uint8_t TMC59; /* TMC59 */ - volatile uint8_t TMC60; /* TMC60 */ - volatile uint8_t TMC61; /* TMC61 */ - volatile uint8_t TMC62; /* TMC62 */ - volatile uint8_t TMC63; /* TMC63 */ - volatile uint8_t TMC64; /* TMC64 */ - volatile uint8_t TMC65; /* TMC65 */ - volatile uint8_t TMC66; /* TMC66 */ - volatile uint8_t TMC67; /* TMC67 */ - volatile uint8_t TMC68; /* TMC68 */ - volatile uint8_t TMC69; /* TMC69 */ - volatile uint8_t TMC70; /* TMC70 */ - volatile uint8_t TMC71; /* TMC71 */ - volatile uint8_t TMC72; /* TMC72 */ - volatile uint8_t TMC73; /* TMC73 */ - volatile uint8_t TMC74; /* TMC74 */ - volatile uint8_t TMC75; /* TMC75 */ - volatile uint8_t TMC76; /* TMC76 */ - volatile uint8_t TMC77; /* TMC77 */ - volatile uint8_t TMC78; /* TMC78 */ - volatile uint8_t TMC79; /* TMC79 */ - volatile uint8_t dummy164[48]; /* */ - -/* #define RSCAN0_TMSTS0_COUNT (80) */ - volatile uint8_t TMSTS0; /* TMSTS0 */ - volatile uint8_t TMSTS1; /* TMSTS1 */ - volatile uint8_t TMSTS2; /* TMSTS2 */ - volatile uint8_t TMSTS3; /* TMSTS3 */ - volatile uint8_t TMSTS4; /* TMSTS4 */ - volatile uint8_t TMSTS5; /* TMSTS5 */ - volatile uint8_t TMSTS6; /* TMSTS6 */ - volatile uint8_t TMSTS7; /* TMSTS7 */ - volatile uint8_t TMSTS8; /* TMSTS8 */ - volatile uint8_t TMSTS9; /* TMSTS9 */ - volatile uint8_t TMSTS10; /* TMSTS10 */ - volatile uint8_t TMSTS11; /* TMSTS11 */ - volatile uint8_t TMSTS12; /* TMSTS12 */ - volatile uint8_t TMSTS13; /* TMSTS13 */ - volatile uint8_t TMSTS14; /* TMSTS14 */ - volatile uint8_t TMSTS15; /* TMSTS15 */ - volatile uint8_t TMSTS16; /* TMSTS16 */ - volatile uint8_t TMSTS17; /* TMSTS17 */ - volatile uint8_t TMSTS18; /* TMSTS18 */ - volatile uint8_t TMSTS19; /* TMSTS19 */ - volatile uint8_t TMSTS20; /* TMSTS20 */ - volatile uint8_t TMSTS21; /* TMSTS21 */ - volatile uint8_t TMSTS22; /* TMSTS22 */ - volatile uint8_t TMSTS23; /* TMSTS23 */ - volatile uint8_t TMSTS24; /* TMSTS24 */ - volatile uint8_t TMSTS25; /* TMSTS25 */ - volatile uint8_t TMSTS26; /* TMSTS26 */ - volatile uint8_t TMSTS27; /* TMSTS27 */ - volatile uint8_t TMSTS28; /* TMSTS28 */ - volatile uint8_t TMSTS29; /* TMSTS29 */ - volatile uint8_t TMSTS30; /* TMSTS30 */ - volatile uint8_t TMSTS31; /* TMSTS31 */ - volatile uint8_t TMSTS32; /* TMSTS32 */ - volatile uint8_t TMSTS33; /* TMSTS33 */ - volatile uint8_t TMSTS34; /* TMSTS34 */ - volatile uint8_t TMSTS35; /* TMSTS35 */ - volatile uint8_t TMSTS36; /* TMSTS36 */ - volatile uint8_t TMSTS37; /* TMSTS37 */ - volatile uint8_t TMSTS38; /* TMSTS38 */ - volatile uint8_t TMSTS39; /* TMSTS39 */ - volatile uint8_t TMSTS40; /* TMSTS40 */ - volatile uint8_t TMSTS41; /* TMSTS41 */ - volatile uint8_t TMSTS42; /* TMSTS42 */ - volatile uint8_t TMSTS43; /* TMSTS43 */ - volatile uint8_t TMSTS44; /* TMSTS44 */ - volatile uint8_t TMSTS45; /* TMSTS45 */ - volatile uint8_t TMSTS46; /* TMSTS46 */ - volatile uint8_t TMSTS47; /* TMSTS47 */ - volatile uint8_t TMSTS48; /* TMSTS48 */ - volatile uint8_t TMSTS49; /* TMSTS49 */ - volatile uint8_t TMSTS50; /* TMSTS50 */ - volatile uint8_t TMSTS51; /* TMSTS51 */ - volatile uint8_t TMSTS52; /* TMSTS52 */ - volatile uint8_t TMSTS53; /* TMSTS53 */ - volatile uint8_t TMSTS54; /* TMSTS54 */ - volatile uint8_t TMSTS55; /* TMSTS55 */ - volatile uint8_t TMSTS56; /* TMSTS56 */ - volatile uint8_t TMSTS57; /* TMSTS57 */ - volatile uint8_t TMSTS58; /* TMSTS58 */ - volatile uint8_t TMSTS59; /* TMSTS59 */ - volatile uint8_t TMSTS60; /* TMSTS60 */ - volatile uint8_t TMSTS61; /* TMSTS61 */ - volatile uint8_t TMSTS62; /* TMSTS62 */ - volatile uint8_t TMSTS63; /* TMSTS63 */ - volatile uint8_t TMSTS64; /* TMSTS64 */ - volatile uint8_t TMSTS65; /* TMSTS65 */ - volatile uint8_t TMSTS66; /* TMSTS66 */ - volatile uint8_t TMSTS67; /* TMSTS67 */ - volatile uint8_t TMSTS68; /* TMSTS68 */ - volatile uint8_t TMSTS69; /* TMSTS69 */ - volatile uint8_t TMSTS70; /* TMSTS70 */ - volatile uint8_t TMSTS71; /* TMSTS71 */ - volatile uint8_t TMSTS72; /* TMSTS72 */ - volatile uint8_t TMSTS73; /* TMSTS73 */ - volatile uint8_t TMSTS74; /* TMSTS74 */ - volatile uint8_t TMSTS75; /* TMSTS75 */ - volatile uint8_t TMSTS76; /* TMSTS76 */ - volatile uint8_t TMSTS77; /* TMSTS77 */ - volatile uint8_t TMSTS78; /* TMSTS78 */ - volatile uint8_t TMSTS79; /* TMSTS79 */ - volatile uint8_t dummy165[48]; /* */ - -/* #define RSCAN0_TMTRSTS0_COUNT (3) */ - union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ - union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ - union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ - - volatile uint8_t dummy166[4]; /* */ - -/* #define RSCAN0_TMTARSTS0_COUNT (3) */ - union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ - union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ - union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ - - volatile uint8_t dummy167[4]; /* */ - -/* #define RSCAN0_TMTCSTS0_COUNT (3) */ - union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ - union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ - union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ - - volatile uint8_t dummy168[4]; /* */ - -/* #define RSCAN0_TMTASTS0_COUNT (3) */ - union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ - union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ - union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ - - volatile uint8_t dummy169[4]; /* */ - -/* #define RSCAN0_TMIEC0_COUNT (3) */ - union iodefine_reg32_t TMIEC0; /* TMIEC0 */ - union iodefine_reg32_t TMIEC1; /* TMIEC1 */ - union iodefine_reg32_t TMIEC2; /* TMIEC2 */ - - volatile uint8_t dummy170[4]; /* */ - -/* #define RSCAN0_TXQCC0_COUNT (5) */ - union iodefine_reg32_t TXQCC0; /* TXQCC0 */ - union iodefine_reg32_t TXQCC1; /* TXQCC1 */ - union iodefine_reg32_t TXQCC2; /* TXQCC2 */ - union iodefine_reg32_t TXQCC3; /* TXQCC3 */ - union iodefine_reg32_t TXQCC4; /* TXQCC4 */ - - volatile uint8_t dummy171[12]; /* */ - -/* #define RSCAN0_TXQSTS0_COUNT (5) */ - union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ - union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ - union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ - union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ - union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ - - volatile uint8_t dummy172[12]; /* */ - -/* #define RSCAN0_TXQPCTR0_COUNT (5) */ - union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ - union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ - union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ - union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ - union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ - - volatile uint8_t dummy173[12]; /* */ - -/* #define RSCAN0_THLCC0_COUNT (5) */ - union iodefine_reg32_t THLCC0; /* THLCC0 */ - union iodefine_reg32_t THLCC1; /* THLCC1 */ - union iodefine_reg32_t THLCC2; /* THLCC2 */ - union iodefine_reg32_t THLCC3; /* THLCC3 */ - union iodefine_reg32_t THLCC4; /* THLCC4 */ - - volatile uint8_t dummy174[12]; /* */ - -/* #define RSCAN0_THLSTS0_COUNT (5) */ - union iodefine_reg32_t THLSTS0; /* THLSTS0 */ - union iodefine_reg32_t THLSTS1; /* THLSTS1 */ - union iodefine_reg32_t THLSTS2; /* THLSTS2 */ - union iodefine_reg32_t THLSTS3; /* THLSTS3 */ - union iodefine_reg32_t THLSTS4; /* THLSTS4 */ - - volatile uint8_t dummy175[12]; /* */ - -/* #define RSCAN0_THLPCTR0_COUNT (5) */ - union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ - union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ - union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ - union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ - union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ - - volatile uint8_t dummy176[12]; /* */ - -/* #define RSCAN0_GTINTSTS0_COUNT (2) */ - union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ - union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ - union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ - union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ - - volatile uint8_t dummy177[12]; /* */ - union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ - - volatile uint8_t dummy178[128]; /* */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID0; /* GAFLID0 */ - union iodefine_reg32_t GAFLM0; /* GAFLM0 */ - union iodefine_reg32_t GAFLP00; /* GAFLP00 */ - union iodefine_reg32_t GAFLP10; /* GAFLP10 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID1; /* GAFLID1 */ - union iodefine_reg32_t GAFLM1; /* GAFLM1 */ - union iodefine_reg32_t GAFLP01; /* GAFLP01 */ - union iodefine_reg32_t GAFLP11; /* GAFLP11 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID2; /* GAFLID2 */ - union iodefine_reg32_t GAFLM2; /* GAFLM2 */ - union iodefine_reg32_t GAFLP02; /* GAFLP02 */ - union iodefine_reg32_t GAFLP12; /* GAFLP12 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID3; /* GAFLID3 */ - union iodefine_reg32_t GAFLM3; /* GAFLM3 */ - union iodefine_reg32_t GAFLP03; /* GAFLP03 */ - union iodefine_reg32_t GAFLP13; /* GAFLP13 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID4; /* GAFLID4 */ - union iodefine_reg32_t GAFLM4; /* GAFLM4 */ - union iodefine_reg32_t GAFLP04; /* GAFLP04 */ - union iodefine_reg32_t GAFLP14; /* GAFLP14 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID5; /* GAFLID5 */ - union iodefine_reg32_t GAFLM5; /* GAFLM5 */ - union iodefine_reg32_t GAFLP05; /* GAFLP05 */ - union iodefine_reg32_t GAFLP15; /* GAFLP15 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID6; /* GAFLID6 */ - union iodefine_reg32_t GAFLM6; /* GAFLM6 */ - union iodefine_reg32_t GAFLP06; /* GAFLP06 */ - union iodefine_reg32_t GAFLP16; /* GAFLP16 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID7; /* GAFLID7 */ - union iodefine_reg32_t GAFLM7; /* GAFLM7 */ - union iodefine_reg32_t GAFLP07; /* GAFLP07 */ - union iodefine_reg32_t GAFLP17; /* GAFLP17 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID8; /* GAFLID8 */ - union iodefine_reg32_t GAFLM8; /* GAFLM8 */ - union iodefine_reg32_t GAFLP08; /* GAFLP08 */ - union iodefine_reg32_t GAFLP18; /* GAFLP18 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID9; /* GAFLID9 */ - union iodefine_reg32_t GAFLM9; /* GAFLM9 */ - union iodefine_reg32_t GAFLP09; /* GAFLP09 */ - union iodefine_reg32_t GAFLP19; /* GAFLP19 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID10; /* GAFLID10 */ - union iodefine_reg32_t GAFLM10; /* GAFLM10 */ - union iodefine_reg32_t GAFLP010; /* GAFLP010 */ - union iodefine_reg32_t GAFLP110; /* GAFLP110 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID11; /* GAFLID11 */ - union iodefine_reg32_t GAFLM11; /* GAFLM11 */ - union iodefine_reg32_t GAFLP011; /* GAFLP011 */ - union iodefine_reg32_t GAFLP111; /* GAFLP111 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID12; /* GAFLID12 */ - union iodefine_reg32_t GAFLM12; /* GAFLM12 */ - union iodefine_reg32_t GAFLP012; /* GAFLP012 */ - union iodefine_reg32_t GAFLP112; /* GAFLP112 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID13; /* GAFLID13 */ - union iodefine_reg32_t GAFLM13; /* GAFLM13 */ - union iodefine_reg32_t GAFLP013; /* GAFLP013 */ - union iodefine_reg32_t GAFLP113; /* GAFLP113 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID14; /* GAFLID14 */ - union iodefine_reg32_t GAFLM14; /* GAFLM14 */ - union iodefine_reg32_t GAFLP014; /* GAFLP014 */ - union iodefine_reg32_t GAFLP114; /* GAFLP114 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID15; /* GAFLID15 */ - union iodefine_reg32_t GAFLM15; /* GAFLM15 */ - union iodefine_reg32_t GAFLP015; /* GAFLP015 */ - union iodefine_reg32_t GAFLP115; /* GAFLP115 */ - -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID0; /* RMID0 */ - union iodefine_reg32_t RMPTR0; /* RMPTR0 */ - union iodefine_reg32_t RMDF00; /* RMDF00 */ - union iodefine_reg32_t RMDF10; /* RMDF10 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID1; /* RMID1 */ - union iodefine_reg32_t RMPTR1; /* RMPTR1 */ - union iodefine_reg32_t RMDF01; /* RMDF01 */ - union iodefine_reg32_t RMDF11; /* RMDF11 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID2; /* RMID2 */ - union iodefine_reg32_t RMPTR2; /* RMPTR2 */ - union iodefine_reg32_t RMDF02; /* RMDF02 */ - union iodefine_reg32_t RMDF12; /* RMDF12 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID3; /* RMID3 */ - union iodefine_reg32_t RMPTR3; /* RMPTR3 */ - union iodefine_reg32_t RMDF03; /* RMDF03 */ - union iodefine_reg32_t RMDF13; /* RMDF13 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID4; /* RMID4 */ - union iodefine_reg32_t RMPTR4; /* RMPTR4 */ - union iodefine_reg32_t RMDF04; /* RMDF04 */ - union iodefine_reg32_t RMDF14; /* RMDF14 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID5; /* RMID5 */ - union iodefine_reg32_t RMPTR5; /* RMPTR5 */ - union iodefine_reg32_t RMDF05; /* RMDF05 */ - union iodefine_reg32_t RMDF15; /* RMDF15 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID6; /* RMID6 */ - union iodefine_reg32_t RMPTR6; /* RMPTR6 */ - union iodefine_reg32_t RMDF06; /* RMDF06 */ - union iodefine_reg32_t RMDF16; /* RMDF16 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID7; /* RMID7 */ - union iodefine_reg32_t RMPTR7; /* RMPTR7 */ - union iodefine_reg32_t RMDF07; /* RMDF07 */ - union iodefine_reg32_t RMDF17; /* RMDF17 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID8; /* RMID8 */ - union iodefine_reg32_t RMPTR8; /* RMPTR8 */ - union iodefine_reg32_t RMDF08; /* RMDF08 */ - union iodefine_reg32_t RMDF18; /* RMDF18 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID9; /* RMID9 */ - union iodefine_reg32_t RMPTR9; /* RMPTR9 */ - union iodefine_reg32_t RMDF09; /* RMDF09 */ - union iodefine_reg32_t RMDF19; /* RMDF19 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID10; /* RMID10 */ - union iodefine_reg32_t RMPTR10; /* RMPTR10 */ - union iodefine_reg32_t RMDF010; /* RMDF010 */ - union iodefine_reg32_t RMDF110; /* RMDF110 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID11; /* RMID11 */ - union iodefine_reg32_t RMPTR11; /* RMPTR11 */ - union iodefine_reg32_t RMDF011; /* RMDF011 */ - union iodefine_reg32_t RMDF111; /* RMDF111 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID12; /* RMID12 */ - union iodefine_reg32_t RMPTR12; /* RMPTR12 */ - union iodefine_reg32_t RMDF012; /* RMDF012 */ - union iodefine_reg32_t RMDF112; /* RMDF112 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID13; /* RMID13 */ - union iodefine_reg32_t RMPTR13; /* RMPTR13 */ - union iodefine_reg32_t RMDF013; /* RMDF013 */ - union iodefine_reg32_t RMDF113; /* RMDF113 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID14; /* RMID14 */ - union iodefine_reg32_t RMPTR14; /* RMPTR14 */ - union iodefine_reg32_t RMDF014; /* RMDF014 */ - union iodefine_reg32_t RMDF114; /* RMDF114 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID15; /* RMID15 */ - union iodefine_reg32_t RMPTR15; /* RMPTR15 */ - union iodefine_reg32_t RMDF015; /* RMDF015 */ - union iodefine_reg32_t RMDF115; /* RMDF115 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID16; /* RMID16 */ - union iodefine_reg32_t RMPTR16; /* RMPTR16 */ - union iodefine_reg32_t RMDF016; /* RMDF016 */ - union iodefine_reg32_t RMDF116; /* RMDF116 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID17; /* RMID17 */ - union iodefine_reg32_t RMPTR17; /* RMPTR17 */ - union iodefine_reg32_t RMDF017; /* RMDF017 */ - union iodefine_reg32_t RMDF117; /* RMDF117 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID18; /* RMID18 */ - union iodefine_reg32_t RMPTR18; /* RMPTR18 */ - union iodefine_reg32_t RMDF018; /* RMDF018 */ - union iodefine_reg32_t RMDF118; /* RMDF118 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID19; /* RMID19 */ - union iodefine_reg32_t RMPTR19; /* RMPTR19 */ - union iodefine_reg32_t RMDF019; /* RMDF019 */ - union iodefine_reg32_t RMDF119; /* RMDF119 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID20; /* RMID20 */ - union iodefine_reg32_t RMPTR20; /* RMPTR20 */ - union iodefine_reg32_t RMDF020; /* RMDF020 */ - union iodefine_reg32_t RMDF120; /* RMDF120 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID21; /* RMID21 */ - union iodefine_reg32_t RMPTR21; /* RMPTR21 */ - union iodefine_reg32_t RMDF021; /* RMDF021 */ - union iodefine_reg32_t RMDF121; /* RMDF121 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID22; /* RMID22 */ - union iodefine_reg32_t RMPTR22; /* RMPTR22 */ - union iodefine_reg32_t RMDF022; /* RMDF022 */ - union iodefine_reg32_t RMDF122; /* RMDF122 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID23; /* RMID23 */ - union iodefine_reg32_t RMPTR23; /* RMPTR23 */ - union iodefine_reg32_t RMDF023; /* RMDF023 */ - union iodefine_reg32_t RMDF123; /* RMDF123 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID24; /* RMID24 */ - union iodefine_reg32_t RMPTR24; /* RMPTR24 */ - union iodefine_reg32_t RMDF024; /* RMDF024 */ - union iodefine_reg32_t RMDF124; /* RMDF124 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID25; /* RMID25 */ - union iodefine_reg32_t RMPTR25; /* RMPTR25 */ - union iodefine_reg32_t RMDF025; /* RMDF025 */ - union iodefine_reg32_t RMDF125; /* RMDF125 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID26; /* RMID26 */ - union iodefine_reg32_t RMPTR26; /* RMPTR26 */ - union iodefine_reg32_t RMDF026; /* RMDF026 */ - union iodefine_reg32_t RMDF126; /* RMDF126 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID27; /* RMID27 */ - union iodefine_reg32_t RMPTR27; /* RMPTR27 */ - union iodefine_reg32_t RMDF027; /* RMDF027 */ - union iodefine_reg32_t RMDF127; /* RMDF127 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID28; /* RMID28 */ - union iodefine_reg32_t RMPTR28; /* RMPTR28 */ - union iodefine_reg32_t RMDF028; /* RMDF028 */ - union iodefine_reg32_t RMDF128; /* RMDF128 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID29; /* RMID29 */ - union iodefine_reg32_t RMPTR29; /* RMPTR29 */ - union iodefine_reg32_t RMDF029; /* RMDF029 */ - union iodefine_reg32_t RMDF129; /* RMDF129 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID30; /* RMID30 */ - union iodefine_reg32_t RMPTR30; /* RMPTR30 */ - union iodefine_reg32_t RMDF030; /* RMDF030 */ - union iodefine_reg32_t RMDF130; /* RMDF130 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID31; /* RMID31 */ - union iodefine_reg32_t RMPTR31; /* RMPTR31 */ - union iodefine_reg32_t RMDF031; /* RMDF031 */ - union iodefine_reg32_t RMDF131; /* RMDF131 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID32; /* RMID32 */ - union iodefine_reg32_t RMPTR32; /* RMPTR32 */ - union iodefine_reg32_t RMDF032; /* RMDF032 */ - union iodefine_reg32_t RMDF132; /* RMDF132 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID33; /* RMID33 */ - union iodefine_reg32_t RMPTR33; /* RMPTR33 */ - union iodefine_reg32_t RMDF033; /* RMDF033 */ - union iodefine_reg32_t RMDF133; /* RMDF133 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID34; /* RMID34 */ - union iodefine_reg32_t RMPTR34; /* RMPTR34 */ - union iodefine_reg32_t RMDF034; /* RMDF034 */ - union iodefine_reg32_t RMDF134; /* RMDF134 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID35; /* RMID35 */ - union iodefine_reg32_t RMPTR35; /* RMPTR35 */ - union iodefine_reg32_t RMDF035; /* RMDF035 */ - union iodefine_reg32_t RMDF135; /* RMDF135 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID36; /* RMID36 */ - union iodefine_reg32_t RMPTR36; /* RMPTR36 */ - union iodefine_reg32_t RMDF036; /* RMDF036 */ - union iodefine_reg32_t RMDF136; /* RMDF136 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID37; /* RMID37 */ - union iodefine_reg32_t RMPTR37; /* RMPTR37 */ - union iodefine_reg32_t RMDF037; /* RMDF037 */ - union iodefine_reg32_t RMDF137; /* RMDF137 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID38; /* RMID38 */ - union iodefine_reg32_t RMPTR38; /* RMPTR38 */ - union iodefine_reg32_t RMDF038; /* RMDF038 */ - union iodefine_reg32_t RMDF138; /* RMDF138 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID39; /* RMID39 */ - union iodefine_reg32_t RMPTR39; /* RMPTR39 */ - union iodefine_reg32_t RMDF039; /* RMDF039 */ - union iodefine_reg32_t RMDF139; /* RMDF139 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID40; /* RMID40 */ - union iodefine_reg32_t RMPTR40; /* RMPTR40 */ - union iodefine_reg32_t RMDF040; /* RMDF040 */ - union iodefine_reg32_t RMDF140; /* RMDF140 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID41; /* RMID41 */ - union iodefine_reg32_t RMPTR41; /* RMPTR41 */ - union iodefine_reg32_t RMDF041; /* RMDF041 */ - union iodefine_reg32_t RMDF141; /* RMDF141 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID42; /* RMID42 */ - union iodefine_reg32_t RMPTR42; /* RMPTR42 */ - union iodefine_reg32_t RMDF042; /* RMDF042 */ - union iodefine_reg32_t RMDF142; /* RMDF142 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID43; /* RMID43 */ - union iodefine_reg32_t RMPTR43; /* RMPTR43 */ - union iodefine_reg32_t RMDF043; /* RMDF043 */ - union iodefine_reg32_t RMDF143; /* RMDF143 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID44; /* RMID44 */ - union iodefine_reg32_t RMPTR44; /* RMPTR44 */ - union iodefine_reg32_t RMDF044; /* RMDF044 */ - union iodefine_reg32_t RMDF144; /* RMDF144 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID45; /* RMID45 */ - union iodefine_reg32_t RMPTR45; /* RMPTR45 */ - union iodefine_reg32_t RMDF045; /* RMDF045 */ - union iodefine_reg32_t RMDF145; /* RMDF145 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID46; /* RMID46 */ - union iodefine_reg32_t RMPTR46; /* RMPTR46 */ - union iodefine_reg32_t RMDF046; /* RMDF046 */ - union iodefine_reg32_t RMDF146; /* RMDF146 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID47; /* RMID47 */ - union iodefine_reg32_t RMPTR47; /* RMPTR47 */ - union iodefine_reg32_t RMDF047; /* RMDF047 */ - union iodefine_reg32_t RMDF147; /* RMDF147 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID48; /* RMID48 */ - union iodefine_reg32_t RMPTR48; /* RMPTR48 */ - union iodefine_reg32_t RMDF048; /* RMDF048 */ - union iodefine_reg32_t RMDF148; /* RMDF148 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID49; /* RMID49 */ - union iodefine_reg32_t RMPTR49; /* RMPTR49 */ - union iodefine_reg32_t RMDF049; /* RMDF049 */ - union iodefine_reg32_t RMDF149; /* RMDF149 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID50; /* RMID50 */ - union iodefine_reg32_t RMPTR50; /* RMPTR50 */ - union iodefine_reg32_t RMDF050; /* RMDF050 */ - union iodefine_reg32_t RMDF150; /* RMDF150 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID51; /* RMID51 */ - union iodefine_reg32_t RMPTR51; /* RMPTR51 */ - union iodefine_reg32_t RMDF051; /* RMDF051 */ - union iodefine_reg32_t RMDF151; /* RMDF151 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID52; /* RMID52 */ - union iodefine_reg32_t RMPTR52; /* RMPTR52 */ - union iodefine_reg32_t RMDF052; /* RMDF052 */ - union iodefine_reg32_t RMDF152; /* RMDF152 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID53; /* RMID53 */ - union iodefine_reg32_t RMPTR53; /* RMPTR53 */ - union iodefine_reg32_t RMDF053; /* RMDF053 */ - union iodefine_reg32_t RMDF153; /* RMDF153 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID54; /* RMID54 */ - union iodefine_reg32_t RMPTR54; /* RMPTR54 */ - union iodefine_reg32_t RMDF054; /* RMDF054 */ - union iodefine_reg32_t RMDF154; /* RMDF154 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID55; /* RMID55 */ - union iodefine_reg32_t RMPTR55; /* RMPTR55 */ - union iodefine_reg32_t RMDF055; /* RMDF055 */ - union iodefine_reg32_t RMDF155; /* RMDF155 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID56; /* RMID56 */ - union iodefine_reg32_t RMPTR56; /* RMPTR56 */ - union iodefine_reg32_t RMDF056; /* RMDF056 */ - union iodefine_reg32_t RMDF156; /* RMDF156 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID57; /* RMID57 */ - union iodefine_reg32_t RMPTR57; /* RMPTR57 */ - union iodefine_reg32_t RMDF057; /* RMDF057 */ - union iodefine_reg32_t RMDF157; /* RMDF157 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID58; /* RMID58 */ - union iodefine_reg32_t RMPTR58; /* RMPTR58 */ - union iodefine_reg32_t RMDF058; /* RMDF058 */ - union iodefine_reg32_t RMDF158; /* RMDF158 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID59; /* RMID59 */ - union iodefine_reg32_t RMPTR59; /* RMPTR59 */ - union iodefine_reg32_t RMDF059; /* RMDF059 */ - union iodefine_reg32_t RMDF159; /* RMDF159 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID60; /* RMID60 */ - union iodefine_reg32_t RMPTR60; /* RMPTR60 */ - union iodefine_reg32_t RMDF060; /* RMDF060 */ - union iodefine_reg32_t RMDF160; /* RMDF160 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID61; /* RMID61 */ - union iodefine_reg32_t RMPTR61; /* RMPTR61 */ - union iodefine_reg32_t RMDF061; /* RMDF061 */ - union iodefine_reg32_t RMDF161; /* RMDF161 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID62; /* RMID62 */ - union iodefine_reg32_t RMPTR62; /* RMPTR62 */ - union iodefine_reg32_t RMDF062; /* RMDF062 */ - union iodefine_reg32_t RMDF162; /* RMDF162 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID63; /* RMID63 */ - union iodefine_reg32_t RMPTR63; /* RMPTR63 */ - union iodefine_reg32_t RMDF063; /* RMDF063 */ - union iodefine_reg32_t RMDF163; /* RMDF163 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID64; /* RMID64 */ - union iodefine_reg32_t RMPTR64; /* RMPTR64 */ - union iodefine_reg32_t RMDF064; /* RMDF064 */ - union iodefine_reg32_t RMDF164; /* RMDF164 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID65; /* RMID65 */ - union iodefine_reg32_t RMPTR65; /* RMPTR65 */ - union iodefine_reg32_t RMDF065; /* RMDF065 */ - union iodefine_reg32_t RMDF165; /* RMDF165 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID66; /* RMID66 */ - union iodefine_reg32_t RMPTR66; /* RMPTR66 */ - union iodefine_reg32_t RMDF066; /* RMDF066 */ - union iodefine_reg32_t RMDF166; /* RMDF166 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID67; /* RMID67 */ - union iodefine_reg32_t RMPTR67; /* RMPTR67 */ - union iodefine_reg32_t RMDF067; /* RMDF067 */ - union iodefine_reg32_t RMDF167; /* RMDF167 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID68; /* RMID68 */ - union iodefine_reg32_t RMPTR68; /* RMPTR68 */ - union iodefine_reg32_t RMDF068; /* RMDF068 */ - union iodefine_reg32_t RMDF168; /* RMDF168 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID69; /* RMID69 */ - union iodefine_reg32_t RMPTR69; /* RMPTR69 */ - union iodefine_reg32_t RMDF069; /* RMDF069 */ - union iodefine_reg32_t RMDF169; /* RMDF169 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID70; /* RMID70 */ - union iodefine_reg32_t RMPTR70; /* RMPTR70 */ - union iodefine_reg32_t RMDF070; /* RMDF070 */ - union iodefine_reg32_t RMDF170; /* RMDF170 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID71; /* RMID71 */ - union iodefine_reg32_t RMPTR71; /* RMPTR71 */ - union iodefine_reg32_t RMDF071; /* RMDF071 */ - union iodefine_reg32_t RMDF171; /* RMDF171 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID72; /* RMID72 */ - union iodefine_reg32_t RMPTR72; /* RMPTR72 */ - union iodefine_reg32_t RMDF072; /* RMDF072 */ - union iodefine_reg32_t RMDF172; /* RMDF172 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID73; /* RMID73 */ - union iodefine_reg32_t RMPTR73; /* RMPTR73 */ - union iodefine_reg32_t RMDF073; /* RMDF073 */ - union iodefine_reg32_t RMDF173; /* RMDF173 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID74; /* RMID74 */ - union iodefine_reg32_t RMPTR74; /* RMPTR74 */ - union iodefine_reg32_t RMDF074; /* RMDF074 */ - union iodefine_reg32_t RMDF174; /* RMDF174 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID75; /* RMID75 */ - union iodefine_reg32_t RMPTR75; /* RMPTR75 */ - union iodefine_reg32_t RMDF075; /* RMDF075 */ - union iodefine_reg32_t RMDF175; /* RMDF175 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID76; /* RMID76 */ - union iodefine_reg32_t RMPTR76; /* RMPTR76 */ - union iodefine_reg32_t RMDF076; /* RMDF076 */ - union iodefine_reg32_t RMDF176; /* RMDF176 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID77; /* RMID77 */ - union iodefine_reg32_t RMPTR77; /* RMPTR77 */ - union iodefine_reg32_t RMDF077; /* RMDF077 */ - union iodefine_reg32_t RMDF177; /* RMDF177 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID78; /* RMID78 */ - union iodefine_reg32_t RMPTR78; /* RMPTR78 */ - union iodefine_reg32_t RMDF078; /* RMDF078 */ - union iodefine_reg32_t RMDF178; /* RMDF178 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID79; /* RMID79 */ - union iodefine_reg32_t RMPTR79; /* RMPTR79 */ - union iodefine_reg32_t RMDF079; /* RMDF079 */ - union iodefine_reg32_t RMDF179; /* RMDF179 */ - -/* end of struct st_rscan_from_rscan0rmidp */ - - volatile uint8_t dummy179[768]; /* */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID0; /* RFID0 */ - union iodefine_reg32_t RFPTR0; /* RFPTR0 */ - union iodefine_reg32_t RFDF00; /* RFDF00 */ - union iodefine_reg32_t RFDF10; /* RFDF10 */ - -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID1; /* RFID1 */ - union iodefine_reg32_t RFPTR1; /* RFPTR1 */ - union iodefine_reg32_t RFDF01; /* RFDF01 */ - union iodefine_reg32_t RFDF11; /* RFDF11 */ - -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID2; /* RFID2 */ - union iodefine_reg32_t RFPTR2; /* RFPTR2 */ - union iodefine_reg32_t RFDF02; /* RFDF02 */ - union iodefine_reg32_t RFDF12; /* RFDF12 */ - -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID3; /* RFID3 */ - union iodefine_reg32_t RFPTR3; /* RFPTR3 */ - union iodefine_reg32_t RFDF03; /* RFDF03 */ - union iodefine_reg32_t RFDF13; /* RFDF13 */ - -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID4; /* RFID4 */ - union iodefine_reg32_t RFPTR4; /* RFPTR4 */ - union iodefine_reg32_t RFDF04; /* RFDF04 */ - union iodefine_reg32_t RFDF14; /* RFDF14 */ - -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID5; /* RFID5 */ - union iodefine_reg32_t RFPTR5; /* RFPTR5 */ - union iodefine_reg32_t RFDF05; /* RFDF05 */ - union iodefine_reg32_t RFDF15; /* RFDF15 */ - -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID6; /* RFID6 */ - union iodefine_reg32_t RFPTR6; /* RFPTR6 */ - union iodefine_reg32_t RFDF06; /* RFDF06 */ - union iodefine_reg32_t RFDF16; /* RFDF16 */ - -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID7; /* RFID7 */ - union iodefine_reg32_t RFPTR7; /* RFPTR7 */ - union iodefine_reg32_t RFDF07; /* RFDF07 */ - union iodefine_reg32_t RFDF17; /* RFDF17 */ - -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID0; /* CFID0 */ - union iodefine_reg32_t CFPTR0; /* CFPTR0 */ - union iodefine_reg32_t CFDF00; /* CFDF00 */ - union iodefine_reg32_t CFDF10; /* CFDF10 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID1; /* CFID1 */ - union iodefine_reg32_t CFPTR1; /* CFPTR1 */ - union iodefine_reg32_t CFDF01; /* CFDF01 */ - union iodefine_reg32_t CFDF11; /* CFDF11 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID2; /* CFID2 */ - union iodefine_reg32_t CFPTR2; /* CFPTR2 */ - union iodefine_reg32_t CFDF02; /* CFDF02 */ - union iodefine_reg32_t CFDF12; /* CFDF12 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID3; /* CFID3 */ - union iodefine_reg32_t CFPTR3; /* CFPTR3 */ - union iodefine_reg32_t CFDF03; /* CFDF03 */ - union iodefine_reg32_t CFDF13; /* CFDF13 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID4; /* CFID4 */ - union iodefine_reg32_t CFPTR4; /* CFPTR4 */ - union iodefine_reg32_t CFDF04; /* CFDF04 */ - union iodefine_reg32_t CFDF14; /* CFDF14 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID5; /* CFID5 */ - union iodefine_reg32_t CFPTR5; /* CFPTR5 */ - union iodefine_reg32_t CFDF05; /* CFDF05 */ - union iodefine_reg32_t CFDF15; /* CFDF15 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID6; /* CFID6 */ - union iodefine_reg32_t CFPTR6; /* CFPTR6 */ - union iodefine_reg32_t CFDF06; /* CFDF06 */ - union iodefine_reg32_t CFDF16; /* CFDF16 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID7; /* CFID7 */ - union iodefine_reg32_t CFPTR7; /* CFPTR7 */ - union iodefine_reg32_t CFDF07; /* CFDF07 */ - union iodefine_reg32_t CFDF17; /* CFDF17 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID8; /* CFID8 */ - union iodefine_reg32_t CFPTR8; /* CFPTR8 */ - union iodefine_reg32_t CFDF08; /* CFDF08 */ - union iodefine_reg32_t CFDF18; /* CFDF18 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID9; /* CFID9 */ - union iodefine_reg32_t CFPTR9; /* CFPTR9 */ - union iodefine_reg32_t CFDF09; /* CFDF09 */ - union iodefine_reg32_t CFDF19; /* CFDF19 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID10; /* CFID10 */ - union iodefine_reg32_t CFPTR10; /* CFPTR10 */ - union iodefine_reg32_t CFDF010; /* CFDF010 */ - union iodefine_reg32_t CFDF110; /* CFDF110 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID11; /* CFID11 */ - union iodefine_reg32_t CFPTR11; /* CFPTR11 */ - union iodefine_reg32_t CFDF011; /* CFDF011 */ - union iodefine_reg32_t CFDF111; /* CFDF111 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID12; /* CFID12 */ - union iodefine_reg32_t CFPTR12; /* CFPTR12 */ - union iodefine_reg32_t CFDF012; /* CFDF012 */ - union iodefine_reg32_t CFDF112; /* CFDF112 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID13; /* CFID13 */ - union iodefine_reg32_t CFPTR13; /* CFPTR13 */ - union iodefine_reg32_t CFDF013; /* CFDF013 */ - union iodefine_reg32_t CFDF113; /* CFDF113 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID14; /* CFID14 */ - union iodefine_reg32_t CFPTR14; /* CFPTR14 */ - union iodefine_reg32_t CFDF014; /* CFDF014 */ - union iodefine_reg32_t CFDF114; /* CFDF114 */ - -/* end of struct st_rscan_from_rscan0cfidm */ - - volatile uint8_t dummy180[144]; /* */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID0; /* TMID0 */ - union iodefine_reg32_t TMPTR0; /* TMPTR0 */ - union iodefine_reg32_t TMDF00; /* TMDF00 */ - union iodefine_reg32_t TMDF10; /* TMDF10 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID1; /* TMID1 */ - union iodefine_reg32_t TMPTR1; /* TMPTR1 */ - union iodefine_reg32_t TMDF01; /* TMDF01 */ - union iodefine_reg32_t TMDF11; /* TMDF11 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID2; /* TMID2 */ - union iodefine_reg32_t TMPTR2; /* TMPTR2 */ - union iodefine_reg32_t TMDF02; /* TMDF02 */ - union iodefine_reg32_t TMDF12; /* TMDF12 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID3; /* TMID3 */ - union iodefine_reg32_t TMPTR3; /* TMPTR3 */ - union iodefine_reg32_t TMDF03; /* TMDF03 */ - union iodefine_reg32_t TMDF13; /* TMDF13 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID4; /* TMID4 */ - union iodefine_reg32_t TMPTR4; /* TMPTR4 */ - union iodefine_reg32_t TMDF04; /* TMDF04 */ - union iodefine_reg32_t TMDF14; /* TMDF14 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID5; /* TMID5 */ - union iodefine_reg32_t TMPTR5; /* TMPTR5 */ - union iodefine_reg32_t TMDF05; /* TMDF05 */ - union iodefine_reg32_t TMDF15; /* TMDF15 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID6; /* TMID6 */ - union iodefine_reg32_t TMPTR6; /* TMPTR6 */ - union iodefine_reg32_t TMDF06; /* TMDF06 */ - union iodefine_reg32_t TMDF16; /* TMDF16 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID7; /* TMID7 */ - union iodefine_reg32_t TMPTR7; /* TMPTR7 */ - union iodefine_reg32_t TMDF07; /* TMDF07 */ - union iodefine_reg32_t TMDF17; /* TMDF17 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID8; /* TMID8 */ - union iodefine_reg32_t TMPTR8; /* TMPTR8 */ - union iodefine_reg32_t TMDF08; /* TMDF08 */ - union iodefine_reg32_t TMDF18; /* TMDF18 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID9; /* TMID9 */ - union iodefine_reg32_t TMPTR9; /* TMPTR9 */ - union iodefine_reg32_t TMDF09; /* TMDF09 */ - union iodefine_reg32_t TMDF19; /* TMDF19 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID10; /* TMID10 */ - union iodefine_reg32_t TMPTR10; /* TMPTR10 */ - union iodefine_reg32_t TMDF010; /* TMDF010 */ - union iodefine_reg32_t TMDF110; /* TMDF110 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID11; /* TMID11 */ - union iodefine_reg32_t TMPTR11; /* TMPTR11 */ - union iodefine_reg32_t TMDF011; /* TMDF011 */ - union iodefine_reg32_t TMDF111; /* TMDF111 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID12; /* TMID12 */ - union iodefine_reg32_t TMPTR12; /* TMPTR12 */ - union iodefine_reg32_t TMDF012; /* TMDF012 */ - union iodefine_reg32_t TMDF112; /* TMDF112 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID13; /* TMID13 */ - union iodefine_reg32_t TMPTR13; /* TMPTR13 */ - union iodefine_reg32_t TMDF013; /* TMDF013 */ - union iodefine_reg32_t TMDF113; /* TMDF113 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID14; /* TMID14 */ - union iodefine_reg32_t TMPTR14; /* TMPTR14 */ - union iodefine_reg32_t TMDF014; /* TMDF014 */ - union iodefine_reg32_t TMDF114; /* TMDF114 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID15; /* TMID15 */ - union iodefine_reg32_t TMPTR15; /* TMPTR15 */ - union iodefine_reg32_t TMDF015; /* TMDF015 */ - union iodefine_reg32_t TMDF115; /* TMDF115 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID16; /* TMID16 */ - union iodefine_reg32_t TMPTR16; /* TMPTR16 */ - union iodefine_reg32_t TMDF016; /* TMDF016 */ - union iodefine_reg32_t TMDF116; /* TMDF116 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID17; /* TMID17 */ - union iodefine_reg32_t TMPTR17; /* TMPTR17 */ - union iodefine_reg32_t TMDF017; /* TMDF017 */ - union iodefine_reg32_t TMDF117; /* TMDF117 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID18; /* TMID18 */ - union iodefine_reg32_t TMPTR18; /* TMPTR18 */ - union iodefine_reg32_t TMDF018; /* TMDF018 */ - union iodefine_reg32_t TMDF118; /* TMDF118 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID19; /* TMID19 */ - union iodefine_reg32_t TMPTR19; /* TMPTR19 */ - union iodefine_reg32_t TMDF019; /* TMDF019 */ - union iodefine_reg32_t TMDF119; /* TMDF119 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID20; /* TMID20 */ - union iodefine_reg32_t TMPTR20; /* TMPTR20 */ - union iodefine_reg32_t TMDF020; /* TMDF020 */ - union iodefine_reg32_t TMDF120; /* TMDF120 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID21; /* TMID21 */ - union iodefine_reg32_t TMPTR21; /* TMPTR21 */ - union iodefine_reg32_t TMDF021; /* TMDF021 */ - union iodefine_reg32_t TMDF121; /* TMDF121 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID22; /* TMID22 */ - union iodefine_reg32_t TMPTR22; /* TMPTR22 */ - union iodefine_reg32_t TMDF022; /* TMDF022 */ - union iodefine_reg32_t TMDF122; /* TMDF122 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID23; /* TMID23 */ - union iodefine_reg32_t TMPTR23; /* TMPTR23 */ - union iodefine_reg32_t TMDF023; /* TMDF023 */ - union iodefine_reg32_t TMDF123; /* TMDF123 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID24; /* TMID24 */ - union iodefine_reg32_t TMPTR24; /* TMPTR24 */ - union iodefine_reg32_t TMDF024; /* TMDF024 */ - union iodefine_reg32_t TMDF124; /* TMDF124 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID25; /* TMID25 */ - union iodefine_reg32_t TMPTR25; /* TMPTR25 */ - union iodefine_reg32_t TMDF025; /* TMDF025 */ - union iodefine_reg32_t TMDF125; /* TMDF125 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID26; /* TMID26 */ - union iodefine_reg32_t TMPTR26; /* TMPTR26 */ - union iodefine_reg32_t TMDF026; /* TMDF026 */ - union iodefine_reg32_t TMDF126; /* TMDF126 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID27; /* TMID27 */ - union iodefine_reg32_t TMPTR27; /* TMPTR27 */ - union iodefine_reg32_t TMDF027; /* TMDF027 */ - union iodefine_reg32_t TMDF127; /* TMDF127 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID28; /* TMID28 */ - union iodefine_reg32_t TMPTR28; /* TMPTR28 */ - union iodefine_reg32_t TMDF028; /* TMDF028 */ - union iodefine_reg32_t TMDF128; /* TMDF128 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID29; /* TMID29 */ - union iodefine_reg32_t TMPTR29; /* TMPTR29 */ - union iodefine_reg32_t TMDF029; /* TMDF029 */ - union iodefine_reg32_t TMDF129; /* TMDF129 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID30; /* TMID30 */ - union iodefine_reg32_t TMPTR30; /* TMPTR30 */ - union iodefine_reg32_t TMDF030; /* TMDF030 */ - union iodefine_reg32_t TMDF130; /* TMDF130 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID31; /* TMID31 */ - union iodefine_reg32_t TMPTR31; /* TMPTR31 */ - union iodefine_reg32_t TMDF031; /* TMDF031 */ - union iodefine_reg32_t TMDF131; /* TMDF131 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID32; /* TMID32 */ - union iodefine_reg32_t TMPTR32; /* TMPTR32 */ - union iodefine_reg32_t TMDF032; /* TMDF032 */ - union iodefine_reg32_t TMDF132; /* TMDF132 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID33; /* TMID33 */ - union iodefine_reg32_t TMPTR33; /* TMPTR33 */ - union iodefine_reg32_t TMDF033; /* TMDF033 */ - union iodefine_reg32_t TMDF133; /* TMDF133 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID34; /* TMID34 */ - union iodefine_reg32_t TMPTR34; /* TMPTR34 */ - union iodefine_reg32_t TMDF034; /* TMDF034 */ - union iodefine_reg32_t TMDF134; /* TMDF134 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID35; /* TMID35 */ - union iodefine_reg32_t TMPTR35; /* TMPTR35 */ - union iodefine_reg32_t TMDF035; /* TMDF035 */ - union iodefine_reg32_t TMDF135; /* TMDF135 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID36; /* TMID36 */ - union iodefine_reg32_t TMPTR36; /* TMPTR36 */ - union iodefine_reg32_t TMDF036; /* TMDF036 */ - union iodefine_reg32_t TMDF136; /* TMDF136 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID37; /* TMID37 */ - union iodefine_reg32_t TMPTR37; /* TMPTR37 */ - union iodefine_reg32_t TMDF037; /* TMDF037 */ - union iodefine_reg32_t TMDF137; /* TMDF137 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID38; /* TMID38 */ - union iodefine_reg32_t TMPTR38; /* TMPTR38 */ - union iodefine_reg32_t TMDF038; /* TMDF038 */ - union iodefine_reg32_t TMDF138; /* TMDF138 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID39; /* TMID39 */ - union iodefine_reg32_t TMPTR39; /* TMPTR39 */ - union iodefine_reg32_t TMDF039; /* TMDF039 */ - union iodefine_reg32_t TMDF139; /* TMDF139 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID40; /* TMID40 */ - union iodefine_reg32_t TMPTR40; /* TMPTR40 */ - union iodefine_reg32_t TMDF040; /* TMDF040 */ - union iodefine_reg32_t TMDF140; /* TMDF140 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID41; /* TMID41 */ - union iodefine_reg32_t TMPTR41; /* TMPTR41 */ - union iodefine_reg32_t TMDF041; /* TMDF041 */ - union iodefine_reg32_t TMDF141; /* TMDF141 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID42; /* TMID42 */ - union iodefine_reg32_t TMPTR42; /* TMPTR42 */ - union iodefine_reg32_t TMDF042; /* TMDF042 */ - union iodefine_reg32_t TMDF142; /* TMDF142 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID43; /* TMID43 */ - union iodefine_reg32_t TMPTR43; /* TMPTR43 */ - union iodefine_reg32_t TMDF043; /* TMDF043 */ - union iodefine_reg32_t TMDF143; /* TMDF143 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID44; /* TMID44 */ - union iodefine_reg32_t TMPTR44; /* TMPTR44 */ - union iodefine_reg32_t TMDF044; /* TMDF044 */ - union iodefine_reg32_t TMDF144; /* TMDF144 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID45; /* TMID45 */ - union iodefine_reg32_t TMPTR45; /* TMPTR45 */ - union iodefine_reg32_t TMDF045; /* TMDF045 */ - union iodefine_reg32_t TMDF145; /* TMDF145 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID46; /* TMID46 */ - union iodefine_reg32_t TMPTR46; /* TMPTR46 */ - union iodefine_reg32_t TMDF046; /* TMDF046 */ - union iodefine_reg32_t TMDF146; /* TMDF146 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID47; /* TMID47 */ - union iodefine_reg32_t TMPTR47; /* TMPTR47 */ - union iodefine_reg32_t TMDF047; /* TMDF047 */ - union iodefine_reg32_t TMDF147; /* TMDF147 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID48; /* TMID48 */ - union iodefine_reg32_t TMPTR48; /* TMPTR48 */ - union iodefine_reg32_t TMDF048; /* TMDF048 */ - union iodefine_reg32_t TMDF148; /* TMDF148 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID49; /* TMID49 */ - union iodefine_reg32_t TMPTR49; /* TMPTR49 */ - union iodefine_reg32_t TMDF049; /* TMDF049 */ - union iodefine_reg32_t TMDF149; /* TMDF149 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID50; /* TMID50 */ - union iodefine_reg32_t TMPTR50; /* TMPTR50 */ - union iodefine_reg32_t TMDF050; /* TMDF050 */ - union iodefine_reg32_t TMDF150; /* TMDF150 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID51; /* TMID51 */ - union iodefine_reg32_t TMPTR51; /* TMPTR51 */ - union iodefine_reg32_t TMDF051; /* TMDF051 */ - union iodefine_reg32_t TMDF151; /* TMDF151 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID52; /* TMID52 */ - union iodefine_reg32_t TMPTR52; /* TMPTR52 */ - union iodefine_reg32_t TMDF052; /* TMDF052 */ - union iodefine_reg32_t TMDF152; /* TMDF152 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID53; /* TMID53 */ - union iodefine_reg32_t TMPTR53; /* TMPTR53 */ - union iodefine_reg32_t TMDF053; /* TMDF053 */ - union iodefine_reg32_t TMDF153; /* TMDF153 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID54; /* TMID54 */ - union iodefine_reg32_t TMPTR54; /* TMPTR54 */ - union iodefine_reg32_t TMDF054; /* TMDF054 */ - union iodefine_reg32_t TMDF154; /* TMDF154 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID55; /* TMID55 */ - union iodefine_reg32_t TMPTR55; /* TMPTR55 */ - union iodefine_reg32_t TMDF055; /* TMDF055 */ - union iodefine_reg32_t TMDF155; /* TMDF155 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID56; /* TMID56 */ - union iodefine_reg32_t TMPTR56; /* TMPTR56 */ - union iodefine_reg32_t TMDF056; /* TMDF056 */ - union iodefine_reg32_t TMDF156; /* TMDF156 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID57; /* TMID57 */ - union iodefine_reg32_t TMPTR57; /* TMPTR57 */ - union iodefine_reg32_t TMDF057; /* TMDF057 */ - union iodefine_reg32_t TMDF157; /* TMDF157 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID58; /* TMID58 */ - union iodefine_reg32_t TMPTR58; /* TMPTR58 */ - union iodefine_reg32_t TMDF058; /* TMDF058 */ - union iodefine_reg32_t TMDF158; /* TMDF158 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID59; /* TMID59 */ - union iodefine_reg32_t TMPTR59; /* TMPTR59 */ - union iodefine_reg32_t TMDF059; /* TMDF059 */ - union iodefine_reg32_t TMDF159; /* TMDF159 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID60; /* TMID60 */ - union iodefine_reg32_t TMPTR60; /* TMPTR60 */ - union iodefine_reg32_t TMDF060; /* TMDF060 */ - union iodefine_reg32_t TMDF160; /* TMDF160 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID61; /* TMID61 */ - union iodefine_reg32_t TMPTR61; /* TMPTR61 */ - union iodefine_reg32_t TMDF061; /* TMDF061 */ - union iodefine_reg32_t TMDF161; /* TMDF161 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID62; /* TMID62 */ - union iodefine_reg32_t TMPTR62; /* TMPTR62 */ - union iodefine_reg32_t TMDF062; /* TMDF062 */ - union iodefine_reg32_t TMDF162; /* TMDF162 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID63; /* TMID63 */ - union iodefine_reg32_t TMPTR63; /* TMPTR63 */ - union iodefine_reg32_t TMDF063; /* TMDF063 */ - union iodefine_reg32_t TMDF163; /* TMDF163 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID64; /* TMID64 */ - union iodefine_reg32_t TMPTR64; /* TMPTR64 */ - union iodefine_reg32_t TMDF064; /* TMDF064 */ - union iodefine_reg32_t TMDF164; /* TMDF164 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID65; /* TMID65 */ - union iodefine_reg32_t TMPTR65; /* TMPTR65 */ - union iodefine_reg32_t TMDF065; /* TMDF065 */ - union iodefine_reg32_t TMDF165; /* TMDF165 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID66; /* TMID66 */ - union iodefine_reg32_t TMPTR66; /* TMPTR66 */ - union iodefine_reg32_t TMDF066; /* TMDF066 */ - union iodefine_reg32_t TMDF166; /* TMDF166 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID67; /* TMID67 */ - union iodefine_reg32_t TMPTR67; /* TMPTR67 */ - union iodefine_reg32_t TMDF067; /* TMDF067 */ - union iodefine_reg32_t TMDF167; /* TMDF167 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID68; /* TMID68 */ - union iodefine_reg32_t TMPTR68; /* TMPTR68 */ - union iodefine_reg32_t TMDF068; /* TMDF068 */ - union iodefine_reg32_t TMDF168; /* TMDF168 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID69; /* TMID69 */ - union iodefine_reg32_t TMPTR69; /* TMPTR69 */ - union iodefine_reg32_t TMDF069; /* TMDF069 */ - union iodefine_reg32_t TMDF169; /* TMDF169 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID70; /* TMID70 */ - union iodefine_reg32_t TMPTR70; /* TMPTR70 */ - union iodefine_reg32_t TMDF070; /* TMDF070 */ - union iodefine_reg32_t TMDF170; /* TMDF170 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID71; /* TMID71 */ - union iodefine_reg32_t TMPTR71; /* TMPTR71 */ - union iodefine_reg32_t TMDF071; /* TMDF071 */ - union iodefine_reg32_t TMDF171; /* TMDF171 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID72; /* TMID72 */ - union iodefine_reg32_t TMPTR72; /* TMPTR72 */ - union iodefine_reg32_t TMDF072; /* TMDF072 */ - union iodefine_reg32_t TMDF172; /* TMDF172 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID73; /* TMID73 */ - union iodefine_reg32_t TMPTR73; /* TMPTR73 */ - union iodefine_reg32_t TMDF073; /* TMDF073 */ - union iodefine_reg32_t TMDF173; /* TMDF173 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID74; /* TMID74 */ - union iodefine_reg32_t TMPTR74; /* TMPTR74 */ - union iodefine_reg32_t TMDF074; /* TMDF074 */ - union iodefine_reg32_t TMDF174; /* TMDF174 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID75; /* TMID75 */ - union iodefine_reg32_t TMPTR75; /* TMPTR75 */ - union iodefine_reg32_t TMDF075; /* TMDF075 */ - union iodefine_reg32_t TMDF175; /* TMDF175 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID76; /* TMID76 */ - union iodefine_reg32_t TMPTR76; /* TMPTR76 */ - union iodefine_reg32_t TMDF076; /* TMDF076 */ - union iodefine_reg32_t TMDF176; /* TMDF176 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID77; /* TMID77 */ - union iodefine_reg32_t TMPTR77; /* TMPTR77 */ - union iodefine_reg32_t TMDF077; /* TMDF077 */ - union iodefine_reg32_t TMDF177; /* TMDF177 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID78; /* TMID78 */ - union iodefine_reg32_t TMPTR78; /* TMPTR78 */ - union iodefine_reg32_t TMDF078; /* TMDF078 */ - union iodefine_reg32_t TMDF178; /* TMDF178 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID79; /* TMID79 */ - union iodefine_reg32_t TMPTR79; /* TMPTR79 */ - union iodefine_reg32_t TMDF079; /* TMDF079 */ - union iodefine_reg32_t TMDF179; /* TMDF179 */ - -/* end of struct st_rscan_from_rscan0tmidp */ - - volatile uint8_t dummy181[768]; /* */ - -/* #define RSCAN0_THLACC0_COUNT (5) */ - union iodefine_reg32_t THLACC0; /* THLACC0 */ - union iodefine_reg32_t THLACC1; /* THLACC1 */ - union iodefine_reg32_t THLACC2; /* THLACC2 */ - union iodefine_reg32_t THLACC3; /* THLACC3 */ - union iodefine_reg32_t THLACC4; /* THLACC4 */ - -} r_io_rscan0_t; - - -typedef struct st_rscan_from_rscan0cncfg -{ - - union iodefine_reg32_t CnCFG; /* CnCFG */ - union iodefine_reg32_t CnCTR; /* CnCTR */ - union iodefine_reg32_t CnSTS; /* CnSTS */ - union iodefine_reg32_t CnERFL; /* CnERFL */ -} r_io_rscan_from_rscan0cncfg_t; - - -typedef struct st_rscan_from_rscan0gaflidj -{ - - union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ - union iodefine_reg32_t GAFLMj; /* GAFLMj */ - union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ - union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ -} r_io_rscan_from_rscan0gaflidj_t; - - -typedef struct st_rscan_from_rscan0rmidp -{ - - union iodefine_reg32_t RMIDp; /* RMIDp */ - union iodefine_reg32_t RMPTRp; /* RMPTRp */ - union iodefine_reg32_t RMDF0p; /* RMDF0p */ - union iodefine_reg32_t RMDF1p; /* RMDF1p */ -} r_io_rscan_from_rscan0rmidp_t; - - -typedef struct st_rscan_from_rscan0rfidm -{ - - union iodefine_reg32_t RFIDm; /* RFIDm */ - union iodefine_reg32_t RFPTRm; /* RFPTRm */ - union iodefine_reg32_t RFDF0m; /* RFDF0m */ - union iodefine_reg32_t RFDF1m; /* RFDF1m */ -} r_io_rscan_from_rscan0rfidm_t; - - -typedef struct st_rscan_from_rscan0tmidp -{ - - union iodefine_reg32_t TMIDp; /* TMIDp */ - union iodefine_reg32_t TMPTRp; /* TMPTRp */ - union iodefine_reg32_t TMDF0p; /* TMDF0p */ - union iodefine_reg32_t TMDF1p; /* TMDF1p */ -} r_io_rscan_from_rscan0tmidp_t; - - -typedef struct st_rscan_from_rscan0cfidm -{ - - union iodefine_reg32_t CFIDm; /* CFIDm */ - union iodefine_reg32_t CFPTRm; /* CFPTRm */ - union iodefine_reg32_t CFDF0m; /* CFDF0m */ - union iodefine_reg32_t CFDF1m; /* CFDF1m */ -} r_io_rscan_from_rscan0cfidm_t; - - -/* Channel array defines of RSCAN0 (2)*/ -#ifdef DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS -volatile struct st_rscan_from_rscan0cfidm* RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */ - -#ifdef DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS -volatile struct st_rscan_from_rscan0tmidp* RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */ - -#ifdef DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS -volatile struct st_rscan_from_rscan0rfidm* RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */ - -#ifdef DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS -volatile struct st_rscan_from_rscan0rmidp* RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */ - -#ifdef DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS -volatile struct st_rscan_from_rscan0gaflidj* RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */ - -#ifdef DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS -volatile struct st_rscan_from_rscan0cncfg* RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */ -/* End of channel array defines of RSCAN0 (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h deleted file mode 100644 index 5c63e293467..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h +++ /dev/null @@ -1,224 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rspi_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef RSPI_IODEFINE_H -#define RSPI_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ -#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ -#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ -#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ -#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ - - -/* Start of channel array defines of RSPI */ - -/* Channel array defines of RSPI */ -/*(Sample) value = RSPI[ channel ]->SPCR; */ -#define RSPI_COUNT (5) -#define RSPI_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of RSPI */ - - -#define SPCR_0 (RSPI0.SPCR) -#define SSLP_0 (RSPI0.SSLP) -#define SPPCR_0 (RSPI0.SPPCR) -#define SPSR_0 (RSPI0.SPSR) -#define SPDR_0 (RSPI0.SPDR.UINT32) -#define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L]) -#define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H]) -#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL]) -#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH]) -#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL]) -#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH]) -#define SPSCR_0 (RSPI0.SPSCR) -#define SPSSR_0 (RSPI0.SPSSR) -#define SPBR_0 (RSPI0.SPBR) -#define SPDCR_0 (RSPI0.SPDCR) -#define SPCKD_0 (RSPI0.SPCKD) -#define SSLND_0 (RSPI0.SSLND) -#define SPND_0 (RSPI0.SPND) -#define SPCMD0_0 (RSPI0.SPCMD0) -#define SPCMD1_0 (RSPI0.SPCMD1) -#define SPCMD2_0 (RSPI0.SPCMD2) -#define SPCMD3_0 (RSPI0.SPCMD3) -#define SPBFCR_0 (RSPI0.SPBFCR) -#define SPBFDR_0 (RSPI0.SPBFDR) -#define SPCR_1 (RSPI1.SPCR) -#define SSLP_1 (RSPI1.SSLP) -#define SPPCR_1 (RSPI1.SPPCR) -#define SPSR_1 (RSPI1.SPSR) -#define SPDR_1 (RSPI1.SPDR.UINT32) -#define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L]) -#define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H]) -#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL]) -#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH]) -#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL]) -#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH]) -#define SPSCR_1 (RSPI1.SPSCR) -#define SPSSR_1 (RSPI1.SPSSR) -#define SPBR_1 (RSPI1.SPBR) -#define SPDCR_1 (RSPI1.SPDCR) -#define SPCKD_1 (RSPI1.SPCKD) -#define SSLND_1 (RSPI1.SSLND) -#define SPND_1 (RSPI1.SPND) -#define SPCMD0_1 (RSPI1.SPCMD0) -#define SPCMD1_1 (RSPI1.SPCMD1) -#define SPCMD2_1 (RSPI1.SPCMD2) -#define SPCMD3_1 (RSPI1.SPCMD3) -#define SPBFCR_1 (RSPI1.SPBFCR) -#define SPBFDR_1 (RSPI1.SPBFDR) -#define SPCR_2 (RSPI2.SPCR) -#define SSLP_2 (RSPI2.SSLP) -#define SPPCR_2 (RSPI2.SPPCR) -#define SPSR_2 (RSPI2.SPSR) -#define SPDR_2 (RSPI2.SPDR.UINT32) -#define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L]) -#define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H]) -#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL]) -#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH]) -#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL]) -#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH]) -#define SPSCR_2 (RSPI2.SPSCR) -#define SPSSR_2 (RSPI2.SPSSR) -#define SPBR_2 (RSPI2.SPBR) -#define SPDCR_2 (RSPI2.SPDCR) -#define SPCKD_2 (RSPI2.SPCKD) -#define SSLND_2 (RSPI2.SSLND) -#define SPND_2 (RSPI2.SPND) -#define SPCMD0_2 (RSPI2.SPCMD0) -#define SPCMD1_2 (RSPI2.SPCMD1) -#define SPCMD2_2 (RSPI2.SPCMD2) -#define SPCMD3_2 (RSPI2.SPCMD3) -#define SPBFCR_2 (RSPI2.SPBFCR) -#define SPBFDR_2 (RSPI2.SPBFDR) -#define SPCR_3 (RSPI3.SPCR) -#define SSLP_3 (RSPI3.SSLP) -#define SPPCR_3 (RSPI3.SPPCR) -#define SPSR_3 (RSPI3.SPSR) -#define SPDR_3 (RSPI3.SPDR.UINT32) -#define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L]) -#define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H]) -#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL]) -#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH]) -#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL]) -#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH]) -#define SPSCR_3 (RSPI3.SPSCR) -#define SPSSR_3 (RSPI3.SPSSR) -#define SPBR_3 (RSPI3.SPBR) -#define SPDCR_3 (RSPI3.SPDCR) -#define SPCKD_3 (RSPI3.SPCKD) -#define SSLND_3 (RSPI3.SSLND) -#define SPND_3 (RSPI3.SPND) -#define SPCMD0_3 (RSPI3.SPCMD0) -#define SPCMD1_3 (RSPI3.SPCMD1) -#define SPCMD2_3 (RSPI3.SPCMD2) -#define SPCMD3_3 (RSPI3.SPCMD3) -#define SPBFCR_3 (RSPI3.SPBFCR) -#define SPBFDR_3 (RSPI3.SPBFDR) -#define SPCR_4 (RSPI4.SPCR) -#define SSLP_4 (RSPI4.SSLP) -#define SPPCR_4 (RSPI4.SPPCR) -#define SPSR_4 (RSPI4.SPSR) -#define SPDR_4 (RSPI4.SPDR.UINT32) -#define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L]) -#define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H]) -#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL]) -#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH]) -#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL]) -#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH]) -#define SPSCR_4 (RSPI4.SPSCR) -#define SPSSR_4 (RSPI4.SPSSR) -#define SPBR_4 (RSPI4.SPBR) -#define SPDCR_4 (RSPI4.SPDCR) -#define SPCKD_4 (RSPI4.SPCKD) -#define SSLND_4 (RSPI4.SSLND) -#define SPND_4 (RSPI4.SPND) -#define SPCMD0_4 (RSPI4.SPCMD0) -#define SPCMD1_4 (RSPI4.SPCMD1) -#define SPCMD2_4 (RSPI4.SPCMD2) -#define SPCMD3_4 (RSPI4.SPCMD3) -#define SPBFCR_4 (RSPI4.SPBFCR) -#define SPBFDR_4 (RSPI4.SPBFDR) - -#define SPCMD_COUNT (4) - - -typedef struct st_rspi -{ - /* RSPI */ - volatile uint8_t SPCR; /* SPCR */ - volatile uint8_t SSLP; /* SSLP */ - volatile uint8_t SPPCR; /* SPPCR */ - volatile uint8_t SPSR; /* SPSR */ - union iodefine_reg32_t SPDR; /* SPDR */ - - volatile uint8_t SPSCR; /* SPSCR */ - volatile uint8_t SPSSR; /* SPSSR */ - volatile uint8_t SPBR; /* SPBR */ - volatile uint8_t SPDCR; /* SPDCR */ - volatile uint8_t SPCKD; /* SPCKD */ - volatile uint8_t SSLND; /* SSLND */ - volatile uint8_t SPND; /* SPND */ - volatile uint8_t dummy1[1]; /* */ - -/* #define SPCMD_COUNT (4) */ - volatile uint16_t SPCMD0; /* SPCMD0 */ - volatile uint16_t SPCMD1; /* SPCMD1 */ - volatile uint16_t SPCMD2; /* SPCMD2 */ - volatile uint16_t SPCMD3; /* SPCMD3 */ - volatile uint8_t dummy2[8]; /* */ - volatile uint8_t SPBFCR; /* SPBFCR */ - volatile uint8_t dummy3[1]; /* */ - volatile uint16_t SPBFDR; /* SPBFDR */ -} r_io_rspi_t; - - -/* Channel array defines of RSPI (2)*/ -#ifdef DECLARE_RSPI_CHANNELS -volatile struct st_rspi* RSPI[ RSPI_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - RSPI_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_RSPI_CHANNELS */ -/* End of channel array defines of RSPI (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h deleted file mode 100644 index 1df2c7c3d17..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h +++ /dev/null @@ -1,111 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rtc_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef RTC_IODEFINE_H -#define RTC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ - - -#define RTCR64CNT (RTC.R64CNT) -#define RTCRSECCNT (RTC.RSECCNT) -#define RTCRMINCNT (RTC.RMINCNT) -#define RTCRHRCNT (RTC.RHRCNT) -#define RTCRWKCNT (RTC.RWKCNT) -#define RTCRDAYCNT (RTC.RDAYCNT) -#define RTCRMONCNT (RTC.RMONCNT) -#define RTCRYRCNT (RTC.RYRCNT) -#define RTCRSECAR (RTC.RSECAR) -#define RTCRMINAR (RTC.RMINAR) -#define RTCRHRAR (RTC.RHRAR) -#define RTCRWKAR (RTC.RWKAR) -#define RTCRDAYAR (RTC.RDAYAR) -#define RTCRMONAR (RTC.RMONAR) -#define RTCRCR1 (RTC.RCR1) -#define RTCRCR2 (RTC.RCR2) -#define RTCRYRAR (RTC.RYRAR) -#define RTCRCR3 (RTC.RCR3) -#define RTCRCR5 (RTC.RCR5) -#define RTCRFRH (RTC.RFRH) -#define RTCRFRL (RTC.RFRL) - - -typedef struct st_rtc -{ - /* RTC */ - volatile uint8_t R64CNT; /* R64CNT */ - volatile uint8_t dummy537[1]; /* */ - volatile uint8_t RSECCNT; /* RSECCNT */ - volatile uint8_t dummy538[1]; /* */ - volatile uint8_t RMINCNT; /* RMINCNT */ - volatile uint8_t dummy539[1]; /* */ - volatile uint8_t RHRCNT; /* RHRCNT */ - volatile uint8_t dummy540[1]; /* */ - volatile uint8_t RWKCNT; /* RWKCNT */ - volatile uint8_t dummy541[1]; /* */ - volatile uint8_t RDAYCNT; /* RDAYCNT */ - volatile uint8_t dummy542[1]; /* */ - volatile uint8_t RMONCNT; /* RMONCNT */ - volatile uint8_t dummy543[1]; /* */ - volatile uint16_t RYRCNT; /* RYRCNT */ - volatile uint8_t RSECAR; /* RSECAR */ - volatile uint8_t dummy544[1]; /* */ - volatile uint8_t RMINAR; /* RMINAR */ - volatile uint8_t dummy545[1]; /* */ - volatile uint8_t RHRAR; /* RHRAR */ - volatile uint8_t dummy546[1]; /* */ - volatile uint8_t RWKAR; /* RWKAR */ - volatile uint8_t dummy547[1]; /* */ - volatile uint8_t RDAYAR; /* RDAYAR */ - volatile uint8_t dummy548[1]; /* */ - volatile uint8_t RMONAR; /* RMONAR */ - volatile uint8_t dummy549[1]; /* */ - volatile uint8_t RCR1; /* RCR1 */ - volatile uint8_t dummy550[1]; /* */ - volatile uint8_t RCR2; /* RCR2 */ - volatile uint8_t dummy551[1]; /* */ - volatile uint16_t RYRAR; /* RYRAR */ - volatile uint8_t dummy552[2]; /* */ - volatile uint8_t RCR3; /* RCR3 */ - volatile uint8_t dummy553[1]; /* */ - volatile uint8_t RCR5; /* RCR5 */ - volatile uint8_t dummy554[3]; /* */ - volatile uint16_t RFRH; /* RFRH */ - volatile uint16_t RFRL; /* RFRL */ -} r_io_rtc_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h deleted file mode 100644 index de594577e2a..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h +++ /dev/null @@ -1,190 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : scif_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef SCIF_IODEFINE_H -#define SCIF_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ -#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ -#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ -#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ -#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ -#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ -#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ -#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ - - -/* Start of channel array defines of SCIF */ - -/* Channel array defines of SCIF */ -/*(Sample) value = SCIF[ channel ]->SCSMR; */ -#define SCIF_COUNT (8) -#define SCIF_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of SCIF */ - - -#define SCSMR_0 (SCIF0.SCSMR) -#define SCBRR_0 (SCIF0.SCBRR) -#define SCSCR_0 (SCIF0.SCSCR) -#define SCFTDR_0 (SCIF0.SCFTDR) -#define SCFSR_0 (SCIF0.SCFSR) -#define SCFRDR_0 (SCIF0.SCFRDR) -#define SCFCR_0 (SCIF0.SCFCR) -#define SCFDR_0 (SCIF0.SCFDR) -#define SCSPTR_0 (SCIF0.SCSPTR) -#define SCLSR_0 (SCIF0.SCLSR) -#define SCEMR_0 (SCIF0.SCEMR) -#define SCSMR_1 (SCIF1.SCSMR) -#define SCBRR_1 (SCIF1.SCBRR) -#define SCSCR_1 (SCIF1.SCSCR) -#define SCFTDR_1 (SCIF1.SCFTDR) -#define SCFSR_1 (SCIF1.SCFSR) -#define SCFRDR_1 (SCIF1.SCFRDR) -#define SCFCR_1 (SCIF1.SCFCR) -#define SCFDR_1 (SCIF1.SCFDR) -#define SCSPTR_1 (SCIF1.SCSPTR) -#define SCLSR_1 (SCIF1.SCLSR) -#define SCEMR_1 (SCIF1.SCEMR) -#define SCSMR_2 (SCIF2.SCSMR) -#define SCBRR_2 (SCIF2.SCBRR) -#define SCSCR_2 (SCIF2.SCSCR) -#define SCFTDR_2 (SCIF2.SCFTDR) -#define SCFSR_2 (SCIF2.SCFSR) -#define SCFRDR_2 (SCIF2.SCFRDR) -#define SCFCR_2 (SCIF2.SCFCR) -#define SCFDR_2 (SCIF2.SCFDR) -#define SCSPTR_2 (SCIF2.SCSPTR) -#define SCLSR_2 (SCIF2.SCLSR) -#define SCEMR_2 (SCIF2.SCEMR) -#define SCSMR_3 (SCIF3.SCSMR) -#define SCBRR_3 (SCIF3.SCBRR) -#define SCSCR_3 (SCIF3.SCSCR) -#define SCFTDR_3 (SCIF3.SCFTDR) -#define SCFSR_3 (SCIF3.SCFSR) -#define SCFRDR_3 (SCIF3.SCFRDR) -#define SCFCR_3 (SCIF3.SCFCR) -#define SCFDR_3 (SCIF3.SCFDR) -#define SCSPTR_3 (SCIF3.SCSPTR) -#define SCLSR_3 (SCIF3.SCLSR) -#define SCEMR_3 (SCIF3.SCEMR) -#define SCSMR_4 (SCIF4.SCSMR) -#define SCBRR_4 (SCIF4.SCBRR) -#define SCSCR_4 (SCIF4.SCSCR) -#define SCFTDR_4 (SCIF4.SCFTDR) -#define SCFSR_4 (SCIF4.SCFSR) -#define SCFRDR_4 (SCIF4.SCFRDR) -#define SCFCR_4 (SCIF4.SCFCR) -#define SCFDR_4 (SCIF4.SCFDR) -#define SCSPTR_4 (SCIF4.SCSPTR) -#define SCLSR_4 (SCIF4.SCLSR) -#define SCEMR_4 (SCIF4.SCEMR) -#define SCSMR_5 (SCIF5.SCSMR) -#define SCBRR_5 (SCIF5.SCBRR) -#define SCSCR_5 (SCIF5.SCSCR) -#define SCFTDR_5 (SCIF5.SCFTDR) -#define SCFSR_5 (SCIF5.SCFSR) -#define SCFRDR_5 (SCIF5.SCFRDR) -#define SCFCR_5 (SCIF5.SCFCR) -#define SCFDR_5 (SCIF5.SCFDR) -#define SCSPTR_5 (SCIF5.SCSPTR) -#define SCLSR_5 (SCIF5.SCLSR) -#define SCEMR_5 (SCIF5.SCEMR) -#define SCSMR_6 (SCIF6.SCSMR) -#define SCBRR_6 (SCIF6.SCBRR) -#define SCSCR_6 (SCIF6.SCSCR) -#define SCFTDR_6 (SCIF6.SCFTDR) -#define SCFSR_6 (SCIF6.SCFSR) -#define SCFRDR_6 (SCIF6.SCFRDR) -#define SCFCR_6 (SCIF6.SCFCR) -#define SCFDR_6 (SCIF6.SCFDR) -#define SCSPTR_6 (SCIF6.SCSPTR) -#define SCLSR_6 (SCIF6.SCLSR) -#define SCEMR_6 (SCIF6.SCEMR) -#define SCSMR_7 (SCIF7.SCSMR) -#define SCBRR_7 (SCIF7.SCBRR) -#define SCSCR_7 (SCIF7.SCSCR) -#define SCFTDR_7 (SCIF7.SCFTDR) -#define SCFSR_7 (SCIF7.SCFSR) -#define SCFRDR_7 (SCIF7.SCFRDR) -#define SCFCR_7 (SCIF7.SCFCR) -#define SCFDR_7 (SCIF7.SCFDR) -#define SCSPTR_7 (SCIF7.SCSPTR) -#define SCLSR_7 (SCIF7.SCLSR) -#define SCEMR_7 (SCIF7.SCEMR) - - -typedef struct st_scif -{ - /* SCIF */ - volatile uint16_t SCSMR; /* SCSMR */ - volatile uint8_t dummy1[2]; /* */ - volatile uint8_t SCBRR; /* SCBRR */ - volatile uint8_t dummy2[3]; /* */ - volatile uint16_t SCSCR; /* SCSCR */ - volatile uint8_t dummy3[2]; /* */ - volatile uint8_t SCFTDR; /* SCFTDR */ - volatile uint8_t dummy4[3]; /* */ - volatile uint16_t SCFSR; /* SCFSR */ - volatile uint8_t dummy5[2]; /* */ - volatile uint8_t SCFRDR; /* SCFRDR */ - volatile uint8_t dummy6[3]; /* */ - volatile uint16_t SCFCR; /* SCFCR */ - volatile uint8_t dummy7[2]; /* */ - volatile uint16_t SCFDR; /* SCFDR */ - volatile uint8_t dummy8[2]; /* */ - volatile uint16_t SCSPTR; /* SCSPTR */ - volatile uint8_t dummy9[2]; /* */ - volatile uint16_t SCLSR; /* SCLSR */ - volatile uint8_t dummy10[2]; /* */ - volatile uint16_t SCEMR; /* SCEMR */ -} r_io_scif_t; - - -/* Channel array defines of SCIF (2)*/ -#ifdef DECLARE_SCIF_CHANNELS -volatile struct st_scif* SCIF[ SCIF_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SCIF_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SCIF_CHANNELS */ -/* End of channel array defines of SCIF (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h deleted file mode 100644 index fad306aca18..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : scim_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef SCIM_IODEFINE_H -#define SCIM_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ -#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ - - -/* Start of channel array defines of SCIM */ - -/* Channel array defines of SCIM */ -/*(Sample) value = SCIM[ channel ]->SMR; */ -#define SCIM_COUNT (2) -#define SCIM_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCIM0, &SCIM1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of SCIM */ - - -#define SMR0 (SCIM0.SMR) -#define BRR0 (SCIM0.BRR) -#define SCR0 (SCIM0.SCR) -#define TDR0 (SCIM0.TDR) -#define SSR0 (SCIM0.SSR) -#define RDR0 (SCIM0.RDR) -#define SCMR0 (SCIM0.SCMR) -#define SEMR0 (SCIM0.SEMR) -#define SNFR0 (SCIM0.SNFR) -#define SECR0 (SCIM0.SECR) -#define SMR1 (SCIM1.SMR) -#define BRR1 (SCIM1.BRR) -#define SCR1 (SCIM1.SCR) -#define TDR1 (SCIM1.TDR) -#define SSR1 (SCIM1.SSR) -#define RDR1 (SCIM1.RDR) -#define SCMR1 (SCIM1.SCMR) -#define SEMR1 (SCIM1.SEMR) -#define SNFR1 (SCIM1.SNFR) -#define SECR1 (SCIM1.SECR) - - -typedef struct st_scim -{ - /* SCIM */ - volatile uint8_t SMR; /* SMR */ - volatile uint8_t BRR; /* BRR */ - volatile uint8_t SCR; /* SCR */ - volatile uint8_t TDR; /* TDR */ - volatile uint8_t SSR; /* SSR */ - volatile uint8_t RDR; /* RDR */ - volatile uint8_t SCMR; /* SCMR */ - volatile uint8_t SEMR; /* SEMR */ - volatile uint8_t SNFR; /* SNFR */ - volatile uint8_t dummy1[4]; /* */ - volatile uint8_t SECR; /* SECR */ -} r_io_scim_t; - - -/* Channel array defines of SCIM (2)*/ -#ifdef DECLARE_SCIM_CHANNELS -volatile struct st_scim* SCIM[ SCIM_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SCIM_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SCIM_CHANNELS */ -/* End of channel array defines of SCIM (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h deleted file mode 100644 index 4293ec42774..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h +++ /dev/null @@ -1,921 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : scux_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef SCUX_IODEFINE_H -#define SCUX_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ - - -/* Start of channel array defines of SCUX */ - -/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ -#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT (4) -#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ -#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ -#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ -#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ - - -/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ -#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT (2) -#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ -#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ - - -/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ -#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT (4) -#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ -#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ -#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ -#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ - - -/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ -#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT (4) -#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ -#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ -#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ -#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ - - -/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ -#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT (4) -#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ -#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ -#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ -#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ - - -/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ -#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT (4) -#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ -#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ -#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ -#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ - -/* End of channel array defines of SCUX */ - - -#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0) -#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0) -#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1) -#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1) -#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2) -#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2) -#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3) -#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3) -#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0) -#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0) -#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1) -#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1) -#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2) -#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2) -#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3) -#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3) -#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0) -#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0) -#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0) -#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0) -#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0) -#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0) -#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0) -#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1) -#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1) -#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1) -#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1) -#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1) -#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1) -#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1) -#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2) -#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2) -#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2) -#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2) -#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2) -#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2) -#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2) -#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3) -#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3) -#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3) -#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3) -#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3) -#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3) -#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3) -#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0) -#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0) -#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0) -#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0) -#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0) -#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0) -#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1) -#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1) -#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1) -#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1) -#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1) -#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1) -#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2) -#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2) -#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2) -#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2) -#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2) -#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2) -#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3) -#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3) -#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3) -#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3) -#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3) -#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3) -#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0) -#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0) -#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0) -#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0) -#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0) -#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0) -#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0) -#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0) -#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0) -#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0) -#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0) -#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0) -#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0) -#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0) -#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0) -#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0) -#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0) -#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0) -#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0) -#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0) -#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0) -#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0) -#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0) -#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0) -#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0) -#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1) -#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1) -#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1) -#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1) -#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1) -#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1) -#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1) -#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1) -#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1) -#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1) -#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1) -#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1) -#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1) -#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1) -#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1) -#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1) -#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1) -#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1) -#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1) -#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1) -#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1) -#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1) -#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1) -#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1) -#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1) -#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0) -#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0) -#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0) -#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0) -#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0) -#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0) -#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0) -#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0) -#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0) -#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0) -#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0) -#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0) -#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0) -#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0) -#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0) -#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0) -#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0) -#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0) -#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0) -#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0) -#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0) -#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1) -#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1) -#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1) -#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1) -#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1) -#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1) -#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1) -#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1) -#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1) -#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1) -#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1) -#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1) -#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1) -#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1) -#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1) -#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1) -#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1) -#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1) -#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1) -#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1) -#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1) -#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2) -#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2) -#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2) -#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2) -#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2) -#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2) -#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2) -#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2) -#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2) -#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2) -#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2) -#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2) -#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2) -#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2) -#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2) -#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2) -#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2) -#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2) -#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2) -#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2) -#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2) -#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3) -#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3) -#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3) -#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3) -#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3) -#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3) -#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3) -#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3) -#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3) -#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3) -#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3) -#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3) -#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3) -#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3) -#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3) -#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3) -#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3) -#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3) -#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3) -#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3) -#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3) -#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0) -#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0) -#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0) -#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0) -#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0) -#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0) -#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0) -#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0) -#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0) -#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0) -#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0) -#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM) -#define SCUXDMACR_CIM (SCUX.DMACR_CIM) -#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32) -#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L]) -#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H]) -#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32) -#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L]) -#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H]) -#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32) -#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L]) -#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H]) -#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32) -#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L]) -#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H]) -#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32) -#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L]) -#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H]) -#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32) -#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L]) -#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H]) -#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32) -#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L]) -#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H]) -#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32) -#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L]) -#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H]) -#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM) -#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM) -#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM) -#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM) -#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM) -#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM) -#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM) -#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM) -#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM) -#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM) -#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM) -#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM) -#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM) -#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM) -#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM) -#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM) - -#define SCUX_DMATDnCIM_COUNT (4) -#define SCUX_DMATUnCIM_COUNT (4) -#define SCUX_FDTSELnCIM_COUNT (4) -#define SCUX_FUTSELnCIM_COUNT (4) -#define SCUX_SRCRSELnCIM_COUNT (4) - - -typedef struct st_scux -{ - /* SCUX */ - -/* start of struct st_scux_from_ipcir_ipc0_n */ - volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ - volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ - volatile uint8_t dummy259[248]; /* */ - -/* end of struct st_scux_from_ipcir_ipc0_n */ - -/* start of struct st_scux_from_ipcir_ipc0_n */ - volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ - volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ - volatile uint8_t dummy260[248]; /* */ - -/* end of struct st_scux_from_ipcir_ipc0_n */ - -/* start of struct st_scux_from_ipcir_ipc0_n */ - volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ - volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ - volatile uint8_t dummy261[248]; /* */ - -/* end of struct st_scux_from_ipcir_ipc0_n */ - -/* start of struct st_scux_from_ipcir_ipc0_n */ - volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ - volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ - volatile uint8_t dummy262[248]; /* */ - -/* end of struct st_scux_from_ipcir_ipc0_n */ - -/* start of struct st_scux_from_opcir_opc0_n */ - volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ - volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ - volatile uint8_t dummy263[248]; /* */ - -/* end of struct st_scux_from_opcir_opc0_n */ - -/* start of struct st_scux_from_opcir_opc0_n */ - volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ - volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ - volatile uint8_t dummy264[248]; /* */ - -/* end of struct st_scux_from_opcir_opc0_n */ - -/* start of struct st_scux_from_opcir_opc0_n */ - volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ - volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ - volatile uint8_t dummy265[248]; /* */ - -/* end of struct st_scux_from_opcir_opc0_n */ - -/* start of struct st_scux_from_opcir_opc0_n */ - volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ - volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ - volatile uint8_t dummy266[248]; /* */ - -/* end of struct st_scux_from_opcir_opc0_n */ - -/* start of struct st_scux_from_ffdir_ffd0_n */ - volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ - volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ - volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ - volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ - volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ - volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ - volatile uint8_t dummy267[4]; /* */ - volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ - -/* end of struct st_scux_from_ffdir_ffd0_n */ - volatile uint8_t dummy268[224]; /* */ - -/* start of struct st_scux_from_ffdir_ffd0_n */ - volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ - volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ - volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */ - volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */ - volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */ - volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ - volatile uint8_t dummy269[4]; /* */ - volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ - -/* end of struct st_scux_from_ffdir_ffd0_n */ - volatile uint8_t dummy270[224]; /* */ - -/* start of struct st_scux_from_ffdir_ffd0_n */ - volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ - volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ - volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */ - volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */ - volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */ - volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ - volatile uint8_t dummy271[4]; /* */ - volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ - -/* end of struct st_scux_from_ffdir_ffd0_n */ - volatile uint8_t dummy272[224]; /* */ - -/* start of struct st_scux_from_ffdir_ffd0_n */ - volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ - volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ - volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */ - volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */ - volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */ - volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ - volatile uint8_t dummy273[4]; /* */ - volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ - -/* end of struct st_scux_from_ffdir_ffd0_n */ - volatile uint8_t dummy274[224]; /* */ - -/* start of struct st_scux_from_ffuir_ffu0_n */ - volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ - volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ - volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ - volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ - volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ - volatile uint8_t dummy275[4]; /* */ - volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ - -/* end of struct st_scux_from_ffuir_ffu0_n */ - volatile uint8_t dummy276[228]; /* */ - -/* start of struct st_scux_from_ffuir_ffu0_n */ - volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ - volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ - volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */ - volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */ - volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ - volatile uint8_t dummy277[4]; /* */ - volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ - -/* end of struct st_scux_from_ffuir_ffu0_n */ - volatile uint8_t dummy278[228]; /* */ - -/* start of struct st_scux_from_ffuir_ffu0_n */ - volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ - volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ - volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */ - volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */ - volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ - volatile uint8_t dummy279[4]; /* */ - volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ - -/* end of struct st_scux_from_ffuir_ffu0_n */ - volatile uint8_t dummy280[228]; /* */ - -/* start of struct st_scux_from_ffuir_ffu0_n */ - volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ - volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ - volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */ - volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */ - volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ - volatile uint8_t dummy281[4]; /* */ - volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ - -/* end of struct st_scux_from_ffuir_ffu0_n */ - volatile uint8_t dummy282[228]; /* */ - -/* start of struct st_scux_from_srcir0_2src0_n */ - volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ - volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ - volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ - volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ - volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ - volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ - volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ - volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ - volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ - volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ - volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ - volatile uint8_t dummy283[4]; /* */ - volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ - volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ - volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ - volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ - volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ - volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ - volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ - volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ - volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ - volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ - volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ - volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ - volatile uint8_t dummy284[4]; /* */ - volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ - volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ - -/* end of struct st_scux_from_srcir0_2src0_n */ - volatile uint8_t dummy285[148]; /* */ - -/* start of struct st_scux_from_srcir0_2src0_n */ - volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ - volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ - volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */ - volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */ - volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */ - volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */ - volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */ - volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */ - volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */ - volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */ - volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */ - volatile uint8_t dummy286[4]; /* */ - volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */ - volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */ - volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */ - volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */ - volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */ - volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */ - volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */ - volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */ - volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */ - volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */ - volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */ - volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */ - volatile uint8_t dummy287[4]; /* */ - volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ - volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ - -/* end of struct st_scux_from_srcir0_2src0_n */ - volatile uint8_t dummy288[148]; /* */ - -/* start of struct st_scux_from_dvuir_dvu0_n */ - volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ - volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ - volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ - volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ - volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ - volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ - volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ - volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ - volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ - volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ - volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ - volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ - volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ - volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ - volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ - volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ - volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ - volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ - volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ - volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ - volatile uint8_t dummy289[4]; /* */ - volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ - -/* end of struct st_scux_from_dvuir_dvu0_n */ - volatile uint8_t dummy290[168]; /* */ - -/* start of struct st_scux_from_dvuir_dvu0_n */ - volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ - volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ - volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */ - volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */ - volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */ - volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */ - volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */ - volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */ - volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */ - volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */ - volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */ - volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */ - volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */ - volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */ - volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */ - volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */ - volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */ - volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */ - volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */ - volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ - volatile uint8_t dummy291[4]; /* */ - volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ - -/* end of struct st_scux_from_dvuir_dvu0_n */ - volatile uint8_t dummy292[168]; /* */ - -/* start of struct st_scux_from_dvuir_dvu0_n */ - volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ - volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ - volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */ - volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */ - volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */ - volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */ - volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */ - volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */ - volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */ - volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */ - volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */ - volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */ - volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */ - volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */ - volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */ - volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */ - volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */ - volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */ - volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */ - volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ - volatile uint8_t dummy293[4]; /* */ - volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ - -/* end of struct st_scux_from_dvuir_dvu0_n */ - volatile uint8_t dummy294[168]; /* */ - -/* start of struct st_scux_from_dvuir_dvu0_n */ - volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ - volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ - volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */ - volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */ - volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */ - volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */ - volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */ - volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */ - volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */ - volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */ - volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */ - volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */ - volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */ - volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */ - volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */ - volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */ - volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */ - volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */ - volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */ - volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ - volatile uint8_t dummy295[4]; /* */ - volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ - -/* end of struct st_scux_from_dvuir_dvu0_n */ - volatile uint8_t dummy296[168]; /* */ - volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ - volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */ - volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */ - volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */ - volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */ - volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */ - volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */ - volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */ - volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */ - volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */ - volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */ - volatile uint8_t dummy297[212]; /* */ - volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ - volatile uint32_t DMACR_CIM; /* DMACR_CIM */ - -/* #define SCUX_DMATDnCIM_COUNT (4) */ - union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ - union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ - union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ - union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ - -/* #define SCUX_DMATUnCIM_COUNT (4) */ - union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ - union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ - union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ - union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */ - - volatile uint8_t dummy298[16]; /* */ - volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ - -/* #define SCUX_FDTSELnCIM_COUNT (4) */ - volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ - volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ - volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ - volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ - -/* #define SCUX_FUTSELnCIM_COUNT (4) */ - volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ - volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ - volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ - volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ - volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ - volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ - -/* #define SCUX_SRCRSELnCIM_COUNT (4) */ - volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ - volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ - volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ - volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ - volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ -} r_io_scux_t; - - -typedef struct st_scux_from_ipcir_ipc0_n -{ - - volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ - volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ - volatile uint8_t dummy1[248]; /* */ -} r_io_scux_from_ipcir_ipc0_n_t; - - -typedef struct st_scux_from_opcir_opc0_n -{ - - volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ - volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ - volatile uint8_t dummy1[248]; /* */ -} r_io_scux_from_opcir_opc0_n_t; - - -typedef struct st_scux_from_ffdir_ffd0_n -{ - - volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ - volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ - volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ - volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ - volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ - volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ - volatile uint8_t dummy1[4]; /* */ - volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ -} r_io_scux_from_ffdir_ffd0_n_t; - - -typedef struct st_scux_from_ffuir_ffu0_n -{ - - volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ - volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ - volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ - volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ - volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ - volatile uint8_t dummy1[4]; /* */ - volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ -} r_io_scux_from_ffuir_ffu0_n_t; - - -typedef struct st_scux_from_srcir0_2src0_n -{ - - volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ - volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ - volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ - volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ - volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ - volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ - volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ - volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ - volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ - volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ - volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ - volatile uint8_t dummy1[4]; /* */ - volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ - volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ - volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ - volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ - volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ - volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ - volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ - volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ - volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ - volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ - volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ - volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ - volatile uint8_t dummy2[4]; /* */ - volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ - volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ -} r_io_scux_from_srcir0_2src0_n_t; - - -typedef struct st_scux_from_dvuir_dvu0_n -{ - - volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ - volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ - volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ - volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ - volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ - volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ - volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ - volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ - volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ - volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ - volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ - volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ - volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ - volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ - volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ - volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ - volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ - volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ - volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ - volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ - volatile uint8_t dummy1[4]; /* */ - volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ -} r_io_scux_from_dvuir_dvu0_n_t; - - -/* Channel array defines of SCUX (2)*/ -#ifdef DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS -volatile struct st_scux_from_dvuir_dvu0_n* SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */ - -#ifdef DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS -volatile struct st_scux_from_srcir0_2src0_n* SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */ - -#ifdef DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS -volatile struct st_scux_from_ffuir_ffu0_n* SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */ - -#ifdef DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS -volatile struct st_scux_from_ffdir_ffd0_n* SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */ - -#ifdef DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS -volatile struct st_scux_from_opcir_opc0_n* SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */ - -#ifdef DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS -volatile struct st_scux_from_ipcir_ipc0_n* SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */ -/* End of channel array defines of SCUX (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h deleted file mode 100644 index dd6dee41d84..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h +++ /dev/null @@ -1,107 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : sdg_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef SDG_IODEFINE_H -#define SDG_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */ -#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */ -#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */ -#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */ - - -/* Start of channel array defines of SDG */ - -/* Channel array defines of SDG */ -/*(Sample) value = SDG[ channel ]->SGCR1; */ -#define SDG_COUNT (4) -#define SDG_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SDG0, &SDG1, &SDG2, &SDG3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of SDG */ - - -#define SGCR1_0 (SDG0.SGCR1) -#define SGCSR_0 (SDG0.SGCSR) -#define SGCR2_0 (SDG0.SGCR2) -#define SGLR_0 (SDG0.SGLR) -#define SGTFR_0 (SDG0.SGTFR) -#define SGSFR_0 (SDG0.SGSFR) -#define SGCR1_1 (SDG1.SGCR1) -#define SGCSR_1 (SDG1.SGCSR) -#define SGCR2_1 (SDG1.SGCR2) -#define SGLR_1 (SDG1.SGLR) -#define SGTFR_1 (SDG1.SGTFR) -#define SGSFR_1 (SDG1.SGSFR) -#define SGCR1_2 (SDG2.SGCR1) -#define SGCSR_2 (SDG2.SGCSR) -#define SGCR2_2 (SDG2.SGCR2) -#define SGLR_2 (SDG2.SGLR) -#define SGTFR_2 (SDG2.SGTFR) -#define SGSFR_2 (SDG2.SGSFR) -#define SGCR1_3 (SDG3.SGCR1) -#define SGCSR_3 (SDG3.SGCSR) -#define SGCR2_3 (SDG3.SGCR2) -#define SGLR_3 (SDG3.SGLR) -#define SGTFR_3 (SDG3.SGTFR) -#define SGSFR_3 (SDG3.SGSFR) - - -typedef struct st_sdg -{ - /* SDG */ - volatile uint8_t SGCR1; /* SGCR1 */ - volatile uint8_t SGCSR; /* SGCSR */ - volatile uint8_t SGCR2; /* SGCR2 */ - volatile uint8_t SGLR; /* SGLR */ - volatile uint8_t SGTFR; /* SGTFR */ - volatile uint8_t SGSFR; /* SGSFR */ -} r_io_sdg_t; - - -/* Channel array defines of SDG (2)*/ -#ifdef DECLARE_SDG_CHANNELS -volatile struct st_sdg* SDG[ SDG_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SDG_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SDG_CHANNELS */ -/* End of channel array defines of SDG (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h deleted file mode 100644 index a7e4c825290..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h +++ /dev/null @@ -1,79 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : spdif_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef SPDIF_IODEFINE_H -#define SPDIF_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ - - -#define SPDIFTLCA (SPDIF.TLCA) -#define SPDIFTRCA (SPDIF.TRCA) -#define SPDIFTLCS (SPDIF.TLCS) -#define SPDIFTRCS (SPDIF.TRCS) -#define SPDIFTUI (SPDIF.TUI) -#define SPDIFRLCA (SPDIF.RLCA) -#define SPDIFRRCA (SPDIF.RRCA) -#define SPDIFRLCS (SPDIF.RLCS) -#define SPDIFRRCS (SPDIF.RRCS) -#define SPDIFRUI (SPDIF.RUI) -#define SPDIFCTRL (SPDIF.CTRL) -#define SPDIFSTAT (SPDIF.STAT) -#define SPDIFTDAD (SPDIF.TDAD) -#define SPDIFRDAD (SPDIF.RDAD) - - -typedef struct st_spdif -{ - /* SPDIF */ - volatile uint32_t TLCA; /* TLCA */ - volatile uint32_t TRCA; /* TRCA */ - volatile uint32_t TLCS; /* TLCS */ - volatile uint32_t TRCS; /* TRCS */ - volatile uint32_t TUI; /* TUI */ - volatile uint32_t RLCA; /* RLCA */ - volatile uint32_t RRCA; /* RRCA */ - volatile uint32_t RLCS; /* RLCS */ - volatile uint32_t RRCS; /* RRCS */ - volatile uint32_t RUI; /* RUI */ - volatile uint32_t CTRL; /* CTRL */ - volatile uint32_t STAT; /* STAT */ - volatile uint32_t TDAD; /* TDAD */ - volatile uint32_t RDAD; /* RDAD */ -} r_io_spdif_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h deleted file mode 100644 index 6615aea8f7e..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h +++ /dev/null @@ -1,199 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : spibsc_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef SPIBSC_IODEFINE_H -#define SPIBSC_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ -#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ - - -/* Start of channel array defines of SPIBSC */ - -/* Channel array defines of SPIBSC */ -/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ -#define SPIBSC_COUNT (2) -#define SPIBSC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SPIBSC0, &SPIBSC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of SPIBSC */ - - -#define CMNCR_0 (SPIBSC0.CMNCR) -#define SSLDR_0 (SPIBSC0.SSLDR) -#define SPBCR_0 (SPIBSC0.SPBCR) -#define DRCR_0 (SPIBSC0.DRCR) -#define DRCMR_0 (SPIBSC0.DRCMR) -#define DREAR_0 (SPIBSC0.DREAR) -#define DROPR_0 (SPIBSC0.DROPR) -#define DRENR_0 (SPIBSC0.DRENR) -#define SMCR_0 (SPIBSC0.SMCR) -#define SMCMR_0 (SPIBSC0.SMCMR) -#define SMADR_0 (SPIBSC0.SMADR) -#define SMOPR_0 (SPIBSC0.SMOPR) -#define SMENR_0 (SPIBSC0.SMENR) -#define SMRDR0_0 (SPIBSC0.SMRDR0.UINT32) -#define SMRDR0_0L (SPIBSC0.SMRDR0.UINT16[R_IO_L]) -#define SMRDR0_0H (SPIBSC0.SMRDR0.UINT16[R_IO_H]) -#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL]) -#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH]) -#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL]) -#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH]) -#define SMRDR1_0 (SPIBSC0.SMRDR1.UINT32) -#define SMRDR1_0L (SPIBSC0.SMRDR1.UINT16[R_IO_L]) -#define SMRDR1_0H (SPIBSC0.SMRDR1.UINT16[R_IO_H]) -#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL]) -#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH]) -#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL]) -#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH]) -#define SMWDR0_0 (SPIBSC0.SMWDR0.UINT32) -#define SMWDR0_0L (SPIBSC0.SMWDR0.UINT16[R_IO_L]) -#define SMWDR0_0H (SPIBSC0.SMWDR0.UINT16[R_IO_H]) -#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL]) -#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH]) -#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL]) -#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH]) -#define SMWDR1_0 (SPIBSC0.SMWDR1.UINT32) -#define SMWDR1_0L (SPIBSC0.SMWDR1.UINT16[R_IO_L]) -#define SMWDR1_0H (SPIBSC0.SMWDR1.UINT16[R_IO_H]) -#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL]) -#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH]) -#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL]) -#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH]) -#define CMNSR_0 (SPIBSC0.CMNSR) -#define CKDLY_0 (SPIBSC0.CKDLY) -#define DRDMCR_0 (SPIBSC0.DRDMCR) -#define DRDRENR_0 (SPIBSC0.DRDRENR) -#define SMDMCR_0 (SPIBSC0.SMDMCR) -#define SMDRENR_0 (SPIBSC0.SMDRENR) -#define SPODLY_0 (SPIBSC0.SPODLY) -#define CMNCR_1 (SPIBSC1.CMNCR) -#define SSLDR_1 (SPIBSC1.SSLDR) -#define SPBCR_1 (SPIBSC1.SPBCR) -#define DRCR_1 (SPIBSC1.DRCR) -#define DRCMR_1 (SPIBSC1.DRCMR) -#define DREAR_1 (SPIBSC1.DREAR) -#define DROPR_1 (SPIBSC1.DROPR) -#define DRENR_1 (SPIBSC1.DRENR) -#define SMCR_1 (SPIBSC1.SMCR) -#define SMCMR_1 (SPIBSC1.SMCMR) -#define SMADR_1 (SPIBSC1.SMADR) -#define SMOPR_1 (SPIBSC1.SMOPR) -#define SMENR_1 (SPIBSC1.SMENR) -#define SMRDR0_1 (SPIBSC1.SMRDR0.UINT32) -#define SMRDR0_1L (SPIBSC1.SMRDR0.UINT16[R_IO_L]) -#define SMRDR0_1H (SPIBSC1.SMRDR0.UINT16[R_IO_H]) -#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL]) -#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH]) -#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL]) -#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH]) -#define SMRDR1_1 (SPIBSC1.SMRDR1.UINT32) -#define SMRDR1_1L (SPIBSC1.SMRDR1.UINT16[R_IO_L]) -#define SMRDR1_1H (SPIBSC1.SMRDR1.UINT16[R_IO_H]) -#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL]) -#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH]) -#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL]) -#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH]) -#define SMWDR0_1 (SPIBSC1.SMWDR0.UINT32) -#define SMWDR0_1L (SPIBSC1.SMWDR0.UINT16[R_IO_L]) -#define SMWDR0_1H (SPIBSC1.SMWDR0.UINT16[R_IO_H]) -#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL]) -#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH]) -#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL]) -#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH]) -#define SMWDR1_1 (SPIBSC1.SMWDR1.UINT32) -#define SMWDR1_1L (SPIBSC1.SMWDR1.UINT16[R_IO_L]) -#define SMWDR1_1H (SPIBSC1.SMWDR1.UINT16[R_IO_H]) -#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL]) -#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH]) -#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL]) -#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH]) -#define CMNSR_1 (SPIBSC1.CMNSR) -#define CKDLY_1 (SPIBSC1.CKDLY) -#define DRDMCR_1 (SPIBSC1.DRDMCR) -#define DRDRENR_1 (SPIBSC1.DRDRENR) -#define SMDMCR_1 (SPIBSC1.SMDMCR) -#define SMDRENR_1 (SPIBSC1.SMDRENR) -#define SPODLY_1 (SPIBSC1.SPODLY) - - -typedef struct st_spibsc -{ - /* SPIBSC */ - volatile uint32_t CMNCR; /* CMNCR */ - volatile uint32_t SSLDR; /* SSLDR */ - volatile uint32_t SPBCR; /* SPBCR */ - volatile uint32_t DRCR; /* DRCR */ - volatile uint32_t DRCMR; /* DRCMR */ - volatile uint32_t DREAR; /* DREAR */ - volatile uint32_t DROPR; /* DROPR */ - volatile uint32_t DRENR; /* DRENR */ - volatile uint32_t SMCR; /* SMCR */ - volatile uint32_t SMCMR; /* SMCMR */ - volatile uint32_t SMADR; /* SMADR */ - volatile uint32_t SMOPR; /* SMOPR */ - volatile uint32_t SMENR; /* SMENR */ - volatile uint8_t dummy1[4]; /* */ - union iodefine_reg32_t SMRDR0; /* SMRDR0 */ - union iodefine_reg32_t SMRDR1; /* SMRDR1 */ - union iodefine_reg32_t SMWDR0; /* SMWDR0 */ - union iodefine_reg32_t SMWDR1; /* SMWDR1 */ - - volatile uint32_t CMNSR; /* CMNSR */ - volatile uint8_t dummy2[4]; /* */ - volatile uint32_t CKDLY; /* CKDLY */ - volatile uint8_t dummy3[4]; /* */ - volatile uint32_t DRDMCR; /* DRDMCR */ - volatile uint32_t DRDRENR; /* DRDRENR */ - volatile uint32_t SMDMCR; /* SMDMCR */ - volatile uint32_t SMDRENR; /* SMDRENR */ - volatile uint32_t SPODLY; /* SPODLY */ -} r_io_spibsc_t; - - -/* Channel array defines of SPIBSC (2)*/ -#ifdef DECLARE_SPIBSC_CHANNELS -volatile struct st_spibsc* SPIBSC[ SPIBSC_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SPIBSC_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SPIBSC_CHANNELS */ -/* End of channel array defines of SPIBSC (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h deleted file mode 100644 index c0134a5d629..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h +++ /dev/null @@ -1,150 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : ssif_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef SSIF_IODEFINE_H -#define SSIF_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ -#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ -#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ -#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ -#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */ -#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ - - -/* Start of channel array defines of SSIF */ - -/* Channel array defines of SSIF */ -/*(Sample) value = SSIF[ channel ]->SSICR; */ -#define SSIF_COUNT (6) -#define SSIF_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channel array defines of SSIF */ - - -#define SSICR_0 (SSIF0.SSICR) -#define SSISR_0 (SSIF0.SSISR) -#define SSIFCR_0 (SSIF0.SSIFCR) -#define SSIFSR_0 (SSIF0.SSIFSR) -#define SSIFTDR_0 (SSIF0.SSIFTDR) -#define SSIFRDR_0 (SSIF0.SSIFRDR) -#define SSITDMR_0 (SSIF0.SSITDMR) -#define SSIFCCR_0 (SSIF0.SSIFCCR) -#define SSIFCMR_0 (SSIF0.SSIFCMR) -#define SSIFCSR_0 (SSIF0.SSIFCSR) -#define SSICR_1 (SSIF1.SSICR) -#define SSISR_1 (SSIF1.SSISR) -#define SSIFCR_1 (SSIF1.SSIFCR) -#define SSIFSR_1 (SSIF1.SSIFSR) -#define SSIFTDR_1 (SSIF1.SSIFTDR) -#define SSIFRDR_1 (SSIF1.SSIFRDR) -#define SSITDMR_1 (SSIF1.SSITDMR) -#define SSIFCCR_1 (SSIF1.SSIFCCR) -#define SSIFCMR_1 (SSIF1.SSIFCMR) -#define SSIFCSR_1 (SSIF1.SSIFCSR) -#define SSICR_2 (SSIF2.SSICR) -#define SSISR_2 (SSIF2.SSISR) -#define SSIFCR_2 (SSIF2.SSIFCR) -#define SSIFSR_2 (SSIF2.SSIFSR) -#define SSIFTDR_2 (SSIF2.SSIFTDR) -#define SSIFRDR_2 (SSIF2.SSIFRDR) -#define SSITDMR_2 (SSIF2.SSITDMR) -#define SSIFCCR_2 (SSIF2.SSIFCCR) -#define SSIFCMR_2 (SSIF2.SSIFCMR) -#define SSIFCSR_2 (SSIF2.SSIFCSR) -#define SSICR_3 (SSIF3.SSICR) -#define SSISR_3 (SSIF3.SSISR) -#define SSIFCR_3 (SSIF3.SSIFCR) -#define SSIFSR_3 (SSIF3.SSIFSR) -#define SSIFTDR_3 (SSIF3.SSIFTDR) -#define SSIFRDR_3 (SSIF3.SSIFRDR) -#define SSITDMR_3 (SSIF3.SSITDMR) -#define SSIFCCR_3 (SSIF3.SSIFCCR) -#define SSIFCMR_3 (SSIF3.SSIFCMR) -#define SSIFCSR_3 (SSIF3.SSIFCSR) -#define SSICR_4 (SSIF4.SSICR) -#define SSISR_4 (SSIF4.SSISR) -#define SSIFCR_4 (SSIF4.SSIFCR) -#define SSIFSR_4 (SSIF4.SSIFSR) -#define SSIFTDR_4 (SSIF4.SSIFTDR) -#define SSIFRDR_4 (SSIF4.SSIFRDR) -#define SSITDMR_4 (SSIF4.SSITDMR) -#define SSIFCCR_4 (SSIF4.SSIFCCR) -#define SSIFCMR_4 (SSIF4.SSIFCMR) -#define SSIFCSR_4 (SSIF4.SSIFCSR) -#define SSICR_5 (SSIF5.SSICR) -#define SSISR_5 (SSIF5.SSISR) -#define SSIFCR_5 (SSIF5.SSIFCR) -#define SSIFSR_5 (SSIF5.SSIFSR) -#define SSIFTDR_5 (SSIF5.SSIFTDR) -#define SSIFRDR_5 (SSIF5.SSIFRDR) -#define SSITDMR_5 (SSIF5.SSITDMR) -#define SSIFCCR_5 (SSIF5.SSIFCCR) -#define SSIFCMR_5 (SSIF5.SSIFCMR) -#define SSIFCSR_5 (SSIF5.SSIFCSR) - - -typedef struct st_ssif -{ - /* SSIF */ - volatile uint32_t SSICR; /* SSICR */ - volatile uint32_t SSISR; /* SSISR */ - volatile uint8_t dummy1[8]; /* */ - volatile uint32_t SSIFCR; /* SSIFCR */ - volatile uint32_t SSIFSR; /* SSIFSR */ - volatile uint32_t SSIFTDR; /* SSIFTDR */ - volatile uint32_t SSIFRDR; /* SSIFRDR */ - volatile uint32_t SSITDMR; /* SSITDMR */ - volatile uint32_t SSIFCCR; /* SSIFCCR */ - volatile uint32_t SSIFCMR; /* SSIFCMR */ - volatile uint32_t SSIFCSR; /* SSIFCSR */ -} r_io_ssif_t; - - -/* Channel array defines of SSIF (2)*/ -#ifdef DECLARE_SSIF_CHANNELS -volatile struct st_ssif* SSIF[ SSIF_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - SSIF_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_SSIF_CHANNELS */ -/* End of channel array defines of SSIF (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h deleted file mode 100644 index a8e60a2647b..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h +++ /dev/null @@ -1,622 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : usb20_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef USB20_IODEFINE_H -#define USB20_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ -#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ - - -/* Start of channel array defines of USB20 */ - -/* Channel array defines of USB20 */ -/*(Sample) value = USB20[ channel ]->SYSCFG0; */ -#define USB20_COUNT (2) -#define USB20_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &USB200, &USB201 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - - - -/* Channel array defines of USB20_FROM_D0FIFOB0 */ -/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ -#define USB20_FROM_D0FIFOB0_COUNT (2) -#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ - &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ -#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ -#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ -#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ - - - - -/* Channel array defines of USB20_FROM_PIPE1ATRE */ -/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ -#define USB20_FROM_PIPE1ATRE_COUNT (5) -#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ - &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ -#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ -#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ -#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ -#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ -#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ -#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ -#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ -#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ -#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ - - - - -/* Channel array defines of USB20_FROM_D0FIFOSEL */ -/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ -#define USB20_FROM_D0FIFOSEL_COUNT (2) -#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ - &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ -#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ -#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ -#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ - - -/* End of channel array defines of USB20 */ - - -#define SYSCFG0_0 (USB200.SYSCFG0) -#define BUSWAIT_0 (USB200.BUSWAIT) -#define SYSSTS0_0 (USB200.SYSSTS0) -#define DVSTCTR0_0 (USB200.DVSTCTR0) -#define TESTMODE_0 (USB200.TESTMODE) -#define D0FBCFG_0 (USB200.D0FBCFG) -#define D1FBCFG_0 (USB200.D1FBCFG) -#define CFIFO_0 (USB200.CFIFO.UINT32) -#define CFIFO_0L (USB200.CFIFO.UINT16[R_IO_L]) -#define CFIFO_0H (USB200.CFIFO.UINT16[R_IO_H]) -#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL]) -#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH]) -#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL]) -#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH]) -#define D0FIFO_0 (USB200.D0FIFO.UINT32) -#define D0FIFO_0L (USB200.D0FIFO.UINT16[R_IO_L]) -#define D0FIFO_0H (USB200.D0FIFO.UINT16[R_IO_H]) -#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL]) -#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH]) -#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL]) -#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH]) -#define D1FIFO_0 (USB200.D1FIFO.UINT32) -#define D1FIFO_0L (USB200.D1FIFO.UINT16[R_IO_L]) -#define D1FIFO_0H (USB200.D1FIFO.UINT16[R_IO_H]) -#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL]) -#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH]) -#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL]) -#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH]) -#define CFIFOSEL_0 (USB200.CFIFOSEL) -#define CFIFOCTR_0 (USB200.CFIFOCTR) -#define D0FIFOSEL_0 (USB200.D0FIFOSEL) -#define D0FIFOCTR_0 (USB200.D0FIFOCTR) -#define D1FIFOSEL_0 (USB200.D1FIFOSEL) -#define D1FIFOCTR_0 (USB200.D1FIFOCTR) -#define INTENB0_0 (USB200.INTENB0) -#define INTENB1_0 (USB200.INTENB1) -#define BRDYENB_0 (USB200.BRDYENB) -#define NRDYENB_0 (USB200.NRDYENB) -#define BEMPENB_0 (USB200.BEMPENB) -#define SOFCFG_0 (USB200.SOFCFG) -#define INTSTS0_0 (USB200.INTSTS0) -#define INTSTS1_0 (USB200.INTSTS1) -#define BRDYSTS_0 (USB200.BRDYSTS) -#define NRDYSTS_0 (USB200.NRDYSTS) -#define BEMPSTS_0 (USB200.BEMPSTS) -#define FRMNUM_0 (USB200.FRMNUM) -#define UFRMNUM_0 (USB200.UFRMNUM) -#define USBADDR_0 (USB200.USBADDR) -#define USBREQ_0 (USB200.USBREQ) -#define USBVAL_0 (USB200.USBVAL) -#define USBINDX_0 (USB200.USBINDX) -#define USBLENG_0 (USB200.USBLENG) -#define DCPCFG_0 (USB200.DCPCFG) -#define DCPMAXP_0 (USB200.DCPMAXP) -#define DCPCTR_0 (USB200.DCPCTR) -#define PIPESEL_0 (USB200.PIPESEL) -#define PIPECFG_0 (USB200.PIPECFG) -#define PIPEBUF_0 (USB200.PIPEBUF) -#define PIPEMAXP_0 (USB200.PIPEMAXP) -#define PIPEPERI_0 (USB200.PIPEPERI) -#define PIPE1CTR_0 (USB200.PIPE1CTR) -#define PIPE2CTR_0 (USB200.PIPE2CTR) -#define PIPE3CTR_0 (USB200.PIPE3CTR) -#define PIPE4CTR_0 (USB200.PIPE4CTR) -#define PIPE5CTR_0 (USB200.PIPE5CTR) -#define PIPE6CTR_0 (USB200.PIPE6CTR) -#define PIPE7CTR_0 (USB200.PIPE7CTR) -#define PIPE8CTR_0 (USB200.PIPE8CTR) -#define PIPE9CTR_0 (USB200.PIPE9CTR) -#define PIPEACTR_0 (USB200.PIPEACTR) -#define PIPEBCTR_0 (USB200.PIPEBCTR) -#define PIPECCTR_0 (USB200.PIPECCTR) -#define PIPEDCTR_0 (USB200.PIPEDCTR) -#define PIPEECTR_0 (USB200.PIPEECTR) -#define PIPEFCTR_0 (USB200.PIPEFCTR) -#define PIPE1TRE_0 (USB200.PIPE1TRE) -#define PIPE1TRN_0 (USB200.PIPE1TRN) -#define PIPE2TRE_0 (USB200.PIPE2TRE) -#define PIPE2TRN_0 (USB200.PIPE2TRN) -#define PIPE3TRE_0 (USB200.PIPE3TRE) -#define PIPE3TRN_0 (USB200.PIPE3TRN) -#define PIPE4TRE_0 (USB200.PIPE4TRE) -#define PIPE4TRN_0 (USB200.PIPE4TRN) -#define PIPE5TRE_0 (USB200.PIPE5TRE) -#define PIPE5TRN_0 (USB200.PIPE5TRN) -#define PIPEBTRE_0 (USB200.PIPEBTRE) -#define PIPEBTRN_0 (USB200.PIPEBTRN) -#define PIPECTRE_0 (USB200.PIPECTRE) -#define PIPECTRN_0 (USB200.PIPECTRN) -#define PIPEDTRE_0 (USB200.PIPEDTRE) -#define PIPEDTRN_0 (USB200.PIPEDTRN) -#define PIPEETRE_0 (USB200.PIPEETRE) -#define PIPEETRN_0 (USB200.PIPEETRN) -#define PIPEFTRE_0 (USB200.PIPEFTRE) -#define PIPEFTRN_0 (USB200.PIPEFTRN) -#define PIPE9TRE_0 (USB200.PIPE9TRE) -#define PIPE9TRN_0 (USB200.PIPE9TRN) -#define PIPEATRE_0 (USB200.PIPEATRE) -#define PIPEATRN_0 (USB200.PIPEATRN) -#define DEVADD0_0 (USB200.DEVADD0) -#define DEVADD1_0 (USB200.DEVADD1) -#define DEVADD2_0 (USB200.DEVADD2) -#define DEVADD3_0 (USB200.DEVADD3) -#define DEVADD4_0 (USB200.DEVADD4) -#define DEVADD5_0 (USB200.DEVADD5) -#define DEVADD6_0 (USB200.DEVADD6) -#define DEVADD7_0 (USB200.DEVADD7) -#define DEVADD8_0 (USB200.DEVADD8) -#define DEVADD9_0 (USB200.DEVADD9) -#define DEVADDA_0 (USB200.DEVADDA) -#define SUSPMODE_0 (USB200.SUSPMODE) -#define D0FIFOB0_0 (USB200.D0FIFOB0) -#define D0FIFOB1_0 (USB200.D0FIFOB1) -#define D0FIFOB2_0 (USB200.D0FIFOB2) -#define D0FIFOB3_0 (USB200.D0FIFOB3) -#define D0FIFOB4_0 (USB200.D0FIFOB4) -#define D0FIFOB5_0 (USB200.D0FIFOB5) -#define D0FIFOB6_0 (USB200.D0FIFOB6) -#define D0FIFOB7_0 (USB200.D0FIFOB7) -#define D1FIFOB0_0 (USB200.D1FIFOB0) -#define D1FIFOB1_0 (USB200.D1FIFOB1) -#define D1FIFOB2_0 (USB200.D1FIFOB2) -#define D1FIFOB3_0 (USB200.D1FIFOB3) -#define D1FIFOB4_0 (USB200.D1FIFOB4) -#define D1FIFOB5_0 (USB200.D1FIFOB5) -#define D1FIFOB6_0 (USB200.D1FIFOB6) -#define D1FIFOB7_0 (USB200.D1FIFOB7) -#define SYSCFG0_1 (USB201.SYSCFG0) -#define BUSWAIT_1 (USB201.BUSWAIT) -#define SYSSTS0_1 (USB201.SYSSTS0) -#define DVSTCTR0_1 (USB201.DVSTCTR0) -#define TESTMODE_1 (USB201.TESTMODE) -#define D0FBCFG_1 (USB201.D0FBCFG) -#define D1FBCFG_1 (USB201.D1FBCFG) -#define CFIFO_1 (USB201.CFIFO.UINT32) -#define CFIFO_1L (USB201.CFIFO.UINT16[R_IO_L]) -#define CFIFO_1H (USB201.CFIFO.UINT16[R_IO_H]) -#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL]) -#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH]) -#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL]) -#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH]) -#define D0FIFO_1 (USB201.D0FIFO.UINT32) -#define D0FIFO_1L (USB201.D0FIFO.UINT16[R_IO_L]) -#define D0FIFO_1H (USB201.D0FIFO.UINT16[R_IO_H]) -#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL]) -#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH]) -#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL]) -#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH]) -#define D1FIFO_1 (USB201.D1FIFO.UINT32) -#define D1FIFO_1L (USB201.D1FIFO.UINT16[R_IO_L]) -#define D1FIFO_1H (USB201.D1FIFO.UINT16[R_IO_H]) -#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL]) -#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH]) -#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL]) -#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH]) -#define CFIFOSEL_1 (USB201.CFIFOSEL) -#define CFIFOCTR_1 (USB201.CFIFOCTR) -#define D0FIFOSEL_1 (USB201.D0FIFOSEL) -#define D0FIFOCTR_1 (USB201.D0FIFOCTR) -#define D1FIFOSEL_1 (USB201.D1FIFOSEL) -#define D1FIFOCTR_1 (USB201.D1FIFOCTR) -#define INTENB0_1 (USB201.INTENB0) -#define INTENB1_1 (USB201.INTENB1) -#define BRDYENB_1 (USB201.BRDYENB) -#define NRDYENB_1 (USB201.NRDYENB) -#define BEMPENB_1 (USB201.BEMPENB) -#define SOFCFG_1 (USB201.SOFCFG) -#define INTSTS0_1 (USB201.INTSTS0) -#define INTSTS1_1 (USB201.INTSTS1) -#define BRDYSTS_1 (USB201.BRDYSTS) -#define NRDYSTS_1 (USB201.NRDYSTS) -#define BEMPSTS_1 (USB201.BEMPSTS) -#define FRMNUM_1 (USB201.FRMNUM) -#define UFRMNUM_1 (USB201.UFRMNUM) -#define USBADDR_1 (USB201.USBADDR) -#define USBREQ_1 (USB201.USBREQ) -#define USBVAL_1 (USB201.USBVAL) -#define USBINDX_1 (USB201.USBINDX) -#define USBLENG_1 (USB201.USBLENG) -#define DCPCFG_1 (USB201.DCPCFG) -#define DCPMAXP_1 (USB201.DCPMAXP) -#define DCPCTR_1 (USB201.DCPCTR) -#define PIPESEL_1 (USB201.PIPESEL) -#define PIPECFG_1 (USB201.PIPECFG) -#define PIPEBUF_1 (USB201.PIPEBUF) -#define PIPEMAXP_1 (USB201.PIPEMAXP) -#define PIPEPERI_1 (USB201.PIPEPERI) -#define PIPE1CTR_1 (USB201.PIPE1CTR) -#define PIPE2CTR_1 (USB201.PIPE2CTR) -#define PIPE3CTR_1 (USB201.PIPE3CTR) -#define PIPE4CTR_1 (USB201.PIPE4CTR) -#define PIPE5CTR_1 (USB201.PIPE5CTR) -#define PIPE6CTR_1 (USB201.PIPE6CTR) -#define PIPE7CTR_1 (USB201.PIPE7CTR) -#define PIPE8CTR_1 (USB201.PIPE8CTR) -#define PIPE9CTR_1 (USB201.PIPE9CTR) -#define PIPEACTR_1 (USB201.PIPEACTR) -#define PIPEBCTR_1 (USB201.PIPEBCTR) -#define PIPECCTR_1 (USB201.PIPECCTR) -#define PIPEDCTR_1 (USB201.PIPEDCTR) -#define PIPEECTR_1 (USB201.PIPEECTR) -#define PIPEFCTR_1 (USB201.PIPEFCTR) -#define PIPE1TRE_1 (USB201.PIPE1TRE) -#define PIPE1TRN_1 (USB201.PIPE1TRN) -#define PIPE2TRE_1 (USB201.PIPE2TRE) -#define PIPE2TRN_1 (USB201.PIPE2TRN) -#define PIPE3TRE_1 (USB201.PIPE3TRE) -#define PIPE3TRN_1 (USB201.PIPE3TRN) -#define PIPE4TRE_1 (USB201.PIPE4TRE) -#define PIPE4TRN_1 (USB201.PIPE4TRN) -#define PIPE5TRE_1 (USB201.PIPE5TRE) -#define PIPE5TRN_1 (USB201.PIPE5TRN) -#define PIPEBTRE_1 (USB201.PIPEBTRE) -#define PIPEBTRN_1 (USB201.PIPEBTRN) -#define PIPECTRE_1 (USB201.PIPECTRE) -#define PIPECTRN_1 (USB201.PIPECTRN) -#define PIPEDTRE_1 (USB201.PIPEDTRE) -#define PIPEDTRN_1 (USB201.PIPEDTRN) -#define PIPEETRE_1 (USB201.PIPEETRE) -#define PIPEETRN_1 (USB201.PIPEETRN) -#define PIPEFTRE_1 (USB201.PIPEFTRE) -#define PIPEFTRN_1 (USB201.PIPEFTRN) -#define PIPE9TRE_1 (USB201.PIPE9TRE) -#define PIPE9TRN_1 (USB201.PIPE9TRN) -#define PIPEATRE_1 (USB201.PIPEATRE) -#define PIPEATRN_1 (USB201.PIPEATRN) -#define DEVADD0_1 (USB201.DEVADD0) -#define DEVADD1_1 (USB201.DEVADD1) -#define DEVADD2_1 (USB201.DEVADD2) -#define DEVADD3_1 (USB201.DEVADD3) -#define DEVADD4_1 (USB201.DEVADD4) -#define DEVADD5_1 (USB201.DEVADD5) -#define DEVADD6_1 (USB201.DEVADD6) -#define DEVADD7_1 (USB201.DEVADD7) -#define DEVADD8_1 (USB201.DEVADD8) -#define DEVADD9_1 (USB201.DEVADD9) -#define DEVADDA_1 (USB201.DEVADDA) -#define SUSPMODE_1 (USB201.SUSPMODE) -#define D0FIFOB0_1 (USB201.D0FIFOB0) -#define D0FIFOB1_1 (USB201.D0FIFOB1) -#define D0FIFOB2_1 (USB201.D0FIFOB2) -#define D0FIFOB3_1 (USB201.D0FIFOB3) -#define D0FIFOB4_1 (USB201.D0FIFOB4) -#define D0FIFOB5_1 (USB201.D0FIFOB5) -#define D0FIFOB6_1 (USB201.D0FIFOB6) -#define D0FIFOB7_1 (USB201.D0FIFOB7) -#define D1FIFOB0_1 (USB201.D1FIFOB0) -#define D1FIFOB1_1 (USB201.D1FIFOB1) -#define D1FIFOB2_1 (USB201.D1FIFOB2) -#define D1FIFOB3_1 (USB201.D1FIFOB3) -#define D1FIFOB4_1 (USB201.D1FIFOB4) -#define D1FIFOB5_1 (USB201.D1FIFOB5) -#define D1FIFOB6_1 (USB201.D1FIFOB6) -#define D1FIFOB7_1 (USB201.D1FIFOB7) - -#define USB20_D0FBCFG_COUNT (2) -#define USB20_D0FIFO_COUNT (2) -#define USB20_INTENB0_COUNT (2) -#define USB20_INTSTS0_COUNT (2) -#define USB20_PIPE1CTR_COUNT (0xF) -#define USB20_DEVADD0_COUNT (0xB) -#define USB20_D0FIFOB0_COUNT (0x8) - - -typedef struct st_usb20 -{ - /* USB20 */ - volatile uint16_t SYSCFG0; /* SYSCFG0 */ - volatile uint16_t BUSWAIT; /* BUSWAIT */ - volatile uint16_t SYSSTS0; /* SYSSTS0 */ - volatile uint8_t dummy1[2]; /* */ - volatile uint16_t DVSTCTR0; /* DVSTCTR0 */ - volatile uint8_t dummy2[2]; /* */ - volatile uint16_t TESTMODE; /* TESTMODE */ - volatile uint8_t dummy3[2]; /* */ - -/* #define USB20_D0FBCFG_COUNT (2) */ - volatile uint16_t D0FBCFG; /* D0FBCFG */ - volatile uint16_t D1FBCFG; /* D1FBCFG */ - union iodefine_reg32_t CFIFO; /* CFIFO */ - -/* #define USB20_D0FIFO_COUNT (2) */ - union iodefine_reg32_t D0FIFO; /* D0FIFO */ - union iodefine_reg32_t D1FIFO; /* D1FIFO */ - - volatile uint16_t CFIFOSEL; /* CFIFOSEL */ - volatile uint16_t CFIFOCTR; /* CFIFOCTR */ - volatile uint8_t dummy4[4]; /* */ - -/* start of struct st_usb20_from_d0fifosel */ - volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ - volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ - -/* end of struct st_usb20_from_d0fifosel */ - -/* start of struct st_usb20_from_d0fifosel */ - volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */ - volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */ - -/* end of struct st_usb20_from_d0fifosel */ - -/* #define USB20_INTENB0_COUNT (2) */ - volatile uint16_t INTENB0; /* INTENB0 */ - volatile uint16_t INTENB1; /* INTENB1 */ - volatile uint8_t dummy5[2]; /* */ - volatile uint16_t BRDYENB; /* BRDYENB */ - volatile uint16_t NRDYENB; /* NRDYENB */ - volatile uint16_t BEMPENB; /* BEMPENB */ - volatile uint16_t SOFCFG; /* SOFCFG */ - volatile uint8_t dummy6[2]; /* */ - -/* #define USB20_INTSTS0_COUNT (2) */ - volatile uint16_t INTSTS0; /* INTSTS0 */ - volatile uint16_t INTSTS1; /* INTSTS1 */ - volatile uint8_t dummy7[2]; /* */ - volatile uint16_t BRDYSTS; /* BRDYSTS */ - volatile uint16_t NRDYSTS; /* NRDYSTS */ - volatile uint16_t BEMPSTS; /* BEMPSTS */ - volatile uint16_t FRMNUM; /* FRMNUM */ - volatile uint16_t UFRMNUM; /* UFRMNUM */ - volatile uint16_t USBADDR; /* USBADDR */ - volatile uint8_t dummy8[2]; /* */ - volatile uint16_t USBREQ; /* USBREQ */ - volatile uint16_t USBVAL; /* USBVAL */ - volatile uint16_t USBINDX; /* USBINDX */ - volatile uint16_t USBLENG; /* USBLENG */ - volatile uint16_t DCPCFG; /* DCPCFG */ - volatile uint16_t DCPMAXP; /* DCPMAXP */ - volatile uint16_t DCPCTR; /* DCPCTR */ - volatile uint8_t dummy9[2]; /* */ - volatile uint16_t PIPESEL; /* PIPESEL */ - volatile uint8_t dummy10[2]; /* */ - volatile uint16_t PIPECFG; /* PIPECFG */ - volatile uint16_t PIPEBUF; /* PIPEBUF */ - volatile uint16_t PIPEMAXP; /* PIPEMAXP */ - volatile uint16_t PIPEPERI; /* PIPEPERI */ - -/* #define USB20_PIPE1CTR_COUNT (0xF) */ - volatile uint16_t PIPE1CTR; /* PIPE1CTR */ - volatile uint16_t PIPE2CTR; /* PIPE2CTR */ - volatile uint16_t PIPE3CTR; /* PIPE3CTR */ - volatile uint16_t PIPE4CTR; /* PIPE4CTR */ - volatile uint16_t PIPE5CTR; /* PIPE5CTR */ - volatile uint16_t PIPE6CTR; /* PIPE6CTR */ - volatile uint16_t PIPE7CTR; /* PIPE7CTR */ - volatile uint16_t PIPE8CTR; /* PIPE8CTR */ - volatile uint16_t PIPE9CTR; /* PIPE9CTR */ - volatile uint16_t PIPEACTR; /* PIPEACTR */ - volatile uint16_t PIPEBCTR; /* PIPEBCTR */ - volatile uint16_t PIPECCTR; /* PIPECCTR */ - volatile uint16_t PIPEDCTR; /* PIPEDCTR */ - volatile uint16_t PIPEECTR; /* PIPEECTR */ - volatile uint16_t PIPEFCTR; /* PIPEFCTR */ - volatile uint8_t dummy11[2]; /* */ - -/* start of struct st_usb20_from_pipe1tre */ - volatile uint16_t PIPE1TRE; /* PIPE1TRE */ - volatile uint16_t PIPE1TRN; /* PIPE1TRN */ - -/* end of struct st_usb20_from_pipe1tre */ - -/* start of struct st_usb20_from_pipe1tre */ - volatile uint16_t PIPE2TRE; /* PIPE2TRE */ - volatile uint16_t PIPE2TRN; /* PIPE2TRN */ - -/* end of struct st_usb20_from_pipe1tre */ - -/* start of struct st_usb20_from_pipe1tre */ - volatile uint16_t PIPE3TRE; /* PIPE3TRE */ - volatile uint16_t PIPE3TRN; /* PIPE3TRN */ - -/* end of struct st_usb20_from_pipe1tre */ - -/* start of struct st_usb20_from_pipe1tre */ - volatile uint16_t PIPE4TRE; /* PIPE4TRE */ - volatile uint16_t PIPE4TRN; /* PIPE4TRN */ - -/* end of struct st_usb20_from_pipe1tre */ - -/* start of struct st_usb20_from_pipe1tre */ - volatile uint16_t PIPE5TRE; /* PIPE5TRE */ - volatile uint16_t PIPE5TRN; /* PIPE5TRN */ - -/* end of struct st_usb20_from_pipe1tre */ - volatile uint16_t PIPEBTRE; /* PIPEBTRE */ - volatile uint16_t PIPEBTRN; /* PIPEBTRN */ - volatile uint16_t PIPECTRE; /* PIPECTRE */ - volatile uint16_t PIPECTRN; /* PIPECTRN */ - volatile uint16_t PIPEDTRE; /* PIPEDTRE */ - volatile uint16_t PIPEDTRN; /* PIPEDTRN */ - volatile uint16_t PIPEETRE; /* PIPEETRE */ - volatile uint16_t PIPEETRN; /* PIPEETRN */ - volatile uint16_t PIPEFTRE; /* PIPEFTRE */ - volatile uint16_t PIPEFTRN; /* PIPEFTRN */ - volatile uint16_t PIPE9TRE; /* PIPE9TRE */ - volatile uint16_t PIPE9TRN; /* PIPE9TRN */ - volatile uint16_t PIPEATRE; /* PIPEATRE */ - volatile uint16_t PIPEATRN; /* PIPEATRN */ - volatile uint8_t dummy12[16]; /* */ - -/* #define USB20_DEVADD0_COUNT (0xB) */ - volatile uint16_t DEVADD0; /* DEVADD0 */ - volatile uint16_t DEVADD1; /* DEVADD1 */ - volatile uint16_t DEVADD2; /* DEVADD2 */ - volatile uint16_t DEVADD3; /* DEVADD3 */ - volatile uint16_t DEVADD4; /* DEVADD4 */ - volatile uint16_t DEVADD5; /* DEVADD5 */ - volatile uint16_t DEVADD6; /* DEVADD6 */ - volatile uint16_t DEVADD7; /* DEVADD7 */ - volatile uint16_t DEVADD8; /* DEVADD8 */ - volatile uint16_t DEVADD9; /* DEVADD9 */ - volatile uint16_t DEVADDA; /* DEVADDA */ - volatile uint8_t dummy13[28]; /* */ - volatile uint16_t SUSPMODE; /* SUSPMODE */ - volatile uint8_t dummy14[92]; /* */ - -/* start of struct st_usb20_from_dmfifob0 */ - volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ - volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ - volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ - volatile uint32_t D0FIFOB3; /* D0FIFOB3 */ - volatile uint32_t D0FIFOB4; /* D0FIFOB4 */ - volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ - volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ - volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ - -/* end of struct st_usb20_from_dmfifob0 */ - -/* start of struct st_usb20_from_dmfifob0 */ - volatile uint32_t D1FIFOB0; /* D1FIFOB0 */ - volatile uint32_t D1FIFOB1; /* D1FIFOB1 */ - volatile uint32_t D1FIFOB2; /* D1FIFOB2 */ - volatile uint32_t D1FIFOB3; /* D1FIFOB3 */ - volatile uint32_t D1FIFOB4; /* D1FIFOB4 */ - volatile uint32_t D1FIFOB5; /* D1FIFOB5 */ - volatile uint32_t D1FIFOB6; /* D1FIFOB6 */ - volatile uint32_t D1FIFOB7; /* D1FIFOB7 */ - -/* end of struct st_usb20_from_dmfifob0 */ -} r_io_usb20_t; - - -typedef struct st_usb20_from_d0fifosel -{ - - volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ - volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ -} r_io_usb20_from_d0fifosel_t; - - -typedef struct st_usb20_from_pipe1tre -{ - - volatile uint16_t PIPE1TRE; /* PIPE1TRE */ - volatile uint16_t PIPE1TRN; /* PIPE1TRN */ -} r_io_usb20_from_pipe1tre_t; - - -typedef struct st_usb20_from_dmfifob0 -{ - - -/* #define USB20_D0FIFOB0_COUNT (0x8) */ - volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ - volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ - volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ - volatile uint32_t D0FIFOB3; /* D0FIFOB3 */ - volatile uint32_t D0FIFOB4; /* D0FIFOB4 */ - volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ - volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ - volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ -} r_io_usb20_from_dmfifob0_t; - - -/* Channel array defines of USB20 (2)*/ -#ifdef DECLARE_USB20_CHANNELS -volatile struct st_usb20* USB20[ USB20_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - USB20_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_USB20_CHANNELS */ - -#ifdef DECLARE_USB20_FROM_D0FIFOB0_CHANNELS -volatile struct st_usb20_from_dmfifob0* USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - USB20_FROM_D0FIFOB0_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */ - -#ifdef DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS -volatile struct st_usb20_from_pipe1tre* USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - USB20_FROM_PIPE1ATRE_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */ - -#ifdef DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS -volatile struct st_usb20_from_d0fifosel* USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - USB20_FROM_D0FIFOSEL_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */ -/* End of channel array defines of USB20 (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h deleted file mode 100644 index 3c962342e5a..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h +++ /dev/null @@ -1,1788 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : vdc5_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef VDC5_IODEFINE_H -#define VDC5_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ -#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ - - -/* Start of channel array defines of VDC5 */ - -/* Channel array defines of VDC5 */ -/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ -#define VDC5_COUNT (2) -#define VDC5_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &VDC50, &VDC51 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - - - -/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */ -/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ -#define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2) -#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ - &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ -#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ -#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ -#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ - - - - -/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */ -/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ -#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2) -#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ - &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ -#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ -#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ -#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ - - - - -/* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */ -/*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ -#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT (2) -#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ - &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ -#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ -#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ -#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ - - - - -/* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */ -/*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ -#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT (2) -#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ - &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ -#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ -#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ -#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ - - - - -/* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */ -/*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ -#define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT (2) -#define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ - &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ -#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ -#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ -#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ - - - - -/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */ -/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ -#define VDC50_FROM_GR0_AB7_ARRAY_COUNT (2) -#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ - &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ -#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ -#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ -#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ - - - - -/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */ -/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ -#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (2) -#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ - &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ -#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ -#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ -#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ - - -/* End of channel array defines of VDC5 */ - - -#define VDC50INP_UPDATE (VDC50.INP_UPDATE) -#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT) -#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT) -#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ) -#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ) -#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE) -#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0) -#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1) -#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE) -#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0) -#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1) -#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0) -#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1) -#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0) -#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1) -#define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG) -#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE) -#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1) -#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2) -#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3) -#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4) -#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5) -#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6) -#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7) -#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9) -#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0) -#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT) -#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1) -#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2) -#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3) -#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4) -#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5) -#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6) -#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7) -#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1) -#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2) -#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3) -#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4) -#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5) -#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6) -#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7) -#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8) -#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1) -#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE) -#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1) -#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2) -#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3) -#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4) -#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5) -#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6) -#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7) -#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8) -#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9) -#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10) -#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11) -#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1) -#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0) -#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1) -#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2) -#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3) -#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD) -#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT) -#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE) -#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD) -#define VDC50GR0_FLM1 (VDC50.GR0_FLM1) -#define VDC50GR0_FLM2 (VDC50.GR0_FLM2) -#define VDC50GR0_FLM3 (VDC50.GR0_FLM3) -#define VDC50GR0_FLM4 (VDC50.GR0_FLM4) -#define VDC50GR0_FLM5 (VDC50.GR0_FLM5) -#define VDC50GR0_FLM6 (VDC50.GR0_FLM6) -#define VDC50GR0_AB1 (VDC50.GR0_AB1) -#define VDC50GR0_AB2 (VDC50.GR0_AB2) -#define VDC50GR0_AB3 (VDC50.GR0_AB3) -#define VDC50GR0_AB7 (VDC50.GR0_AB7) -#define VDC50GR0_AB8 (VDC50.GR0_AB8) -#define VDC50GR0_AB9 (VDC50.GR0_AB9) -#define VDC50GR0_AB10 (VDC50.GR0_AB10) -#define VDC50GR0_AB11 (VDC50.GR0_AB11) -#define VDC50GR0_BASE (VDC50.GR0_BASE) -#define VDC50GR0_CLUT (VDC50.GR0_CLUT) -#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE) -#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET) -#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1) -#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2) -#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3) -#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1) -#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2) -#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3) -#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4) -#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5) -#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6) -#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1) -#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2) -#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE) -#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0) -#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1) -#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0) -#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1) -#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0) -#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1) -#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE) -#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD) -#define VDC50GR2_FLM1 (VDC50.GR2_FLM1) -#define VDC50GR2_FLM2 (VDC50.GR2_FLM2) -#define VDC50GR2_FLM3 (VDC50.GR2_FLM3) -#define VDC50GR2_FLM4 (VDC50.GR2_FLM4) -#define VDC50GR2_FLM5 (VDC50.GR2_FLM5) -#define VDC50GR2_FLM6 (VDC50.GR2_FLM6) -#define VDC50GR2_AB1 (VDC50.GR2_AB1) -#define VDC50GR2_AB2 (VDC50.GR2_AB2) -#define VDC50GR2_AB3 (VDC50.GR2_AB3) -#define VDC50GR2_AB4 (VDC50.GR2_AB4) -#define VDC50GR2_AB5 (VDC50.GR2_AB5) -#define VDC50GR2_AB6 (VDC50.GR2_AB6) -#define VDC50GR2_AB7 (VDC50.GR2_AB7) -#define VDC50GR2_AB8 (VDC50.GR2_AB8) -#define VDC50GR2_AB9 (VDC50.GR2_AB9) -#define VDC50GR2_AB10 (VDC50.GR2_AB10) -#define VDC50GR2_AB11 (VDC50.GR2_AB11) -#define VDC50GR2_BASE (VDC50.GR2_BASE) -#define VDC50GR2_CLUT (VDC50.GR2_CLUT) -#define VDC50GR2_MON (VDC50.GR2_MON) -#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE) -#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD) -#define VDC50GR3_FLM1 (VDC50.GR3_FLM1) -#define VDC50GR3_FLM2 (VDC50.GR3_FLM2) -#define VDC50GR3_FLM3 (VDC50.GR3_FLM3) -#define VDC50GR3_FLM4 (VDC50.GR3_FLM4) -#define VDC50GR3_FLM5 (VDC50.GR3_FLM5) -#define VDC50GR3_FLM6 (VDC50.GR3_FLM6) -#define VDC50GR3_AB1 (VDC50.GR3_AB1) -#define VDC50GR3_AB2 (VDC50.GR3_AB2) -#define VDC50GR3_AB3 (VDC50.GR3_AB3) -#define VDC50GR3_AB4 (VDC50.GR3_AB4) -#define VDC50GR3_AB5 (VDC50.GR3_AB5) -#define VDC50GR3_AB6 (VDC50.GR3_AB6) -#define VDC50GR3_AB7 (VDC50.GR3_AB7) -#define VDC50GR3_AB8 (VDC50.GR3_AB8) -#define VDC50GR3_AB9 (VDC50.GR3_AB9) -#define VDC50GR3_AB10 (VDC50.GR3_AB10) -#define VDC50GR3_AB11 (VDC50.GR3_AB11) -#define VDC50GR3_BASE (VDC50.GR3_BASE) -#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT) -#define VDC50GR3_MON (VDC50.GR3_MON) -#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE) -#define VDC50GAM_SW (VDC50.GAM_SW) -#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1) -#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2) -#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3) -#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4) -#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5) -#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6) -#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7) -#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8) -#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9) -#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10) -#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11) -#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12) -#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13) -#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14) -#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15) -#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16) -#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1) -#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2) -#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3) -#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4) -#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5) -#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6) -#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7) -#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8) -#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE) -#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1) -#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2) -#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3) -#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4) -#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5) -#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6) -#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7) -#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8) -#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9) -#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10) -#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11) -#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12) -#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13) -#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14) -#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15) -#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16) -#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1) -#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2) -#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3) -#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4) -#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5) -#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6) -#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7) -#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8) -#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE) -#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1) -#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2) -#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3) -#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4) -#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5) -#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6) -#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7) -#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8) -#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9) -#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10) -#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11) -#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12) -#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13) -#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14) -#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15) -#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16) -#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1) -#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2) -#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3) -#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4) -#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5) -#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6) -#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7) -#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8) -#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE) -#define VDC50TCON_TIM (VDC50.TCON_TIM) -#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1) -#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2) -#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1) -#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2) -#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1) -#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2) -#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1) -#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2) -#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1) -#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2) -#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1) -#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2) -#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1) -#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2) -#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE) -#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE) -#define VDC50OUT_SET (VDC50.OUT_SET) -#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1) -#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2) -#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST) -#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA) -#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE) -#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1) -#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2) -#define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3) -#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4) -#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5) -#define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6) -#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK) -#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT) -#define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE) -#define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1) -#define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2) -#define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3) -#define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4) -#define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5) -#define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6) -#define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7) -#define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9) -#define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0) -#define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT) -#define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1) -#define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2) -#define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3) -#define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4) -#define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5) -#define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6) -#define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7) -#define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1) -#define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2) -#define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3) -#define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4) -#define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5) -#define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6) -#define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7) -#define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8) -#define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1) -#define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE) -#define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1) -#define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2) -#define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3) -#define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4) -#define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5) -#define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6) -#define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7) -#define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8) -#define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9) -#define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10) -#define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11) -#define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1) -#define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0) -#define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1) -#define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2) -#define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3) -#define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD) -#define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT) -#define VDC50GR1_UPDATE (VDC50.GR1_UPDATE) -#define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD) -#define VDC50GR1_FLM1 (VDC50.GR1_FLM1) -#define VDC50GR1_FLM2 (VDC50.GR1_FLM2) -#define VDC50GR1_FLM3 (VDC50.GR1_FLM3) -#define VDC50GR1_FLM4 (VDC50.GR1_FLM4) -#define VDC50GR1_FLM5 (VDC50.GR1_FLM5) -#define VDC50GR1_FLM6 (VDC50.GR1_FLM6) -#define VDC50GR1_AB1 (VDC50.GR1_AB1) -#define VDC50GR1_AB2 (VDC50.GR1_AB2) -#define VDC50GR1_AB3 (VDC50.GR1_AB3) -#define VDC50GR1_AB4 (VDC50.GR1_AB4) -#define VDC50GR1_AB5 (VDC50.GR1_AB5) -#define VDC50GR1_AB6 (VDC50.GR1_AB6) -#define VDC50GR1_AB7 (VDC50.GR1_AB7) -#define VDC50GR1_AB8 (VDC50.GR1_AB8) -#define VDC50GR1_AB9 (VDC50.GR1_AB9) -#define VDC50GR1_AB10 (VDC50.GR1_AB10) -#define VDC50GR1_AB11 (VDC50.GR1_AB11) -#define VDC50GR1_BASE (VDC50.GR1_BASE) -#define VDC50GR1_CLUT (VDC50.GR1_CLUT) -#define VDC50GR1_MON (VDC50.GR1_MON) -#define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE) -#define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET) -#define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1) -#define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2) -#define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3) -#define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1) -#define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2) -#define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3) -#define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4) -#define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5) -#define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6) -#define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1) -#define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2) -#define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE) -#define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0) -#define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1) -#define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0) -#define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1) -#define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0) -#define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1) -#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE) -#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1) -#define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2) -#define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3) -#define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4) -#define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5) -#define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6) -#define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7) -#define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE) -#define VDC50GR_VIN_MON (VDC50.GR_VIN_MON) -#define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE) -#define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1) -#define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2) -#define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3) -#define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4) -#define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5) -#define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6) -#define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7) -#define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1) -#define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2) -#define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3) -#define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7) -#define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1) -#define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2) -#define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3) -#define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8) -#define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1) -#define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE) -#define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1) -#define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2) -#define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3) -#define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4) -#define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5) -#define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6) -#define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7) -#define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE) -#define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD) -#define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1) -#define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2) -#define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3) -#define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4) -#define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5) -#define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6) -#define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1) -#define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2) -#define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3) -#define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7) -#define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8) -#define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9) -#define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10) -#define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11) -#define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE) -#define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT) -#define VDC50GR_OIR_MON (VDC50.GR_OIR_MON) -#define VDC51INP_UPDATE (VDC51.INP_UPDATE) -#define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT) -#define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT) -#define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ) -#define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ) -#define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE) -#define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0) -#define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1) -#define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE) -#define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0) -#define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1) -#define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0) -#define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1) -#define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0) -#define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1) -#define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG) -#define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE) -#define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1) -#define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2) -#define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3) -#define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4) -#define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5) -#define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6) -#define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7) -#define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9) -#define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0) -#define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT) -#define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1) -#define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2) -#define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3) -#define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4) -#define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5) -#define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6) -#define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7) -#define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1) -#define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2) -#define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3) -#define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4) -#define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5) -#define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6) -#define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7) -#define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8) -#define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1) -#define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE) -#define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1) -#define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2) -#define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3) -#define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4) -#define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5) -#define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6) -#define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7) -#define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8) -#define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9) -#define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10) -#define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11) -#define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1) -#define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0) -#define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1) -#define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2) -#define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3) -#define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD) -#define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT) -#define VDC51GR0_UPDATE (VDC51.GR0_UPDATE) -#define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD) -#define VDC51GR0_FLM1 (VDC51.GR0_FLM1) -#define VDC51GR0_FLM2 (VDC51.GR0_FLM2) -#define VDC51GR0_FLM3 (VDC51.GR0_FLM3) -#define VDC51GR0_FLM4 (VDC51.GR0_FLM4) -#define VDC51GR0_FLM5 (VDC51.GR0_FLM5) -#define VDC51GR0_FLM6 (VDC51.GR0_FLM6) -#define VDC51GR0_AB1 (VDC51.GR0_AB1) -#define VDC51GR0_AB2 (VDC51.GR0_AB2) -#define VDC51GR0_AB3 (VDC51.GR0_AB3) -#define VDC51GR0_AB7 (VDC51.GR0_AB7) -#define VDC51GR0_AB8 (VDC51.GR0_AB8) -#define VDC51GR0_AB9 (VDC51.GR0_AB9) -#define VDC51GR0_AB10 (VDC51.GR0_AB10) -#define VDC51GR0_AB11 (VDC51.GR0_AB11) -#define VDC51GR0_BASE (VDC51.GR0_BASE) -#define VDC51GR0_CLUT (VDC51.GR0_CLUT) -#define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE) -#define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET) -#define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1) -#define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2) -#define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3) -#define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1) -#define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2) -#define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3) -#define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4) -#define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5) -#define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6) -#define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1) -#define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2) -#define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE) -#define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0) -#define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1) -#define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0) -#define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1) -#define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0) -#define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1) -#define VDC51GR2_UPDATE (VDC51.GR2_UPDATE) -#define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD) -#define VDC51GR2_FLM1 (VDC51.GR2_FLM1) -#define VDC51GR2_FLM2 (VDC51.GR2_FLM2) -#define VDC51GR2_FLM3 (VDC51.GR2_FLM3) -#define VDC51GR2_FLM4 (VDC51.GR2_FLM4) -#define VDC51GR2_FLM5 (VDC51.GR2_FLM5) -#define VDC51GR2_FLM6 (VDC51.GR2_FLM6) -#define VDC51GR2_AB1 (VDC51.GR2_AB1) -#define VDC51GR2_AB2 (VDC51.GR2_AB2) -#define VDC51GR2_AB3 (VDC51.GR2_AB3) -#define VDC51GR2_AB4 (VDC51.GR2_AB4) -#define VDC51GR2_AB5 (VDC51.GR2_AB5) -#define VDC51GR2_AB6 (VDC51.GR2_AB6) -#define VDC51GR2_AB7 (VDC51.GR2_AB7) -#define VDC51GR2_AB8 (VDC51.GR2_AB8) -#define VDC51GR2_AB9 (VDC51.GR2_AB9) -#define VDC51GR2_AB10 (VDC51.GR2_AB10) -#define VDC51GR2_AB11 (VDC51.GR2_AB11) -#define VDC51GR2_BASE (VDC51.GR2_BASE) -#define VDC51GR2_CLUT (VDC51.GR2_CLUT) -#define VDC51GR2_MON (VDC51.GR2_MON) -#define VDC51GR3_UPDATE (VDC51.GR3_UPDATE) -#define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD) -#define VDC51GR3_FLM1 (VDC51.GR3_FLM1) -#define VDC51GR3_FLM2 (VDC51.GR3_FLM2) -#define VDC51GR3_FLM3 (VDC51.GR3_FLM3) -#define VDC51GR3_FLM4 (VDC51.GR3_FLM4) -#define VDC51GR3_FLM5 (VDC51.GR3_FLM5) -#define VDC51GR3_FLM6 (VDC51.GR3_FLM6) -#define VDC51GR3_AB1 (VDC51.GR3_AB1) -#define VDC51GR3_AB2 (VDC51.GR3_AB2) -#define VDC51GR3_AB3 (VDC51.GR3_AB3) -#define VDC51GR3_AB4 (VDC51.GR3_AB4) -#define VDC51GR3_AB5 (VDC51.GR3_AB5) -#define VDC51GR3_AB6 (VDC51.GR3_AB6) -#define VDC51GR3_AB7 (VDC51.GR3_AB7) -#define VDC51GR3_AB8 (VDC51.GR3_AB8) -#define VDC51GR3_AB9 (VDC51.GR3_AB9) -#define VDC51GR3_AB10 (VDC51.GR3_AB10) -#define VDC51GR3_AB11 (VDC51.GR3_AB11) -#define VDC51GR3_BASE (VDC51.GR3_BASE) -#define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT) -#define VDC51GR3_MON (VDC51.GR3_MON) -#define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE) -#define VDC51GAM_SW (VDC51.GAM_SW) -#define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1) -#define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2) -#define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3) -#define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4) -#define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5) -#define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6) -#define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7) -#define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8) -#define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9) -#define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10) -#define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11) -#define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12) -#define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13) -#define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14) -#define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15) -#define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16) -#define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1) -#define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2) -#define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3) -#define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4) -#define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5) -#define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6) -#define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7) -#define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8) -#define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE) -#define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1) -#define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2) -#define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3) -#define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4) -#define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5) -#define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6) -#define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7) -#define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8) -#define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9) -#define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10) -#define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11) -#define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12) -#define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13) -#define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14) -#define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15) -#define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16) -#define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1) -#define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2) -#define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3) -#define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4) -#define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5) -#define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6) -#define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7) -#define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8) -#define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE) -#define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1) -#define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2) -#define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3) -#define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4) -#define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5) -#define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6) -#define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7) -#define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8) -#define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9) -#define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10) -#define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11) -#define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12) -#define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13) -#define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14) -#define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15) -#define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16) -#define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1) -#define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2) -#define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3) -#define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4) -#define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5) -#define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6) -#define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7) -#define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8) -#define VDC51TCON_UPDATE (VDC51.TCON_UPDATE) -#define VDC51TCON_TIM (VDC51.TCON_TIM) -#define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1) -#define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2) -#define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1) -#define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2) -#define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1) -#define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2) -#define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1) -#define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2) -#define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1) -#define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2) -#define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1) -#define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2) -#define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1) -#define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2) -#define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE) -#define VDC51OUT_UPDATE (VDC51.OUT_UPDATE) -#define VDC51OUT_SET (VDC51.OUT_SET) -#define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1) -#define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2) -#define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST) -#define VDC51OUT_PDTHA (VDC51.OUT_PDTHA) -#define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE) -#define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1) -#define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2) -#define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3) -#define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4) -#define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5) -#define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6) -#define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK) -#define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT) -#define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE) -#define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1) -#define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2) -#define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3) -#define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4) -#define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5) -#define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6) -#define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7) -#define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9) -#define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0) -#define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT) -#define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1) -#define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2) -#define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3) -#define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4) -#define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5) -#define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6) -#define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7) -#define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1) -#define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2) -#define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3) -#define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4) -#define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5) -#define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6) -#define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7) -#define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8) -#define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1) -#define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE) -#define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1) -#define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2) -#define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3) -#define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4) -#define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5) -#define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6) -#define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7) -#define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8) -#define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9) -#define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10) -#define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11) -#define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1) -#define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0) -#define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1) -#define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2) -#define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3) -#define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD) -#define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT) -#define VDC51GR1_UPDATE (VDC51.GR1_UPDATE) -#define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD) -#define VDC51GR1_FLM1 (VDC51.GR1_FLM1) -#define VDC51GR1_FLM2 (VDC51.GR1_FLM2) -#define VDC51GR1_FLM3 (VDC51.GR1_FLM3) -#define VDC51GR1_FLM4 (VDC51.GR1_FLM4) -#define VDC51GR1_FLM5 (VDC51.GR1_FLM5) -#define VDC51GR1_FLM6 (VDC51.GR1_FLM6) -#define VDC51GR1_AB1 (VDC51.GR1_AB1) -#define VDC51GR1_AB2 (VDC51.GR1_AB2) -#define VDC51GR1_AB3 (VDC51.GR1_AB3) -#define VDC51GR1_AB4 (VDC51.GR1_AB4) -#define VDC51GR1_AB5 (VDC51.GR1_AB5) -#define VDC51GR1_AB6 (VDC51.GR1_AB6) -#define VDC51GR1_AB7 (VDC51.GR1_AB7) -#define VDC51GR1_AB8 (VDC51.GR1_AB8) -#define VDC51GR1_AB9 (VDC51.GR1_AB9) -#define VDC51GR1_AB10 (VDC51.GR1_AB10) -#define VDC51GR1_AB11 (VDC51.GR1_AB11) -#define VDC51GR1_BASE (VDC51.GR1_BASE) -#define VDC51GR1_CLUT (VDC51.GR1_CLUT) -#define VDC51GR1_MON (VDC51.GR1_MON) -#define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE) -#define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET) -#define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1) -#define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2) -#define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3) -#define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1) -#define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2) -#define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3) -#define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4) -#define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5) -#define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6) -#define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1) -#define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2) -#define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE) -#define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0) -#define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1) -#define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0) -#define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1) -#define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0) -#define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1) -#define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE) -#define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1) -#define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2) -#define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3) -#define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4) -#define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5) -#define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6) -#define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7) -#define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE) -#define VDC51GR_VIN_MON (VDC51.GR_VIN_MON) -#define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE) -#define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1) -#define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2) -#define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3) -#define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4) -#define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5) -#define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6) -#define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7) -#define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1) -#define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2) -#define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3) -#define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7) -#define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1) -#define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2) -#define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3) -#define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8) -#define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1) -#define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE) -#define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1) -#define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2) -#define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3) -#define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4) -#define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5) -#define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6) -#define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7) -#define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE) -#define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD) -#define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1) -#define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2) -#define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3) -#define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4) -#define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5) -#define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6) -#define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1) -#define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2) -#define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3) -#define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7) -#define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8) -#define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9) -#define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10) -#define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11) -#define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE) -#define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT) -#define VDC51GR_OIR_MON (VDC51.GR_OIR_MON) - -#define VDC5_IMGCNT_NR_CNT0_COUNT (2) -#define VDC5_SC0_SCL0_FRC1_COUNT (7) -#define VDC5_SC0_SCL0_DS1_COUNT (7) -#define VDC5_SC0_SCL0_US1_COUNT (8) -#define VDC5_SC0_SCL1_WR1_COUNT (4) -#define VDC5_SC0_SCL1_PBUF0_COUNT (4) -#define VDC5_GR0_FLM1_COUNT (6) -#define VDC5_GR0_AB1_COUNT (3) -#define VDC5_ADJ0_ENH_TIM1_COUNT (3) -#define VDC5_ADJ0_ENH_SHP1_COUNT (6) -#define VDC5_ADJ0_ENH_LTI1_COUNT (2) -#define VDC5_GR2_FLM1_COUNT (6) -#define VDC5_GR2_AB1_COUNT (3) -#define VDC5_GR3_FLM1_COUNT (6) -#define VDC5_GR3_AB1_COUNT (3) -#define VDC5_GAM_G_LUT1_COUNT (16) -#define VDC5_GAM_G_AREA1_COUNT (8) -#define VDC5_GAM_B_LUT1_COUNT (16) -#define VDC5_GAM_B_AREA1_COUNT (8) -#define VDC5_GAM_R_LUT1_COUNT (16) -#define VDC5_GAM_R_AREA1_COUNT (8) -#define VDC5_TCON_TIM_STVA1_COUNT (2) -#define VDC5_TCON_TIM_STVB1_COUNT (2) -#define VDC5_TCON_TIM_STH1_COUNT (2) -#define VDC5_TCON_TIM_STB1_COUNT (2) -#define VDC5_TCON_TIM_CPV1_COUNT (2) -#define VDC5_TCON_TIM_POLA1_COUNT (2) -#define VDC5_TCON_TIM_POLB1_COUNT (2) -#define VDC5_OUT_BRIGHT1_COUNT (2) -#define VDC5_SYSCNT_INT1_COUNT (6) -#define VDC5_SC1_SCL0_FRC1_COUNT (7) -#define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) -#define VDC5_SC1_SC1_SCL0_US1_COUNT (8) -#define VDC5_SC1_SCL1_WR1_COUNT (4) -#define VDC5_SC1_SCL1_PBUF0_COUNT (4) -#define VDC5_GR1_FLM1_COUNT (6) -#define VDC5_GR1_AB1_COUNT (3) -#define VDC5_ADJ1_ENH_TIM1_COUNT (3) -#define VDC5_ADJ1_ENH_SHP1_COUNT (6) -#define VDC5_ADJ1_ENH_LTI1_COUNT (2) -#define VDC5_GR_VIN_AB1_COUNT (7) -#define VDC5_OIR_SCL0_FRC1_COUNT (7) -#define VDC5_OIR_SCL0_DS1_COUNT (3) -#define VDC5_OIR_SCL1_WR1_COUNT (4) -#define VDC5_GR_OIR_FLM1_COUNT (6) -#define VDC5_GR_OIR_AB1_COUNT (3) - - -typedef struct st_vdc5 -{ - /* VDC5 */ - volatile uint32_t INP_UPDATE; /* INP_UPDATE */ - volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ - volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ - volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */ - volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ - volatile uint8_t dummy1[108]; /* */ - volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ - -/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */ - volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ - volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ - volatile uint8_t dummy2[20]; /* */ - volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */ - volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */ - volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */ - volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */ - volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */ - volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */ - volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */ - volatile uint8_t dummy3[4]; /* */ - volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */ - volatile uint8_t dummy4[60]; /* */ - -/* start of struct st_vdc5_from_sc0_scl0_update */ - volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ - -/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */ - volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ - volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ - volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ - volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ - volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ - volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ - volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ - volatile uint8_t dummy5[4]; /* */ - volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ - volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ - volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ - -/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */ - volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ - volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ - volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ - volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ - volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ - volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ - volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ - -/* #define VDC5_SC0_SCL0_US1_COUNT (8) */ - volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ - volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ - volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ - volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ - volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ - volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ - volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ - volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ - volatile uint8_t dummy6[4]; /* */ - volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ - volatile uint8_t dummy7[16]; /* */ - volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ - volatile uint8_t dummy8[4]; /* */ - -/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */ - volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ - volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ - volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ - volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ - volatile uint8_t dummy9[4]; /* */ - volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ - volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ - volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ - volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ - volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ - volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ - -/* end of struct st_vdc5_from_sc0_scl0_update */ - volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ - volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ - -/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ - -/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */ - volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ - volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ - volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ - volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ - volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ - volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ - -/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ - volatile uint8_t dummy10[44]; /* */ - -/* start of struct st_vdc5_from_gr0_update */ - volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ - volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ - -/* #define VDC5_GR0_FLM1_COUNT (6) */ - volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ - volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ - volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ - volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ - volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ - volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ - -/* #define VDC5_GR0_AB1_COUNT (3) */ - volatile uint32_t GR0_AB1; /* GR0_AB1 */ - volatile uint32_t GR0_AB2; /* GR0_AB2 */ - volatile uint32_t GR0_AB3; /* GR0_AB3 */ - -/* end of struct st_vdc5_from_gr0_update */ - volatile uint8_t dummy11[12]; /* */ - -/* start of struct st_vdc5_from_gr0_ab7 */ - volatile uint32_t GR0_AB7; /* GR0_AB7 */ - volatile uint32_t GR0_AB8; /* GR0_AB8 */ - volatile uint32_t GR0_AB9; /* GR0_AB9 */ - volatile uint32_t GR0_AB10; /* GR0_AB10 */ - volatile uint32_t GR0_AB11; /* GR0_AB11 */ - volatile uint32_t GR0_BASE; /* GR0_BASE */ - -/* end of struct st_vdc5_from_gr0_ab7 */ - volatile uint32_t GR0_CLUT; /* GR0_CLUT */ - volatile uint8_t dummy12[44]; /* */ - -/* start of struct st_vdc5_from_adj0_update */ - volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ - volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ - -/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */ - volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ - volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ - volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ - -/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */ - volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ - volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ - volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ - volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ - volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ - volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ - -/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */ - volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ - volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ - volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ - volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ - volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ - volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ - volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ - volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ - volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ - -/* end of struct st_vdc5_from_adj0_update */ - volatile uint8_t dummy13[48]; /* */ - -/* start of struct st_vdc5_from_gr0_update */ - volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ - volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ - -/* #define VDC5_GR2_FLM1_COUNT (6) */ - volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ - volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ - volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ - volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ - volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ - volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ - -/* #define VDC5_GR2_AB1_COUNT (3) */ - volatile uint32_t GR2_AB1; /* GR2_AB1 */ - volatile uint32_t GR2_AB2; /* GR2_AB2 */ - volatile uint32_t GR2_AB3; /* GR2_AB3 */ - -/* end of struct st_vdc5_from_gr0_update */ - volatile uint32_t GR2_AB4; /* GR2_AB4 */ - volatile uint32_t GR2_AB5; /* GR2_AB5 */ - volatile uint32_t GR2_AB6; /* GR2_AB6 */ - -/* start of struct st_vdc5_from_gr0_ab7 */ - volatile uint32_t GR2_AB7; /* GR2_AB7 */ - volatile uint32_t GR2_AB8; /* GR2_AB8 */ - volatile uint32_t GR2_AB9; /* GR2_AB9 */ - volatile uint32_t GR2_AB10; /* GR2_AB10 */ - volatile uint32_t GR2_AB11; /* GR2_AB11 */ - volatile uint32_t GR2_BASE; /* GR2_BASE */ - -/* end of struct st_vdc5_from_gr0_ab7 */ - volatile uint32_t GR2_CLUT; /* GR2_CLUT */ - volatile uint32_t GR2_MON; /* GR2_MON */ - volatile uint8_t dummy14[40]; /* */ - -/* start of struct st_vdc5_from_gr0_update */ - volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ - volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ - -/* #define VDC5_GR3_FLM1_COUNT (6) */ - volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ - volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ - volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ - volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ - volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ - volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ - -/* #define VDC5_GR3_AB1_COUNT (3) */ - volatile uint32_t GR3_AB1; /* GR3_AB1 */ - volatile uint32_t GR3_AB2; /* GR3_AB2 */ - volatile uint32_t GR3_AB3; /* GR3_AB3 */ - -/* end of struct st_vdc5_from_gr0_update */ - volatile uint32_t GR3_AB4; /* GR3_AB4 */ - volatile uint32_t GR3_AB5; /* GR3_AB5 */ - volatile uint32_t GR3_AB6; /* GR3_AB6 */ - -/* start of struct st_vdc5_from_gr0_ab7 */ - volatile uint32_t GR3_AB7; /* GR3_AB7 */ - volatile uint32_t GR3_AB8; /* GR3_AB8 */ - volatile uint32_t GR3_AB9; /* GR3_AB9 */ - volatile uint32_t GR3_AB10; /* GR3_AB10 */ - volatile uint32_t GR3_AB11; /* GR3_AB11 */ - volatile uint32_t GR3_BASE; /* GR3_BASE */ - -/* end of struct st_vdc5_from_gr0_ab7 */ - volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ - volatile uint32_t GR3_MON; /* GR3_MON */ - volatile uint8_t dummy15[40]; /* */ - volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ - volatile uint32_t GAM_SW; /* GAM_SW */ - -/* #define VDC5_GAM_G_LUT1_COUNT (16) */ - volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ - volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ - volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ - volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */ - volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */ - volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */ - volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */ - volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */ - volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */ - volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */ - volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */ - volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */ - volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */ - volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ - volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ - volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ - -/* #define VDC5_GAM_G_AREA1_COUNT (8) */ - volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ - volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ - volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ - volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */ - volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */ - volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */ - volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */ - volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */ - volatile uint8_t dummy16[24]; /* */ - volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ - volatile uint8_t dummy17[4]; /* */ - -/* #define VDC5_GAM_B_LUT1_COUNT (16) */ - volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ - volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ - volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ - volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */ - volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */ - volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */ - volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */ - volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */ - volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */ - volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */ - volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */ - volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */ - volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */ - volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ - volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ - volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ - -/* #define VDC5_GAM_B_AREA1_COUNT (8) */ - volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ - volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ - volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ - volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */ - volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */ - volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */ - volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */ - volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */ - volatile uint8_t dummy18[24]; /* */ - volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ - volatile uint8_t dummy19[4]; /* */ - -/* #define VDC5_GAM_R_LUT1_COUNT (16) */ - volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ - volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ - volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ - volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */ - volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */ - volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */ - volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */ - volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */ - volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */ - volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */ - volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */ - volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */ - volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */ - volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ - volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ - volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ - -/* #define VDC5_GAM_R_AREA1_COUNT (8) */ - volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ - volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ - volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ - volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */ - volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */ - volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */ - volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */ - volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */ - volatile uint8_t dummy20[24]; /* */ - volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ - volatile uint32_t TCON_TIM; /* TCON_TIM */ - -/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */ - volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ - volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ - -/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */ - volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ - volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ - -/* #define VDC5_TCON_TIM_STH1_COUNT (2) */ - volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ - volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ - -/* #define VDC5_TCON_TIM_STB1_COUNT (2) */ - volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ - volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ - -/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */ - volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ - volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ - -/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */ - volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ - volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ - -/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */ - volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ - volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ - volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ - volatile uint8_t dummy21[60]; /* */ - volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ - volatile uint32_t OUT_SET; /* OUT_SET */ - -/* #define VDC5_OUT_BRIGHT1_COUNT (2) */ - volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ - volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ - volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ - volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */ - volatile uint8_t dummy22[12]; /* */ - volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ - volatile uint8_t dummy23[88]; /* */ - -/* #define VDC5_SYSCNT_INT1_COUNT (6) */ - volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ - volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ - volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */ - volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */ - volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */ - volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */ - volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ - volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ - volatile uint8_t dummy24[356]; /* */ - -/* start of struct st_vdc5_from_sc0_scl0_update */ - volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */ - -/* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */ - volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */ - volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */ - volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */ - volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */ - volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */ - volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */ - volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */ - volatile uint8_t dummy25[4]; /* */ - volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */ - volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */ - volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */ - -/* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */ - volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */ - volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */ - volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */ - volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */ - volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */ - volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */ - volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */ - -/* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */ - volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */ - volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */ - volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */ - volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */ - volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */ - volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */ - volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */ - volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */ - volatile uint8_t dummy26[4]; /* */ - volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */ - volatile uint8_t dummy27[16]; /* */ - volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */ - volatile uint8_t dummy28[4]; /* */ - -/* #define VDC5_SC1_SCL1_WR1_COUNT (4) */ - volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */ - volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */ - volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */ - volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */ - volatile uint8_t dummy29[4]; /* */ - volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */ - volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */ - volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */ - volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */ - volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */ - volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */ - -/* end of struct st_vdc5_from_sc0_scl0_update */ - volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */ - volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */ - -/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ - -/* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */ - volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */ - volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */ - volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */ - volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */ - volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */ - volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */ - -/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ - volatile uint8_t dummy30[44]; /* */ - -/* start of struct st_vdc5_from_gr0_update */ - volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */ - volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */ - -/* #define VDC5_GR1_FLM1_COUNT (6) */ - volatile uint32_t GR1_FLM1; /* GR1_FLM1 */ - volatile uint32_t GR1_FLM2; /* GR1_FLM2 */ - volatile uint32_t GR1_FLM3; /* GR1_FLM3 */ - volatile uint32_t GR1_FLM4; /* GR1_FLM4 */ - volatile uint32_t GR1_FLM5; /* GR1_FLM5 */ - volatile uint32_t GR1_FLM6; /* GR1_FLM6 */ - -/* #define VDC5_GR1_AB1_COUNT (3) */ - volatile uint32_t GR1_AB1; /* GR1_AB1 */ - volatile uint32_t GR1_AB2; /* GR1_AB2 */ - volatile uint32_t GR1_AB3; /* GR1_AB3 */ - -/* end of struct st_vdc5_from_gr0_update */ - volatile uint32_t GR1_AB4; /* GR1_AB4 */ - volatile uint32_t GR1_AB5; /* GR1_AB5 */ - volatile uint32_t GR1_AB6; /* GR1_AB6 */ - -/* start of struct st_vdc5_from_gr0_ab7 */ - volatile uint32_t GR1_AB7; /* GR1_AB7 */ - volatile uint32_t GR1_AB8; /* GR1_AB8 */ - volatile uint32_t GR1_AB9; /* GR1_AB9 */ - volatile uint32_t GR1_AB10; /* GR1_AB10 */ - volatile uint32_t GR1_AB11; /* GR1_AB11 */ - volatile uint32_t GR1_BASE; /* GR1_BASE */ - -/* end of struct st_vdc5_from_gr0_ab7 */ - volatile uint32_t GR1_CLUT; /* GR1_CLUT */ - volatile uint32_t GR1_MON; /* GR1_MON */ - volatile uint8_t dummy31[40]; /* */ - -/* start of struct st_vdc5_from_adj0_update */ - volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */ - volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */ - -/* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */ - volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */ - volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */ - volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */ - -/* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */ - volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */ - volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */ - volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */ - volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */ - volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */ - volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */ - -/* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */ - volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */ - volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */ - volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */ - volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */ - volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */ - volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */ - volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */ - volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */ - volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */ - -/* end of struct st_vdc5_from_adj0_update */ - volatile uint8_t dummy32[48]; /* */ - volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ - volatile uint8_t dummy33[28]; /* */ - -/* #define VDC5_GR_VIN_AB1_COUNT (7) */ - volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ - volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */ - volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */ - volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */ - volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */ - volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */ - volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */ - volatile uint8_t dummy34[16]; /* */ - volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */ - volatile uint8_t dummy35[4]; /* */ - volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */ - volatile uint8_t dummy36[40]; /* */ - volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */ - -/* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */ - volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */ - volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */ - volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */ - volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */ - volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */ - volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */ - volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */ - volatile uint8_t dummy37[12]; /* */ - -/* #define VDC5_OIR_SCL0_DS1_COUNT (3) */ - volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */ - volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */ - volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */ - volatile uint8_t dummy38[12]; /* */ - volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */ - volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */ - volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */ - volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */ - volatile uint8_t dummy39[16]; /* */ - volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */ - volatile uint8_t dummy40[4]; /* */ - volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */ - volatile uint8_t dummy41[16]; /* */ - volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */ - volatile uint8_t dummy42[4]; /* */ - -/* #define VDC5_OIR_SCL1_WR1_COUNT (4) */ - volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */ - volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */ - volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */ - volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */ - volatile uint8_t dummy43[4]; /* */ - volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */ - volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */ - volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */ - volatile uint8_t dummy44[88]; /* */ - volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */ - volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */ - -/* #define VDC5_GR_OIR_FLM1_COUNT (6) */ - volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */ - volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */ - volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */ - volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */ - volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */ - volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */ - -/* #define VDC5_GR_OIR_AB1_COUNT (3) */ - volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */ - volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */ - volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */ - volatile uint8_t dummy45[12]; /* */ - volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */ - volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */ - volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */ - volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */ - volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */ - volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */ - volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */ - volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */ -} r_io_vdc5_t; - - -typedef struct st_vdc5_from_gr0_update -{ - - volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ - volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ - volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ - volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ - volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ - volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ - volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ - volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ - volatile uint32_t GR0_AB1; /* GR0_AB1 */ - volatile uint32_t GR0_AB2; /* GR0_AB2 */ - volatile uint32_t GR0_AB3; /* GR0_AB3 */ -} r_io_vdc5_from_gr0_update_t; - - -typedef struct st_vdc5_from_gr0_ab7 -{ - - volatile uint32_t GR0_AB7; /* GR0_AB7 */ - volatile uint32_t GR0_AB8; /* GR0_AB8 */ - volatile uint32_t GR0_AB9; /* GR0_AB9 */ - volatile uint32_t GR0_AB10; /* GR0_AB10 */ - volatile uint32_t GR0_AB11; /* GR0_AB11 */ - volatile uint32_t GR0_BASE; /* GR0_BASE */ -} r_io_vdc5_from_gr0_ab7_t; - - -typedef struct st_vdc5_from_adj0_update -{ - - volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ - volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ - volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ - volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ - volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ - volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ - volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ - volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ - volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ - volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ - volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ - volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ - volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ - volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ - volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ - volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ - volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ - volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ - volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ - volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ -} r_io_vdc5_from_adj0_update_t; - - -typedef struct st_vdc5_from_sc0_scl0_update -{ - - volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ - volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ - volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ - volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ - volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ - volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ - volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ - volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ - volatile uint8_t dummy5[4]; /* */ - volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ - volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ - volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ - volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ - volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ - volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ - volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ - volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ - volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ - volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ - volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ - volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ - volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ - volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ - volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ - volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ - volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ - volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ - volatile uint8_t dummy6[4]; /* */ - volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ - volatile uint8_t dummy7[16]; /* */ - volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ - volatile uint8_t dummy8[4]; /* */ - volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ - volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ - volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ - volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ - volatile uint8_t dummy9[4]; /* */ - volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ - volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ - volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ - volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ - volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ - volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ -} r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */; - - -typedef struct st_vdc5_from_sc0_scl1_pbuf0 -{ - - volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ - volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ - volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ - volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ - volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ - volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ -} r_io_vdc5_from_sc0_scl1_pbuf0_t; - - -/* Channel array defines of VDC5 (2)*/ -#ifdef DECLARE_VDC5_CHANNELS -volatile struct st_vdc5* VDC5[ VDC5_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - VDC5_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_VDC5_CHANNELS */ - -#ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS -volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */ - -#ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS -volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */ - -#ifdef DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS -volatile struct st_vdc5_from_sc0_scl1_pbuf0* VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */ - -#ifdef DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS -volatile struct st_vdc5_from_sc0_scl0_update* VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */ - -#ifdef DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS -volatile struct st_vdc5_from_adj0_update* VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */ - -#ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS -volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */ - -#ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS -volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ -#endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */ -/* End of channel array defines of VDC5 (2)*/ - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h deleted file mode 100644 index 82b448e56c1..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h +++ /dev/null @@ -1,57 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : wdt_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) -******************************************************************************/ -#ifndef WDT_IODEFINE_H -#define WDT_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ - -#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */ - - -#define WDTWTCSR (WDT.WTCSR) -#define WDTWTCNT (WDT.WTCNT) -#define WDTWRCSR (WDT.WRCSR) - - -typedef struct st_wdt -{ - /* WDT */ - volatile uint16_t WTCSR; /* WTCSR */ - volatile uint16_t WTCNT; /* WTCNT */ - volatile uint16_t WRCSR; /* WRCSR */ -} r_io_wdt_t; - - -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/reg32_t.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/reg32_t.h deleted file mode 100644 index 0d40bbc7498..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/reg32_t.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __REG32_T -#define __REG32_T - -union reg32_t { - volatile uint32_t UINT32; - volatile uint16_t UINT16[2]; - volatile uint8_t UINT8[4]; -}; - - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c deleted file mode 100644 index 37877ad9a0c..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c +++ /dev/null @@ -1,281 +0,0 @@ -/**************************************************************************//** - * @file mmu_VK_RZ_A1H.c - * @brief MMU Configuration for RZ_A1H Device Series - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf - - Memory Type -0xffffffff |--------------------------| ------------ - | Peripherals | Device -0xfcf00000 |--------------------------| ------------ - | Page Fault | Fault -0xe8300000 |--------------------------| ------------ - | Peripherals | Device -0xe8000000 |--------------------------| ------------ - | Page Fault | Fault -0x60A00000 |--------------------------| ------------ - | On Chip RAM (10M) Mirror | Fault -0x60000000 |--------------------------| ------------ - | SPI multi I/O 64MB | Fault -0x5c000000 |--------------------------| ------------ - | SPI multi I/O 64MB | Fault -0x58000000 |--------------------------| ------------ - | CS5 Mirror | Fault -0x54000000 |--------------------------| ------------ - | CS4 Mirror | Fault -0x50000000 |--------------------------| ------------ - | CS3 Mirror | Fault -0x4c000000 |--------------------------| ------------ - | CS2 Mirror | Fault -0x48000000 |--------------------------| ------------ - | CS1 Mirror | Fault -0x44000000 |--------------------------| ------------ - | CS0 Mirror | Fault -0x40000000 |--------------------------| ------------ - | BSC | RW -0x3ff00000 |--------------------------| ------------ - | SPI_MIO_BASE | RW -0x3fe00000 |--------------------------| ------------ - | Page Fault | Fault -0x20A00000 |--------------------------| ------------ - | On Chip RAM (10M) | RW -0x20000000 |--------------------------| ------------ - | SPI multi I/O 64MB | RO -0x1c000000 |--------------------------| ------------ - | SPI multi I/O 64MB | RO -0x18000000 |--------------------------| ------------ - | CS5 User Area 64MB | RW -0x14000000 |--------------------------| ------------ - | CS4 User Area 64MB | RW -0x10000000 |--------------------------| ------------ - | CS3 SDRAM 64MB | RW -0x0c000000 |--------------------------| ------------ - | CS2 SDRAM 64MB | RW -0x08000000 |--------------------------| ------------ - | CS1 NOR Flash 64MB | RO -0x04000000 |--------------------------| ------------ - | CS0 NOR Flash 64MB | RO -0x00000000 |--------------------------| ------------ -*/ - -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. -//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors should place all memory in domain 0 -//There are no restrictions by privilege level (PL0 can access all memory) - - -#include "VK_RZ_A1H.h" - -//Import symbols from linker -extern uint32_t Image$$VECTORS$$Base; -extern uint32_t Image$$RO_DATA$$Base; -extern uint32_t Image$$RW_DATA$$Base; -extern uint32_t Image$$RW_IRAM1$$Base; -#if !defined ( __ICCARM__ ) -extern uint32_t Image$$TTB$$ZI$$Base; -#endif - -#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) -#elif defined( __ICCARM__ ) -#else -extern uint32_t Image$$RW_DATA_NC$$Base; -extern uint32_t Image$$ZI_DATA_NC$$Base; -#endif - -extern uint32_t Image$$VECTORS$$Limit; -extern uint32_t Image$$RO_DATA$$Limit; -extern uint32_t Image$$RW_DATA$$Limit; -extern uint32_t Image$$RW_IRAM1$$Limit; -#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) -#else -extern uint32_t Image$$RW_DATA_NC$$Limit; -extern uint32_t Image$$ZI_DATA_NC$$Limit; -#endif - -#if defined( __ICCARM__ ) -#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) -#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) -#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) -#define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1) -#else -#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) -#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) -#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) -#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) -#endif - -#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) -#else -#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) -#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) -#endif - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -#if defined ( __ICCARM__ ) -__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; -uint32_t Image$$VECTORS$$Base; -uint32_t Image$$RO_DATA$$Base; -uint32_t Image$$RW_DATA$$Base; -uint32_t Image$$RW_IRAM1$$Base; - -uint32_t Image$$VECTORS$$Limit; -uint32_t Image$$RO_DATA$$Limit; -uint32_t Image$$RW_DATA$$Limit; -uint32_t Image$$RW_IRAM1$$Limit; -#endif - -void MMU_CreateTranslationTable(void) -{ - mmu_region_attributes_Type region; -#if defined ( __ICCARM__ ) -#pragma section=".intvec" -#pragma section=".rodata" -#pragma section=".rwdata" -#pragma section=".bss" - - Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); - Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); - Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); - Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); - Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); - Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); - Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss"); - Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); -#endif - /* - * Generate descriptors. Refer to core_ca.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - section_normal_nc(Sect_Normal_NC, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Create 4GB of faulting entries - MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); - - // R7S72100 memory map. - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); - -#if defined( __ICCARM__ ) - //Define Image - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); -#else - //Define Image - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); -#endif - -#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); -#elif defined ( __ICCARM__ ) - MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); - -#else - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); - MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); -#endif - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x0 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x1 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x1 (Inner WB WA) */ - __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); - __ISB(); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); - __ISB(); -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c deleted file mode 100644 index d04267618cd..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c +++ /dev/null @@ -1,230 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** -* @file nvic_wrapper.c -* $Rev: $ -* $Date:: $ -* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) -******************************************************************************/ - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#include "VKRZA1H.h" -#include "wdt_iodefine.h" -#include "nvic_wrapper.h" - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - -/****************************************************************************** -Macro definitions -******************************************************************************/ -#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */ -#define WDT_WTCNT_WRITE (0x5A00) -#define WDT_WTCSR_WRITE (0xA500) -#define WDT_WRCSR_WOVF_WRITE (0xA500) -#define WDT_WRCSR_RSTE_WRITE (0x5A00) - -/****************************************************************************** -Imported global variables and functions (from other files) -******************************************************************************/ - -/****************************************************************************** -Exported global variables and functions (to be accessed by other files) -******************************************************************************/ - -/****************************************************************************** -Private global variables and functions -******************************************************************************/ - - - -/* ########################## NVIC functions #################################### */ -void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - GIC_SetBinaryPoint(PriorityGroup); -} - - -uint32_t NVIC_GetPriorityGrouping(void) -{ - return GIC_GetBinaryPoint(); -} - - -void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - GIC_EnableIRQ(IRQn); -} - - -void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - GIC_DisableIRQ(IRQn); -} - - -uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - uint32_t pending; - - pending = GIC_GetIRQStatus(IRQn); - pending = (pending & 0x00000001); - - return pending; -} - - -void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - GIC_SetPendingIRQ(IRQn); -} - - -void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - GIC_ClearPendingIRQ(IRQn); -} - - -uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - uint32_t active; - - active = GIC_GetIRQStatus(IRQn); - active = ((active >> 1) & 0x00000001); - - return active; -} - - -void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - GIC_SetPriority(IRQn, (priority << 3)); -} - - -uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - uint32_t priority_field; - - priority_field = GIC_GetPriority(IRQn); - priority_field = (priority_field >> 3); - return priority_field; -} - - -uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - -void NVIC_SystemReset(void) -{ - uint16_t reg; - uint8_t dummy_read; - /* Use Watch Dog Timer to system reset */ - - /* Set WT/IT bit of WTCSR to 1 = Watch Dog */ - /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */ - reg = (WDT_WTCSR_WRITE | 0x0058); - WDTWTCSR = reg; - - /* Clear Count reg */ - reg = (WDT_WTCNT_WRITE | 0x0000); - WDTWTCNT = reg; - - /* Clear WOVF flag */ - dummy_read = WDTWRCSR; - reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000)); - WDTWRCSR = reg; - /* Enable Internal Reset */ - reg = (WDT_WRCSR_RSTE_WRITE | 0x005F); - WDTWRCSR = reg; - - /* Watch Dog start */ - reg = (WDT_WTCSR_WRITE | 0x0078); - WDTWTCSR = reg; - - while(1); /* wait Internal Reset */ -} - -/* ################################## SysTick function ############################################ */ -uint32_t SysTick_Config(uint32_t ticks) -{ - /* Not support this function */ - /* Use mbed Ticker */ - return (1); /* impossible */ -} - - -/* ##################################### Debug In/Output function ########################################### */ -uint32_t ITM_SendChar (uint32_t ch) -{ - /* Not support this function */ - /* Use mbed Serial */ - return (ch); -} - - -int32_t ITM_ReceiveChar (void) -{ - /* Not support this function */ - /* Use mbed Serial */ - return (-1); /* no character available */ -} - - -int32_t ITM_CheckChar (void) -{ - /* Not support this function */ - /* Use mbed Serial */ - return (0); /* no character available */ -} - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c deleted file mode 100644 index 435531a3f3b..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c +++ /dev/null @@ -1,196 +0,0 @@ -/**************************************************************************//** - * @file os_tick_ostm.c - * @brief CMSIS OS Tick implementation for OS Timer - * @version V1.0.1 - * @date 19. September 2017 - ******************************************************************************/ -/* - * Copyright (c) 2017-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "irq_ctrl.h" -#include "cmsis.h" -#include "mbed_drv_cfg.h" - -// Define OS Timer channel and interrupt number -#define OSTM (OSTM0) -#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) - -#ifdef MBED_CONF_RTOS_PRESENT -#include "os_tick.h" - -// Define OS TImer interrupt priority -#ifndef OSTM_IRQ_PRIORITY -#define OSTM_IRQ_PRIORITY 0xFFU -#endif - -static uint32_t OSTM_Clock; // Timer tick frequency -static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag - -// Setup OS Tick. -int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) -{ - uint32_t clock; - uint32_t prio; - uint32_t bits; - - if (freq == 0U) { - return (-1); - } - - OSTM_PendIRQ = 0U; - - // Get CPG.FRQCR[IFC] bits - clock = (CPG.FRQCR >> 8) & 0x03; - - // Determine Divider 2 output clock by using RENESAS_RZ_A1_P0_CLK - if (clock == 0x03U) { - clock = (RENESAS_RZ_A1_P0_CLK * 3U); - } - else if (clock == 0x01U) { - clock = (RENESAS_RZ_A1_P0_CLK * 3U)/2U; - } - else { - clock = RENESAS_RZ_A1_P0_CLK; - } - - // Determine tick frequency - clock = clock / freq; - - // Save frequency for later - OSTM_Clock = clock; - - // Enable OSTM clock - CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); - - // Stop the OSTM counter - OSTM.OSTMnTT = 0x01U; - - // Set interval timer mode and disable interrupts when counting starts - OSTM.OSTMnCTL = 0x00U; - - // Set compare value - OSTM.OSTMnCMP = clock - 1U; - - // Disable corresponding IRQ - IRQ_Disable (OSTM_IRQn); - IRQ_ClearPending(OSTM_IRQn); - - // Determine number of implemented priority bits - IRQ_SetPriority (OSTM_IRQn, 0xFFU); - - prio = IRQ_GetPriority (OSTM_IRQn); - - // At least bits [7:4] must be implemented - if ((prio & 0xF0U) == 0U) { - return (-1); - } - - for (bits = 0; bits < 4; bits++) { - if ((prio & 0x01) != 0) { - break; - } - prio >>= 1; - } - - // Adjust configured priority to the number of implemented priority bits - prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL; - - // Set OSTM interrupt priority - IRQ_SetPriority(OSTM_IRQn, prio-1U); - - // Set edge-triggered, non-secure, single CPU targeted IRQ - IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE); - - // Register tick interrupt handler function - IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler); - - // Enable corresponding IRQ - IRQ_Enable (OSTM_IRQn); - - return (0); -} - -/// Enable OS Tick. -void OS_Tick_Enable (void) -{ - - if (OSTM_PendIRQ != 0U) { - OSTM_PendIRQ = 0U; - IRQ_SetPending (OSTM_IRQn); - } - - // Start the OSTM counter - OSTM.OSTMnTS = 0x01U; -} - -/// Disable OS Tick. -void OS_Tick_Disable (void) -{ - - // Stop the OSTM counter - OSTM.OSTMnTT = 0x01U; - - if (IRQ_GetPending(OSTM_IRQn) != 0) { - IRQ_ClearPending (OSTM_IRQn); - OSTM_PendIRQ = 1U; - } -} - -// Acknowledge OS Tick IRQ. -void OS_Tick_AcknowledgeIRQ (void) -{ - IRQ_ClearPending (OSTM_IRQn); -} - -// Get OS Tick IRQ number. -int32_t OS_Tick_GetIRQn (void) -{ - return (OSTM_IRQn); -} - -// Get OS Tick clock. -uint32_t OS_Tick_GetClock (void) -{ - return (OSTM_Clock); -} - -// Get OS Tick interval. -uint32_t OS_Tick_GetInterval (void) -{ - return (OSTM.OSTMnCMP + 1U); -} - -// Get OS Tick count value. -uint32_t OS_Tick_GetCount (void) -{ - uint32_t cmp = OSTM.OSTMnCMP; - return (cmp - OSTM.OSTMnCNT); -} - -// Get OS Tick overflow status. -uint32_t OS_Tick_GetOverflow (void) -{ - return (IRQ_GetPending(OSTM_IRQn)); -} -#endif - -// Get Cortex-A9 OS Timer interrupt number -IRQn_ID_t mbed_get_a9_tick_irqn(){ - return OSTM_IRQn; -} - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c deleted file mode 100644 index db8954d56d4..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** - * @file system_VK_RZ_A1H_H.c - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "VK_RZ_A1H.h" -#include "RZ_A1_Init.h" -#include "irq_ctrl.h" -#include "mbed_drv_cfg.h" - -/* - Port 0 (P0) MD pin assignment - P0_0: MD_BOOT0 - P0_1: MD_BOOT1 - P0_2: MD_CLK - P0_3: MD_CLKS - */ - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - uint32_t freq; - uint16_t ifc; - - freq = RENESAS_RZ_A1_SYS_CLK; - - /* Get CPG.FRQCR[IFC] bits */ - ifc = (CPG.FRQCR >> 8U) & 0x03U; - - /* Determine Divider 2 output clock */ - if (ifc == 0x03U) { - /* Division ratio is 1/3 */ - freq = (freq / 3U); - } else if (ifc == 0x01U) { - /* Division ratio is 2/3 */ - freq = (freq * 2U) / 3U; - } else { - /* do nothing */ - } - - SystemCoreClock = freq; -} - -/*---------------------------------------------------------------------------- - IRQ Handler Register/Unregister - *----------------------------------------------------------------------------*/ -uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) -{ - return IRQ_SetHandler(irq, handler); -} - -uint32_t InterruptHandlerUnregister (IRQn_Type irq) -{ - return IRQ_SetHandler(irq, (IRQHandler_t)NULL); -} - -/*---------------------------------------------------------------------------- - System Initialization - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -/* do not use global variables because this function is called before - reaching pre-main. RW section maybe overwritten afterwards. */ - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // Enable FPU - __FPU_Enable(); -#endif - - // Enable SRAM write access - CPG.SYSCR3 = 0x0F; - - RZ_A1_InitClock(); - RZ_A1_InitBus(); - - // Invalidate entire Unified TLB - __set_TLBIALL(0); - - // Invalidate entire branch predictor array - __set_BPIALL(0); - __DSB(); - __ISB(); - - // Invalidate instruction cache and flush branch target cache - __set_ICIALLU(0); - __DSB(); - __ISB(); - - // Invalidate data cache - L1C_InvalidateDCacheAll(); - - // Create Translation Table - MMU_CreateTranslationTable(); - - // Enable MMU - MMU_Enable(); - - // Enable Caches - L1C_EnableCaches(); - L1C_EnableBTAC(); - -#if (__L2C_PRESENT == 1) - L2C_InvAllByWay(); - // Enable L2C - L2C_Enable(); -#endif - - // IRQ Initialize - IRQ_Initialize(); -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h deleted file mode 100644 index ef8754d8730..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h +++ /dev/null @@ -1,81 +0,0 @@ -/****************************************************************************** - * @file system_VK_RZ_A1H.h - * @brief CMSIS Device System Header File for ARM Cortex-A Device Series - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_VK_RZ_A1H_H -#define __SYSTEM_VK_RZ_A1H_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */ - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/** - \brief Interrupt Handler Register. - - Registers an Interrupt Handler into the IRQ Table. - */ -extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); - -/** - \brief Interrupt Handler Unregister. - - Unregisters an Interrupt Handler from the IRQ Table. - */ -extern uint32_t InterruptHandlerUnregister(IRQn_Type); - -/** - \brief Create Translation Table. - - Creates Memory Management Unit Translation Table. - */ -extern void MMU_CreateTranslationTable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_VK_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h deleted file mode 100644 index 93cd6004b85..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_DRV_CFG_H -#define MBED_DRV_CFG_H - -/* can_api.c */ -#define CAN_TEST_GLOBAL_CH 1 - -/* gpio_api.c */ -#define GPIO_GROUP_MAX 9 - -/* pwmout_api.c */ -#define FUNC_MOTOR_CTL_PWM -#define FUMC_MTU2_PWM - -/* rtc_api.c */ -#define USE_RTCX1_CLK -//#define USE_EXTAL_CLK -//#define USE_RTCX3_CLK - -#define RENESAS_RZ_A1_P0_CLK CM0_RENESAS_RZ_A1_P0_CLK - -/* Clock Mode 0 */ -/* CLKIN is between 10MHz and 13.33MHz */ -/* Divider 1 uses 1/1 ratio, PLL x30 is ON */ -#define RENESAS_RZ_A1_SYS_CLK (CM0_RENESAS_RZ_A1_CLKIN * 30U) - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c index 3dc76da7b67..b2aa4e8c7ef 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c @@ -30,7 +30,7 @@ static volatile uint8_t wk_CPGSTBCR9; static volatile uint8_t wk_CPGSTBCR10; static volatile uint8_t wk_CPGSTBCR11; static volatile uint8_t wk_CPGSTBCR12; -#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H) +#if defined(TARGET_RZA1H) static volatile uint8_t wk_CPGSTBCR13; #endif static volatile uint8_t wk_CPGSTBREQ1; @@ -52,7 +52,7 @@ static const module_stanby_t module_stanby[] = { {&wk_CPGSTBCR7, &CPGSTBCR7, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR7_BIT_MSTP74, CPG_STBREQ2_BIT_STBRQ26}, /* Ethernet */ {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP83, CPG_STBREQ2_BIT_STBRQ27}, /* MediaLB */ {&wk_CPGSTBCR9, &CPGSTBCR9, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_BIT_MSTP91, CPG_STBREQ2_BIT_STBRQ25}, /* VDC5_0 */ -#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H) +#if defined(TARGET_RZA1H) {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP85, CPG_STBREQ2_BIT_STBRQ21}, /* IMR-LSD */ {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP86, CPG_STBREQ2_BIT_STBRQ22}, /* IMR-LS2_1 */ {&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP87, CPG_STBREQ2_BIT_STBRQ23}, /* IMR-LS2_0 */ @@ -124,7 +124,7 @@ void hal_deepsleep(void) { wk_CPGSTBCR10 = CPGSTBCR10; wk_CPGSTBCR11 = CPGSTBCR11; wk_CPGSTBCR12 = CPGSTBCR12; -#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H) +#if defined(TARGET_RZA1H) wk_CPGSTBCR13 = CPGSTBCR13; #endif @@ -165,7 +165,7 @@ void hal_deepsleep(void) { dummy_8 = CPGSTBCR11; CPGSTBCR12 = 0xFF; dummy_8 = CPGSTBCR12; -#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H) +#if defined(TARGET_RZA1H) CPGSTBCR13 = 0xFF; dummy_8 = CPGSTBCR13; #endif @@ -196,7 +196,7 @@ void hal_deepsleep(void) { dummy_8 = CPGSTBCR11; CPGSTBCR12 = wk_CPGSTBCR12; dummy_8 = CPGSTBCR12; -#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H) +#if defined(TARGET_RZA1H) CPGSTBCR13 = wk_CPGSTBCR13; dummy_8 = CPGSTBCR13; #endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp deleted file mode 100644 index 30f589511c5..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp +++ /dev/null @@ -1,273 +0,0 @@ -/* Ameba implementation of NetworkInterfaceAPI - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "mbed.h" -#include "rtos.h" - -#include "RTWInterface.h" -#include "mbed_interface.h" - -#include "rtw_emac.h" -#include "EMAC.h" -#include "wifi_constants.h" -#include "wifi_conf.h" - -#include "OnboardNetworkStack.h" -#include "EMACMemoryManager.h" -#include "osdep_service.h" - -typedef struct _wifi_scan_hdl { - _sema scan_sema; - nsapi_size_t ap_num; - nsapi_size_t scan_num; - WiFiAccessPoint *ap_details; -} wifi_scan_hdl; - -#define MAX_SCAN_TIMEOUT (15000) - -static rtw_result_t scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result ) -{ - wifi_scan_hdl *scan_handler = (wifi_scan_hdl *)malloced_scan_result->user_data; - if (malloced_scan_result->scan_complete != RTW_TRUE) { - if (scan_handler->ap_details && scan_handler->scan_num > scan_handler->ap_num) { - nsapi_wifi_ap_t ap; - rtw_scan_result_t* record = &malloced_scan_result->ap_details; - record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ - memset((void*)&ap, 0x00, sizeof(nsapi_wifi_ap_t)); - memcpy(ap.ssid, record->SSID.val, record->SSID.len); - memcpy(ap.bssid, record->BSSID.octet, 6); - switch (record->security) { - case RTW_SECURITY_OPEN: - ap.security = NSAPI_SECURITY_NONE; - break; - case RTW_SECURITY_WEP_PSK: - case RTW_SECURITY_WEP_SHARED: - ap.security = NSAPI_SECURITY_WEP; - break; - case RTW_SECURITY_WPA_TKIP_PSK: - case RTW_SECURITY_WPA_AES_PSK: - ap.security = NSAPI_SECURITY_WPA; - break; - case RTW_SECURITY_WPA2_AES_PSK: - case RTW_SECURITY_WPA2_TKIP_PSK: - case RTW_SECURITY_WPA2_MIXED_PSK: - ap.security = NSAPI_SECURITY_WPA2; - break; - case RTW_SECURITY_WPA_WPA2_MIXED: - ap.security = NSAPI_SECURITY_WPA_WPA2; - break; - default: - ap.security = NSAPI_SECURITY_UNKNOWN; - break; - } - ap.rssi = record->signal_strength; - ap.channel = record->channel; - scan_handler->ap_details[scan_handler->ap_num] = WiFiAccessPoint(ap); - } - scan_handler->ap_num++; - } else { - // scan done - rtw_up_sema(&scan_handler->scan_sema); - } - return RTW_SUCCESS; -} - -RTWInterface::RTWInterface(RTW_EMAC &get_rtw_emac, OnboardNetworkStack &get_rtw_obn_stack, bool debug) : - EMACInterface(get_rtw_emac, get_rtw_obn_stack), - rtw_emac(get_rtw_emac), - rtw_obn_stack(get_rtw_obn_stack) -{ - extern __u32 GlobalDebugEnable; - GlobalDebugEnable = debug?1:0; //Conditional statement: display debugging message - rtw_emac.power_up(); -} - -RTWInterface::~RTWInterface() -{ - rtw_emac.wlan_emac_link_change(false); - EMACInterface::disconnect(); -} - -/* - * we may call connect multiple times - */ -nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) -{ - _security = security; - // Check if ssid is empty - if (!ssid) { - return NSAPI_ERROR_PARAMETER; - } - - // Check if ssid is too long - int ssid_length = strlen(ssid); - - if (ssid_length > 0 && ssid_length <= SSID_MAX_LENGTH) { - memset(_ssid, 0, sizeof(_ssid)); - strncpy(_ssid, ssid, sizeof(_ssid)); - } else { - return NSAPI_ERROR_PARAMETER; - } - - // Check if it is an open access point - if (_security != NSAPI_SECURITY_NONE) { - // Check if passphase is empty - if (!pass) { - return NSAPI_ERROR_PARAMETER; - } - // Check if passphase too long - if (strlen(pass) >= PASSPHRASE_MIN_LENGTH && strlen(pass) <= PASSPHRASE_MAX_LENGTH ) { - memset(_pass, 0, sizeof(_pass)); - strncpy(_pass, pass, sizeof(_pass)); - } else { - return NSAPI_ERROR_PARAMETER; - } - } else { // It is an open access point - memset(_pass, 0, sizeof(_pass)); - } - return NSAPI_ERROR_OK; -} - -nsapi_error_t RTWInterface::connect() -{ - int ret; - rtw_security_t sec; - - // Check if the ssid is empty - if (strlen(_ssid) == 0) { - return NSAPI_ERROR_NO_SSID; - } - // Check the security is empty and the passphase is valid - if ((_security != NSAPI_SECURITY_NONE) && (strlen(_pass) < PASSPHRASE_MIN_LENGTH)) { - return NSAPI_ERROR_PARAMETER; - } - // Based on security type set, adapt to Ameba SDK format - switch (_security) { - case NSAPI_SECURITY_WPA: - case NSAPI_SECURITY_WPA2: - case NSAPI_SECURITY_WPA_WPA2: - sec = RTW_SECURITY_WPA_WPA2_MIXED; - break; - case NSAPI_SECURITY_WEP: - sec = RTW_SECURITY_WEP_PSK; - break; - case NSAPI_SECURITY_NONE: - sec = RTW_SECURITY_OPEN; - break; - default: - return NSAPI_ERROR_PARAMETER; - } - // Check if channel number is valid - if (_channel > 0 && _channel < 14) { - uint8_t pscan_config = PSCAN_ENABLE; - wifi_set_pscan_chan(&_channel, &pscan_config, 1); // Indicate which channel will be scanned - } - ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL); // Join a WiFi network - // Check if the WiFi is connected. Return RTW_SUCCESS for succeful; Return RTW_ERROR for error - if (ret != RTW_SUCCESS) { - if(_ssid == "NULL"){ - return NSAPI_ERROR_PARAMETER; - } - else{ - printf("failed: %d\r\n", ret); - return NSAPI_ERROR_NO_CONNECTION; - } - } - rtw_emac.wlan_emac_link_change(true); - ret = EMACInterface::connect(); - return ret; -} - -nsapi_error_t RTWInterface::scan(WiFiAccessPoint *res, unsigned count) -{ - static wifi_scan_hdl scan_handler; - scan_handler.ap_num = 0; - if (!scan_handler.scan_sema) { - rtw_init_sema(&scan_handler.scan_sema, 0); - } - scan_handler.scan_num = count; - scan_handler.ap_details = res; - if (wifi_scan_networks(scan_result_handler, (void *)&scan_handler) != RTW_SUCCESS) { - printf("wifi scan failed\n\r"); - return NSAPI_ERROR_DEVICE_ERROR; - } - if (rtw_down_timeout_sema( &scan_handler.scan_sema, MAX_SCAN_TIMEOUT ) == RTW_FALSE) { - printf("wifi scan timeout\r\n"); - return NSAPI_ERROR_DEVICE_ERROR; - } - if (count <= 0 || count > scan_handler.ap_num) { - count = scan_handler.ap_num; - } - return count; -} - -nsapi_error_t RTWInterface::set_channel(uint8_t channel) -{ - _channel = channel; - return NSAPI_ERROR_UNSUPPORTED; -} - -int8_t RTWInterface::get_rssi() -{ - int rssi = 0; - if (wifi_get_rssi(&rssi) == 0) { - return (int8_t)rssi; - } - return NSAPI_ERROR_OK; -} - -nsapi_error_t RTWInterface::connect(const char *ssid, const char *pass, - nsapi_security_t security, uint8_t channel) -{ - set_channel(channel); - int err = set_credentials(ssid, pass, security); - if(err) { - return err; - } - return connect(); -} - -nsapi_error_t RTWInterface::disconnect() -{ - char essid[33]; - - rtw_emac.wlan_emac_link_change(false); - - EMACInterface::disconnect(); - - if (wifi_is_connected_to_ap() != RTW_SUCCESS) { - return NSAPI_ERROR_NO_CONNECTION; - } - if (wifi_disconnect()<0) { - return NSAPI_ERROR_DEVICE_ERROR; - } - while(1) { - if (wext_get_ssid(WLAN0_NAME, (unsigned char *) essid) < 0) { - break; - } - } - return NSAPI_ERROR_OK; -} - -int RTWInterface::is_connected() -{ - return !wifi_is_connected_to_ap(); -} - -NetworkStack *RTWInterface::get_stack() -{ - return &rtw_obn_stack; -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h deleted file mode 100644 index 06a9328bdcd..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h +++ /dev/null @@ -1,119 +0,0 @@ -/* Ameba implementation of NetworkInterfaceAPI - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef RTW_INTERFACE_H -#define RTW_INTERFACE_H - -#include "netsocket/NetworkInterface.h" -#include "netsocket/WiFiInterface.h" -#include "nsapi.h" -#include "rtos.h" -#include "netif.h" -#include "rtw_emac.h" -#include "OnboardNetworkStack.h" -#include "EMACInterface.h" -#include "LWIPStack.h" - -// Forward declaration -class NetworkStack; - -/** Realtek Wlan (RTW) interface class - * Implementation of the NetworkStack for Ameba - */ -class RTWInterface: public WiFiInterface, public EMACInterface -{ -public: - /** RTWWlanInterface lifetime - */ - RTWInterface( - RTW_EMAC &rtw_emac = RTW_EMAC::get_instance(), - OnboardNetworkStack &rtw_lwip_stack = OnboardNetworkStack::get_default_instance(), bool debug=false); - - ~RTWInterface(); - - /** Set the WiFi network credentials - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection - * (defaults to NSAPI_SECURITY_NONE) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); - - /** Start the interface - * - * Attempts to connect to a WiFi network. - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) - * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t connect(const char *ssid, const char *pass, - nsapi_security_t security = NSAPI_SECURITY_NONE, - uint8_t channel = 0); - - /** Start the interface - * @return 0 on success, negative on failure - */ - virtual nsapi_error_t connect(); - - /** Stop the interface - * @return 0 on success, negative on failure - */ - virtual nsapi_error_t disconnect(); - virtual int is_connected(); - - /** Scan for available networks - * - * The scan will - * If the network interface is set to non-blocking mode, scan will attempt to scan - * for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback - * is attached, the callback will be called when the operation has completed. - * @param ap Pointer to allocated array to store discovered AP - * @param count Size of allocated @a res array, or 0 to only count available AP - * @param timeout Timeout in milliseconds; 0 for no timeout (Default: 0) - * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error - * see @a nsapi_error - */ - virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, unsigned count); - - virtual nsapi_error_t set_channel(uint8_t channel); - virtual int8_t get_rssi(); - - RTW_EMAC &get_emac() const { return rtw_emac; } - - virtual RTWInterface *rtwInterface() { return this; } - -protected: - /** Provide access to the underlying stack - * - * @return The underlying network stack - */ - virtual NetworkStack *get_stack(); - RTW_EMAC &rtw_emac; - OnboardNetworkStack &rtw_obn_stack; - char _ssid[256]; - char _pass[256]; - nsapi_security_t _security; - uint8_t _channel; - static const int SSID_MAX_LENGTH = 32; //The longest ssid - static const int PASSPHRASE_MAX_LENGTH = 63; //The longest passphrase - static const int PASSPHRASE_MIN_LENGTH = 8; // The shortest passphrase -}; -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/PeripheralPins.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/PeripheralPins.h deleted file mode 100644 index 5231e92aa7c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/PeripheralPins.h +++ /dev/null @@ -1,54 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "cmsis.h" -#include "pinmap.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// for spi_api.c -extern const PinMap PinMap_SSI_MOSI[]; -extern const PinMap PinMap_SSI_MISO[]; -extern const PinMap PinMap_SSI_SCLK[]; -extern const PinMap PinMap_SSI_SSEL[]; - -// for serial_api.c -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -// for pwmout_api.c -extern const PinMap PinMap_PWM[]; - -// for i2c_api.c -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -// for analogin_api.c -extern const PinMap PinMap_ADC[]; - -// for analogout_api.c -extern const PinMap PinMap_DAC[]; - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralNames.h deleted file mode 100644 index aba42a11380..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralNames.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define UART_3 3 -#define STDIO_UART_TX PB_0 -#define STDIO_UART_RX PB_1 -#define STDIO_UART UART_3 - - -typedef enum { - DAC_0 = 0, - DAC_1 -} DACName; - - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralPins.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralPins.c deleted file mode 100644 index 2e1890ea32c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PeripheralPins.c +++ /dev/null @@ -1,182 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -// for spi_api.c -const PinMap PinMap_SSI_MOSI[] = { - {PE_2, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)}, - {PC_2, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)}, - {PA_1, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)}, - {PB_6, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)}, - {PD_6, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)}, - {PG_2, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)}, - {PE_6, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)}, - {PD_2, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SSI_MISO[] = { - {PE_3, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)}, - {PC_3, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)}, - {PA_0, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)}, - {PB_7, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)}, - {PD_7, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)}, - {PG_3, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)}, - {PE_7, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)}, - {PD_3, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)}, - {NC, NC, 0} -}; - -// For testing only -const PinMap PinMap_SSI_SCLK[] = { - {PC_1, RTL_PIN_PERI(SPI0, 0, S1), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S1), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S2), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S1), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S2), /* Unused */ 0}, - - {NC, NC, 0} -}; - -// For testing only -const PinMap PinMap_SSI_SSEL[] = { - {PE_5, RTL_PIN_PERI(SPI0, 0, S2), /* Unused */ 0}, - {PC_5, RTL_PIN_PERI(SPI0, 0, S2), /* Unused */ 0}, - {PC_4, RTL_PIN_PERI(SPI0, 0, S1), /* Unused */ 0}, - {PC_0, RTL_PIN_PERI(SPI0, 0, S0), /* Unused */ 0}, - {PA_4, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PD_4, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - - {NC, NC, 0} -}; - -// for serial_api.c -const PinMap PinMap_UART_TX[] = { - {PC_3, RTL_PIN_PERI(UART0, 0, S0), RTL_PIN_FUNC(UART0, S0)}, - {PE_0, RTL_PIN_PERI(UART0, 0, S1), RTL_PIN_FUNC(UART0, S1)}, - {PA_7, RTL_PIN_PERI(UART0, 0, S2), RTL_PIN_FUNC(UART0, S2)}, - {PD_3, RTL_PIN_PERI(UART1, 1, S0), RTL_PIN_FUNC(UART1, S0)}, - {PE_4, RTL_PIN_PERI(UART1, 1, S1), RTL_PIN_FUNC(UART1, S1)}, - {PB_5, RTL_PIN_PERI(UART1, 1, S2), RTL_PIN_FUNC(UART1, S2)}, - {PA_4, RTL_PIN_PERI(UART2, 2, S0), RTL_PIN_FUNC(UART2, S0)}, - {PC_9, RTL_PIN_PERI(UART2, 2, S1), RTL_PIN_FUNC(UART2, S1)}, - {PD_7, RTL_PIN_PERI(UART2, 2, S2), RTL_PIN_FUNC(UART2, S2)}, - {PB_0, RTL_PIN_PERI(LOG_UART, 3, S0), RTL_PIN_FUNC(LOG_UART, S0)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PC_0, RTL_PIN_PERI(UART0, 0, S0), RTL_PIN_FUNC(UART0, S0)}, - {PE_3, RTL_PIN_PERI(UART0, 0, S1), RTL_PIN_FUNC(UART0, S1)}, - {PA_6, RTL_PIN_PERI(UART0, 0, S2), RTL_PIN_FUNC(UART0, S2)}, - {PD_0, RTL_PIN_PERI(UART1, 1, S0), RTL_PIN_FUNC(UART1, S0)}, - {PE_7, RTL_PIN_PERI(UART1, 1, S1), RTL_PIN_FUNC(UART1, S1)}, - {PB_4, RTL_PIN_PERI(UART1, 1, S2), RTL_PIN_FUNC(UART1, S2)}, - {PA_0, RTL_PIN_PERI(UART2, 2, S0), RTL_PIN_FUNC(UART2, S0)}, - {PC_6, RTL_PIN_PERI(UART2, 2, S1), RTL_PIN_FUNC(UART2, S1)}, - {PD_4, RTL_PIN_PERI(UART2, 2, S2), RTL_PIN_FUNC(UART2, S2)}, - {PB_1, RTL_PIN_PERI(LOG_UART, 3, S0), RTL_PIN_FUNC(LOG_UART, S0)}, - {NC, NC, 0} -}; - -// for pwmout_api.c -const PinMap PinMap_PWM[] = { - {PB_4, RTL_PIN_PERI(PWM0, 0, S0), RTL_PIN_FUNC(PWM0, S0)}, - {PB_5, RTL_PIN_PERI(PWM1, 1, S0), RTL_PIN_FUNC(PWM1, S0)}, - {PB_6, RTL_PIN_PERI(PWM2, 2, S0), RTL_PIN_FUNC(PWM2, S0)}, - {PB_7, RTL_PIN_PERI(PWM3, 3, S0), RTL_PIN_FUNC(PWM3, S0)}, - - {PC_0, RTL_PIN_PERI(PWM0, 0, S1), RTL_PIN_FUNC(PWM0, S1)}, - {PC_1, RTL_PIN_PERI(PWM1, 1, S1), RTL_PIN_FUNC(PWM1, S1)}, - {PC_2, RTL_PIN_PERI(PWM2, 2, S1), RTL_PIN_FUNC(PWM2, S1)}, - {PC_3, RTL_PIN_PERI(PWM3, 3, S1), RTL_PIN_FUNC(PWM3, S1)}, - - {PD_3, RTL_PIN_PERI(PWM0, 0, S2), RTL_PIN_FUNC(PWM0, S2)}, - {PD_4, RTL_PIN_PERI(PWM1, 1, S2), RTL_PIN_FUNC(PWM1, S2)}, - {PD_5, RTL_PIN_PERI(PWM2, 2, S2), RTL_PIN_FUNC(PWM2, S2)}, - {PD_6, RTL_PIN_PERI(PWM3, 3, S2), RTL_PIN_FUNC(PWM3, S2)}, - - {PE_0, RTL_PIN_PERI(PWM0, 0, S3), RTL_PIN_FUNC(PWM0, S3)}, - {PE_1, RTL_PIN_PERI(PWM1, 1, S3), RTL_PIN_FUNC(PWM1, S3)}, - {PE_2, RTL_PIN_PERI(PWM2, 2, S3), RTL_PIN_FUNC(PWM2, S3)}, - {PE_3, RTL_PIN_PERI(PWM3, 3, S3), RTL_PIN_FUNC(PWM3, S3)}, - - {NC, NC, 0} -}; - -// for i2c_api.c -const PinMap PinMap_I2C_SDA[] = { - {PD_4, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)}, - {PH_1, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)}, - {PC_8, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)}, - {PE_7, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)}, - - {PC_4, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)}, - {PH_3, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)}, - {PD_7, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)}, - - {PB_7, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)}, - {PE_1, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)}, - {PC_7, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)}, - - {PB_3, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)}, - {PE_3, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)}, - {PE_5, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)}, - {PD_9, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)}, - - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PD_5, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)}, - {PH_0, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)}, - {PC_9, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)}, - {PE_6, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)}, - - {PC_5, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)}, - {PH_2, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)}, - {PD_6, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)}, - - {PB_6, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)}, - {PE_0, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)}, - {PC_6, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)}, - - {PB_2, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)}, - {PE_2, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)}, - {PE_4, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)}, - {PD_8, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)}, - - {NC, NC, 0} -}; - -// For testing only -const PinMap PinMap_ADC[] = { - {A1, /* Unused */ 0, /* Unused */ 0}, - {A2, /* Unused */ 0, /* Unused */ 0}, - - {NC, NC, 0} -}; - -// For testing only -const PinMap PinMap_DAC[] = { - {DA_0, /* Unused */ 0, /* Unused */ 0}, - {DA_1, /* Unused */ 0, /* Unused */ 0}, - - {NC, NC, 0} -}; diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PinNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PinNames.h deleted file mode 100644 index 60895420ed9..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PinNames.h +++ /dev/null @@ -1,238 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _PINNAMES_H_ -#define _PINNAMES_H_ - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PORT_A = 0, - PORT_B = 1, - PORT_C = 2, - PORT_D = 3, - PORT_E = 4, - PORT_F = 5, - PORT_G = 6, - PORT_H = 7, - PORT_I = 8, - PORT_J = 9, - PORT_K = 10, - - PORT_V = 11, - PORT_U = 12, - PORT_MAX -} GPIO_PORT; - -#define RTL_PIN_PERI(FUN, IDX, SEL) ((int)(((FUN) << 8) | ((IDX)<<4) | (SEL))) -#define RTL_PIN_FUNC(FUN, SEL) ((int)(((FUN) << 7) | (SEL))) -#define RTL_GET_PERI_SEL(peri) ((int)((peri)&0x0F)) -#define RTL_GET_PERI_IDX(peri) ((int)(((peri) >> 4)&0x0F)) - -typedef enum { - PIN_INPUT=0, - PIN_OUTPUT -} PinDirection; - - -typedef enum { - PA_0 = (PORT_A<<4|0), - PA_1 = (PORT_A<<4|1), - PA_2 = (PORT_A<<4|2), - PA_3 = (PORT_A<<4|3), - PA_4 = (PORT_A<<4|4), - PA_5 = (PORT_A<<4|5), - PA_6 = (PORT_A<<4|6), - PA_7 = (PORT_A<<4|7), - - PB_0 = (PORT_B<<4|0), - PB_1 = (PORT_B<<4|1), - PB_2 = (PORT_B<<4|2), - PB_3 = (PORT_B<<4|3), - PB_4 = (PORT_B<<4|4), - PB_5 = (PORT_B<<4|5), - PB_6 = (PORT_B<<4|6), - PB_7 = (PORT_B<<4|7), - - PC_0 = (PORT_C<<4|0), - PC_1 = (PORT_C<<4|1), - PC_2 = (PORT_C<<4|2), - PC_3 = (PORT_C<<4|3), - PC_4 = (PORT_C<<4|4), - PC_5 = (PORT_C<<4|5), - PC_6 = (PORT_C<<4|6), - PC_7 = (PORT_C<<4|7), - PC_8 = (PORT_C<<4|8), - PC_9 = (PORT_C<<4|9), - - PD_0 = (PORT_D<<4|0), - PD_1 = (PORT_D<<4|1), - PD_2 = (PORT_D<<4|2), - PD_3 = (PORT_D<<4|3), - PD_4 = (PORT_D<<4|4), - PD_5 = (PORT_D<<4|5), - PD_6 = (PORT_D<<4|6), - PD_7 = (PORT_D<<4|7), - PD_8 = (PORT_D<<4|8), - PD_9 = (PORT_D<<4|9), - - PE_0 = (PORT_E<<4|0), - PE_1 = (PORT_E<<4|1), - PE_2 = (PORT_E<<4|2), - PE_3 = (PORT_E<<4|3), - PE_4 = (PORT_E<<4|4), - PE_5 = (PORT_E<<4|5), - PE_6 = (PORT_E<<4|6), - PE_7 = (PORT_E<<4|7), - PE_8 = (PORT_E<<4|8), - PE_9 = (PORT_E<<4|9), - PE_A = (PORT_E<<4|10), - - PF_0 = (PORT_F<<4|0), - PF_1 = (PORT_F<<4|1), - PF_2 = (PORT_F<<4|2), - PF_3 = (PORT_F<<4|3), - PF_4 = (PORT_F<<4|4), - PF_5 = (PORT_F<<4|5), - /* unavailable pins */ -// PF_6 = (PORT_F<<4|6), -// PF_7 = (PORT_F<<4|7), - - PG_0 = (PORT_G<<4|0), - PG_1 = (PORT_G<<4|1), - PG_2 = (PORT_G<<4|2), - PG_3 = (PORT_G<<4|3), - PG_4 = (PORT_G<<4|4), - PG_5 = (PORT_G<<4|5), - PG_6 = (PORT_G<<4|6), - PG_7 = (PORT_G<<4|7), - - PH_0 = (PORT_H<<4|0), - PH_1 = (PORT_H<<4|1), - PH_2 = (PORT_H<<4|2), - PH_3 = (PORT_H<<4|3), - PH_4 = (PORT_H<<4|4), - PH_5 = (PORT_H<<4|5), - PH_6 = (PORT_H<<4|6), - PH_7 = (PORT_H<<4|7), - - PI_0 = (PORT_I<<4|0), - PI_1 = (PORT_I<<4|1), - PI_2 = (PORT_I<<4|2), - PI_3 = (PORT_I<<4|3), - PI_4 = (PORT_I<<4|4), - PI_5 = (PORT_I<<4|5), - PI_6 = (PORT_I<<4|6), - PI_7 = (PORT_I<<4|7), - - PJ_0 = (PORT_J<<4|0), - PJ_1 = (PORT_J<<4|1), - PJ_2 = (PORT_J<<4|2), - PJ_3 = (PORT_J<<4|3), - PJ_4 = (PORT_J<<4|4), - PJ_5 = (PORT_J<<4|5), - PJ_6 = (PORT_J<<4|6), - /* unavailable pins */ -// PJ_7 = (PORT_J<<4|7), - - PK_0 = (PORT_K<<4|0), - PK_1 = (PORT_K<<4|1), - PK_2 = (PORT_K<<4|2), - PK_3 = (PORT_K<<4|3), - PK_4 = (PORT_K<<4|4), - PK_5 = (PORT_K<<4|5), - PK_6 = (PORT_K<<4|6), - /* unavailable pins */ - // PK_7 = (PORT_K<<4|7), - - AD_1 = (PORT_V<<4|1), - AD_2 = (PORT_V<<4|2), - AD_3 = (PORT_V<<4|3), - - DA_0 = (PORT_U<<4|0), - DA_1 = (PORT_U<<4|1), - - // Not connected - NC = (int)0xFFFFFFFF, - - // Generic signals namings - /* LED1~4 are defined as alias of GPIO pins, they are not the LEDs on board*/ - LED1 = PB_4, - LED2 = PB_5, - LED3 = PB_6, - LED4 = PB_7, - SERIAL_TX = PA_7, - SERIAL_RX = PA_6, - USBTX = PB_0, - USBRX = PB_1, - I2C_SCL = PC_5, - I2C_SDA = PC_4, - SPI_MOSI = PC_2, - SPI_MISO = PC_3, - SPI_SCK = PC_1, - SPI_CS = PC_0, - PWM_OUT = PD_4, - - // Arduino connector namings - - A0 = AD_2,//A0 and A1 are connected - A1 = AD_2, - A2 = AD_3, - A3 = NC, - A4 = NC, - A5 = NC, - - D0 = PA_6, - D1 = PA_7, - D2 = PA_5, - D3 = PD_4, - D4 = PD_5, - D5 = PA_4, - D6 = PA_3, - D7 = PA_2, - D8 = PB_4, - D9 = PB_5, - D10 = PC_0, - D11 = PC_2, - D12 = PC_3, - D13 = PC_1, - D14 = PB_3, - D15 = PB_2, - D16 = PA_1, - D17 = PA_0, - D18 = PE_5 - -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - OpenDrain = 3, - PullDefault = PullNone -} PinMode; - -#define PORT_NUM(pin) (((uint32_t)(pin) >> 4) & 0xF) -#define PIN_NUM(pin) ((uint32_t)(pin) & 0xF) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PortNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PortNames.h deleted file mode 100644 index 29a53243712..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/TARGET_RTL8195A/PortNames.h +++ /dev/null @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB = 1, - PortC = 2, - PortD = 3, - PortE = 4, - PortF = 5, - PortG = 6, - PortH = 7, - PortI = 8 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_api.c deleted file mode 100644 index 13ac03054c3..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_api.c +++ /dev/null @@ -1,211 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "objects.h" -#include "PinNames.h" -#include "hal_adc.h" -#include "analogin_api.h" -#include "PeripheralPins.h" - -#ifdef CONFIG_MBED_ENABLED -#include "platform_stdlib.h" -#endif - -#if CONFIG_ADC_EN -#include "pinmap.h" - - -extern u32 ConfigDebugErr; -extern u32 ConfigDebuginfo; - - -void analogin_init (analogin_t *obj, PinName pin) -{ - uint32_t adc_idx; - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_USERCB_ADPT pSalADCUserCBAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - HAL_ADC_INIT_DAT HalADCInitDataTmp; - PHAL_ADC_INIT_DAT pHalADCInitDataTmp = &HalADCInitDataTmp; - /* To backup user config first */ - -#if defined(CONFIG_MBED_ENABLED) - _memset(&(obj->HalADCInitData), 0, sizeof(HAL_ADC_INIT_DAT)); -#endif - - _memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT)); - _memset(obj, 0x00, sizeof(analogin_t)); - - ConfigDebugErr &= (~(_DBG_ADC_|_DBG_GDMA_)); - ConfigDebugInfo&= (~(_DBG_ADC_|_DBG_GDMA_)); - - adc_idx = pin & 0x0F; - - /* Get I2C device handler */ - pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); - pSalADCUserCBAdpt = (PSAL_ADC_USERCB_ADPT)&(obj->SalADCUserCBAdpt); - - /*To assign the rest pointers*/ - pSalADCMngtAdpt->pSalHndPriv = &(obj->SalADCHndPriv); - pSalADCMngtAdpt->pSalHndPriv->ppSalADCHnd = (void**)&(pSalADCMngtAdpt->pSalHndPriv); - - /* To assign the default (ROM) HAL OP initialization function */ - pSalADCMngtAdpt->pHalOpInit = &HalADCOpInit; - - /* To assign the default (ROM) HAL GDMA OP initialization function */ - pSalADCMngtAdpt->pHalGdmaOpInit = &HalGdmaOpInit; - - /* To assign the default (ROM) SAL interrupt function */ - pSalADCMngtAdpt->pSalIrqFunc = &ADCISRHandle; - - /* To assign the default (ROM) SAL DMA TX interrupt function */ - pSalADCMngtAdpt->pSalDMAIrqFunc = &ADCGDMAISRHandle; - - /* To backup user config first */ - //_memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT)); - - pSalADCMngtAdpt->pHalInitDat = &(obj->HalADCInitData); - pSalADCMngtAdpt->pHalOp = &(obj->HalADCOp); - pSalADCMngtAdpt->pIrqHnd = &(obj->ADCIrqHandleDat); - pSalADCMngtAdpt->pHalGdmaAdp = &(obj->HalADCGdmaAdpt); - pSalADCMngtAdpt->pHalGdmaOp = &(obj->HalADCGdmaOp); - pSalADCMngtAdpt->pIrqGdmaHnd = &(obj->ADCGdmaIrqHandleDat); - pSalADCMngtAdpt->pUserCB = &(obj->SalADCUserCB); - - /* Assign the private SAL handle to public SAL handle */ - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - - /* Assign the internal HAL initial data pointer to the SAL handle */ - pSalADCHND->pInitDat = pSalADCMngtAdpt->pHalInitDat; - - /* Assign the internal user callback pointer to the SAL handle */ - pSalADCHND->pUserCB = pSalADCMngtAdpt->pUserCB; - - /*To assign user callback pointers*/ - - pSalADCMngtAdpt->pUserCB->pRXCB = pSalADCUserCBAdpt; - pSalADCMngtAdpt->pUserCB->pRXCCB = (pSalADCUserCBAdpt+1); - pSalADCMngtAdpt->pUserCB->pERRCB = (pSalADCUserCBAdpt+2); - pSalADCMngtAdpt->pUserCB->pIDMARXCCB= (pSalADCUserCBAdpt+3); - pSalADCMngtAdpt->pUserCB->pDMARXCB = (pSalADCUserCBAdpt+4); - pSalADCMngtAdpt->pUserCB->pDMARXCCB = (pSalADCUserCBAdpt+5); - /* Set ADC Device Number */ - pSalADCHND->DevNum = adc_idx; - - /* Load ADC default value */ - RtkADCLoadDefault(pSalADCHND); - - /* Assign ADC Pin Mux */ - pSalADCHND->PinMux = 0; - pSalADCHND->OpType = ADC_RDREG_TYPE; - - /* Load user setting */ - if ((pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_LITTLE) || (pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_BIG)) { - pSalADCHND->pInitDat->ADCEndian = pHalADCInitDataTmp->ADCEndian; - } - - if ((pHalADCInitDataTmp->ADCAudioEn != ADC_FEATURE_DISABLED) && (pHalADCInitDataTmp->ADCAudioEn < 2)) { - pSalADCHND->pInitDat->ADCAudioEn = pHalADCInitDataTmp->ADCAudioEn; - } - - /* Init ADC now */ - pSalADCHND->pInitDat->ADCBurstSz = 8; - pSalADCHND->pInitDat->ADCOneShotTD = 8; - RtkADCInit(pSalADCHND); -} - -float analogin_read(analogin_t *obj) -{ - float value; - uint32_t AnaloginTmp[2] = {0,0}; - uint32_t AnaloginDatMsk = 0xFFFF; - uint8_t AnaloginIdx = 0; - uint32_t AnalogDat = 0; - -#if defined(CONFIG_MBED_ENABLED) - //no auto-calibration implemented yet, uses hard coded calibrate - uint32_t Offset = 0x2980; - uint32_t AnalogDatFull = 0xAA00; -#else - uint32_t AnalogDatFull = 0; -#endif - - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - AnaloginIdx = pSalADCHND->DevNum; - RtkADCReceiveBuf(pSalADCHND,&AnaloginTmp[0]); - - AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01)))); - AnalogDat = AnaloginTmp[(AnaloginIdx/2)]; - AnalogDat = (AnalogDat & AnaloginDatMsk); - AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01)))); - -#if defined(CONFIG_MBED_ENABLED) - AnalogDat -= Offset; -#else - AnalogDatFull = 0xCE80; -#endif - - value = (float)(AnalogDat) / (float)(AnalogDatFull); - return (float)value; -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint32_t AnaloginTmp[2] = {0,0}; - uint32_t AnaloginDatMsk = 0xFFFF; - uint8_t AnaloginIdx = 0; - uint32_t AnalogDat = 0; - - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - AnaloginIdx = pSalADCHND->DevNum; - RtkADCRxManualRotate(pSalADCHND,&AnaloginTmp[0]); - - AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01)))); - AnalogDat = AnaloginTmp[(AnaloginIdx/2)]; - AnalogDat = (AnalogDat & AnaloginDatMsk); - AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01)))); - - return (uint16_t)AnalogDat; -} - - -void analogin_deinit(analogin_t *obj) -{ - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - - /* To deinit analogin */ - RtkADCDeInit(pSalADCHND); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_ext.h deleted file mode 100644 index 83846aafd45..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogin_ext.h +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ANALOGIN_EXT_H -#define MBED_ANALOGIN_EXT_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern void analogin_deinit(analogin_t *obj); - -#ifdef __cplusplus -} -#endif - -#endif - - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogout_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogout_api.c deleted file mode 100644 index 0a50d63e54f..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/analogout_api.c +++ /dev/null @@ -1,197 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "objects.h" -#include "analogout_api.h" - - -#if CONFIG_DAC_EN - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include - -#define DAC_POSITIVE_FULL_SCALE 0x7E0 -#define DAC_NEGATIVE_FULL_SCALE 0x820 - -extern void HalDACPinMuxInit(void *Data); -extern void HalDACPinMuxDeInit(void *Data); - -/** \brief analogout_init:\n - * to initialize DAC - * - * This function is mainly to initialize a DAC channel. - * \para dac_t *: obj - * \para PinName: pin - */ -void analogout_init(dac_t *obj, PinName pin) -{ - uint32_t dac_idx; - uint32_t DacTemp; - PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); - dac_idx = pin & 0x0F; - - /* Assign dac index */ - pHalDacInitData->DACIdx = dac_idx; - - pHalDacInitData->DACEn = DAC_DISABLE; - pHalDacInitData->DACDataRate = DAC_DATA_RATE_250K; - pHalDacInitData->DACEndian = DAC_DATA_ENDIAN_LITTLE; - pHalDacInitData->DACBurstSz = 10; - pHalDacInitData->DACDbgSel = DAC_DBG_SEL_DISABLE; - pHalDacInitData->DACDscDbgSel = DAC_DSC_DBG_SEL_DISABLE; - pHalDacInitData->DACBPDsc = DAC_BYPASS_DSC_SEL_DISABLE; - pHalDacInitData->DACDeltaSig = 0; - pHalDacInitData->DACAnaCtrl0 = 0; - pHalDacInitData->DACAnaCtrl1 = 0; - pHalDacInitData->DACIntrMSK = DAC_FEATURE_DISABLED; - - /* DAC Function and Clock Enable*/ - HalDACPinMuxInit(pHalDacInitData); - - HalDACInit8195a(pHalDacInitData); - - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, - (BIT_DAC_FIFO_FULL_EN | - BIT_DAC_FIFO_OVERFLOW_EN | - BIT_DAC_FIFO_STOP_EN | - BIT_DAC__WRITE_ERROR_EN | - BIT_DAC_DSC_OVERFLOW0_EN | - BIT_DAC_DSC_OVERFLOW1_EN)); - DBG_DAC_INFO("INTR MSK:%x\n", HAL_DAC_READ32(pHalDacInitData->DACIdx,REG_DAC_INTR_CTRL)); - - DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1); - DacTemp |= (BIT31); - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1, DacTemp); - DBG_DAC_INFO("REG_DAC_ANAPAR_DA1:%08x\n",HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1)); - - DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL); - DacTemp |= BIT3; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL, DacTemp); - DBG_DAC_INFO("REG_DAC_CTRL:%08x\n",DacTemp); - - pHalDacInitData->DACEn = DAC_ENABLE; - HalDACEnableRtl8195a(pHalDacInitData); - osDelay(6); //hardware needs some time to get ready -} - -/** \brief analogout_free:\n - * to free DAC - * - * This function is mainly to free a DAC channel. - * \para dac_t *: obj - */ -void analogout_free(dac_t *obj) -{ - PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); - - HalDACPinMuxDeInit(pHalDacInitData); - - pHalDacInitData->DACEn = DAC_DISABLE; - HalDACEnableRtl8195a(pHalDacInitData); -} - -/** \brief analogout_write:\n - * to execute analogout_write - * - * This function is mainly to execute analog output and the value is a ratio. - * The upper/lower bound of DAC register input value is defined by - * DAC_XXXXX_FULL_SCALE. The parameter "value" of this function should be - * transfered to register value. - * - * \para dac_t * : obj - * \para float : value - */ -void analogout_write(dac_t *obj, float value) -{ - uint32_t dactemp; - uint16_t dacnegtemp; - PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); - - if (value < 0.0f) { - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, 0x00000000); - } else if (value > 1.0f) { - dactemp = (DAC_POSITIVE_FULL_SCALE<<16) | DAC_POSITIVE_FULL_SCALE; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); - } else { - if (value >= 0.5) { - dactemp = (uint32_t)((((value-0.5)/0.5) * (2^12)) * DAC_POSITIVE_FULL_SCALE); - dactemp = dactemp / (2^12); - dactemp = (dactemp<<16) | dactemp; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); - } else { - dacnegtemp = (DAC_NEGATIVE_FULL_SCALE & 0x7FF); - dacnegtemp = ((~dacnegtemp) + 1) & 0x7FF; - dactemp = (uint32_t)(((0.5-value)/0.5) * (2^12) * dacnegtemp); - dactemp = dactemp / (2^12); - dactemp = 0x1000 - dactemp; //change to 2's complement - dactemp = (dactemp<<16) | dactemp; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); - } - } -} - -/** \brief analogout_write_u16:\n - * to execute analogout_write_u16 - * - * The register value of DAC input is a format of 2's complement. - * The most maximum value of positive value drives DAC to output a voltage about 3.3V. - * The most mimimum value of negative value drives DAC to output a voltage about 0. - * And the middle value of 0x000 will drive DAC to output a voltage of half of max voltage. - * - * \para dac_t * : obj - * \para float : value - */ -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - uint32_t dactemp; - PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); - - /* To give a two point data */ - dactemp = (value << 16) | value; - HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); -} - -/** \brief analogout_read_u16:\n - * to read back analog output value in float format - * - * This function is NOT available in rtl8195a hardware design. - * It always returns a fixed value of 0.0; - * \para dac_t * : obj - */ -float analogout_read(dac_t *obj) -{ - return (float)0.0; -} - -/** \brief analogout_read_u16:\n - * to read back analog output register value - * - * This function is NOT available in rtl8195a hardware design. - * It always returns a fixed value of 0xFFFF; - * \para dac_t * : obj - */ -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)0xFFFF; -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device.h deleted file mode 100644 index b4b1b8a4121..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device.h +++ /dev/null @@ -1,22 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar deleted file mode 100644 index 6d7383f16ee..00000000000 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar and /dev/null differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar deleted file mode 100644 index 0b2a03c1dd7..00000000000 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar and /dev/null differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct deleted file mode 100644 index e76eeeb9749..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct +++ /dev/null @@ -1,78 +0,0 @@ -#! armcc -E -; Realtek Semiconductor Corp. -; -; RTL8195A ARMCC Scatter File -; -; MEMORY -; { -; SROM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00007000 -; SRAM (rwx) : ORIGIN = 0x10007000, LENGTH = 0x00070000 - 0x00007000 -; TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 -; DRAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M -; } - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IRAM 0x10007000 (0x70000 - 0x7000) { - - IMAGE2_TABLE 0x10007000 FIXED { - *rtl8195a_init*.o(.image2.ram.data*, +FIRST) - *rtl8195a_init*.o(.image2.validate.rodata*) - } - - LR_IROM1 +0 FIXED { - *(.ARM.exidx) - *(.init_array) - *rtl8195a_crypto*.o (+RO) - *(i.mbedtls*) - *libc.a (+RO) - *rtx_*.o (+RO) - *main*.o (+RO) - *lib_peripheral_mbed_arm.ar (+RO) - *_api*.o (+RO) - } - - RW_IRAM1 +0 UNINIT FIXED { - *rtl8195a_crypto*.o(+RW) - *libc.a (+RW) - *main*.o (+RW) - *lib_peripheral_mbed_arm.ar (+RW) - *_api*.o (+RW) - *rtl8195a_crypto*.o(+ZI) - *libc.a (+ZI) - *main*.o (+ZI) - *lib_peripheral_mbed_arm.ar (+ZI) - *_api*.o (+ZI) - *mbed_boot*.o (+ZI) - } - - ARM_LIB_STACK (0x10070000) EMPTY -Stack_Size { - } -} - -LR_TCM 0x1FFF0000 0x10000 { - TCM_OVERLAY 0x1FFF0000 0x10000 { - *lwip_mem*.o(+ZI) - *lwip_memp*.o(+ZI) - *.o(.tcm.heap*) - } -} - -LR_IROM1 0x30000000 0x200000 { - - ER_DRAM +0 FIXED { - .ANY (+RO) - } - - RW_DRAM1 +0 UNINIT FIXED { - .ANY (+RW) - } - - RW_DRAM2 +0 UNINIT FIXED { - .ANY (+ZI) - } -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_rom.o b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_rom.o deleted file mode 100644 index f2f242854ad..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_rom.o +++ /dev/null @@ -1,648 +0,0 @@ -## ARM Linker, RVCT3.1 [Build num]: Last Updated: Date ; -0x00000000 D __vectors_table -0x00000101 T Reset_Handler -0x00000109 T NMI_Handler -0x0000010d T HardFault_Handler -0x00000121 T MemManage_Handler -0x00000125 T BusFault_Handler -0x00000129 T UsageFault_Handler -0x00000201 T HalLogUartInit -0x00000309 T HalSerialGetcRtl8195a -0x00000329 T HalSerialGetIsrEnRegRtl8195a -0x00000335 T HalSerialSetIrqEnRegRtl8195a -0x00000341 T HalCpuClkConfig -0x00000355 T HalGetCpuClk -0x0000039d T HalRomInfo -0x000003b5 T HalGetRomInfo -0x000003c5 T HalResetVsr -0x00000899 T HalDelayUs -0x000008e1 T HalNMIHandler -0x00000911 T HalHardFaultHandler -0x00000c09 T HalMemManageHandler -0x00000c39 T HalBusFaultHandler -0x00000c69 T HalUsageFaultHandler -0x00000cfd T HalUart0PinCtrlRtl8195A -0x00000dc9 T HalUart1PinCtrlRtl8195A -0x00000e9d T HalUart2PinCtrlRtl8195A -0x00000f75 T HalSPI0PinCtrlRtl8195A -0x00001015 T HalSPI1PinCtrlRtl8195A -0x000010e5 T HalSPI2PinCtrlRtl8195A -0x000011b5 T HalSPI0MCSPinCtrlRtl8195A -0x00001275 T HalI2C0PinCtrlRtl8195A -0x00001381 T HalI2C1PinCtrlRtl8195A -0x00001459 T HalI2C2PinCtrlRtl8195A -0x00001529 T HalI2C3PinCtrlRtl8195A -0x00001639 T HalI2S0PinCtrlRtl8195A -0x0000176d T HalI2S1PinCtrlRtl8195A -0x00001845 T HalPCM0PinCtrlRtl8195A -0x00001949 T HalPCM1PinCtrlRtl8195A -0x00001a1d T HalSDIODPinCtrlRtl8195A -0x00001a6d T HalSDIOHPinCtrlRtl8195A -0x00001ab9 T HalMIIPinCtrlRtl8195A -0x00001b51 T HalWLLEDPinCtrlRtl8195A -0x00001c0d T HalWLANT0PinCtrlRtl8195A -0x00001c61 T HalWLANT1PinCtrlRtl8195A -0x00001cb5 T HalWLBTCOEXPinCtrlRtl8195A -0x00001d05 T HalWLBTCMDPinCtrlRtl8195A -0x00001d59 T HalNFCPinCtrlRtl8195A -0x00001da9 T HalPWM0PinCtrlRtl8195A -0x00001ead T HalPWM1PinCtrlRtl8195A -0x00001fb5 T HalPWM2PinCtrlRtl8195A -0x000020b1 T HalPWM3PinCtrlRtl8195A -0x000021b9 T HalETE0PinCtrlRtl8195A -0x000022c1 T HalETE1PinCtrlRtl8195A -0x000023c9 T HalETE2PinCtrlRtl8195A -0x000024d1 T HalETE3PinCtrlRtl8195A -0x000025d9 T HalEGTIMPinCtrlRtl8195A -0x00002679 T HalSPIFlashPinCtrlRtl8195A -0x00002725 T HalSDRPinCtrlRtl8195A -0x0000280d T HalJTAGPinCtrlRtl8195A -0x00002861 T HalTRACEPinCtrlRtl8195A -0x000028b9 T HalLOGUartPinCtrlRtl8195A -0x0000291d T HalLOGUartIRPinCtrlRtl8195A -0x00002981 T HalSICPinCtrlRtl8195A -0x000029d9 T HalEEPROMPinCtrlRtl8195A -0x00002a31 T HalDEBUGPinCtrlRtl8195A -0x00002b39 T HalPinCtrlRtl8195A -0x00002e5d T SpicRxCmdRtl8195A -0x00002ea5 T SpicWaitBusyDoneRtl8195A -0x00002eb5 T SpicGetFlashStatusRtl8195A -0x00002f55 T SpicWaitWipDoneRtl8195A -0x00002f6d T SpicTxCmdRtl8195A -0x00002fc1 T SpicSetFlashStatusRtl8195A -0x00003049 T SpicCmpDataForCalibrationRtl8195A -0x00003081 T SpicLoadInitParaFromClockRtl8195A -0x000030e5 T SpicInitRtl8195A -0x000031bd T SpicEraseFlashRtl8195A -0x00003279 T SpiFlashApp -0x000033b5 T HalPeripheralIntrHandle -0x00003439 T HalSysOnIntrHandle -0x00003485 T HalWdgIntrHandle -0x000034d5 T HalTimer0IntrHandle -0x00003525 T HalTimer1IntrHandle -0x00003575 T HalI2C3IntrHandle -0x000035c5 T HalTimer2To7IntrHandle -0x00003615 T HalSpi0IntrHandle -0x00003665 T HalGpioIntrHandle -0x000036b5 T HalUart0IntrHandle -0x00003705 T HalSpiFlashIntrHandle -0x00003755 T HalUsbOtgIntrHandle -0x000037a5 T HalSdioHostIntrHandle -0x000037f5 T HalI2s0OrPcm0IntrHandle -0x00003845 T HalI2s1OrPcm1IntrHandle -0x00003895 T HalWlDmaIntrHandle -0x000038e5 T HalWlProtocolIntrHandle -0x00003935 T HalCryptoIntrHandle -0x00003985 T HalGmacIntrHandle -0x000039d5 T HalGdma0Ch0IntrHandle -0x00003a25 T HalGdma0Ch1IntrHandle -0x00003a75 T HalGdma0Ch2IntrHandle; -0x00003ac5 T HalGdma0Ch3IntrHandle -0x00003b15 T HalGdma0Ch4IntrHandle -0x00003b65 T HalGdma0Ch5IntrHandle -0x00003bb5 T HalGdma1Ch0IntrHandle -0x00003c05 T HalGdma1Ch1IntrHandle -0x00003c55 T HalGdma1Ch2IntrHandle -0x00003ca5 T HalGdma1Ch3IntrHandle -0x00003cf5 T HalGdma1Ch4IntrHandle -0x00003d45 T HalGdma1Ch5IntrHandle -0x00003d95 T HalSdioDeviceIntrHandle -0x00003de5 T VectorTableInitRtl8195A -0x00004019 T VectorTableInitForOSRtl8195A -0x00004029 T VectorIrqRegisterRtl8195A -0x00004091 T VectorIrqUnRegisterRtl8195A -0x000040f1 T VectorIrqEnRtl8195A -0x0000418d T VectorIrqDisRtl8195A -0x0000422d T _UartRxDmaIrqHandle -0x00004281 T HalRuartPutCRtl8195a -0x0000429d T HalRuartGetCRtl8195a -0x000042bd T HalRuartRTSCtrlRtl8195a -0x000042e1 T HalRuartGetDebugValueRtl8195a -0x000043e1 T HalRuartGetIMRRtl8195a -0x0000442d T HalRuartSetIMRRtl8195a -0x00004465 T _UartIrqHandle -0x00004681 T HalRuartDmaInitRtl8195a -0x00004845 T HalRuartIntDisableRtl8195a -0x00004855 T HalRuartDeInitRtl8195a -0x00004985 T HalRuartIntEnableRtl8195a -0x00004995 T _UartTxDmaIrqHandle -0x000049d1 T HalRuartRegIrqRtl8195a -0x00004a4d T HalRuartAdapterLoadDefRtl8195a -0x00004add T HalRuartTxGdmaLoadDefRtl8195a -0x00004bc9 T HalRuartRxGdmaLoadDefRtl8195a -0x00004cc9 T RuartLock -0x00004ced T RuartUnLock -0x00004d09 T HalRuartIntSendRtl8195a -0x00004e35 T HalRuartDmaSendRtl8195a -0x00004f89 T HalRuartStopSendRtl8195a -0x0000504d T HalRuartIntRecvRtl8195a -0x000051ad T HalRuartDmaRecvRtl8195a -0x000052cd T HalRuartStopRecvRtl8195a -0x00005385 T RuartIsTimeout -0x000053b1 T HalRuartSendRtl8195a -0x00005599 T HalRuartRecvRtl8195a -0x00005751 T RuartResetRxFifoRtl8195a -0x00005775 T HalRuartResetRxFifoRtl8195a -0x00005829 T HalRuartInitRtl8195a -0x00005df1 T HalGdmaOnOffRtl8195a -0x00005e0d T HalGdmaChIsrEnAndDisRtl8195a -0x00005e51 T HalGdmaChEnRtl8195a -0x00005e6d T HalGdmaChDisRtl8195a -0x00005e91 T HalGdamChInitRtl8195a -0x00005ebd T HalGdmaChSetingRtl8195a -0x000060dd T HalGdmaChBlockSetingRtl8195a -0x00006419 T HalGdmaChIsrCleanRtl8195a -0x000064a1 T HalGdmaChCleanAutoSrcRtl8195a -0x00006501 T HalGdmaChCleanAutoDstRtl8195a -0x00006561 T HalEFUSEPowerSwitch8195AROM -0x000065f9 T HALEFUSEOneByteReadROM -0x00006699 T HALEFUSEOneByteWriteROM -0x0000681d T __rtl_memcmpb_v1_00 -0x00006861 T __rtl_random_v1_00 -0x00006881 T __rtl_align_to_be32_v1_00 -0x00006899 T __rtl_memsetw_v1_00 -0x000068ad T __rtl_memsetb_v1_00 -0x000068bd T __rtl_memcpyw_v1_00 -0x000068dd T __rtl_memcpyb_v1_00 -0x000068f5 T __rtl_memDump_v1_00 -0x00006901 T __rtl_AES_set_encrypt_key -0x00006c11 T __rtl_cryptoEngine_AES_set_decrypt_key -0x00006c95 T __rtl_cryptoEngine_set_security_mode_v1_00 -0x00006ea9 T __rtl_cryptoEngine_init_v1_00 -0x00007055 T __rtl_cryptoEngine_exit_v1_00 -0x000070b1 T __rtl_cryptoEngine_reset_v1_00 -0x000070ed T __rtl_cryptoEngine_v1_00 -0x00007c69 T __rtl_crypto_cipher_init_v1_00 -0x00007c89 T __rtl_crypto_cipher_encrypt_v1_00 -0x00007cad T __rtl_crypto_cipher_decrypt_v1_00 -0x00007cd5 T HalSsiPinmuxEnableRtl8195a -0x00007e45 T HalSsiEnableRtl8195a -0x00007ef9 T HalSsiDisableRtl8195a -0x00007fad T HalSsiLoadSettingRtl8195a -0x00008521 T HalSsiSetInterruptMaskRtl8195a -0x000085c9 T HalSsiGetInterruptMaskRtl8195a -0x0000863d T HalSsiSetSclkPolarityRtl8195a -0x00008715 T HalSsiSetSclkPhaseRtl8195a -0x000087e9 T HalSsiWriteRtl8195a -0x00008861 T HalSsiSetDeviceRoleRtl8195a -0x000088c9 T HalSsiSetRxFifoThresholdLevelRtl8195a -0x00008941 T HalSsiSetTxFifoThresholdLevelRtl8195a -0x000089b9 T HalSsiReadRtl8195a -0x00008a2d T HalSsiGetRxFifoLevelRtl8195a -0x00008aa5 T HalSsiGetTxFifoLevelRtl8195a -0x00008b1d T HalSsiGetStatusRtl8195a -0x00008b91 T HalSsiWriteableRtl8195a -0x00008c09 T HalSsiReadableRtl8195a -0x00008c81 T HalSsiBusyRtl8195a -0x00008cf9 T HalSsiReadInterruptRtl8195a -0x00008efd T HalSsiWriteInterruptRtl8195a -0x00009009 T HalSsiSetSlaveEnableRegisterRtl8195a -0x000090d9 T HalSsiGetInterruptStatusRtl8195a -0x0000914d T HalSsiInterruptEnableRtl8195a -0x00009299 T HalSsiInterruptDisableRtl8195a -0x000093e9 T HalSsiGetRawInterruptStatusRtl8195a -0x0000945d T HalSsiGetSlaveEnableRegisterRtl8195a -0x000094d1 T HalSsiInitRtl8195a -0x00009ba5 T _SsiReadInterrupt -0x00009db1 T _SsiWriteInterrupt -0x00009eb1 T _SsiIrqHandle -0x0000a061 T HalI2CWrite32 -0x0000a09d T HalI2CRead32 -0x0000a0dd T HalI2CDeInit8195a -0x0000a1f1 T HalI2CSendRtl8195a -0x0000a25d T HalI2CReceiveRtl8195a -0x0000a271 T HalI2CEnableRtl8195a -0x0000a389 T HalI2CIntrCtrl8195a -0x0000a3a1 T HalI2CReadRegRtl8195a -0x0000a3b1 T HalI2CWriteRegRtl8195a -0x0000a3c5 T HalI2CSetCLKRtl8195a -0x0000a6e9 T HalI2CMassSendRtl8195a -0x0000a749 T HalI2CClrIntrRtl8195a -0x0000a761 T HalI2CClrAllIntrRtl8195a -0x0000a775 T HalI2CInit8195a -0x0000aa31 T HalI2CDMACtrl8195a -0x0000aa61 T RtkI2CIoCtrl -0x0000aa65 T RtkI2CPowerCtrl -0x0000aa69 T HalI2COpInit -0x0000ac65 T I2CIsTimeout -0x0000b435 T I2CTXGDMAISRHandle -0x0000b4c1 T I2CRXGDMAISRHandle -0x0000b54d T RtkI2CIrqInit -0x0000b611 T RtkI2CIrqDeInit -0x0000b675 T RtkI2CPinMuxInit -0x0000b7c9 T RtkI2CPinMuxDeInit -0x0000b955 T RtkI2CDMAInit -0x0000bc95 T RtkI2CInit -0x0000bdad T RtkI2CDMADeInit -0x0000be4d T RtkI2CDeInit -0x0000bee5 T RtkI2CSendUserAddr -0x0000c07d T RtkI2CSend -0x0000ce51 T RtkI2CLoadDefault -0x0000cf21 T RtkSalI2COpInit -0x0000cf65 T HalI2SWrite32 -0x0000cf85 T HalI2SRead32 -0x0000cfa9 T HalI2SDeInitRtl8195a -0x0000cfc9 T HalI2STxRtl8195a -0x0000d011 T HalI2SRxRtl8195a -0x0000d05d T HalI2SEnableRtl8195a -0x0000d0b1 T HalI2SIntrCtrlRtl8195a -0x0000d0d1 T HalI2SReadRegRtl8195a -0x0000d0dd T HalI2SClrIntrRtl8195a -0x0000d0fd T HalI2SClrAllIntrRtl8195a -0x0000d11d T HalI2SInitRtl8195a -0x0000d2e5 T GPIO_GetIPPinName_8195a -0x0000d331 T GPIO_GetChipPinName_8195a -0x0000d39d T GPIO_PullCtrl_8195a -0x0000d421 T GPIO_FuncOn_8195a -0x0000d481 T GPIO_FuncOff_8195a -0x0000d4e9 T GPIO_Int_Mask_8195a -0x0000d511 T GPIO_Int_SetType_8195a -0x0000d5fd T HAL_GPIO_IrqHandler_8195a -0x0000d645 T HAL_GPIO_MbedIrqHandler_8195a -0x0000d6a1 T HAL_GPIO_UserIrqHandler_8195a -0x0000d6cd T HAL_GPIO_IntCtrl_8195a -0x0000d805 T HAL_GPIO_Init_8195a -0x0000dac1 T HAL_GPIO_DeInit_8195a -0x0000dbd1 T HAL_GPIO_ReadPin_8195a -0x0000dc91 T HAL_GPIO_WritePin_8195a -0x0000ddad T HAL_GPIO_RegIrq_8195a -0x0000ddf5 T HAL_GPIO_UnRegIrq_8195a -0x0000de15 T HAL_GPIO_UserRegIrq_8195a -0x0000def9 T HAL_GPIO_UserUnRegIrq_8195a -0x0000dfc1 T HAL_GPIO_MaskIrq_8195a -0x0000e061 T HAL_GPIO_UnMaskIrq_8195a -0x0000e101 T HAL_GPIO_IntDebounce_8195a -0x0000e1c1 T HAL_GPIO_GetIPPinName_8195a -0x0000e1c9 T HAL_GPIO_PullCtrl_8195a -0x0000e259 T DumpForOneBytes -0x0000e419 T CmdRomHelp -0x0000e491 T CmdWriteWord -0x0000e505 T CmdDumpHelfWord -0x0000e5f1 T CmdDumpWord -0x0000e6f5 T CmdDumpByte -0x0000e751 T CmdSpiFlashTool -0x0000e7a9 T GetRomCmdNum -0x0000e7ad T CmdWriteByte -0x0000e7ed T Isspace -0x0000e801 T Strtoul -0x0000e8b1 T ArrayInitialize -0x0000e8c9 T GetArgc -0x0000e8f9 T GetArgv -0x0000e95d T UartLogCmdExecute -0x0000e9fd T UartLogShowBackSpace -0x0000ea39 T UartLogRecallOldCmd -0x0000ea71 T UartLogHistoryCmd -0x0000eadd T UartLogCmdChk -0x0000ebf5 T UartLogIrqHandle -0x0000ecc5 T RtlConsolInit -0x0000ed49 T RtlConsolTaskRom -0x0000ed79 T RtlExitConsol -0x0000edcd T RtlConsolRom -0x0000ee0d T HalTimerOpInit -0x0000ee59 T HalTimerIrq2To7Handle -0x0000ef09 T HalGetTimerIdRtl8195a -0x0000ef3d T HalTimerInitRtl8195a -0x0000f069 T HalTimerDisRtl8195a -0x0000f089 T HalTimerEnRtl8195a -0x0000f0a9 T HalTimerReadCountRtl8195a -0x0000f0bd T HalTimerIrqClearRtl8195a -0x0000f0d1 T HalTimerDumpRegRtl8195a -0x0000f129 T VSprintf -0x0000f39d T DiagPrintf -0x0000f3b9 T DiagSPrintf -0x0000f3d1 T DiagSnPrintf -0x0000f3ed T prvDiagPrintf -0x0000f40d T prvDiagSPrintf -0x0000f429 T _memcmp -0x0000f465 T _memcpy -#0x0000f511 T _memset -0x0000f585 T Rand -0x0000f60d T _strncpy -0x0000f629 T _strcpy -0x0000f639 T prvStrCpy -0x0000f651 T _strlen -0x0000f669 T _strnlen -0x0000f699 T prvStrLen -0x0000f6b1 T _strcmp -0x0000f6d1 T _strncmp -0x0000f719 T prvStrCmp -0x0000f749 T StrUpr -0x0000f769 T prvAtoi -0x0000f7bd T prvStrStr -0x0000f7d5 T _strsep -0x0000f815 T skip_spaces -0x0000f831 T skip_atoi -0x0000f869 T _parse_integer_fixup_radix -0x0000f8bd T _parse_integer -0x0000f915 T simple_strtoull -0x0000f945 T simple_strtoll -0x0000f965 T simple_strtoul -0x0000f96d T simple_strtol -0x0000f985 T _vsscanf -0x0000ff71 T _sscanf -0x0000ff91 T div_u64 -0x0000ff99 T div_s64 -0x0000ffa1 T div_u64_rem -0x0000ffb1 T div_s64_rem -0x0000ffc1 T _strpbrk -0x0000ffed T _strchr -0x00010005 T aes_set_key -0x000103d1 T aes_encrypt -0x000114a5 T aes_decrypt -0x000125c9 T AES_WRAP -0x00012701 T AES_UnWRAP -0x00012861 T crc32_get -0x00012895 T arc4_byte -0x000128bd T rt_arc4_init -0x00012901 T rt_arc4_crypt -0x000131c1 T rt_md5_init -0x000131f5 T rt_md5_append -0x0001327d T rt_md5_final -0x000132d5 T rt_md5_hmac -0x00013449 T rtw_get_bit_value_from_ieee_value -0x00013475 T rtw_is_cckrates_included -0x000134b5 T rtw_is_cckratesonly_included -0x000134dd T rtw_check_network_type -0x0001350d T rtw_set_fixed_ie -0x0001352d T rtw_set_ie -0x0001355d T rtw_get_ie -0x00013591 T rtw_set_supported_rate -0x00013611 T rtw_get_rateset_len -0x0001362d T rtw_get_wpa_ie -0x000136c9 T rtw_get_wpa2_ie -0x00013701 T rtw_get_wpa_cipher_suite -0x00013769 T rtw_get_wpa2_cipher_suite -0x000137d1 T rtw_parse_wpa_ie -0x000138ad T rtw_parse_wpa2_ie -0x00013965 T rtw_get_sec_ie -0x00013a15 T rtw_get_wps_ie -0x00013a99 T rtw_get_wps_attr -0x00013b49 T rtw_get_wps_attr_content -0x00013b91 T rtw_ieee802_11_parse_elems -0x00013d9d T str_2char2num -0x00013db9 T key_2char2num -0x00013dd1 T convert_ip_addr -0x00013e9d T rom_psk_PasswordHash -0x00013ed5 T rom_psk_CalcGTK -0x00013f69 T rom_psk_CalcPTK -0x00014295 T wep_80211_encrypt -0x000142f5 T wep_80211_decrypt -0x00014389 T tkip_micappendbyte -0x000143d9 T rtw_secmicsetkey -0x00014419 T rtw_secmicappend -0x00014435 T rtw_secgetmic -0x0001449d T rtw_seccalctkipmic -0x000145a5 T tkip_phase1 -0x00014725 T tkip_phase2 -0x00014941 T tkip_80211_encrypt -0x000149d5 T tkip_80211_decrypt -0x00014a8d T aes1_encrypt -0x00014c65 T aesccmp_construct_mic_iv -0x00014ccd T aesccmp_construct_mic_header1 -0x00014d21 T aesccmp_construct_mic_header2 -0x00014db5 T aesccmp_construct_ctr_preload -0x00014e29 T aes_80211_encrypt -0x000151ad T aes_80211_decrypt -0x000155b9 T _sha1_process_message_block -0x00015749 T _sha1_pad_message -0x000157e5 T rt_sha1_init -0x00015831 T rt_sha1_update -0x000158a9 T rt_sha1_finish -0x00015909 T rt_hmac_sha1 -0x00015a65 T rom_aes_128_cbc_encrypt -0x00015ae1 T rom_aes_128_cbc_decrypt -0x00015b5d T rom_rijndaelKeySetupEnc -0x00015c39 T rom_aes_decrypt_init -0x00015d15 T rom_aes_internal_decrypt -0x00016071 T rom_aes_decrypt_deinit -0x00016085 T rom_aes_encrypt_init -0x0001609d T rom_aes_internal_encrypt -0x00016451 T rom_aes_encrypt_deinit -0x00017b35 T bignum_init -0x00017b61 T bignum_deinit -0x00017b81 T bignum_get_unsigned_bin_len -0x00017b85 T bignum_get_unsigned_bin -0x00017c21 T bignum_set_unsigned_bi -0x00017cd1 T bignum_cmp -0x00017cd5 T bignum_cmp_d -0x00017cfd T bignum_add -0x00017d0d T bignum_sub -0x00017d1d T bignum_mul -0x00017d2d T bignum_exptmod -0x00017d51 T WPS_realloc -0x00017d99 T os_zalloc -0x00017dc1 T rom_hmac_sha256_vector -0x00017ebd T rom_hmac_sha256 -0x00018009 T rom_sha256_vector -0x00018221 T phy_CalculateBitShift -0x00018239 T PHY_SetBBReg_8195A -0x00018279 T PHY_QueryBBReg_8195A -0x0001829d T ROM_odm_QueryRxPwrPercentage -0x000182bd T ROM_odm_EVMdbToPercentage -0x000182e5 T ROM_odm_SignalScaleMapping_8195A -0x000183cd T ROM_odm_FalseAlarmCounterStatistics -0x00018721 T ROM_odm_SetEDCCAThreshold -0x00018749 T ROM_odm_SetTRxMux -0x00018771 T ROM_odm_SetCrystalCap -0x000187d5 T ROM_odm_GetDefaultCrytaltalCap -0x000187e9 T ROM_ODM_CfoTrackingReset -0x00018811 T ROM_odm_CfoTrackingFlow -0x0001965d T curve25519_donna -0x0001a391 T aes_test_alignment_detection -0x0001a3ed T aes_mode_reset -0x0001a3f9 T aes_ecb_encrypt -0x0001a431 T aes_ecb_decrypt -0x0001a469 T aes_cbc_encrypt -0x0001a579 T aes_cbc_decrypt -0x0001a701 T aes_cfb_encrypt -0x0001a9e5 T aes_cfb_decrypt -0x0001acc9 T aes_ofb_crypt -0x0001af7d T aes_ctr_crypt -0x0001b289 T aes_encrypt_key128 -0x0001b2a5 T aes_encrypt_key192 -0x0001b2c1 T aes_encrypt_key256 -0x0001b2e1 T aes_encrypt_key -0x0001b351 T aes_decrypt_key128 -0x0001b36d T aes_decrypt_key192 -0x0001b389 T aes_decrypt_key256 -0x0001b3a9 T aes_decrypt_key -0x0001b419 T aes_init -0x0001b41d T CRYPTO_chacha_20 -0x0001bc25 T CRYPTO_poly1305_init -0x0001bd09 T CRYPTO_poly1305_update -0x0001bd8d T CRYPTO_poly1305_finish -0x0001ceb5 T rom_sha512_starts -0x0001d009 T rom_sha512_update -0x0001d011 T rom_sha512_finish -0x0001d261 T rom_sha512 -0x0001d299 T rom_sha512_hmac_starts -0x0001d35d T rom_sha512_hmac_update -0x0001d365 T rom_sha512_hmac_finish -0x0001d3b5 T rom_sha512_hmac_reset -0x0001d3d1 T rom_sha512_hmac -0x0001d40d T rom_sha512_hkdf -0x0001d501 T rom_ed25519_gen_keypair -0x0001d505 T rom_ed25519_gen_signature -0x0001d51d T rom_ed25519_verify_signature -0x0001d521 T rom_ed25519_crypto_sign_seed_keypair -0x0001d579 T rom_ed25519_crypto_sign_detached -0x0001d655 T rom_ed25519_crypto_sign_verify_detached -0x0001f86d T rom_ed25519_ge_double_scalarmult_vartime -0x0001fc35 T rom_ed25519_ge_frombytes_negate_vartime -0x000207d5 T rom_ed25519_ge_p3_tobytes -0x00020821 T rom_ed25519_ge_scalarmult_base -0x000209e1 T rom_ed25519_ge_tobytes -0x00020a2d T rom_ed25519_sc_muladd -0x0002603d T rom_ed25519_sc_reduce -0x00028a4d T __rtl_memchr_v1_00 -0x00028ae1 T __rtl_memcmp_v1_00 -0x00028b49 T __rtl_memcpy_v1_00 -0x00028bed T __rtl_memmove_v1_00 -0x00028cb5 T __rtl_memset_v1_00 -0x00028d49 T __rtl_strcat_v1_00 -0x00028d91 T __rtl_strchr_v1_00 -0x00028e55 T __rtl_strcmp_v1_00 -0x00028ec9 T __rtl_strcpy_v1_00 -0x00028f15 T __rtl_strlen_v1_00 -0x00028f69 T __rtl_strncat_v1_00 -0x00028fc5 T __rtl_strncmp_v1_00 -0x0002907d T __rtl_strncpy_v1_00 -0x000293cd T __rtl_strstr_v1_00 -0x0002960d T __rtl_strsep_v1_00 -0x00029619 T __rtl_strtok_v1_00 -0x0002962d T __rtl__strtok_r_v1_00 -0x00029691 T __rtl_strtok_r_v1_00 -0x00029699 T __rtl_close_v1_00 -0x000296ad T __rtl_fstat_v1_00 -0x000296c1 T __rtl_isatty_v1_00 -0x000296d5 T __rtl_lseek_v1_00 -0x000296e9 T __rtl_open_v1_00 -0x000296fd T __rtl_read_v1_00 -0x00029711 T __rtl_write_v1_00 -0x00029725 T __rtl_sbrk_v1_00 -0x000297bd T __rtl_ltoa_v1_00 -0x00029855 T __rtl_ultoa_v1_00 -0x000298c5 T __rtl_dtoi_v1_00 -0x00029945 T __rtl_dtoi64_v1_00 -0x000299dd T __rtl_dtoui_v1_00 -0x000299e5 T __rtl_ftol_v1_00 -0x00029a51 T __rtl_itof_v1_00 -0x00029ae9 T __rtl_itod_v1_00 -0x00029b79 T __rtl_i64tod_v1_00 -0x00029c55 T __rtl_uitod_v1_00 -0x00029d2d T __rtl_ftod_v1_00 -0x00029de9 T __rtl_dtof_v1_00 -0x00029e89 T __rtl_uitof_v1_00 -0x00029f65 T __rtl_fadd_v1_00 -0x0002a261 T __rtl_fsub_v1_00 -0x0002a559 T __rtl_fmul_v1_00 -0x0002a695 T __rtl_fdiv_v1_00 -0x0002a825 T __rtl_dadd_v1_00 -0x0002aed9 T __rtl_dsub_v1_00 -0x0002b555 T __rtl_dmul_v1_00 -0x0002b8ad T __rtl_ddiv_v1_00 -0x0002be4d T __rtl_dcmpeq_v1_00 -0x0002bebd T __rtl_dcmplt_v1_00 -0x0002bf51 T __rtl_dcmpgt_v1_00 -0x0002c049 T __rtl_dcmple_v1_00 -0x0002c139 T __rtl_fcmplt_v1_00 -0x0002c195 T __rtl_fcmpgt_v1_00 -0x0002c229 T __rtl_cos_f32_v1_00 -0x0002c435 T __rtl_sin_f32_v1_00 -0x0002c639 T __rtl_fabs_v1_00 -0x0002c641 T __rtl_fabsf_v1_00 -0x0002c77d T __rtl_dtoa_r_v1_00 -0x0002d7d1 T __rom_mallocr_init_v1_00 -0x0002d841 T __rtl_free_r_v1_00 -0x0002da31 T __rtl_malloc_r_v1_00 -0x0002df55 T __rtl_realloc_r_v1_00 -0x0002e331 T __rtl_memalign_r_v1_00 -0x0002e421 T __rtl_valloc_r_v1_00 -0x0002e42d T __rtl_pvalloc_r_v1_00 -0x0002e441 T __rtl_calloc_r_v1_00 -0x0002e4a9 T __rtl_cfree_r_v1_00 -0x0002e515 T __rtl_Balloc_v1_00 -0x0002e571 T __rtl_Bfree_v1_00 -0x0002e585 T __rtl_i2b_v1_00 -0x0002e599 T __rtl_multadd_v1_00 -0x0002e629 T __rtl_mult_v1_00 -0x0002e769 T __rtl_pow5mult_v1_00 -0x0002e809 T __rtl_hi0bits_v1_00 -0x0002e845 T __rtl_d2b_v1_00 -0x0002e901 T __rtl_lshift_v1_00 -0x0002e9bd T __rtl_cmp_v1_00 -0x0002ea01 T __rtl_diff_v1_00 -0x0002eae9 T __rtl_sread_v1_00 -0x0002eb39 T __rtl_seofread_v1_00 -0x0002eb3d T __rtl_swrite_v1_00 -0x0002ebc1 T __rtl_sseek_v1_00 -0x0002ec11 T __rtl_sclose_v1_00 -0x0002ec41 T __rtl_sbrk_r_v1_00 -0x0002ef8d T __rtl_fflush_r_v1_00 -0x0002f661 T __rtl_vfprintf_r_v1_00 -0x00030c15 T __rtl_fpclassifyd -0x00030c68 D CpkClkTbl -0x00030c80 D ROM_IMG1_VALID_PATTEN -0x00030c88 D SpicCalibrationPattern -0x00030c98 D SpicInitCPUCLK -0x00030ca8 D BAUDRATE -0x00030d1c D OVSR -0x00030d90 D DIV -0x00030e04 D OVSR_ADJ -0x00030e78 D __AES_rcon -0x00030ea0 D __AES_Te4 -0x000312a0 D I2CDmaChNo -0x000316a0 D UartLogRomCmdTable -0x00031700 D _HalRuartOp -0x00031760 D _HalGdmaOp -0x0003540c D RTW_WPA_OUI_TYPE -0x00035410 D WPA_CIPHER_SUITE_NONE -0x00035414 D WPA_CIPHER_SUITE_WEP40 -0x00035418 D WPA_CIPHER_SUITE_TKIP -0x0003541c D WPA_CIPHER_SUITE_CCMP -0x00035420 D WPA_CIPHER_SUITE_WEP104 -0x00035424 D RSN_CIPHER_SUITE_NONE -0x00035428 D RSN_CIPHER_SUITE_WEP40 -0x0003542c D RSN_CIPHER_SUITE_TKIP -0x00035430 D RSN_CIPHER_SUITE_CCMP -0x00035434 D RSN_CIPHER_SUITE_WEP104 -0x00035444 D RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X -0x00035448 D RSN_AUTH_KEY_MGMT_UNSPEC_802_1X -0x0003544c D RSN_VERSION_BSD -0x00035988 D rom_wps_Te0 -0x00035d88 D rom_wps_rcons -0x00035d94 D rom_wps_Td4s -0x00035e94 D rom_wps_Td0 -0x10000000 D NewVectorTable -0x10000100 D UserIrqFunTable -0x10000200 D UserIrqDataTable -0x10000300 D __rom_bss_start__ -0x10000300 D CfgSysDebugWarn -0x10000304 D CfgSysDebugInfo -0x10000308 D CfgSysDebugErr -0x1000030c D ConfigDebugWarn -0x10000310 D ConfigDebugInfo -0x10000314 D ConfigDebugErr -0x10000318 D HalTimerOp -0x10000334 D GPIOState -0x1000034c D gTimerRecord -0x10000350 D SSI_DBG_CONFIG -0x10000354 D _pHAL_Gpio_Adapter -0x10000358 D Timer2To7VectorTable -#0x10000384 D pUartLogCtl -#0x10000388 D UartLogBuf -#0x10000408 D UartLogCtl -#0x10000430 D UartLogHistoryBuf -#0x100006ac D ArgvArray -0x100006d4 D rom_wlan_ram_map -0x100006e0 D FalseAlmCnt -0x10000720 D ROMInfo -0x10000738 D DM_CfoTrack -0x10000760 D rom_libgloss_ram_map -0x10000bc4 D __rtl_errno -0x10000bc8 D __ram_table_start__ -0x10000bc8 D __rom_bss_end__ -0x10001c60 D _rtl_impure_ptr -0X10006000 D __image2_entry_func__ -0x10006000 D __image2_start__ -0x30000000 D __image3_start__ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S deleted file mode 100644 index c184bdff725..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S +++ /dev/null @@ -1,31 +0,0 @@ -; -; Copyright (c) 2017 Realtek Semiconductor Corp. -; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; http://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - - PRESERVE8 - THUMB - - AREA |i.PLAT_Start|, CODE, READONLY - -PLAT_Start PROC - - EXPORT PLAT_Start - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - IMPORT PLAT_Init - LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - LDR R0, =PLAT_Init - BX R0 - ENDP - ALIGN - END diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a deleted file mode 100644 index 7b2963eb356..00000000000 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a and /dev/null differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a deleted file mode 100644 index bcd22c48804..00000000000 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a and /dev/null differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld deleted file mode 100644 index 01d4ce1969c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -INCLUDE "rtl8195a_rom.h" -/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader). - But we can put .data/.bss of Image2 in this region */ -MEMORY -{ - TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 - DATA_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100 - SRAM1 (rwx) : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000 - SRAM2 (rwx) : ORIGIN = 0x30000000, LENGTH = 2M -} - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* Stack sizes: */ -StackSize = MBED_BOOT_STACK_SIZE; - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .image2.table : - { - KEEP(*(SORT(.image2.ram.data*))) - KEEP(*(.image2.validate.rodata*)) - } > SRAM2 - - .text.sram1 : - { - . = ALIGN(8); - *rtl8195a_crypto*.o (.text* .rodata*) - *mbedtls*.o (.text* .rodata*) - *libc.a: (.text* .rodata*) - *lib_peripheral_mbed_gcc.a: (.text* .rodata*) - *_api*.o (.text* .rodata*) - *main*.o (.text* .rodata*) - } > SRAM1 - - .text.sram2 : - { - . = ALIGN(8); - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > SRAM2 - __etext = .; - - .data.sram1 : - { - . = ALIGN(4); - __data_start__ = .; - __sram_data_start__ = .; - *rtl8195a_crypto*.o (.data*) - *mbedtls*.o (.data*) - __data_end__ = .; - __sram_data_end__ = .; - } > SRAM1 - - .data.sram2 : - { - __dram_data_start__ = .; - *(vtable) - *(.data*) - *(.sdram.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - __dram_data_end__ = .; - } > SRAM2 - __image2_end__ = .; - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > SRAM2 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > SRAM2 - __exidx_end = .; - - .bss.sram1 (NOLOAD) : - { - __bss_start__ = .; - __bss_sram_start__ = .; - *rtl8195a_crypto*.o (.bss* COMMON) - *mbedtls*.o (.bss* COMMON) - *(.bss.thread_stack_main) - *lib_peripheral_mbed_gcc.a: (.bss* COMMON) - *mbed_boot*.o (.bss* COMMON) - __bss_sram_end__ = .; - __bss_end__ = .; - } > SRAM1 - - .bss.sram2 (NOLOAD) : - { - __bss_dram_start__ = .; - *(.bss*) - *(COMMON) - *(.bdsram.data*) - __bss_dram_end__ = .; - } > SRAM2 - - .bf_data : - { - __buffer_data_start__ = .; - *(.bfsram.data*) - __buffer_data_end__ = .; - } > SRAM2 - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize; - __HeapLimit = .; - } > SRAM1 - - .TCM_overlay (NOLOAD): - { - __bss_dtcm_start__ = .; - *lwip_mem*.o (.bss* COMMON) - *lwip_memp*.o (.bss* COMMON) - *(.tcm.heap*) - __bss_dtcm_end__ = .; - } > TCM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - __StackLimit = .; - *(.stack) - . += StackSize - (. - __StackLimit); - } > SRAM1 - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1); - __StackLimit = __StackTop - StackSize; - PROVIDE(__stack = __StackTop); - - /* Check if reserved stack size is too small */ - ASSERT(StackSize >= SIZEOF(.stack_dummy), "reserved stack size is too small") - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit") -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_rom.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_rom.h deleted file mode 100644 index e9a2754ff8e..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_rom.h +++ /dev/null @@ -1,759 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -SECTIONS -{ - __vectors_table = 0x0; - Reset_Handler = 0x101; - NMI_Handler = 0x109; - HardFault_Handler = 0x10d; - MemManage_Handler = 0x121; - BusFault_Handler = 0x125; - UsageFault_Handler = 0x129; - HalLogUartInit = 0x201; - HalSerialPutcRtl8195a = 0x2d9; - HalSerialGetcRtl8195a = 0x309; - HalSerialGetIsrEnRegRtl8195a = 0x329; - HalSerialSetIrqEnRegRtl8195a = 0x335; - HalCpuClkConfig = 0x341; - HalGetCpuClk = 0x355; - HalRomInfo = 0x39d; - HalGetRomInfo = 0x3b5; - HalResetVsr = 0x3c5; - HalDelayUs = 0x899; - HalNMIHandler = 0x8e1; - HalHardFaultHandler = 0x911; - HalMemManageHandler = 0xc09; - HalBusFaultHandler = 0xc39; - HalUsageFaultHandler = 0xc69; - HalUart0PinCtrlRtl8195A = 0xcfd; - HalUart1PinCtrlRtl8195A = 0xdc9; - HalUart2PinCtrlRtl8195A = 0xe9d; - HalSPI0PinCtrlRtl8195A = 0xf75; - HalSPI1PinCtrlRtl8195A = 0x1015; - HalSPI2PinCtrlRtl8195A = 0x10e5; - HalSPI0MCSPinCtrlRtl8195A = 0x11b5; - HalI2C0PinCtrlRtl8195A = 0x1275; - HalI2C1PinCtrlRtl8195A = 0x1381; - HalI2C2PinCtrlRtl8195A = 0x1459; - HalI2C3PinCtrlRtl8195A = 0x1529; - HalI2S0PinCtrlRtl8195A = 0x1639; - HalI2S1PinCtrlRtl8195A = 0x176d; - HalPCM0PinCtrlRtl8195A = 0x1845; - HalPCM1PinCtrlRtl8195A = 0x1949; - HalSDIODPinCtrlRtl8195A = 0x1a1d; - HalSDIOHPinCtrlRtl8195A = 0x1a6d; - HalMIIPinCtrlRtl8195A = 0x1ab9; - HalWLLEDPinCtrlRtl8195A = 0x1b51; - HalWLANT0PinCtrlRtl8195A = 0x1c0d; - HalWLANT1PinCtrlRtl8195A = 0x1c61; - HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5; - HalWLBTCMDPinCtrlRtl8195A = 0x1d05; - HalNFCPinCtrlRtl8195A = 0x1d59; - HalPWM0PinCtrlRtl8195A = 0x1da9; - HalPWM1PinCtrlRtl8195A = 0x1ead; - HalPWM2PinCtrlRtl8195A = 0x1fb5; - HalPWM3PinCtrlRtl8195A = 0x20b1; - HalETE0PinCtrlRtl8195A = 0x21b9; - HalETE1PinCtrlRtl8195A = 0x22c1; - HalETE2PinCtrlRtl8195A = 0x23c9; - HalETE3PinCtrlRtl8195A = 0x24d1; - HalEGTIMPinCtrlRtl8195A = 0x25d9; - HalSPIFlashPinCtrlRtl8195A = 0x2679; - HalSDRPinCtrlRtl8195A = 0x2725; - HalJTAGPinCtrlRtl8195A = 0x280d; - HalTRACEPinCtrlRtl8195A = 0x2861; - HalLOGUartPinCtrlRtl8195A = 0x28b9; - HalLOGUartIRPinCtrlRtl8195A = 0x291d; - HalSICPinCtrlRtl8195A = 0x2981; - HalEEPROMPinCtrlRtl8195A = 0x29d9; - HalDEBUGPinCtrlRtl8195A = 0x2a31; - HalPinCtrlRtl8195A = 0x2b39; - SpicRxCmdRtl8195A = 0x2e5d; - SpicWaitBusyDoneRtl8195A = 0x2ea5; - SpicGetFlashStatusRtl8195A = 0x2eb5; - SpicWaitWipDoneRtl8195A = 0x2f55; - SpicTxCmdRtl8195A = 0x2f6d; - SpicSetFlashStatusRtl8195A = 0x2fc1; - SpicCmpDataForCalibrationRtl8195A = 0x3049; - SpicLoadInitParaFromClockRtl8195A = 0x3081; - SpicInitRtl8195A = 0x30e5; - SpicEraseFlashRtl8195A = 0x31bd; - SpiFlashApp = 0x3279; - HalPeripheralIntrHandle = 0x33b5; - HalSysOnIntrHandle = 0x3439; - HalWdgIntrHandle = 0x3485; - HalTimer0IntrHandle = 0x34d5; - HalTimer1IntrHandle = 0x3525; - HalI2C3IntrHandle = 0x3575; - HalTimer2To7IntrHandle = 0x35c5; - HalSpi0IntrHandle = 0x3615; - HalGpioIntrHandle = 0x3665; - HalUart0IntrHandle = 0x36b5; - HalSpiFlashIntrHandle = 0x3705; - HalUsbOtgIntrHandle = 0x3755; - HalSdioHostIntrHandle = 0x37a5; - HalI2s0OrPcm0IntrHandle = 0x37f5; - HalI2s1OrPcm1IntrHandle = 0x3845; - HalWlDmaIntrHandle = 0x3895; - HalWlProtocolIntrHandle = 0x38e5; - HalCryptoIntrHandle = 0x3935; - HalGmacIntrHandle = 0x3985; - HalGdma0Ch0IntrHandle = 0x39d5; - HalGdma0Ch1IntrHandle = 0x3a25; - HalGdma0Ch2IntrHandle = 0x3a75; - HalGdma0Ch3IntrHandle = 0x3ac5; - HalGdma0Ch4IntrHandle = 0x3b15; - HalGdma0Ch5IntrHandle = 0x3b65; - HalGdma1Ch0IntrHandle = 0x3bb5; - HalGdma1Ch1IntrHandle = 0x3c05; - HalGdma1Ch2IntrHandle = 0x3c55; - HalGdma1Ch3IntrHandle = 0x3ca5; - HalGdma1Ch4IntrHandle = 0x3cf5; - HalGdma1Ch5IntrHandle = 0x3d45; - HalSdioDeviceIntrHandle = 0x3d95; - VectorTableInitRtl8195A = 0x3de5; - VectorTableInitForOSRtl8195A = 0x4019; - VectorIrqRegisterRtl8195A = 0x4029; - VectorIrqUnRegisterRtl8195A = 0x4091; - VectorIrqEnRtl8195A = 0x40f1; - VectorIrqDisRtl8195A = 0x418d; - _UartRxDmaIrqHandle = 0x422d; - HalRuartPutCRtl8195a = 0x4281; - HalRuartGetCRtl8195a = 0x429d; - HalRuartRTSCtrlRtl8195a = 0x42bd; - HalRuartGetDebugValueRtl8195a = 0x42e1; - HalRuartGetIMRRtl8195a = 0x43e1; - HalRuartSetIMRRtl8195a = 0x442d; - _UartIrqHandle = 0x4465; - HalRuartDmaInitRtl8195a = 0x4681; - HalRuartIntDisableRtl8195a = 0x4845; - HalRuartDeInitRtl8195a = 0x4855; - HalRuartIntEnableRtl8195a = 0x4985; - _UartTxDmaIrqHandle = 0x4995; - HalRuartRegIrqRtl8195a = 0x49d1; - HalRuartAdapterLoadDefRtl8195a = 0x4a4d; - HalRuartTxGdmaLoadDefRtl8195a = 0x4add; - HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9; - RuartLock = 0x4cc9; - RuartUnLock = 0x4ced; - HalRuartIntSendRtl8195a = 0x4d09; - HalRuartDmaSendRtl8195a = 0x4e35; - HalRuartStopSendRtl8195a = 0x4f89; - HalRuartIntRecvRtl8195a = 0x504d; - HalRuartDmaRecvRtl8195a = 0x51ad; - HalRuartStopRecvRtl8195a = 0x52cd; - RuartIsTimeout = 0x5385; - HalRuartSendRtl8195a = 0x53b1; - HalRuartRecvRtl8195a = 0x5599; - RuartResetRxFifoRtl8195a = 0x5751; - HalRuartResetRxFifoRtl8195a = 0x5775; - HalRuartInitRtl8195a = 0x5829; - HalGdmaOnOffRtl8195a = 0x5df1; - HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d; - HalGdmaChEnRtl8195a = 0x5e51; - HalGdmaChDisRtl8195a = 0x5e6d; - HalGdamChInitRtl8195a = 0x5e91; - HalGdmaChSetingRtl8195a = 0x5ebd; - HalGdmaChBlockSetingRtl8195a = 0x60dd; - HalGdmaChIsrCleanRtl8195a = 0x6419; - HalGdmaChCleanAutoSrcRtl8195a = 0x64a1; - HalGdmaChCleanAutoDstRtl8195a = 0x6501; - HalEFUSEPowerSwitch8195AROM = 0x6561; - HALEFUSEOneByteReadROM = 0x65f9; - HALEFUSEOneByteWriteROM = 0x6699; - __rtl_memcmpb_v1_00 = 0x681d; - __rtl_random_v1_00 = 0x6861; - __rtl_align_to_be32_v1_00 = 0x6881; - __rtl_memsetw_v1_00 = 0x6899; - __rtl_memsetb_v1_00 = 0x68ad; - __rtl_memcpyw_v1_00 = 0x68bd; - __rtl_memcpyb_v1_00 = 0x68dd; - __rtl_memDump_v1_00 = 0x68f5; - __rtl_AES_set_encrypt_key = 0x6901; - __rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11; - __rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95; - __rtl_cryptoEngine_init_v1_00 = 0x6ea9; - __rtl_cryptoEngine_exit_v1_00 = 0x7055; - __rtl_cryptoEngine_reset_v1_00 = 0x70b1; - __rtl_cryptoEngine_v1_00 = 0x70ed; - __rtl_crypto_cipher_init_v1_00 = 0x7c69; - __rtl_crypto_cipher_encrypt_v1_00 = 0x7c89; - __rtl_crypto_cipher_decrypt_v1_00 = 0x7cad; - HalSsiPinmuxEnableRtl8195a = 0x7cd5; - HalSsiEnableRtl8195a = 0x7e45; - HalSsiDisableRtl8195a = 0x7ef9; - HalSsiLoadSettingRtl8195a = 0x7fad; - HalSsiSetInterruptMaskRtl8195a = 0x8521; - HalSsiGetInterruptMaskRtl8195a = 0x85c9; - HalSsiSetSclkPolarityRtl8195a = 0x863d; - HalSsiSetSclkPhaseRtl8195a = 0x8715; - HalSsiWriteRtl8195a = 0x87e9; - HalSsiSetDeviceRoleRtl8195a = 0x8861; - HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9; - HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941; - HalSsiReadRtl8195a = 0x89b9; - HalSsiGetRxFifoLevelRtl8195a = 0x8a2d; - HalSsiGetTxFifoLevelRtl8195a = 0x8aa5; - HalSsiGetStatusRtl8195a = 0x8b1d; - HalSsiWriteableRtl8195a = 0x8b91; - HalSsiReadableRtl8195a = 0x8c09; - HalSsiBusyRtl8195a = 0x8c81; - HalSsiReadInterruptRtl8195a = 0x8cf9; - HalSsiWriteInterruptRtl8195a = 0x8efd; - HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009; - HalSsiGetInterruptStatusRtl8195a = 0x90d9; - HalSsiInterruptEnableRtl8195a = 0x914d; - HalSsiInterruptDisableRtl8195a = 0x9299; - HalSsiGetRawInterruptStatusRtl8195a = 0x93e9; - HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d; - HalSsiInitRtl8195a = 0x94d1; - _SsiReadInterrupt = 0x9ba5; - _SsiWriteInterrupt = 0x9db1; - _SsiIrqHandle = 0x9eb1; - HalI2CWrite32 = 0xa061; - HalI2CRead32 = 0xa09d; - HalI2CDeInit8195a = 0xa0dd; - HalI2CSendRtl8195a = 0xa1f1; - HalI2CReceiveRtl8195a = 0xa25d; - HalI2CEnableRtl8195a = 0xa271; - HalI2CIntrCtrl8195a = 0xa389; - HalI2CReadRegRtl8195a = 0xa3a1; - HalI2CWriteRegRtl8195a = 0xa3b1; - HalI2CSetCLKRtl8195a = 0xa3c5; - HalI2CMassSendRtl8195a = 0xa6e9; - HalI2CClrIntrRtl8195a = 0xa749; - HalI2CClrAllIntrRtl8195a = 0xa761; - HalI2CInit8195a = 0xa775; - HalI2CDMACtrl8195a = 0xaa31; - RtkI2CIoCtrl = 0xaa61; - RtkI2CPowerCtrl = 0xaa65; - HalI2COpInit = 0xaa69; - I2CIsTimeout = 0xac65; - I2CTXGDMAISRHandle = 0xb435; - I2CRXGDMAISRHandle = 0xb4c1; - RtkI2CIrqInit = 0xb54d; - RtkI2CIrqDeInit = 0xb611; - RtkI2CPinMuxInit = 0xb675; - RtkI2CPinMuxDeInit = 0xb7c9; - RtkI2CDMAInit = 0xb955; - RtkI2CInit = 0xbc95; - RtkI2CDMADeInit = 0xbdad; - RtkI2CDeInit = 0xbe4d; - RtkI2CSendUserAddr = 0xbee5; - RtkI2CSend = 0xc07d; - RtkI2CLoadDefault = 0xce51; - RtkSalI2COpInit = 0xcf21; - HalI2SWrite32 = 0xcf65; - HalI2SRead32 = 0xcf85; - HalI2SDeInitRtl8195a = 0xcfa9; - HalI2STxRtl8195a = 0xcfc9; - HalI2SRxRtl8195a = 0xd011; - HalI2SEnableRtl8195a = 0xd05d; - HalI2SIntrCtrlRtl8195a = 0xd0b1; - HalI2SReadRegRtl8195a = 0xd0d1; - HalI2SClrIntrRtl8195a = 0xd0dd; - HalI2SClrAllIntrRtl8195a = 0xd0fd; - HalI2SInitRtl8195a = 0xd11d; - GPIO_GetIPPinName_8195a = 0xd2e5; - GPIO_GetChipPinName_8195a = 0xd331; - GPIO_PullCtrl_8195a = 0xd39d; - GPIO_FuncOn_8195a = 0xd421; - GPIO_FuncOff_8195a = 0xd481; - GPIO_Int_Mask_8195a = 0xd4e9; - GPIO_Int_SetType_8195a = 0xd511; - HAL_GPIO_IrqHandler_8195a = 0xd5fd; - HAL_GPIO_MbedIrqHandler_8195a = 0xd645; - HAL_GPIO_UserIrqHandler_8195a = 0xd6a1; - HAL_GPIO_IntCtrl_8195a = 0xd6cd; - HAL_GPIO_Init_8195a = 0xd805; - HAL_GPIO_DeInit_8195a = 0xdac1; - HAL_GPIO_ReadPin_8195a = 0xdbd1; - HAL_GPIO_WritePin_8195a = 0xdc91; - HAL_GPIO_RegIrq_8195a = 0xddad; - HAL_GPIO_UnRegIrq_8195a = 0xddf5; - HAL_GPIO_UserRegIrq_8195a = 0xde15; - HAL_GPIO_UserUnRegIrq_8195a = 0xdef9; - HAL_GPIO_MaskIrq_8195a = 0xdfc1; - HAL_GPIO_UnMaskIrq_8195a = 0xe061; - HAL_GPIO_IntDebounce_8195a = 0xe101; - HAL_GPIO_GetIPPinName_8195a = 0xe1c1; - HAL_GPIO_PullCtrl_8195a = 0xe1c9; - DumpForOneBytes = 0xe259; - CmdRomHelp = 0xe419; - CmdWriteWord = 0xe491; - CmdDumpHelfWord = 0xe505; - CmdDumpWord = 0xe5f1; - CmdDumpByte = 0xe6f5; - CmdSpiFlashTool = 0xe751; - GetRomCmdNum = 0xe7a9; - CmdWriteByte = 0xe7ad; - Isspace = 0xe7ed; - Strtoul = 0xe801; - ArrayInitialize = 0xe8b1; - GetArgc = 0xe8c9; - GetArgv = 0xe8f9; - UartLogCmdExecute = 0xe95d; - UartLogShowBackSpace = 0xe9fd; - UartLogRecallOldCmd = 0xea39; - UartLogHistoryCmd = 0xea71; - UartLogCmdChk = 0xeadd; - UartLogIrqHandle = 0xebf5; - RtlConsolInit = 0xecc5; - RtlConsolTaskRom = 0xed49; - RtlExitConsol = 0xed79; - RtlConsolRom = 0xedcd; - HalTimerOpInit = 0xee0d; - HalTimerIrq2To7Handle = 0xee59; - HalGetTimerIdRtl8195a = 0xef09; - HalTimerInitRtl8195a = 0xef3d; - HalTimerDisRtl8195a = 0xf069; - HalTimerEnRtl8195a = 0xf089; - HalTimerReadCountRtl8195a = 0xf0a9; - HalTimerIrqClearRtl8195a = 0xf0bd; - HalTimerDumpRegRtl8195a = 0xf0d1; - VSprintf = 0xf129; - DiagPrintf = 0xf39d; - DiagSPrintf = 0xf3b9; - DiagSnPrintf = 0xf3d1; - prvDiagPrintf = 0xf3ed; - prvDiagSPrintf = 0xf40d; - _memcmp = 0xf429; - _memcpy = 0xf465; - _memset = 0xf511; - __memcmp = 0xf429; - __memcpy = 0xf465; - __memset = 0xf511; - Rand = 0xf585; - _strncpy = 0xf60d; - _strcpy = 0xf629; - __strncpy = 0xf60d; - __strcpy = 0xf629; - prvStrCpy = 0xf639; - _strlen = 0xf651; - _strnlen = 0xf669; - __strlen = 0xf651; - __strnlen = 0xf669; - prvStrLen = 0xf699; - _strcmp = 0xf6b1; - _strncmp = 0xf6d1; - __strcmp = 0xf6b1; - __strncmp = 0xf6d1; - prvStrCmp = 0xf719; - StrUpr = 0xf749; - prvAtoi = 0xf769; - prvStrStr = 0xf7bd; - _strsep = 0xf7d5; - __strsep = 0xf7d5; - skip_spaces = 0xf815; - skip_atoi = 0xf831; - _parse_integer_fixup_radix = 0xf869; - _parse_integer = 0xf8bd; - simple_strtoull = 0xf915; - simple_strtoll = 0xf945; - simple_strtoul = 0xf965; - simple_strtol = 0xf96d; - _vsscanf = 0xf985; - _sscanf = 0xff71; - div_u64 = 0xff91; - div_s64 = 0xff99; - div_u64_rem = 0xffa1; - div_s64_rem = 0xffb1; - __strpbrk = 0xffc1; - __strchr = 0xffed; - aes_set_key = 0x10005; - aes_encrypt = 0x103d1; - aes_decrypt = 0x114a5; - AES_WRAP = 0x125c9; - AES_UnWRAP = 0x12701; - crc32_get = 0x12861; - arc4_byte = 0x12895; - rt_arc4_init = 0x128bd; - rt_arc4_crypt = 0x12901; - rt_md5_init = 0x131c1; - rt_md5_append = 0x131f5; - rt_md5_final = 0x1327d; - rt_md5_hmac = 0x132d5; - rtw_get_bit_value_from_ieee_value = 0x13449; - rtw_is_cckrates_included = 0x13475; - rtw_is_cckratesonly_included = 0x134b5; - rtw_check_network_type = 0x134dd; - rtw_set_fixed_ie = 0x1350d; - rtw_set_ie = 0x1352d; - rtw_get_ie = 0x1355d; - rtw_set_supported_rate = 0x13591; - rtw_get_rateset_len = 0x13611; - rtw_get_wpa_ie = 0x1362d; - rtw_get_wpa2_ie = 0x136c9; - rtw_get_wpa_cipher_suite = 0x13701; - rtw_get_wpa2_cipher_suite = 0x13769; - rtw_parse_wpa_ie = 0x137d1; - rtw_parse_wpa2_ie = 0x138ad; - rtw_get_sec_ie = 0x13965; - rtw_get_wps_ie = 0x13a15; - rtw_get_wps_attr = 0x13a99; - rtw_get_wps_attr_content = 0x13b49; - rtw_ieee802_11_parse_elems = 0x13b91; - str_2char2num = 0x13d9d; - key_2char2num = 0x13db9; - convert_ip_addr = 0x13dd1; - rom_psk_PasswordHash = 0x13e9d; - rom_psk_CalcGTK = 0x13ed5; - rom_psk_CalcPTK = 0x13f69; - wep_80211_encrypt = 0x14295; - wep_80211_decrypt = 0x142f5; - tkip_micappendbyte = 0x14389; - rtw_secmicsetkey = 0x143d9; - rtw_secmicappend = 0x14419; - rtw_secgetmic = 0x14435; - rtw_seccalctkipmic = 0x1449d; - tkip_phase1 = 0x145a5; - tkip_phase2 = 0x14725; - tkip_80211_encrypt = 0x14941; - tkip_80211_decrypt = 0x149d5; - aes1_encrypt = 0x14a8d; - aesccmp_construct_mic_iv = 0x14c65; - aesccmp_construct_mic_header1 = 0x14ccd; - aesccmp_construct_mic_header2 = 0x14d21; - aesccmp_construct_ctr_preload = 0x14db5; - aes_80211_encrypt = 0x14e29; - aes_80211_decrypt = 0x151ad; - _sha1_process_message_block = 0x155b9; - _sha1_pad_message = 0x15749; - rt_sha1_init = 0x157e5; - rt_sha1_update = 0x15831; - rt_sha1_finish = 0x158a9; - rt_hmac_sha1 = 0x15909; - rom_aes_128_cbc_encrypt = 0x15a65; - rom_aes_128_cbc_decrypt = 0x15ae1; - rom_rijndaelKeySetupEnc = 0x15b5d; - rom_aes_decrypt_init = 0x15c39; - rom_aes_internal_decrypt = 0x15d15; - rom_aes_decrypt_deinit = 0x16071; - rom_aes_encrypt_init = 0x16085; - rom_aes_internal_encrypt = 0x1609d; - rom_aes_encrypt_deinit = 0x16451; - bignum_init = 0x17b35; - bignum_deinit = 0x17b61; - bignum_get_unsigned_bin_len = 0x17b81; - bignum_get_unsigned_bin = 0x17b85; - bignum_set_unsigned_bin = 0x17c21; - bignum_cmp = 0x17cd1; - bignum_cmp_d = 0x17cd5; - bignum_add = 0x17cfd; - bignum_sub = 0x17d0d; - bignum_mul = 0x17d1d; - bignum_exptmod = 0x17d2d; - WPS_realloc = 0x17d51; - os_zalloc = 0x17d99; - rom_hmac_sha256_vector = 0x17dc1; - rom_hmac_sha256 = 0x17ebd; - rom_sha256_vector = 0x18009; - phy_CalculateBitShift = 0x18221; - PHY_SetBBReg_8195A = 0x18239; - PHY_QueryBBReg_8195A = 0x18279; - ROM_odm_QueryRxPwrPercentage = 0x1829d; - ROM_odm_EVMdbToPercentage = 0x182bd; - ROM_odm_SignalScaleMapping_8195A = 0x182e5; - ROM_odm_FalseAlarmCounterStatistics = 0x183cd; - ROM_odm_SetEDCCAThreshold = 0x18721; - ROM_odm_SetTRxMux = 0x18749; - ROM_odm_SetCrystalCap = 0x18771; - ROM_odm_GetDefaultCrytaltalCap = 0x187d5; - ROM_ODM_CfoTrackingReset = 0x187e9; - ROM_odm_CfoTrackingFlow = 0x18811; - curve25519_donna = 0x1965d; - aes_test_alignment_detection = 0x1a391; - aes_mode_reset = 0x1a3ed; - aes_ecb_encrypt = 0x1a3f9; - aes_ecb_decrypt = 0x1a431; - aes_cbc_encrypt = 0x1a469; - aes_cbc_decrypt = 0x1a579; - aes_cfb_encrypt = 0x1a701; - aes_cfb_decrypt = 0x1a9e5; - aes_ofb_crypt = 0x1acc9; - aes_ctr_crypt = 0x1af7d; - aes_encrypt_key128 = 0x1b289; - aes_encrypt_key192 = 0x1b2a5; - aes_encrypt_key256 = 0x1b2c1; - aes_encrypt_key = 0x1b2e1; - aes_decrypt_key128 = 0x1b351; - aes_decrypt_key192 = 0x1b36d; - aes_decrypt_key256 = 0x1b389; - aes_decrypt_key = 0x1b3a9; - aes_init = 0x1b419; - CRYPTO_chacha_20 = 0x1b41d; - CRYPTO_poly1305_init = 0x1bc25; - CRYPTO_poly1305_update = 0x1bd09; - CRYPTO_poly1305_finish = 0x1bd8d; - rom_sha512_starts = 0x1ceb5; - rom_sha512_update = 0x1d009; - rom_sha512_finish = 0x1d011; - rom_sha512 = 0x1d261; - rom_sha512_hmac_starts = 0x1d299; - rom_sha512_hmac_update = 0x1d35d; - rom_sha512_hmac_finish = 0x1d365; - rom_sha512_hmac_reset = 0x1d3b5; - rom_sha512_hmac = 0x1d3d1; - rom_sha512_hkdf = 0x1d40d; - rom_ed25519_gen_keypair = 0x1d501; - rom_ed25519_gen_signature = 0x1d505; - rom_ed25519_verify_signature = 0x1d51d; - rom_ed25519_crypto_sign_seed_keypair = 0x1d521; - rom_ed25519_crypto_sign_detached = 0x1d579; - rom_ed25519_crypto_sign_verify_detached = 0x1d655; - rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d; - rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35; - rom_ed25519_ge_p3_tobytes = 0x207d5; - rom_ed25519_ge_scalarmult_base = 0x20821; - rom_ed25519_ge_tobytes = 0x209e1; - rom_ed25519_sc_muladd = 0x20a2d; - rom_ed25519_sc_reduce = 0x2603d; - __rtl_memchr_v1_00 = 0x28a4d; - __rtl_memcmp_v1_00 = 0x28ae1; - __rtl_memcpy_v1_00 = 0x28b49; - __rtl_memmove_v1_00 = 0x28bed; - __rtl_memset_v1_00 = 0x28cb5; - __rtl_strcat_v1_00 = 0x28d49; - __rtl_strchr_v1_00 = 0x28d91; - __rtl_strcmp_v1_00 = 0x28e55; - __rtl_strcpy_v1_00 = 0x28ec9; - __rtl_strlen_v1_00 = 0x28f15; - __rtl_strncat_v1_00 = 0x28f69; - __rtl_strncmp_v1_00 = 0x28fc5; - __rtl_strncpy_v1_00 = 0x2907d; - __rtl_strstr_v1_00 = 0x293cd; - __rtl_strsep_v1_00 = 0x2960d; - __rtl_strtok_v1_00 = 0x29619; - __rtl__strtok_r_v1_00 = 0x2962d; - __rtl_strtok_r_v1_00 = 0x29691; - __rtl_close_v1_00 = 0x29699; - __rtl_fstat_v1_00 = 0x296ad; - __rtl_isatty_v1_00 = 0x296c1; - __rtl_lseek_v1_00 = 0x296d5; - __rtl_open_v1_00 = 0x296e9; - __rtl_read_v1_00 = 0x296fd; - __rtl_write_v1_00 = 0x29711; - __rtl_sbrk_v1_00 = 0x29725; - __rtl_ltoa_v1_00 = 0x297bd; - __rtl_ultoa_v1_00 = 0x29855; - __rtl_dtoi_v1_00 = 0x298c5; - __rtl_dtoi64_v1_00 = 0x29945; - __rtl_dtoui_v1_00 = 0x299dd; - __rtl_ftol_v1_00 = 0x299e5; - __rtl_itof_v1_00 = 0x29a51; - __rtl_itod_v1_00 = 0x29ae9; - __rtl_i64tod_v1_00 = 0x29b79; - __rtl_uitod_v1_00 = 0x29c55; - __rtl_ftod_v1_00 = 0x29d2d; - __rtl_dtof_v1_00 = 0x29de9; - __rtl_uitof_v1_00 = 0x29e89; - __rtl_fadd_v1_00 = 0x29f65; - __rtl_fsub_v1_00 = 0x2a261; - __rtl_fmul_v1_00 = 0x2a559; - __rtl_fdiv_v1_00 = 0x2a695; - __rtl_dadd_v1_00 = 0x2a825; - __rtl_dsub_v1_00 = 0x2aed9; - __rtl_dmul_v1_00 = 0x2b555; - __rtl_ddiv_v1_00 = 0x2b8ad; - __rtl_dcmpeq_v1_00 = 0x2be4d; - __rtl_dcmplt_v1_00 = 0x2bebd; - __rtl_dcmpgt_v1_00 = 0x2bf51; - __rtl_dcmple_v1_00 = 0x2c049; - __rtl_fcmplt_v1_00 = 0x2c139; - __rtl_fcmpgt_v1_00 = 0x2c195; - __rtl_cos_f32_v1_00 = 0x2c229; - __rtl_sin_f32_v1_00 = 0x2c435; - __rtl_fabs_v1_00 = 0x2c639; - __rtl_fabsf_v1_00 = 0x2c641; - __rtl_dtoa_r_v1_00 = 0x2c77d; - __rom_mallocr_init_v1_00 = 0x2d7d1; - __rtl_free_r_v1_00 = 0x2d841; - __rtl_malloc_r_v1_00 = 0x2da31; - __rtl_realloc_r_v1_00 = 0x2df55; - __rtl_memalign_r_v1_00 = 0x2e331; - __rtl_valloc_r_v1_00 = 0x2e421; - __rtl_pvalloc_r_v1_00 = 0x2e42d; - __rtl_calloc_r_v1_00 = 0x2e441; - __rtl_cfree_r_v1_00 = 0x2e4a9; - __rtl_Balloc_v1_00 = 0x2e515; - __rtl_Bfree_v1_00 = 0x2e571; - __rtl_i2b_v1_00 = 0x2e585; - __rtl_multadd_v1_00 = 0x2e599; - __rtl_mult_v1_00 = 0x2e629; - __rtl_pow5mult_v1_00 = 0x2e769; - __rtl_hi0bits_v1_00 = 0x2e809; - __rtl_d2b_v1_00 = 0x2e845; - __rtl_lshift_v1_00 = 0x2e901; - __rtl_cmp_v1_00 = 0x2e9bd; - __rtl_diff_v1_00 = 0x2ea01; - __rtl_sread_v1_00 = 0x2eae9; - __rtl_seofread_v1_00 = 0x2eb39; - __rtl_swrite_v1_00 = 0x2eb3d; - __rtl_sseek_v1_00 = 0x2ebc1; - __rtl_sclose_v1_00 = 0x2ec11; - __rtl_sbrk_r_v1_00 = 0x2ec41; - __rtl_fflush_r_v1_00 = 0x2ef8d; - __rtl_vfprintf_r_v1_00 = 0x2f661; - __rtl_fpclassifyd = 0x30c15; - CpkClkTbl = 0x30c68; - ROM_IMG1_VALID_PATTEN = 0x30c80; - SpicCalibrationPattern = 0x30c88; - SpicInitCPUCLK = 0x30c98; - BAUDRATE = 0x30ca8; - OVSR = 0x30d1c; - DIV = 0x30d90; - OVSR_ADJ = 0x30e04; - __AES_rcon = 0x30e78; - __AES_Te4 = 0x30ea0; - I2CDmaChNo = 0x312a0; - _GPIO_PinMap_Chip2IP_8195a = 0x312b4; - _GPIO_PinMap_PullCtrl_8195a = 0x3136c; - _GPIO_SWPORT_DDR_TBL = 0x31594; - _GPIO_EXT_PORT_TBL = 0x31598; - _GPIO_SWPORT_DR_TBL = 0x3159c; - UartLogRomCmdTable = 0x316a0; - _HalRuartOp = 0x31700; - _HalGdmaOp = 0x31760; - RTW_WPA_OUI_TYPE = 0x3540c; - WPA_CIPHER_SUITE_NONE = 0x35410; - WPA_CIPHER_SUITE_WEP40 = 0x35414; - WPA_CIPHER_SUITE_TKIP = 0x35418; - WPA_CIPHER_SUITE_CCMP = 0x3541c; - WPA_CIPHER_SUITE_WEP104 = 0x35420; - RSN_CIPHER_SUITE_NONE = 0x35424; - RSN_CIPHER_SUITE_WEP40 = 0x35428; - RSN_CIPHER_SUITE_TKIP = 0x3542c; - RSN_CIPHER_SUITE_CCMP = 0x35430; - RSN_CIPHER_SUITE_WEP104 = 0x35434; - RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444; - RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448; - RSN_VERSION_BSD = 0x3544c; - rom_wps_Te0 = 0x35988; - rom_wps_rcons = 0x35d88; - rom_wps_Td4s = 0x35d94; - rom_wps_Td0 = 0x35e94; - __rom_b_cut_end__ = 0x4467c; - __rom_c_cut_text_start__ = 0x4467c; - HalInitPlatformLogUartV02 = 0x4467d; - HalReInitPlatformLogUartV02 = 0x4471d; - HalInitPlatformTimerV02 = 0x44755; - HalShowBuildInfoV02 = 0x447cd; - SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831; - HalSpiInitV02 = 0x4488d; - HalBootFlowV02 = 0x44a29; - HalInitialROMCodeGlobalVarV02 = 0x44ae5; - HalResetVsrV02 = 0x44b41; - HalI2CSendRtl8195aV02 = 0x44ce1; - HalI2CSetCLKRtl8195aV02 = 0x44d59; - RtkI2CSendV02 = 0x4508d; - RtkI2CReceiveV02 = 0x459a1; - HalI2COpInitV02 = 0x461ed; - I2CISRHandleV02 = 0x463e9; - RtkSalI2COpInitV02 = 0x46be1; - SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25; - SpiFlashAppV02 = 0x46c85; - SpicInitRtl8195AV02 = 0x46dc5; - SpicEraseFlashRtl8195AV02 = 0x46ea1; - HalTimerIrq2To7HandleV02 = 0x46f5d; - HalTimerIrqRegisterRtl8195aV02 = 0x46fe1; - HalTimerInitRtl8195aV02 = 0x4706d; - HalTimerReadCountRtl8195aV02 = 0x471b5; - HalTimerReLoadRtl8195aV02 = 0x471d1; - HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d; - HalTimerDeInitRtl8195aV02 = 0x472c1; - HalTimerOpInitV02 = 0x472f9; - GPIO_LockV02 = 0x47345; - GPIO_UnLockV02 = 0x47379; - GPIO_Int_Clear_8195aV02 = 0x473a5; - HAL_GPIO_IntCtrl_8195aV02 = 0x473b5; - FindElementIndexV02 = 0x47541; - HalRuartInitRtl8195aV02 = 0x4756d; - DramInit_rom = 0x47619; - ChangeRandSeed_rom = 0x47979; - Sdr_Rand2_rom = 0x47985; - MemTest_rom = 0x479dd; - SdrCalibration_rom = 0x47a45; - SdrControllerInit_rom = 0x47d99; - SDIO_EnterCritical = 0x47e39; - SDIO_ExitCritical = 0x47e85; - SDIO_IRQ_Handler_Rom = 0x47ec5; - SDIO_Interrupt_Init_Rom = 0x47f31; - SDIO_Device_Init_Rom = 0x47f81; - SDIO_Interrupt_DeInit_Rom = 0x48215; - SDIO_Device_DeInit_Rom = 0x48255; - SDIO_Enable_Interrupt_Rom = 0x48281; - SDIO_Disable_Interrupt_Rom = 0x482a1; - SDIO_Clear_ISR_Rom = 0x482c1; - SDIO_Alloc_Rx_Pkt_Rom = 0x482d9; - SDIO_Free_Rx_Pkt_Rom = 0x48331; - SDIO_Recycle_Rx_BD_Rom = 0x48355; - SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1; - SDIO_RxTask_Rom = 0x4851d; - SDIO_Process_H2C_IOMsg_Rom = 0x4856d; - SDIO_Send_C2H_IOMsg_Rom = 0x4859d; - SDIO_Process_RPWM_Rom = 0x485b5; - SDIO_Reset_Cmd_Rom = 0x485e9; - SDIO_Rx_Data_Transaction_Rom = 0x48611; - SDIO_Send_C2H_PktMsg_Rom = 0x48829; - SDIO_Register_Tx_Callback_Rom = 0x488f5; - SDIO_ReadMem_Rom = 0x488fd; - SDIO_WriteMem_Rom = 0x489a9; - SDIO_SetMem_Rom = 0x48a69; - SDIO_TX_Pkt_Handle_Rom = 0x48b29; - SDIO_TX_FIFO_DataReady_Rom = 0x48c69; - SDIO_IRQ_Handler_BH_Rom = 0x48d95; - SDIO_TxTask_Rom = 0x48e9d; - SDIO_TaskUp_Rom = 0x48eed; - SDIO_Boot_Up = 0x48f55; - __rom_c_cut_text_end__ = 0x49070; - __rom_c_cut_rodata_start__ = 0x49070; - BAUDRATE_v02 = 0x49070; - OVSR_v02 = 0x490fc; - DIV_v02 = 0x49188; - OVSR_ADJ_v02 = 0x49214; - SdrDramInfo_rom = 0x492a0; - SdrDramTiming_rom = 0x492b4; - SdrDramModeReg_rom = 0x492e8; - SdrDramDev_rom = 0x49304; - __rom_c_cut_rodata_end__ = 0x49314; - NewVectorTable = 0x10000000; - UserIrqFunTable = 0x10000100; - UserIrqDataTable = 0x10000200; - __rom_bss_start__ = 0x10000300; - CfgSysDebugWarn = 0x10000300; - CfgSysDebugInfo = 0x10000304; - CfgSysDebugErr = 0x10000308; - ConfigDebugWarn = 0x1000030c; - ConfigDebugInfo = 0x10000310; - ConfigDebugErr = 0x10000314; - HalTimerOp = 0x10000318; - GPIOState = 0x10000334; - gTimerRecord = 0x1000034c; - SSI_DBG_CONFIG = 0x10000350; - _pHAL_Gpio_Adapter = 0x10000354; - Timer2To7VectorTable = 0x10000358; - pUartLogCtl = 0x10000384; - UartLogBuf = 0x10000388; - UartLogCtl = 0x10000408; - UartLogHistoryBuf = 0x10000430; - ArgvArray = 0x100006ac; - rom_wlan_ram_map = 0x100006d4; - FalseAlmCnt = 0x100006e0; - ROMInfo = 0x10000720; - DM_CfoTrack = 0x10000738; - rom_libgloss_ram_map = 0x10000760; - __rtl_errno = 0x10000bc4; -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S deleted file mode 100644 index 219265a5083..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2017 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .syntax unified - .thumb - - .global __StackTop - .global PLAT_Init - - /* entry point of application image */ - .section .text.PLAT_Start - .weak PLAT_Start - .type PLAT_Start, %function -PLAT_Start: - ldr sp, =__StackTop - ldr r0, =PLAT_Init - bx r0 - .size PLAT_Start, .-PLAT_Start - .end diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a deleted file mode 100644 index 3c0932dcf8f..00000000000 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a and /dev/null differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a deleted file mode 100644 index 216b172d94b..00000000000 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a and /dev/null differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf deleted file mode 100644 index c0ae11b3cf5..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2013-2017 Realtek Semiconductor Corp. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*-Memory Regions-*/ -define symbol __SRAM_start__ = 0x10007000; -define symbol __SRAM_end__ = 0x1006FFFF; -define symbol __DTCM_start__ = 0x1FFF0000; -define symbol __DTCM_end__ = 0x1FFFFFFF; -define symbol __DRAM_start__ = 0x30000000; -define symbol __DRAM_end__ = 0x301FFFFF; - -define memory mem with size = 4G; -define region TCM_region = mem:[from __DTCM_start__ to __DTCM_end__]; -define region RAM_region = mem:[from __SRAM_start__ to __SRAM_end__] | - mem:[from __DRAM_start__ to __DRAM_end__]; - -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define block CSTACK with alignment = 8, size = MBED_BOOT_STACK_SIZE { }; -define block HEAP with alignment = 8, size = 0x19000 { }; - -do not initialize { section .noinit }; - -/** - IMAGE2 -**/ -keep { - section .image2.ram.data*, - section .image2.validate.rodata*, -}; - -define block .image2.table with fixed order { - section .image2.ram.data*, - section .image2.validate.rodata*, -}; - -define block FPB_REMAP with alignment = 256, fixed order { - section .fpb.remap* -}; - -define block .text.mbedtls { - readonly object aes.o, - readonly object aesni.o, - readonly object arc4.o, - readonly object asn1parse.o, - readonly object asn1write.o, - readonly object base64.o, - readonly object bignum.o, - readonly object blowfish.o, - readonly object camellia.o, - readonly object ccm.o, - readonly object certs.o, - readonly object cipher.o, - readonly object cipher_wrap.o, - readonly object cmac.o, - readonly object ctr_drbg.o, - readonly object debug.o, - readonly object des.o, - readonly object dhm.o, - readonly object ecdh.o, - readonly object ecdsa.o, - readonly object ecjpake.o, - readonly object ecp.o, - readonly object ecp_curves.o, - readonly object entropy.o, - readonly object entropy_poll.o, - readonly object error.o, - readonly object gcm.o, - readonly object havege.o, - readonly object hmac_drbg.o, - readonly object md.o, - readonly object md2.o, - readonly object md4.o, - readonly object md5.o, - readonly object md_wrap.o, - readonly object memory_buffer_alloc.o, - readonly object net_sockets.o, - readonly object oid.o, - readonly object padlock.o, - readonly object pem.o, - readonly object pk.o, - readonly object pk_wrap.o, - readonly object pkcs11.o, - readonly object pkcs12.o, - readonly object pkcs5.o, - readonly object pkparse.o, - readonly object pkwrite.o, - readonly object platform.o, - readonly object ripemd160.o, - readonly object rsa.o, - readonly object sha1.o, - readonly object sha256.o, - readonly object sha512.o, - readonly object ssl_cache.o, - readonly object ssl_ciphersuites.o, - readonly object ssl_cli.o, - readonly object ssl_cookie.o, - readonly object ssl_srv.o, - readonly object ssl_ticket.o, - readonly object ssl_tls.o, - readonly object threading.o, - readonly object timing.o, - readonly object version.o, - readonly object version_features.o, - readonly object x509.o, - readonly object x509_create.o, - readonly object x509_crl.o, - readonly object x509_crt.o, - readonly object x509_csr.o, - readonly object x509write_crt.o, - readonly object x509write_csr.o, - readonly object xtea.o, -}; - -define block .text.sram { - readonly object rtl8195a_crypto.o, - readonly object vector_table_M.o, - section .text.sram*, -}; - -define block .text.dram { - section .text.dram*, - section .text*, - section .rodata*, - section .sdram.text*, - section .mdns.text*, - section CODE, -}; - -define block .data.sram { - readwrite object rtl8195a_crypto.o, - readwrite object vector_table_M.o, - readwrite object lib_peripheral_mbed_iar.a, - section .data.os.*, - section .data.sram*, - section .wlan.data, - section .wps.data, - section .ram.otg.data.a, - section .bfsram.data*, -}; - -define block .data.dram { - section .data*, - section .data.dram*, - section .sdram.data*, - section .mdns.data*, - section .iar.init_table, - section .iar.dynexit*, - section DATA, - section __DLIB_PERTHREAD, -}; - -define block .data.dtcm { - section .data.dtcm*, -}; - -define block .bss.sram { - zeroinit object rtl8195a_crypto.o, - section .bss.os.*, - section .bss.sram*, - section .bdsram.data*, -}; - -define block .bss.dram { - zeroinit, - section .sdram.bss*, -}; - -define block .bss.dtcm { - zeroinit object lwip_mem.o, - zeroinit object lwip_memp.o, - section .bss.dtcm*, -}; - -place in TCM_region { - section .tcm.heap, - block .data.dtcm, - block .bss.dtcm, -}; - -place in RAM_region { - readonly, - block .text.sram, - block .text.mbedtls, - readwrite, - block .data.sram, - block .bss.sram, - block HEAP, - block CSTACK, - readonly, - block .image2.table, - block .text.dram, - readwrite, - block .data.dram, - block .bss.dram, - block FPB_REMAP, -}; - -include "rtl8195a_rom.h"; diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h deleted file mode 100644 index d9a7b284d9d..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h +++ /dev/null @@ -1,740 +0,0 @@ -define exported symbol __vectors_table = 0x00000000; -define exported symbol Reset_Handler = 0x00000101; -define exported symbol NMI_Handler = 0x00000109; -define exported symbol HardFault_Handler = 0x0000010d; -define exported symbol MemManage_Handler = 0x00000121; -define exported symbol BusFault_Handler = 0x00000125; -define exported symbol UsageFault_Handler = 0x00000129; -define exported symbol HalLogUartInit = 0x00000201; -define exported symbol HalSerialPutcRtl8195a = 0x000002d9; -define exported symbol HalSerialGetcRtl8195a = 0x00000309; -define exported symbol HalSerialGetIsrEnRegRtl8195a = 0x00000329; -define exported symbol HalSerialSetIrqEnRegRtl8195a = 0x00000335; -define exported symbol HalCpuClkConfig = 0x00000341; -define exported symbol HalGetCpuClk = 0x00000355; -define exported symbol HalRomInfo = 0x0000039d; -define exported symbol HalGetRomInfo = 0x000003b5; -define exported symbol HalResetVsr = 0x000003c5; -define exported symbol HalDelayUs = 0x00000899; -define exported symbol HalNMIHandler = 0x000008e1; -define exported symbol HalHardFaultHandler = 0x00000911; -define exported symbol HalMemManageHandler = 0x00000c09; -define exported symbol HalBusFaultHandler = 0x00000c39; -define exported symbol HalUsageFaultHandler = 0x00000c69; -define exported symbol HalUart0PinCtrlRtl8195A = 0x00000cfd; -define exported symbol HalUart1PinCtrlRtl8195A = 0x00000dc9; -define exported symbol HalUart2PinCtrlRtl8195A = 0x00000e9d; -define exported symbol HalSPI0PinCtrlRtl8195A = 0x00000f75; -define exported symbol HalSPI1PinCtrlRtl8195A = 0x00001015; -define exported symbol HalSPI2PinCtrlRtl8195A = 0x000010e5; -define exported symbol HalSPI0MCSPinCtrlRtl8195A = 0x000011b5; -define exported symbol HalI2C0PinCtrlRtl8195A = 0x00001275; -define exported symbol HalI2C1PinCtrlRtl8195A = 0x00001381; -define exported symbol HalI2C2PinCtrlRtl8195A = 0x00001459; -define exported symbol HalI2C3PinCtrlRtl8195A = 0x00001529; -define exported symbol HalI2S0PinCtrlRtl8195A = 0x00001639; -define exported symbol HalI2S1PinCtrlRtl8195A = 0x0000176d; -define exported symbol HalPCM0PinCtrlRtl8195A = 0x00001845; -define exported symbol HalPCM1PinCtrlRtl8195A = 0x00001949; -define exported symbol HalSDIODPinCtrlRtl8195A = 0x00001a1d; -define exported symbol HalSDIOHPinCtrlRtl8195A = 0x00001a6d; -define exported symbol HalMIIPinCtrlRtl8195A = 0x00001ab9; -define exported symbol HalWLLEDPinCtrlRtl8195A = 0x00001b51; -define exported symbol HalWLANT0PinCtrlRtl8195A = 0x00001c0d; -define exported symbol HalWLANT1PinCtrlRtl8195A = 0x00001c61; -define exported symbol HalWLBTCOEXPinCtrlRtl8195A = 0x00001cb5; -define exported symbol HalWLBTCMDPinCtrlRtl8195A = 0x00001d05; -define exported symbol HalNFCPinCtrlRtl8195A = 0x00001d59; -define exported symbol HalPWM0PinCtrlRtl8195A = 0x00001da9; -define exported symbol HalPWM1PinCtrlRtl8195A = 0x00001ead; -define exported symbol HalPWM2PinCtrlRtl8195A = 0x00001fb5; -define exported symbol HalPWM3PinCtrlRtl8195A = 0x000020b1; -define exported symbol HalETE0PinCtrlRtl8195A = 0x000021b9; -define exported symbol HalETE1PinCtrlRtl8195A = 0x000022c1; -define exported symbol HalETE2PinCtrlRtl8195A = 0x000023c9; -define exported symbol HalETE3PinCtrlRtl8195A = 0x000024d1; -define exported symbol HalEGTIMPinCtrlRtl8195A = 0x000025d9; -define exported symbol HalSPIFlashPinCtrlRtl8195A = 0x00002679; -define exported symbol HalSDRPinCtrlRtl8195A = 0x00002725; -define exported symbol HalJTAGPinCtrlRtl8195A = 0x0000280d; -define exported symbol HalTRACEPinCtrlRtl8195A = 0x00002861; -define exported symbol HalLOGUartPinCtrlRtl8195A = 0x000028b9; -define exported symbol HalLOGUartIRPinCtrlRtl8195A = 0x0000291d; -define exported symbol HalSICPinCtrlRtl8195A = 0x00002981; -define exported symbol HalEEPROMPinCtrlRtl8195A = 0x000029d9; -define exported symbol HalDEBUGPinCtrlRtl8195A = 0x00002a31; -define exported symbol HalPinCtrlRtl8195A = 0x00002b39; -define exported symbol SpicRxCmdRtl8195A = 0x00002e5d; -define exported symbol SpicWaitBusyDoneRtl8195A = 0x00002ea5; -define exported symbol SpicGetFlashStatusRtl8195A = 0x00002eb5; -define exported symbol SpicWaitWipDoneRtl8195A = 0x00002f55; -define exported symbol SpicTxCmdRtl8195A = 0x00002f6d; -define exported symbol SpicSetFlashStatusRtl8195A = 0x00002fc1; -define exported symbol SpicCmpDataForCalibrationRtl8195A = 0x00003049; -define exported symbol SpicLoadInitParaFromClockRtl8195A = 0x00003081; -define exported symbol SpicInitRtl8195A = 0x000030e5; -define exported symbol SpicEraseFlashRtl8195A = 0x000031bd; -define exported symbol SpiFlashApp = 0x00003279; -define exported symbol HalPeripheralIntrHandle = 0x000033b5; -define exported symbol HalSysOnIntrHandle = 0x00003439; -define exported symbol HalWdgIntrHandle = 0x00003485; -define exported symbol HalTimer0IntrHandle = 0x000034d5; -define exported symbol HalTimer1IntrHandle = 0x00003525; -define exported symbol HalI2C3IntrHandle = 0x00003575; -define exported symbol HalTimer2To7IntrHandle = 0x000035c5; -define exported symbol HalSpi0IntrHandle = 0x00003615; -define exported symbol HalGpioIntrHandle = 0x00003665; -define exported symbol HalUart0IntrHandle = 0x000036b5; -define exported symbol HalSpiFlashIntrHandle = 0x00003705; -define exported symbol HalUsbOtgIntrHandle = 0x00003755; -define exported symbol HalSdioHostIntrHandle = 0x000037a5; -define exported symbol HalI2s0OrPcm0IntrHandle = 0x000037f5; -define exported symbol HalI2s1OrPcm1IntrHandle = 0x00003845; -define exported symbol HalWlDmaIntrHandle = 0x00003895; -define exported symbol HalWlProtocolIntrHandle = 0x000038e5; -define exported symbol HalCryptoIntrHandle = 0x00003935; -define exported symbol HalGmacIntrHandle = 0x00003985; -define exported symbol HalGdma0Ch0IntrHandle = 0x000039d5; -define exported symbol HalGdma0Ch1IntrHandle = 0x00003a25; -define exported symbol HalGdma0Ch2IntrHandle = 0x00003a75; -define exported symbol HalGdma0Ch3IntrHandle = 0x00003ac5; -define exported symbol HalGdma0Ch4IntrHandle = 0x00003b15; -define exported symbol HalGdma0Ch5IntrHandle = 0x00003b65; -define exported symbol HalGdma1Ch0IntrHandle = 0x00003bb5; -define exported symbol HalGdma1Ch1IntrHandle = 0x00003c05; -define exported symbol HalGdma1Ch2IntrHandle = 0x00003c55; -define exported symbol HalGdma1Ch3IntrHandle = 0x00003ca5; -define exported symbol HalGdma1Ch4IntrHandle = 0x00003cf5; -define exported symbol HalGdma1Ch5IntrHandle = 0x00003d45; -define exported symbol HalSdioDeviceIntrHandle = 0x00003d95; -define exported symbol VectorTableInitRtl8195A = 0x00003de5; -define exported symbol VectorTableInitForOSRtl8195A = 0x00004019; -define exported symbol VectorIrqRegisterRtl8195A = 0x00004029; -define exported symbol VectorIrqUnRegisterRtl8195A = 0x00004091; -define exported symbol VectorIrqEnRtl8195A = 0x000040f1; -define exported symbol VectorIrqDisRtl8195A = 0x0000418d; -define exported symbol _UartRxDmaIrqHandle = 0x0000422d; -define exported symbol HalRuartPutCRtl8195a = 0x00004281; -define exported symbol HalRuartGetCRtl8195a = 0x0000429d; -define exported symbol HalRuartRTSCtrlRtl8195a = 0x000042bd; -define exported symbol HalRuartGetDebugValueRtl8195a = 0x000042e1; -define exported symbol HalRuartGetIMRRtl8195a = 0x000043e1; -define exported symbol HalRuartSetIMRRtl8195a = 0x0000442d; -define exported symbol _UartIrqHandle = 0x00004465; -define exported symbol HalRuartDmaInitRtl8195a = 0x00004681; -define exported symbol HalRuartIntDisableRtl8195a = 0x00004845; -define exported symbol HalRuartDeInitRtl8195a = 0x00004855; -define exported symbol HalRuartIntEnableRtl8195a = 0x00004985; -define exported symbol _UartTxDmaIrqHandle = 0x00004995; -define exported symbol HalRuartRegIrqRtl8195a = 0x000049d1; -define exported symbol HalRuartAdapterLoadDefRtl8195a = 0x00004a4d; -define exported symbol HalRuartTxGdmaLoadDefRtl8195a = 0x00004add; -define exported symbol HalRuartRxGdmaLoadDefRtl8195a = 0x00004bc9; -define exported symbol RuartLock = 0x00004cc9; -define exported symbol RuartUnLock = 0x00004ced; -define exported symbol HalRuartIntSendRtl8195a = 0x00004d09; -define exported symbol HalRuartDmaSendRtl8195a = 0x00004e35; -define exported symbol HalRuartStopSendRtl8195a = 0x00004f89; -define exported symbol HalRuartIntRecvRtl8195a = 0x0000504d; -define exported symbol HalRuartDmaRecvRtl8195a = 0x000051ad; -define exported symbol HalRuartStopRecvRtl8195a = 0x000052cd; -define exported symbol RuartIsTimeout = 0x00005385; -define exported symbol HalRuartSendRtl8195a = 0x000053b1; -define exported symbol HalRuartRecvRtl8195a = 0x00005599; -define exported symbol RuartResetRxFifoRtl8195a = 0x00005751; -define exported symbol HalRuartResetRxFifoRtl8195a = 0x00005775; -define exported symbol HalRuartInitRtl8195a = 0x00005829; -define exported symbol HalGdmaOnOffRtl8195a = 0x00005df1; -define exported symbol HalGdmaChIsrEnAndDisRtl8195a = 0x00005e0d; -define exported symbol HalGdmaChEnRtl8195a = 0x00005e51; -define exported symbol HalGdmaChDisRtl8195a = 0x00005e6d; -define exported symbol HalGdamChInitRtl8195a = 0x00005e91; -define exported symbol HalGdmaChSetingRtl8195a = 0x00005ebd; -define exported symbol HalGdmaChBlockSetingRtl8195a = 0x000060dd; -define exported symbol HalGdmaChIsrCleanRtl8195a = 0x00006419; -define exported symbol HalGdmaChCleanAutoSrcRtl8195a = 0x000064a1; -define exported symbol HalGdmaChCleanAutoDstRtl8195a = 0x00006501; -define exported symbol HalEFUSEPowerSwitch8195AROM = 0x00006561; -define exported symbol HALEFUSEOneByteReadROM = 0x000065f9; -define exported symbol HALEFUSEOneByteWriteROM = 0x00006699; -define exported symbol __rtl_memcmpb_v1_00 = 0x0000681d; -define exported symbol __rtl_random_v1_00 = 0x00006861; -define exported symbol __rtl_align_to_be32_v1_00 = 0x00006881; -define exported symbol __rtl_memsetw_v1_00 = 0x00006899; -define exported symbol __rtl_memsetb_v1_00 = 0x000068ad; -define exported symbol __rtl_memcpyw_v1_00 = 0x000068bd; -define exported symbol __rtl_memcpyb_v1_00 = 0x000068dd; -define exported symbol __rtl_memDump_v1_00 = 0x000068f5; -define exported symbol __rtl_AES_set_encrypt_key = 0x00006901; -define exported symbol __rtl_cryptoEngine_AES_set_decrypt_key = 0x00006c11; -define exported symbol __rtl_cryptoEngine_set_security_mode_v1_00 = 0x00006c95; -define exported symbol __rtl_cryptoEngine_init_v1_00 = 0x00006ea9; -define exported symbol __rtl_cryptoEngine_exit_v1_00 = 0x00007055; -define exported symbol __rtl_cryptoEngine_reset_v1_00 = 0x000070b1; -define exported symbol __rtl_cryptoEngine_v1_00 = 0x000070ed; -define exported symbol __rtl_crypto_cipher_init_v1_00 = 0x00007c69; -define exported symbol __rtl_crypto_cipher_encrypt_v1_00 = 0x00007c89; -define exported symbol __rtl_crypto_cipher_decrypt_v1_00 = 0x00007cad; -define exported symbol HalSsiPinmuxEnableRtl8195a = 0x00007cd5; -define exported symbol HalSsiEnableRtl8195a = 0x00007e45; -define exported symbol HalSsiDisableRtl8195a = 0x00007ef9; -define exported symbol HalSsiLoadSettingRtl8195a = 0x00007fad; -define exported symbol HalSsiSetInterruptMaskRtl8195a = 0x00008521; -define exported symbol HalSsiGetInterruptMaskRtl8195a = 0x000085c9; -define exported symbol HalSsiSetSclkPolarityRtl8195a = 0x0000863d; -define exported symbol HalSsiSetSclkPhaseRtl8195a = 0x00008715; -define exported symbol HalSsiWriteRtl8195a = 0x000087e9; -define exported symbol HalSsiSetDeviceRoleRtl8195a = 0x00008861; -define exported symbol HalSsiSetRxFifoThresholdLevelRtl8195a = 0x000088c9; -define exported symbol HalSsiSetTxFifoThresholdLevelRtl8195a = 0x00008941; -define exported symbol HalSsiReadRtl8195a = 0x000089b9; -define exported symbol HalSsiGetRxFifoLevelRtl8195a = 0x00008a2d; -define exported symbol HalSsiGetTxFifoLevelRtl8195a = 0x00008aa5; -define exported symbol HalSsiGetStatusRtl8195a = 0x00008b1d; -define exported symbol HalSsiWriteableRtl8195a = 0x00008b91; -define exported symbol HalSsiReadableRtl8195a = 0x00008c09; -define exported symbol HalSsiBusyRtl8195a = 0x00008c81; -define exported symbol HalSsiReadInterruptRtl8195a = 0x00008cf9; -define exported symbol HalSsiWriteInterruptRtl8195a = 0x00008efd; -define exported symbol HalSsiSetSlaveEnableRegisterRtl8195a = 0x00009009; -define exported symbol HalSsiGetInterruptStatusRtl8195a = 0x000090d9; -define exported symbol HalSsiInterruptEnableRtl8195a = 0x0000914d; -define exported symbol HalSsiInterruptDisableRtl8195a = 0x00009299; -define exported symbol HalSsiGetRawInterruptStatusRtl8195a = 0x000093e9; -define exported symbol HalSsiGetSlaveEnableRegisterRtl8195a = 0x0000945d; -define exported symbol HalSsiInitRtl8195a = 0x000094d1; -define exported symbol _SsiReadInterrupt = 0x00009ba5; -define exported symbol _SsiWriteInterrupt = 0x00009db1; -define exported symbol _SsiIrqHandle = 0x00009eb1; -define exported symbol HalI2CWrite32 = 0x0000a061; -define exported symbol HalI2CRead32 = 0x0000a09d; -define exported symbol HalI2CDeInit8195a = 0x0000a0dd; -define exported symbol HalI2CSendRtl8195a = 0x0000a1f1; -define exported symbol HalI2CReceiveRtl8195a = 0x0000a25d; -define exported symbol HalI2CEnableRtl8195a = 0x0000a271; -define exported symbol HalI2CIntrCtrl8195a = 0x0000a389; -define exported symbol HalI2CReadRegRtl8195a = 0x0000a3a1; -define exported symbol HalI2CWriteRegRtl8195a = 0x0000a3b1; -define exported symbol HalI2CSetCLKRtl8195a = 0x0000a3c5; -define exported symbol HalI2CMassSendRtl8195a = 0x0000a6e9; -define exported symbol HalI2CClrIntrRtl8195a = 0x0000a749; -define exported symbol HalI2CClrAllIntrRtl8195a = 0x0000a761; -define exported symbol HalI2CInit8195a = 0x0000a775; -define exported symbol HalI2CDMACtrl8195a = 0x0000aa31; -define exported symbol RtkI2CIoCtrl = 0x0000aa61; -define exported symbol RtkI2CPowerCtrl = 0x0000aa65; -define exported symbol HalI2COpInit = 0x0000aa69; -define exported symbol I2CIsTimeout = 0x0000ac65; -define exported symbol I2CTXGDMAISRHandle = 0x0000b435; -define exported symbol I2CRXGDMAISRHandle = 0x0000b4c1; -define exported symbol RtkI2CIrqInit = 0x0000b54d; -define exported symbol RtkI2CIrqDeInit = 0x0000b611; -define exported symbol RtkI2CPinMuxInit = 0x0000b675; -define exported symbol RtkI2CPinMuxDeInit = 0x0000b7c9; -define exported symbol RtkI2CDMAInit = 0x0000b955; -define exported symbol RtkI2CInit = 0x0000bc95; -define exported symbol RtkI2CDMADeInit = 0x0000bdad; -define exported symbol RtkI2CDeInit = 0x0000be4d; -define exported symbol RtkI2CSendUserAddr = 0x0000bee5; -define exported symbol RtkI2CSend = 0x0000c07d; -define exported symbol RtkI2CLoadDefault = 0x0000ce51; -define exported symbol RtkSalI2COpInit = 0x0000cf21; -define exported symbol HalI2SWrite32 = 0x0000cf65; -define exported symbol HalI2SRead32 = 0x0000cf85; -define exported symbol HalI2SDeInitRtl8195a = 0x0000cfa9; -define exported symbol HalI2STxRtl8195a = 0x0000cfc9; -define exported symbol HalI2SRxRtl8195a = 0x0000d011; -define exported symbol HalI2SEnableRtl8195a = 0x0000d05d; -define exported symbol HalI2SIntrCtrlRtl8195a = 0x0000d0b1; -define exported symbol HalI2SReadRegRtl8195a = 0x0000d0d1; -define exported symbol HalI2SClrIntrRtl8195a = 0x0000d0dd; -define exported symbol HalI2SClrAllIntrRtl8195a = 0x0000d0fd; -define exported symbol HalI2SInitRtl8195a = 0x0000d11d; -define exported symbol GPIO_GetIPPinName_8195a = 0x0000d2e5; -define exported symbol GPIO_GetChipPinName_8195a = 0x0000d331; -define exported symbol GPIO_PullCtrl_8195a = 0x0000d39d; -define exported symbol GPIO_FuncOn_8195a = 0x0000d421; -define exported symbol GPIO_FuncOff_8195a = 0x0000d481; -define exported symbol GPIO_Int_Mask_8195a = 0x0000d4e9; -define exported symbol GPIO_Int_SetType_8195a = 0x0000d511; -define exported symbol HAL_GPIO_IrqHandler_8195a = 0x0000d5fd; -define exported symbol HAL_GPIO_MbedIrqHandler_8195a = 0x0000d645; -define exported symbol HAL_GPIO_UserIrqHandler_8195a = 0x0000d6a1; -define exported symbol HAL_GPIO_IntCtrl_8195a = 0x0000d6cd; -define exported symbol HAL_GPIO_Init_8195a = 0x0000d805; -define exported symbol HAL_GPIO_DeInit_8195a = 0x0000dac1; -define exported symbol HAL_GPIO_ReadPin_8195a = 0x0000dbd1; -define exported symbol HAL_GPIO_WritePin_8195a = 0x0000dc91; -define exported symbol HAL_GPIO_RegIrq_8195a = 0x0000ddad; -define exported symbol HAL_GPIO_UnRegIrq_8195a = 0x0000ddf5; -define exported symbol HAL_GPIO_UserRegIrq_8195a = 0x0000de15; -define exported symbol HAL_GPIO_UserUnRegIrq_8195a = 0x0000def9; -define exported symbol HAL_GPIO_MaskIrq_8195a = 0x0000dfc1; -define exported symbol HAL_GPIO_UnMaskIrq_8195a = 0x0000e061; -define exported symbol HAL_GPIO_IntDebounce_8195a = 0x0000e101; -define exported symbol HAL_GPIO_GetIPPinName_8195a = 0x0000e1c1; -define exported symbol HAL_GPIO_PullCtrl_8195a = 0x0000e1c9; -define exported symbol DumpForOneBytes = 0x0000e259; -define exported symbol CmdRomHelp = 0x0000e419; -define exported symbol CmdWriteWord = 0x0000e491; -define exported symbol CmdDumpHelfWord = 0x0000e505; -define exported symbol CmdDumpWord = 0x0000e5f1; -define exported symbol CmdDumpByte = 0x0000e6f5; -define exported symbol CmdSpiFlashTool = 0x0000e751; -define exported symbol GetRomCmdNum = 0x0000e7a9; -define exported symbol CmdWriteByte = 0x0000e7ad; -define exported symbol Isspace = 0x0000e7ed; -define exported symbol Strtoul = 0x0000e801; -define exported symbol ArrayInitialize = 0x0000e8b1; -define exported symbol GetArgc = 0x0000e8c9; -define exported symbol GetArgv = 0x0000e8f9; -define exported symbol UartLogCmdExecute = 0x0000e95d; -define exported symbol UartLogShowBackSpace = 0x0000e9fd; -define exported symbol UartLogRecallOldCmd = 0x0000ea39; -define exported symbol UartLogHistoryCmd = 0x0000ea71; -define exported symbol UartLogCmdChk = 0x0000eadd; -define exported symbol UartLogIrqHandle = 0x0000ebf5; -define exported symbol RtlConsolInit = 0x0000ecc5; -define exported symbol RtlConsolTaskRom = 0x0000ed49; -define exported symbol RtlExitConsol = 0x0000ed79; -define exported symbol RtlConsolRom = 0x0000edcd; -define exported symbol HalTimerOpInit = 0x0000ee0d; -define exported symbol HalTimerIrq2To7Handle = 0x0000ee59; -define exported symbol HalGetTimerIdRtl8195a = 0x0000ef09; -define exported symbol HalTimerInitRtl8195a = 0x0000ef3d; -define exported symbol HalTimerDisRtl8195a = 0x0000f069; -define exported symbol HalTimerEnRtl8195a = 0x0000f089; -define exported symbol HalTimerReadCountRtl8195a = 0x0000f0a9; -define exported symbol HalTimerIrqClearRtl8195a = 0x0000f0bd; -define exported symbol HalTimerDumpRegRtl8195a = 0x0000f0d1; -define exported symbol VSprintf = 0x0000f129; -define exported symbol DiagPrintf = 0x0000f39d; -define exported symbol DiagSPrintf = 0x0000f3b9; -define exported symbol DiagSnPrintf = 0x0000f3d1; -define exported symbol prvDiagPrintf = 0x0000f3ed; -define exported symbol prvDiagSPrintf = 0x0000f40d; -define exported symbol _memcmp = 0x0000f429; -define exported symbol __memcmp = 0x0000f429; -define exported symbol _memcpy = 0x0000f465; -define exported symbol __memcpy = 0x0000f465; -define exported symbol _memset = 0x0000f511; -define exported symbol __memset = 0x0000f511; -define exported symbol Rand = 0x0000f585; -define exported symbol _strncpy = 0x0000f60d; -define exported symbol __strncpy = 0x0000f60d; -define exported symbol _strcpy = 0x0000f629; -define exported symbol __strcpy = 0x0000f629; -define exported symbol prvStrCpy = 0x0000f639; -define exported symbol _strlen = 0x0000f651; -define exported symbol __strlen = 0x0000f651; -define exported symbol _strnlen = 0x0000f669; -define exported symbol __strnlen = 0x0000f669; -define exported symbol prvStrLen = 0x0000f699; -define exported symbol _strcmp = 0x0000f6b1; -define exported symbol __strcmp = 0x0000f6b1; -define exported symbol _strncmp = 0x0000f6d1; -define exported symbol __strncmp = 0x0000f6d1; -define exported symbol prvStrCmp = 0x0000f719; -define exported symbol StrUpr = 0x0000f749; -define exported symbol prvAtoi = 0x0000f769; -define exported symbol prvStrStr = 0x0000f7bd; -define exported symbol _strsep = 0x0000f7d5; -define exported symbol __strsep = 0x0000f7d5; -define exported symbol skip_spaces = 0x0000f815; -define exported symbol skip_atoi = 0x0000f831; -define exported symbol _parse_integer_fixup_radix = 0x0000f869; -define exported symbol _parse_integer = 0x0000f8bd; -define exported symbol __strtoull = 0x0000f915; -define exported symbol __strtoll = 0x0000f945; -define exported symbol __strtoul = 0x0000f965; -define exported symbol __strtol = 0x0000f96d; -define exported symbol simple_strtoull = 0x0000f915; -define exported symbol simple_strtoll = 0x0000f945; -define exported symbol simple_strtoul = 0x0000f965; -define exported symbol simple_strtol = 0x0000f96d; -define exported symbol __vsscanf = 0x0000f985; -define exported symbol __sscanf = 0x0000ff71; -define exported symbol div_u64 = 0x0000ff91; -define exported symbol div_s64 = 0x0000ff99; -define exported symbol div_u64_rem = 0x0000ffa1; -define exported symbol div_s64_rem = 0x0000ffb1; -define exported symbol __strpbrk = 0x0000ffc1; -define exported symbol __strchr = 0x0000ffed; -define exported symbol aes_set_key = 0x00010005; -define exported symbol aes_encrypt = 0x000103d1; -define exported symbol aes_decrypt = 0x000114a5; -define exported symbol AES_WRAP = 0x000125c9; -define exported symbol AES_UnWRAP = 0x00012701; -define exported symbol crc32_get = 0x00012861; -define exported symbol arc4_byte = 0x00012895; -define exported symbol rt_arc4_init = 0x000128bd; -define exported symbol rt_arc4_crypt = 0x00012901; -define exported symbol rt_md5_init = 0x000131c1; -define exported symbol rt_md5_append = 0x000131f5; -define exported symbol rt_md5_final = 0x0001327d; -define exported symbol rt_md5_hmac = 0x000132d5; -define exported symbol rtw_get_bit_value_from_ieee_value = 0x00013449; -define exported symbol rtw_is_cckrates_included = 0x00013475; -define exported symbol rtw_is_cckratesonly_included = 0x000134b5; -define exported symbol rtw_check_network_type = 0x000134dd; -define exported symbol rtw_set_fixed_ie = 0x0001350d; -define exported symbol rtw_set_ie = 0x0001352d; -define exported symbol rtw_get_ie = 0x0001355d; -define exported symbol rtw_set_supported_rate = 0x00013591; -define exported symbol rtw_get_rateset_len = 0x00013611; -define exported symbol rtw_get_wpa_ie = 0x0001362d; -define exported symbol rtw_get_wpa2_ie = 0x000136c9; -define exported symbol rtw_get_wpa_cipher_suite = 0x00013701; -define exported symbol rtw_get_wpa2_cipher_suite = 0x00013769; -define exported symbol rtw_parse_wpa_ie = 0x000137d1; -define exported symbol rtw_parse_wpa2_ie = 0x000138ad; -define exported symbol rtw_get_sec_ie = 0x00013965; -define exported symbol rtw_get_wps_ie = 0x00013a15; -define exported symbol rtw_get_wps_attr = 0x00013a99; -define exported symbol rtw_get_wps_attr_content = 0x00013b49; -define exported symbol rtw_ieee802_11_parse_elems = 0x00013b91; -define exported symbol str_2char2num = 0x00013d9d; -define exported symbol key_2char2num = 0x00013db9; -define exported symbol convert_ip_addr = 0x00013dd1; -define exported symbol rom_psk_PasswordHash = 0x00013e9d; -define exported symbol rom_psk_CalcGTK = 0x00013ed5; -define exported symbol rom_psk_CalcPTK = 0x00013f69; -define exported symbol wep_80211_encrypt = 0x00014295; -define exported symbol wep_80211_decrypt = 0x000142f5; -define exported symbol tkip_micappendbyte = 0x00014389; -define exported symbol rtw_secmicsetkey = 0x000143d9; -define exported symbol rtw_secmicappend = 0x00014419; -define exported symbol rtw_secgetmic = 0x00014435; -define exported symbol rtw_seccalctkipmic = 0x0001449d; -define exported symbol tkip_phase1 = 0x000145a5; -define exported symbol tkip_phase2 = 0x00014725; -define exported symbol tkip_80211_encrypt = 0x00014941; -define exported symbol tkip_80211_decrypt = 0x000149d5; -define exported symbol aes1_encrypt = 0x00014a8d; -define exported symbol aesccmp_construct_mic_iv = 0x00014c65; -define exported symbol aesccmp_construct_mic_header1 = 0x00014ccd; -define exported symbol aesccmp_construct_mic_header2 = 0x00014d21; -define exported symbol aesccmp_construct_ctr_preload = 0x00014db5; -define exported symbol aes_80211_encrypt = 0x00014e29; -define exported symbol aes_80211_decrypt = 0x000151ad; -define exported symbol _sha1_process_message_block = 0x000155b9; -define exported symbol _sha1_pad_message = 0x00015749; -define exported symbol rt_sha1_init = 0x000157e5; -define exported symbol rt_sha1_update = 0x00015831; -define exported symbol rt_sha1_finish = 0x000158a9; -define exported symbol rt_hmac_sha1 = 0x00015909; -define exported symbol rom_aes_128_cbc_encrypt = 0x00015a65; -define exported symbol rom_aes_128_cbc_decrypt = 0x00015ae1; -define exported symbol rom_rijndaelKeySetupEnc = 0x00015b5d; -define exported symbol rom_aes_decrypt_init = 0x00015c39; -define exported symbol rom_aes_internal_decrypt = 0x00015d15; -define exported symbol rom_aes_decrypt_deinit = 0x00016071; -define exported symbol rom_aes_encrypt_init = 0x00016085; -define exported symbol rom_aes_internal_encrypt = 0x0001609d; -define exported symbol rom_aes_encrypt_deinit = 0x00016451; -define exported symbol bignum_init = 0x00017b35; -define exported symbol bignum_deinit = 0x00017b61; -define exported symbol bignum_get_unsigned_bin_len = 0x00017b81; -define exported symbol bignum_get_unsigned_bin = 0x00017b85; -define exported symbol bignum_set_unsigned_bin = 0x00017c21; -define exported symbol bignum_cmp = 0x00017cd1; -define exported symbol bignum_cmp_d = 0x00017cd5; -define exported symbol bignum_add = 0x00017cfd; -define exported symbol bignum_sub = 0x00017d0d; -define exported symbol bignum_mul = 0x00017d1d; -define exported symbol bignum_exptmod = 0x00017d2d; -define exported symbol WPS_realloc = 0x00017d51; -define exported symbol os_zalloc = 0x00017d99; -define exported symbol rom_hmac_sha256_vector = 0x00017dc1; -define exported symbol rom_hmac_sha256 = 0x00017ebd; -define exported symbol rom_sha256_vector = 0x00018009; -define exported symbol phy_CalculateBitShift = 0x00018221; -define exported symbol PHY_SetBBReg_8195A = 0x00018239; -define exported symbol PHY_QueryBBReg_8195A = 0x00018279; -define exported symbol ROM_odm_QueryRxPwrPercentage = 0x0001829d; -define exported symbol ROM_odm_EVMdbToPercentage = 0x000182bd; -define exported symbol ROM_odm_SignalScaleMapping_8195A = 0x000182e5; -define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x000183cd; -define exported symbol ROM_odm_SetEDCCAThreshold = 0x00018721; -define exported symbol ROM_odm_SetTRxMux = 0x00018749; -define exported symbol ROM_odm_SetCrystalCap = 0x00018771; -define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x000187d5; -define exported symbol ROM_ODM_CfoTrackingReset = 0x000187e9; -define exported symbol ROM_odm_CfoTrackingFlow = 0x00018811; -define exported symbol curve25519_donna = 0x0001965d; -define exported symbol aes_test_alignment_detection = 0x0001a391; -define exported symbol aes_mode_reset = 0x0001a3ed; -define exported symbol aes_ecb_encrypt = 0x0001a3f9; -define exported symbol aes_ecb_decrypt = 0x0001a431; -define exported symbol aes_cbc_encrypt = 0x0001a469; -define exported symbol aes_cbc_decrypt = 0x0001a579; -define exported symbol aes_cfb_encrypt = 0x0001a701; -define exported symbol aes_cfb_decrypt = 0x0001a9e5; -define exported symbol aes_ofb_crypt = 0x0001acc9; -define exported symbol aes_ctr_crypt = 0x0001af7d; -define exported symbol aes_encrypt_key128 = 0x0001b289; -define exported symbol aes_encrypt_key192 = 0x0001b2a5; -define exported symbol aes_encrypt_key256 = 0x0001b2c1; -define exported symbol aes_encrypt_key = 0x0001b2e1; -define exported symbol aes_decrypt_key128 = 0x0001b351; -define exported symbol aes_decrypt_key192 = 0x0001b36d; -define exported symbol aes_decrypt_key256 = 0x0001b389; -define exported symbol aes_decrypt_key = 0x0001b3a9; -define exported symbol aes_init = 0x0001b419; -define exported symbol CRYPTO_chacha_20 = 0x0001b41d; -define exported symbol CRYPTO_poly1305_init = 0x0001bc25; -define exported symbol CRYPTO_poly1305_update = 0x0001bd09; -define exported symbol CRYPTO_poly1305_finish = 0x0001bd8d; -define exported symbol rom_sha512_starts = 0x0001ceb5; -define exported symbol rom_sha512_update = 0x0001d009; -define exported symbol rom_sha512_finish = 0x0001d011; -define exported symbol rom_sha512 = 0x0001d261; -define exported symbol rom_sha512_hmac_starts = 0x0001d299; -define exported symbol rom_sha512_hmac_update = 0x0001d35d; -define exported symbol rom_sha512_hmac_finish = 0x0001d365; -define exported symbol rom_sha512_hmac_reset = 0x0001d3b5; -define exported symbol rom_sha512_hmac = 0x0001d3d1; -define exported symbol rom_sha512_hkdf = 0x0001d40d; -define exported symbol rom_ed25519_gen_keypair = 0x0001d501; -define exported symbol rom_ed25519_gen_signature = 0x0001d505; -define exported symbol rom_ed25519_verify_signature = 0x0001d51d; -define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x0001d521; -define exported symbol rom_ed25519_crypto_sign_detached = 0x0001d579; -define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x0001d655; -define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x0001f86d; -define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x0001fc35; -define exported symbol rom_ed25519_ge_p3_tobytes = 0x000207d5; -define exported symbol rom_ed25519_ge_scalarmult_base = 0x00020821; -define exported symbol rom_ed25519_ge_tobytes = 0x000209e1; -define exported symbol rom_ed25519_sc_muladd = 0x00020a2d; -define exported symbol rom_ed25519_sc_reduce = 0x0002603d; -define exported symbol __rtl_memchr_v1_00 = 0x00028a4d; -define exported symbol __rtl_memcmp_v1_00 = 0x00028ae1; -define exported symbol __rtl_memcpy_v1_00 = 0x00028b49; -define exported symbol __rtl_memmove_v1_00 = 0x00028bed; -define exported symbol __rtl_memset_v1_00 = 0x00028cb5; -define exported symbol __rtl_strcat_v1_00 = 0x00028d49; -define exported symbol __rtl_strchr_v1_00 = 0x00028d91; -define exported symbol __rtl_strcmp_v1_00 = 0x00028e55; -define exported symbol __rtl_strcpy_v1_00 = 0x00028ec9; -define exported symbol __rtl_strlen_v1_00 = 0x00028f15; -define exported symbol __rtl_strncat_v1_00 = 0x00028f69; -define exported symbol __rtl_strncmp_v1_00 = 0x00028fc5; -define exported symbol __rtl_strncpy_v1_00 = 0x0002907d; -define exported symbol __rtl_strstr_v1_00 = 0x000293cd; -define exported symbol __rtl_strsep_v1_00 = 0x0002960d; -define exported symbol __rtl_strtok_v1_00 = 0x00029619; -define exported symbol __rtl__strtok_r_v1_00 = 0x0002962d; -define exported symbol __rtl_strtok_r_v1_00 = 0x00029691; -define exported symbol __rtl_close_v1_00 = 0x00029699; -define exported symbol __rtl_fstat_v1_00 = 0x000296ad; -define exported symbol __rtl_isatty_v1_00 = 0x000296c1; -define exported symbol __rtl_lseek_v1_00 = 0x000296d5; -define exported symbol __rtl_open_v1_00 = 0x000296e9; -define exported symbol __rtl_read_v1_00 = 0x000296fd; -define exported symbol __rtl_write_v1_00 = 0x00029711; -define exported symbol __rtl_sbrk_v1_00 = 0x00029725; -define exported symbol __rtl_ltoa_v1_00 = 0x000297bd; -define exported symbol __rtl_ultoa_v1_00 = 0x00029855; -define exported symbol __rtl_dtoi_v1_00 = 0x000298c5; -define exported symbol __rtl_dtoi64_v1_00 = 0x00029945; -define exported symbol __rtl_dtoui_v1_00 = 0x000299dd; -define exported symbol __rtl_ftol_v1_00 = 0x000299e5; -define exported symbol __rtl_itof_v1_00 = 0x00029a51; -define exported symbol __rtl_itod_v1_00 = 0x00029ae9; -define exported symbol __rtl_i64tod_v1_00 = 0x00029b79; -define exported symbol __rtl_uitod_v1_00 = 0x00029c55; -define exported symbol __rtl_ftod_v1_00 = 0x00029d2d; -define exported symbol __rtl_dtof_v1_00 = 0x00029de9; -define exported symbol __rtl_uitof_v1_00 = 0x00029e89; -define exported symbol __rtl_fadd_v1_00 = 0x00029f65; -define exported symbol __rtl_fsub_v1_00 = 0x0002a261; -define exported symbol __rtl_fmul_v1_00 = 0x0002a559; -define exported symbol __rtl_fdiv_v1_00 = 0x0002a695; -define exported symbol __rtl_dadd_v1_00 = 0x0002a825; -define exported symbol __rtl_dsub_v1_00 = 0x0002aed9; -define exported symbol __rtl_dmul_v1_00 = 0x0002b555; -define exported symbol __rtl_ddiv_v1_00 = 0x0002b8ad; -define exported symbol __rtl_dcmpeq_v1_00 = 0x0002be4d; -define exported symbol __rtl_dcmplt_v1_00 = 0x0002bebd; -define exported symbol __rtl_dcmpgt_v1_00 = 0x0002bf51; -define exported symbol __rtl_dcmple_v1_00 = 0x0002c049; -define exported symbol __rtl_fcmplt_v1_00 = 0x0002c139; -define exported symbol __rtl_fcmpgt_v1_00 = 0x0002c195; -define exported symbol __rtl_cos_f32_v1_00 = 0x0002c229; -define exported symbol __rtl_sin_f32_v1_00 = 0x0002c435; -define exported symbol __rtl_fabs_v1_00 = 0x0002c639; -define exported symbol __rtl_fabsf_v1_00 = 0x0002c641; -define exported symbol __rtl_dtoa_r_v1_00 = 0x0002c77d; -define exported symbol __rom_mallocr_init_v1_00 = 0x0002d7d1; -define exported symbol __rtl_free_r_v1_00 = 0x0002d841; -define exported symbol __rtl_malloc_r_v1_00 = 0x0002da31; -define exported symbol __rtl_realloc_r_v1_00 = 0x0002df55; -define exported symbol __rtl_memalign_r_v1_00 = 0x0002e331; -define exported symbol __rtl_valloc_r_v1_00 = 0x0002e421; -define exported symbol __rtl_pvalloc_r_v1_00 = 0x0002e42d; -define exported symbol __rtl_calloc_r_v1_00 = 0x0002e441; -define exported symbol __rtl_cfree_r_v1_00 = 0x0002e4a9; -define exported symbol __rtl_Balloc_v1_00 = 0x0002e515; -define exported symbol __rtl_Bfree_v1_00 = 0x0002e571; -define exported symbol __rtl_i2b_v1_00 = 0x0002e585; -define exported symbol __rtl_multadd_v1_00 = 0x0002e599; -define exported symbol __rtl_mult_v1_00 = 0x0002e629; -define exported symbol __rtl_pow5mult_v1_00 = 0x0002e769; -define exported symbol __rtl_hi0bits_v1_00 = 0x0002e809; -define exported symbol __rtl_d2b_v1_00 = 0x0002e845; -define exported symbol __rtl_lshift_v1_00 = 0x0002e901; -define exported symbol __rtl_cmp_v1_00 = 0x0002e9bd; -define exported symbol __rtl_diff_v1_00 = 0x0002ea01; -define exported symbol __rtl_sread_v1_00 = 0x0002eae9; -define exported symbol __rtl_seofread_v1_00 = 0x0002eb39; -define exported symbol __rtl_swrite_v1_00 = 0x0002eb3d; -define exported symbol __rtl_sseek_v1_00 = 0x0002ebc1; -define exported symbol __rtl_sclose_v1_00 = 0x0002ec11; -define exported symbol __rtl_sbrk_r_v1_00 = 0x0002ec41; -define exported symbol __rtl_fflush_r_v1_00 = 0x0002ef8d; -define exported symbol __rtl_vfprintf_r_v1_00 = 0x0002f661; -define exported symbol __rtl_fpclassifyd = 0x00030c15; -define exported symbol CpkClkTbl = 0x00030c68; -define exported symbol ROM_IMG1_VALID_PATTEN = 0x00030c80; -define exported symbol SpicCalibrationPattern = 0x00030c88; -define exported symbol SpicInitCPUCLK = 0x00030c98; -define exported symbol BAUDRATE = 0x00030ca8; -define exported symbol OVSR = 0x00030d1c; -define exported symbol DIV = 0x00030d90; -define exported symbol OVSR_ADJ = 0x00030e04; -define exported symbol __AES_rcon = 0x00030e78; -define exported symbol __AES_Te4 = 0x00030ea0; -define exported symbol I2CDmaChNo = 0x000312a0; -define exported symbol _GPIO_PinMap_Chip2IP_8195a = 0x000312b4; -define exported symbol _GPIO_PinMap_PullCtrl_8195a = 0x0003136c; -define exported symbol _GPIO_SWPORT_DDR_TBL = 0x00031594; -define exported symbol _GPIO_EXT_PORT_TBL = 0x00031598; -define exported symbol _GPIO_SWPORT_DR_TBL = 0x0003159c; -define exported symbol UartLogRomCmdTable = 0x000316a0; -define exported symbol _HalRuartOp = 0x00031700; -define exported symbol _HalGdmaOp = 0x00031760; -define exported symbol RTW_WPA_OUI_TYPE = 0x0003540c; -define exported symbol WPA_CIPHER_SUITE_NONE = 0x00035410; -define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x00035414; -define exported symbol WPA_CIPHER_SUITE_TKIP = 0x00035418; -define exported symbol WPA_CIPHER_SUITE_CCMP = 0x0003541c; -define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x00035420; -define exported symbol RSN_CIPHER_SUITE_NONE = 0x00035424; -define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x00035428; -define exported symbol RSN_CIPHER_SUITE_TKIP = 0x0003542c; -define exported symbol RSN_CIPHER_SUITE_CCMP = 0x00035430; -define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x00035434; -define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x00035444; -define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x00035448; -define exported symbol RSN_VERSION_BSD = 0x0003544c; -define exported symbol rom_wps_Te0 = 0x00035988; -define exported symbol rom_wps_rcons = 0x00035d88; -define exported symbol rom_wps_Td4s = 0x00035d94; -define exported symbol rom_wps_Td0 = 0x00035e94; -define exported symbol __rom_b_cut_end__ = 0x0004467c; -define exported symbol __rom_c_cut_text_start__ = 0x0004467c; -define exported symbol HalInitPlatformLogUartV02 = 0x0004467d; -define exported symbol HalReInitPlatformLogUartV02 = 0x0004471d; -define exported symbol HalInitPlatformTimerV02 = 0x00044755; -define exported symbol HalShowBuildInfoV02 = 0x000447cd; -define exported symbol SpicReleaseDeepPowerDownFlashRtl8195A = 0x00044831; -define exported symbol HalSpiInitV02 = 0x0004488d; -define exported symbol HalBootFlowV02 = 0x00044a29; -define exported symbol HalInitialROMCodeGlobalVarV02 = 0x00044ae5; -define exported symbol HalResetVsrV02 = 0x00044b41; -define exported symbol HalI2CSendRtl8195aV02 = 0x00044ce1; -define exported symbol HalI2CSetCLKRtl8195aV02 = 0x00044d59; -define exported symbol RtkI2CSendV02 = 0x0004508d; -define exported symbol RtkI2CReceiveV02 = 0x000459a1; -define exported symbol HalI2COpInitV02 = 0x000461ed; -define exported symbol I2CISRHandleV02 = 0x000463e9; -define exported symbol RtkSalI2COpInitV02 = 0x00046be1; -define exported symbol SpicLoadInitParaFromClockRtl8195AV02 = 0x00046c25; -define exported symbol SpiFlashAppV02 = 0x00046c85; -define exported symbol SpicInitRtl8195AV02 = 0x00046dc5; -define exported symbol SpicEraseFlashRtl8195AV02 = 0x00046ea1; -define exported symbol HalTimerIrq2To7HandleV02 = 0x00046f5d; -define exported symbol HalTimerIrqRegisterRtl8195aV02 = 0x00046fe1; -define exported symbol HalTimerInitRtl8195aV02 = 0x0004706d; -define exported symbol HalTimerReadCountRtl8195aV02 = 0x000471b5; -define exported symbol HalTimerReLoadRtl8195aV02 = 0x000471d1; -define exported symbol HalTimerIrqUnRegisterRtl8195aV02 = 0x0004722d; -define exported symbol HalTimerDeInitRtl8195aV02 = 0x000472c1; -define exported symbol HalTimerOpInitV02 = 0x000472f9; -define exported symbol GPIO_LockV02 = 0x00047345; -define exported symbol GPIO_UnLockV02 = 0x00047379; -define exported symbol GPIO_Int_Clear_8195aV02 = 0x000473a5; -define exported symbol HAL_GPIO_IntCtrl_8195aV02 = 0x000473b5; -define exported symbol FindElementIndexV02 = 0x00047541; -define exported symbol HalRuartInitRtl8195aV02 = 0x0004756d; -define exported symbol DramInit_rom = 0x00047619; -define exported symbol ChangeRandSeed_rom = 0x00047979; -define exported symbol Sdr_Rand2_rom = 0x00047985; -define exported symbol MemTest_rom = 0x000479dd; -define exported symbol SdrCalibration_rom = 0x00047a45; -define exported symbol SdrControllerInit_rom = 0x00047d99; -define exported symbol SDIO_EnterCritical = 0x00047e39; -define exported symbol SDIO_ExitCritical = 0x00047e85; -define exported symbol SDIO_IRQ_Handler_Rom = 0x00047ec5; -define exported symbol SDIO_Interrupt_Init_Rom = 0x00047f31; -define exported symbol SDIO_Device_Init_Rom = 0x00047f81; -define exported symbol SDIO_Interrupt_DeInit_Rom = 0x00048215; -define exported symbol SDIO_Device_DeInit_Rom = 0x00048255; -define exported symbol SDIO_Enable_Interrupt_Rom = 0x00048281; -define exported symbol SDIO_Disable_Interrupt_Rom = 0x000482a1; -define exported symbol SDIO_Clear_ISR_Rom = 0x000482c1; -define exported symbol SDIO_Alloc_Rx_Pkt_Rom = 0x000482d9; -define exported symbol SDIO_Free_Rx_Pkt_Rom = 0x00048331; -define exported symbol SDIO_Recycle_Rx_BD_Rom = 0x00048355; -define exported symbol SDIO_RX_IRQ_Handler_BH_Rom = 0x000484f1; -define exported symbol SDIO_RxTask_Rom = 0x0004851d; -define exported symbol SDIO_Process_H2C_IOMsg_Rom = 0x0004856d; -define exported symbol SDIO_Send_C2H_IOMsg_Rom = 0x0004859d; -define exported symbol SDIO_Process_RPWM_Rom = 0x000485b5; -define exported symbol SDIO_Reset_Cmd_Rom = 0x000485e9; -define exported symbol SDIO_Rx_Data_Transaction_Rom = 0x00048611; -define exported symbol SDIO_Send_C2H_PktMsg_Rom = 0x00048829; -define exported symbol SDIO_Register_Tx_Callback_Rom = 0x000488f5; -define exported symbol SDIO_ReadMem_Rom = 0x000488fd; -define exported symbol SDIO_WriteMem_Rom = 0x000489a9; -define exported symbol SDIO_SetMem_Rom = 0x00048a69; -define exported symbol SDIO_TX_Pkt_Handle_Rom = 0x00048b29; -define exported symbol SDIO_TX_FIFO_DataReady_Rom = 0x00048c69; -define exported symbol SDIO_IRQ_Handler_BH_Rom = 0x00048d95; -define exported symbol SDIO_TxTask_Rom = 0x00048e9d; -define exported symbol SDIO_TaskUp_Rom = 0x00048eed; -define exported symbol SDIO_Boot_Up = 0x00048f55; -define exported symbol __rom_c_cut_text_end__ = 0x00049070; -define exported symbol __rom_c_cut_rodata_start__ = 0x00049070; -define exported symbol BAUDRATE_v02 = 0x00049070; -define exported symbol OVSR_v02 = 0x000490fc; -define exported symbol DIV_v02 = 0x00049188; -define exported symbol OVSR_ADJ_v02 = 0x00049214; -define exported symbol SdrDramInfo_rom = 0x000492a0; -define exported symbol SdrDramTiming_rom = 0x000492b4; -define exported symbol NewVectorTable = 0x10000000; -define exported symbol UserIrqFunTable = 0x10000100; -define exported symbol UserIrqDataTable = 0x10000200; -define exported symbol __rom_bss_start__ = 0x10000300; -define exported symbol CfgSysDebugWarn = 0x10000300; -define exported symbol CfgSysDebugInfo = 0x10000304; -define exported symbol CfgSysDebugErr = 0x10000308; -define exported symbol ConfigDebugWarn = 0x1000030c; -define exported symbol ConfigDebugInfo = 0x10000310; -define exported symbol ConfigDebugErr = 0x10000314; -define exported symbol HalTimerOp = 0x10000318; -define exported symbol GPIOState = 0x10000334; -define exported symbol gTimerRecord = 0x1000034c; -define exported symbol SSI_DBG_CONFIG = 0x10000350; -define exported symbol _pHAL_Gpio_Adapter = 0x10000354; -define exported symbol Timer2To7VectorTable = 0x10000358; -define exported symbol rom_wlan_ram_map = 0x100006d4; -define exported symbol ROMInfo = 0x10000720; -define exported symbol rom_libgloss_ram_map = 0x10000760; -define exported symbol __rtl_errno = 0x10000bc4; -define exported symbol __rom_bss_end__ = 0x10000bc8; -define exported symbol __ram_table_start__ = 0x10000bc8; -define exported symbol _rtl_impure_ptr = 0x10001c60; -define exported symbol FalseAlmCnt = 0x100006d4; -define exported symbol DM_CfoTrack = 0x1000072c; diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_startup.S b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_startup.S deleted file mode 100644 index 4e00f35c3db..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_startup.S +++ /dev/null @@ -1,31 +0,0 @@ -; -; Copyright (c) 2017 Realtek Semiconductor Corp. -; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; http://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - - MODULE ?cstartup - - SECTION .text:CODE:NOROOT:REORDER(2) - EXTERN CSTACK$$Limit - EXTERN PLAT_Init - - ; Default image 2 entry - THUMB - PUBWEAK PLAT_Start - -PLAT_Start - LDR SP, =CSTACK$$Limit - LDR R0, =PLAT_Init - BX R0 - - END diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/cmsis.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/cmsis.h deleted file mode 100644 index ab75b339b47..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/cmsis.h +++ /dev/null @@ -1,26 +0,0 @@ -/* mbed Microcontroller Library - * A generic CMSIS include header - ******************************************************************************* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "rtl8195a.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/cmsis_nvic.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/cmsis_nvic.h deleted file mode 100644 index 9aaf7648701..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/cmsis_nvic.h +++ /dev/null @@ -1,36 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM -#define NVIC_ROM_VECTOR_ADDRESS (0x00000000) // Initial vector position at start of ROM - -// CORE: 64 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ... -// Total: 128 vectors = 512 bytes (0x200) to be reserved in RAM -#define NVIC_NUM_VECTORS 128 -#ifndef NVIC_USER_IRQ_OFFSET -#define NVIC_USER_IRQ_OFFSET 64 -#endif - -#include "cmsis.h" - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/diag.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/diag.h deleted file mode 100644 index 0eb6e134d8c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/diag.h +++ /dev/null @@ -1,850 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _DIAG_H_ -#define _DIAG_H_ - -#include "platform_autoconf.h" -#include "basic_types.h" - -#include /* for size_t */ - -extern u32 ConfigDebugErr; -extern u32 ConfigDebugInfo; -extern u32 ConfigDebugWarn; - -extern u32 CfgSysDebugErr; -extern u32 CfgSysDebugInfo; -extern u32 CfgSysDebugWarn; - -#define DBG_ERR_MSG_ON(x) (ConfigDebugErr |= (x)) -#define DBG_WARN_MSG_ON(x) (ConfigDebugWarn |= (x)) -#define DBG_INFO_MSG_ON(x) (ConfigDebugInfo |= (x)) - -#define DBG_ERR_MSG_OFF(x) (ConfigDebugErr &= ~(x)) -#define DBG_WARN_MSG_OFF(x) (ConfigDebugWarn &= ~(x)) -#define DBG_INFO_MSG_OFF(x) (ConfigDebugInfo &= ~(x)) - -// Define debug group -#define _DBG_BOOT_ 0x00000001 -#define _DBG_GDMA_ 0x00000002 -#define _DBG_GPIO_ 0x00000004 -#define _DBG_TIMER_ 0x00000008 -#define _DBG_I2C_ 0x00000010 -#define _DBG_I2S_ 0x00000020 -#define _DBG_MII_ 0x00000040 -#define _DBG_NFC_ 0x00000080 -#define _DBG_PCM_ 0x00000100 -#define _DBG_PWM_ 0x00000200 -#define _DBG_SDIO_ 0x00000400 -#define _DBG_SSI_ 0x00000800 -#define _DBG_SPI_FLASH_ 0x00001000 -#define _DBG_SDR_ 0x00002000 -#define _DBG_UART_ 0x00004000 -#define _DBG_USB_OTG_ 0x00008000 -#define _DBG_USB_CORE_ 0x00010000 -#define _DBG_CRYPTO_ 0x00020000 -#define _DBG_ADC_ 0x00040000 -#define _DBG_DAC_ 0x00080000 - -#define _DBG_MISC_ 0x40000000 -#define _DBG_FAULT_ 0x80000000 - -enum _SYSTEM_DBG_DEFINE_ { - _SYSDBG_MISC_ = 1<<0, - _SYSDBG_MAILBOX_ = 1<<1, - _SYSDBG_TIMER_ = 1<<2 - -}; -typedef uint32_t SYSTEM_DBG; - -extern -_LONG_CALL_ROM_ u32 -DiagPrintf( - IN const char *fmt, ... -); - -u32 -DiagSPrintf( - IN u8 *buf, - IN const char *fmt, ... -); - -int -prvDiagPrintf( - IN const char *fmt, ... -); - -int -prvDiagSPrintf( - IN char *buf, - IN const char *fmt, ... -); - - -#define _DbgDump DiagPrintf - -#define DRIVER_PREFIX "RTL8195A[Driver]: " -#define HAL_PREFIX "RTL8195A[HAL]: " -#define DMA_PREFIX "RTL8195A[DMA]: " -#define SDIO_PREFIX "RTL8195A[SDIO]" -#define MBOX_PREFIX "[OS-MBOX]" -#define TIMER_PREFIX "[OS-TMR]" - -#define BOOT_ERR_PREFIX "[BOOT Err]" -#define BOOT_WARN_PREFIX "[BOOT Wrn]" -#define BOOT_INFO_PREFIX "[BOOT Inf]" - -#define GDMA_ERR_PREFIX "[GDMA Err]" -#define GDMA_WARN_PREFIX "[GDMA Wrn]" -#define GDMA_INFO_PREFIX "[GDMA Inf]" - -#define GPIO_ERR_PREFIX "[GPIO Err]" -#define GPIO_WARN_PREFIX "[GPIO Wrn]" -#define GPIO_INFO_PREFIX "[GPIO Inf]" - -#define TIMER_ERR_PREFIX "[TIMR Err]" -#define TIMER_WARN_PREFIX "[TIMR Wrn]" -#define TIMER_INFO_PREFIX "[TIMR Inf]" - -#define I2C_ERR_PREFIX "[I2C Err]" -#define I2C_WARN_PREFIX "[I2C Wrn]" -#define I2C_INFO_PREFIX "[I2C Inf]" - -#define I2S_ERR_PREFIX "[I2S Err]" -#define I2S_WARN_PREFIX "[I2S Wrn]" -#define I2S_INFO_PREFIX "[I2S Inf]" - -#define MII_ERR_PREFIX "[MII Err]" -#define MII_WARN_PREFIX "[MII Wrn]" -#define MII_INFO_PREFIX "[MII Inf]" - -#define NFC_ERR_PREFIX "[NFC Err]" -#define NFC_WARN_PREFIX "[NFC Wrn]" -#define NFC_INFO_PREFIX "[NFC Inf]" - -#define PCM_ERR_PREFIX "[PCM Err]" -#define PCM_WARN_PREFIX "[PCM Wrn]" -#define PCM_INFO_PREFIX "[PCM Inf]" - -#define PWM_ERR_PREFIX "[PWM Err]" -#define PWM_WARN_PREFIX "[PWM Wrn]" -#define PWM_INFO_PREFIX "[PWM Inf]" - -#define SSI_ERR_PREFIX "[SSI Err]" -#define SSI_WARN_PREFIX "[SSI Wrn]" -#define SSI_INFO_PREFIX "[SSI Inf]" - -#define SDIO_ERR_PREFIX "[SDIO Err]" -#define SDIO_WARN_PREFIX "[SDIO Wrn]" -#define SDIO_INFO_PREFIX "[SDIO Inf]" - -#define SPIF_ERR_PREFIX "[SPIF Err]" -#define SPIF_WARN_PREFIX "[SPIF Wrn]" -#define SPIF_INFO_PREFIX "[SPIF Inf]" - -#define SDR_ERR_PREFIX "[SDR Err]" -#define SDR_WARN_PREFIX "[SDR Wrn]" -#define SDR_INFO_PREFIX "[SDR Inf]" - -#define UART_ERR_PREFIX "[UART Err]" -#define UART_WARN_PREFIX "[UART Wrn]" -#define UART_INFO_PREFIX "[UART Inf]" - -#define USB_ERR_PREFIX "[USB Err]" -#define USB_WARN_PREFIX "[USB Wrn]" -#define USB_INFO_PREFIX "[USB Inf]" - -#define IPSEC_ERR_PREFIX "[CRYP Err]" -#define IPSEC_WARN_PREFIX "[CRYP Wrn]" -#define IPSEC_INFO_PREFIX "[CRYP Inf]" - -#define ADC_ERR_PREFIX "[ADC Err]" -#define ADC_WARN_PREFIX "[ADC Wrn]" -#define ADC_INFO_PREFIX "[ADC Inf]" - -#define DAC_ERR_PREFIX "[DAC Err]" -#define DAC_WARN_PREFIX "[DAC Wrn]" -#define DAC_INFO_PREFIX "[DAC Inf]" - -#define MISC_ERR_PREFIX "[MISC Err]" -#define MISC_WARN_PREFIX "[MISC Wrn]" -#define MISC_INFO_PREFIX "[MISC Inf]" - -#define OTG_ERR_PREFIX "[OTG Err]" -#define OTG_WARN_PREFIX "[OTG Wrn]" -#define OTG_INFO_PREFIX "[OTG Inf]" - -#define OTG_PREFIX "RTL8195A[OTG]: " -#define OTG_PREFIX_LVL "RTL8195A[OTG_LVL_%2x]: " - -//#ifdef -#define CONFIG_DEBUG_ERROR 1 -#define CONFIG_DEBUG_WARN 1 -#define CONFIG_DEBUG_INFO 1 - -#ifndef likely -#define likely(x) (x) -#define unlikely(x) (x) -#endif - -#ifdef CONFIG_DEBUG_LOG - -#if CONFIG_DEBUG_ERROR // if Build-In Debug Error Message - -#define DBG_BOOT_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_BOOT_)) \ - _DbgDump("\r" BOOT_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_GDMA_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_GDMA_)) \ - _DbgDump("\r" GDMA_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_GPIO_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_GPIO_)) \ - _DbgDump("\r" GPIO_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_TIMER_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_TIMER_)) \ - _DbgDump("\r" TIMER_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_I2C_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_I2C_)) \ - _DbgDump("\r" I2C_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_I2S_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_I2S_)) \ - _DbgDump("\r" I2S_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_MII_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_MII_)) \ - _DbgDump("\r" MII_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_NFC_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_NFC_)) \ - _DbgDump("\r" NFC_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_PCM_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_PCM_)) \ - _DbgDump("\r" PCM_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_PWM_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_PWM_)) \ - _DbgDump("\r" PWM_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SSI_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_SSI_)) \ - _DbgDump("\r" SSI_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SDIO_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_SDIO_)) \ - _DbgDump("\r" SDIO_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SPIF_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_SPI_FLASH_)) \ - _DbgDump("\r" SPIF_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SDR_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_SDR_)) \ - _DbgDump("\r" SDR_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_UART_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_UART_)) \ - _DbgDump("\r" UART_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_USBOTG_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_USB_OTG_)) \ - _DbgDump("\r" __VA_ARGS__);\ -}while(0) - -#define DBG_USBCOR_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_USB_CORE_)) \ - _DbgDump("\r" USB_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_CRYPTO_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_CRYPTO_)) \ - _DbgDump("\r" IPSEC_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_ADC_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_ADC_)) \ - _DbgDump("\r" ADC_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_DAC_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_DAC_)) \ - _DbgDump("\r" DAC_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#define MSG_MBOX_ERR(...) do {\ - if (likely(CfgSysDebugErr & _SYSDBG_MAILBOX_)) \ - _DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\ -}while(0) - -#define MSG_TIMER_ERR(...) do {\ - if (likely(CfgSysDebugErr & _SYSDBG_TIMER_)) \ - _DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_8195A_OTG(...) do{\ - if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \ - _DbgDump("\r" OTG_PREFIX __VA_ARGS__);\ - }while(0) - -#define DBG_8195A_OTG_INFO(...) do{\ - if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \ - _DbgDump("\r" OTG_PREFIX __VA_ARGS__);\ - }while(0) - -#define DBG_8195A_OTG_WARN(...) do{\ - if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \ - _DbgDump("\r" OTG_PREFIX __VA_ARGS__);\ - }while(0) - -#define DBG_8195A_OTG_ERR(...) do{\ - if (unlikely(ConfigDebugErr & _DBG_USB_OTG_)) \ - _DbgDump("\r" OTG_PREFIX __VA_ARGS__);\ - }while(0) - -#define DBG_8195A_OTG_LVL(LVL,...) do{\ - if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)){ \ - _DbgDump("\r" OTG_PREFIX_LVL,LVL);\ - _DbgDump(__VA_ARGS__);\ - }\ -}while(0) - -#define DBG_MISC_ERR(...) do {\ - if (likely(ConfigDebugErr & _DBG_MISC_)) \ - _DbgDump("\r" MISC_ERR_PREFIX __VA_ARGS__);\ -}while(0) - -#else // else of "#if CONFIG_DEBUG_ERROR" - -#define DBG_BOOT_ERR(...) -#define DBG_GDMA_ERR(...) -#define DBG_GPIO_ERR(...) -#define DBG_TIMER_ERR(...) -#define DBG_I2C_ERR(...) -#define DBG_I2S_ERR(...) -#define DBG_MII_ERR(...) -#define DBG_NFC_ERR(...) -#define DBG_PCM_ERR(...) -#define DBG_PWM_ERR(...) -#define DBG_SSI_ERR(...) -#define DBG_SDIO_ERR(...) -#define DBG_SPIF_ERR(...) -#define DBG_SDR_ERR(...) -#define DBG_UART_ERR(...) -#define DBG_USBOTG_ERR(...) -#define DBG_USBCOR_ERR(...) -#define DBG_CRYPTO_ERR(...) -#define DBG_ADC_ERR(...) -#define DBG_DAC_ERR(...) - -#define MSG_MBOX_ERR(...) -#define MSG_TIMER_ERR(...) -#define DBG_8195A_OTG(...) -#define DBG_8195A_OTG_LVL(LVL,...) -#define DBG_8195A_OTG_INFO(...) -#define DBG_8195A_OTG_WARN(...) -#define DBG_8195A_OTG_ERR(...) - - -#endif // end of else of "#if CONFIG_DEBUG_ERROR" - -// ============================================================= - -#if CONFIG_DEBUG_WARN // if Build-In Debug Warring Message - -#define DBG_BOOT_WARN(...) do {\ - if (unlikely(ConfigDebugWarn& _DBG_BOOT_)) \ - _DbgDump("\r" BOOT_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_GDMA_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_GDMA_)) \ - _DbgDump("\r" GDMA_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_GPIO_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_GPIO_)) \ - _DbgDump("\r" GPIO_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_TIMER_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_TIMER_)) \ - _DbgDump("\r" TIMER_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_I2C_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_I2C_)) \ - _DbgDump("\r" I2C_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_I2S_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_I2S_)) \ - _DbgDump("\r" I2S_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_MII_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_MII_)) \ - _DbgDump("\r" MII_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_NFC_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_NFC_)) \ - _DbgDump("\r" NFC_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_PCM_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_PCM_)) \ - _DbgDump("\r" PCM_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_PWM_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_PWM_)) \ - _DbgDump("\r" PWM_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SSI_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_SSI_)) \ - _DbgDump("\r" SSI_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SDIO_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_SDIO_)) \ - _DbgDump("\r" SDIO_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SPIF_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_SPI_FLASH_)) \ - _DbgDump("\r" SPIF_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SDR_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_SDR_)) \ - _DbgDump("\r" SDR_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_UART_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_UART_)) \ - _DbgDump("\r" UART_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_USBOTG_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \ - _DbgDump("\r" __VA_ARGS__);\ -}while(0) - -#define DBG_USBCOR_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_USB_CORE_)) \ - _DbgDump("\r" USB_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_CRYPTO_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_CRYPTO_)) \ - _DbgDump("\r" IPSEC_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_ADC_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_ADC_)) \ - _DbgDump("\r" ADC_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_DAC_WARN(...) do {\ - if (unlikely(ConfigDebugWarn & _DBG_DAC_)) \ - _DbgDump("\r" DAC_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#define MSG_MBOX_WARN(...) do {\ - if (unlikely(CfgSysDebugWarn& _SYSDBG_MAILBOX_)) \ - _DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\ -}while(0) - -#define MSG_TIMER_WARN(...) do {\ - if (unlikely(CfgSysDebugWarn & _SYSDBG_TIMER_)) \ - _DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_MISC_WARN(...) do {\ - if (likely(ConfigDebugWarn & _DBG_MISC_)) \ - _DbgDump("\r" MISC_WARN_PREFIX __VA_ARGS__);\ -}while(0) - -#else // else of "#if CONFIG_DEBUG_WARN" - -#define DBG_BOOT_WARN(...) -#define DBG_GDMA_WARN(...) -#define DBG_GPIO_WARN(...) -#define DBG_TIMER_WARN(...) -#define DBG_I2C_WARN(...) -#define DBG_I2S_WARN(...) -#define DBG_MII_WARN(...) -#define DBG_NFC_WARN(...) -#define DBG_PCM_WARN(...) -#define DBG_PWM_WARN(...) -#define DBG_SSI_WARN(...) -#define DBG_SDIO_WARN(...) -#define DBG_SPIF_WARN(...) -#define DBG_SDR_WARN(...) -#define DBG_UART_WARN(...) -#define DBG_USBOTG_WARN(...) -#define DBG_USBCOR_WARN(...) -#define DBG_CRYPTO_WARN(...) -#define DBG_ADC_WARN(...) -#define DBG_DAC_WARN(...) -#define DBG_MISC_WARN(...) - -#define MSG_MBOX_WARN(...) -#define MSG_TIMER_WARN(...) - -#endif // end of else of "#if CONFIG_DEBUG_WARN" - -// ============================================================= - -#if CONFIG_DEBUG_INFO // if Build-In Debug Information Message - -#define DBG_BOOT_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_BOOT_)) \ - _DbgDump("\r" BOOT_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_GDMA_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_GDMA_)) \ - _DbgDump("\r" GDMA_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_GPIO_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_GPIO_)) \ - _DbgDump("\r" GPIO_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_TIMER_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_TIMER_)) \ - _DbgDump("\r" TIMER_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_I2C_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_I2C_)) \ - _DbgDump("\r" I2C_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_I2S_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_I2S_)) \ - _DbgDump("\r" I2S_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_MII_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_MII_)) \ - _DbgDump("\r" MII_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_NFC_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_NFC_)) \ - _DbgDump("\r" NFC_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_PCM_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_PCM_)) \ - _DbgDump("\r" PCM_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_PWM_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_PWM_)) \ - _DbgDump("\r" PWM_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SSI_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_SSI_)) \ - _DbgDump("\r" SSI_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SDIO_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_SDIO_)) \ - _DbgDump("\r" SDIO_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SPIF_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_SPI_FLASH_)) \ - _DbgDump("\r" SPIF_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_SDR_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_SDR_)) \ - _DbgDump("\r" SDR_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_UART_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_UART_)) \ - _DbgDump("\r" UART_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_USBOTG_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \ - _DbgDump("\r" __VA_ARGS__);\ -}while(0) - -#define DBG_USBCOR_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_USB_CORE_)) \ - _DbgDump("\r" USB_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_CRYPTO_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_CRYPTO_)) \ - _DbgDump("\r" IPSEC_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_ADC_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_ADC_)) \ - _DbgDump("\r" ADC_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_DAC_INFO(...) do {\ - if (unlikely(ConfigDebugInfo & _DBG_DAC_)) \ - _DbgDump("\r" DAC_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#define MSG_MBOX_INFO(...) do {\ - if (unlikely(CfgSysDebugInfo & _SYSDBG_MAILBOX_)) \ - _DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\ -}while(0) - -#define MSG_TIMER_INFO(...) do {\ - if (unlikely(CfgSysDebugInfo & _SYSDBG_TIMER_)) \ - _DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_MISC_INFO(...) do {\ - if (likely(ConfigDebugInfo & _DBG_MISC_)) \ - _DbgDump("\r" MISC_INFO_PREFIX __VA_ARGS__);\ -}while(0) - -#else // else of "#if CONFIG_DEBUG_INFO" - -#define DBG_BOOT_INFO(...) -#define DBG_GDMA_INFO(...) -#define DBG_GPIO_INFO(...) -#define DBG_TIMER_INFO(...) -#define DBG_I2C_INFO(...) -#define DBG_I2S_INFO(...) -#define DBG_MII_INFO(...) -#define DBG_NFC_INFO(...) -#define DBG_PCM_INFO(...) -#define DBG_PWM_INFO(...) -#define DBG_SSI_INFO(...) -#define DBG_SDIO_INFO(...) -#define DBG_SPIF_INFO(...) -#define DBG_SDR_INFO(...) -#define DBG_UART_INFO(...) -#define DBG_USBOTG_INFO(...) -#define DBG_USBCOR_INFO(...) -#define DBG_CRYPTO_INFO(...) -#define DBG_ADC_INFO(...) -#define DBG_DAC_INFO(...) -#define DBG_MISC_INFO(...) - -#define MSG_MBOX_INFO(...) -#define MSG_TIMER_INFO(...) - -#endif // end of else of "#if CONFIG_DEBUG_INFO" - -#define DBG_8195A_DRIVER(...) do {\ - if (unlikely(ConfigDebugErr & (_DBG_I2S_|_DBG_PCM_|_DBG_TIMER_))) \ - _DbgDump("\r" DRIVER_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_8195A_HAL(...) do {\ - if (unlikely(ConfigDebugErr & (_DBG_SDR_|_DBG_MISC_))) \ - _DbgDump("\r" HAL_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_8195A_DMA(...) do {\ - if (unlikely(ConfigDebugErr & _DBG_GDMA_)) \ - _DbgDump("\r" DMA_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_8195A_SDIO(...) do {\ - if (unlikely(ConfigDebugErr & _DBG_SDIO_)) \ - _DbgDump("\r" SDIO_PREFIX __VA_ARGS__);\ -}while(0) - -#define DBG_8195A(...) do {\ - if (unlikely(ConfigDebugErr & _DBG_MISC_)) \ - _DbgDump("\r" __VA_ARGS__);\ -}while(0) - -#define MONITOR_LOG(...) do {\ - if (unlikely(ConfigDebugErr & _DBG_MISC_)) \ - _DbgDump( __VA_ARGS__);\ -}while(0) - -#define DBG_ERROR_LOG(...) do {\ - if (unlikely(ConfigDebugErr & _DBG_FAULT_)) \ - _DbgDump( __VA_ARGS__);\ -}while(0) - -#ifdef __GNUC__ -#define DBG_ASSERT(x) do {\ - if (unlikely(!(x))) \ - _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\ - }while(0) -#endif - -#ifdef __ICCARM__ -#define DBG_ASSERT(x) do {\ - if (unlikely(!(x))) \ - _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\ - }while(0) -#endif - -#else // else of "#if CONFIG_DEBUG_LOG" -#define DBG_8195A_DRIVER(...) - -#define DBG_8195A_HAL(...) - -#define DBG_8195A(...) - -#define DBG_8195A_DMA(...) - -#define MONITOR_LOG(...) - -#define DBG_ERROR_LOG(...) - -#define DBG_8195A_SDIO(...) - -#define DBG_BOOT_ERR(...) -#define DBG_GDMA_ERR(...) -#define DBG_GPIO_ERR(...) -#define DBG_TIMER_ERR(...) -#define DBG_I2C_ERR(...) -#define DBG_I2S_ERR(...) -#define DBG_MII_ERR(...) -#define DBG_NFC_ERR(...) -#define DBG_PCM_ERR(...) -#define DBG_PWM_ERR(...) -#define DBG_SSI_ERR(...) -#define DBG_SDIO_ERR(...) -#define DBG_SPIF_ERR(...) -#define DBG_SDR_ERR(...) -#define DBG_UART_ERR(...) -#define DBG_USBOTG_ERR(...) -#define DBG_USBCOR_ERR(...) -#define DBG_CRYPTO_ERR(...) -#define DBG_ADC_ERR(...) -#define DBG_DAC_ERR(...) -#define MSG_MBOX_ERR(...) -#define MSG_TIMER_ERR(...) - -#define DBG_BOOT_WARN(...) -#define DBG_GDMA_WARN(...) -#define DBG_GPIO_WARN(...) -#define DBG_TIMER_WARN(...) -#define DBG_I2C_WARN(...) -#define DBG_I2S_WARN(...) -#define DBG_MII_WARN(...) -#define DBG_NFC_WARN(...) -#define DBG_PCM_WARN(...) -#define DBG_PWM_WARN(...) -#define DBG_SSI_WARN(...) -#define DBG_SDIO_WARN(...) -#define DBG_SPIF_WARN(...) -#define DBG_SDR_WARN(...) -#define DBG_UART_WARN(...) -#define DBG_USBOTG_WARN(...) -#define DBG_USBCOR_WARN(...) -#define DBG_CRYPTO_WARN(...) -#define DBG_ADC_WARN(...) -#define DBG_DAC_WARN(...) -#define MSG_MBOX_WARN(...) -#define MSG_TIMER_WARN(...) - -#define DBG_BOOT_INFO(...) -#define DBG_GDMA_INFO(...) -#define DBG_GPIO_INFO(...) -#define DBG_TIMER_INFO(...) -#define DBG_I2C_INFO(...) -#define DBG_I2S_INFO(...) -#define DBG_MII_INFO(...) -#define DBG_NFC_INFO(...) -#define DBG_PCM_INFO(...) -#define DBG_PWM_INFO(...) -#define DBG_SSI_INFO(...) -#define DBG_SDIO_INFO(...) -#define DBG_SPIF_INFO(...) -#define DBG_SDR_INFO(...) -#define DBG_UART_INFO(...) -#define DBG_USBOTG_INFO(...) -#define DBG_USBCOR_INFO(...) -#define DBG_CRYPTO_INFO(...) -#define DBG_ADC_INFO(...) -#define DBG_DAC_INFO(...) - -#define MSG_MBOX_INFO(...) -#define MSG_TIMER_INFO(...) - -#define DBG_ASSERT(x) - -#endif - -#define ANSI_COLOR_GREEN "\x1b[32m" -#define ANSI_COLOR_CYAN "\x1b[36m" -#define ANSI_COLOR_YELLOW "\x1b[33m" -#define ANSI_COLOR_MAGENTA "\x1b[35m" -#define ANSI_COLOR_RED "\x1b[31m" -#define ANSI_COLOR_BLUE "\x1b[34m" -#define ANSI_COLOR_RESET "\x1b[0m" - -#define IDENT_ONE_SPACE " " -#define IDENT_TWO_SPACE " " -#define IDENT_FOUR_SPACE " " -#define IDENT_SIX_SPACE " " -#define IDENT_EIGHT_SPACE " " - -#ifdef CONFIG_DEBUG_LOG -enum _DBG_CFG_TYPE_ { - DBG_CFG_ERR=0, - DBG_CFG_WARN=1, - DBG_CFG_INFO=2 -}; -typedef uint32_t DBG_CFG_TYPE; - -typedef struct _DBG_CFG_CMD_ { - u8 cmd_name[16]; - u32 cmd_type; -} DBG_CFG_CMD, *PDBG_CFG_CMD; - -#endif - -enum _CONSOLE_OP_STAGE_ { - ROM_STAGE = 0, - RAM_STAGE = 1 -}; -typedef uint32_t CONSOLE_OP_STAGE; - -#endif //_DIAG_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/platform_autoconf.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/platform_autoconf.h deleted file mode 100644 index 5d3c7a03cb6..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/platform_autoconf.h +++ /dev/null @@ -1,246 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -/* - * Automatically generated by make menuconfig: don't edit - */ -#define AUTOCONF_INCLUDED - -/* - * Target Platform Selection - */ -#undef CONFIG_RTL8195A -#define CONFIG_RTL8195A 1 -#undef CONFIG_FPGA -#undef CONFIG_RTL_SIM -#undef CONFIG_POST_SIM - -/* - * < Mass Production Option - */ -#undef CONFIG_MP -#undef CONFIG_CP -#undef CONFIG_FT -#define RTL8195A 1 -#define CONFIG_CPU_CLK 1 -#define CONFIG_CPU_166_6MHZ 1 -#undef CONFIG_CPU_83_3MHZ -#undef CONFIG_CPU_41_6MHZ -#undef CONFIG_CPU_20_8MHZ -#undef CONFIG_CPU_10_4MHZ -#undef CONFIG_CPU_4MHZ -#undef CONFIG_FPGA_CLK -#define PLATFORM_CLOCK (166666666) -#define CPU_CLOCK_SEL_VALUE (0) -#define CONFIG_SDR_CLK 1 -#define CONFIG_SDR_100MHZ 1 -#undef CONFIG_SDR_50MHZ -#undef CONFIG_SDR_25MHZ -#undef CONFIG_SDR_12_5MHZ -#define SDR_CLOCK_SEL_VALUE (0) -#define CONFIG_BOOT_PROCEDURE 1 -#define CONFIG_IMAGE_PAGE_LOAD 1 -#undef CONFIG_IMAGE_AUTO_LOAD -//#undef CONFIG_IMAGE_PAGE_LOAD -//#define CONFIG_IMAGE_AUTO_LOAD 1 - -#undef CONFIG_BOOT_TO_UPGRADE_IMG2 - -#undef CONFIG_PERI_UPDATE_IMG -#define CONFIG_BOOT_FROM_JTAG 1 -#undef CONFIG_ALIGNMENT_EXCEPTION_ENABLE -#define CONFIG_KERNEL 1 - -#define PLATFORM_FREERTOS 1 -#define CONFIG_MBED_ENABLED 1 -#if defined(CONFIG_MBED_ENABLED) -#undef PLATFORM_FREERTOS -#define PLATFORM_CMSIS_RTOS 1 -#endif - -#undef PLATFORM_UCOSII -#undef PLATFORM_ECOS -#undef CONFIG_TASK_SCHEDUL_DIS -#define TASK_SCHEDULER_DISABLED (0) -#define CONFIG_NORMALL_MODE 1 -#undef CONFIG_MEMORY_VERIFY_MODE -#define CONFIG_TIMER_EN 1 -#define CONFIG_TIMER_NORMAL 1 -#undef CONFIG_TIMER_TEST -#define CONFIG_TIMER_MODULE 1 -#define CONFIG_WDG 1 -#undef CONFIG_WDG_NON -#define CONFIG_WDG_NORMAL 1 - -#undef CONFIG_WDG_TEST -#define CONFIG_WDG_MODULE 1 -#define CONFIG_GDMA_EN 1 - -#define CONFIG_GDMA_NORMAL 1 -#undef CONFIG_GDMA_TEST -#define CONFIG_GDMA_MODULE 1 -#define CONFIG_WIFI_EN 1 -#define CONFIG_WIFI_NORMAL 1 -#undef CONFIG_WIFI_TEST -#define CONFIG_WIFI_MODULE 1 -#define CONFIG_GPIO_EN 1 -#define CONFIG_GPIO_NORMAL 1 -#undef CONFIG_GPIO_TEST -#define CONFIG_GPIO_MODULE 1 - -#if defined(CONFIG_INIC) || (CONFIG_SDIOD) -#define CONFIG_SDIO_DEVICE_EN 1 -#define CONFIG_SDIO_DEVICE_NORMAL 1 -#undef CONFIG_SDIO_DEVICE_TEST -#define CONFIG_SDIO_DEVICE_MODULE 1 -#else -#undef CONFIG_SDIO_DEVICE_EN -#endif -#define CONFIG_SDIO_HOST_EN 1 -#define CONFIG_USB_EN 1 -#undef CONFIG_USB_NORMAL -#define CONFIG_USB_TEST 1 -#define CONFIG_USB_MODULE 1 -#define CONFIG_USB_VERIFY 1 -#undef CONFIG_USB_ROM_LIB -//#define CONFIG_USB_DBGINFO_EN 1 -#if defined(CONFIG_INIC) || (CONFIG_USBD) -#define DWC_DEVICE_ONLY 1 -#else -#define DWC_HOST_ONLY 1 -#define CONFIG_USB_HOST_ONLY 1 -#endif - -#undef CONFIG_SDIO_HOST_EN -#undef CONFIG_USB_EN - -#define CONFIG_SPI_COM_EN 1 -#define CONFIG_SPI_COM_NORMAL 1 -#undef CONFIG_SPI_COM_TEST -#define CONFIG_SPI_COM_MODULE 1 -#define CONFIG_UART_EN 1 -#define CONFIG_UART_NORMAL 1 -#undef CONFIG_UART_TEST -#define CONFIG_UART_MODULE 1 -#define CONFIG_I2C_EN 1 -#define CONFIG_I2C_NORMAL 1 -#undef CONFIG_I2C_TEST -#define CONFIG_I2C_MODULE 1 -#undef CONFIG_DEBUG_LOG_I2C_HAL -#undef CONFIG_PCM_EN -#define CONFIG_I2S_EN 1 -#define CONFIG_I2S_NORMAL 1 -#undef CONFIG_I2S_TEST -#define CONFIG_I2S_MODULE 1 - -#undef CONFIG_DEBUG_LOG_I2S_HAL -#undef CONFIG_NFC_EN -#undef CONFIG_NFC_NORMAL -#undef CONFIG_NFC_TEST -#undef CONFIG_NFC_MODULE - -// power saving enable -#define CONFIG_SOC_PS_EN 1 -#define CONFIG_SOC_PS_NORMAL 1 -#undef CONFIG_SOC_PS_TEST -#define CONFIG_SOC_PS_MODULE 1 - -#define CONFIG_CRYPTO_EN 1 -#define CONFIG_CRYPTO_NORMAL 1 -#undef CONFIG_CRYPTO_TEST -#define CONFIG_CRYPTO_MODULE 1 - -//#define CONFIG_MII_EN 1 -#undef CONFIG_MII_EN - -#define CONFIG_PWM_EN 1 -#define CONFIG_PWM_NORMAL 1 -#undef CONFIG_PWM_TEST -#define CONFIG_PWM_MODULE 1 -#define CONFIG_EFUSE_EN 1 -#define CONFIG_EFUSE_NORMAL 1 -#undef CONFIG_EFUSE_TEST -#define CONFIG_EFUSE_MODULE 1 -#define CONFIG_SDR_EN 1 -#define CONFIG_SDR_NORMAL 1 -#undef CONFIG_SDR_TEST -#define CONFIG_SDR_MODULE 1 -#define CONFIG_SPIC_EN 1 -#define CONFIG_SPIC_NORMAL 1 -#undef CONFIG_SPIC_TEST -#define CONFIG_SPIC_MODULE 1 -#define CONFIG_ADC_EN 1 -#define CONFIG_DAC_EN 1 -#define CONFIG_NOR_FLASH 1 -#undef CONFIG_SPI_FLASH -#undef CONFIG_NAND_FLASH -#undef CONFIG_NONE_FLASH -#undef CONFIG_BTBX_EN - -/* - * < Engineer Mode Config - */ -#undef CONFIG_JTAG -#undef CONFIG_COMPILE_FLASH_DOWNLOAD_CODE -#undef CONIFG_COMPILE_EXTERNAL_SRAM_CALIBRATE -#undef CONFIG_CMSIS_MATH_LIB_EN - -/* - * < Application Config - */ -#define CONFIG_NETWORK 1 -#define CONFIG_RTLIB_EN 1 -#define CONFIG_RTLIB_NORMAL 1 -#undef CONFIG_RTLIB_TEST -#define CONFIG_RTLIB_MODULE 1 - -/* - * < System Debug Message Config - */ -#define CONFIG_UART_LOG_HISTORY 1 -#undef CONFIG_CONSOLE_NORMALL_MODE -#define CONFIG_CONSOLE_VERIFY_MODE 1 - -//#undef CONFIG_DEBUG_LOG -#define CONFIG_DEBUG_LOG 1 - -#define CONFIG_DEBUG_ERR_MSG 1 -#undef CONFIG_DEBUG_WARN_MSG -#undef CONFIG_DEBUG_INFO_MSG -#undef CONFIG_APP_DEMO - -/* - * < Select Chip Version - */ -#undef CONFIG_CHIP_A_CUT -#define CONFIG_CHIP_B_CUT 1 -#undef CONFIG_CHIP_C_CUT -#undef CONFIG_CHIP_E_CUT - -/* - * < Select toolchain - */ -#undef CONFIG_TOOLCHAIN_ASDK -#undef CONFIG_TOOLCHAIN_ARM_GCC - -/* - * < Build Option - */ -#define CONFIG_LINK_ROM_LIB 1 -#undef CONFIG_LINK_ROM_SYMB -#undef CONFIG_NORMAL_BUILD -#undef CONFIG_RELEASE_BUILD -#undef CONFIG_RELEASE_BUILD_LIBRARIES -#undef CONFIG_LIB_BUILD_RAM -#define CONFIG_RELEASE_BUILD_RAM_ALL 1 -#undef CONFIG_IMAGE_ALL -#define CONFIG_IMAGE_SEPARATE 1 diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/platform_opts.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/platform_opts.h deleted file mode 100644 index e67a675caa7..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/platform_opts.h +++ /dev/null @@ -1,599 +0,0 @@ -/** -Copyright (c) 2016 Realtek Semiconductor Corp. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - -http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - - ****************************************************************************** - *This file contains general configurations for ameba platform - ****************************************************************************** -*/ - -#ifndef __PLATFORM_OPTS_H__ -#define __PLATFORM_OPTS_H__ - -/*For MP mode setting*/ -#define SUPPORT_MP_MODE 1 - -/** - * For AT cmd Log service configurations - */ -#define SUPPORT_LOG_SERVICE 1 -#if SUPPORT_LOG_SERVICE -#define LOG_SERVICE_BUFLEN 100 //can't larger than UART_LOG_CMD_BUFLEN(127) -#define CONFIG_LOG_HISTORY 0 -#if CONFIG_LOG_HISTORY -#define LOG_HISTORY_LEN 5 -#endif -#define SUPPORT_INTERACTIVE_MODE 0//on/off wifi_interactive_mode -#define CONFIG_LOG_SERVICE_LOCK 0 - -#define CONFIG_ATCMD_MP 0 //support MP AT command -#define USE_MODE 1 //for test - -#endif - -/** - * For interactive mode configurations, depends on log service - */ -#if SUPPORT_INTERACTIVE_MODE -#define CONFIG_INTERACTIVE_MODE 1 -#define CONFIG_INTERACTIVE_EXT 0 -#else -#define CONFIG_INTERACTIVE_MODE 0 -#define CONFIG_INTERACTIVE_EXT 0 -#endif - -/** - * For FreeRTOS tickless configurations - */ -#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 0 // In sleep mode, 0: close PLL clock, 1: reserve PLL clock -#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 1 // In sleep mode, 1: suspend SDRAM, 0: no act - -/******************************************************************************/ - -/** -* For common flash usage -*/ -#define AP_SETTING_SECTOR 0x000FE000 -#define UART_SETTING_SECTOR 0x000FC000 -#define SPI_SETTING_SECTOR 0x000FC000 -#define FAST_RECONNECT_DATA (0x80000 - 0x1000) - -/** - * For Wlan configurations - */ -#define CONFIG_WLAN 1 -#if CONFIG_WLAN -#define CONFIG_LWIP_LAYER 1 -#define CONFIG_INIT_NET 1 //init lwip layer when start up -#define CONFIG_WIFI_IND_USE_THREAD 0 // wifi indicate worker thread -#define CONFIG_ENABLE_AP_POLLING_CLIENT_ALIVE 1 // on or off AP POLLING CLIENT - - -//on/off relative commands in log service -#define CONFIG_SSL_CLIENT 0 -#define CONFIG_WEBSERVER 0 -#define CONFIG_OTA_UPDATE 1 -#define CONFIG_BSD_TCP 0//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size -#define CONFIG_AIRKISS 0//on or off tencent airkiss -#define CONFIG_UART_SOCKET 0 -#define CONFIG_JD_SMART 0//on or off for jdsmart -#define CONFIG_JOYLINK 0//on or off for jdsmart2.0 -#define CONFIG_QQ_LINK 0//on or off for qqlink -#define CONFIG_AIRKISS_CLOUD 0//on or off for weixin hardware cloud -#define CONFIG_UART_YMODEM 0//support uart ymodem upgrade or not -#define CONFIG_GOOGLE_NEST 0//on or off the at command control for google nest -#define CONFIG_TRANSPORT 0//on or off the at command for transport socket -#define CONFIG_ALINK 0//on or off for alibaba alink - -/* For WPS and P2P */ -#define CONFIG_ENABLE_WPS 0 -#define CONFIG_ENABLE_P2P 0 - -#if CONFIG_ENABLE_WPS -#define CONFIG_ENABLE_WPS_DISCOVERY 1 -#endif - -#if CONFIG_ENABLE_P2P -#define CONFIG_ENABLE_WPS_AP 1 -#undef CONFIG_WIFI_IND_USE_THREAD -#define CONFIG_WIFI_IND_USE_THREAD 1 -#endif -#if (CONFIG_ENABLE_P2P && ((CONFIG_ENABLE_WPS_AP == 0) || (CONFIG_ENABLE_WPS == 0))) -#error "If CONFIG_ENABLE_P2P, need to define CONFIG_ENABLE_WPS_AP 1" -#endif - -/* For SSL/TLS */ -#define CONFIG_USE_POLARSSL 0 -#define CONFIG_USE_MBEDTLS 1 -#if ((CONFIG_USE_POLARSSL == 0) && (CONFIG_USE_MBEDTLS == 0)) || ((CONFIG_USE_POLARSSL == 1) && (CONFIG_USE_MBEDTLS == 1)) -#undef CONFIG_USE_POLARSSL -#define CONFIG_USE_POLARSSL 1 -#undef CONFIG_USE_MBEDTLS -#define CONFIG_USE_MBEDTLS 0 - -#endif - -/* For Simple Link */ -#define CONFIG_INCLUDE_SIMPLE_CONFIG 1 - -/*For fast reconnection*/ -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 - -/*For wowlan service settings*/ -#define CONFIG_WOWLAN_SERVICE 0 - -#define CONFIG_GAGENT 0 -/*Disable CONFIG_EXAMPLE_WLAN_FAST_CONNECT when CONFIG_GAGENT is enabled,because - reconnect to previous AP is not suitable when re-configuration. -*/ -#if CONFIG_GAGENT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#endif - - -#endif //end of #if CONFIG_WLAN -/*******************************************************************************/ - -/* For LWIP configuration */ -#define CONFIG_LWIP_DHCP_COARSE_TIMER 60 - -/** - * For Ethernet configurations - */ -#define CONFIG_ETHERNET 0 -#if CONFIG_ETHERNET - -#define CONFIG_LWIP_LAYER 1 -#define CONFIG_INIT_NET 1 //init lwip layer when start up - -//on/off relative commands in log service -#define CONFIG_SSL_CLIENT 0 -#define CONFIG_BSD_TCP 0//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size - -#endif - - -/** - * For iNIC configurations - */ -#ifdef CONFIG_INIC //this flag is defined in IAR project -#define CONFIG_INIC_EN 1//enable iNIC mode -#undef CONFIG_ENABLE_WPS -#define CONFIG_ENABLE_WPS 1 -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 1 -#undef CONFIG_WOWLAN_SERVICE -#define CONFIG_WOWLAN_SERVICE 1 -#undef LOG_SERVICE_BUFLEN -#define LOG_SERVICE_BUFLEN 256 -#undef CONFIG_LWIP_LAYER -#define CONFIG_LWIP_LAYER 0 -#undef CONFIG_OTA_UPDATE -#define CONFIG_OTA_UPDATE 0 -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#define CONFIG_INIC_SDIO_HCI 1 //for SDIO or USB iNIC -#define CONFIG_INIC_USB_HCI 0 -#define CONFIG_INIC_CMD_RSP 1 //need to return msg to host -#endif -/******************End of iNIC configurations*******************/ - - -/* for CoAP example*/ -#define CONFIG_EXAMPLE_COAP 0 - -/* For aj_basic_example */ -#define CONFIG_EXAMPLE_AJ_BASIC 0 - -/*For aj_ameba_led example*/ -#define CONFIG_EXAMPLE_AJ_AMEBA_LED 0 - -/* For WIFI GET BEACON FRAME example */ -#define CONFIG_EXAMPLE_GET_BEACON_FRAME 0 - -/* For WIFI MAC MONITOR example */ -#define CONFIG_EXAMPLE_WIFI_MAC_MONITOR 0 - -/* For HTTP CLIENT example */ -#define CONFIG_EXAMPLE_HTTP_CLIENT 0 - -/* For MQTT example */ -#define CONFIG_EXAMPLE_MQTT 0 - -/* For WiGadget example */ -#define CONFIG_EXAMPLE_WIGADGET 0 - -/*For google nest example*/ -#define CONFIG_EXAMPLE_GOOGLE_NEST 0 - -/* For mDNS example */ -#define CONFIG_EXAMPLE_MDNS 0 - -/* For multicast example */ -#define CONFIG_EXAMPLE_MCAST 0 - -/* For XML example */ -#define CONFIG_EXAMPLE_XML 0 - -/* For socket select example */ -#define CONFIG_EXAMPLE_SOCKET_SELECT 0 - -/* For socket nonblocking connect example */ -#define CONFIG_EXAMPLE_NONBLOCK_CONNECT 0 - -/* For socket TCP bidirectional transmission example */ -#define CONFIG_EXAMPLE_SOCKET_TCP_TRX 0 - -/* For ssl download example */ -#define CONFIG_EXAMPLE_SSL_DOWNLOAD 0 - -/* For http download example */ -#define CONFIG_EXAMPLE_HTTP_DOWNLOAD 0 - -/* For httpc example */ -#define CONFIG_EXAMPLE_HTTPC 0 - -/* For httpd example */ -#define CONFIG_EXAMPLE_HTTPD 0 - -/* For tcp keepalive example */ -#define CONFIG_EXAMPLE_TCP_KEEPALIVE 0 - -/* For sntp show time example */ -#define CONFIG_EXAMPLE_SNTP_SHOWTIME 0 - -/* For pppoe example */ -#define CONFIG_EXAMPLE_PPPOE 0 - -/* For websocket client example */ -#define CONFIG_EXAMPLE_WEBSOCKET 0 - -/*For Audio example */ -#define CONFIG_EXAMPLE_AUDIO 0 -#if CONFIG_EXAMPLE_AUDIO -#define FATFS_DISK_SD 1 -#define CONFIG_EXAMPLE_CODEC_SGTL5000 1 -#endif -/* For audio mp3 pcm example */ -#define CONFIG_EXAMPLE_AUDIO_MP3 0 -#if CONFIG_EXAMPLE_AUDIO_MP3 -#define FATFS_DISK_SD 1 -#define CONFIG_EXAMPLE_MP3_STREAM_SGTL5000 1 -#endif - -/* For audio m4a example */ -#define CONFIG_EXAMPLE_AUDIO_M4A 0 -#if CONFIG_EXAMPLE_AUDIO_M4A -#define CONFIG_EXAMPLE_M4A_FROM_HTTP 1 // 1: From HTTP, 0: From SDCARD -#define FATFS_DISK_SD 1 -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#undef SUPPORT_MP_MODE -#define SUPPORT_MP_MODE 0 -#if (CONFIG_EXAMPLE_M4A_FROM_HTTP == 0) -#undef CONFIG_WLAN -#define CONFIG_WLAN 0 -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#undef SUPPORT_LOG_SERVICE -#define SUPPORT_LOG_SERVICE 0 -#else -#undef FAST_RECONNECT_DATA -#define FAST_RECONNECT_DATA (0x200000-0x1000) -#endif -#endif - -/* For audio m4a example */ -#define CONFIG_EXAMPLE_AUDIO_M4A_SELFPARSE 0 -#if CONFIG_EXAMPLE_AUDIO_M4A_SELFPARSE -#define FATFS_DISK_SD 1 -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMP LE_CONFIG 0 -#undef SUPPORT_MP_MODE -#define SUPPORT_MP_MODE 0 -#undef CONFIG_WLAN -#define CONFIG_WLAN 0 -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#undef SUPPORT_LOG_SERVICE -#define SUPPORT_LOG_SERVICE 0 -#endif - -/* For m4a,mp3 combined example */ -#define CONFIG_EXAMPLE_AUDIO_M4A_MP3 0 -#if CONFIG_EXAMPLE_AUDIO_M4A_MP3 -#define FATFS_DISK_SD 1 -#undef CONFIG_WLAN -#define CONFIG_WLAN 0 -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#undef SUPPORT_LOG_SERVICE -#define SUPPORT_LOG_SERVICE 0 -#undef SUPPORT_MP_MODE -#define SUPPORT_MP_MODE 0 -#endif - -/* For audio amr example */ -#define CONFIG_EXAMPLE_AUDIO_AMR 0 -#if CONFIG_EXAMPLE_AUDIO_AMR -#define FATFS_DISK_SD 1 -#undef CONFIG_WLAN -#define CONFIG_WLAN 0 -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#endif - -/* For audio HLS example */ -#define CONFIG_EXAMPLE_AUDIO_HLS 0 -#if CONFIG_EXAMPLE_AUDIO_HLS -#define FATFS_DISK_SD 1 -#undef FAST_RECONNECT_DATA -#define FAST_RECONNECT_DATA (0x200000-0x1000) -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#undef SUPPORT_MP_MODE -#define SUPPORT_MP_MODE 0 -#endif - -/*Foe alc audio dsp firmware upgrade */ -#define CONFIG_EXAMPLE_ALC_DSP_FW_UPGRADE 0 - -/*Foe audio pcm upload */ -#define CONFIG_EXAMPLE_AUDIO_PCM_UPLOAD 0 - -/* For UART Module AT command example */ -#define CONFIG_EXAMPLE_UART_ATCMD 0 -#if CONFIG_EXAMPLE_UART_ATCMD -#undef FREERTOS_PMU_TICKLESS_PLL_RESERVED -#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 1 -#undef CONFIG_OTA_UPDATE -#define CONFIG_OTA_UPDATE 1 -#undef CONFIG_TRANSPORT -#define CONFIG_TRANSPORT 1 -#undef LOG_SERVICE_BUFLEN -#define LOG_SERVICE_BUFLEN 1600 -#undef CONFIG_LOG_SERVICE_LOCK -#define CONFIG_LOG_SERVICE_LOCK 1 -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#endif - -/* For SPI Module AT command example */ -#define CONFIG_EXAMPLE_SPI_ATCMD 0 - -#if CONFIG_EXAMPLE_SPI_ATCMD -#undef FREERTOS_PMU_TICKLESS_PLL_RESERVED -#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 1 -#undef CONFIG_OTA_UPDATE -#define CONFIG_OTA_UPDATE 1 -#undef CONFIG_TRANSPORT -#define CONFIG_TRANSPORT 1 -#undef LOG_SERVICE_BUFLEN -#define LOG_SERVICE_BUFLEN 1600 -#undef CONFIG_LOG_SERVICE_LOCK -#define CONFIG_LOG_SERVICE_LOCK 1 -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#endif -#define CONFIG_EXAMPLE_MEDIA_SS 0 -#define CONFIG_EXAMPLE_MEDIA_MS 0 -#define CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP 0 - -//Defines for mp3 streaming over wifi, default output through alc5651 -#define CONFIG_EXAMPLE_MP3_STREAM_RTP 0 - -#if CONFIG_EXAMPLE_MP3_STREAM_RTP -#undef CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP -#define CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP 1 -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -//Set this flag to 1 in case sgtl5000 to be used else alc5651 will be used -#define CONFIG_EXAMPLE_MP3_STREAM_SGTL5000 0 -#endif - -// Use media source/sink example - -#if (CONFIG_EXAMPLE_MEDIA_SS==1) || (CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP) - -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#define CONFIG_ENABLE_WPS 0 -#endif - -/* For ISP AT COMMAND config*/ -#define CONFIG_ISP 0 - -/* For Mjpeg capture example*/ -#define CONFIG_EXAMPLE_MJPEG_CAPTURE 0 -#if CONFIG_EXAMPLE_MJPEG_CAPTURE -#define FATFS_DISK_SD 1 -#endif - -/* For DCT example*/ -#define CONFIG_EXAMPLE_DCT 0 - -/* For audio flash mp3 pcm example */ -#define CONFIG_EXAMPLE_FLASH_MP3 0 -#if CONFIG_EXAMPLE_FLASH_MP3 -#define FATFS_DISK_FLASH 1 -#define CONFIG_EXAMPLE_MP3_STREAM_SGTL5000 1 - -#endif - -/****************** For EAP method example *******************/ -#define CONFIG_EXAMPLE_EAP 0 - -// on/off specified eap method -#define CONFIG_ENABLE_PEAP 0 -#define CONFIG_ENABLE_TLS 0 -#define CONFIG_ENABLE_TTLS 0 - -// optional feature: whether to verify the cert of radius server -#define ENABLE_EAP_SSL_VERIFY_SERVER 0 - -#if CONFIG_ENABLE_PEAP || CONFIG_ENABLE_TLS || CONFIG_ENABLE_TTLS -#define CONFIG_ENABLE_EAP - -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT - -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#endif - -#if CONFIG_ENABLE_TLS -#define ENABLE_EAP_SSL_VERIFY_CLIENT 1 -#else -#define ENABLE_EAP_SSL_VERIFY_CLIENT 0 -#endif -/******************End of EAP configurations*******************/ - -/* For usb mass storage example */ -#define CONFIG_EXAMPLE_USB_MASS_STORAGE 0 - -/* For vendor specific example */ -#define CONFIG_EXAMPLE_USB_VENDOR_SPECIFIC 0 - -#define CONFIG_EXAMPLE_USB_ISOC_DEVICE 0 - -/* For FATFS example*/ -#define CONFIG_EXAMPLE_FATFS 0 -#if CONFIG_EXAMPLE_FATFS -#define CONFIG_FATFS_EN 1 -#if CONFIG_FATFS_EN -// fatfs version -#define FATFS_R_10C -// fatfs disk interface -#define FATFS_DISK_USB 0 -#define FATFS_DISK_SD 1 -#define FATFS_DISK_FLASH 0 -#endif -#endif - -/* For iNIC host example*/ -#ifdef CONFIG_INIC_GSPI_HOST //this flag is defined in IAR project -#define CONFIG_EXAMPLE_INIC_GSPI_HOST 1 -#if CONFIG_EXAMPLE_INIC_GSPI_HOST - -#define CONFIG_INIC_HOST 1 - -#undef CONFIG_WLAN -#define CONFIG_WLAN 0 -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#undef CONFIG_LWIP_LAYER -#define CONFIG_LWIP_LAYER 1 -#undef CONFIG_BSD_TCP -#define CONFIG_BSD_TCP 1 - -#endif -#endif - -/*For uart update example*/ -#define CONFIG_UART_UPDATE 0 -#if CONFIG_UART_UPDATE -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#endif - - -/*For arduino wifi shield example */ -#define CONFIG_EXAMPLE_ARDUINO_WIFI 0 -#if CONFIG_EXAMPLE_ARDUINO_WIFI -#undef CONFIG_WIFI_NORMAL -#endif - -/* For uart adapter example */ -/* Please also configure LWIP_UART_ADAPTER to 1 -in lwip_opt.h for support uart adapter*/ -#define CONFIG_EXAMPLE_UART_ADAPTER 0 -#if CONFIG_EXAMPLE_UART_ADAPTER -#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1 -#undef CONFIG_EXAMPLE_MDNS -#define CONFIG_EXAMPLE_MDNS 1 -#undef FREERTOS_PMU_TICKLESS_PLL_RESERVED -#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 1 -#endif -#if CONFIG_JD_SMART -#if (CONFIG_ENABLE_WPS == 1) -#define CONFIG_ENABLE_WPS 0 -#endif -#if (CONFIG_INCLUDE_SIMPLE_CONFIG == 1) -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#endif -#if (CONFIG_EXAMPLE_WLAN_FAST_CONNECT == 1) -#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 -#endif -#endif - -/* For wifi scenarios example (Wi-Fi, WPS enrollee, P2P GO) */ -// also need to enable WPS and P2P -#define CONFIG_EXAMPLE_WLAN_SCENARIO 0 - -/* For broadcast example */ -#define CONFIG_EXAMPLE_BCAST 0 - -/* For high-load memory use case memory usage */ -#define CONFIG_EXAMPLE_HIGH_LOAD_MEMORY_USE 0 - -/* For rarp example */ -#define CONFIG_EXAMPLE_RARP 0 - -/* For ssl server example */ -#define CONFIG_EXAMPLE_SSL_SERVER 0 - -/*For timelapse example */ -#define CONFIG_EXAMPLE_TIMELAPSE 0 -#if CONFIG_EXAMPLE_TIMELAPSE -#define CONFIG_USE_HTTP_SERVER 0 -#if CONFIG_USE_HTTP_SERVER -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#define CONFIG_ENABLE_WPS 0 -#else -#undef CONFIG_INCLUDE_SIMPLE_CONFIG -#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 -#define CONFIG_ENABLE_WPS 0 -#define CONFIG_FATFS_EN 1 -#define FATFS_R_10C -#define FATFS_DISK_SD 1 -#endif -#endif - -/* For ota update http example */ -#define CONFIG_EXAMPLE_OTA_HTTP 0 - -/* For Amazon AWS IoT example */ -#define CONFIG_EXAMPLE_AMAZON_AWS_IOT 0 -#define CONFIG_EXAMPLE_AMAZON_ALEXA 0 - -/*For wifi roaming example*/ -#define CONFIG_EXAMPLE_WIFI_ROAMING 0 -#if CONFIG_QQ_LINK -#define FATFS_R_10C -#define FATFS_DISK_USB 0 -#define FATFS_DISK_SD 1 -#endif -#if CONFIG_ENABLE_WPS -#define WPS_CONNECT_RETRY_COUNT 4 -#define WPS_CONNECT_RETRY_INTERVAL 5000 // in ms -#endif -#define AUTO_RECONNECT_COUNT 8 -#define AUTO_RECONNECT_INTERVAL 5 // in sec -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rand.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rand.h deleted file mode 100644 index 222f2892083..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rand.h +++ /dev/null @@ -1,19 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -u32 -Rand ( - VOID -); - - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_clk.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_clk.h deleted file mode 100644 index cb97516dbed..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_clk.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_RTL8195A_CLK_H -#define MBED_RTL8195A_CLK_H - -#define PLATFORM_CLK (200000000UL/6*5) // 166MHz -//#define SYSTEM_CLK PLATFORM_CLK -//#define TIMER_CLK (32*1000) - -#define __BUILD_CCTRL_MACRO(name,ctrl) \ -static inline void \ -__##name##_ACTCK_Enable(void) \ -{ \ - __RTK_PERI_SETBIT(ctrl, BIT_ACTCK_##name); \ -} \ -static inline void \ -__##name##_SLPCK_Enable(void) \ -{ \ - __RTK_PERI_SETBIT(ctrl, BIT_SLPCK_##name); \ -} \ -static inline void \ -__##name##_ACTCK_Disable(void) \ -{ \ - __RTK_PERI_CLRBIT(ctrl, BIT_ACTCK_##name); \ -} \ -static inline void \ -__##name##_SLPCK_Disable(void) \ -{ \ - __RTK_PERI_CLRBIT(ctrl, BIT_SLPCK_##name); \ -} \ - -//enum clk_idx { -// CLK_ANACK = 0, -// CLK_A33CK = 1, -//}; - -// Interface to ROM functions -extern __longcall uint32_t HalGetCpuClk(void); - -#define __CLK_GetCPUClk HalGetCpuClk - -// Interface for HAL functions -static inline uint32_t CLK_GetCPUClk(void) -{ - return __CLK_GetCPUClk(); -} - -extern void CLK_BackupCPUClk(void); -extern void CLK_ReFillCPUClk(void); -extern uint32_t CLK_Calculate(uint8_t clksel); - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_compiler.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_compiler.h deleted file mode 100644 index 3d0dee3dcb5..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_compiler.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_RTL8195A_COMPILER_H -#define MBED_RTL8195A_COMPILER_H - -#if defined (__ICCARM__) -#ifndef STRINGIFY -#define STRINGIFY(a) #a -#endif -#ifndef SECTION -#define SECTION(_name) _Pragma( STRINGIFY(location=##_name##)) -#endif -#ifndef ALIGNMTO -#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=##_bound##)) -#endif -#define __romcall -#define __longcall - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - -#ifndef __longcall -#define __longcall -#endif - -#elif defined(__CC_ARM) - -#ifndef __longcall -#define __longcall __attribute__ ((long_call)) -#endif - -#else -#define SECTION(_name) __attribute__ ((__section__(_name))) -#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound))) - -#ifndef __packed -#define __packed __attribute__ ((packed)) -#endif - -#ifndef __romcall -#define __romcall __attribute__ ((long_call)) -#endif -#ifndef __longcall -#define __longcall __attribute__ ((long_call)) -#endif -#ifndef __weak -#define __weak __attribute__ ((weak)) -#endif - -#endif - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_crypto.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_crypto.h deleted file mode 100644 index 7e3109a06cf..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_crypto.h +++ /dev/null @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2017 Realtek Semiconductor Corp. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_RTL8195A_CRYPTO_H -#define MBED_RTL8195A_CRYPTO_H - -extern _LONG_CALL_ uint32_t crc32_get(uint8_t *buf, int len); - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_init.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_init.c deleted file mode 100644 index 1b1e581826d..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_init.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "rtl8195a.h" -#include "basic_types.h" -#include "hal_common.h" - -#if defined(__CC_ARM) || \ - (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050) - -extern uint8_t Image$$RW_IRAM1$$ZI$$Base[]; -extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[]; -extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[]; -extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[]; -extern uint8_t Image$$RW_DRAM2$$ZI$$Base[]; -extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[]; -#define __bss_sram_start__ Image$$RW_IRAM1$$ZI$$Base -#define __bss_sram_end__ Image$$RW_IRAM1$$ZI$$Limit -#define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base -#define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit -#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base -#define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit - -#elif defined (__ICCARM__) - -#pragma section=".bss.sram" -#pragma section=".bss.dtcm" -#pragma section=".bss.dram" - -uint8_t *__bss_sram_start__; -uint8_t *__bss_sram_end__; -uint8_t *__bss_dtcm_start__; -uint8_t *__bss_dtcm_end__; -uint8_t *__bss_dram_start__; -uint8_t *__bss_dram_end__; - -void __iar_data_init_app(void) -{ - __bss_sram_start__ = (uint8_t *)__section_begin(".bss.sram"); - __bss_sram_end__ = (uint8_t *)__section_end(".bss.sram"); - __bss_dtcm_start__ = (uint8_t *)__section_begin(".bss.dtcm"); - __bss_dtcm_end__ = (uint8_t *)__section_end(".bss.dtcm"); - __bss_dram_start__ = (uint8_t *)__section_begin(".bss.dram"); - __bss_dram_end__ = (uint8_t *)__section_end(".bss.dram"); -} - -#else - -extern uint8_t __bss_sram_start__[]; -extern uint8_t __bss_sram_end__[]; -extern uint8_t __bss_dtcm_start__[]; -extern uint8_t __bss_dtcm_end__[]; -extern uint8_t __bss_dram_start__[]; -extern uint8_t __bss_dram_end__[]; - -#endif - -extern VECTOR_Func NewVectorTable[]; -extern void SystemCoreClockUpdate(void); -extern VOID En32KCalibration(VOID); -extern void PLAT_Start(void); -extern void PLAT_Main(void); - -IMAGE2_START_RAM_FUN_SECTION -__USED - -const RAM_START_FUNCTION gImage2EntryFun0 = { - PLAT_Start -}; - -IMAGE2_VALID_PATTEN_SECTION -__USED - -const uint8_t IMAGE2_SIGNATURE[20] = { - 'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff, - (FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff), - (FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff), - (FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff), - (FW_CHIP_VER), - (FW_BUS_TYPE), - (FW_INFO_RSV1), - (FW_INFO_RSV2), - (FW_INFO_RSV3), - (FW_INFO_RSV4) -}; - -void TRAP_NMIHandler(void) -{ -#ifdef CONFIG_WDG_NORMAL - uint32_t val; - WDG_REG *ctl; - - // Check if this NMI is triggered by Watchdog Timer - val = __RTK_READ32(VENDOR_REG_BASE, 0); - ctl = (WDG_REG*) &val; - if (ctl->WdgToISR) { - INTR_WatchdogHandler(); - } -#endif -} - -#if defined (__ICCARM__) -void __TRAP_HardFaultHandler_Patch(uint32_t addr) -{ - uint32_t cfsr; - uint32_t bfar; - - uint32_t stackpc; - uint16_t asmcode; - - cfsr = HAL_READ32(0xE000ED28, 0x0); - - // Violation to memory access protection - if (cfsr & 0x82) { - - bfar = HAL_READ32(0xE000ED38, 0x0); - - // invalid access to wifi register, usually happened in LPS 32K or IPS - if (bfar >= WIFI_REG_BASE && bfar < WIFI_REG_BASE + 0x40000) { - - //__BKPT(0); - - /* Get the MemManage fault PC, and step to next command. - * Otherwise it will keep hitting MemMange Fault on the same assembly code. - * - * To step to next command, we need parse the assembly code to check if - * it is 16-bit or 32-bit command. - * Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition), - * Chapter A6 - Thumb Instruction Set Encoding - * - * However, the fault assembly code (Ex. LDR or ADR) is not actually executed, - * So the register value is un-predictable. - **/ - stackpc = HAL_READ32(addr, 0x18); - asmcode = HAL_READ16(stackpc, 0); - if ((asmcode & 0xF800) > 0xE000) { - // 32-bit instruction, (opcode[15:11] = 0b11111, 0b11110, 0b11101) - HAL_WRITE32(addr, 0x18, stackpc + 4); - } else { - // 16-bit instruction - HAL_WRITE32(addr, 0x18, stackpc + 2); - } - - // clear Hard Fault Status Register - HAL_WRITE32(0xE000ED2C, 0x0, HAL_READ32(0xE000ED2C, 0x0)); - return; - } - } - - __TRAP_HardFaultHandler(addr); -} - -void TRAP_HardFaultHandler_Patch(void) -{ - __asm("TST LR, #4 \n" - "ITE EQ \n" - "MRSEQ R0, MSP \n" - "MRSNE R0, PSP \n" - "B __TRAP_HardFaultHandler_Patch "); -} -#endif - -extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n); -_WEAK void SDIO_Device_Off(void) -{ - /* Disable Clock for SDIO function */ - ACTCK_SDIOD_CCTRL(OFF); - - /* SDIO Function Disable */ - SDIOD_ON_FCTRL(OFF); - SDIOD_OFF_FCTRL(OFF); - // SDIO Pin Mux off - SDIOD_PIN_FCTRL(OFF); -} - -void SYSPlatformInit(void) -{ -#ifdef CONFIG_CHIP_A_CUT - //Set SPS lower voltage - HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0, (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0)&0xf0ffffff)); -#else // B-Cut & C-Cut - //Set SPS lower voltage - HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0, ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0)&0xf0ffffff)|0x6000000)); -#endif - - //xtal buffer driving current - HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_XTAL_CTRL1, - ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_XTAL_CTRL1)&(~(BIT_MASK_SYS_XTAL_DRV_RF1< 10000) { /*Delay 100ms*/ - //DiagPrintf("32K linear Calibration Fail!!\n"); - flag = 0; - break; - } - } - } - } -} -// Image2 Entry Function -void PLAT_Init(void) -{ - // Overwrite vector table - NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler; -#if defined ( __ICCARM__ ) - NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch; -#endif - - // Clear RAM BSS -#if defined (__ICCARM__) - __iar_data_init_app(); -#endif - __rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__); - __rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__); - __rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__); - - HAL_WRITE32(SYSTEM_CTRL_BASE, REG_OSC32K_CTRL, (HAL_READ32(SYSTEM_CTRL_BASE, REG_OSC32K_CTRL)|BIT17|BIT18)); - HalDelayUs(40); -#ifdef CONFIG_TIMER_MODULE - // Re-init G-Timer HAL Function pointer with ROM Patch - if (HalCommonInit() != HAL_OK) { - DBG_8195A("Hal Common Init Failed.\n"); - } -#endif - - SystemCoreClockUpdate(); - - SYSPlatformInit(); - // Initialize SPIC, then disable it for power saving. - if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) { - SpicNVMCalLoadAll(); - SpicReadIDRtl8195A(); - SpicDisableRtl8195A(); - } - -#ifdef CONFIG_TIMER_MODULE - - OSC_32_LINEAR_CALIBRATION(10); - HalDelayUs(40); - - Calibration32k(); -#endif - -#ifdef CONFIG_SOC_PS_MODULE - InitSoCPM(); -#endif - -#ifndef CONFIG_SDIO_DEVICE_EN - SDIO_Device_Off(); -#endif - - // Enter App start function - PLAT_Main(); -} - -extern void SVC_Handler(void); -extern void PendSV_Handler(void); -extern void SysTick_Handler(void); - -// The Main App entry point -#if defined (__CC_ARM) -__asm void ARM_PLAT_Main(void) -{ - IMPORT SystemInit - IMPORT __main - BL SystemInit - BL __main -} -#elif defined (__ICCARM__) -extern void __iar_program_start(void); - -void IAR_PLAT_Main(void) -{ - SystemInit(); - __iar_program_start(); -} -#endif - -void PLAT_Main(void) -{ - TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler); - -#if defined (__CC_ARM) - ARM_PLAT_Main(); -#elif defined (__ICCARM__) - IAR_PLAT_Main(); -#else - __asm ("ldr r0, =SystemInit \n" - "blx r0 \n" -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - "ldr r0, =__main \n" -#else - "ldr r0, =_start \n" -#endif - "bx r0 \n" - ); -#endif - - // Never reached - for (;;); -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_misc.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_misc.h deleted file mode 100644 index a2df233452c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_misc.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_RTL8195A_MISC_H -#define MBED_RTL8195A_MISC_H - -// Interface to ROM functions -extern __longcall void *_memset( void *s, int c, size_t n); -extern __longcall void *_memcpy( void *s1, const void *s2, size_t n ); -extern __longcall int _memcmp( const void *av, const void *bv, size_t len); -extern __longcall size_t _strlen(const char *s); -extern __longcall int _strcmp(const char *cs, const char *ct); - -#define __memset _memset -#define __memcpy _memcpy -#define __memcmp _memcmp -#define __strlen _strlen -#define __strcmp _strcmp - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_platform.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_platform.h deleted file mode 100644 index d2875aff996..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_platform.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -// HCI_CLK_CTRL0 -#define BIT_ACTCK_SDIOD BIT(0) -#define BIT_SLPCK_SDIOD BIT(1) -#define BIT_ACTCK_SDIOH BIT(2) -#define BIT_SLPCK_SDIOH BIT(3) -#define BIT_ACTCK_HCI_OTG BIT(4) -#define BIT_SLPCK_HCI_OTG BIT(5) -#define BIT_ACTCK_MII_MPHY BIT(24) -#define BIT_SLPCK_MII_MPHY BIT(25) - - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_trap.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_trap.h deleted file mode 100644 index c59b4534d9e..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl8195a_trap.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_RTL8195A_TRAP_H -#define MBED_RTL8195A_TRAP_H - -typedef void (*VECTOR_Func)(void *data); - -typedef struct { - void (*RamStartFun)(void); - void (*RamWakeupFun)(void); - void (*RamPatchFun0)(void); - void (*RamPatchFun1)(void); - void (*RamPatchFun2)(void); -} RAM_START_TABLE; - -extern uint8_t * __ram_table_start__; - -extern __longcall void HalWdgIntrHandle(void); -extern __longcall void HalHardFaultHandler(u32); - - -#define __TRAP_Init VectorTableInitForOSRtl8195A -#define __TRAP_SetVector VectorTableInitRtl8195A -#define __TRAP_HardFaultHandler HalHardFaultHandler -#define __INTR_Register VectorIrqRegisterRtl8195A -#define __INTR_Unregister VectorIrqUnRegisterRtl8195A -#define __INTR_Enable VectorIrqEnRtl8195A -#define __INTR_Disable VectorIrqDisRtl8195A -#define __INTR_WatchdogHandler HalWdgIntrHandle - -// Interface for HAL layer -static inline void TRAP_Init(void *svc, void *svh, void *tick) -{ - __TRAP_Init(svc, svh, tick); -} - -static inline void TRAP_SetVector(uint32_t stackp) -{ - __TRAP_SetVector(stackp); -} - -static inline bool INTR_Register(IRQ_Handle *handle) -{ - return __INTR_Register(handle); -} - -static inline bool INTR_Unregister(IRQ_Handle *handle) -{ - return __INTR_Unregister(handle); -} - -static inline void INTR_Enable(IRQ_Handle *handle) -{ - __INTR_Enable(handle); -} - -static inline void INTR_Disable(IRQ_Handle *handle) -{ - __INTR_Disable(handle); -} -static inline void INTR_WatchdogHandler(void) -{ - __INTR_WatchdogHandler(); -} - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl_utility.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl_utility.h deleted file mode 100644 index 2cc44187548..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/rtl_utility.h +++ /dev/null @@ -1,68 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef __RTL_UTILITY_H_ -#define __RTL_UTILITY_H_ - -VOID RtlMemcpy(VOID* dec, VOID* sour, u32 sz); -u32 RtlMemcmp(VOID *dst, VOID *src, u32 sz); -VOID RtlMemset(VOID *pbuf, u32 c, u32 sz); - -s8 * -RtlStrncpy( - IN s8 *dest, - IN const s8 *src, - IN SIZE_T count -); - -s8 * -RtlStrcpy( - IN s8 *dest, - IN const s8 *src -); - - -SIZE_T -RtlStrlen( - IN const s8 *s -); - - -SIZE_T -RtlStrnlen( - IN const s8 *s, - IN SIZE_T count -); - - -int -RtlStrcmp( - IN const s8 *cs, - IN const s8 *ct - -); - -int -RtlStrncmp( - IN const s8 *cs, - IN const s8 *ct, - IN SIZE_T count -); - -#endif - - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/strproc.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/strproc.h deleted file mode 100644 index ee944ee3508..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/strproc.h +++ /dev/null @@ -1,108 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _STRPROC_H_ -#define _STRPROC_H_ - -#include /* for size_t */ -#include - -#ifndef isprint -#define in_range(c, lo, up) ((u8)c >= lo && (u8)c <= up) -#define isprint(c) in_range(c, 0x20, 0x7f) -#define isdigit(c) in_range(c, '0', '9') -#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) -#define islower(c) in_range(c, 'a', 'z') -#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v' || c == ',') -#endif - - -extern _LONG_CALL_ROM_ char *_strncpy(char *dest, const char *src, size_t count); -extern _LONG_CALL_ROM_ char *_strcpy(char *dest, const char *src); -extern _LONG_CALL_ROM_ size_t _strlen(const char *s); -extern _LONG_CALL_ROM_ size_t _strnlen(const char *s, size_t count); -extern _LONG_CALL_ROM_ int _strcmp(const char *cs, const char *ct); -extern _LONG_CALL_ROM_ int _strncmp(const char *cs, const char *ct, size_t count); -extern _LONG_CALL_ROM_ int _sscanf(const char *buf, const char *fmt, ...); -extern _LONG_CALL_ROM_ char *_strsep(char **s, const char *ct); -extern _LONG_CALL_ROM_ char *skip_spaces(const char *str); -extern _LONG_CALL_ROM_ int skip_atoi(const char **s); -extern _LONG_CALL_ROM_ int _vsscanf(const char *buf, const char *fmt, va_list args); -extern _LONG_CALL_ROM_ unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base); -extern _LONG_CALL_ROM_ long simple_strtol(const char *cp, char **endp, unsigned int base); -extern _LONG_CALL_ROM_ long long simple_strtoll(const char *cp, char **endp, unsigned int base); -extern _LONG_CALL_ROM_ unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); -extern _LONG_CALL_ROM_ const char *_parse_integer_fixup_radix(const char *s, unsigned int *base); -extern _LONG_CALL_ROM_ unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *p); -extern _LONG_CALL_ROM_ u64 div_u64(u64 dividend, u32 divisor); -extern _LONG_CALL_ROM_ s64 div_s64(s64 dividend, s32 divisor); -extern _LONG_CALL_ROM_ u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder); -extern _LONG_CALL_ROM_ s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder); -extern _LONG_CALL_ROM_ char *_strpbrk(const char *cs, const char *ct); -extern _LONG_CALL_ROM_ char *_strchr(const char *s, int c); - - -extern _LONG_CALL_ROM_ VOID -prvStrCpy( - IN u8 *pDES, - IN const u8 *pSRC -); - -extern _LONG_CALL_ROM_ u32 -prvStrLen( - IN const u8 *pSRC -); - -extern _LONG_CALL_ROM_ u8 -prvStrCmp( - IN const u8 *string1, - IN const u8 *string2 -); - -extern _LONG_CALL_ROM_ u8* -StrUpr( - IN u8 *string -); - -extern _LONG_CALL_ROM_ int prvAtoi( - IN const char * s -); - -extern _LONG_CALL_ROM_ const char * prvStrStr( - IN const char * str1, - IN const char * str2 -); - - -/* - * Fast implementation of tolower() for internal usage. Do not use in your - * code. - */ -static inline char _tolower(const char c) -{ - return c | 0x20; -} - -/* Fast check for octal digit */ -static inline int isodigit(const char c) -{ - return c >= '0' && c <= '7'; -} -#ifndef strtoul -#define strtoul(str, endp, base) simple_strtoul(str, endp, base) -#endif -#ifndef strtol -#define strtol(str, endp, base) simple_strtol(str, endp, base) -#endif - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/system_8195a.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/system_8195a.h deleted file mode 100644 index a730aff7263..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/system_8195a.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM3.h - * @brief CMSIS Device System Header File for - * ARMCM3 Device Series - * @version V1.08 - * @date 23. November 2012 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef _SYSTEM_8195A_H -#define _SYSTEM_8195A_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); -extern u32 SystemGetCpuClk(void); -extern u32 Rand2(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_8195A_H */ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/va_list.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/va_list.h deleted file mode 100644 index 6c7a03eab56..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/va_list.h +++ /dev/null @@ -1,40 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _VA_LIST_H_ -#define _VA_LIST_H_ - -#include "basic_types.h" - -#ifndef va_arg - -typedef s32 acpi_native_int; - -#ifndef _VALIST -#define _VALIST -typedef char *va_list; -#endif /* _VALIST */ - -/* Storage alignment properties */ -#define _AUPBND (sizeof (acpi_native_int) - 1) -#define _ADNBND (sizeof (acpi_native_int) - 1) - -/* Variable argument list macro definitions */ -#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) -#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) -#define va_end(ap) (ap = (va_list) NULL) -#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) - -#endif /* va_arg */ - -#endif //_VA_LIST_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_api.c deleted file mode 100644 index 813834e412d..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_api.c +++ /dev/null @@ -1,78 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "flash_ext.h" - -int32_t flash_init(flash_t *obj) -{ - __flash_ext_turnon(); - - return 0; -} - -int32_t flash_free(flash_t *obj) -{ - __flash_ext_turnoff(); - - return 0; -} - -int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - flash_ext_erase_sector(obj, address); - - return 0; -} - -int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) -{ - return flash_ext_stream_read(obj, address, size, data);; -} - -int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - return flash_ext_stream_write(obj, address, size, data); -} - -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ - if (address >= FLASH_OFS_END) - return MBED_FLASH_INVALID_SIZE; - - return FLASH_SECTOR_SIZE; -} - -uint32_t flash_get_page_size(const flash_t *obj) -{ - return 1; -} - -uint32_t flash_get_start_address(const flash_t *obj) -{ - return FLASH_OFS_START; -} - -uint32_t flash_get_size(const flash_t *obj) -{ - return FLASH_SIZE; -} - -uint8_t flash_get_erase_value(const flash_t *obj) -{ - (void)obj; - - return 0xFF; -} - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_ext.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_ext.c deleted file mode 100644 index 2618ac8f5f6..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_ext.c +++ /dev/null @@ -1,467 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "objects.h" -#include "PinNames.h" -#include "pinmap.h" - -#include "rtl8195a.h" -#include "flash_ext.h" - -extern u32 ConfigDebugInfo; -extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO]; - -static int flash_inited = 0; -static flash_t flashobj; -static void flash_ext_init(void) -{ - if (!SpicFlashInitRtl8195A(SpicOneBitMode)){ - HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3)|0xf); - } else { - flash_inited = 1; - } - flashobj.SpicInitPara.flashtype = SpicInitParaAllClk[0][0].flashtype; -} - -void __flash_ext_turnon(void) -{ - SPI_FLASH_PIN_FCTRL(ON); - SpicWaitBusyDoneRtl8195A(); - - if (flash_inited == 0) { - flash_ext_init(); - } -} - -void __flash_ext_turnoff(void) -{ - SpicDisableRtl8195A(); -} - -void flash_ext_write_protect(flash_t *obj, uint32_t protect) -{ - __flash_ext_turnon(); - SpicWriteProtectFlashRtl8195A(protect); - __flash_ext_turnoff(); -} - -void __flash_ext_erase_sector(flash_t *obj, uint32_t address) -{ - SpicSectorEraseFlashRtl8195A(SPI_FLASH_BASE+address); -} - -void flash_ext_erase_sector(flash_t *obj, uint32_t address) -{ - __flash_ext_turnon(); - __flash_ext_erase_sector(obj, address); - __flash_ext_turnoff(); -} - -void flash_ext_erase_block(flash_t *obj, uint32_t address) -{ - __flash_ext_turnon(); - SpicBlockEraseFlashRtl8195A(SPI_FLASH_BASE+address); - __flash_ext_turnoff(); -} - -int flash_ext_read_word(flash_t *obj, uint32_t address, uint32_t *data) -{ - __flash_ext_turnon(); - - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - *data = HAL_READ32(SPI_FLASH_BASE, address); - __flash_ext_turnoff(); - return 0; -} - -/** - * @brief Write a word to specified address - * @param obj: Specifies the parameter of flash object. - * @param address: Specifies the address to be programmed. - * @param data: Specified the data to be programmed. - * @retval status: Success:1 or Failure: Others. - */ -int flash_ext_write_word(flash_t *obj, uint32_t address, uint32_t data) -{ - u8 flashtype = 0; - __flash_ext_turnon(); - - flashtype = flashobj.SpicInitPara.flashtype; - HAL_WRITE32(SPI_FLASH_BASE, address, data); - SpicWaitBusyDoneRtl8195A(); - - if(flashtype == FLASH_MICRON){ - SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); - } else { - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - } - - __flash_ext_turnoff(); - return 0; -} - -/** - * @brief Read a stream of data from specified address - * @param obj: Specifies the parameter of flash object. - * @param address: Specifies the address to be read. - * @param len: Specifies the length of the data to read. - * @param data: Specified the address to save the readback data. - * @retval status: Success:1 or Failure: Others. - */ -int flash_ext_stream_read(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data) -{ - uint32_t i, offset, word; - uint8_t *ptr, *pbuf; - - __flash_ext_turnon(); - - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - - offset = addr & 0x03; - addr = addr & ~0x03; - pbuf = data; - if (offset != 0) { - word = HAL_READ32(SPI_FLASH_BASE, addr); - ptr = (uint8_t *)&word + offset; - offset = 4 - offset; - for (i = 0; i < offset && len > 0; i++, len--) { - *pbuf = *ptr; - pbuf++; - ptr++; - } - addr += 4; - } - - ptr = (uint8_t *)&word; - if ((uint32_t)pbuf & 0x03) { - while (len >= 4) { - word = HAL_READ32(SPI_FLASH_BASE, addr); - for (i = 0; i < 4; i++) { - *pbuf = *(ptr+i); - pbuf++; - } - addr += 4; - len -= 4; - } - } else { - while (len >= 4) { - *((uint32_t *)pbuf) = HAL_READ32(SPI_FLASH_BASE, addr); - pbuf += 4; - addr += 4; - len -= 4; - } - } - - if (len > 0) { - word = HAL_READ32(SPI_FLASH_BASE, addr); - for (i = 0; i < len; i++) { - *pbuf = *(ptr+i); - pbuf++; - } - } - - __flash_ext_turnoff(); - return 0; -} - -/** - * @brief Write a stream of data to specified address - * @param obj: Specifies the parameter of flash object. - * @param address: Specifies the address to be read. - * @param len: Specifies the length of the data to write. - * @param data: Specified the pointer of the data to be written. - * @retval status: Success:1 or Failure: Others. - */ -int __flash_ext_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data) -{ - uint32_t i, offset, word; - const uint8_t*pbuf; - uint8_t *ptr; - u8 flashtype = 0; - - offset = addr & 0x03; - addr = addr & ~0x03; - pbuf = data; - flashtype = flashobj.SpicInitPara.flashtype; - - if (offset != 0) { - word = HAL_READ32(SPI_FLASH_BASE, addr); - ptr = (uint8_t *)&word + offset; - offset = 4 - offset; - for (i = 0; i < offset && len > 0; i++, len--) { - *ptr = *pbuf; - pbuf++; - ptr++; - } - HAL_WRITE32(SPI_FLASH_BASE, addr, word); - SpicWaitBusyDoneRtl8195A(); - - if(flashtype == FLASH_MICRON){ - SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); - } else { - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - } - addr += 4; - } - - if ((uint32_t)pbuf & 0x03) { - while (len >= 4) { - word = (uint32_t)(*pbuf) | ((uint32_t)(*(pbuf+1)) << 8)| - ((uint32_t)(*(pbuf+2)) << 16) | ((uint32_t)(*(pbuf+3)) << 24); - HAL_WRITE32(SPI_FLASH_BASE, addr, word); - SpicWaitBusyDoneRtl8195A(); - - if(flashtype == FLASH_MICRON){ - SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); - } else { - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - } - - pbuf += 4; - addr += 4; - len -= 4; - } - } else { - while (len >= 4) { - HAL_WRITE32(SPI_FLASH_BASE, addr, (uint32_t)*((uint32_t *)pbuf)); - SpicWaitBusyDoneRtl8195A(); - - if(flashtype == FLASH_MICRON){ - SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); - } else { - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - } - - pbuf += 4; - addr += 4; - len -= 4; - } - } - - if (len > 0) { - word = HAL_READ32(SPI_FLASH_BASE, addr); - ptr = (uint8_t*)&word; - for (i = 0; i < len; i++) { - *(ptr+i) = *pbuf; - pbuf++; - } - - HAL_WRITE32(SPI_FLASH_BASE, addr, word); - SpicWaitBusyDoneRtl8195A(); - - if(flashtype == FLASH_MICRON){ - SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); - } else { - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - } - } - - return 0; -} - -int flash_ext_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data) -{ - int32_t status; - - __flash_ext_turnon(); - status = __flash_ext_stream_write(obj, addr, len, data); - __flash_ext_turnoff(); - - return status; -} - -int flash_stream_read(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data) -{ - return flash_ext_stream_read(obj, addr, len, data); -} - -int flash_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data) -{ - return flash_ext_stream_write(obj, addr, len, data); -} - -/* -Function Description: -This function performans the same functionality as the function flash_stream_write. -It enhances write performance by reducing overheads. -Users can use either of functions depending on their needs. - -* @brief Write a stream of data to specified address -* @param obj: Specifies the parameter of flash object. -* @param address: Specifies the address to be read. -* @param length: Specifies the length of the data to write. -* @param data: Specified the pointer of the data to be written. -* @retval status: Success:1 or Failure: Others. - -*/ - -int flash_ext_burst_write(flash_t *obj, uint32_t address ,uint32_t length, uint8_t *data) -{ - u32 OccuSize; - u32 ProgramSize; - u32 PageSize; - u8 flashtype = 0; - - PageSize = 256; - - __flash_ext_turnon(); - - flashtype = flashobj.SpicInitPara.flashtype; - OccuSize = address & 0xFF; - if((length >= PageSize) ||((length + OccuSize) >= PageSize)){ - ProgramSize = PageSize - OccuSize; - } else { - ProgramSize = length; - } - - flashobj.Length = length; - while(length > 0){ - if(OccuSize){ - SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length)); - // Wait spic busy done - SpicWaitBusyDoneRtl8195A(); - // Wait flash busy done (wip=0) - if(flashtype == FLASH_MICRON){ - SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); - } else { - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - } - - address += ProgramSize; - data += ProgramSize; - length -= ProgramSize; - OccuSize = 0; - } else{ - while((flashobj.Length) >= PageSize){ - SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length)); - // Wait spic busy done - SpicWaitBusyDoneRtl8195A(); - // Wait flash busy done (wip=0) - if(flashtype == FLASH_MICRON){ - SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); - } else { - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - } - - address += PageSize; - data += PageSize; - length -= PageSize; - } - flashobj.Length = length; - if((flashobj.Length) > 0){ - SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length)); - // Wait spic busy done - SpicWaitBusyDoneRtl8195A(); - // Wait flash busy done (wip=0) - if(flashtype == FLASH_MICRON){ - SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); - } else { - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - } - - break; - } - } - flashobj.Length = length; - } - __flash_ext_turnoff(); - return 0; - -} -/** - * @brief Read a stream of data from specified address - * @param obj: Specifies the parameter of flash object. - * @param address: Specifies the address to be read. - * @param len: Specifies the length of the data to read. - * @param data: Specified the address to save the readback data. - * @retval status: Success:1 or Failure: Others. - */ - -int flash_ext_burst_read(flash_t *obj, uint32_t address, uint32_t length, uint8_t *data) -{ - __flash_ext_turnon(); - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - SpicUserReadRtl8195A(length, address, data, SpicOneBitMode); - __flash_ext_turnoff(); - return 0; -} - -int flash_ext_get_status(flash_t *obj) -{ - uint8_t status = 0; - - __flash_ext_turnon(); - status = SpicGetFlashStatusRefinedRtl8195A(flashobj.SpicInitPara); - __flash_ext_turnoff(); - return status; -} - -/* -Function Description: -Please refer to the datatsheet of flash for more details of the content of status register. -The block protected area and the corresponding control bits are provided in the flash datasheet. - -* @brief Set Status register to enable desired operation -* @param obj: Specifies the parameter of flash object. -* @param data: Specifies which bit users like to set - ex: if users want to set the third bit, data = 0x8. - -*/ -int flash_ext_set_status(flash_t *obj, uint32_t data) -{ - __flash_ext_turnon(); - SpicSetFlashStatusRefinedRtl8195A(data, flashobj.SpicInitPara); - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - __flash_ext_turnoff(); - return 0; -} - -/* -Function Description: -This function aims to reset the status register, please make sure the operation is appropriate. -*/ -void flash_ext_reset_status(flash_t *obj) -{ - __flash_ext_turnon(); - SpicSetFlashStatusRefinedRtl8195A(0, flashobj.SpicInitPara); - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - __flash_ext_turnoff(); -} - -int flash_ext_get_extend_addr(flash_t *obj) -{ - uint8_t addr = 0; - - __flash_ext_turnon(); - addr = SpicGetExtendAddrRtl8195A(flashobj.SpicInitPara); - __flash_ext_turnoff(); - return addr; -} -/* -Function Description: -This function is only for Micron 512Mbit flash to access beyond 128Mbit by switching between four 128 Mbit area. -Please refer to flash datasheet for more information about memory mapping. -*/ - -int flash_ext_set_extend_addr(flash_t *obj, uint32_t data) -{ - __flash_ext_turnon(); - SpicSetExtendAddrRtl8195A(data, flashobj.SpicInitPara); - SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); - __flash_ext_turnoff(); - return 0; -} - - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_ext.h deleted file mode 100644 index b2d287bf619..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_ext.h +++ /dev/null @@ -1,53 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_FLASH_EXT_H -#define MBED_FLASH_EXT_H - -#include "device.h" -#include "flash_api.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define FLASH_PAGE_SIZE 256 -#define FLASH_SIZE 0x200000 -#define FLASH_OFS_START 0x0 -#define FLASH_OFS_END (FLASH_OFS_START + FLASH_SIZE) - -extern void flash_ext_erase_sector(flash_t *obj, uint32_t address); -extern void flash_ext_erase_block(flash_t * obj, uint32_t address); -extern int flash_ext_read_word(flash_t *obj, uint32_t address, uint32_t *data); -extern int flash_ext_write_word(flash_t *obj, uint32_t address, uint32_t data); -extern int flash_ext_stream_read(flash_t *obj, uint32_t address, uint32_t len, uint8_t *data); -extern int flash_ext_stream_write(flash_t *obj, uint32_t address, uint32_t len, const uint8_t *data); -extern int flash_stream_read(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data); -extern int flash_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data); -extern void flash_ext_write_protect(flash_t *obj, uint32_t protect); -extern int flash_ext_get_status(flash_t *obj); -extern int flash_ext_set_status(flash_t *obj, uint32_t data); -extern void flash_ext_reset_status(flash_t *obj); - -/* Internal functions for flash API */ -extern void __flash_ext_turnon(void); -extern void __flash_ext_turnoff(void); -extern void __flash_ext_erase_sector(flash_t *obj, uint32_t address); -extern int __flash_ext_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data); -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/gpio_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/gpio_api.c deleted file mode 100644 index 56285489a2e..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/gpio_api.c +++ /dev/null @@ -1,214 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "objects.h" -#include "pinmap.h" - -#if CONFIG_GPIO_EN - -#include "gpio_api.h" - -extern void HAL_GPIO_DeInit(HAL_GPIO_PIN *GPIO_Pin); - -// convert Mbed pin mode to HAL Pin Mode -const u8 GPIO_InPinMode[] = { - DIN_PULL_NONE, // PullNone - DIN_PULL_HIGH, // PullUp - DIN_PULL_LOW, // PullDown - DIN_PULL_NONE // OpenDrain -}; - -const u8 GPIO_SWPORT_DR_TBL[] = { - GPIO_PORTA_DR, - GPIO_PORTB_DR, - GPIO_PORTC_DR -}; - -const u8 GPIO_EXT_PORT_TBL[] = { - GPIO_EXT_PORTA, - GPIO_EXT_PORTB, - GPIO_EXT_PORTC -}; - -const u8 GPIO_SWPORT_DDR_TBL[] = { - GPIO_PORTA_DDR, - GPIO_PORTB_DDR, - GPIO_PORTC_DDR -}; - -void gpio_set_hal_pin_mode(gpio_t *obj) -{ - uint32_t mode; - - mode = obj->mode; - if (obj->direction == PIN_OUTPUT) { - if (mode == OpenDrain) { - obj->hal_pin.pin_mode = DOUT_OPEN_DRAIN; - } else { - obj->hal_pin.pin_mode = DOUT_PUSH_PULL; - } - } else { - if (mode < 4) { - obj->hal_pin.pin_mode = GPIO_InPinMode[mode]; - } else { - obj->hal_pin.pin_mode = DIN_PULL_NONE; - } - } -} - -uint32_t gpio_set(PinName pin) -{ - u32 ip_pin; - - DBG_ASSERT(pin != (PinName)NC); - pin_function(pin, 0); - ip_pin = HAL_GPIO_GetPinName((u32)pin); - - return ip_pin; -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - uint32_t pin_name; - - obj->pin = pin; - - if (pin == (PinName)NC) - return; - - obj->mode = PullNone; - obj->direction = PIN_INPUT; - pin_name = gpio_set(pin); // get the IP pin name - obj->hal_pin.pin_name = pin_name; - obj->hal_pin.pin_mode = DIN_PULL_NONE; - obj->hal_port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name); - obj->hal_pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name); - HAL_GPIO_Init(&obj->hal_pin); -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - obj->mode = mode; - gpio_set_hal_pin_mode(obj); - HAL_GPIO_Init(&obj->hal_pin); -} - -// Initial the Pin direction -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - obj->direction = direction; - gpio_set_hal_pin_mode(obj); - HAL_GPIO_Init(&obj->hal_pin); -} - -// Change the pin direction directly -void gpio_change_dir(gpio_t *obj, PinDirection direction) -{ - uint32_t reg_value; - uint8_t port_num; - uint8_t pin_num; - - obj->direction = direction; - gpio_set_hal_pin_mode(obj); - port_num = obj->hal_port_num; - pin_num = obj->hal_pin_num; - - reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DDR_TBL[port_num]); - if (direction) { - // Out - reg_value |= (1 << pin_num); - } else { - // In - reg_value &= ~(1 << pin_num); - } - HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DDR_TBL[port_num], reg_value); -} - -void gpio_write(gpio_t *obj, int value) -{ - HAL_GPIO_PIN *hal_pin=&obj->hal_pin; - volatile uint32_t reg_value; - uint8_t port_num; - uint8_t pin_num; - - if (hal_pin->pin_mode != DOUT_OPEN_DRAIN) { - port_num = obj->hal_port_num; - pin_num = obj->hal_pin_num; - - reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num]); - reg_value &= ~(1 << pin_num); - reg_value |= ((value&0x01)<< pin_num); - HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num], reg_value); - } else { - HAL_GPIO_WritePin(&obj->hal_pin, value); - } -} - -int gpio_read(gpio_t *obj) -{ - volatile uint32_t reg_value; - uint8_t port_num; - uint8_t pin_num; - HAL_GPIO_PIN_MODE pin_mode; - - port_num = obj->hal_port_num; - pin_num = obj->hal_pin_num; - pin_mode = obj->hal_pin.pin_mode; - - reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_EXT_PORT_TBL[port_num]); - if (pin_mode != DOUT_OPEN_DRAIN) { - return ((reg_value >> pin_num) & 0x01); - } else { - return (!((reg_value >> pin_num) & 0x01)); - } -} - -// This API only works for non-Open-Drain pin -void gpio_direct_write(gpio_t *obj, BOOL value) -{ - uint8_t port_num; - uint8_t pin_num; - uint32_t reg_value; - - port_num = obj->hal_port_num; - pin_num = obj->hal_pin_num; - - reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num]); - reg_value &= ~(1 << pin_num); - reg_value |= (value<< pin_num); - HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num], reg_value); -} - -void gpio_pull_ctrl(gpio_t *obj, PinMode pull_type) -{ - HAL_GPIO_PullCtrl((u32) obj->pin, (u32)pull_type); -} - -void gpio_deinit(gpio_t *obj) -{ - HAL_GPIO_DeInit(&obj->hal_pin); -} - -int gpio_is_connected(const gpio_t *obj) -{ - if(obj->pin != (PinName)NC){ - return 1; - } else { - return 0; - } -} - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/gpio_irq_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/gpio_irq_api.c deleted file mode 100644 index c00b9ba3699..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/gpio_irq_api.c +++ /dev/null @@ -1,86 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "objects.h" -#include "pinmap.h" - -#if CONFIG_GPIO_EN -#include "gpio_irq_api.h" - -extern void HAL_GPIO_DeInit(HAL_GPIO_PIN *GPIO_Pin); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - uint32_t pin_name; - - if (pin == NC) return -1; - - obj->pin = pin; - pin_name = HAL_GPIO_GetPinName((u32)pin);; // get the IP pin name - obj->hal_pin.pin_name = pin_name; - obj->hal_pin.pin_mode = INT_FALLING; // default use Falling trigger - obj->hal_port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name); - obj->hal_pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name); - HAL_GPIO_Irq_Init(&obj->hal_pin); - HAL_GPIO_UserRegIrq(&obj->hal_pin, (VOID*) handler, (VOID*) id); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - HAL_GPIO_UserUnRegIrq(&obj->hal_pin); - HAL_GPIO_DeInit(&obj->hal_pin); -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - HAL_GPIO_MaskIrq(&obj->hal_pin); - switch((uint32_t)event) { - case IRQ_RISE: - obj->hal_pin.pin_mode = INT_RISING; - break; - - case IRQ_FALL: - obj->hal_pin.pin_mode = INT_FALLING; - break; - - case IRQ_NONE: - break; - - default: - break; - } - HAL_GPIO_Init_8195a(&obj->hal_pin); - - HAL_GPIO_IntCtrl(&obj->hal_pin, enable); - if(enable){ - HAL_GPIO_UnMaskIrq(&obj->hal_pin); - } else{ - HAL_GPIO_MaskIrq(&obj->hal_pin); - } -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - HAL_GPIO_UnMaskIrq(&obj->hal_pin); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - HAL_GPIO_MaskIrq(&obj->hal_pin); -} -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/i2c_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/i2c_api.c deleted file mode 100644 index c29af82dd34..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/i2c_api.c +++ /dev/null @@ -1,564 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include -#include "objects.h" -#include "PinNames.h" -#include "hal_i2c.h" - -#if CONFIG_I2C_EN - -#include "pinmap.h" - -#ifdef CONFIG_MBED_ENABLED -#include "PeripheralPins.h" -#endif - -static int address_save_int[4]; -static int Byte_count[4]; -static u32 address_save[4]; -static uint16_t i2c_target_addr[4]; -static SAL_I2C_TRANSFER_BUF i2ctxtranbuf[4]; -static SAL_I2C_TRANSFER_BUF i2crxtranbuf[4]; -extern u32 ConfigDebugErr; -extern u32 ConfigDebuginfo; -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - int i2c_sel; - int i2c_idx; - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_USERCB_ADPT pSalI2CUserCBAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - - // Determine the I2C to use - int i2c_sda = (uint32_t)pinmap_peripheral(sda, PinMap_I2C_SDA); - int i2c_scl = (uint32_t)pinmap_peripheral(scl, PinMap_I2C_SCL); - ConfigDebugErr &= (~(_DBG_I2C_|_DBG_GDMA_)); - ConfigDebugInfo&= (~(_DBG_I2C_|_DBG_GDMA_)); - i2c_sel = pinmap_merge(i2c_sda, i2c_scl); - i2c_idx = RTL_GET_PERI_IDX(i2c_sel); - if (unlikely(i2c_idx == NC)) { - DBG_8195A("%s: Cannot find matched UART\n", __FUNCTION__); - return; - } - - /* Get I2C device handler */ - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)&(obj->SalI2CUserCBAdpt); - - - /*To assign the rest pointers*/ - pSalI2CMngtAdpt->MstRDCmdCnt = 0; - pSalI2CMngtAdpt->InnerTimeOut = 2000; // inner time-out count, 2000 ms - pSalI2CMngtAdpt->pSalHndPriv = &(obj->SalI2CHndPriv); - pSalI2CMngtAdpt->pSalHndPriv->ppSalI2CHnd = (void**)&(pSalI2CMngtAdpt->pSalHndPriv); - - /* To assign the default (ROM) HAL OP initialization function */ -#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) - pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_Patch; -#elif defined(CONFIG_CHIP_E_CUT) - pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_V04; -#endif - /* To assign the default (ROM) HAL GDMA OP initialization function */ - pSalI2CMngtAdpt->pHalGdmaOpInit = HalGdmaOpInit; - - /* To assign the default (ROM) SAL interrupt function */ -#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) - pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_Patch; -#elif defined(CONFIG_CHIP_E_CUT) - pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_V04; -#endif - - /* To assign the default (ROM) SAL DMA TX interrupt function */ - pSalI2CMngtAdpt->pSalDMATxIrqFunc = I2CTXGDMAISRHandle; - - /* To assign the default (ROM) SAL DMA RX interrupt function */ - pSalI2CMngtAdpt->pSalDMARxIrqFunc = I2CRXGDMAISRHandle; - - pSalI2CMngtAdpt->pHalInitDat = &(obj->HalI2CInitData); - pSalI2CMngtAdpt->pHalOp = &(obj->HalI2COp); - pSalI2CMngtAdpt->pIrqHnd = &(obj->I2CIrqHandleDat); - pSalI2CMngtAdpt->pHalTxGdmaAdp = &(obj->HalI2CTxGdmaAdpt); - pSalI2CMngtAdpt->pHalRxGdmaAdp = &(obj->HalI2CRxGdmaAdpt); - pSalI2CMngtAdpt->pHalGdmaOp = &(obj->HalI2CGdmaOp); - pSalI2CMngtAdpt->pIrqTxGdmaHnd = &(obj->I2CTxGdmaIrqHandleDat); - pSalI2CMngtAdpt->pIrqRxGdmaHnd = &(obj->I2CRxGdmaIrqHandleDat); - pSalI2CMngtAdpt->pUserCB = &(obj->SalI2CUserCB); - pSalI2CMngtAdpt->pDMAConf = &(obj->SalI2CDmaUserDef); - - /* Assign the private SAL handle to public SAL handle */ - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - - /* Assign the internal HAL initial data pointer to the SAL handle */ - pSalI2CHND->pInitDat = pSalI2CMngtAdpt->pHalInitDat; - - /* Assign the internal user callback pointer to the SAL handle */ - pSalI2CHND->pUserCB = pSalI2CMngtAdpt->pUserCB; - - /* Assign the internal user define DMA configuration to the SAL handle */ - pSalI2CHND->pDMAConf = pSalI2CMngtAdpt->pDMAConf; - - /*To assign user callback pointers*/ - pSalI2CMngtAdpt->pUserCB->pTXCB = pSalI2CUserCBAdpt; - pSalI2CMngtAdpt->pUserCB->pTXCCB = (pSalI2CUserCBAdpt+1); - pSalI2CMngtAdpt->pUserCB->pRXCB = (pSalI2CUserCBAdpt+2); - pSalI2CMngtAdpt->pUserCB->pRXCCB = (pSalI2CUserCBAdpt+3); - pSalI2CMngtAdpt->pUserCB->pRDREQCB = (pSalI2CUserCBAdpt+4); - pSalI2CMngtAdpt->pUserCB->pERRCB = (pSalI2CUserCBAdpt+5); - pSalI2CMngtAdpt->pUserCB->pDMATXCB = (pSalI2CUserCBAdpt+6); - pSalI2CMngtAdpt->pUserCB->pDMATXCCB = (pSalI2CUserCBAdpt+7); - pSalI2CMngtAdpt->pUserCB->pDMARXCB = (pSalI2CUserCBAdpt+8); - pSalI2CMngtAdpt->pUserCB->pDMARXCCB = (pSalI2CUserCBAdpt+9); - pSalI2CMngtAdpt->pUserCB->pGENCALLCB= (pSalI2CUserCBAdpt+10); - - /* Set I2C Device Number */ - pSalI2CHND->DevNum = i2c_idx; - - /* Load I2C default value */ - RtkI2CLoadDefault(pSalI2CHND); - - /* Assign I2C Pin Mux */ - pSalI2CHND->PinMux = RTL_GET_PERI_SEL(i2c_sel); - pSalI2CHND->OpType = I2C_INTR_TYPE; - pSalI2CHND->I2CMaster = I2C_MASTER_MODE; - pSalI2CHND->I2CSpdMod = I2C_SS_MODE; - pSalI2CHND->I2CClk = 100; - pSalI2CHND->I2CAckAddr = 0; - pSalI2CHND->TimeOut = 300; - pSalI2CHND->AddRtyTimeOut = 3000; - pSalI2CHND->I2CExd |= (I2C_EXD_MTR_ADDR_RTY); - - pSalI2CMngtAdpt->InnerTimeOut = pSalI2CHND->TimeOut; - - /* Init I2C now */ - pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum]; - HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); - HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat); - RtkI2CInitForPS(pSalI2CHND); -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - - uint16_t i2c_default_clk = (uint16_t) pSalI2CHND->I2CClk; - uint16_t i2c_user_clk = (uint16_t) (hz/1000); - - - if (i2c_default_clk != i2c_user_clk) { - /* Deinit I2C first */ - i2c_reset(obj); - if (i2c_user_clk <= 100) { - pSalI2CHND->I2CSpdMod = I2C_SS_MODE; - } else if ((i2c_user_clk > 100) && (i2c_user_clk <= 400)) { - pSalI2CHND->I2CSpdMod = I2C_FS_MODE; - } else if (i2c_user_clk > 400) { - pSalI2CHND->I2CSpdMod = I2C_HS_MODE; - } else { - pSalI2CHND->I2CSpdMod = I2C_SS_MODE; - } - - /* Load the user defined I2C clock */ - pSalI2CHND->I2CClk = i2c_user_clk; - - /* Init I2C now */ - pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum]; - HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); - HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat); - RtkI2CInitForPS(pSalI2CHND); - } -} - -inline int i2c_start(i2c_t *obj) -{ - _memset(address_save_int , 0, sizeof(address_save_int)); - _memset(Byte_count , 0, sizeof(Byte_count)); - _memset(address_save, 0, sizeof(address_save)); - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - return 0; -} - -extern u32 HalDelayUs(IN u32 us); - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - u32 I2CInTOTcnt = 0; - u32 InTimeoutCount = 0; - u32 InStartCount = 0; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - address = (address & 0xFE ) >>1; - - if (i2c_target_addr[pSalI2CHND->DevNum] != address) { - pSalI2CHND->pInitDat->I2CAckAddr = address; - i2c_target_addr[pSalI2CHND->DevNum] = address; - HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); - } - - /* Check if the it's the last byte or not */ - pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS); - if (!stop) { - pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS; - } - - pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum]; - pSalI2CHND->pRXBuf->DataLen = length; - pSalI2CHND->pRXBuf->TargetAddr= address;//pSalI2CHND->I2CAckAddr; - pSalI2CHND->pRXBuf->RegAddr = 0; - pSalI2CHND->pRXBuf->pDataBuf = (u8 *)data; - - if (RtkI2CReceive(pSalI2CHND) != HAL_OK) { - length = length - pSalI2CHND->pRXBuf->DataLen; - return ((int)length); - } else { - /* Calculate user time out parameters */ - I2CInTOTcnt = 300; - if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOUT_ENDLESS)) { - InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); - InStartCount = HalTimerOp.HalTimerReadCount(1); - } - while((pSalI2CHND->DevSts != I2C_STS_IDLE) && - (pSalI2CHND->DevSts != I2C_STS_ERROR) && - (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) { - /* Time-Out check */ - if (InTimeoutCount > 0) { - if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { - pSalI2CHND->DevSts = I2C_STS_TIMEOUT; - pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; - - return ((int)(length)); - } - } else { - if (I2CInTOTcnt == 0) { - pSalI2CHND->DevSts = I2C_STS_TIMEOUT; - pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; - - return ((int)(length)); - } - } - } - if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) { - return ((int)(length - pSalI2CHND->pRXBuf->DataLen)); - } else { - return ((int)(length)); - } - } -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - u32 I2CInTOTcnt = 0; - u32 InTimeoutCount = 0; - u32 InStartCount = 0; - - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - address = (address & 0xFE ) >>1; - - pSalI2CHND->pInitDat->I2CAckAddr = address; - i2c_target_addr[pSalI2CHND->DevNum] = address; - HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); - - /* Check if the it's the last byte or not */ - pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS); - if (!stop) { - pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS; - } - - pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum]; - pSalI2CHND->pTXBuf->DataLen = length; - pSalI2CHND->pTXBuf->TargetAddr= address; - pSalI2CHND->pTXBuf->RegAddr = 0; - pSalI2CHND->pTXBuf->pDataBuf = (u8 *)data; - - if (RtkI2CSend(pSalI2CHND) != HAL_OK) { - length = length - pSalI2CHND->pTXBuf->DataLen; - return ((int)length); - } else { - /* Calculate user time out parameters */ - I2CInTOTcnt = 300; - if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOUT_ENDLESS)) { - InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); - InStartCount = HalTimerOp.HalTimerReadCount(1); - } - while((pSalI2CHND->DevSts != I2C_STS_IDLE) && - (pSalI2CHND->DevSts != I2C_STS_ERROR) && - (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) { - /* Time-Out check */ - if (InTimeoutCount > 0) { - if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { - pSalI2CHND->DevSts = I2C_STS_TIMEOUT; - pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO; - return ((int)(length)); - } - } else { - if (I2CInTOTcnt == 0) { - pSalI2CHND->DevSts = I2C_STS_TIMEOUT; - pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO; - return ((int)(length)); - } - } - } - - if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) { - return ((int)(length - pSalI2CHND->pTXBuf->DataLen)); - } else { - return ((int)(length)); - } - } -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - uint8_t i2cdatlocal; - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - - /* Check if the it's the last byte or not */ - pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS); - if (!last) { - pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS; - } - - pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum]; - pSalI2CHND->pRXBuf->DataLen = 1; - pSalI2CHND->pRXBuf->TargetAddr= i2c_target_addr[pSalI2CHND->DevNum]; - pSalI2CHND->pRXBuf->RegAddr = 0; - pSalI2CHND->pRXBuf->pDataBuf = &i2cdatlocal; - RtkI2CReceive(pSalI2CHND); - - return (int)i2cdatlocal; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - u8 * dp = (u8 *)&address_save[pSalI2CHND->DevNum]; - if(Byte_count[pSalI2CHND->DevNum]<3){ - dp[Byte_count[pSalI2CHND->DevNum]] = data; - Byte_count[pSalI2CHND->DevNum]++; - if(Byte_count[pSalI2CHND->DevNum]==3){ - address_save_int[pSalI2CHND->DevNum] = (dp[1]<<8)+dp[2]; - } - return 1; - } - int address = (dp[0] & 0xFE ) >> 1; - dp[1]= (unsigned char)(address_save_int[pSalI2CHND->DevNum] >> 8); - dp[2]= (unsigned char)(address_save_int[pSalI2CHND->DevNum] & 0xFF); - dp[3]= (unsigned char)data; - - pSalI2CHND->pInitDat->I2CAckAddr = address; - i2c_target_addr[pSalI2CHND->DevNum] = address; - HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); - - pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS); - pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum]; - pSalI2CHND->pTXBuf->DataLen = 3; - pSalI2CHND->pTXBuf->TargetAddr= i2c_target_addr[pSalI2CHND->DevNum]; - pSalI2CHND->pTXBuf->RegAddr = 0; - pSalI2CHND->pTXBuf->pDataBuf = dp+1; - - if (RtkI2CSend(pSalI2CHND) != HAL_OK) { - return 0; - } - address_save_int[pSalI2CHND->DevNum]++; - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - - /* Deinit I2C directly */ - RtkI2CDeInitForPS(pSalI2CHND); -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - address = (address & 0xFE ) >>1; - - uint16_t i2c_user_addr = (uint16_t) address; - - if (i2c_target_addr[pSalI2CHND->DevNum] != i2c_user_addr) { - pSalI2CHND->pInitDat->I2CAckAddr = address; - i2c_target_addr[pSalI2CHND->DevNum] = address; - HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat); - } -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - - /* Deinit I2C first */ - i2c_reset(obj); - - /* Load the user defined I2C clock */ - pSalI2CHND->I2CMaster = I2C_MASTER_MODE; - if (enable_slave) - pSalI2CHND->I2CMaster = I2C_SLAVE_MODE; - - /* Init I2C now */ - RtkI2CInitForPS(pSalI2CHND); - - pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum]; - HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat); -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - int i2cslvrevsts = NoData; - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - - i2cslvrevsts = RtkSalI2CSts(pSalI2CHND); - return i2cslvrevsts; -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - u32 I2CInTOTcnt = 0; - u32 InTimeoutCount = 0; - u32 InStartCount = 0; - - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - - pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum]; - pSalI2CHND->pRXBuf->DataLen = length; - pSalI2CHND->pRXBuf->pDataBuf = (u8 *)data; - - if (RtkI2CReceive(pSalI2CHND) != HAL_OK) { - return 0; //error - } else { - /* Calculate user time out parameters */ - I2CInTOTcnt = 300; - if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOUT_ENDLESS)) { - InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); - InStartCount = HalTimerOp.HalTimerReadCount(1); - } - while((pSalI2CHND->DevSts != I2C_STS_IDLE) && - (pSalI2CHND->DevSts != I2C_STS_ERROR) && - (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) { - /* Time-Out check */ - if (InTimeoutCount > 0) { - if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { - pSalI2CHND->DevSts = I2C_STS_TIMEOUT; - pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; - return ((int)(length)); - } - } else { - if (I2CInTOTcnt == 0) { - pSalI2CHND->DevSts = I2C_STS_TIMEOUT; - pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; - return ((int)(length)); - } - } - } - - if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) { - return ((int)(length - pSalI2CHND->pTXBuf->DataLen)); - } else { - return ((int)(length)); - } - } -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); - - pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum]; - pSalI2CHND->pTXBuf->DataLen = length; - pSalI2CHND->pTXBuf->pDataBuf = (u8 *)data; - - if (RtkI2CSend(pSalI2CHND) != HAL_OK) { - return 0; //error - } - - return 1; -} - -#endif // CONFIG_I2C_SLAVE_EN - -#endif // CONFIG_I2C_EN - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/log_uart_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/log_uart_api.c deleted file mode 100644 index f44f73588b4..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/log_uart_api.c +++ /dev/null @@ -1,502 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "objects.h" -#include "log_uart_api.h" - -#ifdef CONFIG_MBED_ENABLED -#include "platform_stdlib.h" -#endif - -#include - -const u32 log_uart_support_rate[] = { - UART_BAUD_RATE_2400, UART_BAUD_RATE_4800, UART_BAUD_RATE_9600, - UART_BAUD_RATE_19200, UART_BAUD_RATE_38400, UART_BAUD_RATE_57600, - UART_BAUD_RATE_115200, UART_BAUD_RATE_921600, UART_BAUD_RATE_1152000, - - 0xFFFFFFFF -}; - -extern HAL_TIMER_OP HalTimerOp; - -extern u32 ConfigDebugErr; -extern u32 ConfigDebugWarn; -extern u32 ConfigDebugInfo; -extern u32 CfgSysDebugErr; -extern u32 CfgSysDebugInfo; -extern u32 CfgSysDebugWarn; - -extern HAL_Status RuartIsTimeout (u32 StartCount, u32 TimeoutCnt); -extern u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter); -extern VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter); -extern VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter); -extern VOID HalLogUartIrqHandle(VOID * Data); - -int32_t log_uart_init (log_uart_t *obj, int baudrate, int data_bits, SerialParity parity, int stop_bits) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter; - int i; - - _memset((void*)obj, 0, sizeof(log_uart_t)); - pUartAdapter = &obj->log_hal_uart; - // Check Baud rate - for (i=0; log_uart_support_rate[i]!=0xFFFFFF; i++) { - if (log_uart_support_rate[i] == (u32)baudrate) { - break; - } - } - if (log_uart_support_rate[i]== 0xFFFFFF) { - DBG_UART_ERR("log_uart_init: Not support Baud Rate %d\n", baudrate); - return -1; - } - // check word width - if ((data_bits < 5) || (data_bits > 8)) { - DBG_UART_ERR("log_uart_init: Not support Word Width %d\n", data_bits); - return -1; - } - - //4 Inital Log uart - pUartAdapter->BaudRate = baudrate; - pUartAdapter->DataLength = data_bits-5; - pUartAdapter->FIFOControl = FCR_FIFO_EN | FCR_TX_TRIG_HF | FCR_RX_TRIG_HF; - // only enable Rx linstatus at initial, - // Tx & Rx interrupt will be enabled @ transfer start time - pUartAdapter->IntEnReg = IER_ELSI; - switch (parity) { - case ParityNone: - pUartAdapter->Parity = LCR_PARITY_NONE; - break; - - case ParityOdd: - pUartAdapter->Parity = LCR_PARITY_ODD; - break; - - case ParityEven: - pUartAdapter->Parity = LCR_PARITY_EVEN; - break; - - default: - DBG_UART_ERR("log_uart_init: Not support parity type %d\n", parity); - return -1; - } - - if (stop_bits > 1) { - // if width is 5 bits, stop bit will be 1.5 bit - pUartAdapter->Stop = LCR_STOP_2B; - } else { - pUartAdapter->Stop = LCR_STOP_1B; - } - - //4 Initial Log Uart - HalLogUartInitSetting(pUartAdapter); - - // disable all debug message - ConfigDebugErr = 0; - ConfigDebugWarn = 0; - ConfigDebugInfo = 0; - CfgSysDebugErr = 0; - CfgSysDebugInfo = 0; - CfgSysDebugWarn = 0; - - return 0; -} - -void log_uart_free(log_uart_t *obj) -{ - LOG_UART_ADAPTER UartAdapter; - - // Recover the Log UART for debug message printing - //4 Release log uart reset and clock - LOC_UART_FCTRL(OFF); - LOC_UART_FCTRL(ON); - ACTCK_LOG_UART_CCTRL(ON); - - //4 Inital Log uart - UartAdapter.BaudRate = UART_BAUD_RATE_38400; - UartAdapter.DataLength = UART_DATA_LEN_8BIT; - UartAdapter.FIFOControl = 0xC1; - UartAdapter.IntEnReg = 0x00; - UartAdapter.Parity = UART_PARITY_DISABLE; - UartAdapter.Stop = UART_STOP_1BIT; - - // un_register current IRQ first - InterruptUnRegister(&(obj->log_hal_uart.IrqHandle)); - - //4 Initial Log Uart - HalLogUartInit(UartAdapter); -} - -void log_uart_baud(log_uart_t *obj, int baudrate) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter; - int i; - - pUartAdapter = &obj->log_hal_uart; - // Check Baud rate - for (i=0; log_uart_support_rate[i]!=0xFFFFFFFF; i++) { - if (log_uart_support_rate[i] == (u32)baudrate) { - break; - } - } - if (log_uart_support_rate[i]== 0xFFFFFF) { - DBG_UART_ERR("log_uart_baud: Not support Baud Rate %d\n", baudrate); - return; - } - pUartAdapter->BaudRate = baudrate; - HalLogUartSetBaudRate(pUartAdapter); -} - -void log_uart_format(log_uart_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter; - pUartAdapter = &obj->log_hal_uart; - - // check word width - if ((data_bits < 5) || (data_bits > 8)) { - DBG_UART_ERR("log_uart_format: Not support Word Width %d\n", data_bits); - return; - } - - //4 Inital Log uart - pUartAdapter->DataLength = data_bits - 5; - switch (parity) { - case ParityNone: - pUartAdapter->Parity = LCR_PARITY_NONE; - break; - - case ParityOdd: - pUartAdapter->Parity = LCR_PARITY_ODD; - break; - - case ParityEven: - pUartAdapter->Parity = LCR_PARITY_EVEN; - break; - - default: - DBG_UART_ERR("log_uart_format: Not support parity type %d\n", parity); - return; - } - - if (stop_bits > 1) { - // if width is 5 bits, stop bit will be 1.5 bit - pUartAdapter->Stop = LCR_STOP_2B; - } else { - pUartAdapter->Stop = LCR_STOP_1B; - } - - HalLogUartSetLineCtrl(pUartAdapter); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -void log_uart_irq_handler(log_uart_t *obj, loguart_irq_handler handler, uint32_t id) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter; - - pUartAdapter = &(obj->log_hal_uart); - pUartAdapter->api_irq_handler = handler; - pUartAdapter->api_irq_id = id; -} - -void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter; - u8 int_en = 0; - - pUartAdapter = &(obj->log_hal_uart); - - switch (irq) { - case IIR_RX_RDY: - int_en = IER_ERBFI; - break; - - case IIR_THR_EMPTY: - int_en = IER_ETBEI; - break; - - case IIR_RX_LINE_STATUS: - int_en = IER_ELSI; - break; - - case IIR_MODEM_STATUS: - int_en = IER_EDSSI; - break; - - default: - DBG_UART_WARN("log_uart_irq_set: Unknown Irq Id\n"); - return; - } - - if (enable) { - pUartAdapter->IntEnReg |= int_en; - } else { - // disable - pUartAdapter->IntEnReg &= (~int_en); - } - HalLogUartSetIntEn(pUartAdapter); -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -char log_uart_getc(log_uart_t *obj) -{ - while (!log_uart_readable(obj)); - return (char)(HAL_UART_READ32(UART_REV_BUF_OFF) & 0xFF); -} - -void log_uart_putc(log_uart_t *obj, char c) -{ - while (!log_uart_writable(obj)); - HAL_UART_WRITE8(UART_TRAN_HOLD_OFF, c); -} - -int log_uart_readable(log_uart_t *obj) -{ - volatile u8 line_status; - - line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF); - - if (line_status & LSR_DR) { - return 1; - } else { - return 0; - } -} - -int log_uart_writable(log_uart_t *obj) -{ - volatile u8 line_status; - - line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF); - if (line_status & LSR_THRE) { - return 1; - } else { - return 0; - } -} - -void log_uart_clear(log_uart_t *obj) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); - - HalLogUartRstFIFO(pUartAdapter, (LOG_UART_RST_TX_FIFO|LOG_UART_RST_TX_FIFO)); - pUartAdapter->TxCount = 0; - pUartAdapter->RxCount = 0; -} - -void log_uart_clear_tx(log_uart_t *obj) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); - - HalLogUartRstFIFO(pUartAdapter, LOG_UART_RST_TX_FIFO); - pUartAdapter->TxCount = 0; -} - -void log_uart_clear_rx(log_uart_t *obj) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); - - HalLogUartRstFIFO(pUartAdapter, LOG_UART_RST_RX_FIFO); - pUartAdapter->RxCount = 0; -} - -void log_uart_break_set(log_uart_t *obj) -{ - u32 RegValue; - - RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF); - RegValue |= LCR_BC; - HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RegValue); -} - -void log_uart_break_clear(log_uart_t *obj) -{ - u32 RegValue; - - RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF); - RegValue &= ~LCR_BC; - HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RegValue); -} - -void log_uart_tx_comp_handler(log_uart_t *obj, void *handler, uint32_t id) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); - - pUartAdapter->TxCompCallback = (void(*)(void*))handler; - pUartAdapter->TxCompCbPara = (void*)id; -} - -void log_uart_rx_comp_handler(log_uart_t *obj, void *handler, uint32_t id) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - - pUartAdapter->RxCompCallback = (void(*)(void*))handler; - pUartAdapter->RxCompCbPara = (void*)id; -} - -void log_uart_line_status_handler(log_uart_t *obj, void *handler, uint32_t id) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - - pUartAdapter->LineStatusCallback = (void(*)(void*, u8))handler; - pUartAdapter->LineStatusCbPara = (void*)id; -} - -// Blocked(busy wait) receive, return received bytes count -int32_t log_uart_recv (log_uart_t *obj, char *prxbuf, uint32_t len, uint32_t timeout_ms) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - - return (int32_t)HalLogUartRecv(pUartAdapter, (u8 *)prxbuf, len, timeout_ms); -} - -// Blocked(busy wait) send, return transmitted bytes count -int32_t log_uart_send (log_uart_t *obj, char *ptxbuf, uint32_t len, uint32_t timeout_ms) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - - return (int32_t)HalLogUartSend(pUartAdapter, (u8 *)ptxbuf, len, timeout_ms); -} - -// Interrupt mode(no wait) receive, return HAL function result -int32_t log_uart_recv_stream (log_uart_t *obj, char *prxbuf, uint32_t len) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - int ret; - - ret = (int)HalLogUartIntRecv(pUartAdapter, (u8*)prxbuf, len); - return (ret); -} - -// Interrupt Mode(no wait) send, return HAL function result -int32_t log_uart_send_stream (log_uart_t *obj, char *ptxbuf, uint32_t len) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - int ret; - - ret = (int)HalLogUartIntSend(pUartAdapter, (u8*)ptxbuf, len); - return (ret); -} - -// Interrupt mode(no wait) receive with timeout -// return the byte count received before timeout, or error(<0) -int32_t log_uart_recv_stream_timeout (log_uart_t *obj, char *prxbuf, uint32_t len, - uint32_t timeout_ms, void *force_cs) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - uint32_t TimeoutCount=0, StartCount; - int ret; - void (*task_yield)(void); - - task_yield = NULL; - ret = (int)HalLogUartIntRecv(pUartAdapter, (u8*)prxbuf, len); - - if ((ret == HAL_OK) && (timeout_ms > 0)) { - TimeoutCount = (timeout_ms*1000/TIMER_TICK_US); - StartCount = HalTimerOp.HalTimerReadCount(1); - task_yield = (void (*)(void))force_cs; - while (pUartAdapter->RxCount > 0) { - if (HAL_TIMEOUT == RuartIsTimeout(StartCount, TimeoutCount)) { - HalLogUartAbortIntRecv(pUartAdapter); - break; - } - if (NULL != task_yield) { - task_yield(); - } - } - return (len - pUartAdapter->RxCount); - } else { - return (-ret); - } -} - -// Abort Interrupt Mode TX and return how many bytes data has been sent -int32_t log_uart_send_stream_abort (log_uart_t *obj) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - int ret; - - HalLogUartAbortIntSend(pUartAdapter); - - ret = (u32)pUartAdapter->pTxBuf - (u32)pUartAdapter->pTxStartAddr; - return (ret); -} - -// Abort Interrupt Mode RX and return how many bytes data has been received -int32_t log_uart_recv_stream_abort (log_uart_t *obj) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - int ret; - - HalLogUartAbortIntRecv(pUartAdapter); - - ret = (u32)pUartAdapter->pRxBuf - (u32)pUartAdapter->pRxStartAddr; - return (ret); -} - -void log_uart_disable (log_uart_t *obj) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - - HalLogUartDisable(pUartAdapter); -} - -void log_uart_enable (log_uart_t *obj) -{ - HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart); - - HalLogUartEnable(pUartAdapter); -} - -// to read Line-Status register -// Bit 0: RX Data Ready -// Bit 1: Overrun Error -// Bit 2: Parity Error -// Bit 3: Framing Error -// Bit 4: Break Interrupt (received data input is held in 0 state for a longer than a full word tx time) -// Bit 5: TX FIFO empty (THR empty) -// Bit 6: TX FIFO empty (THR & TSR both empty) -// Bit 7: Receiver FIFO Error (parity error, framing error or break indication) -uint8_t log_uart_raed_lsr(log_uart_t *obj) -{ - uint8_t LineStatus; - - LineStatus = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF); - - return LineStatus; -} - -// to read Modem-Status register -// Bit 0: DCTS, The CTS line has changed its state -// Bit 1: DDSR, The DSR line has changed its state -// Bit 2: TERI, RI line has changed its state from low to high state -// Bit 3: DDCD, DCD line has changed its state -// Bit 4: Complement of the CTS input -// Bit 5: Complement of the DSR input -// Bit 6: Complement of the RI input -// Bit 7: Complement of the DCD input -uint8_t log_uart_raed_msr(log_uart_t *obj) -{ - uint8_t RegValue; - - RegValue = HAL_UART_READ8(UART_MODEM_STATUS_REG_OFF); - return RegValue; -} - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/log_uart_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/log_uart_api.h deleted file mode 100644 index e37696914eb..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/log_uart_api.h +++ /dev/null @@ -1,331 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef LOG_UART_API_H -#define LOG_UART_API_H - -#if defined(CONFIG_PLATFORM_8195A) && (CONFIG_PLATFORM_8195A == 1) -#include "device.h" -#include "serial_api.h" -#include "hal_log_uart.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup log_uart LOG_UART - * @ingroup hal - * @brief log_uart functions - * @{ - */ - -///@name Ameba1 Only -///@{ - -/****************************************************** - * Type Definitions - ******************************************************/ -/** Log uart irq handler function pointer type - * - * @param id : The argument for log uart interrupt handler - * @param event : The log uart interrupt indication ID. More details is shown in hal_log_uart.h - */ -typedef void (*loguart_irq_handler)(uint32_t id, LOG_UART_INT_ID event); -typedef struct log_uart_s log_uart_t; - -/****************************************************** - * Function Declarations - ******************************************************/ -/** - * @brief Initialize Realtek log uart. - * Initialize the required parts of the log uart. - * i.e. baudrate, data bits, parity, etc. - * @param[in] obj: The address of log uart object. - * @param[in] baudrate: Baud rate of the log uart object. - * @param[in] data_bits: Data bits of the log uart object. - * @param[in] parity: Parity type of the log uart object - - ParityNone, - Do not use parity - - ParityOdd, - Use odd parity - - ParityEven, - Use even parity - - ParityForced1, - Use even parity, the same as ParityEven - - ParityForced0 - Use odd parity, the same as ParityOdd - * @param[in] stop_bits: The number of stop bits for the log uart object. - * @return 0 if initialization is successful, -1 otherwise - */ -int32_t log_uart_init(log_uart_t *obj, int baudrate, int data_bits, SerialParity parity, int stop_bits); - -/** - * @brief Release the resources related to Realtek log uart. - - * @param[in] obj: The address of log uart object. - * @return None - */ -void log_uart_free(log_uart_t *obj); - -/** - * @brief Set the baud rate of log uart. - - * @param[in] obj: The address of log uart object. - * @param[in] baudrate: Baud rate of the log uart object. - * @return None - */ -void log_uart_baud(log_uart_t *obj, int baudrate); - -/** - * @brief Set parameters for log uart. - * including data bits, parity type and stop bits - - * @param[in] obj: The address of log uart object. - * @param[in] data_bits: Data bits of log uart object. - * @param[in] parity: Parity type of the log uart object - - ParityNone, - Do not use parity - - ParityOdd, - Use odd parity - - ParityEven, - Use even parity - - ParityForced1, - Use even parity, the same as ParityEven - - ParityForced0 - Use odd parity, the same as ParityOdd - * @param[in] stop_bits: The number of stop bits for the log uart object. - * @return None - */ -void log_uart_format(log_uart_t *obj, int data_bits, SerialParity parity, int stop_bits); - -/** - * @brief Set irq handler for log uart. - * @param[in] obj: The address of log uart object. - * @param[in] handler: The interrupt handler for log uart. - * @param[in] id: The argument for log uart interrupt handler. - * @return None - */ -void log_uart_irq_handler(log_uart_t *obj, loguart_irq_handler handler, uint32_t id); - -/** - * @brief Enable/disable the specific irq indication ID. - * @param[in] obj: The address of log uart object. - * @param[in] irq: The log uart interrupt indication ID which will be enabled/disabled. - * @param[in] enable: 1 enable, 0 disable - * @return None - */ -void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable); - -/** - * @brief Read one character from log uart. - This function will block untill the log uart gets something to read - * @param[in] obj: The address of log uart object. - * @return the character read from log uart - */ -char log_uart_getc(log_uart_t *obj); - -/** - * @brief Write one character to log uart. - This function will block untill the data is successfully written to log uart - * @param[in] obj: The address of log uart object. - * @param[in] c: The one byte data to be written to log uart. - * @return None - */ -void log_uart_putc(log_uart_t *obj, char c); - -/** - * @brief Check whether log uart is ready to read data - * @param[in] obj: The address of log uart object. - * @return 1 if there is data at log uart to be read, 0 otherwise - */ -int log_uart_readable(log_uart_t *obj); - -/** - * @brief Check whether log uart is ready to write data - * @param[in] obj: The address of log uart object. - * @return 1 if log uart is ready for writing, 0 otherwise - */ -int log_uart_writable(log_uart_t *obj); - -/** - * @brief Clear both data at log uart - This function will clear data in both TX FIFO and RX FIFO of log uart - * @param[in] obj: The address of log uart object. - * @return None - */ -void log_uart_clear(log_uart_t *obj); - -/** - * @brief Clear TX FIFO of log uart - * @param[in] obj: The address of log uart object. - * @return None - */ -void log_uart_clear_tx(log_uart_t *obj); - -/** - * @brief Clear RX FIFO of log uart - * @param[in] obj: The address of log uart object. - * @return None - */ -void log_uart_clear_rx(log_uart_t *obj); - -/** - * @brief Set break control for log uart - * @param[in] obj: The address of log uart object. - * @return None - */ -void log_uart_break_set(log_uart_t *obj); - -/** - * @brief Clear break control for log uart - * @param[in] obj: The address of log uart object. - * @return None - */ -void log_uart_break_clear(log_uart_t *obj); - -/** - * @brief Set the handler for complete TX - * @param[in] obj: The address of log uart object. - * @param[in] handler: The function which is called when log uart has finished transmitting data. - * @param[in] id: The parameter for handler. - * @return None - */ -void log_uart_tx_comp_handler(log_uart_t *obj, void *handler, uint32_t id); - -/** - * @brief Set the handler for complete RX - * @param[in] obj: The address of log uart object. - * @param[in] handler: The function which is called when log uart has finished receving data - * @param[in] id: The parameter for handler. - * @return None - */ -void log_uart_rx_comp_handler(log_uart_t *obj, void *handler, uint32_t id); - -/** - * @brief Set the handler for line status - * @param[in] obj: The address of log uart object. - * @param[in] handler: The function which is called when log uart gets an line status indication ID. - * @param[in] id: The parameter for handler. - * @return None - */ -void log_uart_line_status_handler(log_uart_t *obj, void *handler, uint32_t id); - -/** - * @brief Read data from log uart in blocking mode. - * @param[in] obj: The address of log uart object. - * @param[out] prxbuf: The buffer to store received data. - * @param[in] len: The maximum length of data to be read - * @param[in] timeout_ms: Blocking time in ms. - * @return the length of received data in bytes - */ -int32_t log_uart_recv(log_uart_t *obj, char *prxbuf, uint32_t len, uint32_t timeout_ms); - -/** - * @brief Send data to log uart in blocking mode - * @param[in] obj: The address of log uart object. - * @param[in] ptxbuf: Data buffer to be sent to log uart - * @param[in] len: Length of data to be sent to log uart - * @param[in] timeout_ms: Blocking time in ms. - * @return the length of sent data in bytes - */ -int32_t log_uart_send(log_uart_t *obj, char *ptxbuf, uint32_t len, uint32_t timeout_ms); - -/** - * @brief Read data from log uart in interrupt mode(Non-blocking) - * @param[in] obj: The address of log uart object. - * @param[out] prxbuf: The buffer to store received data. - * @param[in] len: The maximum length of data to be read - * @return 0 if success - */ -int32_t log_uart_recv_stream(log_uart_t *obj, char *prxbuf, uint32_t len); - -/** - * @brief Send data to log uart in interrupt mode(Non-blocking) - * @param[in] obj: The address of log uart object. - * @param[in] ptxbuf: Data buffer to be sent to log uart - * @param[in] len: Length of data to be sent to log uart - * @return 0 if success - */ -int32_t log_uart_send_stream(log_uart_t *obj, char *ptxbuf, uint32_t len); - -/** - * @brief Read data from log uart with a given timeout in interrupt mode(Non-blocking) - * @param[in] obj: The address of log uart object. - * @param[out] prxbuf: The buffer to store received data. - * @param[in] len: The maximum length of data to be read - * @param[in] timeout_ms: The timeout for reading data in ms - * @param[in] force_cs: User callback function - * @return the length in Byte of received data before timeout, or error (< 0) - */ -int32_t log_uart_recv_stream_timeout(log_uart_t *obj, char *prxbuf, uint32_t len, - uint32_t timeout_ms, void *force_cs); - -/** - * @brief Abort interrupt mode of sending data - * @param[in] obj: The address of log uart object. - * @return the length of data sent to log uart. - */ -int32_t log_uart_send_stream_abort(log_uart_t *obj); - -/** - * @brief Abort interrupt mode of receiving data - * @param[in] obj: The address of log uart object. - * @return the length of data received from log uart. - */ -int32_t log_uart_recv_stream_abort(log_uart_t *obj); - -/** - * @brief Disable log uart - * @param[in] obj: The address of log uart object. - * @return None. - */ -void log_uart_disable(log_uart_t *obj); - -/** - * @brief Enable log uart - * @param[in] obj: The address of log uart object. - * @return None. - */ -void log_uart_enable(log_uart_t *obj); - -/** - * @brief Read Line-Status register - * @return value: - * - Bit 0: RX Data Ready - * - Bit 1: Overrun Error - * - Bit 2: Parity Error - * - Bit 3: Framing Error - * - Bit 4: Break Interrupt (received data input is held in 0 state for a longer than a full word tx time) - * - Bit 5: TX FIFO empty (THR empty) - * - Bit 6: TX FIFO empty (THR & TSR both empty) - * - Bit 7: Receiver FIFO Error (parity error, framing error or break indication) - */ -uint8_t log_uart_raed_lsr(log_uart_t *obj); - -/** - * @brief Read Modem-Status register - * @return value: - * - Bit 0: DCTS, The CTS line has changed its state - * - Bit 1: DDSR, The DSR line has changed its state - * - Bit 2: TERI, RI line has changed its state from low to high state - * - Bit 3: DDCD, DCD line has changed its state - * - Bit 4: Complement of the CTS input - * - Bit 5: Complement of the DSR input - * - Bit 6: Complement of the RI input - * - Bit 7: Complement of the DCD input - */ -uint8_t log_uart_raed_msr(log_uart_t *obj); - -///@} -/*\@}*/ - -#ifdef __cplusplus -} -#endif - -#endif //CONFIG_PLATFORM_8195A -#endif // end of "#ifndef LOG_UART_API_H" - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/objects.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/objects.h deleted file mode 100644 index 985f6e1a655..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/objects.h +++ /dev/null @@ -1,214 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef CONFIG_GPIO_EN -struct gpio_irq_s { - PinName pin; - uint32_t event; - HAL_GPIO_PIN hal_pin; - uint8_t hal_port_num; - uint8_t hal_pin_num; -}; - -typedef struct gpio_irq_s gpio_irq_t; - -struct gpio_s { - PinName pin; - PinMode mode; - PinDirection direction; - HAL_GPIO_PIN hal_pin; - uint8_t hal_port_num; - uint8_t hal_pin_num; -}; - -typedef struct gpio_s gpio_t; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - uint8_t *pin_def; -}; -#endif // end of "#ifdef CONFIG_GPIO_EN" - -#ifdef CONFIG_UART_EN -struct serial_s { - int index; - HAL_RUART_OP hal_uart_op; - HAL_RUART_ADAPTER hal_uart_adp; -#ifdef CONFIG_GDMA_EN - UART_DMA_CONFIG uart_gdma_cfg; - HAL_GDMA_ADAPTER uart_gdma_adp_tx; - HAL_GDMA_ADAPTER uart_gdma_adp_rx; - UART_DMA_MULTIBLK gdma_multiblk_list_tx; - UART_DMA_MULTIBLK gdma_multiblk_list_rx; -#endif - uint32_t tx_len; - uint32_t rx_len; -}; -#endif // end of "#ifdef CONFIG_UART_EN" - -struct log_uart_s { - HAL_LOG_UART_ADAPTER log_hal_uart; -}; - -#ifdef CONFIG_SPI_COM_EN - -#endif - -#ifdef CONFIG_PWM_EN -struct pwmout_s { - uint8_t pwm_idx; - uint8_t pin_sel; - uint32_t period; - uint32_t pulse; - HAL_PWM_ADAPTER pwm_hal_adp; -}; -#endif - -#ifdef CONFIG_I2C_EN -struct i2c_s { - SAL_I2C_MNGT_ADPT SalI2CMngtAdpt; - SAL_I2C_HND_PRIV SalI2CHndPriv; - HAL_I2C_INIT_DAT HalI2CInitData; - HAL_I2C_OP HalI2COp; - IRQ_HANDLE I2CIrqHandleDat; - HAL_GDMA_ADAPTER HalI2CTxGdmaAdpt; - HAL_GDMA_ADAPTER HalI2CRxGdmaAdpt; - HAL_GDMA_OP HalI2CGdmaOp; - IRQ_HANDLE I2CTxGdmaIrqHandleDat; - IRQ_HANDLE I2CRxGdmaIrqHandleDat; - SAL_I2C_USER_CB SalI2CUserCB; - SAL_I2C_USERCB_ADPT SalI2CUserCBAdpt[SAL_USER_CB_NUM]; - SAL_I2C_DMA_USER_DEF SalI2CDmaUserDef; -}; -#endif - - -struct flash_s -{ - SPIC_INIT_PARA SpicInitPara; - u32 Length; -}; - - -#ifdef CONFIG_ADC_EN -struct analogin_s { - SAL_ADC_MNGT_ADPT SalADCMngtAdpt; - SAL_ADC_HND_PRIV SalADCHndPriv; - HAL_ADC_INIT_DAT HalADCInitData; - HAL_ADC_OP HalADCOp; - IRQ_HANDLE ADCIrqHandleDat; - HAL_GDMA_ADAPTER HalADCGdmaAdpt; - HAL_GDMA_OP HalADCGdmaOp; - IRQ_HANDLE ADCGdmaIrqHandleDat; - SAL_ADC_USER_CB SalADCUserCB; - SAL_ADC_USERCB_ADPT SalADCUserCBAdpt[SAL_ADC_USER_CB_NUM]; -}; -#endif - -#if 0 -struct i2c_s { - I2C_Type *i2c; -}; - -struct spi_s { - SPI_Type *spi; -}; - -#endif - -#ifdef CONFIG_NFC_EN -struct nfctag_s { - NFC_ADAPTER NFCAdapter; - void *nfc_rd_cb; // read callback function - void *rd_cb_arg; - void *nfc_wr_cb; // write callback function - void *wr_cb_arg; - void *nfc_ev_cb; // event callback function - void *ev_cb_arg; - void *nfc_cache_rd_cb; // cache read callback function - void *cache_read_cb_arg; - unsigned int event_mask; - int pwr_status; -}; -#endif - -#ifdef CONFIG_TIMER_EN -struct gtimer_s { - TIMER_ADAPTER hal_gtimer_adp; - void *handler; - u32 hid; - u8 timer_id; - u8 is_periodcal; -}; -#endif - -#ifdef CONFIG_I2S_EN -struct i2s_s { - HAL_I2S_ADAPTER I2SAdapter; - HAL_I2S_INIT_DAT InitDat; - u8 sampling_rate; - u8 channel_num; - u8 word_length; - u8 direction; -}; - -#endif - -#ifdef CONFIG_DAC_EN -/** \file objects.h - * \brief A Documented file. - * - * A documented file. -*/ - -/** \struct dac_s objects.h "rtl8195a/objects.h" - * \brief This is a dac_s structure. - * - * For analogout APIs, a pointer to dac_s is used as an input paras. - * A DAC initial data structure is the major element of dac_s. - */ -struct dac_s { - HAL_DAC_INIT_DAT DACpara; -}; -#endif - -#ifdef CONFIG_ADC_EN //True random number generator uses ADC - -struct trng_s{ - uint32_t pin; - struct analogin_s tradcng; - uint8_t inited; -}; -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/ota_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/ota_api.c deleted file mode 100644 index 0d1a2c9459c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/ota_api.c +++ /dev/null @@ -1,176 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2017 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "mbed_wait_api.h" - -#include "rtl8195a.h" -#include "ota_api.h" -#include "flash_ext.h" - -static flash_t flash_obj; - -void OTA_ReadHeader(uint32_t addr, imginfo_t *img) -{ - uint32_t epoch_hi, epoch_lo; - - if (addr != OTA_REGION1_HEADER || addr != OTA_REGION2_HEADER) { - return; - } - - flash_ext_read_word(&flash_obj, addr + OTA_TAG_OFS, &img->tag); - flash_ext_read_word(&flash_obj, addr + OTA_VER_OFS, &img->ver); - flash_ext_read_word(&flash_obj, addr + OTA_EPOCH_OFS, &epoch_hi); - flash_ext_read_word(&flash_obj, addr + OTA_EPOCH_OFS + 4, &epoch_lo); - img->timestamp = ((uint64_t)epoch_hi << 32) | (uint64_t) epoch_lo; - - flash_ext_read_word(&flash_obj, addr + OTA_SIZE_OFS, &img->size); - flash_ext_stream_read(&flash_obj, addr + OTA_HASH_OFS, 32, img->hash); - flash_ext_stream_read(&flash_obj, addr + OTA_CAMPAIGN_OFS, 16, img->campaign); - flash_ext_read_word(&flash_obj, addr + OTA_CRC32_OFS, &img->crc32); -} - -bool OTA_CheckHeader(imginfo_t *img) -{ - uint8_t *msg; - uint32_t crc; - - msg = (uint8_t *)img; - crc = crc32_get(msg, OTA_CRC32_LEN); - if (crc != img->crc32) { - return false; - } - - if ((img->tag & OTA_TAG_CHIP_MSK) != (OTA_TAG_ID & OTA_TAG_CHIP_MSK)) { - return false; - } - - return true; -} - -void OTA_GetImageInfo(uint32_t header, imginfo_t *img) -{ - OTA_ReadHeader(header, img); - - if (!OTA_CheckHeader(img)) { - img->timestamp = 0; - img->valid = false; - } - - img->valid = true; -} - -uint32_t OTA_GetUpdateBase(void) -{ - imginfo_t img1, img2; - - OTA_GetImageInfo(OTA_REGION1_HEADER, &img1); - OTA_GetImageInfo(OTA_REGION2_HEADER, &img2); - - if (img1.valid && img2.valid) { - if (img1.timestamp < img2.timestamp) { - return OTA_REGION1_BASE; - } else { - return OTA_REGION2_BASE; - } - } - - if (img1.valid) { - return OTA_REGION2_BASE; - } - - return OTA_REGION1_BASE; -} - -uint32_t OTA_UpateHeader(uint32_t base, imginfo_t *img) -{ - flash_ext_write_word(&flash_obj, base + OTA_TAG_OFS, img->tag); - flash_ext_write_word(&flash_obj, base + OTA_VER_OFS, img->ver); - flash_ext_write_word(&flash_obj, base + OTA_EPOCH_OFS, img->timestamp >> 32); - flash_ext_write_word(&flash_obj, base + OTA_EPOCH_OFS + 4, (img->timestamp << 32) >> 32); - - flash_ext_write_word(&flash_obj, base + OTA_SIZE_OFS, img->size); - flash_ext_stream_write(&flash_obj, base + OTA_HASH_OFS, 32, img->hash); - flash_ext_stream_write(&flash_obj, base + OTA_CAMPAIGN_OFS, 16, img->campaign); - flash_ext_write_word(&flash_obj, base + OTA_CRC32_OFS, img->crc32); - - return 0; -} - -uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data) -{ - uint32_t addr, start, end, count, shift; - uint8_t *pdata = data; - uint8_t buf[FLASH_SECTOR_SIZE]; - - start = base + offset; - end = start + len; - - if (data == NULL || - base != OTA_REGION1_BASE || base != OTA_REGION2_BASE || - start > FLASH_TOP || end > FLASH_TOP) { - return 0; - } - - addr = start & FLASH_SECTOR_MASK; - if (addr != start) { - shift = start - addr; - count = MIN(FLASH_SECTOR_SIZE - shift, len); - flash_ext_stream_read(&flash_obj, addr, shift, buf); - memcpy((void *)(buf + shift), (void *)pdata, count); - - flash_ext_erase_sector(&flash_obj, addr); - flash_ext_stream_write(&flash_obj, addr, FLASH_SECTOR_SIZE, buf); - addr += FLASH_SECTOR_SIZE; - pdata += count; - } - - while (addr < end) { - count = MIN(FLASH_SECTOR_SIZE, end - addr); - flash_ext_erase_sector(&flash_obj, addr); - flash_ext_stream_write(&flash_obj, addr, count, pdata); - addr += FLASH_SECTOR_SIZE; - pdata += count; - } - return len; -} - -uint32_t OTA_ReadImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data) -{ - uint32_t start, end; - - start = base + offset; - end = start + len; - - if (data == NULL || - base != OTA_REGION1_BASE || base != OTA_REGION2_BASE || - start > FLASH_TOP || end > FLASH_TOP) { - return 0; - } - - return flash_ext_stream_read(&flash_obj, start, len, data); -} - -void OTA_ResetTarget(void) -{ - __RTK_CTRL_WRITE32(0x14, 0x00000021); - wait_ms(1000); - - NVIC_SystemReset(); - - // not reached - while (1); -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/ota_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/ota_api.h deleted file mode 100644 index 81d89ad6d65..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/ota_api.h +++ /dev/null @@ -1,83 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2017 Realtek Semiconductor Corp. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OTA_API_H -#define MBED_OTA_API_H - -#define FLASH_TOP 0x200000 -#define FLASH_SECTOR_SIZE 0x1000 -#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1) - -#define OTA_REGION1_HEADER 0x0b000 -#define OTA_REGION2_HEADER 0x0c000 -#define OTA_REGION1_BASE 0x40000 -#define OTA_REGION2_BASE 0x120000 -#define OTA_REGION1_SIZE 0xe0000 -#define OTA_REGION2_SIZE 0xe0000 -#define OTA_REGION_SIZE 0xe0000 -#define OTA_MBED_FS_BASE 0x10000 -#define OTA_MBED_FS_SIZE 0x30000 - -#define OTA_CRC32_LEN 0x44 -#define OTA_HEADER_LEN 0x48 - -#define OTA_TAG_OFS 0x0 -#define OTA_VER_OFS 0x4 -#define OTA_EPOCH_OFS 0x8 -#define OTA_SIZE_OFS 0x10 -#define OTA_HASH_OFS 0x14 -#define OTA_CAMPAIGN_OFS 0x34 -#define OTA_CRC32_OFS 0x44 -#define OTA_IMAGE_OFS 0x48 - -#define OTA_TAG_ID 0x81950001 -#define OTA_VER_ID 0x81950001 - -#define OTA_TAG_CHIP_MSK 0xFFFF0000 -#define OTA_TAG_INFO_MSK 0x0000FFFF - -typedef struct imginfo_s { - uint32_t tag; - uint32_t ver; - uint64_t timestamp; - uint32_t size; - uint8_t hash[32]; - uint8_t campaign[16]; - uint32_t crc32; - bool valid; - uint32_t header_addr; - uint32_t image_addr; -} imginfo_t; - -#ifdef __cplusplus -extern "C" { -#endif - -extern void OTA_GetImageInfo(uint32_t base, imginfo_t *info); -extern uint32_t OTA_GetUpdateRegion(void); - -extern uint32_t OTA_UpdateHeader(uint32_t base, imginfo_t *img); -extern uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data); -extern void OTA_ReadHeader(uint32_t base, imginfo_t *img); -extern uint32_t OTA_ReadImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data); -extern void OTA_ResetTarget(void); - -#ifdef __cplusplus -} -#endif - -#endif /* MBED_OTA_API_H */ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/port_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/port_api.c deleted file mode 100644 index 0cd3b703fcc..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/port_api.c +++ /dev/null @@ -1,219 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "objects.h" -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "PinNames.h" - -#if CONFIG_GPIO_EN - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -#define GPIO_PORT_NUM 3 -#define GPIO_PORT_WIDTH 32 -#define GPIO_PORT_WIDTH_MAX 32 - -const u8 Default_Port_PinDef[GPIO_PORT_NUM][GPIO_PORT_WIDTH+1] = { - // Port 0 has these pin: - {PA_0, PA_1, PB_3, PB_4, - PB_6, PB_7, PC_1, PC_3, - PC_4, PC_5, PC_6, PC_7, - PC_8, PC_9, PD_1, PD_3, - PD_4, PD_5, PD_6, PD_7, - PD_9, PE_1, PE_2, PE_3, - PE_5, PE_6, PE_7, PE_8, - PG_3, PH_1, PH_3, PH_5, - 0xFF}, - - // Port 1 - {PA_2, PA_3, PA_4, PA_5, - PA_6, PA_7, PB_0, PB_1, - PB_2, PB_5, PC_0, PC_2, - PD_0, PD_2, PD_8, PE_0, - PE_4, PE_9, PE_A, PF_0, - PF_1, PF_2, PF_3, PF_4, - PF_5, PG_0, PG_1, PG_2, - PG_4, PG_5, PG_6, PG_7, - 0xFF}, - - // Port 2 - {PH_0, PH_2, PH_4, PH_6, - PH_7, PI_0, PI_1, PI_2, - PI_3, PI_4, PI_5, PI_6, - PI_7, PJ_0, PJ_1, PJ_2, - PJ_3, PJ_4, PJ_5, PJ_6, - PK_0, PK_1, PK_2, PK_3, - PK_4, PK_5, PK_6, - 0xFF} - -}; - -extern const u8 GPIO_SWPORT_DR_TBL[]; -extern const u8 GPIO_EXT_PORT_TBL[]; - -extern VOID HAL_GPIO_Init(HAL_GPIO_PIN *GPIO_Pin); -extern u32 HAL_GPIO_GetPinName(u32 chip_pin); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - u32 i; - - if (port >= GPIO_PORT_NUM) { - DBG_GPIO_ERR("port_init: Invalid port num(%d), max port num is %d\r\n", \ - port, (GPIO_PORT_NUM-1)); - } - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - - if (obj->pin_def == NULL) { - DBG_GPIO_ERR("Port Define Table isn't assigned\n"); - obj->pin_def = (uint8_t*)&Default_Port_PinDef[port][0]; - } - - i=0; - while (obj->pin_def[i] != 0xff) { - i++; - if (i == GPIO_PORT_WIDTH_MAX) { - break; - } - } - - obj->mask &= ((1<direction = dir; - for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins - if (obj->pin_def[i] == 0xff) { - // end of table - break; - } - if (obj->mask & (1 << i)) { // If the pin is used - - GPIO_Pin.pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name - - if (dir == PIN_OUTPUT) { - GPIO_Pin.pin_mode = DOUT_PUSH_PULL; - } else { // PIN_INPUT - GPIO_Pin.pin_mode = DIN_PULL_NONE; - } - HAL_GPIO_Init(&GPIO_Pin); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - - for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins - if (obj->pin_def[i] == 0xff) { - // end of table - break; - } - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode((PinName)obj->pin_def[i], mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - uint32_t i; - uint32_t pin_name; - uint8_t port_num; - uint8_t pin_num; - uint32_t hal_port[3]; - uint8_t port_changed[3]; - - for (i=0;i<3;i++) { - hal_port[i] = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[i]); - port_changed[i] = 0; - } - - for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins - if (obj->pin_def[i] == 0xff) { - // end of table - break; - } - if (obj->mask & (1 << i)) { // If the pin is used - pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name - port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name); - pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name); - hal_port[port_num] &= ~(1 << pin_num); - hal_port[port_num] |= (((value>>i) & 0x01)<< pin_num); - port_changed[port_num] = 1; - } - } - - for (i=0;i<3;i++) { - if (port_changed[i]) { - HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[i], hal_port[i]); - } - } - -} - -int port_read(port_t *obj) -{ - int value=0; - u32 i; - uint32_t pin_name; - uint8_t port_num; - uint8_t pin_num; - uint32_t hal_port[3]; - - for (i=0;i<3;i++) { - hal_port[i] = HAL_READ32(GPIO_REG_BASE, GPIO_EXT_PORT_TBL[i]); - } - - for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins - if (obj->pin_def[i] == 0xff) { - // end of table - break; - } - if (obj->mask & (1 << i)) { // If the pin is used - pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name - port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name); - pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name); - if (hal_port[port_num] & (1<pwm_idx = pwm_idx; - obj->pin_sel = pin_sel; - obj->period = 0; - obj->pulse = 0; - _memset((void *)&obj->pwm_hal_adp, 0, sizeof(HAL_PWM_ADAPTER)); - if (HAL_OK != HAL_Pwm_Init(&obj->pwm_hal_adp, pwm_idx, pin_sel)) { - DBG_PWM_ERR("pwmout_init Err!\n"); - return; - } - pwmout_period_us(obj, 20000); // 20 ms per default - HAL_Pwm_Enable(&obj->pwm_hal_adp); -} - -void pwmout_free(pwmout_t* obj) -{ - HAL_Pwm_Disable(&obj->pwm_hal_adp); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { - value = 1.0; - } - - obj->pulse = (uint32_t)((float)obj->period * value); - HAL_Pwm_SetDuty(&obj->pwm_hal_adp, obj->period, obj->pulse); -} - -float pwmout_read(pwmout_t* obj) -{ - float value = 0; - if (obj->period > 0) { - value = (float)(obj->pulse) / (float)(obj->period); - } - return ((value > (float)1.0) ? (float)(1.0) : (value)); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, (int)(ms * 1000)); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - float dc = pwmout_read(obj); - - obj->period = us; - // Set duty cycle again - pwmout_write(obj, dc); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float value = (float)us / (float)obj->period; - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} - -#endif // #ifdef CONFIG_PWM_EN -#endif // #if DEVICE_PWMOUT diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/rtc_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/rtc_api.c deleted file mode 100644 index f2d44075d55..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/rtc_api.c +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "rtc_api.h" - -#if DEVICE_RTC -#include -#include "timer_api.h" // software-RTC: use a g-timer for the tick of the RTC -#include "mbed_mktime.h" - -#define SW_RTC_TIMER_ID TIMER4 - -static gtimer_t sw_rtc; -static int sw_rtc_en=0; -static time_t rtc_time; - -void sw_rtc_tick_handler(uint32_t id) -{ - rtc_time++; -} - -void rtc_init(void) -{ - // Initial a periodical timer - gtimer_init(&sw_rtc, SW_RTC_TIMER_ID); - // Tick every 1 sec - gtimer_start_periodical(&sw_rtc, 1000000, (void*)sw_rtc_tick_handler, (uint32_t)&sw_rtc); - sw_rtc_en = 1; -} - -void rtc_free(void) -{ - sw_rtc_en = 0; - gtimer_stop(&sw_rtc); - gtimer_deinit(&sw_rtc); -} - -int rtc_isenabled(void) -{ - return(sw_rtc_en); -} - -time_t rtc_read(void) -{ - return rtc_time; -} - -void rtc_write(time_t t) -{ - gtimer_stop(&sw_rtc); - - // Set the RTC - rtc_time = t; - - gtimer_start(&sw_rtc); -} - -#endif // endof "#if DEVICE_RTC" diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/serial_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/serial_api.c deleted file mode 100644 index c972e5d047b..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/serial_api.c +++ /dev/null @@ -1,541 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "rtl8195a.h" -#include "objects.h" -#include "serial_api.h" - -#ifdef CONFIG_MBED_ENABLED -#include "platform_stdlib.h" -#endif - -#if CONFIG_UART_EN - -#include "pinmap.h" -#include - -#ifdef CONFIG_MBED_ENABLED -#include "PeripheralPins.h" -#endif - -#define UART_NUM (3) -#define SERIAL_TX_IRQ_EN 0x01 -#define SERIAL_RX_IRQ_EN 0x02 -#define SERIAL_TX_DMA_EN 0x01 -#define SERIAL_RX_DMA_EN 0x02 - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; - -static uart_irq_handler irq_handler[UART_NUM]; -static uint32_t serial_irq_en[UART_NUM]={0, 0, 0}; - -#ifdef CONFIG_GDMA_EN -static uint32_t serial_dma_en[UART_NUM] = {0, 0, 0}; -static HAL_GDMA_OP UartGdmaOp; -#endif - -#ifdef CONFIG_MBED_ENABLED -#include "log_uart_api.h" - -#include "hal_log_uart.h" - -int stdio_uart_inited = 0; -serial_t stdio_uart; -log_uart_t stdio_uart_log; - -static uint32_t serial_log_irq_ids; -static uart_irq_handler log_irq_handler; -static uint32_t serial_log_irq_en; - -#endif - -static void SerialTxDoneCallBack(VOID *pAdapter); -static void SerialRxDoneCallBack(VOID *pAdapter); - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - uint32_t uart_tx, uart_rx; - uint32_t uart_sel; - uint8_t uart_idx; - PHAL_RUART_OP pHalRuartOp; - PHAL_RUART_ADAPTER pHalRuartAdapter; -#ifdef CONFIG_GDMA_EN - PUART_DMA_CONFIG pHalRuartDmaCfg; - PHAL_GDMA_OP pHalGdmaOp=&UartGdmaOp; -#endif - - // Determine the UART to use (UART0, UART1, or UART3) - uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); - uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - - uart_sel = pinmap_merge(uart_tx, uart_rx); - uart_idx = RTL_GET_PERI_IDX(uart_sel); - if (unlikely(uart_idx == (uint8_t)NC)) { - DBG_UART_ERR("%s: Cannot find matched UART\n", __FUNCTION__); - return; - } -#ifdef CONFIG_MBED_ENABLED - else if (uart_idx == UART_3) { - obj->index = UART_3; - goto init_stdio; - } -#endif - - pHalRuartOp = &(obj->hal_uart_op); - pHalRuartAdapter = &(obj->hal_uart_adp); - - if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter)) { - DBG_UART_ERR("%s: Allocate Adapter Failed\n", __FUNCTION__); - return; - } - - HalRuartOpInit((VOID*)pHalRuartOp); - -#ifdef CONFIG_GDMA_EN - HalGdmaOpInit((VOID*)pHalGdmaOp); - pHalRuartDmaCfg = &obj->uart_gdma_cfg; - pHalRuartDmaCfg->pHalGdmaOp = pHalGdmaOp; - pHalRuartDmaCfg->pTxHalGdmaAdapter = &obj->uart_gdma_adp_tx; - pHalRuartDmaCfg->pRxHalGdmaAdapter = &obj->uart_gdma_adp_rx; - pHalRuartDmaCfg->pTxDmaBlkList = &obj->gdma_multiblk_list_tx; - pHalRuartDmaCfg->pRxDmaBlkList = &obj->gdma_multiblk_list_rx; - _memset((void*)(pHalRuartDmaCfg->pTxHalGdmaAdapter), 0, sizeof(HAL_GDMA_ADAPTER)); - _memset((void*)(pHalRuartDmaCfg->pRxHalGdmaAdapter), 0, sizeof(HAL_GDMA_ADAPTER)); - _memset((void*)(pHalRuartDmaCfg->pTxDmaBlkList), 0, sizeof(UART_DMA_MULTIBLK)); - _memset((void*)(pHalRuartDmaCfg->pRxDmaBlkList), 0, sizeof(UART_DMA_MULTIBLK)); -#endif - - pHalRuartOp->HalRuartAdapterLoadDef(pHalRuartAdapter, uart_idx); - pHalRuartAdapter->PinmuxSelect = RTL_GET_PERI_SEL(uart_sel); - pHalRuartAdapter->BaudRate = 9600; - pHalRuartAdapter->IrqHandle.Priority = 6; - - if (HalRuartInit(pHalRuartAdapter) != HAL_OK) { - DBG_UART_ERR("serial_init Err!\n"); - return; - } - pHalRuartOp->HalRuartRegIrq(pHalRuartAdapter); - pHalRuartOp->HalRuartIntEnable(pHalRuartAdapter); - -#ifdef CONFIG_MBED_ENABLED -init_stdio: - // For stdio management - if (uart_idx == STDIO_UART) { - // default setting to 38400 - if (stdio_uart_inited) return; - log_uart_init(&stdio_uart_log, 38400, 8, ParityNone, 1); - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -#endif -} - -void serial_free(serial_t *obj) -{ - PHAL_RUART_ADAPTER pHalRuartAdapter; -#ifdef CONFIG_GDMA_EN - u8 uart_idx; - PUART_DMA_CONFIG pHalRuartDmaCfg; -#endif -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - log_uart_free(&stdio_uart_log); - return; - } -#endif - pHalRuartAdapter = &(obj->hal_uart_adp); - - HalRuartDeInit(pHalRuartAdapter); - -#ifdef CONFIG_GDMA_EN - uart_idx = pHalRuartAdapter->UartIndex; - pHalRuartDmaCfg = &obj->uart_gdma_cfg; - if (serial_dma_en[uart_idx] & SERIAL_RX_DMA_EN) { - HalRuartRxGdmaDeInit(pHalRuartDmaCfg); - serial_dma_en[uart_idx] &= ~SERIAL_RX_DMA_EN; - } - - if (serial_dma_en[uart_idx] & SERIAL_TX_DMA_EN) { - HalRuartTxGdmaDeInit(pHalRuartDmaCfg); - serial_dma_en[uart_idx] &= ~SERIAL_TX_DMA_EN; - } -#endif -} - -void serial_baud(serial_t *obj, int baudrate) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - return; - } -#endif - PHAL_RUART_ADAPTER pHalRuartAdapter; - - pHalRuartAdapter = &(obj->hal_uart_adp); - - pHalRuartAdapter->BaudRate = baudrate; - HalRuartSetBaudRate((VOID*)pHalRuartAdapter); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - log_uart_format(&stdio_uart_log, data_bits, parity, stop_bits); - return; - } -#endif - PHAL_RUART_ADAPTER pHalRuartAdapter; - pHalRuartAdapter = &(obj->hal_uart_adp); - - if (data_bits == 8) { - pHalRuartAdapter->WordLen = RUART_WLS_8BITS; - } else { - pHalRuartAdapter->WordLen = RUART_WLS_7BITS; - } - - - switch (parity) { - case ParityOdd: - case ParityForced0: - pHalRuartAdapter->Parity = RUART_PARITY_ENABLE; - pHalRuartAdapter->ParityType = RUART_ODD_PARITY; - break; - case ParityEven: - case ParityForced1: - pHalRuartAdapter->Parity = RUART_PARITY_ENABLE; - pHalRuartAdapter->ParityType = RUART_EVEN_PARITY; - break; - default: // ParityNone - pHalRuartAdapter->Parity = RUART_PARITY_DISABLE; - break; - } - - if (stop_bits == 2) { - pHalRuartAdapter->StopBit = RUART_STOP_BIT_2; - } else { - pHalRuartAdapter->StopBit = RUART_STOP_BIT_1; - } - - HalRuartInit(pHalRuartAdapter); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static void SerialTxDoneCallBack(VOID *pAdapter) -{ - PHAL_RUART_ADAPTER pHalRuartAdapter = pAdapter; - u8 uart_idx = pHalRuartAdapter->UartIndex; - - // Mask UART TX FIFO empty - pHalRuartAdapter->Interrupts &= ~RUART_IER_ETBEI; - HalRuartSetIMRRtl8195a (pHalRuartAdapter); - - if (irq_handler[uart_idx] != NULL) { - irq_handler[uart_idx](serial_irq_ids[uart_idx], TxIrq); - } -} - -static void SerialRxDoneCallBack(VOID *pAdapter) -{ - PHAL_RUART_ADAPTER pHalRuartAdapter = pAdapter; - u8 uart_idx = pHalRuartAdapter->UartIndex; - - if (irq_handler[uart_idx] != NULL) { - irq_handler[uart_idx](serial_irq_ids[uart_idx], RxIrq); - } -} - - -#ifdef CONFIG_MBED_ENABLED -static void serial_loguart_irq_handler(uint32_t id, LOG_UART_INT_ID event) -{ - log_uart_irq_set(&stdio_uart_log, event, 0); - if (log_irq_handler) { - if (event == IIR_RX_RDY || event == IIR_CHAR_TIMEOUT) { - log_irq_handler(serial_log_irq_ids, RxIrq); - } else if (event == IIR_THR_EMPTY) { - log_irq_handler(serial_log_irq_ids, TxIrq); - } - } - return; -} -#endif - - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - log_irq_handler = handler; - serial_log_irq_ids = id; - log_uart_irq_handler(&stdio_uart_log, serial_loguart_irq_handler, id); - return; - } -#endif - PHAL_RUART_ADAPTER pHalRuartAdapter; - u8 uart_idx; - pHalRuartAdapter = &(obj->hal_uart_adp); - uart_idx = pHalRuartAdapter->UartIndex; - irq_handler[uart_idx] = handler; - serial_irq_ids[uart_idx] = id; - pHalRuartAdapter->TxTDCallback = SerialTxDoneCallBack; - pHalRuartAdapter->TxTDCbPara = (void*)pHalRuartAdapter; - pHalRuartAdapter->RxDRCallback = SerialRxDoneCallBack; - pHalRuartAdapter->RxDRCbPara = (void*)pHalRuartAdapter; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - if(enable) { - if (irq == RxIrq) { - log_uart_irq_set(&stdio_uart_log, IIR_RX_RDY, enable); - serial_log_irq_en |= SERIAL_RX_IRQ_EN; - } else { - log_uart_irq_set(&stdio_uart_log, IIR_THR_EMPTY, enable); - serial_log_irq_en |= SERIAL_TX_IRQ_EN; - } - } else { - if (irq == RxIrq) { - log_uart_irq_set(&stdio_uart_log, IIR_RX_RDY, enable); - serial_log_irq_en &= ~SERIAL_RX_IRQ_EN; - } else { - log_uart_irq_set(&stdio_uart_log, IIR_THR_EMPTY, enable); - serial_log_irq_en &= ~SERIAL_TX_IRQ_EN; - } - - log_uart_t *log_obj = &stdio_uart_log; - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(log_obj->log_hal_uart); - if (pUartAdapter->IntEnReg == 0) { - InterruptUnRegister(&pUartAdapter->IrqHandle); - InterruptDis(&pUartAdapter->IrqHandle); - } - } - return; - } -#endif - PHAL_RUART_ADAPTER pHalRuartAdapter; - PHAL_RUART_OP pHalRuartOp; - u8 uart_idx; - pHalRuartAdapter = &(obj->hal_uart_adp); - pHalRuartOp = &(obj->hal_uart_op); - uart_idx = pHalRuartAdapter->UartIndex; - - if (enable) { - if (irq == RxIrq) { - pHalRuartAdapter->Interrupts |= RUART_IER_ERBI | RUART_IER_ELSI; - serial_irq_en[uart_idx] |= SERIAL_RX_IRQ_EN; - HalRuartSetIMRRtl8195a (pHalRuartAdapter); - } else { - serial_irq_en[uart_idx] |= SERIAL_TX_IRQ_EN; - } - - pHalRuartOp->HalRuartRegIrq(pHalRuartAdapter); - pHalRuartOp->HalRuartIntEnable(pHalRuartAdapter); - } else { // disable - if (irq == RxIrq) { - pHalRuartAdapter->Interrupts &= ~(RUART_IER_ERBI | RUART_IER_ELSI); - serial_irq_en[uart_idx] &= ~SERIAL_RX_IRQ_EN; - } else { - pHalRuartAdapter->Interrupts &= ~RUART_IER_ETBEI; - serial_irq_en[uart_idx] &= ~SERIAL_TX_IRQ_EN; - } - HalRuartSetIMRRtl8195a (pHalRuartAdapter); - - if (pHalRuartAdapter->Interrupts == 0) { - InterruptUnRegister(&pHalRuartAdapter->IrqHandle); - InterruptDis(&pHalRuartAdapter->IrqHandle); - } - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - return log_uart_getc(&stdio_uart_log); - } -#endif - PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp); - u8 uart_idx = pHalRuartAdapter->UartIndex; - - while (!serial_readable(obj)); - return (int)((HAL_RUART_READ32(uart_idx, RUART_REV_BUF_REG_OFF)) & 0xFF); -} - -void serial_putc(serial_t *obj, int c) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - log_uart_putc(&stdio_uart_log, (char)c); - - // UnMask LOG_UART TX FIFO empty IRQ - if (serial_log_irq_en & SERIAL_TX_IRQ_EN) { - log_uart_t *log_obj = &stdio_uart_log; - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(log_obj->log_hal_uart); - pUartAdapter->IntEnReg |= IER_ETBEI; - HalLogUartSetIntEn(pUartAdapter); - } - return; - } -#endif - PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp); - u8 uart_idx = pHalRuartAdapter->UartIndex; - - while (!serial_writable(obj)); - HAL_RUART_WRITE32(uart_idx, RUART_TRAN_HOLD_REG_OFF, (c & 0xFF)); - - if (serial_irq_en[uart_idx] & SERIAL_TX_IRQ_EN) { - // UnMask TX FIFO empty IRQ - pHalRuartAdapter->Interrupts |= RUART_IER_ETBEI; - HalRuartSetIMRRtl8195a (pHalRuartAdapter); - } -} - -int serial_readable(serial_t *obj) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - return log_uart_readable(&stdio_uart_log); - } -#endif - - PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp); - u8 uart_idx = pHalRuartAdapter->UartIndex; - - if ((HAL_RUART_READ32(uart_idx, RUART_LINE_STATUS_REG_OFF)) & RUART_LINE_STATUS_REG_DR) { - return 1; - } else { - return 0; - } -} - -int serial_writable(serial_t *obj) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - return log_uart_writable(&stdio_uart_log); - } -#endif - - PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp); - u8 uart_idx = pHalRuartAdapter->UartIndex; - - if (HAL_RUART_READ32(uart_idx, RUART_LINE_STATUS_REG_OFF) & (RUART_LINE_STATUS_REG_THRE)) { - return 1; - } else { - return 0; - } -} - -void serial_clear(serial_t *obj) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - log_uart_clear(&stdio_uart_log); - return; - } -#endif - - PHAL_RUART_ADAPTER pHalRuartAdapter; - - pHalRuartAdapter = &(obj->hal_uart_adp); - HalRuartResetTRxFifo((VOID *)pHalRuartAdapter); -} - -void serial_break_set(serial_t *obj) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - log_uart_break_set(&stdio_uart_log); - return; - } -#endif - - PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp); - u8 uart_idx = pHalRuartAdapter->UartIndex; - u32 RegValue; - RegValue = HAL_RUART_READ32(uart_idx, RUART_LINE_CTL_REG_OFF); - RegValue |= BIT_UART_LCR_BREAK_CTRL; - HAL_RUART_WRITE32(uart_idx, RUART_LINE_CTL_REG_OFF, RegValue); -} - -void serial_break_clear(serial_t *obj) -{ -#ifdef CONFIG_MBED_ENABLED - if (obj->index == UART_3) { - log_uart_break_clear(&stdio_uart_log); - return; - } -#endif - PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp); - u8 uart_idx = pHalRuartAdapter->UartIndex; - u32 RegValue; - RegValue = HAL_RUART_READ32(uart_idx, RUART_LINE_CTL_REG_OFF); - RegValue &= ~(BIT_UART_LCR_BREAK_CTRL); - HAL_RUART_WRITE32(uart_idx, RUART_LINE_CTL_REG_OFF, RegValue); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} - - -#if DEVICE_SERIAL_ASYNCH -#endif -#endif //#if CONFIG_UART_EN - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_api.c deleted file mode 100644 index 57ac3bd26e4..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_api.c +++ /dev/null @@ -1,391 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "objects.h" -#include "spi_api.h" -#include "spi_ex_api.h" -#include "PinNames.h" -#include "pinmap.h" -#include "hal_ssi.h" - -#ifdef CONFIG_MBED_ENABLED -#include "platform_stdlib.h" -#endif - -extern u32 SystemGetCpuClk(VOID); -extern VOID HAL_GPIO_PullCtrl(u32 pin, u32 mode); - -void spi_tx_done_callback(VOID *obj); -void spi_rx_done_callback(VOID *obj); -void spi_bus_tx_done_callback(VOID *obj); - -#ifdef CONFIG_GDMA_EN -HAL_GDMA_OP SpiGdmaOp; -#endif - -uint8_t SPI0_IS_AS_SLAVE = 0; - -//TODO: Load default Setting: It should be loaded from external setting file. -extern const DW_SSI_DEFAULT_SETTING SpiDefaultSetting; - -#ifdef CONFIG_MBED_ENABLED -#include "PeripheralPins.h" -#endif - -void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - SSI_DBG_ENTRANCE("spi_init()\n"); - - int ssi_mosi, ssi_miso, ssi_peri; - uint8_t ssi_idx, ssi_pinmux; - PHAL_SSI_ADAPTOR pHalSsiAdaptor; - PHAL_SSI_OP pHalSsiOp; - - _memset((void*)obj, 0, sizeof(spi_t)); - obj->state = 0; - - uint32_t SystemClock = SystemGetCpuClk(); - uint32_t MaxSsiFreq = (SystemClock >> 2) >> 1; - - /* SsiClockDivider doesn't support odd number */ - DBG_SSI_INFO("SystemClock: %d\n", SystemClock); - DBG_SSI_INFO("MaxSsiFreq : %d\n", MaxSsiFreq); - - ssi_mosi = pinmap_peripheral(mosi, PinMap_SSI_MOSI); - ssi_miso = pinmap_peripheral(miso, PinMap_SSI_MISO); - - ssi_peri = pinmap_merge(ssi_mosi, ssi_miso); - if (unlikely(ssi_peri == NC)) { - DBG_SSI_ERR("spi_init(): Cannot find matched SSI index.\n"); - return; - } - obj->sclk = (u8)sclk; - ssi_idx = RTL_GET_PERI_IDX(ssi_peri); - ssi_pinmux = RTL_GET_PERI_SEL(ssi_peri); - DBG_SSI_INFO("ssi_peri: %d, ssi_idx: %d, ssi_pinmux: %d\n", ssi_peri, ssi_idx, ssi_pinmux); - - pHalSsiAdaptor = &obj->spi_adp; - pHalSsiOp = &obj->spi_op; - - pHalSsiAdaptor->Index = ssi_idx; - pHalSsiAdaptor->PinmuxSelect = ssi_pinmux; - pHalSsiAdaptor->Role = SSI_MASTER; - - HalSsiOpInit((VOID*)pHalSsiOp); - - pHalSsiOp->HalSsiSetDeviceRole(pHalSsiAdaptor, pHalSsiAdaptor->Role); - - /* Pinmux workaround */ - if ((ssi_idx == 0) && (ssi_pinmux == SSI0_MUX_TO_GPIOC)) { - EEPROM_PIN_CTRL(OFF); - } - - if ((ssi_idx == 0) && (ssi_pinmux == SSI0_MUX_TO_GPIOE)) { - DBG_SSI_WARN(ANSI_COLOR_MAGENTA"SPI0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET); - } - - //TODO: Implement default setting structure. - pHalSsiOp->HalSsiLoadSetting(pHalSsiAdaptor, (void*)&SpiDefaultSetting); - pHalSsiAdaptor->DefaultRxThresholdLevel = SpiDefaultSetting.RxThresholdLevel; - - if(HalSsiInit(pHalSsiAdaptor) != HAL_OK){ - DBG_SSI_ERR(ANSI_COLOR_RED"spi_init(): SPI %x init fails.\n"ANSI_COLOR_RESET,pHalSsiAdaptor->Index); - return; - } - - pHalSsiAdaptor->TxCompCallback = spi_tx_done_callback; - pHalSsiAdaptor->TxCompCbPara = (void*)obj; - pHalSsiAdaptor->RxCompCallback = spi_rx_done_callback; - pHalSsiAdaptor->RxCompCbPara = (void*)obj; - pHalSsiAdaptor->TxIdleCallback = spi_bus_tx_done_callback; - pHalSsiAdaptor->TxIdleCbPara = (void*)obj; - -#ifdef CONFIG_GDMA_EN - HalGdmaOpInit((VOID*)&SpiGdmaOp); - pHalSsiAdaptor->DmaConfig.pHalGdmaOp = &SpiGdmaOp; - pHalSsiAdaptor->DmaConfig.pRxHalGdmaAdapter = &obj->spi_gdma_adp_rx; - pHalSsiAdaptor->DmaConfig.pTxHalGdmaAdapter = &obj->spi_gdma_adp_tx; - obj->dma_en = 0; - pHalSsiAdaptor->HaveTxChannel = 0; - pHalSsiAdaptor->HaveRxChannel = 0; -#endif -} - -void spi_free (spi_t *obj) -{ - PHAL_SSI_ADAPTOR pHalSsiAdaptor; - pHalSsiAdaptor = &obj->spi_adp; - HalSsiDeInit(pHalSsiAdaptor); - - SPI0_MULTI_CS_CTRL(OFF); - -#ifdef CONFIG_GDMA_EN - if (obj->dma_en & SPI_DMA_RX_EN) { - HalSsiRxGdmaDeInit(pHalSsiAdaptor); - } - - if (obj->dma_en & SPI_DMA_TX_EN) { - HalSsiTxGdmaDeInit(pHalSsiAdaptor); - } - obj->dma_en = 0; -#endif -} - -void spi_format (spi_t *obj, int bits, int mode, int slave) -{ - PHAL_SSI_ADAPTOR pHalSsiAdaptor; - PHAL_SSI_OP pHalSsiOp; - - pHalSsiAdaptor = &obj->spi_adp; - pHalSsiOp = &obj->spi_op; - - pHalSsiAdaptor->DataFrameSize = (bits - 1); - - /* - * mode | POL PHA - * -----+-------- - * 0 | 0 0 - * 1 | 0 1 - * 2 | 1 0 - * 3 | 1 1 - * - * SCPOL_INACTIVE_IS_LOW = 0, - * SCPOL_INACTIVE_IS_HIGH = 1 - * - * SCPH_TOGGLES_IN_MIDDLE = 0, - * SCPH_TOGGLES_AT_START = 1 - */ - switch (mode) - { - case 0: - pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_LOW; - pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_IN_MIDDLE; - break; - case 1: - pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_LOW; - pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START; - break; - case 2: - pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH; - pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_IN_MIDDLE; - break; - case 3: - pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH; - pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START; - break; - default: // same as 3 - pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH; - pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START; - break; - } - - if (slave == 1) { - if (pHalSsiAdaptor->Index == 0) { - pHalSsiAdaptor->Role = SSI_SLAVE; - pHalSsiAdaptor->SlaveOutputEnable = SLV_TXD_ENABLE; // <-- Slave only - SPI0_IS_AS_SLAVE = 1; - DBG_SSI_INFO("SPI0 is as slave\n"); - } else { - DBG_SSI_ERR("The SPI%d cannot work as Slave mode, only SPI0 does.\r\n", pHalSsiAdaptor->Index); - pHalSsiAdaptor->Role = SSI_MASTER; - } - } else { - pHalSsiAdaptor->Role = SSI_MASTER; - } - pHalSsiOp->HalSsiSetDeviceRole(pHalSsiAdaptor, pHalSsiAdaptor->Role); - -#ifdef CONFIG_GPIO_EN - if (pHalSsiAdaptor->Role == SSI_SLAVE) { - if (pHalSsiAdaptor->SclkPolarity == SCPOL_INACTIVE_IS_LOW) { - HAL_GPIO_PullCtrl((u32)obj->sclk, hal_PullDown); - } else { - HAL_GPIO_PullCtrl((u32)obj->sclk, hal_PullUp); - } - } -#endif - HalSsiSetFormat(pHalSsiAdaptor); -} - -void spi_frequency (spi_t *obj, int hz) -{ - PHAL_SSI_ADAPTOR pHalSsiAdaptor; - - pHalSsiAdaptor = &obj->spi_adp; - HalSsiSetSclk(pHalSsiAdaptor, (u32)hz); -} - -static inline void ssi_write (spi_t *obj, int value) -{ - PHAL_SSI_ADAPTOR pHalSsiAdaptor; - PHAL_SSI_OP pHalSsiOp; - - pHalSsiAdaptor = &obj->spi_adp; - pHalSsiOp = &obj->spi_op; - - while (!pHalSsiOp->HalSsiWriteable(pHalSsiAdaptor)); - pHalSsiOp->HalSsiWrite((VOID*)pHalSsiAdaptor, value); -} - -static inline int ssi_read(spi_t *obj) -{ - PHAL_SSI_ADAPTOR pHalSsiAdaptor; - PHAL_SSI_OP pHalSsiOp; - - pHalSsiAdaptor = &obj->spi_adp; - pHalSsiOp = &obj->spi_op; - - while (!pHalSsiOp->HalSsiReadable(pHalSsiAdaptor)); - return (int)pHalSsiOp->HalSsiRead(pHalSsiAdaptor); -} - -int spi_master_write (spi_t *obj, int value) -{ - ssi_write(obj, value); - return ssi_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - int i; - char out, in; - - for (i = 0; i < total; i++) { - out = (i < tx_length) ? tx_buffer[i] : write_fill; - in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive (spi_t *obj) -{ - PHAL_SSI_ADAPTOR pHalSsiAdaptor; - PHAL_SSI_OP pHalSsiOp; - int Readable; - int Busy; - - pHalSsiAdaptor = &obj->spi_adp; - pHalSsiOp = &obj->spi_op; - - Readable = pHalSsiOp->HalSsiReadable(pHalSsiAdaptor); - Busy = (int)pHalSsiOp->HalSsiBusy(pHalSsiAdaptor); - return ((Readable && !Busy) ? 1 : 0); -} - -int spi_slave_read (spi_t *obj) -{ - return ssi_read(obj); -} - -void spi_slave_write (spi_t *obj, int value) -{ - ssi_write(obj, value); -} - -int spi_busy (spi_t *obj) -{ - PHAL_SSI_ADAPTOR pHalSsiAdaptor; - PHAL_SSI_OP pHalSsiOp; - - pHalSsiAdaptor = &obj->spi_adp; - pHalSsiOp = &obj->spi_op; - - return (int)pHalSsiOp->HalSsiBusy(pHalSsiAdaptor); -} - -// Bus Idle: Real TX done, TX FIFO empty and bus shift all data out already -void spi_bus_tx_done_callback(VOID *obj) -{ - spi_t *spi_obj = (spi_t *)obj; - spi_irq_handler handler; - - if (spi_obj->bus_tx_done_handler) { - handler = (spi_irq_handler)spi_obj->bus_tx_done_handler; - handler(spi_obj->bus_tx_done_irq_id, (SpiIrq)0); - } -} - -void spi_tx_done_callback(VOID *obj) -{ - spi_t *spi_obj = (spi_t *)obj; - spi_irq_handler handler; - - if (spi_obj->state & SPI_STATE_TX_BUSY) { - spi_obj->state &= ~SPI_STATE_TX_BUSY; - if (spi_obj->irq_handler) { - handler = (spi_irq_handler)spi_obj->irq_handler; - handler(spi_obj->irq_id, SpiTxIrq); - } - } -} - -void spi_rx_done_callback(VOID *obj) -{ - spi_t *spi_obj = (spi_t *)obj; - spi_irq_handler handler; - - spi_obj->state &= ~SPI_STATE_RX_BUSY; - if (spi_obj->irq_handler) { - handler = (spi_irq_handler)spi_obj->irq_handler; - handler(spi_obj->irq_id, SpiRxIrq); - } -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SSI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SSI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SSI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SSI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SSI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SSI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SSI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SSI_SSEL; -} - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_ex_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_ex_api.h deleted file mode 100644 index e80a4981ec2..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_ex_api.h +++ /dev/null @@ -1,244 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_SPI_EXT_API_H -#define MBED_SPI_EXT_API_H - -#include "device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup spi_ex SPI_EX - * @ingroup hal - * @brief spi extended functions - * @{ - */ - -///@name Ameba Common -///@{ - -#define SPI_DMA_RX_EN (1<<0) -#define SPI_DMA_TX_EN (1<<1) - -enum { - SPI_SCLK_IDLE_LOW=0, // the SCLK is Low when SPI is inactive - SPI_SCLK_IDLE_HIGH=2 // the SCLK is High when SPI is inactive -}; - -// SPI Master mode: for continuous transfer, how the CS toggle: -enum { - SPI_CS_TOGGLE_EVERY_FRAME=0, // let SCPH=0 then the CS toggle every frame - SPI_CS_TOGGLE_START_STOP=1 // let SCPH=1 the CS toggle at start and stop -}; - -enum { - SPI_SCLK_TOGGLE_MIDDLE=0, // Serial Clk toggle at middle of 1st data bit and latch data at 1st Clk edge - SPI_SCLK_TOGGLE_START=1 // Serial Clk toggle at start of 1st data bit and latch data at 2nd Clk edge -}; - -typedef enum { - CS_0 = 0, - CS_1 = 1, - CS_2 = 2, - CS_3 = 3, - CS_4 = 4, - CS_5 = 5, - CS_6 = 6, - CS_7 = 7 -}ChipSelect; - - -#define SPI_STATE_READY 0x00 -#define SPI_STATE_RX_BUSY (1<<1) -#define SPI_STATE_TX_BUSY (1<<2) - -typedef enum { - SpiRxIrq, - SpiTxIrq -} SpiIrq; - -typedef void (*spi_irq_handler)(uint32_t id, SpiIrq event); - -/** - * @brief Set SPI interrupt handler if needed. - * @param obj: spi object define in application software. - * @param handler: interrupt callback function - * @param id: interrupt callback parameter - * @retval none - */ -void spi_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id); - -/** - * @brief Set SPI interrupt bus tx done handler if needed. - * @param obj: spi object define in application software. - * @param handler: interrupt bus tx done callback function - * @param id: interrupt callback parameter - * @retval none - */ -void spi_bus_tx_done_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id); - -/** - * @brief Slave device to flush tx fifo. - * @param obj: spi slave object define in application software. - * @note : It will discard all data in both tx fifo and rx fifo - */ -void spi_slave_flush_fifo(spi_t * obj); - -/** - * @brief slave recv target length data use interrupt mode. - * @param obj: spi slave object define in application software. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be read. - * @retval : stream init status - */ -int32_t spi_slave_read_stream(spi_t *obj, char *rx_buffer, uint32_t length); - -/** - * @brief slave send target length data use interrupt mode. - * @param obj: spi slave object define in application software. - * @param tx_buffer: buffer to be written to Tx FIFO. - * @param length: number of data bytes to be send. - * @retval : stream init status - */ -int32_t spi_slave_write_stream(spi_t *obj, char *tx_buffer, uint32_t length); - -/** - * @brief master recv target length data use interrupt mode. - * @param obj: spi master object define in application software. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be read. - * @retval : stream init status - */ -int32_t spi_master_read_stream(spi_t *obj, char *rx_buffer, uint32_t length); - -/** - * @brief master send target length data use interrupt mode. - * @param obj: spi master object define in application software. - * @param tx_buffer: buffer to be written to Tx FIFO. - * @param length: number of data bytes to be send. - * @retval : stream init status - */ -int32_t spi_master_write_stream(spi_t *obj, char *tx_buffer, uint32_t length); - -/** - * @brief master send & recv target length data use interrupt mode. - * @param obj: spi master object define in application software. - * @param tx_buffer: buffer to be written to Tx FIFO. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be send & recv. - * @retval : stream init status - */ -int32_t spi_master_write_read_stream(spi_t *obj, char *tx_buffer, char *rx_buffer, uint32_t length); - -/** - * @brief slave recv target length data use interrupt mode and timeout mechanism. - * @param obj: spi slave object define in application software. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be read. - * @param timeout_ms: timeout waiting time. - * @retval : number of bytes read already - */ -int32_t spi_slave_read_stream_timeout(spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms); - -/** - * @brief slave recv target length data use interrupt mode and stop if the spi bus is idle. - * @param obj: spi slave object define in application software. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be read. - * @retval : number of bytes read already - */ -int32_t spi_slave_read_stream_terminate(spi_t *obj, char *rx_buffer, uint32_t length); - -//#ifdef CONFIG_GDMA_EN -/** - * @brief slave recv target length data use DMA mode. - * @param obj: spi slave object define in application software. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be read. - * @retval : stream init status - */ -int32_t spi_slave_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length); - -/** - * @brief slave send target length data use DMA mode. - * @param obj: spi slave object define in application software. - * @param tx_buffer: buffer to be written to Tx FIFO. - * @param length: number of data bytes to be send. - * @retval : stream init status - */ -int32_t spi_slave_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length); - -/** - * @brief master send & recv target length data use DMA mode. - * @param obj: spi master object define in application software. - * @param tx_buffer: buffer to be written to Tx FIFO. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be send & recv. - * @retval : stream init status - */ -int32_t spi_master_write_read_stream_dma(spi_t * obj, char * tx_buffer, char * rx_buffer, uint32_t length); - -/** - * @brief master recv target length data use DMA mode. - * @param obj: spi master object define in application software. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be read. - * @retval : stream init status - * @note : DMA or Interrupt mode can be used to TX dummy data - */ -int32_t spi_master_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length); - -/** - * @brief master send target length data use DMA mode. - * @param obj: spi master object define in application software. - * @param tx_buffer: buffer to be written to Tx FIFO. - * @param length: number of data bytes to be send. - * @retval : stream init status - */ -int32_t spi_master_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length); - -/** - * @brief slave recv target length data use DMA mode and timeout mechanism. - * @param obj: spi slave object define in application software. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be read. - * @param timeout_ms: timeout waiting time. - * @retval : number of bytes read already - */ -int32_t spi_slave_read_stream_dma_timeout(spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms); - -/** - * @brief slave recv target length data use DMA mode and stop if the spi bus is idle. - * @param obj: spi slave object define in application software. - * @param rx_buffer: buffer to save data read from SPI FIFO. - * @param length: number of data bytes to be read. - * @retval : number of bytes read already - */ -int32_t spi_slave_read_stream_dma_terminate(spi_t * obj, char * rx_buffer, uint32_t length); -//#endif - -///@} - -/*\@}*/ - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/timer_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/timer_api.c deleted file mode 100644 index c67a2045fbc..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/timer_api.c +++ /dev/null @@ -1,151 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "objects.h" -#include "timer_api.h" - -#if CONFIG_TIMER_EN - -extern HAL_TIMER_OP HalTimerOp; - -extern HAL_Status HalTimerInitRtl8195a_Patch( - IN VOID *Data -); - -static void gtimer_timeout_handler (uint32_t tid) -{ - gtimer_t *obj = (gtimer_t *)tid; - gtimer_irq_handler handler; - u8 timer_id = obj->hal_gtimer_adp.TimerId; - - if (obj->handler != NULL) { - handler = (gtimer_irq_handler)obj->handler; - handler(obj->hid); - } - - if (!obj->is_periodcal) { - gtimer_stop(obj); - } - - if(timer_id < 2) { - // Timer0 | Timer1: clear ISR here - // Timer 2~7 ISR will be cleared in HAL - HalTimerClearIsr(timer_id); - } -} - -void gtimer_init (gtimer_t *obj, uint32_t tid) -{ - PTIMER_ADAPTER pTimerAdapter = &(obj->hal_gtimer_adp); - - if ((tid == 1) || (tid == 6) || (tid == 7)) { - DBG_TIMER_ERR("gtimer_init: This timer is reserved for HAL driver\r\n", tid); - return; - } - - if (tid > GTIMER_MAX) { - DBG_TIMER_ERR("gtimer_init: Invalid TimerId=%d\r\n", tid); - return; - } - - pTimerAdapter->IrqDis = 0; // Enable Irq @ initial - pTimerAdapter->IrqHandle.IrqFun = (IRQ_FUN) gtimer_timeout_handler; - if(tid == 0) { - pTimerAdapter->IrqHandle.IrqNum = TIMER0_IRQ; - } else if(tid == 1) { - pTimerAdapter->IrqHandle.IrqNum = TIMER1_IRQ; - } else { - pTimerAdapter->IrqHandle.IrqNum = TIMER2_7_IRQ; - } - pTimerAdapter->IrqHandle.Priority = 0; - pTimerAdapter->IrqHandle.Data = (u32)obj; - pTimerAdapter->TimerId = (u8)tid; - pTimerAdapter->TimerIrqPriority = 0; - pTimerAdapter->TimerLoadValueUs = 0xFFFFFFFF; // Just a whatever value - pTimerAdapter->TimerMode = USER_DEFINED; - - HalTimerInit ((VOID*) pTimerAdapter); -} - -void gtimer_deinit (gtimer_t *obj) -{ - PTIMER_ADAPTER pTimerAdapter = &(obj->hal_gtimer_adp); - - HalTimerDeInit((void*)pTimerAdapter); -} - -uint32_t gtimer_read_tick (gtimer_t *obj) -{ - PTIMER_ADAPTER pTimerAdapter = &obj->hal_gtimer_adp; - - return (HalTimerOp.HalTimerReadCount(pTimerAdapter->TimerId)); -} - -uint64_t gtimer_read_us (gtimer_t *obj) -{ - uint64_t time_us; - - time_us = gtimer_read_tick(obj)*1000000/32768; - - return (time_us); -} - -void gtimer_reload (gtimer_t *obj, uint32_t duration_us) -{ - PTIMER_ADAPTER pTimerAdapter = &obj->hal_gtimer_adp; - - HalTimerReLoad(pTimerAdapter->TimerId, duration_us); -} - - -void gtimer_start (gtimer_t *obj) -{ - PTIMER_ADAPTER pTimerAdapter = &obj->hal_gtimer_adp; - u8 TimerId = pTimerAdapter->TimerId; - - HalTimerEnable(TimerId); -} - -void gtimer_start_one_shout (gtimer_t *obj, uint32_t duration_us, void* handler, uint32_t hid) -{ - obj->is_periodcal = _FALSE; - obj->handler = handler; - obj->hid = hid; - gtimer_reload(obj, duration_us); - gtimer_start(obj); -} - -void gtimer_start_periodical (gtimer_t *obj, uint32_t duration_us, void* handler, uint32_t hid) -{ - obj->is_periodcal = _TRUE; - obj->handler = handler; - obj->hid = hid; - if (duration_us > GTIMER_TICK_US) { - // reload will takes extra 1 tick - duration_us -= GTIMER_TICK_US; - } - gtimer_reload(obj, duration_us); - gtimer_start(obj); -} - -void gtimer_stop (gtimer_t *obj) -{ - PTIMER_ADAPTER pTimerAdapter = &obj->hal_gtimer_adp; - HalTimerDisable(pTimerAdapter->TimerId); -} - -#endif // end of "#if CONFIG_TIMER_EN" - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/timer_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/timer_api.h deleted file mode 100644 index 33c61a3761d..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/timer_api.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_EXT_TIMER_API_EXT_H -#define MBED_EXT_TIMER_API_EXT_H - -#include "device.h" - -typedef void (*gtimer_irq_handler)(uint32_t id); - -typedef struct gtimer_s gtimer_t; -enum { - TIMER0 = 2, // GTimer 2, share with PWM_3 - TIMER1 = 3, // GTimer 3, share with PWM_0 - TIMER2 = 4, // GTimer 4, share with PWM_1 - TIMER3 = 5, // GTimer 5, share with PWM_2 - TIMER4 = 0, // GTimer 0, share with software-RTC functions - - GTIMER_MAX = 5 -}; - -void gtimer_init (gtimer_t *obj, uint32_t tid); -void gtimer_deinit (gtimer_t *obj); -uint32_t gtimer_read_tick (gtimer_t *obj); -uint64_t gtimer_read_us (gtimer_t *obj); -void gtimer_reload (gtimer_t *obj, uint32_t duration_us); -void gtimer_start (gtimer_t *obj); -void gtimer_start_one_shout (gtimer_t *obj, uint32_t duration_us, void* handler, uint32_t hid); -void gtimer_start_periodical (gtimer_t *obj, uint32_t duration_us, void* handler, uint32_t hid); -void gtimer_stop (gtimer_t *obj); - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/trng_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/trng_api.c deleted file mode 100644 index 39e82a47ff7..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/trng_api.c +++ /dev/null @@ -1,77 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "trng_api.h" -#include "analogin_api.h" -#include "analogin_ext.h" - -#ifdef CONFIG_MBED_ENABLED -#include "platform_stdlib.h" -#endif - -#if DEVICE_TRNG - - -void trng_init(trng_t *obj) -{ - _memset((void *)obj, 0, sizeof(trng_t)); - analogin_init(&obj->tradcng, (PinName)ADC0); - obj->inited = 1; -} - -void trng_free(trng_t *obj) -{ - if (!obj->inited) { - return; - } - - obj->inited = 0; - analogin_deinit(&obj->tradcng); -} - -static void trng_get_byte(trng_t *obj, unsigned char *byte) -{ - size_t bit; - uint32_t adc[2]; - - PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; - PSAL_ADC_HND pSalADCHND = NULL; - - pSalADCMngtAdpt = &(obj->tradcng.SalADCMngtAdpt); - pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); - - *byte = 0; - for (bit = 0; bit < 8; bit++) { - RtkADCRxManualRotate(pSalADCHND, adc); - *byte |= (adc[0] & 0x01) << bit; - } -} - -int trng_get_bytes(trng_t *obj, uint8_t *buf, size_t len, size_t *output_len) -{ - size_t i; - - if (!obj->inited) { - return -1; - } - - for (i = 0; i < len; i++) { - trng_get_byte(obj, buf + i); - } - - *output_len = len; - return 0; -} -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/us_ticker.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/us_ticker.c deleted file mode 100644 index 81bff2a2faa..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/us_ticker.c +++ /dev/null @@ -1,126 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "objects.h" -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -#define SYS_TIM_ID 1 // the G-Timer ID for System -#define APP_TIM_ID 2 // the G-Timer ID for Application - -/* - * For RTL8195AM, clock source is 32k - * - * us per tick: 30.5 - * tick per ms: 32.7 - * tick per us: 0.032 - * tick per sec: 32768 - * - * Define the following macros to convert between TICK and US. - */ -#define TICK_TO_US(x) (uint64_t)(((x)/2) * 61 + ((x)%2) * TIMER_TICK_US) - -static int us_ticker_inited = 0; -static TIMER_ADAPTER TimerAdapter; - -extern HAL_TIMER_OP HalTimerOp; -extern HAL_TIMER_OP_EXT HalTimerOpExt; - -VOID _us_ticker_irq_handler(void *Data) -{ - us_ticker_irq_handler(); -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) { - return; - } - - us_ticker_inited = 1; - - // Reload and restart sys-timer - HalTimerOp.HalTimerDis(SYS_TIM_ID); - HalTimerOpExt.HalTimerReLoad(SYS_TIM_ID, 0xFFFFFFFFUL); - HalTimerOp.HalTimerEn(SYS_TIM_ID); - - // Initial a app-timer - TimerAdapter.IrqDis = 0; // Enable Irq @ initial - TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) _us_ticker_irq_handler; - TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ; - TimerAdapter.IrqHandle.Priority = 10; - TimerAdapter.IrqHandle.Data = (u32)NULL; - TimerAdapter.TimerId = APP_TIM_ID; - TimerAdapter.TimerIrqPriority = 0; - TimerAdapter.TimerLoadValueUs = 0xFFFFFFFF; - TimerAdapter.TimerMode = USER_DEFINED; - - HalTimerOp.HalTimerInit((void *) &TimerAdapter); -} - -uint32_t us_ticker_read(void) -{ - uint32_t tick_cnt; - - if (!us_ticker_inited) { - us_ticker_init(); - } - - tick_cnt = HalTimerOp.HalTimerReadCount(SYS_TIM_ID); - return (uint32_t)TICK_TO_US(0xFFFFFFFFUL - tick_cnt); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - uint32_t time_cur; - - time_cur = us_ticker_read(); - if (timestamp > time_cur + TIMER_TICK_US) { - TimerAdapter.TimerLoadValueUs = timestamp - time_cur; - } else { - TimerAdapter.TimerLoadValueUs = TIMER_TICK_US; - } - - HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); - HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs); - HalTimerOpExt.HalTimerSync(SYS_TIM_ID); - HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId); -} - -void us_ticker_fire_interrupt(void) -{ - TimerAdapter.TimerLoadValueUs = TIMER_TICK_US; - - HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); - HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs); - HalTimerOpExt.HalTimerSync(SYS_TIM_ID); - HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId); -} - -void us_ticker_disable_interrupt(void) -{ - HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); -} - -void us_ticker_clear_interrupt(void) -{ -} - -void us_ticker_free(void) -{ - HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/default_wifi_interface.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/default_wifi_interface.cpp deleted file mode 100644 index 9ad995a69da..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/default_wifi_interface.cpp +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "RTWInterface.h" - -WiFiInterface *WiFiInterface::get_target_default_instance() -{ - static RTWInterface wifi; - return &wifi; -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp deleted file mode 100644 index c3474191d57..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp +++ /dev/null @@ -1,241 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(CONFIG_MBED_ENABLED) - -#include -#include "mbed_assert.h" -#include "mbed_events.h" - -#include "rtw_emac.h" -#include "EMACMemoryManager.h" - -#include "rtos.h" -#include "lwip/pbuf.h" -#include "netif/etharp.h" - -#include "lwip_intf.h" -#include "wifi_constants.h" -#include "wifi_conf.h" - -#define RTW_EMAC_MTU_SIZE (1500U) - -RTW_EMAC::RTW_EMAC() -{ - set_callback_func((emac_callback)(&RTW_EMAC::wlan_emac_recv), this); -} - -uint32_t RTW_EMAC::get_mtu_size() const -{ - return RTW_EMAC_MTU_SIZE; -} - -uint32_t RTW_EMAC::get_align_preference() const -{ - return true; -} - -void RTW_EMAC::get_ifname(char *name, uint8_t size) const -{ - MBED_ASSERT(name != NULL); - strncpy(name, "r0", size); -} - -uint8_t RTW_EMAC::get_hwaddr_size() const -{ - return ETH_HWADDR_LEN; -} - -bool RTW_EMAC::get_hwaddr(uint8_t *addr) const -{ - char mac[20]; - int val[6]; - int i; - - if (RTW_SUCCESS == wifi_get_mac_address(mac)) { - if (sscanf(mac, "%x:%x:%x:%x:%x:%x", - &val[0], &val[1], &val[2], &val[3], &val[4], &val[5]) != 6) { - printf("Get HW address failed\r\n"); - } - for (i = 0; i < 6; i++) { - addr[i] = (unsigned char) val[i]; - } - } else { - printf("Get HW address failed\r\n"); - } - return true; -} - -void RTW_EMAC::set_hwaddr(const uint8_t *addr) -{ -} - -bool RTW_EMAC::link_out(emac_mem_buf_t *buf) -{ - struct eth_drv_sg *sg_list; - int sg_len = 0; - int tot_len; - emac_mem_buf_t *p; - bool ret = true; - if (!rltk_wlan_running(0)) { - memory_manager->free(buf); - return false; - } - - sg_list = (struct eth_drv_sg *)malloc(sizeof(struct eth_drv_sg)*MAX_ETH_DRV_SG); - if (sg_list == 0) { - memory_manager->free(buf); - return false; - } - - p = buf; - tot_len = memory_manager->get_total_len(p); - for (; p != NULL && sg_len < MAX_ETH_DRV_SG; p = memory_manager->get_next(p)) { - sg_list[sg_len].buf = (unsigned int)(static_cast(memory_manager->get_ptr(p))); - sg_list[sg_len].len = memory_manager->get_len(p); - sg_len++; - } - if (sg_len) { - if (rltk_wlan_send(0, sg_list, sg_len, tot_len) != 0) { - ret = false; - } - } - - memory_manager->free(buf); - free(sg_list); - return ret; -} - -bool RTW_EMAC::power_up() -{ - wifi_on(RTW_MODE_STA); - rtos::ThisThread::sleep_for(1000); - wlan_emac_link_change(true); - return true; -} - -void RTW_EMAC::power_down() -{ - wifi_off(); -} - -void RTW_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) -{ - emac_link_input_cb = input_cb; -} - -void RTW_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) -{ - emac_link_state_cb = state_cb; -} - -void RTW_EMAC::add_multicast_group(const uint8_t *addr) -{ -} - -void RTW_EMAC::remove_multicast_group(const uint8_t *addr) -{ -} - -void RTW_EMAC::set_all_multicast(bool all) -{ -} - -void RTW_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) -{ - memory_manager = &mem_mngr; -} - -void RTW_EMAC::wlan_emac_recv(void *param, struct netif *netif, uint32_t len) -{ - struct eth_drv_sg sg_list[MAX_ETH_DRV_SG] = {0}; - emac_mem_buf_t *buf; - RTW_EMAC *enet = static_cast(param); - emac_mem_buf_t *p; - int sg_len = 0; - if (!rltk_wlan_running(0)) { - return; - } - - if (len > MAX_ETH_MSG || len < 0) { - len = MAX_ETH_MSG; - } - - buf = enet->memory_manager->alloc_heap(len, 0); - if (buf == NULL) { - return; - } - - enet->memory_manager->set_len(buf, len); - p = buf; - for (; p != NULL && sg_len < MAX_ETH_DRV_SG; p = enet->memory_manager->get_next(p)) { - sg_list[sg_len].buf = (unsigned int)(static_cast(enet->memory_manager->get_ptr(p))); - sg_list[sg_len].len = enet->memory_manager->get_len(p); - sg_len++; - } - - rltk_wlan_recv(0, sg_list, sg_len); - if (enet->emac_link_input_cb) { - enet->emac_link_input_cb(buf); - } -} - -void mbed_default_mac_address(char *mac) { - unsigned char RTK_mac_addr[3] = {0x00, 0xE0, 0x4C}; // default Realtek mac address - mac[0] = RTK_mac_addr[0]; - mac[1] = RTK_mac_addr[1]; - mac[2] = RTK_mac_addr[2]; - mac[3] = 0x87; - mac[4] = 0x00; - mac[5] = 0x01; - return; -} - -void mbed_mac_address(char *mac) -{ - char hwaddr[20]; - int val[6]; - int i; - if (RTW_SUCCESS == wifi_get_mac_address(hwaddr)) { - if (sscanf(hwaddr, "%x:%x:%x:%x:%x:%x", - &val[0], &val[1], &val[2], &val[3], &val[4], &val[5]) != 6) { - printf("Get HW address failed\r\n"); - } - for (i = 0; i < 6; i++) { - mac[i] = (unsigned char) val[i]; - } - } else { - printf("Get HW address failed\r\n"); - mbed_default_mac_address(mac); - } -} - -void RTW_EMAC::wlan_emac_link_change(bool up) -{ - if (emac_link_state_cb) { - emac_link_state_cb(up); - } -} - -RTW_EMAC &RTW_EMAC::get_instance() { - static RTW_EMAC rtw_emac; - return rtw_emac; -} -// Weak so a module can override -MBED_WEAK EMAC &EMAC::get_default_instance() { - return RTW_EMAC::get_instance(); -} -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.h b/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.h deleted file mode 100644 index d96d76d1e80..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.h +++ /dev/null @@ -1,164 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef RTW_EMAC_H -#define RTW_EMAC_H - -#include "EMAC.h" -#include "rtos/Mutex.h" -#include "netif.h" -#include "EMACMemoryManager.h" - - -class RTW_EMAC : public EMAC { -public: - RTW_EMAC(); - - static RTW_EMAC &get_instance(); - - /** - * Return maximum transmission unit - * - * @return MTU in bytes - */ - virtual uint32_t get_mtu_size() const; - - /** - * Gets memory buffer alignment preference - * - * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not - * align link out memory buffer chains using the alignment. - * - * @return Memory alignment requirement in bytes - */ - virtual uint32_t get_align_preference() const; - - /** - * Return interface name - * - * @param name Pointer to where the name should be written - * @param size Maximum number of character to copy - */ - virtual void get_ifname(char *name, uint8_t size) const; - - /** - * Returns size of the underlying interface HW address size. - * - * @return HW address size in bytes - */ - virtual uint8_t get_hwaddr_size() const; - - /** - * Return interface-supplied HW address - * - * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size - * - * HW address need not be provided if this interface does not have its own HW - * address configuration; stack will choose address from central system - * configuration if the function returns false and does not write to addr. - * - * @param addr HW address for underlying interface - * @return true if HW address is available - */ - virtual bool get_hwaddr(uint8_t *addr) const; - - /** - * Set HW address for interface - * - * Provided address has to be of correct size, see @a get_hwaddr_size - * - * Called to set the MAC address to actually use - if @a get_hwaddr is provided - * the stack would normally use that, but it could be overridden, eg for test - * purposes. - * - * @param addr Address to be set - */ - virtual void set_hwaddr(const uint8_t *addr); - - /** - * Sends the packet over the link - * - * That can not be called from an interrupt context. - * - * @param buf Packet to be send - * @return True if the packet was send successfully, False otherwise - */ - virtual bool link_out(emac_mem_buf_t *buf); - - /** - * Initializes the HW - * - * @return True on success, False in case of an error. - */ - virtual bool power_up(); - - /** - * Deinitializes the HW - * - */ - virtual void power_down(); - - /** - * Sets a callback that needs to be called for packets received for that interface - * - * @param input_cb Function to be register as a callback - */ - virtual void set_link_input_cb(emac_link_input_cb_t input_cb); - - /** - * Sets a callback that needs to be called on link status changes for given interface - * - * @param state_cb Function to be register as a callback - */ - virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); - - /** Add device to a multicast group - * - * @param address A multicast group hardware address - */ - virtual void add_multicast_group(const uint8_t *address); - - /** Remove device from a multicast group - * - * @param address A multicast group hardware address - */ - virtual void remove_multicast_group(const uint8_t *address); - - /** Request reception of all multicast packets - * - * @param all True to receive all multicasts - * False to receive only multicasts addressed to specified groups - */ - virtual void set_all_multicast(bool all); - - /** Sets memory manager that is used to handle memory buffers - * - * @param mem_mngr Pointer to memory manager - */ - virtual void set_memory_manager(EMACMemoryManager &mem_mngr); - - virtual void wlan_emac_link_change(bool up); - -private: - static void wlan_emac_recv(void *param, struct netif *netif, uint32_t len); - void *emac_link_input_data; - void *emac_link_state_data; - emac_link_input_cb_t emac_link_input_cb; - emac_link_state_change_cb_t emac_link_state_cb; - EMACMemoryManager *memory_manager; -}; -#endif /* RTW_EMAC_H_ */ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/dlist.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/dlist.h deleted file mode 100644 index 85e3aeef16a..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/dlist.h +++ /dev/null @@ -1,279 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ -#ifndef __LIST_H -#define __LIST_H - -#if defined ( __CC_ARM ) -#ifndef inline -#define inline __inline -#endif -#endif - -/* This file is from Linux Kernel (include/linux/list.h) - * and modified by simply removing hardware prefetching of list items. - * Here by copyright, credits attributed to wherever they belong. - * Kulesh Shanmugasundaram (kulesh [squiggly] isis.poly.edu) - */ - -/* - * Simple doubly linked list implementation. - * - * Some of the internal functions ("__xxx") are useful when - * manipulating whole lists rather than single entries, as - * sometimes we already know the next/prev entries and we can - * generate better code by using them directly rather than - * using the generic single-entry routines. - */ - -struct list_head { - struct list_head *next, *prev; -}; - -#define LIST_HEAD_INIT(name) { &(name), &(name) } - -#define LIST_HEAD(name) \ - struct list_head name = LIST_HEAD_INIT(name) - -#define INIT_LIST_HEAD(ptr) do { \ - (ptr)->next = (ptr); (ptr)->prev = (ptr); \ -} while (0) - -/* - * Insert a new entry between two known consecutive entries. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -static inline void __list_add(struct list_head *newitem, - struct list_head *prev, - struct list_head *next) -{ - next->prev = newitem; - newitem->next = next; - newitem->prev = prev; - prev->next = newitem; -} - -/** - * list_add - add a new entry - * @new: new entry to be added - * @head: list head to add it after - * - * Insert a new entry after the specified head. - * This is good for implementing stacks. - */ -static inline void list_add(struct list_head *newitem, struct list_head *head) -{ - __list_add(newitem, head, head->next); -} - -/** - * list_add_tail - add a new entry - * @new: new entry to be added - * @head: list head to add it before - * - * Insert a new entry before the specified head. - * This is useful for implementing queues. - */ -static inline void list_add_tail(struct list_head *newitem, struct list_head *head) -{ - __list_add(newitem, head->prev, head); -} - -/* - * Delete a list entry by making the prev/next entries - * point to each other. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -static inline void __list_del(struct list_head *prev, struct list_head *next) -{ - next->prev = prev; - prev->next = next; -} - -/** - * list_del - deletes entry from list. - * @entry: the element to delete from the list. - * Note: list_empty on entry does not return true after this, the entry is in an undefined state. - */ -static inline void list_del(struct list_head *entry) -{ - __list_del(entry->prev, entry->next); - entry->next = (struct list_head *) 0; - entry->prev = (struct list_head *) 0; -} - -/** - * list_del_init - deletes entry from list and reinitialize it. - * @entry: the element to delete from the list. - */ -static inline void list_del_init(struct list_head *entry) -{ - __list_del(entry->prev, entry->next); - INIT_LIST_HEAD(entry); -} - -/** - * list_move - delete from one list and add as another's head - * @list: the entry to move - * @head: the head that will precede our entry - */ -static inline void list_move(struct list_head *list, struct list_head *head) -{ - __list_del(list->prev, list->next); - list_add(list, head); -} - -/** - * list_move_tail - delete from one list and add as another's tail - * @list: the entry to move - * @head: the head that will follow our entry - */ -static inline void list_move_tail(struct list_head *list, - struct list_head *head) -{ - __list_del(list->prev, list->next); - list_add_tail(list, head); -} - -/** - * list_empty - tests whether a list is empty - * @head: the list to test. - */ -static inline int list_empty(struct list_head *head) -{ - return head->next == head; -} - -static inline void __list_splice(struct list_head *list, - struct list_head *head) -{ - struct list_head *first = list->next; - struct list_head *last = list->prev; - struct list_head *at = head->next; - - first->prev = head; - head->next = first; - - last->next = at; - at->prev = last; -} - -/** - * list_splice - join two lists - * @list: the new list to add. - * @head: the place to add it in the first list. - */ -static inline void list_splice(struct list_head *list, struct list_head *head) -{ - if (!list_empty(list)) - __list_splice(list, head); -} - -/** - * list_splice_init - join two lists and reinitialise the emptied list. - * @list: the new list to add. - * @head: the place to add it in the first list. - * - * The list at @list is reinitialised - */ -static inline void list_splice_init(struct list_head *list, - struct list_head *head) -{ - if (!list_empty(list)) { - __list_splice(list, head); - INIT_LIST_HEAD(list); - } -} - -/** - * list_entry - get the struct for this entry - * @ptr: the &struct list_head pointer. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_struct within the struct. - */ -#define list_entry(ptr, type, member) \ - ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member))) - -/** -* list_first_entry - get the first element from a list -* @ptr: the list head to take the element from. -* @type: the type of the struct this is embedded in. -* @member: the name of the list_head within the struct. -* -* Note, that list is expected to be not empty. -*/ - -#define list_first_entry(ptr, type, member) \ - list_entry((ptr)->next, type, member) - - -/** - * list_for_each - iterate over a list - * @pos: the &struct list_head to use as a loop counter. - * @head: the head for your list. - */ -#define list_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); \ - pos = pos->next) -/** - * list_for_each_prev - iterate over a list backwards - * @pos: the &struct list_head to use as a loop counter. - * @head: the head for your list. - */ -#define list_for_each_prev(pos, head) \ - for (pos = (head)->prev; pos != (head); \ - pos = pos->prev) - -/** - * list_for_each_safe - iterate over a list safe against removal of list entry - * @pos: the &struct list_head to use as a loop counter. - * @n: another &struct list_head to use as temporary storage - * @head: the head for your list. - */ -#define list_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) - -/** - * list_for_each_entry - iterate over list of given type - * @pos: the type * to use as a loop counter. - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define list_for_each_entry(pos, head, member, type) \ - for (pos = list_entry((head)->next, type, member); \ - &pos->member != (head); \ - pos = list_entry(pos->member.next, type, member)) - -/** - * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @pos: the type * to use as a loop counter. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define list_for_each_entry_safe(pos, n, head, member, type) \ - for (pos = list_entry((head)->next, type, member), \ - n = list_entry(pos->member.next, type, member); \ - &pos->member != (head); \ - pos = n, n = list_entry(n->member.next, type, member)) - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h deleted file mode 100644 index d3b7499fc1d..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h +++ /dev/null @@ -1,56 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ -#ifndef __PLATFORM_STDLIB_H__ -#define __PLATFORM_STDLIB_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(CONFIG_PLATFORM_8195A)+\ - defined(CONFIG_PLATFORM_8711B)+\ - defined(CONFIG_PLATFORM_8721D)+\ - defined(CONFIG_PLATFORM_8195BHP)+\ - defined(USE_STM322xG_EVAL)+\ - defined(USE_STM324xG_EVAL)+\ - defined(STM32F10X_XL) > 1 - #error "Cannot define two or more platform at one time" -#endif - -#if defined(CONFIG_PLATFORM_8195A) - #include "platform_stdlib_rtl8195a.h" -#elif defined (CONFIG_PLATFORM_8711B) - #include "platform_stdlib_rtl8711b.h" -#elif defined (CONFIG_PLATFORM_8721D) - #include "platform_stdlib_rtl8721d.h" -#elif defined(CONFIG_PLATFORM_8195BHP) - #include "platform_stdlib_rtl8195bhp.h" -#elif defined(USE_STM322xG_EVAL) || defined(USE_STM324xG_EVAL) || defined(STM32F10X_XL) - #include "platform_stdlib_stm32.h" -#elif defined (CONFIG_PLATFORM_8710C) - #include "platform_stdlib_rtl8710c.h" -#else - #error "Undefined Platform stdlib" -#endif - -#if (CONFIG_PLATFORM_AMEBA_X == 0) -#include "basic_types.h" -#endif - -#ifdef __cplusplus -} -#endif -#endif //__PLATFORM_STDLIB_H__ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib_rtl8195a.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib_rtl8195a.h deleted file mode 100644 index 84ee1c47271..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib_rtl8195a.h +++ /dev/null @@ -1,166 +0,0 @@ -#ifndef PLATFORM_STDLIB_RTL8195A_H -#define PLATFORM_STDLIB_RTL8195A_H - -#define USE_CLIB_PATCH 0 - -#if defined (__GNUC__) - /* build rom should set USE_RTL_ROM_CLIB=0 */ - #if !defined(CONFIG_MBED_ENABLED) - #include - #endif -#endif - -#if defined(CONFIG_BUILD_ROM) || defined(CONFIG_MBED_ENABLED) - #define USE_RTL_ROM_CLIB 0 -#else - #define BUFFERED_PRINTF 0 - #define USE_RTL_ROM_CLIB 1 -#endif - -#if defined (__IARSTDLIB__) - #include - #include - #include - #include - #include "diag.h" - - #define strsep(str, delim) _strsep(str, delim) -#elif defined (__CC_ARM) - #include - #include - #include - #include - #include "diag.h" - #define strsep(str, delim) _strsep(str, delim) -#elif defined (CONFIG_MBED_ENABLED) - #include - #include - #include - #include - #include "diag.h" - - #define strsep(str, delim) _strsep(str, delim) -#else - #include - #include - #include - #include "diag.h" - #include "strproc.h" - #include "basic_types.h" - #include "hal_misc.h" - #if USE_RTL_ROM_CLIB - #include "rtl_lib.h" - #endif - - #undef printf - #undef sprintf - #undef snprintf - #undef atoi - #undef memcmp - #undef memcpy - #undef memset - #undef strcmp - #undef strcpy - #undef strlen - #undef strncmp - #undef strncpy - #undef strsep - #undef strtok - #if USE_RTL_ROM_CLIB - #undef memchr - #undef memmove - #undef strcat - #undef strchr - #undef strncat - #undef strstr - #endif - - #if USE_RTL_ROM_CLIB - #if BUFFERED_PRINTF - extern int buffered_printf(const char* fmt, ...); - #define printf buffered_printf - #else - #define printf rtl_printf - #endif - - #define sprintf rtl_sprintf - #define snprintf rtl_snprintf - #define memchr rtl_memchr - #define memcmp rtl_memcmp - #define memcpy rtl_memcpy - #define memmove rtl_memmove - #define memset rtl_memset - #define strcat rtl_strcat - #define strchr rtl_strchr - #define strcmp(s1, s2) rtl_strcmp((const char *)s1, (const char *)s2) - #define strcpy rtl_strcpy - #define strlen(str) rtl_strlen((const char *)str) - #define strncat rtl_strncat - #define strncmp(s1, s2, n) rtl_strncmp((const char *)s1, (const char *)s2, n) - #define strncpy rtl_strncpy - #define strstr rtl_strstr - #define strsep rtl_strsep - #define strtok rtl_strtok - #else - #if USE_CLIB_PATCH - extern int DiagSscanfPatch(const char *buf, const char *fmt, ...); - extern char* DiagStrtokPatch(char *str, const char* delim); - extern char* DiagStrstrPatch(char *string, char *substring); - extern int DiagSnPrintfPatch(char *buf, size_t size, const char *fmt, ...); - extern u32 DiagPrintfPatch(const char *fmt, ...); - extern u32 DiagSPrintfPatch(u8 *buf, const char *fmt, ...); - #define printf DiagPrintfPatch - #define sprintf DiagSPrintfPatch - #define snprintf DiagSnPrintfPatch - #define strstr(a, b) DiagStrstrPatch((char *)(a), (char *)(b)) - #define strtok DiagStrtokPatch - #else - #define printf DiagPrintf - #define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg) - #if defined (__GNUC__) - #define snprintf DiagSnPrintf // NULL function - #define strstr(str1, str2) prvStrStr(str1, str2) // NULL function - #endif - #define strtok(str, delim) _strsep(str, delim) - #endif - #define memcmp(dst, src, sz) _memcmp(dst, src, sz) - #define memcpy(dst, src, sz) _memcpy(dst, src, sz) - #define memset(dst, val, sz) _memset(dst, val, sz) - #define strchr(s, c) _strchr(s, c) // for B-cut ROM - #define strcmp(str1, str2) prvStrCmp((const unsigned char *) str1, (const unsigned char *) str2) - #define strcpy(dest, src) _strcpy(dest, src) - #define strlen(str) prvStrLen((const unsigned char *) str) - #define strncmp(str1, str2, cnt) _strncmp(str1, str2, cnt) - #define strncpy(dest, src, count) _strncpy(dest, src, count) - #define strsep(str, delim) _strsep(str, delim) - #endif - - #define atoi(str) prvAtoi(str) - #define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM - - #if USE_CLIB_PATCH - #undef sscanf - #define sscanf DiagSscanfPatch - #else - #if defined (__GNUC__) - #undef sscanf //_sscanf - //extern int DiagSscanfPatch(const char *buf, const char *fmt, ...); - //#define sscanf DiagSscanfPatch - #define sscanf sscanf // use libc sscanf - #endif - #endif -#endif // defined (__IARSTDLIB__) - -// -// memory management -// -#if defined(CONFIG_MBED_ENABLED) - //use libc memory functions -#else - extern void *pvPortMalloc( size_t xWantedSize ); - extern void vPortFree( void *pv ); - #define malloc pvPortMalloc - #define free vPortFree -#endif - -#endif // PLATFORM_STDLIB_RTL8195A_H diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_conf.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_conf.h deleted file mode 100644 index d8587513336..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_conf.h +++ /dev/null @@ -1,954 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - ****************************************************************************** - * @file wifi_conf.h - * @author - * @version - * @brief This file provides user interface for Wi-Fi station and AP mode configuration - * base on the functionalities provided by Realtek Wi-Fi driver. - ****************************************************************************** - */ -#ifndef __WIFI_API_H -#define __WIFI_API_H - -/** @addtogroup nic NIC - * @ingroup wlan - * @brief NIC functions - * @{ - */ - -#include "wifi_constants.h" -#include "wifi_structures.h" -#include "wifi_util.h" -#include "wifi_ind.h" -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/****************************************************** - * Macros - ******************************************************/ - -#define RTW_ENABLE_API_INFO - -#ifdef RTW_ENABLE_API_INFO -#if defined(CONFIG_MBED_ENABLED) - extern __u32 GlobalDebugEnable; - #define RTW_API_INFO(...) do {\ - if (GlobalDebugEnable) \ - printf(__VA_ARGS__);\ - }while(0) -#else - #define RTW_API_INFO printf -#endif -#else - #define RTW_API_INFO(args) -#endif - -#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] -#define CMP_MAC( a, b ) (((a[0])==(b[0]))&& \ - ((a[1])==(b[1]))&& \ - ((a[2])==(b[2]))&& \ - ((a[3])==(b[3]))&& \ - ((a[4])==(b[4]))&& \ - ((a[5])==(b[5]))) - -/****************************************************** - * Constants - ******************************************************/ -#define SCAN_LONGEST_WAIT_TIME (4500) - - -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" - -#define PSCAN_ENABLE 0x01 //enable for partial channel scan -#define PSCAN_FAST_SURVEY 0x02 //set to select scan time to FAST_SURVEY_TO, otherwise SURVEY_TO -#define PSCAN_SIMPLE_CONFIG 0x04 //set to select scan time to FAST_SURVEY_TO and resend probe request - -/****************************************************** - * Type Definitions - ******************************************************/ - -/** Scan result callback function pointer type - * - * @param result_ptr : A pointer to the pointer that indicates where to put the next scan result - * @param user_data : User provided data - */ -typedef void (*rtw_scan_result_callback_t)( rtw_scan_result_t** result_ptr, void* user_data ); -typedef rtw_result_t (*rtw_scan_result_handler_t)( rtw_scan_handler_result_t* malloced_scan_result ); - -/****************************************************** - * Structures - ******************************************************/ -typedef struct { - char *buf; - int buf_len; -} scan_buf_arg; - -/****************************************************** - * Structures - ******************************************************/ -typedef struct internal_scan_handler{ - rtw_scan_result_t** pap_details; - rtw_scan_result_t * ap_details; - int scan_cnt; - rtw_bool_t scan_complete; - unsigned char max_ap_size; - rtw_scan_result_handler_t gscan_result_handler; -#if SCAN_USE_SEMAPHORE - void *scan_semaphore; -#else - int scan_running; -#endif - void* user_data; - unsigned int scan_start_time; -} internal_scan_handler_t; - -typedef struct { - rtw_network_info_t network_info; - void *join_sema; -} internal_join_result_t; - -/****************************************************** - * Function Declarations - ******************************************************/ -/** - * @brief Initialize Realtek WiFi API System. - * - Initialize the required parts of the software platform. - * i.e. worker, event registering, semaphore, etc. - * - Initialize the RTW API thread which handles the asynchronous event. - * @return RTW_SUCCESS if initialization is successful, RTW_ERROR otherwise - */ -int wifi_manager_init(void); - -/** - * @brief Join a Wi-Fi network. - * Scan for, associate and authenticate with a Wi-Fi network. - * On successful return, the system is ready to send data packets. - * - * @param[in] ssid: A null terminated string containing the SSID name of the network to join. - * @param[in] security_type: Authentication type: - * - RTW_SECURITY_OPEN - Open Security - * - RTW_SECURITY_WEP_PSK - WEP Security with open authentication - * - RTW_SECURITY_WEP_SHARED - WEP Security with shared authentication - * - RTW_SECURITY_WPA_TKIP_PSK - WPA Security - * - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher - * - RTW_SECURITY_WPA2_TKIP_PSK - WPA2 Security using TKIP cipher - * - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers - * @param[in] password: A byte array containing either the cleartext security key for WPA/WPA2 - * secured networks, or a pointer to an array of rtw_wep_key_t - * structures for WEP secured networks. - * @param[in] ssid_len: The length of the SSID in bytes. - * @param[in] password_len: The length of the security_key in bytes. - * @param[in] key_id: The index of the wep key (0, 1, 2, or 3). If not using it, leave it with value -1. - * @param[in] semaphore: A user provided semaphore that is flagged when the join is complete. If not using it, leave it with NULL value. - * @return RTW_SUCCESS: when the system is joined and ready to send data packets. - * @return RTW_ERROR: if an error occurred. - * @note Please make sure the Wi-Fi is enabled before invoking this function. (@ref wifi_on()) - */ -int wifi_connect( - char *ssid, - rtw_security_t security_type, - char *password, - int ssid_len, - int password_len, - int key_id, - void *semaphore); - -/** - * @brief Join a Wi-Fi network with specified BSSID. - * Scan for, associate and authenticate with a Wi-Fi network. - * On successful return, the system is ready to send data packets. - * @param[in] bssid: The specified BSSID to connect. - * @param[in] ssid: A null terminated string containing the SSID name of the network to join. - * @param[in] security_type: Authentication type: - * - RTW_SECURITY_OPEN - Open Security - * - RTW_SECURITY_WEP_PSK - WEP Security with open authentication - * - RTW_SECURITY_WEP_SHARED - WEP Security with shared authentication - * - RTW_SECURITY_WPA_TKIP_PSK - WPA Security - * - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher - * - RTW_SECURITY_WPA2_TKIP_PSK - WPA2 Security using TKIP cipher - * - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers - * @param[in] password: A byte array containing either the cleartext security key for WPA/WPA2 - * secured networks, or a pointer to an array of rtw_wep_key_t - * structures for WEP secured networks. - * @param[in] ssid_len: The length of the SSID in bytes. - * @param[in] password_len: The length of the security_key in bytes. - * @param[in] key_id: The index of the wep key. - * @param[in] semaphore: A user provided semaphore that is flagged when the join is complete. - * @return RTW_SUCCESS: when the system is joined and ready to send data packets. - * @return RTW_ERROR: if an error occurred. - * @note Please make sure the Wi-Fi is enabled before invoking this function. (@ref wifi_on()) - * @note The difference between @ref wifi_connect_bssid() and @ref wifi_connect() is that BSSID has higher priority as the basis of connection in @ref wifi_connect_bssid. - */ -int wifi_connect_bssid( - unsigned char bssid[ETH_ALEN], - char *ssid, - rtw_security_t security_type, - char *password, - int bssid_len, - int ssid_len, - int password_len, - int key_id, - void *semaphore); - -/** - * @brief Disassociates from current Wi-Fi network. - * @param None - * @return RTW_SUCCESS: On successful disassociation from the AP. - * @return RTW_ERROR: If an error occurred. - */ -int wifi_disconnect(void); - -/** -* @brief Check if Wi-Fi has connected to AP before dhcp. -* @param None -* @return RTW_SUCCESS: If conneced. -* @return RTW_ERROR: If not connect. -*/ -int wifi_is_connected_to_ap(void); - -/** - * @brief Check if the specified interface is up. - * @param[in] interface: The interface can be set as RTW_STA_INTERFACE or RTW_AP_INTERFACE. (@ref rtw_interface_t) - * @return If the function succeeds, the return value is 1. Otherwise, return 0. - */ -int wifi_is_up(rtw_interface_t interface); - -/** Determines if a particular interface is ready to transceive ethernet packets - * - * @param Radio interface to check, options are - * RTW_STA_INTERFACE, RTW_AP_INTERFACE - * @return RTW_SUCCESS : if the interface is ready to - * transceive ethernet packets - * @return RTW_ERROR : if the interface is not ready to - * transceive ethernet packets - */ -int wifi_is_ready_to_transceive(rtw_interface_t interface); - -/** - * @brief This function sets the current Media Access Control (MAC) address of the 802.11 device. - * @param[in] mac: Wi-Fi MAC address. - * @return RTW_SUCCESS or RTW_ERROR - */ -int wifi_set_mac_address(char * mac); - -/** - * @brief Retrieves the current Media Access Control (MAC) address - * (or Ethernet hardware address) of the 802.11 device. - * @param[in] mac: Point to the result of the mac address will be get. - * @return RTW_SUCCESS or RTW_ERROR - */ -int wifi_get_mac_address(char * mac); - -/** - * @brief Enable Wi-Fi powersave mode. - * @param None - * @return RTW_SUCCESS or RTW_ERROR. - */ -int wifi_enable_powersave(void); - -/** - * @brief Disable Wi-Fi powersave mode. - * @param None - * @return RTW_SUCCESS or RTW_ERROR. - */ -int wifi_disable_powersave(void); - -/** Gets the tx power in index units - * - * @param dbm : The variable to receive the tx power in index. - * - * @return RTW_SUCCESS : if successful - * RTW_ERROR : if not successful - */ -int wifi_get_txpower(int *poweridx); - -/** - * @brief Set the tx power in index units. - * @param[in] poweridx: The desired tx power in index. - * @return RTW_SUCCESS: if tx power is successfully set - * @return RTW_ERROR: if tx power is not successfully set - */ -int wifi_set_txpower(int poweridx); - -/** - * @brief Get the associated clients with SoftAP. - * @param[out] client_list_buffer: The location where the client list will be stored. - * @param[in] buffer_length: The buffer length. - * @return RTW_SUCCESS: The result is successfully got. - * @return RTW_ERROR: The result is not successfully got. - */ -int wifi_get_associated_client_list(void * client_list_buffer, unsigned short buffer_length); - -/** - * @brief Get connected AP's BSSID - * @param[out] bssid : the location where the AP BSSID will be stored - * @return RTW_SUCCESS : if result was successfully get - * @return RTW_ERROR : if result was not successfully get - */ -int wifi_get_ap_bssid(unsigned char *bssid); - -/** - * @brief Get the SoftAP information. - * @param[out] ap_info: The location where the AP info will be stored. - * @param[out] security: The security type. - * @return RTW_SUCCESS: The result is successfully got. - * @return RTW_ERROR: The result is not successfully got. - */ -int wifi_get_ap_info(rtw_bss_info_t * ap_info, rtw_security_t* security); - -/** - * @brief Set the country code to driver to determine the channel set. - * @param[in] country_code: Specify the country code. - * @return RTW_SUCCESS: If result is successfully set. - * @return RTW_ERROR: If result is not successfully set. - */ -int wifi_set_country(rtw_country_code_t country_code); - -/** - * @brief retrieved sta mode MAX data rate. - * @param[out] inidata_rate: MAX data rate. - * @return RTW_SUCCESS: If the INIDATA_RATE is successfully retrieved. - * @return RTW_ERROR: If the INIDATA_RATE is not retrieved. - * note: inidata_rate = 2 * (data rate), you need inidata_rate/2.0 to get the real rate - */ -int wifi_get_sta_max_data_rate(__u8 * inidata_rate); - -/** - * @brief Retrieve the latest RSSI value. - * @param[out] pRSSI: Points to the integer to store the RSSI value gotten from driver. - * @return RTW_SUCCESS: If the RSSI is succesfully retrieved. - * @return RTW_ERROR: If the RSSI is not retrieved. - */ -int wifi_get_rssi(int *pRSSI); - -/** - * @brief Set the listening channel for promiscuous mode. - * @param[in] channel: The desired channel. - * @return RTW_SUCCESS: If the channel is successfully set. - * @return RTW_ERROR: If the channel is not successfully set. - * @note Do NOT need to call this function for STA mode wifi driver, since it will determine the channel from received beacon. - */ -int wifi_set_channel(int channel); - -/** - * @brief Get the current channel on STA interface. - * @param[out] channel: A pointer to the variable where the - * channel value will be written - * @return RTW_SUCCESS: If the channel is successfully read. - * @return RTW_ERROR: If the channel is not successfully read. - */ -int wifi_get_channel(int *channel); - -/** - * @brief Register interest in a multicast address.\n - * Once a multicast address has been registered, all packets detected on the - * medium destined for that address are forwarded to the host. - * Otherwise they are ignored. - * @param[in] mac: Ethernet MAC address - * @return RTW_SUCCESS: If the address is registered successfully. - * @return RTW_ERROR: If the address is not registered. - */ -int wifi_register_multicast_address(rtw_mac_t *mac); - -/** - * @brief Unregister interest in a multicast address.\n - * Once a multicast address has been unregistered, all packets detected on the - * medium destined for that address are ignored. - * @param[in] mac: Ethernet MAC address - * @return RTW_SUCCESS: If the address is unregistered successfully. - * @return RTW_ERROR: If the address is not unregistered. - */ -int wifi_unregister_multicast_address(rtw_mac_t *mac); - -/** - * @brief Setup the adaptivity mode. - * You can replace this weak function by the same name funcation to setup adaptivity mode you want. - * @param None - * @return If the function succeeds, the return value is 0. - */ -_WEAK void wifi_set_mib(void); - -/** - * @brief Setup country code. - * You can replace this weak function by the same name funcation to setup country code you want. - * @param None - * @return If the function succeeds, the return value is 0. - */ -//----------------------------------------------------------------------------// -_WEAK void wifi_set_country_code(void); - -/** - * @brief Enable Wi-Fi RF. - * @param None - * @return If the function succeeds, the return value is 0. - * @note The difference between @ref wifi_rf_on() and @ref wifi_on() is that @ref wifi_rf_on() simply enable RF HAL, it does not enable the driver or allocate memory. - */ -int wifi_rf_on(void); - -/** - * @brief Disable Wi-Fi RF. - * @param None - * @return If the function succeeds, the return value is 0. - * @note The difference between @ref wifi_rf_off() and @ref wifi_off() is that @ref wifi_rf_off() simply disable RF HAL, the driver and used heap memory will NOT be released. - */ -int wifi_rf_off(void); - -/** - * @brief Enable Wi-Fi. - * - Bring the Wireless interface "Up" - * - Initialize the driver thread which arbitrates access - * to the SDIO/SPI bus - * - * @param[in] mode: Decide to enable WiFi in which mode. The optional modes are enumerated in @ref rtw_mode_t. - * @return RTW_SUCCESS: if the WiFi chip was initialized successfully. - * @return RTW_ERROR: if the WiFi chip was not initialized successfully. - */ -int wifi_on(rtw_mode_t mode); - -/** - * @brief Disable Wi-Fi. - * - * @param None - * @return RTW_SUCCESS: if deinitialization is successful. - * @return RTW_ERROR: otherwise. - */ -int wifi_off(void); - -/** - * Turn off the Wi-Fi device - * - * - Bring the Wireless interface "Down" - * - De-Initialises the driver thread which arbitrates access - * to the SDIO/SPI bus - * - * @return RTW_SUCCESS if deinitialization is successful, - * RTW_ERROR otherwise - */ -int wifi_off_fastly(void); - -/** - * @brief Set IPS/LPS mode. - * @param[in] ips_mode: The desired IPS mode. It becomes effective when wlan enter ips.\n - * @ref ips_mode is inactive power save mode. Wi-Fi automatically turns RF off if it is not associated to AP. Set 1 to enable inactive power save mode. - * @param[in] lps_mode: The desired LPS mode. It becomes effective when wlan enter lps.\n - * @ref lps_mode is leisure power save mode. Wi-Fi automatically turns RF off during the association to AP is traffic is not busy while it also automatically turns RF on to listen to beacon. Set 1 to enable leisure power save mode. - * @return RTW_SUCCESS if setting LPS mode successful. - * @return RTW_ERROR otherwise. - */ - -int wifi_set_power_mode(unsigned char ips_mode, unsigned char lps_mode); - -/** - * Set TDMA parameters - * - * @param[in] slot_period : We separate TBTT into 2 or 3 slots. - * If we separate TBTT into 2 slots, then slot_period should be larger or equal to 50ms. - * It means 2 slot period is - * slot_period, 100-slot_period - * If we separate TBTT into 3 slots, then slot_period should be less or equal to 33ms. - * It means 3 slot period is - * 100 - 2 * slot_period, slot_period, slot_period - * @param[in] rfon_period_len_1: rf on period of slot 1 - * @param[in] rfon_period_len_2: rf on period of slot 2 - * @param[in] rfon_period_len_3: rf on period of slot 3 - * - * @return RTW_SUCCESS if setting TDMA parameters successful - * RTW_ERROR otherwise - */ -int wifi_set_tdma_param(unsigned char slot_period, unsigned char rfon_period_len_1, unsigned char rfon_period_len_2, unsigned char rfon_period_len_3); - -/** - * @brief Set LPS DTIM. - * @param[in] dtim: In LPS, the package can be buffered at AP side. - * STA leave LPS until dtim count of packages buffered at AP side. - * @return RTW_SUCCESS if setting LPS dtim successful. - * @return RTW_ERROR otherwise - */ -int wifi_set_lps_dtim(unsigned char dtim); - -/** - * @brief Get LPS DTIM. - * @param[out] dtim: In LPS, the package can be buffered at AP side. - * STA leave LPS until dtim count of packages buffered at AP side. - * @return RTW_SUCCESS if getting LPS dtim successful. - * @return RTW_ERROR otherwise. - */ -int wifi_get_lps_dtim(unsigned char *dtim); - -/** - * @brief Trigger Wi-Fi driver to start an infrastructure Wi-Fi network. - * @warning If a STA interface is active when this function is called, the softAP will - * start on the same channel as the STA. It will NOT use the channel provided! - * @param[in] ssid: A null terminated string containing the SSID name of the network. - * @param[in] security_type: - * - RTW_SECURITY_OPEN - Open Security - * - RTW_SECURITY_WPA_TKIP_PSK - WPA Security - * - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher - * - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers - * - WEP security is NOT IMPLEMENTED. It is NOT SECURE! - * @param[in] password: A byte array containing the cleartext security key for the network. - * @param[in] ssid_len: The length of the SSID in bytes. - * @param[in] password_len: The length of the security_key in bytes. - * @param[in] channel: 802.11 channel number. - * @return RTW_SUCCESS: If successfully creates an AP. - * @return RTW_ERROR: If an error occurred. - * @note Please make sure the Wi-Fi is enabled before invoking this function. (@ref wifi_on()) - */ -int wifi_start_ap( - char *ssid, - rtw_security_t security_type, - char *password, - int ssid_len, - int password_len, - int channel); - -/** - * @brief Start an infrastructure Wi-Fi network with hidden SSID. - * @warning If a STA interface is active when this function is called, the softAP will - * start on the same channel as the STA. It will NOT use the channel provided! - * - * @param[in] ssid: A null terminated string containing - * the SSID name of the network to join. - * @param[in] security_type: Authentication type: \n - * - RTW_SECURITY_OPEN - Open Security - * - RTW_SECURITY_WPA_TKIP_PSK - WPA Security - * - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher - * - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers - * - WEP security is NOT IMPLEMENTED. It is NOT SECURE! - * @param[in] password: A byte array containing the cleartext - * security key for the network. - * @param[in] ssid_len: The length of the SSID in bytes. - * @param[in] password_len: The length of the security_key in bytes. - * @param[in] channel: 802.11 channel number - * - * @return RTW_SUCCESS: If successfully creates an AP. - * @return RTW_ERROR: If an error occurred. - */ -int wifi_start_ap_with_hidden_ssid( - char *ssid, - rtw_security_t security_type, - char *password, - int ssid_len, - int password_len, - int channel); - -/** - * @brief Initiate a scan to search for 802.11 networks. - * - * @param[in] scan_type: Specifies whether the scan should - * be Active, Passive or scan - * Prohibited channels - * @param[in] bss_type: Specifies whether the scan should - * search for Infrastructure - * networks (those using an Access - * Point), Ad-hoc networks, or both - * types. - * @param[in] result_ptr: Scan specific ssid. The first 4 - * bytes is ssid lenth, and ssid name - * append after it. - * If no specific ssid need to scan, - * PLEASE CLEAN result_ptr before pass - * it into parameter. - * @param[out] result_ptr: a pointer to a pointer to a result - * storage structure. - * @return RTW_SUCCESS or RTW_ERROR - * @note The scan progressively accumulates results over time, and - * may take between 1 and 3 seconds to complete. The results of - * the scan will be individually provided to the callback - * function. Note: The callback function will be executed in - * the context of the RTW thread. - * @note When scanning specific channels, devices with a - * strong signal strength on nearby channels may be - * detected - */ -int wifi_scan(rtw_scan_type_t scan_type, - rtw_bss_type_t bss_type, - void* result_ptr); - -/** - * @brief Initiate a scan to search for 802.11 networks, a higher level API based on wifi_scan - * to simplify the scan operation. - * @param[in] results_handler: The callback function which will receive and process the result data. - * @param[in] user_data: User specified data that will be passed directly to the callback function. - * @return RTW_SUCCESS or RTW_ERROR - * @note Callback must not use blocking functions, since it is called from the context of the RTW thread. - * The callback, user_data variables will be referenced after the function returns. - * Those variables must remain valid until the scan is completed. - * The usage of this api can reference ATWS in atcmd_wifi.c. - */ -int wifi_scan_networks(rtw_scan_result_handler_t results_handler, void* user_data); - -/** - * @brief Initiate a scan to search for 802.11 networks with specified SSID. - * @param[in] results_handler: The callback function which will receive and process the result data. - * @param[in] user_data: User specified data that will be passed directly to the callback function. - * @param[in] scan_buflen: The length of the result storage structure. - * @param[in] ssid: The SSID of target network. - * @param[in] ssid_len: The length of the target network SSID. - * @return RTW_SUCCESS or RTW_ERROR - * @note Callback must not use blocking functions, since it is called from the context of the RTW thread. - * The callback, user_data variables will be referenced after the function returns. - * Those variables must remain valid until the scan is completed. - */ -int wifi_scan_networks_with_ssid(int (results_handler)(char*, int, char *, void *), void* user_data, int scan_buflen, char* ssid, int ssid_len); - -/** -* @brief Set the channel used to be partial scanned. -* @param[in] channel_list: An array stores the channel list. -* @param[in] pscan_config: the pscan_config of the channel set. -* @param[in] length: The length of the channel_list. -* @return RTW_SUCCESS or RTW_ERROR. -* @note This function should be used with wifi_scan function. First, use @ref wifi_set_pscan_chan to -* indicate which channel will be scanned, and then use @ref wifi_scan to get scanned results. -*/ -int wifi_set_pscan_chan(__u8 * channel_list,__u8 * pscan_config, __u8 length); - -/** - * @brief Get current Wi-Fi setting from driver. - * @param[in] ifname: the wlan interface name, can be WLAN0_NAME or WLAN1_NAME. - * @param[out] pSetting: Points to the rtw_wifi_setting_t structure to store the WIFI setting gotten from driver. - * @return RTW_SUCCESS or RTW_ERROR. - */ -int wifi_get_setting(const char *ifname,rtw_wifi_setting_t *pSetting); - -/** - * @brief Show the network information stored in a rtw_wifi_setting_t structure. - * @param[in] ifname: the wlan interface name, can be WLAN0_NAME or WLAN1_NAME. - * @param[in] pSetting: Points to the rtw_wifi_setting_t structure which information is gotten by @ref wifi_get_setting(). - * @return RTW_SUCCESS or RTW_ERROR. - */ -int wifi_show_setting(const char *ifname,rtw_wifi_setting_t *pSetting); - -/** - * @brief -Set the network mode according to the data rate its supported. - * Driver works in BGN mode in default after driver initialization. This function is used to - * change wireless network mode for station mode before connecting to AP. - * @param[in] mode: Network mode to set. The value can be RTW_NETWORK_B/RTW_NETWORK_BG/RTW_NETWORK_BGN. - * @return RTW_SUCCESS or RTW_ERROR. - */ -int wifi_set_network_mode(rtw_network_mode_t mode); - -/** - * @brief Get the network mode. - * Driver works in BGN mode in default after driver initialization. This function is used to - * get the current wireless network mode for station mode. - * @param[in] pmode: Network mode to get. - * @return RTW_SUCCESS or RTW_ERROR. - */ -int wifi_get_network_mode(rtw_network_mode_t *pmode); - -/** - * @brief Set the chip to start or stop the promiscuous mode. - * @param[in] enabled: enabled can be set 0, 1, 2, 3 and 4. if enabled is zero, disable the promisc, else enable the promisc. - * - 0 means disable the promisc. - * - 1 means enable the promisc special for all ethernet frames. - * - 2 means enable the promisc special for Broadcast/Multicast ethernet frames. - * - 3 means enable the promisc special for all 802.11 frames. - * - 4 means enable the promisc special for Broadcast/Multicast 802.11 frames. - * @param[in] callback: the callback function which will - * receive and process the netowork data. - * @param[in] len_used: specify if the the promisc data length is used. - * If len_used set to 1, packet(frame data) length will be saved and transferred to callback function. - * - * @return RTW_SUCCESS or RTW_ERROR - * @note This function can be used to implement vendor specified simple configure. - * @note To fetch Ethernet frames, the len_used should be set to 1 - */ -int wifi_set_promisc(rtw_rcr_level_t enabled, void (*callback)(unsigned char*, unsigned int, void*), unsigned char len_used); - -/** - * @brief Let Wi-Fi enter promiscuous mode. - * @param[in] None - * @return None - */ -void wifi_enter_promisc_mode(void); - -/** Set the wps phase - * - * @param is_trigger_wps[in] : to trigger wps function or not - * - * @return RTW_SUCCESS or RTW_ERROR - */ -int wifi_set_wps_phase(unsigned char is_trigger_wps); - -/** - * @brief Trigger Wi-Fi driver to restart an infrastructure Wi-Fi network. - * @warning If a STA interface is active when this function is called, the softAP will - * start on the same channel as the STA. It will NOT use the channel provided! - * @param[in] ssid: A null terminated string containing the SSID name of the network. - * @param[in] security_type: - * - RTW_SECURITY_OPEN - Open Security - * - RTW_SECURITY_WPA_TKIP_PSK - WPA Security - * - RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher - * - RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers - * - WEP security is NOT IMPLEMENTED. It is NOT SECURE! - * @param[in] password: A byte array containing the cleartext security key for the network. - * @param[in] ssid_len: The length of the SSID in bytes. - * @param[in] password_len: The length of the security_key in bytes. - * @param[in] channel: 802.11 channel number. - * @return RTW_SUCCESS: If successfully creates an AP. - * @return RTW_ERROR: If an error occurred. - * @note Please make sure the Wi-Fi is enabled before invoking this function. (@ref wifi_on()) - */ -int wifi_restart_ap( - unsigned char *ssid, - rtw_security_t security_type, - unsigned char *password, - int ssid_len, - int password_len, - int channel); - -/** - * @brief Set reconnection mode with configuration. - * @param[in] mode: Set 1/0 to enalbe/disable the reconnection mode. - * @param[in] retry_times: The number of retry limit. - * @param[in] timeout: The timeout value (in seconds). - * @return 0 if success, otherwise return -1. - * @note Defining CONFIG_AUTO_RECONNECT in "autoconf.h" needs to be done before compiling, - * or this API won't be effective. - * @note The difference between @ref wifi_config_autoreconnect() and @ref wifi_set_autoreconnect() is that - * user can specify the retry times and timeout value in @ref wifi_config_autoreconnect(). - * But in @ref wifi_set_autoreconnect() these values are set with 3 retry limit and 5 seconds timeout as default. - */ -int wifi_config_autoreconnect(__u8 mode, __u8 retry_times, __u16 timeout); - -/** - * @brief Set reconnection mode with 3 retry limit and 5 seconds timeout as default. - * @param[in] mode: Set 1/0 to enalbe/disable the reconnection mode. - * @return 0 if success, otherwise return -1. - * @note Defining CONFIG_AUTO_RECONNECT in "autoconf.h" needs to be done before compiling, - * or this API won't be effective. - * @note The difference between @ref wifi_config_autoreconnect() and @ref wifi_set_autoreconnect() is that - * user can specify the retry times and timeout value in @ref wifi_config_autoreconnect(). - * But in @ref wifi_set_autoreconnect() these values are set with 3 retry limit and 5 seconds timeout as default. - */ -int wifi_set_autoreconnect(__u8 mode); - -/** - * @brief Get the result of setting reconnection mode. - * @param[out] mode: Point to the result of setting reconnection mode. - * @return 0 if success, otherwise return -1. - * @note Defining CONFIG_AUTO_RECONNECT in "autoconf.h" needs to be done before compiling, - * or this API won't be effective. - */ -int wifi_get_autoreconnect(__u8 *mode); - -/** - * @brief Present the device disconnect reason while connecting. - * @param None - * @return @ref rtw_connect_error_flag_t - * - 0: RTW_NO_ERROR - * - 1: RTW_NONE_NETWORK - * - 2: RTW_CONNECT_FAIL - * - 3: RTW_WRONG_PASSWORD - * - 4: RTW_DHCP_FAIL - * - 5: RTW_UNKNOWN (initial status) - */ -int wifi_get_last_error(void); - -#ifdef CONFIG_CUSTOM_IE -#ifndef BIT -#define BIT(x) ((__u32)1 << (x)) -#endif - -#ifndef _CUSTOM_IE_TYPE_ -#define _CUSTOM_IE_TYPE_ -/** - * @brief The enumeration is transmission type for wifi custom ie. - */ -enum CUSTOM_IE_TYPE{ - PROBE_REQ = BIT(0), - PROBE_RSP = BIT(1), - BEACON = BIT(2), -}; -typedef __u32 rtw_custom_ie_type_t; -#endif /* _CUSTOM_IE_TYPE_ */ - -/* ie format - * +-----------+--------+-----------------------+ - * |element ID | length | content in length byte| - * +-----------+--------+-----------------------+ - * - * type: refer to CUSTOM_IE_TYPE - */ -#ifndef _CUS_IE_ -#define _CUS_IE_ -/** - * @brief The structure is used to set WIFI custom ie list, and type match CUSTOM_IE_TYPE.\n - * The ie will be transmitted according to the type. - */ -typedef struct _cus_ie{ - __u8 *ie; - __u8 type; -}rtw_custom_ie_t, *p_rtw_custom_ie_t; -#endif /* _CUS_IE_ */ - -/** - * @brief Setup custom ie list. - * @warning This API can't be executed twice before deleting the previous custom ie list. - * @param[in] cus_ie: Pointer to WIFI CUSTOM IE list. - * @param[in] ie_num: The number of WIFI CUSTOM IE list. - * @return 0 if success, otherwise return -1. - * @note Defininig CONFIG_CUSTOM_IE in "autoconf.h" needs to be done before compiling, - * or this API won't be effective. - */ -int wifi_add_custom_ie(void *cus_ie, int ie_num); - -/** - * @brief Update the item in WIFI CUSTOM IE list. - * @param[in] cus_ie: Pointer to WIFI CUSTOM IE address. - * @param[in] ie_index: Index of WIFI CUSTOM IE list. - * @return 0 if success, otherwise return -1. - * @note Defininig CONFIG_CUSTOM_IE in "autoconf.h" needs to be done before compiling, - * or this API won't be effective. - */ -int wifi_update_custom_ie(void *cus_ie, int ie_index); - -/** - * @brief Delete WIFI CUSTOM IE list. - * @param None - * @return 0 if success, otherwise return -1. - * @note Defininig CONFIG_CUSTOM_IE in "autoconf.h" needs to be done before compiling, - * or this API won't be effective. - */ -int wifi_del_custom_ie(void); -#endif - -#ifdef CONFIG_PROMISC - -/** - * @brief Initialize packet filter related data. - * @param None - * @return None - */ -void wifi_init_packet_filter(void); - -/** - * @brief Add packet filter. - * @param[in] filter_id: The filter id. - * @param[in] patt: Point to the filter pattern. - * @param[in] rule: Point to the filter rule. - * @return 0 if success, otherwise return -1. - * @note For now, the maximum number of filters is 5. - */ -int wifi_add_packet_filter(unsigned char filter_id, rtw_packet_filter_pattern_t *patt, rtw_packet_filter_rule_t rule); - -/** - * @brief Enable the packet filter. - * @param[in] filter_id: The filter id. - * @return 0 if success, otherwise return -1. - * @note The filter can be used only if it has been enabled. - */ -int wifi_enable_packet_filter(unsigned char filter_id); - -/** - * @brief Disable the packet filter. - * @param[in] filter_id: The filter id. - * @return 0 if success, otherwise return -1. - */ -int wifi_disable_packet_filter(unsigned char filter_id); - -/** - * @brief Remove the packet filter. - * @param[in] filter_id: The filter id. - * @return 0 if success, otherwise return -1. - */ -int wifi_remove_packet_filter(unsigned char filter_id); -#endif - -/** - * @brief Get antenna infomation. - * @param[in] antenna: Points to store the antenna value gotten from driver, 0: main, 1: aux. - * @return 0 if success, otherwise return -1. - */ -#ifdef CONFIG_ANTENNA_DIVERSITY -int wifi_get_antenna_info(unsigned char *antenna); -#endif // #ifdef CONFIG_ANTENNA_DIVERSITY - -void wifi_set_indicate_mgnt(int enable); - -/** - * @brief Get the information of MP driver - * @param[out] ability : 0x1 stand for mp driver, and 0x0 stand for normal driver - * @return RTW_SUCCESS - */ -int wifi_get_drv_ability(uint32_t *ability); - -/** - * @brief Set channel plan into flash/efuse, must reboot after setting channel plan - * @param[in] channel_plan : the value of channel plan, define in wifi_constants.h - * @return RTW_SUCCESS or RTW_ERROR - */ -int wifi_set_channel_plan(uint8_t channel_plan); - -/** - * @brief Get channel plan from calibration section - * @param[out] channel_plan : point to the value of channel plan, define in wifi_constants.h - * @return RTW_SUCCESS or RTW_ERROR - */ -int wifi_get_channel_plan(uint8_t *channel_plan); - -#ifdef CONFIG_AP_MODE -/** - * @brief Enable packets forwarding in ap mode - * @return RTW_SUCCESS - */ -int wifi_enable_forwarding(void); - -/** - * @brief Disable packets forwarding in ap mode - * @return RTW_SUCCESS - */ -int wifi_disable_forwarding(void); -#endif - -#ifdef CONFIG_CONCURRENT_MODE -/** - * @brief Set flag for concurrent mode wlan1 issue_deauth when channel switched by wlan0 - * usage: wifi_set_ch_deauth(0) -> wlan0 wifi_connect -> wifi_set_ch_deauth(1) - * @param[in] enable : 0 for disable and 1 for enable - * @return RTW_SUCCESS - */ -int wifi_set_ch_deauth(__u8 enable); -#endif - -///@name Ameba1 Only -///@{ -/** - * @brief enable AP sending QoS Null0 Data to poll Sta be alive - * @param[in] enabled: enabled can be set to 0,1. - * - 0 means enable. - * - 1 means disable. - * @return None - */ -void wifi_set_ap_polling_sta(__u8 enabled); -///@} -#ifdef __cplusplus - } -#endif - -/*\@}*/ - -#endif // __WIFI_API_H - -//----------------------------------------------------------------------------// diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_ind.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_ind.h deleted file mode 100644 index 2c5f042d091..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_ind.h +++ /dev/null @@ -1,104 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - * @file wifi_ind.h - * @author - * @version - * @brief This file provides the functions related to event handler mechanism. - ****************************************************************************** - */ - -#ifndef _WIFI_INDICATE_H -#define _WIFI_INDICATE_H - -/** @addtogroup nic NIC - * @ingroup wlan - * @brief NIC functions - * @{ - */ - -#include "wifi_conf.h" - -#ifdef __cplusplus - extern "C" { -#endif - -typedef void (*rtw_event_handler_t)(char *buf, int buf_len, int flags, void* handler_user_data ); - -typedef struct -{ -// rtw_event_indicate_t event_cmd; - rtw_event_handler_t handler; - void* handler_user_data; -} event_list_elem_t; - -/** - * @brief Initialize the event callback list. - * @warning Please make sure this function has been invoked before - * using the event handler related mechanism. - * @param None - * @return None - */ -void init_event_callback_list(void); - -/** - * @brief Wlan driver indicate event to upper layer through wifi_indication. - * @param[in] event: An event reported from driver to upper layer application. Please refer to rtw_event_indicate_t enum. - * @param[in] buf: If it is not NUL, buf is a pointer to the buffer for message string. - * @param[in] buf_len: The length of the buffer. - * @param[in] flags: Indicate some extra information, sometimes it is 0. - * @retval None - * @note If upper layer application triggers additional operations on receiving of wext_wlan_indicate, - * please strictly check current stack size usage (by using uxTaskGetStackHighWaterMark() ), - * and tries not to share the same stack with wlan driver if remaining stack space is not available - * for the following operations. - * ex: using semaphore to notice another thread instead of handing event directly in wifi_indication(). - */ -extern void wifi_indication( rtw_event_indicate_t event, char *buf, int buf_len, int flags); - -/** - * @brief Register the event listener. - * @param[in] event_cmds : The event command number indicated. - * @param[in] handler_func : the callback function which will - * receive and process the event. - * @param[in] handler_user_data : user specific data that will be - * passed directly to the callback function. - * @return RTW_SUCCESS : if successfully registers the event. - * @return RTW_ERROR : if an error occurred. - * @note Set the same event_cmds with empty handler_func will - * unregister the event_cmds. - */ -extern void wifi_reg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func, void *handler_user_data); - -/** - * @brief Un-register the event listener. - * @param[in] event_cmds : The event command number indicated. - * @param[in] handler_func : the callback function which will - * receive and process the event. - * - * @return RTW_SUCCESS : if successfully un-registers the event . - * @return RTW_ERROR : if an error occurred. - */ -extern void wifi_unreg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func); - -#ifdef __cplusplus - } -#endif - -/*\@}*/ - -#endif //_WIFI_INDICATE_H - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_util.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_util.h deleted file mode 100644 index 2a1e8da67bf..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_util.h +++ /dev/null @@ -1,94 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ -#ifndef _UTIL_H -#define _UTIL_H - -#include -#include -#include -#include "wifi_structures.h" - -#ifdef __cplusplus -extern "C" { -#endif - -int wext_get_ssid(const char *ifname, __u8 *ssid); -int wext_set_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len); -int wext_set_bssid(const char *ifname, const __u8 *bssid); -int wext_get_bssid(const char *ifname, __u8 *bssid); -int wext_set_auth_param(const char *ifname, __u16 idx, __u32 value); -int wext_set_key_ext(const char *ifname, __u16 alg, const __u8 *addr, int key_idx, int set_tx, const __u8 *seq, __u16 seq_len, __u8 *key, __u16 key_len); -int wext_get_enc_ext(const char *ifname, __u16 *alg, __u8 *key_idx, __u8 *passphrase); -int wext_set_passphrase(const char *ifname, const __u8 *passphrase, __u16 passphrase_len); -int wext_get_passphrase(const char *ifname, __u8 *passphrase); -int wext_set_mode(const char *ifname, int mode); -int wext_get_mode(const char *ifname, int *mode); -int wext_set_ap_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len); -int wext_set_country(const char *ifname, rtw_country_code_t country_code); -int wext_get_rssi(const char *ifname, int *rssi); -int wext_set_channel(const char *ifname, __u8 ch); -int wext_get_channel(const char *ifname, __u8 *ch); -int wext_register_multicast_address(const char *ifname, rtw_mac_t *mac); -int wext_unregister_multicast_address(const char *ifname, rtw_mac_t *mac); -int wext_set_scan(const char *ifname, char *buf, __u16 buf_len, __u16 flags); -int wext_get_scan(const char *ifname, char *buf, __u16 buf_len); -int wext_set_mac_address(const char *ifname, char * mac); -int wext_get_mac_address(const char *ifname, char * mac); -int wext_enable_powersave(const char *ifname, __u8 lps_mode, __u8 ips_mode); -int wext_disable_powersave(const char *ifname); -int wext_set_tdma_param(const char *ifname, __u8 slot_period, __u8 rfon_period_len_1, __u8 rfon_period_len_2, __u8 rfon_period_len_3); -int wext_set_lps_dtim(const char *ifname, __u8 lps_dtim); -int wext_get_lps_dtim(const char *ifname, __u8 *lps_dtim); -int wext_get_tx_power(const char *ifname, __u8 *poweridx); -int wext_set_txpower(const char *ifname, int poweridx); -int wext_get_associated_client_list(const char *ifname, void * client_list_buffer, __u16 buffer_length); -int wext_get_ap_info(const char *ifname, rtw_bss_info_t * ap_info, rtw_security_t* security); -int wext_mp_command(const char *ifname, char *cmd, int show_msg); -int wext_private_command(const char *ifname, char *cmd, int show_msg); -int wext_private_command_with_retval(const char *ifname, char *cmd, char *ret_buf, int ret_len); -void wext_wlan_indicate(unsigned int cmd, union iwreq_data *wrqu, char *extra); -int wext_set_pscan_channel(const char *ifname, __u8 *ch, __u8 *pscan_config, __u8 length); -int wext_set_autoreconnect(const char *ifname, __u8 mode, __u8 retry_times, __u16 timeout); -int wext_get_autoreconnect(const char *ifname, __u8 *mode); -int wext_set_adaptivity(rtw_adaptivity_mode_t adaptivity_mode); -int wext_set_adaptivity_th_l2h_ini(__u8 l2h_threshold); -int wext_get_auto_chl(const char *ifname, unsigned char *channel_set, unsigned char channel_num); -int wext_set_sta_num(unsigned char ap_sta_num); -int wext_del_station(const char *ifname, unsigned char* hwaddr); -int wext_init_mac_filter(void); -int wext_deinit_mac_filter(void); -int wext_add_mac_filter(unsigned char* hwaddr); -int wext_del_mac_filter(unsigned char* hwaddr); -void wext_set_indicate_mgnt(int enable); -#ifdef CONFIG_CUSTOM_IE -int wext_add_custom_ie(const char *ifname, void * cus_ie, int ie_num); -int wext_update_custom_ie(const char *ifname, void * cus_ie, int ie_index); -int wext_del_custom_ie(const char *ifname); -#endif - -#define wext_handshake_done rltk_wlan_handshake_done - -int wext_send_mgnt(const char *ifname, char *buf, __u16 buf_len, __u16 flags); -int wext_send_eapol(const char *ifname, char *buf, __u16 buf_len, __u16 flags); -int wext_set_gen_ie(const char *ifname, char *buf, __u16 buf_len, __u16 flags); - -#ifdef __cplusplus -} -#endif - -#endif /* _UTIL_H */ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/autoconf.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/autoconf.h deleted file mode 100644 index ddfed02ebe0..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/autoconf.h +++ /dev/null @@ -1,702 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ - -#ifndef WLANCONFIG_H -#define WLANCONFIG_H - -/* - * Include user defined options first. Anything not defined in these files - * will be set to standard values. Override anything you dont like! - */ -#include "platform_opts.h" - -#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) || defined(CONFIG_PLATFORM_8721D) || defined(CONFIG_PLATFORM_8195BHP) -#ifndef CONFIG_PLATFORM_AMEBA_X -#define CONFIG_PLATFORM_AMEBA_X 1 -#endif -#else -#define CONFIG_PLATFORM_AMEBA_X 0 -#endif - -#if (CONFIG_PLATFORM_AMEBA_X == 1) - #if defined(CONFIG_PLATFORM_8195BHP) - #define CONFIG_AXI_HCI - #else - #define CONFIG_LX_HCI - #endif -#else - #define PLATFORM_FREERTOS 1 - #ifdef USE_SDIO_INTERFACE - #define CONFIG_SDIO_HCI - #else - #define CONFIG_GSPI_HCI -#endif -#endif // #if (CONFIG_PLATFORM_AMEBA_X == 1) - -#if defined(CONFIG_HARDWARE_8188F) || defined(CONFIG_HARDWARE_8192E)|| defined(CONFIG_HARDWARE_8723D) || defined(CONFIG_HARDWARE_8821C) || defined(CONFIG_PLATFORM_8195BHP) || defined(CONFIG_HARDWARE_8188E) || defined(CONFIG_PLATFORM_8721D) -#define CONFIG_FW_C2H_PKT -#define PHYDM_LINUX_CODING_STYLE 1 -#else -#define PHYDM_LINUX_CODING_STYLE 0 -#endif - -#if (PHYDM_LINUX_CODING_STYLE == 1) -#define PHYDM_NEW_INTERFACE 1 -#else -#define PHYDM_NEW_INTERFACE 0 -#endif - -#ifndef CONFIG_INIC_EN -#define CONFIG_INIC_EN 0 //For iNIC project -#endif - -#if CONFIG_INIC_EN -#define CONFIG_LWIP_LAYER 0 -#endif - -#define CONFIG_LITTLE_ENDIAN -#define CONFIG_80211N_HT -//#define CONFIG_RECV_REORDERING_CTRL -#define RTW_NOTCH_FILTER 0 -#define CONFIG_EMBEDDED_FWIMG -#define CONFIG_PHY_SETTING_WITH_ODM -#if (CONFIG_PLATFORM_AMEBA_X == 0) -#define CONFIG_ODM_REFRESH_RAMASK -#define HAL_MAC_ENABLE 1 -#define HAL_BB_ENABLE 1 -#define HAL_RF_ENABLE 1 -#endif -#if (CONFIG_PLATFORM_AMEBA_X == 1) -/* Patch when dynamic mechanism is not ready */ -//#define CONFIG_DM_PATCH -#endif - -//#define CONFIG_DEBUG -//#define CONFIG_DEBUG_RTL871X -#if (CONFIG_PLATFORM_AMEBA_X == 1) - #define CONFIG_MEM_MONITOR MEM_MONITOR_SIMPLE - #define WLAN_INTF_DBG 0 - //#define CONFIG_DEBUG_DYNAMIC - //#define DBG_TX 1 - //#define DBG_XMIT_BUF 1 - //#define DBG_XMIT_BUF_EXT 1 - #define DBG_TX_DROP_FRAME -#else - #define CONFIG_MEM_MONITOR MEM_MONITOR_LEAK - //#define CONFIG_TRACE_SKB - //#define WLAN_INTF_DBG -#endif // CONFIG_PLATFORM_AMEBA_X - -//#define CONFIG_DONT_CARE_TP -//#define CONFIG_HIGH_TP -//#define CONFIG_MEMORY_ACCESS_ALIGNED -#define CONFIG_POWER_SAVING -#ifdef CONFIG_POWER_SAVING - #define CONFIG_IPS - #define CONFIG_LPS - //#define CONFIG_LPS_LCLK -#if (CONFIG_PLATFORM_AMEBA_X == 0) -#ifdef CONFIG_LPS_LCLK - #define CONFIG_DETECT_CPWM_BY_POLLING - #define LPS_RPWM_WAIT_MS 300 -#endif -#else - #define CONFIG_LPS_32K - #define TDMA_POWER_SAVING -#endif - #define CONFIG_WAIT_PS_ACK -#endif - -#define BAD_MIC_COUNTERMEASURE 1 -#define DEFRAGMENTATION 1 - -#define WIFI_LOGO_CERTIFICATION 0 -#if WIFI_LOGO_CERTIFICATION - #define RX_AGGREGATION 1 - #define RX_AMSDU 1 -#else - #define RX_AGGREGATION 0 - #define RX_AMSDU 0 -#endif - -#if defined(CONFIG_PLATFORM_8711B) - #define CONFIG_FW_C2H_PKT -#endif - -#if (CONFIG_PLATFORM_AMEBA_X == 1) - #if defined(CONFIG_PLATFORM_8195A) - #define CONFIG_USE_TCM_HEAP 1 /* USE TCM HEAP */ - #endif - #define CONFIG_RECV_TASKLET_THREAD - #define CONFIG_XMIT_TASKLET_THREAD -#else - #define CONFIG_XMIT_THREAD_MODE -#endif // CONFIG_PLATFORM_AMEBA_X -//#define CONFIG_RECV_THREAD_MODE /* Wlan IRQ Polling Mode*/ -//#define CONFIG_ISR_THREAD_MODE_POLLING /* Wlan IRQ Polling Mode*/ - -//1 Chris -#ifndef CONFIG_SDIO_HCI -#define CONFIG_ISR_THREAD_MODE_INTERRUPT /* Wlan IRQ Interrupt Mode*/ -#endif - -#if defined(CONFIG_ISR_THREAD_MODE_POLLING) && defined(CONFIG_ISR_THREAD_MODE_INTERRUPT) -#error "CONFIG_ISR_THREAD_MODE_POLLING and CONFIG_ISR_THREAD_MODE_INTERRUPT are mutually exclusive. " -#endif - -#if (CONFIG_PLATFORM_AMEBA_X == 1) -/* CRC DMEM optimized mode consume 1k less SRM memory consumption */ -#define CRC_IMPLEMENTATION_MODE CRC_IMPLEMENTATION_DMEM_OPTIMIZED -#endif - -/* AES DMEM optimized mode comsume 10k less memory compare to - IMEM optimized mode AES_IMPLEMENTATION_IMEM_OPTIMIZED */ -#define AES_IMPLEMENTATION_MODE AES_IMPLEMENTATION_DMEM_OPTIMIZED - -#define USE_SKB_AS_XMITBUF 1 -#if (CONFIG_PLATFORM_AMEBA_X == 1) -#define USE_XMIT_EXTBUFF 1 -#else -#define USE_XMIT_EXTBUFF 0 -#endif -#define USE_MUTEX_FOR_SPINLOCK 1 - -// remove function to reduce code -#define NOT_SUPPORT_5G -#define NOT_SUPPORT_RF_MULTIPATH -#define NOT_SUPPORT_VHT -#define NOT_SUPPORT_40M -#define NOT_SUPPORT_80M -#if defined(CONFIG_PLATFORM_8195A) -#define NOT_SUPPORT_BBSWING -#endif -#define NOT_SUPPORT_OLD_CHANNEL_PLAN -#define NOT_SUPPORT_BT - -#define CONFIG_WIFI_SPEC 0 -#define CONFIG_FAKE_EFUSE 0 -#if CONFIG_FAKE_EFUSE - #define FAKE_CHIPID CHIPID_8710BN -#endif - -#define CONFIG_AUTO_RECONNECT 1 -#define ENABLE_HWPDN_PIN -#define SUPPORT_SCAN_BUF 1 -#if (CONFIG_PLATFORM_AMEBA_X == 0) -#define BE_I_CUT 1 -#endif - -/* For WPA2 */ -#define CONFIG_INCLUDE_WPA_PSK -#ifdef CONFIG_INCLUDE_WPA_PSK -#define CONFIG_MULTIPLE_WPA_STA -//#define CONFIG_WPA2_PREAUTH -#define PSK_SUPPORT_TKIP 1 -#endif - -/* For promiscuous mode */ -#define CONFIG_PROMISC - -#define PROMISC_DENY_PAIRWISE 0 - -/* For Simple Link */ -#ifndef CONFIG_INCLUDE_SIMPLE_CONFIG -//#define CONFIG_INCLUDE_SIMPLE_CONFIG 1 -#endif - -// for probe request with custom vendor specific IE -#define CONFIG_CUSTOM_IE - -#if (CONFIG_PLATFORM_AMEBA_X == 0) -/* For multicast */ -#define CONFIG_MULTICAST -#endif - -/* For STA+AP Concurrent MODE */ -#define CONFIG_CONCURRENT_MODE -#ifdef CONFIG_CONCURRENT_MODE - #if defined(CONFIG_PLATFORM_8195A) - #define CONFIG_RUNTIME_PORT_SWITCH - #endif - #define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN) + 1) -#else - #define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN)) -#endif - -/****************** For EAP auth configurations *******************/ -#define CONFIG_TLS 0 -#define CONFIG_PEAP 0 -#define CONFIG_TTLS 0 - -// DO NOT change the below config of EAP -#ifdef PRE_CONFIG_EAP -#undef CONFIG_TLS -#define CONFIG_TLS 1 -#undef CONFIG_PEAP -#define CONFIG_PEAP 1 -#undef CONFIG_TTLS -#define CONFIG_TTLS 1 -#endif - -// enable 1X code in lib_wlan as default (increase 380 bytes) -#define CONFIG_EAP - -#if CONFIG_TLS || CONFIG_PEAP || CONFIG_TTLS -#define EAP_REMOVE_UNUSED_CODE 1 -#endif - -#define EAP_SSL_VERIFY_SERVER - -#if CONFIG_TLS -#define EAP_SSL_VERIFY_CLIENT -#endif - -#if CONFIG_TTLS -#define EAP_MSCHAPv2 -#define EAP_TTLS_MSCHAPv2 -//#define EAP_TTLS_EAP -//#define EAP_TTLS_MSCHAP -//#define EAP_TTLS_PAP -//#define EAP_TTLS_CHAP -#endif -/****************** End of EAP configurations *******************/ - -/* For WPS and P2P */ -#define CONFIG_WPS -#if 0 -#define CONFIG_WPS_AP -#define CONFIG_P2P_NEW -#if (!defined(SUPPORT_SCAN_BUF)||!defined(CONFIG_WPS_AP)) && defined(CONFIG_P2P_NEW) -#error "If CONFIG_P2P_NEW, need to SUPPORT_SCAN_BUF" -#endif -#endif - -#define CONFIG_NEW_SIGNAL_STAT_PROCESS -#define CONFIG_SKIP_SIGNAL_SCALE_MAPPING - -/* For AP_MODE */ -#define CONFIG_AP_MODE -extern unsigned char g_user_ap_sta_num; -#define USER_AP_STA_NUM g_user_ap_sta_num -#if (CONFIG_PLATFORM_AMEBA_X == 1) -#define AP_STA_NUM 3 //2014/10/27 modify to 3 -#define USE_DEDICATED_BCN_TX 0 -#if USE_DEDICATED_BCN_TX -#error "WLAN driver for Ameba should not enable USE_DEDICATED_BCN_TX" -#endif -#else -extern unsigned int g_ap_sta_num; -#define AP_STA_NUM 3//g_ap_sta_num -#endif -#ifdef CONFIG_AP_MODE -#if defined(CONFIG_PLATFORM_8195A) - //softap sent qos null0 polling client alive or not - #define CONFIG_AP_POLLING_CLIENT_ALIVE -#endif - #define CONFIG_NATIVEAP_MLME -#if (CONFIG_PLATFORM_AMEBA_X == 1) - #define CONFIG_INTERRUPT_BASED_TXBCN -#endif - #ifdef CONFIG_INTERRUPT_BASED_TXBCN - //#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT - #define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR - #endif -// #define CONFIG_GK_REKEY -#if (CONFIG_PLATFORM_AMEBA_X == 0) - #define USE_DEDICATED_BCN_TX 1 -#endif -#if CONFIG_INIC_EN -// #define REPORT_STA_EVENT //useless -#endif -#else -#if (CONFIG_PLATFORM_AMEBA_X == 0) - #define USE_DEDICATED_BCN_TX 0 -#endif -#endif - -#if defined(CONFIG_AP_MODE) && defined(CONFIG_GK_REKEY) && !defined(CONFIG_MULTIPLE_WPA_STA) -#error "If CONFIG_GK_REKEY when CONFIG_AP_MODE, need to CONFIG_MULTIPLE_WPA_STA" -#endif - -#if (CONFIG_PLATFORM_AMEBA_X == 0) -#if !defined(CONFIG_AP_MODE) && defined(CONFIG_CONCURRENT_MODE) -#error "If CONFIG_CONCURRENT_MODEE, need to CONFIG_AP_MODE" -#endif -#endif - -/* For efuse or flash config */ -#if (CONFIG_PLATFORM_AMEBA_X == 1) - #define CONFIG_RW_PHYSICAL_EFUSE 0 // Mask efuse user blocks - #define CONFIG_HIDE_PROTECT_EFUSE 1 - #define CONFIG_ADAPTOR_INFO_CACHING_FLASH 1 - #define CHECK_FLASH_VALID_MASK 1 - #define CHECK_EFUSE_VALID_MASK 1 - /* For K-free */ -// #if !defined(CONFIG_PLATFORM_8711B) - #define CONFIG_RF_GAIN_OFFSET -// #endif -#endif // CONFIG_PLATFORM_AMEBA_X - -/* For MP_MODE */ -//#define CONFIG_MP_INCLUDED -#ifdef CONFIG_MP_INCLUDED - #define MP_DRIVER 1 - #define CONFIG_MP_IWPRIV_SUPPORT -// #define HAL_EFUSE_MEMORY - #if (CONFIG_PLATFORM_AMEBA_X == 1) - #define MP_REG_TEST - #endif -#else - #define MP_DRIVER 0 - #if defined(CONFIG_PLATFORM_8195A) - //Control wifi mcu function - #define CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD - #define CONFIG_ODM_REFRESH_RAMASK - //#define CONFIG_ANTENNA_DIVERSITY - //#define CONFIG_BT_COEXIST - #endif -#endif // #ifdef CONFIG_MP_INCLUDED - -#ifdef CONFIG_BT_COEXIST - #undef NOT_SUPPORT_BT - #define CONFIG_BT_MAILBOX - #define CONFIG_BT_EFUSE - //#define CONFIG_BT_TWO_ANTENNA -#endif - -#if (CONFIG_PLATFORM_AMEBA_X == 1) - #if defined(CONFIG_PLATFORM_8195A) - #undef CONFIG_RTL8195A - #define CONFIG_RTL8195A - #endif - #if defined(CONFIG_PLATFORM_8711B) - #ifndef CONFIG_RTL8711B - #define CONFIG_RTL8711B - #endif - #undef CONFIG_ADAPTOR_INFO_CACHING_FLASH - #define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0 - //#undef CONFIG_EAP - //#undef CONFIG_IPS - #define CONFIG_8710B_MOVE_TO_ROM - #define CONFIG_EFUSE_SEPARATE - #define CONFIG_MOVE_PSK_TO_ROM - #define CONFIG_WOWLAN - #define CONFIG_TRAFFIC_PROTECT - #define CONFIG_FABVERSION_UMC 1 - #if (CONFIG_INIC_EN == 1) - #undef CONFIG_PROMISC - #undef CONFIG_WPS - #undef CONFIG_AP_MODE - #undef CONFIG_NATIVEAP_MLME - #undef CONFIG_INTERRUPT_BASED_TXBCN - #undef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR - #undef USE_DEDICATED_BCN_TX - //#undef SUPPORT_SCAN_BUF - #undef CONFIG_CONCURRENT_MODE - #undef CONFIG_AUTO_RECONNECT - #endif - #endif - #if defined(CONFIG_PLATFORM_8721D) - #ifndef CONFIG_RTL8721D - #define CONFIG_RTL8721D - #endif - #undef NOT_SUPPORT_5G - #undef CONFIG_ADAPTOR_INFO_CACHING_FLASH - #define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0 - #define CONFIG_EFUSE_SEPARATE - #define CONFIG_WOWLAN - #define CONFIG_TRAFFIC_PROTECT - #define SUPPORT_5G_CHANNEL 1 - #define DBG_DM_DIG 0 // DebugComponents: bit0 - //#define CONFIG_SUPPORT_DYNAMIC_TXPWR //rtw_phydm_fill_desc_dpt todo - #if (CONFIG_INIC_EN == 1) - #undef CONFIG_PROMISC - #undef CONFIG_WPS - #undef CONFIG_AP_MODE - #undef CONFIG_NATIVEAP_MLME - #undef CONFIG_INTERRUPT_BASED_TXBCN - #undef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR - #undef USE_DEDICATED_BCN_TX - //#undef SUPPORT_SCAN_BUF - #undef CONFIG_CONCURRENT_MODE - #undef CONFIG_AUTO_RECONNECT - #endif - #endif - #if defined(CONFIG_PLATFORM_8195BHP) - #define CONFIG_RTL8195B - #undef CONFIG_EAP -// #undef CONFIG_ADAPTOR_INFO_CACHING_FLASH -// #define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0 - #undef CHECK_FLASH_VALID_MASK - #define CHECK_FLASH_VALID_MASK 0 - #undef CHECK_EFUSE_VALID_MASK - #define CHECK_EFUSE_VALID_MASK 0 - #undef CONFIG_RW_PHYSICAL_EFUSE - #define CONFIG_RW_PHYSICAL_EFUSE 1 // efuse_get realraw - #undef NOT_SUPPORT_5G - #undef NOT_SUPPORT_VHT - #undef NOT_SUPPORT_40M - #undef NOT_SUPPORT_80M - #define CONFIG_BW_80 - #define CONFIG_80211AC_VHT - #undef CONFIG_IPS -// #define CONFIG_NO_FW - #define CONFIG_EX_FW_BIN - #define LOAD_FW_HEADER_FROM_DRIVER -// #define RTW_IQK_FW_OFFLOAD - #define CONFIG_PHY_CAPABILITY_QUERY - #define CONFIG_FW_C2H_PKT - #define RTK_AC_SUPPORT - #define PHYDM_NEW_INTERFACE 1 - #define CONFIG_ISR_THREAD_MODE_INTERRUPT /* Wlan IRQ Interrupt Mode*/ -// #define CONFIG_WLAN_RF_CNTL - #define SUPPORT_5G_CHANNEL 1 - #define SUPPORTABLITY_PHYDMLIZE 1 - #define CONFIG_DFS - #ifdef CONFIG_DFS - #define CONFIG_DFS_ACTION - #endif - #undef CONFIG_RF_GAIN_OFFSET - - #define DBG_DM_DIG 0 // DebugComponents: bit0 -// #define CONFIG_DEBUG - - #define RTW_HALMAC /* Use HALMAC architecture */ - #define RTW_HALMAC_MU_BF 0 - #define RTW_HALMAC_SU_BF 0 - #define RTW_HALMAC_BT_COEX 0 - #define RTW_HALMAC_DUMP_INFO 0 - #define RTW_HALMAC_TXBF 0 - #define RTW_HALMAC_FW_OFFLOAD 0 - #define RTW_HALMAC_PHYSICAL_EFUSE 0 - #define RTW_HALMAC_SIZE_OPTIMIZATION 1 - #define RTW_HALMAC_SDIO_CIA_READ 0 - #define RTW_HALMAC_LTE_COEX 0 - - #define CONFIG_MAC_LOOPBACK_DRIVER_RTL8195B 0 - #endif -#elif defined(CONFIG_HARDWARE_8188F) -#define CONFIG_RTL8188F -#elif defined(CONFIG_HARDWARE_8192E) -#define CONFIG_RTL8192E -#elif defined(CONFIG_HARDWARE_8821C) -#define CONFIG_RTL8821C -#elif defined(CONFIG_HARDWARE_8723D) -#define CONFIG_RTL8723D -#elif defined(CONFIG_HARDWARE_8188E) -#define CONFIG_RTL8188E -#else -#define CONFIG_RTL8188E -#endif -#define RTL8192C_SUPPORT 0 -#define RTL8192CE_SUPPORT 0 -#define RTL8192CU_SUPPORT 0 -#define RTL8192D_SUPPORT 0 -#define RTL8192DE_SUPPORT 0 -#define RTL8192DU_SUPPORT 0 -#define RTL8723A_SUPPORT 0 -#define RTL8723AU_SUPPORT 0 -#define RTL8723AS_SUPPORT 0 -#define RTL8192E_SUPPORT 0 -#define RTL8812A_SUPPORT 0 -#define RTL8821A_SUPPORT 0 -#define RTL8723B_SUPPORT 0 -#define RTL8195A_SUPPORT 0 -#define RTL8188E_SUPPORT 0 -#define RTL8188F_SUPPORT 0 -#define RTL8711B_SUPPORT 0 -#define RTL8721D_SUPPORT 0 -#define RTL8821C_SUPPORT 0 -#define RTL8723D_SUPPORT 0 -#if defined(CONFIG_PLATFORM_8195A) -#undef RTL8195A_SUPPORT -#define RTL8195A_SUPPORT 1 -#elif defined(CONFIG_PLATFORM_8711B) -#undef RTL8711B_SUPPORT -#define RTL8711B_SUPPORT 1 -#elif defined(CONFIG_PLATFORM_8721D) -#undef RTL8721D_SUPPORT -#define RTL8721D_SUPPORT 1 -#elif defined(CONFIG_PLATFORM_8195BHP) -#undef RTL8195B_SUPPORT -#define RTL8195B_SUPPORT 1 -#elif defined(CONFIG_HARDWARE_8188F) -#undef RTL8188F_SUPPORT -#define RTL8188F_SUPPORT 1 -#elif defined(CONFIG_HARDWARE_8192E) -#undef RTL8192E_SUPPORT -#define RTL8192E_SUPPORT 1 -#elif defined(CONFIG_HARDWARE_8821C) -#undef RTL8821C_SUPPORT -#define RTL8821C_SUPPORT 1 -#elif defined(CONFIG_HARDWARE_8723D) -#undef RTL8723D_SUPPORT -#define RTL8723D_SUPPORT 1 -#elif defined(CONFIG_HARDWARE_8188E) -#undef RTL8188E_SUPPORT -#define RTL8188E_SUPPORT 1 -#else -#undef RTL8188E_SUPPORT -#define RTL8188E_SUPPORT 1 -#endif - -// for Debug message -#define DBG 0 -#if (CONFIG_PLATFORM_AMEBA_X == 1) -#if(DBG == 0) - #define ROM_E_RTW_MSG 1 - #define ROM_F_RTW_MSG 1 -#if (CONFIG_INIC_EN == 0) && (PHYDM_LINUX_CODING_STYLE == 0) - /* For DM debug*/ - // BB - #define DBG_RX_INFO 1 - #define DBG_DM_DIG 1 // DebugComponents: bit0 - #define DBG_DM_RA_MASK 1 // DebugComponents: bit1 - #define DBG_DM_ANT_DIV 1 // DebugComponents: bit6 - #define DBG_TX_RATE 1 // DebugComponents: bit9 - #define DBG_DM_RA 1 // DebugComponents: bit9 - #define DBG_DM_ADAPTIVITY 1 // DebugComponents: bit17 - // RF - #define DBG_PWR_TRACKING 1 // DebugComponents: bit24 - #define DBG_RF_IQK 1 // DebugComponents: bit26 - // Common - #define DBG_PWR_INDEX 1 // DebugComponents: bit30 -#endif -#endif -#endif - -/* For DM support */ -#if defined(CONFIG_RTL8188F) -#define RATE_ADAPTIVE_SUPPORT 0 -#elif defined(CONFIG_RTL8821C) -#define RATE_ADAPTIVE_SUPPORT 0 -#elif defined(CONFIG_RTL8192E) -#define RATE_ADAPTIVE_SUPPORT 0 -#elif defined(CONFIG_RTL8723D) -#define RATE_ADAPTIVE_SUPPORT 0 -#elif defined(CONFIG_PLATFORM_8711B) -#define RATE_ADAPTIVE_SUPPORT 0 -#define CONFIG_ODM_REFRESH_RAMASK -#elif defined(CONFIG_PLATFORM_8721D) -#define RATE_ADAPTIVE_SUPPORT 0 -//#define CONFIG_ODM_REFRESH_RAMASK -#else -#define RATE_ADAPTIVE_SUPPORT 1 -#endif -// adaptivity -#define RTW_ADAPTIVITY_EN_DISABLE 0 -#define RTW_ADAPTIVITY_EN_ENABLE 1 -#define CONFIG_RTW_ADAPTIVITY_EN RTW_ADAPTIVITY_EN_DISABLE -#define RTW_ADAPTIVITY_MODE_NORMAL 0 -#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1 -#define CONFIG_RTW_ADAPTIVITY_MODE RTW_ADAPTIVITY_MODE_CARRIER_SENSE -#define CONFIG_RTW_ADAPTIVITY_DML 0 - - -#if (CONFIG_PLATFORM_AMEBA_X == 1) - #define CONFIG_POWER_TRAINING_WIL 0 // in RA -#else - #define POWER_BY_RATE_SUPPORT 0 -#endif - -#if (CONFIG_PLATFORM_AMEBA_X == 1) -#define RTL8195A_FOR_TEST_CHIP 0 - -//#define CONFIG_WIFI_TEST 1 -//#define CONFIG_MAC_LOOPBACK_DRIVER 1 -//#define CONFIG_WLAN_HAL_TEST 1 -//#define SKB_PRE_ALLOCATE_TX 1 -#define SKB_PRE_ALLOCATE_RX 0 -#define TX_CHECK_DSEC_ALWAYS 1 -#define CONFIG_DBG_DISABLE_RDU_INTERRUPT -//#define CONFIG_WLAN_HAL_RX_TASK -#if (SKB_PRE_ALLOCATE_RX == 1) - #define EXCHANGE_LXBUS_RX_SKB 0 -#endif -#ifdef CONFIG_FPGA - //Enable mac loopback for test mode (Ameba) - #ifdef CONFIG_WIFI_NORMAL - #define CONFIG_TWO_MAC_DRIVER // for test mode - #else //CONFIG_WIFI_VERIFY - #define ENABLE_MAC_LB_FOR_TEST_MODE - #endif - - #define AP_PSK_SUPPORT_TKIP -#endif - -#ifdef ENABLE_MAC_LB_FOR_TEST_MODE - #define CONFIG_SUDO_PHY_SETTING - #define INT_HANDLE_IN_ISR 1 - #define CONFIG_LWIP_LAYER 0 - #define CONFIG_WLAN_HAL_TEST - #define CONFIG_WLAN_HAL_RX_TASK - #define CONFIG_MAC_LOOPBACK_DRIVER_AMEBA 1 - #define HAL_MAC_ENABLE 1 - #define CONFIG_TWO_MAC_TEST_MODE - #define DISABLE_BB_RF 1 -#else - //#define CONFIG_TWO_MAC_DRIVER //for mornal driver; two mac - #ifdef CONFIG_TWO_MAC_DRIVER - #define CONFIG_SUDO_PHY_SETTING - #define HAL_MAC_ENABLE 1 - #define DISABLE_BB_RF 1 - #else - #define HAL_MAC_ENABLE 1 - #define HAL_BB_ENABLE 1 - #define HAL_RF_ENABLE 1 - #define DISABLE_BB_RF 0 - #endif - //#define INT_HANDLE_IN_ISR 1 -#endif -#endif // CONFIG_PLATFORM_AMEBA_X - -#ifndef CONFIG_LWIP_LAYER -#define CONFIG_LWIP_LAYER 1 -#endif -#define CONFIG_MAC_ADDRESS 0 -//fast reconnection -//#define CONFIG_FAST_RECONNECTION 1 -#if defined(CONFIG_INIC_EN)&&(CONFIG_INIC_EN==1) -#define CONFIG_RECV_REORDERING_CTRL //enable reordering for iNIC high throughput -#undef RX_AGGREGATION -#define RX_AGGREGATION 1 -#undef NOT_SUPPORT_40M -#undef CONFIG_CONCURRENT_MODE -#endif - -#if defined(CONFIG_HARDWARE_8821C) -#define FW_IQK -#define RTW_HALMAC -#define LOAD_FW_HEADER_FROM_DRIVER -#define RTW_HALMAC_SIZE_OPTIMIZATION 1 -//#define CONFIG_NO_FW -#ifdef NOT_SUPPORT_5G -#undef NOT_SUPPORT_5G -#define SUPPORT_5G_CHANNEL 1 -#endif -#endif - -#if defined(CONFIG_RTL8723D) -#define HAL_EFUSE_MEMORY -#endif - -#define CONFIG_DFS -//#define CONFIG_EMPTY_EFUSE_PG_ENABLE - -#define WLAN_WAPPER_VERSION 1 - -#endif //WLANCONFIG_H - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_constants.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_constants.h deleted file mode 100644 index a3416a1f3a6..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_constants.h +++ /dev/null @@ -1,572 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ****************************************************************************** - * @file wifi_constants.h - * @author - * @version - * @brief This file provides the data types used for wlan API. - ****************************************************************************** - */ - -#ifndef _WIFI_CONSTANTS_H -#define _WIFI_CONSTANTS_H - -/** @addtogroup nic NIC - * @ingroup wlan - * @brief NIC functions - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef WLAN0_NAME - #define WLAN0_NAME "wlan0" -#endif -#ifndef WLAN1_NAME - #define WLAN1_NAME "wlan1" -#endif - -#define WEP_ENABLED 0x0001 -#define TKIP_ENABLED 0x0002 -#define AES_ENABLED 0x0004 -#define WSEC_SWFLAG 0x0008 - -#define SHARED_ENABLED 0x00008000 -#define WPA_SECURITY 0x00200000 -#define WPA2_SECURITY 0x00400000 -#define WPS_ENABLED 0x10000000 - -#define RTW_MAX_PSK_LEN (64) -#define RTW_MIN_PSK_LEN (8) -#define MCSSET_LEN 16 - -/** - * @brief The enumeration lists the results of the function. - */ -enum -{ - RTW_SUCCESS = 0, /**< Success */ - RTW_PENDING = 1, /**< Pending */ - RTW_TIMEOUT = 2, /**< Timeout */ - RTW_PARTIAL_RESULTS = 3, /**< Partial results */ - RTW_INVALID_KEY = 4, /**< Invalid key */ - RTW_DOES_NOT_EXIST = 5, /**< Does not exist */ - RTW_NOT_AUTHENTICATED = 6, /**< Not authenticated */ - RTW_NOT_KEYED = 7, /**< Not keyed */ - RTW_IOCTL_FAIL = 8, /**< IOCTL fail */ - RTW_BUFFER_UNAVAILABLE_TEMPORARY = 9, /**< Buffer unavailable temporarily */ - RTW_BUFFER_UNAVAILABLE_PERMANENT = 10, /**< Buffer unavailable permanently */ - RTW_WPS_PBC_OVERLAP = 11, /**< WPS PBC overlap */ - RTW_CONNECTION_LOST = 12, /**< Connection lost */ - RTW_ERROR = -1, /**< Generic Error */ - RTW_BADARG = -2, /**< Bad Argument */ - RTW_BADOPTION = -3, /**< Bad option */ - RTW_NOTUP = -4, /**< Not up */ - RTW_NOTDOWN = -5, /**< Not down */ - RTW_NOTAP = -6, /**< Not AP */ - RTW_NOTSTA = -7, /**< Not STA */ - RTW_BADKEYIDX = -8, /**< BAD Key Index */ - RTW_RADIOOFF = -9, /**< Radio Off */ - RTW_NOTBANDLOCKED = -10, /**< Not band locked */ - RTW_NOCLK = -11, /**< No Clock */ - RTW_BADRATESET = -12, /**< BAD Rate valueset */ - RTW_BADBAND = -13, /**< BAD Band */ - RTW_BUFTOOSHORT = -14, /**< Buffer too short */ - RTW_BUFTOOLONG = -15, /**< Buffer too long */ - RTW_BUSY = -16, /**< Busy */ - RTW_NOTASSOCIATED = -17, /**< Not Associated */ - RTW_BADSSIDLEN = -18, /**< Bad SSID len */ - RTW_OUTOFRANGECHAN = -19, /**< Out of Range Channel */ - RTW_BADCHAN = -20, /**< Bad Channel */ - RTW_BADADDR = -21, /**< Bad Address */ - RTW_NORESOURCE = -22, /**< Not Enough Resources */ - RTW_UNSUPPORTED = -23, /**< Unsupported */ - RTW_BADLEN = -24, /**< Bad length */ - RTW_NOTREADY = -25, /**< Not Ready */ - RTW_EPERM = -26, /**< Not Permitted */ - RTW_NOMEM = -27, /**< No Memory */ - RTW_ASSOCIATED = -28, /**< Associated */ - RTW_RANGE = -29, /**< Not In Range */ - RTW_NOTFOUND = -30, /**< Not Found */ - RTW_WME_NOT_ENABLED = -31, /**< WME Not Enabled */ - RTW_TSPEC_NOTFOUND = -32, /**< TSPEC Not Found */ - RTW_ACM_NOTSUPPORTED = -33, /**< ACM Not Supported */ - RTW_NOT_WME_ASSOCIATION = -34, /**< Not WME Association */ - RTW_SDIO_ERROR = -35, /**< SDIO Bus Error */ - RTW_WLAN_DOWN = -36, /**< WLAN Not Accessible */ - RTW_BAD_VERSION = -37, /**< Incorrect version */ - RTW_TXFAIL = -38, /**< TX failure */ - RTW_RXFAIL = -39, /**< RX failure */ - RTW_NODEVICE = -40, /**< Device not present */ - RTW_UNFINISHED = -41, /**< To be finished */ - RTW_NONRESIDENT = -42, /**< access to nonresident overlay */ - RTW_DISABLED = -43 /**< Disabled in this build */ -}; -typedef unsigned long rtw_result_t; - -/** - * @brief The enumeration lists the possible security types to set when connection.\n - * Station mode supports OPEN, WEP, and WPA2.\n - * AP mode support OPEN and WPA2. - */ -enum { - RTW_SECURITY_OPEN = 0, /**< Open security */ - RTW_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP Security with open authentication */ - RTW_SECURITY_WEP_SHARED = ( WEP_ENABLED | SHARED_ENABLED ), /**< WEP Security with shared authentication */ - RTW_SECURITY_WPA_TKIP_PSK = ( WPA_SECURITY | TKIP_ENABLED ), /**< WPA Security with TKIP */ - RTW_SECURITY_WPA_AES_PSK = ( WPA_SECURITY | AES_ENABLED ), /**< WPA Security with AES */ - RTW_SECURITY_WPA2_AES_PSK = ( WPA2_SECURITY | AES_ENABLED ), /**< WPA2 Security with AES */ - RTW_SECURITY_WPA2_TKIP_PSK = ( WPA2_SECURITY | TKIP_ENABLED ), /**< WPA2 Security with TKIP */ - RTW_SECURITY_WPA2_MIXED_PSK = ( WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED ), /**< WPA2 Security with AES & TKIP */ - RTW_SECURITY_WPA_WPA2_MIXED = ( WPA_SECURITY | WPA2_SECURITY ), /**< WPA/WPA2 Security */ - RTW_SECURITY_WPS_OPEN = WPS_ENABLED, /**< WPS with open security */ - RTW_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */ - RTW_SECURITY_UNKNOWN = -1, /**< May be returned by scan function if security is unknown. Do not pass this to the join function! */ - RTW_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force rtw_security_t type to 32 bits */ -}; -typedef unsigned long rtw_security_t; - -enum { - RTW_ENCRYPTION_UNKNOWN = 0, - RTW_ENCRYPTION_OPEN = 1, - RTW_ENCRYPTION_WEP40 = 2, - RTW_ENCRYPTION_WPA_TKIP = 3, - RTW_ENCRYPTION_WPA_AES = 4, - RTW_ENCRYPTION_WPA2_TKIP = 5, - RTW_ENCRYPTION_WPA2_AES = 6, - RTW_ENCRYPTION_WPA2_MIXED = 7, - RTW_ENCRYPTION_WEP104 = 9, - RTW_ENCRYPTION_UNDEF = 0xFF, -}; -typedef unsigned long rtw_encryption_t; - -enum { - RTW_FALSE = 0, - RTW_TRUE = 1 -}; -typedef unsigned long rtw_bool_t; - -/** - * @brief The enumeration lists the band types. - */ -enum { - RTW_802_11_BAND_5GHZ = 0, /**< Denotes 5GHz radio band */ - RTW_802_11_BAND_2_4GHZ = 1 /**< Denotes 2.4GHz radio band */ -}; -typedef unsigned long rtw_802_11_band_t; - -/** - * @brief The enumeration lists all the country codes able to set to Wi-Fi driver. - */ -enum { - /* CHANNEL PLAN */ - RTW_COUNTRY_WORLD1, // 0x20 - RTW_COUNTRY_ETSI1, // 0x21 - RTW_COUNTRY_FCC1, // 0x22 - RTW_COUNTRY_MKK1, // 0x23 - RTW_COUNTRY_ETSI2, // 0x24 - RTW_COUNTRY_FCC2, // 0x2A - RTW_COUNTRY_WORLD2, // 0x47 - RTW_COUNTRY_MKK2, // 0x58 - RTW_COUNTRY_GLOBAL, // 0x41 - - /* SPECIAL */ - RTW_COUNTRY_WORLD, // WORLD1 - RTW_COUNTRY_EU, // ETSI1 - - /* JAPANESE */ - RTW_COUNTRY_JP, // MKK1 - - /* FCC , 19 countries*/ - RTW_COUNTRY_AS, // FCC2 - RTW_COUNTRY_BM, - RTW_COUNTRY_CA, - RTW_COUNTRY_DM, - RTW_COUNTRY_DO, - RTW_COUNTRY_FM, - RTW_COUNTRY_GD, - RTW_COUNTRY_GT, - RTW_COUNTRY_GU, - RTW_COUNTRY_HT, - RTW_COUNTRY_MH, - RTW_COUNTRY_MP, - RTW_COUNTRY_NI, - RTW_COUNTRY_PA, - RTW_COUNTRY_PR, - RTW_COUNTRY_PW, - RTW_COUNTRY_TW, - RTW_COUNTRY_US, - RTW_COUNTRY_VI, - - /* others, ETSI */ - RTW_COUNTRY_AD, // ETSI1 - RTW_COUNTRY_AE, - RTW_COUNTRY_AF, - RTW_COUNTRY_AI, - RTW_COUNTRY_AL, - RTW_COUNTRY_AM, - RTW_COUNTRY_AN, - RTW_COUNTRY_AR, - RTW_COUNTRY_AT, - RTW_COUNTRY_AU, - RTW_COUNTRY_AW, - RTW_COUNTRY_AZ, - RTW_COUNTRY_BA, - RTW_COUNTRY_BB, - RTW_COUNTRY_BD, - RTW_COUNTRY_BE, - RTW_COUNTRY_BF, - RTW_COUNTRY_BG, - RTW_COUNTRY_BH, - RTW_COUNTRY_BL, - RTW_COUNTRY_BN, - RTW_COUNTRY_BO, - RTW_COUNTRY_BR, - RTW_COUNTRY_BS, - RTW_COUNTRY_BT, - RTW_COUNTRY_BY, - RTW_COUNTRY_BZ, - RTW_COUNTRY_CF, - RTW_COUNTRY_CH, - RTW_COUNTRY_CI, - RTW_COUNTRY_CL, - RTW_COUNTRY_CN, - RTW_COUNTRY_CO, - RTW_COUNTRY_CR, - RTW_COUNTRY_CX, - RTW_COUNTRY_CY, - RTW_COUNTRY_CZ, - RTW_COUNTRY_DE, - RTW_COUNTRY_DK, - RTW_COUNTRY_DZ, - RTW_COUNTRY_EC, - RTW_COUNTRY_EE, - RTW_COUNTRY_EG, - RTW_COUNTRY_ES, - RTW_COUNTRY_ET, - RTW_COUNTRY_FI, - RTW_COUNTRY_FR, - RTW_COUNTRY_GB, - RTW_COUNTRY_GE, - RTW_COUNTRY_GF, - RTW_COUNTRY_GH, - RTW_COUNTRY_GL, - RTW_COUNTRY_GP, - RTW_COUNTRY_GR, - RTW_COUNTRY_GY, - RTW_COUNTRY_HK, - RTW_COUNTRY_HN, - RTW_COUNTRY_HR, - RTW_COUNTRY_HU, - RTW_COUNTRY_ID, - RTW_COUNTRY_IE, - RTW_COUNTRY_IL, - RTW_COUNTRY_IN, - RTW_COUNTRY_IQ, - RTW_COUNTRY_IR, - RTW_COUNTRY_IS, - RTW_COUNTRY_IT, - RTW_COUNTRY_JM, - RTW_COUNTRY_JO, - RTW_COUNTRY_KE, - RTW_COUNTRY_KH, - RTW_COUNTRY_KN, - RTW_COUNTRY_KP, - RTW_COUNTRY_KR, - RTW_COUNTRY_KW, - RTW_COUNTRY_KY, - RTW_COUNTRY_KZ, - RTW_COUNTRY_LA, - RTW_COUNTRY_LB, - RTW_COUNTRY_LC, - RTW_COUNTRY_LI, - RTW_COUNTRY_LK, - RTW_COUNTRY_LR, - RTW_COUNTRY_LS, - RTW_COUNTRY_LT, - RTW_COUNTRY_LU, - RTW_COUNTRY_LV, - RTW_COUNTRY_MA, - RTW_COUNTRY_MC, - RTW_COUNTRY_MD, - RTW_COUNTRY_ME, - RTW_COUNTRY_MF, - RTW_COUNTRY_MK, - RTW_COUNTRY_MN, - RTW_COUNTRY_MO, - RTW_COUNTRY_MQ, - RTW_COUNTRY_MR, - RTW_COUNTRY_MT, - RTW_COUNTRY_MU, - RTW_COUNTRY_MV, - RTW_COUNTRY_MW, - RTW_COUNTRY_MX, - RTW_COUNTRY_MY, - RTW_COUNTRY_NG, - RTW_COUNTRY_NL, - RTW_COUNTRY_NO, - RTW_COUNTRY_NP, - RTW_COUNTRY_NZ, - RTW_COUNTRY_OM, - RTW_COUNTRY_PE, - RTW_COUNTRY_PF, - RTW_COUNTRY_PG, - RTW_COUNTRY_PH, - RTW_COUNTRY_PK, - RTW_COUNTRY_PL, - RTW_COUNTRY_PM, - RTW_COUNTRY_PT, - RTW_COUNTRY_PY, - RTW_COUNTRY_QA, - RTW_COUNTRY_RS, - RTW_COUNTRY_RU, - RTW_COUNTRY_RW, - RTW_COUNTRY_SA, - RTW_COUNTRY_SE, - RTW_COUNTRY_SG, - RTW_COUNTRY_SI, - RTW_COUNTRY_SK, - RTW_COUNTRY_SN, - RTW_COUNTRY_SR, - RTW_COUNTRY_SV, - RTW_COUNTRY_SY, - RTW_COUNTRY_TC, - RTW_COUNTRY_TD, - RTW_COUNTRY_TG, - RTW_COUNTRY_TH, - RTW_COUNTRY_TN, - RTW_COUNTRY_TR, - RTW_COUNTRY_TT, - RTW_COUNTRY_TZ, - RTW_COUNTRY_UA, - RTW_COUNTRY_UG, - RTW_COUNTRY_UY, - RTW_COUNTRY_UZ, - RTW_COUNTRY_VC, - RTW_COUNTRY_VE, - RTW_COUNTRY_VN, - RTW_COUNTRY_VU, - RTW_COUNTRY_WF, - RTW_COUNTRY_WS, - RTW_COUNTRY_YE, - RTW_COUNTRY_YT, - RTW_COUNTRY_ZA, - RTW_COUNTRY_ZW, - RTW_COUNTRY_MAX -}; -typedef unsigned long rtw_country_code_t; - -/** - * @brief The enumeration lists the adaptivity types. - */ -enum { - RTW_ADAPTIVITY_DISABLE = 0, - RTW_ADAPTIVITY_NORMAL, // CE - RTW_ADAPTIVITY_CARRIER_SENSE // MKK -}; -typedef unsigned long rtw_adaptivity_mode_t; - -/** - * @brief The enumeration lists the supported operation mode by WIFI driver, - * including station and AP mode. - */ -enum { - RTW_MODE_NONE = 0, - RTW_MODE_STA, - RTW_MODE_AP, - RTW_MODE_STA_AP, - RTW_MODE_PROMISC, - RTW_MODE_P2P -}; -typedef unsigned long rtw_mode_t; - -enum { - RTW_SCAN_FULL = 0, - RTW_SCAN_SOCIAL, - RTW_SCAN_ONE -}; -typedef unsigned long rtw_scan_mode_t; - -/** - * @brief The enumeration lists the supported autoreconnect mode by WIFI driver. - */ -typedef enum{ - RTW_AUTORECONNECT_DISABLE, - RTW_AUTORECONNECT_FINITE, - RTW_AUTORECONNECT_INFINITE -} rtw_autoreconnect_mode_t; - -/** - * @brief The enumeration lists the status to describe the connection link. - */ -enum { - RTW_LINK_DISCONNECTED = 0, - RTW_LINK_CONNECTED -}; -typedef unsigned long rtw_link_status_t; - -/** - * @brief The enumeration lists the scan types. - */ -enum { - RTW_SCAN_TYPE_ACTIVE = 0x00, /**< Actively scan a network by sending 802.11 probe(s) */ - RTW_SCAN_TYPE_PASSIVE = 0x01, /**< Passively scan a network by listening for beacons from APs */ - RTW_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04 /**< Passively scan on channels not enabled by the country code */ -}; -typedef unsigned long rtw_scan_type_t; - -/** - * @brief The enumeration lists the bss types. - */ -enum { - RTW_BSS_TYPE_INFRASTRUCTURE = 0, /**< Denotes infrastructure network */ - RTW_BSS_TYPE_ADHOC = 1, /**< Denotes an 802.11 ad-hoc IBSS network */ - RTW_BSS_TYPE_ANY = 2, /**< Denotes either infrastructure or ad-hoc network */ - - RTW_BSS_TYPE_UNKNOWN = -1 /**< May be returned by scan function if BSS type is unknown. Do not pass this to the Join function */ -}; -typedef unsigned long rtw_bss_type_t; - -enum { - RTW_SCAN_COMMAMD = 0x01 -}; -typedef unsigned long rtw_scan_command_t; - -enum{ - COMMAND1 = 0x01 -}; -typedef unsigned long rtw_command_type; - -enum { - RTW_WPS_TYPE_DEFAULT = 0x0000, - RTW_WPS_TYPE_USER_SPECIFIED = 0x0001, - RTW_WPS_TYPE_MACHINE_SPECIFIED = 0x0002, - RTW_WPS_TYPE_REKEY = 0x0003, - RTW_WPS_TYPE_PUSHBUTTON = 0x0004, - RTW_WPS_TYPE_REGISTRAR_SPECIFIED = 0x0005, - RTW_WPS_TYPE_NONE = 0x0006, - RTW_WPS_TYPE_WSC = 0x0007 -}; -typedef unsigned long rtw_wps_type_t; - -/** - * @brief The enumeration lists all the network bgn mode. - */ -enum { - RTW_NETWORK_B = 1, - RTW_NETWORK_BG = 3, - RTW_NETWORK_BGN = 11 -}; -typedef unsigned long rtw_network_mode_t; - -/** - * @brief The enumeration lists the interfaces. - */ -enum { - RTW_STA_INTERFACE = 0, /**< STA or Client Interface */ - RTW_AP_INTERFACE = 1, /**< SoftAP Interface */ -}; -typedef unsigned long rtw_interface_t; - -/** - * @brief The enumeration lists the packet filter rules. - */ -enum { - RTW_POSITIVE_MATCHING = 0, /**< Receive the data matching with this pattern and discard the other data */ - RTW_NEGATIVE_MATCHING = 1 /**< Discard the data matching with this pattern and receive the other data */ -}; -typedef unsigned long rtw_packet_filter_rule_t; - -/** - * @brief The enumeration lists the promisc levels. - */ -enum { - RTW_PROMISC_DISABLE = 0, /**< Disable the promisc */ - RTW_PROMISC_ENABLE = 1, /**< Fetch all ethernet packets */ - RTW_PROMISC_ENABLE_1 = 2, /**< Fetch only B/M packets */ - RTW_PROMISC_ENABLE_2 = 3, /**< Fetch all 802.11 packets*/ - RTW_PROMISC_ENABLE_3 = 4, /**< Fetch only B/M 802.11 packets*/ - RTW_PROMISC_ENABLE_4 = 5, /**< Fetch all 802.11 packets & MIMO PLCP headers. Please note that the PLCP header would be struct rtw_rx_info_t defined in wifi_structures.h*/ -}; -typedef unsigned long rtw_rcr_level_t; - -/** - * @brief The enumeration lists the promisc rx type. - */ -#if CONFIG_UNSUPPORT_PLCPHDR_RPT -enum { - RTW_RX_NORMAL = 0, /**< The supported 802.11 packet*/ - RTW_RX_UNSUPPORT = 1, /**< Unsupported 802.11 packet info */ -}; -typedef unsigned long rtw_rx_type_t; -#endif -/** - * @brief The enumeration lists the disconnect reasons. - */ -enum{ - RTW_NO_ERROR = 0, - RTW_NONE_NETWORK = 1, - RTW_CONNECT_FAIL = 2, - RTW_WRONG_PASSWORD = 3 , - RTW_4WAY_HANDSHAKE_TIMEOUT = 4, - RTW_DHCP_FAIL = 5, - RTW_UNKNOWN, -}; -typedef unsigned long rtw_connect_error_flag_t; - -enum { - RTW_TX_PWR_PERCENTAGE_100 = 0, /* 100%, default target output power. */ - RTW_TX_PWR_PERCENTAGE_75 = 1, /* 75% */ - RTW_TX_PWR_PERCENTAGE_50 = 2, /* 50% */ - RTW_TX_PWR_PERCENTAGE_25 = 3, /* 25% */ - RTW_TX_PWR_PERCENTAGE_12_5 = 4, /* 12.5% */ -}; -typedef unsigned long rtw_tx_pwr_percentage_t; - -/** - * @brief The enumeration is event type indicated from wlan driver. - */ -enum _WIFI_EVENT_INDICATE{ - WIFI_EVENT_CONNECT = 0, - WIFI_EVENT_DISCONNECT = 1, - WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, - WIFI_EVENT_SCAN_RESULT_REPORT = 3, - WIFI_EVENT_SCAN_DONE = 4, - WIFI_EVENT_RECONNECTION_FAIL = 5, - WIFI_EVENT_SEND_ACTION_DONE = 6, - WIFI_EVENT_RX_MGNT = 7, - WIFI_EVENT_STA_ASSOC = 8, - WIFI_EVENT_STA_DISASSOC = 9, - WIFI_EVENT_STA_WPS_START = 10, - WIFI_EVENT_WPS_FINISH = 11, - WIFI_EVENT_EAPOL_START = 12, - WIFI_EVENT_EAPOL_RECVD = 13, - WIFI_EVENT_NO_NETWORK = 14, - WIFI_EVENT_BEACON_AFTER_DHCP = 15, - WIFI_EVENT_IP_CHANGED = 16, - WIFI_EVENT_ICV_ERROR = 17, - WIFI_EVENT_CHALLENGE_FAIL = 18, - WIFI_EVENT_MAX, -}; -typedef unsigned long rtw_event_indicate_t; -#ifdef __cplusplus -} -#endif - -/*\@}*/ - -#endif /* _WIFI_CONSTANTS_H */ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_structures.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_structures.h deleted file mode 100644 index c170940239a..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_structures.h +++ /dev/null @@ -1,266 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ****************************************************************************** - * @file wifi_structures.h - * @author - * @version - * @brief This file provides the data structures used for wlan API. - ****************************************************************************** - */ - -#ifndef _WIFI_STRUCTURES_H -#define _WIFI_STRUCTURES_H - -/** @addtogroup nic NIC - * @ingroup wlan - * @brief NIC functions - * @{ - */ - -//#include -#include "wifi_constants.h" -#include "dlist.h" -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(__IAR_SYSTEMS_ICC__) || defined (__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#pragma pack(1) -#endif - -/** - * @brief The structure is used to describe the SSID. - */ -typedef struct rtw_ssid { - unsigned char len; /**< SSID length */ - unsigned char val[33]; /**< SSID name (AP name) */ -} rtw_ssid_t; -#if defined(__IAR_SYSTEMS_ICC__) || defined (__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#pragma pack() -#endif - -#if defined(__IAR_SYSTEMS_ICC__) || defined (__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#pragma pack(1) -#endif - -/** - * @brief The structure is used to describe the unique 6-byte MAC address. - */ -typedef struct rtw_mac { - unsigned char octet[6]; /**< Unique 6-byte MAC address */ -} rtw_mac_t; -#if defined(__IAR_SYSTEMS_ICC__) || defined (__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#pragma pack() -#endif - -/** - * @brief The structure is used to describe the setting about SSID, - * security type, password and default channel, used to start AP mode. - * @note The data length of string pointed by ssid should not exceed 32, - * and the data length of string pointed by password should not exceed 64. - */ -typedef struct rtw_ap_info { - rtw_ssid_t ssid; - rtw_security_t security_type; - unsigned char *password; - int password_len; - int channel; -}rtw_ap_info_t; - -/** - * @brief The structure is used to describe the station mode setting about SSID, - * security type and password, used when connecting to an AP. - * @note The data length of string pointed by ssid should not exceed 32, - * and the data length of string pointed by password should not exceed 64. - */ -typedef struct rtw_network_info { - rtw_ssid_t ssid; - rtw_mac_t bssid; - rtw_security_t security_type; - unsigned char *password; - int password_len; - int key_id; -}rtw_network_info_t; - -#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#pragma pack(1) -#endif - -/** - * @brief The structure is used to describe the scan result of the AP. - */ -typedef struct rtw_scan_result { - rtw_ssid_t SSID; /**< Service Set Identification (i.e. Name of Access Point) */ - rtw_mac_t BSSID; /**< Basic Service Set Identification (i.e. MAC address of Access Point) */ - signed short signal_strength; /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */ - rtw_bss_type_t bss_type; /**< Network type */ - rtw_security_t security; /**< Security type */ - rtw_wps_type_t wps_type; /**< WPS type */ - unsigned int channel; /**< Radio channel that the AP beacon was received on */ - rtw_802_11_band_t band; /**< Radio band */ -} rtw_scan_result_t; -#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#pragma pack() -#endif - -/** - * @brief The structure is used to describe the data needed by scan result handler function. - */ -typedef struct rtw_scan_handler_result { - rtw_scan_result_t ap_details; - rtw_bool_t scan_complete; - void* user_data; - -} rtw_scan_handler_result_t; - -#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#pragma pack(1) -#endif - -/** - * @brief The structure is used to store the WIFI setting gotten from WIFI driver. - */ -typedef struct rtw_wifi_setting { - rtw_mode_t mode; - unsigned char ssid[33]; - unsigned char channel; - rtw_security_t security_type; - unsigned char password[65]; - unsigned char key_idx; -}rtw_wifi_setting_t; -#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#pragma pack() -#endif - -/** - * @brief The structure is used to describe the setting when configure the network. - */ -typedef struct rtw_wifi_config { - unsigned int boot_mode; - unsigned char ssid[32]; - unsigned char ssid_len; - unsigned char security_type; - unsigned char password[65]; - unsigned char password_len; - unsigned char channel; -} rtw_wifi_config_t; - -/** - * @brief The structure is used to describe the maclist. - */ -typedef struct -{ - unsigned int count; /**< Number of MAC addresses in the list */ - rtw_mac_t mac_list[1]; /**< Variable length array of MAC addresses */ -} rtw_maclist_t; - -/** - * @brief The structure is used to describe the bss info of the network.\n - * It include the version, BSSID, beacon_period, capability, SSID, - * channel, atm_window, dtim_period, RSSI e.g. - */ -typedef struct { - unsigned int version; /**< version field */ - unsigned int length; /**< byte length of data in this record, */ - /* starting at version and including IEs */ - rtw_mac_t BSSID; - unsigned short beacon_period; /**< units are Kusec */ - unsigned short capability; /**< Capability information */ - unsigned char SSID_len; - unsigned char SSID[32]; - unsigned char channel; -// struct { -// uint32_t count; /* # rates in this set */ -// uint8_t rates[16]; /* rates in 500kbps units w/hi bit set if basic */ -// } rateset; /* supported rates */ -// rtw_chanspec_t chanspec; /* chanspec for bss */ - unsigned short atim_window; /**< units are Kusec */ - unsigned char dtim_period; /**< DTIM period */ - signed short RSSI; /**< receive signal strength (in dBm) */ - - unsigned char n_cap; /**< BSS is 802.11N Capable */ - unsigned int nbss_cap; /**< 802.11N BSS Capabilities (based on HT_CAP_*) */ - unsigned char basic_mcs[MCSSET_LEN]; /**< 802.11N BSS required MCS set */ - - unsigned short ie_offset; /**< offset at which IEs start, from beginning */ - unsigned int ie_length; /**< byte length of Information Elements */ -} rtw_bss_info_t; - -/** - * @brief The structure is used to set WIFI packet filter pattern. - */ -typedef struct { - unsigned short offset; /**< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */ - unsigned short mask_size; /**< Size of the mask in bytes */ - unsigned char* mask; /**< Pattern mask bytes to be ANDed with the pattern eg. "\xff00" (must be in network byte order) */ - unsigned char* pattern; /**< Pattern bytes used to filter eg. "\x0800" (must be in network byte order) */ -} rtw_packet_filter_pattern_t; - -typedef struct ieee80211_frame_info{ - unsigned short i_fc; - unsigned short i_dur; - unsigned char i_addr1[6]; - unsigned char i_addr2[6]; - unsigned char i_addr3[6]; - unsigned short i_seq; - unsigned char bssid[6]; - unsigned char encrypt; - signed char rssi; -#if CONFIG_UNSUPPORT_PLCPHDR_RPT - rtw_rx_type_t type; -#endif -}ieee80211_frame_info_t; - -#if CONFIG_UNSUPPORT_PLCPHDR_RPT -typedef struct rtw_rx_info { - uint16_t length; //length without FCS - uint8_t filter; // 2: 2T rate pkt; 3: LDPC pkt - signed char rssi; //-128~-1 -}rtw_rx_info_t; - -struct rtw_plcp_info { - struct rtw_plcp_info *prev; - struct rtw_plcp_info *next; - uint16_t length; //length without FCS - uint8_t filter; // 1: HT-20 pkt; 2: HT-40 and not LDPC pkt; 3: LDPC pkt - signed char rssi; //-128~-1 -}; - -struct rtw_rx_buffer { - struct rtw_plcp_info *head; - struct rtw_plcp_info *tail; -}; - -#endif - -typedef struct { - char filter_id; - rtw_packet_filter_pattern_t patt; - rtw_packet_filter_rule_t rule; - unsigned char enable; -}rtw_packet_filter_info_t; - -typedef struct rtw_mac_filter_list{ - struct list_head node; - unsigned char mac_addr[6]; -}rtw_mac_filter_list_t; - -#ifdef __cplusplus -} -#endif - -/*\@}*/ - -#endif /* _WIFI_STRUCTURES_H */ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h deleted file mode 100644 index 5cc291d17c1..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h +++ /dev/null @@ -1,448 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ****************************************************************************** - * Wrapper provide a linux-like interface - ************************************************************************/ -#ifndef __WRAPPER_H__ -#define __WRAPPER_H__ - -//----- ------------------------------------------------------------------ -// Include Files -//----- ------------------------------------------------------------------ -#include -#include -#include "wireless.h" -#include -#include "osdep_service.h" - -#ifndef __LIST_H -#warning "DLIST_NOT_DEFINE!!!!!!" -//----- ------------------------------------------------------------------ -// Linled List -//----- ------------------------------------------------------------------ -/* - * Simple doubly linked list implementation. - * - * Some of the internal functions ("__xxx") are useful when - * manipulating whole lists rather than single entries, as - * sometimes we already know the next/prev entries and we can - * generate better code by using them directly rather than - * using the generic single-entry routines. - */ -// struct list_head { -// struct list_head *next, *prev; -// }; - -#define LIST_HEAD_INIT(name) { &(name), &(name) } -#define INIT_LIST_HEAD(ptr) do { \ - (ptr)->next = (ptr); (ptr)->prev = (ptr); \ -} while (0) - -/* - * Insert a new entry between two known consecutive entries. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -static __inline void __list_add(struct list_head * new, - struct list_head * prev, - struct list_head * next) -{ - next->prev = new; - new->next = next; - new->prev = prev; - prev->next = new; -} - -/* - * Delete a list entry by making the prev/next entries - * point to each other. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -static __inline void __list_del(struct list_head * prev, - struct list_head * next) -{ - next->prev = prev; - prev->next = next; -} - -/** - * list_del - deletes entry from list. - * @entry: the element to delete from the list. - * Note: list_empty on entry does not return true after this, the entry is in an undefined state. - */ -static __inline void list_del(struct list_head *entry) -{ - __list_del(entry->prev, entry->next); -} - -/** - * list_del_init - deletes entry from list and reinitialize it. - * @entry: the element to delete from the list. - */ -static __inline void list_del_init(struct list_head *entry) -{ - __list_del(entry->prev, entry->next); - INIT_LIST_HEAD(entry); -} - -/** - * list_empty - tests whether a list is empty - * @head: the list to test. - */ -static __inline int list_empty(struct list_head *head) -{ - return head->next == head; -} - -/** - * list_splice - join two lists - * @list: the new list to add. - * @head: the place to add it in the first list. - */ -static __inline void list_splice(struct list_head *list, struct list_head *head) -{ - struct list_head *first = list->next; - - if (first != list) { - struct list_head *last = list->prev; - struct list_head *at = head->next; - - first->prev = head; - head->next = first; - - last->next = at; - at->prev = last; - } -} - -void list_add(struct list_head *new, struct list_head *head); -void list_add_tail(struct list_head *new, struct list_head *head); -#endif - -extern void save_and_cli(void); -extern void restore_flags(void); -//----- ------------------------------------------------------------------ -// SKB Operation -//----- ------------------------------------------------------------------ - -#define SMP_CACHE_BYTES 4 -#define SKB_DATA_ALIGN(X) (((X) + (SMP_CACHE_BYTES - 1)) & ~(SMP_CACHE_BYTES - 1)) - -// Consideration for SKB size -// Tx: [INTF_CMD][TX_DESC][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][INTF_STATUS] -// Since SKB is used to accept ethernet packet from upper layer, SKB length of WLAN_MAX_ETHFRM_LEN -// (= 1514) is enough. But since SKB is also used to get spi receive packet, overall buffer space -// should be taken into consideration. -// RX: [INTF_CMD][RX_DESC][Drv_Info][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][CRC][INTF_STATUS] -// -// 32: Driver_Info that carry phy related information for each packets. Required only for receive case. -// WLAN_MAX_ETHFRM_LEN : May not be required because WLAN_HEADER +SNAP can totally -// cover ethernet header. Keep in only for safety. -// -// **Notes** SDIO requires 512 blocks r/w, so 512*4 = 2048 is required. -// 2003/12/26. The value is reduced from 2048 to 1658 for GSPI -// 2014/02/05. The value is 1650 for 8195A LX_BUS -#define SKB_RESERVED_FOR_SAFETY 0 -#define SKB_WLAN_TX_EXTRA_LEN (TXDESC_SIZE + WLAN_HDR_A4_QOS_LEN + WLAN_MAX_IV_LEN + WLAN_SNAP_HEADER - WLAN_ETHHDR_LEN) -#define RX_DRIVER_INFO 32 - -#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI) -#define HAL_INTERFACE_OVERHEAD_SKB_DATA 12 //HAL_INTERFACE_CMD (4) + HAL_INTERFACE_STATUS (8) -#elif defined(CONFIG_LX_HCI) -#define HAL_INTERFACE_OVERHEAD_SKB_DATA 0 -#endif - -#if defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI || defined(CONFIG_LX_HCI) - #if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B) - #if defined(CONFIG_MP_INCLUDED) - #ifdef CONFIG_DONT_CARE_TP - #define MAX_RX_PKT_LIMIT ((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN + 511) / 512) // 4, for lxbus - #else - #define MAX_RX_PKT_LIMIT ((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN + 511) / 512) // 4, for lxbus - #endif - #define MAX_RX_PKT_SIZE MAX_RX_PKT_LIMIT*512 // MAX_SKB_BUF_SIZE = 0+32+40+512*4+0 = 2120 - #else - #ifdef CONFIG_DONT_CARE_TP - #define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN - #else - #define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN // MAX_RX_PKT_SIZE = 64+1514 = 1578 - #endif - #define MAX_RX_PKT_LIMIT ((MAX_RX_PKT_SIZE + 511) / 512) // ((1578 + 512) / 512) = 4 - #endif - #else - #ifdef CONFIG_DONT_CARE_TP - #define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN - #else - #define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN - #endif - #endif - - #ifdef CONFIG_DONT_CARE_TP - #define MAX_TX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\ - ((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\ - WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_TX_ETHFRM_LEN +\ - SKB_RESERVED_FOR_SAFETY) - #define MAX_RX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\ - ((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\ - MAX_RX_PKT_SIZE +\ - SKB_RESERVED_FOR_SAFETY) - #else - #define MAX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\ - ((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\ - MAX_RX_PKT_SIZE +\ - SKB_RESERVED_FOR_SAFETY) // 0+32+40+1578+0 = 1650 - #endif -#else -#define MAX_SKB_BUF_SIZE 2048 -#endif - -#if 0 -struct sk_buff_head { - struct list_head *next, *prev; - u32 qlen; -}; - -struct sk_buff { - /* These two members must be first. */ - struct sk_buff *next; /* Next buffer in list */ - struct sk_buff *prev; /* Previous buffer in list */ - - struct sk_buff_head *list; /* List we are on */ - unsigned char *head; /* Head of buffer */ - unsigned char *data; /* Data head pointer */ - unsigned char *tail; /* Tail pointer */ - unsigned char *end; /* End pointer */ - struct net_device *dev; /* Device we arrived on/are leaving by */ - unsigned int len; /* Length of actual data */ -}; - -/** - * skb_put - add data to a buffer - * @skb: buffer to use - * @len: amount of data to add - * - * This function extends the used data area of the buffer. If this would - * exceed the total buffer size the kernel will panic. A pointer to the - * first byte of the extra data is returned. - */ - -static __inline__ unsigned char *skb_put(struct sk_buff *skb, unsigned int len) -{ - unsigned char *tmp=skb->tail; - skb->tail+=len; - skb->len+=len; - if(skb->tail>skb->end) { - ASSERT(0); - } - - return tmp; -} - -static __inline__ unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) -{ - skb->len-=len; - skb->data = (unsigned char *)(((unsigned int)skb->data) + len); - - return skb->data; -} - -/** - * skb_reserve - adjust headroom - * @skb: buffer to alter - * @len: bytes to move - * - * Increase the headroom of an empty &sk_buff by reducing the tail - * room. This is only allowed for an empty buffer. - */ - -static __inline__ void skb_reserve(struct sk_buff *skb, unsigned int len) -{ - skb->data+=len; - skb->tail+=len; -} - -static __inline__ void skb_queue_head_init(struct sk_buff_head *list) -{ - list->prev = (struct list_head *)list; - list->next = (struct list_head *)list; - list->qlen = 0; -} - -/** - * __skb_queue_tail - queue a buffer at the list tail - * @list: list to use - * @newsk: buffer to queue - * - * Queue a buffer at the end of a list. This function takes no locks - * and you must therefore hold required locks before calling it. - * - * A buffer cannot be placed on two lists at the same time. - */ - -static __inline__ void __skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk) -{ - struct sk_buff *prev, *next; - newsk->list = list; - list->qlen++; - next = (struct sk_buff *)list; - prev = next->prev; - newsk->next = next; - newsk->prev = prev; - next->prev = newsk; - prev->next = newsk; -} - -/** - * skb_queue_tail - queue a buffer at the list tail - * @list: list to use - * @newsk: buffer to queue - * - * Queue a buffer at the tail of the list. This function takes the - * list lock and can be used safely with other locking &sk_buff functions - * safely. - * - * A buffer cannot be placed on two lists at the same time. - */ - -static __inline__ void skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk) -{ - save_and_cli(); - __skb_queue_tail(list, newsk); - restore_flags(); -} - -static __inline__ void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len) -{ - skb->head = buf; - skb->data = buf; - skb->tail = buf; - skb->end = buf + len; -} - -static __inline__ unsigned char *skb_tail_pointer(const struct sk_buff *skb) -{ - return skb->tail; -} - -static __inline__ void skb_reset_tail_pointer(struct sk_buff *skb) -{ - skb->tail = skb->data; -} - -static __inline__ void skb_set_tail_pointer(struct sk_buff *skb, const int offset) -{ - skb->tail = skb->data + offset; -} - -static __inline__ unsigned char *skb_end_pointer(const struct sk_buff *skb) -{ - return skb->end; -} -#endif -/* - * External functions - */ -struct net_device; -extern void kfree_skb_chk_key(struct sk_buff *skb, struct net_device *root_dev); -#ifdef CONFIG_TRACE_SKB -extern void show_skb(void); -extern int _set_skb_list_flag(struct sk_buff *skb, unsigned int queueflag); -extern void dump_skb_list(void); -#define set_skb_list_flag(skb, queueflag) \ - (\ - _set_skb_list_flag((skb), queueflag), \ - (skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__:NULL \ - ) -extern int _clear_skb_list_flag(struct sk_buff *skb, unsigned int queueflag); -#define clear_skb_list_flag(skb, queueflag) \ - (\ - _clear_skb_list_flag((skb), queueflag), \ - (skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__ : NULL \ - ) -#define dev_kfree_skb_any(trx, holder, skb) \ - do{\ - clear_skb_list_flag(skb, SKBLIST_##trx##holder##_MASK);\ - set_skb_list_flag(skb, SKBLIST_POOL);\ - kfree_skb_chk_key(skb, skb->dev);\ - }while (0) -#else -#define dev_kfree_skb_any(skb) kfree_skb_chk_key(skb, skb->dev) -#endif -extern struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len); -extern struct sk_buff *skb_clone(struct sk_buff *skb, int gfp_mask); -extern struct sk_buff *skb_copy(const struct sk_buff *skb, int gfp_mask, unsigned int reserve_len); -extern unsigned char *skb_pull(struct sk_buff *skb, unsigned int len); - -//----- ------------------------------------------------------------------ -// Device structure -//----- ------------------------------------------------------------------ -struct net_device_stats { - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_overflow; /* rx fifo overflow count */ -}; - -struct net_device { - char name[16]; - void *priv; /* pointer to private data */ - unsigned char dev_addr[6]; /* set during bootup */ - int (*init)(void); - int (*open)(struct net_device *dev); - int (*stop)(struct net_device *dev); - int (*hard_start_xmit)(struct sk_buff *skb, struct net_device *dev); - int (*do_ioctl)(struct net_device *dev, struct iwreq *ifr, int cmd); - struct net_device_stats* (*get_stats)(struct net_device *dev); -}; - -typedef struct { - struct net_device *dev; /* Binding wlan driver netdev */ - void *skb; /* pending Rx packet */ - unsigned int tx_busy; - unsigned int rx_busy; - unsigned char enable; - unsigned char mac[6]; -} Rltk_wlan_t; - -#define netdev_priv(dev) dev->priv - -extern struct net_device *alloc_etherdev(int sizeof_priv); -void free_netdev(struct net_device *dev); -int dev_alloc_name(struct net_device *net_dev, const char *ifname); - - -//----- ------------------------------------------------------------------ -// Timer Operation -//----- ------------------------------------------------------------------ -void init_timer(struct timer_list *timer); -void mod_timer(struct timer_list *timer, u32 delay_time_ms); -void cancel_timer_ex(struct timer_list * timer); -void del_timer_sync(struct timer_list * timer); -void init_timer_wrapper(void); -void deinit_timer_wrapper(void); - -void rtw_init_timer(_timer *ptimer, void *adapter, TIMER_FUN pfunc,void* cntx, const char *name); -void rtw_set_timer(_timer *ptimer,u32 delay_time); -u8 rtw_cancel_timer(_timer *ptimer); -void rtw_del_timer(_timer *ptimer); - -#endif //__WRAPPER_H__ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.c deleted file mode 100644 index cae0c3cccea..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.c +++ /dev/null @@ -1,279 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//#define _LWIP_INTF_C_ - -#include -#include -#include -#if !defined(CONFIG_MBED_ENABLED) -#include -#include -#endif -#include -#include -//----- ------------------------------------------------------------------ -// External Reference -//----- ------------------------------------------------------------------ -#if (CONFIG_LWIP_LAYER == 1) -extern struct netif xnetif[]; //LWIP netif -#endif - -/** - * rltk_wlan_set_netif_info - set netif hw address and register dev pointer to netif device - * @idx_wlan: netif index - * 0 for STA only or SoftAP only or STA in STA+SoftAP concurrent mode, - * 1 for SoftAP in STA+SoftAP concurrent mode - * @dev: register netdev pointer to LWIP. Reserved. - * @dev_addr: set netif hw address - * - * Return Value: None - */ -void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr) -{ -#if (CONFIG_LWIP_LAYER == 1) -#if defined(CONFIG_MBED_ENABLED) - //rtw_memcpy(xnetif[idx_wlan]->hwaddr, dev_addr, 6); - //set netif hwaddr later -#else - rtw_memcpy(xnetif[idx_wlan].hwaddr, dev_addr, 6); - xnetif[idx_wlan].state = dev; -#endif -#endif -} - -/** - * rltk_wlan_send - send IP packets to WLAN. Called by low_level_output(). - * @idx: netif index - * @sg_list: data buffer list - * @sg_len: size of each data buffer - * @total_len: total data len - * - * Return Value: None - */ -int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len) -{ -#if (CONFIG_LWIP_LAYER == 1) - struct eth_drv_sg *last_sg; - struct sk_buff *skb = NULL; - int ret = 0; - - if(idx == -1){ - DBG_ERR("netif is DOWN"); - return -1; - } - DBG_TRACE("%s is called", __FUNCTION__); - - save_and_cli(); - if (rltk_wlan_check_isup(idx)) { - rltk_wlan_tx_inc(idx); - } else { - DBG_ERR("netif is DOWN"); - restore_flags(); - return -1; - } - restore_flags(); - - skb = rltk_wlan_alloc_skb(total_len); - if (skb == NULL) { - //DBG_ERR("rltk_wlan_alloc_skb() for data len=%d failed!", total_len); - ret = -1; - goto exit; - } - - for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) { - rtw_memcpy(skb->tail, (void *)(sg_list->buf), sg_list->len); - skb_put(skb, sg_list->len); - } - - rltk_wlan_send_skb(idx, skb); - -exit: - save_and_cli(); - rltk_wlan_tx_dec(idx); - restore_flags(); - return ret; -#endif -} - -/** - * rltk_wlan_recv - indicate packets to LWIP. Called by ethernetif_recv(). - * @idx: netif index - * @sg_list: data buffer list - * @sg_len: size of each data buffer - * - * Return Value: None - */ -void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len) -{ -#if (CONFIG_LWIP_LAYER == 1) - struct eth_drv_sg *last_sg; - struct sk_buff *skb; - - DBG_TRACE("%s is called", __FUNCTION__); - if(idx == -1){ - DBG_ERR("skb is NULL"); - return; - } - skb = rltk_wlan_get_recv_skb(idx); - DBG_ASSERT(skb, "No pending rx skb"); - - for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) { - if (sg_list->buf != 0) { - rtw_memcpy((void *)(sg_list->buf), skb->data, sg_list->len); - skb_pull(skb, sg_list->len); - } - } -#endif -} - -int netif_is_valid_IP(int idx, unsigned char *ip_dest) -{ -#if defined(CONFIG_MBED_ENABLED) - return 1; -#else -#if CONFIG_LWIP_LAYER == 1 - struct netif * pnetif = &xnetif[idx]; - - ip_addr_t addr = { 0 }; - -#ifdef CONFIG_MEMORY_ACCESS_ALIGNED - unsigned int temp; - memcpy(&temp, ip_dest, sizeof(unsigned int)); - u32_t *ip_dest_addr = &temp; -#else - u32_t *ip_dest_addr = (u32_t*)ip_dest; -#endif - -#if LWIP_VERSION_MAJOR >= 2 - ip_addr_set_ip4_u32(&addr, *ip_dest_addr); -#else - addr.addr = *ip_dest_addr; -#endif - -#if (LWIP_VERSION_MAJOR >= 2) - if((ip_addr_get_ip4_u32(netif_ip_addr4(pnetif))) == 0) - return 1; -#else - - if(pnetif->ip_addr.addr == 0) - return 1; -#endif - - if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)){ - return 1; - } - - //if(ip_addr_netcmp(&(pnetif->ip_addr), &addr, &(pnetif->netmask))) //addr&netmask - // return 1; - - if(ip_addr_cmp(&(pnetif->ip_addr),&addr)) - return 1; - - DBG_TRACE("invalid IP: %d.%d.%d.%d ",ip_dest[0],ip_dest[1],ip_dest[2],ip_dest[3]); -#endif -#ifdef CONFIG_DONT_CARE_TP - if(pnetif->flags & NETIF_FLAG_IPSWITCH) - return 1; - else -#endif - return 0; -#endif -} - -#if !defined(CONFIG_MBED_ENABLED) -int netif_get_idx(struct netif* pnetif) -{ -#if (CONFIG_LWIP_LAYER == 1) - int idx = pnetif - xnetif; - - switch(idx) { - case 0: - return 0; - case 1: - return 1; - default: - return -1; - } -#else - return -1; -#endif -} - -unsigned char *netif_get_hwaddr(int idx_wlan) -{ -#if (CONFIG_LWIP_LAYER == 1) - return xnetif[idx_wlan].hwaddr; -#else - return NULL; -#endif -} -#endif - -#if defined(CONFIG_MBED_ENABLED) -emac_callback emac_callback_func = NULL; -void *emac_callback_data = NULL; -void set_callback_func(emac_callback p, void *data) -{ - emac_callback_func = p; - emac_callback_data = data; -} -#endif - -void netif_rx(int idx, unsigned int len) -{ -#if (CONFIG_LWIP_LAYER == 1) -#if defined(CONFIG_MBED_ENABLED) - emac_callback_func(emac_callback_data, NULL, len); -#else - ethernetif_recv(&xnetif[idx], len); -#endif -#endif -#if (CONFIG_INIC_EN == 1) - inic_netif_rx(idx, len); -#endif -} - -void netif_post_sleep_processing(void) -{ -#if (CONFIG_LWIP_LAYER == 1) -#if defined(CONFIG_MBED_ENABLED) -#else - lwip_POST_SLEEP_PROCESSING(); //For FreeRTOS tickless to enable Lwip ARP timer when leaving IPS - Alex Fang -#endif -#endif -} - -void netif_pre_sleep_processing(void) -{ -#if (CONFIG_LWIP_LAYER == 1) -#if defined(CONFIG_MBED_ENABLED) -#else - lwip_PRE_SLEEP_PROCESSING(); -#endif -#endif -} - -#ifdef CONFIG_WOWLAN -unsigned char *rltk_wlan_get_ip(int idx){ -#if (CONFIG_LWIP_LAYER == 1) - return LwIP_GetIP(&xnetif[idx]); -#else - return NULL; -#endif -} -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.h deleted file mode 100644 index 5268dde7761..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.h +++ /dev/null @@ -1,87 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __LWIP_INTF_H__ -#define __LWIP_INTF_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -struct netif; - -//----- ------------------------------------------------------------------ -// Ethernet Buffer -//----- ------------------------------------------------------------------ -#if defined(CONFIG_MBED_ENABLED) -struct eth_drv_sg { - unsigned int buf; - unsigned int len; -}; - -#define MAX_ETH_DRV_SG 32 -#define MAX_ETH_MSG 1540 -#else -#include "ethernetif.h" // moved to ethernetif.h by jimmy 12/2/2015 -#endif -//----- ------------------------------------------------------------------ -// Wlan Interface Provided -//----- ------------------------------------------------------------------ -unsigned char rltk_wlan_check_isup(int idx); -void rltk_wlan_tx_inc(int idx); -void rltk_wlan_tx_dec(int idx); -struct sk_buff * rltk_wlan_get_recv_skb(int idx); -struct sk_buff * rltk_wlan_alloc_skb(unsigned int total_len); -void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr); -void rltk_wlan_send_skb(int idx, struct sk_buff *skb); //struct sk_buff as defined above comment line -int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len); -void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len); -unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down - -#if defined(CONFIG_MBED_ENABLED) -typedef void (*emac_callback)(void *param, struct netif *netif, unsigned int len); -void set_callback_func(emac_callback p, void *data); -#endif - -//----- ------------------------------------------------------------------ -// Network Interface provided -//----- ------------------------------------------------------------------ - -int netif_is_valid_IP(int idx,unsigned char * ip_dest); -int netif_get_idx(struct netif *pnetif); -unsigned char *netif_get_hwaddr(int idx_wlan); -void netif_rx(int idx, unsigned int len); -void netif_post_sleep_processing(void); -void netif_pre_sleep_processing(void); -#if (CONFIG_LWIP_LAYER == 1) -#if !defined(CONFIG_MBED_ENABLED) -extern void ethernetif_recv(struct netif *netif, int total_len); -#endif -extern void lwip_PRE_SLEEP_PROCESSING(void); -extern void lwip_POST_SLEEP_PROCESSING(void); -#endif //CONFIG_LWIP_LAYER == 1 - -#ifdef CONFIG_WOWLAN -extern unsigned char *rltk_wlan_get_ip(int idx); -#endif - -#ifdef __cplusplus -} -#endif - -#endif //#ifndef __LWIP_INTF_H__ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/skbuff.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/skbuff.h deleted file mode 100644 index aab44fef8d3..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/skbuff.h +++ /dev/null @@ -1,72 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ -#ifndef __SKBUFF_H__ -#define __SKBUFF_H__ - -struct sk_buff_head { - struct list_head *next, *prev; - unsigned int qlen; -}; - -#ifdef CONFIG_TRACE_SKB -#define TRACE_SKB_DEPTH 8 -#endif - -struct sk_buff { - /* These two members must be first. */ - struct sk_buff *next; /* Next buffer in list */ - struct sk_buff *prev; /* Previous buffer in list */ - - struct sk_buff_head *list; /* List we are on */ - unsigned char *head; /* Head of buffer */ - unsigned char *data; /* Data head pointer */ - unsigned char *tail; /* Tail pointer */ - unsigned char *end; /* End pointer */ - void *dev; /* Device we arrived on/are leaving by */ - unsigned int len; /* Length of actual data */ -#ifdef CONFIG_TRACE_SKB - unsigned int liston[TRACE_SKB_DEPTH]; /* Trace the Lists we went through */ - const char *funcname[TRACE_SKB_DEPTH]; - unsigned int list_idx; /* Trace the List we are on */ -#endif -//#ifdef CONFIG_DONT_CARE_TP - int dyalloc_flag; -//#endif -}; - -unsigned char *skb_put(struct sk_buff *skb, unsigned int len); -unsigned char *skb_pull(struct sk_buff *skb, unsigned int len); -void skb_reserve(struct sk_buff *skb, unsigned int len); -void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len); -unsigned char *skb_tail_pointer(const struct sk_buff *skb); -void skb_set_tail_pointer(struct sk_buff *skb, const int offset); -unsigned char *skb_end_pointer(const struct sk_buff *skb); - -void init_skb_pool(void); -void init_skb_data_pool(void); - -#ifndef CONFIG_DONT_CARE_TP -struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len); -#else -struct sk_buff *dev_alloc_tx_skb(unsigned int length, unsigned int reserve_len); -struct sk_buff *dev_alloc_rx_skb(unsigned int length, unsigned int reserve_len); -#define dev_alloc_skb dev_alloc_tx_skb -#endif -void kfree_skb(struct sk_buff *skb); - - -#endif //__SKBUFF_H__ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h deleted file mode 100644 index 4d664c8a6e7..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h +++ /dev/null @@ -1,1211 +0,0 @@ -/* - * This file define a set of standard wireless extensions - * - * Version : 22 16.3.07 - * - * Authors : Jean Tourrilhes - HPL - - * Copyright (c) 1997-2007 Jean Tourrilhes, All Rights Reserved. - */ - -#ifndef _LINUX_WIRELESS_H -#define _LINUX_WIRELESS_H - -/************************** DOCUMENTATION **************************/ -/* - * Initial APIs (1996 -> onward) : - * ----------------------------- - * Basically, the wireless extensions are for now a set of standard ioctl - * call + /proc/net/wireless - * - * The entry /proc/net/wireless give statistics and information on the - * driver. - * This is better than having each driver having its entry because - * its centralised and we may remove the driver module safely. - * - * Ioctl are used to configure the driver and issue commands. This is - * better than command line options of insmod because we may want to - * change dynamically (while the driver is running) some parameters. - * - * The ioctl mechanimsm are copied from standard devices ioctl. - * We have the list of command plus a structure descibing the - * data exchanged... - * Note that to add these ioctl, I was obliged to modify : - * # net/core/dev.c (two place + add include) - * # net/ipv4/af_inet.c (one place + add include) - * - * /proc/net/wireless is a copy of /proc/net/dev. - * We have a structure for data passed from the driver to /proc/net/wireless - * Too add this, I've modified : - * # net/core/dev.c (two other places) - * # include/linux/netdevice.h (one place) - * # include/linux/proc_fs.h (one place) - * - * New driver API (2002 -> onward) : - * ------------------------------- - * This file is only concerned with the user space API and common definitions. - * The new driver API is defined and documented in : - * # include/net/iw_handler.h - * - * Note as well that /proc/net/wireless implementation has now moved in : - * # net/core/wireless.c - * - * Wireless Events (2002 -> onward) : - * -------------------------------- - * Events are defined at the end of this file, and implemented in : - * # net/core/wireless.c - * - * Other comments : - * -------------- - * Do not add here things that are redundant with other mechanisms - * (drivers init, ifconfig, /proc/net/dev, ...) and with are not - * wireless specific. - * - * These wireless extensions are not magic : each driver has to provide - * support for them... - * - * IMPORTANT NOTE : As everything in the kernel, this is very much a - * work in progress. Contact me if you have ideas of improvements... - */ - -/***************************** INCLUDES *****************************/ - -/* This header is used in user-space, therefore need to be sanitised - * for that purpose. Those includes are usually not compatible with glibc. - * To know which includes to use in user-space, check iwlib.h. */ -#ifdef __KERNEL__ -#include /* for "caddr_t" et al */ -#include /* for "struct sockaddr" et al */ -#include /* for IFNAMSIZ and co... */ -#endif /* __KERNEL__ */ - -//#include -#define IFNAMSIZ 16 -#define ARPHRD_ETHER 1 /* ethernet hardware format */ - -/***************************** VERSION *****************************/ -/* - * This constant is used to know the availability of the wireless - * extensions and to know which version of wireless extensions it is - * (there is some stuff that will be added in the future...) - * I just plan to increment with each new version. - */ -#define WIRELESS_EXT 22 - -/* - * Changes : - * - * V2 to V3 - * -------- - * Alan Cox start some incompatibles changes. I've integrated a bit more. - * - Encryption renamed to Encode to avoid US regulation problems - * - Frequency changed from float to struct to avoid problems on old 386 - * - * V3 to V4 - * -------- - * - Add sensitivity - * - * V4 to V5 - * -------- - * - Missing encoding definitions in range - * - Access points stuff - * - * V5 to V6 - * -------- - * - 802.11 support (ESSID ioctls) - * - * V6 to V7 - * -------- - * - define IW_ESSID_MAX_SIZE and IW_MAX_AP - * - * V7 to V8 - * -------- - * - Changed my e-mail address - * - More 802.11 support (nickname, rate, rts, frag) - * - List index in frequencies - * - * V8 to V9 - * -------- - * - Support for 'mode of operation' (ad-hoc, managed...) - * - Support for unicast and multicast power saving - * - Change encoding to support larger tokens (>64 bits) - * - Updated iw_params (disable, flags) and use it for NWID - * - Extracted iw_point from iwreq for clarity - * - * V9 to V10 - * --------- - * - Add PM capability to range structure - * - Add PM modifier : MAX/MIN/RELATIVE - * - Add encoding option : IW_ENCODE_NOKEY - * - Add TxPower ioctls (work like TxRate) - * - * V10 to V11 - * ---------- - * - Add WE version in range (help backward/forward compatibility) - * - Add retry ioctls (work like PM) - * - * V11 to V12 - * ---------- - * - Add SIOCSIWSTATS to get /proc/net/wireless programatically - * - Add DEV PRIVATE IOCTL to avoid collisions in SIOCDEVPRIVATE space - * - Add new statistics (frag, retry, beacon) - * - Add average quality (for user space calibration) - * - * V12 to V13 - * ---------- - * - Document creation of new driver API. - * - Extract union iwreq_data from struct iwreq (for new driver API). - * - Rename SIOCSIWNAME as SIOCSIWCOMMIT - * - * V13 to V14 - * ---------- - * - Wireless Events support : define struct iw_event - * - Define additional specific event numbers - * - Add "addr" and "param" fields in union iwreq_data - * - AP scanning stuff (SIOCSIWSCAN and friends) - * - * V14 to V15 - * ---------- - * - Add IW_PRIV_TYPE_ADDR for struct sockaddr private arg - * - Make struct iw_freq signed (both m & e), add explicit padding - * - Add IWEVCUSTOM for driver specific event/scanning token - * - Add IW_MAX_GET_SPY for driver returning a lot of addresses - * - Add IW_TXPOW_RANGE for range of Tx Powers - * - Add IWEVREGISTERED & IWEVEXPIRED events for Access Points - * - Add IW_MODE_MONITOR for passive monitor - * - * V15 to V16 - * ---------- - * - Increase the number of bitrates in iw_range to 32 (for 802.11g) - * - Increase the number of frequencies in iw_range to 32 (for 802.11b+a) - * - Reshuffle struct iw_range for increases, add filler - * - Increase IW_MAX_AP to 64 for driver returning a lot of addresses - * - Remove IW_MAX_GET_SPY because conflict with enhanced spy support - * - Add SIOCSIWTHRSPY/SIOCGIWTHRSPY and "struct iw_thrspy" - * - Add IW_ENCODE_TEMP and iw_range->encoding_login_index - * - * V16 to V17 - * ---------- - * - Add flags to frequency -> auto/fixed - * - Document (struct iw_quality *)->updated, add new flags (INVALID) - * - Wireless Event capability in struct iw_range - * - Add support for relative TxPower (yick !) - * - * V17 to V18 (From Jouni Malinen ) - * ---------- - * - Add support for WPA/WPA2 - * - Add extended encoding configuration (SIOCSIWENCODEEXT and - * SIOCGIWENCODEEXT) - * - Add SIOCSIWGENIE/SIOCGIWGENIE - * - Add SIOCSIWMLME - * - Add SIOCSIWPMKSA - * - Add struct iw_range bit field for supported encoding capabilities - * - Add optional scan request parameters for SIOCSIWSCAN - * - Add SIOCSIWAUTH/SIOCGIWAUTH for setting authentication and WPA - * related parameters (extensible up to 4096 parameter values) - * - Add wireless events: IWEVGENIE, IWEVMICHAELMICFAILURE, - * IWEVASSOCREQIE, IWEVASSOCRESPIE, IWEVPMKIDCAND - * - * V18 to V19 - * ---------- - * - Remove (struct iw_point *)->pointer from events and streams - * - Remove header includes to help user space - * - Increase IW_ENCODING_TOKEN_MAX from 32 to 64 - * - Add IW_QUAL_ALL_UPDATED and IW_QUAL_ALL_INVALID macros - * - Add explicit flag to tell stats are in dBm : IW_QUAL_DBM - * - Add IW_IOCTL_IDX() and IW_EVENT_IDX() macros - * - * V19 to V20 - * ---------- - * - RtNetlink requests support (SET/GET) - * - * V20 to V21 - * ---------- - * - Remove (struct net_device *)->get_wireless_stats() - * - Change length in ESSID and NICK to strlen() instead of strlen()+1 - * - Add IW_RETRY_SHORT/IW_RETRY_LONG retry modifiers - * - Power/Retry relative values no longer * 100000 - * - Add explicit flag to tell stats are in 802.11k RCPI : IW_QUAL_RCPI - * - * V21 to V22 - * ---------- - * - Prevent leaking of kernel space in stream on 64 bits. - */ - -/**************************** CONSTANTS ****************************/ -typedef unsigned char __u8; -typedef char __s8; -typedef unsigned short __u16; -typedef short __s16; -typedef unsigned int __u32; -typedef int __s32; -typedef unsigned long long __u64; -typedef long long __i64; - -#define E2BIG 7 /* Argument list too long */ - -#define ETH_ALEN 6 /* Octets in one ethernet addr */ - -/* Device private ioctl calls */ - -/* - * These 16 ioctls are available to devices via the do_ioctl() device - * vector. Each device should include this file and redefine these names - * as their own. Because these are device dependent it is a good idea - * _NOT_ to issue them to random objects and hope. - * - * THESE IOCTLS ARE _DEPRECATED_ AND WILL DISAPPEAR IN 2.5.X -DaveM - */ - -#define SIOCDEVPRIVATE 0x89F0 /* to 89FF */ - -/* - * These 16 ioctl calls are protocol private - */ - -#define SIOCPROTOPRIVATE 0x89E0 /* to 89EF */ - -/* -------------------------- IOCTL LIST -------------------------- */ - -/* Wireless Identification */ -#define SIOCSIWCOMMIT 0x8B00 /* Commit pending changes to driver */ -#define SIOCGIWNAME 0x8B01 /* get name == wireless protocol */ -/* SIOCGIWNAME is used to verify the presence of Wireless Extensions. - * Common values : "IEEE 802.11-DS", "IEEE 802.11-FH", "IEEE 802.11b"... - * Don't put the name of your driver there, it's useless. */ - -/* Basic operations */ -#define SIOCSIWNWID 0x8B02 /* set network id (pre-802.11) */ -#define SIOCGIWNWID 0x8B03 /* get network id (the cell) */ -#define SIOCSIWFREQ 0x8B04 /* set channel/frequency (Hz) */ -#define SIOCGIWFREQ 0x8B05 /* get channel/frequency (Hz) */ -#define SIOCSIWMODE 0x8B06 /* set operation mode */ -#define SIOCGIWMODE 0x8B07 /* get operation mode */ -#define SIOCSIWSENS 0x8B08 /* set sensitivity (dBm) */ -#define SIOCGIWSENS 0x8B09 /* get sensitivity (dBm) */ - -/* Informative stuff */ -#define SIOCSIWRANGE 0x8B0A /* Unused */ -#define SIOCGIWRANGE 0x8B0B /* Get range of parameters */ -#define SIOCSIWPRIV 0x8B0C /* Unused */ -#define SIOCGIWPRIV 0x8B0D /* get private ioctl interface info */ -#define SIOCSIWSTATS 0x8B0E /* Unused */ -#define SIOCGIWSTATS 0x8B0F /* Get /proc/net/wireless stats */ -/* SIOCGIWSTATS is strictly used between user space and the kernel, and - * is never passed to the driver (i.e. the driver will never see it). */ - -/* Spy support (statistics per MAC address - used for Mobile IP support) */ -#define SIOCSIWSPY 0x8B10 /* set spy addresses */ -#define SIOCGIWSPY 0x8B11 /* get spy info (quality of link) */ -#define SIOCSIWTHRSPY 0x8B12 /* set spy threshold (spy event) */ -#define SIOCGIWTHRSPY 0x8B13 /* get spy threshold */ - -/* Access Point manipulation */ -#define SIOCSIWAP 0x8B14 /* set access point MAC addresses */ -#define SIOCGIWAP 0x8B15 /* get access point MAC addresses */ -#define SIOCGIWAPLIST 0x8B17 /* Deprecated in favor of scanning */ -#define SIOCSIWSCAN 0x8B18 /* trigger scanning (list cells) */ -#define SIOCGIWSCAN 0x8B19 /* get scanning results */ - -/* 802.11 specific support */ -#define SIOCSIWESSID 0x8B1A /* set ESSID (network name) */ -#define SIOCGIWESSID 0x8B1B /* get ESSID */ -#define SIOCSIWNICKN 0x8B1C /* set node name/nickname */ -#define SIOCGIWNICKN 0x8B1D /* get node name/nickname */ -/* As the ESSID and NICKN are strings up to 32 bytes long, it doesn't fit - * within the 'iwreq' structure, so we need to use the 'data' member to - * point to a string in user space, like it is done for RANGE... */ - -/* Other parameters useful in 802.11 and some other devices */ -#define SIOCSIWRATE 0x8B20 /* set default bit rate (bps) */ -#define SIOCGIWRATE 0x8B21 /* get default bit rate (bps) */ -#define SIOCSIWRTS 0x8B22 /* set RTS/CTS threshold (bytes) */ -#define SIOCGIWRTS 0x8B23 /* get RTS/CTS threshold (bytes) */ -#define SIOCSIWFRAG 0x8B24 /* set fragmentation thr (bytes) */ -#define SIOCGIWFRAG 0x8B25 /* get fragmentation thr (bytes) */ -#define SIOCSIWTXPOW 0x8B26 /* set transmit power (dBm) */ -#define SIOCGIWTXPOW 0x8B27 /* get transmit power (dBm) */ -#define SIOCSIWRETRY 0x8B28 /* set retry limits and lifetime */ -#define SIOCGIWRETRY 0x8B29 /* get retry limits and lifetime */ - -/* Encoding stuff (scrambling, hardware security, WEP...) */ -#define SIOCSIWENCODE 0x8B2A /* set encoding token & mode */ -#define SIOCGIWENCODE 0x8B2B /* get encoding token & mode */ -/* Power saving stuff (power management, unicast and multicast) */ -#define SIOCSIWPOWER 0x8B2C /* set Power Management settings */ -#define SIOCGIWPOWER 0x8B2D /* get Power Management settings */ -/* Modulation bitmask */ -#define SIOCSIWMODUL 0x8B2E /* set Modulations settings */ -#define SIOCGIWMODUL 0x8B2F /* get Modulations settings */ - -/* WPA : Generic IEEE 802.11 informatiom element (e.g., for WPA/RSN/WMM). - * This ioctl uses struct iw_point and data buffer that includes IE id and len - * fields. More than one IE may be included in the request. Setting the generic - * IE to empty buffer (len=0) removes the generic IE from the driver. Drivers - * are allowed to generate their own WPA/RSN IEs, but in these cases, drivers - * are required to report the used IE as a wireless event, e.g., when - * associating with an AP. */ -#define SIOCSIWGENIE 0x8B30 /* set generic IE */ -#define SIOCGIWGENIE 0x8B31 /* get generic IE */ - -/* WPA : IEEE 802.11 MLME requests */ -#define SIOCSIWMLME 0x8B16 /* request MLME operation; uses - * struct iw_mlme */ -/* WPA : Authentication mode parameters */ -#define SIOCSIWAUTH 0x8B32 /* set authentication mode params */ -#define SIOCGIWAUTH 0x8B33 /* get authentication mode params */ - -/* WPA : Extended version of encoding configuration */ -#define SIOCSIWENCODEEXT 0x8B34 /* set encoding token & mode */ -#define SIOCGIWENCODEEXT 0x8B35 /* get encoding token & mode */ - -/* WPA2 : PMKSA cache management */ -#define SIOCSIWPMKSA 0x8B36 /* PMKSA cache operation */ - -/* Send Mgnt Frame or Action Frame */ -#define SIOCSIWMGNTSEND 0x8B37 /* Send Mgnt Frame or Action Frame */ - -/* Send WPS EAPOL Frame */ -#define SIOCSIWEAPOLSEND 0x8B38 /* Send WPS EAPOL Frame */ -/* -------------------- DEV PRIVATE IOCTL LIST -------------------- */ - -/* These 32 ioctl are wireless device private, for 16 commands. - * Each driver is free to use them for whatever purpose it chooses, - * however the driver *must* export the description of those ioctls - * with SIOCGIWPRIV and *must* use arguments as defined below. - * If you don't follow those rules, DaveM is going to hate you (reason : - * it make mixed 32/64bit operation impossible). - */ -#define SIOCIWFIRSTPRIV 0x8BE0 -#define SIOCIWLASTPRIV 0x8BFF - -#define SIOCSIWPRIVADAPTIVITY 0x8BFB -#define SIOCGIWPRIVPASSPHRASE 0x8BFC -#define SIOCSIWPRIVCOUNTRY 0x8BFD -#define SIOCSIWPRIVAPESSID 0x8BFE -#define SIOCSIWPRIVPASSPHRASE 0x8BFF -/* Previously, we were using SIOCDEVPRIVATE, but we now have our - * separate range because of collisions with other tools such as - * 'mii-tool'. - * We now have 32 commands, so a bit more space ;-). - * Also, all 'even' commands are only usable by root and don't return the - * content of ifr/iwr to user (but you are not obliged to use the set/get - * convention, just use every other two command). More details in iwpriv.c. - * And I repeat : you are not forced to use them with iwpriv, but you - * must be compliant with it. - */ - -/* ------------------------- IOCTL STUFF ------------------------- */ - -/* The first and the last (range) */ -#define SIOCIWFIRST 0x8B00 -#define SIOCIWLAST SIOCIWLASTPRIV /* 0x8BFF */ -#define IW_IOCTL_IDX(cmd) ((cmd) - SIOCIWFIRST) - -/* Odd : get (world access), even : set (root access) */ -#define IW_IS_SET(cmd) (!((cmd) & 0x1)) -#define IW_IS_GET(cmd) ((cmd) & 0x1) - -/* ----------------------- WIRELESS EVENTS ----------------------- */ -/* Those are *NOT* ioctls, do not issue request on them !!! */ -/* Most events use the same identifier as ioctl requests */ - -#define IWEVTXDROP 0x8C00 /* Packet dropped to excessive retry */ -#define IWEVQUAL 0x8C01 /* Quality part of statistics (scan) */ -#define IWEVCUSTOM 0x8C02 /* Driver specific ascii string */ -#define IWEVREGISTERED 0x8C03 /* Discovered a new node (AP mode) */ -#define IWEVEXPIRED 0x8C04 /* Expired a node (AP mode) */ -#define IWEVGENIE 0x8C05 /* Generic IE (WPA, RSN, WMM, ..) - * (scan results); This includes id and - * length fields. One IWEVGENIE may - * contain more than one IE. Scan - * results may contain one or more - * IWEVGENIE events. */ -#define IWEVMICHAELMICFAILURE 0x8C06 /* Michael MIC failure - * (struct iw_michaelmicfailure) - */ -#define IWEVASSOCREQIE 0x8C07 /* IEs used in (Re)Association Request. - * The data includes id and length - * fields and may contain more than one - * IE. This event is required in - * Managed mode if the driver - * generates its own WPA/RSN IE. This - * should be sent just before - * IWEVREGISTERED event for the - * association. */ -#define IWEVASSOCRESPIE 0x8C08 /* IEs used in (Re)Association - * Response. The data includes id and - * length fields and may contain more - * than one IE. This may be sent - * between IWEVASSOCREQIE and - * IWEVREGISTERED events for the - * association. */ -#define IWEVPMKIDCAND 0x8C09 /* PMKID candidate for RSN - * pre-authentication - * (struct iw_pmkid_cand) */ - -#define IWEVFIRST 0x8C00 -#define IW_EVENT_IDX(cmd) ((cmd) - IWEVFIRST) - -/* Indicate Mgnt Frame and Action Frame to uplayer*/ -#define IWEVMGNTRECV 0x8C10 /* Indicate Mgnt Frame to uplayer */ - -/* ------------------------- PRIVATE INFO ------------------------- */ -/* - * The following is used with SIOCGIWPRIV. It allow a driver to define - * the interface (name, type of data) for its private ioctl. - * Privates ioctl are SIOCIWFIRSTPRIV -> SIOCIWLASTPRIV - */ - -#define IW_PRIV_TYPE_MASK 0x7000 /* Type of arguments */ -#define IW_PRIV_TYPE_NONE 0x0000 -#define IW_PRIV_TYPE_BYTE 0x1000 /* Char as number */ -#define IW_PRIV_TYPE_CHAR 0x2000 /* Char as character */ -#define IW_PRIV_TYPE_INT 0x4000 /* 32 bits int */ -#define IW_PRIV_TYPE_FLOAT 0x5000 /* struct iw_freq */ -#define IW_PRIV_TYPE_ADDR 0x6000 /* struct sockaddr */ - -#define IW_PRIV_SIZE_FIXED 0x0800 /* Variable or fixed number of args */ - -#define IW_PRIV_SIZE_MASK 0x07FF /* Max number of those args */ - -/* - * Note : if the number of args is fixed and the size < 16 octets, - * instead of passing a pointer we will put args in the iwreq struct... - */ - -/* ----------------------- OTHER CONSTANTS ----------------------- */ - -/* Maximum frequencies in the range struct */ -#define IW_MAX_FREQUENCIES 32 -/* Note : if you have something like 80 frequencies, - * don't increase this constant and don't fill the frequency list. - * The user will be able to set by channel anyway... */ - -/* Maximum bit rates in the range struct */ -#define IW_MAX_BITRATES 32 - -/* Maximum tx powers in the range struct */ -#define IW_MAX_TXPOWER 8 -/* Note : if you more than 8 TXPowers, just set the max and min or - * a few of them in the struct iw_range. */ - -/* Maximum of address that you may set with SPY */ -#define IW_MAX_SPY 8 - -/* Maximum of address that you may get in the - list of access points in range */ -#define IW_MAX_AP 64 - -/* Maximum size of the ESSID and NICKN strings */ -#define IW_ESSID_MAX_SIZE 32 - -/* Modes of operation */ -#define IW_MODE_AUTO 0 /* Let the driver decides */ -#define IW_MODE_ADHOC 1 /* Single cell network */ -#define IW_MODE_INFRA 2 /* Multi cell network, roaming, ... */ -#define IW_MODE_MASTER 3 /* Synchronisation master or Access Point */ -#define IW_MODE_REPEAT 4 /* Wireless Repeater (forwarder) */ -#define IW_MODE_SECOND 5 /* Secondary master/repeater (backup) */ -#define IW_MODE_MONITOR 6 /* Passive monitor (listen only) */ - -/* Statistics flags (bitmask in updated) */ -#define IW_QUAL_QUAL_UPDATED 0x01 /* Value was updated since last read */ -#define IW_QUAL_LEVEL_UPDATED 0x02 -#define IW_QUAL_NOISE_UPDATED 0x04 -#define IW_QUAL_ALL_UPDATED 0x07 -#define IW_QUAL_DBM 0x08 /* Level + Noise are dBm */ -#define IW_QUAL_QUAL_INVALID 0x10 /* Driver doesn't provide value */ -#define IW_QUAL_LEVEL_INVALID 0x20 -#define IW_QUAL_NOISE_INVALID 0x40 -#define IW_QUAL_RCPI 0x80 /* Level + Noise are 802.11k RCPI */ -#define IW_QUAL_ALL_INVALID 0x70 - -/* Frequency flags */ -#define IW_FREQ_AUTO 0x00 /* Let the driver decides */ -#define IW_FREQ_FIXED 0x01 /* Force a specific value */ - -/* Maximum number of size of encoding token available - * they are listed in the range structure */ -#define IW_MAX_ENCODING_SIZES 8 - -/* Maximum size of the encoding token in bytes */ -#define IW_ENCODING_TOKEN_MAX 64 /* 512 bits (for now) */ - -/* Flags for encoding (along with the token) */ -#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */ -#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */ -#define IW_ENCODE_MODE 0xF000 /* Modes defined below */ -#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */ -#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */ -#define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */ -#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */ -#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */ -#define IW_ENCODE_TEMP 0x0400 /* Temporary key */ - -/* Power management flags available (along with the value, if any) */ -#define IW_POWER_ON 0x0000 /* No details... */ -#define IW_POWER_TYPE 0xF000 /* Type of parameter */ -#define IW_POWER_PERIOD 0x1000 /* Value is a period/duration of */ -#define IW_POWER_TIMEOUT 0x2000 /* Value is a timeout (to go asleep) */ -#define IW_POWER_SAVING 0x4000 /* Value is relative (how aggressive)*/ -#define IW_POWER_MODE 0x0F00 /* Power Management mode */ -#define IW_POWER_UNICAST_R 0x0100 /* Receive only unicast messages */ -#define IW_POWER_MULTICAST_R 0x0200 /* Receive only multicast messages */ -#define IW_POWER_ALL_R 0x0300 /* Receive all messages though PM */ -#define IW_POWER_FORCE_S 0x0400 /* Force PM procedure for sending unicast */ -#define IW_POWER_REPEATER 0x0800 /* Repeat broadcast messages in PM period */ -#define IW_POWER_MODIFIER 0x000F /* Modify a parameter */ -#define IW_POWER_MIN 0x0001 /* Value is a minimum */ -#define IW_POWER_MAX 0x0002 /* Value is a maximum */ -#define IW_POWER_RELATIVE 0x0004 /* Value is not in seconds/ms/us */ - -/* Transmit Power flags available */ -#define IW_TXPOW_TYPE 0x00FF /* Type of value */ -#define IW_TXPOW_DBM 0x0000 /* Value is in dBm */ -#define IW_TXPOW_MWATT 0x0001 /* Value is in mW */ -#define IW_TXPOW_RELATIVE 0x0002 /* Value is in arbitrary units */ -#define IW_TXPOW_RANGE 0x1000 /* Range of value between min/max */ - -/* Retry limits and lifetime flags available */ -#define IW_RETRY_ON 0x0000 /* No details... */ -#define IW_RETRY_TYPE 0xF000 /* Type of parameter */ -#define IW_RETRY_LIMIT 0x1000 /* Maximum number of retries*/ -#define IW_RETRY_LIFETIME 0x2000 /* Maximum duration of retries in us */ -#define IW_RETRY_MODIFIER 0x00FF /* Modify a parameter */ -#define IW_RETRY_MIN 0x0001 /* Value is a minimum */ -#define IW_RETRY_MAX 0x0002 /* Value is a maximum */ -#define IW_RETRY_RELATIVE 0x0004 /* Value is not in seconds/ms/us */ -#define IW_RETRY_SHORT 0x0010 /* Value is for short packets */ -#define IW_RETRY_LONG 0x0020 /* Value is for long packets */ - -/* Scanning request flags */ -#define IW_SCAN_DEFAULT 0x0000 /* Default scan of the driver */ -#define IW_SCAN_ALL_ESSID 0x0001 /* Scan all ESSIDs */ -#define IW_SCAN_THIS_ESSID 0x0002 /* Scan only this ESSID */ -#define IW_SCAN_ALL_FREQ 0x0004 /* Scan all Frequencies */ -#define IW_SCAN_THIS_FREQ 0x0008 /* Scan only this Frequency */ -#define IW_SCAN_ALL_MODE 0x0010 /* Scan all Modes */ -#define IW_SCAN_THIS_MODE 0x0020 /* Scan only this Mode */ -#define IW_SCAN_ALL_RATE 0x0040 /* Scan all Bit-Rates */ -#define IW_SCAN_THIS_RATE 0x0080 /* Scan only this Bit-Rate */ -/* struct iw_scan_req scan_type */ -#define IW_SCAN_TYPE_ACTIVE 0 -#define IW_SCAN_TYPE_PASSIVE 1 -/* Maximum size of returned data */ -#define IW_SCAN_MAX_DATA 4096 /* In bytes */ - -/* Max number of char in custom event - use multiple of them if needed */ -#define IW_CUSTOM_MAX 256 /* In bytes */ - -/* Generic information element */ -#define IW_GENERIC_IE_MAX 1024 - -/* MLME requests (SIOCSIWMLME / struct iw_mlme) */ -#define IW_MLME_DEAUTH 0 -#define IW_MLME_DISASSOC 1 -#define IW_MLME_AUTH 2 -#define IW_MLME_ASSOC 3 - -/* SIOCSIWAUTH/SIOCGIWAUTH struct iw_param flags */ -#define IW_AUTH_INDEX 0x0FFF -#define IW_AUTH_FLAGS 0xF000 -/* SIOCSIWAUTH/SIOCGIWAUTH parameters (0 .. 4095) - * (IW_AUTH_INDEX mask in struct iw_param flags; this is the index of the - * parameter that is being set/get to; value will be read/written to - * struct iw_param value field) */ -#define IW_AUTH_WPA_VERSION 0 -#define IW_AUTH_CIPHER_PAIRWISE 1 -#define IW_AUTH_CIPHER_GROUP 2 -#define IW_AUTH_KEY_MGMT 3 -#define IW_AUTH_TKIP_COUNTERMEASURES 4 -#define IW_AUTH_DROP_UNENCRYPTED 5 -#define IW_AUTH_80211_AUTH_ALG 6 -#define IW_AUTH_WPA_ENABLED 7 -#define IW_AUTH_RX_UNENCRYPTED_EAPOL 8 -#define IW_AUTH_ROAMING_CONTROL 9 -#define IW_AUTH_PRIVACY_INVOKED 10 - -/* IW_AUTH_WPA_VERSION values (bit field) */ -#define IW_AUTH_WPA_VERSION_DISABLED 0x00000001 -#define IW_AUTH_WPA_VERSION_WPA 0x00000002 -#define IW_AUTH_WPA_VERSION_WPA2 0x00000004 - -/* IW_AUTH_PAIRWISE_CIPHER and IW_AUTH_GROUP_CIPHER values (bit field) */ -#define IW_AUTH_CIPHER_NONE 0x00000001 -#define IW_AUTH_CIPHER_WEP40 0x00000002 -#define IW_AUTH_CIPHER_TKIP 0x00000004 -#define IW_AUTH_CIPHER_CCMP 0x00000008 -#define IW_AUTH_CIPHER_WEP104 0x00000010 - -/* IW_AUTH_KEY_MGMT values (bit field) */ -#define IW_AUTH_KEY_MGMT_802_1X 1 -#define IW_AUTH_KEY_MGMT_PSK 2 - -/* IW_AUTH_80211_AUTH_ALG values (bit field) */ -#define IW_AUTH_ALG_OPEN_SYSTEM 0x00000001 -#define IW_AUTH_ALG_SHARED_KEY 0x00000002 -#define IW_AUTH_ALG_LEAP 0x00000004 - -/* IW_AUTH_ROAMING_CONTROL values */ -#define IW_AUTH_ROAMING_ENABLE 0 /* driver/firmware based roaming */ -#define IW_AUTH_ROAMING_DISABLE 1 /* user space program used for roaming - * control */ - -/* SIOCSIWENCODEEXT definitions */ -#define IW_ENCODE_SEQ_MAX_SIZE 8 -/* struct iw_encode_ext ->alg */ -#define IW_ENCODE_ALG_NONE 0 -#define IW_ENCODE_ALG_WEP 1 -#define IW_ENCODE_ALG_TKIP 2 -#define IW_ENCODE_ALG_CCMP 3 -/* struct iw_encode_ext ->ext_flags */ -#define IW_ENCODE_EXT_TX_SEQ_VALID 0x00000001 -#define IW_ENCODE_EXT_RX_SEQ_VALID 0x00000002 -#define IW_ENCODE_EXT_GROUP_KEY 0x00000004 -#define IW_ENCODE_EXT_SET_TX_KEY 0x00000008 - -/* IWEVMICHAELMICFAILURE : struct iw_michaelmicfailure ->flags */ -#define IW_MICFAILURE_KEY_ID 0x00000003 /* Key ID 0..3 */ -#define IW_MICFAILURE_GROUP 0x00000004 -#define IW_MICFAILURE_PAIRWISE 0x00000008 -#define IW_MICFAILURE_STAKEY 0x00000010 -#define IW_MICFAILURE_COUNT 0x00000060 /* 1 or 2 (0 = count not supported) - */ - -/* Bit field values for enc_capa in struct iw_range */ -#define IW_ENC_CAPA_WPA 0x00000001 -#define IW_ENC_CAPA_WPA2 0x00000002 -#define IW_ENC_CAPA_CIPHER_TKIP 0x00000004 -#define IW_ENC_CAPA_CIPHER_CCMP 0x00000008 - -/* Event capability macros - in (struct iw_range *)->event_capa - * Because we have more than 32 possible events, we use an array of - * 32 bit bitmasks. Note : 32 bits = 0x20 = 2^5. */ -#define IW_EVENT_CAPA_BASE(cmd) ((cmd >= SIOCIWFIRSTPRIV) ? \ - (cmd - SIOCIWFIRSTPRIV + 0x60) : \ - (cmd - SIOCSIWCOMMIT)) -#define IW_EVENT_CAPA_INDEX(cmd) (IW_EVENT_CAPA_BASE(cmd) >> 5) -#define IW_EVENT_CAPA_MASK(cmd) (1 << (IW_EVENT_CAPA_BASE(cmd) & 0x1F)) -/* Event capability constants - event autogenerated by the kernel - * This list is valid for most 802.11 devices, customise as needed... */ -#define IW_EVENT_CAPA_K_0 (IW_EVENT_CAPA_MASK(0x8B04) | \ - IW_EVENT_CAPA_MASK(0x8B06) | \ - IW_EVENT_CAPA_MASK(0x8B1A)) -#define IW_EVENT_CAPA_K_1 (IW_EVENT_CAPA_MASK(0x8B2A)) -/* "Easy" macro to set events in iw_range (less efficient) */ -#define IW_EVENT_CAPA_SET(event_capa, cmd) (event_capa[IW_EVENT_CAPA_INDEX(cmd)] |= IW_EVENT_CAPA_MASK(cmd)) -#define IW_EVENT_CAPA_SET_KERNEL(event_capa) {event_capa[0] |= IW_EVENT_CAPA_K_0; event_capa[1] |= IW_EVENT_CAPA_K_1; } - -/* Modulations bitmasks */ -#define IW_MODUL_ALL 0x00000000 /* Everything supported */ -#define IW_MODUL_FH 0x00000001 /* Frequency Hopping */ -#define IW_MODUL_DS 0x00000002 /* Original Direct Sequence */ -#define IW_MODUL_CCK 0x00000004 /* 802.11b : 5.5 + 11 Mb/s */ -#define IW_MODUL_11B (IW_MODUL_DS | IW_MODUL_CCK) -#define IW_MODUL_PBCC 0x00000008 /* TI : 5.5 + 11 + 22 Mb/s */ -#define IW_MODUL_OFDM_A 0x00000010 /* 802.11a : 54 Mb/s */ -#define IW_MODUL_11A (IW_MODUL_OFDM_A) -#define IW_MODUL_11AB (IW_MODUL_11B | IW_MODUL_11A) -#define IW_MODUL_OFDM_G 0x00000020 /* 802.11g : 54 Mb/s */ -#define IW_MODUL_11G (IW_MODUL_11B | IW_MODUL_OFDM_G) -#define IW_MODUL_11AG (IW_MODUL_11G | IW_MODUL_11A) -#define IW_MODUL_TURBO 0x00000040 /* ATH : bonding, 108 Mb/s */ -/* In here we should define MIMO stuff. Later... */ -#define IW_MODUL_CUSTOM 0x40000000 /* Driver specific */ - -/* Bitrate flags available */ -#define IW_BITRATE_TYPE 0x00FF /* Type of value */ -#define IW_BITRATE_UNICAST 0x0001 /* Maximum/Fixed unicast bitrate */ -#define IW_BITRATE_BROADCAST 0x0002 /* Fixed broadcast bitrate */ - -/****************************** TYPES ******************************/ - -/* --------------------------- SUBTYPES --------------------------- */ - -struct sockaddr_t { - __u8 sa_len; - __u8 sa_family; - char sa_data[14]; -}; - -/* - * Generic format for most parameters that fit in an int - */ -struct iw_param -{ - __s32 value; /* The value of the parameter itself */ - __u8 fixed; /* Hardware should not use auto select */ - __u8 disabled; /* Disable the feature */ - __u16 flags; /* Various specifc flags (if any) */ -}; - -/* - * For all data larger than 16 octets, we need to use a - * pointer to memory allocated in user space. - */ -struct iw_point -{ - void *pointer; /* Pointer to the data (in user space) */ - __u16 length; /* number of fields or size in bytes */ - __u16 flags; /* Optional params */ -}; - -/* - * A frequency - * For numbers lower than 10^9, we encode the number in 'm' and - * set 'e' to 0 - * For number greater than 10^9, we divide it by the lowest power - * of 10 to get 'm' lower than 10^9, with 'm'= f / (10^'e')... - * The power of 10 is in 'e', the result of the division is in 'm'. - */ -struct iw_freq -{ - __s32 m; /* Mantissa */ - __s16 e; /* Exponent */ - __u8 i; /* List index (when in range struct) */ - __u8 flags; /* Flags (fixed/auto) */ -}; - -/* - * Quality of the link - */ -struct iw_quality -{ - __u8 qual; /* link quality (%retries, SNR, - %missed beacons or better...) */ - __u8 level; /* signal level (dBm) */ - __u8 noise; /* noise level (dBm) */ - __u8 updated; /* Flags to know if updated */ -}; - -/* - * Packet discarded in the wireless adapter due to - * "wireless" specific problems... - * Note : the list of counter and statistics in net_device_stats - * is already pretty exhaustive, and you should use that first. - * This is only additional stats... - */ -struct iw_discarded -{ - __u32 nwid; /* Rx : Wrong nwid/essid */ - __u32 code; /* Rx : Unable to code/decode (WEP) */ - __u32 fragment; /* Rx : Can't perform MAC reassembly */ - __u32 retries; /* Tx : Max MAC retries num reached */ - __u32 misc; /* Others cases */ -}; - -/* - * Packet/Time period missed in the wireless adapter due to - * "wireless" specific problems... - */ -struct iw_missed -{ - __u32 beacon; /* Missed beacons/superframe */ -}; - -/* - * Quality range (for spy threshold) - */ -struct iw_thrspy -{ - struct sockaddr_t addr; /* Source address (hw/mac) */ - struct iw_quality qual; /* Quality of the link */ - struct iw_quality low; /* Low threshold */ - struct iw_quality high; /* High threshold */ -}; - -/* - * Optional data for scan request - * - * Note: these optional parameters are controlling parameters for the - * scanning behavior, these do not apply to getting scan results - * (SIOCGIWSCAN). Drivers are expected to keep a local BSS table and - * provide a merged results with all BSSes even if the previous scan - * request limited scanning to a subset, e.g., by specifying an SSID. - * Especially, scan results are required to include an entry for the - * current BSS if the driver is in Managed mode and associated with an AP. - */ -struct iw_scan_req -{ - __u8 scan_type; /* IW_SCAN_TYPE_{ACTIVE,PASSIVE} */ - __u8 essid_len; - __u8 num_channels; /* num entries in channel_list; - * 0 = scan all allowed channels */ - __u8 flags; /* reserved as padding; use zero, this may - * be used in the future for adding flags - * to request different scan behavior */ - struct sockaddr_t bssid; /* ff:ff:ff:ff:ff:ff for broadcast BSSID or - * individual address of a specific BSS */ - - /* - * Use this ESSID if IW_SCAN_THIS_ESSID flag is used instead of using - * the current ESSID. This allows scan requests for specific ESSID - * without having to change the current ESSID and potentially breaking - * the current association. - */ - __u8 essid[IW_ESSID_MAX_SIZE]; - - /* - * Optional parameters for changing the default scanning behavior. - * These are based on the MLME-SCAN.request from IEEE Std 802.11. - * TU is 1.024 ms. If these are set to 0, driver is expected to use - * reasonable default values. min_channel_time defines the time that - * will be used to wait for the first reply on each channel. If no - * replies are received, next channel will be scanned after this. If - * replies are received, total time waited on the channel is defined by - * max_channel_time. - */ - __u32 min_channel_time; /* in TU */ - __u32 max_channel_time; /* in TU */ - - struct iw_freq channel_list[IW_MAX_FREQUENCIES]; -}; - -/* ------------------------- WPA SUPPORT ------------------------- */ - -/* - * Extended data structure for get/set encoding (this is used with - * SIOCSIWENCODEEXT/SIOCGIWENCODEEXT. struct iw_point and IW_ENCODE_* - * flags are used in the same way as with SIOCSIWENCODE/SIOCGIWENCODE and - * only the data contents changes (key data -> this structure, including - * key data). - * - * If the new key is the first group key, it will be set as the default - * TX key. Otherwise, default TX key index is only changed if - * IW_ENCODE_EXT_SET_TX_KEY flag is set. - * - * Key will be changed with SIOCSIWENCODEEXT in all cases except for - * special "change TX key index" operation which is indicated by setting - * key_len = 0 and ext_flags |= IW_ENCODE_EXT_SET_TX_KEY. - * - * tx_seq/rx_seq are only used when respective - * IW_ENCODE_EXT_{TX,RX}_SEQ_VALID flag is set in ext_flags. Normal - * TKIP/CCMP operation is to set RX seq with SIOCSIWENCODEEXT and start - * TX seq from zero whenever key is changed. SIOCGIWENCODEEXT is normally - * used only by an Authenticator (AP or an IBSS station) to get the - * current TX sequence number. Using TX_SEQ_VALID for SIOCSIWENCODEEXT and - * RX_SEQ_VALID for SIOCGIWENCODEEXT are optional, but can be useful for - * debugging/testing. - */ -struct iw_encode_ext -{ - __u32 ext_flags; /* IW_ENCODE_EXT_* */ - __u8 tx_seq[IW_ENCODE_SEQ_MAX_SIZE]; /* LSB first */ - __u8 rx_seq[IW_ENCODE_SEQ_MAX_SIZE]; /* LSB first */ - struct sockaddr_t addr; /* ff:ff:ff:ff:ff:ff for broadcast/multicast - * (group) keys or unicast address for - * individual keys */ - __u16 alg; /* IW_ENCODE_ALG_* */ - __u16 key_len; -#ifdef __CC_ARM //Fix Keil compile error, must modify sizeof iw_encode_ext - Alex Fang - __u8 key[1]; -#else - __u8 key[0]; -#endif -}; - -/* SIOCSIWMLME data */ -struct iw_mlme -{ - __u16 cmd; /* IW_MLME_* */ - __u16 reason_code; - struct sockaddr_t addr; -}; - -/* SIOCSIWPMKSA data */ -#define IW_PMKSA_ADD 1 -#define IW_PMKSA_REMOVE 2 -#define IW_PMKSA_FLUSH 3 - -#define IW_PMKID_LEN 16 - -struct iw_pmksa -{ - __u32 cmd; /* IW_PMKSA_* */ - struct sockaddr_t bssid; - __u8 pmkid[IW_PMKID_LEN]; -}; - -/* IWEVMICHAELMICFAILURE data */ -struct iw_michaelmicfailure -{ - __u32 flags; - struct sockaddr_t src_addr; - __u8 tsc[IW_ENCODE_SEQ_MAX_SIZE]; /* LSB first */ -}; - -/* IWEVPMKIDCAND data */ -#define IW_PMKID_CAND_PREAUTH 0x00000001 /* RNS pre-authentication enabled */ -struct iw_pmkid_cand -{ - __u32 flags; /* IW_PMKID_CAND_* */ - __u32 index; /* the smaller the index, the higher the - * priority */ - struct sockaddr_t bssid; -}; - -/* ------------------------ WIRELESS STATS ------------------------ */ -/* - * Wireless statistics (used for /proc/net/wireless) - */ -struct iw_statistics -{ - __u16 status; /* Status - * - device dependent for now */ - - struct iw_quality qual; /* Quality of the link - * (instant/mean/max) */ - struct iw_discarded discard; /* Packet discarded counts */ - struct iw_missed miss; /* Packet missed counts */ -}; - -/* ------------------------ IOCTL REQUEST ------------------------ */ -/* - * This structure defines the payload of an ioctl, and is used - * below. - * - * Note that this structure should fit on the memory footprint - * of iwreq (which is the same as ifreq), which mean a max size of - * 16 octets = 128 bits. Warning, pointers might be 64 bits wide... - * You should check this when increasing the structures defined - * above in this file... - */ -union iwreq_data -{ - /* Config - generic */ - char name[IFNAMSIZ]; - /* Name : used to verify the presence of wireless extensions. - * Name of the protocol/provider... */ - - struct iw_point essid; /* Extended network name */ - struct iw_param nwid; /* network id (or domain - the cell) */ - struct iw_freq freq; /* frequency or channel : - * 0-1000 = channel - * > 1000 = frequency in Hz */ - - struct iw_param sens; /* signal level threshold */ - struct iw_param bitrate; /* default bit rate */ - struct iw_param txpower; /* default transmit power */ - struct iw_param rts; /* RTS threshold threshold */ - struct iw_param frag; /* Fragmentation threshold */ - __u32 mode; /* Operation mode */ - struct iw_param retry; /* Retry limits & lifetime */ - - struct iw_point encoding; /* Encoding stuff : tokens */ - struct iw_param power; /* PM duration/timeout */ - struct iw_quality qual; /* Quality part of statistics */ - - struct sockaddr_t ap_addr; /* Access point address */ - struct sockaddr_t addr; /* Destination address (hw/mac) */ - - struct iw_param param; /* Other small parameters */ - struct iw_point data; /* Other large parameters */ - struct iw_point passphrase; /* Extended network name */ -}; - -/* - * The structure to exchange data for ioctl. - * This structure is the same as 'struct ifreq', but (re)defined for - * convenience... - * Do I need to remind you about structure size (32 octets) ? - */ -struct iwreq -{ -#if 0 - union - { - char ifrn_name[IFNAMSIZ]; /* if name, e.g. "eth0" */ - } ifr_ifrn; -#endif - char ifr_name[IFNAMSIZ]; /* if name, e.g. "eth0" */ - - /* Data part (defined just above) */ - union iwreq_data u; -}; - -/* -------------------------- IOCTL DATA -------------------------- */ -/* - * For those ioctl which want to exchange mode data that what could - * fit in the above structure... - */ - -/* - * Range of parameters - */ - -struct iw_range -{ - /* Informative stuff (to choose between different interface) */ - __u32 throughput; /* To give an idea... */ - /* In theory this value should be the maximum benchmarked - * TCP/IP throughput, because with most of these devices the - * bit rate is meaningless (overhead an co) to estimate how - * fast the connection will go and pick the fastest one. - * I suggest people to play with Netperf or any benchmark... - */ - - /* NWID (or domain id) */ - __u32 min_nwid; /* Minimal NWID we are able to set */ - __u32 max_nwid; /* Maximal NWID we are able to set */ - - /* Old Frequency (backward compat - moved lower ) */ - __u16 old_num_channels; - __u8 old_num_frequency; - - /* Wireless event capability bitmasks */ - __u32 event_capa[6]; - - /* signal level threshold range */ - __s32 sensitivity; - - /* Quality of link & SNR stuff */ - /* Quality range (link, level, noise) - * If the quality is absolute, it will be in the range [0 ; max_qual], - * if the quality is dBm, it will be in the range [max_qual ; 0]. - * Don't forget that we use 8 bit arithmetics... */ - struct iw_quality max_qual; /* Quality of the link */ - /* This should contain the average/typical values of the quality - * indicator. This should be the threshold between a "good" and - * a "bad" link (example : monitor going from green to orange). - * Currently, user space apps like quality monitors don't have any - * way to calibrate the measurement. With this, they can split - * the range between 0 and max_qual in different quality level - * (using a geometric subdivision centered on the average). - * I expect that people doing the user space apps will feedback - * us on which value we need to put in each driver... */ - struct iw_quality avg_qual; /* Quality of the link */ - - /* Rates */ - __u8 num_bitrates; /* Number of entries in the list */ - __s32 bitrate[IW_MAX_BITRATES]; /* list, in bps */ - - /* RTS threshold */ - __s32 min_rts; /* Minimal RTS threshold */ - __s32 max_rts; /* Maximal RTS threshold */ - - /* Frag threshold */ - __s32 min_frag; /* Minimal frag threshold */ - __s32 max_frag; /* Maximal frag threshold */ - - /* Power Management duration & timeout */ - __s32 min_pmp; /* Minimal PM period */ - __s32 max_pmp; /* Maximal PM period */ - __s32 min_pmt; /* Minimal PM timeout */ - __s32 max_pmt; /* Maximal PM timeout */ - __u16 pmp_flags; /* How to decode max/min PM period */ - __u16 pmt_flags; /* How to decode max/min PM timeout */ - __u16 pm_capa; /* What PM options are supported */ - - /* Encoder stuff */ - __u16 encoding_size[IW_MAX_ENCODING_SIZES]; /* Different token sizes */ - __u8 num_encoding_sizes; /* Number of entry in the list */ - __u8 max_encoding_tokens; /* Max number of tokens */ - /* For drivers that need a "login/passwd" form */ - __u8 encoding_login_index; /* token index for login token */ - - /* Transmit power */ - __u16 txpower_capa; /* What options are supported */ - __u8 num_txpower; /* Number of entries in the list */ - __s32 txpower[IW_MAX_TXPOWER]; /* list, in bps */ - - /* Wireless Extension version info */ - __u8 we_version_compiled; /* Must be WIRELESS_EXT */ - __u8 we_version_source; /* Last update of source */ - - /* Retry limits and lifetime */ - __u16 retry_capa; /* What retry options are supported */ - __u16 retry_flags; /* How to decode max/min retry limit */ - __u16 r_time_flags; /* How to decode max/min retry life */ - __s32 min_retry; /* Minimal number of retries */ - __s32 max_retry; /* Maximal number of retries */ - __s32 min_r_time; /* Minimal retry lifetime */ - __s32 max_r_time; /* Maximal retry lifetime */ - - /* Frequency */ - __u16 num_channels; /* Number of channels [0; num - 1] */ - __u8 num_frequency; /* Number of entry in the list */ - struct iw_freq freq[IW_MAX_FREQUENCIES]; /* list */ - /* Note : this frequency list doesn't need to fit channel numbers, - * because each entry contain its channel index */ - - __u32 enc_capa; /* IW_ENC_CAPA_* bit field */ - - /* More power management stuff */ - __s32 min_pms; /* Minimal PM saving */ - __s32 max_pms; /* Maximal PM saving */ - __u16 pms_flags; /* How to decode max/min PM saving */ - - /* All available modulations for driver (hw may support less) */ - __s32 modul_capa; /* IW_MODUL_* bit field */ - - /* More bitrate stuff */ - __u32 bitrate_capa; /* Types of bitrates supported */ -}; - -/* - * Private ioctl interface information - */ - -struct iw_priv_args -{ - __u32 cmd; /* Number of the ioctl to issue */ - __u16 set_args; /* Type and number of args */ - __u16 get_args; /* Type and number of args */ - char name[IFNAMSIZ]; /* Name of the extension */ -}; - -/* ----------------------- WIRELESS EVENTS ----------------------- */ -/* - * Wireless events are carried through the rtnetlink socket to user - * space. They are encapsulated in the IFLA_WIRELESS field of - * a RTM_NEWLINK message. - */ - -/* - * A Wireless Event. Contains basically the same data as the ioctl... - */ -struct iw_event -{ - __u16 len; /* Real lenght of this stuff */ - __u16 cmd; /* Wireless IOCTL */ - union iwreq_data u; /* IOCTL fixed payload */ -}; - -/* Size of the Event prefix (including padding and alignement junk) */ -#define IW_EV_LCP_LEN (sizeof(struct iw_event) - sizeof(union iwreq_data)) -/* Size of the various events */ -#define IW_EV_CHAR_LEN (IW_EV_LCP_LEN + IFNAMSIZ) -#define IW_EV_UINT_LEN (IW_EV_LCP_LEN + sizeof(__u32)) -#define IW_EV_FREQ_LEN (IW_EV_LCP_LEN + sizeof(struct iw_freq)) -#define IW_EV_PARAM_LEN (IW_EV_LCP_LEN + sizeof(struct iw_param)) -#define IW_EV_ADDR_LEN (IW_EV_LCP_LEN + sizeof(struct sockaddr_t)) -#define IW_EV_QUAL_LEN (IW_EV_LCP_LEN + sizeof(struct iw_quality)) - -/* iw_point events are special. First, the payload (extra data) come at - * the end of the event, so they are bigger than IW_EV_POINT_LEN. Second, - * we omit the pointer, so start at an offset. */ -#define IW_EV_POINT_OFF (((char *) &(((struct iw_point *) NULL)->length)) - \ - (char *) NULL) -#define IW_EV_POINT_LEN (IW_EV_LCP_LEN + sizeof(struct iw_point) - \ - IW_EV_POINT_OFF) - -/* Size of the Event prefix when packed in stream */ -#define IW_EV_LCP_PK_LEN (4) -/* Size of the various events when packed in stream */ -#define IW_EV_CHAR_PK_LEN (IW_EV_LCP_PK_LEN + IFNAMSIZ) -#define IW_EV_UINT_PK_LEN (IW_EV_LCP_PK_LEN + sizeof(__u32)) -#define IW_EV_FREQ_PK_LEN (IW_EV_LCP_PK_LEN + sizeof(struct iw_freq)) -#define IW_EV_PARAM_PK_LEN (IW_EV_LCP_PK_LEN + sizeof(struct iw_param)) -#define IW_EV_ADDR_PK_LEN (IW_EV_LCP_PK_LEN + sizeof(struct sockaddr_t)) -#define IW_EV_QUAL_PK_LEN (IW_EV_LCP_PK_LEN + sizeof(struct iw_quality)) -#define IW_EV_POINT_PK_LEN (IW_EV_LCP_LEN + 4) - -#define IW_EXT_STR_FOURWAY_DONE "WPA/WPA2 handshake done" -#define IW_EXT_STR_RECONNECTION_FAIL "RECONNECTION FAILURE" -#define IW_EVT_STR_STA_ASSOC "STA Assoc" -#define IW_EVT_STR_STA_DISASSOC "STA Disassoc" -#define IW_EVT_STR_SEND_ACTION_DONE "Send Action Done" -#define IW_EVT_STR_NO_NETWORK "No Assoc Network After Scan Done" -#define IW_EVT_STR_ICV_ERROR "ICV Eror" -#define IW_EVT_STR_CHALLENGE_FAIL "Auth Challenge Fail" -#endif /* _LINUX_WIRELESS_H */ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wlan_intf.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wlan_intf.h deleted file mode 100644 index 081447f6993..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wlan_intf.h +++ /dev/null @@ -1,82 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ -#ifndef __WLAN_INTF_H__ -#define __WLAN_INTF_H__ - -#ifdef __cplusplus -extern "C" { -#endif -#include - -#include -#include "wifi_constants.h" - -#ifndef WLAN0_IDX - #define WLAN0_IDX 0 -#endif -#ifndef WLAN1_IDX - #define WLAN1_IDX 1 -#endif -#ifndef WLAN_UNDEF - #define WLAN_UNDEF -1 -#endif - -/***********************************************************/ -/* -struct sk_buff { - // These two members must be first. - struct sk_buff *next; // Next buffer in list - struct sk_buff *prev; // Previous buffer in list - - struct sk_buff_head *list; // List we are on - unsigned char *head; // Head of buffer - unsigned char *data; // Data head pointer - unsigned char *tail; // Tail pointer - unsigned char *end; //End pointer - struct net_device *dev; //Device we arrived on/are leaving by - unsigned int len; // Length of actual data -}; -*/ -/************************************************************/ - -//----- ------------------------------------------------------------------ -// Wlan Interface opened for upper layer -//----- ------------------------------------------------------------------ -int rltk_wlan_init(int idx_wlan, rtw_mode_t mode); //return 0: success. -1:fail -void rltk_wlan_deinit(void); -void rltk_wlan_deinit_fastly(void); -int rltk_wlan_start(int idx_wlan); -void rltk_wlan_statistic(unsigned char idx); -unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down -int rltk_wlan_control(unsigned long cmd, void *data); -int rltk_wlan_handshake_done(void); -int rltk_wlan_rf_on(void); -int rltk_wlan_rf_off(void); -int rltk_wlan_check_bus(void); -int rltk_wlan_wireless_mode(unsigned char mode); -int rltk_wlan_get_wireless_mode(unsigned char *pmode); -int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps); -int rtw_ps_enable(int enable); -int rltk_wlan_is_connected_to_ap(void); - - -#ifdef __cplusplus -} -#endif - - - -#endif //#ifndef __WLAN_INTF_H__ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c deleted file mode 100644 index 13ece1aa534..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c +++ /dev/null @@ -1,1231 +0,0 @@ -/* RTX includes */ -#include "osdep_service.h" -#include "tcm_heap.h" -#include "platform_stdlib.h" - -/********************* os depended utilities ********************/ - -#ifndef USE_MUTEX_FOR_SPINLOCK -#define USE_MUTEX_FOR_SPINLOCK 1 -#endif - - -//----------------------------------------------------------------------- -// Private Variables -//----------------------------------------------------------------------- -static unsigned long CriticalNesting = 0; -#if CONFIG_USE_TCM_HEAP -void *tcm_heap_malloc(int size); -#endif -#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK) -extern int rtw_if_wifi_thread(char *name); -#endif - -//----------------------------------------------------------------------- -// Misc Function -//----------------------------------------------------------------------- -int osdep_print = 0; -#define _func_enter_ do{\ - if(osdep_print)\ - printf("enter %s\r\n", __FUNCTION__);\ - }while(0) -#define _func_exit_ do{\ - if(osdep_print)\ - printf("exit %s\r\n", __FUNCTION__);\ - }while(0) - -void save_and_cli() -{ -_func_enter_; -#if defined(__CC_ARM) - rtw_enter_critical(NULL, NULL); -#else - __disable_irq(); -#endif -_func_exit_; -} - -void restore_flags() -{ -_func_enter_; -#if defined(__CC_ARM) - rtw_exit_critical(NULL, NULL); -#else - __enable_irq(); -#endif -_func_exit_; -} - -void cli() -{ -_func_enter_; - __disable_irq(); -_func_exit_; -} - -/* Not needed on 64bit architectures */ -static unsigned int __div64_32(u64 *n, unsigned int base) -{ - u64 rem = *n; - u64 b = base; - u64 res, d = 1; - unsigned int high = rem >> 32; -_func_enter_; - /* Reduce the thing a bit first */ - res = 0; - if (high >= base) { - high /= base; - res = (u64) high << 32; - rem -= (u64) (high * base) << 32; - } - - while ((u64)b > 0 && b < rem) { - b = b+b; - d = d+d; - } - - do { - if (rem >= b) { - rem -= b; - res += d; - } - b >>= 1; - d >>= 1; - } while (d); -_func_exit_; - *n = res; - return rem; -} - -/********************* os depended service ********************/ - -static void _rtx2_memset(void *pbuf, int c, u32 sz); -u8* _rtx2_malloc(u32 sz) -{ -_func_enter_; - void *p = NULL; - p = (void *)malloc(sz); -_func_exit_; - return p; -} - -u8* _rtx2_zmalloc(u32 sz) -{ -_func_enter_; - u8 *pbuf = _rtx2_malloc(sz); - - if (pbuf != NULL){ - _rtx2_memset(pbuf, 0, sz); - } -_func_exit_; - return pbuf; -} - -static void (*ext_free)( void *p ) = NULL; -static uint32_t ext_upper = 0; -static uint32_t ext_lower = 0; -void rtw_set_mfree_ext( void (*free)( void *p ), uint32_t upper, uint32_t lower ) -{ - ext_free = free; - ext_upper = upper; - ext_lower = lower; -} - -void _rtx2_mfree(u8 *pbuf, u32 sz) -{ -_func_enter_; - if( ((uint32_t)pbuf >= ext_lower) && ((uint32_t)pbuf < ext_upper) ){ - if(ext_free) - ext_free(pbuf); - }else{ - free(pbuf); - } -} - -static void _rtx2_memcpy(void* dst, void* src, u32 sz) -{ -_func_enter_; - memcpy(dst, src, sz); -_func_exit_; -} - -static int _rtx2_memcmp(void *dst, void *src, u32 sz) -{ -_func_enter_; - //under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 - if (!(memcmp(dst, src, sz))) - return _SUCCESS; -_func_exit_; - return _FAIL; -} - -static void _rtx2_memset(void *pbuf, int c, u32 sz) -{ -_func_enter_; - memset(pbuf, c, sz); -_func_exit_; -} - -static void _rtx2_init_sema(_sema *sem, int init_val) -{ -_func_enter_; - rtx_sema_t *p_sem = (rtx_sema_t *)_rtx2_zmalloc(sizeof(rtx_sema_t)); - if(p_sem == NULL){ - goto err_exit; - } - *sem = (_sema)p_sem; - _rtx2_memset(&p_sem->data, 0, sizeof(p_sem->data)); - p_sem->attr.cb_mem = &p_sem->data; - p_sem->attr.cb_size = sizeof(p_sem->data); - p_sem->id = osSemaphoreNew(osRtxSemaphoreTokenLimit, (uint32_t)init_val, &p_sem->attr); - if (p_sem->id == NULL){ - goto err_exit; - } -_func_exit_; - return; -err_exit: - DBG_ERR("error"); - if(p_sem) - _rtx2_mfree((u8 *)p_sem, sizeof(rtx_sema_t)); - *sem = NULL; - return; -} - -static void _rtx2_free_sema(_sema *sema) -{ -_func_enter_; - if(*sema){ - rtx_sema_t *p_sem = (rtx_sema_t *)(*sema); - osSemaphoreDelete(p_sem->id); - if(p_sem) - _rtx2_mfree((u8 *)p_sem, sizeof(rtx_sema_t)); - *sema = NULL; - } else { - DBG_ERR("NULL pointer get"); - } -_func_exit_; -} - -static void _rtx2_up_sema(_sema *sema) -{ -_func_enter_; - if(*sema){ - rtx_sema_t *p_sem = (rtx_sema_t *)(*sema); - osStatus_t status = osSemaphoreRelease(p_sem->id); - if (status != osOK){ - DBG_ERR("error %d", status); - } - } else { - DBG_ERR("NULL pointer get"); - } -_func_exit_; -} - -static void _rtx2_up_sema_from_isr(_sema *sema) -{ -_func_enter_; - if(*sema){ - rtx_sema_t *p_sem = (rtx_sema_t *)*sema; - osStatus_t status = osSemaphoreRelease(p_sem->id); - if (status != osOK){ - DBG_ERR("error %d", status); - } - } else { - DBG_ERR("NULL pointer get"); - } -_func_exit_; -} - -static u32 _rtx2_down_sema(_sema *sema, u32 timeout_ms) -{ - if(*sema){ - rtx_sema_t *p_sem = (rtx_sema_t *)*sema; - if(timeout_ms == RTW_MAX_DELAY) { - timeout_ms = osWaitForever; - } else { - timeout_ms = rtw_ms_to_systime(timeout_ms); - } - osStatus_t status = osSemaphoreAcquire(p_sem->id, timeout_ms); - if (status == osOK){ - return _TRUE; - } - } - return _FALSE; -} - -static void _rtx2_mutex_init(_mutex *mutex) -{ -_func_enter_; - rtx_mutex_t *p_mut = (rtx_mutex_t *)_rtx2_zmalloc(sizeof(rtx_mutex_t)); - if(p_mut == NULL) - goto err_exit; - memset(&p_mut->data, 0, sizeof(p_mut->data)); - p_mut->attr.cb_mem = &p_mut->data; - p_mut->attr.cb_size = sizeof(p_mut->data); - p_mut->id = osMutexNew(&p_mut->attr); - if (p_mut->id == NULL) - goto err_exit; - *mutex = (_mutex)p_mut; -_func_exit_; - return; -err_exit: - DBG_ERR("error"); - if(p_mut) - _rtx2_mfree((u8 *)p_mut, sizeof(rtx_mutex_t)); - *mutex = NULL; - return; -} - -static void _rtx2_mutex_free(_mutex *pmutex) -{ -_func_enter_; - if(*pmutex){ - rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex); - osMutexDelete(p_mut->id); - if(p_mut) - _rtx2_mfree((u8 *)p_mut, sizeof(rtx_mutex_t)); - } -_func_exit_; -} - -static void _rtx2_mutex_get(_mutex *pmutex) -{ -_func_enter_; - if(*pmutex){ - rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex); - if (osMutexAcquire(p_mut->id, 60 * 1000 / OS_TICK_RATE_MS) != osOK) - DBG_ERR("%s(%p) failed, retry\n", __FUNCTION__, p_mut); - } -_func_exit_; -} - -static int _rtx2_mutex_get_timeout(_mutex *pmutex, u32 timeout_ms) -{ -_func_enter_; - if(*pmutex){ - rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex); - if(timeout_ms == RTW_MAX_DELAY) { - timeout_ms = osWaitForever; - } else { - timeout_ms = rtw_ms_to_systime(timeout_ms); - } - if(osMutexAcquire(p_mut->id, timeout_ms) == osOK){ - return _SUCCESS; - } - } -_func_exit_; - DBG_ERR("%s(%p) failed, retry\n", __FUNCTION__, pmutex); - return _FAIL; -} - -static void _rtx2_mutex_put(_mutex *pmutex) -{ -_func_enter_; - if(*pmutex){ - rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex); - if (osMutexRelease(p_mut->id) != osOK) - DBG_ERR("\r\ninternal counter of mutex is 0 or calling task is not the owner of the mutex"); - } -_func_exit_; -} - -static void _rtx2_enter_critical(_lock *plock, _irqL *pirqL) -{ -_func_enter_; - CriticalNesting++; - if(CriticalNesting == 1){ - osKernelLock();//tsk_lock & tsk_unlock should not be called nested - } -_func_exit_; -} - -void mbed_die(void){ - DBG_ERR(" %p die here", osThreadGetId()); - __disable_irq(); - while(1); -} - -static void _rtx2_exit_critical(_lock *plock, _irqL *pirqL) -{ -_func_enter_; - if(CriticalNesting == 0){ - DBG_ERR("die here"); - HALT(); - } - CriticalNesting--; - if(CriticalNesting == 0){ - osKernelUnlock(); - } -_func_exit_; -} - -static void _rtx2_enter_critical_from_isr(_lock *plock, _irqL *pirqL) -{ -_func_enter_; - __disable_irq(); -_func_exit_; -} - -static void _rtx2_exit_critical_from_isr(_lock *plock, _irqL *pirqL) -{ -_func_enter_; - __enable_irq(); -_func_exit_; -} - -static int _rtx2_enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ -_func_enter_; - while(_rtx2_mutex_get_timeout(pmutex, 60 * 1000) != _SUCCESS) - DBG_ERR("\n\r[%p] %s(%p) failed, retry\n", osThreadGetId(), __FUNCTION__, pmutex); -_func_exit_; - return _SUCCESS; -} - -static void _rtx2_exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ -_func_enter_; - _rtx2_mutex_put(pmutex); -_func_exit_; -} - -static void _rtx2_cpu_lock(void) -{ -_func_enter_; - printf(" Not yet ready. Should not come over here!\r\n"); -_func_exit_; -} -static void _rtx2_cpu_unlock(void) -{ -_func_enter_; - printf(" Not yet ready. Should not come over here!\r\n"); -_func_exit_; -} - -static void _rtx2_spinlock_init(_lock *plock) -{ -_func_enter_; -#if USE_MUTEX_FOR_SPINLOCK - _rtx2_mutex_init(plock); -#endif -_func_exit_; -} - -static void _rtx2_spinlock_free(_lock *plock) -{ -_func_enter_; -#if USE_MUTEX_FOR_SPINLOCK - if(plock != NULL){ - _rtx2_mutex_free(plock); - } -#endif -_func_exit_; -} - -static void _rtx2_spinlock(_lock *plock) -{ -_func_enter_; -#if USE_MUTEX_FOR_SPINLOCK - _rtx2_mutex_get(plock); -#endif -_func_exit_; -} - -static void _rtx2_spinunlock(_lock *plock) -{ -_func_enter_; -#if USE_MUTEX_FOR_SPINLOCK - _rtx2_mutex_put(plock); -#endif -_func_exit_; -} - -static void _rtx2_spinlock_irqsave(_lock *plock, _irqL *irqL) -{ -_func_enter_; - _rtx2_enter_critical(plock, irqL); -#if USE_MUTEX_FOR_SPINLOCK - _rtx2_spinlock(plock); -#endif -_func_exit_; -} - -static void _rtx2_spinunlock_irqsave(_lock *plock, _irqL *irqL) -{ -_func_enter_; -#if USE_MUTEX_FOR_SPINLOCK - _rtx2_spinunlock(plock); -#endif - _rtx2_exit_critical(plock, irqL); -_func_exit_; -} - -static int _rtx2_init_xqueue( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages ) -{ -_func_enter_; - rtx_mbox_t *mbox = (rtx_mbox_t *)_rtx2_zmalloc(sizeof(rtx_mbox_t)); - if (mbox == NULL ){ - goto err_exit; - } - mbox->queue_mem = _rtx2_zmalloc(number_of_messages * (message_size + sizeof(os_message_t))); - if(mbox->queue_mem == NULL) - goto err_exit; - mbox->attr.mq_mem = mbox->queue_mem; - mbox->attr.mq_size = number_of_messages * (message_size + sizeof(os_message_t)); - mbox->attr.cb_mem = &mbox->data; - mbox->attr.cb_size = sizeof(mbox->data); - *queue = (_xqueue)mbox; - mbox->id = osMessageQueueNew(number_of_messages, message_size, &mbox->attr); - if(mbox->id == NULL) - goto err_exit; - -_func_exit_; - return _SUCCESS; -err_exit: - DBG_ERR("%s error\r\n", __FUNCTION__); - if(mbox){ - if(mbox->queue_mem) - _rtx2_mfree(mbox->queue_mem, number_of_messages * (message_size + sizeof(os_message_t))); - _rtx2_mfree((u8 *)mbox, sizeof(rtx_mbox_t)); - *queue = NULL; - } - return _FAIL; -} - -static int _rtx2_push_to_xqueue( _xqueue* queue, void* message, u32 timeout_ms ) -{ -_func_enter_; - rtx_mbox_t *mbox; - if(timeout_ms == RTW_MAX_DELAY) { - timeout_ms = osWaitForever; - } else { - timeout_ms = rtw_ms_to_systime(timeout_ms); - } - - if (*queue != NULL){ - mbox = (rtx_mbox_t *)(*queue); - if(osMessageQueuePut(mbox->id, message, 0, timeout_ms) != osOK ){ - DBG_ERR("%s error\n", __FUNCTION__); - return _FAIL; - } - } -_func_exit_; - return _SUCCESS; -} - -static int _rtx2_pop_from_xqueue( _xqueue* queue, void* message, u32 timeout_ms ) -{ -_func_enter_; - if(timeout_ms == RTW_WAIT_FOREVER) { - timeout_ms = osWaitForever; - } else { - timeout_ms = rtw_ms_to_systime(timeout_ms); - } - if (*queue != NULL){ - rtx_mbox_t *mbox = (rtx_mbox_t *)(*queue); - osStatus_t res = osMessageQueueGet(mbox->id, message, NULL, timeout_ms); - if (res == osOK) { -_func_exit_; - return _SUCCESS; - } - } - - DBG_ERR("[%p] %s error", osThreadGetId(), __FUNCTION__); -_func_exit_; - return _FAIL; -} - -static int _rtx2_deinit_xqueue( _xqueue* queue ) -{ -_func_enter_; - if(*queue != NULL){ - rtx_mbox_t *mbox = (rtx_mbox_t *)(*queue); - if(mbox->queue_mem) - _rtx2_mfree(mbox->queue_mem, mbox->attr.mq_size); - _rtx2_mfree((u8 *)mbox, sizeof(rtx_mbox_t)); - *queue = NULL; - } -_func_exit_; - return 0; -} - -static u32 _rtx2_get_current_time(void) -{ - return osKernelGetSysTimerCount(); -} - -static u32 _rtx2_systime_to_ms(u32 systime) -{ - return systime * OS_TICK_RATE_MS; -} - -static u32 _rtx2_systime_to_sec(u32 systime) -{ - return systime / OS_TICK; -} - -static u32 _rtx2_ms_to_systime(u32 ms) -{ - return ms / OS_TICK_RATE_MS; -} - -static u32 _rtx2_sec_to_systime(u32 sec) -{ - return sec * OS_TICK; -} - -static void _rtx2_msleep_os(int ms) -{ -_func_enter_; - osDelay(_rtx2_ms_to_systime(ms)); -_func_exit_; -} - -static void _rtx2_usleep_os(int us) -{ -_func_enter_; -#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F10X_XL) - // FreeRTOS does not provide us level delay. Use busy wait - WLAN_BSP_UsLoop(us); -#elif defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) - //DBG_ERR("%s: Please Implement micro-second delay\n", __FUNCTION__); - HalDelayUs(us); -#else - // #error "Please implement hardware dependent micro second level sleep here" -#endif -_func_exit_; -} - -static void _rtx2_mdelay_os(int ms) -{ -_func_enter_; - osDelay(_rtx2_ms_to_systime(ms)); -_func_exit_; -} - -static void _rtx2_udelay_os(int us) -{ -_func_enter_; -#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F10X_XL) - // FreeRTOS does not provide us level delay. Use busy wait - WLAN_BSP_UsLoop(us); -#elif defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) - //RtlUdelayOS(us); - HalDelayUs(us); -#else - // #error "Please implement hardware dependent micro second level sleep here" -#endif -_func_exit_; -} - -static void _rtx2_yield_os(void) -{ -_func_enter_; - osThreadYield(); -_func_exit_; -} - -static void _rtx2_ATOMIC_SET(ATOMIC_T *v, int i) -{ - atomic_set(v,i); -} - -static int _rtx2_ATOMIC_READ(ATOMIC_T *v) -{ - return atomic_read(v); -} - -static void _rtx2_ATOMIC_ADD(ATOMIC_T *v, int i) -{ - save_and_cli(); - v->counter += i; - restore_flags(); -} - -static void _rtx2_ATOMIC_SUB(ATOMIC_T *v, int i) -{ - save_and_cli(); - v->counter -= i; - restore_flags(); -} - -static void _rtx2_ATOMIC_INC(ATOMIC_T *v) -{ - save_and_cli(); - v->counter++; - restore_flags(); -} - -static void _rtx2_ATOMIC_DEC(ATOMIC_T *v) -{ - save_and_cli(); - v->counter--; - restore_flags(); -} - -static int _rtx2_ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) -{ - int temp; - - save_and_cli(); - temp = v->counter; - temp += i; - v->counter = temp; - restore_flags(); - - return temp; -} - -static int _rtx2_ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) -{ - int temp; - - save_and_cli(); - temp = v->counter; - temp -= i; - v->counter = temp; - restore_flags(); - - return temp; -} - -static int _rtx2_ATOMIC_INC_RETURN(ATOMIC_T *v) -{ - return _rtx2_ATOMIC_ADD_RETURN(v, 1); -} - -static int _rtx2_ATOMIC_DEC_RETURN(ATOMIC_T *v) -{ - return _rtx2_ATOMIC_SUB_RETURN(v, 1); -} - -static u64 _rtx2_modular64(u64 n, u64 base) -{ - unsigned int __base = (base); - unsigned int __rem; -_func_enter_; - if (((n) >> 32) == 0) { - __rem = (unsigned int)(n) % __base; - (n) = (unsigned int)(n) / __base; - } else { - __rem = __div64_32(&(n), __base); - } -_func_exit_; - return __rem; -} - -/* Refer to ecos bsd tcpip codes */ -static int _rtx2_arc4random(void) -{ -_func_enter_; - u32 res = _rtx2_get_current_time(); - static unsigned long seed = 0xDEADB00B; - seed = ((seed & 0x007F00FF) << 7) ^ - ((seed & 0x0F80FF00) >> 8) ^ // be sure to stir those low bits - (res << 13) ^ (res >> 9); // using the clock too! -_func_exit_; - return (int)seed; -} - -static int _rtx2_get_random_bytes(void *buf, u32 len) -{ - unsigned int ranbuf; - unsigned int *lp; - int i, count; - count = len / sizeof(unsigned int); - lp = (unsigned int *) buf; -_func_enter_; - for(i = 0; i < count; i ++) { - lp[i] = _rtx2_arc4random(); - len -= sizeof(unsigned int); - } - - if(len > 0) { - ranbuf = _rtx2_arc4random(); - _rtx2_memcpy(&lp[i], &ranbuf, len); - } -_func_exit_; - return 0; -} - -static u32 _rtx2_GetFreeHeapSize(void) -{ - //TODO - return 0; -} - -/* Convert from wlan priority number to CMSIS type osPriority */ -static osPriority_t make_cmsis_priority (u32 fpriority) -{ - osPriority_t priority = (osPriority_t)fpriority; - priority += osPriorityHigh; - return priority; -} - -static int _rtx2_create_task(struct task_struct *ptask, const char *name, - u32 stack_size, u32 priority, thread_func_t func, void *thctx) -{ -_func_enter_; - rtx_thread_data_t *thread_hdl = NULL; - u32 stacksize = stack_size * 4; //sizeof(DWORD) - u8 *(*_customized_malloc)( u32 size ) = _rtx2_malloc; - u8 *(*_customized_zmalloc)( u32 size ) = _rtx2_zmalloc; - if(!func) - goto err_exit; -#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK) - if(rtw_if_wifi_thread((char *)name) == 0){ - priority = make_cmsis_priority(priority); - _customized_malloc = _rtw_vmalloc; - _customized_zmalloc = _rtw_zvmalloc; - } -#endif - thread_hdl = (rtx_thread_data_t *)_customized_zmalloc(sizeof(rtx_thread_data_t)); - if(thread_hdl == NULL) - goto err_exit; - if(priority > osPriorityRealtime){ - DBG_ERR("[%s]priority is higher than osPriorityRealtime", name); - priority = osPriorityRealtime; - } - thread_hdl->attr.name = name; - thread_hdl->attr.priority = (osPriority_t)priority; - thread_hdl->attr.cb_size = sizeof(thread_hdl->data); - thread_hdl->attr.cb_mem = &thread_hdl->data; - thread_hdl->attr.stack_size = stacksize; - thread_hdl->attr.stack_mem = (void *)_customized_malloc(stacksize); - if (thread_hdl->attr.stack_mem == NULL) { - DBG_ERR("[%s] malloc failed", name); - goto err_exit; - } - - ptask->task = (_thread_hdl_)thread_hdl; - ptask->task_name = name; - ptask->blocked = 0; - ptask->callback_running = 0; - - _rtx2_init_sema(&ptask->wakeup_sema, 0); - _rtx2_init_sema(&ptask->terminate_sema, 0); - //rtw_init_queue(&wq->work_queue); - - thread_hdl->id = osThreadNew((osThreadFunc_t)func, thctx, &thread_hdl->attr); - if (thread_hdl->id == NULL) { - DBG_ERR("[%s] osThreadNew failed", name); - goto err_exit; - } - return _SUCCESS; -err_exit: - if(thread_hdl){ - _rtx2_free_sema(&ptask->wakeup_sema); - _rtx2_free_sema(&ptask->terminate_sema); - _rtx2_memset((u8 *)ptask, 0, sizeof(*ptask)); - if(thread_hdl->attr.stack_mem) - _rtx2_mfree((void *)thread_hdl->attr.stack_mem, thread_hdl->attr.stack_size); - _rtx2_mfree((u8 *)thread_hdl, sizeof(rtx_thread_data_t)); - } - DBG_ERR("Create Task \"%s\" Failed! \n", name); - return _FAIL; -} - -static void _rtx2_delete_task(struct task_struct *ptask) -{ -_func_enter_; - rtx_thread_data_t *thread_hdl = (rtx_thread_data_t *)ptask->task; - if (!thread_hdl){ - DBG_ERR("_rtx2_delete_task(): ptask is NULL!\n"); - return; - } - - ptask->blocked = 1; - - _rtx2_up_sema(&ptask->wakeup_sema); - _rtx2_down_sema(&ptask->terminate_sema, TIMER_MAX_DELAY); - - osThreadTerminate(thread_hdl->id); - if(thread_hdl->attr.stack_mem) - _rtx2_mfree((void *)thread_hdl->attr.stack_mem, thread_hdl->attr.stack_size); - _rtx2_mfree((u8 *)thread_hdl, sizeof(rtx_thread_data_t)); - - //rtw_deinit_queue(&wq->work_queue); - _rtx2_free_sema(&ptask->wakeup_sema); - _rtx2_free_sema(&ptask->terminate_sema); - - ptask->task = NULL; - - DBG_TRACE("Delete Task \"%s\"\n", ptask->task_name); -_func_exit_; -} - -void _rtx2_wakeup_task(struct task_struct *ptask) -{ -_func_enter_; - if(ptask) - _rtx2_up_sema(&ptask->wakeup_sema); -_func_exit_; -} - -static void _rtx2_thread_enter(char *name) -{ -_func_enter_; - DBG_INFO("\n\rRTKTHREAD %s\n", name); -_func_exit_; -} - -static void _rtx2_thread_exit(void) -{ -_func_enter_; - osThreadExit(); -} - -/***************************************************** -************timer data block, defined in rt_CMSIS.c********* - -// Timer definitions -#define osTimerInvalid 0 -#define osTimerStopped 1 -#define osTimerRunning 2 - -// Timer structures - -typedef struct os_timer_cb_ { // Timer Control Block - struct os_timer_cb_ *next; // Pointer to next active Timer, (u8 *)data[0:3] - uint8_t state; // Timer State, (u8 *)data[4] - uint8_t type; // Timer Type (Periodic/One-shot), (u8 *)data[5] - uint16_t reserved; // Reserved, (u8 *)data[6:7] - uint16_t tcnt; // Timer Delay Count, (u8 *)data[8:9] - uint16_t icnt; // Timer Initial Count, (u8 *)data[10:11] - void *arg; // Timer Function Argument, (u8 *)data[12:15] - osTimerDef_t *timer; // Pointer to Timer definition, (u8 *)data[16:19] -} os_timer_cb; -*****************************************************/ -_timerHandle _rtx2_timerCreate( const signed char *pcTimerName, - osdepTickType xTimerPeriodInTicks, - u32 uxAutoReload, - void * pvTimerID, - TIMER_FUN pxCallbackFunction ) -{ -_func_enter_; - rtx_tmr_t *tmr = (rtx_tmr_t *)_rtx2_zmalloc(sizeof(rtx_tmr_t)); - osTimerType_t type = (uxAutoReload == _TRUE)?osTimerPeriodic:osTimerOnce; - if(tmr == NULL) - goto err_exit; - - tmr->attr.name = (const char *)pcTimerName; - tmr->attr.cb_mem = (void *)&tmr->data; - tmr->attr.cb_size = sizeof(tmr->data); - if(pvTimerID == NULL) - pvTimerID = (void *)tmr; - tmr->id = osTimerNew(pxCallbackFunction, type, pvTimerID, &tmr->attr); - if(tmr->id == NULL) - goto err_exit; - -_func_exit_; - return (_timerHandle)tmr; -err_exit: - DBG_ERR("error"); - if(tmr) - _rtx2_mfree((u8 *)tmr, sizeof(rtx_tmr_t)); - return NULL; -} - -u32 _rtx2_timerDelete(_timerHandle xTimer, - osdepTickType xBlockTime) -{ -_func_enter_; - rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer; - osStatus_t status = osTimerDelete(tmr->id); - _rtx2_mfree((u8 *)tmr, sizeof(rtx_tmr_t)); - if(status != osOK){ - DBG_ERR("error %d", status); - return _FAIL; - } -_func_exit_; - return _SUCCESS; -} - -u32 _rtx2_timerIsTimerActive(_timerHandle xTimer) -{ -_func_enter_; - rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer; - if (osTimerIsRunning(tmr->id)) { - return _TRUE; - } - return _FALSE; -} - -u32 _rtx2_timerStop(_timerHandle xTimer, - osdepTickType xBlockTime) -{ -_func_enter_; - rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer; - if(_rtx2_timerIsTimerActive(xTimer) == _TRUE){ - osStatus_t status = osTimerStop(tmr->id); - if(status != osOK){ - DBG_ERR("error %d\n", status); -_func_exit_; - return _FAIL; - } - } -_func_exit_; - return _SUCCESS; -} - -u32 _rtx2_timerChangePeriod(_timerHandle xTimer, - osdepTickType xNewPeriod, - osdepTickType xBlockTime) -{ -_func_enter_; - rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer; - osStatus_t ret; - - if(xNewPeriod == 0) - xNewPeriod += 1; - //xNewPeriod = _rtx2_systime_to_ms(xNewPeriod); - ret = osTimerStart(tmr->id, xNewPeriod); -_func_exit_; - if(ret == osOK) - return _SUCCESS; - - DBG_ERR("%s error\n", __FUNCTION__); - return _FAIL; -} - -void *_rtx2_timerGetID(_timerHandle xTimer) -{ - DBG_ERR("%s: Not implemented yet\n", __FUNCTION__); - return NULL; -} - -u32 _rtx2_timerStart(_timerHandle xTimer, - osdepTickType xBlockTime) -{ - DBG_ERR("%s: Not implemented yet\n", __FUNCTION__); - return _FAIL; -} - -u32 _rtx2_timerStartFromISR(_timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken) -{ - DBG_ERR("%s: Not implemented yet\n", __FUNCTION__); - return _FAIL; -} - -u32 _rtx2_timerStopFromISR(_timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken) -{ - DBG_ERR("%s: Not implemented yet\n", __FUNCTION__); - return _FAIL; -} - -u32 _rtx2_timerResetFromISR(_timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken) -{ - DBG_ERR("%s: Not implemented yet\n", __FUNCTION__); - return _FAIL; -} - -u32 _rtx2_timerChangePeriodFromISR(_timerHandle xTimer, - osdepTickType xNewPeriod, - osdepBASE_TYPE *pxHigherPriorityTaskWoken) -{ - if(xNewPeriod == 0) - xNewPeriod += 1; - DBG_ERR("%s: Not implemented yet\n", __FUNCTION__); - return _FAIL; -} - -u32 _rtx2_timerReset(_timerHandle xTimer, - osdepTickType xBlockTime) -{ - DBG_ERR("%s: Not implemented yet\n", __FUNCTION__); - return _FAIL; -} - -void _rtx2_acquire_wakelock() -{ - //TODO - return; -} - -void _rtx2_release_wakelock() -{ - //TODO - return; -} - -void _rtx2_wakelock_timeout(uint32_t timeout) -{ - //TODO - return; -} - -u8 _rtx2_get_scheduler_state(void) -{ -_func_enter_; - osKernelState_t state = osKernelGetState(); - u8 state_out = OS_SCHEDULER_NOT_STARTED; - switch(state){ - case osKernelRunning: - state_out = OS_SCHEDULER_RUNNING; - break; - case osKernelSuspended: - state_out = OS_SCHEDULER_SUSPENDED; - break; - default: - break; - } -_func_exit_; - return state_out; -} - -const struct osdep_service_ops osdep_service = { - _rtx2_malloc, //rtw_vmalloc - _rtx2_zmalloc, //rtw_zvmalloc - _rtx2_mfree, //rtw_vmfree - _rtx2_malloc, //rtw_malloc - _rtx2_zmalloc, //rtw_zmalloc - _rtx2_mfree, //rtw_mfree - _rtx2_memcpy, //rtw_memcpy - _rtx2_memcmp, //rtw_memcmp - _rtx2_memset, //rtw_memset - _rtx2_init_sema, //rtw_init_sema - _rtx2_free_sema, //rtw_free_sema - _rtx2_up_sema, //rtw_up_sema - _rtx2_up_sema_from_isr, //rtw_up_sema_from_isr - _rtx2_down_sema, //rtw_down_timeout_sema - _rtx2_mutex_init, //rtw_mutex_init - _rtx2_mutex_free, //rtw_mutex_free - _rtx2_mutex_get, //rtw_mutex_get - _rtx2_mutex_get_timeout, //rtw_mutex_get_timeout - _rtx2_mutex_put, //rtw_mutex_put - _rtx2_enter_critical, //rtw_enter_critical - _rtx2_exit_critical, //rtw_exit_critical - _rtx2_enter_critical_from_isr, //rtw_enter_critical_from_isr - _rtx2_exit_critical_from_isr, //rtw_exit_critical_from_isr - NULL, //rtw_enter_critical_bh - NULL, //rtw_exit_critical_bh - _rtx2_enter_critical_mutex, //rtw_enter_critical_mutex - _rtx2_exit_critical_mutex, //rtw_exit_critical_mutex - _rtx2_cpu_lock, //rtw_cpu_lock - _rtx2_cpu_unlock, //rtw_cpu_unlock - _rtx2_spinlock_init, //rtw_spinlock_init - _rtx2_spinlock_free, //rtw_spinlock_free - _rtx2_spinlock, //rtw_spin_lock - _rtx2_spinunlock, //rtw_spin_unlock - _rtx2_spinlock_irqsave, //rtw_spinlock_irqsave - _rtx2_spinunlock_irqsave, //rtw_spinunlock_irqsave - _rtx2_init_xqueue, //rtw_init_xqueue - _rtx2_push_to_xqueue, //rtw_push_to_xqueue - _rtx2_pop_from_xqueue, //rtw_pop_from_xqueue - _rtx2_deinit_xqueue, //rtw_deinit_xqueue - _rtx2_get_current_time, //rtw_get_current_time - _rtx2_systime_to_ms, //rtw_systime_to_ms - _rtx2_systime_to_sec, //rtw_systime_to_sec - _rtx2_ms_to_systime, //rtw_ms_to_systime - _rtx2_sec_to_systime, //rtw_sec_to_systime - _rtx2_msleep_os, //rtw_msleep_os - _rtx2_usleep_os, //rtw_usleep_os - _rtx2_mdelay_os, //rtw_mdelay_os - _rtx2_udelay_os, //rtw_udelay_os - _rtx2_yield_os, //rtw_yield_os - - _rtx2_ATOMIC_SET, //ATOMIC_SET - _rtx2_ATOMIC_READ, //ATOMIC_READ - _rtx2_ATOMIC_ADD, //ATOMIC_ADD - _rtx2_ATOMIC_SUB, //ATOMIC_SUB - _rtx2_ATOMIC_INC, //ATOMIC_INC - _rtx2_ATOMIC_DEC, //ATOMIC_DEC - _rtx2_ATOMIC_ADD_RETURN, //ATOMIC_ADD_RETURN - _rtx2_ATOMIC_SUB_RETURN, //ATOMIC_SUB_RETURN - _rtx2_ATOMIC_INC_RETURN, //ATOMIC_INC_RETURN - _rtx2_ATOMIC_DEC_RETURN, //ATOMIC_DEC_RETURN - - _rtx2_modular64, //rtw_modular64 - _rtx2_get_random_bytes, //rtw_get_random_bytes - _rtx2_GetFreeHeapSize, //rtw_getFreeHeapSize - - _rtx2_create_task, //rtw_create_task - _rtx2_delete_task, //rtw_delete_task - _rtx2_wakeup_task, //rtw_wakeup_task - - _rtx2_thread_enter, //rtw_thread_enter - _rtx2_thread_exit, //rtw_thread_exit - - _rtx2_timerCreate, //rtw_timerCreate - _rtx2_timerDelete, //rtw_timerDelete - _rtx2_timerIsTimerActive, //rtw_timerIsTimerActive - _rtx2_timerStop, //rtw_timerStop - _rtx2_timerChangePeriod, //rtw_timerChangePeriod - _rtx2_timerGetID, //rtw_timerGetID - _rtx2_timerStart, //rtw_timerStart - _rtx2_timerStartFromISR, //rtw_timerStartFromISR - _rtx2_timerStopFromISR, //rtw_timerStopFromISR - _rtx2_timerResetFromISR, //rtw_timerResetFromISR - _rtx2_timerChangePeriodFromISR, //rtw_timerChangePeriodFromISR - _rtx2_timerReset, //rtw_timerReset - - _rtx2_acquire_wakelock, //rtw_acquire_wakelock - _rtx2_release_wakelock, //rtw_release_wakelock - _rtx2_wakelock_timeout, //rtw_wakelock_timeout - _rtx2_get_scheduler_state //rtw_get_scheduler_state -}; - -/* -* Below block is to remove the compilation error of ARMCC -**/ -HAL_CUT_B_RAM_DATA_SECTION -_WEAK unsigned int rand_x = 123456789; - -_WEAK u8* RtlZmalloc(u32 sz) -{ - u8 *pbuf; - - pbuf= rtw_malloc(sz); - - if (pbuf != NULL) { - _memset(pbuf, 0, sz); - } - - return pbuf; -} - -_WEAK void RtlMfree(u8 *pbuf, u32 sz) -{ - rtw_mfree(pbuf, sz); -} - -_WEAK void UartLogIrqHandleRam(void * Data) -{ - printf("%s: Should not come over here!\r\n", __func__); -} - -_WEAK void vPortSVCHandler(void) -{ - printf("%s: Should not come over here!\r\n", __func__); -} - -_WEAK void xPortPendSVHandler(void) -{ - printf("%s: Should not come over here!\r\n", __func__); -} - -_WEAK void xPortSysTickHandler(void) -{ - printf("%s: Should not come over here!\r\n", __func__); -} - -_WEAK u8 *__ram_start_table_start__; - -_WEAK void rtw_odm_acquirespinlock(void * adapter, int type) -{ - printf("%s: Should not come over here!\r\n", __func__); -} - -_WEAK void rtw_odm_releasespinlock(void * adapter, int type) -{ - printf("%s: Should not come over here!\r\n", __func__); -} - -_WEAK void ROM_WIFI_BSSID_SET(u8 iface_type, u8 variable, u8 *val) -{ - printf("%s: Should not come over here!\r\n", __func__); -} - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.h deleted file mode 100644 index ff7a4ef7ad9..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.h +++ /dev/null @@ -1,288 +0,0 @@ -#ifndef _CMSIS_RTOS_SERVICE_H_ -#define _CMSIS_RTOS_SERVICE_H_ - -//----------------------------------------------------------------------- -// Include Files -//----------------------------------------------------------------------- -//#include "wireless.h" -#include "dlist.h" -#include -#include "RTX_Config.h" -#include "rtx_lib.h" -// -------------------------------------------- -// Platform dependent include file -// -------------------------------------------- -#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8195BHP) -#include "platform/platform_stdlib.h" -extern VOID RtlUdelayOS(u32 us); -#elif defined(CONFIG_PLATFORM_8711B) -#include "platform/platform_stdlib.h" -#elif defined(CONFIG_PLATFORM_8721D) -#include "platform/platform_stdlib.h" -#elif defined(CONFIG_HARDWARE_8821C) -#include "basic_types.h" -#include "wlan_basic_types.h" -#elif defined(CONFIG_HARDWARE_8188F) -#include "platform/platform_stdlib.h" -#elif defined(CONFIG_HARDWARE_8192E) -#include "platform/platform_stdlib.h" -#elif defined(CONFIG_HARDWARE_8723D) -#include "platform/platform_stdlib.h" -#else -// other MCU may use standard library -#include -#endif - - -#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI) || defined(CONFIG_LX_HCI) -/* For SPI interface transfer and us delay implementation */ -#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) && !defined(CONFIG_PLATFORM_8721D) && !defined(CONFIG_PLATFORM_8195BHP) -#include -#endif -#endif - - -// -------------------------------------------- -// Platform dependent type define -// -------------------------------------------- -#define OS_TICK OS_TICK_FREQ -#define OS_TICK_RATE_MS (1000/OS_TICK) - -// === SEMAPHORE === -typedef struct { - osSemaphoreId_t id; - osSemaphoreAttr_t attr; - os_semaphore_t data; -} rtx_sema_t; - -// === THREAD === -typedef struct { - osThreadId_t id; - osThreadAttr_t attr; - os_thread_t data; -} rtx_thread_data_t; - -// === MUTEX === -typedef struct { - osMutexId_t id; - osMutexAttr_t attr; - os_mutex_t data; -} rtx_mutex_t; - -// === MAIL BOX === -#define RTX_MB_SIZE 8 - -typedef struct { - osEventFlagsId_t id; - osEventFlagsAttr_t attr; - os_event_flags_t data; - - uint8_t post_idx; - uint8_t fetch_idx; - void* queue[RTX_MB_SIZE]; -} rtx_mqueue_t; - -typedef struct { - osMessageQueueId_t id; - osMessageQueueAttr_t attr; - void *queue_mem; - os_message_queue_t data; -} rtx_mbox_t; - -typedef struct{ - osTimerId_t id; - osTimerAttr_t attr; - os_timer_t data; -} rtx_tmr_t; - -#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) - -// os types -typedef char osdepCHAR; -typedef float osdepFLOAT; -typedef double osdepDOUBLE; -typedef long osdepLONG; -typedef short osdepSHORT; -typedef unsigned long osdepSTACK_TYPE; -typedef long osdepBASE_TYPE; -typedef unsigned long osdepTickType; - -typedef void * _timerHandle; -typedef void * _sema; -typedef void * _mutex; -typedef void * _lock; -typedef void * _queueHandle; -typedef void * _xqueue; -typedef struct timer_list _timer; - -typedef struct sk_buff _pkt; -typedef unsigned char _buffer; -typedef unsigned int systime; - -#ifndef __LIST_H -#warning "DLIST_NOT_DEFINE!!!!!!" -struct list_head { - struct list_head *next, *prev; -}; -#endif - -struct __queue { - struct list_head queue; - _lock lock; -}; - -typedef struct __queue _queue; -typedef struct list_head _list; -typedef unsigned long _irqL; - -typedef void* _thread_hdl_; -typedef void thread_return; -typedef void* thread_context; - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_T atomic_t -#define HZ configTICK_RATE_HZ - -#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -/* emulate a modern version */ -#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 17) - -static __inline _list *get_next(_list *list) -{ - return list->next; -} - -static __inline _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)((char *)&((type *)ptr)->member - (char *)ptr))) -//#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) -#define container_of(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) -#define TASK_PRORITY_LOW 1 -#define TASK_PRORITY_MIDDLE 2 -#define TASK_PRORITY_HIGH 3 -#define TASK_PRORITY_SUPER 4 -#define PRIORITIE_OFFSET 4 - -#define TIMER_MAX_DELAY 0xFFFFFFFF - -void save_and_cli(void); -void restore_flags(void); -void cli(void); - -#ifndef mdelay -#define mdelay(t) ((t/OS_TICK_RATE_MS)>0)?(osDelay(t/OS_TICK_RATE_MS)):(osDelay(1)) -#endif - -#ifndef udelay -#define udelay(t) ((t/(OS_TICK_RATE_MS*1000))>0)?osDelay(t/(OS_TICK_RATE_MS*1000)):(osDelay(1)) -#endif -//----- ------------------------------------------------------------------ -// Common Definition -//----- ------------------------------------------------------------------ - -#define __init -#define __exit -#define __devinit -#define __devexit - -#define KERN_ERR -#define KERN_INFO -#define KERN_NOTICE - -#undef GFP_KERNEL -#define GFP_KERNEL 1 -#define GFP_ATOMIC 1 - -#define SET_MODULE_OWNER(some_struct) do { } while (0) -#define SET_NETDEV_DEV(dev, obj) do { } while (0) -#define register_netdev(dev) (0) -#define unregister_netdev(dev) do { } while (0) -#define netif_queue_stopped(dev) (0) -#define netif_wake_queue(dev) do { } while (0) -#define printk printf - -#define DBG_ERR(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args) -#if WLAN_INTF_DBG -#define DBG_TRACE(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args) -#define DBG_INFO(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args) -#else -#define DBG_TRACE(fmt, args...) -#define DBG_INFO(fmt, args...) -#endif -#define HALT() do { cli(); for(;;);} while(0) -#undef ASSERT -#define ASSERT(x) do { \ - if((x) == 0){\ - printf("\n\rAssert(" #x ") failed on line %d in file %s", __LINE__, __FILE__); \ - HALT();}\ - } while(0) - -#undef DBG_ASSERT -#define DBG_ASSERT(x, msg) do { \ - if((x) == 0) \ - printf("\n\r%s, Assert(" #x ") failed on line %d in file %s", msg, __LINE__, __FILE__); \ - } while(0) - -//----- ------------------------------------------------------------------ -// Atomic Operation -//----- ------------------------------------------------------------------ - -/* - * atomic_read - read atomic variable - * @v: pointer of type atomic_t - * - * Atomically reads the value of @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#undef atomic_read -#define atomic_read(v) ((v)->counter) - -/* - * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value - * - * Atomically sets the value of @v to @i. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#undef atomic_set -#define atomic_set(v,i) ((v)->counter = (i)) - - /* - * These inlines deal with timer wrapping correctly. You are - * strongly encouraged to use them - * 1. Because people otherwise forget - * 2. Because if the timer wrap changes in future you wont have to - * alter your driver code. - * - * time_after(a,b) returns true if the time a is after time b. - * - * Do this with "<0" and ">=0" to only test the sign of the result. A - * good compiler would generate better code (and a really good compiler - * wouldn't care). Gcc is currently neither. - */ - #define time_after(a,b) ((long)(b) - (long)(a) < 0) - #define time_before(a,b) time_after(b,a) - - #define time_after_eq(a,b) ((long)(a) - (long)(b) >= 0) - #define time_before_eq(a,b) time_after_eq(b,a) - - -extern void rtw_init_listhead(_list *list); -extern u32 rtw_is_list_empty(_list *phead); -extern void rtw_list_insert_head(_list *plist, _list *phead); -extern void rtw_list_insert_tail(_list *plist, _list *phead); -extern void rtw_list_delete(_list *plist); - -#if (defined CONFIG_PLATFORM_8711B) || (defined CONFIG_PLATFORM_8721D) -extern u32 random_seed; -#endif - -#endif /* _CMSIS_RTOS_SERVICE_H_ */ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/device_lock.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/device_lock.c deleted file mode 100644 index 6cbef3cc3d7..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/device_lock.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Routines to access hardware - * - * Copyright (c) 2013 Realtek Semiconductor Corp. - * - * This module is a confidential and proprietary property of RealTek and - * possession or use of this module requires written permission of RealTek. - */ - -#include "osdep_service.h" -#include "device_lock.h" - -//------------------------------------------------------ -#define DEVICE_MUTEX_IS_INIT(device) (mutex_init & (1< - -#if defined(CONFIG_PLATFORM_8710C) || defined(CONFIG_PLATFORM_8195BHP) -#include -#include -#if (CONFIG_CMSIS_FREERTOS_EN==1) -#define PLATFORM_FREERTOS 1 -#endif -#else -#if (CONFIG_PLATFORM_AMEBA_X == 1) -#include "platform_autoconf.h" -#endif -#endif - -#if (CONFIG_PLATFORM_AMEBA_X == 0) -#ifndef SUCCESS -#define SUCCESS 0 -#endif -#ifndef FAIL -#define FAIL (-1) -#endif -#ifndef _SUCCESS -#define _SUCCESS 1 -#endif -#ifndef _FAIL -#define _FAIL 0 -#endif -#ifndef FALSE - #define FALSE 0 -#endif - -#ifndef false - #define false 0 -#endif - -#ifndef TRUE - #define TRUE (!FALSE) -#endif - -#ifndef true - #define true (!false) -#endif - - -#ifndef DBG_8195A -#define DBG_8195A -#endif - -#define _TRUE TRUE -#define _FALSE FALSE - -#endif - -#if defined(PLATFORM_FREERTOS) -#include "freertos_service.h" -#elif defined(PLATFORM_ECOS) -#include "ecos/ecos_service.h" -#elif defined(PLATFORM_CMSIS_RTOS) -#include "cmsis_rtos_service.h" -#elif defined(CONFIG_PLATFOMR_CUSTOMER_RTOS) -#include "customer_rtos_service.h" -#endif - -#define RTW_MAX_DELAY 0xFFFFFFFF -#define RTW_WAIT_FOREVER 0xFFFFFFFF - -/****************************************************** - * Constants - ******************************************************/ -/** - * @brief Definitions returned by xTaskGetSchedulerState(). - */ - -#define OS_SCHEDULER_NOT_STARTED 0 -#define OS_SCHEDULER_RUNNING 1 -#define OS_SCHEDULER_SUSPENDED 2 - -/****************************************************** - * Structures - ******************************************************/ -struct timer_list { - _timerHandle timer_hdl; - unsigned long data; - void (*function)(void *); -}; - -/****************************************************** - * Type Definitions - ******************************************************/ -typedef thread_return (*thread_func_t)(thread_context context); -typedef void (*TIMER_FUN)(void *context); -typedef int (*event_handler_t)(char *buf, int buf_len, int flags, void *user_data); - -#define CONFIG_THREAD_COMM_SEMA -struct task_struct { - const char *task_name; - _thread_hdl_ task; /* I: workqueue thread */ - -#ifdef CONFIG_THREAD_COMM_SIGNAL - const char *name; /* I: workqueue thread name */ - u32 queue_num; /* total signal num */ - u32 cur_queue_num; /* cur signal num should < queue_num */ -#elif defined(CONFIG_THREAD_COMM_SEMA) - _sema wakeup_sema; /* for internal use only */ - _sema terminate_sema; /* for internal use only */ -#endif - u32 blocked; /* for internal use only */ - u32 callback_running; /* for internal use only */ -}; - -typedef struct { - _xqueue event_queue; - struct task_struct thread; -}rtw_worker_thread_t; - -typedef struct -{ - event_handler_t function; - char *buf; - int buf_len; - int flags; - void *user_data; -} rtw_event_message_t; - -struct worker_timer_entry { - struct list_head list; - _timerHandle timer_hdl; - rtw_event_message_t message; - rtw_worker_thread_t *worker_thread; - u32 timeout; -}; - -#ifdef CONFIG_THREAD_COMM_SIGNAL -struct work_struct; -typedef void (*work_func_t)(void *context); -struct work_struct { - _list list; - u32 data; - work_func_t func; - void *context; - struct task_struct *used_wq; -}; - -struct delayed_work { - struct work_struct work; - struct timer_list timer; -}; -#endif - - -#ifdef CONFIG_MEM_MONITOR - -/*************************** Memory Monitor *******************************/ -#define MEM_MONITOR_SIMPLE 0x1 -#define MEM_MONITOR_LEAK 0x2 - -#define MEM_MONITOR_FLAG_WIFI_DRV 0x1 -#define MEM_MONITOR_FLAG_WPAS 0x2 -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK -struct mem_entry { - struct list_head list; - int size; - void *ptr; -}; -#endif - -/** - * @brief This function initializes a memory table. - * @param[in] pmem_table: The pointer to the memory table. - * @param[in] used_num: The number of mem_entry kept in monitor which will be set to 0. - * @return None - */ -void init_mem_monitor(_list *pmem_table, int *used_num); - -/** - * @brief This function deinitializes a memory table. - * @param[in] pmem_table: The pointer to the memory table. - * @param[in] used_num: The number of mem_entry kept in monitor. - * @return None - */ -void deinit_mem_monitor(_list *pmem_table, int *used_num); - -/** - * @brief This function alloc mem_entry to the memory table. - * @param[in] pmem_table: The pointer to the memory table to be added. - * @param[in] ptr: The pointer to the position to be added. - * @param[in] size: The size of added memory. - * @param[in] used_num: The number of mem_entry kept in monitor which will add 1 after. - * @param[in] flag: MEM_MONITOR_FLAG_WPAS/MEM_MONITOR_FLAG_WIFI_DRV - * @return None - */ -void add_mem_usage(_list *pmem_table, void *ptr, int size, int *used_num, int flag); - -/** - * @brief This function frees memory from the memory table. - * @param[in] pmem_table: The pointer to the memory table - * @param[in] ptr: The pointer to the position to be free. - * @param[in] used_num: The number of mem_entry kept in monitor. - * @param[in] flag: MEM_MONITOR_FLAG_WPAS/MEM_MONITOR_FLAG_WIFI_DRV - * @return None - */ -void del_mem_usage(_list *pmem_table, void *ptr, int *used_num, int flag); - -/** - * @brief This function get the memory usage of a memory table. - * @param[in] pmem_table: The pointer to the memory table. - * @return The size of the memory used - */ -int get_mem_usage(_list *pmem_table); -/*************************** End Memory Monitor *******************************/ -#endif - - -/*************************** Memory Management *******************************/ -u8* _rtw_vmalloc(u32 sz); -u8* _rtw_zvmalloc(u32 sz); -void _rtw_vmfree(u8 *pbuf, u32 sz); -u8* _rtw_zmalloc(u32 sz); -u8* _rtw_malloc(u32 sz); -void _rtw_mfree(u8 *pbuf, u32 sz); -#ifdef CONFIG_MEM_MONITOR - -/** - * @brief This function allocates the virtually contiguous memory. - * @param[in] sz: The size of memory to be allocated. - * @return The pointer to the beginning of the memory - */ -u8* rtw_vmalloc(u32 sz); - -/** - * @brief This function allocates the virtually contiguous memory - * and the values of the memory are setted to 0. - * @param[in] sz: The size of memory to be allocated. - * @return The pointer to the beginning of the memory - */ -u8* rtw_zvmalloc(u32 sz); - -/** - * @brief This function frees the virtually contiguous memory. - * @param[in] pbuf: The pointer to the beginning of the memory to be free - * @param[in] sz: The size of memory allocated. - * @return None - */ -void rtw_vmfree(u8 *pbuf, u32 sz); - -/** - * @brief This function allocates the memory - * and the values of the memory are setted to 0. - * @param[in] sz: The size of memory to be allocated. - * @return The pointer to the beginning of the memory - */ -u8* rtw_zmalloc(u32 sz); - -/** - * @brief This function allocates the memory. - * @param[in] sz: The size of memory to be allocated. - * @return The pointer to the beginning of the memory - */ -u8* rtw_malloc(u32 sz); - -/** - * @brief This function frees the virtually contiguous memory. - * @param[in] pbuf: The pointer to the beginning of the memory to be free - * @param[in] sz: The size of memory allocated. - * @return None - */ -void rtw_mfree(u8 *pbuf, u32 sz); -#else -#define rtw_vmalloc _rtw_vmalloc -#define rtw_zvmalloc _rtw_zvmalloc -#define rtw_vmfree _rtw_vmfree -#define rtw_zmalloc _rtw_zmalloc -#define rtw_malloc _rtw_malloc -#define rtw_mfree _rtw_mfree -#endif -#define rtw_free(buf) rtw_mfree((u8 *)buf, 0) - -/** - * @brief This function allocates a 2 dimensional array memory. - * @param[in] h: The height of the 2D array. - * @param[in] w: The width of the 2D array. - * @param[in] size: The size of the each charactor in array. - * @return the pointer to the beginning of the block - */ -void* rtw_malloc2d(int h, int w, int size); - -/** - * @brief This function deallocates the block of memory previously allocated to make it available again. - * @param[in] pbuf: Pointer to a memory block previously allocated. - * @param[in] h: The height of the 2D array. - * @param[in] w: The width of the 2D array. - * @param[in] size: The size of the each charactor in array. - * @return None - */ -void rtw_mfree2d(void *pbuf, int h, int w, int size); - -/** - * @brief This function copies the values of "sz" bytes from the location pointed to by "src" - * directly to the memory block pointed to by "des". - * @param[in] dst: Pointer to the destination array where the content is to be copied, type-casted to a pointer of type void*. - * @param[in] src: Pointer to the source of data to be copied, type-casted to a pointer of type void*. - * @param[in] sz: Size of memory to copy. - * @return None - */ -void rtw_memcpy(void* dst, void* src, u32 sz); - -/** - * @brief This function compares the first "sz" bytes of the block of memory pointed by "dst" - * to the first "sz" bytes pointed by "src". - * @param[in] dst: Pointer to block of memory to be compared. - * @param[in] src: pointer to block of memory to compare. - * @param[in] sz: Size of memory to compare. - * @return <0: The first byte that does not match in both memory blocks has a lower value in dst than in src. - * @return 0: The contents of both memory blocks are equal. - * @return <0: The first byte that does not match in both memory blocks has a greater value in dst than in src. - */ -int rtw_memcmp(void *dst, void *src, u32 sz); - -/** - * @brief This function sets the first "sz" bytes of the block of memory pointed by "pbuf" to the specified "c". - * @param[in] pbuf: Pointer to the block of memory to fill. - * @param[in] c: Value to be set. - * @param[in] sz: Size of memory to be set to the value "c". - * @return None - */ -void rtw_memset(void *pbuf, int c, u32 sz); -/*************************** End Memory Management *******************************/ - -/*************************** List *******************************/ - -/** - * @brief This function initializes the head of the list. - * @param[in] list: Pointer to the list to be initialized. - * @return None - */ -void rtw_init_listhead(_list *list); - -/** - * @brief This function tests whether a list is empty. - * @param[in] phead: Pointer to the list to test. - * @return _TRUE/_FALSE - */ -u32 rtw_is_list_empty(_list *phead); - -/** - * @brief This function adds a new entry after "phead" for the list. - * @param[in] plist: Pointer to the list to be added. - * @param[in] phead: List head to add it after. - * @return None - */ -void rtw_list_insert_head(_list *plist, _list *phead); - -/** - * @brief This function adds a new entry before "phead" for the list. - * @param[in] plist: Pointer to the list to be added. - * @param[in] phead: List head to add it before. - * @return None - */ -void rtw_list_insert_tail(_list *plist, _list *phead); - -/** - * @brief This function deletes entry from list and reinitialize it. - * @param[in] plist: The element to delete from the list. - * @return None - * @note Caller must check if the list is empty before calling rtw_list_delete - */ -void rtw_list_delete(_list *plist); -/*************************** End List *******************************/ - - -/*************************** Semaphores *******************************/ -/** - * @brief This function initializes the unnamed semaphore referred to by "sema" to the value "init_val". - * @param[in] sema: Pointer to the semaphore handle to be initialized. - * @param[in] init_val: Initial value for semaphore. - * @return None - */ -void rtw_init_sema(_sema *sema, int init_val); - -/** - * @brief This function deletes the semaphore. - * @param[in] sema: The semaphore to be deleted. - * @return None - */ -void rtw_free_sema(_sema *sema); - -/** - * @brief This function releases the semaphore. - * This macro must not be used from an ISR. - * @param[in] sema: The semaphore to be released. - * @return None - */ -void rtw_up_sema(_sema *sema); - -/** - * @brief This function releases the semaphore. - * This macro can be used from an ISR. - * @param[in] sema: The semaphore to be released. - * @return None - */ -void rtw_up_sema_from_isr(_sema *sema); - -/** - * @brief This function acquires the semaphore. If no more tasks are allowed to acquire the semaphore, - * calling this function will put the task to sleep until the semaphore is up. - * @param[in] sema: The semaphore to be acquired. - * @return pdTRUE: The semaphore was obtained. - * @return pdFALSE: Obtain the semaphore failed. - */ -u32 rtw_down_sema(_sema *sema); - -/** - * @brief This function acquires the semaphore. If no more tasks are allowed to acquire the semaphore, - * calling this function will put the task to sleep until the semaphore is up. - * @param[in] sema: The semaphore to be acquired. - * @param[in] timeout: The time in ms to wait for the semaphore to become available. - * @return pdTRUE: The semaphore was obtained. - * @return pdFALSE: Timeout without the semaphore becoming available. - */ -u32 rtw_down_timeout_sema(_sema *sema, u32 timeout); -/*************************** End Semaphores *******************************/ - -/*************************** Mutexes *******************************/ -/** - * @brief This function implements a mutex semaphore by using the existing queue mechanism. - * @param[in] pmutex: Pointer to the created mutex semaphore. - * @return None - */ -void rtw_mutex_init(_mutex *pmutex); - -/** - * @brief This function deletes the mutex semaphore. - * @param[in] pmutex: Pointer to the mutex semaphore to be deleted. - * @return None - */ -void rtw_mutex_free(_mutex *pmutex); - -/** - * @brief This function releases a mutex semaphore. - * @param[in] pmutex: Pointer to the mutex semaphore to be released. - * @return None - */ -void rtw_mutex_put(_mutex *pmutex); - -/** - * @brief This function obtains a mutex semaphore. - * @param[in] pmutex: Pointer to the mutex semaphore being taken - obtained when - * the mutex semaphore was created. - * @return None - */ -void rtw_mutex_get(_mutex *pmutex); - -/** - * @brief This function obtains a mutex semaphore with a timeout setting. - * @param[in] pmutex: Pointer to the mutex semaphore being taken - obtained when - * the mutex semaphore was created. - * @param[in] timeout: The time in ms to wait for the semaphore to become available. - * @return 0: The semaphore was obtained. - * @return -1: Timeout without the semaphore becoming available. - */ -int rtw_mutex_get_timeout(_mutex *pmutex, u32 timeout_ms); -/*************************** End Mutexes *******************************/ - -/*************************** SchedulerControl *******************************/ -/** - * @brief This function marks the start of a critical code region. - * Preemptive context switches cannot occur when in a critical region. - * @param[in] plock: Pointer to the spin lock semaphore. - * @param[in] pirqL: Pointer to the IRQ. - * @return None - * @note: This may alter the stack (depending on the portable implementation) - * so must be used with care! - */ -void rtw_enter_critical(_lock *plock, _irqL *pirqL); - -/** - * @brief This function marks end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * @param[in] plock: Pointer to the spin lock semaphore. - * @param[in] pirqL: Pointer to the IRQ. - * @return None - * @note: This may alter the stack (depending on the portable implementation) - * so must be used with care! - */ -void rtw_exit_critical(_lock *plock, _irqL *pirqL); - -/** - * @brief This function marks the start of a critical code region from isr. - * @param[in] plock: Pointer to the spin lock semaphore. - * @param[in] pirqL: Pointer to the IRQ. - * @return None - */ -void rtw_enter_critical_from_isr(_lock *plock, _irqL *pirqL); - -/** - * @brief This function marks the end of a critical code region from isr. - * @param[in] plock: Pointer to the spin lock semaphore. - * @param[in] pirqL: Pointer to the IRQ. - * @return None - */ -void rtw_exit_critical_from_isr(_lock *plock, _irqL *pirqL); - -/** - * @brief This function obtains a spin lock semaphore. - * @param[in] plock: Pointer to the spin lock semaphore being taken - obtained when - * the mutex semaphore was created. - * @param[in] pirqL: Pointer to the IRQ. - * @return None - */ -void rtw_enter_critical_bh(_lock *plock, _irqL *pirqL); - -/** - * @brief This function releases a spin lock semaphore. - * @param[in] plock: Pointer to the spin lock semaphore to be released. - * @param[in] pirqL: Pointer to the IRQ. - * @return None - */ -void rtw_exit_critical_bh(_lock *plock, _irqL *pirqL); - -/** - * @brief This function obtains a semaphore. - * @param[in] pmutex: The handle to the mutex semaphore to be obtained. - * @param[in] pirqL: Pointer to the IRQ. - * @return None - */ -int rtw_enter_critical_mutex(_mutex *pmutex, _irqL *pirqL); - -/** - * @brief This function releases a semaphore. - * @param[in] pmutex: The handle to the mutex semaphore to be released. - * @param[in] pirqL: Pointer to the IRQ. - * @return None - */ -void rtw_exit_critical_mutex(_mutex *pmutex, _irqL *pirqL); - -/** - * @brief This function will lock cpu. Can be used when xip active and want to do some flash operation. - * @return None - */ -void rtw_cpu_lock(void); - - /** - * @brief This function unlock cpu. - * @return None - */ -void rtw_cpu_unlock(void); - -/*************************** End SchedulerControl *******************************/ - -/*************************** Semaphores *******************************/ - -/** - * @brief This function implements a spin lock semaphore by using the existing queue mechanism. - * @param[in] plock: Pointer to the created spin lock semaphore. - * @return None - */ -void rtw_spinlock_init(_lock *plock); - -/** - * @brief This function deletes the spin lock semaphore. - * @param[in] pmutex: Pointer to the spin lock semaphore to be deleted. - * @return None - */ -void rtw_spinlock_free(_lock *plock); - -/** - * @brief This function obtains a spin lock semaphore. - * @param[in] plock: Pointer to the spin lock semaphore being taken - obtained when - * the mutex semaphore was created. - * @return None - */ -void rtw_spin_lock(_lock *plock); - -/** - * @brief This function releases a spin lock semaphore. - * @param[in] plock: Pointer to the spin lock semaphore to be released. - * @return None - */ -void rtw_spin_unlock(_lock *plock); - -/** - * @brief This function marks the start of a critical code region and - * obtains a spin lock semaphore. - * @param[in] plock: Pointer to the spin lock semaphore being taken - obtained when - * the mutex semaphore was created. - * @param[in] irqL: Pointer to the IRQ. - * @return None - */ -void rtw_spinlock_irqsave(_lock *plock, _irqL *irqL); - -/** - * @brief This function releases a spin lock semaphore and - marks the end of a critical code region. - * @param[in] plock: Pointer to the spin lock semaphore to be released. - * @param[in] irqL: Pointer to the IRQ. - * @return None - */ -void rtw_spinunlock_irqsave(_lock *plock, _irqL *irqL); -/*************************** End Semaphores *******************************/ - -/*************************** Queues *******************************/ - -/** - * @brief This function creates a new queue instance. - * @param[in] queue: The handle to the newly created queue. - * @param[in] name: The name of the queue - * @param[in] message_size: The number of bytes each message in the queue will require. - * @param[in] number_of_messages: The maximum number of messages that kthe queue can contain. - * @return 0: Creating queue success - * @return -1: Creating queue fail - */ -int rtw_init_xqueue( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages ); - -/** - * @brief This function posts a message to the back of a queue. - * The message is queued by copy, not by reference. - * @param[in] queue: The handle to the queue on which the message is to be posted. - * @param[in] message: The pointer to the message that is to be placed on the queue. - * @param[in] timeout_ms: The maximum amout of time the task should block waiting for - the space to become available on the queue, should it already be full. - The time is defined in ms. - * @return 0: The message was successfully posted. - * @return -1: The message was not posted. - */ -int rtw_push_to_xqueue( _xqueue* queue, void* message, u32 timeout_ms ); - -/** - * @brief This function receives a message from a queue. - * The message is recieved by copy so a buffer adequate size must be provided. - * @param[in] queue: The handle to the queue from which the message is to be received. - * @param[in] message: The pointer to the buffer into which the received message will be copied. - * @param[in] timeout_ms: The maximum amout of time the task should block waiting for a message to - * receive should the queue be empty at the time of the call. - The time is defined in ms. - * @return 0: A message was successfully received from the queue. - * @return -1: No message was received from the queue. - */ -int rtw_pop_from_xqueue( _xqueue* queue, void* message, u32 timeout_ms ); - -/** - * @brief Delete a queue - freeing all the memory allocated for storing of messages placed on the queue. - * @param[in] queue: The handle to the queue to be deleted. - * @return 0: The queue was successfully deleted. - * @return -1: The queue was not empty so cannot be deleted. - */ -int rtw_deinit_xqueue( _xqueue* queue ); - -/** - * @brief This function creates a new queue instance. - * @param[in] pqueue: The handle to the newly created queue. - * @return None - */ -void rtw_init_queue(_queue *pqueue); -void rtw_deinit_queue(_queue *pqueue); -u32 rtw_is_queue_empty(_queue *pqueue); - -/** - * @brief This function tests whether the queue is empty. - * @param[in] pqueue: The handle to the queue to be tested. - * @return None - */ -u32 rtw_queue_empty(_queue *pqueue); - -/** - * @brief This function tests whether the "pelement" is at the "queue". - * @param[in] queue: The pointer to the queue that to be tested. - * @param[in] pelement: The element that to be tested. - * @return _TRUE/_FALSE - */ -u32 rtw_end_of_queue_search(_list *queue, _list *pelement); -_list* rtw_get_queue_head(_queue *queue); -/*************************** End Queues *******************************/ - -/*************************** Time Management *******************************/ - -/** - * @brief Get the count of ticks since the vTaskStartScheduler was called. - * @return The count of ticks since the vTaskStartScheduler was called. - */ -u32 rtw_get_current_time(void); - -/** - * @brief Convert system time to milliseconds. - * @param[in] systime: The system time to be converted. - * @return : The milliseconds that converted by the system time. - */ -u32 rtw_systime_to_ms(u32 systime); - -/** - * @brief Convert system time to seconds. - * @param[in] systime: The system time to be converted. - * @return : The seconds that converted by the system time. - */ -u32 rtw_systime_to_sec(u32 systime); - -/** - * @brief Convert milliseconds to system time. - * @param[in] systime: The milliseconds to be converted. - * @return : The system time that converted by the milliseconds. - */ -u32 rtw_ms_to_systime(u32 ms); - -/** - * @brief Convert seconds to system time. - * @param[in] systime: The seconds to be converted. - * @return : The system time that converted by the seconds. - */ -u32 rtw_sec_to_systime(u32 sec); - -/** - * @brief Get the passing time from the "start" in milliseconds. - * @param[in] start: The start time which is in system time format. - * @return : The passing time from "start" in milliseconds. - */ -s32 rtw_get_passing_time_ms(u32 start); - -/** - * @brief Get the interval time from the "start" to "end" in milliseconds. - * @param[in] start: The start time which is in system time format. - * @param[in] end: The end time which is in system time format. - * @return : The interval time from "start" to "end" in milliseconds. - */ -s32 rtw_get_time_interval_ms(u32 start, u32 end); -/*************************** End Time Management *******************************/ - -/** - * @brief This function suspends execution of the calling thread for "ms" milliseconds. - * @param[in] ms: The time that the function sleep in milliseconds - * @return None -*/ -void rtw_msleep_os(int ms); - -/** - * @brief This function suspends execution of the calling thread for "us" microseconds. - * @param[in] ms: The time that the function sleep in microseconds - * @return None -*/ -void rtw_usleep_os(int us); - -/** - * @brief This function converts the initial portion of the string to integer. - * @param[in] s: The pointer to the string to be converted. - * @return The converted value. -*/ -u32 rtw_atoi(u8* s); - -/** - * @brief This function delays a task for the giving time in milliseconds. - * @param[in] ms: The amount of time, in milliseconds, that the calling task should block. - * @return None -*/ -void rtw_mdelay_os(int ms); - -/** - * @brief This function delays a task for the giving time in microseconds. - * @param[in] ms: The amount of time, in microseconds, that the calling task should block. - * @return None -*/ -void rtw_udelay_os(int us); - -/** - * @brief This function for forcing a context switch. - * @return None -*/ -void rtw_yield_os(void); - -/*************************** ATOMIC Integer *******************************/ - -/** - * @brief This function atomically sets the value of the variable. - * @param[in] v: Pointer of type atomic_t that to be set value. - * @param[in] i: Required value. - * @return None - * @note The guaranteed useful range of an atomic_t is only 24 bits. -*/ -void ATOMIC_SET(ATOMIC_T *v, int i); - -/** - * @brief This function atomically reads the value of the variable. - * @param[in] v: Pointer of type atomic_t that to be read. - * @return The value of the variable. - * @note The guaranteed useful range of an atomic_t is only 24 bits. -*/ -int ATOMIC_READ(ATOMIC_T *v); - -/** - * @brief This function adds "i" to the contained "v". - * @param[in] v: Pointer of type atomic_t. - * @param[in] i: value to add. - * @return None -*/ -void ATOMIC_ADD(ATOMIC_T *v, int i); - -/** - * @brief This function subtracts "i" from th econtained "v". - * @param[in] v: Pointer of type atomic_t. - * @param[in] i: value to subtract. - * @return None -*/ -void ATOMIC_SUB(ATOMIC_T *v, int i); - -/** - * @brief This function adds 1 to the contained "v". - * @param[in] v: Pointer of type atomic_t. - * @return None -*/ -void ATOMIC_INC(ATOMIC_T *v); - -/** - * @brief This function subtracts 1 from th econtained "v". - * @param[in] v: Pointer of type atomic_t. - * @return None -*/ -void ATOMIC_DEC(ATOMIC_T *v); - -/** - * @brief This function adds "i" to the contained "v" and returns the result. - * @param[in] v: Pointer of type atomic_t. - * @param[in] i: value to add. - * @return None -*/ -int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); - -/** - * @brief This function subtracts "i" from th econtained "v" and returns the result. - * @param[in] v: Pointer of type atomic_t. - * @param[in] i: value to subtract. - * @return None -*/ -int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); - -/** - * @brief This function adds 1 to the contained "v" and returns the result. - * @param[in] v: Pointer of type atomic_t. - * @return None -*/ -int ATOMIC_INC_RETURN(ATOMIC_T *v); - -/** - * @brief This function subtracts 1 from th econtained "v" and returns the result. - * @param[in] v: Pointer of type atomic_t. - * @return None -*/ -int ATOMIC_DEC_RETURN(ATOMIC_T *v); - -/** - * @brief This function subtracts 1 from th econtained "v" and test if the result equals 0. - * @param[in] v: Pointer of type atomic_t. - * @return 0: The result after subtracting 1 is 0 - * @return -1: The result after subtracting 1 is not 0 -*/ -int ATOMIC_DEC_AND_TEST(ATOMIC_T *v); -/*************************** End ATOMIC *******************************/ - -u64 rtw_modular64(u64 x, u64 y); - -/** - * @brief This function generates random bytes. - * @param[in] dst: The pointer to the buffer to store the random bytes. - * @param[in] size: The size of the random bytes. - * @return 0 -*/ -int rtw_get_random_bytes(void* dst, u32 size); - -/** - * @brief This function gets the available heap size. - * @return The value of the available heap size. -*/ -u32 rtw_getFreeHeapSize(void); - -void flush_signals_thread(void); - -/** - * @brief This function indicates that the WLAN needs to stay on which means cannot go into power saving mode. - * @return None - * @note Defining configUSE_WAKELOCK_PMU 1 in "FreeRTOSConfig.h" needs to be done before compiling, - * or this API won't be effective. - */ -void rtw_acquire_wakelock(void); - -/** - * @brief This function indicates that the WLAN does not need to stay on which means can go into power saving mode. - * @return None - * @note Defining configUSE_WAKELOCK_PMU 1 in "FreeRTOSConfig.h" needs to be done before compiling, - * or this API won't be effective. - */ -void rtw_release_wakelock(void); -void rtw_wakelock_timeout(u32 timeout); - -/*********************************** Thread related *****************************************/ - -/** - * @brief This function creates a new task and adds it to the list of tasks that are ready to run. - * @param[in] task: The task stucture which will store the task related infomation. - * @param[in] name: A descriptive name for the task. - * @param[in] stack_size: The size of the task stack specified as the variables the stack can hold. - * @param[in] priority: The priority at which the task should run. - * @param[in] func: The task entry function. - * @param[in] thctx: The pointer that will be used as the parameter for the task being created. - * @return pdPASS: The task was successfully created and added to a ready list. - * @return other error code defined in the file errors.h. - * @note For the task name, please do not use "rtw_little_wifi_mcu_thread", "rtw_check_in_req_state_thread", - "rtw_TDMA_change_state_thread", "xmit_thread", "recv_thread", "rtw_recv_tasklet", "rtw_xmit_tasklet", - "rtw_interrupt_thread", "cmd_thread", "usb_init", "MSC_BULK_CMD" and "MSC_BULK_DATA". - */ -int rtw_create_task(struct task_struct *task, const char *name, u32 stack_size, u32 priority, thread_func_t func, void *thctx); - -/** - * @brief This function deletes a task. - * @param[in] task: The task stucture which will be deleted. - * @return None - */ -void rtw_delete_task(struct task_struct * task); - -/** - * @brief This function wake up a task. - * @param[in] task: The task stucture which will be waked up. - * @return None - */ -void rtw_wakeup_task(struct task_struct *task); - -/** - * @brief This function creates a new worker thread. - * @param[in] worker_thread: The pointer to the worker thread stucture. - * @param[in] priority: The priority of the thread. - * @param[in] stack_size: The size of the thread stack specified as the variables the stack can hold. - * @param[in] event_queue_size: The queue size of events. - * @return SUCCESS/FAIL. - */ -int rtw_create_worker_thread( rtw_worker_thread_t* worker_thread, u8 priority, u32 stack_size, u32 event_queue_size ); - -/** - * @brief This function deletes a worker thread. - * @param[in] worker_thread: The pointer to the worker thread stucture to be deleted. - * @return SUCCESS/FAIL. - */ -int rtw_delete_worker_thread( rtw_worker_thread_t* worker_thread ); - -#if 0 //TODO -void rtw_init_delayed_work(struct delayed_work *dwork, work_func_t func, const char *name); -void rtw_deinit_delayed_work(struct delayed_work *dwork); -int rtw_queue_delayed_work(struct workqueue_struct *wq, struct delayed_work *dwork, u32 delay, void* context); -BOOLEAN rtw_cancel_delayed_work(struct delayed_work *dwork); -#endif - -/** - * @brief This function prints the name of the thread in DBG_INFO. - * @param[in] name: The name of the thread. - * @return None - */ -void rtw_thread_enter(char *name); - -/** - * @brief This function exits the calling thread. - * @return None - */ -void rtw_thread_exit(void); - -/** - * @brief This function gets the scheduler state of the calling thread. - * @return OS_SCHEDULER_NOT_STARTED - * @return OS_SCHEDULER_RUNNING - * @return OS_SCHEDULER_SUSPENDED - */ -u8 rtw_get_scheduler_state(void); - -/*************************** End Threads *******************************/ -#ifdef PLATFORM_LINUX -#define rtw_warn_on(condition) WARN_ON(condition) -#else -#define rtw_warn_on(condition) do {} while (0) -#endif - -/*************************** Timers *******************************/ - -/** - * @brief This function creates a new software timer instance. - * @param[in] pcTimerName: A text name that is assigned to the timer. - * @param[in] xTimerPeriodInTicks: The timer period which is defined in tick periods. - * @param[in] uxAutoReload: If uxAutoReload is set to pdTRUE then the timer will - * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. If - * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and - * enter the dormant state after it expires. - * @param[in] pvTimerID: An identifier that is assigned to the timer being created. - * @param[in] pxCallbackFunction: The function to call when the timer expires. - * @return If the timer is successfully create then a handle to the newly - * created timer is returned. If the timer cannot be created, then 0 is returned. - */ -_timerHandle rtw_timerCreate( const signed char *pcTimerName, - osdepTickType xTimerPeriodInTicks, - u32 uxAutoReload, - void * pvTimerID, - TIMER_FUN pxCallbackFunction ); - -/** - * @brief This function deletes a timer that was previously created using rtw_timerCreate. - * @param[in] xTimer: The handle of the timer being deleted. - * @param[in] xBlockTime: Specifies th etime, in ticks, that the calling task should be held in the Blocked - * State to wait for the delete command to be successfully sent to the timer command queue, - * should the queue already be full when rtw_timerDelete was called. - * @return pdFAIL will be returned if the delete command could not be sent to - * the timer command queue even after xTicksToWait ticks had passed. pdPASS will - * be returned if the command was successfully sent to the timer command queue. - * When the command is actually processed will depend on the priority of the - * timer service/daemon task relative to other tasks in the system. - */ -u32 rtw_timerDelete( _timerHandle xTimer, osdepTickType xBlockTime ); - -/** - * @brief This function queries a timer to see if it is active or dormant. - * @param[in] xTimer: The timer being queried. - * @return pdFALSE will be returned if the timer is dormant. A value other than - * pdFALSE will be returned if the timer is active. - * @note A timer will be dormant if: - * 1) It has been created but not started, or - * 2) It is an expired one-shot timer that has not been restarted. - */ -u32 rtw_timerIsTimerActive( _timerHandle xTimer ); - -/** - * @brief This function stops a timer that was previously started. - * @param[in] xTimer: The handle of the timer being stopped. - * @param[in] xBlockTime: Specifies the time, in ticks, that the calling task should - * be held in the Blocked state to wait for the stop command to be successfully - * sent to the timer command queue, should the queue already be full when - * rtw_timerStop() was called. - * @return pdFAIL will be returned if the stop command could not be sent to - * the timer command queue even after xTicksToWait ticks had passed. pdPASS will - * be returned if the command was successfully sent to the timer command queue. - * When the command is actually processed will depend on the priority of the - * timer service/daemon task relative to other tasks in the system. - */ -u32 rtw_timerStop( _timerHandle xTimer, osdepTickType xBlockTime ); - -/** - * @brief This function changes the period of a timer that was previously created. - * @param[in] xTimer: The handle of the timer that is having its period changed. - * @param[in] xNewPeriod: The new period for xTimer. - * @param[in] xBlockTime: Specifies the time, in ticks, that the calling task should - * be held in the Blocked state to wait for the change period command to be - * successfully sent to the timer command queue, should the queue already be - * full when rtw_timerChangePeriod() was called. - * @return pdFAIL will be returned if the change period command could not be - * sent to the timer command queue even after xTicksToWait ticks had passed. - * pdPASS will be returned if the command was successfully sent to the timer - * command queue. When the command is actually processed will depend on the - * priority of the timer service/daemon task relative to other tasks in the - * system. - */ -u32 rtw_timerChangePeriod( _timerHandle xTimer, - osdepTickType xNewPeriod, - osdepTickType xBlockTime ); - -void *rtw_timerGetID( _timerHandle xTimer ); - -u32 rtw_timerStart( _timerHandle xTimer, osdepTickType xBlockTime ); - -u32 rtw_timerStartFromISR( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ); - -u32 rtw_timerStopFromISR( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ); - -u32 rtw_timerResetFromISR( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ); - -u32 rtw_timerChangePeriodFromISR( _timerHandle xTimer, - osdepTickType xNewPeriod, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ); - -u32 rtw_timerReset( _timerHandle xTimer, - osdepTickType xBlockTime ); - - -/*************************** End Timers *******************************/ -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)((char *)&((type *)ptr)->member - (char *)ptr))) - -#define time_after(a,b) ((long)(b) - (long)(a) < 0) -#define time_before(a,b) time_after(b,a) -#define time_after_eq(a,b) ((long)(a) - (long)(b) >= 0) -#define time_before_eq(a,b) time_after_eq(b,a) - -#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) -#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2) - -__inline static u32 _RND4(u32 sz) -{ - u32 val; - - val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2; - - return val; -} - -__inline static u32 _RND8(u32 sz) -{ - u32 val; - - val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3; - - return val; -} - -__inline static u32 _RND128(u32 sz) -{ - u32 val; - - val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7; - - return val; -} - -__inline static u32 _RND256(u32 sz) -{ - u32 val; - - val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8; - - return val; -} - -__inline static u32 _RND512(u32 sz) -{ - u32 val; - - val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9; - - return val; -} - -__inline static u32 bitshift(u32 bitmask) -{ - u32 i; - - for (i = 0; i <= 31; i++) - if (((bitmask>>i) & 0x1) == 1) break; - - return i; -} - -#define rtw_min(a, b) ((a > b) ? b : a) - -/* Macros for handling unaligned memory accesses */ - -#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1])) -#define RTW_PUT_BE16(a, val) \ - do { \ - (a)[0] = ((u16) (val)) >> 8; \ - (a)[1] = ((u16) (val)) & 0xff; \ - } while (0) - -#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0])) -#define RTW_PUT_LE16(a, val) \ - do { \ - (a)[1] = ((u16) (val)) >> 8; \ - (a)[0] = ((u16) (val)) & 0xff; \ - } while (0) - -#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \ - ((u32) (a)[2])) -#define RTW_PUT_BE24(a, val) \ - do { \ - (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \ - (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ - (a)[2] = (u8) (((u32) (val)) & 0xff); \ - } while (0) - -#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ - (((u32) (a)[2]) << 8) | ((u32) (a)[3])) -#define RTW_PUT_BE32(a, val) \ - do { \ - (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ - (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ - (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ - (a)[3] = (u8) (((u32) (val)) & 0xff); \ - } while (0) - -#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \ - (((u32) (a)[1]) << 8) | ((u32) (a)[0])) -#define RTW_PUT_LE32(a, val) \ - do { \ - (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ - (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ - (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ - (a)[0] = (u8) (((u32) (val)) & 0xff); \ - } while (0) - -#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \ - (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \ - (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \ - (((u64) (a)[6]) << 8) | ((u64) (a)[7])) -#define RTW_PUT_BE64(a, val) \ - do { \ - (a)[0] = (u8) (((u64) (val)) >> 56); \ - (a)[1] = (u8) (((u64) (val)) >> 48); \ - (a)[2] = (u8) (((u64) (val)) >> 40); \ - (a)[3] = (u8) (((u64) (val)) >> 32); \ - (a)[4] = (u8) (((u64) (val)) >> 24); \ - (a)[5] = (u8) (((u64) (val)) >> 16); \ - (a)[6] = (u8) (((u64) (val)) >> 8); \ - (a)[7] = (u8) (((u64) (val)) & 0xff); \ - } while (0) - -#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \ - (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ - (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ - (((u64) (a)[1]) << 8) | ((u64) (a)[0])) - -struct osdep_service_ops { - u8* (*rtw_vmalloc)(u32 sz); - u8* (*rtw_zvmalloc)(u32 sz); - void (*rtw_vmfree)(u8 *pbuf, u32 sz); - u8* (*rtw_malloc)(u32 sz); - u8* (*rtw_zmalloc)(u32 sz); - void (*rtw_mfree)(u8 *pbuf, u32 sz); - void (*rtw_memcpy)(void* dst, void* src, u32 sz); - int (*rtw_memcmp)(void *dst, void *src, u32 sz); - void (*rtw_memset)(void *pbuf, int c, u32 sz); - void (*rtw_init_sema)(_sema *sema, int init_val); - void (*rtw_free_sema)(_sema *sema); - void (*rtw_up_sema)(_sema *sema); - void (*rtw_up_sema_from_isr)(_sema *sema); - u32 (*rtw_down_timeout_sema)(_sema *sema, u32 timeout); - void (*rtw_mutex_init)(_mutex *pmutex); - void (*rtw_mutex_free)(_mutex *pmutex); - void (*rtw_mutex_get)(_mutex *pmutex); - int (*rtw_mutex_get_timeout)(_mutex *pmutex, u32 timeout_ms); - void (*rtw_mutex_put)(_mutex *pmutex); - void (*rtw_enter_critical)(_lock *plock, _irqL *pirqL); - void (*rtw_exit_critical)(_lock *plock, _irqL *pirqL); - void (*rtw_enter_critical_from_isr)(_lock *plock, _irqL *pirqL); - void (*rtw_exit_critical_from_isr)(_lock *plock, _irqL *pirqL); - void (*rtw_enter_critical_bh)(_lock *plock, _irqL *pirqL); - void (*rtw_exit_critical_bh)(_lock *plock, _irqL *pirqL); - int (*rtw_enter_critical_mutex)(_mutex *pmutex, _irqL *pirqL); - void (*rtw_exit_critical_mutex)(_mutex *pmutex, _irqL *pirqL); - void (*rtw_cpu_lock)(void); - void (*rtw_cpu_unlock)(void); - void (*rtw_spinlock_init)(_lock *plock); - void (*rtw_spinlock_free)(_lock *plock); - void (*rtw_spin_lock)(_lock *plock); - void (*rtw_spin_unlock)(_lock *plock); - void (*rtw_spinlock_irqsave)(_lock *plock, _irqL *irqL); - void (*rtw_spinunlock_irqsave)(_lock *plock, _irqL *irqL); - int (*rtw_init_xqueue)( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages ); - int (*rtw_push_to_xqueue)( _xqueue* queue, void* message, u32 timeout_ms ); - int (*rtw_pop_from_xqueue)( _xqueue* queue, void* message, u32 timeout_ms ); - int (*rtw_deinit_xqueue)( _xqueue* queue ); - u32 (*rtw_get_current_time)(void); - u32 (*rtw_systime_to_ms)(u32 systime); - u32 (*rtw_systime_to_sec)(u32 systime); - u32 (*rtw_ms_to_systime)(u32 ms); - u32 (*rtw_sec_to_systime)(u32 sec); - void (*rtw_msleep_os)(int ms); - void (*rtw_usleep_os)(int us); - void (*rtw_mdelay_os)(int ms); - void (*rtw_udelay_os)(int us); - void (*rtw_yield_os)(void); - void (*ATOMIC_SET)(ATOMIC_T *v, int i); - int (*ATOMIC_READ)(ATOMIC_T *v); - void (*ATOMIC_ADD)(ATOMIC_T *v, int i); - void (*ATOMIC_SUB)(ATOMIC_T *v, int i); - void (*ATOMIC_INC)(ATOMIC_T *v); - void (*ATOMIC_DEC)(ATOMIC_T *v); - int (*ATOMIC_ADD_RETURN)(ATOMIC_T *v, int i); - int (*ATOMIC_SUB_RETURN)(ATOMIC_T *v, int i); - int (*ATOMIC_INC_RETURN)(ATOMIC_T *v); - int (*ATOMIC_DEC_RETURN)(ATOMIC_T *v); - u64 (*rtw_modular64)(u64 x, u64 y); - int (*rtw_get_random_bytes)(void* dst, u32 size); - u32 (*rtw_getFreeHeapSize)(void); - int (*rtw_create_task)(struct task_struct *task, const char *name, u32 stack_size, u32 priority, thread_func_t func, void *thctx); - void (*rtw_delete_task)(struct task_struct *task); - void (*rtw_wakeup_task)(struct task_struct *task); - -#if 0 //TODO - void (*rtw_init_delayed_work)(struct delayed_work *dwork, work_func_t func, const char *name); - void (*rtw_deinit_delayed_work)(struct delayed_work *dwork); - int (*rtw_queue_delayed_work)(struct workqueue_struct *wq, struct delayed_work *dwork, unsigned long delay, void* context); - BOOLEAN (*rtw_cancel_delayed_work)(struct delayed_work *dwork); -#endif - void (*rtw_thread_enter)(char *name); - void (*rtw_thread_exit)(void); - _timerHandle (*rtw_timerCreate)( const signed char *pcTimerName, - osdepTickType xTimerPeriodInTicks, - u32 uxAutoReload, - void * pvTimerID, - TIMER_FUN pxCallbackFunction ); - u32 (*rtw_timerDelete)( _timerHandle xTimer, - osdepTickType xBlockTime ); - u32 (*rtw_timerIsTimerActive)( _timerHandle xTimer ); - u32 (*rtw_timerStop)( _timerHandle xTimer, - osdepTickType xBlockTime ); - u32 (*rtw_timerChangePeriod)( _timerHandle xTimer, - osdepTickType xNewPeriod, - osdepTickType xBlockTime ); - void* (*rtw_timerGetID)( _timerHandle xTimer ); - u32 (*rtw_timerStart)( _timerHandle xTimer, - osdepTickType xBlockTime ); - u32 (*rtw_timerStartFromISR)( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ); - - u32 (*rtw_timerStopFromISR)( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ); - - u32 (*rtw_timerResetFromISR)( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ); - - u32 (*rtw_timerChangePeriodFromISR)( _timerHandle xTimer, - osdepTickType xNewPeriod, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ); - - u32 (*rtw_timerReset)( _timerHandle xTimer, - osdepTickType xBlockTime ); - - void (*rtw_acquire_wakelock)(void); - void (*rtw_release_wakelock)(void); - void (*rtw_wakelock_timeout)(u32 timeoutMs); - u8 (*rtw_get_scheduler_state)(void); -}; - -#ifdef __cplusplus -} -#endif - -/*\@}*/ - -#endif //#ifndef __OSDEP_SERVICE_H_ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/tcm_heap.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/tcm_heap.h deleted file mode 100644 index 2047879c2e2..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/tcm_heap.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef STRUCT_HEAP_H -#define STRUCT_HEAP_H - -//#include -#include -#include - -/* NOTE: struct size must be a 2's power! */ -typedef struct _MemChunk -{ - struct _MemChunk *next; - int size; -} MemChunk; - -typedef MemChunk heap_buf_t; - -/// A heap -typedef struct Heap -{ - struct _MemChunk *FreeList; ///< Head of the free list -} Heap; - -/** - * Utility macro to allocate a heap of size \a size. - * - * \param name Variable name for the heap. - * \param size Heap size in bytes. - */ -#define HEAP_DEFINE_BUF(name, size) \ - heap_buf_t name[((size) + sizeof(heap_buf_t) - 1) / sizeof(heap_buf_t)] - -/// Initialize \a heap within the buffer pointed by \a memory which is of \a size bytes -void tcm_heap_init(void); - -/// Allocate a chunk of memory of \a size bytes from the heap -void *tcm_heap_allocmem(int size); - -/// Free a chunk of memory of \a size bytes from the heap -void tcm_heap_freemem(void *mem, int size); - -int tcm_heap_freeSpace(void); - -#define HNEW(heap, type) \ - (type*)tcm_heap_allocmem(heap, sizeof(type)) - -#define HNEWVEC(heap, type, nelem) \ - (type*)tcm_heap_allocmem(heap, sizeof(type) * (nelem)) - -#define HDELETE(heap, type, mem) \ - tcm_heap_freemem(heap, mem, sizeof(type)) - -#define HDELETEVEC(heap, type, nelem, mem) \ - tcm_heap_freemem(heap, mem, sizeof(type) * (nelem)) - - -/** - * \name Compatibility interface with C standard library - * \{ - */ -void *tcm_heap_malloc(int size); -void *tcm_heap_calloc(int size); -void tcm_heap_free(void * mem); -/** \} */ - - -#endif /* STRUCT_HEAP_H */ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c deleted file mode 100644 index 543b55524ab..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c +++ /dev/null @@ -1,1331 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - ******************************************************************************/ - -#include -#if CONFIG_USE_TCM_HEAP -#include "tcm_heap.h" -#endif - -#define OSDEP_DBG(x, ...) do {} while(0) - -extern struct osdep_service_ops osdep_service; - -#ifdef CONFIG_LITTLE_ENDIAN -u16 -_htons(u16 n) -{ - return ((n & 0xff) << 8) | ((n & 0xff00) >> 8); -} - -u16 -_ntohs(u16 n) -{ - return _htons(n); -} - -u32 -_htonl(u32 n) -{ - return ((n & 0xff) << 24) | - ((n & 0xff00) << 8) | - ((n & 0xff0000UL) >> 8) | - ((n & 0xff000000UL) >> 24); -} - -u32 -_ntohl(u32 n) -{ - return _htonl(n); -} - -#endif /* CONFIG_LITTLE_ENDIAN */ -/* -* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE -* @return: one of RTW_STATUS_CODE -*/ -int RTW_STATUS_CODE(int error_code) -{ - if(error_code >= 0) - return _SUCCESS; - - return _FAIL; -} - -u32 rtw_atoi(u8* s) -{ - int num=0,flag=0; - int i; - - for(i=0;i<=strlen((char *)s);i++) - { - if(s[i] >= '0' && s[i] <= '9') - num = num * 10 + s[i] -'0'; - else if(s[0] == '-' && i==0) - flag =1; - else - break; - } - - if(flag == 1) - num = num * -1; - - return(num); -} -#if CONFIG_USE_TCM_HEAP -void *tcm_heap_malloc(int size); -void *tcm_heap_calloc(int size); -#endif -u8* _rtw_vmalloc(u32 sz) -{ - u8 *pbuf = NULL; -#if CONFIG_USE_TCM_HEAP - pbuf = tcm_heap_malloc(sz); -#endif - if(pbuf==NULL){ - if(osdep_service.rtw_vmalloc) { - pbuf = osdep_service.rtw_vmalloc(sz); - } else - OSDEP_DBG("Not implement osdep service: rtw_vmalloc"); - } - return pbuf; -} - -u8* _rtw_zvmalloc(u32 sz) -{ - u8 *pbuf = NULL; -#if CONFIG_USE_TCM_HEAP - pbuf = tcm_heap_calloc(sz); -#endif - if(pbuf==NULL){ - if(osdep_service.rtw_zvmalloc) { - pbuf = osdep_service.rtw_zvmalloc(sz); - } else - OSDEP_DBG("Not implement osdep service: rtw_zvmalloc"); - } - return pbuf; -} - -void _rtw_vmfree(u8 *pbuf, u32 sz) -{ - -#if CONFIG_USE_TCM_HEAP - if( (u32)pbuf > 0x1FFF0000 && (u32)pbuf < 0x20000000 ) - tcm_heap_free(pbuf); - else -#endif - { - if(osdep_service.rtw_vmfree) { - osdep_service.rtw_vmfree(pbuf, sz); - } else - OSDEP_DBG("Not implement osdep service: rtw_vmfree"); - } -} - -u8* _rtw_malloc(u32 sz) -{ - if(osdep_service.rtw_malloc) { - u8 *pbuf = osdep_service.rtw_malloc(sz); - return pbuf; - } else - OSDEP_DBG("Not implement osdep service: rtw_malloc"); - - return NULL; -} - -u8* _rtw_zmalloc(u32 sz) -{ - if(osdep_service.rtw_zmalloc) { - u8 *pbuf = osdep_service.rtw_zmalloc(sz); - return pbuf; - } else - OSDEP_DBG("Not implement osdep service: rtw_zmalloc"); - - return NULL; -} - -void _rtw_mfree(u8 *pbuf, u32 sz) -{ - if(osdep_service.rtw_mfree) { - osdep_service.rtw_mfree(pbuf, sz); - } else - OSDEP_DBG("Not implement osdep service: rtw_mfree"); -} - -#ifdef CONFIG_MEM_MONITOR -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK -_list mem_table; -int mem_used_num; -#endif -int min_free_heap_size; - -void init_mem_monitor(_list *pmem_table, int *used_num) -{ -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - rtw_init_listhead(pmem_table); - *used_num = 0; -#endif - min_free_heap_size = rtw_getFreeHeapSize(); -} - -void deinit_mem_monitor(_list *pmem_table, int *used_num) -{ -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - _list *plist; - struct mem_entry *mem_entry; - - if(*used_num > 0) - DBG_ERR("Have %d mem_entry kept in monitor", *used_num); - else - DBG_INFO("No mem_entry kept in monitor"); - - save_and_cli(); - - while (rtw_end_of_queue_search(pmem_table, get_next(pmem_table)) == _FALSE) { - plist = get_next(pmem_table); - mem_entry = LIST_CONTAINOR(plist, struct mem_entry, list); - - DBG_ERR("Not release memory at %p with size of %d", mem_entry->ptr, mem_entry->size); - - rtw_list_delete(plist); - _rtw_mfree((u8 *) mem_entry, sizeof(struct mem_entry)); - } - - restore_flags(); -#endif -} - -void add_mem_usage(_list *pmem_table, void *ptr, int size, int *used_num, int flag) -{ - int free_heap_size = rtw_getFreeHeapSize(); -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - struct mem_entry *mem_entry; -#endif - if(ptr == NULL) { - DBG_ERR("Catch a mem alloc fail with size of %d, current heap free size = %d", size, free_heap_size); - return; - } - else{ - if(flag == MEM_MONITOR_FLAG_WPAS) { - DBG_INFO("Alloc memory at %p with size of %d", ptr, size); - } else { - DBG_INFO("Alloc memory at %p with size of %d", ptr, size); - } - } -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - mem_entry = (struct mem_entry *) _rtw_malloc(sizeof(struct mem_entry)); - - if(mem_entry == NULL) { - DBG_ERR("Fail to alloc mem_entry"); - return; - } - - memset(mem_entry, 0, sizeof(struct mem_entry)); - mem_entry->ptr = ptr; - mem_entry->size = size; - - save_and_cli(); - rtw_list_insert_head(&mem_entry->list, pmem_table); - restore_flags(); - - *used_num ++; -#endif - if(min_free_heap_size > free_heap_size) - min_free_heap_size = free_heap_size; -} - -void del_mem_usage(_list *pmem_table, void *ptr, int *used_num, int flag) -{ -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - _list *plist; - struct mem_entry *mem_entry = NULL; - - if(ptr == NULL) - return; - - if(flag == MEM_MONITOR_FLAG_WPAS) - DBG_INFO("Free memory at %p", ptr); - else - DBG_INFO("Free memory at %p", ptr); - - save_and_cli(); - - plist = get_next(pmem_table); - while ((rtw_end_of_queue_search(pmem_table, plist)) == _FALSE) - { - mem_entry = LIST_CONTAINOR(plist, struct mem_entry, list); - if(mem_entry->ptr == ptr) { - rtw_list_delete(plist); - break; - } - plist = get_next(plist); - } - - restore_flags(); - - if(plist == pmem_table) - DBG_ERR("Fail to find the mem_entry in mem table"); - else { - *used_num --; - _rtw_mfree((u8 *) mem_entry, sizeof(struct mem_entry)); - } -#endif -} - -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK -int get_mem_usage(_list *pmem_table) -{ - _list *plist; - struct mem_entry *mem_entry; - int mem_usage = 0; - int entry_num = 0; - - save_and_cli(); - - if((plist = get_next(pmem_table)) == NULL) { - DBG_ERR("No mem table available\n"); - restore_flags(); - return 0; - } - - while (rtw_end_of_queue_search(pmem_table, plist) == _FALSE) { - entry_num ++; - mem_entry = LIST_CONTAINOR(plist, struct mem_entry, list); - mem_usage += mem_entry->size; - - DBG_INFO("size of mem_entry(%d)=%d\n", entry_num, mem_entry->size); - plist = get_next(plist); - } - - restore_flags(); - - DBG_INFO("Get %d mem_entry\n", entry_num); - - return mem_usage; -} -#endif - - -u8* rtw_vmalloc(u32 sz) -{ - u8 *pbuf = _rtw_vmalloc(sz); -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - add_mem_usage(&mem_table, pbuf, sz, &mem_used_num, MEM_MONITOR_FLAG_WIFI_DRV); -#else - add_mem_usage(NULL, pbuf, sz, NULL, MEM_MONITOR_FLAG_WIFI_DRV); -#endif - return pbuf; -} - -u8* rtw_zvmalloc(u32 sz) -{ - u8 *pbuf = _rtw_zvmalloc(sz); -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - add_mem_usage(&mem_table, pbuf, sz, &mem_used_num, MEM_MONITOR_FLAG_WIFI_DRV); -#else - add_mem_usage(NULL, pbuf, sz, NULL, MEM_MONITOR_FLAG_WIFI_DRV); -#endif - return pbuf; -} - -void rtw_vmfree(u8 *pbuf, u32 sz) -{ - _rtw_vmfree(pbuf, sz); -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - del_mem_usage(&mem_table, pbuf, &mem_used_num, MEM_MONITOR_FLAG_WIFI_DRV); -#else - del_mem_usage(NULL, pbuf, NULL, MEM_MONITOR_FLAG_WIFI_DRV); -#endif -} - -u8* rtw_malloc(u32 sz) -{ - u8 *pbuf = _rtw_malloc(sz); -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - add_mem_usage(&mem_table, pbuf, sz, &mem_used_num, MEM_MONITOR_FLAG_WIFI_DRV); -#else - add_mem_usage(NULL, pbuf, sz, NULL, MEM_MONITOR_FLAG_WIFI_DRV); -#endif - return pbuf; -} - -u8* rtw_zmalloc(u32 sz) -{ - u8 *pbuf = _rtw_zmalloc(sz); -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - add_mem_usage(&mem_table, pbuf, sz, &mem_used_num, MEM_MONITOR_FLAG_WIFI_DRV); -#else - add_mem_usage(NULL, pbuf, sz, NULL, MEM_MONITOR_FLAG_WIFI_DRV); -#endif - return pbuf; -} - -void rtw_mfree(u8 *pbuf, u32 sz) -{ - _rtw_mfree(pbuf, sz); -#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK - del_mem_usage(&mem_table, pbuf, &mem_used_num, MEM_MONITOR_FLAG_WIFI_DRV); -#else - del_mem_usage(NULL, pbuf, NULL, MEM_MONITOR_FLAG_WIFI_DRV); -#endif -} -#endif - -void* rtw_malloc2d(int h, int w, int size) -{ - int j; - - void **a = (void **) rtw_zmalloc( h*sizeof(void *) + h*w*size ); - if(a == NULL) - { - OSDEP_DBG("%s: alloc memory fail!\n", __FUNCTION__); - return NULL; - } - - for( j=0; jqueue)); - rtw_spinlock_init(&(pqueue->lock)); -} - -u32 rtw_queue_empty(_queue *pqueue) -{ - return (rtw_is_list_empty(&(pqueue->queue))); -} - - -u32 rtw_end_of_queue_search(_list *head, _list *plist) -{ - if (head == plist) - return _TRUE; - else - return _FALSE; -} - -#if 1 -void rtw_spinlock_init(_lock *plock) -{ - if(osdep_service.rtw_spinlock_init) - osdep_service.rtw_spinlock_init(plock); - else - OSDEP_DBG("Not implement osdep service: rtw_spinlock_init"); -} - -void rtw_spinlock_free(_lock *plock) -{ - if(osdep_service.rtw_spinlock_free) - osdep_service.rtw_spinlock_free(plock); - else - OSDEP_DBG("Not implement osdep service: rtw_spinlock_free"); -} - -void rtw_spin_lock(_lock *plock) -{ - if(osdep_service.rtw_spin_lock) - osdep_service.rtw_spin_lock(plock); - else - OSDEP_DBG("Not implement osdep service: rtw_spin_lock"); -} - -void rtw_spin_unlock(_lock *plock) -{ - if(osdep_service.rtw_spin_unlock) - osdep_service.rtw_spin_unlock(plock); - else - OSDEP_DBG("Not implement osdep service: rtw_spin_unlock"); -} - -void rtw_spinlock_irqsave(_lock *plock, _irqL *irqL) -{ - if(osdep_service.rtw_spinlock_irqsave) - osdep_service.rtw_spinlock_irqsave(plock, irqL); - else - OSDEP_DBG("Not implement osdep service: rtw_spinlock_irqsave"); -} - -void rtw_spinunlock_irqsave(_lock *plock, _irqL *irqL) -{ - if(osdep_service.rtw_spinunlock_irqsave) - osdep_service.rtw_spinunlock_irqsave(plock, irqL); - else - OSDEP_DBG("Not implement osdep service: rtw_spinunlock_irqsave"); -} -#endif - -int rtw_init_xqueue( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages ) -{ - if(osdep_service.rtw_init_xqueue) - return (int)osdep_service.rtw_init_xqueue(queue, name, message_size, number_of_messages); - else - OSDEP_DBG("Not implement osdep service: rtw_init_xqueue"); - - return FAIL; -} - -int rtw_push_to_xqueue( _xqueue* queue, void* message, u32 timeout_ms ) -{ - if(osdep_service.rtw_push_to_xqueue) - return (int)osdep_service.rtw_push_to_xqueue(queue, message, timeout_ms); - else - OSDEP_DBG("Not implement osdep service: rtw_push_to_xqueue"); - - return FAIL; -} - -int rtw_pop_from_xqueue( _xqueue* queue, void* message, u32 timeout_ms ) -{ - if(osdep_service.rtw_pop_from_xqueue) - return (int)osdep_service.rtw_pop_from_xqueue(queue, message, timeout_ms); - else - OSDEP_DBG("Not implement osdep service: rtw_pop_from_xqueue"); - - return FAIL; -} - -int rtw_deinit_xqueue( _xqueue* queue ) -{ - if(osdep_service.rtw_deinit_xqueue) - return (int)osdep_service.rtw_deinit_xqueue(queue); - else - OSDEP_DBG("Not implement osdep service: rtw_deinit_xqueue"); - - return FAIL; -} - -#if 0 -void rtw_init_queue(_queue *pqueue) -{ - rtw_init_listhead(&(pqueue->queue)); - rtw_mutex_init(&(pqueue->lock)); -} - -void rtw_deinit_queue(_queue *pqueue) -{ - rtw_mutex_free(&(pqueue->lock)); -} - -u32 rtw_is_queue_empty(_queue *pqueue) -{ - return (rtw_is_list_empty(&(pqueue->queue))); -} - -u32 rtw_end_of_queue_search(_list *head, _list *plist) -{ - if (head == plist) - return _TRUE; - - return _FALSE; -} - -_list *rtw_get_queue_head(_queue *queue) -{ - return (&(queue->queue)); -} -#endif - -u32 rtw_get_current_time(void) -{ - if(osdep_service.rtw_get_current_time) - return osdep_service.rtw_get_current_time(); - else - OSDEP_DBG("Not implement osdep service: rtw_get_current_time"); - - return 0; -} - -u32 rtw_systime_to_ms(u32 systime) -{ - if(osdep_service.rtw_systime_to_ms) - return osdep_service.rtw_systime_to_ms(systime); - else - OSDEP_DBG("Not implement osdep service: rtw_systime_to_ms"); - - return 0; -} - -u32 rtw_systime_to_sec(u32 systime) -{ - if(osdep_service.rtw_systime_to_sec) - return osdep_service.rtw_systime_to_sec(systime); - else - OSDEP_DBG("Not implement osdep service: rtw_systime_to_sec"); - - return 0; -} - -u32 rtw_ms_to_systime(u32 ms) -{ - if(osdep_service.rtw_ms_to_systime) - return osdep_service.rtw_ms_to_systime(ms); - else - OSDEP_DBG("Not implement osdep service: rtw_ms_to_systime"); - - return 0; -} - -u32 rtw_sec_to_systime(u32 sec) -{ - if(osdep_service.rtw_sec_to_systime) - return osdep_service.rtw_sec_to_systime(sec); - else - OSDEP_DBG("Not implement osdep service: rtw_sec_to_systime"); - - return 0; -} - -// the input parameter start use the same unit as returned by rtw_get_current_time -s32 rtw_get_passing_time_ms(u32 start) -{ - return rtw_systime_to_ms(rtw_get_current_time() - start); -} - -s32 rtw_get_time_interval_ms(u32 start, u32 end) -{ - return rtw_systime_to_ms(end - start); -} - -void rtw_msleep_os(int ms) -{ - if(osdep_service.rtw_msleep_os) - osdep_service.rtw_msleep_os(ms); - else - OSDEP_DBG("Not implement osdep service: rtw_msleep_os"); -} - -void rtw_usleep_os(int us) -{ - if(osdep_service.rtw_usleep_os) - osdep_service.rtw_usleep_os(us); - else - OSDEP_DBG("Not implement osdep service: rtw_usleep_os"); -} - -void rtw_mdelay_os(int ms) -{ - if(osdep_service.rtw_mdelay_os) - osdep_service.rtw_mdelay_os(ms); - else - OSDEP_DBG("Not implement osdep service: rtw_mdelay_os"); -} - -void rtw_udelay_os(int us) -{ - if(osdep_service.rtw_udelay_os) - osdep_service.rtw_udelay_os(us); - else - OSDEP_DBG("Not implement osdep service: rtw_udelay_os"); -} - -void rtw_yield_os(void) -{ - if(osdep_service.rtw_yield_os) - osdep_service.rtw_yield_os(); - else - OSDEP_DBG("Not implement osdep service: rtw_yield_os"); -} - -void ATOMIC_SET(ATOMIC_T *v, int i) -{ - if(osdep_service.ATOMIC_SET) - osdep_service.ATOMIC_SET(v, i); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_SET"); -} - -int ATOMIC_READ(ATOMIC_T *v) -{ - if(osdep_service.ATOMIC_READ) - return osdep_service.ATOMIC_READ(v); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_READ"); - - return 0; -} - -void ATOMIC_ADD(ATOMIC_T *v, int i) -{ - if(osdep_service.ATOMIC_ADD) - osdep_service.ATOMIC_ADD(v, i); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_ADD"); -} - -void ATOMIC_SUB(ATOMIC_T *v, int i) -{ - if(osdep_service.ATOMIC_SUB) - osdep_service.ATOMIC_SUB(v, i); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_SUB"); -} - -void ATOMIC_INC(ATOMIC_T *v) -{ - if(osdep_service.ATOMIC_INC) - osdep_service.ATOMIC_INC(v); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_INC"); -} - -void ATOMIC_DEC(ATOMIC_T *v) -{ - if(osdep_service.ATOMIC_DEC) - osdep_service.ATOMIC_DEC(v); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_DEC"); -} - -int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) -{ - if(osdep_service.ATOMIC_ADD_RETURN) - return osdep_service.ATOMIC_ADD_RETURN(v, i); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_ADD_RETURN"); - - return 0; -} - -int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) -{ - if(osdep_service.ATOMIC_SUB_RETURN) - return osdep_service.ATOMIC_SUB_RETURN(v, i); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_SUB_RETURN"); - - return 0; -} - -int ATOMIC_INC_RETURN(ATOMIC_T *v) -{ - if(osdep_service.ATOMIC_INC_RETURN) - return osdep_service.ATOMIC_INC_RETURN(v); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_INC_RETURN"); - - return 0; -} - -int ATOMIC_DEC_RETURN(ATOMIC_T *v) -{ - if(osdep_service.ATOMIC_DEC_RETURN) - return osdep_service.ATOMIC_DEC_RETURN(v); - else - OSDEP_DBG("Not implement osdep service: ATOMIC_DEC_RETURN"); - - return 0; -} - -int ATOMIC_DEC_AND_TEST(ATOMIC_T *v) -{ - return ATOMIC_DEC_RETURN(v) == 0; -} - -u64 rtw_modular64(u64 x, u64 y) -{ - if(osdep_service.rtw_modular64) - return osdep_service.rtw_modular64(x, y); - else - OSDEP_DBG("Not implement osdep service: rtw_modular64"); - - return 0; -} - -int rtw_get_random_bytes(void* dst, u32 size) -{ - if(osdep_service.rtw_get_random_bytes) - return osdep_service.rtw_get_random_bytes(dst, size); - else - OSDEP_DBG("Not implement osdep service: rtw_get_random_bytes"); - - return 0; -} - -u32 rtw_getFreeHeapSize(void) -{ - if(osdep_service.rtw_getFreeHeapSize) - return osdep_service.rtw_getFreeHeapSize(); - else - OSDEP_DBG("Not implement osdep service: rtw_getFreeHeapSize"); - - return 0; -} - -int rtw_netif_queue_stopped(void *pnetdev) -{ - return 0; -} - -void rtw_netif_wake_queue(void *pnetdev) -{ -} - -void rtw_netif_start_queue(void *pnetdev) -{ -} - -void rtw_netif_stop_queue(void *pnetdev) -{ -} - -void flush_signals_thread(void) -{ -} - -void rtw_acquire_wakelock(void) -{ - if (osdep_service.rtw_acquire_wakelock) - osdep_service.rtw_acquire_wakelock(); - else - OSDEP_DBG("Not implement osdep service: rtw_acquire_wakelock"); -} - -void rtw_release_wakelock(void) -{ - if (osdep_service.rtw_release_wakelock) - osdep_service.rtw_release_wakelock(); - else - OSDEP_DBG("Not implement osdep service: rtw_release_wakelock"); -} - -void rtw_wakelock_timeout(u32 timeoutms) -{ - if (osdep_service.rtw_wakelock_timeout) - osdep_service.rtw_wakelock_timeout(timeoutms); - else - OSDEP_DBG("Not implement osdep service: rtw_wakelock_timeout"); -} - -int rtw_create_task(struct task_struct *task, const char *name, - u32 stack_size, u32 priority, thread_func_t func, void *thctx) -{ - if(osdep_service.rtw_create_task) - return osdep_service.rtw_create_task(task, name, stack_size, priority, func, thctx); - else - OSDEP_DBG("Not implement osdep service: rtw_create_task"); - return 1; -} -void rtw_delete_task(struct task_struct *task) -{ - if(osdep_service.rtw_delete_task) - osdep_service.rtw_delete_task(task); - else - OSDEP_DBG("Not implement osdep service: rtw_delete_task"); - - return; -} -void rtw_wakeup_task(struct task_struct *task) -{ - if(osdep_service.rtw_wakeup_task) - osdep_service.rtw_wakeup_task(task); - else - OSDEP_DBG("Not implement osdep service: rtw_wakeup_task"); - - return; -} - -static void worker_thread_main( void *arg ) -{ - rtw_worker_thread_t* worker_thread = (rtw_worker_thread_t*) arg; - - while ( 1 ) - { - rtw_event_message_t message; - - if ( rtw_pop_from_xqueue( &worker_thread->event_queue, &message, RTW_WAIT_FOREVER ) == SUCCESS ) - { - message.function(message.buf, message.buf_len, message.flags, message.user_data); - if(message.buf){ - //printf("\n!!!!!Free %p(%d)\n", message.buf, message.buf_len); - _rtw_mfree((u8 *)message.buf, message.buf_len); - } - } - } -} - -int rtw_create_worker_thread( rtw_worker_thread_t* worker_thread, u8 priority, u32 stack_size, u32 event_queue_size ) -{ - if(NULL == worker_thread) - return FAIL; - - memset( worker_thread, 0, sizeof( *worker_thread ) ); - - if ( rtw_init_xqueue( &worker_thread->event_queue, "worker queue", sizeof(rtw_event_message_t), event_queue_size ) != SUCCESS ) - { - return FAIL; - } - - if ( !rtw_create_task( &worker_thread->thread, "worker thread", stack_size, priority, worker_thread_main, (void*) worker_thread ) ) - { - rtw_deinit_xqueue( &worker_thread->event_queue ); - return FAIL; - } - - return SUCCESS; -} - -int rtw_delete_worker_thread( rtw_worker_thread_t* worker_thread ) -{ - if(NULL == worker_thread) - return FAIL; - - rtw_deinit_xqueue( &worker_thread->event_queue ); - - rtw_delete_task(&worker_thread->thread); - - return SUCCESS; -} - -_timerHandle rtw_timerCreate( const signed char *pcTimerName, - osdepTickType xTimerPeriodInTicks, - u32 uxAutoReload, - void * pvTimerID, - TIMER_FUN pxCallbackFunction ) -{ - if(osdep_service.rtw_timerCreate) - return osdep_service.rtw_timerCreate(pcTimerName, xTimerPeriodInTicks, uxAutoReload, - pvTimerID, pxCallbackFunction); - else - OSDEP_DBG("Not implement osdep service: rtw_timerCreate"); - - return 0; -} - -u32 rtw_timerDelete( _timerHandle xTimer, - osdepTickType xBlockTime ) -{ - if(osdep_service.rtw_timerDelete) - return osdep_service.rtw_timerDelete( xTimer, xBlockTime ); - else - OSDEP_DBG("Not implement osdep service: rtw_timerDelete"); - - return 0; -} - -u32 rtw_timerIsTimerActive( _timerHandle xTimer ) -{ - if(osdep_service.rtw_timerIsTimerActive) - return osdep_service.rtw_timerIsTimerActive(xTimer); - else - OSDEP_DBG("Not implement osdep service: rtw_timerIsTimerActive"); - - return 0; -} - -u32 rtw_timerStop( _timerHandle xTimer, - osdepTickType xBlockTime ) -{ - if(osdep_service.rtw_timerStop) - return osdep_service.rtw_timerStop(xTimer, xBlockTime); - else - OSDEP_DBG("Not implement osdep service: rtw_timerStop"); - - return 0; -} - -u32 rtw_timerChangePeriod( _timerHandle xTimer, - osdepTickType xNewPeriod, - osdepTickType xBlockTime ) -{ - if(osdep_service.rtw_timerChangePeriod) - return osdep_service.rtw_timerChangePeriod(xTimer, xNewPeriod, xBlockTime); - else - OSDEP_DBG("Not implement osdep service: rtw_timerChangePeriod"); - - return 0; -} - -void *rtw_timerGetID( _timerHandle xTimer ) -{ - if(osdep_service.rtw_timerGetID) - return osdep_service.rtw_timerGetID(xTimer); - else - OSDEP_DBG("Not implement osdep service: rtw_timerGetID"); - - return NULL; -} - -u32 rtw_timerStart( _timerHandle xTimer, osdepTickType xBlockTime ) -{ - if(osdep_service.rtw_timerStart) - return osdep_service.rtw_timerStart(xTimer, xBlockTime); - else - OSDEP_DBG("Not implement osdep service: rtw_timerStart"); - - return 0; -} - -u32 rtw_timerStartFromISR( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ) -{ - if(osdep_service.rtw_timerStartFromISR) - return osdep_service.rtw_timerStartFromISR(xTimer, pxHigherPriorityTaskWoken); - else - OSDEP_DBG("Not implement osdep service: rtw_timerStartFromISR"); - - return 0; -} - -u32 rtw_timerStopFromISR( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ) -{ - if(osdep_service.rtw_timerStopFromISR) - return osdep_service.rtw_timerStopFromISR(xTimer, pxHigherPriorityTaskWoken); - else - OSDEP_DBG("Not implement osdep service: rtw_timerStopFromISR"); - - return 0; -} - -u32 rtw_timerResetFromISR( _timerHandle xTimer, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ) -{ - if(osdep_service.rtw_timerResetFromISR) - return osdep_service.rtw_timerResetFromISR(xTimer, pxHigherPriorityTaskWoken); - else - OSDEP_DBG("Not implement osdep service: rtw_timerResetFromISR"); - - return 0; -} - -u32 rtw_timerChangePeriodFromISR( _timerHandle xTimer, - osdepTickType xNewPeriod, - osdepBASE_TYPE *pxHigherPriorityTaskWoken ) -{ - if(osdep_service.rtw_timerChangePeriodFromISR) - return osdep_service.rtw_timerChangePeriodFromISR(xTimer, xNewPeriod, pxHigherPriorityTaskWoken); - else - OSDEP_DBG("Not implement osdep service: rtw_timerChangePeriodFromISR"); - - return 0; -} - -u32 rtw_timerReset( _timerHandle xTimer, - osdepTickType xBlockTime ) -{ - if(osdep_service.rtw_timerReset) - return osdep_service.rtw_timerReset(xTimer, xBlockTime); - else - OSDEP_DBG("Not implement osdep service: rtw_timerReset"); - - return 0; -} - - -#if 0 //TODO -void rtw_init_delayed_work(struct delayed_work *dwork, work_func_t func, const char *name) -{ - if(osdep_service.rtw_init_delayed_work) - osdep_service.rtw_init_delayed_work(dwork, func, name); - else - OSDEP_DBG("Not implement osdep service: rtw_init_delayed_work"); - - return; -} - -void rtw_deinit_delayed_work(struct delayed_work *dwork) -{ - if(osdep_service.rtw_deinit_delayed_work) - osdep_service.rtw_deinit_delayed_work(dwork); - else - OSDEP_DBG("Not implement osdep service: rtw_deinit_delayed_work"); - - return; -} - -int rtw_queue_delayed_work(struct workqueue_struct *wq, - struct delayed_work *dwork, u32 delay, void* context) -{ - if(osdep_service.rtw_queue_delayed_work) - osdep_service.rtw_queue_delayed_work(wq, dwork, delay, context); - else - OSDEP_DBG("Not implement osdep service: rtw_queue_delayed_work"); - - return; -} - -BOOLEAN rtw_cancel_delayed_work(struct delayed_work *dwork) -{ - if(osdep_service.rtw_cancel_delayed_work) - osdep_service.rtw_cancel_delayed_work(dwork); - else - OSDEP_DBG("Not implement osdep service: rtw_cancel_delayed_work"); - - return; -} -#endif -void rtw_thread_enter(char *name) -{ - if(osdep_service.rtw_thread_enter) - osdep_service.rtw_thread_enter(name); - else - OSDEP_DBG("Not implement osdep service: rtw_thread_enter"); -} - -void rtw_thread_exit() -{ - if(osdep_service.rtw_thread_exit) - osdep_service.rtw_thread_exit(); - else - OSDEP_DBG("Not implement osdep service: rtw_thread_exit"); -} - -u8 rtw_get_scheduler_state() -{ - // OS_SCHEDULER_NOT_STARTED 0 - // OS_SCHEDULER_RUNNING 1 - // OS_SCHEDULER_SUSPENDED 2 - // OS_SCHEDULER_UNREACHABLE 3 - if(osdep_service.rtw_get_scheduler_state) - return osdep_service.rtw_get_scheduler_state(); - else{ - OSDEP_DBG("Not implement osdep service: rtw_get_scheduler_state"); - return 3; - } -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c deleted file mode 100644 index db4ed916387..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c +++ /dev/null @@ -1,370 +0,0 @@ -//#include -#include "tcm_heap.h" - -#include // memset() - -#include - -//#define _DEBUG - -#if CONFIG_USE_TCM_HEAP -#define FREE_FILL_CODE 0xDEAD -#define ALLOC_FILL_CODE 0xBEEF - -#define ROUND_UP2(x, pad) (((x) + ((pad) - 1)) & ~((pad) - 1)) - -#define TCM_HEAP_SIZE (40*1024) - -static struct Heap g_tcm_heap; - -#if defined (__ICCARM__) -#pragma location=".tcm.heap" -#else -__attribute__((section(".tcm.heap"))) -#endif -HEAP_DEFINE_BUF(tcm_heap, TCM_HEAP_SIZE); -//unsigned char tcm_heap[TCM_HEAP_SIZE]; - -static int g_heap_inited=0; -static _lock tcm_lock; -#if defined(PLATFORM_FREERTOS) -extern void vPortSetExtFree( void (*free)( void *p ), uint32_t upper, uint32_t lower ); -#elif defined(PLATFORM_CMSIS_RTOS) -extern void rtw_set_mfree_ext( void (*free)( void *p ), uint32_t upper, uint32_t lower ); -#endif -void tcm_heap_init(void) -{ - //#ifdef _DEBUG - //memset(memory, FREE_FILL_CODE, size); - //#endif - - //ASSERT2(((int)memory % alignof(heap_buf_t)) == 0, - //"memory buffer is unaligned, please use the HEAP_DEFINE_BUF() macro to declare heap buffers!\n"); - - /* Initialize heap with a single big chunk */ - g_tcm_heap.FreeList = (MemChunk *)&tcm_heap; - g_tcm_heap.FreeList->next = NULL; - g_tcm_heap.FreeList->size = sizeof(tcm_heap); - - g_heap_inited = 1; - rtw_spinlock_init(&tcm_lock); - -#if defined(PLATFORM_FREERTOS) - // let RTOS know how to free memory if using as task stack - vPortSetExtFree(tcm_heap_free, 0x20000000, 0x1fff0000); -#elif defined(PLATFORM_CMSIS_RTOS) - rtw_set_mfree_ext(tcm_heap_free, 0x20000000, 0x1fff0000); -#endif -} - -void tcm_heap_dump(void) -{ - MemChunk *chunk, *prev; - struct Heap* h = &g_tcm_heap; - - printf("---Free List--\n\r"); - for (prev = (MemChunk *)&h->FreeList, chunk = h->FreeList; - chunk; - prev = chunk, chunk = chunk->next) - { - printf(" prev %p, chunk %p, size %d \n\r", prev, chunk, chunk->size); - } - printf("--------------\n\r"); -} - -void *tcm_heap_allocmem(int size) -{ - MemChunk *chunk, *prev; - struct Heap* h = &g_tcm_heap; - _irqL irqL; - - rtw_enter_critical(&tcm_lock, &irqL); - - if(!g_heap_inited) tcm_heap_init(); - - /* Round size up to the allocation granularity */ - size = ROUND_UP2(size, sizeof(MemChunk)); - - /* Handle allocations of 0 bytes */ - if (!size) - size = sizeof(MemChunk); - - /* Walk on the free list looking for any chunk big enough to - * fit the requested block size. - */ - for (prev = (MemChunk *)&h->FreeList, chunk = h->FreeList; - chunk; - prev = chunk, chunk = chunk->next) - { - if (chunk->size >= size) - { - if (chunk->size == size) - { - /* Just remove this chunk from the free list */ - prev->next = chunk->next; - #ifdef _DEBUG - memset(chunk, ALLOC_FILL_CODE, size); - #endif - - rtw_exit_critical(&tcm_lock, &irqL); - //printf("----ALLOC1-----\n\r"); - //tcm_heap_dump(); - //printf("--------------\n\r"); - return (void *)chunk; - } - else - { - /* Allocate from the END of an existing chunk */ - chunk->size -= size; - #ifdef _DEBUG - memset((uint8_t *)chunk + chunk->size, ALLOC_FILL_CODE, size); - #endif - rtw_exit_critical(&tcm_lock, &irqL); - //printf("----ALLOC2-----\n\r"); - //tcm_heap_dump(); - //printf("--------------\n\r"); - - return (void *)((uint8_t *)chunk + chunk->size); - } - } - } - - rtw_exit_critical(&tcm_lock, &irqL); - //printf("----ALLOC3-----\n\r"); - //tcm_heap_dump(); - //printf("--------------\n\r"); - return NULL; /* fail */ -} - - -void tcm_heap_freemem(void *mem, int size) -{ - MemChunk *prev; - //ASSERT(mem); - struct Heap* h = &g_tcm_heap; - _irqL irqL; - - rtw_enter_critical(&tcm_lock, &irqL); - - if(!g_heap_inited) tcm_heap_init(); - -#ifdef _DEBUG - memset(mem, FREE_FILL_CODE, size); -#endif - - /* Round size up to the allocation granularity */ - size = ROUND_UP2(size, sizeof(MemChunk)); - - /* Handle allocations of 0 bytes */ - if (!size) - size = sizeof(MemChunk); - - /* Special cases: first chunk in the free list or memory completely full */ - //ASSERT((uint8_t*)mem != (uint8_t*)h->FreeList); - if (((uint8_t *)mem) < ((uint8_t *)h->FreeList) || !h->FreeList) - { - /* Insert memory block before the current free list head */ - prev = (MemChunk *)mem; - prev->next = h->FreeList; - prev->size = size; - h->FreeList = prev; - } - else /* Normal case: not the first chunk in the free list */ - { - /* - * Walk on the free list. Stop at the insertion point (when mem - * is between prev and prev->next) - */ - prev = h->FreeList; - while (prev->next < (MemChunk *)mem && prev->next) - prev = prev->next; - - /* Make sure mem is not *within* prev */ - //ASSERT((uint8_t*)mem >= (uint8_t*)prev + prev->size); - - /* Should it be merged with previous block? */ - if (((uint8_t *)prev) + prev->size == ((uint8_t *)mem)) - { - /* Yes */ - prev->size += size; - } - else /* not merged with previous chunk */ - { - MemChunk *curr = (MemChunk*)mem; - - /* insert it after the previous node - * and move the 'prev' pointer forward - * for the following operations - */ - curr->next = prev->next; - curr->size = size; - prev->next = curr; - - /* Adjust for the following test */ - prev = curr; - } - } - - /* Also merge with next chunk? */ - if (((uint8_t *)prev) + prev->size == ((uint8_t *)prev->next)) - { - prev->size += prev->next->size; - prev->next = prev->next->next; - - /* There should be only one merge opportunity, becuase we always merge on free */ - //ASSERT((uint8_t*)prev + prev->size != (uint8_t*)prev->next); - } - - rtw_exit_critical(&tcm_lock, &irqL); - //printf("---FREE %x--\n\r", mem); - //tcm_heap_dump(); - //printf("--------------\n\r"); - -} - -int tcm_heap_freeSpace(void) -{ - int free_mem = 0; - struct Heap* h = &g_tcm_heap; - _irqL irqL; - MemChunk *chunk; - - rtw_enter_critical(&tcm_lock, &irqL); - - if(!g_heap_inited) tcm_heap_init(); - - for (chunk = h->FreeList; chunk; chunk = chunk->next) - free_mem += chunk->size; - - rtw_exit_critical(&tcm_lock, &irqL); - return free_mem; -} - - -/** - * Standard malloc interface - */ -void *tcm_heap_malloc(int size) -{ -#if defined(PLATFORM_CMSIS_RTOS) - int64_t *mem; - // Make sure that block is 8-byte aligned - size = (size + 7U) & ~((uint32_t)7U); - size += sizeof(int64_t); - mem = (int64_t *)tcm_heap_allocmem(size); -#else - int *mem; - size += sizeof(int); - mem = (int*)tcm_heap_allocmem(size); -#endif - - - if (mem){ - *mem++ = size; - } - - return mem; -} - -/** - * Standard calloc interface - */ -void *tcm_heap_calloc(int size) -{ - void *mem; - mem = tcm_heap_malloc(size); - if (mem) - memset(mem, 0, size); - - return mem; -} - -/** - * Free a block of memory, determining its size automatically. - * - * \param h Heap from which the block was allocated. - * \param mem Pointer to a block of memory previously allocated with - * either heap_malloc() or heap_calloc(). - * - * \note If \a mem is a NULL pointer, no operation is performed. - * - * \note Freeing the same memory block twice has undefined behavior. - * - * \note This function works like the ANSI C free(). - */ -void tcm_heap_free(void *mem) -{ -#if defined(PLATFORM_CMSIS_RTOS) - int64_t *_mem = (int64_t *)mem; -#else - int *_mem = (int *)mem; -#endif - - if (_mem) - { - --_mem; - tcm_heap_freemem(_mem, *_mem); - } -} - - -static void alloc_test(int size, int test_len) -{ - //Simple test - uint8_t *a[100]; - int i, j; - - for (i = 0; i < test_len; i++) - { - a[i] = tcm_heap_allocmem(size); - //ASSERT(a[i]); - for (j = 0; j < size; j++) - a[i][j] = i; - } - - //ASSERT(heap_freeSpace(&h) == HEAP_SIZE - test_len * ROUND_UP2(size, sizeof(MemChunk))); - - for (i = 0; i < test_len; i++) - { - for (j = 0; j < size; j++) - { - printf("a[%d][%d] = %d\n", i, j, a[i][j]); - //ASSERT(a[i][j] == i); - } - tcm_heap_freemem(a[i], size); - } - //ASSERT(heap_freeSpace(&h) == HEAP_SIZE); -} - -#define ALLOC_SIZE 256 -#define ALLOC_SIZE2 1024 -#define TEST_LEN 20 -#define TEST_LEN2 10 -#define HEAP_SIZE 59*1024 -int tcm_heap_testRun(void) -{ - alloc_test(ALLOC_SIZE, TEST_LEN); - alloc_test(ALLOC_SIZE2, TEST_LEN2); - /* Try to allocate the whole heap */ - uint8_t *b = tcm_heap_allocmem(HEAP_SIZE); - int j; - //ASSERT(b); - //ASSERT(heap_freeSpace(&h) == 0); - - //ASSERT(!heap_allocmem(&h, HEAP_SIZE)); - - for (j = 0; j < HEAP_SIZE; j++) - b[j] = j; - - for (j = 0; j < HEAP_SIZE; j++) - { - printf("b[%d] = %d\n", j, j); - //ASSERT(b[j] == (j & 0xff)); - } - tcm_heap_freemem(b, HEAP_SIZE); - //ASSERT(heap_freeSpace(&h) == HEAP_SIZE); - - return 0; -} - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h deleted file mode 100644 index 1a0127a896a..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_ADC_H_ -#define _HAL_ADC_H_ - -#include "rtl8195a.h" -#include "rtl8195a_adc.h" -#include "hal_gdma.h" - -//================ ADC Configuration ========================= -#define ADC_INTR_OP_TYPE 1 -#define ADC_DMA_OP_TYPE 1 - -// ADC SAL management macros -#define SAL_ADC_USER_CB_NUM (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT)) - -// ADC used module. -// Please set the ADC module flag to 1 to enable the related -#define ADC0_USED 1 -#define ADC1_USED 1 -#define ADC2_USED 1 -#define ADC3_USED 1 - - -//================ Debug MSG Definition ======================= -#define ADC_PREFIX "RTL8195A[adc]: " -#define ADC_PREFIX_LVL " [ADC_DBG]: " - -enum _ADC_DBG_LVL_ { - HAL_ADC_LVL = 0x01, - SAL_ADC_LVL = 0x02, - VERI_ADC_LVL = 0x04, -}; -typedef uint32_t ADC_DBG_LVL; -typedef uint32_t * PADC_DBG_LVL; - -#ifdef CONFIG_DEBUG_LOG -#ifdef CONFIG_DEBUG_LOG_ADC_HAL - - #define DBG_8195A_ADC(...) do{ \ - _DbgDump("\r"ADC_PREFIX __VA_ARGS__);\ - }while(0) - - - #define ADCDBGLVL 0xFF - #define DBG_8195A_ADC_LVL(LVL,...) do{\ - if (LVL&ADCDBGLVL){\ - _DbgDump("\r"ADC_PREFIX_LVL __VA_ARGS__);\ - }\ - }while(0) -#else - #define DBG_ADC_LOG_PERD 100 - #define DBG_8195A_ADC(...) - #define DBG_8195A_ADC_LVL(...) -#endif -#endif - - -//================ ADC HAL Related Enumeration ================== -// ADC Module Selection -enum _ADC_MODULE_SEL_ { - ADC0_SEL = 0x0, - ADC1_SEL = 0x1, - ADC2_SEL = 0x2, - ADC3_SEL = 0x3, -}; -typedef uint32_t ADC_MODULE_SEL; -typedef uint32_t * PADC_MODULE_SEL; - -// ADC module status -enum _ADC_MODULE_STATUS_ { - ADC_DISABLE = 0x0, - ADC_ENABLE = 0x1, -}; -typedef uint32_t ADC_MODULE_STATUS; -typedef uint32_t * PADC_MODULE_STATUS; - -// ADC Data Endian -enum _ADC_DATA_ENDIAN_ { - ADC_DATA_ENDIAN_LITTLE = 0x0, - ADC_DATA_ENDIAN_BIG = 0x1, -}; -typedef uint32_t ADC_DATA_ENDIAN; -typedef uint32_t * PADC_DATA_ENDIAN; - -// ADC Debug Select -enum _ADC_DEBUG_SEL_ { - ADC_DBG_SEL_DISABLE = 0x0, - ADC_DBG_SEL_ENABLE = 0x1, -}; -typedef uint32_t ADC_DEBUG_SEL; -typedef uint32_t * PADC_DEBUG_SEL; - -enum _ADC_COMPARE_SET_ { - ADC_COMP_SMALLER_THAN = 0x0, - ADC_COMP_GREATER_THAN = 0x1, -}; -typedef uint32_t ADC_COMPARE_SET; -typedef uint32_t * PADC_COMPARE_SET; - -// ADC feature status -enum _ADC_FEATURE_STATUS_{ - ADC_FEATURE_DISABLED = 0, - ADC_FEATURE_ENABLED = 1, -}; -typedef uint32_t ADC_FEATURE_STATUS; -typedef uint32_t * PADC_FEATURE_STATUS; - -// ADC operation type -enum _ADC_OP_TYPE_ { - ADC_RDREG_TYPE = 0x0, - ADC_DMA_TYPE = 0x1, - ADC_INTR_TYPE = 0x2, -}; -typedef uint32_t ADC_OP_TYPE; -typedef uint32_t * PADC_OP_TYPE; - -// ADC device status -enum _ADC_DEVICE_STATUS_ { - ADC_STS_UNINITIAL = 0x00, - ADC_STS_INITIALIZED = 0x01, - ADC_STS_IDLE = 0x02, - - ADC_STS_TX_READY = 0x03, - ADC_STS_TX_ING = 0x04, - - ADC_STS_RX_READY = 0x05, - ADC_STS_RX_ING = 0x06, - - ADC_STS_ERROR = 0x07, - ADC_STS_FULL = 0x08, -}; -typedef uint32_t ADC_DEVICE_STATUS; -typedef uint32_t * PADC_DEVICE_STATUS; - -// ADC error type -enum _ADC_ERR_TYPE_ { - ADC_ERR_FIFO_RD_ERROR = 0x40, //ADC FIFO read error -}; -typedef uint32_t ADC_ERR_TYPE; -typedef uint32_t * PADC_ERR_TYPE; - -// ADC initial status -enum _ADC_INITAIL_STATUS_ { - ADC0_INITED = 0x1, - ADC1_INITED = 0x2, - ADC2_INITED = 0x4, - ADC3_INITED = 0x8, -}; -typedef uint32_t ADC_INITAIL_STATUS; -typedef uint32_t * PADC_INITAIL_STATUS; - - -//================ ADC HAL Data Structure ====================== -// ADC HAL initial data structure -typedef struct _HAL_ADC_INIT_DAT_ { - u8 ADCIdx; //ADC index used - u8 ADCEn; //ADC module enable - u8 ADCEndian; //ADC endian selection, - //but actually it's for 32-bit ADC data swap control - //1'b0: no swap, - //1'b1: swap the upper 16-bit and the lower 16-bit - u8 ADCBurstSz; //ADC DMA operation threshold - - u8 ADCCompOnly; //ADC compare mode only enable (without FIFO enable) - u8 ADCOneShotEn; //ADC one-shot mode enable - u8 ADCOverWREn; //ADC overwrite mode enable - u8 ADCOneShotTD; //ADC one shot mode threshold - - u16 ADCCompCtrl; //ADC compare mode control, - //1'b0:less than the compare threshold - //1'b1:greater than the compare threshod - u16 ADCCompTD; //ADC compare mode threshold - - u8 ADCDataRate; //ADC down sample data rate, - u8 ADCAudioEn; //ADC audio mode enable - u8 ADCEnManul; //ADC enable manually - u8 ADCDbgSel; - - u32 RSVD0; - - u32 *ADCData; //ADC data pointer - u32 ADCPWCtrl; //ADC0 power control - u32 ADCIntrMSK; //ADC Interrupt Mask - u32 ADCAnaParAd3; //ADC analog parameter 3 - u32 ADCInInput; //ADC Input is internal? -}HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT; - -// ADC HAL Operations -typedef struct _HAL_ADC_OP_ { - RTK_STATUS (*HalADCInit) (VOID *Data); //HAL ADC initialization - RTK_STATUS (*HalADCDeInit) (VOID *Data); //HAL ADC de-initialization - RTK_STATUS (*HalADCEnable) (VOID *Data); //HAL ADC de-initialization - u32 (*HalADCReceive) (VOID *Data); //HAL ADC receive - RTK_STATUS (*HalADCIntrCtrl) (VOID *Data); //HAL ADC interrupt control - u32 (*HalADCReadReg) (VOID *Data, u8 ADCReg);//HAL ADC read register -}HAL_ADC_OP, *PHAL_ADC_OP; - -// ADC user callback adapter -typedef struct _SAL_ADC_USERCB_ADPT_ { - VOID (*USERCB) (VOID *Data); - u32 USERData; -}SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT; - -// ADC user callback structure -typedef struct _SAL_ADC_USER_CB_ { - PSAL_ADC_USERCB_ADPT pRXCB; //ADC Receive Callback - PSAL_ADC_USERCB_ADPT pRXCCB; //ADC Receive Complete Callback - PSAL_ADC_USERCB_ADPT pERRCB; //ADC Error Callback - PSAL_ADC_USERCB_ADPT pIDMARXCCB; //ADC Error Callback - PSAL_ADC_USERCB_ADPT pDMARXCB; //ADC DMA Receive Callback - PSAL_ADC_USERCB_ADPT pDMARXCCB; //ADC DMA Receive Complete Callback -}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB; - -// ADC Transmit Buffer -typedef struct _SAL_ADC_TRANSFER_BUF_ { - u32 DataLen; //ADC Transmfer Length - u32 *pDataBuf; //ADC Transfer Buffer Pointer - u16 *pUserDataBuf; // -}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF; - -typedef struct _SAL_ADC_DMA_USER_DEF_ { - - u8 TxDatSrcWdth; - u8 TxDatDstWdth; - u8 TxDatSrcBstSz; - u8 TxDatDstBstSz; - - u8 TxChNo; - u8 LlpCtrl; - u16 RSVD0; - - u32 MaxMultiBlk; - u32 pLlix; - u32 pBlockSizeList; -}SAL_ADC_DMA_USER_DEF, *PSAL_ADC_DMA_USER_DEF; - -// Software API Level ADC Handler -typedef struct _SAL_ADC_HND_ { - u8 DevNum; //ADC device number - u8 PinMux; //ADC pin mux seletion - u8 OpType; //ADC operation type selection - volatile u8 DevSts; //ADC device status - - u32 ADCExd; //ADC extended options: - //bit 0: example - //bit 31~bit 1: Reserved - u32 ErrType; // - u32 TimeOut; //ADC IO Timeout count - - PHAL_ADC_INIT_DAT pInitDat; //Pointer to ADC initial data struct - PSAL_ADC_TRANSFER_BUF pRXBuf; //Pointer to ADC TX buffer - PSAL_ADC_USER_CB pUserCB; //Pointer to ADC User Callback -}SAL_ADC_HND, *PSAL_ADC_HND; - -// ADC SAL handle private -typedef struct _SAL_ADC_HND_PRIV_ { - VOID **ppSalADCHnd; //Pointer to SAL_ADC_HND pointer - SAL_ADC_HND SalADCHndPriv; //Private SAL_ADC_HND -}SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV; - -//ADC SAL management adapter -typedef struct _SAL_ADC_MNGT_ADPT_ { - PSAL_ADC_HND_PRIV pSalHndPriv; //Pointer to SAL_ADC_HND - PHAL_ADC_INIT_DAT pHalInitDat; //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT ) - PHAL_ADC_OP pHalOp; //Pointer to HAL ADC operation( HAL_ADC_OP ) - VOID (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function - - PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE ) - VOID (*pSalIrqFunc)(VOID*); //Used for SAL ADC interrupt function - - PSAL_ADC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config - PHAL_GDMA_ADAPTER pHalGdmaAdp; - PHAL_GDMA_OP pHalGdmaOp; - PIRQ_HANDLE pIrqGdmaHnd; - VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function - PSAL_ADC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_ADC_USER_CB ) - VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function -}SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT; - - -//================ ADC HAL Function Prototype =================== -// ADC HAL inline function -// For checking I2C input index valid or not -static inline RTK_STATUS -RtkADCIdxChk( - IN u8 ADCIdx -) -{ -#if !ADC0_USED - if (ADCIdx == ADC0_SEL) - return _EXIT_FAILURE; -#endif - -#if !ADC1_USED - if (ADCIdx == ADC1_SEL) - return _EXIT_FAILURE; -#endif - -#if !ADC2_USED - if (ADCIdx == ADC2_SEL) - return _EXIT_FAILURE; -#endif - -#if !ADC3_USED - if (ADCIdx == ADC3_SEL) - return _EXIT_FAILURE; -#endif - ADCIdx++; //for compile warning. - return _EXIT_SUCCESS; -} - -VOID HalADCOpInit(IN VOID *Data); -PSAL_ADC_HND RtkADCGetSalHnd(IN u8 DACIdx); -RTK_STATUS RtkADCFreeSalHnd(IN PSAL_ADC_HND pSalADCHND); -RTK_STATUS RtkADCLoadDefault(IN VOID *Data); -RTK_STATUS RtkADCInit(IN VOID *Data); -RTK_STATUS RtkADCDeInit(IN VOID *Data); -//RTK_STATUS RtkADCReceive(IN VOID *Data); -u32 RtkADCReceive(IN VOID *Data); -u32 RtkADCReceiveBuf(IN VOID *Data,IN u32 *pBuf); -u32 RtkADCRxManualRotate(IN VOID *Data,IN u32 *pBuf); - -PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN u8 ADCIdx); -RTK_STATUS RtkADCFreeMngtAdpt(IN PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt); -VOID ADCISRHandle(IN VOID *Data); -VOID ADCGDMAISRHandle(IN VOID *Data); -HAL_Status RtkADCDisablePS(IN VOID *Data); -HAL_Status RtkADCEnablePS(IN VOID *Data); -extern VOID QueryRegPwrState(IN u8 FuncIdx,OUT u8* RegState,OUT u8* HwState); -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_api.h deleted file mode 100644 index 08afb79acce..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_api.h +++ /dev/null @@ -1,132 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _HAL_API_H_ -#define _HAL_API_H_ - -#include "basic_types.h" -#include "hal_irqn.h" - -#define HAL_READ32(base, addr) \ - rtk_le32_to_cpu(*((volatile u32*)(base + addr))) - -#define HAL_WRITE32(base, addr, value32) \ - ((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32)) - - -#define HAL_READ16(base, addr) \ - rtk_le16_to_cpu(*((volatile u16*)(base + addr))) - -#define HAL_WRITE16(base, addr, value) \ - ((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value)) - - -#define HAL_READ8(base, addr) \ - (*((volatile u8*)(base + addr))) - -#define HAL_WRITE8(base, addr, value) \ - ((*((volatile u8*)(base + addr))) = value) - -#if 0 -// These "extern _LONG_CALL_" function declaration are for RAM code building only -// For ROM code building, thses code should be marked off -extern _LONG_CALL_ u8 -HalPinCtrlRtl8195A( - IN u32 Function, - IN u32 PinLocation, - IN BOOL Operation - ); - -extern _LONG_CALL_ VOID -HalSerialPutcRtl8195a( - IN u8 c - ); - -extern _LONG_CALL_ u8 -HalSerialGetcRtl8195a( - IN BOOL PullMode - ); - -extern _LONG_CALL_ u32 -HalSerialGetIsrEnRegRtl8195a(VOID); - -extern _LONG_CALL_ VOID -HalSerialSetIrqEnRegRtl8195a ( - IN u32 SetValue - ); - -extern _LONG_CALL_ VOID -VectorTableInitForOSRtl8195A( - IN VOID *PortSVC, - IN VOID *PortPendSVH, - IN VOID *PortSysTick - ); - -extern _LONG_CALL_ BOOL -VectorIrqRegisterRtl8195A( - IN PIRQ_HANDLE pIrqHandle - ); - -extern _LONG_CALL_ BOOL -VectorIrqUnRegisterRtl8195A( - IN PIRQ_HANDLE pIrqHandle - ); - -extern _LONG_CALL_ VOID -VectorIrqEnRtl8195A( - IN PIRQ_HANDLE pIrqHandle - ); - -extern _LONG_CALL_ VOID -VectorIrqDisRtl8195A( - IN PIRQ_HANDLE pIrqHandle - ); -#endif - -extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode); -extern VOID InitWDGIRQ(VOID); - -#define PinCtrl HalPinCtrlRtl8195A - -#define DiagPutChar HalSerialPutcRtl8195a -#define DiagGetChar HalSerialGetcRtl8195a -#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a -#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a - -#define InterruptForOSInit VectorTableInitForOSRtl8195A -#define InterruptRegister VectorIrqRegisterRtl8195A -#define InterruptUnRegister VectorIrqUnRegisterRtl8195A - -#define InterruptEn VectorIrqEnRtl8195A -#define InterruptDis VectorIrqDisRtl8195A - -#define SpicFlashInit SpicFlashInitRtl8195A -#define Calibration32k En32KCalibration -#define WDGInit InitWDGIRQ - -enum _HAL_Status -{ - HAL_OK = 0x00, - HAL_BUSY = 0x01, - HAL_TIMEOUT = 0x02, - HAL_ERR_PARA = 0x03, // error with invaild parameters - HAL_ERR_MEM = 0x04, // error with memory allocation failed - HAL_ERR_HW = 0x05, // error with hardware error - - HAL_ERR_UNKNOWN = 0xee // unknown error - -}; -typedef uint32_t HAL_Status; - - -#endif //_HAL_API_H_ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_common.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_common.h deleted file mode 100644 index 113c1a185af..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_common.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Routines to access hardware - * - * Copyright (c) 2013 Realtek Semiconductor Corp. - * - * This module is a confidential and proprietary property of RealTek and - * possession or use of this module requires written permission of RealTek. - */ - -#ifndef _HAL_COMMON_H_ -#define _HAL_COMMON_H_ - -//================= Function Prototype START =================== -HAL_Status HalCommonInit(void); -//================= Function Prototype END =================== - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_dac.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_dac.h deleted file mode 100644 index 97c6dd06afa..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_dac.h +++ /dev/null @@ -1,339 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _HAL_DAC_H_ -#define _HAL_DAC_H_ - -#include "rtl8195a.h" -#include "rtl8195a_dac.h" -#include "hal_api.h" -#include "hal_gdma.h" - -//================ DAC Configuration ========================= -#define DAC_INTR_OP_TYPE 1 -#define DAC_DMA_OP_TYPE 1 - -// DAC SAL management macros -#define SAL_DAC_USER_CB_NUM (sizeof(SAL_DAC_USER_CB) / sizeof(PSAL_DAC_USERCB_ADPT)) - -// DAC SAL used module. -// Please set the DAC module flag to 1 to enable the related DAC module functions. -#define DAC0_USED 1 -#define DAC1_USED 1 - - -//================ Debug MSG Definition ======================= -#define DAC_PREFIX "RTL8195A[dac]: " -#define DAC_PREFIX_LVL " [DAC_DBG]: " - -enum _DAC_DBG_LVL_ { - HAL_DAC_LVL = 0x00, - SAL_DAC_LVL = 0x02, - VERI_DAC_LVL = 0x04, -}; -typedef uint32_t DAC_DBG_LVL; -typedef uint32_t * PDAC_DBG_LVL; - -#ifdef CONFIG_DEBUG_LOG -#ifdef CONFIG_DEBUG_LOG_DAC_HAL - - #define DBG_8195A_DAC(...) do{ \ - _DbgDump("\r"DAC_PREFIX __VA_ARGS__);\ - }while(0) - - - #define DACDBGLVL 0xFF - #define DBG_8195A_DAC_LVL(LVL,...) do{\ - if (LVL&DACDBGLVL){\ - _DbgDump("\r"DAC_PREFIX_LVL __VA_ARGS__);\ - }\ - }while(0) -#else - #define DBG_DAC_LOG_PERD 100 - #define DBG_8195A_DAC(...) - #define DBG_8195A_DAC_LVL(...) -#endif -#endif - - -//================ DAC HAL Related Enumeration ================== -// DAC Module Selection -enum _DAC_MODULE_SEL_ { - DAC0_SEL = 0x0, - DAC1_SEL = 0x1, -}; -typedef uint32_t DAC_MODULE_SEL; -typedef uint32_t * PDAC_MODULE_SEL; - -// DAC module status -enum _DAC_MODULE_STATUS_ { - DAC_DISABLE = 0x0, - DAC_ENABLE = 0x1, -}; -typedef uint32_t DAC_MODULE_STATUS; -typedef uint32_t * PDAC_MODULE_STATUS; - -// DAC Data Rate -enum _DAC_DATA_RATE_ { - DAC_DATA_RATE_10K = 0x0, - DAC_DATA_RATE_250K = 0x1, -}; -typedef uint32_t DAC_DATA_RATE; -typedef uint32_t * PDAC_DATA_RATE; - -// DAC Data Endian -enum _DAC_DATA_ENDIAN_ { - DAC_DATA_ENDIAN_LITTLE = 0x0, - DAC_DATA_ENDIAN_BIG = 0x1, -}; -typedef uint32_t DAC_DATA_ENDIAN; -typedef uint32_t * PDAC_DATA_ENDIAN; - -// DAC Debug Select -enum _DAC_DEBUG_SEL_ { - DAC_DBG_SEL_DISABLE = 0x0, - DAC_DBG_SEL_ENABLE = 0x1, -}; -typedef uint32_t DAC_DEBUG_SEL; -typedef uint32_t *PDAC_DEBUG_SEL; - -// DAC Dsc Debug Select -enum _DAC_DSC_DEBUG_SEL_ { - DAC_DSC_DBG_SEL_DISABLE = 0x0, - DAC_DSC_DBG_SEL_ENABLE = 0x1, -}; -typedef uint32_t DAC_DSC_DEBUG_SEL; -typedef uint32_t * PDAC_DSC_DEBUG_SEL; - - -// DAC Bypass Dsc Debug Select -enum _DAC_BYPASS_DSC_SEL_ { - DAC_BYPASS_DSC_SEL_DISABLE = 0x0, - DAC_BYPASS_DSC_SEL_ENABLE = 0x1, -}; -typedef uint32_t DAC_BYPASS_DSC_SEL; -typedef uint32_t * PDAC_BYPASS_DSC_SEL; - -// DAC feature status -enum _DAC_FEATURE_STATUS_{ - DAC_FEATURE_DISABLED = 0, - DAC_FEATURE_ENABLED = 1, -}; -typedef uint32_t DAC_FEATURE_STATUS; -typedef uint32_t * PDAC_FEATURE_STATUS; - -// DAC operation type -enum _DAC_OP_TYPE_ { - DAC_POLL_TYPE = 0x0, - DAC_DMA_TYPE = 0x1, - DAC_INTR_TYPE = 0x2, -}; -typedef uint32_t DAC_OP_TYPE; -typedef uint32_t * PDAC_OP_TYPE; - -// DAC device status -enum _DAC_Device_STATUS_ { - DAC_STS_UNINITIAL = 0x00, - DAC_STS_INITIALIZED = 0x01, - DAC_STS_IDLE = 0x02, - - DAC_STS_TX_READY = 0x03, - DAC_STS_TX_ING = 0x04, - - DAC_STS_RX_READY = 0x05, - DAC_STS_RX_ING = 0x06, - - DAC_STS_ERROR = 0x07, -}; -typedef uint32_t DAC_Device_STATUS; -typedef uint32_t * PDAC_Device_STATUS; - -//DAC device error type -enum _DAC_ERR_TYPE_ { - DAC_ERR_FIFO_OVER = 0x04, //DAC FIFO overflow. - DAC_ERR_FIFO_STOP = 0x08, //DAC FIFO is completely empty, and it will be stopped automatically. - DAC_ERR_FIFO_WRFAIL = 0x10, //When DAC is NOT enabled, a write operation attempts to access DAC register. - DAC_ERR_FIFO_DSC_OVER0 = 0x20, - DAC_ERR_FIFO_DSC_OVER1 = 0x40, -}; -typedef uint32_t DAC_ERR_TYPE; -typedef uint32_t * PDAC_ERR_TYPE; - -// DAC data input method -enum _DAC_INPUT_TYPE_{ - DAC_INPUT_SINGLE_WR = 0x1, //DAC input by using single register write - DAC_INPUT_DMA_ONEBLK = 0x2, //DAC input by using single DMA block - DAC_INPUT_DMA_LLP = 0x3, //DAC input by using DMA linked list mode -}; -typedef uint32_t DAC_INPUT_TYPE; -typedef uint32_t * PDAC_INPUT_TYPE; - - - - -//====================================================== -// DAC HAL initial data structure -typedef struct _HAL_DAC_INIT_DAT_ { - u8 DACIdx; //DAC index used - u8 DACEn; //DAC module enable - u8 DACDataRate; //DAC data rate, 1'b0:10KHz, 1'b1:250KHz - u8 DACEndian; //DAC endian selection, - //but actually it's for 32-bit DAC data swap control - //1'b0: no swap, - //1'b1: swap the upper 16-bit and the lower 16-bit - u8 DACFilterSet; //DAC filter settle - u8 DACBurstSz; //DAC burst size - u8 DACDbgSel; //DAC debug sel - u8 DACDscDbgSel; //DAC debug dsc sel - - u8 DACBPDsc; //DAC bypass delta sigma for loopback - u8 DACDeltaSig; //DAC bypass value of delta sigma - u16 RSVD1; - - - - u32 *DACData; //DAC data pointer - u32 DACPWCtrl; //DAC0 and DAC1 power control - u32 DACAnaCtrl0; //DAC anapar_da control 0 - u32 DACAnaCtrl1; //DAC anapar_da control 1 - u32 DACIntrMSK; //DAC Interrupt Mask -}HAL_DAC_INIT_DAT,*PHAL_DAC_INIT_DAT; - -// DAC HAL Operations -typedef struct _HAL_DAC_OP_ { - RTK_STATUS (*HalDACInit) (VOID *Data); //HAL DAC initialization - RTK_STATUS (*HalDACDeInit) (VOID *Data); //HAL DAC de-initialization - RTK_STATUS (*HalDACEnable) (VOID *Data); //HAL DAC de-initialization - u8 (*HalDACSend) (VOID *Data); //HAL DAC receive - RTK_STATUS (*HalDACIntrCtrl) (VOID *Data); //HAL DAC interrupt control - u32 (*HalDACReadReg) (VOID *Data, u8 DACReg);//HAL DAC read register -}HAL_DAC_OP, *PHAL_DAC_OP; - -// DAC user callback adapter -typedef struct _SAL_DAC_USERCB_ADPT_ { - VOID (*USERCB) (VOID *Data); - u32 USERData; -}SAL_DAC_USERCB_ADPT, *PSAL_DAC_USERCB_ADPT; - -// DAC user callback structure -typedef struct _SAL_DAC_USER_CB_ { - PSAL_DAC_USERCB_ADPT pTXCB; //DAC Transmit Callback - PSAL_DAC_USERCB_ADPT pTXCCB; //DAC Transmit Complete Callback - PSAL_DAC_USERCB_ADPT pERRCB; //DAC Error Callback - PSAL_DAC_USERCB_ADPT pDMATXCB; //DAC DMA Transmit Callback - PSAL_DAC_USERCB_ADPT pDMATXCCB; //DAC DMA Transmit Complete Callback -}SAL_DAC_USER_CB, *PSAL_DAC_USER_CB; - -// DAC Transmit Buffer -typedef struct _SAL_DAC_TRANSFER_BUF_ { - u32 DataLen; //DAC Transmfer Length - u32 *pDataBuf; //DAC Transfer Buffer Pointer - u32 RSVD; // -}SAL_DAC_TRANSFER_BUF,*PSAL_DAC_TRANSFER_BUF; - -typedef struct _SAL_DAC_DMA_USER_DEF_ { - - u8 TxDatSrcWdth; - u8 TxDatDstWdth; - u8 TxDatSrcBstSz; - u8 TxDatDstBstSz; - - u8 TxChNo; - u8 LlpCtrl; - u16 RSVD0; - - u32 MaxMultiBlk; - u32 pLlix; - u32 pBlockSizeList; -}SAL_DAC_DMA_USER_DEF, *PSAL_DAC_DMA_USER_DEF; - -// Software API Level DAC Handler -typedef struct _SAL_DAC_HND_ { - u8 DevNum; //DAC device number - u8 PinMux; //DAC pin mux seletion - u8 OpType; //DAC operation type selection - volatile u8 DevSts; //DAC device status - - u8 DACInType; //DAC input type - u8 RSVD0; - u16 RSVD1; - - u32 DACExd; //DAC extended options: - //bit 0: example - //bit 31~bit 1: Reserved - u32 ErrType; // - u32 TimeOut; //DAC IO Timeout count - - PHAL_DAC_INIT_DAT pInitDat; //Pointer to DAC initial data struct - PSAL_DAC_TRANSFER_BUF pTXBuf; //Pointer to DAC TX buffer - PSAL_DAC_USER_CB pUserCB; //Pointer to DAC User Callback - PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA Config -}SAL_DAC_HND, *PSAL_DAC_HND; - -// DAC SAL handle private -typedef struct _SAL_DAC_HND_PRIV_ { - VOID **ppSalDACHnd; //Pointer to SAL_DAC_HND pointer - SAL_DAC_HND SalDACHndPriv; //Private SAL_DAC_HND -}SAL_DAC_HND_PRIV, *PSAL_DAC_HND_PRIV; - -//DAC SAL management adapter -typedef struct _SAL_DAC_MNGT_ADPT_ { - PSAL_DAC_HND_PRIV pSalHndPriv; //Pointer to SAL_DAC_HND - PHAL_DAC_INIT_DAT pHalInitDat; //Pointer to HAL DAC initial data( HAL_I2C_INIT_DAT ) - PHAL_DAC_OP pHalOp; //Pointer to HAL DAC operation( HAL_DAC_OP ) - VOID (*pHalOpInit)(VOID*); //Pointer to HAL DAC initialize function - PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE ) - PSAL_DAC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_DAC_USER_CB ) - VOID (*pSalIrqFunc)(VOID*); //Used for SAL DAC interrupt function - - PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config - PHAL_GDMA_ADAPTER pHalGdmaAdp; - PHAL_GDMA_OP pHalGdmaOp; - VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function - PIRQ_HANDLE pIrqGdmaHnd; - VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function -}SAL_DAC_MNGT_ADPT, *PSAL_DAC_MNGT_ADPT; - - -//================ DAC HAL Function Prototype =================== -// DAC HAL inline function -// For checking DAC input index valid or not -static inline RTK_STATUS -RtkDACIdxChk( - IN u8 DACIdx -) -{ -#if !DAC0_USED - if (DACIdx == DAC0_SEL) - return _EXIT_FAILURE; -#endif - -#if !DAC1_USED - if (DACIdx == DAC1_SEL) - return _EXIT_FAILURE; -#endif - DACIdx = DACIdx; - return _EXIT_SUCCESS; -} - -VOID HalDACOpInit(IN VOID *Data); -RTK_STATUS RtkDACLoadDefault(IN VOID *Data); -RTK_STATUS RtkDACInit(IN VOID *Data); -RTK_STATUS RtkDACDeInit(IN VOID *Data); -RTK_STATUS RtkDACSend(IN VOID *Data); -PSAL_DAC_HND RtkDACGetSalHnd(IN u8 DACIdx); -RTK_STATUS RtkDACFreeSalHnd(IN PSAL_DAC_HND pSalDACHND); -PSAL_DAC_MNGT_ADPT RtkDACGetMngtAdpt(IN u8 DACIdx); -RTK_STATUS RtkDACFreeMngtAdpt(IN PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt); - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_diag.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_diag.h deleted file mode 100644 index 259e6f7f427..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_diag.h +++ /dev/null @@ -1,111 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_DIAG_H_ -#define _HAL_DIAG_H_ - - -//Register offset -#define UART_REV_BUF_OFF 0x00 -#define UART_TRAN_HOLD_OFF 0x00 -#define UART_DLH_OFF 0x04 -#define UART_DLL_OFF 0x00 -#define UART_INTERRUPT_EN_REG_OFF 0x04 -#define UART_INTERRUPT_IDEN_REG_OFF 0x08 -#define UART_FIFO_CTL_REG_OFF 0x08 -#define UART_LINE_CTL_REG_OFF 0x0c -#define UART_MODEM_CTL_REG_OFF 0x10 -#define UART_LINE_STATUS_REG_OFF 0x14 -#define UART_MODEM_STATUS_REG_OFF 0x18 -#define UART_FIFO_ACCESS_REG_OFF 0x70 -#define UART_STATUS_REG_OFF 0x7c -#define UART_TFL_OFF 0x80 -#define UART_RFL_OFF 0x84 - - -//Buad rate -#define UART_BAUD_RATE_2400 2400 -#define UART_BAUD_RATE_4800 4800 -#define UART_BAUD_RATE_9600 9600 -#define UART_BAUD_RATE_19200 19200 -#define UART_BAUD_RATE_38400 38400 -#define UART_BAUD_RATE_57600 57600 -#define UART_BAUD_RATE_115200 115200 -#define UART_BAUD_RATE_921600 921600 -#define UART_BAUD_RATE_1152000 1152000 - -#define UART_PARITY_ENABLE 0x08 -#define UART_PARITY_DISABLE 0 - -#define UART_DATA_LEN_5BIT 0x0 -#define UART_DATA_LEN_6BIT 0x1 -#define UART_DATA_LEN_7BIT 0x2 -#define UART_DATA_LEN_8BIT 0x3 - -#define UART_STOP_1BIT 0x0 -#define UART_STOP_2BIT 0x4 - - -#define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr) -#define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value) -#define HAL_UART_READ16(addr) HAL_READ16(LOG_UART_REG_BASE, addr) -#define HAL_UART_WRITE16(addr, value) HAL_WRITE16(LOG_UART_REG_BASE, addr, value) -#define HAL_UART_READ8(addr) HAL_READ8(LOG_UART_REG_BASE, addr) -#define HAL_UART_WRITE8(addr, value) HAL_WRITE8(LOG_UART_REG_BASE, addr, value) - -typedef struct _LOG_UART_ADAPTER_ { - u32 BaudRate; - u32 FIFOControl; - u32 IntEnReg; - u8 Parity; - u8 Stop; - u8 DataLength; -}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER; - -typedef struct _COMMAND_TABLE_ { - const u8* cmd; - u16 ArgvCnt; - u32 (*func)(u16 argc, u8* argv[]); - const u8* msg; -}COMMAND_TABLE, *PCOMMAND_TABLE; - -//VOID -//HalLogUartHandle(void); - - -extern _LONG_CALL_ROM_ u32 -HalLogUartInit( - IN LOG_UART_ADAPTER UartAdapter - ); - - -extern _LONG_CALL_ROM_ VOID -HalSerialPutcRtl8195a( - IN u8 c - ); - -extern _LONG_CALL_ROM_ u8 -HalSerialGetcRtl8195a( - IN BOOL PullMode - ); - -extern _LONG_CALL_ROM_ u32 -HalSerialGetIsrEnRegRtl8195a(VOID); - -extern _LONG_CALL_ROM_ VOID -HalSerialSetIrqEnRegRtl8195a ( - IN u32 SetValue -); - - -#endif//_HAL_DIAG_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_efuse.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_efuse.h deleted file mode 100644 index 0911d966e32..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_efuse.h +++ /dev/null @@ -1,27 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _HAL_EFUSE_H_ -#define _HAL_EFUSE_H_ - -_LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage); -extern u32 HALEFUSEOneByteReadRAM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage); -extern u32 HALEFUSEOneByteWriteRAM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage); -u32 HALOneByteWriteRAM(IN u32 CtrlSetting,IN u16 Addr,IN u8 Data,IN u8 L25OutVoltage); - -#define EFUSERead8 HALEFUSEOneByteReadRAM -#define EFUSEWrite8 HALEFUSEOneByteWriteRAM - -#define L25EOUTVOLTAGE 7 -#define DISABLE 0 -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gdma.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gdma.h deleted file mode 100644 index f2b0e4dc29e..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gdma.h +++ /dev/null @@ -1,145 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_GDMA_H_ -#define _HAL_GDMA_H_ - -#include "rtl8195a_gdma.h" - -typedef struct _GDMA_CH_LLI_ELE_ { - u32 Sarx; - u32 Darx; - u32 Llpx; - u32 CtlxLow; - u32 CtlxUp; - u32 Temp; -}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE; -#if 1 -#if 0 -typedef struct _GDMA_CH_LLI_ { - PGDMA_CH_LLI_ELE pLliEle; - PGDMA_CH_LLI pNextLli; -}GDMA_CH_LLI, *PGDMA_CH_LLI; - -typedef struct _BLOCK_SIZE_LIST_ { - u32 BlockSize; - PBLOCK_SIZE_LIST pNextBlockSiz; -}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST; -#else -struct GDMA_CH_LLI { - PGDMA_CH_LLI_ELE pLliEle; - struct GDMA_CH_LLI *pNextLli; -}; - -struct BLOCK_SIZE_LIST { - u32 BlockSize; - struct BLOCK_SIZE_LIST *pNextBlockSiz; -}; - -#endif - -#endif -typedef struct _HAL_GDMA_ADAPTER_ { - u32 ChSar; - u32 ChDar; - GDMA_CHANNEL_NUM ChEn; - GDMA_CTL_REG GdmaCtl; - GDMA_CFG_REG GdmaCfg; - u32 PacketLen; - u32 BlockLen; - u32 MuliBlockCunt; - u32 MaxMuliBlock; - struct GDMA_CH_LLI *pLlix; - struct BLOCK_SIZE_LIST *pBlockSizeList; - - PGDMA_CH_LLI_ELE pLli; - u32 NextPlli; - u8 TestItem; - u8 ChNum; - u8 GdmaIndex; - u8 IsrCtrl:1; - u8 GdmaOnOff:1; - u8 Llpctrl:1; - u8 Lli0:1; - u8 Rsvd4to7:4; - u8 GdmaIsrType; -}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER; - -typedef struct _HAL_GDMA_CHNL_ { - u8 GdmaIndx; - u8 GdmaChnl; - u8 IrqNum; - u8 Reserved; -}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL; - -typedef struct _HAL_GDMA_BLOCK_ { - u32 SrcAddr; - u32 DstAddr; - u32 BlockLength; - u32 SrcOffset; - u32 DstOffset; -}HAL_GDMA_BLOCK, *PHAL_GDMA_BLOCK; - -typedef struct _HAL_GDMA_OP_ { - VOID (*HalGdmaOnOff)(VOID *Data); - BOOL (*HalGdamChInit)(VOID *Data); - BOOL (*HalGdmaChSeting)(VOID *Data); - BOOL (*HalGdmaChBlockSeting)(VOID *Data); - VOID (*HalGdmaChDis)(VOID *Data); - VOID (*HalGdmaChEn)(VOID *Data); - VOID (*HalGdmaChIsrEnAndDis) (VOID *Data); - u8 (*HalGdmaChIsrClean)(VOID *Data); - VOID (*HalGdmaChCleanAutoSrc)(VOID *Data); - VOID (*HalGdmaChCleanAutoDst)(VOID *Data); -}HAL_GDMA_OP, *PHAL_GDMA_OP; - -typedef struct _HAL_GDMA_OBJ_ { - HAL_GDMA_ADAPTER HalGdmaAdapter; - IRQ_HANDLE GdmaIrqHandle; - volatile GDMA_CH_LLI_ELE GdmaChLli[16]; - struct GDMA_CH_LLI Lli[16]; - struct BLOCK_SIZE_LIST BlockSizeList[16]; - u8 Busy; // is transfering - u8 BlockNum; -} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ; - -VOID HalGdmaOpInit(IN VOID *Data); -VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter); -VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter); - -extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum); -extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum); -extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption); -extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl); -extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj); -extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj); -extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len); -extern VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock); -extern BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj); - -extern const HAL_GDMA_OP _HalGdmaOp; -extern const HAL_GDMA_CHNL GDMA_Chnl_Option[]; -extern const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[]; -extern const u16 HalGdmaChnlEn[6]; - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gpio.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gpio.h deleted file mode 100644 index feac0808618..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gpio.h +++ /dev/null @@ -1,251 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_GPIO_H_ -#define _HAL_GPIO_H_ - -#define HAL_GPIO_PIN_INT_MODE 0x80 - -enum { - _PORT_A = 0, - _PORT_B = 1, - _PORT_C = 2, - _PORT_D = 3, - _PORT_E = 4, - _PORT_F = 5, - _PORT_G = 6, - _PORT_H = 7, - _PORT_I = 8, - _PORT_J = 9, - _PORT_K = 10, - - _PORT_MAX -}; -typedef uint32_t HAL_GPIO_PORT_NAME; - -enum { - _PA_0 = (_PORT_A<<4|0), - _PA_1 = (_PORT_A<<4|1), - _PA_2 = (_PORT_A<<4|2), - _PA_3 = (_PORT_A<<4|3), - _PA_4 = (_PORT_A<<4|4), - _PA_5 = (_PORT_A<<4|5), - _PA_6 = (_PORT_A<<4|6), - _PA_7 = (_PORT_A<<4|7), - - _PB_0 = (_PORT_B<<4|0), - _PB_1 = (_PORT_B<<4|1), - _PB_2 = (_PORT_B<<4|2), - _PB_3 = (_PORT_B<<4|3), - _PB_4 = (_PORT_B<<4|4), - _PB_5 = (_PORT_B<<4|5), - _PB_6 = (_PORT_B<<4|6), - _PB_7 = (_PORT_B<<4|7), - - _PC_0 = (_PORT_C<<4|0), - _PC_1 = (_PORT_C<<4|1), - _PC_2 = (_PORT_C<<4|2), - _PC_3 = (_PORT_C<<4|3), - _PC_4 = (_PORT_C<<4|4), - _PC_5 = (_PORT_C<<4|5), - _PC_6 = (_PORT_C<<4|6), - _PC_7 = (_PORT_C<<4|7), - _PC_8 = (_PORT_C<<4|8), - _PC_9 = (_PORT_C<<4|9), - - _PD_0 = (_PORT_D<<4|0), - _PD_1 = (_PORT_D<<4|1), - _PD_2 = (_PORT_D<<4|2), - _PD_3 = (_PORT_D<<4|3), - _PD_4 = (_PORT_D<<4|4), - _PD_5 = (_PORT_D<<4|5), - _PD_6 = (_PORT_D<<4|6), - _PD_7 = (_PORT_D<<4|7), - _PD_8 = (_PORT_D<<4|8), - _PD_9 = (_PORT_D<<4|9), - - _PE_0 = (_PORT_E<<4|0), - _PE_1 = (_PORT_E<<4|1), - _PE_2 = (_PORT_E<<4|2), - _PE_3 = (_PORT_E<<4|3), - _PE_4 = (_PORT_E<<4|4), - _PE_5 = (_PORT_E<<4|5), - _PE_6 = (_PORT_E<<4|6), - _PE_7 = (_PORT_E<<4|7), - _PE_8 = (_PORT_E<<4|8), - _PE_9 = (_PORT_E<<4|9), - _PE_A = (_PORT_E<<4|10), - - _PF_0 = (_PORT_F<<4|0), - _PF_1 = (_PORT_F<<4|1), - _PF_2 = (_PORT_F<<4|2), - _PF_3 = (_PORT_F<<4|3), - _PF_4 = (_PORT_F<<4|4), - _PF_5 = (_PORT_F<<4|5), -// _PF_6 = (_PORT_F<<4|6), -// _PF_7 = (_PORT_F<<4|7), - - _PG_0 = (_PORT_G<<4|0), - _PG_1 = (_PORT_G<<4|1), - _PG_2 = (_PORT_G<<4|2), - _PG_3 = (_PORT_G<<4|3), - _PG_4 = (_PORT_G<<4|4), - _PG_5 = (_PORT_G<<4|5), - _PG_6 = (_PORT_G<<4|6), - _PG_7 = (_PORT_G<<4|7), - - _PH_0 = (_PORT_H<<4|0), - _PH_1 = (_PORT_H<<4|1), - _PH_2 = (_PORT_H<<4|2), - _PH_3 = (_PORT_H<<4|3), - _PH_4 = (_PORT_H<<4|4), - _PH_5 = (_PORT_H<<4|5), - _PH_6 = (_PORT_H<<4|6), - _PH_7 = (_PORT_H<<4|7), - - _PI_0 = (_PORT_I<<4|0), - _PI_1 = (_PORT_I<<4|1), - _PI_2 = (_PORT_I<<4|2), - _PI_3 = (_PORT_I<<4|3), - _PI_4 = (_PORT_I<<4|4), - _PI_5 = (_PORT_I<<4|5), - _PI_6 = (_PORT_I<<4|6), - _PI_7 = (_PORT_I<<4|7), - - _PJ_0 = (_PORT_J<<4|0), - _PJ_1 = (_PORT_J<<4|1), - _PJ_2 = (_PORT_J<<4|2), - _PJ_3 = (_PORT_J<<4|3), - _PJ_4 = (_PORT_J<<4|4), - _PJ_5 = (_PORT_J<<4|5), - _PJ_6 = (_PORT_J<<4|6), -// _PJ_7 = (_PORT_J<<4|7), - - _PK_0 = (_PORT_K<<4|0), - _PK_1 = (_PORT_K<<4|1), - _PK_2 = (_PORT_K<<4|2), - _PK_3 = (_PORT_K<<4|3), - _PK_4 = (_PORT_K<<4|4), - _PK_5 = (_PORT_K<<4|5), - _PK_6 = (_PORT_K<<4|6), -// _PK_7 = (_PORT_K<<4|7), - - // Not connected - _PIN_NC = (int)0xFFFFFFFF -}; -typedef uint32_t HAL_PIN_NAME; - -enum -{ - GPIO_PIN_LOW = 0, - GPIO_PIN_HIGH = 1, - GPIO_PIN_ERR = 2 // read Pin error -}; -typedef uint32_t HAL_GPIO_PIN_STATE; - -enum { - DIN_PULL_NONE = 0, //floating or high impedance ? - DIN_PULL_LOW = 1, - DIN_PULL_HIGH = 2, - - DOUT_PUSH_PULL = 3, - DOUT_OPEN_DRAIN = 4, - - INT_LOW = (5|HAL_GPIO_PIN_INT_MODE), // Interrupt Low level trigger - INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger - INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger - INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger -}; -typedef uint32_t HAL_GPIO_PIN_MODE; - -enum { - GPIO_PORT_A = 0, - GPIO_PORT_B = 1, - GPIO_PORT_C = 2, - GPIO_PORT_D = 3 -}; - -enum { - hal_PullNone = 0, - hal_PullUp = 1, - hal_PullDown = 2, - hal_OpenDrain = 3, - hal_PullDefault = hal_PullNone -}; -typedef uint32_t HAL_PinMode; - -typedef struct _HAL_GPIO_PORT_ { - u32 out_data; // to write the GPIO port - u32 in_data; // to read the GPIO port - u32 dir; // config each pin direction -}HAL_GPIO_PORT, *PHAL_GPIO_PORT; - -#define HAL_GPIO_PIN_NAME(port,pin) (((port)<<5)|(pin)) -#define HAL_GPIO_GET_PORT_BY_NAME(x) ((x>>5) & 0x03) -#define HAL_GPIO_GET_PIN_BY_NAME(x) (x & 0x1f) - -typedef struct _HAL_GPIO_PIN_ { - HAL_GPIO_PIN_MODE pin_mode; - u32 pin_name; // Pin: [7:5]: port number, [4:0]: pin number -}HAL_GPIO_PIN, *PHAL_GPIO_PIN; - -typedef struct _HAL_GPIO_OP_ { -#if defined(__ICCARM__) - void* dummy; -#endif -}HAL_GPIO_OP, *PHAL_GPIO_OP; - -typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id); -typedef void (*GPIO_USER_IRQ_FUN)(u32 Id); - -typedef struct _HAL_GPIO_ADAPTER_ { - IRQ_HANDLE IrqHandle; // GPIO HAL IRQ Handle - GPIO_USER_IRQ_FUN UserIrqHandler; // GPIO IRQ Handler - GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x] - VOID *PortA_IrqData[32]; - VOID (*EnterCritical)(void); - VOID (*ExitCritical)(void); - u32 Local_Gpio_Dir[3]; // to record direction setting: 0- IN, 1- Out - u8 Gpio_Func_En; // Is GPIO HW function enabled ? - u8 Locked; -}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER; - -u32 -HAL_GPIO_GetPinName( - u32 chip_pin -); - -VOID -HAL_GPIO_PullCtrl( - u32 pin, - u32 mode -); - -VOID -HAL_GPIO_Init( - HAL_GPIO_PIN *GPIO_Pin -); - -VOID -HAL_GPIO_Irq_Init( - HAL_GPIO_PIN *GPIO_Pin -); - -VOID -HAL_GPIO_IP_DeInit( - VOID -); - - -#endif // end of "#define _HAL_GPIO_H_" - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2c.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2c.h deleted file mode 100644 index 290d93e0064..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2c.h +++ /dev/null @@ -1,634 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_I2C_H_ //#ifndef _HAL_I2C_H_ -#define _HAL_I2C_H_ - -#include "rtl8195a_i2c.h" -#include "hal_gdma.h" - -//================= I2C CONFIGURATION START ================== -// I2C SAL User Configuration Flags - -// I2C SAL operation types -#define I2C_POLL_OP_TYPE 1 -#define I2C_INTR_OP_TYPE 1 -#define I2C_DMA_OP_TYPE 1 - -// I2C supports user register address -#define I2C_USER_REG_ADDR 1 //I2C User specific register address by using - //the first I2C data as the register - //address - -// I2C SAL used module. Please set the I2C module flag to 1 to enable the related -// I2C module functions. -#define I2C0_USED 1 -#define I2C1_USED 1 -#define I2C2_USED 1 -#define I2C3_USED 1 -//================= I2C CONFIGURATION END =================== - - -//================= I2C HAL START ========================== -// I2C debug output -#define I2C_PREFIX "RTL8195A[i2c]: " -#define I2C_PREFIX_LVL " [i2c_DBG]: " - -typedef enum _I2C_DBG_LVL_ { - HAL_I2C_LVL = 0x01, - SAL_I2C_LVL = 0x02, - VERI_I2C_LVL = 0x03, -}I2C_DBG_LVL,*PI2C_DBG_LVL; - -#ifdef CONFIG_DEBUG_LOG -#ifdef CONFIG_DEBUG_LOG_I2C_HAL -#define DBG_I2C_LOG_PERD 100 - - #define I2CDBGLVL 0xFF - #define DBG_8195A_I2C(...) do{ \ - _DbgDump("\r"I2C_PREFIX __VA_ARGS__);\ - }while(0) - - #define DBG_8195A_I2C_LVL(LVL,...) do{\ - if (LVL&I2CDBGLVL){\ - _DbgDump("\r"I2C_PREFIX_LVL __VA_ARGS__);\ - }\ - }while(0) -#else - #define DBG_I2C_LOG_PERD 100 - #define DBG_8195A_I2C(...) - #define DBG_8195A_I2C_LVL(...) -#endif -#else - #define DBG_I2C_LOG_PERD 100 - #define DBG_8195A_I2C(...) - #define DBG_8195A_I2C_LVL(...) -#endif - -#define I2C_MTR_RTY_CNT 1024 -//====================================================== -// I2C HAL related enumeration -// I2C Module Selection -enum _I2C_MODULE_SEL_ { - I2C0_SEL = 0x0, - I2C1_SEL = 0x1, - I2C2_SEL = 0x2, - I2C3_SEL = 0x3, -}; -typedef uint32_t I2C_MODULE_SEL; -typedef uint32_t *PI2C_MODULE_SEL; - -// I2C HAL initial data structure -typedef struct _HAL_I2C_INIT_DAT_ { - u8 I2CIdx; //I2C index used - u8 I2CEn; //I2C module enable - u8 I2CMaster; //Master or Slave mode - u8 I2CAddrMod; //I2C addressing mode(7-bit, 10-bit) - - u8 I2CSpdMod; //I2C speed mode(Standard, Fast, High) - u8 I2CSetup; //I2C SDA setup time - u8 I2CRXTL; //I2C RX FIFO Threshold - u8 I2CTXTL; //I2C TX FIFO Threshold - - u8 I2CBusLd; //I2C bus load (pf) for high speed mode - u8 I2CReSTR; //I2C restart support - u8 I2CGC; //I2C general support - u8 I2CStartB; //I2C start byte support - - u8 I2CSlvNoAck; //I2C slave no ack support - u8 I2CDMACtrl; //I2C DMA feature support - u8 I2CCmd; //I2C Command - u8 I2CDataLen; //I2C Data Length - - u8 I2CSlvAckGC; //I2C slave acks to General Call - u8 I2CStop; //I2C issues STOP bit or not - u16 RSVD0; //Bit0: used to control HalI2CMassSendRtl8195a_Patch sending - // RESTART or not by upper layer SW. - - u8 *I2CRWData; //I2C Read/Write data pointer - - u16 I2CIntrMSK; //I2C Interrupt Mask - u16 I2CIntrClr; //I2C Interrupt register to clear - - u16 I2CAckAddr; //I2C target address in I2C Master mode, - //ack address in I2C Slave mode - u16 I2CSdaHd; //I2C SDA hold time - - u32 I2CClk; //I2C bus clock (in kHz) - - u8 I2CTxDMARqLv; //I2C TX DMA Empty Level - u8 I2CRxDMARqLv; //I2C RX DMA Full Level - u16 RSVD1; //Reserved -}HAL_I2C_INIT_DAT,*PHAL_I2C_INIT_DAT; - -// I2C HAL Operations -typedef struct _HAL_I2C_OP_ { - HAL_Status (*HalI2CInit) (VOID *Data); //HAL I2C initialization - HAL_Status (*HalI2CDeInit) (VOID *Data); //HAL I2C de-initialization - HAL_Status (*HalI2CSend) (VOID *Data); //HAL I2C send - u8 (*HalI2CReceive) (VOID *Data); //HAL I2C receive - HAL_Status (*HalI2CEnable) (VOID *Data); //HAL I2C enable module - HAL_Status (*HalI2CIntrCtrl) (VOID *Data); //HAL I2C interrupt control - u32 (*HalI2CReadReg) (VOID *Data, u8 I2CReg);//HAL I2C read register - HAL_Status (*HalI2CWriteReg) (VOID *Data, u8 I2CReg, u32 RegVal);//HAL I2C write register - HAL_Status (*HalI2CSetCLK) (VOID *Data); //HAL I2C set bus clock - HAL_Status (*HalI2CMassSend) (VOID *Data); //HAL I2C mass send - HAL_Status (*HalI2CClrIntr) (VOID *Data); //HAL I2C clear interrupts - HAL_Status (*HalI2CClrAllIntr) (VOID *Data); //HAL I2C clear all interrupts - HAL_Status (*HalI2CDMACtrl) (VOID *Data); //HAL I2C DMA control -}HAL_I2C_OP, *PHAL_I2C_OP; -//================= I2C HAL END =========================== - - -//================= I2C SAL START ========================== -//I2C SAL Macros - -//====================================================== -// I2C SAL related enumerations -// I2C Extend Features -enum _I2C_EXD_SUPPORT_{ - I2C_EXD_RESTART = 0x1, //BIT_0, RESTART bit - I2C_EXD_GENCALL = 0x2, //BIT_1, Master generates General Call. All "send" operations generate General Call addresss - I2C_EXD_STARTB = 0x4, //BIT_2, Using START BYTE, instead of START Bit - I2C_EXD_SLVNOACK = 0x8, //BIT_3, Slave no ack to master - I2C_EXD_BUS400PF = 0x10, //BIT_4, I2C bus loading is 400pf - I2C_EXD_SLVACKGC = 0x20, //BIT_5, Slave acks to a General Call - I2C_EXD_USER_REG = 0x40, //BIT_6, Using User Register Address - I2C_EXD_USER_TWOB = 0x80, //BIT_7, User Register Address is 2-byte - I2C_EXD_MTR_ADDR_RTY= 0x100, //BIT_8, Master retries to send start condition and Slave address when the slave doesn't ack - // the address. - I2C_EXD_MTR_ADDR_UPD= 0x200, //BIT_9, Master dynamically updates slave address - I2C_EXD_MTR_HOLD_BUS= 0x400, //BIT_10, Master doesn't generate STOP when the FIFO is empty. This would make Master hold - // the bus. -}; -typedef uint32_t I2C_EXD_SUPPORT; -typedef uint32_t *PI2C_EXD_SUPPORT; - -// I2C operation type -enum _I2C_OP_TYPE_ { - I2C_POLL_TYPE = 0x0, - I2C_DMA_TYPE = 0x1, - I2C_INTR_TYPE = 0x2, -}; -typedef uint32_t I2C_OP_TYPE; -typedef uint32_t *PI2C_OP_TYPE; - -// I2C pinmux selection -enum _I2C_PINMUX_ { - I2C_PIN_S0 = 0x0, - I2C_PIN_S1 = 0x1, - I2C_PIN_S2 = 0x2, - I2C_PIN_S3 = 0x3, //Only valid for I2C0 and I2C3 -}; -typedef uint32_t I2C_PINMUX; -typedef uint32_t *PI2C_PINMUX; - -// I2C module status -enum _I2C_MODULE_STATUS_ { - I2C_DISABLE = 0x0, - I2C_ENABLE = 0x1, -}; -typedef uint32_t I2C_MODULE_STATUS; -typedef uint32_t *PI2C_MODULE_STATUS; - -// I2C device status -enum _I2C_Device_STATUS_ { - I2C_STS_UNINITIAL = 0x00, - I2C_STS_INITIALIZED = 0x01, - I2C_STS_IDLE = 0x02, - - I2C_STS_TX_READY = 0x03, - I2C_STS_TX_ING = 0x04, - - I2C_STS_RX_READY = 0x05, - I2C_STS_RX_ING = 0x06, - - I2C_STS_ERROR = 0x10, - I2C_STS_TIMEOUT = 0x11, -}; -typedef uint32_t I2C_Device_STATUS; -typedef uint32_t *PI2C_Device_STATUS; - -// I2C feature status -enum _I2C_FEATURE_STATUS_{ - I2C_FEATURE_DISABLED = 0, - I2C_FEATURE_ENABLED = 1, -}; -typedef uint32_t I2C_FEATURE_STATUS; -typedef uint32_t *PI2C_FEATURE_STATUS; - -// I2C device mode -enum _I2C_DEV_MODE_ { - I2C_SLAVE_MODE = 0x0, - I2C_MASTER_MODE = 0x1, -}; -typedef uint32_t I2C_DEV_MODE; -typedef uint32_t *PI2C_DEV_MODE; - -// I2C Bus Transmit/Receive -enum _I2C_DIRECTION_ { - I2C_ONLY_TX = 0x1, - I2C_ONLY_RX = 0x2, - I2C_TXRX = 0x3, -}; -typedef uint32_t I2C_DIRECTION; -typedef uint32_t *PI2C_DIRECTION; - -//I2C DMA module number -enum _I2C_DMA_MODULE_SEL_ { - I2C_DMA_MODULE_0 = 0x0, - I2C_DMA_MODULE_1 = 0x1 -}; -typedef uint32_t I2C_DMA_MODULE_SEL; -typedef uint32_t *PI2C_DMA_MODULE_SEL; - -// I2C0 DMA peripheral number -enum _I2C0_DMA_PERI_NUM_ { - I2C0_DMA_TX_NUM = 0x8, - I2C0_DMA_RX_NUM = 0x9, -}; -typedef uint32_t I2C0_DMA_PERI_NUM; -typedef uint32_t *PI2C0_DMA_PERI_NUM; - -// I2C1 DMA peripheral number -enum _I2C1_DMA_PERI_NUM_ { - I2C1_DMA_TX_NUM = 0xA, - I2C1_DMA_RX_NUM = 0xB, -}; -typedef uint32_t I2C1_DMA_PERI_NUM; -typedef uint32_t *PI2C1_DMA_PERI_NUM; - -// I2C0 DMA module used -enum _I2C0_DMA_MODULE_ { - I2C0_DMA0 = 0x0, - I2C0_DMA1 = 0x1, -}; -typedef uint32_t I2C0_DMA_MODULE; -typedef uint32_t *PI2C0_DMA_MODULE; - -// I2C0 DMA module used -enum _I2C1_DMA_MODULE_ { - I2C1_DMA0 = 0x0, - I2C1_DMA1 = 0x1, -}; -typedef uint32_t I2C1_DMA_MODULE; -typedef uint32_t *PI2C1_DMA_MODULE; - -// I2C command type -enum _I2C_COMMAND_TYPE_ { - I2C_WRITE_CMD = 0x0, - I2C_READ_CMD = 0x1, -}; -typedef uint32_t I2C_COMMAND_TYPE; -typedef uint32_t *PI2C_COMMAND_TYPE; - -// I2C STOP BIT -enum _I2C_STOP_TYPE_ { - I2C_STOP_DIS = 0x0, - I2C_STOP_EN = 0x1, -}; -typedef uint32_t I2C_STOP_TYPE; -typedef uint32_t *PI2C_STOP_TYPE; - -// I2C error type -enum _I2C_ERR_TYPE_ { - I2C_ERR_RX_UNDER = 0x01, //I2C RX FIFO Underflow - I2C_ERR_RX_OVER = 0x02, //I2C RX FIFO Overflow - I2C_ERR_TX_OVER = 0x04, //I2C TX FIFO Overflow - I2C_ERR_TX_ABRT = 0x08, //I2C TX terminated - I2C_ERR_SLV_TX_NACK = 0x10, //I2C slave transmission terminated by master NACK, - //but there are data in slave TX FIFO - I2C_ERR_MST_A_NACK = 0x20, - I2C_ERR_MST_D_NACK = 0x40, - I2C_ERR_USER_REG_TO = 0x80, - - I2C_ERR_RX_CMD_TO = 0x100, - I2C_ERR_RX_FF_TO = 0x200, - I2C_ERR_TX_CMD_TO = 0x400, - I2C_ERR_TX_FF_TO = 0x800, - - I2C_ERR_TX_ADD_TO = 0x1000, - I2C_ERR_RX_ADD_TO = 0x2000, -}; -typedef uint32_t I2C_ERR_TYPE; -typedef uint32_t *PI2C_ERR_TYPE; - -// I2C Time Out type -enum _I2C_TIMEOUT_TYPE_ { - I2C_TIMEOUT_DISABLE = 0x00, - I2C_TIMEOUT_ENDLESS = 0xFFFFFFFF, -}; -typedef uint32_t I2C_TIMEOUT_TYPE; -typedef uint32_t *PI2C_TIMEOUT_TYPE; - -//====================================================== -// SAL I2C related data structures -// I2C user callback adapter -typedef struct _SAL_I2C_USERCB_ADPT_ { - VOID (*USERCB) (VOID *Data); - u32 USERData; -}SAL_I2C_USERCB_ADPT, *PSAL_I2C_USERCB_ADPT; - -// I2C user callback structure -typedef struct _SAL_I2C_USER_CB_ { - PSAL_I2C_USERCB_ADPT pTXCB; //I2C Transmit Callback - PSAL_I2C_USERCB_ADPT pTXCCB; //I2C Transmit Complete Callback - PSAL_I2C_USERCB_ADPT pRXCB; //I2C Receive Callback - PSAL_I2C_USERCB_ADPT pRXCCB; //I2C Receive Complete Callback - PSAL_I2C_USERCB_ADPT pRDREQCB; //I2C Read Request Callback - PSAL_I2C_USERCB_ADPT pERRCB; //I2C Error Callback - PSAL_I2C_USERCB_ADPT pDMATXCB; //I2C DMA Transmit Callback - PSAL_I2C_USERCB_ADPT pDMATXCCB; //I2C DMA Transmit Complete Callback - PSAL_I2C_USERCB_ADPT pDMARXCB; //I2C DMA Receive Callback - PSAL_I2C_USERCB_ADPT pDMARXCCB; //I2C DMA Receive Complete Callback - PSAL_I2C_USERCB_ADPT pGENCALLCB; //I2C General Call Callback -}SAL_I2C_USER_CB, *PSAL_I2C_USER_CB; - -// I2C Transmit Buffer -typedef struct _SAL_I2C_TRANSFER_BUF_ { - u16 DataLen; //I2C Transmfer Length - u16 TargetAddr; //I2C Target Address. It's only valid in Master Mode. - u32 RegAddr; //I2C Register Address. It's only valid in Master Mode. - u32 RSVD; // - u8 *pDataBuf; //I2C Transfer Buffer Pointer -}SAL_I2C_TRANSFER_BUF,*PSAL_I2C_TRANSFER_BUF; - -typedef struct _SAL_I2C_DMA_USER_DEF_ { - u8 TxDatSrcWdth; - u8 TxDatDstWdth; - u8 TxDatSrcBstSz; - u8 TxDatDstBstSz; - u8 TxChNo; - u8 RSVD0; - u16 RSVD1; - u8 RxDatSrcWdth; - u8 RxDatDstWdth; - u8 RxDatSrcBstSz; - u8 RxDatDstBstSz; - u8 RxChNo; - u8 RSVD2; - u16 RSVD3; -}SAL_I2C_DMA_USER_DEF, *PSAL_I2C_DMA_USER_DEF; - -// RTK I2C OP -typedef struct _RTK_I2C_OP_ { - HAL_Status (*Init) (VOID *Data); - HAL_Status (*DeInit) (VOID *Data); - HAL_Status (*Send) (VOID *Data); - HAL_Status (*Receive) (VOID *Data); - HAL_Status (*IoCtrl) (VOID *Data); - HAL_Status (*PowerCtrl) (VOID *Data); -}RTK_I2C_OP, *PRTK_I2C_OP; - -// Software API Level I2C Handler -typedef struct _SAL_I2C_HND_ { - u8 DevNum; //I2C device number - u8 PinMux; //I2C pin mux seletion - u8 OpType; //I2C operation type selection - volatile u8 DevSts; //I2C device status - - u8 I2CMaster; //I2C Master or Slave mode - u8 I2CAddrMod; //I2C 7-bit or 10-bit mode - u8 I2CSpdMod; //I2C SS/ FS/ HS speed mode - u8 I2CAckAddr; //I2C target address in Master - //mode or ack address in Slave - //mode - - u16 I2CClk; //I2C bus clock - u8 MasterRead; //I2C Master Read Supported, - //An Address will be sent before - //read data back. - - u8 I2CDmaSel; //I2C DMA module select - // 0 for DMA0, - // 1 for DMA1 - u8 I2CTxDMARqLv; //I2C TX DMA Empty Level - u8 I2CRxDMARqLv; //I2C RX DMA Full Level - u16 RSVD0; //Reserved - - u32 AddRtyTimeOut; //I2C TimeOut Value for master send address retry - //(Originally Reserved.) - - u32 I2CExd; //I2C extended options: - //bit 0: I2C RESTART supported, - // 0 for NOT supported, - // 1 for supported - //bit 1: I2C General Call supported - // 0 for NOT supported, - // 1 for supported - //bit 2: I2C START Byte supported - // 0 for NOT supported, - // 1 for supported - //bit 3: I2C Slave-No-Ack - // supported - // 0 for NOT supported, - // 1 for supported - //bit 4: I2C bus loading, - // 0 for 100pf, - // 1 for 400pf - //bit 5: I2C slave ack to General - // Call - //bit 6: I2C User register address - //bit 7: I2C 2-Byte User register - // address - //bit 8: I2C slave address no ack retry, - // It's only for Master mode, - // when slave doesn't ack the - // address - //bit 31~bit 8: Reserved - u32 ErrType; // - u32 TimeOut; //I2C IO Timeout count, in ms - - PHAL_I2C_INIT_DAT pInitDat; //Pointer to I2C initial data struct - PSAL_I2C_TRANSFER_BUF pTXBuf; //Pointer to I2C TX buffer - PSAL_I2C_TRANSFER_BUF pRXBuf; //Pointer to I2C RX buffer - PSAL_I2C_USER_CB pUserCB; //Pointer to I2C User Callback - PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config -}SAL_I2C_HND, *PSAL_I2C_HND; - - - -//====================================================== -// I2C SAL Function Prototypes - -// For checking I2C input index valid or not -static inline HAL_Status -RtkI2CIdxChk( - IN u8 I2CIdx -) -{ - if (I2CIdx > I2C3_SEL) - return HAL_ERR_UNKNOWN; - - return HAL_OK; -} -#if 0 -//For checking I2C operation type valid or not -static inline HAL_Status -RtkI2COpTypeChk( - IN VOID *Data -) -{ - PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; - - if (pSalI2CHND->OpType == I2C_POLL_TYPE) - return HAL_ERR_UNKNOWN; - - if (pSalI2CHND->OpType == I2C_DMA_TYPE) - return HAL_ERR_UNKNOWN; - - if (pSalI2CHND->OpType == I2C_INTR_TYPE) - return HAL_ERR_UNKNOWN; - - pSalI2CHND = pSalI2CHND; - - return HAL_OK; -} -#endif -//For checking I2C DMA available or not -static inline HAL_Status -RtkI2CDMAChk( - IN VOID *Data -) -{ - PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; - - if (pSalI2CHND->OpType == I2C_DMA_TYPE) { - if (pSalI2CHND->DevNum >= I2C2_SEL) - return HAL_ERR_UNKNOWN; - } - else { - return HAL_ERR_UNKNOWN; - } - - return HAL_OK; -} - -//For checking I2C DMA available or not -static inline HAL_Status -RtkI2CDMAInitChk( - IN VOID *Data -) -{ - PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; - - if (pSalI2CHND->OpType != I2C_DMA_TYPE) { - return HAL_ERR_UNKNOWN; - } - else { - return HAL_OK; - } - -} - -//====================================================== -//SAL I2C management function prototype -_LONG_CALL_ROM_ HAL_Status RtkI2CLoadDefault(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status RtkI2CInit(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status RtkI2CDeInit(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status RtkI2CSend(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status RtkI2CReceive(IN VOID *Data); -_LONG_CALL_ROM_ VOID RtkSalI2COpInit(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status RtkI2CSendUserAddr(IN VOID *Data,IN u8 MtrWr); -_LONG_CALL_ROM_ HAL_Status RtkI2CIoCtrl(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status RtkI2CPowerCtrl(IN VOID *Data); -_LONG_CALL_ HAL_Status RtkI2CInitForPS(IN VOID *Data); -_LONG_CALL_ HAL_Status RtkI2CDeInitForPS(IN VOID *Data); -_LONG_CALL_ HAL_Status RtkI2CDisablePS(IN VOID *Data); -_LONG_CALL_ HAL_Status RtkI2CEnablePS(IN VOID *Data); -//================= I2C SAL END =========================== - - -//================= I2C SAL MANAGEMENT START ================= -// I2C SAL management macros -#define SAL_USER_CB_NUM (sizeof(SAL_I2C_USER_CB) / sizeof(PSAL_I2C_USERCB_ADPT)) - -//====================================================== -// I2C SAL management data structures -// I2C SAL handle private -typedef struct _SAL_I2C_HND_PRIV_ { - VOID **ppSalI2CHnd; //Pointer to SAL_I2C_HND pointer - SAL_I2C_HND SalI2CHndPriv; //Private SAL_I2C_HND -}SAL_I2C_HND_PRIV, *PSAL_I2C_HND_PRIV; - -//I2C SAL management adapter -typedef struct _SAL_I2C_MNGT_ADPT_ { - PSAL_I2C_HND_PRIV pSalHndPriv; //Pointer to SAL_I2C_HND - PHAL_I2C_INIT_DAT pHalInitDat; //Pointer to HAL I2C initial data( HAL_I2C_INIT_DAT ) - PHAL_I2C_OP pHalOp; //Pointer to HAL I2C operation( HAL_I2C_OP ) - VOID (*pHalOpInit)(VOID*); //Pointer to HAL I2C initialize function - PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE ) - PSAL_I2C_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_I2C_USER_CB ) - volatile u32 MstRDCmdCnt; //Used for Master Read command count - volatile u32 InnerTimeOut; //Used for SAL internal timeout count - VOID (*pSalIrqFunc)(VOID*); //Used for SAL I2C interrupt function - - PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config - PHAL_GDMA_ADAPTER pHalTxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER - PHAL_GDMA_ADAPTER pHalRxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER - PHAL_GDMA_OP pHalGdmaOp; //Pointer to HAL_GDMA_OP - VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL I2C initialize function - PIRQ_HANDLE pIrqTxGdmaHnd; //Pointer to IRQ handler for Tx GDMA - PIRQ_HANDLE pIrqRxGdmaHnd; //Pointer to IRQ handler for Rx GDMA - VOID (*pSalDMATxIrqFunc)(VOID*); //Used for SAL I2C interrupt function - VOID (*pSalDMARxIrqFunc)(VOID*); //Used for SAL I2C interrupt function - u32 RSVD; //Reserved -}SAL_I2C_MNGT_ADPT, *PSAL_I2C_MNGT_ADPT; - -//====================================================== -//SAL I2C management function prototype -PSAL_I2C_MNGT_ADPT RtkI2CGetMngtAdpt(IN u8 I2CIdx); -HAL_Status RtkI2CFreeMngtAdpt(IN PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt); -PSAL_I2C_HND RtkI2CGetSalHnd(IN u8 I2CIdx); -HAL_Status RtkI2CFreeSalHnd(IN PSAL_I2C_HND pSalI2CHND); -u32 RtkSalI2CSts(IN VOID *Data); - -extern _LONG_CALL_ VOID I2CISRHandle(IN VOID *Data); -extern _LONG_CALL_ VOID I2CTXGDMAISRHandle(IN VOID *Data); -extern _LONG_CALL_ VOID I2CRXGDMAISRHandle(IN VOID *Data); -extern HAL_Status I2CIsTimeout (IN u32 StartCount, IN u32 TimeoutCnt); -extern HAL_TIMER_OP HalTimerOp; -//====================================================== -// Function Prototypes -_LONG_CALL_ VOID HalI2COpInit(IN VOID *Data); -//================= I2C SAL MANAGEMENT END ================== - -//================= Rtl8195a I2C V02 function prototype ============ -_LONG_CALL_ VOID HalI2COpInitV02(IN VOID *Data); -_LONG_CALL_ VOID I2CISRHandleV02(IN VOID *Data); -_LONG_CALL_ HAL_Status RtkI2CSendV02(IN VOID *Data); -_LONG_CALL_ HAL_Status RtkI2CReceiveV02(IN VOID *Data); -_LONG_CALL_ VOID RtkSalI2COpInitV02(IN VOID *Data); -//================= Rtl8195a I2C V02 function prototype END========== - -//================= Rtl8195a I2C V04 function prototype ============ -_LONG_CALL_ VOID HalI2COpInit_V04(IN VOID *Data); -_LONG_CALL_ VOID I2CISRHandle_V04(IN VOID *Data); -//================= Rtl8195a I2C V04 function prototype END========== - -//====================================================== -//SAL I2C patch function prototype -HAL_Status RtkI2CSend_Patch(IN VOID *Data); -HAL_Status RtkI2CReceive_Patch(IN VOID *Data); -VOID HalI2COpInit_Patch(IN VOID *Data); -VOID I2CISRHandle_Patch(IN VOID *Data); - -#ifndef CONFIG_RELEASE_BUILD_LIBRARIES -#define RtkI2CSend RtkI2CSend_Patch -#define RtkI2CReceive RtkI2CReceive_Patch -#endif -HAL_Status RtkI2CSend_Patch(IN VOID *Data); -HAL_Status RtkI2CReceive_Patch(IN VOID *Data); -//================= I2C SAL END =========================== - -#endif //#ifndef _HAL_I2C_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2s.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2s.h deleted file mode 100644 index 10b92d31d4e..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2s.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Routines to access hardware - * - * Copyright (c) 2013 Realtek Semiconductor Corp. - * - * This module is a confidential and proprietary property of RealTek and - * possession or use of this module requires written permission of RealTek. - */ - -#ifndef _HAL_I2S_H_ -#define _HAL_I2S_H_ - -#include "rtl8195a_i2s.h" - -/* User Define Flags */ - -#define I2S_MAX_ID 1 // valid I2S index 0 ~ I2S_MAX_ID - -/**********************************************************************/ -/* I2S HAL initial data structure */ -typedef struct _HAL_I2S_INIT_DAT_ { - u8 I2SIdx; /*I2S index used*/ - u8 I2SEn; /*I2S module enable tx/rx/tx+rx*/ - u8 I2SMaster; /*I2S Master or Slave mode*/ - u8 I2SWordLen; /*I2S Word length 16 or 24bits*/ - - u8 I2SChNum; /*I2S Channel number mono or stereo*/ - u8 I2SPageNum; /*I2S Page Number 2~4*/ - u16 I2SPageSize; /*I2S page Size 1~4096 word*/ - - u8 *I2STxData; /*I2S Tx data pointer*/ - - u8 *I2SRxData; /*I2S Rx data pointer*/ - - u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/ - u32 I2STxIntrClr; /*I2S Tx Interrupt register to clear */ - - u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/ - u32 I2SRxIntrClr; /*I2S Rx Interrupt register to clear*/ - - u16 I2STxIdx; /*I2S TX page index */ - u16 I2SRxIdx; /*I2S RX page index */ - - u16 I2SHWTxIdx; /*I2S HW TX page index */ - u16 I2SHWRxIdx; /*I2S HW RX page index */ - - - u16 I2SRate; /*I2S sample rate*/ - u8 I2STRxAct; /*I2S tx rx act*/ -}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT; - -/**********************************************************************/ -/* I2S Data Structures */ -/* I2S Module Selection */ -typedef enum _I2S_MODULE_SEL_ { - I2S0_SEL = 0x0, - I2S1_SEL = 0x1, -}I2S_MODULE_SEL,*PI2S_MODULE_SEL; -/* -typedef struct _HAL_I2S_ADAPTER_ { - u32 Enable:1; - I2S_CTL_REG I2sCtl; - I2S_SETTING_REG I2sSetting; - u32 abc; - u8 I2sIndex; -}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER; -*/ -/* I2S HAL Operations */ -typedef struct _HAL_I2S_OP_ { - RTK_STATUS (*HalI2SInit) (VOID *Data); - RTK_STATUS (*HalI2SDeInit) (VOID *Data); - RTK_STATUS (*HalI2STx) (VOID *Data, u8 *pBuff); - RTK_STATUS (*HalI2SRx) (VOID *Data, u8 *pBuff); - RTK_STATUS (*HalI2SEnable) (VOID *Data); - RTK_STATUS (*HalI2SIntrCtrl) (VOID *Data); - u32 (*HalI2SReadReg) (VOID *Data, u8 I2SReg); - RTK_STATUS (*HalI2SSetRate) (VOID *Data); - RTK_STATUS (*HalI2SSetWordLen) (VOID *Data); - RTK_STATUS (*HalI2SSetChNum) (VOID *Data); - RTK_STATUS (*HalI2SSetPageNum) (VOID *Data); - RTK_STATUS (*HalI2SSetPageSize) (VOID *Data); - - RTK_STATUS (*HalI2SClrIntr) (VOID *Data); - RTK_STATUS (*HalI2SClrAllIntr) (VOID *Data); - RTK_STATUS (*HalI2SDMACtrl) (VOID *Data); -/* - VOID (*HalI2sOnOff)(VOID *Data); - BOOL (*HalI2sInit)(VOID *Data); - BOOL (*HalI2sSetting)(VOID *Data); - BOOL (*HalI2sEn)(VOID *Data); - BOOL (*HalI2sIsrEnAndDis) (VOID *Data); - BOOL (*HalI2sDumpReg)(VOID *Data); - BOOL (*HalI2s)(VOID *Data); -*/ -}HAL_I2S_OP, *PHAL_I2S_OP; - - -/**********************************************************************/ - -/* I2S Pinmux Selection */ -#if 0 -typedef enum _I2S0_PINMUX_ { - I2S0_TO_S0 = 0x0, - I2S0_TO_S1 = 0x1, - I2S0_TO_S2 = 0x2, -}I2S0_PINMUX, *PI2S0_PINMUX; - -typedef enum _I2S1_PINMUX_ { - I2S1_TO_S0 = 0x0, - I2S1_TO_S1 = 0x1, -}I2S1_PINMUX, *PI2S1_PINMUX; -#endif - -typedef enum _I2S_PINMUX_ { - I2S_S0 = 0, - I2S_S1 = 1, - I2S_S2 = 2, - I2S_S3 = 3 -}I2S_PINMUX, *PI2S_PINMUX; - - -/* I2S Module Status */ -typedef enum _I2S_MODULE_STATUS_ { - I2S_DISABLE = 0x0, - I2S_ENABLE = 0x1, -}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS; - - -/* I2S Device Status */ -typedef enum _I2S_Device_STATUS_ { - I2S_STS_UNINITIAL = 0x00, - I2S_STS_INITIALIZED = 0x01, - I2S_STS_IDLE = 0x02, - - I2S_STS_TX_READY = 0x03, - I2S_STS_TX_ING = 0x04, - - I2S_STS_RX_READY = 0x05, - I2S_STS_RX_ING = 0x06, - - I2S_STS_TRX_READY = 0x07, - I2S_STS_TRX_ING = 0x08, - - I2S_STS_ERROR = 0x09, -}I2S_Device_STATUS, *PI2S_Device_STATUS; - - -/* I2S Feature Status */ -typedef enum _I2S_FEATURE_STATUS_{ - I2S_FEATURE_DISABLED = 0, - I2S_FEATURE_ENABLED = 1, -}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS; - -/* I2S Device Mode */ -typedef enum _I2S_DEV_MODE_ { - I2S_MASTER_MODE = 0x0, - I2S_SLAVE_MODE = 0x1 -}I2S_DEV_MODE, *PI2S_DEV_MODE; - -/* I2S Word Length */ -typedef enum _I2S_WORD_LEN_ { - I2S_WL_16 = 0x0, - I2S_WL_24 = 0x1, -}I2S_WORD_LEN, *PI2S_WORD_LEN; - -/* I2S Bus Transmit/Receive */ -typedef enum _I2S_DIRECTION_ { - I2S_ONLY_RX = 0x0, - I2S_ONLY_TX = 0x1, - I2S_TXRX = 0x2 -}I2S_DIRECTION, *PI2S_DIRECTION; - -/* I2S Channel number */ -typedef enum _I2S_CH_NUM_ { - I2S_CH_STEREO = 0x0, - I2S_CH_RSVD = 0x1, - I2S_CH_MONO = 0x2 -}I2S_CH_NUM, *PI2S_CH_NUM; - -/* I2S Page number */ -typedef enum _I2S_PAGE_NUM_ { - I2S_1PAGE = 0x0, - I2S_2PAGE = 0x1, - I2S_3PAGE = 0x2, - I2S_4PAGE = 0x3 -}I2S_PAGE_NUM, *PI2S_PAGE_NUM; - -/* I2S Sample rate*/ -typedef enum _I2S_SAMPLE_RATE_ { - I2S_SR_8KHZ = 0x00, // /12 - I2S_SR_16KHZ = 0x01, // /6 - I2S_SR_24KHZ = 0x02, // /4 - I2S_SR_32KHZ = 0x03, // /3 - I2S_SR_48KHZ = 0x05, // /2 - I2S_SR_96KHZ = 0x06, // x1, base 96kHz - I2S_SR_7p35KHZ = 0x10, - I2S_SR_14p7KHZ = 0x11, - I2S_SR_22p05KHZ = 0x12, - I2S_SR_29p4KHZ = 0x13, - I2S_SR_44p1KHZ = 0x15, - I2S_SR_88p2KHZ = 0x16 // x1, base 88200Hz -}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE; - -/* I2S TX interrupt mask/status */ -typedef enum _I2S_TX_IMR_ { - I2S_TX_INT_PAGE0_OK = (1<<0), - I2S_TX_INT_PAGE1_OK = (1<<1), - I2S_TX_INT_PAGE2_OK = (1<<2), - I2S_TX_INT_PAGE3_OK = (1<<3), - I2S_TX_INT_FULL = (1<<4), - I2S_TX_INT_EMPTY = (1<<5) -} I2S_TX_IMR, *PI2S_TX_IMR; - -/* I2S RX interrupt mask/status */ -typedef enum _I2S_RX_IMR_ { - I2S_RX_INT_PAGE0_OK = (1<<0), - I2S_RX_INT_PAGE1_OK = (1<<1), - I2S_RX_INT_PAGE2_OK = (1<<2), - I2S_RX_INT_PAGE3_OK = (1<<3), - I2S_RX_INT_EMPTY = (1<<4), - I2S_RX_INT_FULL = (1<<5) -} I2S_RX_IMR, *PI2S_RX_IMR; - -/* I2S User Callbacks */ -typedef struct _SAL_I2S_USER_CB_{ - VOID (*TXCB) (VOID *Data); - VOID (*TXCCB) (VOID *Data); - VOID (*RXCB) (VOID *Data); - VOID (*RXCCB) (VOID *Data); - VOID (*RDREQCB) (VOID *Data); - VOID (*ERRCB) (VOID *Data); - VOID (*GENCALLCB) (VOID *Data); -}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB; - -typedef struct _I2S_USER_CB_{ - VOID (*TxCCB)(uint32_t id, char *pbuf); - u32 TxCBId; - VOID (*RxCCB)(uint32_t id, char *pbuf); - u32 RxCBId; -}I2S_USER_CB,*PI2S_USER_CB; - -/* Software API Level I2S Handler */ -typedef struct _HAL_I2S_ADAPTER_{ - u8 DevNum; //I2S device number - u8 PinMux; //I2S pin mux seletion - u8 RSVD0; //Reserved - volatile u8 DevSts; //I2S device status - - u32 RSVD2; //Reserved - u32 I2SExd; //I2S extended options: - //bit 0: I2C RESTART supported, - // 0 for NOT supported, - // 1 for supported - //bit 1: I2C General Call supported - // 0 for NOT supported, - // 1 for supported - //bit 2: I2C START Byte supported - // 0 for NOT supported, - // 1 for supported - //bit 3: I2C Slave-No-Ack - // supported - // 0 for NOT supported, - // 1 for supported - //bit 4: I2C bus loading, - // 0 for 100pf, - // 1 for 400pf - //bit 5: I2C slave ack to General - // Call - //bit 6: I2C User register address - //bit 7: I2C 2-Byte User register - // address - //bit 31~bit 8: Reserved - u32 ErrType; // - u32 TimeOut; //I2S IO Timeout count - - PHAL_I2S_INIT_DAT pInitDat; //Pointer to I2S initial data struct - I2S_USER_CB UserCB; //Pointer to I2S User Callback - IRQ_HANDLE IrqHandle; // Irq Handler - - u32* TxPageList[4]; // The Tx DAM buffer: pointer of each page - u32* RxPageList[4]; // The Tx DAM buffer: pointer of each page -}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER; - -typedef struct _HAL_I2S_DEF_SETTING_{ - u8 I2SMaster; // Master or Slave mode - u8 DevSts; //I2S device status - u8 I2SChNum; //I2S Channel number mono or stereo - u8 I2SPageNum; //I2S Page number 2~4 - u8 I2STRxAct; //I2S tx rx act, tx only or rx only or tx+rx - u8 I2SWordLen; //I2S Word length 16bit or 24bit - u16 I2SPageSize; //I2S Page size 1~4096 word - - u16 I2SRate; //I2S sample rate 8k ~ 96khz - - u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/ - u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/ -}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING; - - - -/**********************************************************************/ -HAL_Status -RtkI2SLoadDefault(IN VOID *Adapter, IN VOID *Setting); - -HAL_Status -RtkI2SInit(IN VOID *Data); - -HAL_Status -RtkI2SDeInit(IN VOID *Data); - -HAL_Status -RtkI2SEnable(IN VOID *Data); - -HAL_Status -RtkI2SDisable(IN VOID *Data); - -extern HAL_Status -HalI2SInit( IN VOID *Data); - -extern VOID -HalI2SDeInit( IN VOID *Data); - -extern HAL_Status -HalI2SDisable( IN VOID *Data); - -extern HAL_Status -HalI2SEnable( IN VOID *Data); - - - - -/**********************************************************************/ - - -VOID I2S0ISRHandle(VOID *Data); -VOID I2S1ISRHandle(VOID *Data); - - -/**********************************************************************/ - -VOID HalI2SOpInit( - IN VOID *Data -); - - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_irqn.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_irqn.h deleted file mode 100644 index 995e875cf2f..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_irqn.h +++ /dev/null @@ -1,120 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_IRQN_H_ -#define _HAL_IRQN_H_ - -#define PERIPHERAL_IRQ_BASE_NUM 64 - -enum _IRQn_Type_ { -#if 0 -/****** Cortex-M3 Processor Exceptions Numbers ********/ - NON_MASKABLE_INT_IRQ = -14, - HARD_FAULT_IRQ = -13, - MEM_MANAGE_FAULT_IRQ = -12, - BUS_FAULT_IRQ = -11, - USAGE_FAULT_IRQ = -10, - SVCALL_IRQ = -5, - DEBUG_MONITOR_IRQ = -4, - PENDSVC_IRQ = -2, - SYSTICK_IRQ = -1, -#else -/****** Cortex-M3 Processor Exceptions Numbers ********/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ -#endif -/****** RTL8195A Specific Interrupt Numbers ************/ - SYSTEM_ON_IRQ = 0, - WDG_IRQ = 1, - TIMER0_IRQ = 2, - TIMER1_IRQ = 3, - I2C3_IRQ = 4, - TIMER2_7_IRQ = 5, - SPI0_IRQ = 6, - GPIO_IRQ = 7, - UART0_IRQ = 8, - SPI_FLASH_IRQ = 9, - USB_OTG_IRQ = 10, - SDIO_HOST_IRQ = 11, - SDIO_DEVICE_IRQ = 12, - I2S0_PCM0_IRQ = 13, - I2S1_PCM1_IRQ = 14, - WL_DMA_IRQ = 15, - WL_PROTOCOL_IRQ = 16, - CRYPTO_IRQ = 17, - GMAC_IRQ = 18, - PERIPHERAL_IRQ = 19, - GDMA0_CHANNEL0_IRQ = 20, - GDMA0_CHANNEL1_IRQ = 21, - GDMA0_CHANNEL2_IRQ = 22, - GDMA0_CHANNEL3_IRQ = 23, - GDMA0_CHANNEL4_IRQ = 24, - GDMA0_CHANNEL5_IRQ = 25, - GDMA1_CHANNEL0_IRQ = 26, - GDMA1_CHANNEL1_IRQ = 27, - GDMA1_CHANNEL2_IRQ = 28, - GDMA1_CHANNEL3_IRQ = 29, - GDMA1_CHANNEL4_IRQ = 30, - GDMA1_CHANNEL5_IRQ = 31, - -/****** RTL8195A Peripheral Interrupt Numbers ************/ - I2C0_IRQ = 64,// 0 + 64, - I2C1_IRQ = 65,// 1 + 64, - I2C2_IRQ = 66,// 2 + 64, - SPI1_IRQ = 72,// 8 + 64, - SPI2_IRQ = 73,// 9 + 64, - UART1_IRQ = 80,// 16 + 64, - UART2_IRQ = 81,// 17 + 64, - UART_LOG_IRQ = 88,// 24 + 64, - ADC_IRQ = 89,// 25 + 64, - DAC0_IRQ = 91,// 27 + 64, - DAC1_IRQ = 92,// 28 + 64, - //RXI300_IRQ = 93// 29 + 64 - LP_EXTENSION_IRQ = 93,// 29+64 - - PTA_TRX_IRQ = 95,// 31+64 - RXI300_IRQ = 96,// 0+32 + 64 - NFC_IRQ = 97// 1+32+64 -}; -typedef uint32_t IRQn_Type; -typedef uint32_t *PIRQn_Type; - - -typedef VOID (*HAL_VECTOR_FUN) (VOID); - -enum _VECTOR_TABLE_TYPE_{ - DEDECATED_VECTRO_TABLE, - PERIPHERAL_VECTOR_TABLE -}; -typedef uint32_t VECTOR_TABLE_TYPE; -typedef uint32_t *PVECTOR_TABLE_TYPE; - - -typedef void (*IRQ_FUN)(VOID *Data); - -typedef struct _IRQ_HANDLE_ { - IRQ_FUN IrqFun; - IRQn_Type IrqNum; - u32 Data; - u32 Priority; -}IRQ_HANDLE, *PIRQ_HANDLE, IRQ_Handle; - - -#endif //_HAL_IRQN_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_log_uart.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_log_uart.h deleted file mode 100644 index 3274b056ce3..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_log_uart.h +++ /dev/null @@ -1,159 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_LOG_UART_H_ -#define _HAL_LOG_UART_H_ - -#include "hal_diag.h" - -#define LOG_UART_WAIT_FOREVER 0xffffffff - -// Define Line Control Register Bits -enum { - LCR_DLS_5B = 0, // Data Length: 5 bits - LCR_DLS_6B = BIT(0), // Data Length: 6 bits - LCR_DLS_7B = BIT(1), // Data Length: 7 bits - LCR_DLS_8B = (BIT(1)|BIT(0)), // Data Length: 7 bits - - LCR_STOP_1B = 0, // Number of stop bits: 1 - LCR_STOP_2B = BIT(2), // Number of stop bits: 1.5(data len=5) or 2 - - LCR_PARITY_NONE = 0, // Parity Enable: 0 - LCR_PARITY_ODD = BIT(3), // Parity Enable: 1, Even Parity: 0 - LCR_PARITY_EVEN = (BIT(4)|BIT(3)), // Parity Enable: 1, Even Parity: 1 - - LCR_BC = BIT(6), // Break Control Bit - LCR_DLAB = BIT(7) // Divisor Latch Access Bit -}; -typedef uint32_t LOG_UART_LINE_CTRL; - -// define Log UART Interrupt Indication ID -/* -IIR[3:0]: -0000 = modem status -0001 = no interrupt pending -0010 = THR empty -0100 = received data available -0110 = receiver line status -0111 = busy detect -1100 = character timeout -*/ -enum { - IIR_MODEM_STATUS = 0, //Clear to send or data set ready or ring indicator or data carrier detect. - IIR_NO_PENDING = 1, - IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty - IIR_RX_RDY = 4, // RX data ready - IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt - IIR_BUSY = 7, - IIR_CHAR_TIMEOUT = 12 // timeout: Rx dara ready but no read -}; -typedef uint32_t LOG_UART_INT_ID; - -// Define Interrupt Enable Bit -enum { - IER_ERBFI = BIT(0), // Enable Received Data Available Interrupt - IER_ETBEI = BIT(1), // Enable Transmit Holding Register Empty Interrupt - IER_ELSI = BIT(2), // Enable Receiver Line Status Interrupt - IER_EDSSI = BIT(3), // Enable Modem Status Interrupt - IER_PTIME = BIT(7) // Programmable THRE Interrupt Mode Enable -}; -typedef uint32_t LOG_UART_INT_EN; - -// Define Line Status Bit -enum { - LSR_DR = BIT(0), // Data Ready bit - LSR_OE = BIT(1), // Overrun error bit - LSR_PE = BIT(2), // Parity Error bit - LSR_FE = BIT(3), // Framing Error bit - LSR_BI = BIT(4), // Break Interrupt bit - LSR_THRE = BIT(5), // Transmit Holding Register Empty bit(IER_PTIME=0) - LSR_FIFOF = BIT(5), // Transmit FIFO Full bit(IER_PTIME=1) - LSR_TEMT = BIT(6), // Transmitter Empty bit - LSR_RFE = BIT(7) // Receiver FIFO Error bit -}; -typedef uint32_t LOG_UART_LINE_STATUS; - -enum { - LOG_UART_RST_TX_FIFO = 0x01, - LOG_UART_RST_RX_FIFO = 0x02 -}; - -#define LOG_UART_TX_FIFO_DEPTH 16 -#define LOG_UART_RX_FIFO_DEPTH 16 - -// Define FIFO Control Register Bits -enum { - FCR_FIFO_EN = BIT(0), // FIFO Enable. - FCR_RST_RX = BIT(1), // RCVR FIFO Reset, self clear - FCR_RST_TX = BIT(2), // XMIT FIFO Reset, self clear - FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty - FCR_TX_TRIG_2CH = BIT(4), // TX Empty Trigger: 2 characters in the FIFO - FCR_TX_TRIG_QF = BIT(5), // TX Empty Trigger: FIFO 1/4 full - FCR_TX_TRIG_HF = (BIT(5)|BIT(4)), // TX Empty Trigger: FIFO 1/2 full - FCR_TX_TRIG_MASK = (BIT(5)|BIT(4)), // TX Empty Trigger Bit Mask - FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO - FCR_RX_TRIG_QF = BIT(6), // RCVR Trigger: FIFO 1/4 full - FCR_RX_TRIG_HF = BIT(7), // RCVR Trigger: FIFO 1/2 full - FCR_RX_TRIG_AF = (BIT(7)|BIT(6)), // RCVR Trigger: FIFO 2 less than full - FCR_RX_TRIG_MASK = (BIT(7)|BIT(6)) // RCVR Trigger bits Mask -}; -typedef uint32_t LOG_UART_FIFO_CTRL; - -typedef struct _HAL_LOG_UART_ADAPTER_ { - u32 BaudRate; - u32 FIFOControl; - u32 IntEnReg; - u8 Parity; - u8 Stop; - u8 DataLength; - - u8 LineStatus; - volatile u32 TxCount; // how many byte to TX - volatile u32 RxCount; // how many bytes to RX - volatile u8 *pTxBuf; - volatile u8 *pRxBuf; - u8 *pTxStartAddr; - u8 *pRxStartAddr; - - IRQ_HANDLE IrqHandle; - VOID (*LineStatusCallback)(VOID *para, u8 status); // User Line Status interrupt callback - VOID (*TxCompCallback)(VOID *para); // User Tx complete callback - VOID (*RxCompCallback)(VOID *para); // User Rx complete callback - VOID *LineStatusCbPara; // the argument for LineStatusCallback - VOID *TxCompCbPara; // the argument for TxCompCallback - VOID *RxCompCbPara; // the argument for RxCompCallback - - void (*api_irq_handler)(u32 id, LOG_UART_INT_ID event); - u32 api_irq_id; -}HAL_LOG_UART_ADAPTER, *PHAL_LOG_UART_ADAPTER; - -VOID HalLogUartIrqHandle(VOID * Data); -VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter); -VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter); -VOID HalLogUartSetIntEn(HAL_LOG_UART_ADAPTER *pUartAdapter); -u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter); -u32 HalLogUartRecv(HAL_LOG_UART_ADAPTER *pUartAdapter, - u8 *pRxData, u32 Length, u32 TimeoutMS); -u32 HalLogUartSend(HAL_LOG_UART_ADAPTER *pUartAdapter, - u8 *pTxData, u32 Length, u32 TimeoutMS); -HAL_Status HalLogUartIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter, - u8 *pTxData, u32 Length); -HAL_Status HalLogUartIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter, - u8 *pRxData, u32 Length); -VOID HalLogUartAbortIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter); -VOID HalLogUartAbortIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter); -HAL_Status HalLogUartRstFIFO(HAL_LOG_UART_ADAPTER *pUartAdapter, u8 RstCtrl); -VOID HalLogUartEnable(HAL_LOG_UART_ADAPTER *pUartAdapter); -VOID HalLogUartDisable(HAL_LOG_UART_ADAPTER *pUartAdapter); - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_misc.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_misc.h deleted file mode 100644 index f927a82c8dd..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_misc.h +++ /dev/null @@ -1,62 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _MISC_H_ -#define _MISC_H_ - -#include - -#define CHIP_ID_8711AM 0xFF -#define CHIP_ID_8195AM 0xFE -#define CHIP_ID_8711AF 0xFD -#define CHIP_ID_8710AF 0xFC -#define CHIP_ID_8711AN 0xFB -#define CHIP_ID_8710AM 0xFA -#define CHIP_ID_SIP 0xF9 -#define CHIP_ID_COMBO_SIP 0xF8 -#define CHIP_ID_SIP2 0xF7 -#define CHIP_ID_MICO100 0xF1 - -enum _HAL_RESET_REASON{ - REASON_DEFAULT_RST = 0, /**< normal startup by power on */ - REASON_WDT_RST, /**< hardware watch dog reset */ - REASON_EXCEPTION_RST, /**< exception reset, GPIO status won't change */ - REASON_SOFT_WDT_RST, /**< software watch dog reset, GPIO status won't change */ - REASON_SOFT_RESTART, /**< software restart ,system_restart , GPIO status won't change */ - REASON_DEEP_SLEEP_AWAKE, /**< wake up from deep-sleep */ - REASON_EXT_SYS_RST /**< external system reset */ -}; -typedef u32 HAL_RESET_REASON; - -#ifdef CONFIG_TIMER_MODULE -extern _LONG_CALL_ u32 HalDelayUs(u32 us); -#endif - -extern _LONG_CALL_ u32 HalGetCpuClk(VOID); -extern _LONG_CALL_ u8 HalGetRomInfo(VOID); - -extern _LONG_CALL_ROM_ void *_memset( void *s, int c, SIZE_T n ); -extern _LONG_CALL_ROM_ void *_memcpy( void *s1, const void *s2, SIZE_T n ); -#if defined(CONFIG_RELEASE_BUILD_LIBRARIES) && (!defined(E_CUT_ROM_DOMAIN)) -// we built A/B/C cut ROM Lib with this wrong declaration, we need to keep the same for compatible -extern _LONG_CALL_ROM_ int *_memcmp( const void *av, const void *bv, SIZE_T len ); -#else -extern _LONG_CALL_ROM_ int _memcmp( const void *av, const void *bv, SIZE_T len ); -#endif -extern _LONG_CALL_ROM_ SIZE_T _strlen(const char *s); -extern _LONG_CALL_ROM_ int _strcmp(const char *cs, const char *ct); - -VOID HalSetResetCause(IN HAL_RESET_REASON reason); -HAL_RESET_REASON HalGetResetCause(VOID); - -#endif //_MISC_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_peri_on.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_peri_on.h deleted file mode 100644 index db49249ad15..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_peri_on.h +++ /dev/null @@ -1,455 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_PERI_ON_H_ -#define _HAL_PERI_ON_H_ - -#define MASK_ALLON 0xFFFFFFFF - -#define HAL_PERI_ON_READ32(addr) HAL_READ32(PERI_ON_BASE, addr) -#define HAL_PERI_ON_WRITE32(addr, value) HAL_WRITE32(PERI_ON_BASE, addr, value) -#define HAL_PERI_ON_READ16(addr) HAL_READ16(PERI_ON_BASE, addr) -#define HAL_PERI_ON_WRITE16(addr, value) HAL_WRITE16(PERI_ON_BASE, addr, value) -#define HAL_PERI_ON_READ8(addr) HAL_READ8(PERI_ON_BASE, addr) -#define HAL_PERI_ON_WRITE8(addr, value) HAL_WRITE8(PERI_ON_BASE, addr, value) -#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl) \ - HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value))) -#define HAL_PERL_ON_PIN_SEL(addr,mask,value) \ - HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value)) - -//40 REG_SYS_REGU_CTRL0 -#define LDO25M_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl) - -//A0 SYS_DEBUG_CTRL -#define DEBUG_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl) - -//A4 SYS_PINMUX_CTRL -#define SIC_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl) -#define EEPROM_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl) - - -//210 SOV_FUNC_EN -#define LXBUS_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl) -#define FLASH_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(SPI_FLASH_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);} - -#define MEM_CTRL_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(SDR_SDRAM_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);} - -#define LOC_UART_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(LOG_UART_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);} - -#define GDMA0_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(GDMA0_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);} - -#define GDMA1_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(GDMA1_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);} - -#define GTIMER_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(TIMER_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);} - -#define SECURITY_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(CRYPTO_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);} - -//214 SOC_HCI_COM_FUNC_EN -#define SDIOD_ON_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(SDIO_DEVICE_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);} - -#define SDIOD_OFF_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(SDIO_DEVICE_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);} - -#define SDIOH_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(SDIO_HOST_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);} - -#define SDIO_ON_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl) -#define OTG_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(USB_OTG_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);} - -#define OTG_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl) -#define MII_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(MII_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);} - -#define MII_MUX_SEL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl) -#define WL_MACON_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(WIFI_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);} - -//218 SOC_PERI_FUNC0_EN -#define UART0_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(UART0_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);} - -#define UART1_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(UART1_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);} - -#define UART2_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(UART2_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);} - -#define SPI0_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(SPI0_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);} - -#define SPI1_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(SPI1_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);} - -#define SPI2_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(SPI2_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);} - -#define I2C0_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(I2C0_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);} - -#define I2C1_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(I2C1_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);} - -#define I2C2_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(I2C2_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);} - -#define I2C3_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(I2C3_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);} - -#define I2S0_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(I2S0_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);} - -#define I2S1_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(I2S1_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);} - -#define PCM0_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(PCM0_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);} - -#define PCM1_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(PCM1_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);} - -//21C SOC_PERI_FUNC1_EN -#define ADC0_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(ADC_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);} - -#define DAC0_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(DAC_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);} - -#define DAC1_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(DAC_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);} - -#define GPIO_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(GPIO_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);} - -//220 SOC_PERI_BD_FUNC0_EN -#define UART0_BD_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(UART0_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);} - -#define UART1_BD_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(UART1_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);} - -#define UART2_BD_FCTRL(ctrl) { \ - if (!ctrl) { \ - HAL_READ32(UART2_REG_BASE,0);\ - }\ - HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);} - -//230 PESOC_CLK_CTRL -#define ACTCK_CPU_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl) -#define ACTCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl) -#define SLPCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl) -#define ACTCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl) -#define SLPCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl) -#define ACTCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl) -#define SLPCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl) -#define ACTCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl) -#define SLPCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl) -#define ACTCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl) -#define SLPCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl) -#define ACTCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl) -#define SLPCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl) -#define ACTCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl) -#define SLPCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl) -#define ACTCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl) -#define SLPCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl) -#define ACTCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl) -#define SLPCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl) -#define ACTCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl) -#define SLPCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl) - -//234 PESOC_PERI_CLK_CTRL0 -#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl) -#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl) -#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl) -#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl) -#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl) -#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl) -#define ACTCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl) -#define SLPCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl) -#define ACTCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl) -#define SLPCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl) -#define ACTCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl) -#define SLPCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl) - -//238 PESOC_PERI_CLK_CTRL1 -#define ACTCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl) -#define SLPCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl) -#define ACTCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl) -#define SLPCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl) -#define ACTCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl) -#define SLPCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl) -#define ACTCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl) -#define SLPCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl) -#define ACTCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl) -#define SLPCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl) -#define ACTCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl) -#define SLPCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl) -#define ACTCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl) -#define SLPCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl) -#define ACTCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl) -#define SLPCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl) - -//240 PESOC_HCI_CLK_CTRL0 -#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl) -#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl) -#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl) -#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl) -#define ACTCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl) -#define SLPCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl) -#define ACTCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl) -#define SLPCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl) - -//244 PESOC_COM_CLK_CTRL1 -#define ACTCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl) -#define SLPCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl) -#define ACTCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl) -#define SLPCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl) -#define ACTCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl) -#define SLPCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl) -#define NFC_CAL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl) - -//250 REG_PERI_CLK_SEL -#define TRACE_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num)) -#define FLASH_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num)) -#define SDR_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num)) -#define I2C_SCLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num)) - -//270 REG_OSC32K_CTRL -#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl) - -//280 REG_UART_MUX_CTRL -#define UART0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl) -#define UART0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num)) -#define UART1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl) -#define UART1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num)) -#define UART2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl) -#define UART2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num)) - -//284 REG_SPI_MUX_CTRL -#define SPI0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl) -#define SPI0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num)) -#define SPI1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl) -#define SPI1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num)) -#define SPI2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl) -#define SPI2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num)) -#define SPI0_MULTI_CS_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl) - -//288 REG_I2C_MUX_CTRL -#define I2C0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl) -#define I2C0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num)) -#define I2C1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl) -#define I2C1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num)) -#define I2C2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl) -#define I2C2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num)) -#define I2C3_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl) -#define I2C3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num)) - -//28C REG_I2S_MUX_CTRL -#define I2S0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl) -#define I2S0_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl) -#define I2S0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num)) -#define I2S1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl) -#define I2S1_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl) -#define I2S1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num)) -#define PCM0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl) -#define PCM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num)) -#define PCM1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl) -#define PCM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num)) - -//2A0 HCI_PINMUX_CTRL -#define SDIOD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl) -#define SDIOH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl) -#define MII_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl) - -//2A4 WL_PINMUX_CTRL -#define LED_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl) -#define LED_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num)) -#define ANT0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl) -#define ANT1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl) -#define BTCOEX_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl) -#define BTCMD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl) -#define NFC_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl) - -//2AC PWM_PINMUX_CTRL -#define PWM0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl) -#define PWM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num)) -#define PWM1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl) -#define PWM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num)) -#define PWM2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl) -#define PWM2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num)) -#define PWM3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl) -#define PWM3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num)) -#define ETE0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl) -#define ETE0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num)) -#define ETE1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl) -#define ETE1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num)) -#define ETE2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl) -#define ETE2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num)) -#define ETE3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl) -#define ETE3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num)) - -//2C0 CPU_PERIPHERAL_CTRL -#define SPI_FLASH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl) -#define SPI_FLASH_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num)) -#define SDR_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl) -#define TRACE_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl) -#define LOG_UART_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl) -#define LOG_UART_IR_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl) - -//300 REG_PESOC_MEM_CTRL -#define SDR_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl)) -#define FLASH_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl)) - -//304 REG_PESOC_SOC_CTRL -#define SRAM_MUX_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num)) -#define LX_WL_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl) -#define LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl) -#define LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl) -#define MII_LX_WRAPPER_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl) -#define MII_LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl) -#define MII_LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl) -#define GDMA_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num)) - -//308 PESOC_PERI_CTRL -#define SPI_RN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl) - -//320 GPIO_SHTDN_CTRL -#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl) -#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl) -#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl) -#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl) -#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl) -#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl) -#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl) -#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl) -#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl) -#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl) -#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl) - -//374 -#define EGTIM_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl) -#define EGTIM_RSIG_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num)) -#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num)) -#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num)) -#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num)) - - -#endif //_HAL_PERI_ON_H_ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pinmux.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pinmux.h deleted file mode 100644 index 28a30c5283f..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pinmux.h +++ /dev/null @@ -1,86 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _HAL_PINMUX_ -#define _HAL_PINMUX_ - - -//Function Index -#define UART0 0 -#define UART1 1 -#define UART2 2 -#define SPI0 8 -#define SPI1 9 -#define SPI2 10 -#define SPI0_MCS 15 -#define I2C0 16 -#define I2C1 17 -#define I2C2 18 -#define I2C3 19 -#define I2S0 24 -#define I2S1 25 -#define PCM0 28 -#define PCM1 29 -#define ADC0 32 -#define DAC0 36 -#define DAC1 37 -#define SDIOD 64 -#define SDIOH 65 -#define USBOTG 66 -#define MII 88 -#define WL_LED 96 -#define WL_ANT0 104 -#define WL_ANT1 105 -#define WL_BTCOEX 108 -#define WL_BTCMD 109 -#define NFC 112 -#define PWM0 160 -#define PWM1 161 -#define PWM2 162 -#define PWM3 163 -#define ETE0 164 -#define ETE1 165 -#define ETE2 166 -#define ETE3 167 -#define EGTIM 168 -#define SPI_FLASH 196 -#define SDR 200 -#define JTAG 216 -#define TRACE 217 -#define LOG_UART 220 -#define LOG_UART_IR 221 -#define SIC 224 -#define EEPROM 225 -#define DEBUG 226 - -//Location Index(Pin Mux Selection) -#define S0 0 -#define S1 1 -#define S2 2 -#define S3 3 - -_LONG_CALL_ u8 -HalPinCtrlRtl8195A( - IN u32 Function, - IN u32 PinLocation, - IN BOOL Operation); - -u8 GpioFunctionChk( - IN u32 chip_pin, - IN u8 Operation); - -u8 -FunctionChk( - IN u32 Function, - IN u32 PinLocation -); -#endif //_HAL_PINMUX_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_platform.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_platform.h deleted file mode 100644 index ca2b406bf30..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_platform.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - - -#ifndef _HAL_PLATFORM_ -#define _HAL_PLATFORM_ - -#define ROMVERSION 0x03 -#define ROMINFORMATION (ROMVERSION) - -#define SYSTEM_CLK PLATFORM_CLOCK - -#define SDR_SDRAM_BASE 0x30000000 -#define SYSTEM_CTRL_BASE 0x40000000 -#define PERI_ON_BASE 0x40000000 -#define VENDOR_REG_BASE 0x40002800 -#define SPI_FLASH_BASE 0x98000000 -#define SDR_CTRL_BASE 0x40005000 - -#define PERIPHERAL_IRQ_STATUS 0x04 -#define PERIPHERAL_IRQ_MODE 0x08 -#define PERIPHERAL_IRQ_EN 0x0C -#define LP_PERI_EXT_IRQ_STATUS 0x24 -#define LP_PERI_EXT_IRQ_MODE 0x28 -#define LP_PERI_EXT_IRQ_EN 0x2C - -#define PERIPHERAL_IRQ_ALL_LEVEL 0 - -#define TIMER_CLK 32*1000 - -//3 Peripheral IP Base Address -#define GPIO_REG_BASE 0x40001000 -#define TIMER_REG_BASE 0x40002000 -#define NFC_INTERFACE_BASE 0x40002400 -#define LOG_UART_REG_BASE 0x40003000 -#define I2C2_REG_BASE 0x40003400 -#define I2C3_REG_BASE 0x40003800 -#define SPI_FLASH_CTRL_BASE 0x40006000 -#define ADC_REG_BASE 0x40010000 -#define DAC_REG_BASE 0x40011000 -#define UART0_REG_BASE 0x40040000 -#define UART1_REG_BASE 0x40040400 -#define UART2_REG_BASE 0x40040800 -#define SPI0_REG_BASE 0x40042000 -#define SPI1_REG_BASE 0x40042400 -#define SPI2_REG_BASE 0x40042800 -#define I2C0_REG_BASE 0x40044000 -#define I2C1_REG_BASE 0x40044400 -#define SDIO_DEVICE_REG_BASE 0x40050000 -#define MII_REG_BASE 0x40050000 -#define SDIO_HOST_REG_BASE 0x40058000 -#define GDMA0_REG_BASE 0x40060000 -#define GDMA1_REG_BASE 0x40061000 -#define I2S0_REG_BASE 0x40062000 -#define I2S1_REG_BASE 0x40063000 -#define PCM0_REG_BASE 0x40064000 -#define PCM1_REG_BASE 0x40065000 -#define CRYPTO_REG_BASE 0x40070000 -#define WIFI_REG_BASE 0x40080000 -#define USB_OTG_REG_BASE 0x400C0000 - -#define GDMA1_REG_OFF 0x1000 -#define I2S1_REG_OFF 0x1000 -#define PCM1_REG_OFF 0x1000 -#define SSI_REG_OFF 0x400 -#define RUART_REG_OFF 0x400 - -#define CPU_CLK_TYPE_NO 6 - -enum _BOOT_TYPE_ { - BOOT_FROM_FLASH = 0, - BOOT_FROM_SDIO = 1, - BOOT_FROM_USB = 2, - BOOT_FROM_RSVD = 3, -}; - -enum _EFUSE_CPU_CLK_ { - #if 1 - CLK_200M = 0, - CLK_100M = 1, - CLK_50M = 2, - CLK_25M = 3, - CLK_12_5M = 4, - CLK_4M = 5, - #else - CLK_25M = 0, - CLK_200M = 1, - CLK_100M = 2, - CLK_50M = 3, - CLK_12_5M = 4, - CLK_4M = 5, - #endif -}; - - -#endif //_HAL_PLATFORM_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pwm.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pwm.h deleted file mode 100644 index 9197e5abef1..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pwm.h +++ /dev/null @@ -1,69 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_PWM_H_ -#define _HAL_PWM_H_ - -#define MAX_PWM_CTRL_PIN 4 -#define MAX_GTIMER_NUM 4 -#define MAX_DEVID_TICK 1020 - -// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T) -//#define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5 -#define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2 -#define PWM_GTIMER_TICK_TIME 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2 - -typedef struct _HAL_PWM_ADAPTER_ { - u8 pwm_id; // the PWM ID, 0~3 - u8 sel; // PWM Pin selection, 0~3 - u8 gtimer_id; // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6 - u8 enable; // is enabled -// u32 timer_value; // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM - u32 tick_time; // the tick time for the G-timer - u32 period; // the period of a PWM control cycle, in PWM tick - u32 pulsewidth; // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio -// float duty_ratio; // the dyty ratio = pulswidth/period -}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER; - -typedef struct _HAL_PWM_GTIMER_ { - u32 tick_time; // the tick time for the G-timer - u8 reference; // map of referenced by PWM -}HAL_PWM_TIMER, *PHAL_PWM_TIMER; - -extern HAL_Status -HAL_Pwm_Init( - HAL_PWM_ADAPTER *pPwmAdapt, - u32 pwm_id, - u32 sel -); - -extern void -HAL_Pwm_Enable( - HAL_PWM_ADAPTER *pPwmAdapt -); - -extern void -HAL_Pwm_Disable( - HAL_PWM_ADAPTER *pPwmAdapt -); - -extern void -HAL_Pwm_SetDuty( - HAL_PWM_ADAPTER *pPwmAdapt, - u32 period, - u32 pulse_width -); - - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_soc_ps_monitor.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_soc_ps_monitor.h deleted file mode 100644 index 85aa3169628..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_soc_ps_monitor.h +++ /dev/null @@ -1,354 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _HAL_SOCPWR_ -#define _HAL_SOCPWR_ - - - -#define MAX_BACKUP_SIZE 129 -#define MAXFUNC 10 -#define FSTREG 0xFF - -#define REG_VDR_ANACK_CAL_CTRL 0xA0 - -#define PS_MASK 0xFFFFFFFF - -//pwr state -#define HWACT 0 -#define HWCG 1 -#define HWINACT 2 -#define UNDEF 3 -#define ALLMET 0xff - -//SLP -#define SLP_STIMER BIT0 -#define SLP_GTIMER BIT1 -#define SLP_GPIO BIT2 -#define SLP_WL BIT3 -#define SLP_NFC BIT4 -#define SLP_SDIO BIT5 -#define SLP_USB BIT6 -#define SLP_TIMER33 BIT7 - -//DSTBY -#define DSTBY_STIMER BIT0 -#define DSTBY_NFC BIT1 -#define DSTBY_TIMER33 BIT2 -#define DSTBY_GPIO BIT3 - -//DS wake event -#define DS_TIMER33 BIT0 -#define DS_GPIO BIT1 - -enum power_state_idx{ - ACT = 0, - WFE = 1, - WFI = 2, - SNOOZE = 3, - SLPCG = 4, - SLPPG = 5, - DSTBY = 6, - DSLP = 7, - INACT = 8, - MAXSTATE = 9 -}; - -enum clk_idx{ - ANACK = 0, - A33CK = 1, -}; - - -typedef struct _power_state_{ - u8 FuncIdx; - u8 PowerState; -}POWER_STATE, *pPOWER_STATE; - -typedef struct _reg_power_state_{ - u8 FuncIdx; - u8 PwrState; -}REG_POWER_STATE, *pPREG_POWER_STATE; - -#if 0 -typedef struct _power_state_{ - u8 FuncIdx; - u8 PowerState; - u32 ReqDuration; - u32 RegCount; - u32 RemainDuration; -}POWER_STATE, *pPOWER_STATE; - -typedef struct _reg_power_state_{ - u8 FuncIdx; - u8 PwrState; - u32 ReqDuration; - //u8 StateIdx; -}REG_POWER_STATE, *pPREG_POWER_STATE; -#endif - -typedef struct _power_mgn_{ - u8 ActFuncCount; - POWER_STATE PwrState[MAXFUNC]; - u8 CurrentState; - u8 SDREn; - u32 MSPbackup[MAX_BACKUP_SIZE]; - u32 CPURegbackup[25]; - u32 CPUPSP; - u32 WakeEventFlag; - BOOL SleepFlag; - //u32 CPUReg[13]; - //u32 MSBackUp[128]; -}Power_Mgn, *pPower_Mgn; - -typedef struct _SYS_ADAPTER_ { - u8 function; -}SYS_ADAPTER, *PSYS_ADAPTER; - -extern Power_Mgn PwrAdapter; - -u8 ChangeSoCPwrState( - IN u8 RequestState, - IN u32 ReqCount -); - -VOID PrintCPU(VOID); -void WakeFromSLPPG(void); -VOID SOCPSTestApp(VOID *Data); - - -#if defined (__CC_ARM) -static __asm __inline VOID CPURegBackUp(VOID) -{ - // TODO: ARM compiler has different way using assembly - -/* //backup cpu reg - #if 0 - asm volatile - ( - "PUSH {PSR, PC, LR, R12,R3,R2,R1,R0}\n" - ); - #endif - #if 0 - asm volatile - ( - "PUSH {r0,r1,r2,r3,r4}\n" - ); - #endif - - // asm volatile - // { - MOV (PwrAdapter.CPURegbackup[0]), R0 - MOV (PwrAdapter.CPURegbackup[1]), R1 - MOV (PwrAdapter.CPURegbackup[2]), R2 - MOV (PwrAdapter.CPURegbackup[3]), R3 - MOV (PwrAdapter.CPURegbackup[4]), R4 - MOV (PwrAdapter.CPURegbackup[5]), R5 - MOV (PwrAdapter.CPURegbackup[6]), R6 - MOV (PwrAdapter.CPURegbackup[7]), R7 - MOV (PwrAdapter.CPURegbackup[8]), R8 - MOV (PwrAdapter.CPURegbackup[9]), R9 - MOV (PwrAdapter.CPURegbackup[10]), R10 - MOV (PwrAdapter.CPURegbackup[11]), R11 - MOV (PwrAdapter.CPURegbackup[12]), R12 - - //MOV (PwrAdapter.CPURegbackup[13]), R13 - MOV (PwrAdapter.CPURegbackup[13]), SP - - //MOV %0, R14 - LDR (PwrAdapter.CPURegbackup[14]), =SLPPG_WAKEUP_POINT - ADD (PwrAdapter.CPURegbackup[14]), #1 - - LDR (PwrAdapter.CPURegbackup[15]), =SLPPG_WAKEUP_POINT - ADD (PwrAdapter.CPURegbackup[15]), #1 - - MRS (PwrAdapter.CPURegbackup[16]), PSR -// }; - -#if 1 - // asm volatile -//{ - MOV (PwrAdapter.CPURegbackup[24]), R13 - MOV (PwrAdapter.CPURegbackup[23]), PC - MRS (PwrAdapter.CPURegbackup[22]), CONTROL - MRS (PwrAdapter.CPURegbackup[21]), PSP - MRS (PwrAdapter.CPURegbackup[20]), MSP - // }; -#endif - #ifdef CONFIG_SOC_PS_VERIFY - PrintCPU(); - #endif //#ifdef CONFIG_SOC_PS_VERIFY*/ -} -#else -__inline static VOID -CPURegBackUp( - VOID -) -{ -#if defined (__ICCARM__) - // TODO: IAR has different way using assembly -#elif defined (__GNUC__) - //backup cpu reg - #if 0 - asm volatile - ( - "PUSH {PSR, PC, LR, R12,R3,R2,R1,R0}\n" - ); - #endif - #if 0 - asm volatile - ( - "PUSH {r0,r1,r2,r3,r4}\n" - ); - #endif - - asm volatile - ( - - "MOV %0, r0\n" - :"=r"(PwrAdapter.CPURegbackup[0]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r1\n" - :"=r"(PwrAdapter.CPURegbackup[1]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r2\n" - :"=r"(PwrAdapter.CPURegbackup[2]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r3\n" - :"=r"(PwrAdapter.CPURegbackup[3]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r4\n" - :"=r"(PwrAdapter.CPURegbackup[4]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r5\n" - :"=r"(PwrAdapter.CPURegbackup[5]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r6\n" - :"=r"(PwrAdapter.CPURegbackup[6]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r7\n" - :"=r"(PwrAdapter.CPURegbackup[7]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r8\n" - :"=r"(PwrAdapter.CPURegbackup[8]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r9\n" - :"=r"(PwrAdapter.CPURegbackup[9]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r10\n" - :"=r"(PwrAdapter.CPURegbackup[10]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r11\n" - :"=r"(PwrAdapter.CPURegbackup[11]) - ::"memory" - ); - asm volatile - ( - "MOV %0, r12\n" - :"=r"(PwrAdapter.CPURegbackup[12]) - ::"memory" - ); - - asm volatile - ( - "MOV %0, r13\n" - :"=r"(PwrAdapter.CPURegbackup[13]) - ::"memory" - ); - asm volatile - ( - //"MOV %0, r14\n" - "LDR %0, =SLPPG_WAKEUP_POINT\n" - "ADD %0, #1\n" - :"=r"(PwrAdapter.CPURegbackup[14]) - ::"memory" - ); - asm volatile - ( - "LDR %0, =SLPPG_WAKEUP_POINT\n" - "ADD %0, #1\n" - :"=r"(PwrAdapter.CPURegbackup[15]) - ::"memory" - ); - asm volatile - ( - "MRS %0, PSR\n" - :"=r"(PwrAdapter.CPURegbackup[16]) - ::"memory" - ); - -#if 1 - asm volatile - ( - "mov %0, r13\n" - "MOV %1, PC\n" - "MRS %2, CONTROL\n" - "MRS %3, PSP\n" - "MRS %4, MSP\n" - :"=r"(PwrAdapter.CPURegbackup[24]),"=r"(PwrAdapter.CPURegbackup[23]),"=r"(PwrAdapter.CPURegbackup[22]),"=r"(PwrAdapter.CPURegbackup[21]),"=r"(PwrAdapter.CPURegbackup[20]) - ::"memory" - ); -#endif - #ifdef CONFIG_SOC_PS_VERIFY - PrintCPU(); - #endif //#ifdef CONFIG_SOC_PS_VERIFY -#endif //#elif defined (__GNUC__) -} -#endif - -VOID RegPowerState(REG_POWER_STATE RegPwrState); - -#endif //_HAL_SOCPWR_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_spi_flash.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_spi_flash.h deleted file mode 100644 index 6380ed97bb1..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_spi_flash.h +++ /dev/null @@ -1,385 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - - -#ifndef _HAL_SPIFLASH__ -#define _HAL_SPIFLASH__ -//====================================================== -// Header files - -#define SPIC_CALIBRATION_IN_NVM 1 // if store the SPIC calibration data in the NVM -#ifndef CONFIG_IMAGE_SEPARATE // Store SPIC Calibration only for seprated image -#undef SPIC_CALIBRATION_IN_NVM -#define SPIC_CALIBRATION_IN_NVM 0 -#endif - -//====================================================== -// Definition -#define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32) -#define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16) -#define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8) -#define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr) -#define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr) -#define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr) - -typedef struct _SPIC_PARA_MODE_ { - u8 Valid:1; // valid - u8 CpuClk:3; // CPU clock - u8 BitMode:2; // Bit mode - u8 Reserved:2; // reserved -} SPIC_PARA_MODE, *PSPIC_PARA_MODE; - -typedef struct _SPIC_INIT_PARA_ { - u8 BaudRate; - u8 RdDummyCyle; - u8 DelayLine; - union { - u8 Rsvd; - u8 Valid; - SPIC_PARA_MODE Mode; - }; -#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES)) - u8 id[3]; - u8 flashtype; -#endif -}SPIC_INIT_PARA, *PSPIC_INIT_PARA; - - -enum _SPIC_BIT_MODE_ { - SpicOneBitMode = 0, - SpicDualBitMode = 1, - SpicQuadBitMode = 2, -}; - -//====================================================== -// Flash type used -#define FLASH_OTHERS 0 -#define FLASH_MXIC 1 -#define FLASH_MXIC_4IO 2 -#define FLASH_WINBOND 3 -#define FLASH_MICRON 4 -#define FLASH_EON 5 -#define FLASH_GD 6 -#define FLASH_CYPRESS 7 - -//#define FLASH_MXIC_MX25L4006E 0 -//#define FLASH_MXIC_MX25L8073E 0 -//#define FLASH_MICRON_N25Q512A 1 -// The below parts are based on the flash characteristics -//====== Flash Command Definition ====== -//#if FLASH_MICRON_N25Q512A - -/*Common command*/ -#define FLASH_CMD_WREN 0x06 //write enable -#define FLASH_CMD_WRDI 0x04 //write disable -#define FLASH_CMD_WRSR 0x01 //write status register -#define FLASH_CMD_RDID 0x9F //read idenfication -#define FLASH_CMD_RDUID 0x4B //Read Unique ID -#define FLASH_CMD_RDSR 0x05 //read status register -#define FLASH_CMD_RDSFDP 0x5A //Read SFDP -#define FLASH_CMD_READ 0x03 //read data -#define FLASH_CMD_FREAD 0x0B //fast read data -#define FLASH_CMD_PP 0x02 //Page Program -#define FLASH_CMD_DREAD 0x3B //Double Output Mode command 1-1-2 -#define FLASH_CMD_2READ 0xBB // 2 x I/O read command 1-2-2 -#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 1-1-4 -#define FLASH_CMD_4READ 0xEB // 4 x I/O read command 1-4-4 -#define FLASH_CMD_DPP 0xA2 // 1-1-2 -#define FLASH_CMD_2PP 0xD2 // 1-2-2 -#define FLASH_CMD_QPP 0x32 // 1-1-4 -#define FLASH_CMD_4PP 0x38 //quad page program 1-4-4 -#define FLASH_CMD_SE 0x20 //Sector Erase -#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52) -#define FLASH_CMD_CE 0xC7 //Chip Erase(or 0xC7) -#define FLASH_CMD_DP 0xB9 //Deep Power Down -#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down - -/*Micron Special command*/ -#define FLASH_CMD_DE 0xC4 -#define FLASH_CMD_4PP2 0x12 -#define FLASH_CMD_RFSR 0x70 -#define FLASH_CMD_CFSR 0x50 -#define FLASH_CMD_RNCR 0xB5 -#define FLASH_CMD_WNCR 0xB1 -#define FLASH_CMD_RVCR 0x85 -#define FLASH_CMD_WVCR 0x81 -#define FLASH_CMD_REVCR 0x65 -#define FLASH_CMD_WEVCR 0x61 -#define FLASH_CMD_REAR 0xC8 -#define FLASH_CMD_WEAR 0xC5 -#define FLASH_CMD_ENQUAD 0x35 -#define FLASH_CMD_EXQUAD 0xF5 - -/*MXIC Special command*/ -#define FLASH_CMD_RDCR 0x15 //read configurate register -#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode -#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode -#define FLASH_CMD_ENSO 0xB1 // enter secured OTP -#define FLASH_CMD_EXSO 0xC1 // exit secured OTP -#define FLASH_CMD_RDSCUR 0x2B // read security register -#define FLASH_CMD_WRSCUR 0x2F // write security register - -/*WINBOND Special command*/ -#define FLASH_CMD_GLOCK 0x7E -#define FLASH_CMD_GUNLOCK 0x98 -#define FLASH_CMD_RLOCK 0x3D -#define FLASH_CMD_SLOCK 0x36 -#define FLASH_CMD_SUNLOCK 0x39 -#define FLASH_CMD_WRSR3 0x11 -#define FLASH_CMD_RDSR3 0x15 - -/*Cypress Special command*/ -#define FLASH_CMD_RDSR4 0x07 //read status register 2 -#define FLASH_CMD_CLSR 0x30 //Clear status register 2 error bit - -//#endif -#if 0 -#if FLASH_MXIC_MX25L4006E - #define FLASH_CMD_WREN 0x06 //write enable - #define FLASH_CMD_WRDI 0x04 //write disable - #define FLASH_CMD_WRSR 0x01 //write status register - #define FLASH_CMD_RDID 0x9F //read idenfication - #define FLASH_CMD_RDSR 0x05 //read status register - #define FLASH_CMD_READ 0x03 //read data - #define FLASH_CMD_FREAD 0x0B //fast read data - #define FLASH_CMD_RDSFDP 0x5A //Read SFDP - #define FLASH_CMD_RES 0xAB //Read Electronic ID - #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID - #define FLASH_CMD_DREAD 0x3B //Double Output Mode command - #define FLASH_CMD_SE 0x20 //Sector Erase - #define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52) - #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) - #define FLASH_CMD_PP 0x02 //Page Program - #define FLASH_CMD_DP 0xB9 //Deep Power Down - #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down - #define FLASH_CMD_RDCR 0x15 //read configurate register - #define FLASH_CMD_2READ 0xBB // 2 x I/O read command - #define FLASH_CMD_4READ 0xEB // 4 x I/O read command - #define FLASH_CMD_QREAD 0x6B // 1I / 4O read command - #define FLASH_CMD_4PP 0x38 //quad page program - #define FLASH_CMD_FF 0xFF //Release Read Enhanced - #define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode - #define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode - #define FLASH_CMD_ENSO 0xB1 // enter secured OTP - #define FLASH_CMD_EXSO 0xC1 // exit secured OTP - #define FLASH_CMD_RDSCUR 0x2B // read security register - #define FLASH_CMD_WRSCUR 0x2F // write security register -#elif FLASH_MXIC_MX25L8073E - #define FLASH_CMD_WREN 0x06 //write enable - #define FLASH_CMD_WRDI 0x04 //write disable - #define FLASH_CMD_WRSR 0x01 //write status register - #define FLASH_CMD_RDID 0x9F //read idenfication - #define FLASH_CMD_RDSR 0x05 //read status register - #define FLASH_CMD_READ 0x03 //read data - #define FLASH_CMD_FREAD 0x0B //fast read data - #define FLASH_CMD_RDSFDP 0x5A //Read SFDP - #define FLASH_CMD_RES 0xAB //Read Electronic ID - #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID - #define FLASH_CMD_DREAD 0x3B //Double Output Mode command - #define FLASH_CMD_SE 0x20 //Sector Erase - #define FLASH_CMD_BE 0x52 //Block Erase - #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) - #define FLASH_CMD_PP 0x02 //Page Program - #define FLASH_CMD_DP 0xB9 //Deep Power Down - #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down - #define FLASH_CMD_2READ 0xBB // 2 x I/O read command - #define FLASH_CMD_4READ 0xEB // 4 x I/O read command - #define FLASH_CMD_QREAD 0x6B // 1I / 4O read command - #define FLASH_CMD_4PP 0x38 //quad page program - #define FLASH_CMD_FF 0xFF //Release Read Enhanced - #define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode - #define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode - #define FLASH_CMD_ENSO 0xB1 // enter secured OTP - #define FLASH_CMD_EXSO 0xC1 // exit secured OTP - #define FLASH_CMD_RDSCUR 0x2B // read security register - #define FLASH_CMD_WRSCUR 0x2F // write security register -#else - #define FLASH_CMD_WREN 0x06 //write enable - #define FLASH_CMD_WRDI 0x04 //write disable - #define FLASH_CMD_WRSR 0x01 //write status register - #define FLASH_CMD_RDID 0x9F //read idenfication - #define FLASH_CMD_RDSR 0x05 //read status register - #define FLASH_CMD_READ 0x03 //read data - #define FLASH_CMD_FREAD 0x0B //fast read data - #define FLASH_CMD_RDSFDP 0x5A //Read SFDP - #define FLASH_CMD_RES 0xAB //Read Electronic ID - #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID - #define FLASH_CMD_DREAD 0x3B //Double Output Mode command - #define FLASH_CMD_SE 0x20 //Sector Erase - #define FLASH_CMD_BE 0x52 //Block Erase - #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) - #define FLASH_CMD_PP 0x02 //Page Program - #define FLASH_CMD_DP 0xB9 //Deep Power Down - #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down - #define FLASH_CMD_2READ 0xBB // 2 x I/O read command - #define FLASH_CMD_4READ 0xEB // 4 x I/O read command - #define FLASH_CMD_QREAD 0x6B // 1I / 4O read command - #define FLASH_CMD_4PP 0x38 //quad page program - #define FLASH_CMD_FF 0xFF //Release Read Enhanced - #define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode - #define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode - #define FLASH_CMD_ENSO 0xB1 // enter secured OTP - #define FLASH_CMD_EXSO 0xC1 // exit secured OTP - #define FLASH_CMD_RDSCUR 0x2B // read security register - #define FLASH_CMD_WRSCUR 0x2F // write security register -#endif //#if FLASH_MXIC_MX25L4006E -#endif -// ============================ - -// ===== Flash Parameter Definition ===== -//#if FLASH_MICRON_N25Q512A -#if 0 -#define FLASH_RD_2IO_EN 1 -#define FLASH_RD_2O_EN 1 -#define FLASH_RD_4IO_EN 1 -#define FLASH_RD_4O_EN 1 -#define FLASH_WR_2IO_EN 1 -#define FLASH_WR_2O_EN 1 -#define FLASH_WR_4IO_EN 1 -#define FLASH_WR_4O_EN 1 -#endif -#define FLASH_DM_CYCLE_2O 0x08 // 1-1-2 -#define FLASH_DM_CYCLE_2IO 0x04 // 1-2-2 -#define FLASH_DM_CYCLE_4O 0x08 // 1-1-4 -#define FLASH_DM_CYCLE_4IO 0x08 // 1-4-4 -#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)// 1-1-2 -#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_RD_QUAD_IO)// 1-4-4 -#define FLASH_VLD_QUAD_CMDS2 (BIT_WR_BLOCKING | BIT_RD_QUAD_O)// 1-1-4 - - -//#endif -#if 0 -#if FLASH_MXIC_MX25L4006E -#define FLASH_RD_2IO_EN 1 -#define FLASH_RD_2O_EN 0 -#define FLASH_RD_4IO_EN 1 -#define FLASH_RD_4O_EN 0 -#define FLASH_WR_2IO_EN 1 -#define FLASH_WR_2O_EN 0 -#define FLASH_WR_4IO_EN 1 -#define FLASH_WR_4O_EN 0 -#define FLASH_DM_CYCLE_2O 0x04 // 1-1-2 -#define FLASH_DM_CYCLE_2IO 0x08 // 1-2-2 -#define FLASH_DM_CYCLE_4O 0x04 // 1-1-4 -#define FLASH_DM_CYCLE_4IO 0x08 // 1-4-4 -#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_WR_DUAL_II | BIT_RD_DUAL_IO) -#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO) - -#elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it, - //the code MUST be rechecked according to the flash spec. - #define FLASH_RD_2IO_EN 1 - #define FLASH_RD_2O_EN 0 - #define FLASH_RD_4IO_EN 1 - #define FLASH_RD_4O_EN 0 - #define FLASH_WR_2IO_EN 1 - #define FLASH_WR_2O_EN 0 - #define FLASH_WR_4IO_EN 1 - #define FLASH_WR_4O_EN 0 - - #define FLASH_DM_CYCLE_2O 0x08 - #define FLASH_DM_CYCLE_2IO 0x04 - #define FLASH_DM_CYCLE_4O 0x08 - #define FLASH_DM_CYCLE_4IO 0x04 - - #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO) - #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO) -#else - #define FLASH_RD_2IO_EN 1 - #define FLASH_RD_2O_EN 0 - #define FLASH_RD_4IO_EN 1 - #define FLASH_RD_4O_EN 0 - #define FLASH_WR_2IO_EN 1 - #define FLASH_WR_2O_EN 0 - #define FLASH_WR_4IO_EN 1 - #define FLASH_WR_4O_EN 0 - - #define FLASH_DM_CYCLE_2O 0x08 - #define FLASH_DM_CYCLE_2IO 0x04 - #define FLASH_DM_CYCLE_4O 0x08 - #define FLASH_DM_CYCLE_4IO 0x04 - - #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO) - #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO) -#endif -#endif -#if 0 -//====================================================== -// Function prototype -BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode); - -_LONG_CALL_ -extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); - -// spi-flash controller initialization -_LONG_CALL_ -extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); - -// wait sr[0] = 0, wait transmission done -_LONG_CALL_ -extern VOID SpicWaitBusyDoneRtl8195A(VOID); - -// wait spi-flash status register[0] = 0 -//_LONG_CALL_ -//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); -#endif - -//====================================================== -// ROM Function prototype -_LONG_CALL_ VOID SpiFlashAppV02(IN VOID *Data); -_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN u8 InitBaudRate,IN u8 SpicBitMode); - -_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID); - -_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN u8 CpuClkMode,IN u8 BaudRate,IN PSPIC_INIT_PARA pSpicInitPara); - - -VOID SpicBlockEraseFlashRtl8195A(IN u32 Address); -VOID SpicSectorEraseFlashRtl8195A(IN u32 Address); -VOID SpicDieEraseFlashRtl8195A(IN u32 Address); -VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect); -VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); -VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara); -VOID SpicTxCmdWithDataRtl8195A(IN u8 cmd,IN u8 DataPhaseLen,IN u8* pData,IN SPIC_INIT_PARA SpicInitPara); -VOID SpicTxCmdWithDataNoCheckRtl8195A(IN u8 cmd, IN u8 DataPhaseLen,IN u8* pData); -VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara); -VOID SpicRxCmdWithDataRtl8195A(IN u8 cmd,IN u8 DataPhaseLen, IN u8* pData,IN SPIC_INIT_PARA SpicInitPara); -u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); -u8 SpicGetFlashStatus3Rtl8195A(IN SPIC_INIT_PARA SpicInitPara); -u8 SpicGetFlashStatus4Rtl8195A(IN SPIC_INIT_PARA SpicInitPara); -VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode); -u32 SpicWaitWipRtl8195A(VOID); -u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk); -VOID SpicDisableRtl8195A(VOID); -VOID SpicDeepPowerDownFlashRtl8195A(VOID); -VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo); -VOID SpicUserReadRtl8195A(IN u32 Length, IN u32 addr, IN u8 * data, IN u8 BitMode); -VOID SpicUserReadFourByteRtl8195A(IN u32 Length, IN u32 addr, IN u32 * data, IN u8 BitMode); -VOID SpicReadUniqueIDRtl8195A(IN u8 *buff,IN u8 len); -VOID SpicReadIDRtl8195A(VOID); -VOID SpicSetFlashStatusRefinedRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara); -VOID SpicSetExtendAddrRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara); -u8 SpicGetExtendAddrRtl8195A(IN SPIC_INIT_PARA SpicInitPara); -VOID SpicSetLockModeRtl8195A(IN u8 Mode); -VOID SpicLockFlashRtl8195A(VOID); -VOID SpicUnlockFlashRtl8195A(VOID); -VOID SpicSingleLockRtl8195A(IN u32 Address); -VOID SpicSingleUnlockRtl8195A(IN u32 Address); -u8 SpicReadLockStateRtl8195A(IN u32 Address); - -#if SPIC_CALIBRATION_IN_NVM -VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk); -VOID SpicNVMCalLoadAll(void); -VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk); -#endif // #if SPIC_CALIBRATION_IN_NVM - -#endif //_HAL_SPIFLASH__ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_ssi.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_ssi.h deleted file mode 100644 index 43881a18d25..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_ssi.h +++ /dev/null @@ -1,344 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_SSI_H_ -#define _HAL_SSI_H_ - -#include "rtl8195a_ssi.h" - -/** - * LOG Configurations - */ - -extern u32 SSI_DBG_CONFIG; -extern uint8_t SPI0_IS_AS_SLAVE; - - -#define SSI_DBG_ENTRANCE(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) { \ - DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \ - } \ -}while(0) - -#define SSI_DBG_INIT(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_INIT_V(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_INIT_VV(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_PINMUX(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_ENDIS(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_INT(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_INT_V(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_INT_HNDLR(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_INT_READ(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_INT_WRITE(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_STATUS(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_FIFO(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_READ(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_WRITE(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -#define SSI_DBG_SLV_CTRL(...) do {\ - if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \ - DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ -}while(0) - -enum _SSI_DBG_TYPE_LIST_ { - DBG_TYPE_ENTRANCE = 1 << 0, - DBG_TYPE_INIT = 1 << 1, - DBG_TYPE_INIT_V = 1 << 2, - DBG_TYPE_INIT_VV = 1 << 3, - DBG_TYPE_PINMUX = 1 << 4, - DBG_TYPE_ENDIS = 1 << 5, - DBG_TYPE_INT = 1 << 6, - DBG_TYPE_INT_V = 1 << 7, - DBG_TYPE_INT_HNDLR = 1 << 8, - DBG_TYPE_INT_READ = 1 << 9, - DBG_TYPE_INT_WRITE = 1 << 10, - DBG_TYPE_STATUS = 1 << 11, - DBG_TYPE_FIFO = 1 << 12, - DBG_TYPE_READ = 1 << 13, - DBG_TYPE_WRITE = 1 << 14, - DBG_TYPE_SLV_CTRL = 1 << 15 -}; -typedef uint32_t SSI_DBG_TYPE_LIST; -typedef uint32_t *PSSI_DBG_TYPE_LIST; - - typedef struct _SSI_DMA_CONFIG_ { - VOID *pHalGdmaOp; - VOID *pTxHalGdmaAdapter; - VOID *pRxHalGdmaAdapter; - u8 RxDmaBurstSize; - u8 TxDmaBurstSize; - u8 RxDmaEnable; - u8 TxDmaEnable; - IRQ_HANDLE RxGdmaIrqHandle; - IRQ_HANDLE TxGdmaIrqHandle; -}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG; - -#if CONFIG_GDMA_EN -typedef struct _HAL_SSI_DMA_MULTIBLK_ { - volatile GDMA_CH_LLI_ELE GdmaChLli[16]; - struct GDMA_CH_LLI Lli[16]; - struct BLOCK_SIZE_LIST BlockSizeList[16]; -}SSI_DMA_MULTIBLK, *PSSI_DMA_MULTIBLK; -#endif -/** - * DesignWare SSI Configurations - */ -typedef struct _HAL_SSI_ADAPTOR_ { - SSI_DMA_CONFIG DmaConfig; - IRQ_HANDLE IrqHandle; - // - VOID (*RxCompCallback)(VOID *Para); - VOID *RxCompCbPara; - VOID *RxData; - VOID (*TxCompCallback)(VOID *Para); - VOID *TxCompCbPara; - VOID *TxData; - u32 DmaRxDataLevel; - u32 DmaTxDataLevel; - u32 InterruptPriority; - u32 RxLength; - u32 RxLengthRemainder; - u32 RxThresholdLevel; - u32 TxLength; - u32 TxThresholdLevel; - u32 SlaveSelectEnable; - // - u16 ClockDivider; - u16 DataFrameNumber; - // - u8 ControlFrameSize; - u8 DataFrameFormat; - u8 DataFrameSize; - u8 DmaControl; - u8 Index; - u8 InterruptMask; - u8 MicrowireDirection; - u8 MicrowireHandshaking; - u8 MicrowireTransferMode; - u8 PinmuxSelect; - u8 Role; - u8 SclkPhase; - u8 SclkPolarity; - u8 SlaveOutputEnable; - u8 TransferMode; - u8 TransferMechanism; - - // Extend - u8 Reserve; - u8 HaveTxChannel; - u8 HaveRxChannel; - u8 DefaultRxThresholdLevel; - #if CONFIG_GDMA_EN - SSI_DMA_MULTIBLK DmaTxMultiBlk, DmaRxMultiBlk; - #endif - u32 ReservedDummy; - VOID (*TxIdleCallback)(VOID *Para); - VOID *TxIdleCbPara; -}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR; - -typedef struct _HAL_SSI_OP_{ - HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor); - HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor); - HAL_Status (*HalSsiEnable)(VOID *Adaptor); - HAL_Status (*HalSsiDisable)(VOID *Adaptor); - HAL_Status (*HalSsiInit)(VOID *Adaptor); - HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor); - HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor); - HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value); - HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting); - HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor); - HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role); - HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor); - HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor); - HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length); - HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor); - HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor); - HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length); - HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex); - u32 (*HalSsiBusy)(VOID *Adaptor); - u32 (*HalSsiReadable)(VOID *Adaptor); - u32 (*HalSsiWriteable)(VOID *Adaptor); - u32 (*HalSsiGetInterruptMask)(VOID *Adaptor); - u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor); - u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor); - u32 (*HalSsiGetStatus)(VOID *Adaptor); - u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor); - u32 (*HalSsiRead)(VOID *Adaptor); - u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor); - u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor); -}HAL_SSI_OP, *PHAL_SSI_OP; - -typedef struct _DW_SSI_DEFAULT_SETTING_ { - VOID (*RxCompCallback)(VOID *Para); - VOID *RxCompCbPara; - VOID *RxData; - VOID (*TxCompCallback)(VOID *Para); - VOID *TxCompCbPara; - VOID *TxData; - u32 DmaRxDataLevel; - u32 DmaTxDataLevel; - u32 InterruptPriority; - u32 RxLength; - u32 RxLengthRemainder; - u32 RxThresholdLevel; - u32 TxLength; - u32 TxThresholdLevel; - u32 SlaveSelectEnable; - // - u16 ClockDivider; - u16 DataFrameNumber; - // - u8 ControlFrameSize; - u8 DataFrameFormat; - u8 DataFrameSize; - u8 DmaControl; - //u8 Index; - u8 InterruptMask; - u8 MicrowireDirection; - u8 MicrowireHandshaking; - u8 MicrowireTransferMode; - //u8 PinmuxSelect; - //u8 Role; - u8 SclkPhase; - u8 SclkPolarity; - u8 SlaveOutputEnable; - u8 TransferMode; - u8 TransferMechanism; -} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING; - - -struct spi_s { - HAL_SSI_ADAPTOR spi_adp; - HAL_SSI_OP spi_op; - u32 irq_handler; - u32 irq_id; - u32 dma_en; - volatile u32 state; - u8 sclk; -#if CONFIG_GDMA_EN - HAL_GDMA_ADAPTER spi_gdma_adp_tx; - HAL_GDMA_ADAPTER spi_gdma_adp_rx; -#endif - u32 bus_tx_done_handler; - u32 bus_tx_done_irq_id; -}; - -VOID HalSsiOpInit(VOID *Adaptor); -static __inline__ VOID HalSsiSetSclk( - IN PHAL_SSI_ADAPTOR pHalSsiAdapter, - IN u32 ClkRate) -{ - HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate); -} - -HAL_Status HalSsiInit(VOID * Data); -HAL_Status HalSsiDeInit(VOID * Data); -HAL_Status HalSsiEnable(VOID * Data); -HAL_Status HalSsiDisable(VOID * Data); -HAL_Status HalSsiEnterCritical(VOID * Data); -HAL_Status HalSsiExitCritical(VOID * Data); -HAL_Status HalSsiTimeout(u32 StartCount, u32 TimeoutCnt); -HAL_Status HalSsiStopRecv(VOID * Data); -HAL_Status HalSsiSetFormat(VOID * Data); -VOID HalSsiClearFIFO(VOID * Data); -#if CONFIG_GDMA_EN -HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter); -VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter); -HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter); -VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter); -HAL_Status HalSsiRxMultiBlkChnl(PHAL_SSI_ADAPTOR pHalSsiAdapter); -HAL_Status HalSsiDmaRecv(VOID * Adapter, u8 * pRxData, u32 Length); -HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length); - -static __inline__ VOID -HalSsiDmaInit( - IN PHAL_SSI_ADAPTOR pHalSsiAdapter -) -{ - #if CONFIG_CHIP_E_CUT - HalSsiDmaInitRtl8195a_V04((void *)pHalSsiAdapter); - #else - HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter); - #endif -} -/* -static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length) -{ - return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length)); -} - -static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8 *pRxData, u32 Length) -{ - return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length)); -} -*/ - -#endif // end of "#ifdef CONFIG_GDMA_EN" - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h deleted file mode 100644 index a16f4439790..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Routines to access hardware - * - * Copyright (c) 2013 Realtek Semiconductor Corp. - * - * This module is a confidential and proprietary property of RealTek and - * possession or use of this module requires written permission of RealTek. - */ - -#ifndef _HAL_TIMER_H_ -#define _HAL_TIMER_H_ -#include "basic_types.h" -#include "hal_platform.h" -#include "rtl8195a_timer.h" - -#define GTIMER_CLK_HZ (32768) -#define GTIMER_TICK_US (1000000/GTIMER_CLK_HZ) - -enum _TIMER_MODE_ { - FREE_RUN_MODE = 0, - USER_DEFINED = 1 -}; -typedef uint32_t TIMER_MODE; -typedef uint32_t *PTIMER_MODE; - - -typedef struct _TIMER_ADAPTER_ { - - u32 TimerLoadValueUs; - u32 TimerIrqPriority; - TIMER_MODE TimerMode; - IRQ_HANDLE IrqHandle; - u8 TimerId; - u8 IrqDis; - -}TIMER_ADAPTER, *PTIMER_ADAPTER; - - -typedef struct _HAL_TIMER_OP_ { - u32 (*HalGetTimerId)(u32 *TimerId); - BOOL (*HalTimerInit)(VOID *Data); - u32 (*HalTimerReadCount)(u32 TimerId); - VOID (*HalTimerIrqClear)(u32 TimerId); - VOID (*HalTimerDis)(u32 TimerId); - VOID (*HalTimerEn)(u32 TimerId); - VOID (*HalTimerDumpReg)(u32 TimerId); -}HAL_TIMER_OP, *PHAL_TIMER_OP; - -typedef struct _HAL_TIMER_OP_EXT_ { - PHAL_TIMER_OP phal_timer_op_rom; - VOID (*HalTimerIrqEn)(u32 TimerId); - VOID (*HalTimerReLoad)(u32 TimerId, u32 LoadUs); - VOID (*HalTimerSync)(u32 TimerId); -}HAL_TIMER_OP_EXT, *PHAL_TIMER_OP_EXT; - -#ifdef CONFIG_TIMER_MODULE -// This variable declared in ROM code -extern HAL_TIMER_OP HalTimerOp; -extern HAL_TIMER_OP_EXT HalTimerOpExt; -#endif - -VOID HalTimerOpInit_Patch( - IN VOID *Data -); - - -//====================================================== -// ROM Function prototype -_LONG_CALL_ VOID HalTimerOpInitV02(IN VOID *Data); - -#ifndef CONFIG_RELEASE_BUILD_LIBRARIES -#define HalTimerOpInit HalTimerOpInit_Patch -#endif - -#ifdef CONFIG_RELEASE_BUILD_LIBRARIES -void HalTimerOpInit( - void *Data -); - -HAL_Status -HalTimerInit( - void *Data -); - -void -HalTimerEnable( - uint32_t TimerId -); - -void -HalTimerDisable( - uint32_t TimerId -); - -void -HalTimerReLoad( - uint32_t TimerId, - uint32_t LoadUs -); - -void -HalTimerDeInit( - void *Data -); - -#endif // #ifdef CONFIG_RELEASE_BUILD_LIBRARIES -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_uart.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_uart.h deleted file mode 100644 index b9598f10276..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_uart.h +++ /dev/null @@ -1,264 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_UART_H_ -#define _HAL_UART_H_ - -#include "rtl8195a_uart.h" - -/** - * RUART Configurations - */ -#define UART_WAIT_FOREVER 0xffffffff - -#define UART_DMA_MBLK_NUM 16 // maximum block number for each DMA transfer, it must <= 16 -#define UART_DMA_BLOCK_SIZE 4092 // the block size of multiple block DMA, it cann0t over 4095 - -typedef struct _HAL_UART_DMA_MULTIBLK_ { - volatile GDMA_CH_LLI_ELE GdmaChLli[UART_DMA_MBLK_NUM]; - struct GDMA_CH_LLI Lli[UART_DMA_MBLK_NUM]; - struct BLOCK_SIZE_LIST BlockSizeList[UART_DMA_MBLK_NUM]; -}UART_DMA_MULTIBLK, *PUART_DMA_MULTIBLK; - -typedef struct _UART_DMA_CONFIG_ { - u8 TxDmaEnable; - u8 RxDmaEnable; - u8 TxDmaBurstSize; - u8 RxDmaBurstSize; - VOID *pHalGdmaOp; - VOID *pTxHalGdmaAdapter; - VOID *pRxHalGdmaAdapter; - IRQ_HANDLE TxGdmaIrqHandle; - IRQ_HANDLE RxGdmaIrqHandle; -#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES)) - UART_DMA_MULTIBLK *pTxDmaBlkList; // point to multi-block list - UART_DMA_MULTIBLK *pRxDmaBlkList; // point to multi-block list - u8 TxDmaMBChnl; // is using DMA multiple block channel - u8 RxDmaMBChnl; // is using DMA multiple block channel -#endif -}UART_DMA_CONFIG, *PUART_DMA_CONFIG; - -typedef struct _HAL_RUART_ADAPTER_ { - u32 BaudRate; - u32 FlowControl; - u32 FifoControl; - u32 Interrupts; - u32 TxCount; // how many byte to TX - u32 RxCount; // how many bytes to RX - u8 *pTxBuf; - u8 *pRxBuf; - HAL_UART_State State; // UART state - u8 Status; // Transfer Status - u8 Locked; // is UART locked for operation - u8 UartIndex; - u8 WordLen; // word length select: 0 -> 7 bits, 1 -> 8 bits - u8 StopBit; // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit - u8 Parity; // parity check enable - u8 ParityType; // parity check type - u8 StickParity; - u8 ModemStatus; // the modem status - u8 DmaEnable; - u8 TestCaseNumber; - u8 PinmuxSelect; - BOOL PullMode; - IRQ_HANDLE IrqHandle; - PUART_DMA_CONFIG DmaConfig; - VOID (*ModemStatusInd)(VOID *pAdapter); // modem status indication interrupt handler - VOID (*TxTDCallback)(VOID *pAdapter); // User Tx Done callback function - VOID (*RxDRCallback)(VOID *pAdapter); // User Rx Data ready callback function - VOID (*TxCompCallback)(VOID *para); // User Tx complete callback function - VOID (*RxCompCallback)(VOID *para); // User Rx complete callback function - VOID *TxTDCbPara; // the pointer agrument for TxTDCallback - VOID *RxDRCbPara; // the pointer agrument for RxDRCallback - VOID *TxCompCbPara; // the pointer argument for TxCompCbPara - VOID *RxCompCbPara; // the pointer argument for RxCompCallback - VOID (*EnterCritical)(void); - VOID (*ExitCritical)(void); - -#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES)) - //1 New member only can be added below: members above must be fixed for ROM code - u32 *pDefaultBaudRateTbl; // point to the table of pre-defined baud rate - u8 *pDefaultOvsrRTbl; // point to the table of OVSR for pre-defined baud rate - u16 *pDefaultDivTbl; // point to the table of DIV for pre-defined baud rate - u8 *pDefOvsrAdjBitTbl_10; // point to the table of OVSR-Adj bits for 10 bits - u8 *pDefOvsrAdjBitTbl_9; // point to the table of OVSR-Adj bits for 9 bits - u8 *pDefOvsrAdjBitTbl_8; // point to the table of OVSR-Adj bits for 8 bits - u16 *pDefOvsrAdjTbl_10; // point to the table of OVSR-Adj for pre-defined baud rate - u16 *pDefOvsrAdjTbl_9; // point to the table of OVSR-Adj for pre-defined baud rate - u16 *pDefOvsrAdjTbl_8; // point to the table of OVSR-Adj for pre-defined baud rate - PUART_DMA_MULTIBLK pTxDMAMBlk; // point to the Link List Table of the DMA Multiple Block - PUART_DMA_MULTIBLK pRxDMAMBlk; // point to the Link List Table of the DMA Multiple Block - u32 BaudRateUsing; // Current using Baud-Rate - u8 WordLenUsing; // Current using Word Length - u8 ParityUsing; // Current using Parity check - u8 RTSCtrl; // Software RTS Control - -#if 0//CONFIG_CHIP_E_CUT - u8 TxState; - u8 RxState; - u32 TxInitSize; // how many byte to TX at atart - u32 RxInitSize; // how many bytes to RX at start - - VOID (*RuartEnterCritical)(VOID *para); // enter critical: disable UART interrupt - VOID (*RuartExitCritical)(VOID *para); // exit critical: re-enable UART interrupt - VOID (*TaskYield)(VOID *para); // User Task Yield: do a context switch while waitting - VOID *TaskYieldPara; // the agrument (pointer) for TaskYield -#endif // #if CONFIG_CHIP_E_CUT -#endif -}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER; - -typedef struct _HAL_RUART_OP_ { - VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx); // Load UART adapter default setting - VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load TX GDMA default setting - VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load RX GDMA default setting - HAL_Status (*HalRuartResetRxFifo)(VOID *Data); - HAL_Status (*HalRuartInit)(VOID *Data); - VOID (*HalRuartDeInit)(VOID *Data); - HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData); - u32 (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout); - HAL_Status (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length); - HAL_Status (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length); - HAL_Status (*HalRuartStopSend)(VOID *Data); - HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte); - u32 (*HalRuartRecv)(VOID *Data, u8 *pRxData, u32 Length, u32 Timeout); - HAL_Status (*HalRuartIntRecv)(VOID *Data, u8 *pRxData, u32 Length); - HAL_Status (*HalRuartDmaRecv)(VOID *Data, u8 *pRxData, u32 Length); - HAL_Status (*HalRuartStopRecv)(VOID *Data); - u8 (*HalRuartGetIMR)(VOID *Data); - VOID (*HalRuartSetIMR)(VOID *Data); - u32 (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel); - VOID (*HalRuartDmaInit)(VOID *Data); - VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl); - VOID (*HalRuartRegIrq)(VOID *Data); - VOID (*HalRuartIntEnable)(VOID *Data); - VOID (*HalRuartIntDisable)(VOID *Data); -}HAL_RUART_OP, *PHAL_RUART_OP; - -typedef struct _RUART_DATA_ { - PHAL_RUART_ADAPTER pHalRuartAdapter; - BOOL PullMode; - u8 BinaryData; - u8 SendBuffer; - u8 RecvBuffer; -}RUART_DATA, *PRUART_DATA; - -typedef struct _RUART_ADAPTER_ { - PHAL_RUART_OP pHalRuartOp; - PHAL_RUART_ADAPTER pHalRuartAdapter; - PUART_DMA_CONFIG pHalRuartDmaCfg; -}RUART_ADAPTER, *PRUART_ADAPTER; - -extern VOID -HalRuartOpInit( - IN VOID *Data -); - -extern HAL_Status -HalRuartTxGdmaInit( - PHAL_RUART_ADAPTER pHalRuartAdapter, - PUART_DMA_CONFIG pUartGdmaConfig, - u8 IsMultiBlk -); - -extern VOID -HalRuartTxGdmaDeInit( - PUART_DMA_CONFIG pUartGdmaConfig -); - -extern HAL_Status -HalRuartRxGdmaInit( - PHAL_RUART_ADAPTER pHalRuartAdapter, - PUART_DMA_CONFIG pUartGdmaConfig, - u8 IsMultiBlk -); - -extern VOID -HalRuartRxGdmaDeInit( - PUART_DMA_CONFIG pUartGdmaConfig -); - -extern HAL_Status -HalRuartResetTxFifo( - VOID *Data -); - -extern HAL_Status -HalRuartResetRxFifo( - IN VOID *Data -); - -HAL_Status -HalRuartResetTRxFifo( - IN VOID *Data -); - -extern HAL_Status -HalRuartSetBaudRate( - IN VOID *Data -); - -extern HAL_Status -HalRuartInit( - IN VOID *Data -); - -extern VOID -HalRuartDeInit( - IN VOID *Data -); - -extern HAL_Status -HalRuartDisable( - IN VOID *Data -); - -extern HAL_Status -HalRuartEnable( - IN VOID *Data -); - -HAL_Status -HalRuartFlowCtrl( - IN VOID *Data -); - -VOID -HalRuartEnterCritical( - IN VOID *Data -); - -VOID -HalRuartExitCritical( - IN VOID *Data -); - -HAL_Status -HalRuartDmaSend( - IN VOID *Data, - IN u8 *pTxBuf, - IN u32 Length -); - -HAL_Status -HalRuartDmaRecv( - IN VOID *Data, - IN u8 *pRxBuf, - IN u32 Length -); - -extern const HAL_RUART_OP _HalRuartOp; -extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter); -extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter); - -#endif - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_util.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_util.h deleted file mode 100644 index 02281f67445..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_util.h +++ /dev/null @@ -1,256 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _HAL_UTIL_H_ -#define _HAL_UTIL_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Simple doubly linked list implementation. - * - * Some of the internal functions ("__xxx") are useful when - * manipulating whole lists rather than single entries, as - * sometimes we already know the next/prev entries and we can - * generate better code by using them directly rather than - * using the generic single-entry routines. - */ -struct LIST_HEADER { - struct LIST_HEADER *Next, *Prev; -}; - -typedef struct LIST_HEADER _LIST; - -//#define RTL_LIST_HEAD_INIT(name) { &(name), &(name) } - -#define RTL_INIT_LIST_HEAD(ptr) do { \ - (ptr)->Next = (ptr); (ptr)->Prev = (ptr); \ -} while (0) - - -/* - * Insert a new entry between two known consecutive entries. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ - static __inline__ VOID - __List_Add( - IN struct LIST_HEADER * New, - IN struct LIST_HEADER * Prev, - IN struct LIST_HEADER * Next -) -{ - Next->Prev = New; - New->Next = Next; - New->Prev = Prev; - Prev->Next = New; -} - -/* - * Delete a list entry by making the prev/next entries - * point to each other. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ - static __inline__ VOID - __List_Del( - IN struct LIST_HEADER * Prev, - IN struct LIST_HEADER * Next - ) -{ - Next->Prev = Prev; - Prev->Next = Next; -} - -/** - * ListDel - deletes entry from list. - * @entry: the element to delete from the list. - * Note: list_empty on entry does not return true after this, the entry is in an undefined state. - */ -static __inline__ VOID -ListDel( - IN struct LIST_HEADER *Entry -) -{ - __List_Del(Entry->Prev, Entry->Next); -} - -/** - * ListDelInit - deletes entry from list and reinitialize it. - * @entry: the element to delete from the list. - */ -static __inline__ VOID -ListDelInit( - IN struct LIST_HEADER *Entry -) -{ - __List_Del(Entry->Prev, Entry->Next); - RTL_INIT_LIST_HEAD(Entry); - -} - -/** - * ListEmpty - tests whether a list is empty - * @head: the list to test. - */ -static __inline__ u32 -ListEmpty( - IN struct LIST_HEADER *Head -) -{ - return Head->Next == Head; -} - -/** - * ListSplice - join two lists - * @list: the new list to add. - * @head: the place to add it in the first list. - */ -static __inline__ VOID -ListSplice( - IN struct LIST_HEADER *List, - IN struct LIST_HEADER *Head -) -{ - struct LIST_HEADER *First = List->Next; - - if (First != List) { - struct LIST_HEADER *Last = List->Prev; - struct LIST_HEADER *At = Head->Next; - - First->Prev = Head; - Head->Next = First; - - Last->Next = At; - At->Prev = Last; - } -} - -static __inline__ VOID -ListAdd( - IN struct LIST_HEADER *New, - IN struct LIST_HEADER *head -) -{ - __List_Add(New, head, head->Next); -} - - -static __inline__ VOID -ListAddTail( - IN struct LIST_HEADER *New, - IN struct LIST_HEADER *head -) -{ - __List_Add(New, head->Prev, head); -} - -static __inline VOID -RtlInitListhead( - IN _LIST *list -) -{ - RTL_INIT_LIST_HEAD(list); -} - - -/* -For the following list_xxx operations, -caller must guarantee the atomic context. -Otherwise, there will be racing condition. -*/ -static __inline u32 -RtlIsListEmpty( - IN _LIST *phead -) -{ - - if (ListEmpty(phead)) - return _TRUE; - else - return _FALSE; - -} - -static __inline VOID -RtlListInsertHead( - IN _LIST *plist, - IN _LIST *phead -) -{ - ListAdd(plist, phead); -} - -static __inline VOID -RtlListInsertTail( - IN _LIST *plist, - IN _LIST *phead -) -{ - ListAddTail(plist, phead); -} - - -static __inline _LIST -*RtlListGetNext( - IN _LIST *plist -) -{ - return plist->Next; -} - -static __inline VOID -RtlListDelete( - IN _LIST *plist -) -{ - ListDelInit(plist); -} - -#define RTL_LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) - -#ifndef CONTAINER_OF -#define CONTAINER_OF(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) -#endif -#if 0 -#define list_entry(ptr, type, member) \ - CONTAINER_OF(ptr, type, member) - -#define list_first_entry(ptr, type, member) \ - list_entry((ptr)->Next, type, member) - -#define list_next_entry(pos, member, type) \ - list_entry((pos)->member.Next, type, member) - -#define list_for_each_entry(pos, head, member, type) \ - for (pos = list_first_entry(head, type, member); \ - &pos->member != (head); \ - pos = list_next_entry(pos, member, type)) -#define list_for_each(pos, head) \ - for (pos = (head)->Next; pos != (head); pos = pos->Next) -#endif - -#ifndef BIT - #define BIT(x) ( 1 << (x)) -#endif - -#ifdef __cplusplus -} -#endif - -#endif //_HAL_UTIL_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_vector_table.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_vector_table.h deleted file mode 100644 index cd2d1149177..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_vector_table.h +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _HAL_VECTOR_TABLE_H_ -#define _HAL_VECTOR_TABLE_H_ - -extern _LONG_CALL_ROM_ VOID -VectorTableInitRtl8195A( - IN u32 StackP -); - -extern _LONG_CALL_ROM_ VOID -VectorTableInitForOSRtl8195A( - IN VOID *PortSVC, - IN VOID *PortPendSVH, - IN VOID *PortSysTick -); - -extern _LONG_CALL_ROM_ BOOL -VectorIrqRegisterRtl8195A( - IN PIRQ_HANDLE pIrqHandle -); - -extern _LONG_CALL_ROM_ BOOL -VectorIrqUnRegisterRtl8195A( - IN PIRQ_HANDLE pIrqHandle -); - -extern _LONG_CALL_ROM_ VOID -VectorIrqEnRtl8195A( - IN PIRQ_HANDLE pIrqHandle -); - -extern _LONG_CALL_ROM_ VOID -VectorIrqDisRtl8195A( - IN PIRQ_HANDLE pIrqHandle -); - -extern _LONG_CALL_ROM_ VOID -HalPeripheralIntrHandle(VOID); - -#endif //_HAL_VECTOR_TABLE_H_ - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h deleted file mode 100644 index 24eda206aa3..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h +++ /dev/null @@ -1,284 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _HAL_8195A_H_ -#define _HAL_8195A_H_ - -#include "platform_autoconf.h" -#include "basic_types.h" -#include "section_config.h" -#include "rtl8195a_sys_on.h" -#include "rtl8195a_peri_on.h" -#include "hal_platform.h" -#include "hal_pinmux.h" -#include "hal_api.h" -#include "hal_peri_on.h" -#include "hal_misc.h" -#include "hal_irqn.h" -#include "hal_vector_table.h" -#include "hal_diag.h" -#include "hal_spi_flash.h" -#include "rtl8195a_spi_flash.h" -#include "hal_timer.h" -#include "hal_util.h" -#include "hal_efuse.h" -#include "hal_soc_ps_monitor.h" -#include "diag.h" -#include "system_8195a.h" - -// from RDC team -#ifdef CONFIG_MBED_ENABLED -// Add for Mbed -OS -#include -#include -#include - -#include "rtl8195a_compiler.h" -#include "rtl8195a_platform.h" -#include "rtl8195a_crypto.h" - -#define REG32(reg) (*(volatile uint32_t *)(reg)) -#define REG16(reg) (*(volatile uint16_t *)(reg)) -#define REG08(reg) (*(volatile uint8_t *)(reg)) - -#ifndef BIT -#define BIT(x) (1 << (x)) -#endif -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) -#define ABS(x) ((x > 0) ? x : -x) -#define MAX(x,y) ((x) < (y) ? (y) : (x)) -#ifndef MIN -#define MIN(x,y) ((x) > (y) ? (y) : (x)) -#endif - -#define __RTK_READ32(B,A) (REG32((B) + (A))) -#define __RTK_READ16(B,A) (REG16((B) + (A))) -#define __RTK_READ08(B,A) (REG08((B) + (A))) -#define __RTK_WRITE32(B,A,V) (REG32((B) + (A)) = (V)) -#define __RTK_WRITE16(B,A,V) (REG32((B) + (A)) = (V)) -#define __RTK_WRITE08(B,A,V) (REG32((B) + (A)) = (V)) - -#define __RTK_SETBIT(A,V) (REG32(A) |= V) -#define __RTK_CLRBIT(A,V) (REG32(A) &= ~V) -#define __RTK_SETMSK(A,M,V) (REG32(A) = ((REG32(A) & (~M)) | V)) - -#define PERI_BASE 0x40000000 - -#define __BUILD_MACRO(name,ctrl) \ -static inline uint32_t \ -__##name##_READ32(uint32_t addr) \ -{ \ - return __RTK_READ32(ctrl##_BASE,addr); \ -} \ -static inline uint16_t \ -__##name##_READ16(uint32_t addr) \ -{ \ - return __RTK_READ16(ctrl##_BASE,addr); \ -} \ -static inline uint8_t \ -__##name##_READ08(uint32_t addr) \ -{ \ - return __RTK_READ08(ctrl##_BASE,addr); \ -} \ -static inline void \ -__##name##_WRITE32(uint32_t addr, uint32_t val) \ -{ \ - __RTK_WRITE32(ctrl##_BASE,addr,val); \ -} \ -static inline void \ -__##name##_WRITE16(uint32_t addr, uint16_t val) \ -{ \ - __RTK_WRITE16(ctrl##_BASE,addr,val); \ -} \ -static inline void \ -__##name##_WRITE08(uint32_t addr, uint8_t val) \ -{ \ - __RTK_WRITE08(ctrl##_BASE,addr,val); \ -} \ -static inline void \ -__##name##_SETBIT(uint32_t addr, uint32_t val) \ -{ \ - __RTK_SETBIT(ctrl##_BASE+addr,val); \ -} \ -static inline void \ -__##name##_CLRBIT(uint32_t addr, uint32_t val) \ -{ \ - __RTK_CLRBIT(ctrl##_BASE+addr,val); \ -} \ -static inline void \ -__##name##_SETMSK(uint32_t addr, uint32_t msk, uint32_t val) \ -{ \ - __RTK_SETMSK(ctrl##_BASE+addr,msk,val); \ -} \ - -//__BUILD_MACRO(RTK_CTRL, CTRL) -//__BUILD_MACRO(RTK_PERI, PERI) -//__BUILD_MACRO(RTK_VENDOR, VENDOR) -//__BUILD_MACRO(RTK_SDRC, SDRC) - -__BUILD_MACRO(RTK_CTRL, SYSTEM_CTRL) -__BUILD_MACRO(RTK_PERI, PERI) -__BUILD_MACRO(RTK_SDRC, SDR_CTRL) -__BUILD_MACRO(RTK_VENDOR, VENDOR_REG) - - -#define __BUILD_FCTRL_MACRO(name,ctrl) \ -static inline void \ -__##name##_Enable(void) \ -{ \ - __RTK_PERI_SETBIT(ctrl, BIT_FCTRL_##name); \ -} \ -static inline void \ -__##name##_Disable(void) \ -{ \ - __RTK_READ32(name##_BASE, 0); \ - __RTK_PERI_CLRBIT(ctrl, BIT_FCTRL_##name); \ -} - - - -#include "rtl8195a_trap.h" -#include "rtl8195a_clk.h" -#include "rtl8195a_misc.h" - -#endif - -/* ---------------------------------------------------------------------------- - -- Cortex M3 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration - * @{ - */ - -#define __CM3_REV 0x0200 /**< Core revision r0p0 */ -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm3.h" - -#ifdef CONFIG_TIMER_EN -#include "hal_timer.h" -#endif - -#ifdef CONFIG_GDMA_EN -#include "hal_gdma.h" -#include "rtl8195a_gdma.h" -#endif - -#ifdef CONFIG_GPIO_EN -#include "hal_gpio.h" -#include "rtl8195a_gpio.h" -#endif - -#ifdef CONFIG_SPI_COM_EN -#include "hal_ssi.h" -#include "rtl8195a_ssi.h" -#endif - -#ifdef CONFIG_UART_EN -#include "hal_uart.h" -#include "rtl8195a_uart.h" -#endif - -#ifdef CONFIG_I2C_EN -#include "hal_i2c.h" -#include "rtl8195a_i2c.h" -#endif - -#ifdef CONFIG_PCM_EN -#include "hal_pcm.h" -#include "rtl8195a_pcm.h" -#endif - -#ifdef CONFIG_PWM_EN -#include "hal_pwm.h" -#include "rtl8195a_pwm.h" -#endif - -#ifdef CONFIG_I2S_EN -#include "hal_i2s.h" -#include "rtl8195a_i2s.h" -#endif - -#ifdef CONFIG_DAC_EN -#include "hal_dac.h" -#include "rtl8195a_dac.h" -#endif - -#ifdef CONFIG_ADC_EN -#include "hal_adc.h" -#include "rtl8195a_adc.h" -#endif - -#ifdef CONFIG_SDR_EN -#endif - -#ifdef CONFIG_SPIC_EN -#endif - -#ifdef CONFIG_SDIO_DEVICE_EN -#include "hal_sdio.h" -#endif - -#ifdef CONFIG_NFC_EN -//#include "hal_nfc.h" -//#include "rtl8195a_nfc.h" -#endif - -#ifdef CONFIG_WDG -#include "rtl8195a_wdt.h" -#endif - -#ifdef CONFIG_USB_EN -//#include "hal_usb.h" -//#include "rtl8195a_usb.h" -#endif - -#include "hal_log_uart.h" - -#ifdef CONFIG_MII_EN -//#include "hal_mii.h" -//#include "rtl8195a_mii.h" -#endif - -// firmware information, located at the header of Image2 -#define FW_VERSION (0x0100) -#define FW_SUBVERSION (0x0001) -#define FW_CHIP_ID (0x8195) -#define FW_CHIP_VER (0x01) -#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO -#define FW_INFO_RSV1 (0x00) // the firmware information reserved -#define FW_INFO_RSV2 (0x00) // the firmware information reserved -#define FW_INFO_RSV3 (0x00) // the firmware information reserved -#define FW_INFO_RSV4 (0x00) // the firmware information reserved - -#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1 -#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data -// Flash Map for Calibration data -#define FLASH_CAL_DATA_BASE 0xA000 -#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset) -#define FLASH_CAL_DATA_SIZE 0x1000 -#define FLASH_SECTOR_SIZE 0x1000 -// SPIC Calibration Data -#define FLASH_SPIC_PARA_OFFSET 0x80 -#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET) -// SDRC Calibration Data -#define FLASH_SDRC_PARA_OFFSET 0x180 -#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET) -// ADC Calibration Data -#define FLASH_ADC_PARA_OFFSET 0x200 -#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET) - -#endif //_HAL_8195A_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h deleted file mode 100644 index 785dd666597..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h +++ /dev/null @@ -1,354 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _RTL8195A_ADC_H_ -#define _RTL8195A_ADC_H_ - - -//================ Register Bit Field ========================== -//2 REG_ADC_FIFO_READ - -#define BIT_SHIFT_ADC_FIFO_RO 0 -#define BIT_MASK_ADC_FIFO_RO 0xffffffffL -#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO) -#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO) -#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO) - - -//2 REG_ADC_CONTROL - -#define BIT_SHIFT_ADC_DBG_SEL 24 -#define BIT_MASK_ADC_DBG_SEL 0x7 -#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL) -#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL) -#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL) - - -#define BIT_SHIFT_ADC_THRESHOLD 16 -#define BIT_MASK_ADC_THRESHOLD 0x3f -#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD) -#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD) -#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD) - - -#define BIT_SHIFT_ADC_BURST_SIZE 8 -#define BIT_MASK_ADC_BURST_SIZE 0x1f -#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE) -#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE) -#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE) - -#define BIT_ADC_ENDIAN BIT(3) -#define BIT_SHIFT_ADC_ENDIAN 3 -#define BIT_MASK_ADC_ENDIAN 0x1 -#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN) - -#define BIT_ADC_OVERWRITE BIT(2) -#define BIT_SHIFT_ADC_OVERWRITE 2 -#define BIT_MASK_ADC_OVERWRITE 0x1 -#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE) - -#define BIT_ADC_ONESHOT BIT(1) -#define BIT_SHIFT_ADC_ONESHOT 1 -#define BIT_MASK_ADC_ONESHOT 0x1 -#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT) - -#define BIT_ADC_COMP_ONLY BIT(0) -#define BIT_SHIFT_ADC_COMP_ONLY 0 -#define BIT_MASK_ADC_COMP_ONLY 0x1 -#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY) - - -//2 REG_ADC_INTR_EN -#define BIT_ADC_AWAKE_CPU_EN BIT(7) -#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7 -#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1 -#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN) - -#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6) -#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6 -#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1 -#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN) - -#define BIT_ADC_FIFO_RD_REQ_EN BIT(5) -#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5 -#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1 -#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN) - -#define BIT_ADC_FIFO_FULL_EN BIT(4) -#define BIT_SHIFT_ADC_FIFO_FULL_EN 4 -#define BIT_MASK_ADC_FIFO_FULL_EN 0x1 -#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN) - -#define BIT_ADC_COMP_3_EN BIT(3) -#define BIT_SHIFT_ADC_COMP_3_EN 3 -#define BIT_MASK_ADC_COMP_3_EN 0x1 -#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN) - -#define BIT_ADC_COMP_2_EN BIT(2) -#define BIT_SHIFT_ADC_COMP_2_EN 2 -#define BIT_MASK_ADC_COMP_2_EN 0x1 -#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN) - -#define BIT_ADC_COMP_1_EN BIT(1) -#define BIT_SHIFT_ADC_COMP_1_EN 1 -#define BIT_MASK_ADC_COMP_1_EN 0x1 -#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN) - -#define BIT_ADC_COMP_0_EN BIT(0) -#define BIT_SHIFT_ADC_COMP_0_EN 0 -#define BIT_MASK_ADC_COMP_0_EN 0x1 -#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN) - - -//2 REG_ADC_INTR_STS -#define BIT_ADC_FIFO_THRESHOLD BIT(7) -#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7 -#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1 -#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD) - -#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6) -#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6 -#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1 -#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST) - -#define BIT_ADC_FIFO_RD_REQ_ST BIT(5) -#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5 -#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1 -#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST) - -#define BIT_ADC_FIFO_FULL_ST BIT(4) -#define BIT_SHIFT_ADC_FIFO_FULL_ST 4 -#define BIT_MASK_ADC_FIFO_FULL_ST 0x1 -#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST) - -#define BIT_ADC_COMP_3_ST BIT(3) -#define BIT_SHIFT_ADC_COMP_3_ST 3 -#define BIT_MASK_ADC_COMP_3_ST 0x1 -#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST) - -#define BIT_ADC_COMP_2_ST BIT(2) -#define BIT_SHIFT_ADC_COMP_2_ST 2 -#define BIT_MASK_ADC_COMP_2_ST 0x1 -#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST) - -#define BIT_ADC_COMP_1_ST BIT(1) -#define BIT_SHIFT_ADC_COMP_1_ST 1 -#define BIT_MASK_ADC_COMP_1_ST 0x1 -#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST) - -#define BIT_ADC_COMP_0_ST BIT(0) -#define BIT_SHIFT_ADC_COMP_0_ST 0 -#define BIT_MASK_ADC_COMP_0_ST 0x1 -#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST) - - -//2 REG_ADC_COMP_VALUE_L - -#define BIT_SHIFT_ADC_COMP_TH_1 16 -#define BIT_MASK_ADC_COMP_TH_1 0xffff -#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1) -#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1) -#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1) - - -#define BIT_SHIFT_ADC_COMP_TH_0 0 -#define BIT_MASK_ADC_COMP_TH_0 0xffff -#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0) -#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0) -#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0) - - -//2 REG_ADC_COMP_VALUE_H - -#define BIT_SHIFT_ADC_COMP_TH_3 16 -#define BIT_MASK_ADC_COMP_TH_3 0xffff -#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3) -#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3) -#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3) - - -#define BIT_SHIFT_ADC_COMP_TH_2 0 -#define BIT_MASK_ADC_COMP_TH_2 0xffff -#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2) -#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2) -#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2) - - -//2 REG_ADC_COMP_SET - -#define BIT_SHIFT_ADC_GREATER_THAN 0 -#define BIT_MASK_ADC_GREATER_THAN 0xf -#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN) -#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN) -#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN) - - -//2 REG_ADC_POWER - -#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16 -#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff -#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR) -#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR) -#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR) - -#define BIT_ADC_FIFO_ON_ST BIT(11) -#define BIT_SHIFT_ADC_FIFO_ON_ST 11 -#define BIT_MASK_ADC_FIFO_ON_ST 0x1 -#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST) - -#define BIT_ADC_ISO_ON_ST BIT(10) -#define BIT_SHIFT_ADC_ISO_ON_ST 10 -#define BIT_MASK_ADC_ISO_ON_ST 0x1 -#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST) - -#define BIT_ADC_PWR33_ON_ST BIT(9) -#define BIT_SHIFT_ADC_PWR33_ON_ST 9 -#define BIT_MASK_ADC_PWR33_ON_ST 0x1 -#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST) - -#define BIT_ADC_PWR12_ON_ST BIT(8) -#define BIT_SHIFT_ADC_PWR12_ON_ST 8 -#define BIT_MASK_ADC_PWR12_ON_ST 0x1 -#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST) - -#define BIT_ADC_ISO_MANUAL BIT(3) -#define BIT_SHIFT_ADC_ISO_MANUAL 3 -#define BIT_MASK_ADC_ISO_MANUAL 0x1 -#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL) - -#define BIT_ADC_PWR33_MANUAL BIT(2) -#define BIT_SHIFT_ADC_PWR33_MANUAL 2 -#define BIT_MASK_ADC_PWR33_MANUAL 0x1 -#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL) - -#define BIT_ADC_PWR12_MANUAL BIT(1) -#define BIT_SHIFT_ADC_PWR12_MANUAL 1 -#define BIT_MASK_ADC_PWR12_MANUAL 0x1 -#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL) - -#define BIT_ADC_PWR_AUTO BIT(0) -#define BIT_SHIFT_ADC_PWR_AUTO 0 -#define BIT_MASK_ADC_PWR_AUTO 0x1 -#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO) - - -//2 REG_ADC_ANAPAR_AD0 - -#define BIT_SHIFT_ADC_ANAPAR_AD0 2 -#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff -#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0) -#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0) -#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0) - -#define BIT_ADC_AUDIO_EN BIT(1) -#define BIT_SHIFT_ADC_AUDIO_EN 1 -#define BIT_MASK_ADC_AUDIO_EN 0x1 -#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN) - -#define BIT_ADC_EN_MANUAL BIT(0) -#define BIT_SHIFT_ADC_EN_MANUAL 0 -#define BIT_MASK_ADC_EN_MANUAL 0x1 -#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL) - - -//2 REG_ADC_ANAPAR_AD1 - -#define BIT_SHIFT_ADC_ANAPAR_AD1 0 -#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL -#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1) -#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1) -#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1) - - -//2 REG_ADC_ANAPAR_AD2 - -#define BIT_SHIFT_ADC_ANAPAR_AD2 0 -#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL -#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2) -#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2) -#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2) - - -//2 REG_ADC_ANAPAR_AD3 - -#define BIT_SHIFT_ADC_ANAPAR_AD3 0 -#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL -#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3) -#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3) -#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3) - - -//2 REG_ADC_ANAPAR_AD4 - -#define BIT_SHIFT_ADC_ANAPAR_AD4 0 -#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL -#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4) -#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4) -#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4) - - -//2 REG_ADC_ANAPAR_AD5 - -#define BIT_SHIFT_ADC_ANAPAR_AD5 0 -#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL -#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5) -#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5) -#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5) - - -//2 REG_ADC_CALI_DATA - -#define BIT_SHIFT_ADC_CALI_DATA_6 16 -#define BIT_MASK_ADC_CALI_DATA_6 0xffff -#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6) -#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6) -#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6) - - -#define BIT_SHIFT_ADC_CALI_DATA_0 0 -#define BIT_MASK_ADC_CALI_DATA_0 0xffff -#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0) -#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0) -#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0) - -//================ Register Reg Field ========================= -#define REG_ADC_FIFO_READ 0x0000 -#define REG_ADC_CONTROL 0x0004 -#define REG_ADC_INTR_EN 0x0008 -#define REG_ADC_INTR_STS 0x000C -#define REG_ADC_COMP_VALUE_L 0x0010 -#define REG_ADC_COMP_VALUE_H 0x0014 -#define REG_ADC_COMP_SET 0x0018 -#define REG_ADC_POWER 0x001C -#define REG_ADC_ANAPAR_AD0 0x0020 -#define REG_ADC_ANAPAR_AD1 0x0024 -#define REG_ADC_ANAPAR_AD2 0x0028 -#define REG_ADC_ANAPAR_AD3 0x002C -#define REG_ADC_ANAPAR_AD4 0x0030 -#define REG_ADC_ANAPAR_AD5 0x0034 -#define REG_ADC_CALI_DATA 0x0038 - -//================ ADC HAL related enumeration ================== - -//================ ADC Function Prototypes ===================== -#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value) -#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr) - -RTK_STATUS HalADCInit8195a(IN VOID *Data); -RTK_STATUS HalADCDeInit8195a(IN VOID *Data); -RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data); -RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data); -u32 HalADCReceiveRtl8195a(IN VOID *Data); -u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg); - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_dac.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_dac.h deleted file mode 100644 index a4f689b7672..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_dac.h +++ /dev/null @@ -1,306 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _RTL8195A_DAC_H_ -#define _RTL8195A_DAC_H_ - -//================ Register Bit Field ========================== -//2 REG_DAC0_FIFO_WR - -#define BIT_SHIFT_DAC0_FIFO_WO 0 -#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL -#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO) -#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO) -#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO) - - -//2 REG_DAC_CTRL - -#define BIT_SHIFT_DAC_DELTA_SIGMA 25 -#define BIT_MASK_DAC_DELTA_SIGMA 0x7 -#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA) -#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA) -#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA) - -#define BIT_DAC_BYPASS_DSC BIT(24) -#define BIT_SHIFT_DAC_BYPASS_DSC 24 -#define BIT_MASK_DAC_BYPASS_DSC 0x1 -#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC) - - -#define BIT_SHIFT_DAC_DSC_DBG_SEL 19 -#define BIT_MASK_DAC_DSC_DBG_SEL 0x3 -#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL) -#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL) -#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL) - - -#define BIT_SHIFT_DAC_DBG_SEL 16 -#define BIT_MASK_DAC_DBG_SEL 0x7 -#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL) -#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL) -#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL) - - -#define BIT_SHIFT_DAC_BURST_SIZE 8 -#define BIT_MASK_DAC_BURST_SIZE 0xf -#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE) -#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE) -#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE) - -#define BIT_DAC_FILTER_SETTLE BIT(4) -#define BIT_SHIFT_DAC_FILTER_SETTLE 4 -#define BIT_MASK_DAC_FILTER_SETTLE 0x1 -#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE) - -#define BIT_DAC_OV_OPTION BIT(3) -#define BIT_SHIFT_DAC_OV_OPTION 3 -#define BIT_MASK_DAC_OV_OPTION 0x1 -#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION) - -#define BIT_DAC_ENDIAN BIT(2) -#define BIT_SHIFT_DAC_ENDIAN 2 -#define BIT_MASK_DAC_ENDIAN 0x1 -#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN) - -#define BIT_DAC_SPEED BIT(1) -#define BIT_SHIFT_DAC_SPEED 1 -#define BIT_MASK_DAC_SPEED 0x1 -#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED) - -#define BIT_DAC_FIFO_EN BIT(0) -#define BIT_SHIFT_DAC_FIFO_EN 0 -#define BIT_MASK_DAC_FIFO_EN 0x1 -#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN) - - -//2 REG_DAC_INTR_CTRL -#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6) -#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6 -#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1 -#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN) - -#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5) -#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5 -#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1 -#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN) - -#define BIT_DAC__WRITE_ERROR_EN BIT(4) -#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4 -#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1 -#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN) - -#define BIT_DAC_FIFO_STOP_EN BIT(3) -#define BIT_SHIFT_DAC_FIFO_STOP_EN 3 -#define BIT_MASK_DAC_FIFO_STOP_EN 0x1 -#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN) - -#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2) -#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2 -#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1 -#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN) - -#define BIT_DAC_FIFO_WR_REQ_EN BIT(1) -#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1 -#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1 -#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN) - -#define BIT_DAC_FIFO_FULL_EN BIT(0) -#define BIT_SHIFT_DAC_FIFO_FULL_EN 0 -#define BIT_MASK_DAC_FIFO_FULL_EN 0x1 -#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN) - - -//2 REG_DAC_INTR_STS -#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6) -#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6 -#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1 -#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST) - -#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5) -#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5 -#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1 -#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST) - -#define BIT_DAC__WRITE_ERROR_ST BIT(4) -#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4 -#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1 -#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST) - -#define BIT_DAC_FIFO_STOP_ST BIT(3) -#define BIT_SHIFT_DAC_FIFO_STOP_ST 3 -#define BIT_MASK_DAC_FIFO_STOP_ST 0x1 -#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST) - -#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2) -#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2 -#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1 -#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST) - -#define BIT_DAC_FIFO_WR_REQ_ST BIT(1) -#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1 -#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1 -#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST) - -#define BIT_DAC_FIFO_FULL_ST BIT(0) -#define BIT_SHIFT_DAC_FIFO_FULL_ST 0 -#define BIT_MASK_DAC_FIFO_FULL_ST 0x1 -#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST) - - -//2 REG_DAC_PWR_CTRL - -#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16 -#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff -#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR) -#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR) -#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR) - -#define BIT_ST_DAC_FIFO_ON BIT(11) -#define BIT_SHIFT_ST_DAC_FIFO_ON 11 -#define BIT_MASK_ST_DAC_FIFO_ON 0x1 -#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON) - -#define BIT_ST_DAC_ISO_ON BIT(10) -#define BIT_SHIFT_ST_DAC_ISO_ON 10 -#define BIT_MASK_ST_DAC_ISO_ON 0x1 -#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON) - -#define BIT_ST_DAC_PWR33_ON BIT(9) -#define BIT_SHIFT_ST_DAC_PWR33_ON 9 -#define BIT_MASK_ST_DAC_PWR33_ON 0x1 -#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON) - -#define BIT_ST_DAC_PWR12_ON BIT(8) -#define BIT_SHIFT_ST_DAC_PWR12_ON 8 -#define BIT_MASK_ST_DAC_PWR12_ON 0x1 -#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON) - -#define BIT_DAC_ISO_MANU BIT(3) -#define BIT_SHIFT_DAC_ISO_MANU 3 -#define BIT_MASK_DAC_ISO_MANU 0x1 -#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU) - -#define BIT_DAC_PWR33_MANU BIT(2) -#define BIT_SHIFT_DAC_PWR33_MANU 2 -#define BIT_MASK_DAC_PWR33_MANU 0x1 -#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU) - -#define BIT_DAC_PWR12_MANU BIT(1) -#define BIT_SHIFT_DAC_PWR12_MANU 1 -#define BIT_MASK_DAC_PWR12_MANU 0x1 -#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU) - -#define BIT_DAC_PWR_AUTO BIT(0) -#define BIT_SHIFT_DAC_PWR_AUTO 0 -#define BIT_MASK_DAC_PWR_AUTO 0x1 -#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO) - - -//2 REG_DAC_ANAPAR_DA0 - -#define BIT_SHIFT_PWR_ALL_CNTR 12 -#define BIT_MASK_PWR_ALL_CNTR 0xfffff -#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR) -#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR) -#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR) - - -#define BIT_SHIFT_PWR_FUP_CNTR 0 -#define BIT_MASK_PWR_FUP_CNTR 0xfff -#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR) -#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR) -#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR) - - -//2 REG_DAC_ANAPAR_DA1 -#define BIT_FUP_EN BIT(31) -#define BIT_SHIFT_FUP_EN 31 -#define BIT_MASK_FUP_EN 0x1 -#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN) - - -#define BIT_SHIFT_ANAPAR_DA 8 -#define BIT_MASK_ANAPAR_DA 0x7fffff -#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA) -#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA) -#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA) - -#define BIT_D_POW_DACVREF BIT(7) -#define BIT_SHIFT_D_POW_DACVREF 7 -#define BIT_MASK_D_POW_DACVREF 0x1 -#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF) - -#define BIT_D_POW_VREF2 BIT(6) -#define BIT_SHIFT_D_POW_VREF2 6 -#define BIT_MASK_D_POW_VREF2 0x1 -#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2) - -#define BIT_D_POW_MBIAS BIT(5) -#define BIT_SHIFT_D_POW_MBIAS 5 -#define BIT_MASK_D_POW_MBIAS 0x1 -#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS) - -#define BIT_D_POW_DIV4 BIT(4) -#define BIT_SHIFT_D_POW_DIV4 4 -#define BIT_MASK_D_POW_DIV4 0x1 -#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4) - -#define BIT_D_POW_DF1SE_R BIT(3) -#define BIT_SHIFT_D_POW_DF1SE_R 3 -#define BIT_MASK_D_POW_DF1SE_R 0x1 -#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R) - -#define BIT_D_POW_DF2SE_L BIT(2) -#define BIT_SHIFT_D_POW_DF2SE_L 2 -#define BIT_MASK_D_POW_DF2SE_L 0x1 -#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L) - -#define BIT_D_POW_DAC_R BIT(1) -#define BIT_SHIFT_D_POW_DAC_R 1 -#define BIT_MASK_D_POW_DAC_R 0x1 -#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R) - -#define BIT_D_POW_DAC_L BIT(0) -#define BIT_SHIFT_D_POW_DAC_L 0 -#define BIT_MASK_D_POW_DAC_L 0x1 -#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L) - - -//================ Register Reg Field ========================= -#define REG_DAC0_FIFO_WR 0x0000 -#define REG_DAC_CTRL 0x0004 -#define REG_DAC_INTR_CTRL 0x0008 -#define REG_DAC_INTR_STS 0x000C -#define REG_DAC_PWR_CTRL 0x0010 -#define REG_DAC_ANAPAR_DA0 0x0014 -#define REG_DAC_ANAPAR_DA1 0x0018 - - -//================ DAC HAL related enumeration ================== - - -//================ DAC HAL Macro =========================== -#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \ - ,addr,value) -#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr) - - -//================ DAC Function Prototypes ===================== -RTK_STATUS HalDACInit8195a(IN VOID *Data); -RTK_STATUS HalDACDeInit8195a(IN VOID *Data); -RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data); -RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data); -u8 HalDACSendRtl8195a(IN VOID *Data); -u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg); - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h deleted file mode 100644 index eddf68a8e08..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h +++ /dev/null @@ -1,548 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - - -#ifndef _RTL8195A_GDMA_H_ -#define _RTL8195A_GDMA_H_ - -// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1 -// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL -#define GDMA_HANDSHAKE_UART0_TX 0 -#define GDMA_HANDSHAKE_UART0_RX 1 -#define GDMA_HANDSHAKE_UART1_TX 2 -#define GDMA_HANDSHAKE_UART1_RX 3 -#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed -#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed - -#define GDMA_HANDSHAKE_SSI0_TX 4 -#define GDMA_HANDSHAKE_SSI0_RX 5 -#define GDMA_HANDSHAKE_SSI1_TX 6 -#define GDMA_HANDSHAKE_SSI1_RX 7 -#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed -#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed - -#define GDMA_HANDSHAKE_I2C0_TX 8 -#define GDMA_HANDSHAKE_I2C0_RX 9 -#define GDMA_HANDSHAKE_I2C1_TX 10 -#define GDMA_HANDSHAKE_I2C1_RX 11 - -#define GDMA_HANDSHAKE_ADC 12 -#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed -#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed - -#define HAL_GDMAX_READ32(GdmaIndex, addr) \ - HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) -#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \ - HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value) -#define HAL_GDMAX_READ16(GdmaIndex, addr) \ - HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) -#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \ - HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value) -#define HAL_GDMAX_READ8(GdmaIndex, addr) \ - HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) -#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \ - HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value) - - -#define GDMA_CH_MAX 0x06 - -#define REG_GDMA_CH_OFF 0x058 -#define REG_GDMA_CH_SAR 0x000 -#define REG_GDMA_CH_DAR 0x008 -#define REG_GDMA_CH_LLP 0x010 -#define REG_GDMA_CH_CTL 0x018 -#define REG_GDMA_CH_SSTAT 0x020 -#define REG_GDMA_CH_DSTAT 0x028 -#define REG_GDMA_CH_SSTATAR 0x030 -#define REG_GDMA_CH_DSTATAR 0x038 -#define REG_GDMA_CH_CFG 0x040 -#define REG_GDMA_CH_SGR 0x048 -#define REG_GDMA_CH_DSR 0x050 - -#define MAX_DMA_BLOCK_SIZE 4092 - -//3 Interrupt Registers -#define REG_GDMA_RAW_INT_BASE 0x2C0 -#define REG_GDMA_RAW_INT_TFR 0x2C0 -#define REG_GDMA_RAW_INT_BLOCK 0x2c8 -#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0 -#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8 -#define REG_GDMA_RAW_INT_ERR 0x2E0 - -#define REG_GDMA_STATUS_INT_BASE 0x2E8 -#define REG_GDMA_STATUS_INT_TFR 0x2E8 -#define REG_GDMA_STATUS_INT_BLOCK 0x2F0 -#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8 -#define REG_GDMA_STATUS_INT_DST_TRAN 0x300 -#define REG_GDMA_STATUS_INT_ERR 0x308 - -#define REG_GDMA_MASK_INT_BASE 0x310 -#define REG_GDMA_MASK_INT_TFR 0x310 -#define REG_GDMA_MASK_INT_BLOCK 0x318 -#define REG_GDMA_MASK_INT_SRC_TRAN 0x320 -#define REG_GDMA_MASK_INT_DST_TRAN 0x328 -#define REG_GDMA_MASK_INT_INT_ERR 0x330 - -#define REG_GDMA_CLEAR_INT_BASE 0x338 -#define REG_GDMA_CLEAR_INT_TFR 0x338 -#define REG_GDMA_CLEAR_INT_BLOCK 0x340 -#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348 -#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350 -#define REG_GDMA_CLEAR_INT_ERR 0x358 -#define REG_GDMA_STATUS_INT 0x360 - -//3 Software handshaking Registers -#define REG_GDMA_REQ_SRC 0x368 -#define REG_GDMA_REQ_DST 0x370 -#define REG_GDMA_REQ_SGL_REQ 0x378 -#define REG_GDMA_REQ_DST_REQ 0x380 -#define REG_GDMA_REQ_LST_SRC 0x388 -#define REG_GDMA_REQ_LST_DST 0x390 - -//3 Miscellaneous Registers -#define REG_GDMA_DMAC_CFG 0x398 -#define REG_GDMA_CH_EN 0x3A0 -#define REG_GDMA_DMA_ID 0x3A8 -#define REG_GDMA_DMA_TEST 0x3B0 -#define REG_GDMA_DMA_COM_PARAMS6 0x3C8 -#define REG_GDMA_DMA_COM_PARAMS5 0x3D0 -#define REG_GDMA_DMA_COM_PARAMS4 0x3D8 -#define REG_GDMA_DMA_COM_PARAMS3 0x3E0 -#define REG_GDMA_DMA_COM_PARAMS2 0x3E8 -#define REG_GDMA_DMA_COM_PARAMS1 0x3F0 -#define REG_GDMA_DMA_COM_PARAMS0 0x3F8 - -//3 CTL Register Bit Control -#define BIT_SHIFT_CTLX_LO_INT_EN 0 -#define BIT_MASK_CTLX_LO_INT_EN 0x1 -#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN) -#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN)) - -#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1 -#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7 -#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH) -#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)) - -#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4 -#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7 -#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH) -#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)) - -#define BIT_SHIFT_CTLX_LO_DINC 7 -#define BIT_MASK_CTLX_LO_DINC 0x3 -#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC) -#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC)) - -#define BIT_SHIFT_CTLX_LO_SINC 9 -#define BIT_MASK_CTLX_LO_SINC 0x3 -#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC) -#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC)) - -#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11 -#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7 -#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE) -#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE)) - -#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14 -#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7 -#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE) -#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE)) - - -#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17 -#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1 -#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN) -#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)) - - -#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18 -#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1 -#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN) -#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)) - - -#define BIT_SHIFT_CTLX_LO_TT_FC 20 -#define BIT_MASK_CTLX_LO_TT_FC 0x7 -#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC) -#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC)) - - -#define BIT_SHIFT_CTLX_LO_DMS 23 -#define BIT_MASK_CTLX_LO_DMS 0x3 -#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS) -#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS)) - - -#define BIT_SHIFT_CTLX_LO_SMS 25 -#define BIT_MASK_CTLX_LO_SMS 0x3 -#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS) -#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS)) - - -#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27 -#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1 -#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN) -#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN)) - -#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28 -#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1 -#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN) -#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)) - - -#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0 -#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF -#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS) -#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS)) - - -#define BIT_SHIFT_CTLX_UP_DONE 12 -#define BIT_MASK_CTLX_UP_DONE 0x1 -#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE) -#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE)) - - -//3 CFG Register Bit Control -#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5 -#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7 -#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR) -#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR)) - - -#define BIT_SHIFT_CFGX_LO_CH_SUSP 8 -#define BIT_MASK_CFGX_LO_CH_SUSP 0x1 -#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP) -#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP)) - - -#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9 -#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1 -#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY) -#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)) - - -#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10 -#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1 -#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST) -#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST)) - -#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11 -#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1 -#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC) -#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)) - -#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12 -#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3 -#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L) -#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L)) - -#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14 -#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3 -#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L) -#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L)) - -#define BIT_SHIFT_CFGX_LO_LOCK_CH 16 -#define BIT_MASK_CFGX_LO_LOCK_CH 0x1 -#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH) -#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH)) - -#define BIT_SHIFT_CFGX_LO_LOCK_B 17 -#define BIT_MASK_CFGX_LO_LOCK_B 0x1 -#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B) -#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B)) - -#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18 -#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1 -#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL) -#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL)) - -#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19 -#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1 -#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL) -#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL)) - -#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20 -#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF -#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST) -#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST)) - -#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30 -#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1 -#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC) -#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC)) - -#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31 -#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1 -#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST) -#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST)) - -#define BIT_SHIFT_CFGX_UP_FCMODE 0 -#define BIT_MASK_CFGX_UP_FCMODE 0x1 -#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE) -#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE)) - -#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1 -#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1 -#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE) -#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE)) - -#define BIT_SHIFT_CFGX_UP_PROTCTL 2 -#define BIT_MASK_CFGX_UP_PROTCTL 0x7 -#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL) -#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL)) - -#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5 -#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1 -#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN) -#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN)) - -#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6 -#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1 -#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN) -#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN)) - -#define BIT_SHIFT_CFGX_UP_SRC_PER 7 -#define BIT_MASK_CFGX_UP_SRC_PER 0xF -#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER) -#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER)) - -#define BIT_SHIFT_CFGX_UP_DEST_PER 11 -#define BIT_MASK_CFGX_UP_DEST_PER 0xF -#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER) -#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER)) - -enum _GDMA_CHANNEL_NUM_ { - GdmaNoCh = 0x0000, - GdmaCh0 = 0x0101, - GdmaCh1 = 0x0202, - GdmaCh2 = 0x0404, - GdmaCh3 = 0x0808, - GdmaCh4 = 0x1010, - GdmaCh5 = 0x2020, - GdmaCh6 = 0x4040, - GdmaCh7 = 0x8080, - GdmaAllCh = 0xffff -}; -typedef uint32_t GDMA_CHANNEL_NUM; -typedef uint32_t *PGDMA_CHANNEL_NUM; - - -//3 CTL register struct - -enum _GDMA_CTL_TT_FC_TYPE_ { - TTFCMemToMem = 0x00, - TTFCMemToPeri = 0x01, - TTFCPeriToMem = 0x02 -}; -typedef uint32_t GDMA_CTL_TT_FC_TYPE; -typedef uint32_t *PGDMA_CTL_TT_FC_TYPE; - -//Max type = Bus Width -enum _GDMA_CTL_TR_WIDTH_ { - TrWidthOneByte = 0x00, - TrWidthTwoBytes = 0x01, - TrWidthFourBytes = 0x02 -}; -typedef uint32_t GDMA_CTL_TR_WIDTH; -typedef uint32_t *PGDMA_CTL_TR_WIDTH; - -enum _GDMA_CTL_MSIZE_ { - MsizeOne = 0x00, - MsizeFour = 0x01, - MsizeEight = 0x02 -}; -typedef uint32_t GDMA_CTL_MSIZE; -typedef uint32_t *PGDMA_CTL_MSIZE; - -enum _GDMA_INC_TYPE_ { - IncType = 0x00, - DecType = 0x01, - NoChange = 0x02 -}; -typedef uint32_t GDMA_INC_TYPE; -typedef uint32_t *PGDMA_INC_TYPE; - - -typedef struct _GDMA_CTL_REG_ { - GDMA_CTL_TT_FC_TYPE TtFc; - GDMA_CTL_TR_WIDTH DstTrWidth; - GDMA_CTL_TR_WIDTH SrcTrWidth; - GDMA_INC_TYPE Dinc; - GDMA_INC_TYPE Sinc; - GDMA_CTL_MSIZE DestMsize; - GDMA_CTL_MSIZE SrcMsize; - - u8 IntEn :1; // Bit 0 - u8 SrcGatherEn :1; // Bit 1 - u8 DstScatterEn :1; // Bit 2 - u8 LlpDstEn :1; // Bit 3 - u8 LlpSrcEn :1; // Bit 4 - u8 Done :1; // Bit 5 - u8 Rsvd6To7 :2; //Bit 6 -7 - u16 BlockSize; - -}GDMA_CTL_REG, *PGDMA_CTL_REG; - - -//3 CFG Register Structure - -enum _GDMA_CH_PRIORITY_ { - Prior0 = 0, - Prior1 = 1, - Prior2 = 2, - Prior3 = 3, - Prior4 = 4, - Prior5 = 5, - Prior6 = 6, - Prior7 = 7 -}; -typedef uint32_t GDMA_CH_PRIORITY; -typedef uint32_t *PGDMA_CH_PRIORITY; - -enum _GDMA_LOCK_LEVEL_ { - OverComplDmaTransfer = 0x00, - OverComplDmaBlockTransfer = 0x01, - OverComplDmaTransation = 0x02 -}; -typedef uint32_t GDMA_LOCK_LEVEL; -typedef uint32_t *PGDMA_LOCK_LEVEL; - - -typedef struct _GDMA_CFG_REG_ { - GDMA_CH_PRIORITY ChPrior; - GDMA_LOCK_LEVEL LockBL; - GDMA_LOCK_LEVEL LockChL; - u16 MaxAbrst; - u8 SrcPer; - u8 DestPer; - u16 ChSusp :1; //Bit 0 - u16 FifoEmpty :1; //Bit 1 - u16 HsSelDst :1; //Bit 2 - u16 HsSelSrc :1; //Bit 3 - u16 LockCh :1; //Bit 4 - u16 LockB :1; //Bit 5 - u16 DstHsPol :1; //Bit 6 - u16 SrcHsPol :1; //Bit 7 - u16 ReloadSrc :1; //Bit 8 - u16 ReloadDst :1; //Bit 9 - u16 FifoMode :1; //Bit 10 - u16 DsUpdEn :1; //Bit 11 - u16 SsUpdEn :1; //Bit 12 - u16 Rsvd13To15 :3; -}GDMA_CFG_REG, *PGDMA_CFG_REG; - -enum _GDMA_ISR_TYPE_ { - TransferType = 0x1, - BlockType = 0x2, - SrcTransferType = 0x4, - DstTransferType = 0x8, - ErrType = 0x10 -}; -typedef uint32_t GDMA_ISR_TYPE; -typedef uint32_t *PGDMA_ISR_TYPE; - - -VOID -HalGdmaOnOffRtl8195a ( - IN VOID *Data -); - -BOOL -HalGdamChInitRtl8195a( - IN VOID *Data -); - -BOOL -HalGdmaChSetingRtl8195a( - IN VOID *Data -); - -BOOL -HalGdmaChBlockSetingRtl8195a( - IN VOID *Data -); - -BOOL -HalGdmaChBlockSetingRtl8195a_Patch( - IN VOID *Data -); - -VOID -HalGdmaChDisRtl8195a ( - IN VOID *Data -); - -VOID -HalGdmaChEnRtl8195a ( - IN VOID *Data -); - -VOID -HalGdmaChIsrEnAndDisRtl8195a ( - IN VOID *Data -); - -u8 -HalGdmaChIsrCleanRtl8195a ( - IN VOID *Data -); - -VOID -HalGdmaChCleanAutoSrcRtl8195a ( - IN VOID *Data -); - -VOID -HalGdmaChCleanAutoDstRtl8195a ( - IN VOID *Data -); - -u32 -HalGdmaQueryDArRtl8195a( - IN VOID *Data -); - -u32 -HalGdmaQuerySArRtl8195a( - IN VOID *Data -); - -BOOL -HalGdmaQueryChEnRtl8195a ( - IN VOID *Data -); - -#ifdef CONFIG_CHIP_E_CUT -_LONG_CALL_ BOOL -HalGdmaChBlockSetingRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ u32 -HalGdmaQueryDArRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ u32 -HalGdmaQuerySArRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ BOOL -HalGdmaQueryChEnRtl8195a_V04 ( - IN VOID *Data -); - -#endif // #ifdef CONFIG_CHIP_E_CUT - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h deleted file mode 100644 index cdc90a01312..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h +++ /dev/null @@ -1,341 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - - -#ifndef _RTL8195A_GPIO_H_ -#define _RTL8195A_GPIO_H_ - -#include "hal_api.h" -#include "hal_gpio.h" - -#define GPIO_PORTA_DR 0x00 // data register -#define GPIO_PORTA_DDR 0x04 // data direction -#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software - -#define GPIO_PORTB_DR 0x0c // data register -#define GPIO_PORTB_DDR 0x10 // data direction -#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software - -#define GPIO_PORTC_DR 0x18 // data register -#define GPIO_PORTC_DDR 0x1c // data direction -#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software - -//1 Only the PORTA can be configured to generate interrupts -#define GPIO_INT_EN 0x30 // Interrupt enable register -#define GPIO_INT_MASK 0x34 // Interrupt mask -#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register -#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register -#define GPIO_INT_STATUS 0x40 // Interrupt status -#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask -#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce -#define GPIO_PORTA_EOI 0x4c // Clear interrupt - -#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back -#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back -#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back - -#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK - -enum { - HAL_GPIO_HIGHZ = 0, - HAL_GPIO_PULL_LOW = 1, - HAL_GPIO_PULL_HIGH = 2 -}; - -//====================================================== -// ROM Function prototype -extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; -#ifndef CONFIG_RELEASE_BUILD_LIBRARIES -static __inline HAL_Status -GPIO_Lock ( - VOID -) -{ - HAL_Status Status; - - if (_pHAL_Gpio_Adapter->EnterCritical) { - _pHAL_Gpio_Adapter->EnterCritical(); - } - - if(_pHAL_Gpio_Adapter->Locked) { - Status = HAL_BUSY; - } - else { - _pHAL_Gpio_Adapter->Locked = 1; - Status = HAL_OK; - } - - if (_pHAL_Gpio_Adapter->ExitCritical) { - _pHAL_Gpio_Adapter->ExitCritical(); - } - - return Status; -} - - -static __inline VOID -GPIO_UnLock ( - VOID -) -{ - if (_pHAL_Gpio_Adapter->EnterCritical) { - _pHAL_Gpio_Adapter->EnterCritical(); - } - - _pHAL_Gpio_Adapter->Locked = 0; - - if (_pHAL_Gpio_Adapter->ExitCritical) { - _pHAL_Gpio_Adapter->ExitCritical(); - } -} -#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES - -_LONG_CALL_ extern u32 -HAL_GPIO_IrqHandler_8195a( - IN VOID *pData -); - -_LONG_CALL_ extern u32 -HAL_GPIO_MbedIrqHandler_8195a( - IN VOID *pData -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_IntCtrl_8195a( - HAL_GPIO_PIN *GPIO_Pin, - u32 En -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_Init_8195a( - HAL_GPIO_PIN *GPIO_Pin -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_DeInit_8195a( - HAL_GPIO_PIN *GPIO_Pin -); - -_LONG_CALL_ HAL_GPIO_PIN_STATE -HAL_GPIO_ReadPin_8195a( - HAL_GPIO_PIN *GPIO_Pin -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_WritePin_8195a( - HAL_GPIO_PIN *GPIO_Pin, - HAL_GPIO_PIN_STATE Pin_State -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_RegIrq_8195a( - IN PIRQ_HANDLE pIrqHandle -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_UnRegIrq_8195a( - IN PIRQ_HANDLE pIrqHandle -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_UserRegIrq_8195a( - HAL_GPIO_PIN *GPIO_Pin, - VOID *IrqHandler, - VOID *IrqData -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_UserUnRegIrq_8195a( - HAL_GPIO_PIN *GPIO_Pin -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_MaskIrq_8195a( - HAL_GPIO_PIN *GPIO_Pin -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_UnMaskIrq_8195a( - HAL_GPIO_PIN *GPIO_Pin -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_IntDebounce_8195a( - HAL_GPIO_PIN *GPIO_Pin, - u8 Enable -); - -_LONG_CALL_ u32 -HAL_GPIO_GetIPPinName_8195a( - u32 chip_pin -); - -_LONG_CALL_ HAL_Status -HAL_GPIO_PullCtrl_8195a( - u32 chip_pin, - u8 pull_type -); - -_LONG_CALL_ u32 -GPIO_GetChipPinName_8195a( - u32 port, - u32 pin -); - -_LONG_CALL_ VOID -GPIO_PullCtrl_8195a( - u32 chip_pin, - u8 pull_type -); - -_LONG_CALL_ VOID -GPIO_Int_SetType_8195a( - u8 pin_num, - u8 int_mode -); - - -_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En); -_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr); - -HAL_Status -HAL_GPIO_ClearISR_8195a( - HAL_GPIO_PIN *GPIO_Pin -); - - -/********** HAL In-Line Functions **********/ - -/** - * @brief Reads the specified input port pin. - * - * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. - * - * @retval The input port pin current status(High or Low). - */ -static __inline s32 -HAL_GPIO_ReadPin( - HAL_GPIO_PIN *GPIO_Pin -) -{ - return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin); -} - -/** - * @brief Write the specified output port pin. - * - * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. - * - * @param Pin_State: The state going to be set to the assigned GPIO pin. - * - * @retval None - */ -static __inline VOID -HAL_GPIO_WritePin( - HAL_GPIO_PIN *GPIO_Pin, - u32 Value -) -{ - HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value); -} - -/** - * @brief To register a user interrupt handler for a specified pin - * - * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. - * - * @param IrqHandler: The IRQ handler to be assigned to the specified pin - * - * @param IrqData: The pointer will be pass the the IRQ handler - * - * @retval None - */ -static __inline VOID -HAL_GPIO_UserRegIrq( - HAL_GPIO_PIN *GPIO_Pin, - VOID *IrqHandler, - VOID *IrqData -) -{ - HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData); -} - -/** - * @brief To un-register a user interrupt handler for a specified pin - * - * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. - * - * @retval None - */ -static __inline VOID -HAL_GPIO_UserUnRegIrq( - HAL_GPIO_PIN *GPIO_Pin -) -{ - HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin); -} - - -/** - * @brief Enable/Disable GPIO interrupt - * - * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization. - * - * @param En: Enable (1) or Disable (0) - * - * @retval HAL_Status - */ -static __inline VOID -HAL_GPIO_IntCtrl( - HAL_GPIO_PIN *GPIO_Pin, - u32 En -) -{ - HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En); -} - -/** - * @brief Mask the interrupt of a specified pin - * - * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. - * - * @retval None - */ -static __inline VOID -HAL_GPIO_MaskIrq( - HAL_GPIO_PIN *GPIO_Pin -) -{ - HAL_GPIO_MaskIrq_8195a(GPIO_Pin); -} - - -/** - * @brief UnMask the interrupt of a specified pin - * - * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. - * - * @retval None - */ -static __inline VOID -HAL_GPIO_UnMaskIrq( - HAL_GPIO_PIN *GPIO_Pin -) -{ - HAL_GPIO_ClearISR_8195a(GPIO_Pin); - HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin); -} - - -#endif // end of "#define _RTL8195A_GPIO_H_" - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h deleted file mode 100644 index edd27c1e322..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h +++ /dev/null @@ -1,870 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _RTL8195A_I2C_H_ -#define _RTL8195A_I2C_H_ - -#include "hal_api.h" - -//================ Register Bit Field ================== -//2 REG_DW_I2C_IC_CON -#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6) -#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6 -#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1 -#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE) - -#define BIT_IC_CON_IC_RESTART_EN BIT(5) -#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5 -#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1 -#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN) - -#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4) -#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4 -#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1 -#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER) - -#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3) -#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3 -#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1 -#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE) - - -#define BIT_SHIFT_IC_CON_SPEED 1 -#define BIT_MASK_IC_CON_SPEED 0x3 -#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED) -#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED) -#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED) - -#define BIT_IC_CON_MASTER_MODE BIT(0) -#define BIT_SHIFT_IC_CON_MASTER_MODE 0 -#define BIT_MASK_IC_CON_MASTER_MODE 0x1 -#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE) - - -//2 REG_DW_I2C_IC_TAR -#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12) -#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12 -#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1 -#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER) - -#define BIT_IC_TAR_SPECIAL BIT(11) -#define BIT_SHIFT_IC_TAR_SPECIAL 11 -#define BIT_MASK_IC_TAR_SPECIAL 0x1 -#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL) - -#define BIT_IC_TAR_GC_OR_START BIT(10) -#define BIT_SHIFT_IC_TAR_GC_OR_START 10 -#define BIT_MASK_IC_TAR_GC_OR_START 0x1 -#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START) - - -#define BIT_SHIFT_IC_TAR 0 -#define BIT_MASK_IC_TAR 0x3ff -#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR) -#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR) -#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR) - - -//2 REG_DW_I2C_IC_SAR - -#define BIT_SHIFT_IC_SAR 0 -#define BIT_MASK_IC_SAR 0x3ff -#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR) -#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR) -#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR) - - -//2 REG_DW_I2C_IC_HS_MADDR - -#define BIT_SHIFT_IC_HS_MADDR 0 -#define BIT_MASK_IC_HS_MADDR 0x7 -#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR) -#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR) -#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR) - - -//2 REG_DW_I2C_IC_DATA_CMD -#define BIT_IC_DATA_CMD_RESTART BIT(10) -#define BIT_SHIFT_IC_DATA_CMD_RESTART 10 -#define BIT_MASK_IC_DATA_CMD_RESTART 0x1 -#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART) - -#define BIT_IC_DATA_CMD_STOP BIT(9) -#define BIT_SHIFT_IC_DATA_CMD_STOP 9 -#define BIT_MASK_IC_DATA_CMD_STOP 0x1 -#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP) - -#define BIT_IC_DATA_CMD_CMD BIT(8) -#define BIT_SHIFT_IC_DATA_CMD_CMD 8 -#define BIT_MASK_IC_DATA_CMD_CMD 0x1 -#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD) - - -#define BIT_SHIFT_IC_DATA_CMD_DAT 0 -#define BIT_MASK_IC_DATA_CMD_DAT 0xff -#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT) -#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT) -#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT) - - -//2 REG_DW_I2C_IC_SS_SCL_HCNT - -#define BIT_SHIFT_IC_SS_SCL_HCNT 0 -#define BIT_MASK_IC_SS_SCL_HCNT 0xffff -#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT) -#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT) -#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT) - - -//2 REG_DW_I2C_IC_SS_SCL_LCNT - -#define BIT_SHIFT_IC_SS_SCL_LCNT 0 -#define BIT_MASK_IC_SS_SCL_LCNT 0xffff -#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT) -#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT) -#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT) - - -//2 REG_DW_I2C_IC_FS_SCL_HCNT - -#define BIT_SHIFT_IC_FS_SCL_HCNT 0 -#define BIT_MASK_IC_FS_SCL_HCNT 0xffff -#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT) -#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT) -#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT) - - -//2 REG_DW_I2C_IC_FS_SCL_LCNT - -#define BIT_SHIFT_IC_FS_SCL_LCNT 0 -#define BIT_MASK_IC_FS_SCL_LCNT 0xffff -#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT) -#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT) -#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT) - - -//2 REG_DW_I2C_IC_HS_SCL_HCNT - -#define BIT_SHIFT_IC_HS_SCL_HCNT 0 -#define BIT_MASK_IC_HS_SCL_HCNT 0xffff -#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT) -#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT) -#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT) - - -//2 REG_DW_I2C_IC_HS_SCL_LCNT - -#define BIT_SHIFT_IC_HS_SCL_LCNT 0 -#define BIT_MASK_IC_HS_SCL_LCNT 0xffff -#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT) -#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT) -#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT) - - -//2 REG_DW_I2C_IC_INTR_STAT -#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11) -#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11 -#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL) - -#define BIT_IC_INTR_STAT_R_START_DET BIT(10) -#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10 -#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET) - -#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9) -#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9 -#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET) - -#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8) -#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8 -#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY) - -#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7) -#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7 -#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE) - -#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6) -#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6 -#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT) - -#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5) -#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5 -#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ) - -#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4) -#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4 -#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY) - -#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3) -#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3 -#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER) - -#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2) -#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2 -#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL) - -#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1) -#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1 -#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER) - -#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0) -#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0 -#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1 -#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER) - - -//2 REG_DW_I2C_IC_INTR_MASK -#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11) -#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11 -#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL) - -#define BIT_IC_INTR_MASK_M_START_DET BIT(10) -#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10 -#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET) - -#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9) -#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9 -#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET) - -#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8) -#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8 -#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY) - -#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7) -#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7 -#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE) - -#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6) -#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6 -#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT) - -#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5) -#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5 -#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ) - -#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4) -#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4 -#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY) - -#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3) -#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3 -#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER) - -#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2) -#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2 -#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL) - -#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1) -#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1 -#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER) - -#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0) -#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0 -#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1 -#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER) - - -//2 REG_DW_I2C_IC_RAW_INTR_STAT -#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11) -#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11 -#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL) - -#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10) -#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10 -#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET) - -#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9) -#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9 -#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET) - -#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8) -#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8 -#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY) - -#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7) -#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7 -#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE) - -#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6) -#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6 -#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT) - -#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5) -#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5 -#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ) - -#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4) -#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4 -#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY) - -#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3) -#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3 -#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER) - -#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2) -#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2 -#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL) - -#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1) -#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1 -#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER) - -#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0) -#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0 -#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1 -#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER) - - -//2 REG_DW_I2C_IC_RX_TL - -#define BIT_SHIFT_IC_RX_TL 0 -#define BIT_MASK_IC_RX_TL 0xff -#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL) -#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL) -#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL) - - -//2 REG_DW_I2C_IC_TX_TL - -#define BIT_SHIFT_IC_TX_TL 0 -#define BIT_MASK_IC_TX_TL 0xff -#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL) -#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL) -#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL) - - -//2 REG_DW_I2C_IC_CLR_INTR -#define BIT_IC_CLR_INTR BIT(0) -#define BIT_SHIFT_IC_CLR_INTR 0 -#define BIT_MASK_IC_CLR_INTR 0x1 -#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR) - - -//2 REG_DW_I2C_IC_CLR_RX_UNDER -#define BIT_IC_CLR_RX_UNDER BIT(0) -#define BIT_SHIFT_IC_CLR_RX_UNDER 0 -#define BIT_MASK_IC_CLR_RX_UNDER 0x1 -#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER) - - -//2 REG_DW_I2C_IC_CLR_RX_OVER -#define BIT_IC_CLR_RX_OVER BIT(0) -#define BIT_SHIFT_IC_CLR_RX_OVER 0 -#define BIT_MASK_IC_CLR_RX_OVER 0x1 -#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER) - - -//2 REG_DW_I2C_IC_CLR_TX_OVER -#define BIT_IC_CLR_TX_OVER BIT(0) -#define BIT_SHIFT_IC_CLR_TX_OVER 0 -#define BIT_MASK_IC_CLR_TX_OVER 0x1 -#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER) - - -//2 REG_DW_I2C_IC_CLR_RD_REQ -#define BIT_IC_CLR_RD_REQ BIT(0) -#define BIT_SHIFT_IC_CLR_RD_REQ 0 -#define BIT_MASK_IC_CLR_RD_REQ 0x1 -#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ) - - -//2 REG_DW_I2C_IC_CLR_TX_ABRT -#define BIT_CLR_RD_REQ BIT(0) -#define BIT_SHIFT_CLR_RD_REQ 0 -#define BIT_MASK_CLR_RD_REQ 0x1 -#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ) - - -//2 REG_DW_I2C_IC_CLR_RX_DONE -#define BIT_IC_CLR_RX_DONE BIT(0) -#define BIT_SHIFT_IC_CLR_RX_DONE 0 -#define BIT_MASK_IC_CLR_RX_DONE 0x1 -#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE) - - -//2 REG_DW_I2C_IC_CLR_ACTIVITY -#define BIT_IC_CLR_ACTIVITY BIT(0) -#define BIT_SHIFT_IC_CLR_ACTIVITY 0 -#define BIT_MASK_IC_CLR_ACTIVITY 0x1 -#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY) - - -//2 REG_DW_I2C_IC_CLR_STOP_DET -#define BIT_IC_CLR_STOP_DET BIT(0) -#define BIT_SHIFT_IC_CLR_STOP_DET 0 -#define BIT_MASK_IC_CLR_STOP_DET 0x1 -#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET) - - -//2 REG_DW_I2C_IC_CLR_START_DET -#define BIT_IC_CLR_START_DET BIT(0) -#define BIT_SHIFT_IC_CLR_START_DET 0 -#define BIT_MASK_IC_CLR_START_DET 0x1 -#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET) - - -//2 REG_DW_I2C_IC_CLR_GEN_CALL -#define BIT_IC_CLR_GEN_CALL BIT(0) -#define BIT_SHIFT_IC_CLR_GEN_CALL 0 -#define BIT_MASK_IC_CLR_GEN_CALL 0x1 -#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL) - - -//2 REG_DW_I2C_IC_ENABLE -#define BIT_IC_ENABLE BIT(0) -#define BIT_SHIFT_IC_ENABLE 0 -#define BIT_MASK_IC_ENABLE 0x1 -#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE) - - -//2 REG_DW_I2C_IC_STATUS -#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6) -#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6 -#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1 -#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY) - -#define BIT_IC_STATUS_MST_ACTIVITY BIT(5) -#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5 -#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1 -#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY) - -#define BIT_IC_STATUS_RFF BIT(4) -#define BIT_SHIFT_IC_STATUS_RFF 4 -#define BIT_MASK_IC_STATUS_RFF 0x1 -#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF) - -#define BIT_IC_STATUS_RFNE BIT(3) -#define BIT_SHIFT_IC_STATUS_RFNE 3 -#define BIT_MASK_IC_STATUS_RFNE 0x1 -#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE) - -#define BIT_IC_STATUS_TFE BIT(2) -#define BIT_SHIFT_IC_STATUS_TFE 2 -#define BIT_MASK_IC_STATUS_TFE 0x1 -#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE) - -#define BIT_IC_STATUS_TFNF BIT(1) -#define BIT_SHIFT_IC_STATUS_TFNF 1 -#define BIT_MASK_IC_STATUS_TFNF 0x1 -#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF) - -#define BIT_IC_STATUS_ACTIVITY BIT(0) -#define BIT_SHIFT_IC_STATUS_ACTIVITY 0 -#define BIT_MASK_IC_STATUS_ACTIVITY 0x1 -#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY) - - -//2 REG_DW_I2C_IC_TXFLR - -#define BIT_SHIFT_IC_TXFLR 0 -#define BIT_MASK_IC_TXFLR 0x3f -#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR) -#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR) -#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR) - - -//2 REG_DW_I2C_IC_RXFLR - -#define BIT_SHIFT_IC_RXFLR 0 -#define BIT_MASK_IC_RXFLR 0x1f -#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR) -#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR) -#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR) - - -//2 REG_DW_I2C_IC_SDA_HOLD - -#define BIT_SHIFT_IC_SDA_HOLD 0 -#define BIT_MASK_IC_SDA_HOLD 0xffff -#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD) -#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD) -#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD) - - -//2 REG_DW_I2C_IC_TX_ABRT_SOURCE -#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) - -#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) - -#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0) -#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0 -#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1 -#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) - - -//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY -#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0) -#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0 -#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1 -#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY) - - -//2 REG_DW_I2C_IC_DMA_CR -#define BIT_IC_DMA_CR_TDMAE BIT(1) -#define BIT_SHIFT_IC_DMA_CR_TDMAE 1 -#define BIT_MASK_IC_DMA_CR_TDMAE 0x1 -#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE) - -#define BIT_IC_DMA_CR_RDMAE BIT(0) -#define BIT_SHIFT_IC_DMA_CR_RDMAE 0 -#define BIT_MASK_IC_DMA_CR_RDMAE 0x1 -#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE) - - -//2 REG_DW_I2C_IC_DMA_TDLR - -#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0 -#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f -#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL) -#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL) -#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL) - - -//2 REG_DW_I2C_IC_DMA_RDLR - -#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0 -#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf -#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL) -#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL) -#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL) - - -//2 REG_DW_I2C_IC_SDA_SETUP - -#define BIT_SHIFT_IC_SDA_SETUP 0 -#define BIT_MASK_IC_SDA_SETUP 0xff -#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP) -#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP) -#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP) - - -//2 REG_DW_I2C_IC_ACK_GENERAL_CALL -#define BIT_IC_ACK_GENERAL_CALL BIT(0) -#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0 -#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1 -#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL) - - -//2 REG_DW_I2C_IC_ENABLE_STATUS -#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2) -#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2 -#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1 -#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) - -#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1) -#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1 -#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1 -#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) - -#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0) -#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0 -#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1 -#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN) - - -//2 REG_DW_I2C_IC_COMP_PARAM_1 - -#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16 -#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff -#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) -#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) -#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) - - -#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8 -#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff -#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) -#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) -#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) - -#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7) -#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7 -#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1 -#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) - -#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6) -#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6 -#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1 -#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA) - -#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5) -#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5 -#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1 -#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO) - -#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4) -#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4 -#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1 -#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES) - - -#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2 -#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3 -#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) -#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) -#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) - - -#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0 -#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3 -#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) -#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) -#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) - - -//2 REG_DW_I2C_IC_COMP_VERSION - -#define BIT_SHIFT_IC_COMP_VERSION 0 -#define BIT_MASK_IC_COMP_VERSION 0xffffffffL -#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION) -#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION) -#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION) - - -//2 REG_DW_I2C_IC_COMP_TYPE - -#define BIT_SHIFT_IC_COMP_TYPE 0 -#define BIT_MASK_IC_COMP_TYPE 0xffffffffL -#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE) -#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE) -#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE) - -//======================== Register Address Definition ======================== -#define REG_DW_I2C_IC_CON 0x0000 -#define REG_DW_I2C_IC_TAR 0x0004 -#define REG_DW_I2C_IC_SAR 0x0008 -#define REG_DW_I2C_IC_HS_MADDR 0x000C -#define REG_DW_I2C_IC_DATA_CMD 0x0010 -#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014 -#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018 -#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C -#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020 -#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024 -#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028 -#define REG_DW_I2C_IC_INTR_STAT 0x002C -#define REG_DW_I2C_IC_INTR_MASK 0x0030 -#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034 -#define REG_DW_I2C_IC_RX_TL 0x0038 -#define REG_DW_I2C_IC_TX_TL 0x003C -#define REG_DW_I2C_IC_CLR_INTR 0x0040 -#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044 -#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048 -#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C -#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050 -#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054 -#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058 -#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C -#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060 -#define REG_DW_I2C_IC_CLR_START_DET 0x0064 -#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068 -#define REG_DW_I2C_IC_ENABLE 0x006C -#define REG_DW_I2C_IC_STATUS 0x0070 -#define REG_DW_I2C_IC_TXFLR 0x0074 -#define REG_DW_I2C_IC_RXFLR 0x0078 -#define REG_DW_I2C_IC_SDA_HOLD 0x007C -#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080 -#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084 -#define REG_DW_I2C_IC_DMA_CR 0x0088 -#define REG_DW_I2C_IC_DMA_TDLR 0x008C -#define REG_DW_I2C_IC_DMA_RDLR 0x0090 -#define REG_DW_I2C_IC_SDA_SETUP 0x0094 -#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098 -#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C -#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4 -#define REG_DW_I2C_IC_COMP_VERSION 0x00F8 -#define REG_DW_I2C_IC_COMP_TYPE 0x00FC - -//====================================================== -// I2C related enumeration -// I2C Address Mode -enum _I2C_ADDR_MODE_ { - I2C_ADDR_7BIT = 0, - I2C_ADDR_10BIT = 1, -}; -typedef uint32_t I2C_ADDR_MODE; -typedef uint32_t *PI2C_ADDR_MODE; - -// I2C Speed Mode -enum _I2C_SPD_MODE_ { - I2C_SS_MODE = 1, - I2C_FS_MODE = 2, - I2C_HS_MODE = 3, -}; -typedef uint32_t I2C_SPD_MODE; -typedef uint32_t *PI2C_SPD_MODE; - -//I2C Timing Parameters -#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns. -#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns. - -#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns. -#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns. - -#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf -#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf - -#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf -#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf - - -//====================================================== -//I2C Essential functions and macros -_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal); -_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg); - -#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value) -#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr) - -// Rtl8195a I2C function prototypes -_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data); -_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data); -_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data); -_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg); -_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal); - -//Rtl8195a I2C V02 function prototype -_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data); -#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) -_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data); -#elif defined(CONFIG_CHIP_E_CUT) -_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data); -#endif -//Rtl8195a I2C V02 function prototype END - -//Rtl8195a I2C V04 function prototype -_LONG_CALL_ HAL_Status HalI2CSendRtl8195a_V04(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a_V04(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CInit8195a_V04(IN VOID *Data); -_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195a_V04(IN VOID *Data); -//Rtl8195a I2C V04 function prototype END - -HAL_Status HalI2CInit8195a_Patch(IN VOID *Data); -HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data); -HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data); -HAL_Status HalI2CMassSendRtl8195a_Patch(IN VOID *Data); -HAL_Status HalI2CEnableRtl8195a_Patch(IN VOID *Data); -HAL_Status HalI2CSetTarRtl8195a(IN VOID *Data); -HAL_Status HalI2CSetSarRtl8195a(IN VOID *Data); - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2s.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2s.h deleted file mode 100644 index 13d7f59ea61..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2s.h +++ /dev/null @@ -1,714 +0,0 @@ -/* - * Routines to access hardware - * - * Copyright (c) 2013 Realtek Semiconductor Corp. - * - * This module is a confidential and proprietary property of RealTek and - * possession or use of this module requires written permission of RealTek. - */ - - -#ifndef _RTL8195A_I2S_H_ -#define _RTL8195A_I2S_H_ - - -//=============== Register Bit Field Definition ==================== -// REG_I2S_CONTROL -#define BIT_CTLX_I2S_EN BIT(0) -#define BIT_SHIFT_CTLX_I2S_EN 0 -#define BIT_MASK_CTLX_I2S_EN 0x1 -#define BIT_CTRL_CTLX_I2S_EN(x) (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN) - -#define BIT_SHIFT_CTLX_I2S_TRX_ACT 1 -#define BIT_MASK_CTLX_I2S_TRX_ACT 0x3 -#define BIT_CTRL_CTLX_I2S_TRX_ACT(x) (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT) -#define BIT_GET_CTLX_I2S_TRX_ACT(x) (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT) - -#define BIT_SHIFT_CTLX_I2S_CH_NUM 3 -#define BIT_MASK_CTLX_I2S_CH_NUM 0x3 -#define BIT_CTRL_CTLX_I2S_CH_NUM(x) (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM) -#define BIT_GET_CTLX_I2S_CH_NUM(x) (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM) - -#define BIT_CTLX_I2S_WL BIT(6) -#define BIT_SHIFT_CTLX_I2S_WL 6 -#define BIT_MASK_CTLX_I2S_WL 0x1 -#define BIT_CTRL_CTLX_I2S_WL(x) (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL) - -#define BIT_CTLX_I2S_LRSWAP BIT(10) -#define BIT_SHIFT_CTLX_I2S_LRSWAP 10 -#define BIT_MASK_CTLX_I2S_LRSWAP 0x1 -#define BIT_CTRL_CTLX_I2S_LRSWAP(x) (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP) - -#define BIT_CTLX_I2S_SCK_INV BIT(11) -#define BIT_SHIFT_CTLX_I2S_SCK_INV 11 -#define BIT_MASK_CTLX_I2S_SCK_INV 0x1 -#define BIT_CTRL_CTLX_I2S_SCK_INV(x) (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV) - -#define BIT_CTLX_I2S_ENDIAN_SWAP BIT(12) -#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP 12 -#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP 0x1 -#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP) - -#define BIT_CTLX_I2S_SLAVE_MODE BIT(29) -#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE 29 -#define BIT_MASK_CTLX_I2S_SLAVE_MODE 0x1 -#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x) (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE) - -#define BIT_CTLX_I2S_CLK_SRC BIT(30) -#define BIT_SHIFT_CTLX_I2S_CLK_SRC 30 -#define BIT_MASK_CTLX_I2S_CLK_SRC 0x1 -#define BIT_CTRL_CTLX_I2S_CLK_SRC(x) (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC) - -#define BIT_CTLX_I2S_SW_RSTN BIT(31) -#define BIT_SHIFT_CTLX_I2S_SW_RSTN 31 -#define BIT_MASK_CTLX_I2S_SW_RSTN 0x1 -#define BIT_CTRL_CTLX_I2S_SW_RSTN(x) (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN) - -// REG_I2S_SETTING -#define BIT_SHIFT_SETTING_I2S_PAGE_SZ 0 -#define BIT_MASK_SETTING_I2S_PAGE_SZ 0xFFF -#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ) -#define BIT_GET_SETTING_I2S_PAGE_SZ(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ) - -#define BIT_SHIFT_SETTING_I2S_PAGE_NUM 12 -#define BIT_MASK_SETTING_I2S_PAGE_NUM 0x3 -#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM) -#define BIT_GET_SETTING_I2S_PAGE_NUM(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM) - -#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE 14 -#define BIT_MASK_SETTING_I2S_SAMPLE_RATE 0x7 -#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) -#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) - -// i2s trx page own bit -#define BIT_PAGE_I2S_OWN_BIT BIT(31) -#define BIT_SHIFT_PAGE_I2S_OWN_BIT 31 -#define BIT_MASK_PAGE_I2S_OWN_BIT 0x1 -#define BIT_CTRL_PAGE_I2S_OWN_BIT(x) (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT) - -//=============== Register Address Definition ==================== -#define REG_I2S_PAGE_OWN_OFF 0x004 - -#define REG_I2S_CTL 0x000 -#define REG_I2S_TX_PAGE_PTR 0x004 -#define REG_I2S_RX_PAGE_PTR 0x008 -#define REG_I2S_SETTING 0x00C - -#define REG_I2S_TX_MASK_INT 0x010 -#define REG_I2S_TX_STATUS_INT 0x014 -#define REG_I2S_RX_MASK_INT 0x018 -#define REG_I2S_RX_STATUS_INT 0x01c - - -#define REG_I2S_TX_PAGE0_OWN 0x020 -#define REG_I2S_TX_PAGE1_OWN 0x024 -#define REG_I2S_TX_PAGE2_OWN 0x028 -#define REG_I2S_TX_PAGE3_OWN 0x02C -#define REG_I2S_RX_PAGE0_OWN 0x030 -#define REG_I2S_RX_PAGE1_OWN 0x034 -#define REG_I2S_RX_PAGE2_OWN 0x038 -#define REG_I2S_RX_PAGE3_OWN 0x03C - -/*I2S Essential Functions and Macros*/ -VOID -HalI2SWrite32( - IN u8 I2SIdx, - IN u8 I2SReg, - IN u32 I2SVal -); - -u32 -HalI2SRead32( - IN u8 I2SIdx, - IN u8 I2SReg -); - -/* -#define HAL_I2SX_READ32(I2sIndex, addr) \ - HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr) -#define HAL_I2SX_WRITE32(I2sIndex, addr, value) \ - HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value) -*/ - -#define HAL_I2S_WRITE32(I2SIdx, addr, value) HalI2SWrite32(I2SIdx,addr,value) -#define HAL_I2S_READ32(I2SIdx, addr) HalI2SRead32(I2SIdx,addr) - -/* I2S debug output*/ -#define I2S_PREFIX "RTL8195A[i2s]: " -#define I2S_PREFIX_LVL " [i2s_DBG]: " - -typedef enum _I2S_DBG_LVL_ { - HAL_I2S_LVL = 0x01, - SAL_I2S_LVL = 0x02, - VERI_I2S_LVL = 0x03, -}I2S_DBG_LVL,*PI2S_DBG_LVL; - -#ifdef CONFIG_DEBUG_LOG -#ifdef CONFIG_DEBUG_LOG_I2S_HAL - - #define DBG_8195A_I2S(...) do{ \ - _DbgDump("\r"I2S_PREFIX __VA_ARGS__);\ - }while(0) - - - #define I2SDBGLVL 0xFF - #define DBG_8195A_I2S_LVL(LVL,...) do{\ - if (LVL&I2SDBGLVL){\ - _DbgDump("\r"I2S_PREFIX_LVL __VA_ARGS__);\ - }\ - }while(0) -#else - #define DBG_I2S_LOG_PERD 100 - #define DBG_8195A_I2S(...) - #define DBG_8195A_I2S_LVL(...) -#endif -#else - #define DBG_I2S_LOG_PERD 100 - #define DBG_8195A_I2S(...) - #define DBG_8195A_I2S_LVL(...) -#endif - -/* -#define REG_I2S_PAGE_OWN_OFF 0x004 -#define REG_I2S_CTL 0x000 -#define REG_I2S_TX_PAGE_PTR 0x004 -#define REG_I2S_RX_PAGE_PTR 0x008 -#define REG_I2S_SETTING 0x00C - -#define REG_I2S_TX_MASK_INT 0x010 -#define REG_I2S_TX_STATUS_INT 0x014 -#define REG_I2S_RX_MASK_INT 0x018 -#define REG_I2S_RX_STATUS_INT 0x01c - - - -#define REG_I2S_TX_PAGE0_OWN 0x020 -#define REG_I2S_TX_PAGE1_OWN 0x024 -#define REG_I2S_TX_PAGE2_OWN 0x028 -#define REG_I2S_TX_PAGE3_OWN 0x02C -#define REG_I2S_RX_PAGE0_OWN 0x030 -#define REG_I2S_RX_PAGE1_OWN 0x034 -#define REG_I2S_RX_PAGE2_OWN 0x038 -#define REG_I2S_RX_PAGE3_OWN 0x03C -*/ -/* template -#define BIT_SHIFT_CTLX_ 7 -#define BIT_MASK_CTLX_ 0x1 -#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_) -#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_)) -*//* -#define BIT_SHIFT_CTLX_IIS_EN 0 -#define BIT_MASK_CTLX_IIS_EN 0x1 -#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN) -#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN)) - -#define BIT_SHIFT_CTLX_TRX 1 -#define BIT_MASK_CTLX_TRX 0x3 -#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX) -#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX)) - -#define BIT_SHIFT_CTLX_CH_NUM 3 -#define BIT_MASK_CTLX_CH_NUM 0x3 -#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM) -#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM)) - -#define BIT_SHIFT_CTLX_EDGE_SW 5 -#define BIT_MASK_CTLX_EDGE_SW 0x1 -#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW) -#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW)) - -#define BIT_SHIFT_CTLX_WL 6 -#define BIT_MASK_CTLX_WL 0x1 -#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL) -#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL)) - -#define BIT_SHIFT_CTLX_LOOP_BACK 7 -#define BIT_MASK_CTLX_LOOP_BACK 0x1 -#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK) -#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK)) - - -#define BIT_SHIFT_CTLX_FORMAT 8 -#define BIT_MASK_CTLX_FORMAT 0x3 -#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT) -#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT)) - -#define BIT_SHIFT_CTLX_LRSWAP 10 -#define BIT_MASK_CTLX_LRSWAP 0x1 -#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP) -#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP)) - -#define BIT_SHIFT_CTLX_SCK_INV 11 -#define BIT_MASK_CTLX_SCK_INV 0x1 -#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV) -#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV)) - -#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12 -#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1 -#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP) -#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP)) - - -#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15 -#define BIT_MASK_CTLX_DEBUG_SWITCH 0x3 -#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH) -#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH)) - -#define BIT_SHIFT_CTLX_SLAVE_SEL 29 -#define BIT_MASK_CTLX_SLAVE_SEL 0x1 -#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL) -#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL)) - - -#define BIT_SHIFT_CTLX_CLK_SRC 30 -#define BIT_MASK_CTLX_CLK_SRC 0x1 -#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC) -#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC)) - - - -#define BIT_SHIFT_CTLX_SW_RSTN 31 -#define BIT_MASK_CTLX_SW_RSTN 0x1 -#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN) -#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN)) - - -#define BIT_SHIFT_SETTING_PAGE_SZ 0 -#define BIT_MASK_SETTING_PAGE_SZ 0xFFF -#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ) -#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ)) - -#define BIT_SHIFT_SETTING_PAGE_NUM 12 -#define BIT_MASK_SETTING_PAGE_NUM 0x3 -#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM) -#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM)) - -#define BIT_SHIFT_SETTING_SAMPLE_RATE 14 -#define BIT_MASK_SETTING_SAMPLE_RATE 0x7 -#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE) -#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE)) -*/ - -typedef enum _I2S_CTL_FORMAT { - FormatI2s = 0x00, - FormatLeftJustified = 0x01, - FormatRightJustified = 0x02 -}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT; - -typedef enum _I2S_CTL_CHNUM { - ChannelStereo = 0x00, - Channel5p1 = 0x01, - ChannelMono = 0x02 -}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM; - -typedef enum _I2S_CTL_TRX_ACT { - RxOnly = 0x00, - TxOnly = 0x01, - TXRX = 0x02 -}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT; -/* -typedef struct _I2S_CTL_REG_ { - I2S_CTL_FORMAT Format; - I2S_CTL_CHNUM ChNum; - I2S_CTL_TRX_ACT TrxAct; - - u32 I2s_En :1; // Bit 0 - u32 Rsvd1to4 :4; // Bit 1-4 is TrxAct, ChNum - u32 EdgeSw :1; // Bit 5 Edge switch - u32 WordLength :1; // Bit 6 - u32 LoopBack :1; // Bit 7 - u32 Rsvd8to9 :2; // Bit 8-9 is Format - u32 DacLrSwap :1; // Bit 10 - u32 SckInv :1; // Bit 11 - u32 EndianSwap :1; // Bit 12 - u32 Rsvd13to14 :2; // Bit 11-14 - u32 DebugSwitch :2; // Bit 15-16 - u32 Rsvd17to28 :12; // Bit 17-28 - u32 SlaveMode :1; // Bit 29 - u32 SR44p1KHz :1; // Bit 30 - u32 SwRstn :1; // Bit 31 -} I2S_CTL_REG, *PI2S_CTL_REG; -*/ -typedef enum _I2S_SETTING_PAGE_NUM { - I2s1Page = 0x00, - I2s2Page = 0x01, - I2s3Page = 0x02, - I2s4Page = 0x03 -}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM; - -//sampling rate -typedef enum _I2S_SETTING_SR { - I2sSR8K = 0x00, - I2sSR16K = 0x01, - I2sSR24K = 0x02, - I2sSR32K = 0x03, - I2sSR48K = 0x05, - I2sSR44p1K = 0x15, - I2sSR96K = 0x06, - I2sSR88p2K = 0x16 -}I2S_SETTING_SR, *PI2S_SETTING_SR; -/* -typedef struct _I2S_SETTING_REG_ { - I2S_SETTING_PAGE_NUM PageNum; - I2S_SETTING_SR SampleRate; - - u32 PageSize:12; // Bit 0-11 -}I2S_SETTING_REG, *PI2S_SETTING_REG; - -typedef enum _I2S_TX_ISR { - I2sTxP0OK = 0x01, - I2sTxP1OK = 0x02, - I2sTxP2OK = 0x04, - I2sTxP3OK = 0x08, - I2sTxPageUn = 0x10, - I2sTxFifoEmpty = 0x20 -}I2S_TX_ISR, *PI2S_TX_ISR; - -typedef enum _I2S_RX_ISR { - I2sRxP0OK = 0x01, - I2sRxP1OK = 0x02, - I2sRxP2OK = 0x04, - I2sRxP3OK = 0x08, - I2sRxPageUn = 0x10, - I2sRxFifoFull = 0x20 -}I2S_RX_ISR, *PI2S_RX_ISR; -*/ - -/* Hal I2S function prototype*/ -RTK_STATUS -HalI2SInitRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SInitRtl8195a_Patch( - IN VOID *Data -); - -RTK_STATUS -HalI2SDeInitRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2STxRtl8195a( - IN VOID *Data, - IN u8 *pBuff -); - -RTK_STATUS -HalI2SRxRtl8195a( - IN VOID *Data, - OUT u8 *pBuff -); - -RTK_STATUS -HalI2SEnableRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SIntrCtrlRtl8195a( - IN VOID *Data -); - -u32 -HalI2SReadRegRtl8195a( - IN VOID *Data, - IN u8 I2SReg -); - -RTK_STATUS -HalI2SSetRateRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SSetWordLenRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SSetChNumRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SSetPageNumRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SSetPageSizeRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SSetDirectionRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SSetDMABufRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SClrIntrRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SClrAllIntrRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SDMACtrlRtl8195a( - IN VOID *Data -); - -u8 -HalI2SGetTxPageRtl8195a( - IN VOID *Data -); - -u8 -HalI2SGetRxPageRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SPageSendRtl8195a( - IN VOID *Data, - IN u8 PageIdx -); - -RTK_STATUS -HalI2SPageRecvRtl8195a( - IN VOID *Data -); - -RTK_STATUS -HalI2SClearAllOwnBitRtl8195a( - IN VOID *Data -); - -#ifdef CONFIG_CHIP_E_CUT -_LONG_CALL_ RTK_STATUS -HalI2SInitRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SSetRateRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SSetWordLenRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SSetChNumRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SSetPageNumRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SSetPageSizeRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SSetDirectionRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SSetDMABufRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ u8 -HalI2SGetTxPageRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ u8 -HalI2SGetRxPageRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SPageSendRtl8195a_V04( - IN VOID *Data, - IN u8 PageIdx -); - -_LONG_CALL_ RTK_STATUS -HalI2SPageRecvRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ RTK_STATUS -HalI2SClearAllOwnBitRtl8195a_V04( - IN VOID *Data -); - -#endif // #ifdef CONFIG_CHIP_E_CUT - -// HAL functions Wrapper -static __inline VOID -HalI2SSetRate( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SSetRateRtl8195a(Data); -#else - HalI2SSetRateRtl8195a_V04(Data); -#endif -} - -static __inline VOID -HalI2SSetWordLen( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SSetWordLenRtl8195a(Data); -#else - HalI2SSetWordLenRtl8195a_V04(Data); -#endif -} - -static __inline VOID -HalI2SSetChNum( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SSetChNumRtl8195a(Data); -#else - HalI2SSetChNumRtl8195a_V04(Data); -#endif -} - -static __inline VOID -HalI2SSetPageNum( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SSetPageNumRtl8195a(Data); -#else - HalI2SSetPageNumRtl8195a_V04(Data); -#endif -} - -static __inline VOID -HalI2SSetPageSize( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SSetPageSizeRtl8195a(Data); -#else - HalI2SSetPageSizeRtl8195a_V04(Data); -#endif -} - -static __inline VOID -HalI2SSetDirection( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SSetDirectionRtl8195a(Data); -#else - HalI2SSetDirectionRtl8195a_V04(Data); -#endif -} - -static __inline VOID -HalI2SSetDMABuf( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SSetDMABufRtl8195a(Data); -#else - HalI2SSetDMABufRtl8195a_V04(Data); -#endif -} - -static __inline u8 -HalI2SGetTxPage( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - return HalI2SGetTxPageRtl8195a(Data); -#else - return HalI2SGetTxPageRtl8195a_V04(Data); -#endif -} - -static __inline u8 -HalI2SGetRxPage( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - return HalI2SGetRxPageRtl8195a(Data); -#else - return HalI2SGetRxPageRtl8195a_V04(Data); -#endif -} - -static __inline VOID -HalI2SPageSend( - IN VOID *Data, - IN u8 PageIdx -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SPageSendRtl8195a(Data, PageIdx); -#else - HalI2SPageSendRtl8195a_V04(Data, PageIdx); -#endif -} - -static __inline VOID -HalI2SPageRecv( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SPageRecvRtl8195a(Data); -#else - HalI2SPageRecvRtl8195a_V04(Data); -#endif -} - -static __inline VOID -HalI2SClearAllOwnBit( - IN VOID *Data -) -{ -#ifndef CONFIG_CHIP_E_CUT - HalI2SClearAllOwnBitRtl8195a(Data); -#else - HalI2SClearAllOwnBitRtl8195a_V04(Data); -#endif -} - -#endif /* _RTL8195A_I2S_H_ */ - - diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h deleted file mode 100644 index a768b12eb2e..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h +++ /dev/null @@ -1,1263 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef __INC_RTL8195A_PERI_ON_H -#define __INC_RTL8195A_PERI_ON_H - -#define CPU_OPT_WIDTH 0x1F - -//2 REG_NOT_VALID - -//2 REG_PEON_PWR_CTRL -#define BIT_SOC_UAHV_EN BIT(2) -#define BIT_SOC_UALV_EN BIT(1) -#define BIT_SOC_USBD_EN BIT(0) - -//2 REG_PON_ISO_CTRL - -//2 REG_NOT_VALID -#define BIT_ISO_OSC32K_EN BIT(4) -//#define BIT_ISO_USBA_EN BIT(1) -//#define BIT_ISO_USBD_EN BIT(0) - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_SOC_FUNC_EN -#define BIT_SOC_SECURITY_ENGINE_EN BIT(20) -#define BIT_SOC_GTIMER_EN BIT(16) -#define BIT_SOC_GDMA1_EN BIT(14) -#define BIT_SOC_GDMA0_EN BIT(13) -#define BIT_SOC_LOG_UART_EN BIT(12) -#define BIT_SOC_CPU_EN BIT(8) -#define BIT_SOC_MEM_CTRL_EN BIT(6) -#define BIT_SOC_FLASH_EN BIT(4) -#define BIT_SOC_LXBUS_EN BIT(2) -#define BIT_SOC_OCP_EN BIT(1) -#define BiT_SOC_FUN_EN BIT(0) - -//2 REG_SOC_HCI_COM_FUNC_EN -#define BIT_SOC_HCI_WL_MACON_EN BIT(16) -#define BIT_SOC_HCI_SM_SEL BIT(13) -#define BIT_SOC_HCI_MII_EN BIT(12) -#define BIT_SOC_HCI_OTG_RST_MUX BIT(5) -#define BIT_SOC_HCI_OTG_EN BIT(4) -#define BIT_SOC_HCI_SDIOD_ON_RST_MUX BIT(3) -#define BIT_SOC_HCI_SDIOH_EN BIT(2) -#define BIT_SOC_HCI_SDIOD_OFF_EN BIT(1) -#define BIT_SOC_HCI_SDIOD_ON_EN BIT(0) - -//2 REG_SOC_PERI_FUNC0_EN -#define BIT_PERI_PCM1_EN BIT(29) -#define BIT_PERI_PCM0_EN BIT(28) -#define BIT_PERI_I2S1_EN BIT(25) -#define BIT_PERI_I2S0_EN BIT(24) -#define BIT_PERI_I2C3_EN BIT(19) -#define BIT_PERI_I2C2_EN BIT(18) -#define BIT_PERI_I2C1_EN BIT(17) -#define BIT_PERI_I2C0_EN BIT(16) -#define BIT_PERI_SPI2_EN BIT(10) -#define BIT_PERI_SPI1_EN BIT(9) -#define BIT_PERI_SPI0_EN BIT(8) -#define BIT_PERI_UART2_EN BIT(2) -#define BIT_PERI_UART1_EN BIT(1) -#define BIT_PERI_UART0_EN BIT(0) - -//2 REG_SOC_PERI_FUNC1_EN -#define BIT_PERI_GPIO_EN BIT(8) -#define BIT_PERI_DAC1_EN BIT(5) -#define BIT_PERI_DAC0_EN BIT(4) -#define BIT_PERI_ADC0_EN BIT(0) - -//2 REG_SOC_PERI_BD_FUNC0_EN -#define BIT_PERI_UART2_BD_EN BIT(2) -#define BIT_PERI_UART1_BD_EN BIT(1) -#define BIT_PERI_UART0_BD_EN BIT(0) - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_PESOC_CLK_CTRL -#define BIT_SOC_SLPCK_BTCMD_EN BIT(29) -#define BIT_SOC_ACTCK_BTCMD_EN BIT(28) -#define BIT_SOC_SLPCK_GPIO_EN BIT(25) -#define BIT_SOC_ACTCK_GPIO_EN BIT(24) -#define BIT_SOC_SLPCK_GDMA1_EN BIT(19) -#define BIT_SOC_ACTCK_GDMA1_EN BIT(18) -#define BIT_SOC_SLPCK_GDMA0_EN BIT(17) -#define BIT_SOC_ACTCK_GDMA0_EN BIT(16) -#define BIT_SOC_SLPCK_TIMER_EN BIT(15) -#define BIT_SOC_ACTCK_TIMER_EN BIT(14) -#define BIT_SOC_SLPCK_LOG_UART_EN BIT(13) -#define BIT_SOC_ACTCK_LOG_UART_EN BIT(12) -#define BIT_SOC_SLPCK_SDR_EN BIT(11) -#define BIT_SOC_ACTCK_SDR_EN BIT(10) -#define BIT_SOC_SLPCK_FLASH_EN BIT(9) -#define BIT_SOC_ACTCK_FLASH_EN BIT(8) -#define BIT_SOC_SLPCK_VENDOR_REG_EN BIT(7) -#define BIT_SOC_ACTCK_VENDOR_REG_EN BIT(6) -#define BIT_SOC_SLPCK_TRACE_EN BIT(5) -#define BIT_SOC_ACTCK_TRACE_EN BIT(4) -#define BIT_SOC_CKE_PLFM BIT(2) -#define BIT_SOC_CKE_OCP BIT(0) - -//2 REG_PESOC_PERI_CLK_CTRL0 -#define BIT_SOC_SLPCK_SPI2_EN BIT(21) -#define BIT_SOC_ACTCK_SPI2_EN BIT(20) -#define BIT_SOC_SLPCK_SPI1_EN BIT(19) -#define BIT_SOC_ACTCK_SPI1_EN BIT(18) -#define BIT_SOC_SLPCK_SPI0_EN BIT(17) -#define BIT_SOC_ACTCK_SPI0_EN BIT(16) -#define BIT_SOC_SLPCK_UART2_EN BIT(5) -#define BIT_SOC_ACTCK_UART2_EN BIT(4) -#define BIT_SOC_SLPCK_UART1_EN BIT(3) -#define BIT_SOC_ACTCK_UART1_EN BIT(2) -#define BIT_SOC_SLPCK_UART0_EN BIT(1) -#define BIT_SOC_ACTCK_UART0_EN BIT(0) - -//2 REG_PESOC_PERI_CLK_CTRL1 -#define BIT_SOC_SLPCK_DAC_EN BIT(29) -#define BIT_SOC_ACTCK_DAC_EN BIT(28) -#define BIT_SOC_SLPCK_ADC_EN BIT(25) -#define BIT_SOC_ACTCK_ADC_EN BIT(24) -#define BIT_SOC_SLPCK_PCM_EN BIT(21) -#define BIT_SOC_ACTCK_PCM_EN BIT(20) -#define BIT_SOC_SLPCK_I2S_EN BIT(17) -#define BIT_SOC_ACTCK_I2S_EN BIT(16) -#define BIT_SOC_SLPCK_I2C3_EN BIT(7) -#define BIT_SOC_ACTCK_I2C3_EN BIT(6) -#define BIT_SOC_SLPCK_I2C2_EN BIT(5) -#define BIT_SOC_ACTCK_I2C2_EN BIT(4) -#define BIT_SOC_SLPCK_I2C1_EN BIT(3) -#define BIT_SOC_ACTCK_I2C1_EN BIT(2) -#define BIT_SOC_SLPCK_I2C0_EN BIT(1) -#define BIT_SOC_ACTCK_I2C0_EN BIT(0) - -//2 REG_PESOC_CLK_CTRL3 - -//2 REG_PESOC_HCI_CLK_CTRL0 -#define BIT_SOC_SLPCK_MII_MPHY_EN BIT(25) -#define BIT_SOC_ACTCK_MII_MPHY_EN BIT(24) -#define BIT_SOC_SLPCK_OTG_EN BIT(5) -#define BIT_SOC_ACTCK_OTG_EN BIT(4) -#define BIT_SOC_SLPCK_SDIO_HST_EN BIT(3) -#define BIT_SOC_ACTCK_SDIO_HST_EN BIT(2) -#define BIT_SOC_SLPCK_SDIO_DEV_EN BIT(1) -#define BIT_SOC_ACTCK_SDIO_DEV_EN BIT(0) - -//2 REG_PESOC_COM_CLK_CTRL1 -#define BIT_SOC_NFC_CAL_EN BIT(18) -#define BIT_SOC_SLPCK_NFC_EN BIT(17) -#define BIT_SOC_ACTCK_NFC_EN BIT(16) -#define BIT_SOC_SLPCK_SECURITY_ENG_EN BIT(5) -#define BIT_SOC_ACTCK_SECURITY_ENG_EN BIT(4) -#define BIT_SOC_SLPCK_WL_EN BIT(1) -#define BIT_SOC_ACTCK_WL_EN BIT(0) - -//2 REG_PESOC_HW_ENG_CLK_CTRL - -//2 REG_RSVD - -//2 REG_PESOC_CLK_SEL -#define BIT_PESOC_SPI1_SCLK_SEL BIT(18) - -#define BIT_SHIFT_PESOC_PERI_SCLK_SEL 16 -#define BIT_MASK_PESOC_PERI_SCLK_SEL 0x3 -#define BIT_PESOC_PERI_SCLK_SEL(x) (((x) & BIT_MASK_PESOC_PERI_SCLK_SEL) << BIT_SHIFT_PESOC_PERI_SCLK_SEL) - - -#define BIT_SHIFT_PESOC_SDR_CK_SEL 10 -#define BIT_MASK_PESOC_SDR_CK_SEL 0x3 -#define BIT_PESOC_SDR_CK_SEL(x) (((x) & BIT_MASK_PESOC_SDR_CK_SEL) << BIT_SHIFT_PESOC_SDR_CK_SEL) - - -#define BIT_SHIFT_PESOC_FLASH_CK_SEL 8 -#define BIT_MASK_PESOC_FLASH_CK_SEL 0x3 -#define BIT_PESOC_FLASH_CK_SEL(x) (((x) & BIT_MASK_PESOC_FLASH_CK_SEL) << BIT_SHIFT_PESOC_FLASH_CK_SEL) - - -#define BIT_SHIFT_PESOC_TRACE_CK_SEL 4 -#define BIT_MASK_PESOC_TRACE_CK_SEL 0x3 -#define BIT_PESOC_TRACE_CK_SEL(x) (((x) & BIT_MASK_PESOC_TRACE_CK_SEL) << BIT_SHIFT_PESOC_TRACE_CK_SEL) - - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_SYS_ANACK_CAL_CTRL -#define BIT_SYS_ANACK_CAL_CMD BIT(15) -#define BIT_SYS_ANACK_CAL_SEL BIT(14) - -#define BIT_SHIFT_SYS_ANACK_CAL_RPT 0 -#define BIT_MASK_SYS_ANACK_CAL_RPT 0x3fff -#define BIT_SYS_ANACK_CAL_RPT(x) (((x) & BIT_MASK_SYS_ANACK_CAL_RPT) << BIT_SHIFT_SYS_ANACK_CAL_RPT) - - -//2 REG_OSC32K_CTRL - -#define BIT_SHIFT_32K_BIAS_CURRENT 16 -#define BIT_MASK_32K_BIAS_CURRENT 0xffff -#define BIT_32K_BIAS_CURRENT(x) (((x) & BIT_MASK_32K_BIAS_CURRENT) << BIT_SHIFT_32K_BIAS_CURRENT) - - -#define BIT_SHIFT_32K_RESISTOR_COM 2 -#define BIT_MASK_32K_RESISTOR_COM 0x3 -#define BIT_32K_RESISTOR_COM(x) (((x) & BIT_MASK_32K_RESISTOR_COM) << BIT_SHIFT_32K_RESISTOR_COM) - -#define BIT_32K_DBG_SEL BIT(1) -#define BIT_32K_POW_CKGEN_EN BIT(0) - -//2 REG_OSC32K_REG_CTRL0 -#define BIT_32K_REG_INDIRT_CMD BIT(23) - -#define BIT_SHIFT_32K_REG_INDIRT_ADDR 16 -#define BIT_MASK_32K_REG_INDIRT_ADDR 0x3f -#define BIT_32K_REG_INDIRT_ADDR(x) (((x) & BIT_MASK_32K_REG_INDIRT_ADDR) << BIT_SHIFT_32K_REG_INDIRT_ADDR) - - -#define BIT_SHIFT_32K_REG_INDIRT_WDATA 0 -#define BIT_MASK_32K_REG_INDIRT_WDATA 0xffff -#define BIT_32K_REG_INDIRT_WDATA(x) (((x) & BIT_MASK_32K_REG_INDIRT_WDATA) << BIT_SHIFT_32K_REG_INDIRT_WDATA) - - -//2 REG_OSC32K_REG_CTRL1 - -#define BIT_SHIFT_32K_REG_INDIRT_RDATA 0 -#define BIT_MASK_32K_REG_INDIRT_RDATA 0xffff -#define BIT_32K_REG_INDIRT_RDATA(x) (((x) & BIT_MASK_32K_REG_INDIRT_RDATA) << BIT_SHIFT_32K_REG_INDIRT_RDATA) - - -//2 REG_THERMAL_METER_CTRL - -#define BIT_SHIFT_TEMP_VALUE 24 -#define BIT_MASK_TEMP_VALUE 0x3f -#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) - - -#define BIT_SHIFT_TEMP_DELTA 16 -#define BIT_MASK_TEMP_DELTA 0x3f -#define BIT_TEMP_DELTA(x) (((x) & BIT_MASK_TEMP_DELTA) << BIT_SHIFT_TEMP_DELTA) - -#define BIT_THERMAL_METER_EN BIT(15) -#define BIT_THERMAL_METER_VALID BIT(14) - -#define BIT_SHIFT_THERMAL_METER_TIMER 0 -#define BIT_MASK_THERMAL_METER_TIMER 0xfff -#define BIT_THERMAL_METER_TIMER(x) (((x) & BIT_MASK_THERMAL_METER_TIMER) << BIT_SHIFT_THERMAL_METER_TIMER) - - -//2 REG_UART_MUX_CTRL - -#define BIT_SHIFT_UART2_PIN_SEL 9 -#define BIT_MASK_UART2_PIN_SEL 0x7 -#define BIT_UART2_PIN_SEL(x) (((x) & BIT_MASK_UART2_PIN_SEL) << BIT_SHIFT_UART2_PIN_SEL) - -#define BIT_UART2_PIN_EN BIT(8) - -#define BIT_SHIFT_UART1_PIN_SEL 5 -#define BIT_MASK_UART1_PIN_SEL 0x7 -#define BIT_UART1_PIN_SEL(x) (((x) & BIT_MASK_UART1_PIN_SEL) << BIT_SHIFT_UART1_PIN_SEL) - -#define BIT_UART1_PIN_EN BIT(4) - -#define BIT_SHIFT_UART0_PIN_SEL 1 -#define BIT_MASK_UART0_PIN_SEL 0x7 -#define BIT_UART0_PIN_SEL(x) (((x) & BIT_MASK_UART0_PIN_SEL) << BIT_SHIFT_UART0_PIN_SEL) - -#define BIT_UART0_PIN_EN BIT(0) - -//2 REG_SPI_MUX_CTRL -#define BIT_SPI0_MULTI_CS_EN BIT(28) - -#define BIT_SHIFT_SPI2_PIN_SEL 9 -#define BIT_MASK_SPI2_PIN_SEL 0x7 -#define BIT_SPI2_PIN_SEL(x) (((x) & BIT_MASK_SPI2_PIN_SEL) << BIT_SHIFT_SPI2_PIN_SEL) - -#define BIT_SPI2_PIN_EN BIT(8) - -#define BIT_SHIFT_SPI1_PIN_SEL 5 -#define BIT_MASK_SPI1_PIN_SEL 0x7 -#define BIT_SPI1_PIN_SEL(x) (((x) & BIT_MASK_SPI1_PIN_SEL) << BIT_SHIFT_SPI1_PIN_SEL) - -#define BIT_SPI1_PIN_EN BIT(4) - -#define BIT_SHIFT_SPI0_PIN_SEL 1 -#define BIT_MASK_SPI0_PIN_SEL 0x7 -#define BIT_SPI0_PIN_SEL(x) (((x) & BIT_MASK_SPI0_PIN_SEL) << BIT_SHIFT_SPI0_PIN_SEL) - -#define BIT_SPI0_PIN_EN BIT(0) - -//2 REG_I2C_MUX_CTRL - -#define BIT_SHIFT_I2C3_PIN_SEL 13 -#define BIT_MASK_I2C3_PIN_SEL 0x7 -#define BIT_I2C3_PIN_SEL(x) (((x) & BIT_MASK_I2C3_PIN_SEL) << BIT_SHIFT_I2C3_PIN_SEL) - -#define BIT_I2C3_PIN_EN BIT(12) - -#define BIT_SHIFT_I2C2_PIN_SEL 9 -#define BIT_MASK_I2C2_PIN_SEL 0x7 -#define BIT_I2C2_PIN_SEL(x) (((x) & BIT_MASK_I2C2_PIN_SEL) << BIT_SHIFT_I2C2_PIN_SEL) - -#define BIT_I2C2_PIN_EN BIT(8) - -#define BIT_SHIFT_I2C1_PIN_SEL 5 -#define BIT_MASK_I2C1_PIN_SEL 0x7 -#define BIT_I2C1_PIN_SEL(x) (((x) & BIT_MASK_I2C1_PIN_SEL) << BIT_SHIFT_I2C1_PIN_SEL) - -#define BIT_I2C1_PIN_EN BIT(4) - -#define BIT_SHIFT_I2C0_PIN_SEL 1 -#define BIT_MASK_I2C0_PIN_SEL 0x7 -#define BIT_I2C0_PIN_SEL(x) (((x) & BIT_MASK_I2C0_PIN_SEL) << BIT_SHIFT_I2C0_PIN_SEL) - -#define BIT_I2C0_PIN_EN BIT(0) - -//2 REG_I2S_MUX_CTRL/ REG_PCM_MUX_CTRL - -//2 REG_NOT_VALID - -#define BIT_SHIFT_PCM1_PIN_SEL 21 -#define BIT_MASK_PCM1_PIN_SEL 0x7 -#define BIT_PCM1_PIN_SEL(x) (((x) & BIT_MASK_PCM1_PIN_SEL) << BIT_SHIFT_PCM1_PIN_SEL) - -#define BIT_PCM1_PIN_EN BIT(20) - -#define BIT_SHIFT_PCM0_PIN_SEL 17 -#define BIT_MASK_PCM0_PIN_SEL 0x7 -#define BIT_PCM0_PIN_SEL(x) (((x) & BIT_MASK_PCM0_PIN_SEL) << BIT_SHIFT_PCM0_PIN_SEL) - -#define BIT_PCM0_PIN_EN BIT(16) - -//2 REG_NOT_VALID - -#define BIT_SHIFT_I2S1_PIN_SEL 6 -#define BIT_MASK_I2S1_PIN_SEL 0x3 -#define BIT_I2S1_PIN_SEL(x) (((x) & BIT_MASK_I2S1_PIN_SEL) << BIT_SHIFT_I2S1_PIN_SEL) - -#define BIT_I2S1_MCK_EN BIT(5) -#define BIT_I2S1_PIN_EN BIT(4) - -#define BIT_SHIFT_I2S0_PIN_SEL 2 -#define BIT_MASK_I2S0_PIN_SEL 0x3 -#define BIT_I2S0_PIN_SEL(x) (((x) & BIT_MASK_I2S0_PIN_SEL) << BIT_SHIFT_I2S0_PIN_SEL) - -#define BIT_I2S0_MCK_EN BIT(1) -#define BIT_I2S0_PIN_EN BIT(0) - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_HCI_PINMUX_CTRL -#define BIT_HCI_MII_PIN_EN BIT(24) -#define BIT_HCI_SDIOH_PIN_EN BIT(1) -#define BIT_HCI_SDIOD_PIN_EN BIT(0) - -//2 REG_WL_PINMUX_CTRL -#define BIT_NFC_PIN_EN BIT(16) -#define BIT_WL_BTCMD_PIN_EN BIT(13) -#define BIT_WL_BTCOEX_PIN_EN BIT(12) -#define BIT_WL_ANT1_PIN_EN BIT(9) -#define BIT_WL_ANT0_PIN_EN BIT(8) - -#define BIT_SHIFT_WL_LED_PIN_SEL 1 -#define BIT_MASK_WL_LED_PIN_SEL 0x3 -#define BIT_WL_LED_PIN_SEL(x) (((x) & BIT_MASK_WL_LED_PIN_SEL) << BIT_SHIFT_WL_LED_PIN_SEL) - -#define BIT_WL_LED_PIN_EN BIT(0) - -//2 REG_BT_PINMUX_CTRL - -//2 REG_PWM_PINMUX_CTRL - -#define BIT_SHIFT_ETE3_PIN_SEL 29 -#define BIT_MASK_ETE3_PIN_SEL 0x3 -#define BIT_ETE3_PIN_SEL(x) (((x) & BIT_MASK_ETE3_PIN_SEL) << BIT_SHIFT_ETE3_PIN_SEL) - -#define BIT_ETE3_PIN_EN BIT(28) - -#define BIT_SHIFT_ETE2_PIN_SEL 25 -#define BIT_MASK_ETE2_PIN_SEL 0x3 -#define BIT_ETE2_PIN_SEL(x) (((x) & BIT_MASK_ETE2_PIN_SEL) << BIT_SHIFT_ETE2_PIN_SEL) - -#define BIT_ETE2_PIN_EN BIT(24) - -#define BIT_SHIFT_ETE1_PIN_SEL 21 -#define BIT_MASK_ETE1_PIN_SEL 0x3 -#define BIT_ETE1_PIN_SEL(x) (((x) & BIT_MASK_ETE1_PIN_SEL) << BIT_SHIFT_ETE1_PIN_SEL) - -#define BIT_ETE1_PIN_EN BIT(20) - -#define BIT_SHIFT_ETE0_PIN_SEL 17 -#define BIT_MASK_ETE0_PIN_SEL 0x3 -#define BIT_ETE0_PIN_SEL(x) (((x) & BIT_MASK_ETE0_PIN_SEL) << BIT_SHIFT_ETE0_PIN_SEL) - -#define BIT_ETE0_PIN_EN BIT(16) - -#define BIT_SHIFT_PWM3_PIN_SEL 13 -#define BIT_MASK_PWM3_PIN_SEL 0x3 -#define BIT_PWM3_PIN_SEL(x) (((x) & BIT_MASK_PWM3_PIN_SEL) << BIT_SHIFT_PWM3_PIN_SEL) - -#define BIT_PWM3_PIN_EN BIT(12) - -#define BIT_SHIFT_PWM2_PIN_SEL 9 -#define BIT_MASK_PWM2_PIN_SEL 0x3 -#define BIT_PWM2_PIN_SEL(x) (((x) & BIT_MASK_PWM2_PIN_SEL) << BIT_SHIFT_PWM2_PIN_SEL) - -#define BIT_PWM2_PIN_EN BIT(8) - -#define BIT_SHIFT_PWM1_PIN_SEL 5 -#define BIT_MASK_PWM1_PIN_SEL 0x3 -#define BIT_PWM1_PIN_SEL(x) (((x) & BIT_MASK_PWM1_PIN_SEL) << BIT_SHIFT_PWM1_PIN_SEL) - -#define BIT_PWM1_PIN_EN BIT(4) - -#define BIT_SHIFT_PWM0_PIN_SEL 1 -#define BIT_MASK_PWM0_PIN_SEL 0x3 -#define BIT_PWM0_PIN_SEL(x) (((x) & BIT_MASK_PWM0_PIN_SEL) << BIT_SHIFT_PWM0_PIN_SEL) - -#define BIT_PWM0_PIN_EN BIT(0) - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_CPU_PERIPHERAL_CTRL - -#define BIT_SHIFT_LOG_UART_PIN_SEL 22 -#define BIT_MASK_LOG_UART_PIN_SEL 0x3 -#define BIT_LOG_UART_PIN_SEL(x) (((x) & BIT_MASK_LOG_UART_PIN_SEL) << BIT_SHIFT_LOG_UART_PIN_SEL) - -#define BIT_LOG_UART_IR_EN BIT(21) -#define BIT_LOG_UART_PIN_EN BIT(20) -#define BIT_TRACE_PIN_EN BIT(17) -#define BIT_SDR_PIN_EN BIT(4) - -#define BIT_SHIFT_SPI_FLSH_PIN_SEL 1 -#define BIT_MASK_SPI_FLSH_PIN_SEL 0x3 -#define BIT_SPI_FLSH_PIN_SEL(x) (((x) & BIT_MASK_SPI_FLSH_PIN_SEL) << BIT_SHIFT_SPI_FLSH_PIN_SEL) - -#define BIT_SPI_FLSH_PIN_EN BIT(0) - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_HCI_CTRL_STATUS_0 - -//2 REG_HCI_CTRL_STATUS_1 - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_PESOC_MEM_CTRL - -#define BIT_SHIFT_PESOC_SDR_DDL_CTRL 16 -#define BIT_MASK_PESOC_SDR_DDL_CTRL 0xff -#define BIT_PESOC_SDR_DDL_CTRL(x) (((x) & BIT_MASK_PESOC_SDR_DDL_CTRL) << BIT_SHIFT_PESOC_SDR_DDL_CTRL) - - -#define BIT_SHIFT_PESOC_FLASH_DDL_CTRL 0 -#define BIT_MASK_PESOC_FLASH_DDL_CTRL 0xff -#define BIT_PESOC_FLASH_DDL_CTRL(x) (((x) & BIT_MASK_PESOC_FLASH_DDL_CTRL) << BIT_SHIFT_PESOC_FLASH_DDL_CTRL) - - -//2 REG_PESOC_SOC_CTRL - -#define BIT_SHIFT_PESOC_GDMA_CFG 16 -#define BIT_MASK_PESOC_GDMA_CFG 0x1fff -#define BIT_PESOC_GDMA_CFG(x) (((x) & BIT_MASK_PESOC_GDMA_CFG) << BIT_SHIFT_PESOC_GDMA_CFG) - -#define BIT_PESOC_MII_LX_SLV_SWAP_SEL BIT(13) -#define BIT_PESOC_MII_LX_MST_SWAP_SEL BIT(12) -#define BIT_PESOC_MII_LX_WRAPPER_EN BIT(11) -#define BIT_PESOC_LX_SLV_SWAP_SEL BIT(10) -#define BIT_PESOC_LX_MST_SWAP_SEL BIT(9) -#define BIT_PESOC_LX_WL_SWAP_SEL BIT(8) - -#define BIT_SHIFT_PESOC_SRAM_MUX_CFG 0 -#define BIT_MASK_PESOC_SRAM_MUX_CFG 0x7 -#define BIT_PESOC_SRAM_MUX_CFG(x) (((x) & BIT_MASK_PESOC_SRAM_MUX_CFG) << BIT_SHIFT_PESOC_SRAM_MUX_CFG) - - -//2 REG_PESOC_PERI_CTRL -#define BIT_SOC_FUNC_SPI_RN BIT(8) - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID -#define BIT_FW_CTRL_INT0 BIT(24) - -//2 REG_NOT_VALID - -//2 REG_GPIO_SHTDN_CTRL -#define BIT_GPIO_GPK_SHTDN_N BIT(10) -#define BIT_GPIO_GPJ_SHTDN_N BIT(9) -#define BIT_GPIO_GPI_SHTDN_N BIT(8) -#define BIT_GPIO_GPH_SHTDN_N BIT(7) -#define BIT_GPIO_GPG_SHTDN_N BIT(6) -#define BIT_GPIO_GPF_SHTDN_N BIT(5) -#define BIT_GPIO_GPE_SHTDN_N BIT(4) -#define BIT_GPIO_GPD_SHTDN_N BIT(3) -#define BIT_GPIO_GPC_SHTDN_N BIT(2) -#define BIT_GPIO_GPB_SHTDN_N BIT(1) -#define BIT_GPIO_GPA_SHTDN_N BIT(0) - -//2 REG_GPIO_DRIVING_CTRL -#define BIT_GPIO_GPK_DRV_SEL BIT(20) -#define BIT_GPIO_GPJ_DRV_SEL BIT(18) -#define BIT_GPIO_GPI_DRV_SEL BIT(16) -#define BIT_GPIO_GPH_DRV_SEL BIT(14) -#define BIT_GPIO_GPG_DRV_SEL BIT(12) -#define BIT_GPIO_GPF_DRV_SEL BIT(10) -#define BIT_GPIO_GPE_DRV_SEL BIT(8) -#define BIT_GPIO_GPD_DRV_SEL BIT(6) -#define BIT_GPIO_GPC_DRV_SEL BIT(4) -#define BIT_GPIO_GPB_DRV_SEL BIT(2) -#define BIT_GPIO_GPA_DRV_SEL BIT(0) - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_GPIO_PULL_CTRL0 - -#define BIT_SHIFT_GPIO_GPB7_PULL_CTRL 30 -#define BIT_MASK_GPIO_GPB7_PULL_CTRL 0x3 -#define BIT_GPIO_GPB7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB7_PULL_CTRL) << BIT_SHIFT_GPIO_GPB7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPB6_PULL_CTRL 28 -#define BIT_MASK_GPIO_GPB6_PULL_CTRL 0x3 -#define BIT_GPIO_GPB6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB6_PULL_CTRL) << BIT_SHIFT_GPIO_GPB6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPB5_PULL_CTRL 26 -#define BIT_MASK_GPIO_GPB5_PULL_CTRL 0x3 -#define BIT_GPIO_GPB5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB5_PULL_CTRL) << BIT_SHIFT_GPIO_GPB5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPB4_PULL_CTRL 24 -#define BIT_MASK_GPIO_GPB4_PULL_CTRL 0x3 -#define BIT_GPIO_GPB4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB4_PULL_CTRL) << BIT_SHIFT_GPIO_GPB4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPB3_PULL_CTRL 22 -#define BIT_MASK_GPIO_GPB3_PULL_CTRL 0x3 -#define BIT_GPIO_GPB3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB3_PULL_CTRL) << BIT_SHIFT_GPIO_GPB3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPB2_PULL_CTRL 20 -#define BIT_MASK_GPIO_GPB2_PULL_CTRL 0x3 -#define BIT_GPIO_GPB2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB2_PULL_CTRL) << BIT_SHIFT_GPIO_GPB2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPB1_PULL_CTRL 18 -#define BIT_MASK_GPIO_GPB1_PULL_CTRL 0x3 -#define BIT_GPIO_GPB1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB1_PULL_CTRL) << BIT_SHIFT_GPIO_GPB1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPB0_PULL_CTRL 16 -#define BIT_MASK_GPIO_GPB0_PULL_CTRL 0x3 -#define BIT_GPIO_GPB0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB0_PULL_CTRL) << BIT_SHIFT_GPIO_GPB0_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPA7_PULL_CTRL 14 -#define BIT_MASK_GPIO_GPA7_PULL_CTRL 0x3 -#define BIT_GPIO_GPA7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA7_PULL_CTRL) << BIT_SHIFT_GPIO_GPA7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPA6_PULL_CTRL 12 -#define BIT_MASK_GPIO_GPA6_PULL_CTRL 0x3 -#define BIT_GPIO_GPA6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA6_PULL_CTRL) << BIT_SHIFT_GPIO_GPA6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPA5_PULL_CTRL 10 -#define BIT_MASK_GPIO_GPA5_PULL_CTRL 0x3 -#define BIT_GPIO_GPA5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA5_PULL_CTRL) << BIT_SHIFT_GPIO_GPA5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPA4_PULL_CTRL 8 -#define BIT_MASK_GPIO_GPA4_PULL_CTRL 0x3 -#define BIT_GPIO_GPA4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA4_PULL_CTRL) << BIT_SHIFT_GPIO_GPA4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPA3_PULL_CTRL 6 -#define BIT_MASK_GPIO_GPA3_PULL_CTRL 0x3 -#define BIT_GPIO_GPA3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA3_PULL_CTRL) << BIT_SHIFT_GPIO_GPA3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPA2_PULL_CTRL 4 -#define BIT_MASK_GPIO_GPA2_PULL_CTRL 0x3 -#define BIT_GPIO_GPA2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA2_PULL_CTRL) << BIT_SHIFT_GPIO_GPA2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPA1_PULL_CTRL 2 -#define BIT_MASK_GPIO_GPA1_PULL_CTRL 0x3 -#define BIT_GPIO_GPA1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA1_PULL_CTRL) << BIT_SHIFT_GPIO_GPA1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPA0_PULL_CTRL 0 -#define BIT_MASK_GPIO_GPA0_PULL_CTRL 0x3 -#define BIT_GPIO_GPA0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA0_PULL_CTRL) << BIT_SHIFT_GPIO_GPA0_PULL_CTRL) - - -//2 REG_GPIO_PULL_CTRL1 - -#define BIT_SHIFT_GPIO_GPD7_PULL_CTRL 29 -#define BIT_MASK_GPIO_GPD7_PULL_CTRL 0x7 -#define BIT_GPIO_GPD7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD7_PULL_CTRL) << BIT_SHIFT_GPIO_GPD7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPD6_PULL_CTRL 28 -#define BIT_MASK_GPIO_GPD6_PULL_CTRL 0x3 -#define BIT_GPIO_GPD6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD6_PULL_CTRL) << BIT_SHIFT_GPIO_GPD6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPD5_PULL_CTRL 26 -#define BIT_MASK_GPIO_GPD5_PULL_CTRL 0x3 -#define BIT_GPIO_GPD5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD5_PULL_CTRL) << BIT_SHIFT_GPIO_GPD5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPD4_PULL_CTRL 24 -#define BIT_MASK_GPIO_GPD4_PULL_CTRL 0x3 -#define BIT_GPIO_GPD4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD4_PULL_CTRL) << BIT_SHIFT_GPIO_GPD4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPD3_PULL_CTRL 22 -#define BIT_MASK_GPIO_GPD3_PULL_CTRL 0x3 -#define BIT_GPIO_GPD3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD3_PULL_CTRL) << BIT_SHIFT_GPIO_GPD3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPD2_PULL_CTRL 20 -#define BIT_MASK_GPIO_GPD2_PULL_CTRL 0x3 -#define BIT_GPIO_GPD2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD2_PULL_CTRL) << BIT_SHIFT_GPIO_GPD2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPD1_PULL_CTRL 18 -#define BIT_MASK_GPIO_GPD1_PULL_CTRL 0x3 -#define BIT_GPIO_GPD1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD1_PULL_CTRL) << BIT_SHIFT_GPIO_GPD1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPD0_PULL_CTRL 16 -#define BIT_MASK_GPIO_GPD0_PULL_CTRL 0x3 -#define BIT_GPIO_GPD0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD0_PULL_CTRL) << BIT_SHIFT_GPIO_GPD0_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC7_PULL_CTRL 14 -#define BIT_MASK_GPIO_GPC7_PULL_CTRL 0x3 -#define BIT_GPIO_GPC7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC7_PULL_CTRL) << BIT_SHIFT_GPIO_GPC7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC6_PULL_CTRL 12 -#define BIT_MASK_GPIO_GPC6_PULL_CTRL 0x3 -#define BIT_GPIO_GPC6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC6_PULL_CTRL) << BIT_SHIFT_GPIO_GPC6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC5_PULL_CTRL 10 -#define BIT_MASK_GPIO_GPC5_PULL_CTRL 0x3 -#define BIT_GPIO_GPC5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC5_PULL_CTRL) << BIT_SHIFT_GPIO_GPC5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC4_PULL_CTRL 8 -#define BIT_MASK_GPIO_GPC4_PULL_CTRL 0x3 -#define BIT_GPIO_GPC4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC4_PULL_CTRL) << BIT_SHIFT_GPIO_GPC4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC3_PULL_CTRL 6 -#define BIT_MASK_GPIO_GPC3_PULL_CTRL 0x3 -#define BIT_GPIO_GPC3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC3_PULL_CTRL) << BIT_SHIFT_GPIO_GPC3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC2_PULL_CTRL 4 -#define BIT_MASK_GPIO_GPC2_PULL_CTRL 0x3 -#define BIT_GPIO_GPC2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC2_PULL_CTRL) << BIT_SHIFT_GPIO_GPC2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC1_PULL_CTRL 2 -#define BIT_MASK_GPIO_GPC1_PULL_CTRL 0x3 -#define BIT_GPIO_GPC1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC1_PULL_CTRL) << BIT_SHIFT_GPIO_GPC1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC0_PULL_CTRL 0 -#define BIT_MASK_GPIO_GPC0_PULL_CTRL 0x3 -#define BIT_GPIO_GPC0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC0_PULL_CTRL) << BIT_SHIFT_GPIO_GPC0_PULL_CTRL) - - -//2 REG_GPIO_PULL_CTRL2 - -#define BIT_SHIFT_GPIO_GPF5_PULL_CTRL 26 -#define BIT_MASK_GPIO_GPF5_PULL_CTRL 0x3 -#define BIT_GPIO_GPF5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF5_PULL_CTRL) << BIT_SHIFT_GPIO_GPF5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPF4_PULL_CTRL 24 -#define BIT_MASK_GPIO_GPF4_PULL_CTRL 0x3 -#define BIT_GPIO_GPF4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF4_PULL_CTRL) << BIT_SHIFT_GPIO_GPF4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPF3_PULL_CTRL 22 -#define BIT_MASK_GPIO_GPF3_PULL_CTRL 0x3 -#define BIT_GPIO_GPF3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF3_PULL_CTRL) << BIT_SHIFT_GPIO_GPF3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPF2_PULL_CTRL 20 -#define BIT_MASK_GPIO_GPF2_PULL_CTRL 0x3 -#define BIT_GPIO_GPF2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF2_PULL_CTRL) << BIT_SHIFT_GPIO_GPF2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPF1_PULL_CTRL 18 -#define BIT_MASK_GPIO_GPF1_PULL_CTRL 0x3 -#define BIT_GPIO_GPF1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF1_PULL_CTRL) << BIT_SHIFT_GPIO_GPF1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPF0_PULL_CTRL 16 -#define BIT_MASK_GPIO_GPF0_PULL_CTRL 0x3 -#define BIT_GPIO_GPF0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF0_PULL_CTRL) << BIT_SHIFT_GPIO_GPF0_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE7_PULL_CTRL 14 -#define BIT_MASK_GPIO_GPE7_PULL_CTRL 0x3 -#define BIT_GPIO_GPE7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE7_PULL_CTRL) << BIT_SHIFT_GPIO_GPE7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE6_PULL_CTRL 12 -#define BIT_MASK_GPIO_GPE6_PULL_CTRL 0x3 -#define BIT_GPIO_GPE6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE6_PULL_CTRL) << BIT_SHIFT_GPIO_GPE6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE5_PULL_CTRL 10 -#define BIT_MASK_GPIO_GPE5_PULL_CTRL 0x3 -#define BIT_GPIO_GPE5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE5_PULL_CTRL) << BIT_SHIFT_GPIO_GPE5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE4_PULL_CTRL 8 -#define BIT_MASK_GPIO_GPE4_PULL_CTRL 0x3 -#define BIT_GPIO_GPE4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE4_PULL_CTRL) << BIT_SHIFT_GPIO_GPE4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE3_PULL_CTRL 6 -#define BIT_MASK_GPIO_GPE3_PULL_CTRL 0x3 -#define BIT_GPIO_GPE3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE3_PULL_CTRL) << BIT_SHIFT_GPIO_GPE3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE2_PULL_CTRL 4 -#define BIT_MASK_GPIO_GPE2_PULL_CTRL 0x3 -#define BIT_GPIO_GPE2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE2_PULL_CTRL) << BIT_SHIFT_GPIO_GPE2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE1_PULL_CTRL 2 -#define BIT_MASK_GPIO_GPE1_PULL_CTRL 0x3 -#define BIT_GPIO_GPE1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE1_PULL_CTRL) << BIT_SHIFT_GPIO_GPE1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE0_PULL_CTRL 0 -#define BIT_MASK_GPIO_GPE0_PULL_CTRL 0x3 -#define BIT_GPIO_GPE0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE0_PULL_CTRL) << BIT_SHIFT_GPIO_GPE0_PULL_CTRL) - - -//2 REG_NOT_VALID - -#define BIT_SHIFT_GPIO_GPH7_PULL_CTRL 30 -#define BIT_MASK_GPIO_GPH7_PULL_CTRL 0x3 -#define BIT_GPIO_GPH7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH7_PULL_CTRL) << BIT_SHIFT_GPIO_GPH7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPH6_PULL_CTRL 28 -#define BIT_MASK_GPIO_GPH6_PULL_CTRL 0x3 -#define BIT_GPIO_GPH6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH6_PULL_CTRL) << BIT_SHIFT_GPIO_GPH6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPH5_PULL_CTRL 26 -#define BIT_MASK_GPIO_GPH5_PULL_CTRL 0x3 -#define BIT_GPIO_GPH5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH5_PULL_CTRL) << BIT_SHIFT_GPIO_GPH5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPH4_PULL_CTRL 24 -#define BIT_MASK_GPIO_GPH4_PULL_CTRL 0x3 -#define BIT_GPIO_GPH4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH4_PULL_CTRL) << BIT_SHIFT_GPIO_GPH4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPH3_PULL_CTRL 22 -#define BIT_MASK_GPIO_GPH3_PULL_CTRL 0x3 -#define BIT_GPIO_GPH3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH3_PULL_CTRL) << BIT_SHIFT_GPIO_GPH3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPH2_PULL_CTRL 20 -#define BIT_MASK_GPIO_GPH2_PULL_CTRL 0x3 -#define BIT_GPIO_GPH2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH2_PULL_CTRL) << BIT_SHIFT_GPIO_GPH2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPH1_PULL_CTRL 18 -#define BIT_MASK_GPIO_GPH1_PULL_CTRL 0x3 -#define BIT_GPIO_GPH1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH1_PULL_CTRL) << BIT_SHIFT_GPIO_GPH1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPH0_PULL_CTRL 16 -#define BIT_MASK_GPIO_GPH0_PULL_CTRL 0x3 -#define BIT_GPIO_GPH0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH0_PULL_CTRL) << BIT_SHIFT_GPIO_GPH0_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPG7_PULL_CTRL 14 -#define BIT_MASK_GPIO_GPG7_PULL_CTRL 0x3 -#define BIT_GPIO_GPG7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG7_PULL_CTRL) << BIT_SHIFT_GPIO_GPG7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPG6_PULL_CTRL 12 -#define BIT_MASK_GPIO_GPG6_PULL_CTRL 0x3 -#define BIT_GPIO_GPG6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG6_PULL_CTRL) << BIT_SHIFT_GPIO_GPG6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPG5_PULL_CTRL 10 -#define BIT_MASK_GPIO_GPG5_PULL_CTRL 0x3 -#define BIT_GPIO_GPG5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG5_PULL_CTRL) << BIT_SHIFT_GPIO_GPG5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPG4_PULL_CTRL 8 -#define BIT_MASK_GPIO_GPG4_PULL_CTRL 0x3 -#define BIT_GPIO_GPG4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG4_PULL_CTRL) << BIT_SHIFT_GPIO_GPG4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPG3_PULL_CTRL 6 -#define BIT_MASK_GPIO_GPG3_PULL_CTRL 0x3 -#define BIT_GPIO_GPG3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG3_PULL_CTRL) << BIT_SHIFT_GPIO_GPG3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPG2_PULL_CTRL 4 -#define BIT_MASK_GPIO_GPG2_PULL_CTRL 0x3 -#define BIT_GPIO_GPG2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG2_PULL_CTRL) << BIT_SHIFT_GPIO_GPG2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPG1_PULL_CTRL 2 -#define BIT_MASK_GPIO_GPG1_PULL_CTRL 0x3 -#define BIT_GPIO_GPG1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG1_PULL_CTRL) << BIT_SHIFT_GPIO_GPG1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPG0_PULL_CTRL 0 -#define BIT_MASK_GPIO_GPG0_PULL_CTRL 0x3 -#define BIT_GPIO_GPG0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG0_PULL_CTRL) << BIT_SHIFT_GPIO_GPG0_PULL_CTRL) - - -//2 REG_GPIO_PULL_CTRL4 - -#define BIT_SHIFT_GPIO_GPJ6_PULL_CTRL 28 -#define BIT_MASK_GPIO_GPJ6_PULL_CTRL 0x3 -#define BIT_GPIO_GPJ6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ6_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPJ5_PULL_CTRL 26 -#define BIT_MASK_GPIO_GPJ5_PULL_CTRL 0x3 -#define BIT_GPIO_GPJ5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ5_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPJ4_PULL_CTRL 24 -#define BIT_MASK_GPIO_GPJ4_PULL_CTRL 0x3 -#define BIT_GPIO_GPJ4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ4_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPJ3_PULL_CTRL 22 -#define BIT_MASK_GPIO_GPJ3_PULL_CTRL 0x3 -#define BIT_GPIO_GPJ3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ3_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPJ2_PULL_CTRL 20 -#define BIT_MASK_GPIO_GPJ2_PULL_CTRL 0x3 -#define BIT_GPIO_GPJ2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ2_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPJ1_PULL_CTRL 18 -#define BIT_MASK_GPIO_GPJ1_PULL_CTRL 0x3 -#define BIT_GPIO_GPJ1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ1_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPJ0_PULL_CTRL 16 -#define BIT_MASK_GPIO_GPJ0_PULL_CTRL 0x3 -#define BIT_GPIO_GPJ0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ0_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ0_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPI7_PULL_CTRL 14 -#define BIT_MASK_GPIO_GPI7_PULL_CTRL 0x3 -#define BIT_GPIO_GPI7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI7_PULL_CTRL) << BIT_SHIFT_GPIO_GPI7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPI6_PULL_CTRL 12 -#define BIT_MASK_GPIO_GPI6_PULL_CTRL 0x3 -#define BIT_GPIO_GPI6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI6_PULL_CTRL) << BIT_SHIFT_GPIO_GPI6_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPI5_PULL_CTRL 10 -#define BIT_MASK_GPIO_GPI5_PULL_CTRL 0x3 -#define BIT_GPIO_GPI5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI5_PULL_CTRL) << BIT_SHIFT_GPIO_GPI5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPI4_PULL_CTRL 8 -#define BIT_MASK_GPIO_GPI4_PULL_CTRL 0x3 -#define BIT_GPIO_GPI4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI4_PULL_CTRL) << BIT_SHIFT_GPIO_GPI4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPI3_PULL_CTRL 6 -#define BIT_MASK_GPIO_GPI3_PULL_CTRL 0x3 -#define BIT_GPIO_GPI3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI3_PULL_CTRL) << BIT_SHIFT_GPIO_GPI3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPI2_PULL_CTRL 4 -#define BIT_MASK_GPIO_GPI2_PULL_CTRL 0x3 -#define BIT_GPIO_GPI2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI2_PULL_CTRL) << BIT_SHIFT_GPIO_GPI2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPI1_PULL_CTRL 2 -#define BIT_MASK_GPIO_GPI1_PULL_CTRL 0x3 -#define BIT_GPIO_GPI1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI1_PULL_CTRL) << BIT_SHIFT_GPIO_GPI1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPI0_PULL_CTRL 0 -#define BIT_MASK_GPIO_GPI0_PULL_CTRL 0x3 -#define BIT_GPIO_GPI0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI0_PULL_CTRL) << BIT_SHIFT_GPIO_GPI0_PULL_CTRL) - - -//2 REG_GPIO_PULL_CTRL5 - -#define BIT_SHIFT_GPIO_GPEA_PULL_CTRL 20 -#define BIT_MASK_GPIO_GPEA_PULL_CTRL 0x3 -#define BIT_GPIO_GPEA_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPEA_PULL_CTRL) << BIT_SHIFT_GPIO_GPEA_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE9_PULL_CTRL 18 -#define BIT_MASK_GPIO_GPE9_PULL_CTRL 0x3 -#define BIT_GPIO_GPE9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE9_PULL_CTRL) << BIT_SHIFT_GPIO_GPE9_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPE8_PULL_CTRL 16 -#define BIT_MASK_GPIO_GPE8_PULL_CTRL 0x3 -#define BIT_GPIO_GPE8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE8_PULL_CTRL) << BIT_SHIFT_GPIO_GPE8_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPK7_PULL_CTRL 12 -#define BIT_MASK_GPIO_GPK7_PULL_CTRL 0x3 -#define BIT_GPIO_GPK7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK7_PULL_CTRL) << BIT_SHIFT_GPIO_GPK7_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPK5_PULL_CTRL 10 -#define BIT_MASK_GPIO_GPK5_PULL_CTRL 0x3 -#define BIT_GPIO_GPK5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK5_PULL_CTRL) << BIT_SHIFT_GPIO_GPK5_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPK4_PULL_CTRL 8 -#define BIT_MASK_GPIO_GPK4_PULL_CTRL 0x3 -#define BIT_GPIO_GPK4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK4_PULL_CTRL) << BIT_SHIFT_GPIO_GPK4_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPK3_PULL_CTRL 6 -#define BIT_MASK_GPIO_GPK3_PULL_CTRL 0x3 -#define BIT_GPIO_GPK3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK3_PULL_CTRL) << BIT_SHIFT_GPIO_GPK3_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPK2_PULL_CTRL 4 -#define BIT_MASK_GPIO_GPK2_PULL_CTRL 0x3 -#define BIT_GPIO_GPK2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK2_PULL_CTRL) << BIT_SHIFT_GPIO_GPK2_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPK1_PULL_CTRL 2 -#define BIT_MASK_GPIO_GPK1_PULL_CTRL 0x3 -#define BIT_GPIO_GPK1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK1_PULL_CTRL) << BIT_SHIFT_GPIO_GPK1_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPK0_PULL_CTRL 0 -#define BIT_MASK_GPIO_GPK0_PULL_CTRL 0x3 -#define BIT_GPIO_GPK0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK0_PULL_CTRL) << BIT_SHIFT_GPIO_GPK0_PULL_CTRL) - - -//2 REG_GPIO_PULL_CTRL6 - -#define BIT_SHIFT_GPIO_GPD9_PULL_CTRL 18 -#define BIT_MASK_GPIO_GPD9_PULL_CTRL 0x3 -#define BIT_GPIO_GPD9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD9_PULL_CTRL) << BIT_SHIFT_GPIO_GPD9_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPD8_PULL_CTRL 16 -#define BIT_MASK_GPIO_GPD8_PULL_CTRL 0x3 -#define BIT_GPIO_GPD8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD8_PULL_CTRL) << BIT_SHIFT_GPIO_GPD8_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC9_PULL_CTRL 2 -#define BIT_MASK_GPIO_GPC9_PULL_CTRL 0x3 -#define BIT_GPIO_GPC9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC9_PULL_CTRL) << BIT_SHIFT_GPIO_GPC9_PULL_CTRL) - - -#define BIT_SHIFT_GPIO_GPC8_PULL_CTRL 0 -#define BIT_MASK_GPIO_GPC8_PULL_CTRL 0x3 -#define BIT_GPIO_GPC8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC8_PULL_CTRL) << BIT_SHIFT_GPIO_GPC8_PULL_CTRL) - - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_PERI_PWM0_CTRL -#define BIT_PERI_PWM0_EN BIT(31) - -#define BIT_SHIFT_PERI_PWM0_GT_SEL 24 -#define BIT_MASK_PERI_PWM0_GT_SEL 0xf -#define BIT_PERI_PWM0_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM0_GT_SEL) << BIT_SHIFT_PERI_PWM0_GT_SEL) - - -#define BIT_SHIFT_PERI_PWM0_DUTY 12 -#define BIT_MASK_PERI_PWM0_DUTY 0x3ff -#define BIT_PERI_PWM0_DUTY(x) (((x) & BIT_MASK_PERI_PWM0_DUTY) << BIT_SHIFT_PERI_PWM0_DUTY) - - -#define BIT_SHIFT_PERI_PWM0_PERIOD 0 -#define BIT_MASK_PERI_PWM0_PERIOD 0x3ff -#define BIT_PERI_PWM0_PERIOD(x) (((x) & BIT_MASK_PERI_PWM0_PERIOD) << BIT_SHIFT_PERI_PWM0_PERIOD) - - -//2 REG_PERI_PWM1_CTRL -#define BIT_PERI_PWM1_EN BIT(31) - -#define BIT_SHIFT_PERI_PWM1_GT_SEL 24 -#define BIT_MASK_PERI_PWM1_GT_SEL 0xf -#define BIT_PERI_PWM1_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM1_GT_SEL) << BIT_SHIFT_PERI_PWM1_GT_SEL) - - -#define BIT_SHIFT_PERI_PWM1_DUTY 12 -#define BIT_MASK_PERI_PWM1_DUTY 0x3ff -#define BIT_PERI_PWM1_DUTY(x) (((x) & BIT_MASK_PERI_PWM1_DUTY) << BIT_SHIFT_PERI_PWM1_DUTY) - - -#define BIT_SHIFT_PERI_PWM1_PERIOD 0 -#define BIT_MASK_PERI_PWM1_PERIOD 0x3ff -#define BIT_PERI_PWM1_PERIOD(x) (((x) & BIT_MASK_PERI_PWM1_PERIOD) << BIT_SHIFT_PERI_PWM1_PERIOD) - - -//2 REG_PERI_PWM2_CTRL -#define BIT_PERI_PWM2_EN BIT(31) - -#define BIT_SHIFT_PERI_PWM2_GT_SEL 24 -#define BIT_MASK_PERI_PWM2_GT_SEL 0xf -#define BIT_PERI_PWM2_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM2_GT_SEL) << BIT_SHIFT_PERI_PWM2_GT_SEL) - - -#define BIT_SHIFT_PERI_PWM2_DUTY 12 -#define BIT_MASK_PERI_PWM2_DUTY 0x3ff -#define BIT_PERI_PWM2_DUTY(x) (((x) & BIT_MASK_PERI_PWM2_DUTY) << BIT_SHIFT_PERI_PWM2_DUTY) - - -#define BIT_SHIFT_PERI_PWM2_PERIOD 0 -#define BIT_MASK_PERI_PWM2_PERIOD 0x3ff -#define BIT_PERI_PWM2_PERIOD(x) (((x) & BIT_MASK_PERI_PWM2_PERIOD) << BIT_SHIFT_PERI_PWM2_PERIOD) - - -//2 REG_PERI_PWM3_CTRL -#define BIT_PERI_PWM3_EN BIT(31) - -#define BIT_SHIFT_PERI_PWM3_GT_SEL 24 -#define BIT_MASK_PERI_PWM3_GT_SEL 0xf -#define BIT_PERI_PWM3_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM3_GT_SEL) << BIT_SHIFT_PERI_PWM3_GT_SEL) - - -#define BIT_SHIFT_PERI_PWM3_DUTY 12 -#define BIT_MASK_PERI_PWM3_DUTY 0x3ff -#define BIT_PERI_PWM3_DUTY(x) (((x) & BIT_MASK_PERI_PWM3_DUTY) << BIT_SHIFT_PERI_PWM3_DUTY) - - -#define BIT_SHIFT_PERI_PWM3_PERIOD 0 -#define BIT_MASK_PERI_PWM3_PERIOD 0x3ff -#define BIT_PERI_PWM3_PERIOD(x) (((x) & BIT_MASK_PERI_PWM3_PERIOD) << BIT_SHIFT_PERI_PWM3_PERIOD) - - -//2 REG_PERI_TIM_EVT_CTRL -#define BIT_PERI_GT_EVT3_EN BIT(31) - -#define BIT_SHIFT_PERI_GT_EVT3_SRC_SEL 28 -#define BIT_MASK_PERI_GT_EVT3_SRC_SEL 0x7 -#define BIT_PERI_GT_EVT3_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT3_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT3_SRC_SEL) - - -#define BIT_SHIFT_PERI_GT_EVT3_PULSE_DUR 24 -#define BIT_MASK_PERI_GT_EVT3_PULSE_DUR 0xf -#define BIT_PERI_GT_EVT3_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT3_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT3_PULSE_DUR) - -#define BIT_PERI_GT_EVT2_EN BIT(23) - -#define BIT_SHIFT_PERI_GT_EVT2_SRC_SEL 20 -#define BIT_MASK_PERI_GT_EVT2_SRC_SEL 0x7 -#define BIT_PERI_GT_EVT2_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT2_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT2_SRC_SEL) - - -#define BIT_SHIFT_PERI_GT_EVT2_PULSE_DUR 16 -#define BIT_MASK_PERI_GT_EVT2_PULSE_DUR 0xf -#define BIT_PERI_GT_EVT2_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT2_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT2_PULSE_DUR) - -#define BIT_PERI_GT_EVT1_EN BIT(15) - -#define BIT_SHIFT_PERI_GT_EVT1_SRC_SEL 12 -#define BIT_MASK_PERI_GT_EVT1_SRC_SEL 0x7 -#define BIT_PERI_GT_EVT1_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT1_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT1_SRC_SEL) - - -#define BIT_SHIFT_PERI_GT_EVT1_PULSE_DUR 8 -#define BIT_MASK_PERI_GT_EVT1_PULSE_DUR 0xf -#define BIT_PERI_GT_EVT1_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT1_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT1_PULSE_DUR) - -#define BIT_PERI_GT_EVT0_EN BIT(7) - -#define BIT_SHIFT_PERI_GT_EVT0_SRC_SEL 4 -#define BIT_MASK_PERI_GT_EVT0_SRC_SEL 0x7 -#define BIT_PERI_GT_EVT0_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT0_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT0_SRC_SEL) - - -#define BIT_SHIFT_PERI_GT_EVT0_PULSE_DUR 0 -#define BIT_MASK_PERI_GT_EVT0_PULSE_DUR 0xf -#define BIT_PERI_GT_EVT0_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT0_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT0_PULSE_DUR) - - -//2 REG_PERI_EGTIM_CTRL - -#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL 12 -#define BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL 0x3 -#define BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL) - - -#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL 10 -#define BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL 0x3 -#define BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL) - - -#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL 8 -#define BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL 0x3 -#define BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL) - - -//2 REG_NOT_VALID - -#define BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL 4 -#define BIT_MASK_PERI_EGTIM_REF_SIG_SEL 0x3 -#define BIT_PERI_EGTIM_REF_SIG_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_REF_SIG_SEL) << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL) - -#define BIT_PERI_EGTIM_EN BIT(0) - -//2 REG_NOT_VALID - -//2 REG_PEON_CFG - -//2 REG_PEON_STATUS -#define BIT_PEON_SDIO_ALDN BIT(0) - - -//========== Register Address Definition ==================// -#define REG_PEON_PWR_CTRL 0x0200 -#define REG_PON_ISO_CTRL 0x0204 -#define REG_SOC_FUNC_EN 0x0210 -#define REG_SOC_HCI_COM_FUNC_EN 0x0214 -#define REG_SOC_PERI_FUNC0_EN 0x0218 -#define REG_SOC_PERI_FUNC1_EN 0x021C -#define REG_SOC_PERI_BD_FUNC0_EN 0x0220 -#define REG_PESOC_CLK_CTRL 0x0230 -#define REG_PESOC_PERI_CLK_CTRL0 0x0234 -#define REG_PESOC_PERI_CLK_CTRL1 0x0238 -#define REG_PESOC_CLK_CTRL3 0x023C -#define REG_PESOC_HCI_CLK_CTRL0 0x0240 -#define REG_PESOC_COM_CLK_CTRL1 0x0244 -#define REG_PESOC_HW_ENG_CLK_CTRL 0x0248 -#define REG_PESOC_CLK_SEL 0x0250 -#define REG_SYS_ANACK_CAL_CTRL 0x026C -#define REG_OSC32K_CTRL 0x0270 -#define REG_OSC32K_REG_CTRL0 0x0274 -#define REG_OSC32K_REG_CTRL1 0x0278 -#define REG_THERMAL_METER_CTRL 0x027C -#define REG_UART_MUX_CTRL 0x0280 -#define REG_SPI_MUX_CTRL 0x0284 -#define REG_I2C_MUX_CTRL 0x0288 -#define REG_I2S_MUX_CTRL 0x028C -#define REG_HCI_PINMUX_CTRL 0x02A0 -#define REG_WL_PINMUX_CTRL 0x02A4 -#define REG_BT_PINMUX_CTRL 0x02A8 -#define REG_PWM_PINMUX_CTRL 0x02AC -#define REG_CPU_PERIPHERAL_CTRL 0x02C0 -#define REG_HCI_CTRL_STATUS_0 0x02E0 -#define REG_HCI_CTRL_STATUS_1 0x02E4 -#define REG_PESOC_MEM_CTRL 0x0300 -#define REG_PESOC_SOC_CTRL 0x0304 -#define REG_PESOC_PERI_CTRL 0x0308 -#define REG_GPIO_SHTDN_CTRL 0x0320 -#define REG_GPIO_DRIVING_CTRL 0x0324 -#define REG_GPIO_PULL_CTRL0 0x0330 -#define REG_GPIO_PULL_CTRL1 0x0334 -#define REG_GPIO_PULL_CTRL2 0x0338 -#define REG_GPIO_PULL_CTRL3 0x033C -#define REG_GPIO_PULL_CTRL4 0x0340 -#define REG_GPIO_PULL_CTRL5 0x0344 -#define REG_GPIO_PULL_CTRL6 0x0348 -#define REG_PERI_PWM0_CTRL 0x0360 -#define REG_PERI_PWM1_CTRL 0x0364 -#define REG_PERI_PWM2_CTRL 0x0368 -#define REG_PERI_PWM3_CTRL 0x036C -#define REG_PERI_TIM_EVT_CTRL 0x0370 -#define REG_PERI_EGTIM_CTRL 0x0374 -#define REG_PEON_CFG 0x03F0 -#define REG_PEON_STATUS 0x03F4 - - -#endif // end of "#ifndef __INC_RTL8195A_PERI_ON_H" diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h deleted file mode 100644 index 19e7fef38a6..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h +++ /dev/null @@ -1,69 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - - -#ifndef _RTL8195A_PWM_H_ -#define _RTL8195A_PWM_H_ - -extern void -HAL_Pwm_SetDuty_8195a( - HAL_PWM_ADAPTER *pPwmAdapt, - u32 period, - u32 pulse_width -); - -extern HAL_Status -HAL_Pwm_Init_8195a( - HAL_PWM_ADAPTER *pPwmAdapt -); - -extern void -HAL_Pwm_Enable_8195a( - HAL_PWM_ADAPTER *pPwmAdapt -); - -extern void -HAL_Pwm_Disable_8195a( - HAL_PWM_ADAPTER *pPwmAdapt -); - -extern void -HAL_Pwm_Dinit_8195a( - HAL_PWM_ADAPTER *pPwmAdapt -); - -#ifdef CONFIG_CHIP_E_CUT -extern _LONG_CALL_ void -HAL_Pwm_SetDuty_8195a_V04( - HAL_PWM_ADAPTER *pPwmAdapt, - u32 period, - u32 pulse_width -); - -extern _LONG_CALL_ HAL_Status -HAL_Pwm_Init_8195a_V04( - HAL_PWM_ADAPTER *pPwmAdapt -); - -extern _LONG_CALL_ void -HAL_Pwm_Enable_8195a_V04( - HAL_PWM_ADAPTER *pPwmAdapt -); - -extern _LONG_CALL_ void -HAL_Pwm_Disable_8195a_V04( - HAL_PWM_ADAPTER *pPwmAdapt -); -#endif - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h deleted file mode 100644 index 561ad066451..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h +++ /dev/null @@ -1,1040 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef _RTL8195A_SDIO_H_ -#define _RTL8195A_SDIO_H_ - -#include "hal_api.h" -#include "hal_util.h" -#if defined(CONFIG_SDIO_BOOT_SIM) || defined(CONFIG_SDIO_BOOT_ROM) -#define SDIO_BOOT_DRIVER 1 // is this SDIO driver works for booting -#else -#include "osdep_api.h" -#define SDIO_BOOT_DRIVER 0 // is this SDIO driver works for booting -#endif - -#if defined(__IAR_SYSTEMS_ICC__) //for IAR SDK -#include "platform_opts.h" -#endif - -#ifndef CONFIG_INIC_EN -#define CONFIG_INIC_EN 0 -#endif -#if CONFIG_INIC_EN -#define CONFIG_INIC_SKB_TX 1 //use SKB for trx to improve the throughput -#define CONFIG_INIC_SKB_RX 1 -#endif - -#if defined(__IAR_SYSTEMS_ICC__) && (CONFIG_INIC_EN == 0)//for IAR SDK - #define SDIO_API_DEFINED 1 -#else - #define SDIO_API_DEFINED 0 -#endif - -#ifndef PRIORITIE_OFFSET //PRIORITIE_OFFSET in FreeRTOSConfig.h -#define PRIORITIE_OFFSET 0 -#endif - -#define SDIO_DEBUG 0 -#define SDIO_MP_MODE 0 // if includes MP mode function -#define SDIO_MAX_WAIT_RX_DMA 100 // Wait RX DMA done -#define SDIO_RX_PKT_SIZE_OVER_16K 0 /* is support SDIO RX packet size > 16K. if true, - a big packet will be transmited via multiple RX_BD */ -#define SDIO_MAILBOX_SIZE 10 // the maximum number of message block can be stored in this mailbox -#define SDIO_PERIODICAL_TIMER_INTERVAL 2000 // in ms, the interval of SDIO periodical timer -#define SDIO_AVG_TP_WIN_SIZE 20 // the number of entry to log the byte count for every periodical timer statistic, to calculate throughput - -#define HAL_SDIO_READ32(addr) HAL_READ32(SDIO_DEVICE_REG_BASE, addr) -#define HAL_SDIO_WRITE32(addr, value) HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value) -#define HAL_SDIO_READ16(addr) HAL_READ16(SDIO_DEVICE_REG_BASE, addr) -#define HAL_SDIO_WRITE16(addr, value) HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value) -#define HAL_SDIO_READ8(addr) HAL_READ8(SDIO_DEVICE_REG_BASE, addr) -#define HAL_SDIO_WRITE8(addr, value) HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value) - -/***** Register Address *****/ -#define REG_SPDIO_TXBD_ADDR 0xA0 // 4 Bytes -#define REG_SPDIO_TXBD_SIZE 0xA4 // 4 Bytes -#define REG_SPDIO_TXBD_WPTR 0xA8 // 2 Bytes -#define REG_SPDIO_TXBD_RPTR 0xAC // 2 Bytes -#define REG_SPDIO_RXBD_ADDR 0xB0 // 4 Bytes -#define REG_SPDIO_RXBD_SIZE 0xB4 // 2 Bytes -#define REG_SPDIO_RXBD_C2H_WPTR 0xB6 // 2 Bytes -#define REG_SPDIO_RXBD_C2H_RPTR 0xB8 // 2 Bytes -#define REG_SPDIO_HCI_RX_REQ 0xBA // 1 Byte -#define REG_SPDIO_CPU_RST_DMA 0xBB // 1 Byte -#define REG_SPDIO_RX_REQ_ADDR 0xBC // 2 Bytes -#define REG_SPDIO_CPU_INT_MASK 0xC0 // 2 Bytes -#define REG_SPDIO_CPU_INT_STAS 0xC2 // 2 Bytes -#define REG_SPDIO_CCPWM 0xC4 // 1 Byts -#define REG_SPDIO_CPU_IND 0xC5 // 1 Byte -#define REG_SPDIO_CCPWM2 0xC6 // 2 Bytes -#define REG_SPDIO_CPU_H2C_MSG 0xC8 // 4 Bytes -#define REG_SPDIO_CPU_C2H_MSG 0xCC // 4 Bytes -#define REG_SPDIO_CRPWM 0xD0 // 1 Bytes -#define REG_SPDIO_CRPWM2 0xD2 // 2 Bytes -#define REG_SPDIO_AHB_DMA_CTRL 0xD4 // 4 Bytes -#define REG_SPDIO_RXBD_CNT 0xD8 // 4 Bytes -#define REG_SPDIO_TX_BUF_UNIT_SZ 0xD9 // 1 Bytes -#define REG_SPDIO_RX_BD_FREE_CNT 0xDA // 2 Bytes -#define REG_SPDIO_CPU_H2C_MSG_EXT 0xDC // 4 Bytes -#define REG_SPDIO_CPU_C2H_MSG_EXT 0xE0 // 4 Bytes - -// Register REG_SPDIO_CPU_RST_DMA -#define BIT_CPU_RST_SDIO_DMA BIT(7) - -// Register REG_SPDIO_CPU_INT_MASK, REG_SPDIO_CPU_INT_STAS -#define BIT_TXFIFO_H2C_OVF BIT(0) -#define BIT_H2C_BUS_RES_FAIL BIT(1) -#define BIT_H2C_DMA_OK BIT(2) -#define BIT_C2H_DMA_OK BIT(3) -#define BIT_H2C_MSG_INT BIT(4) -#define BIT_RPWM1_INT BIT(5) -#define BIT_RPWM2_INT BIT(6) -#define BIT_SDIO_RST_CMD_INT BIT(7) -#define BIT_RXBD_FLAG_ERR_INT BIT(8) -#define BIT_RX_BD_AVAI_INT BIT(9) -#define BIT_HOST_WAKE_CPU_INT BIT(10) - -// Register REG_SPDIO_CPU_IND -#define BIT_SYSTEM_TRX_RDY_IND BIT(0) - -// Register REG_SPDIO_HCI_RX_REQ -#define BIT_HCI_RX_REQ BIT(0) - -/* Register for SOC_HCI_COM_FUN_EN */ -#define BIT_SOC_HCI_SDIOD_OFF_EN BIT(1) // SDIO Function Block on Power_Off domain -#define BIT_SOC_HCI_SDIOD_ON_EN BIT(0) // SDIO Function Block on Power_On domain - -/* Register REG_PESOC_HCI_CLK_CTRL0 */ -#define BIT_SOC_SLPCK_SDIO_HST_EN BIT(3) // SDIO_HST clock enable when CPU sleep command -#define BIT_SOC_ACTCK_SDIO_HST_EN BIT(2) // SDIO_HST clock enable in CPU run mode -#define BIT_SOC_SLPCK_SDIO_DEV_EN BIT(1) // SDIO_DEV clock enable when CPU sleep command -#define BIT_SOC_ACTCK_SDIO_DEV_EN BIT(0) // SDIO_DEV clock enable in CPU run mode - -/***** Structer for each Register *****/ -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) -// Little Endian -// Register REG_SPDIO_HCI_RX_REQ @ 0xBA -typedef struct _SPDIO_HCI_RX_REQ { - u8 HCI_RX_REQ:1; /* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */ - u8 Reserved:7; /* bit[7:1], Reserved */ -} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ; - -// Register REG_SPDIO_CPU_RST_DMA @ 0xBB -typedef struct _SPDIO_CPU_RST_DMA { - u8 Reserved:7; /* bit[6:0], Reserved */ - u8 CPU_RST_SDIO:1; /* bit[7], CPU set this bit to reset SDIO DMA */ -} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA; - -// Register REG_SPDIO_CPU_INT_MASK @ 0xC0 -typedef struct _SPDIO_CPU_INT_MASK { - u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */ - u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */ - u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */ - u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */ - u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */ - u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */ - u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */ - u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */ - u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */ - u16 Reserved:7; /* bit[15:9], Reserved */ -} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK; - -// Register REG_SPDIO_CPU_INT_STATUS @ 0xC2 -typedef struct _SPDIO_CPU_INT_STAS { - u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */ - u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */ - u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */ - u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */ - u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */ - u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */ - u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */ - u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */ - u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */ - u16 Reserved:7; /* bit[15:9], Reserved */ -} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS; - -// Register REG_SPDIO_CCPWM @ 0xC4 -typedef struct _SPDIO_CCPWM { - u8 :1; /* bit[0] */ - u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */ - u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */ - u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */ - u8 Reserved:3; /* bit[6:4], Reserved */ - u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */ -} SPDIO_CCPWM, *PSPDIO_CCPWM; - -// Register REG_SPDIO_CPU_IND @ 0xC5 -typedef struct _SPDIO_CPU_IND { - u8 SYS_TRX_RDY:1; /* bit[0], To indicate the Host system that CPU is ready for TRX - , to be sync to 0x87[0] */ - u8 Reserved:7; /* bit[7:1], Reserved */ -} SPDIO_CPU_IND, *PSPDIO_CPU_IND; - -// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8 -typedef struct _SPDIO_CPU_H2C_MSG { - u32 CPU_H2C_MSG:30; /* bit[30:0], Host CPU to FW message, sync from REG_SDIO_H2C_MSG */ - u32 Reserved:1; /* bit[31], Reserved */ -} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG; - -// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC -typedef struct _SPDIO_CPU_C2H_MSG { - u32 CPU_C2H_MSG:30; /* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */ - u32 Reserved:1; /* bit[31], Reserved */ -} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG; - -// Register REG_SPDIO_CRPWM @ 0xD0 -typedef struct _SPDIO_CRPWM { - u8 :1; /* bit[0] */ - u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */ - u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */ - u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */ - u8 Reserved:3; /* bit[6:4], Reserved */ - u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */ -} SPDIO_CRPWM, *PSPDIO_CRPWM; - -// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4 -typedef struct _SPDIO_AHB_DMA_CTRL { - u32 TXFF_WLEVEL:7; /* bit[6:0], SPDIO TX FIFO water level */ - u32 :1; /* bit[7] */ - u32 RXFF_WLEVEL:7; /* bit[14:8], SPDIO RX FIFO water level */ - u32 :1; /* bit[15] */ - u32 AHB_DMA_CS:4; /* bit[19:16], AHB DMA state */ - u32 :1; /* bit[20] */ - u32 AHB_MASTER_RDY:1; /* bit[21], AHB Master Hready signal */ - u32 AHB_DMA_TRANS:2; /* bit[23:22], AHB DMA Trans value, for debugging */ - u32 AHB_BUSY_WAIT_CNT:4; /* bit[27:24], timeout for AHB controller to wait busy */ - u32 AHB_BURST_TYPE:3; /* bit[30:28], AHB burst type */ - u32 DISPATCH_TXAGG:1; /* bit[31], Enable to dispatch aggregated TX packet */ -} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL; - -#else /* else of '#if LITTLE_ENDIAN' */ -// Big Endian -typedef struct _SPDIO_HCI_RX_REQ { - u8 Reserved:7; /* bit[7:1], Reserved */ - u8 HCI_RX_REQ:1; /* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */ -} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ; - -// Register REG_SPDIO_CPU_RST_DMA @ 0xBB -typedef struct _SPDIO_CPU_RST_DMA { - u8 CPU_RST_SDIO:1; /* bit[7], CPU set this bit to reset SDIO DMA */ - u8 Reserved:7; /* bit[6:0], Reserved */ -} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA; - -// Register REG_SPDIO_CPU_INT_MASK @ 0xC0 -typedef struct _SPDIO_CPU_INT_MASK { - u16 Reserved:7; /* bit[15:9], Reserved */ - u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */ - u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */ - u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */ - u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */ - u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */ - u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */ - u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */ - u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */ - u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */ -} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK; - -// Register REG_SPDIO_CPU_INT_STAS @ 0xC2 -typedef struct _SPDIO_CPU_INT_STAS { - u16 Reserved:7; /* bit[15:9], Reserved */ - u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */ - u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */ - u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */ - u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */ - u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */ - u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */ - u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */ - u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */ - u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */ -} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS; - -// Register REG_SPDIO_CCPWM @ 0xC4 -typedef struct _SPDIO_CCPWM { - u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */ - u8 Reserved:3; /* bit[6:4], Reserved */ - u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */ - u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */ - u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */ - u8 :1; /* bit[0] */ -} SPDIO_CCPWM, *PSPDIO_CCPWM; - -// Register REG_SPDIO_CPU_IND @ 0xC5 -typedef struct _SPDIO_CPU_IND { - u8 Reserved:7; /* bit[7:1], Reserved */ - u8 SYS_TRX_RDY:1; /* bit[0], To indicate the Host system that CPU is ready for TRX - , to be sync to 0x87[0] */ -} SPDIO_CPU_IND, *PSPDIO_CPU_IND; - -// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8 -typedef struct _SPDIO_CPU_H2C_MSG { - u32 Reserved:1; /* bit[31], Reserved */ - u32 CPU_H2C_MSG:30; /* bit[30:0], Host CPU to FW message */ -} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG; - -// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC -typedef struct _SPDIO_CPU_C2H_MSG { - u32 Reserved:1; /* bit[31], Reserved */ - u32 CPU_C2H_MSG:30; /* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */ -} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG; - -// Register REG_SPDIO_CRPWM @ 0xD0 -typedef struct _SPDIO_CRPWM { - u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */ - u8 Reserved:3; /* bit[6:4], Reserved */ - u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */ - u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */ - u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */ - u8 :1; /* bit[0] */ -} SPDIO_CRPWM, *PSPDIO_CRPWM; - -// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4 -typedef struct _SPDIO_AHB_DMA_CTRL { - u32 DISPATCH_TXAGG:1; /* bit[31], Enable to dispatch aggregated TX packet */ - u32 AHB_BURST_TYPE:3; /* bit[30:28], AHB burst type */ - u32 AHB_BUSY_WAIT_CNT:4; /* bit[27:24], timeout for AHB controller to wait busy */ - u32 AHB_DMA_TRANS:2; /* bit[23:22], AHB DMA Trans value, for debugging */ - u32 AHB_MASTER_RDY:1; /* bit[21], AHB Master Hready signal */ - u32 :1; /* bit[20] */ - u32 AHB_DMA_CS:4; /* bit[19:16], AHB DMA state */ - u32 :1; /* bit[15] */ - u32 RXFF_WLEVEL:7; /* bit[14:8], SPDIO RX FIFO water level */ - u32 :1; /* bit[7] */ - u32 TXFF_WLEVEL:7; /* bit[6:0], SPDIO TX FIFO water level */ -} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL; - -#endif /* end of '#if LITTLE_ENDIAN' */ - - -//#define TX_FIFO_ADDR 0x0000 -//#define TX_FIFO_SIZE 0x8000 - -//TX BD setting -#if SDIO_BOOT_DRIVER -// for build ROM library -#define SDIO_TX_BD_NUM 2 // Number of TX BD -#define SDIO_TX_BD_BUF_SIZE (2048+32) // the size of a TX BD pointed buffer, WLan header = 26 bytes -#define SDIO_TX_PKT_NUM 10 // Number of TX packet handler - -//RX BD setting -#define RX_BD_FREE_TH 4 // trigger the interrupt when free RX BD over this threshold - -#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned - -#define SDIO_RX_PKT_NUM 3 // Number of RX packet handler -//#define SDIO_RX_BD_NUM 10 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least -#define SDIO_RX_BD_NUM (SDIO_RX_PKT_NUM*2) // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least -#define SDIO_RX_BD_BUF_SIZE (2048+24) // the size of a RX BD pointed buffer, sizeof(RX Desc) = 26 bytes -#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2: - one for RX_Desc, the other for payload */ - -// CCPWM2 bit map definition for Firmware download -#define SDIO_INIT_DONE (BIT0) -#define SDIO_MEM_WR_DONE (BIT1) -#define SDIO_MEM_RD_DONE (BIT2) -#define SDIO_MEM_ST_DONE (BIT3) - -#define SDIO_CPWM2_TOGGLE (BIT15) - -#else -#if CONFIG_INIC_EN -//TX BD setting -#define SDIO_TX_BD_NUM 20 // Number of TX BD -#define SDIO_TX_BD_BUF_SIZE 1540 //1514+24 -//#define SDIO_TX_PKT_NUM 1 // not used - -//RX BD setting -#define RX_BD_FREE_TH 5 // trigger the interrupt when free RX BD over this threshold -#define SDIO_RX_BD_BUF_SIZE 1540 //1514+24 -#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned -#define SDIO_RX_BD_NUM 32 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least -#define SDIO_RX_PKT_NUM 128 // Number of RX packet handler -#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2: - one for RX_Desc, the other for payload */ - -#else -#define SDIO_TX_BD_NUM 24 // Number of TX BD -#define SDIO_TX_BD_BUF_SIZE (2048+32) // the size of a TX BD pointed buffer, WLan header = 26 bytes -#define SDIO_TX_PKT_NUM 128 // Number of TX packet handler - -//RX BD setting -#define RX_BD_FREE_TH 5 // trigger the interrupt when free RX BD over this threshold - -#define SDIO_RX_BD_BUF_SIZE 2048 -#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned - -//#define SDIO_TX_FIFO_SIZE (1024*64) // 64K -#define SDIO_RX_BD_NUM 24 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least -#define SDIO_RX_PKT_NUM 128 // Number of RX packet handler -#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2: - one for RX_Desc, the other for payload */ -#endif -#endif - -#define SDIO_IRQ_PRIORITY 10 - -/* SDIO Events */ -#define SDIO_EVENT_IRQ BIT(0) // Interrupt triggered -#define SDIO_EVENT_RX_PKT_RDY BIT(1) // A new SDIO packet ready -#define SDIO_EVENT_C2H_DMA_DONE BIT(2) // Interrupt of C2H DMA done triggered -#define SDIO_EVENT_DUMP BIT(3) // SDIO status dump periodically Enable -#define SDIO_EVENT_TXBD_REFILL BIT(4) // To refill TX BD buffer -#define SDIO_EVENT_EXIT BIT(28) // Request to exit the SDIO task -#define SDIO_EVENT_MP_STOPPED BIT(29) // The SDIO task is stopped -#define SDIO_EVENT_TX_STOPPED BIT(30) // The SDIO task is stopped -#define SDIO_EVENT_RX_STOPPED BIT(31) // The SDIO task is stopped - -#define SDIO_TASK_PRIORITY 1 // it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest) -#define SDIO_MP_TASK_PRIORITY 2 // it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest) -//#if SDIO_TASK_PRIORITY > (configMAX_PRIORITIES - 1) -#if SDIO_TASK_PRIORITY > (4 - 1) -#error "SDIO Task Priority Should be 0~(configMAX_PRIORITIES-1)" -#endif - -//#define TX_RX_PACKET_SIZE 0x144 - -typedef struct _SDIO_TX_BD_ { - u32 Address; /* The TX buffer physical address, it must be 4-bytes aligned */ -}SDIO_TX_BD, *PSDIO_TX_BD; - -#define TX_BD_STRUCTURE_SIZE (sizeof(SDIO_TX_BD)) - - -/* The RX Buffer Descriptor format */ - -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) -typedef struct _SDIO_RX_BD_ { - u32 BuffSize:14; /* bit[13:0], RX Buffer Size, Maximum 16384-1 */ - u32 LS:1; /* bit[14], is the Last Segment ? */ - u32 FS:1; /* bit[15], is the First Segment ? */ - u32 Seq:16; /* bit[31:16], The sequence number, it's no use for now */ - u32 PhyAddr; /* The RX buffer physical address, it must be 4-bytes aligned */ -} SDIO_RX_BD, *PSDIO_RX_BD; -#else -typedef struct _SDIO_RX_BD_ { - u32 Seq:16; /* bit[31:16], The sequence number, be used for ?? */ - u32 FS:1; /* bit[15], is the First Segment ? */ - u32 LS:1; /* bit[14], is the Last Segment ? */ - u32 BuffSize:14; /* bit[13:0], RX Buffer Size, Maximum 16384 */ - u32 PhyAddr; /* The RX buffer physical address, it must be 4-bytes aligned */ -} SDIO_RX_BD, *PSDIO_RX_BD; -#endif -#define RX_BD_STRUCTURE_SIZE (sizeof(SDIO_RX_BD)) - -// TODO: This data structer just for test, we should modify it for the normal driver -typedef struct _SDIO_TX_DESC{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 txpktsize:16; // bit[15:0] - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number -#else - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 txpktsize:16; // bit[15:0] -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the packet type - u32 rsvd0:24; -#else - u32 rsvd0:24; - u32 type:8; // bit[7:0], the packet type -#endif - - // u4Byte 2 - u32 rsvd1; - - // u4Byte 3 - u32 rsvd2; - - // u4Byte 4 - u32 rsvd3; - - // u4Byte 5 - u32 rsvd4; -} SDIO_TX_DESC, *PSDIO_TX_DESC; - -// TX Desc for Memory Write command -typedef struct _SDIO_TX_DESC_MW{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 txpktsize:16; // bit[15:0] - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number -#else - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 txpktsize:16; // bit[15:0] -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the packet type - u32 reply:1; // bit[8], request to send a reply message - u32 rsvd0:23; -#else - u32 rsvd0:23; - u32 reply:1; // bit[8], request to send a reply message - u32 type:8; // bit[7:0], the packet type -#endif - - // u4Byte 2 - u32 start_addr; // memory write start address - - // u4Byte 3 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 write_len:16; // bit[15:0], the length to write - u32 rsvd2:16; // bit[31:16] -#else - u32 rsvd2:16; // bit[31:16] - u32 write_len:16; // bit[15:0], the length to write -#endif - - // u4Byte 4 - u32 rsvd3; - - // u4Byte 5 - u32 rsvd4; -} SDIO_TX_DESC_MW, *PSDIO_TX_DESC_MW; - -// TX Desc for Memory Read command -typedef struct _SDIO_TX_DESC_MR{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 txpktsize:16; // bit[15:0] - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number -#else - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 txpktsize:16; // bit[15:0] -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the packet type - u32 rsvd0:24; -#else - u32 rsvd0:24; - u32 type:8; // bit[7:0], the packet type -#endif - - // u4Byte 2 - u32 start_addr; // memory write start address - - // u4Byte 3 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 read_len:16; // bit[15:0], the length to read - u32 rsvd2:16; // bit[31:16] -#else - u32 rsvd2:16; // bit[31:16] - u32 read_len:16; // bit[15:0], the length to read -#endif - - // u4Byte 4 - u32 rsvd3; - - // u4Byte 5 - u32 rsvd4; -} SDIO_TX_DESC_MR, *PSDIO_TX_DESC_MR; - -// TX Desc for Memory Set command -typedef struct _SDIO_TX_DESC_MS{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 txpktsize:16; // bit[15:0] - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number -#else - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 txpktsize:16; // bit[15:0] -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the packet type - u32 data:8; // bit[8:15], the value to be written to the memory - u32 reply:1; // bit[16], request to send a reply message - u32 rsvd0:15; -#else - u32 rsvd0:15; - u32 reply:1; // bit[16], request to send a reply message - u32 data:8; // bit[8:15], the value to be written to the memory - u32 type:8; // bit[7:0], the packet type -#endif - - // u4Byte 2 - u32 start_addr; // memory write start address - - // u4Byte 3 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 write_len:16; // bit[15:0], the length to write - u32 rsvd2:16; // bit[31:16] -#else - u32 rsvd2:16; // bit[31:16] - u32 write_len:16; // bit[15:0], the length to write -#endif - - // u4Byte 4 - u32 rsvd3; - - // u4Byte 5 - u32 rsvd4; -} SDIO_TX_DESC_MS, *PSDIO_TX_DESC_MS; - -// TX Desc for Jump to Start command -typedef struct _SDIO_TX_DESC_JS{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 txpktsize:16; // bit[15:0] - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number -#else - u32 bus_agg_num:8; // bit[31:24], the bus aggregation number - u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) - u32 txpktsize:16; // bit[15:0] -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the packet type - u32 rsvd0:24; -#else - u32 rsvd0:24; - u32 type:8; // bit[7:0], the packet type -#endif - - // u4Byte 2 - u32 start_fun; // the pointer of the startup function - - // u4Byte 3 - u32 rsvd2; - - // u4Byte 4 - u32 rsvd3; - - // u4Byte 5 - u32 rsvd4; -} SDIO_TX_DESC_JS, *PSDIO_TX_DESC_JS; - - -#define SIZE_TX_DESC (sizeof(SDIO_TX_DESC)) -// define the TX BD buffer size with unite of 64 byets -/* Be carefull!! the setting of hardware's TX BD buffer size may exceed the real size of - the TX BD buffer size, and then it may cause the hardware DMA write the buffer overflow */ -#define SDIO_TX_BUF_SZ_UNIT 64 -#define SDIO_TX_BD_BUF_USIZE ((((SDIO_TX_BD_BUF_SIZE+sizeof(SDIO_TX_DESC)-1)/SDIO_TX_BUF_SZ_UNIT)+1)&0xff) - -typedef struct _SDIO_TX_BD_BUFFER_ { - SDIO_TX_DESC TX_Desc; - u8 TX_Buffer[SDIO_TX_BD_BUF_SIZE]; -}SDIO_TX_BD_BUFFER, *PSDIO_TX_BD_BUFFER; - - -// TODO: This data structer just for test, we should modify it for the normal driver -typedef struct _SDIO_RX_DESC{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 pkt_len:16; // bit[15:0], the packet size - u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc - u32 rsvd0:6; // bit[29:24] - u32 icv:1; // bit[30], ICV error - u32 crc:1; // bit[31], CRC error -#else - u32 crc:1; // bit[31], CRC error - u32 icv:1; // bit[30], ICV error - u32 rsvd0:6; // bit[29:24] - u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc - u32 pkt_len:16; // bit[15:0], the packet size -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the type of this packet - u32 rsvd1:24; // bit[31:8] -#else - u32 rsvd1:24; // bit[31:8] - u32 type:8; // bit[7:0], the type of this packet -#endif - - // u4Byte 2 - u32 rsvd2; - - // u4Byte 3 - u32 rsvd3; - - // u4Byte 4 - u32 rsvd4; - - // u4Byte 5 - u32 rsvd5; -} SDIO_RX_DESC, *PSDIO_RX_DESC; - -// For memory read command -typedef struct _SDIO_RX_DESC_MR{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 pkt_len:16; // bit[15:0], the packet size - u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc - u32 rsvd0:8; // bit[31:24] -#else - u32 rsvd0:8; // bit[31:24] - u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc - u32 pkt_len:16; // bit[15:0], the packet size -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the type of this packet - u32 rsvd1:24; // bit[31:8] -#else - u32 rsvd1:24; // bit[31:8] - u32 type:8; // bit[7:0], the type of this packet -#endif - - // u4Byte 2 - u32 start_addr; - - // u4Byte 3 - u32 rsvd2; - - // u4Byte 4 - u32 rsvd3; - - // u4Byte 5 - u32 rsvd4; -} SDIO_RX_DESC_MR, *PSDIO_RX_DESC_MR; - -// For memory write reply command -typedef struct _SDIO_RX_DESC_MW{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 pkt_len:16; // bit[15:0], the packet size - u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc - u32 rsvd0:8; // bit[31:24] -#else - u32 rsvd0:8; // bit[31:24] - u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc - u32 pkt_len:16; // bit[15:0], the packet size -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the type of this packet - u32 rsvd1:24; // bit[31:8] -#else - u32 rsvd1:24; // bit[31:8] - u32 type:8; // bit[7:0], the type of this packet -#endif - - // u4Byte 2 - u32 start_addr; - - // u4Byte 3 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 write_len:16; // bit[15:0], the type of this packet - u32 result:8; // bit[23:16], the result of memory write command - u32 rsvd2:8; // bit[31:24] -#else - u32 rsvd2:8; // bit[31:24] - u32 result:8; // bit[23:16], the result of memory write command - u32 write_len:16; // bit[15:0], the type of this packet -#endif - - // u4Byte 4 - u32 rsvd3; - - // u4Byte 5 - u32 rsvd4; -} SDIO_RX_DESC_MW, *PSDIO_RX_DESC_MW; - -// For memory set reply command -typedef struct _SDIO_RX_DESC_MS{ - // u4Byte 0 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 pkt_len:16; // bit[15:0], the packet size - u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc - u32 rsvd0:8; // bit[31:24] -#else - u32 rsvd0:8; // bit[31:24] - u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc - u32 pkt_len:16; // bit[15:0], the packet size -#endif - - // u4Byte 1 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 type:8; // bit[7:0], the type of this packet - u32 rsvd1:24; // bit[31:8] -#else - u32 rsvd1:24; // bit[31:8] - u32 type:8; // bit[7:0], the type of this packet -#endif - - // u4Byte 2 - u32 start_addr; - - // u4Byte 3 -#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) - u32 write_len:16; // bit[15:0], the type of this packet - u32 result:8; // bit[23:16], the result of memory write command - u32 rsvd2:8; // bit[31:24] -#else - u32 rsvd2:8; // bit[31:24] - u32 result:8; // bit[23:16], the result of memory write command - u32 write_len:16; // bit[15:0], the type of this packet -#endif - - // u4Byte 4 - u32 rsvd3; - - // u4Byte 5 - u32 rsvd4; -} SDIO_RX_DESC_MS, *PSDIO_RX_DESC_MS; - -#define SIZE_RX_DESC (sizeof(SDIO_RX_DESC)) - -typedef struct _SDIO_RX_BD_BUFFER_ { - SDIO_RX_DESC RX_Desc; - u8 RX_Buffer[SDIO_RX_BD_BUF_SIZE]; -}SDIO_RX_BD_BUFFER, *PSDIO_RX_BD_BUFFER; - - -/* The data structer for a packet fordwarding to the WLan driver to transmit it */ -// TODO: This data structer just for test, we may need modify it for the normal driver -typedef struct _SDIO_TX_PACKET_ { - u8 *pHeader; // Point to the 1st byte of the packets - u16 PktSize; // the size (bytes) of this packet - _LIST list; // the link list to chain packets - u8 isDyna; // is Dynamic allocated -} SDIO_TX_PACKET, *PSDIO_TX_PACKET; - -/* the data structer to bind a TX_BD with a TX Packet */ -typedef struct _SDIO_TX_BD_HANDLE_ { - SDIO_TX_BD *pTXBD; // Point to the TX_BD buffer -#if SDIO_API_DEFINED - VOID *priv; -#else -#if CONFIG_INIC_EN -#if CONFIG_INIC_SKB_TX - struct sk_buff *skb; -#endif -#endif -#endif - SDIO_TX_PACKET *pPkt; // point to the Tx Packet - u8 isPktEnd; // For a packet over 1 BD , this flag to indicate is this BD contains a packet end - u8 isFree; // is this TX BD free -} SDIO_TX_BD_HANDLE, *PSDIO_TX_BD_HANDLE; - -/* The data structer for a packet which from the WLan driver to send to the Host */ -// TODO: This data structer just for test, we may need modify it for the normal driver - -#if SDIO_BOOT_DRIVER -typedef struct _SDIO_RX_PACKET_ { -// SDIO_RX_DESC RxDesc; // The RX Descriptor for this packet, to be send to Host ahead this packet - u8 *pData; // point to the head of payload of this packet - u16 Offset; // the offset from the pData to the payload buffer - _LIST list; // the link list to chain packets - u8 PktBuf[SDIO_RX_BD_BUF_SIZE]; // the Rx_Desc + payload data buffer, the first 24 bytes is reserved for RX_DESC -} SDIO_RX_PACKET, *PSDIO_RX_PACKET; -#else -typedef struct _SDIO_RX_PACKET_ { - SDIO_RX_DESC RxDesc; // The RX Descriptor for this packet, to be send to Host ahead this packet -#if SDIO_API_DEFINED - VOID *priv; -#else -#if CONFIG_INIC_EN -#if CONFIG_INIC_SKB_RX - struct sk_buff *skb; -#endif -#endif -#endif - u8 *pData; // point to the head of payload of this packet - u16 Offset; // the offset from the pData to the payload buffer - _LIST list; // the link list to chain packets - u8 isDyna; // is Dynamic allocated -} SDIO_RX_PACKET, *PSDIO_RX_PACKET; -#endif - -/* the data structer to bind a RX_BD with a RX Packet */ -typedef struct _SDIO_RX_BD_HANDLE_ { - SDIO_RX_BD *pRXBD; // Point to the RX_BD buffer - SDIO_RX_PACKET *pPkt; // point to the Rx Packet - u8 isPktEnd; // For a packet over 1 BD , this flag to indicate is this BD contains a packet end - u8 isFree; // is this RX BD free (DMA done and its RX packet has been freed) -} SDIO_RX_BD_HANDLE, *PSDIO_RX_BD_HANDLE; - -#if SDIO_MP_MODE -typedef struct _SDIO_MP_CMD_ { - u8 cmd_name[16]; - u32 cmd_type; -} SDIO_MP_CMD, *PSDIO_MP_CMD; - -typedef enum _SDIO_MP_CMD_TYPE_{ - SDIO_MP_START=1, - SDIO_MP_STOP=2, - SDIO_MP_LOOPBACK=3, - SDIO_MP_STATUS=4, - SDIO_MP_READ_REG8=5, - SDIO_MP_READ_REG16=6, - SDIO_MP_READ_REG32=7, - SDIO_MP_WRITE_REG8=8, - SDIO_MP_WRITE_REG16=9, - SDIO_MP_WRITE_REG32=10, - SDIO_MP_WAKEUP=11, // wakeup the SDIO task manually, for debugging - SDIO_MP_DUMP=12, // start/stop to dump the SDIO status periodically - SDIO_MP_CTX=13, // setup continue TX test - SDIO_MP_CRX=14, // setup continue RX test - SDIO_MP_CRX_DA=15, // setup continue RX with dynamic allocate RX Buf test - SDIO_MP_CRX_STOP=16, // setup continue RX test - SDIO_MP_DBG_MSG=17, // Debug message On/Off - -}SDIO_MP_CMD_TYPE; - -typedef enum _SDIO_CRX_MODE_{ - SDIO_CRX_STATIC_BUF = 1, - SDIO_CRX_DYNA_BUF = 2, -} SDIO_CRX_MODE; - -typedef struct _SDIO_MP_RX_PACKET_ { - _LIST list; // this member MUST be the 1st one, the link list to chain packets - u8 *pData; // point to the head of payload of this packet - u16 Offset; // the offset from the pData to the payload - u16 DataLen; // the data length of this packet -} SDIO_MP_RX_PACKET, *PSDIO_MP_RX_PACKET; - -#endif // end of '#if SDIO_MP_MODE' - -#define SDIO_CMD_TX_ETH 0x83 // request to TX a 802.3 packet -#define SDIO_CMD_TX_WLN 0x81 // request to TX a 802.11 packet -#define SDIO_CMD_H2C 0x11 // H2C(host to device) command packet -#define SDIO_CMD_MEMRD 0x51 // request to read a block of memory data -#define SDIO_CMD_MEMWR 0x53 // request to write a block of memory -#define SDIO_CMD_MEMST 0x55 // request to set a block of memory with a value -#define SDIO_CMD_STARTUP 0x61 // request to jump to the start up function - -#define SDIO_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet -#define SDIO_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet -#define SDIO_CMD_C2H 0x10 // C2H(device to host) command packet -#define SDIO_CMD_MEMRD_RSP 0x50 // response to memory block read command -#define SDIO_CMD_MEMWR_RSP 0x52 // response to memory write command -#define SDIO_CMD_MEMST_RSP 0x54 // response to memory set command -#define SDIO_CMD_STARTED 0x60 // indicate the program has jumped to the given function - -enum SDIO_RPWM2_BITS { - RPWM2_ACT_BIT = BIT0, // Active - RPWM2_SLEEP_BIT = 0, // Sleep - RPWM2_DSTANDBY_BIT = BIT1, // Deep Standby - RPWM2_PG_BIT = 0, // Power Gated - RPWM2_FBOOT_BIT = BIT2, // fast reboot - RPWM2_NBOOT_BIT = 0, // normal reboot - RPWM2_WKPIN_A5_BIT = BIT3, // enable GPIO A5 wakeup - RPWM2_WKPIN_C7_BIT = BIT4, // enable GPIO C7 wakeup - RPWM2_WKPIN_D5_BIT = BIT5, // enable GPIO D5 wakeup - RPWM2_WKPIN_E3_BIT = BIT6, // enable GPIO E3 wakeup - RPWM2_PIN_A5_LV_BIT = BIT7, // GPIO A5 wakeup level - RPWM2_PIN_C7_LV_BIT = BIT8, // GPIO C7 wakeup level - RPWM2_PIN_D5_LV_BIT = BIT9, // GPIO D5 wakeup level - RPWM2_PIN_E3_LV_BIT = BIT10, // GPIO E3 wakeup level - RPWM2_CG_BIT = BIT11, // Clock Gated - RPWM2_ACK_BIT = BIT14, // Acknowledge - RPWM2_TOGGLE_BIT = BIT15, // Toggle bit -}; - -enum SDIO_CPWM2_BITS { - CPWM2_ACT_BIT = BIT0, // Active - CPWM2_DSTANDBY_BIT = BIT1, // Deep Standby - CPWM2_FBOOT_BIT = BIT2, // fast reboot - CPWM2_INIC_FW_RDY_BIT = BIT3, // is the iNIC FW(1) or Boot FW(0) - - CPWM2_TOGGLE_BIT = BIT15, // Toggle bit -}; - -#ifdef CONFIG_SDIO_DEVICE_VERIFY - -#define TX_BD_STRUCTURE_NUM 10 -#define RX_BD_STRUCTURE_NUM 10 -#define TX_BD_BUFFER_SIZE 0x1000//0x2000//0x800 -#define RX_BD_BUFFER_SIZE 0x400//0x800 - -#define SDIO_RAM_ADDR_BASE 0x20080000 -#define SDIO_BUFFER_HEAD(addr) SDIO_RAM_ADDR_BASE + addr -#define HAL_SDIO_BUFFER_READ8(addr) HAL_READ8(SDIO_RAM_ADDR_BASE, addr) -#define HAL_SDIO_BUFFER_READ32(addr) HAL_READ32(SDIO_RAM_ADDR_BASE, addr) -#define HAL_SDIO_BUFFER_WRITE32(addr, value) HAL_WRITE32(SDIO_RAM_ADDR_BASE, addr, value) - -//#define RX_BD_ADDR 0x8000 -//#define RX_BUFFER_ADDR 0x8050 - -typedef enum _SDIO_TEST_FUNC_ { - SDIO_TEST_INIT, // 0 - SDIO_TEST_INT_ON, // 1 - SDIO_TEST_INT_OFF, // 2 - SDIO_HCI_RX_REQ, // 3 - SDIO_RESET_TXFIFIO, // 4 - SDIO_CPU_RST_DMA, // 5 - SDIO_CPU_CLR_INT_REG, // 6 - SDIO_TIMER_TEST, // 7 - SDIO_TEST_DEBUG, // 8 - SDIO_TEST, // 9 - SDIO_HELP = 0xff -}SDIO_TEST_FUNC, *PSDIO_TEST_FUNC; - -typedef struct _SDIO_TEST_ADAPTER_ { - u32 TXWritePtr; - u32 TXReadPtr; - u16 RXWritePtr; - u16 RXReadPtr; - u16 IntMask; - u16 IntStatus; -} SDIO_TEST_ADAPTER, *PSDIO_TEST_ADAPTER; - - -VOID -MovePKTToRX( - IN u32 Source, IN u32 Destination, IN u32 PKTSize -); - -BOOL -PacketProcess( - IN SDIO_TEST_ADAPTER *pDevStatus -); - -VOID -SdioDeviceIrqHandleFunc( - IN VOID *DATA -); - -VOID -SdioDeviceTestApp( - IN u32 Data -); - -VOID -InitRXBD(VOID); - -VOID -InitTXFIFO(VOID); - -VOID -IrqRegister(VOID); - -#endif // end of "#ifdef CONFIG_SDIO_DEVICE_VERIFY" - -#endif /* #ifndef _RTL8195A_SDIO_H_ */ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h deleted file mode 100644 index 315db89171f..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h +++ /dev/null @@ -1,1155 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef _RTL8195A_SPI_FLASH_H -#define _RTL8195A_SPI_FLASH_H - -#define CPU_OPT_WIDTH 0x1F - -//2 REG_NOT_VALID - -//2 REG_SPIC_CTRLR0 - -#define BIT_SHIFT_CK_MTIMES 23 -#define BIT_MASK_CK_MTIMES 0x1f -#define BIT_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES) -#define BIT_CTRL_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES) -#define BIT_GET_CK_MTIMES(x) (((x) >> BIT_SHIFT_CK_MTIMES) & BIT_MASK_CK_MTIMES) - -#define BIT_FAST_RD BIT(22) -#define BIT_SHIFT_FAST_RD 22 -#define BIT_MASK_FAST_RD 0x1 -#define BIT_CTRL_FAST_RD(x) (((x) & BIT_MASK_FAST_RD) << BIT_SHIFT_FAST_RD) - - -#define BIT_SHIFT_CMD_CH 20 -#define BIT_MASK_CMD_CH 0x3 -#define BIT_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH) -#define BIT_CTRL_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH) -#define BIT_GET_CMD_CH(x) (((x) >> BIT_SHIFT_CMD_CH) & BIT_MASK_CMD_CH) - - -#define BIT_SHIFT_DATA_CH 18 -#define BIT_MASK_DATA_CH 0x3 -#define BIT_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH) -#define BIT_CTRL_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH) -#define BIT_GET_DATA_CH(x) (((x) >> BIT_SHIFT_DATA_CH) & BIT_MASK_DATA_CH) - - -#define BIT_SHIFT_ADDR_CH 16 -#define BIT_MASK_ADDR_CH 0x3 -#define BIT_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH) -#define BIT_CTRL_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH) -#define BIT_GET_ADDR_CH(x) (((x) >> BIT_SHIFT_ADDR_CH) & BIT_MASK_ADDR_CH) - - -#define BIT_SHIFT_TMOD 8 -#define BIT_MASK_TMOD 0x3 -#define BIT_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD) -#define BIT_CTRL_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD) -#define BIT_GET_TMOD(x) (((x) >> BIT_SHIFT_TMOD) & BIT_MASK_TMOD) - -#define BIT_SCPOL BIT(7) -#define BIT_SHIFT_SCPOL 7 -#define BIT_MASK_SCPOL 0x1 -#define BIT_CTRL_SCPOL(x) (((x) & BIT_MASK_SCPOL) << BIT_SHIFT_SCPOL) - -#define BIT_SCPH BIT(6) -#define BIT_SHIFT_SCPH 6 -#define BIT_MASK_SCPH 0x1 -#define BIT_CTRL_SCPH(x) (((x) & BIT_MASK_SCPH) << BIT_SHIFT_SCPH) - -//2 REG_SPIC_CTRLR1 - -#define BIT_SHIFT_NDF 0 -#define BIT_MASK_NDF 0xfff -#define BIT_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF) -#define BIT_CTRL_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF) -#define BIT_GET_NDF(x) (((x) >> BIT_SHIFT_NDF) & BIT_MASK_NDF) - - -//2 REG_SPIC_SSIENR -#define BIT_ATCK_CMD BIT(1) -#define BIT_SHIFT_ATCK_CMD 1 -#define BIT_MASK_ATCK_CMD 0x1 -#define BIT_CTRL_ATCK_CMD(x) (((x) & BIT_MASK_ATCK_CMD) << BIT_SHIFT_ATCK_CMD) - -#define BIT_SPIC_EN BIT(0) -#define BIT_SHIFT_SPIC_EN 0 -#define BIT_MASK_SPIC_EN 0x1 -#define BIT_CTRL_SPIC_EN(x) (((x) & BIT_MASK_SPIC_EN) << BIT_SHIFT_SPIC_EN) - -//2 REG_SPIC_MWCR - -//2 REG_SPIC_SER -#define BIT_SER BIT(0) -#define BIT_SHIFT_SER 0 -#define BIT_MASK_SER 0x1 -#define BIT_CTRL_SER(x) (((x) & BIT_MASK_SER) << BIT_SHIFT_SER) - -//2 REG_SPIC_BAUDR - -#define BIT_SHIFT_SCKDV 0 -#define BIT_MASK_SCKDV 0xffff -#define BIT_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV) -#define BIT_CTRL_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV) -#define BIT_GET_SCKDV(x) (((x) >> BIT_SHIFT_SCKDV) & BIT_MASK_SCKDV) - - -//2 REG_SPIC_TXFTLR - -#define BIT_SHIFT_TFT 0 -#define BIT_MASK_TFT 0x1f -#define BIT_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT) -#define BIT_CTRL_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT) -#define BIT_GET_TFT(x) (((x) >> BIT_SHIFT_TFT) & BIT_MASK_TFT) - - -//2 REG_SPIC_RXFTLR - -#define BIT_SHIFT_RFT 0 -#define BIT_MASK_RFT 0x1f -#define BIT_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT) -#define BIT_CTRL_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT) -#define BIT_GET_RFT(x) (((x) >> BIT_SHIFT_RFT) & BIT_MASK_RFT) - - -//2 REG_SPIC_TXFLR - -#define BIT_SHIFT_TXFL 0 -#define BIT_MASK_TXFL 0x3f -#define BIT_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL) -#define BIT_CTRL_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL) -#define BIT_GET_TXFL(x) (((x) >> BIT_SHIFT_TXFL) & BIT_MASK_TXFL) - - -//2 REG_SPIC_RXFLR - -#define BIT_SHIFT_RXFL 0 -#define BIT_MASK_RXFL 0x3f -#define BIT_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL) -#define BIT_CTRL_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL) -#define BIT_GET_RXFL(x) (((x) >> BIT_SHIFT_RXFL) & BIT_MASK_RXFL) - - -//2 REG_SPIC_SR -#define BIT_TXE BIT(5) -#define BIT_SHIFT_TXE 5 -#define BIT_MASK_TXE 0x1 -#define BIT_CTRL_TXE(x) (((x) & BIT_MASK_TXE) << BIT_SHIFT_TXE) - -#define BIT_RFF BIT(4) -#define BIT_SHIFT_RFF 4 -#define BIT_MASK_RFF 0x1 -#define BIT_CTRL_RFF(x) (((x) & BIT_MASK_RFF) << BIT_SHIFT_RFF) - -#define BIT_RFNE BIT(3) -#define BIT_SHIFT_RFNE 3 -#define BIT_MASK_RFNE 0x1 -#define BIT_CTRL_RFNE(x) (((x) & BIT_MASK_RFNE) << BIT_SHIFT_RFNE) - -#define BIT_TFE BIT(2) -#define BIT_SHIFT_TFE 2 -#define BIT_MASK_TFE 0x1 -#define BIT_CTRL_TFE(x) (((x) & BIT_MASK_TFE) << BIT_SHIFT_TFE) - -#define BIT_TFNF BIT(1) -#define BIT_SHIFT_TFNF 1 -#define BIT_MASK_TFNF 0x1 -#define BIT_CTRL_TFNF(x) (((x) & BIT_MASK_TFNF) << BIT_SHIFT_TFNF) - -#define BIT_BUSY BIT(0) -#define BIT_SHIFT_BUSY 0 -#define BIT_MASK_BUSY 0x1 -#define BIT_CTRL_BUSY(x) (((x) & BIT_MASK_BUSY) << BIT_SHIFT_BUSY) - -//2 REG_SPIC_IMR -#define BIT_TXSIM BIT(9) -#define BIT_SHIFT_TXSIM 9 -#define BIT_MASK_TXSIM 0x1 -#define BIT_CTRL_TXSIM(x) (((x) & BIT_MASK_TXSIM) << BIT_SHIFT_TXSIM) - -#define BIT_ACEIM BIT(8) -#define BIT_SHIFT_ACEIM 8 -#define BIT_MASK_ACEIM 0x1 -#define BIT_CTRL_ACEIM(x) (((x) & BIT_MASK_ACEIM) << BIT_SHIFT_ACEIM) - -#define BIT_BYEIM BIT(7) -#define BIT_SHIFT_BYEIM 7 -#define BIT_MASK_BYEIM 0x1 -#define BIT_CTRL_BYEIM(x) (((x) & BIT_MASK_BYEIM) << BIT_SHIFT_BYEIM) - -#define BIT_WBEIM BIT(6) -#define BIT_SHIFT_WBEIM 6 -#define BIT_MASK_WBEIM 0x1 -#define BIT_CTRL_WBEIM(x) (((x) & BIT_MASK_WBEIM) << BIT_SHIFT_WBEIM) - -#define BIT_FSEIM BIT(5) -#define BIT_SHIFT_FSEIM 5 -#define BIT_MASK_FSEIM 0x1 -#define BIT_CTRL_FSEIM(x) (((x) & BIT_MASK_FSEIM) << BIT_SHIFT_FSEIM) - -#define BIT_RXFIM BIT(4) -#define BIT_SHIFT_RXFIM 4 -#define BIT_MASK_RXFIM 0x1 -#define BIT_CTRL_RXFIM(x) (((x) & BIT_MASK_RXFIM) << BIT_SHIFT_RXFIM) - -#define BIT_RXOIM BIT(3) -#define BIT_SHIFT_RXOIM 3 -#define BIT_MASK_RXOIM 0x1 -#define BIT_CTRL_RXOIM(x) (((x) & BIT_MASK_RXOIM) << BIT_SHIFT_RXOIM) - -#define BIT_RXUIM BIT(2) -#define BIT_SHIFT_RXUIM 2 -#define BIT_MASK_RXUIM 0x1 -#define BIT_CTRL_RXUIM(x) (((x) & BIT_MASK_RXUIM) << BIT_SHIFT_RXUIM) - -#define BIT_TXOIM BIT(1) -#define BIT_SHIFT_TXOIM 1 -#define BIT_MASK_TXOIM 0x1 -#define BIT_CTRL_TXOIM(x) (((x) & BIT_MASK_TXOIM) << BIT_SHIFT_TXOIM) - -#define BIT_TXEIM BIT(0) -#define BIT_SHIFT_TXEIM 0 -#define BIT_MASK_TXEIM 0x1 -#define BIT_CTRL_TXEIM(x) (((x) & BIT_MASK_TXEIM) << BIT_SHIFT_TXEIM) - -//2 REG_SPIC_ISR -#define BIT_TXSIS BIT(9) -#define BIT_SHIFT_TXSIS 9 -#define BIT_MASK_TXSIS 0x1 -#define BIT_CTRL_TXSIS(x) (((x) & BIT_MASK_TXSIS) << BIT_SHIFT_TXSIS) - -#define BIT_ACEIS BIT(8) -#define BIT_SHIFT_ACEIS 8 -#define BIT_MASK_ACEIS 0x1 -#define BIT_CTRL_ACEIS(x) (((x) & BIT_MASK_ACEIS) << BIT_SHIFT_ACEIS) - -#define BIT_BYEIS BIT(7) -#define BIT_SHIFT_BYEIS 7 -#define BIT_MASK_BYEIS 0x1 -#define BIT_CTRL_BYEIS(x) (((x) & BIT_MASK_BYEIS) << BIT_SHIFT_BYEIS) - -#define BIT_WBEIS BIT(6) -#define BIT_SHIFT_WBEIS 6 -#define BIT_MASK_WBEIS 0x1 -#define BIT_CTRL_WBEIS(x) (((x) & BIT_MASK_WBEIS) << BIT_SHIFT_WBEIS) - -#define BIT_FSEIS BIT(5) -#define BIT_SHIFT_FSEIS 5 -#define BIT_MASK_FSEIS 0x1 -#define BIT_CTRL_FSEIS(x) (((x) & BIT_MASK_FSEIS) << BIT_SHIFT_FSEIS) - -#define BIT_RXFIS BIT(4) -#define BIT_SHIFT_RXFIS 4 -#define BIT_MASK_RXFIS 0x1 -#define BIT_CTRL_RXFIS(x) (((x) & BIT_MASK_RXFIS) << BIT_SHIFT_RXFIS) - -#define BIT_RXOIS BIT(3) -#define BIT_SHIFT_RXOIS 3 -#define BIT_MASK_RXOIS 0x1 -#define BIT_CTRL_RXOIS(x) (((x) & BIT_MASK_RXOIS) << BIT_SHIFT_RXOIS) - -#define BIT_RXUIS BIT(2) -#define BIT_SHIFT_RXUIS 2 -#define BIT_MASK_RXUIS 0x1 -#define BIT_CTRL_RXUIS(x) (((x) & BIT_MASK_RXUIS) << BIT_SHIFT_RXUIS) - -#define BIT_TXOIS BIT(1) -#define BIT_SHIFT_TXOIS 1 -#define BIT_MASK_TXOIS 0x1 -#define BIT_CTRL_TXOIS(x) (((x) & BIT_MASK_TXOIS) << BIT_SHIFT_TXOIS) - -#define BIT_TXEIS BIT(0) -#define BIT_SHIFT_TXEIS 0 -#define BIT_MASK_TXEIS 0x1 -#define BIT_CTRL_TXEIS(x) (((x) & BIT_MASK_TXEIS) << BIT_SHIFT_TXEIS) - -//2 REG_SPIC_RISR -#define BIT_ACEIR BIT(8) -#define BIT_SHIFT_ACEIR 8 -#define BIT_MASK_ACEIR 0x1 -#define BIT_CTRL_ACEIR(x) (((x) & BIT_MASK_ACEIR) << BIT_SHIFT_ACEIR) - -#define BIT_BYEIR BIT(7) -#define BIT_SHIFT_BYEIR 7 -#define BIT_MASK_BYEIR 0x1 -#define BIT_CTRL_BYEIR(x) (((x) & BIT_MASK_BYEIR) << BIT_SHIFT_BYEIR) - -#define BIT_WBEIR BIT(6) -#define BIT_SHIFT_WBEIR 6 -#define BIT_MASK_WBEIR 0x1 -#define BIT_CTRL_WBEIR(x) (((x) & BIT_MASK_WBEIR) << BIT_SHIFT_WBEIR) - -#define BIT_FSEIR BIT(5) -#define BIT_SHIFT_FSEIR 5 -#define BIT_MASK_FSEIR 0x1 -#define BIT_CTRL_FSEIR(x) (((x) & BIT_MASK_FSEIR) << BIT_SHIFT_FSEIR) - -#define BIT_RXFIR BIT(4) -#define BIT_SHIFT_RXFIR 4 -#define BIT_MASK_RXFIR 0x1 -#define BIT_CTRL_RXFIR(x) (((x) & BIT_MASK_RXFIR) << BIT_SHIFT_RXFIR) - -#define BIT_RXOIR BIT(3) -#define BIT_SHIFT_RXOIR 3 -#define BIT_MASK_RXOIR 0x1 -#define BIT_CTRL_RXOIR(x) (((x) & BIT_MASK_RXOIR) << BIT_SHIFT_RXOIR) - -#define BIT_RXUIR BIT(2) -#define BIT_SHIFT_RXUIR 2 -#define BIT_MASK_RXUIR 0x1 -#define BIT_CTRL_RXUIR(x) (((x) & BIT_MASK_RXUIR) << BIT_SHIFT_RXUIR) - -#define BIT_TXOIR BIT(1) -#define BIT_SHIFT_TXOIR 1 -#define BIT_MASK_TXOIR 0x1 -#define BIT_CTRL_TXOIR(x) (((x) & BIT_MASK_TXOIR) << BIT_SHIFT_TXOIR) - -#define BIT_TXEIR BIT(0) -#define BIT_SHIFT_TXEIR 0 -#define BIT_MASK_TXEIR 0x1 -#define BIT_CTRL_TXEIR(x) (((x) & BIT_MASK_TXEIR) << BIT_SHIFT_TXEIR) - -//2 REG_SPIC_TXOICR -#define BIT_TXOICR BIT(0) -#define BIT_SHIFT_TXOICR 0 -#define BIT_MASK_TXOICR 0x1 -#define BIT_CTRL_TXOICR(x) (((x) & BIT_MASK_TXOICR) << BIT_SHIFT_TXOICR) - -//2 REG_SPIC_RXOICR -#define BIT_RXOCIR BIT(0) -#define BIT_SHIFT_RXOCIR 0 -#define BIT_MASK_RXOCIR 0x1 -#define BIT_CTRL_RXOCIR(x) (((x) & BIT_MASK_RXOCIR) << BIT_SHIFT_RXOCIR) - -//2 REG_SPC_RXUICR -#define BIT_RXUICR BIT(0) -#define BIT_SHIFT_RXUICR 0 -#define BIT_MASK_RXUICR 0x1 -#define BIT_CTRL_RXUICR(x) (((x) & BIT_MASK_RXUICR) << BIT_SHIFT_RXUICR) - -//2 REG_SPIC_MSTICR -#define BIT_MSTICR BIT(0) -#define BIT_SHIFT_MSTICR 0 -#define BIT_MASK_MSTICR 0x1 -#define BIT_CTRL_MSTICR(x) (((x) & BIT_MASK_MSTICR) << BIT_SHIFT_MSTICR) - -//2 REG_SPIC_ICR - -#define BIT_SHIFT_ICR 0 -#define BIT_MASK_ICR 0xff -#define BIT_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR) -#define BIT_CTRL_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR) -#define BIT_GET_ICR(x) (((x) >> BIT_SHIFT_ICR) & BIT_MASK_ICR) - - -//2 REG_SPIC_DMACR - -//2 REG_SPIC_DMATDLR0 - -//2 REG_SPIC_DMATDLR1 - -//2 REG_SPIC_IDR - -#define BIT_SHIFT_IDCODE 0 -#define BIT_MASK_IDCODE 0xffffffffL -#define BIT_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE) -#define BIT_CTRL_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE) -#define BIT_GET_IDCODE(x) (((x) >> BIT_SHIFT_IDCODE) & BIT_MASK_IDCODE) - - -//2 REG_SPIC_VERSION - -#define BIT_SHIFT_SPIC_VERSION 0 -#define BIT_MASK_SPIC_VERSION 0xffffffffL -#define BIT_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION) -#define BIT_CTRL_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION) -#define BIT_GET_SPIC_VERSION(x) (((x) >> BIT_SHIFT_SPIC_VERSION) & BIT_MASK_SPIC_VERSION) - - -//2 REG_SPIC_DR0 - -#define BIT_SHIFT_DR0 0 -#define BIT_MASK_DR0 0xffffffffL -#define BIT_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0) -#define BIT_CTRL_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0) -#define BIT_GET_DR0(x) (((x) >> BIT_SHIFT_DR0) & BIT_MASK_DR0) - - -//2 REG_SPIC_DR1 - -#define BIT_SHIFT_DR1 0 -#define BIT_MASK_DR1 0xffffffffL -#define BIT_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1) -#define BIT_CTRL_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1) -#define BIT_GET_DR1(x) (((x) >> BIT_SHIFT_DR1) & BIT_MASK_DR1) - - -//2 REG_SPIC_DR2 - -#define BIT_SHIFT_DR2 0 -#define BIT_MASK_DR2 0xffffffffL -#define BIT_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2) -#define BIT_CTRL_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2) -#define BIT_GET_DR2(x) (((x) >> BIT_SHIFT_DR2) & BIT_MASK_DR2) - - -//2 REG_SPIC_DR3 - -#define BIT_SHIFT_DR3 0 -#define BIT_MASK_DR3 0xffffffffL -#define BIT_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3) -#define BIT_CTRL_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3) -#define BIT_GET_DR3(x) (((x) >> BIT_SHIFT_DR3) & BIT_MASK_DR3) - - -//2 REG_SPIC_DR4 - -#define BIT_SHIFT_DR4 0 -#define BIT_MASK_DR4 0xffffffffL -#define BIT_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4) -#define BIT_CTRL_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4) -#define BIT_GET_DR4(x) (((x) >> BIT_SHIFT_DR4) & BIT_MASK_DR4) - - -//2 REG_SPIC_DR5 - -#define BIT_SHIFT_DR5 0 -#define BIT_MASK_DR5 0xffffffffL -#define BIT_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5) -#define BIT_CTRL_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5) -#define BIT_GET_DR5(x) (((x) >> BIT_SHIFT_DR5) & BIT_MASK_DR5) - - -//2 REG_SPIC_DR6 - -#define BIT_SHIFT_DR6 0 -#define BIT_MASK_DR6 0xffffffffL -#define BIT_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6) -#define BIT_CTRL_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6) -#define BIT_GET_DR6(x) (((x) >> BIT_SHIFT_DR6) & BIT_MASK_DR6) - - -//2 REG_SPIC_DR7 - -#define BIT_SHIFT_DR7 0 -#define BIT_MASK_DR7 0xffffffffL -#define BIT_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7) -#define BIT_CTRL_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7) -#define BIT_GET_DR7(x) (((x) >> BIT_SHIFT_DR7) & BIT_MASK_DR7) - - -//2 REG_SPIC_DR8 - -#define BIT_SHIFT_DR8 0 -#define BIT_MASK_DR8 0xffffffffL -#define BIT_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8) -#define BIT_CTRL_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8) -#define BIT_GET_DR8(x) (((x) >> BIT_SHIFT_DR8) & BIT_MASK_DR8) - - -//2 REG_SPIC_DR9 - -#define BIT_SHIFT_DR9 0 -#define BIT_MASK_DR9 0xffffffffL -#define BIT_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9) -#define BIT_CTRL_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9) -#define BIT_GET_DR9(x) (((x) >> BIT_SHIFT_DR9) & BIT_MASK_DR9) - - -//2 REG_SPIC_DR10 - -#define BIT_SHIFT_DR10 0 -#define BIT_MASK_DR10 0xffffffffL -#define BIT_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10) -#define BIT_CTRL_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10) -#define BIT_GET_DR10(x) (((x) >> BIT_SHIFT_DR10) & BIT_MASK_DR10) - - -//2 REG_SPIC_DR11 - -#define BIT_SHIFT_DR11 0 -#define BIT_MASK_DR11 0xffffffffL -#define BIT_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11) -#define BIT_CTRL_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11) -#define BIT_GET_DR11(x) (((x) >> BIT_SHIFT_DR11) & BIT_MASK_DR11) - - -//2 REG_SPIC_DR12 - -#define BIT_SHIFT_DR12 0 -#define BIT_MASK_DR12 0xffffffffL -#define BIT_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12) -#define BIT_CTRL_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12) -#define BIT_GET_DR12(x) (((x) >> BIT_SHIFT_DR12) & BIT_MASK_DR12) - - -//2 REG_SPIC_DR13 - -#define BIT_SHIFT_DR13 0 -#define BIT_MASK_DR13 0xffffffffL -#define BIT_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13) -#define BIT_CTRL_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13) -#define BIT_GET_DR13(x) (((x) >> BIT_SHIFT_DR13) & BIT_MASK_DR13) - - -//2 REG_SPIC_DR14 - -#define BIT_SHIFT_DR14 0 -#define BIT_MASK_DR14 0xffffffffL -#define BIT_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14) -#define BIT_CTRL_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14) -#define BIT_GET_DR14(x) (((x) >> BIT_SHIFT_DR14) & BIT_MASK_DR14) - - -//2 REG_SPIC_DR15 - -#define BIT_SHIFT_DR15 0 -#define BIT_MASK_DR15 0xffffffffL -#define BIT_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15) -#define BIT_CTRL_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15) -#define BIT_GET_DR15(x) (((x) >> BIT_SHIFT_DR15) & BIT_MASK_DR15) - - -//2 REG_SPIC_DR16 - -#define BIT_SHIFT_DR16 0 -#define BIT_MASK_DR16 0xffffffffL -#define BIT_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16) -#define BIT_CTRL_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16) -#define BIT_GET_DR16(x) (((x) >> BIT_SHIFT_DR16) & BIT_MASK_DR16) - - -//2 REG_SPIC_DR17 - -#define BIT_SHIFT_DR17 0 -#define BIT_MASK_DR17 0xffffffffL -#define BIT_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17) -#define BIT_CTRL_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17) -#define BIT_GET_DR17(x) (((x) >> BIT_SHIFT_DR17) & BIT_MASK_DR17) - - -//2 REG_SPIC_DR18 - -#define BIT_SHIFT_DR18 0 -#define BIT_MASK_DR18 0xffffffffL -#define BIT_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18) -#define BIT_CTRL_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18) -#define BIT_GET_DR18(x) (((x) >> BIT_SHIFT_DR18) & BIT_MASK_DR18) - - -//2 REG_SPIC_DR19 - -#define BIT_SHIFT_DR19 0 -#define BIT_MASK_DR19 0xffffffffL -#define BIT_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19) -#define BIT_CTRL_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19) -#define BIT_GET_DR19(x) (((x) >> BIT_SHIFT_DR19) & BIT_MASK_DR19) - - -//2 REG_SPIC_DR20 - -#define BIT_SHIFT_DR20 0 -#define BIT_MASK_DR20 0xffffffffL -#define BIT_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20) -#define BIT_CTRL_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20) -#define BIT_GET_DR20(x) (((x) >> BIT_SHIFT_DR20) & BIT_MASK_DR20) - - -//2 REG_SPIC_DR21 - -#define BIT_SHIFT_DR21 0 -#define BIT_MASK_DR21 0xffffffffL -#define BIT_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21) -#define BIT_CTRL_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21) -#define BIT_GET_DR21(x) (((x) >> BIT_SHIFT_DR21) & BIT_MASK_DR21) - - -//2 REG_SPIC_DR22 - -#define BIT_SHIFT_DR22 0 -#define BIT_MASK_DR22 0xffffffffL -#define BIT_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22) -#define BIT_CTRL_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22) -#define BIT_GET_DR22(x) (((x) >> BIT_SHIFT_DR22) & BIT_MASK_DR22) - - -//2 REG_SPIC_DR23 - -#define BIT_SHIFT_DR23 0 -#define BIT_MASK_DR23 0xffffffffL -#define BIT_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23) -#define BIT_CTRL_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23) -#define BIT_GET_DR23(x) (((x) >> BIT_SHIFT_DR23) & BIT_MASK_DR23) - - -//2 REG_SPIC_DR24 - -#define BIT_SHIFT_DR24 0 -#define BIT_MASK_DR24 0xffffffffL -#define BIT_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24) -#define BIT_CTRL_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24) -#define BIT_GET_DR24(x) (((x) >> BIT_SHIFT_DR24) & BIT_MASK_DR24) - - -//2 REG_SPIC_DR25 - -#define BIT_SHIFT_DR25 0 -#define BIT_MASK_DR25 0xffffffffL -#define BIT_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25) -#define BIT_CTRL_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25) -#define BIT_GET_DR25(x) (((x) >> BIT_SHIFT_DR25) & BIT_MASK_DR25) - - -//2 REG_SPIC_DR26 - -#define BIT_SHIFT_DR26 0 -#define BIT_MASK_DR26 0xffffffffL -#define BIT_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26) -#define BIT_CTRL_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26) -#define BIT_GET_DR26(x) (((x) >> BIT_SHIFT_DR26) & BIT_MASK_DR26) - - -//2 REG_SPIC_DR27 - -#define BIT_SHIFT_DR27 0 -#define BIT_MASK_DR27 0xffffffffL -#define BIT_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27) -#define BIT_CTRL_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27) -#define BIT_GET_DR27(x) (((x) >> BIT_SHIFT_DR27) & BIT_MASK_DR27) - - -//2 REG_SPIC_DR28 - -#define BIT_SHIFT_DR28 0 -#define BIT_MASK_DR28 0xffffffffL -#define BIT_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28) -#define BIT_CTRL_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28) -#define BIT_GET_DR28(x) (((x) >> BIT_SHIFT_DR28) & BIT_MASK_DR28) - - -//2 REG_SPIC_DR29 - -#define BIT_SHIFT_DR29 0 -#define BIT_MASK_DR29 0xffffffffL -#define BIT_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29) -#define BIT_CTRL_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29) -#define BIT_GET_DR29(x) (((x) >> BIT_SHIFT_DR29) & BIT_MASK_DR29) - - -//2 REG_SPIC_DR30 - -#define BIT_SHIFT_DR30 0 -#define BIT_MASK_DR30 0xffffffffL -#define BIT_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30) -#define BIT_CTRL_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30) -#define BIT_GET_DR30(x) (((x) >> BIT_SHIFT_DR30) & BIT_MASK_DR30) - - -//2 REG_SPIC_DR31 - -#define BIT_SHIFT_DR31 0 -#define BIT_MASK_DR31 0xffffffffL -#define BIT_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31) -#define BIT_CTRL_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31) -#define BIT_GET_DR31(x) (((x) >> BIT_SHIFT_DR31) & BIT_MASK_DR31) - - -//2 REG_SPIC_READ_FAST_SINGLE - -#define BIT_SHIFT_FRD_CMD 0 -#define BIT_MASK_FRD_CMD 0xff -#define BIT_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD) -#define BIT_CTRL_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD) -#define BIT_GET_FRD_CMD(x) (((x) >> BIT_SHIFT_FRD_CMD) & BIT_MASK_FRD_CMD) - - -//2 REG_SPIC_READ_DUAL_DATA - -#define BIT_SHIFT_RD_DUAL_O_CMD 0 -#define BIT_MASK_RD_DUAL_O_CMD 0xff -#define BIT_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD) -#define BIT_CTRL_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD) -#define BIT_GET_RD_DUAL_O_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_O_CMD) & BIT_MASK_RD_DUAL_O_CMD) - - -//2 REG_SPIC_READ_DUAL_ADDR_DATA - -#define BIT_SHIFT_RD_DUAL_IO_CMD 0 -#define BIT_MASK_RD_DUAL_IO_CMD 0xff -#define BIT_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD) -#define BIT_CTRL_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD) -#define BIT_GET_RD_DUAL_IO_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_IO_CMD) & BIT_MASK_RD_DUAL_IO_CMD) - - -//2 REG_SPIC_READ_QUAD_DATA - -#define BIT_SHIFT_RD_QUAD_O_CMD 0 -#define BIT_MASK_RD_QUAD_O_CMD 0xff -#define BIT_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD) -#define BIT_CTRL_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD) -#define BIT_GET_RD_QUAD_O_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_O_CMD) & BIT_MASK_RD_QUAD_O_CMD) - - -//2 REG_SPIC_READ_QUAD_ADDR_DATA - -#define BIT_SHIFT_RD_QUAD_IO_CMD 0 -#define BIT_MASK_RD_QUAD_IO_CMD 0xff -#define BIT_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD) -#define BIT_CTRL_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD) -#define BIT_GET_RD_QUAD_IO_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_IO_CMD) & BIT_MASK_RD_QUAD_IO_CMD) - - -//2 REG_SPIC_WRITE_SIGNLE - -#define BIT_SHIFT_WR_CMD 0 -#define BIT_MASK_WR_CMD 0xff -#define BIT_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD) -#define BIT_CTRL_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD) -#define BIT_GET_WR_CMD(x) (((x) >> BIT_SHIFT_WR_CMD) & BIT_MASK_WR_CMD) - - -//2 REG_SPIC_WRITE_DUAL_DATA - -#define BIT_SHIFT_WR_DUAL_I_CMD 0 -#define BIT_MASK_WR_DUAL_I_CMD 0xff -#define BIT_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD) -#define BIT_CTRL_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD) -#define BIT_GET_WR_DUAL_I_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_I_CMD) & BIT_MASK_WR_DUAL_I_CMD) - - -//2 REG_SPIC_WRITE_DUAL_ADDR_DATA - -#define BIT_SHIFT_WR_DUAL_II_CMD 0 -#define BIT_MASK_WR_DUAL_II_CMD 0xff -#define BIT_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD) -#define BIT_CTRL_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD) -#define BIT_GET_WR_DUAL_II_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_II_CMD) & BIT_MASK_WR_DUAL_II_CMD) - - -//2 REG_SPIC_WRITE_QUAD_DATA - -#define BIT_SHIFT_WR_QUAD_I_CMD 0 -#define BIT_MASK_WR_QUAD_I_CMD 0xff -#define BIT_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD) -#define BIT_CTRL_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD) -#define BIT_GET_WR_QUAD_I_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_I_CMD) & BIT_MASK_WR_QUAD_I_CMD) - - -//2 REG_SPIC_WRITE_QUAD_ADDR_DATA - -#define BIT_SHIFT_WR_QUAD_II_CMD 0 -#define BIT_MASK_WR_QUAD_II_CMD 0xff -#define BIT_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD) -#define BIT_CTRL_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD) -#define BIT_GET_WR_QUAD_II_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_II_CMD) & BIT_MASK_WR_QUAD_II_CMD) - - -//2 REG_SPIC_WRITE_ENABLE - -#define BIT_SHIFT_WR_EN_CMD 0 -#define BIT_MASK_WR_EN_CMD 0xff -#define BIT_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD) -#define BIT_CTRL_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD) -#define BIT_GET_WR_EN_CMD(x) (((x) >> BIT_SHIFT_WR_EN_CMD) & BIT_MASK_WR_EN_CMD) - - -//2 REG_SPIC_READ_STATUS - -#define BIT_SHIFT_RD_ST_CMD 0 -#define BIT_MASK_RD_ST_CMD 0xff -#define BIT_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD) -#define BIT_CTRL_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD) -#define BIT_GET_RD_ST_CMD(x) (((x) >> BIT_SHIFT_RD_ST_CMD) & BIT_MASK_RD_ST_CMD) - - -//2 REG_SPIC_CTRLR2 - -#define BIT_SHIFT_FIFO_ENTRY 4 -#define BIT_MASK_FIFO_ENTRY 0xf -#define BIT_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY) -#define BIT_CTRL_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY) -#define BIT_GET_FIFO_ENTRY(x) (((x) >> BIT_SHIFT_FIFO_ENTRY) & BIT_MASK_FIFO_ENTRY) - -#define BIT_WR_SEQ BIT(3) -#define BIT_SHIFT_WR_SEQ 3 -#define BIT_MASK_WR_SEQ 0x1 -#define BIT_CTRL_WR_SEQ(x) (((x) & BIT_MASK_WR_SEQ) << BIT_SHIFT_WR_SEQ) - -#define BIT_WPN_DNUM BIT(2) -#define BIT_SHIFT_WPN_DNUM 2 -#define BIT_MASK_WPN_DNUM 0x1 -#define BIT_CTRL_WPN_DNUM(x) (((x) & BIT_MASK_WPN_DNUM) << BIT_SHIFT_WPN_DNUM) - -#define BIT_WPN_SET BIT(1) -#define BIT_SHIFT_WPN_SET 1 -#define BIT_MASK_WPN_SET 0x1 -#define BIT_CTRL_WPN_SET(x) (((x) & BIT_MASK_WPN_SET) << BIT_SHIFT_WPN_SET) - -#define BIT_SO_DUM BIT(0) -#define BIT_SHIFT_SO_DUM 0 -#define BIT_MASK_SO_DUM 0x1 -#define BIT_CTRL_SO_DUM(x) (((x) & BIT_MASK_SO_DUM) << BIT_SHIFT_SO_DUM) - -//2 REG_SPIC_FBAUDR - -#define BIT_SHIFT_FSCKDV 0 -#define BIT_MASK_FSCKDV 0xfff -#define BIT_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV) -#define BIT_CTRL_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV) -#define BIT_GET_FSCKDV(x) (((x) >> BIT_SHIFT_FSCKDV) & BIT_MASK_FSCKDV) - - -//2 REG_SPIC_ADDR_LENGTH - -#define BIT_SHIFT_ADDR_PHASE_LENGTH 0 -#define BIT_MASK_ADDR_PHASE_LENGTH 0x3 -#define BIT_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH) -#define BIT_CTRL_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH) -#define BIT_GET_ADDR_PHASE_LENGTH(x) (((x) >> BIT_SHIFT_ADDR_PHASE_LENGTH) & BIT_MASK_ADDR_PHASE_LENGTH) - - -//2 REG_SPIC_AUTO_LENGTH - -#define BIT_SHIFT_CS_H_WR_DUM_LEN 28 -#define BIT_MASK_CS_H_WR_DUM_LEN 0xf -#define BIT_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN) -#define BIT_CTRL_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN) -#define BIT_GET_CS_H_WR_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_WR_DUM_LEN) & BIT_MASK_CS_H_WR_DUM_LEN) - - -#define BIT_SHIFT_CS_H_RD_DUM_LEN 26 -#define BIT_MASK_CS_H_RD_DUM_LEN 0x3 -#define BIT_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN) -#define BIT_CTRL_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN) -#define BIT_GET_CS_H_RD_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_RD_DUM_LEN) & BIT_MASK_CS_H_RD_DUM_LEN) - - -#define BIT_SHIFT_AUTO_DUM_LEN 18 -#define BIT_MASK_AUTO_DUM_LEN 0xff -#define BIT_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN) -#define BIT_CTRL_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN) -#define BIT_GET_AUTO_DUM_LEN(x) (((x) >> BIT_SHIFT_AUTO_DUM_LEN) & BIT_MASK_AUTO_DUM_LEN) - - -#define BIT_SHIFT_AUTO_ADDR__LENGTH 16 -#define BIT_MASK_AUTO_ADDR__LENGTH 0x3 -#define BIT_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH) -#define BIT_CTRL_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH) -#define BIT_GET_AUTO_ADDR__LENGTH(x) (((x) >> BIT_SHIFT_AUTO_ADDR__LENGTH) & BIT_MASK_AUTO_ADDR__LENGTH) - - -#define BIT_SHIFT_RD_DUMMY_LENGTH 0 -#define BIT_MASK_RD_DUMMY_LENGTH 0xffff -#define BIT_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH) -#define BIT_CTRL_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH) -#define BIT_GET_RD_DUMMY_LENGTH(x) (((x) >> BIT_SHIFT_RD_DUMMY_LENGTH) & BIT_MASK_RD_DUMMY_LENGTH) - - -//2 REG_SPIC_VALID_CMD -#define BIT_WR_BLOCKING BIT(9) -#define BIT_SHIFT_WR_BLOCKING 9 -#define BIT_MASK_WR_BLOCKING 0x1 -#define BIT_CTRL_WR_BLOCKING(x) (((x) & BIT_MASK_WR_BLOCKING) << BIT_SHIFT_WR_BLOCKING) - -#define BIT_WR_QUAD_II BIT(8) -#define BIT_SHIFT_WR_QUAD_II 8 -#define BIT_MASK_WR_QUAD_II 0x1 -#define BIT_CTRL_WR_QUAD_II(x) (((x) & BIT_MASK_WR_QUAD_II) << BIT_SHIFT_WR_QUAD_II) - -#define BIT_WR_QUAD_I BIT(7) -#define BIT_SHIFT_WR_QUAD_I 7 -#define BIT_MASK_WR_QUAD_I 0x1 -#define BIT_CTRL_WR_QUAD_I(x) (((x) & BIT_MASK_WR_QUAD_I) << BIT_SHIFT_WR_QUAD_I) - -#define BIT_WR_DUAL_II BIT(6) -#define BIT_SHIFT_WR_DUAL_II 6 -#define BIT_MASK_WR_DUAL_II 0x1 -#define BIT_CTRL_WR_DUAL_II(x) (((x) & BIT_MASK_WR_DUAL_II) << BIT_SHIFT_WR_DUAL_II) - -#define BIT_WR_DUAL_I BIT(5) -#define BIT_SHIFT_WR_DUAL_I 5 -#define BIT_MASK_WR_DUAL_I 0x1 -#define BIT_CTRL_WR_DUAL_I(x) (((x) & BIT_MASK_WR_DUAL_I) << BIT_SHIFT_WR_DUAL_I) - -#define BIT_RD_QUAD_IO BIT(4) -#define BIT_SHIFT_RD_QUAD_IO 4 -#define BIT_MASK_RD_QUAD_IO 0x1 -#define BIT_CTRL_RD_QUAD_IO(x) (((x) & BIT_MASK_RD_QUAD_IO) << BIT_SHIFT_RD_QUAD_IO) - -#define BIT_RD_QUAD_O BIT(3) -#define BIT_SHIFT_RD_QUAD_O 3 -#define BIT_MASK_RD_QUAD_O 0x1 -#define BIT_CTRL_RD_QUAD_O(x) (((x) & BIT_MASK_RD_QUAD_O) << BIT_SHIFT_RD_QUAD_O) - -#define BIT_RD_DUAL_IO BIT(2) -#define BIT_SHIFT_RD_DUAL_IO 2 -#define BIT_MASK_RD_DUAL_IO 0x1 -#define BIT_CTRL_RD_DUAL_IO(x) (((x) & BIT_MASK_RD_DUAL_IO) << BIT_SHIFT_RD_DUAL_IO) - -#define BIT_RD_DUAL_I BIT(1) -#define BIT_SHIFT_RD_DUAL_I 1 -#define BIT_MASK_RD_DUAL_I 0x1 -#define BIT_CTRL_RD_DUAL_I(x) (((x) & BIT_MASK_RD_DUAL_I) << BIT_SHIFT_RD_DUAL_I) - -#define BIT_FRD_SINGEL BIT(0) -#define BIT_SHIFT_FRD_SINGEL 0 -#define BIT_MASK_FRD_SINGEL 0x1 -#define BIT_CTRL_FRD_SINGEL(x) (((x) & BIT_MASK_FRD_SINGEL) << BIT_SHIFT_FRD_SINGEL) - -//2 REG_SPIC_FLASE_SIZE - -#define BIT_SHIFT_FLASE_SIZE 0 -#define BIT_MASK_FLASE_SIZE 0xf -#define BIT_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE) -#define BIT_CTRL_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE) -#define BIT_GET_FLASE_SIZE(x) (((x) >> BIT_SHIFT_FLASE_SIZE) & BIT_MASK_FLASE_SIZE) - - -//2 REG_SPIC_FLUSH_FIFO -#define BIT_FLUSH_FIFO BIT(0) -#define BIT_SHIFT_FLUSH_FIFO 0 -#define BIT_MASK_FLUSH_FIFO 0x1 -#define BIT_CTRL_FLUSH_FIFO(x) (((x) & BIT_MASK_FLUSH_FIFO) << BIT_SHIFT_FLUSH_FIFO) - -//=================== Register Address Definition ============================// -#define REG_SPIC_CTRLR0 0x0000//O -#define REG_SPIC_CTRLR1 0x0004//O -#define REG_SPIC_SSIENR 0x0008//O -#define REG_SPIC_MWCR 0x000C -#define REG_SPIC_SER 0x0010//O -#define REG_SPIC_BAUDR 0x0014//O -#define REG_SPIC_TXFTLR 0x0018 -#define REG_SPIC_RXFTLR 0x001C//O -#define REG_SPIC_TXFLR 0x0020//O -#define REG_SPIC_RXFLR 0x0024 -#define REG_SPIC_SR 0x0028 -#define REG_SPIC_IMR 0x002C//O -#define REG_SPIC_ISR 0x0030 -#define REG_SPIC_RISR 0x0034 -#define REG_SPIC_TXOICR 0x0038 -#define REG_SPIC_RXOICR 0x003C -#define REG_SPC_RXUICR 0x0040 -#define REG_SPIC_MSTICR 0x0044 -#define REG_SPIC_ICR 0x0048 -#define REG_SPIC_DMACR 0x004C -#define REG_SPIC_DMATDLR0 0x0050 -#define REG_SPIC_DMATDLR1 0x0054 -#define REG_SPIC_IDR 0x0058 -#define REG_SPIC_VERSION 0x005C -#define REG_SPIC_DR0 0x0060 -#define REG_SPIC_DR1 0x0064 -#define REG_SPIC_DR2 0x0068 -#define REG_SPIC_DR3 0x006C -#define REG_SPIC_DR4 0x0070 -#define REG_SPIC_DR5 0x0074 -#define REG_SPIC_DR6 0x0078 -#define REG_SPIC_DR7 0x007C -#define REG_SPIC_DR8 0x0080 -#define REG_SPIC_DR9 0x0084 -#define REG_SPIC_DR10 0x0088 -#define REG_SPIC_DR11 0x008C -#define REG_SPIC_DR12 0x0090 -#define REG_SPIC_DR13 0x0094 -#define REG_SPIC_DR14 0x0098 -#define REG_SPIC_DR15 0x009C -#define REG_SPIC_DR16 0x00A0 -#define REG_SPIC_DR17 0x00A4 -#define REG_SPIC_DR18 0x00A8 -#define REG_SPIC_DR19 0x00AC -#define REG_SPIC_DR20 0x00B0 -#define REG_SPIC_DR21 0x00B4 -#define REG_SPIC_DR22 0x00B8 -#define REG_SPIC_DR23 0x00BC -#define REG_SPIC_DR24 0x00C0 -#define REG_SPIC_DR25 0x00C4 -#define REG_SPIC_DR26 0x00C8 -#define REG_SPIC_DR27 0x00CC -#define REG_SPIC_DR28 0x00D0 -#define REG_SPIC_DR29 0x00D4 -#define REG_SPIC_DR30 0x00D8 -#define REG_SPIC_DR31 0x00DC -#define REG_SPIC_READ_FAST_SINGLE 0x00E0//O -#define REG_SPIC_READ_DUAL_DATA 0x00E4//O -#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8//O -#define REG_SPIC_READ_QUAD_DATA 0x00EC//O -#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0//O -#define REG_SPIC_WRITE_SIGNLE 0x00F4//O -#define REG_SPIC_WRITE_DUAL_DATA 0x00F8//O -#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O -#define REG_SPIC_WRITE_QUAD_DATA 0x0100//O -#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O -#define REG_SPIC_WRITE_ENABLE 0x0108//O -#define REG_SPIC_READ_STATUS 0x010C//O -#define REG_SPIC_CTRLR2 0x0110//O -#define REG_SPIC_FBAUDR 0x0114//O -#define REG_SPIC_ADDR_LENGTH 0x0118//O -#define REG_SPIC_AUTO_LENGTH 0x011C//O -#define REG_SPIC_VALID_CMD 0x0120//O -#define REG_SPIC_FLASE_SIZE 0x0124//O -#define REG_SPIC_FLUSH_FIFO 0x0128//O - -VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); // spi-flash controller initialization -VOID SpicRxCmdRtl8195A(u8); // recieve command -VOID SpicTxCmdRtl8195A(u8 cmd, SPIC_INIT_PARA SpicInitPara); // transfer command -u8 SpicGetFlashStatusRtl8195A(SPIC_INIT_PARA SpicInitPara); // RDSR, read spi-flash status register -VOID SpicSetFlashStatusRtl8195A(u32 data, SPIC_INIT_PARA SpicInitPara); // WRSR, write spi-flash status register -VOID SpicWaitBusyDoneRtl8195A(VOID); // wait sr[0] = 0, wait transmission done -VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0 -VOID SpicEraseFlashRtl8195A(VOID); // CE, flash chip erase -u32 SpicCmpDataForCalibrationRtl8195A(VOID); // compare read_data and golden_data -VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); - -#if 1//CONFIG_CHIP_E_CUT - -VOID -SpicTxCmdWithDataRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u8 cmd, - IN u8 DataPhaseLen, - IN u8* pData -); - -VOID -SpicTxFlashInstRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u8 cmd, - IN u8 DataPhaseLen, - IN u8* pData -); - -VOID -SpicDeepPowerDownFlashRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara -); - -VOID -SpicBlockEraseFlashRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u32 Address -); - -VOID -SpicSectorEraseFlashRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u32 Address -); - -VOID -SpicWriteProtectFlashRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u32 Protect -); - -BOOLEAN -SpicFlashInitRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u8 SpicBitMode -); - -u32 -SpicCalibrationRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u8 SpicBitMode, - IN u32 DefRdDummyCycle -); - -VOID -SpicConfigAutoModeRtl8195A_V04( - IN u8 SpicBitMode -); - -VOID -SpicWaitWipDoneRefinedRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara -); - -VOID -SpicRxCmdRefinedRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u8 cmd -); - -u8 -SpicGetFlashStatusRefinedRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara -); - -VOID -SpicInitRefinedRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u8 InitBaudRate, - IN u8 SpicBitMode -); - -VOID -SpicEraseFlashRefinedRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara -); - -VOID -SpicSetFlashStatusRefinedRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u32 data -); - -u32 -SpicWaitWipRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara -); - -u32 -SpicOneBitCalibrationRtl8195A_V04( - IN SPIC_INIT_PARA *pSpicInitPara, - IN u8 SysCpuClk -); - -VOID -SpicLoadInitParaFromClockRtl8195A_V04( - IN u8 CpuClkMode, - IN u8 BaudRate, - IN PSPIC_INIT_PARA pSpicInitPara -) ; - -u8 -SpicGetFlashFlagRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara); - -VOID -SpicWaitOperationDoneRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara); - -VOID -SpicUserProgramRtl8195A_V04(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo); - -VOID -SpicUserReadRtl8195A_V04(IN u32 Length, IN u32 addr, IN u8 * data); - -VOID -SpicUserReadFourByteRtl8195A_V04(IN u32 Length, IN u32 addr, IN u32 * data, IN u8 BitMode); - -VOID -SpicSetExtendAddrRtl8195A_V04(IN u32 data, IN SPIC_INIT_PARA * pSpicInitPara); - -u8 -SpicGetExtendAddrRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara); - -VOID -SpicReadIDRtl8195A_V04(VOID); - -VOID -SpicDieEraseFlashRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara, IN u32 Address); - -u8 -SpicGetConfigRegRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara); -#endif // #if CONFIG_CHIP_E_CUT - -#endif // end of "#ifndef _RTL8195A_SPI_FLASH_H" diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h deleted file mode 100644 index b2aa425e4b7..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h +++ /dev/null @@ -1,568 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _RTL8195A_SSI_H_ -#define _RTL8195A_SSI_H_ - -#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read - -#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2) -#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4) - -/* Parameters of DW_apb_ssi for RTL8195A */ -#define SSI_TX_FIFO_DEPTH 64 -#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH) -#define SSI_RX_FIFO_DEPTH 64 -#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH) - -#define SSI0_REG_BASE 0x40042000 -#define SSI1_REG_BASE 0x40042400 -#define SSI2_REG_BASE 0x40042800 - -/* Memory Map of DW_apb_ssi */ -#define REG_DW_SSI_CTRLR0 0x00 // 16 bits -#define REG_DW_SSI_CTRLR1 0x04 // 16 bits -#define REG_DW_SSI_SSIENR 0x08 // 1 bit -#define REG_DW_SSI_MWCR 0x0C // 3 bits -#define REG_DW_SSI_SER 0x10 // -#define REG_DW_SSI_BAUDR 0x14 // 16 bits -#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW -#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW -#define REG_DW_SSI_TXFLR 0x20 // -#define REG_DW_SSI_RXFLR 0x24 // -#define REG_DW_SSI_SR 0x28 // 7 bits -#define REG_DW_SSI_IMR 0x2C // -#define REG_DW_SSI_ISR 0x30 // 6 bits -#define REG_DW_SSI_RISR 0x34 // 6 bits -#define REG_DW_SSI_TXOICR 0x38 // 1 bits -#define REG_DW_SSI_RXOICR 0x3C // 1 bits -#define REG_DW_SSI_RXUICR 0x40 // 1 bits -#define REG_DW_SSI_MSTICR 0x44 // 1 bits -#define REG_DW_SSI_ICR 0x48 // 1 bits -#define REG_DW_SSI_DMACR 0x4C // 2 bits -#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW -#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW -#define REG_DW_SSI_IDR 0x58 // 32 bits -#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits -#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC -#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits -#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits -#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits -#define REG_DW_SSI_RSVD_2 0xFC // 32 bits - -// CTRLR0 0x00 // 16 bits, 6.2.1 -// DFS Reset Value: 0x7 -#define BIT_SHIFT_CTRLR0_DFS 0 -#define BIT_MASK_CTRLR0_DFS 0xF -#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS) -#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS)) - -#define BIT_SHIFT_CTRLR0_FRF 4 -#define BIT_MASK_CTRLR0_FRF 0x3 -#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF) -#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF)) - -#define BIT_SHIFT_CTRLR0_SCPH 6 -#define BIT_MASK_CTRLR0_SCPH 0x1 -#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH) -#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH)) - -#define BIT_SHIFT_CTRLR0_SCPOL 7 -#define BIT_MASK_CTRLR0_SCPOL 0x1 -#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL) -#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL)) - -#define BIT_SHIFT_CTRLR0_TMOD 8 -#define BIT_MASK_CTRLR0_TMOD 0x3 -#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD) -#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD)) - -#define BIT_SHIFT_CTRLR0_SLV_OE 10 -#define BIT_MASK_CTRLR0_SLV_OE 0x1 -#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE) -#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE)) - -#define BIT_SHIFT_CTRLR0_SRL 11 -#define BIT_MASK_CTRLR0_SRL 0x1 -#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL) -#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL)) - -#define BIT_SHIFT_CTRLR0_CFS 12 -#define BIT_MASK_CTRLR0_CFS 0xF -#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS) -#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS)) - -// CTRLR1 0x04 // 16 bits -#define BIT_SHIFT_CTRLR1_NDF 0 -#define BIT_MASK_CTRLR1_NDF 0xFFFF -#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF) -#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF)) - -// SSIENR 0x08 // 1 bit -#define BIT_SHIFT_SSIENR_SSI_EN 0 -#define BIT_MASK_SSIENR_SSI_EN 0x1 -#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN) -#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN)) - -// MWCR 0x0c // 3 bits -#define BIT_SHIFT_MWCR_MWMOD 0 -#define BIT_MASK_MWCR_MWMOD 0x1 -#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD) -#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD)) - -#define BIT_SHIFT_MWCR_MDD 1 -#define BIT_MASK_MWCR_MDD 0x1 -#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD) -#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD)) - -#define BIT_SHIFT_MWCR_MHS 2 -#define BIT_MASK_MWCR_MHS 0x1 -#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS) -#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS)) - -// SER 0x10 // Variable Length -#define BIT_SHIFT_SER_SER 0 -#define BIT_MASK_SER_SER 0xFF -#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER) -#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER)) - -// BAUDR 0x14 // 16 bits -#define BIT_SHIFT_BAUDR_SCKDV 0 -#define BIT_MASK_BAUDR_SCKDV 0xFFFF -#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV) -#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV)) - -// TXFLTR 0x18 // Variable Length -#define BIT_SHIFT_TXFTLR_TFT 0 -#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0 -#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT) -#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT)) - -// RXFLTR 0x1c // Variable Length -#define BIT_SHIFT_RXFTLR_RFT 0 -#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0 -#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT) -#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT)) - -// TXFLR 0x20 // see [READ ONLY] -#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0 - -// RXFLR 0x24 // see [READ ONLY] -#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0 - -// SR 0x28 // 7 bits [READ ONLY] -#define BIT_SR_BUSY BIT0 -#define BIT_SR_TFNF BIT1 -#define BIT_SR_TFE BIT2 -#define BIT_SR_RFNE BIT3 -#define BIT_SR_RFF BIT4 -#define BIT_SR_TXE BIT5 -#define BIT_SR_DCOL BIT6 - -// IMR 0x2c // see -#define BIT_SHIFT_IMR_TXEIM 0 -#define BIT_MASK_IMR_TXEIM 0x1 -// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM) -#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM)) - -#define BIT_SHIFT_IMR_TXOIM 1 -#define BIT_MASK_IMR_TXOIM 0x1 -// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM) -#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM)) - -#define BIT_SHIFT_IMR_RXUIM 2 -#define BIT_MASK_IMR_RXUIM 0x1 -// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM) -#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM)) - -#define BIT_SHIFT_IMR_RXOIM 3 -#define BIT_MASK_IMR_RXOIM 0x1 -// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM) -#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM)) - -#define BIT_SHIFT_IMR_RXFIM 4 -#define BIT_MASK_IMR_RXFIM 0x1 -// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM) -#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM)) - -#define BIT_SHIFT_IMR_MSTIM 5 -#define BIT_MASK_IMR_MSTIM 0x1 -// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM) -#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM)) - -#define BIT_IMR_TXEIM BIT0 -#define BIT_IMR_TXOIM BIT1 -#define BIT_IMR_RXUIM BIT2 -#define BIT_IMR_RXOIM BIT3 -#define BIT_IMR_RXFIM BIT4 -#define BIT_IMR_MSTIM BIT5 - -// ISR 0x30 // 6 bits [READ ONLY] -#define BIT_ISR_TXEIS BIT0 -#define BIT_ISR_TXOIS BIT1 -#define BIT_ISR_RXUIS BIT2 -#define BIT_ISR_RXOIS BIT3 -#define BIT_ISR_RXFIS BIT4 -#define BIT_ISR_MSTIS BIT5 - -// RISR 0x34 // 6 bits [READ ONLY] -#define BIT_RISR_TXEIR BIT0 -#define BIT_RISR_TXOIR BIT1 -#define BIT_RISR_RXUIR BIT2 -#define BIT_RISR_RXOIR BIT3 -#define BIT_RISR_RXFIR BIT4 -#define BIT_RISR_MSTIR BIT5 - -// TXOICR 0x38 // 1 bits [READ ONLY] -// RXOICR 0x3c // 1 bits [READ ONLY] -// RXUICR 0x40 // 1 bits [READ ONLY] -// MSTICR 0x44 // 1 bits [READ ONLY] -// ICR 0x48 // 1 bits [READ ONLY] - -// DMACR 0x4c // 2 bits -#define BIT_SHIFT_DMACR_RDMAE 0 -#define BIT_MASK_DMACR_RDMAE 0x1 -#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE) -#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE)) - -#define BIT_SHIFT_DMACR_TDMAE 1 -#define BIT_MASK_DMACR_TDMAE 0x1 -#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE) -#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE)) - -// DMATDLR 0x50 -#define BIT_SHIFT_DMATDLR_DMATDL 0 -#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0 -#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL) -#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL)) - -// DMARDLR 0x54 -#define BIT_SHIFT_DMARDLR_DMARDL 0 -#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0 -#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL) -#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL)) - -// IDR 0x58 // 32 bits [READ ONLY] -// COMP_VERSION 0x5c // 32 bits [READ ONLY] - -// DR 0x60 // 16 bits 0x60-0xEC -#define BIT_SHIFT_DR_DR 0 -#define BIT_MASK_DR_DR 0xFFFF -#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR) -#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR)) - -// RX_SAMPLE_DLY 0xF0 // 8 bits -#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0 -#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF -#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD) -#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD)) - -// RSVD_0 0xF4 // 32 bits -// RSVD_1 0xF8 // 32 bits -// RSVD_2 0xFC // 32 bits - -// SSI0 Pinmux -#define BIT_SHIFT_SSI0_PIN_EN 0 -#define BIT_MASK_SSI0_PIN_EN 0x1 -#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN) -#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN)) - -#define BIT_SHIFT_SSI0_PIN_SEL 1 -#define BIT_MASK_SSI0_PIN_SEL 0x7 -#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL) -#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL)) - -// SSI1 Pinmux -#define BIT_SHIFT_SSI1_PIN_EN 4 -#define BIT_MASK_SSI1_PIN_EN 0x1 -#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN) -#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN)) - -#define BIT_SHIFT_SSI1_PIN_SEL 5 -#define BIT_MASK_SSI1_PIN_SEL 0x7 -#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL) -#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL)) - -// SSI2 Pinmux -#define BIT_SHIFT_SSI2_PIN_EN 8 -#define BIT_MASK_SSI2_PIN_EN 0x1 -#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN) -#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN)) - -#define BIT_SHIFT_SSI2_PIN_SEL 9 -#define BIT_MASK_SSI2_PIN_SEL 0x7 -#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL) -#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL)) - -// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL) -#define BIT_SHIFT_SSI0_MULTI_CS_EN 28 -#define BIT_MASK_SSI0_MULTI_CS_EN 0x1 -#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN) -#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN)) - - -#define HAL_SSI_READ32(SsiIndex, addr) \ - HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) -#define HAL_SSI_WRITE32(SsiIndex, addr, value) \ - HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) -#define HAL_SSI_READ16(SsiIndex, addr) \ - HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) -#define HAL_SSI_WRITE16(SsiIndex, addr, value) \ - HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) -#define HAL_SSI_READ8(SsiIndex, addr) \ - HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) -#define HAL_SSI_WRITE8(SsiIndex, addr, value) \ - HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) - - -// SSI Pinmux Select -enum _SSI0_PINMUX_SELECT_ { - SSI0_MUX_TO_GPIOE = S0, - SSI0_MUX_TO_GPIOC = S1 -}; -typedef uint32_t SSI0_PINMUX_SELECT; -typedef uint32_t *PSSI0_PINMUX_SELECT; - -enum _SSI1_PINMUX_SELECT_ { - SSI1_MUX_TO_GPIOA = S0, - SSI1_MUX_TO_GPIOB = S1, - SSI1_MUX_TO_GPIOD = S2 -}; -typedef uint32_t SSI1_PINMUX_SELECT; -typedef uint32_t *PSSI1_PINMUX_SELECT; - -enum _SSI2_PINMUX_SELECT_ { - SSI2_MUX_TO_GPIOG = S0, - SSI2_MUX_TO_GPIOE = S1, - SSI2_MUX_TO_GPIOD = S2 -}; -typedef uint32_t SSI2_PINMUX_SELECT; -typedef uint32_t *PSSI2_PINMUX_SELECT; - -enum _SSI0_MULTI_CS_PINMUX_SELECT_ { - SSI0_CS_MUX_TO_GPIOE = S0, - SSI0_CS_MUX_TO_GPIOC = S1 -}; -typedef uint32_t SSI0_MULTI_CS_PINMUX_SELECT; -typedef uint32_t *PSSI0_MULTI_CS_PINMUX_SELECT; - -enum _SSI_CTRLR0_TMOD_ { - TMOD_TR = 0, - TMOD_TO = 1, - TMOD_RO = 2, - TMOD_EEPROM_R = 3 -}; -typedef uint32_t SSI_CTRLR0_TMOD; -typedef uint32_t *PSSI_CTRLR0_TMOD; - -enum _SSI_CTRLR0_SCPOL_ { - SCPOL_INACTIVE_IS_LOW = 0, - SCPOL_INACTIVE_IS_HIGH = 1 -}; -typedef uint32_t SSI_CTRLR0_SCPOL; -typedef uint32_t *PSSI_CTRLR0_SCPOL; - -enum _SSI_CTRLR0_SCPH_ { - SCPH_TOGGLES_IN_MIDDLE = 0, - SCPH_TOGGLES_AT_START = 1 -}; -typedef uint32_t SSI_CTRLR0_SCPH; -typedef uint32_t *PSSI_CTRLR0_SCPH; - -enum _SSI_CTRLR0_DFS_ { - DFS_4_BITS = 3, - DFS_5_BITS = 4, - DFS_6_BITS = 5, - DFS_7_BITS = 6, - DFS_8_BITS = 7, - DFS_9_BITS = 8, - DFS_10_BITS = 9, - DFS_11_BITS = 10, - DFS_12_BITS = 11, - DFS_13_BITS = 12, - DFS_14_BITS = 13, - DFS_15_BITS = 14, - DFS_16_BITS = 15, -}; -typedef uint32_t SSI_CTRLR0_DFS; -typedef uint32_t *PSSI_CTRLR0_DFS; - -enum _SSI_CTRLR0_CFS_ { - CFS_1_BIT = 0, - CFS_2_BITS = 1, - CFS_3_BITS = 2, - CFS_4_BITS = 3, - CFS_5_BITS = 4, - CFS_6_BITS = 5, - CFS_7_BITS = 6, - CFS_8_BITS = 7, - CFS_9_BITS = 8, - CFS_10_BITS = 9, - CFS_11_BITS = 10, - CFS_12_BITS = 11, - CFS_13_BITS = 12, - CFS_14_BITS = 13, - CFS_15_BITS = 14, - CFS_16_BITS = 15 -}; -typedef uint32_t SSI_CTRLR0_CFS; -typedef uint32_t *PSSI_CTRLR0_CFS; - -enum _SSI_CTRLR0_SLV_OE_ { - SLV_TXD_ENABLE = 0, - SLV_TXD_DISABLE = 1 -}; -typedef uint32_t SSI_CTRLR0_SLV_OE; -typedef uint32_t *PSSI_CTRLR0_SLV_OE; - -enum _SSI_ROLE_SELECT_ { - SSI_SLAVE = 0, - SSI_MASTER = 1 -}; -typedef uint32_t SSI_ROLE_SELECT; -typedef uint32_t *PSSI_ROLE_SELECT; - -enum _SSI_FRAME_FORMAT_ { - FRF_MOTOROLA_SPI = 0, - FRF_TI_SSP = 1, - FRF_NS_MICROWIRE = 2, - FRF_RSVD = 3 -}; -typedef uint32_t SSI_FRAME_FORMAT; -typedef uint32_t *PSSI_FRAME_FORMAT; - -enum _SSI_DMACR_ENABLE_ { - SSI_NODMA = 0, - SSI_RXDMA_ENABLE = 1, - SSI_TXDMA_ENABLE = 2, - SSI_TRDMA_ENABLE = 3 -}; -typedef uint32_t SSI_DMACR_ENABLE; -typedef uint32_t *PSSI_DMACR_ENABLE; - -enum _SSI_MWCR_HANDSHAKE_ { - MW_HANDSHAKE_DISABLE = 0, - MW_HANDSHAKE_ENABLE = 1 -}; -typedef uint32_t SSI_MWCR_HANDSHAKE; -typedef uint32_t *PSSI_MWCR_HANDSHAKE; - -enum _SSI_MWCR_DIRECTION_ { - MW_DIRECTION_SLAVE_TO_MASTER = 0, - MW_DIRECTION_MASTER_TO_SLAVE = 1 -}; -typedef uint32_t SSI_MWCR_DIRECTION; -typedef uint32_t *PSSI_MWCR_DIRECTION; - -enum _SSI_MWCR_TMOD_ { - MW_TMOD_NONSEQUENTIAL = 0, - MW_TMOD_SEQUENTIAL = 1 -}; -typedef uint32_t SSI_MWCR_TMOD; -typedef uint32_t *PSSI_MWCR_TMOD; - -enum _SSI_DATA_TRANSFER_MECHANISM_ { - SSI_DTM_BASIC, - SSI_DTM_INTERRUPT, - SSI_DTM_DMA -}; -typedef uint32_t SSI_DATA_TRANSFER_MECHANISM; -typedef uint32_t *PSSI_DATA_TRANSFER_MECHANISM; - - -_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value); -_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting); -_LONG_CALL_ROM_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role); -_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length); -_LONG_CALL_ROM_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor); -_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length); -_LONG_CALL_ROM_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex); -_LONG_CALL_ROM_ u32 HalSsiBusyRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ u32 HalSsiReadableRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor); -_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor); -_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor); -_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor); -_LONG_CALL_ROM_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor); - -_LONG_CALL_ROM_ VOID _SsiReadInterrupt(VOID *Adaptor); -_LONG_CALL_ROM_ VOID _SsiWriteInterrupt(VOID *Adaptor); -_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor); - -// ROM code patch -VOID _SsiReadInterruptRtl8195a(VOID *Adapter); -VOID _SsiWriteInterruptRtl8195a(VOID *Adapter); -HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor); -HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor); -HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor); -HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter); -HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter); -HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter); -VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate); -HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length); -HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length); -VOID HalSsiTxFIFOThresholdRtl8195a(VOID *Adaptor, u32 txftl); -HAL_Status HalSsiEnterCriticalRtl8195a(VOID * Data); -HAL_Status HalSsiExitCriticalRtl8195a(VOID * Data); -HAL_Status HalSsiIsTimeoutRtl8195a(u32 StartCount, u32 TimeoutCnt); -HAL_Status HalSsiStopRecvRtl8195a(VOID * Data); - -#if CONFIG_CHIP_E_CUT -HAL_Status HalSsiPinmuxEnableRtl8195a_V04(VOID *Adaptor); -HAL_Status HalSsiPinmuxDisableRtl8195a_V04(VOID * Adaptor); -VOID _SsiReadInterruptRtl8195a_V04(VOID *Adapter); -VOID _SsiWriteInterruptRtl8195a_V04(VOID *Adapter); -HAL_Status HalSsiInitRtl8195a_V04(VOID *Adaptor); -HAL_Status HalSsiSetFormatRtl8195a_V04(VOID * Adaptor); -HAL_Status HalSsiDeInitRtl8195a_V04(VOID *Adapter); -HAL_Status HalSsiIntReadRtl8195a_V04(VOID *Adapter, VOID *RxData, u32 Length); -HAL_Status HalSsiIntWriteRtl8195a_V04(VOID *Adapter, u8 *pTxData, u32 Length); -HAL_Status HalSsiClockOffRtl8195a_V04(VOID * Adapter); -HAL_Status HalSsiClockOnRtl8195a_V04(VOID * Adapter); -VOID HalSsiSetSclkRtl8195a_V04(VOID *Adapter, u32 ClkRate); -VOID HalSsiTxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter); -VOID HalSsiRxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter); -VOID HalSsiDmaInitRtl8195a_V04(VOID *Adapter); -HAL_Status HalSsiDmaSendRtl8195a_V04(IN VOID * Adapter, IN u8 * pTxData, IN u32 Length); -HAL_Status HalSsiDmaRecvRtl8195a_V04(IN VOID * Adapter, IN u8 * pRxData, IN u32 Length); -HAL_Status HalSsiDmaSendMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pTxData, u32 Length); -HAL_Status HalSsiDmaRecvMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pRxData, u32 Length); - -#endif - -#if CONFIG_GDMA_EN -VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter); -VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter); -VOID HalSsiDmaInitRtl8195a(VOID *Adapter); -HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length); -HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length); -HAL_Status HalSsiDmaSendMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length); -HAL_Status HalSsiDmaRecvMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length); - -#endif // end of "#ifdef CONFIG_GDMA_EN" - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h deleted file mode 100644 index dee486e2913..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h +++ /dev/null @@ -1,1105 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ -#ifndef __INC_RTL8195A_SYS_ON_BIT_H -#define __INC_RTL8195A_SYS_ON_BIT_H - -#define CPU_OPT_WIDTH 0x1F - -//2 REG_NOT_VALID - -//2 REG_SYS_PWR_CTRL - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID -#define BIT_SYS_PWR_SOC_EN BIT(2) -#define BIT_SYS_PWR_RET_MEM_EN BIT(1) -#define BIT_SYS_PWR_PEON_EN BIT(0) - -//2 REG_SYS_ISO_CTRL - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID -#define BIT_SYS_ISO_SYSPLL BIT(7) - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID -#define BIT_SYS_ISO_SOC BIT(2) -#define BIT_SYS_ISO_RET_MEM BIT(1) -#define BIT_SYS_ISO_PEON BIT(0) - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_SYS_FUNC_EN -#define BIT_SYS_AMACRO_EN BIT(31) -#define BIT_SYS_PWRON_TRAP_SHTDN_N BIT(30) -#define BIT_SYS_FEN_SIC_MST BIT(25) -#define BIT_SYS_FEN_SIC BIT(24) - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID -#define BIT_SOC_SYSPEON_EN BIT(4) - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID -#define BIT_SYS_FEN_EELDR BIT(0) - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_SYS_CLK_CTRL0 - -//2 REG_NOT_VALID -#define BIT_SOC_OCP_IOBUS_CK_EN BIT(2) -#define BIT_SYSON_CK_EELDR_EN BIT(1) -#define BIT_SYSON_CK_SYSREG_EN BIT(0) - -//2 REG_SYS_CLK_CTRL1 - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -#define BIT_SHIFT_PESOC_OCP_CPU_CK_SEL 4 -#define BIT_MASK_PESOC_OCP_CPU_CK_SEL 0x7 -#define BIT_PESOC_OCP_CPU_CK_SEL(x) (((x) & BIT_MASK_PESOC_OCP_CPU_CK_SEL) << BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) - - -//2 REG_NOT_VALID -#define BIT_PESOC_EELDR_CK_SEL BIT(0) - -//2 REG_SYS_SWR_CTRL3 - -//2 REG_RSV_CTRL - -//2 REG_RF_CTRL - -//2 REG_SYS_EFUSE_SYSCFG0 - -#define BIT_SHIFT_SYS_EEROM_SWR_PAR_05_00 24 -#define BIT_MASK_SYS_EEROM_SWR_PAR_05_00 0x3f -#define BIT_SYS_EEROM_SWR_PAR_05_00(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_05_00) << BIT_SHIFT_SYS_EEROM_SWR_PAR_05_00) - - -#define BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04 20 -#define BIT_MASK_SYS_EEROM_LDO_PAR_07_04 0xf -#define BIT_SYS_EEROM_LDO_PAR_07_04(x) (((x) & BIT_MASK_SYS_EEROM_LDO_PAR_07_04) << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04) - -#define BIT_SYS_CHIPPDN_EN BIT(17) -#define BIT_SYS_EEROM_B12V_EN BIT(16) - -#define BIT_SHIFT_SYS_EEROM_VID1 8 -#define BIT_MASK_SYS_EEROM_VID1 0xff -#define BIT_SYS_EEROM_VID1(x) (((x) & BIT_MASK_SYS_EEROM_VID1) << BIT_SHIFT_SYS_EEROM_VID1) - - -#define BIT_SHIFT_SYS_EEROM_VID0 0 -#define BIT_MASK_SYS_EEROM_VID0 0xff -#define BIT_SYS_EEROM_VID0(x) (((x) & BIT_MASK_SYS_EEROM_VID0) << BIT_SHIFT_SYS_EEROM_VID0) - - -//2 REG_SYS_EFUSE_SYSCFG1 - -#define BIT_SHIFT_SYS_PDSPL_STL 24 -#define BIT_MASK_SYS_PDSPL_STL 0x3 -#define BIT_SYS_PDSPL_STL(x) (((x) & BIT_MASK_SYS_PDSPL_STL) << BIT_SHIFT_SYS_PDSPL_STL) - - -#define BIT_SHIFT_SYS_PDSOC_STL 22 -#define BIT_MASK_SYS_PDSOC_STL 0x3 -#define BIT_SYS_PDSOC_STL(x) (((x) & BIT_MASK_SYS_PDSOC_STL) << BIT_SHIFT_SYS_PDSOC_STL) - - -#define BIT_SHIFT_SYS_PDPON_STL 20 -#define BIT_MASK_SYS_PDPON_STL 0x3 -#define BIT_SYS_PDPON_STL(x) (((x) & BIT_MASK_SYS_PDPON_STL) << BIT_SHIFT_SYS_PDPON_STL) - - -#define BIT_SHIFT_SYS_SWREG_XRT 18 -#define BIT_MASK_SYS_SWREG_XRT 0x3 -#define BIT_SYS_SWREG_XRT(x) (((x) & BIT_MASK_SYS_SWREG_XRT) << BIT_SHIFT_SYS_SWREG_XRT) - - -#define BIT_SHIFT_SYS_SWSLC_STL 16 -#define BIT_MASK_SYS_SWSLC_STL 0x3 -#define BIT_SYS_SWSLC_STL(x) (((x) & BIT_MASK_SYS_SWSLC_STL) << BIT_SHIFT_SYS_SWSLC_STL) - - -#define BIT_SHIFT_SYS_EEROM_SWR_PAR_46_45 14 -#define BIT_MASK_SYS_EEROM_SWR_PAR_46_45 0x3 -#define BIT_SYS_EEROM_SWR_PAR_46_45(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_46_45) << BIT_SHIFT_SYS_EEROM_SWR_PAR_46_45) - - -#define BIT_SHIFT_SYS_EEROM_SWR_PAR_40_39 12 -#define BIT_MASK_SYS_EEROM_SWR_PAR_40_39 0x3 -#define BIT_SYS_EEROM_SWR_PAR_40_39(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_40_39) << BIT_SHIFT_SYS_EEROM_SWR_PAR_40_39) - - -#define BIT_SHIFT_SYS_EEROM_SWR_PAR_33_26 4 -#define BIT_MASK_SYS_EEROM_SWR_PAR_33_26 0xff -#define BIT_SYS_EEROM_SWR_PAR_33_26(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_33_26) << BIT_SHIFT_SYS_EEROM_SWR_PAR_33_26) - - -#define BIT_SHIFT_SYS_EEROM_SWSLD_VOL 0 -#define BIT_MASK_SYS_EEROM_SWSLD_VOL 0x7 -#define BIT_SYS_EEROM_SWSLD_VOL(x) (((x) & BIT_MASK_SYS_EEROM_SWSLD_VOL) << BIT_SHIFT_SYS_EEROM_SWSLD_VOL) - - -//2 REG_SYS_EFUSE_SYSCFG2 - -#define BIT_SHIFT_SYS_EERROM_ANAPAR_SPLL_24_15 21 -#define BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15 0x3ff -#define BIT_SYS_EERROM_ANAPAR_SPLL_24_15(x) (((x) & BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15) << BIT_SHIFT_SYS_EERROM_ANAPAR_SPLL_24_15) - - -#define BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_05_02 16 -#define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02 0xf -#define BIT_SYS_EEROM_ANAPAR_SPLL_05_02(x) (((x) & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02) << BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_05_02) - - -#define BIT_SHIFT_SYS_EEROM_XTAL_STEL_SEL 12 -#define BIT_MASK_SYS_EEROM_XTAL_STEL_SEL 0x3 -#define BIT_SYS_EEROM_XTAL_STEL_SEL(x) (((x) & BIT_MASK_SYS_EEROM_XTAL_STEL_SEL) << BIT_SHIFT_SYS_EEROM_XTAL_STEL_SEL) - - -#define BIT_SHIFT_SYS_EEROM_XTAL_FREQ_SEL 8 -#define BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL 0xf -#define BIT_SYS_EEROM_XTAL_FREQ_SEL(x) (((x) & BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL) << BIT_SHIFT_SYS_EEROM_XTAL_FREQ_SEL) - - -//2 REG_SYS_EFUSE_SYSCFG3 - -#define BIT_SHIFT_SYS_DBG_PINGP_EN 28 -#define BIT_MASK_SYS_DBG_PINGP_EN 0xf -#define BIT_SYS_DBG_PINGP_EN(x) (((x) & BIT_MASK_SYS_DBG_PINGP_EN) << BIT_SHIFT_SYS_DBG_PINGP_EN) - - -#define BIT_SHIFT_SYS_DBG_SEL 16 -#define BIT_MASK_SYS_DBG_SEL 0xfff -#define BIT_SYS_DBG_SEL(x) (((x) & BIT_MASK_SYS_DBG_SEL) << BIT_SHIFT_SYS_DBG_SEL) - - -#define BIT_SHIFT_SYS_DBGBY3_LOC_SEL 14 -#define BIT_MASK_SYS_DBGBY3_LOC_SEL 0x3 -#define BIT_SYS_DBGBY3_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY3_LOC_SEL) << BIT_SHIFT_SYS_DBGBY3_LOC_SEL) - - -#define BIT_SHIFT_SYS_DBGBY2_LOC_SEL 12 -#define BIT_MASK_SYS_DBGBY2_LOC_SEL 0x3 -#define BIT_SYS_DBGBY2_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY2_LOC_SEL) << BIT_SHIFT_SYS_DBGBY2_LOC_SEL) - - -#define BIT_SHIFT_SYS_DBGBY1_LOC_SEL 10 -#define BIT_MASK_SYS_DBGBY1_LOC_SEL 0x3 -#define BIT_SYS_DBGBY1_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY1_LOC_SEL) << BIT_SHIFT_SYS_DBGBY1_LOC_SEL) - - -#define BIT_SHIFT_SYS_DBGBY0_LOC_SEL 8 -#define BIT_MASK_SYS_DBGBY0_LOC_SEL 0x3 -#define BIT_SYS_DBGBY0_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY0_LOC_SEL) << BIT_SHIFT_SYS_DBGBY0_LOC_SEL) - -#define BIT_SYS_EEROM_ANAPAR_SPLL_49 BIT(3) - -#define BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_27_25 0 -#define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_27_25 0x7 -#define BIT_SYS_EEROM_ANAPAR_SPLL_27_25(x) (((x) & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_27_25) << BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_27_25) - - -//2 REG_SYS_EFUSE_SYSCFG4 - -#define BIT_SHIFT_SYS_GPIOA_E2 1 -#define BIT_MASK_SYS_GPIOA_E2 0x7 -#define BIT_SYS_GPIOA_E2(x) (((x) & BIT_MASK_SYS_GPIOA_E2) << BIT_SHIFT_SYS_GPIOA_E2) - -#define BIT_SYS_GPIOA_H3L1 BIT(0) - -//2 REG_SYS_EFUSE_SYSCFG5 - -//2 REG_NOT_VALID - -//2 REG_SYS_EFUSE_SYSCFG6 - -#define BIT_SHIFT_SYS_SPIC_INIT_BAUD_RATE_SEL 26 -#define BIT_MASK_SYS_SPIC_INIT_BAUD_RATE_SEL 0x3 -#define BIT_SYS_SPIC_INIT_BAUD_RATE_SEL(x) (((x) & BIT_MASK_SYS_SPIC_INIT_BAUD_RATE_SEL) << BIT_SHIFT_SYS_SPIC_INIT_BAUD_RATE_SEL) - - -#define BIT_SHIFT_SYS_CPU_CLK_SEL 24 -#define BIT_MASK_SYS_CPU_CLK_SEL 0x3 -#define BIT_SYS_CPU_CLK_SEL(x) (((x) & BIT_MASK_SYS_CPU_CLK_SEL) << BIT_SHIFT_SYS_CPU_CLK_SEL) - - -//2 REG_SYS_EFUSE_SYSCFG7 -#define BIT_SYS_MEM_RMV_SIGN BIT(31) -#define BIT_SYS_MEM_RMV_1PRF1 BIT(29) -#define BIT_SYS_MEM_RMV_1PRF0 BIT(28) -#define BIT_SYS_MEM_RMV_1PSR BIT(27) -#define BIT_SYS_MEM_RMV_1PHSR BIT(26) -#define BIT_SYS_MEM_RMV_ROM BIT(25) - -#define BIT_SHIFT_SYS_MEM_RME_CPU 22 -#define BIT_MASK_SYS_MEM_RME_CPU 0x7 -#define BIT_SYS_MEM_RME_CPU(x) (((x) & BIT_MASK_SYS_MEM_RME_CPU) << BIT_SHIFT_SYS_MEM_RME_CPU) - - -#define BIT_SHIFT_SYS_MEM_RME_WLAN 19 -#define BIT_MASK_SYS_MEM_RME_WLAN 0x7 -#define BIT_SYS_MEM_RME_WLAN(x) (((x) & BIT_MASK_SYS_MEM_RME_WLAN) << BIT_SHIFT_SYS_MEM_RME_WLAN) - -#define BIT_SYS_MEM_RME_USB BIT(18) -#define BIT_SYS_MEM_RME_SDIO BIT(17) - -//2 REG_SYS_REGU_CTRL0 - -#define BIT_SHIFT_SYS_REGU_LDO25M_ADJ 20 -#define BIT_MASK_SYS_REGU_LDO25M_ADJ 0xf -#define BIT_SYS_REGU_LDO25M_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDO25M_ADJ) << BIT_SHIFT_SYS_REGU_LDO25M_ADJ) - -#define BIT_SYS_REGU_ANACK_4M_EN BIT(19) -#define BIT_SYS_REGU_ANACK_4M_SEL BIT(18) -#define BIT_SYS_REGU_PC_EF_EN BIT(17) -#define BIT_SYS_REGU_LDOH12_SLP_EN BIT(16) - -#define BIT_SHIFT_SYS_REGU_LDOH12_ADJ 12 -#define BIT_MASK_SYS_REGU_LDOH12_ADJ 0xf -#define BIT_SYS_REGU_LDOH12_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDOH12_ADJ) << BIT_SHIFT_SYS_REGU_LDOH12_ADJ) - - -#define BIT_SHIFT_SYS_REGU_LDO25E_ADJ 8 -#define BIT_MASK_SYS_REGU_LDO25E_ADJ 0xf -#define BIT_SYS_REGU_LDO25E_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDO25E_ADJ) << BIT_SHIFT_SYS_REGU_LDO25E_ADJ) - -#define BIT_SYS_REGU_DSLEPM_EN BIT(7) -#define BIT_SYS_REGU_PC_33V_EN BIT(3) -#define BIT_SYS_REGU_PC_EF25_EN BIT(2) -#define BIT_SYS_REGU_LDO25M_EN BIT(1) -#define BIT_SYS_REGU_LDO25E_EN BIT(0) - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_SYS_SWR_CTRL0 - -#define BIT_SHIFT_SYS_SWR12_COMP_R2 30 -#define BIT_MASK_SYS_SWR12_COMP_R2 0x3 -#define BIT_SYS_SWR12_COMP_R2(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R2) << BIT_SHIFT_SYS_SWR12_COMP_R2) - - -#define BIT_SHIFT_SYS_SWR12_COMP_R1 28 -#define BIT_MASK_SYS_SWR12_COMP_R1 0x3 -#define BIT_SYS_SWR12_COMP_R1(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R1) << BIT_SHIFT_SYS_SWR12_COMP_R1) - - -#define BIT_SHIFT_SYS_SWR12_COMP_C3 26 -#define BIT_MASK_SYS_SWR12_COMP_C3 0x3 -#define BIT_SYS_SWR12_COMP_C3(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C3) << BIT_SHIFT_SYS_SWR12_COMP_C3) - - -#define BIT_SHIFT_SYS_SWR12_COMP_C2 24 -#define BIT_MASK_SYS_SWR12_COMP_C2 0x3 -#define BIT_SYS_SWR12_COMP_C2(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C2) << BIT_SHIFT_SYS_SWR12_COMP_C2) - - -#define BIT_SHIFT_SYS_SWR12_COMP_C1 22 -#define BIT_MASK_SYS_SWR12_COMP_C1 0x3 -#define BIT_SYS_SWR12_COMP_C1(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C1) << BIT_SHIFT_SYS_SWR12_COMP_C1) - -#define BIT_SYS_SWR12_COMP_TYPE_L BIT(21) -#define BIT_SYS_SWR12_FPWM_MD BIT(20) - -#define BIT_SHIFT_SYS_SPSLDO_VOL 17 -#define BIT_MASK_SYS_SPSLDO_VOL 0x7 -#define BIT_SYS_SPSLDO_VOL(x) (((x) & BIT_MASK_SYS_SPSLDO_VOL) << BIT_SHIFT_SYS_SPSLDO_VOL) - - -#define BIT_SHIFT_SYS_SWR12_IN 14 -#define BIT_MASK_SYS_SWR12_IN 0x7 -#define BIT_SYS_SWR12_IN(x) (((x) & BIT_MASK_SYS_SWR12_IN) << BIT_SHIFT_SYS_SWR12_IN) - - -#define BIT_SHIFT_SYS_SWR12_STD 12 -#define BIT_MASK_SYS_SWR12_STD 0x3 -#define BIT_SYS_SWR12_STD(x) (((x) & BIT_MASK_SYS_SWR12_STD) << BIT_SHIFT_SYS_SWR12_STD) - - -#define BIT_SHIFT_SYS_SWR12_VOL 8 -#define BIT_MASK_SYS_SWR12_VOL 0xf -#define BIT_SYS_SWR12_VOL(x) (((x) & BIT_MASK_SYS_SWR12_VOL) << BIT_SHIFT_SYS_SWR12_VOL) - - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID -#define BIT_SYS_SWR_EN BIT(1) -#define BIT_SYS_SWR_LDO_EN BIT(0) - -//2 REG_SYS_SWR_CTRL1 -#define BIT_SYS_SW12_PFM_SEL BIT(25) -#define BIT_SYS_SW12_AUTO_ZCD_L BIT(24) -#define BIT_SYS_SW12_AUTO_MODE BIT(23) -#define BIT_SYS_SW12_LDOF_L BIT(22) -#define BIT_SYS_SW12_OCPS_L BIT(21) - -#define BIT_SHIFT_SYS_SW12_TBOX 17 -#define BIT_MASK_SYS_SW12_TBOX 0x3 -#define BIT_SYS_SW12_TBOX(x) (((x) & BIT_MASK_SYS_SW12_TBOX) << BIT_SHIFT_SYS_SW12_TBOX) - - -#define BIT_SHIFT_SYS_SW12_NONOVRLAP_DLY 15 -#define BIT_MASK_SYS_SW12_NONOVRLAP_DLY 0x3 -#define BIT_SYS_SW12_NONOVRLAP_DLY(x) (((x) & BIT_MASK_SYS_SW12_NONOVRLAP_DLY) << BIT_SHIFT_SYS_SW12_NONOVRLAP_DLY) - -#define BIT_SYS_SW12_CLAMP_DUTY BIT(14) -#define BIT_SYS_SWR12_BYPASS_SSR BIT(13) -#define BIT_SYS_SWR12_ZCDOUT_EN BIT(12) -#define BIT_SYS_SWR12_POW_ZCD BIT(11) -#define BIT_SYS_SW12_AREN BIT(10) - -#define BIT_SHIFT_SYS_SWR12_OCP_CUR 7 -#define BIT_MASK_SYS_SWR12_OCP_CUR 0x7 -#define BIT_SYS_SWR12_OCP_CUR(x) (((x) & BIT_MASK_SYS_SWR12_OCP_CUR) << BIT_SHIFT_SYS_SWR12_OCP_CUR) - -#define BIT_SYS_SWR12_OCP_EN BIT(6) - -#define BIT_SHIFT_SYS_SWR12_SAWTOOTH_CF_L 4 -#define BIT_MASK_SYS_SWR12_SAWTOOTH_CF_L 0x3 -#define BIT_SYS_SWR12_SAWTOOTH_CF_L(x) (((x) & BIT_MASK_SYS_SWR12_SAWTOOTH_CF_L) << BIT_SHIFT_SYS_SWR12_SAWTOOTH_CF_L) - - -#define BIT_SHIFT_SYS_SWR12_SAWTOOTH_CFC_L 2 -#define BIT_MASK_SYS_SWR12_SAWTOOTH_CFC_L 0x3 -#define BIT_SYS_SWR12_SAWTOOTH_CFC_L(x) (((x) & BIT_MASK_SYS_SWR12_SAWTOOTH_CFC_L) << BIT_SHIFT_SYS_SWR12_SAWTOOTH_CFC_L) - - -#define BIT_SHIFT_SYS_SWR12_COMP_R3 0 -#define BIT_MASK_SYS_SWR12_COMP_R3 0x3 -#define BIT_SYS_SWR12_COMP_R3(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R3) << BIT_SHIFT_SYS_SWR12_COMP_R3) - - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_SYS_XTAL_CTRL0 -#define BIT_SYS_XTAL_XQSEL BIT(31) -#define BIT_SYS_XTAL_XQSEL_RF BIT(30) - -#define BIT_SHIFT_SYS_XTAL_SC_XO 24 -#define BIT_MASK_SYS_XTAL_SC_XO 0x3f -#define BIT_SYS_XTAL_SC_XO(x) (((x) & BIT_MASK_SYS_XTAL_SC_XO) << BIT_SHIFT_SYS_XTAL_SC_XO) - - -#define BIT_SHIFT_SYS_XTAL_SC_XI 18 -#define BIT_MASK_SYS_XTAL_SC_XI 0x3f -#define BIT_SYS_XTAL_SC_XI(x) (((x) & BIT_MASK_SYS_XTAL_SC_XI) << BIT_SHIFT_SYS_XTAL_SC_XI) - - -#define BIT_SHIFT_SYS_XTAL_GMN 13 -#define BIT_MASK_SYS_XTAL_GMN 0x1f -#define BIT_SYS_XTAL_GMN(x) (((x) & BIT_MASK_SYS_XTAL_GMN) << BIT_SHIFT_SYS_XTAL_GMN) - - -#define BIT_SHIFT_SYS_XTAL_GMP 8 -#define BIT_MASK_SYS_XTAL_GMP 0x1f -#define BIT_SYS_XTAL_GMP(x) (((x) & BIT_MASK_SYS_XTAL_GMP) << BIT_SHIFT_SYS_XTAL_GMP) - -#define BIT_SYS_XTAL_EN BIT(1) -#define BIT_SYS_XTAL_BGMB_EN BIT(0) - -//2 REG_SYS_XTAL_CTRL1 - -#define BIT_SHIFT_SYS_XTAL_COUNTER_MUX 25 -#define BIT_MASK_SYS_XTAL_COUNTER_MUX 0x3 -#define BIT_SYS_XTAL_COUNTER_MUX(x) (((x) & BIT_MASK_SYS_XTAL_COUNTER_MUX) << BIT_SHIFT_SYS_XTAL_COUNTER_MUX) - -#define BIT_SYS_XTAL_DELAY_SYSPLL BIT(24) -#define BIT_SYS_XTAL_DELAY_USB BIT(23) -#define BIT_SYS_XTAL_DELAY_WLAFE BIT(22) -#define BIT_SYS_XTAL_AGPIO_SEL BIT(21) - -#define BIT_SHIFT_SYS_XTAL_DRV_AGPIO 19 -#define BIT_MASK_SYS_XTAL_DRV_AGPIO 0x3 -#define BIT_SYS_XTAL_DRV_AGPIO(x) (((x) & BIT_MASK_SYS_XTAL_DRV_AGPIO) << BIT_SHIFT_SYS_XTAL_DRV_AGPIO) - - -#define BIT_SHIFT_SYS_XTAL_AGPIO 16 -#define BIT_MASK_SYS_XTAL_AGPIO 0x7 -#define BIT_SYS_XTAL_AGPIO(x) (((x) & BIT_MASK_SYS_XTAL_AGPIO) << BIT_SHIFT_SYS_XTAL_AGPIO) - - -#define BIT_SHIFT_SYS_XTAL_DRV_SYSPLL 14 -#define BIT_MASK_SYS_XTAL_DRV_SYSPLL 0x3 -#define BIT_SYS_XTAL_DRV_SYSPLL(x) (((x) & BIT_MASK_SYS_XTAL_DRV_SYSPLL) << BIT_SHIFT_SYS_XTAL_DRV_SYSPLL) - -#define BIT_SYS_XTAL_GATE_SYSPLL BIT(13) - -#define BIT_SHIFT_SYS_XTAL_DRV_USB 11 -#define BIT_MASK_SYS_XTAL_DRV_USB 0x3 -#define BIT_SYS_XTAL_DRV_USB(x) (((x) & BIT_MASK_SYS_XTAL_DRV_USB) << BIT_SHIFT_SYS_XTAL_DRV_USB) - -#define BIT_SYS_XTAL_GATE_USB BIT(10) - -#define BIT_SHIFT_SYS_XTAL_DRV_WLAFE 8 -#define BIT_MASK_SYS_XTAL_DRV_WLAFE 0x3 -#define BIT_SYS_XTAL_DRV_WLAFE(x) (((x) & BIT_MASK_SYS_XTAL_DRV_WLAFE) << BIT_SHIFT_SYS_XTAL_DRV_WLAFE) - -#define BIT_SYS_XTAL_GATE_WLAFE BIT(7) - -#define BIT_SHIFT_SYS_XTAL_DRV_RF2 5 -#define BIT_MASK_SYS_XTAL_DRV_RF2 0x3 -#define BIT_SYS_XTAL_DRV_RF2(x) (((x) & BIT_MASK_SYS_XTAL_DRV_RF2) << BIT_SHIFT_SYS_XTAL_DRV_RF2) - -#define BIT_SYS_XTAL_GATE_RF2 BIT(4) - -#define BIT_SHIFT_SYS_XTAL_DRV_RF1 3 -#define BIT_MASK_SYS_XTAL_DRV_RF1 0x3 -#define BIT_SYS_XTAL_DRV_RF1(x) (((x) & BIT_MASK_SYS_XTAL_DRV_RF1) << BIT_SHIFT_SYS_XTAL_DRV_RF1) - -#define BIT_SYS_XTAL_GATE_RF1 BIT(1) - -#define BIT_SHIFT_SYS_XTAL_LDO 0 -#define BIT_MASK_SYS_XTAL_LDO 0x3 -#define BIT_SYS_XTAL_LDO(x) (((x) & BIT_MASK_SYS_XTAL_LDO) << BIT_SHIFT_SYS_XTAL_LDO) - - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_SYS_SYSPLL_CTRL0 - -#define BIT_SHIFT_SYS_SYSPLL_LPF_R3 29 -#define BIT_MASK_SYS_SYSPLL_LPF_R3 0x7 -#define BIT_SYS_SYSPLL_LPF_R3(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_R3) << BIT_SHIFT_SYS_SYSPLL_LPF_R3) - - -#define BIT_SHIFT_SYS_SYSPLL_LPF_CS 27 -#define BIT_MASK_SYS_SYSPLL_LPF_CS 0x3 -#define BIT_SYS_SYSPLL_LPF_CS(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_CS) << BIT_SHIFT_SYS_SYSPLL_LPF_CS) - - -#define BIT_SHIFT_SYS_SYSPLL_LPF_CP 25 -#define BIT_MASK_SYS_SYSPLL_LPF_CP 0x3 -#define BIT_SYS_SYSPLL_LPF_CP(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_CP) << BIT_SHIFT_SYS_SYSPLL_LPF_CP) - - -#define BIT_SHIFT_SYS_SYSPLL_LPF_C3 23 -#define BIT_MASK_SYS_SYSPLL_LPF_C3 0x3 -#define BIT_SYS_SYSPLL_LPF_C3(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_C3) << BIT_SHIFT_SYS_SYSPLL_LPF_C3) - -#define BIT_SYS_SYSPLL_WDOG_ENB BIT(22) -#define BIT_SYS_SYSPLL_CKTST_EN BIT(21) - -#define BIT_SHIFT_SYS_SYSPLL_MONCK_SEL 18 -#define BIT_MASK_SYS_SYSPLL_MONCK_SEL 0x7 -#define BIT_SYS_SYSPLL_MONCK_SEL(x) (((x) & BIT_MASK_SYS_SYSPLL_MONCK_SEL) << BIT_SHIFT_SYS_SYSPLL_MONCK_SEL) - - -#define BIT_SHIFT_SYS_SYSPLL_CP_IOFFSET 13 -#define BIT_MASK_SYS_SYSPLL_CP_IOFFSET 0x1f -#define BIT_SYS_SYSPLL_CP_IOFFSET(x) (((x) & BIT_MASK_SYS_SYSPLL_CP_IOFFSET) << BIT_SHIFT_SYS_SYSPLL_CP_IOFFSET) - -#define BIT_SYS_SYSPLL_CP_IDOUBLE BIT(12) - -#define BIT_SHIFT_SYS_SYSPLL_CP_BIAS 9 -#define BIT_MASK_SYS_SYSPLL_CP_BIAS 0x7 -#define BIT_SYS_SYSPLL_CP_BIAS(x) (((x) & BIT_MASK_SYS_SYSPLL_CP_BIAS) << BIT_SHIFT_SYS_SYSPLL_CP_BIAS) - -#define BIT_SYS_SYSPLL_FREF_EDGE BIT(8) -#define BIT_SYS_SYSPLL_EN BIT(1) -#define BIT_SYS_SYSPLL_LVPC_EN BIT(0) - -//2 REG_SYS_SYSPLL_CTRL1 -#define BIT_SYS_SYSPLL_CK500K_SEL BIT(15) -#define BIT_SYS_SYSPLL_CK200M_EN BIT(14) -#define BIT_SYS_SYSPLL_CKSDR_EN BIT(13) - -#define BIT_SHIFT_SYS_SYSPLL_CKSDR_DIV 11 -#define BIT_MASK_SYS_SYSPLL_CKSDR_DIV 0x3 -#define BIT_SYS_SYSPLL_CKSDR_DIV(x) (((x) & BIT_MASK_SYS_SYSPLL_CKSDR_DIV) << BIT_SHIFT_SYS_SYSPLL_CKSDR_DIV) - -#define BIT_SYS_SYSPLL_CK24P576_EN BIT(9) -#define BIT_SYS_SYSPLL_CK22P5792_EN BIT(8) -#define BIT_SYS_SYSPLL_CK_PS_EN BIT(6) - -#define BIT_SHIFT_SYS_SYSPLL_CK_PS_SEL 3 -#define BIT_MASK_SYS_SYSPLL_CK_PS_SEL 0x7 -#define BIT_SYS_SYSPLL_CK_PS_SEL(x) (((x) & BIT_MASK_SYS_SYSPLL_CK_PS_SEL) << BIT_SHIFT_SYS_SYSPLL_CK_PS_SEL) - - -#define BIT_SHIFT_SYS_SYSPLL_LPF_RS 0 -#define BIT_MASK_SYS_SYSPLL_LPF_RS 0x7 -#define BIT_SYS_SYSPLL_LPF_RS(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_RS) << BIT_SHIFT_SYS_SYSPLL_LPF_RS) - - -//2 REG_SYS_SYSPLL_CTRL2 - -#define BIT_SHIFT_XTAL_DRV_RF_LATCH 0 -#define BIT_MASK_XTAL_DRV_RF_LATCH 0xffffffffL -#define BIT_XTAL_DRV_RF_LATCH(x) (((x) & BIT_MASK_XTAL_DRV_RF_LATCH) << BIT_SHIFT_XTAL_DRV_RF_LATCH) - - -//2 REG_RSVD - -//2 REG_RSVD - -#define BIT_SHIFT_PESOC_CPU_OCP_CK_SEL 0 -#define BIT_MASK_PESOC_CPU_OCP_CK_SEL 0x7 -#define BIT_PESOC_CPU_OCP_CK_SEL(x) (((x) & BIT_MASK_PESOC_CPU_OCP_CK_SEL) << BIT_SHIFT_PESOC_CPU_OCP_CK_SEL) - - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_ - -//2 REG_SYS_ANA_TIM_CTRL - -#define BIT_SHIFT_SYS_ANACK_TU_TIME 16 -#define BIT_MASK_SYS_ANACK_TU_TIME 0x3f -#define BIT_SYS_ANACK_TU_TIME(x) (((x) & BIT_MASK_SYS_ANACK_TU_TIME) << BIT_SHIFT_SYS_ANACK_TU_TIME) - -#define BIT_SYS_DSBYCNT_EN BIT(15) - -#define BIT_SHIFT_SYS_DSTDY_TIM_SCAL 8 -#define BIT_MASK_SYS_DSTDY_TIM_SCAL 0xf -#define BIT_SYS_DSTDY_TIM_SCAL(x) (((x) & BIT_MASK_SYS_DSTDY_TIM_SCAL) << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) - - -#define BIT_SHIFT_SYS_DSTBY_TIM_PERIOD 0 -#define BIT_MASK_SYS_DSTBY_TIM_PERIOD 0xff -#define BIT_SYS_DSTBY_TIM_PERIOD(x) (((x) & BIT_MASK_SYS_DSTBY_TIM_PERIOD) << BIT_SHIFT_SYS_DSTBY_TIM_PERIOD) - - -//2 REG_SYS_DSLP_TIM_CTRL - -#define BIT_SHIFT_SYS_REGU_ASIF_EN 24 -#define BIT_MASK_SYS_REGU_ASIF_EN 0xff -#define BIT_SYS_REGU_ASIF_EN(x) (((x) & BIT_MASK_SYS_REGU_ASIF_EN) << BIT_SHIFT_SYS_REGU_ASIF_EN) - - -#define BIT_SHIFT_SYS_REGU_ASIF_THP_DA 20 -#define BIT_MASK_SYS_REGU_ASIF_THP_DA 0x3 -#define BIT_SYS_REGU_ASIF_THP_DA(x) (((x) & BIT_MASK_SYS_REGU_ASIF_THP_DA) << BIT_SHIFT_SYS_REGU_ASIF_THP_DA) - - -#define BIT_SHIFT_SYS_REGU_ASIF_TPD_CK 18 -#define BIT_MASK_SYS_REGU_ASIF_TPD_CK 0x3 -#define BIT_SYS_REGU_ASIF_TPD_CK(x) (((x) & BIT_MASK_SYS_REGU_ASIF_TPD_CK) << BIT_SHIFT_SYS_REGU_ASIF_TPD_CK) - - -#define BIT_SHIFT_SYS_REGU_ASIF_TSP_DA 16 -#define BIT_MASK_SYS_REGU_ASIF_TSP_DA 0x3 -#define BIT_SYS_REGU_ASIF_TSP_DA(x) (((x) & BIT_MASK_SYS_REGU_ASIF_TSP_DA) << BIT_SHIFT_SYS_REGU_ASIF_TSP_DA) - -#define BIT_SYS_REGU_ASIF_POLL BIT(15) -#define BIT_SYS_REGU_ASIF_MODE BIT(14) -#define BIT_SYS_REGU_ASIF_WE BIT(12) - -#define BIT_SHIFT_SYS_REGU_ASIF_AD 8 -#define BIT_MASK_SYS_REGU_ASIF_AD 0xf -#define BIT_SYS_REGU_ASIF_AD(x) (((x) & BIT_MASK_SYS_REGU_ASIF_AD) << BIT_SHIFT_SYS_REGU_ASIF_AD) - - -#define BIT_SHIFT_SYS_REGU_ASIF_WD 0 -#define BIT_MASK_SYS_REGU_ASIF_WD 0xff -#define BIT_SYS_REGU_ASIF_WD(x) (((x) & BIT_MASK_SYS_REGU_ASIF_WD) << BIT_SHIFT_SYS_REGU_ASIF_WD) - - -//2 REG_SYS_DSLP_TIM_CAL_CTRL -#define BIT_SYS_DSLP_TIM_EN BIT(24) - -#define BIT_SHIFT_SYS_DSLP_TIM_PERIOD 0 -#define BIT_MASK_SYS_DSLP_TIM_PERIOD 0x7fffff -#define BIT_SYS_DSLP_TIM_PERIOD(x) (((x) & BIT_MASK_SYS_DSLP_TIM_PERIOD) << BIT_SHIFT_SYS_DSLP_TIM_PERIOD) - - -//2 REG_RSVD - -//2 REG_SYS_DEBUG_CTRL -#define BIT_SYS_DBG_PIN_EN BIT(0) - -//2 REG_SYS_PINMUX_CTRL -#define BIT_EEPROM_PIN_EN BIT(4) -#define BIT_SIC_PIN_EN BIT(0) - -//2 REG_SYS_GPIO_DSTBY_WAKE_CTRL0 -#define BIT_SYS_GPIOE3_WEVENT_STS BIT(27) -#define BIT_SYS_GPIOD5_WEVENT_STS BIT(26) -#define BIT_SYS_GPIOC7_WEVENT_STS BIT(25) -#define BIT_SYS_GPIOA5_WEVENT_STS BIT(24) -#define BIT_SYS_GPIO_GPE3_PULL_CTRL_EN BIT(19) -#define BIT_SYS_GPIO_GPD5_PULL_CTRL_EN BIT(18) -#define BIT_SYS_GPIO_GPC7_PULL_CTRL_EN BIT(17) -#define BIT_SYS_GPIO_GPA5_PULL_CTRL_EN BIT(16) -#define BIT_SYS_GPIOE3_WINT_MODE BIT(11) -#define BIT_SYS_GPIOD5_WINT_MODE BIT(10) -#define BIT_SYS_GPIOC7_WINT_MODE BIT(9) -#define BIT_SYS_GPIOA5_WINT_MODE BIT(8) -#define BIT_SYS_GPIOE3_PIN_EN BIT(3) -#define BIT_SYS_GPIOD5_PIN_EN BIT(2) -#define BIT_SYS_GPIOC7_PIN_EN BIT(1) -#define BIT_SYS_GPIOA5_PIN_EN BIT(0) - -//2 REG_SYS_GPIO_DSTBY_WAKE_CTRL1 -#define BIT_SYS_GPIOE3_SHTDN_N BIT(19) -#define BIT_SYS_GPIOD5_SHTDN_N BIT(18) -#define BIT_SYS_GPIOC7_SHTDN_N BIT(17) -#define BIT_SYS_GPIOA5_SHTDN_N BIT(16) - -#define BIT_SHIFT_SYS_WINT_DEBOUNCE_TIM_SCAL 8 -#define BIT_MASK_SYS_WINT_DEBOUNCE_TIM_SCAL 0x3 -#define BIT_SYS_WINT_DEBOUNCE_TIM_SCAL(x) (((x) & BIT_MASK_SYS_WINT_DEBOUNCE_TIM_SCAL) << BIT_SHIFT_SYS_WINT_DEBOUNCE_TIM_SCAL) - -#define BIT_SYS_GPIOE3_WINT_DEBOUNCE_EN BIT(3) -#define BIT_SYS_GPIOD5_WINT_DEBOUNCE_EN BIT(2) -#define BIT_SYS_GPIOC7_WINT_DEBOUNCE_EN BIT(1) -#define BIT_SYS_GPIOA5_WINT_DEBOUNCE_EN BIT(0) - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_SYS_DEBUG_REG - -#define BIT_SHIFT_SYS_DBG_VALUE 0 -#define BIT_MASK_SYS_DBG_VALUE 0xffffffffL -#define BIT_SYS_DBG_VALUE(x) (((x) & BIT_MASK_SYS_DBG_VALUE) << BIT_SHIFT_SYS_DBG_VALUE) - - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_SYS_EEPROM_CTRL0 - -#define BIT_SHIFT_EFUSE_UNLOCK 24 -#define BIT_MASK_EFUSE_UNLOCK 0xff -#define BIT_EFUSE_UNLOCK(x) (((x) & BIT_MASK_EFUSE_UNLOCK) << BIT_SHIFT_EFUSE_UNLOCK) - - -//2 REG_NOT_VALID -#define BIT_SYS_EFUSE_LDALL BIT(16) - -#define BIT_SHIFT_SYS_EEPROM_VPDIDX 8 -#define BIT_MASK_SYS_EEPROM_VPDIDX 0xff -#define BIT_SYS_EEPROM_VPDIDX(x) (((x) & BIT_MASK_SYS_EEPROM_VPDIDX) << BIT_SHIFT_SYS_EEPROM_VPDIDX) - - -#define BIT_SHIFT_SYS_EEPROM_MD 6 -#define BIT_MASK_SYS_EEPROM_MD 0x3 -#define BIT_SYS_EEPROM_MD(x) (((x) & BIT_MASK_SYS_EEPROM_MD) << BIT_SHIFT_SYS_EEPROM_MD) - -#define BIT_SYS_AUTOLOAD_SUS BIT(5) -#define BIT_SYS_EEPROM_SEL BIT(4) -#define BIT_SYS_EEPROM_EECS BIT(3) -#define BIT_SYS_EEPROM_EESK BIT(2) -#define BIT_SYS_EEPROM_EEDI BIT(1) -#define BIT_SYS_EEPROM_EEDO BIT(0) - -//2 REG_SYS_EEPROM_CTRL1 - -#define BIT_SHIFT_SYS_EEPROM_VPD 0 -#define BIT_MASK_SYS_EEPROM_VPD 0xffffffffL -#define BIT_SYS_EEPROM_VPD(x) (((x) & BIT_MASK_SYS_EEPROM_VPD) << BIT_SHIFT_SYS_EEPROM_VPD) - - -//2 REG_SYS_EFUSE_CTRL -#define BIT_SYS_EF_RWFLAG BIT(31) - -#define BIT_SHIFT_SYS_EF_PGPD 28 -#define BIT_MASK_SYS_EF_PGPD 0x7 -#define BIT_SYS_EF_PGPD(x) (((x) & BIT_MASK_SYS_EF_PGPD) << BIT_SHIFT_SYS_EF_PGPD) - - -#define BIT_SHIFT_SYS_EF_RDT 24 -#define BIT_MASK_SYS_EF_RDT 0xf -#define BIT_SYS_EF_RDT(x) (((x) & BIT_MASK_SYS_EF_RDT) << BIT_SHIFT_SYS_EF_RDT) - - -#define BIT_SHIFT_SYS_EF_PGTS 20 -#define BIT_MASK_SYS_EF_PGTS 0xf -#define BIT_SYS_EF_PGTS(x) (((x) & BIT_MASK_SYS_EF_PGTS) << BIT_SHIFT_SYS_EF_PGTS) - -#define BIT_SYS_EF_PDWN BIT(19) -#define BIT_SYS_EF_ALDEN BIT(18) - -#define BIT_SHIFT_SYS_EF_ADDR 8 -#define BIT_MASK_SYS_EF_ADDR 0x3ff -#define BIT_SYS_EF_ADDR(x) (((x) & BIT_MASK_SYS_EF_ADDR) << BIT_SHIFT_SYS_EF_ADDR) - - -#define BIT_SHIFT_SYS_EF_DATA 0 -#define BIT_MASK_SYS_EF_DATA 0xff -#define BIT_SYS_EF_DATA(x) (((x) & BIT_MASK_SYS_EF_DATA) << BIT_SHIFT_SYS_EF_DATA) - - -//2 REG_SYS_EFUSE_TEST -#define BIT_SYS_EF_CRES_SEL BIT(26) - -#define BIT_SHIFT_SYS_EF_SCAN_START 16 -#define BIT_MASK_SYS_EF_SCAN_START 0x1ff -#define BIT_SYS_EF_SCAN_START(x) (((x) & BIT_MASK_SYS_EF_SCAN_START) << BIT_SHIFT_SYS_EF_SCAN_START) - - -#define BIT_SHIFT_SYS_EF_SCAN_END 12 -#define BIT_MASK_SYS_EF_SCAN_END 0xf -#define BIT_SYS_EF_SCAN_END(x) (((x) & BIT_MASK_SYS_EF_SCAN_END) << BIT_SHIFT_SYS_EF_SCAN_END) - -#define BIT_SYS_EF_FORCE_PGMEN BIT(11) - -#define BIT_SHIFT_SYS_EF_CELL_SEL 8 -#define BIT_MASK_SYS_EF_CELL_SEL 0x3 -#define BIT_SYS_EF_CELL_SEL(x) (((x) & BIT_MASK_SYS_EF_CELL_SEL) << BIT_SHIFT_SYS_EF_CELL_SEL) - -#define BIT_SYS_EF_TRPT BIT(7) - -#define BIT_SHIFT_SYS_EF_SCAN_TTHD 0 -#define BIT_MASK_SYS_EF_SCAN_TTHD 0x7f -#define BIT_SYS_EF_SCAN_TTHD(x) (((x) & BIT_MASK_SYS_EF_SCAN_TTHD) << BIT_SHIFT_SYS_EF_SCAN_TTHD) - - -//2 REG_SYS_DSTBY_INFO0 - -//2 REG_NOT_VALID - -//2 REG_SYS_DSTBY_INFO1 - -//2 REG_SYS_DSTBY_INFO2 - -//2 REG_NOT_VALID - -//2 REG_SYS_DSTBY_INFO3 - -//2 REG_SYS_SLP_WAKE_EVENT_MSK0 -#define BIT_SYSON_WEVT_GPIO_DSTBY_MSK BIT(29) -#define BIT_SYSON_WEVT_A33_MSK BIT(28) -#define BIT_SYSON_WEVT_ADC_MSK BIT(26) -#define BIT_SYSON_WEVT_I2C_MSK BIT(24) -#define BIT_SYSON_WEVT_SPI_MSK BIT(22) -#define BIT_SYSON_WEVT_UART_MSK BIT(20) -#define BIT_SYSON_WEVT_USB_MSK BIT(16) -#define BIT_SYSON_WEVT_SDIO_MSK BIT(14) -#define BIT_SYSON_WEVT_NFC_MSK BIT(9) -#define BIT_SYSON_WEVT_WLAN_MSK BIT(8) -#define BIT_SYSON_WEVT_GPIO_MSK BIT(4) -#define BIT_SYSON_WEVT_CHIP_EN_MSK BIT(3) -#define BIT_SYSON_WEVT_OVER_CURRENT_MSK BIT(2) -#define BIT_SYSON_WEVT_GTIM_MSK BIT(1) -#define BIT_SYSON_WEVT_SYSTIM_MSK BIT(0) - -//2 REG_SYS_SLP_WAKE_EVENT_MSK1 - -//2 REG_SYS_SLP_WAKE_EVENT_STATUS0 -#define BIT_SYSON_WEVT_GPIO_DSTBY_STS BIT(29) -#define BIT_SYSON_WEVT_A33_STS BIT(28) -#define BIT_SYSON_WEVT_ADC_STS BIT(26) -#define BIT_SYSON_WEVT_I2C_STS BIT(24) -#define BIT_SYSON_WEVT_SPI_STS BIT(22) -#define BIT_SYSON_WEVT_UART_STS BIT(20) -#define BIT_SYSON_WEVT_USB_STS BIT(16) -#define BIT_SYSON_WEVT_SDIO_STS BIT(14) -#define BIT_SYSON_WEVT_NFC_STS BIT(9) -#define BIT_SYSON_WEVT_WLAN_STS BIT(8) -#define BIT_SYSON_WEVT_GPIO_STS BIT(4) -#define BIT_SYSON_WEVT_CHIP_EN_STS BIT(3) -#define BIT_SYSON_WEVT_OVER_CURRENT_STS BIT(2) -#define BIT_SYSON_WEVT_GTIM_STS BIT(1) -#define BIT_SYSON_WEVT_SYSTIM_STS BIT(0) - -//2 REG_SYS_SLP_WAKE_EVENT_STATUS1 - -//2 REG_SYS_SNF_WAKE_EVENT_MSK0 - -#define BIT_SHIFT_SYS_WKPERI_IMR0 1 -#define BIT_MASK_SYS_WKPERI_IMR0 0x7fffffffL -#define BIT_SYS_WKPERI_IMR0(x) (((x) & BIT_MASK_SYS_WKPERI_IMR0) << BIT_SHIFT_SYS_WKPERI_IMR0) - -#define BIT_SYSON_SNFEVT_ADC_MSK BIT(0) - -//2 REG_SYS_SNF_WAKE_EVENT_STATUS - -#define BIT_SHIFT_SYS_WKPERI_ISR0 1 -#define BIT_MASK_SYS_WKPERI_ISR0 0x7fffffffL -#define BIT_SYS_WKPERI_ISR0(x) (((x) & BIT_MASK_SYS_WKPERI_ISR0) << BIT_SHIFT_SYS_WKPERI_ISR0) - -#define BIT_SYSON_SNFEVT_ADC_STS BIT(0) - -//2 REG_SYS_PWRMGT_CTRL -#define BIT_SYSON_REGU_DSLP BIT(7) - -//2 REG_NOT_VALID -#define BIT_SYSON_PM_CMD_SLP BIT(2) -#define BIT_SYSON_PM_CMD_DSTBY BIT(1) -#define BIT_SYSON_PM_CMD_DSLP BIT(0) - -//2 REG_RSVD - -//2 REG_SYS_PWRMGT_OPTION -#define BIT_SYSON_PMOPT_NORM_SYSCLK_SEL BIT(30) -#define BIT_SYSON_PMOPT_NORM_SYSPLL_EN BIT(29) -#define BIT_SYSON_PMOPT_NORM_XTAL_EN BIT(28) -#define BIT_SYSON_PMOPT_NORM_EN_SOC BIT(27) -#define BIT_SYSON_PMOPT_NORM_EN_PWM BIT(26) -#define BIT_SYSON_PMOPT_NORM_EN_SWR BIT(25) -#define BIT_SYSON_PMOPT_NORM_LPLDO_SEL BIT(24) -#define BIT_SYSON_PMOPT_SNZ_SYSCLK_SEL BIT(22) -#define BIT_SYSON_PMOPT_SNZ_SYSPLL_EN BIT(21) -#define BIT_SYSON_PMOPT_SNZ_XTAL_EN BIT(20) -#define BIT_SYSON_PMOPT_SNZ_EN_SOC BIT(19) -#define BIT_SYSON_PMOPT_SNZ_EN_PWM BIT(18) -#define BIT_SYSON_PMOPT_SNZ_EN_SWR BIT(17) -#define BIT_SYSON_PMOPT_SNZ_LPLDO_SEL BIT(16) -#define BIT_SYSON_PMOPT_SLP_SYSCLK_SEL BIT(14) -#define BIT_SYSON_PMOPT_SLP_SYSPLL_EN BIT(13) -#define BIT_SYSON_PMOPT_SLP_XTAL_EN BIT(12) -#define BIT_SYSON_PMOPT_SLP_EN_SOC BIT(11) -#define BIT_SYSON_PMOPT_SLP_EN_PWM BIT(10) -#define BIT_SYSON_PMOPT_SLP_EN_SWR BIT(9) -#define BIT_SYSON_PMOPT_SLP_LPLDO_SEL BIT(8) -#define BIT_SYSON_PMOPT_DSTBY_SYSCLK_SEL BIT(6) -#define BIT_SYSON_PMOPT_DSTBY_SYSPLL_EN BIT(5) -#define BIT_SYSON_PMOPT_DSTBY_XTAL_EN BIT(4) -#define BIT_SYSON_PMOPT_DSTBY_EN_SOC BIT(3) -#define BIT_SYSON_PMOPT_DSTBY_EN_PWM BIT(2) -#define BIT_SYSON_PMOPT_DSTBY_EN_SWR BIT(1) -#define BIT_SYSON_PMOPT_DSTBY_LPLDO_SEL BIT(0) - -//2 REG_SYS_PWRMGT_OPTION_EXT -#define BIT_SYSON_PMOPT_SLP_ANACK_SEL BIT(2) -#define BIT_SYSON_PMOPT_SLP_ANACK_EN BIT(1) -#define BIT_SYSON_PMOPT_SLP_SWR_ADJ BIT(0) - -//2 REG_SYS_DSLP_WEVENT -#define BIT_SYSON_DSLP_GPIO BIT(2) -#define BIT_SYSON_DSLP_NFC BIT(1) -#define BIT_SYSON_DSLP_WTIMER33 BIT(0) - -//2 REG_SYS_PERI_MONITOR -#define BIT_SYSON_ISO33_NFC BIT(0) - -//2 REG_SYS_SYSTEM_CFG0 -#define BIT_SYSCFG_BD_PKG_SEL BIT(31) - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -#define BIT_SHIFT_VENDOR_ID 8 -#define BIT_MASK_VENDOR_ID 0xf -#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) - - -#define BIT_SHIFT_CHIP_VER 4 -#define BIT_MASK_CHIP_VER 0xf -#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) - - -#define BIT_SHIFT_RF_RL_ID 0 -#define BIT_MASK_RF_RL_ID 0xf -#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) - - -//2 REG_SYS_SYSTEM_CFG1 - -#define BIT_SHIFT_SYSCFG_TRP_ICFG 28 -#define BIT_MASK_SYSCFG_TRP_ICFG 0xf -#define BIT_SYSCFG_TRP_ICFG(x) (((x) & BIT_MASK_SYSCFG_TRP_ICFG) << BIT_SHIFT_SYSCFG_TRP_ICFG) - -#define BIT_SYSCFG_TRP_BOOT_SEL_ BIT(27) -#define BIT_SysCFG_TRP_SPSLDO_SEL BIT(26) -#define BIT_V15_VLD BIT(16) -#define BIT_SYS_SYSPLL_CLK_RDY BIT(9) -#define BIT_SYS_XCLK_VLD BIT(8) -#define BIT_SYSCFG_ALDN_STS BIT(0) - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - -//2 REG_RSVD - -//2 REG_NOT_VALID - -//2 REG_NOT_VALID - - -//================= Register Address Definition =====================// -#define REG_SYS_PWR_CTRL 0x0000 -#define REG_SYS_ISO_CTRL 0x0002 -#define REG_SYS_FUNC_EN 0x0008 -#define REG_SYS_CLK_CTRL0 0x0010 -#define REG_SYS_CLK_CTRL1 0x0014 -#define REG_SYS_EFUSE_SYSCFG0 0x0020 -#define REG_SYS_EFUSE_SYSCFG1 0x0024 -#define REG_SYS_EFUSE_SYSCFG2 0x0028 -#define REG_SYS_EFUSE_SYSCFG3 0x002C -#define REG_SYS_EFUSE_SYSCFG4 0x0030 -#define REG_SYS_EFUSE_SYSCFG5 0x0034 -#define REG_SYS_EFUSE_SYSCFG6 0x0038 -#define REG_SYS_EFUSE_SYSCFG7 0x003C -#define REG_SYS_REGU_CTRL0 0x0040 -#define REG_SYS_SWR_CTRL0 0x0048 -#define REG_SYS_SWR_CTRL1 0x004C -#define REG_SYS_XTAL_CTRL0 0x0060 -#define REG_SYS_XTAL_CTRL1 0x0064 -#define REG_SYS_SYSPLL_CTRL0 0x0070 -#define REG_SYS_SYSPLL_CTRL1 0x0074 -#define REG_SYS_SYSPLL_CTRL2 0x0078 -#define REG_SYS_ANA_TIM_CTRL 0x0090 -#define REG_SYS_DSLP_TIM_CTRL 0x0094 -#define REG_SYS_DSLP_TIM_CAL_CTRL 0x0098 -#define REG_SYS_DEBUG_CTRL 0x00A0 -#define REG_SYS_PINMUX_CTRL 0x00A4 -#define REG_SYS_GPIO_DSTBY_WAKE_CTRL0 0x00A8 -#define REG_SYS_GPIO_DSTBY_WAKE_CTRL1 0x00AC -#define REG_SYS_DEBUG_REG 0x00BC -#define REG_SYS_EEPROM_CTRL0 0x00E0 -#define REG_SYS_EEPROM_CTRL1 0x00E4 -#define REG_SYS_EFUSE_CTRL 0x00E8 -#define REG_SYS_EFUSE_TEST 0x00EC -#define REG_SYS_DSTBY_INFO0 0x00F0 -#define REG_SYS_DSTBY_INFO1 0x00F4 -#define REG_SYS_DSTBY_INFO2 0x00F8 -#define REG_SYS_DSTBY_INFO3 0x00FC -#define REG_SYS_SLP_WAKE_EVENT_MSK0 0x0100 -#define REG_SYS_SLP_WAKE_EVENT_MSK1 0x0104 -#define REG_SYS_SLP_WAKE_EVENT_STATUS0 0x0108 -#define REG_SYS_SLP_WAKE_EVENT_STATUS1 0x010C -#define REG_SYS_SNF_WAKE_EVENT_MSK0 0x0110 -#define REG_SYS_SNF_WAKE_EVENT_STATUS 0x0114 -#define REG_SYS_PWRMGT_CTRL 0x0118 -#define REG_SYS_PWRMGT_OPTION 0x0120 -#define REG_SYS_PWRMGT_OPTION_EXT 0x0124 -#define REG_SYS_DSLP_WEVENT 0x0130 -#define REG_SYS_PERI_MONITOR 0x0134 -#define REG_SYS_SYSTEM_CFG0 0x01F0 -#define REG_SYS_SYSTEM_CFG1 0x01F4 -#define REG_SYS_SYSTEM_CFG2 0x01F8 - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h deleted file mode 100644 index f8ad6fd821b..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h +++ /dev/null @@ -1,271 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _RTL8195A_TIMER_H_ -#define _RTL8195A_TIMER_H_ - - -#define TIMER_TICK_US 32 - -#define TIMER_LOAD_COUNT_OFF 0x00 -#define TIMER_CURRENT_VAL_OFF 0x04 -#define TIMER_CTL_REG_OFF 0x08 -#define TIMER_EOI_OFF 0x0c -#define TIMER_INT_STATUS_OFF 0x10 -#define TIMER_INTERVAL 0x14 -#define TIMERS_INT_STATUS_OFF 0xa0 -#define TIMERS_EOI_OFF 0xa4 -#define TIMERS_RAW_INT_STATUS_OFF 0xa8 -#define TIMERS_COMP_VER_OFF 0xac - -#define MAX_TIMER_VECTOR_TABLE_NUM 6 - -#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr) -#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value) -#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr) -#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value) -#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr) -#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value) - -_LONG_CALL_ u32 -HalGetTimerIdRtl8195a( - IN u32 *TimerID -); - -_LONG_CALL_ BOOL -HalTimerInitRtl8195a( - IN VOID *Data -); - -_LONG_CALL_ u32 -HalTimerReadCountRtl8195a( - IN u32 TimerId -); - -_LONG_CALL_ VOID -HalTimerIrqClearRtl8195a( - IN u32 TimerId -); - -_LONG_CALL_ VOID -HalTimerDisRtl8195a( - IN u32 TimerId -); - -_LONG_CALL_ VOID -HalTimerEnRtl8195a( - IN u32 TimerId -); - -_LONG_CALL_ VOID -HalTimerDumpRegRtl8195a( - IN u32 TimerId -); - -// ROM Code patch -HAL_Status -HalTimerInitRtl8195a_Patch( - IN VOID *Data -); - -u32 -HalTimerReadCountRtl8195a_Patch( - IN u32 TimerId -); - -VOID -HalTimerReLoadRtl8195a_Patch( - IN u32 TimerId, - IN u32 LoadUs -); - -VOID -HalTimerSyncRtl8195a( - IN u32 TimerId -); - -u32 -HalTimerReadCountRtl8195a_Patch( - IN u32 TimerId -); - -VOID -HalTimerIrqEnRtl8195a( - IN u32 TimerId -); - -VOID -HalTimerIrqDisRtl8195a( - IN u32 TimerId -); - -VOID -HalTimerClearIsrRtl8195a( - IN u32 TimerId -); - -VOID -HalTimerEnRtl8195a_Patch( - IN u32 TimerId -); - -VOID -HalTimerDisRtl8195a_Patch( - IN u32 TimerId -); - -VOID -HalTimerSyncRtl8195a( - IN u32 TimerId -); - -VOID -HalTimerDeInitRtl8195a_Patch( - IN VOID *Data -); - -#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT) - -__weak _LONG_CALL_ -VOID -HalTimerIrq2To7HandleV02( - IN VOID *Data -); - -__weak _LONG_CALL_ROM_ -HAL_Status -HalTimerIrqRegisterRtl8195aV02( - IN VOID *Data -); - -__weak _LONG_CALL_ -HAL_Status -HalTimerInitRtl8195aV02( - IN VOID *Data -); - -__weak _LONG_CALL_ -u32 -HalTimerReadCountRtl8195aV02( - IN u32 TimerId -); - -__weak _LONG_CALL_ -VOID -HalTimerReLoadRtl8195aV02( - IN u32 TimerId, - IN u32 LoadUs -); - -__weak _LONG_CALL_ROM_ -HAL_Status -HalTimerIrqUnRegisterRtl8195aV02( - IN VOID *Data -); - -__weak _LONG_CALL_ -VOID -HalTimerDeInitRtl8195aV02( - IN VOID *Data -); - -#endif // end of "#ifdef CONFIG_CHIP_C_CUT" - -#ifdef CONFIG_CHIP_E_CUT -_LONG_CALL_ VOID -HalTimerReLoadRtl8195a_V04( - IN u32 TimerId, - IN u32 LoadUs -); - -_LONG_CALL_ HAL_Status -HalTimerInitRtl8195a_V04( - IN VOID *Data -); -#endif // #ifdef CONFIG_CHIP_E_CUT - -// HAL functions wrapper -#ifndef CONFIG_RELEASE_BUILD_LIBRARIES -static __inline HAL_Status -HalTimerInit( - IN VOID *Data -) -{ -#ifdef CONFIG_CHIP_E_CUT - return (HalTimerInitRtl8195a_V04(Data)); -#else - return (HalTimerInitRtl8195a_Patch(Data)); -#endif -} - -static __inline VOID -HalTimerEnable( - IN u32 TimerId -) -{ - HalTimerIrqEnRtl8195a(TimerId); - HalTimerEnRtl8195a_Patch(TimerId); -} - -static __inline VOID -HalTimerDisable( - IN u32 TimerId -) -{ - HalTimerDisRtl8195a_Patch(TimerId); -} - -static __inline VOID -HalTimerClearIsr( - IN u32 TimerId -) -{ - HalTimerClearIsrRtl8195a(TimerId); -} - -static __inline VOID -HalTimerReLoad( - IN u32 TimerId, - IN u32 LoadUs -) -{ -#ifdef CONFIG_CHIP_E_CUT - HalTimerReLoadRtl8195a_V04(TimerId, LoadUs); -#else - HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs); -#endif -} - -#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) - -static __inline VOID -HalTimerDeInit( - IN VOID *Data -) -{ - HalTimerDeInitRtl8195a_Patch(Data); -} - -#else - -static __inline VOID -HalTimerDeInit( - IN VOID *Data -) -{ - HalTimerDeInitRtl8195aV02(Data); -} - -#endif // end of "#ifndef CONFIG_CHIP_C_CUT" -#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES -#endif //_RTL8195A_TIMER_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h deleted file mode 100644 index 1ddbce84af7..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h +++ /dev/null @@ -1,681 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef _RTL8195A_UART_H_ -#define _RTL8195A_UART_H_ - -#define MAX_UART_INDEX 2 - -#define RUART_DLL_OFF 0x00 -#define RUART_DLM_OFF 0x04 //RW, DLAB = 1 -#define RUART_INTERRUPT_EN_REG_OFF 0x04 -#define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger) -#define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty) -#define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status) -#define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition) - -#define RUART_INT_ID_REG_OFF 0x08 //[R] -#define RUART_IIR_INT_PEND 0x01 -#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0) -#define RUART_FIFO_CTL_REG_OFF 0x08 //[W] -#define RUART_FIFO_CTL_REG_FIFO_ENABLE 0x01 //BIT0 -#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear -#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2) //BIT2, 0x04, Write 1 clear -#define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3 - -#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9 -#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1 - -#define RUART_MODEM_CTL_REG_OFF 0x10 -#define RUART_MCR_RTS BIT1 -#define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20 - -#define RUART_LINE_CTL_REG_OFF 0x0C -#define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80 - -#define RUART_LINE_STATUS_REG_OFF 0x14 -#define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator -#define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run -#define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error -#define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error -#define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error -#define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable -#define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit) -#define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error -#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \ - RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \ - RUART_LINE_STATUS_ERR_RXFIFO) //Line status error - -#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register -#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register -#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear -#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection -#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16] - -#define RUART_STS_REG_OFF 0x20 -#define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver -#define RUART_STS_REG_XFACTOR 0xF<<4 - -#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register -#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register - -#define RUART_MISC_CTL_REG_OFF 0x28 -#define RUART_TXDMA_EN_MASK 0x02 // [1] -#define RUART_RXDMA_EN_MASK 0x04 // [2] -#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 // [7:3] -#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 // [12:8] - -#define RUART_DEBUG_REG_OFF 0x3C - -// RUART_LINE_CTL_REG_OFF (0x0C) -#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits -#define BIT_MASK_LCR_WLS_8BITS 0x1 -#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS) -#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS)) - -#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit -#define BIT_MASK_LCR_STB_EN 0x1 -#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB) -#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB)) - -#define BIT_SHIFT_LCR_PARITY_EN 3 -#define BIT_MASK_LCR_PARITY_EN 0x1 -#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN) -#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN)) - -#define BIT_SHIFT_LCR_PARITY_TYPE 4 -#define BIT_MASK_LCR_PARITY_TYPE 0x1 -#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE) -#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE)) - -#define BIT_SHIFT_LCR_STICK_PARITY_EN 5 -#define BIT_MASK_LCR_STICK_PARITY_EN 0x1 -#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN) -#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN)) - -#define BIT_SHIFT_LCR_BREAK_CTRL 6 -#define BIT_MASK_LCR_BREAK_CTRL 0x1 -#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL) - -#define RUART_BAUD_RATE_2400 2400 -#define RUART_BAUD_RATE_4800 4800 -#define RUART_BAUD_RATE_9600 9600 -#define RUART_BAUD_RATE_19200 19200 -#define RUART_BAUD_RATE_38400 38400 -#define RUART_BAUD_RATE_57600 57600 -#define RUART_BAUD_RATE_115200 115200 -#define RUART_BAUD_RATE_921600 921600 -#define RUART_BAUD_RATE_1152000 1152000 - -#define HAL_RUART_READ32(UartIndex, addr) \ - HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) -#define HAL_RUART_WRITE32(UartIndex, addr, value) \ - HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) -#define HAL_RUART_READ16(UartIndex, addr) \ - HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) -#define HAL_RUART_WRITE16(UartIndex, addr, value) \ - HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) -#define HAL_RUART_READ8(UartIndex, addr) \ - HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) -#define HAL_RUART_WRITE8(UartIndex, addr, value) \ - HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) - -#define UART_OVSR_POOL_MIN 1000 -#define UART_OVSR_POOL_MAX 2090 -#define DIVISOR_RESOLUTION 10 -#define JITTER_LIMIT 100 -#define UART_SCLK (200000000*5/12) - -typedef struct _RUART_SPEED_SETTING_ { - u32 BaudRate; - u32 Ovsr; - u32 Div; - u32 Ovsr_adj; -#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES)) - u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity - u8 Ovsr_adj_bits; - u16 *Ovsr_adj_map; - u32 max_err; // 10 ~ 100: 30 - u32 Ovsr_min; // 10 ~ 20: 1000 - u32 Ovsr_max; // 10 ~ 20: 2000 - u32 divisor_resolution; // 1 ~ 20: 10 - u32 jitter_lim; // 50 ~ 100: 100 - u32 sclk; // 83.33333 MHz -#endif -}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING; - -enum _UART_RXFIFO_TRIGGER_LEVEL_ { - OneByte = 0x00, - FourBytes = 0x01, - EightBytes = 0x10, - FourteenBytes = 0x11 -}; -typedef uint32_t UART_RXFIFO_TRIGGER_LEVEL; -typedef uint32_t *PUART_RXFIFO_TRIGGER_LEVEL; - -enum _RUART0_PINMUX_SELECT_ { - RUART0_MUX_TO_GPIOC = S0, - RUART0_MUX_TO_GPIOE = S1, - RUART0_MUX_TO_GPIOA = S2 -}; -typedef uint32_t RUART0_PINMUX_SELECT; -typedef uint32_t *PRUART0_PINMUX_SELECT; - -enum _RUART1_PINMUX_SELECT_ { - RUART1_MUX_TO_GPIOD = S0, - RUART1_MUX_TO_GPIOE = S1, - RUART1_MUX_TO_GPIOB = S2 -}; -typedef uint32_t RUART1_PINMUX_SELECT; -typedef uint32_t *PRUART1_PINMUX_SELECT; - -enum _RUART2_PINMUX_SELECT_ { - RUART2_MUX_TO_GPIOA = S0, - RUART2_MUX_TO_GPIOC = S1, - RUART2_MUX_TO_GPIOD = S2 -}; -typedef uint32_t RUART2_PINMUX_SELECT; -typedef uint32_t *PRUART2_PINMUX_SELECT; - -enum _RUART_FLOW_CONTROL_ { - AUTOFLOW_DISABLE = 0, - AUTOFLOW_ENABLE = 1 -}; -typedef uint32_t RUART_FLOW_CONTROL; -typedef uint32_t *PRUART_FLOW_CONTROL; - -enum _RUART_WORD_LEN_SEL_ { - RUART_WLS_7BITS = 0, - RUART_WLS_8BITS = 1 -}; -typedef uint32_t RUART_WORD_LEN_SEL; -typedef uint32_t *PRUART_WORD_LEN_SEL; - -enum _RUART_STOP_BITS_ { - RUART_STOP_BIT_1 = 0, - RUART_STOP_BIT_2 = 1 -}; -typedef uint32_t RUART_STOP_BITS; -typedef uint32_t *PRUART_STOP_BITS; - -enum _RUART_PARITY_CONTROL_ { - RUART_PARITY_DISABLE = 0, - RUART_PARITY_ENABLE = 1 -}; -typedef uint32_t RUART_PARITY_CONTROL; -typedef uint32_t *PRUART_PARITY_CONTROL; - -enum _RUART_PARITY_TYPE_ { - RUART_ODD_PARITY = 0, - RUART_EVEN_PARITY = 1 -}; -typedef uint32_t RUART_PARITY_TYPE; -typedef uint32_t *PRUART_PARITY_TYPE; - -enum _RUART_STICK_PARITY_CONTROL_ { - RUART_STICK_PARITY_DISABLE = 0, - RUART_STICK_PARITY_ENABLE = 1 -}; -typedef uint32_t RUART_STICK_PARITY_CONTROL; -typedef uint32_t *PRUART_STICK_PARITY_CONTROL; - -enum _UART_INT_ID_ { - ModemStatus = 0, - TxFifoEmpty = 1, - ReceiverDataAvailable = 2, - ReceivLineStatus = 3, - TimeoutIndication = 6 -}; -typedef uint32_t UART_INT_ID; -typedef uint32_t *PUART_INT_ID; - -enum _HAL_UART_State_ -{ - HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet - HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use - HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration - HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX - HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX - HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX - HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout - HAL_UART_STATE_ERROR = 0x40 // UART Error -}; -typedef uint32_t HAL_UART_State; -typedef uint32_t *PHAL_UART_State; - -enum _HAL_UART_Status_ -{ - HAL_UART_STATUS_OK = 0x00, // Transfer OK - HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout - HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run - HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error - HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error - HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt - HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error - HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error -}; -typedef uint32_t HAL_UART_Status; -typedef uint32_t *PHAL_UART_Status; - -u32 -HalRuartGetDebugValueRtl8195a( - IN VOID* Data, - IN u32 DbgSel - ); - -#if 0 -u32 -FindElementIndex( - u32 Element, - u32* Array - ); -#endif - -VOID -RuartResetRxFifoRtl8195a( - IN u8 UartIndex - ); -#if 0 -VOID -RuartBusDomainEnableRtl8195a( - IN u8 UartIndex - ); -#endif - -HAL_Status -HalRuartResetRxFifoRtl8195a( - IN VOID *Data - ); - -HAL_Status -HalRuartInitRtl8195a( - IN VOID *Data - ); - -VOID -HalRuartDeInitRtl8195a( - IN VOID *Data ///< RUART Adapter - ); - -HAL_Status -HalRuartPutCRtl8195a( - IN VOID *Data, - IN u8 TxData - ); - -u32 -HalRuartSendRtl8195a( - IN VOID *Data, - IN u8 *pTxData, - IN u32 Length, - IN u32 Timeout - ); - -HAL_Status -HalRuartIntSendRtl8195a( - IN VOID *Data, // PHAL_RUART_ADAPTER - IN u8 *pTxData, // the Buffer to be send - IN u32 Length // the length of data to be send - ); - -HAL_Status -HalRuartDmaSendRtl8195a( - IN VOID *Data, // PHAL_RUART_ADAPTER - IN u8 *pTxData, // the Buffer to be send - IN u32 Length // the length of data to be send -); - -HAL_Status -HalRuartStopSendRtl8195a( - IN VOID *Data // PHAL_RUART_ADAPTER -); - -HAL_Status -HalRuartGetCRtl8195a( - IN VOID *Data, - OUT u8 *pRxByte - ); - -u32 -HalRuartRecvRtl8195a( - IN VOID *Data, - IN u8 *pRxData, - IN u32 Length, - IN u32 Timeout - ); - -HAL_Status -HalRuartIntRecvRtl8195a( - IN VOID *Data, ///< RUART Adapter - IN u8 *pRxData, ///< Rx buffer - IN u32 Length // buffer length - ); - -HAL_Status -HalRuartDmaRecvRtl8195a( - IN VOID *Data, ///< RUART Adapter - IN u8 *pRxData, ///< Rx buffer - IN u32 Length // buffer length - ); - -HAL_Status -HalRuartStopRecvRtl8195a( - IN VOID *Data // PHAL_RUART_ADAPTER -); - -u8 -HalRuartGetIMRRtl8195a( - IN VOID *Data - ); - -_LONG_CALL_ROM_ VOID -HalRuartSetIMRRtl8195a( - IN VOID *Data - ); - -VOID -HalRuartDmaInitRtl8195a( - IN VOID *Data - ); - -VOID -HalRuartRTSCtrlRtl8195a( - IN VOID *Data, - IN BOOLEAN RtsCtrl - ); - -VOID -HalRuartRegIrqRtl8195a( - IN VOID *Data - ); - -VOID -HalRuartIntEnableRtl8195a( - IN VOID *Data - ); - -VOID -HalRuartIntDisableRtl8195a( - IN VOID *Data - ); - -VOID -HalRuartAdapterLoadDefRtl8195a( - IN VOID *pAdp, - IN u8 UartIdx -); - -VOID -HalRuartTxGdmaLoadDefRtl8195a( - IN VOID *pAdp, - IN VOID *pCfg -); - -VOID -HalRuartRxGdmaLoadDefRtl8195a( - IN VOID *pAdp, - IN VOID *pCfg -); - -_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02( - IN VOID *Data, // PHAL_RUART_ADAPTER - IN u8 *pTxData, // the Buffer to be send - IN u32 Length // the length of data to be send -); - -_LONG_CALL_ HAL_Status -HalRuartIntRecvRtl8195aV02( - IN VOID *Data, ///< RUART Adapter - IN u8 *pRxData, ///< Rx buffer - IN u32 Length // buffer length -); - -_LONG_CALL_ s32 -FindElementIndex_v02( - u32 Element, ///< RUART Baudrate - u32* Array, ///< Pre-defined Baudrate Array - u32 ElementNo -); - -_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data); - -// New added function 2015/04/20 -HAL_Status -HalRuartResetTxFifoRtl8195a( - IN VOID *Data ///< RUART Adapter - ); - -HAL_Status -HalRuartResetRxFifoRtl8195a_Patch( - IN VOID *Data ///< RUART Adapter -); - -HAL_Status -HalRuartResetTRxFifoRtl8195a( - IN VOID *Data ///< RUART Adapter -); - -HAL_Status -HalRuartSetBaudRateRtl8195a( - IN VOID *Data - ); - -HAL_Status -HalRuartEnableRtl8195a( - IN VOID *Data -); - -HAL_Status -HalRuartDisableRtl8195a( - IN VOID *Data -); - -HAL_Status -HalRuartFlowCtrlRtl8195a( - IN VOID *Data -); - -u32 -_UartTxDmaIrqHandle_Patch( - IN VOID *Data -); - -u32 -_UartRxDmaIrqHandle_Patch( - IN VOID *Data -); - -HAL_Status -HalRuartDmaSendRtl8195a_Patch( - IN VOID *Data, - IN u8 *pTxData, - IN u32 Length -); - -HAL_Status -HalRuartDmaRecvRtl8195a_Patch( - IN VOID *Data, - IN u8 *pRxData, - IN u32 Length -); - -HAL_Status -HalRuartMultiBlkDmaSendRtl8195a( - IN VOID *Data, - IN u8 *pTxData, - IN u32 Length -); - -HAL_Status -HalRuartMultiBlkDmaRecvRtl8195a( - IN VOID *Data, - IN u8 *pRxData, - IN u32 Length -); - -HAL_Status -RuartIsTimeout ( - u32 StartCount, - u32 TimeoutCnt -); - -HAL_Status -HalRuartStopRecvRtl8195a_Patch( - IN VOID *Data -); - -HAL_Status -HalRuartStopSendRtl8195a_Patch( - IN VOID *Data -); - -VOID -HalRuartEnterCriticalRtl8195a( - IN VOID *Data -); - -VOID -HalRuartExitCriticalRtl8195a( - IN VOID *Data -); - -VOID -HalRuartTxGdmaEnable8195a( - IN VOID *pHalRuartAdapter -); - -VOID -HalRuartTxGdmaDisable8195a( - IN VOID *pHalRuartAdapter -); - -VOID -HalRuartRxGdmaEnable8195a( - IN VOID *pHalRuartAdapter -); - -VOID -HalRuartRxGdmaDisable8195a( - IN VOID *pHalRuartAdapter -); - -#if CONFIG_CHIP_E_CUT -_LONG_CALL_ HAL_Status -HalRuartResetTxFifoRtl8195a_V04( - IN VOID *Data ///< RUART Adapter -); - -_LONG_CALL_ HAL_Status -HalRuartResetRxFifoRtl8195a_V04( - IN VOID *Data ///< RUART Adapter -); - -_LONG_CALL_ HAL_Status -HalRuartResetTRxFifoRtl8195a_V04( - IN VOID *Data ///< RUART Adapter -); - -_LONG_CALL_ HAL_Status -HalRuartSetBaudRateRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ HAL_Status -HalRuartInitRtl8195a_V04( - IN VOID *Data ///< RUART Adapter -); - -_LONG_CALL_ HAL_Status -HalRuartEnableRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ HAL_Status -HalRuartDisableRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ HAL_Status -HalRuartFlowCtrlRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ u32 -_UartTxDmaIrqHandle_V04( - IN VOID *Data -); - -_LONG_CALL_ u32 -_UartRxDmaIrqHandle_V04( - IN VOID *Data -); - -_LONG_CALL_ HAL_Status -HalRuartDmaSendRtl8195a_V04( - IN VOID *Data, - IN u8 *pTxData, - IN u32 Length -); - -_LONG_CALL_ HAL_Status -HalRuartDmaRecvRtl8195a_V04( - IN VOID *Data, - IN u8 *pRxData, - IN u32 Length -); - -_LONG_CALL_ HAL_Status -HalRuartMultiBlkDmaSendRtl8195a_V04( - IN VOID *Data, - IN u8 *pTxData, - IN u32 Length -); - -_LONG_CALL_ HAL_Status -HalRuartMultiBlkDmaRecvRtl8195a_V04( - IN VOID *Data, - IN u8 *pRxData, - IN u32 Length -); - -_LONG_CALL_ HAL_Status -HalRuartStopRecvRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ HAL_Status -HalRuartStopSendRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ VOID -HalRuartEnterCriticalRtl8195a_V04( - IN VOID *Data -); - -_LONG_CALL_ VOID -HalRuartExitCriticalRtl8195a_V04( - IN VOID *Data -); -#endif // #if CONFIG_CHIP_E_CUT - -#ifdef CONFIG_MBED_ENABLED -// Interface to ROM functions -extern __longcall HAL_Status RuartIsTimeout(uint32_t StartCount, uint32_t TimeoutCnt); -#endif - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h deleted file mode 100644 index 752497359fa..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h +++ /dev/null @@ -1,94 +0,0 @@ -/******************************************************************************* - *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * Licensed under the Permissive Binary License, Version 1.0 (the "License"); - * you may not use this file except in compliance with the License. - * - * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and limitations under the License. - ******************************************************************************* - */ - -#ifndef _RTL8195A_WDT_H_ -#define _RTL8195A_WDT_H_ - -#define WDGTIMERELY (10*1024) //us - -typedef struct _WDG_REG_ { - u16 WdgScalar; - u8 WdgEnByte; - u8 WdgClear:1; - u8 WdgCunLimit:4; - u8 Rsvd:1; - u8 WdgMode:1; - u8 WdgToISR:1; -}WDG_REG, *PWDG_REG; - -typedef struct _WDG_ADAPTER_ { - - WDG_REG Ctrl; - IRQ_HANDLE IrqHandle; - TIMER_ADAPTER WdgGTimer; - VOID (*UserCallback)(u32 callback_id); // User callback function - u32 callback_id; -}WDG_ADAPTER, *PWDG_ADAPTER; - -enum _WDG_CNTLMT_ { - CNT1H = 0, - CNT3H = 1, - CNT7H = 2, - CNTFH = 3, - CNT1FH = 4, - CNT3FH = 5, - CNT7FH = 6, - CNTFFH = 7, - CNT1FFH = 8, - CNT3FFH = 9, - CNT7FFH = 10, - CNTFFFH = 11 -}; -typedef uint32_t WDG_CNTLMT; -typedef uint32_t *PWDG_CNTLMT; - - -enum _WDG_MODE_ { - INT_MODE = 0, - RESET_MODE = 1 -}; -typedef uint32_t WDG_MODE; -typedef uint32_t *PWDG_MODE; - -extern VOID -WDGInitial( - IN u32 Period -); - -extern VOID -WDGIrqInitial( - VOID -); - -extern VOID -WDGIrqInitial( - VOID -); - -extern VOID -WDGStop( - VOID -); - -extern VOID -WDGRefresh( - VOID -); - -extern VOID -WDGIrqCallBackReg( - IN VOID *CallBack, - IN u32 Id -); - -#endif //_RTL8195A_WDT_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/os/cmsis_pmu_8195a.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/os/cmsis_pmu_8195a.c deleted file mode 100644 index f787ad81261..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/os/cmsis_pmu_8195a.c +++ /dev/null @@ -1,213 +0,0 @@ -#if DEVICE_SLEEP - -//#include "FreeRTOS.h" -#include "cmsis_pmu_8195a.h" - -#include - -#include "platform_autoconf.h" -#include "platform_stdlib.h" -//#include "sys_api.h" - -#include "sleep_ex_api.h" - -#ifndef portNVIC_SYSTICK_CURRENT_VALUE_REG -#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) ) -#endif - -uint32_t missing_tick = 0; - -static uint32_t wakelock = 0; -//static uint32_t wakelock = DEFAULT_WAKELOCK; - -static uint32_t wakeup_event = DEFAULT_WAKEUP_EVENT; - -typedef struct { - uint32_t nDeviceId; - PSM_HOOK_FUN sleep_hook_fun; - void* sleep_param_ptr; - PSM_HOOK_FUN wakeup_hook_fun; - void* wakeup_param_ptr; -} PSM_DD_HOOK_INFO; - -#define MAX_PSM_DD_HOOK_INFO_SIZE 8 -uint32_t psm_dd_hook_info_size = 0; -PSM_DD_HOOK_INFO psm_dd_hook_infos[MAX_PSM_DD_HOOK_INFO_SIZE]; - -static uint8_t last_wakelock_state[32] = { - DEFAULT_WAKELOCK & 0x01, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 -}; -static uint32_t last_acquire_wakelock_time[32] = {0}; -static uint32_t hold_wakelock_time[32] = {0}; -static uint32_t base_sys_time = 0; - -static uint32_t sys_sleep_time = 0; - -unsigned char reserve_pll = 0; -unsigned char generate_wakelock_stats = 0; - - -/* -------- FreeRTOS macro implementation -------- */ - -int cmsis_ready_to_sleep() { - return wakelock == 0; -} - -void pmu_acquire_wakelock(uint32_t lock_id) { - - wakelock |= BIT(lock_id); - - if (generate_wakelock_stats) { - uint32_t i; - - //uint32_t current_timestamp = osKernelSysTick(); - uint32_t current_timestamp = osKernelGetSysTimerCount(); - - for (i=0; i<32; i++) { - if ( (1< 0) { - sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i]); - } - } - pcWriteBuffer += strlen( pcWriteBuffer ); - } - sprintf(pcWriteBuffer, "time passed: %d ms, system sleep %d ms\r\n", current_timestamp - base_sys_time, sys_sleep_time); - } -} - -void pmu_clean_wakelock_stat() { - uint32_t i; - - //base_sys_time = osKernelSysTick(); - base_sys_time = osKernelGetSysTimerCount(); - - for (i=0; i<32; i++) { - hold_wakelock_time[i] = 0; - if (last_wakelock_state[i] == 1) { - last_acquire_wakelock_time[i] = base_sys_time; - } - } - sys_sleep_time = 0; -} - -void pmu_add_wakeup_event(uint32_t event) { - wakeup_event |= event; -} - -void pmu_del_wakeup_event(uint32_t event) { - wakeup_event &= ~event; - // To fulfill tickless design, system timer is required to be wakeup event - wakeup_event |= SLEEP_WAKEUP_BY_STIMER; -} - -void pmu_register_sleep_callback(uint32_t nDeviceId, PSM_HOOK_FUN sleep_hook_fun, void* sleep_param_ptr, PSM_HOOK_FUN wakeup_hook_fun, void* wakeup_param_ptr) { - uint32_t i; - for (i=0; i 1) { - // if we have more than 2 items, just swap the last item into current slot - psm_dd_hook_infos[i].nDeviceId = psm_dd_hook_infos[psm_dd_hook_info_size-1].nDeviceId; - psm_dd_hook_infos[i].sleep_hook_fun = psm_dd_hook_infos[psm_dd_hook_info_size-1].sleep_hook_fun; - psm_dd_hook_infos[i].sleep_param_ptr = psm_dd_hook_infos[psm_dd_hook_info_size-1].sleep_param_ptr; - psm_dd_hook_infos[i].wakeup_hook_fun = psm_dd_hook_infos[psm_dd_hook_info_size-1].wakeup_hook_fun; - psm_dd_hook_infos[i].wakeup_param_ptr = psm_dd_hook_infos[psm_dd_hook_info_size-1].wakeup_param_ptr; - - // Then erase the last item - psm_dd_hook_infos[psm_dd_hook_info_size-1].nDeviceId = 0; - psm_dd_hook_infos[psm_dd_hook_info_size-1].sleep_hook_fun = NULL; - psm_dd_hook_infos[psm_dd_hook_info_size-1].sleep_param_ptr = NULL; - psm_dd_hook_infos[psm_dd_hook_info_size-1].wakeup_hook_fun = NULL; - psm_dd_hook_infos[psm_dd_hook_info_size-1].wakeup_param_ptr = NULL; - } else { - // we only have one item, just erase it - psm_dd_hook_infos[i].nDeviceId = 0; - psm_dd_hook_infos[i].sleep_hook_fun = NULL; - psm_dd_hook_infos[i].sleep_param_ptr = NULL; - psm_dd_hook_infos[i].wakeup_hook_fun = NULL; - psm_dd_hook_infos[i].wakeup_param_ptr = NULL; - } - psm_dd_hook_info_size--; - break; - } - } -} - -void pmu_set_pll_reserved(unsigned char reserve) { - reserve_pll = reserve; -} - -#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/os/cmsis_pmu_8195a.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/os/cmsis_pmu_8195a.h deleted file mode 100644 index adff9cc8ea3..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/os/cmsis_pmu_8195a.h +++ /dev/null @@ -1,110 +0,0 @@ -#ifndef __FREERTOS_PMU_H_ -#define __FREERTOS_PMU_H_ - -#if DEVICE_SLEEP -#include "sleep_ex_api.h" - -#ifndef BIT -#define BIT(n) (1< - -#define PLATFORM_LITTLE_ENDIAN 0 -#define PLATFORM_BIG_ENDIAN 1 - -#define SYSTEM_ENDIAN PLATFORM_LITTLE_ENDIAN - -#define SUCCESS 0 -#define FAIL (-1) - -#undef _SUCCESS -#define _SUCCESS 1 - -#undef _FAIL -#define _FAIL 0 - -#ifndef FALSE - #define FALSE 0 -#endif - -#ifndef TRUE - #define TRUE (!FALSE) -#endif - -#define _TRUE TRUE -#define _FALSE FALSE - -#ifndef NULL -#define NULL 0 -#endif - -#ifdef __GNUC__ -#define __weak __attribute__((weak)) -#define likely(x) __builtin_expect ((x), 1) -#define unlikely(x) __builtin_expect ((x), 0) -#endif - -typedef unsigned int uint; -typedef signed int sint; - -#ifdef __ICCARM__ -typedef signed long long __int64_t; -typedef unsigned long long __uint64_t; -#endif - -#if defined(CONFIG_MBED_ENABLED) -typedef int8_t s8; -typedef uint8_t u8; -typedef int16_t s16; -typedef uint16_t u16; -typedef int32_t s32; -typedef uint32_t u32; -typedef int64_t s64; -typedef uint64_t u64; -#else -#define s8 int8_t -#define u8 uint8_t -#define s16 int16_t -#define u16 uint16_t -#define s32 int32_t -#define u32 uint32_t -#define s64 int64_t -#define u64 uint64_t -#endif - -#ifndef BOOL -typedef unsigned char BOOL; -#endif -#ifndef __cplusplus -#ifndef bool -typedef unsigned char bool; -#endif -#endif - -#define UCHAR uint8_t -#define USHORT uint16_t - -#if defined(CONFIG_MBED_ENABLED) -typedef unsigned int UINT; -#else -#define UINT uint32_t -#endif - -#define ULONG uint32_t - -enum _RTK_STATUS_ { - _EXIT_SUCCESS = 0, - _EXIT_FAILURE = 1 -}; -typedef uint32_t RTK_STATUS; -typedef uint32_t * PRTK_STATUS; - -#define IN -#define OUT -#define VOID void -#define INOUT -#define NDIS_OID uint -#define NDIS_STATUS uint - -#ifndef PVOID -typedef void * PVOID; -#endif - -typedef u32 dma_addr_t; - -typedef void (*proc_t)(void*); - -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; - -typedef __kernel_size_t SIZE_T; -typedef __kernel_ssize_t SSIZE_T; -#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) - -#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T)) -#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1) - -#define SIZE_PTR SIZE_T -#define SSIZE_PTR SSIZE_T - -#ifndef ON -#define ON 1 -#endif - -#ifndef OFF -#define OFF 0 -#endif - -#ifndef ENABLE -#define ENABLE 1 -#endif - -#ifndef DISABLE -#define DISABLE 0 -#endif - - -#define BIT0 0x0001 -#define BIT1 0x0002 -#define BIT2 0x0004 -#define BIT3 0x0008 -#define BIT4 0x0010 -#define BIT5 0x0020 -#define BIT6 0x0040 -#define BIT7 0x0080 -#define BIT8 0x0100 -#define BIT9 0x0200 -#define BIT10 0x0400 -#define BIT11 0x0800 -#define BIT12 0x1000 -#define BIT13 0x2000 -#define BIT14 0x4000 -#define BIT15 0x8000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#define BIT_(__n) (1<<(__n)) - -#ifndef BIT -#define BIT(__n) (1<<(__n)) -#endif - -#if defined (__ICCARM__) -#define STRINGIFY(a) #a -#define SECTION(_name) _Pragma( STRINGIFY(location=_name)) -#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=_bound)) -#define _PACKED_ __packed -#define _LONG_CALL_ -#define _LONG_CALL_ROM_ -#define _WEAK __weak -#if (__VER__ >= 8000000) -#define _USED __attribute__((used)) -#else -#define _USED _Pragma("__root") -#endif - -#elif defined(__CC_ARM) -// defined in rtl8195a_compiler.h -#define SECTION(_name) __attribute__ ((section(_name))) -#define _LONG_CALL_ __attribute__ ((long_call)) -#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound))) -#define _LONG_CALL_ROM_ _LONG_CALL_ -#define _WEAK __attribute__ ((weak)) -#define _USED __attribute__((used)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#define SECTION(_name) __attribute__ ((__section__(_name))) -#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound))) -#define _PACKED_ __attribute__ ((packed)) -#ifdef CONFIG_RELEASE_BUILD_LIBRARIES -#define _LONG_CALL_ -#define _LONG_CALL_ROM_ -#ifdef E_CUT_ROM_DOMAIN -#undef _LONG_CALL_ROM_ -#define _LONG_CALL_ROM_ -#endif -#else -#define _LONG_CALL_ -#define _LONG_CALL_ROM_ _LONG_CALL_ -#endif -#define _WEAK __attribute__ ((weak)) -#define _USED __attribute__((used)) - -#else -#define SECTION(_name) __attribute__ ((__section__(_name))) -#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound))) -#define _PACKED_ __attribute__ ((packed)) -#ifdef CONFIG_RELEASE_BUILD_LIBRARIES -#define _LONG_CALL_ -#define _LONG_CALL_ROM_ __attribute__ ((long_call)) -#ifdef E_CUT_ROM_DOMAIN -#undef _LONG_CALL_ROM_ -#define _LONG_CALL_ROM_ -#endif -#else -#define _LONG_CALL_ __attribute__ ((long_call)) -#define _LONG_CALL_ROM_ _LONG_CALL_ -#endif -#define _WEAK __attribute__ ((weak)) -#define _USED __attribute__((used)) -#endif - - - -//port from fw by thomas -// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness - -#define SWAP32(x) ((u32)( \ - (((u32)(x) & (u32)0x000000ff) << 24) | \ - (((u32)(x) & (u32)0x0000ff00) << 8) | \ - (((u32)(x) & (u32)0x00ff0000) >> 8) | \ - (((u32)(x) & (u32)0xff000000) >> 24))) - -#define WAP16(x) ((u16)( \ - (((u16)(x) & (u16)0x00ff) << 8) | \ - (((u16)(x) & (u16)0xff00) >> 8))) - -#if SYSTEM_ENDIAN == PLATFORM_LITTLE_ENDIAN -#ifndef rtk_le16_to_cpu -#define rtk_cpu_to_le32(x) ((u32)(x)) -#define rtk_le32_to_cpu(x) ((u32)(x)) -#define rtk_cpu_to_le16(x) ((u16)(x)) -#define rtk_le16_to_cpu(x) ((u16)(x)) -#define rtk_cpu_to_be32(x) SWAP32((x)) -#define rtk_be32_to_cpu(x) SWAP32((x)) -#define rtk_cpu_to_be16(x) WAP16((x)) -#define rtk_be16_to_cpu(x) WAP16((x)) -#endif - -#elif SYSTEM_ENDIAN == PLATFORM_BIG_ENDIAN -#ifndef rtk_le16_to_cpu -#define rtk_cpu_to_le32(x) SWAP32((x)) -#define rtk_le32_to_cpu(x) SWAP32((x)) -#define rtk_cpu_to_le16(x) WAP16((x)) -#define rtk_le16_to_cpu(x) WAP16((x)) -#define rtk_cpu_to_be32(x) ((__u32)(x)) -#define rtk_be32_to_cpu(x) ((__u32)(x)) -#define rtk_cpu_to_be16(x) ((__u16)(x)) -#define rtk_be16_to_cpu(x) ((__u16)(x)) -#endif -#endif - - -/* - * Call endian free function when - * 1. Read/write packet content. - * 2. Before write integer to IO. - * 3. After read integer from IO. -*/ - -// -// Byte Swapping routine. -// -#define EF1Byte (u8) -#define EF2Byte le16_to_cpu -#define EF4Byte le32_to_cpu - -// -// Read LE format data from memory -// -#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr))) -#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr))) -#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr))) - -// -// Write LE data to memory -// -#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val) -#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val) -#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val) - -// -// Example: -// BIT_LEN_MASK_32(0) => 0x00000000 -// BIT_LEN_MASK_32(1) => 0x00000001 -// BIT_LEN_MASK_32(2) => 0x00000003 -// BIT_LEN_MASK_32(32) => 0xFFFFFFFF -// -#define BIT_LEN_MASK_32(__BitLen) \ - (0xFFFFFFFF >> (32 - (__BitLen))) -// -// Example: -// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 -// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 -// -#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ - (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) - -// -// Description: -// Return 4-byte value in host byte ordering from -// 4-byte pointer in litten-endian system. -// -#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ - (EF4Byte(*((u32 *)(__pStart)))) - -// -// Description: -// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to -// 4-byte value in host byte ordering. -// -#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ - & \ - BIT_LEN_MASK_32(__BitLen) \ - ) - -// -// Description: -// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering -// and return the result in 4-byte value in host byte ordering. -// -#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ - & \ - ( ~ BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ - ) - -// -// Description: -// Set subfield of little-endian 4-byte value to specified value. -// -#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ - *((u32 *)(__pStart)) = \ - EF4Byte( \ - LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - | \ - ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ - ); - - -#define BIT_LEN_MASK_16(__BitLen) \ - (0xFFFF >> (16 - (__BitLen))) - -#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ - (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) - -#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ - (EF2Byte(*((u16 *)(__pStart)))) - -#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ - & \ - BIT_LEN_MASK_16(__BitLen) \ - ) - -#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ - & \ - ( ~ BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ - ) - -#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ - *((u16 *)(__pStart)) = \ - EF2Byte( \ - LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ - | \ - ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ - ); - -#define BIT_LEN_MASK_8(__BitLen) \ - (0xFF >> (8 - (__BitLen))) - -#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ - (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) - -#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ - (EF1Byte(*((u8 *)(__pStart)))) - -#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ - & \ - BIT_LEN_MASK_8(__BitLen) \ - ) - -#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ - & \ - ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ - ) - -#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ - *((u8 *)(__pStart)) = \ - EF1Byte( \ - LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - | \ - ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ - ); - -//pclint -#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ - ) - -//pclint -#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \ -{ \ - *((pu1Byte)(__pStart)) = \ - EF1Byte( \ - LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ - | \ - ((u1Byte)__Value) \ - ); \ -} - -// Get the N-bytes aligment offset from the current length -#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) - -typedef unsigned char BOOLEAN,*PBOOLEAN; - -#define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0) -#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag) -#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag)) -#define CLEAR_FLAGS(__Flag) ((__Flag) = 0) -#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags)) - -/* Define compilor specific symbol */ -// -// inline function -// - -#if defined ( __ICCARM__ ) -#define __inline__ inline -#define __inline inline -#define __inline_definition //In dialect C99, inline means that a function's definition is provided - //only for inlining, and that there is another definition - //(without inline) somewhere else in the program. - //That means that this program is incomplete, because if - //add isn't inlined (for example, when compiling without optimization), - //then main will have an unresolved reference to that other definition. - - // Do not inline function is the function body is defined .c file and this - // function will be called somewhere else, otherwise there is compile error -#elif defined ( __CC_ARM ) -#define __inline__ __inline //__linine__ is not supported in keil compilor, use __inline instead -#define inline __inline -#define __inline_definition // for dialect C99 -#elif defined ( __GNUC__ ) -#define __inline__ inline -#define __inline inline -#define __inline_definition inline -#endif - -// -// pack -// - -#if defined (__ICCARM__) - -#define RTW_PACK_STRUCT_BEGIN _Pragma( STRINGIFY(pack(1))) -#define RTW_PACK_STRUCT_STRUCT -#define RTW_PACK_STRUCT_END _Pragma( STRINGIFY(pack())) -//#define RTW_PACK_STRUCT_USE_INCLUDES - -#elif defined (__CC_ARM) - -#define RTW_PACK_STRUCT_BEGIN __packed -#define RTW_PACK_STRUCT_STRUCT -#define RTW_PACK_STRUCT_END - -#elif defined (__GNUC__) - -#define RTW_PACK_STRUCT_BEGIN -#define RTW_PACK_STRUCT_STRUCT __attribute__ ((__packed__)) -#define RTW_PACK_STRUCT_END - -#elif defined(PLATFORM_WINDOWS) - -#define RTW_PACK_STRUCT_BEGIN -#define RTW_PACK_STRUCT_STRUCT -#define RTW_PACK_STRUCT_END -#define RTW_PACK_STRUCT_USE_INCLUDES -#endif - -// for standard library -#ifdef __ICCARM__ -#define __extension__ /* Ignore */ -#define __restrict /* Ignore */ -#endif - -typedef struct _RAM_START_FUNCTION_ { - VOID (*RamStartFun) (VOID); -}RAM_START_FUNCTION, *PRAM_START_FUNCTION; - -typedef struct _RAM_FUNCTION_START_TABLE_ { - VOID (*RamStartFun) (VOID); - VOID (*RamWakeupFun) (VOID); - VOID (*RamPatchFun0) (VOID); - VOID (*RamPatchFun1) (VOID); - VOID (*RamPatchFun2) (VOID); -}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE; - -#endif// __BASIC_TYPES_H__ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/section_config.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/section_config.h deleted file mode 100644 index 06031d9ca72..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/section_config.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Routines to access hardware - * - * Copyright (c) 2013 Realtek Semiconductor Corp. - * - * This module is a confidential and proprietary property of RealTek and - * possession or use of this module requires written permission of RealTek. - */ - -#ifndef _SECTION_CONFIG_H_ -#define _SECTION_CONFIG_H_ - -#include "basic_types.h" -#include "platform_autoconf.h" - -#define RAM_DEDECATED_VECTOR_TABLE_SECTION \ - SECTION(".ram_dedecated_vector_table") - -#define RAM_USER_IRQ_FUN_TABLE_SECTION \ - SECTION(".ram_user_define_irq_table") - -#define RAM_USER_IRQ_DATA_TABLE_SECTION \ - SECTION(".ram_user_define_data_table") - -//3 Timer Section -#define SECTION_RAM_TIMER2TO7_VECTOR_TABLE \ - SECTION(".timer2_7_vector_table.data") - -#define SECTION_RAM_BSS_TIMER_RECORDER_TABLE \ - SECTION(".timer.ram.data") - -#define TIMER_ROM_TEXT_SECTION \ - SECTION(".timer.rom.text") - -#define TIMER_ROM_DATA_SECTION \ - SECTION(".timer.rom.rodata") - -#define TIMER_RAM_TEXT_SECTION \ - SECTION(".timer.ram.text") - -#define TIMER_RAM_DATA_SECTION \ - SECTION(".timer.ram.data") - - -//3 Wifi Section -#define WIFI_ROM_TEXT_SECTION \ - SECTION(".wifi.rom.text") - -#define WIFI_ROM_DATA_SECTION \ - SECTION(".wifi.rom.rodata") - -#define WIFI_RAM_TEXT_SECTION \ - SECTION(".wifi.ram.text") - -#define WIFI_RAM_DATA_SECTION \ - SECTION(".wifi.ram.data") - -//3 Hal Section -#define HAL_ROM_TEXT_SECTION \ - SECTION(".hal.rom.text") - -#define HAL_ROM_DATA_SECTION \ - SECTION(".hal.rom.rodata") - -#define HAL_RAM_TEXT_SECTION \ - SECTION(".hal.ram.text") - -#define HAL_FLASH_TEXT_SECTION \ - SECTION(".hal.flash.text") - -#define HAL_FLASH_DATA_SECTION \ - SECTION(".hal.flash.data") - -#define HAL_SDRC_TEXT_SECTION \ - SECTION(".hal.sdrc.text") - -#define HAL_SDRC_DATA_SECTION \ - SECTION(".hal.sdrc.data") - -#define HAL_CUT_B_RAM_DATA_SECTION \ - SECTION(".cutb.ram.data") - -#define HAL_CUT_C_RAM_DATA_SECTION \ - SECTION(".cutc.ram.data") - -#define HAL_RAM_DATA_SECTION \ - SECTION(".hal.ram.data") - -#define HAL_RAM_BSS_SECTION \ - SECTION(".hal.ram.bss") - -#define HAL_ROM_OP_SECTION \ - SECTION(".halop.rom.rodata") - -#define HAL_GPIO_TEXT_SECTION \ - SECTION(".hal.gpio.text") - -#define HAL_GPIO_DATA_SECTION \ - SECTION(".hal.gpio.data") - -#define FWU_DATA_SECTION \ - SECTION(".fwu.data") - -#define FWU_RODATA_SECTION \ - SECTION(".fwu.rodata") - -#define FWU_TEXT_SECTION \ - SECTION(".fwu.text") - -//3 C-Cut ROM Patch/New functions location -#define C_CUT_ROM_TEXT_SECTION \ - SECTION(".cutc.rom.text") - -#define C_CUT_ROM_RODATA_SECTION \ - SECTION(".cutc.rom.rodata") - -#define C_CUT_ROM_DATA_SECTION \ - SECTION(".cutc.ram.data") -//3 No ROM code changed for D_Cut, so no D-Cut section -//3 E-Cut ROM Patch/New functions location -#define E_CUT_ROM_TEXT_SECTION \ - SECTION(".cute.rom.text") - -#define E_CUT_ROM_RODATA_SECTION \ - SECTION(".cute.rom.rodata") - -#define E_CUT_ROM_DATA_SECTION \ - SECTION(".cute.ram.data") - -/* -#define FWUROM_DATA_SECTION \ - SECTION(".fwurom.data") - -#define FWUROM_RODATA_SECTION \ - SECTION(".fwurom.rodata") -*/ - -#define FWUROM_TEXT_SECTION \ - SECTION(".fwurom.text") - -#define XMPORT_ROM_TEXT_SECTION \ - SECTION(".xmportrom.text") - -#define XDMROM_TEXT_SECTION \ - SECTION(".xmodemrom.text") - - -//3 Store the Image 1 validate code -#if defined (__CC_ARM) -#define IMAGE1_VALID_PATTEN_SECTION \ - SECTION(".image1.validate.rodata") __attribute__((used)) -#define IMAGE2_VALID_PATTEN_SECTION \ - SECTION(".image2.validate.rodata") __attribute__((used)) -#else -#define IMAGE1_VALID_PATTEN_SECTION \ - SECTION(".image1.validate.rodata") - -#define IMAGE2_VALID_PATTEN_SECTION \ - SECTION(".image2.validate.rodata") -#endif - - -//3 Infra Section -#define INFRA_ROM_TEXT_SECTION \ - SECTION(".infra.rom.text") - -#define INFRA_ROM_DATA_SECTION \ - SECTION(".infra.rom.rodata") - -#define INFRA_RAM_TEXT_SECTION \ - SECTION(".infra.ram.text") - -#define INFRA_RAM_DATA_SECTION \ - SECTION(".infra.ram.data") - -#define INFRA_RAM_BSS_SECTION \ - SECTION(".infra.ram.bss") - -#define INFRA_START_SECTION \ - SECTION(".infra.ram.start") - - -//3 Pin Mutex Section -#define PINMUX_ROM_TEXT_SECTION \ - SECTION(".hal.rom.text") - -#define PINMUX_ROM_DATA_SECTION \ - SECTION(".hal.rom.rodata") - -#define PINMUX_RAM_TEXT_SECTION \ - SECTION(".hal.ram.text") - -#define PINMUX_RAM_DATA_SECTION \ - SECTION(".hal.ram.data") - -#define PINMUX_RAM_BSS_SECTION \ - SECTION(".hal.ram.bss") - - -//3 Monitor App Section -#define MON_ROM_TEXT_SECTION \ - SECTION(".mon.rom.text") - -#define MON_ROM_DATA_SECTION \ - SECTION(".mon.rom.rodata") - -#define MON_RAM_TEXT_SECTION \ - SECTION(".mon.ram.text") - -#define MON_RAM_DATA_SECTION \ - SECTION(".mon.ram.data") - -#define MON_RAM_BSS_SECTION \ - SECTION(".mon.ram.bss") - - -//3 SDIO Section -#define SECTION_SDIO_RAM -#define SECTION_SDIO_ROM -#define SDIO_ROM_BSS_SECTION \ - SECTION(".sdio.rom.bss") -#define SDIO_ROM_TEXT_SECTION \ - SECTION(".sdio.rom.text") - -//3 SRAM Config Section -#define SRAM_BD_DATA_SECTION \ - SECTION(".bdsram.data") - -#define SRAM_BF_DATA_SECTION \ - SECTION(".bfsram.data") - -#define START_RAM_FUN_SECTION \ - SECTION(".start.ram.data") - -#define START_RAM_FUN_A_SECTION \ - SECTION(".start.ram.data.a") - -#define START_RAM_FUN_B_SECTION \ - SECTION(".start.ram.data.b") - -#define START_RAM_FUN_C_SECTION \ - SECTION(".start.ram.data.c") - -#define START_RAM_FUN_D_SECTION \ - SECTION(".start.ram.data.d") - -#define START_RAM_FUN_E_SECTION \ - SECTION(".start.ram.data.e") - -//Non-Flash Boot Section -#define NON_FLASH_BOOT_DATA_SECTION \ - SECTION(".nonflash.data") -#define NON_FLASH_BOOT_HEAP_SECTION \ - SECTION(".nonflash.heap") - -// USB OTG Section -#define OTG_ROM_BSS_SECTION \ - SECTION(".otg.rom.bss") - -#if defined(CONFIG_CHIP_E_CUT) || defined(CONFIG_USB_BOOT_SIM) -#define OTG_ROM_TEXT_SECTION \ - SECTION(".otg.rom.text") - -#define OTG_ROM_DATA_SECTION \ - SECTION(".otg.rom.rodata") - -#define START_OTG_RAM_FUN_SECTION \ - SECTION(".ram.otg.data.a") - -#define START_OTG_RAM_DATA_SECTION \ - SECTION(".ram.otg.data.b") - -#else -#define OTG_ROM_TEXT_SECTION \ -// SECTION(".otg.ram.text") - -#define OTG_ROM_DATA_SECTION \ -// SECTION(".otg.ram.rodata") - -#define START_OTG_RAM_FUN_SECTION \ -// SECTION(".ram.otg.data.a") - -#define START_OTG_RAM_DATA_SECTION \ -// SECTION(".ram.otg.data.b") -#endif - -#if defined (__CC_ARM) -#define IMAGE2_START_RAM_FUN_SECTION \ - SECTION(".image2.ram.data") __attribute__((used)) -#else -#define IMAGE2_START_RAM_FUN_SECTION \ - SECTION(".image2.ram.data") -#endif - -#define SDRAM_DATA_SECTION \ - SECTION(".sdram.data") - -//3 Wlan Section -#define WLAN_ROM_TEXT_SECTION \ - SECTION(".wlan.rom.text") - -#define WLAN_ROM_DATA_SECTION \ - SECTION(".wlan.rom.rodata") - -#define WLAN_RAM_MAP_SECTION \ - SECTION(".wlan_ram_map") - -//3 Apple Section -#define APPLE_ROM_TEXT_SECTION \ - SECTION(".apple.rom.text") - -#define APPLE_ROM_DATA_SECTION \ - SECTION(".apple.rom.rodata") - -//3 Libc Section -#define LIBC_ROM_TEXT_SECTION \ - SECTION(".libc.rom.text") - -#define LIBC_ROM_DATA_SECTION \ - SECTION(".libc.rom.rodata") - -#define LIBC_RAM_BSS_SECTION \ - SECTION(".libc.ram.bss") - -//3 SSL Section -#define SSL_ROM_TEXT_SECTION \ - SECTION(".ssl.rom.text") - -#define SSL_ROM_DATA_SECTION \ - SECTION(".ssl.rom.rodata") - -#define SSL_RAM_MAP_SECTION \ - SECTION(".ssl_ram_map") - -#endif //_SECTION_CONFIG_H_ diff --git a/targets/TARGET_Realtek/mbed_rtx.h b/targets/TARGET_Realtek/mbed_rtx.h deleted file mode 100644 index ce516af453b..00000000000 --- a/targets/TARGET_Realtek/mbed_rtx.h +++ /dev/null @@ -1,33 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - -#if defined(TARGET_RTL8195A) - -#include "rtl8195a.h" - -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; - #define INITIAL_SP ((uint32_t)(Image$$ARM_LIB_STACK$$ZI$$Base)) -#elif defined(__GNUC__) - extern uint32_t __StackTop; - #define INITIAL_SP ((uint32_t)(&__StackTop)) -#endif - -#endif -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h deleted file mode 100644 index ba3c327aeb5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_6 = (int)USART6_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 5 -typedef enum { - SPI_1 = (int)SPI1_BASE, ELMO_RF_SPI2 = SPI_1, - SPI_2 = (int)SPI2_BASE, ELMO_SPI1 = SPI_2, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE, - SPI_5 = (int)SPI5_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c deleted file mode 100644 index 7d2eb4d6b5a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c +++ /dev/null @@ -1,212 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, - {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, -// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO -// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, - {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO - {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO - {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO - {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, - {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO - {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, - {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { -// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, -// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK -// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h deleted file mode 100644 index e81c7b8479e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h +++ /dev/null @@ -1,176 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_2 = 0x32, - - PH_0 = 0x70, - PH_1 = 0x71, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Arduino connector namings - A0 = PC_0, - A1 = PC_1, - A2 = PC_2, - A3 = PC_3, - A4 = NC, - A5 = NC, - D0 = PA_3, - D1 = PA_2, - D2 = PA_1, - D3 = PA_0, - D4 = NC, - D5 = NC, - D6 = NC, - D7 = NC, - D8 = NC, - D9 = NC, - D10 = PB_12, - D11 = PB_15, - D12 = PB_14, - D13 = PB_13, - D14 = PC_9, - D15 = PA_8, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#else - STDIO_UART_TX = PA_9, -#endif -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#else - STDIO_UART_RX = PA_10, -#endif - - // Generic signals namings - LED1 = PB_0, - LED2 = PB_1, - LED3 = PB_0, - LED4 = PB_1, - USER_BUTTON = PB_7, - // Standardized button names - BUTTON1 = USER_BUTTON, - SERIAL_TX = STDIO_UART_TX, - SERIAL_RX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - USBRX = STDIO_UART_RX, - I2C_SCL = D15, - I2C_SDA = D14, - SPI_MOSI = D11, - SPI_MISO = D12, - SPI_SCK = D13, - SPI_CS = D10, - RF_SPI_MOSI = PA_7, - RF_SPI_MISO = PA_6, - RF_SPI_SCK = PA_5, - RF_SPI_CS = PA_4, - RF_RESET = PC_4, - RF_DIO0 = PC_10, - RF_DIO1 = PC_11, - RF_DIO2 = PC_12, - RF_DIO3 = PD_2, - RF_DIO4 = PB_5, - RF_DIO5 = PB_6, - RF_RXTX_SW = PC_13 -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c deleted file mode 100644 index 731bf598537..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c +++ /dev/null @@ -1,191 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 8 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 96 | 96 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 96 | 96 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 48 | 48 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 96 | 96 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | YES - *----------------------------------------------------------------------------- -**/ - -#include "stm32f4xx.h" - - -/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ -#define USE_PLL_HSE_EXTC (0) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ - - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif - -uint8_t SetSysClock_PLL_HSI(void); - - - -/** -* @brief Configures the System clock source, PLL Multiplier and Divider factors, -* AHB/APBx prescalers and Flash settings -* @note This function should be called only once the RCC clock configuration -* is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - /* 1- Try to start with HSE and external clock */ -#if USE_PLL_HSE_EXTC != 0 - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { - /* 2- If fail try to start with HSE and external xtal */ -#if USE_PLL_HSE_XTAL != 0 - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) { - while (1) { - // [TODO] Put something here to tell the user that a problem occured... - } - } - } - } - - /* Output clock on MCO2 pin(PC9) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz -} - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) - //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) - //RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) - //RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) - - RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 2 MHz (8 MHz / 4) - RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (2 MHz * 192) - - - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) - RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - - //if (bypass == 0) - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal - //else - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock - - return 1; // OK -} -#endif - -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) - //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) - RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) - RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) - RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_WIO_EMW3166/PeripheralNames.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_WIO_EMW3166/PeripheralNames.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_WIO_EMW3166/PeripheralPins.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralPins.c rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_WIO_EMW3166/PeripheralPins.c diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_WIO_EMW3166/PinNames.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_WIO_EMW3166/PinNames.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_WIO_EMW3166/system_clock.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_WIO_EMW3166/system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h deleted file mode 100644 index 361fe5e0e18..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h +++ /dev/null @@ -1,100 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE, - UART_6 = (int)USART6_BASE, - UART_7 = (int)UART7_BASE, - UART_8 = (int)UART8_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 6 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE, - SPI_5 = (int)SPI5_BASE, - SPI_6 = (int)SPI6_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE, - PWM_12 = (int)TIM12_BASE, - PWM_13 = (int)TIM13_BASE, - PWM_14 = (int)TIM14_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE, - CAN_2 = (int)CAN2_BASE -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c deleted file mode 100644 index adb6f141506..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c +++ /dev/null @@ -1,161 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - - {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -// TIM3 cannot be used because already used by the Bluetooth UART -// TIM1 is used by LPO emulation. If external LPO is connected this can be used for PWM. -const PinMap PinMap_PWM[] = { - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_USART6)}, // HCI UART_TX - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_USART6)}, // HCI UART_RX - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RTS[] = { - {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_USART6)}, // HCI UART_RTS - {NC, NC, 0} -}; - -const PinMap PinMap_UART_CTS[] = { - {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLDOWN, GPIO_AF8_USART6)}, // HCI UART_CTS - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {NC, NC, 0} -}; - -const PinMap PinMap_CAN_RD[] = { - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_CAN_TD[] = { - {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h deleted file mode 100644 index 6e01719b920..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h +++ /dev/null @@ -1,195 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, - PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - - PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, - PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, - PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, - PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, - - PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, - PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, - PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, - PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, - - PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, - PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, - PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, - PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, - - PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, - PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, - PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, - PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, - - PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, - PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, - PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, - PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, - - PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, - PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, - PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, - PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, - - PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, - PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, - PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, - PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, - - // Module Pins - // A - P_A5 = PC_2, // UART-DTR - P_A6 = PF_2, // Switch-0 - P_A7 = PE_0, // Red, Mode - P_A8 = PB_6, // Green, Switch-1 - P_A9 = PB_8, // Blue - P_A10 = PA_11, // UART-CTS - P_A11 = PA_9, // UART-TXD - P_A12 = PA_12, // UART-RTS - P_A13 = PA_10, // UART-RXD - P_A14 = PD_9, // GPIO-0 - P_A15 = PD_8, // GPIO-1 - P_A16 = PD_11, // GPIO-2 - P_A17 = PD_12, // GPIO-3 - P_A18 = PA_3, // UART-DSR - // B - // C - P_C5 = PG_4, // SPI-IRQ - P_C6 = PE_13, // SPI-MISO - P_C8 = PE_12, // Res - P_C10 = PE_14, // SPI-MOSI - P_C11 = PE_11, // SPI-CS0 - P_C12 = PE_9, // Res - P_C13 = PF_6, // GPIO-4 - P_C14 = PC_1, // RMII-MDC - P_C15 = PA_2, // RMII-MDIO - P_C16 = PF_7, // GPIO-7 - P_C17 = PF_1, // I2C-SCL - P_C18 = PF_0, // I2C-SDA - // D - P_D1 = PB_12, // RMII-TXD0 - P_D2 = PB_13, // RMII-TXD1 - P_D3 = PB_11, // RMII-TXEN - P_D4 = PA_7, // RMII-CRSDV - P_D5 = PC_4, // RMII-RXD0 - P_D6 = PC_5, // RMII-RXD1 - P_D8 = PA_1, // RMII-REFCLK - // TP - P_TP5 = PB_4, // NTRST - P_TP7 = PA_13, // TMS SWDIO - P_TP8 = PA_15, // TDI - P_TP9 = PA_14, // TCK SWCLK - P_TP10 = PB_3, // TDO - //P_TP11, // BOOT0 - - // Internal - LED1 = PD_9, - LED2 = PA_12, - LED3 = PD_8, - LED4 = PA_11, - LED5 = PC_2, - LED6 = PA_3, - LED7 = PF_6, - LED_RED = PE_0, - LED_GREEN = PB_6, - LED_BLUE = PB_8, - SW1 = PF_2, - SW2 = PG_4, - - // Standardized button names - BUTTON1 = SW1, - BUTTON2 = SW2, - - I2C_SDA = PF_0, - I2C_SCL = PF_1, - SPI0_MOSI = PE_14, - SPI0_MISO = PE_13, - SPI0_SCK = PE_12, - SPI0_CS = PE_11, - SPI1_CS = PE_9, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - SPI_MOSI = SPI0_MOSI, - SPI_MISO = SPI0_MISO, - SPI_SCK = SPI0_SCK, - SPI_CS = SPI0_CS, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#elif MBED_CONF_TARGET_USB_TX - STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, -#else - STDIO_UART_TX = PA_9, -#endif - -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#elif MBED_CONF_TARGET_USB_RX - STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, -#else - STDIO_UART_RX = PA_10, -#endif - - // DAPLink - USBRX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - SWDIO = PA_15, - SWCLK = PA_14, - NTRST = PB_4, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h deleted file mode 100644 index ec9c26f91cb..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h +++ /dev/null @@ -1,256 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, - PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - - PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, - PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, - PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, - PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, - - PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, - PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, - PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, - PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, - - PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, - PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, - PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, - PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, - - PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, - PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, - PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, - PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, - - PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, - PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, - PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, - PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, - - PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, - PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, - PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, - PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, - - PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, - PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, - PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, - PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Module Pins - // PortA - P_A1 = NC, - P_A2 = NC, - P_A3 = NC, - P_A4 = NC, - P_A5 = PC_2, - P_A6 = PF_2, - P_A7 = PE_0, - P_A8 = PB_6, - P_A9 = PB_8, - P_A10 = PA_11, - P_A11 = PA_9, - P_A12 = PA_12, - P_A13 = PA_10, - P_A14 = PD_9, - P_A15 = PD_8, - P_A16 = PD_11, - P_A17 = PD_12, - P_A18 = PA_3, - // PortB - P_B1 = NC, - P_B2 = NC, - P_B3 = NC, - P_B4 = NC, - P_B5 = NC, - P_B6 = NC, - P_B7 = NC, - P_B8 = NC, - // PortC - P_C1 = NC, - P_C2 = NC, - P_C3 = NC, - P_C4 = NC, - P_C5 = PG_4, - P_C6 = PE_13, - P_C7 = NC, - P_C8 = PE_12, - P_C9 = NC, - P_C10 = PE_14, - P_C11 = PE_11, - P_C12 = PE_9, - P_C13 = PF_6, - P_C14 = PC_1, - P_C15 = PA_2, - P_C16 = PF_7, - P_C17 = PF_1, - P_C18 = PF_0, - // PortD - P_D1 = PB_12, - P_D2 = PB_13, - P_D3 = PB_11, - P_D4 = PA_7, - P_D5 = PC_4, - P_D6 = PC_5, - P_D7 = NC, - P_D8 = PA_1, - // TestPads - P_TP5 = PB_4, - P_TP7 = PA_13, - P_TP8 = PA_15, - P_TP9 = PA_14, - P_TP10 = PB_3, - //P_TP11, // BOOT0 - - // Mbed pins - LED_RED = PE_0, - LED_GREEN = PB_6, - LED_BLUE = PB_8, - - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - - SW1 = PF_2, - - // Standardized button names - BUTTON1 = SW1, - - I2C_SDA = PF_0, - I2C_SCL = PF_1, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - SPI0_MOSI = PE_14, - SPI0_MISO = PE_13, - SPI0_SCK = PE_12, - SPI0_CS = PE_11, //CS for SPI Flash on MCB - SPI1_CS = PE_9, //CS for LCD on MTB - SPI2_CS = PG_4, //CS for SD card on MTB - - SPI_MOSI = SPI0_MOSI, - SPI_MISO = SPI0_MISO, - SPI_SCK = SPI0_SCK, - SPI_CS = SPI0_CS, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#elif MBED_CONF_TARGET_USB_TX - STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, -#else - STDIO_UART_TX = PA_9, -#endif - -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#elif MBED_CONF_TARGET_USB_RX - STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, -#else - STDIO_UART_RX = PA_10, -#endif - - // DAPLink - USBRX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - SWDIO = PA_15, - SWCLK = PA_14, - NTRST = PB_4, - - // MTB Aliases - // Left side (top view) - TGT_SWDIO = SWDIO, - TGT_SWCLK = SWCLK, - TGT_RESET = NTRST, - TGT_TX = USBTX, - TGT_RX = USBRX, - TX1 = P_A15, - RX1 = P_A14, - SDA1 = P_C18, - SCL1 = P_C17, - MOSI1 = P_C10, - MISO1 = P_C6, - SCK1 = SPI_SCK, - GP0 = BUTTON1, - GP1 = P_C11, - AIN0 = P_C13, - AIN1 = P_A18, - AIN2 = P_A5, - - //Right side (top view) - GND = NC, - GP10 = NC, - RTS = NC, - CTS = NC, - GP7 = P_C12, //LCD CS on MTB - GP6 = P_A12, //LCD Reset on MTB - GP5 = P_A10, //LCD A0 on MTB - GP4 = P_A17, - TX2 = NC, - RX2 = NC, - SDA2 = NC, - SCL2 = NC, - MOSI2 = NC, - MISO2 = NC, - SCK2 = NC, - GP3 = P_A16, - GP2 = P_C5, //CS for SD Card on MTB - PWM2 = LED_GREEN, - PWM1 = LED_BLUE, - PWM0 = LED_RED, - -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_OKDO_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_OKDO_ODIN_W2/PinNames.h deleted file mode 100644 index 7d6186f36bd..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_OKDO_ODIN_W2/PinNames.h +++ /dev/null @@ -1,236 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, - PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - - PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, - PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, - PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, - PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, - - PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, - PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, - PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, - PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, - - PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, - PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, - PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, - PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, - - PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, - PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, - PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, - PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, - - PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, - PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, - PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, - PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, - - PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, - PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, - PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, - PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, - - PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, - PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, - PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, - PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Module Pins - // PortA - P_A1 = NC, - P_A2 = NC, - P_A3 = NC, - P_A4 = NC, - P_A5 = PC_2, - P_A6 = PF_2, - P_A7 = PE_0, - P_A8 = PB_6, - P_A9 = PB_8, - P_A10 = PA_11, - P_A11 = PA_9, - P_A12 = PA_12, - P_A13 = PA_10, - P_A14 = PD_9, - P_A15 = PD_8, - P_A16 = PD_11, - P_A17 = PD_12, - P_A18 = PA_3, - // PortB - P_B1 = NC, - P_B2 = NC, - P_B3 = NC, - P_B4 = NC, - P_B5 = NC, - P_B6 = NC, - P_B7 = NC, - P_B8 = NC, - // PortC - P_C1 = NC, - P_C2 = NC, - P_C3 = NC, - P_C4 = NC, - P_C5 = PG_4, - P_C6 = PE_13, - P_C7 = NC, - P_C8 = PE_12, - P_C9 = NC, - P_C10 = PE_14, - P_C11 = PE_11, - P_C12 = PE_9, - P_C13 = PF_6, - P_C14 = PC_1, - P_C15 = PA_2, - P_C16 = PF_7, - P_C17 = PF_1, - P_C18 = PF_0, - // PortD - P_D1 = PB_12, - P_D2 = PB_13, - P_D3 = PB_11, - P_D4 = PA_7, - P_D5 = PC_4, - P_D6 = PC_5, - P_D7 = NC, - P_D8 = PA_1, - // TestPads - P_TP5 = PB_4, - P_TP7 = PA_13, - P_TP8 = PA_15, - P_TP9 = PA_14, - P_TP10 = PB_3, - //P_TP11, // BOOT0 - - // Mbed pins - LED_RED = PE_0, - LED_GREEN = PB_6, - LED_BLUE = PB_8, - - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - - SW1 = PF_2, - - // Standardized button names - BUTTON1 = SW1, - - I2C_SDA = PF_0, - I2C_SCL = PF_1, - - SPI0_MOSI = PE_14, - SPI0_MISO = PE_13, - SPI0_SCK = PE_12, - SPI0_CS = PE_11, //CS for SPI Flash on MCB - SPI1_CS = PE_9, //CS for LCD on MTB - SPI2_CS = PG_4, //CS for SD card on MTB - - SPI_MOSI = SPI0_MOSI, - SPI_MISO = SPI0_MISO, - SPI_SCK = SPI0_SCK, - SPI_CS = SPI0_CS, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#elif MBED_CONF_TARGET_USB_TX - STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, -#else - STDIO_UART_TX = PA_9, -#endif - -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#elif MBED_CONF_TARGET_USB_RX - STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, -#else - STDIO_UART_RX = PA_10, -#endif - - // DAPLink - USBRX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - SWDIO = PA_15, - SWCLK = PA_14, - NTRST = PB_4, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - //Right side (top view) - GND = NC, - GP10 = NC, - RTS = NC, - CTS = NC, - GP7 = P_C12, //LCD CS on MTB - GP6 = P_A12, //LCD Reset on MTB - GP5 = P_A10, //LCD A0 on MTB - GP4 = P_A17, - TX2 = NC, - RX2 = NC, - SDA2 = NC, - SCL2 = NC, - MOSI2 = NC, - MISO2 = NC, - SCK2 = NC, - GP3 = P_A16, - GP2 = P_C5, //CS for SD Card on MTB - PWM2 = LED_GREEN, - PWM1 = LED_BLUE, - PWM0 = LED_RED, - -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h deleted file mode 100644 index f57551108b1..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h +++ /dev/null @@ -1,218 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, - PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - - PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, - PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, - PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, - PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, - - PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, - PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, - PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, - PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, - - PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, - PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, - PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, - PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, - - PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, - PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, - PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, - PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, - - PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, - PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, - PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, - PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, - - PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, - PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, - PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, - PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, - - PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, - PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, - PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, - PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, - - // Module Pins - // A - P_A5 = PC_2, // UART-DTR - P_A6 = PF_2, // Switch-0 - P_A7 = PE_0, // Red, Mode - P_A8 = PB_6, // Green, Switch-1 - P_A9 = PB_8, // Blue - P_A10 = PA_11, // UART-CTS - P_A11 = PA_9, // UART-TXD - P_A12 = PA_12, // UART-RTS - P_A13 = PA_10, // UART-RXD - P_A14 = PD_9, // GPIO-0 - P_A15 = PD_8, // GPIO-1 - P_A16 = PD_11, // GPIO-2 - P_A17 = PD_12, // GPIO-3 - P_A18 = PA_3, // UART-DSR - // B - // C - P_C5 = PG_4, // SPI-IRQ - P_C6 = PE_13, // SPI-MISO - P_C8 = PE_12, // Res - P_C10 = PE_14, // SPI-MOSI - P_C11 = PE_11, // SPI-CS0 - P_C12 = PE_9, // Res - P_C13 = PF_6, // GPIO-4 - P_C14 = PC_1, // RMII-MDC - P_C15 = PA_2, // RMII-MDIO - P_C16 = PF_7, // GPIO-7 - P_C17 = PF_1, // I2C-SCL - P_C18 = PF_0, // I2C-SDA - // D - P_D1 = PB_12, // RMII-TXD0 - P_D2 = PB_13, // RMII-TXD1 - P_D3 = PB_11, // RMII-TXEN - P_D4 = PA_7, // RMII-CRSDV - P_D5 = PC_4, // RMII-RXD0 - P_D6 = PC_5, // RMII-RXD1 - P_D8 = PA_1, // RMII-REFCLK - // TP - P_TP5 = PB_4, // NTRST - P_TP7 = PA_13, // TMS SWDIO - P_TP8 = PA_15, // TDI - P_TP9 = PA_14, // TCK SWCLK - P_TP10 = PB_3, // TDO - //P_TP11, // BOOT0 - - // Board Pins - // A0-A5 - A0 = PF_6, // AI4 - A1 = PA_3, // AI3 - A2 = PC_2, // AI12 - A3 = PF_7, // LPOCLK, not AI - A4 = PG_4, // not AI - A5 = PE_0, // not AI - // D0-D15 - D0 = PD_9, // UART3-RX - D1 = PD_8, // UART3-TX - D2 = PA_10, // UART1-RX - D3 = PA_11, // CAN1-RX - D4 = PA_12, // CAN1-TX - D5 = PB_8, - D6 = PD_11, // UART3-CTS - D7 = PD_12, // UART3-RTS - D8 = PA_9, // UART1-TX - D9 = PE_9, // SDCard-CS - D10 = PE_11, // SSEL - D11 = PE_14, // MOSI - D12 = PE_13, // MISO - D13 = PE_12, // SCK - D14 = PF_0, // SDA - D15 = PF_1, // SCL - // Internal - LED1 = PE_0, // Red / Mode - LED2 = PB_6, // Green / Switch-1 - LED3 = PB_8, // Blue - LED4 = D10, - LED_RED = LED1, - LED_GREEN = LED2, - LED_BLUE = LED3, - SW0 = PF_2, // Switch-0 - SW1 = PB_6, // Green / Switch-1 - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - I2C_SCL = D15, - I2C_SDA = D14, - SPI0_MOSI = D11, - SPI0_MISO = D12, - SPI0_SCK = D13, - SPI0_CS = D10, - SPI1_CS = D9, - - SPI_MOSI = SPI0_MOSI, - SPI_MISO = SPI0_MISO, - SPI_SCK = SPI0_SCK, - SPI_CS = SPI0_CS, - - - // Standardized button names - BUTTON1 = SW0, - BUTTON2 = SW1, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#elif MBED_CONF_TARGET_USB_TX - STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, -#else - STDIO_UART_TX = D8, -#endif - -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#elif MBED_CONF_TARGET_USB_RX - STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, -#else - STDIO_UART_RX = D2, -#endif - - // ST-Link - USBRX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - SWDIO = PA_15, - SWCLK = PA_14, - NTRST = PB_4, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c deleted file mode 100644 index bf5cd658e68..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c +++ /dev/null @@ -1,45 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2017, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : HAL - * File : hal_overrides.c - * - * Description : Placeholder for HAL overrides. - *-------------------------------------------------------------------------*/ - -#include "stm32f4xx_hal.h" -#include "stm32f4xx_hal_rcc.h" -#include "stm32f4xx_hal_gpio.h" - -void HAL_MspInit(void) -{ - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - - GPIO_InitTypeDef GPIO_InitDef; - - GPIO_InitDef.Pin = GPIO_PIN_6 | GPIO_PIN_8; - GPIO_InitDef.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitDef.Pull = GPIO_NOPULL; - GPIO_InitDef.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(GPIOB, &GPIO_InitDef); - - GPIO_InitDef.Pin = GPIO_PIN_0; - HAL_GPIO_Init(GPIOE, &GPIO_InitDef); - - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_SET); - HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, GPIO_PIN_SET); -} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE deleted file mode 100644 index a8161761a33..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE +++ /dev/null @@ -1,2 +0,0 @@ -Unless specifically indicated otherwise in a file, files are licensed under the -Permissive Binary License1.0 (PBL-1.0) as can be found in: LICENSE-permissive-binary-license-1.0.txt diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt deleted file mode 100644 index d648fd563a7..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt +++ /dev/null @@ -1,49 +0,0 @@ -Permissive Binary License - -Version 1.0, September 2015 - -Redistribution. Redistribution and use in binary form, without -modification, are permitted provided that the following conditions are -met: - -1) Redistributions must reproduce the above copyright notice and the - following disclaimer in the documentation and/or other materials - provided with the distribution. - -2) Unless to the extent explicitly permitted by law, no reverse - engineering, decompilation, or disassembly of this software is - permitted. - -3) Redistribution as part of a software development kit must include the - accompanying file named “DEPENDENCIES” and any dependencies listed in - that file. - -4) Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -Limited patent license. The copyright holders (and contributors) grant a -worldwide, non-exclusive, no-charge, royalty-free patent license to -make, have made, use, offer to sell, sell, import, and otherwise -transfer this software, where such license applies only to those patent -claims licensable by the copyright holders (and contributors) that are -necessarily infringed by this software. This patent license shall not -apply to any combinations that include this software. No hardware is -licensed hereunder. - -If you institute patent litigation against any entity (including a -cross-claim or counterclaim in a lawsuit) alleging that the software -itself infringes your patent(s), then your rights granted under this -license shall terminate as of the date such litigation is filed. - -DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND -CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT -NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar deleted file mode 100644 index 8390fe50e39..00000000000 Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar and /dev/null differ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a deleted file mode 100644 index 7923dfc2d6e..00000000000 Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a and /dev/null differ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a deleted file mode 100644 index a7e547190d6..00000000000 Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a and /dev/null differ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.cpp deleted file mode 100644 index 40dbe5c495e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.cpp +++ /dev/null @@ -1,2080 +0,0 @@ -/* ODIN-W2 implementation of WiFiInterface - * Copyright (c) 2016 u-blox Malmö AB - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if MBED_CONF_LWIP_PRESENT - -#include "OdinWiFiInterface.h" -#include "cb_main.h" -#include "cb_wlan.h" -#include "cb_wlan_types.h" -#include "cb_wlan_driver_config.h" - -#include "wifi_emac.h" -#include "netsocket/WiFiAccessPoint.h" -#include "enterprise_handle.h" - -#define VALIDATE_CERT(X) \ - if(strlen(X) > cbSECMNG_MAX_CERTIFICATE_SIZE){ \ - return NSAPI_ERROR_PARAMETER; \ - } \ - -#define ODIN_WIFI_BSSID_CACHE (5) -#define ODIN_WIFI_STA_DEFAULT_CONN_TMO (20000) - -#define ODIN_WIFI_AP_ALLOWED_RATE_MASK 0xfffffff -#define ODIN_MAX_AP_STATIONS (10) - -#define APP_MASK_LOWESTBIT(BITMASK) ((BITMASK) & (-(BITMASK))) -#define APP_MASK_SHIFTUP(MASK, SHIFTMASK) ((cbWLAN_RateMask)((SHIFTMASK != 0 ) ? (MASK * APP_MASK_LOWESTBIT(SHIFTMASK)) : MASK)) - -enum user_msg_types_t { - // cbWLAN_StatusIndicationInfo use from 0 to ~10 - - cbWLAN_SCAN_INDICATION = 100, - - ODIN_WIFI_MSG_USER_CONNECT, - ODIN_WIFI_MSG_USER_DISCONNECT, - ODIN_WIFI_MSG_USER_CONNECT_TIMEOUT, - ODIN_WIFI_MSG_USER_SCAN, - ODIN_WIFI_MSG_USER_SCAN_RSP, - ODIN_WIFI_MSG_USER_STOP, - - ODIN_WIFI_MSG_USER_AP_START, - ODIN_WIFI_MSG_USER_AP_STOP -}; - -struct user_connect_s { - const char *ssid; - const char *passwd; - uint8_t channel; - auth_cert_s *cert_handle; - nsapi_security_t security; - unsigned int timeout; - const char *user_name; - const char *user_passwd; -}; - -struct user_scan_s { - WiFiAccessPoint *ap_list; - nsapi_size_t ap_list_size; -}; - -struct user_scan_rsp_s { - WiFiAccessPoint *ap_list; - nsapi_size_or_error_t found_aps; -}; - -struct user_response_s { - nsapi_error_t error; -}; - -struct user_ap_start_s { - const char *ssid; - const char *passwd; - uint8_t channel; - nsapi_security_t security; - uint16_t beacon_interval; -}; - -struct wlan_status_started_s { - cbWLAN_StatusStartedInfo info; -}; - -struct wlan_status_connected_s { - cbWLAN_StatusConnectedInfo info; -}; - -struct wlan_status_connection_failure_s { - cbWLAN_StatusDisconnectedInfo info; -}; - -struct odin_wifi_msg_s { - unsigned int type; - - union data_t { - struct user_connect_s user_connect; - struct user_response_s user_response; - struct user_scan_s user_scan; - struct user_scan_rsp_s user_scan_rsp; - struct user_ap_start_s user_ap_start; - struct wlan_status_started_s wlan_status_started; - struct wlan_status_connected_s wlan_status_connected; - struct wlan_status_connection_failure_s wlan_status_connection_failure; - } data; -}; - -static void generateWEPKeys(const char *passphrase, cbWLAN_WEPKey keys[4]); - -static void set_wpa_rsn_cipher( - nsapi_security_t security, - cbWLAN_CipherSuite &wpa_ciphers, - cbWLAN_CipherSuite &rsn_ciphers); - -static bool is_valid_AP_channel(cbWLAN_Channel channel); -static cbTARGET_ConfigParams map_odin_config(target_config_params_e parameter); -static cbTARGET_PowerSaveMode convertPowerSaveAtToIoctl(target_power_save_mode_e powerSaveMode); - -// Friend declared C-functions that calls corresponding wi-fi object member function -struct wlan_callb_s { - - static void scan_indication_callback(void *callb_context, cbWLAN_ScanIndicationInfo *scan_info, cb_boolean is_last_result) - { - MBED_ASSERT(callb_context != NULL); - - OdinWiFiInterface *wifi = (OdinWiFiInterface*)callb_context; - - wifi->wlan_scan_indication(scan_info, is_last_result); - }; - - static void status_indication_callback(void *callb_context, cbWLAN_StatusIndicationInfo status, void *data) - { - MBED_ASSERT(callb_context != NULL); - - OdinWiFiInterface *wifi = (OdinWiFiInterface*)callb_context; - - wifi->wlan_status_indication(status, data); - }; - - static void odin_thread_fcn(OdinWiFiInterface *wifi) - { - wifi->handle_in_msg(); - }; -}; - -// Static declared class variables -bool OdinWiFiInterface::_wlan_initialized = false; -int32_t OdinWiFiInterface::_target_id = cbMAIN_TARGET_INVALID_ID; - -OdinWiFiInterface::OdinWiFiInterface(OdinWiFiEMAC &emac_obj, OnboardNetworkStack &stack) : - EMACInterface(emac_obj, stack), - _thread(osPriorityNormal, 4096) -{ - init(false); -} - -OdinWiFiInterface::OdinWiFiInterface(bool debug, OdinWiFiEMAC &emac_obj, OnboardNetworkStack &stack) : - EMACInterface(emac_obj, stack), - _thread(osPriorityNormal, 4096) -{ - init(debug); -} - -OdinWiFiInterface::~OdinWiFiInterface() -{ - osStatus ok; - - // Allocate and initialize user_connect message - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_STOP; - - // Put user_connect message in input queue or cache queue - switch(_state) { - case S_STARTED: - ok = _in_queue.put(msg, 0); - MBED_ASSERT(ok == osOK); - break; - - case S_WAIT_START: - ok = _cache_queue.put(msg, 0); - MBED_ASSERT(ok == osOK); - break; - - default: - MBED_ASSERT(false); - break; - } - - // To synchronize, wait until response message is available - osEvent evt = _out_queue.get(); - MBED_ASSERT(evt.status == osEventMessage); - - msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_STOP); - - //Final cleanup - _thread.terminate(); - delete _msg_pool; -} - -nsapi_error_t OdinWiFiInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) -{ - int len; - - if(ssid == NULL || *ssid == '\0' ) { - return NSAPI_ERROR_PARAMETER; - } - - if ((pass == NULL || *pass == '\0') && (security == NSAPI_SECURITY_WEP || security == NSAPI_SECURITY_WPA - || security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA_WPA2)){ - return NSAPI_ERROR_PARAMETER; - } - - len = strlen(pass); - - if (len > cbWLAN_MAX_PASSPHRASE_LENGTH -1){ - return NSAPI_ERROR_PARAMETER; - } - - _mutex.lock(); - - strncpy(_sta.ssid, ssid, cbWLAN_SSID_MAX_LENGTH); - strncpy(_sta.passwd, pass, cbWLAN_MAX_PASSPHRASE_LENGTH); - _sta.security = security; - - _mutex.unlock(); - - return NSAPI_ERROR_OK; -} - -nsapi_error_t OdinWiFiInterface::set_certificates(const char *client_cert, const char *client_pvt_key , const char *ca_cert ) -{ - int size; - - /* Check if client certificate is valid */ - if((client_cert != NULL) && (*client_cert != '\0')) { - VALIDATE_CERT(client_cert); - _certs.client_cert = client_cert; - /* Check if private key is valid in case passed separately from client_cert */ - if (client_pvt_key!= NULL){ - VALIDATE_CERT(client_pvt_key); - } - /* If private key is passed as part of client cert it could be NULL */ - _certs.client_prvt_key = client_pvt_key; - } - - /* Check if ca certificate is valid */ - if((ca_cert != NULL) || (*ca_cert != '\0' )) { - VALIDATE_CERT(ca_cert); - _certs.ca_cert = ca_cert; - } - - return NSAPI_ERROR_OK; -} - -nsapi_error_t OdinWiFiInterface::set_channel(uint8_t channel) -{ - if (channel > 165 || (channel > 11 && channel < 36)){ - return NSAPI_ERROR_PARAMETER; - } - - _mutex.lock(); - _sta.channel = channel; - _mutex.unlock(); - - return NSAPI_ERROR_OK; -} - -nsapi_error_t OdinWiFiInterface::set_timeout(int ms) -{ - _mutex.lock(); - _sta.timeout_ms = ms; - _mutex.unlock(); - - return NSAPI_ERROR_OK; -} - -nsapi_error_t OdinWiFiInterface::connect() -{ - return connect(_sta.ssid, _sta.passwd, _sta.security, _sta.channel); -} - -nsapi_error_t OdinWiFiInterface::connect( - const char *ssid, - const char *pass, - nsapi_security_t security, - uint8_t channel) -{ - nsapi_error_t error_code = NSAPI_ERROR_OK; - osStatus ok; - - if (ssid == NULL || *ssid == NULL) { - return NSAPI_ERROR_PARAMETER; - } - - if ((pass == NULL || *pass == NULL) && (security == NSAPI_SECURITY_WEP || security == NSAPI_SECURITY_WPA - || security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA_WPA2)){ - return NSAPI_ERROR_PARAMETER; - } - - // Allocate and initialize user_connect message - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_CONNECT; - msg->data.user_connect.ssid = ssid; // Must be valid until task is completed - msg->data.user_connect.passwd = pass; // Must be valid until task is completed - msg->data.user_connect.security = security; - msg->data.user_connect.channel = channel; - - // Put user_connect message in input queue or cache queue - switch(_state) { - case S_STARTED: - ok = _in_queue.put(msg, 0); - MBED_ASSERT(ok == osOK); - break; - - case S_WAIT_START: - ok = _cache_queue.put(msg, 0); // handle once we are started - MBED_ASSERT(ok == osOK); - break; - - default: - MBED_ASSERT(false); - break; - } - - // To synchronize, wait until response message is available - osEvent evt = _out_queue.get(); - MBED_ASSERT(evt.status == osEventMessage); - - msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_CONNECT); - - // Return the result of the connect call - error_code = msg->data.user_response.error; - - ok = _msg_pool->free(msg); - MBED_ASSERT(ok == osOK); - - return error_code; -} - -nsapi_error_t OdinWiFiInterface::connect( - const char *ssid, - const char *pass, - nsapi_security_t security, - auth_cert_s *cert_handle, - const char *username, - const char *user_pswd, - uint8_t channel) -{ - nsapi_error_t error_code = NSAPI_ERROR_OK; - osStatus ok; - - if(ssid == NULL || *ssid == NULL || cert_handle == NULL) { - return NSAPI_ERROR_PARAMETER; - } - - if((security == NSAPI_SECURITY_PEAP) && (username == NULL || user_pswd == NULL)) { - return NSAPI_ERROR_PARAMETER; - } - - if((security == NSAPI_SECURITY_EAP_TLS) && (cert_handle->client_cert == NULL || cert_handle->client_prvt_key == NULL)) { - return NSAPI_ERROR_PARAMETER; - } - - if((pass == NULL || *pass == NULL) && (security == NSAPI_SECURITY_WEP || security == NSAPI_SECURITY_WPA - || security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA_WPA2)) { - return NSAPI_ERROR_PARAMETER; - } - - // Allocate and initialize user_connect message - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_CONNECT; - msg->data.user_connect.ssid = ssid; // Must be valid until task is completed - msg->data.user_connect.passwd = pass; // Must be valid until task is completed - msg->data.user_connect.security = security; - msg->data.user_connect.channel = channel; - msg->data.user_connect.cert_handle = cert_handle; - msg->data.user_connect.user_name = username; - msg->data.user_connect.user_passwd = user_pswd; - - // Put user_connect message in input queue or cache queue - switch(_state) { - case S_STARTED: - ok = _in_queue.put(msg, 0); - MBED_ASSERT(ok == osOK); - break; - - case S_WAIT_START: - ok = _cache_queue.put(msg, 0); // handle once we are started - MBED_ASSERT(ok == osOK); - break; - - default: - MBED_ASSERT(false); - break; - } - - // To synchronize, wait until response message is available - osEvent evt = _out_queue.get(); - MBED_ASSERT(evt.status == osEventMessage); - - msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_CONNECT); - - // Return the result of the connect call - error_code = msg->data.user_response.error; - - ok = _msg_pool->free(msg); - MBED_ASSERT(ok == osOK); - - return error_code; -} - -nsapi_error_t OdinWiFiInterface::disconnect() -{ - nsapi_error_t error_code = NSAPI_ERROR_OK; - - // Allocate and init the user disconnect message - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_DISCONNECT; - - // Put the user disconnect message in the input queue - osStatus ok = _in_queue.put(msg); - MBED_ASSERT(ok == osOK); - - // To synchronize, wait until response message is available - osEvent evt = _out_queue.get(); - MBED_ASSERT(evt.status == osEventMessage); - - msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_DISCONNECT); - - // Return the result of the disconnect call - error_code = msg->data.user_response.error; - - _msg_pool->free(msg); - - return error_code; -} - -int8_t OdinWiFiInterface::get_rssi() -{ - cbMAIN_driverLock(); - int8_t rssi = cbWLAN_STA_getRSSI(); - cbMAIN_driverUnlock(); - - return rssi; -} - -int OdinWiFiInterface::scan(WiFiAccessPoint *res_list, unsigned count) -{ - osStatus ok; - nsapi_size_or_error_t found_aps = NSAPI_ERROR_DEVICE_ERROR; - - // Allocate and initialize user_connect message - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_SCAN; - msg->data.user_scan.ap_list = res_list; // Must be valid during execution - msg->data.user_scan.ap_list_size = count; - - // Put user_connect message in input queue or cache queue - switch(_state) { - case S_STARTED: - ok = _in_queue.put(msg); - MBED_ASSERT(ok == osOK); - break; - - case S_WAIT_START: - ok = _cache_queue.put(msg); - MBED_ASSERT(ok == osOK); - break; - - default: - MBED_ASSERT(false); - break; - } - - // To synchronize, wait until response message is available - osEvent evt = _out_queue.get(); - MBED_ASSERT(evt.status == osEventMessage); - - msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_SCAN_RSP); - - found_aps = msg->data.user_scan_rsp.found_aps; - - _msg_pool->free(msg); - - return found_aps; -} - -void OdinWiFiInterface::set_config(void *setting, cb_uint32 value) { - cbTARGET_ConfigParams param; - target_config_params_e configuration = *(target_config_params_e*)setting; - param = map_odin_config(configuration); - wlan_set_gParams(param, value); -} - -void OdinWiFiInterface::wlan_set_gParams(cbTARGET_ConfigParams setting, cb_uint32 value) { - cbMAIN_driverLock(); - cbTARGET_configure(cbTARGET_targetResolve(_target_id), setting, (void*)value); - cbMAIN_driverUnlock(); -} - -unsigned int OdinWiFiInterface::get_config(void *setting) { - cbTARGET_ConfigParams param; - target_config_params_e configuration = *(target_config_params_e*)setting; - param = map_odin_config(configuration); - return wlan_get_gParams(param); -} - -unsigned int OdinWiFiInterface::wlan_get_gParams(cbTARGET_ConfigParams setting) { - cb_uint32 value = 0xFF; - cbMAIN_driverLock(); - cbTARGET_configure(cbTARGET_targetResolve(_target_id), setting, (void*)&value); - cbMAIN_driverUnlock(); - return value; -} - -#ifdef DEVICE_WIFI_AP - -nsapi_error_t OdinWiFiInterface::set_ap_network(const char *ip_address, const char *netmask, const char *gateway) -{ - nsapi_error_t result = NSAPI_ERROR_PARAMETER; - - _mutex.lock(); - - if ((ip_address != NULL) && (netmask != NULL) && (gateway != NULL)) - { - strncpy(_ap.ip_address, ip_address, sizeof(_ap.ip_address)); - strncpy(_ap.netmask, netmask, sizeof(_ap.netmask)); - strncpy(_ap.gateway, gateway, sizeof(_ap.gateway)); - - _ap.use_dhcp = false; - - result = NSAPI_ERROR_OK; - } - else { - memset(_ap.ip_address, 0, sizeof(_ap.ip_address)); - memset(_ap.netmask, 0, sizeof(_ap.netmask)); - memset(_ap.gateway, 0, sizeof(_ap.gateway)); - - _ap.use_dhcp = true; - - result = NSAPI_ERROR_OK; - } - - _mutex.unlock(); - - return result; -} - - -nsapi_error_t OdinWiFiInterface::set_ap_credentials(const char *ssid, const char *pass, - nsapi_security_t security) -{ - _mutex.lock(); - - _ap.ssid = ssid; - _ap.passwd = pass; - _ap.security = security; - - _mutex.unlock(); - - return NSAPI_ERROR_OK; -} - -nsapi_error_t OdinWiFiInterface::set_ap_channel(uint8_t channel) -{ - _mutex.lock(); - _ap.channel = channel; - _mutex.unlock(); - - return NSAPI_ERROR_OK; -} - -int OdinWiFiInterface::get_ap_connection_count() -{ - int cnt; - - _mutex.lock(); - cnt = _ap.cnt_connected; - _mutex.unlock(); - - return cnt; -} - -int OdinWiFiInterface::get_ap_max_connection_count() -{ - return ODIN_MAX_AP_STATIONS; -} - -nsapi_error_t OdinWiFiInterface::set_ap_dhcp(bool dhcp) -{ - _mutex.lock(); - _ap.use_dhcp = dhcp; - _mutex.unlock(); - - return NSAPI_ERROR_OK; -} - -nsapi_error_t OdinWiFiInterface::ap_start(const char *ssid, const char *pass, - nsapi_security_t security, uint8_t channel) -{ - int error_code = NSAPI_ERROR_OK; - osStatus ok; - - // Allocate and initialize message - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_AP_START; - msg->data.user_ap_start.ssid = ssid; // Must be valid until task is completed - msg->data.user_ap_start.passwd = pass; // Must be valid until task is completed - msg->data.user_ap_start.security = security; - msg->data.user_ap_start.channel = channel; // Must be valid until task is completed - msg->data.user_ap_start.beacon_interval = _ap.beacon_interval; - - // Put message in input queue or cache queue - switch(_state) { - case S_STARTED: - ok = _in_queue.put(msg); - MBED_ASSERT(ok == osOK); - break; - - case S_WAIT_START: - ok = _cache_queue.put(msg); // handle once we are started - MBED_ASSERT(ok == osOK); - break; - - default: - MBED_ASSERT(false); - break; - } - - // To synchronize, wait until response message is available - osEvent evt = _out_queue.get(); - MBED_ASSERT(evt.status == osEventMessage); - - msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_AP_START); - - // Return the result of the call - error_code = msg->data.user_response.error; - - ok = _msg_pool->free(msg); - MBED_ASSERT(ok == osOK); - - return error_code; -} - -nsapi_error_t OdinWiFiInterface::ap_start() -{ - return ap_start(_ap.ssid, _ap.passwd, _ap.security, _ap.channel); -} - -nsapi_error_t OdinWiFiInterface::ap_stop() -{ - nsapi_error_t error_code = NSAPI_ERROR_OK; - - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_AP_STOP; - - // Put the user message in the input queue - osStatus ok = _in_queue.put(msg); - MBED_ASSERT(ok == osOK); - - // To synchronize, wait until response message is available - osEvent evt = _out_queue.get(); - MBED_ASSERT(evt.status == osEventMessage); - - msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_AP_STOP); - - // Return the result of the disconnect call - error_code = msg->data.user_response.error; - - _msg_pool->free(msg); - - return error_code; -} - -nsapi_error_t OdinWiFiInterface::set_ap_beacon_interval(uint16_t interval) -{ - _mutex.lock(); - _ap.beacon_interval = interval; - _mutex.unlock(); - - return NSAPI_ERROR_OK; -} - -#endif - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_connect_fail_wait_disconnect(void) -{ - cbRTSL_Status error_code; - - cbMAIN_driverLock(); - error_code = cbWLAN_disconnect(_wlan_status_connected_info.handle); - cbMAIN_driverUnlock(); - - MBED_ASSERT(error_code == cbSTATUS_OK); - - return S_STA_CONNECTION_FAIL_WAIT_DISCONNECT; -} - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_wait_connect() -{ - _timer.reset(); - _timer.start(); - - return S_STA_WAIT_CONNECT; -} - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_wait_disconnect() -{ - cbRTSL_Status error_code; - - cbMAIN_driverLock(); - error_code = cbWLAN_disconnect(_wlan_status_disconnected_info.handle); - cbMAIN_driverUnlock(); - - MBED_ASSERT(error_code == cbSTATUS_OK); - - return S_STA_WAIT_DISCONNECT; -} - - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_wait_start() -{ - return S_AP_WAIT_START; -} - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_started() -{ - _ap.cnt_connected = 0; - - return S_AP_STARTED; -} - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_wait_stop() -{ - cbMAIN_driverLock(); - cbRTSL_Status status = cbWLAN_apStop(_ap.handle); - cbMAIN_driverUnlock(); - - MBED_ASSERT(status == cbSTATUS_OK); - - return S_AP_WAIT_STOP; -} - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_fail_wait_stop() -{ - cbMAIN_driverLock(); - cbRTSL_Status status = cbWLAN_apStop(_ap.handle); - cbMAIN_driverUnlock(); - - MBED_ASSERT(status == cbSTATUS_OK); - - return S_AP_FAIL_WAIT_STOP; -} - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_wait_drv_stop() -{ - cbMAIN_driverLock(); - cbRTSL_Status status = cbWLAN_stop(); - cbMAIN_driverUnlock(); - MBED_ASSERT(status == cbSTATUS_OK); - - return S_AP_WAIT_DRV_STOP; -} - -OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_wait_drv_start() -{ - cbMAIN_WlanStartParams startParams; - - memset(&startParams, 0, sizeof(startParams)); - - startParams.txPowerSettings.lowTxPowerLevel = cbWLAN_TX_POWER_AUTO; - startParams.txPowerSettings.medTxPowerLevel = cbWLAN_TX_POWER_AUTO; - startParams.txPowerSettings.maxTxPowerLevel = cbWLAN_TX_POWER_AUTO; - - cbMAIN_driverLock(); - cb_int32 status = cbMAIN_startWlan(_target_id, &startParams); - cbMAIN_driverUnlock(); - MBED_ASSERT(status == cbSTATUS_OK); - - return S_AP_WAIT_DRV_START; -} - -void OdinWiFiInterface::handle_in_msg(void) -{ - while(true) { - - osEvent evt = _in_queue.get(1000); - - if(evt.status == osEventMessage) { - - struct odin_wifi_msg_s *msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - - _mutex.lock(); - - switch(msg->type) { - case ODIN_WIFI_MSG_USER_CONNECT: - handle_user_connect(&(msg->data.user_connect)); - break; - - case ODIN_WIFI_MSG_USER_DISCONNECT: - handle_user_disconnect(); - break; - - case ODIN_WIFI_MSG_USER_CONNECT_TIMEOUT: - handle_user_connect_timeout(); - break; - - case ODIN_WIFI_MSG_USER_STOP: - handle_user_stop(); - break; - - case ODIN_WIFI_MSG_USER_SCAN: - handle_user_scan(&(msg->data.user_scan)); - break; - - case ODIN_WIFI_MSG_USER_AP_START: - handle_user_ap_start(&(msg->data.user_ap_start)); - break; - - case ODIN_WIFI_MSG_USER_AP_STOP: - handle_user_ap_stop(); - break; - - case cbWLAN_STATUS_STOPPED: - handle_wlan_status_stopped(); - break; - - case cbWLAN_STATUS_STARTED: - handle_wlan_status_started(&(msg->data.wlan_status_started)); - break; - - case cbWLAN_STATUS_ERROR: - handle_wlan_status_error(); - break; - - case cbWLAN_STATUS_DISCONNECTED: - handle_wlan_status_disconnected(); - break; - - case cbWLAN_STATUS_CONNECTION_FAILURE: - handle_wlan_status_connection_failure(&(msg->data.wlan_status_connection_failure)); - break; - - case cbWLAN_STATUS_CONNECTING: - handle_wlan_status_connecting(); - break; - - case cbWLAN_STATUS_CONNECTED: - flush_drvr_ind_pkts = true; - handle_wlan_status_connected(&(msg->data.wlan_status_connected)); - flush_drvr_ind_pkts = false; - break; - - case cbWLAN_SCAN_INDICATION: - handle_wlan_scan_indication(); - break; - - case cbWLAN_STATUS_AP_UP: - handle_wlan_status_ap_up(); - break; - - case cbWLAN_STATUS_AP_DOWN: - handle_wlan_status_ap_down(); - break; - - case cbWLAN_STATUS_AP_STA_ADDED: - _ap.cnt_connected++; - if(_debug) {printf("cbWLAN_STATUS_AP_STA_ADDED: %d\r\n", _ap.cnt_connected);} - break; - - case cbWLAN_STATUS_AP_STA_REMOVED: - _ap.cnt_connected--; - if(_debug) {printf("cbWLAN_STATUS_AP_STA_REMOVED: %d\r\n", _ap.cnt_connected);} - break; - - default: - MBED_ASSERT(false); - break; - } - - _mutex.unlock(); - - if(msg != 0) { - _msg_pool->free(msg); - } - } - else if(evt.status == osEventTimeout) { - //Make sure the connect timeout is checked - handle_user_connect_timeout(); - } - else { - MBED_ASSERT(false); - } - } -} - -void OdinWiFiInterface::handle_cached_msg(void) -{ - osEvent evt = _cache_queue.get(0); - if(evt.status == osEventMessage) { - - struct odin_wifi_msg_s *msg = (odin_wifi_msg_s*)evt.value.p; - MBED_ASSERT(msg != 0); - - switch(msg->type) { - case ODIN_WIFI_MSG_USER_CONNECT: - handle_user_connect(&(msg->data.user_connect)); - break; - - case ODIN_WIFI_MSG_USER_SCAN: - handle_user_scan(&(msg->data.user_scan)); - break; - - case ODIN_WIFI_MSG_USER_STOP: - handle_user_stop(); - break; - - case ODIN_WIFI_MSG_USER_AP_START: - handle_user_ap_start(&(msg->data.user_ap_start)); - break; - - default: - MBED_ASSERT(false); - break; - } - - if(msg != 0) { - _msg_pool->free(msg); - } - } -} - -void OdinWiFiInterface::handle_user_connect(user_connect_s *user_connect) -{ - MBED_ASSERT(user_connect != 0); - - nsapi_error_t error_code = NSAPI_ERROR_DEVICE_ERROR; - - if((_state_sta == S_STA_IDLE) && (_state_ap == S_AP_IDLE)) { - // No STA or AP activity in progress - - error_code = wlan_set_channel(user_connect->channel); - - if (error_code == NSAPI_ERROR_OK) { - if((user_connect->security == NSAPI_SECURITY_PEAP) || (user_connect->security == NSAPI_SECURITY_EAP_TLS)) - error_code = wlan_connect(user_connect->ssid, user_connect->passwd, user_connect->security, user_connect->cert_handle, user_connect->user_name, user_connect->user_passwd, user_connect->channel); - else - error_code = wlan_connect(user_connect->ssid, user_connect->passwd, user_connect->security); - } - } - else { - // Parallel STA or AP activity is not supported - error_code = NSAPI_ERROR_UNSUPPORTED; - } - - if(error_code == NSAPI_ERROR_OK) { - _state_sta = entry_wait_connect(); - } - else - { - // Remain in S_STA_IDLE - // Release user connect call - - send_user_response_msg(ODIN_WIFI_MSG_USER_CONNECT, error_code); - } -} - -void OdinWiFiInterface::handle_user_disconnect(void) -{ - switch(_state_sta) { - case S_STA_CONNECTED: - case S_STA_DISCONNECTED_WAIT_CONNECT: - emac.set_wifi_emac_handle(_wlan_status_disconnected_info.handle); - _state_sta = entry_wait_disconnect(); - break; - - default: - send_user_response_msg(ODIN_WIFI_MSG_USER_DISCONNECT, NSAPI_ERROR_NO_CONNECTION); - break; - } -} - -void OdinWiFiInterface::handle_user_stop() -{ - MBED_ASSERT(_state == S_STARTED); - MBED_ASSERT(_state_sta == S_STA_IDLE); - MBED_ASSERT(_state_ap == S_AP_IDLE); - - _interface->bringdown(); - - cbMAIN_driverLock(); - cbRTSL_Status status = cbWLAN_stop(); - cbMAIN_driverUnlock(); - MBED_ASSERT(status == cbSTATUS_OK); - - _state = S_WAIT_STOP; - _state_sta = S_INVALID; - _state_ap = S_INVALID; -} - -void OdinWiFiInterface::handle_user_scan(user_scan_s *user_scan) -{ - MBED_ASSERT(_state == S_STARTED); - MBED_ASSERT(user_scan != 0); - - cbWLAN_ScanParameters params; - params.ssid.ssidLength = 0; //Broadcast scan - params.channel = cbWLAN_CHANNEL_ALL; - memset(&_scan_cache, 0, sizeof(scan_cache_s)); - - cbRTSL_Status status = cbSTATUS_ERROR; - for(int i = 0; (i < 10) && (status != cbSTATUS_OK); i++) { - if(i > 0) { - rtos::ThisThread::sleep_for(500); - } - - cbMAIN_driverLock(); - status = cbWLAN_scan(¶ms, wlan_callb_s::scan_indication_callback, this); - if(status == cbSTATUS_OK) { - _scan_active = true; - _scan_list = user_scan->ap_list; - _scan_list_size = user_scan->ap_list_size; - _scan_list_cnt = 0; - } - cbMAIN_driverUnlock(); - } - - if(status != cbSTATUS_OK) { - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_SCAN_RSP; - msg->data.user_scan_rsp.ap_list = 0; - msg->data.user_scan_rsp.found_aps = NSAPI_ERROR_DEVICE_ERROR; - - osStatus ok = _out_queue.put(msg); - MBED_ASSERT(ok == osOK); - } -} - -void OdinWiFiInterface::handle_user_connect_timeout() -{ - if((_state_sta == S_STA_WAIT_CONNECT) && (_sta.timeout_ms > 0)) { - int elapsed_time = _timer.read_ms(); - - if(elapsed_time > _sta.timeout_ms) { - if(_debug) { - printf("TIMEOUT: %d ms, ACTUAL %d ms\n\r", _sta.timeout_ms, elapsed_time); - } - _timer.stop(); - - emac.set_wifi_emac_handle(_wlan_status_connected_info.handle); - _state_sta = entry_connect_fail_wait_disconnect(); - } - } -} - -void OdinWiFiInterface::handle_user_ap_start(user_ap_start_s *user_ap_start) -{ - MBED_ASSERT(user_ap_start != 0); - - nsapi_error_t error_code = NSAPI_ERROR_OK; - - bool channel_ok = is_valid_AP_channel(user_ap_start->channel); - - if((_state_sta == S_STA_IDLE) && (_state_ap == S_AP_IDLE) && channel_ok) { - // No STA or AP activity in progress - - error_code = wlan_ap_start( - user_ap_start->ssid, - user_ap_start->passwd, - user_ap_start->security, - user_ap_start->channel, - user_ap_start->beacon_interval); - } - else { - // Parallel STA or AP activity is not supported - error_code = NSAPI_ERROR_UNSUPPORTED; - } - - if(error_code == NSAPI_ERROR_OK) { - _state_ap = entry_ap_wait_start(); - } - else - { - send_user_response_msg(ODIN_WIFI_MSG_USER_AP_START, error_code); - } -} - -void OdinWiFiInterface::handle_user_ap_stop() -{ - switch(_state_ap) { - case S_AP_STARTED: - _state_ap = entry_ap_wait_stop(); - break; - - default: - send_user_response_msg(ODIN_WIFI_MSG_USER_AP_STOP, NSAPI_ERROR_DEVICE_ERROR); - break; - } -} - -void OdinWiFiInterface::handle_wlan_status_started(wlan_status_started_s *start) -{ - if (_debug) { - printf("cbWLAN_STATUS_STARTED\n\r"); - } - - MBED_ASSERT(start != 0); - - switch(_state) { - case S_WAIT_START: - sprintf(_mac_addr_str, - "%02x:%02x:%02x:%02x:%02x:%02x", - start->info.macAddress[0], - start->info.macAddress[1], - start->info.macAddress[2], - start->info.macAddress[3], - start->info.macAddress[4], - start->info.macAddress[5]); - - if (!_interface) { - nsapi_error_t error_code = _stack.add_ethernet_interface(_emac, true, &_interface); - if (error_code != NSAPI_ERROR_OK) { - _interface = NULL; - } - else { - _interface->attach(_connection_status_cb); - } - } - - if (!_wlan_initialized) { - _wlan_initialized = true; - } - - // The OdinWifiInterface object is now fully initialized - _state = S_STARTED; - _state_sta = S_STA_IDLE; - _state_ap = S_AP_IDLE; - - handle_cached_msg(); - break; - - case S_STARTED: - switch(_state_ap) { - case S_AP_WAIT_DRV_START: - _state_ap = S_AP_IDLE; - - send_user_response_msg(ODIN_WIFI_MSG_USER_AP_STOP, NSAPI_ERROR_OK); - break; - - default: - MBED_ASSERT(false); - break; - } - break; - - default: - MBED_ASSERT(false); - break; - } - -} - -void OdinWiFiInterface::handle_wlan_status_stopped() -{ - if (_debug) { - printf("cbWLAN_STATUS_STOPPED\n\r"); - } - - cbRTSL_Status status; - - switch(_state) { - case S_WAIT_START: - // Ignore - break; - - case S_WAIT_STOP: - _state = S_INVALID; - - cbMAIN_driverLock(); - status = cbWLAN_deregisterStatusCallback(wlan_callb_s::status_indication_callback, this); - cbMAIN_driverUnlock(); - MBED_ASSERT(status == cbSTATUS_OK); - - send_user_response_msg(ODIN_WIFI_MSG_USER_STOP, NSAPI_ERROR_OK); - break; - - case S_STARTED: - switch(_state_ap) { - case S_AP_WAIT_DRV_STOP: - _state_ap = entry_ap_wait_drv_start(); - break; - - default: - MBED_ASSERT(false); - break; - } - break; - - default: - MBED_ASSERT(FALSE); - break; - } -} - -void OdinWiFiInterface::handle_wlan_status_error() -{ - if (_debug) { - printf("cbWLAN_STATUS_ERROR\n\r"); - } -} - -void OdinWiFiInterface::handle_wlan_status_connecting() -{ - if (_debug) { - printf("cbWLAN_STATUS_CONNECTING\n\r"); - } - - handle_user_connect_timeout(); -} - -void OdinWiFiInterface::handle_wlan_status_connected(wlan_status_connected_s *wlan_connect) -{ - nsapi_error_t error_code; - - MBED_ASSERT(wlan_connect != 0); - - switch(_state_sta) { - case S_STA_CONNECTED: - case S_STA_WAIT_CONNECT: - _timer.stop(); - - if(_debug) { - printf("MBED_IPSTACK_ \r\n"); - } - - error_code = _interface->bringup(_dhcp, - _ip_address[0] ? _ip_address : 0, - _netmask[0] ? _netmask : 0, - _gateway[0] ? _gateway : 0, - DEFAULT_STACK); - - memcpy(&_wlan_status_connected_info, &(wlan_connect->info), sizeof(cbWLAN_StatusConnectedInfo)); - emac.set_wifi_emac_handle(_wlan_status_connected_info.handle); - - if (error_code == NSAPI_ERROR_OK || error_code == NSAPI_ERROR_IS_CONNECTED) { - if(_state_sta != S_STA_CONNECTED){ - _state_sta = S_STA_CONNECTED; - send_user_response_msg(ODIN_WIFI_MSG_USER_CONNECT, NSAPI_ERROR_OK); - } - } - else { - _state_sta = entry_connect_fail_wait_disconnect(); - } - break; - - case S_STA_DISCONNECTED_WAIT_CONNECT: - _state_sta = S_STA_CONNECTED; - break; - - case S_STA_CONNECTION_FAIL_WAIT_DISCONNECT: - case S_STA_WAIT_DISCONNECT: - //Ignore - break; - - default: - MBED_ASSERT(FALSE); - break; - } -} - -void OdinWiFiInterface::handle_wlan_status_connection_failure(wlan_status_connection_failure_s *connect_failure) -{ - MBED_ASSERT(connect_failure != 0); - - if(_debug) { - printf("WLAN STATUS CONNECTION FAILURE\r\n"); - } - - memcpy(&_wlan_status_disconnected_info, &(connect_failure->info), sizeof(cbWLAN_StatusDisconnectedInfo)); - emac.set_wifi_emac_handle(_wlan_status_disconnected_info.handle); - - switch(_state_sta) { - case S_STA_WAIT_CONNECT: - //Ignore - wait until timeout or connection success - handle_user_connect_timeout(); - break; - - case S_STA_CONNECTION_FAIL_WAIT_DISCONNECT: - //Ignore - break; - - case S_STA_CONNECTED: - _state_sta = S_STA_DISCONNECTED_WAIT_CONNECT; - break; - - case S_STA_DISCONNECTED_WAIT_CONNECT: - //Ignore - break; - - case S_STA_WAIT_DISCONNECT: - //Ignore - break; - - default: - if(_debug) printf("ASSERT: S %d\r\n", _state_sta); - MBED_ASSERT(FALSE); - break; - } -} - -void OdinWiFiInterface::handle_wlan_status_disconnected(void) -{ - nsapi_error_t error_code = NSAPI_ERROR_OK; - - if(_debug) { - printf("WLAN STATUS DISCONNECTED\r\n"); - } - - switch(_state_sta) { - case S_STA_WAIT_CONNECT: - handle_user_connect_timeout(); - break; - - case S_STA_CONNECTED: - _state_sta = S_STA_DISCONNECTED_WAIT_CONNECT; - break; - - case S_STA_DISCONNECTED_WAIT_CONNECT: - //Ignore - break; - - case S_STA_CONNECTION_FAIL_WAIT_DISCONNECT: - _state_sta = S_STA_IDLE; - switch(_wlan_status_disconnected_info.reason) { - case cbWLAN_STATUS_DISCONNECTED_AUTH_FAILURE: - case cbWLAN_STATUS_DISCONNECTED_ASSOC_FAILURE: - case cbWLAN_STATUS_DISCONNECTED_MIC_FAILURE: - error_code = NSAPI_ERROR_AUTH_FAILURE; - break; - case cbWLAN_STATUS_DISCONNECTED_NO_BSSID_FOUND: - case cbWLAN_STATUS_DISCONNECTED_UNKNOWN: - error_code = NSAPI_ERROR_NO_CONNECTION; - break; - default: - error_code = NSAPI_ERROR_DEVICE_ERROR; - break; - } - send_user_response_msg(ODIN_WIFI_MSG_USER_CONNECT, error_code); - break; - - case S_STA_WAIT_DISCONNECT: - if(_debug) { - printf("MBED_IPSTACK_BRINGDOWN\r\n"); - } - _interface->bringdown(); - - _state_sta = S_STA_IDLE; - - send_user_response_msg(ODIN_WIFI_MSG_USER_DISCONNECT, NSAPI_ERROR_OK); - break; - - default: - MBED_ASSERT(FALSE); - break; - } -} - -void OdinWiFiInterface::handle_wlan_scan_indication() -{ - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = ODIN_WIFI_MSG_USER_SCAN_RSP; - msg->data.user_scan_rsp.ap_list = _scan_list; - msg->data.user_scan_rsp.found_aps = _scan_list_cnt; - - _scan_active = false; - _scan_list = 0; - _scan_list_size = 0; - _scan_list_cnt = 0; - memset(&_scan_cache, 0, sizeof(scan_cache_s)); - - if(_debug) printf("SCAN END\r\n"); - - osStatus ok = _out_queue.put(msg); - MBED_ASSERT(ok == osOK); -} - -void OdinWiFiInterface::handle_wlan_status_ap_up() -{ - nsapi_error_t error_code; - - if (_debug) { - printf("cbWLAN_STATUS_AP_UP\n\r"); - } - - switch(_state_ap) { - case S_AP_WAIT_START: - - if(_debug) { - printf("MBED_IPSTACK_BRINGUP\r\n"); - } - - error_code = _interface->bringup(_ap.use_dhcp, - _ap.ip_address[0] ? _ap.ip_address : 0, - _ap.netmask[0] ? _ap.netmask : 0, - _ap.gateway[0] ? _ap.gateway : 0, - DEFAULT_STACK); - - if(error_code == NSAPI_ERROR_OK) { - _state_ap = S_AP_STARTED; - - send_user_response_msg(ODIN_WIFI_MSG_USER_AP_START, NSAPI_ERROR_OK); - } - else { - _ap.error_code = error_code; - - _state_ap = entry_ap_fail_wait_stop(); - } - break; - - default: - MBED_ASSERT(FALSE); - break; - } -} - -void OdinWiFiInterface::handle_wlan_status_ap_down() -{ - if (_debug) { - printf("cbWLAN_STATUS_AP_DOWN\n\r"); - } - - if(_debug) { - printf("MBED_IPSTACK_BRINGDOWN\r\n"); - } - - switch(_state_ap) { - case S_AP_WAIT_STOP: - _interface->bringdown(); - - _state_ap = entry_ap_wait_drv_stop(); - break; - - case S_AP_FAIL_WAIT_STOP: - _state_ap = S_AP_IDLE; - - send_user_response_msg(ODIN_WIFI_MSG_USER_AP_START, _ap.error_code); - break; - - default: - MBED_ASSERT(false); - break; - } -} - -void OdinWiFiInterface::init(bool debug = false) -{ - _mutex.lock(); - - // Initialise internal variables - _state = S_NOT_INITIALISED; - _state_sta = S_INVALID; - _state_ap = S_INVALID; - - memset(&_sta, 0, sizeof(sta_s)); - _sta.security = NSAPI_SECURITY_WPA_WPA2; - set_dhcp(true); - _sta.timeout_ms = ODIN_WIFI_STA_DEFAULT_CONN_TMO; - - memset(&_ap, 0, sizeof(ap_s)); - _sta.security = NSAPI_SECURITY_WPA_WPA2; - _ap.use_dhcp = true; - _ap.beacon_interval = 100; - - _scan_active = false; - _scan_list = 0; - _scan_list_size = 0; - _scan_list_cnt = 0; - memset(&_scan_cache, 0, sizeof(scan_cache_s)); - - _debug = debug; - _dbg_timeout = 0; - - memset(_mac_addr_str, 0, ODIN_WIFI_MAX_MAC_ADDR_STR); - memset(&_wlan_status_connected_info, 0, sizeof(cbWLAN_StatusConnectedInfo)); - memset(&_wlan_status_disconnected_info, 0, sizeof(cbWLAN_StatusDisconnectedInfo)); - _wlan_status_connected_info.handle = cbWLAN_DEFAULT_HANDLE; - _wlan_status_disconnected_info.handle = cbWLAN_DEFAULT_HANDLE; - _ap.handle = cbWLAN_DEFAULT_HANDLE; - - _msg_pool = new MemoryPool(); - - if(!_wlan_initialized) { - - _target_id = cbMAIN_initWlan(); - MBED_ASSERT(_target_id != cbMAIN_TARGET_INVALID_ID); - } - cbMAIN_driverLock(); - cbMAIN_WlanStartParams startParams; - - memset(&startParams, 0, sizeof(startParams)); - - startParams.txPowerSettings.lowTxPowerLevel = cbWLAN_TX_POWER_AUTO; - startParams.txPowerSettings.medTxPowerLevel = cbWLAN_TX_POWER_AUTO; - startParams.txPowerSettings.maxTxPowerLevel = cbWLAN_TX_POWER_AUTO; - - cb_int32 status = cbMAIN_startWlan(_target_id, &startParams); - MBED_ASSERT(status == cbSTATUS_OK); - - cbRTSL_Status reg_status = cbWLAN_registerStatusCallback(wlan_callb_s::status_indication_callback, this); - MBED_ASSERT(reg_status == cbSTATUS_OK); - - if(!_wlan_initialized) { - cbMAIN_startOS(); - } - cbMAIN_driverUnlock(); - - _state = S_WAIT_START; - - _thread.start(callback(wlan_callb_s::odin_thread_fcn, this)); - - _mutex.unlock(); -} - -void OdinWiFiInterface::send_user_response_msg(unsigned int type, nsapi_error_t error_code) -{ - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = type; - msg->data.user_response.error = error_code; - - osStatus ok = _out_queue.put(msg, 0); - MBED_ASSERT(ok == osOK); -} - -nsapi_error_t OdinWiFiInterface::wlan_set_channel(uint8_t channel) -{ - nsapi_error_t error_code = NSAPI_ERROR_OK; - cbRTSL_Status status = cbSTATUS_OK; - - if (channel != 0) - { - cbWLAN_ChannelList channel_list; - - channel_list.length = 1; - channel_list.channels[0] = channel; - - cbMAIN_driverLock(); - status = cbWLAN_setChannelList(&channel_list); - cbMAIN_driverUnlock(); - } - else - { - cbMAIN_driverLock(); - status = cbWLAN_setChannelList(NULL); - cbMAIN_driverUnlock(); - } - - if(status != cbSTATUS_OK) { - error_code = NSAPI_ERROR_UNSUPPORTED; - } - - return error_code; -} - -nsapi_error_t OdinWiFiInterface::wlan_connect( - const char *ssid, - const char *passwd, - nsapi_security_t security, - auth_cert_s *cert_handle, - const char *username, - const char *user_pswd, - uint8_t channel) -{ - nsapi_error_t error_code = NSAPI_ERROR_OK; - cbRTSL_Status status = cbSTATUS_OK; - cbWLAN_CommonConnectParameters connect_params; - cbWLAN_EnterpriseConnectParameters enterpriseParams; - static cbWLAN_Handle handle = cbWLAN_DEFAULT_HANDLE; - - memset(&enterpriseParams, 0, sizeof(cbWLAN_EnterpriseConnectParameters)); - memset(&connect_params, 0, sizeof(cbWLAN_CommonConnectParameters)); - - strncpy((char*)connect_params.ssid.ssid, ssid, cbWLAN_SSID_MAX_LENGTH); - connect_params.ssid.ssidLength = strlen((const char*)connect_params.ssid.ssid); - - switch (security) - { - case NSAPI_SECURITY_NONE: - cbMAIN_driverLock(); - handle = cbWLAN_connectOpen(&connect_params); - cbMAIN_driverUnlock(); - break; - case NSAPI_SECURITY_WPA: - case NSAPI_SECURITY_WPA2: - case NSAPI_SECURITY_WPA_WPA2: - char temp_passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH]; - cbWLAN_WPAPSKConnectParameters wpa_connect_params; - - memset(temp_passphrase, 0, cbWLAN_MAX_PASSPHRASE_LENGTH); - strncpy(temp_passphrase, passwd, cbWLAN_MAX_PASSPHRASE_LENGTH); - - cbMAIN_driverLock(); - status = cbWLAN_Util_PSKFromPWD(temp_passphrase, connect_params.ssid, wpa_connect_params.psk.key); - - if (status == cbSTATUS_OK) { - handle = cbWLAN_connectWPAPSK(&connect_params, &wpa_connect_params); - } - cbMAIN_driverUnlock(); - if(_debug) {printf("cbWLAN_connect: %d\r\n", handle);} - break; - - case NSAPI_SECURITY_EAP_TLS: - cbMAIN_driverLock(); - enterpriseParams.authMode = cbWLAN_ENTERPRISE_MODE_EAPTLS; - if((cert_handle->client_cert == NULL) && _debug) - { - printf("No client certificate found in root \r\n"); - } - handle = cb_eap_conn_handler(cert_handle->client_cert, cert_handle->client_prvt_key, &connect_params, &enterpriseParams); - cbMAIN_driverUnlock(); - if(_debug) {printf("cbWLAN_connect: %d\r\n", status);} - break; - - case NSAPI_SECURITY_PEAP: - cbMAIN_driverLock(); - enterpriseParams.authMode = cbWLAN_ENTERPRISE_MODE_PEAP; - strncpy((char*)enterpriseParams.username, username, cbWLAN_MAX_USERNAME_LENGTH); - strncpy((char*)enterpriseParams.passphrase, user_pswd, cbWLAN_MAX_USERNAME_LENGTH); - - /* cert_handle->ca_cert could be NULL if client don;t need to verify server */ - handle = cb_eap_conn_handler(cert_handle->ca_cert, NULL, &connect_params, &enterpriseParams); - cbMAIN_driverUnlock(); - if(_debug) {printf("cbWLAN_connect: %d\r\n", status);} - break; - - case NSAPI_SECURITY_WEP: - - default: - status = cbSTATUS_ERROR; - break; - } - - if(status != cbSTATUS_OK || handle == cbWLAN_INVALID_HANDLE) { - error_code = NSAPI_ERROR_UNSUPPORTED; - } - - return error_code; -} - -nsapi_error_t OdinWiFiInterface::wlan_ap_start( - const char *ssid, - const char *pass, - nsapi_security_t security, - uint8_t channel, - uint16_t beacon_interval) -{ - cbRTSL_Status status = cbSTATUS_ERROR; - nsapi_error_t error_code = NSAPI_ERROR_OK; - - cbWLAN_CommonApParameters params; - cbWLAN_WPAPSKApParameters wpa_params; - - static cbWLAN_Handle handle = cbWLAN_DEFAULT_HANDLE; - - char temp_passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH]; - - memset(¶ms, 0, sizeof(cbWLAN_CommonApParameters)); - memset(&wpa_params, 0, sizeof(cbWLAN_WPAPSKApParameters)); - memset(temp_passphrase, 0, cbWLAN_MAX_PASSPHRASE_LENGTH); - - params.ssid.ssidLength = strlen(ssid); - memcpy(params.ssid.ssid, ssid, params.ssid.ssidLength); - params.channel = channel; - params.basicRates = cbRATE_MASK_01 | APP_MASK_SHIFTUP(cbRATE_MASK_01, cbRATE_MASK_G); - params.allowedRates = ODIN_WIFI_AP_ALLOWED_RATE_MASK; - cbMAIN_driverLock(); - status = cbWLAN_ioctl(cbWLAN_IOCTL_SET_AP_BEACON_INTERVAL, (void*)&beacon_interval); - cbMAIN_driverUnlock(); - - if (status != cbSTATUS_OK) { - error_code = NSAPI_ERROR_PARAMETER; - } else { - switch (security) { - case NSAPI_SECURITY_NONE: - cbMAIN_driverLock(); - handle = cbWLAN_apStartOpen(¶ms); - cbMAIN_driverUnlock(); - break; - - case NSAPI_SECURITY_WEP: - status = cbSTATUS_ERROR; - break; - - case NSAPI_SECURITY_WPA: - case NSAPI_SECURITY_WPA2: - case NSAPI_SECURITY_WPA_WPA2: - set_wpa_rsn_cipher(security, wpa_params.wpaCiphers, wpa_params.rsnCiphers); - - memcpy(temp_passphrase, pass, strlen(pass)); - - cbMAIN_driverLock(); - status = cbWLAN_Util_PSKFromPWD(temp_passphrase, params.ssid, wpa_params.psk.key); - - if (status == cbSTATUS_OK) { - handle = cbWLAN_apStartWPAPSK(¶ms, &wpa_params); - } - cbMAIN_driverUnlock(); - break; - - default: - status = cbSTATUS_ERROR; - break; - } - - if (status != cbSTATUS_OK || handle == cbWLAN_INVALID_HANDLE) { - error_code = NSAPI_ERROR_UNSUPPORTED; - } - } - _ap.handle = handle; - return error_code; -} - -void OdinWiFiInterface::wlan_scan_indication(cbWLAN_ScanIndicationInfo *scan_info, cb_boolean is_last_result) -{ - //If ongoing scan - if(_scan_active) { - - //To save msg buffers only send last result as a message to _in_queue - //Results before final one is stored - - if(is_last_result == TRUE) { - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = cbWLAN_SCAN_INDICATION; - - osStatus ok = _in_queue.put(msg); - MBED_ASSERT(ok == osOK); - } - else { - _mutex.lock(); - - // Add scan result to scan_list - update_scan_list(scan_info); - - _mutex.unlock(); - } - } - else { - if(_debug) printf("UNEXPECTED SCAN IND\r\n"); - } -} - -void OdinWiFiInterface::wlan_status_indication(cbWLAN_StatusIndicationInfo status, void *data) -{ - if (!flush_drvr_ind_pkts) { - struct odin_wifi_msg_s* msg = _msg_pool->alloc(); - MBED_ASSERT(msg != NULL); - - msg->type = status; - memcpy(&(msg->data), data, sizeof(odin_wifi_msg_s::data_t)); - - osStatus ok = _in_queue.put(msg, 0); - MBED_ASSERT(ok == osOK); - } -} - -static nsapi_security_t convertToNSAPI_security(cbWLAN_AuthenticationSuite authSuit) -{ - nsapi_security_t result = NSAPI_SECURITY_UNKNOWN; - - if (authSuit == cbWLAN_AUTHENTICATION_SUITE_NONE) - result = NSAPI_SECURITY_NONE; - else if (authSuit & cbWLAN_AUTHENTICATION_SUITE_SHARED_SECRET) - result = NSAPI_SECURITY_WEP; - else if ((authSuit & cbWLAN_AUTHENTICATION_SUITE_USE_WPA2) && (authSuit & cbWLAN_AUTHENTICATION_SUITE_USE_WPA)) - result = NSAPI_SECURITY_WPA_WPA2; - else if (authSuit & cbWLAN_AUTHENTICATION_SUITE_USE_WPA) - result = NSAPI_SECURITY_WPA; - else if (authSuit & cbWLAN_AUTHENTICATION_SUITE_USE_WPA2) - result = NSAPI_SECURITY_WPA2; - - return result; -} - -static void set_wpa_rsn_cipher( - nsapi_security_t security, - cbWLAN_CipherSuite &wpa_ciphers, - cbWLAN_CipherSuite &rsn_ciphers) -{ - wpa_ciphers = cbWLAN_CIPHER_SUITE_NONE; - rsn_ciphers = cbWLAN_CIPHER_SUITE_NONE; - - switch(security) { - case NSAPI_SECURITY_WPA: - wpa_ciphers = cbWLAN_CIPHER_SUITE_TKIP; - break; - - case NSAPI_SECURITY_WPA2: - rsn_ciphers = cbWLAN_CIPHER_SUITE_AES_CCMP; - break; - - case NSAPI_SECURITY_WPA_WPA2: - wpa_ciphers = (cbWLAN_CipherSuite)(cbWLAN_CIPHER_SUITE_TKIP | cbWLAN_CIPHER_SUITE_AES_CCMP); - rsn_ciphers = (cbWLAN_CipherSuite)(cbWLAN_CIPHER_SUITE_TKIP | cbWLAN_CIPHER_SUITE_AES_CCMP); - break; - - default: - MBED_ASSERT(false); - break; - } -} - -void OdinWiFiInterface::update_scan_list(cbWLAN_ScanIndicationInfo *scan_info) -{ - MBED_ASSERT(scan_info != 0); - - bool found; - - if(_scan_list != 0) { - //User included AP list in scan call - MBED_ASSERT(_scan_list_size > 0); - MBED_ASSERT(_scan_list_cnt <= _scan_list_size); - - // If there is room for yet another found AP - if(_scan_list_cnt < _scan_list_size) { - found = false; - - // Make sure it is not already previously found - for(nsapi_size_t i = 0; (i < _scan_list_cnt) && (!found); i++) { - if(memcmp(scan_info->bssid, _scan_list[i].get_bssid(), sizeof(cbWLAN_MACAddress)) == 0) { - found = true; - } - } - - // If new AP, add it - if(!found) { - nsapi_wifi_ap_t ap; - - memset(&ap, 0, sizeof(nsapi_wifi_ap_t)); - memcpy(ap.bssid, scan_info->bssid, sizeof(ap.bssid)); - strncpy((char*)ap.ssid, (char*)scan_info->ssid.ssid, scan_info->ssid.ssidLength); - ap.ssid[scan_info->ssid.ssidLength] = 0; - ap.security = convertToNSAPI_security(scan_info->authenticationSuites); - ap.rssi = (int8_t)(scan_info->rssi); - ap.channel = scan_info->channel; - - WiFiAccessPoint wap(ap); - - _scan_list[_scan_list_cnt] = wap; - _scan_list_cnt++; - } - } - } - else - { - //User did not include AP list in scan call. Instead use cache and report found number only - MBED_ASSERT(_scan_cache.count <= ODIN_WIFI_SCAN_CACHE_SIZE); - - //New channel => clear cache - if(_scan_cache.last_channel != scan_info->channel) { - memset(&_scan_cache, 0, sizeof(scan_cache_s)); - _scan_cache.last_channel = scan_info->channel; - } - - //Check if already found - found = false; - if(_scan_cache.count > 0) { - for(int i = 0; (i < _scan_cache.count) && (!found); i++) { - if(memcmp(_scan_cache.bssid[i], scan_info->bssid, sizeof(cbWLAN_MACAddress)) == 0) { - found = true; - } - } - } - - //If new AP - if(!found) { - //Add to cache (if space) - if(_scan_cache.count < ODIN_WIFI_SCAN_CACHE_SIZE) { - memcpy(_scan_cache.bssid[_scan_cache.count], scan_info->bssid, sizeof(cbWLAN_MACAddress)); - _scan_cache.count++; - } - - _scan_list_cnt++; - } - } -} - -static void generateWEPKeys(const char *passphrase, cbWLAN_WEPKey keys[4]) -{ - unsigned char pseed[4] = { 0 }; - unsigned int randNumber, tmp, i, j; - - for (i = 0; i < strlen(passphrase); i++) - { - pseed[i % 4] ^= (unsigned char)passphrase[i]; - } - - randNumber = pseed[0] | (pseed[1] << 8) | (pseed[2] << 16) | (pseed[3] << 24); - - for (i = 0; i < 4; i++) - { - for (j = 0; j < 5; j++) - { - randNumber = (randNumber * 0x343fd + 0x269ec3) & 0xffffffff; - tmp = (randNumber >> 16) & 0xff; - keys[i].key[j] = (unsigned char)tmp; - } - keys[i].length = 5; - } -} - -static bool is_valid_AP_channel(cbWLAN_Channel channel) -{ - bool ok = false; - - switch (channel) { - case cbWLAN_CHANNEL_01: - case cbWLAN_CHANNEL_02: - case cbWLAN_CHANNEL_03: - case cbWLAN_CHANNEL_04: - case cbWLAN_CHANNEL_05: - case cbWLAN_CHANNEL_06: - case cbWLAN_CHANNEL_07: - case cbWLAN_CHANNEL_08: - case cbWLAN_CHANNEL_09: - case cbWLAN_CHANNEL_10: - case cbWLAN_CHANNEL_11: -/* -// TODO: DO NOT ENABLE UNTIL GUARANTEED EUROPEAN MODULE (or this is blocked in wlan driver..) - case cbWLAN_CHANNEL_12: - case cbWLAN_CHANNEL_13: -*/ - case cbWLAN_CHANNEL_36: - case cbWLAN_CHANNEL_40: - case cbWLAN_CHANNEL_44: - case cbWLAN_CHANNEL_48: - ok = true; - break; - - default: - ok = false; - break; - } - - return ok; -} - -static cbTARGET_ConfigParams map_odin_config(target_config_params_e parameter) -{ - cbTARGET_ConfigParams config; - - switch (parameter) { - case ODIN_CFG_SET_POWER_SAVE_MODE: config = cbTARGET_CFG_SET_POWER_SAVE_MODE; - case ODIN_CFG_GET_POWER_SAVE_MODE: config = cbTARGET_CFG_GET_POWER_SAVE_MODE; - case ODIN_CFG_SET_LISTEN_INTERVAL: config = cbTARGET_CFG_SET_LISTEN_INTERVAL; - case ODIN_CFG_GET_LISTEN_INTERVAL: config = cbTARGET_CFG_GET_LISTEN_INTERVAL; - case ODIN_CFG_SET_MIN_SCAN_TIME: config = cbTARGET_CFG_SET_MIN_SCAN_TIME; - case ODIN_CFG_GET_MIN_SCAN_TIME: config = cbTARGET_CFG_GET_MIN_SCAN_TIME; - case ODIN_CFG_SET_MAX_SCAN_TIME: config = cbTARGET_CFG_SET_MAX_SCAN_TIME; - case ODIN_CFG_GET_MAX_SCAN_TIME: config = cbTARGET_CFG_GET_MAX_SCAN_TIME; - case ODIN_CFG_SET_SCAN_TYPE: config = cbTARGET_CFG_SET_SCAN_TYPE; - case ODIN_CFG_GET_SCAN_TYPE: config = cbTARGET_CFG_GET_SCAN_TYPE; - case ODIN_CFG_SET_DTIM_ENABLE: config = cbTARGET_CFG_SET_DTIM_ENABLE; - case ODIN_CFG_GET_DTIM_ENABLE: config = cbTARGET_CFG_GET_DTIM_ENABLE; - case ODIN_CFG_SET_QOS_ENABLE: config = cbTARGET_CFG_SET_QOS_ENABLE; - case ODIN_CFG_GET_QOS_ENABLE: config = cbTARGET_CFG_GET_QOS_ENABLE; - case ODIN_CFG_SET_RTS_THRESHOLD: config = cbTARGET_CFG_SET_RTS_THRESHOLD; - case ODIN_CFG_GET_RTS_THRESHOLD: config = cbTARGET_CFG_GET_RTS_THRESHOLD; - case ODIN_CFG_SET_TX_POWER: config = cbTARGET_CFG_SET_TX_POWER; - case ODIN_CFG_GET_TX_POWER: config = cbTARGET_CFG_GET_TX_POWER; - case ODIN_CFG_SET_MAX_PASSIVE_SCAN_TIME: config = cbTARGET_CFG_SET_MAX_PASSIVE_SCAN_TIME; - case ODIN_CFG_GET_MAX_PASSIVE_SCAN_TIME: config = cbTARGET_CFG_GET_MAX_PASSIVE_SCAN_TIME; - case ODIN_CFG_SET_SCAN_LISTEN_INTERVAL: config = cbTARGET_CFG_SET_SCAN_LISTEN_INTERVAL; - case ODIN_CFG_GET_SCAN_LISTEN_INTERVAL: config = cbTARGET_CFG_GET_SCAN_LISTEN_INTERVAL; - case ODIN_CFG_SET_DOT11_SHORT_RETRY_LIMIT: config = cbTARGET_CFG_SET_DOT11_SHORT_RETRY_LIMIT; - case ODIN_CFG_GET_DOT11_SHORT_RETRY_LIMIT: config = cbTARGET_CFG_GET_DOT11_SHORT_RETRY_LIMIT; - case ODIN_CFG_SET_DOT11_LONG_RETRY_LIMIT: config = cbTARGET_CFG_SET_DOT11_LONG_RETRY_LIMIT; - case ODIN_CFG_GET_DOT11_LONG_RETRY_LIMIT: config = cbTARGET_CFG_GET_DOT11_LONG_RETRY_LIMIT; - case ODIN_CFG_SET_AP_DOT11_SHORT_RETRY_LIMIT: config = cbTARGET_CFG_SET_AP_DOT11_SHORT_RETRY_LIMIT; - case ODIN_CFG_GET_AP_DOT11_SHORT_RETRY_LIMIT: config = cbTARGET_CFG_GET_AP_DOT11_SHORT_RETRY_LIMIT; - case ODIN_CFG_SET_AP_DOT11_LONG_RETRY_LIMIT: config = cbTARGET_CFG_SET_AP_DOT11_LONG_RETRY_LIMIT; - case ODIN_CFG_GET_AP_DOT11_LONG_RETRY_LIMIT: config = cbTARGET_CFG_GET_AP_DOT11_LONG_RETRY_LIMIT; - case ODIN_CFG_SET_REMAIN_ON_CHANNEL: config = cbTARGET_CFG_SET_REMAIN_ON_CHANNEL; - case ODIN_CFG_GET_REMAIN_ON_CHANNEL: config = cbTARGET_CFG_GET_REMAIN_ON_CHANNEL; - case ODIN_CFG_SET_STA_TX_RATE_MASK: config = cbTARGET_CFG_SET_STA_TX_RATE_MASK; - case ODIN_CFG_GET_STA_TX_RATE_MASK: config = cbTARGET_CFG_GET_STA_TX_RATE_MASK; - case ODIN_CFG_SET_RSSI_GOOD: config = cbTARGET_CFG_SET_RSSI_GOOD; - case ODIN_CFG_GET_RSSI_GOOD: config = cbTARGET_CFG_GET_RSSI_GOOD; - case ODIN_CFG_SET_RSSI_BAD: config = cbTARGET_CFG_SET_RSSI_BAD; - case ODIN_CFG_GET_RSSI_BAD: config = cbTARGET_CFG_GET_RSSI_BAD; - case ODIN_CFG_SET_SLEEP_TIMEOUT: config = cbTARGET_CFG_SET_SLEEP_TIMEOUT; - case ODIN_CFG_GET_SLEEP_TIMEOUT: config = cbTARGET_CFG_GET_SLEEP_TIMEOUT; - case ODIN_CFG_SET_GOOD_RSSI_YIELD_TMO: config = cbTARGET_CFG_SET_GOOD_RSSI_YIELD_TMO; - case ODIN_CFG_GET_GOOD_RSSI_YIELD_TMO: config = cbTARGET_CFG_GET_GOOD_RSSI_YIELD_TMO; - case ODIN_CFG_SET_BAD_RSSI_YIELD_TMO: config = cbTARGET_CFG_SET_BAD_RSSI_YIELD_TMO; - case ODIN_CFG_GET_BAD_RSSI_YIELD_TMO: config = cbTARGET_CFG_GET_BAD_RSSI_YIELD_TMO; - case ODIN_CFG_SET_FORCE_WORLD_MODE: config = cbTARGET_CFG_SET_FORCE_WORLD_MODE; - case ODIN_CFG_GET_FORCE_WORLD_MODE: config = cbTARGET_CFG_GET_FORCE_WORLD_MODE; - case ODIN_CFG_GET_TX_PACKET_ACK_TIMEOUT_WD: config = cbTARGET_CFG_SET_TX_PACKET_ACK_TIMEOUT_WD; - case ODIN_CFG_SET_TX_PACKET_ACK_TIMEOUT_WD: config = cbTARGET_CFG_GET_TX_PACKET_ACK_TIMEOUT_WD; - case ODIN_CFG_SET_CTS_PROTECTION: config = cbTARGET_CFG_SET_CTS_PROTECTION; - case ODIN_CFG_GET_CTS_PROTECTION: config = cbTARGET_CFG_GET_CTS_PROTECTION; - case ODIN_CFG_SET_HIDDEN_SSID: config = cbTARGET_CFG_SET_HIDDEN_SSID; - case ODIN_CFG_GET_HIDDEN_SSID: config = cbTARGET_CFG_GET_HIDDEN_SSID; - case ODIN_CFG_SET_AP_STA_INACTIVITY_TIMEOUT: config = cbTARGET_CFG_SET_AP_STA_INACTIVITY_TIMEOUT; - case ODIN_CFG_GET_AP_STA_INACTIVITY_TIMEOUT: config = cbTARGET_CFG_GET_AP_STA_INACTIVITY_TIMEOUT; - case ODIN_CFG_SET_ROAMING_AREA_HYSTERESIS: config = cbTARGET_CFG_SET_ROAMING_AREA_HYSTERESIS; - case ODIN_CFG_GET_ROAMING_AREA_HYSTERESIS: config = cbTARGET_CFG_GET_ROAMING_AREA_HYSTERESIS; - case ODIN_CFG_SET_PMF_STA: config = cbTARGET_CFG_SET_PMF_STA; - case ODIN_CFG_GET_PMF_STA: config = cbTARGET_CFG_GET_PMF_STA; - case ODIN_CFG_SET_FT_MODE: config = cbTARGET_CFG_SET_FT_MODE; - case ODIN_CFG_GET_FT_MODE: config = cbTARGET_CFG_GET_FT_MODE; - default: - MBED_ASSERT(false); - } - return config; -} - -static cbTARGET_PowerSaveMode convertPowerSaveAtToIoctl(target_power_save_mode_e powerSaveMode) -{ - cbTARGET_PowerSaveMode mode; - - switch (powerSaveMode) { - case ODIN_POWER_SAVE_MODE_OFF: mode = cbTARGET_POWER_SAVE_MODE_OFF; - case ODIN_POWER_SAVE_MODE_SLEEP: mode = cbTARGET_POWER_SAVE_MODE_SLEEP; - case ODIN_POWER_SAVE_MODE_DEEP_SLEEP: mode = cbTARGET_POWER_SAVE_MODE_DEEP_SLEEP; - default: - MBED_ASSERT(false); - } - - return mode; -} - -#endif // MBED_CONF_LWIP_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h deleted file mode 100644 index f747134fdde..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h +++ /dev/null @@ -1,455 +0,0 @@ -/* ODIN-W2 implementation of WiFiInterface - * Copyright (c) 2016 u-blox Malm� AB - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ODIN_WIFI_INTERFACE_H -#define ODIN_WIFI_INTERFACE_H - -#if MBED_CONF_LWIP_PRESENT - -#include "WiFiInterface.h" -#if DEVICE_WIFI_AP -#include "UbloxWiFiSoftAPInterface.h" -#endif - -#include "UbloxWiFiConfigInterface.h" -#include "mbed.h" -#include "netsocket/WiFiAccessPoint.h" -#include "netsocket/EMACInterface.h" -#include "nsapi_types.h" -#include "lwip/netif.h" -#include "rtos.h" -#include "cb_wlan.h" -#include "odin_drv_conf.h" -#include "wifi_emac.h" - -#define ODIN_WIFI_MAX_MAC_ADDR_STR (18) -#define ODIN_WIFI_SCAN_CACHE_SIZE (5) - -struct odin_wifi_msg_s; -struct user_connect_s; -struct user_scan_s; -struct user_ap_start_s; -struct wlan_status_started_s; -struct wlan_status_connected_s; -struct wlan_status_connection_failure_s; -struct wlan_scan_indication_s; - -typedef struct { - const char *client_cert; - const char *client_prvt_key; - const char *ca_cert; -}auth_cert_s; - -/** OdinWiFiInterface class - * Implementation of the WiFiInterface for the ODIN-W2 module - */ -#if DEVICE_WIFI_AP -class OdinWiFiInterface : public WiFiInterface, public UbloxWiFiSoftAPInterface, public EMACInterface -#else -class OdinWiFiInterface : public WiFiInterface, public EMACInterface -#endif -{ -public: - /** OdinWiFiInterface lifetime - */ - OdinWiFiInterface(OdinWiFiEMAC &emac_obj = OdinWiFiEMAC::get_instance(), OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance()); - - OdinWiFiInterface(bool debug, OdinWiFiEMAC &emac_obj = OdinWiFiEMAC::get_instance(), OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance()); - - ~OdinWiFiInterface(); - - /** Set the WiFi network credentials - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection - * (defaults to NSAPI_SECURITY_NONE) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); - - /** Set the WiFi network credentials - * - * @param client_cert Pointer to client certificate - * @param client_pvt_key Pointer to client private key - * @param ca_cert Pointer to ca certificate - * @return 0 on success, or error code on failure - */ - nsapi_error_t set_certificates(const char *client_cert, const char *client_pvt_key , const char *ca_cert ); - - /** Set the WiFi network channel - * - * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_channel(uint8_t channel); - - /** Start the interface - * - * Attempts to connect to a WiFi network. - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) - * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t connect( - const char *ssid, - const char *pass, - nsapi_security_t security = NSAPI_SECURITY_NONE, - uint8_t channel = 0); - - /** Start the interface [local interface] - * - * Attempt to connect to a Wi-Fi network using EAP (EAP_TLS and PEAP). - * - * @param ssid Name of the network to connect to. - * @param pass Security passphrase to connect to the network. - * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE). - * @param channel Channel to make the connection, or 0 for any (Default: 0). - * @param auth_cert_s struct contains pointer to client_certificate, client_private_key and ca_certificate (Default: NULL). - * @param username name of client registered with authentication server (Default: NULL). - * @param password password against user registered with authentication server (Default: NULL). - * @return NSAPI_ERROR_OK on success, or error code on failure. - */ - nsapi_error_t connect( - const char *ssid, - const char *pass, - nsapi_security_t security, - auth_cert_s *cert_handle, - const char *username = NULL, - const char *user_pswd = NULL, - uint8_t channel = 0); - - /** Start the interface - * - * Attempts to connect to a WiFi network. Requires ssid and passphrase to be set. - * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. - * - * @return 0 on success, negative error code on failure - */ - virtual nsapi_error_t connect(); - - /** Stop the interface - * - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t disconnect(); - - - - - /** Gets the current radio signal strength for active connection - * - * @return Connection strength in dBm (negative value), - * or 0 if measurement impossible - */ - virtual int8_t get_rssi(); - - /** Scan for available networks - * - * If the network interface is set to non-blocking mode, scan will attempt to scan - * for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback - * is attached, the callback will be called when the operation has completed. - * - * @param ap Pointer to allocated array to store discovered AP - * @param count Size of allocated @a res array, or 0 to only count available AP - * @param timeout Timeout in milliseconds; 0 for no timeout (Default: 0) - * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error - * see @a nsapi_error - */ - virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, nsapi_size_t count); - - /** Sets timeout for connection setup. Note that the time for DHCP retrieval is not included. - * - * @param timeout Timeout in ms. Use 0 for waiting forever. The timeout might take up to X sec longer than - * specified since the Wi-Fi driver might need some time to finish and cleanup. - * @return 0 on success, negative error code on failure - */ - virtual nsapi_error_t set_timeout(int ms); - - /** Get general settings and tuning parameters - * - * - * @param setting setting to read. - * @return parameter value - */ - virtual unsigned int get_config(void *setting); - - /** - * Set general tuning parameter. - * - * @param setting setting to modify. - * @param value value to set. - */ - virtual void set_config(void *setting, cb_uint32 value); -#ifdef DEVICE_WIFI_AP - - /** Set IP config for access point - * - * This function has to be called before the access point is started. - * - * @param gateway Null-terminated representation of the local gateway - * @param netmask Null-terminated representation of the network mask - * @return 0 on success, negative error code on failure - */ - //TODO: In previous WiFiInterface.h but not in new UbloxWiFiSoftAPInterface - virtual nsapi_error_t set_ap_network(const char *ip_address, const char *netmask, const char *gateway); - - /** Set the WiFi network credentials - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection - * (defaults to NSAPI_SECURITY_NONE) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_ap_credentials(const char *ssid, const char *pass = 0, - nsapi_security_t security = NSAPI_SECURITY_NONE); - - /** Set the WiFi network channel - * - * @param channel Channel on which the connection is to be made. - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_ap_channel(uint8_t channel); - - /** Gets the current number of active connections - * - * @return number of active connections - */ - virtual int get_ap_connection_count(); - - /** Gets the max supported number of active connections - * - * @return maximum number of active connections - */ - virtual int get_ap_max_connection_count(); - - /** Enable or disable DHCP on the network access point - * - * Enables DHCP in SoftAP mode. Defaults to enabled unless - * a static IP address has been assigned. Requires that the network is - * service stopped. - * - * @param dhcp True to enable DHCP - * @return 0 on success, negative error code on failure - */ - virtual nsapi_error_t set_ap_dhcp(bool dhcp); - - /** Set the beacon interval. - * - * Note that the value needs to be set before ap_start in order to take effect. - * - * @param interval Beason interval in time units (Default: 100 time units = 102.4 ms) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_ap_beacon_interval(uint16_t interval); - - /** Start the interface - * - * Attempts to serve a WiFi network. - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) - * @param channel Channel on which the connection is to be made. - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t ap_start(const char *ssid, const char *pass = 0, - nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0); - - /** Start the interface - * - * Attempts to serve a WiFi network. Requires ssid to be set. - * passphrase is optional. - * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. - * - * @return 0 on success, negative error code on failure - */ - virtual nsapi_error_t ap_start(); - - /** Stop the interface - * - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t ap_stop(); - -#endif - -private: - - enum OdinWifiState { - S_NOT_INITIALISED = 1, - S_WAIT_START, - S_STARTED, - S_WAIT_STOP, - - S_STA_IDLE, - S_STA_WAIT_CONNECT, - S_STA_CONNECTED, - S_STA_DISCONNECTED_WAIT_CONNECT, - S_STA_CONNECTION_FAIL_WAIT_DISCONNECT, - S_STA_WAIT_DISCONNECT, - - S_AP_IDLE, - S_AP_WAIT_START, - S_AP_STARTED, - S_AP_WAIT_STOP, - S_AP_FAIL_WAIT_STOP, - S_AP_WAIT_DRV_STOP, - S_AP_WAIT_DRV_START, - - S_INVALID - }; - - struct sta_s { - char ssid[cbWLAN_SSID_MAX_LENGTH]; - char passwd[cbWLAN_MAX_PASSPHRASE_LENGTH]; - nsapi_security_t security; - uint8_t channel; - int timeout_ms; - }; - - struct ap_s { - const char *ssid; - const char *passwd; - nsapi_security_t security; - uint8_t channel; - bool use_dhcp; - - char ip_address[IPADDR_STRLEN_MAX]; - char netmask[IPADDR_STRLEN_MAX]; - char gateway[IPADDR_STRLEN_MAX]; - - int cnt_connected; - - nsapi_error_t error_code; - uint16_t beacon_interval; - - cbWLAN_Handle handle; - }; - - struct scan_cache_s { - int count; - uint8_t last_channel; - cbWLAN_MACAddress bssid[ODIN_WIFI_SCAN_CACHE_SIZE]; - }; - - OdinWifiState entry_connect_fail_wait_disconnect(); - OdinWifiState entry_wait_connect(); - OdinWifiState entry_wait_disconnect(); - OdinWifiState entry_ap_wait_start(); - OdinWifiState entry_ap_started(); - OdinWifiState entry_ap_wait_stop(); - OdinWifiState entry_ap_fail_wait_stop(); - OdinWifiState entry_ap_wait_drv_stop(); - OdinWifiState entry_ap_wait_drv_start(); - - void handle_in_msg(); - void handle_cached_msg(); - - void handle_user_connect(user_connect_s *user_connect); - void handle_user_disconnect(); - void handle_user_scan(user_scan_s *user_scan); - void handle_user_connect_timeout(); - void handle_user_stop(); - - void handle_user_ap_start(user_ap_start_s *user_ap_start); - void handle_user_ap_stop(); - - void handle_wlan_status_started(wlan_status_started_s *start); - void handle_wlan_status_stopped(void); - void handle_wlan_status_error(void); - void handle_wlan_status_connecting(void); - void handle_wlan_status_connected(wlan_status_connected_s *wlan_connect); - void handle_wlan_status_connection_failure(wlan_status_connection_failure_s *connect_failure); - void handle_wlan_status_disconnected(void); - void handle_wlan_scan_indication(); - - void handle_wlan_status_ap_up(); - void handle_wlan_status_ap_down(); - - unsigned int wlan_get_gParams(cbTARGET_ConfigParams setting); - void wlan_set_gParams(cbTARGET_ConfigParams setting, cb_uint32 value); - - void init(bool debug); - nsapi_error_t wlan_set_channel(uint8_t channel); - nsapi_error_t wlan_connect( - const char *ssid, - const char *passwd, - nsapi_security_t security, - auth_cert_s *cert_handle = NULL, - const char *username = NULL, - const char *user_pswd = NULL, - uint8_t channel = 0); - nsapi_error_t wlan_ap_start( - const char *ssid, - const char *pass, - nsapi_security_t security, - uint8_t channel, - uint16_t beacon_interval); - - void timeout_user_connect(); - void update_scan_list(cbWLAN_ScanIndicationInfo *scan_info); - void send_user_response_msg(unsigned int type, nsapi_error_t error_code); - void wlan_status_indication(cbWLAN_StatusIndicationInfo status, void *data); - void wlan_scan_indication(cbWLAN_ScanIndicationInfo *scan_info, cb_boolean is_last_result); - - static bool _wlan_initialized; // Controls that cbWLAN is initiated only once - static int32_t _target_id; - - OdinWifiState _state; - OdinWifiState _state_sta; - OdinWifiState _state_ap; - - struct sta_s _sta; - struct ap_s _ap; - auth_cert_s _certs; - char _mac_addr_str[ODIN_WIFI_MAX_MAC_ADDR_STR]; - - cbWLAN_StatusConnectedInfo _wlan_status_connected_info; - cbWLAN_StatusDisconnectedInfo _wlan_status_disconnected_info; - - bool _scan_active; - WiFiAccessPoint *_scan_list; - nsapi_size_t _scan_list_size; - nsapi_size_t _scan_list_cnt; - struct scan_cache_s _scan_cache; - - friend struct wlan_callb_s; - - Mutex _mutex; - Queue _in_queue; - Queue _out_queue; - Queue _cache_queue; - MemoryPool *_msg_pool; - Thread _thread; - Timer _timer; - - bool _debug; - int _dbg_timeout; - - OdinWiFiEMAC &emac = OdinWiFiEMAC::get_instance(); - - // This flag is added to flush the packets that were coming in between while the status was connected hence causing message pool overflow - bool flush_drvr_ind_pkts = false; -}; - -#endif - -#endif // MBED_CONF_LWIP_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/UbloxWiFiConfigInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/UbloxWiFiConfigInterface.h deleted file mode 100644 index 1136c8ba2b9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/UbloxWiFiConfigInterface.h +++ /dev/null @@ -1,53 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2019, u-blox Malm�, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef UBLOX_WIFI_CONFIGAPINTERFACE_H -#define UBLOX_WIFI_CONFIGAPINTERFACE_H - -#include -#include "cb_wlan_driver_config.h" - -/** UbloxWiFiConfigInterface class - * - * Common interface that is shared between WiFi devices supporting SoftAP mode - */ -class UbloxWiFiConfigInterface -{ -public: - /** UbloxWiFiConfigInterface lifetime - */ - virtual ~UbloxWiFiConfigInterface() {}; - - /** Get general settings and tuning parameters - * - * - * @param setting setting to read. - * @return parameter value - */ - virtual unsigned int get_config(void *setting) = 0; - - /** - * Set general tuning parameter. - * - * @param setting setting to modify. - * @param value value to set. - */ - virtual void set_config(void *setting, cb_uint32 value) = 0; -}; - -#endif - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/UbloxWiFiSoftAPInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/UbloxWiFiSoftAPInterface.h deleted file mode 100755 index 70da4fe4cb9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/UbloxWiFiSoftAPInterface.h +++ /dev/null @@ -1,108 +0,0 @@ - -/* UbloxWiFiSoftAPInterface - * Copyright (c) 2015 - 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef UBLOX_WIFI_SOFTAPINTERFACE_H -#define UBLOX_WIFI_SOFTAPINTERFACE_H - -#include -#include "netsocket/WiFiAccessPoint.h" - -/** UbloxWiFiSoftAPInterface class - * - * Common interface that is shared between WiFi devices supporting SoftAP mode - */ -class UbloxWiFiSoftAPInterface -{ -public: - /** UbloxWiFiSoftAPInterface lifetime - */ - virtual ~UbloxWiFiSoftAPInterface() {}; - - /** Set the WiFi network credentials - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection - * (defaults to NSAPI_SECURITY_NONE) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_ap_credentials(const char *ssid, const char *pass = 0, - nsapi_security_t security = NSAPI_SECURITY_NONE) = 0; - - /** Set the WiFi network channel - * - * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_ap_channel(uint8_t channel) = 0; - - /** Gets the current number of active connections - * - * @return number of active connections - */ - virtual int get_ap_connection_count() = 0; - - /** Gets the max supported number of active connections - * - * @return maximum number of active connections - */ - virtual int get_ap_max_connection_count() = 0; - - /** Enable or disable DHCP on the network access point - * - * Enables DHCP in SoftAP mode. Defaults to enabled unless - * a static IP address has been assigned. Requires that the network is - * service stopped. - * - * @param dhcp True to enable DHCP - * @return 0 on success, negative error code on failure - */ - virtual nsapi_error_t set_ap_dhcp(bool dhcp) = 0; - - /** Start the interface - * - * Attempts to serve a WiFi network. - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) - * @param channel Channel on which the connection is to be made. - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t ap_start(const char *ssid, const char *pass = 0, - nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0) = 0; - - /** Start the interface - * - * Attempts to serve a WiFi network. Requires ssid to be set. - * passphrase is optional. - * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. - * - * @return 0 on success, negative error code on failure - */ - virtual nsapi_error_t ap_start() = 0; - - /** Stop the interface - * - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t ap_stop() = 0; - -}; - -#endif - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h deleted file mode 100644 index a35748ae36e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h +++ /dev/null @@ -1,216 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malm�, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : - * File : bt_types.h - * - * Description : Common Bluetooth types - *-------------------------------------------------------------------------*/ - -/** - * @file bt_types.h - * @brief Common Bluetooth types - */ - -#ifndef _BT_TYPES_H_ -#define _BT_TYPES_H_ - -#include "cb_comdefs.h" - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -#define SIZE_OF_BD_ADDR (6) -#define SIZE_OF_COD (3) -#define SIZE_OF_LINK_KEY (16) -#define SIZE_OF_NAME_INCOMING (248) -#define SIZE_OF_NAME_OUTGOING (64) -#define SIZE_OF_PIN_CODE ((cb_uint8)16) -#define SIZE_OF_LAP (3) -#define SIZE_OF_AFH_LMP_HCI_CHANNEL_MAP (10) -#define CHANNEL_MAP_SIZE (5) -#define SIZE_OF_EXT_INQ_RSP (240) -#define MIN_PASSKEY_VALUE (0) -#define MAX_PASSKEY_VALUE (999999) -#define INVALID_CONN_HANDLE ((TConnHandle)0xFFFF) -#define MAX_ADV_DATA_LENGTH (31) -#define UUID_LENGTH (16) - - -#define PACKET_TYPE_DM1 (0x0008) -#define PACKET_TYPE_DH1 (0x0010) -#define PACKET_TYPE_DM3 (0x0400) -#define PACKET_TYPE_DH3 (0x0800) -#define PACKET_TYPE_DM5 (0x4000) -#define PACKET_TYPE_DH5 (0x8000) - -#define PACKET_TYPE_NO_2_DH1 (0x0002) -#define PACKET_TYPE_NO_3_DH1 (0x0004) -#define PACKET_TYPE_NO_2_DH3 (0x0100) -#define PACKET_TYPE_NO_3_DH3 (0x0200) -#define PACKET_TYPE_NO_2_DH5 (0x1000) -#define PACKET_TYPE_NO_3_DH5 (0x2000) - -#define PACKET_TYPE_ALL (PACKET_TYPE_DM1 | PACKET_TYPE_DH1 | PACKET_TYPE_DM3 | PACKET_TYPE_DH3 | PACKET_TYPE_DM5 | PACKET_TYPE_DH5) - -#define BD_ADDR_IS_STATIC_RANDOM(BdAddress) ((BdAddress[0] & 0xC0) == 0xC0) -#define BD_ADDR_IS_NON_RESOLVABLE(BdAddress) ((BdAddress[0] & 0xC0) == 0x00) -#define BD_ADDR_IS_RESOLVABLE(BdAddress) ((BdAddress[0] & 0xC0) == 0x40) - -#define BT_INVALID_STATIC_LINK_KEY (0) -/*=========================================================================== - * TYPES - *=========================================================================*/ - -typedef cb_int32 int32; -typedef cb_uint32 uint32; -typedef cb_boolean boolean; -typedef cb_int8 int8; -typedef cb_uint8 uint8; -typedef cb_int16 int16; -typedef cb_uint16 uint16; - -typedef cb_uint8 TErrorCode; -typedef cb_uint8 TLinkType; -typedef cb_uint16 TPacketType; -typedef cb_uint16 TConnHandle; - -typedef enum -{ - BT_SECURITY_MODE_1 = 1, - BT_SECURITY_MODE_2, - BT_SECURITY_MODE_3, - BT_SECURITY_MODE_4 - -} TSecurityMode; - -typedef enum -{ - BT_SECURITY_LEVEL_0 = 0, - BT_SECURITY_LEVEL_1, - BT_SECURITY_LEVEL_2, - BT_SECURITY_LEVEL_3, - // Used with security modes 1,2,3 where security level is not applicable - BT_SECURITY_LEVEL_DUMMY = 5, - -} TSecurityLevel; - - -typedef enum -{ - BT_MASTER_SLAVE_POLICY_ALWAYS_MASTER = 0, - BT_MASTER_SLAVE_POLICY_OTHER_SIDE_DECIDE = 1 - -} TMasterSlavePolicy; - -typedef enum -{ - BT_TYPE_CLASSIC = 0, - BT_TYPE_LOW_ENERGY = 1 - -} TBluetoothType; - -typedef enum -{ - BT_PUBLIC_ADDRESS = 0x00, - BT_RANDOM_ADDRESS = 0x01, - -} TAddressType; - -typedef struct -{ - cb_uint8 BdAddress[SIZE_OF_BD_ADDR]; - TAddressType AddrType; - -} TBdAddr; - -typedef struct -{ - cb_uint8 Cod[SIZE_OF_COD]; - -} TCod; - -typedef struct -{ - cb_uint8 LinkKey[SIZE_OF_LINK_KEY]; - -} TLinkKey; - -typedef struct -{ - cb_uint8 Name[SIZE_OF_NAME_INCOMING]; - -} TName; - -typedef struct -{ - cb_uint8 Name[SIZE_OF_NAME_OUTGOING]; - -} TNameOutgoing; - -typedef struct -{ - cb_uint8 PinCode[SIZE_OF_PIN_CODE]; - -} TPinCode; - -typedef cb_uint32 TPasskey; - -typedef struct -{ - cb_uint8 Lap[SIZE_OF_LAP]; - -} TLap; - -typedef struct -{ - cb_uint8 Data[SIZE_OF_EXT_INQ_RSP]; - -} TExtInqRsp; - -typedef cb_uint8 TAfhLmpHciChannelMap[SIZE_OF_AFH_LMP_HCI_CHANNEL_MAP]; - -typedef struct -{ - uint16 channel[CHANNEL_MAP_SIZE]; -} TChannelMap; - - -typedef enum -{ - BT_ADV_TYPE_ADV = 0x01, - BT_ADV_TYPE_SCAN = 0x00, -} TAdvDataType; - -typedef struct -{ - TAdvDataType type; - cb_uint8 length; - cb_uint8 data[MAX_ADV_DATA_LENGTH]; -} TAdvData; - -typedef struct -{ - cb_uint16 createConnectionTimeout; - cb_uint16 connectionIntervalMin; - cb_uint16 connectionIntervalMax; - cb_uint16 connectionLatency; - cb_uint16 linkLossTimeout; - cb_uint16 scanInterval; - cb_uint16 scanWindow; -} TAclParamsLe; - -#endif /* _BT_TYPES_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h deleted file mode 100644 index 249036572d7..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h +++ /dev/null @@ -1,94 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Assert - * File : cb_assert.h - * - * Description : ASSERT macro variations. - *-------------------------------------------------------------------------*/ - -#ifndef _CB_ASSERT_H_ -#define _CB_ASSERT_H_ - -#include "cb_comdefs.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -/* - * Internal platform function declaration. - * Shall never be called directly. - */ - -extern void cbOS_error(cb_int32 errorCode, const cb_char *file, cb_uint32 line); -extern void cbOS_error2(const cb_char *file, cb_uint32 line); - -#ifndef NASSERT - -#ifndef __CB_FILE__ - #define __CB_FILE__ __FILE__ -#endif - -/* - * If the condition (C) evaluates to FALSE, the registered error handler in cbOS - * is called with file and line info before the system is reset. - */ - -#define cb_ASSERT(C) do { if(!(C)){cbOS_error2(__CB_FILE__,__LINE__);} } while(0) - -#define cb_ASSERTC(C) do { if(!(C)){cbOS_error2(__CB_FILE__ , __LINE__);} } while(0) - -#define cb_ASSERT2(C, E) do { if(!(C)){cbOS_error(E, __CB_FILE__ , __LINE__);} } while(0) - -/* - * The registered error handler is called with the file and line info before a system reset. - */ - -#define cb_EXIT(E) do { cbOS_error(((cb_int32)(E)), __CB_FILE__, __LINE__); } while(0) - - -#else - -#define cb_ASSERT(C) - -#define cb_ASSERTC(C) do { if(!(C)){cbWD_systemReset();} } while(0) // Critical assert is never removed. - -#define cb_ASSERT2(C, E) - -#define cb_EXIT(E) do { cbWD_systemReset(); } while(0) - -#endif - - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _cb_ASSERT_H_ */ - - - - - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h deleted file mode 100644 index 352337abcf8..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h +++ /dev/null @@ -1,878 +0,0 @@ -/** - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Bluetooth Connection Manager - * File : cb_bt_conn_man.h - * - * Description : Bluetooth Connection Management - * - *-------------------------------------------------------------------------*/ - -/** - * @file cb_bt_conn_man.h - * @brief Connection management. Functionality for setting up and tearing - * down Bluetooth connections. Profile services are also enabled - * using this module. - */ - -#ifndef _CB_BT_CONN_MAN_H_ -#define _CB_BT_CONN_MAN_H_ - -#include "cb_comdefs.h" -#include "bt_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbBCM_OK (0) -#define cbBCM_ERROR (-1) -#define cbBCM_ILLEGAL_HANDLE (-2) -#define cbBCM_NOT_IMPLEMENTED (-3) -#define cbBCM_ERROR_DISCONNECTING (-4) -#define cbBCM_ERROR_ALREADY_REGISTERED (-5) -#define cbBCM_ERROR_ALREADY_CONNECTED (-6) - -#define cbBCM_ACL_CONNECTION_FAILED (-7) -#define cbBCM_SERVICE_SEARCH_FAILED (-8) -#define cbBCM_RFCOMM_CONNECTION_FAILED (-9) -#define cbBCM_SPS_CONNECTION_FAILED (-10) -#define cbBCM_ACL_DISCONNECTED (-11) - -#define cbBCM_INVALID_CONNECTION_HANDLE (cb_UINT32_MAX) -#define cbBCM_INVALID_SERVER_CHANNEL (cb_UINT8_MAX) -#define cbBCM_SERVICE_NAME_MAX_LEN (32) - -#define cbBCM_DEV_ID_VENDOR_ID_SRC_BLUETOOTH (0x0001) -#define cbBCM_DEV_ID_VENDOR_ID_SRC_USB (0x0002) -#define cbBCM_CONNECTBLUE_VENDOR_ID (0x0071) - -/*=========================================================================== - * TYPES - *=========================================================================*/ -typedef cb_uint32 cbBCM_Handle; - -typedef enum -{ - cbBCM_INVALID_CONNECTION = 0, - cbBCM_SPP_CONNECTION, // Serial Port Profile - cbBCM_DUN_CONNECTION, // Dial Up Networking Profile - cbBCM_UUID_CONNECTION, // UUID - cbBCM_PAN_CONNECTION, // PAN - - cbBCM_ACL_LE_CONNECTION, // GATT - cbBCM_SPS_CONNECTION // LE connectBlue Serial Service connection -}cbBCM_ConnectionType; - -typedef enum -{ - cbBM_LINK_QUALITY_READY_OK, - cbBM_LINK_QUALITY_READY_ERROR -} cbBCM_LinkQualityEvt; - -/** - * Bluetooth Classic Acl connection parameters - */ -typedef struct -{ - cb_uint16 pageTimeout; /** Length of connection attempt. Default value 5000ms. */ - cb_uint16 packetType; /** Packet types allowed in the connection. By default all packets but 3MBit EDR are allowed. */ - TMasterSlavePolicy masterSlavePolicy; /** Whether master slave switch shall be allowed or not. By default master slave switch is allowed. */ - cb_uint16 clockOffset; /** Clock offset is part in inquiry response. Using this value may result in faster connection setup Default value 0. */ - cb_uint16 linkSupervisionTimeout; /** Link supervision timeout. Default value 2000ms. */ -} cbBCM_ConnectionParameters; - -/** - * Bluetooth Low Energy Acl connection parameters - */ -typedef struct -{ - cb_uint32 createConnectionTimeout; /** Length of connection attempt in ms. Default value 5000ms. */ - cb_uint16 connectionIntervalMin; /** Minimum connection interval in ms. Default value 6ms. */ - cb_uint16 connectionIntervalMax; /** Maximum connection interval in ms. Default value 8ms. */ - cb_uint16 connectionLatency; /** Slave latency. Default value 0. */ - cb_uint16 linkLossTimeout; /** Link loss timeout in ms. Default 2000ms. */ -} cbBCM_ConnectionParametersLe; - -typedef enum -{ - cbBCM_PAN_ROLE_PANU = 0, - cbBCM_PAN_ROLE_NAP, - cbBCM_PAN_ROLE_NONE -}cbBCM_PAN_Role; - -typedef struct -{ - TBdAddr address; - TNameOutgoing remoteName; - cb_int8 remoteRssi; - cbBCM_ConnectionType type; - TConnHandle aclHandle; - TBluetoothType btType; - cb_uint8 serverChannel; - cb_uint8 uuid[16] ; - cb_boolean uuidValid; - cb_char serviceName[cbBCM_SERVICE_NAME_MAX_LEN]; -} cbBCM_ConnectionInfo; - -typedef void (*cbBCM_ConnectInd)( - cbBCM_Handle handle, - cbBCM_ConnectionInfo info); - -typedef void (*cbBCM_ConnectEvt)( - cbBCM_Handle handle, - cbBCM_ConnectionInfo info); - -typedef void (*cbBCM_ConnectCnf)( - cbBCM_Handle handle, - cbBCM_ConnectionInfo info, - cb_int32 status); - -typedef void (*cbBCM_DisconnectEvt)( - cbBCM_Handle handle); - -typedef struct -{ - cbBCM_ConnectInd pfConnectInd; - cbBCM_ConnectEvt pfConnectEvt; - cbBCM_ConnectCnf pfConnectCnf; - cbBCM_DisconnectEvt pfDisconnectEvt; -} cbBCM_ConnectionCallback; - -typedef void(*cbBCM_RoleDiscoveryCallback)( - cbBCM_Handle handle, - cb_int8 status, - cb_uint8 role); - -typedef void (*cbBCM_RssiCallback)( - cbBCM_Handle handle, - cb_int32 status, - cb_int8 rssi); - -typedef void (*cbBCM_DataEvt)( - cbBCM_Handle handle, - cb_uint8 *pBuf, - cb_uint32 nBytes); - -typedef void (*cbBCM_WriteCnf)( - cbBCM_Handle handle, - cb_int32 status); - -/** - * Set max number of Bluetooth links. - * Not used by application - * @return status TRUE if command was successful - */ -typedef cb_int32 (*cbBCM_SetMaxLinksCmd)(cb_uint32 maxLinks); - -/** - * Check if Handle is free to use - * @return TRUE if handle is free, FALSE otherwise - */ -typedef cb_boolean (*cbBCM_IsHandleFree)(cbBCM_Handle handle); - -/** - * Callback to indicate that remaining buffer size needs to be obtained from - * upper layer. The callback returns remaining buffer size and there is - * therefore no response function. - * Not used by application - * @return Number of free bytes in channel data buffer - */ -typedef cb_uint16 (*cbBCM_RemainBufSizeInd)(void); - -typedef struct -{ - cbBCM_ConnectEvt pfConnectEvt; - cbBCM_DisconnectEvt pfDisconnectEvt; - cbBCM_DataEvt pfDataEvt; - cbBCM_WriteCnf pfWriteCnf; - cbBCM_SetMaxLinksCmd pfSetMaxLinks; - cbBCM_RemainBufSizeInd pfRemainBufSizeInd; - cbBCM_IsHandleFree pfIsHandleFree; -} cbBCM_DataCallback; - -typedef void (*cbBCM_ServiceSearchCompleteCallback)(cb_int32 status); - -typedef void (*cbBCM_ServiceSearchSppCallback)( - cb_uint8 serverChannel, - cb_char *pServiceName); - -typedef void (*cbBCM_ServiceSearchDunCallback)( - cb_uint8 serverChannel, - cb_char *pServiceName); - -typedef void (*cbBCM_ServiceSearchDeviceIdCallback)( - cb_uint16 didSpecVersion, - cb_uint16 didVendorId, - cb_uint16 didProductId, - cb_uint16 didProductVersion, - cb_boolean didPrimaryService, - cb_uint16 didVendorIdSource); - -typedef void(*cbBCM_LinkQualityCallback)( - cbBCM_LinkQualityEvt linkQualityEvt, - uint8 linkQuality); - -typedef void(*cbBCM_ServiceClassEnabled)(cb_uint8 serviceChannel); -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ -/** - * Initialization of connection manager. Called during stack - * initialization. Shall not be called by application. - * - * @return None - */ -extern void cbBCM_init(void); - -/** - * Enable a Bluetooth Serial Port Profile (SPP)service record to - * allow other devices to connect to this device using SPP. - * - * @param pServiceName The name of the service - * @param pServerChannel Pointer to return variable. The server channel is used to identify - * incoming connections. - * @param pConnectionCallback Callback structure for connection management. - * @param pServiceClassEnabled Callback structure to inform when service is running. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_enableServerProfileSpp( - cb_char *pServiceName, - cb_uint8 *pServerChannel, - cbBCM_ConnectionCallback *pConnectionCallback, - cbBCM_ServiceClassEnabled pServiceClassEnabled); - -/** - * Enable a Dial Up Networking Profile (DUN)service record to - * allow other devices to connect to this device using DUN. - * - * @param pServiceName The name of the service - * @param pServerChannel Pointer to return variable. The server channel is used to identify - * incoming connections. - * @param pConnectionCallback Callback structure for connection management. - * @param pServiceClassEnabled Callback structure to inform when service is running. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_enableServerProfileDun( - cb_char *pServiceName, - cb_uint8 *pServerChannel, - cbBCM_ConnectionCallback *pConnectionCallback, - cbBCM_ServiceClassEnabled pServiceClassEnabled); - -/** - * Enable a service record with an application specific UUID. - * This is used to enable Android and iOS support. - * - * @param pUuid128 The UUID of the service. - * @param pServiceName The name of the service - * @param pServerChannel Pointer to return variable. The server channel is used to identify - * incoming connections. - * @param pConnectionCallback Callback structure for connection management. - * @param pServiceClassEnabled Callback structure to inform when service is running. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_enableServerProfileUuid128( - cb_uint8 *pUuid128, - cb_char *pServiceName, - cb_uint8 *pServerChannel, - cbBCM_ConnectionCallback *pConnectionCallback, - cbBCM_ServiceClassEnabled pServiceClassEnabled); - -/** -* Registers the server role of the local device. If role is cbBCM_PAN_ROLE_NAP a service -* record will be registred in the local service data base. The local device can only act as a -* PAN NAP or Pan user at a time. If PAN NAP is enabled the device will only accept incoming -* connections from PAN users. If PAN user is enabled it is only possible to be connected to -* one remote PAN NAP device. -* -* @param pServiceName The name of the service -* @param role The PAN role of the local device -* @param pConnectionCallback Callback structure for connection management. -* @param pServiceClassEnabled Callback structure to inform when service is running. -* @return If the operation is successful cbBCM_OK is returned. -*/ -extern cb_int32 cbBCM_enableServerProfilePan( - cb_char *pServiceName, - cbBCM_PAN_Role role, - cbBCM_ConnectionCallback *pConnectionCallback, - cbBCM_ServiceClassEnabled pServiceClassEnabled); - -/** - * Enable device id service record.The device id service record is a method by which - * Bluetooth devices may provide information that may be used by peer Bluetooth devices - * to find representative icons or load associated support software. - * This information is published as Bluetooth SDP records, and optionally in the - * Extended Inquiry Response. - * @param vendorId Uniquely identifier for the vendor of the device. Used in conjunction with required attribute 0x0205, VendorIDSource, which determines which organization assigned the VendorID value. Note: The Bluetooth Special Interest Group assigns Device ID Vendor ID and the USB Implementer's Forum assigns vendor IDs, either of which can be used for the VendorID value here. Device providers should procure the vendor ID from the USB Implementer's Forum or the Company Identifier from the Bluetooth SIG. The VendorID '0xFFFF' is reserved as the default VendorID when no Device ID Service Record is present in the device. - * @param productId This is intended to distinguish between different products made by the vendor above. These IDs are managed by the vendors themselves. - * @param version A numeric expression identifying the device release number in Binary-Coded Decimal. This is a vendor-assigned field, which defines the version of the product identified by the VendorID and ProductID attributes. This attribute is intended to differentiate between versions of products with identical VendorIDs and ProductIDs. The value of the field is 0xJJMN for version JJ.M.N (JJ - major version number, M - minor version number, N - sub-minor version number); e.g., version 2.1.3 is represented with value 0x0213 and version 2.0.0 is represented with a value of 0x0200. When upward-compatible changes are made to the device, it is recommended that the minor version number be incremented. If incompatible changes are made to the device, it is recommended that the major version number be incremented. - * @param vendorIdSource Organization that assigned the VendorID attribute. Use 0x0001 for Bluetooth SIG assigned Device ID Vendor ID value from the Assigned Numbers document and 0x0002 for USB Implementer's Forum assigned Vendor ID value - * @return If the operation is successful cbBCM_OK is returned. Note that only one device id service record can be registered. - */ -extern cb_int32 cbBCM_enableDeviceIdServiceRecord( - cb_uint16 vendorId, - cb_uint16 productId, - cb_uint16 version, - cb_uint16 vendorIdSource); - -/** - * Set Bluetooth watchdog settings - * - * @param disconnectReset Reset the device on any dropped Bluetooth connection - * @return void - */ -extern void cbBCM_setBluetoothWatchdogValue(cb_uint32 disconnectReset); - -/** - * Set the packet types to use. Call cbBCM_cmdChangePacketType() - * to start using the new packet types. - * - * @param packetType See packet types in bt_types.h - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_uint32 cbBCM_setPacketType(cb_uint16 packetType); - -/** - * Get BT classic packet type. - * - * @return Allowed packet types returned. - */ -extern cb_uint16 cbBCM_getPacketType(void); - -/** - * Set max number of Bluetooth classic links. Reconfigures buffer management. - * - * @param maxLinks Max number of Bluetooth classic connections. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_setMaxLinksClassic(cb_uint16 maxLinks); - -/** - * Get max number of Bluetooth classic links. - * - * @return The maximum number of Bluetooth classic links. - */ -extern cb_uint16 cbBCM_getMaxLinksClassic(void); - -/** - * Set max number of Bluetooth Low Energy links. Reconfigures buffer management. - * - * @param maxLinks Max number of Bluetooth Low Energy connections. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_setMaxLinksLE(cb_uint16 maxLinks); - -/** - * Get max number of Bluetooth Low Energy links. - * - * @return The maximum number of Bluetooth Low Energy links. - */ -extern cb_uint16 cbBCM_getMaxLinksLE(void); - -/** - * Initiate a Bluetooth Serial Port Profile connection. - * The connection sequence includes ACL connection setup, SDP service - * search and RFCOMM connection setup. The server channel of the first - * valid SPP service record will be used. A pfConnectCnf callback will - * be received when the connection is complete.The error code in the - * callback is cbBCM_OK if the connection was successfully established. - * The error code in the callback is cbBCM_ERROR if the connection failed. - * @param pAddress Pointer to address of remote device. - * @param pServiceName Name of SPP service. Automatic service search - * is performed to find a service with matching name. - * If set to NULL then the last of the SPP services - * on the remote device will be used. If serverChannel - * parameter is different than cbBCM_INVALID_SERVER_CHANNEL - * this parameter is ignored and the specified server channel - * will be used. - * @param serverChannel RFCOMM server channel that shall be used. Set to - * cbBCM_INVALID_SERVER_CHANNEL to perform automatic - * service search to find the server channel. - * @param pRemoteName Pointer used in case user connects to the Bluetooth name - * @param pAclParameters Link configuration including link supervision timeout - * and master slave policy. Pass NULL to use default connection - * parameters. - * @param pConnectionCallback Callback structure for connection management. - * @return If the operation is successful the connection handle is returned. If - * not cbBCM_INVALID_CONNECTION_HANDLE is returned. - */ -extern cbBCM_Handle cbBCM_reqConnectSpp( - TBdAddr *pAddress, - cb_char *pServiceName, - cb_uint8 serverChannel, - cb_char *pRemoteName, - cbBCM_ConnectionParameters *pAclParameters, - cb_boolean qosEnable, - cbBCM_ConnectionCallback *pConnectionCallback); - -/** - * Accept or reject an incoming SPP connection. This is a - * response to a cbBCM_ConnectInd connection indication. - * - * @param handle Connection handle - * @param accept TRUE to accept the incoming connection. - FALSE to reject. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_rspConnectSppCnf( - cbBCM_Handle handle, - cb_boolean accept); - -/** - * Initiate a Bluetooth Dial Up Networking Profile connection. - * The connection sequence includes ACL connection setup, SDP service - * search and RFCOMM connection setup. The server channel of the first - * valid SPP service record will be used. A pfConnectCnf callback will - * be received when the connection is complete.The error code in the - * callback is cbBCM_OK if the connection was successfully established. - * The error code in the callback is cbBCM_ERROR if the connection failed. - * @param pAddress Pointer to address of remote device. - * @param pServiceName Name of DUN service. Automatic service search - * is performed to find a service with matching name. - * If set to NULL then the last of the DUN services - * on the remote device will be used. If serverChannel - * parameter is different than cbBCM_INVALID_SERVER_CHANNEL - * this parameter is ignored and the specified server channel - * will be used. - * @param serverChannel RFCOMM server channel that shall be used. Set to - * cbBCM_INVALID_SERVER_CHANNEL to perform automatic - * service search to find the server channel. - * @param pAclParameters Link configuration including link supervision timeout - * and master slave policy. Pass NULL to use default connection - * parameters. - * @param pConnectionCallback Callback structure for connection management. - * @return If the operation is successful the connection handle is returned. If - * not cbBCM_INVALID_CONNECTION_HANDLE is returned. - */ -extern cbBCM_Handle cbBCM_reqConnectDun( - TBdAddr *pAddress, - cb_char *pServiceName, - cb_uint8 serverChannel, - cbBCM_ConnectionParameters *pAclParameters, - cb_boolean qosEnable, - cbBCM_ConnectionCallback *pConnectionCallback); - -/** - * Accept or reject an incoming DUN connection. This is a - * response to a cbBCM_ConnectInd connection indication. - * - * @param handle Connection handle - * @param accept TRUE to accept the incoming connection. - FALSE to reject. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_rspConnectDunCnf( - cbBCM_Handle handle, - cb_boolean accept); - -/** - * Initiate a Bluetooth Serial Port Profile connection with a specific UUID. - * The connection sequence includes ACL connection setup, SDP service - * search and RFCOMM connection setup. The server channel of the first - * valid SPP service record with the specified UUID will be used. A pfConnectCnf - * callback will be received when the connection is complete.The error code in the - * callback is cbBCM_OK if the connection was successfully established. - * The error code in the callback is cbBCM_ERROR if the connection failed. - * @param pAddress Pointer to address of remote device. - * @param pUuid Pointer to uuid of the remote service. - * @param pServiceName Name of SPP service. Automatic service search - * is performed to find a service with matching name. - * If set to NULL then the last of the SPP services - * on the remote device will be used. If serverChannel - * parameter is different than cbBCM_INVALID_SERVER_CHANNEL - * this parameter is ignored and the specified server channel - * will be used. - * @param serverChannel RFCOMM server channel that shall be used. Set to - * cbBCM_INVALID_SERVER_CHANNEL to perform automatic - * service search to find the server channel. - * @param pAclParameters Link configuration including link supervision timeout - * and master slave policy. Pass NULL to use default connection - * parameters. - * @param pConnectionCallback Callback structure for connection management. - * @return If the operation is successful the connection handle is returned. If - * not cbBCM_INVALID_CONNECTION_HANDLE is returned. - */ -extern cbBCM_Handle cbBCM_reqConnectUuid( - TBdAddr *pAddress, - cb_uint8 *pUuid, - cb_char *pServiceName, - cb_uint8 serverChannel, - cbBCM_ConnectionParameters *pAclParameters, - cb_boolean qosEnable, - cbBCM_ConnectionCallback *pConnectionCallback); - -/** - * Accept or reject an incoming SPP connection. This is a - * response to a cbBCM_ConnectInd connection indication. - * - * @param handle Connection handle - * @param accept TRUE to accept the incoming connection. - * FALSE to reject. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_rspConnectUuidCnf( - cbBCM_Handle handle, - cb_boolean accept); - -/** - * Initiate a Bluetooth PAN Profile connection. - * The connection sequence includes ACL connection setup and L2CAP connection setup. - * A pfConnectCnf callback will be received when the connection is complete. - * The error code in the*callback is cbBCM_OK if the connection was successfully established. - * The error code in the callback is cbBCM_ERROR if the connection failed. - * - * @param pAddress Pointer to address of remote device. - * @param remoteRole PAN role of the remote device - * @param localRole PAN role of the local device - * @param pAclParams Link configuration including link supervision timeout - * and master slave policy. Pass NULL to use default connection - * parameters. - * @param pConnectionCallback Callback structure for connection management. - * @return If the operation is successful the connection handle is returned. If - * not cbBCM_INVALID_CONNECTION_HANDLE is returned. - */ -extern cbBCM_Handle cbBCM_reqConnectPan( - TBdAddr *pAddress, - cbBCM_PAN_Role remoteRole, - cbBCM_PAN_Role localRole, - cbBCM_ConnectionParameters *pAclParams, - cbBCM_ConnectionCallback *pConnectionCallback); - -/** - * Accept or reject an incoming PAN connection. This is a - * response to a cbBCM_ConnectInd connection indication. - * - * @param handle Connection handle - * @param accept TRUE to accept the incoming connection. - * FALSE to reject. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_rspConnectPan( - cbBCM_Handle handle, - cb_boolean accept); - -/** - * Enable Serial Port Service. - * When the device is acting Bluetooth Low Energy peripheral the Serial - * Port Service will be added to the attribute table. - * - * @param pConnectionCallback Callback structure for connection management. - * @return If the operation is successful cbBCM_OK is returned. - * @param pConnectionCallback Callback structure for connection management. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_enableSps( - cbBCM_ConnectionCallback *pConnectionCallback); - -/** - * Enable or disable Bluetooth low energy auto connect. - * When the device is acting as central and auto connect is enabled it runs - * passive scan and initiates an ACL connection to devices that performs - * directed advertisements. - * The serial port service muast be enabled using cbBCM_enableSps() before - * auto connect is enabled. - * If SPS is enabled the SPS Gatt client will initiate a SPS connection - * attempt on the ACL connection. - * When the device is acting peripheral this functionality is inactive. - * - * @param enable Set to TRUE to enable. Set to false to disable. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_autoConnect( - cb_boolean enable); - -/** - * Initiate a Serial Port Service connection. - * The connection sequence includes ACL connection setup , GATT service - * search and Serial Port Service connection setup. A connect confirm - * callback will be received when the connection is complete. The error - * code in the callback is cbBCM_OK if the connection was successfully established. - * The error code in the callback is cbBCM_ERROR if the connection failed. - * The serial port service must be enabled using cbBCM_enableSps() before - * auto connect request is made.. - * @param pAddress Address of remote device. - * @param pAclLeParams Link configuration parameters - * @param pConnectionCallback Callback structure for connection management. - * @return If the operation is successful the connection handle is returned. If - * not cbBCM_INVALID_CONNECTION_HANDLE is returned. - */ -extern cbBCM_Handle cbBCM_reqConnectSps( - TBdAddr *pAddress, - cb_char *pRemoteName, - cbBCM_ConnectionParametersLe *pAclLeParams, - cbBCM_ConnectionCallback *pConnectionCallback); - -/** - * Accept or reject an incoming SPS connection. This is a - * response to a cbBCM_ConnectInd connection indication. - * @param handle Connection handle - * @param accept TRUE to accept the incoming connection. - * FALSE to reject. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_rspConnectSpsCnf( - cbBCM_Handle handle, - cb_boolean accept); - -/** - * Initiate a Bluetooth low energy ACL connection. The ACL connection is - * intended for GATT communication. - * A connect confirm callback will be received when the connection is complete. The error - * code in the callback is cbBCM_OK if the connection was successfully established. - * The error code in the callback is cbBCM_ERROR if the connection failed. - * @param pAddress Address of remote device. - * @param pAclLeParams Link configuration parameters - * @param pConnectionCallback Callback structure for connection management. - * @return If the operation is successful the connection handle is returned. If - * not cbBCM_INVALID_CONNECTION_HANDLE is returned. - */ -extern cbBCM_Handle cbBCM_reqConnectAclLe( - TBdAddr *pAddress, - cbBCM_ConnectionParametersLe *pAclLeParams, - cbBCM_ConnectionCallback *pConnectionCallback); - -/** - * @brief Initiate disconnection of active connection. A disconnect event - * will be received when the disconnection is complete. - * - * @param handle Connection handle - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_cmdDisconnect( - cbBCM_Handle handle); - -/** - * @brief Initiate a Serial Port Profile (SPP) service search to find server channel and service name. - * @param pAddress Address of device on which service search shall be performed. - * @param maxServices Max number of services - * @param pCallback Callback used to notify each found service record - * @param pCompleteCallback Callback used to notify that the search is completed - * @return If the operation is successful initiated cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_reqServiceSearchSpp( - TBdAddr *pAddress, - cb_uint16 maxServices, - cbBCM_ServiceSearchSppCallback pCallback, - cbBCM_ServiceSearchCompleteCallback pCompleteCallback); - -/** - * @brief Initiate a Dial Up Networking (DUN) service search to find server channel and service name. - * @param pAddress Address of device on which service search shall be performed. - * @param maxServices Max number of services - * @param pCallback Callback used to notify each found service record - * @param pCompleteCallback Callback used to notify that the search is completed - * @return If the operation is successful initiated cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_reqServiceSearchDun( - TBdAddr *pAddress, - cb_uint16 maxServices, - cbBCM_ServiceSearchSppCallback pCallback, - cbBCM_ServiceSearchCompleteCallback pCompleteCallback); - -/** - * @brief Initiate a UUID service search to find server channel and service name. - * @param pAddress Address of device on which service search shall be performed. - * @param pUuid128 128 UUID to search for. - * @param maxServices Max number of services - * @param pCallback Callback used to notify each found service record - * @param pCompleteCallback Callback used to notify that the search is completed - * @return If the operation is successful initiated cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_reqServiceSearchUuid( - TBdAddr *pAddress, - const cb_uint8 *pUuid128, - cb_uint16 maxServices, - cbBCM_ServiceSearchSppCallback pCallback, - cbBCM_ServiceSearchCompleteCallback pCompleteCallback); - -/** - * @brief Initiate a Device information service search. - * @param pAddress Address of device on which service search shall be performed. - * @param maxServices Max number of services - * @param pCallback Callback used to notify each found service record - * @param pCompleteCallback Callback used to notify that the search is completed - * @return If the operation is successful initiated cbBCM_OK is returned. - */ -cb_int32 cbBCM_reqServiceSearchDeviceId( - TBdAddr *pAddress, - cb_uint16 maxServices, - cbBCM_ServiceSearchDeviceIdCallback pCallback, - cbBCM_ServiceSearchCompleteCallback pCompleteCallback); - -/** - * @brief Get local Master/Slave role in an active connection. - * @param bdAddr address to the connection - * @param roleDiscoveryCallback Callback function used to notify the role - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_RoleDiscovery( - TBdAddr bdAddr, - cbBCM_RoleDiscoveryCallback roleDiscoveryCallback); - -/** - * @brief Get current Received Signal Strength Indication (RSSI) - * of an active connection. - * @param bdAddress bt address to the connected device - * @param rssiCallback Callback function used to notify the rssi value - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_getRssi( - TBdAddr bdAddress, - cbBCM_RssiCallback rssiCallback); - -/* - * Read the LinkQuality . - * @return status as int32. - * @cbBM_LinkQualityCallback is used to provide result. - */ -extern cb_int32 cbBCM_GetLinkQuality(TBdAddr bdAddr, cbBCM_LinkQualityCallback linkQualityCallback); - -/** - * @brief Change the packet types currently used for an active Bluetooth - * Classic connection. - * @param handle Connection handle - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_cmdChangePacketType( - cbBCM_Handle handle); - -/** - * @brief Get the current connection parameters for an active Bluetooth - * Low Energy ACL connection. - * @param handle Connection handle - * @param pConnectionInterval Connection interval - * @param pConnectionLatency Connection latency - * @param pLinkSupervisionTmo Link supervision timeout - * @return If the update is successfully initiated cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_getConnectionParams( - cbBCM_Handle handle, - cb_uint16 *pConnectionInterval, - cb_uint16 *pConnectionLatency, - cb_uint16 *pLinkSupervisionTmo); - -/** - * @brief Update connection parameters for an active Bluetooth - * Low Energy ACL connection. - * @param handle Connection handle - * @param pAclLeParams New Link configuration parameters - * @return If the update is successfully initiated cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_updateConnectionParams( - cbBCM_Handle handle, - cbBCM_ConnectionParametersLe *pAclLeParams); - -/** - * Register a GATT device information service. The device information service - * is used by remote devices to get for example the model and firmware version - * of this device. - * Note that an application easily can define and register its own device information - * service if other characteristics are required. - * @param pManufacturer String defining the manufacturer. - * @param pModel String defining the device model. - * @param pFwVersion String defining the firmware version. - * @param startIndex Start index of the attribute database for the device info service. - * Note that this must not change during the lifetime of the product. - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_enableDevInfoService( - const cb_char *pManufacturer, - const cb_char *pModel, - const cb_char *pFwVersion, - cb_uint16 startIndex); - -/** - * @brief Get the address of the remote device on an - * active connection - * - * @param handle Connection handle - * @return Address of the remote device. - */ -extern TBdAddr cbBCM_getAddress(cbBCM_Handle handle); - -/** - * @brief Register a data manager for a type of connections. Shall not be - * used by the application. Only used by data managers. - * - * @param type Connection type. - * @param pDataCallback Data callback - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_registerDataCallback( - cbBCM_ConnectionType type, - const cbBCM_DataCallback *pDataCallback); - -/** - * @brief Get the protocol handle for an active connection. Shall not be used - * by the application. Only used by data managers. - * - * @param handle Connection handle - * @return If the operation is not successful cbBCM_INVALID_CONNECTION_HANDLE - * is returned. If the operation is successful the protocol handle is - * returned. - */ -extern cbBCM_Handle cbBCM_getProtocolHandle( - cbBCM_Handle handle); - -/** - * @brief Get the bcm id from acl handle for an active connection. - * - * @param handle Connection handle - * @return bcm handle. - */ -extern cbBCM_Handle cbBCM_getIdFromAclHandle(TConnHandle aclHandle); - -/** - * @brief Get the acl handle from bcm handle. - * - * @param handle bcm handle - * @return acl handle - */ -extern TConnHandle cbBCM_getAclFromIdHandle(cbBCM_Handle bcmHandle); - -/** - * @brief Set active poll mode to introduce periodic BT classic link polling. - * @param mode Active poll mode 0=disable, 1=enable (default period), 2-UINT16_MAX: period of poll - * @return If the update is successfully initiated cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_setActivePollMode(cb_uint16 mode); - -/** - * @brief Get active poll mode. - * @return Active poll mode 0=disable, 1=enable - */ -extern cb_uint16 cbBCM_getActivePollMode(void); - -/** - * @brief Change which packet types can be used for the connection identified by the handle - * @param handle Connection handle - * @param aclPacketType bit map according to packet types defined in bt_types.h - * @return If the operation is successful cbBCM_OK is returned. - */ -extern cb_int32 cbBCM_changeConnectionPacketType( - cbBCM_Handle handle, - TPacketType aclPacketType); - - -#ifdef __cplusplus -} -#endif - - -#endif /* _CB_BT_CONN_MAN_H_ */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h deleted file mode 100644 index 5cfabc2543e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h +++ /dev/null @@ -1,1024 +0,0 @@ -/* - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Bluetooth Manager - * File : cb_bt_man.h - * - * Description : General Bluetooth functionality - * - *-------------------------------------------------------------------------*/ - -/** - * @file cb_bt_man.h - * - * @brief General Bluetooth functionality. This includes initialization of - * the Bluetooth radio and stack, handling properties such as device - * name, scanning for other devices using inquiry or Bluetooth Low Energy - * scan and more. - */ - -#ifndef _CB_BT_MAN_H_ -#define _CB_BT_MAN_H_ - -#include "cb_comdefs.h" -#include "bt_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== -* DEFINES -*=========================================================================*/ -#define cbBM_OK (0) -#define cbBM_ERROR (-1) -#define cbBM_MAX_OUTPUT_POWER (127) - -#define cbBM_ADV_CHANNEL_MAP_CH_37_BIT 0x01 -#define cbBM_ADV_CHANNEL_MAP_CH_38_BIT 0x02 -#define cbBM_ADV_CHANNEL_MAP_CH_39_BIT 0x04 -#define cbBM_ADV_CHANNEL_MAP_ALL (cbBM_ADV_CHANNEL_MAP_CH_37_BIT | cbBM_ADV_CHANNEL_MAP_CH_38_BIT | cbBM_ADV_CHANNEL_MAP_CH_39_BIT) -/*=========================================================================== -* TYPES -*=========================================================================*/ - -extern const TBdAddr invalidBdAddress; - -typedef enum -{ - cbBM_INQUIRY_GENERAL = 0, - cbBM_INQUIRY_LIMITED = 1, -} cbBM_InquiryType; - -typedef void(*cbBM_TIStatusCallback)( - cb_int32 status, - cb_int8 temperature); - -typedef void (*cbBM_InquiryEventCallback)( - TBdAddr *pBdAddress, - TCod cod, - cb_uint16 clockOffset, - cb_int8 rssi, - cb_char *pName, - TExtInqRsp* pExtInqRsp, - cb_uint8 length); - -typedef void (*cbBM_InquiryCompleteCallback)( - cb_int32 status); - -typedef void (*cbBM_RemoteNameCallback)( - TBdAddr *pBdAddress, - TName *pName, - cb_int32 status); - -typedef enum -{ - cbBM_DEVICE_DISCOVERY_LE_ALL = 0, // Limited size filtering to reduce duplicate results (for devices in filter). - cbBM_DEVICE_DISCOVERY_LE_GENERAL, - cbBM_DEVICE_DISCOVERY_LE_LIMITED, - cbBM_DEVICE_DISCOVERY_LE_ALL_NO_FILTERING // No found devices filtered out due to previously found -} cbBM_DeviceDiscoveryTypeLe; - -typedef enum -{ - cbBM_ACTIVE_SCAN = 0, - cbBM_PASSIVE_SCAN = 1 -} cbBM_ScanTypeLe; - - -typedef void (*cbBM_DeviceDiscoveryLeEventCallback)( - TBdAddr *pBdAddress, // Bluetooth address - cb_int8 rssi, // Tx power in dBm - cb_char *pName, // Remote name as null terminated string - TAdvData *pAdvData); // Advertisment data of remote device - -typedef void (*cbBM_DeviceDiscoveryLeCompleteCallback)( - cb_int32 status); - -typedef enum -{ - cbBM_DISCOVERABLE_MODE_NONE = 0, - cbBM_DISCOVERABLE_MODE_LIMITED = 1, - cbBM_DISCOVERABLE_MODE_GENERAL = 2, -} cbBM_DiscoverableMode; - -typedef enum -{ - cbBM_CONNECTABLE_MODE_NOT_CONNECTABLE = 0, - cbBM_CONNECTABLE_MODE_CONNECTABLE -} cbBM_ConnectableMode; - -typedef enum -{ - cbBM_DISCOVERABLE_MODE_LE_NONE = 0, - cbBM_DISCOVERABLE_MODE_LE_LIMITED = 1, - cbBM_DISCOVERABLE_MODE_LE_GENERAL = 2, -} cbBM_DiscoverableModeLe; - -typedef enum -{ - cbBM_CONNECTABLE_MODE_LE_NOT_CONNECTABLE = 0, - cbBM_CONNECTABLE_MODE_LE_CONNECTABLE -} cbBM_ConnectableModeLe; - -typedef enum -{ - cbBM_SET_CHANNEL_MAP_CNF_POS, - cbBM_SET_CHANNEL_MAP_CNF_NEG, -} cbBM_ChannelMapEvt; - -typedef void (*cbBM_ChannelMapCallb)( - cbBM_ChannelMapEvt chMapEvt, - TChannelMap *pChMap); // Channel map bit mask - -typedef void (*cbBM_InitComplete)(void); -typedef void(*cbBM_LocalAddressCb)(void); - -typedef enum -{ - cbBM_LE_ROLE_DISABLED = 0, - cbBM_LE_ROLE_CENTRAL = 1, - cbBM_LE_ROLE_PERIPHERAL = 2, -} cbBM_LeRole; - -/** - * Bluetooth Manager initialization parameters. - */ -typedef struct -{ - TBdAddr address; /** Bluetooth address that shall be assigned to controller. Pass invalidBdAddress to use controller default address*/ - cbBM_LeRole leRole; /** Bluetooth low energy role */ - cb_int8 maxOutputPower; /** Maximum output power. */ - cb_int32 nvdsStartIdLinkKeysClassic; /** Start id for CLASSIC link keys storage in NVDS. */ - cb_int32 maxLinkKeysClassic; /** Max number of CLASSIC link keys */ - cb_int32 nvdsStartIdLinkKeysLe; /** Start id for BLE link keys storage in NVDS. */ - cb_int32 maxLinkKeysLe; /** Max number of link keys BLE*/ -} cbBM_InitParams; - -typedef void(*cbBM_ServiceEnabled)(cb_uint8 serviceChannel); -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Initialize the Bluetooth Radio, the connectBlue Embedded Bluetooth - * Stack and the Bluetooth Manager. - * The init complete callback is used to notify when the initialization is - * complete. During initialization default values are set for all properties. - * The application shall set desired values for the main Bluetooth properties - * such as local name after the initialization is complete. After init the device - * is non discoverable and non connectable. - * - * @param pInitParameters Init parameters - * @param initCompleteCallback Callback used to notify when the initialization is complete. - * @param pBtReadyCallback Callback used to notify when the customized Bluetooth - * initialization is ready. - * @return None - */ -extern void cbBM_init( - cbBM_InitParams *pInitParameters, - cbBM_InitComplete initCompleteCallback); - -/** - * This function executes cbBM_setQosParams command according to parameters. - * @param connectConfig decides whether to turn off connectability and discoverability - * when max links are reached. - * @param qosConfig QoS enable=1, disable=0 - * @param connectConfig QoS "off during connection"=0, "on during connection"=1 - * @return true if in parameters are valid. - */ -extern cb_int32 cbBM_setQosParams( - cb_uint8 qosConfig, - cb_uint8 connectConfig); - -/** - * This function sets the link supervision timeout in LLC. - * @param linkSupervisionTimeout in milliseconds - * @return true if in parameter is valid. - */ -extern cb_int32 cbBM_setLinkSupervisionTimeout( - cb_uint16 linkSupervisionTimeout); - -/** - * This function gets the link supervision timeout from LLC. - * @return link supervision timeout in milliseconds - */ -extern cb_uint16 cbBM_getLinkSupervisionTimeout(void); - -/** - * This function enables or disables the fast connect feature (interlaced page scan). - * @param fastConnect enable=TRUE, disable=FALSE - * @return cbBM_OK if in parameter is valid. - */ -extern cb_int32 cbBM_setFastConnect( - cb_boolean fastConnect); -/** - * This function gets whether the fast connect feature is enabled or disabled. - * @return fast connect; enabled=TRUE, disabled=FALSE - */ -extern cb_boolean cbBM_getFastConnect(void); - -/** - * This function enables or disables the fast discovery feature (interlaced inquiry scan). - * @param fastDiscovery enable=TRUE, disable=FALSE - * @return cbBM_OK if in parameter is valid. - */ -extern cb_int32 cbBM_setFastDiscovery( - cb_boolean fastDiscovery); - -/** - * This function gets whether the fast discovery feature is enabled or disabled. - * @return fast connect enabled=TRUE, disabled=FALSE - */ -extern cb_boolean cbBM_getFastDiscovery(void); - -/** - * This function sets the page timeout in LLC. - * @param pageTimeout in milliseconds - * @return cbBM_OK if successful - */ -extern cb_int32 cbBM_setPageTimeout( - cb_uint16 pageTimeout); - -/** - * This function gets the page timeout from LLC. - * @return page timeout in milliseconds. - */ -extern cb_uint16 cbBM_getPageTimeout(void); - -/** - * This function sets all default parameters for LE. - * This function needs to be called before the cbBM_init. - */ -extern void cbBM_setDefaultValuesLeParams(void); - -/** - * This function executes HCI_cmdWrScanEnable command according to parameters. - * @param discoverableMode discoverable mode - * @param connectableMode connectable mode - * @return cbBM_OK if HCI command could be executed. - */ -extern cb_int32 cbBM_updateScan( - cbBM_DiscoverableMode discoverableMode, - cbBM_ConnectableMode connectableMode); - -/** - * Get the current Bluetooth address of the device from radio. This can - * be a way to get a alive-message from the radio. Also, if the radio resets, - * the address is set to a chip default value. - * - * @param callback to application when address has been read. - */ -extern void cbBM_checkRadioAlive(cbBM_LocalAddressCb callback); - -/** - * Get the current Bluetooth address of the device. - * @param pAddress Pointer to return variable. - * @return if the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_getLocalAddress(TBdAddr *pAddress); - -/** - * Set local name - * This sets the Bluetooth Classic device name as well as the Bluetooth Low - * Energy device name. Inquiry and advertising is updated. - * @param pName The new local name (null terminated string). Max length is 32 chars. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_setLocalName(cb_char* pName); - -/** - * Get local name. - * Get the current local name. - * @param pName Pointer to return variable. - * @param length Max length of the name string. Name will be truncated if length is too small. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_getLocalName( - cb_char *pName, - cb_uint32 length); - -/** - * Set class of device - * @param cod New Class of Device. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_setCod(TCod cod); - -/** - * Get current class of device. - * @param pCod Pointer to return variable. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_getCod(TCod* pCod); - -/** - * Set discoverable mode for Bluetooth Classic. - * @param discoverable New discoverable mode. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_setDiscoverableMode(cbBM_DiscoverableMode discoverable); - -/** - * Get current discoverable mode for Bluetooth Classic. - * @param pDiscoverable Pointer to return variable. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_getDiscoverableMode(cbBM_DiscoverableMode *pDiscoverable); - -/** - * Set connectable mode for Bluetooth Classic. - * @param connectable Connectable mode - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_setConnectableMode(cbBM_ConnectableMode connectable); - -/** - * Get current connectable mode for Bluetooth Classic - * @param pConnectable Pointer to return variable. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_getConnectableMode(cbBM_ConnectableMode *pConnectable); - -/** - * Set master slave policy for Bluetooth Classic - * @param policy Master slave policy - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_setMasterSlavePolicy(TMasterSlavePolicy policy); - -/** - * Set master slave policy for Bluetooth Classic - * @param pPolicy Pointer to return variable - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_getMasterSlavePolicy(TMasterSlavePolicy *pPolicy); - -/** - * Enable/disable sniff mode - * @param enable TRUE=enable sniff mode, FALSE=disable sniff mode - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_setSniffMode(cb_boolean enable); - -/** - * Get sniff mode - * @param pEnable Pointer to return variable - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_getSniffMode(cb_boolean *pEnable); - -/** - * Set default channel map for Bluetooth Classic. Used to exclude channels - * from usage. - * Request an update of which channels shall be used by adaptive frequency hopping. - * typically this is not needed since the Bluetooth is very good at select which - * channels to use. - * @param channelMap Channel map bit mask. Note that at least 20 channels must be enabled. - * @param channelMapCallback Callback used to notify if the channel map - * is accepted by the radio. - * @return If the operation is successfully initiated cbBM_OK is returned. - */ -extern cb_int32 cbBM_setAfhChannelMap( - TChannelMap channelMap, - cbBM_ChannelMapCallb channelMapCallback); - -/** - * Get the default channel map. - * @param pMap Pointer to return variable where the channel map bit mask is stored. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_getAfhChannelMap(TChannelMap *pMap); - -/** - * Start an Bluetooth inquiry. - * The event callback is called for every device that is found during inquiry. - * @param type Type of inquiry. - * @param inquiryLengthInMs Length of inquiry in ms - * @param eventCallback Callback used to notify each found device - * @param completeCallback Callback used to notify when the inquiry is completed - * @return If the inquiry is successfully started cbBM_OK is returned - */ -extern cb_int32 cbBM_inquiry( - cbBM_InquiryType type, - cb_uint32 inquiryLengthInMs, - cbBM_InquiryEventCallback eventCallback, - cbBM_InquiryCompleteCallback completeCallback); - -/** - * Cancel an ongoing inquiry. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_inquiryCancel(void); - -/** - * Perform a remote name request for Bluetooth Classic. - * @param pAddress Pointer to address of remote device. - * @param clockOffset Clock offset. Can be found in inquiry response. Use 0 if not available. - * @param pageTimeout Page timeout in ms (Length of connection attempt). - * @param remoteNameCallb Callback used to notify the completion of the - * name request. - * @return If the operation is successfully initiated cbBM_OK is returned. - */ -extern cb_int32 cbBM_remoteName( - TBdAddr *pAddress, - cb_uint16 clockOffset, - cb_uint16 pageTimeout, - cbBM_RemoteNameCallback remoteNameCallb); - -/** - * Add service class to inquiry response data. Typically - * not used by the application. - * @param uuid16 The UUID to add. E.g. 0x1101=SPP, 0x1115=PANU, 0x1116=NAP - * @param pCallback callback to indicate service is enabled - * @param serviceChannel channel the service is started on - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_addServiceClass(cb_uint16 uuid16, cbBM_ServiceEnabled pCallback,cb_uint8 serviceChannel); - -/** - * Check if service class is already registered. - * @param uuid16 The UUID to check. E.g. 0x1101=SPP, 0x1115=PANU, 0x1116=NAP - * @return TRUE If the ServiceClass is registered, FALSE otherwise. - */ -cb_boolean cbBM_isServiceClassRegistered(cb_uint16 uuid16 ); - -/** - * Add service class to inquiry response data. Typically - * not used by the application. - * @param uuid128 The UUID to add. - * @param pCallback callback to indicate service is enabled. - * @param serviceChannel channel the service is started on. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_add128BitsServiceClass(cb_uint8* uuid128, cbBM_ServiceEnabled pCallback, cb_uint8 serviceChannel); - -/** - * Set maximum Bluetooth Classic ACL links the stack - * shall allow. - * @param maxConnections Max ACL connections. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_setMaxConnections(cb_uint32 maxConnections); - -/** - * Get controller version string. - * @return Pointer to NULL terminated version string. - */ -extern cb_char* cbBM_getControllerVersionString(void); - -/** - * Get stack version string. - * @return Pointer to NULL terminated version string. - */ -extern cb_char* cbBM_getStackVersionString(void); - -/** - * Get current Bluetooth Low Energy Role. - * @return Current Bluetooth Low Energy role. - */ -extern cbBM_LeRole cbBM_getLeRole(void); - -/** - * Set Bluetooth Low Energy discoverable mode. - * Only valid for peripheral role. - * @param discoverableMode Bluetooth Low Energy discoverable mode - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setDiscoverableModeLe( - cbBM_DiscoverableModeLe discoverableMode); - -/** - * Get Bluetooth Low Energy discoverable mode. - * @param pDiscoverableMode Pointer to return variable - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_getDiscoverableModeLe( - cbBM_DiscoverableModeLe *pDiscoverableMode); - -/** - * Set Bluetooth Low Energy connectable mode. - * Only valid for peripheral role. - * @param connectable Set to TRUE to accept connections - * Set to FALSE to reject incoming connections - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setConnectableModeLe( - cbBM_ConnectableModeLe connectable); - -/** - * Get current connectable mode. - * @param pConnectable Pointer to return variable. - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_getConnectableModeLe( - cbBM_ConnectableModeLe* pConnectable); - -/** - * Set custom advertising data. - * Only valid for peripheral role. - * @param pAdvData Pointer to advertising data. - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setCustomAdvData( - TAdvData* pAdvData); - -/** - * Set custom scan response data. - * Only valid for peripheral role. - * @param pScanRspData Pointer to scan response data. - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setCustomScanRspData( - TAdvData* pScanRspData); - -/** - * Set current scan response data. - * Only valid for peripheral role. - * @param pAdvData Pointer to scan response data. - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_getAdvData( - TAdvData* pAdvData); - -/** - * Get current scan response data. - * Only valid for peripheral role. - * @param pScanRspData Pointer to scan response data. - * @return cbBM_OK is returned on success. - */ - extern cb_int32 cbBM_getScanRspData( - TAdvData* pScanRspData); - -/** - * Start an Bluetooth Low Energy device discovery. - * The event callback is called for every device that is found during inquiry. - * @param type Type of discovery. - * @param discoveryLength Length of inquiry in seconds. - * @param scanType Active or passive scan - * @param eventCallback Callback used to notify each found device - * @param completeCallback Callback used to notify when the inquiry is completed. - * @return If the device discovery is successfully started cbBM_OK is returned. - */ -extern cb_int32 cbBM_deviceDiscoveryLe( - cbBM_DeviceDiscoveryTypeLe type, - cb_uint16 discoveryLength, - cbBM_ScanTypeLe scanType, - cbBM_DeviceDiscoveryLeEventCallback eventCallback, - cbBM_DeviceDiscoveryLeCompleteCallback completeCallback); - -/** - * Cancel an ongoing device discovery. - * @return If the operation is successful cbBM_OK is returned. - */ -extern cb_int32 cbBM_deviceDiscoveryLeCancel(void); - -/** - * Perform a remote name request for Bluetooth Low Energy. - * @param pAddress Pointer to address of remote device. - * @param remoteNameCallback Callback used to notify the completion of the - * name request. - * @return If the operation is successfully initiated cbBM_OK is returned. - */ -extern cb_int32 cbBM_remoteNameLe(TBdAddr *pAddress, - cbBM_RemoteNameCallback remoteNameCallback); - - - -/* - * Add 128bit service UUID to scan response data. Typically - * not used by the application. - * @param uuid128 Pointer to 128bit UUID - * @return If the operation is successfully initiated cbBM_OK is returned. - */ -extern cb_int32 cbBM_add128BitsServiceClassLe(cb_uint8* uuid128); - -/* - * Read the used max tx power . - * @return max tx power level in dBm. - */ -extern cb_int8 cbBM_getMaxTxPower(void); - -/* - * Read the connection parameters for Bond. - * @param bondParams Pointer to structure where the connection parameters are stored. - * @return void - */ -void cbBM_getBondParameters(TAclParamsLe* bondParams); - -/* - * Read the connection parameters for connection. - * @param aclParams Pointer to structure where the connection parameters are stored. - * @return void - */ -void cbBM_getConnectParameters(TAclParamsLe* aclParams); - -/* - * Read the connection parameters for remote name request. - * @param aclParams Pointer to structure where the connection parameters are stored. - * @return void - */ -void cbBM_getRemoteNameReqParameters(TAclParamsLe* aclParams); - -/* - * Read the vendor specific status of the WL18 chipset. - * @param callback Callback used to notify the completion of the - * status request. - * @return Returns cbBM_OK if successfully started. - */ -cb_int32 cbBM_getTISystemStatus(cbBM_TIStatusCallback callback); - -/* - * Set BT classic as not supported in the peripheral advertisment. - * @param enforceDisable TRUE to set BT classic not supported - * @return cbBM_OK if successful - */ -cb_int32 cbBM_setForceClassicNotSupportedInAdv(cb_boolean enforceDisable); - -/* - * Set BT classic as not supported in the peripheral advertisment. - * - * @return TRUE if BT classic is set to not supported in the peripheral advertisment. - */ -cb_boolean cbBM_getForceClassicNotSupportedInAdv(void); - -/** - * Set min advertisment interval - * - * @param newValue Minimial interval value as slots (1 slot is 0.625ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setAdvertisingIntervalMin(cb_uint16 val); - -/** - * Set max advertisment interval - * - * @param newValue Time in slots (1 slot is 0.625ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setAdvertisingIntervalMax(cb_uint16 newValue); - -/** - * Set advertisment channel map - * - * @param Bit mask of channels to use; Channel 37, 38, 39 - * (cbBM_ADV_CHANNEL_MAP_CH_37_BIT, cbBM_ADV_CHANNEL_MAP_CH_38_BIT, cbBM_ADV_CHANNEL_MAP_CH_39_BIT) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setAdvChannelmap(cb_uint16 newValue); - -/** - * Set min connection interval - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setConnectConnIntervalMin(cb_uint16 newValue); - -/** - * Set max connection interval - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setConnectConnIntervalMax(cb_uint16 newValue); - -/** - * Set connection latency - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setConnectConnLatency(cb_uint16 newValue); - -/** - * Set link loss (or supervision) timeout - * - * @param newValue Time in ms (make sure it is larger than the connection latency) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setConnectLinklossTmo(cb_uint16 newValue); - -/** - * Set create connection (or page) timeout - * - * @param newValue Time in ms - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setConnectCreateConnTmo(cb_uint16 newValue); - -/** - * Set connect scan interval - * - * @param newValue Time in slots (1 slot is 0.625ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setConnectScanInterval(cb_uint16 newValue); - -/** - * Set connect scan window - * - * @param newValue Time in slots (1 slot is 0.625ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setConnectScanWindow(cb_uint16 newValue); - -/** - * Set min bond connection interval - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setBondConnIntervalMin(cb_uint16 newValue); - -/** - * Set max bond connection interval - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setBondConnIntervalMax(cb_uint16 newValue); - -/** - * Set bond connection latency - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setBondConnLatency(cb_uint16 newValue); - -/** - * Set bond link loss (or supervision) timeout - * - * @param newValue Time in ms (make sure it is larger than the connection latency) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setBondLinklossTmo(cb_uint16 newValue); - -/** - * Set bond create connection (or page) timeout - * - * @param newValue Time in ms - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setBondCreateConnTmo(cb_uint16 newValue); - -/** - * Set bond scan interval - * - * @param newValue Time in slots (1 slot is 0.625ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setBondScanInterval(cb_uint16 newValue); - -/** - * Set bond scan window - * - * @param newValue Time in slots (1 slot is 0.625ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setBondScanWindow(cb_uint16 newValue); - -/** - * Set min remote name connection interval - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setRemoteNameConnIntervalMin(cb_uint16 newValue); - -/** - * Set max remote name connection interval - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setRemoteNameConnIntervalMax(cb_uint16 newValue); - -/** - * Set remote name connection latency - * - * @param newValue Time in slots (1 slot is 1.25ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setRemoteNameConnLatency(cb_uint16 newValue); - -/** - * Set remote name link loss (or supervision) timeout - * - * @param newValue Time in ms (make sure it is larger than the connection latency) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setRemoteNameLinklossTmo(cb_uint16 newValue); - -/** - * Set remote name create connection (or page) timeout - * - * @param newValue Time in ms - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setRemoteNameCreateConnTmo(cb_uint16 newValue); - -/** - * Set remote name scan interval - * - * @param newValue Time in slots (1 slot is 0.625ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setRemoteNameScanInterval(cb_uint16 newValue); - -/** - * Set remote name scan window - * - * @param newValue Time in slots (1 slot is 0.625ms) - * @return cbBM_OK is returned on success. - */ -extern cb_int32 cbBM_setRemoteNameScanWindow(cb_uint16 newValue); - -/** - * Get min advertisment interval - * - * @return Time in slots (1 slot is 0.625ms) - */ -extern cb_uint16 cbBM_getAdvertisingIntervalMin(void); - -/** - * Get max advertisment interval - * - * @return Time in slots (1 slot is 0.625ms) - */ -extern cb_uint16 cbBM_getAdvertisingIntervalMax(void); - -/** - * Get advertisment channel map - * - * @return Bit mask of channels to use; Channel 37, 38, 39 - * (cbBM_ADV_CHANNEL_MAP_CH_37_BIT, cbBM_ADV_CHANNEL_MAP_CH_38_BIT, cbBM_ADV_CHANNEL_MAP_CH_39_BIT) - */ -extern cb_uint16 cbBM_getAdvChannelmap(void); - -/** - * Get min connection interval - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getConnectConnIntervalMin(void); - -/** - * Get max connection interval - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getConnectConnIntervalMax(void); - -/** - * Get connection latency - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getConnectConnLatency(void); - -/** - * Get link loss (or supervision) timeout - * - * @return Time in ms - */ -extern cb_uint16 cbBM_getConnectLinklossTmo(void); - -/** - * Get create connection (or page) timeout - * - * @return Time in ms - */ -extern cb_uint16 cbBM_getConnectCreateConnTmo(void); - -/** - * Get connection scan interval - * - * @return Time in slots (1 slot is 0.625ms) - */ -extern cb_uint16 cbBM_getConnectScanInterval(void); - -/** - * Get connection scan window - * - * @return Time in slots (1 slot is 0.625ms) - */ -extern cb_uint16 cbBM_getConnectScanWindow(void); - -/** - * Get min bond connection interval - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getBondConnIntervalMin(void); - -/** - * Get bond connection interval - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getBondConnIntervalMax(void); - -/** - * Get bond connection latency - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getBondConnLatency(void); - -/** - * Get bond link loss (or supervision) timeout - * - * @return Time in ms - */ -extern cb_uint16 cbBM_getBondLinklossTmo(void); - -/** - * Get bond connection (or page) timeout - * - * @return Time in ms - */ -extern cb_uint16 cbBM_getBondCreateConnTmo(void); - -/** - * Get bond scan interval - * - * @return Time in slots (1 slot is 0.625ms) - */ -extern cb_uint16 cbBM_getBondScanInterval(void); - -/** - * Get bond scan window - * - * @return Time in slots (1 slot is 0.625ms) - */ -extern cb_uint16 cbBM_getBondScanWindow(void); - -/** - * Get min remote name connection interval - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getRemoteNameConnIntervalMin(void); - -/** - * Get max remote name connection interval - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getRemoteNameConnIntervalMax(void); - -/** - * Get remote name connection latency - * - * @return Time in slots (1 slot is 1.25ms) - */ -extern cb_uint16 cbBM_getRemoteNameConnLatency(void); - -/** - * Get remote name link loss (or supervision) timeout - * - * @return Time in ms - */ -extern cb_uint16 cbBM_getRemoteNameLinklossTmo(void); - -/** - * Get remote name connection (or page) timeout - * - * @return Time in ms - */ -extern cb_uint16 cbBM_getRemoteNameCreateConnTmo(void); - -/** - * Get remote name scan interval - * - * @return Time in slots (1 slot is 0.625ms) - */ -extern cb_uint16 cbBM_getRemoteNameScanInterval(void); - -/** - * Get remote name scan window - * - * @return Time in slots (1 slot is 0.625ms) - */ -extern cb_uint16 cbBM_getRemoteNameScanWindow(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h deleted file mode 100644 index 0a68d38dbec..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Bluetooth PAN Data Manager - * File : cb_bt_pan.h - * - * Description : Data management for PAN profile - * - *-------------------------------------------------------------------------*/ - -#ifndef _CB_BT_PAN_H_ -#define _CB_BT_PAN_H_ - -#include "cb_comdefs.h" -#include "bt_types.h" -#include "cb_bt_conn_man.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbBTPAN_RESULT_OK ((cb_int32)0x00000000) -#define cbBTPAN_RESULT_ERROR ((cb_int32)0x00000001) -#define cbBTPAN_RESULT_ILLEGAL_HANDLE ((cb_int32)0x00000002) -#define cbBTPAN_RESULT_FLOW_STOP ((cb_int32)0x00000003) -#define cbBTPAN_RESULT_LINK_LOSS ((cb_int32)0x00000004) - -/*=========================================================================== - * TYPES - *=========================================================================*/ -typedef cb_uint32 cbBTPAN_Handle; - -/*--------------------------------------------------------------------------- - * Callback to indicate that a Bnep connection has been established. - * - * @param connHandle: Connection handle - * @param info: Information about the connection - * - * @return None - *-------------------------------------------------------------------------*/ -typedef void(*cbBTPAN_ConnectEvt) (cbBCM_Handle connHandle, cbBCM_ConnectionInfo info); - -/*--------------------------------------------------------------------------- - * Callback to indicate that a Bnep connection has been disconnected. - * - * @param connHandle: Connection handle - * - * @return None - *-------------------------------------------------------------------------*/ -typedef void(*cbBTPAN_DisconnectEvt) (cbBCM_Handle connHandle); - -/*--------------------------------------------------------------------------- - * Callback to indicate that data has been received from remote device. -* - * @param btPanHandle: PAN handle - * @param length: Length of the data - * @param pData: Pointer to the data - * - * @return None - *-------------------------------------------------------------------------*/ -typedef void(*cbBTPAN_DataEvt) (cbBCM_Handle connHandle, cb_uint8 * pData, cb_uint16 length); - -/*--------------------------------------------------------------------------- - * Callback to indicate that data has been taken care by PAN. New - * data can now be sent on this handle. - * - * @param btPanHandle: PAN handle - * @param result: cbBTPAN_RESULT_OK if the data sending succeeded - * - * @return None - *-------------------------------------------------------------------------*/ -typedef void(*cbBTPAN_DataCnf) (cbBCM_Handle connHandle, cb_int32 result); - -typedef struct -{ - cbBTPAN_ConnectEvt pfConnectEvt; - cbBTPAN_DisconnectEvt pfDisconnectEvt; - cbBTPAN_DataEvt pfDataEvt; - cbBTPAN_DataCnf pfWriteCnf; -} cbBTPAN_Callback; - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ -/** - * Initialization of Bluetooth PAN data. Called during stack - * initialization. Shall not be called by application. - * - * @return None - */ -extern void cbBTPAN_init(void); - -/** - * Registers for PAN data callbacks. Only one registration is supported. - * - * @param pDataCallback Data callback - * - * @return cbBTPAN_RESULT_OK if successful - */ -extern cb_uint32 cbBTPAN_registerDataCallback(cbBTPAN_Callback * pDataCallback); - -/*--------------------------------------------------------------------------- - * Sends data to the remote device. Note that you have to wait for the - * confirmation callback (cbBTPAN_DataCnf) before calling another cbBTPAN_reqData. - * - * @param connHandle: Connection handle - * @param pBuf: Pointer to the data - * @param bufSize: Length of the data - * - * @return cbBTPAN_RESULT_OK if successful - *-------------------------------------------------------------------------*/ -extern cb_int32 cbBTPAN_reqData(cbBCM_Handle connHandle, cb_uint8 * pBuf, cb_uint16 bufSize); - -/*--------------------------------------------------------------------------- - * Gets the max frame size that can be sent/received with - * cbBTPAN_reqData/pfDataEvt - * - * @return max frame size - *-------------------------------------------------------------------------*/ -extern cb_int32 cbBTPAN_getMaxFrameSize(void); - -#ifdef __cplusplus -} -#endif - -#endif //_cb_BT_PAN_H_ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h deleted file mode 100644 index 38d92d41d61..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h +++ /dev/null @@ -1,387 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Bluetooth Security Manager - * File : cb_bt_sec_man.h - * - * Description : Bluetooth security application support - *-------------------------------------------------------------------------*/ - -/** - * @file cb_bt_sec_man.h - * @brief Bluetooth security application support. This includes bonding, - * security modes, passkey and pin code handling. - */ - -#ifndef _CB_BT_SEC_MAN_H_ -#define _CB_BT_SEC_MAN_H_ - -#include "cb_comdefs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbBSM_OK (0) -#define cbBSM_ERROR (-1) - -#define cbBSM_PASSKEY_MAX_VALUE (999999) - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -/** - * cbBSM_SECURITY_MODE_1_DISABLED - * Security disabled - * - Remote Device BT 2.1: Auto accept (No man-in-the-middle attack protection, encryption enabled) - * - Remote Device BT 2.0: Authentication and encryption disabled. - * - Bluetooth Low Energy: Auto accept (No man-in-the-middle attack protection, encryption enabled) - * - * cbBSM_SECURITY_MODE_2_BT_2_0 - * - Enforce BT 2.0 (Service level authentication and encryption enabled) - * Please note that the device is not BT 2.1 qualified for this setting. It is included for backward compatibility. Invalid for Bluetooth Low Energy. - * - * cbBSM_SECURITY_MODE_3_FIXED_PIN - * - Remote Device BT 2.1: Service level authentication and encryption enabled. - * - Remote Device BT 2.0: Service level authentication and encryption enabled. - * - Bluetooth Low Energy: Service level authentication and encryption enabled. - * Please note that this security mode will not work with a general BT 2.1 device. However, it will work between two connectBlue BT 2.1 Serial Port Adapters. Use security mode 4 to make the device work with a general BT 2.1 device. - * - * cbBSM_SECURITY_MODE_4_JUST_WORKS - * - Remote Device BT 2.1: Auto accept (no man-in-the-middle attack protection, encryption enabled) - * - Remote Device BT 2.0: Service level authentication and encryption enabled. - * - Bluetooth Low Energy: Auto accept (no man-in-the-middle attack protection, encryption enabled) - * This security mode is intended for pairing in safe environments. When this mode is set, pairability (see AT*AGPM) is automatically disabled. In data mode, pairing can be enabled for 60 seconds by pressing the "External Connect" button for at least 5 seconds. When the module is pairable, the LED will blink. If the mode is changed from Just Works to another, pairability must be enabled again using the AT*AGPM command. - * - * cbBSM_SECURITY_MODE_5_DISPLAY_ONLY - * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should be presented a passkey. - * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required. - * - Bluetooth Low Energy: Service level authentication and encryption enabled. User should be presented a passkey. - * This security mode is used when the device has a display that can present a 6-digit value that the user shall enter on the remote device. - * - * cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO - * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should compare two values. - * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required. - * This security mode is used when the device has a display that can present a 6-digit value that the user shall verify with yes or no to the remote device's presented value. - * Invalid for Bluetooth Low Energy. - * - * cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY - * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should enter a passkey. - * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required. - * - Bluetooth Low Energy: Service level authentication and encryption enabled. User should enter a passkey. - * This security mode is used when the device only has a keyboard where the user can enter a 6-digit value that is presented on the remote device. - */ -typedef enum -{ - cbBSM_SECURITY_MODE_1_DISABLED = 1, - cbBSM_SECURITY_MODE_2_BT_2_0, - cbBSM_SECURITY_MODE_3_FIXED_PIN, - cbBSM_SECURITY_MODE_4_JUST_WORKS, - cbBSM_SECURITY_MODE_5_DISPLAY_ONLY, - cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO, - cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY -} cbBSM_SecurityMode; - -typedef struct -{ - TPinCode pin; - cb_uint8 nBytes; -} cbBSM_PinCode; - -typedef enum -{ - cbBSM_BOND_TYPE_CLASSIC, - cbBSM_BOND_TYPE_LE, - cbBSM_BOND_TYPE_ALL, -} cbBSM_BondTypes; - -typedef enum -{ - cbBSM_BOND_STATUS_OK = 0, - cbBSM_BOND_STATUS_ERR_PAGE_TMO, - cbBSM_BOND_STATUS_ERR_AUTH_FAIL, - cbBSM_BOND_STATUS_ERR_NO_MITM -} cbBSM_BondStatus; - -/** - * Callback to indicate that bonding is finished. - * @param bdAddress Remote BD address - * @param bondStatus Bond status, e.g. cbBSM_BOND_STATUS_OK - * @return None - */ -typedef void (*cbBSM_BondCnf)( - cbBSM_BondStatus status, - TBdAddr* pBdAddress); - -/** - * Callback to indicate that a pin code is required from upper layer. - * Respond the pin code request with cbBSM_rspFixedPin/cbBSM_rspNegFixedPin - * This is only used when either local or remote side does not support - * BT 2.1 secure simple pairing. - * @param bdAddress Remote BD address - * @return None - */ -typedef void (*cbBSM_RequestPinInd)( - TBdAddr* pBdAddress); - -/** - * Callback to indicate that user confirmation is required. The user should - * compare numericValues on local and remote side and respond the confirmation - * request with cbBSM_rspUserConfirmation if values match and - * cbBSM_rspNegUserConfirmation if they do not match or user wants to interrupt - * the pairing attempt. - * This is only used when both sides support BT 2.1 secure simple pairing and - * security mode cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO is used. - * @param bdAddress Remote BD address - * @param numericValue The numeric value to be compared - * @return None - */ -typedef void (*cbBSM_UserConfirmationInd)( - TBdAddr* pBdAddress, - cb_uint32 numericValue); - -/** - * Callback to indicate that a passkey is required from upper layer. - * Respond the passkey request with cbBSM_rspUserPasskey/cbBSM_rspNegUserPasskey. - * This is only used when both sides support BT 2.1 secure simple pairing and - * security modes cbBSM_SECURITY_MODE_3_FIXED_PIN or cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY is used - * @param bdAddress Remote BD address - * @return None - */ -typedef void (*cbBSM_UserPasskeyInd)( - TBdAddr* pBdAddress); - -/** - * Callback to indicate that a passkey is used in the pairing procedure. - * The passkey should be displayed to the user. - * This is only used when both sides support BT 2.1 secure simple pairing and - * security mode cbBSM_SECURITY_MODE_5_DISPLAY_ONLY is used. - * @param bdAddress Remote BD address - * @param passkey Passkey - * @return None - */ -typedef void (*cbBSM_UserPasskeyEvt)( - TBdAddr* pBdAddress, - cb_uint32 passkey); - -typedef struct -{ - cbBSM_RequestPinInd requestPinInd; - cbBSM_UserConfirmationInd userConfirmationInd; - cbBSM_UserPasskeyInd userPasskeyInd; - cbBSM_UserPasskeyEvt userPasskeyEvt; - cbBSM_BondCnf bondConfirmation; - cbBSM_BondCnf bondEvent; -} cbBSM_Callbacks; - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Initialization of BLuetooth security manager. Called during stack - * initialization. Shall not be called by application. - * - * @return None - */ -extern void cbBSM_init(void); - -/** - * Register security callbacks. Callbacks in the struct that are not - * of any interest can be set to NULL. - * - * @param pPairingCallbacks Pointer to the security callback struct - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_registerCallbacks(cbBSM_Callbacks* pPairingCallbacks); - -/** - * Set security mode. See comments on cbBSM_SecurityMode for - * description of the different security modes. - * - * @param securityMode Security mode. Default security is cbBSM_SECURITY_MODE_1_DISABLED - * @param allowPairingInNonBondableMode Normally FALSE. Set to TRUE if pairing should be allowed when not bondable. - * No link keys will then be stored. - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_setSecurityMode( - cbBSM_SecurityMode securityMode, - cb_boolean allowPairingInNonBondableMode); - -/** - * Read current security mode. - * - * @param pSecurityMode Security mode - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_getSecurityMode(cbBSM_SecurityMode* pSecurityMode); - -/** - * Sets the local device pairable mode. - * - * @param pairable TRUE=pairable, FALSE=not pairable (default) - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_setPairable(boolean pairable); - -/** - * Gets the local device pairable mode. - * - * @param pPairable Pointer to return value - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_getPairable(boolean* pPairable); - -/** - * Performs bonding with a remote device. The cbBSM_BondCnf callback will - * be called upon success/failure. - * - * @param remoteDevice Remote BD address - * @param type Classic or LE - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_reqBond( - TBdAddr remoteDevice, - TBluetoothType type); - -/** - * Responds on the cbBSM_RequestPinInd callback with a pin code - * This is only used when either local or remote side does not support - * BT 2.1 secure simple pairing. - * - * @param pBdAddress Pointer to the remote BD address - * @param pinCodeLength Length of the provided pin code - * @param pPinCode Pointer to the provided pin code - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_rspFixedPin( - TBdAddr* pBdAddress, - cb_uint8 pinCodeLength, - cb_uint8 *pPinCode); - -/** - * Responds the cbBSM_RequestPinInd callback. Can be used to interrupt a - * pairing attempt from the remote device. - * This is only used when either local or remote side does not support - * BT 2.1 secure simple pairing. - * - * @param pBdAddress Pointer to the remote BD address - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_rspNegFixedPin(TBdAddr* pBdAddress); - -/** - * Responds on the cbBSM_UserPasskeyInd callback. - * This is only used when both sides support BT 2.1 secure simple pairing. - * - * @param pBdAddress Pointer to the remote BD address - * @param passkey Passkey, range: 0-999999 - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_rspUserPasskey( - TBdAddr *pBdAddress, - uint32 passkey); - -/** - * Responds on the cbBSM_UserPasskeyInd callback. Can be used to interrupt a - * pairing attempt from the remote device. - * This is only used when both sides support BT 2.1 secure simple pairing. - * - * @param pBdAddress Pointer to the remote BD address - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_rspNegUserPasskey(TBdAddr *pBdAddress); - -/** - * Responds on the cbBSM_UserConfirmationInd callback. Accepts the numeric value. - * This is only used when both sides support BT 2.1 secure simple pairing. - * - * @param pBdAddress Pointer to the remote BD address - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_rspUserConfirmation(TBdAddr* pBdAddress); - -/** - * Responds on the cbBSM_UserConfirmationInd callback. Rejects the numeric value. - * This is only used when both sides support BT 2.1 secure simple pairing. - * - * @param pBdAddress Pointer to the remote BD address - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_rspNegUserConfirmation(TBdAddr* pBdAddress); - -/** - * Get number of bonded devices. - * - * @param type Bond type - * @param pNo Pointer to return value. - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_getAllNumberBondedDevices( - cbBSM_BondTypes type, - uint32* pNo); - -/** -* Get a bonded devices. -* -* @param deviceIndex Index of the bonded device -* @param pBdAddr Pointer to remote BD address. -* @param pIsLe Should be TRUE for LE and FALSE for classic -* @return If the operation is successful cbBSM_OK is returned. -*/ -extern cb_int32 cbBSM_getBondedDevice( - cb_int32 deviceIndex, - TBdAddr* pBdAddr, - cb_boolean pIsLe); - -/** - * Delete a bonded device and its link keys. - * - * @param pBdAddress to the address of the device which bond shall be deleted. - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_deleteBondedDevice(TBdAddr* pBdAddress); - -/** - * Delete all bonded devices and link keys. - * - * @return If the operation is successful cbBSM_OK is returned. - */ -extern cb_int32 cbBSM_deleteAllBondedDevices(void); - -/** - * Initializes the static Link Keys for both classic and LE. - * nvdsId: nvds id for the static link key, - * (0) disables the use of a static link key. - * - * @return cbBSM_OK. - */ -cb_int32 cbBSM_setStaticLinkKeyNvdsId(cb_int32 nvdsId); - -#ifdef __cplusplus -} -#endif - -#endif /* _CB_BT_SEC_MAN_H_ */ - - - - - - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h deleted file mode 100644 index 8154684e127..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Bluetooth Serial - * File : cb_bt_serial.h - * - * Description : Data management for RFCOMM based profiles such and Serial - * Port Profile (SPP). - * - *-------------------------------------------------------------------------*/ - -/** - * @file cb_bt_serial.h - * @brief Data management for RFCOMM based profiles such and Serial - * Port Profile (SPP). - */ - -#ifndef _CB_BT_SERIAL_H_ -#define _CB_BT_SERIAL_H_ - -#include "cb_comdefs.h" -#include "bt_types.h" -#include "cb_bt_conn_man.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== -* DEFINES -*=========================================================================*/ -#define cbBSE_OK 0 -#define cbBSE_ERROR -1 -#define cbBSE_NO_DATA -2 - -/*=========================================================================== -* TYPES -*=========================================================================*/ - -typedef void (*cbBSE_DataAvailEvt)( - cbBCM_Handle handle); - -typedef void (*cbBSE_WriteCnf)( - cbBCM_Handle handle, - cb_int32 status, - cb_uint32 nBytes, - cb_int32 tag); - -typedef struct -{ - cbBSE_DataAvailEvt pfDataEvt; - cbBSE_WriteCnf pfWriteCnf; -} cbBSE_Callback; - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Initialization of Bluetooth serial manager. Called during stack - * initialization. Shall not be called by application. - * - * @return None - */ -extern void cbBSE_init(void); - -/** - * Open a data channel. - * - * @param handle Connection handle - * @param pCallback Callback for data events. - * @return If the operation is successful cbBSE_OK is returned. - */ -extern cb_int32 cbBSE_open( - cbBCM_Handle handle, - cbBSE_Callback *pCallback); - -/** - * Send data to remote device. A data confirmation event is generated when - * the data has been sent and a cbBSE_write call can be done. - * - * Detailed description optionally verbose. - * @param handle Connection handle - * @param pBuf Data pointer - * @param nBytes nBytes Size of data to be sent. - * @param tag Tag passed as argument in corresponding data confirmation callback. - * @return If the operation is successful cbBSE_OK is returned. - */ -extern cb_int32 cbBSE_write( - cbBCM_Handle handle, - cb_uint8 *pBuf, - cb_uint32 nBytes, - cb_int32 tag); - -/** - * Get received data. - * - * @param handle Connection handle - * @param ppBuf Pointer to data buffer - * @param pLength Pointer to buffer length variable. - * @return cbBSE_OK is returned if data is available. If no data is available - * then cbBSE_NO_DATA is returned. - */ -extern cb_int32 cbBSE_getReadBuf( - cbBCM_Handle handle, - cb_uint8 **ppBuf, - cb_uint32 *pLength); - -/** - * Notify that received data has been handled and underlying buffers - * can be freed. - * - * @param handle Connection handle - * @param nBytes Number of bytes consumed. - * @return If the operation is successful cbBSE_OK is returned. - */ -extern cb_int32 cbBSE_readBufConsumed( - cbBCM_Handle handle, - cb_uint32 nBytes); - -/** - * Read max frame size for a data channel. - * - * @param handle Connection handle - * @param pFrameSize Max frame size for connection. - * @return If the operation is successful cbBSE_OK is returned. - */ -extern cb_int32 cbBSE_frameSize(cbBCM_Handle handle, cb_uint32 *pFrameSize); - -/** - * Bluetooth serial message handling. Shall not be called by application. - * - * @param msgId Message id - * @param pData Pointer to message data - * @return None - */ -extern void cbBSE_handleMsg(cb_uint32 msgId, void* pData); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h deleted file mode 100644 index 695466cc4fe..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h +++ /dev/null @@ -1,154 +0,0 @@ -/** - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Bluetooth Serial - * File : cb_bt_serial_le.h - * - * Description : Data management for Serial Port Service. - * - *-------------------------------------------------------------------------*/ - -/** - * @file cb_bt_serial_le.h - * @brief Data management for Serial Port Service. - */ - -#ifndef _CB_BT_SERIAL_LE_H_ -#define _CB_BT_SERIAL_LE_H_ - -#include "cb_comdefs.h" -#include "bt_types.h" -#include "cb_bt_conn_man.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== -* DEFINES -*=========================================================================*/ -#define cbBSL_OK 0 -#define cbBSL_ERROR -1 -#define cbBSL_NO_DATA -2 - -/*=========================================================================== -* TYPES -*=========================================================================*/ - -typedef void (*cbBSL_DataAvailEvt)( - cbBCM_Handle handle); - -typedef void (*cbBSL_WriteCnf)( - cbBCM_Handle handle, - cb_int32 status, - cb_uint32 nBytes, - cb_int32 tag); - -typedef struct -{ - cbBSL_DataAvailEvt pfDataEvt; - cbBSL_WriteCnf pfWriteCnf; -} cbBSL_Callback; - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Initialization of Bluetooth serial manager. Called during stack - * initialization. Shall not be called by application. - * - * @return None - */ -extern void cbBSL_init(void); - -/** - * Open a data channel. - * - * @param handle Connection handle - * @param pCallback Callback for data events. - * @return If the operation is successful cbBSL_OK is returned. - */ -extern cb_int32 cbBSL_open( - cbBCM_Handle handle, - cbBSL_Callback *pCallback); - -/** - * Send data to remote device. A data confirmation event is generated when - * the data has been sent and a cbBSL_write call can be done. - * - * Detailed description optionally verbose. - * @param handle Connection handle - * @param pBuf Data pointer - * @param nBytes nBytes Size of data to be sent. - * @param tag Tag passed as argument in corresponding data confirmation callback. - * @return If the operation is successful cbBSL_OK is returned. - */ -extern cb_int32 cbBSL_write( - cbBCM_Handle handle, - cb_uint8 *pBuf, - cb_uint32 nBytes, - cb_int32 tag); - -/** - * Get received data. - * - * @param handle Connection handle - * @param ppBuf Pointer to data buffer - * @param pLength Pointer to buffer length variable. - * @return cbBSL_OK is returned if data is available. If no data is available - * then cbBSL_NO_DATA is returned. - */ -extern cb_int32 cbBSL_getReadBuf( - cbBCM_Handle handle, - cb_uint8 **ppBuf, - cb_uint32 *pLength); - -/** - * Notify that received data has been handled and underlying buffers - * can be freed. - * - * @param handle Connection handle - * @param nBytes Number of bytes consumed. - * @return If the operation is successful cbBSL_OK is returned. - */ -extern cb_int32 cbBSL_readBufConsumed( - cbBCM_Handle handle, - cb_uint32 nBytes); - -/** - * Read max frame size for a data channel. - * - * @param handle Connection handle - * @param pFrameSize Max frame size for connection. - * @return If the operation is successful cbBSE_OK is returned. - */ -extern cb_int32 cbBSL_frameSize(cbBCM_Handle handle, cb_uint32 *pFrameSize); - -/** - * Bluetooth serial message handling. Shall not be called by application. - * - * @param msgId Message id - * @param pData Pointer to message data - * @return None - */ -extern void cbBSL_handleMsg(cb_uint32 msgId, void* pData); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h deleted file mode 100644 index aa2f149da6e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h +++ /dev/null @@ -1,253 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Bluetooth Test - * File : cb_bt_test_man.h - * - * Description : Functionality for Bluetooth radio tests and qualification. - *-------------------------------------------------------------------------*/ - -/** -* @file cb_bt_test_man.h -* @brief Functionality for Bluetooth radio tests and qualification. - */ - -#ifndef _CB_BT_TEST_MAN_H_ -#define _CB_BT_TEST_MAN_H_ - -#include "cb_comdefs.h" - -#include "cb_bt_man.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbBTM_OK (0) -#define cbBTM_ERROR (-1) - -/*=========================================================================== - * TYPES - *=========================================================================*/ -typedef enum -{ - cbBTM_TEST_CONF_POS, - cbBTM_TEST_CONF_NEG -} cbBTM_TestEvt; - -typedef void (*cbBTM_TestCallback)(cbBTM_TestEvt evt); -typedef void (*cbBTM_LeTestEndCallback)(cbBTM_TestEvt evt, cb_uint16 nbrOfPackets); - - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Init Bluetooth test manager - * @returns None - */ -extern void cbBTM_init(void); - -/** - * Enable Device under test mode. Used for Bluetooth Classic radio tests. - * - * @param callback Test callback used to notify if the test was successfully started. - * @returns cbBTM_OK is returned - */ -extern cb_int32 cbBTM_enableDUT(cbBTM_TestCallback callback); - -/** - * This command operates the RF transceiver in continuous transmission mode (which is most likely used in - * regulatory and standardization procedures and tests, such as FCC and ETSI certifications). Activating the - * VS runs the TX START sequence code using the configured frequency, modulation, pattern, and power - * level. The VS also enables the generation of a user-defined pattern (or correcting definitions without a - * patch) by setting a new pattern generator (also known as a PN generator) init value and mask. - * based on HCI_VS_DRPb_Tester_Con_TX, HCI Opcode 0xFDCA - * The cbBTM_TestCallback is used to notify if the test is sucessfully started. - * - * @param frequency Transmission frequency in MHz Range: 2402 - 2480 - * @param modulationScheme Range: 0x00 - 0x05 where - * 0x00 = CW - * 0x01 = BT BR (GFSK) - * 0x02 = BT EDR 2MB (p/4-DQPSK) - * 0x03 = BT EDR 3MB (8-DPSK) - * 0x04 = BT LE (BLE, GMSK) - * 0x05 = ANT (GFSK) - * @param testPattern Range: 0x00 - 0x07 - * 0x00 = PN9 - * 0x01 = PN15 - * 0x02 = ZOZO (101010101010101010) - * 0x03 = All 1 - * 0x04 = All 0 - * 0x05 = FOFO (1111000011110000) - * 0x06 = FFOO (1111111100000000) - * 0x07 = Not used - * @param powerLevelIndex Range: 0-7: 7 = Max Output Power, 0 = Min Output Power, 0x08 (PA off) 8 = PA Off (leakage) - * @param reserved1 shall be set to 0 - * @param reserved2 shall be set to 0 - * @param callback Test callback used to notify if the test was successfully started. - * - * @return cbBTM_OK is returned - */ -extern cb_int32 cbBTM_tiDrpbTesterConTx( - cb_uint16 frequency, - cb_uint8 modulationScheme, - cb_uint8 testPattern, - cb_uint8 powerLevelIndex, - cb_uint32 reserved1, - cb_uint32 reserved2, - cbBTM_TestCallback callback); - -/** - *This command operates the RF transceiver in continuous reception mode (most likely used in regulatory - * and standardization procedures and tests, such as FCC and ETSI certifications). By activating the VS, the - * RX START sequence code runs, using the configured frequency, RX mode, and modulation type. - * based on HCI_VS_DRPb_Tester_Con_RX, HCI Opcode 0xFDCB - * - * The cbBTM_TestCallback is used to notify if the test is successfully started. - * @param frequency Transmission frequency in MHz Range: 2402 - 2480 - * @param rxMode Range: 0 -3: - * 0x00 = Connection mode - * 0x01 = Best RF mode (ADPL closed loop) - For expert use only! - * 0x02 = Low current mode (ADPLL open loop) - For expert use only! - * 0x03 = Scan mode - * @param modulationScheme Range: 0x03 - 0x05 where - * 0x03 = BT (BR, EDR 2MB, EDR 3MB) - * 0x04 = BT LE (BLE, GMSK) - * 0x05 = ANT (GFSK) - * @param callback Test callback used to notify if the test was successfully started. - * - * @return cbBTM_OK is returned - */ -extern cb_int32 cbBTM_tiDrpbTesterConRx( - cb_uint16 frequency, - cb_uint8 rxMode, - cb_uint8 modulationScheme, - cbBTM_TestCallback callback); - -/** - * - * This command operates the RF transceiver in continuous reception mode (most likely used in regulatory - * and standardization procedures and tests, such as FCC and ETSI certifications). Activating the VS runs - * the RX START sequence code using the configured frequency, RX mode, and modulation type. - * This command emulates Bluetooth connection mode. Connection does not require a setup procedure. - * Based on HCI_VS_DRPb_Tester_Packet_TX_RX HCI Opcode 0xFDCC - * - * @param aclPacketType ACL TX packet type. Range: 0x00 - 0x0B - * 0x00 = DM1 - * 0x01 = DH1 - * 0x02 = DM3 - * 0x03 = DH3 - * 0x04 = DM5 - * 0x05 = DH5 - * 0x06 = 2-DH1 - * 0x07 = 2-DH3 - * 0x08 = 2-DH5 - * 0x09 = 3-DH1 - * 0x0A = 3-DH3 - * 0x0B = 3-DH5 - * @param frequencyMode 0x00 = Hopping 0x03 = Single frequency - * @param txSingleFrequency Transmission frequency in MHz,Range 2402 - 2480, 0xFFFF = no TX - * @param rxSingleFrequency Transmission frequency in MHz,Range 2402 - 2480, 0xFFFF = no RX - * @param aclDataPattern ACL TX packet data pattern Range: 0x00 - 0x05 - * 0x00 = All 0 - * 0x01 = All 1 - * 0x02 = ZOZO (101010101010101010) - * 0x03 = FOFO (1111000011110000) - * 0x04 = Ordered (1, 2, 3, 4, and so on) - * 0x05 = PRBS9 (pseudo-random bit sequence) - * @param useExtendedFeatures Shall be SET to 0 - * @param aclDataLength ACL packet data length. - * DM1: 0 - 17 ACL packet data length in bytes - * DH1: 0 - 27 - * DM3: 0 - 121 - * DH3: 0 - 183 - * DM5: 0 - 224 - * DH5: 0 - 339 - * 2-DH1: 0 - 54 - * 2-DH3: 0 - 367 - * 2-DH5: 0 - 679 - * 3-DH1: 0 - 83 - * 3-DH3: 0 - 552 - * 3-DH5: 0 - 1021 - * @param powerLevel Range 0-7: 7 = Max Output Power; 0 = Min Output; Power 8 = PA Off (leakage) 0x08 (PA off) - * @param disableWhitening 0x00 = Enable whitening, 0x01 = Disable whitening - * @param prbs9Init PRBS9 Init, range 0x0000 - 0x01FF - * @param callback Test callback used to notify if the test was successfully started. - * - * @return cbBTM_OK is returned - */ -extern cb_int32 cbBTM_tiDrpbTesterPacketTxRx( - cb_uint8 aclPacketType, - cb_uint8 frequencyMode, - cb_uint16 txSingleFrequency, - cb_uint16 rxSingleFrequency, - cb_uint8 aclDataPattern, - cb_uint8 useExtendedFeatures, - cb_uint16 aclDataLength, - cb_uint8 powerLevel, - cb_uint8 disableWhitening, - cb_uint16 prbs9Init, - cbBTM_TestCallback callback); - -/** - * Enable Bluetooth Low Energy Transmitter test. - * @param txFreq Transmit frequency. N = (F - 2402) / 2, Range: 0x00 to 0x27, Frequency Range : 2402 MHz to 2480 MHz, - Use oxFF to generate a pseudo random hopping frequency useful for some scenarios during type approval. - * @param length Length in bytes of payload data in each packet - * @param packetPayload 0x00 Pseudo-Random bit sequence 9 - * 0x01 Pattern of alternating bits 11110000 - * 0x02 Pattern of alternating bits 10101010 - * 0x03 Pseudo-Random bit sequence 15 - * 0x04 Pattern of All 1 bits - * 0x05 Pattern of All 0 bits - * 0x06 Pattern of alternating bits 00001111 - * 0x07 Pattern of alternating bits 0101 - * @param callback Test callback used to notify if the test was successfully started. - * @return cbBTM_OK is returned - */ -extern cb_int32 cbBTM_enableBleTransmitterTest( - cb_uint8 txFreq, - cb_uint8 length, - cb_uint8 packetPayload, - cbBTM_TestCallback callback); - -/** - * Enable Bluetooth Low Energy Receiver test. - * @param rxFreq Receive frequency. N = (F - 2402) / 2, Range: 0x00 to 0x27, Frequency Range : 2402 MHz to 2480 MHz, - * @param callback Test callback used to notify if the test was successfully started. - * @returns cbBTM_OK is returned - */ -extern cb_int32 cbBTM_enableBleReceiverTest( - cb_uint8 rxFreq, - cbBTM_TestCallback callback); - -/** - * End Bluetooth Low Energy Receiver or Transmitter test. - * @param callback Test callback used to notify if the test was successfully ended. - * @returns cbBTM_OK is returned - */ -extern cb_int32 cbBTM_bleTestEnd(cbBTM_LeTestEndCallback callback); - -#ifdef __cplusplus -} -#endif - -#endif /* _CB_BT_TEST_MAN_H_ */ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h deleted file mode 100644 index 255a4c056f7..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h +++ /dev/null @@ -1,86 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Bluetooth utility - * File : cb_bt_utils.h - * - * Description : - *-------------------------------------------------------------------------*/ - -#ifndef _CB_BT_UTILS_H_ -#define _CB_BT_UTILS_H_ - -#include "cb_comdefs.h" -#include "bt_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * FUNCTIONS - *========================================================================= - */ - -/** - * Compare two Bluetooth addresses - * - * @param addr1 Pointer to first address to compare - * @param addr2 Pointer to second address to compare - * @returns TRUE if equal otherwise FALSE - */ -extern cb_boolean cbBT_UTILS_cmpBdAddr( - TBdAddr* addr1, - TBdAddr* addr2); - -/** - * Check if address in invalid i.e. {{0,0,0,0,0,0},BT_PUBLIC_ADDRESS} - * - * @param addr Pointer to address to check - * @returns TRUE if invalid otherwise FALSE - */ -extern cb_boolean cbBT_UTILS_isInvalidBdAddr( - TBdAddr* addr); - -/** - * Set invalid address i.e. {{0,0,0,0,0,0},BT_PUBLIC_ADDRESS} - * - * @param addr Pointer where to put the address - */ -extern void cbBT_UTILS_setInvalidBdAddr( - TBdAddr* addr); - -/** - * Get invalid address - * - * @returns Pointer to the invalid address - */ -extern const TBdAddr* cbBT_UTILS_getInvalidBdAddr(void); - -/** - * Copy Bluetooth address - * - * @param dest Pointer to destination address - * @param src Pointer to source address - */ -extern void cbBT_UTILS_cpyBdAddr( - TBdAddr* dest, - TBdAddr* src); - -#ifdef __cplusplus -} -#endif - -#endif /* _CB_BT_UTILS_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h deleted file mode 100644 index b5a1acda27d..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h +++ /dev/null @@ -1,80 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malm�, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : WLAN - * File : cb_cert_utils.h - * - * Description : - *-------------------------------------------------------------------------*/ - -/** - * @file cb_cert_utils.h The main WLAN component interface. - * All functions declared extern needs to be provided by another/upper layer. - * @ingroup wlan - */ - -#ifndef _CB_CERT_UTILS_H_ -#define _CB_CERT_UTILS_H_ - -#include "cb_types.h" -#include "cb_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbCERT_CRT_MAX_CHAIN_LENGTH 5ul - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -typedef struct cbCERT_Stream_s cbCERT_Stream; -typedef cb_uint32 cbCERT_StreamPosition; - -/** - * Stream vtable interface used by WLAN supplicant to access SSL certificates - * for WPA Enterprise authentication. - * - * @ingroup wlan - */ -struct cbCERT_Stream_s { - cb_int32(*read)(const cbCERT_Stream *stream, void *buf, cb_uint32 count); /**< Read function pointer, place count bytes in buf. */ - cb_int32(*write)(const cbCERT_Stream *stream, void *buf, cb_uint32 count); /**< Read function pointer, place count bytes in buf. */ - void(*rewind)(const cbCERT_Stream *stream); /**< Rewind function pointer, rewind stream internal iterator to the beginning. Mandatory for all streams. */ - void(*setPosition)(const cbCERT_Stream *stream, cbCERT_StreamPosition position); /**< Set absolute position. */ - cbCERT_StreamPosition(*getPosition)(const cbCERT_Stream *stream); /**< Get current position. */ - cb_uint32(*getSize)(const cbCERT_Stream *stream); /**< GetSize function pointer, return total size of stream contents. */ -}; - -/*=========================================================================== - * CERT API - *=========================================================================*/ - -cbRTSL_Status cbCERT_Util_parseDERCert(cbCERT_Stream const * const certificate, cbCERT_Stream const * const outputStream); -cbRTSL_Status cbCERT_Util_parseDERKey(cbCERT_Stream const * const key, cbCERT_Stream const * const outputStream); -cbRTSL_Status cbCERT_Util_parsePEMCert(cbCERT_Stream const * const certificate, cbCERT_Stream const * const outputStream); -cbRTSL_Status cbCERT_Util_parsePEMKey(cbCERT_Stream const * const certificate, cb_char const * const key, cb_uint32 keyLength, cbCERT_Stream const * const outputStream); - -#ifdef __cplusplus -} -#endif - -#endif /* _CB_CERT_UTILS_H_ */ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h deleted file mode 100644 index bc0f7c34cc9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h +++ /dev/null @@ -1,190 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Common Definitions - * File : cb_comdefs.h - * - * Description : Common definitions. - *-------------------------------------------------------------------------*/ - -#ifndef _CB_COMDEFS_H_ -#define _CB_COMDEFS_H_ - -#include "cb_platform_basic_types.h" - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -#ifndef FALSE -# define FALSE (0) -#endif - -#ifndef TRUE -# define TRUE (!FALSE) -#endif - -#ifndef NULL -# define NULL ((void*)0) -#endif - -/** - * Returns the maximum value of the two parameters. - */ -#define cb_MAX(a,b) (((a) > (b)) ? (a) : (b)) - -/** - * Returns the minimum value of the two parameters. - */ -#define cb_MIN(a,b) (((a) < (b)) ? (a) : (b)) - -/** - * Used in function definitions to declare an input parameter unused to avoid warnings. - */ -#ifndef cb_UNUSED -# define cb_UNUSED(x) x -#endif - - -#ifndef cb_ASSERT -# error "No platform definition for ASSERT!" -#endif - -/** - * Used when declaring an empty array that does not take up space in a struct. - * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; } - * In some compilers this is empty i.e. payload[]. While in some it requires a zero. - * I.e. payload[0]; - * Use this define to get it working for your system. - */ -#ifndef cb_EMPTY_ARRAY -# define cb_EMPTY_ARRAY (0) -#endif - - -#define cb_BIT_0 (1ul) -#define cb_BIT_1 (1ul << 1) -#define cb_BIT_2 (1ul << 2) -#define cb_BIT_3 (1ul << 3) -#define cb_BIT_4 (1ul << 4) -#define cb_BIT_5 (1ul << 5) -#define cb_BIT_6 (1ul << 6) -#define cb_BIT_7 (1ul << 7) -#define cb_BIT_8 (1ul << 8) -#define cb_BIT_9 (1ul << 9) -#define cb_BIT_10 (1ul << 10) -#define cb_BIT_11 (1ul << 11) -#define cb_BIT_12 (1ul << 12) -#define cb_BIT_13 (1ul << 13) -#define cb_BIT_14 (1ul << 14) -#define cb_BIT_15 (1ul << 15) -#define cb_BIT_16 (1ul << 16) -#define cb_BIT_17 (1ul << 17) -#define cb_BIT_18 (1ul << 18) -#define cb_BIT_19 (1ul << 19) -#define cb_BIT_20 (1ul << 20) -#define cb_BIT_21 (1ul << 21) -#define cb_BIT_22 (1ul << 22) -#define cb_BIT_23 (1ul << 23) -#define cb_BIT_24 (1ul << 24) -#define cb_BIT_25 (1ul << 25) -#define cb_BIT_26 (1ul << 26) -#define cb_BIT_27 (1ul << 27) -#define cb_BIT_28 (1ul << 28) -#define cb_BIT_29 (1ul << 29) -#define cb_BIT_30 (1ul << 30) -#define cb_BIT_31 (1ul << 31) - -/** - * Clears (set to zero) a bit or bits in a variable. - * @param variable The variable. - * @param bit The bit or bits to clear - */ -#define cb_CLEAR_BIT(variable,bit) ((variable) &= ~((bit))) - -/** - * Gets a bit i.e. checks if it is set in a variable. - * - * Also works to see if any of several bits are set. - * - * @param variable The variable. - * @param bit The bit to check if it set. - * @return @ref TRUE if any of the bits are set, @ref FALSE otherwise. - */ -#define cb_GET_BIT(variable,bit) (((variable) & ((bit))) ? TRUE : FALSE) - -/** - * Calculate the number of elements in an array. - * - * @note Won't work on pointer to array as the sizeof(pointer) is 4. - * - * @param _array The array. - * @return Number of elements in array. - */ -#define ELEMENTS_OF(_array) (sizeof((_array)) / sizeof((_array)[0])) - -/** - * Sets (set to 1) a bit or bits in a variable. - * - * @param variable The variable. - * @param bit The bit or bits to set in the variable. - */ -#define cb_SET_BIT(variable,bit) ((variable) |= (bit)) - -#define cb_UINT8_MAX ((cb_uint8)0xff) -#define cb_UINT16_MAX ((cb_uint16)0xffff) -#define cb_UINT32_MAX ((cb_uint32)0xffffffff) -#define cb_INT8_MAX ((cb_int8)0x7f) -#define cb_INT16_MAX ((cb_int16)0x7fff) -#define cb_INT32_MAX ((cb_int32)0x7fffffff) -#define cb_INT8_MIN ((cb_int8)0x80) -#define cb_INT16_MIN ((cb_int16)0x8000) -#define cb_INT32_MIN ((cb_int32)0x80000000) - -/* Packed struct default defines */ -#ifndef cb_PACKED_STRUCT_ATTR_INLINE_POST -# define cb_PACKED_STRUCT_ATTR_INLINE_POST -#endif -#ifndef cb_PACKED_STRUCT_ATTR_INLINE_PRE -# define cb_PACKED_STRUCT_ATTR_INLINE_PRE -#endif -#ifndef cb_PACKED_STRUCT_ATTR_PRE -# define cb_PACKED_STRUCT_ATTR_PRE -#endif -#ifndef cb_PACKED_STRUCT_ATTR_POST -# define cb_PACKED_STRUCT_ATTR_POST -#endif - -#define cb_PACKED_STRUCT_BEGIN(name) \ - cb_PACKED_STRUCT_ATTR_PRE \ - typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct name##_t - -#define cb_PACKED_STRUCT_END(name) \ - cb_PACKED_STRUCT_ATTR_INLINE_POST name; \ - cb_PACKED_STRUCT_ATTR_POST - -#ifdef __GNUC__ -# define DO_PRAGMA(x) _Pragma (#x) -# define TODO(x) DO_PRAGMA(message ("TODO - " #x)) -#else -# define TODO(x) -#endif - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -#endif /* _cb_COMDEFS_H_ */ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h deleted file mode 100644 index 319f45f3760..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h +++ /dev/null @@ -1,504 +0,0 @@ -/* - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : GATT - * File : cb_gatt.h - * - * Description : Definitions and types for GATT(Generic Attribute Profile) - * that are in common for both client and server. - * - *-------------------------------------------------------------------------*/ - -/** - * @file cb_gatt.h - * - * @brief Definitions and types for GATT(Generic Attribute Profile) - * that are in common for both client and server. - */ - -#ifndef _CB_GATT_H_ -#define _CB_GATT_H_ - -#include "bt_types.h" - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#define cbGATT_OK (0) -#define cbGATT_ERROR (-1) -#define cbGATT_ERROR_WRONG_STATE (-2) -#define cbGATT_ERROR_WRONG_HANDLE (-3) -#define cbGATT_ERROR_WRONG_PARAMETERS (-4) - -// This should be the same as in ATT -#define cbGATT_DEFAULT_MTU_LE 23 - -#define cbGATT_GET_MAX_READ_MULTIPLE_MTU(mtu) (mtu-1) -#define cbGATT_GET_MAX_WRITE_CHARACTERISTIC_MTU(mtu) (mtu-3) -#define cbGATT_GET_MAX_WRITE_SIGNED_CHARACTERISTIC_MTU(mtu) (mtu-13) -#define cbGATT_GET_MAX_NOTIFICATION_MTU(mtu) (mtu-3) -#define cbGATT_GET_MAX_INDICATION_MTU(mtu) (mtu-3) - -#define cbGATT_INVALID_ATTR_HANDLE 0x0000 -#define cbGATT_MIN_ATTR_HANDLE 0x0001 -#define cbGATT_MAX_ATTR_HANDLE 0xFFFF - -#define cbGATT_PROP_BCST 0x01 // Broadcast -#define cbGATT_PROP_RD 0x02 // Readable -#define cbGATT_PROP_WR_NO_RSP 0x04 // Write with no response -#define cbGATT_PROP_WR 0x08 // Writable -#define cbGATT_PROP_NOT 0x10 // Notify -#define cbGATT_PROP_IND 0x20 // Indicate -#define cbGATT_PROP_SIGN_WR 0x40 // Authenticated signed write -#define cbGATT_PROP_EXT 0x80 // extended property - -#define cbGATT_PROP_EXT_REL_WR 0x0001 // Reliable write -#define cbGATT_PROP_EXT_WR_AUX 0x0002 // auxiliary write -#define cbGATT_CLIENT_CFG_NONE 0x0000 // Client configuration disabled -#define cbGATT_CLIENT_CFG_NOT 0x0001 // Client notification configuration -#define cbGATT_CLIENT_CFG_IND 0x0002 // Server indication configuration -#define cbGATT_SERVER_CFG_BCST 0x0001 // Server broadcast configuration - -#define cbGATT_GET_BROADCAST_PROP(prop) ((0x01 & prop) == 0x01) -#define cbGATT_GET_READ_PROP(prop) ((0x02 & prop) == 0x02) -#define cbGATT_GET_WRITE_WITHOUT_RSP_PROP(prop) ((0x04 & prop) == 0x04) -#define cbGATT_GET_WRITE_PROP(prop) ((0x08 & prop) == 0x08) -#define cbGATT_GET_NOTIFY_PROP(prop) ((0x10 & prop) == 0x10) -#define cbGATT_GET_INDICATE_PROP(prop) ((0x20 & prop) == 0x20) -#define cbGATT_GET_AUTH_SIGNED_WRITES_PROP(prop) ((0x40 & prop) == 0x40) -#define cbGATT_GET_EXTENDED_PROP(prop) ((0x80 & prop) == 0x80) - -#define cbGATT_GET_PROP_EXT_REL_WR(prop) ((0x0001 & prop) == 0x0001) -#define cbGATT_GET_PROP_EXT_WR_AUX(prop) ((0x0002 & prop) == 0x0002) -#define cbGATT_GET_CLIENT_CFG_NOT(cfg) ((0x0001 & cfg) == 0x0001) -#define cbGATT_GET_CLIENT_CFG_IND(cfg) ((0x0002 & cfg) == 0x0002) -#define cbGATT_GET_SERVER_CFG_BCST(cfg) ((0x0001 & cfg) == 0x0001) - -#define cbGATT_SET_BROADCAST_PROP(prop) (prop = prop | 0x01) -#define cbGATT_SET_READ_PROPERTY(prop) (prop = prop | 0x02) -#define cbGATT_SET_WRITE_WITHOUT_RSP_PROP(prop) (prop = prop | 0x04) -#define cbGATT_SET_WRITE_PROP(prop) (prop = prop | 0x08) -#define cbGATT_SET_NOTIFY_PROP(prop) (prop = prop | 0x10) -#define cbGATT_SET_INDICATE_PROP(prop) (prop = prop | 0x20) -#define cbGATT_SET_AUTH_SIGNED_WRITES_PROP(prop) (prop = prop | 0x40) -#define cbGATT_SET_EXTENDED_PROP(prop) (prop = prop | 0x80) - -#define cbGATT_SET_PROP_EXT_REL_WR(prop) (prop = prop | 0x0001) -#define cbGATT_SET_PROP_EXT_WR_AUX(prop) (prop = prop | 0x0002) -#define cbGATT_SET_CLIENT_CFG_NOT(cfg) (cfg = cfg | 0x0001) -#define cbGATT_SET_CLIENT_CFG_IND(cfg) (cfg = cfg | 0x0002) -#define cbGATT_SET_SERVER_CFG_BCST(cfg) (cfg = cfg | 0x0001) - -// Below specification level as of 2011-09-13 -#define cbGATT_SERVICE_GENERIC_ACCESS 0x1800 // 0.5 -#define cbGATT_SERVICE_GENERIC_ATTRIBUTE 0x1801 // 0.5 -#define cbGATT_SERVICE_IMMEDIATE_ALERT 0x1802 // Adopted -#define cbGATT_SERVICE_LINK_LOSS 0x1803 // Adopted -#define cbGATT_SERVICE_TX_POWER 0x1804 // Adopted -#define cbGATT_SERVICE_CURRENT_TIME 0x1805 // Prototype -#define cbGATT_SERVICE_REFERENCE_TIME_UPDATE 0x1806 // Prototype -#define cbGATT_SERVICE_NEXT_DST_CHANGE 0x1807 // Prototype -#define cbGATT_SERVICE_HEALTH_THERMOMETER 0x1809 // Adopted -#define cbGATT_SERVICE_DEVICE_INFORMATION 0x180A // Adopted -#define cbGATT_SERVICE_NETWORK_AVAILABILITY 0x180B // 0.9 -#define cbGATT_SERVICE_WATCHDOG 0x180C // 0.5 -#define cbGATT_SERVICE_HEART_RATE 0x180D // Adopted -#define cbGATT_SERVICE_PHONE_ALERT_STATUS 0x180E // Prototype -#define cbGATT_SERVICE_BATTERY_SERVICE 0x180F // Prototype -#define cbGATT_SERVICE_BLOOD_PRESSURE 0x1810 // 0.9 -#define cbGATT_SERVICE_ALERT_NOTIFICATION 0x1811 // Prototype -#define cbGATT_SERVICE_HUMAN_INTERFACE_DEVICE 0x1812 // 0.5 -#define cbGATT_SERVICE_SCAN_PARAMETER 0x1813 // 0.5 - -#define cbGATT_PRIMARY_SERVICE_DECL 0x2800 -#define cbGATT_SECONDARY_SERVICE_DECL 0x2801 -#define cbGATT_INCLUDE_DECL 0x2802 -#define cbGATT_CHAR_DECL 0x2803 -#define cbGATT_CHAR_EXT_PROP 0x2900 -#define cbGATT_CHAR_USER_DESC 0x2901 -#define cbGATT_CLIENT_CHAR_CONFIG 0x2902 -#define cbGATT_SERVER_CHAR_CONFIG 0x2903 -#define cbGATT_CHAR_FORMAT 0x2904 -#define cbGATT_CHAR_AGGR_FORMAT 0x2905 - -#define cbGATT_CHAR_GAP_DEVICE_NAME 0x2A00 // Adopted -#define cbGATT_CHAR_GAP_APPEARANCE 0x2A01 // Adopted -#define cbGATT_CHAR_GAP_PERIP_PRIV 0x2A02 // Adopted -#define cbGATT_CHAR_GAP_RECONN_ADDR 0x2A03 // Adopted -#define cbGATT_CHAR_GAP_CONN_PARAMS 0x2A04 // Adopted -#define cbGATT_CHAR_GATT_SVC_CHANGED 0x2A05 // Adopted -#define cbGATT_CHAR_ALERT_LEVEL 0x2A06 // Adopted -#define cbGATT_CHAR_TX_POWER_LEVEL 0x2A07 // Adopted -#define cbGATT_CHAR_DATE_TIME 0x2A08 // Adopted -#define cbGATT_CHAR_DAY_OF_WEEK 0x2A09 // Prototype -#define cbGATT_CHAR_DAY_DATE_TIME 0x2A0A // Prototype -#define cbGATT_CHAR_EXACT_TIME_100 0x2A0B // 0.9 -#define cbGATT_CHAR_EXACT_TIME_256 0x2A0C // Prototype -#define cbGATT_CHAR_DST_OFFSET 0x2A0D // Prototype -#define cbGATT_CHAR_TIME_ZONE 0x2A0E // Prototype -#define cbGATT_CHAR_LOCAL_TIME_INFORMATION 0x2A0F // Prototype -#define cbGATT_CHAR_SECONDARY_TIME_ZONE 0x2A10 // 0.9 -#define cbGATT_CHAR_TIME_WITH_DST 0x2A11 // Prototype -#define cbGATT_CHAR_TIME_ACCURACY 0x2A12 // Prototype -#define cbGATT_CHAR_TIME_SOURCE 0x2A13 // Prototype -#define cbGATT_CHAR_REFERENCE_TIME_INFORMATION 0x2A14 // Prototype -#define cbGATT_CHAR_TIME_BROADCAST 0x2A15 // 0.9 -#define cbGATT_CHAR_TIME_UPDATE_CONTROL_POINT 0x2A16 // Prototype -#define cbGATT_CHAR_TIME_UPDATE_STATE 0x2A17 // Prototype -#define cbGATT_CHAR_BOOLEAN 0x2A18 // 0.9 -#define cbGATT_CHAR_BATTERY_LEVEL 0x2A19 // 0.9 -#define cbGATT_CHAR_BATTERY_POWER_STATE 0x2A1A // 0.9 -#define cbGATT_CHAR_BATTERY_LEVEL_STATE 0x2A1B // 0.9 -#define cbGATT_CHAR_TEMP_MEASUREMENT 0x2A1C // Adopted -#define cbGATT_CHAR_TEMP_TYPE 0x2A1D // Adopted -#define cbGATT_CHAR_INTERMEDIATE_TEMP 0x2A1E // Adopted -#define cbGATT_CHAR_TEMP_CELSIUS 0x2A1F // 0.9 -#define cbGATT_CHAR_TEMP_FAHRENHEIT 0x2A20 // 0.9 -#define cbGATT_CHAR_MEASUREMENT_INTERVAL 0x2A21 // Adopted -#define cbGATT_CHAR_SYSTEM_ID 0x2A23 // Adopted -#define cbGATT_CHAR_MODEL_NUMBER_STRING 0x2A24 // Adopted -#define cbGATT_CHAR_SERIAL_NUMBER_STRING 0x2A25 // Adopted -#define cbGATT_CHAR_FIRMWARE_REV_STRING 0x2A26 // Adopted -#define cbGATT_CHAR_HARDWARE_REV_STRING 0x2A27 // Adopted -#define cbGATT_CHAR_SOFTWARE_REV_STRING 0x2A28 // Adopted -#define cbGATT_CHAR_MANUFACTURER_NAME_STRING 0x2A29 // Adopted -#define cbGATT_CHAR_IEEE_REG_CERT_DATA_LIST 0x2A2A // Adopted -#define cbGATT_CHAR_CURRENT_TIME 0x2A2B // Prototype -#define cbGATT_CHAR_ELEVATION 0x2A2C // 0.5 -#define cbGATT_CHAR_LATITUDE 0x2A2D // 0.5 -#define cbGATT_CHAR_LONGITUDE 0x2A2E // 0.5 -#define cbGATT_CHAR_POSITION_2D 0x2A2F // 0.5 -#define cbGATT_CHAR_POSITION_3D 0x2A30 // 0.5 -#define cbGATT_CHAR_VENDOR_ID_V1_1 0x2A31 // 0.5 -#define cbGATT_CHAR_PRODUCT_ID 0x2A32 // 0.5 -#define cbGATT_CHAR_HID_VERSION 0x2A33 // 0.5 -#define cbGATT_CHAR_VENDOR_ID_SOURCE 0x2A34 // 0.5 -#define cbGATT_CHAR_BLOOD_PRESSURE_MEASUREMENT 0x2A35 // 0.9 -#define cbGATT_CHAR_INTERMEDIATE_BLOOD_PRESSURE 0x2A36 // 0.9 -#define cbGATT_CHAR_HEART_RATE_MEASUREMENT 0x2A37 // Adopted -#define cbGATT_CHAR_BODY_SENSOR_LOCATION 0x2A38 // Adopted -#define cbGATT_CHAR_HEART_RATE_CONTROL_POINT 0x2A39 // Adopted -#define cbGATT_CHAR_REMOVABLE 0x2A3A // 0.5 -#define cbGATT_CHAR_SERVICE_REQUIRED 0x2A3B // 0.9 -#define cbGATT_CHAR_SCIENTIFIC_TEMP_CELSIUS 0x2A3C // 0.9 -#define cbGATT_CHAR_STRING 0x2A3D // 0.9 -#define cbGATT_CHAR_NETWORK_AVAILABILITY 0x2A3E // 0.9 -#define cbGATT_CHAR_ALERT_STATUS 0x2A3F // Prototype -#define cbGATT_CHAR_RINGER_CONTROL_POINT 0x2A40 // Prototype -#define cbGATT_CHAR_RINGER_SETTING 0x2A41 // Prototype -#define cbGATT_CHAR_ALERT_CATEGORY_ID_BIT_MASK 0x2A42 // 0.9 -#define cbGATT_CHAR_ALERT_CATEGORY_ID 0x2A43 // 0.9 -#define cbGATT_CHAR_ALERT_NOTIF_CONTROL_POINT 0x2A44 // 0.9 -#define cbGATT_CHAR_UNREAD_ALERT_STATUS 0x2A45 // 0.9 -#define cbGATT_CHAR_NEW_ALERT 0x2A46 // 0.9 -#define cbGATT_CHAR_SUPPORTED_NEW_ALERT_CATEGORY 0x2A47 // 0.9 -#define cbGATT_CHAR_SUPPORTED_UNREAD_ALERT_CATEGORY 0x2A48 // 0.9 -#define cbGATT_CHAR_BLOOD_PRESSURE_FEATURE 0x2A49 // 0.9 - -/*============================================================================== - * TYPES - *============================================================================== - */ - -typedef enum -{ - cbGATT_WRITE_METHOD_WITH_RSP, - cbGATT_WRITE_METHOD_NO_RSP, - cbGATT_WRITE_METHOD_SIGN, - cbGATT_WRITE_METHOD_RELIABLE_PREPARE, -} cbGATT_WriteMethod; - -typedef enum -{ - cbGATT_UNIT_UNITLESS = 0x2700, - cbGATT_UNIT_LENGTH_METRE = 0x2701, - cbGATT_UNIT_MASS_KILOGRAM = 0x2702, - cbGATT_UNIT_TIME_SECOND = 0x2703, - cbGATT_UNIT_ELECTRIC_CURRENT_AMPERE = 0x2704, - cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_KELVIN = 0x2705, - cbGATT_UNIT_AMOUNT_OF_SUBSTANCE_MOLE = 0x2706, - cbGATT_UNIT_LUMINOUS_INTENSITY_CANDELA = 0x2707, - cbGATT_UNIT_AREA_SQUARE_METRES = 0x2710, - cbGATT_UNIT_VOLUME_CUBIC_METRES = 0x2711, - cbGATT_UNIT_VELOCITY_METRES_PER_SECOND = 0x2712, - cbGATT_UNIT_ACCELERATION_METRES_PER_SECOND_SQUARED = 0x2713, - cbGATT_UNIT_WAVENUMBER_RECIPROCAL_METRE = 0x2714, - cbGATT_UNIT_DENSITY_KILOGRAM_PER_CUBIC_METRE = 0x2715, - cbGATT_UNIT_SURFACE_DENSITY_KILOGRAM_PER_SQUARE_METRE = 0x2716, - cbGATT_UNIT_SPECIFIC_VOLUME_CUBIC_METRE_PER_KILOGRAM = 0x2717, - cbGATT_UNIT_CURRENT_DENSITY_AMPERE_PER_SQUARE_METRE = 0x2718, - cbGATT_UNIT_MAGNETIC_FIELD_STRENGTH_AMPERE_PER_METRE = 0x2719, - cbGATT_UNIT_AMOUNT_CONCENTRATION_MOLE_PER_CUBIC_METRE = 0x271A, - cbGATT_UNIT_MASS_CONCENTRATION_KILOGRAM_PER_CUBIC_METRE = 0x271B, - cbGATT_UNIT_LUMINANCE_CANDELA_PER_SQUARE_METRE = 0x271C, - cbGATT_UNIT_REFRACTIVE_INDEX = 0x271D, - cbGATT_UNIT_RELATIVE_PERMEABILITY = 0x271E, - cbGATT_UNIT_PLANE_ANGLE_RADIAN = 0x2720, - cbGATT_UNIT_SOLID_ANGLE_STERADIAN = 0x2721, - cbGATT_UNIT_FREQUENCY_HERTZ = 0x2722, - cbGATT_UNIT_FORCE_NEWTON = 0x2723, - cbGATT_UNIT_PRESSURE_PASCAL = 0x2724, - cbGATT_UNIT_ENERGY_JOULE = 0x2725, - cbGATT_UNIT_POWER_WATT = 0x2726, - cbGATT_UNIT_ELECTRIC_CHARGE_COULOMB = 0x2727, - cbGATT_UNIT_ELECTRIC_POTENTIAL_DIFFERENCE_VOLT = 0x2728, - cbGATT_UNIT_CAPACITANCE_FARAD = 0x2729, - cbGATT_UNIT_ELECTRIC_RESISTANCE_OHM = 0x272A, - cbGATT_UNIT_ELECTRIC_CONDUCTANCE_SIEMENS = 0x272B, - cbGATT_UNIT_MAGNETIC_FLEX_WEBER = 0x272C, - cbGATT_UNIT_MAGNETIC_FLEX_DENSITY_TESLA = 0x272D, - cbGATT_UNIT_INDUCTANCE_HENRY = 0x272E, - cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_CELSIUS = 0x272F, - cbGATT_UNIT_LUMINOUS_FLUX_LUMEN = 0x2730, - cbGATT_UNIT_ILLUMINANCE_LUX = 0x2731, - cbGATT_UNIT_ACTIVITY_REFERRED_TO_A_RADIONUCLIDE_BECQUEREL = 0x2732, - cbGATT_UNIT_ABSORBED_DOSE_GRAY = 0x2733, - cbGATT_UNIT_DOSE_EQUIVALENT_SIEVERT = 0x2734, - cbGATT_UNIT_CATALYTIC_ACTIVITY_KATAL = 0x2735, - cbGATT_UNIT_DYNAMIC_VISCOSITY_PASCAL_SECOND = 0x2740, - cbGATT_UNIT_MOMENT_OF_FORCE_NEWTON_METRE = 0x2741, - cbGATT_UNIT_SURFACE_TENSION_NEWTON_PER_METRE = 0x2742, - cbGATT_UNIT_ANGULAR_VELOCITY_RADIAN_PER_SECOND = 0x2743, - cbGATT_UNIT_ANGULAR_ACCELERATION_RADIAN_PER_SECOND_SQUARED = 0x2744, - cbGATT_UNIT_HEAT_FLUX_DENSITY_WATT_PER_SQUARE_METRE = 0x2745, - cbGATT_UNIT_HEAT_CAPACITY_JOULE_PER_KELVIN = 0x2746, - cbGATT_UNIT_SPECIFIC_HEAT_CAPACITY_JOULE_PER_KILOGRAM_KELVIN = 0x2747, - cbGATT_UNIT_SPECIFIC_ENERGY_JOULE_PER_KILOGRAM = 0x2748, - cbGATT_UNIT_THERMAL_CONDUCTIVITY_WATT_PER_METRE_KELVIN = 0x2749, - cbGATT_UNIT_ENERGY_DENSITY_JOULE_PER_CUBIC_METRE = 0x274A, - cbGATT_UNIT_ELECTRIC_FIELD_STRENGTH_VOLT_PER_METRE = 0x274B, - cbGATT_UNIT_ELECTRIC_CHARGE_DENSITY_COULOMB_PER_CUBIC_METRE = 0x274C, - cbGATT_UNIT_SURFACE_CHARGE_DENSITY_COULOMB_PER_SQUARE_METRE = 0x274D, - cbGATT_UNIT_ELECTRIC_FLUX_DENSITY_COULOMB_PER_SQUARE_METRE = 0x274E, - cbGATT_UNIT_PERMITTIVITY_FARAD_PER_METRE = 0x274F, - cbGATT_UNIT_PERMEABILITY_HENRY_PER_METRE = 0x2750, - cbGATT_UNIT_MOLAR_ENERGY_JOULE_PER_MOLE = 0x2751, - cbGATT_UNIT_MOLAR_ENTROPY_JOULE_PER_MOLE_KELVIN = 0x2752, - cbGATT_UNIT_EXPOSURE_COULOMB_PER_KILOGRAM = 0x2753, - cbGATT_UNIT_ABSORBED_DOSE_RATE_GRAY_PER_SECOND = 0x2754, - cbGATT_UNIT_RADIANT_INTENSITY_WATT_PER_STERADIAN = 0x2755, - cbGATT_UNIT_RADIANCE_WATT_PER_SQUARE_METER_STERADIAN = 0x2756, - cbGATT_UNIT_CATALYTIC_ACTIVITY_CONCENTRATION_KATAL_PER_CUBIC_METRE = 0x2757, - cbGATT_UNIT_TIME_MINUTE = 0x2760, - cbGATT_UNIT_TIME_HOUR = 0x2761, - cbGATT_UNIT_TIME_DAY = 0x2762, - cbGATT_UNIT_PLANE_ANGLE_DEGREE = 0x2763, - cbGATT_UNIT_PLANE_ANGLE_MINUTE = 0x2764, - cbGATT_UNIT_PLANE_ANGLE_SECOND = 0x2765, - cbGATT_UNIT_AREA_HECTARE = 0x2766, - cbGATT_UNIT_VOLUME_LITRE = 0x2767, - cbGATT_UNIT_MASS_TONNE = 0x2768, - cbGATT_UNIT_PRESSURE_BAR = 0x2780, - cbGATT_UNIT_PRESSURE_MILLIMETRE_OF_MERCURY = 0x2781, - cbGATT_UNIT_LENGTH_ANGSTROM = 0x2782, - cbGATT_UNIT_LENGTH_NAUTICAL_MILE = 0x2783, - cbGATT_UNIT_AREA_BARN = 0x2784, - cbGATT_UNIT_VELOCITY_KNOT = 0x2785, - cbGATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_NEPER = 0x2786, - cbGATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_BEL = 0x2787, - cbGATT_UNIT_LENGTH_YARD = 0x27A0, - cbGATT_UNIT_LENGTH_PARSEC = 0x27A1, - cbGATT_UNIT_LENGTH_INCH = 0x27A2, - cbGATT_UNIT_LENGTH_FOOT = 0x27A3, - cbGATT_UNIT_LENGTH_MILE = 0x27A4, - cbGATT_UNIT_PRESSURE_POUND_FORCE_PER_SQUARE_INCH = 0x27A5, - cbGATT_UNIT_VELOCITY_KILOMETRE_PER_HOUR = 0x27A6, - cbGATT_UNIT_VELOCITY_MILE_PER_HOUR = 0x27A7, - cbGATT_UNIT_ANGULAR_VELOCITY_REVOLUTION_PER_MINUTE = 0x27A8, - cbGATT_UNIT_ENERGY_GRAM_CALORIE = 0x27A9, - cbGATT_UNIT_ENERGY_KILOGRAM_CALORIE = 0x27AA, - cbGATT_UNIT_ENERGY_KILOWATT_HOUR = 0x27AB, - cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_FAHRENHEIT = 0x27AC, - cbGATT_UNIT_PERCENTAGE = 0x27AD, - cbGATT_UNIT_PER_MILLE = 0x27AE, - cbGATT_UNIT_PERIOD_BEATS_PER_MINUTE = 0x27AF, - cbGATT_UNIT_ELECTRIC_CHARGE_AMPERE_HOURS = 0x27B0, - cbGATT_UNIT_MASS_DENSITY_MILLIGRAM_PER_DECILITRE = 0x27B1, - cbGATT_UNIT_MASS_DENSITY_MILLIMOLE_PER_LITRE = 0x27B2, - cbGATT_UNIT_TIME_YEAR = 0x27B3, - cbGATT_UNIT_TIME_MONTH = 0x27B4, -} cbGATT_Unit; - -typedef enum -{ - - // Note, check http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.cbGATT.characteristic_presentation_format.xml - // for any changes - cbGATT_FORMAT_TYPE_BOOLEAN = 0x01, - cbGATT_FORMAT_TYPE_2BIT = 0x02, - cbGATT_FORMAT_TYPE_NIBBLE = 0x03, - cbGATT_FORMAT_TYPE_UINT8 = 0x04, - cbGATT_FORMAT_TYPE_UINT12 = 0x05, - cbGATT_FORMAT_TYPE_UINT16 = 0x06, - cbGATT_FORMAT_TYPE_UINT24 = 0x07, - cbGATT_FORMAT_TYPE_UINT32 = 0x08, - cbGATT_FORMAT_TYPE_UINT48 = 0x09, - cbGATT_FORMAT_TYPE_UINT64 = 0x0A, - cbGATT_FORMAT_TYPE_UINT128 = 0x0B, - cbGATT_FORMAT_TYPE_SINT8 = 0x0C, - cbGATT_FORMAT_TYPE_SINT12 = 0x0D, - cbGATT_FORMAT_TYPE_SINT16 = 0x0E, - cbGATT_FORMAT_TYPE_SINT24 = 0x0F, - cbGATT_FORMAT_TYPE_SINT32 = 0x10, - cbGATT_FORMAT_TYPE_SINT48 = 0x11, - cbGATT_FORMAT_TYPE_SINT64 = 0x12, - cbGATT_FORMAT_TYPE_SINT128 = 0x13, - cbGATT_FORMAT_TYPE_FLOAT32 = 0x14, - cbGATT_FORMAT_TYPE_FLOAT64 = 0x15, - cbGATT_FORMAT_TYPE_SFLOAT = 0x16, - cbGATT_FORMAT_TYPE_FLOAT = 0x17, - cbGATT_FORMAT_TYPE_DUINT16 = 0x18, - cbGATT_FORMAT_TYPE_UTF8S = 0x19, - cbGATT_FORMAT_TYPE_UTF16S = 0x1A, - cbGATT_FORMAT_TYPE_STRUCT = 0x1B, -} cbGATT_FormatType; - -typedef enum -{ - // This should map to ATT_TRole - cbGATT_ROLE_CLIENT = 0, - cbGATT_ROLE_SERVER = 1, - cbGATT_ROLE_BOTH = 2 -} cbGATT_Role; - -typedef enum -{ - cbGATT_NAMESPACE_BT_SIG = 0x01, -} cbGATT_Namespace; - -typedef enum -{ - cbGATT_NAMESPACE_DESC_UNKNOWN = 0x0000, -} cbGATT_NamespaceDesc; - -typedef struct -{ - cbGATT_FormatType format; - cb_uint8 exponent; - cbGATT_Unit unit; - cbGATT_Namespace gattNamespace; - cbGATT_NamespaceDesc namespaceDesc; -} cbGATT_CharFormat; - -// This enum must match ATT_TErrorCode for the first two parts -// (not the GATT specific) -typedef enum -{ - cbGATT_ERROR_CODE_OK = 0x00, - cbGATT_ERROR_CODE_INVALID_HANDLE = 0x01, - cbGATT_ERROR_CODE_READ_NOT_PERMITTED = 0x02, - cbGATT_ERROR_CODE_WRITE_NOT_PERMITTED = 0x03, - cbGATT_ERROR_CODE_INVALID_PDU = 0x04, - cbGATT_ERROR_CODE_INSUFFICIENT_AUTHENTICATION = 0x05, - cbGATT_ERROR_CODE_REQUEST_NOT_SUPPORTED = 0x06, - cbGATT_ERROR_CODE_INVALID_OFFSET = 0x07, - cbGATT_ERROR_CODE_INSUFFICIENT_AUTHORIZATION = 0x08, - cbGATT_ERROR_CODE_PREPARE_FULL_QUEUE = 0x09, - cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND = 0x0A, - cbGATT_ERROR_CODE_ATTRIBUTE_NOT_LONG = 0x0B, - cbGATT_ERROR_CODE_INSUFFICIENT_ENCRYPT_KEY_SIZE = 0x0C, - cbGATT_ERROR_CODE_INVALID_ATTRIBUTE_VALUE_LENGTH = 0x0D, - cbGATT_ERROR_CODE_UNLIKELY_ERROR = 0x0E, - cbGATT_ERROR_CODE_INSUFFICIENT_ENCRYPTION = 0x0F, - cbGATT_ERROR_CODE_UNSUPPORTED_GROUP_TPYE = 0x10, - cbGATT_ERROR_CODE_INSUFFICIENT_RESOURCES = 0x11, - - cbGATT_ERROR_CODE_OUT_OF_RANGE = 0xFF, - cbGATT_ERROR_CODE_PROCEDURE_ALREADY_IN_PROGRESS = 0xFE, - cbGATT_ERROR_CODE_IMPROPER_CLIENT_CHAR_CFG = 0xFD, - - // Special error codes not according to BT spec. - // Will never be sent over the air. - cbGATT_ERROR_CODE_TRANSACTION_TIMEOUT = 0x80, - cbGATT_ERROR_CODE_DISCONNECTED = 0x81, - cbGATT_ERROR_CODE_RELIABLE_CHECK_FAILED = 0x82, - cbGATT_ERROR_CODE_DELAYED_RSP = 0x83, -} cbGATT_ErrorCode; - - -typedef enum -{ - // This must map to ATT_TUuidFormat - cbGATT_UUID_16 = 0x01, - cbGATT_UUID_128 = 0x02 -} cbGATT_UuidFormat; - -typedef enum -{ - cbGATT_FINAL_DATA = 0x00, - cbGATT_MORE_DATA = 0x01, - cbGATT_CANCEL_DATA = 0x02 -} cbGATT_WriteLongCharFlag; - -typedef struct -{ - // This must map to ATT_TUuid - union - { - cb_uint16 uuid16; - cb_uint8 uuid128[16]; - }; - cbGATT_UuidFormat format; -} cbGATT_Uuid; - -/** - * Called when an ACL connection is established - * @param handle Connection handle - * @param errorCode Connect error code - * @param role TODO Add a proper type for role client/server master/slave central/peripheral - * @param peerBdAddress Address of remote device - * @param connInterval Connection interval - * @param connLatency Connection latency - * @param connTmo Connection timeout - * @param masterClkAccuracy Master clock accuracy - * @return None - */ -typedef void (*cbGATT_ConnComplEvt)( - TConnHandle handle, - TErrorCode errorCode, - cb_uint8 role, - TBdAddr peerBdAddress, - cb_uint16 connInterval, - cb_uint16 connLatency, - cb_uint16 connTmo, - cb_uint8 masterClkAccuracy); -/** - * Called when ACL connection is lost. - * @param handle Connection handle - * @param errorCode Disconnect error code - * @return None - */ -typedef void (*cbGATT_DisconnectEvt)( - TConnHandle handle, - TErrorCode errorCode); - - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h deleted file mode 100644 index 94f5d13b2ef..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h +++ /dev/null @@ -1,652 +0,0 @@ -/* - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component GATT - * File cb_gatt_client.h - * - * Description Definitions and types for GATT client functionality - * - */ - -/** - * @file cb_gatt_client.h - * - * This file contains all GATT client functionality. There are some restrictions - * on how this API is used. - * - Pointer data in callbacks are only valid in the context of the callback - * - Only one request at a time should be done from each app(app handle). The - * app must wait until all responses from an outstanding request have been - * received. - * - In the callback of the request another request can not be done except when - * the request is interrupted by setting the return value to FALSE - * or when in the last callback which contains an error code. - * - Most of the GATT requests can be interrupted by returning FALSE in the - * callback. - * - * See Bluetooth 4.0 specification for more info on GATT and ATT chapters: - * https://www.bluetooth.org/en-us/specification/adopted-specifications - * - */ - -#ifndef _CB_GATT_CLIENT_H_ -#define _CB_GATT_CLIENT_H_ - -#include "bt_types.h" -#include "cb_gatt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*============================================================================== - * TYPES - *============================================================================== - */ - -/** - * Callback for discover all primary services. This callback will be called - * for each primary service found. - * @param connHandle Connection handle - * @param errorCode cbGATT_ERROR_CODE_OK when succeeded - * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback - * when search is finished. - * cbGATT_ERROR_CODE_ on failure - * @param startGroupHandle Start handle of the service - * @param endGroupHandle End handle of the service - * @param pUuid Pointer to UUID of the service - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_DiscoverAllPrimaryServicesCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint16 startGroupHandle, - cb_uint16 endGroupHandle, - cbGATT_Uuid* pUuid); - -/** - * Callback for discover all secondary services. This callback will be called - * for each secondary service found. - * @param connHandle Connection handle - * @param errorCode cbGATT_ERROR_CODE_OK when succeeded - * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback - * when search is finished. - * cbGATT_ERROR_CODE on failure - * @param startGroupHandle Start handle of the service - * @param endGroupHandle End handle of the service - * @param pUuid Pointer to UUID of the service - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_DiscoverAllSecondaryServicesCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint16 startGroupHandle, - cb_uint16 endGroupHandle, - cbGATT_Uuid* pUuid); - -/** - * Callback for discover all primary services by UUID. This callback will be - * called for each primary service found. - * @param connHandle Connection handle - * @param errorCode cbGATT_ERROR_CODE_OK when succeeded - * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback - * when search is finished. - * cbGATT_ERROR_CODE_* on failure - * @param startGroupHandle Start handle of the service - * @param endGroupHandle End handle of the service - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_DiscoverPrimaryServiceByUuidCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint16 startHandle, - cb_uint16 endHandle); - -/** - * Callback for find included services. This callback will be called - * for each service found. - * @param connHandle Connection handle - * @param errorCode cbGATT_ERROR_CODE_OK when succeeded - * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback - * when search is finished. - * cbGATT_ERROR_CODE_* on failure - * @param startGroupHandle Start handle of the service - * @param endGroupHandle End handle of the service - * @param pUuid Pointer to UUID of the service - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_FindIncludedServicesCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint16 attrHandle, - cb_uint16 startGroupHandle, - cb_uint16 endGroupHandle, - cbGATT_Uuid* pUuid); - -/** - * Callback for discover all characteristics of service. This callback will - * be called for each characteristic found. - * @param connHandle Connection handle - * @param errorCode cbGATT_ERROR_CODE_OK when succeeded - * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback - * when search is finished. - * cbGATT_ERROR_CODE_* on failure - * @param attrHandle Attribute handle of the characteristic - * @param properties Bitmap of properties of the characteristic. - * See cbGATT_PROP_*. - * @param valueHandle Attribute handle of the characteristic value. - * This is where the actual data is located. - * @param pUuid Pointer to UUID of the characteristic - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_DiscoverAllCharacteristicsOfServiceCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint16 attrHandle, - cb_uint8 properties, - cb_uint16 valueHandle, - cbGATT_Uuid* pUuid); - -/** - * Callback for discover all descriptors of a characteristic. This callback - * will be called for each descriptor found. - * @param connHandle Connection handle - * @param errorCode cbGATT_ERROR_CODE_OK when succeeded - * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback - * when search is finished. - * cbGATT_ERROR_CODE_* on failure - * @param charAttrHandle Attribute handle of the characteristic - * @param attrHandle Attribute handle of the characteristic descriptor. - * @param pUuid Pointer to UUID of the descriptor - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_DiscoverAllCharacteristicDescriptorsCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint16 charAttrHandle, - cb_uint16 attrHandle, - cbGATT_Uuid* pUuid); - -/** - * Callback for read characteristic. This callback will be called for each - * data chunk read. - * The last callback will contain either an error code or moreToRead = FALSE - * @param connHandle Connection handle - * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded - * @param attrHandle Attribute handle of the characteristic - * @param pAttrValue Pointer to the read data chunk. - * @param length Length of the read data chunk - * @param moreToRead TRUE = more data to read from the characteristic - * FALSE = no more data to read - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_ReadCharacteristicCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint16 attrHandle, - cb_uint8* pAttrValue, - cb_uint16 length, - cb_boolean moreToRead); - -/** - * Callback for read characteristic by UUID. This callback will be called - * for each data chunk read. - * The last callback will contain either an error code or moreToRead = FALSE - * @param connHandle Connection handle - * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded - * @param attrHandle Attribute handle of the characteristic - * @param pAttrValue Pointer to the read data chunk. - * @param length Length of the read data chunk - * @param moreToRead TRUE = more data to read from the characteristic - * FALSE = no more data to read - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_ReadCharacteristicByUuidCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint16 attrHandle, - cb_uint8* pAttrValue, - cb_uint16 length, - cb_boolean moreToRead); - -// TODO to have or not?? -typedef void (*cbGATT_ReadLongCharacteristicCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint8* pAttrValue, - cb_uint16 length); - -/** - * Callback for read multiple characteristics. This callback will be called - * for each data chunk read. - * The last callback will contain either an error code or moreToRead = FALSE - * @param connHandle Connection handle - * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded - * @param pAttrValues Pointer to the read data chunk. - * @param length Length of the read data chunk - * @param moreToRead TRUE = more data to read from the characteristic(s) - * FALSE = no more data to read - * @return TRUE to continue or FALSE to interrupt the search. - */ -typedef cb_boolean (*cbGATT_ReadMultipleCharacteristicCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode, - cb_uint8* pAttrValues, - cb_uint16 length, - cb_boolean moreToRead); - -/** - * Callback for write characteristic with response from the remote side - * @param connHandle Connection handle - * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded - */ -typedef void (*cbGATT_WriteCharacteristicCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode); - -/** - * Callback for write characteristic with no response from the remote side - * @param connHandle Connection handle - * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded - */ -typedef void (*cbGATT_WriteCharacteristicNoRspCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode); - -/** - * Callback for write characteristic configuration with response from the - * remote side. - * @param connHandle Connection handle - * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded - */ -typedef void (*cbGATT_WriteCharacteristicConfigCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode); - -/** - * Callback for write long characteristic with response from the - * remote side. - * @param connHandle Connection handle - * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded - */ -typedef void (*cbGATT_WriteLongCharacteristicCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode); - -/** -* Callback for receiving value indication. The client configuration - * notifications must have been enabled before this will be sent to the app. - * Note that the indication is replied by GATT when exiting the callback. - * @param connHandle Connection handle - * @param attrHandle Attribute handle of the indicated value - * @param pAttrValue Pointer to the value data - * @param length Length of the value data - */ -typedef void (*cbGATT_CharacteristicValueIndication)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pAttrValue, - cb_uint16 length); - -/** - * Callback for receiving value notification. The client configuration - * notifications must have been enabled before this will be sent to the app. - * @param connHandle Connection handle - * @param attrHandle Attribute handle of the notified value - * @param pAttrValue Pointer to the value data - * @param length Length of the value data - */ -typedef void (*cbGATT_CharacteristicValueNotification)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pAttrValue, - cb_uint16 length); - -typedef struct -{ - cbGATT_ConnComplEvt connComplEvt; - cbGATT_DisconnectEvt disconnectEvt; - cbGATT_DiscoverAllPrimaryServicesCnf discoverAllPrimaryServicesCnf; - cbGATT_DiscoverAllSecondaryServicesCnf discoverAllSecondaryServicesCnf; - cbGATT_DiscoverPrimaryServiceByUuidCnf discoverPrimaryServiceByUuidCnf; - cbGATT_FindIncludedServicesCnf findIncludedServicesCnf; - cbGATT_DiscoverAllCharacteristicsOfServiceCnf discoverAllCharacteristicsOfServiceCnf; - cbGATT_DiscoverAllCharacteristicDescriptorsCnf discoverAllCharacteristicDescriptorsCnf; - cbGATT_ReadCharacteristicCnf readCharacteristicCnf; - cbGATT_ReadCharacteristicByUuidCnf readCharacteristicByUuidCnf; - cbGATT_ReadLongCharacteristicCnf readLongCharacteristicCnf; - cbGATT_ReadMultipleCharacteristicCnf readMultipleCharacteristicCnf; - cbGATT_WriteCharacteristicCnf writeCharacteristicCnf; - cbGATT_WriteCharacteristicNoRspCnf writeCharacteristicNoRspCnf; - cbGATT_WriteCharacteristicConfigCnf writeCharacteristicConfigCnf; - cbGATT_WriteLongCharacteristicCnf writeLongCharacteristicCnf; -} cbGATT_ClientCallBack; - - -typedef struct -{ - cbGATT_CharacteristicValueIndication characteristicValueIndication; - cbGATT_CharacteristicValueNotification characteristicValueNotification; -} cbGATT_ClientNotIndCallBack; - -/*============================================================================= - * EXPORTED FUNCTIONS - *============================================================================= - */ - -/** - * Register a GATT client. This must be done before any GATT client - * functionality can be used. - * @param pCallBack Callback structure that should be provided by the app. Use - * NULL as pointer for callbacks that are not used. - * @param pAppHandle Pointer where to put created app handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_registerClient( - const cbGATT_ClientCallBack* pCallBack, - cb_uint8* pAppHandle); - -/** - * Register a notification/indication handler for an attribute handle - * This is used when the application needs a specific handler for an - * attribute. This can be done first after connection setup. - * @param pCallBack Callback structure that should be provided by the app. Use - * NULL as pointer for callbacks that are not used. - * @param appHandle App handle - * @param attrHandle Attribute handle for the notification/indication to - * subscribe on. - * @param connHandle Connection handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_registerNotIndHandler( - const cbGATT_ClientNotIndCallBack* pCallBack, - cb_uint8 appHandle, - cb_uint16 attrHandle, - TConnHandle connHandle); - -/** - * De-register a notification/indication handler. This is used when the - * app does not want to subscribe to the attribute handle any longer e.g. - * the client characteristic configuration has been disabled. The handler is - * automatically de-registered on disconnection. - * @param pCallBack Registered callback. - * @param appHandle App handle - * @param attrHandle Attribute handle for the notification/indication to - * subscribe on. - * @param connHandle Connection handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_deregisterNotIndHandler( - const cbGATT_ClientNotIndCallBack* pCallBack, - cb_uint8 appHandle, - cb_uint16 attrHandle, - TConnHandle connHandle); - -/** - * Register a default notification/indication handler. This is used when the - * app wants to subscribe to all attribute handles notifications/indications - * for all connections. This can only be used by one app at a time. - * @param pCallBack Callback structure that should be provided by the app. Use - * NULL as pointer for callbacks that are not used. - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_registerDefaultNotIndHandler( - const cbGATT_ClientNotIndCallBack* pCallBack); - -/** - * Discover all primary services. Results will be provided in the - * cbGATT_DiscoverAllPrimaryServicesCnf callback. - * @param connHandle Connection handle - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_discoverAllPrimaryServices( - TConnHandle connHandle, - cb_uint8 appHandle); - -/** - * Discover all secondary services. Results will be provided in the - * cbGATT_DiscoverAllSecondaryServicesCnf callback. - * @param connHandle Connection handle - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_discoverAllSecondaryServices( - TConnHandle connHandle, - cb_uint8 appHandle); - -/** - * Discover all primary services by UUID. This will filter out all results - * based on the UUID. Results will be provided in the - * cbGATT_DiscoverPrimaryServiceByUuidCnf callback. - * @param connHandle Connection handle - * @param pUuid Pointer to the 16 or 128 bits UUID to search for - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_discoverPrimaryServiceByUuid( - TConnHandle connHandle, - cbGATT_Uuid* pUuid, - cb_uint8 appHandle); - -/** - * Discover all characteristics of a service. The handles can be - * retrieved by doing a discover primary/secondary services request. Results - * will be provided in the cbGATT_DiscoverAllCharacteristicsOfServiceCnf - * callback. - * @param connHandle Connection handle - * @param startHandle Start handle of the service - * @param endHandle End handle of the service - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_discoverAllCharacteristicsOfService( - TConnHandle connHandle, - cb_uint16 startHandle, - cb_uint16 endHandle, - cb_uint8 appHandle); - -/** - * Find included services of a given service. The handles can be - * retrieved by doing a discover primary/secondary services request. Results - * will be provided in the cbGATT_FindIncludedServicesCnf callback. - * @param connHandle Connection handle - * @param startHandle Start handle of the service - * @param endHandle End handle of the service - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_findIncludedServices( - TConnHandle connHandle, - cb_uint16 startHandle, - cb_uint16 endHandle, - cb_uint8 appHandle); - -/** - * Discover all descriptors of a characteristic. The handles can be - * retrieved by doing a cbGATT_discoverAllCharacteristicsOfService. Results - * will be provided in the cbGATT_DiscoverAllCharacteristicDescriptorsCnf. - * callback. If the app wants to do a discover characteristics by UUID this - * function can be used and in the callback filter on UUID. - * @param connHandle Connection handle - * @param valueHandle Handle of the characteristic value - * @param serviceEndHandle End handle of the service which the characteristic - * belongs to. - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_discoverAllCharacteristicDescriptors( - TConnHandle connHandle, - cb_uint16 valueHandle, - cb_uint16 serviceEndHandle, - cb_uint8 appHandle); - -/** - * Read characteristic/descriptor value. The handles can be retrieved by - * doing a cbGATT_discoverAllCharacteristicsOfService or - * cbGATT_discoverAllCharacteristicDescriptors. Results will be provided in - * the cbGATT_ReadCharacteristicCnf callback. - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param offset Offset where to start read from - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_readCharacteristic( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint16 offset, - cb_uint8 appHandle); - -/** - * Read characteristic/descriptor value by UUID. The app can search the whole - * database by using cbGATT_MIN_ATTR_HANDLE and cbGATT_MAX_ATTR_HANDLE. - * Results will be provided in the cbGATT_ReadCharacteristicByUuidCnf - * callback. - * @param connHandle Connection handle - * @param startHandle Handle, where to start looking for the UUID - * @param endHandle Handle, where to stop looking for the UUID - * @param pUuid Pointer to the 16 or 128 bits UUID - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_readCharacteristicByUuid( - TConnHandle connHandle, - cb_uint16 startHandle, - cb_uint16 endHandle, - cbGATT_Uuid* pUuid, - cb_uint8 appHandle); - -// Used for reading long characteristics value or descriptor -// TODO is this function necessary, because cbGATT_readCharacteristic will read long if needed -cb_int32 cbGATT_readLongCharacteristic( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pDest, - cb_uint8 appHandle); - - -/** - * Read multiple characteristics in a single read. The app must know the - * length of each data element in the returned list. Therefore only the last - * data element may have a variable length. - * Results will be provided in the cbGATT_ReadMultipleCharacteristicCnf - * callback. - * @param connHandle Connection handle - * @param pAttrHandleList Pointer to a list of attribute handles - * @param nbrOfHandles Number of attribute handles in pAttrHandleList - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_readMultipleCharacteristic( - TConnHandle connHandle, - cb_uint16* pAttrHandleList, - cb_uint16 nbrOfHandles, - cb_uint8 appHandle); - -/** - * Write characteristic/descriptor and wait for response from remote side. - * Results will be provided in the cbGATT_WriteCharacteristicCnf - * callback. - * @param connHandle Connection handle - * @param attrHandle Attribute handle of the value - * @param pData Pointer to the data byte sequence - * @param length Number of bytes to write - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_writeCharacteristic( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pData, - cb_uint16 length, - cb_uint8 appHandle); - -/** - * Write client/server characteristic/descriptor configuration. - * cbGATT_writeCharacteristic can also be used instead of this function. - * Results will be provided in the cbGATT_WriteCharacteristicConfigCnf - * callback. - * @param connHandle Connection handle - * @param attrHandle Attribute handle of the value - * @param config Configuration i.e. cbGATT_CLIENT_CFG_* or - * cbGATT_SERVER_CFG_* - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_writeCharacteristicConfig( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint16 config, - cb_uint8 appHandle); - -/** - * Write characteristic/descriptor with no response from remote side. - * Results will be provided in the cbGATT_WriteCharacteristicNoRspCnf - * callback. - * @param connHandle Connection handle - * @param attrHandle Attribute handle of the value - * @param pData Pointer to the data byte sequence - * @param length Number of bytes to write - * @param pSignature Pointer to encrypted signature which is checked by the - * server. If the check fails the write is discarded. - * The devices must be bonded and CSRK exchanged. Use NULL - * when no signature is being used. - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_writeCharacteristicNoRsp( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pData, - cb_uint16 length, - cb_uint8* pSignature, - cb_uint8 appHandle); - -/** - * Write long characteristic/descriptor and wait for response from remote - * side. Results will be provided in the cbGATT_WriteLongCharacteristicCnf - * callback. - * @param connHandle Connection handle - * @param attrHandle Attribute handle of the value - * @param pData Pointer to the data byte sequence - * @param length Number of bytes to write - * @param reliable TRUE = the data will be sent back to client and - * checked by GATT. - * FALSE = no check of data - * @param flag Flag which is used when sending several packets - * or when data is canceled. If sending several packets all - * but the last packet should set the flag to more data. - * The last data packet should set the flag to final. - * @param offset Offset of the data to write. Is used when several packets - * need to be sent to write a complete data value. - * @param appHandle App handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_writeLongCharacteristic( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pData, - cb_uint16 length, - cb_boolean reliable, - cbGATT_WriteLongCharFlag flag, - cb_uint16 offset, - cb_uint8 appHandle); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h deleted file mode 100644 index d2286c6dd49..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h +++ /dev/null @@ -1,329 +0,0 @@ -/*------------------------------------------------------------------------------ - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. -*------------------------------------------------------------------------------ -* Component: GATT -* File : cb_gatt_server.h -* -* Description: -* GATT server functionality -*------------------------------------------------------------------------------ -*/ - -/** - * @file cb_gatt_server.h - * - * @brief GATT server functionality - */ - -#ifndef _CB_GATT_SERVER_H_ -#define _CB_GATT_SERVER_H_ - -#include "bt_types.h" -#include "cb_gatt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*============================================================================== - * CONSTANTS - *============================================================================== - */ - -#define cbGATT_RD_SEC_NONE 0x01 -#define cbGATT_RD_SEC_UNAUTH 0x02 -#define cbGATT_RD_SEC_AUTH 0x04 -#define cbGATT_WR_SEC_NONE 0x10 -#define cbGATT_WR_SEC_UNAUTH 0x20 -#define cbGATT_WR_SEC_AUTH 0x40 - -#define cbGATT_NBR_OF_ATTR_OF_SERVICE(x) (sizeof(x)/sizeof(cbGATT_Attribute)) - -#define cbGATT_APP_START_SERVICE_HANDLE 1024 - -/*============================================================================== - * TYPES - *============================================================================== - */ - -/** - * Attribute database entry - * @param pUuid 16 or 128-bits UUID - * @param uuidFormat Format of the pUuid - * @param properties Properties see cbGATT_PROP_* in cb_gatt.h - * @param security Read/write security properties for this characteristic see cbGATT_WR_SEC_* and cbGATT_RD_SEC_* - * @param pvValue1 Depends on pUuid, see below - * cbGATT_CHAR_EXT_PROP - properties as cb_uint32 - * cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device reads the client config, cbGATT_ServerReadClientConfig - * cbGATT_SERVER_CHAR_CONFIG - callback that is called when remote device reads the server config, cbGATT_ServerReadServerConfig - * cbGATT_CHAR_FORMAT - Pointer to cbGATT_CharFormat - * cbGATT_CHAR_USER_DESC and all other CHARACTERISTICS value - cbGATT_ServerReadAttr callback - * cbGATT_INCLUDE_DECL - Pointer to inlcuded service cbGATT_Attribute - * @param pvValue2 Depends on pUuid, see below - * cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device writes the client config cbGATT_ServerWriteClientConfig - * cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device writes the client config cbGATT_ServerWriteClientConfig - * cbGATT_SERVER_CHAR_CONFIG - callback that is called when remote device writes the server config cbGATT_ServerWriteServerConfig - * cbGATT_CHAR_USER_DESC and all other CHARACTERISTICS value - cbGATT_ServerWriteAttr callback - * @param pAttrHandle Pointer where to write the attribute handle in case it's needed by the app. - * If not needed, pass NULL. Will be written after the service has been added. - */ -typedef struct -{ - void* pUuid; - cbGATT_UuidFormat uuidFormat; - cb_uint8 properties; - cb_uint8 security; - void* pvValue1; - void* pvValue2; - cb_uint16* pAttrHandle; -} cbGATT_Attribute; - -/** - * Callback is called when the indication has been confirmed. - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param errorCode cbGATT_ERROR_CODE_OK when succeeded - */ -typedef void (*cbGATT_CharacteristicValueIndicationCnf)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cbGATT_ErrorCode errorCode); - -/** - * Callback is called when the notification has been sent. - * @param connHandle Connection handle - * @param errorCode cbGATT_ERROR_CODE_OK when succeeded - */ -typedef void (*cbGATT_CharacteristicValueNotificationCnf)( - TConnHandle connHandle, - cbGATT_ErrorCode errorCode); - -/** - * Callback is called when the GATT client has commited a write long - * @param connHandle Connection handle - * @param commit TRUE = commit, FALSE = cancel - * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. - */ -typedef cbGATT_ErrorCode (*cbGATT_CharacteristicWriteLongCommitEvt)( - TConnHandle connHandle, - cb_boolean commit); - -// Callbacks to use in server table - -/** - * Callback is called when the client is reading an attribute - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param pAttr Pointer to attribute record - * @param pAttrValue Pointer where to put the read data - * @param pLength Pointer where to put the read length. - * @param maxLength Max number of bytes that is allowed for pAttrValue - * @param offset The offset of the read data - * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. - */ -typedef cbGATT_ErrorCode (*cbGATT_ServerReadAttr)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cbGATT_Attribute* pAttr, - cb_uint8* pAttrValue, - cb_uint16* pLength, - cb_uint16 maxLength, - cb_uint16 offset); - -/** - * Callback is called when the client is writing an attribute. - * If the application wants to send the response later it can - * return the cbGATT_ERROR_CODE_DELAYED_RSP error code and call cbGATT_writeRsp - * when ready. - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param pAttr Pointer to attribute record - * @param pAttrValue Pointer where to get the data - * @param length The length. - * @param writeMethod Which write method the client is using. - * This depends on the properties in the attribute table. - * @param offset The offset of the written data - * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. - */ -typedef cbGATT_ErrorCode (*cbGATT_ServerWriteAttr)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cbGATT_Attribute* pAttr, - cb_uint8* pAttrValue, - cb_uint16 length, - cbGATT_WriteMethod writeMethod, - cb_uint16 offset); - -/** - * Callback is called when the client is reading the client config - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param pConfig Pointer where to write the config - * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. - */ -typedef cbGATT_ErrorCode (*cbGATT_ServerReadClientConfig)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint16* pConfig); - -/** - * Callback is called when the client is writing the client config - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param config The config to be stored - * @param writeMethod Which write method the client is using. - * This depends on the properties in the attribute table. - * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. - */ -typedef cbGATT_ErrorCode (*cbGATT_ServerWriteClientConfig)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint16 config, - cbGATT_WriteMethod writeMethod); - -/** - * Callback is called when the client is reading the server config - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param pConfig Pointer where to write the config - * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. - */ -typedef cbGATT_ErrorCode (*cbGATT_ServerReadServerConfig)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint16* pConfig); - -/** - * Callback is called when the client is writing the server config - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param config The config to be stored - * @param writeMethod Which write method the client is using. - * This depends on the properties in the attribute table. - * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. - */ -typedef cbGATT_ErrorCode (*cbGATT_ServerWriteServerConfig)( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint16 config, - cbGATT_WriteMethod writeMethod); - -typedef struct -{ - cbGATT_ConnComplEvt connComplEvt; - cbGATT_DisconnectEvt disconnectEvt; - cbGATT_CharacteristicValueIndicationCnf characteristicValueIndicationCnf; - cbGATT_CharacteristicValueNotificationCnf characteristicValueNotificationCnf; - cbGATT_CharacteristicWriteLongCommitEvt characteristicWriteLongCommitEvt; -} cbGATT_ServerCallBack; - - -/*============================================================================= - * EXPORTED FUNCTIONS - *============================================================================= - */ - -/** - * Register server callbacks - * @param pCallBack Server callback - * @param pAppHandle Where to store app handle - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_registerServer( - const cbGATT_ServerCallBack* pCallBack, - cb_uint8* pAppHandle); - -/** - * Deregister all server callbacks - * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed. - */ -cb_int32 cbGATT_deregisterAllServers(void); - -/** - * Send notification to GATT client. The characteristicValueNotificationCnf - * callback will be called when finished and a new notification can be sent. - * The client config notification must have been enabled by the GATT client - * before an notification can be sent. - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param pData Pointer to data to send - * @param length Length of pData - * @param appHandle App handle - * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. - */ -cb_int32 cbGATT_notification( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pData, - cb_uint16 length, - cb_uint8 appHandle); - -/** - * Send indication to GATT client. The characteristicValueIndicationCnf - * callback will be called when finished and a new indication can be sent. - * The client config indication must have been enabled by the GATT client - * before an indication can be sent. - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param pData Pointer to data to send - * @param length Length of pData - * @param appHandle App handle - * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. - */ -cb_int32 cbGATT_indication( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pData, - cb_uint16 length, - cb_uint8 appHandle); - -/** - * Delay write respone to client, see cbGATT_ServerWriteAttr - * @param connHandle Connection handle - * @param attrHandle Handle of the attribute value - * @param errorCode Error code, use cbGATT_ERROR_CODE_OK if OK otherwise some cbGATT_ERROR_CODE_* - * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. - */ -cb_int32 cbGATT_writeRsp( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8 errorCode); // For delayed write responses - -/** - * Add service list to attribute database - * @param pAttrList Attribute list - * @param attrListSize Size of the attribute list - * @param startHandle Start handle. Note that startHandle for the application - * should start at lowest 1024, cbGATT_APP_START_SERVICE_HANDLE. - * 1-1023 is reserved for GATT/GAP and other u-blox services. - * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. - */ -cb_int32 cbGATT_addService( - const cbGATT_Attribute* pAttrList, - cb_uint16 attrListSize, - cb_uint16 startHandle); - -/** - * NOTE: Only for tests - * Free all services. Use with care since this will also remove GATT and GAP services. - * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. - */ -cb_int32 cbGATT_freeServices(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h deleted file mode 100644 index 248a7511e05..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : GATT - * File : cb_gatt_utils.h - * - * Description : Helper functions for GATT - * - *-------------------------------------------------------------------------*/ - -/** - * @file cb_gatt_utils.h - * - * @brief Helper functions for GATT - */ - -#ifndef _CB_GATT_UTILS_H_ -#define _CB_GATT_UTILS_H_ - -#include "cb_comdefs.h" -#include "bt_types.h" -#include "cb_gatt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*============================================================================= - * FUNCTIONS - *============================================================================= - */ - -/** - * Returns a string representing the error code. NULL if the error code is - * not found. - * @param errorCode GATT error code - */ -cb_char* cbGATT_UTILS_getStringFromErrorCode( - cbGATT_ErrorCode errorCode); - -/** - * Returns a string representing the GATT/ATT properties for a characteristic. - * @param properties Bitmap of properties see cbGATT_PROP_* - */ -cb_char* cbGATT_UTILS_getStringFromProperties( - cb_uint8 properties); - -/** - * Returns a string representing the UUID. NULL if the UUID is not - * found. - * @param pUuid Pointer to 128 or 16-bit UUID - */ -cb_char* cbGATT_UTILS_getStringFromUuid( - cbGATT_Uuid* pUuid); - -/** - * Returns a string representing the UUID as hex bytes. - * @param pUuid Pointer to 128 or 16-bit UUID - * @param resultStr Allocated buffer to put hex string in. - * Should fit 16*2+1 = 33 bytes - */ -cb_char* cbGATT_UTILS_getHexStringFromUuid( - cbGATT_Uuid* pUuid, - cb_char* resultStr); - -/** - * Returns a string representing the data as hex bytes. - * @param pData Pointer to data - * @param len Length of data - * @param resultStr Pointer to allocated buffer to put hex string in. - * Should fit len*2+1 bytes - */ -cb_char* cbGATT_UTILS_dataToHex( - cb_uint8* pData, - cb_uint16 len, - cb_char* resultStr); - -/** - * Reverse bytes - * @param src Pointer to data to reverse bytes for - * @param nbrOfBytes Length of src - */ -void cbGATT_UTILS_reverseBytes( - cb_uint8* src, - cb_uint16 nbrOfBytes); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h deleted file mode 100644 index 5b69d39d127..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h +++ /dev/null @@ -1,222 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component: CB HW - * File : cb_hw.h - * - * Description: Setup of hardware. - * TODO clean up this interface.. - *-------------------------------------------------------------------------*/ - -#ifndef _CB_HW_H_ -#define _CB_HW_H_ - -#include "cb_comdefs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbHW_SECUREBOOT_SIGN_LENGTH 344 -#define cbHW_FW_NAME_MAX_LENGTH 22 -#define cbHW_FW_NAME_MIN_LENGTH 1 -#define cbHW_FW_FLAG_MAX_LENGTH 8 // 8 bit fields -#define cbHW_FW_FLAG_MIN_LENGTH 1 -#define cbHW_UNIQUE_ID_SIZE 12 - -typedef enum { - cbHW_PCB_VERSION_UNKNOWN, - cbHW_PCB_VERSION_1, - cbHW_PCB_VERSION_2, - cbHW_PCB_VERSION_3, - cbHW_PCB_VERSION_4, - cbHW_PCB_VERSION_5 -} cbHW_PCBVersion; - -typedef enum { - cbHW_RESET_REASON_UNKNOWN = 0, - cbHW_RESET_REASON_FW_UPDATE, - cbHW_RESET_REASON_PRODUCTION_MODE -} cbHW_ResetReason; - -typedef enum { - cbHW_FLOW_CONTROL_DISABLED = 0, - cbHW_FLOW_CONTROL_ENABLED -} cbHW_FlowControl; - -typedef enum { - cbHW_IRQ_HIGH = 2U, - cbHW_IRQ_MEDIUM = 3U, - cbHW_IRQ_DEFAULT = 5U, - cbHW_IRQ_LOW = 12U -} cbHW_PRIO_LVL; - -typedef enum { - cbHW_SYSTICK_DISABLED, - cbHW_SYSTICK_LOW_FREQ, - cbHW_SYSTICK_DEFAULT, -} cbHW_SysTickMode; - -typedef enum { - cbHW_HASH_MD5 -} cbHW_HashType; -/*=========================================================================== - * TYPES - *=========================================================================*/ - -typedef void (*cbHW_StopModeStatusEvt)(cb_boolean enable); -typedef void (*cbHW_SysTickCb)(void); - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -void cbHW_init(void); -void cbHW_registerStopModeStatusEvt(cbHW_StopModeStatusEvt evt); -void cbHW_disableIrq(void); -void cbHW_enableIrq(void); -void cbHW_disableAllIrq(void); // Should not be used unless extremely critical -void cbHW_enableAllIrq(void); -void cbHW_enterSleepMode(void); -void cbHW_enterStopMode(void); -void cbHW_setWakeupEvent(void); -void cbHW_resetWakeupEvent(void); -void cbHW_setSysTickMode(cbHW_SysTickMode sysTickMode); - -/** - * Wait for specified amount of microseconds. May be interrupt dependent. - * @note Granularity may vary between systems. Will be at least systick based. - * The system may go to sleep during the delay. - * - * @param us Time to delay in microseconds. - */ -void cbHW_delay(cb_uint32 us); - -/** -* Puts the chip in NVIC soft reset -* @note: this does not reset any watchdog timer already enabled -*/ -void cbHW_reset(void); - -/** -* Wait for specified amount of microseconds using a software loop. -* @note Granularity may vary between systems. -* The system will not go to sleep during the delay. -* -* @param us Time to delay in microseconds. -*/ -void cbHW_softDelay(cb_uint32 us); -cb_boolean cbHW_sysFreqIsSupported(cb_uint32 sysFreq); -void cbHW_setSysFreq(cb_uint32 sysFreq); -cb_uint32 cbHW_getSysFreq(void); -void cbHW_writeBackupRegister(cb_uint32 registerId, cb_uint32 value); -cb_uint32 cbHW_readBackupRegister(cb_int32 registerId); -void cbHW_getHWId(cb_uint8 uid[cbHW_UNIQUE_ID_SIZE]); -cbHW_PCBVersion cbHW_getPCBVersion(void); - -/** -* Register a system tick callback. -* The system tick will be generated once evert millisecond. -* -* @param cb Callback function for the system tick timer. -*/ -void cbHW_registerSysTickISRCallback(cbHW_SysTickCb cb); - -/** -* Get the current tick frequency for the @ref cbHW_getTicks tick counter. -* @note The frequency may be altered with different system clocks and power modes. -* -* @return The current tick frequency. -*/ -cb_uint32 cbHW_getTickFrequency(void); - -/** -* Get the current value of the tick counter. -* Time base in @ref cbHW_getTickFrequency. -* @note The value may wrap. -* -* @return The current tick counter. -*/ -cb_uint32 cbHW_getTicks(void); - -/** -* Enter forced boot mode. The bootloader will start in x-modem -* mode and emit CCCC.. to notify that it is ready to receive -* a new fw. -* This function will return and boot mode will be entered -* after a device specific timeout. -* @param address x-modem file download start address -* @param baudrate x-modem download buadrate -* @return None -*/ -void cbHW_forceBoot(cb_uint32 address, cb_uint32 baudrate); - -/** -* Enter forced boot mode. The bootloader will start in x-modem -* mode and emit CCCC.. to notify that it is ready to receive -* a new fw. -* This function will return and boot mode will be entered -* after a device specific timeout. -* @param address x-modem file download start address -* @param baudrate x-modem download buadrate -* @param fwId firmware id -* @param fwSize firmware file size -* @param fwSignature firmware signature -* @param fwName firmware name -* @param fwFlags firmware flags -* @return None -*/ -void cbHW_forceBootSecure( - cb_uint32 address, - cb_uint32 baudrate, - cb_uint32 fwId, - cb_uint32 fwSize, - cb_char* fwSignature, - cb_char* fwName, - cb_char* fwFlags); - -/** -* Cancel entry into boot mode. The user canceled entry -* into forced boot mode. -* This function will clean up the RTC memory that was -* configured for a forced boot operation. Use this function -* for both cbHW_forceBootSecure and cbHW_forceBoot -* @return None -*/ -void cbHW_cancelforceBoot(void); - -void cbHW_enterProductionMode(cbHW_FlowControl flowControl); -cbHW_ResetReason cbHW_resetReason(void); -cbHW_FlowControl cbHW_flowControl(void); - -/** -* Calculates a hash over a dataset. -* @param type: type of hashing, MD5 for now -* @param pInData: pointer to Data over which the hashing should be done -* @param indataSize: size of data buffer. -* @param pOutData: pointer to result data -* @return None -*/ -void cbHW_hash(cbHW_HashType type, const cb_uint8* pInData,cb_uint32 indataSize, cb_uint8* pOutData); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h deleted file mode 100644 index cb7401afd75..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h +++ /dev/null @@ -1,184 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component: Main for WiFi-driver and BT stack - * File : cb_main.h - * - * Description : - *-------------------------------------------------------------------------*/ - -#ifndef _CB_MAIN_H_ -#define _CB_MAIN_H_ - -#include "bt_types.h" -#include "cb_bt_man.h" -#include "cb_wlan.h" -#include "mbed_events.h" - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbMAIN_TARGET_INVALID_ID -1 - -/*=========================================================================== - * TYPES - *=========================================================================*/ -typedef struct -{ - TBdAddr address; /** Bluetooth address that shall be assigned to controller. Pass invalidBdAddress to use controller default address*/ - cbBM_LeRole leRole; /** Bluetooth low energy role */ - cb_int8 maxOutputPower; /** Maximum output power. */ - cb_uint32 maxLinkKeysClassic; /** Max number of CLASSIC link keys */ - cb_uint32 maxLinkKeysLe; /** Max number of link keys BLE*/ -} cbMAIN_BtInitParams; - -typedef void(*cbMAIN_ErrorHandler)( - cb_int32 errorCode, - const cb_char* filename, - cb_uint32 line); - -typedef struct -{ - cbWLAN_MACAddress mac; /**< MAC of WLAN interface, set to all zeros if hardware programmed address should be used. */ - cbWM_TxPowerSettings txPowerSettings; /**< Transmission power settings. */ -} cbMAIN_WlanStartParams; - -#if (BLE_STACK_UBX != true) - -typedef void (*vs_cmd_send_t)(uint16_t opcode); - -typedef struct { - vs_cmd_send_t vs_command_callback; - char *Service_pack; - uint32_t service_pack_size; -} cordio_callback_s; - -#endif /* !BLE_STACK_UBX */ - -/*--------------------------------------------------------------------------- - * Callback to indicate that initialization of BT stack is completed. - *-------------------------------------------------------------------------*/ -typedef void(*cbMAIN_initBtComplete)(void); - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Initialize OS, timers, GPIO's, heap and OTP. - * - * @return void - */ -extern void cbMAIN_initOS(void); - -/** - * Start Bluetooth HW. - * - * @param pInitParameters Initial configuration parameters. These parameters can - * not be changed once Bluetooth has been started. - * @param callback Will be invoked when initialisation is done. - * @return void - */ -extern void cbMAIN_initBt(cbMAIN_BtInitParams *pInitParameters, cbMAIN_initBtComplete callback); - -/** - * Initialize WLAN component. - * @return Port specific TARGET identifier - */ -extern cb_int32 cbMAIN_initWlan(void); - -/** - * Start WLAN component. - * Create WLAN driver instance, bind it to targetId and start the driver. - * - * @param targetId Port specific TARGET identifier. - * @param params Start parameters passed to WLAN driver instance. - * @return cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR. - */ -extern cb_int32 cbMAIN_startWlan(cb_int32 targetId, cbMAIN_WlanStartParams *params); - -/** - * Register error handler function. - * - * @param errHandler Function to be invoked in case of error. - * @return void - */ -extern void cbMAIN_registerErrorHandler(cbMAIN_ErrorHandler errHandler); - -/** - * Start driver OS. This must be called after all cbMAIN_initOS/cbMAIN_initBt/cbMAIN_initWlan - * to start the driver thread. - * - * @return void - */ -extern void cbMAIN_startOS(void); - -/** - * Get event queue. Used for running a function in the same thread context as the driver. - * Can not be called before cbMAIN_initOS/cbMAIN_initBt/cbMAIN_initWlan. - * Use cbMAIN_dispatchEventQueue to trigger the driver to call the queued up functions. - * @return EventQueue Pointer to the event queue where function calls can be enqueued. - */ -extern EventQueue* cbMAIN_getEventQueue(void); - -/** - * Lock driver from usage. This must be used if a C API function is used outside of the driver thread context. - * The driver should only be locked for as small time as possible. - * @return void - */ -extern void cbMAIN_driverLock(void); - -/** - * Unlock driver. used when the C API function has finished executing to release the driver for others to use. - * - * @return void - */ -extern void cbMAIN_driverUnlock(void); - -/** - * Dispatch event queue. Should be called to trigger calls that have been queued up in the driver context - * - * @return void - */ -extern void cbMAIN_dispatchEventQueue(void); - -#if (BLE_STACK_UBX != true) -/** -* Initialize BT Hardware by detecting if external LPO is connected else Emulate LPO by using TIMER1 and -* configuring PORTA in alternate mode as source of external clk(LPO for BT). -* -* @return void -*/ -void cbCordio_Btinit(cordio_callback_s *bt_callback_cordio); - -/** -* Get BT address saved in OTP memory and provide it to stack for assignment. -* -* @param BdAddress Pointer to be initialized with BT address saved in OTP -* @return void -*/ -void cbCordio_Retreive_Btaddr(cb_uint8 *BdAddress); - - -/** -* Update HCI H4 UART baud-rate to 3Mbps to achieve minimum setup time. -* -* @return void -*/ -void update_uart_baud_rate(void); - -#endif /* BLE_STACK_UBX */ - -#endif /*_CB_MAIN_H_*/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h deleted file mode 100644 index 95404e3d081..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h +++ /dev/null @@ -1,72 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : OTP - * File : cb_otp.h - * - * Description : Support for One Time Programmable memory intended for - * storing production parameters such as mac addresses, trim - * values and product configuration. Writing to OTP memory shall - * only be done in a production environment. - *-------------------------------------------------------------------------*/ - -/** - * @file cb_otp.h - * @ingroup platform - */ - -#ifndef _CB_OTP_H_ -#define _CB_OTP_H_ - -#include "cb_comdefs.h" -#include "cb_status.h" - -#define cbOTP_MAX_SIZE (30) - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum -{ - cbOTP_MAC_BLUETOOTH = 1, - cbOTP_MAC_WLAN, - cbOTP_MAC_ETHERNET, - cbOTP_MAC_FEATURE_INFO, - cbOTP_MAC_DEBUG_UNIT, - cbOTP_SERIAL_NUMBER, - cbOTP_TYPE_CODE, - cbOTP_SIGNATURE, - cbOTP_MAC_WLAN_AP, - cbOTP_UUID, - cbOTP_RF_FREQ_CALIBRATION, - cbOTP_RESERVED_UNUSED = 255 -} cbOTP_Id; - - -/** - * Read a OTP parameter - * @param id The id of the parameter to write - * @param len The length of the parameter to write - * @param buf Pointer to data to be written - * @returns The read length of the id is returned. If the read fails 0 is returned - */ -cb_uint32 cbOTP_read(cbOTP_Id id, cb_uint32 len, cb_uint8 *buf); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h deleted file mode 100644 index c64e2c7b7cc..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h +++ /dev/null @@ -1,130 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Wireless LAN driver - * File : cb_types.h - * - * Description : Common definitions for a GCC compatible compiler. - *-------------------------------------------------------------------------*/ - -/** - * @file cb_types.h Defines type required for the entire driver. - * The defines in this file will have to be adapted for the platform. - * @ingroup platform - */ - -#ifndef _CB_PLATFORM_BASIC_TYPES_H_ -#define _CB_PLATFORM_BASIC_TYPES_H_ - -#include -#include - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -/*=========================================================================== - * COMMON SYSTEM DEFINES - *=========================================================================*/ - -typedef int8_t cb_int8; -typedef int16_t cb_int16; -typedef int32_t cb_int32; -typedef int64_t cb_int64; - -typedef uint8_t cb_uint8; -typedef uint16_t cb_uint16; -typedef uint32_t cb_uint32; -typedef uint64_t cb_uint64; - -typedef bool cb_boolean; -typedef char cb_char; -typedef int cb_int; - -/** - * Used when declaring an empty array that does not take up space in a struct. - * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; } - * In some compilers this is empty i.e. payload[]. While in some it requires a zero. - * I.e. payload[0]; - * Use this define to get it working for your system. - */ -#define cb_EMPTY_ARRAY (0) - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -/** - * Used in function definitions to declare an input parameter unused to avoid warnings. - */ -#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) -#define cb_UNUSED(x) UNUSED_ ## x __attribute__((unused)) -#else -#define cb_UNUSED(x) UNUSED_ ## x -#endif - - -/** - * Define cb_ASSERT to the wanted assert handler. - */ -/* -#define cb_ASSERT(exp) do { if (!(exp)) { \ - W_PRINT("ASSERT %s:%d\n", __FILE__, __LINE__); \ - while(1); \ - } } while(0) -*/ -#include "cb_assert.h" - - -/**@{*/ -/** - * Packed struct defines. - * - cb_PACKED_STRUCT_ATTR_PRE is used before the typedef'ed struct declaration. - * - cb_PACKED_STRUCT_ATTR_INLINE_PRE is after the typedef but before the struct declaration. - * - cb_PACKED_STRUCT_ATTR_INLINE_POST is used after the struct declaration but before the typedef'ed name. - * - cb_PACKED_STRUCT_ATTR_POST is used after the entire struct declaration. - * - * example: - * cb_PACKED_STRUCT_ATTR_PRE - * typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct myPackedStruct { - * int a; - * int b; - * } cb_PACKED_STRUCT_ATTR_INLINE_POST myPackedStruct - * cb_PACKED_STRUCT_ATTR_POST - * - */ - -#define cb_PACKED_STRUCT_ATTR_PRE - -#if defined(__ICCARM__) -#define cb_PACKED_STRUCT_ATTR_INLINE_PRE __packed -#else -#define cb_PACKED_STRUCT_ATTR_INLINE_PRE -#endif - -#if defined(__ICCARM__) -#define cb_PACKED_STRUCT_ATTR_INLINE_POST __packed -#else -#define cb_PACKED_STRUCT_ATTR_INLINE_POST __attribute__ ((__packed__)) -#endif - - -#define cb_PACKED_STRUCT_ATTR_POST - -/**@}*/ - - -#endif /* _CB_PLATFORM_BASIC_TYPES_H_ */ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h deleted file mode 100644 index 90b68e784a6..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h +++ /dev/null @@ -1,36 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Wireless LAN driver - * File : cb_types.h - * - * Description : Common definitions for a GCC compatible compiler. - *-------------------------------------------------------------------------*/ - -/** - * @file cb_types.h Defines type required for the entire driver. - * The defines in this file will have to be adapted for the platform. - * @ingroup platform - */ - -#ifndef _CB_PORT_TYPES_H_ -#define _CB_PORT_TYPES_H_ - -#include -#include "cb_assert.h" - - -#endif /* _CB_PORT_TYPES_H_ */ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h deleted file mode 100644 index c1c51444936..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h +++ /dev/null @@ -1,47 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : RTSL - * File : cb_status.h - * - * Description : Common RTSL status codes - *-------------------------------------------------------------------------*/ -#ifndef _CB_STATUS_H_ -#define _CB_STATUS_H_ - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -#define OK(status) (status == cbSTATUS_OK) -#define BUSY(status) (status == cbSTATUS_BUSY) -#define ERR(status) (status == cbSTATUS_ERROR) - -/*=========================================================================== - * TYPES - *=========================================================================*/ - - typedef enum - { - cbSTATUS_OK, - cbSTATUS_ERROR, - cbSTATUS_BUSY, - cbSTATUS_RECEIVE_DATA_MODE, - cbSTATUS_TIMEOUT - - } cbRTSL_Status; - -#endif /* _CB_STATUS_H_ */ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_target.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_target.h deleted file mode 100644 index 9da57e8a240..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_target.h +++ /dev/null @@ -1,178 +0,0 @@ -/** - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malm�, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : WLAN driver - * File : cb_target.h - * - * Description : OWL222a Wireless LAN module representation - *-------------------------------------------------------------------------*/ - -/** - * @file cb_target.h Handles the lowest layer of communication to the target - * before the SDIO stack. - * - * @note Create and Destroy methods are not specified here as these are not part - * of the interface used by the driver. The application should specify these - * as needed and simply supply the driver with a target handle. - * - * @ingroup port - */ - -#ifndef _CB_TARGET_H_ -#define _CB_TARGET_H_ - -#include "cb_wlan_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbTARGET_SDIO_BLOCK_SIZE (256) - -/*=========================================================================== - * TYPES - *=========================================================================*/ -typedef struct cbTARGET_Handle cbTARGET_Handle; - -typedef struct cbTARGET_FunctionHandle cbTARGET_FunctionHandle; - -typedef void(*cbTARGET_ISRHandler)(void* hCallback); - - -typedef enum { - cbTARGET_CBTYPE_IRQ, - cbTARGET_CBTYPE_START, - cbTARGET_CBTYPE_STOP, -} cbTARGET_CallbackType; - -typedef enum cbTARGET_SDIO_Function { - cbTARGET_SDIO_FUNCTION_0, - cbTARGET_SDIO_FUNCTION_1, - cbTARGET_SDIO_FUNCTION_2, - cbTARGET_SDIO_FUNCTION_3, - cbTARGET_SDIO_FUNCTION_4, - cbTARGET_SDIO_FUNCTION_5, - cbTARGET_SDIO_FUNCTION_6, - cbTARGET_SDIO_FUNCTION_7, -} cbTARGET_SDIO_Function; - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Map/resolve target handle from port specific identifier. - * - * @param targetId Port specific target identifier. - * @return Target handle matching target identifier. - */ -cbTARGET_Handle *cbTARGET_targetResolve(cb_int32 targetId); - -/** - * Perform a hardware reset of the TARGET. - */ -void cbTARGET_reset(cbTARGET_Handle *hTarget); - -/** - * Register a interrupt handler with the TARGET. - */ -void cbTARGET_registerISRHandler(cbTARGET_Handle *hTarget, cbTARGET_ISRHandler handler, void* hContext); - - -/** - * Initiate a SDIO function and return a controlling object. - * - * @param hTarget Handle to target object. - * @param func SDIO function to initiate. - * @return Handle to a SDIO function object. - */ -cbTARGET_FunctionHandle* cbTARGET_initFunction(cbTARGET_Handle *hTarget, cbTARGET_SDIO_Function func); - -/** - * Write a buffer to the target using SDIO FIFO access. - * - * @param hFunction Handle to a SDIO target function object. - * @param address SDIO address. - * @param data Send buffer. - * @param dataSize Number of valid data bytes in transfer. - * @return True if successful, otherwise FALSE. - */ -cb_boolean cbTARGET_FIFOWrite(cbTARGET_FunctionHandle* hFunction, cb_uint32 address, cb_uint8* data, cb_uint32 dataSize); - -/** - * Read from the target into a buffer using SDIO FIFO access. - * - * @param hFunction Handle to a SDIO target function object. - * @param address SDIO address. - * @param data Receive buffer. - * @param dataSize Number of valid data bytes in transfer. - * @return TRUE if successful, otherwise FALSE. - */ -cb_boolean cbTARGET_FIFORead(cbTARGET_FunctionHandle* hFunction, cb_uint32 address, cb_uint8* data, cb_uint32 dataSize); - -/** - * Write a buffer to the target. - * - * @param hFunction Handle to a SDIO target function object. - * @param address SDIO address. - * @param data Send buffer. - * @param dataSize Number of valid data bytes in transfer. - * @return True if successful, otherwise FALSE. - */ -cb_boolean cbTARGET_write(cbTARGET_FunctionHandle* hFunction, cb_uint32 address, cb_uint8* data, cb_uint32 dataSize); - -/** - * Read from the target into a buffer. - * - * @param hFunction Handle to a SDIO target function object. - * @param address SDIO address. - * @param data Receive buffer. - * @param dataSize Number of valid data bytes in transfer. - * @return TRUE if successful, otherwise FALSE. - */ -cb_boolean cbTARGET_read(cbTARGET_FunctionHandle* hFunction, cb_uint32 address, cb_uint8* data, cb_uint32 dataSize); - -/** - * Write a single byte to the function 0 of the SDIO target. - * - * @param hTarget Handle to target object. - * @param address SDIO address. - * @param data Send buffer. - * @return True if successful, otherwise FALSE. - */ -cb_boolean cbTARGET_f0_writeByte(cbTARGET_Handle *hTarget, cb_uint32 address, cb_uint8 data); - -/** - * Read a single byte from the function 0 of the SDIO target. - * - * @param hTarget Handle to target object. - * @param address SDIO address. - * @param data Receive buffer. - * @return TRUE if successful, otherwise FALSE. - */ -cb_boolean cbTARGET_f0_readByte(cbTARGET_Handle *hTarget, cb_uint32 address, cb_uint8 *data); - - -cb_uint16 cbTARGET_getBlockSize(cbTARGET_Handle *hTarget); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h deleted file mode 100644 index 923639182ff..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h +++ /dev/null @@ -1,287 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : RTSL - * File : cb_types.h - * - * Description : Common type definitions - *-------------------------------------------------------------------------*/ - -/** - * @file cb_types.h Defines type required for the entire driver. - * The defines in this file will have to be adapted for the platform. - * @ingroup platform - */ - -#ifndef _CB_TYPES_H_ -#define _CB_TYPES_H_ - -#include "cb_port_types.h" - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -/*=========================================================================== - * COMMON SYSTEM DEFINES - *=========================================================================*/ - -#ifndef FALSE -# define FALSE (0) -#endif -#ifndef TRUE -# define TRUE (!FALSE) -#endif - -#ifndef NULL -# define NULL ((void *) 0) -#endif - -/** - * Returns the maximum value of the two parameters. - */ -#ifndef cb_MAX -# define cb_MAX(x , y) (((x) > (y)) ? (x) : (y)) -#endif -/** - * Returns the minimum value of the two parameters. - */ -#ifndef cb_MIN -# define cb_MIN(x , y) (((x) < (y)) ? (x) : (y)) -#endif - -#ifndef ELEMENTS_OF -# define ELEMENTS_OF(_array) (sizeof((_array)) / sizeof((_array)[0])) -#endif - -#define cbWM_ARRAY_SIZE(a) ELEMENTS_OF(a) - -/** - * Used when declaring an empty array that does not take up space in a struct. - * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; } - * In some compilers this is empty i.e. payload[]. While in some it requires a zero. - * I.e. payload[0]; - * Use this define to get it working for your system. - */ -#ifndef cb_EMPTY_ARRAY -# define cb_EMPTY_ARRAY (0) -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -/** - * Used in function definitions to declare an inparameter unused to avoid warnings. - */ -#ifndef cb_UNUSED -# define cb_UNUSED(x) x -#endif - -#ifndef cb_ASSERT -# error "No port definition for ASSERT!" -#endif - -#ifndef cb_ARG_POINTER_CHECK -# define cb_ARG_POINTER_CHECK(ptr) if((ptr) == NULL) {cb_ASSERT(FALSE); return;} -#endif -#ifndef cb_ARG_POINTER_CHECK_RETURN -# define cb_ARG_POINTER_CHECK_RETURN(ptr, returnValue) if((ptr) == NULL) {cb_ASSERT(FALSE); return (returnValue);} -#endif - -#ifndef cb_BIT_0 -#define cb_BIT_0 (1ul) -#endif -#ifndef cb_BIT_1 -#define cb_BIT_1 (1ul << 1) -#endif -#ifndef cb_BIT_2 -#define cb_BIT_2 (1ul << 2) -#endif -#ifndef cb_BIT_3 -#define cb_BIT_3 (1ul << 3) -#endif -#ifndef cb_BIT_4 -#define cb_BIT_4 (1ul << 4) -#endif -#ifndef cb_BIT_5 -#define cb_BIT_5 (1ul << 5) -#endif -#ifndef cb_BIT_6 -#define cb_BIT_6 (1ul << 6) -#endif -#ifndef cb_BIT_7 -#define cb_BIT_7 (1ul << 7) -#endif -#ifndef cb_BIT_8 -#define cb_BIT_8 (1ul << 8) -#endif -#ifndef cb_BIT_9 -#define cb_BIT_9 (1ul << 9) -#endif -#ifndef cb_BIT_10 -#define cb_BIT_10 (1ul << 10) -#endif -#ifndef cb_BIT_11 -#define cb_BIT_11 (1ul << 11) -#endif -#ifndef cb_BIT_12 -#define cb_BIT_12 (1ul << 12) -#endif -#ifndef cb_BIT_13 -#define cb_BIT_13 (1ul << 13) -#endif -#ifndef cb_BIT_14 -#define cb_BIT_14 (1ul << 14) -#endif -#ifndef cb_BIT_15 -#define cb_BIT_15 (1ul << 15) -#endif -#ifndef cb_BIT_16 -#define cb_BIT_16 (1ul << 16) -#endif -#ifndef cb_BIT_17 -#define cb_BIT_17 (1ul << 17) -#endif -#ifndef cb_BIT_18 -#define cb_BIT_18 (1ul << 18) -#endif -#ifndef cb_BIT_19 -#define cb_BIT_19 (1ul << 19) -#endif -#ifndef cb_BIT_20 -#define cb_BIT_20 (1ul << 20) -#endif -#ifndef cb_BIT_21 -#define cb_BIT_21 (1ul << 21) -#endif -#ifndef cb_BIT_22 -#define cb_BIT_22 (1ul << 22) -#endif -#ifndef cb_BIT_23 -#define cb_BIT_23 (1ul << 23) -#endif -#ifndef cb_BIT_24 -#define cb_BIT_24 (1ul << 24) -#endif -#ifndef cb_BIT_25 -#define cb_BIT_25 (1ul << 25) -#endif -#ifndef cb_BIT_26 -#define cb_BIT_26 (1ul << 26) -#endif -#ifndef cb_BIT_27 -#define cb_BIT_27 (1ul << 27) -#endif -#ifndef cb_BIT_28 -#define cb_BIT_28 (1ul << 28) -#endif -#ifndef cb_BIT_29 -#define cb_BIT_29 (1ul << 29) -#endif -#ifndef cb_BIT_30 -#define cb_BIT_30 (1ul << 30) -#endif -#ifndef cb_BIT_31 -#define cb_BIT_31 (1ul << 31) -#endif - -#ifndef cb_UINT8_MAX -#define cb_UINT8_MAX ((cb_uint8)0xff) -#endif -#ifndef cb_UINT16_MAX -#define cb_UINT16_MAX ((cb_uint16)0xffff) -#endif -#ifndef cb_UINT32_MAX -#define cb_UINT32_MAX ((cb_uint32)0xffffffff) -#endif -#ifndef cb_INT8_MAX -#define cb_INT8_MAX ((cb_uint8)0x7f) -#endif -#ifndef cb_INT16_MAX -#define cb_INT16_MAX ((cb_uint16)0x7fff) -#endif -#ifndef cb_INT32_MAX -#define cb_INT32_MAX ((cb_uint32)0x7fffffff) -#endif -#ifndef cb_INT8_MIN -#define cb_INT8_MIN ((cb_uint8)0x80) -#endif -#ifndef cb_INT16_MIN -#define cb_INT16_MIN ((cb_uint16)0x8000) -#endif -#ifndef cb_INT32_MIN -#define cb_INT32_MIN ((cb_uint32)0x80000000) -#endif - -/** - * Clears (set to zero) a bit or bits in a variable. - * @param variable The variable. - * @param bit The bit or bits to clear - */ -#ifndef cb_CLEAR_BIT -# define cb_CLEAR_BIT(variable,bit) ((variable) &= ~((bit))) -#endif - -/** - * Gets a bit i.e. checks if it is set in a variable. - * - * Also works to see if any of several bits are set. - * - * @param variable The variable. - * @param bit The bit to check if it set. - * @return @ref TRUE if any of the bits are set, @ref FALSE otherwise. - */ -#ifndef cb_GET_BIT -# define cb_GET_BIT(variable,bit) (((variable) & ((bit))) ? TRUE : FALSE) -#endif - -/** - * Sets (set to 1) a bit or bits in a variable. - * - * @param variable The variable. - * @param bit The bit or bits to set in the variable. - */ -#ifndef cb_SET_BIT -# define cb_SET_BIT(variable,bit) ((variable) |= (bit)) -#endif - - -/*Packed struct defines*/ -#ifndef cb_PACKED_STRUCT_ATTR_INLINE_POST -# define cb_PACKED_STRUCT_ATTR_INLINE_POST -#endif -#ifndef cb_PACKED_STRUCT_ATTR_INLINE_PRE -# define cb_PACKED_STRUCT_ATTR_INLINE_PRE -#endif -#ifndef cb_PACKED_STRUCT_ATTR_PRE -# define cb_PACKED_STRUCT_ATTR_PRE -#endif -#ifndef cb_PACKED_STRUCT_ATTR_POST -# define cb_PACKED_STRUCT_ATTR_POST -#endif - -#ifndef cb_PACKED_STRUCT_BEGIN -# define cb_PACKED_STRUCT_BEGIN(name) \ - cb_PACKED_STRUCT_ATTR_PRE \ - typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct name -#endif - -#ifndef cb_PACKED_STRUCT_END -# define cb_PACKED_STRUCT_END(name) \ - cb_PACKED_STRUCT_ATTR_INLINE_POST name; \ - cb_PACKED_STRUCT_ATTR_POST -#endif - -#endif /* _CB_TYPES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h deleted file mode 100644 index dd500225c45..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h +++ /dev/null @@ -1,71 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component: Watchdog - * File: cb_watchdog.h - * - * Description: Functionality for watchdog and reset. - *-------------------------------------------------------------------------*/ -#ifndef _CB_WATCHDOG_H_ -#define _CB_WATCHDOG_H_ - -#include "cb_comdefs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -/*=========================================================================== - * TYPES - *=========================================================================*/ - - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Put watchdog in a defined state. - */ -void cbWD_init(void); - -/** - * Resets the CPU. - */ -void cbWD_systemReset(void); - -/** - * Enables watchdog. Watchdog needs to be polled using cbWD_poll() with - * shorter intervals then specified by timeInMilliseconds. - * - * @param timeInMilliseconds Watchdog timeout in milliseconds. - */ -void cbWD_enable(cb_uint32 timeInMilliseconds); - -/** - * Poll the watchdog timer. This must be done with shorter intervalls - * than the time in cbWD_enable(). - */ -void cbWD_poll(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _CB_WATCHDOG_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h deleted file mode 100644 index a8c62cbe003..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h +++ /dev/null @@ -1,605 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : WLAN - * File : cb_wlan.h - * - * Description : Main WLAN component, ties together WM, SUPPLICANT and - * TARGET to one streamlined API. - *-------------------------------------------------------------------------*/ - -/** - * @file cb_wlan.h The main WLAN component interface. - * All functions declared extern needs to be provided by another/upper layer. - * @ingroup wlan - */ - -#ifndef _CB_WLAN_H_ -#define _CB_WLAN_H_ - -#include "cb_types.h" -#include "cb_wlan_types.h" -#include "cb_cert_utils.h" -#include "cb_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -/** - * Max username length in @ref cbWLAN_EnterpriseConnectParameters - * - * @ingroup wlan - */ -#define cbWLAN_MAX_USERNAME_LENGTH 32 - -/** - * Max password length in @ref cbWLAN_Util_PSKFromPWD and @ref cbWLAN_EnterpriseConnectParameters - * - * @ingroup wlan - */ -#define cbWLAN_MAX_PASSPHRASE_LENGTH 64 - -/** - * PSK length in @ref cbWLAN_WPAPSKConnectParameters - * - * @ingroup wlan - */ -#define cbWLAN_PSK_LENGTH 32 - - -/** - * Max domain name length in @ref cbWLAN_EnterpriseConnectParameters - * - * @ingroup wlan - */ -#define cbWLAN_MAX_DOMAIN_LENGTH 64 - -/** - * Size of the misc buffer in @ref cbWM_ChangeBSS and @ref cbWM_StartFT. - * - * @ingroup types - */ -#define MISC_BUFFER_SIZE 255 - -#define cbWLAN_FTIE_SIZE 255 -#define cbWLAN_RSNIE_SIZE 44 -#define cbWLAN_MDIE_SIZE 5 - -#define cbWLAN_DEFAULT_HANDLE ((cbWLAN_Handle)1) -#define cbWLAN_INVALID_HANDLE (cb_UINT32_MAX) -/*=========================================================================== - * TYPES - *=========================================================================*/ -typedef cb_uint32 cbWLAN_Handle; -/** - * Start parameters passed to WLAN driver. - * - * @ingroup wlan - */ -typedef struct cbWLAN_StartParameters { - cbWLAN_MACAddress mac; /**< MAC of WLAN interface, set to all zeros if hardware programmed address should be used. */ - cbWM_ModuleType deviceType; /**< Specify current device type. */ - union { - struct { - cbWM_TxPowerSettings txPowerSettings; /**< Transmission power settings. */ - cb_uint8 numberOfAntennas; /**< Number of antennas use for wifi (MIMO supports 2x2). */ - cb_uint8 primaryAntenna; /**< Primary antenna selection. */ - } ODIN_W26X; - } deviceSpecific; -} cbWLAN_StartParameters; - -/** - * Common connect parameters. - * - * @ingroup wlan - */ -typedef struct cbWLAN_CommonConnectParameters { - cbWLAN_MACAddress bssid; /**< BSSID to connect to, set to all zero for any BSSID. */ - cbWLAN_Ssid ssid; /**< SSID to connect to. */ -} cbWLAN_CommonConnectParameters; - - -/** - * WEP specific connect parameters. - * - * @ingroup wlan - */ -typedef struct cbWLAN_WEPConnectParameters { - cbWLAN_WEPKey keys[4]; /**< WEP keys. */ - cb_uint32 txKey; /**< Active WEP transmission key index (0-3). */ -} cbWLAN_WEPConnectParameters; - -/** -* WPA PSK parameters. -* -* @ingroup wlan -*/ -typedef struct cbWLAN_WPAPSK { - cb_uint8 key[cbWLAN_PSK_LENGTH]; /**< WPA pre-shared key in binary form. */ -} cbWLAN_WPAPSK; - -/** - * WPA PSK specific connect parameters. - * - * @ingroup wlan - */ -typedef struct cbWLAN_WPAPSKConnectParameters { - cbWLAN_WPAPSK psk; /**< WPA pre-shared key*/ -} cbWLAN_WPAPSKConnectParameters; - -#if defined(CB_FEATURE_802DOT11R) -/** - * Associate information elements with FT elements. - * - * @ingroup wlan - */ -typedef struct cbWLAN_AssociateInformationElements{ - cb_uint8 wpaIe[cbWLAN_RSNIE_SIZE]; - cb_uint32 wpaIeLen; - cb_uint8 mdIe[cbWLAN_MDIE_SIZE]; - cb_uint32 mdIeLen; - cb_uint8 ftIe[cbWLAN_FTIE_SIZE]; - cb_uint32 ftIeLen; -} cbWLAN_AssociateInformationElements; -#endif - -#if defined(CB_FEATURE_802DOT11W) -/** -* 80211w PMF specific connect parameters. -* -* @ingroup wlan -*/ -typedef struct cbWLAN_PMFApParameters { - cbWLAN_PMF pmf; /**< MFPR, MFPC RSN capabilties*/ - cb_uint8 comeBackTime; /**< 1 - 10 sec */ - cb_uint16 saQueryTimeOut; /**< 100 - 500 msec */ -} cbWLAN_PMFApParameters; -#endif - -/** - * WPA Enterprise specific connect parameters. - * - * @ingroup wlan - */ -typedef struct cbWLAN_EnterpriseConnectParameters { - cbWLAN_EnterpriseMode authMode; /**< Enterprise authentication mode. */ - cb_uint8 username[cbWLAN_MAX_USERNAME_LENGTH]; /**< Username string. */ - cb_uint8 passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH]; /**< Passphrase string. */ - cb_uint8 domain[cbWLAN_MAX_DOMAIN_LENGTH]; /**< Domain string. */ - cbCERT_Stream *clientCertificate; /**< Stream handle to provide SSL certificate for authentication. */ - cbCERT_Stream *clientPrivateKey; /**< Stream handle to provide SSL private key for authentication. */ - cbCERT_Stream *CACertificate; /**< Stream handle to provide CA certificate for server certificate validation, - Can be NULL if server certificate shouldn't be validated. */ -} cbWLAN_EnterpriseConnectParameters; - -/** - * Common access point parameters. - * - * @ingroup wlan - */ -typedef struct cbWLAN_CommonApParameters { - cbWLAN_Ssid ssid; /**< SSID to connect to. */ - cbWLAN_Channel channel; /**< Active channel. */ - cbWLAN_RateMask basicRates; /**< Basic rates. */ - cbWLAN_RateMask allowedRates; /**< BSS allowed rates. */ - cb_uint8 dtimInterval; /**< Dtim Interval. */ -} cbWLAN_CommonApParameters; - - -/** -* WPA PSK specific AP parameters. -* -* @ingroup wlan -*/ -typedef struct cbWLAN_WPAPSKApParameters { - cbWLAN_CipherSuite rsnCiphers; /**< Bit field indicating which ciphers that shall be displayed in RSN information elements. If 0 no RSN information elements is added to beacons and probe responses. */ - cbWLAN_CipherSuite wpaCiphers; /**< Bit field indicating which ciphers that shall be displayed in WPA information elements. If 0 no WPA information elements is added to beacons and probe responses. */ - cbWLAN_WPAPSK psk; /**< WPA pre-shared key*/ -#if defined(CB_FEATURE_802DOT11W) - cbWLAN_PMFApParameters pmfParameters; -#endif - cb_uint32 gtkRekeyInterval; /**< Group rekey interval in seconds */ -} cbWLAN_WPAPSKApParameters; - -/** - * Scan parameters - * - * @ingroup wlan - */ -typedef struct cbWLAN_ScanParameters { - cbWLAN_Ssid ssid; /**< SSID to scan for, set to zero length for broadcast scan. */ - cbWLAN_Channel channel; -} cbWLAN_ScanParameters; - -/** - * Scan result information reported from WLAN component. Contains info for - * one specific BSS. - * - * @ingroup wlan - */ -typedef struct cbWLAN_ScanIndicationInfo { - cbWLAN_MACAddress bssid; /**< BSS BSSID */ - cbWLAN_Ssid ssid; /**< BSS SSID */ - cbWLAN_Channel channel; /**< BSS channel */ - cbWLAN_OperationalMode operationalMode; /**< BSS type */ - cb_int32 rssi; /**< RSSI for scan result packet. */ - - cbWLAN_AuthenticationSuite authenticationSuites; /**< Supported authentication suites */ - cbWLAN_CipherSuite unicastCiphers; /**< Supported unicast cipher suites */ - cbWLAN_CipherSuite groupCipher; /**< Supported group cipher suites */ -#if defined(CB_FEATURE_802DOT11R) - cbWLAN_MDInformation mobilityDomainId; /**< Mobility Domain Id and Ft capability policy>*/ -#endif - cbWLAN_RateMask basicRateSet; /**< Basic rate set, i.e. required rates. */ - cbWLAN_RateMask supportedRateSet; /**< Supported rate set, super set of basic rate set. */ - cb_uint32 beaconPeriod; /**< Beacon period in ms. */ - cb_uint32 DTIMPeriod; /**< DTIM period in beacon intervals */ - cb_uint8 countryCode[2]; /**< Two letter country code */ - cb_uint32 flags; /**< QoS, short preamble, DFS, privacy */ - cb_uint16 RSNCapabilities; /**< Protected management frames capabilities*/ -} cbWLAN_ScanIndicationInfo; - -/** - * Status indications indicated by @ref cbWLAN_statusIndication. - * - * @ingroup wlan - */ -typedef enum { - cbWLAN_STATUS_STOPPED, - cbWLAN_STATUS_STARTED, - cbWLAN_STATUS_ERROR, - cbWLAN_STATUS_DISCONNECTED, - cbWLAN_STATUS_CONNECTING, - cbWLAN_STATUS_CONNECTED, - cbWLAN_STATUS_CONNECTION_FAILURE, - cbWLAN_STATUS_AP_UP, - cbWLAN_STATUS_AP_DOWN, - cbWLAN_STATUS_AP_STA_ADDED, - cbWLAN_STATUS_AP_STA_REMOVED, - cbWLAN_STATUS_80211r_REASSOCIATING, - cbWLAN_STATUS_80211r_REASSOCIATED, -} cbWLAN_StatusIndicationInfo; - -/** - * Disconnection reasons for @ref cbWLAN_STATUS_DISCONNECTED. - * - * @ingroup wlan - */ -typedef enum { - cbWLAN_STATUS_DISCONNECTED_UNKNOWN = 0x00, - cbWLAN_STATUS_DISCONNECTED_NO_BSSID_FOUND, - cbWLAN_STATUS_DISCONNECTED_ASSOC_FAILURE, - cbWLAN_STATUS_DISCONNECTED_AUTH_FAILURE, - cbWLAN_STATUS_DISCONNECTED_MIC_FAILURE, - cbWLAN_STATUS_DISCONNECTED_ROAMING, -} cbWLAN_StatusDisconnectedReason; - -/** - * IOCTL parameters @ref cbWLAN_ioctl - * - * @ingroup wlan - */ -typedef enum { - cbWLAN_IOCTL_FIRST = 0, - cbWLAN_IOCTL_SET_AP_BEACON_INTERVAL = 9, //!< Beacon period in TUs - cbWLAN_IOCTL_GET_AP_BEACON_INTERVAL = 10, //!< Beacon period in TUs -} cbWLAN_Ioctl; - - -/** - * Start parameters indicated from WLAN driver for status indication - * @ref cbWLAN_STATUS_STARTED. - * - * @ingroup wlan - */ -typedef struct cbWLAN_StatusStartedInfo { - cbWLAN_MACAddress macAddress; /**< MAC address of WLAN driver. */ -} cbWLAN_StatusStartedInfo; - -/** - * Disconnected parameters indicated from WLAN driver for status indication - * @ref cbWLAN_STATUS_DISCONNECTED. - * - * @ingroup wlan - */ -typedef struct cbWLAN_StatusDisconnectedInfo { - cbWLAN_Handle handle; /**< Handle returned by cbWLAN_connectXXX */ - cbWLAN_StatusDisconnectedReason reason; -} cbWLAN_StatusDisconnectedInfo; - -/** - * Connected parameters indicated from WLAN driver for status indication - * @ref cbWLAN_STATUS_CONNECTED. - * - * @ingroup wlan - */ -typedef struct cbWLAN_StatusConnectedInfo { - cbWLAN_Handle handle; /**< Handle returned by cbWLAN_connectXXX */ - cbWLAN_MACAddress bssid; /**< BSSID of the BSS connected to. */ - cbWLAN_Channel channel; /**< Operating channels of the BSS connected to. */ - cb_uint16 mobilityDomainId; -} cbWLAN_StatusConnectedInfo; - -/** - * Received Ethernet data packet information and properties. - * - * @ingroup wlan - */ -typedef struct cbWLAN_PacketIndicationInfo { - void *rxData; /**< Pointer to the port specific data type. */ - cb_uint32 size; /**< Length of the data payload in the port specific packet data type. */ - cb_boolean isChecksumVerified; /**< True if the TCP/UDP checksum is verified and correct. */ -} cbWLAN_PacketIndicationInfo; - -/** - * Status updates from WLAN component. - * @note The callback must not make any call back to WLAN. - * - * @param callbackContext Context pointer provided in @ref cbWLAN_registerStatusCallback. - * @param status Status indication type. - * @param data Additional status indication data, depends on indication type. - * - * @sa cbWLAN_registerStatusCallback - */ -typedef void (*cbWLAN_statusIndication)(void *callbackContext, cbWLAN_StatusIndicationInfo status, void *data); - - -/** - * Indication of received Ethernet data packet. - * - * @param callbackContext Context pointer provided in @ref cbWLAN_registerPacketIndicationCallback. - * @param packetInfo Pointer to struct containing packet information and data pointers. - */ -typedef void (*cbWLAN_packetIndication)(void *callbackContext, cbWLAN_PacketIndicationInfo *packetInfo); - -/** -* Scan result indication from WLAN component. -* -* @param callbackContext Context pointer provided in @ref cbWLAN_scan. -* @param bssDescriptor Pointer to struct containing scan result information. -* @param isLastResult @ref TRUE if scan scan is finished. -*/ -typedef void (*cbWLAN_scanIndication)(void *callbackContext, cbWLAN_ScanIndicationInfo *bssDescriptor, cb_boolean isLastResult); - -/*=========================================================================== - * WLAN API - *=========================================================================*/ - -/** - * Initialize WLAN component. - * - * @return @ref cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_init(); - - -/** - * Stop WLAN component. - * Stop and destroy WLAN driver instance. - * - * @return @ref cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_stop(void); - -/** -* Connect to access point in open mode (no encryption). -* Connection progress is reported as @ref cbWLAN_statusIndication callbacks. -* -* @param commonParams Connection parameters. -* @return @ref cbWLAN_Handle if call successful, otherwise -1. -*/ -cbWLAN_Handle cbWLAN_connectOpen(cbWLAN_CommonConnectParameters *commonParams); - -/** -* Connect to access point in open mode with WEP encryption. -* Connection progress is reported as @ref cbWLAN_statusIndication callbacks. -* -* @param commonParams Connection parameters. -* @param wepParams WEP specific connection parameters. -* @return @ref cbWLAN_Handle if call successful, otherwise -1. -*/ -cbWLAN_Handle cbWLAN_connectWEP(cbWLAN_CommonConnectParameters *commonParams, cbWLAN_WEPConnectParameters *wepParams); - -/** -* Connect to access point with WPA PSK authentication. -* Connection progress is reported as @ref cbWLAN_statusIndication callbacks. -* -* @param commonParams Connection parameters. -* @param wpaParams WPA PSK specific connection parameters. -* @return @ref cbWLAN_Handle if call successful, otherwise -1. -*/ -cbWLAN_Handle cbWLAN_connectWPAPSK(cbWLAN_CommonConnectParameters *commonParams, cbWLAN_WPAPSKConnectParameters *wpaParams); - -/** -* Connect to access point with WPA Enterprise authentication. -* Connection progress is reported as @ref cbWLAN_statusIndication callbacks. -* -* @param commonParams Connection parameters. -* @param enterpriseParams WPA Enterprise specific connection parameters. -* @return @ref cbWLAN_Handle if call successful, otherwise -1. -*/ -cbWLAN_Handle cbWLAN_connectEnterprise(cbWLAN_CommonConnectParameters *commonParams, cbWLAN_EnterpriseConnectParameters *enterpriseParams); - -/** - * Disconnect from access point or stop ongoing connection attempt. - * Disconnection progress is reported as @ref cbWLAN_statusIndication callback. - * - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_disconnect(cbWLAN_Handle handle); - -/** - * Initiate BSS scan. - * If specific channel is set in scan parameters, only that channel is - * scanned. If SSID is specified, a directed probe request against that SSID - * will be used. Scan results are reported in @ref cbWLAN_scanIndication - * callbacks. - * @note Depending on channel using DFS or not, passive scans may be used - * instead of active probe requests. - * - * @param params Scan parameters - * @param scanIndication Callback function for scan results. - * @param callbackContext Context pointer, will be sent back in callback. - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_scan(cbWLAN_ScanParameters *params, cbWLAN_scanIndication scanIndication, void *callbackContext); - - -/** -* Retrieve an RSSI value for station mode. -* -* @note Depending on connection state and data transfer interval -* the value may be incorrect. -* -* @return RSSI value in dBm -*/ -cb_int16 cbWLAN_STA_getRSSI(); - -/** -* Start access point in open mode (no encryption). -* Connection progress is reported as @ref cbWLAN_statusIndication callbacks. -* -* @param commonParams Common Accesspoint parameters. -* @return @ref cbWLAN_Handle if call successful, otherwise -1. -*/ -cbWLAN_Handle cbWLAN_apStartOpen(cbWLAN_CommonApParameters *commonParams); - -/** -* Start access point with WPA PSK authentication. -* Connection progress is reported as @ref cbWLAN_statusIndication callbacks. -* -* @param commonParams Common Accesspoint parameters. -* @param wpaParams WPA PSK specific parameters. -* @return @ref cbWLAN_Handle if call successful, otherwise -1. -*/ -cbWLAN_Handle cbWLAN_apStartWPAPSK(cbWLAN_CommonApParameters *commonParams, cbWLAN_WPAPSKApParameters *wpaParams); - -/** - * Stop access point. - * - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_apStop(cbWLAN_Handle handle); - -/** - * Send an Ethernet data packet. - * @note Data send when not in connected state is just dropped. - * - * @param txData Pointer to the port specific Ethernet data type containing transmit data - */ -void cbWLAN_sendPacket(cbWLAN_Handle handle, void *txData); - -/** - * Register a status indication callback. - * @note There may be multiple clients connected. - * - * @param statusIndication Callback function. - * @param callbackContext Context pointer, will be sent back in callback. - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_registerStatusCallback(cbWLAN_statusIndication statusIndication, void *callbackContext); - - -/** - * Register a status indication callback. - * - * @param packetIndication Callback function. - * @param callbackContext Context pointer, will be sent back in callback. - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_registerPacketIndicationCallback(cbWLAN_Handle handle, cbWLAN_packetIndication packetIndication, void *callbackContext); - -/** - * Deregister the specified status indication callback. - * - * @param statusIndication Callback function. - * @param callbackContext Context pointer, will be sent back in callback. - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_deregisterStatusCallback(cbWLAN_statusIndication statusIndication, void *callbackContext); - - -cbRTSL_Status cbWLAN_Util_PSKFromPWD(cb_char passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH], cbWLAN_Ssid ssid, cb_uint8 psk[cbWLAN_PSK_LENGTH]); - -/** - * Set the channel list to be used for connection and scanning. - * The list will be filtered according to the allowed channel list - * set. The list can include both 2.4GHz and 5GHz channels. - * If channel list parameter is NULL the default channel list is - * restored. - * - * @param channelList Pointer to channel list for the driver to use. - * - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_setChannelList(const cbWLAN_ChannelList *channelList); - -/** - * Returns the wanted channel list. - * - * @param channelList Pointer to channel list - * - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_getChannelList(cbWLAN_ChannelList *channelList); - -/** - * Returns the channel list currently used. This channel list - * depend on the channel list specified by the user and the - * current regulatory domain. - * - * @param channelList Pointer to channel list - * - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_getActiveChannelList(cbWLAN_ChannelList *channelList); - -/** - * WLAN control settings. Both in and out parameters are supported. - * If an ioctl request is not supported cbSTATUS_ERROR is returned and - * the value parameter shall be ignored. - * - * @param ioctl Parameter that shall be set. @ref cbWLAN_Ioctl lists all supported parameters. - * @param value Value. @ref cbWLAN_Ioctl lists the type for all supported parameters. - * - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_ioctl(cbWLAN_Ioctl ioctl, void* value); - -cbRTSL_Status cbWLAN_getVersion(cbWM_Version* version); - -#if defined(CB_FEATURE_802DOT11R) - -/** - * Called for changing the BSS - * - * @param params Parameter containing the BSS parameters. - * - * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. - */ -cbRTSL_Status cbWLAN_changeBSS(cbWLAN_BSSChangeParameters params); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* _CB_WLAN_H_ */ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_driver_config.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_driver_config.h deleted file mode 100644 index 2aad3e7d672..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_driver_config.h +++ /dev/null @@ -1,344 +0,0 @@ -/** - *--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malm�, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * Component : Wireless LAN driver - * File : cb_wlan_driver_config.h - * - * Description : OS related functions - *-------------------------------------------------------------------------*/ -/** - * @file cb_wlan_driver_config.h Driver configuration. - * @ingroup port - */ -#ifndef _CB_WLAN_DRIVER_CONFIG_H_ -#define _CB_WLAN_DRIVER_CONFIG_H_ - -#include -#include -#include -#include "cb_target.h" -#include "cb_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbWLAN_ENABLE_802_11b -#define cbWLAN_ENABLE_802_11g -#define cbWLAN_ENABLE_802_11n - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -#define cbTARGET_GSETTING_4_ADDRESS_MODE_STATION_DYNAMIC cb_BIT_0 -#define cbTARGET_GSETTING_4_ADDRESS_MODE_STATION_ALWAYS cb_BIT_1 -/** - * General settings and tuning parameters . - * - * @ingroup types - */ -typedef enum wm_gsetting_e { - cbTARGET_GSETTING_START = 0, - cbTARGET_GSETTING_PREAMBLE = cbTARGET_GSETTING_START, /**< 0 = Long preamble, 1 = Short preamble */ - cbTARGET_GSETTING_MIN_SCAN_TIME, /**< Minimum scan time in TU per channel */ - cbTARGET_GSETTING_MAX_SCAN_TIME, /**< Maximum scan time in TU per channel */ - cbTARGET_GSETTING_SCAN_TYPE, /**< Use @ref cbWM_ScanType. */ - cbTARGET_GSETTING_BEACON_INTERVAL, /**< Beacon interval for Ad-hoc/IBSS networks. */ - cbTARGET_GSETTING_JOIN_FAILURE_TIMEOUT, /**< Time in beacons before the join procedure times out. */ - cbTARGET_GSETTING_BT_COEX, /**< Bluetooth co-existence 0 = off, 1 = on */ - cbTARGET_GSETTING_DATA_RATE, /**< Set the data rate to use. Use @ref cbWLAN_Rate */ - cbTARGET_GSETTING_LINK_ADAPTION, /**< Dynamically adapt the data rate. 0 = off, 1 = on */ - cbTARGET_GSETTING_POWER_SAVE, /**< 0 = off, 1 = Fast PSP, 2 = Max PSP */ - cbTARGET_GSETTING_DTIM_ENABLE, /**< Enable DTIM when powersaving */ - cbTARGET_GSETTING_QOS_ENABLE, /**< Enable QoS */ - cbTARGET_GSETTING_RTS_THRESHOLD, /**< Set the RTS (Request to send) threshold */ - cbTARGET_GSETTING_FRAGMENTATION_THRESHOLD, /**< Set the fragmentation threshold */ - cbTARGET_GSETTING_TX_POWER, /**< Desired output power in dBm. */ - cbTARGET_GSETTING_MAX_PASSIVE_SCAN_TIME, /**< Maximum scan time for passive scan */ - cbTARGET_GSETTING_MODULE_TYPE, /**< Type of module. TODO: remove. Legacy parameter that shouldn't be possible to change. */ - cbTARGET_GSETTING_SCAN_LISTEN_INTERVAL, /**< Listen interval between channel scans */ - cbTARGET_GSETTING_SLEEP_TIMEOUT, /**< Only allow power save modes after this period of inactivity. Timeout in ms. Only used when power save is enabled */ - cbTARGET_GSETTING_DOT11_SHORT_RETRY_LIMIT, /**< 802.11 short retry limit for station (dot11ShortRetryLimit). Bit 31-24 reserved, bit 23-16 EAPOL & Broadcast, bit 15-8 MGMT, bit 7-0 data. */ - cbTARGET_GSETTING_DOT11_LONG_RETRY_LIMIT, /**< 802.11 long retry limit for station (dot11LongRetryLimit). Bit 31-24 reserved, bit 23-16 EAPOL & Broadcast, bit 15-8 MGMT, bit 7-0 data. */ - cbTARGET_GSETTING_AP_DOT11_SHORT_RETRY_LIMIT, /**< 802.11 short retry limit for AP (dot11ShortRetryLimit). Bit 31-24 reserved, bit 23-16 EAPOL & Broadcast, bit 15-8 MGMT, bit 7-0 data. */ - cbTARGET_GSETTING_AP_DOT11_LONG_RETRY_LIMIT, /**< 802.11 long retry limit for AP (dot11LongRetryLimit). Bit 31-24 reserved, bit 23-16 EAPOL & Broadcast, bit 15-8 MGMT, bit 7-0 data. */ - cbTARGET_GSETTING_CHANNEL_TYPE, /**< 0-NO_HT, 1-HT20, 2-HT40MINUS, 3-HT40PLUS */ - cbTARGET_GSETTING_PMF_STA, /**< Protected Management frame Option for STA*/ - cbTARGET_GSETTING_REMAIN_ON_CHANNEL, /**< Set 0 disable, 1 enable */ - cbTARGET_GSETTING_STA_TX_RATE_MASK, /**< TX rates for station. May be overridden if not supported by AP. Set to 0 for AP default. @sa cbWLAN_RateMask_e */ - cbTARGET_GSETTING_RSSI_GOOD, /**< When to abort scanning and initiate connection */ - cbTARGET_GSETTING_RSSI_BAD, /**< When to use BAD_RSSI_SCAN_YIELD_TIMEOUT for scanning between each channel for roaming */ - cbTARGET_GSETTING_GOOD_RSSI_SCAN_YIELD_TIMEOUT, /**< Gap between each channel when doing background scan with a good connection */ - cbTARGET_GSETTING_BAD_RSSI_SCAN_YIELD_TIMEOUT, /**< Gap between each channel when doing background scan with a bad connection */ - cbTARGET_GSETTING_ROAM_BLACKLIST_LAST_BSSID_TIMEOUT, /**< How long a new connection to the last connected AP should be banned */ - cbTARGET_GSETTING_FORCE_WORLD_MODE, /**< Set 0 disable, 1 enable */ - cbTARGET_GSETTING_TX_PACKET_ACK_TIMEOUT_WD, /**< Max time for an Tx packet to not being acked by the radio before we send a soft-error event */ - cbTARGET_GSETTING_CTS_PROTECTION, /** send CTS to self before transmission. 0 disable, 1 enable. */ - cbTARGET_GSETTING_HIDDEN_SSID, /** Hidden ssid, 0 disable else enable. */ - cbTARGET_GSETTING_AP_STA_INACTIVITY_TIMEOUT, /**< Aging period for Station in seconds */ - cbTARGET_GSETTING_ROAMING_AREA_HYSTERESIS, /** Threshold between good and bad connection. */ - cbTARGET_GSETTING_FT_MODE, /** 802.11r (FT) mode, 0 - Disabled, 1 - FT over air, 2 - FT over DS */ - cbTARGET_GSETTING_4_ADDRESS_MODE, /** Bit0 - enable dynamic mode for station. Bit1 - always enable for station. */ - cbTARGET_GSETTING_MAX, -} cbWM_GSETTING; - -typedef enum targetConfigParams { - cbTARGET_CFG_FIRST, - cbTARGET_CFG_SET_POWER_SAVE_MODE = cbTARGET_CFG_FIRST, //!< Set power mode @ref cbWLAN_IoctlPowerSaveMode - cbTARGET_CFG_GET_POWER_SAVE_MODE, //!< Get power mode @ref cbWLAN_IoctlPowerSaveMode - cbTARGET_CFG_SET_LISTEN_INTERVAL, //!< Set listen interval, integer value 0 - 16 - cbTARGET_CFG_GET_LISTEN_INTERVAL, //!< Get listen interval, integer value 0 - 16 - cbTARGET_CFG_SET_DTIM_ENABLE, //!< Set DTIM enable 0, disable 1 enable - cbTARGET_CFG_GET_DTIM_ENABLE, //!< Get DTIM enable 0, disable 1 enable - cbTARGET_CFG_SET_SLEEP_TIMEOUT, //!< Set enter power save entry delay (in ms). Power save mode will be entered only if there no activity during this delay - cbTARGET_CFG_GET_SLEEP_TIMEOUT, //!< Get enter power save entry delay (in ms). Power save mode will be entered only if there no activity during this delay - cbTARGET_CFG_SET_RSSI_GOOD, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_RSSI_GOOD, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_RSSI_BAD, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_RSSI_BAD, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_GOOD_RSSI_YIELD_TMO, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_GOOD_RSSI_YIELD_TMO, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_BAD_RSSI_YIELD_TMO, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_BAD_RSSI_YIELD_TMO, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_BLACKLIST_LAST_BSSID_TIMEOUT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_BLACKLIST_LAST_BSSID_TIMEOUT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_PMF_STA, //!< Set PMF option - cbTARGET_CFG_GET_PMF_STA, //!< Get PMF option - cbTARGET_CFG_SET_FT_MODE, //!< Set fast transition option - cbTARGET_CFG_GET_FT_MODE, //!< Get fast transition option - cbTARGET_CFG_SET_MIN_SCAN_TIME, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_MIN_SCAN_TIME, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_MAX_SCAN_TIME, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_MAX_SCAN_TIME, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_SCAN_TYPE, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_SCAN_TYPE, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_QOS_ENABLE, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_QOS_ENABLE, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_RTS_THRESHOLD, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_RTS_THRESHOLD, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_TX_POWER, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_TX_POWER, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_MAX_PASSIVE_SCAN_TIME, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_MAX_PASSIVE_SCAN_TIME, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_SCAN_LISTEN_INTERVAL, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_SCAN_LISTEN_INTERVAL, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_DOT11_SHORT_RETRY_LIMIT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_DOT11_SHORT_RETRY_LIMIT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_DOT11_LONG_RETRY_LIMIT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_DOT11_LONG_RETRY_LIMIT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_AP_DOT11_SHORT_RETRY_LIMIT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_AP_DOT11_SHORT_RETRY_LIMIT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_AP_DOT11_LONG_RETRY_LIMIT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_AP_DOT11_LONG_RETRY_LIMIT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_REMAIN_ON_CHANNEL, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_REMAIN_ON_CHANNEL, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_STA_TX_RATE_MASK, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_STA_TX_RATE_MASK, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_FORCE_WORLD_MODE, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_FORCE_WORLD_MODE, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_TX_PACKET_ACK_TIMEOUT_WD, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_TX_PACKET_ACK_TIMEOUT_WD, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_CTS_PROTECTION, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_CTS_PROTECTION, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_HIDDEN_SSID, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_HIDDEN_SSID, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_AP_STA_INACTIVITY_TIMEOUT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_AP_STA_INACTIVITY_TIMEOUT, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_SET_ROAMING_AREA_HYSTERESIS, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_GET_ROAMING_AREA_HYSTERESIS, //!< SEE CORRESPONDING GSETTING - cbTARGET_CFG_LAST, - cbTARGET_CFG_SET_GSETTING = 1000, //!< Pipe to @ref cbWM_gSet. - cbTARGET_CFG_SET_TSETTING = 2000, //!< Pipe to @ref cbWM_tSet. - cbTARGET_CFG_GET_GSETTING = 3000, //!< Pipe to @ref cbWM_gGet. - cbTARGET_CFG_GET_TSETTING = 4000, //!< Pipe to @ref cbWM_tGet. -} cbTARGET_ConfigParams; - -#define cbTARGET_GSETTING_REG(X) ((cb_uint32)((X) - cbTARGET_GSETTING_START)) - -/** - * Target specific settings and tuning parameters . - * - * @ingroup types - */ -typedef enum wm_tsetting_e { - cbTARGET_TSETTING_START = 1000, - cbTARGET_TSETTING_PS_LISTEN_INTERVAL = cbTARGET_TSETTING_START, /**< Powersave: Listen interval in beacons. */ - cbTARGET_TSETTING_PS_FAST_PSP_TIMEOUT, /**< Powersave: In mode Fast PSP timeout in ms before entering PS. */ - cbTARGET_TSETTING_ANTENNA_RECEIVE_DIVERSITY, /**< Enable receive antenna diversity. 0 = off, 1 = on. */ - cbTARGET_TSETTING_QOS_WMM_NOACK, /**< Enable WMM QoS no-ack acknowledgment policy. 0 = normal ack, 1 = no-ack. */ - cbTARGET_TSETTING_PS_BEACON_EARLY_TERMINATION, /**< Powersave: In Max PSP, use beacon early termination. */ - cbTARGET_TSETTING_MAX, -} cbWM_TSETTING; - -#define cbTARGET_TSETTING_REG(X) ((cb_uint32)((X) - cbTARGET_TSETTING_START)) - -/** - * Defines the type of scanning procedure. - * Passive scan will only listen for beacons. - * Active scan will send out a probe request - * and listen for both probe responses and beacons. - * - * @ingroup types - */ -typedef enum cbWM_ScanType_e { - cbWM_SCAN_INVALID, - cbWM_SCAN_ACTIVE, - cbWM_SCAN_PASSIVE, -} cbWM_ScanType; - -/** - * Power save levels. - * @note Levels between 2 and cbWM_POWERSAVE_MAX are target specific. - * - * @ingroup types - */ -typedef enum cbWM_PowerSaveType_e { - cbWM_POWERSAVE_OFF = 0, - cbWM_POWERSAVE_FAST_PSP = 1, - cbWM_POWERSAVE_MAX_PSP = 2, - cbWM_POWERSAVE_MAX = cb_UINT8_MAX, -} cbWM_PowerSaveType; - -/** - * Power save modes set using @ref cbWLAN_ioctl - * - * @ingroup wlan - */ -typedef enum { - cbTARGET_POWER_SAVE_MODE_OFF, - cbTARGET_POWER_SAVE_MODE_SLEEP, - cbTARGET_POWER_SAVE_MODE_DEEP_SLEEP -} cbTARGET_PowerSaveMode; - -typedef enum { - cbWLAN_ONE_ANTENNA = 1, - cbWLAN_TWO_ANTENNAS -} cbWLAN_NUMBER_OF_ANTENNAS; - -typedef enum { - cbWLAN_PRIMARY_ANTENNA_ONE = 1, - cbWLAN_PRIMARY_ANTENNA_TWO -} cbWLAN_PRIMARY_ANTENNA; -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Get general tuning parameter. - * - * @param hTarget Handle to the current driver instance. - * @param setting setting to read. - * @return parameter value - */ -cb_uint32 cbTARGET_gGet(cbTARGET_Handle* hTarget, cbWM_GSETTING setting); - -/** - * Set general tuning parameter. - * - * @param hTarget Handle to the current driver instance. - * @param setting setting to modify. - * @param value value to set. - */ -void cbTARGET_gSet(cbTARGET_Handle* hTarget, cbWM_GSETTING setting, cb_uint32 value); - -/** - * Get target specific tuning parameter. - * - * @param hTarget Handle to the current driver instance. - * @param setting setting to read. - * @return parameter value - */ -cb_uint32 cbTARGET_tGet(cbTARGET_Handle* hTarget, cbWM_TSETTING setting); - -/** - * Set target specific tuning parameter. - * - * @param hTarget Handle to the current driver instance. - * @param setting setting to modify. - * @param value value to set. - */ -void cbTARGET_tSet(cbTARGET_Handle* hTarget, cbWM_TSETTING setting, cb_uint32 value); - -struct cb_wlan_configuration* cbTARGET_configuration_create(); - -cbRTSL_Status cbTARGET_configure(cbTARGET_Handle* hTarget, cbTARGET_ConfigParams parameter, void* value); - -/*-------------------------------------------------------------------------- - * Constants - *-------------------------------------------------------------------------*/ - -#define W_CONST_PREAMBLE (1) -#define W_CONST_LISTEN_INTERVAL (16) -#define W_CONST_MIN_SCAN_TIME (25) -#define W_CONST_MAX_SCAN_TIME (50) -#define W_CONST_SCAN_TYPE (cbWM_SCAN_ACTIVE) -#define W_CONST_BEACON_INTERVAL (100) -#define W_CONST_JOIN_FAILURE_TIMEOUT (600) -#define W_CONST_WLAN_BT_COEX (0) -#define W_CONST_DATA_RATE (cbWLAN_RATE_24) -#define W_CONST_LINK_ADAPTION (1) -#define W_CONST_POWER_SAVE (2) -#define W_CONST_DTIM_ENABLE (1) -#define W_CONST_QOS_ENABLE (1) -#define W_CONST_CHANNEL_TYPE (1) //HT20MHz -#define W_CONST_RTS_THRESHOLD (2347) -#define W_CONST_FRAGMENTATION_THRESHOLD (2346) -#define W_CONST_TX_POWER (15) -#define W_CONST_MAX_PASSIVE_SCAN_TIME (150) -#define W_CONST_SCAN_LISTEN_INTERVAL (150) -#define W_CONST_SLEEP_TIMEOUT (100) // Timeout in ms, 100ms timeout gives almost same throughput as without power save but still low power consumption -#define W_CONST_DEFAULT_MODULE_TYPE (cbWM_MODULE_UNKNOWN) -#define W_CONST_PMF_OPTIONAL (cbWLAN_PMF_OPTIONAL) -#define W_CONST_REMAIN_ON_CHANNEL (1) // Enabled -#define W_CONST_DEFAULT_STA_TX_RATES (0) // Use AP default -#define W_CONST_GOOD_RSSI (55) -#define W_CONST_BAD_RSSI (70) -#define W_CONST_GOOD_RSSI_SCAN_YIELD_TIMEOUT (1500) -#define W_CONST_BAD_RSSI_SCAN_YIELD_TIMEOUT (W_CONST_SCAN_LISTEN_INTERVAL) -#define W_CONST_BLACKLIST_LAST_BSSID_TIMEOUT (20) // Seconds -#define W_CONST_ROAMING_AREA_HYSTERESIS (3) -#define W_CONST_TX_PACKET_ACK_TIMEOUT (10000) -#define W_CONST_FT_MODE (2) - -#define W_CONST_DEFAULT_FORCE_WORLD_MODE (0) - -#define W_CONST_DEFAULT_AP_STA_INACTIVITY_TIMEOUT (120) - - -#define W_CONST_DEFAULT_DOT11_SHORT_RETRY_LIMIT (0x0a0a0a0aul) -#define W_CONST_DEFAULT_DOT11_LONG_RETRY_LIMIT (0x0a0a0a0aul) -#define W_CONST_DEFAULT_AP_DOT11_SHORT_RETRY_LIMIT (0x0a0a0a0aul) -#define W_CONST_DEFAULT_AP_DOT11_LONG_RETRY_LIMIT (0x0a0a0a0aul) - -//Target specific values -#define W_CONST_PS_LISTEN_INTERVAL (0) -#define W_CONST_PS_FAST_PSP_TIMEOUT (50) -#define W_CONST_ANTENNA_RECEIVE_DIVERSITY (0) -#define W_CONST_PS_BEACON_EARLY_TERMINATION (0) - -#define W_CONST_2_4GHZ_MGMT_RATE (cbWLAN_RATE_01) -#define W_CONST_5GHZ_MGMT_RATE (cbWLAN_RATE_06) - -#define W_CONST_DEFAULT_RSSI (-100) - -#ifdef __cplusplus -} -#endif - -#endif /* _CB_SYSTEM_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h deleted file mode 100644 index 9136b91f0d6..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h +++ /dev/null @@ -1,119 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : Wireless LAN driver - * File : cb_wlan_target_data.h - * - * Description : Port specific data buffer handling (ethernet frames) - *-------------------------------------------------------------------------*/ - -/** - * @file cb_wlan_target_data.h Handles the anonymous port specific packetization - * of ethernet frames. - * @ingroup target - */ - -#ifndef _CB_WLANTARGET_DATA_H_ -#define _CB_WLANTARGET_DATA_H_ - -#include "cb_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -typedef struct cbWLANTARGET_dataFrame cbWLANTARGET_dataFrame; -typedef struct cbWLANTARGET_Handle cbWLANTARGET_Handle; - - -/** - * Copy data from frame data memory to buffer. - * - * @param buffer The destination buffer. - * @param frame Frame memory pointer (@ref cbWLANTARGET_allocDataFrame). - * @param size Number of bytes to copy. - * @param offsetInFrame Offset into frame memory. - * @return @ref TRUE if successful, otherwise @ref FALSE. - */ -typedef cb_boolean(*cbWLANTARGET_copyFromDataFrame)(cb_uint8* buffer, cbWLANTARGET_dataFrame* frame, cb_uint32 size, cb_uint32 offsetInFrame); - -/** - * Copy data from buffer to frame data memory. - * - * @param frame Frame memory pointer (@ref cbWLANTARGET_allocDataFrame). - * @param buffer The destination buffer. - * @param size Number of bytes to copy. - * @param offsetInFrame Offset into frame memory. - * @return @ref TRUE if successful, otherwise @ref FALSE. - */ -typedef cb_boolean(*cbWLANTARGET_copyToDataFrame)(cbWLANTARGET_dataFrame* frame, cb_uint8* buffer, cb_uint32 size, cb_uint32 offsetInFrame); - -/** - * Allocate memory in frame data memory. - * - * @param size Number of bytes to allocate. - * @return Pointer to the frame memory. - * - * @ref cbWLANTARGET_freeDataFrame - */ -typedef cbWLANTARGET_dataFrame*(*cbWLANTARGET_allocDataFrame)(cb_uint32 size); - -/** - * Destroy memory in frame data memory. - * - * @param frame Pointer to the frame memory that should be destroyed. - * @ref cbWLANTARGET_allocDataFrame - */ -typedef void(*cbWLANTARGET_freeDataFrame)(cbWLANTARGET_dataFrame* frame); - -typedef cb_uint32(*cbWLANTARGET_getDataFrameSize)(cbWLANTARGET_dataFrame* frame); - -typedef cb_uint8(*cbWLANTARGET_getDataFrameTID)(cbWLANTARGET_dataFrame* frame); - -typedef struct -{ - cbWLANTARGET_copyFromDataFrame copyFromDataFrameIndication; - cbWLANTARGET_copyToDataFrame copyToDataFrameIndication; - cbWLANTARGET_allocDataFrame allocDataFrameIndication; - cbWLANTARGET_freeDataFrame freeDataFrameIndication; - cbWLANTARGET_getDataFrameSize getDataFrameSizeIndication; - cbWLANTARGET_getDataFrameTID getDataFrameTIDIndication; -}cbWLANTARGET_Callback; - -/*=========================================================================== - * FUNCTIONS - *=========================================================================*/ - -/** - * Register WLAN target callbacks. This should be done for packetization between - * the WLAN driver and an IP stack. - * - * @param callbacks Callbacks - */ -void cbWLANTARGET_registerCallbacks(cbWLANTARGET_Callback* callbacks); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h deleted file mode 100644 index c029a90b876..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h +++ /dev/null @@ -1,699 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : WLAN driver - * File : cb_wlan_types.h - * - * Description : Common wireless LAN defines and types. - *-------------------------------------------------------------------------*/ - -/** - * @file cb_wlan_types.h The main WLAN 802.11 interface - * - * @ingroup WLANDriver - */ - -#ifndef _CB_WLAN_TYPES_H_ -#define _CB_WLAN_TYPES_H_ - -#include "cb_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*=========================================================================== - * DEFINES - *=========================================================================*/ - -/** - * Max length for an SSID - * - * @ingroup wlantypes - */ -#define cbWLAN_SSID_MAX_LENGTH (32) - -/** - * EAPOL ethernet type - * - * @ingroup wlantypes - */ -#define cbWLAN_ETHTYPE_EAPOL (0x888E) - -/** - * Maximum size of a predefined WEP key - * - * @ingroup wlantypes - */ -#define cbWLAN_KEY_SIZE_WEP_MAX (cbWLAN_KEY_SIZE_WEP128) - -#define cbWLAN_OUI_SIZE 3 - -#define cbRATE_MASK_B (cbRATE_MASK_01 | cbRATE_MASK_02 | cbRATE_MASK_5_5 | cbRATE_MASK_11) -#define cbRATE_MASK_G (cbRATE_MASK_06 | cbRATE_MASK_09 | cbRATE_MASK_12 | cbRATE_MASK_18 | cbRATE_MASK_24 | cbRATE_MASK_36 | cbRATE_MASK_48 | cbRATE_MASK_54) -#define cbRATE_MASK_A (cbRATE_MASK_G) -#define cbRATE_MASK_N (cbRATE_MASK_MCS0 | cbRATE_MASK_MCS1 | cbRATE_MASK_MCS2 | cbRATE_MASK_MCS3 | cbRATE_MASK_MCS4 | cbRATE_MASK_MCS5 | cbRATE_MASK_MCS6 | cbRATE_MASK_MCS7) -#define cbRATE_TX_MIMO (cbRATE_MASK_MCS8 | cbRATE_MASK_MCS9 | cbRATE_MASK_MCS10 | cbRATE_MASK_MCS11 | cbRATE_MASK_MCS12 | cbRATE_MASK_MCS13 | cbRATE_MASK_MCS14 | cbRATE_MASK_MCS15) -#define cbRATE_TX_WIDE (cbRATE_MASK_WIDE) -#define cbRATE_MASK_ALL (cbRATE_MASK_B | cbRATE_MASK_G | cbRATE_MASK_N | cbRATE_TX_MIMO | cbRATE_TX_WIDE) - -#define cbWLAN_MAX_CHANNEL_LIST_LENGTH 38 - -#define cbWLAN_TX_POWER_AUTO 0xFF - -#define cbWLAN_PMF_MFPR cb_BIT_6 // Bit 6: Management Frame Protection Required (MFPR) -#define cbWLAN_PMF_MFPC cb_BIT_7 // Bit 7: Management Frame Protection Capable (MFPC). - -/*=========================================================================== - * TYPES - *=========================================================================*/ - -/** - * The encryption mode. - * - * @ingroup wlantypes - */ -typedef enum cbWLAN_EncryptionMode_e { - cbWLAN_ENC_NONE, - cbWLAN_ENC_WEP64, - cbWLAN_ENC_WEP128, - cbWLAN_ENC_TKIP, - cbWLAN_ENC_AES, - cbWLAN_ENC_BIP, -} cbWLAN_EncryptionMode; - -typedef enum cbWLAN_CipherSuite { - cbWLAN_CIPHER_SUITE_NONE = 0x00, - cbWLAN_CIPHER_SUITE_WEP64 = 0x01, - cbWLAN_CIPHER_SUITE_WEP128 = 0x02, - cbWLAN_CIPHER_SUITE_TKIP = 0x04, - cbWLAN_CIPHER_SUITE_AES_CCMP = 0x08, - cbWLAN_CIPHER_SUITE_BIP = 0x10, -} cbWLAN_CipherSuite; - -typedef enum cbWLAN_AuthenticationSuite { - cbWLAN_AUTHENTICATION_SUITE_NONE = 0x0000, - cbWLAN_AUTHENTICATION_SUITE_SHARED_SECRET = 0x0001, - cbWLAN_AUTHENTICATION_SUITE_PSK = 0x0002, - cbWLAN_AUTHENTICATION_SUITE_8021X = 0x0004, - cbWLAN_AUTHENTICATION_SUITE_USE_WPA = 0x0008, - cbWLAN_AUTHENTICATION_SUITE_USE_WPA2 = 0x0010, - cbWLAN_AUTHENTICATION_SUITE_PSK_SHA256 = 0x0020, - cbWLAN_AUTHENTICATION_SUITE_8021X_SHA256 = 0x0040, - cbWLAN_AUTHENTICATION_SUITE_8021X_FT = 0x0080, - cbWLAN_AUTHENTICATION_SUITE_PSK_FT = 0x0100, -} cbWLAN_AuthenticationSuite; - - -/** - * Enterprise authentication mode. - * - * @ingroup wlan - */ -typedef enum cbWLAN_EnterpriseMode { - cbWLAN_ENTERPRISE_MODE_LEAP, - cbWLAN_ENTERPRISE_MODE_PEAP, - cbWLAN_ENTERPRISE_MODE_EAPTLS, -} cbWLAN_EnterpriseMode; - -/** - * Key sizes for the supported encryptions. - * - * @ingroup wlantypes - */ -typedef enum cbWLAN_EncryptionKeySize_e { - cbWLAN_KEY_SIZE_WEP64 = 5, - cbWLAN_KEY_SIZE_WEP128 = 13, - cbWLAN_KEY_SIZE_WEP2 = 16, - cbWLAN_KEY_SIZE_TKIP = 16, - cbWLAN_KEY_SIZE_AES = 16, - cbWLAN_KEY_SIZE_TKIP_MIC = 8 -} cbWLAN_EncryptionKeySize; - -enum cbWLAN_Channel_e { - cbWLAN_CHANNEL_ALL = 0, - cbWLAN_CHANNEL_01 = 1, - cbWLAN_CHANNEL_02, - cbWLAN_CHANNEL_03, - cbWLAN_CHANNEL_04, - cbWLAN_CHANNEL_05, - cbWLAN_CHANNEL_06, - cbWLAN_CHANNEL_07, - cbWLAN_CHANNEL_08, - cbWLAN_CHANNEL_09, - cbWLAN_CHANNEL_10, - cbWLAN_CHANNEL_11, - cbWLAN_CHANNEL_12, - cbWLAN_CHANNEL_13, - cbWLAN_CHANNEL_14, - - cbWLAN_CHANNEL_36 = 36, - cbWLAN_CHANNEL_40 = 40, - cbWLAN_CHANNEL_44 = 44, - cbWLAN_CHANNEL_48 = 48, - cbWLAN_CHANNEL_52 = 52, - cbWLAN_CHANNEL_56 = 56, - cbWLAN_CHANNEL_60 = 60, - cbWLAN_CHANNEL_64 = 64, - cbWLAN_CHANNEL_100 = 100, - cbWLAN_CHANNEL_104 = 104, - cbWLAN_CHANNEL_108 = 108, - cbWLAN_CHANNEL_112 = 112, - cbWLAN_CHANNEL_116 = 116, - cbWLAN_CHANNEL_120 = 120, - cbWLAN_CHANNEL_124 = 124, - cbWLAN_CHANNEL_128 = 128, - cbWLAN_CHANNEL_132 = 132, - cbWLAN_CHANNEL_136 = 136, - cbWLAN_CHANNEL_140 = 140, - cbWLAN_CHANNEL_149 = 149, - cbWLAN_CHANNEL_153 = 153, - cbWLAN_CHANNEL_157 = 157, - cbWLAN_CHANNEL_161 = 161, - cbWLAN_CHANNEL_165 = 165 -}; - -/** - * WLAN Channels - * Valid values are found in @ref cbWLAN_Channel_e - * @ingroup wlantypes - */ -typedef cb_uint8 cbWLAN_Channel; - -/** - * WLAN Channel list - * @ingroup wlantypes - */ -typedef struct { - cb_uint32 length; - cbWLAN_Channel channels[cbWLAN_MAX_CHANNEL_LIST_LENGTH]; -} cbWLAN_ChannelList; - -/** - * Standard 802.11 rates - * - * @ingroup wlantypes - */ -enum cbWLAN_Rate_e { - cbWLAN_RATE_01 = 1, // 1 - cbWLAN_RATE_02, // 2 - cbWLAN_RATE_5_5, // 3 - cbWLAN_RATE_06, // 4 - cbWLAN_RATE_09, // 5 - cbWLAN_RATE_11, // 6 - cbWLAN_RATE_12, // 7 - cbWLAN_RATE_18, // 8 - cbWLAN_RATE_24, // 9 - cbWLAN_RATE_36, // 10 - cbWLAN_RATE_48, // 11 - cbWLAN_RATE_54, // 12 - cbWLAN_RATE_MCS0, // 13 - cbWLAN_RATE_MCS1, // 14 - cbWLAN_RATE_MCS2, // 15 - cbWLAN_RATE_MCS3, // 16 - cbWLAN_RATE_MCS4, // 17 - cbWLAN_RATE_MCS5, // 18 - cbWLAN_RATE_MCS6, // 19 - cbWLAN_RATE_MCS7, // 20 - cbWLAN_RATE_MCS8, // 21 - cbWLAN_RATE_MCS9, // 22 - cbWLAN_RATE_MCS10, // 23 - cbWLAN_RATE_MCS11, // 24 - cbWLAN_RATE_MCS12, // 25 - cbWLAN_RATE_MCS13, // 26 - cbWLAN_RATE_MCS14, // 27 - cbWLAN_RATE_MCS15, // 28 - cbWLAN_RATE_MAX, // 29 - cbWLAN_RATE_UNSUPPORTED = 0xff -}; - -/** - * Type for containing values found in @ref cbWLAN_Rate_e - * @ingroup wlantypes - */ -typedef cb_uint8 cbWLAN_Rate; - - -/** - * Mask bits for standard 802.11 rates - * - * @ingroup wlantypes - */ -enum cbWLAN_RateMask_e { - cbRATE_MASK_01 = 0x00000001, - cbRATE_MASK_02 = 0x00000002, - cbRATE_MASK_5_5 = 0x00000004, - cbRATE_MASK_11 = 0x00000008, - cbRATE_MASK_06 = 0x00000010, - cbRATE_MASK_09 = 0x00000020, - cbRATE_MASK_12 = 0x00000040, - cbRATE_MASK_18 = 0x00000080, - cbRATE_MASK_24 = 0x00000100, - cbRATE_MASK_36 = 0x00000200, - cbRATE_MASK_48 = 0x00000400, - cbRATE_MASK_54 = 0x00000800, - // NOTE: Don't move MCS rates bit offset, see note on define below - cbRATE_MASK_MCS0 = 0x00001000, - cbRATE_MASK_MCS1 = 0x00002000, - cbRATE_MASK_MCS2 = 0x00004000, - cbRATE_MASK_MCS3 = 0x00008000, - cbRATE_MASK_MCS4 = 0x00010000, - cbRATE_MASK_MCS5 = 0x00020000, - cbRATE_MASK_MCS6 = 0x00040000, - cbRATE_MASK_MCS7 = 0x00080000, - //TX MIMO RATES - cbRATE_MASK_MCS8 = 0x00100000, - cbRATE_MASK_MCS9 = 0x00200000, - cbRATE_MASK_MCS10 = 0x00400000, - cbRATE_MASK_MCS11 = 0x00800000, - cbRATE_MASK_MCS12 = 0x01000000, - cbRATE_MASK_MCS13 = 0x02000000, - cbRATE_MASK_MCS14 = 0x04000000, - cbRATE_MASK_MCS15 = 0x08000000, - //TX RATE USE WIDE CHANNEL - cbRATE_MASK_WIDE = 0x80000000 -}; - - -/** - * Access categories - * - * @ingroup wlantypes - */ -typedef enum cbWLAN_AccessCategory_e { - cbWLAN_AC_BK = 1, /**< Background */ - cbWLAN_AC_SP = 2, /**< Background (Spare) */ - - cbWLAN_AC_BE = 0, /**< Best effort */ - cbWLAN_AC_EE = 3, /**< Best effort (Excellent Effort) */ - - cbWLAN_AC_CL = 4, /**< Video (Controlled Load) */ - cbWLAN_AC_VI = 5, /**< Video */ - - cbWLAN_AC_VO = 6, /**< Voice */ - cbWLAN_AC_NC = 7, /**< Voice (Network Control)*/ -} cbWLAN_AccessCategory; - -/** -* Fast Transition (802.11r) modes. -* -* @ingroup wlantypes -*/ -typedef enum cbWLAN_FTMode_e { - cbWLAN_FT_OFF, - cbWLAN_FT_OVER_AIR, - cbWLAN_FT_OVER_DS, -} cbWLAN_FTMode; -/** -* connectBlue Hardware Identification -* -* @ingroup types -*/ -typedef enum cbWM_ModuleType_e { - cbWM_MODULE_UNKNOWN, - cbWM_MODULE_OWL22X, - cbWM_MODULE_OWL253, - cbWM_MODULE_OWS451, - cbWM_MODULE_OWL351, - cbWM_MODULE_ODIN_W16X = cbWM_MODULE_OWL351, - cbWM_MODULE_ODIN_W26X, -} cbWM_ModuleType; - -/** - * Mac address type - * - * @ingroup wlantypes - */ -typedef cb_uint8 cbWLAN_MACAddress[6]; - -/** - * Type for containing values found in @ref cbWLAN_RateMask_e - * @ingroup wlantypes - */ -typedef cb_uint32 cbWLAN_RateMask; - -/** - * Transmission power - * - * @ingroup wlantypes - */ -typedef cb_uint8 cbWLAN_TxPower; - -/** - * The different frequency bands to choose from. - * - * @ingroup wlantypes - */ -typedef enum cbWLAN_Band_e { - cbWLAN_BAND_UNDEFINED, - cbWLAN_BAND_2_4GHz, - cbWLAN_BAND_5GHz, -} cbWLAN_Band; - -/** - * The operational mode. - * - * @ingroup wlantypes - */ -typedef enum cbWLAN_OperationalMode_e { - cbWLAN_OPMODE_MANAGED, - cbWLAN_OPMODE_ADHOC, -} cbWLAN_OperationalMode; - -/** - * Encryption key type - * - * @ingroup wlantypes - */ -typedef enum cbWLAN_KeyType_e { - cbWLAN_KEY_UNICAST, - cbWLAN_KEY_BROADCAST, - cbWLAN_KEY_IGTK, -} cbWLAN_KeyType; - -typedef enum { - cbWLAN_CONNECT_MODE_OPEN, - cbWLAN_CONNECT_MODE_WEP_OPEN, - cbWLAN_CONNECT_MODE_WPA_PSK, - cbWLAN_CONNECT_MODE_ENTERPRISE, -} cbWLAN_ConnectMode; - -typedef enum { - cbWLAN_AP_MODE_OPEN, - cbWLAN_AP_MODE_WEP_OPEN, - cbWLAN_AP_MODE_WPA_PSK, - cbWLAN_AP_MODE_ENTERPRISE, -} cbWLAN_ApMode; - -#if defined(CB_FEATURE_802DOT11R) -/** - * Description of the Mobility Domain Information Element - * - * @ingroup wlantypes - */ - -cb_PACKED_STRUCT_BEGIN(cbWLAN_MDInformation) { - cb_uint8 eId; - cb_uint8 len; - cb_uint16 MDID; - cb_uint8 FtCapabilityPolicy; -} cb_PACKED_STRUCT_END(cbWLAN_MDInformation); - -/** - * Description of the Timeout Interval Information Element - * - * @ingroup wlantypes - */ - -cb_PACKED_STRUCT_BEGIN(cbWLAN_TimeOutInformation){ - cb_uint8 eId; - cb_uint8 len; - cb_uint8 timeOutType; - cb_uint32 value; -} cb_PACKED_STRUCT_END(cbWLAN_TimeOutInformation); - -/** - * Description of the Mobility Domain Information Element - * - * @ingroup wlantypes - */ - -cb_PACKED_STRUCT_BEGIN(cbWLAN_FtInformation){ - cb_uint8 eId; - cb_uint8 len; - cb_uint16 micControl; - cb_uint8 mic[16]; - cb_uint8 ANonce[32]; - cb_uint8 SNonce[32]; - cb_uint8 optionalParams[174]; // length field can maximum be 256, therefore optional params can be max 172 bytes -} cb_PACKED_STRUCT_END(cbWLAN_FtInformation); - - - -typedef struct cbWLAN_BSSChangeParameters { - cbWLAN_MACAddress currentBssid; /**< BSSID of connected AP. > */ - cbWLAN_MACAddress targetBssid; /**< BSSID to connect to. > */ - cbWLAN_Channel channel; /**< The channel the BSS is located on. > */ - cb_uint32 reAssocDeadline; /**< Reassociation Deadline time*/ -} cbWLAN_BSSChangeParameters; -#endif - -//#if defined(CB_FEATURE_802DOT11W) -typedef enum { - cbWLAN_PMF_DISABLE = 0, /**< MFPC = 0, MFPR = 0 */ - cbWLAN_PMF_OPTIONAL = 1, /**< MFPC = 1, MFPR = 0 */ - cbWLAN_PMF_REQUIRED = 2, /**< MFPC = 1, MFPR = 1 */ -} cbWLAN_PMF; -//#endif -typedef enum cbAP_KdeType_e { - RESERVED, - GTK_KDE, - RESERVED_2, - MAC_ADDRESS_KDE, - PMKID_KDE, - SMK_KDE, - NONCE_KDE, - LIFETIME_KDE, - ERROR_KDE, - IGTK_KDE, - KEY_ID_KDE, -} cbAP_KdeType; - - -/** - * Ethernet header - * - * @ingroup wlantypes - */ -cb_PACKED_STRUCT_BEGIN(cbWLAN_EthernetHeader) { - cbWLAN_MACAddress dest; - cbWLAN_MACAddress src; - cb_uint16 type; -} cb_PACKED_STRUCT_END(cbWLAN_EthernetHeader); - - -cb_PACKED_STRUCT_BEGIN(cbWLAN_EthernetFrame) { - cbWLAN_EthernetHeader header; - cb_uint8 payload[cb_EMPTY_ARRAY]; -} cb_PACKED_STRUCT_END(cbWLAN_EthernetFrame); - -/** - * SNAP header - * - * @ingroup wlantypes - */ -cb_PACKED_STRUCT_BEGIN(cbWLAN_SNAPHeader) { - cb_uint8 dsap; - cb_uint8 ssap; - cb_uint8 ctrl; - cb_uint8 encapsulation[3]; - cb_uint16 ethType; -} cb_PACKED_STRUCT_END(cbWLAN_SNAPHeader); - -cb_PACKED_STRUCT_BEGIN(cbWLAN_SNAPFrame) { - cbWLAN_SNAPHeader header; - cb_uint8 payload[cb_EMPTY_ARRAY]; -} cb_PACKED_STRUCT_END(cbWLAN_SNAPFrame); - - -/** - * Defines an ssid. - * - * @ingroup wlantypes - */ -typedef struct cbWLAN_Ssid_s { - cb_uint8 ssid[cbWLAN_SSID_MAX_LENGTH]; - cb_uint32 ssidLength; -} cbWLAN_Ssid; - -/** - * Defines one wep key. - * - * @ingroup wlantypes - */ -typedef struct cbWLAN_WepKey_s { - cb_uint8 key[cbWLAN_KEY_SIZE_WEP_MAX]; - cb_uint32 length; -} cbWLAN_WEPKey; - -/** - * Describes host revisions. - * @see cbWM_Version - * - * @ingroup types - */ -typedef struct { - struct { - cb_uint32 major; - cb_uint32 minor; - cb_uint32 patch1; - } software; - struct { - const char* id; - } manufacturer; -} cbWM_DriverRevision; - -/** - * Describes firmware revisions. - * @see cbWM_Version - * - * @ingroup types - */ -typedef struct { - struct { - cb_uint32 major; - cb_uint32 minor; - cb_uint32 patch1; - cb_uint32 patch2; - } firmware; - struct { - const char* id; - } manufacturer; -} cbWM_FWRevision; - -/** - * Describes firmware revisions. Is divided into three parts; one for the - * host driver side, one for target firmware, and one information string - * descibing the HW manufacturer. - * - * @ingroup types - */ -typedef struct version_st{ - cbWM_DriverRevision host; - cbWM_FWRevision target; -} cbWM_Version; - -/** - * Describes power levels for dynamic power level control. - * - * @ingroup types - */ -typedef struct cbWM_TxPowerSettings_s { - cbWLAN_TxPower lowTxPowerLevel; - cbWLAN_TxPower medTxPowerLevel; - cbWLAN_TxPower maxTxPowerLevel; -} cbWM_TxPowerSettings; - -/** - * Describes the startup settings needed to boot properly. - * - * @ingroup types - */ -typedef struct cbWM_BootParameters_s { - cbWM_TxPowerSettings txPowerSettings; - cb_uint8 primaryAntenna; - cb_uint8 numberOfAntennas; -} cbWM_BootParameters; - -/** - * Describes an access point. - * - * @ingroup types - */ -typedef struct cbWLAN_ApInformation { - cbWLAN_Ssid ssid; /**< SSID */ - cbWLAN_MACAddress bssid; /**< BSSID */ - cbWLAN_Channel channel; /**< Channel */ -} cbWLAN_ApInformation; - -/** - * Describes a station connected to an access point. - * - * @ingroup types - */ -typedef struct cbWLAN_ApStaInformation { - cbWLAN_MACAddress MAC; -} cbWLAN_ApStaInformation; - -typedef struct cbWLAN_HTCapabilities_st { - cbWLAN_RateMask rates; - cb_uint16 info; -} cbWLAN_HTCapabilities; -/*--------------------------------------------------------------------------- - * VARIABLE DECLARATIONS - *-------------------------------------------------------------------------*/ -extern const cbWLAN_MACAddress nullMac; -extern const cbWLAN_MACAddress broadcastMac; - -extern const cb_uint8 OUI_Microsoft[cbWLAN_OUI_SIZE]; -extern const cb_uint8 OUI_Epigram[cbWLAN_OUI_SIZE]; -extern const cb_uint8 OUI_ConnectBlue[cbWLAN_OUI_SIZE]; -extern const cb_uint8 OUI_IEEE8021[cbWLAN_OUI_SIZE]; - -extern const cb_uint8 PATTERN_TKIP[2]; -extern const cb_uint8 PATTERN_WME_IE[3]; -extern const cb_uint8 PATTERN_WME_PE[3]; - -/*--------------------------------------------------------------------------- - * FUNCTIONS - *-------------------------------------------------------------------------*/ - -/** - * Misc - */ - -/** - * Returns the correct frequency @ref cbWLAN_Band band based on the input channel. - * - * For @ref cbWLAN_CHANNEL_ALL This function will return @ref cbWLAN_BAND_2_4GHz. - * - * @param channel The channel to be queried for band. - * @return The @ref cbWLAN_Band band for the requested channel. - */ -cbWLAN_Band cbWLAN_getBandFromChannel(cbWLAN_Channel channel); - -/** - * Returns the valid rates @ref cbWLAN_RateMask based for the channel. - * - * @param channel The channel to be queried for rates. - * @return The valid rates @ref cbWLAN_RateMask for the requested channel. - */ -cbWLAN_RateMask cbWLAN_getRatesForChannel(cbWLAN_Channel channel, cb_uint8 numberOfAntennas); - -/** - * Checks is the input rate is a 802.11n rate or not. - * - * @param rate The rate to check - * @return @ref TRUE if the input rate is an n-rate. @ref FALSE otherwise. - */ -cb_boolean cbWLAN_isNRate(cbWLAN_Rate rate); - -/** - * Checks if a channel is valid - * - * @return @ref TRUE if the channel is valid. @ref FALSE otherwise. - */ -cb_boolean cbWLAN_isValidChannel(cbWLAN_Channel channel); - -/** - * Checks if a channel is valid for HT40- - * - * @return @ref TRUE if the channel is valid. @ref FALSE otherwise. - */ -cb_boolean cbWLAN_isValidHT40MinusChannel(cbWLAN_Channel channel); - -/** - * Checks if a channel is valid for HT40+ - * - * @return @ref TRUE if the channel is valid. @ref FALSE otherwise. - */ -cb_boolean cbWLAN_isValidHT40PlusChannel(cbWLAN_Channel channel); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/default_wifi_interface.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/default_wifi_interface.cpp deleted file mode 100644 index e2d6f02c6bd..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/default_wifi_interface.cpp +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifdef MBED_CONF_LWIP_PRESENT - -#include "OdinWiFiInterface.h" - -WiFiInterface *WiFiInterface::get_target_default_instance() -{ - static OdinWiFiInterface wifi; - return &wifi; -} - -#endif // MBED_CONF_LWIP_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/enterprise_handle.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/enterprise_handle.h deleted file mode 100644 index e4c3c627780..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/enterprise_handle.h +++ /dev/null @@ -1,69 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmö, All Rights Reserved - * SPDX-License-Identifier: LicenseRef-PBL - * - * This file and the related binary are licensed under the - * Permissive Binary License, Version 1.0 (the "License"); - * you may not use these files except in compliance with the License. - * - * You may obtain a copy of the License here: - * LICENSE-permissive-binary-license-1.0.txt and at - * https://www.mbed.com/licenses/PBL-1.0 - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Component : WIFI - * File : enterprize_handle.h - * - * Description : - *-------------------------------------------------------------------------*/ -#include -#include "cb_comdefs.h" -#include -#include -#include "cb_cert_utils.h" -#include "cb_wlan.h" -#include "cb_hw.h" - -/*=========================================================================== - * DEFINES - *=========================================================================*/ -#define cbSECMNG_MAX_CERTIFICATE_SIZE 4096 -#define cbSECMNG_MAX_DER_FILE_SIZE (4096 + 3) // we need to make room for the 3 size bytes -#define cbSECMNG_MD5_LEN 16 -#define cbSECMNG_MD5_STRING_LEN ((cbSECMNG_MD5_LEN * 2) + 1) -#define cbSECMNG_MAX_CERTIFICATE_NAME_LEN 32 -#define cbSECMNG_MAX_CERTIFICATE_PASSWORD_LEN 64 - -/*=========================================================================== - * TYPES - *=========================================================================*/ -typedef enum { - cbSECMNG_TYPE_ALL = -1, - cbSECMNG_TRUSTED_ROOT, - cbSECMNG_CLIENT_CERT, - cbSECMNG_CLIENT_PRIVATE_KEY, -} cbSECMNG_Type; - -/*=========================================================================== - * DECLARATIONS - *=========================================================================*/ -#ifdef __cplusplus -extern "C" { -#endif - -/** Call eap connection handler - * - * @param cert Reference to certificate e.g client or CA server certificate - * @param pvt_key Reference to private key in case if private key is inside cert reference it can be passed as NULL. - In case of EAP_TLS we need private key along with client certificate and not require in case of PEAP so NULL can be passed. - * @param commonParams Connection parameters. - * @param enterpriseParams Enterprise parameters. - * @return 0 on success, or error code on failure - */ -cbWLAN_Handle cb_eap_conn_handler(cb_char const* cert, cb_char const* pvt_key, cbWLAN_CommonConnectParameters *commonParams, cbWLAN_EnterpriseConnectParameters *enterpriseParams); - -#ifdef __cplusplus -} -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/odin_drv_conf.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/odin_drv_conf.h deleted file mode 100644 index 358953aa00a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/odin_drv_conf.h +++ /dev/null @@ -1,118 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2019, u-blox Malm�, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ODIN_DRV_CONFIG_H -#define ODIN_DRV_CONFIG_H - -/** Enum of WiFi Configuration types - * - * The configuration type specifies a particular parameter of - * a WiFi interface. And will be used particular configuration to - * use when initializing a WiFi network e.g. 802.11r, 802.11w - * SEE CORRESPONDING GSETTING - * - */ -typedef enum target_config_params_e { - ODIN_CFG_FIRST, - ODIN_CFG_SET_POWER_SAVE_MODE = ODIN_CFG_FIRST, - ODIN_CFG_GET_POWER_SAVE_MODE, - ODIN_CFG_SET_MIN_SCAN_TIME, - ODIN_CFG_GET_MIN_SCAN_TIME, - ODIN_CFG_SET_MAX_SCAN_TIME, - ODIN_CFG_GET_MAX_SCAN_TIME, - ODIN_CFG_SET_SCAN_TYPE, - ODIN_CFG_GET_SCAN_TYPE, - ODIN_CFG_SET_LISTEN_INTERVAL, - ODIN_CFG_GET_LISTEN_INTERVAL, - ODIN_CFG_SET_DTIM_ENABLE, - ODIN_CFG_GET_DTIM_ENABLE, - ODIN_CFG_SET_QOS_ENABLE, - ODIN_CFG_GET_QOS_ENABLE, - ODIN_CFG_SET_RTS_THRESHOLD, - ODIN_CFG_GET_RTS_THRESHOLD, - ODIN_CFG_SET_TX_POWER, - ODIN_CFG_GET_TX_POWER, - ODIN_CFG_SET_MAX_PASSIVE_SCAN_TIME, - ODIN_CFG_GET_MAX_PASSIVE_SCAN_TIME, - ODIN_CFG_SET_SCAN_LISTEN_INTERVAL, - ODIN_CFG_GET_SCAN_LISTEN_INTERVAL, - ODIN_CFG_SET_DOT11_SHORT_RETRY_LIMIT, - ODIN_CFG_GET_DOT11_SHORT_RETRY_LIMIT, - ODIN_CFG_SET_DOT11_LONG_RETRY_LIMIT, - ODIN_CFG_GET_DOT11_LONG_RETRY_LIMIT, - ODIN_CFG_SET_AP_DOT11_SHORT_RETRY_LIMIT, - ODIN_CFG_GET_AP_DOT11_SHORT_RETRY_LIMIT, - ODIN_CFG_SET_AP_DOT11_LONG_RETRY_LIMIT, - ODIN_CFG_GET_AP_DOT11_LONG_RETRY_LIMIT, - ODIN_CFG_SET_REMAIN_ON_CHANNEL, - ODIN_CFG_GET_REMAIN_ON_CHANNEL, - ODIN_CFG_SET_STA_TX_RATE_MASK, - ODIN_CFG_GET_STA_TX_RATE_MASK, - ODIN_CFG_SET_RSSI_GOOD, - ODIN_CFG_GET_RSSI_GOOD, - ODIN_CFG_SET_RSSI_BAD, - ODIN_CFG_GET_RSSI_BAD, - ODIN_CFG_SET_SLEEP_TIMEOUT, - ODIN_CFG_GET_SLEEP_TIMEOUT, - ODIN_CFG_SET_GOOD_RSSI_YIELD_TMO, - ODIN_CFG_GET_GOOD_RSSI_YIELD_TMO, - ODIN_CFG_SET_BAD_RSSI_YIELD_TMO, - ODIN_CFG_GET_BAD_RSSI_YIELD_TMO, - ODIN_CFG_SET_FORCE_WORLD_MODE, - ODIN_CFG_GET_FORCE_WORLD_MODE, - ODIN_CFG_SET_TX_PACKET_ACK_TIMEOUT_WD, - ODIN_CFG_GET_TX_PACKET_ACK_TIMEOUT_WD, - ODIN_CFG_SET_CTS_PROTECTION, - ODIN_CFG_GET_CTS_PROTECTION, - ODIN_CFG_SET_HIDDEN_SSID, - ODIN_CFG_GET_HIDDEN_SSID, - ODIN_CFG_SET_AP_STA_INACTIVITY_TIMEOUT, - ODIN_CFG_GET_AP_STA_INACTIVITY_TIMEOUT, - ODIN_CFG_SET_ROAMING_AREA_HYSTERESIS, - ODIN_CFG_GET_ROAMING_AREA_HYSTERESIS, - ODIN_CFG_SET_RSSI_MIN, - ODIN_CFG_GET_RSSI_MIN, - ODIN_CFG_SET_ROAM_BAD_CHANNEL_RSSI_HYSTERESIS, - ODIN_CFG_GET_ROAM_BAD_CHANNEL_RSSI_HYSTERESIS, - ODIN_CFG_SET_ROAM_NO_ROAM_TMO, - ODIN_CFG_GET_ROAM_NO_ROAM_TMO, - ODIN_CFG_SET_ROAM_WAIT_TIMEOUT, - ODIN_CFG_GET_ROAM_WAIT_TIMEOUT, - ODIN_CFG_SET_SHORT_GI, - ODIN_CFG_GET_SHORT_GI, - ODIN_CFG_SET_WIRELESS_ISOLATION, - ODIN_CFG_GET_WIRELESS_ISOLATION, - ODIN_CFG_SET_PMF_STA, - ODIN_CFG_GET_PMF_STA, - ODIN_CFG_SET_FT_MODE, - ODIN_CFG_GET_FT_MODE, - ODIN_CFG_LAST, -} target_config_params_e; - -/** -* Power save modes set using @ref cbWLAN_ioctl -* -* @ingroup wlan -*/ -typedef enum { - ODIN_POWER_SAVE_MODE_OFF, - ODIN_POWER_SAVE_MODE_SLEEP, - ODIN_POWER_SAVE_MODE_DEEP_SLEEP -} target_power_save_mode_e; - -#endif - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c deleted file mode 100644 index dd18f312665..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c +++ /dev/null @@ -1,124 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *-------------------------------------------------------------------------------------- - * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL - * | (external 8 MHz clock) | (external 8 MHz clock) - *-------------------------------------------------------------------------------------- - * SYSCLK(MHz) | 168 | 180 - *-------------------------------------------------------------------------------------- - * AHBCLK (MHz) | 168 | 180 - *-------------------------------------------------------------------------------------- - * APB1CLK (MHz) | 42 | 45 - *-------------------------------------------------------------------------------------- - * APB2CLK (MHz) | 84 | 90 - *-------------------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO - *-------------------------------------------------------------------------------------- -**/ - -#include "stm32f4xx.h" - - -/* Select the SYSCLOCK to start with (0=OFF, 1=ON) */ -#define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */ -#define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */ - - -void SetSysClock(void); - - -/** System Clock Configuration -*/ -#if USE_SYSCLOCK_168 != 0 -/* - * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery - * and SYSCLK=168MHZ - */ -void SetSysClock(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - __HAL_RCC_PWR_CLK_ENABLE(); - - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 24; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 - | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); - - // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3); - - -} - -#elif USE_SYSCLOCK_180 != 0 -/* - * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery - * and SYSCLK=180MHZ - */ -void SetSysClock(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - __HAL_RCC_PWR_CLK_ENABLE(); - - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 8; - RCC_OscInitStruct.PLL.PLLN = 360; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - HAL_PWREx_EnableOverDrive(); - - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 - | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); - - // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3); - -} -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h deleted file mode 100644 index 27aee777891..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h +++ /dev/null @@ -1,95 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE, - LPUART_1 = (int)LPUART1_BASE -} UARTName; - -#define STDIO_UART_TX PC_12 -#define STDIO_UART_RX PD_2 -#define STDIO_UART UART_5 - -#define DEVICE_SPI_COUNT 3 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_15 = (int)TIM15_BASE, - PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c deleted file mode 100644 index aa859f63796..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c +++ /dev/null @@ -1,269 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // IN5 - ARDUINO A0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // IN6 - ARDUINO A1 -// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // IN7 // PA_2 is used as SERIAL_TX -// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // IN8 // PA_3 is used as SERIAL_RX - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // IN9 - ARDUINO A2 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15 - ARDUINO A3 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // IN1 - ARDUINO A5 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // IN2 - ARDUINO A4 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // IN3 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // IN4 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin) - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// Warning: TIM5 cannot be used because already used by the us_ticker. -const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 (used by us_ticker) - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 (used by us_ticker) -// {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // PA_2 is used as SERIAL_TX -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 (used by us_ticker) -// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1 -// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // PA_3 is used as SERIAL_RX -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 (used by us_ticker) -// {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 -// {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1 - {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 -// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N -// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N -// {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 -// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 -// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO D3 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D5 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO D10 -// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N - {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 -// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 -// {PB_9, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO D6 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N -// {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1 -// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2 -// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 -// {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - ARDUINO D9 -// {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 -// {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 -// {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, -// {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, -// {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, -// {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, -// {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs -// {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, -// {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, -// {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 - {NC, NC, 0} -}; - -const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, -// {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, -// {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, -// {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, -// {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, -// {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PG_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12 - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PG_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13 - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PG_9, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PG_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_CAN_RD[] = { - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_CAN_TD[] = { - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h deleted file mode 100644 index 7a919852018..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h +++ /dev/null @@ -1,168 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_2 = 0x32, - - PG_9 = 0x69, - PG_10 = 0x6A, - PG_11 = 0x6B, - PG_12 = 0x6C, - - PH_0 = 0x70, - PH_1 = 0x71, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // Arduino connector namings - A0 = PA_0, - A1 = PA_1, - A2 = PA_4, - A3 = PB_0, - A4 = PC_1, - A5 = PC_0, - D0 = PA_3, - D1 = PA_2, - D2 = PA_10, - D3 = PB_3, - D4 = PB_5, - D5 = PB_4, - D6 = PB_10, - D7 = PA_8, - D8 = PA_9, - D9 = PC_7, - D10 = PB_6, - D11 = PA_7, - D12 = PA_6, - D13 = PA_5, - D14 = PB_9, - D15 = PB_8, - - // Generic signals namings - LED1 = PG_12, - LED2 = PG_12, - LED3 = PG_12, - LED4 = PG_12, - USER_BUTTON = PC_13, - // Standardized button names - BUTTON1 = USER_BUTTON, - SERIAL_TX = PC_12, - SERIAL_RX = PD_2, - USBTX = PC_12, - USBRX = PD_2, - I2C_SCL = PC_0, - I2C_SDA = PC_1, - SPI_MOSI = PG_11, - SPI_MISO = PG_10, - SPI_SCK = PG_9, - SPI_CS = PG_12, - PWM_OUT = PB_3, - - //USB pins - USB_OTG_FS_SOF = PA_8, - USB_OTG_FS_VBUS = PA_9, - USB_OTG_FS_ID = PA_10, - USB_OTG_FS_DM = PA_11, - USB_OTG_FS_DP = PA_12, - USB_OTG_FS_NOE_ALT = PA_13, - USB_OTG_FS_NOE = PC_9, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c deleted file mode 100644 index 7dac0c38b3a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c +++ /dev/null @@ -1,328 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) - * | 3- USE_PLL_HSI (internal 16 MHz) - * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 80 - * AHBCLK (MHz) | 80 - * APB1CLK (MHz) | 80 - * APB2CLK (MHz) | 80 - * USB capable | YES - *----------------------------------------------------------------------------- -**/ - -#include "stm32l4xx.h" -#include "mbed_error.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock -#define USE_PLL_MSI 0x1 // Use MSI internal clock - -#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - -#if ((CLOCK_SOURCE) & USE_PLL_MSI) -uint8_t SetSysClock_PLL_MSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_MSI) - /* 4- If fail start with MSI clock */ - if (SetSysClock_PLL_MSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } - } - - // Output clock on MCO1 pin(PA8) for debugging purpose -#if DEBUG_MCO == 1 - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); -#endif -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - - // Used to gain time after DeepSleep in case HSI is used - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - return 0; - } - - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN - } - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) - RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) - RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) - - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { - return 0; // FAIL - } - - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - // Output clock on MCO1 pin(PA8) for debugging purpose -#if DEBUG_MCO == 2 - if (bypass == 0) { - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - } else { - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz - } -#endif - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - - // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) - RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) - RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { - return 0; // FAIL - } - - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - // Output clock on MCO1 pin(PA8) for debugging purpose -#if DEBUG_MCO == 3 - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz -#endif - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - -#if ((CLOCK_SOURCE) & USE_PLL_MSI) -/******************************************************************************/ -/* PLL (clocked by MSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - -#if MBED_CONF_TARGET_LSE_AVAILABLE - // Enable LSE Oscillator to automatically calibrate the MSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); -#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ - - /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ - RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ - RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ - RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ - RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - -#if MBED_CONF_TARGET_LSE_AVAILABLE - /* Enable MSI Auto-calibration through LSE */ - HAL_RCCEx_EnableMSIPLLMode(); -#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { - return 0; // FAIL - } - - // Output clock on MCO1 pin(PA8) for debugging purpose -#if DEBUG_MCO == 4 - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz -#endif - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h deleted file mode 100644 index cf3ad860850..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h +++ /dev/null @@ -1,54 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************GPIO***************/ -extern const PinMap PinMap_GPIO[]; - -/************PWM****************/ -#if DEVICE_PWMOUT -extern const PinMap PinMap_PWM[]; -#endif - -/************UART***************/ -#if DEVICE_SERIAL -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -#if DEVICE_SERIAL_FC -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; -#endif -#endif - -/************ADC***************/ -#if DEVICE_ANALOGIN -extern const PinMap PinMap_ADC[]; -#endif - -/************SPI***************/ -#if DEVICE_SPI -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h deleted file mode 100644 index 375c460af1b..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, - Port1 = 1, - Port2 = 2, - Port3 = 3 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c deleted file mode 100755 index 77f80daeb7d..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * ======== CC3220SF_LAUNCHXL.c ======== - * This file is responsible for setting up the board specific items for the - * CC3220SF_LAUNCHXL board. - */ - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "CC3220SF_LAUNCHXL.h" - -/* - * =============================== Power =============================== - */ -/* - * This table defines the parking state to be set for each parkable pin - * during LPDS. (Device pins must be parked during LPDS to achieve maximum - * power savings.) If the pin should be left unparked, specify the state - * PowerCC32XX_DONT_PARK. For example, for a UART TX pin, the device - * will automatically park the pin in a high state during transition to LPDS, - * so the Power Manager does not need to explictly park the pin. So the - * corresponding entries in this table should indicate PowerCC32XX_DONT_PARK. - */ -PowerCC32XX_ParkInfo parkInfo[] = { -/* PIN PARK STATE PIN ALIAS (FUNCTION) - ----------------- ------------------------------ -------------------- */ - {PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10 */ - {PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11 */ - {PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12 */ - {PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13 */ - {PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14 */ - {PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15 */ - {PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16 */ - {PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17 */ - {PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN */ - {PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22 */ - {PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG) */ - {PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG) */ - {PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG) */ - {PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG) */ - {PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28 */ - {PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2 */ - {PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1 */ - {PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2 */ - {PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P */ - {PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0 */ - {PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N */ - {PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30 */ - {PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO1 (XDS_UART_RX) */ - {PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO2 (XDS_UART_TX) */ - {PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3 */ - {PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4 */ - {PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5 */ - {PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6 */ - {PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7 */ - {PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8 */ - {PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9 */ -}; - -/* - * This structure defines the configuration for the Power Manager. - * - * In this configuration the Power policy is disabled by default (because - * enablePolicy is set to false). The Power policy can be enabled dynamically - * at runtime by calling Power_enablePolicy(), or at build time, by changing - * enablePolicy to true in this structure. - */ -const PowerCC32XX_ConfigV1 PowerCC32XX_config = { - .policyInitFxn = &PowerCC32XX_initPolicy, - .policyFxn = &PowerCC32XX_sleepPolicy, - .enterLPDSHookFxn = NULL, - .resumeLPDSHookFxn = NULL, - .enablePolicy = false, - .enableGPIOWakeupLPDS = true, - .enableGPIOWakeupShutdown = true, - .enableNetworkWakeupLPDS = true, - .wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13, - .wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE, - .wakeupGPIOFxnLPDS = NULL, - .wakeupGPIOFxnLPDSArg = 0, - .wakeupGPIOSourceShutdown = PRCM_HIB_GPIO13, - .wakeupGPIOTypeShutdown = PRCM_HIB_RISE_EDGE, - .ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 | - PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4, - .keepDebugActiveDuringLPDS = false, - .ioRetentionShutdown = PRCM_IO_RET_GRP_1, - .pinParkDefs = parkInfo, - .numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo) -}; -/* - * =============================== SPI =============================== - */ -#include -#include - -SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT]; - -#ifdef TOOLCHAIN_GCC_ARM -__attribute__ ((aligned (32))) -#elif defined TOOLCHAIN_ARM -__attribute__ ((aligned (32))) -#elif defined TOOLCHAIN_IAR -#pragma data_alignment=32 -#endif -uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT]; - -const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = { - /* index 0 is reserved for LSPI that links to the NWP */ - { - .baseAddr = LSPI_BASE, - .intNum = INT_LSPI, - .intPriority = (~0), - .spiPRCM = PRCM_LSPI, - .csControl = SPI_SW_CTRL_CS, - .csPolarity = SPI_CS_ACTIVEHIGH, - .pinMode = SPI_4PIN_MODE, - .turboMode = SPI_TURBO_OFF, - .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0], - .defaultTxBufValue = 0, - .rxChannelIndex = UDMA_CH12_LSPI_RX, - .txChannelIndex = UDMA_CH13_LSPI_TX, - .minDmaTransferSize = 100, - .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG, - .misoPin = SPICC32XXDMA_PIN_NO_CONFIG, - .clkPin = SPICC32XXDMA_PIN_NO_CONFIG, - .csPin = SPICC32XXDMA_PIN_NO_CONFIG - }, - { - .baseAddr = GSPI_BASE, - .intNum = INT_GSPI, - .intPriority = (~0), - .spiPRCM = PRCM_GSPI, - .csControl = SPI_HW_CTRL_CS, - .csPolarity = SPI_CS_ACTIVELOW, - .pinMode = SPI_4PIN_MODE, - .turboMode = SPI_TURBO_OFF, - .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1], - .defaultTxBufValue = 0, - .rxChannelIndex = UDMA_CH6_GSPI_RX, - .txChannelIndex = UDMA_CH7_GSPI_TX, - .minDmaTransferSize = 10, - .mosiPin = SPICC32XXDMA_PIN_07_MOSI, - .misoPin = SPICC32XXDMA_PIN_06_MISO, - .clkPin = SPICC32XXDMA_PIN_05_CLK, - .csPin = SPICC32XXDMA_PIN_08_CS - } -}; - -const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = { - { - .fxnTablePtr = &SPICC32XXDMA_fxnTable, - .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0], - .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0] - }, - { - .fxnTablePtr = &SPICC32XXDMA_fxnTable, - .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1], - .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1] - } -}; - -const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT; - -/* - * =============================== PWM =============================== - */ -#include -#include - -PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; - -const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { - { /* CC3220SF_LAUNCHXL_PWM6 */ - .pwmPin = PWMTimerCC32XX_PIN_01 - }, - { /* CC3220SF_LAUNCHXL_PWM7 */ - .pwmPin = PWMTimerCC32XX_PIN_02 - }, - { /* CC3220SF_LAUNCHXL_PWM0 */ - .pwmPin = PWMTimerCC32XX_PIN_17 - }, - { /* CC3220SF_LAUNCHXL_PWM3 */ - .pwmPin = PWMTimerCC32XX_PIN_19 - }, - { /* CC3220SF_LAUNCHXL_PWM2 */ - .pwmPin = PWMTimerCC32XX_PIN_21 - }, - { /* CC3220SF_LAUNCHXL_PWM5 */ - .pwmPin = PWMTimerCC32XX_PIN_64 - }, -}; - -const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { - { - .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], - .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] - }, - { - .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], - .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] - }, - { - .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM0], - .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM0] - }, - { - .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM3], - .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM3] - }, - { - .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM2], - .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM2] - }, - { - .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM5], - .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM5] - } -}; - -const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; - -/* - * =============================== DMA =============================== - */ -#include - -#if defined(__TI_COMPILER_VERSION__) -#pragma DATA_ALIGN(dmaControlTable, 1024) -#elif defined(__IAR_SYSTEMS_ICC__) -#pragma data_alignment=1024 -#elif defined(__GNUC__) -__attribute__ ((aligned (1024))) -#endif -static tDMAControlTable dmaControlTable[64]; - -/* - * ======== dmaErrorFxn ======== - * This is the handler for the uDMA error interrupt. - */ -static void dmaErrorFxn(uintptr_t arg) -{ - int status = MAP_uDMAErrorStatusGet(); - MAP_uDMAErrorStatusClear(); - - /* Suppress unused variable warning */ - (void)status; - - while (1); -} - -UDMACC32XX_Object udmaCC3220SObject; - -const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = { - .controlBaseAddr = (void *)dmaControlTable, - .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn, - .intNum = INT_UDMAERR, - .intPriority = (~0) -}; - -const UDMACC32XX_Config UDMACC32XX_config = { - .object = &udmaCC3220SObject, - .hwAttrs = &udmaCC3220SHWAttrs -}; -/* - * =============================== General =============================== - */ -/* - * ======== CC3220SF_LAUNCHXL_initGeneral ======== - */ -void CC3220SF_LAUNCHXL_initGeneral(void) -{ - MAP_IntMasterEnable(); - //MAP_IntEnable(FAULT_SYSTICK); - PRCMCC3200MCUInit(); - //Power_init(); -} - -#if defined TOOLCHAIN_ARM -__attribute__((section("signature_section"), used)) -#elif defined TOOLCHAIN_IAR -#pragma default_variable_attributes = @ ".dbghdr" -#elif defined TOOLCHAIN_GCC_ARM -__attribute__ ((section (".dbghdr"))) -#endif -const unsigned long ulDebugHeader[]= -{ - 0x5AA5A55A, - 0x000FF800, - 0xEFA3247D -}; diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h deleted file mode 100755 index efd23d0bbaa..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file C3220SF_LAUNCHXL.h - * - * @brief CC3220 Board Specific APIs - * - * The CC3220SF_LAUNCHXL header file should be included in an application as - * follows: - * @code - * #include - * @endcode - * - * ============================================================================ - */ -#ifndef __CC3220SF_LAUNCHXL_H -#define __CC3220SF_LAUNCHXL_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define CC3220SF_LAUNCHXL_GPIO_LED_OFF (0) -#define CC3220SF_LAUNCHXL_GPIO_LED_ON (1) - -/*! - * @def CC3220SF_LAUNCHXL_ADCName - * @brief Enum of ADC names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_ADCName { - CC3220SF_LAUNCHXL_ADC0 = 0, - CC3220SF_LAUNCHXL_ADC1, - - CC3220SF_LAUNCHXL_ADCCOUNT -} CC3220SF_LAUNCHXL_ADCName; - -/*! - * @def CC3220SF_LAUNCHXL_CaptureName - * @brief Enum of Capture names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_CaptureName { - CC3220SF_LAUNCHXL_CAPTURE0 = 0, - CC3220SF_LAUNCHXL_CAPTURE1, - - CC3220SF_LAUNCHXL_CAPTURECOUNT -} CC3220SF_LAUNCHXL_CaptureName; - -/*! - * @def CC3220SF_LAUNCHXL_CryptoName - * @brief Enum of Crypto names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_CryptoName { - CC3220SF_LAUNCHXL_CRYPTO0 = 0, - - CC3220SF_LAUNCHXL_CRYPTOCOUNT -} CC3220SF_LAUNCHXL_CryptoName; - -/*! - * @def CC3220SF_LAUNCHXL_GPIOName - * @brief Enum of GPIO names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_GPIOName { - CC3220SF_LAUNCHXL_GPIO_SW2 = 0, - CC3220SF_LAUNCHXL_GPIO_SW3, - CC3220SF_LAUNCHXL_SPI_MASTER_READY, - CC3220SF_LAUNCHXL_SPI_SLAVE_READY, - CC3220SF_LAUNCHXL_GPIO_LED_D7, - - /* - * CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the - * I2C and PWM peripherals. In order for those examples to work, these - * LEDs are taken out of gpioPinCOnfig[] - */ - /* CC3220SF_LAUNCHXL_GPIO_LED_D6, */ - /* CC3220SF_LAUNCHXL_GPIO_LED_D5, */ - - /* Sharp 96x96 LCD Pins */ - CC3220SF_LAUNCHXL_LCD_CS, - CC3220SF_LAUNCHXL_LCD_POWER, - CC3220SF_LAUNCHXL_LCD_ENABLE, - - CC3220SF_LAUNCHXL_GPIOCOUNT -} CC3220SF_LAUNCHXL_GPIOName; - -/*! - * @def CC3220SF_LAUNCHXL_I2CName - * @brief Enum of I2C names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_I2CName { - CC3220SF_LAUNCHXL_I2C0 = 0, - - CC3220SF_LAUNCHXL_I2CCOUNT -} CC3220SF_LAUNCHXL_I2CName; - -/*! - * @def CC3220SF_LAUNCHXL_I2SName - * @brief Enum of I2S names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_I2SName { - CC3220SF_LAUNCHXL_I2S0 = 0, - - CC3220SF_LAUNCHXL_I2SCOUNT -} CC3220SF_LAUNCHXL_I2SName; - -/*! - * @def CC3220SF_LAUNCHXL_PWMName - * @brief Enum of PWM names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_PWMName { - CC3220SF_LAUNCHXL_PWM6 = 0, - CC3220SF_LAUNCHXL_PWM7, - CC3220SF_LAUNCHXL_PWM0, - CC3220SF_LAUNCHXL_PWM3, - CC3220SF_LAUNCHXL_PWM2, - CC3220SF_LAUNCHXL_PWM5, - CC3220SF_LAUNCHXL_PWMCOUNT -} CC3220SF_LAUNCHXL_PWMName; - -/*! - * @def CC3220SF_LAUNCHXL_SDFatFSName - * @brief Enum of SDFatFS names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_SDFatFSName { - CC3220SF_LAUNCHXL_SDFatFS0 = 0, - - CC3220SF_LAUNCHXL_SDFatFSCOUNT -} CC3220SF_LAUNCHXL_SDFatFSName; - -/*! - * @def CC3220SF_LAUNCHXL_SDName - * @brief Enum of SD names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_SDName { - CC3220SF_LAUNCHXL_SD0 = 0, - - CC3220SF_LAUNCHXL_SDCOUNT -} CC3220SF_LAUNCHXL_SDName; - -/*! - * @def CC3220SF_LAUNCHXL_SPIName - * @brief Enum of SPI names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_SPIName { - CC3220SF_LAUNCHXL_SPI0 = 0, - CC3220SF_LAUNCHXL_SPI1, - - CC3220SF_LAUNCHXL_SPICOUNT -} CC3220SF_LAUNCHXL_SPIName; - -/*! - * @def CC3220SF_LAUNCHXL_TimerName - * @brief Enum of Timer names on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_TimerName { - CC3220SF_LAUNCHXL_TIMER0 = 0, - CC3220SF_LAUNCHXL_TIMER1, - CC3220SF_LAUNCHXL_TIMER2, - - CC3220SF_LAUNCHXL_TIMERCOUNT -} CC3220SF_LAUNCHXL_TimerName; - -/*! - * @def CC3220SF_LAUNCHXL_UARTName - * @brief Enum of UARTs on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_UARTName { - CC3220SF_LAUNCHXL_UART0 = 0, - CC3220SF_LAUNCHXL_UART1, - - CC3220SF_LAUNCHXL_UARTCOUNT -} CC3220SF_LAUNCHXL_UARTName; - -/*! - * @def CC3220SF_LAUNCHXL_WatchdogName - * @brief Enum of Watchdogs on the CC3220SF_LAUNCHXL dev board - */ -typedef enum CC3220SF_LAUNCHXL_WatchdogName { - CC3220SF_LAUNCHXL_WATCHDOG0 = 0, - - CC3220SF_LAUNCHXL_WATCHDOGCOUNT -} CC3220SF_LAUNCHXL_WatchdogName; - -/*! - * @brief Initialize the general board specific settings - * - * This function initializes the general board specific settings. - */ -extern void CC3220SF_LAUNCHXL_initGeneral(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CC3220SF_LAUNCHXL_H */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h deleted file mode 100644 index 97f72f739ec..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)CC3220SF_UARTA0_BASE, - UART_1 = (int)CC3220SF_UARTA1_BASE -} UARTName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3 -} ADCName; - -typedef enum { - PWM_1 = 1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6 -} PWMName; - -typedef enum { - GSPI = 0 -} SPIName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -#define MBED_UART0 P55, P57 -#define MBED_UART1 P07, P08 -#define MBED_UARTUSB USBTX, USBRX - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c deleted file mode 100644 index 33a53adabee..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c +++ /dev/null @@ -1,159 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************GPIO***************/ -const PinMap PinMap_GPIO[] = { - {PIN_50, CC3220SF_GPIOA0_BASE, 0}, //GPIO_00 (PM/Dig Mux) - {PIN_55, CC3220SF_GPIOA0_BASE, 1}, //GPIO_01 - {PIN_57, CC3220SF_GPIOA0_BASE, 2}, //GPIO_02 (Dig/ADC Mux) - {PIN_58, CC3220SF_GPIOA0_BASE, 3}, //GPIO_03 (Dig/ADC Mux) - {PIN_59, CC3220SF_GPIOA0_BASE, 4}, //GPIO_04 (Dig/ADC Mux) - {PIN_60, CC3220SF_GPIOA0_BASE, 5}, //GPIO_05 (Dig/ADC Mux) - {PIN_61, CC3220SF_GPIOA0_BASE, 6}, //GPIO_06 - {PIN_62, CC3220SF_GPIOA0_BASE, 7}, //GPIO_07 - - {PIN_63, CC3220SF_GPIOA1_BASE, 8}, //GPIO_08 - {PIN_64, CC3220SF_GPIOA1_BASE, 9}, //GPIO_09 - {PIN_01, CC3220SF_GPIOA1_BASE, 10}, //GPIO_10 - {PIN_02, CC3220SF_GPIOA1_BASE, 11}, //GPIO_11 - {PIN_03, CC3220SF_GPIOA1_BASE, 12}, //GPIO_12 - {PIN_04, CC3220SF_GPIOA1_BASE, 13}, //GPIO_13 - {PIN_05, CC3220SF_GPIOA1_BASE, 14}, //GPIO_14 - {PIN_06, CC3220SF_GPIOA1_BASE, 15}, //GPIO_15 - - {PIN_07, CC3220SF_GPIOA2_BASE, 16}, //GPIO_16 - {PIN_08, CC3220SF_GPIOA2_BASE, 17}, //GPIO_17 - //this is only here for reference - {PIN_XX, CC3220SF_GPIOA2_BASE, 18}, //GPIO_18 (Reserved) No package pin associate with this GPIO - {PIN_XX, CC3220SF_GPIOA2_BASE, 19}, //GPIO_19 (Reserved) No package pin associate with this GPIO - {PIN_XX, CC3220SF_GPIOA2_BASE, 20}, //GPIO_20 (Reserved) No package pin associate with this GPIO - {PIN_XX, CC3220SF_GPIOA2_BASE, 21}, //GPIO_21 (Reserved) No package pin associate with this GPIO - {PIN_15, CC3220SF_GPIOA2_BASE, 22}, //GPIO_22 - {PIN_16, CC3220SF_GPIOA2_BASE, 23}, //GPIO_23 - - {PIN_17, CC3220SF_GPIOA3_BASE, 24}, //GPIO_24 - // pin 21 is one of three that must have a passive pullup or pulldown resistor - // on board to configure the chip hardware power-up mode. Because of this, - // if this pin is used for digital functions, it must be output only. - {PIN_21, CC3220SF_GPIOA3_BASE, 25}, //GPIO_25 - //this is only here for reference - {PIN_XX, CC3220SF_GPIOA3_BASE, 26}, //GPIO_26 (Restricted Use; Antenna Selection 1 Only) No package pin associate with this GPIO - {PIN_XX, CC3220SF_GPIOA3_BASE, 27}, //GPIO_27 (Restricted Use; Antenna Selection 1 Only) No package pin associate with this GPIO - {PIN_18, CC3220SF_GPIOA3_BASE, 28}, //GPIO_28 - {PIN_20, CC3220SF_GPIOA3_BASE, 29}, //GPIO_29 - {PIN_53, CC3220SF_GPIOA3_BASE, 30}, //GPIO_30 (PM/Dig Mux) - {PIN_45, CC3220SF_GPIOA3_BASE, 31}, //GPIO_31 (PM/Dig Mux) - {NC, NC, 0} -}; - -/************PWM***************/ -#if DEVICE_PWMOUT -const PinMap PinMap_PWM[] = { - {PIN_01, PWM_1, 3}, - {PIN_02, PWM_2, 3}, - {PIN_17, PWM_3, 5}, - {PIN_19, PWM_4, 8}, - {PIN_21, PWM_5, 9}, - {PIN_64, PWM_6, 3}, - {NC, NC, 0} -}; -#endif - -/************UART***************/ -#if DEVICE_SERIAL -const PinMap PinMap_UART_TX[] = { - {PIN_01, UART_1, 7}, - {PIN_03, UART_0, 7}, - {PIN_07, UART_1, 5}, - {PIN_16, UART_1, 2}, - {PIN_53, UART_0, 9}, - {PIN_55, UART_0, 3}, - {PIN_55, UART_1, 6}, - {PIN_58, UART_1, 6}, - {PIN_62, UART_0, 11}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PIN_02, UART_1, 7}, - {PIN_04, UART_0, 7}, - {PIN_08, UART_1, 5}, - {PIN_17, UART_1, 2}, - {PIN_45, UART_0, 9}, - {PIN_45, UART_1, 2}, - {PIN_57, UART_0, 3}, - {PIN_57, UART_1, 6}, - {PIN_59, UART_1, 6}, - {NC, NC, 0} -}; -#if DEVICE_SERIAL_FC -const PinMap PinMap_UART_RTS[] = { - {PIN_50, UART_0, 3}, - {PIN_50, UART_1, 10}, - {PIN_52, UART_0, 6}, - {PIN_61, UART_0, 5}, - {PIN_62, UART_0, 10}, - {PIN_62, UART_1, 3}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_CTS[] = { - {PIN_50, UART_0, 12}, - {PIN_61, UART_0, 6}, - {PIN_61, UART_1, 3}, - {NC, NC, 0} -}; -#endif -#endif - -#if DEVICE_ANALOGIN -const PinMap PinMap_ADC[] = { - {PIN_57, ADC0_0, 0}, - {PIN_58, ADC0_1, 0}, - {PIN_59, ADC0_2, 0}, - {PIN_60, ADC0_3, 0}, - {NC, NC, 0} -}; -#endif - -#if DEVICE_SPI -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PIN_05, GSPI, 7}, - {PIN_45, GSPI, 7}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PIN_07, GSPI, 7}, - {PIN_52, GSPI, 7}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PIN_06, GSPI, 7}, - {PIN_53, GSPI, 7}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PIN_08, GSPI, 7}, - {PIN_50, GSPI, 7}, - {NC, NC, 0} -}; -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PinNames.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PinNames.h deleted file mode 100644 index ab2651d7016..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PinNames.h +++ /dev/null @@ -1,161 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - P01 = 0x00000000, - P02 = 0x00000001, - P03 = 0x00000002, - P04 = 0x00000003, - P05 = 0x00000004, - P06 = 0x00000005, - P07 = 0x00000006, - P08 = 0x00000007, - P11 = 0x0000000A, - P12 = 0x0000000B, - P13 = 0x0000000C, - P14 = 0x0000000D, - P15 = 0x0000000E, - P16 = 0x0000000F, - P17 = 0x00000010, - P18 = 0x00000011, - P19 = 0x00000012, - P20 = 0x00000013, - P21 = 0x00000014, - P29 = 0x0000001C, - P30 = 0x0000001D, - P45 = 0x0000002C, - P46 = 0x0000002D, - P47 = 0x0000002E, - P48 = 0x0000002F, - P49 = 0x00000030, - P50 = 0x00000031, - P52 = 0x00000033, - P53 = 0x00000034, - P55 = 0x00000036, - P56 = 0x00000037, - P57 = 0x00000038, - P58 = 0x00000039, - P59 = 0x0000003A, - P60 = 0x0000003B, - P61 = 0x0000003C, - P62 = 0x0000003D, - P63 = 0x0000003E, - P64 = 0x0000003F, - - PIN_01 = P01, - PIN_02 = P02, - PIN_03 = P03, - PIN_04 = P04, - PIN_05 = P05, - PIN_06 = P06, - PIN_07 = P07, - PIN_08 = P08, - PIN_11 = P11, - PIN_12 = P12, - PIN_13 = P13, - PIN_14 = P14, - PIN_15 = P15, - PIN_16 = P16, - PIN_17 = P17, - PIN_18 = P18, - PIN_19 = P19, - PIN_20 = P20, - PIN_21 = P21, - PIN_29 = P29, - PIN_30 = P30, - PIN_45 = P45, - PIN_46 = P46, - PIN_47 = P47, - PIN_48 = P48, - PIN_49 = P49, - PIN_50 = P50, - PIN_52 = P52, - PIN_53 = P53, - PIN_55 = P55, - PIN_56 = P56, - PIN_57 = P57, - PIN_58 = P58, - PIN_59 = P59, - PIN_60 = P60, - PIN_61 = P61, - PIN_62 = P62, - PIN_63 = P63, - PIN_64 = P64, - - //LED 1 => RED, LED 2 => YELLOW, LED 3 = GREEN - LED1 = PIN_64, - LED2 = PIN_01, - LED3 = PIN_02, - - LED_RED = LED1, - LED_YELLOW = LED2, - LED_GREEN = LED3, - - // UART0 - USBTX = PIN_55, - USBRX = PIN_57, - - //Button - BUTTON1 = PIN_04, - BUTTON2 = PIN_15, - - //SPI1 - SPICC32XXDMA_MOSI = P07, - SPICC32XXDMA_MISO = P06, - SPICC32XXDMA_CLK = P05, - SPICC32XXDMA_CS = P08, - - // CI Shield - D10 = SPICC32XXDMA_CS, - D11 = SPICC32XXDMA_MOSI, - D12 = SPICC32XXDMA_MISO, - D13 = SPICC32XXDMA_CLK, - - // Not connected - NC = (int)0xFFFFFFFF, - PIN_RESERVED = NC, - PIN_XX = NC -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - OpenDrain = 3, - OpenDrainPullUp = 4, - OpenDrainPullDown = 5, - Analog = 6, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/TargetConfiguration.ccxml b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/TargetConfiguration.ccxml deleted file mode 100644 index bb4ded18916..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/TargetConfiguration.ccxml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c deleted file mode 100644 index 7c636f9d310..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c +++ /dev/null @@ -1,73 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "PinNames.h" -#include "cmsis.h" - -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/driverlib/adc.h" -#include "ti/devices/cc32xx/driverlib/prcm.h" -#include "ti/devices/cc32xx/driverlib/pin.h" -#include "ti/devices/cc32xx/inc/hw_memmap.h" - -#define ADC_DATA_MASK 0x3FFC //the data is from bit [13:2] -#define ADC_RESOLUTION 0xFFF - -void analogin_init(analogin_t *obj, PinName pin) -{ - ADCEnable(CC3220SF_ADC_BASE); - obj->pin = pin; - pin_mode(pin, Analog); - switch (pin) { - case PIN_57: - obj->adc_ch = ADC_CH_0; - break; - case PIN_58: - obj->adc_ch = ADC_CH_1; - break; - case PIN_59: - obj->adc_ch = ADC_CH_2; - break; - case PIN_60: - obj->adc_ch = ADC_CH_3; - break; - default: - MBED_ASSERT(NC != (PinName)NC); - } - - ADCChannelEnable(CC3220SF_ADC_BASE, obj->adc_ch); -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - unsigned long adc_raw = ADCFIFORead(CC3220SF_ADC_BASE, obj->adc_ch); - - return (uint16_t)((adc_raw & ADC_DATA_MASK) >> 2); -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)ADC_RESOLUTION); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device.h deleted file mode 100644 index 33ce58a44a1..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device.h +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h deleted file mode 100644 index feb3e90c50b..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h +++ /dev/null @@ -1,346 +0,0 @@ -/**************************************************************************//** - * @file CC3220SF.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for - * Device CC3220SF - * @version V5.00 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef CC3220SF_H -#define CC3220SF_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -// mbed-os core_cm4.h adds offset of 16. Deduct 16 from the IRQ enums -#define INT_IRQn_OFFSET 16 - -typedef enum IRQn -{ -/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ - - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - -/* =========================================== CC3220SF Specific Interrupt Numbers ========================================= */ - INT_GPIOA0_IRQn = 16 - INT_IRQn_OFFSET, // GPIO Port S0 - INT_GPIOA1_IRQn = 17 - INT_IRQn_OFFSET, // GPIO Port S1 - INT_GPIOA2_IRQn = 18 - INT_IRQn_OFFSET, // GPIO Port S2 - INT_GPIOA3_IRQn = 19 - INT_IRQn_OFFSET, // GPIO Port S3 - INT_UARTA0_IRQn = 21 - INT_IRQn_OFFSET, // UART0 Rx and Tx - INT_UARTA1_IRQn = 22 - INT_IRQn_OFFSET, // UART1 Rx and Tx - INT_I2CA0_IRQn = 24 - INT_IRQn_OFFSET, // I2C controller - INT_ADCCH0_IRQn = 30 - INT_IRQn_OFFSET, // ADC Sequence 0 - INT_ADCCH1_IRQn = 31 - INT_IRQn_OFFSET, // ADC Sequence 1 - INT_ADCCH2_IRQn = 32 - INT_IRQn_OFFSET, // ADC Sequence 2 - INT_ADCCH3_IRQn = 33 - INT_IRQn_OFFSET, // ADC Sequence 3 - INT_WDT_IRQn = 34 - INT_IRQn_OFFSET, // Watchdog Timer0 - INT_TIMERA0A_IRQn = 35 - INT_IRQn_OFFSET, // Timer 0 subtimer A - INT_TIMERA0B_IRQn = 36 - INT_IRQn_OFFSET, // Timer 0 subtimer B - INT_TIMERA1A_IRQn = 37 - INT_IRQn_OFFSET, // Timer 1 subtimer A - INT_TIMERA1B_IRQn = 38 - INT_IRQn_OFFSET, // Timer 1 subtimer B - INT_TIMERA2A_IRQn = 39 - INT_IRQn_OFFSET, // Timer 2 subtimer A - INT_TIMERA2B_IRQn = 40 - INT_IRQn_OFFSET, // Timer 2 subtimer B - INT_FLASH_IRQn = 45 - INT_IRQn_OFFSET, // FLASH Control - INT_TIMERA3A_IRQn = 51 - INT_IRQn_OFFSET, // Timer 3 subtimer A - INT_TIMERA3B_IRQn = 52 - INT_IRQn_OFFSET, // Timer 3 subtimer B - INT_UDMA_IRQn = 62 - INT_IRQn_OFFSET, // uDMA controller - INT_UDMAERR_IRQn = 63 - INT_IRQn_OFFSET, // uDMA Error - INT_SHA_IRQn = 164 - INT_IRQn_OFFSET, // SHA - INT_AES_IRQn = 167 - INT_IRQn_OFFSET, // AES - INT_DES_IRQn = 169 - INT_IRQn_OFFSET, // DES - INT_MMCHS_IRQn = 175 - INT_IRQn_OFFSET, // SDIO - INT_I2S_IRQn = 177 - INT_IRQn_OFFSET, // McAPS - INT_CAMERA_IRQn = 179 - INT_IRQn_OFFSET, // Camera - INT_NWPIC_IRQn = 187 - INT_IRQn_OFFSET, // Interprocessor communication - INT_PRCM_IRQn = 188 - INT_IRQn_OFFSET, // Power, Reset and Clock Module - INT_SSPI_IRQn = 191 - INT_IRQn_OFFSET, // Shared SPI - INT_GSPI_IRQn = 192 - INT_IRQn_OFFSET, // Generic SPI - INT_LSPI_IRQn = 193 - INT_IRQn_OFFSET // Link SPI -} IRQn_Type; - - - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* =========================== Configuration of the Arm Cortex-M4 Processor and Core Peripherals =========================== */ -#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */ -/* ToDo: define the correct core features for the CC3220SF */ -#define __MPU_PRESENT 1 /*!< Set to 1 if MPU is present */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0 /*!< Set to 1 if FPU is present */ -#define __FPU_DP 0 /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */ -#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ -#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ -#define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */ - - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include /*!< Arm Cortex-M4 processor and core peripherals */ -#include "system_CC3220SF.h" /*!< CC3220SF System */ - - -/* ======================================== Start of section using anonymous unions ======================================== */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ GPIO ================ */ -/* =========================================================================================================================== */ - -/** - * @brief GPIO - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Address offset : 0x00000000 */ - uint32_t RESERVED0[255]; - __IO uint32_t DIR; /*!< Address offset : 0x00000400 */ - __IO uint32_t IS; /*!< Address offset : 0x00000404 */ - __IO uint32_t IBE; /*!< Address offset : 0x00000408 */ - __IO uint32_t IEV; /*!< Address offset : 0x0000040C */ - __IO uint32_t IM; /*!< Address offset : 0x00000410 */ - __IO uint32_t RIS; /*!< Address offset : 0x00000414 */ - __IO uint32_t MIS; /*!< Address offset : 0x00000418 */ - __O uint32_t ICR; /*!< Address offset : 0x0000041C */ - __IO uint32_t AFSEL; /*!< Address offset : 0x00000420 */ - uint32_t RESERVED1[55]; - __IO uint32_t DR2R; /*!< Address offset : 0x00000500 */ - __IO uint32_t DR4R; /*!< Address offset : 0x00000504 */ - __IO uint32_t DR8R; /*!< Address offset : 0x00000508 */ - __IO uint32_t ODR; /*!< Address offset : 0x0000050C */ - __IO uint32_t PUR; /*!< Address offset : 0x00000510 */ - __IO uint32_t PDR; /*!< Address offset : 0x00000514 */ - __IO uint32_t SLR; /*!< Address offset : 0x00000518 */ - __IO uint32_t DEN; /*!< Address offset : 0x0000051C */ - __IO uint32_t LOCK; /*!< Address offset : 0x00000520 */ - __IO uint32_t CR; /*!< Address offset : 0x00000524 */ - __IO uint32_t AMSEL; /*!< Address offset : 0x00000528 */ - __IO uint32_t PCTL; /*!< Address offset : 0x0000052C ! This register is not used in cc3xx. ! */ - __IO uint32_t ADCCTL; /*!< Address offset : 0x00000530 ! This register is not used in cc3xx. ! */ - __IO uint32_t DMACTL; /*!< Address offset : 0x00000534 */ - __IO uint32_t SI; /*!< Address offset : 0x00000538 */ - uint32_t RESERVED2[677]; - __IO uint32_t PERIPHID4; /*!< Address offset : 0x00000FD0 */ - __IO uint32_t PERIPHID5; /*!< Address offset : 0x00000FD4 */ - __IO uint32_t PERIPHID6; /*!< Address offset : 0x00000FD8 */ - __IO uint32_t PERIPHID7; /*!< Address offset : 0x00000FDC */ - __IO uint32_t PERIPHID0; /*!< Address offset : 0x00000FE0 */ - __IO uint32_t PERIPHID1; /*!< Address offset : 0x00000FE4 */ - __IO uint32_t PERIPHID2; /*!< Address offset : 0x00000FE8 */ - __IO uint32_t PERIPHID3; /*!< Address offset : 0x00000FEC */ - __IO uint32_t PCELLID0; /*!< Address offset : 0x00000FF0 */ - __IO uint32_t PCELLID1; /*!< Address offset : 0x00000FF4 */ - __IO uint32_t PCELLID2; /*!< Address offset : 0x00000FF8 */ - __IO uint32_t PCELLID3; /*!< Address offset : 0x00000FFC */ -} CC3220SF_GPIO_TypeDef; - -/* =========================================================================================================================== */ -/* ================ UART ================ */ -/* =========================================================================================================================== */ - -/** - * @brief UART - */ -typedef struct -{ - __IO uint32_t DR; /*!< Data, Address offset : 0x00 */ - union { - __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */ - __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */ - }; - uint32_t RESERVED0[4]; - __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */ - uint32_t RESERVED1[1]; - __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */ - __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */ - __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */ - __IO uint32_t LCRH; /*!< Line Control, Address offset : 0x2C */ - __IO uint32_t CTL; /*!< Control, Address offset : 0x30 */ - __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */ - __IO uint32_t IM; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */ - __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */ - __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */ - __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */ - __IO uint32_t DMACTL; /*!< DMA Control, Address offset : 0x48 */ - __IO uint32_t LCTL; /*!< Address offset : 0x90 */ - __IO uint32_t LSS; /*!< Address offset : 0x94 */ - __IO uint32_t LTIM; /*!< Address offset : 0x98 */ - __IO uint32_t BITADDR; /*!< 9BITADDR Address offset : 0xA4 */ - __IO uint32_t BITMASK; /*!< 9BITMASK Address offset : 0xA8 */ - __IO uint32_t PP; /*!< Address offset : 0xFC0 */ - __IO uint32_t CC; /*!< Address offset : 0xFC8 */ -} CC3220SF_UART_TypeDef; - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -/* Peripheral and SRAM base address */ -#define CC3220SF_FLASH_BASE 0x01000000 -#define CC3220SF_SRAM_BASE 0x20000000 -#define CC3220SF_WDT_BASE 0x40000000 -#define CC3220SF_GPIOA0_BASE 0x40004000 -#define CC3220SF_GPIOA1_BASE 0x40005000 -#define CC3220SF_GPIOA2_BASE 0x40006000 -#define CC3220SF_GPIOA3_BASE 0x40007000 -#define CC3220SF_GPIOA4_BASE 0x40024000 -#define CC3220SF_UARTA0_BASE 0x4000C000 -#define CC3220SF_UARTA1_BASE 0x4000D000 -#define CC3220SF_I2CA0_BASE 0x40020000 -#define CC3220SF_TIMERA0_BASE 0x40030000 -#define CC3220SF_TIMERA1_BASE 0x40031000 -#define CC3220SF_TIMERA2_BASE 0x40032000 -#define CC3220SF_TIMERA3_BASE 0x40033000 -#define CC3220SF_STACKDIE_CTRL_BASE 0x400F5000 -#define CC3220SF_COMMON_REG_BASE 0x400F7000 -#define CC3220SF_FLASH_CONTROL_BASE 0x400FD000 -#define CC3220SF_SYSTEM_CONTROL_BASE 0x400FE000 -#define CC3220SF_UDMA_BASE 0x400FF000 -#define CC3220SF_SDHOST_BASE 0x44010000 -#define CC3220SF_CAMERA_BASE 0x44018000 -#define CC3220SF_I2S_BASE 0x4401C000 -#define CC3220SF_SSPI_BASE 0x44020000 -#define CC3220SF_GSPI_BASE 0x44021000 -#define CC3220SF_LSPI_BASE 0x44022000 -#define CC3220SF_ARCM_BASE 0x44025000 -#define CC3220SF_APPS_CONFIG_BASE 0x44026000 -#define CC3220SF_GPRCM_BASE 0x4402D000 -#define CC3220SF_OCP_SHARED_BASE 0x4402E000 -#define CC3220SF_ADC_BASE 0x4402E800 -#define CC3220SF_HIB1P2_BASE 0x4402F000 -#define CC3220SF_HIB3P3_BASE 0x4402F800 -#define CC3220SF_DTHE_BASE 0x44030000 -#define CC3220SF_SHAMD5_BASE 0x44035000 -#define CC3220SF_AES_BASE 0x44037000 -#define CC3220SF_DES_BASE 0x44039000 - -/** - * @} - */ - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -/******************************************************************************/ -/* */ -/* GPIO */ -/* */ -/******************************************************************************/ - -#define CC3220SF_GPIO0 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA0_BASE) -#define CC3220SF_GPIO1 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA1_BASE) -#define CC3220SF_GPIO2 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA2_BASE) -#define CC3220SF_GPIO3 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA3_BASE) -#define CC3220SF_GPIO4 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA4_BASE) - -/******************************************************************************/ -/* */ -/* UART */ -/* */ -/******************************************************************************/ - -#define CC3220SF_UART0 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA0_BASE) -#define CC3220SF_UART1 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA1_BASE) - - -/** - * @} - */ - - -/* ========================================= End of section using anonymous unions ========================================= */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* CC3220SF_H */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.cpp deleted file mode 100755 index 267980a3cab..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.cpp +++ /dev/null @@ -1,160 +0,0 @@ -/* CC3220SF_Init.cpp - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "nsapi_types.h" -#include "ti/drivers/net/wifi/netcfg.h" -#include "ti/drivers/ti_SPI.h" -#include "ti/drivers/dma/UDMACC32XX.h" -#include "ti/drivers/net/wifi/sl_socket.h" -#include "ti/drivers/net/wifi/netapp.h" -#include "ti/drivers/net/wifi/wlan.h" -#include "mbed.h" -#include "cc3200_simplelink.h" -#include "CC3220SF_Init.h" - -#define CHANNEL_MASK_ALL (0x1FFF) -#define RSSI_TH_MAX (-95) -#define TASK_STACK_SIZE (2048) - -/* The SimpleLink host driver architecture mandate spawn thread to be created prior to calling Sl_start (turning the NWP on). */ -/* The purpose of this thread is to handle asynchronous events sent from the NWP. - * Every event is classified and later handled by the Host driver event handlers. */ -Thread sl_Task_thread(osPriorityNormal, TASK_STACK_SIZE, NULL, "sl_task_thread"); -Mutex sl_init_mutex; - -void sl_task_entry() -{ - sl_Task(NULL); -} - -int CC3220SF_initSimplelink(void) -{ - uint8_t ucConfigOpt; - uint8_t ucPower; - int32_t RetVal = -1; - int32_t Mode = -1; - uint32_t IfBitmap = 0; - SlWlanScanParamCommand_t ScanDefault = {0}; - SlWlanRxFilterOperationCommandBuff_t RxFilterIdMask = {{0}}; - static bool simplelink_powered = false; - - sl_init_mutex.lock(); - if (!simplelink_powered) - { - if (sl_Task_thread.start(callback(sl_task_entry)) != osOK) - { - printf("sl_Task failed\n"); - sl_init_mutex.unlock(); - return -1; - } - UDMACC32XX_init(); - SPI_init(); - - /* Turn NWP on */ - Mode = sl_Start(0, 0, 0); - if(Mode != ROLE_STA) - { - /* Set NWP role as STA */ - RetVal = sl_WlanSetMode(ROLE_STA); - assert(RetVal == 0); - - /* For changes to take affect, we restart the NWP */ - RetVal = sl_Stop(0); - assert(RetVal == 0); - - Mode = sl_Start(0, 0, 0); - assert(RetVal == 0); - } - - if(Mode != ROLE_STA) - { - printf("Failed to configure device to it's default state"); - sl_init_mutex.unlock(); - return -1; - } - - /* Set policy to auto only */ - RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION, SL_WLAN_CONNECTION_POLICY(1,0,0,0), NULL ,0); - assert(RetVal == 0); - - /* Disable Auto Provisioning */ - RetVal = sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP, 0xFF, 0, NULL, 0x0); - assert(RetVal == 0); - - /* Delete existing profiles */ - RetVal = sl_WlanProfileDel(0xFF); - assert(RetVal == 0); - - /* enable DHCP client */ - RetVal = sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_DHCP, 0, 0); - assert(RetVal == 0); - - /* Disable ipv6 */ - IfBitmap = !(SL_NETCFG_IF_IPV6_STA_LOCAL | SL_NETCFG_IF_IPV6_STA_GLOBAL); - RetVal = sl_NetCfgSet(SL_NETCFG_IF, SL_NETCFG_IF_STATE, sizeof(IfBitmap),(const unsigned char *)&IfBitmap); - assert(RetVal == 0); - - /* Configure scan parameters to default */ - ScanDefault.ChannelsMask = CHANNEL_MASK_ALL; - ScanDefault.RssiThreshold = RSSI_TH_MAX; - - RetVal = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS, sizeof(ScanDefault), (uint8_t *)&ScanDefault); - assert(RetVal == 0); - - /* Disable scans */ - ucConfigOpt = SL_WLAN_SCAN_POLICY(0, 0); - RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_SCAN , ucConfigOpt, NULL, 0); - assert(RetVal == 0); - - /* Set TX power lvl to max */ - ucPower = 0; - RetVal = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER, 1, (uint8_t *)&ucPower); - assert(RetVal == 0); - - /* Set NWP Power policy to 'normal' */ - RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_PM, SL_WLAN_NORMAL_POLICY, NULL, 0); - assert(RetVal == 0); - - /* Unregister mDNS services */ - RetVal = sl_NetAppMDNSUnRegisterService(0, 0, 0); - assert(RetVal == 0); - - /* Remove all 64 RX filters (8*8) */ - memset(RxFilterIdMask.FilterBitmap , 0xFF, 8); - - RetVal = sl_WlanSet(SL_WLAN_RX_FILTERS_ID, SL_WLAN_RX_FILTER_REMOVE, sizeof(SlWlanRxFilterOperationCommandBuff_t),(uint8_t *)&RxFilterIdMask); - assert(RetVal == 0); - - /* Set NWP role as STA */ - RetVal = sl_WlanSetMode(ROLE_STA); - assert(RetVal == 0); - - /* For changes to take affect, we restart the NWP */ - RetVal = sl_Stop(0/*SL_STOP_TIMEOUT*/); - assert(RetVal == 0); - - Mode = sl_Start(0, 0, 0); - if(ROLE_STA != Mode) - { - printf("Failed to configure device to its default state\n"); - sl_init_mutex.unlock(); - return -1; - } - simplelink_powered = true; - } - sl_init_mutex.unlock(); - return 0; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.h deleted file mode 100755 index 1a577dba3ba..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.h +++ /dev/null @@ -1,30 +0,0 @@ -/* CC3220SF_Init.h - * - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __CC3220SF_INIT_H -#define __CC3220SF_INIT_H - -#ifdef __cplusplus -extern "C" { -#endif - -int CC3220SF_initSimplelink(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CC3220SF_INIT_H */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp deleted file mode 100644 index 4515891ff61..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp +++ /dev/null @@ -1,674 +0,0 @@ -/* CC3220SF implementation of NetworkInterfaceAPI - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cc3200_simplelink.h" -#include "CC3220SF_WiFiInterface.h" - -#define CONNECT_TIMEOUT_MS (4000) -#define IP_SET_TIMEOUT_MS (2000) -#define READ_THREAD_SLEEP_MS (50) -#define SOCKET_TASK_STACK_SIZE (2048) - -CC3220SFInterface * CC3220SFInterface::cc3200sf_wifi_instance; - -CC3220SFInterface::CC3220SFInterface(): - _thread_read_socket(osPriorityNormal, SOCKET_TASK_STACK_SIZE, NULL, "read_socket_thread"), - _initialized(false), - _started(false), - _channel(6), - _connect_sem(0, 1), - _ip_set_sem(0, 1) -{ - memset(_id_in_use, 0, sizeof(_id_in_use)); - memset(_socket_obj, 0, sizeof(_socket_obj)); - memset(_cbs, 0, sizeof(_cbs)); - memset(_ssid, 0, sizeof(_ssid)); - memset(_pass, 0, sizeof(_pass)); - _security = NSAPI_SECURITY_UNKNOWN; - cc3200sf_wifi_instance = this; - _cc3200_simplelink.initialize(); - _thread_read_socket.start(callback(this, &CC3220SFInterface::_socket_background_thread)); -} - -nsapi_error_t CC3220SFInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, - uint8_t channel) -{ - nsapi_error_t ret_code; - - ret_code = set_credentials(ssid, pass, security); - if(ret_code) - { - printf ("set_credentials failed with 0x%x\n", ret_code); - return ret_code; - } - - return connect(); -} - -nsapi_error_t CC3220SFInterface::connect() -{ - nsapi_error_t status; - - if (strlen(_ssid) == 0) - { - return NSAPI_ERROR_NO_SSID; - } - - if(get_ip_address()) - { - return NSAPI_ERROR_IS_CONNECTED; - } - - _cc3200_simplelink.set_connection_status(NSAPI_STATUS_CONNECTING); - - status = _startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION); - if(status != NSAPI_ERROR_OK) - { - return status; - } - _started = true; - - if (!_cc3200_simplelink.dhcp(true, CC3200_SIMPLELINK::WIFI_ROLE_STATION)) - { - return NSAPI_ERROR_DHCP_FAILURE; - } - int connect_error = _cc3200_simplelink.connect(_ssid, _pass, _security); - if (connect_error) - { - return connect_error; - } - - // Connect is async call. Wait till connection completes - if (_connect_sem.try_acquire_for(CONNECT_TIMEOUT_MS) == false) - { - printf("Connection timed out\n"); - return NSAPI_ERROR_CONNECTION_TIMEOUT; - } - if (_ip_set_sem.try_acquire_for(IP_SET_TIMEOUT_MS) == false) - { - printf("IP address set timed out\n"); - } - else - { - _cc3200_simplelink.set_connection_status(NSAPI_STATUS_GLOBAL_UP); - } - - if (!get_ip_address()) - { - return NSAPI_ERROR_DHCP_FAILURE; - } - - return NSAPI_ERROR_OK; -} - -nsapi_error_t CC3220SFInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) -{ - if (!ssid) { - return NSAPI_ERROR_PARAMETER; - } - - if ((strlen(ssid) == 0) || (strlen(ssid) > 32)) { - return NSAPI_ERROR_PARAMETER; - } - - if ((security != NSAPI_SECURITY_NONE) && (strcmp(pass, "") == 0)) { - return NSAPI_ERROR_PARAMETER; - } - - switch (security) - { - case NSAPI_SECURITY_WPA: - case NSAPI_SECURITY_WPA2: - case NSAPI_SECURITY_WPA_WPA2: - case NSAPI_SECURITY_WEP: - if ((strlen(pass) < 8) || (strlen(pass) > 63)) { // 802.11 password 8-63 characters - return NSAPI_ERROR_PARAMETER; - } - break; - case NSAPI_SECURITY_NONE: - break; - default: - return NSAPI_ERROR_PARAMETER; - } - - if (security != NSAPI_SECURITY_NONE) - { - if(!pass) - { - return NSAPI_ERROR_PARAMETER; - } - } - - strncpy(_ssid, ssid, sizeof(_ssid)); - strncpy(_pass, pass, sizeof(_pass)); - _security = security; - - return NSAPI_ERROR_OK; -} - -nsapi_error_t CC3220SFInterface::set_channel(uint8_t channel) -{ - return NSAPI_ERROR_UNSUPPORTED; -} - -nsapi_error_t CC3220SFInterface::disconnect() -{ - nsapi_error_t status; - - _started = false; - _initialized = false; - - if (_cc3200_simplelink.disconnect()) - { - status = NSAPI_ERROR_OK; - _cc3200_simplelink.set_connection_status(NSAPI_STATUS_DISCONNECTED); - } - else - { - status = NSAPI_ERROR_DEVICE_ERROR; - } - return status; -} - -const char *CC3220SFInterface::get_ip_address() -{ - if(!_started) { - return NULL; - } - - const char *ip_buff = _cc3200_simplelink.getIPAddress(); - if(!ip_buff || std::strcmp(ip_buff, "0.0.0.0") == 0) { - return NULL; - } - - return ip_buff; -} - -const char *CC3220SFInterface::get_mac_address() -{ - return _cc3200_simplelink.getMACAddress(); -} - -const char *CC3220SFInterface::get_gateway() -{ - return _started ? _cc3200_simplelink.getGateway() : NULL; -} - -const char *CC3220SFInterface::get_netmask() -{ - return _started ? _cc3200_simplelink.getNetmask() : NULL; -} - -int8_t CC3220SFInterface::get_rssi() -{ - return _started ? _cc3200_simplelink.getRSSI() : 0; -} - -int CC3220SFInterface::scan(WiFiAccessPoint *res, unsigned count) -{ - nsapi_error_t status; - - status = _startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION); - if(status != NSAPI_ERROR_OK) { - return status; - } - - return _cc3200_simplelink.scan(res, count); -} - -nsapi_error_t CC3220SFInterface::_startup(const int8_t wifi_mode) -{ - if (!_started) { - if (!_cc3200_simplelink.startup(wifi_mode)) { - return NSAPI_ERROR_DEVICE_ERROR; - } - } - return NSAPI_ERROR_OK; -} - -void CC3220SFInterface::attach(mbed::Callback status_cb) -{ - _cc3200_simplelink.attach(status_cb); -} - -nsapi_connection_status_t CC3220SFInterface::get_connection_status() const -{ - return _cc3200_simplelink.get_connection_status(); -} - -nsapi_error_t CC3220SFInterface::socket_open(void **handle, nsapi_protocol_t proto) -{ - int32_t sd, i, ret = NSAPI_ERROR_PARAMETER; - - if (!handle) - { - return ret; - } - - _mutex.lock(); - for (i = 0; i < CC3220SF_SOCKET_COUNT; i++) { - if (_id_in_use[i] == false) - { - _id_in_use[i] = true; - break; - } - } - - if (i == CC3220SF_SOCKET_COUNT) { - _mutex.unlock(); - return NSAPI_ERROR_NO_SOCKET; - } - - struct cc3200_socket *socket = new struct cc3200_socket; - if (!socket) - { - _mutex.unlock(); - return NSAPI_ERROR_NO_SOCKET; - } - - sd = _cc3200_simplelink.open_socket(proto); - if (sd >= 0) // socket open succeeded - { - socket->id = i; - socket->sd = sd; - socket->proto = proto; - socket->connected = false; - socket->read_data_available = 0; - socket->data_to_read = 0; - socket->callback_pending = false; - *handle = socket; - _socket_obj[i] = (void *)socket; - ret = NSAPI_ERROR_OK; - } - else - { - delete socket; - *handle = NULL; - ret = NSAPI_ERROR_NO_SOCKET; - } - _mutex.unlock(); - return ret; -} - -nsapi_error_t CC3220SFInterface::socket_close(void *handle) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - int err = NSAPI_ERROR_OK; - - if (!socket) { - return NSAPI_ERROR_NO_SOCKET; - } - - _mutex.lock(); - if (!_cc3200_simplelink.close_socket(socket->sd)) - { - err = NSAPI_ERROR_DEVICE_ERROR; - } - socket->connected = false; - socket->callback_pending = false; - _id_in_use[socket->id] = false; - _socket_obj[socket->id] = 0; - _mutex.unlock(); - delete socket; - return err; -} - -#if 0 -nsapi_error_t CC3220SFInterface::gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version) -{ - nsapi_addr_t ip_address; - ip_address.version = NSAPI_IPv4; - if (_cc3200_simplelink.dns_lookup(name, (char*)ip_address.bytes, sizeof(ip_address.bytes), version) == NSAPI_ERROR_OK) - { - address->set_addr(ip_address); - return NSAPI_ERROR_OK; - } - else - { - return NSAPI_ERROR_DNS_FAILURE; - } -} -#endif - -nsapi_error_t CC3220SFInterface::get_dns_server(int index, SocketAddress *address, const char *interface_name) -{ - nsapi_addr_t dns_address; - dns_address.version = NSAPI_IPv4; - if (_cc3200_simplelink.getDNS(dns_address.bytes, sizeof(dns_address.bytes)) == NSAPI_ERROR_OK) - { - address->set_addr(dns_address); - return NSAPI_ERROR_OK; - } - else - { - return NSAPI_ERROR_DNS_FAILURE; - } -} - -nsapi_error_t CC3220SFInterface::setsockopt(nsapi_socket_t handle, int level, - int optname, const void *optval, unsigned optlen) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (!socket) - { - return NSAPI_ERROR_NO_SOCKET; - } - _mutex.lock(); - nsapi_error_t retcode = _cc3200_simplelink.setsockopt(socket->sd, level, optname, optval, optlen); - _mutex.unlock(); - return retcode; -} - -nsapi_error_t CC3220SFInterface::getsockopt(nsapi_socket_t handle, int level, int optname, - void *optval, unsigned *optlen) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (!socket) - { - return NSAPI_ERROR_NO_SOCKET; - } - _mutex.lock(); - nsapi_error_t retcode = _cc3200_simplelink.getsockopt(socket->sd, level, optname, optval, optlen); - _mutex.unlock(); - - return retcode; -} - -int CC3220SFInterface::socket_bind(void *handle, const SocketAddress &address) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (!socket) - { - return NSAPI_ERROR_NO_SOCKET; - } - - _mutex.lock(); - - int ret = _cc3200_simplelink.bind_socket(socket->sd, address); - _mutex.unlock(); - return ret; -} - -int CC3220SFInterface::socket_listen(void *handle, int backlog) -{ - return NSAPI_ERROR_UNSUPPORTED; -} - -int CC3220SFInterface::socket_connect(void *handle, const SocketAddress &addr) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (!socket) - { - return NSAPI_ERROR_NO_SOCKET; - } - _mutex.lock(); - - int ret; - if (_cc3200_simplelink.connect_socket(socket->sd, addr) == NSAPI_ERROR_OK) - { - socket->connected= true; - ret = NSAPI_ERROR_OK; - } - else - { - printf("socket_connect failed\n"); - ret = NSAPI_ERROR_DEVICE_ERROR; - } - _mutex.unlock(); - return ret; -} - -int CC3220SFInterface::socket_accept(void *handle, void **socket, SocketAddress *address) -{ - // TODO - return NSAPI_ERROR_UNSUPPORTED; -} - -int CC3220SFInterface::socket_send(void *handle, const void *data, unsigned size) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (!socket) - { - return NSAPI_ERROR_NO_SOCKET; - } - _mutex.lock(); - int ret = _cc3200_simplelink.send(socket->sd, data, size); - if (ret > 0) - { - socket->callback_pending = true; - } - _mutex.unlock(); - - return ret; -} - -int CC3220SFInterface::socket_recv(void *handle, void *data, unsigned size) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (!socket) - { - return NSAPI_ERROR_NO_SOCKET; - } - _mutex.lock(); - socket->data_to_read = size; - int ret = _socket_receive_data(socket, data); - _mutex.unlock(); - - return ret; -} - -int CC3220SFInterface::socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned size) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (!socket) - { - return NSAPI_ERROR_NO_SOCKET; - } - - _mutex.lock(); - // Sending a datagram of length 0 is OK - int ret = _cc3200_simplelink.sendto_socket(socket->sd, data, size, address); - - if (ret >= 0) - { - socket->callback_pending = true; - } - _mutex.unlock(); - - return ret; -} - -int CC3220SFInterface::socket_recvfrom(void *handle, SocketAddress *address, void *buffer, unsigned size) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (!socket) - { - return NSAPI_ERROR_NO_SOCKET; - } - - _mutex.lock(); - // It's okay to receive 0 for a datagram protocol. Unlike TCP, it doesn't mean the peer has closed the connection. - socket->data_to_read = size; - int ret = _socket_receive_data(socket, buffer); - if (ret >= 0 && address) - { - *address = socket->addr; - } - _mutex.unlock(); - - return ret; -} - -void CC3220SFInterface::socket_attach(void *handle, void (*callback)(void *), void *data) -{ - struct cc3200_socket *socket = (struct cc3200_socket *)handle; - if (socket) - { - _mutex.lock(); - _cbs[socket->id].callback = callback; - _cbs[socket->id].data = data; - _mutex.unlock(); - } -} - -void CC3220SFInterface::_socket_background_thread() -{ - while (1) - { - for (int i = 0; i < CC3220SF_SOCKET_COUNT; i++) - { - _mutex.lock(); - if (_socket_obj[i]) - { - struct cc3200_socket *socket = (struct cc3200_socket *)_socket_obj[i]; - /* Check if an async event needs to be sent*/ - if ((socket->callback_pending) && _cbs[socket->id].callback) - { - _cbs[socket->id].callback(_cbs[socket->id].data); - socket->callback_pending = false; - } - /* Check if there is something to read for this socket. But if it */ - /* has already been read : don't read again */ - if ((socket->read_data_available == 0) && (socket->data_to_read) && _cbs[socket->id].callback) - { - int read_amount, bytes_to_receive = socket->data_to_read; - if (bytes_to_receive > MAX_RECV_PACKET_SIZE) - { - bytes_to_receive = MAX_RECV_PACKET_SIZE; - } - if (socket->proto == NSAPI_UDP) - { - read_amount = _cc3200_simplelink.recvfrom(socket->sd, socket->read_data_internal_buffer, bytes_to_receive, socket->addr); - } - else - { - read_amount= _cc3200_simplelink.recv(socket->sd, socket->read_data_internal_buffer, bytes_to_receive); - } - //printf("background receive %d %d\n", bytes_to_receive, read_amount); - if (read_amount > 0) - { - socket->read_data_available = read_amount; - // For UDP packet, no packet fragmentation, so none or all - if (socket->proto == NSAPI_UDP) - { - socket->data_to_read = 0; - } - else - { - socket->data_to_read -= read_amount; - } - } - else if ((read_amount < 0 && read_amount != NSAPI_ERROR_WOULD_BLOCK) || (read_amount == 0)) - { - /* Mark connection has been lost or closed */ - printf("Connection lost\n"); - socket->connected = false; - socket->data_to_read = 0; - } - - if (read_amount >= 0) - { - /* There is something to read in this socket*/ - _cbs[socket->id].callback(_cbs[socket->id].data); - } - } - } - _mutex.unlock(); - } - ThisThread::sleep_for(READ_THREAD_SLEEP_MS); - } -} - -// This function is expected to run with mutex protection -int CC3220SFInterface::_socket_receive_data(void *obj, void *data) -{ - int recv = 0; - char *ptr = (char *)data; - int bytes_to_receive = 0; - - cc3200_socket *socket = (cc3200_socket *)obj; - - if (socket->read_data_available == 0) - { - // Need to receive - int read_amount; - - // Simplelink can receive up to MAX_RECV_PACKET_SIZE - bytes_to_receive = socket->data_to_read; - if (bytes_to_receive > MAX_RECV_PACKET_SIZE) - { - bytes_to_receive = MAX_RECV_PACKET_SIZE; - } - if (socket->proto == NSAPI_UDP) // TODO: is this good enough to distinguish recvfrom and recv? - { - read_amount = _cc3200_simplelink.recvfrom(socket->sd, socket->read_data_internal_buffer, bytes_to_receive, socket->addr); - } - else - { - read_amount= _cc3200_simplelink.recv(socket->sd, socket->read_data_internal_buffer, bytes_to_receive); - } - //printf("foreground receive %d %d\n", bytes_to_receive, read_amount); - if (read_amount == 0) - { - // No data to read - socket->data_to_read = 0; - return 0; - } - if (read_amount > 0) - { - socket->read_data_available = read_amount; - } - else // read_amount < 0 - { - if (read_amount == NSAPI_ERROR_WOULD_BLOCK) - { - return NSAPI_ERROR_WOULD_BLOCK; - } - else - { - socket->connected = false; - printf("connection lost\n"); - socket->data_to_read = 0; - return NSAPI_ERROR_CONNECTION_LOST; - } - } - } - if (socket->read_data_available > 0) - { - // Data has been received or there's already data waiting to be copied into the buffer provided - uint32_t i = 0; - while (i < socket->read_data_available) - { - *ptr++ = socket->read_data_internal_buffer[i]; - i++; - } - recv += i; - - /* All the stored data has been read, reset buffer */ - memset(socket->read_data_internal_buffer, 0, sizeof(socket->read_data_internal_buffer)); - // For UDP packet, no packet fragmentation, so none or all - if (socket->proto == NSAPI_UDP) - { - socket->data_to_read = 0; - } - else - { - socket->data_to_read -= socket->read_data_available; - } - socket->read_data_available = 0; - } - return recv; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.h deleted file mode 100644 index 8b14a9231e6..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.h +++ /dev/null @@ -1,373 +0,0 @@ -/* CC3220 implementation of NetworkInterfaceAPI - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef CC3220SF_INTERFACE_H -#define CC3220SF_INTERFACE_H - -#include "mbed.h" -#include "cc3200_simplelink.h" - -#define CC3220SF_SOCKET_COUNT (MAX_CONCURRENT_ACTIONS) -#define MAX_RECV_PACKET_SIZE (1544) - -/** TI (CC3220SF) interface class - * Implementation of the NetworkStack for TI CC3200 Simplelink stack - */ -class CC3220SFInterface: public NetworkStack, public WiFiInterface -{ -public: - /** - * @brief CC3220SFInterface default constructor - */ - - CC3220SFInterface(); - - /** Start the interface - * @return 0 on success, negative on failure - */ - virtual nsapi_error_t connect(); - - /** Start the interface - * - * Attempts to connect to a WiFi network. - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) - * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t connect(const char *ssid, const char *pass, - nsapi_security_t security = NSAPI_SECURITY_NONE, - uint8_t channel = 0); - - /** Set the WiFi network credentials - * - * @param ssid Name of the network to connect to - * @param pass Security passphrase to connect to the network - * @param security Type of encryption for connection - * (defaults to NSAPI_SECURITY_NONE) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); - - /** Set the WiFi network channel - * - * - * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) - * @return 0 on success, or error code on failure - */ - virtual nsapi_error_t set_channel(uint8_t channel); - - /** Stop the interface - * @return 0 on success, negative on failure - */ - virtual int disconnect(); - - /** Set a static IP address - * - * Configures this network interface to use a static IP address. - * Implicitly disables DHCP, which can be enabled in set_dhcp. - * Requires that the network is disconnected. - * - * @param address Null-terminated representation of the local IP address - * @param netmask Null-terminated representation of the local network mask - * @param gateway Null-terminated representation of the local gateway - * @return 0 on success, negative error code on failure - */ - //virtual nsapi_error_t set_network(const char *ip_address, const char *netmask, const char *gateway); - - /** Enable or disable DHCP on the network - * - * Requires that the network is disconnected - * - * @param dhcp False to disable dhcp (defaults to enabled) - * @return 0 on success, negative error code on failure - */ - //virtual nsapi_error_t set_dhcp(bool dhcp); - - /** Get the internally stored IP address - * @return IP address of the interface or null if not yet connected - */ - virtual const char *get_ip_address(); - - /** Get the internally stored MAC address - * @return MAC address of the interface - */ - virtual const char *get_mac_address(); - - /** Get the local gateway - * - * @return Null-terminated representation of the local gateway - * or null if no network mask has been recieved - */ - virtual const char *get_gateway(); - - /** Get the local network mask - * - * @return Null-terminated representation of the local network mask - * or null if no network mask has been recieved - */ - virtual const char *get_netmask(); - - /** Gets the current radio signal strength for active connection - * - * @return Connection strength in dBm (negative value) - */ - virtual int8_t get_rssi(); - - /** Scan for available networks - * - * The scan will - * If the network interface is set to non-blocking mode, scan will attempt to scan - * for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback - * is attached, the callback will be called when the operation has completed. - * @param res Pointer to allocated array to store discovered AP - * @param count Size of allocated @a res array, or 0 to only count available AP - * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error - * see @a nsapi_error - */ - virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, unsigned count); - - - /** Translates a hostname to an IP address with specific version - * - * The hostname may be either a domain name or an IP address. If the - * hostname is an IP address, no network transactions will be performed. - * - * If no stack-specific DNS resolution is provided, the hostname - * will be resolve using a UDP socket on the stack. - * - * @param address Destination for the host SocketAddress - * @param host Hostname to resolve - * @param version IP version of address to resolve, NSAPI_UNSPEC indicates - * version is chosen by the stack (defaults to NSAPI_UNSPEC) - * @return 0 on success, negative error code on failure - */ - using NetworkInterface::gethostbyname; - //virtual nsapi_error_t gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version); - - /** Add a domain name server to list of servers to query - * - * @param addr Destination for the host address - * @return 0 on success, negative error code on failure - */ - using NetworkInterface::add_dns_server; - - virtual nsapi_error_t get_dns_server(int index, SocketAddress *address, const char* interface_name = NULL); - - /** Set socket options - * - * The setsockopt allow an application to pass stack-specific hints - * to the underlying stack. For unsupported options, - * NSAPI_ERROR_UNSUPPORTED is returned and the socket is unmodified. - * - * @param handle Socket handle - * @param level Stack-specific protocol level - * @param optname Stack-specific option identifier - * @param optval Option value - * @param optlen Length of the option value - * @return 0 on success, negative error code on failure - */ - virtual nsapi_error_t setsockopt(nsapi_socket_t handle, int level, - int optname, const void *optval, unsigned optlen); - - /** Get socket options - * - * getsockopt allows an application to retrieve stack-specific options - * from the underlying stack using stack-specific level and option names, - * or to request generic options using levels from nsapi_socket_level_t. - * - * For unsupported options, NSAPI_ERROR_UNSUPPORTED is returned - * and the socket is unmodified. - * - * @param level Stack-specific protocol level or nsapi_socket_level_t - * @param optname Level-specific option name - * @param optval Destination for option value - * @param optlen Length of the option value - * @return 0 on success, negative error code on failure - */ - virtual nsapi_error_t getsockopt(nsapi_socket_t handle, int level, int optname, - void *optval, unsigned *optlen); - - /** Register callback for status reporting - * - * The specified status callback function will be called on status changes - * on the network. The parameters on the callback are the event type and - * event-type dependent reason parameter. - * - * @param status_cb The callback for status changes - */ - virtual void attach(mbed::Callback status_cb); - - /** Get the connection status - * - * @return The connection status according to ConnectionStatusType - */ - virtual nsapi_connection_status_t get_connection_status() const; - -protected: - /** Open a socket - * @param handle Handle in which to store new socket - * @param proto Type of socket to open, NSAPI_TCP or NSAPI_UDP - * @return 0 on success, negative on failure - */ - virtual int socket_open(void **handle, nsapi_protocol_t proto); - - /** Close the socket - * @param handle Socket handle - * @return 0 on success, negative on failure - * @note On failure, any memory associated with the socket must still - * be cleaned up - */ - virtual int socket_close(void *handle); - - /** Bind a server socket to a specific port - * @param handle Socket handle - * @param address Local address to listen for incoming connections on - * @return 0 on success, negative on failure. - */ - virtual int socket_bind(void *handle, const SocketAddress &address); - - /** Start listening for incoming connections - * @param handle Socket handle - * @param backlog Number of pending connections that can be queued up at any - * one time [Default: 1] - * @return 0 on success, negative on failure - */ - virtual int socket_listen(void *handle, int backlog); - - /** Connects this TCP socket to the server - * @param handle Socket handle - * @param address SocketAddress to connect to - * @return 0 on success, negative on failure - */ - virtual int socket_connect(void *handle, const SocketAddress &address); - - /** Accept a new connection. - * @param handle Handle in which to store new socket - * @param server Socket handle to server to accept from - * @return 0 on success, negative on failure - * @note This call is not-blocking, if this call would block, must - * immediately return NSAPI_ERROR_WOULD_WAIT - */ - virtual int socket_accept(void *handle, void **socket, SocketAddress *address); - - /** Send data to the remote host - * @param handle Socket handle - * @param data The buffer to send to the host - * @param size The length of the buffer to send - * @return Number of written bytes on success, negative on failure - * @note This call is not-blocking, if this call would block, must - * immediately return NSAPI_ERROR_WOULD_WAIT - */ - virtual int socket_send(void *handle, const void *data, unsigned size); - - /** Receive data from the remote host - * @param handle Socket handle - * @param data The buffer in which to store the data received from the host - * @param size The maximum length of the buffer - * @return Number of received bytes on success, negative on failure - * @note This call is not-blocking, if this call would block, must - * immediately return NSAPI_ERROR_WOULD_WAIT - */ - virtual int socket_recv(void *handle, void *data, unsigned size); - - /** Send a packet to a remote endpoint - * @param handle Socket handle - * @param address The remote SocketAddress - * @param data The packet to be sent - * @param size The length of the packet to be sent - * @return The number of written bytes on success, negative on failure - * @note This call is not-blocking, if this call would block, must - * immediately return NSAPI_ERROR_WOULD_WAIT - */ - virtual int socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned size); - - /** Receive a packet from a remote endpoint - * @param handle Socket handle - * @param address Destination for the remote SocketAddress or null - * @param buffer The buffer for storing the incoming packet data - * If a packet is too long to fit in the supplied buffer, - * excess bytes are discarded - * @param size The length of the buffer - * @return The number of received bytes on success, negative on failure - * @note This call is not-blocking, if this call would block, must - * immediately return NSAPI_ERROR_WOULD_WAIT - */ - virtual int socket_recvfrom(void *handle, SocketAddress *address, void *buffer, unsigned size); - - /** Register a callback on state change of the socket - * @param handle Socket handle - * @param callback Function to call on state change - * @param data Argument to pass to callback - * @note Callback may be called in an interrupt context. - */ - virtual void socket_attach(void *handle, void (*callback)(void *), void *data); - - /** Provide access to the NetworkStack object - * - * @return The underlying NetworkStack object - */ - virtual NetworkStack *get_stack() - { - return this; - } - -private: - static const int CC3220SF_SSID_MAX_LENGTH = 32; /* 32 is what 802.11 defines as longest possible name */ - static const int CC3220SF_PASSPHRASE_MAX_LENGTH = 63; /* The longest allowed passphrase */ - static const int CC3220SF_PASSPHRASE_MIN_LENGTH = 8; /* The shortest allowed passphrase */ - - struct { - void (*callback)(void *); - void *data; - } _cbs[CC3220SF_SOCKET_COUNT]; - - struct cc3200_socket { - int id; - int sd; - nsapi_protocol_t proto; - volatile bool connected; - char read_data_internal_buffer[MAX_RECV_PACKET_SIZE]; - volatile uint32_t read_data_available; - uint32_t data_to_read; - bool callback_pending; - SocketAddress addr; - }; - bool _id_in_use[CC3220SF_SOCKET_COUNT]; - void * _socket_obj[CC3220SF_SOCKET_COUNT]; // store addresses of socket handles - Mutex _mutex; - Thread _thread_read_socket; - CC3200_SIMPLELINK _cc3200_simplelink; - int _initialized; - int _started; - char _ssid[CC3220SF_SSID_MAX_LENGTH + 1]; /* 32 is what 802.11 defines as longest possible name; +1 for the \0 */ - nsapi_security_t _security; - uint8_t _channel; - char _pass[CC3220SF_PASSPHRASE_MAX_LENGTH + 1]; - - void _socket_background_thread(); - int _socket_receive_data(void *obj, void *data); - nsapi_error_t _init(void); - nsapi_error_t _startup(const int8_t wifi_mode); - Semaphore _connect_sem; - Semaphore _ip_set_sem; - static CC3220SFInterface * cc3200sf_wifi_instance; - friend void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent); - friend void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent); -}; -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/CC3220SF.sct b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/CC3220SF.sct deleted file mode 100644 index f015722ed09..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/CC3220SF.sct +++ /dev/null @@ -1,104 +0,0 @@ -#! armcc -E - -/* Device specific values */ -#define ROM_START 0x01000000 -#define ROM_SIZE 0x100000 -#define FLASH_HDR_START ROM_START -#define FLASH_HDR_SIZE 0x800 -#define RAM_START 0x20000000 -#define RAM_SIZE 0x40000 -#define VECTORS 195 /* This value must match NVIC_NUM_VECTORS */ - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((VECTORS * 4) + 7) & ~7) - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -#if defined(MBED_APP_START) - /* - * There're two cases if MBED_APP_START is defined. - * Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build. - * In this build, include FLASH_HDR region. - */ - #define FLASH_HDR_INCLUDED 1 - - #if MBED_APP_START == ROM_START - #if defined(MBED_APP_SIZE) - #define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE) - #define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE) - #endif - #else - /* - * Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build. - * In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area - */ - #undef FLASH_HDR_INCLUDED - #define FLASH_HDR_INCLUDED 0 - #define ROM_EXEC_START MBED_APP_START - #if defined(MBED_APP_SIZE) - #define ROM_EXEC_SIZE MBED_APP_SIZE - #else - #define ROM_EXEC_SIZE (ROM_SIZE- (MBED_APP_START - ROM_START)) - #endif - #endif -#else - /* - * MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader. - * In this build, include FLASH_HDR region - */ - #define FLASH_HDR_INCLUDED 1 - #define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE) - #if defined(MBED_APP_SIZE) - #define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE) - #else - #define ROM_EXEC_SIZE (ROM_SIZE - FLASH_HDR_SIZE) - #endif -#endif - - -#if FLASH_HDR_INCLUDED == 1 -;#warning include cookie -LR_IROM1 ROM_START ROM_SIZE { - - ER_FLASH FLASH_HDR_START FLASH_HDR_SIZE { - *(signature_section, +Last) - } - - ER_IROM1 ROM_EXEC_START FIXED { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ;RW_IRAM1 (RAM_START + VECTORS_SIZE) (RAM_SIZE - VECTORS_SIZE) { ; RW data - RW_IRAM1 (0x20000000+0x308) (0x00040000-0x308) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -Stack_Size { ; stack - } -} -#else -;#warning exclude cookie -LR_IROM1 ROM_EXEC_START ROM_EXEC_SIZE { - - ER_IROM1 ROM_EXEC_START ROM_EXEC_SIZE { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ;RW_IRAM1 (RAM_START + VECTORS_SIZE) (RAM_SIZE - VECTORS_SIZE) { ; RW data - RW_IRAM1 (0x20000000+0x308) (0x00040000-0x308) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_STACK (RAM_START + RAM_SIZE) EMPTY -Stack_Size { ; stack - } -} -#endif - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/startup_CC3220SF.S b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/startup_CC3220SF.S deleted file mode 100644 index 18a1d833b38..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/startup_CC3220SF.S +++ /dev/null @@ -1,369 +0,0 @@ -;/* -; * Copyright (c) 2018-2019 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT_GPIOA0_IRQHandler ; /* 16 */ - DCD INT_GPIOA1_IRQHandler ; /* 17 */ - DCD INT_GPIOA2_IRQHandler ; /* 18 */ - DCD INT_GPIOA3_IRQHandler ; /* 19 */ - DCD 0 ; /* 20 Reserved interrupt */ - DCD INT_UARTA0_IRQHandler ; /* 21 */ - DCD INT_UARTA1_IRQHandler ; /* 22 */ - DCD 0 ; /* 23 Reserved interrupt */ - DCD INT_I2CA0_IRQHandler ; /* 24 */ - DCD 0 ; /* 25 Reserved interrupt */ - DCD 0 ; /* 26 Reserved interrupt */ - DCD 0 ; /* 27 Reserved interrupt */ - DCD 0 ; /* 28 Reserved interrupt */ - DCD 0 ; /* 29 Reserved interrupt */ - DCD INT_ADCCH0_IRQHandler ; /* 30 */ - DCD INT_ADCCH1_IRQHandler ; /* 31 */ - DCD INT_ADCCH2_IRQHandler ; /* 32 */ - DCD INT_ADCCH3_IRQHandler ; /* 33 */ - DCD INT_WDT_IRQHandler ; /* 34 */ - DCD INT_TIMERA0A_IRQHandler ; /* 35 */ - DCD INT_TIMERA0B_IRQHandler ; /* 36 */ - DCD INT_TIMERA1A_IRQHandler ; /* 37 */ - DCD INT_TIMERA1B_IRQHandler ; /* 38 */ - DCD INT_TIMERA2A_IRQHandler ; /* 39 */ - DCD INT_TIMERA2B_IRQHandler ; /* 40 */ - DCD 0 ; /* 41 Reserved interrupt */ - DCD 0 ; /* 42 Reserved interrupt */ - DCD 0 ; /* 43 Reserved interrupt */ - DCD 0 ; /* 44 Reserved interrupt */ - DCD INT_FLASH_IRQHandler ; /* 45 */ - DCD 0 ; /* 46 Reserved interrupt */ - DCD 0 ; /* 47 Reserved interrupt */ - DCD 0 ; /* 48 Reserved interrupt */ - DCD 0 ; /* 49 Reserved interrupt */ - DCD 0 ; /* 50 Reserved interrupt */ - DCD INT_TIMERA3A_IRQHandler ; /* 51 */ - DCD INT_TIMERA3B_IRQHandler ; /* 52 */ - DCD 0 ; /* 53 Reserved interrupt */ - DCD 0 ; /* 54 Reserved interrupt */ - DCD 0 ; /* 55 Reserved interrupt */ - DCD 0 ; /* 56 Reserved interrupt */ - DCD 0 ; /* 57 Reserved interrupt */ - DCD 0 ; /* 58 Reserved interrupt */ - DCD 0 ; /* 59 Reserved interrupt */ - DCD 0 ; /* 60 Reserved interrupt */ - DCD 0 ; /* 61 Reserved interrupt */ - DCD INT_UDMA_IRQHandler ; /* 62 */ - DCD INT_UDMAERR_IRQHandler ; /* 63 */ - DCD 0 ; /* 64 Reserved interrupt */ - DCD 0 ; /* 65 Reserved interrupt */ - DCD 0 ; /* 66 Reserved interrupt */ - DCD 0 ; /* 67 Reserved interrupt */ - DCD 0 ; /* 68 Reserved interrupt */ - DCD 0 ; /* 69 Reserved interrupt */ - DCD 0 ; /* 70 Reserved interrupt */ - DCD 0 ; /* 71 Reserved interrupt */ - DCD 0 ; /* 72 Reserved interrupt */ - DCD 0 ; /* 73 Reserved interrupt */ - DCD 0 ; /* 74 Reserved interrupt */ - DCD 0 ; /* 75 Reserved interrupt */ - DCD 0 ; /* 76 Reserved interrupt */ - DCD 0 ; /* 77 Reserved interrupt */ - DCD 0 ; /* 78 Reserved interrupt */ - DCD 0 ; /* 79 Reserved interrupt */ - DCD 0 ; /* 80 Reserved interrupt */ - DCD 0 ; /* 81 Reserved interrupt */ - DCD 0 ; /* 82 Reserved interrupt */ - DCD 0 ; /* 83 Reserved interrupt */ - DCD 0 ; /* 84 Reserved interrupt */ - DCD 0 ; /* 85 Reserved interrupt */ - DCD 0 ; /* 86 Reserved interrupt */ - DCD 0 ; /* 87 Reserved interrupt */ - DCD 0 ; /* 88 Reserved interrupt */ - DCD 0 ; /* 89 Reserved interrupt */ - DCD 0 ; /* 90 Reserved interrupt */ - DCD 0 ; /* 91 Reserved interrupt */ - DCD 0 ; /* 92 Reserved interrupt */ - DCD 0 ; /* 93 Reserved interrupt */ - DCD 0 ; /* 94 Reserved interrupt */ - DCD 0 ; /* 95 Reserved interrupt */ - DCD 0 ; /* 96 Reserved interrupt */ - DCD 0 ; /* 97 Reserved interrupt */ - DCD 0 ; /* 98 Reserved interrupt */ - DCD 0 ; /* 99 Reserved interrupt */ - DCD 0 ; /* 100 Reserved interrupt */ - DCD 0 ; /* 101 Reserved interrupt */ - DCD 0 ; /* 102 Reserved interrupt */ - DCD 0 ; /* 103 Reserved interrupt */ - DCD 0 ; /* 104 Reserved interrupt */ - DCD 0 ; /* 105 Reserved interrupt */ - DCD 0 ; /* 106 Reserved interrupt */ - DCD 0 ; /* 107 Reserved interrupt */ - DCD 0 ; /* 108 Reserved interrupt */ - DCD 0 ; /* 109 Reserved interrupt */ - DCD 0 ; /* 110 Reserved interrupt */ - DCD 0 ; /* 111 Reserved interrupt */ - DCD 0 ; /* 112 Reserved interrupt */ - DCD 0 ; /* 113 Reserved interrupt */ - DCD 0 ; /* 114 Reserved interrupt */ - DCD 0 ; /* 115 Reserved interrupt */ - DCD 0 ; /* 116 Reserved interrupt */ - DCD 0 ; /* 117 Reserved interrupt */ - DCD 0 ; /* 118 Reserved interrupt */ - DCD 0 ; /* 119 Reserved interrupt */ - DCD 0 ; /* 120 Reserved interrupt */ - DCD 0 ; /* 121 Reserved interrupt */ - DCD 0 ; /* 122 Reserved interrupt */ - DCD 0 ; /* 123 Reserved interrupt */ - DCD 0 ; /* 124 Reserved interrupt */ - DCD 0 ; /* 125 Reserved interrupt */ - DCD 0 ; /* 126 Reserved interrupt */ - DCD 0 ; /* 127 Reserved interrupt */ - DCD 0 ; /* 128 Reserved interrupt */ - DCD 0 ; /* 129 Reserved interrupt */ - DCD 0 ; /* 130 Reserved interrupt */ - DCD 0 ; /* 131 Reserved interrupt */ - DCD 0 ; /* 132 Reserved interrupt */ - DCD 0 ; /* 133 Reserved interrupt */ - DCD 0 ; /* 134 Reserved interrupt */ - DCD 0 ; /* 135 Reserved interrupt */ - DCD 0 ; /* 136 Reserved interrupt */ - DCD 0 ; /* 137 Reserved interrupt */ - DCD 0 ; /* 138 Reserved interrupt */ - DCD 0 ; /* 139 Reserved interrupt */ - DCD 0 ; /* 140 Reserved interrupt */ - DCD 0 ; /* 141 Reserved interrupt */ - DCD 0 ; /* 142 Reserved interrupt */ - DCD 0 ; /* 143 Reserved interrupt */ - DCD 0 ; /* 144 Reserved interrupt */ - DCD 0 ; /* 145 Reserved interrupt */ - DCD 0 ; /* 146 Reserved interrupt */ - DCD 0 ; /* 147 Reserved interrupt */ - DCD 0 ; /* 148 Reserved interrupt */ - DCD 0 ; /* 149 Reserved interrupt */ - DCD 0 ; /* 150 Reserved interrupt */ - DCD 0 ; /* 151 Reserved interrupt */ - DCD 0 ; /* 152 Reserved interrupt */ - DCD 0 ; /* 153 Reserved interrupt */ - DCD 0 ; /* 154 Reserved interrupt */ - DCD 0 ; /* 155 Reserved interrupt */ - DCD 0 ; /* 156 Reserved interrupt */ - DCD 0 ; /* 157 Reserved interrupt */ - DCD 0 ; /* 158 Reserved interrupt */ - DCD 0 ; /* 159 Reserved interrupt */ - DCD 0 ; /* 160 Reserved interrupt */ - DCD 0 ; /* 161 Reserved interrupt */ - DCD 0 ; /* 162 Reserved interrupt */ - DCD 0 ; /* 163 Reserved interrupt */ - DCD INT_SHA_IRQHandler ; /* 164 */ - DCD 0 ; /* 165 Reserved interrupt */ - DCD 0 ; /* 166 Reserved interrupt */ - DCD INT_AES_IRQHandler ; /* 167 */ - DCD 0 ; /* 168 Reserved interrupt */ - DCD INT_DES_IRQHandler ; /* 169 */ - DCD 0 ; /* 170 Reserved interrupt */ - DCD 0 ; /* 171 Reserved interrupt */ - DCD 0 ; /* 172 Reserved interrupt */ - DCD 0 ; /* 173 Reserved interrupt */ - DCD 0 ; /* 174 Reserved interrupt */ - DCD INT_MMCHS_IRQHandler ; /* 175 */ - DCD 0 ; /* 176 Reserved interrupt */ - DCD INT_I2S_IRQHandler ; /* 177 */ - DCD 0 ; /* 178 Reserved interrupt */ - DCD INT_CAMERA_IRQHandler ; /* 179 */ - DCD 0 ; /* 180 Reserved interrupt */ - DCD 0 ; /* 181 Reserved interrupt */ - DCD 0 ; /* 182 Reserved interrupt */ - DCD 0 ; /* 183 Reserved interrupt */ - DCD 0 ; /* 184 Reserved interrupt */ - DCD 0 ; /* 185 Reserved interrupt */ - DCD 0 ; /* 186 Reserved interrupt */ - DCD INT_NWPIC_IRQHandler ; /* 187 */ - DCD INT_PRCM_IRQHandler ; /* 188 */ - DCD 0 ; /* 189 Reserved interrupt */ - DCD 0 ; /* 190 Reserved interrupt */ - DCD INT_SSPI_IRQHandler ; /* 191 */ - DCD INT_GSPI_IRQHandler ; /* 192 */ - DCD INT_LSPI_IRQHandler ; /* 193 */ - DCD 0 ; /* 194 Reserved interrupt */ - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT INT_GPIOA0_IRQHandler [WEAK] - EXPORT INT_GPIOA1_IRQHandler [WEAK] - EXPORT INT_GPIOA2_IRQHandler [WEAK] - EXPORT INT_GPIOA3_IRQHandler [WEAK] - EXPORT INT_UARTA0_IRQHandler [WEAK] - EXPORT INT_UARTA1_IRQHandler [WEAK] - EXPORT INT_I2CA0_IRQHandler [WEAK] - EXPORT INT_ADCCH0_IRQHandler [WEAK] - EXPORT INT_ADCCH1_IRQHandler [WEAK] - EXPORT INT_ADCCH2_IRQHandler [WEAK] - EXPORT INT_ADCCH3_IRQHandler [WEAK] - EXPORT INT_WDT_IRQHandler [WEAK] - EXPORT INT_TIMERA0A_IRQHandler [WEAK] - EXPORT INT_TIMERA0B_IRQHandler [WEAK] - EXPORT INT_TIMERA1A_IRQHandler [WEAK] - EXPORT INT_TIMERA1B_IRQHandler [WEAK] - EXPORT INT_TIMERA2A_IRQHandler [WEAK] - EXPORT INT_TIMERA2B_IRQHandler [WEAK] - EXPORT INT_FLASH_IRQHandler [WEAK] - EXPORT INT_TIMERA3A_IRQHandler [WEAK] - EXPORT INT_TIMERA3B_IRQHandler [WEAK] - EXPORT INT_UDMA_IRQHandler [WEAK] - EXPORT INT_UDMAERR_IRQHandler [WEAK] - EXPORT INT_SHA_IRQHandler [WEAK] - EXPORT INT_AES_IRQHandler [WEAK] - EXPORT INT_DES_IRQHandler [WEAK] - EXPORT INT_MMCHS_IRQHandler [WEAK] - EXPORT INT_I2S_IRQHandler [WEAK] - EXPORT INT_CAMERA_IRQHandler [WEAK] - EXPORT INT_NWPIC_IRQHandler [WEAK] - EXPORT INT_PRCM_IRQHandler [WEAK] - EXPORT INT_SSPI_IRQHandler [WEAK] - EXPORT INT_GSPI_IRQHandler [WEAK] - EXPORT INT_LSPI_IRQHandler [WEAK] - -INT_GPIOA0_IRQHandler -INT_GPIOA1_IRQHandler -INT_GPIOA2_IRQHandler -INT_GPIOA3_IRQHandler -INT_UARTA0_IRQHandler -INT_UARTA1_IRQHandler -INT_I2CA0_IRQHandler -INT_ADCCH0_IRQHandler -INT_ADCCH1_IRQHandler -INT_ADCCH2_IRQHandler -INT_ADCCH3_IRQHandler -INT_WDT_IRQHandler -INT_TIMERA0A_IRQHandler -INT_TIMERA0B_IRQHandler -INT_TIMERA1A_IRQHandler -INT_TIMERA1B_IRQHandler -INT_TIMERA2A_IRQHandler -INT_TIMERA2B_IRQHandler -INT_FLASH_IRQHandler -INT_TIMERA3A_IRQHandler -INT_TIMERA3B_IRQHandler -INT_UDMA_IRQHandler -INT_UDMAERR_IRQHandler -INT_SHA_IRQHandler -INT_AES_IRQHandler -INT_DES_IRQHandler -INT_MMCHS_IRQHandler -INT_I2S_IRQHandler -INT_CAMERA_IRQHandler -INT_NWPIC_IRQHandler -INT_PRCM_IRQHandler -INT_SSPI_IRQHandler -INT_GSPI_IRQHandler -INT_LSPI_IRQHandler - - B . - - ENDP - - ALIGN - - END diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/gcc_arm.ld b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/gcc_arm.ld deleted file mode 100644 index 25fa6835c35..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/gcc_arm.ld +++ /dev/null @@ -1,218 +0,0 @@ -/* Device specific values */ - -#define ROM_START 0x01000000 -#define ROM_SIZE 0x100000 -#define FLASH_HDR_START ROM_START -#define FLASH_HDR_SIZE 0x800 -#define RAM_START 0x20000000 -#define RAM_SIZE 0x40000 -#define VECTORS 195 /* This value must match NVIC_NUM_VECTORS */ - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((VECTORS * 4) + 7) & 0xFFFFFFF8) - -#if defined(MBED_APP_START) - /* - * There're two cases if MBED_APP_START is defined. - * Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build. - * In this build, include FLASH_HDR region. - */ - #define FLASH_HDR_INCLUDED 1 - - #if MBED_APP_START == ROM_START - #if defined(MBED_APP_SIZE) - #define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE) - #define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE) - #endif - #else - /* - * Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build. - * In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area - */ - #undef FLASH_HDR_INCLUDED - #define FLASH_HDR_INCLUDED 0 - #define ROM_EXEC_START MBED_APP_START - #if defined(MBED_APP_SIZE) - #define ROM_EXEC_SIZE MBED_APP_SIZE - #else - #define ROM_EXEC_SIZE (ROM_SIZE- (MBED_APP_START - ROM_START)) - #endif - #endif -#else - /* - * MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader. - * In this build, include FLASH_HDR region - */ - #define FLASH_HDR_INCLUDED 1 - #define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE) - #if defined(MBED_APP_SIZE) - #define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE) - #else - #define ROM_EXEC_SIZE (ROM_SIZE - FLASH_HDR_SIZE) - #endif -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - - -MEMORY -{ - FLASH_HDR (rx) : ORIGIN = FLASH_HDR_START, LENGTH = FLASH_HDR_SIZE - FLASH (rx) : ORIGIN = ROM_EXEC_START, LENGTH = ROM_EXEC_SIZE - RAM (rwx) : ORIGIN = RAM_START + VECTORS_SIZE, LENGTH = RAM_SIZE - VECTORS_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ -#if FLASH_HDR_INCLUDED == 1 - .dbghdr : ALIGN (2048) { - KEEP (*(.dbghdr)) - } > FLASH_HDR -#endif - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Location counter can end up 2byte aligned with narrow Thumb code but - __etext is assumed by startup code to be the LMA of a section in RAM - which must be 4byte aligned */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - . = ALIGN(4); - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/startup_CC3220SF.S b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/startup_CC3220SF.S deleted file mode 100644 index cdf76314c4c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/startup_CC3220SF.S +++ /dev/null @@ -1,451 +0,0 @@ -/**************************************************************************//** - * @file startup_CC3220SF.S - * @brief CMSIS Cortex-M4 Core Device Startup File for - * Device CC3220SF - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x1000 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - - .section .isr_vector - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long INT_GPIOA0_IRQHandler /* 16 */ - .long INT_GPIOA1_IRQHandler /* 17 */ - .long INT_GPIOA2_IRQHandler /* 18 */ - .long INT_GPIOA3_IRQHandler /* 19 */ - .long 0 /* 20 Reserved interrupt */ - .long INT_UARTA0_IRQHandler /* 21 */ - .long INT_UARTA1_IRQHandler /* 22 */ - .long 0 /* 23 Reserved interrupt */ - .long INT_I2CA0_IRQHandler /* 24 */ - .long 0 /* 25 Reserved interrupt */ - .long 0 /* 26 Reserved interrupt */ - .long 0 /* 27 Reserved interrupt */ - .long 0 /* 28 Reserved interrupt */ - .long 0 /* 29 Reserved interrupt */ - .long INT_ADCCH0_IRQHandler /* 30 */ - .long INT_ADCCH1_IRQHandler /* 31 */ - .long INT_ADCCH2_IRQHandler /* 32 */ - .long INT_ADCCH3_IRQHandler /* 33 */ - .long INT_WDT_IRQHandler /* 34 */ - .long INT_TIMERA0A_IRQHandler /* 35 */ - .long INT_TIMERA0B_IRQHandler /* 36 */ - .long INT_TIMERA1A_IRQHandler /* 37 */ - .long INT_TIMERA1B_IRQHandler /* 38 */ - .long INT_TIMERA2A_IRQHandler /* 39 */ - .long INT_TIMERA2B_IRQHandler /* 40 */ - .long 0 /* 41 Reserved interrupt */ - .long 0 /* 42 Reserved interrupt */ - .long 0 /* 43 Reserved interrupt */ - .long 0 /* 44 Reserved interrupt */ - .long INT_FLASH_IRQHandler /* 45 */ - .long 0 /* 46 Reserved interrupt */ - .long 0 /* 47 Reserved interrupt */ - .long 0 /* 48 Reserved interrupt */ - .long 0 /* 49 Reserved interrupt */ - .long 0 /* 50 Reserved interrupt */ - .long INT_TIMERA3A_IRQHandler /* 51 */ - .long INT_TIMERA3B_IRQHandler /* 52 */ - .long 0 /* 53 Reserved interrupt */ - .long 0 /* 54 Reserved interrupt */ - .long 0 /* 55 Reserved interrupt */ - .long 0 /* 56 Reserved interrupt */ - .long 0 /* 57 Reserved interrupt */ - .long 0 /* 58 Reserved interrupt */ - .long 0 /* 59 Reserved interrupt */ - .long 0 /* 60 Reserved interrupt */ - .long 0 /* 61 Reserved interrupt */ - .long INT_UDMA_IRQHandler /* 62 */ - .long INT_UDMAERR_IRQHandler /* 63 */ - .long 0 /* 64 Reserved interrupt */ - .long 0 /* 65 Reserved interrupt */ - .long 0 /* 66 Reserved interrupt */ - .long 0 /* 67 Reserved interrupt */ - .long 0 /* 68 Reserved interrupt */ - .long 0 /* 69 Reserved interrupt */ - .long 0 /* 70 Reserved interrupt */ - .long 0 /* 71 Reserved interrupt */ - .long 0 /* 72 Reserved interrupt */ - .long 0 /* 73 Reserved interrupt */ - .long 0 /* 74 Reserved interrupt */ - .long 0 /* 75 Reserved interrupt */ - .long 0 /* 76 Reserved interrupt */ - .long 0 /* 77 Reserved interrupt */ - .long 0 /* 78 Reserved interrupt */ - .long 0 /* 79 Reserved interrupt */ - .long 0 /* 80 Reserved interrupt */ - .long 0 /* 81 Reserved interrupt */ - .long 0 /* 82 Reserved interrupt */ - .long 0 /* 83 Reserved interrupt */ - .long 0 /* 84 Reserved interrupt */ - .long 0 /* 85 Reserved interrupt */ - .long 0 /* 86 Reserved interrupt */ - .long 0 /* 87 Reserved interrupt */ - .long 0 /* 88 Reserved interrupt */ - .long 0 /* 89 Reserved interrupt */ - .long 0 /* 90 Reserved interrupt */ - .long 0 /* 91 Reserved interrupt */ - .long 0 /* 92 Reserved interrupt */ - .long 0 /* 93 Reserved interrupt */ - .long 0 /* 94 Reserved interrupt */ - .long 0 /* 95 Reserved interrupt */ - .long 0 /* 96 Reserved interrupt */ - .long 0 /* 97 Reserved interrupt */ - .long 0 /* 98 Reserved interrupt */ - .long 0 /* 99 Reserved interrupt */ - .long 0 /* 100 Reserved interrupt */ - .long 0 /* 101 Reserved interrupt */ - .long 0 /* 102 Reserved interrupt */ - .long 0 /* 103 Reserved interrupt */ - .long 0 /* 104 Reserved interrupt */ - .long 0 /* 105 Reserved interrupt */ - .long 0 /* 106 Reserved interrupt */ - .long 0 /* 107 Reserved interrupt */ - .long 0 /* 108 Reserved interrupt */ - .long 0 /* 109 Reserved interrupt */ - .long 0 /* 110 Reserved interrupt */ - .long 0 /* 111 Reserved interrupt */ - .long 0 /* 112 Reserved interrupt */ - .long 0 /* 113 Reserved interrupt */ - .long 0 /* 114 Reserved interrupt */ - .long 0 /* 115 Reserved interrupt */ - .long 0 /* 116 Reserved interrupt */ - .long 0 /* 117 Reserved interrupt */ - .long 0 /* 118 Reserved interrupt */ - .long 0 /* 119 Reserved interrupt */ - .long 0 /* 120 Reserved interrupt */ - .long 0 /* 121 Reserved interrupt */ - .long 0 /* 122 Reserved interrupt */ - .long 0 /* 123 Reserved interrupt */ - .long 0 /* 124 Reserved interrupt */ - .long 0 /* 125 Reserved interrupt */ - .long 0 /* 126 Reserved interrupt */ - .long 0 /* 127 Reserved interrupt */ - .long 0 /* 128 Reserved interrupt */ - .long 0 /* 129 Reserved interrupt */ - .long 0 /* 130 Reserved interrupt */ - .long 0 /* 131 Reserved interrupt */ - .long 0 /* 132 Reserved interrupt */ - .long 0 /* 133 Reserved interrupt */ - .long 0 /* 134 Reserved interrupt */ - .long 0 /* 135 Reserved interrupt */ - .long 0 /* 136 Reserved interrupt */ - .long 0 /* 137 Reserved interrupt */ - .long 0 /* 138 Reserved interrupt */ - .long 0 /* 139 Reserved interrupt */ - .long 0 /* 140 Reserved interrupt */ - .long 0 /* 141 Reserved interrupt */ - .long 0 /* 142 Reserved interrupt */ - .long 0 /* 143 Reserved interrupt */ - .long 0 /* 144 Reserved interrupt */ - .long 0 /* 145 Reserved interrupt */ - .long 0 /* 146 Reserved interrupt */ - .long 0 /* 147 Reserved interrupt */ - .long 0 /* 148 Reserved interrupt */ - .long 0 /* 149 Reserved interrupt */ - .long 0 /* 150 Reserved interrupt */ - .long 0 /* 151 Reserved interrupt */ - .long 0 /* 152 Reserved interrupt */ - .long 0 /* 153 Reserved interrupt */ - .long 0 /* 154 Reserved interrupt */ - .long 0 /* 155 Reserved interrupt */ - .long 0 /* 156 Reserved interrupt */ - .long 0 /* 157 Reserved interrupt */ - .long 0 /* 158 Reserved interrupt */ - .long 0 /* 159 Reserved interrupt */ - .long 0 /* 160 Reserved interrupt */ - .long 0 /* 161 Reserved interrupt */ - .long 0 /* 162 Reserved interrupt */ - .long 0 /* 163 Reserved interrupt */ - .long INT_SHA_IRQHandler /* 164 */ - .long 0 /* 165 Reserved interrupt */ - .long 0 /* 166 Reserved interrupt */ - .long INT_AES_IRQHandler /* 167 */ - .long 0 /* 168 Reserved interrupt */ - .long INT_DES_IRQHandler /* 169 */ - .long 0 /* 170 Reserved interrupt */ - .long 0 /* 171 Reserved interrupt */ - .long 0 /* 172 Reserved interrupt */ - .long 0 /* 173 Reserved interrupt */ - .long 0 /* 174 Reserved interrupt */ - .long INT_MMCHS_IRQHandler /* 175 */ - .long 0 /* 176 Reserved interrupt */ - .long INT_I2S_IRQHandler /* 177 */ - .long 0 /* 178 Reserved interrupt */ - .long INT_CAMERA_IRQHandler /* 179 */ - .long 0 /* 180 Reserved interrupt */ - .long 0 /* 181 Reserved interrupt */ - .long 0 /* 182 Reserved interrupt */ - .long 0 /* 183 Reserved interrupt */ - .long 0 /* 184 Reserved interrupt */ - .long 0 /* 185 Reserved interrupt */ - .long 0 /* 186 Reserved interrupt */ - .long INT_NWPIC_IRQHandler /* 187 */ - .long INT_PRCM_IRQHandler /* 188 */ - .long 0 /* 189 Reserved interrupt */ - .long 0 /* 190 Reserved interrupt */ - .long INT_SSPI_IRQHandler /* 191 */ - .long INT_GSPI_IRQHandler /* 192 */ - .long INT_LSPI_IRQHandler /* 193 */ - .long 0 /* 194 Reserved interrupt */ - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler INT_GPIOA0_IRQHandler - def_irq_handler INT_GPIOA1_IRQHandler - def_irq_handler INT_GPIOA2_IRQHandler - def_irq_handler INT_GPIOA3_IRQHandler - def_irq_handler INT_UARTA0_IRQHandler - def_irq_handler INT_UARTA1_IRQHandler - def_irq_handler INT_I2CA0_IRQHandler - def_irq_handler INT_ADCCH0_IRQHandler - def_irq_handler INT_ADCCH1_IRQHandler - def_irq_handler INT_ADCCH2_IRQHandler - def_irq_handler INT_ADCCH3_IRQHandler - def_irq_handler INT_WDT_IRQHandler - def_irq_handler INT_TIMERA0A_IRQHandler - def_irq_handler INT_TIMERA0B_IRQHandler - def_irq_handler INT_TIMERA1A_IRQHandler - def_irq_handler INT_TIMERA1B_IRQHandler - def_irq_handler INT_TIMERA2A_IRQHandler - def_irq_handler INT_TIMERA2B_IRQHandler - def_irq_handler INT_FLASH_IRQHandler - def_irq_handler INT_TIMERA3A_IRQHandler - def_irq_handler INT_TIMERA3B_IRQHandler - def_irq_handler INT_UDMA_IRQHandler - def_irq_handler INT_UDMAERR_IRQHandler - def_irq_handler INT_SHA_IRQHandler - def_irq_handler INT_AES_IRQHandler - def_irq_handler INT_DES_IRQHandler - def_irq_handler INT_MMCHS_IRQHandler - def_irq_handler INT_I2S_IRQHandler - def_irq_handler INT_CAMERA_IRQHandler - def_irq_handler INT_NWPIC_IRQHandler - def_irq_handler INT_PRCM_IRQHandler - def_irq_handler INT_SSPI_IRQHandler - def_irq_handler INT_GSPI_IRQHandler - def_irq_handler INT_LSPI_IRQHandler - .end diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/CC3220SF.icf b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/CC3220SF.icf deleted file mode 100644 index 24760ca2876..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/CC3220SF.icf +++ /dev/null @@ -1,100 +0,0 @@ -/* Device specific values */ - -define symbol ROM_START = 0x01000000; -define symbol ROM_SIZE = 0x100000; -define symbol FLASH_HDR_START = ROM_START; -define symbol FLASH_HDR_SIZE = 0x800; -define symbol RAM_START = 0x20000000; -define symbol RAM_SIZE = 0x40000; -define symbol VECTORS = 195; /* This value must match NVIC_NUM_VECTORS */ - -/* Common - Do not change */ - -if (isdefinedsymbol(MBED_APP_START)) { - /* - * There're two cases if MBED_APP_START is defined. - * Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build. - * In this build, include FLASH_HDR region. - */ - if (MBED_APP_START == ROM_START) { - define symbol FLASH_HDR_INCLUDED = 1; - if (isdefinedsymbol(MBED_APP_SIZE)) { - define symbol ROM_EXEC_START = (ROM_START + FLASH_HDR_SIZE); - define symbol ROM_EXEC_SIZE = (MBED_APP_SIZE - FLASH_HDR_SIZE); - } - } - else { - /* - * Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build. - * In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area - */ - define symbol FLASH_HDR_INCLUDED = 0; - define symbol ROM_EXEC_START = MBED_APP_START; - if (isdefinedsymbol(MBED_APP_SIZE)) { - define symbol ROM_EXEC_SIZE= MBED_APP_SIZE; - } - else { - define symbol ROM_EXEC_SIZE = (ROM_SIZE- (MBED_APP_START - ROM_START)); - } - } -} -else { - /* - * MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader. - * In this build, include FLASH_HDR region - */ - define symbol FLASH_HDR_INCLUDED = 1; - define symbol ROM_EXEC_START = (ROM_START + FLASH_HDR_SIZE); - if (isdefinedsymbol (MBED_APP_SIZE)) { - define symbol ROM_EXEC_SIZE = (MBED_APP_SIZE - FLASH_HDR_SIZE); - } - else { - define symbol ROM_EXEC_SIZE = (ROM_SIZE - FLASH_HDR_SIZE); - } -} - - -/* Round up VECTORS_SIZE to 8 bytes */ -define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; - -/* boot stack size*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -/* Place the boot stack at the top of the RAM */ -define symbol CSTACK_START = (RAM_START + RAM_SIZE - MBED_BOOT_STACK_SIZE); -define symbol CSTACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* The rest of RAM */ -define symbol RAM_REGION_START = (RAM_START + VECTORS_SIZE); -define symbol RAM_REGION_SIZE = (RAM_SIZE - VECTORS_SIZE - MBED_BOOT_STACK_SIZE); - -define memory mem with size = 4G; -/* ROM regions */ -define region FLASH_HDR_region = mem:[from FLASH_HDR_START size FLASH_HDR_SIZE]; -define region FLASH_region = mem:[from ROM_EXEC_START size ROM_EXEC_SIZE]; - -/* RAM regions */ -define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; -define region CSTACK_region = mem:[from CSTACK_START size CSTACK_SIZE]; - -if (FLASH_HDR_INCLUDED == 1) { - keep {section .dbghdr}; - place in FLASH_HDR_region { readonly section .dbghdr }; -} - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem: ROM_EXEC_START { readonly section .intvec }; - -place in FLASH_region { readonly }; - -define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -place in CSTACK_region { block CSTACK }; - -define symbol __size_heap__ = 0x10000; -define block HEAP with expanding size, alignment = 8, minimum size = __size_heap__ { }; -place in RAM_region { block HEAP, readwrite, zeroinit }; - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/startup_CC3220SF.S b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/startup_CC3220SF.S deleted file mode 100644 index 04234fab247..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/startup_CC3220SF.S +++ /dev/null @@ -1,486 +0,0 @@ -;/**************************************************************************//** -; * @file startup_CC3220SF.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Device CC3220SF -; * @version V5.00 -; * @date 07. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT_GPIOA0_IRQHandler /* 16 */ - DCD INT_GPIOA1_IRQHandler /* 17 */ - DCD INT_GPIOA2_IRQHandler /* 18 */ - DCD INT_GPIOA3_IRQHandler /* 19 */ - DCD 0 /* 20 Reserved interrupt */ - DCD INT_UARTA0_IRQHandler /* 21 */ - DCD INT_UARTA1_IRQHandler /* 22 */ - DCD 0 /* 23 Reserved interrupt */ - DCD INT_I2CA0_IRQHandler /* 24 */ - DCD 0 /* 25 Reserved interrupt */ - DCD 0 /* 26 Reserved interrupt */ - DCD 0 /* 27 Reserved interrupt */ - DCD 0 /* 28 Reserved interrupt */ - DCD 0 /* 29 Reserved interrupt */ - DCD INT_ADCCH0_IRQHandler /* 30 */ - DCD INT_ADCCH1_IRQHandler /* 31 */ - DCD INT_ADCCH2_IRQHandler /* 32 */ - DCD INT_ADCCH3_IRQHandler /* 33 */ - DCD INT_WDT_IRQHandler /* 34 */ - DCD INT_TIMERA0A_IRQHandler /* 35 */ - DCD INT_TIMERA0B_IRQHandler /* 36 */ - DCD INT_TIMERA1A_IRQHandler /* 37 */ - DCD INT_TIMERA1B_IRQHandler /* 38 */ - DCD INT_TIMERA2A_IRQHandler /* 39 */ - DCD INT_TIMERA2B_IRQHandler /* 40 */ - DCD 0 /* 41 Reserved interrupt */ - DCD 0 /* 42 Reserved interrupt */ - DCD 0 /* 43 Reserved interrupt */ - DCD 0 /* 44 Reserved interrupt */ - DCD INT_FLASH_IRQHandler /* 45 */ - DCD 0 /* 46 Reserved interrupt */ - DCD 0 /* 47 Reserved interrupt */ - DCD 0 /* 48 Reserved interrupt */ - DCD 0 /* 49 Reserved interrupt */ - DCD 0 /* 50 Reserved interrupt */ - DCD INT_TIMERA3A_IRQHandler /* 51 */ - DCD INT_TIMERA3B_IRQHandler /* 52 */ - DCD 0 /* 53 Reserved interrupt */ - DCD 0 /* 54 Reserved interrupt */ - DCD 0 /* 55 Reserved interrupt */ - DCD 0 /* 56 Reserved interrupt */ - DCD 0 /* 57 Reserved interrupt */ - DCD 0 /* 58 Reserved interrupt */ - DCD 0 /* 59 Reserved interrupt */ - DCD 0 /* 60 Reserved interrupt */ - DCD 0 /* 61 Reserved interrupt */ - DCD INT_UDMA_IRQHandler /* 62 */ - DCD INT_UDMAERR_IRQHandler /* 63 */ - DCD 0 /* 64 Reserved interrupt */ - DCD 0 /* 65 Reserved interrupt */ - DCD 0 /* 66 Reserved interrupt */ - DCD 0 /* 67 Reserved interrupt */ - DCD 0 /* 68 Reserved interrupt */ - DCD 0 /* 69 Reserved interrupt */ - DCD 0 /* 70 Reserved interrupt */ - DCD 0 /* 71 Reserved interrupt */ - DCD 0 /* 72 Reserved interrupt */ - DCD 0 /* 73 Reserved interrupt */ - DCD 0 /* 74 Reserved interrupt */ - DCD 0 /* 75 Reserved interrupt */ - DCD 0 /* 76 Reserved interrupt */ - DCD 0 /* 77 Reserved interrupt */ - DCD 0 /* 78 Reserved interrupt */ - DCD 0 /* 79 Reserved interrupt */ - DCD 0 /* 80 Reserved interrupt */ - DCD 0 /* 81 Reserved interrupt */ - DCD 0 /* 82 Reserved interrupt */ - DCD 0 /* 83 Reserved interrupt */ - DCD 0 /* 84 Reserved interrupt */ - DCD 0 /* 85 Reserved interrupt */ - DCD 0 /* 86 Reserved interrupt */ - DCD 0 /* 87 Reserved interrupt */ - DCD 0 /* 88 Reserved interrupt */ - DCD 0 /* 89 Reserved interrupt */ - DCD 0 /* 90 Reserved interrupt */ - DCD 0 /* 91 Reserved interrupt */ - DCD 0 /* 92 Reserved interrupt */ - DCD 0 /* 93 Reserved interrupt */ - DCD 0 /* 94 Reserved interrupt */ - DCD 0 /* 95 Reserved interrupt */ - DCD 0 /* 96 Reserved interrupt */ - DCD 0 /* 97 Reserved interrupt */ - DCD 0 /* 98 Reserved interrupt */ - DCD 0 /* 99 Reserved interrupt */ - DCD 0 /* 100 Reserved interrupt */ - DCD 0 /* 101 Reserved interrupt */ - DCD 0 /* 102 Reserved interrupt */ - DCD 0 /* 103 Reserved interrupt */ - DCD 0 /* 104 Reserved interrupt */ - DCD 0 /* 105 Reserved interrupt */ - DCD 0 /* 106 Reserved interrupt */ - DCD 0 /* 107 Reserved interrupt */ - DCD 0 /* 108 Reserved interrupt */ - DCD 0 /* 109 Reserved interrupt */ - DCD 0 /* 110 Reserved interrupt */ - DCD 0 /* 111 Reserved interrupt */ - DCD 0 /* 112 Reserved interrupt */ - DCD 0 /* 113 Reserved interrupt */ - DCD 0 /* 114 Reserved interrupt */ - DCD 0 /* 115 Reserved interrupt */ - DCD 0 /* 116 Reserved interrupt */ - DCD 0 /* 117 Reserved interrupt */ - DCD 0 /* 118 Reserved interrupt */ - DCD 0 /* 119 Reserved interrupt */ - DCD 0 /* 120 Reserved interrupt */ - DCD 0 /* 121 Reserved interrupt */ - DCD 0 /* 122 Reserved interrupt */ - DCD 0 /* 123 Reserved interrupt */ - DCD 0 /* 124 Reserved interrupt */ - DCD 0 /* 125 Reserved interrupt */ - DCD 0 /* 126 Reserved interrupt */ - DCD 0 /* 127 Reserved interrupt */ - DCD 0 /* 128 Reserved interrupt */ - DCD 0 /* 129 Reserved interrupt */ - DCD 0 /* 130 Reserved interrupt */ - DCD 0 /* 131 Reserved interrupt */ - DCD 0 /* 132 Reserved interrupt */ - DCD 0 /* 133 Reserved interrupt */ - DCD 0 /* 134 Reserved interrupt */ - DCD 0 /* 135 Reserved interrupt */ - DCD 0 /* 136 Reserved interrupt */ - DCD 0 /* 137 Reserved interrupt */ - DCD 0 /* 138 Reserved interrupt */ - DCD 0 /* 139 Reserved interrupt */ - DCD 0 /* 140 Reserved interrupt */ - DCD 0 /* 141 Reserved interrupt */ - DCD 0 /* 142 Reserved interrupt */ - DCD 0 /* 143 Reserved interrupt */ - DCD 0 /* 144 Reserved interrupt */ - DCD 0 /* 145 Reserved interrupt */ - DCD 0 /* 146 Reserved interrupt */ - DCD 0 /* 147 Reserved interrupt */ - DCD 0 /* 148 Reserved interrupt */ - DCD 0 /* 149 Reserved interrupt */ - DCD 0 /* 150 Reserved interrupt */ - DCD 0 /* 151 Reserved interrupt */ - DCD 0 /* 152 Reserved interrupt */ - DCD 0 /* 153 Reserved interrupt */ - DCD 0 /* 154 Reserved interrupt */ - DCD 0 /* 155 Reserved interrupt */ - DCD 0 /* 156 Reserved interrupt */ - DCD 0 /* 157 Reserved interrupt */ - DCD 0 /* 158 Reserved interrupt */ - DCD 0 /* 159 Reserved interrupt */ - DCD 0 /* 160 Reserved interrupt */ - DCD 0 /* 161 Reserved interrupt */ - DCD 0 /* 162 Reserved interrupt */ - DCD 0 /* 163 Reserved interrupt */ - DCD INT_SHA_IRQHandler /* 164 */ - DCD 0 /* 165 Reserved interrupt */ - DCD 0 /* 166 Reserved interrupt */ - DCD INT_AES_IRQHandler /* 167 */ - DCD 0 /* 168 Reserved interrupt */ - DCD INT_DES_IRQHandler /* 169 */ - DCD 0 /* 170 Reserved interrupt */ - DCD 0 /* 171 Reserved interrupt */ - DCD 0 /* 172 Reserved interrupt */ - DCD 0 /* 173 Reserved interrupt */ - DCD 0 /* 174 Reserved interrupt */ - DCD INT_MMCHS_IRQHandler /* 175 */ - DCD 0 /* 176 Reserved interrupt */ - DCD INT_I2S_IRQHandler /* 177 */ - DCD 0 /* 178 Reserved interrupt */ - DCD INT_CAMERA_IRQHandler /* 179 */ - DCD 0 /* 180 Reserved interrupt */ - DCD 0 /* 181 Reserved interrupt */ - DCD 0 /* 182 Reserved interrupt */ - DCD 0 /* 183 Reserved interrupt */ - DCD 0 /* 184 Reserved interrupt */ - DCD 0 /* 185 Reserved interrupt */ - DCD 0 /* 186 Reserved interrupt */ - DCD INT_NWPIC_IRQHandler /* 187 */ - DCD INT_PRCM_IRQHandler /* 188 */ - DCD 0 /* 189 Reserved interrupt */ - DCD 0 /* 190 Reserved interrupt */ - DCD INT_SSPI_IRQHandler /* 191 */ - DCD INT_GSPI_IRQHandler /* 192 */ - DCD INT_LSPI_IRQHandler /* 193 */ - DCD 0 /* 194 Reserved interrupt */ - -__Vectors EQU __vector_table - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK INT_GPIOA0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_GPIOA0_IRQHandler - B INT_GPIOA0_IRQHandler - - PUBWEAK INT_GPIOA1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_GPIOA1_IRQHandler - B INT_GPIOA1_IRQHandler - - PUBWEAK INT_GPIOA2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_GPIOA2_IRQHandler - B INT_GPIOA2_IRQHandler - - PUBWEAK INT_GPIOA3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_GPIOA3_IRQHandler - B INT_GPIOA3_IRQHandler - - PUBWEAK INT_UARTA0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_UARTA0_IRQHandler - B INT_UARTA0_IRQHandler - - PUBWEAK INT_UARTA1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_UARTA1_IRQHandler - B INT_UARTA1_IRQHandler - - PUBWEAK INT_I2CA0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_I2CA0_IRQHandler - B INT_I2CA0_IRQHandler - - PUBWEAK INT_ADCCH0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_ADCCH0_IRQHandler - B INT_ADCCH0_IRQHandler - - PUBWEAK INT_ADCCH1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_ADCCH1_IRQHandler - B INT_ADCCH1_IRQHandler - - PUBWEAK INT_ADCCH2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_ADCCH2_IRQHandler - B INT_ADCCH2_IRQHandler - - PUBWEAK INT_ADCCH3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_ADCCH3_IRQHandler - B INT_ADCCH3_IRQHandler - - PUBWEAK INT_WDT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_WDT_IRQHandler - B INT_WDT_IRQHandler - - PUBWEAK INT_TIMERA0A_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_TIMERA0A_IRQHandler - B INT_TIMERA0A_IRQHandler - - PUBWEAK INT_TIMERA0B_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_TIMERA0B_IRQHandler - B INT_TIMERA0B_IRQHandler - - PUBWEAK INT_TIMERA1A_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_TIMERA1A_IRQHandler - B INT_TIMERA1A_IRQHandler - - PUBWEAK INT_TIMERA1B_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_TIMERA1B_IRQHandler - B INT_TIMERA1B_IRQHandler - - PUBWEAK INT_TIMERA2A_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_TIMERA2A_IRQHandler - B INT_TIMERA2A_IRQHandler - - PUBWEAK INT_TIMERA2B_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_TIMERA2B_IRQHandler - B INT_TIMERA2B_IRQHandler - - PUBWEAK INT_FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_FLASH_IRQHandler - B INT_FLASH_IRQHandler - - PUBWEAK INT_TIMERA3A_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_TIMERA3A_IRQHandler - B INT_TIMERA3A_IRQHandler - - PUBWEAK INT_TIMERA3B_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_TIMERA3B_IRQHandler - B INT_TIMERA3B_IRQHandler - - PUBWEAK INT_UDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_UDMA_IRQHandler - B INT_UDMA_IRQHandler - - PUBWEAK INT_UDMAERR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_UDMAERR_IRQHandler - B INT_UDMAERR_IRQHandler - - PUBWEAK INT_SHA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_SHA_IRQHandler - B INT_SHA_IRQHandler - - PUBWEAK INT_AES_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_AES_IRQHandler - B INT_AES_IRQHandler - - PUBWEAK INT_DES_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_DES_IRQHandler - B INT_DES_IRQHandler - - PUBWEAK INT_MMCHS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_MMCHS_IRQHandler - B INT_MMCHS_IRQHandler - - PUBWEAK INT_I2S_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_I2S_IRQHandler - B INT_I2S_IRQHandler - - PUBWEAK INT_CAMERA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_CAMERA_IRQHandler - B INT_CAMERA_IRQHandler - - PUBWEAK INT_NWPIC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_NWPIC_IRQHandler - B INT_NWPIC_IRQHandler - - PUBWEAK INT_PRCM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_PRCM_IRQHandler - B INT_PRCM_IRQHandler - - PUBWEAK INT_SSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_SSPI_IRQHandler - B INT_SSPI_IRQHandler - - PUBWEAK INT_GSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_GSPI_IRQHandler - B INT_GSPI_IRQHandler - - PUBWEAK INT_LSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -INT_LSPI_IRQHandler - B INT_LSPI_IRQHandler - END diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp deleted file mode 100644 index 683a37d4222..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp +++ /dev/null @@ -1,937 +0,0 @@ -/* CC3200_SIMPLELINK Class - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "cc3200_simplelink.h" -#include "nsapi_types.h" -#include "ip4string.h" -#include "CC3220SF_Init.h" - -#define SOCKET_IS_NON_BLOCKING (1) - -#define SL_STOP_TIMEOUT (200) - -CC3200_SIMPLELINK::CC3200_SIMPLELINK() - : _connect_error(0), - _initialized(false), - _current_role(0), - _fail(false), - _closed(false), - _connection_status(NSAPI_STATUS_DISCONNECTED), - _connected_ssid(), - _connected_channel(0), - _timeout(CC3200_SIMPLELINK_MISC_TIMEOUT) -{ - memset(_ip_buffer, 0, sizeof(_ip_buffer)); - memset(_gateway_buffer, 0, sizeof(_gateway_buffer)); - memset(_netmask_buffer, 0, sizeof(_netmask_buffer)); - memset(_mac_buffer, 0, sizeof(_mac_buffer)); -} - -/*! - \brief Configure SimpleLink to default state. - - This routine configures the device to a default state. - It's important to note that this is one example for a 'restore to default state' - function, which meet the needs of this application, 'Network Terminal'. User who - wish to incorporate this function into he's app, must adjust the implementation - and make sure it meets he's needs. - - \return Upon successful completion, the function shall return 0. - In case of failure, this function would return -1. - -*/ -nsapi_error_t CC3200_SIMPLELINK::initialize() -{ - int ret = NSAPI_ERROR_OK; - - if (!_initialized) - { - ret = CC3220SF_initSimplelink(); - if (ret == 0) - { - _current_role = WIFI_ROLE_STATION; - _initialized = true; - } - else - { - printf("simplelink_powerup failed with %d", ret); - return NSAPI_ERROR_DEVICE_ERROR; - } - } - return NSAPI_ERROR_OK; -} - -bool CC3200_SIMPLELINK::startup(int role) -{ - int32_t ret_val = -1; - if (role != WIFI_ROLE_STATION && role != WIFI_ROLE_AP && role != WIFI_ROLE_P2P) - { - return false; - } - if (role != _current_role) - { - ret_val = sl_WlanSetMode(role); - assert(ret_val == 0); - - /* For changes to take affect, we restart the NWP */ - ret_val = sl_Stop(SL_STOP_TIMEOUT); - assert(ret_val == 0); - - ret_val = sl_Start(0, 0, 0); - assert(ret_val == 0); - _current_role = role; - } - return true; -} - -// TODO: This will involve file system write -bool CC3200_SIMPLELINK::dhcp(bool enabled, int role) -{ -#ifdef FILE_SYSTEM_ENABLE - int32_t ret_val = -1; - uint32_t config_id, config_option; - - if (role != WIFI_ROLE_STATION && role != WIFI_ROLE_AP) - { - return false; - } - - if (role == WIFI_ROLE_STATION) - { - config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; - } - else - { - config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; - } - if (enabled) - { - config_option = SL_NETCFG_ADDR_DHCP; - ret_val = sl_NetCfgSet(config_id, config_option, 0, 0); - } - else - { - config_option = SL_NETCFG_ADDR_STATIC; - SlNetCfgIpV4Args_t ipV4; - ipV4.Ip = (_u32)SL_IPV4_VAL(_ip_buffer[0],_ip_buffer[1],_ip_buffer[2],_ip_buffer[3]); // _u32 IP address - ipV4.IpMask = (_u32)SL_IPV4_VAL(_netmask_buffer[0],_netmask_buffer[1],_netmask_buffer[2],_netmask_buffer[3]); // _u32 Subnet mask for this STA/P2P - ipV4.IpGateway = (_u32)SL_IPV4_VAL(_gateway_buffer[0],_gateway_buffer[1],_gateway_buffer[2],_gateway_buffer[3]); // _u32 Default gateway address - ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(_dns_server_buffer[0],_dns_server_buffer[1],_dns_server_buffer[2],_dns_server_buffer[3]); // _u32 DNS server address - ret_val = sl_NetCfgSet(config_id, config_option, sizeof(SlNetCfgIpV4Args_t), (_u8 *)&ipV4); - } - if (ret_val == 0) - { - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - return true; - } - else - { - return false; - } -#else - return true; -#endif -} - -nsapi_error_t CC3200_SIMPLELINK::connect(const char *ssid, const char *passPhrase, nsapi_security_t security) -{ - nsapi_error_t status; - _i16 ret; - SlWlanSecParams_t sec_params; - - if (!ssid || (!passPhrase && security != NSAPI_SECURITY_NONE)) - { - printf("Invalid credentials\r\n"); - return NSAPI_ERROR_PARAMETER; - } - - status = initialize(); - if(status != NSAPI_ERROR_OK) - { - return status; - } - - strncpy(_connected_ssid, ssid, sizeof(_connected_ssid)); - - memset((void*)&sec_params, 0, sizeof(sec_params)); - - startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION); - if(status != NSAPI_ERROR_OK) - { - return status; - } - - sec_params.Key = (signed char*)passPhrase; - sec_params.KeyLen = strlen(passPhrase); - switch (security) { - case NSAPI_SECURITY_WPA: - case NSAPI_SECURITY_WPA2: - case NSAPI_SECURITY_WPA_WPA2: - sec_params.Type = SL_WLAN_SEC_TYPE_WPA_WPA2; - break; - case NSAPI_SECURITY_WEP: - sec_params.Type = SL_WLAN_SEC_TYPE_WEP; - break; - case NSAPI_SECURITY_NONE: - sec_params.Type = SL_WLAN_SEC_TYPE_OPEN; - break; - default: - return NSAPI_ERROR_PARAMETER; - } - ret = sl_WlanConnect((const _i8*)ssid,(const _i16)(strlen(ssid)),(const _u8 *)NULL, - (const SlWlanSecParams_t*)&sec_params ,(const SlWlanSecParamsExt_t*)NULL); - if (ret != SL_RET_CODE_OK) { - return NSAPI_ERROR_NO_CONNECTION; - } - - return NSAPI_ERROR_OK; -} - -bool CC3200_SIMPLELINK::disconnect() -{ - return (sl_WlanDisconnect() == 0); -} - -const char *CC3200_SIMPLELINK::getIPAddress() -{ - int i; - _u16 config_id; - _u8 ip4addr[4]; - - if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client - { - config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; - } - else - { - config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go - } - _u16 len = sizeof(SlNetCfgIpV4Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC - SlNetCfgIpV4Args_t ipV4 = {0}; - - sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4); - /*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", - (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", - (int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0), - (int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0), - (int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0), - (int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/ - for (i = 0; i < 4; i ++) - { - ip4addr[i] = SL_IPV4_BYTE(ipV4.Ip,(3-i)); - } - ip4tos((const void *)ip4addr, (char *)_ip_buffer); - - return _ip_buffer; -} - -const char *CC3200_SIMPLELINK::getMACAddress() -{ - _u16 macAddressLen = SL_MAC_ADDR_LEN; - _u16 ConfigOpt = 0; - _u8 macAddress[SL_MAC_ADDR_LEN]; - - sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,&ConfigOpt,&macAddressLen,macAddress); - // Format this into xx:xx:xx:xx:xx:xx - sprintf(_mac_buffer, "%2x:%2x:%2x:%2x:%2x:%2x",macAddress[0], macAddress[1], macAddress[2], macAddress[3], macAddress[4], macAddress[5]); - return _mac_buffer; -} - -const char *CC3200_SIMPLELINK::getGateway() -{ - int i; - _u16 config_id; - _u8 ip4addr[4]; - - if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client - { - config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; - } - else - { - config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go - } - _u16 len = sizeof(SlNetCfgIpV4Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC - SlNetCfgIpV4Args_t ipV4 = {0}; - - sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4); - /*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", - (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", - (int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0), - (int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0), - (int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0), - (int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/ - for (i = 0; i < 4; i ++) - { - ip4addr[i] = SL_IPV4_BYTE(ipV4.IpGateway,(3-i)); - } - ip4tos((const void *)ip4addr, (char *)_gateway_buffer); - return _gateway_buffer; -} - -const char *CC3200_SIMPLELINK::getNetmask() -{ - int i; - _u16 config_id; - _u8 ip4addr[4]; - - if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client - { - config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; - } - else - { - config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go - } - _u16 len = sizeof(SlNetCfgIpV4Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC - SlNetCfgIpV4Args_t ipV4 = {0}; - - sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4); - /*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", - (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", - (int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0), - (int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0), - (int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0), - (int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/ - for (i = 0; i < 4; i ++) - { - ip4addr[i] = SL_IPV4_BYTE(ipV4.IpMask,(3-i)); - } - ip4tos((const void *)ip4addr, (char *)_netmask_buffer); - return _netmask_buffer; -} - -nsapi_error_t CC3200_SIMPLELINK::getDNS(unsigned char* ip4addr, uint32_t size) -{ - int i; - _u16 config_id; - - if (ip4addr == NULL || size < 4) - { - return NSAPI_ERROR_PARAMETER; - } - if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client - { - config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; - } - else - { - config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go - } - _u16 len = sizeof(SlNetCfgIpV4Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC - SlNetCfgIpV4Args_t ipV4 = {0}; - - sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4); - /*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", - (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", - (int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0), - (int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0), - (int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0), - (int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/ - for (i = 0; i < 4; i ++) - { - ip4addr[i] = SL_IPV4_BYTE(ipV4.IpDnsServer,(3-i)); - } - return NSAPI_ERROR_OK; -} - -int CC3200_SIMPLELINK::scan(WiFiAccessPoint *res, unsigned count) -{ - _u8 entries_count = MAX_SCAN_ENTRIES; - uint8_t triggeredScanTrials = 0; - _i16 ret = 0; - - if ((count != 0) && (count < MAX_SCAN_ENTRIES)) - { - entries_count = count; - } - - /* Get scan results from NWP - results would be placed inside the local buffer first */ - ret = sl_WlanGetNetworkList(0, entries_count, netEntries); - - /* If scan policy isn't set, invoking 'sl_WlanGetNetworkList()' for the first time triggers 'one shot' scan. - * The scan parameters would be according to the system persistent settings on enabled channels. - * For more information, see: - */ - - if(SL_ERROR_WLAN_GET_NETWORK_LIST_EAGAIN == ret) - { - while(triggeredScanTrials < MAX_SCAN_ATTEMPTS) - { - /* We wait for one second for the NWP to complete the initiated scan and collect results */ - ThisThread::sleep_for(1000); - - /* Collect results form one-shot scans.*/ - ret = sl_WlanGetNetworkList(0, entries_count, netEntries); - if(ret > 0) - { - break; - } - else - { - /* If NWP results aren't ready, try 'MAX_SCAN_ATTEMPTS' to get results */ - triggeredScanTrials++ ; - printf("Tried %d times", triggeredScanTrials); - } - } - - if (count == 0 || res == NULL) - { - if (ret > 0) - { - return ret; - } - else - { - printf("\n\r[scan] : Unable to retrieve the network list\n\r"); - return 0; - } - } - } - if (ret <= 0) - { - printf("\n\r[scan] : Unable to retrieve the network list\n\r"); - return 0; - } - // scan is successful if code reaches here. - if (res && count) - { - unsigned i; - - for (i = 0; i < count; i ++) - { - nsapi_wifi_ap_t ap; - netEntries[i].Ssid[netEntries[i].SsidLen] = 0; /* Ensure the SSID is null terminated */ - memset((void*)&ap, 0x00, sizeof(nsapi_wifi_ap_t)); - memcpy(ap.ssid, netEntries[i].Ssid, netEntries[i].SsidLen); - memcpy(ap.bssid, netEntries[i].Bssid, 6); - switch (SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(netEntries[i].SecurityInfo)) - { - case SL_WLAN_SECURITY_TYPE_BITMAP_OPEN: - ap.security = NSAPI_SECURITY_NONE; - break; - case SL_WLAN_SECURITY_TYPE_BITMAP_WEP: - ap.security = NSAPI_SECURITY_WEP; - break; - case SL_WLAN_SECURITY_TYPE_BITMAP_WPA: - ap.security = NSAPI_SECURITY_WPA; - break; - case SL_WLAN_SECURITY_TYPE_BITMAP_WPA2: - ap.security = NSAPI_SECURITY_WPA2; - break; - case (SL_WLAN_SECURITY_TYPE_BITMAP_WPA | SL_WLAN_SECURITY_TYPE_BITMAP_WPA2): - ap.security = NSAPI_SECURITY_WPA_WPA2; - break; - default: - ap.security = NSAPI_SECURITY_UNKNOWN; - break; - } - ap.rssi = netEntries[i].Rssi; - ap.channel = netEntries[i].Channel; - res[i] = WiFiAccessPoint(ap); - } - return count; - } - else // Either res == NULL or count == 0, return the number of scanned networks - { - return ret; - } -} - -nsapi_error_t CC3200_SIMPLELINK::set_channel(int channel) -{ - if (_current_role == WIFI_ROLE_STATION) - { - return NSAPI_ERROR_UNSUPPORTED; - } - - _i16 Status = sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_CHANNEL, 1, (unsigned char*)&channel); - if (Status == SL_RET_CODE_OK) - { - _connected_channel = channel; - return NSAPI_ERROR_OK; - } - else if (Status == SL_ERROR_INVALID_PARAM) - { - return NSAPI_ERROR_PARAMETER; - } - else - { - return NSAPI_ERROR_DEVICE_ERROR; - } -} - -nsapi_error_t CC3200_SIMPLELINK::dns_lookup(const char *name, char *ip, uint32_t ip_size, nsapi_version_t version) -{ - _i16 Status; - SlNetAppDnsClientTime_t Time; - Time.MaxResponseTime = 2000; // Max DNS retry timeout, DNS request timeout changed every retry, start with 100Ms up to MaxResponseTime Ms - Time.NumOfRetries = 30; // number DNS retries before sl_NetAppDnsGetHostByName failed - Status = sl_NetAppSet(SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, sizeof(Time), (_u8*)&Time); - if( Status ) - { - return NSAPI_ERROR_DNS_FAILURE; - } - if (name && ip) - { - if ((version == NSAPI_IPv4 || version == NSAPI_UNSPEC) && ip_size >= NSAPI_IPv4_BYTES) - { - if (sl_NetAppDnsGetHostByName((_i8*)name, strlen(name), (_u32 *)ip, SL_AF_INET) == 0) - { - printf("%s has ip %d.%d.%d.%d\n", name, (int)SL_IPV4_BYTE(*(_u32 *)ip,3),(int)SL_IPV4_BYTE(*(_u32 *)ip,2),(int)SL_IPV4_BYTE(*(_u32 *)ip,1),(int)SL_IPV4_BYTE(*(_u32 *)ip,0)); - return NSAPI_ERROR_OK; - } - else - { - printf("sl_NetAppDnsGetHostByName failed\n"); - return NSAPI_ERROR_DNS_FAILURE; - } - } - if (version == NSAPI_IPv6 && ip_size >= NSAPI_IPv6_BYTES) - { - if (sl_NetAppDnsGetHostByName((_i8*)name, strlen(name), (_u32 *)ip, SL_AF_INET6) == 0) - { - return NSAPI_ERROR_OK; - } - else - { - return NSAPI_ERROR_DNS_FAILURE; - } - } - } - return NSAPI_ERROR_DNS_FAILURE; -} - -int8_t CC3200_SIMPLELINK::getRSSI() -{ - int i; - // Match connected network - for (i = 0; i < MAX_SCAN_ENTRIES; i++) - { - if (strcmp((char*)netEntries[i].Ssid, _connected_ssid) == 0 && netEntries[i].Channel == _connected_channel) - { - break; - } - } - if (i < MAX_SCAN_ENTRIES) - { - return netEntries[i].Rssi; - } - else - { - printf("Unscanned network, initiate network scan to get valid RSSI.\n"); - return 0; - } -} - -int8_t CC3200_SIMPLELINK::get_current_wifi_mode() -{ - return _current_role; -} - -nsapi_connection_status_t CC3200_SIMPLELINK::get_connection_status() const -{ - return _connection_status; -} - -void CC3200_SIMPLELINK::set_connection_status(nsapi_connection_status_t status) -{ - _connection_status = status; - if(_connection_status_cb) - { - _connection_status_cb(NSAPI_EVENT_CONNECTION_STATUS_CHANGE, _connection_status); - } -} - -void CC3200_SIMPLELINK::attach(mbed::Callback status_cb) -{ - _connection_status_cb = status_cb; -} - -nsapi_error_t CC3200_SIMPLELINK::open_socket(nsapi_protocol_t proto) -{ - int32_t sock = 0; - - if (proto == NSAPI_TCP) - { - sock = sl_Socket(SL_AF_INET, SL_SOCK_STREAM, 0); - } - else if (proto == NSAPI_UDP) - { - sock = sl_Socket(SL_AF_INET, SL_SOCK_DGRAM, 0); - } - if (sock >= 0) - { - return sock; - } - else - { - printf("open_socket failed with %d\n", (int)sock); - return NSAPI_ERROR_NO_SOCKET; - } -} - -bool CC3200_SIMPLELINK::close_socket(uint32_t sock) -{ - int32_t retcode = 0; - - retcode = sl_Close(sock); - if (retcode == 0) - { - return true; - } - else - { - printf("close_socket failed with %d\n", (int)retcode); - return false; - } -} -nsapi_error_t CC3200_SIMPLELINK::setsockopt(uint32_t sd, int level, - int optname, const void *optval, unsigned optlen) -{ - _i16 retcode = sl_SetSockOpt((_i16)sd, level, optname, optval, optlen); - if (retcode == 0) - { - return NSAPI_ERROR_OK; - } - else - { - printf ("sl_SetSockOpt failed with %d\n", (int)retcode); - return NSAPI_ERROR_DEVICE_ERROR; - } -} - -nsapi_error_t CC3200_SIMPLELINK::getsockopt(uint32_t sd, int level, - int optname, void *optval, unsigned* optlen) -{ - _i16 retcode =sl_GetSockOpt((_i16)sd, level, optname, optval, (SlSocklen_t*)optlen); - if (retcode == 0) - { - return NSAPI_ERROR_OK; - } - else - { - printf ("sl_GetSockOpt failed with %d\n", (int)retcode); - return NSAPI_ERROR_DEVICE_ERROR; - } -} - -nsapi_error_t CC3200_SIMPLELINK::connect_socket(uint32_t sd, const SocketAddress &sock_addr) -{ - sockAddr_t sAddr; - SlSockAddr_t* sa; - int32_t addrSize; - int32_t status = -1; - short int nonBlocking = SOCKET_IS_NON_BLOCKING; - - _fill_sl_address(sAddr, sa, addrSize, sock_addr); - - if (1 == nonBlocking) - { - // non-blocking - status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, &nonBlocking, sizeof(nonBlocking)); - if(status < 0) - { - printf("sl_SetSockOpt failed with %d\n\r", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - } - status = -1; - while (status < 0) - { - status = sl_Connect((short int)sd, sa, (short int)addrSize); - // on a non-blocking connect, retry if SL_ERROR_BSD_EALREADY is returned - { - if (status == SL_ERROR_BSD_EALREADY && 1 == nonBlocking) - { - ThisThread::sleep_for(1); - continue; - } - else if (status < 0) - { - printf("sl_Connect failed with %d\n", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - } - } - return NSAPI_ERROR_OK; -} - -nsapi_error_t CC3200_SIMPLELINK::bind_socket(uint32_t sd, const SocketAddress &sock_addr) -{ - sockAddr_t sAddr; - SlSockAddr_t* sa; - int32_t addrSize; - int32_t status = -1; - - _fill_sl_address(sAddr, sa, addrSize, sock_addr); - - status = sl_Bind(sd, sa, addrSize); - if (status == 0) - { - return NSAPI_ERROR_OK; - } - else - { - printf ("sl_Bind failed with %d\n", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } -} - -int CC3200_SIMPLELINK::sendto_socket(uint32_t sd, const void * buf, uint32_t bufLen, const SocketAddress &sock_addr) -{ - sockAddr_t sAddr; - SlSockAddr_t* sa; - int32_t addrSize; - int32_t status = -1; - - _fill_sl_address(sAddr, sa, addrSize, sock_addr); - - while (1) - { - status = sl_SendTo(sd, buf, bufLen, 0, sa, addrSize); - if (status == SL_ERROR_BSD_EAGAIN && 1 == SOCKET_IS_NON_BLOCKING) - { - ThisThread::sleep_for(1); - continue; - } - else if (status < 0) - { - printf ("sl_SendTo failed with %d\n", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - break; - } - return status; -} - -int32_t CC3200_SIMPLELINK::send(int sd, const void *data, uint32_t size) -{ - int32_t status = -1; - - while (1) - { - status = sl_Send(sd, data, size, 0); - if (status == SL_ERROR_BSD_EAGAIN && 1 == SOCKET_IS_NON_BLOCKING) - { - ThisThread::sleep_for(1); - continue; - } - else if (status < 0) - { - printf ("sl_Send failed with %d\n", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - break; - } - return status; -} - -int32_t CC3200_SIMPLELINK::recv(int sd, void *data, uint32_t size) -{ - int32_t status = -1; - SlSockNonblocking_t BlockingOption; - struct SlTimeval_t TimeVal; - - BlockingOption.NonBlockingEnabled = SOCKET_IS_NON_BLOCKING; - - if (1 == SOCKET_IS_NON_BLOCKING) - { - // non-blocking - status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, (_u8*)&BlockingOption,sizeof(BlockingOption)); - if(status < 0) - { - printf("sl_SetSockOpt failed with %d\n\r", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - } - else - { - /* In case of blocking, a timeout for sl_RecvFrom will be set to TimeVal - * When timeout is expired sl_Recv will return SL_ERROR_BSD_EAGAIN */ - TimeVal.tv_sec = _timeout; - TimeVal.tv_usec = 0; - status = sl_SetSockOpt(sd,SL_SOL_SOCKET,SL_SO_RCVTIMEO, - (uint8_t *)&TimeVal, - sizeof(TimeVal)); - if(status < 0) - { - printf ("sl_SetSockOpt failed with %d\n", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - } - - memset((void *)data, 0, size); - - status = sl_Recv(sd, data, size, 0); - if(status == SL_ERROR_BSD_EAGAIN) - { - if (1 == SOCKET_IS_NON_BLOCKING) - { - return NSAPI_ERROR_WOULD_BLOCK; - } - else - { - printf ("Timeout expired before receiving packet\n"); - return NSAPI_ERROR_TIMEOUT; - } - } - else if(status < 0) - { - printf ("sl_Recv failed with %d\n", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - else - { - return status; - } -} - -int32_t CC3200_SIMPLELINK::recvfrom(uint32_t sd, void * buf, uint32_t size, SocketAddress &sock_addr) -{ - sockAddr_t sAddr; - SlSockAddr_t* sa; - int32_t addrSize; - int32_t status = -1; - SlSockNonblocking_t BlockingOption; - struct SlTimeval_t TimeVal; - nsapi_addr_t nsapi_addr = sock_addr.get_addr(); - - - BlockingOption.NonBlockingEnabled = SOCKET_IS_NON_BLOCKING; - - if (1 == SOCKET_IS_NON_BLOCKING) - { - // non-blocking - status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, (_u8*)&BlockingOption,sizeof(BlockingOption)); - if(status < 0) - { - printf("sl_SetSockOpt failed with %d\n\r", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - } - else - { - /* In case of blocking, a timeout for sl_RecvFrom will be set to TimeVal - * When timeout is expired sl_RecvFrom will return SL_ERROR_BSD_EAGAIN */ - TimeVal.tv_sec = _timeout; - TimeVal.tv_usec = 0; - status = sl_SetSockOpt(sd,SL_SOL_SOCKET,SL_SO_RCVTIMEO, - (uint8_t *)&TimeVal, - sizeof(TimeVal)); - if(status < 0) - { - printf ("sl_SetSockOpt failed with %d\n", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - } - - memset((void*)buf, 0, size); - - _fill_sl_address(sAddr, sa, addrSize, sock_addr); - - // sl_RecvFrom requires size to be 1-16000 bytes. Can't pass 0 - if (size == 0) - { - status = sl_RecvFrom(sd, buf, 1, 0, sa, (SlSocklen_t*)&addrSize); - } - else - { - status = sl_RecvFrom(sd, buf, size, 0, sa, (SlSocklen_t*)&addrSize); - } - if(status == SL_ERROR_BSD_EAGAIN) - { - if (1 == SOCKET_IS_NON_BLOCKING) - { - return NSAPI_ERROR_WOULD_BLOCK; - } - else - { - printf ("Timeout expired before receiving packet\n"); - return NSAPI_ERROR_TIMEOUT; - } - } - else if(status < 0) - { - printf ("sl_RecvFrom failed with %d\n", (int)status); - return NSAPI_ERROR_DEVICE_ERROR; - } - else if ((status > 0 && size > 0) || (status == 0 && size == 0)) - { - // Fill the ip and port - memset((void*)&nsapi_addr, 0, sizeof(nsapi_addr)); - bool ipv6 = (sock_addr.get_ip_version() == NSAPI_IPv6); - if (ipv6) - { - sock_addr.set_port(sl_Ntohs(sAddr.in6.sin6_port)); - nsapi_addr.version = NSAPI_IPv6; - *(unsigned long *)&nsapi_addr.bytes[0] = sAddr.in6.sin6_addr._S6_un._S6_u32[0]; - *(unsigned long *)&nsapi_addr.bytes[4] = sAddr.in6.sin6_addr._S6_un._S6_u32[1]; - *(unsigned long *)&nsapi_addr.bytes[8] = sAddr.in6.sin6_addr._S6_un._S6_u32[2]; - *(unsigned long *)&nsapi_addr.bytes[12] = sAddr.in6.sin6_addr._S6_un._S6_u32[3]; - sock_addr.set_addr(nsapi_addr); - } - else - { - sock_addr.set_port(sl_Ntohs(sAddr.in4.sin_port)); - nsapi_addr.version = NSAPI_IPv4; - *(unsigned int*)nsapi_addr.bytes = sAddr.in4.sin_addr.s_addr; - sock_addr.set_addr(nsapi_addr); - } - } - return status; -} - -void CC3200_SIMPLELINK::setTimeout(uint32_t timeout_ms) -{ - _timeout = timeout_ms; -} - -void CC3200_SIMPLELINK::_fill_sl_address(sockAddr_t &sAddr, SlSockAddr_t* &sa, int32_t &addrSize, const SocketAddress &sock_addr) -{ - nsapi_addr_t nsapi_addr = sock_addr.get_addr(); - bool ipv6 = (sock_addr.get_ip_version() == NSAPI_IPv6); - - memset((void*)&sAddr, 0, sizeof(sAddr)); - - if (ipv6) - { - sAddr.in6.sin6_family = SL_AF_INET6; - sAddr.in6.sin6_port = sl_Htons(sock_addr.get_port()); - sAddr.in6.sin6_flowinfo = 0; - - sAddr.in6.sin6_addr._S6_un._S6_u32[0] = *(unsigned long *)&nsapi_addr.bytes[0]; - sAddr.in6.sin6_addr._S6_un._S6_u32[1] = *(unsigned long *)&nsapi_addr.bytes[4]; - sAddr.in6.sin6_addr._S6_un._S6_u32[2] = *(unsigned long *)&nsapi_addr.bytes[8]; - sAddr.in6.sin6_addr._S6_un._S6_u32[3] = *(unsigned long *)&nsapi_addr.bytes[12]; - sa = (SlSockAddr_t*)&sAddr.in6; - addrSize = sizeof(SlSockAddrIn6_t); - } - else - { - sAddr.in4.sin_family = SL_AF_INET; - sAddr.in4.sin_port = sl_Htons(sock_addr.get_port()); - sAddr.in4.sin_addr.s_addr = *(unsigned int*)nsapi_addr.bytes; - sa = (SlSockAddr_t*)&sAddr.in4; - addrSize = sizeof(SlSockAddrIn_t); - } -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.h deleted file mode 100644 index 424a99071b6..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.h +++ /dev/null @@ -1,330 +0,0 @@ - -/* CC3200_SIMPLELINK Class - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef CC3200_SIMPLELINK_H -#define CC3200_SIMPLELINK_H -#include "mbed.h" -#include -#include "nsapi_types.h" -#include "nsapi.h" -#include "rtos.h" -#include "netsocket/WiFiAccessPoint.h" -#include "ti/drivers/net/wifi/netcfg.h" -#include "ti/drivers/ti_SPI.h" -#include "ti/drivers/dma/UDMACC32XX.h" -#include "ti/drivers/net/wifi/sl_socket.h" -#include "ti/drivers/net/wifi/netapp.h" -#include "ti/drivers/net/wifi/wlan.h" - -#define MAX_SCAN_TIMEOUT (15000) -#define MAX_SCAN_ENTRIES (15) -#define MAX_SCAN_ATTEMPTS (10) - -#ifndef CC3200_SIMPLELINK_MISC_TIMEOUT -#define CC3200_SIMPLELINK_MISC_TIMEOUT 2000 -#endif - -/** - * This is the interface class to CC3200 Simplelink - */ -class CC3200_SIMPLELINK -{ -public: - CC3200_SIMPLELINK(); - - /** - * Initialize CC3200_SIMPLELINK to default state (STATION mode) - */ - nsapi_error_t initialize(); - - /** - * Startup the CC3200_SIMPLELINK - * - * @param role role of WIFI 0-Station, 2-AP, 3-P2P - * @return true only if it was setup correctly - */ - bool startup(int role); - - /** - * Reset CC3200_SIMPLELINK - * - * @return true only if CC3200_SIMPLELINK resets successfully - */ - //bool reset(void); - - /** - * Enable/Disable DHCP - * - * @param enabled DHCP enabled when true - * @param mode mode of DHCP 0-softAP, 1-station, 2-both - * @return true only if CC3200_SIMPLELINK enables/disables DHCP successfully - */ - bool dhcp(bool enabled, int mode); - - /** - * Connect CC3200 SimpleLink to AP - * - * @param ap the name of the AP - * @param passPhrase the password of AP - * @param security security type - * @return NSAPI_ERROR_OK only if CC3200 SimpleLink is connected successfully - */ - nsapi_error_t connect(const char *ap, const char *passPhrase, nsapi_security_t security); - - /** - * Disconnect CC3200 SimpleLink from AP - * - * @return true only if CC3200_SIMPLELINK is disconnected successfully - */ - bool disconnect(void); - - /** - * Get the IP address of CC3200 SimpleLink - * - * @return null-teriminated IP address or null if no IP address is assigned - */ - const char *getIPAddress(void); - - /** - * Get the MAC address of CC3200 SimpleLink - * - * @return null-terminated MAC address or null if no MAC address is assigned - */ - const char *getMACAddress(void); - - /** Get the local gateway - * - * @return Null-terminated representation of the local gateway - * or null if no network mask has been received - */ - const char *getGateway(); - - /** Get the local network mask - * - * @return Null-terminated representation of the local network mask - * or null if no network mask has been recieved - */ - const char *getNetmask(); - - /** Get DNS server address - * - * @param ipaddr Pointer to allocated array to store DNS server raw address - * @param len Size of the storage area - * @return NSAPI_ERROR_OK on success or other error codes on failure - */ - nsapi_error_t getDNS(unsigned char* ip4addr, uint32_t len); - - /* Return RSSI for active connection - * - * @return Measured RSSI - */ - int8_t getRSSI(); - - /** Scan for available networks - * - * @param ap Pointer to allocated array to store discovered AP - * @param limit Size of allocated @a res array, or 0 to only count available AP - * @return Number of entries in @a res, or if @a count was 0 number of available networks, negative on error - * see @a nsapi_error - */ - int scan(WiFiAccessPoint *res, unsigned count); - - /** Set channel - * - * @param channel channel to set - * @return NSAPI error code - */ - nsapi_error_t set_channel(int channel); - - /**Perform a dns query - * - * @param name Hostname to resolve - * @param ip Buffer to store IP address - * @return NSAPI error code - */ - nsapi_error_t dns_lookup(const char *name, char *ip, uint32_t ip_size, nsapi_version_t version); - - /** - * Open a socket - * - * @return handle of the opened socket only if socket opened successfully, 0 or error otherwise - */ - nsapi_error_t open_socket(nsapi_protocol_t proto); - - /** - * Close a socket - * - * @return true if socket was closed successfully, false otherwise - */ - bool close_socket(uint32_t sock); - - /** - * Set socket options - * - * @param sd socket descritor - * @param level protocol level for this option - * @param optname option name to interrogate - * @param optval points to the value for the option - * @param optlen length of the option value - * @return nsapi status - */ - nsapi_error_t setsockopt(uint32_t sd, int level, - int optname, const void *optval, unsigned optlen); - - /** - * Get socket options - * - * @param sd socket descriptor - * @param level protocol level for this option - * @param optname option name to interrogate - * @param optval points to the value for the option - * @param optlen length of the option value - * @return nsapi status - */ - nsapi_error_t getsockopt(uint32_t sd, int level, - int optname, void *optval, unsigned* optlen); - /** - * Initiate a connection on a socket (blocking) - * - * @param sd socket handle - * @param sock_addr SocketAddress structure - * @return nsapi status - */ - nsapi_error_t connect_socket(uint32_t sd, const SocketAddress &sock_addr); - - /** - * Assigns a socket an local address - * - * @param sd socket handle - * @param sock_addr SocketAddress structure - * - * @return nsapi status - */ - nsapi_error_t bind_socket(uint32_t sd, const SocketAddress &sock_addr); - - /** - * Write data to socket Initiate a connection on a socket (nonblocking) - * - * @param sd socket handle - * @param buf pointer to a buffer containing the data to be sent - * @param bufLen data length in bytes - * @param sock_addr SocketAddress structure - * @return a socket handle - */ - int sendto_socket(uint32_t sd, const void * buf, uint32_t bufLen, const SocketAddress &sock_addr); - - /** - * Sends data to an open socket (nonblocking) - * - * @param sd sd of socket to send to - * @param data data to be sent - * @param size number of bytes to be sent - max 1024 - * @return number of sent bytes on success, negative error code on failure - */ - int32_t send(int id, const void *data, uint32_t size); - - /** - * Receives stream data from an open TCP socket (nonblocking) - * - * @param sd sd to receive from - * @param data placeholder for returned information - * @param size number of bytes to be received - * @return the number of bytes received - */ - int32_t recv(int sd, void *data, uint32_t size); - - /** - * Receives data from socket - * - * @param sd sd to receive from - * @param buf placeholder for returned information - * @param size number of bytes to be received - * @param sock_addr SocketAddress structure - * @return the number of bytes received - */ - int32_t recvfrom(uint32_t sd, void * buf, uint32_t size, SocketAddress &sock_addr); - - /** - * Allows timeout to be changed between commands - * - * @param timeout_ms timeout of the connection - */ - void setTimeout(uint32_t timeout_ms=CC3200_SIMPLELINK_MISC_TIMEOUT); - - /** - * Attach a function to call whenever network state has changed - * - * @param func A pointer to a void function, or 0 to set as none - */ - void attach(mbed::Callback status_cb); - - /** - * Read default Wifi role - * - * return Station, AP or P2P - */ - int8_t get_current_wifi_mode(); - - /** - * Write default Wifi - */ - //bool set_default_wifi_mode(const int8_t mode); - - /** Get the connection status - * - * @return The connection status according to ConnectionStatusType - */ - nsapi_connection_status_t get_connection_status() const; - - /** Set the connection status - * - * @param status The connection status to set - */ - void set_connection_status(nsapi_connection_status_t status); - - static const int8_t WIFI_ROLE_STATION = 1; - static const int8_t WIFI_ROLE_AP = 2; - static const int8_t WIFI_ROLE_P2P = 3; - -private: - - typedef union{ - SlSockAddrIn6_t in6; /* Socket info for Ipv6 */ - SlSockAddrIn_t in4; /* Socket info for Ipv4 */ - }sockAddr_t; - - char _ip_buffer[NSAPI_IPv4_SIZE]; - char _gateway_buffer[NSAPI_IPv4_SIZE]; - char _netmask_buffer[NSAPI_IPv4_SIZE]; - char _mac_buffer[NSAPI_MAC_SIZE]; - char _dns_server_buffer[NSAPI_IPv4_SIZE]; - - int _connect_error; - bool _initialized; - int _current_role; - bool _fail; - bool _closed; - nsapi_connection_status_t _connection_status; - mbed::Callback _connection_status_cb; - char _connected_ssid[SL_WLAN_SSID_MAX_LENGTH+1]; /* 32 is what 802.11 defines as longest possible name; +1 for the \0 */ - int _connected_channel; - SlWlanNetworkEntry_t netEntries[MAX_SCAN_ENTRIES]; - int _timeout; - void _fill_sl_address(sockAddr_t &sAddr, SlSockAddr_t* &sa, int32_t &addrSize, const SocketAddress &sock_addr); -}; -#endif /* CC3200_SIMPLELINK_H_ */ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis.h deleted file mode 100644 index da2cc131f6c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis.h +++ /dev/null @@ -1,41 +0,0 @@ -/* CC3220SF CMSIS Library -* -* Copyright (c) 2006-2018 ARM Limited -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -******************************************************************************* -* A generic CMSIS include header, pulling in CC3220SF specifics -*******************************************************************************/ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "CC3220SF.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis_nvic.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis_nvic.h deleted file mode 100644 index 64f735054de..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis_nvic.h +++ /dev/null @@ -1,39 +0,0 @@ -/* CC3220SF CMSIS Library -* -* Copyright (c) 2006-2018 ARM Limited -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -*******************************************************************************/ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (195) -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/default_wifi_interface.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/default_wifi_interface.cpp deleted file mode 100644 index 228042cd02c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/default_wifi_interface.cpp +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "CC3220SF_WiFiInterface.h" - -WiFiInterface *WiFiInterface::get_target_default_instance() -{ - static CC3220SFInterface wifi; - return &wifi; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c deleted file mode 100644 index 4c2482c0516..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************//** - * @file system_CC3220SF.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for - * Device CC3220SF - * @version V5.00 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "CC3220SF.h" -#include "../inc/hw_types.h" -#include "CC3220SF_LAUNCHXL.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -/* ToDo: add here your necessary defines for device initialization - following is an example for different system frequencies */ -#define XTAL (40000000U) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (2 * XTAL) - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -/* ToDo: initialize SystemCoreClock with the system core clock frequency value - achieved after system intitialization. - This means system core clock frequency after call to SystemInit() */ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/ - - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ - -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ -} - -void SystemInit (void) -{ - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; - CC3220SF_LAUNCHXL_initGeneral(); -} - -/* - * ======== ClockP_getCpuFreq ======== - */ -void ClockP_getCpuFreq(ClockP_FreqHz *freq) -{ - freq->lo = (uint32_t)SystemCoreClock; - freq->hi = 0; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h deleted file mode 100644 index fb686bb02d5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************//** - * @file system_CC3220SF.h - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for - * Device CC3220SF - * @version V5.00 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_CC3220SF_H /* ToDo: replace '' with your device name */ -#define SYSTEM_CC3220SF_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "ti/drivers/net/wifi/wlan.h" -#include "ti/drivers/dpl/ClockP.h" - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -extern void PRCMMCUReset(unsigned char bIncludeSubsystem); -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __CC3200_SystemReset(void) -{ - /* Stop the NWP */ - _i16 retcode = sl_Stop(0); - if (retcode != 0 && retcode != SL_RET_CODE_DEV_NOT_STARTED) - { - printf("sl_stop failed with 0x%x\n", retcode); - } - - PRCMMCUReset(0); -} -#ifdef NVIC_SystemReset -#undef NVIC_SystemReset -#endif -#define NVIC_SystemReset __CC3200_SystemReset - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM__H */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/wifi_event_handler.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/wifi_event_handler.cpp deleted file mode 100755 index 3cb50f356c8..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/wifi_event_handler.cpp +++ /dev/null @@ -1,514 +0,0 @@ -/* - * Copyright (c) 2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/***************************************************************************** - - Application Name - Network terminal - - Application Overview - Network Terminal is a command line interface (cli) based application, - used to demonstrate the CC32XX/CC31XX networking capabilities. - It does that by offering a list of commands, divided into four silos: - - Wlan : Contains link layer functions like scan, connect, etc. - NetApp : Demonstrates the usage of networking applications. - Socket : Shows variety of socket API and responsible for sending and receiving packets. - Transceiver : Gives the user a direct interface to the NWP radio for RF tests, raw sockets (L1) and more. - - Application Details - Refer to 'Network Terminal' README.html - -*****************************************************************************/ - -/* Standard includes */ -#include -#include -#include -#include "rtos.h" - -#include -#include - -#define HANDLER_TRACE_ENABLE 0 - -/**************************************************************************** - LOCAL FUNCTION PROTOTYPES -****************************************************************************/ - - -/**************************************************************************** - GLOBAL VARIABLES -****************************************************************************/ - - - -/***************************************************************************** - Callback Functions -*****************************************************************************/ - -/*! - \brief SimpleLinkWlanEventHandler - - This handler gets called whenever a WLAN event is reported - by the host driver / NWP. Here user can implement he's own logic - for any of these events. This handler is used by 'network_terminal' - application to show case the following scenarios: - - 1. Handling connection / Disconnection. - 2. Handling Addition of station / removal. - 3. RX filter match handler. - 4. P2P connection establishment. - - \param pWlanEvent - pointer to Wlan event data. - - \return void - - \note For more information, please refer to: user.h in the porting - folder of the host driver and the CC3120/CC3220 NWP programmer's - guide (SWRU455) sections 4.3.4, 4.4.5 and 4.5.5. - - \sa cmdWlanConnectCallback, cmdEnableFilterCallback, cmdWlanDisconnectCallback, - cmdP2PModecallback. - -*/ -void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) -{ - if(!pWlanEvent) - { - return; - } - - switch(pWlanEvent->Id) - { - case SL_WLAN_EVENT_CONNECT: - { - #if HANDLER_TRACE_ENABLE == 1 - printf("\n\r[WLAN EVENT] STA Connected to the AP: %s , " - "BSSID: %x:%x:%x:%x:%x:%x\n\r", - pWlanEvent->Data.Connect.SsidName, pWlanEvent->Data.Connect.Bssid[0], - pWlanEvent->Data.Connect.Bssid[1],pWlanEvent->Data.Connect.Bssid[2], - pWlanEvent->Data.Connect.Bssid[3],pWlanEvent->Data.Connect.Bssid[4], - pWlanEvent->Data.Connect.Bssid[5]); - #endif - CC3220SFInterface::cc3200sf_wifi_instance->_connect_sem.release(); - } - break; - - case SL_WLAN_EVENT_DISCONNECT: - { - SlWlanEventDisconnect_t *pEventData = NULL; - - pEventData = &pWlanEvent->Data.Disconnect; - - /* If the user has initiated 'Disconnect' request, - 'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED */ - if(SL_WLAN_DISCONNECT_USER_INITIATED == pEventData->ReasonCode) - { - #if HANDLER_TRACE_ENABLE == 1 - printf("\n\r[WLAN EVENT] Device disconnected from the AP\n\r"); - #endif - } - else - { - printf("\n\r[WLAN ERROR] Device disconnected from the AP\n\r"); - } - } - break; - - case SL_WLAN_EVENT_PROVISIONING_STATUS: - { - /* Do nothing, this suppress provisioning event is because simplelink is configured to default state. */ - } - break; - - case SL_WLAN_EVENT_STA_ADDED: - { - printf("\n\r[WLAN EVENT] STA was added to AP: BSSID: %x:%x:%x:%x:%x:%x\n\r", - pWlanEvent->Data.STAAdded.Mac[0],pWlanEvent->Data.STAAdded.Mac[1], - pWlanEvent->Data.STAAdded.Mac[2],pWlanEvent->Data.STAAdded.Mac[3], - pWlanEvent->Data.STAAdded.Mac[4],pWlanEvent->Data.STAAdded.Mac[5]); - } - break; - - case SL_WLAN_EVENT_STA_REMOVED: - { - printf("\n\r[WLAN EVENT] STA was removed from AP\n\r"); - } - break; - - case SL_WLAN_EVENT_RXFILTER: - { - SlWlanEventRxFilterInfo_t *triggred_filter = NULL; - - triggred_filter = &(pWlanEvent->Data.RxFilterInfo) ; - - printf("\n\r[WLAN EVENT] Rx filter match triggered. Set filters in filter bitmap :0x%x.\n\r", triggred_filter->UserActionIdBitmap[0]); - - /* - * User can write he's / her's rx filter match handler here. - * Be advised, you can use the 'triggred_filter' structure info to determine which filter - * has received a match. (Bit X is set if user action id X was passed to a filter that matched a packet.) - */ - } - break; - - case SL_WLAN_EVENT_P2P_DEVFOUND: - { - printf("\n\r[WLAN EVENT] P2P Remote device found\n\r"); - } - break; - - case SL_WLAN_EVENT_P2P_REQUEST: - { - printf("\n\r[WLAN EVENT] P2P Negotiation request received\n\r"); - } - break; - - case SL_WLAN_EVENT_P2P_CONNECT: - { - printf("n\r[WLAN EVENT] P2P connection was successfully completed as CLIENT\n\r"); - printf("n\rBSSID is %02x:%02x:%02x:%02x:%02x:%02x\n\r", - pWlanEvent->Data.STAAdded.Mac[0], - pWlanEvent->Data.STAAdded.Mac[1], - pWlanEvent->Data.STAAdded.Mac[2], - pWlanEvent->Data.STAAdded.Mac[3], - pWlanEvent->Data.STAAdded.Mac[4], - pWlanEvent->Data.STAAdded.Mac[5]); - } - break; - - case SL_WLAN_EVENT_P2P_CLIENT_ADDED: - { - printf("n\r[WLAN EVENT] P2P connection was successfully completed as GO\n\r"); - printf("n\rBSSID is %02x:%02x:%02x:%02x:%02x:%02x\n\r", - pWlanEvent->Data.P2PClientAdded.Mac[0], - pWlanEvent->Data.P2PClientAdded.Mac[1], - pWlanEvent->Data.P2PClientAdded.Mac[2], - pWlanEvent->Data.P2PClientAdded.Mac[3], - pWlanEvent->Data.P2PClientAdded.Mac[4], - pWlanEvent->Data.P2PClientAdded.Mac[5]); - } - break; - - case SL_WLAN_EVENT_P2P_DISCONNECT: - { - printf("\n\r[WLAN EVENT] STA disconnected from device.\n\r"); - } - break; - - default: - { - printf("\n\r[WLAN EVENT] Unexpected event [0x%x]\n\r", (unsigned int)pWlanEvent->Id); - } - break; - } -} - -/*! - \brief SimpleLinkNetAppEventHandler - - This handler gets called whenever a Netapp event is reported - by the host driver / NWP. Here user can implement he's own logic - for any of these events. This handler is used by 'network_terminal' - application to show case the following scenarios: - - 1. Handling IPv4 / IPv6 IP address acquisition. - 2. Handling IPv4 / IPv6 IP address Dropping. - - \param pNetAppEvent - pointer to Netapp event data. - - \return void - - \note For more information, please refer to: user.h in the porting - folder of the host driver and the CC3120/CC3220 NWP programmer's - guide (SWRU455) section 5.7 - -*/ -void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) -{ - if(!pNetAppEvent) - { - return; - } - - switch(pNetAppEvent->Id) - { - case SL_NETAPP_EVENT_IPV4_ACQUIRED: - { - #if HANDLER_TRACE_ENABLE == 1 - SlIpV4AcquiredAsync_t *pEventData = NULL; - - /* Ip Acquired Event Data */ - pEventData = &pNetAppEvent->Data.IpAcquiredV4; - - printf("\n\r[NETAPP EVENT] IP set to: IPv4=%d.%d.%d.%d , " - "Gateway=%d.%d.%d.%d\n\r", - - (unsigned int)SL_IPV4_BYTE(pEventData->Ip,3), - (unsigned int)SL_IPV4_BYTE(pEventData->Ip,2), - (unsigned int)SL_IPV4_BYTE(pEventData->Ip,1), - (unsigned int)SL_IPV4_BYTE(pEventData->Ip,0), - - (unsigned int)SL_IPV4_BYTE(pEventData->Gateway,3), - (unsigned int)SL_IPV4_BYTE(pEventData->Gateway,2), - (unsigned int)SL_IPV4_BYTE(pEventData->Gateway,1), - (unsigned int)SL_IPV4_BYTE(pEventData->Gateway,0)); - #endif - CC3220SFInterface::cc3200sf_wifi_instance->_ip_set_sem.release(); - } - break; - - case SL_NETAPP_EVENT_IPV6_ACQUIRED: - { - uint32_t i = 0; - - printf("\n\r[NETAPP EVENT] IP Acquired: IPv6="); - - for(i = 0; i < 3 ; i++) - { - printf("%04x:%04x:\n", ((unsigned int)(pNetAppEvent->Data.IpAcquiredV6.Ip[i]>>16) & 0xffff), (unsigned int)pNetAppEvent->Data.IpAcquiredV6.Ip[i] & 0xffff); - } - - printf("%04x:%04x\n", ((unsigned int)(pNetAppEvent->Data.IpAcquiredV6.Ip[3]>>16) & 0xffff), (unsigned int)pNetAppEvent->Data.IpAcquiredV6.Ip[3] & 0xffff); - } - break; - - case SL_NETAPP_EVENT_DHCPV4_LEASED: - { - printf("\n\r[NETAPP EVENT] IP Leased to Client: IP=%d.%d.%d.%d \n\r", - (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,3), (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,2), - (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,1), (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,0)); - } - break; - - case SL_NETAPP_EVENT_DHCPV4_RELEASED: - { - printf("\n\r[NETAPP EVENT] IP is released.\n\r"); - } - break; - - default: - { - printf("\n\r[NETAPP EVENT] Unexpected event [0x%x] \n\r", (unsigned int)pNetAppEvent->Id); - } - break; - } -} - -/*! - \brief SimpleLinkHttpServerEventHandler - - This handler gets called whenever a HTTP event is reported - by the NWP internal HTTP server. - - \param pHttpEvent - pointer to http event data. - - \param pHttpEvent - pointer to http response. - - \return void - - \note For more information, please refer to: user.h in the porting - folder of the host driver and the CC3120/CC3220 NWP programmer's - guide (SWRU455) chapter 9. - -*/ -void SimpleLinkHttpServerEventHandler(SlNetAppHttpServerEvent_t *pHttpEvent, - SlNetAppHttpServerResponse_t *pHttpResponse) -{ - /* Unused in this application */ -} - -/*! - \brief SimpleLinkGeneralEventHandler - - This handler gets called whenever a general error is reported - by the NWP / Host driver. Since these errors are not fatal, - application can handle them. - - \param pDevEvent - pointer to device error event. - - \return void - - \note For more information, please refer to: user.h in the porting - folder of the host driver and the CC3120/CC3220 NWP programmer's - guide (SWRU455) section 17.9. - -*/ -void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent) -{ - if(!pDevEvent) - { - return; - } - /* - Most of the general errors are not FATAL are are to be handled - appropriately by the application - */ - printf("\n\r[GENERAL EVENT] - ID=[%d] Sender=[%d]\n\n", - pDevEvent->Data.Error.Code, - pDevEvent->Data.Error.Source); -} - -/*! - \brief SimpleLinkSockEventHandler - - This handler gets called whenever a socket event is reported - by the NWP / Host driver. - - \param SlSockEvent_t - pointer to socket event data. - - \return void - - \note For more information, please refer to: user.h in the porting - folder of the host driver and the CC3120/CC3220 NWP programmer's - guide (SWRU455) section 7.6. - -*/ -void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) -{ - #if HANDLER_TRACE_ENABLE == 1 - printf("\n\r[INFO] - event detected: " - "Event=%d, AbortData=0x%x\n\r", - (unsigned int)pSock->Event, - (unsigned int)pSock->SocketAsyncEvent.SockTxFailData.Status); - #endif - -} - -/*! - \brief SimpleLinkFatalErrorEventHandler - - This handler gets called whenever a socket event is reported - by the NWP / Host driver. After this routine is called, the user's - application must restart the device in order to recover. - - \param slFatalErrorEvent - pointer to fatal error event. - - \return void - - \note For more information, please refer to: user.h in the porting - folder of the host driver and the CC3120/CC3220 NWP programmer's - guide (SWRU455) section 17.9. - -*/ -void SimpleLinkFatalErrorEventHandler(SlDeviceFatal_t *slFatalErrorEvent) -{ - - switch (slFatalErrorEvent->Id) - { - case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: - { - printf("\n\r[ERROR] - FATAL ERROR: Abort NWP event detected: " - "AbortType=%d, AbortData=0x%x\n\r", - (unsigned int)slFatalErrorEvent->Data.DeviceAssert.Code, - (unsigned int)slFatalErrorEvent->Data.DeviceAssert.Value); - } - break; - - case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: - { - printf("\n\r[ERROR] - FATAL ERROR: Driver Abort detected. \n\r"); - } - break; - - case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: - { - printf("\n\r[ERROR] - FATAL ERROR: No Cmd Ack detected " - "[cmd opcode = 0x%x] \n\r", - (unsigned int)slFatalErrorEvent->Data.NoCmdAck.Code); - } - break; - - case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: - { - printf("\n\r[ERROR] - FATAL ERROR: Sync loss detected n\r"); - } - break; - - case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: - { - printf("\n\r[ERROR] - FATAL ERROR: Async event timeout detected " - "[event opcode =0x%x] \n\r", - (unsigned int)slFatalErrorEvent->Data.CmdTimeout.Code); - } - break; - - default: - printf("\n\r[ERROR] - FATAL ERROR: Unspecified error detected \n\r"); - break; - } -} - -/*! - \brief SimpleLinkNetAppRequestEventHandler - - This handler gets called whenever a NetApp event is reported - by the NWP / Host driver. User can write he's logic to handle - the event here. - - \param pNetAppRequest - Pointer to NetApp request structure. - - \param pNetAppResponse - Pointer to NetApp request Response. - - \note For more information, please refer to: user.h in the porting - folder of the host driver and the CC3120/CC3220 NWP programmer's - guide (SWRU455) section 17.9. - - \return void - -*/ -void SimpleLinkNetAppRequestEventHandler(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse) -{ - /* Unused in this application */ -} - -/*! - \brief SimpleLinkNetAppRequestMemFreeEventHandler - - This handler gets called whenever the NWP is done handling with - the buffer used in a NetApp request. This allows the use of - dynamic memory with these requests. - - \param pNetAppRequest - Pointer to NetApp request structure. - - \param pNetAppResponse - Pointer to NetApp request Response. - - \note For more information, please refer to: user.h in the porting - folder of the host driver and the CC3120/CC3220 NWP programmer's - guide (SWRU455) section 17.9. - - \return void - -*/ -void SimpleLinkNetAppRequestMemFreeEventHandler(uint8_t *buffer) -{ - /* Unused in this application */ -} - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c deleted file mode 100644 index ccdd4f81476..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c +++ /dev/null @@ -1,81 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if DEVICE_FLASH - -#include "stdbool.h" -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "flash_api.h" -#include "ti/devices/cc32xx/driverlib/flash.h" - -#define CC3200_FLASH_SECTOR_SIZE 0x800 -#define CC3200_FLASH_PAGE_SIZE 0x4 -#define CC3200_FLASH_START_ADDRESS 0x01000000 -#define CC3200_FLASH_SIZE (1024*1024) - -int32_t flash_init(flash_t *obj) -{ - return 0; -} - -int32_t flash_free(flash_t *obj) -{ - //FlashDisable(); - return 0; -} - -int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - return FlashErase(address); -} - -int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - return FlashProgram((unsigned long *)data, (unsigned long)address, - (unsigned long)size); -} - -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ - if ((address >= CC3200_FLASH_START_ADDRESS) && address < (CC3200_FLASH_START_ADDRESS + CC3200_FLASH_SIZE)) { - return CC3200_FLASH_SECTOR_SIZE; - } else { - return MBED_FLASH_INVALID_SIZE; - } -} - -uint32_t flash_get_page_size(const flash_t *obj) -{ - return CC3200_FLASH_PAGE_SIZE; -} - -uint32_t flash_get_start_address(const flash_t *obj) -{ - return CC3200_FLASH_START_ADDRESS; -} - -uint32_t flash_get_size(const flash_t *obj) -{ - return CC3200_FLASH_SIZE; -} - -uint8_t flash_get_erase_value(const flash_t *obj) -{ - (void)obj; - - return 0xFF; -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c deleted file mode 100644 index dbb449eb194..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c +++ /dev/null @@ -1,101 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "mbed_error.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/driverlib/pin.h" -#include "ti/devices/cc32xx/driverlib/gpio.h" -#include "ti/devices/cc32xx/inc/hw_ints.h" -#include "ti/devices/cc32xx/driverlib/prcm.h" - - -uint32_t gpio_set(PinName pin) -{ - pin_function(pin, 0); - return (1); -} - -// function to initialise the gpio pin -// this links the board control bits for each pin -// with the object created for the pin -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO); - obj->baseAddr = gpio_base; - obj->pin_mask = 1 << (pinmap_find_function(pin, PinMap_GPIO) % 8); - - // determine PRCM GPIO CLOCK index - unsigned short prcm_peripheral = 0; - switch (gpio_base) { - case CC3220SF_GPIOA0_BASE: - prcm_peripheral = PRCM_GPIOA0; - break; - case CC3220SF_GPIOA1_BASE: - prcm_peripheral = PRCM_GPIOA1; - break; - case CC3220SF_GPIOA2_BASE: - prcm_peripheral = PRCM_GPIOA2; - break; - case CC3220SF_GPIOA3_BASE: - prcm_peripheral = PRCM_GPIOA3; - break; - default: - break; - } - - // initialize GPIO PORT clock - PRCMPeripheralClkEnable(prcm_peripheral, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); - - // wait for GPIO clock to settle - while (!PRCMPeripheralStatusGet(prcm_peripheral)); -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - obj->mode = mode; - //set the pin mux to be GPIO which is PIN MODE 0 - pin_mode(obj->pin, mode); - PinModeSet(obj->pin, PIN_MODE_0); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - obj->dir = direction; - GPIODirModeSet(obj->baseAddr, obj->pin_mask, direction); -} - -int gpio_is_connected(const gpio_t *obj) -{ - return (obj->pin == NC); -} - -void gpio_write(gpio_t *obj, int value) -{ - GPIOPinWrite(obj->baseAddr, obj->pin_mask, value * obj->pin_mask); -} - -int gpio_read(gpio_t *obj) -{ - return (GPIOPinRead(obj->baseAddr, obj->pin_mask) != 0); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c deleted file mode 100644 index 487450fbf81..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c +++ /dev/null @@ -1,182 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "cmsis.h" -#include "PeripheralPins.h" - -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/inc/hw_gpio.h" -#include "ti/devices/cc32xx/driverlib/gpio.h" -#include "ti/devices/cc32xx/inc/hw_ints.h" -#include "ti/devices/cc32xx/inc/hw_memmap.h" -#include "ti/devices/cc32xx/inc/hw_common_reg.h" - -#define CHANNEL_NUM 32 - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(unsigned long gpio_port) -{ - - uint32_t chan_base = 0; - switch ((unsigned long) gpio_port) { - case CC3220SF_GPIOA0_BASE: - chan_base = 0; - break; - case CC3220SF_GPIOA1_BASE: - chan_base = 8; - break; - case CC3220SF_GPIOA2_BASE: - chan_base = 16; - break; - case CC3220SF_GPIOA3_BASE: - chan_base = 24; - break; - default: - return; - break; - } - - uint16_t pin_mask = 0x01; - for (int i = 0; i < 8; i++) { - - //checking for interrupt on each GPIO pin - if ((GPIOIntStatus((unsigned long)gpio_port, true) & pin_mask) > 0) { - gpio_irq_event event = (gpio_irq_event)GPIOIntTypeGet((unsigned long)gpio_port, pin_mask); - if (event == GPIO_RISING_EDGE) { - event = IRQ_RISE; - } else if (event == GPIO_FALLING_EDGE) { - event = IRQ_FALL; - } - - if (channel_ids[chan_base + i] == 0) { - continue; - } - - irq_handler(channel_ids[chan_base + i], (gpio_irq_event)event); - - } - GPIOIntClear((unsigned long)gpio_port, pin_mask); - pin_mask = pin_mask << 1; - } - -} - -void gpio_irqA0(void) -{ - handle_interrupt_in(CC3220SF_GPIOA0_BASE); -} - -void gpio_irqA1(void) -{ - handle_interrupt_in(CC3220SF_GPIOA1_BASE); -} - -void gpio_irqA2(void) -{ - handle_interrupt_in(CC3220SF_GPIOA2_BASE); -} - -void gpio_irqA3(void) -{ - handle_interrupt_in(CC3220SF_GPIOA3_BASE); -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - if (pin == NC) { - return -1; - } - - - - unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO); - unsigned long ch_num = pinmap_find_function(pin, PinMap_GPIO); - obj->baseAddr = gpio_base; - obj->pin = pin; - obj->ch = ch_num; - obj->pin_mask = 1 << (ch_num % 8); - irq_handler = handler; - uint32_t vector = (uint32_t)gpio_irqA0; - switch (gpio_base) { - case CC3220SF_GPIOA0_BASE: - vector = (uint32_t)gpio_irqA0; - obj->irq_offset = INT_GPIOA0_IRQn; - break; - case CC3220SF_GPIOA1_BASE: - vector = (uint32_t)gpio_irqA1; - obj->irq_offset = INT_GPIOA1_IRQn; - break; - case CC3220SF_GPIOA2_BASE: - vector = (uint32_t)gpio_irqA2; - obj->irq_offset = INT_GPIOA2_IRQn; - break; - case CC3220SF_GPIOA3_BASE: - vector = (uint32_t)gpio_irqA3; - obj->irq_offset = INT_GPIOA3_IRQn; - break; - default: - break; - } - channel_ids[obj->ch] = id; - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_offset); - NVIC_DisableIRQ((IRQn_Type)obj->irq_offset); - NVIC_SetVector((IRQn_Type)obj->irq_offset, vector); - NVIC_EnableIRQ((IRQn_Type)obj->irq_offset); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - channel_ids[obj->ch] = 0; - GPIOIntDisable(obj->baseAddr, obj->pin_mask); -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - - if (enable) { - GPIOIntEnable(obj->baseAddr, obj->pin_mask); - } else { - GPIOIntDisable(obj->baseAddr, obj->pin_mask); - } - - switch (event) { - case IRQ_RISE: - GPIOIntTypeSet(obj->baseAddr, obj->pin_mask, GPIO_RISING_EDGE); - break; - case IRQ_FALL: - GPIOIntTypeSet(obj->baseAddr, obj->pin_mask, GPIO_FALLING_EDGE); - break; - default: - break; - } -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - GPIOIntEnable(obj->baseAddr, obj->pin_mask); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - GPIOIntDisable(obj->baseAddr, obj->pin_mask); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c deleted file mode 100644 index 26469d955ff..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c +++ /dev/null @@ -1,114 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if DEVICE_LPTICKER -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/driverlib/prcm.h" - -/******************************************************************************* - * lp_ticker implementation on this target is mapped on top of the sleep clock counter - * that is running in the lowest energy modes. The sleep clock counter is 48b running - * at 32.768KHz. This gives 0.03ms resolution for the low power timer which requires - * millisecond accuracy. - * - ******************************************************************************/ - -#include "lp_ticker_api.h" -#include "mbed_critical.h" - -// There's actually 48b but Mbed OS supports 32b only. -#define RTC_BITS 32u -#define RTC_FREQ 32768u - -static bool rtc_inited = false; - -const ticker_info_t *lp_ticker_get_info() -{ - static const ticker_info_t info = { - RTC_FREQ, // 32KHz - RTC_BITS // 32 bit counter - }; - return &info; -} - -void lp_ticker_init() -{ - if (PRCMRTCInUseGet() == true) - // When RTC is in use, slow clock counter can't be accessed - { - return; - } - if (!rtc_inited) { - NVIC_SetVector(INT_PRCM_IRQn, (uint32_t)lp_ticker_irq_handler); - NVIC_ClearPendingIRQ(INT_PRCM_IRQn); - NVIC_EnableIRQ(INT_PRCM_IRQn); - PRCMIntStatus(); // Read clears pending interrupts - rtc_inited = true; - } else { - PRCMIntDisable(PRCM_INT_SLOW_CLK_CTR); - } -} - -void lp_ticker_free() -{ - /* Disable the RTC if it was inited and is no longer in use by anyone. */ - if (rtc_inited) { - NVIC_DisableIRQ(INT_PRCM_IRQn); - rtc_inited = false; - } -} - -void lp_ticker_set_interrupt(timestamp_t timestamp) -{ - // timestamp is defined as 32b. - core_util_critical_section_enter(); - // Clear pending interrupt - PRCMIntStatus(); - PRCMSlowClkCtrMatchSet(timestamp); - PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR); - core_util_critical_section_exit(); -} - -void lp_ticker_fire_interrupt(void) -{ - core_util_critical_section_enter(); - NVIC_SetPendingIRQ(INT_PRCM_IRQn); - core_util_critical_section_exit(); -} - -void lp_ticker_disable_interrupt() -{ - PRCMIntDisable(PRCM_INT_SLOW_CLK_CTR); -} - -void lp_ticker_clear_interrupt() -{ - PRCMIntStatus(); // Read clears pending interrupts -} - -timestamp_t lp_ticker_read() -{ - // Read forever until reaching two of the same - volatile unsigned long long read_previous, read_current; - do { - read_previous = PRCMSlowClkCtrFastGet(); - read_current = PRCMSlowClkCtrFastGet(); - } while (read_previous != read_current); - - return read_current; -} - -#endif /* DEVICE_LPTICKER */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h deleted file mode 100644 index 83d5766f865..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h +++ /dev/null @@ -1,179 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "stdbool.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "serial_object.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - unsigned long baseAddr; - PinName pin; - PinMode mode; - PinDirection dir; - unsigned long pin_mask; -} gpio_t; - -struct gpio_irq_s { - unsigned long baseAddr; - uint32_t port; - PinName pin; - uint32_t ch; - unsigned long pin_mask; - unsigned long irq_offset; -}; - -struct port_s { - unsigned long baseAddr; - unsigned long peripheralId; - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - uint32_t period_us; - float duty_percent; - void *handle; - PWMName pwm; -}; - -struct serial_s { - CC3220SF_UART_TypeDef *uart; - int index; - uint32_t baudRate; /*!< Baud rate for UART */ - unsigned int baseAddr; /*! UART Peripheral's base address */ - unsigned int intNum; /*! UART Peripheral's interrupt vector */ - unsigned int powerMgrId; /* Determined from base address */ - unsigned long peripheralId; /* Value that can be passed to PRCM functions */ - UART_LEN dataLength; /* Data length for UART */ - UART_STOP stopBits; /* Stop bits for UART */ - UART_PAR parityType; /* Parity bit type for UART */ -}; - -struct analogin_s { - PinName pin; - unsigned long adc_ch; -}; - -struct trng_s { - uint32_t placeholder; -}; - -struct flash_s { - uint32_t placeholder; -}; - -typedef struct spi_clock_config_s { - - //! \param ulSPIClk is the rate of clock supplied to the SPI module. - uint32_t ulSPIClk; - - //! \param ulBitRate is the desired bit rate.(master mode) - uint32_t ulBitRate; - - //! - //! The SPI module can operate in either master or slave mode. The parameter - //! \e ulMode can be one of the following - //! -\b SPI_MODE_MASTER - //! -\b SPI_MODE_SLAVE - uint32_t ulMode; - - //! - //! The SPI module supports 4 sub modes based on SPI clock polarity and phase. - //! - //! 
-    //! Polarity Phase  Sub-Mode
-    //!   0       0        0
-    //!   0       1        1
-    //!   1       0        2
-    //!   1       1        3
-    //!
- - //! Required sub mode can be select by setting \e ulSubMode parameter to one - //! of the following - //! - \b SPI_SUB_MODE_0 - //! - \b SPI_SUB_MODE_1 - //! - \b SPI_SUB_MODE_2 - //! - \b SPI_SUB_MODE_3 - uint32_t ulSubMode; - - //! The parameter \e ulConfig is logical OR of five values: the word length, - //! active level for chip select, software or hardware controlled chip select, - //! 3 or 4 pin mode and turbo mode. - //! mode. - //! - //! SPI support 8, 16 and 32 bit word lengths defined by:- - //! - \b SPI_WL_8 - //! - \b SPI_WL_16 - //! - \b SPI_WL_32 - //! - //! Active state of Chip Select can be defined by:- - //! - \b SPI_CS_ACTIVELOW - //! - \b SPI_CS_ACTIVEHIGH - //! - //! SPI chip select can be configured to be controlled either by hardware or - //! software:- - //! - \b SPI_SW_CS - //! - \b SPI_HW_CS - //! - //! The module can work in 3 or 4 pin mode defined by:- - //! - \b SPI_3PIN_MODE - //! - \b SPI_4PIN_MODE - //! - //! Turbo mode can be set on or turned off using:- - //! - \b SPI_TURBO_MODE_ON - //! - \b SPI_TURBO_MODE_OFF - uint32_t ulConfig; -} spi_clock_config_t; - -struct spi_s { - /*! SPI module number */ - uint32_t instance; - - /*! SPICC32XXDMA Peripheral's base address */ - uint32_t baseAddr; - - /*! SPI Word lengh */ - uint32_t word_length; - - /*! SPI clock configuration */ - spi_clock_config_t clock_config; - - /*! Is clock update needed */ - bool clock_update; - - /*! Is CS controlled by GPIO */ - bool cs_control_gpio; - -#if DEVICE_SPI_ASYNCH - uint32_t handler; - uint32_t mask; - uint32_t event; -#endif -}; -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c deleted file mode 100644 index 6c584fc90b4..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c +++ /dev/null @@ -1,65 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "mbed_error.h" - -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/inc/hw_memmap.h" -#include "ti/devices/cc32xx/inc/hw_ocp_shared.h" -#include "ti/devices/cc32xx/driverlib/pin.h" - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int function) -{ - MBED_ASSERT(pin != (PinName)NC); -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - switch (mode) { - case PullNone: - PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); - break; - case PullUp: - PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PU); - break; - case PullDown: - PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PD); - break; - case OpenDrain: - PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD); - break; - case OpenDrainPullUp: - PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PU); - break; - case OpenDrainPullDown: - PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PD); - break; - case Analog: - PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_ANALOG); - break; - default: - PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); - break; - } -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c deleted file mode 100644 index 64d1cca8883..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c +++ /dev/null @@ -1,130 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "PeripheralPins.h" - -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/driverlib/pin.h" -#include "ti/devices/cc32xx/driverlib/gpio.h" -#include "ti/devices/cc32xx/inc/hw_ints.h" -#include "ti/devices/cc32xx/driverlib/prcm.h" - -#define NUM_PORTS 4 -#define NUM_PINS_PER_PORT 8 -#define PORT_MASK 0x3 - -static const uint8_t pinTable[] = { - /* 00 01 02 03 04 05 06 07 */ - PIN_50, PIN_55, PIN_57, PIN_58, PIN_59, PIN_60, PIN_61, PIN_62, - /* 08 09 10 11 12 13 14 15 */ - PIN_63, PIN_64, PIN_01, PIN_02, PIN_03, PIN_04, PIN_05, PIN_06, - /* 16 17 18 19 20 21 22 23 */ - PIN_07, PIN_08, PIN_XX, PIN_XX, PIN_XX, PIN_XX, PIN_15, PIN_16, - /* 24 25 26 27 28 29 30 31 */ - PIN_17, PIN_21, PIN_29, PIN_30, PIN_18, PIN_20, PIN_53, PIN_45, - /* 32 */ - PIN_52 -}; - -const uint16_t PortPinTypes[] = { - PIN_TYPE_STD, /* GPIO_CFG_IN_NOPULL */ - PIN_TYPE_STD_PU, /* GPIO_CFG_IN_PU */ - PIN_TYPE_STD_PD, /* GPIO_CFG_IN_PD */ - PIN_TYPE_OD, /* GPIO_CFG_OUT_OD_NOPULL */ - PIN_TYPE_OD_PU, /* GPIO_CFG_OUT_OD_PU */ - PIN_TYPE_OD_PD, /* GPIO_CFG_OUT_OD_PD */ - (uint16_t)PIN_TYPE_ANALOG // Revisit this, PIN_TYPE_ANALOG gets truncated to 16b -}; - -PinName port_pin(PortName port, int pin_n) -{ - int gpio_num = (port * 8) + pin_n; - PinName pin = (PinName)pinTable[gpio_num]; - return pin; -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - obj->port = port; - obj->mask = mask; - - switch (port) { - case Port0: - obj->baseAddr = CC3220SF_GPIOA0_BASE; - obj->peripheralId = PRCM_GPIOA0; - break; - case Port1: - obj->baseAddr = CC3220SF_GPIOA1_BASE; - obj->peripheralId = PRCM_GPIOA1; - break; - case Port2: - obj->baseAddr = CC3220SF_GPIOA2_BASE; - obj->peripheralId = PRCM_GPIOA2; - break; - case Port3: - obj->baseAddr = CC3220SF_GPIOA3_BASE; - obj->peripheralId = PRCM_GPIOA3; - break; - } - - // initialize GPIO PORT clock - PRCMPeripheralClkEnable(obj->peripheralId, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); - // wait for GPIO clock to settle - while (!PRCMPeripheralStatusGet(obj->peripheralId)); - - for (int i = 0; i < 8; i++) { - if (obj->mask & (1 << i)) { - PinName pin = port_pin(obj->port, i); - PinModeSet(pin, PIN_MODE_0); - pin_mode(pin, PullNone); - } - } - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) -{ - for (int i = 0; i < 8; i++) { - if (obj->mask & (1 << i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - switch (dir) { - case PIN_INPUT: - GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_IN); - break; - case PIN_OUTPUT: - GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_OUT); - break; - } -} - -void port_write(port_t *obj, int value) -{ - GPIOPinWrite(obj->baseAddr, obj->mask, value); -} - -int port_read(port_t *obj) -{ - return (int)(GPIOPinRead(obj->baseAddr, obj->mask)); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c deleted file mode 100644 index 01eeef57df5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c +++ /dev/null @@ -1,138 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -#include "ti/drivers/pwm/PWMTimerCC32XX.h" -#include "ti/drivers/PWM.h" -#include "CC3220SF_LAUNCHXL.h" - -extern const PWM_Config PWM_config[]; - -void pwmout_init(pwmout_t *obj, PinName pin) -{ - PWM_Params pwmParams; - int pwmIndex = CC3220SF_LAUNCHXL_PWMCOUNT; - - PWM_init(); - - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - obj->pwm = pwm; - - switch (pin) { - case PIN_01: - pwmIndex = CC3220SF_LAUNCHXL_PWM6; - break; - - case PIN_02: - pwmIndex = CC3220SF_LAUNCHXL_PWM7; - break; - - case PIN_17: - pwmIndex = CC3220SF_LAUNCHXL_PWM0; - break; - - case PIN_19: - pwmIndex = CC3220SF_LAUNCHXL_PWM3; - break; - - case PIN_21: - pwmIndex = CC3220SF_LAUNCHXL_PWM2; - break; - - case PIN_64: - pwmIndex = CC3220SF_LAUNCHXL_PWM5; - break; - - default: - while (1); - } - - obj->handle = (void *)&PWM_config[pwmIndex]; - - // Initialize the PWM parameters - PWM_Params_init(&pwmParams); - - obj->duty_percent = PWM_DEFAULT_DUTY_PERCENT; - obj->period_us = PWM_DEFAULT_PERIOD_US; - - if (PWM_open(pwmIndex, &pwmParams)) { - PWM_start((PWM_Handle)obj->handle); - } else { - while (1); - } -} - -void pwmout_free(pwmout_t *obj) -{ - PWM_stop((PWM_Handle)obj->handle); - PWM_close((PWM_Handle)obj->handle); -} - -void pwmout_write(pwmout_t *obj, float value) -{ - PWM_setDuty((PWM_Handle)obj->handle, value * 100); - obj->duty_percent = value; -} - -float pwmout_read(pwmout_t *obj) -{ - return (obj->duty_percent); -} - -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000 * 1000); -} - -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t *obj, int us) -{ - PWM_setPeriod((PWM_Handle)obj->handle, us); - obj->period_us = us; -} - -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - if (obj->period_us) { - float value = (float)us / (float)obj->period_us; - pwmout_write(obj, value); - } -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c deleted file mode 100644 index 81d4ad8207f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c +++ /dev/null @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "rtc_api.h" - -#if DEVICE_RTC -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/driverlib/prcm.h" - -void rtc_init(void) -{ - static bool rtc_initialized = false; - if (!rtc_initialized) { - if (!PRCMRTCInUseGet()) { - PRCMRTCInUseSet(); - } - rtc_initialized = true; - } -} - -void rtc_free(void) -{ -} - -int rtc_isenabled(void) -{ - return PRCMRTCInUseGet(); -} - -time_t rtc_read(void) -{ - unsigned long ulSecs = 0; - unsigned short usMsec = 0; - PRCMRTCGet(&ulSecs, &usMsec); - return ulSecs; -} - -void rtc_write(time_t t) -{ - PRCMRTCSet(t, 0); -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c deleted file mode 100644 index 4b2da425fbc..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c +++ /dev/null @@ -1,437 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include -#include -#include -#include -#include "mbed_assert.h" - -#include "serial_api.h" -#include "serial_object.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_api.h" -#include "PeripheralPins.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define UART_NUM 2 - -static const uint32_t dataLength[] = { - UART_CONFIG_WLEN_5, /* UART_LEN_5 */ - UART_CONFIG_WLEN_6, /* UART_LEN_6 */ - UART_CONFIG_WLEN_7, /* UART_LEN_7 */ - UART_CONFIG_WLEN_8 /* UART_LEN_8 */ -}; - -static const uint32_t stopBits[] = { - UART_CONFIG_STOP_ONE, /* UART_STOP_ONE */ - UART_CONFIG_STOP_TWO /* UART_STOP_TWO */ -}; - -static const uint32_t parityType[] = { - UART_CONFIG_PAR_NONE, /* UART_PAR_NONE */ - UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN */ - UART_CONFIG_PAR_ODD, /* UART_PAR_ODD */ - UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO */ - UART_CONFIG_PAR_ONE /* UART_PAR_ONE */ -}; - -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -struct serial_global_data_s { - uint32_t serial_irq_id; - gpio_t sw_rts, sw_cts; - uint8_t count, rx_irq_set_flow, rx_irq_set_api; -}; - -static struct serial_global_data_s uart_data[UART_NUM]; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - - // determine the UART to use - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart != NC); - - obj->uart = (CC3220SF_UART_TypeDef *)uart; - - // Set default values for UART - obj->dataLength = UART_LEN_8; - obj->stopBits = UART_STOP_ONE; - obj->parityType = UART_PAR_NONE; - - switch (uart) { - case UART_0: { - obj->index = 0; - obj->baseAddr = CC3220SF_UARTA0_BASE; - obj->powerMgrId = 12; /*!< Resource ID: UART 0 */ - obj->intNum = INT_UARTA0_IRQn; - obj->peripheralId = PRCM_UARTA0; - } - break; - case UART_1: { - obj->index = 1; - obj->baseAddr = CC3220SF_UARTA1_BASE; - obj->powerMgrId = 13; /*!< Resource ID: UART 1 */ - obj->intNum = INT_UARTA1_IRQn; - obj->peripheralId = PRCM_UARTA1; - } - break; - } - - PRCMPeripheralClkEnable(obj->peripheralId, PRCM_RUN_MODE_CLK); - - // Pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - MAP_PinTypeUART(tx, pinmap_function(tx, PinMap_UART_TX)); - MAP_PinTypeUART(rx, pinmap_function(rx, PinMap_UART_RX)); - - MAP_UARTEnable(obj->baseAddr); - - // Set default baud rate and format - serial_baud(obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - // set rx/tx pins in PullUp mode - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - /* Set flow control */ - uart_data[obj->index].sw_rts.pin = NC; - uart_data[obj->index].sw_cts.pin = NC; - serial_set_flow_control(obj, FlowControlNone, NC, NC); - - is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - uart_data[obj->index].serial_irq_id = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudRate = baudrate; - - MAP_UARTConfigSetExpClk(obj->baseAddr, MAP_PRCMPeripheralClockGet(obj->peripheralId), - obj->baudRate, (dataLength[obj->dataLength] | - stopBits[obj->stopBits] | parityType[obj->parityType])); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); - - stop_bits -= 1; - data_bits -= 5; - - switch (parity) { - case ParityNone: - obj->parityType = UART_PAR_NONE; - break; - case ParityOdd : - obj->parityType = UART_PAR_ODD; - break; - case ParityEven: - obj->parityType = UART_PAR_EVEN; - break; - case ParityForced1: - obj->parityType = UART_PAR_ONE; - break; - case ParityForced0: - obj->parityType = UART_PAR_ZERO; - break; - default: - obj->parityType = UART_PAR_NONE; - break; - } - - switch (data_bits) { - case 0: - obj->dataLength = UART_LEN_5; - break; - case 1: - obj->dataLength = UART_LEN_6; - break; - case 2: - obj->dataLength = UART_LEN_7; - break; - case 3: - obj->dataLength = UART_LEN_8; - break; - default: - obj->dataLength = UART_LEN_8; - break; - } - - switch (stop_bits) { - case 0: - obj->stopBits = UART_STOP_ONE; - break; - case 1: - obj->stopBits = UART_STOP_TWO; - break; - default: - obj->stopBits = UART_STOP_ONE; - break; - } - - MAP_UARTConfigSetExpClk(obj->baseAddr, MAP_PRCMPeripheralClockGet(obj->peripheralId), - obj->baudRate, (dataLength[obj->dataLength] | - stopBits[obj->stopBits] | parityType[obj->parityType])); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t intstatus, uint32_t index, CC3220SF_UART_TypeDef *puart) -{ - SerialIrq irq_type; - if (intstatus & UART_INT_TX) { - irq_type = TxIrq; - } else { - irq_type = RxIrq; - } - uint32_t rxErrors = puart->RSR & 0x0000000F; - if (rxErrors) { - puart->ECR = 0; - } - if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) { - gpio_write(&uart_data[index].sw_rts, 1); - // Disable interrupt if it wasn't enabled by other part of the application - if (!uart_data[index].rx_irq_set_api) { - puart->IM &= ~(UART_INT_RX | UART_INT_RT); - } - } - if (uart_data[index].serial_irq_id != 0) { - if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) { - irq_handler(uart_data[index].serial_irq_id, irq_type); - } - } - if (irq_type == TxIrq) { - puart->ICR = UART_INT_TX; // clear TX interrupt - } else { - puart->ICR = UART_INT_RX; // clear RX interrupt - } -} - -void uart0_irq() -{ - uart_irq(CC3220SF_UART0->MIS, 0, (CC3220SF_UART_TypeDef *)CC3220SF_UART0); -} -void uart1_irq() -{ - uart_irq(CC3220SF_UART1->MIS, 1, (CC3220SF_UART_TypeDef *)CC3220SF_UART1); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - uart_data[obj->index].serial_irq_id = id; -} - -void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - /* Clear interrupts */ - uint32_t status = MAP_UARTIntStatus(obj->baseAddr, true); - MAP_UARTIntClear(obj->baseAddr, status); - - switch ((int)obj->uart) { - case UART_0: - irq_n = INT_UARTA0_IRQn; - vector = (uint32_t)&uart0_irq; - break; - case UART_1: - irq_n = INT_UARTA1_IRQn; - vector = (uint32_t)&uart1_irq; - break; - } - - if (enable) { - if (irq == TxIrq) { - MAP_UARTIntEnable(obj->baseAddr, UART_INT_TX); - } else { - MAP_UARTIntEnable(obj->baseAddr, UART_INT_RX); - } - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - } else { - /* Disable IRQ */ - MAP_UARTIntDisable(obj->baseAddr, UART_INT_TX | UART_INT_RX); - NVIC_DisableIRQ(irq_n); - } -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - if (RxIrq == irq) { - uart_data[obj->index].rx_irq_set_api = enable; - } - serial_irq_set_internal(obj, irq, enable); -} - -/*static void serial_flow_irq_set(serial_t *obj, uint32_t enable) -{ - uart_data[obj->index].rx_irq_set_flow = enable; - serial_irq_set_internal(obj, RxIrq, enable); -}*/ - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) -{ - while (!serial_readable(obj)); - return obj->uart->DR; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)); - obj->uart->DR = c; -} - -int serial_readable(serial_t *obj) -{ - return ((obj->uart->FR & UART_FR_RXFE) ? 0 : 1); -} - -int serial_writable(serial_t *obj) -{ - return ((obj->uart->FR & UART_FR_TXFF) ? 0 : 1); -} - -void serial_clear(serial_t *obj) -{ - obj->uart->DR = 0x00; -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - MAP_UARTBreakCtl(obj->baseAddr, true); -} - -void serial_break_clear(serial_t *obj) -{ - MAP_UARTBreakCtl(obj->baseAddr, false); -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - switch (type) { - case FlowControlRTS: - pinmap_pinout(rxflow, PinMap_UART_RTS); - MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_RX); - MAP_UARTModemControlSet(obj->baseAddr, UART_OUTPUT_RTS); - break; - - case FlowControlCTS: - pinmap_pinout(txflow, PinMap_UART_CTS); - MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_TX); - MAP_UARTModemControlClear(obj->baseAddr, UART_OUTPUT_RTS); - break; - - case FlowControlRTSCTS: - pinmap_pinout(rxflow, PinMap_UART_RTS); - pinmap_pinout(txflow, PinMap_UART_CTS); - MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); - MAP_UARTModemControlSet(obj->baseAddr, UART_OUTPUT_RTS); - break; - - case FlowControlNone: - MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_NONE); - MAP_UARTModemControlClear(obj->baseAddr, UART_OUTPUT_RTS); - break; - } -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_object.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_object.h deleted file mode 100644 index a3402ab7576..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_object.h +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_SERIAL_OBJECT_H -#define MBED_SERIAL_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum UART_LEN_ { - UART_LEN_5 = 0, /*!< Data length is 5 bits */ - UART_LEN_6 = 1, /*!< Data length is 6 bits */ - UART_LEN_7 = 2, /*!< Data length is 7 bits */ - UART_LEN_8 = 3 /*!< Data length is 8 bits */ -} UART_LEN; - -typedef enum UART_STOP_ { - UART_STOP_ONE = 0, /*!< One stop bit */ - UART_STOP_TWO = 1 /*!< Two stop bits */ -} UART_STOP; - -typedef enum UART_PAR_ { - UART_PAR_NONE = 0, /*!< No parity */ - UART_PAR_EVEN = 1, /*!< Parity bit is even */ - UART_PAR_ODD = 2, /*!< Parity bit is odd */ - UART_PAR_ZERO = 3, /*!< Parity bit is always zero */ - UART_PAR_ONE = 4 /*!< Parity bit is always one */ -} UART_PAR; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c deleted file mode 100644 index 11e3f5527f5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c +++ /dev/null @@ -1,462 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#if DEVICE_SPI - -#include -#include "hal/spi_api.h" -#include "objects.h" -#include "ti/devices/cc32xx/inc/hw_ints.h" -#include "ti/devices/cc32xx/inc/hw_memmap.h" -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/driverlib/pin.h" -#include "ti/devices/cc32xx/driverlib/rom_map.h" -#include "ti/devices/cc32xx/driverlib/ti_spi_driverlib.h" -#include "ti/devices/cc32xx/driverlib/prcm.h" -#include "PeripheralPins.h" - -#define PIN_MODE_SPI 7 -#define SPI_WL_MASK 0xF80 - -/** - * Brief Reconfigure peripheral. - * - * If the peripheral has changed ownership clear old configuration and - * re-initialize the peripheral with the new settings. - * - * Parameter obj The object - */ -static void spi_configure_driver_instance(spi_t *obj) -{ -#if DEVICE_SPI_ASYNCH - struct spi_s *spi_inst = &obj->spi; -#else - struct spi_s *spi_inst = obj; -#endif - - if (spi_inst->clock_update) { - SPIReset(spi_inst->baseAddr); - SPIConfigSetExpClk(spi_inst->baseAddr, spi_inst->clock_config.ulSPIClk, - spi_inst->clock_config.ulBitRate, spi_inst->clock_config.ulMode, - spi_inst->clock_config.ulSubMode, spi_inst->clock_config.ulConfig); - spi_inst->clock_update = false; - SPIEnable(spi_inst->baseAddr); - } -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -/** Initialize the SPI peripheral - * - * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral - * Parameter obj The SPI object to initialize - * Parameter mosi The pin to use for MOSI - * Parameter miso The pin to use for MISO - * Parameter sclk The pin to use for SCLK - * Parameter ssel The pin to use for SSEL - */ -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ -#if DEVICE_SPI_ASYNCH - struct spi_s *spi_inst = &obj->spi; -#else - struct spi_s *spi_inst = obj; -#endif - - /* Get instance based on requested pins. */ - spi_inst->instance = 1; - spi_inst->baseAddr = GSPI_BASE; - spi_inst->clock_config.ulConfig = SPI_4PIN_MODE; - spi_inst->clock_config.ulConfig |= SPI_HW_CTRL_CS; - spi_inst->clock_config.ulConfig |= SPI_CS_ACTIVELOW; - if (ssel == NC) { - spi_inst->cs_control_gpio = true; - } else { - spi_inst->cs_control_gpio = false; - } - spi_inst->clock_config.ulConfig |= SPI_TURBO_OFF; -#if DEVICE_SPI_ASYNCH - /* Set default values for asynchronous variables. */ - spi_inst->handler = 0; - spi_inst->mask = 0; - spi_inst->event = 0; -#endif - - /* Configure GPIO pin if chip select has been set. */ - MAP_PinTypeSPI((unsigned long) mosi & 0xff, (unsigned long) PIN_MODE_SPI); - MAP_PinTypeSPI((unsigned long) miso & 0xff, (unsigned long) PIN_MODE_SPI); - MAP_PinTypeSPI((unsigned long) sclk & 0xff, (unsigned long) PIN_MODE_SPI); - if (ssel != NC) { - MAP_PinTypeSPI((unsigned long) ssel & 0xff, (unsigned long) PIN_MODE_SPI); - } - spi_inst->clock_update = true; -} - -/** Release a SPI object - * - * TODO: spi_free is currently unimplemented - * This will require reference counting at the C++ level to be safe - * - * Return the pins owned by the SPI object to their reset state - * Disable the SPI peripheral - * Disable the SPI clock - * Parameter obj The SPI object to deinitialize - */ -void spi_free(spi_t *obj) -{ - -} - -/** Configure the SPI format - * - * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. - * The default bit order is MSB. - * Parameter obj The SPI object to configure - * Parameter bits The number of bits per frame - * Parameter mode The SPI mode (clock polarity, phase, and shift direction) - * Parameter slave Zero for master mode or non-zero for slave mode - */ -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - /* SPI module supports 8/16/32 bit transfers. */ - MBED_ASSERT(bits == 8 || bits == 16 || bits == 32); - /* SPI module doesn't support Mbed HAL Slave API. */ - MBED_ASSERT(slave == 0); - -#if DEVICE_SPI_ASYNCH - struct spi_s *spi_inst = &obj->spi; -#else - struct spi_s *spi_inst = obj; -#endif - if ((uint32_t)bits != spi_inst->word_length) { - spi_inst->word_length = bits; - spi_inst->clock_update = true; - } - spi_inst->clock_config.ulConfig &= ~SPI_WL_MASK; - spi_inst->clock_config.ulConfig |= (bits - 1) << 7; - spi_inst->clock_config.ulMode = SPI_MODE_MASTER; - - // TI calls it submode - // SPI_SUB_MODE_0 - clk active high, sampling on the rising edge - // SPI_SUB_MODE_1 - clk active high, sampling on the falling edge - // SPI_SUB_MODE_2 - clk active low, sampling on the falling edge - // SPI_SUB_MODE_3 - clk active low, sampling on the rising edge - - /* Convert Mbed HAL mode to TI mode. */ - - if (mode == 0) { - if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_0) { - spi_inst->clock_update = true; - } - spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_0; - } else if (mode == 1) { - if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_1) { - spi_inst->clock_update = true; - } - spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_1; - } else if (mode == 2) { - if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_2) { - spi_inst->clock_update = true; - } - spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_2; - } else if (mode == 3) { - if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_3) { - spi_inst->clock_update = true; - } - spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_3; - } - spi_configure_driver_instance(spi_inst); -} - -/** Set the SPI baud rate - * - * Actual frequency may differ from the desired frequency due to available dividers and bus clock - * Configures the SPI peripheral's baud rate - * Parameter obj The SPI object to configure - * Parameter hz The baud rate in Hz - */ -void spi_frequency(spi_t *obj, int hz) -{ -#if DEVICE_SPI_ASYNCH - struct spi_s *spi_inst = &obj->spi; -#else - struct spi_s *spi_inst = obj; -#endif - - spi_inst->clock_config.ulSPIClk = PRCMPeripheralClockGet(PRCM_GSPI); - if (spi_inst->clock_config.ulBitRate != (uint32_t)hz) { - spi_inst->clock_update = true; - spi_inst->clock_config.ulBitRate = hz; - } - spi_configure_driver_instance(spi_inst); -} - -/** Write a byte out in master mode and receive a value - * - * Parameter obj The SPI peripheral to use for sending - * Parameter value The value to send - * Return Returns the value received during send - */ -int spi_master_write(spi_t *obj, int value) -{ -#if DEVICE_SPI_ASYNCH - struct spi_s *spi_inst = &obj->spi; -#else - struct spi_s *spi_inst = obj; -#endif - - uint32_t data_read = 0; - - /* Configure peripheral if necessary. */ - spi_configure_driver_instance(obj); - - if (!spi_inst->cs_control_gpio) { - SPICSEnable(spi_inst->baseAddr); - } - /* Transfer a data word. */ - SPIDataPut(spi_inst->baseAddr, value); - SPIDataGet(spi_inst->baseAddr, (unsigned long *)&data_read); - if (!spi_inst->cs_control_gpio) { - SPICSDisable(spi_inst->baseAddr); - } - return data_read & ((1 << spi_inst->word_length) - 1); -} - -/** Write a block out in master mode and receive a value - * - * The total number of bytes sent and received will be the maximum of - * tx_length and rx_length. The bytes written will be padded with the - * value 0xff. - * - * Parameter obj The SPI peripheral to use for sending - * Parameter tx_buffer Pointer to the byte-array of data to write to the device - * Parameter tx_length Number of bytes to write, may be zero - * Parameter rx_buffer Pointer to the byte-array of data to read from the device - * Parameter rx_length Number of bytes to read, may be zero - * Parameter write_fill Default data transmitted while performing a read - * @returns - * The number of bytes written and read from the device. This is - * maximum of tx_length and rx_length. - */ -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) -{ -#if DEVICE_SPI_ASYNCH - struct spi_s *spi_inst = &obj->spi; -#else - struct spi_s *spi_inst = obj; -#endif - - int i, spi_words = 0, cs_flags = 0;; - - /* Configure peripheral if necessary. */ - spi_configure_driver_instance(obj); - - if (tx_length >= rx_length) { - if (spi_inst->word_length == 16) { - spi_words = (tx_length >> 1); - } else if (spi_inst->word_length == 32) { - spi_words = (tx_length >> 2); - } else if (spi_inst->word_length == 8) { - spi_words = tx_length; - } - - unsigned char *rx_temp = malloc(tx_length); - SPITransfer(spi_inst->baseAddr, (unsigned char *)tx_buffer, - (unsigned char *)rx_temp, (unsigned long) spi_words, - SPI_CS_ENABLE | SPI_CS_DISABLE); - // Copy the desired data from temp_rx - for (i = 0; i < rx_length; i ++) { - rx_buffer[i] = rx_temp[i]; - } - free(rx_temp); - return (tx_length); - } else // tx_length < rx_length - // Copy the data from tx_buffer to a temp buffer and fill the the rest of the tx_buffer with write_fill) - { - if (spi_inst->word_length == 16) { - spi_words = (rx_length >> 1); - } else if (spi_inst->word_length == 32) { - spi_words = (rx_length >> 2); - } else if (spi_inst->word_length == 8) { - spi_words = rx_length; - } - - unsigned char *tx_temp = malloc(rx_length); - for (i = 0; i < tx_length; i ++) { - tx_temp[i] = tx_buffer[i]; - } - for (i = tx_length; i < rx_length; i ++) { - tx_temp[i] = write_fill; - } - if (!spi_inst->cs_control_gpio) { - cs_flags = SPI_CS_ENABLE | SPI_CS_DISABLE; - } - SPITransfer(spi_inst->baseAddr, (unsigned char *)tx_temp, - (unsigned char *)rx_buffer, (unsigned long) spi_words, - cs_flags); - free(tx_temp); - return rx_length; - } - -} - -/** Checks if the specified SPI peripheral is in use - * - * Parameter obj The SPI peripheral to check - * Return non-zero if the peripheral is currently transmitting - */ -int spi_busy(spi_t *obj) -{ - /* Legacy API call. Always return zero. */ - return 0; -} - -/** Get the module number - * - * Parameter obj The SPI peripheral to check - * Return The module number - */ -uint8_t spi_get_module(spi_t *obj) -{ -#if DEVICE_SPI_ASYNCH - struct spi_s *spi_inst = &obj->spi; -#else - struct spi_s *spi_inst = obj; -#endif - - return spi_inst->instance; -} - -#if DEVICE_SPISLAVE - -/** Check if a value is available to read - * - * Parameter obj The SPI peripheral to check - * Return non-zero if a value is available - */ -int spi_slave_receive(spi_t *obj) -{ - return 0; -} - -/** Get a received value out of the SPI receive buffer in slave mode - * - * Blocks until a value is available - * Parameter obj The SPI peripheral to read - * Return The value received - */ -int spi_slave_read(spi_t *obj) -{ - return 0; -} - -/** Write a value to the SPI peripheral in slave mode - * - * Blocks until the SPI peripheral can be written to - * Parameter obj The SPI peripheral to write - * Parameter value The value to write - */ -void spi_slave_write(spi_t *obj, int value) -{ - return; -} - -#endif - -#if DEVICE_SPI_ASYNCH - -/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff - * - * Parameter obj The SPI object that holds the transfer information - * Parameter tx The transmit buffer - * Parameter tx_length The number of bytes to transmit - * Parameter rx The receive buffer - * Parameter rx_length The number of bytes to receive - * Parameter bit_width The bit width of buffer words - * Parameter event The logical OR of events to be registered - * Parameter handler SPI interrupt handler - * Parameter hint A suggestion for how to use DMA with this transfer - */ -void spi_master_transfer(spi_t *obj, - const void *tx, - size_t tx_length, - void *rx, - size_t rx_length, - uint8_t bit_width, - uint32_t handler, - uint32_t mask, - DMAUsage hint) -{ -} - -/** The asynchronous IRQ handler - * - * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination - * conditions, such as buffer overflows or transfer complete. - * Parameter obj The SPI object that holds the transfer information - * Return Event flags if a transfer termination condition was met; otherwise 0. - */ -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - /* Return latest event. */ - return obj->spi.event; -} - -/** Attempts to determine if the SPI peripheral is already in use - * - * If a temporary DMA channel has been allocated, peripheral is in use. - * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA - * channel were allocated. - * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check - * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if - * there are any bytes in the FIFOs. - * Parameter obj The SPI object to check for activity - * Return Non-zero if the SPI port is active or zero if it is not. - */ -uint8_t spi_active(spi_t *obj) -{ - /* Callback handler is non-zero when a transfer is in progress. */ - return (obj->spi.handler != 0); -} - -/** Abort an SPI transfer - * - * Parameter obj The SPI peripheral to stop - */ -void spi_abort_asynch(spi_t *obj) -{ -} - -#endif // DEVICE_SPI_ASYNCH - -#endif // DEVICE_SPI diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/DeviceFamily.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/DeviceFamily.h deleted file mode 100755 index 8566650a7cf..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/DeviceFamily.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file DeviceFamily.h - * - * @brief Infrastructure to select correct driverlib path and identify devices - * - * This module enables the selection of the correct driverlib path for the current - * device. It also facilitates the use of per-device conditional compilation - * to enable minor variations in drivers between devices. - * - * In order to use this functionality, DeviceFamily_XYZ must be defined as one of - * the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines - * are set based on DeviceFamily_XYZ. - */ - -#ifndef ti_devices_DeviceFamily__include -#define ti_devices_DeviceFamily__include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * DeviceFamily_ID_XYZ values. - * - * DeviceFamily_ID may be used in the preprocessor for conditional compilation. - * DeviceFamily_ID is set to one of these values based on the top level - * DeviceFamily_XYZ define. - */ -#define DeviceFamily_ID_CC13X0 1 -#define DeviceFamily_ID_CC26X0 2 -#define DeviceFamily_ID_CC26X0R2 3 -#define DeviceFamily_ID_CC13X2_V1 4 -#define DeviceFamily_ID_CC13X2_V2 5 -#define DeviceFamily_ID_CC13X2 DeviceFamily_ID_CC13X2_V1 -#define DeviceFamily_ID_CC26X2_V1 6 -#define DeviceFamily_ID_CC26X2_V2 7 -#define DeviceFamily_ID_CC26X2 DeviceFamily_ID_CC26X2_V1 -#define DeviceFamily_ID_CC3200 8 -#define DeviceFamily_ID_CC3220 9 -#define DeviceFamily_ID_MSP432P401x 10 -#define DeviceFamily_ID_MSP432P4x1xI 11 -#define DeviceFamily_ID_MSP432P4x1xT 12 -#define DeviceFamily_ID_MSP432E401Y 13 -#define DeviceFamily_ID_MSP432E411Y 14 - -/* - * DeviceFamily_PARENT_XYZ values. - * - * DeviceFamily_PARENT may be used in the preprocessor for conditional - * compilation. DeviceFamily_PARENT is set to one of these values based - * on the top-level DeviceFamily_XYZ define. - */ -#define DeviceFamily_PARENT_CC13X0_CC26X0 1 -#define DeviceFamily_PARENT_CC13X2_CC26X2 2 -#define DeviceFamily_PARENT_MSP432P401R 3 -#define DeviceFamily_PARENT_MSP432P4111 4 - -/* - * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and - * DeviceFamily_PARENT based on the DeviceFamily_XYZ define. - * If DeviceFamily_XYZ is undefined, a compiler error is thrown. If - * multiple DeviceFamily_XYZ are defined, the first one encountered is used. - */ -#if defined(DeviceFamily_CC13X0) - #define DeviceFamily_ID DeviceFamily_ID_CC13X0 - #define DeviceFamily_DIRECTORY cc13x0 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC13X2) - #define DeviceFamily_ID DeviceFamily_ID_CC13X2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC13X2_V1) - #define DeviceFamily_ID DeviceFamily_ID_CC13X2_V1 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC13X2_V2) - #define DeviceFamily_ID DeviceFamily_ID_CC13X2_V2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC26X0) - #define DeviceFamily_ID DeviceFamily_ID_CC26X0 - #define DeviceFamily_DIRECTORY cc26x0 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC26X0R2) - #define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 - #define DeviceFamily_DIRECTORY cc26x0r2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC26X2) - #define DeviceFamily_ID DeviceFamily_ID_CC26X2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC26X2_V1) - #define DeviceFamily_ID DeviceFamily_ID_CC26X2_V1 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC26X2_V2) - #define DeviceFamily_ID DeviceFamily_ID_CC26X2_V2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC3200) - #define DeviceFamily_ID DeviceFamily_ID_CC3200 - #define DeviceFamily_DIRECTORY cc32xx - -#elif defined(DeviceFamily_CC3220) - #define DeviceFamily_ID DeviceFamily_ID_CC3220 - #define DeviceFamily_DIRECTORY cc32xx - -#elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P401x - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R - #if !defined(__MSP432P401R__) - #define __MSP432P401R__ - #endif - -#elif defined(DeviceFamily_MSP432P4x1xI) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 - #if !defined(__MSP432P4111__) - #define __MSP432P4111__ - #endif - -#elif defined(DeviceFamily_MSP432P4x1xT) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 - #if !defined(__MSP432P4111__) - #define __MSP432P4111__ - #endif - -#elif defined(DeviceFamily_MSP432E401Y) - #define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y - #define DeviceFamily_DIRECTORY msp432e4 - #if !defined(__MSP432E401Y__) - #define __MSP432E401Y__ - #endif - -#elif defined(DeviceFamily_MSP432E411Y) - #define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y - #define DeviceFamily_DIRECTORY msp432e4 - #if !defined(__MSP432E411Y__) - #define __MSP432E411Y__ - #endif -#else - #error "DeviceFamily_XYZ undefined. You must defined DeviceFamily_XYZ!" -#endif - -/*! - * @brief Macro to include correct driverlib path. - * - * @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined - * first. - * - * @param x A token containing the path of the file to include based on - * the root device folder. The preceding forward slash must be - * omitted. For example: - * - #include DeviceFamily_constructPath(inc/hw_memmap.h) - * - #include DeviceFamily_constructPath(driverlib/ssi.h) - * - * @return Returns an include path. - * - */ -#define DeviceFamily_constructPath(x) - -#ifdef __cplusplus -} -#endif - -#endif /* ti_devices_DeviceFamily__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.c deleted file mode 100755 index c36561c9553..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.c +++ /dev/null @@ -1,693 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// adc.c -// -// Driver for the ADC module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ADC_Analog_to_Digital_Converter_api -//! @{ -// -//***************************************************************************** -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ints.h" -#include "inc/hw_adc.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "adc.h" - - -//***************************************************************************** -// -//! Enables the ADC -//! -//! \param ulBase is the base address of the ADC -//! -//! This function sets the ADC global enable -//! -//! \return None. -// -//***************************************************************************** -void ADCEnable(unsigned long ulBase) -{ - // - // Set the global enable bit in the control register. - // - HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1; -} - -//***************************************************************************** -// -//! Disable the ADC -//! -//! \param ulBase is the base address of the ADC -//! -//! This function clears the ADC global enable -//! -//! \return None. -// -//***************************************************************************** -void ADCDisable(unsigned long ulBase) -{ - // - // Clear the global enable bit in the control register. - // - HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ; -} - -//***************************************************************************** -// -//! Enables specified ADC channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function enables specified ADC channel and configures the -//! pin as analog pin. -//! -//! \return None. -// -//***************************************************************************** -void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulCh; - - ulCh = (ulChannel == ADC_CH_0)? 0x02 : - (ulChannel == ADC_CH_1)? 0x04 : - (ulChannel == ADC_CH_2)? 0x08 : 0x10; - - HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh; -} - -//***************************************************************************** -// -//! Disables specified ADC channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channelsber -//! -//! This function disables specified ADC channel. -//! -//! \return None. -// -//***************************************************************************** -void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulCh; - - ulCh = (ulChannel == ADC_CH_0)? 0x02 : - (ulChannel == ADC_CH_1)? 0x04 : - (ulChannel == ADC_CH_2)? 0x08 : 0x10; - - HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh; -} - -//***************************************************************************** -// -//! Enables and registers ADC interrupt handler for specified channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! \param pfnHandler is a pointer to the function to be called when the -//! ADC channel interrupt occurs. -//! -//! This function enables and registers ADC interrupt handler for specified -//! channel. Individual interrupt for each channel should be enabled using -//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear -//! the interrupt source. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \return None. -// -//***************************************************************************** -void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel, - void (*pfnHandler)(void)) -{ - unsigned long ulIntNo; - - // - // Get the interrupt number associted with the specified channel - // - ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 : - (ulChannel == ADC_CH_1)? INT_ADCCH1 : - (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3; - - // - // Register the interrupt handler - // - IntRegister(ulIntNo,pfnHandler); - - // - // Enable ADC interrupt - // - IntEnable(ulIntNo); -} - - -//***************************************************************************** -// -//! Disables and unregisters ADC interrupt handler for specified channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function disables and unregisters ADC interrupt handler for specified -//! channel. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \return None. -// -//***************************************************************************** -void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulIntNo; - - // - // Get the interrupt number associted with the specified channel - // - ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 : - (ulChannel == ADC_CH_1)? INT_ADCCH1 : - (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3; - - // - // Disable ADC interrupt - // - IntDisable(ulIntNo); - - // - // Unregister the interrupt handler - // - IntUnregister(ulIntNo); -} - -//***************************************************************************** -// -//! Enables individual interrupt sources for specified channel -//! -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated ADC interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! - \b ADC_DMA_DONE for DMA done -//! - \b ADC_FIFO_OVERFLOW for FIFO over flow -//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow -//! - \b ADC_FIFO_EMPTY for FIFO empty -//! - \b ADC_FIFO_FULL for FIFO full -//! -//! \return None. -// -//***************************************************************************** -void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags) -{ - unsigned long ulOffset; - unsigned long ulDmaMsk; - - // - // Enable DMA Done interrupt - // - if(ulIntFlags & ADC_DMA_DONE) - { - ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: - (ulChannel == ADC_CH_1)?0x00002000: - (ulChannel == ADC_CH_2)?0x00004000:0x00008000; - - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; - } - - ulIntFlags = ulIntFlags & 0x0F; - // - // Get the interrupt enable register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_irq_en + ulChannel; - - // - // Unmask the specified interrupts - // - HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf); -} - - -//***************************************************************************** -// -//! Disables individual interrupt sources for specified channel -//! -//! -//! \param ulBase is the base address of the ADC. -//! \param ulChannel is one of the valid ADC channels -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function disables the indicated ADC interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The parameters\e ulIntFlags and \e ulChannel should be as explained in -//! ADCIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags) -{ - unsigned long ulOffset; - unsigned long ulDmaMsk; - - // - // Disable DMA Done interrupt - // - if(ulIntFlags & ADC_DMA_DONE) - { - ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: - (ulChannel == ADC_CH_1)?0x00002000: - (ulChannel == ADC_CH_2)?0x00004000:0x00008000; - - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; - } - - // - // Get the interrupt enable register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_irq_en + ulChannel; - - // - // Unmask the specified interrupts - // - HWREG(ulBase + ulOffset) &= ~ulIntFlags; -} - - -//***************************************************************************** -// -//! Gets the current channel interrupt status -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function returns the interrupt status of the specified ADC channel. -//! -//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable(). -//! -//! \return Return the ADC channel interrupt status, enumerated as a bit -//! field of values described in ADCIntEnable() -// -//***************************************************************************** -unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulOffset; - unsigned long ulDmaMsk; - unsigned long ulIntStatus; - - // - // Get DMA Done interrupt status - // - ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: - (ulChannel == ADC_CH_1)?0x00002000: - (ulChannel == ADC_CH_2)?0x00004000:0x00008000; - - ulIntStatus = HWREG(APPS_CONFIG_BASE + - APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk; - - - // - // Get the interrupt enable register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_irq_status + ulChannel; - - // - // Read ADC interrupt status - // - ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf; - - // - // Return the current interrupt status - // - return(ulIntStatus); -} - - -//***************************************************************************** -// -//! Clears the current channel interrupt sources -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. -//! -//! This function clears individual interrupt source for the specified -//! ADC channel. -//! -//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void ADCIntClear(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags) -{ - unsigned long ulOffset; - unsigned long ulDmaMsk; - - // - // Clear DMA Done interrupt - // - if(ulIntFlags & ADC_DMA_DONE) - { - ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: - (ulChannel == ADC_CH_1)?0x00002000: - (ulChannel == ADC_CH_2)?0x00004000:0x00008000; - - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; - } - - // - // Get the interrupt enable register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_irq_status + ulChannel; - - // - // Clear the specified interrupts - // - HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE)); -} - -//***************************************************************************** -// -//! Enables the ADC DMA operation for specified channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function enables the DMA operation for specified ADC channel -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \return None. -// -//***************************************************************************** -void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulBitMask; - - // - // Get the bit mask for enabling DMA for specified channel - // - ulBitMask = (ulChannel == ADC_CH_0)?0x01: - (ulChannel == ADC_CH_1)?0x04: - (ulChannel == ADC_CH_2)?0x10:0x40; - - // - // Enable DMA request for the specified channel - // - HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask; -} - -//***************************************************************************** -// -//! Disables the ADC DMA operation for specified channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function disables the DMA operation for specified ADC channel -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \return None. -// -//***************************************************************************** -void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulBitMask; - - // - // Get the bit mask for disabling DMA for specified channel - // - ulBitMask = (ulChannel == ADC_CH_0)?0x01: - (ulChannel == ADC_CH_1)?0x04: - (ulChannel == ADC_CH_2)?0x10:0x40; - - // - // Disable DMA request for the specified channel - // - HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask; -} - -//***************************************************************************** -// -//! Configures the ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! \param ulValue is wrap arround value of the timer -//! -//! This function Configures the ADC internal timer. The ADC timer is a 17 bit -//! used to timestamp the ADC data samples internally. -//! User can read the timestamp along with the sample from the FIFO register(s). -//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp -//! -//! The parameter \e ulValue can take any value between 0 - 2^17 -//! -//! \returns None. -// -//***************************************************************************** -void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue) -{ - unsigned long ulReg; - - // - // Read the currrent config - // - ulReg = HWREG(ulBase + ADC_O_adc_timer_configuration); - - // - // Mask and set timer count field - // - ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF)); - - // - // Set the timer count value - // - HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg; -} - -//***************************************************************************** -// -//! Resets ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! -//! This function resets 17-bit ADC internal timer -//! -//! \returns None. -// -//***************************************************************************** -void ADCTimerReset(unsigned long ulBase) -{ - // - // Reset the timer - // - HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24); -} - -//***************************************************************************** -// -//! Enables ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! -//! This function enables 17-bit ADC internal timer -//! -//! \returns None. -// -//***************************************************************************** -void ADCTimerEnable(unsigned long ulBase) -{ - // - // Enable the timer - // - HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25); -} - -//***************************************************************************** -// -//! Disables ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! -//! This function disables 17-bit ADC internal timer -//! -//! \returns None. -// -//***************************************************************************** -void ADCTimerDisable(unsigned long ulBase) -{ - // - // Disable the timer - // - HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25); -} - -//***************************************************************************** -// -//! Gets the current value of ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! -//! This function the current value of 17-bit ADC internal timer -//! -//! \returns Return the current value of ADC internal timer. -// -//***************************************************************************** -unsigned long ADCTimerValueGet(unsigned long ulBase) -{ - return(HWREG(ulBase + ADC_O_adc_timer_current_count)); -} - -//***************************************************************************** -// -//! Gets the current FIFO level for specified ADC channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels. -//! -//! This function returns the current FIFO level for specified ADC channel. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \returns Return the current FIFO level for specified channel -// -//***************************************************************************** -unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulOffset; - - // - // Get the fifo level register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel; - - // - // Return FIFO level - // - return(HWREG(ulBase + ulOffset) & 0x7); -} - -//***************************************************************************** -// -//! Reads FIFO for specified ADC channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels. -//! -//! This function returns one data sample from the channel fifo as specified by -//! \e ulChannel parameter. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \returns Return one data sample from the channel fifo. -// -//***************************************************************************** -unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulOffset; - - // - // Get the fifo register offset for specified channel - // - ulOffset = ADC_O_channel0FIFODATA + ulChannel; - - // - // Return FIFO level - // - return(HWREG(ulBase + ulOffset)); -} - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.h deleted file mode 100755 index 6f7095050de..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// adc.h -// -// Defines and Macros for the ADC. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// Values that can be passed to APIs as ulChannel parameter -//***************************************************************************** -#define ADC_CH_0 0x00000000 -#define ADC_CH_1 0x00000008 -#define ADC_CH_2 0x00000010 -#define ADC_CH_3 0x00000018 - - -//***************************************************************************** -// -// Values that can be passed to ADCIntEnable(), ADCIntDisable() -// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus() -// -//***************************************************************************** -#define ADC_DMA_DONE 0x00000010 -#define ADC_FIFO_OVERFLOW 0x00000008 -#define ADC_FIFO_UNDERFLOW 0x00000004 -#define ADC_FIFO_EMPTY 0x00000002 -#define ADC_FIFO_FULL 0x00000001 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void ADCEnable(unsigned long ulBase); -extern void ADCDisable(unsigned long ulBase); -extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel); -extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel); -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags); -extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags); -extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel); -extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel); -extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue); -extern void ADCTimerEnable(unsigned long ulBase); -extern void ADCTimerDisable(unsigned long ulBase); -extern void ADCTimerReset(unsigned long ulBase); -extern unsigned long ADCTimerValueGet(unsigned long ulBase); -extern unsigned char ADCFIFOLvlGet(unsigned long ulBase, - unsigned long ulChannel); -extern unsigned long ADCFIFORead(unsigned long ulBase, - unsigned long ulChannel); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.c deleted file mode 100755 index 4033f1501c6..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.c +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// camera.c -// -// Driver for the camera controller module -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup camera_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_camera.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "camera.h" - -//****************************************************************************** -// -//! Resets the Camera core -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function resets the camera core -//! -//! \return None. -// -//****************************************************************************** -void CameraReset(unsigned long ulBase) -{ - // - // Reset the camera - // - HWREG(ulBase + CAMERA_O_CC_SYSCONFIG) = CAMERA_CC_SYSCONFIG_SOFT_RESET; - - // - // Wait for reset completion - // - while(!(HWREG(ulBase + CAMERA_O_CC_SYSSTATUS)& - CAMERA_CC_SYSSTATUS_RESET_DONE2)) - { - - } - -} - -//****************************************************************************** -// -//! Configures camera parameters -//! -//! \param ulBase is the base address of the camera module. -//! \param ulHSPol sets the HSync polarity -//! \param ulVSPol sets the VSync polarity -//! \param ulFlags are configuration flags -//! -//! This function sets different camera parameters. -//! -//! The parameter \e ulHSPol should be on the follwoing: -//! - \b CAM_HS_POL_HI -//! - \b CAM_HS_POL_LO -//! -//! The parameter \e ulVSPol should be on the follwoing: -//! - \b CAM_VS_POL_HI -//! - \b CAM_VS_POL_LO -//! -//! The parameter \e ulFlags can be logical OR of one or more of the follwoing -//! or 0: -//! - \b CAM_PCLK_RISE_EDGE -//! - \b CAM_PCLK_FALL_EDGE -//! - \b CAM_ORDERCAM_SWAP -//! - \b CAM_NOBT_SYNCHRO -//! - \b CAM_IF_SYNCHRO -//! -//! \return None. -// -//****************************************************************************** -void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol, - unsigned long ulVSPol, unsigned long ulFlags) -{ - unsigned long ulReg; - - // - // Read the register - // - ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL); - - // - // Set the requested parameter - // - ulFlags = (ulFlags|ulHSPol|ulVSPol); - ulReg = ((ulReg & ~(CAMERA_CC_CTRL_NOBT_SYNCHRO | - CAMERA_CC_CTRL_NOBT_HS_POL | - CAMERA_CC_CTRL_NOBT_VS_POL | - CAMERA_CC_CTRL_BT_CORRECT | - CAMERA_CC_CTRL_PAR_ORDERCAM | - CAMERA_CC_CTRL_PAR_CLK_POL )) | ulFlags); - - // - // Write the configuration - // - HWREG(ulBase + CAMERA_O_CC_CTRL)=ulReg; -} - - -//****************************************************************************** -// -//! Set the internal clock divider -//! -//! \param ulBase is the base address of the camera module. -//! \param ulCamClkIn is input to camera module -//! \param ulXClk defines the output required -//! -//! This function sets the internal clock divider based on \e ulCamClkIn to -//! generate XCLK as specified be \e ulXClk. Maximum suppoter division is 30 -//! -//! \return None. -// -//****************************************************************************** -void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn, - unsigned long ulXClk) -{ - unsigned long ulReg; - unsigned long ucDiv; - - // - // Read the register - // - ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK); - - // - // Mask XCLK divider value - // - ulReg &= ~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M); - - // - // Compute the divider - // - ucDiv = ((ulCamClkIn)/ulXClk); - - // - // Max supported division is 30 - // - if(ucDiv > 30) - { - return; - } - - // - // Set and write back the configuration - // - ulReg |= ucDiv; - HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg; -} - - -//****************************************************************************** -// -//! Sets the internal divide in specified mode -//! -//! \param ulBase is the base address of the camera module. -//! \param bXClkFlags decides the divide mode -//! -//! This function sets the internal divide in specified mode. -//! -//! The parameter \e bXClkFlags should be one of the following : -//! -//! - \b CAM_XCLK_STABLE_LO -//! - \b CAM_XCLK_STABLE_HI -//! - \b CAM_XCLK_DIV_BYPASS -//! -//! \return None. -// -//****************************************************************************** -void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags) -{ - unsigned long ulReg; - - // - // Read and Mask XTAL Divider config. - // - ulReg = (HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) & - ~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M)); - - // - // Set config. base on parameter flag - // - switch(bXClkFlags) - { - - case CAM_XCLK_STABLE_HI : ulReg |= 0x00000001; - break; - - case CAM_XCLK_DIV_BYPASS: ulReg |= 0x0000001F; - break; - } - - // - // Write the config. - // - HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg; -} - - -//****************************************************************************** -// -//! Enable camera DMA -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function enables transfer request to DMA from camera. DMA specific -//! configuration has to be done seperately. -//! -//! \return None. -// -//****************************************************************************** -void CameraDMAEnable(unsigned long ulBase) -{ - // - // Enable DMA - // - HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= CAMERA_CC_CTRL_DMA_DMA_EN; -} - - -//****************************************************************************** -// -//! Disable camera DMA -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function masks transfer request to DMA from camera. -//! -//! \return None. -// -//****************************************************************************** -void CameraDMADisable(unsigned long ulBase) -{ - // - // Disable DMA - // - HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_DMA_EN; -} - - - -//****************************************************************************** -// -//! Sets the FIFO threshold for DMA transfer request -//! -//! \param ulBase is the base address of the camera module. -//! \param ulThreshold specifies the FIFO threshold -//! -//! This function sets the FIFO threshold for DMA transfer request. -//! Parameter \e ulThreshold can range from 1 - 64 -//! -//! \return None. -// -//****************************************************************************** -void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold) -{ - // - // Read and Mask DMA threshold field - // - HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M; - // - // Write the new threshold value - // - HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= (ulThreshold -1); -} - - -//****************************************************************************** -// -//! Register camera interrupt handler -//! -//! \param ulBase is the base address of the camera module. -//! \param pfnHandler hold pointer to interrupt handler -//! -//! This function registers and enables global camera interrupt from the -//! interrupt controller. Individual camera interrupts source -//! should be enabled using \sa CameraIntEnable(). -//! -//! \return None. -// -//****************************************************************************** -void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler. - // - IntRegister(INT_CAMERA, pfnHandler); - - // - // Enable the Camera interrupt. - // - IntEnable(INT_CAMERA); -} - - -//****************************************************************************** -// -//! Un-Register camera interrupt handler -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function unregisters and disables global camera interrupt from the -//! interrupt controller. -//! -//! \return None. -// -//****************************************************************************** -void CameraIntUnregister(unsigned long ulBase) -{ - // - // Disable the interrupt. - // - IntDisable(INT_CAMERA); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_CAMERA); -} - - -//****************************************************************************** -//! Enables individual camera interrupt sources. -//! -//! \param ulBase is the base address of the camera module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables individual camera interrupt sources. -//! -//! the parameter \e ulIntFlags should be logical OR of one or more of the -//! following: -//! -//! - \b CAM_INT_DMA -//! - \b CAM_INT_FE -//! - \b CAM_INT_FSC_ERR -//! - \b CAM_INT_FIFO_NOEMPTY -//! - \b CAM_INT_FIFO_FULL -//! - \b CAM_INT_FIFO_THR -//! - \b CAM_INT_FIFO_OF -//! - \b CAN_INT_FIFO_UR -//! -//! \return None. -// -//****************************************************************************** -void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // unmask Camera DMA done interrupt - // - if(ulIntFlags & CAM_INT_DMA) - { - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ((1<<8)); - } - - // - // Enable specific camera interrupts - // - HWREG(ulBase + CAMERA_O_CC_IRQENABLE) |= ulIntFlags; -} - - -//****************************************************************************** -//! Disables individual camera interrupt sources. -//! -//! \param ulBase is the base address of the camera module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables individual camera interrupt sources. -//! -//! The parameter \e ulIntFlags should be logical OR of one or more of the -//! values as defined in CameraIntEnable(). -//! -//! \return None. -// -//****************************************************************************** -void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Mask Camera DMA done interrupt - // - if(ulIntFlags & CAM_INT_DMA) - { - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ((1<<8)); - } - - // - // Disable specific camera interrupts - // - HWREG(ulBase + CAMERA_O_CC_IRQENABLE) &= ~ulIntFlags; -} - -//****************************************************************************** -// -//! Returns the current interrupt status, -//! -//! \param ulBase is the base address of the camera module. -//! \param ulBase is the base address of the camera module. -//! -//! This functions returns the current interrupt status for the camera. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in CameraIntEnable(). -//****************************************************************************** -unsigned long CameraIntStatus(unsigned long ulBase) -{ - unsigned ulIntFlag; - - // - // Read camera interrupt - // - ulIntFlag = HWREG(ulBase + CAMERA_O_CC_IRQSTATUS); - - // - // - // Read camera DMA doner interrupt - // - if(HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED) & (1<<8)) - { - ulIntFlag |= CAM_INT_DMA; - } - - // - // Return status - // - return(ulIntFlag); -} - - -//****************************************************************************** -//! Clears individual camera interrupt sources. -//! -//! \param ulBase is the base address of the camera module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be Clears. -//! -//! This function Clears individual camera interrupt sources. -//! -//! The parameter \e ulIntFlags should be logical OR of one or more of the -//! values as defined in CameraIntEnable(). -//! -//! \return None. -// -//****************************************************************************** -void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Clear DMA done int status - // - if(ulIntFlags & CAM_INT_DMA) - { - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ((1<<8)); - } - - // - // Clear the interrupts - // - HWREG(ulBase + CAMERA_O_CC_IRQSTATUS) = ulIntFlags; -} - -//****************************************************************************** -// -//! Starts image capture -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function starts the image capture over the configured camera interface -//! This function should be called after configuring the camera module -//! completele -//! -//! \return None. -// -//****************************************************************************** -void CameraCaptureStart(unsigned long ulBase) -{ - // - // Set the mode - // - HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~0xF; - - // - // Enable image capture - // - HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_EN; -} - -//****************************************************************************** -// -//! Stops image capture -//! -//! \param ulBase is the base address of the camera module. -//! \param bImmediate is \b true to stop capture imeediately else \b flase. -//! -//! This function stops the image capture over the camera interface. -//! The capture is stopped either immediatelt or at the end of current frame -//! based on \e bImmediate parameter. -//! -//! \return None. -// -//****************************************************************************** -void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate) -{ - if(bImmediate) - { - // - // Stop capture immediately - // - HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_FRAME_TRIG; - } - else - { - // - // Stop capture at the end of frame - // - HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_FRAME_TRIG; - } - - // - // Request camera to stop capture - // - HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_EN; -} - - -//****************************************************************************** -// -//! Reads the camera buffer (FIFO) -//! -//! \param ulBase is the base address of the camera module. -//! \param pBuffer is the pointer to the read buffer -//! \param ucSize specifies the size to data to be read -//! -//! This function reads the camera buffer (FIFO). -//! -//! \return None. -// -//****************************************************************************** -void CameraBufferRead(unsigned long ulBase, unsigned long *pBuffer, - unsigned char ucSize) -{ - unsigned char *pCamBuff; - unsigned char i; - - // - // Initilize a pointer to ecamera buffer - // - pCamBuff = (unsigned char *)CAM_BUFFER_ADDR; - - // - // Read out requested data - // - for(i=0; i < ucSize; i++) - { - *(pBuffer+i) = *(pCamBuff + i); - } -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.h deleted file mode 100755 index a3c08f91bae..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// camera.h -// -// Prototypes and macros for the camera controller module. -// -//***************************************************************************** - -#ifndef __CAMERA_H__ -#define __CAMERA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// Macro defining Camera buffer address -//***************************************************************************** -#define CAM_BUFFER_ADDR 0x44018100 - - -//***************************************************************************** -// Value that can be passed to CameraXClkSet(). -//***************************************************************************** -#define CAM_XCLK_STABLE_LO 0x00 -#define CAM_XCLK_STABLE_HI 0x01 -#define CAM_XCLK_DIV_BYPASS 0x02 - - -//***************************************************************************** -// Value that can be passed to CameraIntEnable(), CameraIntDisable, -// CameraIntClear() or returned from CameraIntStatus(). -//***************************************************************************** -#define CAM_INT_DMA 0x80000000 -#define CAM_INT_FE 0x00010000 -#define CAM_INT_FIFO_NOEMPTY 0x00000010 -#define CAM_INT_FIFO_FULL 0x00000008 -#define CAM_INT_FIFO_THR 0x00000004 -#define CAM_INT_FIFO_OF 0x00000002 -#define CAN_INT_FIFO_UR 0x00000001 - - -//***************************************************************************** -// Value that can be passed to CameraXClkConfig(). -//***************************************************************************** -#define CAM_HS_POL_HI 0x00000000 -#define CAM_HS_POL_LO 0x00000200 -#define CAM_VS_POL_HI 0x00000000 -#define CAM_VS_POL_LO 0x00000100 - -#define CAM_PCLK_RISE_EDGE 0x00000000 -#define CAM_PCLK_FALL_EDGE 0x00000400 - -#define CAM_ORDERCAM_SWAP 0x00000800 -#define CAM_NOBT_SYNCHRO 0x00002000 -#define CAM_IF_SYNCHRO 0x00080000 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void CameraReset(unsigned long ulBase); -extern void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol, - unsigned long ulVSPol, unsigned long ulFlags); -extern void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn, - unsigned long ulXClk); -extern void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags); -extern void CameraDMAEnable(unsigned long ulBase); -extern void CameraDMADisable(unsigned long ulBase); -extern void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold); -extern void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void CameraIntUnregister(unsigned long ulBase); -extern void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long CameraIntStatus(unsigned long ulBase); -extern void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate); -extern void CameraCaptureStart(unsigned long ulBase); -extern void CameraBufferRead(unsigned long ulBase,unsigned long *pBuffer, - unsigned char ucSize); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif //__CAMERA_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.c deleted file mode 100755 index 5b01ae09303..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// cpu.c -// -// Instruction wrappers for special CPU instructions needed by the -// -// -//***************************************************************************** -#include "cpu.h" - -//***************************************************************************** -// -// Wrapper function for the CPSID instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(gcc) -unsigned long __attribute__((naked)) -CPUcpsid(void) -{ - unsigned long ulRet; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " dsb \n" - " isb \n" - " bx lr\n" - : "=r" (ulRet)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ulRet); -} -#endif -#if defined(ewarm) -unsigned long -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " dsb \n" - " isb \n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif - -#if defined(arm_cc) -unsigned long -CPUcpsid(void) -{ - // TODO: Implement it! - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function returning the state of PRIMASK (indicating whether -// interrupts are enabled or disabled). -// -//***************************************************************************** -#if defined(gcc) -unsigned long __attribute__((naked)) -CPUprimask(void) -{ - unsigned long ulRet; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n" - : "=r" (ulRet)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ulRet); -} -#endif -#if defined(ewarm) -unsigned long -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(arm_cc) -unsigned long -CPUprimask(void) -{ - // TODO: Implement it! - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(gcc) -unsigned long __attribute__((naked)) -CPUcpsie(void) -{ - unsigned long ulRet; - - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " dsb \n" - " isb \n" - " bx lr\n" - : "=r" (ulRet)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ulRet); -} -#endif -#if defined(ewarm) -unsigned long -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " dsb \n" - " isb \n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(arm_cc) -unsigned long -CPUcpsie(void) -{ - // TODO: Implement it! - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the WFI instruction. -// -//***************************************************************************** -#if defined(gcc) -void __attribute__((naked)) -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" dsb \n" - " isb \n" - " wfi \n" - " bx lr\n"); -} -#endif -#if defined(ewarm) -void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" dsb \n" - " isb \n" - " wfi \n"); -} -#endif -#if defined(arm_cc) -void -CPUwfi(void) -{ - // TODO: Implement it! -} -#endif - -//***************************************************************************** -// -// Wrapper function for writing the BASEPRI register. -// -//***************************************************************************** -#if defined(gcc) -void __attribute__((naked)) -CPUbasepriSet(unsigned long ulNewBasepri) -{ - - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n" - " dsb \n" - " isb \n" - " bx lr\n"); -} -#endif -#if defined(ewarm) -void -CPUbasepriSet(unsigned long ulNewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n" - " dsb \n" - " isb \n"); -} -#endif -#if defined(arm_cc) -void -CPUbasepriSet(unsigned long ulNewBasepri) -{ - // - // Set the BASEPRI register - // - // TODO: Implement it! -} -#endif - -//***************************************************************************** -// -// Wrapper function for reading the BASEPRI register. -// -//***************************************************************************** -#if defined(gcc) -unsigned long __attribute__((naked)) -CPUbasepriGet(void) -{ - unsigned long ulRet; - - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n" - : "=r" (ulRet)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ulRet); -} -#endif -#if defined(ewarm) -unsigned long -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(arm_cc) -unsigned long -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - // TODO: Implement it - return(0); -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.h deleted file mode 100755 index 0b968363fa3..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// cpu.h -// -// Prototypes for the CPU instruction wrapper functions. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -// TODO, move this to tools -#ifdef TOOLCHAIN_GCC_ARM -#define gcc -#elif TOOLCHAIN_ARM -#define arm_cc -#elif defined TOOLCHAIN_IAR -#define ewarm -#endif - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern unsigned long CPUcpsid(void); -extern unsigned long CPUcpsie(void); -extern unsigned long CPUprimask(void); -extern void CPUwfi(void); -extern unsigned long CPUbasepriGet(void); -extern void CPUbasepriSet(unsigned long ulNewBasepri); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __CPU_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.c deleted file mode 100755 index 46f31aae3c9..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// crc.c -// -// Driver for the CRC module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup CRC_Cyclic_Redundancy_Check_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_dthe.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "driverlib/crc.h" -#include "driverlib/debug.h" - -//***************************************************************************** -// -//! Set the configuration of CRC functionality with the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32CRCConfig is the configuration of the CRC engine. -//! -//! This function configures the operation of the CRC engine within the EC -//! module. The configuration is specified with the \e ui32CRCConfig argument. -//! It is the logical OR of any of the following options: -//! -//! CRC Initialization Value -//! - \b EC_CRC_CFG_INIT_SEED - Initialize with seed value -//! - \b EC_CRC_CFG_INIT_0 - Initialize to all '0s' -//! - \b EC_CRC_CFG_INIT_1 - Initialize to all '1s' -//! -//! Input Data Size -//! - \b EC_CRC_CFG_SIZE_8BIT - Input data size of 8 bits -//! - \b EC_CRC_CFG_SIZE_32BIT - Input data size of 32 bits -//! -//! Post Process Reverse/Inverse -//! - \b EC_CRC_CFG_RESINV - Result inverse enable -//! - \b EC_CRC_CFG_OBR - Output reverse enable -//! -//! Input Bit Reverse -//! - \b EC_CRC_CFG_IBR - Bit reverse enable -//! -//! Endian Control -//! - \b EC_CRC_CFG_ENDIAN_SBHW - Swap byte in half-word -//! - \b EC_CRC_CFG_ENDIAN_SHW - Swap half-word -//! -//! Operation Type -//! - \b EC_CRC_CFG_TYPE_P8005 - Polynomial 0x8005 -//! - \b EC_CRC_CFG_TYPE_P1021 - Polynomial 0x1021 -//! - \b EC_CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7 -//! - \b EC_CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41 -//! - \b EC_CRC_CFG_TYPE_TCPCHKSUM - TCP checksum -//! -//! \return None. -// -//***************************************************************************** -void -CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) || - (ui32CRCConfig & CRC_CFG_INIT_0) || - (ui32CRCConfig & CRC_CFG_INIT_1) || - (ui32CRCConfig & CRC_CFG_SIZE_8BIT) || - (ui32CRCConfig & CRC_CFG_SIZE_32BIT) || - (ui32CRCConfig & CRC_CFG_RESINV) || - (ui32CRCConfig & CRC_CFG_OBR) || - (ui32CRCConfig & CRC_CFG_IBR) || - (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) || - (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) || - (ui32CRCConfig & CRC_CFG_TYPE_P8005) || - (ui32CRCConfig & CRC_CFG_TYPE_P1021) || - (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) || - (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) || - (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM)); - - // - // Write the control register with the configuration. - // - HWREG(ui32Base + DTHE_O_CRC_CTRL) = ui32CRCConfig; -} - -//***************************************************************************** -// -//! Write the seed value for CRC operations in the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32Seed is the seed value. -//! -//! This function writes the seed value for use with CRC operations in the -//! EC module. This value is the start value for CRC operations. If this -//! value is not written, then the residual seed from the previous operation -//! is used as the starting value. -//! -//! \note The seed must be written only if \b EC_CRC_CFG_INIT_SEED is -//! set with the CRCConfigSet() function. -// -//***************************************************************************** -void -CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - - // - // Write the seed value to the seed register. - // - HWREG(ui32Base + DTHE_O_CRC_SEED) = ui32Seed; -} - -//***************************************************************************** -// -//! Write data into the EC module for CRC operations. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32Data is the data to be written. -//! -//! This function writes either 8 or 32 bits of data into the EC module for -//! CRC operations. The distinction between 8 and 32 bits of data is made -//! when the \b EC_CRC_CFG_SIZE_8BIT or \b EC_CRC_CFG_SIZE_32BIT flag -//! is set using the CRCConfigSet() function. -//! -//! When writing 8 bits of data, ensure the data is in the least signficant -//! byte position. The remaining bytes should be written with zero. For -//! example, when writing 0xAB, \e ui32Data should be 0x000000AB. -//! -//! \return None -// -//***************************************************************************** -void -CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - - // - // Write the data - // - HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data; -} - -//***************************************************************************** -// -//! Reads the result of a CRC operation in the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! -//! This function reads either the unmodified CRC result or the post -//! processed CRC result from the EC module. The post-processing options -//! are selectable through \b EC_CRC_CFG_RESINV and \b EC_CRC_CFG_OBR -//! parameters in the CRCConfigSet() function. -//! -//! \return The CRC result. -// -//***************************************************************************** -uint32_t -CRCResultRead(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - - // - // return value. - // - return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP)); - -} - -//***************************************************************************** -// -//! Process data to generate a CRC with the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param puiDataIn is a pointer to an array of data that is processed. -//! \param ui32DataLength is the number of data items that are processed -//! to produce the CRC. -//! \param ui32Config the config parameter to determine the CRC mode -//! -//! This function processes an array of data to produce a CRC result. -//! This function takes the CRC mode as the parameter. -//! -//! The data in the array pointed to be \e pui32DataIn is either an array -//! of bytes or an array or words depending on the selection of the input -//! data size options \b EC_CRC_CFG_SIZE_8BIT and -//! \b EC_CRC_CFG_SIZE_32BIT. -//! -//! This function returns either the unmodified CRC result or the -//! post- processed CRC result from the EC module. The post-processing -//! options are selectable through \b EC_CRC_CFG_RESINV and -//! \b EC_CRC_CFG_OBR parameters. -//! -//! \return The CRC result. -// -//***************************************************************************** -uint32_t -CRCDataProcess(uint32_t ui32Base, void *puiDataIn, - uint32_t ui32DataLength, uint32_t ui32Config) -{ - uint8_t *pui8DataIn; - uint32_t *pui32DataIn; - - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - - // - // See if the CRC is operating in 8-bit or 32-bit mode. - // - if(ui32Config & DTHE_CRC_CTRL_SIZE) - { - // - // The CRC is operating in 8-bit mode, so create an 8-bit pointer to - // the data. - // - pui8DataIn = (uint8_t *)puiDataIn; - - // - // Loop through the input data. - // - while(ui32DataLength--) - { - // - // Write the next data byte. - // - HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui8DataIn++; - } - } - else - { - // - // The CRC is operating in 32-bit mode, so loop through the input data. - // - pui32DataIn = (uint32_t *)puiDataIn; - while(ui32DataLength--) - { - // - // Write the next data word. - // - HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui32DataIn++; - } - } - - // - // Return the result. - // - return(CRCResultRead(ui32Base)); -} - - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.h deleted file mode 100755 index 5e8d3f5e74c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// crc.h -// -// Defines and Macros for CRC module. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_CRC_H__ -#define __DRIVERLIB_CRC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used in the ui32Config argument of the -// ECConfig function. -// -//***************************************************************************** -#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed -#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s' -#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s' -#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size -#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size -#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable -#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable -#define CRC_CFG_IBR 0x00000080 // Bit reverse enable -#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word -#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word -#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005 -#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021 -#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7 -#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41 -#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum - -//***************************************************************************** -// -// Function prototypes. -// -//***************************************************************************** -extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig); -extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn, - uint32_t ui32DataLength, uint32_t ui32Config); -extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data); -extern uint32_t CRCResultRead(uint32_t ui32Base); -extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_CRC_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/debug.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/debug.h deleted file mode 100755 index cef10a43ab9..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/debug.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// debug.h -// -// Macros for assisting debug of the driver library. -// -//***************************************************************************** -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.c deleted file mode 100755 index 890a0447728..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.c +++ /dev/null @@ -1,864 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// flash.c -// -// Driver for programming the on-chip flash. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup flash_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_flash_ctrl.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ints.h" -#include "inc/hw_gprcm.h" -#include "inc/hw_hib1p2.h" -#include "inc/hw_hib3p3.h" -#include "inc/hw_common_reg.h" -#include "inc/hw_stack_die_ctrl.h" -#include "debug.h" -#include "flash.h" -#include "utils.h" -#include "interrupt.h" - -#define HAVE_WRITE_BUFFER 1 - - - -//***************************************************************************** -// -// An array that maps the specified memory bank to the appropriate Flash -// Memory Protection Program Enable (FMPPE) register. -// -//***************************************************************************** -static const unsigned long g_pulFMPPERegs[] = -{ - FLASH_FMPPE0, - FLASH_FMPPE1, - FLASH_FMPPE2, - FLASH_FMPPE3, - FLASH_FMPPE4, - FLASH_FMPPE5, - FLASH_FMPPE6, - FLASH_FMPPE7, - FLASH_FMPPE8, - FLASH_FMPPE9, - FLASH_FMPPE10, - FLASH_FMPPE11, - FLASH_FMPPE12, - FLASH_FMPPE13, - FLASH_FMPPE14, - FLASH_FMPPE15 - - -}; - -//***************************************************************************** -// -// An array that maps the specified memory bank to the appropriate Flash -// Memory Protection Read Enable (FMPRE) register. -// -//***************************************************************************** -static const unsigned long g_pulFMPRERegs[] = -{ - FLASH_FMPRE0, - FLASH_FMPRE1, - FLASH_FMPRE2, - FLASH_FMPRE3, - FLASH_FMPRE4, - FLASH_FMPRE5, - FLASH_FMPRE6, - FLASH_FMPRE7, - FLASH_FMPRE8, - FLASH_FMPRE9, - FLASH_FMPRE10, - FLASH_FMPRE11, - FLASH_FMPRE12, - FLASH_FMPRE13, - FLASH_FMPRE14, - FLASH_FMPRE15, -}; - -//***************************************************************************** -// -//! Flash Disable -//! -//! This function Disables the internal Flash. -//! -//! \return None. -// -//***************************************************************************** -void -FlashDisable() -{ - - // - // Wait for Flash Busy to get cleared - // - while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) - & GPRCM_TOP_DIE_ENABLE_FLASH_BUSY)) - { - - } - - // - // Assert reset - // - HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000; - - // - // 50 usec Delay Loop - // - UtilsDelay((50*80)/3); - - // - // Disable TDFlash - // - HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0; - - // - // 50 usec Delay Loop - // - UtilsDelay((50*80)/3); - - HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; - - // - // 50 usec Delay Loop - // - UtilsDelay((50*80)/3); -} - - -//***************************************************************************** -// -//! Erases a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be erased. -//! -//! This function will erase a 2 kB block of the on-chip flash. After erasing, -//! the block will be filled with 0xFF bytes. Read-only and execute-only -//! blocks cannot be erased. -//! -//! This function will not return until the block has been erased. -//! -//! \return Returns 0 on success, or -1 if an invalid block address was -//! specified or the block is write-protected. -// -//***************************************************************************** -long -FlashErase(unsigned long ulAddress) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1))); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) - = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_ERMISC); - - // Erase the block. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) - = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE; - - // - // Wait until the block has been erased. - // - while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE) - { - } - - // - // Return an error if an access violation or erase error occurred. - // - if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) - & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | - FLASH_CTRL_FCRIS_ERRIS)) - - - { - return(-1); - } - - // - // Success. - // - return(0); -} - - -//***************************************************************************** -// -//! Erases a block of flash but does not wait for completion. -//! -//! \param ulAddress is the start address of the flash block to be erased. -//! -//! This function will erase a 2 kB block of the on-chip flash. After erasing, -//! the block will be filled with 0xFF bytes. Read-only and execute-only -//! blocks cannot be erased. -//! -//! This function will return immediately after commanding the erase operation. -//! Applications making use of the function can determine completion state by -//! using a flash interrupt handler or by polling FlashIntStatus. -//! -//! \return None. -// -//***************************************************************************** -void -FlashEraseNonBlocking(unsigned long ulAddress) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1))); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = - (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_ERMISC); - - // - // Command the flash controller to erase the block. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE; -} - - -//***************************************************************************** -// -//! Erases a complele flash at shot. -//! -//! This function erases a complele flash at shot -//! -//! \return Returns 0 on success, or -1 if the block is write-protected. -// -//***************************************************************************** -long -FlashMassErase() -{ - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = - (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_ERMISC); - - // - // Command the flash controller for mass erase. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = - FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1; - - // - // Wait until mass erase completes. - // - while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_MERASE1) - { - - } - - // - // Return an error if an access violation or erase error occurred. - // - if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) - & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | - FLASH_CTRL_FCRIS_ERRIS)) - { - return -1; - } - - // - // Success. - // - return 0; -} - -//***************************************************************************** -// -//! Erases a complele flash at shot but does not wait for completion. -//! -//! -//! This function will not return until the Flash has been erased. -//! -//! \return None. -// -//***************************************************************************** -void -FlashMassEraseNonBlocking() -{ - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = - (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_ERMISC); - - // - // Command the flash controller for mass erase. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = - FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1; - -} - -//***************************************************************************** -// -//! Programs flash. -//! -//! \param pulData is a pointer to the data to be programmed. -//! \param ulAddress is the starting address in flash to be programmed. Must -//! be a multiple of four. -//! \param ulCount is the number of bytes to be programmed. Must be a multiple -//! of four. -//! -//! This function will program a sequence of words into the on-chip flash. -//! Each word in a page of flash can only be programmed one time between an -//! erase of that page; programming a word multiple times will result in an -//! unpredictable value in that word of flash. -//! -//! Since the flash is programmed one word at a time, the starting address and -//! byte count must both be multiples of four. It is up to the caller to -//! verify the programmed contents, if such verification is required. -//! -//! This function will not return until the data has been programmed. -//! -//! \return Returns 0 on success, or -1 if a programming error is encountered. -// -//***************************************************************************** -long -FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & 3)); - ASSERT(!(ulCount & 3)); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) - = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC); - - - // - // See if this device has a write buffer. - // - -#if HAVE_WRITE_BUFFER - { - // - // Loop over the words to be programmed. - // - while(ulCount) - { - // - // Set the address of this block of words. for 1 MB - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F); - - // - // Loop over the words in this 32-word block. - // - while(((ulAddress & 0x7C) || - (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) && - (ulCount != 0)) - { - // - // Write this word into the write buffer. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN - + (ulAddress & 0x7C)) = *pulData++; - ulAddress += 4; - ulCount -= 4; - } - - // - // Program the contents of the write buffer into flash. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) - = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF; - - // - // Wait until the write buffer has been programmed. - // - while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) & FLASH_CTRL_FMC2_WRBUF) - { - } - } - } -#else - { - // - // Loop over the words to be programmed. - // - while(ulCount) - { - // - // Program the next word. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE; - - // - // Wait until the word has been programmed. - // - while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_WRITE) - { - } - - // - // Increment to the next word. - // - pulData++; - ulAddress += 4; - ulCount -= 4; - } - } -#endif - // - // Return an error if an access violation occurred. - // - - if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | - FLASH_CTRL_FCRIS_INVDRIS | FLASH_CTRL_FCRIS_PROGRIS)) - - { - return(-1); - } - - // - // Success. - // - return(0); -} - - -//***************************************************************************** -// -//! Programs flash but does not poll for completion. -//! -//! \param pulData is a pointer to the data to be programmed. -//! \param ulAddress is the starting address in flash to be programmed. Must -//! be a multiple of four. -//! \param ulCount is the number of bytes to be programmed. Must be a multiple -//! of four. -//! -//! This function will start programming one or more words into the on-chip -//! flash and return immediately. The number of words that can be programmed -//! in a single call depends the part on which the function is running. For -//! parts without support for a flash write buffer, only a single word may be -//! programmed on each call to this function (\e ulCount must be 1). If a -//! write buffer is present, up to 32 words may be programmed on condition -//! that the block being programmed does not straddle a 32 word address -//! boundary. For example, wherease 32 words can be programmed if the address -//! passed is 0x100 (a multiple of 128 bytes or 32 words), only 31 words could -//! be programmed at 0x104 since attempting to write 32 would cross the 32 -//! word boundary at 0x180. -//! -//! Since the flash is programmed one word at a time, the starting address and -//! byte count must both be multiples of four. It is up to the caller to -//! verify the programmed contents, if such verification is required. -//! -//! This function will return immediately after commanding the erase operation. -//! Applications making use of the function can determine completion state by -//! using a flash interrupt handler or by polling FlashIntStatus. -//! -//! \return 0 if the write was started successfully, -1 if there was an error. -// -//***************************************************************************** -long -FlashProgramNonBlocking(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & 3)); - ASSERT(!(ulCount & 3)); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) - = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC); - - // - // See if this device has a write buffer. - // - -#if HAVE_WRITE_BUFFER - { - // - // Make sure the address/count specified doesn't straddle a 32 word - // boundary. - // - if(((ulAddress + (ulCount - 1)) & ~0x7F) != (ulAddress & ~0x7F)) - { - return(-1); - } - - // - // Loop over the words to be programmed. - // - while(ulCount) - { - // - // Set the address of this block of words. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F); - - // - // Loop over the words in this 32-word block. - // - while(((ulAddress & 0x7C) || (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) && - (ulCount != 0)) - { - // - // Write this word into the write buffer. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + (ulAddress & 0x7C)) = *pulData++; - ulAddress += 4; - ulCount -= 4; - } - - // - // Program the contents of the write buffer into flash. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF; - } - } -#else - { - // - // We don't have a write buffer so we can only write a single word. - // - if(ulCount > 1) - { - return(-1); - } - - // - // Write a single word. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE; - } -#endif - // - // Success. - // - return(0); -} - - -//***************************************************************************** -// -//! Gets the protection setting for a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be queried. -//! -//! This function gets the current protection for the specified 2-kB block -//! of flash. Each block can be read/write, read-only, or execute-only. -//! Read/write blocks can be read, executed, erased, and programmed. Read-only -//! blocks can be read and executed. Execute-only blocks can only be executed; -//! processor and debugger data reads are not allowed. -//! -//! \return Returns the protection setting for this block. See -//! FlashProtectSet() for possible values. -// -//***************************************************************************** -tFlashProtection -FlashProtectGet(unsigned long ulAddress) -{ - unsigned long ulFMPRE, ulFMPPE; - unsigned long ulBank; - - // - // Check the argument. - // - ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); - - // - // Calculate the Flash Bank from Base Address, and mask off the Bank - // from ulAddress for subsequent reference. - // - ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 16); - ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1); - - // - // Read the appropriate flash protection registers for the specified - // flash bank. - // - ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]); - ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]); - - // - // Check the appropriate protection bits for the block of memory that - // is specified by the address. - // - switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & - FLASH_FMP_BLOCK_0) << 1) | - ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) - { - // - // This block is marked as execute only (that is, it can not be erased - // or programmed, and the only reads allowed are via the instruction - // fetch interface). - // - case 0: - case 1: - { - return(FlashExecuteOnly); - } - - // - // This block is marked as read only (that is, it can not be erased or - // programmed). - // - case 2: - { - return(FlashReadOnly); - } - - // - // This block is read/write; it can be read, erased, and programmed. - // - case 3: - default: - { - return(FlashReadWrite); - } - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the flash interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the flash -//! interrupt occurs. -//! -//! This sets the handler to be called when the flash interrupt occurs. The -//! flash controller can generate an interrupt when an invalid flash access -//! occurs, such as trying to program or erase a read-only block, or trying to -//! read from an execute-only block. It can also generate an interrupt when a -//! program or erase operation has completed. The interrupt will be -//! automatically enabled when the handler is registered. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_FLASH, pfnHandler); - - // - // Enable the flash interrupt. - // - IntEnable(INT_FLASH); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the flash interrupt. -//! -//! This function will clear the handler to be called when the flash interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_FLASH); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_FLASH); -} - -//***************************************************************************** -// -//! Enables individual flash controller interrupt sources. -//! -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values. -//! -//! Enables the indicated flash controller interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntEnable(unsigned long ulIntFlags) -{ - // - // Enable the specified interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) |= ulIntFlags; -} - -//***************************************************************************** -// -//! Disables individual flash controller interrupt sources. -//! -//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values. -//! -//! Disables the indicated flash controller interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntDisable(unsigned long ulIntFlags) -{ - // - // Disable the specified interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) &= ~(ulIntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the flash controller. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b FLASH_CTRL_PROGRAM and \b FLASH_CTRL_ACCESS. -// -//***************************************************************************** -unsigned long -FlashIntStatus(tBoolean bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)); - } - else - { - return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)); - } -} - -//***************************************************************************** -// -//! Clears flash controller interrupt sources. -//! -//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. -//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_AMISC values. -//! -//! The specified flash controller interrupt sources are cleared, so that they -//! no longer assert. This must be done in the interrupt handler to keep it -//! from being called again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntClear(unsigned long ulIntFlags) -{ - // - // Clear the flash interrupt. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = ulIntFlags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.h deleted file mode 100755 index 75cf0cfd8db..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// flash.h -// -// Prototypes for the flash driver. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and -// returned from FlashIntStatus(). -// -//***************************************************************************** -#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask -#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask -#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask -#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask -#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask -#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void FlashDisable(void); -extern long FlashErase(unsigned long ulAddress); -extern void FlashEraseNonBlocking(unsigned long ulAddress); -extern long FlashMassErase(void); -extern void FlashMassEraseNonBlocking(void); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern long FlashProgramNonBlocking(unsigned long *pulData, - unsigned long ulAddress, - unsigned long ulCount); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.c deleted file mode 100755 index e2c5ff2aa89..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.c +++ /dev/null @@ -1,717 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// gpio.c -// -// Driver for the GPIO module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup GPIO_General_Purpose_InputOutput_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_gpio.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_common_reg.h" -#include "debug.h" -#include "gpio.h" -#include "interrupt.h" - - -//***************************************************************************** -// -//! \internal -//! Checks a GPIO base address. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! This function determines if a GPIO port base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static tBoolean -GPIOBaseValid(unsigned long ulPort) -{ - return((ulPort == GPIOA0_BASE) || - (ulPort == GPIOA1_BASE) || - (ulPort == GPIOA2_BASE) || - (ulPort == GPIOA3_BASE) || - (ulPort == GPIOA4_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the GPIO interrupt number. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! Given a GPIO base address, returns the corresponding interrupt number. -//! -//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. -// -//***************************************************************************** -long -GPIOGetIntNumber(unsigned long ulPort) -{ - unsigned int ulInt; - - // - // Determine the GPIO interrupt number for the given module. - // - switch(ulPort) - { - case GPIOA0_BASE: - { - ulInt = INT_GPIOA0; - break; - } - - case GPIOA1_BASE: - { - ulInt = INT_GPIOA1; - break; - } - - case GPIOA2_BASE: - { - ulInt = INT_GPIOA2; - break; - } - - case GPIOA3_BASE: - { - ulInt = INT_GPIOA3; - break; - } - - default: - { - return(-1); - } - } - - // - // Return GPIO interrupt number. - // - return(ulInt); -} - -//***************************************************************************** -// -//! Sets the direction and mode of the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port -//! \param ucPins is the bit-packed representation of the pin(s). -//! \param ulPinIO is the pin direction and/or mode. -//! -//! This function will set the specified pin(s) on the selected GPIO port -//! as either an input or output under software control, or it will set the -//! pin to be under hardware control. -//! -//! The parameter \e ulPinIO is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_DIR_MODE_IN -//! - \b GPIO_DIR_MODE_OUT -//! -//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as -//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin -//! will be programmed as a software controlled output. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note GPIOPadConfigSet() must also be used to configure the corresponding -//! pad(s) in order for them to propagate the signal to/from the GPIO. -//! -//! \return None. -// -//***************************************************************************** -void -GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT)); - - // - // Set the pin direction and mode. - // - HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ? - (HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) : - (HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins))); -} - -//***************************************************************************** -// -//! Gets the direction and mode of a pin. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPin is the pin number. -//! -//! This function gets the direction and control mode for a specified pin on -//! the selected GPIO port. The pin can be configured as either an input or -//! output under software control, or it can be under hardware control. The -//! type of control and direction are returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIODirModeSet(). -// -//***************************************************************************** -unsigned long -GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) -{ - unsigned long ulDir; - - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // Not needed because pin mask is pass in directly - //ucPin = 1 << ucPin; - - // - // Return the pin direction and mode. - // - ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR); - return(((ulDir & ucPin) ? 1 : 0)); -} - -//***************************************************************************** -// -//! Sets the interrupt type for the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! \param ulIntType specifies the type of interrupt trigger mechanism. -//! -//! This function sets up the various interrupt trigger mechanisms for the -//! specified pin(s) on the selected GPIO port. -//! -//! The parameter \e ulIntType is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_FALLING_EDGE -//! - \b GPIO_RISING_EDGE -//! - \b GPIO_BOTH_EDGES -//! - \b GPIO_LOW_LEVEL -//! - \b GPIO_HIGH_LEVEL -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note In order to avoid any spurious interrupts, the user must -//! ensure that the GPIO inputs remain stable for the duration of -//! this function. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - ASSERT((ulIntType == GPIO_FALLING_EDGE) || - (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) || - (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL)); - - // - // Set the pin interrupt type. - // - HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ? - (HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) : - (HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins))); - HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ? - (HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) : - (HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins))); - HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ? - (HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) : - (HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins))); -} - -//***************************************************************************** -// -//! Gets the interrupt type for a pin. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPin is the pin number. -//! -//! This function gets the interrupt type for a specified pin on the selected -//! GPIO port. The pin can be configured as a falling edge, rising edge, or -//! both edge detected interrupt, or it can be configured as a low level or -//! high level detected interrupt. The type of interrupt detection mechanism -//! is returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIOIntTypeSet(). -// -//***************************************************************************** -unsigned long -GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) -{ - unsigned long ulIBE, ulIS, ulIEV; - - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // Not needed because using the pin mask is pass in directly - //ucPin = 1 << ucPin; - - // - // Return the pin interrupt type. - // - ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE); - ulIS = HWREG(ulPort + GPIO_O_GPIO_IS); - ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV); - return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | - ((ulIEV & ucPin) ? 4 : 0)); -} - -//***************************************************************************** -// -//! Enables the specified GPIO interrupts. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ulIntFlags is the bit mask of the interrupt sources to enable. -//! -//! This function enables the indicated GPIO interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done -//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. -//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. -//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. -//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. -//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. -//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. -//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. -//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Enable the interrupts. - // - HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags; -} - -//***************************************************************************** -// -//! Disables the specified GPIO interrupts. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ulIntFlags is the bit mask of the interrupt sources to disable. -//! -//! This function disables the indicated GPIO interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done -//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. -//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. -//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. -//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. -//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. -//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. -//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. -//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Disable the interrupts. - // - HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags); -} - -//***************************************************************************** -// -//! Gets interrupt status for the specified GPIO port. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in GPIOIntEnable(). -// -//***************************************************************************** -long -GPIOIntStatus(unsigned long ulPort, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Return the interrupt status. - // - if(bMasked) - { - return(HWREG(ulPort + GPIO_O_GPIO_MIS)); - } - else - { - return(HWREG(ulPort + GPIO_O_GPIO_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the interrupt for the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! Clears the interrupt for the specified pin(s). -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to GPIOIntEnable(). -//! -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Clear the interrupts. - // - HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a GPIO port. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling -//! function. -//! -//! This function will ensure that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected from the selected -//! GPIO port. This function will also enable the corresponding GPIO interrupt -//! in the interrupt controller; individual pin interrupts and interrupt -//! sources must be enabled with GPIOIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ulPort = GPIOGetIntNumber(ulPort); - - // - // Register the interrupt handler. - // - IntRegister(ulPort, pfnIntHandler); - - // - // Enable the GPIO interrupt. - // - IntEnable(ulPort); -} - -//***************************************************************************** -// -//! Removes an interrupt handler for a GPIO port. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! This function will unregister the interrupt handler for the specified -//! GPIO port. This function will also disable the corresponding -//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts -//! and interrupt sources must be disabled with GPIOIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntUnregister(unsigned long ulPort) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ulPort = GPIOGetIntNumber(ulPort); - - // - // Disable the GPIO interrupt. - // - IntDisable(ulPort); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulPort); -} - -//***************************************************************************** -// -//! Reads the values present of the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! -//! The values at the specified pin(s) are read, as specified by \e ucPins. -//! Values are returned for both input and output pin(s), and the value -//! for pin(s) that are not specified by \e ucPins are set to 0. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return Returns a bit-packed byte providing the state of the specified -//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents -//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins -//! is returned as a 0. Bits 31:8 should be ignored. -// -//***************************************************************************** -long -GPIOPinRead(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Return the pin value(s). - // - return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2)))); -} - -//***************************************************************************** -// -//! Writes a value to the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! \param ucVal is the value to write to the pin(s). -//! -//! Writes the corresponding bit values to the output pin(s) specified by -//! \e ucPins. Writing to a pin configured as an input pin has no effect. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Write the pins. - // - HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal; -} - -//***************************************************************************** -// -//! Enables a GPIO port as a trigger to start a DMA transaction. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! This function enables a GPIO port to be used as a trigger to start a uDMA -//! transaction. The GPIO pin will still generate interrupts if the interrupt is -//! enabled for the selected pin. -//! -//! \return None. -// -//***************************************************************************** -void -GPIODMATriggerEnable(unsigned long ulPort) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Set the pin as a DMA trigger. - // - if(ulPort == GPIOA0_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1; - } - else if(ulPort == GPIOA1_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2; - } - else if(ulPort == GPIOA2_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4; - } - else if(ulPort == GPIOA3_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8; - } -} - -//***************************************************************************** -// -//! Disables a GPIO port as a trigger to start a DMA transaction. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! This function disables a GPIO port to be used as a trigger to start a uDMA -//! transaction. This function can be used to disable this feature if it was -//! enabled via a call to GPIODMATriggerEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -GPIODMATriggerDisable(unsigned long ulPort) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Set the pin as a DMA trigger. - // - if(ulPort == GPIOA0_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1; - } - else if(ulPort == GPIOA1_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2; - } - else if(ulPort == GPIOA2_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4; - } - else if(ulPort == GPIOA3_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8; - } -} - - -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.h deleted file mode 100755 index e1560089403..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// gpio.h -// -// Defines and Macros for GPIO API. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions -// in the ulIntFlags parameter. -// -//***************************************************************************** -#define GPIO_INT_DMA 0x00000100 -#define GPIO_INT_PIN_0 0x00000001 -#define GPIO_INT_PIN_1 0x00000002 -#define GPIO_INT_PIN_2 0x00000004 -#define GPIO_INT_PIN_3 0x00000008 -#define GPIO_INT_PIN_4 0x00000010 -#define GPIO_INT_PIN_5 0x00000020 -#define GPIO_INT_PIN_6 0x00000040 -#define GPIO_INT_PIN_7 0x00000080 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern void GPIODMATriggerEnable(unsigned long ulPort); -extern void GPIODMATriggerDisable(unsigned long ulPort); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags); -extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags); -extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags); -extern void GPIOIntRegister(unsigned long ulPort, - void (*pfnIntHandler)(void)); -extern void GPIOIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern long GPIOGetIntNumber(unsigned long ulPort); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.c deleted file mode 100755 index b4b87e75fee..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// hwspinlock.c -// -// Driver for the Apps-NWP spinlock -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup HwSpinLock_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ints.h" -#include "inc/hw_common_reg.h" -#include "hwspinlock.h" - -//***************************************************************************** -// Global semaphore register list -//***************************************************************************** -static const uint32_t HwSpinLock_RegLst[]= -{ - COMMON_REG_BASE + COMMON_REG_O_SPI_Properties_Register -}; - -//***************************************************************************** -// -//! Acquire specified spin lock. -//! -//! \param ui32LockID is one of the valid spin lock. -//! -//! This function acquires specified spin lock and will not retun util the -//! specified lock is acquired. -//! -//! The parameter \e ui32LockID should \b HWSPINLOCK_MCSPIS0. -//! -//! return None. -// -//***************************************************************************** -void HwSpinLockAcquire(uint32_t ui32LockID) -{ - uint32_t ui32BitPos; - uint32_t ui32SemVal; - uint32_t ui32RegAddr; - - // - // Extract the bit position from the - // LockID - // - ui32BitPos = ((ui32LockID >> 16) & 0x0FFF); - ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF]; - - // - // Set the corresponding - // ownership bits to 'b01 - // - ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos)); - - // - // Retry untill we succeed - // - do - { - HWREG(ui32RegAddr) = ui32SemVal; - } - while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) ); - -} - -//***************************************************************************** -// -//! Try to acquire specified spin lock. -//! -//! \param ui32LockID is one of the valid spin lock. -//! \param ui32Retry is the number of reties. -//! -//! This function tries acquire specified spin lock in \e ui32Retry retries. -//! -//! The parameter \e ui32Retry can be any value between 0 and 2^32. -//! -//! return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry) -{ - uint32_t ui32BitPos; - uint32_t ui32SemVal; - uint32_t ui32RegAddr; - - // - // Extract the bit position from the - // LockID - // - ui32BitPos = ((ui32LockID >> 16) & 0x0FFF); - ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF]; - - // - // Set the corresponding - // ownership bits to 'b01 - // - ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos)); - - // - // Check for 0 retry. - // - if(ui32Retry == 0) - { - ui32Retry = 1; - } - - // - // Retry the number of times specified - // - do - { - HWREG(ui32RegAddr) = ui32SemVal; - ui32Retry--; - } - while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) && ui32Retry ); - - - // - // Check the semaphore status - // - if(HWREG(ui32RegAddr) & (1 << ui32BitPos )) - { - return 0; - } - else - { - return -1; - } -} - -//***************************************************************************** -// -//! Release a previously owned spin lock -//! -//! \param ui32LockID is one of the valid spin lock. -//! -//! This function releases previously owned spin lock. -//! -//! \return None. -// -//***************************************************************************** -void HwSpinLockRelease(uint32_t ui32LockID) -{ - uint32_t ui32BitPos; - uint32_t ui32SemVal; - - // - // Extract the bit position from the - // lock id. - // - ui32BitPos = ((ui32LockID >> 16) & 0x00FF); - - // - // Release the spin lock, only if already owned - // - if(HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) & (1 << ui32BitPos )) - { - ui32SemVal = (0xFFFFFFFF & ~(0x3 << ui32BitPos)); - HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) = ui32SemVal; - } -} - -//***************************************************************************** -// -//! Get the current or previous ownership status. -//! -//! \param ui32LockID is one of the valid spin lock. -//! \param bCurrentStatus is \b true for current status, \b flase otherwise -//! -//! This function gets the current or previous ownership status of the -//! specified spin lock based on \e bCurrentStatus parameter. -//! -//! \return Returns \b HWSPINLOCK_OWNER_APPS, \b HWSPINLOCK_OWNER_NWP or -//! \b HWSPINLOCK_OWNER_NONE. -// -//***************************************************************************** -uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus) -{ - uint32_t ui32BitPos; - uint32_t ui32SemVal; - - if(bCurrentStatus) - { - // - // Extract the bit position from the - // lock id. - // - ui32BitPos = ((ui32LockID >> 16) & 0x00FF); - - // - // return semaphore - // - return((HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) >> ui32BitPos ) & 0x3 ); - } - else - { - // - // Extract the bit position - // - ui32BitPos = ((ui32LockID >> 24) & 0xFF); - - // - // Identify which register to read - // - if((ui32LockID & 0xF) > 4) - { - ui32SemVal = ((HWREG(COMMON_REG_BASE + - COMMON_REG_O_SEMAPHORE_PREV_OWNER1) >> ui32BitPos ) & 0x3); - } - else - { - ui32SemVal = ((HWREG(COMMON_REG_BASE + - COMMON_REG_O_SEMAPHORE_PREV_OWNER2) >> ui32BitPos ) & 0x3); - } - - // - // return the owner - // - return ui32SemVal; - } -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.h deleted file mode 100755 index 70277321208..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// hwspinlock.h -// -// Prototypes for the Apps-NWP spinlock. -// -//***************************************************************************** - -#ifndef __HWSPINLOCK_H__ -#define __HWSPINLOCK_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// values that can be passed to API as ui32LockID parameter -//***************************************************************************** -#define HWSPINLOCK_SSPI 0x02000000 - -//***************************************************************************** -// Values that are returned from HwSpinLockTest() -//***************************************************************************** -#define HWSPINLOCK_OWNER_APPS 0x00000001 -#define HWSPINLOCK_OWNER_NWP 0x00000002 -#define HWSPINLOCK_OWNER_NONE 0x00000000 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HwSpinLockAcquire(uint32_t ui32LockID); -extern int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry); -extern void HwSpinLockRelease(uint32_t ui32LockID); -extern uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __HWSPINLOCK_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.c deleted file mode 100755 index 8f4c00a17d8..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.c +++ /dev/null @@ -1,1013 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// i2s.c -// -// Driver for the I2S interface. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup I2S_api -//! @{ -// -//***************************************************************************** -#include "inc/hw_types.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_mcasp.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "i2s.h" - -//***************************************************************************** -// Macros -//***************************************************************************** -#define MCASP_GBL_RCLK 0x00000001 -#define MCASP_GBL_RHCLK 0x00000002 -#define MCASP_GBL_RSER 0x00000004 -#define MCASP_GBL_RSM 0x00000008 -#define MCASP_GBL_RFSYNC 0x00000010 -#define MCASP_GBL_XCLK 0x00000100 -#define MCASP_GBL_XHCLK 0x00000200 -#define MCASP_GBL_XSER 0x00000400 -#define MCASP_GBL_XSM 0x00000800 -#define MCASP_GBL_XFSYNC 0x00001000 - - -//***************************************************************************** -// -//! \internal -//! Releases the specifed submodule out of reset. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulFlag is one of the valid sub module. -//! -//! This function Releases the specifed submodule out of reset. -//! -//! \return None. -// -//***************************************************************************** -static void I2SGBLEnable(unsigned long ulBase, unsigned long ulFlag) -{ - unsigned long ulReg; - - // - // Read global control register - // - ulReg = HWREG(ulBase + MCASP_O_GBLCTL); - - // - // Remove the sub modules reset as specified by ulFlag parameter - // - ulReg |= ulFlag; - - // - // Write the configuration - // - HWREG(ulBase + MCASP_O_GBLCTL) = ulReg; - - // - // Wait for write completeion - // - while(HWREG(ulBase + MCASP_O_GBLCTL) != ulReg) - { - - } - -} - -//***************************************************************************** -// -//! Enables transmit and/or receive. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulMode is one of the valid modes. -//! -//! This function enables the I2S module in specified mode. The parameter -//! \e ulMode should be one of the following -//! -//! -\b I2S_MODE_TX_ONLY -//! -\b I2S_MODE_TX_RX_SYNC -//! -//! \return None. -// -//***************************************************************************** -void I2SEnable(unsigned long ulBase, unsigned long ulMode) -{ - // - // FSYNC and Bit clock are output only in master mode - // - if( HWREG(ulBase + MCASP_O_ACLKXCTL) & 0x20) - { - // - // Set FSYNC anc BitClk as output - // - HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000; - } - - - if(ulMode & 0x2) - { - // - // Remove Rx HCLK reset - // - I2SGBLEnable(ulBase, MCASP_GBL_RHCLK); - - // - // Remove Rx XCLK reset - // - I2SGBLEnable(ulBase, MCASP_GBL_RCLK); - - // - // Enable Rx SERDES(s) - // - I2SGBLEnable(ulBase, MCASP_GBL_RSER); - - // - // Enable Rx state machine - // - I2SGBLEnable(ulBase, MCASP_GBL_RSM); - - // - // Enable FSync generator - // - I2SGBLEnable(ulBase, MCASP_GBL_RFSYNC); - } - - - // - // Remove Tx HCLK reset - // - I2SGBLEnable(ulBase, MCASP_GBL_XHCLK); - - // - // Remove Tx XCLK reset - // - I2SGBLEnable(ulBase, MCASP_GBL_XCLK); - - - if(ulMode & 0x1) - { - // - // Enable Tx SERDES(s) - // - I2SGBLEnable(ulBase, MCASP_GBL_XSER); - - // - // Enable Tx state machine - // - I2SGBLEnable(ulBase, MCASP_GBL_XSM); - } - - // - // Enable FSync generator - // - I2SGBLEnable(ulBase, MCASP_GBL_XFSYNC); -} - -//***************************************************************************** -// -//! Disables transmit and/or receive. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function disables transmit and/or receive from I2S module. -//! -//! \return None. -// -//***************************************************************************** -void I2SDisable(unsigned long ulBase) -{ - // - // Reset all sub modules - // - HWREG(ulBase + MCASP_O_GBLCTL) = 0; - - // - // Wait for write to complete - // - while( HWREG(ulBase + MCASP_O_GBLCTL) != 0) - { - - } -} - -//***************************************************************************** -// -//! Waits to send data over the specified data line -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is one of the valid data lines. -//! \param ulData is the data to be transmitted. -//! -//! This function sends the \e ucData to the transmit register for the -//! specified data line. If there is no space available, this -//! function waits until there is space available before returning. -//! -//! \return None. -// -//***************************************************************************** -void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulData) -{ - // - // Compute register the offeset - // - ulDataLine = (ulDataLine-1) << 2; - - // - // Wait for free space in fifo - // - while(!( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA)) - { - - } - - // - // Write Data into the FIFO - // - HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData; -} - -//***************************************************************************** -// -//! Sends data over the specified data line -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is one of the valid data lines. -//! \param ulData is the data to be transmitted. -//! -//! This function writes the \e ucData to the transmit register for -//! the specified data line. This function does not block, so if there is no -//! space available, then \b -1 is returned, and the application must retry the -//! function later. -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -long I2SDataPutNonBlocking(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulData) -{ - - // - // Compute register the offeset - // - ulDataLine = (ulDataLine-1) << 2; - - // - // Send Data if fifo has free space - // - if( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA) - { - // - // Write data into the FIFO - // - HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData; - return 0; - } - - // - // FIFO is full - // - return(-1); -} - -//***************************************************************************** -// -//! Waits for data from the specified data line. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is one of the valid data lines. -//! \param pulData is pointer to receive data variable. -//! -//! This function gets data from the receive register for the specified -//! data line. If there are no data available, this function waits until a -//! receive before returning. -//! -//! \return None. -// -//***************************************************************************** -void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine, - unsigned long *pulData) -{ - - // - // Compute register the offeset - // - ulDataLine = (ulDataLine-1) << 2; - - // - // Wait for atleat on word in FIFO - // - while(!(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA)) - { - - } - - // - // Read the Data - // - *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine); -} - - -//***************************************************************************** -// -//! Receives data from the specified data line. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is one of the valid data lines. -//! \param pulData is pointer to receive data variable. -//! -//! This function gets data from the receive register for the specified -//! data line. -//! -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -long I2SDataGetNonBlocking(unsigned long ulBase, unsigned long ulDataLine, - unsigned long *pulData) -{ - - // - // Compute register the offeset - // - ulDataLine = (ulDataLine-1) << 2; - - // - // Check if data is available in FIFO - // - if(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA) - { - // - // Read the Data - // - *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine); - return 0; - } - - // - // FIFO is empty - // - return -1; -} - - -//***************************************************************************** -// -//! Sets the configuration of the I2S module. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulI2SClk is the rate of the clock supplied to the I2S module. -//! \param ulBitClk is the desired bit rate. -//! \param ulConfig is the data format. -//! -//! This function configures the I2S for operation in the specified data -//! format. The bit rate is provided in the \e ulBitClk parameter and the data -//! format in the \e ulConfig parameter. -//! -//! The \e ulConfig parameter is the logical OR of three values: the slot size -//! the data read/write port select, Master or Slave mode -//! -//! Follwoing selects the Master-Slave mode -//! -\b I2S_MODE_MASTER -//! -\b I2S_MODE_SLAVE -//! -//! Following selects the slot size: -//! -\b I2S_SLOT_SIZE_24 -//! -\b I2S_SLOT_SIZE_16 -//! -//! Following selects the data read/write port: -//! -\b I2S_PORT_DMA -//! -\b I2S_PORT_CPU -//! -//! \return None. -// -//***************************************************************************** -void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk, - unsigned long ulBitClk, unsigned long ulConfig) -{ - unsigned long ulHClkDiv; - unsigned long ulClkDiv; - unsigned long ulSlotSize; - unsigned long ulBitMask; - - // - // Calculate clock dividers - // - ulHClkDiv = ((ulI2SClk/ulBitClk)-1); - ulClkDiv = 0; - - // - // Check if HCLK divider is overflowing - // - if(ulHClkDiv > 0xFFF) - { - ulHClkDiv = 0xFFF; - - // - // Calculate clock divider - // - ulClkDiv = ((ulI2SClk/(ulBitClk * (ulHClkDiv + 1))) & 0x1F); - } - - // - // - // - ulClkDiv = ((ulConfig & I2S_MODE_SLAVE )?0x80:0xA0|ulClkDiv); - - HWREG(ulBase + MCASP_O_ACLKXCTL) = ulClkDiv; - - HWREG(ulBase + MCASP_O_AHCLKXCTL) = (0x8000|ulHClkDiv); - - // - // Write the Tx format register - // - HWREG(ulBase + MCASP_O_TXFMT) = (0x18000 | (ulConfig & 0x7FFF)); - - // - // Write the Rx format register - // - HWREG(ulBase + MCASP_O_RXFMT) = (0x18000 | ((ulConfig >> 16) &0x7FFF)); - - // - // Check if in master mode - // - if( ulConfig & I2S_MODE_SLAVE) - { - // - // Configure Tx FSync generator in I2S mode - // - HWREG(ulBase + MCASP_O_TXFMCTL) = 0x111; - - // - // Configure Rx FSync generator in I2S mode - // - HWREG(ulBase + MCASP_O_RXFMCTL) = 0x111; - } - else - { - // - // Configure Tx FSync generator in I2S mode - // - HWREG(ulBase + MCASP_O_TXFMCTL) = 0x113; - - // - // Configure Rx FSync generator in I2S mode - // - HWREG(ulBase + MCASP_O_RXFMCTL) = 0x113; - } - - // - // Compute Slot Size - // - ulSlotSize = ((((ulConfig & 0xFF) >> 4) + 1) * 2); - - // - // Creat the bit mask - // - ulBitMask = (0xFFFFFFFF >> (32 - ulSlotSize)); - - // - // Set Tx bit valid mask - // - HWREG(ulBase + MCASP_O_TXMASK) = ulBitMask; - - // - // Set Rx bit valid mask - // - HWREG(ulBase + MCASP_O_RXMASK) = ulBitMask; - - // - // Set Tx slot valid mask - // - HWREG(ulBase + MCASP_O_TXTDM) = 0x3; - - // - // Set Rx slot valid mask - // - HWREG(ulBase + MCASP_O_RXTDM) = 0x3; -} - -//***************************************************************************** -// -//! Configure and enable transmit FIFO. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulTxLevel is the transmit FIFO DMA request level. -//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO. -//! -//! This function configures and enable I2S transmit FIFO. -//! -//! The parameter \e ulTxLevel sets the level at which transmit DMA requests -//! are generated. This should be non-zero integer multiple of number of -//! serializers enabled as transmitters -//! -//! The parameter \e ulWordsPerTransfer sets the number of words that are -//! transferred from the transmit FIFO to the data line(s). This value must -//! equal the number of serializers used as transmitters. -//! -//! \return None. -// -//***************************************************************************** -void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulWordsPerTransfer) -{ - // - // Set transmit FIFO configuration and - // enable it - // - HWREG(ulBase + MCASP_0_WFIFOCTL) = ((1 <<16) | ((ulTxLevel & 0xFF) << 8) - | (ulWordsPerTransfer & 0x1F)); - -} - -//***************************************************************************** -// -//! Disables transmit FIFO. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function disables the I2S transmit FIFO. -//! -//! \return None. -// -//***************************************************************************** -void I2STxFIFODisable(unsigned long ulBase) -{ - // - // Disable transmit FIFO. - // - HWREG(ulBase + MCASP_0_WFIFOCTL) = 0; -} - -//***************************************************************************** -// -//! Configure and enable receive FIFO. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulRxLevel is the receive FIFO DMA request level. -//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO. -//! -//! This function configures and enable I2S receive FIFO. -//! -//! The parameter \e ulRxLevel sets the level at which receive DMA requests -//! are generated. This should be non-zero integer multiple of number of -//! serializers enabled as receivers. -//! -//! The parameter \e ulWordsPerTransfer sets the number of words that are -//! transferred to the receive FIFO from the data line(s). This value must -//! equal the number of serializers used as receivers. -//! -//! \return None. -// -//***************************************************************************** -void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel, - unsigned long ulWordsPerTransfer) -{ - // - // Set FIFO configuration - // - HWREG(ulBase + MCASP_0_RFIFOCTL) = ( (1 <<16) | ((ulRxLevel & 0xFF) << 8) - | (ulWordsPerTransfer & 0x1F)); - -} - -//***************************************************************************** -// -//! Disables receive FIFO. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function disables the I2S receive FIFO. -//! -//! \return None. -// -//***************************************************************************** -void I2SRxFIFODisable(unsigned long ulBase) -{ - // - // Disable receive FIFO. - // - HWREG(ulBase + MCASP_0_RFIFOCTL) = 0; -} - -//***************************************************************************** -// -//! Get the transmit FIFO status. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function gets the number of 32-bit words currently in the transmit -//! FIFO. -//! -//! \return Returns transmit FIFO status. -// -//***************************************************************************** -unsigned long I2STxFIFOStatusGet(unsigned long ulBase) -{ - // - // Return transmit FIFO level - // - return HWREG(ulBase + MCASP_0_WFIFOSTS); -} - -//***************************************************************************** -// -//! Get the receive FIFO status. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function gets the number of 32-bit words currently in the receive -//! FIFO. -//! -//! \return Returns receive FIFO status. -// -//***************************************************************************** -unsigned long I2SRxFIFOStatusGet(unsigned long ulBase) -{ - // - // Return receive FIFO level - // - return HWREG(ulBase + MCASP_0_RFIFOSTS); -} - -//***************************************************************************** -// -//! Configure the serializer in specified mode. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is the data line (serilizer) to be configured. -//! \param ulSerMode is the required serializer mode. -//! \param ulInActState sets the inactive state of the data line. -//! -//! This function configure and enable the serializer associated with the given -//! data line in specified mode. -//! -//! The paramenter \e ulDataLine selects to data line to be configured and -//! can be one of the following: -//! -\b I2S_DATA_LINE_0 -//! -\b I2S_DATA_LINE_1 -//! -//! The parameter \e ulSerMode can be one of the following: -//! -\b I2S_SER_MODE_TX -//! -\b I2S_SER_MODE_RX -//! -\b I2S_SER_MODE_DISABLE -//! -//! The parameter \e ulInActState can be one of the following -//! -\b I2S_INACT_TRI_STATE -//! -\b I2S_INACT_LOW_LEVEL -//! -\b I2S_INACT_LOW_HIGH -//! -//! \return Returns receive FIFO status. -// -//***************************************************************************** -void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulSerMode, unsigned long ulInActState) -{ - if( ulSerMode == I2S_SER_MODE_TX) - { - // - // Set the data line in output mode - // - HWREG(ulBase + MCASP_O_PDIR) |= ulDataLine; - } - else - { - // - // Set the data line in input mode - // - HWREG(ulBase + MCASP_O_PDIR) &= ~ulDataLine; - } - - // - // Set the serializer configuration. - // - HWREG(ulBase + MCASP_O_XRSRCTL0 + ((ulDataLine-1) << 2)) - = (ulSerMode | ulInActState); -} - -//***************************************************************************** -// -//! Enables individual I2S interrupt sources. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2S interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! -\b I2S_INT_XUNDRN -//! -\b I2S_INT_XSYNCERR -//! -\b I2S_INT_XLAST -//! -\b I2S_INT_XDATA -//! -\b I2S_INT_XSTAFRM -//! -\b I2S_INT_XDMA -//! -\b I2S_INT_ROVRN -//! -\b I2S_INT_RSYNCERR -//! -\b I2S_INT_RLAST -//! -\b I2S_INT_RDATA -//! -\b I2S_INT_RSTAFRM -//! -\b I2S_INT_RDMA -//! -//! \return None. -// -//***************************************************************************** -void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - - // - // Enable DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR ) - |= ((ulIntFlags &0xC0000000) >> 20); - - // - // Enable specific Tx Interrupts - // - HWREG(ulBase + MCASP_O_EVTCTLX) |= (ulIntFlags & 0xFF); - - // - // Enable specific Rx Interrupts - // - HWREG(ulBase + MCASP_O_EVTCTLR) |= ((ulIntFlags >> 16) & 0xFF); -} - -//***************************************************************************** -// -//! Disables individual I2S interrupt sources. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated I2S interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to I2SIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Disable DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) - |= ((ulIntFlags &0xC0000000) >> 20); - - // - // Disable specific Tx Interrupts - // - HWREG(ulBase + MCASP_O_EVTCTLX) &= ~(ulIntFlags & 0xFF); - - // - // Disable specific Rx Interrupts - // - HWREG(ulBase + MCASP_O_EVTCTLR) &= ~((ulIntFlags >> 16) & 0xFF); -} - - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function returns the raw interrupt status for I2S enumerated -//! as a bit field of values: -//! -\b I2S_STS_XERR -//! -\b I2S_STS_XDMAERR -//! -\b I2S_STS_XSTAFRM -//! -\b I2S_STS_XDATA -//! -\b I2S_STS_XLAST -//! -\b I2S_STS_XSYNCERR -//! -\b I2S_STS_XUNDRN -//! -\b I2S_STS_XDMA -//! -\b I2S_STS_RERR -//! -\b I2S_STS_RDMAERR -//! -\b I2S_STS_RSTAFRM -//! -\b I2S_STS_RDATA -//! -\b I2S_STS_RLAST -//! -\b I2S_STS_RSYNCERR -//! -\b I2S_STS_ROVERN -//! -\b I2S_STS_RDMA -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described above. -// -//***************************************************************************** -unsigned long I2SIntStatus(unsigned long ulBase) -{ - unsigned long ulStatus; - - // - // Get DMA interrupt status - // - ulStatus = - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW) << 20; - - ulStatus &= 0xC0000000; - - // - // Read Tx Interrupt status - // - ulStatus |= HWREG(ulBase + MCASP_O_TXSTAT); - - // - // Read Rx Interrupt status - // - ulStatus |= HWREG(ulBase + MCASP_O_RXSTAT) << 16; - - // - // Return the status - // - return ulStatus; -} - -//***************************************************************************** -// -//! Clears I2S interrupt sources. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulStatFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2S interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the value -//! describe in I2SIntStatus(). -//! -//! \return None. -// -//***************************************************************************** -void I2SIntClear(unsigned long ulBase, unsigned long ulStatFlags) -{ - // - // Clear DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) - |= ((ulStatFlags &0xC0000000) >> 20); - - // - // Clear Tx Interrupt - // - HWREG(ulBase + MCASP_O_TXSTAT) = ulStatFlags & 0x1FF ; - - // - // Clear Rx Interrupt - // - HWREG(ulBase + MCASP_O_RXSTAT) = (ulStatFlags >> 16) & 0x1FF; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a I2S interrupt. -//! -//! \param ulBase is the base address of the I2S module. -//! \param pfnHandler is a pointer to the function to be called when the -//! I2S interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! I2S interrupts must be enabled via I2SIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler - // - IntRegister(INT_I2S,pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_I2S); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a I2S interrupt. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a I2S interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void I2SIntUnregister(unsigned long ulBase) -{ - // - // Disable interrupt - // - IntDisable(INT_I2S); - - // - // Unregister the handler - // - IntUnregister(INT_I2S); - -} - -//***************************************************************************** -// -//! Set the active slots for Trasmitter -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulActSlot is the bit-mask of activ slots -//! -//! This function sets the active slots for the transmitter. By default both -//! the slots are active. The parameter \e ulActSlot is logical OR follwoing -//! values: -//! -\b I2S_ACT_SLOT_EVEN -//! -\b I2S_ACT_SLOT_ODD -//! -//! \return None. -// -//***************************************************************************** -void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot) -{ - HWREG(ulBase + MCASP_O_TXTDM) = ulActSlot; -} - -//***************************************************************************** -// -//! Set the active slots for Receiver -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulActSlot is the bit-mask of activ slots -//! -//! This function sets the active slots for the receiver. By default both -//! the slots are active. The parameter \e ulActSlot is logical OR follwoing -//! values: -//! -\b I2S_ACT_SLOT_EVEN -//! -\b I2S_ACT_SLOT_ODD -//! -//! \return None. -// -//***************************************************************************** -void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot) -{ - HWREG(ulBase + MCASP_O_RXTDM) = ulActSlot; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.h deleted file mode 100755 index 260308fe7e1..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// i2s.h -// -// Defines and Macros for the I2S. -// -//***************************************************************************** - -#ifndef __I2S_H__ -#define __I2S_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// I2S DMA ports. -// -//***************************************************************************** -#define I2S_TX_DMA_PORT 0x4401E200 -#define I2S_RX_DMA_PORT 0x4401E280 - -//***************************************************************************** -// -// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter. -// -//***************************************************************************** -#define I2S_SLOT_SIZE_8 0x00300032 -#define I2S_SLOT_SIZE_16 0x00700074 -#define I2S_SLOT_SIZE_24 0x00B000B6 - - -#define I2S_PORT_CPU 0x00080008 -#define I2S_PORT_DMA 0x00000000 - -#define I2S_MODE_MASTER 0x00000000 -#define I2S_MODE_SLAVE 0x00008000 - -//***************************************************************************** -// -// Values that can be passed as ulDataLine parameter. -// -//***************************************************************************** -#define I2S_DATA_LINE_0 0x00000001 -#define I2S_DATA_LINE_1 0x00000002 - -//***************************************************************************** -// -// Values that can be passed to I2SSerializerConfig() as the ulSerMode -// parameter. -// -//***************************************************************************** -#define I2S_SER_MODE_TX 0x00000001 -#define I2S_SER_MODE_RX 0x00000002 -#define I2S_SER_MODE_DISABLE 0x00000000 - -//***************************************************************************** -// -// Values that can be passed to I2SSerializerConfig() as the ulInActState -// parameter. -// -//***************************************************************************** -#define I2S_INACT_TRI_STATE 0x00000000 -#define I2S_INACT_LOW_LEVEL 0x00000008 -#define I2S_INACT_HIGH_LEVEL 0x0000000C - -//***************************************************************************** -// -// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the -// ulIntFlags parameter. -// -//***************************************************************************** -#define I2S_INT_XUNDRN 0x00000001 -#define I2S_INT_XSYNCERR 0x00000002 -#define I2S_INT_XLAST 0x00000010 -#define I2S_INT_XDATA 0x00000020 -#define I2S_INT_XSTAFRM 0x00000080 -#define I2S_INT_XDMA 0x80000000 -#define I2S_INT_ROVRN 0x00010000 -#define I2S_INT_RSYNCERR 0x00020000 -#define I2S_INT_RLAST 0x00100000 -#define I2S_INT_RDATA 0x00200000 -#define I2S_INT_RSTAFRM 0x00800000 -#define I2S_INT_RDMA 0x40000000 - - -//***************************************************************************** -// -// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet -// -//***************************************************************************** -#define I2S_ACT_SLOT_EVEN 0x00000001 -#define I2S_ACT_SLOT_ODD 0x00000002 - -//***************************************************************************** -// -// Values that can be passed to I2SIntClear() as the -// ulIntFlags parameter and returned from I2SIntStatus(). -// -//***************************************************************************** -#define I2S_STS_XERR 0x00000100 -#define I2S_STS_XDMAERR 0x00000080 -#define I2S_STS_XSTAFRM 0x00000040 -#define I2S_STS_XDATA 0x00000020 -#define I2S_STS_XLAST 0x00000010 -#define I2S_STS_XSYNCERR 0x00000002 -#define I2S_STS_XUNDRN 0x00000001 -#define I2S_STS_XDMA 0x80000000 -#define I2S_STS_RERR 0x01000000 -#define I2S_STS_RDMAERR 0x00800000 -#define I2S_STS_RSTAFRM 0x00400000 -#define I2S_STS_RDATA 0x00200000 -#define I2S_STS_RLAST 0x00100000 -#define I2S_STS_RSYNCERR 0x00020000 -#define I2S_STS_ROVERN 0x00010000 -#define I2S_STS_RDMA 0x40000000 - -//***************************************************************************** -// -// Values that can be passed to I2SEnable() as the ulMode parameter. -// -//***************************************************************************** -#define I2S_MODE_TX_ONLY 0x00000001 -#define I2S_MODE_TX_RX_SYNC 0x00000003 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void I2SEnable(unsigned long ulBase, unsigned long ulMode); -extern void I2SDisable(unsigned long ulBase); - -extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulData); -extern long I2SDataPutNonBlocking(unsigned long ulBase, - unsigned long ulDataLine, unsigned long ulData); - -extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine, - unsigned long *pulData); -extern long I2SDataGetNonBlocking(unsigned long ulBase, - unsigned long ulDataLine, unsigned long *pulData); - -extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk, - unsigned long ulBitClk, unsigned long ulConfig); - -extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulWordsPerTransfer); -extern void I2STxFIFODisable(unsigned long ulBase); -extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel, - unsigned long ulWordsPerTransfer); -extern void I2SRxFIFODisable(unsigned long ulBase); -extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase); -extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase); - -extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulSerMode, unsigned long ulInActState); - -extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long I2SIntStatus(unsigned long ulBase); -extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void I2SIntUnregister(unsigned long ulBase); -extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot); -extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif //__I2S_H__ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.c deleted file mode 100755 index a4a447129b0..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.c +++ /dev/null @@ -1,770 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// interrupt.c -// -// Driver for the NVIC Interrupt Controller. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup interrupt_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "cpu.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// This is a mapping between priority grouping encodings and the number of -// preemption priority bits. -// -//***************************************************************************** -static const unsigned long g_pulPriority[] = -{ - NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, - NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, - NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number and the register that contains -// the priority encoding for that interrupt. -// -//***************************************************************************** -static const unsigned long g_pulRegs[] = -{ - 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, - NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, - NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, - NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, - NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, - NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, - NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37, - NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43, - NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48 - -}; - - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt enable for that -// interrupt. -// -//***************************************************************************** -static const unsigned long g_pulEnRegs[] = -{ - NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt disable for that -// interrupt. -// -//***************************************************************************** -static const unsigned long g_pulDisRegs[] = -{ - NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt pend for that interrupt. -// -//***************************************************************************** -static const unsigned long g_pulPendRegs[] = -{ - NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt unpend for that -// interrupt. -// -//***************************************************************************** -static const unsigned long g_pulUnpendRegs[] = -{ - NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4, - NVIC_UNPEND5 -}; - - -//***************************************************************************** -// -//! \internal -//! The default interrupt handler. -//! -//! This is the default interrupt handler for all interrupts. It simply loops -//! forever so that the system state is preserved for observation by a -//! debugger. Since interrupts should be disabled before unregistering the -//! corresponding handler, this should never be called. -//! -//! \return None. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! Enables the processor interrupt. -//! -//! Allows the processor to respond to interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. -//! -//! \note Previously, this function had no return value. As such, it was -//! possible to include interrupt.h and call this function without -//! having included hw_types.h. Now that the return is a -//! tBoolean, a compiler error will occur in this case. The solution -//! is to include hw_types.h before including interrupt.h. -//! -//! \return Returns \b true if interrupts were disabled when the function was -//! called or \b false if they were initially enabled. -// -//***************************************************************************** -tBoolean -IntMasterEnable(void) -{ - // - // Enable processor interrupts. - // - return(CPUcpsie()); -} - -//***************************************************************************** -// -//! Disables the processor interrupt. -//! -//! Prevents the processor from receiving interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. -//! -//! \note Previously, this function had no return value. As such, it was -//! possible to include interrupt.h and call this function without -//! having included hw_types.h. Now that the return is a -//! tBoolean, a compiler error will occur in this case. The solution -//! is to include hw_types.h before including interrupt.h. -//! -//! \return Returns \b true if interrupts were already disabled when the -//! function was called or \b false if they were initially enabled. -// -//***************************************************************************** -tBoolean -IntMasterDisable(void) -{ - // - // Disable processor interrupts. - // - return(CPUcpsid()); -} -//***************************************************************************** -// -//! Sets the NVIC VTable base. -//! -//! \param ulVtableBase specifies the new base address of VTable -//! -//! This function is used to specify a new base address for the VTable. -//! This function must be called before using IntRegister() for registering -//! any interrupt handler. -//! -//! -//! \return None. -// -//***************************************************************************** -void -IntVTableBaseSet(unsigned long ulVtableBase) -{ - HWREG(NVIC_VTABLE) = ulVtableBase; -} - -//***************************************************************************** -// -//! Registers a function to be called when an interrupt occurs. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! \param pfnHandler is a pointer to the function to be called. -//! -//! This function is used to specify the handler function to be called when the -//! given interrupt is asserted to the processor. When the interrupt occurs, -//! if it is enabled (via IntEnable()), the handler function will be called in -//! interrupt context. Since the handler function can preempt other code, care -//! must be taken to protect memory or peripherals that are accessed by the -//! handler and other non-handler code. -//! -//! -//! \return None. -// -//***************************************************************************** -void -IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) -{ - unsigned long *ulNvicTbl; - - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE); - ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler; -} - -//***************************************************************************** -// -//! Unregisters the function to be called when an interrupt occurs. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! -//! This function is used to indicate that no handler should be called when the -//! given interrupt is asserted to the processor. The interrupt source will be -//! automatically disabled (via IntDisable()) if necessary. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -IntUnregister(unsigned long ulInterrupt) -{ - unsigned long *ulNvicTbl; - - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE); - ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler; -} - -//***************************************************************************** -// -//! Sets the priority grouping of the interrupt controller. -//! -//! \param ulBits specifies the number of bits of preemptable priority. -//! -//! This function specifies the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. The range of -//! the grouping values are dependent upon the hardware implementation; on -//! the CC3200 , three bits are available for hardware interrupt -//! prioritization and therefore priority grouping values of three through -//! seven have the same effect. -//! -//! \return None. -// -//***************************************************************************** -void -IntPriorityGroupingSet(unsigned long ulBits) -{ - // - // Check the arguments. - // - ASSERT(ulBits < NUM_PRIORITY); - - // - // Set the priority grouping. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; -} - -//***************************************************************************** -// -//! Gets the priority grouping of the interrupt controller. -//! -//! This function returns the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. -//! -//! \return The number of bits of preemptable priority. -// -//***************************************************************************** -unsigned long -IntPriorityGroupingGet(void) -{ - unsigned long ulLoop, ulValue; - - // - // Read the priority grouping. - // - ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; - - // - // Loop through the priority grouping values. - // - for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++) - { - // - // Stop looping if this value matches. - // - if(ulValue == g_pulPriority[ulLoop]) - { - break; - } - } - - // - // Return the number of priority bits. - // - return(ulLoop); -} - -//***************************************************************************** -// -//! Sets the priority of an interrupt. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! \param ucPriority specifies the priority of the interrupt. -//! -//! This function is used to set the priority of an interrupt. When multiple -//! interrupts are asserted simultaneously, the ones with the highest priority -//! are processed before the lower priority interrupts. Smaller numbers -//! correspond to higher interrupt priorities; priority 0 is the highest -//! interrupt priority. -//! -//! The hardware priority mechanism will only look at the upper N bits of the -//! priority level (where N is 3), so any prioritization must be performed in -//! those bits. The remaining bits can be used to sub-prioritize the interrupt -//! sources, and may be used by the hardware priority mechanism on a future -//! part. This arrangement allows priorities to migrate to different NVIC -//! implementations without changing the gross prioritization of the -//! interrupts. -//! -//! The parameter \e ucPriority can be any one of the following -//! -\b INT_PRIORITY_LVL_0 -//! -\b INT_PRIORITY_LVL_1 -//! -\b INT_PRIORITY_LVL_2 -//! -\b INT_PRIORITY_LVL_3 -//! -\b INT_PRIORITY_LVL_4 -//! -\b INT_PRIORITY_LVL_5 -//! -\b INT_PRIORITY_LVL_6 -//! -\b INT_PRIORITY_LVL_7 -//! -//! \return None. -// -//***************************************************************************** -void -IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); - - // - // Set the interrupt priority. - // - ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); - ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); - ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); - HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; -} - -//***************************************************************************** -// -//! Gets the priority of an interrupt. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! -//! This function gets the priority of an interrupt. See IntPrioritySet() for -//! a definition of the priority value. -//! -//! \return Returns the interrupt priority, or -1 if an invalid interrupt was -//! specified. -// -//***************************************************************************** -long -IntPriorityGet(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); - - // - // Return the interrupt priority. - // - return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & - 0xFF); -} - -//***************************************************************************** -// -//! Enables an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be enabled. -//! -//! The specified interrupt is enabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! \return None. -// -//***************************************************************************** -void -IntEnable(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to enable. - // - if(ulInterrupt == FAULT_MPU) - { - // - // Enable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_BUS) - { - // - // Enable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_USAGE) - { - // - // Enable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Enable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt >= 16) - { - // - // Enable the general interrupt. - // - HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) = - 1 << ((ulInterrupt - 16) & 31); - __asm(" dsb "); - __asm(" isb "); - } -} - -//***************************************************************************** -// -//! Disables an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be disabled. -//! -//! The specified interrupt is disabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! \return None. -// -//***************************************************************************** -void -IntDisable(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to disable. - // - if(ulInterrupt == FAULT_MPU) - { - // - // Disable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_BUS) - { - // - // Disable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_USAGE) - { - // - // Disable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Disable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt >= 16) - { - // - // Disable the general interrupt. - // - HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) = - 1 << ((ulInterrupt - 16) & 31); - __asm(" dsb "); - __asm(" isb "); - } - -} - -//***************************************************************************** -// -//! Pends an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be pended. -//! -//! The specified interrupt is pended in the interrupt controller. This will -//! cause the interrupt controller to execute the corresponding interrupt -//! handler at the next available time, based on the current interrupt state -//! priorities. For example, if called by a higher priority interrupt handler, -//! the specified interrupt handler will not be called until after the current -//! interrupt handler has completed execution. The interrupt must have been -//! enabled for it to be called. -//! -//! \return None. -// -//***************************************************************************** -void -IntPendSet(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to pend. - // - if(ulInterrupt == FAULT_NMI) - { - // - // Pend the NMI interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_PENDSV) - { - // - // Pend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Pend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt >= 16) - { - // - // Pend the general interrupt. - // - HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) = - 1 << ((ulInterrupt - 16) & 31); - __asm(" dsb "); - __asm(" isb "); - } - -} - -//***************************************************************************** -// -//! Unpends an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be unpended. -//! -//! The specified interrupt is unpended in the interrupt controller. This will -//! cause any previously generated interrupts that have not been handled yet -//! (due to higher priority interrupts or the interrupt no having been enabled -//! yet) to be discarded. -//! -//! \return None. -// -//***************************************************************************** -void -IntPendClear(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to unpend. - // - if(ulInterrupt == FAULT_PENDSV) - { - // - // Unpend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Unpend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; - } - else if(ulInterrupt >= 16) - { - // - // Unpend the general interrupt. - // - HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) = - 1 << ((ulInterrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Sets the priority masking level -//! -//! \param ulPriorityMask is the priority level that will be masked. -//! -//! This function sets the interrupt priority masking level so that all -//! interrupts at the specified or lesser priority level is masked. This -//! can be used to globally disable a set of interrupts with priority below -//! a predetermined threshold. A value of 0 disables priority -//! masking. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater will be blocked. -//! -//! The hardware priority mechanism will only look at the upper N bits of the -//! priority level (where N is 3), so any -//! prioritization must be performed in those bits. -//! -//! \return None. -// -//***************************************************************************** -void -IntPriorityMaskSet(unsigned long ulPriorityMask) -{ - CPUbasepriSet(ulPriorityMask); -} - -//***************************************************************************** -// -//! Gets the priority masking level -//! -//! This function gets the current setting of the interrupt priority masking -//! level. The value returned is the priority level such that all interrupts -//! of that and lesser priority are masked. A value of 0 means that priority -//! masking is disabled. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater will be blocked. -//! -//! The hardware priority mechanism will only look at the upper N bits of the -//! priority level (where N is 3), so any -//! prioritization must be performed in those bits. -//! -//! \return Returns the value of the interrupt priority level mask. -// -//***************************************************************************** -unsigned long -IntPriorityMaskGet(void) -{ - return(CPUbasepriGet()); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.h deleted file mode 100755 index 876f7a4e0e1..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// interrupt.h -// -// Prototypes for the NVIC Interrupt Controller Driver. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// A union that describes the entries of the vector table. The union is needed -// since the first entry is the stack pointer and the remainder are function -// pointers. -// -//***************************************************************************** -typedef union -{ - void (*pfnHandler)(void); - unsigned long ulPtr; -} -uVectorEntry; - - -//***************************************************************************** -// -// Macro to generate an interrupt priority mask based on the number of bits -// of priority supported by the hardware. -// -//***************************************************************************** -#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) - -//***************************************************************************** -// Interrupt priority levels -//***************************************************************************** -#define INT_PRIORITY_LVL_0 0x00 -#define INT_PRIORITY_LVL_1 0x20 -#define INT_PRIORITY_LVL_2 0x40 -#define INT_PRIORITY_LVL_3 0x60 -#define INT_PRIORITY_LVL_4 0x80 -#define INT_PRIORITY_LVL_5 0xA0 -#define INT_PRIORITY_LVL_6 0xC0 -#define INT_PRIORITY_LVL_7 0xE0 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean IntMasterEnable(void); -extern tBoolean IntMasterDisable(void); -extern void IntVTableBaseSet(unsigned long ulVtableBase); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); -extern void IntPendSet(unsigned long ulInterrupt); -extern void IntPendClear(unsigned long ulInterrupt); -extern void IntPriorityMaskSet(unsigned long ulPriorityMask); -extern unsigned long IntPriorityMaskGet(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.c deleted file mode 100755 index 79b77ba9b77..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.c +++ /dev/null @@ -1,884 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// pin.c -// -// Mapping of peripherals to pins. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup pin_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ocp_shared.h" -#include "pin.h" - -//***************************************************************************** -// Macros -//***************************************************************************** -#define PAD_MODE_MASK 0x0000000F -#define PAD_STRENGTH_MASK 0x000000E0 -#define PAD_TYPE_MASK 0x00000310 -#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \ - OCP_SHARED_O_GPIO_PAD_CONFIG_0)) - -//***************************************************************************** -// PIN to PAD matrix -//***************************************************************************** -static const unsigned long g_ulPinToPadMap[64] = -{ - 10,11,12,13,14,15,16,17,255,255,18, - 19,20,21,22,23,24,40,28,29,25,255, - 255,255,255,255,255,255,255,255,255,255,255, - 255,255,255,255,255,255,255,255,255,255,255, - 31,255,255,255,255,0,255,32,30,255,1, - 255,2,3,4,5,6,7,8,9 -}; - - -//***************************************************************************** -// -//! Configures pin mux for the specified pin. -//! -//! \param ulPin is a valid pin. -//! \param ulPinMode is one of the valid mode -//! -//! This function configures the pin mux that selects the peripheral function -//! associated with a particular SOC pin. Only one peripheral function at a -//! time can be associated with a pin, and each peripheral function should -//! only be associated with a single pin at a time. -//! -//! \return none -// -//***************************************************************************** -void PinModeSet(unsigned long ulPin,unsigned long ulPinMode) -{ - - unsigned long ulPad; - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Set the mode. - // - HWREG(ulPad) = (((HWREG(ulPad) & ~PAD_MODE_MASK) | ulPinMode) & ~(3<<10)); - -} - -//***************************************************************************** -// -//! Gets current pin mux configuration of specified pin. -//! -//! \param ulPin is a valid pin. -//! -//! This function get the current configuration of the pin mux. -//! -//! \return Returns current pin mode if \e ulPin is valid, 0xFF otherwise. -// -//***************************************************************************** -unsigned long PinModeGet(unsigned long ulPin) -{ - - unsigned long ulPad; - - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ; - - // - // return the mode. - // - return (HWREG(ulPad) & PAD_MODE_MASK); - -} - -//***************************************************************************** -// -//! Sets the direction of the specified pin(s). -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinIO is the pin direction and/or mode. -//! -//! This function configures the specified pin(s) as either input only or -//! output only or it configures the pin to be under hardware control. -//! -//! The parameter \e ulPinIO is an enumerated data type that can be one of -//! the following values: -//! -//! - \b PIN_DIR_MODE_IN -//! - \b PIN_DIR_MODE_OUT -//! - \b PIN_DIR_MODE_HW -//! -//! where \b PIN_DIR_MODE_IN specifies that the pin is programmed as a -//! input only, \b PIN_DIR_MODE_OUT specifies that the pin is -//! programmed output only, and \b PIN_DIR_MODE_HW specifies that the pin is -//! placed under hardware control. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO) -{ - unsigned long ulPad; - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Set the direction - // - HWREG(ulPad) = ((HWREG(ulPad) & ~0xC00) | ulPinIO); -} - -//***************************************************************************** -// -//! Gets the direction of a pin. -//! -//! \param ulPin is one of the valid pin. -//! -//! This function gets the direction and control mode for a specified pin on -//! the selected GPIO port. The pin can be configured as either an input only -//! or output only, or it can be under hardware control. The type of control -//! and direction are returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIODirModeSet(). -// -//***************************************************************************** -unsigned long PinDirModeGet(unsigned long ulPin) -{ - unsigned long ulPad; - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Return the direction - // - return ((HWREG(ulPad) & 0xC00)); -} - -//***************************************************************************** -// -//! Gets Pin output drive strength and Type -//! -//! \param ulPin is one of the valid pin -//! \param pulPinStrength is pointer to storage for output drive strength -//! \param pulPinType is pinter to storage for pin type -//! -//! This function gets the pin type and output drive strength for the pin -//! specified by \e ulPin parameter. Parameters \e pulPinStrength and -//! \e pulPinType corresponds to the values used in PinConfigSet(). -//! -//! -//! \return None. -// -//***************************************************************************** -void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength, - unsigned long *pulPinType) -{ - - unsigned long ulPad; - - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - - // - // Get the type - // - *pulPinType = (HWREG(ulPad) & PAD_TYPE_MASK); - - // - // Get the output drive strength - // - *pulPinStrength = (HWREG(ulPad) & PAD_STRENGTH_MASK); - -} - -//***************************************************************************** -// -//! Configure Pin output drive strength and Type -//! -//! \param ulPin is one of the valid pin -//! \param ulPinStrength is logical OR of valid output drive strengths. -//! \param ulPinType is one of the valid pin type. -//! -//! This function sets the pin type and strength for the pin specified by -//! \e ulPin parameter. -//! -//! The parameter \e ulPinStrength should be one of the following -//! - \b PIN_STRENGTH_2MA -//! - \b PIN_STRENGTH_4MA -//! - \b PIN_STRENGTH_6MA -//! -//! -//! The parameter \e ulPinType should be one of the following -//! For standard type -//! -//! - \b PIN_TYPE_STD -//! - \b PIN_TYPE_STD_PU -//! - \b PIN_TYPE_STD_PD -//! -//! And for Open drain type -//! -//! - \b PIN_TYPE_OD -//! - \b PIN_TYPE_OD_PU -//! - \b PIN_TYPE_OD_PD -//! -//! \return None. -// -//***************************************************************************** -void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength, - unsigned long ulPinType) -{ - - unsigned long ulPad; - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Write the register - // - if(ulPinType == PIN_TYPE_ANALOG) - { - // - // Isolate the input - // - HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8)); - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Isolate the output - // - HWREG(ulPad) = 0xC00; - - } - else - { - // - // Enable the input - // - HWREG(0x4402E144) &= ~((0x80 << ulPad) & (0x1E << 8)); - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Write the configuration - // - HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) | - (ulPinStrength | ulPinType )); - } - - -} - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by UART peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The UART pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! -//! \note This function cannot be used to turn any pin into a UART pin; it -//! only sets the pin mode and configures it for proper UART operation. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode) -{ - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD); -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by I2C peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The I2C pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! the pin. -//! -//! -//! \note This function cannot be used to turn any pin into a I2C pin; it -//! only sets the pin mode and configures it for proper I2C operation. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode) -{ - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for open-drain operation with a weak pull-up. - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_OD_PU); -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by SPI peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The SPI pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a SPI pin; it -//! only sets the pin mode and configures it for proper SPI operation. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode) -{ - - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); - -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by I2S peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The I2S pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a I2S pin; it -//! only sets the pin mode and configures it for proper I2S operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode) -{ - - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); - -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by Timer peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The timer PWM pins must be properly configured for the Timer peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin; other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! -//! \note This function cannot be used to turn any pin into a timer PWM pin; it -//! only sets the pin mode and configures it for proper timer PWM operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode) -{ - - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by Camera peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The Camera pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a Camera pin; it -//! only sets the pin mode and configures it for proper Camera operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode) -{ - - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); - -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by GPIO peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! \param bOpenDrain is one to decide either OpenDrain or STD -//! -//! The GPIO pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,tBoolean bOpenDrain) -{ - - // - // Set the pin for standard push-pull operation. - // - if(bOpenDrain) - { - PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_OD); - } - else - { - PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_STD); - } - - // - // Set the pin to specified mode - // - PinModeSet(ulPin, ulPinMode); - -} - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by ADC -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The ADC pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a ADC pin; it -//! only sets the pin mode and configures it for proper ADC operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode) -{ - // - // Configure the Pin - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by SD Host peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The MMC pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a SD Host pin; it -//! only sets the pin mode and configures it for proper SD Host operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode) -{ - // - // Set pin mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Configure the Pin - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD); - -} - - -//***************************************************************************** -// -//! Sets the hysteresis for all the pins -//! -//! \param ulHysteresis is one of the valid predefined hysterisys values -//! -//! This function sets the hysteresis vlaue for all the pins. The parameter -//! \e ulHysteresis can be on one the following: -//! -\b PIN_HYSTERESIS_OFF - To turn Off hysteresis, default on POR -//! -\b PIN_HYSTERESIS_10 - To turn On hysteresis, 10% -//! -\b PIN_HYSTERESIS_20 - To turn On hysteresis, 20% -//! -\b PIN_HYSTERESIS_30 - To turn On hysteresis, 30% -//! -\b PIN_HYSTERESIS_40 - To turn On hysteresis, 40% -//! -//! \return None. -// -//***************************************************************************** -void PinHysteresisSet(unsigned long ulHysteresis) -{ - unsigned long ulRegValue; - - // - // Read the current value - // - ulRegValue = (HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) - & ~(0x0000001C)); - - // - // Set the new Hysteresis - // - if( ulHysteresis != PIN_HYSTERESIS_OFF ) - { - ulRegValue |= (ulHysteresis & 0x0000001C); - } - - // - // Write the new value - // - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) = ulRegValue; -} - -//***************************************************************************** -// -//! Sets the level of the pin when locked -//! -//! \param ulPin is one of the valid pin. -//! \param ucLevel is the level the pin drives when locked -//! -//! This function sets the pin level when the pin is locked using -//! \sa PinLock() API. -//! -//! By default all pins are set to drive 0. -//! -//! \note Use case is to park the pins when entering LPDS -//! -//! \return None. -// -//***************************************************************************** -void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel) -{ - unsigned long ulPad; - - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Get the required bit - // - ulPad = 1 << ulPad; - - if(ucLevel) - { - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) |= ulPad; - } - else - { - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) &= ~ulPad; - } - } -} - -//***************************************************************************** -// -//! Locks all the pins to configured level(s). -//! -//! \param ulOutEnable the bit-packed representation of pins to be set as output -//! -//! This function locks all the pins to the pre-configure level. By default -//! the pins are set to drive 0. Default level can be changed using -//! \sa PinLockLevelSet() API. -//! -//! The \e ulOutEnable paramter is bit-packed representation of pins that -//! are required to be enabled as output. If a bit is set 1, the corresponding -//! pin (as shown below) are set and locked as output. -//! -//! |------|-----------------------------------------------| -//! | Bit |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |------|-----------------------------------------------| -//! | Pin |xx|xx|20|19|30|29|21|17|16|15|14|13|12|11|08|07| -//! |------|-----------------------------------------------| -//! -//! |------|-----------------------------------------------| -//! | Bit |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |------|-----------------------------------------------| -//! | Pin |06|05|04|03|02|01|64|63|62|61|60|59|58|57|55|50| -//! |------|-----------------------------------------------| -//! -//! -//! \note Use case is to park the pins when entering LPDS -//! -//! \return None. -// -//***************************************************************************** -void PinLock(unsigned long ulOutEnable) -{ - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Enable/disable the pin(s) output - // - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_7 ) = ~ulOutEnable; - - // - // Lock the pins to selected levels - // - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) |= (3 << 24); - } -} - -//***************************************************************************** -// -//! Unlocks all the pins. -//! -//! This function unlocks all the pins and can be used for peripheral function. -//! -//! By default all the pins are in unlocked state. -//! -//! \note Use case is to un-park the pins when exiting LPDS -//! -//! \return None. -// -//***************************************************************************** -void PinUnlock() -{ - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Unlock the pins - // - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) &= ~(3 << 24); - } -} - -//***************************************************************************** -// -// Gets pad number from pin number -// -// \param ulPin is a valid pin number -// -// This function return the pad corresponding to the specified pin -// -// \return Pad number on success, 0xFF otherwise -// -//***************************************************************************** -unsigned long PinToPadGet(unsigned long ulPin) -{ - // - // Return the corresponding Pad - // - return g_ulPinToPadMap[ulPin & 0x3F]; -} - - -//***************************************************************************** -// -// Gets pin number from pad number -// -// \param ulPad is a valid pad number -// -// This function return the pin corresponding to the specified pad -// -// \return Pin number on success, 0xFF otherwise -// -//***************************************************************************** -unsigned long PinFromPadGet(unsigned long ulPad) -{ - unsigned long ulPin; - - // - // search and return the pin number - // - for(ulPin=0; ulPin < sizeof(g_ulPinToPadMap)/4; ulPin++) - { - if(g_ulPinToPadMap[ulPin] == ulPad) - { - return ulPin; - } - } - - return 0xFF; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.h deleted file mode 100755 index ca4684018e0..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// pin.h -// -// Defines and Macros for the pin mux module -// -//***************************************************************************** - -#ifndef __PIN_H__ -#define __PIN_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// Macros Defining Pins -//***************************************************************************** - -#define PIN_01 0x00000000 -#define PIN_02 0x00000001 -#define PIN_03 0x00000002 -#define PIN_04 0x00000003 -#define PIN_05 0x00000004 -#define PIN_06 0x00000005 -#define PIN_07 0x00000006 -#define PIN_08 0x00000007 -#define PIN_11 0x0000000A -#define PIN_12 0x0000000B -#define PIN_13 0x0000000C -#define PIN_14 0x0000000D -#define PIN_15 0x0000000E -#define PIN_16 0x0000000F -#define PIN_17 0x00000010 -#define PIN_18 0x00000011 -#define PIN_19 0x00000012 -#define PIN_20 0x00000013 -#define PIN_21 0x00000014 -#define PIN_29 0x0000001C -#define PIN_30 0x0000001D -#define PIN_45 0x0000002C -#define PIN_46 0x0000002D -#define PIN_47 0x0000002E -#define PIN_48 0x0000002F -#define PIN_49 0x00000030 -#define PIN_50 0x00000031 -#define PIN_52 0x00000033 -#define PIN_53 0x00000034 -#define PIN_55 0x00000036 -#define PIN_56 0x00000037 -#define PIN_57 0x00000038 -#define PIN_58 0x00000039 -#define PIN_59 0x0000003A -#define PIN_60 0x0000003B -#define PIN_61 0x0000003C -#define PIN_62 0x0000003D -#define PIN_63 0x0000003E -#define PIN_64 0x0000003F - - -//***************************************************************************** -// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet() -//***************************************************************************** - -#define PIN_MODE_0 0x00000000 -#define PIN_MODE_1 0x00000001 -#define PIN_MODE_2 0x00000002 -#define PIN_MODE_3 0x00000003 -#define PIN_MODE_4 0x00000004 -#define PIN_MODE_5 0x00000005 -#define PIN_MODE_6 0x00000006 -#define PIN_MODE_7 0x00000007 -#define PIN_MODE_8 0x00000008 -#define PIN_MODE_9 0x00000009 -#define PIN_MODE_10 0x0000000A -#define PIN_MODE_11 0x0000000B -#define PIN_MODE_12 0x0000000C -#define PIN_MODE_13 0x0000000D -#define PIN_MODE_14 0x0000000E -#define PIN_MODE_15 0x0000000F -// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation -// PIN_MODE_255 should never be used in any user code. -#define PIN_MODE_255 0x000000FF - -//***************************************************************************** -// Macros that can be used with PinDirModeSet() and returned from -// PinDirModeGet(). -//***************************************************************************** -#define PIN_DIR_MODE_IN 0x00000C00 // Pin is input -#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output -#define PIN_DIR_MODE_HW 0x00000000 // Pin is peripheral function - -//***************************************************************************** -// Macros that can be used with PinConfigSet() -//***************************************************************************** -#define PIN_STRENGTH_2MA 0x00000020 -#define PIN_STRENGTH_4MA 0x00000040 -#define PIN_STRENGTH_6MA 0x00000060 - -#define PIN_TYPE_STD 0x00000000 -#define PIN_TYPE_STD_PU 0x00000100 -#define PIN_TYPE_STD_PD 0x00000200 - -#define PIN_TYPE_OD 0x00000010 -#define PIN_TYPE_OD_PU 0x00000110 -#define PIN_TYPE_OD_PD 0x00000210 -#define PIN_TYPE_ANALOG 0x10000000 - -//***************************************************************************** -// Macros that can be used with PinHysteresisSet() -//***************************************************************************** -#define PIN_HYSTERESIS_OFF 0x00000000 -#define PIN_HYSTERESIS_10 0x00000004 -#define PIN_HYSTERESIS_20 0x0000000C -#define PIN_HYSTERESIS_30 0x00000014 -#define PIN_HYSTERESIS_40 0x0000001C - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode); -extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO); -extern unsigned long PinDirModeGet(unsigned long ulPin); -extern unsigned long PinModeGet(unsigned long ulPin); -extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength, - unsigned long *pulPinType); -extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength, - unsigned long ulPinType); -extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode, - tBoolean bOpenDrain); -extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode); -extern void PinHysteresisSet(unsigned long ulHysteresis); -extern void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel); -extern void PinLock(unsigned long ulOutEnable); -extern void PinUnlock(void); -extern unsigned long PinToPadGet(unsigned long ulPin); -extern unsigned long PinFromPadGet(unsigned long ulPad); - -#ifdef __cplusplus -} -#endif - -#endif //__PIN_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.c deleted file mode 100755 index 6e408e8b80d..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.c +++ /dev/null @@ -1,2752 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -//! \addtogroup PRCM_Power_Reset_Clock_Module_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_apps_rcm.h" -#include "inc/hw_gprcm.h" -#include "inc/hw_hib1p2.h" -#include "inc/hw_hib3p3.h" -#include "inc/hw_ocp_shared.h" -#include "inc/hw_common_reg.h" -#include "prcm.h" -#include "interrupt.h" -#include "cpu.h" -#include "flash.h" -#include "utils.h" -#include "pin.h" - - -//***************************************************************************** -// Macro definition -//***************************************************************************** -#define PRCM_SOFT_RESET 0x00000001 -#define PRCM_ENABLE_STATUS 0x00000002 -#define SYS_CLK 80000000 -#define XTAL_CLK 40000000 - - -//***************************************************************************** -// CC3200 does not have a true RTC capability. However, API(s) in this file -// provide an effective mechanism to support RTC feature in the device. -// -// The implementation to support RTC has been kept very simple. A set of -// HIB Memory Registers in conjunction with Slow Clock Counter are used -// to render RTC information to users. Core principle of design involves -// two steps (a) establish an association between user provided wall-clock -// and slow clock counter. (b) store reference value of this associattion -// in HIB Registers. This reference value and SCC value are then combined -// to create real-world calendar time. -// -// Across HIB cycles, value stored in HIB Registers is retained and slow -// clock counter continues to tick, thereby, this arragement is relevant -// and valid as long as device has a (tickle) battery power. -// -// Further, provision also has been made to set an alarm. When it RTC value -// matches that of set for alarm, an interrupt is generated. -// -// HIB MEM REG0 and REG1 are reserved for TI. -// -// If RTC feature is not used, then HIB REG2 & REG3 are available to user. -// -// Lower half of REG0 is used for TI HW ECO. -//***************************************************************************** -#define RTC_U64MSEC_MK(u32Secs, u16Msec) (((unsigned long long)u32Secs << 10)|\ - (u16Msec & 0x3FF)) - -#define RTC_SECS_IN_U64MSEC(u64Msec) ((unsigned long)(u64Msec >> 10)) -#define RTC_MSEC_IN_U64MSEC(u64Msec) ((unsigned short)(u64Msec & 0x3FF)) - -#define RTC_SECS_U32_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG3) -#define RTC_MSEC_U16_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2+2) - -#define RTC_U32SECS_REG (HWREG(RTC_SECS_U32_REG_ADDR)) -#define RTC_U16MSEC_REG (*(unsigned short*)RTC_MSEC_U16_REG_ADDR) - -//***************************************************************************** -// Register Access and Updates -// -// Tick of SCC has a resolution of 32768Hz, meaning 1 sec is equal to 32768 -// clock ticks. Ideal way of getting time in millisecond will involve floating -// point arithmetic (division by 32.768). To avoid this, we simply divide it by -// 32, which will give a range from 0 -1023(instead of 0-999). To use this -// output correctly we have to take care of this inaccuracy externally. -// following wrapper can be used to convert the value from cycles to -// millisecond: -// -// CYCLES_U16MS(cycles) ((cycles *1000)/ 1024), -// -// Similarly, before setting the value, it must be first converted (from ms to -// cycles). -// -// U16MS_CYCLES(msec) ((msec *1024)/1000) -// -// Note: There is a precision loss of 1 ms with the above scheme. -// -//***************************************************************************** -#define SCC_U64MSEC_GET() (PRCMSlowClkCtrGet() >> 5) -#define SCC_U64MSEC_MATCH_SET(u64Msec) (PRCMSlowClkCtrMatchSet(u64Msec << 5)) -#define SCC_U64MSEC_MATCH_GET() (PRCMSlowClkCtrMatchGet() >> 5) - -//***************************************************************************** -// -// Bit: 31 is used to indicate use of RTC. If set as '1', RTC feature is used. -// Bits: 30 to 26 are reserved, available to software for use -// Bits: 25 to 16 are used to save millisecond part of RTC reference. -// Bits: 15 to 0 are being used for HW Changes / ECO -// -//***************************************************************************** - -//***************************************************************************** -// Set RTC USE Bit -//***************************************************************************** -static void RTCUseSet(void) -{ - unsigned short usRegValue; - - usRegValue = RTC_U16MSEC_REG | (1 << 15); - - UtilsDelay((80*200)/3); - - RTC_U16MSEC_REG = usRegValue; -} - -//***************************************************************************** -// Checks if RTC-USE bit is set -//***************************************************************************** -static tBoolean IsRTCUsed(void) -{ - unsigned short usRegValue; - - usRegValue = RTC_U16MSEC_REG; - - UtilsDelay((80*200)/3); - - return ((usRegValue & (1 << 15))? true : false); -} - -//***************************************************************************** -// Read 16-bit mSecs -//***************************************************************************** -static unsigned short RTCU16MSecRegRead(void) -{ - unsigned short usRegValue; - - usRegValue = RTC_U16MSEC_REG; - - UtilsDelay((80*200)/3); - - return (usRegValue & 0x3FF); -} - -//***************************************************************************** -// Write 16-bit mSecs -//***************************************************************************** -static void RTCU16MSecRegWrite(unsigned short u16Msec) -{ - unsigned short usRegValue; - - usRegValue = RTC_U16MSEC_REG; - - UtilsDelay((80*200)/3); - - RTC_U16MSEC_REG = ((usRegValue & ~0x3FF) |u16Msec); -} - -//***************************************************************************** -// Read 32-bit Secs -//***************************************************************************** -static unsigned long RTCU32SecRegRead(void) -{ - return (PRCMHIBRegRead(RTC_SECS_U32_REG_ADDR)); -} - -//***************************************************************************** -// Write 32-bit Secs -//***************************************************************************** -static void RTCU32SecRegWrite(unsigned long u32Msec) -{ - PRCMHIBRegWrite(RTC_SECS_U32_REG_ADDR, u32Msec); -} - -//***************************************************************************** -// Macros -//***************************************************************************** -#define IS_RTC_USED() IsRTCUsed() -#define RTC_USE_SET() RTCUseSet() - -#define RTC_U16MSEC_REG_RD() RTCU16MSecRegRead() -#define RTC_U16MSEC_REG_WR(u16Msec) RTCU16MSecRegWrite(u16Msec) - -#define RTC_U32SECS_REG_RD() RTCU32SecRegRead() -#define RTC_U32SECS_REG_WR(u32Secs) RTCU32SecRegWrite(u32Secs) - -#define SELECT_SCC_U42BITS(u64Msec) (u64Msec & 0x3ffffffffff) - -//***************************************************************************** -// Global Peripheral clock and rest Registers -//***************************************************************************** -static const PRCM_PeriphRegs_t PRCM_PeriphRegsList[] = -{ - - {APPS_RCM_O_CAMERA_CLK_GATING, APPS_RCM_O_CAMERA_SOFT_RESET }, - {APPS_RCM_O_MCASP_CLK_GATING, APPS_RCM_O_MCASP_SOFT_RESET }, - {APPS_RCM_O_MMCHS_CLK_GATING, APPS_RCM_O_MMCHS_SOFT_RESET }, - {APPS_RCM_O_MCSPI_A1_CLK_GATING, APPS_RCM_O_MCSPI_A1_SOFT_RESET }, - {APPS_RCM_O_MCSPI_A2_CLK_GATING, APPS_RCM_O_MCSPI_A2_SOFT_RESET }, - {APPS_RCM_O_UDMA_A_CLK_GATING, APPS_RCM_O_UDMA_A_SOFT_RESET }, - {APPS_RCM_O_GPIO_A_CLK_GATING, APPS_RCM_O_GPIO_A_SOFT_RESET }, - {APPS_RCM_O_GPIO_B_CLK_GATING, APPS_RCM_O_GPIO_B_SOFT_RESET }, - {APPS_RCM_O_GPIO_C_CLK_GATING, APPS_RCM_O_GPIO_C_SOFT_RESET }, - {APPS_RCM_O_GPIO_D_CLK_GATING, APPS_RCM_O_GPIO_D_SOFT_RESET }, - {APPS_RCM_O_GPIO_E_CLK_GATING, APPS_RCM_O_GPIO_E_SOFT_RESET }, - {APPS_RCM_O_WDOG_A_CLK_GATING, APPS_RCM_O_WDOG_A_SOFT_RESET }, - {APPS_RCM_O_UART_A0_CLK_GATING, APPS_RCM_O_UART_A0_SOFT_RESET }, - {APPS_RCM_O_UART_A1_CLK_GATING, APPS_RCM_O_UART_A1_SOFT_RESET }, - {APPS_RCM_O_GPT_A0_CLK_GATING , APPS_RCM_O_GPT_A0_SOFT_RESET }, - {APPS_RCM_O_GPT_A1_CLK_GATING, APPS_RCM_O_GPT_A1_SOFT_RESET }, - {APPS_RCM_O_GPT_A2_CLK_GATING, APPS_RCM_O_GPT_A2_SOFT_RESET }, - {APPS_RCM_O_GPT_A3_CLK_GATING, APPS_RCM_O_GPT_A3_SOFT_RESET }, - {APPS_RCM_O_CRYPTO_CLK_GATING, APPS_RCM_O_CRYPTO_SOFT_RESET }, - {APPS_RCM_O_MCSPI_S0_CLK_GATING, APPS_RCM_O_MCSPI_S0_SOFT_RESET }, - {APPS_RCM_O_I2C_CLK_GATING, APPS_RCM_O_I2C_SOFT_RESET } - -}; - -//***************************************************************************** -// -//! Performs a software reset of a MCU and associated peripherals -//! -//! \param bIncludeSubsystem is \b true to reset associated peripherals. -//! -//! This function performs a software reset of a MCU and associated peripherals. -//! To reset the associated peripheral, the parameter \e bIncludeSubsystem -//! should be set to \b true. -//! -//! \return None. -// -//***************************************************************************** -void PRCMMCUReset(tBoolean bIncludeSubsystem) -{ - if(bIncludeSubsystem) - { - // - // Reset Apps processor and associated peripheral - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2; - } - else - { - // - // Reset Apps processor only - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1; - } - - // - // Wait for system to enter hibernate - // - __asm(" wfi\n"); - - // - // Infinite loop - // - while(1) - { - - } -} - -//***************************************************************************** -// -//! Gets the reason for a reset. -//! -//! This function returns the reason(s) for a reset. The reset reason are:- -//! -\b PRCM_POWER_ON - Device is powering up. -//! -\b PRCM_LPDS_EXIT - Device is exiting from LPDS. -//! -\b PRCM_CORE_RESET - Device is exiting soft core only reset -//! -\b PRCM_MCU_RESET - Device is exiting soft subsystem reset. -//! -\b PRCM_WDT_RESET - Device was reset by watchdog. -//! -\b PRCM_SOC_RESET - Device is exting SOC reset. -//! -\b PRCM_HIB_EXIT - Device is exiting hibernate. -//! -//! \return Returns one of the cause defined above. -// -//***************************************************************************** -unsigned long PRCMSysResetCauseGet() -{ - unsigned long ulWakeupStatus; - - // - // Read the Reset status - // - ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF); - - // - // For hibernate do additional check. - // - if(ulWakeupStatus == PRCM_POWER_ON) - { - if(PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS) & 0x1) - { - ulWakeupStatus = PRCM_HIB_EXIT; - - if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000280)) == 0x00000280 ) - { - ulWakeupStatus = PRCM_WDT_RESET; - } - } - } - else if((ulWakeupStatus == PRCM_LPDS_EXIT) && - !(HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG1) & (1 <<2)) ) - { - if(HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x1<<8)) - { - ulWakeupStatus = PRCM_POWER_ON; - } - } - - // - // Return status. - // - return ulWakeupStatus; -} - -//***************************************************************************** -// -//! Enable clock(s) to peripheral. -//! -//! \param ulPeripheral is one of the valid peripherals -//! \param ulClkFlags are bitmask of clock(s) to be enabled. -//! -//! This function enables the clock for the specified peripheral. Peripherals -//! are by default clock gated (disabled) and generates a bus fault if -//! accessed. -//! -//! The parameter \e ulClkFlags can be logical OR of the following: -//! -\b PRCM_RUN_MODE_CLK - Ungates clock to the peripheral -//! -\b PRCM_SLP_MODE_CLK - Keeps the clocks ungated in sleep. -//! -//! \return None. -// -//***************************************************************************** -void -PRCMPeripheralClkEnable(unsigned long ulPeripheral, unsigned long ulClkFlags) -{ - // - // Enable the specified peripheral clocks, Nothing to be done for PRCM_ADC - // as it is a dummy define for pinmux utility code generation - // - if(ulPeripheral != PRCM_ADC) - { - HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags; - } - - // - // Checking ROM Version less than 2.x.x. - // Only for driverlib backward compatibility - // - if( (HWREG(0x00000400) & 0xFFFF) < 2 ) - { - // - // Set the default clock for camera - // - if(ulPeripheral == PRCM_CAMERA) - { - HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404; - } - } -} - -//***************************************************************************** -// -//! Disables clock(s) to peripheral. -//! -//! \param ulPeripheral is one of the valid peripherals -//! \param ulClkFlags are bitmask of clock(s) to be enabled. -//! -//! This function disable the clock for the specified peripheral. Peripherals -//! are by default clock gated (disabled) and generated a bus fault if -//! accessed. -//! -//! The parameter \e ulClkFlags can be logical OR bit fields as defined in -//! PRCMEnablePeripheral(). -//! -//! \return None. -// -//***************************************************************************** -void -PRCMPeripheralClkDisable(unsigned long ulPeripheral, unsigned long ulClkFlags) -{ - // - // Disable the specified peripheral clocks - // - HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) &= ~ulClkFlags; -} - -//***************************************************************************** -// -//! Gets the input clock for the specified peripheral. -//! -//! \param ulPeripheral is one of the valid peripherals. -//! -//! This function gets the input clock for the specified peripheral. -//! -//! The parameter \e ulPeripheral has the same definition as that in -//! PRCMPeripheralClkEnable(); -//! -//! \return Returns input clock frequency for specified peripheral. -// -//***************************************************************************** -unsigned long -PRCMPeripheralClockGet(unsigned long ulPeripheral) -{ - unsigned long ulClockFreq; - unsigned long ulHiPulseDiv; - unsigned long ulLoPulseDiv; - - // - // Get the clock based on specified peripheral. - // - if(((ulPeripheral == PRCM_SSPI) | (ulPeripheral == PRCM_LSPI) - | (ulPeripheral == PRCM_GSPI))) - { - return XTAL_CLK; - } - else if(ulPeripheral == PRCM_CAMERA) - { - ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) >> 8) & 0x07); - ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN)& 0xFF); - } - else if(ulPeripheral == PRCM_SDHOST) - { - ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) >> 8) & 0x07); - ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN)& 0xFF); - } - else - { - return SYS_CLK; - } - - // - // Compute the clock freq. from the divider value - // - ulClockFreq = (240000000/((ulHiPulseDiv + 1) + (ulLoPulseDiv + 1))); - - // - // Return the clock rate. - // - return ulClockFreq; -} - -//***************************************************************************** -// -//! Performs a software reset of a peripheral. -//! -//! \param ulPeripheral is one of the valid peripheral. -//! -//! This function does soft reset of the specified peripheral -//! -//! \return None. -// -//***************************************************************************** -void -PRCMPeripheralReset(unsigned long ulPeripheral) -{ - volatile unsigned long ulDelay; - - if( ulPeripheral != PRCM_DTHE) - { - // - // Assert the reset - // - HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg) - |= PRCM_SOFT_RESET; - // - // Delay a little bit. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) - { - } - - // - // Deassert the reset - // - HWREG(ARCM_BASE+PRCM_PeriphRegsList[ulPeripheral].ulRstReg) - &= ~PRCM_SOFT_RESET; - } -} - -//***************************************************************************** -// -//! Determines if a peripheral is ready. -//! -//! \param ulPeripheral is one of the valid modules -//! -//! This function determines if a particular peripheral is ready to be -//! accessed. The peripheral may be in a non-ready state if it is not enabled, -//! is being held in reset, or is in the process of becoming ready after being -//! enabled or taken out of reset. -//! -//! \return Returns \b true if the peripheral is ready, \b false otherwise. -// -//***************************************************************************** -tBoolean -PRCMPeripheralStatusGet(unsigned long ulPeripheral) -{ - unsigned long ReadyBit; - - // - // Read the ready bit status - // - ReadyBit = HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg); - ReadyBit = ReadyBit & PRCM_ENABLE_STATUS; - - if (ReadyBit) - { - // - // Module is ready - // - return(true); - } - else - { - // - // Module is not ready - // - return(false); - } -} - -//***************************************************************************** -// -//! Configure I2S fracactional divider -//! -//! \param ulI2CClkFreq is the required input clock for McAPS module -//! -//! This function configures I2S fractional divider. By default this -//! divider is set to output 24 Mhz clock to I2S module. -//! -//! The minimum frequency that can be obtained by configuring this divider is -//! -//! (240000KHz/1023.99) = 234.377 KHz -//! -//! \return None. -// -//***************************************************************************** -void -PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq) -{ - unsigned long long ullDiv; - unsigned short usInteger; - unsigned short usFrac; - - ullDiv = (((unsigned long long)240000000 * 65536)/ulI2CClkFreq); - - usInteger = (ullDiv/65536); - usFrac = (ullDiv%65536); - - HWREG(ARCM_BASE + APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0) = - ((usInteger & 0x3FF) << 16 | usFrac); -} - -//***************************************************************************** -// -//! Sets the LPDS exit PC and SP restore vlaues. -//! -//! \param ulStackPtr is the SP restore value. -//! \param ulProgCntr is the PC restore value -//! -//! This function sets the LPDS exit PC and SP restore vlaues. Setting -//! \e ulProgCntr to a non-zero value, forces bootloader to jump to that -//! address with Stack Pointer initialized to \e ulStackPtr on LPDS exit, -//! otherwise the application's vector table entries are used. -//! -//! \return None. -// -//***************************************************************************** -void -PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr) -{ - // - // ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Set The SP Value - // - HWREG(0x4402E160) = ulStackPtr; - - // - // Set The PC Value - // - HWREG(0x4402E198) = ulProgCntr; - - } - else - { - // - // Set The SP Value - // - HWREG(0x4402E18C) = ulStackPtr; - - // - // Set The PC Value - // - HWREG(0x4402E190) = ulProgCntr; - } -} - -//***************************************************************************** -// -//! Puts the system into Low Power Deel Sleep (LPDS) power mode. -//! -//! This function puts the system into Low Power Deel Sleep (LPDS) power mode. -//! A call to this function never returns and the execution starts from Reset. -//! \sa PRCMLPDSRestoreInfoSet(). -//! -//! \return None. -//! -//! \note External debugger will always disconnect whenever the system -//! enters LPDS and debug interface is shutdown until next POR reset. In order -//! to avoid this and allow for connecting back the debugger after waking up -//! from LPDS \sa PRCMLPDSEnterKeepDebugIf(). -//! -// -//***************************************************************************** -void -PRCMLPDSEnter() -{ - unsigned long ulChipId; - - // - // Read the Chip ID - // - ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); - - // - // Check if flash exists - // - if( (0x11 == ulChipId) || (0x19 == ulChipId)) - { - - // - // Disable the flash - // - FlashDisable(); - } - -#ifndef KEEP_TESTPD_ALIVE - - // - // Disable TestPD - // - HWREG(0x4402E168) |= (1<<9); -#endif - - // - // Set bandgap duty cycle to 1 - // - HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; - - // - // Request LPDS - // - HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) - = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ; - - // - // Wait for system to enter LPDS - // - __asm(" wfi\n"); - - // - // Infinite loop - // - while(1) - { - - } - -} - - -//***************************************************************************** -// -//! Puts the system into Low Power Deel Sleep (LPDS) power mode keeping -//! debug interface alive. -//! -//! This function puts the system into Low Power Deel Sleep (LPDS) power mode -//! keeping debug interface alive. A call to this function never returns and the -//! execution starts from Reset \sa PRCMLPDSRestoreInfoSet(). -//! -//! \return None. -//! -//! \note External debugger will always disconnect whenever the system -//! enters LPDS, using this API will allow connecting back the debugger after -//! waking up from LPDS. This API is recommended for development purposes -//! only as it adds to the current consumption of the system. -//! -// -//***************************************************************************** -void -PRCMLPDSEnterKeepDebugIf() -{ - unsigned long ulChipId; - - // - // Read the Chip ID - // - ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); - - // - // Check if flash exists - // - if( (0x11 == ulChipId) || (0x19 == ulChipId)) - { - - // - // Disable the flash - // - FlashDisable(); - } - - // - // Set bandgap duty cycle to 1 - // - HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; - - // - // Request LPDS - // - HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) - = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ; - - // - // Wait for system to enter LPDS - // - __asm(" wfi\n"); - - // - // Infinite loop - // - while(1) - { - - } - -} - -//***************************************************************************** -// -//! Enable the individual LPDS wakeup source(s). -//! -//! \param ulLpdsWakeupSrc is logical OR of wakeup sources. -//! -//! This function enable the individual LPDS wakeup source(s) and following -//! three wakeup sources (\e ulLpdsWakeupSrc ) are supported by the device. -//! -\b PRCM_LPDS_HOST_IRQ -//! -\b PRCM_LPDS_GPIO -//! -\b PRCM_LPDS_TIMER -//! -//! \return None. -// -//***************************************************************************** -void -PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc) -{ - unsigned long ulRegVal; - - // - // Read the current wakup sources - // - ulRegVal = HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG); - - // - // Enable individual wakeup source - // - ulRegVal = ((ulRegVal | ulLpdsWakeupSrc) & 0x91); - - // - // Set the configuration in the register - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) = ulRegVal; -} - -//***************************************************************************** -// -//! Disable the individual LPDS wakeup source(s). -//! -//! \param ulLpdsWakeupSrc is logical OR of wakeup sources. -//! -//! This function enable the individual LPDS wakeup source(s) and following -//! three wake up sources (\e ulLpdsWakeupSrc ) are supported by the device. -//! -\b PRCM_LPDS_HOST_IRQ -//! -\b PRCM_LPDS_GPIO -//! -\b PRCM_LPDS_TIMER -//! -//! \return None. -// -//***************************************************************************** -void -PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc) -{ - HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) &= ~ulLpdsWakeupSrc; -} - - -//***************************************************************************** -// -//! Get LPDS wakeup cause -//! -//! This function gets LPDS wakeup caouse -//! -//! \return Returns values enumerated as described in -//! PRCMLPDSWakeupSourceEnable(). -// -//***************************************************************************** -unsigned long -PRCMLPDSWakeupCauseGet() -{ - return (HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_SRC)); -} - -//***************************************************************************** -// -//! Sets LPDS wakeup Timer -//! -//! \param ulTicks is number of 32.768 KHz clocks -//! -//! This function sets internal LPDS wakeup timer running at 32.768 KHz. The -//! timer is only configured if the parameter \e ulTicks is in valid range i.e. -//! from 21 to 2^32. -//! -//! \return Returns \b true on success, \b false otherwise. -// -//***************************************************************************** -void -PRCMLPDSIntervalSet(unsigned long ulTicks) -{ - // - // Check sleep is atleast for 21 cycles - // If not set the sleep time to 21 cycles - // - if( ulTicks < 21) - { - ulTicks = 21; - } - - HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG) = ulTicks; - HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG) = ulTicks-20; -} - -//***************************************************************************** -// -//! Selects the GPIO for LPDS wakeup -//! -//! \param ulGPIOPin is one of the valid GPIO fro LPDS wakeup. -//! \param ulType is the wakeup trigger type. -//! -//! This function setects the wakeup GPIO for LPDS wakeup and can be -//! used to select one out of 7 pre-defined GPIO(s). -//! -//! The parameter \e ulLpdsGPIOSel should be one of the following:- -//! -\b PRCM_LPDS_GPIO2 -//! -\b PRCM_LPDS_GPIO4 -//! -\b PRCM_LPDS_GPIO13 -//! -\b PRCM_LPDS_GPIO17 -//! -\b PRCM_LPDS_GPIO11 -//! -\b PRCM_LPDS_GPIO24 -//! -\b PRCM_LPDS_GPIO26 -//! -//! The parameter \e ulType sets the trigger type and can be one of the -//! following: -//! - \b PRCM_LPDS_LOW_LEVEL -//! - \b PRCM_LPDS_HIGH_LEVEL -//! - \b PRCM_LPDS_FALL_EDGE -//! - \b PRCM_LPDS_RISE_EDGE -//! -//! \return None. -// -//***************************************************************************** -void -PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType) -{ - // - // Set the wakeup GPIO - // - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL, ulGPIOPin); - - // - // Set the trigger type. - // - HWREG(GPRCM_BASE + GPRCM_O_APPS_GPIO_WAKE_CONF) = (ulType & 0x3); -} - -//***************************************************************************** -// -//! Puts the system into Sleep. -//! -//! This function puts the system into sleep power mode. System exits the power -//! state on any one of the available interrupt. On exit from sleep mode the -//! function returns to the calling function with all the processor core -//! registers retained. -//! -//! \return None. -// -//***************************************************************************** -void -PRCMSleepEnter() -{ - // - // Request Sleep - // - CPUwfi(); -} - -//***************************************************************************** -// -//! Enable SRAM column retention during LPDS Power mode(s) -//! -//! \param ulSramColSel is bit mask of valid SRAM columns. -//! \param ulModeFlags is the bit mask of power modes. -//! -//! This functions enables the SRAM retention. The device supports configurable -//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is of -//! 64 KB size. -//! -//! The parameter \e ulSramColSel should be logical OR of the following:- -//! -\b PRCM_SRAM_COL_1 -//! -\b PRCM_SRAM_COL_2 -//! -\b PRCM_SRAM_COL_3 -//! -\b PRCM_SRAM_COL_4 -//! -//! The parameter \e ulModeFlags selects the power modes and sholud be logical -//! OR of one or more of the following -//! -\b PRCM_SRAM_LPDS_RET -//! -//! \return None. -// -//**************************************************************************** -void -PRCMSRAMRetentionEnable(unsigned long ulSramColSel, unsigned long ulModeFlags) -{ - if(ulModeFlags & PRCM_SRAM_LPDS_RET) - { - // - // Configure LPDS SRAM retention register - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) = (ulSramColSel & 0xF); - } -} - -//***************************************************************************** -// -//! Disable SRAM column retention during LPDS Power mode(s). -//! -//! \param ulSramColSel is bit mask of valid SRAM columns. -//! \param ulFlags is the bit mask of power modes. -//! -//! This functions disable the SRAM retention. The device supports configurable -//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is -//! of 64 KB size. -//! -//! The parameter \e ulSramColSel should be logical OR of the following:- -//! -\b PRCM_SRAM_COL_1 -//! -\b PRCM_SRAM_COL_2 -//! -\b PRCM_SRAM_COL_3 -//! -\b PRCM_SRAM_COL_4 -//! -//! The parameter \e ulFlags selects the power modes and sholud be logical OR -//! of one or more of the following -//! -\b PRCM_SRAM_LPDS_RET -//! -//! \return None. -// -//**************************************************************************** -void -PRCMSRAMRetentionDisable(unsigned long ulSramColSel, unsigned long ulFlags) -{ - if(ulFlags & PRCM_SRAM_LPDS_RET) - { - // - // Configure LPDS SRAM retention register - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) &= ~(ulSramColSel & 0xF); - } -} - - -//***************************************************************************** -// -//! Enables individual HIB wakeup source(s). -//! -//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources. -//! -//! This function enables individual HIB wakeup source(s). The paramter -//! \e ulHIBWakupSrc is the bit mask of HIB wakeup sources and should be -//! logical OR of one or more of the follwoing :- -//! -\b PRCM_HIB_SLOW_CLK_CTR -//! -\b PRCM_HIB_GPIO2 -//! -\b PRCM_HIB_GPIO4 -//! -\b PRCM_HIB_GPIO13 -//! -\b PRCM_HIB_GPIO17 -//! -\b PRCM_HIB_GPIO11 -//! -\b PRCM_HIB_GPIO24 -//! -\b PRCM_HIB_GPIO26 -//! -//! \return None. -// -//***************************************************************************** -void -PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc) -{ - unsigned long ulRegValue; - - // - // Read the RTC register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); - - // - // Enable the RTC as wakeup source if specified - // - ulRegValue |= (ulHIBWakupSrc & 0x1); - - // - // Enable HIB wakeup sources - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); - - // - // REad the GPIO wakeup configuration register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN); - - // - // Enable the specified GPIOs a wakeup sources - // - ulRegValue |= ((ulHIBWakupSrc>>16)&0xFF); - - // - // Write the new register configuration - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue); -} - -//***************************************************************************** -// -//! Disable individual HIB wakeup source(s). -//! -//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources. -//! -//! This function disable individual HIB wakeup source(s). The paramter -//! \e ulHIBWakupSrc is same as bit fileds defined in -//! PRCMEnableHibernateWakeupSource() -//! -//! \return None. -// -//***************************************************************************** -void -PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc) -{ - unsigned long ulRegValue; - - // - // Read the RTC register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); - - // - // Disable the RTC as wakeup source if specified - // - ulRegValue &= ~(ulHIBWakupSrc & 0x1); - - // - // Disable HIB wakeup sources - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); - - // - // Read the GPIO wakeup configuration register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN); - - // - // Enable the specified GPIOs a wakeup sources - // - ulRegValue &= ~((ulHIBWakupSrc>>16)&0xFF); - - // - // Write the new register configuration - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue); -} - - -//***************************************************************************** -// -//! Get hibernate wakeup cause -//! -//! This function gets the hibernate wakeup cause. -//! -//! \return Returns \b PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK or -//! \b PRCM_HIB_WAKEUP_CAUSE_GPIO -// -//***************************************************************************** -unsigned long -PRCMHibernateWakeupCauseGet() -{ - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - return ((PRCMHIBRegRead((OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8))>>2)&0x7); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Sets Hibernate wakeup Timer -//! -//! \param ullTicks is number of 32.768 KHz clocks -//! -//! This function sets internal hibernate wakeup timer running at 32.768 KHz. -//! -//! \return Returns \b true on success, \b false otherwise. -// -//***************************************************************************** -void -PRCMHibernateIntervalSet(unsigned long long ullTicks) -{ - unsigned long long ullRTCVal; - - // - // Latch the RTC vlaue - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1); - - // - // Read latched values as 2 32-bit vlaues - // - ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW); - ullRTCVal = ullRTCVal << 32; - ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW); - - // - // Add the interval - // - ullRTCVal = ullRTCVal + ullTicks; - - // - // Set RTC match value - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF, - (unsigned long)(ullRTCVal)); - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF, - (unsigned long)(ullRTCVal>>32)); -} - - -//***************************************************************************** -// -//! Selects the GPIO(s) for hibernate wakeup -//! -//! \param ulGPIOBitMap is the bit-map of valid hibernate wakeup GPIO. -//! \param ulType is the wakeup trigger type. -//! -//! This function setects the wakeup GPIO for hibernate and can be -//! used to select any combination of 7 pre-defined GPIO(s). -//! -//! This function enables individual HIB wakeup source(s). The paramter -//! \e ulGPIOBitMap should be one of the follwoing :- -//! -\b PRCM_HIB_GPIO2 -//! -\b PRCM_HIB_GPIO4 -//! -\b PRCM_HIB_GPIO13 -//! -\b PRCM_HIB_GPIO17 -//! -\b PRCM_HIB_GPIO11 -//! -\b PRCM_HIB_GPIO24 -//! -\b PRCM_HIB_GPIO26 -//! -//! The parameter \e ulType sets the trigger type and can be one of the -//! following: -//! - \b PRCM_HIB_LOW_LEVEL -//! - \b PRCM_HIB_HIGH_LEVEL -//! - \b PRCM_HIB_FALL_EDGE -//! - \b PRCM_HIB_RISE_EDGE -//! -//! \return None. -// -//***************************************************************************** -void -PRCMHibernateWakeUpGPIOSelect(unsigned long ulGPIOBitMap, unsigned long ulType) -{ - unsigned char ucLoop; - unsigned long ulRegValue; - - // - // Shift the bits to extract the GPIO selection - // - ulGPIOBitMap >>= 16; - - // - // Set the configuration for each GPIO - // - for(ucLoop=0; ucLoop < 7; ucLoop++) - { - if(ulGPIOBitMap & (1<>32)); -} - -//***************************************************************************** -// -//! Gets slow clock counter match value. -//! -//! This function gets the match value for slow clock counter. This is use -//! to interrupt the processor when RTC counts to the specified value. -//! -//! \return None. -// -//***************************************************************************** -unsigned long long PRCMSlowClkCtrMatchGet() -{ - unsigned long long ullValue; - - // - // Get RTC match value - // - ullValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF); - ullValue = ullValue<<32; - ullValue |= PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF); - - // - // Return the value - // - return ullValue; -} - - -//***************************************************************************** -// -//! Write to On-Chip Retention (OCR) register. -//! -//! This function writes to On-Chip retention register. The device supports two -//! 4-byte OCR register which are retained across all power mode. -//! -//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1. -//! -//! These registers are shared by the RTC implementation (if Driverlib RTC -//! APIs are used), ROM, and user application. -//! -//! When RTC APIs in use: -//! -//! |-----------------------------------------------| -//! | INDEX 1 | -//! |-----------------------------------------------| -//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |-----------------------------------------------| -//! | Reserved by RTC APIs - YY | -//! |-----------------------------------------------| -//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |-----------------------------------------------| -//! | Reserved by RTC APIs - YY | -//! |-----------------------------------------------| -//! -//! -//! |-----------------------------------------------| -//! | INDEX 0 | -//! |-----------------------------------------------| -//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |-----------------------------------------------| -//! | Reserved by RTC APIs - YY | -//! |-----------------------------------------------| -//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |-----------------------------------------------| -//! |YY| For User Application |XX| -//! |-----------------------------------------------| -//! -//! YY => Reserved by RTC APIs. If Driverlib RTC APIs are used -//! XX => Reserved by ROM -//! -//! -//! When RTC APIs are not in use: -//! -//! |-----------------------------------------------| -//! | INDEX 1 | -//! |-----------------------------------------------| -//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |-----------------------------------------------| -//! | For User Application | -//! |-----------------------------------------------| -//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |-----------------------------------------------| -//! | For User Application | -//! |-----------------------------------------------| -//! -//! -//! |-----------------------------------------------| -//! | INDEX 0 | -//! |-----------------------------------------------| -//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |-----------------------------------------------| -//! | For User Application | -//! |-----------------------------------------------| -//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |-----------------------------------------------| -//! | For User Application |XX| -//! |-----------------------------------------------| -//! -//! XX => Reserved by ROM -//! -//! -//! -//! \return None. -// -//***************************************************************************** -void PRCMOCRRegisterWrite(unsigned char ucIndex, unsigned long ulRegValue) -{ - unsigned long ulVal; - - // - // Compuitr the offset - // - ucIndex = ucIndex << 2; - - // - // If bit 0 is reserved - // - if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && - (ucIndex == 0) ) - { - ulVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex); - ulRegValue = ((ulRegValue << 0x1) | (ulVal & (0x1))); - } - - // - // Write thr value - // - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex,ulRegValue); - -} - -//***************************************************************************** -// -//! Read from On-Chip Retention (OCR) register. -//! -//! This function reads from On-Chip retention register. The device supports two -//! 4-byte OCR register which are retained across all power mode. -//! -//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1. -//! -//! \sa PRCMOCRRegisterWrite() for the register usage details. -//! -//! \return None. -// -//***************************************************************************** -unsigned long PRCMOCRRegisterRead(unsigned char ucIndex) -{ - unsigned long ulRet; - - // - // Read the OCR register - // - ulRet = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2 + (ucIndex << 2)); - - // - // If bit 0 is reserved - // - if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && - (ucIndex == 0) ) - { - ulRet = ulRet >> 0x1; - } - - // - // Return the read value. - // - return ulRet; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the PRCM. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; -//! -//! \return None. -// -//***************************************************************************** -void PRCMIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler. - // - IntRegister(INT_PRCM, pfnHandler); - - // - // Enable the PRCM interrupt. - // - IntEnable(INT_PRCM); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the PRCM. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a PRCM interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \return None. -// -//***************************************************************************** -void PRCMIntUnregister() -{ - // - // Enable the UART interrupt. - // - IntDisable(INT_PRCM); - - // - // Register the interrupt handler. - // - IntUnregister(INT_PRCM); -} - -//***************************************************************************** -// -//! Enables individual PRCM interrupt sources. -//! -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated ARCM interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -\b PRCM_INT_SLOW_CLK_CTR -//! -// -//***************************************************************************** -void PRCMIntEnable(unsigned long ulIntFlags) -{ - unsigned long ulRegValue; - - if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR ) - { - // - // Enable PRCM interrupt - // - HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) |= 0x4; - - // - // Enable RTC interrupt - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE); - ulRegValue |= 0x1; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue); - } -} - -//***************************************************************************** -// -//! Disables individual PRCM interrupt sources. -//! -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated ARCM interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to PRCMEnableInterrupt(). -//! -//! \return None. -// -//***************************************************************************** -void PRCMIntDisable(unsigned long ulIntFlags) -{ - unsigned long ulRegValue; - - if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR ) - { - // - // Disable PRCM interrupt - // - HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) &= ~0x4; - - // - // Disable RTC interrupt - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE); - ulRegValue &= ~0x1; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue); - } -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! This function returns the PRCM interrupt status of interrupts that are -//! allowed to reflect to the processor. The interrupts are cleared on read. -//! -//! \return Returns the current interrupt status. -// -//***************************************************************************** -unsigned long PRCMIntStatus() -{ - return HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS); -} - -//***************************************************************************** -// -//! Mark the function of RTC as being used -//! -//! This function marks in HW that feature to maintain calendar time in device -//! is being used. -//! -//! Specifically, this feature reserves user's HIB Register-1 accessed through -//! PRCMOCRRegisterWrite(1) for internal work / purpose, therefore, the stated -//! register is not available to user. Also, users must not excercise the Slow -//! Clock Counter API(s), if RTC has been set for use. -//! -//! The RTC feature, if set or marked, can be only reset either through reboot -//! or power cycle. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCInUseSet() -{ - RTC_USE_SET(); - return; -} - -//***************************************************************************** -// -//! Ascertain whether function of RTC is being used -//! -//! This function indicates whether function of RTC is being used on the device -//! or not. -//! -//! This routine should be utilized by the application software, when returning -//! from low-power, to confirm that RTC has been put to use and may not need to -//! set the value of the RTC. -//! -//! The RTC feature, if set or marked, can be only reset either through reboot -//! or power cycle. -//! -//! \return None. -// -//***************************************************************************** -tBoolean PRCMRTCInUseGet() -{ - return IS_RTC_USED()? true : false; -} - -//***************************************************************************** -// -//! Set the calendar time in the device. -//! -//! \param ulSecs refers to the seconds part of the calendar time -//! \param usMsec refers to the fractional (ms) part of the second -//! -//! This function sets the specified calendar time in the device. The calendar -//! time is outlined in terms of seconds and milliseconds. However, the device -//! makes no assumption about the origin or reference of the calendar time. -//! -//! The device uses the indicated calendar value to update and maintain the -//! wall-clock time across active and low power states. -//! -//! The function PRCMRTCInUseSet() must be invoked prior to use of this feature. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec) -{ - unsigned long long ullMsec = 0; - - if(IS_RTC_USED()) { - ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec) - SCC_U64MSEC_GET(); - - RTC_U32SECS_REG_WR(RTC_SECS_IN_U64MSEC(ullMsec)); - RTC_U16MSEC_REG_WR(RTC_MSEC_IN_U64MSEC(ullMsec)); - } - - return; -} - -//***************************************************************************** -// -//! Get the instantaneous calendar time from the device. -//! -//! \param ulSecs refers to the seconds part of the calendar time -//! \param usMsec refers to the fractional (ms) part of the second -//! -//! This function fetches the instantaneous value of the ticking calendar time -//! from the device. The calendar time is outlined in terms of seconds and -//! milliseconds. -//! -//! The device provides the calendar value that has been maintained across -//! active and low power states. -//! -//! The function PRCMRTCSet() must have been invoked once to set a reference. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec) -{ - unsigned long long ullMsec = 0; - - if(IS_RTC_USED()) { - ullMsec = RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), - RTC_U16MSEC_REG_RD()); - ullMsec += SCC_U64MSEC_GET(); - } - - *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec); - *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec); - - return; -} - -//***************************************************************************** -// -//! Set a calendar time alarm. -//! -//! \param ulSecs refers to the seconds part of the calendar time -//! \param usMsec refers to the fractional (ms) part of the second -//! -//! This function sets an wall-clock alarm in the device to be reported for a -//! futuristic calendar time. The calendar time is outlined in terms of seconds -//! and milliseconds. -//! -//! The device provides uses the calendar value that has been maintained across -//! active and low power states to report attainment of alarm time. -//! -//! The function PRCMRTCSet() must have been invoked once to set a reference. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec) -{ - unsigned long long ullMsec = 0; - - if(IS_RTC_USED()) { - ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec); - ullMsec -= RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), - RTC_U16MSEC_REG_RD()); - SCC_U64MSEC_MATCH_SET(SELECT_SCC_U42BITS(ullMsec)); - } - - return; -} - -//***************************************************************************** -// -//! Get a previously set calendar time alarm. -//! -//! \param ulSecs refers to the seconds part of the calendar time -//! \param usMsec refers to the fractional (ms) part of the second -//! -//! This function fetches from the device a wall-clock alarm that would have -//! been previously set in the device. The calendar time is outlined in terms -//! of seconds and milliseconds. -//! -//! If no alarm was set in the past, then this function would fetch a random -//! information. -//! -//! The function PRCMRTCMatchSet() must have been invoked once to set an alarm. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec) -{ - unsigned long long ullMsec = 0; - - if(IS_RTC_USED()) { - ullMsec = SCC_U64MSEC_MATCH_GET(); - ullMsec += RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), - RTC_U16MSEC_REG_RD()); - } - - *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec); - *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec); - - return; -} - -//***************************************************************************** -// -//! MCU Initialization Routine -//! -//! This function contains all the mandatory bug fixes, ECO enables, -//! initializations for both CC3200 and CC3220. -//! -//! \note \b ###IMPORTANT### : This is a routine which should be one of the -//! first things to be executed after control comes to MCU Application code. -//! -//! \return None -// -//***************************************************************************** -void PRCMCC3200MCUInit() -{ - - if( PRCMSysResetCauseGet() != PRCM_LPDS_EXIT ) - { - if( 0x00010001 == HWREG(0x00000400) ) - { - -#ifndef REMOVE_CC3200_ES_1_2_1_CODE - - unsigned long ulRegVal; - - // - // DIG DCDC NFET SEL and COT mode disable - // - HWREG(0x4402F010) = 0x30031820; - HWREG(0x4402F00C) = 0x04000000; - - UtilsDelay(32000); - - // - // ANA DCDC clock config - // - HWREG(0x4402F11C) = 0x099; - HWREG(0x4402F11C) = 0x0AA; - HWREG(0x4402F11C) = 0x1AA; - - // - // PA DCDC clock config - // - HWREG(0x4402F124) = 0x099; - HWREG(0x4402F124) = 0x0AA; - HWREG(0x4402F124) = 0x1AA; - - // - // TD Flash timing configurations in case of MCU WDT reset - // - if((HWREG(0x4402D00C) & 0xFF) == 0x00000005) - { - HWREG(0x400F707C) |= 0x01840082; - HWREG(0x400F70C4)= 0x1; - HWREG(0x400F70C4)= 0x0; - } - - // - // Take I2C semaphore - // - ulRegVal = HWREG(0x400F7000); - ulRegVal = (ulRegVal & ~0x3) | 0x1; - HWREG(0x400F7000) = ulRegVal; - - // - // Take GPIO semaphore - // - ulRegVal = HWREG(0x400F703C); - ulRegVal = (ulRegVal & ~0x3FF) | 0x155; - HWREG(0x400F703C) = ulRegVal; - - // - // Enable 32KHz internal RC oscillator - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_INT_OSC_CONF, 0x00000101); - - // - // Delay for a little bit. - // - UtilsDelay(8000); - - // - // Enable 16MHz clock - // - HWREG(HIB1P2_BASE+HIB1P2_O_CM_OSC_16M_CONFIG) = 0x00010008; - - // - // Delay for a little bit. - // - UtilsDelay(8000); - -#endif // REMOVE_CC3200_ES_1_2_1_CODE - - } - else - { - - unsigned long ulRegValue; - - // - // DIG DCDC LPDS ECO Enable - // - HWREG(0x4402F064) |= 0x800000; - - // - // Enable hibernate ECO for PG 1.32 devices only. With this ECO enabled, - // any hibernate wakeup source will be kept maked until the device enters - // hibernate completely (analog + digital) - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0, ulRegValue | (1<<4)); - - // - // Handling the clock switching (for 1.32 only) - // - HWREG(0x4402E16C) |= 0x3C; - } - - - // - // Enable uDMA - // - PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK); - - // - // Reset uDMA - // - PRCMPeripheralReset(PRCM_UDMA); - - // - // Disable uDMA - // - PRCMPeripheralClkDisable(PRCM_UDMA,PRCM_RUN_MODE_CLK); - - // - // Enable RTC - // - - PRCMHIBRegWrite(0x4402F804,0x1); - - // - // Enable Timers - // - PRCMPeripheralClkEnable(PRCM_TIMERA0,PRCM_RUN_MODE_CLK); - PRCMPeripheralClkEnable(PRCM_TIMERA1,PRCM_RUN_MODE_CLK); - PRCMPeripheralClkEnable(PRCM_TIMERA2,PRCM_RUN_MODE_CLK); - PRCMPeripheralClkEnable(PRCM_TIMERA3,PRCM_RUN_MODE_CLK); - - // - // Enable UART0 - // - PRCMPeripheralClkEnable(PRCM_UARTA0,PRCM_RUN_MODE_CLK); - PRCMPeripheralClkEnable(PRCM_UARTA1,PRCM_RUN_MODE_CLK); - - // - // Enable GPIOs - // - PRCMPeripheralClkEnable(PRCM_GPIOA0,PRCM_RUN_MODE_CLK); - PRCMPeripheralClkEnable(PRCM_GPIOA1,PRCM_RUN_MODE_CLK); - PRCMPeripheralClkEnable(PRCM_GPIOA2,PRCM_RUN_MODE_CLK); - PRCMPeripheralClkEnable(PRCM_GPIOA3,PRCM_RUN_MODE_CLK); - - // - // Enable SPI - // - PRCMPeripheralClkEnable(PRCM_GSPI,PRCM_RUN_MODE_CLK); - - // - // SWD mode - // - if(((HWREG(0x4402F0C8) & 0xFF) == 0x2)) - { - HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2); - HWREG(0x4402E114) = ((HWREG(0x4402E114) & ~0xC0F) | 0x2); - } - - // - // Override JTAG mux - // - HWREG(0x4402E184) |= 0x2; - - // - // Change UART pins(55,57) mode to PIN_MODE_0 if they are in PIN_MODE_1 - // - if (PinModeGet(PIN_55) == PIN_MODE_1) - { - PinModeSet(PIN_55,PIN_MODE_0); - } - if (PinModeGet(PIN_57) == PIN_MODE_1) - { - PinModeSet(PIN_57,PIN_MODE_0); - } - - // - // Change I2C pins(1,2) mode to PIN_MODE_0 if they are in PIN_MODE_1 - // - if (PinModeGet(PIN_01) == PIN_MODE_1) - { - PinModeSet(PIN_01,PIN_MODE_0); - } - if (PinModeGet(PIN_02) == PIN_MODE_1) - { - PinModeSet(PIN_02,PIN_MODE_0); - } - - // - // DIG DCDC VOUT trim settings based on PROCESS INDICATOR - // - if(((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE) - { - HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x32 << 18)); - } - else - { - HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x29 << 18)); - } - - // - // Enable SOFT RESTART in case of DIG DCDC collapse - // - HWREG(0x4402FC74) &= ~(0x10000000); - - // - // Required only if ROM version is lower than 2.x.x - // - if( (HWREG(0x00000400) & 0xFFFF) < 2 ) - { - // - // Disable the sleep for ANA DCDC - // - HWREG(0x4402F0A8) |= 0x00000004 ; - } - else if( (HWREG(0x00000400) >> 16) >= 1 ) - { - // - // Enable NWP force reset and HIB on WDT reset - // Enable direct boot path for flash - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= ((7<<5) | 0x1); - if((HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) & 0x1) ) - { - HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) &= ~0x1; - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= (1<<9); - - // - // Clear the RTC hib wake up source - // - HWREG(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN) &= ~0x1; - - // - // Reset RTC match value - // - HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF) = 0; - HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF) = 0; - - } - } - - unsigned long efuse_reg2; - unsigned long ulDevMajorVer, ulDevMinorVer; - // - // Read the device identification register - // - efuse_reg2= HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); - - // - // Read the ROM mojor and minor version - // - ulDevMajorVer = ((efuse_reg2 >> 28) & 0xF); - ulDevMinorVer = ((efuse_reg2 >> 24) & 0xF); - - if(((ulDevMajorVer == 0x3) && (ulDevMinorVer == 0)) || (ulDevMajorVer < 0x3)) - { - unsigned int Scratch, PreRegulatedMode; - - // 0x4402F840 => 6th bit “1” indicates device is in pre-regulated mode. - PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; - - if( PreRegulatedMode) - { - Scratch = HWREG(0x4402F028); - Scratch &= 0xFFFFFF7F; // <7:7> = 0 - HWREG(0x4402F028) = Scratch; - - Scratch = HWREG(0x4402F010); - Scratch &= 0x0FFFFFFF; // <31:28> = 0 - Scratch |= 0x10000000; // <31:28> = 1 - HWREG(0x4402F010) = Scratch; - } - else - { - Scratch = HWREG(0x4402F024); - - Scratch &= 0xFFFFFFF0; // <3:0> = 0 - Scratch |= 0x00000001; // <3:0> = 1 - Scratch &= 0xFFFFF0FF; // <11:8> = 0000 - Scratch |= 0x00000500; // <11:8> = 0101 - Scratch &= 0xFFFE7FFF; // <16:15> = 0000 - Scratch |= 0x00010000; // <16:15> = 10 - - HWREG(0x4402F024) = Scratch; - - Scratch = HWREG(0x4402F028); - - Scratch &= 0xFFFFFF7F; // <7:7> = 0 - Scratch &= 0x0FFFFFFF; // <31:28> = 0 - Scratch &= 0xFF0FFFFF; // <23:20> = 0 - Scratch |= 0x00300000; // <23:20> = 0011 - Scratch &= 0xFFF0FFFF; // <19:16> = 0 - Scratch |= 0x00030000; // <19:16> = 0011 - - HWREG(0x4402F028) = Scratch; - HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 - } - } - else - { - unsigned int Scratch, PreRegulatedMode; - - // 0x4402F840 => 6th bit “1” indicates device is in pre-regulated mode. - PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; - - Scratch = HWREG(0x4402F028); - Scratch &= 0xFFFFFF7F; // <7:7> = 0 - HWREG(0x4402F028) = Scratch; - - HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 - if( PreRegulatedMode) - { - HWREG(0x4402F010) |= 0x10000000; // <31:28> = 1 - } - } - } - else - { - unsigned long ulRegVal; - - // - // I2C Configuration - // - ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register); - ulRegVal = (ulRegVal & ~0x3) | 0x1; - HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = ulRegVal; - - // - // GPIO configuration - // - ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register); - ulRegVal = (ulRegVal & ~0x3FF) | 0x155; - HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = ulRegVal; - - } -} - -//***************************************************************************** -// -//! Reads 32-bit value from register at specified address -//! -//! \param ulRegAddr is the address of register to be read. -//! -//! This function reads 32-bit value from the register as specified by -//! \e ulRegAddr. -//! -//! \return Return the value of the register. -// -//***************************************************************************** -unsigned long PRCMHIBRegRead(unsigned long ulRegAddr) -{ - unsigned long ulValue; - - // - // Read the Reg value - // - ulValue = HWREG(ulRegAddr); - - // - // Wait for 200 uSec - // - UtilsDelay((80*200)/3); - - // - // Return the value - // - return ulValue; -} - -//***************************************************************************** -// -//! Writes 32-bit value to register at specified address -//! -//! \param ulRegAddr is the address of register to be read. -//! \param ulValue is the 32-bit value to be written. -//! -//! This function writes 32-bit value passed as \e ulValue to the register as -//! specified by \e ulRegAddr -//! -//! \return None -// -//***************************************************************************** -void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue) -{ - // - // Read the Reg value - // - HWREG(ulRegAddr) = ulValue; - - // - // Wait for 200 uSec - // - UtilsDelay((80*200)/3); -} - -//***************************************************************************** -// -//! \param ulDivider is clock frequency divider value -//! \param ulWidth is the width of the high pulse -//! -//! This function sets the input frequency for camera module. -//! -//! The frequency is calculated as follows: -//! -//! f_out = 240MHz/ulDivider; -//! -//! The parameter \e ulWidth sets the width of the high pulse. -//! -//! For e.g.: -//! -//! ulDivider = 4; -//! ulWidth = 2; -//! -//! f_out = 30 MHz and 50% duty cycle -//! -//! And, -//! -//! ulDivider = 4; -//! ulWidth = 1; -//! -//! f_out = 30 MHz and 25% duty cycle -//! -//! \return 0 on success, 1 on error -// -//***************************************************************************** -unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth) -{ - if(ulDivider > ulWidth && ulWidth != 0 ) - { - // - // Set the hifh pulse width - // - HWREG(ARCM_BASE + - APPS_RCM_O_CAMERA_CLK_GEN) = (((ulWidth & 0x07) -1) << 8); - - // - // Set the low pulse width - // - HWREG(ARCM_BASE + - APPS_RCM_O_CAMERA_CLK_GEN) = ((ulDivider - ulWidth - 1) & 0x07); - // - // Return success - // - return 0; - } - - // - // Success; - // - return 1; -} - -//***************************************************************************** -// -//! Enable the IO value retention -//! -//! \param ulIORetGrpFlags is one of the valid IO groups. -//! -//! This function enables the IO retention for group of pins as specified by -//! \e ulIORetGrpFlags parameter. Enabling retention will immediately lock the -//! digital pins, in the specified group, to their current state (0 or 1). -//! Output pins can only be driven when retention is disabled. -//! -//! The parameter \e ulIORetGrpFlags can be logical OR of one or -//! more of the following: -//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface -//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 -//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 -//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 -//! -//! \note Use case is to park the pins when entering HIB. -//! -//! \return None. -// -//***************************************************************************** -void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags) -{ - unsigned long ulRegVal; - - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Disable IO Pad to ODI Path - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00001D00; - - // - // 0b'0 in bit 5 for JTAG PADS - // 0b'0 in bit 0 for all other IOs - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00000023); - - // - // Enable retention for GRP0 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF); - ulRegVal |= 0x5; - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF,ulRegVal); - } - - // - // Enable retention for GRP1 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); - ulRegVal |= ((0x3<<5)); - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0,ulRegVal); - } - - // - // Enable retention for GRP2 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); - ulRegVal |= 0x00000101; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); - } - - // - // Enable retention for GRP3 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); - ulRegVal |= 0x00000204; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); - } - } -} - -//***************************************************************************** -// -//! Disable the IO value retention -//! -//! \param ulIORetGrpFlags is one of the valid IO groups. -//! -//! This function disable the IO retention for group of pins as specified by -//! \e ulIORetGrpFlags parameter. Disabling retention will unlock the -//! digital pins in the specified group. Output pins can only be driven when -//! retention is disabled. -//! -//! The parameter \e ulIORetGrpFlags can be logical OR of one or -//! more of the following: -//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface -//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 -//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 -//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 -//! -//! \note Use case is to un-park the pins when exiting HIB -//! -//! \return None. -// -//***************************************************************************** -void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags) -{ - unsigned long ulRegVal; - - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - - // - // Enable IO Pad to ODI Path - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00001D00); - - // - // 0b'1 in bit 5 for JTAG PADS - // 0b'1 in bit 0 for all other IOs - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00000023; - - // - // Disable retention for GRP0 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF); - ulRegVal &= ~0x5; - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF,ulRegVal); - } - - // - // Disable retention for GRP1 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); - ulRegVal &= ~((0x3<<5)); - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0,ulRegVal); - } - - // - // Disable retention for GRP2 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); - ulRegVal &= ~0x00000101; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); - - } - - // - // Disable retention for GRP3 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); - ulRegVal &= ~0x00000204; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); - } - - } -} - -//***************************************************************************** -// -//! Gets the device type -//! -//! This function returns bit-packed value representing the device type -//! -//! The returned value is logical OR of one or more of the following:- -//! -//! -\b PRCM_DEV_TYPE_FLAG_R - R variant -//! -\b PRCM_DEV_TYPE_FLAG_F - F variant -//! -\b PRCM_DEV_TYPE_FLAG_Z - Z variant -//! -\b PRCM_DEV_TYPE_FLAG_SECURE - Device is secure -//! -\b PRCM_DEV_TYPE_FLAG_PRE_PROD - Device is a pre-production part -//! -\b PRCM_DEV_TYPE_FLAG_3200 - Device is CC3200 -//! -\b PRCM_DEV_TYPE_FLAG_3220 - Device is CC3220 -//! -\b PRCM_DEV_TYPE_FLAG_REV1 - Device Rev 1 -//! -\b PRCM_DEV_TYPE_FLAG_REV2 - Device Rev 2 -//! -//! Pre-defined helper macros:- -//! -//! -\b PRCM_DEV_TYPE_PRE_CC3200R - Pre-Production CC3200R -//! -\b PRCM_DEV_TYPE_PRE_CC3200F - Pre-Production CC3200F -//! -\b PRCM_DEV_TYPE_PRE_CC3200Z - Pre-Production CC3200Z -//! -\b PRCM_DEV_TYPE_CC3200R - Production CC3200R -//! -\b PRCM_DEV_TYPE_PRE_CC3220R - Pre-Production CC3220R -//! -\b PRCM_DEV_TYPE_PRE_CC3220F - Pre-Production CC3220F -//! -\b PRCM_DEV_TYPE_PRE_CC3220Z - Pre-Production CC3220Z -//! -\b PRCM_DEV_TYPE_CC3220R - Production CC3220R -//! -\b PRCM_DEV_TYPE_PRE_CC3220RS - Pre-Production CC3220RS -//! -\b PRCM_DEV_TYPE_PRE_CC3220FS - Pre-Production CC3220FS -//! -\b PRCM_DEV_TYPE_PRE_CC3220ZS - Pre-Production CC3220ZS -//! -\b PRCM_DEV_TYPE_CC3220RS - Production CC3220RS -//! -\b PRCM_DEV_TYPE_CC3220FS - Production CC3220FS -//! -//! \return Returns, bit-packed value representing the device type, -//! or 0 if device is unknown -// -//***************************************************************************** -unsigned long PRCMDeviceTypeGet() -{ - unsigned long ulDevType; - unsigned long ulChipId; - unsigned long ulDevMajorVer; - unsigned long ulDevMinorVer; - - // - // Read the device identification register - // - ulChipId = HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); - - // - // Read the ROM mojor and minor version - // - ulDevMajorVer = ((ulChipId >> 28) & 0xF); - ulDevMinorVer = ((ulChipId >> 24) & 0xF); - - - ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); - - // - // Get the device variant from the chip id - // - switch((ulChipId & 0xF)) - { - // - // It is R variant - // - case 0x0: - ulDevType = PRCM_DEV_TYPE_FLAG_R; - break; - - // - // It is F variant, non secure F variant is always Pre-Production - // - case 0x1: - ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_PRE_PROD; - break; - - // - // It is Z variant and is always Pre-Production - // - case 0x3: - ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_PRE_PROD; - break; - - // - // It is Secure R - // - case 0x8: - ulDevType = PRCM_DEV_TYPE_FLAG_R|PRCM_DEV_TYPE_FLAG_SECURE; - break; - - // - // It is Secure F - // - case 0x9: - ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_SECURE; - break; - - // - // It is secure Z variant and variant is always Pre-Production - // - case 0xB: - ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_SECURE| - PRCM_DEV_TYPE_FLAG_PRE_PROD; - break; - - // - // Undefined variant - // - default: - ulDevType = 0x0; - } - - if( ulDevType != 0 ) - { - if( ulDevMajorVer == 0x3 ) - { - ulDevType |= PRCM_DEV_TYPE_FLAG_3220; - } - else if( ulDevMajorVer == 0x2 ) - { - ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220); - - if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0) ) - { - if(ulDevMinorVer == 0x0) - { - ulDevType |= PRCM_DEV_TYPE_FLAG_REV1; - } - else - { - ulDevType |= PRCM_DEV_TYPE_FLAG_REV2; - } - } - else - { - if(ulDevMinorVer == 0x1) - { - ulDevType |= PRCM_DEV_TYPE_FLAG_REV1; - } - } - } - else - { - if(ulDevMinorVer == 0x4) - { - if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0)) - { - ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220); - } - else - { - ulDevType |= PRCM_DEV_TYPE_FLAG_3200; - } - } - else - { - ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3200); - } - } - } - - - return ulDevType; -} - - - -//**************************************************************************** -// -//! Used to trigger a hibernate cycle for the device using RTC -//! -//! This API can be used to do a clean reboot of device. -//! -//! \note This routine should only be exercised after all the network processing -//! has been stopped. To stop network processing use \b sl_stop API from -//! simplelink library. -//! -//! \return None -// -//**************************************************************************** -void PRCMHibernateCycleTrigger() -{ - unsigned long ulRegValue; - unsigned long long ullRTCVal; - - // - // Read the RTC register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); - - // - // Enable the RTC as wakeup source if specified - // - ulRegValue |= (PRCM_HIB_SLOW_CLK_CTR & 0x1); - - // - // Enable HIB wakeup sources - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); - - // - // Latch the RTC vlaue - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1); - - // - // Read latched values as 2 32-bit vlaues - // - ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW); - ullRTCVal = ullRTCVal << 32; - ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW); - - // - //Considering worst case execution times of ROM,RAM,Flash value of 160 is used - // - ullRTCVal = ullRTCVal + 160; - - // - // Set RTC match value - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF, - (unsigned long)(ullRTCVal)); - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF, - (unsigned long)(ullRTCVal>>32)); - // - // Note : Any addition of code after this line would need a change in - // ullTicks Interval currently set to 160 - // - - // - // Request hibernate. - // - PRCMHIBRegWrite((HIB3P3_BASE+HIB3P3_O_MEM_HIB_REQ),0x1); - - // - // Wait for system to enter hibernate - // - __asm(" wfi\n"); - - // - // Infinite loop - // - while(1) - { - - } -} - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.h deleted file mode 100755 index 73785aa9756..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// prcm.h -// -// Prototypes for the PRCM control driver. -// -//***************************************************************************** - -#ifndef __PRCM_H__ -#define __PRCM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Peripheral clock and reset control registers -// -//***************************************************************************** -typedef struct _PRCM_PeripheralRegs_ -{ - -unsigned long ulClkReg; -unsigned long ulRstReg; - -}PRCM_PeriphRegs_t; - -//***************************************************************************** -// Values that can be passed to PRCMPeripheralEnable() and -// PRCMPeripheralDisable() -//***************************************************************************** -#define PRCM_RUN_MODE_CLK 0x00000001 -#define PRCM_SLP_MODE_CLK 0x00000100 - -//***************************************************************************** -// Values that can be passed to PRCMSRAMRetentionEnable() and -// PRCMSRAMRetentionDisable() as ulSramColSel. -//***************************************************************************** -#define PRCM_SRAM_COL_1 0x00000001 -#define PRCM_SRAM_COL_2 0x00000002 -#define PRCM_SRAM_COL_3 0x00000004 -#define PRCM_SRAM_COL_4 0x00000008 - -//***************************************************************************** -// Values that can be passed to PRCMSRAMRetentionEnable() and -// PRCMSRAMRetentionDisable() as ulModeFlags. -//***************************************************************************** -#define PRCM_SRAM_LPDS_RET 0x00000002 - -//***************************************************************************** -// Values that can be passed to PRCMLPDSWakeupSourceEnable(), -// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable(). -//***************************************************************************** -#define PRCM_LPDS_HOST_IRQ 0x00000080 -#define PRCM_LPDS_GPIO 0x00000010 -#define PRCM_LPDS_TIMER 0x00000001 - -//***************************************************************************** -// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type -//***************************************************************************** -#define PRCM_LPDS_LOW_LEVEL 0x00000002 -#define PRCM_LPDS_HIGH_LEVEL 0x00000000 -#define PRCM_LPDS_FALL_EDGE 0x00000001 -#define PRCM_LPDS_RISE_EDGE 0x00000003 - -//***************************************************************************** -// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() -//***************************************************************************** -#define PRCM_LPDS_GPIO2 0x00000000 -#define PRCM_LPDS_GPIO4 0x00000001 -#define PRCM_LPDS_GPIO13 0x00000002 -#define PRCM_LPDS_GPIO17 0x00000003 -#define PRCM_LPDS_GPIO11 0x00000004 -#define PRCM_LPDS_GPIO24 0x00000005 -#define PRCM_LPDS_GPIO26 0x00000006 - -//***************************************************************************** -// Values that can be passed to PRCMHibernateWakeupSourceEnable(), -// PRCMHibernateWakeupSourceDisable(). -//***************************************************************************** -#define PRCM_HIB_SLOW_CLK_CTR 0x00000001 - -//***************************************************************************** -// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType -//***************************************************************************** -#define PRCM_HIB_LOW_LEVEL 0x00000000 -#define PRCM_HIB_HIGH_LEVEL 0x00000001 -#define PRCM_HIB_FALL_EDGE 0x00000002 -#define PRCM_HIB_RISE_EDGE 0x00000003 - -//***************************************************************************** -// Values that can be passed to PRCMHibernateWakeupSourceEnable(), -// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect() -//***************************************************************************** -#define PRCM_HIB_GPIO2 0x00010000 -#define PRCM_HIB_GPIO4 0x00020000 -#define PRCM_HIB_GPIO13 0x00040000 -#define PRCM_HIB_GPIO17 0x00080000 -#define PRCM_HIB_GPIO11 0x00100000 -#define PRCM_HIB_GPIO24 0x00200000 -#define PRCM_HIB_GPIO26 0x00400000 - -//***************************************************************************** -// Values that will be returned from PRCMSysResetCauseGet(). -//***************************************************************************** -#define PRCM_POWER_ON 0x00000000 -#define PRCM_LPDS_EXIT 0x00000001 -#define PRCM_CORE_RESET 0x00000003 -#define PRCM_MCU_RESET 0x00000004 -#define PRCM_WDT_RESET 0x00000005 -#define PRCM_SOC_RESET 0x00000006 -#define PRCM_HIB_EXIT 0x00000007 - -//***************************************************************************** -// Values that can be passed to PRCMHibernateWakeupCauseGet(). -//***************************************************************************** -#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002 -#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004 - -//***************************************************************************** -// Values that can be passed to PRCMSEnableInterrupt -//***************************************************************************** -#define PRCM_INT_SLOW_CLK_CTR 0x00004000 - -//***************************************************************************** -// Values that can be passed to PRCMPeripheralClkEnable(), -// PRCMPeripheralClkDisable(), PRCMPeripheralReset() -//***************************************************************************** -#define PRCM_CAMERA 0x00000000 -#define PRCM_I2S 0x00000001 -#define PRCM_SDHOST 0x00000002 -#define PRCM_GSPI 0x00000003 -#define PRCM_LSPI 0x00000004 -#define PRCM_UDMA 0x00000005 -#define PRCM_GPIOA0 0x00000006 -#define PRCM_GPIOA1 0x00000007 -#define PRCM_GPIOA2 0x00000008 -#define PRCM_GPIOA3 0x00000009 -#define PRCM_GPIOA4 0x0000000A -#define PRCM_WDT 0x0000000B -#define PRCM_UARTA0 0x0000000C -#define PRCM_UARTA1 0x0000000D -#define PRCM_TIMERA0 0x0000000E -#define PRCM_TIMERA1 0x0000000F -#define PRCM_TIMERA2 0x00000010 -#define PRCM_TIMERA3 0x00000011 -#define PRCM_DTHE 0x00000012 -#define PRCM_SSPI 0x00000013 -#define PRCM_I2CA0 0x00000014 -// Note : PRCM_ADC is a dummy define for pinmux utility code generation -// PRCM_ADC should never be used in any user code. -#define PRCM_ADC 0x000000FF - - -//***************************************************************************** -// Values that can be passed to PRCMIORetEnable() and PRCMIORetDisable() -//***************************************************************************** -#define PRCM_IO_RET_GRP_0 0x00000001 -#define PRCM_IO_RET_GRP_1 0x00000002 -#define PRCM_IO_RET_GRP_2 0x00000004 -#define PRCM_IO_RET_GRP_3 0x00000008 - -//***************************************************************************** -// Macros definig the device type -//***************************************************************************** -#define PRCM_DEV_TYPE_FLAG_R 0x00000001 -#define PRCM_DEV_TYPE_FLAG_F 0x00000002 -#define PRCM_DEV_TYPE_FLAG_Z 0x00000004 -#define PRCM_DEV_TYPE_FLAG_SECURE 0x00000008 -#define PRCM_DEV_TYPE_FLAG_PRE_PROD 0x00000010 -#define PRCM_DEV_TYPE_FLAG_3200 0x00000020 -#define PRCM_DEV_TYPE_FLAG_3220 0x00000040 -#define PRCM_DEV_TYPE_FLAG_REV1 0x00010000 -#define PRCM_DEV_TYPE_FLAG_REV2 0x00020000 - -//***************************************************************************** -// Pre-defined helper macros -//***************************************************************************** -#define PRCM_DEV_TYPE_PRE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3200| \ - PRCM_DEV_TYPE_FLAG_R) - -#define PRCM_DEV_TYPE_PRE_CC3200F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3200| \ - PRCM_DEV_TYPE_FLAG_F) - -#define PRCM_DEV_TYPE_PRE_CC3200Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3200| \ - PRCM_DEV_TYPE_FLAG_Z) - -#define PRCM_DEV_TYPE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3200| \ - PRCM_DEV_TYPE_FLAG_R) - -#define PRCM_DEV_TYPE_PRE_CC3220R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_R) - -#define PRCM_DEV_TYPE_PRE_CC3220F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_F) - -#define PRCM_DEV_TYPE_PRE_CC3220Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_Z) - -#define PRCM_DEV_TYPE_CC3220R (PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_R) - - -#define PRCM_DEV_TYPE_PRE_CC3220RS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_R| \ - PRCM_DEV_TYPE_FLAG_SECURE) - -#define PRCM_DEV_TYPE_PRE_CC3220FS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_F| \ - PRCM_DEV_TYPE_FLAG_SECURE) - -#define PRCM_DEV_TYPE_PRE_CC3220ZS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_Z| \ - PRCM_DEV_TYPE_FLAG_SECURE) - -#define PRCM_DEV_TYPE_CC3220RS (PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_R| \ - PRCM_DEV_TYPE_FLAG_SECURE) - -#define PRCM_DEV_TYPE_CC3220FS (PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_F| \ - PRCM_DEV_TYPE_FLAG_SECURE) - - -#define PRCM_DEV_TYPE_PRE_CC3220Z1 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_Z| \ - PRCM_DEV_TYPE_FLAG_REV1) - -#define PRCM_DEV_TYPE_PRE_CC3220Z2 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_Z| \ - PRCM_DEV_TYPE_FLAG_REV2) - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PRCMMCUReset(tBoolean bIncludeSubsystem); -extern unsigned long PRCMSysResetCauseGet(void); - -extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral, - unsigned long ulClkFlags); -extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral, - unsigned long ulClkFlags); -extern void PRCMPeripheralReset(unsigned long ulPeripheral); -extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral); - -extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq); -extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral); - -extern void PRCMSleepEnter(void); - -extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel, - unsigned long ulFlags); -extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel, - unsigned long ulFlags); -extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP, - unsigned long ulRestorePC); -extern void PRCMLPDSEnter(void); -extern void PRCMLPDSIntervalSet(unsigned long ulTicks); -extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc); -extern unsigned long PRCMLPDSWakeupCauseGet(void); -extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, - unsigned long ulType); -extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc); - -extern void PRCMHibernateEnter(void); -extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc); -extern unsigned long PRCMHibernateWakeupCauseGet(void); -extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap, - unsigned long ulType); -extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc); -extern void PRCMHibernateIntervalSet(unsigned long long ullTicks); - -extern unsigned long long PRCMSlowClkCtrGet(void); -extern unsigned long long PRCMSlowClkCtrFastGet(void); -extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks); -extern unsigned long long PRCMSlowClkCtrMatchGet(void); - -extern void PRCMOCRRegisterWrite(unsigned char ucIndex, - unsigned long ulRegValue); -extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex); - -extern void PRCMIntRegister(void (*pfnHandler)(void)); -extern void PRCMIntUnregister(void); -extern void PRCMIntEnable(unsigned long ulIntFlags); -extern void PRCMIntDisable(unsigned long ulIntFlags); -extern unsigned long PRCMIntStatus(void); -extern void PRCMRTCInUseSet(void); -extern tBoolean PRCMRTCInUseGet(void); -extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec); -extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec); -extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec); -extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec); -extern void PRCMCC3200MCUInit(void); -extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr); -extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue); -extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider, - unsigned char ulWidth); -extern void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags); -extern void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags); -extern unsigned long PRCMDeviceTypeGet(void); -extern void PRCMLPDSEnterKeepDebugIf(void); -extern void PRCMHibernateCycleTrigger(void); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __PRCM_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom.h deleted file mode 100755 index cac74cdde17..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom.h +++ /dev/null @@ -1,2787 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// rom.h - Macros to facilitate calling functions in the ROM. -// -// -//***************************************************************************** -// -// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND. -// -//***************************************************************************** - -#ifndef __ROM_H__ -#define __ROM_H__ - -//***************************************************************************** -// -// For backward compatibility with older Driverlib versions -// -//***************************************************************************** -#ifdef TARGET_IS_CC3200 -#define USE_CC3200_ROM_DRV_API -#endif - -//***************************************************************************** -// -// Pointers to the main API tables. -// -//***************************************************************************** -#define ROM_APITABLE ((unsigned long *)0x0000040C) -#define ROM_VERSION (ROM_APITABLE[0]) -#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) -#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[2])) -#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[3])) -#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[4])) -#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[5])) -#define ROM_PRCMTABLE ((unsigned long *)(ROM_APITABLE[6])) -#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[7])) -#define ROM_SPITABLE ((unsigned long *)(ROM_APITABLE[8])) -#define ROM_CAMERATABLE ((unsigned long *)(ROM_APITABLE[9])) -#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[10])) -#define ROM_PINTABLE ((unsigned long *)(ROM_APITABLE[11])) -#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[12])) -#define ROM_UTILSTABLE ((unsigned long *)(ROM_APITABLE[13])) -#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[14])) -#define ROM_HWSPINLOCKTABLE ((unsigned long *)(ROM_APITABLE[15])) -#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[16])) -#define ROM_AESTABLE ((unsigned long *)(ROM_APITABLE[17])) -#define ROM_DESTABLE ((unsigned long *)(ROM_APITABLE[18])) -#define ROM_SHAMD5TABLE ((unsigned long *)(ROM_APITABLE[19])) -#define ROM_CRCTABLE ((unsigned long *)(ROM_APITABLE[20])) -#define ROM_SDHOSTTABLE ((unsigned long *)(ROM_APITABLE[21])) -#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[22])) -#define ROM_CPUTABLE ((unsigned long *)(ROM_APITABLE[23])) - -//***************************************************************************** -// -// Macros for calling ROM functions in the Interrupt API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntEnable \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntMasterEnable \ - ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntMasterDisable \ - ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntDisable \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityGroupingSet \ - ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityGroupingGet \ - ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPrioritySet \ - ((void (*)(unsigned long ulInterrupt, \ - unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityGet \ - ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPendSet \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPendClear \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityMaskSet \ - ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityMaskGet \ - ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntRegister \ - ((void (*)(unsigned long ulInterrupt, \ - void (*pfnHandler)(void)))ROM_INTERRUPTTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntUnregister \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntVTableBaseSet \ - ((void (*)(unsigned long ulVtableBase))ROM_INTERRUPTTABLE[14]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Timer API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerConfigure \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulConfig))ROM_TIMERTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerControlLevel \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - tBoolean bInvert))ROM_TIMERTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerControlEvent \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulEvent))ROM_TIMERTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerControlStall \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - tBoolean bStall))ROM_TIMERTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerPrescaleSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerPrescaleGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerPrescaleMatchSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerPrescaleMatchGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerLoadSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerLoadGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerValueGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerMatchSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerMatchGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntRegister \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - void (*pfnHandler)(void)))ROM_TIMERTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntUnregister \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_TIMERTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_TIMERTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - tBoolean bMasked))ROM_TIMERTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_TIMERTABLE[20]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerValueSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[22]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerDMAEventSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDMAEvent))ROM_TIMERTABLE[23]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerDMAEventGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_TIMERTABLE[24]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the UART API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTParityModeSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulParity))ROM_UARTTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTParityModeGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFIFOLevelSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTxLevel, \ - unsigned long ulRxLevel))ROM_UARTTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFIFOLevelGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long *pulTxLevel, \ - unsigned long *pulRxLevel))ROM_UARTTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTConfigSetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulUARTClk, \ - unsigned long ulBaud, \ - unsigned long ulConfig))ROM_UARTTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulUARTClk, \ - unsigned long *pulBaud, \ - unsigned long *pulConfig))ROM_UARTTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTEnable \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTDisable \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFIFOEnable \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFIFODisable \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharsAvail \ - ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTSpaceAvail \ - ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharGetNonBlocking \ - ((long (*)(unsigned long ulBase))ROM_UARTTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharGet \ - ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharPutNonBlocking \ - ((tBoolean (*)(unsigned long ulBase, \ - unsigned char ucData))ROM_UARTTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharPut \ - ((void (*)(unsigned long ulBase, \ - unsigned char ucData))ROM_UARTTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTBreakCtl \ - ((void (*)(unsigned long ulBase, \ - tBoolean bBreakState))ROM_UARTTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTBusy \ - ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntRegister \ - ((void (*)(unsigned long ulBase, \ - void(*pfnHandler)(void)))ROM_UARTTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_UARTTABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_UARTTABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - tBoolean bMasked))ROM_UARTTABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_UARTTABLE[23]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTDMAEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDMAFlags))ROM_UARTTABLE[24]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTDMADisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDMAFlags))ROM_UARTTABLE[25]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTRxErrorGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[26]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTRxErrorClear \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[27]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTModemControlSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulControl))ROM_UARTTABLE[28]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTModemControlClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulControl))ROM_UARTTABLE[29]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTModemControlGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[30]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTModemStatusGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[31]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFlowControlSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulMode))ROM_UARTTABLE[32]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFlowControlGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[33]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTTxIntModeSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulMode))ROM_UARTTABLE[34]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTTxIntModeGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[35]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the uDMA API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelTransferSet \ - ((void (*)(unsigned long ulChannelStructIndex, \ - unsigned long ulMode, \ - void *pvSrcAddr, \ - void *pvDstAddr, \ - unsigned long ulTransferSize))ROM_UDMATABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAEnable \ - ((void (*)(void))ROM_UDMATABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMADisable \ - ((void (*)(void))ROM_UDMATABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAErrorStatusGet \ - ((unsigned long (*)(void))ROM_UDMATABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAErrorStatusClear \ - ((void (*)(void))ROM_UDMATABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelEnable \ - ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelDisable \ - ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelIsEnabled \ - ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAControlBaseSet \ - ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAControlBaseGet \ - ((void * (*)(void))ROM_UDMATABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelRequest \ - ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelAttributeEnable \ - ((void (*)(unsigned long ulChannelNum, \ - unsigned long ulAttr))ROM_UDMATABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelAttributeDisable \ - ((void (*)(unsigned long ulChannelNum, \ - unsigned long ulAttr))ROM_UDMATABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelAttributeGet \ - ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelControlSet \ - ((void (*)(unsigned long ulChannelStructIndex, \ - unsigned long ulControl))ROM_UDMATABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelSizeGet \ - ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelModeGet \ - ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAIntStatus \ - ((unsigned long (*)(void))ROM_UDMATABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAIntClear \ - ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAControlAlternateBaseGet \ - ((void * (*)(void))ROM_UDMATABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(unsigned long ulChannelNum, \ - unsigned ulTaskCount, \ - void *pvTaskList, \ - unsigned long ulIsPeriphSG))ROM_UDMATABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelAssign \ - ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAIntRegister \ - ((void (*)(unsigned long ulIntChannel, \ - void (*pfnHandler)(void)))ROM_UDMATABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAIntUnregister \ - ((void (*)(unsigned long ulIntChannel))ROM_UDMATABLE[23]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Watchdog API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogIntClear \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogRunning \ - ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogEnable \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogLock \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogUnlock \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogLockState \ - ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogReloadSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulLoadVal))ROM_WATCHDOGTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogReloadGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogValueGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - tBoolean bMasked))ROM_WATCHDOGTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogStallEnable \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogStallDisable \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogIntRegister \ - ((void (*)(unsigned long ulBase, \ - void(*pfnHandler)(void)))ROM_WATCHDOGTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the I2C API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CIntRegister \ - ((void (*)(uint32_t ui32Base, \ - void(pfnHandler)(void)))ROM_I2CTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CIntUnregister \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CTxFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CTxFIFOFlush \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CRxFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CRxFIFOFlush \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFOStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFODataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFODataPutNonBlocking \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFODataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFODataGetNonBlocking \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t *pui8Data))ROM_I2CTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterBurstLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Length))ROM_I2CTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterBurstCountGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterGlitchFilterConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveFIFOEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveFIFODisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterBusBusy \ - ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterBusy \ - ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterControl \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Cmd))ROM_I2CTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterDataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntClear \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[24]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[25]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[26]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[27]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[28]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[29]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[30]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[31]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterTimeoutSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Value))ROM_I2CTABLE[32]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveACKOverride \ - ((void (*)(uint32_t ui32Base, \ - bool bEnable))ROM_I2CTABLE[33]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveACKValueSet \ - ((void (*)(uint32_t ui32Base, \ - bool bACK))ROM_I2CTABLE[34]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterLineStateGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[35]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterSlaveAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8SlaveAddr, \ - bool bReceive))ROM_I2CTABLE[36]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveDataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[37]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[38]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[39]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveInit \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8SlaveAddr))ROM_I2CTABLE[41]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveAddressSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8AddrNum, \ - uint8_t ui8SlaveAddr))ROM_I2CTABLE[42]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntClear \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[44]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[45]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[46]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[47]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[48]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[49]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[50]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[51]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterInitExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32I2CClk, \ - bool bFast))ROM_I2CTABLE[52]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SPI API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIEnable \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDisable \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIReset \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIConfigSetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulSPIClk, \ - unsigned long ulBitRate, \ - unsigned long ulMode, \ - unsigned long ulSubMode, \ - unsigned long ulConfig))ROM_SPITABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDataGetNonBlocking \ - ((long (*)(unsigned long ulBase, \ - unsigned long * pulData))ROM_SPITABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDataGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long *pulData))ROM_SPITABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDataPutNonBlocking \ - ((long (*)(unsigned long ulBase, \ - unsigned long ulData))ROM_SPITABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDataPut \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulData))ROM_SPITABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIFIFOEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulFlags))ROM_SPITABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIFIFODisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulFlags))ROM_SPITABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIFIFOLevelSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTxLevel, \ - unsigned long ulRxLevel))ROM_SPITABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIFIFOLevelGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long *pulTxLevel, \ - unsigned long *pulRxLevel))ROM_SPITABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIWordCountSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulWordCount))ROM_SPITABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntRegister \ - ((void (*)(unsigned long ulBase, \ - void(*pfnHandler)(void)))ROM_SPITABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SPITABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SPITABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - tBoolean bMasked))ROM_SPITABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SPITABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDmaEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulFlags))ROM_SPITABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDmaDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulFlags))ROM_SPITABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPICSEnable \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPICSDisable \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPITransfer \ - ((long (*)(unsigned long ulBase, \ - unsigned char *ucDout, \ - unsigned char *ucDin, \ - unsigned long ulSize, \ - unsigned long ulFlags))ROM_SPITABLE[23]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CAM API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraReset \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraParamsConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulHSPol, \ - unsigned long ulVSPol, \ - unsigned long ulFlags))ROM_CAMERATABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraXClkConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulCamClkIn, \ - unsigned long ulXClk))ROM_CAMERATABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraXClkSet \ - ((void (*)(unsigned long ulBase, \ - unsigned char bXClkFlags))ROM_CAMERATABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraDMAEnable \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraDMADisable \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraThresholdSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulThreshold))ROM_CAMERATABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntRegister \ - ((void (*)(unsigned long ulBase, \ - void (*pfnHandler)(void)))ROM_CAMERATABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_CAMERATABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_CAMERATABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntStatus \ - ((unsigned long (*)(unsigned long ulBase))ROM_CAMERATABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_CAMERATABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraCaptureStop \ - ((void (*)(unsigned long ulBase, \ - tBoolean bImmediate))ROM_CAMERATABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraCaptureStart \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraBufferRead \ - ((void (*)(unsigned long ulBase, \ - unsigned long *pBuffer, \ - unsigned char ucSize))ROM_CAMERATABLE[15]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the FLASH API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashDisable \ - ((void (*)(void))ROM_FLASHTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashErase \ - ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashMassErase \ - ((long (*)(void))ROM_FLASHTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashMassEraseNonBlocking \ - ((void (*)(void))ROM_FLASHTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashEraseNonBlocking \ - ((void (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashProgram \ - ((long (*)(unsigned long *pulData, \ - unsigned long ulAddress, \ - unsigned long ulCount))ROM_FLASHTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashProgramNonBlocking \ - ((long (*)(unsigned long *pulData, \ - unsigned long ulAddress, \ - unsigned long ulCount))ROM_FLASHTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntRegister \ - ((void (*)(void (*pfnHandler)(void)))ROM_FLASHTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntUnregister \ - ((void (*)(void))ROM_FLASHTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntEnable \ - ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntDisable \ - ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntStatus \ - ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntClear \ - ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashProtectGet \ - ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[13]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Pin API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinModeSet \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinDirModeSet \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinIO))ROM_PINTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinDirModeGet \ - ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinModeGet \ - ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinConfigGet \ - ((void (*)(unsigned long ulPin, \ - unsigned long *pulPinStrength, \ - unsigned long *pulPinType))ROM_PINTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinConfigSet \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinStrength, \ - unsigned long ulPinType))ROM_PINTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeUART \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeI2C \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeSPI \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeI2S \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeTimer \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeCamera \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeGPIO \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode, \ - tBoolean bOpenDrain))ROM_PINTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeADC \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeSDHost \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[14]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinHysteresisSet \ - ((void (*)(unsigned long ulHysteresis))ROM_PINTABLE[15]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinLockLevelSet \ - ((void (*)(unsigned long ulPin, \ - unsigned char ucLevel))ROM_PINTABLE[16]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinLock \ - ((void (*)(unsigned long ulOutEnable))ROM_PINTABLE[17]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinUnlock \ - ((void (*)(void))ROM_PINTABLE[18]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SYSTICK API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickEnable \ - ((void (*)(void))ROM_SYSTICKTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickDisable \ - ((void (*)(void))ROM_SYSTICKTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickIntRegister \ - ((void (*)(void (*pfnHandler)(void)))ROM_SYSTICKTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickIntUnregister \ - ((void (*)(void))ROM_SYSTICKTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickIntEnable \ - ((void (*)(void))ROM_SYSTICKTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickIntDisable \ - ((void (*)(void))ROM_SYSTICKTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickPeriodSet \ - ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickPeriodGet \ - ((unsigned long (*)(void))ROM_SYSTICKTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickValueGet \ - ((unsigned long (*)(void))ROM_SYSTICKTABLE[8]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the UTILS API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UtilsDelay \ - ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the I2S API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulMode))ROM_I2STABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDisable \ - ((void (*)(unsigned long ulBase))ROM_I2STABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDataPut \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long ulData))ROM_I2STABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDataPutNonBlocking \ - ((long (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long ulData))ROM_I2STABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDataGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long *pulData))ROM_I2STABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDataGetNonBlocking \ - ((long (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long *pulData))ROM_I2STABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SConfigSetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulI2SClk, \ - unsigned long ulBitClk, \ - unsigned long ulConfig))ROM_I2STABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2STxFIFOEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTxLevel, \ - unsigned long ulWordsPerTransfer))ROM_I2STABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2STxFIFODisable \ - ((void (*)(unsigned long ulBase))ROM_I2STABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SRxFIFOEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulRxLevel, \ - unsigned long ulWordsPerTransfer))ROM_I2STABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SRxFIFODisable \ - ((void (*)(unsigned long ulBase))ROM_I2STABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2STxFIFOStatusGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SRxFIFOStatusGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SSerializerConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long ulSerMode, \ - unsigned long ulInActState))ROM_I2STABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_I2STABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_I2STABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntStatus \ - ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_I2STABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntRegister \ - ((void (*)(unsigned long ulBase, \ - void (*pfnHandler)(void)))ROM_I2STABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_I2STABLE[19]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2STxActiveSlotSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulActSlot))ROM_I2STABLE[20]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SRxActiveSlotSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulActSlot))ROM_I2STABLE[21]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the GPIO API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIODirModeSet \ - ((void (*)(unsigned long ulPort, \ - unsigned char ucPins, \ - unsigned long ulPinIO))ROM_GPIOTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIODirModeGet \ - ((unsigned long (*)(unsigned long ulPort, \ - unsigned char ucPin))ROM_GPIOTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntTypeSet \ - ((void (*)(unsigned long ulPort, \ - unsigned char ucPins, \ - unsigned long ulIntType))ROM_GPIOTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIODMATriggerEnable \ - ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIODMATriggerDisable \ - ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntTypeGet \ - ((unsigned long (*)(unsigned long ulPort, \ - unsigned char ucPin))ROM_GPIOTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntEnable \ - ((void (*)(unsigned long ulPort, \ - unsigned long ulIntFlags))ROM_GPIOTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntDisable \ - ((void (*)(unsigned long ulPort, \ - unsigned long ulIntFlags))ROM_GPIOTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntStatus \ - ((long (*)(unsigned long ulPort, \ - tBoolean bMasked))ROM_GPIOTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntClear \ - ((void (*)(unsigned long ulPort, \ - unsigned long ulIntFlags))ROM_GPIOTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntRegister \ - ((void (*)(unsigned long ulPort, \ - void (*pfnIntHandler)(void)))ROM_GPIOTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntUnregister \ - ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOPinRead \ - ((long (*)(unsigned long ulPort, \ - unsigned char ucPins))ROM_GPIOTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOPinWrite \ - ((void (*)(unsigned long ulPort, \ - unsigned char ucPins, \ - unsigned char ucVal))ROM_GPIOTABLE[13]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the AES API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_AESTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESKey1Set \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key, \ - uint32_t ui32Keysize))ROM_AESTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESKey2Set \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key, \ - uint32_t ui32Keysize))ROM_AESTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESKey3Set \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key))ROM_AESTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIVSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8IVdata))ROM_AESTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESTagRead \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8TagData))ROM_AESTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint64_t ui64Length))ROM_AESTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESAuthDataLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_AESTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataReadNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest, \ - uint8_t ui8Length))ROM_AESTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataRead \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest, \ - uint8_t ui8Length))ROM_AESTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t ui8Length))ROM_AESTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t ui8Length))ROM_AESTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t *pui8Dest, \ - uint32_t ui32Length))ROM_AESTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataMAC \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint32_t ui32Length, \ - uint8_t *pui8Tag))ROM_AESTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataProcessAE \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t *pui8Dest, \ - uint32_t ui32Length, \ - uint8_t *pui8AuthSrc, \ - uint32_t ui32AuthLength, \ - uint8_t *pui8Tag))ROM_AESTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_AESTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntRegister \ - ((void (*)(uint32_t ui32Base, \ - void(*pfnHandler)(void)))ROM_AESTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntUnregister \ - ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_AESTABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_AESTABLE[22]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIVGet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8IVdata))ROM_AESTABLE[23]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the DES API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_DESTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataRead \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest, \ - uint8_t ui8Length))ROM_DESTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataReadNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest, \ - uint8_t ui8Length))ROM_DESTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t *pui8Dest, \ - uint32_t ui32Length))ROM_DESTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t ui8Length))ROM_DESTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t ui8Length))ROM_DESTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_DESTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_DESTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntRegister \ - ((void (*)(uint32_t ui32Base, \ - void(*pfnHandler)(void)))ROM_DESTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_DESTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntUnregister \ - ((void (*)(uint32_t ui32Base))ROM_DESTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIVSet \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8IVdata))ROM_DESTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key))ROM_DESTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_DESTABLE[16]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SHAMD5 API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5ConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_SHAMD5TABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8DataSrc, \ - uint32_t ui32DataLength, \ - uint8_t *pui8HashResult))ROM_SHAMD5TABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src))ROM_SHAMD5TABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src))ROM_SHAMD5TABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DMADisable \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DMAEnable \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DataLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_SHAMD5TABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5HMACKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src))ROM_SHAMD5TABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5HMACPPKeyGenerate \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key, \ - uint8_t *pui8PPKey))ROM_SHAMD5TABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5HMACPPKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src))ROM_SHAMD5TABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5HMACProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8DataSrc, \ - uint32_t ui32DataLength, \ - uint8_t *pui8HashResult))ROM_SHAMD5TABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntRegister \ - ((void (*)(uint32_t ui32Base, \ - void(*pfnHandler)(void)))ROM_SHAMD5TABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_SHAMD5TABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntUnregister \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5ResultRead \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest))ROM_SHAMD5TABLE[17]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CRC API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCDataProcess \ - ((uint32_t (*)(uint32_t ui32Base, \ - void *puiDataIn, \ - uint32_t ui32DataLength, \ - uint32_t ui32Config))ROM_CRCTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_CRCTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCResultRead \ - ((uint32_t (*)(uint32_t ui32Base))ROM_CRCTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCSeedSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seed))ROM_CRCTABLE[4]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SDHOST API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostCmdReset \ - ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostInit \ - ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostCmdSend \ - ((long (*)(unsigned long ulBase, \ - unsigned long ulCmd, \ - unsigned ulArg))ROM_SDHOSTTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntRegister \ - ((void (*)(unsigned long ulBase, \ - void (*pfnHandler)(void)))ROM_SDHOSTTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SDHOSTTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SDHOSTTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntStatus \ - ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SDHOSTTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostRespGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulRespnse[4]))ROM_SDHOSTTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostBlockSizeSet \ - ((void (*)(unsigned long ulBase, \ - unsigned short ulBlkSize))ROM_SDHOSTTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostBlockCountSet \ - ((void (*)(unsigned long ulBase, \ - unsigned short ulBlkCount))ROM_SDHOSTTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostDataNonBlockingWrite \ - ((tBoolean (*)(unsigned long ulBase, \ - unsigned long ulData))ROM_SDHOSTTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostDataNonBlockingRead \ - ((tBoolean (*)(unsigned long ulBase, \ - unsigned long *pulData))ROM_SDHOSTTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostDataWrite \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulData))ROM_SDHOSTTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostDataRead \ - ((void (*)(unsigned long ulBase, \ - unsigned long *ulData))ROM_SDHOSTTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostSetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulSDHostClk, \ - unsigned long ulCardClk))ROM_SDHOSTTABLE[17]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostCardErrorMaskSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulErrMask))ROM_SDHOSTTABLE[18]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostCardErrorMaskGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[19]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the PRCM API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMMCUReset \ - ((void (*)(tBoolean bIncludeSubsystem))ROM_PRCMTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSysResetCauseGet \ - ((unsigned long (*)(void))ROM_PRCMTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralClkEnable \ - ((void (*)(unsigned long ulPeripheral, \ - unsigned long ulClkFlags))ROM_PRCMTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralClkDisable \ - ((void (*)(unsigned long ulPeripheral, \ - unsigned long ulClkFlags))ROM_PRCMTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralReset \ - ((void (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralStatusGet \ - ((tBoolean (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMI2SClockFreqSet \ - ((void (*)(unsigned long ulI2CClkFreq))ROM_PRCMTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralClockGet \ - ((unsigned long (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSleepEnter \ - ((void (*)(void))ROM_PRCMTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSRAMRetentionEnable \ - ((void (*)(unsigned long ulSramColSel, \ - unsigned long ulFlags))ROM_PRCMTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSRAMRetentionDisable \ - ((void (*)(unsigned long ulSramColSel, \ - unsigned long ulFlags))ROM_PRCMTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSEnter \ - ((void (*)(void))ROM_PRCMTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSIntervalSet \ - ((void (*)(unsigned long ulTicks))ROM_PRCMTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSWakeupSourceEnable \ - ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSWakeupCauseGet \ - ((unsigned long (*)(void))ROM_PRCMTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSWakeUpGPIOSelect \ - ((void (*)(unsigned long ulGPIOPin, \ - unsigned long ulType))ROM_PRCMTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSWakeupSourceDisable \ - ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateEnter \ - ((void (*)(void))ROM_PRCMTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateWakeupSourceEnable \ - ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateWakeupCauseGet \ - ((unsigned long (*)(void))ROM_PRCMTABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateWakeUpGPIOSelect \ - ((void (*)(unsigned long ulMultiGPIOBitMap, \ - unsigned long ulType))ROM_PRCMTABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateWakeupSourceDisable \ - ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[23]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateIntervalSet \ - ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[24]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSlowClkCtrGet \ - ((unsigned long long (*)(void))ROM_PRCMTABLE[25]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSlowClkCtrMatchSet \ - ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[26]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSlowClkCtrMatchGet \ - ((unsigned long long (*)(void))ROM_PRCMTABLE[27]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMOCRRegisterWrite \ - ((void (*)(unsigned char ucIndex, \ - unsigned long ulRegValue))ROM_PRCMTABLE[28]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMOCRRegisterRead \ - ((unsigned long (*)(unsigned char ucIndex))ROM_PRCMTABLE[29]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntRegister \ - ((void (*)(void (*pfnHandler)(void)))ROM_PRCMTABLE[30]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntUnregister \ - ((void (*)(void))ROM_PRCMTABLE[31]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntEnable \ - ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[32]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntDisable \ - ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[33]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntStatus \ - ((unsigned long (*)(void))ROM_PRCMTABLE[34]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCInUseSet \ - ((void (*)(void))ROM_PRCMTABLE[35]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCInUseGet \ - ((tBoolean (*)(void))ROM_PRCMTABLE[36]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCSet \ - ((void (*)(unsigned long ulSecs, \ - unsigned short usMsec))ROM_PRCMTABLE[37]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCGet \ - ((void (*)(unsigned long *ulSecs, \ - unsigned short *usMsec))ROM_PRCMTABLE[38]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCMatchSet \ - ((void (*)(unsigned long ulSecs, \ - unsigned short usMsec))ROM_PRCMTABLE[39]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCMatchGet \ - ((void (*)(unsigned long *ulSecs, \ - unsigned short *usMsec))ROM_PRCMTABLE[40]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSRestoreInfoSet \ - ((void (*)(unsigned long ulRestoreSP, \ - unsigned long ulRestorePC))ROM_PRCMTABLE[41]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSlowClkCtrFastGet \ - ((unsigned long long (*)(void))ROM_PRCMTABLE[42]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMCC3200MCUInit \ - ((void (*)(void))ROM_PRCMTABLE[43]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHIBRegRead \ - ((unsigned long (*)(unsigned long ulRegAddr))ROM_PRCMTABLE[44]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHIBRegWrite \ - ((void (*)(unsigned long ulRegAddr, \ - unsigned long ulValue))ROM_PRCMTABLE[45]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMCameraFreqSet \ - ((unsigned long (*)(unsigned char ulDivider, \ - unsigned char ulWidth))ROM_PRCMTABLE[46]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIORetentionEnable \ - ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[47]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIORetentionDisable \ - ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[48]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMDeviceTypeGet \ - ((unsigned long (*)(void))ROM_PRCMTABLE[49]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSEnterKeepDebugIf \ - ((void (*)(void))ROM_PRCMTABLE[50]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateCycleTrigger \ - ((void (*)(void))ROM_PRCMTABLE[51]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the HWSPINLOCK API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_HwSpinLockAcquire \ - ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_HwSpinLockTryAcquire \ - ((int32_t (*)(uint32_t ui32LockID, \ - uint32_t ui32Retry))ROM_HWSPINLOCKTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_HwSpinLockRelease \ - ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_HwSpinLockTest \ - ((uint32_t (*)(uint32_t ui32LockID, \ - bool bCurrentStatus))ROM_HWSPINLOCKTABLE[3]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the ADC API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCEnable \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCDisable \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCChannelEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCChannelDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntRegister \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel, \ - void (*pfnHandler)(void)))ROM_ADCTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntUnregister \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel, \ - unsigned long ulIntFlags))ROM_ADCTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel, \ - unsigned long ulIntFlags))ROM_ADCTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel, \ - unsigned long ulIntFlags))ROM_ADCTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCDMAEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCDMADisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulValue))ROM_ADCTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerEnable \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerDisable \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerReset \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerValueGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCFIFOLvlGet \ - ((unsigned char (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCFIFORead \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[20]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CPU API. -// -//***************************************************************************** -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUcpsid \ - ((unsigned long (*)(void))ROM_CPUTABLE[0]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUcpsie \ - ((unsigned long (*)(void))ROM_CPUTABLE[1]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUprimask \ - ((unsigned long (*)(void))ROM_CPUTABLE[2]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUwfi \ - ((void (*)(void))ROM_CPUTABLE[3]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUbasepriGet \ - ((unsigned long (*)(void))ROM_CPUTABLE[4]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUbasepriSet \ - ((void (*)(unsigned long ulNewBasepri))ROM_CPUTABLE[5]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions Directly. -// -//***************************************************************************** -#define ROM_UtilsDelayDirect \ - ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0]) - -#define ROM_PRCMLPDSEnterDirect \ - ((void (*)(void))ROM_PRCMTABLE[13]) - -#define ROM_PRCMLPDSEnterKeepDebugIfDirect \ - ((void (*)(void))ROM_PRCMTABLE[50]) - -#endif // __ROM_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_map.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_map.h deleted file mode 100755 index cb2e07e1fc5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_map.h +++ /dev/null @@ -1,3321 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// rom_map.h - Macros to facilitate calling functions in the ROM when they are -// available. -// -//***************************************************************************** -//***************************************************************************** -// -// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND. -// -//***************************************************************************** - -#ifndef __ROM_MAP_H__ -#define __ROM_MAP_H__ - -//***************************************************************************** -// Patched ROM APIs -//***************************************************************************** -#include "rom_patch.h" - -//***************************************************************************** -// -// Macros for the Interrupt API. -// -//***************************************************************************** -#ifdef ROM_IntEnable -#define MAP_IntEnable \ - ROM_IntEnable -#else -#define MAP_IntEnable \ - IntEnable -#endif -#ifdef ROM_IntMasterEnable -#define MAP_IntMasterEnable \ - ROM_IntMasterEnable -#else -#define MAP_IntMasterEnable \ - IntMasterEnable -#endif -#ifdef ROM_IntMasterDisable -#define MAP_IntMasterDisable \ - ROM_IntMasterDisable -#else -#define MAP_IntMasterDisable \ - IntMasterDisable -#endif -#ifdef ROM_IntDisable -#define MAP_IntDisable \ - ROM_IntDisable -#else -#define MAP_IntDisable \ - IntDisable -#endif -#ifdef ROM_IntPriorityGroupingSet -#define MAP_IntPriorityGroupingSet \ - ROM_IntPriorityGroupingSet -#else -#define MAP_IntPriorityGroupingSet \ - IntPriorityGroupingSet -#endif -#ifdef ROM_IntPriorityGroupingGet -#define MAP_IntPriorityGroupingGet \ - ROM_IntPriorityGroupingGet -#else -#define MAP_IntPriorityGroupingGet \ - IntPriorityGroupingGet -#endif -#ifdef ROM_IntPrioritySet -#define MAP_IntPrioritySet \ - ROM_IntPrioritySet -#else -#define MAP_IntPrioritySet \ - IntPrioritySet -#endif -#ifdef ROM_IntPriorityGet -#define MAP_IntPriorityGet \ - ROM_IntPriorityGet -#else -#define MAP_IntPriorityGet \ - IntPriorityGet -#endif -#ifdef ROM_IntPendSet -#define MAP_IntPendSet \ - ROM_IntPendSet -#else -#define MAP_IntPendSet \ - IntPendSet -#endif -#ifdef ROM_IntPendClear -#define MAP_IntPendClear \ - ROM_IntPendClear -#else -#define MAP_IntPendClear \ - IntPendClear -#endif -#ifdef ROM_IntPriorityMaskSet -#define MAP_IntPriorityMaskSet \ - ROM_IntPriorityMaskSet -#else -#define MAP_IntPriorityMaskSet \ - IntPriorityMaskSet -#endif -#ifdef ROM_IntPriorityMaskGet -#define MAP_IntPriorityMaskGet \ - ROM_IntPriorityMaskGet -#else -#define MAP_IntPriorityMaskGet \ - IntPriorityMaskGet -#endif -#ifdef ROM_IntRegister -#define MAP_IntRegister \ - ROM_IntRegister -#else -#define MAP_IntRegister \ - IntRegister -#endif -#ifdef ROM_IntUnregister -#define MAP_IntUnregister \ - ROM_IntUnregister -#else -#define MAP_IntUnregister \ - IntUnregister -#endif -#ifdef ROM_IntVTableBaseSet -#define MAP_IntVTableBaseSet \ - ROM_IntVTableBaseSet -#else -#define MAP_IntVTableBaseSet \ - IntVTableBaseSet -#endif - -//***************************************************************************** -// -// Macros for the Timer API. -// -//***************************************************************************** -#ifdef ROM_TimerEnable -#define MAP_TimerEnable \ - ROM_TimerEnable -#else -#define MAP_TimerEnable \ - TimerEnable -#endif -#ifdef ROM_TimerDisable -#define MAP_TimerDisable \ - ROM_TimerDisable -#else -#define MAP_TimerDisable \ - TimerDisable -#endif -#ifdef ROM_TimerConfigure -#define MAP_TimerConfigure \ - ROM_TimerConfigure -#else -#define MAP_TimerConfigure \ - TimerConfigure -#endif -#ifdef ROM_TimerControlLevel -#define MAP_TimerControlLevel \ - ROM_TimerControlLevel -#else -#define MAP_TimerControlLevel \ - TimerControlLevel -#endif -#ifdef ROM_TimerControlEvent -#define MAP_TimerControlEvent \ - ROM_TimerControlEvent -#else -#define MAP_TimerControlEvent \ - TimerControlEvent -#endif -#ifdef ROM_TimerControlStall -#define MAP_TimerControlStall \ - ROM_TimerControlStall -#else -#define MAP_TimerControlStall \ - TimerControlStall -#endif -#ifdef ROM_TimerPrescaleSet -#define MAP_TimerPrescaleSet \ - ROM_TimerPrescaleSet -#else -#define MAP_TimerPrescaleSet \ - TimerPrescaleSet -#endif -#ifdef ROM_TimerPrescaleGet -#define MAP_TimerPrescaleGet \ - ROM_TimerPrescaleGet -#else -#define MAP_TimerPrescaleGet \ - TimerPrescaleGet -#endif -#ifdef ROM_TimerPrescaleMatchSet -#define MAP_TimerPrescaleMatchSet \ - ROM_TimerPrescaleMatchSet -#else -#define MAP_TimerPrescaleMatchSet \ - TimerPrescaleMatchSet -#endif -#ifdef ROM_TimerPrescaleMatchGet -#define MAP_TimerPrescaleMatchGet \ - ROM_TimerPrescaleMatchGet -#else -#define MAP_TimerPrescaleMatchGet \ - TimerPrescaleMatchGet -#endif -#ifdef ROM_TimerLoadSet -#define MAP_TimerLoadSet \ - ROM_TimerLoadSet -#else -#define MAP_TimerLoadSet \ - TimerLoadSet -#endif -#ifdef ROM_TimerLoadGet -#define MAP_TimerLoadGet \ - ROM_TimerLoadGet -#else -#define MAP_TimerLoadGet \ - TimerLoadGet -#endif -#ifdef ROM_TimerValueGet -#define MAP_TimerValueGet \ - ROM_TimerValueGet -#else -#define MAP_TimerValueGet \ - TimerValueGet -#endif -#ifdef ROM_TimerMatchSet -#define MAP_TimerMatchSet \ - ROM_TimerMatchSet -#else -#define MAP_TimerMatchSet \ - TimerMatchSet -#endif -#ifdef ROM_TimerMatchGet -#define MAP_TimerMatchGet \ - ROM_TimerMatchGet -#else -#define MAP_TimerMatchGet \ - TimerMatchGet -#endif -#ifdef ROM_TimerIntRegister -#define MAP_TimerIntRegister \ - ROM_TimerIntRegister -#else -#define MAP_TimerIntRegister \ - TimerIntRegister -#endif -#ifdef ROM_TimerIntUnregister -#define MAP_TimerIntUnregister \ - ROM_TimerIntUnregister -#else -#define MAP_TimerIntUnregister \ - TimerIntUnregister -#endif -#ifdef ROM_TimerIntEnable -#define MAP_TimerIntEnable \ - ROM_TimerIntEnable -#else -#define MAP_TimerIntEnable \ - TimerIntEnable -#endif -#ifdef ROM_TimerIntDisable -#define MAP_TimerIntDisable \ - ROM_TimerIntDisable -#else -#define MAP_TimerIntDisable \ - TimerIntDisable -#endif -#ifdef ROM_TimerIntStatus -#define MAP_TimerIntStatus \ - ROM_TimerIntStatus -#else -#define MAP_TimerIntStatus \ - TimerIntStatus -#endif -#ifdef ROM_TimerIntClear -#define MAP_TimerIntClear \ - ROM_TimerIntClear -#else -#define MAP_TimerIntClear \ - TimerIntClear -#endif -#ifdef ROM_TimerValueSet -#define MAP_TimerValueSet \ - ROM_TimerValueSet -#else -#define MAP_TimerValueSet \ - TimerValueSet -#endif -#ifdef ROM_TimerDMAEventSet -#define MAP_TimerDMAEventSet \ - ROM_TimerDMAEventSet -#else -#define MAP_TimerDMAEventSet \ - TimerDMAEventSet -#endif -#ifdef ROM_TimerDMAEventGet -#define MAP_TimerDMAEventGet \ - ROM_TimerDMAEventGet -#else -#define MAP_TimerDMAEventGet \ - TimerDMAEventGet -#endif - -//***************************************************************************** -// -// Macros for the UART API. -// -//***************************************************************************** -#ifdef ROM_UARTParityModeSet -#define MAP_UARTParityModeSet \ - ROM_UARTParityModeSet -#else -#define MAP_UARTParityModeSet \ - UARTParityModeSet -#endif -#ifdef ROM_UARTParityModeGet -#define MAP_UARTParityModeGet \ - ROM_UARTParityModeGet -#else -#define MAP_UARTParityModeGet \ - UARTParityModeGet -#endif -#ifdef ROM_UARTFIFOLevelSet -#define MAP_UARTFIFOLevelSet \ - ROM_UARTFIFOLevelSet -#else -#define MAP_UARTFIFOLevelSet \ - UARTFIFOLevelSet -#endif -#ifdef ROM_UARTFIFOLevelGet -#define MAP_UARTFIFOLevelGet \ - ROM_UARTFIFOLevelGet -#else -#define MAP_UARTFIFOLevelGet \ - UARTFIFOLevelGet -#endif -#ifdef ROM_UARTConfigSetExpClk -#define MAP_UARTConfigSetExpClk \ - ROM_UARTConfigSetExpClk -#else -#define MAP_UARTConfigSetExpClk \ - UARTConfigSetExpClk -#endif -#ifdef ROM_UARTConfigGetExpClk -#define MAP_UARTConfigGetExpClk \ - ROM_UARTConfigGetExpClk -#else -#define MAP_UARTConfigGetExpClk \ - UARTConfigGetExpClk -#endif -#ifdef ROM_UARTEnable -#define MAP_UARTEnable \ - ROM_UARTEnable -#else -#define MAP_UARTEnable \ - UARTEnable -#endif -#ifdef ROM_UARTDisable -#define MAP_UARTDisable \ - ROM_UARTDisable -#else -#define MAP_UARTDisable \ - UARTDisable -#endif -#ifdef ROM_UARTFIFOEnable -#define MAP_UARTFIFOEnable \ - ROM_UARTFIFOEnable -#else -#define MAP_UARTFIFOEnable \ - UARTFIFOEnable -#endif -#ifdef ROM_UARTFIFODisable -#define MAP_UARTFIFODisable \ - ROM_UARTFIFODisable -#else -#define MAP_UARTFIFODisable \ - UARTFIFODisable -#endif -#ifdef ROM_UARTCharsAvail -#define MAP_UARTCharsAvail \ - ROM_UARTCharsAvail -#else -#define MAP_UARTCharsAvail \ - UARTCharsAvail -#endif -#ifdef ROM_UARTSpaceAvail -#define MAP_UARTSpaceAvail \ - ROM_UARTSpaceAvail -#else -#define MAP_UARTSpaceAvail \ - UARTSpaceAvail -#endif -#ifdef ROM_UARTCharGetNonBlocking -#define MAP_UARTCharGetNonBlocking \ - ROM_UARTCharGetNonBlocking -#else -#define MAP_UARTCharGetNonBlocking \ - UARTCharGetNonBlocking -#endif -#ifdef ROM_UARTCharGet -#define MAP_UARTCharGet \ - ROM_UARTCharGet -#else -#define MAP_UARTCharGet \ - UARTCharGet -#endif -#ifdef ROM_UARTCharPutNonBlocking -#define MAP_UARTCharPutNonBlocking \ - ROM_UARTCharPutNonBlocking -#else -#define MAP_UARTCharPutNonBlocking \ - UARTCharPutNonBlocking -#endif -#ifdef ROM_UARTCharPut -#define MAP_UARTCharPut \ - ROM_UARTCharPut -#else -#define MAP_UARTCharPut \ - UARTCharPut -#endif -#ifdef ROM_UARTBreakCtl -#define MAP_UARTBreakCtl \ - ROM_UARTBreakCtl -#else -#define MAP_UARTBreakCtl \ - UARTBreakCtl -#endif -#ifdef ROM_UARTBusy -#define MAP_UARTBusy \ - ROM_UARTBusy -#else -#define MAP_UARTBusy \ - UARTBusy -#endif -#ifdef ROM_UARTIntRegister -#define MAP_UARTIntRegister \ - ROM_UARTIntRegister -#else -#define MAP_UARTIntRegister \ - UARTIntRegister -#endif -#ifdef ROM_UARTIntUnregister -#define MAP_UARTIntUnregister \ - ROM_UARTIntUnregister -#else -#define MAP_UARTIntUnregister \ - UARTIntUnregister -#endif -#ifdef ROM_UARTIntEnable -#define MAP_UARTIntEnable \ - ROM_UARTIntEnable -#else -#define MAP_UARTIntEnable \ - UARTIntEnable -#endif -#ifdef ROM_UARTIntDisable -#define MAP_UARTIntDisable \ - ROM_UARTIntDisable -#else -#define MAP_UARTIntDisable \ - UARTIntDisable -#endif -#ifdef ROM_UARTIntStatus -#define MAP_UARTIntStatus \ - ROM_UARTIntStatus -#else -#define MAP_UARTIntStatus \ - UARTIntStatus -#endif -#ifdef ROM_UARTIntClear -#define MAP_UARTIntClear \ - ROM_UARTIntClear -#else -#define MAP_UARTIntClear \ - UARTIntClear -#endif -#ifdef ROM_UARTDMAEnable -#define MAP_UARTDMAEnable \ - ROM_UARTDMAEnable -#else -#define MAP_UARTDMAEnable \ - UARTDMAEnable -#endif -#ifdef ROM_UARTDMADisable -#define MAP_UARTDMADisable \ - ROM_UARTDMADisable -#else -#define MAP_UARTDMADisable \ - UARTDMADisable -#endif -#ifdef ROM_UARTRxErrorGet -#define MAP_UARTRxErrorGet \ - ROM_UARTRxErrorGet -#else -#define MAP_UARTRxErrorGet \ - UARTRxErrorGet -#endif -#ifdef ROM_UARTRxErrorClear -#define MAP_UARTRxErrorClear \ - ROM_UARTRxErrorClear -#else -#define MAP_UARTRxErrorClear \ - UARTRxErrorClear -#endif -#ifdef ROM_UARTModemControlSet -#define MAP_UARTModemControlSet \ - ROM_UARTModemControlSet -#else -#define MAP_UARTModemControlSet \ - UARTModemControlSet -#endif -#ifdef ROM_UARTModemControlClear -#define MAP_UARTModemControlClear \ - ROM_UARTModemControlClear -#else -#define MAP_UARTModemControlClear \ - UARTModemControlClear -#endif -#ifdef ROM_UARTModemControlGet -#define MAP_UARTModemControlGet \ - ROM_UARTModemControlGet -#else -#define MAP_UARTModemControlGet \ - UARTModemControlGet -#endif -#ifdef ROM_UARTModemStatusGet -#define MAP_UARTModemStatusGet \ - ROM_UARTModemStatusGet -#else -#define MAP_UARTModemStatusGet \ - UARTModemStatusGet -#endif -#ifdef ROM_UARTFlowControlSet -#define MAP_UARTFlowControlSet \ - ROM_UARTFlowControlSet -#else -#define MAP_UARTFlowControlSet \ - UARTFlowControlSet -#endif -#ifdef ROM_UARTFlowControlGet -#define MAP_UARTFlowControlGet \ - ROM_UARTFlowControlGet -#else -#define MAP_UARTFlowControlGet \ - UARTFlowControlGet -#endif -#ifdef ROM_UARTTxIntModeSet -#define MAP_UARTTxIntModeSet \ - ROM_UARTTxIntModeSet -#else -#define MAP_UARTTxIntModeSet \ - UARTTxIntModeSet -#endif -#ifdef ROM_UARTTxIntModeGet -#define MAP_UARTTxIntModeGet \ - ROM_UARTTxIntModeGet -#else -#define MAP_UARTTxIntModeGet \ - UARTTxIntModeGet -#endif - -//***************************************************************************** -// -// Macros for the uDMA API. -// -//***************************************************************************** -#ifdef ROM_uDMAChannelTransferSet -#define MAP_uDMAChannelTransferSet \ - ROM_uDMAChannelTransferSet -#else -#define MAP_uDMAChannelTransferSet \ - uDMAChannelTransferSet -#endif -#ifdef ROM_uDMAEnable -#define MAP_uDMAEnable \ - ROM_uDMAEnable -#else -#define MAP_uDMAEnable \ - uDMAEnable -#endif -#ifdef ROM_uDMADisable -#define MAP_uDMADisable \ - ROM_uDMADisable -#else -#define MAP_uDMADisable \ - uDMADisable -#endif -#ifdef ROM_uDMAErrorStatusGet -#define MAP_uDMAErrorStatusGet \ - ROM_uDMAErrorStatusGet -#else -#define MAP_uDMAErrorStatusGet \ - uDMAErrorStatusGet -#endif -#ifdef ROM_uDMAErrorStatusClear -#define MAP_uDMAErrorStatusClear \ - ROM_uDMAErrorStatusClear -#else -#define MAP_uDMAErrorStatusClear \ - uDMAErrorStatusClear -#endif -#ifdef ROM_uDMAChannelEnable -#define MAP_uDMAChannelEnable \ - ROM_uDMAChannelEnable -#else -#define MAP_uDMAChannelEnable \ - uDMAChannelEnable -#endif -#ifdef ROM_uDMAChannelDisable -#define MAP_uDMAChannelDisable \ - ROM_uDMAChannelDisable -#else -#define MAP_uDMAChannelDisable \ - uDMAChannelDisable -#endif -#ifdef ROM_uDMAChannelIsEnabled -#define MAP_uDMAChannelIsEnabled \ - ROM_uDMAChannelIsEnabled -#else -#define MAP_uDMAChannelIsEnabled \ - uDMAChannelIsEnabled -#endif -#ifdef ROM_uDMAControlBaseSet -#define MAP_uDMAControlBaseSet \ - ROM_uDMAControlBaseSet -#else -#define MAP_uDMAControlBaseSet \ - uDMAControlBaseSet -#endif -#ifdef ROM_uDMAControlBaseGet -#define MAP_uDMAControlBaseGet \ - ROM_uDMAControlBaseGet -#else -#define MAP_uDMAControlBaseGet \ - uDMAControlBaseGet -#endif -#ifdef ROM_uDMAChannelRequest -#define MAP_uDMAChannelRequest \ - ROM_uDMAChannelRequest -#else -#define MAP_uDMAChannelRequest \ - uDMAChannelRequest -#endif -#ifdef ROM_uDMAChannelAttributeEnable -#define MAP_uDMAChannelAttributeEnable \ - ROM_uDMAChannelAttributeEnable -#else -#define MAP_uDMAChannelAttributeEnable \ - uDMAChannelAttributeEnable -#endif -#ifdef ROM_uDMAChannelAttributeDisable -#define MAP_uDMAChannelAttributeDisable \ - ROM_uDMAChannelAttributeDisable -#else -#define MAP_uDMAChannelAttributeDisable \ - uDMAChannelAttributeDisable -#endif -#ifdef ROM_uDMAChannelAttributeGet -#define MAP_uDMAChannelAttributeGet \ - ROM_uDMAChannelAttributeGet -#else -#define MAP_uDMAChannelAttributeGet \ - uDMAChannelAttributeGet -#endif -#ifdef ROM_uDMAChannelControlSet -#define MAP_uDMAChannelControlSet \ - ROM_uDMAChannelControlSet -#else -#define MAP_uDMAChannelControlSet \ - uDMAChannelControlSet -#endif -#ifdef ROM_uDMAChannelSizeGet -#define MAP_uDMAChannelSizeGet \ - ROM_uDMAChannelSizeGet -#else -#define MAP_uDMAChannelSizeGet \ - uDMAChannelSizeGet -#endif -#ifdef ROM_uDMAChannelModeGet -#define MAP_uDMAChannelModeGet \ - ROM_uDMAChannelModeGet -#else -#define MAP_uDMAChannelModeGet \ - uDMAChannelModeGet -#endif -#ifdef ROM_uDMAIntStatus -#define MAP_uDMAIntStatus \ - ROM_uDMAIntStatus -#else -#define MAP_uDMAIntStatus \ - uDMAIntStatus -#endif -#ifdef ROM_uDMAIntClear -#define MAP_uDMAIntClear \ - ROM_uDMAIntClear -#else -#define MAP_uDMAIntClear \ - uDMAIntClear -#endif -#ifdef ROM_uDMAControlAlternateBaseGet -#define MAP_uDMAControlAlternateBaseGet \ - ROM_uDMAControlAlternateBaseGet -#else -#define MAP_uDMAControlAlternateBaseGet \ - uDMAControlAlternateBaseGet -#endif -#ifdef ROM_uDMAChannelScatterGatherSet -#define MAP_uDMAChannelScatterGatherSet \ - ROM_uDMAChannelScatterGatherSet -#else -#define MAP_uDMAChannelScatterGatherSet \ - uDMAChannelScatterGatherSet -#endif -#ifdef ROM_uDMAChannelAssign -#define MAP_uDMAChannelAssign \ - ROM_uDMAChannelAssign -#else -#define MAP_uDMAChannelAssign \ - uDMAChannelAssign -#endif -#ifdef ROM_uDMAIntRegister -#define MAP_uDMAIntRegister \ - ROM_uDMAIntRegister -#else -#define MAP_uDMAIntRegister \ - uDMAIntRegister -#endif -#ifdef ROM_uDMAIntUnregister -#define MAP_uDMAIntUnregister \ - ROM_uDMAIntUnregister -#else -#define MAP_uDMAIntUnregister \ - uDMAIntUnregister -#endif - -//***************************************************************************** -// -// Macros for the Watchdog API. -// -//***************************************************************************** -#ifdef ROM_WatchdogIntClear -#define MAP_WatchdogIntClear \ - ROM_WatchdogIntClear -#else -#define MAP_WatchdogIntClear \ - WatchdogIntClear -#endif -#ifdef ROM_WatchdogRunning -#define MAP_WatchdogRunning \ - ROM_WatchdogRunning -#else -#define MAP_WatchdogRunning \ - WatchdogRunning -#endif -#ifdef ROM_WatchdogEnable -#define MAP_WatchdogEnable \ - ROM_WatchdogEnable -#else -#define MAP_WatchdogEnable \ - WatchdogEnable -#endif -#ifdef ROM_WatchdogLock -#define MAP_WatchdogLock \ - ROM_WatchdogLock -#else -#define MAP_WatchdogLock \ - WatchdogLock -#endif -#ifdef ROM_WatchdogUnlock -#define MAP_WatchdogUnlock \ - ROM_WatchdogUnlock -#else -#define MAP_WatchdogUnlock \ - WatchdogUnlock -#endif -#ifdef ROM_WatchdogLockState -#define MAP_WatchdogLockState \ - ROM_WatchdogLockState -#else -#define MAP_WatchdogLockState \ - WatchdogLockState -#endif -#ifdef ROM_WatchdogReloadSet -#define MAP_WatchdogReloadSet \ - ROM_WatchdogReloadSet -#else -#define MAP_WatchdogReloadSet \ - WatchdogReloadSet -#endif -#ifdef ROM_WatchdogReloadGet -#define MAP_WatchdogReloadGet \ - ROM_WatchdogReloadGet -#else -#define MAP_WatchdogReloadGet \ - WatchdogReloadGet -#endif -#ifdef ROM_WatchdogValueGet -#define MAP_WatchdogValueGet \ - ROM_WatchdogValueGet -#else -#define MAP_WatchdogValueGet \ - WatchdogValueGet -#endif -#ifdef ROM_WatchdogIntStatus -#define MAP_WatchdogIntStatus \ - ROM_WatchdogIntStatus -#else -#define MAP_WatchdogIntStatus \ - WatchdogIntStatus -#endif -#ifdef ROM_WatchdogStallEnable -#define MAP_WatchdogStallEnable \ - ROM_WatchdogStallEnable -#else -#define MAP_WatchdogStallEnable \ - WatchdogStallEnable -#endif -#ifdef ROM_WatchdogStallDisable -#define MAP_WatchdogStallDisable \ - ROM_WatchdogStallDisable -#else -#define MAP_WatchdogStallDisable \ - WatchdogStallDisable -#endif -#ifdef ROM_WatchdogIntRegister -#define MAP_WatchdogIntRegister \ - ROM_WatchdogIntRegister -#else -#define MAP_WatchdogIntRegister \ - WatchdogIntRegister -#endif -#ifdef ROM_WatchdogIntUnregister -#define MAP_WatchdogIntUnregister \ - ROM_WatchdogIntUnregister -#else -#define MAP_WatchdogIntUnregister \ - WatchdogIntUnregister -#endif - -//***************************************************************************** -// -// Macros for the I2C API. -// -//***************************************************************************** -#ifdef ROM_I2CIntRegister -#define MAP_I2CIntRegister \ - ROM_I2CIntRegister -#else -#define MAP_I2CIntRegister \ - I2CIntRegister -#endif -#ifdef ROM_I2CIntUnregister -#define MAP_I2CIntUnregister \ - ROM_I2CIntUnregister -#else -#define MAP_I2CIntUnregister \ - I2CIntUnregister -#endif -#ifdef ROM_I2CTxFIFOConfigSet -#define MAP_I2CTxFIFOConfigSet \ - ROM_I2CTxFIFOConfigSet -#else -#define MAP_I2CTxFIFOConfigSet \ - I2CTxFIFOConfigSet -#endif -#ifdef ROM_I2CTxFIFOFlush -#define MAP_I2CTxFIFOFlush \ - ROM_I2CTxFIFOFlush -#else -#define MAP_I2CTxFIFOFlush \ - I2CTxFIFOFlush -#endif -#ifdef ROM_I2CRxFIFOConfigSet -#define MAP_I2CRxFIFOConfigSet \ - ROM_I2CRxFIFOConfigSet -#else -#define MAP_I2CRxFIFOConfigSet \ - I2CRxFIFOConfigSet -#endif -#ifdef ROM_I2CRxFIFOFlush -#define MAP_I2CRxFIFOFlush \ - ROM_I2CRxFIFOFlush -#else -#define MAP_I2CRxFIFOFlush \ - I2CRxFIFOFlush -#endif -#ifdef ROM_I2CFIFOStatus -#define MAP_I2CFIFOStatus \ - ROM_I2CFIFOStatus -#else -#define MAP_I2CFIFOStatus \ - I2CFIFOStatus -#endif -#ifdef ROM_I2CFIFODataPut -#define MAP_I2CFIFODataPut \ - ROM_I2CFIFODataPut -#else -#define MAP_I2CFIFODataPut \ - I2CFIFODataPut -#endif -#ifdef ROM_I2CFIFODataPutNonBlocking -#define MAP_I2CFIFODataPutNonBlocking \ - ROM_I2CFIFODataPutNonBlocking -#else -#define MAP_I2CFIFODataPutNonBlocking \ - I2CFIFODataPutNonBlocking -#endif -#ifdef ROM_I2CFIFODataGet -#define MAP_I2CFIFODataGet \ - ROM_I2CFIFODataGet -#else -#define MAP_I2CFIFODataGet \ - I2CFIFODataGet -#endif -#ifdef ROM_I2CFIFODataGetNonBlocking -#define MAP_I2CFIFODataGetNonBlocking \ - ROM_I2CFIFODataGetNonBlocking -#else -#define MAP_I2CFIFODataGetNonBlocking \ - I2CFIFODataGetNonBlocking -#endif -#ifdef ROM_I2CMasterBurstLengthSet -#define MAP_I2CMasterBurstLengthSet \ - ROM_I2CMasterBurstLengthSet -#else -#define MAP_I2CMasterBurstLengthSet \ - I2CMasterBurstLengthSet -#endif -#ifdef ROM_I2CMasterBurstCountGet -#define MAP_I2CMasterBurstCountGet \ - ROM_I2CMasterBurstCountGet -#else -#define MAP_I2CMasterBurstCountGet \ - I2CMasterBurstCountGet -#endif -#ifdef ROM_I2CMasterGlitchFilterConfigSet -#define MAP_I2CMasterGlitchFilterConfigSet \ - ROM_I2CMasterGlitchFilterConfigSet -#else -#define MAP_I2CMasterGlitchFilterConfigSet \ - I2CMasterGlitchFilterConfigSet -#endif -#ifdef ROM_I2CSlaveFIFOEnable -#define MAP_I2CSlaveFIFOEnable \ - ROM_I2CSlaveFIFOEnable -#else -#define MAP_I2CSlaveFIFOEnable \ - I2CSlaveFIFOEnable -#endif -#ifdef ROM_I2CSlaveFIFODisable -#define MAP_I2CSlaveFIFODisable \ - ROM_I2CSlaveFIFODisable -#else -#define MAP_I2CSlaveFIFODisable \ - I2CSlaveFIFODisable -#endif -#ifdef ROM_I2CMasterBusBusy -#define MAP_I2CMasterBusBusy \ - ROM_I2CMasterBusBusy -#else -#define MAP_I2CMasterBusBusy \ - I2CMasterBusBusy -#endif -#ifdef ROM_I2CMasterBusy -#define MAP_I2CMasterBusy \ - ROM_I2CMasterBusy -#else -#define MAP_I2CMasterBusy \ - I2CMasterBusy -#endif -#ifdef ROM_I2CMasterControl -#define MAP_I2CMasterControl \ - ROM_I2CMasterControl -#else -#define MAP_I2CMasterControl \ - I2CMasterControl -#endif -#ifdef ROM_I2CMasterDataGet -#define MAP_I2CMasterDataGet \ - ROM_I2CMasterDataGet -#else -#define MAP_I2CMasterDataGet \ - I2CMasterDataGet -#endif -#ifdef ROM_I2CMasterDataPut -#define MAP_I2CMasterDataPut \ - ROM_I2CMasterDataPut -#else -#define MAP_I2CMasterDataPut \ - I2CMasterDataPut -#endif -#ifdef ROM_I2CMasterDisable -#define MAP_I2CMasterDisable \ - ROM_I2CMasterDisable -#else -#define MAP_I2CMasterDisable \ - I2CMasterDisable -#endif -#ifdef ROM_I2CMasterEnable -#define MAP_I2CMasterEnable \ - ROM_I2CMasterEnable -#else -#define MAP_I2CMasterEnable \ - I2CMasterEnable -#endif -#ifdef ROM_I2CMasterErr -#define MAP_I2CMasterErr \ - ROM_I2CMasterErr -#else -#define MAP_I2CMasterErr \ - I2CMasterErr -#endif -#ifdef ROM_I2CMasterIntClear -#define MAP_I2CMasterIntClear \ - ROM_I2CMasterIntClear -#else -#define MAP_I2CMasterIntClear \ - I2CMasterIntClear -#endif -#ifdef ROM_I2CMasterIntDisable -#define MAP_I2CMasterIntDisable \ - ROM_I2CMasterIntDisable -#else -#define MAP_I2CMasterIntDisable \ - I2CMasterIntDisable -#endif -#ifdef ROM_I2CMasterIntEnable -#define MAP_I2CMasterIntEnable \ - ROM_I2CMasterIntEnable -#else -#define MAP_I2CMasterIntEnable \ - I2CMasterIntEnable -#endif -#ifdef ROM_I2CMasterIntStatus -#define MAP_I2CMasterIntStatus \ - ROM_I2CMasterIntStatus -#else -#define MAP_I2CMasterIntStatus \ - I2CMasterIntStatus -#endif -#ifdef ROM_I2CMasterIntEnableEx -#define MAP_I2CMasterIntEnableEx \ - ROM_I2CMasterIntEnableEx -#else -#define MAP_I2CMasterIntEnableEx \ - I2CMasterIntEnableEx -#endif -#ifdef ROM_I2CMasterIntDisableEx -#define MAP_I2CMasterIntDisableEx \ - ROM_I2CMasterIntDisableEx -#else -#define MAP_I2CMasterIntDisableEx \ - I2CMasterIntDisableEx -#endif -#ifdef ROM_I2CMasterIntStatusEx -#define MAP_I2CMasterIntStatusEx \ - ROM_I2CMasterIntStatusEx -#else -#define MAP_I2CMasterIntStatusEx \ - I2CMasterIntStatusEx -#endif -#ifdef ROM_I2CMasterIntClearEx -#define MAP_I2CMasterIntClearEx \ - ROM_I2CMasterIntClearEx -#else -#define MAP_I2CMasterIntClearEx \ - I2CMasterIntClearEx -#endif -#ifdef ROM_I2CMasterTimeoutSet -#define MAP_I2CMasterTimeoutSet \ - ROM_I2CMasterTimeoutSet -#else -#define MAP_I2CMasterTimeoutSet \ - I2CMasterTimeoutSet -#endif -#ifdef ROM_I2CSlaveACKOverride -#define MAP_I2CSlaveACKOverride \ - ROM_I2CSlaveACKOverride -#else -#define MAP_I2CSlaveACKOverride \ - I2CSlaveACKOverride -#endif -#ifdef ROM_I2CSlaveACKValueSet -#define MAP_I2CSlaveACKValueSet \ - ROM_I2CSlaveACKValueSet -#else -#define MAP_I2CSlaveACKValueSet \ - I2CSlaveACKValueSet -#endif -#ifdef ROM_I2CMasterLineStateGet -#define MAP_I2CMasterLineStateGet \ - ROM_I2CMasterLineStateGet -#else -#define MAP_I2CMasterLineStateGet \ - I2CMasterLineStateGet -#endif -#ifdef ROM_I2CMasterSlaveAddrSet -#define MAP_I2CMasterSlaveAddrSet \ - ROM_I2CMasterSlaveAddrSet -#else -#define MAP_I2CMasterSlaveAddrSet \ - I2CMasterSlaveAddrSet -#endif -#ifdef ROM_I2CSlaveDataGet -#define MAP_I2CSlaveDataGet \ - ROM_I2CSlaveDataGet -#else -#define MAP_I2CSlaveDataGet \ - I2CSlaveDataGet -#endif -#ifdef ROM_I2CSlaveDataPut -#define MAP_I2CSlaveDataPut \ - ROM_I2CSlaveDataPut -#else -#define MAP_I2CSlaveDataPut \ - I2CSlaveDataPut -#endif -#ifdef ROM_I2CSlaveDisable -#define MAP_I2CSlaveDisable \ - ROM_I2CSlaveDisable -#else -#define MAP_I2CSlaveDisable \ - I2CSlaveDisable -#endif -#ifdef ROM_I2CSlaveEnable -#define MAP_I2CSlaveEnable \ - ROM_I2CSlaveEnable -#else -#define MAP_I2CSlaveEnable \ - I2CSlaveEnable -#endif -#ifdef ROM_I2CSlaveInit -#define MAP_I2CSlaveInit \ - ROM_I2CSlaveInit -#else -#define MAP_I2CSlaveInit \ - I2CSlaveInit -#endif -#ifdef ROM_I2CSlaveAddressSet -#define MAP_I2CSlaveAddressSet \ - ROM_I2CSlaveAddressSet -#else -#define MAP_I2CSlaveAddressSet \ - I2CSlaveAddressSet -#endif -#ifdef ROM_I2CSlaveIntClear -#define MAP_I2CSlaveIntClear \ - ROM_I2CSlaveIntClear -#else -#define MAP_I2CSlaveIntClear \ - I2CSlaveIntClear -#endif -#ifdef ROM_I2CSlaveIntDisable -#define MAP_I2CSlaveIntDisable \ - ROM_I2CSlaveIntDisable -#else -#define MAP_I2CSlaveIntDisable \ - I2CSlaveIntDisable -#endif -#ifdef ROM_I2CSlaveIntEnable -#define MAP_I2CSlaveIntEnable \ - ROM_I2CSlaveIntEnable -#else -#define MAP_I2CSlaveIntEnable \ - I2CSlaveIntEnable -#endif -#ifdef ROM_I2CSlaveIntClearEx -#define MAP_I2CSlaveIntClearEx \ - ROM_I2CSlaveIntClearEx -#else -#define MAP_I2CSlaveIntClearEx \ - I2CSlaveIntClearEx -#endif -#ifdef ROM_I2CSlaveIntDisableEx -#define MAP_I2CSlaveIntDisableEx \ - ROM_I2CSlaveIntDisableEx -#else -#define MAP_I2CSlaveIntDisableEx \ - I2CSlaveIntDisableEx -#endif -#ifdef ROM_I2CSlaveIntEnableEx -#define MAP_I2CSlaveIntEnableEx \ - ROM_I2CSlaveIntEnableEx -#else -#define MAP_I2CSlaveIntEnableEx \ - I2CSlaveIntEnableEx -#endif -#ifdef ROM_I2CSlaveIntStatus -#define MAP_I2CSlaveIntStatus \ - ROM_I2CSlaveIntStatus -#else -#define MAP_I2CSlaveIntStatus \ - I2CSlaveIntStatus -#endif -#ifdef ROM_I2CSlaveIntStatusEx -#define MAP_I2CSlaveIntStatusEx \ - ROM_I2CSlaveIntStatusEx -#else -#define MAP_I2CSlaveIntStatusEx \ - I2CSlaveIntStatusEx -#endif -#ifdef ROM_I2CSlaveStatus -#define MAP_I2CSlaveStatus \ - ROM_I2CSlaveStatus -#else -#define MAP_I2CSlaveStatus \ - I2CSlaveStatus -#endif -#ifdef ROM_I2CMasterInitExpClk -#define MAP_I2CMasterInitExpClk \ - ROM_I2CMasterInitExpClk -#else -#define MAP_I2CMasterInitExpClk \ - I2CMasterInitExpClk -#endif - -//***************************************************************************** -// -// Macros for the SPI API. -// -//***************************************************************************** -#ifdef ROM_SPIEnable -#define MAP_SPIEnable \ - ROM_SPIEnable -#else -#define MAP_SPIEnable \ - SPIEnable -#endif -#ifdef ROM_SPIDisable -#define MAP_SPIDisable \ - ROM_SPIDisable -#else -#define MAP_SPIDisable \ - SPIDisable -#endif -#ifdef ROM_SPIReset -#define MAP_SPIReset \ - ROM_SPIReset -#else -#define MAP_SPIReset \ - SPIReset -#endif -#ifdef ROM_SPIConfigSetExpClk -#define MAP_SPIConfigSetExpClk \ - ROM_SPIConfigSetExpClk -#else -#define MAP_SPIConfigSetExpClk \ - SPIConfigSetExpClk -#endif -#ifdef ROM_SPIDataGetNonBlocking -#define MAP_SPIDataGetNonBlocking \ - ROM_SPIDataGetNonBlocking -#else -#define MAP_SPIDataGetNonBlocking \ - SPIDataGetNonBlocking -#endif -#ifdef ROM_SPIDataGet -#define MAP_SPIDataGet \ - ROM_SPIDataGet -#else -#define MAP_SPIDataGet \ - SPIDataGet -#endif -#ifdef ROM_SPIDataPutNonBlocking -#define MAP_SPIDataPutNonBlocking \ - ROM_SPIDataPutNonBlocking -#else -#define MAP_SPIDataPutNonBlocking \ - SPIDataPutNonBlocking -#endif -#ifdef ROM_SPIDataPut -#define MAP_SPIDataPut \ - ROM_SPIDataPut -#else -#define MAP_SPIDataPut \ - SPIDataPut -#endif -#ifdef ROM_SPIFIFOEnable -#define MAP_SPIFIFOEnable \ - ROM_SPIFIFOEnable -#else -#define MAP_SPIFIFOEnable \ - SPIFIFOEnable -#endif -#ifdef ROM_SPIFIFODisable -#define MAP_SPIFIFODisable \ - ROM_SPIFIFODisable -#else -#define MAP_SPIFIFODisable \ - SPIFIFODisable -#endif -#ifdef ROM_SPIFIFOLevelSet -#define MAP_SPIFIFOLevelSet \ - ROM_SPIFIFOLevelSet -#else -#define MAP_SPIFIFOLevelSet \ - SPIFIFOLevelSet -#endif -#ifdef ROM_SPIFIFOLevelGet -#define MAP_SPIFIFOLevelGet \ - ROM_SPIFIFOLevelGet -#else -#define MAP_SPIFIFOLevelGet \ - SPIFIFOLevelGet -#endif -#ifdef ROM_SPIWordCountSet -#define MAP_SPIWordCountSet \ - ROM_SPIWordCountSet -#else -#define MAP_SPIWordCountSet \ - SPIWordCountSet -#endif -#ifdef ROM_SPIIntRegister -#define MAP_SPIIntRegister \ - ROM_SPIIntRegister -#else -#define MAP_SPIIntRegister \ - SPIIntRegister -#endif -#ifdef ROM_SPIIntUnregister -#define MAP_SPIIntUnregister \ - ROM_SPIIntUnregister -#else -#define MAP_SPIIntUnregister \ - SPIIntUnregister -#endif -#ifdef ROM_SPIIntEnable -#define MAP_SPIIntEnable \ - ROM_SPIIntEnable -#else -#define MAP_SPIIntEnable \ - SPIIntEnable -#endif -#ifdef ROM_SPIIntDisable -#define MAP_SPIIntDisable \ - ROM_SPIIntDisable -#else -#define MAP_SPIIntDisable \ - SPIIntDisable -#endif -#ifdef ROM_SPIIntStatus -#define MAP_SPIIntStatus \ - ROM_SPIIntStatus -#else -#define MAP_SPIIntStatus \ - SPIIntStatus -#endif -#ifdef ROM_SPIIntClear -#define MAP_SPIIntClear \ - ROM_SPIIntClear -#else -#define MAP_SPIIntClear \ - SPIIntClear -#endif -#ifdef ROM_SPIDmaEnable -#define MAP_SPIDmaEnable \ - ROM_SPIDmaEnable -#else -#define MAP_SPIDmaEnable \ - SPIDmaEnable -#endif -#ifdef ROM_SPIDmaDisable -#define MAP_SPIDmaDisable \ - ROM_SPIDmaDisable -#else -#define MAP_SPIDmaDisable \ - SPIDmaDisable -#endif -#ifdef ROM_SPICSEnable -#define MAP_SPICSEnable \ - ROM_SPICSEnable -#else -#define MAP_SPICSEnable \ - SPICSEnable -#endif -#ifdef ROM_SPICSDisable -#define MAP_SPICSDisable \ - ROM_SPICSDisable -#else -#define MAP_SPICSDisable \ - SPICSDisable -#endif -#ifdef ROM_SPITransfer -#define MAP_SPITransfer \ - ROM_SPITransfer -#else -#define MAP_SPITransfer \ - SPITransfer -#endif - -//***************************************************************************** -// -// Macros for the CAM API. -// -//***************************************************************************** -#ifdef ROM_CameraReset -#define MAP_CameraReset \ - ROM_CameraReset -#else -#define MAP_CameraReset \ - CameraReset -#endif -#ifdef ROM_CameraParamsConfig -#define MAP_CameraParamsConfig \ - ROM_CameraParamsConfig -#else -#define MAP_CameraParamsConfig \ - CameraParamsConfig -#endif -#ifdef ROM_CameraXClkConfig -#define MAP_CameraXClkConfig \ - ROM_CameraXClkConfig -#else -#define MAP_CameraXClkConfig \ - CameraXClkConfig -#endif -#ifdef ROM_CameraXClkSet -#define MAP_CameraXClkSet \ - ROM_CameraXClkSet -#else -#define MAP_CameraXClkSet \ - CameraXClkSet -#endif -#ifdef ROM_CameraDMAEnable -#define MAP_CameraDMAEnable \ - ROM_CameraDMAEnable -#else -#define MAP_CameraDMAEnable \ - CameraDMAEnable -#endif -#ifdef ROM_CameraDMADisable -#define MAP_CameraDMADisable \ - ROM_CameraDMADisable -#else -#define MAP_CameraDMADisable \ - CameraDMADisable -#endif -#ifdef ROM_CameraThresholdSet -#define MAP_CameraThresholdSet \ - ROM_CameraThresholdSet -#else -#define MAP_CameraThresholdSet \ - CameraThresholdSet -#endif -#ifdef ROM_CameraIntRegister -#define MAP_CameraIntRegister \ - ROM_CameraIntRegister -#else -#define MAP_CameraIntRegister \ - CameraIntRegister -#endif -#ifdef ROM_CameraIntUnregister -#define MAP_CameraIntUnregister \ - ROM_CameraIntUnregister -#else -#define MAP_CameraIntUnregister \ - CameraIntUnregister -#endif -#ifdef ROM_CameraIntEnable -#define MAP_CameraIntEnable \ - ROM_CameraIntEnable -#else -#define MAP_CameraIntEnable \ - CameraIntEnable -#endif -#ifdef ROM_CameraIntDisable -#define MAP_CameraIntDisable \ - ROM_CameraIntDisable -#else -#define MAP_CameraIntDisable \ - CameraIntDisable -#endif -#ifdef ROM_CameraIntStatus -#define MAP_CameraIntStatus \ - ROM_CameraIntStatus -#else -#define MAP_CameraIntStatus \ - CameraIntStatus -#endif -#ifdef ROM_CameraIntClear -#define MAP_CameraIntClear \ - ROM_CameraIntClear -#else -#define MAP_CameraIntClear \ - CameraIntClear -#endif -#ifdef ROM_CameraCaptureStop -#define MAP_CameraCaptureStop \ - ROM_CameraCaptureStop -#else -#define MAP_CameraCaptureStop \ - CameraCaptureStop -#endif -#ifdef ROM_CameraCaptureStart -#define MAP_CameraCaptureStart \ - ROM_CameraCaptureStart -#else -#define MAP_CameraCaptureStart \ - CameraCaptureStart -#endif -#ifdef ROM_CameraBufferRead -#define MAP_CameraBufferRead \ - ROM_CameraBufferRead -#else -#define MAP_CameraBufferRead \ - CameraBufferRead -#endif - -//***************************************************************************** -// -// Macros for the FLASH API. -// -//***************************************************************************** -#ifdef ROM_FlashDisable -#define MAP_FlashDisable \ - ROM_FlashDisable -#else -#define MAP_FlashDisable \ - FlashDisable -#endif -#ifdef ROM_FlashErase -#define MAP_FlashErase \ - ROM_FlashErase -#else -#define MAP_FlashErase \ - FlashErase -#endif -#ifdef ROM_FlashMassErase -#define MAP_FlashMassErase \ - ROM_FlashMassErase -#else -#define MAP_FlashMassErase \ - FlashMassErase -#endif -#ifdef ROM_FlashMassEraseNonBlocking -#define MAP_FlashMassEraseNonBlocking \ - ROM_FlashMassEraseNonBlocking -#else -#define MAP_FlashMassEraseNonBlocking \ - FlashMassEraseNonBlocking -#endif -#ifdef ROM_FlashEraseNonBlocking -#define MAP_FlashEraseNonBlocking \ - ROM_FlashEraseNonBlocking -#else -#define MAP_FlashEraseNonBlocking \ - FlashEraseNonBlocking -#endif -#ifdef ROM_FlashProgram -#define MAP_FlashProgram \ - ROM_FlashProgram -#else -#define MAP_FlashProgram \ - FlashProgram -#endif -#ifdef ROM_FlashProgramNonBlocking -#define MAP_FlashProgramNonBlocking \ - ROM_FlashProgramNonBlocking -#else -#define MAP_FlashProgramNonBlocking \ - FlashProgramNonBlocking -#endif -#ifdef ROM_FlashIntRegister -#define MAP_FlashIntRegister \ - ROM_FlashIntRegister -#else -#define MAP_FlashIntRegister \ - FlashIntRegister -#endif -#ifdef ROM_FlashIntUnregister -#define MAP_FlashIntUnregister \ - ROM_FlashIntUnregister -#else -#define MAP_FlashIntUnregister \ - FlashIntUnregister -#endif -#ifdef ROM_FlashIntEnable -#define MAP_FlashIntEnable \ - ROM_FlashIntEnable -#else -#define MAP_FlashIntEnable \ - FlashIntEnable -#endif -#ifdef ROM_FlashIntDisable -#define MAP_FlashIntDisable \ - ROM_FlashIntDisable -#else -#define MAP_FlashIntDisable \ - FlashIntDisable -#endif -#ifdef ROM_FlashIntStatus -#define MAP_FlashIntStatus \ - ROM_FlashIntStatus -#else -#define MAP_FlashIntStatus \ - FlashIntStatus -#endif -#ifdef ROM_FlashIntClear -#define MAP_FlashIntClear \ - ROM_FlashIntClear -#else -#define MAP_FlashIntClear \ - FlashIntClear -#endif -#ifdef ROM_FlashProtectGet -#define MAP_FlashProtectGet \ - ROM_FlashProtectGet -#else -#define MAP_FlashProtectGet \ - FlashProtectGet -#endif - -//***************************************************************************** -// -// Macros for the Pin API. -// -//***************************************************************************** -#ifdef ROM_PinModeSet -#define MAP_PinModeSet \ - ROM_PinModeSet -#else -#define MAP_PinModeSet \ - PinModeSet -#endif -#ifdef ROM_PinDirModeSet -#define MAP_PinDirModeSet \ - ROM_PinDirModeSet -#else -#define MAP_PinDirModeSet \ - PinDirModeSet -#endif -#ifdef ROM_PinDirModeGet -#define MAP_PinDirModeGet \ - ROM_PinDirModeGet -#else -#define MAP_PinDirModeGet \ - PinDirModeGet -#endif -#ifdef ROM_PinModeGet -#define MAP_PinModeGet \ - ROM_PinModeGet -#else -#define MAP_PinModeGet \ - PinModeGet -#endif -#ifdef ROM_PinConfigGet -#define MAP_PinConfigGet \ - ROM_PinConfigGet -#else -#define MAP_PinConfigGet \ - PinConfigGet -#endif -#ifdef ROM_PinConfigSet -#define MAP_PinConfigSet \ - ROM_PinConfigSet -#else -#define MAP_PinConfigSet \ - PinConfigSet -#endif -#ifdef ROM_PinTypeUART -#define MAP_PinTypeUART \ - ROM_PinTypeUART -#else -#define MAP_PinTypeUART \ - PinTypeUART -#endif -#ifdef ROM_PinTypeI2C -#define MAP_PinTypeI2C \ - ROM_PinTypeI2C -#else -#define MAP_PinTypeI2C \ - PinTypeI2C -#endif -#ifdef ROM_PinTypeSPI -#define MAP_PinTypeSPI \ - ROM_PinTypeSPI -#else -#define MAP_PinTypeSPI \ - PinTypeSPI -#endif -#ifdef ROM_PinTypeI2S -#define MAP_PinTypeI2S \ - ROM_PinTypeI2S -#else -#define MAP_PinTypeI2S \ - PinTypeI2S -#endif -#ifdef ROM_PinTypeTimer -#define MAP_PinTypeTimer \ - ROM_PinTypeTimer -#else -#define MAP_PinTypeTimer \ - PinTypeTimer -#endif -#ifdef ROM_PinTypeCamera -#define MAP_PinTypeCamera \ - ROM_PinTypeCamera -#else -#define MAP_PinTypeCamera \ - PinTypeCamera -#endif -#ifdef ROM_PinTypeGPIO -#define MAP_PinTypeGPIO \ - ROM_PinTypeGPIO -#else -#define MAP_PinTypeGPIO \ - PinTypeGPIO -#endif -#ifdef ROM_PinTypeADC -#define MAP_PinTypeADC \ - ROM_PinTypeADC -#else -#define MAP_PinTypeADC \ - PinTypeADC -#endif -#ifdef ROM_PinTypeSDHost -#define MAP_PinTypeSDHost \ - ROM_PinTypeSDHost -#else -#define MAP_PinTypeSDHost \ - PinTypeSDHost -#endif -#ifdef ROM_PinHysteresisSet -#define MAP_PinHysteresisSet \ - ROM_PinHysteresisSet -#else -#define MAP_PinHysteresisSet \ - PinHysteresisSet -#endif -#ifdef ROM_PinLockLevelSet -#define MAP_PinLockLevelSet \ - ROM_PinLockLevelSet -#else -#define MAP_PinLockLevelSet \ - PinLockLevelSet -#endif -#ifdef ROM_PinLock -#define MAP_PinLock \ - ROM_PinLock -#else -#define MAP_PinLock \ - PinLock -#endif -#ifdef ROM_PinUnlock -#define MAP_PinUnlock \ - ROM_PinUnlock -#else -#define MAP_PinUnlock \ - PinUnlock -#endif - -//***************************************************************************** -// -// Macros for the SYSTICK API. -// -//***************************************************************************** -#ifdef ROM_SysTickEnable -#define MAP_SysTickEnable \ - ROM_SysTickEnable -#else -#define MAP_SysTickEnable \ - SysTickEnable -#endif -#ifdef ROM_SysTickDisable -#define MAP_SysTickDisable \ - ROM_SysTickDisable -#else -#define MAP_SysTickDisable \ - SysTickDisable -#endif -#ifdef ROM_SysTickIntRegister -#define MAP_SysTickIntRegister \ - ROM_SysTickIntRegister -#else -#define MAP_SysTickIntRegister \ - SysTickIntRegister -#endif -#ifdef ROM_SysTickIntUnregister -#define MAP_SysTickIntUnregister \ - ROM_SysTickIntUnregister -#else -#define MAP_SysTickIntUnregister \ - SysTickIntUnregister -#endif -#ifdef ROM_SysTickIntEnable -#define MAP_SysTickIntEnable \ - ROM_SysTickIntEnable -#else -#define MAP_SysTickIntEnable \ - SysTickIntEnable -#endif -#ifdef ROM_SysTickIntDisable -#define MAP_SysTickIntDisable \ - ROM_SysTickIntDisable -#else -#define MAP_SysTickIntDisable \ - SysTickIntDisable -#endif -#ifdef ROM_SysTickPeriodSet -#define MAP_SysTickPeriodSet \ - ROM_SysTickPeriodSet -#else -#define MAP_SysTickPeriodSet \ - SysTickPeriodSet -#endif -#ifdef ROM_SysTickPeriodGet -#define MAP_SysTickPeriodGet \ - ROM_SysTickPeriodGet -#else -#define MAP_SysTickPeriodGet \ - SysTickPeriodGet -#endif -#ifdef ROM_SysTickValueGet -#define MAP_SysTickValueGet \ - ROM_SysTickValueGet -#else -#define MAP_SysTickValueGet \ - SysTickValueGet -#endif - -//***************************************************************************** -// -// Macros for the UTILS API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define MAP_UtilsDelay \ - ROM_UtilsDelay -#else -#define MAP_UtilsDelay \ - UtilsDelay -#endif - -//***************************************************************************** -// -// Macros for the I2S API. -// -//***************************************************************************** -#ifdef ROM_I2SEnable -#define MAP_I2SEnable \ - ROM_I2SEnable -#else -#define MAP_I2SEnable \ - I2SEnable -#endif -#ifdef ROM_I2SDisable -#define MAP_I2SDisable \ - ROM_I2SDisable -#else -#define MAP_I2SDisable \ - I2SDisable -#endif -#ifdef ROM_I2SDataPut -#define MAP_I2SDataPut \ - ROM_I2SDataPut -#else -#define MAP_I2SDataPut \ - I2SDataPut -#endif -#ifdef ROM_I2SDataPutNonBlocking -#define MAP_I2SDataPutNonBlocking \ - ROM_I2SDataPutNonBlocking -#else -#define MAP_I2SDataPutNonBlocking \ - I2SDataPutNonBlocking -#endif -#ifdef ROM_I2SDataGet -#define MAP_I2SDataGet \ - ROM_I2SDataGet -#else -#define MAP_I2SDataGet \ - I2SDataGet -#endif -#ifdef ROM_I2SDataGetNonBlocking -#define MAP_I2SDataGetNonBlocking \ - ROM_I2SDataGetNonBlocking -#else -#define MAP_I2SDataGetNonBlocking \ - I2SDataGetNonBlocking -#endif -#ifdef ROM_I2SConfigSetExpClk -#define MAP_I2SConfigSetExpClk \ - ROM_I2SConfigSetExpClk -#else -#define MAP_I2SConfigSetExpClk \ - I2SConfigSetExpClk -#endif -#ifdef ROM_I2STxFIFOEnable -#define MAP_I2STxFIFOEnable \ - ROM_I2STxFIFOEnable -#else -#define MAP_I2STxFIFOEnable \ - I2STxFIFOEnable -#endif -#ifdef ROM_I2STxFIFODisable -#define MAP_I2STxFIFODisable \ - ROM_I2STxFIFODisable -#else -#define MAP_I2STxFIFODisable \ - I2STxFIFODisable -#endif -#ifdef ROM_I2SRxFIFOEnable -#define MAP_I2SRxFIFOEnable \ - ROM_I2SRxFIFOEnable -#else -#define MAP_I2SRxFIFOEnable \ - I2SRxFIFOEnable -#endif -#ifdef ROM_I2SRxFIFODisable -#define MAP_I2SRxFIFODisable \ - ROM_I2SRxFIFODisable -#else -#define MAP_I2SRxFIFODisable \ - I2SRxFIFODisable -#endif -#ifdef ROM_I2STxFIFOStatusGet -#define MAP_I2STxFIFOStatusGet \ - ROM_I2STxFIFOStatusGet -#else -#define MAP_I2STxFIFOStatusGet \ - I2STxFIFOStatusGet -#endif -#ifdef ROM_I2SRxFIFOStatusGet -#define MAP_I2SRxFIFOStatusGet \ - ROM_I2SRxFIFOStatusGet -#else -#define MAP_I2SRxFIFOStatusGet \ - I2SRxFIFOStatusGet -#endif -#ifdef ROM_I2SSerializerConfig -#define MAP_I2SSerializerConfig \ - ROM_I2SSerializerConfig -#else -#define MAP_I2SSerializerConfig \ - I2SSerializerConfig -#endif -#ifdef ROM_I2SIntEnable -#define MAP_I2SIntEnable \ - ROM_I2SIntEnable -#else -#define MAP_I2SIntEnable \ - I2SIntEnable -#endif -#ifdef ROM_I2SIntDisable -#define MAP_I2SIntDisable \ - ROM_I2SIntDisable -#else -#define MAP_I2SIntDisable \ - I2SIntDisable -#endif -#ifdef ROM_I2SIntStatus -#define MAP_I2SIntStatus \ - ROM_I2SIntStatus -#else -#define MAP_I2SIntStatus \ - I2SIntStatus -#endif -#ifdef ROM_I2SIntClear -#define MAP_I2SIntClear \ - ROM_I2SIntClear -#else -#define MAP_I2SIntClear \ - I2SIntClear -#endif -#ifdef ROM_I2SIntRegister -#define MAP_I2SIntRegister \ - ROM_I2SIntRegister -#else -#define MAP_I2SIntRegister \ - I2SIntRegister -#endif -#ifdef ROM_I2SIntUnregister -#define MAP_I2SIntUnregister \ - ROM_I2SIntUnregister -#else -#define MAP_I2SIntUnregister \ - I2SIntUnregister -#endif -#ifdef ROM_I2STxActiveSlotSet -#define MAP_I2STxActiveSlotSet \ - ROM_I2STxActiveSlotSet -#else -#define MAP_I2STxActiveSlotSet \ - I2STxActiveSlotSet -#endif -#ifdef ROM_I2SRxActiveSlotSet -#define MAP_I2SRxActiveSlotSet \ - ROM_I2SRxActiveSlotSet -#else -#define MAP_I2SRxActiveSlotSet \ - I2SRxActiveSlotSet -#endif - -//***************************************************************************** -// -// Macros for the GPIO API. -// -//***************************************************************************** -#ifdef ROM_GPIODirModeSet -#define MAP_GPIODirModeSet \ - ROM_GPIODirModeSet -#else -#define MAP_GPIODirModeSet \ - GPIODirModeSet -#endif -#ifdef ROM_GPIODirModeGet -#define MAP_GPIODirModeGet \ - ROM_GPIODirModeGet -#else -#define MAP_GPIODirModeGet \ - GPIODirModeGet -#endif -#ifdef ROM_GPIOIntTypeSet -#define MAP_GPIOIntTypeSet \ - ROM_GPIOIntTypeSet -#else -#define MAP_GPIOIntTypeSet \ - GPIOIntTypeSet -#endif -#ifdef ROM_GPIODMATriggerEnable -#define MAP_GPIODMATriggerEnable \ - ROM_GPIODMATriggerEnable -#else -#define MAP_GPIODMATriggerEnable \ - GPIODMATriggerEnable -#endif -#ifdef ROM_GPIODMATriggerDisable -#define MAP_GPIODMATriggerDisable \ - ROM_GPIODMATriggerDisable -#else -#define MAP_GPIODMATriggerDisable \ - GPIODMATriggerDisable -#endif -#ifdef ROM_GPIOIntTypeGet -#define MAP_GPIOIntTypeGet \ - ROM_GPIOIntTypeGet -#else -#define MAP_GPIOIntTypeGet \ - GPIOIntTypeGet -#endif -#ifdef ROM_GPIOIntEnable -#define MAP_GPIOIntEnable \ - ROM_GPIOIntEnable -#else -#define MAP_GPIOIntEnable \ - GPIOIntEnable -#endif -#ifdef ROM_GPIOIntDisable -#define MAP_GPIOIntDisable \ - ROM_GPIOIntDisable -#else -#define MAP_GPIOIntDisable \ - GPIOIntDisable -#endif -#ifdef ROM_GPIOIntStatus -#define MAP_GPIOIntStatus \ - ROM_GPIOIntStatus -#else -#define MAP_GPIOIntStatus \ - GPIOIntStatus -#endif -#ifdef ROM_GPIOIntClear -#define MAP_GPIOIntClear \ - ROM_GPIOIntClear -#else -#define MAP_GPIOIntClear \ - GPIOIntClear -#endif -#ifdef ROM_GPIOIntRegister -#define MAP_GPIOIntRegister \ - ROM_GPIOIntRegister -#else -#define MAP_GPIOIntRegister \ - GPIOIntRegister -#endif -#ifdef ROM_GPIOIntUnregister -#define MAP_GPIOIntUnregister \ - ROM_GPIOIntUnregister -#else -#define MAP_GPIOIntUnregister \ - GPIOIntUnregister -#endif -#ifdef ROM_GPIOPinRead -#define MAP_GPIOPinRead \ - ROM_GPIOPinRead -#else -#define MAP_GPIOPinRead \ - GPIOPinRead -#endif -#ifdef ROM_GPIOPinWrite -#define MAP_GPIOPinWrite \ - ROM_GPIOPinWrite -#else -#define MAP_GPIOPinWrite \ - GPIOPinWrite -#endif - -//***************************************************************************** -// -// Macros for the AES API. -// -//***************************************************************************** -#ifdef ROM_AESConfigSet -#define MAP_AESConfigSet \ - ROM_AESConfigSet -#else -#define MAP_AESConfigSet \ - AESConfigSet -#endif -#ifdef ROM_AESKey1Set -#define MAP_AESKey1Set \ - ROM_AESKey1Set -#else -#define MAP_AESKey1Set \ - AESKey1Set -#endif -#ifdef ROM_AESKey2Set -#define MAP_AESKey2Set \ - ROM_AESKey2Set -#else -#define MAP_AESKey2Set \ - AESKey2Set -#endif -#ifdef ROM_AESKey3Set -#define MAP_AESKey3Set \ - ROM_AESKey3Set -#else -#define MAP_AESKey3Set \ - AESKey3Set -#endif -#ifdef ROM_AESIVSet -#define MAP_AESIVSet \ - ROM_AESIVSet -#else -#define MAP_AESIVSet \ - AESIVSet -#endif -#ifdef ROM_AESTagRead -#define MAP_AESTagRead \ - ROM_AESTagRead -#else -#define MAP_AESTagRead \ - AESTagRead -#endif -#ifdef ROM_AESDataLengthSet -#define MAP_AESDataLengthSet \ - ROM_AESDataLengthSet -#else -#define MAP_AESDataLengthSet \ - AESDataLengthSet -#endif -#ifdef ROM_AESAuthDataLengthSet -#define MAP_AESAuthDataLengthSet \ - ROM_AESAuthDataLengthSet -#else -#define MAP_AESAuthDataLengthSet \ - AESAuthDataLengthSet -#endif -#ifdef ROM_AESDataReadNonBlocking -#define MAP_AESDataReadNonBlocking \ - ROM_AESDataReadNonBlocking -#else -#define MAP_AESDataReadNonBlocking \ - AESDataReadNonBlocking -#endif -#ifdef ROM_AESDataRead -#define MAP_AESDataRead \ - ROM_AESDataRead -#else -#define MAP_AESDataRead \ - AESDataRead -#endif -#ifdef ROM_AESDataWriteNonBlocking -#define MAP_AESDataWriteNonBlocking \ - ROM_AESDataWriteNonBlocking -#else -#define MAP_AESDataWriteNonBlocking \ - AESDataWriteNonBlocking -#endif -#ifdef ROM_AESDataWrite -#define MAP_AESDataWrite \ - ROM_AESDataWrite -#else -#define MAP_AESDataWrite \ - AESDataWrite -#endif -#ifdef ROM_AESDataProcess -#define MAP_AESDataProcess \ - ROM_AESDataProcess -#else -#define MAP_AESDataProcess \ - AESDataProcess -#endif -#ifdef ROM_AESDataMAC -#define MAP_AESDataMAC \ - ROM_AESDataMAC -#else -#define MAP_AESDataMAC \ - AESDataMAC -#endif -#ifdef ROM_AESDataProcessAE -#define MAP_AESDataProcessAE \ - ROM_AESDataProcessAE -#else -#define MAP_AESDataProcessAE \ - AESDataProcessAE -#endif -#ifdef ROM_AESIntStatus -#define MAP_AESIntStatus \ - ROM_AESIntStatus -#else -#define MAP_AESIntStatus \ - AESIntStatus -#endif -#ifdef ROM_AESIntEnable -#define MAP_AESIntEnable \ - ROM_AESIntEnable -#else -#define MAP_AESIntEnable \ - AESIntEnable -#endif -#ifdef ROM_AESIntDisable -#define MAP_AESIntDisable \ - ROM_AESIntDisable -#else -#define MAP_AESIntDisable \ - AESIntDisable -#endif -#ifdef ROM_AESIntClear -#define MAP_AESIntClear \ - ROM_AESIntClear -#else -#define MAP_AESIntClear \ - AESIntClear -#endif -#ifdef ROM_AESIntRegister -#define MAP_AESIntRegister \ - ROM_AESIntRegister -#else -#define MAP_AESIntRegister \ - AESIntRegister -#endif -#ifdef ROM_AESIntUnregister -#define MAP_AESIntUnregister \ - ROM_AESIntUnregister -#else -#define MAP_AESIntUnregister \ - AESIntUnregister -#endif -#ifdef ROM_AESDMAEnable -#define MAP_AESDMAEnable \ - ROM_AESDMAEnable -#else -#define MAP_AESDMAEnable \ - AESDMAEnable -#endif -#ifdef ROM_AESDMADisable -#define MAP_AESDMADisable \ - ROM_AESDMADisable -#else -#define MAP_AESDMADisable \ - AESDMADisable -#endif -#ifdef ROM_AESIVGet -#define MAP_AESIVGet \ - ROM_AESIVGet -#else -#define MAP_AESIVGet \ - AESIVGet -#endif - -//***************************************************************************** -// -// Macros for the DES API. -// -//***************************************************************************** -#ifdef ROM_DESConfigSet -#define MAP_DESConfigSet \ - ROM_DESConfigSet -#else -#define MAP_DESConfigSet \ - DESConfigSet -#endif -#ifdef ROM_DESDataRead -#define MAP_DESDataRead \ - ROM_DESDataRead -#else -#define MAP_DESDataRead \ - DESDataRead -#endif -#ifdef ROM_DESDataReadNonBlocking -#define MAP_DESDataReadNonBlocking \ - ROM_DESDataReadNonBlocking -#else -#define MAP_DESDataReadNonBlocking \ - DESDataReadNonBlocking -#endif -#ifdef ROM_DESDataProcess -#define MAP_DESDataProcess \ - ROM_DESDataProcess -#else -#define MAP_DESDataProcess \ - DESDataProcess -#endif -#ifdef ROM_DESDataWrite -#define MAP_DESDataWrite \ - ROM_DESDataWrite -#else -#define MAP_DESDataWrite \ - DESDataWrite -#endif -#ifdef ROM_DESDataWriteNonBlocking -#define MAP_DESDataWriteNonBlocking \ - ROM_DESDataWriteNonBlocking -#else -#define MAP_DESDataWriteNonBlocking \ - DESDataWriteNonBlocking -#endif -#ifdef ROM_DESDMADisable -#define MAP_DESDMADisable \ - ROM_DESDMADisable -#else -#define MAP_DESDMADisable \ - DESDMADisable -#endif -#ifdef ROM_DESDMAEnable -#define MAP_DESDMAEnable \ - ROM_DESDMAEnable -#else -#define MAP_DESDMAEnable \ - DESDMAEnable -#endif -#ifdef ROM_DESIntClear -#define MAP_DESIntClear \ - ROM_DESIntClear -#else -#define MAP_DESIntClear \ - DESIntClear -#endif -#ifdef ROM_DESIntDisable -#define MAP_DESIntDisable \ - ROM_DESIntDisable -#else -#define MAP_DESIntDisable \ - DESIntDisable -#endif -#ifdef ROM_DESIntEnable -#define MAP_DESIntEnable \ - ROM_DESIntEnable -#else -#define MAP_DESIntEnable \ - DESIntEnable -#endif -#ifdef ROM_DESIntRegister -#define MAP_DESIntRegister \ - ROM_DESIntRegister -#else -#define MAP_DESIntRegister \ - DESIntRegister -#endif -#ifdef ROM_DESIntStatus -#define MAP_DESIntStatus \ - ROM_DESIntStatus -#else -#define MAP_DESIntStatus \ - DESIntStatus -#endif -#ifdef ROM_DESIntUnregister -#define MAP_DESIntUnregister \ - ROM_DESIntUnregister -#else -#define MAP_DESIntUnregister \ - DESIntUnregister -#endif -#ifdef ROM_DESIVSet -#define MAP_DESIVSet \ - ROM_DESIVSet -#else -#define MAP_DESIVSet \ - DESIVSet -#endif -#ifdef ROM_DESKeySet -#define MAP_DESKeySet \ - ROM_DESKeySet -#else -#define MAP_DESKeySet \ - DESKeySet -#endif -#ifdef ROM_DESDataLengthSet -#define MAP_DESDataLengthSet \ - ROM_DESDataLengthSet -#else -#define MAP_DESDataLengthSet \ - DESDataLengthSet -#endif - -//***************************************************************************** -// -// Macros for the SHAMD5 API. -// -//***************************************************************************** -#ifdef ROM_SHAMD5ConfigSet -#define MAP_SHAMD5ConfigSet \ - ROM_SHAMD5ConfigSet -#else -#define MAP_SHAMD5ConfigSet \ - SHAMD5ConfigSet -#endif -#ifdef ROM_SHAMD5DataProcess -#define MAP_SHAMD5DataProcess \ - ROM_SHAMD5DataProcess -#else -#define MAP_SHAMD5DataProcess \ - SHAMD5DataProcess -#endif -#ifdef ROM_SHAMD5DataWrite -#define MAP_SHAMD5DataWrite \ - ROM_SHAMD5DataWrite -#else -#define MAP_SHAMD5DataWrite \ - SHAMD5DataWrite -#endif -#ifdef ROM_SHAMD5DataWriteNonBlocking -#define MAP_SHAMD5DataWriteNonBlocking \ - ROM_SHAMD5DataWriteNonBlocking -#else -#define MAP_SHAMD5DataWriteNonBlocking \ - SHAMD5DataWriteNonBlocking -#endif -#ifdef ROM_SHAMD5DMADisable -#define MAP_SHAMD5DMADisable \ - ROM_SHAMD5DMADisable -#else -#define MAP_SHAMD5DMADisable \ - SHAMD5DMADisable -#endif -#ifdef ROM_SHAMD5DMAEnable -#define MAP_SHAMD5DMAEnable \ - ROM_SHAMD5DMAEnable -#else -#define MAP_SHAMD5DMAEnable \ - SHAMD5DMAEnable -#endif -#ifdef ROM_SHAMD5DataLengthSet -#define MAP_SHAMD5DataLengthSet \ - ROM_SHAMD5DataLengthSet -#else -#define MAP_SHAMD5DataLengthSet \ - SHAMD5DataLengthSet -#endif -#ifdef ROM_SHAMD5HMACKeySet -#define MAP_SHAMD5HMACKeySet \ - ROM_SHAMD5HMACKeySet -#else -#define MAP_SHAMD5HMACKeySet \ - SHAMD5HMACKeySet -#endif -#ifdef ROM_SHAMD5HMACPPKeyGenerate -#define MAP_SHAMD5HMACPPKeyGenerate \ - ROM_SHAMD5HMACPPKeyGenerate -#else -#define MAP_SHAMD5HMACPPKeyGenerate \ - SHAMD5HMACPPKeyGenerate -#endif -#ifdef ROM_SHAMD5HMACPPKeySet -#define MAP_SHAMD5HMACPPKeySet \ - ROM_SHAMD5HMACPPKeySet -#else -#define MAP_SHAMD5HMACPPKeySet \ - SHAMD5HMACPPKeySet -#endif -#ifdef ROM_SHAMD5HMACProcess -#define MAP_SHAMD5HMACProcess \ - ROM_SHAMD5HMACProcess -#else -#define MAP_SHAMD5HMACProcess \ - SHAMD5HMACProcess -#endif -#ifdef ROM_SHAMD5IntClear -#define MAP_SHAMD5IntClear \ - ROM_SHAMD5IntClear -#else -#define MAP_SHAMD5IntClear \ - SHAMD5IntClear -#endif -#ifdef ROM_SHAMD5IntDisable -#define MAP_SHAMD5IntDisable \ - ROM_SHAMD5IntDisable -#else -#define MAP_SHAMD5IntDisable \ - SHAMD5IntDisable -#endif -#ifdef ROM_SHAMD5IntEnable -#define MAP_SHAMD5IntEnable \ - ROM_SHAMD5IntEnable -#else -#define MAP_SHAMD5IntEnable \ - SHAMD5IntEnable -#endif -#ifdef ROM_SHAMD5IntRegister -#define MAP_SHAMD5IntRegister \ - ROM_SHAMD5IntRegister -#else -#define MAP_SHAMD5IntRegister \ - SHAMD5IntRegister -#endif -#ifdef ROM_SHAMD5IntStatus -#define MAP_SHAMD5IntStatus \ - ROM_SHAMD5IntStatus -#else -#define MAP_SHAMD5IntStatus \ - SHAMD5IntStatus -#endif -#ifdef ROM_SHAMD5IntUnregister -#define MAP_SHAMD5IntUnregister \ - ROM_SHAMD5IntUnregister -#else -#define MAP_SHAMD5IntUnregister \ - SHAMD5IntUnregister -#endif -#ifdef ROM_SHAMD5ResultRead -#define MAP_SHAMD5ResultRead \ - ROM_SHAMD5ResultRead -#else -#define MAP_SHAMD5ResultRead \ - SHAMD5ResultRead -#endif - -//***************************************************************************** -// -// Macros for the CRC API. -// -//***************************************************************************** -#ifdef ROM_CRCConfigSet -#define MAP_CRCConfigSet \ - ROM_CRCConfigSet -#else -#define MAP_CRCConfigSet \ - CRCConfigSet -#endif -#ifdef ROM_CRCDataProcess -#define MAP_CRCDataProcess \ - ROM_CRCDataProcess -#else -#define MAP_CRCDataProcess \ - CRCDataProcess -#endif -#ifdef ROM_CRCDataWrite -#define MAP_CRCDataWrite \ - ROM_CRCDataWrite -#else -#define MAP_CRCDataWrite \ - CRCDataWrite -#endif -#ifdef ROM_CRCResultRead -#define MAP_CRCResultRead \ - ROM_CRCResultRead -#else -#define MAP_CRCResultRead \ - CRCResultRead -#endif -#ifdef ROM_CRCSeedSet -#define MAP_CRCSeedSet \ - ROM_CRCSeedSet -#else -#define MAP_CRCSeedSet \ - CRCSeedSet -#endif - -//***************************************************************************** -// -// Macros for the SDHOST API. -// -//***************************************************************************** -#ifdef ROM_SDHostCmdReset -#define MAP_SDHostCmdReset \ - ROM_SDHostCmdReset -#else -#define MAP_SDHostCmdReset \ - SDHostCmdReset -#endif -#ifdef ROM_SDHostInit -#define MAP_SDHostInit \ - ROM_SDHostInit -#else -#define MAP_SDHostInit \ - SDHostInit -#endif -#ifdef ROM_SDHostCmdSend -#define MAP_SDHostCmdSend \ - ROM_SDHostCmdSend -#else -#define MAP_SDHostCmdSend \ - SDHostCmdSend -#endif -#ifdef ROM_SDHostIntRegister -#define MAP_SDHostIntRegister \ - ROM_SDHostIntRegister -#else -#define MAP_SDHostIntRegister \ - SDHostIntRegister -#endif -#ifdef ROM_SDHostIntUnregister -#define MAP_SDHostIntUnregister \ - ROM_SDHostIntUnregister -#else -#define MAP_SDHostIntUnregister \ - SDHostIntUnregister -#endif -#ifdef ROM_SDHostIntEnable -#define MAP_SDHostIntEnable \ - ROM_SDHostIntEnable -#else -#define MAP_SDHostIntEnable \ - SDHostIntEnable -#endif -#ifdef ROM_SDHostIntDisable -#define MAP_SDHostIntDisable \ - ROM_SDHostIntDisable -#else -#define MAP_SDHostIntDisable \ - SDHostIntDisable -#endif -#ifdef ROM_SDHostIntStatus -#define MAP_SDHostIntStatus \ - ROM_SDHostIntStatus -#else -#define MAP_SDHostIntStatus \ - SDHostIntStatus -#endif -#ifdef ROM_SDHostIntClear -#define MAP_SDHostIntClear \ - ROM_SDHostIntClear -#else -#define MAP_SDHostIntClear \ - SDHostIntClear -#endif -#ifdef ROM_SDHostRespGet -#define MAP_SDHostRespGet \ - ROM_SDHostRespGet -#else -#define MAP_SDHostRespGet \ - SDHostRespGet -#endif -#ifdef ROM_SDHostBlockSizeSet -#define MAP_SDHostBlockSizeSet \ - ROM_SDHostBlockSizeSet -#else -#define MAP_SDHostBlockSizeSet \ - SDHostBlockSizeSet -#endif -#ifdef ROM_SDHostBlockCountSet -#define MAP_SDHostBlockCountSet \ - ROM_SDHostBlockCountSet -#else -#define MAP_SDHostBlockCountSet \ - SDHostBlockCountSet -#endif -#ifdef ROM_SDHostDataNonBlockingWrite -#define MAP_SDHostDataNonBlockingWrite \ - ROM_SDHostDataNonBlockingWrite -#else -#define MAP_SDHostDataNonBlockingWrite \ - SDHostDataNonBlockingWrite -#endif -#ifdef ROM_SDHostDataNonBlockingRead -#define MAP_SDHostDataNonBlockingRead \ - ROM_SDHostDataNonBlockingRead -#else -#define MAP_SDHostDataNonBlockingRead \ - SDHostDataNonBlockingRead -#endif -#ifdef ROM_SDHostDataWrite -#define MAP_SDHostDataWrite \ - ROM_SDHostDataWrite -#else -#define MAP_SDHostDataWrite \ - SDHostDataWrite -#endif -#ifdef ROM_SDHostDataRead -#define MAP_SDHostDataRead \ - ROM_SDHostDataRead -#else -#define MAP_SDHostDataRead \ - SDHostDataRead -#endif -#ifdef ROM_SDHostSetExpClk -#define MAP_SDHostSetExpClk \ - ROM_SDHostSetExpClk -#else -#define MAP_SDHostSetExpClk \ - SDHostSetExpClk -#endif -#ifdef ROM_SDHostCardErrorMaskSet -#define MAP_SDHostCardErrorMaskSet \ - ROM_SDHostCardErrorMaskSet -#else -#define MAP_SDHostCardErrorMaskSet \ - SDHostCardErrorMaskSet -#endif -#ifdef ROM_SDHostCardErrorMaskGet -#define MAP_SDHostCardErrorMaskGet \ - ROM_SDHostCardErrorMaskGet -#else -#define MAP_SDHostCardErrorMaskGet \ - SDHostCardErrorMaskGet -#endif - -//***************************************************************************** -// -// Macros for the PRCM API. -// -//***************************************************************************** -#ifdef ROM_PRCMMCUReset -#define MAP_PRCMMCUReset \ - ROM_PRCMMCUReset -#else -#define MAP_PRCMMCUReset \ - PRCMMCUReset -#endif -#ifdef ROM_PRCMSysResetCauseGet -#define MAP_PRCMSysResetCauseGet \ - ROM_PRCMSysResetCauseGet -#else -#define MAP_PRCMSysResetCauseGet \ - PRCMSysResetCauseGet -#endif -#ifdef ROM_PRCMPeripheralClkEnable -#define MAP_PRCMPeripheralClkEnable \ - ROM_PRCMPeripheralClkEnable -#else -#define MAP_PRCMPeripheralClkEnable \ - PRCMPeripheralClkEnable -#endif -#ifdef ROM_PRCMPeripheralClkDisable -#define MAP_PRCMPeripheralClkDisable \ - ROM_PRCMPeripheralClkDisable -#else -#define MAP_PRCMPeripheralClkDisable \ - PRCMPeripheralClkDisable -#endif -#ifdef ROM_PRCMPeripheralReset -#define MAP_PRCMPeripheralReset \ - ROM_PRCMPeripheralReset -#else -#define MAP_PRCMPeripheralReset \ - PRCMPeripheralReset -#endif -#ifdef ROM_PRCMPeripheralStatusGet -#define MAP_PRCMPeripheralStatusGet \ - ROM_PRCMPeripheralStatusGet -#else -#define MAP_PRCMPeripheralStatusGet \ - PRCMPeripheralStatusGet -#endif -#ifdef ROM_PRCMI2SClockFreqSet -#define MAP_PRCMI2SClockFreqSet \ - ROM_PRCMI2SClockFreqSet -#else -#define MAP_PRCMI2SClockFreqSet \ - PRCMI2SClockFreqSet -#endif -#ifdef ROM_PRCMPeripheralClockGet -#define MAP_PRCMPeripheralClockGet \ - ROM_PRCMPeripheralClockGet -#else -#define MAP_PRCMPeripheralClockGet \ - PRCMPeripheralClockGet -#endif -#ifdef ROM_PRCMSleepEnter -#define MAP_PRCMSleepEnter \ - ROM_PRCMSleepEnter -#else -#define MAP_PRCMSleepEnter \ - PRCMSleepEnter -#endif -#ifdef ROM_PRCMSRAMRetentionEnable -#define MAP_PRCMSRAMRetentionEnable \ - ROM_PRCMSRAMRetentionEnable -#else -#define MAP_PRCMSRAMRetentionEnable \ - PRCMSRAMRetentionEnable -#endif -#ifdef ROM_PRCMSRAMRetentionDisable -#define MAP_PRCMSRAMRetentionDisable \ - ROM_PRCMSRAMRetentionDisable -#else -#define MAP_PRCMSRAMRetentionDisable \ - PRCMSRAMRetentionDisable -#endif -#ifdef ROM_PRCMLPDSEnter -#define MAP_PRCMLPDSEnter \ - ROM_PRCMLPDSEnter -#else -#define MAP_PRCMLPDSEnter \ - PRCMLPDSEnter -#endif -#ifdef ROM_PRCMLPDSIntervalSet -#define MAP_PRCMLPDSIntervalSet \ - ROM_PRCMLPDSIntervalSet -#else -#define MAP_PRCMLPDSIntervalSet \ - PRCMLPDSIntervalSet -#endif -#ifdef ROM_PRCMLPDSWakeupSourceEnable -#define MAP_PRCMLPDSWakeupSourceEnable \ - ROM_PRCMLPDSWakeupSourceEnable -#else -#define MAP_PRCMLPDSWakeupSourceEnable \ - PRCMLPDSWakeupSourceEnable -#endif -#ifdef ROM_PRCMLPDSWakeupCauseGet -#define MAP_PRCMLPDSWakeupCauseGet \ - ROM_PRCMLPDSWakeupCauseGet -#else -#define MAP_PRCMLPDSWakeupCauseGet \ - PRCMLPDSWakeupCauseGet -#endif -#ifdef ROM_PRCMLPDSWakeUpGPIOSelect -#define MAP_PRCMLPDSWakeUpGPIOSelect \ - ROM_PRCMLPDSWakeUpGPIOSelect -#else -#define MAP_PRCMLPDSWakeUpGPIOSelect \ - PRCMLPDSWakeUpGPIOSelect -#endif -#ifdef ROM_PRCMLPDSWakeupSourceDisable -#define MAP_PRCMLPDSWakeupSourceDisable \ - ROM_PRCMLPDSWakeupSourceDisable -#else -#define MAP_PRCMLPDSWakeupSourceDisable \ - PRCMLPDSWakeupSourceDisable -#endif -#ifdef ROM_PRCMHibernateEnter -#define MAP_PRCMHibernateEnter \ - ROM_PRCMHibernateEnter -#else -#define MAP_PRCMHibernateEnter \ - PRCMHibernateEnter -#endif -#ifdef ROM_PRCMHibernateWakeupSourceEnable -#define MAP_PRCMHibernateWakeupSourceEnable \ - ROM_PRCMHibernateWakeupSourceEnable -#else -#define MAP_PRCMHibernateWakeupSourceEnable \ - PRCMHibernateWakeupSourceEnable -#endif -#ifdef ROM_PRCMHibernateWakeupCauseGet -#define MAP_PRCMHibernateWakeupCauseGet \ - ROM_PRCMHibernateWakeupCauseGet -#else -#define MAP_PRCMHibernateWakeupCauseGet \ - PRCMHibernateWakeupCauseGet -#endif -#ifdef ROM_PRCMHibernateWakeUpGPIOSelect -#define MAP_PRCMHibernateWakeUpGPIOSelect \ - ROM_PRCMHibernateWakeUpGPIOSelect -#else -#define MAP_PRCMHibernateWakeUpGPIOSelect \ - PRCMHibernateWakeUpGPIOSelect -#endif -#ifdef ROM_PRCMHibernateWakeupSourceDisable -#define MAP_PRCMHibernateWakeupSourceDisable \ - ROM_PRCMHibernateWakeupSourceDisable -#else -#define MAP_PRCMHibernateWakeupSourceDisable \ - PRCMHibernateWakeupSourceDisable -#endif -#ifdef ROM_PRCMHibernateIntervalSet -#define MAP_PRCMHibernateIntervalSet \ - ROM_PRCMHibernateIntervalSet -#else -#define MAP_PRCMHibernateIntervalSet \ - PRCMHibernateIntervalSet -#endif -#ifdef ROM_PRCMSlowClkCtrGet -#define MAP_PRCMSlowClkCtrGet \ - ROM_PRCMSlowClkCtrGet -#else -#define MAP_PRCMSlowClkCtrGet \ - PRCMSlowClkCtrGet -#endif -#ifdef ROM_PRCMSlowClkCtrMatchSet -#define MAP_PRCMSlowClkCtrMatchSet \ - ROM_PRCMSlowClkCtrMatchSet -#else -#define MAP_PRCMSlowClkCtrMatchSet \ - PRCMSlowClkCtrMatchSet -#endif -#ifdef ROM_PRCMSlowClkCtrMatchGet -#define MAP_PRCMSlowClkCtrMatchGet \ - ROM_PRCMSlowClkCtrMatchGet -#else -#define MAP_PRCMSlowClkCtrMatchGet \ - PRCMSlowClkCtrMatchGet -#endif -#ifdef ROM_PRCMOCRRegisterWrite -#define MAP_PRCMOCRRegisterWrite \ - ROM_PRCMOCRRegisterWrite -#else -#define MAP_PRCMOCRRegisterWrite \ - PRCMOCRRegisterWrite -#endif -#ifdef ROM_PRCMOCRRegisterRead -#define MAP_PRCMOCRRegisterRead \ - ROM_PRCMOCRRegisterRead -#else -#define MAP_PRCMOCRRegisterRead \ - PRCMOCRRegisterRead -#endif -#ifdef ROM_PRCMIntRegister -#define MAP_PRCMIntRegister \ - ROM_PRCMIntRegister -#else -#define MAP_PRCMIntRegister \ - PRCMIntRegister -#endif -#ifdef ROM_PRCMIntUnregister -#define MAP_PRCMIntUnregister \ - ROM_PRCMIntUnregister -#else -#define MAP_PRCMIntUnregister \ - PRCMIntUnregister -#endif -#ifdef ROM_PRCMIntEnable -#define MAP_PRCMIntEnable \ - ROM_PRCMIntEnable -#else -#define MAP_PRCMIntEnable \ - PRCMIntEnable -#endif -#ifdef ROM_PRCMIntDisable -#define MAP_PRCMIntDisable \ - ROM_PRCMIntDisable -#else -#define MAP_PRCMIntDisable \ - PRCMIntDisable -#endif -#ifdef ROM_PRCMIntStatus -#define MAP_PRCMIntStatus \ - ROM_PRCMIntStatus -#else -#define MAP_PRCMIntStatus \ - PRCMIntStatus -#endif -#ifdef ROM_PRCMRTCInUseSet -#define MAP_PRCMRTCInUseSet \ - ROM_PRCMRTCInUseSet -#else -#define MAP_PRCMRTCInUseSet \ - PRCMRTCInUseSet -#endif -#ifdef ROM_PRCMRTCInUseGet -#define MAP_PRCMRTCInUseGet \ - ROM_PRCMRTCInUseGet -#else -#define MAP_PRCMRTCInUseGet \ - PRCMRTCInUseGet -#endif -#ifdef ROM_PRCMRTCSet -#define MAP_PRCMRTCSet \ - ROM_PRCMRTCSet -#else -#define MAP_PRCMRTCSet \ - PRCMRTCSet -#endif -#ifdef ROM_PRCMRTCGet -#define MAP_PRCMRTCGet \ - ROM_PRCMRTCGet -#else -#define MAP_PRCMRTCGet \ - PRCMRTCGet -#endif -#ifdef ROM_PRCMRTCMatchSet -#define MAP_PRCMRTCMatchSet \ - ROM_PRCMRTCMatchSet -#else -#define MAP_PRCMRTCMatchSet \ - PRCMRTCMatchSet -#endif -#ifdef ROM_PRCMRTCMatchGet -#define MAP_PRCMRTCMatchGet \ - ROM_PRCMRTCMatchGet -#else -#define MAP_PRCMRTCMatchGet \ - PRCMRTCMatchGet -#endif -#ifdef ROM_PRCMLPDSRestoreInfoSet -#define MAP_PRCMLPDSRestoreInfoSet \ - ROM_PRCMLPDSRestoreInfoSet -#else -#define MAP_PRCMLPDSRestoreInfoSet \ - PRCMLPDSRestoreInfoSet -#endif -#ifdef ROM_PRCMSlowClkCtrFastGet -#define MAP_PRCMSlowClkCtrFastGet \ - ROM_PRCMSlowClkCtrFastGet -#else -#define MAP_PRCMSlowClkCtrFastGet \ - PRCMSlowClkCtrFastGet -#endif -#ifdef ROM_PRCMCC3200MCUInit -#define MAP_PRCMCC3200MCUInit \ - ROM_PRCMCC3200MCUInit -#else -#define MAP_PRCMCC3200MCUInit \ - PRCMCC3200MCUInit -#endif -#ifdef ROM_PRCMHIBRegRead -#define MAP_PRCMHIBRegRead \ - ROM_PRCMHIBRegRead -#else -#define MAP_PRCMHIBRegRead \ - PRCMHIBRegRead -#endif -#ifdef ROM_PRCMHIBRegWrite -#define MAP_PRCMHIBRegWrite \ - ROM_PRCMHIBRegWrite -#else -#define MAP_PRCMHIBRegWrite \ - PRCMHIBRegWrite -#endif -#ifdef ROM_PRCMCameraFreqSet -#define MAP_PRCMCameraFreqSet \ - ROM_PRCMCameraFreqSet -#else -#define MAP_PRCMCameraFreqSet \ - PRCMCameraFreqSet -#endif -#ifdef ROM_PRCMIORetentionEnable -#define MAP_PRCMIORetentionEnable \ - ROM_PRCMIORetentionEnable -#else -#define MAP_PRCMIORetentionEnable \ - PRCMIORetentionEnable -#endif -#ifdef ROM_PRCMIORetentionDisable -#define MAP_PRCMIORetentionDisable \ - ROM_PRCMIORetentionDisable -#else -#define MAP_PRCMIORetentionDisable \ - PRCMIORetentionDisable -#endif -#ifdef ROM_PRCMDeviceTypeGet -#define MAP_PRCMDeviceTypeGet \ - ROM_PRCMDeviceTypeGet -#else -#define MAP_PRCMDeviceTypeGet \ - PRCMDeviceTypeGet -#endif -#ifdef ROM_PRCMLPDSEnterKeepDebugIf -#define MAP_PRCMLPDSEnterKeepDebugIf \ - ROM_PRCMLPDSEnterKeepDebugIf -#else -#define MAP_PRCMLPDSEnterKeepDebugIf \ - PRCMLPDSEnterKeepDebugIf -#endif -#ifdef ROM_PRCMHibernateCycleTrigger -#define MAP_PRCMHibernateCycleTrigger \ - ROM_PRCMHibernateCycleTrigger -#else -#define MAP_PRCMHibernateCycleTrigger \ - PRCMHibernateCycleTrigger -#endif - -//***************************************************************************** -// -// Macros for the HWSPINLOCK API. -// -//***************************************************************************** -#ifdef ROM_HwSpinLockAcquire -#define MAP_HwSpinLockAcquire \ - ROM_HwSpinLockAcquire -#else -#define MAP_HwSpinLockAcquire \ - HwSpinLockAcquire -#endif -#ifdef ROM_HwSpinLockTryAcquire -#define MAP_HwSpinLockTryAcquire \ - ROM_HwSpinLockTryAcquire -#else -#define MAP_HwSpinLockTryAcquire \ - HwSpinLockTryAcquire -#endif -#ifdef ROM_HwSpinLockRelease -#define MAP_HwSpinLockRelease \ - ROM_HwSpinLockRelease -#else -#define MAP_HwSpinLockRelease \ - HwSpinLockRelease -#endif -#ifdef ROM_HwSpinLockTest -#define MAP_HwSpinLockTest \ - ROM_HwSpinLockTest -#else -#define MAP_HwSpinLockTest \ - HwSpinLockTest -#endif - -//***************************************************************************** -// -// Macros for the ADC API. -// -//***************************************************************************** -#ifdef ROM_ADCEnable -#define MAP_ADCEnable \ - ROM_ADCEnable -#else -#define MAP_ADCEnable \ - ADCEnable -#endif -#ifdef ROM_ADCDisable -#define MAP_ADCDisable \ - ROM_ADCDisable -#else -#define MAP_ADCDisable \ - ADCDisable -#endif -#ifdef ROM_ADCChannelEnable -#define MAP_ADCChannelEnable \ - ROM_ADCChannelEnable -#else -#define MAP_ADCChannelEnable \ - ADCChannelEnable -#endif -#ifdef ROM_ADCChannelDisable -#define MAP_ADCChannelDisable \ - ROM_ADCChannelDisable -#else -#define MAP_ADCChannelDisable \ - ADCChannelDisable -#endif -#ifdef ROM_ADCIntRegister -#define MAP_ADCIntRegister \ - ROM_ADCIntRegister -#else -#define MAP_ADCIntRegister \ - ADCIntRegister -#endif -#ifdef ROM_ADCIntUnregister -#define MAP_ADCIntUnregister \ - ROM_ADCIntUnregister -#else -#define MAP_ADCIntUnregister \ - ADCIntUnregister -#endif -#ifdef ROM_ADCIntEnable -#define MAP_ADCIntEnable \ - ROM_ADCIntEnable -#else -#define MAP_ADCIntEnable \ - ADCIntEnable -#endif -#ifdef ROM_ADCIntDisable -#define MAP_ADCIntDisable \ - ROM_ADCIntDisable -#else -#define MAP_ADCIntDisable \ - ADCIntDisable -#endif -#ifdef ROM_ADCIntStatus -#define MAP_ADCIntStatus \ - ROM_ADCIntStatus -#else -#define MAP_ADCIntStatus \ - ADCIntStatus -#endif -#ifdef ROM_ADCIntClear -#define MAP_ADCIntClear \ - ROM_ADCIntClear -#else -#define MAP_ADCIntClear \ - ADCIntClear -#endif -#ifdef ROM_ADCDMAEnable -#define MAP_ADCDMAEnable \ - ROM_ADCDMAEnable -#else -#define MAP_ADCDMAEnable \ - ADCDMAEnable -#endif -#ifdef ROM_ADCDMADisable -#define MAP_ADCDMADisable \ - ROM_ADCDMADisable -#else -#define MAP_ADCDMADisable \ - ADCDMADisable -#endif -#ifdef ROM_ADCTimerConfig -#define MAP_ADCTimerConfig \ - ROM_ADCTimerConfig -#else -#define MAP_ADCTimerConfig \ - ADCTimerConfig -#endif -#ifdef ROM_ADCTimerEnable -#define MAP_ADCTimerEnable \ - ROM_ADCTimerEnable -#else -#define MAP_ADCTimerEnable \ - ADCTimerEnable -#endif -#ifdef ROM_ADCTimerDisable -#define MAP_ADCTimerDisable \ - ROM_ADCTimerDisable -#else -#define MAP_ADCTimerDisable \ - ADCTimerDisable -#endif -#ifdef ROM_ADCTimerReset -#define MAP_ADCTimerReset \ - ROM_ADCTimerReset -#else -#define MAP_ADCTimerReset \ - ADCTimerReset -#endif -#ifdef ROM_ADCTimerValueGet -#define MAP_ADCTimerValueGet \ - ROM_ADCTimerValueGet -#else -#define MAP_ADCTimerValueGet \ - ADCTimerValueGet -#endif -#ifdef ROM_ADCFIFOLvlGet -#define MAP_ADCFIFOLvlGet \ - ROM_ADCFIFOLvlGet -#else -#define MAP_ADCFIFOLvlGet \ - ADCFIFOLvlGet -#endif -#ifdef ROM_ADCFIFORead -#define MAP_ADCFIFORead \ - ROM_ADCFIFORead -#else -#define MAP_ADCFIFORead \ - ADCFIFORead -#endif - -//***************************************************************************** -// -// Macros for the CPU API. -// -//***************************************************************************** -#ifdef ROM_CPUcpsid -#define MAP_CPUcpsid \ - ROM_CPUcpsid -#else -#define MAP_CPUcpsid \ - CPUcpsid -#endif -#ifdef ROM_CPUcpsie -#define MAP_CPUcpsie \ - ROM_CPUcpsie -#else -#define MAP_CPUcpsie \ - CPUcpsie -#endif -#ifdef ROM_CPUprimask -#define MAP_CPUprimask \ - ROM_CPUprimask -#else -#define MAP_CPUprimask \ - CPUprimask -#endif -#ifdef ROM_CPUwfi -#define MAP_CPUwfi \ - ROM_CPUwfi -#else -#define MAP_CPUwfi \ - CPUwfi -#endif -#ifdef ROM_CPUbasepriGet -#define MAP_CPUbasepriGet \ - ROM_CPUbasepriGet -#else -#define MAP_CPUbasepriGet \ - CPUbasepriGet -#endif -#ifdef ROM_CPUbasepriSet -#define MAP_CPUbasepriSet \ - ROM_CPUbasepriSet -#else -#define MAP_CPUbasepriSet \ - CPUbasepriSet -#endif - -#endif // __ROM_MAP_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_patch.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_patch.h deleted file mode 100755 index 985c6821152..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_patch.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// rom_patch.h - Macros to facilitate patching driverlib API's in the ROM. -// -// - -//***************************************************************************** -// -// List of API's in the ROM that need to be patched. -// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut -//***************************************************************************** - -#ifndef __ROM_PATCH_H__ -#define __ROM_PATCH_H__ - -#if defined(TARGET_IS_CC3200) || defined(USE_CC3200_ROM_DRV_API) -#undef ROM_ADCIntClear -#undef ROM_IntEnable -#undef ROM_IntDisable -#undef ROM_IntPendSet -#undef ROM_SDHostCardErrorMaskSet -#undef ROM_SDHostCardErrorMaskGet -#undef ROM_TimerConfigure -#undef ROM_TimerDMAEventSet -#undef ROM_TimerDMAEventGet -#undef ROM_SDHostDataNonBlockingWrite -#undef ROM_SDHostDataWrite -#undef ROM_SDHostDataRead -#undef ROM_SDHostDataNonBlockingRead -#undef ROM_PRCMSysResetCauseGet -#undef ROM_PRCMPeripheralClkEnable -#undef ROM_PRCMLPDSWakeUpGPIOSelect -#undef ROM_PRCMHibernateWakeupSourceEnable -#undef ROM_PRCMHibernateWakeupSourceDisable -#undef ROM_PRCMHibernateWakeupCauseGet -#undef ROM_PRCMHibernateIntervalSet -#undef ROM_PRCMHibernateWakeUpGPIOSelect -#undef ROM_PRCMHibernateEnter -#undef ROM_PRCMSlowClkCtrGet -#undef ROM_PRCMSlowClkCtrMatchSet -#undef ROM_PRCMSlowClkCtrMatchGet -#undef ROM_PRCMOCRRegisterWrite -#undef ROM_PRCMOCRRegisterRead -#undef ROM_PRCMIntEnable -#undef ROM_PRCMIntDisable -#undef ROM_PRCMRTCInUseSet -#undef ROM_PRCMRTCInUseGet -#undef ROM_PRCMRTCSet -#undef ROM_PRCMRTCGet -#undef ROM_PRCMRTCMatchSet -#undef ROM_PRCMRTCMatchGet -#undef ROM_PRCMPeripheralClkDisable -#undef ROM_PRCMPeripheralReset -#undef ROM_PRCMPeripheralStatusGet -#undef ROM_SPIConfigSetExpClk -#undef ROM_AESDataProcess -#undef ROM_DESDataProcess -#undef ROM_I2SEnable -#undef ROM_I2SConfigSetExpClk -#undef ROM_PinConfigSet -#undef ROM_PRCMLPDSEnter -#undef ROM_PRCMCC3200MCUInit -#undef ROM_SDHostIntStatus -#undef ROM_SDHostBlockCountSet -#undef ROM_UARTModemControlSet -#undef ROM_UARTModemControlClear -#undef ROM_CameraXClkSet -#undef ROM_PRCMMCUReset -#undef ROM_PRCMPeripheralClkEnable -#undef ROM_SPIDmaDisable -#endif - -#if defined(USE_CC3220_ROM_DRV_API) -#undef ROM_PRCMDeviceTypeGet -#undef ROM_SDHostDataNonBlockingRead -#undef ROM_PRCMIORetentionEnable -#undef ROM_PRCMIORetentionDisable -#undef ROM_PRCMCC3200MCUInit -#undef ROM_SHAMD5ConfigSet -#undef ROM_SHAMD5HMACKeySet -#endif - -#endif // __ROM_PATCH_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.c deleted file mode 100755 index 722f46285b7..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.c +++ /dev/null @@ -1,745 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// sdhost.c -// -// Driver for the SD Host (SDHost) Interface -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup Secure_Digital_Host_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_mmchs.h" -#include "inc/hw_ints.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "sdhost.h" - - -//***************************************************************************** -// -//! Configures SDHost module. -//! -//! \param ulBase is the base address of SDHost module. -//! -//! This function configures the SDHost module, enabling internal sub-modules. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostInit(unsigned long ulBase) -{ - // - // Assert module reset - // - HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2; - - // - // Wait for soft reset to complete - // - while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) ) - { - - } - - // - // Assert internal reset - // - HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24); - - // - // Wait for Reset to complete - // - while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) ) - { - - } - - // - // Set capability register, 1.8 and 3.0 V - // - HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24); - - // - // Select bus voltage, 3.0 V - // - HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9; - - // - // Power up the bus - // - HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8; - - // - // Wait for power on - // - while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) ) - { - - } - - HWREG(ulBase + MMCHS_O_CON) |= 1 << 21; - - // - // Un-mask all events - // - HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF; -} - - -//***************************************************************************** -// -//! Resets SDHost command line -//! -//! \param ulBase is the base address of SDHost module. -//! -//! This function assers a soft reset for the command line -//! -//! \return None. -// -//***************************************************************************** -void -SDHostCmdReset(unsigned long ulBase) -{ - HWREG(ulBase + MMCHS_O_SYSCTL) |= 1 << 25; - while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (1 << 25)) ) - { - - } -} - -//***************************************************************************** -// -//! Sends command over SDHost interface -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulCmd is the command to send. -//! \param ulArg is the argument for the command. -//! -//! This function send command to the attached card over the SDHost interface. -//! -//! The \e ulCmd parameter can be one of \b SDHOST_CMD_0 to \b SDHOST_CMD_63. -//! It can be logically ORed with one or more of the following: -//! - \b SDHOST_MULTI_BLK for multi-block transfer -//! - \b SDHOST_WR_CMD if command is followed by write data -//! - \b SDHOST_RD_CMD if command is followed by read data -//! - \b SDHOST_DMA_EN if SDHost need to generate DMA request. -//! - \b SDHOST_RESP_LEN_136 if 136 bit response is expected -//! - \b SDHOST_RESP_LEN_48 if 48 bit response is expected -//! - \b SDHOST_RESP_LEN_48B if 48 bit response with busy bit is expected -//! -//! The parameter \e ulArg is the argument for the command -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -long -SDHostCmdSend(unsigned long ulBase, unsigned long ulCmd, unsigned ulArg) -{ - // - // Set Data Timeout - // - HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x000E0000; - - // - // Check for cmd inhabit - // - if( (HWREG(ulBase + MMCHS_O_PSTATE) & 0x1)) - { - return -1; - } - - // - // Set the argument - // - HWREG(ulBase + MMCHS_O_ARG) = ulArg; - - // - // Send the command - // - HWREG(ulBase + MMCHS_O_CMD) = ulCmd; - - return 0; -} - -//***************************************************************************** -// -//! Writes a data word into the SDHost write buffer. -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulData is data word to be transfered. -//! -//! This function writes a single data word into the SDHost write buffer. The -//! function returns \b true if there was a space available in the buffer else -//! returns \b false. -//! -//! \return Return \b true on success, \b false otherwise. -// -//***************************************************************************** -tBoolean -SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData) -{ - - // - // See if there is a space in the write buffer - // - if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) ) - { - // - // Write the data into the buffer - // - HWREG(ulBase + MMCHS_O_DATA) = ulData; - - // - // Success. - // - return(true); - } - else - { - // - // No free sapce, failure. - // - return(false); - } -} - -//***************************************************************************** -// -//! Waits to write a data word into the SDHost write buffer. -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulData is data word to be transfered. -//! -//! This function writes \e ulData into the SDHost write buffer. If there is no -//! space in the write buffer this function waits until there is a space -//! available before returning. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostDataWrite(unsigned long ulBase, unsigned long ulData) -{ - // - // Wait until space is available - // - while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) ) - { - - } - - // - // Write the data - // - HWREG(ulBase + MMCHS_O_DATA) = ulData; -} - - -//***************************************************************************** -// -//! Waits for a data word from the SDHost read buffer -//! -//! \param ulBase is the base address of SDHost module. -//! \param pulData is pointer to read data variable. -//! -//! This function reads a single data word from the SDHost read buffer. If there -//! is no data available in the buffer the function will wait until a data -//! word is received before returning. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostDataRead(unsigned long ulBase, unsigned long *pulData) -{ - // - // Wait until data is available - // - while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) ) - { - - } - - // - // Read the data - // - *pulData = HWREG(ulBase + MMCHS_O_DATA); -} - -//***************************************************************************** -// -//! Reads single data word from the SDHost read buffer -//! -//! \param ulBase is the base address of SDHost module. -//! \param pulData is pointer to read data variable. -//! -//! This function reads a data word from the SDHost read buffer. The -//! function returns \b true if there was data available in to buffer else -//! returns \b false. -//! -//! \return Return \b true on success, \b false otherwise. -// -//***************************************************************************** -tBoolean -SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData) -{ - - // - // See if there is any data in the read buffer. - // - if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) ) - { - // - // Read the data word. - // - *pulData = HWREG(ulBase + MMCHS_O_DATA); - - // - // Success - // - return(true); - } - else - { - // - // No data available, failure. - // - return(false); - } -} - - -//***************************************************************************** -// -//! Registers the interrupt handler for SDHost interrupt -//! -//! \param ulBase is the base address of SDHost module -//! \param pfnHandler is a pointer to the function to be called when the -//! SDHost interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! SDHost interrupts must be enabled via SDHostIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler. - // - IntRegister(INT_MMCHS, pfnHandler); - - // - // Enable the SDHost interrupt. - // - IntEnable(INT_MMCHS); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for SDHost interrupt -//! -//! \param ulBase is the base address of SDHost module -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a SDHost interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntUnregister(unsigned long ulBase) -{ - // - // Disable the SDHost interrupt. - // - IntDisable(INT_MMCHS); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_MMCHS); -} - -//***************************************************************************** -// -//! Enable individual interrupt source for the specified SDHost -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated SDHost interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! - \b SDHOST_INT_CC Command Complete interrupt -//! - \b SDHOST_INT_TC Transfer Complete interrupt -//! - \b SDHOST_INT_BWR Buffer Write Ready interrupt -//! - \b SDHOST_INT_BRR Buffer Read Ready interrupt -//! - \b SDHOST_INT_ERRI Error interrupt -//! - \b SDHOST_INT_CTO Command Timeout error interrupt -//! - \b SDHOST_INT_CEB Command End Bit error interrupt -//! - \b SDHOST_INT_DTO Data Timeout error interrupt -//! - \b SDHOST_INT_DCRC Data CRC error interrupt -//! - \b SDHOST_INT_DEB Data End Bit error -//! - \b SDHOST_INT_CERR Cart Status Error interrupt -//! - \b SDHOST_INT_BADA Bad Data error interrupt -//! - \b SDHOST_INT_DMARD Read DMA done interrupt -//! - \b SDHOST_INT_DMAWR Write DMA done interrupt -//! -//! Note that SDHOST_INT_ERRI can only be used with \sa SDHostIntStatus() -//! and is internally logical OR of all error status bits. Setting this bit -//! alone as \e ulIntFlags doesn't generates any interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags) -{ - // - // Enable DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = - (ulIntFlags >> 30); - - // - // Enable the individual interrupt sources - // - HWREG(ulBase + MMCHS_O_ISE) |= (ulIntFlags & 0x3FFFFFFF); -} - -//***************************************************************************** -// -//! Enable individual interrupt source for the specified SDHost -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function disables the indicated SDHost interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to SDHostIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags) -{ - // - // Disable DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = - (ulIntFlags >> 30); - // - // Disable the individual interrupt sources - // - HWREG(ulBase + MMCHS_O_ISE) &= ~(ulIntFlags & 0x3FFFFFFF); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of SDHost module. -//! -//! This function returns the interrupt status for the specified SDHost. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in SDHostIntEnable(). -// -//***************************************************************************** -unsigned long -SDHostIntStatus(unsigned long ulBase) -{ - unsigned long ulIntStatus; - - // - // Get DMA done interrupt status - // - ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW); - ulIntStatus = (ulIntStatus << 30); - - // - // Return the status of individual interrupt sources - // - ulIntStatus |= (HWREG(ulBase + MMCHS_O_STAT) & 0x3FFFFFFF); - - return(ulIntStatus); -} - -//***************************************************************************** -// -//! Clears the individual interrupt sources. -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified SDHost interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to SDHostIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags) -{ - // - // Clear DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = - (ulIntFlags >> 30); - // - // Clear the individual interrupt sources - // - HWREG(ulBase + MMCHS_O_STAT) = (ulIntFlags & 0x3FFFFFFF); -} - -//***************************************************************************** -// -//! Sets the card status error mask. -//! -//! \param ulBase is the base address of SDHost module -//! \param ulErrMask is the bit mask of card status errors to be enabled -//! -//! This function sets the card status error mask for response type R1, R1b, -//! R5, R5b and R6 response. The parameter \e ulErrMask is the bit mask of card -//! status errors to be enabled, if the corresponding bits in the 'card status' -//! field of a respose are set then the host controller indicates a card error -//! interrupt status. Only bits referenced as type E (error) in status field in -//! the response can set a card status error. -//! -//! \return None -// -//***************************************************************************** -void -SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask) -{ - // - // Set the card status error mask - // - HWREG(ulBase + MMCHS_O_CSRE) = ulErrMask; -} - - -//***************************************************************************** -// -//! Gets the card status error mask. -//! -//! \param ulBase is the base address of SDHost module -//! -//! This function gets the card status error mask for response type R1, R1b, -//! R5, R5b and R6 response. -//! -//! \return Returns the current card status error. -// -//***************************************************************************** -unsigned long -SDHostCardErrorMaskGet(unsigned long ulBase) -{ - // - // Return the card status error mask - // - return(HWREG(ulBase + MMCHS_O_CSRE)); -} - -//***************************************************************************** -// -//! Sets the SD Card clock. -//! -//! \param ulBase is the base address of SDHost module -//! \param ulSDHostClk is the rate of clock supplied to SDHost module -//! \param ulCardClk is the required SD interface clock -//! -//! This function configures the SDHost interface to supply the specified clock -//! to the connected card. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, - unsigned long ulCardClk) -{ - unsigned long ulDiv; - - // - // Disable card clock - // - HWREG(ulBase + MMCHS_O_SYSCTL) &= ~0x4; - - // - // Enable internal clock - // - HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x1; - - ulDiv = ((ulSDHostClk/ulCardClk) & 0x3FF); - - // - // Set clock divider, - // - HWREG(ulBase + MMCHS_O_SYSCTL) = ((HWREG(ulBase + MMCHS_O_SYSCTL) & - ~0x0000FFC0)| (ulDiv) << 6); - - // - // Wait for clock to stablize - // - while( !(HWREG(ulBase + MMCHS_O_SYSCTL) & 0x2) ) - { - - } - - // - // Enable card clock - // - HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x4; -} - -//***************************************************************************** -// -//! Get the response for the last command. -//! -//! \param ulBase is the base address of SDHost module -//! \param ulRespnse is 128-bit response. -//! -//! This function gets the response from the SD card for the last command -//! send. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]) -{ - - // - // Read the responses. - // - ulRespnse[0] = HWREG(ulBase + MMCHS_O_RSP10); - ulRespnse[1] = HWREG(ulBase + MMCHS_O_RSP32); - ulRespnse[2] = HWREG(ulBase + MMCHS_O_RSP54); - ulRespnse[3] = HWREG(ulBase + MMCHS_O_RSP76); - -} - -//***************************************************************************** -// -//! Set the block size for data transfer -//! -//! \param ulBase is the base address of SDHost module -//! \param ulBlkSize is the transfer block size in bytes -//! -//! This function sets the block size the data transfer. -//! -//! The parameter \e ulBlkSize is size of each data block in bytes. -//! This should be in range 0 - 2^10. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize) -{ - // - // Set the block size - // - HWREG(ulBase + MMCHS_O_BLK) = ((HWREG(ulBase + MMCHS_O_BLK) & 0x00000FFF)| - (ulBlkSize & 0xFFF)); -} - -//***************************************************************************** -// -//! Set the block size and count for data transfer -//! -//! \param ulBase is the base address of SDHost module -//! \param ulBlkCount is the number of blocks -//! -//! This function sets block count for the data transfer. This needs to be set -//! for each block transfer. \sa SDHostBlockSizeSet() -//! -//! \return None. -// -//***************************************************************************** -void -SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount) -{ - unsigned long ulRegVal; - - // - // Read the current value - // - ulRegVal = HWREG(ulBase + MMCHS_O_BLK); - - // - // Set the number of blocks - // - HWREG(ulBase + MMCHS_O_BLK) = ((ulRegVal & 0x0000FFFF)| - (ulBlkCount << 16)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.h deleted file mode 100755 index 456f95865fe..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// sdhost.h -// -// Defines and Macros for the SDHost. -// -//***************************************************************************** - -#ifndef __SDHOST_H__ -#define __SDHOST_H__ - - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -//{ -#endif - - -//***************************************************************************** -// Values that can be passed to SDHostRespGet(). -//***************************************************************************** -#define SDHOST_RESP_10 0x00000003 -#define SDHOST_RESP_32 0x00000002 -#define SDHOST_RESP_54 0x00000001 -#define SDHOST_RESP_76 0x00000000 - - -//***************************************************************************** -// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(), -// SDHostIntClear() ,and returned from SDHostIntStatus(). -//***************************************************************************** -#define SDHOST_INT_CC 0x00000001 -#define SDHOST_INT_TC 0x00000002 -#define SDHOST_INT_BWR 0x00000010 -#define SDHOST_INT_BRR 0x00000020 -#define SDHOST_INT_ERRI 0x00008000 -#define SDHOST_INT_CTO 0x00010000 -#define SDHOST_INT_CEB 0x00040000 -#define SDHOST_INT_DTO 0x00100000 -#define SDHOST_INT_DCRC 0x00200000 -#define SDHOST_INT_DEB 0x00400000 -#define SDHOST_INT_CERR 0x10000000 -#define SDHOST_INT_BADA 0x20000000 -#define SDHOST_INT_DMARD 0x40000000 -#define SDHOST_INT_DMAWR 0x80000000 - -//***************************************************************************** -// Values that can be passed to SDHostCmdSend(). -//***************************************************************************** -#define SDHOST_CMD_0 0x00000000 -#define SDHOST_CMD_1 0x01000000 -#define SDHOST_CMD_2 0x02000000 -#define SDHOST_CMD_3 0x03000000 -#define SDHOST_CMD_4 0x04000000 -#define SDHOST_CMD_5 0x05000000 -#define SDHOST_CMD_6 0x06000000 -#define SDHOST_CMD_7 0x07000000 -#define SDHOST_CMD_8 0x08000000 -#define SDHOST_CMD_9 0x09000000 -#define SDHOST_CMD_10 0x0A000000 -#define SDHOST_CMD_11 0x0B000000 -#define SDHOST_CMD_12 0x0C000000 -#define SDHOST_CMD_13 0x0D000000 -#define SDHOST_CMD_14 0x0E000000 -#define SDHOST_CMD_15 0x0F000000 -#define SDHOST_CMD_16 0x10000000 -#define SDHOST_CMD_17 0x11000000 -#define SDHOST_CMD_18 0x12000000 -#define SDHOST_CMD_19 0x13000000 -#define SDHOST_CMD_20 0x14000000 -#define SDHOST_CMD_21 0x15000000 -#define SDHOST_CMD_22 0x16000000 -#define SDHOST_CMD_23 0x17000000 -#define SDHOST_CMD_24 0x18000000 -#define SDHOST_CMD_25 0x19000000 -#define SDHOST_CMD_26 0x1A000000 -#define SDHOST_CMD_27 0x1B000000 -#define SDHOST_CMD_28 0x1C000000 -#define SDHOST_CMD_29 0x1D000000 -#define SDHOST_CMD_30 0x1E000000 -#define SDHOST_CMD_31 0x1F000000 -#define SDHOST_CMD_32 0x20000000 -#define SDHOST_CMD_33 0x21000000 -#define SDHOST_CMD_34 0x22000000 -#define SDHOST_CMD_35 0x23000000 -#define SDHOST_CMD_36 0x24000000 -#define SDHOST_CMD_37 0x25000000 -#define SDHOST_CMD_38 0x26000000 -#define SDHOST_CMD_39 0x27000000 -#define SDHOST_CMD_40 0x28000000 -#define SDHOST_CMD_41 0x29000000 -#define SDHOST_CMD_42 0x2A000000 -#define SDHOST_CMD_43 0x2B000000 -#define SDHOST_CMD_44 0x2C000000 -#define SDHOST_CMD_45 0x2D000000 -#define SDHOST_CMD_46 0x2E000000 -#define SDHOST_CMD_47 0x2F000000 -#define SDHOST_CMD_48 0x30000000 -#define SDHOST_CMD_49 0x31000000 -#define SDHOST_CMD_50 0x32000000 -#define SDHOST_CMD_51 0x33000000 -#define SDHOST_CMD_52 0x34000000 -#define SDHOST_CMD_53 0x35000000 -#define SDHOST_CMD_54 0x36000000 -#define SDHOST_CMD_55 0x37000000 -#define SDHOST_CMD_56 0x38000000 -#define SDHOST_CMD_57 0x39000000 -#define SDHOST_CMD_58 0x3A000000 -#define SDHOST_CMD_59 0x3B000000 -#define SDHOST_CMD_60 0x3C000000 -#define SDHOST_CMD_61 0x3D000000 -#define SDHOST_CMD_62 0x3E000000 -#define SDHOST_CMD_63 0x3F000000 - -//***************************************************************************** -// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend(). -//***************************************************************************** -#define SDHOST_MULTI_BLK 0x00000022 -#define SDHOST_DMA_EN 0x00000001 -#define SDHOST_WR_CMD 0x00200000 -#define SDHOST_RD_CMD 0x00200010 -#define SDHOST_RESP_LEN_136 0x00010000 -#define SDHOST_RESP_LEN_48 0x00020000 -#define SDHOST_RESP_LEN_48B 0x00030000 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void SDHostCmdReset(unsigned long ulBase); -extern void SDHostInit(unsigned long ulBase); -extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd, - unsigned ulArg); -extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void SDHostIntUnregister(unsigned long ulBase); -extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags); -extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags); -extern unsigned long SDHostIntStatus(unsigned long ulBase); -extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags); -extern void SDHostCardErrorMaskSet(unsigned long ulBase, - unsigned long ulErrMask); -extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase); -extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, - unsigned long ulCardClk); -extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]); -extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize); -extern void SDHostBlockCountSet(unsigned long ulBase, - unsigned short ulBlkCount); -extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase, - unsigned long ulData); -extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase, - unsigned long *pulData); -extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData); -extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -//} -#endif - -#endif // __SDHOST_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.c deleted file mode 100755 index bf0b20621ed..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.c +++ /dev/null @@ -1,1249 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// shamd5.c -// -// Driver for the SHA/MD5 module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup SHA_Secure_Hash_Algorithm_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_dthe.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_nvic.h" -#include "inc/hw_shamd5.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/shamd5.h" - -//***************************************************************************** -// -//! Enables the uDMA requests in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function configures the DMA options of the SHA/MD5 module. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DMAEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the new configuration into the register. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= - SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN; -} - -//***************************************************************************** -// -//! Disables the uDMA requests in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function configures the DMA options of the SHA/MD5 module. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DMADisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the new configuration into the register. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= - ~(SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN); -} - -//***************************************************************************** -// -//! Get the interrupt status of the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the current value of the IRQSTATUS register. The -//! value will be a logical OR of the following: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return Interrupt status -// -//***************************************************************************** -uint32_t -SHAMD5IntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Temp; - uint32_t ui32IrqEnable; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Return the value of the IRQSTATUS register. - // - if(bMasked) - { - ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_MIS); - ui32IrqEnable = HWREG(ui32Base + SHAMD5_O_IRQENABLE); - return((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & - ui32IrqEnable) | (ui32Temp & 0x00000007) << 16); - } - else - { - ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_RIS); - return(HWREG(ui32Base + SHAMD5_O_IRQSTATUS) | - (ui32Temp & 0x00000007) << 16); - - } -} - -//***************************************************************************** -// -//! Enable interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to enable. -//! -//! This function enables interrupt sources in the SHA/MD5 module. -//! ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Enable the interrupt sources. - // - HWREG(DTHE_BASE + DTHE_O_SHA_IM) &= ~((ui32IntFlags & 0x00070000) >> 16); - HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; - - // - // Enable all interrupts. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_PIT_EN; -} - -//***************************************************************************** -// -//! Disable interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to disable. -//! -//! \e ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Clear the corresponding flags disabling the interrupt sources. - // - HWREG(DTHE_BASE + DTHE_O_SHA_IM) |= ((ui32IntFlags & 0x00070000) >> 16); - HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); - - // - // If there are no interrupts enabled, then disable all interrupts. - // - if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0) - { - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_PIT_EN; - } -} - -//***************************************************************************** -// -//! Clears interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to disable. -//! -//! \e ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Clear the corresponding flags disabling the interrupt sources. - // - HWREG(DTHE_BASE + DTHE_O_SHA_IC) = ((ui32IntFlags & 0x00070000) >> 16); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled SHA/MD5 interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables SHA/MD5 interrupts on the interrupt controller; -//! specific SHA/MD5 interrupt sources must be enabled using -//! SHAMD5IntEnable(). The interrupt handler being registered must clear -//! the source of the interrupt using SHAMD5IntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_SHA, pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_SHA); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_SHA); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SHA); -} - -//***************************************************************************** -// -//! Write the hash length to the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32Length is the hash length in bytes. -//! -//! This function writes the length of the hash data of the current operation -//! to the SHA/MD5 module. The value must be a multiple of 64 if the close -//! hash is not set in the mode register. -//! -//! \note When this register is written, hash processing is triggered. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Set the LENGTH register and start processing. - // - HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Writes the mode in the SHA/MD5 module. -//! Sets the request value to SHAMD5_O_MODE register. -//! Each parameter defines one of the bit fields in the SHAMD5_O_MODE register. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32CryptoMode sets the hash algorithm to be used. -//! \param algConstFlag sets the requested value to -//! SHAMD5_MODE_ALGO_CONSTANT bit field. -//! \param closeHashFlag sets the requested value to -//! SHAMD5_MODE_CLOSE_HASH bit field. -//! \param HMACKeyFlag sets the requested value to -//! SHAMD5_MODE_HMAC_KEY_PROC bit field. -//! \param HMACOuterHashFlag sets the requested value to -//! SHAMD5_MODE_HMAC_OUTER_HASH bit field. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32CryptoMode, uint8_t algConstFlag, uint8_t closeHashFlag, - uint8_t HMACKeyFlag, uint8_t HMACOuterHashFlag) -{ - uint32_t RegData = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32CryptoMode == SHAMD5_ALGO_MD5) || - (ui32CryptoMode == SHAMD5_ALGO_SHA1) || - (ui32CryptoMode == SHAMD5_ALGO_SHA224) || - (ui32CryptoMode == SHAMD5_ALGO_SHA256)); - - RegData = (uint32_t)( ui32CryptoMode | ((algConstFlag&0x1)< 0) && (ulPeriod <= 16777216)); - - // - // Set the period of the SysTick counter. - // - HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; -} - -//***************************************************************************** -// -//! Gets the period of the SysTick counter. -//! -//! This function returns the rate at which the SysTick counter wraps, which -//! equates to the number of processor clocks between interrupts. -//! -//! \return Returns the period of the SysTick counter. -// -//***************************************************************************** -unsigned long -SysTickPeriodGet(void) -{ - // - // Return the period of the SysTick counter. - // - return(HWREG(NVIC_ST_RELOAD) + 1); -} - -//***************************************************************************** -// -//! Gets the current value of the SysTick counter. -//! -//! This function returns the current value of the SysTick counter, which is -//! a value between the period - 1 and zero, inclusive. -//! -//! \return Returns the current value of the SysTick counter. -// -//***************************************************************************** -unsigned long -SysTickValueGet(void) -{ - // - // Return the current value of the SysTick counter. - // - return(HWREG(NVIC_ST_CURRENT)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/systick.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/systick.h deleted file mode 100755 index b09e26e4099..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/systick.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// systick.h -// -// Prototypes for the SysTick driver. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.c deleted file mode 100755 index ecd02a30b76..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.c +++ /dev/null @@ -1,1361 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// aes.c -// -// Driver for the AES module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup AES_Advanced_Encryption_Standard_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_aes.h" -#include "inc/hw_dthe.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "ti_aes.h" -#include "debug.h" -#include "interrupt.h" - -#define AES_BLOCK_SIZE_IN_BYTES 16 - -//***************************************************************************** -// -//! Configures the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Config is the configuration of the AES module. -//! -//! This function configures the AES module based on the specified parameters. -//! It does not change any DMA- or interrupt-related parameters. -//! -//! The ui32Config parameter is a bit-wise OR of a number of configuration -//! flags. The valid flags are grouped based on their function. -//! -//! The direction of the operation is specified with only of following flags: -//! -//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode -//! - \b AES_CFG_DIR_DECRYPT - Decryption mode -//! -//! The key size is specified with only one of the following flags: -//! -//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits -//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits -//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits -//! -//! The mode of operation is specified with only one of the following flags. -//! -//! - \b AES_CFG_MODE_ECB - Electronic codebook mode -//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode -//! - \b AES_CFG_MODE_CFB - Cipher feedback mode -//! - \b AES_CFG_MODE_CTR - Counter mode -//! - \b AES_CFG_MODE_ICM - Integer counter mode -//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode -//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with -//! ciphertext stealing with previous/intermediate tweak value and j loaded -//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with -//! ciphertext stealing with key2, i and j loaded -//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with -//! ciphertext stealing with key2 and i loaded, j = 0 -//! - \b AES_CFG_MODE_F8 - F8 mode -//! - \b AES_CFG_MODE_F9 - F9 mode -//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication -//! code mode -//! - \b AES_CFG_MODE_GCM - Galois/counter mode -//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H -//! loaded and Y0-encrypted forced to zero -//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H -//! loaded and Y0-encrypted calculated internally -//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH -//! (both H and Y0-encrypted calculated internally) -//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode -//! -//! The following defines are used to specify the counter width. It is only -//! required to be defined when using CTR, CCM, or GCM modes, only one of the -//! following defines must be used to specify the counter width length: -//! -//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits -//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits -//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits -//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits -//! -//! Only one of the following defines must be used to specify the length field -//! for CCM operations (L): -//! -//! - \b AES_CFG_CCM_L_2 - 2 bytes -//! - \b AES_CFG_CCM_L_4 - 4 bytes -//! - \b AES_CFG_CCM_L_8 - 8 bytes -//! -//! Only one of the following defines must be used to specify the length of the -//! authentication field for CCM operations (M) through the \e ui32Config -//! argument in the AESConfigSet() function: -//! -//! - \b AES_CFG_CCM_M_4 - 4 bytes -//! - \b AES_CFG_CCM_M_6 - 6 bytes -//! - \b AES_CFG_CCM_M_8 - 8 bytes -//! - \b AES_CFG_CCM_M_10 - 10 bytes -//! - \b AES_CFG_CCM_M_12 - 12 bytes -//! - \b AES_CFG_CCM_M_14 - 14 bytes -//! - \b AES_CFG_CCM_M_16 - 16 bytes -//! -//! \return None. -// -//***************************************************************************** -void -AESConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) || - (ui32Config & AES_CFG_DIR_DECRYPT)); - ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) || - (ui32Config & AES_CFG_KEY_SIZE_192BIT) || - (ui32Config & AES_CFG_KEY_SIZE_256BIT)); - ASSERT((ui32Config & AES_CFG_MODE_ECB) || - (ui32Config & AES_CFG_MODE_CBC) || - (ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_ICM) || - (ui32Config & AES_CFG_MODE_CFB) || - (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) || - (ui32Config & AES_CFG_MODE_XTS_K2IJL) || - (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) || - (ui32Config & AES_CFG_MODE_F8) || - (ui32Config & AES_CFG_MODE_F9) || - (ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_CBCMAC) || - (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || - (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || - (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || - (ui32Config & AES_CFG_MODE_CCM)); - ASSERT(((ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || - (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || - (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || - (ui32Config & AES_CFG_MODE_CCM)) && - ((ui32Config & AES_CFG_CTR_WIDTH_32) || - (ui32Config & AES_CFG_CTR_WIDTH_64) || - (ui32Config & AES_CFG_CTR_WIDTH_96) || - (ui32Config & AES_CFG_CTR_WIDTH_128))); - ASSERT((ui32Config & AES_CFG_MODE_CCM) && - ((ui32Config & AES_CFG_CCM_L_2) || - (ui32Config & AES_CFG_CCM_L_4) || - (ui32Config & AES_CFG_CCM_L_8)) && - ((ui32Config & AES_CFG_CCM_M_4) || - (ui32Config & AES_CFG_CCM_M_6) || - (ui32Config & AES_CFG_CCM_M_8) || - (ui32Config & AES_CFG_CCM_M_10) || - (ui32Config & AES_CFG_CCM_M_12) || - (ui32Config & AES_CFG_CCM_M_14) || - (ui32Config & AES_CFG_CCM_M_16))); - - // - // Backup the save context field before updating the register. - // - if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT) - { - ui32Config |= AES_CTRL_SAVE_CONTEXT; - } - - // - // Write the CTRL register with the new value - // - HWREG(ui32Base + AES_O_CTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Writes the key 1 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui8Key is an array of bytes, containing the key to be -//! configured. The least significant word in the 0th index. -//! \param ui32Keysize is the size of the key, which must be one of the -//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or -//! \b AES_CFG_KEY_SIZE_256. -//! -//! This function writes key 1 configuration registers based on the key -//! size. This function is used in all modes. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); - - // - // With all key sizes, the first 4 words are written. - // - HWREG(ui32Base + AES_O_KEY1_0) = * ((uint32_t *)(pui8Key + 0)); - HWREG(ui32Base + AES_O_KEY1_1) = * ((uint32_t *)(pui8Key + 4)); - HWREG(ui32Base + AES_O_KEY1_2) = * ((uint32_t *)(pui8Key + 8)); - HWREG(ui32Base + AES_O_KEY1_3) = * ((uint32_t *)(pui8Key + 12)); - - // - // The key is 192 or 256 bits. Write the next 2 words. - // - if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) - { - HWREG(ui32Base + AES_O_KEY1_4) = * ((uint32_t *)(pui8Key + 16)); - HWREG(ui32Base + AES_O_KEY1_5) = * ((uint32_t *)(pui8Key + 20)); - } - - // - // The key is 256 bits. Write the last 2 words. - // - if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) - { - HWREG(ui32Base + AES_O_KEY1_6) = * ((uint32_t *)(pui8Key + 24)); - HWREG(ui32Base + AES_O_KEY1_7) = * ((uint32_t *)(pui8Key + 28)); - } -} - -//***************************************************************************** -// -//! Writes the key 2 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui8Key is an array of bytes, containing the key to be -//! configured. The least significant word in the 0th index. -//! \param ui32Keysize is the size of the key, which must be one of the -//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or -//! \b AES_CFG_KEY_SIZE_256. -//! -//! This function writes the key 2 configuration registers based on the key -//! size. This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); - - // - // With all key sizes, the first 4 words are written. - // - HWREG(ui32Base + AES_O_KEY2_0) = * ((uint32_t *)(pui8Key + 0)); - HWREG(ui32Base + AES_O_KEY2_1) = * ((uint32_t *)(pui8Key + 4)); - HWREG(ui32Base + AES_O_KEY2_2) = * ((uint32_t *)(pui8Key + 8)); - HWREG(ui32Base + AES_O_KEY2_3) = * ((uint32_t *)(pui8Key + 12)); - - // - // The key is 192 or 256 bits. Write the next 2 words. - // - if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) - { - HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 16)); - HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 20)); - } - - // - // The key is 256 bits. Write the last 2 words. - // - if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) - { - HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 24)); - HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 28)); - } -} - -//***************************************************************************** -// -//! Writes key 3 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui8Key is a pointer to an array bytes, containing -//! the key to be configured. The least significant word is in the 0th index. -//! -//! This function writes the key 2 configuration registers with key 3 data -//! used in CBC-MAC and F8 modes. This key is always 128 bits. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the key into the upper 4 key registers - // - HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 0)); - HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 4)); - HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 8)); - HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 12)); -} - -//***************************************************************************** -// -//! Writes the Initial Vector (IV) register, needed in some of the AES Modes. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8IVdata is an array of 16 bytes (128 bits), containing the IV -//! value to be configured. The least significant word is in the 0th index. -//! -//! This functions writes the initial vector registers in the AES module. -//! -//! \return None. -// -//***************************************************************************** -void -AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the initial vector registers. - // - HWREG(ui32Base + AES_O_IV_IN_0) = *((uint32_t *)(pui8IVdata+0)); - HWREG(ui32Base + AES_O_IV_IN_1) = *((uint32_t *)(pui8IVdata+4)); - HWREG(ui32Base + AES_O_IV_IN_2) = *((uint32_t *)(pui8IVdata+8)); - HWREG(ui32Base + AES_O_IV_IN_3) = *((uint32_t *)(pui8IVdata+12)); -} - - -//***************************************************************************** -// -//! Reads the Initial Vector (IV) register, needed in some of the AES Modes. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8IVdata is pointer to an array of 16 bytes. -//! -//! This functions reads the initial vector registers in the AES module. -//! -//! \return None. -// -//***************************************************************************** -void -AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the initial vector registers. - // - *((uint32_t *)(pui8IVdata+ 0)) = HWREG(ui32Base + AES_O_IV_IN_0); - *((uint32_t *)(pui8IVdata+ 4)) = HWREG(ui32Base + AES_O_IV_IN_1); - *((uint32_t *)(pui8IVdata+ 8)) = HWREG(ui32Base + AES_O_IV_IN_2); - *((uint32_t *)(pui8IVdata+12)) = HWREG(ui32Base + AES_O_IV_IN_3); -} - -//***************************************************************************** -// -//! Saves the tag registers to a user-defined location. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8TagData is pointer to the location that stores the tag data. -//! -//! This function stores the tag data for use authenticated encryption and -//! decryption operations. -//! -//! \return None. -// -//***************************************************************************** -void -AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Read the tag data. - // - *((uint32_t *)(pui8TagData+0)) = HWREG((ui32Base + AES_O_TAG_OUT_0)); - *((uint32_t *)(pui8TagData+4)) = HWREG((ui32Base + AES_O_TAG_OUT_1)); - *((uint32_t *)(pui8TagData+8)) = HWREG((ui32Base + AES_O_TAG_OUT_2)); - *((uint32_t *)(pui8TagData+12)) = HWREG((ui32Base + AES_O_TAG_OUT_3)); -} - -//***************************************************************************** -// -//! Used to set the write crypto data length in the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui64Length is the crypto data length in bytes. -//! -//! This function stores the cryptographic data length in blocks for all modes. -//! Data lengths up to (2^61 - 1) bytes are allowed. For GCM, any value up -//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used. For -//! basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the -//! length field, indicating that the length is infinite. -//! -//! When this function is called, the engine is triggered to start using -//! this context. -//! -//! \note This length does not include the authentication-only data used in -//! some modes. Use the AESAuthLengthSet() function to specify the -//! authentication data length. -//! -//! \return None -// -//***************************************************************************** -void -AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register by shifting the 64-bit ui64Length. - // - HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length); - HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32); -} - -//***************************************************************************** -// -//! Sets the optional additional authentication data (AAD) length. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Length is the length in bytes. -//! -//! This function is only used to write the authentication data length in the -//! combined modes (GCM or CCM) and XTS mode. Supported AAD lengths for CCM -//! are from 0 to (2^16 - 28) bytes. For GCM, any value up to (2^32 - 1) can -//! be used. For XTS mode, this register is used to load j. Loading of j is -//! only required if j != 0. j represents the sequential number of the 128-bit -//! blocks inside the data unit. Consequently, j must be multiplied by 16 -//! when passed to this function, thereby placing the block number in -//! bits [31:4] of the register. -//! -//! When this function is called, the engine is triggered to start using -//! this context for GCM and CCM. -//! -//! \return None -// -//***************************************************************************** -void -AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length into the register. - // - HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers without blocking. -//! This api writes data in blocks -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Dest is a pointer to an array of words of data. -//! \param ui8Length the length can be from 1 to 16 -//! -//! This function reads a block of either plaintext or ciphertext out of the -//! AES module. If the output data is not ready, the function returns -//! false. If the read completed successfully, the function returns true. -//! A block is 16 bytes or 4 words. -//! -//! \return true or false. -// -//***************************************************************************** -bool -AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) -{ - volatile uint32_t pui32Dest[4]; - uint8_t ui8BytCnt; - uint8_t *pui8DestTemp; - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - if((ui8Length == 0)||(ui8Length>16)) - { - return(false); - } - - // - // Check if the output is ready before reading the data. If it not ready, - // return false. - // - if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - return(false); - } - - // - // Read a block of data from the data registers - // - pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); - pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); - pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); - pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); - - // - //Copy the data to a block memory - // - pui8DestTemp = (uint8_t *)pui32Dest; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); - } - // - // Read successful, return true. - // - return(true); -} - - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers with blocking. -//! This api writes data in blocks -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Dest is a pointer to an array of words. -//! \param ui8Length is the length of data in bytes to be read. -//! ui8Length can be from 1 to 16 -//! -//! This function reads a block of either plaintext or ciphertext out of the -//! AES module. If the output is not ready, the function waits until it -//! is ready. A block is 16 bytes or 4 words. -//! -//! \return None. -// -//***************************************************************************** - -void -AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) -{ - volatile uint32_t pui32Dest[4]; - uint8_t ui8BytCnt; - uint8_t *pui8DestTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - if((ui8Length == 0)||(ui8Length>16)) - { - return; - } - - - // - // Wait for the output to be ready before reading the data. - // - while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Read a block of data from the data registers - // - pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); - pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); - pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); - pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); - // - //Copy the data to a block memory - // - pui8DestTemp = (uint8_t *)pui32Dest; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); - } - - return; -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to an array of words of data. -//! \param ui8Length the length can be from 1 to 16 -//! -//! This function writes a block of either plaintext or ciphertext into the -//! AES module. If the input is not ready, the function returns false -//! If the write completed successfully, the function returns true. -//! -//! \return True or false. -// -//***************************************************************************** -bool -AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) -{ - volatile uint32_t pui32Src[4]={0,0,0,0}; - uint8_t ui8BytCnt; - uint8_t *pui8SrcTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - if((ui8Length == 0)||(ui8Length>16)) - { - return(false); - } - - // - // Check if the input is ready. If not, then return false. - // - if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL)))) - { - return(false); - } - - - // - //Copy the data to a block memory - // - pui8SrcTemp = (uint8_t *)pui32Src; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); - } - // - // Write a block of data into the data registers. - // - HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; - HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; - HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; - HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; - - // - // Write successful, return true. - // - return(true); -} - - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers with blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to an array of bytes. -//! \param ui8Length the length can be from 1 to 16 -//! -//! This function writes a block of either plaintext or ciphertext into the -//! AES module. If the input is not ready, the function waits until it is -//! ready before performing the write. -//! -//! \return None. -// -//***************************************************************************** - -void -AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) -{ - volatile uint32_t pui32Src[4]={0,0,0,0}; - uint8_t ui8BytCnt; - uint8_t *pui8SrcTemp; - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - if((ui8Length == 0)||(ui8Length>16)) - { - return; - } - // - // Wait for input ready. - // - while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - //Copy the data to a block memory - // - pui8SrcTemp = (uint8_t *)pui32Src; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); - } - - // - // Write a block of data into the data registers. - // - HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; - HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; - HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; - HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; -} - - -//***************************************************************************** -// -//! Used to process(transform) blocks of data, either encrypt or decrypt it. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to the memory location where the input data -//! is stored. -//! \param pui8Dest is a pointer to the memory location output is written. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! -//! This function iterates the encryption or decryption mechanism number over -//! the data length. Before calling this function, ensure that the AES -//! module is properly configured the key, data size, mode, etc. Only ECB, -//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used. The data -//! is processed in 4-word (16-byte) blocks. -//! -//! \note This function only supports values of \e ui32Length less than 2^32, -//! because the memory size is restricted to between 0 to 2^32 bytes. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, - uint32_t ui32Length) -{ - uint32_t ui32Count, ui32BlkCount, ui32ByteCount; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register first, which triggers the engine to start - // using this context. - // - AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); - - // - // Now loop until the blocks are written. - // - ui32BlkCount = ui32Length/16; - for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + (ui32Count*16) ,16); - - // - // Read the data registers. - // - AESDataRead(ui32Base, pui8Dest + (ui32Count*16) ,16); - - } - - // - //Now handle the residue bytes - // - ui32ByteCount = ui32Length%16; - if(ui32ByteCount) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + (16*ui32BlkCount) ,ui32ByteCount); - - // - // Read the data registers. - // - AESDataRead(ui32Base, pui8Dest + (16*ui32BlkCount) ,ui32ByteCount); - } - - - - // - // Return true to indicate successful completion of the function. - // - return(true); -} -//***************************************************************************** -// -//! Used to generate message authentication code (MAC) using CBC-MAC and F9 mode. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to the memory location where the input data -//! is stored. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! \param pui8Tag is a pointer to a 4-word array where the hash tag is -//! written. -//! -//! This function processes data to produce a hash tag that can be used tor -//! authentication. Before calling this function, ensure that the AES -//! module is properly configured the key, data size, mode, etc. Only -//! CBC-MAC and F9 modes should be used. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, uint32_t ui32Length, - uint8_t *pui8Tag) -{ - uint32_t ui32Count, ui32BlkCount, ui32ByteCount; - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register first, which triggers the engine to start - // using this context. - // - AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); - - // - // Write the data registers. - // - - // - // Now loop until the blocks are written. - // - ui32BlkCount = ui32Length/16; - for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + ui32Count*16 ,16); - } - - // - //Now handle the residue bytes - // - ui32ByteCount = ui32Length%16; - if(ui32ByteCount) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + (ui32Count*ui32BlkCount) ,ui32ByteCount); - } - - // - // Wait for the context data regsiters to be ready. - // - while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0) - { - } - - // - // Read the hash tag value. - // - AESTagRead(AES_BASE, pui8Tag); - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Used for Authenticated encryption (AE) of the data. Processes and authenticates blocks of data, -//! either encrypt the data or decrypt the data. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to the memory location where the input data -//! is stored. The data must be padded to the 16-byte boundary. -//! \param pui8Dest is a pointer to the memory location output is written. -//! The space for written data must be rounded up to the 16-byte boundary. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! \param pui8AuthSrc is a pointer to the memory location where the -//! additional authentication data is stored. The data must be padded to the -//! 16-byte boundary. -//! \param ui32AuthLength is the length of the additional authentication -//! data in bytes. -//! \param pui8Tag is a pointer to a 4-word array where the hash tag is -//! written. -//! -//! This function encrypts or decrypts blocks of data in addition to -//! authentication data. A hash tag is also produced. Before calling this -//! function, ensure that the AES module is properly configured the key, -//! data size, mode, etc. Only CCM and GCM modes should be used. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, - uint32_t ui32Length, uint8_t *pui8AuthSrc, - uint32_t ui32AuthLength, uint8_t *pui8Tag) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Set the data length. - // - AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); - - // - // Set the additional authentication data length. - // - AESAuthDataLengthSet(AES_BASE, ui32AuthLength); - - // - // Now loop until the authentication data blocks are written. - // - for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8AuthSrc + (ui32Count),16); - } - - // - // Now loop until the data blocks are written. - // - for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + (ui32Count),16); - - // - // - // Read the data registers. - // - AESDataRead(ui32Base, pui8Dest + (ui32Count),16); - } - - // - // Wait for the context data regsiters to be ready. - // - while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0) - { - } - - // - // Read the hash tag value. - // - AESTagRead(AES_BASE, pui8Tag); - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Returns the current AES module interrupt status. -//! -//! \param ui32Base is the base address of the AES module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! \return Returns a bit mask of the interrupt sources, which is a logical OR -//! of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt. -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -// -//***************************************************************************** -uint32_t -AESIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Temp; - uint32_t ui32IrqEnable; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Read the IRQ status register and return the value. - // - if(bMasked) - { - ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_MIS); - ui32IrqEnable = HWREG(ui32Base + AES_O_IRQENABLE); - return((HWREG(ui32Base + AES_O_IRQSTATUS) & - ui32IrqEnable) | ((ui32Temp & 0x0000000F) << 16)); - } - else - { - ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_RIS); - return(HWREG(ui32Base + AES_O_IRQSTATUS) | - ((ui32Temp & 0x0000000F) << 16)); - } -} - -//***************************************************************************** -// -//! Enables AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to enable. -//! -//! This function enables the interrupts in the AES module. The \e ui32IntFlags -//! parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note Interrupts that have been previously been enabled are not disabled -//! when this function is called. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || - (ui32IntFlags == AES_INT_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DATA_IN) || - (ui32IntFlags == AES_INT_DATA_OUT) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - // - // Set the flags. - // - HWREG(DTHE_BASE + DTHE_O_AES_IM) &= ~((ui32IntFlags & 0x000F0000) >> 16); - HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; -} - -//***************************************************************************** -// -//! Disables AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. -//! -//! This function disables the interrupt sources in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note The DMA done interrupts are the only interrupts that can be cleared. -//! The remaining interrupts can be disabled instead using AESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || - (ui32IntFlags == AES_INT_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DATA_IN) || - (ui32IntFlags == AES_INT_DATA_OUT) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - // - // Clear the flags. - // - HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x000F0000) >> 16); - HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); -} - -//***************************************************************************** -// -//! Clears AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. -//! -//! This function clears the interrupt sources in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note Only the DMA done interrupts can be cleared. The remaining -//! interrupts should be disabled with AESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - HWREG(DTHE_BASE + DTHE_O_AES_IC) = ((ui32IntFlags >> 16) & 0x0000000F); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled AES interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables AES interrupts on the interrupt controller; specific AES -//! interrupt sources must be enabled using AESIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! AESIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() is used to enable AES interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_AES, pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_AES); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_AES); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_AES); -} - -//***************************************************************************** -// -//! Enables uDMA requests for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Flags is a bit mask of the uDMA requests to be enabled. -//! -//! This function enables the uDMA request sources in the AES module. -//! The \e ui32Flags parameter is the logical OR of any of the following: -//! -//! - \b AES_DMA_DATA_IN -//! - \b AES_DMA_DATA_OUT -//! - \b AES_DMA_CONTEXT_IN -//! - \b AES_DMA_CONTEXT_OUT -//! -//! \return None. -// -//***************************************************************************** -void -AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Flags == AES_DMA_DATA_IN) || - (ui32Flags == AES_DMA_DATA_OUT) || - (ui32Flags == AES_DMA_CONTEXT_IN) || - (ui32Flags == AES_DMA_CONTEXT_OUT)); - - // - // Set the flags in the current register value. - // - HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags; -} - -//***************************************************************************** -// -//! Disables uDMA requests for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Flags is a bit mask of the uDMA requests to be disabled. -//! -//! This function disables the uDMA request sources in the AES module. -//! The \e ui32Flags parameter is the logical OR of any of the -//! following: -//! -//! - \b AES_DMA_DATA_IN -//! - \b AES_DMA_DATA_OUT -//! - \b AES_DMA_CONTEXT_IN -//! - \b AES_DMA_CONTEXT_OUT -//! -//! \return None. -// -//***************************************************************************** -void -AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Flags == AES_DMA_DATA_IN) || - (ui32Flags == AES_DMA_DATA_OUT) || - (ui32Flags == AES_DMA_CONTEXT_IN) || - (ui32Flags == AES_DMA_CONTEXT_OUT)); - - // - // Clear the flags in the current register value. - // - HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.h deleted file mode 100755 index de5d2c68b8f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// aes.h -// -// Defines and Macros for the AES module. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_AES_H__ -#define __DRIVERLIB_AES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the operation direction in the -// ui32Config argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_DIR_ENCRYPT 0x00000004 -#define AES_CFG_DIR_DECRYPT 0x00000000 - -//***************************************************************************** -// -// The following defines are used to specify the key size in the ui32Config -// argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_KEY_SIZE_128BIT 0x00000008 -#define AES_CFG_KEY_SIZE_192BIT 0x00000010 -#define AES_CFG_KEY_SIZE_256BIT 0x00000018 - -//***************************************************************************** -// -// The following defines are used to specify the mode of operation in the -// ui32Config argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_MODE_M 0x2007fe60 -#define AES_CFG_MODE_ECB 0x00000000 -#define AES_CFG_MODE_CBC 0x00000020 -#define AES_CFG_MODE_CTR 0x00000040 -#define AES_CFG_MODE_ICM 0x00000200 -#define AES_CFG_MODE_CFB 0x00000400 -#define AES_CFG_MODE_XTS_TWEAKJL \ - 0x00000800 -#define AES_CFG_MODE_XTS_K2IJL \ - 0x00001000 -#define AES_CFG_MODE_XTS_K2ILJ0 \ - 0x00001800 -#define AES_CFG_MODE_F8 0x00002000 -#define AES_CFG_MODE_F9 0x20004000 -#define AES_CFG_MODE_CBCMAC 0x20008000 -#define AES_CFG_MODE_GCM_HLY0ZERO \ - 0x20010040 -#define AES_CFG_MODE_GCM_HLY0CALC \ - 0x20020040 -#define AES_CFG_MODE_GCM_HY0CALC \ - 0x20030040 -#define AES_CFG_MODE_CCM 0x20040040 - -//***************************************************************************** -// -// The following defines are used to specify the counter width in the -// ui32Config argument in the AESConfig function. It is only required to -// be defined when using CTR, CCM, or GCM modes. Only one length is permitted. -// -//***************************************************************************** -#define AES_CFG_CTR_WIDTH_32 0x00000000 -#define AES_CFG_CTR_WIDTH_64 0x00000080 -#define AES_CFG_CTR_WIDTH_96 0x00000100 -#define AES_CFG_CTR_WIDTH_128 0x00000180 - -//***************************************************************************** -// -// The following defines are used to define the width of the length field for -// CCM operation through the ui32Config argument in the AESConfig function. -// This value is also known as L. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_CCM_L_2 0x00080000 -#define AES_CFG_CCM_L_4 0x00180000 -#define AES_CFG_CCM_L_8 0x00380000 - -//***************************************************************************** -// -// The following defines are used to define the length of the authentication -// field for CCM operations through the ui32Config argument in the AESConfig -// function. This value is also known as M. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_CCM_M_4 0x00400000 -#define AES_CFG_CCM_M_6 0x00800000 -#define AES_CFG_CCM_M_8 0x00c00000 -#define AES_CFG_CCM_M_10 0x01000000 -#define AES_CFG_CCM_M_12 0x01400000 -#define AES_CFG_CCM_M_14 0x01800000 -#define AES_CFG_CCM_M_16 0x01c00000 - -//***************************************************************************** -// -// Interrupt flags for use with the AESIntEnable, AESIntDisable, and -// AESIntStatus functions. -// -//***************************************************************************** -#define AES_INT_CONTEXT_IN 0x00000001 -#define AES_INT_CONTEXT_OUT 0x00000008 -#define AES_INT_DATA_IN 0x00000002 -#define AES_INT_DATA_OUT 0x00000004 -#define AES_INT_DMA_CONTEXT_IN 0x00010000 -#define AES_INT_DMA_CONTEXT_OUT 0x00020000 -#define AES_INT_DMA_DATA_IN 0x00040000 -#define AES_INT_DMA_DATA_OUT 0x00080000 - -//***************************************************************************** -// -// Defines used when enabling and disabling DMA requests in the -// AESEnableDMA and AESDisableDMA functions. -// -//***************************************************************************** -#define AES_DMA_DATA_IN 0x00000040 -#define AES_DMA_DATA_OUT 0x00000020 -#define AES_DMA_CONTEXT_IN 0x00000080 -#define AES_DMA_CONTEXT_OUT 0x00000100 - -//***************************************************************************** -// -// Function prototypes. -// -//***************************************************************************** -extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, - uint32_t ui32Keysize); -extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, - uint32_t ui32Keysize); -extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key); -extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata); -extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata); -extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData); -extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length); -extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length); -extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, - uint8_t ui8Length); -extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, - uint8_t ui8Length); -extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t ui8Length); -extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t ui8Length); -extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t *pui8Dest, - uint32_t ui32Length); -extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, - uint32_t ui32Length, - uint8_t *pui8Tag); -extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t *pui8Dest, uint32_t ui32Length, - uint8_t *pui8AuthSrc, uint32_t ui32AuthLength, - uint8_t *pui8Tag); -extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked); -extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); -extern void AESIntUnregister(uint32_t ui32Base); -extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); -extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_AES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.c deleted file mode 100755 index d6f40ca13ce..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.c +++ /dev/null @@ -1,888 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// des.c -// -// Driver for the DES data transformation. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup DES_Data_Encryption_Standard_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_des.h" -#include "inc/hw_dthe.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "debug.h" -#include "ti_des.h" -#include "interrupt.h" - - -//***************************************************************************** -// -//! Configures the DES module for operation. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Config is the configuration of the DES module. -//! -//! This function configures the DES module for operation. -//! -//! The \e ui32Config parameter is a bit-wise OR of a number of configuration -//! flags. The valid flags are grouped below based on their function. -//! -//! The direction of the operation is specified with one of the following two -//! flags. Only one is permitted. -//! -//! - \b DES_CFG_DIR_ENCRYPT - Encryption -//! - \b DES_CFG_DIR_DECRYPT - Decryption -//! -//! The operational mode of the DES engine is specified with one of the -//! following flags. Only one is permitted. -//! -//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode -//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode -//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode -//! -//! The selection of single DES or triple DES is specified with one of the -//! following two flags. Only one is permitted. -//! -//! - \b DES_CFG_SINGLE - Single DES -//! - \b DES_CFG_TRIPLE - Triple DES -//! -//! \return None. -// -//***************************************************************************** -void -DESConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Backup the save context field. - // - ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT); - - // - // Write the control register. - // - HWREG(ui32Base + DES_O_CTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the key used for DES operations. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Key is a pointer to an array that holds the key -//! -//! This function sets the key used for DES operations. -//! -//! \e pui8Key should be 64 bits long (2 words) if single DES is being used or -//! 192 bits (6 words) if triple DES is being used. -//! -//! \return None. -// -//***************************************************************************** -void -DESKeySet(uint32_t ui32Base, uint8_t *pui8Key) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Write the first part of the key. - // - HWREG(ui32Base + DES_O_KEY1_L) = * ((uint32_t *)(pui8Key + 0)); - HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4)); - - // - // If we are performing triple DES, then write the key registers for - // the second and third rounds. - // - if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE) - { - HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8)); - HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12)); - HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16)); - HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20)); - } -} - -//***************************************************************************** -// -//! Sets the initialization vector in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8IVdata is a pointer to an array of 64 bits (2 words) of data to -//! be written into the initialization vectors registers. -//! -//! This function sets the initialization vector in the DES module. It returns -//! true if the registers were successfully written. If the context registers -//! cannot be written at the time the function was called, then false is -//! returned. -//! -//! \return True or false. -// -//***************************************************************************** -bool -DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Check to see if context registers can be overwritten. If not, return - // false. - // - if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0) - { - return(false); - } - - // - // Write the initialization vector registers. - // - HWREG(ui32Base + DES_O_IV_L) = *((uint32_t *) (pui8IVdata + 0)); - HWREG(ui32Base + DES_O_IV_H) = *((uint32_t *) (pui8IVdata + 4)); - - // - // Return true to indicate the write was successful. - // - return(true); -} - -//***************************************************************************** -// -//! Sets the crytographic data length in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Length is the length of the data in bytes. -//! -//! This function writes the cryptographic data length into the DES module. -//! When this register is written, the engine is triggersed to start using -//! this context. -//! -//! \note Data lengths up to (2^32 - 1) bytes are allowed. -//! -//! \return None. -// -//***************************************************************************** -void -DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Write the length register. - // - HWREG(ui32Base + DES_O_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Dest is a pointer to an array of 2 words. -//! \param ui8Length the length can be from 1 to 8 -//! -//! This function returns true if the data was ready when the function was -//! called. If the data was not ready, false is returned. -//! -//! \return True or false. -// -//***************************************************************************** -bool -DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) -{ - volatile uint32_t pui32Dest[2]; - uint8_t ui8BytCnt; - uint8_t *pui8DestTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - if((ui8Length == 0)||(ui8Length>8)) - { - return(false); - } - - // - // Check to see if the data is ready to be read. - // - if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) - { - return(false); - } - - // - // Read two words of data from the data registers. - // - pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); - pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); - - // - //Copy the data to a block memory - // - pui8DestTemp = (uint8_t *)pui32Dest; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); - } - - // - // Return true to indicate a successful write. - // - return(true); -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers with blocking. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Dest is a pointer to an array of bytes. -//! \param ui8Length the length can be from 1 to 8 -//! -//! This function waits until the DES module is finished and encrypted or -//! decrypted data is ready. The output data is then stored in the pui8Dest -//! array. -//! -//! \return None -// -//***************************************************************************** -void -DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) -{ - volatile uint32_t pui32Dest[2]; - uint8_t ui8BytCnt; - uint8_t *pui8DestTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - if((ui8Length == 0)||(ui8Length>8)) - { - return; - } - // - // Wait for data output to be ready. - // - while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0) - { - } - - // - // Read two words of data from the data registers. - // - pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); - pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); - - // - //Copy the data to a block memory - // - pui8DestTemp = (uint8_t *)pui32Dest; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); - } -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Src is a pointer to an array of 2 words. -//! \param ui8Length the length can be from 1 to 8 -//! -//! This function returns false if the DES module is not ready to accept -//! data. It returns true if the data was written successfully. -//! -//! \return true or false. -// -//***************************************************************************** -bool -DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) -{ - - volatile uint32_t pui32Src[2]={0,0}; - uint8_t ui8BytCnt; - uint8_t *pui8SrcTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - if((ui8Length == 0)||(ui8Length>8)) - { - return(false); - } - - // - // Check if the DES module is ready to encrypt or decrypt data. If it - // is not, return false. - // - if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL)))) - { - return(false); - } - - // - // Copy the data to a block memory - // - pui8SrcTemp = (uint8_t *)pui32Src; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); - } - - // - // Write the data. - // - HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; - HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; - - // - // Return true to indicate a successful write. - // - return(true); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Src is a pointer to an array of bytes. -//! \param ui8Length the length can be from 1 to 8 -//! -//! This function waits until the DES module is ready before writing the -//! data contained in the pui8Src array. -//! -//! \return None. -// -//***************************************************************************** -void -DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) -{ - volatile uint32_t pui32Src[2]={0,0}; - uint8_t ui8BytCnt; - uint8_t *pui8SrcTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - if((ui8Length == 0)||(ui8Length>8)) - { - return; - } - - // - // Wait for the input ready bit to go high. - // - while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0) - { - } - - // - //Copy the data to a block memory - // - pui8SrcTemp = (uint8_t *)pui32Src; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); - } - - // - // Write the data. - // - HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; - HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; -} - -//***************************************************************************** -// -//! Processes blocks of data through the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Src is a pointer to an array of words that contains the -//! source data for processing. -//! \param pui8Dest is a pointer to an array of words consisting of the -//! processed data. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! It must be a multiple of eight. -//! -//! This function takes the data contained in the pui8Src array and processes -//! it using the DES engine. The resulting data is stored in the -//! pui8Dest array. The function blocks until all of the data has been -//! processed. If processing is successful, the function returns true. -//! -//! \note This functions assumes that the DES module has been configured, -//! and initialization values and keys have been written. -//! -//! \return true or false. -// -//***************************************************************************** -bool -DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, - uint32_t ui32Length) -{ - uint32_t ui32Count, ui32BlkCount, ui32ByteCount; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Length % 8) == 0); - - // - // Write the length register first. This triggers the engine to start - // using this context. - // - HWREG(ui32Base + DES_O_LENGTH) = ui32Length; - - - // - // Now loop until the blocks are written. - // - ui32BlkCount = ui32Length/8; - for(ui32Count = 0; ui32Count > 16); - HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; -} - -//***************************************************************************** -// -//! Disables interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. -//! -//! This function disables interrupt sources in the DES module. -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DATA_IN - Data input interrupt -//! - \b DES_INT_DATA_OUT - Data output interrupt -//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \return None. -// -//***************************************************************************** -void -DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DATA_IN) || - (ui32IntFlags & DES_INT_DATA_OUT) || - (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - // - // Clear the interrupts from the flags. - // - HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x00070000) >> 16); - HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); -} - -//***************************************************************************** -// -//! Clears interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. -//! -//! This function disables interrupt sources in the DES module. -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt -//! -//! \note The DMA done interrupts are the only interrupts that can be cleared. -//! The remaining interrupts can be disabled instead using DESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled DES interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables DES interrupts on the interrupt controller; specific DES -//! interrupt sources must be enabled using DESIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! DESIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() should be used to enable DES interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_DES, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(INT_DES); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -DESIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_DES); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_DES); -} - -//***************************************************************************** -// -//! Enables DMA request sources in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Flags is a bit mask of the DMA requests to be enabled. -//! -//! This function enables DMA request sources in the DES module. The -//! \e ui32Flags parameter should be the logical OR of any of the following: -//! -//! - \b DES_DMA_CONTEXT_IN - Context In -//! - \b DES_DMA_DATA_OUT - Data Out -//! - \b DES_DMA_DATA_IN - Data In -//! -//! \return None. -// -//***************************************************************************** -void -DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || - (ui32Flags & DES_DMA_DATA_OUT) || - (ui32Flags & DES_DMA_DATA_IN)); - - // - // Set the data in and data out DMA request enable bits. - // - HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags; -} - -//***************************************************************************** -// -//! Disables DMA request sources in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Flags is a bit mask of the DMA requests to be disabled. -//! -//! This function disables DMA request sources in the DES module. The -//! \e ui32Flags parameter should be the logical OR of any of the following: -//! -//! - \b DES_DMA_CONTEXT_IN - Context In -//! - \b DES_DMA_DATA_OUT - Data Out -//! - \b DES_DMA_DATA_IN - Data In -//! -//! \return None. -// -//***************************************************************************** -void -DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || - (ui32Flags & DES_DMA_DATA_OUT) || - (ui32Flags & DES_DMA_DATA_IN)); - - // - // Disable the DMA sources. - // - HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.h deleted file mode 100755 index ecd6ab61a5d..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// des.h -// -// Defines and Macros for the DES module. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_DES_H__ -#define __DRIVERLIB_DES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the direction with the -// ui32Config argument in the DESConfig() function. Only one is permitted. -// -//***************************************************************************** -#define DES_CFG_DIR_DECRYPT 0x00000000 -#define DES_CFG_DIR_ENCRYPT 0x00000004 - -//***************************************************************************** -// -// The following defines are used to specify the operational with the -// ui32Config argument in the DESConfig() function. Only one is permitted. -// -//***************************************************************************** -#define DES_CFG_MODE_ECB 0x00000000 -#define DES_CFG_MODE_CBC 0x00000010 -#define DES_CFG_MODE_CFB 0x00000020 - -//***************************************************************************** -// -// The following defines are used to select between single DES and triple DES -// with the ui32Config argument in the DESConfig() function. Only one is -// permitted. -// -//***************************************************************************** -#define DES_CFG_SINGLE 0x00000000 -#define DES_CFG_TRIPLE 0x00000008 - -//***************************************************************************** -// -// The following defines are used with the DESIntEnable(), DESIntDisable() and -// DESIntStatus() functions. -// -//***************************************************************************** -#define DES_INT_CONTEXT_IN 0x00000001 -#define DES_INT_DATA_IN 0x00000002 -#define DES_INT_DATA_OUT 0x00000004 -#define DES_INT_DMA_CONTEXT_IN 0x00010000 -#define DES_INT_DMA_DATA_IN 0x00020000 -#define DES_INT_DMA_DATA_OUT 0x00040000 - -//***************************************************************************** -// -// The following defines are used with the DESEnableDMA() and DESDisableDMA() -// functions. -// -//***************************************************************************** -#define DES_DMA_CONTEXT_IN 0x00000080 -#define DES_DMA_DATA_OUT 0x00000040 -#define DES_DMA_DATA_IN 0x00000020 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, - uint8_t ui8Length); -extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, - uint8_t ui8Length); -extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t *pui8Dest, uint32_t ui32Length); -extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t ui8Length); -extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t ui8Length); -extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); -extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); -extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); -extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked); -extern void DESIntUnregister(uint32_t ui32Base); -extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata); -extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key); -extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_DES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.c deleted file mode 100644 index b4f0f6316f4..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.c +++ /dev/null @@ -1,2053 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// i2c.c -// -// Driver for Inter-IC (I2C) bus block. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup I2C_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_i2c.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "debug.h" -#include "ti_i2c.h" -#include "interrupt.h" - -//***************************************************************************** -// -// A mapping of I2C base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32I2CIntMap[][2] = -{ - { I2CA0_BASE, INT_I2CA0}, -}; - -static const int_fast8_t g_i8I2CIntMapRows = - sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]); - -//***************************************************************************** -// -//! \internal -//! Checks an I2C base address. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function determines if a I2C module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_I2CBaseValid(uint32_t ui32Base) -{ - return((ui32Base == I2CA0_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the I2C interrupt number. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! Given a I2C base address, this function returns the corresponding -//! interrupt number. -//! -//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid. -// -//***************************************************************************** -static uint32_t -_I2CIntNumberGet(uint32_t ui32Base) -{ - int_fast8_t i8Idx, i8Rows; - const uint32_t (*ppui32I2CIntMap)[2]; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - ppui32I2CIntMap = g_ppui32I2CIntMap; - i8Rows = g_i8I2CIntMapRows; - - // - // Loop through the table that maps I2C base addresses to interrupt - // numbers. - // - for(i8Idx = 0; i8Idx < i8Rows; i8Idx++) - { - // - // See if this base address matches. - // - if(ppui32I2CIntMap[i8Idx][0] == ui32Base) - { - // - // Return the corresponding interrupt number. - // - return(ppui32I2CIntMap[i8Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Initializes the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. -//! \param bFast set up for fast data transfers. -//! -//! This function initializes operation of the I2C Master block by configuring -//! the bus speed for the master and enabling the I2C Master block. -//! -//! If the parameter \e bFast is \b true, then the master block is set up to -//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at -//! 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually -//! write the I2CMTPR after calling this function. For High Speed (3.4 Mbps) -//! mode, a specific command is used to switch to the faster clocks after the -//! initial communication with the slave is done at either 100 Kbps or -//! 400 Kbps. -//! -//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast) -{ - uint32_t ui32SCLFreq; - uint32_t ui32TPR; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Must enable the device before doing anything else. - // - I2CMasterEnable(ui32Base); - - // - // Get the desired SCL speed. - // - if(bFast == true) - { - ui32SCLFreq = 400000; - } - else - { - ui32SCLFreq = 100000; - } - - // - // Compute the clock divider that achieves the fastest speed less than or - // equal to the desired speed. The numerator is biased to favor a larger - // clock divider so that the resulting clock is always less than or equal - // to the desired clock, never greater. - // - ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / - (2 * 10 * ui32SCLFreq)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; - - // - // Check to see if this I2C peripheral is High-Speed enabled. If yes, also - // choose the fastest speed that is less than or equal to 3.4 Mbps. - // - if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) - { - ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) / - (2 * 3 * 3400000)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; - } -} - -//***************************************************************************** -// -//! Initializes the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8SlaveAddr 7-bit slave address -//! -//! This function initializes operation of the I2C Slave block by configuring -//! the slave address and enabling the I2C Slave block. -//! -//! The parameter \e ui8SlaveAddr is the value that is compared against the -//! slave address sent by an I2C master. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Must enable the device before doing anything else. - // - I2CSlaveEnable(ui32Base); - - // - // Set up the slave address. - // - HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; -} - -//***************************************************************************** -// -//! Sets the I2C slave address. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8AddrNum determines which slave address is set. -//! \param ui8SlaveAddr is the 7-bit slave address -//! -//! This function writes the specified slave address. The \e ui32AddrNum field -//! dictates which slave address is configured. For example, a value of 0 -//! configures the primary address and a value of 1 configures the secondary. -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8AddrNum > 1)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Determine which slave address is being set. - // - switch(ui8AddrNum) - { - // - // Set up the primary slave address. - // - case 0: - { - HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; - break; - } - - // - // Set up and enable the secondary slave address. - // - case 1: - { - HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; - break; - } - } -} - -//***************************************************************************** -// -//! Enables the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function enables operation of the I2C Master block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master block. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; -} - -//***************************************************************************** -// -//! Enables the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This fucntion enables operation of the I2C Slave block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the clock to the slave block. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; - - // - // Enable the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Disables the I2C master block. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function disables operation of the I2C master block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master block. - // - HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); -} - -//***************************************************************************** -// -//! Disables the I2C slave block. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function disables operation of the I2C slave block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = 0; - - // - // Disable the clock to the slave block. - // - HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the I2C module. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param pfnHandler is a pointer to the function to be called when the -//! I2C interrupt occurs. -//! -//! This function sets the handler to be called when an I2C interrupt occurs. -//! This function enables the global interrupt in the interrupt controller; -//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and -//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's -//! responsibility to clear the interrupt source via I2CMasterIntClear() and -//! I2CSlaveIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the I2C port. - // - ui32Int = _I2CIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the I2C interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the I2C module. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function clears the handler to be called when an I2C interrupt -//! occurs. This function also masks off the interrupt in the interrupt r -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -I2CIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the I2C port. - // - ui32Int = _I2CIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables the I2C Master interrupt. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function enables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) = 1; -} - -//***************************************************************************** -// -//! Enables individual I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2C Master interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt -//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt -//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt -//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt -//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt -//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt -//! - \b I2C_MASTER_INT_START - Start Condition interrupt -//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt -//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt -//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt -//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt -//! - \b I2C_MASTER_INT_DATA - Data interrupt -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Enables the I2C Slave interrupt. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function enables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; -} - -//***************************************************************************** -// -//! Enables individual I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2C Slave interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt -//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt -//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt -//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt -//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt -//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt -//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt -//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt -//! - \b I2C_SLAVE_INT_DATA - Data interrupt -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the I2C Master interrupt. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function disables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) = 0; -} - -//***************************************************************************** -// -//! Disables individual I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated I2C Master interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the I2C Slave interrupt. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function disables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; -} - -//***************************************************************************** -// -//! Disables individual I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated I2C Slave interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Master module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -bool -I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); - } - else - { - return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Master module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in I2CMasterIntEnableEx(). -// -//***************************************************************************** -uint32_t -I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + I2C_O_MMIS)); - } - else - { - return(HWREG(ui32Base + I2C_O_MRIS)); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Slave module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -bool -I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false); - } - else - { - return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Slave module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in I2CSlaveIntEnableEx(). -// -//***************************************************************************** -uint32_t -I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + I2C_O_SMIS)); - } - else - { - return(HWREG(ui32Base + I2C_O_SRIS)); - } -} - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! The I2C Master interrupt source is cleared, so that it no longer -//! asserts. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C master interrupt source. - // - HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; - - // - // Workaround for I2C master interrupt clear errata for some - // devices. For later devices, this write is ignored and therefore - // harmless (other than the slight performance hit). - // - HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC; -} - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2C Master interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C master interrupt source. - // - HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! The I2C Slave interrupt source is cleared, so that it no longer asserts. -//! This function must be called in the interrupt handler to keep the interrupt -//! from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC; -} - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2C Slave interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Sets the address that the I2C Master places on the bus. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui8SlaveAddr 7-bit slave address -//! \param bReceive flag indicating the type of communication with the slave -//! -//! This function configures the address that the I2C Master places on the -//! bus when initiating a transaction. When the \e bReceive parameter is set -//! to \b true, the address indicates that the I2C Master is initiating a -//! read from the slave; otherwise the address indicates that the I2C -//! Master is initiating a write to the slave. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, - bool bReceive) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Set the address of the slave with which the master will communicate. - // - HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; -} - -//***************************************************************************** -// -//! Reads the state of the SDA and SCL pins. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function returns the state of the I2C bus by providing the real time -//! values of the SDA and SCL pins. -//! -//! -//! \return Returns the state of the bus with SDA in bit position 1 and SCL in -//! bit position 0. -// -//***************************************************************************** -uint32_t -I2CMasterLineStateGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the line state. - // - return(HWREG(ui32Base + I2C_O_MBMON)); -} - -//***************************************************************************** -// -//! Indicates whether or not the I2C Master is busy. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function returns an indication of whether or not the I2C Master is -//! busy transmitting or receiving data. -//! -//! \return Returns \b true if the I2C Master is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -bool -I2CMasterBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the busy status. - // - if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Indicates whether or not the I2C bus is busy. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function returns an indication of whether or not the I2C bus is busy. -//! This function can be used in a multi-master environment to determine if -//! another master is currently using the bus. -//! -//! \return Returns \b true if the I2C bus is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -bool -I2CMasterBusBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the bus busy status. - // - if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Controls the state of the I2C Master module. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32Cmd command to be issued to the I2C Master module. -//! -//! This function is used to control the state of the Master module send and -//! receive operations. The \e ui8Cmd parameter can be one of the following -//! values: -//! -//! - \b I2C_MASTER_CMD_SINGLE_SEND -//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE -//! - \b I2C_MASTER_CMD_BURST_SEND_START -//! - \b I2C_MASTER_CMD_BURST_SEND_CONT -//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH -//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP -//! - \b I2C_MASTER_CMD_QUICK_COMMAND -//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND -//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND -//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND)); - - // - // Send the command. - // - HWREG(ui32Base + I2C_O_MCS) = ui32Cmd; -} - -//***************************************************************************** -// -//! Gets the error status of the I2C Master module. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function is used to obtain the error status of the Master module send -//! and receive operations. -//! -//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE, -//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or -//! \b I2C_MASTER_ERR_ARB_LOST. -// -//***************************************************************************** -uint32_t -I2CMasterErr(uint32_t ui32Base) -{ - uint32_t ui32Err; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Get the raw error state - // - ui32Err = HWREG(ui32Base + I2C_O_MCS); - - // - // If the I2C master is busy, then all the other bit are invalid, and - // don't have an error to report. - // - if(ui32Err & I2C_MCS_BUSY) - { - return(I2C_MASTER_ERR_NONE); - } - - // - // Check for errors. - // - if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST)) - { - return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_ACK | I2C_MCS_ADRACK)); - } - else - { - return(I2C_MASTER_ERR_NONE); - } -} - -//***************************************************************************** -// -//! Transmits a byte from the I2C Master. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui8Data data to be transmitted from the I2C Master. -//! -//! This function places the supplied data into I2C Master Data Register. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the byte. - // - HWREG(ui32Base + I2C_O_MDR) = ui8Data; -} - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Master. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function reads a byte of data from the I2C Master Data Register. -//! -//! \return Returns the byte received from by the I2C Master, cast as an -//! uint32_t. -// -//***************************************************************************** -uint32_t -I2CMasterDataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_MDR)); -} - -//***************************************************************************** -// -//! Sets the Master clock timeout value. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32Value is the number of I2C clocks before the timeout is -//! asserted. -//! -//! This function enables and configures the clock low timeout feature in the -//! I2C peripheral. This feature is implemented as a 12-bit counter, with the -//! upper 8-bits being programmable. For example, to program a timeout of 20ms -//! with a 100kHz SCL frequency, \e ui32Value would be 0x7d. -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the timeout value. - // - HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value; -} - -//***************************************************************************** -// -//! Configures ACK override behavior of the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bEnable enables or disables ACK override. -//! -//! This function enables or disables ACK override, allowing the user -//! application to drive the value on SDA during the ACK cycle. -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable or disable based on bEnable. - // - if(bEnable) - { - HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; - } - else - { - HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; - } -} - -//***************************************************************************** -// -//! Writes the ACK value. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer. -//! -//! This function puts the desired ACK value on SDA during the ACK cycle. The -//! value written is only valid when ACK override is enabled using -//! I2CSlaveACKOverride(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // ACK or NACK based on the value of bACK. - // - if(bACK) - { - HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; - } - else - { - HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; - } -} - -//***************************************************************************** -// -//! Gets the I2C Slave module status -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function returns the action requested from a master, if any. -//! Possible values are: -//! -//! - \b I2C_SLAVE_ACT_NONE -//! - \b I2C_SLAVE_ACT_RREQ -//! - \b I2C_SLAVE_ACT_TREQ -//! - \b I2C_SLAVE_ACT_RREQ_FBR -//! - \b I2C_SLAVE_ACT_OWN2SEL -//! - \b I2C_SLAVE_ACT_QCMD -//! - \b I2C_SLAVE_ACT_QCMD_DATA -//! -//! \note Not all devices support the second I2C slave's own address -//! or the quick command function. Please consult the device data sheet to -//! determine if these features are supported. -//! -//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been -//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that -//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ -//! to indicate that an I2C master has requested that the I2C Slave module send -//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent -//! data to the I2C slave and the first byte following the slave's own address -//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C -//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick -//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the -//! data bit was set when the quick command was received. -// -//***************************************************************************** -uint32_t -I2CSlaveStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the slave status. - // - return(HWREG(ui32Base + I2C_O_SCSR)); -} - -//***************************************************************************** -// -//! Transmits a byte from the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8Data is the data to be transmitted from the I2C Slave -//! -//! This function places the supplied data into I2C Slave Data Register. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the byte. - // - HWREG(ui32Base + I2C_O_SDR) = ui8Data; -} - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function reads a byte of data from the I2C Slave Data Register. -//! -//! \return Returns the byte received from by the I2C Slave, cast as an -//! uint32_t. -// -//***************************************************************************** -uint32_t -I2CSlaveDataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_SDR)); -} - -//***************************************************************************** -// -//! Configures the I2C transmit (TX) FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param ui32Config is the configuration of the FIFO using specified macros. -//! -//! This configures the I2C peripheral's transmit FIFO. The transmit FIFO can -//! be used by the master or slave, but not both. The following macros are -//! used to configure the TX FIFO behavior for master or slave, with or without -//! DMA: -//! -//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE, -//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA -//! -//! To select the trigger level, one of the following macros should be used: -//! -//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2, -//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4, -//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6, -//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8 -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear transmit configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000; - - // - // Store new transmit configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; -} - -//***************************************************************************** -// -//! Flushes the transmit (TX) FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! -//! This function flushes the I2C transmit FIFO. -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CTxFIFOFlush(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Flush the TX FIFO. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH; -} - -//***************************************************************************** -// -//! Configures the I2C receive (RX) FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param ui32Config is the configuration of the FIFO using specified macros. -//! -//! This configures the I2C peripheral's receive FIFO. The receive FIFO can be -//! used by the master or slave, but not both. The following macros are used -//! to configure the RX FIFO behavior for master or slave, with or without DMA: -//! -//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE, -//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA -//! -//! To select the trigger level, one of the following macros should be used: -//! -//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2, -//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4, -//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6, -//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8 -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear receive configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff; - - // - // Store new receive configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; -} - -//***************************************************************************** -// -//! Flushes the receive (RX) FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! -//! This function flushes the I2C receive FIFO. -//! -//! \return None. -// -//***************************************************************************** -void -I2CRxFIFOFlush(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Flush the TX FIFO. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH; -} - -//***************************************************************************** -// -//! Gets the current FIFO status. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! -//! This function retrieves the status for both the transmit (TX) and receive -//! (RX) FIFOs. The trigger level for the transmit FIFO is set using -//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet(). -//! -//! \return Returns the FIFO status, enumerated as a bit field containing -//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY, -//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and -//! \b I2C_FIFO_TX_EMPTY. -// -//***************************************************************************** -uint32_t -I2CFIFOStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the contents of the FIFO status register. - // - return(HWREG(ui32Base + I2C_O_FIFOSTATUS)); -} - -//***************************************************************************** -// -//! Writes a data byte to the I2C transmit FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param ui8Data is the data to be placed into the transmit FIFO. -//! -//! This function adds a byte of data to the I2C transmit FIFO. If there is -//! no space available in the FIFO, this function waits for space to become -//! available before returning. -//! -//! \return None. -// -//***************************************************************************** -void -I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Wait until there is space. - // - while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) - { - } - - // - // Place data into the FIFO. - // - HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; -} - -//***************************************************************************** -// -//! Writes a data byte to the I2C transmit FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param ui8Data is the data to be placed into the transmit FIFO. -//! -//! This function adds a byte of data to the I2C transmit FIFO. If there is -//! no space available in the FIFO, this function returns a zero. -//! -//! \return The number of elements added to the I2C transmit FIFO. -// -//***************************************************************************** -uint32_t -I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // If FIFO is full, return zero. - // - if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) - { - return(0); - } - else - { - HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; - return(1); - } -} - -//***************************************************************************** -// -//! Reads a byte from the I2C receive FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! -//! This function reads a byte of data from I2C receive FIFO and places it in -//! the location specified by the \e pui8Data parameter. If there is no data -//! available, this function waits until data is received before returning. -//! -//! \return The data byte. -// -//***************************************************************************** -uint32_t -I2CFIFODataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Wait until there is data to read. - // - while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) - { - } - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_FIFODATA)); -} - -//***************************************************************************** -// -//! Reads a byte from the I2C receive FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param pui8Data is a pointer where the read data is stored. -//! -//! This function reads a byte of data from I2C receive FIFO and places it in -//! the location specified by the \e pui8Data parameter. If there is no data -//! available, this functions returns 0. -//! -//! \return The number of elements read from the I2C receive FIFO. -// -//***************************************************************************** -uint32_t -I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // If nothing in the FIFO, return zero. - // - if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) - { - return(0); - } - else - { - *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA); - return(1); - } -} - -//***************************************************************************** -// -//! Set the burst length for a I2C master FIFO operation. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui8Length is the length of the burst transfer. -//! -//! This function configures the burst length for a I2C Master FIFO operation. -//! The burst field is limited to 8 bits or 256 bytes. The burst length -//! applies to a single I2CMCS BURST operation meaning that it specifies the -//! burst length for only the current operation (can be TX or RX). Each burst -//! operation must configure the burst length prior to writing the BURST bit -//! in the I2CMCS using I2CMasterControl(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255)); - - // - // Set the burst length. - // - HWREG(ui32Base + I2C_O_MBLEN) = ui8Length; -} - -//***************************************************************************** -// -//! Returns the current value of the burst transfer counter. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function returns the current value of the burst transfer counter that -//! is used by the FIFO mechanism. Software can use this value to determine -//! how many bytes remain in a transfer, or where in the transfer the burst -//! operation was if an error has occurred. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -I2CMasterBurstCountGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Get burst count. - // - return(HWREG(ui32Base + I2C_O_MBCNT)); -} - -//***************************************************************************** -// -//! Configures the I2C Master glitch filter. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32Config is the glitch filter configuration. -//! -//! This function configures the I2C Master glitch filter. The value passed in -//! to \e ui32Config determines the sampling range of the glitch filter, which -//! is configurable between 1 and 32 system clock cycles. The default -//! configuration of the glitch filter is 0 system clock cycles, which means -//! that it's disabled. -//! -//! The \e ui32Config field should be any of the following values: -//! -//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED -//! - \b I2C_MASTER_GLITCH_FILTER_1 -//! - \b I2C_MASTER_GLITCH_FILTER_2 -//! - \b I2C_MASTER_GLITCH_FILTER_3 -//! - \b I2C_MASTER_GLITCH_FILTER_4 -//! - \b I2C_MASTER_GLITCH_FILTER_8 -//! - \b I2C_MASTER_GLITCH_FILTER_16 -//! - \b I2C_MASTER_GLITCH_FILTER_32 -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Configure the glitch filter field of MTPR. - // - HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; -} - -//***************************************************************************** -// -//! Enables FIFO usage for the I2C Slave module. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32Config is the desired FIFO configuration of the I2C Slave. -//! -//! This function configures the I2C Slave module to use the FIFO(s). This -//! function should be used in combination with I2CTxFIFOConfigSet() and/or -//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell -//! the FIFO hardware whether to interact with the I2C Master or Slave. The -//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and -//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config -//! field. -//! -//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(), -//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration. -//! Therefore, application software should call I2CSlaveEnable() followed by -//! I2CSlaveFIFOEnable() with the desired FIFO configuration. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the FIFOs for the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Disable FIFO usage for the I2C Slave module. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function disables the FIFOs for the I2C Slave. After calling this -//! this function, the FIFOs are disabled, but the Slave remains active. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveFIFODisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable slave FIFOs. - // - HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.h deleted file mode 100644 index bd4ee41cc28..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// i2c.h -// -// Prototypes for the I2C Driver. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_I2C_H__ -#define __DRIVERLIB_I2C_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** - -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - 0x00000007 -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - 0x00000007 -#define I2C_MASTER_CMD_BURST_SEND_START \ - 0x00000003 -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - 0x00000001 -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_SEND_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - 0x0000000b -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - 0x00000009 -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_QUICK_COMMAND \ - 0x00000027 -#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ - 0x00000013 -#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ - 0x00000046 -#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ - 0x00000046 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ - 0x00000042 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ - 0x00000040 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ - 0x00000044 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ - 0x0000004a -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ - 0x00000048 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ - 0x00000044 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 - -//***************************************************************************** -// -// I2C Master glitch filter configuration. -// -//***************************************************************************** -#define I2C_MASTER_GLITCH_FILTER_DISABLED \ - 0 -#define I2C_MASTER_GLITCH_FILTER_1 \ - 0x00010000 -#define I2C_MASTER_GLITCH_FILTER_2 \ - 0x00020000 -#define I2C_MASTER_GLITCH_FILTER_3 \ - 0x00030000 -#define I2C_MASTER_GLITCH_FILTER_4 \ - 0x00040000 -#define I2C_MASTER_GLITCH_FILTER_8 \ - 0x00050000 -#define I2C_MASTER_GLITCH_FILTER_16 \ - 0x00060000 -#define I2C_MASTER_GLITCH_FILTER_32 \ - 0x00070000 - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 -#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data -#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte -#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave -#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command -#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value - -//***************************************************************************** -// -// Miscellaneous I2C driver definitions. -// -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// I2C Master interrupts. -// -//***************************************************************************** -#define I2C_MASTER_INT_RX_FIFO_FULL \ - 0x00000800 // RX FIFO Full Interrupt -#define I2C_MASTER_INT_TX_FIFO_EMPTY \ - 0x00000400 // TX FIFO Empty Interrupt -#define I2C_MASTER_INT_RX_FIFO_REQ \ - 0x00000200 // RX FIFO Request Interrupt -#define I2C_MASTER_INT_TX_FIFO_REQ \ - 0x00000100 // TX FIFO Request Interrupt -#define I2C_MASTER_INT_ARB_LOST \ - 0x00000080 // Arb Lost Interrupt -#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt -#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt -#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt -#define I2C_MASTER_INT_TX_DMA_DONE \ - 0x00000008 // TX DMA Complete Interrupt -#define I2C_MASTER_INT_RX_DMA_DONE \ - 0x00000004 // RX DMA Complete Interrupt -#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt -#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt - -//***************************************************************************** -// -// I2C Slave interrupts. -// -//***************************************************************************** -#define I2C_SLAVE_INT_RX_FIFO_FULL \ - 0x00000100 // RX FIFO Full Interrupt -#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ - 0x00000080 // TX FIFO Empty Interrupt -#define I2C_SLAVE_INT_RX_FIFO_REQ \ - 0x00000040 // RX FIFO Request Interrupt -#define I2C_SLAVE_INT_TX_FIFO_REQ \ - 0x00000020 // TX FIFO Request Interrupt -#define I2C_SLAVE_INT_TX_DMA_DONE \ - 0x00000010 // TX DMA Complete Interrupt -#define I2C_SLAVE_INT_RX_DMA_DONE \ - 0x00000008 // RX DMA Complete Interrupt -#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt -#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt -#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt - -//***************************************************************************** -// -// I2C Slave FIFO configuration macros. -// -//***************************************************************************** -#define I2C_SLAVE_TX_FIFO_ENABLE \ - 0x00000002 -#define I2C_SLAVE_RX_FIFO_ENABLE \ - 0x00000004 - -//***************************************************************************** -// -// I2C FIFO configuration macros. -// -//***************************************************************************** -#define I2C_FIFO_CFG_TX_MASTER 0x00000000 -#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 -#define I2C_FIFO_CFG_RX_MASTER 0x00000000 -#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 -#define I2C_FIFO_CFG_TX_MASTER_DMA \ - 0x00002000 -#define I2C_FIFO_CFG_TX_SLAVE_DMA \ - 0x0000a000 -#define I2C_FIFO_CFG_RX_MASTER_DMA \ - 0x20000000 -#define I2C_FIFO_CFG_RX_SLAVE_DMA \ - 0xa0000000 -#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 -#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 -#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 -#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 -#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 -#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 -#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 -#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 -#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 -#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 -#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 -#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 -#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 -#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 -#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 -#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 -#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 -#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 - -//***************************************************************************** -// -// I2C FIFO status. -// -//***************************************************************************** -#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ - 0x00040000 -#define I2C_FIFO_RX_FULL 0x00020000 -#define I2C_FIFO_RX_EMPTY 0x00010000 -#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ - 0x00000004 -#define I2C_FIFO_TX_FULL 0x00000002 -#define I2C_FIFO_TX_EMPTY 0x00000001 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void)); -extern void I2CIntUnregister(uint32_t ui32Base); -extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CTxFIFOFlush(uint32_t ui32Base); -extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CRxFIFOFlush(uint32_t ui32Base); -extern uint32_t I2CFIFOStatus(uint32_t ui32Base); -extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); -extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, - uint8_t ui8Data); -extern uint32_t I2CFIFODataGet(uint32_t ui32Base); -extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, - uint8_t *pui8Data); -extern void I2CMasterBurstLengthSet(uint32_t ui32Base, - uint8_t ui8Length); -extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); -extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, - uint32_t ui32Config); -extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CSlaveFIFODisable(uint32_t ui32Base); -extern bool I2CMasterBusBusy(uint32_t ui32Base); -extern bool I2CMasterBusy(uint32_t ui32Base); -extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); -extern uint32_t I2CMasterDataGet(uint32_t ui32Base); -extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); -extern void I2CMasterDisable(uint32_t ui32Base); -extern void I2CMasterEnable(uint32_t ui32Base); -extern uint32_t I2CMasterErr(uint32_t ui32Base); -extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast); -extern void I2CMasterIntClear(uint32_t ui32Base); -extern void I2CMasterIntDisable(uint32_t ui32Base); -extern void I2CMasterIntEnable(uint32_t ui32Base); -extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); -extern void I2CMasterIntEnableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CMasterIntDisableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, - bool bMasked); -extern void I2CMasterIntClearEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); -extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); -extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); -extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); -extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, - uint8_t ui8SlaveAddr, - bool bReceive); -extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); -extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); -extern void I2CSlaveDisable(uint32_t ui32Base); -extern void I2CSlaveEnable(uint32_t ui32Base); -extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); -extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, - uint8_t ui8SlaveAddr); -extern void I2CSlaveIntClear(uint32_t ui32Base); -extern void I2CSlaveIntDisable(uint32_t ui32Base); -extern void I2CSlaveIntEnable(uint32_t ui32Base); -extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void I2CSlaveIntDisableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); -extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, - bool bMasked); -extern uint32_t I2CSlaveStatus(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_I2C_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.c deleted file mode 100644 index 7c19126021d..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.c +++ /dev/null @@ -1,1528 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// spi.c -// -// Driver for the SPI. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup SPI_Serial_Peripheral_Interface_api -//! @{ -// -//***************************************************************************** - - -#include "inc/hw_ints.h" -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_mcspi.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "ti_spi_driverlib.h" - - -//***************************************************************************** -// -// A mapping of SPI base address to interupt number. -// -//***************************************************************************** -static const unsigned long g_ppulSPIIntMap[][3] = -{ - { SSPI_BASE, INT_SSPI }, // Shared SPI - { GSPI_BASE, INT_GSPI }, // Generic SPI - { LSPI_BASE, INT_LSPI }, // LINK SPI -}; - -//***************************************************************************** -// -// A mapping of SPI base address to DMA done interrupt mask bit(s). -// -//***************************************************************************** -static const unsigned long g_ulSPIDmaMaskMap[][2]= -{ - {SSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK}, - {LSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK}, - {GSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK}, -}; - -//***************************************************************************** -// -//! \internal -//! Transfer bytes over SPI channel -//! -//! \param ulBase is the base address of SPI module -//! \param ucDout is the pointer to Tx data buffer or 0. -//! \param ucDin is pointer to Rx data buffer or 0 -//! \param ulCount is the size of data in bytes. -//! -//! This function transfers \e ulCount bytes of data over SPI channel. -//! -//! The function will not return until data has been transmitted -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout, - unsigned char *ucDin, unsigned long ulCount, - unsigned long ulFlags) -{ - unsigned long ulReadReg; - unsigned long ulWriteReg; - unsigned long ulStatReg; - unsigned long ulOutIncr; - unsigned long ulInIncr; - unsigned long ulTxDummy; - unsigned long ulRxDummy; - - // - // Initialize the variables - // - ulOutIncr = 1; - ulInIncr = 1; - - // - // Check if output buffer pointer is 0 - // - if(ucDout == 0) - { - ulOutIncr = 0; - ulTxDummy = 0xFFFFFFFF; - ucDout = (unsigned char *)&ulTxDummy; - } - - // - // Check if input buffer pointer is 0 - // - if(ucDin == 0) - { - ulInIncr = 0; - ucDin = (unsigned char *)&ulRxDummy; - } - - // - // Load the register addresses. - // - ulReadReg = (ulBase + MCSPI_O_RX0); - ulWriteReg = (ulBase + MCSPI_O_TX0); - ulStatReg = (ulBase + MCSPI_O_CH0STAT); - - // - // Enable CS based on Flag - // - if( ulFlags & SPI_CS_ENABLE) - { - HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; - } - - while(ulCount) - { - // - // Wait for space in output register/FIFO. - // - while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) - { - } - - // - // Write the data - // - HWREG(ulWriteReg) = *ucDout; - - // - // Wait for data in input register/FIFO. - // - while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) - { - } - - // - // Read the data - // - *ucDin = HWREG(ulReadReg); - - // - // Increment pointers. - // - ucDout = ucDout + ulOutIncr; - ucDin = ucDin + ulInIncr; - - // - // Decrement the count. - // - ulCount--; - } - - // - // Disable CS based on Flag - // - if( ulFlags & SPI_CS_DISABLE) - { - HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; - } - - return 0; -} - -//***************************************************************************** -// -//! \internal -//! Transfer half-words over SPI channel -//! -//! \param ulBase is the base address of SPI module -//! \param usDout is the pointer to Tx data buffer or 0. -//! \param usDin is pointer to Rx data buffer or 0 -//! \param ulCount is the size of data in bytes. -//! -//! This function transfers \e ulCount bytes of data over SPI channel. Since -//! the API sends a half-word at a time \e ulCount should be a multiple -//! of two. -//! -//! The function will not return until data has been transmitted -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -static long SPITransfer16(unsigned long ulBase, unsigned short *usDout, - unsigned short *usDin, unsigned long ulCount, - unsigned long ulFlags) -{ - unsigned long ulReadReg; - unsigned long ulWriteReg; - unsigned long ulStatReg; - unsigned long ulOutIncr; - unsigned long ulInIncr; - unsigned long ulTxDummy; - unsigned long ulRxDummy; - - // - // Initialize the variables. - // - ulOutIncr = 1; - ulInIncr = 1; - - // - // Check if count is multiple of half-word - // - if(ulCount%2) - { - return -1; - } - - // - // Compute number of half words. - // - ulCount = ulCount/2; - - // - // Check if output buffer pointer is 0 - // - if(usDout == 0) - { - ulOutIncr = 0; - ulTxDummy = 0xFFFFFFFF; - usDout = (unsigned short *)&ulTxDummy; - } - - // - // Check if input buffer pointer is 0 - // - if(usDin == 0) - { - ulInIncr = 0; - usDin = (unsigned short *)&ulRxDummy; - } - - // - // Load the register addresses. - // - ulReadReg = (ulBase + MCSPI_O_RX0); - ulWriteReg = (ulBase + MCSPI_O_TX0); - ulStatReg = (ulBase + MCSPI_O_CH0STAT); - - // - // Enable CS based on Flag - // - if( ulFlags & SPI_CS_ENABLE) - { - HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; - } - - while(ulCount) - { - // - // Wait for space in output register/FIFO. - // - while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) - { - } - - // - // Write the data - // - HWREG(ulWriteReg) = *usDout; - - // - // Wait for data in input register/FIFO. - // - while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) - { - } - - // - // Read the data - // - *usDin = HWREG(ulReadReg); - - // - // Increment pointers. - // - usDout = usDout + ulOutIncr; - usDin = usDin + ulInIncr; - - // - // Decrement the count. - // - ulCount--; - } - - // - // Disable CS based on Flag - // - if( ulFlags & SPI_CS_DISABLE) - { - HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; - } - - return 0; -} - -//***************************************************************************** -// -//! \internal -//! Transfer words over SPI channel -//! -//! \param ulBase is the base address of SPI module -//! \param ulDout is the pointer to Tx data buffer or 0. -//! \param ulDin is pointer to Rx data buffer or 0 -//! \param ulCount is the size of data in bytes. -//! -//! This function transfers \e ulCount bytes of data over SPI channel. Since -//! the API sends a word at a time \e ulCount should be a multiple of four. -//! -//! The function will not return until data has been transmitted -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout, - unsigned long *ulDin, unsigned long ulCount, - unsigned long ulFlags) -{ - unsigned long ulReadReg; - unsigned long ulWriteReg; - unsigned long ulStatReg; - unsigned long ulOutIncr; - unsigned long ulInIncr; - unsigned long ulTxDummy; - unsigned long ulRxDummy; - - // - // Initialize the variables. - // - ulOutIncr = 1; - ulInIncr = 1; - - // - // Check if count is multiple of word - // - if(ulCount%4) - { - return -1; - } - - // - // Compute the number of words to be transferd - // - ulCount = ulCount/4; - - // - // Check if output buffer pointer is 0 - // - if(ulDout == 0) - { - ulOutIncr = 0; - ulTxDummy = 0xFFFFFFFF; - ulDout = &ulTxDummy; - } - - // - // Check if input buffer pointer is 0 - // - if(ulDin == 0) - { - ulInIncr = 0; - ulDin = &ulRxDummy; - } - - - // - // Load the register addresses. - // - ulReadReg = (ulBase + MCSPI_O_RX0); - ulWriteReg = (ulBase + MCSPI_O_TX0); - ulStatReg = (ulBase + MCSPI_O_CH0STAT); - - // - // Enable CS based on Flag - // - if( ulFlags & SPI_CS_ENABLE) - { - HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; - } - - while(ulCount) - { - // - // Wait for space in output register/FIFO. - // - while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) - { - } - - // - // Write the data - // - HWREG(ulWriteReg) = *ulDout; - - // - // Wait for data in input register/FIFO. - // - while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) - { - } - - // - // Read the data - // - *ulDin = HWREG(ulReadReg); - - // - // Increment pointers. - // - ulDout = ulDout + ulOutIncr; - ulDin = ulDin + ulInIncr; - - // - // Decrement the count. - // - ulCount--; - } - - // - // Disable CS based on Flag - // - if( ulFlags & SPI_CS_DISABLE) - { - HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; - } - - return 0; -} - -//***************************************************************************** -// -//! \internal -//! Gets the SPI interrupt number. -//! -//! \param ulBase is the base address of the SPI module -//! -//! Given a SPI base address, returns the corresponding interrupt number. -//! -//! \return Returns a SPI interrupt number, or -1 if \e ulBase is invalid. -// -//***************************************************************************** -static long -SPIIntNumberGet(unsigned long ulBase) -{ - unsigned long ulIdx; - - // - // Loop through the table that maps SPI base addresses to interrupt - // numbers. - // - for(ulIdx = 0; ulIdx < (sizeof(g_ppulSPIIntMap) / - sizeof(g_ppulSPIIntMap[0])); ulIdx++) - { - // - // See if this base address matches. - // - if(g_ppulSPIIntMap[ulIdx][0] == ulBase) - { - // - // Return the corresponding interrupt number. - // - return(g_ppulSPIIntMap[ulIdx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(-1); -} - -//***************************************************************************** -// -//! \internal -//! Gets the SPI DMA interrupt mask bit. -//! -//! \param ulBase is the base address of the SPI module -//! -//! Given a SPI base address, DMA interrupt mask bit. -//! -//! \return Returns a DMA interrupt mask bit, or -1 if \e ulBase is invalid. -// -//***************************************************************************** -static long -SPIDmaMaskGet(unsigned long ulBase) -{ - unsigned long ulIdx; - - // - // Loop through the table that maps SPI base addresses to interrupt - // numbers. - // - for(ulIdx = 0; ulIdx < (sizeof(g_ulSPIDmaMaskMap) / - sizeof(g_ulSPIDmaMaskMap[0])); ulIdx++) - { - // - // See if this base address matches. - // - if(g_ulSPIDmaMaskMap[ulIdx][0] == ulBase) - { - // - // Return the corresponding interrupt number. - // - return(g_ulSPIDmaMaskMap[ulIdx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(-1); -} - -//***************************************************************************** -// -//! Enables transmitting and receiving. -//! -//! \param ulBase is the base address of the SPI module -//! -//! This function enables the SPI channel for transmitting and receiving. -//! -//! \return None -//! -// -//***************************************************************************** -void -SPIEnable(unsigned long ulBase) -{ - // - // Set Channel Enable Bit - // - HWREG(ulBase + MCSPI_O_CH0CTRL) |= MCSPI_CH0CTRL_EN; -} - -//***************************************************************************** -// -//! Disables the transmitting and receiving. -//! -//! \param ulBase is the base address of the SPI module -//! -//! This function disables the SPI channel for transmitting and receiving. -//! -//! \return None -//! -// -//***************************************************************************** -void -SPIDisable(unsigned long ulBase) -{ - // - // Reset Channel Enable Bit - // - HWREG(ulBase + MCSPI_O_CH0CTRL) &= ~MCSPI_CH0CTRL_EN; -} - - -//***************************************************************************** -// -//! Enables the SPI DMA operation for transmitting and/or receving. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulFlags selectes the DMA signal for transmit and/or receive. -//! -//! This function enables transmit and/or receive DMA request based on the -//! \e ulFlags parameter. -//! -//! The parameter \e ulFlags is the logical OR of one or more of -//! the following : -//! - \b SPI_RX_DMA -//! - \b SPI_TX_DMA -//! -//! \return None. -// -//***************************************************************************** -void -SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags) -{ - // - // Enable DMA based on ulFlags - // - HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags; -} - -//***************************************************************************** -// -//! Disables the SPI DMA operation for transmitting and/or receving. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulFlags selectes the DMA signal for transmit and/or receive. -//! -//! This function disables transmit and/or receive DMA request based on the -//! \e ulFlags parameter. -//! -//! The parameter \e ulFlags is the logical OR of one or more of -//! the following : -//! - \b SPI_RX_DMA -//! - \b SPI_TX_DMA -//! -//! \return None. -// -//***************************************************************************** -void -SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags) -{ - // - // Disable DMA based on ulFlags - // - HWREG(ulBase + MCSPI_O_CH0CONF) &= ~ulFlags; -} - -//***************************************************************************** -// -//! Performs a software reset of the specified SPI module -//! -//! \param ulBase is the base address of the SPI module -//! -//! This function performs a software reset of the specified SPI module -//! -//! \return None. -// -//***************************************************************************** -void -SPIReset(unsigned long ulBase) -{ - - // - // Assert soft reset (auto clear) - // - HWREG(ulBase + MCSPI_O_SYSCONFIG) |= MCSPI_SYSCONFIG_SOFTRESET; - - // - // wait until reset is done - // - while(!(HWREG(ulBase + MCSPI_O_SYSSTATUS)& MCSPI_SYSSTATUS_RESETDONE)) - { - } -} - -//***************************************************************************** -// -//! Sets the configuration of a SPI module -//! -//! \param ulBase is the base address of the SPI module -//! \param ulSPIClk is the rate of clock supplied to the SPI module. -//! \param ulBitRate is the desired bit rate.(master mode) -//! \param ulMode is the mode of operation. -//! \param ulSubMode is one of the valid sub-modes. -//! \param ulConfig is logical OR of configuration paramaters. -//! -//! This function configures SPI port for operation in specified sub-mode and -//! required bit rated as specified by \e ulMode and \e ulBitRate parameters -//! respectively. -//! -//! The SPI module can operate in either master or slave mode. The parameter -//! \e ulMode can be one of the following -//! -\b SPI_MODE_MASTER -//! -\b SPI_MODE_SLAVE -//! -//! The SPI module supports 4 sub modes based on SPI clock polarity and phase. -//! -//! 
-//! Polarity Phase  Sub-Mode
-//!   0       0        0
-//!   0       1        1
-//!   1       0        2
-//!   1       1        3
-//!
-//! -//! Required sub mode can be select by setting \e ulSubMode parameter to one -//! of the following -//! - \b SPI_SUB_MODE_0 -//! - \b SPI_SUB_MODE_1 -//! - \b SPI_SUB_MODE_2 -//! - \b SPI_SUB_MODE_3 -//! -//! The parameter \e ulConfig is logical OR of five values: the word length, -//! active level for chip select, software or hardware controled chip select, -//! 3 or 4 pin mode and turbo mode. -//! mode. -//! -//! SPI support 8, 16 and 32 bit word lengths defined by:- -//! - \b SPI_WL_8 -//! - \b SPI_WL_16 -//! - \b SPI_WL_32 -//! -//! Active state of Chip[ Selece can be defined by:- -//! - \b SPI_CS_ACTIVELOW -//! - \b SPI_CS_ACTIVEHIGH -//! -//! SPI chip select can be configured to be controlled either by hardware or -//! software:- -//! - \b SPI_SW_CS -//! - \b SPI_HW_CS -//! -//! The module can work in 3 or 4 pin mode defined by:- -//! - \b SPI_3PIN_MODE -//! - \b SPI_4PIN_MODE -//! -//! Turbo mode can be set on or turned off using:- -//! - \b SPI_TURBO_MODE_ON -//! - \b SPI_TURBO_MODE_OFF -//! -//! \return None. -// -//***************************************************************************** -void -SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, - unsigned long ulBitRate, unsigned long ulMode, - unsigned long ulSubMode, unsigned long ulConfig) -{ - - unsigned long ulRegData; - unsigned long ulDivider; - - // - // Read MODULCTRL register - // - ulRegData = HWREG(ulBase + MCSPI_O_MODULCTRL); - - // - // Set Master mode with h/w chip select - // - ulRegData &= ~(MCSPI_MODULCTRL_MS | - MCSPI_MODULCTRL_SINGLE); - - // - // Enable software control Chip Select, Init delay - // and 3-pin mode - // - ulRegData |= (((ulConfig >> 24) | ulMode) & 0xFF); - - // - // Write the configuration - // - HWREG(ulBase + MCSPI_O_MODULCTRL) = ulRegData; - - // - // Set IS, DPE0, DPE1 based on master or slave mode - // - if(ulMode == SPI_MODE_MASTER) - { - ulRegData = 0x1 << 16; - } - else - { - ulRegData = 0x6 << 16; - } - - // - // Mask the configurations and set clock divider granularity - // to 1 cycle - // - ulRegData = (ulRegData & (~(MCSPI_CH0CONF_WL_M | - MCSPI_CH0CONF_EPOL | - MCSPI_CH0CONF_POL | - MCSPI_CH0CONF_PHA | - MCSPI_CH0CONF_TURBO ) | - MCSPI_CH0CONF_CLKG)); - - // - // Get the divider value - // - ulDivider = ((ulSPIClk/ulBitRate) - 1); - - // - // The least significant four bits of the divider is used fo configure - // CLKD in MCSPI_CHCONF next eight least significant bits are used to - // configure the EXTCLK in MCSPI_CHCTRL - // - ulRegData |= ((ulDivider & 0x0000000F) << 2); - HWREG(ulBase + MCSPI_O_CH0CTRL) = ((ulDivider & 0x00000FF0) << 4); - - // - // Set the protocol, CS polarity, word length - // and turbo mode - // - ulRegData = ((ulRegData | - ulSubMode) | (ulConfig & 0x0008FFFF)); - - // - // Write back the CONF register - // - HWREG(ulBase + MCSPI_O_CH0CONF) = ulRegData; - -} - -//***************************************************************************** -// -//! Receives a word from the specified port. -//! -//! \param ulBase is the base address of the SPI module. -//! \param pulData is pointer to receive data variable. -//! -//! This function gets a SPI word from the receive FIFO for the specified -//! port. -//! -//! \return Returns the number of elements read from the receive FIFO. -// -//***************************************************************************** -long -SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) -{ - unsigned long ulRegVal; - - // - // Read register status register - // - ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT); - - // - // Check is data is available - // - if(ulRegVal & MCSPI_CH0STAT_RXS) - { - *pulData = HWREG(ulBase + MCSPI_O_RX0); - return(1); - } - - return(0); -} - -//***************************************************************************** -// -//! Waits for the word to be received on the specified port. -//! -//! \param ulBase is the base address of the SPI module. -//! \param pulData is pointer to receive data variable. -//! -//! This function gets a SPI word from the receive FIFO for the specified -//! port. If there is no word available, this function waits until a -//! word is received before returning. -//! -//! \return Returns the word read from the specified port, cast as an -//! \e unsigned long. -// -//***************************************************************************** -void -SPIDataGet(unsigned long ulBase, unsigned long *pulData) -{ - // - // Wait for Rx data - // - while(!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS)) - { - } - - // - // Read the value - // - *pulData = HWREG(ulBase + MCSPI_O_RX0); -} - -//***************************************************************************** -// -//! Transmits a word on the specified port. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulData is data to be transmitted. -//! -//! This function transmits a SPI word on the transmit FIFO for the specified -//! port. -//! -//! \return Returns the number of elements written to the transmit FIFO. -//! -//***************************************************************************** -long -SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) -{ - unsigned long ulRegVal; - - // - // Read status register - // - ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT); - - // - // Write value into Tx register/FIFO - // if space is available - // - if(ulRegVal & MCSPI_CH0STAT_TXS) - { - HWREG(ulBase + MCSPI_O_TX0) = ulData; - return(1); - } - - return(0); -} - -//***************************************************************************** -// -//! Waits until the word is transmitted on the specified port. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulData is data to be transmitted. -//! -//! This function transmits a SPI word on the transmit FIFO for the specified -//! port. This function waits until the space is available on transmit FIFO -//! -//! \return None -//! -//***************************************************************************** -void -SPIDataPut(unsigned long ulBase, unsigned long ulData) -{ - // - // Wait for space in FIFO - // - while(!(HWREG(ulBase + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS)) - { - } - - // - // Write the data - // - HWREG(ulBase + MCSPI_O_TX0) = ulData; -} - -//***************************************************************************** -// -//! Enables the transmit and/or receive FIFOs. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulFlags selects the FIFO(s) to be enabled -//! -//! This function enables the transmit and/or receive FIFOs as specified by -//! \e ulFlags. -//! The parameter \e ulFlags shoulde be logical OR of one or more of the -//! following: -//! - \b SPI_TX_FIFO -//! - \b SPI_RX_FIFO -//! -//! \return None. -// -//***************************************************************************** -void -SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags) -{ - // - // Set FIFO enable bits. - // - HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags; -} - -//***************************************************************************** -// -//! Disables the transmit and/or receive FIFOs. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulFlags selects the FIFO(s) to be enabled -//! -//! This function disables transmit and/or receive FIFOs. as specified by -//! \e ulFlags. -//! The parameter \e ulFlags shoulde be logical OR of one or more of the -//! following: -//! - \b SPI_TX_FIFO -//! - \b SPI_RX_FIFO -//! -//! \return None. -// -//***************************************************************************** -void -SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags) -{ - // - // Reset FIFO Enable bits. - // - HWREG(ulBase + MCSPI_O_CH0CONF) &= ~(ulFlags); -} - -//***************************************************************************** -// -//! Sets the FIFO level at which DMA requests or interrupts are generated. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulTxLevel is the Almost Empty Level for transmit FIFO. -//! \param ulRxLevel is the Almost Full Level for the receive FIFO. -//! -//! This function Sets the FIFO level at which DMA requests or interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulRxLevel) -{ - unsigned long ulRegVal; - - // - // Read the current configuration - // - ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); - - // - // Mask and set new FIFO thresholds. - // - ulRegVal = ((ulRegVal & 0xFFFF0000) | (((ulRxLevel-1) << 8) | (ulTxLevel-1))); - - // - // Set the transmit and receive FIFO thresholds. - // - HWREG(ulBase + MCSPI_O_XFERLEVEL) = ulRegVal; - -} - -//***************************************************************************** -// -//! Gets the FIFO level at which DMA requests or interrupts are generated. -//! -//! \param ulBase is the base address of the SPI module -//! \param pulTxLevel is a pointer to storage for the transmit FIFO level -//! \param pulRxLevel is a pointer to storage for the receive FIFO level -//! -//! This function gets the FIFO level at which DMA requests or interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void -SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, - unsigned long *pulRxLevel) -{ - unsigned long ulRegVal; - - // - // Read the current configuration - // - ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); - - *pulTxLevel = (ulRegVal & 0xFF); - - *pulRxLevel = ((ulRegVal >> 8) & 0xFF); - -} - -//***************************************************************************** -// -//! Sets the word count. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulWordCount is number of SPI words to be transmitted. -//! -//! This function sets the word count, which is the number of SPI word to -//! be transferred on channel when using the FIFO buffer. -//! -//! \return None. -// -//***************************************************************************** -void -SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount) -{ - unsigned long ulRegVal; - - // - // Read the current configuration - // - ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); - - // - // Mask and set the word count - // - HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF)| - (ulWordCount & 0xFFFF) << 16); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a SPI interrupt. -//! -//! \param ulBase is the base address of the SPI module -//! \param pfnHandler is a pointer to the function to be called when the -//! SPI interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! SPI interrupts must be enabled via SPIIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)) -{ - unsigned long ulInt; - - // - // Determine the interrupt number based on the SPI module - // - ulInt = SPIIntNumberGet(ulBase); - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnHandler); - - // - // Enable the SPI interrupt. - // - IntEnable(ulInt); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a SPI interrupt. -//! -//! \param ulBase is the base address of the SPI module -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a SPI interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntUnregister(unsigned long ulBase) -{ - unsigned long ulInt; - - // - // Determine the interrupt number based on the SPI module - // - ulInt = SPIIntNumberGet(ulBase); - - // - // Disable the interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} - -//***************************************************************************** -// -//! Enables individual SPI interrupt sources. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated SPI interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! - \b SPI_INT_DMATX -//! - \b SPI_INT_DMARX -//! - \b SPI_INT_EOW -//! - \b SPI_INT_RX_OVRFLOW -//! - \b SPI_INT_RX_FULL -//! - \b SPI_INT_TX_UDRFLOW -//! - \b SPI_INT_TX_EMPTY -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - unsigned long ulDmaMsk; - - // - // Enable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMATX) - { - ulDmaMsk = SPIDmaMaskGet(ulBase); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; - } - - // - // Enable DMA Rx Interrupt - // - if(ulIntFlags & SPI_INT_DMARX) - { - ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; - } - - // - // Enable the specific Interrupts - // - HWREG(ulBase + MCSPI_O_IRQENABLE) |= (ulIntFlags & 0x0003000F); -} - - -//***************************************************************************** -// -//! Disables individual SPI interrupt sources. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated SPI interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to SPIIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - unsigned long ulDmaMsk; - - // - // Disable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMATX) - { - ulDmaMsk = SPIDmaMaskGet(ulBase); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; - } - - // - // Disable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMARX) - { - ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; - } - - // - // Disable the specific Interrupts - // - HWREG(ulBase + MCSPI_O_IRQENABLE) &= ~(ulIntFlags & 0x0003000F); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the SPI module -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the specified SPI. -//! The status of interrupts that are allowed to reflect to the processor can -//! be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in SPIIntEnable(). -// -//***************************************************************************** -unsigned long -SPIIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - unsigned long ulIntStat; - unsigned long ulIntFlag; - unsigned long ulDmaMsk; - - // - // Get SPI interrupt status - // - ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F; - - if(bMasked) - { - ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE); - } - - // - // Get the interrupt bit - // - ulDmaMsk = SPIDmaMaskGet(ulBase); - - // - // Get the DMA interrupt status - // - if(bMasked) - { - ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED); - } - else - { - ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW); - } - - // - // Get SPI Tx DMA done status - // - if(ulIntStat & ulDmaMsk) - { - ulIntFlag |= SPI_INT_DMATX; - } - - // - // Get SPI Rx DMA done status - // - if(ulIntStat & (ulDmaMsk >> 1)) - { - ulIntFlag |= SPI_INT_DMARX; - } - - // - // Return status - // - return(ulIntFlag); -} - -//***************************************************************************** -// -//! Clears SPI interrupt sources. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified SPI interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to SPIIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - unsigned long ulDmaMsk; - - // - // Disable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMATX) - { - ulDmaMsk = SPIDmaMaskGet(ulBase); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; - } - - // - // Disable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMARX) - { - ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; - } - - // - // Clear Interrupts - // - HWREG(ulBase + MCSPI_O_IRQSTATUS) = (ulIntFlags & 0x0003000F); -} - -//***************************************************************************** -// -//! Enables the chip select in software controlled mode -//! -//! \param ulBase is the base address of the SPI module. -//! -//! This function enables the Chip select in software controlled mode. The -//! active state of CS will depend on the configuration done via -//! \sa SPIConfigExpClkSet(). -//! -//! \return None. -// -//***************************************************************************** -void SPICSEnable(unsigned long ulBase) -{ - // - // Set Chip Select enable bit. - // - HWREG( ulBase+MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; -} - -//***************************************************************************** -// -//! Disables the chip select in software controlled mode -//! -//! \param ulBase is the base address of the SPI module. -//! -//! This function disables the Chip select in software controlled mode. The -//! active state of CS will depend on the configuration done via -//! sa SPIConfigSetExpClk(). -//! -//! \return None. -// -//***************************************************************************** -void SPICSDisable(unsigned long ulBase) -{ - // - // Reset Chip Select enable bit. - // - HWREG( ulBase+MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; -} - -//***************************************************************************** -// -//! Send/Receive data buffer over SPI channel -//! -//! \param ulBase is the base address of SPI module -//! \param ucDout is the pointer to Tx data buffer or 0. -//! \param ucDin is pointer to Rx data buffer or 0 -//! \param ulCount is the size of data in bytes. -//! \param ulFlags controlls chip select toggling. -//! -//! This function transfers \e ulCount bytes of data over SPI channel. Since -//! the API sends a SPI word at a time \e ulCount should be a multiple of -//! word length set using SPIConfigSetExpClk(). -//! -//! If the \e ucDout parameter is set to 0, the function will send 0xFF over -//! the SPI MOSI line. -//! -//! If the \e ucDin parameter is set to 0, the function will ignore data on SPI -//! MISO line. -//! -//! The parameter \e ulFlags is logical OR of one or more of the following -//! -//! - \b SPI_CS_ENABLE if CS needs to be enabled at start of transfer. -//! - \b SPI_CS_DISABLE if CS need to be disabled at the end of transfer. -//! -//! This function will not return until data has been transmitted -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -long SPITransfer(unsigned long ulBase, unsigned char *ucDout, - unsigned char *ucDin, unsigned long ulCount, - unsigned long ulFlags) -{ - unsigned long ulWordLength; - long lRet; - - // - // Get the word length - // - ulWordLength = (HWREG(ulBase + MCSPI_O_CH0CONF) & MCSPI_CH0CONF_WL_M); - - // - // Check for word length. - // - if( !((ulWordLength == SPI_WL_8) || (ulWordLength == SPI_WL_16) || - (ulWordLength == SPI_WL_32)) ) - { - return -1; - } - - if( ulWordLength == SPI_WL_8 ) - { - // - // Do byte transfer - // - lRet = SPITransfer8(ulBase,ucDout,ucDin,ulCount,ulFlags); - } - else if( ulWordLength == SPI_WL_16 ) - { - - // - // Do half-word transfer - // - lRet = SPITransfer16(ulBase,(unsigned short *)ucDout, - (unsigned short *)ucDin,ulCount,ulFlags); - } - else - { - // - // Do word transfer - // - lRet = SPITransfer32(ulBase,(unsigned long *)ucDout, - (unsigned long *)ucDin,ulCount,ulFlags); - } - - // - // return - // - return lRet; - -} -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.h deleted file mode 100644 index 6a2aa50c90f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// spi.h -// -// Defines and Macros for the SPI. -// -//***************************************************************************** - -#ifndef __SPI_H__ -#define __SPI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter -//***************************************************************************** -#define SPI_MODE_MASTER 0x00000000 -#define SPI_MODE_SLAVE 0x00000004 - -//***************************************************************************** -// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter -//***************************************************************************** -#define SPI_SUB_MODE_0 0x00000000 -#define SPI_SUB_MODE_1 0x00000001 -#define SPI_SUB_MODE_2 0x00000002 -#define SPI_SUB_MODE_3 0x00000003 - - -//***************************************************************************** -// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter -//***************************************************************************** -#define SPI_SW_CTRL_CS 0x01000000 -#define SPI_HW_CTRL_CS 0x00000000 -#define SPI_3PIN_MODE 0x02000000 -#define SPI_4PIN_MODE 0x00000000 -#define SPI_TURBO_ON 0x00080000 -#define SPI_TURBO_OFF 0x00000000 -#define SPI_CS_ACTIVEHIGH 0x00000000 -#define SPI_CS_ACTIVELOW 0x00000040 -#define SPI_WL_8 0x00000380 -#define SPI_WL_16 0x00000780 -#define SPI_WL_32 0x00000F80 - -//***************************************************************************** -// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable() -//***************************************************************************** -#define SPI_TX_FIFO 0x08000000 -#define SPI_RX_FIFO 0x10000000 - -//***************************************************************************** -// Values that can be passed to SPIDMAEnable() and SPIDMADisable() -//***************************************************************************** -#define SPI_RX_DMA 0x00008000 -#define SPI_TX_DMA 0x00004000 - -//***************************************************************************** -// Values that can be passed to SPIIntEnable(), SPIIntDiasble(), -// SPIIntClear() or returned from SPIStatus() -//***************************************************************************** -#define SPI_INT_DMATX 0x20000000 -#define SPI_INT_DMARX 0x10000000 -#define SPI_INT_EOW 0x00020000 -#define SPI_INT_WKS 0x00010000 -#define SPI_INT_RX_OVRFLOW 0x00000008 -#define SPI_INT_RX_FULL 0x00000004 -#define SPI_INT_TX_UDRFLOW 0x00000002 -#define SPI_INT_TX_EMPTY 0x00000001 - -//***************************************************************************** -// Values that can be passed to SPITransfer() -//***************************************************************************** -#define SPI_CS_ENABLE 0x00000001 -#define SPI_CS_DISABLE 0x00000002 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void SPIEnable(unsigned long ulBase); -extern void SPIDisable(unsigned long ulBase); -extern void SPIReset(unsigned long ulBase); -extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, - unsigned long ulBitRate, unsigned long ulMode, - unsigned long ulSubMode, unsigned long ulConfig); -extern long SPIDataGetNonBlocking(unsigned long ulBase, - unsigned long * pulData); -extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SPIDataPutNonBlocking(unsigned long ulBase, - unsigned long ulData); -extern void SPIDataPut(unsigned long ulBase, unsigned long ulData); -extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags); -extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags); -extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulRxLevel); -extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, - unsigned long *pulRxLevel); -extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount); -extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void SPIIntUnregister(unsigned long ulBase); -extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags); -extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags); -extern void SPICSEnable(unsigned long ulBase); -extern void SPICSDisable(unsigned long ulBase); -extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout, - unsigned char *ucDin, unsigned long ulSize, - unsigned long ulFlags); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SPI_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.c deleted file mode 100644 index 33689376a0e..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.c +++ /dev/null @@ -1,1105 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// timer.c -// -// Driver for the timer module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup GPT_General_Purpose_Timer_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_timer.h" -#include "inc/hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "ti_timer.h" - - -//***************************************************************************** -// -//! \internal -//! Checks a timer base address. -//! -//! \param ulBase is the base address of the timer module. -//! -//! This function determines if a timer module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static tBoolean -TimerBaseValid(unsigned long ulBase) -{ - return((ulBase == TIMERA0_BASE) || (ulBase == TIMERA1_BASE) || - (ulBase == TIMERA2_BASE) || (ulBase == TIMERA3_BASE)); -} -#endif - -//***************************************************************************** -// -//! Enables the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function enables operation of the timer module. The timer must be -//! configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -TimerEnable(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Enable the timer(s) module. - // - HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); -} - -//***************************************************************************** -// -//! Disables the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to disable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function disables operation of the timer module. -//! -//! \return None. -// -//***************************************************************************** -void -TimerDisable(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Disable the timer module. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & - (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); -} - -//***************************************************************************** -// -//! Configures the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulConfig is the configuration for the timer. -//! -//! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured, and is left in the disabled -//! state. The 16/32-bit timer is comprised of two 16-bit timers that can -//! operate independently or be concatenated to form a 32-bit timer. -//! -//! The configuration is specified in \e ulConfig as one of the following -//! values: -//! -//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer -//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer -//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers -//! -//! When configured for a pair of half-width timers, each timer is separately -//! configured. The first timer is configured by setting \e ulConfig to -//! the result of a logical OR operation between one of the following values -//! and \e ulConfig: -//! -//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer -//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer -//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture -//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture -//! - \b TIMER_CFG_A_PWM - Half-width PWM output -//! -//! Similarly, the second timer is configured by setting \e ulConfig to -//! the result of a logical OR operation between one of the corresponding -//! \b TIMER_CFG_B_* values and \e ulConfig. -//! -//! \return None. -// -//***************************************************************************** -void -TimerConfigure(unsigned long ulBase, unsigned long ulConfig) -{ - - ASSERT( (ulConfig == TIMER_CFG_ONE_SHOT) || - (ulConfig == TIMER_CFG_ONE_SHOT_UP) || - (ulConfig == TIMER_CFG_PERIODIC) || - (ulConfig == TIMER_CFG_PERIODIC_UP) || - (((ulConfig & 0xff000000) == TIMER_CFG_SPLIT_PAIR) && - ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) || - (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))))); - - - // - // Enable CCP to IO path - // - HWREG(0x440260B0) = 0xFF; - - // - // Disable the timers. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); - - // - // Set the global timer configuration. - // - HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; - - // - // Set the configuration of the A and B timers. Note that the B timer - // configuration is ignored by the hardware in 32-bit modes. - // - HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; - HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; -} - -//***************************************************************************** -// -//! Controls the output level. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param bInvert specifies the output level. -//! -//! This function sets the PWM output level for the specified timer. If the -//! \e bInvert parameter is \b true, then the timer's output is made active -//! low; otherwise, it is made active high. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the output levels as requested. - // - ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; - HWREG(ulBase + TIMER_O_CTL) = (bInvert ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} - -//***************************************************************************** -// -//! Controls the event type. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ulEvent specifies the type of event; must be one of -//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or -//! \b TIMER_EVENT_BOTH_EDGES. -//! -//! This function sets the signal edge(s) that triggers the timer when in -//! capture mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the event type. - // - ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M); - HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & - ~(TIMER_CTL_TAEVENT_M | - TIMER_CTL_TBEVENT_M)) | ulEvent); -} - -//***************************************************************************** -// -//! Controls the stall handling. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bStall specifies the response to a stall signal. -//! -//! This function controls the stall response for the specified timer. If the -//! \e bStall parameter is \b true, then the timer stops counting if the -//! processor enters debug mode; otherwise the timer keeps running while in -//! debug mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the stall mode. - // - ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; - HWREG(ulBase + TIMER_O_CTL) = (bStall ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} - -//***************************************************************************** -// -//! Set the timer prescale value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale value which must be between 0 and 255 -//! (inclusive) for 16/32-bit timers. -//! -//! This function sets the value of the input clock prescaler. The prescaler -//! is only operational when in half-width mode and is used to extend the range -//! of the half-width timer modes. -//! -//! \return None. -// -//***************************************************************************** -void -TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - ASSERT(ulValue < 256); - - // - // Set the timer A prescaler if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAPR) = ulValue; - } - - // - // Set the timer B prescaler if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBPR) = ulValue; - } -} - - -//***************************************************************************** -// -//! Get the timer prescale value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler. The prescaler -//! is only operational when in half-width mode and is used to extend the range -//! of the half-width timer modes. -//! -//! \return The value of the timer prescaler. -// -//***************************************************************************** - -unsigned long -TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Return the appropriate prescale value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : - HWREG(ulBase + TIMER_O_TBPR)); -} - -//***************************************************************************** -// -//! Set the timer prescale match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale match value which must be between 0 -//! and 255 (inclusive) for 16/32-bit timers. -//! -//! This function sets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and the prescaler, -//! the prescale match effectively extends the range of the match. -//! -//! \note The availability of the prescaler match varies with the -//! part and timer mode in use. Please consult the datasheet for the part you -//! are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - ASSERT(ulValue < 256); - - // - // Set the timer A prescale match if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAPMR) = ulValue; - } - - // - // Set the timer B prescale match if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBPMR) = ulValue; - } -} - -//***************************************************************************** -// -//! Get the timer prescale match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and prescaler, the -//! prescale match effectively extends the range of the match. -//! -//! \note The availability of the prescaler match varies with the -//! part and timer mode in use. Please consult the datasheet for the part you -//! are using to determine whether this support is available. -//! -//! \return The value of the timer prescale match. -// -//***************************************************************************** -unsigned long -TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Return the appropriate prescale match value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : - HWREG(ulBase + TIMER_O_TBPMR)); -} - -//***************************************************************************** -// -//! Sets the timer load value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for full-width operation. -//! \param ulValue is the load value. -//! -//! This function sets the timer load value; if the timer is running then the -//! value is immediately loaded into the timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the timer A load value if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAILR) = ulValue; - } - - // - // Set the timer B load value if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBILR) = ulValue; - } -} - -//***************************************************************************** -// -//! Gets the timer load value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for full-width operation. -//! -//! This function gets the currently programmed interval load value for the -//! specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \return Returns the load value for the timer. -// -//***************************************************************************** -unsigned long -TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate load value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : - HWREG(ulBase + TIMER_O_TBILR)); -} - -//***************************************************************************** -// -//! Gets the current timer value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function reads the current value of the specified timer. -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -unsigned long -TimerValueGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate timer value. Ti SDK code reads TnR which is ticker count. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAV) : - HWREG(ulBase + TIMER_O_TBV)); -} - -//***************************************************************************** -// -//! Sets the current timer value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! \param ulValue is the new value of the timer to be set. -//! -//! This function sets the current value of the specified timer. -//! -//! \return None. -// -//***************************************************************************** -void -TimerValueSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Set the appropriate timer value. - // - if(ulTimer == TIMER_A) - { - HWREG(ulBase + TIMER_O_TAV) = ulValue; - } - else - { - HWREG(ulBase + TIMER_O_TBV) = ulValue; - } -} - - -//***************************************************************************** -// -//! Sets the timer match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for 32-bit operation. -//! \param ulValue is the match value. -//! -//! This function sets the match value for a timer. This is used in capture -//! count mode to determine when to interrupt the processor and in PWM mode to -//! determine the duty cycle of the output signal. -//! -//! \return None. -// -//***************************************************************************** -void -TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the timer A match value if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; - } - - // - // Set the timer B match value if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; - } -} - -//***************************************************************************** -// -//! Gets the timer match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function gets the match value for the specified timer. -//! -//! \return Returns the match value for the timer. -// -//******************************************************************************** -unsigned long -TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate match value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : - HWREG(ulBase + TIMER_O_TBMATCHR)); -} - - -//***************************************************************************** -// -//! Registers an interrupt handler for the timer interrupt. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param pfnHandler is a pointer to the function to be called when the timer -//! interrupt occurs. -//! -//! This function sets the handler to be called when a timer interrupt occurs. -//! In addition, this function enables the global interrupt in the interrupt -//! controller; specific timer interrupts must be enabled via TimerIntEnable(). -//! It is the interrupt handler's responsibility to clear the interrupt source -//! via TimerIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A : - ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A : - ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A))); - - // - // Register an interrupt handler for timer A if requested. - // - if(ulTimer & TIMER_A) - { - // - // Register the interrupt handler. - // - IntRegister(ulBase, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ulBase); - } - - // - // Register an interrupt handler for timer B if requested. - // - if(ulTimer & TIMER_B) - { - // - // Register the interrupt handler. - // - IntRegister(ulBase + 1, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ulBase + 1); - } -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the timer interrupt. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function clears the handler to be called when a timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - - ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A : - ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A : - ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A))); - - - - // - // Unregister the interrupt handler for timer A if requested. - // - if(ulTimer & TIMER_A) - { - // - // Disable the interrupt. - // - IntDisable(ulBase); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulBase); - } - - // - // Unregister the interrupt handler for timer B if requested. - // - if(ulTimer & TIMER_B) - { - // - // Disable the interrupt. - // - IntDisable(ulBase + 1); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulBase + 1); - } -} - -//***************************************************************************** -// -//! Enables individual timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The \e ulIntFlags parameter must be the logical OR of any combination of -//! the following: -//! -//! - \b TIMER_CAPB_EVENT - Capture B event interrupt -//! - \b TIMER_CAPB_MATCH - Capture B match interrupt -//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt -//! - \b TIMER_CAPA_EVENT - Capture A event interrupt -//! - \b TIMER_CAPA_MATCH - Capture A match interrupt -//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; -} - -//***************************************************************************** -// -//! Disables individual timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! Disables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to TimerIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the timer module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the timer module. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! values described in TimerIntEnable(). -// -//***************************************************************************** -unsigned long -TimerIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : - HWREG(ulBase + TIMER_O_RIS)); -} - -//***************************************************************************** -// -//! Clears timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to TimerIntEnable(). -//! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; -} - -//***************************************************************************** -// -//! Enables the events that can trigger a DMA request. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulDMAEvent is a bit mask of the events that can trigger DMA. -//! -//! This function enables the timer events that can trigger the start of a DMA -//! sequence. The DMA trigger events are specified in the \e ui32DMAEvent -//! parameter by passing in the logical OR of the following values: -//! -//! - \b TIMER_DMA_MODEMATCH_B - The mode match DMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_CAPEVENT_B - The capture event DMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_CAPMATCH_B - The capture match DMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_TIMEOUT_B - The timeout DMA trigger for timer B is enabled. -//! - \b TIMER_DMA_MODEMATCH_A - The mode match DMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_CAPEVENT_A - The capture event DMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_CAPMATCH_A - The capture match DMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_TIMEOUT_A - The timeout DMA trigger for timer A is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Set the DMA triggers. - // - HWREG(ulBase + TIMER_O_DMAEV) = ulDMAEvent; -} - -//***************************************************************************** -// -//! Returns the events that can trigger a DMA request. -//! -//! \param ulBase is the base address of the timer module. -//! -//! This function returns the timer events that can trigger the start of a DMA -//! sequence. The DMA trigger events are the logical OR of the following -//! values: -//! -//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match DMA trigger for timer -//! B. -//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event DMA trigger for -//! timer B. -//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match DMA trigger for -//! timer B. -//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout DMA trigger for timer B. -//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match DMA trigger for timer -//! A. -//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event DMA trigger for -//! timer A. -//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match DMA trigger for -//! timer A. -//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout DMA trigger for timer A. -//! -//! \return The timer events that trigger the uDMA. -// -//***************************************************************************** -unsigned long -TimerDMAEventGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Return the current DMA triggers. - // - return(HWREG(ulBase + TIMER_O_DMAEV)); -} -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.h deleted file mode 100644 index cd4275a164a..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// timer.h -// -// Prototypes for the timer module -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** - -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count - // timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count - // timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers - -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** - -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - - -//***************************************************************************** -// -// Values that can be passed to TimerSynchronize as the ulTimers parameter. -// -//***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B - -//***************************************************************************** -// -// Values that can be passed to TimerDMAEventSet() or returned from -// TimerDMAEventGet(). -// -//***************************************************************************** -#define TIMER_DMA_MODEMATCH_B 0x00000800 -#define TIMER_DMA_CAPEVENT_B 0x00000400 -#define TIMER_DMA_CAPMATCH_B 0x00000200 -#define TIMER_DMA_TIMEOUT_B 0x00000100 -#define TIMER_DMA_MODEMATCH_A 0x00000010 -#define TIMER_DMA_CAPEVENT_A 0x00000004 -#define TIMER_DMA_CAPMATCH_A 0x00000002 -#define TIMER_DMA_TIMEOUT_A 0x00000001 - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); - -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); - -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent); -extern unsigned long TimerDMAEventGet(unsigned long ulBase); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.c deleted file mode 100755 index 5d386cdc9e7..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.c +++ /dev/null @@ -1,1501 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// uart.c -// -// Driver for the UART. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup UART_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_uart.h" -#include "debug.h" -#include "interrupt.h" -#include "uart.h" - - -//***************************************************************************** -// -// A mapping of UART base address to interupt number. -// -//***************************************************************************** -static const unsigned long g_ppulUARTIntMap[][2] = -{ - { UARTA0_BASE, INT_UARTA0 }, - { UARTA1_BASE, INT_UARTA1 }, -}; - -//***************************************************************************** -// -//! \internal -//! Checks a UART base address. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function determines if a UART port base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static tBoolean -UARTBaseValid(unsigned long ulBase) -{ - return((ulBase == UARTA0_BASE) || (ulBase == UARTA1_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the UART interrupt number. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Given a UART base address, returns the corresponding interrupt number. -//! -//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid. -// -//***************************************************************************** -static long -UARTIntNumberGet(unsigned long ulBase) -{ - unsigned long ulIdx; - - // - // Loop through the table that maps UART base addresses to interrupt - // numbers. - // - for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) / - sizeof(g_ppulUARTIntMap[0])); ulIdx++) - { - // - // See if this base address matches. - // - if(g_ppulUARTIntMap[ulIdx][0] == ulBase) - { - // - // Return the corresponding interrupt number. - // - return(g_ppulUARTIntMap[ulIdx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(-1); -} - -//***************************************************************************** -// -//! Sets the type of parity. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulParity specifies the type of parity to use. -//! -//! This function sets the type of parity to use for transmitting and expect -//! when receiving. The \e ulParity parameter must be one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two allow -//! direct control of the parity bit; it is always either one or zero based on -//! the mode. -//! -//! \return None. -// -//***************************************************************************** -void -UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - ASSERT((ulParity == UART_CONFIG_PAR_NONE) || - (ulParity == UART_CONFIG_PAR_EVEN) || - (ulParity == UART_CONFIG_PAR_ODD) || - (ulParity == UART_CONFIG_PAR_ONE) || - (ulParity == UART_CONFIG_PAR_ZERO)); - - // - // Set the parity mode. - // - HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & - ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ulParity); -} - -//***************************************************************************** -// -//! Gets the type of parity currently being used. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function gets the type of parity used for transmitting data and -//! expected when receiving data. -//! -//! \return Returns the current parity settings, specified as one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. -// -//***************************************************************************** -unsigned long -UARTParityModeGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the current parity setting. - // - return(HWREG(ulBase + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! Sets the FIFO level at which interrupts are generated. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of -//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, -//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. -//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of -//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, -//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. -//! -//! This function sets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulRxLevel) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - ASSERT((ulTxLevel == UART_FIFO_TX1_8) || - (ulTxLevel == UART_FIFO_TX2_8) || - (ulTxLevel == UART_FIFO_TX4_8) || - (ulTxLevel == UART_FIFO_TX6_8) || - (ulTxLevel == UART_FIFO_TX7_8)); - ASSERT((ulRxLevel == UART_FIFO_RX1_8) || - (ulRxLevel == UART_FIFO_RX2_8) || - (ulRxLevel == UART_FIFO_RX4_8) || - (ulRxLevel == UART_FIFO_RX6_8) || - (ulRxLevel == UART_FIFO_RX7_8)); - - // - // Set the FIFO interrupt levels. - // - HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; -} - -//***************************************************************************** -// -//! Gets the FIFO level at which interrupts are generated. -//! -//! \param ulBase is the base address of the UART port. -//! \param pulTxLevel is a pointer to storage for the transmit FIFO level, -//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, -//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. -//! \param pulRxLevel is a pointer to storage for the receive FIFO level, -//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, -//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. -//! -//! This function gets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, - unsigned long *pulRxLevel) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Read the FIFO level register. - // - ulTemp = HWREG(ulBase + UART_O_IFLS); - - // - // Extract the transmit and receive FIFO levels. - // - *pulTxLevel = ulTemp & UART_IFLS_TX_M; - *pulRxLevel = ulTemp & UART_IFLS_RX_M; -} - -//***************************************************************************** -// -//! Sets the configuration of a UART. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulUARTClk is the rate of the clock supplied to the UART module. -//! \param ulBaud is the desired baud rate. -//! \param ulConfig is the data format for the port (number of data bits, -//! number of stop bits, and parity). -//! -//! This function configures the UART for operation in the specified data -//! format. The baud rate is provided in the \e ulBaud parameter and the data -//! format in the \e ulConfig parameter. -//! -//! The \e ulConfig parameter is the logical OR of three values: the number of -//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, -//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 -//! select from eight to five data bits per byte (respectively). -//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop -//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, -//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO -//! select the parity mode (no parity bit, even parity bit, odd parity bit, -//! parity bit always one, and parity bit always zero, respectively). -//! -//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). -//! -//! -//! \return None. -// -//***************************************************************************** -void -UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, - unsigned long ulBaud, unsigned long ulConfig) -{ - unsigned long ulDiv; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - ASSERT(ulBaud != 0); - - // - // Stop the UART. - // - UARTDisable(ulBase); - - // - // Is the required baud rate greater than the maximum rate supported - // without the use of high speed mode? - // - if((ulBaud * 16) > ulUARTClk) - { - // - // Enable high speed mode. - // - HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; - - // - // Half the supplied baud rate to compensate for enabling high speed - // mode. This allows the following code to be common to both cases. - // - ulBaud /= 2; - } - else - { - // - // Disable high speed mode. - // - HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); - } - - // - // Compute the fractional baud rate divider. - // - ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2; - - // - // Set the baud rate. - // - HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; - HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; - - // - // Set parity, data length, and number of stop bits. - // - HWREG(ulBase + UART_O_LCRH) = ulConfig; - - // - // Clear the flags register. - // - HWREG(ulBase + UART_O_FR) = 0; - - // - // Start the UART. - // - UARTEnable(ulBase); -} - -//***************************************************************************** -// -//! Gets the current configuration of a UART. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulUARTClk is the rate of the clock supplied to the UART module. -//! \param pulBaud is a pointer to storage for the baud rate. -//! \param pulConfig is a pointer to storage for the data format. -//! -//! The baud rate and data format for the UART is determined, given an -//! explicitly provided peripheral clock (hence the ExpClk suffix). The -//! returned baud rate is the actual baud rate; it may not be the exact baud -//! rate requested or an ``official'' baud rate. The data format returned in -//! \e pulConfig is enumerated the same as the \e ulConfig parameter of -//! UARTConfigSetExpClk(). -//! -//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). -//! -//! -//! \return None. -// -//***************************************************************************** -void -UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, - unsigned long *pulBaud, unsigned long *pulConfig) -{ - unsigned long ulInt, ulFrac; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Compute the baud rate. - // - ulInt = HWREG(ulBase + UART_O_IBRD); - ulFrac = HWREG(ulBase + UART_O_FBRD); - *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac); - - // - // See if high speed mode enabled. - // - if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE) - { - // - // High speed mode is enabled so the actual baud rate is actually - // double what was just calculated. - // - *pulBaud *= 2; - } - - // - // Get the parity, data length, and number of stop bits. - // - *pulConfig = (HWREG(ulBase + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | - UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! Enables transmitting and receiving. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit -//! and receive FIFOs. -//! -//! \return None. -// -//***************************************************************************** -void -UARTEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Enable the FIFO. - // - HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; - - // - // Enable RX, TX, and the UART. - // - HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! Disables transmitting and receiving. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of -//! transmission of the current character, and flushes the transmit FIFO. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Wait for end of TX. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) - { - } - - // - // Disable the FIFO. - // - HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); - - // - // Disable the UART. - // - HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! Enables the transmit and receive FIFOs. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This functions enables the transmit and receive FIFOs in the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Enable the FIFO. - // - HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; -} - -//***************************************************************************** -// -//! Disables the transmit and receive FIFOs. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This functions disables the transmit and receive FIFOs in the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFODisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Disable the FIFO. - // - HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); -} - -//***************************************************************************** -// -//! Sets the states of the RTS modem control signals. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulControl is a bit-mapped flag indicating which modem control bits -//! should be set. -//! -//! This function sets the states of the RTS modem handshake outputs -//! from the UART. -//! -//! The \e ulControl parameter is the logical OR of any of the following: -//! -//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal -//! -//! \note The availability of hardware modem handshake signals varies with the -//! part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTModemControlSet(unsigned long ulBase, unsigned long ulControl) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - - ASSERT(ulBase == UARTA1_BASE); - ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0); - - // - // Set the appropriate modem control output bits. - // - ulTemp = HWREG(ulBase + UART_O_CTL); - ulTemp |= (ulControl & (UART_OUTPUT_RTS)); - HWREG(ulBase + UART_O_CTL) = ulTemp; -} - -//***************************************************************************** -// -//! Clears the states of the RTS modem control signals. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulControl is a bit-mapped flag indicating which modem control bits -//! should be set. -//! -//! This function clears the states of the RTS modem handshake outputs -//! from the UART. -//! -//! The \e ulControl parameter is the logical OR of any of the following: -//! -//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal -//! -//! \note The availability of hardware modem handshake signals varies with the -//! part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - ASSERT(ulBase == UARTA1_BASE); - ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0); - - // - // Set the appropriate modem control output bits. - // - ulTemp = HWREG(ulBase + UART_O_CTL); - ulTemp &= ~(ulControl & (UART_OUTPUT_RTS)); - HWREG(ulBase + UART_O_CTL) = ulTemp; -} - -//***************************************************************************** -// -//! Gets the states of the RTS modem control signals. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current states of each of the UART modem -//! control signal, RTS. -//! -//! \note The availability of hardware modem handshake signals varies with the -//! part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return Returns the states of the handshake output signal. -// -//***************************************************************************** -unsigned long -UARTModemControlGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == UARTA1_BASE); - - return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS)); -} - -//***************************************************************************** -// -//! Gets the states of the CTS modem status signal. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current states of the UART modem status signal, -//! CTS. -//! -//! \note The availability of hardware modem handshake signals varies with the -//! part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return Returns the states of the handshake output signal -// -//***************************************************************************** -unsigned long -UARTModemStatusGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - - ASSERT(ulBase == UARTA1_BASE); - - return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_CTS)); -} - -//***************************************************************************** -// -//! Sets the UART hardware flow control mode to be used. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulMode indicates the flow control modes to be used. This parameter -//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and -//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) -//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. -//! -//! This function sets the required hardware flow control modes. If \e ulMode -//! contains flag \b UART_FLOWCONTROL_TX, data is only transmitted if the -//! incoming CTS signal is asserted. If \e ulMode contains flag -//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is -//! asserted only when there is space available in the receive FIFO. If no -//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be -//! passed. -//! -//! \note The availability of hardware flow control varies with the -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) -{ - // - // Check the arguments. - // - - ASSERT(UARTBaseValid(ulBase)); - ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); - - // - // Set the flow control mode as requested. - // - HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & - ~(UART_FLOWCONTROL_TX | - UART_FLOWCONTROL_RX)) | ulMode); -} - -//***************************************************************************** -// -//! Returns the UART hardware flow control mode currently in use. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current hardware flow control mode. -//! -//! \note The availability of hardware flow control varies with the -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns the current flow control mode in use. This is a -//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit -//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) -//! flow control is in use. If hardware flow control is disabled, -//! \b UART_FLOWCONTROL_NONE is returned. -// -//***************************************************************************** -unsigned long -UARTFlowControlGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - - ASSERT(UARTBaseValid(ulBase)); - - return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | - UART_FLOWCONTROL_RX)); -} - -//***************************************************************************** -// -//! Sets the operating mode for the UART transmit interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulMode is the operating mode for the transmit interrupt. It may be -//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle -//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO -//! level. -//! -//! This function allows the mode of the UART transmit interrupt to be set. By -//! default, the transmit interrupt is asserted when the FIFO level falls past -//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this -//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the -//! transmit interrupt is asserted once the transmitter is completely idle - -//! the transmit FIFO is empty and all bits, including any stop bits, have -//! cleared the transmitter. -//! -//! \note The availability of end-of-transmission mode varies with the -//! part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - ASSERT((ulMode == UART_TXINT_MODE_EOT) || - (ulMode == UART_TXINT_MODE_FIFO)); - - // - // Set or clear the EOT bit of the UART control register as appropriate. - // - HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & - ~(UART_TXINT_MODE_EOT | - UART_TXINT_MODE_FIFO)) | ulMode); -} - -//***************************************************************************** -// -//! Returns the current operating mode for the UART transmit interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current operating mode for the UART transmit -//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit -//! interrupt is currently set to be asserted once the transmitter is -//! completely idle - the transmit FIFO is empty and all bits, including any -//! stop bits, have cleared the transmitter. The return value is -//! \b UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon -//! the level of the transmit FIFO. -//! -//! \note The availability of end-of-transmission mode varies with the -//! part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. -// -//***************************************************************************** -unsigned long -UARTTxIntModeGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the current transmit interrupt mode. - // - return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT | - UART_TXINT_MODE_FIFO)); -} - -//***************************************************************************** -// -//! Determines if there are any characters in the receive FIFO. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is data -//! available in the receive FIFO. -//! -//! \return Returns \b true if there is data in the receive FIFO or \b false -//! if there is no data in the receive FIFO. -// -//***************************************************************************** -tBoolean -UARTCharsAvail(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the availability of characters. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); -} - -//***************************************************************************** -// -//! Determines if there is any space in the transmit FIFO. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is space -//! available in the transmit FIFO. -//! -//! \return Returns \b true if there is space available in the transmit FIFO -//! or \b false if there is no space available in the transmit FIFO. -// -//***************************************************************************** -tBoolean -UARTSpaceAvail(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the availability of space. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); -} - -//***************************************************************************** -// -//! Receives a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. -//! -//! -//! \return Returns the character read from the specified port, cast as a -//! \e long. A \b -1 is returned if there are no characters present in the -//! receive FIFO. The UARTCharsAvail() function should be called before -//! attempting to call this function. -// -//***************************************************************************** -long -UARTCharGetNonBlocking(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // See if there are any characters in the receive FIFO. - // - if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) - { - // - // Read and return the next character. - // - return(HWREG(ulBase + UART_O_DR)); - } - else - { - // - // There are no characters, so return a failure. - // - return(-1); - } -} - -//***************************************************************************** -// -//! Waits for a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. If there are no characters available, this function waits until a -//! character is received before returning. -//! -//! \return Returns the character read from the specified port, cast as a -//! \e long. -// -//***************************************************************************** -long -UARTCharGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Wait until a char is available. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) - { - } - - // - // Now get the char. - // - return(HWREG(ulBase + UART_O_DR)); -} - -//***************************************************************************** -// -//! Sends a character to the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! This function writes the character \e ucData to the transmit FIFO for the -//! specified port. This function does not block, so if there is no space -//! available, then a \b false is returned, and the application must retry the -//! function later. -//! -//! \return Returns \b true if the character was successfully placed in the -//! transmit FIFO or \b false if there was no space available in the transmit -//! FIFO. -// -//***************************************************************************** -tBoolean -UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // See if there is space in the transmit FIFO. - // - if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) - { - // - // Write this character to the transmit FIFO. - // - HWREG(ulBase + UART_O_DR) = ucData; - - // - // Success. - // - return(true); - } - else - { - // - // There is no space in the transmit FIFO, so return a failure. - // - return(false); - } -} - -//***************************************************************************** -// -//! Waits to send a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! This function sends the character \e ucData to the transmit FIFO for the -//! specified port. If there is no space available in the transmit FIFO, this -//! function waits until there is space available before returning. -//! -//! \return None. -// -//***************************************************************************** -void -UARTCharPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Wait until space is available. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) - { - } - - // - // Send the char. - // - HWREG(ulBase + UART_O_DR) = ucData; -} - -//***************************************************************************** -// -//! Causes a BREAK to be sent. -//! -//! \param ulBase is the base address of the UART port. -//! \param bBreakState controls the output level. -//! -//! Calling this function with \e bBreakState set to \b true asserts a break -//! condition on the UART. Calling this function with \e bBreakState set to -//! \b false removes the break condition. For proper transmission of a break -//! command, the break must be asserted for at least two complete frames. -//! -//! \return None. -// -//***************************************************************************** -void -UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Set the break condition as requested. - // - HWREG(ulBase + UART_O_LCRH) = - (bBreakState ? - (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK))); -} - -//***************************************************************************** -// -//! Determines whether the UART transmitter is busy or not. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \b false is returned, the transmit FIFO is -//! empty and all bits of the last transmitted character, including all stop -//! bits, have left the hardware shift register. -//! -//! \return Returns \b true if the UART is transmitting or \b false if all -//! transmissions are complete. -// -//***************************************************************************** -tBoolean -UARTBusy(unsigned long ulBase) -{ - // - // Check the argument. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Determine if the UART is busy. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a UART interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Determine the interrupt number based on the UART port. - // - - ulInt = UARTIntNumberGet(ulBase); - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnHandler); - - // - // Enable the UART interrupt. - // - IntEnable(ulInt); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a UART interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a UART interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntUnregister(unsigned long ulBase) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Determine the interrupt number based on the UART port. - // - ulInt = UARTIntNumberGet(ulBase); - - // - // Disable the interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} - -//***************************************************************************** -// -//! Enables individual UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! - \b UART_INT_OE - Overrun Error interrupt -//! - \b UART_INT_BE - Break Error interrupt -//! - \b UART_INT_PE - Parity Error interrupt -//! - \b UART_INT_FE - Framing Error interrupt -//! - \b UART_INT_RT - Receive Timeout interrupt -//! - \b UART_INT_TX - Transmit interrupt -//! - \b UART_INT_RX - Receive interrupt -//! - \b UART_INT_CTS - CTS interrupt -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + UART_O_IM) |= ulIntFlags; -} - -//***************************************************************************** -// -//! Disables individual UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to UARTIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the UART port. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the specified UART. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in UARTIntEnable(). -// -//***************************************************************************** -unsigned long -UARTIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + UART_O_MIS)); - } - else - { - return(HWREG(ulBase + UART_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified UART interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to UARTIntEnable(). -//! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + UART_O_ICR) = ulIntFlags; -} - -//***************************************************************************** -// -//! Enable UART DMA operation. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulDMAFlags is a bit mask of the DMA features to enable. -//! -//! The specified UART DMA features are enabled. The UART can be -//! configured to use DMA for transmit or receive, and to disable -//! receive if an error occurs. The \e ulDMAFlags parameter is the -//! logical OR of any of the following values: -//! -//! - UART_DMA_RX - enable DMA for receive -//! - UART_DMA_TX - enable DMA for transmit -//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Set the requested bits in the UART DMA control register. - // - HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags; -} - -//***************************************************************************** -// -//! Disable UART DMA operation. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulDMAFlags is a bit mask of the DMA features to disable. -//! -//! This function is used to disable UART DMA features that were enabled -//! by UARTDMAEnable(). The specified UART DMA features are disabled. The -//! \e ulDMAFlags parameter is the logical OR of any of the following values: -//! -//! - UART_DMA_RX - disable DMA for receive -//! - UART_DMA_TX - disable DMA for transmit -//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error -//! -//! \return None. -// -//***************************************************************************** -void -UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Clear the requested bits in the UART DMA control register. - // - HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags; -} - -//***************************************************************************** -// -//! Gets current receiver errors. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current state of each of the 4 receiver error -//! sources. The returned errors are equivalent to the four error bits -//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() -//! with the exception that the overrun error is set immediately the overrun -//! occurs rather than when a character is next read. -//! -//! \return Returns a logical OR combination of the receiver error flags, -//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK -//! and \b UART_RXERROR_OVERRUN. -// -//***************************************************************************** -unsigned long -UARTRxErrorGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the current value of the receive status register. - // - return(HWREG(ulBase + UART_O_RSR) & 0x0000000F); -} - -//***************************************************************************** -// -//! Clears all reported receiver errors. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function is used to clear all receiver error conditions reported via -//! UARTRxErrorGet(). If using the overrun, framing error, parity error or -//! break interrupts, this function must be called after clearing the interrupt -//! to ensure that later errors of the same type trigger another interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -UARTRxErrorClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Any write to the Error Clear Register will clear all bits which are - // currently set. - // - HWREG(ulBase + UART_O_ECR) = 0; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.h deleted file mode 100755 index ba03c2fb515..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// uart.h -// -// Defines and Macros for the UART. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_DMATX 0x20000 // DMA Tx Done interrupt Mask -#define UART_INT_DMARX 0x10000 // DMA Rx Done interrupt Mask -#define UART_INT_EOT 0x800 // End of transfer interrupt Mask -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask -#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask - - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter -// and returned by UARTConfigGetExpClk in the pulConfig parameter. -// Additionally, the UART_CONFIG_PAR_* subset can be passed to -// UARTParityModeSet as the ulParity parameter, and are returned by -// UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and -// returned by UARTFIFOLevelGet in the pulTxLevel. -// -//***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and -// returned by UARTFIFOLevelGet in the pulRxLevel. -// -//***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). -// -//***************************************************************************** -#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error -#define UART_DMA_TX 0x00000002 // Enable DMA for transmit -#define UART_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// Values returned from UARTRxErrorGet(). -// -//***************************************************************************** -#define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to UARTModemControlSet()and UARTModemControlClear() -// or returned from UARTModemControlGet(). -// -//***************************************************************************** -#define UART_OUTPUT_RTS 0x00000800 - -//***************************************************************************** -// -// Values that can be returned from UARTModemStatusGet(). -// -//***************************************************************************** -#define UART_INPUT_CTS 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to UARTFlowControl() or returned from -// UARTFlowControlGet(). -// -//***************************************************************************** -#define UART_FLOWCONTROL_TX 0x00008000 -#define UART_FLOWCONTROL_RX 0x00004000 -#define UART_FLOWCONTROL_NONE 0x00000000 - -//***************************************************************************** -// -// Values that can be passed to UARTTxIntModeSet() or returned from -// UARTTxIntModeGet(). -// -//***************************************************************************** -#define UART_TXINT_MODE_FIFO 0x00000000 -#define UART_TXINT_MODE_EOT 0x00000010 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulRxLevel); -extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, - unsigned long *pulRxLevel); -extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, - unsigned long ulBaud, unsigned long ulConfig); -extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, - unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern void UARTFIFOEnable(unsigned long ulBase); -extern void UARTFIFODisable(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharGetNonBlocking(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern tBoolean UARTBusy(unsigned long ulBase); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); -extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); -extern unsigned long UARTRxErrorGet(unsigned long ulBase); -extern void UARTRxErrorClear(unsigned long ulBase); -extern void UARTModemControlSet(unsigned long ulBase, - unsigned long ulControl); -extern void UARTModemControlClear(unsigned long ulBase, - unsigned long ulControl); -extern unsigned long UARTModemControlGet(unsigned long ulBase); -extern unsigned long UARTModemStatusGet(unsigned long ulBase); -extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode); -extern unsigned long UARTFlowControlGet(unsigned long ulBase); -extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode); -extern unsigned long UARTTxIntModeGet(unsigned long ulBase); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.c deleted file mode 100755 index 001cbb8793a..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.c +++ /dev/null @@ -1,1257 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// udma.c -// -// Driver for the micro-DMA controller. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup uDMA_Micro_Direct_Memory_Access_api -//! @{ -// -//***************************************************************************** - - -#include "inc/hw_types.h" -#include "inc/hw_udma.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "debug.h" -#include "interrupt.h" -#include "udma.h" - - -//***************************************************************************** -// -//! Enables the uDMA controller for use. -//! -//! This function enables the uDMA controller. The uDMA controller must be -//! enabled before it can be configured and used. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAEnable(void) -{ - // - // Set the master enable bit in the config register. - // - HWREG(UDMA_BASE + UDMA_O_CFG) = UDMA_CFG_MASTEN; -} - -//***************************************************************************** -// -//! Disables the uDMA controller for use. -//! -//! This function disables the uDMA controller. Once disabled, the uDMA -//! controller cannot operate until re-enabled with uDMAEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -uDMADisable(void) -{ - // - // Clear the master enable bit in the config register. - // - HWREG(UDMA_BASE + UDMA_O_CFG) = 0; -} - -//***************************************************************************** -// -//! Gets the uDMA error status. -//! -//! This function returns the uDMA error status. It should be called from -//! within the uDMA error interrupt handler to determine if a uDMA error -//! occurred. -//! -//! \return Returns non-zero if a uDMA error is pending. -// -//***************************************************************************** -unsigned long -uDMAErrorStatusGet(void) -{ - // - // Return the uDMA error status. - // - return(HWREG(UDMA_BASE + UDMA_O_ERRCLR)); -} - -//***************************************************************************** -// -//! Clears the uDMA error interrupt. -//! -//! This function clears a pending uDMA error interrupt. This function should -//! be called from within the uDMA error interrupt handler to clear the -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAErrorStatusClear(void) -{ - // - // Clear the uDMA error interrupt. - // - HWREG(UDMA_BASE + UDMA_O_ERRCLR) = 1; -} - -//***************************************************************************** -// -//! Enables a uDMA channel for operation. -//! -//! \param ulChannelNum is the channel number to enable. -//! -//! This function enables a specific uDMA channel for use. This function must -//! be used to enable a channel before it can be used to perform a uDMA -//! transfer. -//! -//! When a uDMA transfer is completed, the channel is automatically disabled by -//! the uDMA controller. Therefore, this function should be called prior to -//! starting up any new transfer. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelEnable(unsigned long ulChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the enable set register. - // - HWREG(UDMA_BASE + UDMA_O_ENASET) = 1 << (ulChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Disables a uDMA channel for operation. -//! -//! \param ulChannelNum is the channel number to disable. -//! -//! This function disables a specific uDMA channel. Once disabled, a channel -//! cannot respond to uDMA transfer requests until re-enabled via -//! uDMAChannelEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelDisable(unsigned long ulChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the enable clear register. - // - HWREG(UDMA_BASE + UDMA_O_ENACLR) = 1 << (ulChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Checks if a uDMA channel is enabled for operation. -//! -//! \param ulChannelNum is the channel number to check. -//! -//! This function checks to see if a specific uDMA channel is enabled. This -//! function can be used to check the status of a transfer, as the channel is -//! automatically disabled at the end of a transfer. -//! -//! \return Returns \b true if the channel is enabled, \b false if disabled. -// -//***************************************************************************** -tBoolean -uDMAChannelIsEnabled(unsigned long ulChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // AND the specified channel bit with the enable register and return the - // result. - // - return((HWREG(UDMA_BASE + UDMA_O_ENASET) & - (1 << (ulChannelNum & 0x1f))) ? true : false); -} - -//***************************************************************************** -// -//! Sets the base address for the channel control table. -//! -//! \param pControlTable is a pointer to the 1024-byte-aligned base address -//! of the uDMA channel control table. -//! -//! This function configures the base address of the channel control table. -//! This table resides in system memory and holds control information for each -//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base -//! address must be configured before any of the channel functions can be used. -//! -//! The size of the channel control table depends on the number of uDMA -//! channels and the transfer modes that are used. Refer to the introductory -//! text and the microcontroller datasheet for more information about the -//! channel control table. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAControlBaseSet(void *pControlTable) -{ - // - // Check the arguments. - // - ASSERT(((unsigned long)pControlTable & ~0x3FF) == - (unsigned long)pControlTable); - ASSERT((unsigned long)pControlTable >= 0x20000000); - - // - // Program the base address into the register. - // - HWREG(UDMA_BASE + UDMA_O_CTLBASE) = (unsigned long)pControlTable; -} - -//***************************************************************************** -// -//! Gets the base address for the channel control table. -//! -//! This function gets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. -//! -//! \return Returns a pointer to the base address of the channel control table. -// -//***************************************************************************** -void * -uDMAControlBaseGet(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return((void *)HWREG(UDMA_BASE + UDMA_O_CTLBASE)); -} - -//***************************************************************************** -// -//! Gets the base address for the channel control table alternate structures. -//! -//! This function gets the base address of the second half of the channel -//! control table that holds the alternate control structures for each channel. -//! -//! \return Returns a pointer to the base address of the second half of the -//! channel control table. -// -//***************************************************************************** -void * -uDMAControlAlternateBaseGet(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return((void *)HWREG(UDMA_BASE + UDMA_O_ALTBASE)); -} - -//***************************************************************************** -// -//! Requests a uDMA channel to start a transfer. -//! -//! \param ulChannelNum is the channel number on which to request a uDMA -//! transfer. -//! -//! This function allows software to request a uDMA channel to begin a -//! transfer. This function could be used for performing a memory-to-memory -//! transfer or if for some reason, a transfer needs to be initiated by software -//! instead of the peripheral associated with that channel. -//! -//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then -//! the completion is signaled on the uDMA dedicated interrupt. If a -//! peripheral channel is used, then the completion is signaled on the -//! peripheral's interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelRequest(unsigned long ulChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the software uDMA request register. - // - HWREG(UDMA_BASE + UDMA_O_SWREQ) = 1 << (ulChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Enables attributes of a uDMA channel. -//! -//! \param ulChannelNum is the channel to configure. -//! \param ulAttr is a combination of attributes for the channel. -//! -//! This function is used to enable attributes of a uDMA channel. -//! -//! The \e ulAttr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelNum parameter, extract just the channel number - // from this parameter. - // - ulChannelNum &= 0x1f; - - // - // Set the useburst bit for this channel if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_USEBURST) - { - HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) = 1 << ulChannelNum; - } - - // - // Set the alternate control select bit for this channel, - // if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_ALTSELECT) - { - HWREG(UDMA_BASE + UDMA_O_ALTSET) = 1 << ulChannelNum; - } - - // - // Set the high priority bit for this channel, if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(UDMA_BASE + UDMA_O_PRIOSET) = 1 << ulChannelNum; - } - - // - // Set the request mask bit for this channel, if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_REQMASK) - { - HWREG(UDMA_BASE + UDMA_O_REQMASKSET) = 1 << ulChannelNum; - } -} - -//***************************************************************************** -// -//! Disables attributes of a uDMA channel. -//! -//! \param ulChannelNum is the channel to configure. -//! \param ulAttr is a combination of attributes for the channel. -//! -//! This function is used to disable attributes of a uDMA channel. -//! -//! The \e ulAttr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelNum parameter, extract just the channel number - // from this parameter. - // - ulChannelNum &= 0x1f; - - // - // Clear the useburst bit for this channel if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_USEBURST) - { - HWREG(UDMA_BASE + UDMA_O_USEBURSTCLR) = 1 << ulChannelNum; - } - - // - // Clear the alternate control select bit for this channel, if set in - // ulConfig. - // - if(ulAttr & UDMA_ATTR_ALTSELECT) - { - HWREG(UDMA_BASE + UDMA_O_ALTCLR) = 1 << ulChannelNum; - } - - // - // Clear the high priority bit for this channel, if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(UDMA_BASE + UDMA_O_PRIOCLR) = 1 << ulChannelNum; - } - - // - // Clear the request mask bit for this channel, if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_REQMASK) - { - HWREG(UDMA_BASE + UDMA_O_REQMASKCLR) = 1 << ulChannelNum; - } -} - -//***************************************************************************** -// -//! Gets the enabled attributes of a uDMA channel. -//! -//! \param ulChannelNum is the channel to configure. -//! -//! This function returns a combination of flags representing the attributes of -//! the uDMA channel. -//! -//! \return Returns the logical OR of the attributes of the uDMA channel, which -//! can be any of the following: -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -// -//***************************************************************************** -unsigned long -uDMAChannelAttributeGet(unsigned long ulChannelNum) -{ - unsigned long ulAttr = 0; - - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelNum parameter, extract just the channel number - // from this parameter. - // - ulChannelNum &= 0x1f; - - // - // Check to see if useburst bit is set for this channel. - // - if(HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) & (1 << ulChannelNum)) - { - ulAttr |= UDMA_ATTR_USEBURST; - } - - // - // Check to see if the alternate control bit is set for this channel. - // - if(HWREG(UDMA_BASE + UDMA_O_ALTSET) & (1 << ulChannelNum)) - { - ulAttr |= UDMA_ATTR_ALTSELECT; - } - - // - // Check to see if the high priority bit is set for this channel. - // - if(HWREG(UDMA_BASE + UDMA_O_PRIOSET) & (1 << ulChannelNum)) - { - ulAttr |= UDMA_ATTR_HIGH_PRIORITY; - } - - // - // Check to see if the request mask bit is set for this channel. - // - if(HWREG(UDMA_BASE + UDMA_O_REQMASKSET) & (1 << ulChannelNum)) - { - ulAttr |= UDMA_ATTR_REQMASK; - } - - // - // Return the configuration flags. - // - return(ulAttr); -} - -//***************************************************************************** -// -//! Sets the control parameters for a uDMA channel control structure. -//! -//! \param ulChannelStructIndex is the logical OR of the uDMA channel number -//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param ulControl is logical OR of several control values to set the control -//! parameters for the channel. -//! -//! This function is used to set control parameters for a uDMA transfer. These -//! parameters are typically not changed often. -//! -//! The \e ulChannelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e ulControl parameter is the logical OR of five values: the data size, -//! the source address increment, the destination address increment, the -//! arbitration size, and the use burst flag. The choices available for each -//! of these values is described below. -//! -//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or -//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. -//! -//! Choose the source address increment from one of \b UDMA_SRC_INC_8, -//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or -//! to select non-incrementing. -//! -//! Choose the destination address increment from one of \b UDMA_DST_INC_8, -//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or -//! to select non-incrementing. -//! -//! The arbitration size determines how many items are transferred before -//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size -//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, -//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 -//! items, in powers of 2. -//! -//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only -//! respond to burst requests at the tail end of a scatter-gather transfer. -//! -//! \note The address increment cannot be smaller than the data size. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelControlSet(unsigned long ulChannelStructIndex, - unsigned long ulControl) -{ - tDMAControlTable *pCtl; - - // - // Check the arguments. - // - ASSERT((ulChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ulChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pCtl = (tDMAControlTable *)HWREG(UDMA_BASE+UDMA_O_CTLBASE); - - // - // Get the current control word value and mask off the fields to be - // changed, then OR in the new settings. - // - pCtl[ulChannelStructIndex].ulControl = - ((pCtl[ulChannelStructIndex].ulControl & - ~(UDMA_CHCTL_DSTINC_M | - UDMA_CHCTL_DSTSIZE_M | - UDMA_CHCTL_SRCINC_M | - UDMA_CHCTL_SRCSIZE_M | - UDMA_CHCTL_ARBSIZE_M | - UDMA_CHCTL_NXTUSEBURST)) | - ulControl); -} - -//***************************************************************************** -// -//! Sets the transfer parameters for a uDMA channel control structure. -//! -//! \param ulChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param ulMode is the type of uDMA transfer. -//! \param pvSrcAddr is the source address for the transfer. -//! \param pvDstAddr is the destination address for the transfer. -//! \param ulTransferSize is the number of data items to transfer. -//! -//! This function is used to configure the parameters for a uDMA transfer. -//! These parameters are typically changed often. The function -//! uDMAChannelControlSet() MUST be called at least once for this channel prior -//! to calling this function. -//! -//! The \e ulChannelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e ulMode parameter should be one of the following values: -//! -//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode -//! to this value at the end of a transfer. -//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. -//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once -//! started even if the request is removed. -//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the -//! primary and alternate control structures for the channel. This mode -//! allows use of ping-pong buffering for uDMA transfers. -//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather -//! transfer. -//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather -//! transfer. -//! -//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first -//! location of the data to be transferred. These addresses should be aligned -//! according to the item size. For example, if the item size is set to 4-bytes, -//! these addresses must be 4-byte aligned. The compiler can take care of this -//! alignment if the pointers are pointing to storage of the appropriate -//! data type. -//! -//! The \e ulTransferSize parameter is the number of data items, not the number -//! of bytes. The value of this parameter should not exceed 1024. -//! -//! The two scatter-gather modes, memory and peripheral, are actually different -//! depending on whether the primary or alternate control structure is -//! selected. This function looks for the \b UDMA_PRI_SELECT and -//! \b UDMA_ALT_SELECT flag along with the channel number and sets the -//! scatter-gather mode as appropriate for the primary or alternate control -//! structure. -//! -//! The channel must also be enabled using uDMAChannelEnable() after calling -//! this function. The transfer does not begin until the channel has been -//! configured and enabled. Note that the channel is automatically disabled -//! after the transfer is completed, meaning that uDMAChannelEnable() must be -//! called again after setting up the next transfer. -//! -//! \note Great care must be taken to not modify a channel control structure -//! that is in use or else the results are unpredictable, including the -//! possibility of undesired data transfers to or from memory or peripherals. -//! For BASIC and AUTO modes, it is safe to make changes when the channel is -//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For -//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the -//! primary or alternate control structure only when the other is being used. -//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a -//! channel control structure is inactive and safe to modify. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelTransferSet(unsigned long ulChannelStructIndex, - unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr, - unsigned long ulTransferSize) -{ - tDMAControlTable *pControlTable; - unsigned long ulControl; - unsigned long ulInc; - unsigned long ulBufferBytes; - - // - // Check the arguments. - // - ASSERT((ulChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); - ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER); - ASSERT((unsigned long)pvSrcAddr >= 0x20000000); - ASSERT((unsigned long)pvDstAddr >= 0x20000000); - ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024)); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ulChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); - - // - // Get the current control word value and mask off the mode and size - // fields. - // - ulControl = (pControlTable[ulChannelStructIndex].ulControl & - ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // Adjust the mode if the alt control structure is selected. - // - if(ulChannelStructIndex & UDMA_ALT_SELECT) - { - if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) - { - ulMode |= UDMA_MODE_ALT_SELECT; - } - } - - // - // Set the transfer size and mode in the control word (but don't write the - // control word yet as it could kick off a transfer). - // - ulControl |= ulMode | ((ulTransferSize - 1) << 4); - - // - // Get the address increment value for the source, from the control word. - // - ulInc = (ulControl & UDMA_CHCTL_SRCINC_M); - - // - // Compute the ending source address of the transfer. If the source - // increment is set to none, then the ending address is the same as the - // beginning. - // - if(ulInc != UDMA_SRC_INC_NONE) - { - ulInc = ulInc >> 26; - ulBufferBytes = ulTransferSize << ulInc; - pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulBufferBytes - 1); - } - - // - // Load the source ending address into the control block. - // - pControlTable[ulChannelStructIndex].pvSrcEndAddr = pvSrcAddr; - - // - // Get the address increment value for the destination, from the control - // word. - // - ulInc = ulControl & UDMA_CHCTL_DSTINC_M; - - // - // Compute the ending destination address of the transfer. If the - // destination increment is set to none, then the ending address is the - // same as the beginning. - // - if(ulInc != UDMA_DST_INC_NONE) - { - // - // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer must point to the end of - // the alternate structure for this channel instead of calculating - // the end of the buffer in the normal way. - // - if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) - { - pvDstAddr = - (void *)&pControlTable[ulChannelStructIndex | - UDMA_ALT_SELECT].ulSpare; - } - // - // Not a scatter-gather transfer, calculate end pointer normally. - // - else - { - ulInc = ulInc >> 30; - ulBufferBytes = ulTransferSize << ulInc; - pvDstAddr = (void *)((unsigned long)pvDstAddr + ulBufferBytes - 1); - } - } - - // - // Load the destination ending address into the control block. - // - pControlTable[ulChannelStructIndex].pvDstEndAddr = pvDstAddr; - - // - // Write the new control word value. - // - pControlTable[ulChannelStructIndex].ulControl = ulControl; -} - -//***************************************************************************** -// -//! Configures a uDMA channel for scatter-gather mode. -//! -//! \param ulChannelNum is the uDMA channel number. -//! \param ulTaskCount is the number of scatter-gather tasks to execute. -//! \param pvTaskList is a pointer to the beginning of the scatter-gather -//! task list. -//! \param ulIsPeriphSG is a flag to indicate it is a peripheral scatter-gather -//! transfer (else it is memory scatter-gather transfer) -//! -//! This function is used to configure a channel for scatter-gather mode. -//! The caller must have already set up a task list and must pass a pointer to -//! the start of the task list as the \e pvTaskList parameter. The -//! \e ulTaskCount parameter is the count of tasks in the task list, not the -//! size of the task list. The flag \e bIsPeriphSG should be used to indicate -//! if scatter-gather should be configured for peripheral or memory -//! operation. -//! -//! \sa uDMATaskStructEntry -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount, - void *pvTaskList, unsigned long ulIsPeriphSG) -{ - tDMAControlTable *pControlTable; - tDMAControlTable *pTaskTable; - - // - // Check the parameters - // - ASSERT((ulChannelNum & 0xffff) < 32); - ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); - ASSERT(pvTaskList != 0); - ASSERT(ulTaskCount <= 1024); - ASSERT(ulTaskCount != 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelNum parameter, extract just the channel number - // from this parameter. - // - ulChannelNum &= 0x1f; - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); - - // - // Get a handy pointer to the task list - // - pTaskTable = (tDMAControlTable *)pvTaskList; - - // - // Compute the ending address for the source pointer. This address is the - // last element of the last task in the task table - // - pControlTable[ulChannelNum].pvSrcEndAddr = - &pTaskTable[ulTaskCount - 1].ulSpare; - - // - // Compute the ending address for the destination pointer. This address - // is the end of the alternate structure for this channel. - // - pControlTable[ulChannelNum].pvDstEndAddr = - &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare; - - // - // Compute the control word. Most configurable items are fixed for - // scatter-gather. Item and increment sizes are all 32-bit and arb - // size must be 4. The count is the number of items in the task list - // times 4 (4 words per task). - // - pControlTable[ulChannelNum].ulControl = - (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | - UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | - UDMA_CHCTL_ARBSIZE_4 | - (((ulTaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | - (ulIsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : - UDMA_CHCTL_XFERMODE_MEM_SG)); -} - -//***************************************************************************** -// -//! Gets the current transfer size for a uDMA channel control structure. -//! -//! \param ulChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the uDMA transfer size for a channel. The -//! transfer size is the number of items to transfer, where the size of an item -//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, -//! then the number of remaining items is returned. If the transfer is -//! complete, then 0 is returned. -//! -//! \return Returns the number of items remaining to transfer. -// -//***************************************************************************** -unsigned long -uDMAChannelSizeGet(unsigned long ulChannelStructIndex) -{ - tDMAControlTable *pControlTable; - unsigned long ulControl; - - // - // Check the arguments. - // - ASSERT((ulChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ulChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); - - // - // Get the current control word value and mask off all but the size field - // and the mode field. - // - ulControl = (pControlTable[ulChannelStructIndex].ulControl & - (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // If the size field and mode field are 0 then the transfer is finished - // and there are no more items to transfer - // - if(ulControl == 0) - { - return(0); - } - - // - // Otherwise, if either the size field or more field is non-zero, then - // not all the items have been transferred. - // - else - { - // - // Shift the size field and add one, then return to user. - // - return((ulControl >> 4) + 1); - } -} - -//***************************************************************************** -// -//! Gets the transfer mode for a uDMA channel control structure. -//! -//! \param ulChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the transfer mode for the uDMA channel and -//! to query the status of a transfer on a channel. When the transfer is -//! complete the mode is \b UDMA_MODE_STOP. -//! -//! \return Returns the transfer mode of the specified channel and control -//! structure, which is one of the following values: \b UDMA_MODE_STOP, -//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. -// -//***************************************************************************** -unsigned long -uDMAChannelModeGet(unsigned long ulChannelStructIndex) -{ - tDMAControlTable *pControlTable; - unsigned long ulControl; - - // - // Check the arguments. - // - ASSERT((ulChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_O_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ulChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); - - // - // Get the current control word value and mask off all but the mode field. - // - ulControl = (pControlTable[ulChannelStructIndex].ulControl & - UDMA_CHCTL_XFERMODE_M); - - // - // Check if scatter/gather mode, and if so, mask off the alt bit. - // - if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || - ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) - { - ulControl &= ~UDMA_MODE_ALT_SELECT; - } - - // - // Return the mode to the caller. - // - return(ulControl); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the uDMA controller. -//! -//! \param ulIntChannel identifies which uDMA interrupt is to be registered. -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! This function registers and enables the handler to be called when the uDMA -//! controller generates an interrupt. The \e ulIntChannel parameter should be -//! one of the following: -//! -//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts -//! from the uDMA software channel (UDMA_CHANNEL_SW) -//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error -//! interrupts -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note The interrupt handler for the uDMA is for transfer completion when -//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The -//! interrupts for each peripheral channel are handled through the individual -//! peripheral interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(pfnHandler); - ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR)); - - // - // Register the interrupt handler. - // - IntRegister(ulIntChannel, pfnHandler); - - // - // Enable the memory management fault. - // - IntEnable(ulIntChannel); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the uDMA controller. -//! -//! \param ulIntChannel identifies which uDMA interrupt to unregister. -//! -//! This function disables and unregisters the handler to be called for the -//! specified uDMA interrupt. The \e ulIntChannel parameter should be one of -//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function -//! uDMAIntRegister(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntUnregister(unsigned long ulIntChannel) -{ - // - // Disable the interrupt. - // - IntDisable(ulIntChannel); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulIntChannel); -} - -//***************************************************************************** -// -//! Gets the uDMA controller channel interrupt status. -//! -//! This function is used to get the interrupt status of the uDMA controller. -//! The returned value is a 32-bit bit mask that indicates which channels are -//! requesting an interrupt. This function can be used from within an -//! interrupt handler to determine or confirm which uDMA channel has requested -//! an interrupt. -//! -//! \note This function is only available on devices that have the DMA Channel -//! Interrupt Status Register (DMACHIS). Please consult the data sheet for -//! your part. -//! -//! \return Returns a 32-bit mask which indicates requesting uDMA channels. -//! There is a bit for each channel and a 1 indicates that the channel -//! is requesting an interrupt. Multiple bits can be set. -// -//***************************************************************************** -unsigned long -uDMAIntStatus(void) -{ - - - // - // Return the value of the uDMA interrupt status register - // - return(HWREG(UDMA_BASE + UDMA_O_CHIS)); -} - -//***************************************************************************** -// -//! Clears uDMA interrupt status. -//! -//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel. -//! -//! This function clears bits in the uDMA interrupt status register according -//! to which bits are set in \e ulChanMask. There is one bit for each channel. -//! If a a bit is set in \e ulChanMask, then that corresponding channel's -//! interrupt status is cleared (if it was set). -//! -//! \note This function is only available on devices that have the DMA Channel -//! Interrupt Status Register (DMACHIS). Please consult the data sheet for -//! your part. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntClear(unsigned long ulChanMask) -{ - - // - // Clear the requested bits in the uDMA interrupt status register - // - HWREG(UDMA_BASE + UDMA_O_CHIS) = ulChanMask; -} - -//***************************************************************************** -// -//! Assigns a peripheral mapping for a uDMA channel. -//! -//! \param ulMapping is a macro specifying the peripheral assignment for -//! a channel. -//! -//! This function assigns a peripheral mapping to a uDMA channel. It is -//! used to select which peripheral is used for a uDMA channel. The parameter -//! \e ulMapping should be one of the macros named \b UDMA_CHn_tttt from the -//! header file \e udma.h. For example, to assign uDMA channel 8 to the -//! UARTA0 RX channel, the parameter should be the macro \b UDMA_CH8_UARTA0_RX. -//! -//! Please consult the data sheet for a table showing all the -//! possible peripheral assignments for the uDMA channels for a particular -//! device. -//! -//! \note This function is only available on devices that have the DMA Channel -//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for -//! your part. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAssign(unsigned long ulMapping) -{ - unsigned long ulMapReg; - unsigned long ulMapShift; - unsigned long ulChannelNum; - - // - // Check the parameters - // - ASSERT((ulMapping & 0xffffff00) < 0x00050000); - - - // - // Extract the channel number and map encoding value from the parameter. - // - ulChannelNum = ulMapping & 0x1f; - ulMapping = ulMapping >> 16; - - // - // Find the uDMA channel mapping register and shift value to use for this - // channel - // - ulMapReg = UDMA_BASE + UDMA_O_CHMAP0 + ((ulChannelNum / 8) * 4); - ulMapShift = (ulChannelNum % 8) * 4; - - // - // Set the channel map encoding for this channel - // - HWREG(ulMapReg) = (HWREG(ulMapReg) & ~(0xf << ulMapShift)) | - ulMapping << ulMapShift; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.h deleted file mode 100755 index ca95de0d525..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.h +++ /dev/null @@ -1,664 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// udma.h -// -// Prototypes and macros for the uDMA controller. -// -//***************************************************************************** - -#ifndef __UDMA_H__ -#define __UDMA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup uDMA_Micro_Direct_Memory_Access_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// A structure that defines an entry in the channel control table. These -// fields are used by the uDMA controller and normally it is not necessary for -// software to directly read or write fields in the table. -// -//***************************************************************************** -typedef struct -{ - // - // The ending source address of the data transfer. - // - volatile void *pvSrcEndAddr; - - // - // The ending destination address of the data transfer. - // - volatile void *pvDstEndAddr; - - // - // The channel control mode. - // - volatile unsigned long ulControl; - - // - // An unused location. - // - volatile unsigned long ulSpare; -} -tDMAControlTable; - -//***************************************************************************** -// -//! A helper macro for building scatter-gather task table entries. -//! -//! \param ulTransferCount is the count of items to transfer for this task. -//! \param ulItemSize is the bit size of the items to transfer for this task. -//! \param ulSrcIncrement is the bit size increment for source data. -//! \param pvSrcAddr is the starting address of the data to transfer. -//! \param ulDstIncrement is the bit size increment for destination data. -//! \param pvDstAddr is the starting address of the destination data. -//! \param ulArbSize is the arbitration size to use for the transfer task. -//! \param ulMode is the transfer mode for this task. -//! -//! This macro is intended to be used to help populate a table of uDMA tasks -//! for a scatter-gather transfer. This macro will calculate the values for -//! the fields of a task structure entry based on the input parameters. -//! -//! There are specific requirements for the values of each parameter. No -//! checking is done so it is up to the caller to ensure that correct values -//! are used for the parameters. -//! -//! The \e ulTransferCount parameter is the number of items that will be -//! transferred by this task. It must be in the range 1-1024. -//! -//! The \e ulItemSize parameter is the bit size of the transfer data. It must -//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. -//! -//! The \e ulSrcIncrement parameter is the increment size for the source data. -//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, -//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. -//! -//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source -//! data. -//! -//! The \e ulDstIncrement parameter is the increment size for the destination -//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, -//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. -//! -//! The \e pvDstAddr parameter is a void pointer to the beginning of the -//! location where the data will be transferred. -//! -//! The \e ulArbSize parameter is the arbitration size for the transfer, and -//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on -//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in -//! powers of 2, from 1 to 1024. -//! -//! The \e ulMode parameter is the mode to use for this transfer task. It -//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note -//! that normally all tasks will be one of the scatter-gather modes while the -//! last task is a task list will be AUTO or BASIC. -//! -//! This macro is intended to be used to initialize individual entries of -//! a structure of tDMAControlTable type, like this: -//! -//! \verbatim -//! tDMAControlTable MyTaskList[] = -//! { -//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, -//! UDMA_SRC_INC_8, MySourceBuf, -//! UDMA_DST_INC_8, MyDestBuf, -//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), -//! uDMATaskStructEntry(Task2Count, ... ), -//! } -//! \endverbatim -//! -//! \return Nothing; this is not a function. -// -//***************************************************************************** -#define uDMATaskStructEntry(ulTransferCount, \ - ulItemSize, \ - ulSrcIncrement, \ - pvSrcAddr, \ - ulDstIncrement, \ - pvDstAddr, \ - ulArbSize, \ - ulMode) \ - { \ - (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ - ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \ - ((ulSrcIncrement) >> 26)) - 1]))), \ - (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \ - ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \ - ((ulDstIncrement) >> 30)) - 1]))), \ - (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \ - (((ulTransferCount) - 1) << 4) | \ - ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \ - } - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Flags that can be passed to uDMAChannelAttributeEnable(), -// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). -// -//***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 -#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F - -//***************************************************************************** -// -// DMA control modes that can be passed to uDMAModeSet() and returned -// uDMAModeGet(). -// -//***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ - 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ - 0x00000006 -#define UDMA_MODE_ALT_SELECT 0x00000001 - -//***************************************************************************** -// -// Flags to be OR'd with the channel ID to indicate if the primary or alternate -// control structure should be used. -// -//***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 - -//***************************************************************************** -// -// uDMA interrupt sources, to be passed to uDMAIntRegister() and -// uDMAIntUnregister(). -// -//***************************************************************************** -#define UDMA_INT_SW INT_UDMA -#define UDMA_INT_ERR INT_UDMAERR - -//***************************************************************************** - -//***************************************************************************** -// -// Channel configuration values that can be passed to uDMAControlSet(). -// -//***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xc0000000 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_NEXT_USEBURST 0x00000008 - -//***************************************************************************** -// -// Values that can be passed to uDMAChannelAssign() to select peripheral -// mapping for each channel. The channels named RESERVED may be assigned -// to a peripheral in future parts. -// -//***************************************************************************** -// -// Channel 0 -// -#define UDMA_CH0_TIMERA0_A 0x00000000 -#define UDMA_CH0_SHAMD5_CIN 0x00010000 -#define UDMA_CH0_SW 0x00030000 - -// -// Channel 1 -// -#define UDMA_CH1_TIMERA0_B 0x00000001 -#define UDMA_CH1_SHAMD5_DIN 0x00010001 -#define UDMA_CH1_SW 0x00030001 - -// -// Channel 2 -// -#define UDMA_CH2_TIMERA1_A 0x00000002 -#define UDMA_CH2_SHAMD5_COUT 0x00010002 -#define UDMA_CH2_SW 0x00030002 - -// -// Channel 3 -// -#define UDMA_CH3_TIMERA1_B 0x00000003 -#define UDMA_CH3_DES_CIN 0x00010003 -#define UDMA_CH3_SW 0x00030003 - -// -// Channel 4 -// -#define UDMA_CH4_TIMERA2_A 0x00000004 -#define UDMA_CH4_DES_DIN 0x00010004 -#define UDMA_CH4_I2S_RX 0x00020004 -#define UDMA_CH4_SW 0x00030004 - -// -// Channel 5 -// -#define UDMA_CH5_TIMERA2_B 0x00000005 -#define UDMA_CH5_DES_DOUT 0x00010005 -#define UDMA_CH5_I2S_TX 0x00020005 -#define UDMA_CH5_SW 0x00030005 - -// -// Channel 6 -// -#define UDMA_CH6_TIMERA3_A 0x00000006 -#define UDMA_CH6_GSPI_RX 0x00010006 -#define UDMA_CH6_GPIOA2 0x00020006 -#define UDMA_CH6_SW 0x00030006 - -// -// Channel 7 -// -#define UDMA_CH7_TIMERA3_B 0x00000007 -#define UDMA_CH7_GSPI_TX 0x00010007 -#define UDMA_CH7_GPIOA3 0x00020007 -#define UDMA_CH7_SW 0x00030007 - - -// -// Channel 8 -// -#define UDMA_CH8_UARTA0_RX 0x00000008 -#define UDMA_CH8_TIMERA0_A 0x00010008 -#define UDMA_CH8_TIMERA2_A 0x00020008 -#define UDMA_CH8_SW 0x00030008 - - -// -// Channel 9 -// -#define UDMA_CH9_UARTA0_TX 0x00000009 -#define UDMA_CH9_TIMERA0_B 0x00010009 -#define UDMA_CH9_TIMERA2_B 0x00020009 -#define UDMA_CH9_SW 0x00030009 - - -// -// Channel 10 -// -#define UDMA_CH10_UARTA1_RX 0x0000000A -#define UDMA_CH10_TIMERA1_A 0x0001000A -#define UDMA_CH10_TIMERA3_A 0x0002000A -#define UDMA_CH10_SW 0x0003000A - -// -// Channel 11 -// -#define UDMA_CH11_UARTA1_TX 0x0000000B -#define UDMA_CH11_TIMERA1_B 0x0001000B -#define UDMA_CH11_TIMERA3_B 0x0002000B -#define UDMA_CH11_SW 0x0003000B - - -// -// Channel 12 -// -#define UDMA_CH12_LSPI_RX 0x0000000C -#define UDMA_CH12_SW 0x0003000C - - -// -// Channel 13 -// -#define UDMA_CH13_LSPI_TX 0x0000000D -#define UDMA_CH13_SW 0x0003000D - - -// -// Channel 14 -// -#define UDMA_CH14_ADC_CH0 0x0000000E -#define UDMA_CH14_SDHOST_RX 0x0002000E -#define UDMA_CH14_SW 0x0003000E - - -// -// Channel 15 -// -#define UDMA_CH15_ADC_CH1 0x0000000F -#define UDMA_CH15_SDHOST_TX 0x0002000F -#define UDMA_CH15_SW 0x0003000F - - -// -// Channel 16 -// -#define UDMA_CH16_ADC_CH2 0x00000010 -#define UDMA_CH16_TIMERA2_A 0x00010010 -#define UDMA_CH16_SW 0x00030010 - - -// -// Channel 17 -// -#define UDMA_CH17_ADC_CH3 0x00000011 -#define UDMA_CH17_TIMERA2_B 0x00010011 -#define UDMA_CH17_SW 0x00030011 - -// -// Channel 18 -// -#define UDMA_CH18_GPIOA0 0x00000012 -#define UDMA_CH18_AES_CIN 0x00010012 -#define UDMA_CH18_I2S_RX 0x00020012 -#define UDMA_CH18_SW 0x00030012 - - -// -// Channel 19 -// -#define UDMA_CH19_GPOIA1 0x00000013 -#define UDMA_CH19_AES_COUT 0x00010013 -#define UDMA_CH19_I2S_TX 0x00020013 -#define UDMA_CH19_SW 0x00030013 - - -// -// Channel 20 -// -#define UDMA_CH20_GPIOA2 0x00000014 -#define UDMA_CH20_AES_DIN 0x00010014 -#define UDMA_CH20_SW 0x00030014 - - -// -// Channel 21 -// -#define UDMA_CH21_GPIOA3 0x00000015 -#define UDMA_CH21_AES_DOUT 0x00010015 -#define UDMA_CH21_SW 0x00030015 - - -// -// Channel 22 -// -#define UDMA_CH22_CAMERA 0x00000016 -#define UDMA_CH22_GPIOA4 0x00010016 -#define UDMA_CH22_SW 0x00030016 - - -// -// Channel 23 -// -#define UDMA_CH23_SDHOST_RX 0x00000017 -#define UDMA_CH23_TIMERA3_A 0x00010017 -#define UDMA_CH23_TIMERA2_A 0x00020017 -#define UDMA_CH23_SW 0x00030017 - - -// -// Channel 24 -// -#define UDMA_CH24_SDHOST_TX 0x00000018 -#define UDMA_CH24_TIMERA3_B 0x00010018 -#define UDMA_CH24_TIMERA2_B 0x00020018 -#define UDMA_CH24_SW 0x00030018 - - -// -// Channel 25 -// -#define UDMA_CH25_SSPI_RX 0x00000019 -#define UDMA_CH25_I2CA0_RX 0x00010019 -#define UDMA_CH25_SW 0x00030019 - - -// -// Channel 26 -// -#define UDMA_CH26_SSPI_TX 0x0000001A -#define UDMA_CH26_I2CA0_TX 0x0001001A -#define UDMA_CH26_SW 0x0003001A - - -// -// Channel 27 -// -#define UDMA_CH27_GPIOA0 0x0001001B -#define UDMA_CH27_SW 0x0003001B - - -// -// Channel 28 -// -#define UDMA_CH28_GPIOA1 0x0001001C -#define UDMA_CH28_SW 0x0003001C - - -// -// Channel 29 -// -#define UDMA_CH29_GPIOA4 0x0000001D -#define UDMA_CH29_SW 0x0003001D - - -// -// Channel 30 -// -#define UDMA_CH30_GSPI_RX 0x0000001E -#define UDMA_CH30_SDHOST_RX 0x0001001E -#define UDMA_CH30_I2CA0_RX 0x0002001E -#define UDMA_CH30_SW 0x0003001E - - -// -// Channel 31 -// -#define UDMA_CH31_GSPI_TX 0x0000001F -#define UDMA_CH31_SDHOST_TX 0x0001001F -#define UDMA_CH31_I2CA0_RX 0x0002001F -#define UDMA_CH31_SW 0x0003001F - -//***************************************************************************** -// -// The following are defines for the Micro Direct Memory Access (uDMA) offsets. -// -//***************************************************************************** -#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End - // Pointer -#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address - // End Pointer -#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SRCENDP register. -// -//***************************************************************************** -#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer -#define UDMA_SRCENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_DSTENDP register. -// -//***************************************************************************** -#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer -#define UDMA_DSTENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHCTL register. -// -//***************************************************************************** -#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment -#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word -#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word -#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment -#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word -#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment -#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word -#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word -#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment -#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word -#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers -#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst -#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_CHCTL_XFERMODE_STOP \ - 0x00000000 // Stop -#define UDMA_CHCTL_XFERMODE_BASIC \ - 0x00000001 // Basic -#define UDMA_CHCTL_XFERMODE_AUTO \ - 0x00000002 // Auto-Request -#define UDMA_CHCTL_XFERMODE_PINGPONG \ - 0x00000003 // Ping-Pong -#define UDMA_CHCTL_XFERMODE_MEM_SG \ - 0x00000004 // Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_MEM_SGA \ - 0x00000005 // Alternate Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SG \ - 0x00000006 // Peripheral Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SGA \ - 0x00000007 // Alternate Peripheral - // Scatter-Gather -#define UDMA_CHCTL_XFERSIZE_S 4 - - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void uDMAEnable(void); -extern void uDMADisable(void); -extern unsigned long uDMAErrorStatusGet(void); -extern void uDMAErrorStatusClear(void); -extern void uDMAChannelEnable(unsigned long ulChannelNum); -extern void uDMAChannelDisable(unsigned long ulChannelNum); -extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum); -extern void uDMAControlBaseSet(void *pControlTable); -extern void *uDMAControlBaseGet(void); -extern void *uDMAControlAlternateBaseGet(void); -extern void uDMAChannelRequest(unsigned long ulChannelNum); -extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum, - unsigned long ulAttr); -extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum, - unsigned long ulAttr); -extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum); -extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex, - unsigned long ulControl); -extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, - unsigned long ulMode, void *pvSrcAddr, - void *pvDstAddr, - unsigned long ulTransferSize); -extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, - unsigned ulTaskCount, void *pvTaskList, - unsigned long ulIsPeriphSG); -extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex); -extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex); -extern void uDMAIntRegister(unsigned long ulIntChannel, - void (*pfnHandler)(void)); -extern void uDMAIntUnregister(unsigned long ulIntChannel); -extern unsigned long uDMAIntStatus(void); -extern void uDMAIntClear(unsigned long ulChanMask); -extern void uDMAChannelAssign(unsigned long ulMapping); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __UDMA_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.c deleted file mode 100755 index 18c93725348..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// utils.c -// -// Utility APIs -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup Utils_api -//! @{ -// -//***************************************************************************** -#include "utils.h" - - -//***************************************************************************** -// -//! Provides a small delay. -//! -//! \param ulCount is the number of delay loop iterations to perform. -//! -//! This function provides a means of generating a constant length delay. It -//! is written in assembly to keep the delay consistent across tool chains, -//! avoiding the need to tune the delay based on the tool chain in use. -//! -//! The loop takes 3 cycles/loop. -//! -//! \return None. -// -//***************************************************************************** - -#if defined(ewarm) || defined(DOXYGEN) -void -UtilsDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne.n UtilsDelay\n"); -} -#endif - -#if defined(gcc) -void __attribute__((naked)) -UtilsDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne UtilsDelay\n" - " bx lr"); -} -#endif - -#if defined (arm_cc) -// Use C code for now. TODO, change to assembly if precision is needed. -void UtilsDelay(unsigned long ulCount) -{ - volatile unsigned long delay = (ulCount >> 2); - while (delay --); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.h deleted file mode 100755 index df74f04b0f2..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// utils.h -// -// Prototypes and macros for utility APIs -// -//***************************************************************************** - -#ifndef __UTILS_H__ -#define __UTILS_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -// TODO, move this to tools -#ifdef TOOLCHAIN_GCC_ARM -#define gcc -#elif defined TOOLCHAIN_ARM -#define arm_cc -#elif defined TOOLCHAIN_IAR -#define ewarm -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UtilsDelay(unsigned long ulCount); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif //__UTILS_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/version.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/version.h deleted file mode 100755 index db0b6878ea2..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/version.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// version.h -// -// Contains Driverlib version details -// -//***************************************************************************** - -#ifndef __DRIVERLIB_VERSION_H__ -#define __DRIVERLIB_VERSION_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#define DRIVERLIB_MAJOR_VERSION_NUM 01 -#define DRIVERLIB_MINOR_VERSION_NUM 51 -#define DRIVERLIB_PATCH_VERSION_NUM 03 -#define DRIVERLIB_BUILD_VERSION_NUM 00 -#define DRIVERLIB_RELEASE_DAY 15 -#define DRIVERLIB_RELEASE_MONTH 01 -#define DRIVERLIB_RELEASE_YEAR 2018 - -///////////////////////////////////////////// -// !!! Please update the changes.log file !!! -///////////////////////////////////////////// - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_VERSION_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.c deleted file mode 100755 index c0358b1691f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// wdt.c -// -// Driver for the Watchdog Timer Module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup WDT_Watchdog_Timer_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_wdt.h" -#include "debug.h" -#include "interrupt.h" -#include "wdt.h" - -//***************************************************************************** -// -//! Determines if the watchdog timer is enabled. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This will check to see if the watchdog timer is enabled. -//! -//! \return Returns \b true if the watchdog timer is enabled, and \b false -//! if it is not. -// -//***************************************************************************** -tBoolean -WatchdogRunning(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // See if the watchdog timer module is enabled, and return. - // - return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); -} - -//***************************************************************************** -// -//! Enables the watchdog timer. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This will enable the watchdog timer counter and interrupt. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock() -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Enable the watchdog timer module. - // - HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; -} - -//***************************************************************************** -// -//! Enables the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Locks out write access to the watchdog timer configuration registers. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogLock(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK - // register causes the lock to go into effect. - // - HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; -} - -//***************************************************************************** -// -//! Disables the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Enables write access to the watchdog timer configuration registers. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogUnlock(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Unlock watchdog register writes. - // - HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; -} - -//***************************************************************************** -// -//! Gets the state of the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Returns the lock state of the watchdog timer registers. -//! -//! \return Returns \b true if the watchdog timer registers are locked, and -//! \b false if they are not locked. -// -//***************************************************************************** -tBoolean -WatchdogLockState(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Get the lock state. - // - return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); -} - -//***************************************************************************** -// -//! Sets the watchdog timer reload value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param ulLoadVal is the load value for the watchdog timer. -//! -//! This function sets the value to load into the watchdog timer when the count -//! reaches zero for the first time; if the watchdog timer is running when this -//! function is called, then the value will be immediately loaded into the -//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an -//! interrupt is immediately generated. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Set the load register. - // - HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; -} - -//***************************************************************************** -// -//! Gets the watchdog timer reload value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function gets the value that is loaded into the watchdog timer when -//! the count reaches zero for the first time. -//! -//! \sa WatchdogReloadSet() -//! -//! \return None. -// -//***************************************************************************** -unsigned long -WatchdogReloadGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Get the load register. - // - return(HWREG(ulBase + WDT_O_LOAD)); -} - -//***************************************************************************** -// -//! Gets the current watchdog timer value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function reads the current value of the watchdog timer. -//! -//! \return Returns the current value of the watchdog timer. -// -//***************************************************************************** -unsigned long -WatchdogValueGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Get the current watchdog timer register value. - // - return(HWREG(ulBase + WDT_O_VALUE)); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param pfnHandler is a pointer to the function to be called when the -//! watchdog timer interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; the watchdog -//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via -//! WatchdogIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note This function will only register the standard watchdog interrupt -//! handler. To register the NMI watchdog handler, use IntRegister() -//! to register the handler for the \b FAULT_NMI interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Register the interrupt handler and - // Enable the watchdog timer interrupt. - // - IntRegister(INT_WDT, pfnHandler); - IntEnable(INT_WDT); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function does the actual unregistering of the interrupt handler. This -//! function will clear the handler to be called when a watchdog timer -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note This function will only unregister the standard watchdog interrupt -//! handler. To unregister the NMI watchdog handler, use IntUnregister() -//! to unregister the handler for the \b FAULT_NMI interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Disable the interrupt - IntDisable(INT_WDT); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_WDT); -} - -//***************************************************************************** -// -//! Gets the current watchdog timer interrupt status. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This returns the interrupt status for the watchdog timer module. Either -//! the raw interrupt status or the status of interrupt that is allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, where a 1 indicates that the -//! watchdog interrupt is active, and a 0 indicates that it is not active. -// -//***************************************************************************** -unsigned long -WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + WDT_O_MIS)); - } - else - { - return(HWREG(ulBase + WDT_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! The watchdog timer interrupt source is cleared, so that it no longer -//! asserts. -//! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Clear the interrupt source. - // - HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; -} - -//***************************************************************************** -// -//! Enables stalling of the watchdog timer during debug events. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function allows the watchdog timer to stop counting when the processor -//! is stopped by the debugger. By doing so, the watchdog is prevented from -//! expiring (typically almost immediately from a human time perspective) and -//! resetting the system (if reset is enabled). The watchdog will instead -//! expired after the appropriate number of processor cycles have been executed -//! while debugging (or at the appropriate time after the processor has been -//! restarted). -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogStallEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Enable timer stalling. - // - HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; -} - -//***************************************************************************** -// -//! Disables stalling of the watchdog timer during debug events. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function disables the debug mode stall of the watchdog timer. By -//! doing so, the watchdog timer continues to count regardless of the processor -//! debug state. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogStallDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Disable timer stalling. - // - HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.h deleted file mode 100755 index 7a14d3fc0a0..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// wdt.h - Prototypes for the Watchdog Timer API -// -// - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallEnable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/asmdefs.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/asmdefs.h deleted file mode 100755 index de722a7ff27..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/asmdefs.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -// asmdefs.h - Macros to allow assembly code be portable among toolchains. -// -//***************************************************************************** - -#ifndef __ASMDEFS_H__ -#define __ASMDEFS_H__ - -//***************************************************************************** -// -// The defines required for code_red. -// -//***************************************************************************** -#ifdef codered - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // codered - -//***************************************************************************** -// -// The defines required for EW-ARM. -// -//***************************************************************************** -#ifdef ewarm - -// -// Section headers. -// -#define __LIBRARY__ module -#define __TEXT__ rseg CODE:CODE(2) -#define __DATA__ rseg DATA:DATA(2) -#define __BSS__ rseg DATA:DATA(2) -#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) - -// -// Assembler nmenonics. -// -#define __ALIGN__ alignrom 2 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ thumb -#define __WORD__ dcd -#define __INLINE_DATA__ data - -#endif // ewarm - -//***************************************************************************** -// -// The defines required for GCC. -// -//***************************************************************************** -#if defined(gcc) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // gcc - -//***************************************************************************** -// -// The defines required for RV-MDK. -// -//***************************************************************************** -#ifdef rvmdk - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - thumb - require8 - preserve8 - -// -// Section headers. -// -#define __LIBRARY__ ; -#define __TEXT__ area ||.text||, code, readonly, align=2 -#define __DATA__ area ||.data||, data, align=2 -#define __BSS__ area ||.bss||, noinit, align=2 -#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 - -// -// Assembler nmenonics. -// -#define __ALIGN__ align 4 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ -#define __WORD__ dcd -#define __INLINE_DATA__ - -#endif // rvmdk - -//***************************************************************************** -// -// The defines required for Sourcery G++. -// -//***************************************************************************** -#if defined(sourcerygxx) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // sourcerygxx - -#endif // __ASMDEF_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_adc.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_adc.h deleted file mode 100755 index d518bc3222b..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_adc.h +++ /dev/null @@ -1,886 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following are defines for the ADC register offsets. -// -//***************************************************************************** -#define ADC_O_ADC_CTRL 0x00000000 // ADC control register. -#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting -#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting -#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting -#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting -#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting -#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting -#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting -#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting -#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable - // register -#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable - // register -#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable - // register -#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable - // register -#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable - // register -#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable - // register -#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable - // register -#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable - // register -#define ADC_O_adc_ch0_irq_status \ - 0x00000044 // Channel 0 interrupt status - // register - -#define ADC_O_adc_ch1_irq_status \ - 0x00000048 // Channel 1 interrupt status - // register - -#define ADC_O_adc_ch2_irq_status \ - 0x0000004C - -#define ADC_O_adc_ch3_irq_status \ - 0x00000050 // Channel 3 interrupt status - // register - -#define ADC_O_adc_ch4_irq_status \ - 0x00000054 // Channel 4 interrupt status - // register - -#define ADC_O_adc_ch5_irq_status \ - 0x00000058 - -#define ADC_O_adc_ch6_irq_status \ - 0x0000005C // Channel 6 interrupt status - // register - -#define ADC_O_adc_ch7_irq_status \ - 0x00000060 // Channel 7 interrupt status - // register - -#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register -#define ADC_O_adc_timer_configuration \ - 0x00000068 // ADC timer configuration register - -#define ADC_O_adc_timer_current_count \ - 0x00000070 // ADC timer current count register - -#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register -#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register -#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register -#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register -#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register -#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register -#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register -#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register -#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register -#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status - // register -#define ADC_O_adc_ch2_fifo_lvl 0x0000009C -#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status - // register -#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status - // register -#define ADC_O_adc_ch5_fifo_lvl 0x000000A8 -#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status - // register -#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status - // register - -#define ADC_O_ADC_CH_ENABLE 0x000000B8 - -//****************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ADC_CTRL register. -// -//****************************************************************************** -#define ADC_ADC_CTRL_adc_cap_scale \ - 0x00000020 // ADC CAP SCALE. - -#define ADC_ADC_CTRL_adc_buf_bypass \ - 0x00000010 // ADC ANA CIO buffer bypass. - // Signal is modelled in ANA TOP. - // When '1': ADC buffer is bypassed. - -#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1: - // ADC buffer is enabled. -#define ADC_ADC_CTRL_adc_core_en \ - 0x00000004 // ANA ADC core en. This signal act - // as glbal enable to ADC CIO. When - // 1: ADC core is enabled. - -#define ADC_ADC_CTRL_adc_soft_reset \ - 0x00000002 // ADC soft reset. When '1' : reset - // ADC internal logic. - -#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC - // module is enabled -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch0_gain register. -// -//****************************************************************************** -#define ADC_adc_ch0_gain_adc_channel0_gain_M \ - 0x00000003 // gain setting for ADC channel 0. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch0_gain_adc_channel0_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch1_gain register. -// -//****************************************************************************** -#define ADC_adc_ch1_gain_adc_channel1_gain_M \ - 0x00000003 // gain setting for ADC channel 1. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch1_gain_adc_channel1_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch2_gain register. -// -//****************************************************************************** -#define ADC_adc_ch2_gain_adc_channel2_gain_M \ - 0x00000003 // gain setting for ADC channel 2. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch2_gain_adc_channel2_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch3_gain register. -// -//****************************************************************************** -#define ADC_adc_ch3_gain_adc_channel3_gain_M \ - 0x00000003 // gain setting for ADC channel 3. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch3_gain_adc_channel3_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch4_gain register. -// -//****************************************************************************** -#define ADC_adc_ch4_gain_adc_channel4_gain_M \ - 0x00000003 // gain setting for ADC channel 4 - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch4_gain_adc_channel4_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch5_gain register. -// -//****************************************************************************** -#define ADC_adc_ch5_gain_adc_channel5_gain_M \ - 0x00000003 // gain setting for ADC channel 5. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch5_gain_adc_channel5_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch6_gain register. -// -//****************************************************************************** -#define ADC_adc_ch6_gain_adc_channel6_gain_M \ - 0x00000003 // gain setting for ADC channel 6 - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch6_gain_adc_channel6_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch7_gain register. -// -//****************************************************************************** -#define ADC_adc_ch7_gain_adc_channel7_gain_M \ - 0x00000003 // gain setting for ADC channel 7. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch7_gain_adc_channel7_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch0_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch1_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch2_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch3_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch4_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch5_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch6_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch7_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch0_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch1_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch2_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch3_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch4_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch5_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch6_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch7_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_dma_mode_en register. -// -//****************************************************************************** -#define ADC_adc_dma_mode_en_DMA_MODEenable_M \ - 0x000000FF // this register enable DMA mode. - // when '1' respective ADC channel - // is enabled for DMA. When '0' only - // interrupt mode is enabled. Bit 0: - // channel 0 DMA mode enable. Bit 1: - // channel 1 DMA mode enable. Bit 2: - // channel 2 DMA mode enable. Bit 3: - // channel 3 DMA mode enable. bit 4: - // channel 4 DMA mode enable. bit 5: - // channel 5 DMA mode enable. bit 6: - // channel 6 DMA mode enable. bit 7: - // channel 7 DMA mode enable. - -#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_timer_configuration register. -// -//****************************************************************************** -#define ADC_adc_timer_configuration_timeren \ - 0x02000000 // when '1' timer is enabled. - -#define ADC_adc_timer_configuration_timerreset \ - 0x01000000 // when '1' reset timer. - -#define ADC_adc_timer_configuration_timercount_M \ - 0x00FFFFFF // Timer count configuration. 17 - // bit counter is supported. Other - // MSB's are redundent. - -#define ADC_adc_timer_configuration_timercount_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_timer_current_count register. -// -//****************************************************************************** -#define ADC_adc_timer_current_count_timercurrentcount_M \ - 0x0001FFFF // Timer count configuration - -#define ADC_adc_timer_current_count_timercurrentcount_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel0FIFODATA register. -// -//****************************************************************************** -#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel1FIFODATA register. -// -//****************************************************************************** -#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel2FIFODATA register. -// -//****************************************************************************** -#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel3FIFODATA register. -// -//****************************************************************************** -#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel4FIFODATA register. -// -//****************************************************************************** -#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel5FIFODATA register. -// -//****************************************************************************** -#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel6FIFODATA register. -// -//****************************************************************************** -#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel7FIFODATA register. -// -//****************************************************************************** -#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch0_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch1_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch2_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch3_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch4_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch5_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch6_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch7_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0 - - - -#endif // __HW_ADC_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_aes.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_aes.h deleted file mode 100755 index 574f7576f83..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_aes.h +++ /dev/null @@ -1,800 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_AES_H__ -#define __HW_AES_H__ - -//***************************************************************************** -// -// The following are defines for the AES_P register offsets. -// -//***************************************************************************** -#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third - // key -#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit - // key) / CBC-MAC third key (MSW) -#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC - // third key (LSW) -#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit - // key) / CBC-MAC third key -#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key / - // Hash Key input -#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit - // key) + CCM/CBC-MAC second key - // (MSW) / Hash Key input (MSW) -#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key - // (LSW) / Hash Key input (LSW) -#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key / - // Hash Key input -#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key) -#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key) -#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key) -#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key) -#define AES_O_KEY1_2 0x00000030 // Key -#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key) -#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key) -#define AES_O_KEY1_1 0x0000003C // Key -#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input - // (LSW) -#define AES_O_IV_IN_1 0x00000044 // Initialization vector input -#define AES_O_IV_IN_2 0x00000048 // Initialization vector input -#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input - // (MSW) -#define AES_O_CTRL 0x00000050 // register determines the mode of - // operation of the AES Engine -#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers - // (LSW and MSW) store the - // cryptographic data length in - // bytes for all modes. Once - // processing with this context is - // started@@ this length decrements - // to zero. Data lengths up to (2^61 - // – 1) bytes are allowed. For GCM@@ - // any value up to 2^36 - 32 bytes - // can be used. This is because a - // 32-bit counter mode is used; the - // maximum number of 128-bit blocks - // is 2^32 – 2@@ resulting in a - // maximum number of bytes of 2^36 - - // 32. A write to this register - // triggers the engine to start - // using this context. This is valid - // for all modes except GCM and CCM. - // Note that for the combined - // modes@@ this length does not - // include the authentication only - // data; the authentication length - // is specified in the - // AES_AUTH_LENGTH register below. - // All modes must have a length > 0. - // For the combined modes@@ it is - // allowed to have one of the - // lengths equal to zero. For the - // basic encryption modes - // (ECB/CBC/CTR/ICM/CFB128) it is - // allowed to program zero to the - // length field; in that case the - // length is assumed infinite. All - // data must be byte (8-bit) - // aligned; bit aligned data streams - // are not supported by the AES - // Engine. For a Host read - // operation@@ these registers - // return all-zeroes. -#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers - // (LSW and MSW) store the - // cryptographic data length in - // bytes for all modes. Once - // processing with this context is - // started@@ this length decrements - // to zero. Data lengths up to (2^61 - // – 1) bytes are allowed. For GCM@@ - // any value up to 2^36 - 32 bytes - // can be used. This is because a - // 32-bit counter mode is used; the - // maximum number of 128-bit blocks - // is 2^32 – 2@@ resulting in a - // maximum number of bytes of 2^36 - - // 32. A write to this register - // triggers the engine to start - // using this context. This is valid - // for all modes except GCM and CCM. - // Note that for the combined - // modes@@ this length does not - // include the authentication only - // data; the authentication length - // is specified in the - // AES_AUTH_LENGTH register below. - // All modes must have a length > 0. - // For the combined modes@@ it is - // allowed to have one of the - // lengths equal to zero. For the - // basic encryption modes - // (ECB/CBC/CTR/ICM/CFB128) it is - // allowed to program zero to the - // length field; in that case the - // length is assumed infinite. All - // data must be byte (8-bit) - // aligned; bit aligned data streams - // are not supported by the AES - // Engine. For a Host read - // operation@@ these registers - // return all-zeroes. -#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The - // authentication length register - // store the authentication data - // length in bytes for combined - // modes only (GCM or CCM) Supported - // AAD-lengths for CCM are from 0 to - // (2^16 - 2^8) bytes. For GCM any - // value up to (2^32 - 1) bytes can - // be used. Once processing with - // this context is started@@ this - // length decrements to zero. A - // write to this register triggers - // the engine to start using this - // context for GCM and CCM. For XTS - // this register is optionally used - // to load ‘j’. Loading of ‘j’ is - // only required if ‘j’ != 0. ‘j’ is - // a 28-bit value and must be - // written to bits [31-4] of this - // register. ‘j’ represents the - // sequential number of the 128-bit - // block inside the data unit. For - // the first block in a unit@@ this - // value is zero. It is not required - // to provide a ‘j’ for each new - // data block within a unit. Note - // that it is possible to start with - // a ‘j’ unequal to zero; refer to - // Table 4 for more details. For a - // Host read operation@@ these - // registers return all-zeroes. -#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write - // plaintext/ciphertext (MSW) -#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write - // plaintext/ciphertext -#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write - // plaintext/ciphertext -#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write - // plaintext/ciphertext (LSW) -#define AES_O_TAG_OUT_0 0x00000070 -#define AES_O_TAG_OUT_1 0x00000074 -#define AES_O_TAG_OUT_2 0x00000078 -#define AES_O_TAG_OUT_3 0x0000007C -#define AES_O_REVISION 0x00000080 // Register AES_REVISION -#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This - // register configures the DMA - // signals and controls the IDLE and - // reset logic -#define AES_O_SYSSTATUS 0x00000088 -#define AES_O_IRQSTATUS 0x0000008C // This register indicates the - // interrupt status. If one of the - // interrupt bits is set the - // interrupt output will be asserted -#define AES_O_IRQENABLE 0x00000090 // This register contains an enable - // bit for each unique interrupt - // generated by the module. It - // matches the layout of - // AES_IRQSTATUS register. An - // interrupt is enabled when the bit - // in this register is set to ‘1’. - // An interrupt that is enabled is - // propagated to the SINTREQUEST_x - // output. All interrupts need to be - // enabled explicitly by writing - // this register. - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_6 register. -// -//****************************************************************************** -#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_6_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_7 register. -// -//****************************************************************************** -#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_7_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_4 register. -// -//****************************************************************************** -#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_4_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_5 register. -// -//****************************************************************************** -#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_5_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_2 register. -// -//****************************************************************************** -#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_2_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_3 register. -// -//****************************************************************************** -#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_3_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_0 register. -// -//****************************************************************************** -#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_0_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_1 register. -// -//****************************************************************************** -#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_1_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_6 register. -// -//****************************************************************************** -#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_6_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_7 register. -// -//****************************************************************************** -#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_7_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_4 register. -// -//****************************************************************************** -#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_4_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_5 register. -// -//****************************************************************************** -#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_5_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_2 register. -// -//****************************************************************************** -#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_2_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_3 register. -// -//****************************************************************************** -#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_3_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_0 register. -// -//****************************************************************************** -#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_0_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_1 register. -// -//****************************************************************************** -#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_1_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_0 register. -// -//****************************************************************************** -#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data -#define AES_IV_IN_0_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_1 register. -// -//****************************************************************************** -#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data -#define AES_IV_IN_1_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_2 register. -// -//****************************************************************************** -#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data -#define AES_IV_IN_2_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_3 register. -// -//****************************************************************************** -#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data -#define AES_IV_IN_3_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_CTRL register. -// -//****************************************************************************** -#define AES_CTRL_CONTEXT_READY \ - 0x80000000 // If ‘1’@@ this read-only status - // bit indicates that the context - // data registers can be overwritten - // and the host is permitted to - // write the next context. - -#define AES_CTRL_SVCTXTRDY \ - 0x40000000 // If ‘1’@@ this read-only status - // bit indicates that an AES - // authentication TAG and/or IV - // block(s) is/are available for the - // host to retrieve. This bit is - // only asserted if the - // ‘save_context’ bit is set to ‘1’. - // The bit is mutual exclusive with - // the ‘context_ready’ bit. - -#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate - // that an authentication TAG or - // result IV needs to be stored as a - // result context. If this bit is - // set@@ context output DMA and/or - // interrupt will be asserted if the - // operation is finished and related - // signals are enabled. -#define AES_CTRL_CCM_M 0x01C00000 // Defines “M�? that indicated the - // length of the authentication - // field for CCM operations; the - // authentication field length - // equals two times (the value of - // CCM-M plus one). Note that the - // AES Engine always returns a - // 128-bit authentication field@@ of - // which the M least significant - // bytes are valid. All values are - // supported. -#define AES_CTRL_CCM_S 22 -#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L�? that indicated the - // width of the length field for CCM - // operations; the length field in - // bytes equals the value of CMM-L - // plus one. Supported values for L - // are (programmed value): 2 (1)@@ 4 - // (3) and 8 (7). -#define AES_CTRL_CCM_L_S 19 -#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a - // combined mode@@ using AES for - // both authentication and - // encryption. No additional mode - // selection is required. 0 Other - // mode selected 1 ccm mode selected -#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is - // a combined mode@@ using the - // Galois field multiplier GF(2^128) - // for authentication and AES-CTR - // mode for encryption@@ the bits - // specify the GCM mode. 0x0 No - // operation 0x1 GHASH with H loaded - // and Y0-encrypted forced to zero - // 0x2 GHASH with H loaded and - // Y0-encrypted calculated - // internally 0x3 Autonomous GHASH - // (both H and Y0-encrypted - // calculated internally) -#define AES_CTRL_GCM_S 16 -#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the - // Direction bit must be set to ‘1’ - // for this mode. 0 Other mode - // selected 1 cbcmac mode selected -#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the - // AES key size must be set to - // 128-bit for this mode. 0 Other - // mode selected 1 f9 selected -#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the - // AES key size must be set to - // 128-bit for this mode. 0 Other - // mode selected 1 f8 selected -#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected; - // the bits specify the XTS mode.01 - // = Previous/intermediate tweak - // value and ‘j’ loaded (value is - // loaded via IV@@ j is loaded via - // the AAD length register) 0x0 No - // operation 0x1 - // Previous/intermediate tweak value - // and ‘j’ loaded (value is loaded - // via IV@@ j is loaded via the AAD - // length register) 0x2 Key2@@ i and - // j loaded (i is loaded via IV@@ j - // is loaded via the AAD length - // register) 0x3 Key2 and i loaded@@ - // j=0 (i is loaded via IV) -#define AES_CTRL_XTS_S 11 -#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback - // mode (CFB128) is selected. 0 - // other mode selected 1 cfb - // selected -#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM) - // is selected@@ this is a counter - // mode with a 16-bit wide counter. - // 0 Other mode selected. 1 ICM mode - // selected -#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for - // AES-CTR mode 0x0 Counter is 32 - // bits 0x1 Counter is 64 bits 0x2 - // Counter is 128 bits 0x3 Counter - // is 192 bits -#define AES_CTRL_CTR_WIDTH_S 7 -#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for - // GCM and CCM@@ when - // encryption/decryption is - // required. 0 Other mode selected 1 - // Counter mode -#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc - // mode -#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is - // 128 bits. 0x2 Key is 192 bits 0x3 - // Key is 256 -#define AES_CTRL_KEY_SIZE_S 3 -#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt - // operation is performed. If set to - // ‘0’ a decrypt operation is - // performed. Read 0 decryption is - // selected Read 1 Encryption is - // selected -#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status - // bit indicates that the 16-byte - // input buffer is empty@@ and the - // host is permitted to write the - // next block of data. -#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status - // bit indicates that an AES output - // block is available for the host - // to retrieve. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// AES_O_C_LENGTH_0 register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// AES_O_C_LENGTH_1 register. -// -//****************************************************************************** -#define AES_C_LENGTH_1_LENGTH_M \ - 0x1FFFFFFF // Data length (MSW) length - // registers (LSW and MSW) store the - // cryptographic data length in - // bytes for all modes. Once - // processing with this context is - // started@@ this length decrements - // to zero. Data lengths up to (2^61 - // – 1) bytes are allowed. For GCM@@ - // any value up to 2^36 - 32 bytes - // can be used. This is because a - // 32-bit counter mode is used; the - // maximum number of 128-bit blocks - // is 2^32 – 2@@ resulting in a - // maximum number of bytes of 2^36 - - // 32. A write to this register - // triggers the engine to start - // using this context. This is valid - // for all modes except GCM and CCM. - // Note that for the combined - // modes@@ this length does not - // include the authentication only - // data; the authentication length - // is specified in the - // AES_AUTH_LENGTH register below. - // All modes must have a length > 0. - // For the combined modes@@ it is - // allowed to have one of the - // lengths equal to zero. For the - // basic encryption modes - // (ECB/CBC/CTR/ICM/CFB128) it is - // allowed to program zero to the - // length field; in that case the - // length is assumed infinite. All - // data must be byte (8-bit) - // aligned; bit aligned data streams - // are not supported by the AES - // Engine. For a Host read - // operation@@ these registers - // return all-zeroes. - -#define AES_C_LENGTH_1_LENGTH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// AES_O_AUTH_LENGTH register. -// -//****************************************************************************** -#define AES_AUTH_LENGTH_AUTH_M \ - 0xFFFFFFFF // data - -#define AES_AUTH_LENGTH_AUTH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_0 register. -// -//****************************************************************************** -#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt -#define AES_DATA_IN_0_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_1 register. -// -//****************************************************************************** -#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt -#define AES_DATA_IN_1_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_2 register. -// -//****************************************************************************** -#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt -#define AES_DATA_IN_2_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_3 register. -// -//****************************************************************************** -#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt -#define AES_DATA_IN_3_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register. -// -//****************************************************************************** -#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW) -#define AES_TAG_OUT_0_HASH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register. -// -//****************************************************************************** -#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW) -#define AES_TAG_OUT_1_HASH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register. -// -//****************************************************************************** -#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW) -#define AES_TAG_OUT_2_HASH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register. -// -//****************************************************************************** -#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW) -#define AES_TAG_OUT_3_HASH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_REVISION register. -// -//****************************************************************************** -#define AES_REVISION_SCHEME_M 0xC0000000 -#define AES_REVISION_SCHEME_S 30 -#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define AES_REVISION_FUNC_S 16 -#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by - // IP design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define AES_REVISION_R_RTL_S 11 -#define AES_REVISION_X_MAJOR_M \ - 0x00000700 // Major Revision (X)@@ maintained - // by IP specification owner. X - // changes ONLY when: (1) There is a - // major feature addition. An - // example would be adding Master - // Mode to Utopia Level2. The Func - // field (or Class/Type in old PID - // format) will remain the same. X - // does NOT change due to: (1) Bug - // fixes (2) Change in feature - // parameters. - -#define AES_REVISION_X_MAJOR_S 8 -#define AES_REVISION_CUSTOM_M 0x000000C0 -#define AES_REVISION_CUSTOM_S 6 -#define AES_REVISION_Y_MINOR_M \ - 0x0000003F // Minor Revision (Y)@@ maintained - // by IP specification owner. Y - // changes ONLY when: (1) Features - // are scaled (up or down). - // Flexibility exists in that this - // feature scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R@@ S@@ X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless@@ the spec tracks - // the IP bugs. An RTL release (say - // for silicon PG1.1) that occurs - // due to bug fix should document - // the corresponding spec number - // (X.Y.S) in its release notes. - -#define AES_REVISION_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_SYSCONFIG register. -// -//****************************************************************************** -#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \ - 0x00000200 // If set to '1' the two context - // out requests - // (dma_req_context_out_en@@ Bit [8] - // above@@ and context_out interrupt - // enable@@ Bit [3] of AES_IRQENABLE - // register) are mapped on the - // corresponding data output request - // bit. In this case@@ the original - // ‘context out’ bit values are - // ignored. - -#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ - 0x00000100 // If set to ‘1’@@ the DMA context - // output request is enabled (for - // context data out@@ e.g. TAG for - // authentication modes). 0 Dma - // disabled 1 Dma enabled - -#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ - 0x00000080 // If set to ‘1’@@ the DMA context - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ - 0x00000040 // If set to ‘1’@@ the DMA output - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ - 0x00000020 // If set to ‘1’@@ the DMA input - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_SYSSTATUS register. -// -//****************************************************************************** -#define AES_SYSSTATUS_RESETDONE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IRQSTATUS register. -// -//****************************************************************************** -#define AES_IRQSTATUS_CONTEXT_OUT \ - 0x00000008 // This bit indicates - // authentication tag (and IV) - // interrupt(s) is/are active and - // triggers the interrupt output. - -#define AES_IRQSTATUS_DATA_OUT \ - 0x00000004 // This bit indicates data output - // interrupt is active and triggers - // the interrupt output. - -#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input - // interrupt is active and triggers - // the interrupt output. -#define AES_IRQSTATUS_CONTEX_IN \ - 0x00000001 // This bit indicates context - // interrupt is active and triggers - // the interrupt output. - -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IRQENABLE register. -// -//****************************************************************************** -#define AES_IRQENABLE_CONTEXT_OUT \ - 0x00000008 // This bit indicates - // authentication tag (and IV) - // interrupt(s) is/are active and - // triggers the interrupt output. - -#define AES_IRQENABLE_DATA_OUT \ - 0x00000004 // This bit indicates data output - // interrupt is active and triggers - // the interrupt output. - -#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input - // interrupt is active and triggers - // the interrupt output. -#define AES_IRQENABLE_CONTEX_IN \ - 0x00000001 // This bit indicates context - // interrupt is active and triggers - // the interrupt output. - - - - -#endif // __HW_AES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_config.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_config.h deleted file mode 100755 index e5f26928ab5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_config.h +++ /dev/null @@ -1,745 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef __HW_APPS_CONFIG_H__ -#define __HW_APPS_CONFIG_H__ - -//***************************************************************************** -// -// The following are defines for the APPS_CONFIG register offsets. -// -//***************************************************************************** -#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \ - 0x00000000 // Patch trap address Register - // array - -#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \ - 0x00000078 - -#define APPS_CONFIG_O_FAULT_STATUS_REG \ - 0x0000007C - -#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \ - 0x00000080 - -#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \ - 0x00000084 - -#define APPS_CONFIG_O_DMA_DONE_INT_MASK \ - 0x0000008C - -#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \ - 0x00000090 - -#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \ - 0x00000094 - -#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \ - 0x00000098 - -#define APPS_CONFIG_O_DMA_DONE_INT_ACK \ - 0x0000009C - -#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \ - 0x000000A0 - -#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \ - 0x000000A4 - -#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \ - 0x000000A8 - -#define APPS_CONFIG_O_RESERVD_REG_0 \ - 0x000000AC - -#define APPS_CONFIG_O_GPT_TRIG_SEL \ - 0x000000B0 - -#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \ - 0x000000B4 - -#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \ - 0x000000B8 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \ - 0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus - // fault is generated for the - // address - // PATCH_TRAP_ADDR_REG[n][31:0] from - // Idcode bus. The exception routine - // should take care to jump to the - // location where the patch - // correspond to this address is - // kept. - -#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_PATCH_TRAP_EN_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \ - 0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus - // fault is generated for the - // address PATCH_TRAP_ADD[n][31:0] - // from Idcode bus. The exception - // routine should take care to jump - // to the location where the patch - // correspond to this address is - // kept. - -#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_FAULT_STATUS_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \ - 0x0000003E // This field shows because of - // which patch trap address the - // bus_fault is generated. If the - // PATCH_ERR bit is set, then it - // means the bus fault is generated - // because of - // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX] - -#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1 -#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \ - 0x00000001 // This bit is set when there is a - // bus fault because of patched - // address access to the Apps boot - // rom. Write 0 to clear this - // register. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \ - 0x00000001 // This bit is set when there is a - // an error in memss write access. - // And the address causing this - // error is captured in - // MEMSS_ERR_ADDR_REG. To capture - // the next error address one have - // to clear this bit. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_MASK register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \ - 0x0000F000 // 1= disable corresponding - // interrupt;0 = interrupt enabled - // bit 14: ADC channel 7 interrupt - // enable/disable bit 13: ADC - // channel 5 interrupt - // enable/disable bit 12: ADC - // channel 3 interrupt - // enable/disable bit 11: ADC - // channel 1 interrupt - // enable/disable - -#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12 -#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \ - 0x00000800 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \ - 0x00000400 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \ - 0x00000200 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \ - 0x00000100 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \ - 0x00000080 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \ - 0x00000040 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \ - 0x00000020 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \ - 0x00000010 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \ - 0x00000008 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \ - 0x00000004 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \ - 0x00000002 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \ - 0x00000001 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \ - 0x0000F000 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect bit 14: ADC channel 7 DMA - // Done IRQ bit 13: ADC channel 5 - // DMA Done IRQ bit 12: ADC channel - // 3 DMA Done IRQ bit 11: ADC - // channel 1 DMA Done IRQ - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12 -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \ - 0x00000800 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \ - 0x00000400 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \ - 0x00000200 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \ - 0x00000100 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \ - 0x00000080 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \ - 0x00000040 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \ - 0x00000020 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \ - 0x00000010 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \ - 0x00000008 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \ - 0x00000004 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \ - 0x00000002 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \ - 0x00000001 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \ - 0x0000F000 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect bit 14: ADC channel 7 DMA - // Done IRQ mask bit 13: ADC channel - // 5 DMA Done IRQ mask bit 12: ADC - // channel 3 DMA Done IRQ mask bit - // 11: ADC channel 1 DMA Done IRQ - // mask - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12 -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000800 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000400 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \ - 0x00000200 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \ - 0x00000100 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000080 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000040 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000020 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000010 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000008 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000004 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000002 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000001 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \ - 0xFFFFFFFF // write 1 or 0 to clear all - // DMA_DONE interrupt; - -#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_ACK register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \ - 0x0000F000 // write 1 to clear corresponding - // interrupt; 0 = no effect; bit 14: - // ADC channel 7 DMA Done IRQ bit - // 13: ADC channel 5 DMA Done IRQ - // bit 12: ADC channel 3 DMA Done - // IRQ bit 11: ADC channel 1 DMA - // Done IRQ - -#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12 -#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \ - 0x00000800 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \ - 0x00000400 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \ - 0x00000200 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \ - 0x00000100 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \ - 0x00000080 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \ - 0x00000040 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \ - 0x00000020 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \ - 0x00000010 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \ - 0x00000008 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \ - 0x00000004 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \ - 0x00000002 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \ - 0x00000001 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \ - 0x0000F000 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask bit 14: ADC - // channel 7 DMA Done IRQ bit 13: - // ADC channel 5 DMA Done IRQ bit - // 12: ADC channel 3 DMA Done IRQ - // bit 11: ADC channel 1 DMA Done - // IRQ - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12 -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000800 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000400 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \ - 0x00000200 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \ - 0x00000100 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000080 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000040 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000020 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000010 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000008 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000004 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000002 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000001 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \ - 0x0000F000 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive bit 14: ADC channel 7 - // DMA Done IRQ bit 13: ADC channel - // 5 DMA Done IRQ bit 12: ADC - // channel 3 DMA Done IRQ bit 11: - // ADC channel 1 DMA Done IRQ - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12 -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \ - 0x00000800 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \ - 0x00000400 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \ - 0x00000200 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \ - 0x00000100 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \ - 0x00000080 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \ - 0x00000040 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \ - 0x00000020 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \ - 0x00000010 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \ - 0x00000008 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \ - 0x00000004 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \ - 0x00000002 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \ - 0x00000001 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \ - 0x00000001 // Write 1 to clear the LSB of - // FAULT_STATUS_REG - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_RESERVD_REG_0 register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_GPT_TRIG_SEL register. -// -//****************************************************************************** -#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \ - 0x000000FF // This bit is implemented for GPT - // trigger mode select. GPT IP - // support 2 modes: RTC mode and - // external trigger. When this bit - // is set to logic '1': enable - // external trigger mode for APPS - // GPT CP0 and CP1 pin. bit 0: when - // set '1' enable external GPT - // trigger 0 on GPIO0 CP0 pin else - // RTC mode is selected. bit 1: when - // set '1' enable external GPT - // trigger 1 on GPIO0 CP1 pin else - // RTC mode is selected. bit 2: when - // set '1' enable external GPT - // trigger 2 on GPIO1 CP0 pin else - // RTC mode is selected. bit 3: when - // set '1' enable external GPT - // trigger 3 on GPIO1 CP1 pin else - // RTC mode is selected. bit 4: when - // set '1' enable external GPT - // trigger 4 on GPIO2 CP0 pin else - // RTC mode is selected. bit 5: when - // set '1' enable external GPT - // trigger 5 on GPIO2 CP1 pin else - // RTC mode is selected. bit 6: when - // set '1' enable external GPT - // trigger 6 on GPIO3 CP0 pin else - // RTC mode is selected. bit 7: when - // set '1' enable external GPT - // trigger 7 on GPIO3 CP1 pin else - // RTC mode is selected. - -#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \ - 0x00000007 // Capture data from d2d_spare pads - -#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \ - 0x00000007 // Send data to d2d_spare pads - - // eventually this will get - // registered in top die - -#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0 - - - -#endif // __HW_APPS_CONFIG_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_rcm.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_rcm.h deleted file mode 100755 index 997bccd8c2b..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_rcm.h +++ /dev/null @@ -1,1504 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_APPS_RCM_H__ -#define __HW_APPS_RCM_H__ - -//***************************************************************************** -// -// The following are defines for the APPS_RCM register offsets. -// -//***************************************************************************** -#define APPS_RCM_O_CAMERA_CLK_GEN \ - 0x00000000 - -#define APPS_RCM_O_CAMERA_CLK_GATING \ - 0x00000004 - -#define APPS_RCM_O_CAMERA_SOFT_RESET \ - 0x00000008 - -#define APPS_RCM_O_MCASP_CLK_GATING \ - 0x00000014 - -#define APPS_RCM_O_MCASP_SOFT_RESET \ - 0x00000018 - -#define APPS_RCM_O_MMCHS_CLK_GEN \ - 0x00000020 - -#define APPS_RCM_O_MMCHS_CLK_GATING \ - 0x00000024 - -#define APPS_RCM_O_MMCHS_SOFT_RESET \ - 0x00000028 - -#define APPS_RCM_O_MCSPI_A1_CLK_GEN \ - 0x0000002C - -#define APPS_RCM_O_MCSPI_A1_CLK_GATING \ - 0x00000030 - -#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \ - 0x00000034 - -#define APPS_RCM_O_MCSPI_A2_CLK_GEN \ - 0x00000038 - -#define APPS_RCM_O_MCSPI_A2_CLK_GATING \ - 0x00000040 - -#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \ - 0x00000044 - -#define APPS_RCM_O_UDMA_A_CLK_GATING \ - 0x00000048 - -#define APPS_RCM_O_UDMA_A_SOFT_RESET \ - 0x0000004C - -#define APPS_RCM_O_GPIO_A_CLK_GATING \ - 0x00000050 - -#define APPS_RCM_O_GPIO_A_SOFT_RESET \ - 0x00000054 - -#define APPS_RCM_O_GPIO_B_CLK_GATING \ - 0x00000058 - -#define APPS_RCM_O_GPIO_B_SOFT_RESET \ - 0x0000005C - -#define APPS_RCM_O_GPIO_C_CLK_GATING \ - 0x00000060 - -#define APPS_RCM_O_GPIO_C_SOFT_RESET \ - 0x00000064 - -#define APPS_RCM_O_GPIO_D_CLK_GATING \ - 0x00000068 - -#define APPS_RCM_O_GPIO_D_SOFT_RESET \ - 0x0000006C - -#define APPS_RCM_O_GPIO_E_CLK_GATING \ - 0x00000070 - -#define APPS_RCM_O_GPIO_E_SOFT_RESET \ - 0x00000074 - -#define APPS_RCM_O_WDOG_A_CLK_GATING \ - 0x00000078 - -#define APPS_RCM_O_WDOG_A_SOFT_RESET \ - 0x0000007C - -#define APPS_RCM_O_UART_A0_CLK_GATING \ - 0x00000080 - -#define APPS_RCM_O_UART_A0_SOFT_RESET \ - 0x00000084 - -#define APPS_RCM_O_UART_A1_CLK_GATING \ - 0x00000088 - -#define APPS_RCM_O_UART_A1_SOFT_RESET \ - 0x0000008C - -#define APPS_RCM_O_GPT_A0_CLK_GATING \ - 0x00000090 - -#define APPS_RCM_O_GPT_A0_SOFT_RESET \ - 0x00000094 - -#define APPS_RCM_O_GPT_A1_CLK_GATING \ - 0x00000098 - -#define APPS_RCM_O_GPT_A1_SOFT_RESET \ - 0x0000009C - -#define APPS_RCM_O_GPT_A2_CLK_GATING \ - 0x000000A0 - -#define APPS_RCM_O_GPT_A2_SOFT_RESET \ - 0x000000A4 - -#define APPS_RCM_O_GPT_A3_CLK_GATING \ - 0x000000A8 - -#define APPS_RCM_O_GPT_A3_SOFT_RESET \ - 0x000000AC - -#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \ - 0x000000B0 - -#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \ - 0x000000B4 - -#define APPS_RCM_O_CRYPTO_CLK_GATING \ - 0x000000B8 - -#define APPS_RCM_O_CRYPTO_SOFT_RESET \ - 0x000000BC - -#define APPS_RCM_O_MCSPI_S0_CLK_GATING \ - 0x000000C8 - -#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \ - 0x000000CC - -#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \ - 0x000000D0 - -#define APPS_RCM_O_I2C_CLK_GATING \ - 0x000000D8 - -#define APPS_RCM_O_I2C_SOFT_RESET \ - 0x000000DC - -#define APPS_RCM_O_APPS_LPDS_REQ \ - 0x000000E4 - -#define APPS_RCM_O_APPS_TURBO_REQ \ - 0x000000EC - -#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \ - 0x00000108 - -#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \ - 0x0000010C - -#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \ - 0x00000110 - -#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \ - 0x00000114 - -#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \ - 0x00000118 - -#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \ - 0x00000120 - -#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \ - 0x00000124 - - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CAMERA_CLK_GEN register. -// -//****************************************************************************** -#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of Camera func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8 -#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \ - 0x000000F8 - -#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3 -#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \ - 0x00000007 // Configuration of ON-TIME for - // dividing PLL clk (240 MHz) in - // generation of Camera func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CAMERA_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17 -#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable camera clk during - // deep-sleep mode - -#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9 -#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable camera clk during - // sleep mode ; 0- Disable camera - // clk during sleep mode - -#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1 -#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable camera clk during run - // mode ; 0- Disable camera clk - // during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CAMERA_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \ - 0x00000002 // 1 - Camera clocks/resets are - // enabled ; 0 - Camera - // clocks/resets are disabled - -#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for Camera-core - // ; 0 - De-assert reset for - // Camera-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCASP_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MCASP_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17 -#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable MCASP clk during - // deep-sleep mode - -#define APPS_RCM_MCASP_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9 -#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable MCASP clk during sleep - // mode ; 0- Disable MCASP clk - // during sleep mode - -#define APPS_RCM_MCASP_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1 -#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable MCASP clk during run - // mode ; 0- Disable MCASP clk - // during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCASP_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \ - 0x00000002 // 1 - MCASP Clocks/resets are - // enabled ; 0 - MCASP Clocks/resets - // are disabled - -#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for MCASP-core - // ; 0 - De-assert reset for - // MCASP-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MMCHS_CLK_GEN register. -// -//****************************************************************************** -#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MMCHS func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8 -#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \ - 0x000000F8 - -#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3 -#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \ - 0x00000007 // Configuration of ON-TIME for - // dividing PLL clk (240 MHz) in - // generation of MMCHS func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MMCHS_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17 -#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable MMCHS clk during - // deep-sleep mode - -#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9 -#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable MMCHS clk during sleep - // mode ; 0- Disable MMCHS clk - // during sleep mode - -#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1 -#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable MMCHS clk during run - // mode ; 0- Disable MMCHS clk - // during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MMCHS_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \ - 0x00000002 // 1 - MMCHS Clocks/resets are - // enabled ; 0 - MMCHS Clocks/resets - // are disabled - -#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for MMCHS-core - // ; 0 - De-assert reset for - // MMCHS-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A1_CLK_GEN register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \ - 0x00010000 // 0 - XTAL clk is used as baud clk - // for MCSPI_A1 ; 1 - PLL divclk is - // used as baud clk for MCSPI_A1. - -#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \ - 0x0000F800 - -#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11 -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_A1 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8 -#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \ - 0x000000F8 - -#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3 -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \ - 0x00000007 // Configuration of ON-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_A1 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A1_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17 -#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable MCSPI_A1 clk during - // deep-sleep mode - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9 -#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable MCSPI_A1 clk during - // sleep mode ; 0- Disable MCSPI_A1 - // clk during sleep mode - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1 -#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable MCSPI_A1 clk during - // run mode ; 0- Disable MCSPI_A1 - // clk during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A1_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \ - 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are - // enabled ; 0 - MCSPI_A1 - // Clocks/Resets are disabled - -#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for - // MCSPI_A1-core ; 0 - De-assert - // reset for MCSPI_A1-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A2_CLK_GEN register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \ - 0x00010000 // 0 - XTAL clk is used as baud-clk - // for MCSPI_A2 ; 1 - PLL divclk is - // used as baud-clk for MCSPI_A2 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \ - 0x0000F800 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11 -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_A2 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8 -#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \ - 0x000000F8 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3 -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \ - 0x00000007 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_A2 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A2_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17 -#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable MCSPI_A2 clk during - // deep-sleep mode - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9 -#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable MCSPI_A2 clk during - // sleep mode ; 0- Disable MCSPI_A2 - // clk during sleep mode - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1 -#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable MCSPI_A2 clk during - // run mode ; 0- Disable MCSPI_A2 - // clk during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A2_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \ - 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are - // enabled ; 0 - MCSPI_A2 - // Clocks/Resets are disabled - -#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for - // MCSPI_A2-core ; 0 - De-assert - // reset for MCSPI_A2-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UDMA_A_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable UDMA_A clk during - // deep-sleep mode 0 - Disable - // UDMA_A clk during deep-sleep mode - // ; - -#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9 -#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable UDMA_A clk during - // sleep mode 0 - Disable UDMA_A clk - // during sleep mode ; - -#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1 -#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable UDMA_A clk during run - // mode 0 - Disable UDMA_A clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UDMA_A_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \ - 0x00000002 // 1 - UDMA_A Clocks/Resets are - // enabled ; 0 - UDMA_A - // Clocks/Resets are disabled - -#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for DMA_A ; 0 - - // De-assert reset for DMA_A - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_A_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_A clk during - // deep-sleep mode 0 - Disable - // GPIO_A clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_A clk during - // sleep mode 0 - Disable GPIO_A clk - // during sleep mode ; - -#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_A clk during run - // mode 0 - Disable GPIO_A clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_A_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_A Clocks/Resets are - // enabled ; 0 - GPIO_A - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_A ; 0 - // - De-assert reset for GPIO_A - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_B_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_B clk during - // deep-sleep mode 0 - Disable - // GPIO_B clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_B clk during - // sleep mode 0 - Disable GPIO_B clk - // during sleep mode ; - -#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_B clk during run - // mode 0 - Disable GPIO_B clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_B_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_B Clocks/Resets are - // enabled ; 0 - GPIO_B - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_B ; 0 - // - De-assert reset for GPIO_B - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_C_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_C clk during - // deep-sleep mode 0 - Disable - // GPIO_C clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_C clk during - // sleep mode 0 - Disable GPIO_C clk - // during sleep mode ; - -#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_C clk during run - // mode 0 - Disable GPIO_C clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_C_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_C Clocks/Resets are - // enabled ; 0 - GPIO_C - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_C ; 0 - // - De-assert reset for GPIO_C - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_D_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_D clk during - // deep-sleep mode 0 - Disable - // GPIO_D clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_D clk during - // sleep mode 0 - Disable GPIO_D clk - // during sleep mode ; - -#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_D clk during run - // mode 0 - Disable GPIO_D clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_D_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_D Clocks/Resets are - // enabled ; 0 - GPIO_D - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_D ; 0 - // - De-assert reset for GPIO_D - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_E_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_E clk during - // deep-sleep mode 0 - Disable - // GPIO_E clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_E clk during - // sleep mode 0 - Disable GPIO_E clk - // during sleep mode ; - -#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_E clk during run - // mode 0 - Disable GPIO_E clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_E_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_E Clocks/Resets are - // enabled ; 0 - GPIO_E - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_E ; 0 - // - De-assert reset for GPIO_E - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_WDOG_A_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \ - 0x03000000 // "00" - Sysclk ; "01" - REF_CLK - // (38.4 MHz) ; "10/11" - Slow_clk - -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24 -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable WDOG_A clk during - // deep-sleep mode 0 - Disable - // WDOG_A clk during deep-sleep mode - // ; - -#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9 -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable WDOG_A clk during - // sleep mode 0 - Disable WDOG_A clk - // during sleep mode ; - -#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1 -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable WDOG_A clk during run - // mode 0 - Disable WDOG_A clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_WDOG_A_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \ - 0x00000002 // 1 - WDOG_A Clocks/Resets are - // enabled ; 0 - WDOG_A - // Clocks/Resets are disabled - -#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for WDOG_A ; 0 - // - De-assert reset for WDOG_A - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UART_A0_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable UART_A0 clk during - // deep-sleep mode 0 - Disable - // UART_A0 clk during deep-sleep - // mode ; - -#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9 -#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable UART_A0 clk during - // sleep mode 0 - Disable UART_A0 - // clk during sleep mode ; - -#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1 -#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable UART_A0 clk during - // run mode 0 - Disable UART_A0 clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UART_A0_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \ - 0x00000002 // 1 - UART_A0 Clocks/Resets are - // enabled ; 0 - UART_A0 - // Clocks/Resets are disabled - -#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for UART_A0 ; 0 - // - De-assert reset for UART_A0 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UART_A1_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable UART_A1 clk during - // deep-sleep mode 0 - Disable - // UART_A1 clk during deep-sleep - // mode ; - -#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9 -#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable UART_A1 clk during - // sleep mode 0 - Disable UART_A1 - // clk during sleep mode ; - -#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1 -#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable UART_A1 clk during - // run mode 0 - Disable UART_A1 clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UART_A1_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \ - 0x00000002 // 1 - UART_A1 Clocks/Resets are - // enabled ; 0 - UART_A1 - // Clocks/Resets are disabled - -#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // UART_A1 ; 0 - De-assert the soft - // reset for UART_A1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A0_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the GPT_A0 clock - // during deep-sleep ; 0 - Disable - // the GPT_A0 clock during - // deep-sleep - -#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the GPT_A0 clock - // during sleep ; 0 - Disable the - // GPT_A0 clock during sleep - -#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the GPT_A0 clock - // during run ; 0 - Disable the - // GPT_A0 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A0_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \ - 0x00000002 // 1 - GPT_A0 clocks/resets are - // enabled ; 0 - GPT_A0 - // clocks/resets are disabled - -#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // GPT_A0 ; 0 - De-assert the soft - // reset for GPT_A0 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A1_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the GPT_A1 clock - // during deep-sleep ; 0 - Disable - // the GPT_A1 clock during - // deep-sleep - -#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the GPT_A1 clock - // during sleep ; 0 - Disable the - // GPT_A1 clock during sleep - -#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the GPT_A1 clock - // during run ; 0 - Disable the - // GPT_A1 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A1_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \ - 0x00000002 // 1 - GPT_A1 clocks/resets are - // enabled ; 0 - GPT_A1 - // clocks/resets are disabled - -#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // GPT_A1 ; 0 - De-assert the soft - // reset for GPT_A1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A2_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the GPT_A2 clock - // during deep-sleep ; 0 - Disable - // the GPT_A2 clock during - // deep-sleep - -#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the GPT_A2 clock - // during sleep ; 0 - Disable the - // GPT_A2 clock during sleep - -#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the GPT_A2 clock - // during run ; 0 - Disable the - // GPT_A2 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A2_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \ - 0x00000002 // 1 - GPT_A2 clocks/resets are - // enabled ; 0 - GPT_A2 - // clocks/resets are disabled - -#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // GPT_A2 ; 0 - De-assert the soft - // reset for GPT_A2 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A3_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the GPT_A3 clock - // during deep-sleep ; 0 - Disable - // the GPT_A3 clock during - // deep-sleep - -#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the GPT_A3 clock - // during sleep ; 0 - Disable the - // GPT_A3 clock during sleep - -#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the GPT_A3 clock - // during run ; 0 - Disable the - // GPT_A3 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A3_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \ - 0x00000002 // 1 - GPT_A3 Clocks/resets are - // enabled ; 0 - GPT_A3 - // Clocks/resets are disabled - -#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // GPT_A3 ; 0 - De-assert the soft - // reset for GPT_A3 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register. -// -//****************************************************************************** -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \ - 0x03FF0000 - -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16 -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \ - 0x0000FFFF - -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register. -// -//****************************************************************************** -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \ - 0x00010000 // 1 - Assert the reset for MCASP - // Frac-clk div; 0 - Donot assert - // the reset for MCASP frac clk-div - -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \ - 0x000003FF - -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CRYPTO_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable the Crypto clock - // during deep-sleep - -#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9 -#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the Crypto clock - // during sleep ; 0 - Disable the - // Crypto clock during sleep - -#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1 -#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the Crypto clock - // during run ; 0 - Disable the - // Crypto clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CRYPTO_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \ - 0x00000002 // 1 - Crypto clocks/resets are - // enabled ; 0 - Crypto - // clocks/resets are disabled - -#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // Crypto ; 0 - De-assert the soft - // reset for Crypto - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_S0_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable the MCSPI_S0 clock - // during deep-sleep - -#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9 -#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the MCSPI_S0 clock - // during sleep ; 0 - Disable the - // MCSPI_S0 clock during sleep - -#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1 -#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the MCSPI_S0 clock - // during run ; 0 - Disable the - // MCSPI_S0 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_S0_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \ - 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are - // enabled ; 0 - MCSPI_S0 - // Clocks/resets are disabled - -#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // MCSPI_S0 ; 0 - De-assert the soft - // reset for MCSPI_S0 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \ - 0x00010000 // 0 - XTAL clk is used as baud-clk - // for MCSPI_S0 ; 1 - PLL divclk is - // used as buad-clk for MCSPI_S0 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \ - 0x0000F800 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11 -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_S0 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8 -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \ - 0x000000F8 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3 -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \ - 0x00000007 // Configuration of ON-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_S0 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_I2C_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the I2C Clock during - // deep-sleep 0 - Disable the I2C - // clock during deep-sleep - -#define APPS_RCM_I2C_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_I2C_CLK_GATING_NU1_S 9 -#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the I2C clock during - // sleep ; 0 - Disable the I2C clock - // during sleep - -#define APPS_RCM_I2C_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_I2C_CLK_GATING_NU2_S 1 -#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the I2C clock during - // run ; 0 - Disable the I2C clock - // during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_I2C_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \ - 0x00000002 // 1 - I2C Clocks/Resets are - // enabled ; 0 - I2C clocks/resets - // are disabled - -#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // Shared-I2C ; 0 - De-assert the - // soft reset for Shared-I2C - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_LPDS_REQ register. -// -//****************************************************************************** -#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \ - 0x00000001 // 1 - Request for LPDS - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_TURBO_REQ register. -// -//****************************************************************************** -#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \ - 0x00000001 // 1 - Request for TURBO - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register. -// -//****************************************************************************** -#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \ - 0x00000002 // 1 - Enable the NWP to wake APPS - // from deep-sleep ; 0 - Disable NWP - // to wake APPS from deep-sleep - -#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \ - 0x00000001 // 1 - Enable deep-sleep wake timer - // in APPS RCM for deep-sleep; 0 - - // Disable deep-sleep wake timer in - // APPS RCM - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register. -// -//****************************************************************************** -#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \ - 0xFFFF0000 // Configuration (in slow_clks) - // which says when to request for - // OPP during deep-sleep exit - -#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16 -#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \ - 0x0000FFFF // Configuration (in slow_clks) - // which says when to request for - // WAKE during deep-sleep exit - -#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register. -// -//****************************************************************************** -#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \ - 0x00000002 // 1- Enable the sleep wakeup due - // to NWP request. 0- Disable the - // sleep wakeup due to NWP request - -#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \ - 0x00000001 // 1- Enable the sleep wakeup due - // to sleep-timer; 0-Disable the - // sleep wakeup due to sleep-timer - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register. -// -//****************************************************************************** -#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \ - 0xFFFFFFFF // Configuration (number of - // sysclks-80MHz) for the Sleep - // wakeup timer - -#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register. -// -//****************************************************************************** -#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \ - 0x00000001 // When 1 => APPS generated a wake - // request to NWP (When NWP is in - // any of its low-power modes : - // SLP/DSLP/LPDS) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register. -// -//****************************************************************************** -#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \ - 0x00000008 // 1 - Indicates that deep-sleep - // timer expiry had caused the - // wakeup from deep-sleep - -#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \ - 0x00000004 // 1 - Indicates that sleep timer - // expiry had caused the wakeup from - // sleep - -#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \ - 0x00000002 // 1 - Indicates that NWP had - // caused the wakeup from deep-sleep - -#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \ - 0x00000001 // 1 - Indicates that NWP had - // caused the wakeup from Sleep - - - - -#endif // __HW_APPS_RCM_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_camera.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_camera.h deleted file mode 100755 index 11e4edb0e37..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_camera.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_CAMERA_H__ -#define __HW_CAMERA_H__ - -//***************************************************************************** -// -// The following are defines for the CAMERA register offsets. -// -//***************************************************************************** -#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP - // revision code ( Parallel Mode) -#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the - // various parameters of the OCP - // interface (CCP and Parallel Mode) -#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status - // information about the module - // excluding the interrupt status - // information (CCP and Parallel - // Mode) -#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups - // all the status of the module - // internal events that can generate - // an interrupt (CCP & Parallel - // Mode) -#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register - // allows to enable/disable the - // module internal sources of - // interrupt on an event-by-event - // basis (CCP & Parallel Mode) -#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the - // various parameters of the Camera - // Core block (CCP & Parallel Mode) -#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA - // interface of the Camera Core - // block (CCP & Parallel Mode) -#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value - // of the clock divisor used to - // generate the external clock - // (Parallel Mode) -#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to - // the FIFO and read from the FIFO - // (CCP & Parallel Mode) -#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status - // of some important variables of - // the camera core module (CCP & - // Parallel Mode) -#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values - // of the generic parameters of the - // module - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_REVISION register. -// -//****************************************************************************** -#define CAMERA_CC_REVISION_REV_M \ - 0x000000FF // IP revision [7:4] Major revision - // [3:0] Minor revision Examples: - // 0x10 for 1.0 0x21 for 2.1 - -#define CAMERA_CC_REVISION_REV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_SYSCONFIG register. -// -//****************************************************************************** -#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \ - 0x00000018 // Slave interface power management - // req/ack control """00"" - // Force-idle. An idle request is - // acknoledged unconditionally" - // """01"" No-idle. An idle request - // is never acknowledged" """10"" - // reserved (Smart-idle not - // implemented)" - -#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3 -#define CAMERA_CC_SYSCONFIG_SOFT_RESET \ - 0x00000002 // Software reset. Set this bit to - // 1 to trigger a module reset. The - // bit is automatically reset by the - // hardware. During reset it always - // returns 0. 0 Normal mode 1 The - // module is reset - -#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \ - 0x00000001 // Internal OCP clock gating - // strategy 0 OCP clock is - // free-running 1 Automatic OCP - // clock gating strategy is applied - // based on the OCP interface - // activity - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_SYSSTATUS register. -// -//****************************************************************************** -#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \ - 0x00000001 // Internal Reset Monitoring 0 - // Internal module reset is on-going - // 1 Reset completed - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_IRQSTATUS register. -// -//****************************************************************************** -#define CAMERA_CC_IRQSTATUS_FS_IRQ \ - 0x00080000 // Frame Start has occurred 0 Event - // false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_LE_IRQ \ - 0x00040000 // Line End has occurred 0 Event - // false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_LS_IRQ \ - 0x00020000 // Line Start has occurred 0 Event - // false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FE_IRQ \ - 0x00010000 // Frame End has occurred 0 Event - // false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \ - 0x00000800 // FSP code error 0 Event false "1 - // Event is true (""pending"")" 0 - // Event status bit unchanged 1 - // Event status bit is reset - -#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \ - 0x00000400 // Frame Height Error 0 Event false - // "1 Event is true (""pending"")" 0 - // Event status bit unchanged 1 - // Event status bit is reset - -#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \ - 0x00000200 // False Synchronization Code 0 - // Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \ - 0x00000100 // Shifted Synchronization Code 0 - // Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \ - 0x00000010 // FIFO is not empty 0 Event false - // "1 Event is true (""pending"")" 0 - // Event status bit unchanged 1 - // Event status bit is reset - -#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \ - 0x00000008 // FIFO is full 0 Event false "1 - // Event is true (""pending"")" 0 - // Event status bit unchanged 1 - // Event status bit is reset - -#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \ - 0x00000004 // FIFO threshold has been reached - // 0 Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \ - 0x00000002 // FIFO overflow has occurred 0 - // Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \ - 0x00000001 // FIFO underflow has occurred 0 - // Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_IRQENABLE register. -// -//****************************************************************************** -#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \ - 0x00080000 // Frame Start Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \ - 0x00040000 // Line End Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \ - 0x00020000 // Line Start Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \ - 0x00010000 // Frame End Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \ - 0x00000800 // FSP code Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \ - 0x00000400 // Frame Height Error Interrupt - // Enable 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \ - 0x00000200 // False Synchronization Code - // Interrupt Enable 0 Event is - // masked 1 Event generates an - // interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \ - 0x00000100 // False Synchronization Code - // Interrupt Enable 0 Event is - // masked 1 Event generates an - // interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \ - 0x00000010 // FIFO Threshold Interrupt Enable - // 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \ - 0x00000008 // FIFO Threshold Interrupt Enable - // 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \ - 0x00000004 // FIFO Threshold Interrupt Enable - // 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \ - 0x00000002 // FIFO Overflow Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \ - 0x00000001 // FIFO Underflow Interrupt Enable - // 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -//****************************************************************************** -// -// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register. -// -//****************************************************************************** -#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \ - 0x00080000 // Synchronize all camera sensor - // inputs This must be set during - // the configuration phase before - // CC_EN set to '1'. This can be - // used in very high frequency to - // avoid dependancy to the IO - // timings. 0 No synchro (most of - // applications) 1 Synchro enabled - // (should never be required) - -#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite - // states machines of the camera - // core module - by writing a 1 to - // this bit. must be applied when - // CC_EN = 0 Reads returns 0 -#define CAMERA_CC_CTRL_CC_FRAME_TRIG \ - 0x00020000 // Set the modality in which CC_EN - // works when a disabling of the - // sensor camera core is wanted "If - // CC_FRAME_TRIG = 1 by writing - // ""0"" to CC_EN" the module is - // disabled at the end of the frame - // "If CC_FRAME_TRIG = 0 by writing - // ""0"" to CC_EN" the module is - // disabled immediately - -#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of - // the camera core module "By - // writing ""1"" to this field the - // module is enabled." "By writing - // ""0"" to this field the module is - // disabled at" the end of the frame - // if CC_FRAM_TRIG =1 and is - // disabled immediately if - // CC_FRAM_TRIG = 0 -#define CAMERA_CC_CTRL_NOBT_SYNCHRO \ - 0x00002000 // Enables to start at the - // beginning of the frame or not in - // NoBT 0 Acquisition starts when - // Vertical synchro is high 1 - // Acquisition starts when Vertical - // synchro goes from low to high - // (beginning of the frame) - - // Recommended. - -#define CAMERA_CC_CTRL_BT_CORRECT \ - 0x00001000 // Enables the correction within - // the sync codes in BT mode 0 - // correction is not enabled 1 - // correction is enabled - -#define CAMERA_CC_CTRL_PAR_ORDERCAM \ - 0x00000800 // Enables swap between image-data - // in parallel mode 0 swap is not - // enabled 1 swap is enabled - -#define CAMERA_CC_CTRL_PAR_CLK_POL \ - 0x00000400 // Inverts the clock coming from - // the sensor in parallel mode 0 - // clock not inverted - data sampled - // on rising edge 1 clock inverted - - // data sampled on falling edge - -#define CAMERA_CC_CTRL_NOBT_HS_POL \ - 0x00000200 // Sets the polarity of the - // synchronization signals in NOBT - // parallel mode 0 CAM_P_HS is - // active high 1 CAM_P_HS is active - // low - -#define CAMERA_CC_CTRL_NOBT_VS_POL \ - 0x00000100 // Sets the polarity of the - // synchronization signals in NOBT - // parallel mode 0 CAM_P_VS is - // active high 1 CAM_P_VS is active - // low - -#define CAMERA_CC_CTRL_PAR_MODE_M \ - 0x0000000E // Sets the Protocol Mode of the - // Camera Core module in parallel - // mode (when CCP_MODE = 0) """000"" - // Parallel NOBT 8-bit" """001"" - // Parallel NOBT 10-bit" """010"" - // Parallel NOBT 12-bit" """011"" - // reserved" """100"" Parallet BT - // 8-bit" """101"" Parallel BT - // 10-bit" """110"" reserved" - // """111"" FIFO test mode. Refer to - // Table 12 - FIFO Write and Read - // access" - -#define CAMERA_CC_CTRL_PAR_MODE_S 1 -#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode - // 0 CCP mode disabled 1 CCP mode - // enabled -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_CTRL_DMA register. -// -//****************************************************************************** -#define CAMERA_CC_CTRL_DMA_DMA_EN \ - 0x00000100 // Sets the number of dma request - // lines 0 DMA interface disabled - // The DMA request line stays - // inactive 1 DMA interface enabled - // The DMA request line is - // operational - -#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \ - 0x0000007F // Sets the threshold of the FIFO - // the assertion of the dmarequest - // line takes place when the - // threshold is reached. - // """0000000"" threshold set to 1" - // """0000001"" threshold set to 2" - // … """1111111"" threshold set to - // 128" - -#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_CTRL_XCLK register. -// -//****************************************************************************** -#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \ - 0x0000001F // Sets the clock divisor value for - // CAM_XCLK generation. based on - // CAM_MCK (value of CAM_MCLK is - // 96MHz) """00000"" CAM_XCLK Stable - // Low Level" Divider not enabled - // """00001"" CAM_XCLK Stable High - // Level" Divider not enabled from 2 - // to 30 CAM_XCLK = CAM_MCLK / - // XCLK_DIV """11111"" Bypass - - // CAM_XCLK = CAM_MCLK" - -#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_FIFO_DATA register. -// -//****************************************************************************** -#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \ - 0xFFFFFFFF // Writes the 32-bit word into the - // FIFO Reads the 32-bit word from - // the FIFO - -#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the CAMERA_O_CC_TEST register. -// -//****************************************************************************** -#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \ - 0xFF000000 // FIFO READ Pointer This field - // shows the value of the FIFO read - // pointer Expected value ranges - // from 0 to 127 - -#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24 -#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \ - 0x00FF0000 // FIFO WRITE pointer This field - // shows the value of the FIFO write - // pointer Expected value ranges - // from 0 to 127 - -#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16 -#define CAMERA_CC_TEST_FIFO_LEVEL_M \ - 0x0000FF00 // FIFO level (how many 32-bit - // words the FIFO contains) This - // field shows the value of the FIFO - // level and can assume values from - // 0 to 128 - -#define CAMERA_CC_TEST_FIFO_LEVEL_S 8 -#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \ - 0x000000FF // FIFO level peak This field shows - // the max value of the FIFO level - // and can assume values from 0 to - // 128 - -#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_GEN_PAR register. -// -//****************************************************************************** -#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \ - 0x00000007 // Camera Core FIFO DEPTH generic - // parameter - -#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0 - - - -#endif // __HW_CAMERA_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_common_reg.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_common_reg.h deleted file mode 100755 index f296e1c533b..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_common_reg.h +++ /dev/null @@ -1,1115 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_COMMON_REG_H__ -#define __HW_COMMON_REG_H__ - -//***************************************************************************** -// -// The following are defines for the COMMON_REG register offsets. -// -//***************************************************************************** -#define COMMON_REG_O_I2C_Properties_Register \ - 0x00000000 - -#define COMMON_REG_O_SPI_Properties_Register \ - 0x00000004 - -#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \ - 0x0000000C - -#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \ - 0x00000010 - -#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \ - 0x00000014 - -#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \ - 0x00000018 - -#define COMMON_REG_O_Flash_ctrl_reg \ - 0x0000001C - -#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \ - 0x00000024 - -#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \ - 0x00000028 - -#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \ - 0x0000002C - -#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \ - 0x00000030 - -#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \ - 0x00000034 - -#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \ - 0x00000038 - -#define COMMON_REG_O_GPIO_properties_register \ - 0x0000003C - -#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \ - 0x00000040 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \ - 0x00000044 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \ - 0x00000048 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \ - 0x0000004C - -#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \ - 0x00000050 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \ - 0x00000054 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \ - 0x00000058 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \ - 0x0000005C - -#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \ - 0x00000060 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \ - 0x00000064 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \ - 0x00000068 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \ - 0x0000006C - -#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \ - 0x00000070 - -#define COMMON_REG_O_NW_SEMAPPHORE_PEND \ - 0x00000074 - -#define COMMON_REG_O_SEMAPHORE_STATUS \ - 0x00000078 - -#define COMMON_REG_O_IDMEM_TIM_Update \ - 0x0000007C - -#define COMMON_REG_O_FPGA_ROM_WR_EN \ - 0x00000080 - -#define COMMON_REG_O_NW_INT_MASK \ - 0x00000084 - -#define COMMON_REG_O_NW_INT_MASK_SET \ - 0x00000088 - -#define COMMON_REG_O_NW_INT_MASK_CLR \ - 0x0000008C - -#define COMMON_REG_O_NW_INT_STS_CLR \ - 0x00000090 - -#define COMMON_REG_O_NW_INT_ACK 0x00000094 -#define COMMON_REG_O_NW_INT_TRIG \ - 0x00000098 - -#define COMMON_REG_O_NW_INT_STS_MASKED \ - 0x0000009C - -#define COMMON_REG_O_NW_INT_STS_RAW \ - 0x000000A0 - -#define COMMON_REG_O_APPS_INT_MASK \ - 0x000000A4 - -#define COMMON_REG_O_APPS_INT_MASK_SET \ - 0x000000A8 - -#define COMMON_REG_O_APPS_INT_MASK_CLR \ - 0x000000AC - -#define COMMON_REG_O_APPS_INT_STS_CLR \ - 0x000000B0 - -#define COMMON_REG_O_APPS_INT_ACK \ - 0x000000B4 - -#define COMMON_REG_O_APPS_INT_TRIG \ - 0x000000B8 - -#define COMMON_REG_O_APPS_INT_STS_MASKED \ - 0x000000BC - -#define COMMON_REG_O_APPS_INT_STS_RAW \ - 0x000000C0 - -#define COMMON_REG_O_IDMEM_TIM_Updated \ - 0x000000C4 - -#define COMMON_REG_O_APPS_GPIO_TRIG_EN \ - 0x000000C8 - -#define COMMON_REG_O_EMU_DEBUG_REG \ - 0x000000CC - -#define COMMON_REG_O_SEMAPHORE_STATUS2 \ - 0x000000D0 - -#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \ - 0x000000D4 - -#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \ - 0x000000D8 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_I2C_Properties_Register register. -// -//****************************************************************************** -#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \ - 0x00000003 // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SPI_Properties_Register register. -// -//****************************************************************************** -#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \ - 0x00000003 // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register. -// -//****************************************************************************** -#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \ - 0x0000000F // Interrupt enable APPS bit 0 -> - // when '1' enable I2C interrupt bit - // 1 -> when '1' enable SPI - // interrupt bit 3 -> - // when '1' enable GPIO interrupt - -#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_sh_resource_Interrupt_status register. -// -//****************************************************************************** -#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \ - 0x0000000F // Interrupt enable APPS bit 0 -> - // when '1' enable I2C interrupt bit - // 1 -> when '1' enable SPI - // interrupt bit 3 -> - // when '1' enable GPIO interrupt - -#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register. -// -//****************************************************************************** -#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \ - 0x0000000F // Interrupt enable NWP bit 0 -> - // when '1' enable I2C interrupt bit - // 1 -> when '1' enable SPI - // interrupt bit 3 -> - // when '1' enable GPIO interrupt - -#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NWP_sh_resource_Interrupt_status register. -// -//****************************************************************************** -#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \ - 0x0000000F // Interrupt enable NWP bit 0 -> - // when '1' enable I2C interrupt bit - // 1 -> when '1' enable SPI - // interrupt bit 3 -> - // when '1' enable GPIO interrupt - -#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Flash_ctrl_reg register. -// -//****************************************************************************** -#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \ - 0x00000003 // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M0_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \ - 0x0003FFFF // Master 0 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M1_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \ - 0x0003FFFF // Master 1 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M2_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \ - 0x0003FFFF // Master 2 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M3_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \ - 0x0003FFFF // Master 3 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M4_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \ - 0x0003FFFF // Master 4 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M5_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \ - 0x0003FFFF // Master 5 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_GPIO_properties_register register. -// -//****************************************************************************** -#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \ - 0x000003FF // Shared GPIO configuration - // register. Bit [1:0] to configure - // GPIO0 Bit [3:2] to configure - // GPIO1 Bit [5:4] to configure - // GPIO2 Bit [7:6] to configure - // GPIO3 Bit [9:8] to configure - // GPIO4 each GPIO can be - // individully selected. When “00�? - // GPIO is free resource. When “01�? - // GPIO is APPS resource. When “10�? - // GPIO is NWP resource. Writing 11 - // doesnt have any affect, i.e. If - // one write only relevant gpio - // semaphore and other bits are 1s, - // it'll not disturb the other - // semaphore bits. For example : Say - // If NW wants to take control of - // gpio-1, one should write - // 10'b11_1111_1011 and if one wants - // to release it write - // 10'b11_1111_0011. - -#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE1 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE2 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE3 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE4 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE5 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE6 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE7 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE8 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE9 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE10 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE11 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE12 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \ - 0xFFFFFFFF // APPS NW semaphore register - not - // reflected in status. - -#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_SEMAPPHORE_PEND register. -// -//****************************************************************************** -#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \ - 0xFFFFFFFF // APPS SEMAPOHORE STATUS - -#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_SEMAPPHORE_PEND register. -// -//****************************************************************************** -#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \ - 0xFFFFFFFF // NW SEMAPHORE STATUS - -#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SEMAPHORE_STATUS register. -// -//****************************************************************************** -#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \ - 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore - // status of flash_control 7:6 - // :semaphore status of - // gpio_properties 5:4 - // :semaphore status of - // spi_propertie 1:0 :semaphore - // status of i2c_propertie - -#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_IDMEM_TIM_Update register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_FPGA_ROM_WR_EN register. -// -//****************************************************************************** -#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \ - 0x00000001 // when '1' enables Write into - // IDMEM CORE ROM, APPS ROM, NWP ROM - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_MASK register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \ - 0xFFFFFFFF // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_MASK_SET register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \ - 0xFFFFFFFF // write 1 to set corresponding bit - // in NW_INT_MASK;0 = no effect - -#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_MASK_CLR register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // bit in NW_INT_MASK;0 = no effect - -#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_STS_CLR register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // interrupt; 0 = no effect; - // interrupt is not lost if coincide - // with write operation - -#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_ACK register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // interrupt;0 = no effect - -#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_TRIG register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \ - 0xFFFFFFFF // Writing a 1 to a bit in this - // register causes the the Host CPU - // if enabled (not masked). This - // register is self-clearing. - // Writing 0 has no effect - -#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_STS_MASKED register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \ - 0xFFFFFFFF // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by NW_INT mask - -#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_STS_RAW register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \ - 0xFFFFFFFF // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_MASK register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \ - 0xFFFFFFFF // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_MASK_SET register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \ - 0xFFFFFFFF // write 1 to set corresponding bit - // in APPS_INT_MASK;0 = no effect - -#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_MASK_CLR register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // bit in APPS_INT_MASK;0 = no - // effect - -#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_STS_CLR register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // interrupt; 0 = no effect; - // interrupt is not lost if coincide - // with write operation - -#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_ACK register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // interrupt;0 = no effect - -#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_TRIG register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \ - 0xFFFFFFFF // Writing a 1 to a bit in this - // register causes the the Host CPU - // if enabled (not masked). This - // register is self-clearing. - // Writing 0 has no effect - -#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_STS_MASKED register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \ - 0xFFFFFFFF // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by APPS_INT mask - -#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_STS_RAW register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \ - 0xFFFFFFFF // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_IDMEM_TIM_Updated register. -// -//****************************************************************************** -#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \ - 0x00000001 // toggle in this signal - // indicatesIDMEM_TIM_UPDATE - // register mentioned above is - // updated. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_GPIO_TRIG_EN register. -// -//****************************************************************************** -#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \ - 0x0000001F // APPS GPIO Trigger EN control. - // Bit 0: when '1' enable GPIO 0 - // trigger. This bit enables trigger - // for all GPIO 0 pins (GPIO 0 to - // GPIO7). Bit 1: when '1' enable - // GPIO 1 trigger. This bit enables - // trigger for all GPIO 1 pins ( - // GPIO8 to GPIO15). Bit 2: when '1' - // enable GPIO 2 trigger. This bit - // enables trigger for all GPIO 2 - // pins (GPIO16 to GPIO23). Bit 3: - // when '1' enable GPIO 3 trigger. - // This bit enables trigger for all - // GPIO 3 pins (GPIO24 to GPIO31). - // Bit 4: when '1' enable GPIO 4 - // trigger. This bit enables trigger - // for all GPIO 4 pins.(GPIO32 to - // GPIO39) - -#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_EMU_DEBUG_REG register. -// -//****************************************************************************** -#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \ - 0xFFFFFFFF // 0 th bit used for stalling APPS - // DMA and 1st bit is used for - // stalling NWP DMA for debug - // purpose. Other bits are unused. - -#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SEMAPHORE_STATUS2 register. -// -//****************************************************************************** -#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \ - 0x00FFFFFF // SEMAPHORE STATUS 23:22 - // :semaphore status of - // apps_nw_semaphore11 21:20 - // :semaphore status of - // apps_nw_semaphore11 19:18 - // :semaphore status of - // apps_nw_semaphore10 17:16 - // :semaphore status of - // apps_nw_semaphore9 15:14 - // :semaphore status of - // apps_nw_semaphore8 13:12 - // :semaphore status of - // apps_nw_semaphore7 11:10 - // :semaphore status of - // apps_nw_semaphore6 9:8 :semaphore - // status of apps_nw_semaphore5 7:6 - // :semaphore status of - // apps_nw_semaphore4 5:4 :semaphore - // status of apps_nw_semaphore3 3:2 - // :semaphore status of - // apps_nw_semaphore2 1:0 :semaphore - // status of apps_nw_semaphore1 - -#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register. -// -//****************************************************************************** -#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \ - 0x0003FFFF // 1:0 : prvious owner of - // i2c_properties_reg[1:0] 3:2 : - // prvious owner of - // spi_properties_reg[1:0] 5:4 : - // prvious owner of - // gpio_properties_reg[1:0] 9:8 : - // prvious owner of - // gpio_properties_reg[3:2] 11:10 : - // prvious owner of - // gpio_properties_reg[5:4] 13:12 : - // prvious owner of - // gpio_properties_reg[7:6] 15:14 : - // prvious owner of - // gpio_properties_reg[9:8] 17:16 : - // prvious owner of - // flash_control_reg[1:0] - -#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register. -// -//****************************************************************************** -#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \ - 0x00FFFFFF // 1:0 : previous owner of - // apps_nw_semaphore1_reg[1:0] 3:2 : - // previous owner of - // apps_nw_semaphore2_reg[1:0] 5:4 : - // previous owner of - // apps_nw_semaphore3_reg[1:0] 7:6 : - // previous owner of - // apps_nw_semaphore4_reg[1:0] 9:8 : - // previous owner of - // apps_nw_semaphore5_reg[1:0] 11:10 - // : previous owner of - // apps_nw_semaphore6_reg[1:0] 13:12 - // : previous owner of - // apps_nw_semaphore7_reg[1:0] 15:14 - // : previous owner of - // apps_nw_semaphore8_reg[1:0] 17:16 - // : previous owner of - // apps_nw_semaphore9_reg[1:0] 19:18 - // : previous owner of - // apps_nw_semaphore10_reg[1:0] - // 21:20 : previous owner of - // apps_nw_semaphore11_reg[1:0] - // 23:22 : previous owner of - // apps_nw_semaphore12_reg[1:0] - -#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0 - - - -#endif // __HW_COMMON_REG_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_des.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_des.h deleted file mode 100755 index 7d8de2c32fc..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_des.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_DES_H__ -#define __HW_DES_H__ - -//***************************************************************************** -// -// The following are defines for the DES_P register offsets. -// -//***************************************************************************** -#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key -#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key -#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key -#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key -#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit - // key/192-bit key -#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit - // key/192-bit key -#define DES_O_IV_L 0x00000018 // Initialization vector LSW -#define DES_O_IV_H 0x0000001C // Initialization vector MSW -#define DES_O_CTRL 0x00000020 -#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data - // length in bytes for all modes. - // Once processing is started with - // this context this length - // decrements to zero. Data lengths - // up to (2^32 – 1) bytes are - // allowed. A write to this register - // triggers the engine to start - // using this context. For a Host - // read operation these registers - // return all-zeroes. -#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write - // encrypted/decrypted data. -#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write - // encrypted/decrypted data. -#define DES_O_REVISION 0x00000030 -#define DES_O_SYSCONFIG 0x00000034 -#define DES_O_SYSSTATUS 0x00000038 -#define DES_O_IRQSTATUS 0x0000003C // This register indicates the - // interrupt status. If one of the - // interrupt bits is set the - // interrupt output will be asserted -#define DES_O_IRQENABLE 0x00000040 // This register contains an enable - // bit for each unique interrupt - // generated by the module. It - // matches the layout of - // DES_IRQSTATUS register. An - // interrupt is enabled when the bit - // in this register is set to 1 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY3_L register. -// -//****************************************************************************** -#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3 -#define DES_KEY3_L_KEY3_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY3_H register. -// -//****************************************************************************** -#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3 -#define DES_KEY3_H_KEY3_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY2_L register. -// -//****************************************************************************** -#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2 -#define DES_KEY2_L_KEY2_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY2_H register. -// -//****************************************************************************** -#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2 -#define DES_KEY2_H_KEY2_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY1_L register. -// -//****************************************************************************** -#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1 -#define DES_KEY1_L_KEY1_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY1_H register. -// -//****************************************************************************** -#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1 -#define DES_KEY1_H_KEY1_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IV_L register. -// -//****************************************************************************** -#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC - // CFB modes -#define DES_IV_L_IV_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IV_H register. -// -//****************************************************************************** -#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC - // CFB modes -#define DES_IV_H_IV_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_CTRL register. -// -//****************************************************************************** -#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit - // indicates that the context data - // registers can be overwritten and - // the host is permitted to write - // the next context. -#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0 - // ecb mode 0x1 cbc mode 0x2 cfb - // mode 0x3 reserved -#define DES_CTRL_MODE_S 4 -#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES - // encryption/decryption. 0 des mode - // 1 tdes mode -#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0 - // decryption is selected 1 - // Encryption is selected -#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to - // encrypt/decrypt data -#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data - // decrypted/encrypted ready -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_LENGTH register. -// -//****************************************************************************** -#define DES_LENGTH_LENGTH_M 0xFFFFFFFF -#define DES_LENGTH_LENGTH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DATA_L register. -// -//****************************************************************************** -#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption -#define DES_DATA_L_DATA_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DATA_H register. -// -//****************************************************************************** -#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption -#define DES_DATA_H_DATA_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_REVISION register. -// -//****************************************************************************** -#define DES_REVISION_SCHEME_M 0xC0000000 -#define DES_REVISION_SCHEME_S 30 -#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define DES_REVISION_FUNC_S 16 -#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP - // design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define DES_REVISION_R_RTL_S 11 -#define DES_REVISION_X_MAJOR_M \ - 0x00000700 // Major Revision (X) maintained by - // IP specification owner. X changes - // ONLY when: (1) There is a major - // feature addition. An example - // would be adding Master Mode to - // Utopia Level2. The Func field (or - // Class/Type in old PID format) - // will remain the same. X does NOT - // change due to: (1) Bug fixes (2) - // Change in feature parameters. - -#define DES_REVISION_X_MAJOR_S 8 -#define DES_REVISION_CUSTOM_M 0x000000C0 -#define DES_REVISION_CUSTOM_S 6 -#define DES_REVISION_Y_MINOR_M \ - 0x0000003F // Minor Revision (Y) maintained by - // IP specification owner. Y changes - // ONLY when: (1) Features are - // scaled (up or down). Flexibility - // exists in that this feature - // scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R S X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless the spec tracks the - // IP bugs. An RTL release (say for - // silicon PG1.1) that occurs due to - // bug fix should document the - // corresponding spec number (X.Y.S) - // in its release notes. - -#define DES_REVISION_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_SYSCONFIG register. -// -//****************************************************************************** -#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ - 0x00000080 // If set to ‘1’ the DMA context - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ - 0x00000040 // If set to ‘1’ the DMA output - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ - 0x00000020 // If set to ‘1’ the DMA input - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_SYSSTATUS register. -// -//****************************************************************************** -#define DES_SYSSTATUS_RESETDONE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IRQSTATUS register. -// -//****************************************************************************** -#define DES_IRQSTATUS_DATA_OUT \ - 0x00000004 // This bit indicates data output - // interrupt is active and triggers - // the interrupt output. - -#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input - // interrupt is active and triggers - // the interrupt output. -#define DES_IRQSTATUS_CONTEX_IN \ - 0x00000001 // This bit indicates context - // interrupt is active and triggers - // the interrupt output. - -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IRQENABLE register. -// -//****************************************************************************** -#define DES_IRQENABLE_M_DATA_OUT \ - 0x00000004 // If this bit is set to ‘1’ the - // secure data output interrupt is - // enabled. - -#define DES_IRQENABLE_M_DATA_IN \ - 0x00000002 // If this bit is set to ‘1’ the - // secure data input interrupt is - // enabled. - -#define DES_IRQENABLE_M_CONTEX_IN \ - 0x00000001 // If this bit is set to ‘1’ the - // secure context interrupt is - // enabled. - - - - -#endif // __HW_DES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_dthe.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_dthe.h deleted file mode 100755 index fa5d39450aa..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_dthe.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** - -#ifndef __HW_DTHE_H__ -#define __HW_DTHE_H__ - -//***************************************************************************** -// -// The following are defines for the DTHE register offsets. -// -//***************************************************************************** -#define DTHE_O_SHA_IM 0x00000810 -#define DTHE_O_SHA_RIS 0x00000814 -#define DTHE_O_SHA_MIS 0x00000818 -#define DTHE_O_SHA_IC 0x0000081C -#define DTHE_O_AES_IM 0x00000820 -#define DTHE_O_AES_RIS 0x00000824 -#define DTHE_O_AES_MIS 0x00000828 -#define DTHE_O_AES_IC 0x0000082C -#define DTHE_O_DES_IM 0x00000830 -#define DTHE_O_DES_RIS 0x00000834 -#define DTHE_O_DES_MIS 0x00000838 -#define DTHE_O_DES_IC 0x0000083C -#define DTHE_O_EIP_CGCFG 0x00000A00 -#define DTHE_O_EIP_CGREQ 0x00000A04 -#define DTHE_O_CRC_CTRL 0x00000C00 -#define DTHE_O_CRC_SEED 0x00000C10 -#define DTHE_O_CRC_DIN 0x00000C14 -#define DTHE_O_CRC_RSLT_PP 0x00000C18 -#define DTHE_O_RAND_KEY0 0x00000F00 -#define DTHE_O_RAND_KEY1 0x00000F04 -#define DTHE_O_RAND_KEY2 0x00000F08 -#define DTHE_O_RAND_KEY3 0x00000F0C - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_SHAMD5_IMST register. -// -//****************************************************************************** -#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is - // raised when DMA writes last word - // of input data to internal FIFO of - // the engine -#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is - // raised when DMA complets the - // output context movement from - // internal register -#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is - // raised when DMA complets Context - // write to internal register -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_SHAMD5_IRIS register. -// -//****************************************************************************** -#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done -#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done -#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_SHAMD5_IMIS register. -// -//****************************************************************************** -#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done -#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done -#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_SHAMD5_ICIS register. -// -//****************************************************************************** -#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done�? - // flag -#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done�? flag -#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done�? flag -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_AES_IMST register. -// -//****************************************************************************** -#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is - // raised when DMA finishes writing - // last word of the process result -#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is - // raised when DMA writes last word - // of input data to internal FIFO of - // the engine -#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is - // raised when DMA complets the - // output context movement from - // internal register -#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is - // raised when DMA complets Context - // write to internal register -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_AES_IRIS register. -// -//****************************************************************************** -#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done -#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done -#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done -#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_AES_IMIS register. -// -//****************************************************************************** -#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done -#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done -#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done -#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_AES_ICIS register. -// -//****************************************************************************** -#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement - // done�? flag -#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done�? - // flag -#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done�? flag -#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done�? flag -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_DES_IMST register. -// -//****************************************************************************** -#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is - // raised when DMA finishes writing - // last word of the process result -#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is - // raised when DMA writes last word - // of input data to internal FIFO of - // the engine -#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is - // raised when DMA complets Context - // write to internal register -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_DES_IRIS register. -// -//****************************************************************************** -#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done -#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done -#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_DES_IMIS register. -// -//****************************************************************************** -#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done -#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done -#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_DES_ICIS register. -// -//****************************************************************************** -#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement - // done�? flag -#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done�? - // flag -#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done�? flag -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_EIP_CGCFG register. -// -//****************************************************************************** -#define DTHE_EIP_CGCFG_EIP29_CFG \ - 0x00000010 // Clock gating protocol setting - // for EIP29T. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -#define DTHE_EIP_CGCFG_EIP75_CFG \ - 0x00000008 // Clock gating protocol setting - // for EIP75T. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -#define DTHE_EIP_CGCFG_EIP16_CFG \ - 0x00000004 // Clock gating protocol setting - // for DES. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -#define DTHE_EIP_CGCFG_EIP36_CFG \ - 0x00000002 // Clock gating protocol setting - // for AES. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -#define DTHE_EIP_CGCFG_EIP57_CFG \ - 0x00000001 // Clock gating protocol setting - // for SHAMD5. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_EIP_CGREQ register. -// -//****************************************************************************** -#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5�? write “1�? to lower - // bits [4:0] will set the bit. - // Write “0�? will be ignored When - // “0x2�? write “1�? to lower bit - // [4:0] will clear the bit. Write - // “0�? will be ignored for other key - // value, regular read write - // operation -#define DTHE_EIP_CGREQ_Key_S 28 -#define DTHE_EIP_CGREQ_EIP29_REQ \ - 0x00000010 // 0 – request clock gating 1 – - // request to un-gate the clock. - -#define DTHE_EIP_CGREQ_EIP75_REQ \ - 0x00000008 // 0 – request clock gating 1 – - // request to un-gate the clock. - -#define DTHE_EIP_CGREQ_EIP16_REQ \ - 0x00000004 // 0 – request clock gating 1 – - // request to un-gate the clock. - -#define DTHE_EIP_CGREQ_EIP36_REQ \ - 0x00000002 // 0 – request clock gating 1 – - // request to un-gate the clock. - -#define DTHE_EIP_CGREQ_EIP57_REQ \ - 0x00000001 // 0 – request clock gating 1 – - // request to un-gate the clock. - -//****************************************************************************** -// -// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register. -// -//****************************************************************************** -#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED - // register context as starting - // value 10 – all “zero�? 11 – all - // “one�? This is self clearing. With - // first write to data register this - // value clears to zero and remain - // zero for rest of the operation - // unless written again -#define DTHE_CRC_CTRL_INIT_S 13 -#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8 - // bit -#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result - // before storing to CRC_RSLT_PP0 -#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result - // byte before storing to - // CRC_RSLT_PP0. applicable for all - // bytes in word -#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For - // all bytes in word -#define DTHE_CRC_CTRL_ENDIAN_M \ - 0x00000030 // Endian control [0] – swap byte - // in half-word [1] – swap half word - -#define DTHE_CRC_CTRL_ENDIAN_S 4 -#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 – - // polynomial 0x8005 0001 – - // polynomial 0x1021 0010 – - // polynomial 0x4C11DB7 0011 – - // polynomial 0x1EDC6F41 1000 – TCP - // checksum TYPE in DTHE_S_CRC_CTRL - // & DTHE_S_CRC_CTRL should be - // exclusive -#define DTHE_CRC_CTRL_TYPE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DTHE_O_CRC_SEED register. -// -//****************************************************************************** -#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and - // checksum operation. Please see - // CTRL register for more detail. - // This resister also holds the - // latest result of CRC or checksum - // operation -#define DTHE_CRC_SEED_SEED_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DTHE_O_CRC_DIN register. -// -//****************************************************************************** -#define DTHE_CRC_DIN_DATA_IN_M \ - 0xFFFFFFFF // Input data for CRC or checksum - // operation - -#define DTHE_CRC_DIN_DATA_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_CRC_RSLT_PP register. -// -//****************************************************************************** -#define DTHE_CRC_RSLT_PP_RSLT_PP_M \ - 0xFFFFFFFF // Input data for CRC or checksum - // operation - -#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_RAND_KEY0 register. -// -//****************************************************************************** -#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key - // [31:0] -#define DTHE_RAND_KEY0_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_RAND_KEY1 register. -// -//****************************************************************************** -#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key - // [63:32] -#define DTHE_RAND_KEY1_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_RAND_KEY2 register. -// -//****************************************************************************** -#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key - // [95:34] -#define DTHE_RAND_KEY2_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_RAND_KEY3 register. -// -//****************************************************************************** -#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key - // [127:96] -#define DTHE_RAND_KEY3_KEY_S 0 - - - -#endif // __HW_DTHE_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_flash_ctrl.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_flash_ctrl.h deleted file mode 100755 index ba68c123949..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_flash_ctrl.h +++ /dev/null @@ -1,1860 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_FLASH_CTRL_H__ -#define __HW_FLASH_CTRL_H__ - -//***************************************************************************** -// -// The following are defines for the FLASH_CTRL register offsets. -// -//***************************************************************************** -#define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA) - // offset 0x000 During a write - // operation this register contains - // a 4-byte-aligned address and - // specifies where the data is - // written. During erase operations - // this register contains a 1 - // KB-aligned CPU byte address and - // specifies which block is erased. - // Note that the alignment - // requirements must be met by - // software or the results of the - // operation are unpredictable. -#define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset - // 0x004 This register contains the - // data to be written during the - // programming cycle or read during - // the read cycle. Note that the - // contents of this register are - // undefined for a read access of an - // execute-only block. This register - // is not used during erase cycles. -#define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC) - // offset 0x008 When this register - // is written the Flash memory - // controller initiates the - // appropriate access cycle for the - // location specified by the Flash - // Memory Address (FMA) register . - // If the access is a write access - // the data contained in the Flash - // Memory Data (FMD) register is - // written to the specified address. - // This register must be the final - // register written and initiates - // the memory operation. The four - // control bits in the lower byte of - // this register are used to - // initiate memory operations. -#define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt - // Status (FCRIS) offset 0x00C This - // register indicates that the Flash - // memory controller has an - // interrupt condition. An interrupt - // is sent to the interrupt - // controller only if the - // corresponding FCIM register bit - // is set. -#define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask - // (FCIM) offset 0x010 This register - // controls whether the Flash memory - // controller generates interrupts - // to the controller. -#define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked - // Interrupt Status and Clear - // (FCMISC) offset 0x014 This - // register provides two functions. - // First it reports the cause of an - // interrupt by indicating which - // interrupt source or sources are - // signalling the interrupt. Second - // it serves as the method to clear - // the interrupt reporting. -#define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2) - // offset 0x020 When this register - // is written the Flash memory - // controller initiates the - // appropriate access cycle for the - // location specified by the Flash - // Memory Address (FMA) register . - // If the access is a write access - // the data contained in the Flash - // Write Buffer (FWB) registers is - // written. This register must be - // the final register written as it - // initiates the memory operation. -#define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid - // (FWBVAL) offset 0x030 This - // register provides a bitwise - // status of which FWBn registers - // have been written by the - // processor since the last write of - // the Flash memory write buffer. - // The entries with a 1 are written - // on the next write of the Flash - // memory write buffer. This - // register is cleared after the - // write operation by hardware. A - // protection violation on the write - // operation also clears this - // status. Software can program the - // same 32 words to various Flash - // memory locations by setting the - // FWB[n] bits after they are - // cleared by the write operation. - // The next write operation then - // uses the same data as the - // previous one. In addition if a - // FWBn register change should not - // be written to Flash memory - // software can clear the - // corresponding FWB[n] bit to - // preserve the existing data when - // the next write operation occurs. -#define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0 - // This register indicates the size - // of the on-chip Flash memory. - // Important: This register should - // be used to determine the size of - // the Flash memory that is - // implemented on this - // microcontroller. However to - // support legacy software the DC0 - // register is available. A read of - // the DC0 register correctly - // identifies legacy memory sizes. - // Software must use the FSIZE - // register for memory sizes that - // are not listed in the DC0 - // register description. -#define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4 - // This register indicates the size - // of the on-chip SRAM. Important: - // This register should be used to - // determine the size of the SRAM - // that is implemented on this - // microcontroller. However to - // support legacy software the DC0 - // register is available. A read of - // the DC0 register correctly - // identifies legacy memory sizes. - // Software must use the SSIZE - // register for memory sizes that - // are not listed in the DC0 - // register description. - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FMA register. -// -//****************************************************************************** -#define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in - // Flash memory where operation is - // performed except for nonvolatile - // registers -#define FLASH_CTRL_FMA_OFFSET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FMD register. -// -//****************************************************************************** -#define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write - // operation. -#define FLASH_CTRL_FMD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FMC register. -// -//****************************************************************************** -#define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This - // field contains a write key which - // is used to minimize the incidence - // of accidental Flash memory - // writes. The value 0xA442 must be - // written into this field for a - // Flash memory write to occur. - // Writes to the FMC register - // without this WRKEY value are - // ignored. A read of this field - // returns the value 0. -#define FLASH_CTRL_FMC_WRKEY_S 16 -#define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit - // is used to commit writes to - // Flash-memory-resident registers - // and to monitor the progress of - // that process. Value Description 1 - // Set this bit to commit (write) - // the register value to a - // Flash-memory-resident register. - // When read a 1 indicates that the - // previous commit access is not - // complete. 0 A write of 0 has no - // effect on the state of this bit. - // When read a 0 indicates that the - // previous commit access is - // complete. -#define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit - // is used to mass erase the Flash - // main memory and to monitor the - // progress of that process. Value - // Description 1 Set this bit to - // erase the Flash main memory. When - // read a 1 indicates that the - // previous mass erase access is not - // complete. 0 A write of 0 has no - // effect on the state of this bit. - // When read a 0 indicates that the - // previous mass erase access is - // complete. -#define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory - // This bit is used to erase a page - // of Flash memory and to monitor - // the progress of that process. - // Value Description 1 Set this bit - // to erase the Flash memory page - // specified by the contents of the - // FMA register. When read a 1 - // indicates that the previous page - // erase access is not complete. 0 A - // write of 0 has no effect on the - // state of this bit. When read a 0 - // indicates that the previous page - // erase access is complete. -#define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory - // This bit is used to write a word - // into Flash memory and to monitor - // the progress of that process. - // Value Description 1 Set this bit - // to write the data stored in the - // FMD register into the Flash - // memory location specified by the - // contents of the FMA register. - // When read a 1 indicates that the - // write update access is not - // complete. 0 A write of 0 has no - // effect on the state of this bit. - // When read a 0 indicates that the - // previous write update access is - // complete. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FCRIS register. -// -//****************************************************************************** -#define FLASH_CTRL_FCRIS_PROGRIS \ - 0x00002000 // Program Verify Error Raw - // Interrupt Status Value - // Description 1 An interrupt is - // pending because the verify of a - // PROGRAM operation failed. 0 An - // interrupt has not occurred. This - // bit is cleared by writing a 1 to - // the PROGMISC bit in the FCMISC - // register. - -#define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt - // Status Value Description 1 An - // interrupt is pending because the - // verify of an ERASE operation - // failed. 0 An interrupt has not - // occurred. This bit is cleared by - // writing a 1 to the ERMISC bit in - // the FCMISC register. -#define FLASH_CTRL_FCRIS_INVDRIS \ - 0x00000400 // Invalid Data Raw Interrupt - // Status Value Description 1 An - // interrupt is pending because a - // bit that was previously - // programmed as a 0 is now being - // requested to be programmed as a - // 1. 0 An interrupt has not - // occurred. This bit is cleared by - // writing a 1 to the INVMISC bit in - // the FCMISC register. - -#define FLASH_CTRL_FCRIS_VOLTRIS \ - 0x00000200 // Pump Voltage Raw Interrupt - // Status Value Description 1 An - // interrupt is pending because the - // regulated voltage of the pump - // went out of spec during the Flash - // operation and the operation was - // terminated. 0 An interrupt has - // not occurred. This bit is cleared - // by writing a 1 to the VOLTMISC - // bit in the FCMISC register. - -#define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This - // bit provides status EEPROM - // operation. Value Description 1 An - // EEPROM interrupt has occurred. 0 - // An EEPROM interrupt has not - // occurred. This bit is cleared by - // writing a 1 to the EMISC bit in - // the FCMISC register. -#define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status - // This bit provides status on - // programming cycles which are - // write or erase actions generated - // through the FMC or FMC2 register - // bits (see page 537 and page 549). - // Value Description 1 The - // programming or erase cycle has - // completed. 0 The programming or - // erase cycle has not completed. - // This status is sent to the - // interrupt controller when the - // PMASK bit in the FCIM register is - // set. This bit is cleared by - // writing a 1 to the PMISC bit in - // the FCMISC register. -#define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status - // Value Description 1 A program or - // erase action was attempted on a - // block of Flash memory that - // contradicts the protection policy - // for that block as set in the - // FMPPEn registers. 0 No access has - // tried to improperly program or - // erase the Flash memory. This - // status is sent to the interrupt - // controller when the AMASK bit in - // the FCIM register is set. This - // bit is cleared by writing a 1 to - // the AMISC bit in the FCMISC - // register. -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register. -// -//****************************************************************************** -#define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask - // Value Description 1 An interrupt - // is sent to the interrupt - // controller when the ILLARIS bit - // is set. 0 The ILLARIS interrupt - // is suppressed and not sent to the - // interrupt controller. -#define FLASH_CTRL_FCIM_PROGMASK \ - 0x00002000 // PROGVER Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the PROGRIS bit is set. 0 - // The PROGRIS interrupt is - // suppressed and not sent to the - // interrupt controller. - -#define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the PRERIS bit is set. 0 The - // PRERIS interrupt is suppressed - // and not sent to the interrupt - // controller. -#define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the ERRIS bit is set. 0 The - // ERRIS interrupt is suppressed and - // not sent to the interrupt - // controller. -#define FLASH_CTRL_FCIM_INVDMASK \ - 0x00000400 // Invalid Data Interrupt Mask - // Value Description 1 An interrupt - // is sent to the interrupt - // controller when the INVDRIS bit - // is set. 0 The INVDRIS interrupt - // is suppressed and not sent to the - // interrupt controller. - -#define FLASH_CTRL_FCIM_VOLTMASK \ - 0x00000200 // VOLT Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the VOLTRIS bit is set. 0 - // The VOLTRIS interrupt is - // suppressed and not sent to the - // interrupt controller. - -#define FLASH_CTRL_FCIM_LOCKMASK \ - 0x00000100 // LOCK Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the LOCKRIS bit is set. 0 - // The LOCKRIS interrupt is - // suppressed and not sent to the - // interrupt controller. - -#define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the ERIS bit is set. 0 The - // ERIS interrupt is suppressed and - // not sent to the interrupt - // controller. -#define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This - // bit controls the reporting of the - // programming raw interrupt status - // to the interrupt controller. - // Value Description 1 An interrupt - // is sent to the interrupt - // controller when the PRIS bit is - // set. 0 The PRIS interrupt is - // suppressed and not sent to the - // interrupt controller. -#define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit - // controls the reporting of the - // access raw interrupt status to - // the interrupt controller. Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the ARIS bit is set. 0 The - // ARIS interrupt is suppressed and - // not sent to the interrupt - // controller. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FCMISC register. -// -//****************************************************************************** -#define FLASH_CTRL_FCMISC_ILLMISC \ - 0x00004000 // Illegal Address Masked Interrupt - // Status and Clear Value - // Description 1 When read a 1 - // indicates that an unmasked - // interrupt was signaled. Writing a - // 1 to this bit clears ILLAMISC and - // also the ILLARIS bit in the FCRIS - // register (see page 540). 0 When - // read a 0 indicates that an - // interrupt has not occurred. A - // write of 0 has no effect on the - // state of this bit. - -#define FLASH_CTRL_FCMISC_PROGMISC \ - 0x00002000 // PROGVER Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // PROGMISC and also the PROGRIS bit - // in the FCRIS register (see page - // 540). 0 When read a 0 indicates - // that an interrupt has not - // occurred. A write of 0 has no - // effect on the state of this bit. - -#define FLASH_CTRL_FCMISC_PREMISC \ - 0x00001000 // PREVER Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // PREMISC and also the PRERIS bit - // in the FCRIS register . 0 When - // read a 0 indicates that an - // interrupt has not occurred. A - // write of 0 has no effect on the - // state of this bit. - -#define FLASH_CTRL_FCMISC_ERMISC \ - 0x00000800 // ERVER Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // ERMISC and also the ERRIS bit in - // the FCRIS register 0 When read a - // 0 indicates that an interrupt has - // not occurred. A write of 0 has no - // effect on the state of this bit. - -#define FLASH_CTRL_FCMISC_INVDMISC \ - 0x00000400 // Invalid Data Masked Interrupt - // Status and Clear Value - // Description 1 When read a 1 - // indicates that an unmasked - // interrupt was signaled. Writing a - // 1 to this bit clears INVDMISC and - // also the INVDRIS bit in the FCRIS - // register (see page 540). 0 When - // read a 0 indicates that an - // interrupt has not occurred. A - // write of 0 has no effect on the - // state of this bit. - -#define FLASH_CTRL_FCMISC_VOLTMISC \ - 0x00000200 // VOLT Masked Interrupt Status and - // Clear Value Description 1 When - // read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // VOLTMISC and also the VOLTRIS bit - // in the FCRIS register (see page - // 540). 0 When read a 0 indicates - // that an interrupt has not - // occurred. A write of 0 has no - // effect on the state of this bit. - -#define FLASH_CTRL_FCMISC_LOCKMISC \ - 0x00000100 // LOCK Masked Interrupt Status and - // Clear Value Description 1 When - // read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // LOCKMISC and also the LOCKRIS bit - // in the FCRIS register (see page - // 540). 0 When read a 0 indicates - // that an interrupt has not - // occurred. A write of 0 has no - // effect on the state of this bit. - -#define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // EMISC and also the ERIS bit in - // the FCRIS register 0 When read a - // 0 indicates that an interrupt has - // not occurred. A write of 0 has no - // effect on the state of this bit. -#define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt - // Status and Clear Value - // Description 1 When read a 1 - // indicates that an unmasked - // interrupt was signaled because a - // programming cycle completed. - // Writing a 1 to this bit clears - // PMISC and also the PRIS bit in - // the FCRIS register 0 When read a - // 0 indicates that a programming - // cycle complete interrupt has not - // occurred. A write of 0 has no - // effect on the state of this bit. -#define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled - // because a program or erase action - // was attempted on a block of Flash - // memory that contradicts the - // protection policy for that block - // as set in the FMPPEn registers. - // Writing a 1 to this bit clears - // AMISC and also the ARIS bit in - // the FCRIS register 0 When read a - // 0 indicates that no improper - // accesses have occurred. A write - // of 0 has no effect on the state - // of this bit. -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register. -// -//****************************************************************************** -#define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This - // field contains a write key which - // is used to minimize the incidence - // of accidental Flash memory - // writes. The value 0xA442 must be - // written into this field for a - // write to occur. Writes to the - // FMC2 register without this WRKEY - // value are ignored. A read of this - // field returns the value 0. -#define FLASH_CTRL_FMC2_WRKEY_S 16 -#define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This - // bit is used to start a buffered - // write to Flash memory. Value - // Description 1 Set this bit to - // write the data stored in the FWBn - // registers to the location - // specified by the contents of the - // FMA register. When read a 1 - // indicates that the previous - // buffered Flash memory write - // access is not complete. 0 A write - // of 0 has no effect on the state - // of this bit. When read a 0 - // indicates that the previous - // buffered Flash memory write - // access is complete. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWBVAL register. -// -//****************************************************************************** -#define FLASH_CTRL_FWBVAL_FWBN_M \ - 0xFFFFFFFF // Flash Memory Write Buffer Value - // Description 1 The corresponding - // FWBn register has been updated - // since the last buffer write - // operation and is ready to be - // written to Flash memory. 0 The - // corresponding FWBn register has - // no new data to be written. Bit 0 - // corresponds to FWB0 offset 0x100 - // and bit 31 corresponds to FWB31 - // offset 0x13C. - -#define FLASH_CTRL_FWBVAL_FWBN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB1_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB2_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB3_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB4_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB5_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB6_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB7_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB8_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB9_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB10 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB10_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB11 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB11_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB12 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB12_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB13 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB13_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB14 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB14_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB15 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB15_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB16 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB16_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB17 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB17_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB18 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB18_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB19 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB19_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB20 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB20_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB21 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB21_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB22 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB22_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB23 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB23_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB24 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB24_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB25 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB25_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB26 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB26_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB27 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB27_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB28 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB28_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB29 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB29_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB30 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB30_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB31 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB31_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB32 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB32_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FSIZE register. -// -//****************************************************************************** -#define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of - // the on-chip Flash memory. Value - // Description 0x0003 8 KB of Flash - // 0x0007 16 KB of Flash 0x000F 32 - // KB of Flash 0x001F 64 KB of Flash - // 0x002F 96 KB of Flash 0x003F 128 - // KB of Flash 0x005F 192 KB of - // Flash 0x007F 256 KB of Flash -#define FLASH_CTRL_FSIZE_SIZE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_SSIZE register. -// -//****************************************************************************** -#define FLASH_CTRL_SSIZE_SRAM_SIZE_M \ - 0x0000FFFF // SRAM Size Indicates the size of - // the on-chip SRAM. Value - // Description 0x0007 2 KB of SRAM - // 0x000F 4 KB of SRAM 0x0017 6 KB - // of SRAM 0x001F 8 KB of SRAM - // 0x002F 12 KB of SRAM 0x003F 16 KB - // of SRAM 0x004F 20 KB of SRAM - // 0x005F 24 KB of SRAM 0x007F 32 KB - // of SRAM - -#define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0 -#define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key -#define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1 -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read - // Enable 0 -#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read - // Enable 1 -#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read - // Enable 2 -#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read - // Enable 3 -#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read - // Enable 4 -#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read - // Enable 5 -#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read - // Enable 6 -#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read - // Enable 7 -#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read - // Enable 8 -#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read - // Enable 9 -#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read - // Enable 10 -#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read - // Enable 11 -#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read - // Enable 12 -#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read - // Enable 13 -#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read - // Enable 14 -#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read - // Enable 15 - -#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program - // Enable 0 -#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program - // Enable 1 -#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program - // Enable 2 -#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program - // Enable 3 -#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program - // Enable 4 -#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program - // Enable 5 -#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program - // Enable 6 -#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program - // Enable 7 -#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program - // Enable 8 -#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program - // Enable 9 -#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program - // Enable 10 -#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program - // Enable 11 -#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program - // Enable 12 -#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program - // Enable 13 -#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program - // Enable 14 -#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program - // Enable 15 - -#define FLASH_USECRL 0x400FE140 // USec Reload -#define FLASH_CTRL_ERASE_SIZE 0x00000400 - - -#endif // __HW_FLASH_CTRL_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gpio.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gpio.h deleted file mode 100755 index 118e24704d5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gpio.h +++ /dev/null @@ -1,1347 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// The following are defines for the GPIO register offsets. -// -//***************************************************************************** -#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000 - // 7000 0x4002 4000 GPIO Data - // (GPIODATA)@@ offset 0x000 The - // GPIODATA register is the data - // register. In software control - // mode@@ values written in the - // GPIODATA register are transferred - // onto the GPIO port pins if the - // respective pins have been - // configured as outputs through the - // GPIO Direction (GPIODIR) register - // (see page 653). In order to write - // to GPIODATA@@ the corresponding - // bits in the mask@@ resulting from - // the address bus bits [9:2]@@ must - // be set. Otherwise@@ the bit - // values remain unchanged by the - // write. Similarly@@ the values - // read from this register are - // determined for each bit by the - // mask bit derived from the address - // used to access the data - // register@@ bits [9:2]. Bits that - // are set in the address mask cause - // the corresponding bits in - // GPIODATA to be read@@ and bits - // that are clear in the address - // mask cause the corresponding bits - // in GPIODATA to be read as 0@@ - // regardless of their value. A read - // from GPIODATA returns the last - // bit value written if the - // respective pins are configured as - // outputs@@ or it returns the value - // on the corresponding input pin - // when these are configured as - // inputs. All bits are cleared by a - // reset. -#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000 - // 7400 0x4002 4400 GPIO Direction - // (GPIODIR)@@ offset 0x400 The - // GPIODIR register is the data - // direction register. Setting a bit - // in the GPIODIR register - // configures the corresponding pin - // to be an output@@ while clearing - // a bit configures the - // corresponding pin to be an input. - // All bits are cleared by a reset@@ - // meaning all GPIO pins are inputs - // by default. -#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000 - // 7404 0x4002 4404 GPIO Interrupt - // Sense (GPIOIS)@@ offset 0x404 The - // GPIOIS register is the interrupt - // sense register. Setting a bit in - // the GPIOIS register configures - // the corresponding pin to detect - // levels@@ while clearing a bit - // configures the corresponding pin - // to detect edges. All bits are - // cleared by a reset. -#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000 - // 7408 0x4002 4408 GPIO Interrupt - // Both Edges (GPIOIBE)@@ offset - // 0x408 The GPIOIBE register allows - // both edges to cause interrupts. - // When the corresponding bit in the - // GPIO Interrupt Sense (GPIOIS) - // register is set to detect edges@@ - // setting a bit in the GPIOIBE - // register configures the - // corresponding pin to detect both - // rising and falling edges@@ - // regardless of the corresponding - // bit in the GPIO Interrupt Event - // (GPIOIEV) register . Clearing a - // bit configures the pin to be - // controlled by the GPIOIEV - // register. All bits are cleared by - // a reset. -#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000 - // 740C 0x4002 440C GPIO Interrupt - // Event (GPIOIEV)@@ offset 0x40C - // The GPIOIEV register is the - // interrupt event register. Setting - // a bit in the GPIOIEV register - // configures the corresponding pin - // to detect rising edges or high - // levels@@ depending on the - // corresponding bit value in the - // GPIO Interrupt Sense (GPIOIS) - // register . Clearing a bit - // configures the pin to detect - // falling edges or low levels@@ - // depending on the corresponding - // bit value in the GPIOIS register. - // All bits are cleared by a reset. -#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000 - // 7410 0x4002 4410 GPIO Interrupt - // Mask (GPIOIM)@@ offset 0x410 The - // GPIOIM register is the interrupt - // mask register. Setting a bit in - // the GPIOIM register allows - // interrupts that are generated by - // the corresponding pin to be sent - // to the interrupt controller on - // the combined interrupt signal. - // Clearing a bit prevents an - // interrupt on the corresponding - // pin from being sent to the - // interrupt controller. All bits - // are cleared by a reset. -#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000 - // 7414 0x4002 4414 GPIO Raw - // Interrupt Status (GPIORIS)@@ - // offset 0x414 The GPIORIS register - // is the raw interrupt status - // register. A bit in this register - // is set when an interrupt - // condition occurs on the - // corresponding GPIO pin. If the - // corresponding bit in the GPIO - // Interrupt Mask (GPIOIM) register - // is set@@ the interrupt is sent to - // the interrupt controller. Bits - // read as zero indicate that - // corresponding input pins have not - // initiated an interrupt. A bit in - // this register can be cleared by - // writing a 1 to the corresponding - // bit in the GPIO Interrupt Clear - // (GPIOICR) register. -#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000 - // 7418 0x4002 4418 GPIO Masked - // Interrupt Status (GPIOMIS)@@ - // offset 0x418 The GPIOMIS register - // is the masked interrupt status - // register. If a bit is set in this - // register@@ the corresponding - // interrupt has triggered an - // interrupt to the interrupt - // controller. If a bit is clear@@ - // either no interrupt has been - // generated@@ or the interrupt is - // masked. If no port pin@@ other - // than the one that is being used - // as an ADC trigger@@ is being used - // to generate interrupts@@ the - // appropriate Interrupt Set Enable - // (ENn) register can disable the - // interrupts for the port@@ and the - // ADC interrupt can be used to read - // back the converted data. - // Otherwise@@ the port interrupt - // handler must ignore and clear - // interrupts on the port pin and - // wait for the ADC interrupt@@ or - // the ADC interrupt must be - // disabled in the EN0 register and - // the port interrupt handler must - // poll the ADC registers until the - // conversion is completed. If no - // port pin@@ other than the one - // that is being used as an ADC - // trigger@@ is being used to - // generate interrupts@@ the - // appropriate Interrupt Set Enable - // (ENn) register can disable the - // interrupts for the port@@ and the - // ADC interrupt can be used to read - // back the converted data. - // Otherwise@@ the port interrupt - // handler must ignore and clear - // interrupts on the port pin and - // wait for the ADC interrupt@@ or - // the ADC interrupt must be - // disabled in the EN0 register and - // the port interrupt handler must - // poll the ADC registers until the - // conversion is completed. Note - // that if the Port B GPIOADCCTL - // register is cleared@@ PB4 can - // still be used as an external - // trigger for the ADC. This is a - // legacy mode which allows code - // written for previous Stellaris - // devices to operate on this - // microcontroller. GPIOMIS is the - // state of the interrupt after - // masking. -#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000 - // 741C 0x4002 441C GPIO Interrupt - // Clear (GPIOICR)@@ offset 0x41C - // The GPIOICR register is the - // interrupt clear register. Writing - // a 1 to a bit in this register - // clears the corresponding - // interrupt bit in the GPIORIS and - // GPIOMIS registers. Writing a 0 - // has no effect. -#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000 - // 7420 0x4002 4420 GPIO Alternate - // Function Select (GPIOAFSEL)@@ - // offset 0x420 The GPIOAFSEL - // register is the mode control - // select register. If a bit is - // clear@@ the pin is used as a GPIO - // and is controlled by the GPIO - // registers. Setting a bit in this - // register configures the - // corresponding GPIO line to be - // controlled by an associated - // peripheral. Several possible - // peripheral functions are - // multiplexed on each GPIO. The - // GPIO Port Control (GPIOPCTL) - // register is used to select one of - // the possible functions. -#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000 - // 7500 0x4002 4500 GPIO 2-mA Drive - // Select (GPIODR2R)@@ offset 0x500 - // The GPIODR2R register is the 2-mA - // drive control register. Each GPIO - // signal in the port can be - // individually configured without - // affecting the other pads. When - // setting the DRV2 bit for a GPIO - // signal@@ the corresponding DRV4 - // bit in the GPIODR4R register and - // DRV8 bit in the GPIODR8R register - // are automatically cleared by - // hardware. By default@@ all GPIO - // pins have 2-mA drive. -#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000 - // 7504 0x4002 4504 GPIO 4-mA Drive - // Select (GPIODR4R)@@ offset 0x504 - // The GPIODR4R register is the 4-mA - // drive control register. Each GPIO - // signal in the port can be - // individually configured without - // affecting the other pads. When - // setting the DRV4 bit for a GPIO - // signal@@ the corresponding DRV2 - // bit in the GPIODR2R register and - // DRV8 bit in the GPIODR8R register - // are automatically cleared by - // hardware. -#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000 - // 7508 0x4002 4508 GPIO 8-mA Drive - // Select (GPIODR8R)@@ offset 0x508 - // The GPIODR8R register is the 8-mA - // drive control register. Each GPIO - // signal in the port can be - // individually configured without - // affecting the other pads. When - // setting the DRV8 bit for a GPIO - // signal@@ the corresponding DRV2 - // bit in the GPIODR2R register and - // DRV4 bit in the GPIODR4R register - // are automatically cleared by - // hardware. The 8-mA setting is - // also used for high-current - // operation. Note: There is no - // configuration difference between - // 8-mA and high-current operation. - // The additional current capacity - // results from a shift in the - // VOH/VOL levels. -#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000 - // 750C 0x4002 450C GPIO Open Drain - // Select (GPIOODR)@@ offset 0x50C - // The GPIOODR register is the open - // drain control register. Setting a - // bit in this register enables the - // open-drain configuration of the - // corresponding GPIO pad. When - // open-drain mode is enabled@@ the - // corresponding bit should also be - // set in the GPIO Digital Input - // Enable (GPIODEN) register . - // Corresponding bits in the drive - // strength and slew rate control - // registers (GPIODR2R@@ GPIODR4R@@ - // GPIODR8R@@ and GPIOSLR) can be - // set to achieve the desired rise - // and fall times. The GPIO acts as - // an open-drain input if the - // corresponding bit in the GPIODIR - // register is cleared. If open - // drain is selected while the GPIO - // is configured as an input@@ the - // GPIO will remain an input and the - // open-drain selection has no - // effect until the GPIO is changed - // to an output. When using the I2C - // module@@ in addition to - // configuring the pin to open - // drain@@ the GPIO Alternate - // Function Select (GPIOAFSEL) - // register bits for the I2C clock - // and data pins should be set -#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000 - // 7510 0x4002 4510 GPIO Pull-Up - // Select (GPIOPUR)@@ offset 0x510 - // The GPIOPUR register is the - // pull-up control register. When a - // bit is set@@ a weak pull-up - // resistor on the corresponding - // GPIO signal is enabled. Setting a - // bit in GPIOPUR automatically - // clears the corresponding bit in - // the GPIO Pull-Down Select - // (GPIOPDR) register . Write access - // to this register is protected - // with the GPIOCR register. Bits in - // GPIOCR that are cleared prevent - // writes to the equivalent bit in - // this register. -#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000 - // 7514 0x4002 4514 GPIO Pull-Down - // Select (GPIOPDR)@@ offset 0x514 - // The GPIOPDR register is the - // pull-down control register. When - // a bit is set@@ a weak pull-down - // resistor on the corresponding - // GPIO signal is enabled. Setting a - // bit in GPIOPDR automatically - // clears the corresponding bit in - // the GPIO Pull-Up Select (GPIOPUR) - // register -#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000 - // 7518 0x4002 4518 The GPIOSLR - // register is the slew rate control - // register. Slew rate control is - // only available when using the - // 8-mA drive strength option via - // the GPIO 8-mA Drive Select - // (GPIODR8R) register -#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000 - // 751C 0x4002 451C GPIO Digital - // Enable (GPIODEN)@@ offset 0x51C - // Note: Pins configured as digital - // inputs are Schmitt-triggered. The - // GPIODEN register is the digital - // enable register. By default@@ all - // GPIO signals except those listed - // below are configured out of reset - // to be undriven (tristate). Their - // digital function is disabled; - // they do not drive a logic value - // on the pin and they do not allow - // the pin voltage into the GPIO - // receiver. To use the pin as a - // digital input or output (either - // GPIO or alternate function)@@ the - // corresponding GPIODEN bit must be - // set. -#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000 - // 7520 0x4002 4520 GPIO Lock - // (GPIOLOCK)@@ offset 0x520 The - // GPIOLOCK register enables write - // access to the GPIOCR register . - // Writing 0x4C4F.434B to the - // GPIOLOCK register unlocks the - // GPIOCR register. Writing any - // other value to the GPIOLOCK - // register re-enables the locked - // state. Reading the GPIOLOCK - // register returns the lock status - // rather than the 32-bit value that - // was previously written. - // Therefore@@ when write accesses - // are disabled@@ or locked@@ - // reading the GPIOLOCK register - // returns 0x0000.0001. When write - // accesses are enabled@@ or - // unlocked@@ reading the GPIOLOCK - // register returns 0x0000.0000. -#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000 - // 7524 0x4002 4524 GPIO Commit - // (GPIOCR)@@ offset 0x524 The - // GPIOCR register is the commit - // register. The value of the GPIOCR - // register determines which bits of - // the GPIOAFSEL@@ GPIOPUR@@ - // GPIOPDR@@ and GPIODEN registers - // are committed when a write to - // these registers is performed. If - // a bit in the GPIOCR register is - // cleared@@ the data being written - // to the corresponding bit in the - // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ - // or GPIODEN registers cannot be - // committed and retains its - // previous value. If a bit in the - // GPIOCR register is set@@ the data - // being written to the - // corresponding bit of the - // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ - // or GPIODEN registers is committed - // to the register and reflects the - // new value. The contents of the - // GPIOCR register can only be - // modified if the status in the - // GPIOLOCK register is unlocked. - // Writes to the GPIOCR register are - // ignored if the status in the - // GPIOLOCK register is locked. -#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000 - // 7528 0x4002 4528 The GPIOAMSEL - // register controls isolation - // circuits to the analog side of a - // unified I/O pad. Because the - // GPIOs may be driven by a 5-V - // source and affect analog - // operation@@ analog circuitry - // requires isolation from the pins - // when they are not used in their - // analog function. Each bit of this - // register controls the isolation - // circuitry for the corresponding - // GPIO signal. -#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) 0x4000 552C - // 0x4000 652C 0x4000 752C 0x4002 - // 452C GPIO Port Control - // (GPIOPCTL)@@ offset 0x52C The - // GPIOPCTL register is used in - // conjunction with the GPIOAFSEL - // register and selects the specific - // peripheral signal for each GPIO - // pin when using the alternate - // function mode. Most bits in the - // GPIOAFSEL register are cleared on - // reset@@ therefore most GPIO pins - // are configured as GPIOs by - // default. When a bit is set in the - // GPIOAFSEL register@@ the - // corresponding GPIO signal is - // controlled by an associated - // peripheral. The GPIOPCTL register - // selects one out of a set of - // peripheral functions for each - // GPIO@@ providing additional - // flexibility in signal definition. -#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in - // cc3xx. ADC trigger via GPIO is - // not supported. 0x4000 5530 0x4000 - // 6530 0x4000 7530 0x4002 4530 GPIO - // ADC Control (GPIOADCCTL)@@ offset - // 0x530 This register is used to - // configure a GPIO pin as a source - // for the ADC trigger. Note that if - // the Port B GPIOADCCTL register is - // cleared@@ PB4 can still be used - // as an external trigger for the - // ADC. This is a legacy mode which - // allows code written for previous - // Stellaris devices to operate on - // this microcontroller. -#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000 - // 7534 0x4002 4534 GPIO DMA Control - // (GPIODMACTL)@@ offset 0x534 This - // register is used to configure a - // GPIO pin as a source for the ?DMA - // trigger. -#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000 - // 7538 0x4002 4538 GPIO Select - // Interrupt (GPIOSI)@@ offset 0x538 - // This register is used to enable - // individual interrupts for each - // pin. Note: This register is only - // available on Port P and Port Q. -#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000 - // 7FD0 0x4002 4FD0 GPIO Peripheral - // Identification 4 - // (GPIOPeriphID4)@@ offset 0xFD0 - // The GPIOPeriphID4@@ - // GPIOPeriphID5@@ GPIOPeriphID6@@ - // and GPIOPeriphID7 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000 - // 7FD4 0x4002 4FD4 GPIO Peripheral - // Identification 5 - // (GPIOPeriphID5)@@ offset 0xFD4 - // The GPIOPeriphID4@@ - // GPIOPeriphID5@@ GPIOPeriphID6@@ - // and GPIOPeriphID7 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000 - // 7FD8 0x4002 4FD8 GPIO Peripheral - // Identification 6 - // (GPIOPeriphID6)@@ offset 0xFD8 - // The GPIOPeriphID4@@ - // GPIOPeriphID5@@ GPIOPeriphID6@@ - // and GPIOPeriphID7 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000 - // 7FDC 0x4002 4FDC GPIO Peripheral - // Identification 7 - // (GPIOPeriphID7)@@ offset 0xFDC - // The GPIOPeriphID4@@ - // GPIOPeriphID5@@ GPIOPeriphID6@@ - // and GPIOPeriphID7 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000 - // 7FE0 0x4002 4FE0 GPIO Peripheral - // Identification 0 - // (GPIOPeriphID0)@@ offset 0xFE0 - // The GPIOPeriphID0@@ - // GPIOPeriphID1@@ GPIOPeriphID2@@ - // and GPIOPeriphID3 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000 - // 7FE4 0x4002 4FE4 GPIO Peripheral - // Identification 1 - // (GPIOPeriphID1)@@ offset 0xFE4 - // The GPIOPeriphID0@@ - // GPIOPeriphID1@@ GPIOPeriphID2@@ - // and GPIOPeriphID3 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000 - // 7FE8 0x4002 4FE8 GPIO Peripheral - // Identification 2 - // (GPIOPeriphID2)@@ offset 0xFE8 - // The GPIOPeriphID0@@ - // GPIOPeriphID1@@ GPIOPeriphID2@@ - // and GPIOPeriphID3 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000 - // 7FEC 0x4002 4FEC GPIO Peripheral - // Identification 3 - // (GPIOPeriphID3)@@ offset 0xFEC - // The GPIOPeriphID0@@ - // GPIOPeriphID1@@ GPIOPeriphID2@@ - // and GPIOPeriphID3 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000 - // 7FF0 0x4002 4FF0 GPIO PrimeCell - // Identification 0 (GPIOPCellID0)@@ - // offset 0xFF0 The GPIOPCellID0@@ - // GPIOPCellID1@@ GPIOPCellID2@@ and - // GPIOPCellID3 registers are four - // 8-bit wide registers@@ that can - // conceptually be treated as one - // 32-bit register. The register is - // used as a standard - // cross-peripheral identification - // system. -#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000 - // 7FF4 0x4002 4FF4 GPIO PrimeCell - // Identification 1 (GPIOPCellID1)@@ - // offset 0xFF4 The GPIOPCellID0@@ - // GPIOPCellID1@@ GPIOPCellID2@@ and - // GPIOPCellID3 registers are four - // 8-bit wide registers@@ that can - // conceptually be treated as one - // 32-bit register. The register is - // used as a standard - // cross-peripheral identification - // system. -#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000 - // 7FF8 0x4002 4FF8 GPIO PrimeCell - // Identification 2 (GPIOPCellID2)@@ - // offset 0xFF8 The GPIOPCellID0@@ - // GPIOPCellID1@@ GPIOPCellID2@@ and - // GPIOPCellID3 registers are four - // 8-bit wide registers@@ that can - // conceptually be treated as one - // 32-bit register. The register is - // used as a standard - // cross-peripheral identification - // system. -#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000 - // 7FFC 0x4002 4FFC GPIO PrimeCell - // Identification 3 (GPIOPCellID3)@@ - // offset 0xFFC The GPIOPCellID0@@ - // GPIOPCellID1@@ GPIOPCellID2@@ and - // GPIOPCellID3 registers are four - // 8-bit wide registers@@ that can - // conceptually be treated as one - // 32-bit register. The register is - // used as a standard - // cross-peripheral identification - // system.0xb1 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register. -// -//****************************************************************************** -#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is - // virtually mapped to 256 locations - // in the address space. To - // facilitate the reading and - // writing of data to these - // registers by independent - // drivers@@ the data read from and - // written to the registers are - // masked by the eight address lines - // [9:2]. Reads from this register - // return its current state. Writes - // to this register only affect bits - // that are not masked by ADDR[9:2] - // and are configured as outputs. -#define GPIO_GPIO_DATA_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register. -// -//****************************************************************************** -#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value - // Description 0 Corresponding pin - // is an input. 1 Corresponding pins - // is an output. -#define GPIO_GPIO_DIR_DIR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_IS register. -// -//****************************************************************************** -#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value - // Description 0 The edge on the - // corresponding pin is detected - // (edge-sensitive). 1 The level on - // the corresponding pin is detected - // (level-sensitive). -#define GPIO_GPIO_IS_IS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register. -// -//****************************************************************************** -#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value - // Description 0 Interrupt - // generation is controlled by the - // GPIO Interrupt Event (GPIOIEV) - // register. 1 Both edges on the - // corresponding pin trigger an - // interrupt. -#define GPIO_GPIO_IBE_IBE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register. -// -//****************************************************************************** -#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value - // Description 1 A falling edge or a - // Low level on the corresponding - // pin triggers an interrupt. 0 A - // rising edge or a High level on - // the corresponding pin triggers an - // interrupt. -#define GPIO_GPIO_IEV_IEV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_IM register. -// -//****************************************************************************** -#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value - // Description 0 The interrupt from - // the corresponding pin is masked. - // 1 The interrupt from the - // corresponding pin is sent to the - // interrupt controller. -#define GPIO_GPIO_IM_IME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register. -// -//****************************************************************************** -#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value - // Description 1 An interrupt - // condition has occurred on the - // corresponding pin. 0 interrupt - // condition has not occurred on the - // corresponding pin. A bit is - // cleared by writing a 1 to the - // corresponding bit in the GPIOICR - // register. -#define GPIO_GPIO_RIS_RIS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register. -// -//****************************************************************************** -#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status - // Value Description 1 An interrupt - // condition on the corresponding - // pin has triggered an interrupt to - // the interrupt controller. 0 An - // interrupt condition on the - // corresponding pin is masked or - // has not occurred. A bit is - // cleared by writing a 1 to the - // corresponding bit in the GPIOICR - // register. -#define GPIO_GPIO_MIS_MIS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register. -// -//****************************************************************************** -#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value - // Description 1 The corresponding - // interrupt is cleared. 0 The - // corresponding interrupt is - // unaffected. -#define GPIO_GPIO_ICR_IC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register. -// -//****************************************************************************** -#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Output Pad - // 2-mA Drive Enable Value - // Description 1 The corresponding - // GPIO pin has 2-mA drive. The - // drive for the corresponding GPIO - // pin is controlled by the GPIODR4R - // or GPIODR8R register. 0 Setting a - // bit in either the GPIODR4 - // register or the GPIODR8 register - // clears the corresponding 2-mA - // enable bit. The change is - // effective on the second clock - // cycle after the write if - // accessing GPIO via the APB memory - // aperture. If using AHB access@@ - // the change is effective on the - // next clock cycle. -#define GPIO_GPIO_DR2R_DRV2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register. -// -//****************************************************************************** -#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Output Pad - // 4-mA Drive Enable Value - // Description 1 The corresponding - // GPIO pin has 4-mA drive. The - // drive for the corresponding GPIO - // pin is controlled by the GPIODR2R - // or GPIODR8R register. 0 Setting a - // bit in either the GPIODR2 - // register or the GPIODR8 register - // clears the corresponding 4-mA - // enable bit. The change is - // effective on the second clock - // cycle after the write if - // accessing GPIO via the APB memory - // aperture. If using AHB access@@ - // the change is effective on the - // next clock cycle. -#define GPIO_GPIO_DR4R_DRV4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register. -// -//****************************************************************************** -#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Output Pad - // 8-mA Drive Enable Value - // Description 1 The corresponding - // GPIO pin has 8-mA drive. The - // drive for the corresponding GPIO - // pin is controlled by the GPIODR2R - // or GPIODR4R register. 0 Setting a - // bit in either the GPIODR2 - // register or the GPIODR4 register - // clears the corresponding 8-mA - // enable bit. The change is - // effective on the second clock - // cycle after the write if - // accessing GPIO via the APB memory - // aperture. If using AHB access@@ - // the change is effective on the - // next clock cycle. -#define GPIO_GPIO_DR8R_DRV8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register. -// -//****************************************************************************** -#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Output Pad - // Open Drain Enable Value - // Description 1 The corresponding - // pin is configured as open drain. - // 0 The corresponding pin is not - // configured as open drain. -#define GPIO_GPIO_ODR_ODE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register. -// -//****************************************************************************** -#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Pad Weak - // Pull-Up Enable Value Description - // 1 The corresponding pin has a - // weak pull-up resistor. 0 The - // corresponding pin is not - // affected. Setting a bit in the - // GPIOPDR register clears the - // corresponding bit in the GPIOPUR - // register. The change is effective - // on the second clock cycle after - // the write if accessing GPIO via - // the APB memory aperture. If using - // AHB access@@ the change is - // effective on the next clock - // cycle. -#define GPIO_GPIO_PUR_PUE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register. -// -//****************************************************************************** -#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Pad Weak - // Pull-Down Enable Value - // Description 1 The corresponding - // pin has a weak pull-down - // resistor. 0 The corresponding pin - // is not affected. Setting a bit in - // the GPIOPUR register clears the - // corresponding bit in the GPIOPDR - // register. The change is effective - // on the second clock cycle after - // the write if accessing GPIO via - // the APB memory aperture. If using - // AHB access@@ the change is - // effective on the next clock - // cycle. -#define GPIO_GPIO_PDR_PDE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register. -// -//****************************************************************************** -#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Slew Rate - // Limit Enable (8-mA drive only) - // Value Description 1 Slew rate - // control is enabled for the - // corresponding pin. 0 Slew rate - // control is disabled for the - // corresponding pin. -#define GPIO_GPIO_SLR_SRL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register. -// -//****************************************************************************** -#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Digital Enable - // Value Description 0 The digital - // functions for the corresponding - // pin are disabled. 1 The digital - // functions for the corresponding - // pin are enabled. -#define GPIO_GPIO_DEN_DEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register. -// -//****************************************************************************** -#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in - // cc3xx. GPIO Lock A write of the - // value 0x4C4F.434B unlocks the - // GPIO Commit (GPIOCR) register for - // write access.A write of any other - // value or a write to the GPIOCR - // register reapplies the lock@@ - // preventing any register updates. - // A read of this register returns - // the following values: Value - // Description 0x1 The GPIOCR - // register is locked and may not be - // modified. 0x0 The GPIOCR register - // is unlocked and may be modified. -#define GPIO_GPIO_LOCK_LOCK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_CR register. -// -//****************************************************************************** -#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) GPIO Commit - // Value Description The - // corresponding GPIOAFSEL@@ - // GPIOPUR@@ GPIOPDR@@ or GPIODEN - // bits can be written. 1 The - // corresponding GPIOAFSEL@@ - // GPIOPUR@@ GPIOPDR@@ or GPIODEN - // bits cannot be written. 0 Note: - // The default register type for the - // GPIOCR register is RO for all - // GPIO pins with the exception of - // the NMI pin and the four JTAG/SWD - // pins (PD7@@ PF0@@ and PC[3:0]). - // These six pins are the only GPIOs - // that are protected by the GPIOCR - // register. Because of this@@ the - // register type for GPIO Port D7@@ - // GPIO Port F0@@ and GPIO Port - // C[3:0] is R/W. The default reset - // value for the GPIOCR register is - // 0x0000.00FF for all GPIO pins@@ - // with the exception of the NMI pin - // and the four JTAG/SWD pins (PD7@@ - // PF0@@ and PC[3:0]). To ensure - // that the JTAG port is not - // accidentally programmed as GPIO - // pins@@ the PC[3:0] pins default - // to non-committable. Similarly@@ - // to ensure that the NMI pin is not - // accidentally programmed as a GPIO - // pin@@ the PD7 and PF0 pins - // default to non-committable. - // Because of this@@ the default - // reset value of GPIOCR for GPIO - // Port C is 0x0000.00F0@@ for GPIO - // Port D is 0x0000.007F@@ and for - // GPIO Port F is 0x0000.00FE. -#define GPIO_GPIO_CR_CR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register. -// -//****************************************************************************** -#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \ - 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) GPIO Analog - // Mode Select Value Description 1 - // The analog function of the pin is - // enabled@@ the isolation is - // disabled@@ and the pin is capable - // of analog functions. 0 The analog - // function of the pin is disabled@@ - // the isolation is enabled@@ and - // the pin is capable of digital - // functions as specified by the - // other GPIO configuration - // registers. Note: This register - // and bits are only valid for GPIO - // signals that share analog - // function through a unified I/O - // pad. The reset state of this - // register is 0 for all signals. - -#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register. -// -//****************************************************************************** -#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 7 This field controls the - // configuration for GPIO pin 7. -#define GPIO_GPIO_PCTL_PMC7_S 28 -#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 6 This field controls the - // configuration for GPIO pin 6. -#define GPIO_GPIO_PCTL_PMC6_S 24 -#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 5 This field controls the - // configuration for GPIO pin 5. -#define GPIO_GPIO_PCTL_PMC5_S 20 -#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 4 This field controls the - // configuration for GPIO pin 4. -#define GPIO_GPIO_PCTL_PMC4_S 16 -#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 43 This field controls - // the configuration for GPIO pin 3. -#define GPIO_GPIO_PCTL_PMC3_S 12 -#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 1 This field controls the - // configuration for GPIO pin 1. -#define GPIO_GPIO_PCTL_PMC1_S 8 -#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 2 This field controls the - // configuration for GPIO pin 2. -#define GPIO_GPIO_PCTL_PMC2_S 4 -#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 0 This field controls the - // configuration for GPIO pin 0. -#define GPIO_GPIO_PCTL_PMC0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_ADCCTL register. -// -//****************************************************************************** -#define GPIO_GPIO_ADCCTL_ADCEN_M \ - 0x000000FF // This register is not used in - // cc3xx. ADC trigger via GPIO is - // not supported. ADC Trigger Enable - // Value Description 1 The - // corresponding pin is used to - // trigger the ADC. 0 The - // corresponding pin is not used to - // trigger the ADC. - -#define GPIO_GPIO_ADCCTL_ADCEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_DMACTL register. -// -//****************************************************************************** -#define GPIO_GPIO_DMACTL_DMAEN_M \ - 0x000000FF // This register is not used in the - // cc3xx. Alternate register to - // support this feature is coded in - // the APPS_NWP_CMN space. refer - // register as offset 0x400F70D8 - // ?DMA Trigger Enable Value - // Description 1 The corresponding - // pin is used to trigger the ?DMA. - // 0 The corresponding pin is not - // used to trigger the ?DMA. - -#define GPIO_GPIO_DMACTL_DMAEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_SI register. -// -//****************************************************************************** -#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value - // Description 1 Each pin has its - // own interrupt vector. 0 All port - // pin interrupts are OR'ed together - // to produce a summary interrupt. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID4 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID4_PID4_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [7:0] - -#define GPIO_GPIO_PERIPHID4_PID4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID5 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID5_PID5_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [15:8] - -#define GPIO_GPIO_PERIPHID5_PID5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID6 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID6_PID6_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [23:16] - -#define GPIO_GPIO_PERIPHID6_PID6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID7 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID7_PID7_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [31:24] - -#define GPIO_GPIO_PERIPHID7_PID7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID0 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID0_PID0_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [7:0] Can be used by - // software to identify the presence - // of this peripheral. - -#define GPIO_GPIO_PERIPHID0_PID0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID1 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID1_PID1_M \ - 0x000000FF // GPIO Peripheral ID Register - // [15:8] Can be used by software to - // identify the presence of this - // peripheral. - -#define GPIO_GPIO_PERIPHID1_PID1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID2 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID2_PID2_M \ - 0x000000FF // This register is not used in - // CC3XX.v GPIO Peripheral ID - // Register [23:16] Can be used by - // software to identify the presence - // of this peripheral. - -#define GPIO_GPIO_PERIPHID2_PID2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID3 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID3_PID3_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [31:24] Can be used by - // software to identify the presence - // of this peripheral. - -#define GPIO_GPIO_PERIPHID3_PID3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PCELLID0 register. -// -//****************************************************************************** -#define GPIO_GPIO_PCELLID0_CID0_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO PrimeCell ID Register - // [7:0] Provides software a - // standard cross-peripheral - // identification system. - -#define GPIO_GPIO_PCELLID0_CID0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PCELLID1 register. -// -//****************************************************************************** -#define GPIO_GPIO_PCELLID1_CID1_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO PrimeCell ID Register - // [15:8] Provides software a - // standard cross-peripheral - // identification system. - -#define GPIO_GPIO_PCELLID1_CID1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PCELLID2 register. -// -//****************************************************************************** -#define GPIO_GPIO_PCELLID2_CID2_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO PrimeCell ID Register - // [23:16] Provides software a - // standard cross-peripheral - // identification system. - -#define GPIO_GPIO_PCELLID2_CID2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PCELLID3 register. -// -//****************************************************************************** -#define GPIO_GPIO_PCELLID3_CID3_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO PrimeCell ID Register - // [31:24] Provides software a - // standard cross-peripheral - // identification system. - -#define GPIO_GPIO_PCELLID3_CID3_S 0 - - - -#endif // __HW_GPIO_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gprcm.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gprcm.h deleted file mode 100755 index 72b99d6d511..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gprcm.h +++ /dev/null @@ -1,3320 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_GPRCM_H__ -#define __HW_GPRCM_H__ - -//***************************************************************************** -// -// The following are defines for the GPRCM register offsets. -// -//***************************************************************************** -#define GPRCM_O_APPS_SOFT_RESET 0x00000000 -#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \ - 0x00000004 - -#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \ - 0x00000008 - -#define GPRCM_O_APPS_RESET_CAUSE \ - 0x0000000C - -#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \ - 0x00000010 - -#define GPRCM_O_APPS_SRAM_DSLP_CFG \ - 0x00000018 - -#define GPRCM_O_APPS_SRAM_LPDS_CFG \ - 0x0000001C - -#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \ - 0x00000020 - -#define GPRCM_O_TOP_DIE_ENABLE 0x00000100 -#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \ - 0x00000104 - -#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \ - 0x00000108 - -#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C -#define GPRCM_O_APPS_GPIO_WAKE_CONF \ - 0x00000110 - -#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \ - 0x00000114 - -#define GPRCM_O_MEM_HCLK_DIV_CFG \ - 0x00000118 - -#define GPRCM_O_MEM_SYSCLK_DIV_CFG \ - 0x0000011C - -#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \ - 0x00000120 - -#define GPRCM_O_NWP_SOFT_RESET 0x00000400 -#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \ - 0x00000404 - -#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \ - 0x00000408 - -#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C -#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \ - 0x00000410 - -#define GPRCM_O_NWP_SRAM_DSLP_CFG \ - 0x00000418 - -#define GPRCM_O_NWP_SRAM_LPDS_CFG \ - 0x0000041C - -#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \ - 0x00000420 - -#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \ - 0x00000424 - -#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \ - 0x00000428 - -#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \ - 0x0000042C - -#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \ - 0x00000430 - -#define GPRCM_O_NWP_GPIO_WAKE_CONF \ - 0x00000434 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \ - 0x00000438 - -#define GPRCM_O_GPRCM_DIEID_READ_REG5 \ - 0x00000448 - -#define GPRCM_O_GPRCM_DIEID_READ_REG6 \ - 0x0000044C - -#define GPRCM_O_REF_FSM_CFG0 0x00000800 -#define GPRCM_O_REF_FSM_CFG1 0x00000804 -#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \ - 0x00000808 - -#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \ - 0x0000080C - -#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \ - 0x00000810 - -#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \ - 0x00000814 - -#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \ - 0x00000818 - -#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \ - 0x0000081C - -#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \ - 0x00000820 - -#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \ - 0x00000824 - -#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \ - 0x00000828 - -#define GPRCM_O_SPARE_RW0 0x0000082C -#define GPRCM_O_SPARE_RW1 0x00000830 -#define GPRCM_O_APLLMCS_MCU_OVERRIDES \ - 0x00000834 - -#define GPRCM_O_SYSCLK_SWITCH_STATUS \ - 0x00000838 - -#define GPRCM_O_REF_LDO_CONTROLS \ - 0x0000083C - -#define GPRCM_O_REF_RTRIM_CONTROL \ - 0x00000840 - -#define GPRCM_O_REF_SLICER_CONTROLS0 \ - 0x00000844 - -#define GPRCM_O_REF_SLICER_CONTROLS1 \ - 0x00000848 - -#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \ - 0x0000084C - -#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \ - 0x00000850 - -#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \ - 0x00000854 - -#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \ - 0x00000858 - -#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \ - 0x0000085C - -#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \ - 0x00000860 - -#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \ - 0x00000864 - -#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868 -#define GPRCM_O_MEMSS_PWR_PS 0x0000086C -#define GPRCM_O_REF_FSM_DEBUG 0x00000870 -#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \ - 0x00000874 - -#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \ - 0x00000878 - -#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \ - 0x0000087C - -#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \ - 0x00000880 - -#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \ - 0x00000884 - -#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \ - 0x00000888 - -#define GPRCM_O_MEM_REF_FSM_CFG2 \ - 0x0000088C - -#define GPRCM_O_TESTCTRL_POWER_CTRL \ - 0x00000C10 - -#define GPRCM_O_SSDIO_POWER_CTRL \ - 0x00000C14 - -#define GPRCM_O_MCSPI_N1_POWER_CTRL \ - 0x00000C18 - -#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C -#define GPRCM_O_WL_SDIO_POWER_CTRL \ - 0x00000C20 - -#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \ - 0x00000C24 - -#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \ - 0x00000C28 - -#define GPRCM_O_APPS_SECURE_INIT_DONE \ - 0x00000C30 - -#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \ - 0x00000C34 - -#define GPRCM_O_EN_APPS_REBOOT 0x00000C38 -#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \ - 0x00000C3C - -#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \ - 0x00000C40 - -#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \ - 0x00000C44 - -#define GPRCM_O_NWP_PWR_STATE 0x00000C48 -#define GPRCM_O_APPS_PWR_STATE 0x00000C4C -#define GPRCM_O_MCU_PWR_STATE 0x00000C50 -#define GPRCM_O_WTOP_PM_PS 0x00000C54 -#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \ - 0x00000C58 - -#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \ - 0x00000C5C - -#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \ - 0x00000C60 - -#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \ - 0x00000C64 - -#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \ - 0x00000C68 - -#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \ - 0x00000C6C - -#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \ - 0x00000C70 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \ - 0x00000C78 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \ - 0x00000C7C - -#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \ - 0x00000C80 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \ - 0x00000C84 - -#define GPRCM_O_WTOP_MEM_RET_CFG \ - 0x00000C88 - -#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \ - 0x00000C8C - -#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \ - 0x00000C90 - -#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \ - 0x00000C94 - -#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \ - 0x00000C98 - -#define GPRCM_O_DCDC_CLK_GEN_CONFIG \ - 0x00000C9C - -#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \ - 0x00000CA0 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \ - 0x00000CA4 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \ - 0x00000CA8 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \ - 0x00000CAC - -#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \ - 0x00000CB0 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \ - 0x00000CB4 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \ - 0x00000CB8 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \ - 0x00000CBC - -#define GPRCM_O_GPRCM_DIEID_READ_REG0 \ - 0x00000CC0 - -#define GPRCM_O_GPRCM_DIEID_READ_REG1 \ - 0x00000CC4 - -#define GPRCM_O_GPRCM_DIEID_READ_REG2 \ - 0x00000CC8 - -#define GPRCM_O_GPRCM_DIEID_READ_REG3 \ - 0x00000CCC - -#define GPRCM_O_GPRCM_DIEID_READ_REG4 \ - 0x00000CD0 - -#define GPRCM_O_APPS_SS_OVERRIDES \ - 0x00000CD4 - -#define GPRCM_O_NWP_SS_OVERRIDES \ - 0x00000CD8 - -#define GPRCM_O_SHARED_SS_OVERRIDES \ - 0x00000CDC - -#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \ - 0x00000CE0 - -#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \ - 0x00000CE4 - -#define GPRCM_O_MCU_PSCON_OVERRIDES \ - 0x00000CE8 - -#define GPRCM_O_WTOP_PSCON_OVERRIDES \ - 0x00000CEC - -#define GPRCM_O_WELP_PSCON_OVERRIDES \ - 0x00000CF0 - -#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \ - 0x00000CF4 - -#define GPRCM_O_MCSPI_PSCON_OVERRIDES \ - 0x00000CF8 - -#define GPRCM_O_SSDIO_PSCON_OVERRIDES \ - 0x00000CFC - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SOFT_RESET register. -// -//****************************************************************************** -#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \ - 0x00000002 // Soft-reset1 for APPS : Cortex - // sysrstn is asserted and in - // addition to that the associated - // APPS Peripherals are also reset. - // This is an auto-clear bit. - -#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \ - 0x00000001 // Soft-reset0 for APPS : Only - // sys-resetn for Cortex will be - // asserted. This is an auto-clear - // bit. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_LPDS_WAKEUP_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \ - 0x000000FF // Mask for LPDS Wakeup interrupt : - // [7] - Host IRQ from NWP [6] - - // NWP_LPDS_Wake_irq (TRUE_LPDS) [5] - // - NWP Wake-request to APPS [4] - - // GPIO [3:1] - Reserved [0] - LPDS - // Wakeup-timer - -#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_LPDS_WAKEUP_SRC register. -// -//****************************************************************************** -#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \ - 0x000000FF // Indicates the cause for wakeup - // from LPDS : [7] - Host IRQ from - // NWP [6] - NWP_LPDS_Wake_irq - // (TRUE_LPDS) [5] - NWP - // Wake-request to APPS [4] - GPIO - // [3:1] - Reserved [0] - LPDS - // Wakeup-timer - -#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_RESET_CAUSE register. -// -//****************************************************************************** -#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \ - 0x000000FF // Indicates the reset cause for - // APPS : "0000" - Wake from HIB/OFF - // mode; "0001" - Wake from LPDS ; - // "0010" - Reserved ; "0011" - - // Soft-reset0 (Only APPS - // Cortex-sysrstn is asserted); - // "0100" - Soft-reset1 (APPS - // Cortex-sysrstn and APPS - // peripherals are reset); "0101" - - // WDOG0 (APPS Cortex-sysrstn and - // APPS peripherals are reset); - // "0110" - MCU Soft-reset (APPS + - // NWP Cortex-sysrstn + Peripherals - // are reset); "0111" - Secure Init - // done (Indication that reset has - // happened after DevInit); "1000" - - // Dev Mode Patch Init done (During - // development mode, patch - // downloading and Cortex - // re-vectoring is completed) - -#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \ - 0xFFFFFFFF // OPP Request Configuration - // (Number of slow-clk cycles) for - // LPDS Wake-timer : This - // configuration implies the RTC - // time-stamp, which must be few - // slow-clks prior to - // APPS_LPDS_WAKETIME_WAKE_CFG, such - // that by the time actual wakeup is - // given, OPP is already switched to - // ACTIVE (RUN). - -#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SRAM_DSLP_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \ - 0x000FFFFF // Configuration of APPS Memories - // during Deep-sleep : 0 - SRAMs are - // OFF ; 1 - SRAMs are Retained. - // APPS SRAM Cluster information : - // [0] - 1st column in MEMSS - // (Applicable only when owned by - // APPS); [1] - 2nd column in MEMSS - // (Applicable only when owned by - // APPS); [2] - 3rd column in MEMSS - // (Applicable only when owned by - // APPS) ; [3] - 4th column in MEMSS - // (Applicable only when owned by - // APPS) ; [16] - MCU-PD - Apps - // cluster 0 (TBD); [19:18] - - // Reserved. - -#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SRAM_LPDS_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \ - 0x000FFFFF // Configuration of APPS Memories - // during LPDS : 0 - SRAMs are OFF ; - // 1 - SRAMs are Retained. APPS SRAM - // Cluster information : [0] - 1st - // column in MEMSS (Applicable only - // when owned by APPS); [1] - 2nd - // column in MEMSS (Applicable only - // when owned by APPS); [2] - 3rd - // column in MEMSS (Applicable only - // when owned by APPS) ; [3] - 4th - // column in MEMSS (Applicable only - // when owned by APPS) ; [16] - - // MCU-PD - Apps cluster 0 (TBD); - // [19:18] - Reserved. - -#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \ - 0xFFFFFFFF // Configuration (in no of - // slow_clks) which says when the - // actual wakeup request for - // removing the PD-reset be given. - -#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TOP_DIE_ENABLE register. -// -//****************************************************************************** -#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \ - 0x00001000 - -#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \ - 0x00000F00 - -#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8 -#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \ - 0x00000002 // 1 - Top-die is enabled ; - -#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \ - 0x00000001 // 1 - Enable the top-die ; 0 - - // Disable the top-die - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register. -// -//****************************************************************************** -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \ - 0xF0000000 // Configuration (in slow_clks) for - // number of clks between - // Flash-3p3-rstn to D2D POR Resetn. - -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28 -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \ - 0x00FF0000 // Configuration (in slow_clks) for - // number of clks between Top-die - // Switch-Enable and Top-die Flash - // 3p3 Reset removal - -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16 -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \ - 0x000000FF // Configuration (in slow_clks) for - // number of clks between D2D POR - // Reset removal and bottom die FMC - // reset removal - -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_GLOBAL_SOFT_RESET register. -// -//****************************************************************************** -#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \ - 0x00000001 // 1 - Assert the global reset for - // MCU (APPS + NWP) ; Asserts both - // Cortex sysrstn and its - // peripherals 0 - Deassert the - // global reset for MCU (APPS + NWP) - // ; Asserts both Cortex sysrstn and - // its peripherals Note : Reset for - // shared peripherals is not - // affected here. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_ADC_CLK_CONFIG register. -// -//****************************************************************************** -#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \ - 0x000007C0 // Configuration (in number of 38.4 - // MHz clks) for the OFF-Time in - // generation of ADC_CLK - -#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6 -#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \ - 0x0000003E // Configuration (in number of 38.4 - // MHz clks) for the ON-Time in - // generation of ADC_CLK - -#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1 -#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \ - 0x00000001 // 1 - Enable the ADC_CLK ; 0 - - // Disable the ADC_CLK - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_GPIO_WAKE_CONF register. -// -//****************************************************************************** -#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \ - 0x00000003 // "00" - Wake on Level0 on - // selected GPIO pin (GPIO is - // selected inside the HIB3p3 - // module); "01" - Wakeup on - // fall-edge of GPIO pin. - -#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register. -// -//****************************************************************************** -#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \ - 0xFFFFFFFE - -#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1 -#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \ - 0x00000001 // 1 - Override the secure-mode - // done for booting up NWP (Wakeup - // NWP on its event independent of - // CM4 state) ; 0 - Donot override - // the secure-mode done for NWP boot - // (NWP must be enabled by CM4 only) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_HCLK_DIV_CFG register. -// -//****************************************************************************** -#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \ - 0x00000007 // Division configuration for - // HCLKDIVOUT : "000" - Divide by 1 - // ; "001" - Divide by 2 ; "010" - - // Divide by 3 ; "011" - Divide by 4 - // ; "100" - Divide by 5 ; "101" - - // Divide by 6 ; "110" - Divide by 7 - // ; "111" - Divide by 8 - -#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_SYSCLK_DIV_CFG register. -// -//****************************************************************************** -#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \ - 0x00000038 - -#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3 -#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \ - 0x00000007 - -#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_LOCK_TIME_CONF register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \ - 0x0000FF00 - -#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8 -#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \ - 0x000000FF - -#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_SOFT_RESET register. -// -//****************************************************************************** -#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \ - 0x00000002 // Soft-reset1 for NWP - Cortex - // sysrstn and NWP associated - // peripherals are - This is an - // auto-clr bit. - -#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \ - 0x00000001 // Soft-reset0 for NWP - Only - // Cortex-sysrstn is asserted - This - // is an auto-clear bit. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_LPDS_WAKEUP_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \ - 0x000000FF // Mask for LPDS Wakeup interrupt : - // 7 - WLAN Host Interrupt ; 6 - - // WLAN to NWP Wake request ; 5 - - // APPS to NWP Wake request; 4 - - // GPIO Wakeup ; 3 - Autonomous UART - // Wakeup ; 2 - SSDIO Wakeup ; 1 - - // Autonomous SPI Wakeup ; 0 - LPDS - // Wakeup-timer - -#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_LPDS_WAKEUP_SRC register. -// -//****************************************************************************** -#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \ - 0x000000FF // Indicates the cause for NWP - // LPDS-Wakeup : 7 - WLAN Host - // Interrupt ; 6 - WLAN to NWP Wake - // request ; 5 - APPS to NWP Wake - // request; 4 - GPIO Wakeup ; 3 - - // Autonomous UART Wakeup ; 2 - - // SSDIO Wakeup ; 1 - Autonomous SPI - // Wakeup ; 0 - LPDS Wakeup-timer - -#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_RESET_CAUSE register. -// -//****************************************************************************** -#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \ - 0x000000FF // Indicates the reset cause for - // NWP : "0000" - Wake from HIB/OFF - // mode; "0001" - Wake from LPDS ; - // "0010" - Reserved ; "0011" - - // Soft-reset0 (Only NWP - // Cortex-sysrstn is asserted); - // "0100" - Soft-reset1 (NWP - // Cortex-sysrstn and NWP - // peripherals are reset); "0101" - - // WDOG0 (NWP Cortex-sysrstn and NWP - // peripherals are reset); "0110" - - // MCU Soft-reset (APPS + NWP - // Cortex-sysrstn + Peripherals are - // reset); "0111" - SSDIO Function2 - // reset (Only Cortex-sysrstn is - // asserted) ; "1000" - Reset due to - // WDOG of APPS (NWP Cortex-sysrstn - // and NWP peripherals are reset); - -#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \ - 0xFFFFFFFF // OPP Request Configuration - // (Number of slow-clk cycles) for - // LPDS Wake-timer - -#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_SRAM_DSLP_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \ - 0x000FFFFF // Configuration of NWP Memories - // during DSLP : 0 - SRAMs are OFF ; - // 1 - SRAMs are Retained. NWP SRAM - // Cluster information : [2] - 3rd - // column in MEMSS (Applicable only - // when owned by NWP) ; [3] - 4th - // column in MEMSS (Applicable only - // when owned by NWP) ; [4] - 5th - // column in MEMSS (Applicable only - // when owned by NWP) ; [5] - 6th - // column in MEMSS (Applicable only - // when owned by NWP) ; [6] - 7th - // column in MEMSS (Applicable only - // when owned by NWP) ; [7] - 8th - // column in MEMSS (Applicable only - // when owned by NWP) ; [8] - 9th - // column in MEMSS (Applicable only - // when owned by NWP) ; [9] - 10th - // column in MEMSS (Applicable only - // when owned by NWP) ; [10] - 11th - // column in MEMSS (Applicable only - // when owned by NWP) ; [11] - 12th - // column in MEMSS (Applicable only - // when owned by NWP) ; [12] - 13th - // column in MEMSS (Applicable only - // when owned by NWP) ; [13] - 14th - // column in MEMSS (Applicable only - // when owned by NWP) ; [14] - 15th - // column in MEMSS (Applicable only - // when owned by NWP) ; [19:18] - - // Reserved. - -#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_SRAM_LPDS_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \ - 0x000FFFFF // Configuration of NWP Memories - // during LPDS : 0 - SRAMs are OFF ; - // 1 - SRAMs are Retained. NWP SRAM - // Cluster information : [2] - 3rd - // column in MEMSS (Applicable only - // when owned by NWP) ; [3] - 4th - // column in MEMSS (Applicable only - // when owned by NWP) ; [4] - 5th - // column in MEMSS (Applicable only - // when owned by NWP) ; [5] - 6th - // column in MEMSS (Applicable only - // when owned by NWP) ; [6] - 7th - // column in MEMSS (Applicable only - // when owned by NWP) ; [7] - 8th - // column in MEMSS (Applicable only - // when owned by NWP) ; [8] - 9th - // column in MEMSS (Applicable only - // when owned by NWP) ; [9] - 10th - // column in MEMSS (Applicable only - // when owned by NWP) ; [10] - 11th - // column in MEMSS (Applicable only - // when owned by NWP) ; [11] - 12th - // column in MEMSS (Applicable only - // when owned by NWP) ; [12] - 13th - // column in MEMSS (Applicable only - // when owned by NWP) ; [13] - 14th - // column in MEMSS (Applicable only - // when owned by NWP) ; [14] - 15th - // column in MEMSS (Applicable only - // when owned by NWP) ; [19:18] - - // Reserved. - -#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \ - 0xFFFFFFFF // Wake time configuration (no of - // slow clks) for NWP wake from - // LPDS. - -#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register. -// -//****************************************************************************** -#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \ - 0xFFFE0000 - -#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17 -#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \ - 0x00010000 // 0 - APPS is selected as host for - // Autonms SPI ; 1 - External host - // is selected as host for Autonms - // SPI - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register. -// -//****************************************************************************** -#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \ - 0x00010000 - -#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \ - 0x00000002 // When 1 => IDLE-mode is - // acknowledged by the SPI-IP. (This - // is for MCSPI_N1) - -#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \ - 0x00000001 // When 1 => Request for IDLE-mode - // for autonomous SPI. (This is for - // MCSPI_N1) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register. -// -//****************************************************************************** -#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \ - 0x00000001 // 1 - Request for waking up NWP - // from any of its low-power modes - // (SLP/DSLP/LPDS) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register. -// -//****************************************************************************** -#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \ - 0x00000001 // 1 - Request for wakinp up WLAN - // from its ELP Mode (This gets - // triggered to ELP-logic of WLAN) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_GPIO_WAKE_CONF register. -// -//****************************************************************************** -#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \ - 0x00000003 // "00" - Wakeup on level0 of the - // selected GPIO (GPIO gets selected - // inside HIB3P3-module); "01" - - // Wakeup on fall-edge of selected - // GPIO. - -#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG12 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \ - 0x0000FFFF // This corrsponds to ROW_32 - // [31:16] of the FUSEFARM. SPARE - -#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG5 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \ - 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM - // : [5:0] - ADC OFFSET ; [13:6] - - // TEMP_SENSE ; [14:14] - DFT_GSG ; - // [15:15] - FMC_DISABLE ; [31:16] - - // WLAN_MAC ID - -#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG6 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \ - 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM - // : [31:0] : WLAN MAC ID - -#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_FSM_CFG0 register. -// -//****************************************************************************** -#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \ - 0x00FF0000 // ANA-BGAP Settling time (In - // number of slow_clks) - -#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16 -#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \ - 0x0000FF00 // Slicer LDO settling time (In - // number of slow clks) - -#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8 -#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \ - 0x000000FF // Dig-buffer settling time (In - // number of slow clks) - -#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_FSM_CFG1 register. -// -//****************************************************************************** -#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \ - 0xFF000000 // XTAL settling time (In number of - // slow clks) - -#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24 -#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \ - 0x00FF0000 // LV Slicer settling time - -#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16 -#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \ - 0x0000FF00 // HV Slicer Pull-down settling - // time - -#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8 -#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \ - 0x000000FF // HV Slicer settling time - -#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \ - 0x00007F00 // Configuration for WLAN APLLMCS - - // N[6:0], if the XTAL frequency is - // 40 MHz (Selected by efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8 -#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \ - 0x000000FF // Configuration for WLAN APLLMCS - - // M[7:0], if the XTAL frequency is - // 40 MHz (Selected by efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \ - 0x00000010 // Configuration for WLAN APLLMCS - - // if the XTAL frequency if 40 MHz - // (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \ - 0x00000008 // Configuration for WLAN APLLMCS - - // Sel96, if the XTAL frequency is - // 40 MHz (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \ - 0x00000007 // Configuration for WLAN APLLMCS - - // Selinpfreq, if the XTAL frequency - // is 40 MHz (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \ - 0x00007F00 // Configuration for WLAN APLLMCS - - // N[6:0], if the XTAL frequency is - // 26 MHz (Selected by efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8 -#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \ - 0x000000FF // Configuration for WLAN APLLMCS - - // M[7:0], if the XTAL frequency is - // 26 MHz (Selected by efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \ - 0x00000010 // Configuration for WLAN APLLMCS - - // if the XTAL frequency if 26 MHz - // (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \ - 0x00000008 // Configuration for WLAN APLLMCS - - // Sel96, if the XTAL frequency is - // 26 MHz (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \ - 0x00000007 // Configuration for WLAN APLLMCS - - // Selinpfreq, if the XTAL frequency - // is 26 MHz (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \ - 0x00080000 - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \ - 0x00070000 - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16 -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \ - 0x00000700 - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8 -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \ - 0x00000020 // Override control for - // WLAN_APLLMCS_M[8]. When set to1, - // M[8] will be selected by bit [3]. - // (Else controlled from WTOP) - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \ - 0x00000010 // Override for WLAN_APLLMCS_M[8]. - // Applicable only when bit [4] is - // set to 1. (Else controlled from - // WTOP) - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \ - 0x00000004 // Override control for - // WLAN_APLLMCS_N[8:7]. When set - // to1, N[8:7] will be selected by - // bits [2:1]. (Else controlled from - // WTOP) - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \ - 0x00000003 // Override value for - // WLAN_APLLMCS_N[8:7] bits. - // Applicable only when bit [1] is - // set to 1. (Else controlled from - // WTOP) - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \ - 0x38000000 - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \ - 0x07000000 - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \ - 0x007F0000 // Configuration for MCU-APLLMCS : - // N during RUN mode. Selected if - // the XTAL frequency is 38.4 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \ - 0x0000FF00 // Configuration for MCU-APLLMCS : - // M during RUN mode. Selected if - // the XTAL frequency is 38.4 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \ - 0x00000010 // Configuration for MCU-APLLMCS : - // M[8] during RUN mode. Selected if - // the XTAL frequency is 38.4 MHz - // (From Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \ - 0x00000003 // Configuration for MCU-APLLMCS : - // N[8:7] during RUN mode. Selected - // if the XTAL frequency is 38.4 MHz - // (From Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \ - 0x00000010 // Configuration for MCU-APLLMCS : - // HISPEED during RUN mode. Selected - // if the XTAL frequency is 38.4 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \ - 0x00000008 // Configuration for MCU-APLLMCS : - // SEL96 during RUN mode. Selected - // if the XTAL frequency is 38.4 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \ - 0x00000007 // Configuration for MCU-APLLMCS : - // SELINPFREQ during RUN mode. - // Selected if the XTAL frequency is - // 38.4 MHz (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \ - 0x007F0000 // Configuration for MCU-APLLMCS : - // N during RUN mode. Selected if - // the XTAL frequency is 26 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \ - 0x0000FF00 // Configuration for MCU-APLLMCS : - // M during RUN mode. Selected if - // the XTAL frequency is 26 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \ - 0x00000010 // Configuration for MCU-APLLMCS : - // M[8] during RUN mode. Selected if - // the XTAL frequency is 26 MHz - // (From Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \ - 0x00000003 // Configuration for MCU-APLLMCS : - // N[8:7] during RUN mode. Selected - // if the XTAL frequency is 26 MHz - // (From Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \ - 0x00000010 // Configuration for MCU-APLLMCS : - // HISPEED during RUN mode. Selected - // if the XTAL frequency is 26 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \ - 0x00000008 // Configuration for MCU-APLLMCS : - // SEL96 during RUN mode. Selected - // if the XTAL frequency is 26 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \ - 0x00000007 // Configuration for MCU-APLLMCS : - // SELINPFREQ during RUN mode. - // Selected if the XTAL frequency is - // 26 MHz (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \ - 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 - - // APLLMCS_MCU is not locked - -#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \ - 0x00000200 // Override for APLLMCS_MCU Enable. - // Applicable if bit [8] is set - -#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \ - 0x00000100 // 1 - Enable for APLLMCS_MCU comes - // from bit [9]. 0 - Enable for - // APLLMCS_MCU comes from FSM. - -#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \ - 0x00000006 // Override for sysclk src - // (applicable only if bit [0] is - // set to 1. "00"- SLOW_CLK "01"- - // XTAL_CLK "10"- PLL_CLK - -#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1 -#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \ - 0x00000001 // 1 - Sysclk src is selected from - // bits [2:1] of this register. 0 - - // Sysclk src is selected from FSM - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SYSCLK_SWITCH_STATUS register. -// -//****************************************************************************** -#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \ - 0x00000001 // 1 - Sysclk switching is - // complete. 0 - Sysclk switching is - // in progress. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_LDO_CONTROLS register. -// -//****************************************************************************** -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \ - 0x00010000 // 1 - Enable for REF_LDO comes - // from bit [0] of this register ; 0 - // - Enable for REF_LDO comes from - // the FSM. Note : Final REF_LDO_EN - // reaches on the port - // TOP_PM_REG2[0] of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \ - 0x0000C000 // Spare bits for REF_CTRL_FSM. - // Reaches directly on port - // TOP_PM_REG2[15:14] of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14 -#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \ - 0x00003800 // REF TLOAD Enable. Reaches - // directly on port - // TOP_PM_REG2[13:11] of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11 -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \ - 0x00000700 // REF_LDO Test-mux control. - // Reaches directly on port - // TOP_PM_REG2[10:8] of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8 -#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \ - 0x000000C0 // REF BW Control. Reaches directly - // on port TOP_PM_REG2[7:6] of - // gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6 -#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \ - 0x0000003C // REF VTRIM Control. Reaches - // directly on port TOP_PM_REG2[5:2] - // of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2 -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \ - 0x00000002 // REF LDO Bypass Enable. Reaches - // directly on port TOP_PM_REG2[1] - // of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \ - 0x00000001 // Override for REF_LDO Enable. - // Applicable only if bit [16] of - // this register is set. Note : - // Final REF_LDO_EN reaches on the - // port TOP_PM_REG2[0] of gprcm. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_RTRIM_CONTROL register. -// -//****************************************************************************** -#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \ - 0x18000000 // This is [5:4] bits of - // TOP_PM_REG0 - -#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27 -#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \ - 0x07FF0000 // This is [15:5] bits of - // TOP_CLKM_REG0 - -#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16 -#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \ - 0x00000100 // 1 - CLKM_RTRIM comes for - // bits[4:0] of this register. 0 - - // CLKM_RTRIM comes from Efuse - // (after efuse_done = 1). - -#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \ - 0x0000001F // CLKM_TRIM Override. Applicable - // when efuse_done = 0 or bit[8] is - // set to 1. - -#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_SLICER_CONTROLS0 register. -// -//****************************************************************************** -#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \ - 0x00200000 // 1 - EN_DIG_BUF_TOP comes from - // bit [14] of this register. 0 - - // EN_DIG_BUF_TOP comes from the - // FSM. Note : Final EN_DIG_BUF_WLAN - // reaches on TOP_CLKM_REG1_IN[14] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \ - 0x00100000 // 1 - EN_DIG_BUF_TOP comes from - // bit [15] of this register. 0 - - // EN_DIG_BUF_TOP comes from the - // FSM. Note : Final EN_DIG_BUF_TOP - // reaches on TOP_CLKM_REG1_IN[15] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \ - 0x00080000 // 1 - EN_XTAL comes from bit [3] - // of this register. 0 - EN_XTAL - // comes from FSM. Note : Final - // XTAL_EN reaches on - // TOP_CLKM_REG1_IN[3] of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \ - 0x00040000 // 1 - Enable HV Slicer comes from - // bit [2] of this register. 0 - - // Enable HV Slicer comes from FSM. - // Note : Final HV_SLICER_EN reaches - // on port TOP_CLKM_REG1_IN[1] of - // gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \ - 0x00020000 // 1 - Enable LV Slicer comes from - // bit[1] of this register. 0 - - // Enable LV Slicer comes from FSM. - // Note : final LV_SLICER_EN reaches - // on port TOP_CLKM_REG1_IN[2] of - // gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \ - 0x00010000 // 1 - Enable HV Pull-down comes - // from bit[0] of this register. 0 - - // Enable HV Pull-down comes from - // FSM. Note : Final HV_PULL_DOWN - // reaches on port - // TOP_CLKM_REG1_IN[0] of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \ - 0x00008000 // Override for EN_DIG_BUF_TOP. - // Applicable if bit[20] is set to - // 1. Note : Final EN_DIG_BUF_TOP - // reaches on TOP_CLKM_REG1_IN[15] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \ - 0x00004000 // Override for EN_DIG_BUF_WLAN. - // Applicable if bit[19] is set to - // 1. Note : Final EN_DIG_BUF_WLAN - // reaches on TOP_CLKM_REG1_IN[14] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \ - 0x00002000 // CLKOUT Flip Enable. Reaches on - // bit[13] of TOP_CLKM_REG1_IN[13] - // port of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \ - 0x00001000 // Enable divide2 in WLAN Clk-path. - // Reaches on TOP_CLKM_REG1_IN[12] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \ - 0x00000800 // Enable divide3 in WLAN Clk-path. - // Reaches on TOP_CLKM_REG1_IN[11] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \ - 0x00000400 // Enable divide4 in WLAN Clk-path. - // Reaches on TOP_CLKM_REG1_IN[10] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \ - 0x000003C0 // CM Test-mux select. Reaches on - // TOP_CLMM_REG1_IN[9:6] port of - // gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6 -#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \ - 0x00000030 // Slicer spare0 control. Reaches - // on TOP_CLKM_REG1_IN[5:4] port of - // gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4 -#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \ - 0x00000008 // Enable XTAL override. Reaches on - // TOP_CLKM_REG1_IN[3] port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \ - 0x00000004 // Enable HV Slicer override. - // Reaches on TOP_CLKM_REG1_IN[1] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \ - 0x00000002 // Enable LV Slicer override. - // Reaches on TOP_CLKM_REG1_IN[2] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \ - 0x00000001 // Enable HV Pull-down override. - // Reaches on TOP_CLKM_REG1_IN[0] - // port of gprcm - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_SLICER_CONTROLS1 register. -// -//****************************************************************************** -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \ - 0x0000FC00 // Slicer spare1. Reaches on port - // TOP_CLKM_REG2_IN[15:10] of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10 -#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \ - 0x000003F0 // XOSC Trim. Reaches on port - // TOP_CLKM_REG2_IN[9:4] of gprcm - -#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4 -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \ - 0x00000008 // Slicer ITRIM Toggle. Reaches on - // port TOP_CLKM_REG2_IN[3] of - // gprcm. - -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \ - 0x00000007 // LV Slicer trim. Reaches on port - // TOP_CLKM_REG2_IN[2:0] of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register. -// -//****************************************************************************** -#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \ - 0xFF800000 - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23 -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \ - 0x00400000 // 1 - REF_MAG_TRIM comes from - // bit[4:0] of register - // REF_ANA_BGAP_CONTROLS1 [Addr : - // 0x0850]; 0 - REF_MAG_TRIM comes - // from efuse (After efc_done = 1). - // Note : Final REF_MAG_TRIM reaches - // on port TOP_PM_REG1[4:0] of gprcm - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \ - 0x00200000 // 1 - REF_V2I_TRIM comes from - // bit[9:6] of this register ; 0 - - // REF_V2I_TRIM comes from efuse - // (After efc_done = 1). Note : - // Final REF_V2I_TRIM reaches on - // port TOP_PM_REG0[9:6] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \ - 0x00100000 // 1 - REF_TEMP_TRIM comes from - // bit[15:10] of this register ; 0 - - // REF_TEMP_TRIM comes from efuse - // (After efc_done = 1). Note : - // Final REF_TEMP_TRIM reaches on - // port TOP_PM_REG0[15:10] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \ - 0x00080000 // 1 - REF_STARTUP_EN comes from - // bit [3] of this register ; 0 - - // REF_STARTUP_EN comes from FSM. - // Note : Final REF_STARTUP_EN - // reaches on port TOP_PM_REG0[3] of - // gprcm - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \ - 0x00040000 // 1 - REF_V2I_EN comes from bit - // [2] of this register ; 0 - - // REF_V2I_EN comes from FSM. Note : - // Final REF_V2I_EN reaches on port - // TOP_PM_REG0[2] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \ - 0x00020000 // 1 - REF_FC_EN comes from bit [1] - // of this register ; 0 - REF_FC_EN - // comes from FSM. Note : Final - // REF_FC_EN reaches on port - // TOP_PM_REG0[1] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \ - 0x00010000 // 1 - REF_BGAP_EN comes from bit - // [0] of this register ; 0 - - // REF_BGAP_EN comes from FSM. Note - // : Final REF_BGAP_EN reaches on - // port TOP_PM_REG0[0] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \ - 0x0000FC00 // REF_TEMP_TRIM override. - // Applicable when bit [20] of this - // register set to 1. (or efc_done = - // 0) Note : Final REF_TEMP_TRIM - // reaches on port - // TOP_PM_REG0[15:10] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10 -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \ - 0x000003C0 // REF_V2I_TRIM Override. - // Applicable when bit [21] of this - // register set to 1 . (of efc_done - // = 0) Note : Final REF_V2I_TRIM - // reaches on port TOP_PM_REG0[9:6] - // of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6 -#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \ - 0x00000030 - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4 -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \ - 0x00000008 // REF_STARTUP_EN override. - // Applicable when bit [19] of this - // register is set to 1. Note : - // Final REF_STARTUP_EN reaches on - // port TOP_PM_REG0[3] of gprcm - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \ - 0x00000004 // REF_V2I_EN override. Applicable - // when bit [21] of this register is - // set to 1. Note : Final REF_V2I_EN - // reaches on port TOP_PM_REG0[2] of - // gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \ - 0x00000002 // REF_FC_EN override. Applicable - // when bit [17] of this register is - // set to 1. Note : Final REF_FC_EN - // reaches on port TOP_PM_REG0[1] of - // gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \ - 0x00000001 // REF_BGAP_EN override. Applicable - // when bit [16] of this register - // set to 1. Note : Final - // REF_BGAP_EN reaches on port - // TOP_PM_REG0[0] of gprcm. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register. -// -//****************************************************************************** -#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \ - 0xFFFF0000 - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16 -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \ - 0x0000C000 // REF_BGAP_SPARE. Reaches on port - // TOP_PM_REG1[15:14] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14 -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \ - 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on - // port TOP_PM_REG1[13:9] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9 -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \ - 0x000001E0 // REF_FILT_TRIM. Reaches on port - // TOP_PM_REG1[8:5] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5 -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \ - 0x0000001F // REF_MAG_TRIM Override. - // Applicable when bit[22] of - // REF_ANA_BGAP_CONTROLS0 [0x084C] - // set to 1 (of efc_done = 0). Note - // : Final REF_MAG_TRIM reaches on - // port TOP_PM_REG1[4:0] of gprcm - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register. -// -//****************************************************************************** -#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \ - 0xFFFF0000 - -#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16 -#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \ - 0x0000FFFF // Spare control. Reaches on - // TOP_PM_REG3 [15:0] of gprcm. - -#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register. -// -//****************************************************************************** -#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \ - 0xFFFF0000 // Spare control. Reaches on - // TOP_CLKM_REG3 [15:0] of gprcm. - -#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16 -#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \ - 0x0000FFFF // Spare control. Reaches on - // TOP_CLKM_REG4 [15:0] of gprcm. - -#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register. -// -//****************************************************************************** -#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \ - 0xFFFF0000 - -#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16 -#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \ - 0x0000FFFF - -#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register. -// -//****************************************************************************** -#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \ - 0xFFFFFFC0 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6 -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \ - 0x00000020 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \ - 0x00000010 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \ - 0x00000008 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \ - 0x00000004 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \ - 0x00000002 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_PLL_REF_LOCK_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \ - 0xFFFFFFF8 - -#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3 -#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \ - 0x00000004 - -#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \ - 0x00000002 - -#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_PSCON_DEBUG register. -// -//****************************************************************************** -#define GPRCM_MCU_PSCON_DEBUG_reserved_M \ - 0xFFFFFFC0 - -#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6 -#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \ - 0x00000038 // MCU_PSCON_RTC_ON = "0000"; - // MCU_PSCON_RTC_OFF = "0001"; - // MCU_PSCON_RTC_RET = "0010"; - // MCU_PSCON_RTC_OFF_TO_ON = "0011"; - // MCU_PSCON_RTC_RET_TO_ON = "0100"; - // MCU_PSCON_RTC_ON_TO_RET = "0101"; - // MCU_PSCON_RTC_ON_TO_OFF = "0110"; - // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP - // = "0111"; - // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP - // = "1000"; - -#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3 -#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \ - 0x00000007 - -#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEMSS_PWR_PS register. -// -//****************************************************************************** -#define GPRCM_MEMSS_PWR_PS_reserved_M \ - 0xFFFFFFF8 - -#define GPRCM_MEMSS_PWR_PS_reserved_S 3 -#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \ - 0x00000007 // MEMSS_PM_SLEEP = "000"; - // MEMSS_PM_WAIT_OPP = "010"; - // MEMSS_PM_ACTIVE = "011"; - // MEMSS_PM_SLEEP_TO_ACTIVE = "100"; - // MEMSS_PM_ACTIVE_TO_SLEEP = "101"; - -#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_FSM_DEBUG register. -// -//****************************************************************************** -#define GPRCM_REF_FSM_DEBUG_reserved_M \ - 0xFFFFFFC0 - -#define GPRCM_REF_FSM_DEBUG_reserved_S 6 -#define GPRCM_REF_FSM_DEBUG_fref_mode_M \ - 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11 - // - XTAL Mode - -#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4 -#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \ - 0x0000000F // constant FREF_CLK_OFF = "00000"; - // constant FREF_EN_BGAP = "00001"; - // constant FREF_EN_LDO = "00010"; - // constant FREF_EN_SLI_HV = - // "00011"; constant - // FREF_EN_SLI_HV_PD = "00100"; - // constant FREF_EN_DIG_BUF = - // "00101"; constant FREF_EN_OSC = - // "00110"; constant FREF_EN_SLI_LV - // = "00111"; constant - // FREF_EN_CLK_REQ = "01000"; - // constant FREF_CLK_VALID = - // "01001"; constant FREF_MODE_DET0 - // = "01010"; constant - // FREF_MODE_DET1 = "01011"; - // constant FREF_MODE_DET2 = - // "10010"; constant FREF_MODE_DET3 - // = "10011"; constant FREF_VALID = - // "01100"; constant FREF_VALID0 = - // "01101"; constant FREF_VALID1 = - // "01110"; constant FREF_VALID2 = - // "01111"; constant - // FREF_WAIT_EXT_TCXO0 = "10000"; - // constant FREF_WAIT_EXT_TCXO1 = - // "10001"; - -#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register. -// -//****************************************************************************** -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \ - 0xFFFFFFE0 - -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5 -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \ - 0x00000010 // 1 - Override the sytem-opp - // request to ANATOP using bit0 of - // this register - -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \ - 0x0000000F // "0001" - RUN ; "0010" - DSLP ; - // "0100" - LPDS ; Others - NA - -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register. -// -//****************************************************************************** -#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \ - 0xFFFFFFFE - -#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1 -#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \ - 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS) - // entry even if Test-Pd is kept ON - // ; 0 - Donot enable sleep-opp - // (DSLP/LPDS) entry with Test-Pd - // ON. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \ - 0xFFFFFFF8 - -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3 -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \ - 0x00000004 // NA - -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \ - 0x00000002 // NA - -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \ - 0x00000001 // NA - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \ - 0x00000004 // 1 - Override the MCU-PD power - // modes using bits [1] & [0] ; - -#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \ - 0x00000002 // 1 - Request for power-down of - // MCU-PD ; - -#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \ - 0x00000001 // 1 - Request for retention mode - // of MCU-PD. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \ - 0x00000002 // 1- Override the MCSPI - // (Autonomous SPI) memory state - // using bit [0] - -#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \ - 0x00000001 // 1 - Request for power-down of - // Autonomous SPI 8k memory ; 0 - - // Donot request power-down of - // Autonomous SPI 8k Memory - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \ - 0x00000100 - -#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \ - 0x00000002 - -#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_REF_FSM_CFG2 register. -// -//****************************************************************************** -#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \ - 0x00380000 // Number of RTC clocks for keeping - // the FC_EN asserted high - -#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19 -#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \ - 0x00070000 // Number of RTC clocks for keeping - // the STARTUP_EN asserted high - -#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16 -#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \ - 0x0000FFFF // Number of RTC clocks for waiting - // for clock to settle. - -#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TESTCTRL_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \ - 0x00000006 - -#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1 -#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \ - 0x00000001 // 0 - Disable the TestCtrl-pd ; 1 - // - Enable the TestCtrl-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SSDIO_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \ - 0x00000006 // 1 - SSDIO-PD is ON ; 0 - - // SSDIO-PD is OFF - -#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1 -#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \ - 0x00000001 // 0 - Disable the SSDIO-pd ; 1 - - // Enable the SSDIO-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCSPI_N1_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \ - 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 - - // MCSPI_N1-PD if OFF - -#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1 -#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \ - 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1 - // - Enable the MCSPI_N1-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WELP_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \ - 0x00001C00 - -#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10 -#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \ - 0x00000200 - -#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \ - 0x00000100 - -#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \ - 0x00000006 - -#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1 -#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \ - 0x00000001 // 0 - Disable the WELP-pd ; 1 - - // Enable the WELP-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WL_SDIO_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \ - 0x00000006 - -#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1 -#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \ - 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 - - // Enable the WL_SDIO-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register. -// -//****************************************************************************** -#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \ - 0x00FFFFFF // SRAM (WTOP+DRP) state during - // Active-mode : 1 - SRAMs are ON ; - // 0 - SRAMs are OFF. Cluster - // information : [0] - 1st column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) [1] - 2nd column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [2] - 3rd column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [3] - 4th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [4] - - // 5th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [5] - 6th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [6] - 7th column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [7] - 8th column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [8] - 9th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [9] - - // 10th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [10] - 11th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [11] - 12th column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [12] - 13th column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [13] - 14th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [14] - - // 15th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [15] - 16th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [23:16] - Internal to - // WTOP Cluster - -#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register. -// -//****************************************************************************** -#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \ - 0x00FFFFFF // SRAM (WTOP+DRP) state during - // Sleep-mode : 1 - SRAMs are RET ; - // 0 - SRAMs are OFF. Cluster - // information : [0] - 1st column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) [1] - 2nd column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [2] - 3rd column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [3] - 4th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [4] - - // 5th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [5] - 6th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [6] - 7th column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [7] - 8th column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [8] - 9th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [9] - - // 10th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [10] - 11th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [11] - 12th column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [12] - 13th column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [13] - 14th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [14] - - // 15th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [15] - 16th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [23:16] - Internal to - // WTOP Cluster - -#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SECURE_INIT_DONE register. -// -//****************************************************************************** -#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \ - 0x00000002 // 1-Secure mode init is done ; - // 0-Secure mode init is not done - -#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \ - 0x00000001 // Must be programmed 1 in order to - // say that secure-mode device init - // is done - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_DEV_MODE_INIT_DONE register. -// -//****************************************************************************** -#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \ - 0x00000001 // 1 - Patch download and other - // initializations are done (before - // removing APPS resetn) for - // development mode (#3) . 0 - - // Development mode (#3) init is not - // done yet - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_EN_APPS_REBOOT register. -// -//****************************************************************************** -#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \ - 0x00000001 // 1 - When 1, disable the reboot - // of APPS after DevInit is - // completed. In this case, APPS - // will permanantly help in reset. 0 - // - When 0, enable the reboot of - // APPS after DevInit is completed. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_APPS_PERIPH_PRESENT register. -// -//****************************************************************************** -#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \ - 0x00010000 // 1 - Enable ; 0 - Disable - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \ - 0x00008000 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \ - 0x00004000 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \ - 0x00002000 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \ - 0x00001000 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \ - 0x00000800 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \ - 0x00000400 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \ - 0x00000200 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \ - 0x00000100 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \ - 0x00000080 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \ - 0x00000040 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \ - 0x00000020 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \ - 0x00000010 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \ - 0x00000008 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \ - 0x00000004 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \ - 0x00000002 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_NWP_PERIPH_PRESENT register. -// -//****************************************************************************** -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \ - 0x00000200 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \ - 0x00000100 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \ - 0x00000080 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \ - 0x00000040 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \ - 0x00000020 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \ - 0x00000010 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \ - 0x00000008 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \ - 0x00000004 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \ - 0x00000002 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register. -// -//****************************************************************************** - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \ - 0x00000040 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \ - 0x00000020 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \ - 0x00000010 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \ - 0x00000008 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \ - 0x00000004 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \ - 0x00000002 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_PWR_STATE register. -// -//****************************************************************************** -#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \ - 0x00000F00 // "0000"- PORZ :- NWP is yet to be - // enabled by APPS during powerup - // (from HIB/OFF) ; "0011"- ACTIVE - // :- NWP is enabled, clocks and - // resets to NWP-SubSystem are - // enabled ; "0010"- LPDS :- NWP is - // in LPDS-mode ; Clocks and reset - // to NWP-SubSystem are gated ; - // "0101"- WAIT_FOR_OPP :- NWP is in - // transition from LPDS to ACTIVE, - // where it is waiting for OPP to be - // stable ; "1000"- - // WAKE_TIMER_OPP_REQ :- NWP is in - // transition from LPDS, where the - // wakeup cause is LPDS_Wake timer - // OTHERS : NA - -#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8 -#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \ - 0x00000007 // "000" - NWP_RUN : NWP is in RUN - // state (default) - Applicable only - // when NWP_PWR_STATE_PS = ACTIVE ; - // "001" - NWP_SLP : NWP is in SLEEP - // state (default) - Applicable only - // when NWP_PWR_STATE_PS = ACTIVE ; - // "010" - NWP_DSLP : NWP is in - // Deep-Sleep state (default) - - // Applicable only when - // NWP_PWR_STATE_PS = ACTIVE ; "011" - // - WAIT_FOR_ACTIVE : NWP is in - // transition from Deep-sleep to - // Run, where it is waiting for OPP - // to be stable ; "100" - - // WAIT_FOR_DSLP_TIMER_WAKE_REQ : - // NWP is in transition from - // Deep-sleep to Run, where the - // wakeup cause is deep-sleep - // wake-timer - -#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_PWR_STATE register. -// -//****************************************************************************** -#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \ - 0x00000F00 // "0000"- PORZ :- APPS is waiting - // for PLL_clock during powerup - // (from HIB/OFF) ; "0011"- ACTIVE - // :- APPS is enabled, clocks and - // resets to APPS-SubSystem are - // enabled ; APPS might be either in - // Secure or Un-secure mode during - // this state. "1001" - - // SECURE_MODE_LPDS :- While in - // ACTIVE (Secure-mode), APPS had to - // program the DevInit_done bit at - // the end, after which it enters - // into this state, where the reset - // to APPS will be asserted. From - // this state APPS might either - // re-boot itself or enter into LPDS - // depending upon whether the device - // is 3200 or 3100. "0010"- LPDS :- - // APPS is in LPDS-mode ; Clocks and - // reset to APPS-SubSystem are gated - // ; "0101"- WAIT_FOR_OPP :- APPS is - // in transition from LPDS to - // ACTIVE, where it is waiting for - // OPP to be stable ; "1000" - - // WAKE_TIMER_OPP_REQ : APPS is in - // transition from LPDS, where the - // wakeup cause is LPDS_Wake timer ; - // "1010" - WAIT_FOR_PATCH_INIT : - // APPS enters into this state - // during development-mode #3 (SOP = - // 3), where it is waiting for patch - // download to complete and 0x4 hack - // is programmed. OTHERS : NA - -#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8 -#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \ - 0x00000007 // "000" - APPS_RUN : APPS is in - // RUN state (default) - Applicable - // only when APPS_PWR_STATE_PS = - // ACTIVE ; "001" - APPS_SLP : APPS - // is in SLEEP state (default) - - // Applicable only when - // APPS_PWR_STATE_PS = ACTIVE ; - // "010" - APPS_DSLP : APPS is in - // Deep-Sleep state (default) - - // Applicable only when - // APPS_PWR_STATE_PS = ACTIVE ; - // "011" - WAIT_FOR_ACTIVE : APPS is - // in transition from Deep-sleep to - // Run, where it is waiting for OPP - // to be stable ; "100" - - // WAIT_FOR_DSLP_TIMER_WAKE_REQ : - // APPS is in transition from - // Deep-sleep to Run, where the - // wakeup cause is deep-sleep - // wake-timer - -#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_PWR_STATE register. -// -//****************************************************************************** -#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \ - 0x0000001F // TBD - -#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WTOP_PM_PS register. -// -//****************************************************************************** -#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \ - 0x00000007 // "011" - WTOP_PM_ACTIVE (Default) - // :- WTOP_Pd is in ACTIVE mode; - // "100" - WTOP_PM_ACTIVE_TO_SLEEP - // :- WTOP_Pd is in transition from - // ACTIVE to SLEEP ; "000" - - // WTOP_PM_SLEEP : WTOP-Pd is in - // Sleep-state ; "100" - - // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd - // is in transition from SLEEP to - // ACTIVE ; "000" - - // WTOP_PM_WAIT_FOR_OPP : Wait for - // OPP to be stable ; - -#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for WTOP PD - // Resetz. When set to 1, - // WTOP_Resetz will be controlled by - // bit [0] - -#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for WTOP PD Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for WELP PD - // Resetz. When set to 1, - // WELP_Resetz will be controlled by - // bit [0] - -#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for WELP PD Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for WL_SDIO - // Resetz. When set to 1, - // WL_SDIO_Resetz will be controlled - // by bit [0] - -#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for WL_SDIO Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for SSDIO - // Resetz. When set to 1, - // SSDIO_Resetz will be controlled - // by bit [0] - -#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for SSDIO Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for MCSPI_N1 - // Resetz. When set to 1, - // MCSPI_N1_Resetz will be - // controlled by bit [0] - -#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for MCSPI_N1 Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for TESTCTRL-PD - // Resetz. When set to 1, - // TESTCTRL_Resetz will be - // controlled by bit [0] - -#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for TESTCTRL Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for MCU-PD - // Resetz. When set to 1, MCU_Resetz - // will be controlled by bit [0] - -#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for MCU Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG0 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \ - 0xFFFFFFFF // This is ROW_14 [31:0] of - // FUSEFARM. [0:0] : XTAL_IS_26MHZ - // [5:1] : TOP_CLKM_RTRIM[4:0] - // [10:6] : ANA_BGAP_MAG_TRIM[4:0] - // [16:11] : ANA_BGAP_TEMP_TRIM[5:0] - // [20:17] : ANA_BGAP_V2I_TRIM[3:0] - // [25:22] : PROCESS INDICATOR - // [26:26] : Reserved [31:27] : - // FUSEROM Version - -#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG1 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \ - 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM - // 1. NWP Peripheral Present bits - // [15:8] NWP_GPT_N0_PP [15:15] - // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP - // [13:13] NWP_UDMA_PP [12:12] - // NWP_UART_N0_PP [11:11] - // NWP_UART_N1_PP [10:10] - // NWP_SSDIO_PP [9:9] - // NWP_MCSPI_N1_PP [8:8] 2. Shared - // Peripheral Present bits [7:0] - // SHARED SPI PP [6:6] - // SHARED I2C PP [5:5] SHARED - // GPIO-A PP [4:4] SHARED GPIO-B PP - // [3:3] SHARED GPIO-C PP [2:2] - // SHARED GPIO-D PP [1:1] SHARED - // GPIO-E PP [0:0] - -#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG2 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \ - 0xFFFFFFFF // This is ROW_16[15:0] & - // ROW_15[31:16] of FUSEFARM. - // [31:21] - Reserved [20:16] - - // CHIP_ID [15:15] - SSBD SOP - // Control [14:14] - SSBD TAP - // Control [13:2] - APPS Peripheral - // Present bits : APPS_CAMERA_PP - // [13:13] APPS_MMCHS_PP [12:12] - // APPS_MCASP_PP [11:11] - // APPS_MCSPI_A1_PP [10:10] - // APPS_MCSPI_A2_PP [9:9] - // APPS_UDMA_PP [8:8] APPS_WDOG_PP - // [7:7] APPS_UART_A0_PP [6:6] - // APPS_UART_A1_PP [5:5] - // APPS_GPT_A0_PP [4:4] - // APPS_GPT_A1_PP [3:3] - // APPS_GPT_A2_PP [2:2] - // APPS_GPT_A3_PP [1:1] [0:0] - NWP - // Peripheral present bits - // NWP_ACSPI_PP [0:0] - -#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG3 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \ - 0xFFFFFFFF // This is ROW_17[15:0] & - // ROW_16[31:16] of FUSEFARM : - // [31:16] - TEST_TAP_KEY(15:0) - // [15:0] - Reserved - -#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WTOP_MEM_RET_CFG register. -// -//****************************************************************************** -#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \ - 0x00000001 // 1 - Soft-compile memories in - // WTOP can be turned-off during - // WTOP-sleep mode ; 0 - - // Soft-compile memories in WTOP - // must be kept on during WTOP-sleep - // mode. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register. -// -//****************************************************************************** -#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \ - 0x007FFFFF // TBD - -#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register. -// -//****************************************************************************** -#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \ - 0x000FFFFF // TBD - -#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register. -// -//****************************************************************************** -#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \ - 0x00000018 - -#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3 -#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \ - 0x00000004 - -#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \ - 0x00000002 - -#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \ - 0x00000001 // TBD - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register. -// -//****************************************************************************** -#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \ - 0x00000001 // 1 - Enable switching of sysclk - // to Coex-clk path ; 0 - Disable - // switching of sysclk to Coex-clk - // path. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_DCDC_CLK_GEN_CONFIG register. -// -//****************************************************************************** -#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \ - 0x00000001 // 1 - Enable the clock for DCDC - // (PWM-mode) ; 0 - Disable the - // clock for DCDC (PWM-mode) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG4 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \ - 0x0000FFFF // This corresponds to - // ROW_17[31:16] of the FUSEFARM : - // [15:0] : TEST_TAP_KEY(31:16) - -#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG5 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \ - 0xFFFFFFFF // Corresponds to ROW_18 of - // FUSEFARM. [29:0] - - // MEMSS_COLUMN_SEL_LSW ; [30:30] - - // WLAN GEM DISABLE ; [31:31] - - // SERIAL WIRE JTAG SELECT - -#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG6 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \ - 0x0000FFFF // Corresponds to ROW_19[15:0] of - // FUSEFARM. [15:0] : - // MEMSS_COLUMN_SEL_MSW - -#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG7 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_20[15:0] & - // ROW_19[31:16] of FUSEFARM. - // FLASH_REGION0 - -#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG8 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_21[15:0] & - // ROW_20[31:16] of FUSEFARM. - // FLASH_REGION1 - -#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG9 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_22[15:0] & - // ROW_21[31:16] of FUSEFARM. - // FLASH_REGION2 - -#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG10 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_23[15:0] & - // ROW_22[31:16] of FUSEFARM. - // FLASH_REGION3 - -#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG11 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_24[15:0] & - // ROW_23[31:16] of FUSEFARM. - // FLASH_DESCRIPTOR - -#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG0 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \ - 0xFFFFFFFF // Corresponds to bits [191:160] of - // the FUSEFARM. This is ROW_5 of - // FUSEFARM [191:160] : [31:0] : - // DIE_ID0 [31:0] : DEVX [11:0] DEVY - // [23:12] DEVWAF [29:24] DEV_SPARE - // [31:30] - -#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG1 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \ - 0xFFFFFFFF // Corresponds to bits [223:192] of - // the FUSEFARM. This is ROW_6 of - // FUSEFARM :- DEVLOT [23:0] DEVFAB - // [28:24] DEVFABBE [31:29] - -#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG2 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \ - 0xFFFFFFFF // Corresponds to bits [255:224] of - // the FUSEFARM. This is ROW_7 of - // FUSEFARM:- DEVDESREV[4:0] - // Memrepair[5:5] MakeDefined[16:6] - // CHECKSUM[30:17] Reserved : - // [31:31] - -#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG3 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \ - 0xFFFFFFFF // Corresponds to bits [287:256] of - // the FUSEFARM. This is ROW_8 of - // FUSEFARM :- DIEID0 - DEVREG - // [31:0] - -#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG4 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \ - 0xFFFFFFFF // Corresponds to bits [319:288] of - // the FUSEFARM. This is ROW_9 of - // FUSEFARM :- [7:0] - VBATMON ; - // [13:8] - BUFF_OFFSET ; [15:15] - - // DFT_GXG ; [14:14] - DFT_GLX ; - // [19:16] - PHY ROM Version ; - // [23:20] - MAC ROM Version ; - // [27:24] - NWP ROM Version ; - // [31:28] - APPS ROM Version - -#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SS_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_APPS_SS_OVERRIDES_reserved_M \ - 0xFFFFFC00 - -#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10 -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \ - 0x00000200 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \ - 0x00000100 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \ - 0x00000080 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \ - 0x00000040 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \ - 0x00000020 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \ - 0x00000010 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \ - 0x00000008 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \ - 0x00000004 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \ - 0x00000002 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_SS_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_NWP_SS_OVERRIDES_reserved_M \ - 0xFFFFFC00 - -#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10 -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \ - 0x00000200 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \ - 0x00000100 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \ - 0x00000080 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \ - 0x00000040 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \ - 0x00000020 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \ - 0x00000010 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \ - 0x00000008 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \ - 0x00000004 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \ - 0x00000002 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SHARED_SS_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \ - 0xFFFFFF00 - -#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8 -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \ - 0x00000080 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \ - 0x00000040 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \ - 0x00000020 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \ - 0x00000010 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \ - 0x00000008 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \ - 0x00000004 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \ - 0x00000002 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \ - 0xFFFFFF00 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8 -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \ - 0x00000080 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \ - 0x00000040 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \ - 0x00000020 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \ - 0x00000010 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \ - 0x00000008 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \ - 0x00000004 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \ - 0x00000002 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TOP_DIE_FSM_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \ - 0xFFFFF000 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12 -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \ - 0x00000800 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \ - 0x00000400 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \ - 0x00000200 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \ - 0x00000100 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \ - 0x00000080 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \ - 0x00000040 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \ - 0x00000020 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \ - 0x00000010 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \ - 0x00000008 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \ - 0x00000004 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \ - 0x00000002 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \ - 0xFFF00000 - -#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20 -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \ - 0x00080000 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \ - 0x00040000 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \ - 0x00020000 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \ - 0x00010000 - -#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \ - 0x0000FC00 - -#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10 -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \ - 0x00000200 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \ - 0x00000100 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \ - 0x000000F0 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4 -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \ - 0x0000000F - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WTOP_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \ - 0xFFC00000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22 -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \ - 0x00200000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \ - 0x00100000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \ - 0x00080000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \ - 0x00040000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \ - 0x00020000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \ - 0x00010000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \ - 0x0000FF00 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8 -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \ - 0x000000FF - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WELP_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \ - 0xFFFFFFFC - -#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2 -#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \ - 0x00000002 - -#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \ - 0xFFFFFFFC - -#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2 -#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \ - 0x00000002 - -#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCSPI_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \ - 0xFFFFFF00 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8 -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \ - 0x00000080 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \ - 0x00000040 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \ - 0x00000020 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \ - 0x00000010 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \ - 0x00000008 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \ - 0x00000004 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \ - 0x00000002 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SSDIO_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \ - 0xFFFFFFFC - -#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2 -#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \ - 0x00000002 - -#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \ - 0x00000001 - - - - -#endif // __HW_GPRCM_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib1p2.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib1p2.h deleted file mode 100755 index 06694512f46..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib1p2.h +++ /dev/null @@ -1,1748 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_HIB1P2_H__ -#define __HW_HIB1P2_H__ - -//***************************************************************************** -// -// The following are defines for the HIB1P2 register offsets. -// -//***************************************************************************** -#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \ - 0x00000000 - -#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \ - 0x00000004 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \ - 0x00000008 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \ - 0x0000000C - -#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \ - 0x00000010 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \ - 0x00000014 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \ - 0x00000018 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \ - 0x0000001C - -#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \ - 0x00000020 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \ - 0x00000024 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \ - 0x00000028 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \ - 0x00000064 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \ - 0x00000068 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \ - 0x0000006C - -#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \ - 0x00000070 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \ - 0x00000074 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \ - 0x00000078 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \ - 0x0000007C - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \ - 0x00000080 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \ - 0x00000084 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \ - 0x00000088 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \ - 0x0000008C - -#define HIB1P2_O_PMBIST_PARAMETERS0 \ - 0x00000094 - -#define HIB1P2_O_PMBIST_PARAMETERS1 \ - 0x00000098 - -#define HIB1P2_O_PMBIST_PARAMETERS2 \ - 0x0000009C - -#define HIB1P2_O_PMBIST_PARAMETERS3 \ - 0x000000A0 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \ - 0x000000A4 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \ - 0x000000A8 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \ - 0x000000AC - -#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \ - 0x000000B0 - -#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \ - 0x000000B4 - -#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \ - 0x000000B8 - -#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \ - 0x000000BC - -#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \ - 0x000000C0 - -#define HIB1P2_O_CM_OSC_16M_CONFIG \ - 0x000000C4 - -#define HIB1P2_O_SOP_SENSE_VALUE \ - 0x000000C8 - -#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \ - 0x000000CC - -#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \ - 0x000000D0 - -#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \ - 0x000000D4 - -#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \ - 0x000000D8 - -#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \ - 0x000000DC - -#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \ - 0x000000E0 - -#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \ - 0x000000E4 - -#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \ - 0x000000E8 - -#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \ - 0x000000EC - -#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \ - 0x000000F0 - -#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \ - 0x000000F4 - -#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \ - 0x000000F8 - -#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \ - 0x000000FC - -#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \ - 0x00000100 - -#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \ - 0x00000104 - -#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \ - 0x00000108 - -#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \ - 0x0000010C - -#define HIB1P2_O_CM_SPARE 0x00000110 -#define HIB1P2_O_PORPOL_SPARE 0x00000114 -#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \ - 0x00000118 - -#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \ - 0x0000011C - -#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \ - 0x00000120 - -#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \ - 0x00000124 - -#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \ - 0x00000128 - -#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \ - 0x0000012C - -#define HIB1P2_O_MEM_HIB_FSM_DEBUG \ - 0x00000130 - -#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \ - 0x00000134 - -#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \ - 0x00000138 - -#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \ - 0x0000013C - -#define HIB1P2_O_MEM_CM_TEST_MODE \ - 0x00000140 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \ - 0xC0000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \ - 0x30000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \ - 0x08000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \ - 0x04000000 // FSM Override value for SLDO_EN : - // Applicable only when bit [4] of - // this register is set to 1. - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \ - 0x02000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \ - 0x01000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \ - 0x00FC0000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \ - 0x0003FF00 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \ - 0x00000080 // FSM Override value for - // SKA_LDO_EN : Applicable only when - // bit [3] of this register is set - // to 1. - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \ - 0x00000040 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \ - 0x00000020 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \ - 0x00000010 // When 1, bit[26] of this register - // will be used as SLDO_EN - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \ - 0x00000008 // When 1, bit[26] of this register - // will be used as SKA_LDO_EN - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \ - 0x00000007 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \ - 0xFFC00000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \ - 0x003F0000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \ - 0x00008000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \ - 0x00004000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \ - 0x00002000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \ - 0x00001000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \ - 0x00000800 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \ - 0x000007FF - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \ - 0x80000000 // Override value for DCDC_DIG_EN : - // Applicable only when bit [31] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. Else from FSM - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \ - 0x40000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \ - 0x20000000 // Override value for - // DCDC_DIG_EN_SUBREG_1P8V : - // Applicable only when bit [30] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. Else from FSM - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \ - 0x10000000 // Override value for - // DCDC_DIG_EN_SUBREG_1P2V : - // Applicable only when bit [29] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. Else from FSM - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \ - 0x08000000 // Override value for - // DCDC_DIG_SLP_EN : Applicable only - // when bit [28] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. Else from FSM - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \ - 0x04000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \ - 0x02000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \ - 0x01000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \ - 0x00800000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \ - 0x00400000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \ - 0x003F0000 // Override value for - // DCDC_DIG_VTRIM : Applicable only - // when bit [27] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16 -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \ - 0x0000C000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14 -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \ - 0x00003000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12 -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \ - 0x00000800 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \ - 0x00000780 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7 -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \ - 0x00000078 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3 -#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \ - 0x00000007 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \ - 0x80000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \ - 0x40000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \ - 0x20000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \ - 0x10000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \ - 0x08000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \ - 0x04000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \ - 0x02000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \ - 0x01FFFFFF - -#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS2 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \ - 0xF0000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \ - 0x0F000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \ - 0x00C00000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \ - 0x00300000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \ - 0x000F0000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16 -#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \ - 0x00008000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \ - 0x00007800 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \ - 0x00000400 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \ - 0x000003FC - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \ - 0x00000002 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \ - 0x00000001 // Override value for - // DCDC_DIG_COT_EN : Applicable only - // when bit[26] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS3 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \ - 0x80000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \ - 0x7F800000 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \ - 0x00400000 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \ - 0x00200000 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \ - 0x001FE000 // Override value for - // DCDC_DIG_ILIM_TRIM : Applicable - // only when bit [25] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \ - 0x00001800 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \ - 0x00000400 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \ - 0x00000200 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \ - 0x000001F0 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \ - 0x0000000C - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \ - 0x00000002 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS4 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \ - 0x80000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \ - 0x40000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \ - 0x20000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \ - 0x1FFFFFFF - -#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS5 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS6 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \ - 0x80000000 // Override for ANA DCDC EN - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \ - 0x40000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \ - 0x20000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \ - 0x10000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \ - 0x08000000 // Override for ANA DCDC PWM - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \ - 0x04000000 // Override for ANA DCDC SLP - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \ - 0x02000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \ - 0x01000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \ - 0x00800000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \ - 0x00400000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \ - 0x00200000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \ - 0x001E0000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \ - 0x00018000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \ - 0x00006000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \ - 0x00001000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \ - 0x00000F00 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \ - 0x000000F0 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \ - 0x0000000F - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \ - 0xF0000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \ - 0x0C000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \ - 0x03000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \ - 0x00F00000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \ - 0x000F0000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \ - 0x00008000 // (Earlier SHOOTTHRU CTRL) - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \ - 0x00004000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \ - 0x00003E00 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \ - 0x00000100 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \ - 0x00000080 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \ - 0x00000060 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \ - 0x00000010 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \ - 0x0000000C - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2 -#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \ - 0x00000003 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS16 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \ - 0x00200000 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \ - 0x00100000 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \ - 0x000FF000 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12 -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \ - 0x00000C00 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10 -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \ - 0x00000200 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \ - 0x00000100 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \ - 0x000000F8 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3 -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \ - 0x00000006 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1 -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS17 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \ - 0x80000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \ - 0x40000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \ - 0x3FFFFFFF - -#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS18 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS19 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \ - 0x80000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \ - 0x40000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \ - 0x20000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \ - 0x18000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27 -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \ - 0x04000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \ - 0x02000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \ - 0x01000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \ - 0x00800000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \ - 0x00400000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \ - 0x003C0000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18 -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \ - 0x00020000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \ - 0x00010000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \ - 0x00008000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \ - 0x00004000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \ - 0x00002000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \ - 0x00001000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \ - 0x00000800 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \ - 0x00000400 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \ - 0x00000200 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \ - 0x000001E0 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5 -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \ - 0x0000001E - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1 -#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \ - 0xF0000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \ - 0x0F000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \ - 0x00F00000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \ - 0x000F0000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \ - 0x0000F000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \ - 0x00000F00 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \ - 0x000000C0 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \ - 0x00000030 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \ - 0x0000000C - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \ - 0x00000003 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \ - 0xC0000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \ - 0x30000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \ - 0x0C000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \ - 0x03000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \ - 0x00800000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \ - 0x00400000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \ - 0x00200000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \ - 0x001F0000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \ - 0x0000F000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \ - 0x00000800 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \ - 0x00000400 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \ - 0x000003FC - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \ - 0x00000003 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \ - 0x80000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \ - 0x40000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \ - 0x20000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \ - 0x1F000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \ - 0x00E00000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \ - 0x001C0000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \ - 0x0003C000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \ - 0x00003C00 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \ - 0x00000300 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \ - 0x00000080 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \ - 0x00000040 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \ - 0x00000020 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \ - 0x0000001F - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \ - 0x80000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \ - 0x40000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \ - 0x3FFFFFFF - -#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PMBIST_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \ - 0x80000000 - -#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \ - 0x7FFFF800 - -#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11 -#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \ - 0x000007FF - -#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PMBIST_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \ - 0xFFFF0000 - -#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16 -#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \ - 0x00008000 - -#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \ - 0x00007FFF - -#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PMBIST_PARAMETERS2 register. -// -//****************************************************************************** -#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PMBIST_PARAMETERS3 register. -// -//****************************************************************************** -#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \ - 0xFFFF0000 - -#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16 -#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \ - 0x0000E000 - -#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13 -#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \ - 0x00001000 - -#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \ - 0x00000FFF - -#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \ - 0x80000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \ - 0x7C000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26 -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \ - 0x03E00000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21 -#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \ - 0x001FFFFF - -#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \ - 0xFFFFFFC0 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6 -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \ - 0x00000020 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \ - 0x00000010 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \ - 0x00000008 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \ - 0x00000004 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \ - 0x00000002 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \ - 0xFFFFFFFC - -#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2 -#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \ - 0x00000002 - -#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_VTRIM_CFG register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \ - 0xFF000000 - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24 -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \ - 0x00FC0000 - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18 -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \ - 0x0003F000 - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12 -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \ - 0x00000FC0 - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6 -#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \ - 0x0000003F - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \ - 0xFFFF8000 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \ - 0x00007000 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \ - 0x00000E00 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \ - 0x000001C0 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \ - 0x00000038 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \ - 0x00000007 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \ - 0xFFFFFFF8 - -#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3 -#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \ - 0x00000007 - -#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register. -// -//****************************************************************************** -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \ - 0xFFFFFFC0 - -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6 -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \ - 0x00000038 - -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3 -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \ - 0x00000007 - -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register. -// -//****************************************************************************** -#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \ - 0xFFFFFFF8 - -#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3 -#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \ - 0x00000007 - -#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_CM_OSC_16M_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \ - 0xFFFC0000 - -#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18 -#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \ - 0x00020000 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \ - 0x00010000 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \ - 0x0000FC00 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10 -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \ - 0x000003F0 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4 -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \ - 0x00000008 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \ - 0x00000007 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_SOP_SENSE_VALUE register. -// -//****************************************************************************** -#define HIB1P2_SOP_SENSE_VALUE_reserved_M \ - 0xFFFFFF00 - -#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8 -#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \ - 0x000000FF - -#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register. -// -//****************************************************************************** -#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register. -// -//****************************************************************************** -#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \ - 0x0000FFFF - -#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register. -// -//****************************************************************************** -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \ - 0xFF800000 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23 -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \ - 0x00400000 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \ - 0x003FC000 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14 -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \ - 0x00002000 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \ - 0x00001FC0 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6 -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \ - 0x00000020 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \ - 0x0000001F - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register. -// -//****************************************************************************** -#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \ - 0xFFFFFFFF // Corresponds to ROW_12 of - // FUSEFARM. [7:0] : - // DCDC_DIG_ILIM_TRIM_LOWV(7:0) - // [15:8] : - // DCDC_ANA_ILIM_TRIM_LOWV(7:0) - // [23:16] : - // DCDC_FLASH_ILIM_TRIM_LOWV(7:0) - // [24:24] : DTHE SHA DISABLE - // [25:25] : DTHE DES DISABLE - // [26:26] : DTHE AES DISABLE - // [31:27] : HD_BG_RTRIM (4:0) - -#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register. -// -//****************************************************************************** -#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \ - 0xFFFFFFFF // Corresponds to ROW_13 of the - // FUSEFARM. [7:0] : HD_BG_MAG_TRIM - // (7:0) [14:8] : HD_BG_TEMP_TRIM - // (6:0) [15:15] : GREYOUT ENABLE - // DUTY CYCLING [31:16] : - // Reserved/Checksum - -#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB1P2_POR_TEST_CTRL register. -// -//****************************************************************************** -#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \ - 0xFFFFFF00 - -#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8 -#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \ - 0x000000FF - -#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \ - 0xFFFF0000 - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16 -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \ - 0x0000FF00 - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8 -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \ - 0x000000FE - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1 -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \ - 0xFFF00000 - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20 -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \ - 0x000FFFFF - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \ - 0xFFFFFE00 - -#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9 -#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \ - 0x00000100 - -#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \ - 0x000000FC - -#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2 -#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \ - 0x00000002 - -#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \ - 0xFFFF0000 - -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16 -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \ - 0x0000FFFF - -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \ - 0xFFFF0000 - -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16 -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \ - 0x0000FFFF - -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \ - 0xFFFFF000 - -#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12 -#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \ - 0x00000FFF - -#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register. -// -//****************************************************************************** -#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \ - 0xFF000000 - -#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24 -#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \ - 0x00FF0000 - -#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16 -#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \ - 0x0000FFFF - -#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PORPOL_SPARE register. -// -//****************************************************************************** -#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \ - 0xFFFFFFFF - -#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \ - 0x00000100 - -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \ - 0x000000F0 - -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4 -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \ - 0x0000000F - -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \ - 0x00000100 - -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \ - 0x000000F0 - -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \ - 0x0000000F - -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \ - 0x00000100 - -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \ - 0x000000F0 - -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4 -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \ - 0x0000000F - -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \ - 0x00000100 - -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \ - 0x000000F0 - -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \ - 0x0000000F - -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register. -// -//****************************************************************************** -#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \ - 0x00000002 - -#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register. -// -//****************************************************************************** -#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \ - 0x00000002 - -#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_HIB_FSM_DEBUG register. -// -//****************************************************************************** -#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \ - 0x00000700 - -#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8 -#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \ - 0x000000F0 - -#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4 -#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \ - 0x0000000F - -#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register. -// -//****************************************************************************** -#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \ - 0x000FFFFF - -#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register. -// -//****************************************************************************** -#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register. -// -//****************************************************************************** -#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \ - 0x00000002 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_CM_TEST_MODE register. -// -//****************************************************************************** -#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \ - 0x00000001 - - - - -#endif // __HW_HIB1P2_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib3p3.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib3p3.h deleted file mode 100755 index 93c385e761e..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib3p3.h +++ /dev/null @@ -1,1136 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_HIB3P3_H__ -#define __HW_HIB3P3_H__ - -//***************************************************************************** -// -// The following are defines for the HIB3P3 register offsets. -// -//***************************************************************************** -#define HIB3P3_O_MEM_HIB_REQ 0x00000000 -#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \ - 0x00000004 - -#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \ - 0x00000008 - -#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \ - 0x0000000C - -#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \ - 0x00000010 - -#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \ - 0x00000014 - -#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \ - 0x00000018 - -#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \ - 0x0000001C - -#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \ - 0x00000020 - -#define HIB3P3_O_MEM_INT_OSC_CONF \ - 0x0000002C - -#define HIB3P3_O_MEM_XTAL_OSC_CONF \ - 0x00000034 - -#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \ - 0x00000038 - -#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \ - 0x0000003C - -#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \ - 0x00000040 - -#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \ - 0x00000044 - -#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050 -#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \ - 0x00000054 - -#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \ - 0x00000058 - -#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \ - 0x0000005C - -#define HIB3P3_O_MEM_HIB_UART_CONF \ - 0x00000400 - -#define HIB3P3_O_MEM_GPIO_WAKE_EN \ - 0x00000404 - -#define HIB3P3_O_MEM_GPIO_WAKE_CONF \ - 0x00000408 - -#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \ - 0x0000040C - -#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \ - 0x00000410 - -#define HIB3P3_O_MEM_JTAG_CONF 0x00000414 -#define HIB3P3_O_MEM_HIB_REG0 0x00000418 -#define HIB3P3_O_MEM_HIB_REG1 0x0000041C -#define HIB3P3_O_MEM_HIB_REG2 0x00000420 -#define HIB3P3_O_MEM_HIB_REG3 0x00000424 -#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \ - 0x0000045C - -#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \ - 0x00000460 - -#define HIB3P3_O_MEM_HIB_MISC_CONFIG \ - 0x00000464 - -#define HIB3P3_O_MEM_HIB_WAKE_STATUS \ - 0x00000468 - -#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \ - 0x0000046C - -#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \ - 0x00000470 - -#define HIB3P3_O_HIBANA_SPARE_LOWV \ - 0x00000474 - -#define HIB3P3_O_HIB_TMUX_CTRL 0x00000478 -#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \ - 0x0000047C - -#define HIB3P3_O_HIB_COMP_TRIM 0x00000480 -#define HIB3P3_O_HIB_EN_TS 0x00000484 -#define HIB3P3_O_HIB_1P8V_DET_EN \ - 0x00000488 - -#define HIB3P3_O_HIB_VBAT_MON_EN \ - 0x0000048C - -#define HIB3P3_O_HIB_NHIB_ENABLE \ - 0x00000490 - -#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \ - 0x00000494 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REQ register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REQ_reserved_M \ - 0xFFFFFE00 - -#define HIB3P3_MEM_HIB_REQ_reserved_S 9 -#define HIB3P3_MEM_HIB_REQ_NU1_M \ - 0x000001FC - -#define HIB3P3_MEM_HIB_REQ_NU1_S 2 -#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \ - 0x00000002 // 1 - Specifies that the Hiberante - // mode is without clocks ; 0 - - // Specified that the Hibernate mode - // is with clocks This register will - // be reset during Hibernate - // -WO-Clks mode (but not during - // Hibernate-W-Clks mode). - -#define HIB3P3_MEM_HIB_REQ_mem_hib_req \ - 0x00000001 // 1 - Request for hibernate mode - // (This is an auto-clear bit) ; 0 - - // Donot request for hibernate mode - // This register will be reset - // during Hibernate -WO-Clks mode - // (but not during Hibernate-W-Clks - // mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1 -#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \ - 0x00000001 // 1 - Enable the RTC timer to - // start running ; 0 - Keep the RTC - // timer disabled This register will - // be reset during Hibernate - // -WO-Clks mode (but not during - // Hibernate-W-Clks mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1 -#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \ - 0x00000001 // 1 - Reset the RTC timer ; 0 - - // Donot reset the RTC timer. This - // is an auto-clear bit. This - // register will be reset during - // Hibernate -WO-Clks mode (but not - // during Hibernate-W-Clks mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1 -#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \ - 0x00000001 // 1 - Latch the running RTC timer - // into local registers. After - // programming this bit to 1, the - // F/w can read the latched RTC - // timer values from - // MEM_HIB_RTC_TIMER_LSW and - // MEM_HIB_RTC_TIMER_MSW. Before the - // F/w (APPS or NWP) wants to read - // the RTC-Timer, it has to program - // this bit to 1, then only read the - // MSW and LSW values. This is an - // auto-clear bit. This register - // will be reset during Hibernate - // -WO-Clks mode (but not during - // Hibernate-W-Clks mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \ - 0xFFFFFFFF // Lower 32b value of the latched - // RTC-Timer. - -#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16 -#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \ - 0x0000FFFF // Upper 32b value of the latched - // RTC-Timer. - -#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1 -#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \ - 0x00000001 // 1 - Enable the RTC timer based - // wakeup during Hibernate mode ; 0 - // - Disable the RTC timer based - // wakeup during Hibernate mode This - // register will be reset during - // Hibernate-WO-Clks mode (but not - // during Hibernate-W-Clks mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \ - 0xFFFFFFFF // Configuration for RTC-Timer - // Wakeup (Lower 32b word) - -#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16 -#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \ - 0x0000FFFF // Configuration for RTC-Timer - // Wakeup (Upper 16b word) - -#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_INT_OSC_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16 -#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \ - 0x00008000 // 1 - Internal 32kHz Oscillator is - // valid ; 0 - Internal 32k - // oscillator clk is not valid - -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \ - 0x00007E00 - -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9 -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \ - 0x00000100 // When 1, the INT_32K_OSC_EN comes - // from bit [0] of this register, - // else comes from the FSM. This - // register will be reset during - // Hibernate-WO-Clks mode (but not - // during Hibernate-W-Clks mode) - -#define HIB3P3_MEM_INT_OSC_CONF_NU1 \ - 0x00000080 - -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \ - 0x0000007E - -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1 -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \ - 0x00000001 // Override value for INT_OSC_EN. - // Applicable only when bit [3] of - // this register is set to 1. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_XTAL_OSC_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \ - 0xFFF00000 - -#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \ - 0x00080000 // When 1, the SLICER_EN comes from - // bit [10] of this register, else - // comes from the FSM. - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \ - 0x00040000 // When 1, the XTAL_EN comes from - // bit [0] of this register, else - // comes from the FSM. - -#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \ - 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL - // Clk is yet to be valid. - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \ - 0x0001F800 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \ - 0x00000400 // SLICER_EN Override value : - // Applicable only when bit [19] of - // this register is set to 1. - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \ - 0x00000380 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \ - 0x00000070 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \ - 0x00000008 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \ - 0x00000006 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \ - 0x00000001 // XTAL_EN Override value : - // Applicable only when bit [18] of - // this register is set to 1. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_BGAP_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \ - 0xFFF80000 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19 -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \ - 0x00040000 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \ - 0x0001C000 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14 -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \ - 0x00001000 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \ - 0x00000800 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \ - 0x00000400 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \ - 0x000003FF - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_BGAP_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \ - 0xE0000000 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29 -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \ - 0x1F000000 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24 -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \ - 0x00000008 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \ - 0x00000004 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \ - 0x00000002 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_DETECTION_STATUS register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \ - 0xFFFFFF80 - -#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7 -#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \ - 0x00000040 // 1 - 1.8 V supply forced mode. - -#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \ - 0x00000004 // 1 - 3.3 V supply forced mode for - // Flash supply - -#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \ - 0x00000002 // 1 - Forced clock mode - -#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \ - 0x00000001 // 1 - XTAL clock mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_MISC_CONTROLS register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \ - 0xFFFFF800 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11 -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \ - 0x00000400 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \ - 0x00000200 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \ - 0x000001C0 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6 -#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \ - 0x00000020 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \ - 0x00000010 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_CONFIG register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \ - 0xFF000000 - -#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24 -#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \ - 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD - // for digital path (SHARED4) ; 0 - - // Disable VDD_FLASH_INDP_PAD for - // digital path (SHARED4) ; Before - // programming this bit to 1, ensure - // that the device is in FORCED 3.3 - // supply Mode, which can be - // inferred from the register : - // MEM_HIB_DETECTION_STATUS : 0x0040 - -#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \ - 0x00040000 // 1 - Enable the - // VDD_FB_GPIO_MUX_PAD for digital - // path (SHARED3) ; 0 - Disable the - // VDD_FB_GPIO_MUX_PAD for digital - // path (SHARED3) ; This pin can be - // used only in modes other than - // SOP("111") - -#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \ - 0x00020000 // 1 - Enable the PM_TEST_PAD for - // digital GPIO path (SHARED2) ; 0 - - // Disable the PM_TEST_PAD for - // digital GPIO path (SHARED2) This - // pin can be used for digital only - // in modes other then SOP-111 - -#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \ - 0x00010000 // 1 - Enable the XTAL_N pin - // digital GPIO path (SHARED1); 0 - - // Disable the XTAL_N pin digital - // GPIO path (SHARED1). Before - // programming this bit to 1, ensure - // that the device is in FORCED CLK - // Mode, which can inferred from the - // register : - // MEM_HIB_DETECTION_STATUS : - // 0x0040. - -#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \ - 0x00000100 // 1 - Enable the XTAL Clock ; 0 - - // Donot enable the XTAL Clock. This - // bit has to be programmed to 1 (by - // APPS Devinit F/w), during exit - // from OFF or Hib_wo_clks modes, - // after checking if the slow_clk - // mode is XTAL_CLK mode. Once - // enabled the XTAL will be disabled - // only after entering HIB_WO_CLKS - // mode. This register will be reset - // during Hibernate -WO-Clks mode - // (but not during Hibernate-W-Clks - // mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \ - 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0 - // - Disable the HIB RTC - IRQ - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \ - 0xFFFFFFFF // Configuration for LSW of the - // RTC-Timestamp at which interrupt - // need to be generated - -#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \ - 0x0000FFFF // Configuration for MSW of thr - // RTC-Timestamp at which the - // interrupt need to be generated - -#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_UART_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1 -#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \ - 0x00000001 // 1 - Enable the UART-Autonomous - // mode wakeup during Hibernate mode - // ; This is an auto-clear bit, once - // programmed to 1, it will latched - // into an internal register which - // remain asserted until the - // Hib-wakeup is initiated. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_GPIO_WAKE_EN register. -// -//****************************************************************************** -#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \ - 0xFFFFFF00 - -#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8 -#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \ - 0x000000FF // 1 - Enable the GPIO-Autonomous - // mode wakeup during Hibernate mode - // ; This is an auto-clear bit, once - // programmed to 1, it will latched - // into an internal register which - // remain asserted until the - // Hib-wakeup is initiated. - -#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_GPIO_WAKE_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16 -#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \ - 0x0000FFFF // Configuration to say whether the - // GPIO wakeup has to happen on - // Level0 or falling-edge for the - // given group. “00�? – Level0 “01�? – - // Level1 “10�?- Fall-edge “11�?- - // Rise-edge [1:0] – Conf for GPIO0 - // [3:2] – Conf for GPIO1 [5:4] – - // Conf for GPIO2 [7:6] – Conf for - // GPIO3 [9:8] – Conf for GPIO4 - // [11:10] – Conf for GPIO5 [13:12] - // – Conf for GPIO6 - -#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \ - 0x00000004 // 1 - Override the OEN33 and RET33 - // controls of GPIOs during - // SOP-Bootdebug mode ; 0 - Donot - // override the OEN33 and RET33 - // controls of GPIOs during - // SOP-Bootdebug mode - -#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \ - 0x00000002 - -#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \ - 0x00000004 // 1 - Override the OEN33 and RET33 - // controls of UART NRTS GPIO during - // SOP-Bootdebug mode ; 0 - Donot - // override the OEN33 and RET33 - // controls of UART NRTS GPIO during - // SOP-Bootdebug mode - -#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \ - 0x00000002 - -#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_JTAG_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \ - 0x00000200 - -#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \ - 0x00000100 - -#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \ - 0x00000008 - -#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \ - 0x00000004 - -#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \ - 0x00000002 - -#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REG0 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \ - 0xFFFFFFFF - -#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REG1 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \ - 0xFFFFFFFF - -#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REG2 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \ - 0xFFFFFFFF - -#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REG3 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \ - 0xFFFFFFFF - -#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \ - 0xFFFF0000 // Configuration for the number of - // slow-clks between de-assertion of - // EN_BG_3P3V to assertion of - // EN_BG_3P3V - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \ - 0x00008000 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \ - 0x00006000 // Configuration for the number of - // slow-clks between assertion of - // EN_COMP_3P3V and assertion of - // EN_COMP_LATCH_3P3V - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \ - 0x00001800 // Configuration for the number of - // slow-clks between assertion of - // (EN_CAP_SW_3P3V,EN_COMP_REF) and - // assertion of (EN_COMP_3P3V) - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \ - 0x00000600 // Configuration for the number of - // slow-clks between assertion of - // (EN_BG_3P3V) and assertion of - // (EN_CAP_SW_3P3V, - // EN_COMP_REF_3P3V) - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \ - 0x00000100 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \ - 0x00000080 // 1 - EN_VBOK4BG_REF comes from - // bit[10] of the register - // MEM_BGAP_PARAMETERS0 [0x0038]. 0 - // - EN_VBOK4BG_REF comes directly - // from the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \ - 0x00000040 // 1 - EN_VBOK4BG comes from - // bit[11] of the register - // MEM_BGAP_PARAMETERS0 [0x0038]. 0 - // - EN_VBOK4BG comes directly from - // the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \ - 0x00000020 // 1 - EN_V2I comes from bit[2] of - // the register MEM_BGAP_PARAMETERS1 - // [0x003C]. 0 - EN_V2I comes - // directly from the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \ - 0x00000010 // 1 - EN_POR_COMP_REF comes from - // bit[9] of the register - // MEM_HIB_MISC_CONTROLS [0x0044]. 0 - // - EN_POR_COMP_REF comes directly - // from the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \ - 0x00000008 // 1 - EN_POR_COMP comes from - // bit[10] of the register - // MEM_HIB_MISC_CONTROLS [0x044]. 0 - // - EN_POR_COMP comes directly from - // the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \ - 0x00000004 // 1 - EN_CAP_SW comes from bit[1] - // of the register - // MEM_BGAP_PARAMETERS1 [0x003C]. 0 - // - EN_CAP_SW comes directly from - // Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \ - 0x00000002 // 1 - EN_BGAP comes from bit[0] of - // the register MEM_BGAP_PARAMETERS1 - // [0x003C]. 0 - EN_BGAP comes - // directly from Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \ - 0x0000C000 // Configuration for number of - // slow-clks between de-assertion of - // EN_COMP_LATCH and assertion of - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \ - 0x00003000 // Configuration for number of - // slow-clks between assertion of - // EN_COMP_REF to assertion of - // EN_COMP during HIB-Exit - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \ - 0x00000C00 // TBD - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \ - 0x00000300 // Configuration in number of - // slow-clks between assertion of - // (EN_BGAP_3P3V, EN_CAP_SW_3P3V, - // EN_ACT_IREF_3P3V, EN_COMP_REF) to - // assertion of EN_COMP_3P3V - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \ - 0x000000C0 // Configuration in number of - // slow-clks between de-assertion of - // (EN_COMP_3P3V, EN_COMP_REF_3P3V, - // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V) - // to deassertion of EN_BGAP_3P3V. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \ - 0x0000003F - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_MISC_CONFIG register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_WAKE_STATUS register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \ - 0x0000001E // "0100" - GPIO ; "0010" - RTC ; - // "0001" - UART Others - Reserved - -#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1 -#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \ - 0x00000001 // 1 - Wake from Hibernate ; 0 - - // Wake from OFF - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \ - 0x00000007 - -#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \ - 0xFFFFF800 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \ - 0x00000600 // Deassertion of EN_COMP_LATCH_3P3 - // to deassertion of (EN_COMP_3P3, - // EN_COMP_REF_3P3, EN_ACT_IREF_3P3, - // EN_CAP_SW_3P3) - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \ - 0x000001C0 // Assertion of EN_COMP_LATCH_3P3 - // to deassertion of - // EN_COMP_LATCH_3P3 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \ - 0x00000030 // Deassertion of (EN_CAP_SW_3P3, - // EN_COMP_REF_3P3, EN_COMP_3P3, - // EN_COMP_OUT_LATCH_3P3) to - // deassertion of EN_BGAP_3P3 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \ - 0x0000000C // Assertion of EN_COMP_3P3 to - // assertion of EN_COMPOUT_LATCH_3P3 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \ - 0x00000003 // Assertion of EN_COMP_3P3 to - // assertion of EN_COMPOUT_LATCH_3P3 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIBANA_SPARE_LOWV register. -// -//****************************************************************************** -#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \ - 0xFFC00000 - -#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22 -#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \ - 0x0001FFFF - -#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_TMUX_CTRL register. -// -//****************************************************************************** -#define HIB3P3_HIB_TMUX_CTRL_reserved_M \ - 0xFFFFFC00 - -#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10 -#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \ - 0x000003FF - -#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register. -// -//****************************************************************************** -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \ - 0xFFFFF000 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12 -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \ - 0x00000800 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \ - 0x00000400 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \ - 0x00000200 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \ - 0x00000100 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \ - 0x000000F0 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4 -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \ - 0x0000000F - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_COMP_TRIM register. -// -//****************************************************************************** -#define HIB3P3_HIB_COMP_TRIM_reserved_M \ - 0xFFFFFFF8 - -#define HIB3P3_HIB_COMP_TRIM_reserved_S 3 -#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \ - 0x00000007 - -#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_EN_TS register. -// -//****************************************************************************** -#define HIB3P3_HIB_EN_TS_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_HIB_EN_TS_reserved_S 1 -#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_1P8V_DET_EN register. -// -//****************************************************************************** -#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1 -#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_VBAT_MON_EN register. -// -//****************************************************************************** -#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \ - 0xFFFFFFFC - -#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2 -#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \ - 0x00000002 - -#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_NHIB_ENABLE register. -// -//****************************************************************************** -#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register. -// -//****************************************************************************** -#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \ - 0x00000001 - - - - -#endif // __HW_HIB3P3_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_i2c.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_i2c.h deleted file mode 100755 index 5a8246a615f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_i2c.h +++ /dev/null @@ -1,501 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following are defines for the I2C register offsets. -// -//***************************************************************************** -#define I2C_O_MSA 0x00000000 -#define I2C_O_MCS 0x00000004 -#define I2C_O_MDR 0x00000008 -#define I2C_O_MTPR 0x0000000C -#define I2C_O_MIMR 0x00000010 -#define I2C_O_MRIS 0x00000014 -#define I2C_O_MMIS 0x00000018 -#define I2C_O_MICR 0x0000001C -#define I2C_O_MCR 0x00000020 -#define I2C_O_MCLKOCNT 0x00000024 -#define I2C_O_MBMON 0x0000002C -#define I2C_O_MBLEN 0x00000030 -#define I2C_O_MBCNT 0x00000034 -#define I2C_O_SOAR 0x00000800 -#define I2C_O_SCSR 0x00000804 -#define I2C_O_SDR 0x00000808 -#define I2C_O_SIMR 0x0000080C -#define I2C_O_SRIS 0x00000810 -#define I2C_O_SMIS 0x00000814 -#define I2C_O_SICR 0x00000818 -#define I2C_O_SOAR2 0x0000081C -#define I2C_O_SACKCTL 0x00000820 -#define I2C_O_FIFODATA 0x00000F00 -#define I2C_O_FIFOCTL 0x00000F04 -#define I2C_O_FIFOSTATUS 0x00000F08 -#define I2C_O_OBSMUXSEL0 0x00000F80 -#define I2C_O_OBSMUXSEL1 0x00000F84 -#define I2C_O_MUXROUTE 0x00000F88 -#define I2C_O_PV 0x00000FB0 -#define I2C_O_PP 0x00000FC0 -#define I2C_O_PC 0x00000FC4 -#define I2C_O_CC 0x00000FC8 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MSA register. -// -//****************************************************************************** -#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address -#define I2C_MSA_SA_S 1 -#define I2C_MSA_RS 0x00000001 // Receive not send -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCS register. -// -//****************************************************************************** -#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error -#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy -#define I2C_MCS_IDLE 0x00000020 // I2C Idle -#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost -#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable -#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address -#define I2C_MCS_ERROR 0x00000002 // Error -#define I2C_MCS_BUSY 0x00000001 // I2C Busy -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MDR register. -// -//****************************************************************************** -#define I2C_MDR_DATA_M 0x000000FF // Data Transferred -#define I2C_MDR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MTPR register. -// -//****************************************************************************** -#define I2C_MTPR_HS 0x00000080 // High-Speed Enable -#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period -#define I2C_MTPR_TPR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MIMR register. -// -//****************************************************************************** -#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt - // Mask -#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask -#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask -#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask -#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask -#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MRIS register. -// -//****************************************************************************** -#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt - // Status -#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt - // Status -#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt - // Status -#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt - // Status -#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt - // Status -#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt - // Status -#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status -#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt - // Status -#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MMIS register. -// -//****************************************************************************** -#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask -#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask -#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status -#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status -#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt - // Status -#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MICR register. -// -//****************************************************************************** -#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt - // Clear -#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt - // Clear -#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt - // Clear -#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt - // Clear -#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear -#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear -#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear -#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt - // Clear -#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear -#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear -#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear -#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR register. -// -//****************************************************************************** -#define I2C_MCR_MMD 0x00000040 // Multi-master Disable -#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable -#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable -#define I2C_MCR_LPBK 0x00000001 // I2C Loopback -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. -// -//****************************************************************************** -#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count -#define I2C_MCLKOCNT_CNTL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBMON register. -// -//****************************************************************************** -#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status -#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBLEN register. -// -//****************************************************************************** -#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length -#define I2C_MBLEN_CNTL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBCNT register. -// -//****************************************************************************** -#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count -#define I2C_MBCNT_CNTL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR register. -// -//****************************************************************************** -#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address -#define I2C_SOAR_OAR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SCSR register. -// -//****************************************************************************** -#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write -#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status -#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched -#define I2C_SCSR_FBR 0x00000004 // First Byte Received -#define I2C_SCSR_TREQ 0x00000002 // Transmit Request -#define I2C_SCSR_DA 0x00000001 // Device Active -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SDR register. -// -//****************************************************************************** -#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer -#define I2C_SDR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SIMR register. -// -//****************************************************************************** -#define I2C_SIMR_IM 0x00000100 // Interrupt Mask -#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask -#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask -#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask -#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask -#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SRIS register. -// -//****************************************************************************** -#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status -#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt - // Status -#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt - // Status -#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status -#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt - // Status -#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt - // Status -#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SMIS register. -// -//****************************************************************************** -#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt - // Status -#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt - // Status -#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt - // Status -#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt - // Status -#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SICR register. -// -//****************************************************************************** -#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask -#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask -#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear -#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear -#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear -#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear -#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR2 register. -// -//****************************************************************************** -#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable -#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 -#define I2C_SOAR2_OAR2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SACKCTL register. -// -//****************************************************************************** -#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value -#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFODATA register. -// -//****************************************************************************** -#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte -#define I2C_FIFODATA_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOCTL register. -// -//****************************************************************************** -#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment -#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush -#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable -#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger -#define I2C_FIFOCTL_RXTRIG_S 16 -#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment -#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush -#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable -#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger -#define I2C_FIFOCTL_TXTRIG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register. -// -//****************************************************************************** -#define I2C_FIFOSTATUS_RXABVTRIG \ - 0x00040000 // RX FIFO Above Trigger Level - -#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full -#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty -#define I2C_FIFOSTATUS_TXBLWTRIG \ - 0x00000004 // TX FIFO Below Trigger Level - -#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full -#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register. -// -//****************************************************************************** -#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3 -#define I2C_OBSMUXSEL0_LN3_S 24 -#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2 -#define I2C_OBSMUXSEL0_LN2_S 16 -#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1 -#define I2C_OBSMUXSEL0_LN1_S 8 -#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0 -#define I2C_OBSMUXSEL0_LN0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register. -// -//****************************************************************************** -#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7 -#define I2C_OBSMUXSEL1_LN7_S 24 -#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6 -#define I2C_OBSMUXSEL1_LN6_S 16 -#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5 -#define I2C_OBSMUXSEL1_LN5_S 8 -#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4 -#define I2C_OBSMUXSEL1_LN4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MUXROUTE register. -// -//****************************************************************************** -#define I2C_MUXROUTE_LN7ROUTE_M \ - 0x70000000 // Lane 7 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN7ROUTE_S 28 -#define I2C_MUXROUTE_LN6ROUTE_M \ - 0x07000000 // Lane 6 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN6ROUTE_S 24 -#define I2C_MUXROUTE_LN5ROUTE_M \ - 0x00700000 // Lane 5 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN5ROUTE_S 20 -#define I2C_MUXROUTE_LN4ROUTE_M \ - 0x00070000 // Lane 4 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN4ROUTE_S 16 -#define I2C_MUXROUTE_LN3ROUTE_M \ - 0x00007000 // Lane 3 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN3ROUTE_S 12 -#define I2C_MUXROUTE_LN2ROUTE_M \ - 0x00000700 // Lane 2 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN2ROUTE_S 8 -#define I2C_MUXROUTE_LN1ROUTE_M \ - 0x00000070 // Lane 1 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN1ROUTE_S 4 -#define I2C_MUXROUTE_LN0ROUTE_M \ - 0x00000007 // Lane 0 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN0ROUTE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PV register. -// -//****************************************************************************** -#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision -#define I2C_PV_MAJOR_S 8 -#define I2C_PV_MINOR_M 0x000000FF // Minor Revision -#define I2C_PV_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PP register. -// -//****************************************************************************** -#define I2C_PP_HS 0x00000001 // High-Speed Capable -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PC register. -// -//****************************************************************************** -#define I2C_PC_HS 0x00000001 // High-Speed Capable -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_CC register. -// -//****************************************************************************** - - - -#endif // __HW_I2C_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ints.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ints.h deleted file mode 100755 index 59da049796a..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ints.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on CC3200. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following are defines for the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following are defines for the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA0 16 // GPIO Port S0 -#define INT_GPIOA1 17 // GPIO Port S1 -#define INT_GPIOA2 18 // GPIO Port S2 -#define INT_GPIOA3 19 // GPIO Port S3 -#define INT_UARTA0 21 // UART0 Rx and Tx -#define INT_UARTA1 22 // UART1 Rx and Tx -#define INT_I2CA0 24 // I2C controller -#define INT_ADCCH0 30 // ADC Sequence 0 -#define INT_ADCCH1 31 // ADC Sequence 1 -#define INT_ADCCH2 32 // ADC Sequence 2 -#define INT_ADCCH3 33 // ADC Sequence 3 -#define INT_WDT 34 // Watchdog Timer0 -#define INT_TIMERA0A 35 // Timer 0 subtimer A -#define INT_TIMERA0B 36 // Timer 0 subtimer B -#define INT_TIMERA1A 37 // Timer 1 subtimer A -#define INT_TIMERA1B 38 // Timer 1 subtimer B -#define INT_TIMERA2A 39 // Timer 2 subtimer A -#define INT_TIMERA2B 40 // Timer 2 subtimer B -#define INT_FLASH 45 // FLASH Control -#define INT_TIMERA3A 51 // Timer 3 subtimer A -#define INT_TIMERA3B 52 // Timer 3 subtimer B -#define INT_UDMA 62 // uDMA controller -#define INT_UDMAERR 63 // uDMA Error -#define INT_SHA 164 // SHA -#define INT_AES 167 // AES -#define INT_DES 169 // DES -#define INT_MMCHS 175 // SDIO -#define INT_I2S 177 // McAPS -#define INT_CAMERA 179 // Camera -#define INT_NWPIC 187 // Interprocessor communication -#define INT_PRCM 188 // Power, Reset and Clock Module -#define INT_SSPI 191 // Shared SPI -#define INT_GSPI 192 // Generic SPI -#define INT_LSPI 193 // Link SPI - -//***************************************************************************** -// -// The following are defines for the total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 195 //The above number plus 2? - - -//***************************************************************************** -// -// The following are defines for the total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - - -#endif // __HW_INTS_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcasp.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcasp.h deleted file mode 100755 index ec6e483dc4c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcasp.h +++ /dev/null @@ -1,1704 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_MCASP_H__ -#define __HW_MCASP_H__ - -//***************************************************************************** -// -// The following are defines for the MCASP register offsets. -// -//***************************************************************************** -#define MCASP_O_PID 0x00000000 -#define MCASP_O_ESYSCONFIG 0x00000004 // Power Idle SYSCONFIG register. -#define MCASP_O_PFUNC 0x00000010 -#define MCASP_O_PDIR 0x00000014 -#define MCASP_O_PDOUT 0x00000018 -#define MCASP_O_PDSET 0x0000001C // The pin data set register - // (PDSET) is an alias of the pin - // data output register (PDOUT) for - // writes only. Writing a 1 to the - // PDSET bit sets the corresponding - // bit in PDOUT and if PFUNC = 1 - // (GPIO function) and PDIR = 1 - // (output) drives a logic high on - // the pin. -#define MCASP_O_PDIN 0x0000001C // The pin data input register - // (PDIN) holds the I/O pin state of - // each of the McASP pins. PDIN - // allows the actual value of the - // pin to be read regardless of the - // state of PFUNC and PDIR. -#define MCASP_O_PDCLR 0x00000020 // The pin data clear register - // (PDCLR) is an alias of the pin - // data output register (PDOUT) for - // writes only. Writing a 1 to the - // PDCLR bit clears the - // corresponding bit in PDOUT and if - // PFUNC = 1 (GPIO function) and - // PDIR = 1 (output) drives a logic - // low on the pin. -#define MCASP_O_TLGC 0x00000030 // for IODFT -#define MCASP_O_TLMR 0x00000034 // for IODFT -#define MCASP_O_TLEC 0x00000038 // for IODFT -#define MCASP_O_GBLCTL 0x00000044 -#define MCASP_O_AMUTE 0x00000048 -#define MCASP_O_LBCTL 0x0000004C -#define MCASP_O_TXDITCTL 0x00000050 -#define MCASP_O_GBLCTLR 0x00000060 -#define MCASP_O_RXMASK 0x00000064 -#define MCASP_O_RXFMT 0x00000068 -#define MCASP_O_RXFMCTL 0x0000006C -#define MCASP_O_ACLKRCTL 0x00000070 -#define MCASP_O_AHCLKRCTL 0x00000074 -#define MCASP_O_RXTDM 0x00000078 -#define MCASP_O_EVTCTLR 0x0000007C -#define MCASP_O_RXSTAT 0x00000080 -#define MCASP_O_RXTDMSLOT 0x00000084 -#define MCASP_O_RXCLKCHK 0x00000088 -#define MCASP_O_REVTCTL 0x0000008C -#define MCASP_O_GBLCTLX 0x000000A0 -#define MCASP_O_TXMASK 0x000000A4 -#define MCASP_O_TXFMT 0x000000A8 -#define MCASP_O_TXFMCTL 0x000000AC -#define MCASP_O_ACLKXCTL 0x000000B0 -#define MCASP_O_AHCLKXCTL 0x000000B4 -#define MCASP_O_TXTDM 0x000000B8 -#define MCASP_O_EVTCTLX 0x000000BC -#define MCASP_O_TXSTAT 0x000000C0 -#define MCASP_O_TXTDMSLOT 0x000000C4 -#define MCASP_O_TXCLKCHK 0x000000C8 -#define MCASP_O_XEVTCTL 0x000000CC -#define MCASP_O_CLKADJEN 0x000000D0 -#define MCASP_O_DITCSRA0 0x00000100 -#define MCASP_O_DITCSRA1 0x00000104 -#define MCASP_O_DITCSRA2 0x00000108 -#define MCASP_O_DITCSRA3 0x0000010C -#define MCASP_O_DITCSRA4 0x00000110 -#define MCASP_O_DITCSRA5 0x00000114 -#define MCASP_O_DITCSRB0 0x00000118 -#define MCASP_O_DITCSRB1 0x0000011C -#define MCASP_O_DITCSRB2 0x00000120 -#define MCASP_O_DITCSRB3 0x00000124 -#define MCASP_O_DITCSRB4 0x00000128 -#define MCASP_O_DITCSRB5 0x0000012C -#define MCASP_O_DITUDRA0 0x00000130 -#define MCASP_O_DITUDRA1 0x00000134 -#define MCASP_O_DITUDRA2 0x00000138 -#define MCASP_O_DITUDRA3 0x0000013C -#define MCASP_O_DITUDRA4 0x00000140 -#define MCASP_O_DITUDRA5 0x00000144 -#define MCASP_O_DITUDRB0 0x00000148 -#define MCASP_O_DITUDRB1 0x0000014C -#define MCASP_O_DITUDRB2 0x00000150 -#define MCASP_O_DITUDRB3 0x00000154 -#define MCASP_O_DITUDRB4 0x00000158 -#define MCASP_O_DITUDRB5 0x0000015C -#define MCASP_O_XRSRCTL0 0x00000180 -#define MCASP_O_XRSRCTL1 0x00000184 -#define MCASP_O_XRSRCTL2 0x00000188 -#define MCASP_O_XRSRCTL3 0x0000018C -#define MCASP_O_XRSRCTL4 0x00000190 -#define MCASP_O_XRSRCTL5 0x00000194 -#define MCASP_O_XRSRCTL6 0x00000198 -#define MCASP_O_XRSRCTL7 0x0000019C -#define MCASP_O_XRSRCTL8 0x000001A0 -#define MCASP_O_XRSRCTL9 0x000001A4 -#define MCASP_O_XRSRCTL10 0x000001A8 -#define MCASP_O_XRSRCTL11 0x000001AC -#define MCASP_O_XRSRCTL12 0x000001B0 -#define MCASP_O_XRSRCTL13 0x000001B4 -#define MCASP_O_XRSRCTL14 0x000001B8 -#define MCASP_O_XRSRCTL15 0x000001BC -#define MCASP_O_TXBUF0 0x00000200 -#define MCASP_O_TXBUF1 0x00000204 -#define MCASP_O_TXBUF2 0x00000208 -#define MCASP_O_TXBUF3 0x0000020C -#define MCASP_O_TXBUF4 0x00000210 -#define MCASP_O_TXBUF5 0x00000214 -#define MCASP_O_TXBUF6 0x00000218 -#define MCASP_O_TXBUF7 0x0000021C -#define MCASP_O_TXBUF8 0x00000220 -#define MCASP_O_TXBUF9 0x00000224 -#define MCASP_O_TXBUF10 0x00000228 -#define MCASP_O_TXBUF11 0x0000022C -#define MCASP_O_TXBUF12 0x00000230 -#define MCASP_O_TXBUF13 0x00000234 -#define MCASP_O_TXBUF14 0x00000238 -#define MCASP_O_TXBUF15 0x0000023C -#define MCASP_O_RXBUF0 0x00000280 -#define MCASP_O_RXBUF1 0x00000284 -#define MCASP_O_RXBUF2 0x00000288 -#define MCASP_O_RXBUF3 0x0000028C -#define MCASP_O_RXBUF4 0x00000290 -#define MCASP_O_RXBUF5 0x00000294 -#define MCASP_O_RXBUF6 0x00000298 -#define MCASP_O_RXBUF7 0x0000029C -#define MCASP_O_RXBUF8 0x000002A0 -#define MCASP_O_RXBUF9 0x000002A4 -#define MCASP_O_RXBUF10 0x000002A8 -#define MCASP_O_RXBUF11 0x000002AC -#define MCASP_O_RXBUF12 0x000002B0 -#define MCASP_O_RXBUF13 0x000002B4 -#define MCASP_O_RXBUF14 0x000002B8 -#define MCASP_O_RXBUF15 0x000002BC -#define MCASP_0_WFIFOCTL 0x00001000 -#define MCASP_0_WFIFOSTS 0x00001004 -#define MCASP_0_RFIFOCTL 0x00001008 -#define MCASP_0_RFIFOSTS 0x0000100C - - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PID register. -// -//****************************************************************************** -#define MCASP_PID_SCHEME_M 0xC0000000 -#define MCASP_PID_SCHEME_S 30 -#define MCASP_PID_RESV_M 0x30000000 -#define MCASP_PID_RESV_S 28 -#define MCASP_PID_FUNCTION_M 0x0FFF0000 // McASP -#define MCASP_PID_FUNCTION_S 16 -#define MCASP_PID_RTL_M 0x0000F800 -#define MCASP_PID_RTL_S 11 -#define MCASP_PID_REVMAJOR_M 0x00000700 -#define MCASP_PID_REVMAJOR_S 8 -#define MCASP_PID_CUSTOM_M 0x000000C0 // non-custom -#define MCASP_PID_CUSTOM_S 6 -#define MCASP_PID_REVMINOR_M 0x0000003F -#define MCASP_PID_REVMINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// MCASP_O_ESYSCONFIG register. -// -//****************************************************************************** -#define MCASP_ESYSCONFIG_RSV_M 0xFFFFFFC0 // Reserved as per PDR 3.5 -#define MCASP_ESYSCONFIG_RSV_S 6 -#define MCASP_ESYSCONFIG_OTHER_M \ - 0x0000003C // Reserved for future expansion - -#define MCASP_ESYSCONFIG_OTHER_S 2 -#define MCASP_ESYSCONFIG_IDLE_MODE_M \ - 0x00000003 // Idle Mode - -#define MCASP_ESYSCONFIG_IDLE_MODE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PFUNC register. -// -//****************************************************************************** -#define MCASP_PFUNC_AFSR 0x80000000 // AFSR PFUNC 31 0 1 -#define MCASP_PFUNC_AHCLKR 0x40000000 // AHCLKR PFUNC 30 0 1 -#define MCASP_PFUNC_ACLKR 0x20000000 // ACLKR PFUNC 29 0 1 -#define MCASP_PFUNC_AFSX 0x10000000 // AFSX PFUNC 28 0 1 -#define MCASP_PFUNC_AHCLKX 0x08000000 // AHCLKX PFUNC 27 0 1 -#define MCASP_PFUNC_ACLKX 0x04000000 // ACLKX PFUNC 26 0 1 -#define MCASP_PFUNC_AMUTE 0x02000000 // AMUTE PFUNC 25 0 1 -#define MCASP_PFUNC_RESV1_M 0x01FF0000 // Reserved -#define MCASP_PFUNC_RESV1_S 16 -#define MCASP_PFUNC_AXR15 0x00008000 // AXR PFUNC BIT 15 0 1 -#define MCASP_PFUNC_AXR14 0x00004000 // AXR PFUNC BIT 14 0 1 -#define MCASP_PFUNC_AXR13 0x00002000 // AXR PFUNC BIT 13 0 1 -#define MCASP_PFUNC_AXR12 0x00001000 // AXR PFUNC BIT 12 0 1 -#define MCASP_PFUNC_AXR11 0x00000800 // AXR PFUNC BIT 11 0 1 -#define MCASP_PFUNC_AXR10 0x00000400 // AXR PFUNC BIT 10 0 1 -#define MCASP_PFUNC_AXR9 0x00000200 // AXR PFUNC BIT 9 0 1 -#define MCASP_PFUNC_AXR8 0x00000100 // AXR PFUNC BIT 8 0 1 -#define MCASP_PFUNC_AXR7 0x00000080 // AXR PFUNC BIT 7 0 1 -#define MCASP_PFUNC_AXR6 0x00000040 // AXR PFUNC BIT 6 0 1 -#define MCASP_PFUNC_AXR5 0x00000020 // AXR PFUNC BIT 5 0 1 -#define MCASP_PFUNC_AXR4 0x00000010 // AXR PFUNC BIT 4 0 1 -#define MCASP_PFUNC_AXR3 0x00000008 // AXR PFUNC BIT 3 0 1 -#define MCASP_PFUNC_AXR2 0x00000004 // AXR PFUNC BIT 2 0 1 -#define MCASP_PFUNC_AXR1 0x00000002 // AXR PFUNC BIT 1 0 1 -#define MCASP_PFUNC_AXR0 0x00000001 // AXR PFUNC BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDIR register. -// -//****************************************************************************** -#define MCASP_PDIR_AFSR 0x80000000 // AFSR PDIR 31 0 1 -#define MCASP_PDIR_AHCLKR 0x40000000 // AHCLKR PDIR 30 0 1 -#define MCASP_PDIR_ACLKR 0x20000000 // ACLKR PDIR 29 0 1 -#define MCASP_PDIR_AFSX 0x10000000 // AFSX PDIR 28 0 1 -#define MCASP_PDIR_AHCLKX 0x08000000 // AHCLKX PDIR 27 0 1 -#define MCASP_PDIR_ACLKX 0x04000000 // ACLKX PDIR 26 0 1 -#define MCASP_PDIR_AMUTE 0x02000000 // AMUTE PDIR 25 0 1 -#define MCASP_PDIR_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDIR_RESV_S 16 -#define MCASP_PDIR_AXR15 0x00008000 // AXR PDIR BIT 15 0 1 -#define MCASP_PDIR_AXR14 0x00004000 // AXR PDIR BIT 14 0 1 -#define MCASP_PDIR_AXR13 0x00002000 // AXR PDIR BIT 13 0 1 -#define MCASP_PDIR_AXR12 0x00001000 // AXR PDIR BIT 12 0 1 -#define MCASP_PDIR_AXR11 0x00000800 // AXR PDIR BIT 11 0 1 -#define MCASP_PDIR_AXR10 0x00000400 // AXR PDIR BIT 10 0 1 -#define MCASP_PDIR_AXR9 0x00000200 // AXR PDIR BIT 9 0 1 -#define MCASP_PDIR_AXR8 0x00000100 // AXR PDIR BIT 8 0 1 -#define MCASP_PDIR_AXR7 0x00000080 // AXR PDIR BIT 7 0 1 -#define MCASP_PDIR_AXR6 0x00000040 // AXR PDIR BIT 6 0 1 -#define MCASP_PDIR_AXR5 0x00000020 // AXR PDIR BIT 5 0 1 -#define MCASP_PDIR_AXR4 0x00000010 // AXR PDIR BIT 4 0 1 -#define MCASP_PDIR_AXR3 0x00000008 // AXR PDIR BIT 3 0 1 -#define MCASP_PDIR_AXR2 0x00000004 // AXR PDIR BIT 2 0 1 -#define MCASP_PDIR_AXR1 0x00000002 // AXR PDIR BIT 1 0 1 -#define MCASP_PDIR_AXR0 0x00000001 // AXR PDIR BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDOUT register. -// -//****************************************************************************** -#define MCASP_PDOUT_AFSR 0x80000000 // AFSR PDOUT 31 0 1 -#define MCASP_PDOUT_AHCLKR 0x40000000 // AHCLKR PDOUT 30 0 1 -#define MCASP_PDOUT_ACLKR 0x20000000 // ACLKR PDOUT 29 0 1 -#define MCASP_PDOUT_AFSX 0x10000000 // AFSX PDOUT 28 0 1 -#define MCASP_PDOUT_AHCLKX 0x08000000 // AHCLKX PDOUT 27 0 1 -#define MCASP_PDOUT_ACLKX 0x04000000 // ACLKX PDOUT 26 0 1 -#define MCASP_PDOUT_AMUTE 0x02000000 // AMUTE PDOUT 25 0 1 -#define MCASP_PDOUT_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDOUT_RESV_S 16 -#define MCASP_PDOUT_AXR15 0x00008000 // AXR PDOUT BIT 15 0 1 -#define MCASP_PDOUT_AXR14 0x00004000 // AXR PDOUT BIT 14 0 1 -#define MCASP_PDOUT_AXR13 0x00002000 // AXR PDOUT BIT 13 0 1 -#define MCASP_PDOUT_AXR12 0x00001000 // AXR PDOUT BIT 12 0 1 -#define MCASP_PDOUT_AXR11 0x00000800 // AXR PDOUT BIT 11 0 1 -#define MCASP_PDOUT_AXR10 0x00000400 // AXR PDOUT BIT 10 0 1 -#define MCASP_PDOUT_AXR9 0x00000200 // AXR PDOUT BIT 9 0 1 -#define MCASP_PDOUT_AXR8 0x00000100 // AXR PDOUT BIT 8 0 1 -#define MCASP_PDOUT_AXR7 0x00000080 // AXR PDOUT BIT 7 0 1 -#define MCASP_PDOUT_AXR6 0x00000040 // AXR PDOUT BIT 6 0 1 -#define MCASP_PDOUT_AXR5 0x00000020 // AXR PDOUT BIT 5 0 1 -#define MCASP_PDOUT_AXR4 0x00000010 // AXR PDOUT BIT 4 0 1 -#define MCASP_PDOUT_AXR3 0x00000008 // AXR PDOUT BIT 3 0 1 -#define MCASP_PDOUT_AXR2 0x00000004 // AXR PDOUT BIT 2 0 1 -#define MCASP_PDOUT_AXR1 0x00000002 // AXR PDOUT BIT 1 0 1 -#define MCASP_PDOUT_AXR0 0x00000001 // AXR PDOUT BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDSET register. -// -//****************************************************************************** -#define MCASP_PDSET_AFSR 0x80000000 -#define MCASP_PDSET_AHCLKR 0x40000000 -#define MCASP_PDSET_ACLKR 0x20000000 -#define MCASP_PDSET_AFSX 0x10000000 -#define MCASP_PDSET_AHCLKX 0x08000000 -#define MCASP_PDSET_ACLKX 0x04000000 -#define MCASP_PDSET_AMUTE 0x02000000 -#define MCASP_PDSET_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDSET_RESV_S 16 -#define MCASP_PDSET_AXR15 0x00008000 -#define MCASP_PDSET_AXR14 0x00004000 -#define MCASP_PDSET_AXR13 0x00002000 -#define MCASP_PDSET_AXR12 0x00001000 -#define MCASP_PDSET_AXR11 0x00000800 -#define MCASP_PDSET_AXR10 0x00000400 -#define MCASP_PDSET_AXR9 0x00000200 -#define MCASP_PDSET_AXR8 0x00000100 -#define MCASP_PDSET_AXR7 0x00000080 -#define MCASP_PDSET_AXR6 0x00000040 -#define MCASP_PDSET_AXR5 0x00000020 -#define MCASP_PDSET_AXR4 0x00000010 -#define MCASP_PDSET_AXR3 0x00000008 -#define MCASP_PDSET_AXR2 0x00000004 -#define MCASP_PDSET_AXR1 0x00000002 -#define MCASP_PDSET_AXR0 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDIN register. -// -//****************************************************************************** -#define MCASP_PDIN_AFSR 0x80000000 -#define MCASP_PDIN_AHCLKR 0x40000000 -#define MCASP_PDIN_ACLKR 0x20000000 -#define MCASP_PDIN_AFSX 0x10000000 -#define MCASP_PDIN_AHCLKX 0x08000000 -#define MCASP_PDIN_ACLKX 0x04000000 -#define MCASP_PDIN_AMUTE 0x02000000 -#define MCASP_PDIN_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDIN_RESV_S 16 -#define MCASP_PDIN_AXR15 0x00008000 -#define MCASP_PDIN_AXR14 0x00004000 -#define MCASP_PDIN_AXR13 0x00002000 -#define MCASP_PDIN_AXR12 0x00001000 -#define MCASP_PDIN_AXR11 0x00000800 -#define MCASP_PDIN_AXR10 0x00000400 -#define MCASP_PDIN_AXR9 0x00000200 -#define MCASP_PDIN_AXR8 0x00000100 -#define MCASP_PDIN_AXR7 0x00000080 -#define MCASP_PDIN_AXR6 0x00000040 -#define MCASP_PDIN_AXR5 0x00000020 -#define MCASP_PDIN_AXR4 0x00000010 -#define MCASP_PDIN_AXR3 0x00000008 -#define MCASP_PDIN_AXR2 0x00000004 -#define MCASP_PDIN_AXR1 0x00000002 -#define MCASP_PDIN_AXR0 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDCLR register. -// -//****************************************************************************** -#define MCASP_PDCLR_AFSR 0x80000000 // AFSR PDCLR 31 0 1 -#define MCASP_PDCLR_AHCLKR 0x40000000 // AHCLKR PDCLR 30 0 1 -#define MCASP_PDCLR_ACLKR 0x20000000 // ACLKR PDCLR 29 0 1 -#define MCASP_PDCLR_AFSX 0x10000000 // AFSX PDCLR 28 0 1 -#define MCASP_PDCLR_AHCLKX 0x08000000 // AHCLKX PDCLR 27 0 1 -#define MCASP_PDCLR_ACLKX 0x04000000 // ACLKX PDCLR 26 0 1 -#define MCASP_PDCLR_AMUTE 0x02000000 // AMUTE PDCLR 25 0 1 -#define MCASP_PDCLR_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDCLR_RESV_S 16 -#define MCASP_PDCLR_AXR15 0x00008000 // AXR PDCLR BIT 15 0 1 -#define MCASP_PDCLR_AXR14 0x00004000 // AXR PDCLR BIT 14 0 1 -#define MCASP_PDCLR_AXR13 0x00002000 // AXR PDCLR BIT 13 0 1 -#define MCASP_PDCLR_AXR12 0x00001000 // AXR PDCLR BIT 12 0 1 -#define MCASP_PDCLR_AXR11 0x00000800 // AXR PDCLR BIT 11 0 1 -#define MCASP_PDCLR_AXR10 0x00000400 // AXR PDCLR BIT 10 0 1 -#define MCASP_PDCLR_AXR9 0x00000200 // AXR PDCLR BIT 9 0 1 -#define MCASP_PDCLR_AXR8 0x00000100 // AXR PDCLR BIT 8 0 1 -#define MCASP_PDCLR_AXR7 0x00000080 // AXR PDCLR BIT 7 0 1 -#define MCASP_PDCLR_AXR6 0x00000040 // AXR PDCLR BIT 6 0 1 -#define MCASP_PDCLR_AXR5 0x00000020 // AXR PDCLR BIT 5 0 1 -#define MCASP_PDCLR_AXR4 0x00000010 // AXR PDCLR BIT 4 0 1 -#define MCASP_PDCLR_AXR3 0x00000008 // AXR PDCLR BIT 3 0 1 -#define MCASP_PDCLR_AXR2 0x00000004 // AXR PDCLR BIT 2 0 1 -#define MCASP_PDCLR_AXR1 0x00000002 // AXR PDCLR BIT 1 0 1 -#define MCASP_PDCLR_AXR0 0x00000001 // AXR PDCLR BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TLGC register. -// -//****************************************************************************** -#define MCASP_TLGC_RESV_M 0xFFFF0000 // Reserved -#define MCASP_TLGC_RESV_S 16 -#define MCASP_TLGC_MT_M 0x0000C000 // MISR on/off trigger command 0x0 - // 0x1 0x2 0x3 -#define MCASP_TLGC_MT_S 14 -#define MCASP_TLGC_RESV1_M 0x00003E00 // Reserved -#define MCASP_TLGC_RESV1_S 9 -#define MCASP_TLGC_MMS 0x00000100 // Source of MISR input 0 1 -#define MCASP_TLGC_ESEL 0x00000080 // Output enable select 0 1 -#define MCASP_TLGC_TOEN 0x00000040 // Test output enable control. 0 1 -#define MCASP_TLGC_MC_M 0x00000030 // States of MISR 0x0 0x1 0x2 0x3 -#define MCASP_TLGC_MC_S 4 -#define MCASP_TLGC_PC_M 0x0000000E // Pattern code 0x0 0x1 0x2 0x3 0x4 - // 0x5 0x6 0x7 -#define MCASP_TLGC_PC_S 1 -#define MCASP_TLGC_TM 0x00000001 // Tie high; do not write to this - // bit 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TLMR register. -// -//****************************************************************************** -#define MCASP_TLMR_TLMR_M 0xFFFFFFFF // Contains test result signature. -#define MCASP_TLMR_TLMR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TLEC register. -// -//****************************************************************************** -#define MCASP_TLEC_TLEC_M 0xFFFFFFFF // Contains number of cycles during - // which MISR sig will be - // accumulated. -#define MCASP_TLEC_TLEC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_GBLCTL register. -// -//****************************************************************************** -#define MCASP_GBLCTL_XFRST 0x00001000 // Frame sync generator reset 0 1 -#define MCASP_GBLCTL_XSMRST 0x00000800 // XMT state machine reset 0 1 -#define MCASP_GBLCTL_XSRCLR 0x00000400 // XMT serializer clear 0 1 -#define MCASP_GBLCTL_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 -#define MCASP_GBLCTL_XCLKRST 0x00000100 // XMT clock divder reset 0 1 -#define MCASP_GBLCTL_RFRST 0x00000010 // Frame sync generator reset 0 1 -#define MCASP_GBLCTL_RSMRST 0x00000008 // RCV state machine reset 0 1 -#define MCASP_GBLCTL_RSRCLR 0x00000004 // RCV serializer clear 0 1 -#define MCASP_GBLCTL_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 -#define MCASP_GBLCTL_RCLKRST 0x00000001 // RCV clock divder reset 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_AMUTE register. -// -//****************************************************************************** -#define MCASP_AMUTE_XDMAERR 0x00001000 // MUTETXDMAERR occur 0 1 -#define MCASP_AMUTE_RDMAERR 0x00000800 // MUTERXDMAERR occur 0 1 -#define MCASP_AMUTE_XCKFAIL 0x00000400 // XMT bad clock 0 1 -#define MCASP_AMUTE_RCKFAIL 0x00000200 // RCV bad clock 0 1 -#define MCASP_AMUTE_XSYNCERR 0x00000100 // XMT unexpected FS 0 1 -#define MCASP_AMUTE_RSYNCERR 0x00000080 // RCV unexpected FS 0 1 -#define MCASP_AMUTE_XUNDRN 0x00000040 // XMT underrun occurs 0 1 -#define MCASP_AMUTE_ROVRN 0x00000020 // RCV overun occurs 0 1 -#define MCASP_AMUTE_INSTAT 0x00000010 -#define MCASP_AMUTE_INEN 0x00000008 // drive AMUTE active on mute in - // active 0 1 -#define MCASP_AMUTE_INPOL 0x00000004 // Mute input polarity 0 1 -#define MCASP_AMUTE_MUTEN_M 0x00000003 // AMUTE pin enable 0x0 0x1 0x2 -#define MCASP_AMUTE_MUTEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_LBCTL register. -// -//****************************************************************************** -#define MCASP_LBCTL_IOLBEN 0x00000010 // IO loopback enable 0 1 -#define MCASP_LBCTL_MODE_M 0x0000000C // Loop back clock source generator - // 0x0 0x1 0x2 0x3 -#define MCASP_LBCTL_MODE_S 2 -#define MCASP_LBCTL_ORD 0x00000002 // Loopback order 0 1 -#define MCASP_LBCTL_DLBEN 0x00000001 // Loop back mode 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXDITCTL register. -// -//****************************************************************************** -#define MCASP_TXDITCTL_VB 0x00000008 // Valib bit for odd TDM 0 1 -#define MCASP_TXDITCTL_VA 0x00000004 // Valib bit for even TDM 0 1 -#define MCASP_TXDITCTL_DITEN 0x00000001 // XMT DIT Mode Enable 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_GBLCTLR register. -// -//****************************************************************************** -#define MCASP_GBLCTLR_XFRST 0x00001000 -#define MCASP_GBLCTLR_XSMRST 0x00000800 -#define MCASP_GBLCTLR_XSRCLR 0x00000400 -#define MCASP_GBLCTLR_XHCLKRST 0x00000200 -#define MCASP_GBLCTLR_XCLKRST 0x00000100 -#define MCASP_GBLCTLR_RFRST 0x00000010 // Frame sync generator reset 0 1 -#define MCASP_GBLCTLR_RSMRST 0x00000008 // RCV state machine reset 0 1 -#define MCASP_GBLCTLR_RSRCLR 0x00000004 // RCV serializer clear 0 1 -#define MCASP_GBLCTLR_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 -#define MCASP_GBLCTLR_RCLKRST 0x00000001 // RCV clock divder reset 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXMASK register. -// -//****************************************************************************** -#define MCASP_RXMASK_RMASK31 0x80000000 // RMASK BIT 31 0 1 -#define MCASP_RXMASK_RMASK30 0x40000000 // RMASK BIT 30 0 1 -#define MCASP_RXMASK_RMASK29 0x20000000 // RMASK BIT 29 0 1 -#define MCASP_RXMASK_RMASK28 0x10000000 // RMASK BIT 28 0 1 -#define MCASP_RXMASK_RMASK27 0x08000000 // RMASK BIT 27 0 1 -#define MCASP_RXMASK_RMASK26 0x04000000 // RMASK BIT 26 0 1 -#define MCASP_RXMASK_RMASK25 0x02000000 // RMASK BIT 25 0 1 -#define MCASP_RXMASK_RMASK24 0x01000000 // RMASK BIT 24 0 1 -#define MCASP_RXMASK_RMASK23 0x00800000 // RMASK BIT 23 0 1 -#define MCASP_RXMASK_RMASK22 0x00400000 // RMASK BIT 22 0 1 -#define MCASP_RXMASK_RMASK21 0x00200000 // RMASK BIT 21 0 1 -#define MCASP_RXMASK_RMASK20 0x00100000 // RMASK BIT 20 0 1 -#define MCASP_RXMASK_RMASK19 0x00080000 // RMASK BIT 19 0 1 -#define MCASP_RXMASK_RMASK18 0x00040000 // RMASK BIT 18 0 1 -#define MCASP_RXMASK_RMASK17 0x00020000 // RMASK BIT 17 0 1 -#define MCASP_RXMASK_RMASK16 0x00010000 // RMASK BIT 16 0 1 -#define MCASP_RXMASK_RMASK15 0x00008000 // RMASK BIT 15 0 1 -#define MCASP_RXMASK_RMASK14 0x00004000 // RMASK BIT 14 0 1 -#define MCASP_RXMASK_RMASK13 0x00002000 // RMASK BIT 13 0 1 -#define MCASP_RXMASK_RMASK12 0x00001000 // RMASK BIT 12 0 1 -#define MCASP_RXMASK_RMASK11 0x00000800 // RMASK BIT 11 0 1 -#define MCASP_RXMASK_RMASK10 0x00000400 // RMASK BIT 10 0 1 -#define MCASP_RXMASK_RMASK9 0x00000200 // RMASK BIT 9 0 1 -#define MCASP_RXMASK_RMASK8 0x00000100 // RMASK BIT 8 0 1 -#define MCASP_RXMASK_RMASK7 0x00000080 // RMASK BIT 7 0 1 -#define MCASP_RXMASK_RMASK6 0x00000040 // RMASK BIT 6 0 1 -#define MCASP_RXMASK_RMASK5 0x00000020 // RMASK BIT 5 0 1 -#define MCASP_RXMASK_RMASK4 0x00000010 // RMASK BIT 4 0 1 -#define MCASP_RXMASK_RMASK3 0x00000008 // RMASK BIT 3 0 1 -#define MCASP_RXMASK_RMASK2 0x00000004 // RMASK BIT 2 0 1 -#define MCASP_RXMASK_RMASK1 0x00000002 // RMASK BIT 1 0 1 -#define MCASP_RXMASK_RMASK0 0x00000001 // RMASK BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXFMT register. -// -//****************************************************************************** -#define MCASP_RXFMT_RDATDLY_M 0x00030000 // RCV Frame sync delay 0x0 0 Bit - // delay 0x1 1 Bit delay 0x2 2 Bit - // delay -#define MCASP_RXFMT_RDATDLY_S 16 -#define MCASP_RXFMT_RRVRS 0x00008000 // RCV serial stream bit order 0 1 -#define MCASP_RXFMT_RPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 -#define MCASP_RXFMT_RPAD_S 13 -#define MCASP_RXFMT_RPBIT_M 0x00001F00 // Pad bit position -#define MCASP_RXFMT_RPBIT_S 8 -#define MCASP_RXFMT_RSSZ_M 0x000000F0 // RCV slot Size 0x0 0x1 0x2 0x3 - // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB - // 0xC 0xD 0xE 0xF -#define MCASP_RXFMT_RSSZ_S 4 -#define MCASP_RXFMT_RBUSEL 0x00000008 // Write to RBUF using CPU/DMA 0 - // DMA port access 1 CPU port Access -#define MCASP_RXFMT_RROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 - // 0x3 0x4 0x5 0x6 0x7 -#define MCASP_RXFMT_RROT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXFMCTL register. -// -//****************************************************************************** -#define MCASP_RXFMCTL_RMOD_M 0x0000FF80 // RCV Frame sync mode -#define MCASP_RXFMCTL_RMOD_S 7 -#define MCASP_RXFMCTL_FRWID 0x00000010 // RCV Frame sync Duration 0 1 -#define MCASP_RXFMCTL_FSRM 0x00000002 // RCV frame sync External 0 1 -#define MCASP_RXFMCTL_FSRP 0x00000001 // RCV Frame sync Polarity 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_ACLKRCTL register. -// -//****************************************************************************** -#define MCASP_ACLKRCTL_BUSY 0x00100000 -#define MCASP_ACLKRCTL_DIVBUSY 0x00080000 -#define MCASP_ACLKRCTL_ADJBUSY 0x00040000 -#define MCASP_ACLKRCTL_CLKRADJ_M \ - 0x00030000 - -#define MCASP_ACLKRCTL_CLKRADJ_S 16 -#define MCASP_ACLKRCTL_CLKRP 0x00000080 // RCV Clock Polarity 0 1 -#define MCASP_ACLKRCTL_CLKRM 0x00000020 // RCV clock source 0 1 -#define MCASP_ACLKRCTL_CLKRDIV_M \ - 0x0000001F // RCV clock devide ratio - -#define MCASP_ACLKRCTL_CLKRDIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register. -// -//****************************************************************************** -#define MCASP_AHCLKRCTL_BUSY 0x00100000 -#define MCASP_AHCLKRCTL_DIVBUSY 0x00080000 -#define MCASP_AHCLKRCTL_ADJBUSY 0x00040000 -#define MCASP_AHCLKRCTL_HCLKRADJ_M \ - 0x00030000 - -#define MCASP_AHCLKRCTL_HCLKRADJ_S 16 -#define MCASP_AHCLKRCTL_HCLKRM 0x00008000 // High Freq. RCV clock Source 0 1 -#define MCASP_AHCLKRCTL_HCLKRP 0x00004000 // High Freq. clock Polarity Before - // diviser 0 1 -#define MCASP_AHCLKRCTL_HCLKRDIV_M \ - 0x00000FFF // RCV clock Divide Ratio - -#define MCASP_AHCLKRCTL_HCLKRDIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXTDM register. -// -//****************************************************************************** -#define MCASP_RXTDM_RTDMS31 0x80000000 // RCV mode during TDM time slot 31 - // 0 1 -#define MCASP_RXTDM_RTDMS30 0x40000000 // RCV mode during TDM time slot 30 - // 0 1 -#define MCASP_RXTDM_RTDMS29 0x20000000 // RCV mode during TDM time slot 29 - // 0 1 -#define MCASP_RXTDM_RTDMS28 0x10000000 // RCV mode during TDM time slot 28 - // 0 1 -#define MCASP_RXTDM_RTDMS27 0x08000000 // RCV mode during TDM time slot 27 - // 0 1 -#define MCASP_RXTDM_RTDMS26 0x04000000 // RCV mode during TDM time slot 26 - // 0 1 -#define MCASP_RXTDM_RTDMS25 0x02000000 // RCV mode during TDM time slot 25 - // 0 1 -#define MCASP_RXTDM_RTDMS24 0x01000000 // RCV mode during TDM time slot 24 - // 0 1 -#define MCASP_RXTDM_RTDMS23 0x00800000 // RCV mode during TDM time slot 23 - // 0 1 -#define MCASP_RXTDM_RTDMS22 0x00400000 // RCV mode during TDM time slot 22 - // 0 1 -#define MCASP_RXTDM_RTDMS21 0x00200000 // RCV mode during TDM time slot 21 - // 0 1 -#define MCASP_RXTDM_RTDMS20 0x00100000 // RCV mode during TDM time slot 20 - // 0 1 -#define MCASP_RXTDM_RTDMS19 0x00080000 // RCV mode during TDM time slot 19 - // 0 1 -#define MCASP_RXTDM_RTDMS18 0x00040000 // RCV mode during TDM time slot 18 - // 0 1 -#define MCASP_RXTDM_RTDMS17 0x00020000 // RCV mode during TDM time slot 17 - // 0 1 -#define MCASP_RXTDM_RTDMS16 0x00010000 // RCV mode during TDM time slot 16 - // 0 1 -#define MCASP_RXTDM_RTDMS15 0x00008000 // RCV mode during TDM time slot 15 - // 0 1 -#define MCASP_RXTDM_RTDMS14 0x00004000 // RCV mode during TDM time slot 14 - // 0 1 -#define MCASP_RXTDM_RTDMS13 0x00002000 // RCV mode during TDM time slot 13 - // 0 1 -#define MCASP_RXTDM_RTDMS12 0x00001000 // RCV mode during TDM time slot 12 - // 0 1 -#define MCASP_RXTDM_RTDMS11 0x00000800 // RCV mode during TDM time slot 11 - // 0 1 -#define MCASP_RXTDM_RTDMS10 0x00000400 // RCV mode during TDM time slot 10 - // 0 1 -#define MCASP_RXTDM_RTDMS9 0x00000200 // RCV mode during TDM time slot 9 - // 0 1 -#define MCASP_RXTDM_RTDMS8 0x00000100 // RCV mode during TDM time slot 8 - // 0 1 -#define MCASP_RXTDM_RTDMS7 0x00000080 // RCV mode during TDM time slot 7 - // 0 1 -#define MCASP_RXTDM_RTDMS6 0x00000040 // RCV mode during TDM time slot 6 - // 0 1 -#define MCASP_RXTDM_RTDMS5 0x00000020 // RCV mode during TDM time slot 5 - // 0 1 -#define MCASP_RXTDM_RTDMS4 0x00000010 // RCV mode during TDM time slot 4 - // 0 1 -#define MCASP_RXTDM_RTDMS3 0x00000008 // RCV mode during TDM time slot 3 - // 0 1 -#define MCASP_RXTDM_RTDMS2 0x00000004 // RCV mode during TDM time slot 2 - // 0 1 -#define MCASP_RXTDM_RTDMS1 0x00000002 // RCV mode during TDM time slot 1 - // 0 1 -#define MCASP_RXTDM_RTDMS0 0x00000001 // RCV mode during TDM time slot 0 - // 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_EVTCTLR register. -// -//****************************************************************************** -#define MCASP_EVTCTLR_RSTAFRM 0x00000080 // RCV Start of Frame Interrupt 0 1 -#define MCASP_EVTCTLR_RDATA 0x00000020 // RCV Data Interrupt 0 1 -#define MCASP_EVTCTLR_RLAST 0x00000010 // RCV Last Slot Interrupt 0 1 -#define MCASP_EVTCTLR_RDMAERR 0x00000008 // RCV DMA Bus Error 0 1 -#define MCASP_EVTCTLR_RCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 -#define MCASP_EVTCTLR_RSYNCERR 0x00000002 // RCV Unexpected FSR Interrupt 0 1 -#define MCASP_EVTCTLR_ROVRN 0x00000001 // RCV Underrun Flag 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXSTAT register. -// -//****************************************************************************** -#define MCASP_RXSTAT_RERR 0x00000100 // RCV Error 0 1 -#define MCASP_RXSTAT_RDMAERR 0x00000080 // RCV DMA bus error 0 1 -#define MCASP_RXSTAT_RSTAFRM 0x00000040 // Start of Frame-RCV 0 1 -#define MCASP_RXSTAT_RDATA 0x00000020 // Data Ready Flag 0 1 -#define MCASP_RXSTAT_RLAST 0x00000010 // Last Slot Interrupt Flag 0 1 -#define MCASP_RXSTAT_RTDMSLOT 0x00000008 // EvenOdd Slot 0 1 -#define MCASP_RXSTAT_RCKFAIL 0x00000004 // Bad Transmit Flag 0 1 -#define MCASP_RXSTAT_RSYNCERR 0x00000002 // Unexpected RCV Frame sync flag 0 - // 1 -#define MCASP_RXSTAT_ROVRN 0x00000001 // RCV Underrun Flag 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register. -// -//****************************************************************************** -#define MCASP_RXTDMSLOT_RSLOTCNT_M \ - 0x000003FF // Current RCV time slot count - -#define MCASP_RXTDMSLOT_RSLOTCNT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXCLKCHK register. -// -//****************************************************************************** -#define MCASP_RXCLKCHK_RCNT_M 0xFF000000 // RCV clock count value -#define MCASP_RXCLKCHK_RCNT_S 24 -#define MCASP_RXCLKCHK_RMAX_M 0x00FF0000 // RCV clock maximum boundary -#define MCASP_RXCLKCHK_RMAX_S 16 -#define MCASP_RXCLKCHK_RMIN_M 0x0000FF00 // RCV clock minimum boundary -#define MCASP_RXCLKCHK_RMIN_S 8 -#define MCASP_RXCLKCHK_RPS_M 0x0000000F // RCV clock check prescaler 0x0 - // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 -#define MCASP_RXCLKCHK_RPS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_REVTCTL register. -// -//****************************************************************************** -#define MCASP_REVTCTL_RDATDMA 0x00000001 // RCV data DMA request 0 Enable - // DMA Transfer 1 Disable DMA - // Transfer -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_GBLCTLX register. -// -//****************************************************************************** -#define MCASP_GBLCTLX_XFRST 0x00001000 // Frame sync generator reset 0 1 -#define MCASP_GBLCTLX_XSMRST 0x00000800 // XMT state machine reset 0 1 -#define MCASP_GBLCTLX_XSRCLR 0x00000400 // XMT serializer clear 0 1 -#define MCASP_GBLCTLX_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 -#define MCASP_GBLCTLX_XCLKRST 0x00000100 // XMT clock divder reset 0 1 -#define MCASP_GBLCTLX_RFRST 0x00000010 -#define MCASP_GBLCTLX_RSMRST 0x00000008 -#define MCASP_GBLCTLX_RSRCLKR 0x00000004 -#define MCASP_GBLCTLX_RHCLKRST 0x00000002 -#define MCASP_GBLCTLX_RCLKRST 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXMASK register. -// -//****************************************************************************** -#define MCASP_TXMASK_XMASK31 0x80000000 // XMASK BIT 31 0 1 -#define MCASP_TXMASK_XMASK30 0x40000000 // XMASK BIT 30 0 1 -#define MCASP_TXMASK_XMASK29 0x20000000 // XMASK BIT 29 0 1 -#define MCASP_TXMASK_XMASK28 0x10000000 // XMASK BIT 28 0 1 -#define MCASP_TXMASK_XMASK27 0x08000000 // XMASK BIT 27 0 1 -#define MCASP_TXMASK_XMASK26 0x04000000 // XMASK BIT 26 0 1 -#define MCASP_TXMASK_XMASK25 0x02000000 // XMASK BIT 25 0 1 -#define MCASP_TXMASK_XMASK24 0x01000000 // XMASK BIT 24 0 1 -#define MCASP_TXMASK_XMASK23 0x00800000 // XMASK BIT 23 0 1 -#define MCASP_TXMASK_XMASK22 0x00400000 // XMASK BIT 22 0 1 -#define MCASP_TXMASK_XMASK21 0x00200000 // XMASK BIT 21 0 1 -#define MCASP_TXMASK_XMASK20 0x00100000 // XMASK BIT 20 0 1 -#define MCASP_TXMASK_XMASK19 0x00080000 // XMASK BIT 19 0 1 -#define MCASP_TXMASK_XMASK18 0x00040000 // XMASK BIT 18 0 1 -#define MCASP_TXMASK_XMASK17 0x00020000 // XMASK BIT 17 0 1 -#define MCASP_TXMASK_XMASK16 0x00010000 // XMASK BIT 16 0 1 -#define MCASP_TXMASK_XMASK15 0x00008000 // XMASK BIT 15 0 1 -#define MCASP_TXMASK_XMASK14 0x00004000 // XMASK BIT 14 0 1 -#define MCASP_TXMASK_XMASK13 0x00002000 // XMASK BIT 13 0 1 -#define MCASP_TXMASK_XMASK12 0x00001000 // XMASK BIT 12 0 1 -#define MCASP_TXMASK_XMASK11 0x00000800 // XMASK BIT 11 0 1 -#define MCASP_TXMASK_XMASK10 0x00000400 // XMASK BIT 10 0 1 -#define MCASP_TXMASK_XMASK9 0x00000200 // XMASK BIT 9 0 1 -#define MCASP_TXMASK_XMASK8 0x00000100 // XMASK BIT 8 0 1 -#define MCASP_TXMASK_XMASK7 0x00000080 // XMASK BIT 7 0 1 -#define MCASP_TXMASK_XMASK6 0x00000040 // XMASK BIT 6 0 1 -#define MCASP_TXMASK_XMASK5 0x00000020 // XMASK BIT 5 0 1 -#define MCASP_TXMASK_XMASK4 0x00000010 // XMASK BIT 4 0 1 -#define MCASP_TXMASK_XMASK3 0x00000008 // XMASK BIT 3 0 1 -#define MCASP_TXMASK_XMASK2 0x00000004 // XMASK BIT 2 0 1 -#define MCASP_TXMASK_XMASK1 0x00000002 // XMASK BIT 1 0 1 -#define MCASP_TXMASK_XMASK0 0x00000001 // XMASK BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXFMT register. -// -//****************************************************************************** -#define MCASP_TXFMT_XDATDLY_M 0x00030000 // XMT Frame sync delay 0x0 0 Bit - // delay 0x1 1 Bit delay 0x2 2 Bit - // delay -#define MCASP_TXFMT_XDATDLY_S 16 -#define MCASP_TXFMT_XRVRS 0x00008000 // XMT serial stream bit order 0 1 -#define MCASP_TXFMT_XPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 -#define MCASP_TXFMT_XPAD_S 13 -#define MCASP_TXFMT_XPBIT_M 0x00001F00 // Pad bit position -#define MCASP_TXFMT_XPBIT_S 8 -#define MCASP_TXFMT_XSSZ_M 0x000000F0 // XMT slot Size 0x0 0x1 0x2 0x3 - // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB - // 0xC 0xD 0xE 0xF -#define MCASP_TXFMT_XSSZ_S 4 -#define MCASP_TXFMT_XBUSEL 0x00000008 // Write to XBUF using CPU/DMA 0 - // DMA port access 1 CPU port Access -#define MCASP_TXFMT_XROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 - // 0x3 0x4 0x5 0x6 0x7 -#define MCASP_TXFMT_XROT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXFMCTL register. -// -//****************************************************************************** -#define MCASP_TXFMCTL_XMOD_M 0x0000FF80 // XMT Frame sync mode -#define MCASP_TXFMCTL_XMOD_S 7 -#define MCASP_TXFMCTL_FXWID 0x00000010 // XMT Frame sync Duration 0 1 -#define MCASP_TXFMCTL_FSXM 0x00000002 // XMT frame sync External 0 1 -#define MCASP_TXFMCTL_FSXP 0x00000001 // XMT Frame sync Polarity 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_ACLKXCTL register. -// -//****************************************************************************** -#define MCASP_ACLKXCTL_BUSY 0x00100000 -#define MCASP_ACLKXCTL_DIVBUSY 0x00080000 -#define MCASP_ACLKXCTL_ADJBUSY 0x00040000 -#define MCASP_ACLKXCTL_CLKXADJ_M \ - 0x00030000 - -#define MCASP_ACLKXCTL_CLKXADJ_S 16 -#define MCASP_ACLKXCTL_CLKXP 0x00000080 // XMT Clock Polarity 0 1 -#define MCASP_ACLKXCTL_ASYNC 0x00000040 // XMT/RCV operation sync /Async 0 - // 1 -#define MCASP_ACLKXCTL_CLKXM 0x00000020 // XMT clock source 0 1 -#define MCASP_ACLKXCTL_CLKXDIV_M \ - 0x0000001F // XMT clock devide ratio - -#define MCASP_ACLKXCTL_CLKXDIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register. -// -//****************************************************************************** -#define MCASP_AHCLKXCTL_BUSY 0x00100000 -#define MCASP_AHCLKXCTL_DIVBUSY 0x00080000 -#define MCASP_AHCLKXCTL_ADJBUSY 0x00040000 -#define MCASP_AHCLKXCTL_HCLKXADJ_M \ - 0x00030000 - -#define MCASP_AHCLKXCTL_HCLKXADJ_S 16 -#define MCASP_AHCLKXCTL_HCLKXM 0x00008000 // High Freq. XMT clock Source 0 1 -#define MCASP_AHCLKXCTL_HCLKXP 0x00004000 // High Freq. clock Polarity Before - // diviser 0 1 -#define MCASP_AHCLKXCTL_HCLKXDIV_M \ - 0x00000FFF // XMT clock Divide Ratio - -#define MCASP_AHCLKXCTL_HCLKXDIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXTDM register. -// -//****************************************************************************** -#define MCASP_TXTDM_XTDMS31 0x80000000 // XMT mode during TDM time slot 31 - // 0 1 -#define MCASP_TXTDM_XTDMS30 0x40000000 // XMT mode during TDM time slot 30 - // 0 1 -#define MCASP_TXTDM_XTDMS29 0x20000000 // XMT mode during TDM time slot 29 - // 0 1 -#define MCASP_TXTDM_XTDMS28 0x10000000 // XMT mode during TDM time slot 28 - // 0 1 -#define MCASP_TXTDM_XTDMS27 0x08000000 // XMT mode during TDM time slot 27 - // 0 1 -#define MCASP_TXTDM_XTDMS26 0x04000000 // XMT mode during TDM time slot 26 - // 0 1 -#define MCASP_TXTDM_XTDMS25 0x02000000 // XMT mode during TDM time slot 25 - // 0 1 -#define MCASP_TXTDM_XTDMS24 0x01000000 // XMT mode during TDM time slot 24 - // 0 1 -#define MCASP_TXTDM_XTDMS23 0x00800000 // XMT mode during TDM time slot 23 - // 0 1 -#define MCASP_TXTDM_XTDMS22 0x00400000 // XMT mode during TDM time slot 22 - // 0 1 -#define MCASP_TXTDM_XTDMS21 0x00200000 // XMT mode during TDM time slot 21 - // 0 1 -#define MCASP_TXTDM_XTDMS20 0x00100000 // XMT mode during TDM time slot 20 - // 0 1 -#define MCASP_TXTDM_XTDMS19 0x00080000 // XMT mode during TDM time slot 19 - // 0 1 -#define MCASP_TXTDM_XTDMS18 0x00040000 // XMT mode during TDM time slot 18 - // 0 1 -#define MCASP_TXTDM_XTDMS17 0x00020000 // XMT mode during TDM time slot 17 - // 0 1 -#define MCASP_TXTDM_XTDMS16 0x00010000 // XMT mode during TDM time slot 16 - // 0 1 -#define MCASP_TXTDM_XTDMS15 0x00008000 // XMT mode during TDM time slot 15 - // 0 1 -#define MCASP_TXTDM_XTDMS14 0x00004000 // XMT mode during TDM time slot 14 - // 0 1 -#define MCASP_TXTDM_XTDMS13 0x00002000 // XMT mode during TDM time slot 13 - // 0 1 -#define MCASP_TXTDM_XTDMS12 0x00001000 // XMT mode during TDM time slot 12 - // 0 1 -#define MCASP_TXTDM_XTDMS11 0x00000800 // XMT mode during TDM time slot 11 - // 0 1 -#define MCASP_TXTDM_XTDMS10 0x00000400 // XMT mode during TDM time slot 10 - // 0 1 -#define MCASP_TXTDM_XTDMS9 0x00000200 // XMT mode during TDM time slot 9 - // 0 1 -#define MCASP_TXTDM_XTDMS8 0x00000100 // XMT mode during TDM time slot 8 - // 0 1 -#define MCASP_TXTDM_XTDMS7 0x00000080 // XMT mode during TDM time slot 7 - // 0 1 -#define MCASP_TXTDM_XTDMS6 0x00000040 // XMT mode during TDM time slot 6 - // 0 1 -#define MCASP_TXTDM_XTDMS5 0x00000020 // XMT mode during TDM time slot 5 - // 0 1 -#define MCASP_TXTDM_XTDMS4 0x00000010 // XMT mode during TDM time slot 4 - // 0 1 -#define MCASP_TXTDM_XTDMS3 0x00000008 // XMT mode during TDM time slot 3 - // 0 1 -#define MCASP_TXTDM_XTDMS2 0x00000004 // XMT mode during TDM time slot 2 - // 0 1 -#define MCASP_TXTDM_XTDMS1 0x00000002 // XMT mode during TDM time slot 1 - // 0 1 -#define MCASP_TXTDM_XTDMS0 0x00000001 // XMT mode during TDM time slot 0 - // 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_EVTCTLX register. -// -//****************************************************************************** -#define MCASP_EVTCTLX_XSTAFRM 0x00000080 // XMT Start of Frame Interrupt 0 1 -#define MCASP_EVTCTLX_XDATA 0x00000020 // XMT Data Interrupt 0 1 -#define MCASP_EVTCTLX_XLAST 0x00000010 // XMT Last Slot Interrupt 0 1 -#define MCASP_EVTCTLX_XDMAERR 0x00000008 // XMT DMA Bus Error 0 1 -#define MCASP_EVTCTLX_XCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 -#define MCASP_EVTCTLX_XSYNCERR 0x00000002 // XMT Unexpected FSR Interrupt 0 1 -#define MCASP_EVTCTLX_XUNDRN 0x00000001 // XMT Underrun Interrupt 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXSTAT register. -// -//****************************************************************************** -#define MCASP_TXSTAT_XERR 0x00000100 // XMT Error 0 1 -#define MCASP_TXSTAT_XDMAERR 0x00000080 // XMT DMA bus error 0 1 -#define MCASP_TXSTAT_XSTAFRM 0x00000040 // Start of Frame-XMT 0 1 -#define MCASP_TXSTAT_XDATA 0x00000020 // Data Ready Flag 0 1 -#define MCASP_TXSTAT_XLAST 0x00000010 // Last Slot Interrupt Flag 0 1 -#define MCASP_TXSTAT_XTDMSLOT 0x00000008 // EvenOdd Slot 0 1 -#define MCASP_TXSTAT_XCKFAIL 0x00000004 // Bad Transmit Flag 0 1 -#define MCASP_TXSTAT_XSYNCERR 0x00000002 // Unexpected XMT Frame sync flag 0 - // 1 -#define MCASP_TXSTAT_XUNDRN 0x00000001 // XMT Underrun Flag 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register. -// -//****************************************************************************** -#define MCASP_TXTDMSLOT_XSLOTCNT_M \ - 0x000003FF // Current XMT time slot count - // during reset the value of this - // register is 0b0101111111 (0x17f) - // and after reset 0 - -#define MCASP_TXTDMSLOT_XSLOTCNT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXCLKCHK register. -// -//****************************************************************************** -#define MCASP_TXCLKCHK_XCNT_M 0xFF000000 // XMT clock count value -#define MCASP_TXCLKCHK_XCNT_S 24 -#define MCASP_TXCLKCHK_XMAX_M 0x00FF0000 // XMT clock maximum boundary -#define MCASP_TXCLKCHK_XMAX_S 16 -#define MCASP_TXCLKCHK_XMIN_M 0x0000FF00 // XMT clock minimum boundary -#define MCASP_TXCLKCHK_XMIN_S 8 -#define MCASP_TXCLKCHK_RESV 0x00000080 // Reserved -#define MCASP_TXCLKCHK_XPS_M 0x0000000F // XMT clock check prescaler 0x0 - // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 -#define MCASP_TXCLKCHK_XPS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XEVTCTL register. -// -//****************************************************************************** -#define MCASP_XEVTCTL_XDATDMA 0x00000001 // XMT data DMA request 0 Enable - // DMA Transfer 1 Disable DMA - // Transfer -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_CLKADJEN register. -// -//****************************************************************************** -#define MCASP_CLKADJEN_ENABLE 0x00000001 // One-shot clock adjust enable 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA0 register. -// -//****************************************************************************** -#define MCASP_DITCSRA0_DITCSRA0_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status - -#define MCASP_DITCSRA0_DITCSRA0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA1 register. -// -//****************************************************************************** -#define MCASP_DITCSRA1_DITCSRA1_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status - -#define MCASP_DITCSRA1_DITCSRA1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA2 register. -// -//****************************************************************************** -#define MCASP_DITCSRA2_DITCSRA2_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status Register - -#define MCASP_DITCSRA2_DITCSRA2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA3 register. -// -//****************************************************************************** -#define MCASP_DITCSRA3_DITCSRA3_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status Register - -#define MCASP_DITCSRA3_DITCSRA3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA4 register. -// -//****************************************************************************** -#define MCASP_DITCSRA4_DITCSRA4_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status - -#define MCASP_DITCSRA4_DITCSRA4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA5 register. -// -//****************************************************************************** -#define MCASP_DITCSRA5_DITCSRA5_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status - -#define MCASP_DITCSRA5_DITCSRA5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB0 register. -// -//****************************************************************************** -#define MCASP_DITCSRB0_DITCSRB0_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB0_DITCSRB0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB1 register. -// -//****************************************************************************** -#define MCASP_DITCSRB1_DITCSRB1_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB1_DITCSRB1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB2 register. -// -//****************************************************************************** -#define MCASP_DITCSRB2_DITCSRB2_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB2_DITCSRB2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB3 register. -// -//****************************************************************************** -#define MCASP_DITCSRB3_DITCSRB3_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB3_DITCSRB3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB4 register. -// -//****************************************************************************** -#define MCASP_DITCSRB4_DITCSRB4_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB4_DITCSRB4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB5 register. -// -//****************************************************************************** -#define MCASP_DITCSRB5_DITCSRB5_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB5_DITCSRB5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA0 register. -// -//****************************************************************************** -#define MCASP_DITUDRA0_DITUDRA0_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA0_DITUDRA0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA1 register. -// -//****************************************************************************** -#define MCASP_DITUDRA1_DITUDRA1_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA1_DITUDRA1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA2 register. -// -//****************************************************************************** -#define MCASP_DITUDRA2_DITUDRA2_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA2_DITUDRA2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA3 register. -// -//****************************************************************************** -#define MCASP_DITUDRA3_DITUDRA3_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA3_DITUDRA3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA4 register. -// -//****************************************************************************** -#define MCASP_DITUDRA4_DITUDRA4_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA4_DITUDRA4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA5 register. -// -//****************************************************************************** -#define MCASP_DITUDRA5_DITUDRA5_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA5_DITUDRA5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB0 register. -// -//****************************************************************************** -#define MCASP_DITUDRB0_DITUDRB0_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB0_DITUDRB0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB1 register. -// -//****************************************************************************** -#define MCASP_DITUDRB1_DITUDRB1_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB1_DITUDRB1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB2 register. -// -//****************************************************************************** -#define MCASP_DITUDRB2_DITUDRB2_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB2_DITUDRB2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB3 register. -// -//****************************************************************************** -#define MCASP_DITUDRB3_DITUDRB3_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB3_DITUDRB3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB4 register. -// -//****************************************************************************** -#define MCASP_DITUDRB4_DITUDRB4_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB4_DITUDRB4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB5 register. -// -//****************************************************************************** -#define MCASP_DITUDRB5_DITUDRB5_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB5_DITUDRB5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL0_RRDY 0x00000020 -#define MCASP_XRSRCTL0_XRDY 0x00000010 -#define MCASP_XRSRCTL0_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL0_DISMOD_S 2 -#define MCASP_XRSRCTL0_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL0_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL1_RRDY 0x00000020 -#define MCASP_XRSRCTL1_XRDY 0x00000010 -#define MCASP_XRSRCTL1_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL1_DISMOD_S 2 -#define MCASP_XRSRCTL1_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL1_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL2_RRDY 0x00000020 -#define MCASP_XRSRCTL2_XRDY 0x00000010 -#define MCASP_XRSRCTL2_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL2_DISMOD_S 2 -#define MCASP_XRSRCTL2_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL2_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL3_RRDY 0x00000020 -#define MCASP_XRSRCTL3_XRDY 0x00000010 -#define MCASP_XRSRCTL3_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL3_DISMOD_S 2 -#define MCASP_XRSRCTL3_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL3_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL4_RRDY 0x00000020 -#define MCASP_XRSRCTL4_XRDY 0x00000010 -#define MCASP_XRSRCTL4_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL4_DISMOD_S 2 -#define MCASP_XRSRCTL4_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL4_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL5_RRDY 0x00000020 -#define MCASP_XRSRCTL5_XRDY 0x00000010 -#define MCASP_XRSRCTL5_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL5_DISMOD_S 2 -#define MCASP_XRSRCTL5_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL5_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL6_RRDY 0x00000020 -#define MCASP_XRSRCTL6_XRDY 0x00000010 -#define MCASP_XRSRCTL6_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL6_DISMOD_S 2 -#define MCASP_XRSRCTL6_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL6_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL7_RRDY 0x00000020 -#define MCASP_XRSRCTL7_XRDY 0x00000010 -#define MCASP_XRSRCTL7_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL7_DISMOD_S 2 -#define MCASP_XRSRCTL7_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL7_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL8_RRDY 0x00000020 -#define MCASP_XRSRCTL8_XRDY 0x00000010 -#define MCASP_XRSRCTL8_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL8_DISMOD_S 2 -#define MCASP_XRSRCTL8_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL8_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL9_RRDY 0x00000020 -#define MCASP_XRSRCTL9_XRDY 0x00000010 -#define MCASP_XRSRCTL9_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL9_DISMOD_S 2 -#define MCASP_XRSRCTL9_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL9_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL10_RRDY 0x00000020 -#define MCASP_XRSRCTL10_XRDY 0x00000010 -#define MCASP_XRSRCTL10_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL10_DISMOD_S 2 -#define MCASP_XRSRCTL10_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL10_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL11_RRDY 0x00000020 -#define MCASP_XRSRCTL11_XRDY 0x00000010 -#define MCASP_XRSRCTL11_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL11_DISMOD_S 2 -#define MCASP_XRSRCTL11_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL11_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL12_RRDY 0x00000020 -#define MCASP_XRSRCTL12_XRDY 0x00000010 -#define MCASP_XRSRCTL12_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL12_DISMOD_S 2 -#define MCASP_XRSRCTL12_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL12_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL13_RRDY 0x00000020 -#define MCASP_XRSRCTL13_XRDY 0x00000010 -#define MCASP_XRSRCTL13_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL13_DISMOD_S 2 -#define MCASP_XRSRCTL13_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL13_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL14_RRDY 0x00000020 -#define MCASP_XRSRCTL14_XRDY 0x00000010 -#define MCASP_XRSRCTL14_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL14_DISMOD_S 2 -#define MCASP_XRSRCTL14_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL14_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL15_RRDY 0x00000020 -#define MCASP_XRSRCTL15_XRDY 0x00000010 -#define MCASP_XRSRCTL15_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL15_DISMOD_S 2 -#define MCASP_XRSRCTL15_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL15_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF0 register. -// -//****************************************************************************** -#define MCASP_TXBUF0_XBUF0_M 0xFFFFFFFF // Transmit Buffer 0 -#define MCASP_TXBUF0_XBUF0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF1 register. -// -//****************************************************************************** -#define MCASP_TXBUF1_XBUF1_M 0xFFFFFFFF // Transmit Buffer 1 -#define MCASP_TXBUF1_XBUF1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF2 register. -// -//****************************************************************************** -#define MCASP_TXBUF2_XBUF2_M 0xFFFFFFFF // Transmit Buffer 2 -#define MCASP_TXBUF2_XBUF2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF3 register. -// -//****************************************************************************** -#define MCASP_TXBUF3_XBUF3_M 0xFFFFFFFF // Transmit Buffer 3 -#define MCASP_TXBUF3_XBUF3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF4 register. -// -//****************************************************************************** -#define MCASP_TXBUF4_XBUF4_M 0xFFFFFFFF // Transmit Buffer 4 -#define MCASP_TXBUF4_XBUF4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF5 register. -// -//****************************************************************************** -#define MCASP_TXBUF5_XBUF5_M 0xFFFFFFFF // Transmit Buffer 5 -#define MCASP_TXBUF5_XBUF5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF6 register. -// -//****************************************************************************** -#define MCASP_TXBUF6_XBUF6_M 0xFFFFFFFF // Transmit Buffer 6 -#define MCASP_TXBUF6_XBUF6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF7 register. -// -//****************************************************************************** -#define MCASP_TXBUF7_XBUF7_M 0xFFFFFFFF // Transmit Buffer 7 -#define MCASP_TXBUF7_XBUF7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF8 register. -// -//****************************************************************************** -#define MCASP_TXBUF8_XBUF8_M 0xFFFFFFFF // Transmit Buffer 8 -#define MCASP_TXBUF8_XBUF8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF9 register. -// -//****************************************************************************** -#define MCASP_TXBUF9_XBUF9_M 0xFFFFFFFF // Transmit Buffer 9 -#define MCASP_TXBUF9_XBUF9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF10 register. -// -//****************************************************************************** -#define MCASP_TXBUF10_XBUF10_M 0xFFFFFFFF // Transmit Buffer 10 -#define MCASP_TXBUF10_XBUF10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF11 register. -// -//****************************************************************************** -#define MCASP_TXBUF11_XBUF11_M 0xFFFFFFFF // Transmit Buffer 11 -#define MCASP_TXBUF11_XBUF11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF12 register. -// -//****************************************************************************** -#define MCASP_TXBUF12_XBUF12_M 0xFFFFFFFF // Transmit Buffer 12 -#define MCASP_TXBUF12_XBUF12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF13 register. -// -//****************************************************************************** -#define MCASP_TXBUF13_XBUF13_M 0xFFFFFFFF // Transmit Buffer 13 -#define MCASP_TXBUF13_XBUF13_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF14 register. -// -//****************************************************************************** -#define MCASP_TXBUF14_XBUF14_M 0xFFFFFFFF // Transmit Buffer 14 -#define MCASP_TXBUF14_XBUF14_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF15 register. -// -//****************************************************************************** -#define MCASP_TXBUF15_XBUF15_M 0xFFFFFFFF // Transmit Buffer 15 -#define MCASP_TXBUF15_XBUF15_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF0 register. -// -//****************************************************************************** -#define MCASP_RXBUF0_RBUF0_M 0xFFFFFFFF // Receive Buffer 0 -#define MCASP_RXBUF0_RBUF0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF1 register. -// -//****************************************************************************** -#define MCASP_RXBUF1_RBUF1_M 0xFFFFFFFF // Receive Buffer 1 -#define MCASP_RXBUF1_RBUF1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF2 register. -// -//****************************************************************************** -#define MCASP_RXBUF2_RBUF2_M 0xFFFFFFFF // Receive Buffer 2 -#define MCASP_RXBUF2_RBUF2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF3 register. -// -//****************************************************************************** -#define MCASP_RXBUF3_RBUF3_M 0xFFFFFFFF // Receive Buffer 3 -#define MCASP_RXBUF3_RBUF3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF4 register. -// -//****************************************************************************** -#define MCASP_RXBUF4_RBUF4_M 0xFFFFFFFF // Receive Buffer 4 -#define MCASP_RXBUF4_RBUF4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF5 register. -// -//****************************************************************************** -#define MCASP_RXBUF5_RBUF5_M 0xFFFFFFFF // Receive Buffer 5 -#define MCASP_RXBUF5_RBUF5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF6 register. -// -//****************************************************************************** -#define MCASP_RXBUF6_RBUF6_M 0xFFFFFFFF // Receive Buffer 6 -#define MCASP_RXBUF6_RBUF6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF7 register. -// -//****************************************************************************** -#define MCASP_RXBUF7_RBUF7_M 0xFFFFFFFF // Receive Buffer 7 -#define MCASP_RXBUF7_RBUF7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF8 register. -// -//****************************************************************************** -#define MCASP_RXBUF8_RBUF8_M 0xFFFFFFFF // Receive Buffer 8 -#define MCASP_RXBUF8_RBUF8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF9 register. -// -//****************************************************************************** -#define MCASP_RXBUF9_RBUF9_M 0xFFFFFFFF // Receive Buffer 9 -#define MCASP_RXBUF9_RBUF9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF10 register. -// -//****************************************************************************** -#define MCASP_RXBUF10_RBUF10_M 0xFFFFFFFF // Receive Buffer 10 -#define MCASP_RXBUF10_RBUF10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF11 register. -// -//****************************************************************************** -#define MCASP_RXBUF11_RBUF11_M 0xFFFFFFFF // Receive Buffer 11 -#define MCASP_RXBUF11_RBUF11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF12 register. -// -//****************************************************************************** -#define MCASP_RXBUF12_RBUF12_M 0xFFFFFFFF // Receive Buffer 12 -#define MCASP_RXBUF12_RBUF12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF13 register. -// -//****************************************************************************** -#define MCASP_RXBUF13_RBUF13_M 0xFFFFFFFF // Receive Buffer 13 -#define MCASP_RXBUF13_RBUF13_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF14 register. -// -//****************************************************************************** -#define MCASP_RXBUF14_RBUF14_M 0xFFFFFFFF // Receive Buffer 14 -#define MCASP_RXBUF14_RBUF14_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF15 register. -// -//****************************************************************************** -#define MCASP_RXBUF15_RBUF15_M 0xFFFFFFFF // Receive Buffer 15 -#define MCASP_RXBUF15_RBUF15_S 0 - - - -#endif // __HW_MCASP_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcspi.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcspi.h deleted file mode 100755 index aeddbc2e740..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcspi.h +++ /dev/null @@ -1,1743 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_MCSPI_H__ -#define __HW_MCSPI_H__ - -//***************************************************************************** -// -// The following are defines for the MCSPI register offsets. -// -//***************************************************************************** -#define MCSPI_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) - // Used by software to track - // features bugs and compatibility -#define MCSPI_O_HL_HWINFO 0x00000004 // Information about the IP - // module's hardware configuration - // i.e. typically the module's HDL - // generics (if any). Actual field - // format and encoding is up to the - // module's designer to decide. -#define MCSPI_O_HL_SYSCONFIG 0x00000010 // 0x4402 1010 0x4402 2010 Clock - // management configuration -#define MCSPI_O_REVISION 0x00000100 // 0x4402 1100 0x4402 2100 This - // register contains the hard coded - // RTL revision number. -#define MCSPI_O_SYSCONFIG 0x00000110 // 0x4402 1110 0x4402 2110 This - // register allows controlling - // various parameters of the OCP - // interface. -#define MCSPI_O_SYSSTATUS 0x00000114 // 0x4402 1114 0x4402 2114 This - // register provides status - // information about the module - // excluding the interrupt status - // information -#define MCSPI_O_IRQSTATUS 0x00000118 // 0x4402 1118 0x4402 2118 The - // interrupt status regroups all the - // status of the module internal - // events that can generate an - // interrupt -#define MCSPI_O_IRQENABLE 0x0000011C // 0x4402 111C 0x4402 211C This - // register allows to enable/disable - // the module internal sources of - // interrupt on an event-by-event - // basis. -#define MCSPI_O_WAKEUPENABLE 0x00000120 // 0x4402 1120 0x4402 2120 The - // wakeup enable register allows to - // enable/disable the module - // internal sources of wakeup on - // event-by-event basis. -#define MCSPI_O_SYST 0x00000124 // 0x4402 1124 0x4402 2124 This - // register is used to check the - // correctness of the system - // interconnect either internally to - // peripheral bus or externally to - // device IO pads when the module is - // configured in system test - // (SYSTEST) mode. -#define MCSPI_O_MODULCTRL 0x00000128 // 0x4402 1128 0x4402 2128 This - // register is dedicated to the - // configuration of the serial port - // interface. -#define MCSPI_O_CH0CONF 0x0000012C // 0x4402 112C 0x4402 212C This - // register is dedicated to the - // configuration of the channel 0 -#define MCSPI_O_CH0STAT 0x00000130 // 0x4402 1130 0x4402 2130 This - // register provides status - // information about transmitter and - // receiver registers of channel 0 -#define MCSPI_O_CH0CTRL 0x00000134 // 0x4402 1134 0x4402 2134 This - // register is dedicated to enable - // the channel 0 -#define MCSPI_O_TX0 0x00000138 // 0x4402 1138 0x4402 2138 This - // register contains a single SPI - // word to transmit on the serial - // link what ever SPI word length - // is. -#define MCSPI_O_RX0 0x0000013C // 0x4402 113C 0x4402 213C This - // register contains a single SPI - // word received through the serial - // link what ever SPI word length - // is. -#define MCSPI_O_CH1CONF 0x00000140 // 0x4402 1140 0x4402 2140 This - // register is dedicated to the - // configuration of the channel. -#define MCSPI_O_CH1STAT 0x00000144 // 0x4402 1144 0x4402 2144 This - // register provides status - // information about transmitter and - // receiver registers of channel 1 -#define MCSPI_O_CH1CTRL 0x00000148 // 0x4402 1148 0x4402 2148 This - // register is dedicated to enable - // the channel 1 -#define MCSPI_O_TX1 0x0000014C // 0x4402 114C 0x4402 214C This - // register contains a single SPI - // word to transmit on the serial - // link what ever SPI word length - // is. -#define MCSPI_O_RX1 0x00000150 // 0x4402 1150 0x4402 2150 This - // register contains a single SPI - // word received through the serial - // link what ever SPI word length - // is. -#define MCSPI_O_CH2CONF 0x00000154 // 0x4402 1154 0x4402 2154 This - // register is dedicated to the - // configuration of the channel 2 -#define MCSPI_O_CH2STAT 0x00000158 // 0x4402 1158 0x4402 2158 This - // register provides status - // information about transmitter and - // receiver registers of channel 2 -#define MCSPI_O_CH2CTRL 0x0000015C // 0x4402 115C 0x4402 215C This - // register is dedicated to enable - // the channel 2 -#define MCSPI_O_TX2 0x00000160 // 0x4402 1160 0x4402 2160 This - // register contains a single SPI - // word to transmit on the serial - // link what ever SPI word length - // is. -#define MCSPI_O_RX2 0x00000164 // 0x4402 1164 0x4402 2164 This - // register contains a single SPI - // word received through the serial - // link what ever SPI word length - // is. -#define MCSPI_O_CH3CONF 0x00000168 // 0x4402 1168 0x4402 2168 This - // register is dedicated to the - // configuration of the channel 3 -#define MCSPI_O_CH3STAT 0x0000016C // 0x4402 116C 0x4402 216C This - // register provides status - // information about transmitter and - // receiver registers of channel 3 -#define MCSPI_O_CH3CTRL 0x00000170 // 0x4402 1170 0x4402 2170 This - // register is dedicated to enable - // the channel 3 -#define MCSPI_O_TX3 0x00000174 // 0x4402 1174 0x4402 2174 This - // register contains a single SPI - // word to transmit on the serial - // link what ever SPI word length - // is. -#define MCSPI_O_RX3 0x00000178 // 0x4402 1178 0x4402 2178 This - // register contains a single SPI - // word received through the serial - // link what ever SPI word length - // is. -#define MCSPI_O_XFERLEVEL 0x0000017C // 0x4402 117C 0x4402 217C This - // register provides transfer levels - // needed while using FIFO buffer - // during transfer. -#define MCSPI_O_DAFTX 0x00000180 // 0x4402 1180 0x4402 2180 This - // register contains the SPI words - // to transmit on the serial link - // when FIFO used and DMA address is - // aligned on 256 bit.This register - // is an image of one of MCSPI_TX(i) - // register corresponding to the - // channel which have its FIFO - // enabled. -#define MCSPI_O_DAFRX 0x000001A0 // 0x4402 11A0 0x4402 21A0 This - // register contains the SPI words - // to received on the serial link - // when FIFO used and DMA address is - // aligned on 256 bit.This register - // is an image of one of MCSPI_RX(i) - // register corresponding to the - // channel which have its FIFO - // enabled. - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_HL_REV register. -// -//****************************************************************************** -#define MCSPI_HL_REV_SCHEME_M 0xC0000000 -#define MCSPI_HL_REV_SCHEME_S 30 -#define MCSPI_HL_REV_RSVD_M 0x30000000 // Reserved These bits are - // initialized to zero and writes to - // them are ignored. -#define MCSPI_HL_REV_RSVD_S 28 -#define MCSPI_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define MCSPI_HL_REV_FUNC_S 16 -#define MCSPI_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP - // design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define MCSPI_HL_REV_R_RTL_S 11 -#define MCSPI_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by - // IP specification owner. X changes - // ONLY when: (1) There is a major - // feature addition. An example - // would be adding Master Mode to - // Utopia Level2. The Func field (or - // Class/Type in old PID format) - // will remain the same. X does NOT - // change due to: (1) Bug fixes (2) - // Change in feature parameters. -#define MCSPI_HL_REV_X_MAJOR_S 8 -#define MCSPI_HL_REV_CUSTOM_M 0x000000C0 -#define MCSPI_HL_REV_CUSTOM_S 6 -#define MCSPI_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by - // IP specification owner. Y changes - // ONLY when: (1) Features are - // scaled (up or down). Flexibility - // exists in that this feature - // scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R S X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless the spec tracks the - // IP bugs. An RTL release (say for - // silicon PG1.1) that occurs due to - // bug fix should document the - // corresponding spec number (X.Y.S) - // in its release notes. -#define MCSPI_HL_REV_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register. -// -//****************************************************************************** -#define MCSPI_HL_HWINFO_RETMODE 0x00000040 -#define MCSPI_HL_HWINFO_FFNBYTE_M \ - 0x0000003E - -#define MCSPI_HL_HWINFO_FFNBYTE_S 1 -#define MCSPI_HL_HWINFO_USEFIFO 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// MCSPI_O_HL_SYSCONFIG register. -// -//****************************************************************************** -#define MCSPI_HL_SYSCONFIG_IDLEMODE_M \ - 0x0000000C // Configuration of the local - // target state management mode. By - // definition target can handle - // read/write transaction as long as - // it is out of IDLE state. 0x0 - // Force-idle mode: local target's - // idle state follows (acknowledges) - // the system's idle requests - // unconditionally i.e. regardless - // of the IP module's internal - // requirements.Backup mode for - // debug only. 0x1 No-idle mode: - // local target never enters idle - // state.Backup mode for debug only. - // 0x2 Smart-idle mode: local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module shall not - // generate (IRQ- or - // DMA-request-related) wakeup - // events. 0x3 "Smart-idle - // wakeup-capable mode: local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module may - // generate (IRQ- or - // DMA-request-related) wakeup - // events when in idle state.Mode is - // only relevant if the appropriate - // IP module ""swakeup"" output(s) - // is (are) implemented." - -#define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2 -#define MCSPI_HL_SYSCONFIG_FREEEMU \ - 0x00000002 // Sensitivity to emulation (debug) - // suspend input signal. 0 IP module - // is sensitive to emulation suspend - // 1 IP module is not sensitive to - // emulation suspend - -#define MCSPI_HL_SYSCONFIG_SOFTRESET \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_REVISION register. -// -//****************************************************************************** -#define MCSPI_REVISION_REV_M 0x000000FF // IP revision [7:4] Major revision - // [3:0] Minor revision Examples: - // 0x10 for 1.0 0x21 for 2.1 -#define MCSPI_REVISION_REV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register. -// -//****************************************************************************** -#define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \ - 0x00000300 // Clocks activity during wake up - // mode period 0x0 OCP and - // Functional clocks may be switched - // off. 0x1 OCP clock is maintained. - // Functional clock may be - // switched-off. 0x2 Functional - // clock is maintained. OCP clock - // may be switched-off. 0x3 OCP and - // Functional clocks are maintained. - -#define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8 -#define MCSPI_SYSCONFIG_SIDLEMODE_M \ - 0x00000018 // Power management 0x0 If an idle - // request is detected the McSPI - // acknowledges it unconditionally - // and goes in Inactive mode. - // Interrupt DMA requests and wake - // up lines are unconditionally - // de-asserted and the module wakeup - // capability is deactivated even if - // the bit - // MCSPI_SYSCONFIG[EnaWakeUp] is - // set. 0x1 If an idle request is - // detected the request is ignored - // and the module does not switch to - // wake up mode and keeps on - // behaving normally. 0x2 If an idle - // request is detected the module - // will switch to idle mode based on - // its internal activity. The wake - // up capability cannot be used. 0x3 - // If an idle request is detected - // the module will switch to idle - // mode based on its internal - // activity and the wake up - // capability can be used if the bit - // MCSPI_SYSCONFIG[EnaWakeUp] is - // set. - -#define MCSPI_SYSCONFIG_SIDLEMODE_S 3 -#define MCSPI_SYSCONFIG_ENAWAKEUP \ - 0x00000004 // WakeUp feature control 0 WakeUp - // capability is disabled 1 WakeUp - // capability is enabled - -#define MCSPI_SYSCONFIG_SOFTRESET \ - 0x00000002 // Software reset. During reads it - // always returns 0. 0 (write) - // Normal mode 1 (write) Set this - // bit to 1 to trigger a module - // reset.The bit is automatically - // reset by the hardware. - -#define MCSPI_SYSCONFIG_AUTOIDLE \ - 0x00000001 // Internal OCP Clock gating - // strategy 0 OCP clock is - // free-running 1 Automatic OCP - // clock gating strategy is applied - // based on the OCP interface - // activity - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register. -// -//****************************************************************************** -#define MCSPI_SYSSTATUS_RESETDONE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register. -// -//****************************************************************************** -#define MCSPI_IRQSTATUS_EOW 0x00020000 -#define MCSPI_IRQSTATUS_WKS 0x00010000 -#define MCSPI_IRQSTATUS_RX3_FULL \ - 0x00004000 - -#define MCSPI_IRQSTATUS_TX3_UNDERFLOW \ - 0x00002000 - -#define MCSPI_IRQSTATUS_TX3_EMPTY \ - 0x00001000 - -#define MCSPI_IRQSTATUS_RX2_FULL \ - 0x00000400 - -#define MCSPI_IRQSTATUS_TX2_UNDERFLOW \ - 0x00000200 - -#define MCSPI_IRQSTATUS_TX2_EMPTY \ - 0x00000100 - -#define MCSPI_IRQSTATUS_RX1_FULL \ - 0x00000040 - -#define MCSPI_IRQSTATUS_TX1_UNDERFLOW \ - 0x00000020 - -#define MCSPI_IRQSTATUS_TX1_EMPTY \ - 0x00000010 - -#define MCSPI_IRQSTATUS_RX0_OVERFLOW \ - 0x00000008 - -#define MCSPI_IRQSTATUS_RX0_FULL \ - 0x00000004 - -#define MCSPI_IRQSTATUS_TX0_UNDERFLOW \ - 0x00000002 - -#define MCSPI_IRQSTATUS_TX0_EMPTY \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_IRQENABLE register. -// -//****************************************************************************** -#define MCSPI_IRQENABLE_EOW_ENABLE \ - 0x00020000 // End of Word count Interrupt - // Enable. 0 Interrupt disabled 1 - // Interrupt enabled - -#define MCSPI_IRQENABLE_WKE 0x00010000 // Wake Up event interrupt Enable - // in slave mode when an active - // control signal is detected on the - // SPIEN line programmed in the - // field MCSPI_CH0CONF[SPIENSLV] 0 - // Interrupt disabled 1 Interrupt - // enabled -#define MCSPI_IRQENABLE_RX3_FULL_ENABLE \ - 0x00004000 // Receiver register Full Interrupt - // Enable. Ch 3 0 Interrupt disabled - // 1 Interrupt enabled - -#define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \ - 0x00002000 // Transmitter register Underflow - // Interrupt Enable. Ch 3 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \ - 0x00001000 // Transmitter register Empty - // Interrupt Enable. Ch3 0 Interrupt - // disabled 1 Interrupt enabled - -#define MCSPI_IRQENABLE_RX2_FULL_ENABLE \ - 0x00000400 // Receiver register Full Interrupt - // Enable. Ch 2 0 Interrupt disabled - // 1 Interrupt enabled - -#define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \ - 0x00000200 // Transmitter register Underflow - // Interrupt Enable. Ch 2 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \ - 0x00000100 // Transmitter register Empty - // Interrupt Enable. Ch 2 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_RX1_FULL_ENABLE \ - 0x00000040 // Receiver register Full Interrupt - // Enable. Ch 1 0 Interrupt disabled - // 1 Interrupt enabled - -#define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \ - 0x00000020 // Transmitter register Underflow - // Interrupt Enable. Ch 1 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \ - 0x00000010 // Transmitter register Empty - // Interrupt Enable. Ch 1 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \ - 0x00000008 // Receiver register Overflow - // Interrupt Enable. Ch 0 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_RX0_FULL_ENABLE \ - 0x00000004 // Receiver register Full Interrupt - // Enable. Ch 0 0 Interrupt disabled - // 1 Interrupt enabled - -#define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \ - 0x00000002 // Transmitter register Underflow - // Interrupt Enable. Ch 0 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \ - 0x00000001 // Transmitter register Empty - // Interrupt Enable. Ch 0 0 - // Interrupt disabled 1 Interrupt - // enabled - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// MCSPI_O_WAKEUPENABLE register. -// -//****************************************************************************** -#define MCSPI_WAKEUPENABLE_WKEN 0x00000001 // WakeUp functionality in slave - // mode when an active control - // signal is detected on the SPIEN - // line programmed in the field - // MCSPI_CH0CONF[SPIENSLV] 0 The - // event is not allowed to wakeup - // the system even if the global - // control bit - // MCSPI_SYSCONF[EnaWakeUp] is set. - // 1 The event is allowed to wakeup - // the system if the global control - // bit MCSPI_SYSCONF[EnaWakeUp] is - // set. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_SYST register. -// -//****************************************************************************** -#define MCSPI_SYST_SSB 0x00000800 // Set status bit 0 No action. - // Writing 0 does not clear already - // set status bits; This bit must be - // cleared prior attempting to clear - // a status bit of the - // register. 1 - // Force to 1 all status bits of - // MCSPI_IRQSTATUS register. Writing - // 1 into this bit sets to 1 all - // status bits contained in the - // register. -#define MCSPI_SYST_SPIENDIR 0x00000400 // Set the direction of the - // SPIEN[3:0] lines and SPICLK line - // 0 output (as in master mode) 1 - // input (as in slave mode) -#define MCSPI_SYST_SPIDATDIR1 0x00000200 // Set the direction of the - // SPIDAT[1] 0 output 1 input -#define MCSPI_SYST_SPIDATDIR0 0x00000100 // Set the direction of the - // SPIDAT[0] 0 output 1 input -#define MCSPI_SYST_WAKD 0x00000080 // SWAKEUP output (signal data - // value of internal signal to - // system). The signal is driven - // high or low according to the - // value written into this register - // bit. 0 The pin is driven low. 1 - // The pin is driven high. -#define MCSPI_SYST_SPICLK 0x00000040 // SPICLK line (signal data value) - // If MCSPI_SYST[SPIENDIR] = 1 - // (input mode direction) this bit - // returns the value on the CLKSPI - // line (high or low) and a write - // into this bit has no effect. If - // MCSPI_SYST[SPIENDIR] = 0 (output - // mode direction) the CLKSPI line - // is driven high or low according - // to the value written into this - // register. -#define MCSPI_SYST_SPIDAT_1 0x00000020 // SPIDAT[1] line (signal data - // value) If MCSPI_SYST[SPIDATDIR1] - // = 0 (output mode direction) the - // SPIDAT[1] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIDATDIR1] = 1 (input - // mode direction) this bit returns - // the value on the SPIDAT[1] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIDAT_0 0x00000010 // SPIDAT[0] line (signal data - // value) If MCSPI_SYST[SPIDATDIR0] - // = 0 (output mode direction) the - // SPIDAT[0] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIDATDIR0] = 1 (input - // mode direction) this bit returns - // the value on the SPIDAT[0] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIEN_3 0x00000008 // SPIEN[3] line (signal data - // value) If MCSPI_SYST[SPIENDIR] = - // 0 (output mode direction) the - // SPIENT[3] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIENDIR] = 1 (input - // mode direction) this bit returns - // the value on the SPIEN[3] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIEN_2 0x00000004 // SPIEN[2] line (signal data - // value) If MCSPI_SYST[SPIENDIR] = - // 0 (output mode direction) the - // SPIENT[2] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIENDIR] = 1 (input - // mode direction) this bit returns - // the value on the SPIEN[2] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIEN_1 0x00000002 // SPIEN[1] line (signal data - // value) If MCSPI_SYST[SPIENDIR] = - // 0 (output mode direction) the - // SPIENT[1] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIENDIR] = 1 (input - // mode direction) this bit returns - // the value on the SPIEN[1] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIEN_0 0x00000001 // SPIEN[0] line (signal data - // value) If MCSPI_SYST[SPIENDIR] = - // 0 (output mode direction) the - // SPIENT[0] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIENDIR] = 1 (input - // mode direction) this bit returns - // the value on the SPIEN[0] line - // (high or low) and a write into - // this bit has no effect. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_MODULCTRL register. -// -//****************************************************************************** -#define MCSPI_MODULCTRL_FDAA 0x00000100 // FIFO DMA Address 256-bit aligned - // This register is used when a FIFO - // is managed by the module and DMA - // connected to the controller - // provides only 256 bit aligned - // address. If this bit is set the - // enabled channel which uses the - // FIFO has its datas managed - // through MCSPI_DAFTX and - // MCSPI_DAFRX registers instead of - // MCSPI_TX(i) and MCSPI_RX(i) - // registers. 0 FIFO data managed by - // MCSPI_TX(i) and MCSPI_RX(i) - // registers. 1 FIFO data managed by - // MCSPI_DAFTX and MCSPI_DAFRX - // registers. -#define MCSPI_MODULCTRL_MOA 0x00000080 // Multiple word ocp access: This - // register can only be used when a - // channel is enabled using a FIFO. - // It allows the system to perform - // multiple SPI word access for a - // single 32-bit OCP word access. - // This is possible for WL < 16. 0 - // Multiple word access disabled 1 - // Multiple word access enabled with - // FIFO -#define MCSPI_MODULCTRL_INITDLY_M \ - 0x00000070 // Initial spi delay for first - // transfer: This register is an - // option only available in SINGLE - // master mode The controller waits - // for a delay to transmit the first - // spi word after channel enabled - // and corresponding TX register - // filled. This Delay is based on - // SPI output frequency clock No - // clock output provided to the - // boundary and chip select is not - // active in 4 pin mode within this - // period. 0x0 No delay for first - // spi transfer. 0x1 The controller - // wait 4 spi bus clock 0x2 The - // controller wait 8 spi bus clock - // 0x3 The controller wait 16 spi - // bus clock 0x4 The controller wait - // 32 spi bus clock - -#define MCSPI_MODULCTRL_INITDLY_S 4 -#define MCSPI_MODULCTRL_SYSTEM_TEST \ - 0x00000008 // Enables the system test mode 0 - // Functional mode 1 System test - // mode (SYSTEST) - -#define MCSPI_MODULCTRL_MS 0x00000004 // Master/ Slave 0 Master - The - // module generates the SPICLK and - // SPIEN[3:0] 1 Slave - The module - // receives the SPICLK and - // SPIEN[3:0] -#define MCSPI_MODULCTRL_PIN34 0x00000002 // Pin mode selection: This - // register is used to configure the - // SPI pin mode in master or slave - // mode. If asserted the controller - // only use SIMOSOMI and SPICLK - // clock pin for spi transfers. 0 - // SPIEN is used as a chip select. 1 - // SPIEN is not used.In this mode - // all related option to chip select - // have no meaning. -#define MCSPI_MODULCTRL_SINGLE 0x00000001 // Single channel / Multi Channel - // (master mode only) 0 More than - // one channel will be used in - // master mode. 1 Only one channel - // will be used in master mode. This - // bit must be set in Force SPIEN - // mode. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH0CONF register. -// -//****************************************************************************** -#define MCSPI_CH0CONF_CLKG 0x20000000 // Clock divider granularity This - // register defines the granularity - // of channel clock divider: power - // of two or one clock cycle - // granularity. When this bit is set - // the register MCSPI_CHCTRL[EXTCLK] - // must be configured to reach a - // maximum of 4096 clock divider - // ratio. Then The clock divider - // ratio is a concatenation of - // MCSPI_CHCONF[CLKD] and - // MCSPI_CHCTRL[EXTCLK] values 0 - // Clock granularity of power of two - // 1 One clock cycle ganularity -#define MCSPI_CH0CONF_FFER 0x10000000 // FIFO enabled for receive:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to receive data. 1 The - // buffer is used to receive data. -#define MCSPI_CH0CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to transmit data. 1 The - // buffer is used to transmit data. -#define MCSPI_CH0CONF_TCS0_M 0x06000000 // Chip Select Time Control This - // 2-bits field defines the number - // of interface clock cycles between - // CS toggling and first or last - // edge of SPI clock. 0x0 0.5 clock - // cycle 0x1 1.5 clock cycle 0x2 2.5 - // clock cycle 0x3 3.5 clock cycle -#define MCSPI_CH0CONF_TCS0_S 25 -#define MCSPI_CH0CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit - // polarity is held to 0 during SPI - // transfer. 1 Start bit polarity is - // held to 1 during SPI transfer. -#define MCSPI_CH0CONF_SBE 0x00800000 // Start bit enable for SPI - // transfer 0 Default SPI transfer - // length as specified by WL bit - // field 1 Start bit D/CX added - // before SPI transfer polarity is - // defined by MCSPI_CH0CONF[SBPOL] -#define MCSPI_CH0CONF_SPIENSLV_M \ - 0x00600000 // Channel 0 only and slave mode - // only: SPI slave select signal - // detection. Reserved bits for - // other cases. 0x0 Detection - // enabled only on SPIEN[0] 0x1 - // Detection enabled only on - // SPIEN[1] 0x2 Detection enabled - // only on SPIEN[2] 0x3 Detection - // enabled only on SPIEN[3] - -#define MCSPI_CH0CONF_SPIENSLV_S 21 -#define MCSPI_CH0CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep - // SPIEN active between SPI words. - // (single channel master mode only) - // 0 Writing 0 into this bit drives - // low the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it high when - // MCSPI_CHCONF(i)[EPOL]=1. 1 - // Writing 1 into this bit drives - // high the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it low when - // MCSPI_CHCONF(i)[EPOL]=1 -#define MCSPI_CH0CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is - // deactivated (recommended for - // single SPI word transfer) 1 Turbo - // is activated to maximize the - // throughput for multi SPI words - // transfer. -#define MCSPI_CH0CONF_IS 0x00040000 // Input Select 0 Data Line0 - // (SPIDAT[0]) selected for - // reception. 1 Data Line1 - // (SPIDAT[1]) selected for - // reception -#define MCSPI_CH0CONF_DPE1 0x00020000 // Transmission Enable for data - // line 1 (SPIDATAGZEN[1]) 0 Data - // Line1 (SPIDAT[1]) selected for - // transmission 1 No transmission on - // Data Line1 (SPIDAT[1]) -#define MCSPI_CH0CONF_DPE0 0x00010000 // Transmission Enable for data - // line 0 (SPIDATAGZEN[0]) 0 Data - // Line0 (SPIDAT[0]) selected for - // transmission 1 No transmission on - // Data Line0 (SPIDAT[0]) -#define MCSPI_CH0CONF_DMAR 0x00008000 // DMA Read request The DMA Read - // request line is asserted when the - // channel is enabled and a new data - // is available in the receive - // register of the channel. The DMA - // Read request line is deasserted - // on read completion of the receive - // register of the channel. 0 DMA - // Read Request disabled 1 DMA Read - // Request enabled -#define MCSPI_CH0CONF_DMAW 0x00004000 // DMA Write request. The DMA Write - // request line is asserted when The - // channel is enabled and the - // transmitter register of the - // channel is empty. The DMA Write - // request line is deasserted on - // load completion of the - // transmitter register of the - // channel. 0 DMA Write Request - // disabled 1 DMA Write Request - // enabled -#define MCSPI_CH0CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 - // Transmit and Receive mode 0x1 - // Receive only mode 0x2 Transmit - // only mode 0x3 Reserved -#define MCSPI_CH0CONF_TRM_S 12 -#define MCSPI_CH0CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved - // 0x01 Reserved 0x02 Reserved 0x03 - // The SPI word is 4-bits long 0x04 - // The SPI word is 5-bits long 0x05 - // The SPI word is 6-bits long 0x06 - // The SPI word is 7-bits long 0x07 - // The SPI word is 8-bits long 0x08 - // The SPI word is 9-bits long 0x09 - // The SPI word is 10-bits long 0x0A - // The SPI word is 11-bits long 0x0B - // The SPI word is 12-bits long 0x0C - // The SPI word is 13-bits long 0x0D - // The SPI word is 14-bits long 0x0E - // The SPI word is 15-bits long 0x0F - // The SPI word is 16-bits long 0x10 - // The SPI word is 17-bits long 0x11 - // The SPI word is 18-bits long 0x12 - // The SPI word is 19-bits long 0x13 - // The SPI word is 20-bits long 0x14 - // The SPI word is 21-bits long 0x15 - // The SPI word is 22-bits long 0x16 - // The SPI word is 23-bits long 0x17 - // The SPI word is 24-bits long 0x18 - // The SPI word is 25-bits long 0x19 - // The SPI word is 26-bits long 0x1A - // The SPI word is 27-bits long 0x1B - // The SPI word is 28-bits long 0x1C - // The SPI word is 29-bits long 0x1D - // The SPI word is 30-bits long 0x1E - // The SPI word is 31-bits long 0x1F - // The SPI word is 32-bits long -#define MCSPI_CH0CONF_WL_S 7 -#define MCSPI_CH0CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held - // high during the active state. 1 - // SPIEN is held low during the - // active state. -#define MCSPI_CH0CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. - // (only when the module is a Master - // SPI device). A programmable clock - // divider divides the SPI reference - // clock (CLKSPIREF) with a 4-bit - // value and results in a new clock - // SPICLK available to shift-in and - // shift-out data. By default the - // clock divider ratio has a power - // of two granularity when - // MCSPI_CHCONF[CLKG] is cleared - // Otherwise this register is the 4 - // LSB bit of a 12-bit register - // concatenated with clock divider - // extension MCSPI_CHCTRL[EXTCLK] - // register.The value description - // below defines the clock ratio - // when MCSPI_CHCONF[CLKG] is set to - // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 - // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 - // 512 0xA 1024 0xB 2048 0xC 4096 - // 0xD 8192 0xE 16384 0xF 32768 -#define MCSPI_CH0CONF_CLKD_S 2 -#define MCSPI_CH0CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held - // high during the active state 1 - // SPICLK is held low during the - // active state -#define MCSPI_CH0CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched - // on odd numbered edges of SPICLK. - // 1 Data are latched on even - // numbered edges of SPICLK. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH0STAT register. -// -//****************************************************************************** -#define MCSPI_CH0STAT_RXFFF 0x00000040 -#define MCSPI_CH0STAT_RXFFE 0x00000020 -#define MCSPI_CH0STAT_TXFFF 0x00000010 -#define MCSPI_CH0STAT_TXFFE 0x00000008 -#define MCSPI_CH0STAT_EOT 0x00000004 -#define MCSPI_CH0STAT_TXS 0x00000002 -#define MCSPI_CH0STAT_RXS 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH0CTRL register. -// -//****************************************************************************** -#define MCSPI_CH0CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This - // register is used to concatenate - // with MCSPI_CHCONF[CLKD] register - // for clock ratio only when - // granularity is one clock cycle - // (MCSPI_CHCONF[CLKG] set to 1). - // Then the max value reached is - // 4096 clock divider ratio. 0x00 - // Clock ratio is CLKD + 1 0x01 - // Clock ratio is CLKD + 1 + 16 0xFF - // Clock ratio is CLKD + 1 + 4080 -#define MCSPI_CH0CTRL_EXTCLK_S 8 -#define MCSPI_CH0CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" - // is not active" 1 "Channel ""i"" - // is active" -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_TX0 register. -// -//****************************************************************************** -#define MCSPI_TX0_TDATA_M 0xFFFFFFFF // Channel 0 Data to transmit -#define MCSPI_TX0_TDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_RX0 register. -// -//****************************************************************************** -#define MCSPI_RX0_RDATA_M 0xFFFFFFFF // Channel 0 Received Data -#define MCSPI_RX0_RDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH1CONF register. -// -//****************************************************************************** -#define MCSPI_CH1CONF_CLKG 0x20000000 // Clock divider granularity This - // register defines the granularity - // of channel clock divider: power - // of two or one clock cycle - // granularity. When this bit is set - // the register MCSPI_CHCTRL[EXTCLK] - // must be configured to reach a - // maximum of 4096 clock divider - // ratio. Then The clock divider - // ratio is a concatenation of - // MCSPI_CHCONF[CLKD] and - // MCSPI_CHCTRL[EXTCLK] values 0 - // Clock granularity of power of two - // 1 One clock cycle ganularity -#define MCSPI_CH1CONF_FFER 0x10000000 // FIFO enabled for receive:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to receive data. 1 The - // buffer is used to receive data. -#define MCSPI_CH1CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to transmit data. 1 The - // buffer is used to transmit data. -#define MCSPI_CH1CONF_TCS1_M 0x06000000 // Chip Select Time Control This - // 2-bits field defines the number - // of interface clock cycles between - // CS toggling and first or last - // edge of SPI clock. 0x0 0.5 clock - // cycle 0x1 1.5 clock cycle 0x2 2.5 - // clock cycle 0x3 3.5 clock cycle -#define MCSPI_CH1CONF_TCS1_S 25 -#define MCSPI_CH1CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit - // polarity is held to 0 during SPI - // transfer. 1 Start bit polarity is - // held to 1 during SPI transfer. -#define MCSPI_CH1CONF_SBE 0x00800000 // Start bit enable for SPI - // transfer 0 Default SPI transfer - // length as specified by WL bit - // field 1 Start bit D/CX added - // before SPI transfer polarity is - // defined by MCSPI_CH1CONF[SBPOL] -#define MCSPI_CH1CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep - // SPIEN active between SPI words. - // (single channel master mode only) - // 0 Writing 0 into this bit drives - // low the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it high when - // MCSPI_CHCONF(i)[EPOL]=1. 1 - // Writing 1 into this bit drives - // high the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it low when - // MCSPI_CHCONF(i)[EPOL]=1 -#define MCSPI_CH1CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is - // deactivated (recommended for - // single SPI word transfer) 1 Turbo - // is activated to maximize the - // throughput for multi SPI words - // transfer. -#define MCSPI_CH1CONF_IS 0x00040000 // Input Select 0 Data Line0 - // (SPIDAT[0]) selected for - // reception. 1 Data Line1 - // (SPIDAT[1]) selected for - // reception -#define MCSPI_CH1CONF_DPE1 0x00020000 // Transmission Enable for data - // line 1 (SPIDATAGZEN[1]) 0 Data - // Line1 (SPIDAT[1]) selected for - // transmission 1 No transmission on - // Data Line1 (SPIDAT[1]) -#define MCSPI_CH1CONF_DPE0 0x00010000 // Transmission Enable for data - // line 0 (SPIDATAGZEN[0]) 0 Data - // Line0 (SPIDAT[0]) selected for - // transmission 1 No transmission on - // Data Line0 (SPIDAT[0]) -#define MCSPI_CH1CONF_DMAR 0x00008000 // DMA Read request The DMA Read - // request line is asserted when the - // channel is enabled and a new data - // is available in the receive - // register of the channel. The DMA - // Read request line is deasserted - // on read completion of the receive - // register of the channel. 0 DMA - // Read Request disabled 1 DMA Read - // Request enabled -#define MCSPI_CH1CONF_DMAW 0x00004000 // DMA Write request. The DMA Write - // request line is asserted when The - // channel is enabled and the - // transmitter register of the - // channel is empty. The DMA Write - // request line is deasserted on - // load completion of the - // transmitter register of the - // channel. 0 DMA Write Request - // disabled 1 DMA Write Request - // enabled -#define MCSPI_CH1CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 - // Transmit and Receive mode 0x1 - // Receive only mode 0x2 Transmit - // only mode 0x3 Reserved -#define MCSPI_CH1CONF_TRM_S 12 -#define MCSPI_CH1CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved - // 0x01 Reserved 0x02 Reserved 0x03 - // The SPI word is 4-bits long 0x04 - // The SPI word is 5-bits long 0x05 - // The SPI word is 6-bits long 0x06 - // The SPI word is 7-bits long 0x07 - // The SPI word is 8-bits long 0x08 - // The SPI word is 9-bits long 0x09 - // The SPI word is 10-bits long 0x0A - // The SPI word is 11-bits long 0x0B - // The SPI word is 12-bits long 0x0C - // The SPI word is 13-bits long 0x0D - // The SPI word is 14-bits long 0x0E - // The SPI word is 15-bits long 0x0F - // The SPI word is 16-bits long 0x10 - // The SPI word is 17-bits long 0x11 - // The SPI word is 18-bits long 0x12 - // The SPI word is 19-bits long 0x13 - // The SPI word is 20-bits long 0x14 - // The SPI word is 21-bits long 0x15 - // The SPI word is 22-bits long 0x16 - // The SPI word is 23-bits long 0x17 - // The SPI word is 24-bits long 0x18 - // The SPI word is 25-bits long 0x19 - // The SPI word is 26-bits long 0x1A - // The SPI word is 27-bits long 0x1B - // The SPI word is 28-bits long 0x1C - // The SPI word is 29-bits long 0x1D - // The SPI word is 30-bits long 0x1E - // The SPI word is 31-bits long 0x1F - // The SPI word is 32-bits long -#define MCSPI_CH1CONF_WL_S 7 -#define MCSPI_CH1CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held - // high during the active state. 1 - // SPIEN is held low during the - // active state. -#define MCSPI_CH1CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. - // (only when the module is a Master - // SPI device). A programmable clock - // divider divides the SPI reference - // clock (CLKSPIREF) with a 4-bit - // value and results in a new clock - // SPICLK available to shift-in and - // shift-out data. By default the - // clock divider ratio has a power - // of two granularity when - // MCSPI_CHCONF[CLKG] is cleared - // Otherwise this register is the 4 - // LSB bit of a 12-bit register - // concatenated with clock divider - // extension MCSPI_CHCTRL[EXTCLK] - // register.The value description - // below defines the clock ratio - // when MCSPI_CHCONF[CLKG] is set to - // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 - // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 - // 512 0xA 1024 0xB 2048 0xC 4096 - // 0xD 8192 0xE 16384 0xF 32768 -#define MCSPI_CH1CONF_CLKD_S 2 -#define MCSPI_CH1CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held - // high during the active state 1 - // SPICLK is held low during the - // active state -#define MCSPI_CH1CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched - // on odd numbered edges of SPICLK. - // 1 Data are latched on even - // numbered edges of SPICLK. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH1STAT register. -// -//****************************************************************************** -#define MCSPI_CH1STAT_RXFFF 0x00000040 -#define MCSPI_CH1STAT_RXFFE 0x00000020 -#define MCSPI_CH1STAT_TXFFF 0x00000010 -#define MCSPI_CH1STAT_TXFFE 0x00000008 -#define MCSPI_CH1STAT_EOT 0x00000004 -#define MCSPI_CH1STAT_TXS 0x00000002 -#define MCSPI_CH1STAT_RXS 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH1CTRL register. -// -//****************************************************************************** -#define MCSPI_CH1CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This - // register is used to concatenate - // with MCSPI_CHCONF[CLKD] register - // for clock ratio only when - // granularity is one clock cycle - // (MCSPI_CHCONF[CLKG] set to 1). - // Then the max value reached is - // 4096 clock divider ratio. 0x00 - // Clock ratio is CLKD + 1 0x01 - // Clock ratio is CLKD + 1 + 16 0xFF - // Clock ratio is CLKD + 1 + 4080 -#define MCSPI_CH1CTRL_EXTCLK_S 8 -#define MCSPI_CH1CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" - // is not active" 1 "Channel ""i"" - // is active" -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_TX1 register. -// -//****************************************************************************** -#define MCSPI_TX1_TDATA_M 0xFFFFFFFF // Channel 1 Data to transmit -#define MCSPI_TX1_TDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_RX1 register. -// -//****************************************************************************** -#define MCSPI_RX1_RDATA_M 0xFFFFFFFF // Channel 1 Received Data -#define MCSPI_RX1_RDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH2CONF register. -// -//****************************************************************************** -#define MCSPI_CH2CONF_CLKG 0x20000000 // Clock divider granularity This - // register defines the granularity - // of channel clock divider: power - // of two or one clock cycle - // granularity. When this bit is set - // the register MCSPI_CHCTRL[EXTCLK] - // must be configured to reach a - // maximum of 4096 clock divider - // ratio. Then The clock divider - // ratio is a concatenation of - // MCSPI_CHCONF[CLKD] and - // MCSPI_CHCTRL[EXTCLK] values 0 - // Clock granularity of power of two - // 1 One clock cycle ganularity -#define MCSPI_CH2CONF_FFER 0x10000000 // FIFO enabled for receive:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to receive data. 1 The - // buffer is used to receive data. -#define MCSPI_CH2CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to transmit data. 1 The - // buffer is used to transmit data. -#define MCSPI_CH2CONF_TCS2_M 0x06000000 // Chip Select Time Control This - // 2-bits field defines the number - // of interface clock cycles between - // CS toggling and first or last - // edge of SPI clock. 0x0 0.5 clock - // cycle 0x1 1.5 clock cycle 0x2 2.5 - // clock cycle 0x3 3.5 clock cycle -#define MCSPI_CH2CONF_TCS2_S 25 -#define MCSPI_CH2CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit - // polarity is held to 0 during SPI - // transfer. 1 Start bit polarity is - // held to 1 during SPI transfer. -#define MCSPI_CH2CONF_SBE 0x00800000 // Start bit enable for SPI - // transfer 0 Default SPI transfer - // length as specified by WL bit - // field 1 Start bit D/CX added - // before SPI transfer polarity is - // defined by MCSPI_CH2CONF[SBPOL] -#define MCSPI_CH2CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep - // SPIEN active between SPI words. - // (single channel master mode only) - // 0 Writing 0 into this bit drives - // low the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it high when - // MCSPI_CHCONF(i)[EPOL]=1. 1 - // Writing 1 into this bit drives - // high the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it low when - // MCSPI_CHCONF(i)[EPOL]=1 -#define MCSPI_CH2CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is - // deactivated (recommended for - // single SPI word transfer) 1 Turbo - // is activated to maximize the - // throughput for multi SPI words - // transfer. -#define MCSPI_CH2CONF_IS 0x00040000 // Input Select 0 Data Line0 - // (SPIDAT[0]) selected for - // reception. 1 Data Line1 - // (SPIDAT[1]) selected for - // reception -#define MCSPI_CH2CONF_DPE1 0x00020000 // Transmission Enable for data - // line 1 (SPIDATAGZEN[1]) 0 Data - // Line1 (SPIDAT[1]) selected for - // transmission 1 No transmission on - // Data Line1 (SPIDAT[1]) -#define MCSPI_CH2CONF_DPE0 0x00010000 // Transmission Enable for data - // line 0 (SPIDATAGZEN[0]) 0 Data - // Line0 (SPIDAT[0]) selected for - // transmission 1 No transmission on - // Data Line0 (SPIDAT[0]) -#define MCSPI_CH2CONF_DMAR 0x00008000 // DMA Read request The DMA Read - // request line is asserted when the - // channel is enabled and a new data - // is available in the receive - // register of the channel. The DMA - // Read request line is deasserted - // on read completion of the receive - // register of the channel. 0 DMA - // Read Request disabled 1 DMA Read - // Request enabled -#define MCSPI_CH2CONF_DMAW 0x00004000 // DMA Write request. The DMA Write - // request line is asserted when The - // channel is enabled and the - // transmitter register of the - // channel is empty. The DMA Write - // request line is deasserted on - // load completion of the - // transmitter register of the - // channel. 0 DMA Write Request - // disabled 1 DMA Write Request - // enabled -#define MCSPI_CH2CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 - // Transmit and Receive mode 0x1 - // Receive only mode 0x2 Transmit - // only mode 0x3 Reserved -#define MCSPI_CH2CONF_TRM_S 12 -#define MCSPI_CH2CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved - // 0x01 Reserved 0x02 Reserved 0x03 - // The SPI word is 4-bits long 0x04 - // The SPI word is 5-bits long 0x05 - // The SPI word is 6-bits long 0x06 - // The SPI word is 7-bits long 0x07 - // The SPI word is 8-bits long 0x08 - // The SPI word is 9-bits long 0x09 - // The SPI word is 10-bits long 0x0A - // The SPI word is 11-bits long 0x0B - // The SPI word is 12-bits long 0x0C - // The SPI word is 13-bits long 0x0D - // The SPI word is 14-bits long 0x0E - // The SPI word is 15-bits long 0x0F - // The SPI word is 16-bits long 0x10 - // The SPI word is 17-bits long 0x11 - // The SPI word is 18-bits long 0x12 - // The SPI word is 19-bits long 0x13 - // The SPI word is 20-bits long 0x14 - // The SPI word is 21-bits long 0x15 - // The SPI word is 22-bits long 0x16 - // The SPI word is 23-bits long 0x17 - // The SPI word is 24-bits long 0x18 - // The SPI word is 25-bits long 0x19 - // The SPI word is 26-bits long 0x1A - // The SPI word is 27-bits long 0x1B - // The SPI word is 28-bits long 0x1C - // The SPI word is 29-bits long 0x1D - // The SPI word is 30-bits long 0x1E - // The SPI word is 31-bits long 0x1F - // The SPI word is 32-bits long -#define MCSPI_CH2CONF_WL_S 7 -#define MCSPI_CH2CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held - // high during the active state. 1 - // SPIEN is held low during the - // active state. -#define MCSPI_CH2CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. - // (only when the module is a Master - // SPI device). A programmable clock - // divider divides the SPI reference - // clock (CLKSPIREF) with a 4-bit - // value and results in a new clock - // SPICLK available to shift-in and - // shift-out data. By default the - // clock divider ratio has a power - // of two granularity when - // MCSPI_CHCONF[CLKG] is cleared - // Otherwise this register is the 4 - // LSB bit of a 12-bit register - // concatenated with clock divider - // extension MCSPI_CHCTRL[EXTCLK] - // register.The value description - // below defines the clock ratio - // when MCSPI_CHCONF[CLKG] is set to - // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 - // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 - // 512 0xA 1024 0xB 2048 0xC 4096 - // 0xD 8192 0xE 16384 0xF 32768 -#define MCSPI_CH2CONF_CLKD_S 2 -#define MCSPI_CH2CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held - // high during the active state 1 - // SPICLK is held low during the - // active state -#define MCSPI_CH2CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched - // on odd numbered edges of SPICLK. - // 1 Data are latched on even - // numbered edges of SPICLK. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH2STAT register. -// -//****************************************************************************** -#define MCSPI_CH2STAT_RXFFF 0x00000040 -#define MCSPI_CH2STAT_RXFFE 0x00000020 -#define MCSPI_CH2STAT_TXFFF 0x00000010 -#define MCSPI_CH2STAT_TXFFE 0x00000008 -#define MCSPI_CH2STAT_EOT 0x00000004 -#define MCSPI_CH2STAT_TXS 0x00000002 -#define MCSPI_CH2STAT_RXS 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH2CTRL register. -// -//****************************************************************************** -#define MCSPI_CH2CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This - // register is used to concatenate - // with MCSPI_CHCONF[CLKD] register - // for clock ratio only when - // granularity is one clock cycle - // (MCSPI_CHCONF[CLKG] set to 1). - // Then the max value reached is - // 4096 clock divider ratio. 0x00 - // Clock ratio is CLKD + 1 0x01 - // Clock ratio is CLKD + 1 + 16 0xFF - // Clock ratio is CLKD + 1 + 4080 -#define MCSPI_CH2CTRL_EXTCLK_S 8 -#define MCSPI_CH2CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" - // is not active" 1 "Channel ""i"" - // is active" -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_TX2 register. -// -//****************************************************************************** -#define MCSPI_TX2_TDATA_M 0xFFFFFFFF // Channel 2 Data to transmit -#define MCSPI_TX2_TDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_RX2 register. -// -//****************************************************************************** -#define MCSPI_RX2_RDATA_M 0xFFFFFFFF // Channel 2 Received Data -#define MCSPI_RX2_RDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH3CONF register. -// -//****************************************************************************** -#define MCSPI_CH3CONF_CLKG 0x20000000 // Clock divider granularity This - // register defines the granularity - // of channel clock divider: power - // of two or one clock cycle - // granularity. When this bit is set - // the register MCSPI_CHCTRL[EXTCLK] - // must be configured to reach a - // maximum of 4096 clock divider - // ratio. Then The clock divider - // ratio is a concatenation of - // MCSPI_CHCONF[CLKD] and - // MCSPI_CHCTRL[EXTCLK] values 0 - // Clock granularity of power of two - // 1 One clock cycle ganularity -#define MCSPI_CH3CONF_FFER 0x10000000 // FIFO enabled for receive:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to receive data. 1 The - // buffer is used to receive data. -#define MCSPI_CH3CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to transmit data. 1 The - // buffer is used to transmit data. -#define MCSPI_CH3CONF_TCS3_M 0x06000000 // Chip Select Time Control This - // 2-bits field defines the number - // of interface clock cycles between - // CS toggling and first or last - // edge of SPI clock. 0x0 0.5 clock - // cycle 0x1 1.5 clock cycle 0x2 2.5 - // clock cycle 0x3 3.5 clock cycle -#define MCSPI_CH3CONF_TCS3_S 25 -#define MCSPI_CH3CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit - // polarity is held to 0 during SPI - // transfer. 1 Start bit polarity is - // held to 1 during SPI transfer. -#define MCSPI_CH3CONF_SBE 0x00800000 // Start bit enable for SPI - // transfer 0 Default SPI transfer - // length as specified by WL bit - // field 1 Start bit D/CX added - // before SPI transfer polarity is - // defined by MCSPI_CH3CONF[SBPOL] -#define MCSPI_CH3CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep - // SPIEN active between SPI words. - // (single channel master mode only) - // 0 Writing 0 into this bit drives - // low the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it high when - // MCSPI_CHCONF(i)[EPOL]=1. 1 - // Writing 1 into this bit drives - // high the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it low when - // MCSPI_CHCONF(i)[EPOL]=1 -#define MCSPI_CH3CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is - // deactivated (recommended for - // single SPI word transfer) 1 Turbo - // is activated to maximize the - // throughput for multi SPI words - // transfer. -#define MCSPI_CH3CONF_IS 0x00040000 // Input Select 0 Data Line0 - // (SPIDAT[0]) selected for - // reception. 1 Data Line1 - // (SPIDAT[1]) selected for - // reception -#define MCSPI_CH3CONF_DPE1 0x00020000 // Transmission Enable for data - // line 1 (SPIDATAGZEN[1]) 0 Data - // Line1 (SPIDAT[1]) selected for - // transmission 1 No transmission on - // Data Line1 (SPIDAT[1]) -#define MCSPI_CH3CONF_DPE0 0x00010000 // Transmission Enable for data - // line 0 (SPIDATAGZEN[0]) 0 Data - // Line0 (SPIDAT[0]) selected for - // transmission 1 No transmission on - // Data Line0 (SPIDAT[0]) -#define MCSPI_CH3CONF_DMAR 0x00008000 // DMA Read request The DMA Read - // request line is asserted when the - // channel is enabled and a new data - // is available in the receive - // register of the channel. The DMA - // Read request line is deasserted - // on read completion of the receive - // register of the channel. 0 DMA - // Read Request disabled 1 DMA Read - // Request enabled -#define MCSPI_CH3CONF_DMAW 0x00004000 // DMA Write request. The DMA Write - // request line is asserted when The - // channel is enabled and the - // transmitter register of the - // channel is empty. The DMA Write - // request line is deasserted on - // load completion of the - // transmitter register of the - // channel. 0 DMA Write Request - // disabled 1 DMA Write Request - // enabled -#define MCSPI_CH3CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 - // Transmit and Receive mode 0x1 - // Receive only mode 0x2 Transmit - // only mode 0x3 Reserved -#define MCSPI_CH3CONF_TRM_S 12 -#define MCSPI_CH3CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved - // 0x01 Reserved 0x02 Reserved 0x03 - // The SPI word is 4-bits long 0x04 - // The SPI word is 5-bits long 0x05 - // The SPI word is 6-bits long 0x06 - // The SPI word is 7-bits long 0x07 - // The SPI word is 8-bits long 0x08 - // The SPI word is 9-bits long 0x09 - // The SPI word is 10-bits long 0x0A - // The SPI word is 11-bits long 0x0B - // The SPI word is 12-bits long 0x0C - // The SPI word is 13-bits long 0x0D - // The SPI word is 14-bits long 0x0E - // The SPI word is 15-bits long 0x0F - // The SPI word is 16-bits long 0x10 - // The SPI word is 17-bits long 0x11 - // The SPI word is 18-bits long 0x12 - // The SPI word is 19-bits long 0x13 - // The SPI word is 20-bits long 0x14 - // The SPI word is 21-bits long 0x15 - // The SPI word is 22-bits long 0x16 - // The SPI word is 23-bits long 0x17 - // The SPI word is 24-bits long 0x18 - // The SPI word is 25-bits long 0x19 - // The SPI word is 26-bits long 0x1A - // The SPI word is 27-bits long 0x1B - // The SPI word is 28-bits long 0x1C - // The SPI word is 29-bits long 0x1D - // The SPI word is 30-bits long 0x1E - // The SPI word is 31-bits long 0x1F - // The SPI word is 32-bits long -#define MCSPI_CH3CONF_WL_S 7 -#define MCSPI_CH3CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held - // high during the active state. 1 - // SPIEN is held low during the - // active state. -#define MCSPI_CH3CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. - // (only when the module is a Master - // SPI device). A programmable clock - // divider divides the SPI reference - // clock (CLKSPIREF) with a 4-bit - // value and results in a new clock - // SPICLK available to shift-in and - // shift-out data. By default the - // clock divider ratio has a power - // of two granularity when - // MCSPI_CHCONF[CLKG] is cleared - // Otherwise this register is the 4 - // LSB bit of a 12-bit register - // concatenated with clock divider - // extension MCSPI_CHCTRL[EXTCLK] - // register.The value description - // below defines the clock ratio - // when MCSPI_CHCONF[CLKG] is set to - // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 - // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 - // 512 0xA 1024 0xB 2048 0xC 4096 - // 0xD 8192 0xE 16384 0xF 32768 -#define MCSPI_CH3CONF_CLKD_S 2 -#define MCSPI_CH3CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held - // high during the active state 1 - // SPICLK is held low during the - // active state -#define MCSPI_CH3CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched - // on odd numbered edges of SPICLK. - // 1 Data are latched on even - // numbered edges of SPICLK. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH3STAT register. -// -//****************************************************************************** -#define MCSPI_CH3STAT_RXFFF 0x00000040 -#define MCSPI_CH3STAT_RXFFE 0x00000020 -#define MCSPI_CH3STAT_TXFFF 0x00000010 -#define MCSPI_CH3STAT_TXFFE 0x00000008 -#define MCSPI_CH3STAT_EOT 0x00000004 -#define MCSPI_CH3STAT_TXS 0x00000002 -#define MCSPI_CH3STAT_RXS 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH3CTRL register. -// -//****************************************************************************** -#define MCSPI_CH3CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This - // register is used to concatenate - // with MCSPI_CHCONF[CLKD] register - // for clock ratio only when - // granularity is one clock cycle - // (MCSPI_CHCONF[CLKG] set to 1). - // Then the max value reached is - // 4096 clock divider ratio. 0x00 - // Clock ratio is CLKD + 1 0x01 - // Clock ratio is CLKD + 1 + 16 0xFF - // Clock ratio is CLKD + 1 + 4080 -#define MCSPI_CH3CTRL_EXTCLK_S 8 -#define MCSPI_CH3CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" - // is not active" 1 "Channel ""i"" - // is active" -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_TX3 register. -// -//****************************************************************************** -#define MCSPI_TX3_TDATA_M 0xFFFFFFFF // Channel 3 Data to transmit -#define MCSPI_TX3_TDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_RX3 register. -// -//****************************************************************************** -#define MCSPI_RX3_RDATA_M 0xFFFFFFFF // Channel 3 Received Data -#define MCSPI_RX3_RDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register. -// -//****************************************************************************** -#define MCSPI_XFERLEVEL_WCNT_M 0xFFFF0000 // Spi word counterThis register - // holds the programmable value of - // number of SPI word to be - // transferred on channel which is - // using the FIFO buffer.When - // transfer had started a read back - // in this register returns the - // current SPI word transfer index. - // 0x0000 Counter not used 0x0001 - // one word 0xFFFE 65534 spi word - // 0xFFFF 65535 spi word -#define MCSPI_XFERLEVEL_WCNT_S 16 -#define MCSPI_XFERLEVEL_AFL_M 0x0000FF00 // Buffer Almost Full This register - // holds the programmable almost - // full level value used to - // determine almost full buffer - // condition. If the user wants an - // interrupt or a DMA read request - // to be issued during a receive - // operation when the data buffer - // holds at least n bytes then the - // buffer MCSPI_MODULCTRL[AFL] must - // be set with n-1.The size of this - // register is defined by the - // generic parameter FFNBYTE. 0x00 - // one byte 0x01 2 bytes 0xFE - // 255bytes 0xFF 256bytes -#define MCSPI_XFERLEVEL_AFL_S 8 -#define MCSPI_XFERLEVEL_AEL_M 0x000000FF // Buffer Almost EmptyThis register - // holds the programmable almost - // empty level value used to - // determine almost empty buffer - // condition. If the user wants an - // interrupt or a DMA write request - // to be issued during a transmit - // operation when the data buffer is - // able to receive n bytes then the - // buffer MCSPI_MODULCTRL[AEL] must - // be set with n-1. 0x00 one byte - // 0x01 2 bytes 0xFE 255 bytes 0xFF - // 256bytes -#define MCSPI_XFERLEVEL_AEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_DAFTX register. -// -//****************************************************************************** -#define MCSPI_DAFTX_DAFTDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA - // 256 bit aligned address. "This - // Register is only is used when - // MCSPI_MODULCTRL[FDAA] is set to - // ""1"" and only one of the - // MCSPI_CH(i)CONF[FFEW] of enabled - // channels is set. If these - // conditions are not respected any - // access to this register return a - // null value." -#define MCSPI_DAFTX_DAFTDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_DAFRX register. -// -//****************************************************************************** -#define MCSPI_DAFRX_DAFRDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA - // 256 bit aligned address. "This - // Register is only is used when - // MCSPI_MODULCTRL[FDAA] is set to - // ""1"" and only one of the - // MCSPI_CH(i)CONF[FFEW] of enabled - // channels is set. If these - // conditions are not respected any - // access to this register return a - // null value." -#define MCSPI_DAFRX_DAFRDATA_S 0 - - - -#endif // __HW_MCSPI_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_memmap.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_memmap.h deleted file mode 100755 index 0919ee8c1d2..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_memmap.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following are defines for the base address of the memories and -// peripherals on the slave_1 interface. -// -//***************************************************************************** -#define FLASH_BASE 0x01000000 -#define SRAM_BASE 0x20000000 -#define WDT_BASE 0x40000000 -#define GPIOA0_BASE 0x40004000 -#define GPIOA1_BASE 0x40005000 -#define GPIOA2_BASE 0x40006000 -#define GPIOA3_BASE 0x40007000 -#define GPIOA4_BASE 0x40024000 -#define UARTA0_BASE 0x4000C000 -#define UARTA1_BASE 0x4000D000 -#define I2CA0_BASE 0x40020000 -#define TIMERA0_BASE 0x40030000 -#define TIMERA1_BASE 0x40031000 -#define TIMERA2_BASE 0x40032000 -#define TIMERA3_BASE 0x40033000 -#define STACKDIE_CTRL_BASE 0x400F5000 -#define COMMON_REG_BASE 0x400F7000 -#define FLASH_CONTROL_BASE 0x400FD000 -#define SYSTEM_CONTROL_BASE 0x400FE000 -#define UDMA_BASE 0x400FF000 -#define SDHOST_BASE 0x44010000 -#define CAMERA_BASE 0x44018000 -#define I2S_BASE 0x4401C000 -#define SSPI_BASE 0x44020000 -#define GSPI_BASE 0x44021000 -#define LSPI_BASE 0x44022000 -#define ARCM_BASE 0x44025000 -#define APPS_CONFIG_BASE 0x44026000 -#define GPRCM_BASE 0x4402D000 -#define OCP_SHARED_BASE 0x4402E000 -#define ADC_BASE 0x4402E800 -#define HIB1P2_BASE 0x4402F000 -#define HIB3P3_BASE 0x4402F800 -#define DTHE_BASE 0x44030000 -#define SHAMD5_BASE 0x44035000 -#define AES_BASE 0x44037000 -#define DES_BASE 0x44039000 - - -#endif // __HW_MEMMAP_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mmchs.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mmchs.h deleted file mode 100755 index 88b8e755853..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mmchs.h +++ /dev/null @@ -1,1917 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_MMCHS_H__ -#define __HW_MMCHS_H__ - -//***************************************************************************** -// -// The following are defines for the MMCHS register offsets. -// -//***************************************************************************** -#define MMCHS_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) - // Used by software to track - // features bugs and compatibility -#define MMCHS_O_HL_HWINFO 0x00000004 // Information about the IP - // module's hardware configuration - // i.e. typically the module's HDL - // generics (if any). Actual field - // format and encoding is up to the - // module's designer to decide. -#define MMCHS_O_HL_SYSCONFIG 0x00000010 // Clock management configuration -#define MMCHS_O_SYSCONFIG 0x00000110 // System Configuration Register - // This register allows controlling - // various parameters of the OCP - // interface. -#define MMCHS_O_SYSSTATUS 0x00000114 // System Status Register This - // register provides status - // information about the module - // excluding the interrupt status - // information -#define MMCHS_O_CSRE 0x00000124 // Card status response error This - // register enables the host - // controller to detect card status - // errors of response type R1 R1b - // for all cards and of R5 R5b and - // R6 response for cards types SD or - // SDIO. When a bit MMCHS_CSRE[i] is - // set to 1 if the corresponding bit - // at the same position in the - // response MMCHS_RSP0[i] is set to - // 1 the host controller indicates a - // card error (MMCHS_STAT[CERR]) - // interrupt status to avoid the - // host driver reading the response - // register (MMCHS_RSP0). Note: No - // automatic card error detection - // for autoCMD12 is implemented; the - // host system has to check - // autoCMD12 response register - // (MMCHS_RESP76) for possible card - // errors. -#define MMCHS_O_SYSTEST 0x00000128 // System Test register This - // register is used to control the - // signals that connect to I/O pins - // when the module is configured in - // system test (SYSTEST) mode for - // boundary connectivity - // verification. Note: In SYSTEST - // mode a write into MMCHS_CMD - // register will not start a - // transfer. The buffer behaves as a - // stack accessible only by the - // local host (push and pop - // operations). In this mode the - // Transfer Block Size - // (MMCHS_BLK[BLEN]) and the Blocks - // count for current transfer - // (MMCHS_BLK[NBLK]) are needed to - // generate a Buffer write ready - // interrupt (MMCHS_STAT[BWR]) or a - // Buffer read ready interrupt - // (MMCHS_STAT[BRR]) and DMA - // requests if enabled. -#define MMCHS_O_CON 0x0000012C // Configuration register This - // register is used: - to select the - // functional mode or the SYSTEST - // mode for any card. - to send an - // initialization sequence to any - // card. - to enable the detection - // on DAT[1] of a card interrupt for - // SDIO cards only. and also to - // configure : - specific data and - // command transfers for MMC cards - // only. - the parameters related to - // the card detect and write protect - // input signals. -#define MMCHS_O_PWCNT 0x00000130 // Power counter register This - // register is used to program a mmc - // counter to delay command - // transfers after activating the - // PAD power this value depends on - // PAD characteristics and voltage. -#define MMCHS_O_BLK 0x00000204 // Transfer Length Configuration - // register MMCHS_BLK[BLEN] is the - // block size register. - // MMCHS_BLK[NBLK] is the block - // count register. This register - // shall be used for any card. -#define MMCHS_O_ARG 0x00000208 // Command argument Register This - // register contains command - // argument specified as bit 39-8 of - // Command-Format These registers - // must be initialized prior to - // sending the command itself to the - // card (write action into the - // register MMCHS_CMD register). - // Only exception is for a command - // index specifying stuff bits in - // arguments making a write - // unnecessary. -#define MMCHS_O_CMD 0x0000020C // Command and transfer mode - // register MMCHS_CMD[31:16] = the - // command register MMCHS_CMD[15:0] - // = the transfer mode. This - // register configures the data and - // command transfers. A write into - // the most significant byte send - // the command. A write into - // MMCHS_CMD[15:0] registers during - // data transfer has no effect. This - // register shall be used for any - // card. Note: In SYSTEST mode a - // write into MMCHS_CMD register - // will not start a transfer. -#define MMCHS_O_RSP10 0x00000210 // Command response[31:0] Register - // This 32-bit register holds bits - // positions [31:0] of command - // response type - // R1/R1b/R2/R3/R4/R5/R5b/R6 -#define MMCHS_O_RSP32 0x00000214 // Command response[63:32] Register - // This 32-bit register holds bits - // positions [63:32] of command - // response type R2 -#define MMCHS_O_RSP54 0x00000218 // Command response[95:64] Register - // This 32-bit register holds bits - // positions [95:64] of command - // response type R2 -#define MMCHS_O_RSP76 0x0000021C // Command response[127:96] - // Register This 32-bit register - // holds bits positions [127:96] of - // command response type R2 -#define MMCHS_O_DATA 0x00000220 // Data Register This register is - // the 32-bit entry point of the - // buffer for read or write data - // transfers. The buffer size is - // 32bits x256(1024 bytes). Bytes - // within a word are stored and read - // in little endian format. This - // buffer can be used as two 512 - // byte buffers to transfer data - // efficiently without reducing the - // throughput. Sequential and - // contiguous access is necessary to - // increment the pointer correctly. - // Random or skipped access is not - // allowed. In little endian if the - // local host accesses this register - // byte-wise or 16bit-wise the least - // significant byte (bits [7:0]) - // must always be written/read - // first. The update of the buffer - // address is done on the most - // significant byte write for full - // 32-bit DATA register or on the - // most significant byte of the last - // word of block transfer. Example - // 1: Byte or 16-bit access - // Mbyteen[3:0]=0001 (1-byte) => - // Mbyteen[3:0]=0010 (1-byte) => - // Mbyteen[3:0]=1100 (2-bytes) OK - // Mbyteen[3:0]=0001 (1-byte) => - // Mbyteen[3:0]=0010 (1-byte) => - // Mbyteen[3:0]=0100 (1-byte) OK - // Mbyteen[3:0]=0001 (1-byte) => - // Mbyteen[3:0]=0010 (1-byte) => - // Mbyteen[3:0]=1000 (1-byte) Bad -#define MMCHS_O_PSTATE 0x00000224 // Present state register The Host - // can get status of the Host - // Controller from this 32-bit read - // only register. -#define MMCHS_O_HCTL 0x00000228 // Control register This register - // defines the host controls to set - // power wakeup and transfer - // parameters. MMCHS_HCTL[31:24] = - // Wakeup control MMCHS_HCTL[23:16] - // = Block gap control - // MMCHS_HCTL[15:8] = Power control - // MMCHS_HCTL[7:0] = Host control -#define MMCHS_O_SYSCTL 0x0000022C // SD system control register This - // register defines the system - // controls to set software resets - // clock frequency management and - // data timeout. MMCHS_SYSCTL[31:24] - // = Software resets - // MMCHS_SYSCTL[23:16] = Timeout - // control MMCHS_SYSCTL[15:0] = - // Clock control -#define MMCHS_O_STAT 0x00000230 // Interrupt status register The - // interrupt status regroups all the - // status of the module internal - // events that can generate an - // interrupt. MMCHS_STAT[31:16] = - // Error Interrupt Status - // MMCHS_STAT[15:0] = Normal - // Interrupt Status -#define MMCHS_O_IE 0x00000234 // Interrupt SD enable register - // This register allows to - // enable/disable the module to set - // status bits on an event-by-event - // basis. MMCHS_IE[31:16] = Error - // Interrupt Status Enable - // MMCHS_IE[15:0] = Normal Interrupt - // Status Enable -#define MMCHS_O_ISE 0x00000238 // Interrupt signal enable register - // This register allows to - // enable/disable the module - // internal sources of status on an - // event-by-event basis. - // MMCHS_ISE[31:16] = Error - // Interrupt Signal Enable - // MMCHS_ISE[15:0] = Normal - // Interrupt Signal Enable -#define MMCHS_O_AC12 0x0000023C // Auto CMD12 Error Status Register - // The host driver may determine - // which of the errors cases related - // to Auto CMD12 has occurred by - // checking this MMCHS_AC12 register - // when an Auto CMD12 Error - // interrupt occurs. This register - // is valid only when Auto CMD12 is - // enabled (MMCHS_CMD[ACEN]) and - // Auto CMD12Error (MMCHS_STAT[ACE]) - // is set to 1. Note: These bits are - // automatically reset when starting - // a new adtc command with data. -#define MMCHS_O_CAPA 0x00000240 // Capabilities register This - // register lists the capabilities - // of the MMC/SD/SDIO host - // controller. -#define MMCHS_O_CUR_CAPA 0x00000248 // Maximum current capabilities - // Register This register indicates - // the maximum current capability - // for each voltage. The value is - // meaningful if the voltage support - // is set in the capabilities - // register (MMCHS_CAPA). - // Initialization of this register - // (via a write access to this - // register) depends on the system - // capabilities. The host driver - // shall not modify this register - // after the initilaization. This - // register is only reinitialized by - // a hard reset (via RESETN signal) -#define MMCHS_O_FE 0x00000250 // Force Event Register for Error - // Interrupt status The force Event - // Register is not a physically - // implemented register. Rather it - // is an address at which the Error - // Interrupt Status register can be - // written. The effect of a write to - // this address will be reflected in - // the Error Interrupt Status - // Register if corresponding bit of - // the Error Interrupt Status Enable - // Register is set. -#define MMCHS_O_ADMAES 0x00000254 // ADMA Error Status Register When - // ADMA Error Interrupt is occurred - // the ADMA Error States field in - // this register holds the ADMA - // state and the ADMA System Address - // Register holds the address around - // the error descriptor. For - // recovering the error the Host - // Driver requires the ADMA state to - // identify the error descriptor - // address as follows: ST_STOP: - // Previous location set in the ADMA - // System Address register is the - // error descriptor address ST_FDS: - // Current location set in the ADMA - // System Address register is the - // error descriptor address ST_CADR: - // This sate is never set because do - // not generate ADMA error in this - // state. ST_TFR: Previous location - // set in the ADMA System Address - // register is the error descriptor - // address In case of write - // operation the Host Driver should - // use ACMD22 to get the number of - // written block rather than using - // this information since unwritten - // data may exist in the Host - // Controller. The Host Controller - // generates the ADMA Error - // Interrupt when it detects invalid - // descriptor data (Valid=0) at the - // ST_FDS state. In this case ADMA - // Error State indicates that an - // error occurs at ST_FDS state. The - // Host Driver may find that the - // Valid bit is not set in the error - // descriptor. -#define MMCHS_O_ADMASAL 0x00000258 // ADMA System address Low bits -#define MMCHS_O_REV 0x000002FC // Versions Register This register - // contains the hard coded RTL - // vendor revision number the - // version number of SD - // specification compliancy and a - // slot status bit. MMCHS_REV[31:16] - // = Host controller version - // MMCHS_REV[15:0] = Slot Interrupt - // Status - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_HL_REV register. -// -//****************************************************************************** -#define MMCHS_HL_REV_SCHEME_M 0xC0000000 -#define MMCHS_HL_REV_SCHEME_S 30 -#define MMCHS_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define MMCHS_HL_REV_FUNC_S 16 -#define MMCHS_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP - // design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define MMCHS_HL_REV_R_RTL_S 11 -#define MMCHS_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by - // IP specification owner. X changes - // ONLY when: (1) There is a major - // feature addition. An example - // would be adding Master Mode to - // Utopia Level2. The Func field (or - // Class/Type in old PID format) - // will remain the same. X does NOT - // change due to: (1) Bug fixes (2) - // Change in feature parameters. -#define MMCHS_HL_REV_X_MAJOR_S 8 -#define MMCHS_HL_REV_CUSTOM_M 0x000000C0 -#define MMCHS_HL_REV_CUSTOM_S 6 -#define MMCHS_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by - // IP specification owner. Y changes - // ONLY when: (1) Features are - // scaled (up or down). Flexibility - // exists in that this feature - // scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R S X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless the spec tracks the - // IP bugs. An RTL release (say for - // silicon PG1.1) that occurs due to - // bug fix should document the - // corresponding spec number (X.Y.S) - // in its release notes. -#define MMCHS_HL_REV_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register. -// -//****************************************************************************** -#define MMCHS_HL_HWINFO_RETMODE 0x00000040 -#define MMCHS_HL_HWINFO_MEM_SIZE_M \ - 0x0000003C - -#define MMCHS_HL_HWINFO_MEM_SIZE_S 2 -#define MMCHS_HL_HWINFO_MERGE_MEM \ - 0x00000002 - -#define MMCHS_HL_HWINFO_MADMA_EN \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// MMCHS_O_HL_SYSCONFIG register. -// -//****************************************************************************** -#define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \ - 0x00000030 // Configuration of the local - // initiator state management mode. - // By definition initiator may - // generate read/write transaction - // as long as it is out of STANDBY - // state. 0x0 Force-standby mode: - // local initiator is - // unconditionally placed in standby - // state.Backup mode for debug only. - // 0x1 No-standby mode: local - // initiator is unconditionally - // placed out of standby - // state.Backup mode for debug only. - // 0x2 Smart-standby mode: local - // initiator standby status depends - // on local conditions i.e. the - // module's functional requirement - // from the initiator.IP module - // shall not generate - // (initiator-related) wakeup - // events. 0x3 "Smart-Standby - // wakeup-capable mode: local - // initiator standby status depends - // on local conditions i.e. the - // module's functional requirement - // from the initiator. IP module may - // generate (master-related) wakeup - // events when in standby state.Mode - // is only relevant if the - // appropriate IP module ""mwakeup"" - // output is implemented." - -#define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4 -#define MMCHS_HL_SYSCONFIG_IDLEMODE_M \ - 0x0000000C // Configuration of the local - // target state management mode. By - // definition target can handle - // read/write transaction as long as - // it is out of IDLE state. 0x0 - // Force-idle mode: local target's - // idle state follows (acknowledges) - // the system's idle requests - // unconditionally i.e. regardless - // of the IP module's internal - // requirements.Backup mode for - // debug only. 0x1 No-idle mode: - // local target never enters idle - // state.Backup mode for debug only. - // 0x2 Smart-idle mode: local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module shall not - // generate (IRQ- or - // DMA-request-related) wakeup - // events. 0x3 "Smart-idle - // wakeup-capable mode: local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module may - // generate (IRQ- or - // DMA-request-related) wakeup - // events when in idle state.Mode is - // only relevant if the appropriate - // IP module ""swakeup"" output(s) - // is (are) implemented." - -#define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2 -#define MMCHS_HL_SYSCONFIG_FREEEMU \ - 0x00000002 // Sensitivity to emulation (debug) - // suspend input signal. - // Functionality NOT implemented in - // MMCHS. 0 IP module is sensitive - // to emulation suspend 1 IP module - // is not sensitive to emulation - // suspend - -#define MMCHS_HL_SYSCONFIG_SOFTRESET \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register. -// -//****************************************************************************** -#define MMCHS_SYSCONFIG_STANDBYMODE_M \ - 0x00003000 // Master interface power - // Management standby/wait control. - // The bit field is only useful when - // generic parameter MADMA_EN - // (Master ADMA enable) is set as - // active otherwise it is a read - // only register read a '0'. 0x0 - // Force-standby. Mstandby is forced - // unconditionnaly. 0x1 No-standby. - // Mstandby is never asserted. 0x2 - // Smart-standby mode: local - // initiator standby status depends - // on local conditions i.e. the - // module's functional requirement - // from the initiator.IP module - // shall not generate - // (initiator-related) wakeup - // events. 0x3 Smart-Standby - // wakeup-capable mode: "local - // initiator standby status depends - // on local conditions i.e. the - // module's functional requirement - // from the initiator. IP module may - // generate (master-related) wakeup - // events when in standby state.Mode - // is only relevant if the - // appropriate IP module ""mwakeup"" - // output is implemented." - -#define MMCHS_SYSCONFIG_STANDBYMODE_S 12 -#define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \ - 0x00000300 // Clocks activity during wake up - // mode period. Bit8: OCP interface - // clock Bit9: Functional clock 0x0 - // OCP and Functional clock may be - // switched off. 0x1 OCP clock is - // maintained. Functional clock may - // be switched-off. 0x2 Functional - // clock is maintained. OCP clock - // may be switched-off. 0x3 OCP and - // Functional clocks are maintained. - -#define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8 -#define MMCHS_SYSCONFIG_SIDLEMODE_M \ - 0x00000018 // Power management 0x0 If an idle - // request is detected the MMCHS - // acknowledges it unconditionally - // and goes in Inactive mode. - // Interrupt and DMA requests are - // unconditionally de-asserted. 0x1 - // If an idle request is detected - // the request is ignored and the - // module keeps on behaving - // normally. 0x2 Smart-idle mode: - // local target's idle state - // eventually follows (acknowledges) - // the system's idle requests - // depending on the IP module's - // internal requirements.IP module - // shall not generate (IRQ- or - // DMA-request-related) wakeup - // events. 0x3 Smart-idle - // wakeup-capable mode: "local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module may - // generate (IRQ- or - // DMA-request-related) wakeup - // events when in idle state.Mode is - // only relevant if the appropriate - // IP module ""swakeup"" output(s) - // is (are) implemented." - -#define MMCHS_SYSCONFIG_SIDLEMODE_S 3 -#define MMCHS_SYSCONFIG_ENAWAKEUP \ - 0x00000004 // Wakeup feature control 0 Wakeup - // capability is disabled 1 Wakeup - // capability is enabled - -#define MMCHS_SYSCONFIG_SOFTRESET \ - 0x00000002 - -#define MMCHS_SYSCONFIG_AUTOIDLE \ - 0x00000001 // Internal Clock gating strategy 0 - // Clocks are free-running 1 - // Automatic clock gating strategy - // is applied based on the OCP and - // MMC interface activity - -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register. -// -//****************************************************************************** -#define MMCHS_SYSSTATUS_RESETDONE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CSRE register. -// -//****************************************************************************** -#define MMCHS_CSRE_CSRE_M 0xFFFFFFFF // Card status response error -#define MMCHS_CSRE_CSRE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_SYSTEST register. -// -//****************************************************************************** -#define MMCHS_SYSTEST_OBI 0x00010000 -#define MMCHS_SYSTEST_SDCD 0x00008000 -#define MMCHS_SYSTEST_SDWP 0x00004000 -#define MMCHS_SYSTEST_WAKD 0x00002000 -#define MMCHS_SYSTEST_SSB 0x00001000 -#define MMCHS_SYSTEST_D7D 0x00000800 -#define MMCHS_SYSTEST_D6D 0x00000400 -#define MMCHS_SYSTEST_D5D 0x00000200 -#define MMCHS_SYSTEST_D4D 0x00000100 -#define MMCHS_SYSTEST_D3D 0x00000080 -#define MMCHS_SYSTEST_D2D 0x00000040 -#define MMCHS_SYSTEST_D1D 0x00000020 -#define MMCHS_SYSTEST_D0D 0x00000010 -#define MMCHS_SYSTEST_DDIR 0x00000008 -#define MMCHS_SYSTEST_CDAT 0x00000004 -#define MMCHS_SYSTEST_CDIR 0x00000002 -#define MMCHS_SYSTEST_MCKD 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CON register. -// -//****************************************************************************** -#define MMCHS_CON_SDMA_LNE 0x00200000 // Slave DMA Level/Edge Request: - // The waveform of the DMA request - // can be configured either edge - // sensitive with early de-assertion - // on first access to MMCHS_DATA - // register or late de-assertion - // request remains active until last - // allowed data written into - // MMCHS_DATA. 0 Slave DMA edge - // sensitive Early DMA de-assertion - // 1 Slave DMA level sensitive Late - // DMA de-assertion -#define MMCHS_CON_DMA_MNS 0x00100000 // DMA Master or Slave selection: - // When this bit is set and the - // controller is configured to use - // the DMA Ocp master interface is - // used to get datas from system - // using ADMA2 procedure (direct - // access to the memory).This option - // is only available if generic - // parameter MADMA_EN is asserted to - // '1'. 0 The controller is slave on - // data transfers with system. 1 The - // controller is master on data - // exchange with system controller - // must be configured as using DMA. -#define MMCHS_CON_DDR 0x00080000 // Dual Data Rate mode: When this - // register is set the controller - // uses both clock edge to emit or - // receive data. Odd bytes are - // transmitted on falling edges and - // even bytes are transmitted on - // rise edges. It only applies on - // Data bytes and CRC Start end bits - // and CRC status are kept full - // cycle. This bit field is only - // meaningful and active for even - // clock divider ratio of - // MMCHS_SYSCTL[CLKD] it is - // insensitive to MMCHS_HCTL[HSPE] - // setting. 0 Standard mode : data - // are transmitted on a single edge - // depending on MMCHS_HCTRL[HSPE]. 1 - // Data Bytes and CRC are - // transmitted on both edge. -#define MMCHS_CON_BOOT_CF0 0x00040000 -#define MMCHS_CON_BOOT_ACK 0x00020000 // Book acknowledge received: When - // this bit is set the controller - // should receive a boot status on - // DAT0 line after next command - // issued. If no status is received - // a data timeout will be generated. - // 0 No acknowledge to be received 1 - // A boot status will be received on - // DAT0 line after issuing a - // command. -#define MMCHS_CON_CLKEXTFREE 0x00010000 // External clock free running: - // This register is used to maintain - // card clock out of transfer - // transaction to enable slave - // module for example to generate a - // synchronous interrupt on DAT[1]. - // The Clock will be maintain only - // if MMCHS_SYSCTL[CEN] is set. 0 - // External card clock is cut off - // outside active transaction - // period. 1 External card clock is - // maintain even out of active - // transaction period only if - // MMCHS_SYSCTL[CEN] is set. -#define MMCHS_CON_PADEN 0x00008000 // Control Power for MMC Lines: - // This register is only useful when - // MMC PADs contain power saving - // mechanism to minimize its leakage - // power. It works as a GPIO that - // directly control the ACTIVE pin - // of PADs. Excepted for DAT[1] the - // signal is also combine outside - // the module with the dedicated - // power control MMCHS_CON[CTPL] - // bit. 0 ADPIDLE module pin is not - // forced it is automatically - // generated by the MMC fsms. 1 - // ADPIDLE module pin is forced to - // active state. -#define MMCHS_CON_OBIE 0x00004000 // Out-of-Band Interrupt Enable MMC - // cards only: This bit enables the - // detection of Out-of-Band - // Interrupt on MMCOBI input pin. - // The usage of the Out-of-Band - // signal (OBI) is optional and - // depends on the system - // integration. 0 Out-of-Band - // interrupt detection disabled 1 - // Out-of-Band interrupt detection - // enabled -#define MMCHS_CON_OBIP 0x00002000 // Out-of-Band Interrupt Polarity - // MMC cards only: This bit selects - // the active level of the - // out-of-band interrupt coming from - // MMC cards. The usage of the - // Out-of-Band signal (OBI) is - // optional and depends on the - // system integration. 0 active high - // level 1 active low level -#define MMCHS_CON_CEATA 0x00001000 // CE-ATA control mode MMC cards - // compliant with CE-ATA:By default - // this bit is set to 0. It is use - // to indicate that next commands - // are considered as specific CE-ATA - // commands that potentially use - // 'command completion' features. 0 - // Standard MMC/SD/SDIO mode. 1 - // CE-ATA mode next commands are - // considered as CE-ATA commands. -#define MMCHS_CON_CTPL 0x00000800 // Control Power for DAT[1] line - // MMC and SD cards: By default this - // bit is set to 0 and the host - // controller automatically disables - // all the input buffers outside of - // a transaction to minimize the - // leakage current. SDIO cards: When - // this bit is set to 1 the host - // controller automatically disables - // all the input buffers except the - // buffer of DAT[1] outside of a - // transaction in order to detect - // asynchronous card interrupt on - // DAT[1] line and minimize the - // leakage current of the buffers. 0 - // Disable all the input buffers - // outside of a transaction. 1 - // Disable all the input buffers - // except the buffer of DAT[1] - // outside of a transaction. -#define MMCHS_CON_DVAL_M 0x00000600 // Debounce filter value All cards - // This register is used to define a - // debounce period to filter the - // card detect input signal (SDCD). - // The usage of the card detect - // input signal (SDCD) is optional - // and depends on the system - // integration and the type of the - // connector housing that - // accommodates the card. 0x0 33 us - // debounce period 0x1 231 us - // debounce period 0x2 1 ms debounce - // period 0x3 84 ms debounce period -#define MMCHS_CON_DVAL_S 9 -#define MMCHS_CON_WPP 0x00000100 // Write protect polarity For SD - // and SDIO cards only This bit - // selects the active level of the - // write protect input signal - // (SDWP). The usage of the write - // protect input signal (SDWP) is - // optional and depends on the - // system integration and the type - // of the connector housing that - // accommodates the card. 0 active - // high level 1 active low level -#define MMCHS_CON_CDP 0x00000080 // Card detect polarity All cards - // This bit selects the active level - // of the card detect input signal - // (SDCD). The usage of the card - // detect input signal (SDCD) is - // optional and depends on the - // system integration and the type - // of the connector housing that - // accommodates the card. 0 active - // high level 1 active low level -#define MMCHS_CON_MIT 0x00000040 // MMC interrupt command Only for - // MMC cards. This bit must be set - // to 1 when the next write access - // to the command register - // (MMCHS_CMD) is for writing a MMC - // interrupt command (CMD40) - // requiring the command timeout - // detection to be disabled for the - // command response. 0 Command - // timeout enabled 1 Command timeout - // disabled -#define MMCHS_CON_DW8 0x00000020 // 8-bit mode MMC select For - // SD/SDIO cards this bit must be - // set to 0. For MMC card this bit - // must be set following a valid - // SWITCH command (CMD6) with the - // correct value and extend CSD - // index written in the argument. - // Prior to this command the MMC - // card configuration register (CSD - // and EXT_CSD) must be verified for - // compliancy with MMC standard - // specification 4.x (see section - // 3.6). 0 1-bit or 4-bit Data width - // (DAT[0] used MMC SD cards) 1 - // 8-bit Data width (DAT[7:0] used - // MMC cards) -#define MMCHS_CON_MODE 0x00000010 // Mode select All cards These bits - // select between Functional mode - // and SYSTEST mode. 0 Functional - // mode. Transfers to the - // MMC/SD/SDIO cards follow the card - // protocol. MMC clock is enabled. - // MMC/SD transfers are operated - // under the control of the CMD - // register. 1 SYSTEST mode The - // signal pins are configured as - // general-purpose input/output and - // the 1024-byte buffer is - // configured as a stack memory - // accessible only by the local host - // or system DMA. The pins retain - // their default type (input output - // or in-out). SYSTEST mode is - // operated under the control of the - // SYSTEST register. -#define MMCHS_CON_STR 0x00000008 // Stream command Only for MMC - // cards. This bit must be set to 1 - // only for the stream data - // transfers (read or write) of the - // adtc commands. Stream read is a - // class 1 command (CMD11: - // READ_DAT_UNTIL_STOP). Stream - // write is a class 3 command - // (CMD20: WRITE_DAT_UNTIL_STOP). 0 - // Block oriented data transfer 1 - // Stream oriented data transfer -#define MMCHS_CON_HR 0x00000004 // Broadcast host response Only for - // MMC cards. This register is used - // to force the host to generate a - // 48-bit response for bc command - // type. "It can be used to - // terminate the interrupt mode by - // generating a CMD40 response by - // the core (see section 4.3 - // ""Interrupt Mode"" in the MMC [1] - // specification). In order to have - // the host response to be generated - // in open drain mode the register - // MMCHS_CON[OD] must be set to 1." - // When MMCHS_CON[CEATA] is set to 1 - // and MMCHS_ARG set to 0x00000000 - // when writing 0x00000000 into - // MMCHS_CMD register the host - // controller performs a 'command - // completion signal disable' token - // i.e. CMD line held to '0' during - // 47 cycles followed by a 1. 0 The - // host does not generate a 48-bit - // response instead of a command. 1 - // The host generates a 48-bit - // response instead of a command or - // a command completion signal - // disable token. -#define MMCHS_CON_INIT 0x00000002 // Send initialization stream All - // cards. When this bit is set to 1 - // and the card is idle an - // initialization sequence is sent - // to the card. "An initialization - // sequence consists of setting the - // CMD line to 1 during 80 clock - // cycles. The initialisation - // sequence is mandatory - but it is - // not required to do it through - // this bit - this bit makes it - // easier. Clock divider - // (MMCHS_SYSCTL[CLKD]) should be - // set to ensure that 80 clock - // periods are greater than 1ms. - // (see section 9.3 ""Power-Up"" in - // the MMC card specification [1] or - // section 6.4 in the SD card - // specification [2])." Note: in - // this mode there is no command - // sent to the card and no response - // is expected 0 The host does not - // send an initialization sequence. - // 1 The host sends an - // initialization sequence. -#define MMCHS_CON_OD 0x00000001 // Card open drain mode. Only for - // MMC cards. This bit must be set - // to 1 for MMC card commands 1 2 3 - // and 40 and if the MMC card bus is - // operating in open-drain mode - // during the response phase to the - // command sent. Typically during - // card identification mode when the - // card is either in idle ready or - // ident state. It is also necessary - // to set this bit to 1 for a - // broadcast host response (see - // Broadcast host response register - // MMCHS_CON[HR]) 0 No Open Drain 1 - // Open Drain or Broadcast host - // response -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_PWCNT register. -// -//****************************************************************************** -#define MMCHS_PWCNT_PWRCNT_M 0x0000FFFF // Power counter register. This - // register is used to introduce a - // delay between the PAD ACTIVE pin - // assertion and the command issued. - // 0x0000 No additional delay added - // 0x0001 TCF delay (card clock - // period) 0x0002 TCF x 2 delay - // (card clock period) 0xFFFE TCF x - // 65534 delay (card clock period) - // 0xFFFF TCF x 65535 delay (card - // clock period) -#define MMCHS_PWCNT_PWRCNT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_BLK register. -// -//****************************************************************************** -#define MMCHS_BLK_NBLK_M 0xFFFF0000 // Blocks count for current - // transfer This register is enabled - // when Block count Enable - // (MMCHS_CMD[BCE]) is set to 1 and - // is valid only for multiple block - // transfers. Setting the block - // count to 0 results no data blocks - // being transferred. Note: The host - // controller decrements the block - // count after each block transfer - // and stops when the count reaches - // zero. This register can be - // accessed only if no transaction - // is executing (i.e after a - // transaction has stopped). Read - // operations during transfers may - // return an invalid value and write - // operation will be ignored. In - // suspend context the number of - // blocks yet to be transferred can - // be determined by reading this - // register. When restoring transfer - // context prior to issuing a Resume - // command The local host shall - // restore the previously saved - // block count. 0x0000 Stop count - // 0x0001 1 block 0x0002 2 blocks - // 0xFFFF 65535 blocks -#define MMCHS_BLK_NBLK_S 16 -#define MMCHS_BLK_BLEN_M 0x00000FFF // Transfer Block Size. This - // register specifies the block size - // for block data transfers. Read - // operations during transfers may - // return an invalid value and write - // operations are ignored. When a - // CMD12 command is issued to stop - // the transfer a read of the BLEN - // field after transfer completion - // (MMCHS_STAT[TC] set to 1) will - // not return the true byte number - // of data length while the stop - // occurs but the value written in - // this register before transfer is - // launched. 0x000 No data transfer - // 0x001 1 byte block length 0x002 2 - // bytes block length 0x003 3 bytes - // block length 0x1FF 511 bytes - // block length 0x200 512 bytes - // block length 0x7FF 2047 bytes - // block length 0x800 2048 bytes - // block length -#define MMCHS_BLK_BLEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_ARG register. -// -//****************************************************************************** -#define MMCHS_ARG_ARG_M 0xFFFFFFFF // Command argument bits [31:0] -#define MMCHS_ARG_ARG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CMD register. -// -//****************************************************************************** -#define MMCHS_CMD_INDX_M 0x3F000000 // Command index Binary encoded - // value from 0 to 63 specifying the - // command number send to card 0x00 - // CMD0 or ACMD0 0x01 CMD1 or ACMD1 - // 0x02 CMD2 or ACMD2 0x03 CMD3 or - // ACMD3 0x04 CMD4 or ACMD4 0x05 - // CMD5 or ACMD5 0x06 CMD6 or ACMD6 - // 0x07 CMD7 or ACMD7 0x08 CMD8 or - // ACMD8 0x09 CMD9 or ACMD9 0x0A - // CMD10 or ACMD10 0x0B CMD11 or - // ACMD11 0x0C CMD12 or ACMD12 0x0D - // CMD13 or ACMD13 0x0E CMD14 or - // ACMD14 0x0F CMD15 or ACMD15 0x10 - // CMD16 or ACMD16 0x11 CMD17 or - // ACMD17 0x12 CMD18 or ACMD18 0x13 - // CMD19 or ACMD19 0x14 CMD20 or - // ACMD20 0x15 CMD21 or ACMD21 0x16 - // CMD22 or ACMD22 0x17 CMD23 or - // ACMD23 0x18 CMD24 or ACMD24 0x19 - // CMD25 or ACMD25 0x1A CMD26 or - // ACMD26 0x1B CMD27 or ACMD27 0x1C - // CMD28 or ACMD28 0x1D CMD29 or - // ACMD29 0x1E CMD30 or ACMD30 0x1F - // CMD31 or ACMD31 0x20 CMD32 or - // ACMD32 0x21 CMD33 or ACMD33 0x22 - // CMD34 or ACMD34 0x23 CMD35 or - // ACMD35 0x24 CMD36 or ACMD36 0x25 - // CMD37 or ACMD37 0x26 CMD38 or - // ACMD38 0x27 CMD39 or ACMD39 0x28 - // CMD40 or ACMD40 0x29 CMD41 or - // ACMD41 0x2A CMD42 or ACMD42 0x2B - // CMD43 or ACMD43 0x2C CMD44 or - // ACMD44 0x2D CMD45 or ACMD45 0x2E - // CMD46 or ACMD46 0x2F CMD47 or - // ACMD47 0x30 CMD48 or ACMD48 0x31 - // CMD49 or ACMD49 0x32 CMD50 or - // ACMD50 0x33 CMD51 or ACMD51 0x34 - // CMD52 or ACMD52 0x35 CMD53 or - // ACMD53 0x36 CMD54 or ACMD54 0x37 - // CMD55 or ACMD55 0x38 CMD56 or - // ACMD56 0x39 CMD57 or ACMD57 0x3A - // CMD58 or ACMD58 0x3B CMD59 or - // ACMD59 0x3C CMD60 or ACMD60 0x3D - // CMD61 or ACMD61 0x3E CMD62 or - // ACMD62 0x3F CMD63 or ACMD63 -#define MMCHS_CMD_INDX_S 24 -#define MMCHS_CMD_CMD_TYPE_M 0x00C00000 // Command type This register - // specifies three types of special - // command: Suspend Resume and - // Abort. These bits shall be set to - // 00b for all other commands. 0x0 - // Others Commands 0x1 "CMD52 for - // writing ""Bus Suspend"" in CCCR" - // 0x2 "CMD52 for writing ""Function - // Select"" in CCCR" 0x3 "Abort - // command CMD12 CMD52 for writing - // "" I/O Abort"" in CCCR" -#define MMCHS_CMD_CMD_TYPE_S 22 -#define MMCHS_CMD_DP 0x00200000 // Data present select This - // register indicates that data is - // present and DAT line shall be - // used. It must be set to 0 in the - // following conditions: - command - // using only CMD line - command - // with no data transfer but using - // busy signal on DAT[0] - Resume - // command 0 Command with no data - // transfer 1 Command with data - // transfer -#define MMCHS_CMD_CICE 0x00100000 // Command Index check enable This - // bit must be set to 1 to enable - // index check on command response - // to compare the index field in the - // response against the index of the - // command. If the index is not the - // same in the response as in the - // command it is reported as a - // command index error - // (MMCHS_STAT[CIE] set to1) Note: - // The register CICE cannot be - // configured for an Auto CMD12 then - // index check is automatically - // checked when this command is - // issued. 0 Index check disable 1 - // Index check enable -#define MMCHS_CMD_CCCE 0x00080000 // Command CRC check enable This - // bit must be set to 1 to enable - // CRC7 check on command response to - // protect the response against - // transmission errors on the bus. - // If an error is detected it is - // reported as a command CRC error - // (MMCHS_STAT[CCRC] set to 1). - // Note: The register CCCE cannot be - // configured for an Auto CMD12 and - // then CRC check is automatically - // checked when this command is - // issued. 0 CRC7 check disable 1 - // CRC7 check enable -#define MMCHS_CMD_RSP_TYPE_M 0x00030000 // Response type This bits defines - // the response type of the command - // 0x0 No response 0x1 Response - // Length 136 bits 0x2 Response - // Length 48 bits 0x3 Response - // Length 48 bits with busy after - // response -#define MMCHS_CMD_RSP_TYPE_S 16 -#define MMCHS_CMD_MSBS 0x00000020 // Multi/Single block select This - // bit must be set to 1 for data - // transfer in case of multi block - // command. For any others command - // this bit shall be set to 0. 0 - // Single block. If this bit is 0 it - // is not necessary to set the - // register MMCHS_BLK[NBLK]. 1 Multi - // block. When Block Count is - // disabled (MMCHS_CMD[BCE] is set - // to 0) in Multiple block transfers - // (MMCHS_CMD[MSBS] is set to 1) the - // module can perform infinite - // transfer. -#define MMCHS_CMD_DDIR 0x00000010 // Data transfer Direction Select - // This bit defines either data - // transfer will be a read or a - // write. 0 Data Write (host to - // card) 1 Data Read (card to host) -#define MMCHS_CMD_ACEN 0x00000004 // Auto CMD12 Enable SD card only. - // When this bit is set to 1 the - // host controller issues a CMD12 - // automatically after the transfer - // completion of the last block. The - // Host Driver shall not set this - // bit to issue commands that do not - // require CMD12 to stop data - // transfer. In particular secure - // commands do not require CMD12. 0 - // Auto CMD12 disable 1 Auto CMD12 - // enable or CCS detection enabled. -#define MMCHS_CMD_BCE 0x00000002 // Block Count Enable Multiple - // block transfers only. This bit is - // used to enable the block count - // register (MMCHS_BLK[NBLK]). When - // Block Count is disabled - // (MMCHS_CMD[BCE] is set to 0) in - // Multiple block transfers - // (MMCHS_CMD[MSBS] is set to 1) the - // module can perform infinite - // transfer. 0 Block count disabled - // for infinite transfer. 1 Block - // count enabled for multiple block - // transfer with known number of - // blocks -#define MMCHS_CMD_DE 0x00000001 // DMA Enable This bit is used to - // enable DMA mode for host data - // access. 0 DMA mode disable 1 DMA - // mode enable -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_RSP10 register. -// -//****************************************************************************** -#define MMCHS_RSP10_RSP1_M 0xFFFF0000 // Command Response [31:16] -#define MMCHS_RSP10_RSP1_S 16 -#define MMCHS_RSP10_RSP0_M 0x0000FFFF // Command Response [15:0] -#define MMCHS_RSP10_RSP0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_RSP32 register. -// -//****************************************************************************** -#define MMCHS_RSP32_RSP3_M 0xFFFF0000 // Command Response [63:48] -#define MMCHS_RSP32_RSP3_S 16 -#define MMCHS_RSP32_RSP2_M 0x0000FFFF // Command Response [47:32] -#define MMCHS_RSP32_RSP2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_RSP54 register. -// -//****************************************************************************** -#define MMCHS_RSP54_RSP5_M 0xFFFF0000 // Command Response [95:80] -#define MMCHS_RSP54_RSP5_S 16 -#define MMCHS_RSP54_RSP4_M 0x0000FFFF // Command Response [79:64] -#define MMCHS_RSP54_RSP4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_RSP76 register. -// -//****************************************************************************** -#define MMCHS_RSP76_RSP7_M 0xFFFF0000 // Command Response [127:112] -#define MMCHS_RSP76_RSP7_S 16 -#define MMCHS_RSP76_RSP6_M 0x0000FFFF // Command Response [111:96] -#define MMCHS_RSP76_RSP6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_DATA register. -// -//****************************************************************************** -#define MMCHS_DATA_DATA_M 0xFFFFFFFF // Data Register [31:0] In - // functional mode (MMCHS_CON[MODE] - // set to the default value 0) A - // read access to this register is - // allowed only when the buffer read - // enable status is set to 1 - // (MMCHS_PSTATE[BRE]) otherwise a - // bad access (MMCHS_STAT[BADA]) is - // signaled. A write access to this - // register is allowed only when the - // buffer write enable status is set - // to 1(MMCHS_STATE[BWE]) otherwise - // a bad access (MMCHS_STAT[BADA]) - // is signaled and the data is not - // written. -#define MMCHS_DATA_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_PSTATE register. -// -//****************************************************************************** -#define MMCHS_PSTATE_CLEV 0x01000000 -#define MMCHS_PSTATE_DLEV_M 0x00F00000 // DAT[3:0] line signal level - // DAT[3] => bit 23 DAT[2] => bit 22 - // DAT[1] => bit 21 DAT[0] => bit 20 - // This status is used to check DAT - // line level to recover from errors - // and for debugging. This is - // especially useful in detecting - // the busy signal level from - // DAT[0]. The value of these - // registers after reset depends on - // the DAT lines level at that time. -#define MMCHS_PSTATE_DLEV_S 20 -#define MMCHS_PSTATE_WP 0x00080000 -#define MMCHS_PSTATE_CDPL 0x00040000 -#define MMCHS_PSTATE_CSS 0x00020000 -#define MMCHS_PSTATE_CINS 0x00010000 -#define MMCHS_PSTATE_BRE 0x00000800 -#define MMCHS_PSTATE_BWE 0x00000400 -#define MMCHS_PSTATE_RTA 0x00000200 -#define MMCHS_PSTATE_WTA 0x00000100 -#define MMCHS_PSTATE_DLA 0x00000004 -#define MMCHS_PSTATE_DATI 0x00000002 -#define MMCHS_PSTATE_CMDI 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_HCTL register. -// -//****************************************************************************** -#define MMCHS_HCTL_OBWE 0x08000000 // Wakeup event enable for - // 'Out-of-Band' Interrupt. This bit - // enables wakeup events for - // 'Out-of-Band' assertion. Wakeup - // is generated if the wakeup - // feature is enabled - // (MMCHS_SYSCONFIG[ENAWAKEUP]). The - // write to this register is ignored - // when MMCHS_CON[OBIE] is not set. - // 0 Disable wakeup on 'Out-of-Band' - // Interrupt 1 Enable wakeup on - // 'Out-of-Band' Interrupt -#define MMCHS_HCTL_REM 0x04000000 // Wakeup event enable on SD card - // removal This bit enables wakeup - // events for card removal - // assertion. Wakeup is generated if - // the wakeup feature is enabled - // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 - // Disable wakeup on card removal 1 - // Enable wakeup on card removal -#define MMCHS_HCTL_INS 0x02000000 // Wakeup event enable on SD card - // insertion This bit enables wakeup - // events for card insertion - // assertion. Wakeup is generated if - // the wakeup feature is enabled - // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 - // Disable wakeup on card insertion - // 1 Enable wakeup on card insertion -#define MMCHS_HCTL_IWE 0x01000000 // Wakeup event enable on SD card - // interrupt This bit enables wakeup - // events for card interrupt - // assertion. Wakeup is generated if - // the wakeup feature is enabled - // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 - // Disable wakeup on card interrupt - // 1 Enable wakeup on card interrupt -#define MMCHS_HCTL_IBG 0x00080000 // Interrupt block at gap This bit - // is valid only in 4-bit mode of - // SDIO card to enable interrupt - // detection in the interrupt cycle - // at block gap for a multiple block - // transfer. For MMC cards and for - // SD card this bit should be set to - // 0. 0 Disable interrupt detection - // at the block gap in 4-bit mode 1 - // Enable interrupt detection at the - // block gap in 4-bit mode -#define MMCHS_HCTL_RWC 0x00040000 // Read wait control The read wait - // function is optional only for - // SDIO cards. If the card supports - // read wait this bit must be - // enabled then requesting a stop at - // block gap (MMCHS_HCTL[SBGR]) - // generates a read wait period - // after the current end of block. - // Be careful if read wait is not - // supported it may cause a conflict - // on DAT line. 0 Disable Read Wait - // Control. Suspend/Resume cannot be - // supported. 1 Enable Read Wait - // Control -#define MMCHS_HCTL_CR 0x00020000 // Continue request This bit is - // used to restart a transaction - // that was stopped by requesting a - // stop at block gap - // (MMCHS_HCTL[SBGR]). Set this bit - // to 1 restarts the transfer. The - // bit is automatically set to 0 by - // the host controller when transfer - // has restarted i.e DAT line is - // active (MMCHS_PSTATE[DLA]) or - // transferring data - // (MMCHS_PSTATE[WTA]). The Stop at - // block gap request must be - // disabled (MMCHS_HCTL[SBGR]=0) - // before setting this bit. 0 No - // affect 1 transfer restart -#define MMCHS_HCTL_SBGR 0x00010000 // Stop at block gap request This - // bit is used to stop executing a - // transaction at the next block - // gap. The transfer can restart - // with a continue request - // (MMHS_HCTL[CR]) or during a - // suspend/resume sequence. In case - // of read transfer the card must - // support read wait control. In - // case of write transfer the host - // driver shall set this bit after - // all block data written. Until the - // transfer completion - // (MMCHS_STAT[TC] set to 1) the - // host driver shall leave this bit - // set to 1. If this bit is set the - // local host shall not write to the - // data register (MMCHS_DATA). 0 - // Transfer mode 1 Stop at block gap -#define MMCHS_HCTL_SDVS_M 0x00000E00 // SD bus voltage select All cards. - // The host driver should set to - // these bits to select the voltage - // level for the card according to - // the voltage supported by the - // system (MMCHS_CAPA[VS18VS30VS33]) - // before starting a transfer. 0x5 - // 1.8V (Typical) 0x6 3.0V (Typical) - // 0x7 3.3V (Typical) -#define MMCHS_HCTL_SDVS_S 9 -#define MMCHS_HCTL_SDBP 0x00000100 // SD bus power Before setting this - // bit the host driver shall select - // the SD bus voltage - // (MMCHS_HCTL[SDVS]). If the host - // controller detects the No card - // state this bit is automatically - // set to 0. If the module is power - // off a write in the command - // register (MMCHS_CMD) will not - // start the transfer. A write to - // this bit has no effect if the - // selected SD bus voltage - // MMCHS_HCTL[SDVS] is not supported - // according to capability register - // (MMCHS_CAPA[VS*]). 0 Power off 1 - // Power on -#define MMCHS_HCTL_CDSS 0x00000080 // Card Detect Signal Selection - // This bit selects source for the - // card detection.When the source - // for the card detection is - // switched the interrupt should be - // disabled during the switching - // period by clearing the Interrupt - // Status/Signal Enable register in - // order to mask unexpected - // interrupt being caused by the - // glitch. The Interrupt - // Status/Signal Enable should be - // disabled during over the period - // of debouncing. 0 SDCD# is - // selected (for normal use) 1 The - // Card Detect Test Level is - // selected (for test purpose) -#define MMCHS_HCTL_CDTL 0x00000040 // Card Detect Test Level: This bit - // is enabled while the Card Detect - // Signal Selection is set to 1 and - // it indicates card inserted or - // not. 0 No Card 1 Card Inserted -#define MMCHS_HCTL_DMAS_M 0x00000018 // DMA Select Mode: One of - // supported DMA modes can be - // selected. The host driver shall - // check support of DMA modes by - // referring the Capabilities - // register. Use of selected DMA is - // determined by DMA Enable of the - // Transfer Mode register. This - // register is only meaningful when - // MADMA_EN is set to 1. When - // MADMA_EN is set to 0 the bit - // field is read only and returned - // value is 0. 0x0 Reserved 0x1 - // Reserved 0x2 32-bit Address ADMA2 - // is selected 0x3 Reserved -#define MMCHS_HCTL_DMAS_S 3 -#define MMCHS_HCTL_HSPE 0x00000004 // High Speed Enable: Before - // setting this bit the Host Driver - // shall check the High Speed - // Support in the Capabilities - // register. If this bit is set to 0 - // (default) the Host Controller - // outputs CMD line and DAT lines at - // the falling edge of the SD Clock. - // If this bit is set to 1 the Host - // Controller outputs CMD line and - // DAT lines at the rising edge of - // the SD Clock.This bit shall not - // be set when dual data rate mode - // is activated in MMCHS_CON[DDR]. 0 - // Normal speed mode 1 High speed - // mode -#define MMCHS_HCTL_DTW 0x00000002 // Data transfer width For MMC card - // this bit must be set following a - // valid SWITCH command (CMD6) with - // the correct value and extend CSD - // index written in the argument. - // Prior to this command the MMC - // card configuration register (CSD - // and EXT_CSD) must be verified for - // compliance with MMC standard - // specification 4.x (see section - // 3.6). This register has no effect - // when the MMC 8-bit mode is - // selected (register MMCHS_CON[DW8] - // set to1 ) For SD/SDIO cards this - // bit must be set following a valid - // SET_BUS_WIDTH command (ACMD6) - // with the value written in bit 1 - // of the argument. Prior to this - // command the SD card configuration - // register (SCR) must be verified - // for the supported bus width by - // the SD card. 0 1-bit Data width - // (DAT[0] used) 1 4-bit Data width - // (DAT[3:0] used) -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_SYSCTL register. -// -//****************************************************************************** -#define MMCHS_SYSCTL_SRD 0x04000000 // Software reset for DAT line This - // bit is set to 1 for reset and - // released to 0 when completed. DAT - // finite state machine in both - // clock domain are also reset. Here - // below are the registers cleared - // by MMCHS_SYSCTL[SRD]: #VALUE! - - // MMCHS_PSTATE: BRE BWE RTA WTA DLA - // and DATI - MMCHS_HCTL: SBGR and - // CR - MMCHS_STAT: BRR BWR BGE and - // TC OCP and MMC buffer data - // management is reinitialized. 0 - // Reset completed 1 Software reset - // for DAT line -#define MMCHS_SYSCTL_SRC 0x02000000 // Software reset for CMD line This - // bit is set to 1 for reset and - // released to 0 when completed. CMD - // finite state machine in both - // clock domain are also reset. Here - // below the registers cleared by - // MMCHS_SYSCTL[SRC]: - - // MMCHS_PSTATE: CMDI - MMCHS_STAT: - // CC OCP and MMC command status - // management is reinitialized. 0 - // Reset completed 1 Software reset - // for CMD line -#define MMCHS_SYSCTL_SRA 0x01000000 // Software reset for all This bit - // is set to 1 for reset and - // released to 0 when completed. - // This reset affects the entire - // host controller except for the - // card detection circuit and - // capabilities registers. 0 Reset - // completed 1 Software reset for - // all the design -#define MMCHS_SYSCTL_DTO_M 0x000F0000 // Data timeout counter value and - // busy timeout. This value - // determines the interval by which - // DAT lines timeouts are detected. - // The host driver needs to set this - // bitfield based on - the maximum - // read access time (NAC) (Refer to - // the SD Specification Part1 - // Physical Layer) - the data read - // access time values (TAAC and - // NSAC) in the card specific data - // register (CSD) of the card - the - // timeout clock base frequency - // (MMCHS_CAPA[TCF]). If the card - // does not respond within the - // specified number of cycles a data - // timeout error occurs - // (MMCHS_STA[DTO]). The - // MMCHS_SYSCTL[DTO] register is - // also used to check busy duration - // to generate busy timeout for - // commands with busy response or - // for busy programming during a - // write command. Timeout on CRC - // status is generated if no CRC - // token is present after a block - // write. 0x0 TCF x 2^13 0x1 TCF x - // 2^14 0xE TCF x 2^27 0xF Reserved -#define MMCHS_SYSCTL_DTO_S 16 -#define MMCHS_SYSCTL_CLKD_M 0x0000FFC0 // Clock frequency select These - // bits define the ratio between a - // reference clock frequency (system - // dependant) and the output clock - // frequency on the CLK pin of - // either the memory card (MMC SD or - // SDIO). 0x000 Clock Ref bypass - // 0x001 Clock Ref bypass 0x002 - // Clock Ref / 2 0x003 Clock Ref / 3 - // 0x3FF Clock Ref / 1023 -#define MMCHS_SYSCTL_CLKD_S 6 -#define MMCHS_SYSCTL_CEN 0x00000004 // Clock enable This bit controls - // if the clock is provided to the - // card or not. 0 The clock is not - // provided to the card . Clock - // frequency can be changed . 1 The - // clock is provided to the card and - // can be automatically gated when - // MMCHS_SYSCONFIG[AUTOIDLE] is set - // to 1 (default value) . The host - // driver shall wait to set this bit - // to 1 until the Internal clock is - // stable (MMCHS_SYSCTL[ICS]). -#define MMCHS_SYSCTL_ICS 0x00000002 -#define MMCHS_SYSCTL_ICE 0x00000001 // Internal clock enable This - // register controls the internal - // clock activity. In very low power - // state the internal clock is - // stopped. Note: The activity of - // the debounce clock (used for - // wakeup events) and the OCP clock - // (used for reads and writes to the - // module register map) are not - // affected by this register. 0 The - // internal clock is stopped (very - // low power state). 1 The internal - // clock oscillates and can be - // automatically gated when - // MMCHS_SYSCONFIG[AUTOIDLE] is set - // to 1 (default value) . -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_STAT register. -// -//****************************************************************************** -#define MMCHS_STAT_BADA 0x20000000 -#define MMCHS_STAT_CERR 0x10000000 -#define MMCHS_STAT_ADMAE 0x02000000 -#define MMCHS_STAT_ACE 0x01000000 -#define MMCHS_STAT_DEB 0x00400000 -#define MMCHS_STAT_DCRC 0x00200000 -#define MMCHS_STAT_DTO 0x00100000 -#define MMCHS_STAT_CIE 0x00080000 -#define MMCHS_STAT_CEB 0x00040000 -#define MMCHS_STAT_CCRC 0x00020000 -#define MMCHS_STAT_CTO 0x00010000 -#define MMCHS_STAT_ERRI 0x00008000 -#define MMCHS_STAT_BSR 0x00000400 -#define MMCHS_STAT_OBI 0x00000200 -#define MMCHS_STAT_CIRQ 0x00000100 -#define MMCHS_STAT_CREM 0x00000080 -#define MMCHS_STAT_CINS 0x00000040 -#define MMCHS_STAT_BRR 0x00000020 -#define MMCHS_STAT_BWR 0x00000010 -#define MMCHS_STAT_DMA 0x00000008 -#define MMCHS_STAT_BGE 0x00000004 -#define MMCHS_STAT_TC 0x00000002 -#define MMCHS_STAT_CC 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_IE register. -// -//****************************************************************************** -#define MMCHS_IE_BADA_ENABLE 0x20000000 // Bad access to data space - // Interrupt Enable 0 Masked 1 - // Enabled -#define MMCHS_IE_CERR_ENABLE 0x10000000 // Card error interrupt Enable 0 - // Masked 1 Enabled -#define MMCHS_IE_ADMAE_ENABLE 0x02000000 // ADMA error Interrupt Enable 0 - // Masked 1 Enabled -#define MMCHS_IE_ACE_ENABLE 0x01000000 // Auto CMD12 error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_DEB_ENABLE 0x00400000 // Data end bit error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_DCRC_ENABLE 0x00200000 // Data CRC error Interrupt Enable - // 0 Masked 1 Enabled -#define MMCHS_IE_DTO_ENABLE 0x00100000 // Data timeout error Interrupt - // Enable 0 The data timeout - // detection is deactivated. The - // host controller provides the - // clock to the card until the card - // sends the data or the transfer is - // aborted. 1 The data timeout - // detection is enabled. -#define MMCHS_IE_CIE_ENABLE 0x00080000 // Command index error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_CEB_ENABLE 0x00040000 // Command end bit error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_CCRC_ENABLE 0x00020000 // Command CRC error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_CTO_ENABLE 0x00010000 // Command timeout error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_NULL 0x00008000 // Fixed to 0 The host driver shall - // control error interrupts using - // the Error Interrupt Signal Enable - // register. Writes to this bit are - // ignored -#define MMCHS_IE_BSR_ENABLE 0x00000400 // Boot status interrupt Enable A - // write to this register when - // MMCHS_CON[BOOT_ACK] is set to 0x0 - // is ignored. 0 Masked 1 Enabled -#define MMCHS_IE_OBI_ENABLE 0x00000200 // Out-of-Band interrupt Enable A - // write to this register when - // MMCHS_CON[OBIE] is set to '0' is - // ignored. 0 Masked 1 Enabled -#define MMCHS_IE_CIRQ_ENABLE 0x00000100 // Card interrupt Enable A clear of - // this bit also clears the - // corresponding status bit. During - // 1-bit mode if the interrupt - // routine doesn't remove the source - // of a card interrupt in the SDIO - // card the status bit is reasserted - // when this bit is set to 1. 0 - // Masked 1 Enabled -#define MMCHS_IE_CREM_ENABLE 0x00000080 // Card removal Interrupt Enable 0 - // Masked 1 Enabled -#define MMCHS_IE_CINS_ENABLE 0x00000040 // Card insertion Interrupt Enable - // 0 Masked 1 Enabled -#define MMCHS_IE_BRR_ENABLE 0x00000020 // Buffer Read Ready Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_BWR_ENABLE 0x00000010 // Buffer Write Ready Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_DMA_ENABLE 0x00000008 // DMA interrupt Enable 0 Masked 1 - // Enabled -#define MMCHS_IE_BGE_ENABLE 0x00000004 // Block Gap Event Interrupt Enable - // 0 Masked 1 Enabled -#define MMCHS_IE_TC_ENABLE 0x00000002 // Transfer completed Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_CC_ENABLE 0x00000001 // Command completed Interrupt - // Enable 0 Masked 1 Enabled -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_ISE register. -// -//****************************************************************************** -#define MMCHS_ISE_BADA_SIGEN 0x20000000 // Bad access to data space signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CERR_SIGEN 0x10000000 // Card error interrupt signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_ADMAE_SIGEN 0x02000000 // ADMA error signal status Enable - // 0 Masked 1 Enabled -#define MMCHS_ISE_ACE_SIGEN 0x01000000 // Auto CMD12 error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_DEB_SIGEN 0x00400000 // Data end bit error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_DCRC_SIGEN 0x00200000 // Data CRC error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_DTO_SIGEN 0x00100000 // Data timeout error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CIE_SIGEN 0x00080000 // Command index error signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CEB_SIGEN 0x00040000 // Command end bit error signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CCRC_SIGEN 0x00020000 // Command CRC error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CTO_SIGEN 0x00010000 // Command timeout error signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_NULL 0x00008000 // Fixed to 0 The host driver shall - // control error interrupts using - // the Error Interrupt Signal Enable - // register. Writes to this bit are - // ignored -#define MMCHS_ISE_BSR_SIGEN 0x00000400 // Boot status signal status - // EnableA write to this register - // when MMCHS_CON[BOOT_ACK] is set - // to 0x0 is ignored. 0 Masked 1 - // Enabled -#define MMCHS_ISE_OBI_SIGEN 0x00000200 // Out-Of-Band Interrupt signal - // status Enable A write to this - // register when MMCHS_CON[OBIE] is - // set to '0' is ignored. 0 Masked 1 - // Enabled -#define MMCHS_ISE_CIRQ_SIGEN 0x00000100 // Card interrupt signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CREM_SIGEN 0x00000080 // Card removal signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CINS_SIGEN 0x00000040 // Card insertion signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_BRR_SIGEN 0x00000020 // Buffer Read Ready signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_BWR_SIGEN 0x00000010 // Buffer Write Ready signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_DMA_SIGEN 0x00000008 // DMA interrupt Signal status - // enable 0 Masked 1 Enabled -#define MMCHS_ISE_BGE_SIGEN 0x00000004 // Black Gap Event signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_TC_SIGEN 0x00000002 // Transfer completed signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CC_SIGEN 0x00000001 // Command completed signal status - // Enable 0 Masked 1 Enabled -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_AC12 register. -// -//****************************************************************************** -#define MMCHS_AC12_CNI 0x00000080 -#define MMCHS_AC12_ACIE 0x00000010 -#define MMCHS_AC12_ACEB 0x00000008 -#define MMCHS_AC12_ACCE 0x00000004 -#define MMCHS_AC12_ACTO 0x00000002 -#define MMCHS_AC12_ACNE 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CAPA register. -// -//****************************************************************************** -#define MMCHS_CAPA_BIT64 0x10000000 -#define MMCHS_CAPA_VS18 0x04000000 -#define MMCHS_CAPA_VS30 0x02000000 -#define MMCHS_CAPA_VS33 0x01000000 -#define MMCHS_CAPA_SRS 0x00800000 -#define MMCHS_CAPA_DS 0x00400000 -#define MMCHS_CAPA_HSS 0x00200000 -#define MMCHS_CAPA_AD2S 0x00080000 -#define MMCHS_CAPA_MBL_M 0x00030000 -#define MMCHS_CAPA_MBL_S 16 -#define MMCHS_CAPA_BCF_M 0x00003F00 -#define MMCHS_CAPA_BCF_S 8 -#define MMCHS_CAPA_TCU 0x00000080 -#define MMCHS_CAPA_TCF_M 0x0000003F -#define MMCHS_CAPA_TCF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register. -// -//****************************************************************************** -#define MMCHS_CUR_CAPA_CUR_1V8_M \ - 0x00FF0000 - -#define MMCHS_CUR_CAPA_CUR_1V8_S 16 -#define MMCHS_CUR_CAPA_CUR_3V0_M \ - 0x0000FF00 - -#define MMCHS_CUR_CAPA_CUR_3V0_S 8 -#define MMCHS_CUR_CAPA_CUR_3V3_M \ - 0x000000FF - -#define MMCHS_CUR_CAPA_CUR_3V3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_FE register. -// -//****************************************************************************** -#define MMCHS_FE_FE_BADA 0x20000000 -#define MMCHS_FE_FE_CERR 0x10000000 -#define MMCHS_FE_FE_ADMAE 0x02000000 -#define MMCHS_FE_FE_ACE 0x01000000 -#define MMCHS_FE_FE_DEB 0x00400000 -#define MMCHS_FE_FE_DCRC 0x00200000 -#define MMCHS_FE_FE_DTO 0x00100000 -#define MMCHS_FE_FE_CIE 0x00080000 -#define MMCHS_FE_FE_CEB 0x00040000 -#define MMCHS_FE_FE_CCRC 0x00020000 -#define MMCHS_FE_FE_CTO 0x00010000 -#define MMCHS_FE_FE_CNI 0x00000080 -#define MMCHS_FE_FE_ACIE 0x00000010 -#define MMCHS_FE_FE_ACEB 0x00000008 -#define MMCHS_FE_FE_ACCE 0x00000004 -#define MMCHS_FE_FE_ACTO 0x00000002 -#define MMCHS_FE_FE_ACNE 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_ADMAES register. -// -//****************************************************************************** -#define MMCHS_ADMAES_LME 0x00000004 // ADMA Length Mismatch Error: (1) - // While Block Count Enable being - // set the total data length - // specified by the Descriptor table - // is different from that specified - // by the Block Count and Block - // Length. (2) Total data length can - // not be divided by the block - // length. 0 No Error 1 Error -#define MMCHS_ADMAES_AES_M 0x00000003 // ADMA Error State his field - // indicates the state of ADMA when - // error is occurred during ADMA - // data transfer. "This field never - // indicates ""10"" because ADMA - // never stops in this state." 0x0 - // ST_STOP (Stop DMA)Contents of - // SYS_SDR register 0x1 ST_STOP - // (Stop DMA)Points the error - // descriptor 0x2 Never set this - // state(Not used) 0x3 ST_TFR - // (Transfer Data)Points the next of - // the error descriptor -#define MMCHS_ADMAES_AES_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_ADMASAL register. -// -//****************************************************************************** -#define MMCHS_ADMASAL_ADMA_A32B_M \ - 0xFFFFFFFF // ADMA System address 32 bits.This - // register holds byte address of - // executing command of the - // Descriptor table. 32-bit Address - // Descriptor uses lower 32-bit of - // this register. At the start of - // ADMA the Host Driver shall set - // start address of the Descriptor - // table. The ADMA increments this - // register address which points to - // next line when every fetching a - // Descriptor line. When the ADMA - // Error Interrupt is generated this - // register shall hold valid - // Descriptor address depending on - // the ADMA state. The Host Driver - // shall program Descriptor Table on - // 32-bit boundary and set 32-bit - // boundary address to this - // register. ADMA2 ignores lower - // 2-bit of this register and - // assumes it to be 00b. - -#define MMCHS_ADMASAL_ADMA_A32B_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_REV register. -// -//****************************************************************************** -#define MMCHS_REV_VREV_M 0xFF000000 // Vendor Version Number: IP - // revision [7:4] Major revision - // [3:0] Minor revision Examples: - // 0x10 for 1.0 0x21 for 2.1 -#define MMCHS_REV_VREV_S 24 -#define MMCHS_REV_SREV_M 0x00FF0000 -#define MMCHS_REV_SREV_S 16 -#define MMCHS_REV_SIS 0x00000001 // Slot Interrupt Status This - // status bit indicates the inverted - // state of interrupt signal for the - // module. By a power on reset or by - // setting a software reset for all - // (MMCHS_HCTL[SRA]) the interrupt - // signal shall be de-asserted and - // this status shall read 0. - - - -#endif // __HW_MMCHS_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_nvic.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_nvic.h deleted file mode 100755 index c8c0c88fa34..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_nvic.h +++ /dev/null @@ -1,1708 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following are defines for the NVIC register addresses. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status - // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg - -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable -#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable -#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable -#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable -#define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable - -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable - -#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable -#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable -#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable -#define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable - -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending - -#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending -#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending -#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending -#define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending - -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending - -#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending -#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending -#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending -#define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending - -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit - -#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit -#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit -#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit -#define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit - -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority - -#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority -#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority -#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority -#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority -#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority -#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority -#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority -#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority -#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority -#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority -#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority -#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority -#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority -#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority -#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority -#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority -#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority -#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority -#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority -#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority -#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority -#define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority -#define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority -#define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority -#define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority -#define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority -#define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority -#define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority -#define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority -#define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority -#define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority -#define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority -#define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority -#define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority -#define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority - - - -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset - // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size - // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size - // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size - // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable - -#undef NVIC_EN1_INT_M -#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable - -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN2 register. -// -//***************************************************************************** -#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN3 register. -// -//***************************************************************************** -#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN4 register. -// -//***************************************************************************** -#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable - -#undef NVIC_DIS1_INT_M -#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable - -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS2 register. -// -//***************************************************************************** -#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS3 register. -// -//***************************************************************************** -#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS4 register. -// -//***************************************************************************** -#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending - -#undef NVIC_PEND1_INT_M -#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending - -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND2 register. -// -//***************************************************************************** -#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND3 register. -// -//***************************************************************************** -#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND4 register. -// -//***************************************************************************** -#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending - -#undef NVIC_UNPEND1_INT_M -#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND2 register. -// -//***************************************************************************** -#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND3 register. -// -//***************************************************************************** -#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND4 register. -// -//***************************************************************************** -#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active - -#undef NVIC_ACTIVE1_INT_M -#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active - -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE2 register. -// -//***************************************************************************** -#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE3 register. -// -//***************************************************************************** -#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE4 register. -// -//***************************************************************************** -#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI14 register. -// -//***************************************************************************** -#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask -#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask -#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask -#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask -#define NVIC_PRI14_INTD_S 29 -#define NVIC_PRI14_INTC_S 21 -#define NVIC_PRI14_INTB_S 13 -#define NVIC_PRI14_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI15 register. -// -//***************************************************************************** -#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask -#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask -#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask -#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask -#define NVIC_PRI15_INTD_S 29 -#define NVIC_PRI15_INTC_S 21 -#define NVIC_PRI15_INTB_S 13 -#define NVIC_PRI15_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI16 register. -// -//***************************************************************************** -#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask -#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask -#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask -#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask -#define NVIC_PRI16_INTD_S 29 -#define NVIC_PRI16_INTC_S 21 -#define NVIC_PRI16_INTB_S 13 -#define NVIC_PRI16_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI17 register. -// -//***************************************************************************** -#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask -#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask -#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask -#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask -#define NVIC_PRI17_INTD_S 29 -#define NVIC_PRI17_INTC_S 21 -#define NVIC_PRI17_INTB_S 13 -#define NVIC_PRI17_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI18 register. -// -//***************************************************************************** -#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask -#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask -#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask -#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask -#define NVIC_PRI18_INTD_S 29 -#define NVIC_PRI18_INTC_S 21 -#define NVIC_PRI18_INTB_S 13 -#define NVIC_PRI18_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI19 register. -// -//***************************************************************************** -#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask -#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask -#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask -#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask -#define NVIC_PRI19_INTD_S 29 -#define NVIC_PRI19_INTC_S 21 -#define NVIC_PRI19_INTB_S 13 -#define NVIC_PRI19_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI20 register. -// -//***************************************************************************** -#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask -#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask -#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask -#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask -#define NVIC_PRI20_INTD_S 29 -#define NVIC_PRI20_INTC_S 21 -#define NVIC_PRI20_INTB_S 13 -#define NVIC_PRI20_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI21 register. -// -//***************************************************************************** -#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask -#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask -#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask -#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask -#define NVIC_PRI21_INTD_S 29 -#define NVIC_PRI21_INTC_S 21 -#define NVIC_PRI21_INTB_S 13 -#define NVIC_PRI21_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI22 register. -// -//***************************************************************************** -#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask -#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask -#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask -#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask -#define NVIC_PRI22_INTD_S 29 -#define NVIC_PRI22_INTC_S 21 -#define NVIC_PRI22_INTB_S 13 -#define NVIC_PRI22_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI23 register. -// -//***************************************************************************** -#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask -#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask -#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask -#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask -#define NVIC_PRI23_INTD_S 29 -#define NVIC_PRI23_INTC_S 21 -#define NVIC_PRI23_INTB_S 13 -#define NVIC_PRI23_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI24 register. -// -//***************************************************************************** -#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask -#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask -#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask -#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask -#define NVIC_PRI24_INTD_S 29 -#define NVIC_PRI24_INTC_S 21 -#define NVIC_PRI24_INTB_S 13 -#define NVIC_PRI24_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI25 register. -// -//***************************************************************************** -#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask -#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask -#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask -#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask -#define NVIC_PRI25_INTD_S 29 -#define NVIC_PRI25_INTC_S 21 -#define NVIC_PRI25_INTB_S 13 -#define NVIC_PRI25_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI26 register. -// -//***************************************************************************** -#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask -#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask -#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask -#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask -#define NVIC_PRI26_INTD_S 29 -#define NVIC_PRI26_INTC_S 21 -#define NVIC_PRI26_INTB_S 13 -#define NVIC_PRI26_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI27 register. -// -//***************************************************************************** -#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask -#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask -#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask -#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask -#define NVIC_PRI27_INTD_S 29 -#define NVIC_PRI27_INTC_S 21 -#define NVIC_PRI27_INTB_S 13 -#define NVIC_PRI27_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI28 register. -// -//***************************************************************************** -#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask -#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask -#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask -#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask -#define NVIC_PRI28_INTD_S 29 -#define NVIC_PRI28_INTC_S 21 -#define NVIC_PRI28_INTB_S 13 -#define NVIC_PRI28_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI29 register. -// -//***************************************************************************** -#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask -#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask -#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask -#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask -#define NVIC_PRI29_INTD_S 29 -#define NVIC_PRI29_INTC_S 21 -#define NVIC_PRI29_INTB_S 13 -#define NVIC_PRI29_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI30 register. -// -//***************************************************************************** -#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask -#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask -#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask -#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask -#define NVIC_PRI30_INTD_S 29 -#define NVIC_PRI30_INTC_S 21 -#define NVIC_PRI30_INTB_S 13 -#define NVIC_PRI30_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI31 register. -// -//***************************************************************************** -#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask -#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask -#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask -#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask -#define NVIC_PRI31_INTD_S 29 -#define NVIC_PRI31_INTC_S 21 -#define NVIC_PRI31_INTB_S 13 -#define NVIC_PRI31_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI32 register. -// -//***************************************************************************** -#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask -#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask -#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask -#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask -#define NVIC_PRI32_INTD_S 29 -#define NVIC_PRI32_INTC_S 21 -#define NVIC_PRI32_INTB_S 13 -#define NVIC_PRI32_INTA_S 5 - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor - -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor - -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number - -#undef NVIC_INT_CTRL_VEC_PEN_M -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number - -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number - -#undef NVIC_INT_CTRL_VEC_ACT_M -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number - -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset - -#undef NVIC_VTABLE_OFFSET_M -#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset - -#define NVIC_VTABLE_OFFSET_S 9 - -#undef NVIC_VTABLE_OFFSET_S -#define NVIC_VTABLE_OFFSET_S 10 - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid - -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation - -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid - -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation - -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_NUMBER -// register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE_ADDR_S 5 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access -#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none -#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only -#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw -#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none -#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable -#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable -#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable -#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable -#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable -#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable -#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable -#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes -#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes -#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes -#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes -#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes -#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes -#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes -#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes -#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes -#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes -#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes -#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes -#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes -#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes -#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes -#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes -#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes -#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes -#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes -#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes -#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes -#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes -#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes -#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes -#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes -#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes -#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes -#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE1_ADDR_S 5 -#define NVIC_MPU_BASE1_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR1_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR1_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR1_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE2_ADDR_S 5 -#define NVIC_MPU_BASE2_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR2_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR2_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR2_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE3_ADDR_S 5 -#define NVIC_MPU_BASE3_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR3_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR3_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR3_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID - -#undef NVIC_SW_TRIG_INTID_M -#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID - -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ocp_shared.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ocp_shared.h deleted file mode 100755 index 670cad67103..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ocp_shared.h +++ /dev/null @@ -1,3443 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_OCP_SHARED_H__ -#define __HW_OCP_SHARED_H__ - -//***************************************************************************** -// -// The following are defines for the OCP_SHARED register offsets. -// -//***************************************************************************** -#define OCP_SHARED_O_SEMAPHORE1 0x00000000 -#define OCP_SHARED_O_SEMAPHORE2 0x00000004 -#define OCP_SHARED_O_SEMAPHORE3 0x00000008 -#define OCP_SHARED_O_SEMAPHORE4 0x0000000C -#define OCP_SHARED_O_SEMAPHORE5 0x00000010 -#define OCP_SHARED_O_SEMAPHORE6 0x00000014 -#define OCP_SHARED_O_SEMAPHORE7 0x00000018 -#define OCP_SHARED_O_SEMAPHORE8 0x0000001C -#define OCP_SHARED_O_SEMAPHORE9 0x00000020 -#define OCP_SHARED_O_SEMAPHORE10 \ - 0x00000024 - -#define OCP_SHARED_O_SEMAPHORE11 \ - 0x00000028 - -#define OCP_SHARED_O_SEMAPHORE12 \ - 0x0000002C - -#define OCP_SHARED_O_IC_LOCKER_ID \ - 0x00000030 - -#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \ - 0x00000034 - -#define OCP_SHARED_O_WL_SEMAPHORE_PEND \ - 0x00000038 - -#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \ - 0x0000003C - -#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \ - 0x00000040 - -#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \ - 0x00000044 - -#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \ - 0x00000048 - -#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \ - 0x0000004C - -#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \ - 0x00000050 - -#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \ - 0x00000054 - -#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \ - 0x00000058 - -#define OCP_SHARED_O_SSBD_SEED 0x0000005C -#define OCP_SHARED_O_SSBD_CHK 0x00000060 -#define OCP_SHARED_O_SSBD_POLY_SEL \ - 0x00000064 - -#define OCP_SHARED_O_SPARE_REG_0 \ - 0x00000068 - -#define OCP_SHARED_O_SPARE_REG_1 \ - 0x0000006C - -#define OCP_SHARED_O_SPARE_REG_2 \ - 0x00000070 - -#define OCP_SHARED_O_SPARE_REG_3 \ - 0x00000074 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \ - 0x000000A0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \ - 0x000000A4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \ - 0x000000A8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \ - 0x000000AC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \ - 0x000000B0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \ - 0x000000B4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \ - 0x000000B8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \ - 0x000000BC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \ - 0x000000C0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \ - 0x000000C4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \ - 0x000000C8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \ - 0x000000CC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \ - 0x000000D0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \ - 0x000000D4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \ - 0x000000D8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \ - 0x000000DC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \ - 0x000000E0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \ - 0x000000E4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \ - 0x000000E8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \ - 0x000000EC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \ - 0x000000F0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \ - 0x000000F4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \ - 0x000000F8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \ - 0x000000FC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \ - 0x00000100 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \ - 0x00000104 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \ - 0x00000108 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \ - 0x0000010C - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \ - 0x00000110 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \ - 0x00000114 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \ - 0x00000118 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \ - 0x0000011C - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \ - 0x00000120 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \ - 0x00000124 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \ - 0x00000128 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \ - 0x0000012C - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \ - 0x00000130 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \ - 0x00000134 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \ - 0x00000138 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \ - 0x0000013C - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \ - 0x00000140 - -#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \ - 0x00000144 // This register provide control to - // GPIO_CC3XXV1 IO PAD. Common - // control signals to all bottom Die - // IO's are controlled via this. - -#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \ - 0x00000148 - -#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \ - 0x0000014C - -#define OCP_SHARED_O_D2D_MISC_PAD_CONF \ - 0x00000150 - -#define OCP_SHARED_O_SOP_CONF_OVERRIDE \ - 0x00000154 - -#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \ - 0x00000158 - -#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \ - 0x0000015C - -#define OCP_SHARED_O_ALT_PC_VAL_NW \ - 0x00000160 - -#define OCP_SHARED_O_ALT_PC_VAL_APPS \ - 0x00000164 - -#define OCP_SHARED_O_SPARE_REG_4 \ - 0x00000168 - -#define OCP_SHARED_O_SPARE_REG_5 \ - 0x0000016C - -#define OCP_SHARED_O_SH_SPI_CS_MASK \ - 0x00000170 - -#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \ - 0x00000174 - -#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \ - 0x00000178 - -#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \ - 0x0000017C - -#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \ - 0x00000180 - -#define OCP_SHARED_O_CC3XX_DEV_PADCONF \ - 0x00000184 - -#define OCP_SHARED_O_SPARE_REG_8 \ - 0x00000188 - -#define OCP_SHARED_O_SPARE_REG_6 \ - 0x0000018C - -#define OCP_SHARED_O_SPARE_REG_7 \ - 0x00000190 - -#define OCP_SHARED_O_APPS_WLAN_ORBIT \ - 0x00000194 - -#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \ - 0x00000198 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE1 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE2 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE3 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE4 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE5 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE6 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE7 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE8 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE9 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE10 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE11 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE12 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_IC_LOCKER_ID register. -// -//****************************************************************************** -#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \ - 0x00000007 // This register is used for - // allowing only one master OCP to - // perform write transactions to the - // OCP slaves. Each bit represents - // an IP in the following format: { - // JTAG,WLAN, NWP mcu}. As any of - // the bits is set to one, the - // correlating IP is preventing the - // other IP's from performing write - // transactions to the slaves. As - // the Inter Connect is locked, the - // only the locking IP can write to - // the register and by that - // releasing the lock. 3'b000 => IC - // is not locked. 3'b001 => IC is - // locked by NWP mcu. 3'b010 => IC - // is locked by WLAN. 3'b100 => IC - // is locked by JTAG. - -#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_MCU_SEMAPHORE_PEND register. -// -//****************************************************************************** -#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \ - 0x0000FFFF // This register specifies the - // semaphore for which the NWP mcu - // is waiting to be released. It is - // set to the serial number of a - // given locked semaphore after it - // was read by the NWP mcu. Only - // [11:0] is used. - -#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_WL_SEMAPHORE_PEND register. -// -//****************************************************************************** -#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \ - 0x0000FFFF // This register specifies the - // semaphore for which the WLAN is - // waiting to be released. It is set - // to the serial number of a given - // locked semaphore after it was - // read by the WLAN. Only [11:0] is - // used. - -#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register. -// -//****************************************************************************** -#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \ - 0x0000FFFF // This information serves the IPs - // for knowing in which platform are - // they integrated at: 0 = CC31XX. - -#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \ - 0x00000FFF // Captured/released semaphores - // status for the 12 semaphores. - // Each bit of the 12 bits - // represents a semaphore. 0 => - // Semaphore Free. 1 => Semaphore - // Captured. - -#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_CONFIG_CTRL register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \ - 0x00000010 // This bit is used to enable - // timeout mechanism for top_ocp_ic - // (for debug puropse). When 1 value - // , in case any ocp slave doesn't - // give sresponse within 16 cylcles - // top_ic will give error response - // itself to avoid bus hange. - -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \ - 0x00000008 // 1 bit should be accessible only - // in devinit. This will enable 0x4 - // hack for apps processor - -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \ - 0x00000004 // 1 bit, should be accessible only - // in devinit. This will enable 0x4 - // hack for nw processor - -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \ - 0x00000002 // When set NW can take over apps - // rom and flash via IDCODE bus. - // Apps will able to access this - // register only during devinit and - // reset value should be 0. - -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \ - 0x00000001 // When this bit is set to 0 WPSI - // host interface wil be selected, - // when this bit is set to 1 , WLAN - // host async bridge will be - // selected. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \ - 0x3FFFFFFF // This register provides memss RAM - // column configuration for column 0 - // to 9. 3 bits are allocated per - // column. This register is required - // to be configured before starting - // RAM access. Changing register - // setting while code is running - // will result into unpredictable - // memory behaviour. Register is - // supported to configured ones - // after core is booted up. 3 bit - // encoding per column is as - // follows: when 000 : WLAN, 001: - // NWP, 010: APPS, 011: PHY, 100: - // OCLA column 0 select: bit [2:0] - // :when 000 -> WLAN,001 -> NWP,010 - // -> APPS, 011 -> PHY, 100 -> OCLA - // column 1 select: bit [5:3] - // :column 2 select: bit [8 : 6]: - // column 3 select : bit [11: 9] - // column 4 select : bit [14:12] - // column 5 select : bit [17:15] - // column 6 select : bit [20:18] - // column 7 select : bit [23:21] - // column 8 select : bit [26:24] - // column 9 select : bit [29:27] - // column 10 select - -#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \ - 0x00000FFF // This register provides memss RAM - // column configuration for column - // 10 to 15. 3 bits are allocated - // per column. This register is - // required to be configured before - // starting RAM access. Changing - // register setting while code is - // running will result into - // unpredictable memory behaviour. - // Register is supported to - // configured ones after core is - // booted up. 3 bit encoding per - // column is as follows: when 000 : - // WLAN, 001: NWP, 010: APPS, 011: - // PHY, 100: OCLA column 11 select : - // bit [2:0] column 12 select : bit - // [5:3] column 13 select : bit [8 : - // 6] column 14 select : - -#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_WLAN_ELP_WAKE_EN register. -// -//****************************************************************************** -#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \ - 0x00000001 // when '1' : signal will enabled - // ELP power doamin when '0': ELP is - // not powered up. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register. -// -//****************************************************************************** -#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \ - 0xFFFFFFFF // 32 bit, Writable only during - // devinit, and whole 32 bit should - // be output of the config register - // module. This register is not used - // , similar register availble in - // GPRCM space. - -#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register. -// -//****************************************************************************** -#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \ - 0xFFFFFFFF // 32 bit, Writable only during - // devinit, and whole 32 bit should - // be output of the config register - // module. - -#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SSBD_SEED register. -// -//****************************************************************************** -#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \ - 0xFFFFFFFF // 32 bit, Writable only during - // devinit, and whole 32 bit should - // be output of the config register - // module. - -#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SSBD_CHK register. -// -//****************************************************************************** -#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \ - 0xFFFFFFFF // 32 bit, Writable only during - // devinit, and whole 32 bit should - // be output of the config register - // module. - -#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SSBD_POLY_SEL register. -// -//****************************************************************************** -#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \ - 0x00000003 // 2 bit, Writable only during - // devinit, and whole 2 bit should - // be output of the config register - // module. - -#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_0 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \ - 0xFFFFFFFF // Devinit code should look for - // whether corresponding fuse is - // blown and if blown write to the - // 11th bit of this register to - // disable flshtst interface - -#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_1 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \ - 0xFFFFFFFF // NWP Software register - -#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_2 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \ - 0xFFFFFFFF // NWP Software register - -#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_3 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \ - 0xFFFFFFFF // APPS Software register - -#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." "For example in - // case of I2C Value gets latched at - // rising edge of RET33.""" """ 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \ - 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." "For example in - // case of I2C Value gets latched at - // rising edge of RET33.""" """ 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \ - 0x00000080 // when '1' enable ISO A control to - // D2D Pads else ISO is disabled. - // For these PADS to be functional - // this signals should be set 0. - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \ - 0x00000040 // when '1' enable ISO Y control to - // D2D Pads else ISO is disabled. - // For these PADS to be functional - // this signals should be set 0. - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \ - 0x00000020 // If level ‘1’ enables the PAD to - // ODI path for JTAG PADS [PAD 23, - // 24, 28, 29]. Else ODI is pulled - // ‘Low’ regardless of PAD level." - // "Value gets latched at rising - // edge of RET33.""" """ - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \ - 0x00000018 // 00’: hysteriris = 10% of VDDS - // (difference between upper and - // lower threshold of the schmit - // trigger) ‘01’: hysteriris = 20% - // of VDDS (difference between upper - // and lower threshold of the schmit - // trigger) ‘10’: hysteriris = 30% - // of VDDS (difference between upper - // and lower threshold of the schmit - // trigger) ‘11’: hysteriris = 40% - // of VDDS (difference between upper - // and lower threshold of the schmit - // trigger)" """ - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3 -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \ - 0x00000004 // If logic ‘0’ there is no - // hysteresis. Set to ‘1’ to enable - // hysteresis. Leave the choice to - // customers""" - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \ - 0x00000002 // Normal functional operation set - // this to logic ‘1’ to increase the - // speed of the o/p buffer at the - // cost of 0.2uA static current - // consumption per IO. During IDDQ - // test and during Hibernate this - // would be forced to logic ‘0’. - // Value is not latched at rising - // edge of RET33."" - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \ - 0x00000001 // If level ‘1’ enables the PAD to - // ODI path. Else ODI is pulled - // ‘Low’ regardless of PAD level." - // "Value gets latched at rising - // edge of RET33.""" """ - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register. -// -//****************************************************************************** -#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \ - 0x0000003F // this register implements common - // IO control to all devement mode - // PADs; these PADs are DEV_PAD33 to - // DEV_PAD39. Bit [1:0] : Drive - // strength control. These 2 bits - // are connected to DEV PAD drive - // strength control. possible drive - // stregnths are 2MA, 4MA and 6 MA - // for the these IO's. bit 0: when - // set to logic value '1' enable 2MA - // drive strength for DEVPAD01 to 07 - // bit 1: when set to logic value - // '1' enable 4MA drive strength for - // DEVPAD01 to 07. bit[3:2] : WK - // PULL UP and PULL down control. - // These 2 bits provide IWKPUEN and - // IWKPDEN control for all DEV IO's. - // bit 2: when set to logic value - // '1' enable WKPU to DEVPAD01 to 07 - // bit 3: when set to logic value - // '1' enable WKPD to DEVPAD01 to - // 07. bit 4: WK PULL control for - // DEV_PKG_DETECT pin. when '1' - // pullup enabled else it is - // disable. bit 5: when set to logic - // value '1' enable 8MA drive - // strength for DEVPAD01 to 07. - -#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register. -// -//****************************************************************************** -#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \ - 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - // this register control OEN2X pin - // of D2D TOSTACK PAD: OEN1X and - // OEN2X decoding is as follows: - // "when ""00"" :" "when ""01"" : - // dirve strength is '1' and output - // buffer enabled." "when ""10"" : - // drive strength is 2 and output - // buffer is disabled." "when ""11"" - // : dirve strength is '3' and - // output buffer enabled." - -#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_D2D_MISC_PAD_CONF register. -// -//****************************************************************************** -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \ - 0x00000200 // This register provide OEN2X - // control to D2D PADS OEN/OEN2X - // control. When 0 : Act as input - // buffer else output buffer with - // drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \ - 0x00000100 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \ - 0x00000080 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \ - 0x00000040 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \ - 0x00000020 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \ - 0x00000010 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \ - 0x00000008 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \ - 0x00000007 // D2D SPARE PAD OEN/OEN2X control. - // When 0: Act as input buffer else - // output buffer with drive strength - // 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SOP_CONF_OVERRIDE register. -// -//****************************************************************************** -#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \ - 0x00000001 // when '1' : signal will ovberride - // SoP setting of JTAG PADS. when - // '0': SoP setting will control - // JTAG PADs [ TDI, TDO, TMS, TCK] - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \ - 0x00000020 // This register contains debug - // subsystem status bits From APPS - // MCU status bit to indicates - // whether serial wire or 4 pins - // jtag select. - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \ - 0x00000010 // cjtag bypass bit select - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \ - 0x00000008 // serial wire interface bit select - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \ - 0x00000004 // apps tap enable status - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \ - 0x00000002 // tap enable status - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \ - 0x00000001 // ssbd unlock status - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \ - 0x0000FFFF // debug mux select register. Upper - // 8 bits are used for debug module - // selection. Lower 8 bit [7:0] used - // inside debug module for selecting - // module specific signals. - // Bits[15:8: when set x"00" : GPRCM - // debug bus. When "o1" : SDIO debug - // debug bus when x"02" : - // autonoumous SPI when x"03" : - // TOPIC when x"04": memss when - // x"25": mcu debug bus : APPS debug - // when x"45": mcu debug bus : NWP - // debug when x"65": mcu debug bus : - // AHB2VBUS debug when x"85": mcu - // debug bus : VBUS2HAB debug when - // x"95": mcu debug bus : RCM debug - // when x"A5": mcu debug bus : - // crypto debug when x"06": WLAN - // debug bus when x"07": debugss bus - // when x"08": ADC debug when x"09": - // SDIO PHY debug bus then "others" - // : no debug is selected - -#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_ALT_PC_VAL_NW register. -// -//****************************************************************************** -#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \ - 0xFFFFFFFF // 32 bit. Program counter value - // for 0x4 address when Alt_pc_en_nw - // is set. - -#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_ALT_PC_VAL_APPS register. -// -//****************************************************************************** -#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \ - 0xFFFFFFFF // 32 bit. Program counter value - // for 0x4 address when - // Alt_pc_en_apps is set - -#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_4 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \ - 0xFFFFFFFE // HW register - -#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1 -#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \ - 0x00000001 // Data to the top die launched at - // negative edge instead of positive - // edge. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_5 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \ - 0xFFFFFFFF // HW register - -#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SH_SPI_CS_MASK register. -// -//****************************************************************************** -#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \ - 0x0000000F // ( chip select 0 is unmasked - // after reset. When ‘1’ : CS is - // unmasked or else masked. Valid - // configurations are 1000, 0100, - // 0010 or 0001. Any other setting - // can lead to unpredictable - // behavior. - -#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEVICE_TYPE register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \ - 0x00000060 // reserved bits tied off "00". - -#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5 -#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \ - 0x0000001F // CC3XX Device type information. - -#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register. -// -//****************************************************************************** -#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \ - 0x000000F0 // [4] 1: switch between - // WLAN_I2C_SCL and - // TOP_GPIO_PORT4_I2C closes 0: - // switch opens [5] 1: switch - // between WLAN_I2C_SCL and - // TOP_VSENSE_PORT closes 0: switch - // opens [6] 1: switch between - // WLAN_I2C_SCL and WLAN_ANA_TP4 - // closes 0: switch opens [7] - // Reserved - -#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4 -#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \ - 0x0000000F // [0] 1: switch between - // WLAN_I2C_SDA and - // TOP_GPIO_PORT3_I2C closes 0: - // switch opens [1] 1: switch - // between WLAN_I2C_SDA and - // TOP_IFORCE_PORT closes 0: switch - // opens [2] 1: switch between - // WLAN_I2C_SDA and WLAN_ANA_TP3 - // closes 0: switch opens [3] - // Reserved - -#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \ - 0x00000001 // when '0' indicates package type - // is development. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_AUTONMS_SPICLK_SEL register. -// -//****************************************************************************** -#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \ - 0x00000002 // This bit is used to bypass MCPSI - // autonomous mode .if this bit is 1 - // autonomous MCSPI logic will be - // bypassed and it will act as link - // SPI - -#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \ - 0x00000001 // This bit is used in SPI - // Autonomous mode to switch clock - // from system clock to SPI clk that - // is coming from PAD. When value 1 - // PAD SPI clk is used as system - // clock in LPDS mode by SPI as well - // as autonomous wrapper logic. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEV_PADCONF register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \ - 0x0000FFFF - -#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_IDMEM_TIM_UPDATE register. -// -//****************************************************************************** -#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \ - 0xFFFFFFFF - -#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_6 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \ - 0xFFFFFFFF // NWP Software register - -#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_7 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \ - 0xFFFFFFFF // NWP Software register - -#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_APPS_WLAN_ORBIT register. -// -//****************************************************************************** -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \ - 0xFFFFFC00 // Spare bit - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10 -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \ - 0x00000200 // A rising edge on this bit - // indicates that the test case - // passes. This bit would be brought - // out on the pin interface during - // ORBIT. - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \ - 0x00000100 // This register bit is writable by - // the FW and when set to 1 it - // indicates the start of a test - // execution. A failing edge on this - // bit indicates that the test - // execution is complete. This bit - // would be brought out on the pin - // interface during ORBIT. - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \ - 0x000000FC // Implies the test case ID that - // needs to run. - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2 -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \ - 0x00000002 // This bit is used to trigger the - // execution of test cases within - // the (ROM based) IP. - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \ - 0x00000001 // When this bit is 1 it implies - // ORBIT mode of operation and the - // (ROM based) IP start the - // execution from a test case - // perspective - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register. -// -//****************************************************************************** -#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \ - 0xFFFFFFFF // scratch pad register. - -#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0 - - - -#endif // __HW_OCP_SHARED_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_shamd5.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_shamd5.h deleted file mode 100755 index aaee0ef4bde..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_shamd5.h +++ /dev/null @@ -1,1240 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_SHAMD5_H__ -#define __HW_SHAMD5_H__ - -//***************************************************************************** -// -// The following are defines for the SHAMD5_P register offsets. -// -//***************************************************************************** -#define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for - // MD5 [159:128] for SHA-1 [255:224] - // for SHA-2 / HMAC Key [31:0] for - // HMAC key proc READ: Outer Digest - // [127:96] for MD5 [159:128] for - // SHA-1 [255:224] for SHA-2 -#define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for - // MD5 [127:96] for SHA-1 [223:192] - // for SHA-2 / HMAC Key [63:32] for - // HMAC key proc READ: Outer Digest - // [95:64] for MD5 [127:96] for - // SHA-1 [223:192] for SHA-2 -#define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for - // MD5 [95:64] for SHA-1 [191:160] - // for SHA-2 / HMAC Key [95:64] for - // HMAC key proc READ: Outer Digest - // [63:32] for MD5 [95:64] for SHA-1 - // [191:160] for SHA-2 -#define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for - // MD5 [63:31] for SHA-1 [159:128] - // for SHA-2 / HMAC Key [127:96] for - // HMAC key proc READ: Outer Digest - // [31:0] for MD5 [63:32] for SHA-1 - // [159:128] for SHA-2 -#define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for - // SHA-1 [127:96] for SHA-2 / HMAC - // Key [159:128] for HMAC key proc - // READ: Outer Digest [31:0] for - // SHA-1 [127:96] for SHA-2 -#define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for - // SHA-2 / HMAC Key [191:160] for - // HMAC key proc READ: Outer Digest - // [95:64] for SHA-2 -#define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for - // SHA-2 / HMAC Key [223:192] for - // HMAC key proc READ: Outer Digest - // [63:32] for SHA-2 -#define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for - // SHA-2 / HMAC Key [255:224] for - // HMAC key proc READ: Outer Digest - // [31:0] for SHA-2 -#define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest - // [127:96] for MD5 [159:128] for - // SHA-1 [255:224] for SHA-2 / HMAC - // Key [287:256] for HMAC key proc - // READ: Intermediate / Inner Digest - // [127:96] for MD5 [159:128] for - // SHA-1 [255:224] for SHA-2 / - // Result Digest/MAC [127:96] for - // MD5 [159:128] for SHA-1 [223:192] - // for SHA-2 224 [255:224] for SHA-2 - // 256 -#define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest - // [95:64] for MD5 [127:96] for - // SHA-1 [223:192] for SHA-2 / HMAC - // Key [319:288] for HMAC key proc - // READ: Intermediate / Inner Digest - // [95:64] for MD5 [127:96] for - // SHA-1 [223:192] for SHA-2 / - // Result Digest/MAC [95:64] for MD5 - // [127:96] for SHA-1 [191:160] for - // SHA-2 224 [223:192] for SHA-2 256 -#define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest - // [63:32] for MD5 [95:64] for SHA-1 - // [191:160] for SHA- 2 / HMAC Key - // [351:320] for HMAC key proc READ: - // Intermediate / Inner Digest - // [63:32] for MD5 [95:64] for SHA-1 - // [191:160] for SHA-2 / Result - // Digest/MAC [63:32] for MD5 - // [95:64] for SHA-1 [159:128] for - // SHA-2 224 [191:160] for SHA-2 256 -#define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest - // [31:0] for MD5 [63:32] for SHA-1 - // [159:128] for SHA-2 / HMAC Key - // [383:352] for HMAC key proc READ: - // Intermediate / Inner Digest - // [31:0] for MD5 [63:32] for SHA-1 - // [159:128] for SHA-2 / Result - // Digest/MAC [31:0] for MD5 [63:32] - // for SHA-1 [127:96] for SHA-2 224 - // [159:128] for SHA-2 256 -#define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest - // [31:0] for SHA-1 [127:96] for - // SHA-2 / HMAC Key [415:384] for - // HMAC key proc READ: Intermediate - // / Inner Digest [31:0] for SHA-1 - // [127:96] for SHA-2 / Result - // Digest/MAC [31:0] for SHA-1 - // [95:64] for SHA-2 224 [127:96] - // for SHA-2 256 -#define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest - // [95:64] for SHA-2 / HMAC Key - // [447:416] for HMAC key proc READ: - // Intermediate / Inner Digest - // [95:64] for SHA-2 / Result - // Digest/MAC [63:32] for SHA-2 224 - // [95:64] for SHA-2 256 -#define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest - // [63:32] for SHA-2 / HMAC Key - // [479:448] for HMAC key proc READ: - // Intermediate / Inner Digest - // [63:32] for SHA-2 / Result - // Digest/MAC [31:0] for SHA-2 224 - // [63:32] for SHA-2 256 -#define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest - // [31:0] for SHA-2 / HMAC Key - // [511:480] for HMAC key proc READ: - // Intermediate / Inner Digest - // [31:0] for SHA-2 / Result - // Digest/MAC [31:0] for SHA-2 256 -#define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count - // ([31:6] only [5:0] assumed 0) - // READ: Result / IntermediateDigest - // Count The initial digest byte - // count for hash/HMAC continue - // operations (HMAC Key Processing = - // 0 and Use Algorithm Constants = - // 0) on the Secure World must be - // written to this register prior to - // starting the operation by writing - // to S_HASH_MODE. When either HMAC - // Key Processing is 1 or Use - // Algorithm Constants is 1 this - // register does not need to be - // written it will be overwritten - // with 64 (1 hash block of key XOR - // ipad) or 0 respectively - // automatically. When starting a - // HMAC operation from pre-computes - // (HMAC Key Processing is 0) then - // the value 64 must be written here - // to compensate for the appended - // key XOR ipad block. Note that the - // value written should always be a - // 64 byte multiple the lower 6 bits - // written are ignored. The updated - // digest byte count (initial digest - // byte count + bytes processed) can - // be read from this register when - // the status register indicates - // that the operation is done or - // suspended due to a context switch - // request or when a Secure World - // context out DMA is requested. In - // Advanced DMA mode when not - // suspended with a partial result - // reading the SHAMD5_DIGEST_COUNT - // register triggers the Hash/HMAC - // Engine to start the next context - // input DMA. Therefore reading the - // SHAMD5_DIGEST_COUNT register - // should always be the last - // context-read action if not - // suspended with a partial result - // (i.e. PartHashReady interrupt not - // pending). -#define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE -#define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining - // Byte Count (bytes) READ: - // Remaining Byte Count. The value - // programmed MUST be a 64-byte - // multiple if Close Hash is set to - // 0. This register is also the - // trigger to start processing: once - // this register is written the core - // will commence requesting input - // data via DMA or IRQ (if - // programmed length > 0) and start - // processing. The remaining byte - // count for the active operation - // can be read from this register - // when the interrupt status - // register indicates that the - // operation is suspended due to a - // context switch request. -#define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0 -#define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1 -#define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2 -#define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3 -#define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4 -#define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5 -#define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6 -#define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7 -#define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8 -#define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9 -#define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10 -#define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11 -#define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12 -#define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13 -#define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14 -#define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15 -#define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV -#define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG -#define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS -#define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS -#define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The - // SHAMD5_IRQENABLE register contains - // an enable bit for each unique - // interrupt for the public side. An - // interrupt is enabled when both - // the global enable in - // SHAMD5_SYSCONFIG (PIT_en) and the - // bit in this register are both set - // to 1. An interrupt that is - // enabled is propagated to the - // SINTREQUEST_P output. Please note - // that the dedicated partial hash - // output (SINTREQUEST_PART_P) is - // not affected by this register it - // is only affected by the global - // enable SHAMD5_SYSCONFIG (PIT_en). -#define SHAMD5_O_HASH512_ODIGEST_A \ - 0x00000200 - -#define SHAMD5_O_HASH512_ODIGEST_B \ - 0x00000204 - -#define SHAMD5_O_HASH512_ODIGEST_C \ - 0x00000208 - -#define SHAMD5_O_HASH512_ODIGEST_D \ - 0x0000020C - -#define SHAMD5_O_HASH512_ODIGEST_E \ - 0x00000210 - -#define SHAMD5_O_HASH512_ODIGEST_F \ - 0x00000214 - -#define SHAMD5_O_HASH512_ODIGEST_G \ - 0x00000218 - -#define SHAMD5_O_HASH512_ODIGEST_H \ - 0x0000021C - -#define SHAMD5_O_HASH512_ODIGEST_I \ - 0x00000220 - -#define SHAMD5_O_HASH512_ODIGEST_J \ - 0x00000224 - -#define SHAMD5_O_HASH512_ODIGEST_K \ - 0x00000228 - -#define SHAMD5_O_HASH512_ODIGEST_L \ - 0x0000022C - -#define SHAMD5_O_HASH512_ODIGEST_M \ - 0x00000230 - -#define SHAMD5_O_HASH512_ODIGEST_N \ - 0x00000234 - -#define SHAMD5_O_HASH512_ODIGEST_O \ - 0x00000238 - -#define SHAMD5_O_HASH512_ODIGEST_P \ - 0x0000023C - -#define SHAMD5_O_HASH512_IDIGEST_A \ - 0x00000240 - -#define SHAMD5_O_HASH512_IDIGEST_B \ - 0x00000244 - -#define SHAMD5_O_HASH512_IDIGEST_C \ - 0x00000248 - -#define SHAMD5_O_HASH512_IDIGEST_D \ - 0x0000024C - -#define SHAMD5_O_HASH512_IDIGEST_E \ - 0x00000250 - -#define SHAMD5_O_HASH512_IDIGEST_F \ - 0x00000254 - -#define SHAMD5_O_HASH512_IDIGEST_G \ - 0x00000258 - -#define SHAMD5_O_HASH512_IDIGEST_H \ - 0x0000025C - -#define SHAMD5_O_HASH512_IDIGEST_I \ - 0x00000260 - -#define SHAMD5_O_HASH512_IDIGEST_J \ - 0x00000264 - -#define SHAMD5_O_HASH512_IDIGEST_K \ - 0x00000268 - -#define SHAMD5_O_HASH512_IDIGEST_L \ - 0x0000026C - -#define SHAMD5_O_HASH512_IDIGEST_M \ - 0x00000270 - -#define SHAMD5_O_HASH512_IDIGEST_N \ - 0x00000274 - -#define SHAMD5_O_HASH512_IDIGEST_O \ - 0x00000278 - -#define SHAMD5_O_HASH512_IDIGEST_P \ - 0x0000027C - -#define SHAMD5_O_HASH512_DIGEST_COUNT \ - 0x00000280 - -#define SHAMD5_O_HASH512_MODE 0x00000284 -#define SHAMD5_O_HASH512_LENGTH 0x00000288 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_A_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_B_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_C_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_D_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_E_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_F_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_G_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_H_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_A_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_B_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_C_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_D_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_E_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_F_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_G_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_H_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_DIGEST_COUNT register. -// -//****************************************************************************** -#define SHAMD5_DIGEST_COUNT_DATA_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DIGEST_COUNT_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_MODE register. -// -//****************************************************************************** -#define SHAMD5_MODE_HMAC_OUTER_HASH \ - 0x00000080 // The HMAC Outer Hash is performed - // on the hash digest when the inner - // hash hash finished (block length - // exhausted and final hash - // performed if close_hash is 1). - // This bit should normally be set - // together with close_hash to - // finish the inner hash first or - // Block Length should be zero (HMAC - // continue with the just outer hash - // to be done). Auto cleared - // internally when outer hash - // performed. 0 No operation 1 hmac - // processing - -#define SHAMD5_MODE_HMAC_KEY_PROC \ - 0x00000020 // Performs HMAC key processing on - // the 512 bit HMAC key loaded into - // the SHAMD5_IDIGEST_{A to H} and - // SHAMD5_ODIGEST_{A to H} register - // block. Once HMAC key processing - // is finished this bit is - // automatically cleared and the - // resulting Inner and Outer digest - // is available from - // SHAMD5_IDIGEST_{A to H} and - // SHAMD5_ODIGEST_{A to H} - // respectively after which regular - // hash processing (using - // SHAMD5_IDIGEST_{A to H} as initial - // digest) will commence until the - // Block Length is exhausted. 0 No - // operation. 1 Hmac processing. - -#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the - // hash/HMAC will be 'closed' at the - // end of the block as per - // MD5/SHA-1/SHA-2 specification - // (i.e. appropriate padding is - // added) or no padding is done - // allowing the hash to be continued - // later. However if the hash/HMAC - // is not closed then the Block - // Length MUST be a multiple of 64 - // bytes to ensure correct - // operation. Auto cleared - // internally when hash closed. 0 No - // padding hash computation can be - // contimued. 1 Last packet will be - // padded. -#define SHAMD5_MODE_ALGO_CONSTANT \ - 0x00000008 // The initial digest register will - // be overwritten with the algorithm - // constants for the selected - // algorithm when hashing and the - // initial digest count register - // will be reset to 0. This will - // start a normal hash operation. - // When continuing an existing hash - // or when performing an HMAC - // operation this register must be - // set to 0 and the - // intermediate/inner digest or HMAC - // key and digest count need to be - // written to the context input - // registers prior to writing - // SHAMD5_MODE. Auto cleared - // internally after first block - // processed. 0 Use pre-calculated - // digest (from an other operation) - // 1 Use constants of the selected - // algo. - -#define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash - // algorithm to be used for - // processing: 0x0 md5_128 algorithm - // 0x1 sha1_160 algorithm 0x2 - // sha2_224 algorithm 0x3 sha2_256 - // algorithm -#define SHAMD5_MODE_ALGO_S 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_LENGTH register. -// -//****************************************************************************** -#define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data -#define SHAMD5_LENGTH_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA0_IN_DATA0_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA0_IN_DATA0_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA1_IN_DATA1_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA1_IN_DATA1_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA2_IN_DATA2_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA2_IN_DATA2_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA3_IN_DATA3_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA3_IN_DATA3_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA4_IN_DATA4_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA4_IN_DATA4_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA5_IN_DATA5_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA5_IN_DATA5_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA6_IN_DATA6_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA6_IN_DATA6_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA7_IN_DATA7_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA7_IN_DATA7_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA8_IN_DATA8_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA8_IN_DATA8_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA9_IN_DATA9_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA9_IN_DATA9_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA10_IN_DATA10_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA10_IN_DATA10_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA11_IN_DATA11_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA11_IN_DATA11_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA12_IN_DATA12_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA12_IN_DATA12_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA13_IN_DATA13_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA13_IN_DATA13_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA14_IN_DATA14_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA14_IN_DATA14_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA15_IN_DATA15_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA15_IN_DATA15_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_REVISION register. -// -//****************************************************************************** -#define SHAMD5_REVISION_SCHEME_M 0xC0000000 -#define SHAMD5_REVISION_SCHEME_S 30 -#define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define SHAMD5_REVISION_FUNC_S 16 -#define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP - // design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define SHAMD5_REVISION_R_RTL_S 11 -#define SHAMD5_REVISION_X_MAJOR_M \ - 0x00000700 // Major Revision (X) maintained by - // IP specification owner. X changes - // ONLY when: (1) There is a major - // feature addition. An example - // would be adding Master Mode to - // Utopia Level2. The Func field (or - // Class/Type in old PID format) - // will remain the same. X does NOT - // change due to: (1) Bug fixes (2) - // Change in feature parameters. - -#define SHAMD5_REVISION_X_MAJOR_S 8 -#define SHAMD5_REVISION_CUSTOM_M 0x000000C0 -#define SHAMD5_REVISION_CUSTOM_S 6 -#define SHAMD5_REVISION_Y_MINOR_M \ - 0x0000003F // Minor Revision (Y) maintained by - // IP specification owner. Y changes - // ONLY when: (1) Features are - // scaled (up or down). Flexibility - // exists in that this feature - // scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R S X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless the spec tracks the - // IP bugs. An RTL release (say for - // silicon PG1.1) that occurs due to - // bug fix should document the - // corresponding spec number (X.Y.S) - // in its release notes. - -#define SHAMD5_REVISION_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register. -// -//****************************************************************************** -#define SHAMD5_SYSCONFIG_PADVANCED \ - 0x00000080 // If set to 1 Advanced mode is - // enabled for the Secure World. If - // set to 0 Legacy mode is enabled - // for the Secure World. - -#define SHAMD5_SYSCONFIG_PCONT_SWT \ - 0x00000040 // Finish all pending data and - // context DMA input requests (but - // will not assert any new requests) - // finish processing all data in the - // module and provide a saved - // context (partial hash result - // updated digest count remaining - // length updated mode information - // where applicable) for the last - // operation that was interrupted so - // that it can be resumed later. - -#define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008 -#define SHAMD5_SYSCONFIG_PIT_EN 0x00000004 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register. -// -//****************************************************************************** -#define SHAMD5_SYSSTATUS_RESETDONE \ - 0x00000001 // data - -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register. -// -//****************************************************************************** -#define SHAMD5_IRQSTATUS_CONTEXT_READY \ - 0x00000008 // indicates that the secure side - // context input registers are - // available for a new context for - // the next packet to be processed. - -#define SHAMD5_IRQSTATUS_PARTHASH_READY \ - 0x00000004 // After a secure side context - // switch request this bit will read - // as 1 indicating that the saved - // context is available from the - // secure side context output - // registers. Note that if the - // context switch request coincides - // with a final hash (when hashing) - // or an outer hash (when doing - // HMAC) that PartHashReady will not - // become active but a regular - // Output Ready will occur instead - // (indicating that the result is - // final and therefore no - // continuation is required). - -#define SHAMD5_IRQSTATUS_INPUT_READY \ - 0x00000002 // indicates that the secure side - // data FIFO is ready to receive the - // next 64 byte data block. - -#define SHAMD5_IRQSTATUS_OUTPUT_READY \ - 0x00000001 // Indicates that a (partial) - // result or saved context is - // available from the secure side - // context output registers. - -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register. -// -//****************************************************************************** -#define SHAMD5_IRQENABLE_M_CONTEXT_READY \ - 0x00000008 // mask for context ready - -#define SHAMD5_IRQENABLE_M_PARTHASH_READY \ - 0x00000004 // mask for partial hash - -#define SHAMD5_IRQENABLE_M_INPUT_READY \ - 0x00000002 // mask for input_ready - -#define SHAMD5_IRQENABLE_M_OUTPUT_READY \ - 0x00000001 // mask for output_ready - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_A register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_A_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_A_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_B register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_B_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_B_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_C register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_C_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_C_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_D register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_D_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_D_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_E register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_E_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_E_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_F register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_F_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_F_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_G register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_G_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_G_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_H register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_H_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_H_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_I register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_I_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_I_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_J register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_J_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_J_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_K register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_K_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_K_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_L register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_L_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_L_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_M register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_M_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_M_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_N register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_N_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_N_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_O register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_O_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_O_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_P register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_A register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_A_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_A_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_B register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_B_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_B_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_C register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_C_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_C_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_D register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_D_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_D_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_E register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_E_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_E_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_F register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_F_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_F_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_G register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_G_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_G_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_H register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_H_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_H_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_I register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_I_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_I_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_J register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_J_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_J_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_K register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_K_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_K_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_L register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_L_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_L_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_M register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_M_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_M_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_N register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_N_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_N_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_O register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_O_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_O_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_P register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_DIGEST_COUNT register. -// -//****************************************************************************** -#define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_MODE register. -// -//****************************************************************************** -#define SHAMD5_HASH512_MODE_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_MODE_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_LENGTH register. -// -//****************************************************************************** -#define SHAMD5_HASH512_LENGTH_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_LENGTH_DATA_S 0 - - - -#endif // __HW_SHAMD5_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h deleted file mode 100755 index d406163277c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h +++ /dev/null @@ -1,762 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef __HW_STACK_DIE_CTRL_H__ -#define __HW_STACK_DIE_CTRL_H__ - -//***************************************************************************** -// -// The following are defines for the STACK_DIE_CTRL register offsets. -// -//***************************************************************************** -#define STACK_DIE_CTRL_O_STK_UP_RESET \ - 0x00000000 // Can be written only by Base - // Processor. Writing to this - // register will reset the stack - // processor reset will be - // de-asserted upon clearing this - // register. - -#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \ - 0x00000004 // This register defines who among - // base processor and stack - // processor have highest priority - // for Sram Access. Can be written - // only by Base Processor. - -#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \ - 0x00000008 // In Spinlock mode this Register - // defines who among base processor - // and stack processor have access - // to Sram Bank2 right now. In - // Handshake mode this Register - // defines who among base processor - // and stack processor have access - // to Sram Bank2 and Bank3 right - // now. Its Clear only register and - // is set by hardware. Lower bit can - // be cleared only by Base Processor - // and Upper bit Cleared only by the - // Stack processor. - -#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \ - 0x0000000C // In Spinlock mode whenever Base - // processor wants the access to - // Sram Bank2 it should request for - // it by writing into this register. - // It'll get interrupt whenever it - // is granted. In Handshake mode - // this bit will be set by Stack - // processor. Its a set only bit and - // is cleared by HW when the request - // is granted. - -#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \ - 0x00000010 // In Spinlock mode Whenever Stack - // processor wants the access to - // Sram Bank2 it should request for - // it by writing into this register. - // It'll get interrupt whenever it - // is granted. In Handshake mode - // this bit will be set by the Base - // processor. Its a set only bit and - // is cleared by HW when the request - // is granted. - -#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \ - 0x00000014 // Register defines who among base - // processor and stack processor - // have access to Sram Bank3 right - // now. Its Clear only register and - // is set by hardware. Lower bit can - // be cleared only by Base Processor - // and Upper bit Cleared only by the - // Stack processor. - -#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \ - 0x00000018 // In Spinlock mode whenever Base - // processor wants the access to - // Sram Bank3 it should request for - // it by writing into this register. - // It'll get interrupt whenever it - // is granted. In Handshake mode - // this bit will be set by Stack - // processor. Its a set only bit and - // is cleared by HW when the request - // is granted. - -#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \ - 0x0000001C // In Spinlock mode Whenever Stack - // processor wants the access to - // Sram Bank3 it should request for - // it by writing into this register. - // It'll get interrupt whenever it - // is granted. In Handshake mode - // this bit will be set by the Base - // processor. Its a set only bit and - // is cleared by HW when the request - // is granted. - -#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \ - 0x00000020 // Read State Machine timing - // configuration register. Generally - // Bit 4 and 3 will be identical. - // For stacked die always 43 are 0 - // and 6:5 == 1 for 120Mhz. - -#define STACK_DIE_CTRL_O_RDSM_CFG_EE \ - 0x00000024 // Read State Machine timing - // configuration register. Generally - // Bit 4 and 3 will be identical. - // For stacked die always 43 are 0 - // and 6:5 == 1 for 120Mhz. - -#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \ - 0x00000028 // Reading this register Base - // procesor will able to know the - // reason for the interrupt. This is - // clear only register - set by HW - // upon an interrupt to Base - // processor and can be cleared only - // by BASE processor. - -#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \ - 0x0000002C // Reading this register Stack - // procesor will able to know the - // reason for the interrupt. This is - // clear only register - set by HW - // upon an interrupt to Stack - // processor and can be cleared only - // by Stack processor. - -#define STACK_DIE_CTRL_O_STK_CLK_EN \ - 0x00000030 // Can be written only by base - // processor. Controls the enable - // pin of the cgcs for the clocks - // going to CM3 dft ctrl block and - // Sram. - -#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \ - 0x00000034 // Can be written only by the base - // processor. Decides the ram - // sharing mode :: handshake or - // Spinlock mode. - -#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \ - 0x00000038 // Stores the last bus fault - // address. - -#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \ - 0x0000003C // write only registers on read - // returns 0.W Write 1 to clear the - // bust fault to store the new bus - // fault address - -#define STACK_DIE_CTRL_O_RESET_CAUSE \ - 0x00000040 // Reset cause value captured from - // the ICR_CLKRST block. - -#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \ - 0x00000044 // Watchdog timer event value - // captured from the ICR_CLKRST - // block - -#define STACK_DIE_CTRL_O_DMA_REQ \ - 0x00000048 // To send Dma Request to bottom - // die. - -#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \ - 0x0000004C // Address offset within SRAM to - // which CM3 should jump after - // reset. - -#define STACK_DIE_CTRL_O_SW_REG1 \ - 0x00000050 // These are sw registers for - // topdie processor and bottom die - // processor to communicate. Both - // can set and read these registers. - // In case of write clash bottom - // die's processor wins and top die - // processor access is ignored. - -#define STACK_DIE_CTRL_O_SW_REG2 \ - 0x00000054 // These are sw registers for - // topdie processor and bottom die - // processor to communicate. Both - // can set and read these registers. - // In case of write clash bottom - // die's processor wins and top die - // processor access is ignored. - -#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \ - 0x00000058 // By posting the request Flash can - // be put into low-power mode - // (Sleep) without powering down the - // Flash. Earlier (in Garnet) this - // was fully h/w controlled and the - // control for this was coming from - // SysCtl while entering into Cortex - // Deep-sleep mode. But for our - // device the D2D i/f doesnt support - // this. The Firmware has to program - // the register in the top-die for - // entering into this mode and wait - // for an interrupt. - -#define STACK_DIE_CTRL_O_MISC_CTL \ - 0x0000005C // Miscellanious control register. - -#define STACK_DIE_CTRL_O_SW_DFT_CTL \ - 0x000000FC // DFT control and status bits - -#define STACK_DIE_CTRL_O_PADN_CTL_0 \ - 0x00000100 // Mainly for For controlling the - // pads OEN pins. There are total 60 - // pads and hence 60 control registe - // i.e n value varies from 0 to 59. - // Here is the mapping for the - // pad_ctl register number and the - // functionality : 0 D2DPAD_DMAREQ1 - // 1 D2DPAD_DMAREQ0 2 - // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 - // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 - // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 - // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS - // 10 D2DPAD_JTAG_TDI 11-27 - // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE - // -1:0] 28-56 D2DPAD_TOSTACK - // [D2D_TOSTACK_SIZE -1:0] 57-59 - // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE - // -1:0] 0:00 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_UP_RESET register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \ - 0x00000001 // 1 :Assert Reset 0 : Deassert the - // Reset - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \ - 0x00000003 // 00 : Equal Priority 01 : Stack - // Processor have priority 10 : Base - // Processor have priority 11 : - // Unused - -#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \ - 0x00000002 // Stack Processor should clear it - // when it is done with the sram - // bank usage. Set by HW It is set - // when Stack Processor is granted - // the access to this bank - -#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \ - 0x00000001 // Base Processor should clear it - // when it is done wth the sram - // usage. Set by HW It is set when - // Base Processor is granted the - // access to this bank - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \ - 0x00000001 // Base Processor will set when - // Sram access is needed in Spin - // Lock mode. In Handshake mode - // Stack Processor will set to - // inform Base Processor that it is - // done with the processing of data - // in SRAM and is now ready to use - // by the base processor. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \ - 0x00000001 // Stack Processor will set when - // Sram access is needed in Spin - // Lock mode. In Handshake mode Base - // Processor will set to inform - // Stack Processor to start - // processing the data in the Ram. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \ - 0x00000002 // Stack Processor should clear it - // when it is done with the sram - // bank usage. Set by HW It is set - // when Stack Processor is granted - // the access to this bank. - -#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \ - 0x00000001 // Base Processor should clear it - // when it is done wth the sram - // usage. Set by HW it is set when - // Base Processor is granted the - // access to this bank. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \ - 0x00000001 // Base Processor will set when - // Sram access is needed in Spin - // Lock mode. Not used in handshake - // mode. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \ - 0x00000001 // Stack Processor will set when - // Sram access is needed in Spin - // Lock mode. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_RDSM_CFG_CPU register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \ - 0x000000C0 // Bank Clock Hi Time 00 : HCLK - // pulse 01 : 1 cycle of HCLK 10 : - // 1.5 cycles of HCLK 11 : 2 cycles - // of HCLK - -#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6 -#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \ - 0x00000020 // FLCLK 0 : indicates flash clock - // rise aligns on HCLK rise 1 : - // indicates flash clock rise aligns - // on HCLK fall - -#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \ - 0x00000010 // 0 : Always register flash rdata - // before sending to CPU 1 : Drive - // Flash rdata directly out on MISS - // (Both ICODE / DCODE) - -#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \ - 0x0000000F // Number of wait states inserted - -#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_RDSM_CFG_EE register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \ - 0x000000C0 // Bank Clock Hi Time 00 : HCLK - // pulse 01 : 1 cycle of HCLK 10 : - // 1.5 cycles of HCLK 11 : 2 cycles - // of HCLK - -#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6 -#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \ - 0x00000020 // FLCLK 0 : indicates flash clock - // rise aligns on HCLK rise 1 : - // indicates flash clock rise aligns - // on HCLK fall - -#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \ - 0x00000010 // 0 : Always register flash rdata - // before sending to CPU 1 : Drive - // Flash rdata directly out on MISS - // (Both ICODE / DCODE) - -#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \ - 0x0000000F // Number of wait states inserted - -#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \ - 0x00000010 // Set when Relinquish Interrupt - // sent to Base processor for Bank3. - -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \ - 0x00000008 // Set when Relinquish Interrupt - // sent to Base processor for Bank2. - -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \ - 0x00000004 // Set when Bank3 is granted to - // Base processor. - -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \ - 0x00000002 // Set when Bank2 is granted to - // BAse processor. - -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \ - 0x00000001 // Set when there Base processor do - // an Invalid access to Sram. Ex : - // Accessing the bank which is not - // granted for BAse processor. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \ - 0x00000008 // Set when Relinquish Interrupt - // sent to Stack processor for - // Bank3. - -#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \ - 0x00000004 // Set when Relinquish Interrupt - // sent to Stack processor for - // Bank2. - -#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \ - 0x00000002 // Set when Bank3 is granted to - // Stack processor. - -#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \ - 0x00000001 // Set when Bank2 is granted to - // Stack processor. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_CLK_EN register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \ - 0x00000004 // Enable the clock going to sram. - -#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \ - 0x00000002 // Enable the clock going to dft - // control block - -#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \ - 0x00000001 // Enable the clock going to Cm3 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \ - 0x00000001 // 0 : Handshake Mode 1 : Spinlock - // mode. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \ - 0xFFFFFFFF // Fault Address - -#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BUS_FAULT_CLR register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \ - 0x00000001 // When set it'll clear the bust - // fault address register to store - // the new bus fault address - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_RESET_CAUSE register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_DMA_REQ register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \ - 0x00000002 // Generate DMAREQ1 on setting this - // bit. - -#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \ - 0x00000001 // Generate DMAREQ0 on setting this - // bit. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SW_REG1 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SW_REG2 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \ - 0x00000002 // captures the status of of - // fmc_lpm_ack - -#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \ - 0x00000001 // When set assert - // iflpe2fmc_lpm_req to FMC. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_MISC_CTL register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \ - 0x00000080 // 1 : will reset the async wdog - // timer runing on piosc clock - -#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \ - 0x00000020 // Setting this Will send to - // interttupt to CM3 - -#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \ - 0x00000010 // Setting this Will send to - // interttupt to CM3 - -#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \ - 0x00000008 // Setting this Will send to - // interttupt to CM3 - -#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \ - 0x00000004 // While testing Flash Setting this - // bit will Control the - // CE/STR/AIN/CLKIN going to flash - // banks 12 and 3. 0 : Control - // signals coming from FMC for Bank - // 3 goes to Bank3 1 : Control - // signals coming from FMC for Bank - // 0 goes to Bank2 - -#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \ - 0x00000002 // While testing Flash Setting this - // bit will Control the - // CE/STR/AIN/CLKIN going to flash - // banks 12 and 3. 0 : Control - // signals coming from FMC for Bank - // 2 goes to Bank2 1 : Control - // signals coming from FMC for Bank - // 0 goes to Bank2 - -#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \ - 0x00000001 // While testing Flash Setting this - // bit will Control the - // CE/STR/AIN/CLKIN going to flash - // banks 12 and 3. 0 : Control - // signals coming from FMC for Bank - // 1 goes to Bank1 1 : Control - // signals coming from FMC for Bank - // 0 goes to Bank1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SW_DFT_CTL register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \ - 0x20000000 // when set to '1' all flash - // control signals switch over to - // CM3 control when '0' it is under - // the D2D interface control - -#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \ - 0x10000000 // 1 indicates in SWIF mode the - // control signals to flash are from - // FMC CPU read controls the clock - // and address. that is one can give - // address via FMC and read through - // IDMEM. - -#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \ - 0x00800000 // 'CPU Done' bit for PBIST. Write - // '1' to indicate test done. - -#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \ - 0x00400000 // 'CPU Fail' bit for PBIST. Write - // '1' to indicate test failed. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \ - 0x00001000 // when set to '1' flash bank 4 - // (EEPROM) is owned by the CM3for - // reads over DCODE bus. When '0' - // access control given to D2D - // interface. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \ - 0x00000800 // when set to '1' flash bank 3 is - // owned by the CM3for reads over - // DCODE bus. When '0' access - // control given to D2D interface. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \ - 0x00000400 // when set to '1' flash bank 2 is - // owned by the CM3for reads over - // DCODE bus. When '0' access - // control given to D2D interface. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \ - 0x00000200 // when set to '1' flash bank 1 is - // owned by the CM3for reads over - // DCODE bus. When '0' access - // control given to D2D interface. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \ - 0x00000100 // when set to '1' flash bank 0 is - // owned by the CM3 for reads over - // DCODE bus. When '0' access - // control given to D2D interface. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_PADN_CTL_0 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \ - 0x00000008 // This bit is valid for only the - // spare pads ie for n=57 to 59. - // value to drive at the output of - // the pad - -#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \ - 0x00000004 // This bit is valid for only the - // spare pads ie for n=57 to 59. - // captures the 'Y' pin of the pad - // which is the data being driven - // into the die - -#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \ - 0x00000002 // OEN2X control when '1' enables - // the output with 1x. Total drive - // strength is decided bu oen1x - // setting + oen2x setting. - -#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \ - 0x00000001 // OEN1X control when '1' enables - // the output with 1x . Total drive - // strength is decided bu oen1x - // setting + oen2x setting. - - - - -#endif // __HW_STACK_DIE_CTRL_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_timer.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_timer.h deleted file mode 100755 index af36c3fff3f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_timer.h +++ /dev/null @@ -1,776 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -//***************************************************************************** - -//##### INTERNAL BEGIN ##### -// -// This is an auto-generated file. Do not edit by hand. -// Created by version 6779 of DriverLib. -// -//##### INTERNAL END ##### - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following are defines for the Timer register offsets. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // GPTM Configuration -#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode -#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode -#define TIMER_O_CTL 0x0000000C // GPTM Control -//##### GARNET BEGIN ##### -#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize -//##### GARNET END ##### -#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask -#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status -#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status -#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear -#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load -#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load -#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match -#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match -#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale -#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale -#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match -#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match -#define TIMER_O_TAR 0x00000048 // GPTM Timer A -#define TIMER_O_TBR 0x0000004C // GPTM Timer B -#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value -#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value -#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide -#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot -#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot -#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value -#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value -#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event -#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties - - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_M 0x00000007 // GPTM Configuration -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) - // counter configuration -#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The - // function is controlled by bits - // 1:0 of GPTMTAMR and GPTMTBMR - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy - // Operation -#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register - // Update -#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt - // Enable -#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write -//##### GARNET END ##### -#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode -#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger -#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt - // Enable -#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction -#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode - // Select -#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode -#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode -#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy - // Operation -#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register - // Update -#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt - // Enable -#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write -//##### GARNET END ##### -#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode -#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger -#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt - // Enable -#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction -#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode - // Select -#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode -#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode -#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level -#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger - // Enable -#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode -#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges -#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable -#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable -#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level -#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger - // Enable -#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable -#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode -#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges -#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable -#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable -//##### GARNET BEGIN ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_SYNC register. -// -//***************************************************************************** -#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11 -#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of - // GPTM11 is triggered -#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of - // GPTM11 is triggered -#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A - // and Timer B of GPTM11 is - // triggered -#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10 -#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of - // GPTM10 is triggered -#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of - // GPTM10 is triggered -#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A - // and Timer B of GPTM10 is - // triggered -#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9 -#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of - // GPTM9 is triggered -#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of - // GPTM9 is triggered -#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A - // and Timer B of GPTM9 is - // triggered -#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8 -#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of - // GPTM8 is triggered -#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of - // GPTM8 is triggered -#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A - // and Timer B of GPTM8 is - // triggered -#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7 -#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of - // GPTM7 is triggered -#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of - // GPTM7 is triggered -#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM7 is - // triggered -#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6 -#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of - // GPTM6 is triggered -#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of - // GPTM6 is triggered -#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM6 is - // triggered -#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5 -#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of - // GPTM5 is triggered -#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of - // GPTM5 is triggered -#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A - // and Timer B of GPTM5 is - // triggered -#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4 -#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of - // GPTM4 is triggered -#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of - // GPTM4 is triggered -#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A - // and Timer B of GPTM4 is - // triggered -#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3 -#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of - // GPTM3 is triggered -#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of - // GPTM3 is triggered -#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A - // and Timer B of GPTM3 is - // triggered -#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2 -#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of - // GPTM2 is triggered -#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of - // GPTM2 is triggered -#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A - // and Timer B of GPTM2 is - // triggered -#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1 -#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of - // GPTM1 is triggered -#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of - // GPTM1 is triggered -#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A - // and Timer B of GPTM1 is - // triggered -#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0 -#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of - // GPTM0 is triggered -#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of - // GPTM0 is triggered -#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A - // and Timer B of GPTM0 is - // triggered -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_IMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update - // Error Interrupt Mask -//##### GARNET END ##### -#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match - // Interrupt Mask -#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt - // Mask -#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt - // Mask -#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt - // Mask -#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match - // Interrupt Mask -#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask -#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt - // Mask -#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt - // Mask -#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RIS register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update - // Error Raw Interrupt Status -//##### GARNET END ##### -#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw - // Interrupt -#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw - // Interrupt -#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw - // Interrupt -#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw - // Interrupt -#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw - // Interrupt -#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt -#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw - // Interrupt -#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw - // Interrupt -#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_MIS register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update - // Error Masked Interrupt Status -//##### GARNET END ##### -#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked - // Interrupt -#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked - // Interrupt -#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked - // Interrupt -#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked - // Interrupt -#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked - // Interrupt -#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt -#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked - // Interrupt -#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked - // Interrupt -#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ICR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update - // Error Interrupt Clear -//##### GARNET END ##### -#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match - // Interrupt Clear -#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt - // Clear -#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt - // Clear -#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt - // Clear -#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match - // Interrupt Clear -#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear -#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt - // Clear -#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt - // Clear -#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAILR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load - // Register -//##### GARNET END ##### -#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load - // Register High -#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load - // Register Low -#define TIMER_TAILR_TAILRH_S 16 -#define TIMER_TAILR_TAILRL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TAILR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBILR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load - // Register -//##### GARNET END ##### -#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load - // Register -#define TIMER_TBILR_TBILRL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TBILR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMATCHR -// register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register -//##### GARNET END ##### -#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High -#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low -#define TIMER_TAMATCHR_TAMRH_S 16 -#define TIMER_TAMATCHR_TAMRL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TAMATCHR_TAMR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMATCHR -// register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register -//##### GARNET END ##### -#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low -//##### GARNET BEGIN ##### -#define TIMER_TBMATCHR_TBMR_S 0 -//##### GARNET END ##### -#define TIMER_TBMATCHR_TBMRL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte -//##### GARNET END ##### -#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale -//##### GARNET BEGIN ##### -#define TIMER_TAPR_TAPSRH_S 8 -//##### GARNET END ##### -#define TIMER_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte -//##### GARNET END ##### -#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale -//##### GARNET BEGIN ##### -#define TIMER_TBPR_TBPSRH_S 8 -//##### GARNET END ##### -#define TIMER_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High - // Byte -//##### GARNET END ##### -#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match -//##### GARNET BEGIN ##### -#define TIMER_TAPMR_TAPSMRH_S 8 -//##### GARNET END ##### -#define TIMER_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High - // Byte -//##### GARNET END ##### -#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match -//##### GARNET BEGIN ##### -#define TIMER_TBPMR_TBPSMRH_S 8 -//##### GARNET END ##### -#define TIMER_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register -//##### GARNET END ##### -#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High -#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low -#define TIMER_TAR_TARH_S 16 -#define TIMER_TAR_TARL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TAR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register -//##### GARNET END ##### -#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B -#define TIMER_TBR_TBRL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TBR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAV register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value -//##### GARNET END ##### -#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High -#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low -#define TIMER_TAV_TAVH_S 16 -#define TIMER_TAV_TAVL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TAV_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBV register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value -//##### GARNET END ##### -#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register -#define TIMER_TBV_TBVL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TBV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RTCPD register. -// -//***************************************************************************** -#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value -#define TIMER_RTCPD_RTCPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPS register. -// -//***************************************************************************** -#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot -#define TIMER_TAPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPS register. -// -//***************************************************************************** -#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TBPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPV register. -// -//***************************************************************************** -#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TAPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPV register. -// -//***************************************************************************** -#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value -#define TIMER_TBPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_PP register. -// -//***************************************************************************** -#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start -#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers -#define TIMER_PP_SIZE_M 0x0000000F // Count Size -#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are - // 16 bits each with an 8-bit - // prescale counter -#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are - // 32 bits each with an 16-bit - // prescale counter -//##### GARNET END ##### - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_CFG -// register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_CTL -// register. -// -//***************************************************************************** -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_RIS -// register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_TAILR -// register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_TBILR -// register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the -// TIMER_O_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the -// TIMER_O_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_TAR -// register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_TBR -// register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -//***************************************************************************** -// -// The following are deprecated defines for the reset values of the timer -// registers. -// -//***************************************************************************** -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_TnMR -// register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_TnPR -// register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_TnPMR -// register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -#endif - -#endif // __HW_TIMER_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_types.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_types.h deleted file mode 100755 index 30f4270dd9c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_types.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - - -#endif // __HW_TYPES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_uart.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_uart.h deleted file mode 100755 index 9c2604ccbea..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_uart.h +++ /dev/null @@ -1,415 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// The following are defines for the UART register offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 -#define UART_O_RSR 0x00000004 -#define UART_O_ECR 0x00000004 -#define UART_O_FR 0x00000018 -#define UART_O_ILPR 0x00000020 -#define UART_O_IBRD 0x00000024 -#define UART_O_FBRD 0x00000028 -#define UART_O_LCRH 0x0000002C -#define UART_O_CTL 0x00000030 -#define UART_O_IFLS 0x00000034 -#define UART_O_IM 0x00000038 -#define UART_O_RIS 0x0000003C -#define UART_O_MIS 0x00000040 -#define UART_O_ICR 0x00000044 -#define UART_O_DMACTL 0x00000048 -#define UART_O_LCTL 0x00000090 -#define UART_O_LSS 0x00000094 -#define UART_O_LTIM 0x00000098 -#define UART_O_9BITADDR 0x000000A4 -#define UART_O_9BITAMASK 0x000000A8 -#define UART_O_PP 0x00000FC0 -#define UART_O_CC 0x00000FC8 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//****************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//****************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//****************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//****************************************************************************** -#define UART_FR_RI 0x00000100 // Ring Indicator -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy -#define UART_FR_DCD 0x00000004 // Data Carrier Detect -#define UART_FR_DSR 0x00000002 // Data Set Ready -#define UART_FR_CTS 0x00000001 // Clear To Send -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//****************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//****************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//****************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//****************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 : - // UART_LCRH_WLEN_5 : 5 bits - // (default) 0x00000020 : - // UART_LCRH_WLEN_6 : 6 bits - // 0x00000040 : UART_LCRH_WLEN_7 : 7 - // bits 0x00000060 : - // UART_LCRH_WLEN_8 : 8 bits -#define UART_LCRH_WLEN_S 5 -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//****************************************************************************** -#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send -#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send -#define UART_CTL_RI 0x00002000 // Ring Indicator -#define UART_CTL_DCD 0x00001000 // Data Carrier Detect -#define UART_CTL_RTS 0x00000800 // Request to Send -#define UART_CTL_DTR 0x00000400 // Data Terminal Ready -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_LIN 0x00000040 // LIN Mode Enable -#define UART_CTL_HSE 0x00000020 // High-Speed Enable -#define UART_CTL_EOT 0x00000010 // End of Transmission -#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//****************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX_S 3 -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//****************************************************************************** -#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask -#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask -#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask -#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask -#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt - // Mask -#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask -#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt - // Mask -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask -#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem - // Interrupt Mask -#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Mask -#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem - // Interrupt Mask -#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem - // Interrupt Mask -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//****************************************************************************** -#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt - // Status -#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status -#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt - // Status -#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt - // Status -#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw - // Interrupt Status -#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status -#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw - // Interrupt Status -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status -#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw - // Interrupt Status -#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem - // Raw Interrupt Status -#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw - // Interrupt Status -#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw - // Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//****************************************************************************** -#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt - // Status -#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt - // Status -#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt - // Status -#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt - // Status -#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked - // Interrupt Status -#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt - // Status -#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked - // Interrupt Status -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status -#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked - // Interrupt Status -#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem - // Masked Interrupt Status -#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked - // Interrupt Status -#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked - // Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//****************************************************************************** -#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear -#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear -#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear -#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear -#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt - // Clear -#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear -#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt - // Clear -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem - // Interrupt Clear -#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Clear -#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem - // Interrupt Clear -#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem - // Interrupt Clear -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DMACTL register. -// -//****************************************************************************** -#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error -#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCTL register. -// -//****************************************************************************** -#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 : - // UART_LCTL_BLEN_13T : Sync break - // length is 13T bits (default) - // 0x00000010 : UART_LCTL_BLEN_14T : - // Sync break length is 14T bits - // 0x00000020 : UART_LCTL_BLEN_15T : - // Sync break length is 15T bits - // 0x00000030 : UART_LCTL_BLEN_16T : - // Sync break length is 16T bits -#define UART_LCTL_BLEN_S 4 -#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LSS register. -// -//****************************************************************************** -#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot -#define UART_LSS_TSS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LTIM register. -// -//****************************************************************************** -#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value -#define UART_LTIM_TIMER_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UART_O_9BITADDR register. -// -//****************************************************************************** -#define UART_9BITADDR_9BITEN \ - 0x00008000 // Enable 9-Bit Mode - -#define UART_9BITADDR_ADDR_M \ - 0x000000FF // Self Address for 9-Bit Mode - -#define UART_9BITADDR_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UART_O_9BITAMASK register. -// -//****************************************************************************** -#define UART_9BITAMASK_RANGE_M \ - 0x0000FF00 // Self Address Range for 9-Bit - // Mode - -#define UART_9BITAMASK_RANGE_S 8 -#define UART_9BITAMASK_MASK_M \ - 0x000000FF // Self Address Mask for 9-Bit Mode - -#define UART_9BITAMASK_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_PP register. -// -//****************************************************************************** -#define UART_PP_MSE 0x00000008 // Modem Support Extended -#define UART_PP_MS 0x00000004 // Modem Support -#define UART_PP_NB 0x00000002 // 9-Bit Support -#define UART_PP_SC 0x00000001 // Smart Card Support -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CC register. -// -//****************************************************************************** -#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source - // 0x00000005 : UART_CC_CS_PIOSC : - // PIOSC 0x00000000 : - // UART_CC_CS_SYSCLK : The system - // clock (default) -#define UART_CC_CS_S 0 - - - -#endif // __HW_UART_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_udma.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_udma.h deleted file mode 100755 index 8f01306ccbd..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_udma.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_UDMA_H__ -#define __HW_UDMA_H__ - -//***************************************************************************** -// -// The following are defines for the UDMA register offsets. -// -//***************************************************************************** -#define UDMA_O_STAT 0x00000000 -#define UDMA_O_CFG 0x00000004 -#define UDMA_O_CTLBASE 0x00000008 -#define UDMA_O_ALTBASE 0x0000000C -#define UDMA_O_WAITSTAT 0x00000010 -#define UDMA_O_SWREQ 0x00000014 -#define UDMA_O_USEBURSTSET 0x00000018 -#define UDMA_O_USEBURSTCLR 0x0000001C -#define UDMA_O_REQMASKSET 0x00000020 -#define UDMA_O_REQMASKCLR 0x00000024 -#define UDMA_O_ENASET 0x00000028 -#define UDMA_O_ENACLR 0x0000002C -#define UDMA_O_ALTSET 0x00000030 -#define UDMA_O_ALTCLR 0x00000034 -#define UDMA_O_PRIOSET 0x00000038 -#define UDMA_O_PRIOCLR 0x0000003C -#define UDMA_O_ERRCLR 0x0000004C -#define UDMA_O_CHASGN 0x00000500 -#define UDMA_O_CHIS 0x00000504 -#define UDMA_O_CHMAP0 0x00000510 -#define UDMA_O_CHMAP1 0x00000514 -#define UDMA_O_CHMAP2 0x00000518 -#define UDMA_O_CHMAP3 0x0000051C -#define UDMA_O_PV 0x00000FB0 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_STAT register. -// -//****************************************************************************** -#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 -#define UDMA_STAT_DMACHANS_S 16 -#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status - // 0x00000090 : UDMA_STAT_STATE_DONE - // : Done 0x00000000 : - // UDMA_STAT_STATE_IDLE : Idle - // 0x00000010 : - // UDMA_STAT_STATE_RD_CTRL : Reading - // channel controller data - // 0x00000030 : - // UDMA_STAT_STATE_RD_DSTENDP : - // Reading destination end pointer - // 0x00000040 : - // UDMA_STAT_STATE_RD_SRCDAT : - // Reading source data 0x00000020 : - // UDMA_STAT_STATE_RD_SRCENDP : - // Reading source end pointer - // 0x00000080 : - // UDMA_STAT_STATE_STALL : Stalled - // 0x000000A0 : - // UDMA_STAT_STATE_UNDEF : Undefined - // 0x00000060 : UDMA_STAT_STATE_WAIT - // : Waiting for uDMA request to - // clear 0x00000070 : - // UDMA_STAT_STATE_WR_CTRL : Writing - // channel controller data - // 0x00000050 : - // UDMA_STAT_STATE_WR_DSTDAT : - // Writing destination data -#define UDMA_STAT_STATE_S 4 -#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CFG register. -// -//****************************************************************************** -#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CTLBASE register. -// -//****************************************************************************** -#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address -#define UDMA_CTLBASE_ADDR_S 10 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ALTBASE register. -// -//****************************************************************************** -#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address - // Pointer -#define UDMA_ALTBASE_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_WAITSTAT register. -// -//****************************************************************************** -#define UDMA_WAITSTAT_WAITREQ_M \ - 0xFFFFFFFF // Channel [n] Wait Status - -#define UDMA_WAITSTAT_WAITREQ_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SWREQ register. -// -//****************************************************************************** -#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request -#define UDMA_SWREQ_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UDMA_O_USEBURSTSET register. -// -//****************************************************************************** -#define UDMA_USEBURSTSET_SET_M \ - 0xFFFFFFFF // Channel [n] Useburst Set - -#define UDMA_USEBURSTSET_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UDMA_O_USEBURSTCLR register. -// -//****************************************************************************** -#define UDMA_USEBURSTCLR_CLR_M \ - 0xFFFFFFFF // Channel [n] Useburst Clear - -#define UDMA_USEBURSTCLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_REQMASKSET register. -// -//****************************************************************************** -#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set -#define UDMA_REQMASKSET_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register. -// -//****************************************************************************** -#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear -#define UDMA_REQMASKCLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ENASET register. -// -//****************************************************************************** -#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set -#define UDMA_ENASET_CHENSET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ENACLR register. -// -//****************************************************************************** -#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear -#define UDMA_ENACLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ALTSET register. -// -//****************************************************************************** -#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set -#define UDMA_ALTSET_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ALTCLR register. -// -//****************************************************************************** -#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear -#define UDMA_ALTCLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_PRIOSET register. -// -//****************************************************************************** -#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set -#define UDMA_PRIOSET_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_PRIOCLR register. -// -//****************************************************************************** -#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear -#define UDMA_PRIOCLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ERRCLR register. -// -//****************************************************************************** -#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHASGN register. -// -//****************************************************************************** -#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select -#define UDMA_CHASGN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHIS register. -// -//****************************************************************************** -#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status -#define UDMA_CHIS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHMAP0 register. -// -//****************************************************************************** -#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select -#define UDMA_CHMAP0_CH7SEL_S 28 -#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select -#define UDMA_CHMAP0_CH6SEL_S 24 -#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select -#define UDMA_CHMAP0_CH5SEL_S 20 -#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select -#define UDMA_CHMAP0_CH4SEL_S 16 -#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select -#define UDMA_CHMAP0_CH3SEL_S 12 -#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select -#define UDMA_CHMAP0_CH2SEL_S 8 -#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select -#define UDMA_CHMAP0_CH1SEL_S 4 -#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select -#define UDMA_CHMAP0_CH0SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHMAP1 register. -// -//****************************************************************************** -#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select -#define UDMA_CHMAP1_CH15SEL_S 28 -#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select -#define UDMA_CHMAP1_CH14SEL_S 24 -#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select -#define UDMA_CHMAP1_CH13SEL_S 20 -#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select -#define UDMA_CHMAP1_CH12SEL_S 16 -#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select -#define UDMA_CHMAP1_CH11SEL_S 12 -#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select -#define UDMA_CHMAP1_CH10SEL_S 8 -#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select -#define UDMA_CHMAP1_CH9SEL_S 4 -#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select -#define UDMA_CHMAP1_CH8SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHMAP2 register. -// -//****************************************************************************** -#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select -#define UDMA_CHMAP2_CH23SEL_S 28 -#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select -#define UDMA_CHMAP2_CH22SEL_S 24 -#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select -#define UDMA_CHMAP2_CH21SEL_S 20 -#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select -#define UDMA_CHMAP2_CH20SEL_S 16 -#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select -#define UDMA_CHMAP2_CH19SEL_S 12 -#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select -#define UDMA_CHMAP2_CH18SEL_S 8 -#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select -#define UDMA_CHMAP2_CH17SEL_S 4 -#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select -#define UDMA_CHMAP2_CH16SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHMAP3 register. -// -//****************************************************************************** -#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select -#define UDMA_CHMAP3_CH31SEL_S 28 -#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select -#define UDMA_CHMAP3_CH30SEL_S 24 -#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select -#define UDMA_CHMAP3_CH29SEL_S 20 -#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select -#define UDMA_CHMAP3_CH28SEL_S 16 -#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select -#define UDMA_CHMAP3_CH27SEL_S 12 -#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select -#define UDMA_CHMAP3_CH26SEL_S 8 -#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select -#define UDMA_CHMAP3_CH25SEL_S 4 -#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select -#define UDMA_CHMAP3_CH24SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_PV register. -// -//****************************************************************************** -#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision -#define UDMA_PV_MAJOR_S 8 -#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision -#define UDMA_PV_MINOR_S 0 - - - -#endif // __HW_UDMA_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_wdt.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_wdt.h deleted file mode 100755 index 75d5591afe3..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_wdt.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_WDT_H__ -#define __HW_WDT_H__ - -//***************************************************************************** -// -// The following are defines for the WDT register offsets. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 -#define WDT_O_VALUE 0x00000004 -#define WDT_O_CTL 0x00000008 -#define WDT_O_ICR 0x0000000C -#define WDT_O_RIS 0x00000010 -#define WDT_O_MIS 0x00000014 -#define WDT_O_TEST 0x00000418 -#define WDT_O_LOCK 0x00000C00 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOAD register. -// -//****************************************************************************** -#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value -#define WDT_LOAD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_VALUE register. -// -//****************************************************************************** -#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value -#define WDT_VALUE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_CTL register. -// -//****************************************************************************** -#define WDT_CTL_WRC 0x80000000 // Write Complete -#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type -#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit - // is not used in cc3xx, WDOG shall - // always generate RESET to system - // irrespective of this bit setting. -#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_ICR register. -// -//****************************************************************************** -#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear -#define WDT_ICR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_RIS register. -// -//****************************************************************************** -#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_MIS register. -// -//****************************************************************************** -#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_TEST register. -// -//****************************************************************************** -#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable -#define WDT_TEST_STALL_EN_S 10 -#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//****************************************************************************** -#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock -#define WDT_LOCK_S 0 -#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WDT_LOCK_LOCKED 0x00000001 // Locked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and -// WDT_MIS registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - - - - - -#endif // __HW_WDT_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.c deleted file mode 100644 index 7332b511539..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== PWM.c ======== - */ - -#include -#include -#include - -#include -#include - -extern const PWM_Config PWM_config[]; -extern const uint_least8_t PWM_count; - -/* Default PWM parameters structure */ -const PWM_Params PWM_defaultParams = { - .periodUnits = PWM_PERIOD_US, /* Period is defined in Hz */ - .periodValue = PWM_DEFAULT_PERIOD_US, /* 1US */ - .dutyUnits = PWM_DUTY_FRACTION, /* Duty is fraction of period */ - .dutyValue = PWM_DEFAULT_DUTY_PERCENT, /* 0% duty cycle */ - .idleLevel = PWM_IDLE_LOW, /* Low idle level */ - .custom = NULL /* No custom params */ -}; - -static bool isInitialized = false; - -/* - * ======== PWM_close ======== - */ -void PWM_close(PWM_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== PWM_control ======== - */ -int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, void *arg) -{ - return handle->fxnTablePtr->controlFxn(handle, cmd, arg); -} - -/* - * ======== PWM_init ======== - */ -void PWM_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < PWM_count; i++) { - PWM_config[i].fxnTablePtr->initFxn((PWM_Handle) &(PWM_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== PWM_open ======== - */ -PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params) -{ - PWM_Handle handle = NULL; - - if (isInitialized && (index < PWM_count)) { - /* If params are NULL use defaults */ - if (params == NULL) { - params = (PWM_Params *) &PWM_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (PWM_Handle) &(PWM_config[index]); - - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== PWM_Params_init ======== - */ -void PWM_Params_init(PWM_Params *params) -{ - *params = PWM_defaultParams; -} - -/* - * ======== PWM_setDuty ======== - */ -int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty) -{ - return(handle->fxnTablePtr->setDutyFxn(handle, duty)); -} - -/* - * ======== PWM_setDuty ======== - */ -int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period) -{ - return(handle->fxnTablePtr->setPeriodFxn(handle, period)); -} - -/* - * ======== PWM_start ======== - */ -void PWM_start(PWM_Handle handle) -{ - handle->fxnTablePtr->startFxn(handle); -} - -/* - * ======== PWM_stop ======== - */ -void PWM_stop(PWM_Handle handle) -{ - handle->fxnTablePtr->stopFxn(handle); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.h deleted file mode 100644 index 091141747ba..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.h +++ /dev/null @@ -1,594 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file PWM.h - * @brief PWM driver interface - * - * To use the PWM driver, ensure that the correct driver library for your - * device is linked in and include this header file as follows: - * @code - * #include - * @endcode - * - * This module serves as the main interface for applications. Its purpose - * is to redirect the PWM APIs to specific driver implementations - * which are specified using a pointer to a #PWM_FxnTable. - * - * # Overview # - * The PWM driver in TI-RTOS facilitates the generation of Pulse Width - * Modulated signals via simple and portable APIs. PWM instances must be - * opened by calling PWM_open() while passing in a PWM index and a parameters - * data structure. - * - * The driver APIs serve as an interface to a typical TI-RTOS application. - * The specific peripheral implementations are responsible for creating all OS - * specific primitives to allow for thread-safe operation. - * - * When a PWM instance is opened, the period, duty cycle and idle level are - * configured and the PWM is stopped (waveforms not generated until PWM_start() - * is called). The maximum period and duty supported is device dependent; - * refer to the implementation specific documentation for values. - * - * PWM outputs are active-high, meaning the duty will control the duration of - * high output on the pin (at 0% duty, the output is always low, at 100% duty, - * the output is always high). - * - * # Usage # - * - * @code - * PWM_Handle pwm; - * PWM_Params pwmParams; - * - * // Initialize the PWM driver. - * PWM_init(); - * - * // Initialize the PWM parameters - * PWM_Params_init(&pwmParams); - * pwmParams.idleLevel = PWM_IDLE_LOW; // Output low when PWM is not running - * pwmParams.periodUnits = PWM_PERIOD_HZ; // Period is in Hz - * pwmParams.periodValue = 1e6; // 1MHz - * pwmParams.dutyUnits = PWM_DUTY_FRACTION; // Duty is in fractional percentage - * pwmParams.dutyValue = 0; // 0% initial duty cycle - * - * // Open the PWM instance - * pwm = PWM_open(Board_PWM0, &pwmParams); - * - * if (pwm == NULL) { - * // PWM_open() failed - * while (1); - * } - * - * PWM_start(pwm); // start PWM with 0% duty cycle - * - * PWM_setDuty(pwm, - * (PWM_DUTY_FRACTION_MAX / 2)); // set duty cycle to 50% - * @endcode - * - * Details for the example code above are described in the following - * subsections. - * - * ### PWM Driver Configuration # - * - * In order to use the PWM APIs, the application is required - * to provide device-specific PWM configuration in the Board.c file. - * The PWM driver interface defines a configuration data structure: - * - * @code - * typedef struct PWM_Config_ { - * PWM_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } PWM_Config; - * @endcode - * - * The application must declare an array of PWM_Config elements, named - * PWM_config[]. Each element of PWM_config[] is populated with - * pointers to a device specific PWM driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as which pin will be driven, and which timer peripheral - * will be used. Each element in PWM_config[] corresponds to - * a PWM instance, and none of the elements should have NULL pointers. - * - * Additionally, the PWM driver interface defines a global integer variable - * 'PWM_count' which is initialized to the number of PWM instances the - * application has defined in the PWM_Config array. - * - * You will need to check the device-specific PWM driver implementation's - * header file for example configuration. Please also refer to the - * Board.c file of any of your examples to see the PWM configuration. - * - * ### Initializing the PWM Driver # - * - * PWM_init() must be called before any other PWM APIs. This function - * calls the device implementation's PWM initialization function, for each - * element of PWM_config[]. - * - * ### Opening the PWM Driver # - * - * Opening a PWM requires four steps: - * 1. Create and initialize a PWM_Params structure. - * 2. Fill in the desired parameters. - * 3. Call PWM_open(), passing the index of the PWM in the PWM_config - * structure, and the address of the PWM_Params structure. The - * PWM instance is specified by the index in the PWM_config structure. - * 4. Check that the PWM handle returned by PWM_open() is non-NULL, - * and save it. The handle will be used to read and write to the - * PWM you just opened. - * - * Only one PWM index can be used at a time; calling PWM_open() a second - * time with the same index previously passed to PWM_open() will result in - * an error. You can, though, re-use the index if the instance is closed - * via PWM_close(). - * In the example code, Board_PWM0 is passed to PWM_open(). This macro - * is defined in the example's Board.h file. - * - * ### Modes of Operation # - * - * A PWM instance can be configured to interpret the period as one of three - * units: - * - #PWM_PERIOD_US: The period is in microseconds. - * - #PWM_PERIOD_HZ: The period is in (reciprocal) Hertz. - * - #PWM_PERIOD_COUNTS: The period is in timer counts. - * - * A PWM instance can be configured to interpret the duty as one of three - * units: - * - #PWM_DUTY_US: The duty is in microseconds. - * - #PWM_DUTY_FRACTION: The duty is in a fractional part of the period - * where 0 is 0% and #PWM_DUTY_FRACTION_MAX is 100%. - * - #PWM_DUTY_COUNTS: The period is in timer counts and must be less than - * the period. - * - * The idle level parameter is used to set the output to high/low when the - * PWM is not running (stopped or not started). The idle level can be - * set to: - * - #PWM_IDLE_LOW - * - #PWM_IDLE_HIGH - * - * The default PWM configuration is to set a duty of 0% with a 1MHz frequency. - * The default period units are in PWM_PERIOD_HZ and the default duty units - * are in PWM_DUTY_FRACTION. Finally, the default output idle level is - * PWM_IDLE_LOW. It is the application's responsibility to set the duty for - * each PWM output used. - * - * ### Controlling the PWM Duty Cycle # - * - * Once the PWM instance has been opened and started, the primary API used - * by the application will be #PWM_setDuty() to control the duty cycle of a - * PWM pin: - * - * @code - * PWM_setDuty(pwm, PWM_DUTY_FRACTION_MAX / 2); // Set 50% duty cycle - * @endcode - * - * # Implementation # - * - * The PWM driver interface module is joined (at link time) to an - * array of PWM_Config data structures named *PWM_config*. - * PWM_config is implemented in the application with each entry being a - * PWM instance. Each entry in *PWM_config* contains a: - * - (PWM_FxnTable *) to a set of functions that implement a PWM peripheral - * - (void *) data object that is associated with the PWM_FxnTable - * - (void *) hardware attributes that are associated with the PWM_FxnTable - * - * The PWM APIs are redirected to the device specific implementations - * using the PWM_FxnTable pointer of the PWM_config entry. - * In order to use device specific functions of the PWM driver directly, - * link in the correct driver library for your device and include the - * device specific PWM driver header file (which in turn includes PWM.h). - * For example, for the MSP432 family of devices, you would include the - * following header file: - * @code - * #include - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_PWM__include -#define ti_drivers_PWM__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define PWM_DEFAULT_PERIOD_US 1 -#define PWM_DEFAULT_DUTY_PERCENT 0 - -/*! - * @brief Maximum duty (100%) when configuring duty cycle as a fraction of - * period. - */ -#define PWM_DUTY_FRACTION_MAX ((uint32_t) 100) - -/*! - * Common PWM_control command code reservation offset. - * PWM driver implementations should offset command codes with PWM_CMD_RESERVED - * growing positively. - * - * Example implementation specific command codes: - * @code - * #define PWMXYZ_COMMAND0 (PWM_CMD_RESERVED + 0) - * #define PWMXYZ_COMMAND1 (PWM_CMD_RESERVED + 1) - * @endcode - */ -#define PWM_CMD_RESERVED (32) - -/*! - * Common PWM_control status code reservation offset. - * PWM driver implementations should offset status codes with - * PWM_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define PWMXYZ_STATUS_ERROR0 (PWM_STATUS_RESERVED - 0) - * #define PWMXYZ_STATUS_ERROR1 (PWM_STATUS_RESERVED - 1) - * #define PWMXYZ_STATUS_ERROR2 (PWM_STATUS_RESERVED - 2) - * @endcode - */ -#define PWM_STATUS_RESERVED (-32) - -/*! - * @brief Success status code returned by: - * PWM_control(), PWM_setDuty(), PWM_setPeriod(). - * - * Functions return PWM_STATUS_SUCCESS if the call was executed - * successfully. - */ -#define PWM_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by PWM_control(). - * - * PWM_control() returns PWM_STATUS_ERROR if the control code was not executed - * successfully. - */ -#define PWM_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by PWM_control() for undefined - * command codes. - * - * PWM_control() returns PWM_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define PWM_STATUS_UNDEFINEDCMD (-2) - -/*! - * @brief An error status code returned by PWM_setPeriod(). - * - * PWM_setPeriod() returns PWM_STATUS_INVALID_PERIOD if the period argument is - * invalid for the current configuration. - */ -#define PWM_STATUS_INVALID_PERIOD (-3) - -/*! - * @brief An error status code returned by PWM_setDuty(). - * - * PWM_setDuty() returns PWM_STATUS_INVALID_DUTY if the duty cycle argument is - * invalid for the current configuration. - */ -#define PWM_STATUS_INVALID_DUTY (-4) - -/*! - * @brief PWM period unit definitions. Refer to device specific - * implementation if using PWM_PERIOD_COUNTS (raw PWM/Timer counts). - */ -typedef enum PWM_Period_Units_ { - PWM_PERIOD_US, /*!< Period in microseconds */ - PWM_PERIOD_HZ, /*!< Period in (reciprocal) Hertz - (for example 2MHz = 0.5us period) */ - PWM_PERIOD_COUNTS /*!< Period in timer counts */ -} PWM_Period_Units; - -/*! - * @brief PWM duty cycle unit definitions. Refer to device specific - * implementation if using PWM_DUTY_COUNTS (raw PWM/Timer counts). - */ -typedef enum PWM_Duty_Units_ { - PWM_DUTY_US, /*!< Duty cycle in microseconds */ - PWM_DUTY_FRACTION, /*!< Duty as a fractional part of PWM_DUTY_FRACTION_MAX */ - PWM_DUTY_COUNTS /*!< Duty in timer counts */ -} PWM_Duty_Units; - -/*! - * @brief Idle output level when PWM is not running (stopped / not started). - */ -typedef enum PWM_IdleLevel_ { - PWM_IDLE_LOW = 0, - PWM_IDLE_HIGH = 1, -} PWM_IdleLevel; - -/*! - * @brief PWM Parameters - * - * PWM Parameters are used to with the PWM_open() call. Default values for - * these parameters are set using PWM_Params_init(). - * - * @sa PWM_Params_init() - */ -typedef struct PWM_Params_ { - PWM_Period_Units periodUnits; /*!< Units in which the period is specified */ - uint32_t periodValue; /*!< PWM initial period */ - PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */ - uint32_t dutyValue; /*!< PWM initial duty */ - PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */ - void *custom; /*!< Custom argument used by driver - implementation */ -} PWM_Params; - -/*! - * @brief A handle that is returned from a PWM_open() call. - */ -typedef struct PWM_Config_ *PWM_Handle; - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_close(). - */ -typedef void (*PWM_CloseFxn) (PWM_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_control(). - */ -typedef int_fast16_t (*PWM_ControlFxn) (PWM_Handle handle, uint_fast16_t cmd, - void *arg); -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_init(). - */ -typedef void (*PWM_InitFxn) (PWM_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_open(). - */ -typedef PWM_Handle (*PWM_OpenFxn) (PWM_Handle handle, PWM_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_setDuty(). - */ -typedef int_fast16_t (*PWM_SetDutyFxn) (PWM_Handle handle, - uint32_t duty); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_setPeriod(). - */ -typedef int_fast16_t (*PWM_SetPeriodFxn) (PWM_Handle handle, - uint32_t period); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_start(). - */ -typedef void (*PWM_StartFxn) (PWM_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_stop(). - */ -typedef void (*PWM_StopFxn) (PWM_Handle handle); - -/*! - * @brief The definition of a PWM function table that contains the - * required set of functions to control a specific PWM driver - * implementation. - */ -typedef struct PWM_FxnTable_ { - /*! Function to close the specified instance */ - PWM_CloseFxn closeFxn; - /*! Function to driver implementation specific control function */ - PWM_ControlFxn controlFxn; - /*! Function to initialize the given data object */ - PWM_InitFxn initFxn; - /*! Function to open the specified instance */ - PWM_OpenFxn openFxn; - /*! Function to set the duty cycle for a specific instance */ - PWM_SetDutyFxn setDutyFxn; - /*! Function to set the period for a specific instance */ - PWM_SetPeriodFxn setPeriodFxn; - /*! Function to start the PWM output for a specific instance */ - PWM_StartFxn startFxn; - /*! Function to stop the PWM output for a specific instance */ - PWM_StopFxn stopFxn; -} PWM_FxnTable; - -/*! - * @brief PWM Global configuration. - * - * The PWM_Config structure contains a set of pointers used to characterize - * the PWM driver implementation. - * - */ -typedef struct PWM_Config_ { - /*! Pointer to a table of driver-specific implementations of PWM APIs */ - PWM_FxnTable const *fxnTablePtr; - /*! Pointer to a driver specific data object */ - void *object; - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} PWM_Config; - -/*! - * @brief Function to close a PWM instance specified by the PWM handle. - * - * @pre PWM_open() must have been called first. - * @pre PWM_stop() must have been called first if PWM was started. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @sa PWM_open() - * @sa PWM_start() - * @sa PWM_stop() - */ -extern void PWM_close(PWM_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * PWM_Handle. - * - * @pre PWM_open() must have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @param cmd A command value defined by the driver specific - * implementation. - * - * @param arg A pointer to an optional R/W (read/write) argument that - * is accompanied with cmd. - * - * @return A PWM_Status describing an error or success state. Negative values - * indicate an error occurred. - * - * @sa PWM_open() - */ -extern int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief This function initializes the PWM module. - * - * @pre The PWM_config structure must exist and be persistent before this - * function can be called. This function must be called before any - * other PWM driver APIs. This function does not modify any peripheral - * registers & should only be called once. - */ -extern void PWM_init(void); - -/*! - * @brief This function opens a given PWM instance and sets the period, - * duty and idle level to those specified in the params argument. - * - * @param index Logical instance number for the PWM indexed into - * the PWM_config table. - * - * @param params Pointer to an parameter structure. If NULL default - * values are used. - * - * @return A PWM_Handle if successful or NULL on an error or if it has been - * opened already. If NULL is returned further PWM API calls will - * result in undefined behavior. - * - * @sa PWM_close() - */ -extern PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params); - -/*! - * @brief Function to initialize the PWM_Params structure to default values. - * - * @param params A pointer to PWM_Params structure for initialization. - * - * Defaults values are: - * Period units: PWM_PERIOD_HZ - * Period: 1e6 (1MHz) - * Duty cycle units: PWM_DUTY_FRACTION - * Duty cycle: 0% - * Idle level: PWM_IDLE_LOW - */ -extern void PWM_Params_init(PWM_Params *params); - -/*! - * @brief Function to set the duty cycle of the specified PWM handle. PWM - * instances run in active high output mode; 0% is always low output, - * 100% is always high output. This API can be called while the PWM - * is running & duty must always be lower than or equal to the period. - * If an error occurs while calling the function the PWM duty cycle - * will remain unchanged. - * - * @pre PWM_open() must have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @param duty Duty cycle in the units specified by the params used - * in PWM_open(). - * - * @return A PWM status describing an error or success. Negative values - * indicate an error. - * - * @sa PWM_open() - */ -extern int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty); - -/*! - * @brief Function to set the period of the specified PWM handle. This API - * can be called while the PWM is running & the period must always be - * larger than the duty cycle. - * If an error occurs while calling the function the PWM period - * will remain unchanged. - * - * @pre PWM_open() must have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @param period Period in the units specified by the params used - * in PWM_open(). - * - * @return A PWM status describing an error or success state. Negative values - * indicate an error. - * - * @sa PWM_open() - */ -extern int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period); - -/*! - * @brief Function to start the specified PWM handle with current settings. - * - * @pre PWM_open() has to have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @sa PWM_open() - * @sa PWM_stop() - */ -extern void PWM_start(PWM_Handle handle); - -/*! - * @brief Function to stop the specified PWM handle. Output will set to the - * idle level specified by params in PWM_open(). - * - * @pre PWM_open() has to have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @sa PWM_open() - * @sa PWM_start() - */ -extern void PWM_stop(PWM_Handle handle); - -#ifdef __cplusplus -} -#endif -#endif /* ti_drivers_PWM__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Power.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Power.h deleted file mode 100755 index 38b96bcdaa9..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Power.h +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file Power.h - * - * @brief Power Manager interface - * - * The Power header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Operation # - * The Power Manager facilitates the transition of the MCU from active states - * to sleep states and vice versa. It provides other drivers the - * ability to set and release dependencies on hardware resources, and keeps - * reference counts on each resource to know when to enable or disable the - * resource. It provides drivers the ability to register callback functions - * to be invoked upon specific power events. In addition, drivers and - * applications can set or release constraints to prevent the MCU from - * transitioning into specific active or sleep states. - * - * The Power Manager APIs and configuration parameters are described here. - * For a detailed description of terms and concepts, and usage by different - * types of software components (peripheral drivers, power policies, - * and applications) please see the - * SimpleLink SDK Power Management User's Guide. - * - * ============================================================================ - */ - -#ifndef ti_drivers_Power__include -#define ti_drivers_Power__include - -#include -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Power latency types */ -#define Power_TOTAL (1U) /*!< total latency */ -#define Power_RESUME (2U) /*!< resume latency */ - -/* Power notify responses */ -#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ -#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ - -/* Power status */ -#define Power_SOK (0) /*!< OK, operation succeeded */ -#define Power_EFAIL (-1) /*!< general failure */ -#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ -#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ -#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ -#define Power_EBUSY (-5) /*!< busy with another transition */ - -/* Power transition states */ -#define Power_ACTIVE (1U) /*!< normal active state */ -#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ -#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ -#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ -#define Power_CHANGING_PERF_LEVEL (5U) /*!< moving to new performance level */ - - -/*! - * @brief Power policy initialization function pointer - */ -typedef void (*Power_PolicyInitFxn)(void); - -/*! - * @brief Power policy function pointer - */ -typedef void (*Power_PolicyFxn)(void); - -/*! - * @brief Power notify function pointer - */ -typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType, - uintptr_t eventArg, uintptr_t clientArg); - -/*! - * @brief Power notify object structure. - * - * This struct specification is for internal use. Notification clients must - * pre-allocate a notify object when registering for a notification; - * Power_registerNotify() will take care initializing the internal elements - * appropriately. - */ -typedef struct Power_NotifyObj_ { - List_Elem link; /*!< for placing on the notify list */ - uint_fast16_t eventTypes; /*!< the event type */ - Power_NotifyFxn notifyFxn; /*!< notification function */ - uintptr_t clientArg; /*!< argument provided by client */ -} Power_NotifyObj; - -/*! - * @brief Disable the configured power policy from running when the CPU is - * idle - * - * Calling this function clears the flag that controls whether the configured - * power policy function is invoked on each pass through the Idle loop. - * This function call will override both a 'true' setting of the - * "enablePolicy" setting in the Power Manager configuration object, as well - * as a previous runtime call to the Power_enablePolicy() function. - * - * @return The old value of "enablePolicy". - * - * @sa Power_enablePolicy - */ -bool Power_disablePolicy(void); - -/*! - * @brief Enable the configured power policy to run when the CPU is idle - * - * Calling this function sets a flag that will cause the configured power - * policy function to be invoked on each pass through the Idle loop. This - * function call will override both a 'false' setting of the "enablePolicy" - * setting in the Power Manager configuration object, as well as a previous - * runtime call to the Power_disablePolicy() function. - * - * For some processor families, automatic power transitions can make initial - * application development more difficult, as well as being at odds with - * basic debugger operation. This convenience function allows an application - * to be initially configured, built, and debugged, without automatic power - * transitions during idle time. When the application is found to be working, - * this function can be called (typically in main()) to enable the policy - * to run, without having to change the application configuration. - * - * @sa Power_disablePolicy - */ -void Power_enablePolicy(void); - -/*! - * @brief Get the constraints that have been declared with Power - * - * This function returns a bitmask indicating the constraints that are - * currently declared to the Power Manager (via previous calls to - * Power_setConstraint()). For each constraint that is currently declared, - * the corresponding bit in the bitmask will be set. For example, if two - * clients have independently declared two different constraints, the returned - * bitmask will have two bits set. - * - * Constraint identifiers are device specific, and defined in the - * device-specific Power include file. For example, the constraints for - * MSP432 are defined in PowerMSP432.h. The corresponding bit in the - * bitmask returned by this function can be derived by a left-shift using - * the constraint identifier. For example, for MSP432, for the corresponding - * bit for the PowerMSP432_DISALLOW_SLEEP constraint, the bit position is - * determined by the operation: (1 << PowerMSP432_DISALLOW_SLEEP) - * - * @return A bitmask of the currently declared constraints. - * - * @sa Power_setConstraint - */ -uint_fast32_t Power_getConstraintMask(void); - -/*! - * @brief Get the current dependency count for a resource - * - * This function returns the number of dependencies that are currently - * declared upon a resource. - * - * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. - * - * @param resourceId resource id - * - * @return The number of dependencies declared for the resource. - * Power_EINVALIDINPUT if the resourceId is invalid. - * - * @sa Power_setDependency - */ -int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId); - -/*! - * @brief Get the current performance level - * - * This function returns the current device performance level in effect. - * - * If performance scaling is not supported for the device, this function - * will always indicate a performance level of zero. - * - * @return The current performance level. - * - * @sa Power_setPerformanceLevel - */ -uint_fast16_t Power_getPerformanceLevel(void); - -/*! - * @brief Get the hardware transition latency for a sleep state - * - * This function reports the minimal hardware transition latency for a specific - * sleep state. The reported latency is that for a direct transition, and does - * not include any additional latency that might occur due to software-based - * notifications. - * - * Sleep states are device specific, and defined in the device-specific Power - * include file. For example, the sleep states for CC32XX are defined in - * PowerCC32XX.h. - * - * This function is typically called by the power policy function. The latency - * is reported in units of microseconds. - * - * @param sleepState the sleep state - * - * @param type the latency type (Power_TOTAL or Power_RESUME) - * - * @return The latency value, in units of microseconds. - */ -uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, - uint_fast16_t type); - -/*! - * @brief Get the current transition state of the Power Manager - * - * This function returns the current transition state for the Power Manager. - * For example, when no transitions are in progress, a status of Power_ACTIVE - * is returned. Power_ENTERING_SLEEP is returned during the transition to - * sleep, before sleep has occurred. Power_EXITING_SLEEP is returned - * after wakeup, as the device is being transitioned back to Power_ACTIVE. - * And Power_CHANGING_PERF_LEVEL is returned when a change is being made - * to the performance level. - * - * @return The current Power Manager transition state. - */ -uint_fast16_t Power_getTransitionState(void); - -/*! - * @brief Power function to be added to the application idle loop - * - * This function should be added to the application idle loop. (The method to - * do this depends upon the operating system being used.) This function - * will invoke the configured power policy function when appropriate. The - * specific policy function to be invoked is configured as the 'policyFxn' - * in the application-defined Power configuration object. - * - */ -void Power_idleFunc(void); - -/*! - * @brief Power initialization function - * - * This function initializes Power Manager internal state. It must be called - * prior to any other Power API. This function is normally called as part - * of TI-RTOS board initialization, for example, from within the - * \_initGeneral() function. - * - * @return Power_SOK - */ -int_fast16_t Power_init(void); - -/*! - * @brief Register a function to be called upon a specific power event - * - * This function registers a function to be called when a Power event occurs. - * Registrations and the corresponding notifications are processed in - * first-in-first-out (FIFO) order. The function registered must behave as - * described later, below. - * - * The pNotifyObj parameter is a pointer to a pre-allocated, opaque object - * that will be used by Power to support the notification. This object could - * be dynamically allocated, or declared as a global object. This function - * will properly initialized the object's fields as appropriate; the caller - * just needs to provide a pointer to this pre-existing object. - * - * The eventTypes parameter identifies the type of power event(s) for which - * the notify function being registered is to be called. (Event identifiers are - * device specific, and defined in the device-specific Power include file. - * For example, the events for MSP432 are defined in PowerMSP432.h.) The - * eventTypes parameter for this function call is treated as a bitmask, so - * multiple event types can be registered at once, using a common callback - * function. For example, to call the specified notifyFxn when both - * the entering deepsleep and awake from deepsleep events occur, eventTypes - * should be specified as: PowerMSP432_ENTERING_DEEPSLEEP | - * PowerMSP432_AWAKE_DEEPSLEEP - * - * The notifyFxn parameter specifies a callback function to be called when the - * specified Power event occurs. The notifyFxn must implement the following - * signature: - * status = notifyFxn(eventType, eventArg, clientArg); - * - * Where: eventType identifies the event being signalled, eventArg is an - * optional event-specific argument, and clientArg is an abitrary argument - * specified by the client at registration. Note that multipe types of events - * can be specified when registering the notification callback function, - * but when the callback function is actually called by Power, only a - * single eventType will be specified for the callback (i.e., the current - * event). The status returned by the client notification function must - * be one of the following constants: Power_NOTIFYDONE if the client processed - * the notification successfully, or Power_NOTIFYERROR if an error occurred - * during notification. - * - * The clientArg parameter is an arbitrary, client-defined argument to be - * passed back to the client upon notification. This argument may allow one - * notify function to be used by multiple instances of a driver (that is, the - * clientArg can be used to identify the instance of the driver that is being - * notified). - * - * @param pNotifyObj notification object (preallocated by caller) - * - * @param eventTypes event type or types - * - * @param notifyFxn client's callback function - * - * @param clientArg client-specified argument to pass with notification - * - * @return Power_SOK on success. - * Power_EINVALIDPOINTER if either pNotifyObj or notifyFxn are NULL. - * - * @sa Power_unregisterNotify - */ -int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, - uint_fast16_t eventTypes, - Power_NotifyFxn notifyFxn, - uintptr_t clientArg); - -/*! - * @brief Release a previously declared constraint - * - * This function releases a constraint that was previously declared with - * Power_setConstraint(). For example, if a device driver is starting an I/O - * transaction and wants to prohibit activation of a sleep state during the - * transaction, it uses Power_setConstraint() to declare the constraint, - * before starting the transaction. When the transaction completes, the - * driver calls this function to release the constraint, to allow the Power - * manager to once again allow transitions to sleep. - * - * Constraint identifiers are device specific, and defined in the - * device-specific Power include file. For example, the constraints for - * MSP432 are defined in PowerMSP432.h. - * - * Only one constraint can be specified with each call to this function; to - * release multiple constraints this function must be called multiple times. - * - * It is critical that clients call Power_releaseConstraint() when operational - * constraints no longer exists. Otherwise, Power may be left unnecessarily - * restricted from activating power savings. - * - * @param constraintId constraint id - * - * @return CC26XX/CC13XX only: Power_SOK. To minimize code size - * asserts are used internally to check that the constraintId is valid, - * and that the constraint count is not already zero; - * the function always returns Power_SOK. - * - * @return All other devices: Power_SOK on success, - * Power_EINVALIDINPUT if the constraintId is invalid, and Power_EFAIL - * if the constraint count is already zero. - * - * @sa Power_setConstraint - */ -int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId); - -/*! - * @brief Release a previously declared dependency - * - * This function releases a dependency that had been previously declared upon - * a resource (by a call to Power_setDependency()). - * - * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. - * - * @param resourceId resource id - * - * @return CC26XX/CC13XX only: Power_SOK. To minimize code size - * asserts are used internally to check that the resourceId is valid, - * and that the resource reference count is not already zero; - * the function always returns Power_SOK. - * - * @return All other devices: Power_SOK on success, - * Power_EINVALIDINPUT if the resourceId is invalid, and Power_EFAIL - * if the resource reference count is already zero. - * - * @sa Power_setDependency - */ -int_fast16_t Power_releaseDependency(uint_fast16_t resourceId); - -/*! - * @brief Declare an operational constraint - * - * Before taking certain actions, the Power Manager checks to see if the - * requested action would conflict with a client-declared constraint. If the - * action does conflict, Power will not proceed with the request. This is the - * function that allows clients to declare their constraints with Power. - * - * Constraint identifiers are device specific, and defined in the - * device-specific Power include file. For example, the constraints for - * MSP432 are defined in PowerMSP432.h. - * - * Only one constraint can be specified with each call to this function; to - * declare multiple constraints this function must be called multiple times. - * - * @param constraintId constraint id - * - * @return CC26XX/CC13XX only: Power_SOK. To minimize code size an - * assert is used internally to check that the constraintId is valid; - * the function always returns Power_SOK. - * - * @return All other devices: Power_SOK on success, - * Power_EINVALIDINPUT if the constraintId is invalid. - * - * @sa Power_releaseConstraint - */ -int_fast16_t Power_setConstraint(uint_fast16_t constraintId); - -/*! - * @brief Declare a dependency upon a resource - * - * This function declares a dependency upon a resource. For example, if a - * UART driver needs a specific UART peripheral, it uses this function to - * declare this to the Power Manager. If the resource had been inactive, - * then Power will activate the peripheral during this function call. - * - * What is needed to make a peripheral resource 'active' will vary by device - * family. For some devices this may be a simple enable of a clock to the - * specified peripheral. For others it may also require a power on of a - * power domain. In either case, the Power Manager will take care of these - * details, and will also implement reference counting for resources and their - * interdependencies. For example, if multiple UART peripherals reside in - * a shared serial power domain, the Power Manager will power up the serial - * domain when it is first needed, and then automatically power the domain off - * later, when all related dependencies for the relevant peripherals are - * released. - * - * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. - * - * @param resourceId resource id - * - * @return CC26XX/CC13XX only: Power_SOK. To minimize code size an - * assert is used internally to check that the resourceId is valid; - * the function always returns Power_SOK. - * - * @return All other devices: Power_SOK on success, - * Power_EINVALIDINPUT if the reseourceId is invalid. - * - * @sa Power_releaseDependency - */ -int_fast16_t Power_setDependency(uint_fast16_t resourceId); - -/*! - * @brief Set the MCU performance level - * - * This function manages a transition to a new device performance level. - * Before the actual transition is initiated, notifications will be sent to - * any clients who've registered (with Power_registerNotify()) for a - * 'start change performance level' notification. The event name is device - * specific, and defined in the device-specific Power include file. For - * example, for MSP432, the event is "PowerMSP432_START_CHANGE_PERF_LEVEL", - * which is defined in PowerMSP432.h. Once notifications have been completed, - * the change to the performance level is initiated. After the level change - * is completed, there is a comparable event that can be used to signal a - * client that the change has completed. For example, on MSP432 the - * "PowerMSP432_DONE_CHANGE_PERF_LEVEL" event can be used to signal - * completion. - * - * This function will not return until the new performance level is in effect. - * If performance scaling is not supported for the device, or is prohibited - * by an active constraint, or if the specified level is invalid, then an - * error status will be returned. - * - * @param level the new performance level - * - * @return Power_SOK on success. - * Power_EINVALIDINPUT if the specified performance level is out of - * range of valid levels. - * Power_EBUSY if another transition is already in progress, or if - * a single constraint is set to prohibit any change to the - * performance level. - * Power_ECHANGE_NOT_ALLOWED if a level-specific constraint prohibits - * a change to the requested level. - * Power_EFAIL if performance scaling is not supported, if an - * error occurred during initialization, or if an error occurred - * during client notifications. - * - * @sa Power_getPerformanceLevel - */ -int_fast16_t Power_setPerformanceLevel(uint_fast16_t level); - -/*! - * @brief Set a new Power policy - * - * This function allows a new Power policy function to be selected at runtime. - * - * @param policy the new Power policy function - */ -void Power_setPolicy(Power_PolicyFxn policy); - -/*! - * @brief Put the device into a shutdown state - * - * This function will transition the device into a shutdown state. - * Before the actual transition is initiated, notifications will be sent to - * any clients who've registered (with Power_registerNotify()) for an - * 'entering shutdown' event. The event name is device specific, and defined - * in the device-specific Power include file. For example, for CC32XX, the - * event is "PowerCC32XX_ENTERING_SHUTDOWN", which is defined in - * PowerCC32XX.h. Once notifications have been completed, the device shutdown - * will commence. - * - * If the device is successfully transitioned to shutdown, this function - * call will never return. Upon wakeup, the device and application will - * be rebooted (through a device reset). If the transition is not - * successful, one of the error codes listed below will be returned. - * - * On some devices a timed wakeup from shutdown can be specified, using - * the shutdownTime parameter. This enables an autonomous application reboot - * at a future time. For example, an application can go to shutdown, and then - * automatically reboot at a future time to do some work. And once that work - * is done, the application can shutdown again, for another timed interval. - * The time interval is specified via the shutdownTime parameter. (On devices - * that do not support this feature, any value specified for shutdownTime will - * be ignored.) If the specified shutdownTime is less than the total - * shutdown latency for the device, then shutdownTime will be ignored. The - * shutdown latency for the device can be found in the device-specific Power - * include file. For example, for the CC32XX, this latency is defined in - * PowerCC32XX.h, as "PowerCC32XX_TOTALTIMESHUTDOWN".) - * - * @param shutdownState the device-specific shutdown state - * - * @param shutdownTime the amount of time (in milliseconds) to keep the - * the device in the shutdown state; this parameter - * is not supported on all device families - * - * @return Power_ECHANGE_NOT_ALLOWED if a constraint is prohibiting shutdown. - * Power_EFAIL if an error occurred during client notifications. - * Power_EINVALIDINPUT if the shutdownState is invalid. - * Power_EBUSY if another transition is already in progress. - */ -int_fast16_t Power_shutdown(uint_fast16_t shutdownState, - uint_fast32_t shutdownTime); - -/*! - * @brief Transition the device into a sleep state - * - * This function is called from the power policy when it has made a decision - * to put the device in a specific sleep state. This function returns to the - * caller (the policy function) once the device has awoken from sleep. - * - * This function must be called with interrupts disabled, and should not be - * called directly by the application, or by any drivers. - * This function does not check declared constraints; the policy function - * must check constraints before calling this function to initiate sleep. - * - * @param sleepState the sleep state - * - * @return Power_SOK on success, the device has slept and is awake again. - * Power_EFAIL if an error occurred during client notifications, or - * if a general failure occurred. - * Power_EINVALIDINPUT if the sleepState is invalid. - * Power_EBUSY if another transition is already in progress. - */ -int_fast16_t Power_sleep(uint_fast16_t sleepState); - -/*! - * @brief Unregister previously registered notifications - * - * This function unregisters for event notifications that were previously - * registered with Power_registerNotify(). The caller must specify a pointer - * to the same notification object used during registration. - * - * @param pNotifyObj notify object - * - * @sa Power_registerNotify - */ -void Power_unregisterNotify(Power_NotifyObj *pNotifyObj); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_Power__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Timer.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Timer.h deleted file mode 100644 index a35edae0f38..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Timer.h +++ /dev/null @@ -1,549 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file Timer.h - * @brief Timer driver interface - * - * The timer header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Overview # - * The timer driver serves as the main interface for a typical RTOS - * application. Its purpose is to redirect the timer APIs to device specific - * implementations which are specified using a pointer to a #Timer_FxnTable. - * The device specific implementations are responsible for creating all the - * RTOS specific primitives to allow for thead-safe operation. This driver - * does not have PWM or capture functionalities. These functionalities are - * addressed in both the capture and PWM driver. - * - * The timer driver also handles the general purpose timer resource allocation. - * For each driver that requires use of a general purpose timer, it calls - * Timer_open() to occupy the specified timer, and calls Timer_close() to - * release the occupied timer resource. - * - * # Usage # - * The following example code opens a timer in continuous callback mode. The - * period is set to 1000 Hz. - * - * @code - * Timer_Handle handle; - * Timer_Params params; - * - * Timer_Params_init(¶ms); - * params.periodUnits = Timer_PERIOD_HZ; - * params.period = 1000; - * params.timerMode = Timer_CONTINUOUS_CALLBACK; - * params.timerCallback = UserCallbackFunction; - * - * handle = Timer_open(Board_TIMER0, ¶ms); - * - * if (handle == NULL) { - * // Timer_open() failed - * while (1); - * } - * - * status = Timer_start(handle); - * - * if (status == Timer_STATUS_ERROR) { - * //Timer_start() failed - * while (1); - * } - * - * sleep(10000); - * - * Timer_stop(handle); - * @endcode - * - * ### Timer Driver Configuration # - * - * In order to use the timer APIs, the application is required to provide - * device specific timer configuration in the Board.c file. The timer driver - * interface defines a configuration data structure: - * - * @code - * typedef struct Timer_Config_ { - * Timer_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } Timer_Config; - * @endcode - * - * The application must declare an array of Timer_Config elements, named - * Timer_config[]. Each element of Timer_config[] are populated with - * pointers to a device specific timer driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the timer peripheral's base address, interrupt - * number and interrupt priority. Each element in Timer_config[] corresponds - * to a timer instance, and none of the elements should have NULL pointers. - * There is no correlation between the index and the peripheral designation - * (such as TIMER0 or TIMER1). For example, it is possible to use - * Timer_config[0] for TIMER1. - * - * You will need to check the device specific timer driver implementation's - * header file for example configuration. - * - * ### Initializing the Timer Driver # - * - * Timer_init() must be called before any other timer APIs. This function - * calls the device implementation's timer initialization function, for each - * element of Timer_config[]. - * - * ### Modes of Operation # - * - * The timer driver supports four modes of operation which may be specified in - * the Timer_Params. The device specific implementation may configure the timer - * peripheral as an up or down counter. In any case, Timer_getCount() will - * return a value characteristic of an up counter. - * - * #Timer_ONESHOT_CALLBACK is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. When the timer interrupt - * is triggered, the specified callback function will be called. The timer - * will not generate another interrupt unless Timer_start() is called again. - * Calling Timer_stop() or Timer_close() after Timer_start() but, before the - * timer interrupt, will prevent the specified callback from ever being - * invoked. - * - * #Timer_ONESHOT_BLOCKING is a blocking call. A semaphore is used to block - * the calling thread's execution until the timer generates an interrupt. If - * Timer_stop() is called, the calling thread will become unblocked - * immediately. The behavior of the timer in this mode is similar to a sleep - * function. - * - * #Timer_CONTINUOUS_CALLBACK is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. When the timer interrupt is - * treiggered, the specified callback function will be called. The timer is - * automatically restarted and will continue to periodically generate - * interrupts until Timer_stop() is called. - * - * #Timer_FREE_RUNNING is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. The timer will not - * generate an interrupt in this mode. The timer hardware will run until - * Timer_stop() is called. - * - * # Implementation # - * - * The timer driver interface module is joined (at link time) to an - * array of Timer_Config data structures named *Timer_config*. - * Timer_config is implemented in the application with each entry being an - * instance of a timer peripheral. Each entry in *Timer_config* contains a: - * - (Timer_FxnTable *) to a set of functions that implement a timer peripheral - * - (void *) data object that is associated with the Timer_FxnTable - * - (void *) hardware attributes that are associated with the Timer_FxnTable - * - * The timer APIs are redirected to the device specific implementations - * using the Timer_FxnTable pointer of the Timer_config entry. - * In order to use device specific functions of the timer driver directly, - * link in the correct driver library for your device and include the - * device specific timer driver header file (which in turn includes Timer.h). - * For example, for the MSP432 family of devices, you would include the - * following header file: - * - * @code - * #include - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_Timer__include -#define ti_drivers_Timer__include - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include - -/*! - * Common Timer_control command code reservation offset. - * Timer driver implementations should offset command codes with Timer_CMD_RESERVED - * growing positively - * - * Example implementation specific command codes: - * @code - * #define TimerXYZ_CMD_COMMAND0 Timer_CMD_RESERVED + 0 - * #define TimerXYZ_CMD_COMMAND1 Timer_CMD_RESERVED + 1 - * @endcode - */ -#define Timer_CMD_RESERVED (32) - -/*! - * Common Timer_control status code reservation offset. - * Timer driver implementations should offset status codes with - * Timer_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define TimerXYZ_STATUS_ERROR0 Timer_STATUS_RESERVED - 0 - * #define TimerXYZ_STATUS_ERROR1 Timer_STATUS_RESERVED - 1 - * @endcode - */ -#define Timer_STATUS_RESERVED (-32) - -/*! - * @brief Successful status code. - */ -#define Timer_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code. - */ -#define Timer_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by Timer_control() for undefined - * command codes. - * - * Timer_control() returns Timer_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define Timer_STATUS_UNDEFINEDCMD (-2) - -/*! - * @brief A handle that is returned from a Timer_open() call. - */ -typedef struct Timer_Config_ *Timer_Handle; - -/*! - * @brief Timer mode settings - * - * This enum defines the timer modes that may be specified in #Timer_Params. - */ -typedef enum Timer_Mode_ { - Timer_ONESHOT_CALLBACK, /*!< User routine doesn't get blocked and - user-specified callback function is - invoked once the timer interrupt happens - for only one time */ - Timer_ONESHOT_BLOCKING, /*!< User routine gets blocked until timer - interrupt happens for only one time. */ - Timer_CONTINUOUS_CALLBACK, /*!< User routine doesn't get blocked and - user-specified callback function is - invoked with every timer interrupt. */ - Timer_FREE_RUNNING -} Timer_Mode; - -/*! - * @brief Timer period unit enum - * - * This enum defines the units that may be specified for the period - * in #Timer_Params. This unit has no effect with Timer_getCounts. - */ -typedef enum Timer_PeriodUnits_ { - Timer_PERIOD_US, /*!< Period specified in micro seconds. */ - Timer_PERIOD_HZ, /*!< Period specified in hertz; interrupts per - second. */ - Timer_PERIOD_COUNTS /*!< Period specified in ticks or counts. Varies - from board to board. */ -} Timer_PeriodUnits; - -/*! - * @brief Timer callback function - * - * User definable callback function prototype. The timer driver will call the - * defined function and pass in the timer driver's handle and the pointer to the - * user-specified the argument. - * - * @param handle Timer_Handle - */ -typedef void (*Timer_CallBackFxn)(Timer_Handle handle); - -/*! - * @brief Timer Parameters - * - * Timer parameters are used to with the Timer_open() call. Default values for - * these parameters are set using Timer_Params_init(). - * - */ -typedef struct Timer_Params_ { - /*! Mode to be used by the timer driver. */ - Timer_Mode timerMode; - - /*! Units used to specify the period. */ - Timer_PeriodUnits periodUnits; - - /*! Callback function called when timerMode is Timer_ONESHOT_CALLBACK or - Timer_CONTINUOUS_CALLBACK. */ - Timer_CallBackFxn timerCallback; - - /*! Period in units of periodUnits. */ - uint32_t period; -} Timer_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_control(). - */ -typedef int_fast16_t (*Timer_ControlFxn)(Timer_Handle handle, - uint_fast16_t cmd, void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_close(). - */ -typedef void (*Timer_CloseFxn)(Timer_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_getCount(). - */ -typedef uint32_t (*Timer_GetCountFxn)(Timer_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_init(). - */ -typedef void (*Timer_InitFxn)(Timer_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_open(). - */ -typedef Timer_Handle (*Timer_OpenFxn)(Timer_Handle handle, - Timer_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_start(). - */ -typedef int32_t (*Timer_StartFxn)(Timer_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_stop(). - */ -typedef void (*Timer_StopFxn)(Timer_Handle handle); - -/*! - * @brief The definition of a timer function table that contains the - * required set of functions to control a specific timer driver - * implementation. - */ -typedef struct Timer_FxnTable_ { - /*! Function to close the specified peripheral. */ - Timer_CloseFxn closeFxn; - - /*! Function to implementation specific control function. */ - Timer_ControlFxn controlFxn; - - /*! Function to get the count of the specified peripheral. */ - Timer_GetCountFxn getCountFxn; - - /*! Function to initialize the given data object. */ - Timer_InitFxn initFxn; - - /*! Function to open the specified peripheral. */ - Timer_OpenFxn openFxn; - - /*! Function to start the specified peripheral. */ - Timer_StartFxn startFxn; - - /*! Function to stop the specified peripheral. */ - Timer_StopFxn stopFxn; -} Timer_FxnTable; - -/*! - * @brief Timer Global configuration - * - * The Timer_Config structure contains a set of pointers used to characterize - * the timer driver implementation. - * - * This structure needs to be defined before calling Timer_init() and it must - * not be changed thereafter. - * - * @sa Timer_init() - */ -typedef struct Timer_Config_ { - /*! Pointer to a table of driver-specific implementations of timer APIs. */ - Timer_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object. */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure. */ - void const *hwAttrs; -} Timer_Config; - -/*! - * @brief Function to close a timer. The corresponding timer to the - * Timer_Handle becomes an available timer resource. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @sa Timer_open() - */ -extern void Timer_close(Timer_Handle handle); - -/*! - * @brief Function performs device specific features on a given - * Timer_Handle. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @param cmd A command value defined by the driver specific - * implementation. - * - * @param arg A pointer to an optional R/W (read/write) argument that - * is accompanied with cmd. - * - * @return A Timer_Status describing an error or success state. Negative values - * indicate an error occurred. - * - * @sa Timer_open() - */ -extern int_fast16_t Timer_control(Timer_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief Function to get the current count of a timer. The value returned - * represents timer counts. The value returned is always - * characteristic of an up counter. This is true even if the timer - * peripheral is counting down. Some device specific implementations - * may employ a prescaler in addition to this timer count. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @sa Timer_open() - * - * @return The current count of the timer in timer ticks. - * - */ -extern uint32_t Timer_getCount(Timer_Handle handle); - - -/*! - * @brief Function to initialize a timer module. This function will go through - * all available hardware resources and mark them as "available". - * - * @pre The Timer_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other timer driver APIs. - * - * @sa Timer_open() - */ -extern void Timer_init(void); - -/*! - * @brief Function to initialize a given timer peripheral specified by the - * index argument. The Timer_Params specifies which mode the timer - * will operate. The accuracy of the desired period is limited by the - * the clock. For example, a 100 MHz clock will have a tick resolution - * of 10 nanoseconds. This function takes care of timer resource - * allocation. If the particular timer is available to use, the timer - * driver owns it and returns a Timer_Handle. - * - * @pre Timer_init() has been called. - * - * @param index Logical peripheral number for the timer indexed into - * the Timer_config table. - * - * @param params Pointer to an parameter block, if NULL it will use - * default values. - * - * @return A Timer_Handle upon success or NULL. If the desired period results - * in overflow, or saturation, of the timer, NULL is returned. If the - * timer resource is already in use, NULL is returned. - * - * @sa Timer_init() - * @sa Timer_close() - */ -extern Timer_Handle Timer_open(uint_least8_t index, Timer_Params *params); - -/*! - * @brief Function to initialize the Timer_Params struct to its defaults. - * - * @param params A pointer to Timer_Params structure for - * initialization. - * - * Defaults values are: - * timerMode = Timer_ONESHOT_BLOCKING - * periodUnit = Timer_PERIOD_COUNTS - * timerCallback = NULL - * period = (uint16_t) ~0 - */ -extern void Timer_Params_init(Timer_Params *params); - -/*! - * @brief Function to start the timer. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @return Timer_STATUS_SUCCESS or Timer_STATUS_ERROR. - * - * @sa Timer_stop() - */ -extern int32_t Timer_start(Timer_Handle handle); - -/*! - * @brief Function to stop timer. If the timer is already stopped, this - * function has no effect. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @sa Timer_start() - */ -extern void Timer_stop(Timer_Handle handle); - -/* The following are included for backwards compatibility. These should not be - * used by the application. - */ -#define TIMER_CMD_RESERVED Timer_CMD_RESERVED -#define TIMER_STATUS_RESERVED Timer_STATUS_RESERVED -#define TIMER_STATUS_SUCCESS Timer_STATUS_SUCCESS -#define TIMER_STATUS_ERROR Timer_STATUS_ERROR -#define TIMER_STATUS_UNDEFINEDCMD Timer_STATUS_UNDEFINEDCMD -#define TIMER_ONESHOT_CB Timer_ONESHOT_CALLBACK -#define TIMER_ONESHOT_BLOCK Timer_ONESHOT_BLOCKING -#define TIMER_CONTINUOUS_CB Timer_CONTINUOUS_CALLBACK -#define TIMER_MODE_FREE_RUNNING Timer_FREE_RUNNING -#define TIMER_PERIOD_US Timer_PERIOD_US -#define TIMER_PERIOD_HZ Timer_PERIOD_HZ -#define TIMER_PERIOD_COUNTS Timer_PERIOD_COUNTS -#define Timer_Period_Units Timer_PeriodUnits - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_Timer__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.c deleted file mode 100755 index 66f5cd82a0c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -extern const UDMACC32XX_Config UDMACC32XX_config[]; - -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); - -static bool dmaInitialized = false; -static Power_NotifyObj postNotifyObj; /* LPDS wake-up notify object */ - -/* Reference count for open calls */ -static uint32_t refCount = 0; - -/* - * ======== UDMACC32XX_close ======== - */ -void UDMACC32XX_close(UDMACC32XX_Handle handle) -{ - UDMACC32XX_Object *object = handle->object; - uintptr_t key; - - Power_releaseDependency(PowerCC32XX_PERIPH_UDMA); - - key = HwiP_disable(); - - refCount--; - - if (refCount == 0) { - Power_unregisterNotify(&postNotifyObj); - object->isOpen = false; - } - - HwiP_restore(key); -} - -/* - * ======== UDMACC32XX_init ======== - */ -void UDMACC32XX_init() -{ - HwiP_Params hwiParams; - UDMACC32XX_Handle handle = (UDMACC32XX_Handle)&(UDMACC32XX_config[0]); - UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - UDMACC32XX_Object *object = handle->object; - - if (!dmaInitialized) { - object->isOpen = false; - - HwiP_Params_init(&hwiParams); - hwiParams.priority = hwAttrs->intPriority; - - /* Will check in UDMACC32XX_open() if this failed */ - object->hwiHandle = HwiP_create(hwAttrs->intNum, hwAttrs->dmaErrorFxn, - &hwiParams); - if (object->hwiHandle == NULL) { - DebugP_log0("Failed to create uDMA error Hwi!!\n"); - } - else { - dmaInitialized = true; - } - } -} - -/* - * ======== UDMACC32XX_open ======== - */ -UDMACC32XX_Handle UDMACC32XX_open() -{ - UDMACC32XX_Handle handle = (UDMACC32XX_Handle)&(UDMACC32XX_config); - UDMACC32XX_Object *object = handle->object; - UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - uintptr_t key; - - if (!dmaInitialized) { - return (NULL); - } - - Power_setDependency(PowerCC32XX_PERIPH_UDMA); - - key = HwiP_disable(); - - /* - * If the UDMA has not been opened yet, create the error Hwi - * and initialize the control table base address. - */ - if (object->isOpen == false) { - MAP_PRCMPeripheralReset(PRCM_UDMA); - - MAP_uDMAEnable(); - MAP_uDMAControlBaseSet(hwAttrs->controlBaseAddr); - - Power_registerNotify(&postNotifyObj, PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t)handle); - - object->isOpen = true; - } - - refCount++; - - HwiP_restore(key); - - return (handle); -} - -/* - * ======== postNotifyFxn ======== - * Called by Power module when waking up from LPDS. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - UDMACC32XX_Handle handle = (UDMACC32XX_Handle)clientArg; - UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - - MAP_uDMAEnable(); - MAP_uDMAControlBaseSet(hwAttrs->controlBaseAddr); - - return (Power_NOTIFYDONE); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.h deleted file mode 100755 index d57f9b28cfd..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file UDMACC32XX.h - * - * @brief uDMA driver implementation for CC32XX. - * - * This driver is intended for use only by TI-RTOS drivers that use the uDMA - * peripheral (e.g., SPI and I2S). This driver is mainly used for Power - * management of the UDMA peripheral. - * - * The application should only define the memory for the control table and - * set up the UDMACC32XX_HWAttrs and UDMACC32XX_Config structures. - * - * The UDMACC32XX header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_dma_UDMACC32XX__include -#define ti_drivers_dma_UDMACC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief UDMA error function pointer - */ -typedef void (*UDMACC32XX_ErrorFxn)(uintptr_t arg); - -/*! - * @brief UDMACC32XX Hardware attributes - * - * This structure contains the base address of the uDMA control - * table, and uDMA error interrupt attributes. - * - * The control table is used by the uDMA controller to store channel - * control structures. The control table can be located anywhere in - * system memory, but must be contiguous and aligned on a 1024-byte boundary. - * - * dmaErrorFxn is the uDMA peripheral's error interrupt handler. - * - * intPriority is priority of the uDMA peripheral's error interrupt, as - * defined by the underlying OS. It is passed unmodified to the - * underlying OS's interrupt handler creation code, so you need to - * refer to the OS documentation for usage. If the - * driver uses the ti.dpl interface instead of making OS - * calls directly, then the HwiP port handles the interrupt priority - * in an OS specific way. In the case of the SYS/BIOS port, - * intPriority is passed unmodified to Hwi_create(). - * - * A sample structure is shown below: - * @code - * - * #include - * - * #if defined(__TI_COMPILER_VERSION__) - * #pragma DATA_ALIGN(dmaControlTable, 1024) - * #elif defined(__IAR_SYSTEMS_ICC__) - * #pragma data_alignment=1024 - * #elif defined(__GNUC__) - * __attribute__ ((aligned (1024))) - * #endif - * - * static tDMAControlTable dmaControlTable[64]; - * - * #include - * - * UDMACC32XX_Object udmaCC32XXObject; - * - * const UDMACC32XX_HWAttrs udmaCC32XXHWAttrs = { - * .controlBaseAddr = (void *)dmaControlTable, - * .dmaErrorFxn = UDMACC32XX_errorFxn, - * .intNum = INT_UDMAERR, - * .intPriority = (~0) - * }; - * @endcode - * - */ -typedef struct UDMACC32XX_HWAttrs { - void *controlBaseAddr; /*!< uDMA control registers base address */ - UDMACC32XX_ErrorFxn dmaErrorFxn; /*!< uDMA error interrupt handler */ - uint8_t intNum; /*!< uDMA error interrupt number */ - uint8_t intPriority; /*!< uDMA error interrupt priority. */ -} UDMACC32XX_HWAttrs; - -/*! - * @brief UDMACC32XX Global configuration - * - * The UDMACC32XX_Config structure contains pointers used by the UDMACC32XX - * driver. - * - * This structure needs to be defined before calling UDMACC32XX_init() and - * it must not be changed thereafter. - */ -typedef struct UDMACC32XX_Config { - void *object; /*!< Pointer to UDMACC32XX object */ - void const *hwAttrs; /*!< Pointer to hardware attributes */ -} UDMACC32XX_Config; - -/*! - * @brief A handle that is returned from a UDMACC32XX_open() call. - */ -typedef struct UDMACC32XX_Config *UDMACC32XX_Handle; - -/*! - * @brief UDMACC32XX object - * - * The application must not access any member variables of this structure! - */ -typedef struct UDMACC32XX_Object { - bool isOpen; /* Flag for open/close status */ - HwiP_Handle hwiHandle; /* DMA error Hwi */ -} UDMACC32XX_Object; - -/*! - * @brief Function to close the DMA driver. - * - * This function releases Power dependency on UDMA that was previously - * set with a call to UDMACC32XX_open(). If there is only one outstanding - * UDMACC32XX_open() call (i.e. all but one UDMACC32XX_open() calls have - * been matched by a corresponding call to UDMACC32XX_close()), this - * function will disable the UDMA. - * - * @pre UDMACC32XX_open() has to be called first. - * Calling context: Task - * - * @param handle A UDMACC32XX_Handle returned from UDMACC32XX_open() - * - * @return none - * - * @sa UDMACC32XX_open - */ -extern void UDMACC32XX_close(UDMACC32XX_Handle handle); - -/*! - * @brief Function to initialize the CC32XX DMA driver - * - * The function will set the isOpen flag to false, and should be called prior - * to opening the DMA driver. - * - * @return none - * - * @sa UDMACC32XX_open() - */ -extern void UDMACC32XX_init(); - -/*! - * @brief Function to initialize the CC32XX DMA peripheral - * - * UDMACC32XX_open() can be called multiple times. Each time the - * function is called, it will set a dependency on the peripheral and - * enable the clock. The Power dependency count on the UDMA will be - * equal to the number of outstanding calls to UDMACC32XX_open(). - * Calling UDMACC32XX_close() will decrement the Power dependency count, - * and the last call to UDMACC32XX_close() will disable the UDMA. - * - * @pre UDMACC32XX_init() has to be called first. - * Calling context: Task - * - * @return UDMACC32XX_Handle on success or NULL if an error has occurred. - * - * @sa UDMACC32XX_close() - */ -extern UDMACC32XX_Handle UDMACC32XX_open(); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_dma_UDMACC32XX__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/ClockP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/ClockP.h deleted file mode 100755 index 76a0bd810b8..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/ClockP.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file ClockP.h - * - * @brief Clock interface for the RTOS Porting Interface - * - * The ClockP module can be used to schedule functions that run at intervals - * specified in the underlying kernel's system ticks. ClockP instances are - * one-shot. The one-shot function will be run once - * after the specified period has elapsed since calling ClockP_start(). - * - * The ClockP module can also be used to obtain the period of the kernel's - * system tick in microseconds. This is useful for determining the number of - * ticks needed for setting a Clock object's period. - * - * When using the TI-RTOS kernel, ClockP functions are run at software - * interrupt level. With FreeRTOS, the ClockP functions are run by a timer - * service task with priority configured by the application. - * - * A common use case is to post a semaphore in the clock function. There is a - * specific API for this: Semaphore_postFromClock(). This must be used in a - * clock function (instead of Semaphore_post). - * - * ============================================================================ - */ - -#ifndef ti_dpl_ClockP__include -#define ti_dpl_ClockP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * ClockP object. - * - * nortos: 32 (biggest of the HW-specific ClockP instance structs) - * SysBIOS: 36 - */ -#define ClockP_STRUCT_SIZE (36) - -/*! - * @brief ClockP structure. - * - * Opaque structure that should be large enough to hold any of the - * RTOS specific ClockP objects. - */ -typedef union ClockP_Struct { - uint32_t dummy; /*!< Align object */ - char data[ClockP_STRUCT_SIZE]; -} ClockP_Struct; - -/*! - * @brief Frequency-in-hertz struct - */ -typedef struct ClockP_FreqHz { - uint32_t hi; /*!< most significant 32-bits of frequency */ - uint32_t lo; /*!< least significant 32-bits of frequency */ -} ClockP_FreqHz; - -/*! - * @brief Status codes for ClockP APIs - */ -typedef enum ClockP_Status { - ClockP_OK = 0, - ClockP_FAILURE = -1 -} ClockP_Status; - -/*! - * @brief Opaque client reference to an instance of a ClockP - * - * A ClockP_Handle returned from the ::ClockP_create represents that instance. - * and then is used in the other instance based functions (e.g. ::ClockP_start, - * ::ClockP_stop, etc.). - */ -typedef void *ClockP_Handle; - -#define ClockP_handle(x) ((ClockP_Handle)(x)) - -extern uint32_t ClockP_tickPeriod; - -/*! - * @brief Prototype for a ClockP function. - */ -typedef void (*ClockP_Fxn)(uintptr_t arg); - -/*! - * @brief Basic ClockP Parameters - * - * Structure that contains the parameters passed into ::ClockP_create - * when creating a ClockP instance. The ::ClockP_Params_init function should - * be used to initialize the fields to default values before the application - * sets the fields manually. The ClockP default parameters are noted in - * ClockP_Params_init. - * The default startFlag is false, meaning the user will have to call - * ClockP_start(). If startFlag is true, the clock instance will be - * started automatically when it is created. - * - * The default value of period is 0, indicating a one-shot clock object. - * A non-zero period indicates the clock function will be called - * periodically at the period rate (in system clock ticks), after the - * clock is initially started and set to expire with the 'timeout' - * argument. - */ -typedef struct ClockP_Params { - bool startFlag; /*!< Start immediately after instance is created. */ - uint32_t period; /*!< Period of clock object. */ - uintptr_t arg; /*!< Argument passed into the clock function. */ -} ClockP_Params; - - -/*! - * @brief Function to construct a clock object. - * - * @param clockP Pointer to ClockP_Struct object. - * @param timeout The startup timeout, if supported by the RTOS. - * @param clockFxn Function called when timeout or period expires. - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The ClockP default - * parameters are noted in ::SwiP_Params_init. - * - * @return A ClockP_Handle on success or a NULL on an error - */ -extern ClockP_Handle ClockP_construct(ClockP_Struct *clockP, - ClockP_Fxn clockFxn, - uint32_t timeout, - ClockP_Params *params); - -/*! - * @brief Function to destruct a clock object - * - * @param clockP Pointer to a ClockP_Struct object that was passed to - * ClockP_construct(). - * - * @return - */ -extern void ClockP_destruct(ClockP_Struct *clockP); - -/*! - * @brief Function to create a clock object. - * - * @param clockFxn Function called when timeout or period expires. - * @param timeout The startup timeout, if supported by the RTOS. - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The ClockP default - * parameters are noted in ::ClockP_Params_init. - * - * @return A ClockP_Handle on success or a NULL on an error. This handle can - * be passed to ClockP_start() - */ -extern ClockP_Handle ClockP_create(ClockP_Fxn clockFxn, - uint32_t timeout, - ClockP_Params *params); - -/*! - * @brief Function to delete a clock. - * - * @param handle A ClockP_Handle returned from ::ClockP_create - */ -extern void ClockP_delete(ClockP_Handle handle); - -/*! - * @brief Get CPU frequency in Hz - * - * @param freq Pointer to the FreqHz structure - */ -extern void ClockP_getCpuFreq(ClockP_FreqHz *freq); - -/*! - * @brief Get the system tick period in microseconds. - * - * @return The kernel's system tick period in microseconds. - */ -extern uint32_t ClockP_getSystemTickPeriod(); - -/*! - * @brief Get the current tick value - * - * The value returned will wrap back to zero after it reaches the max - * value that can be stored in 32 bits. - * - * @return Time in system clock ticks - */ -extern uint32_t ClockP_getSystemTicks(); - -/*! - * @brief Get number of ClockP tick periods expected to expire between - * now and the next interrupt from the timer peripheral - * - * Returns the number of ClockP tick periods that are expected to expore - * between now and the next interrupt from the timer peripheral. - * - * Used internally by PowerCC26XX module - * - * @return count in ticks - */ -extern uint32_t ClockP_getTicksUntilInterrupt(); - -/*! - * @brief Get timeout of clock instance. - * - * Returns the remaining time in clock ticks if the instance has - * been started. If the clock is not active, the initial timeout value - * is returned. - * - * @return remaining timeout in clock ticks. - * - * Cannot change the initial timeout if the clock has been started. - */ -extern uint32_t ClockP_getTimeout(ClockP_Handle handle); - -/*! - * @brief Determine if a clock object is currently active (i.e., running) - * - * Returns true if the clock object is currently active, otherwise - * returns false. - * - * @return active state - */ -extern bool ClockP_isActive(ClockP_Handle handle); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * - name: NULL - * - arg: 0 - * - * @param params Pointer to the instance configuration parameters. - */ -extern void ClockP_Params_init(ClockP_Params *params); - -/*! - * @brief Set the initial timeout - * - * @param timeout Initial timeout in ClockP ticks - * - * Cannot change the initial timeout if the clock has been started. - */ -extern void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout); - -/*! - * @brief Function to start a clock. - * - * @param handle A ClockP_Handle returned from ::ClockP_create - */ -extern void ClockP_start(ClockP_Handle handle); - -/*! - * @brief Function to stop a clock. - * - * @param handle A ClockP_Handle returned from ::ClockP_create - * - * It is ok to call ClockP_stop() for a clock that has not been started. - * - * @return Status of the functions - * - ClockP_OK: Stopped the clock function successfully - * - ClockP_FAILURE: The API failed. - */ -extern void ClockP_stop(ClockP_Handle handle); - -extern void ClockP_timestamp(ClockP_Handle handle); - -/*! - * @brief Set delay in microseconds - * - * @param usec A duration in micro seconds - * - * @return ClockP_OK - */ -extern void ClockP_usleep(uint32_t usec); - -/*! - * @brief Set delay in seconds - * - * @param sec A duration in seconds - * - * @return ClockP_OK - */ -extern void ClockP_sleep(uint32_t sec); - - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_ClockP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/DebugP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/DebugP.h deleted file mode 100755 index 51faa02c346..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/DebugP.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (c) 2015, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file DebugP.h - * - * @brief Debug support - * - * The DebugP module allows application to do logging and assert checking. - * - * DebugP_assert calls can be added into code. If the code - * is compiled with the compiler define DebugP_ASSERT_ENABLED set to a - * non-zero value, the call is passed onto the underlying assert checking. - * If DebugP_ASSERT_ENABLED is zero (or not defined), the calls are - * resolved to nothing. - * - * This module sits on top of the assert checking of the underlying - * RTOS. Please refer to the underlying RTOS port implementation for - * more details. - * - * Similarly, DebugP_logN calls can be added into code. If the code - * is compiled with the compiler define DebugP_LOG_ENABLED set to a - * non-zero value, the call is passed onto the underlying assert checking. - * If DebugP_LOG_ENABLED is zero (or not defined), the calls are - * resolved to nothing. - - * This module sits on top of the logging of the underlying - * RTOS. Please refer to the underlying RTOS port implementation for - * more details. - * - * ============================================================================ - */ - -#ifndef ti_dpl_DebugP__include -#define ti_dpl_DebugP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif - -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#if DebugP_ASSERT_ENABLED -extern void _DebugP_assert(int expression, const char *file, int line); -/*! - * @brief Assert checking function - * - * If the expression is evaluated to true, the API does nothing. - * If it is evaluated to false, the underlying RTOS port implementation - * handles the assert via its mechanisms. - * - * @param expression Expression to evaluate - */ -#define DebugP_assert(expression) (_DebugP_assert(expression, \ - __FILE__, __LINE__)) -#else -#define DebugP_assert(expression) -#endif - -#if DebugP_LOG_ENABLED -/*! - * @brief Debug log function with 0 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - */ -extern void DebugP_log0(const char *format); - -/*! - * @brief Debug log function with 1 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - * @param p1 first parameter to format string - */ -extern void DebugP_log1(const char *format, uintptr_t p1); - -/*! - * @brief Debug log function with 2 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - * @param p1 first parameter to format string - * @param p2 second parameter to format string - */ -extern void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2); - -/*! - * @brief Debug log function with 3 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - * @param p1 first parameter to format string - * @param p2 second parameter to format string - * @param p3 third parameter to format string - */ -extern void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3); - -/*! - * @brief Debug log function with 4 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - * @param p1 first parameter to format string - * @param p2 second parameter to format string - * @param p3 third parameter to format string - * @param p4 fourth parameter to format string - */ -extern void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4); -#else -#define DebugP_log0(format) -#define DebugP_log1(format, p1) -#define DebugP_log2(format, p1, p2) -#define DebugP_log3(format, p1, p2, p3) -#define DebugP_log4(format, p1, p2, p3, p4) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_DebugP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiP.h deleted file mode 100755 index fa6f1260490..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiP.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file HwiP.h - * - * @brief Hardware Interrupt module for the RTOS Porting Interface - * - * The ::HwiP_disable/::HwiP_restore APIs can be called recursively. The order - * of the HwiP_restore calls, must be in reversed order. For example: - * @code - * uintptr_t key1, key2; - * key1 = HwiP_disable(); - * key2 = HwiP_disable(); - * HwiP_restore(key2); - * HwiP_restore(key1); - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_dpl_HwiP__include -#define ti_dpl_HwiP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * HwiP object. - * - * nortos: 12 - * SysBIOS: 28 - */ -#define HwiP_STRUCT_SIZE (28) - -/*! - * @brief HwiP structure. - * - * Opaque structure that should be large enough to hold any of the RTOS - * specific HwiP objects. - */ -typedef union HwiP_Struct { - uint32_t dummy; /*!< Align object */ - char data[HwiP_STRUCT_SIZE]; -} HwiP_Struct; - -/*! - * @brief Opaque client reference to an instance of a HwiP - * - * A HwiP_Handle returned from the ::HwiP_create represents that instance. - */ -typedef void *HwiP_Handle; - -/*! - * @brief Status codes for HwiP APIs - */ -typedef enum HwiP_Status { - HwiP_OK = 0, - HwiP_FAILURE = -1 -} HwiP_Status; - -/*! - * @brief Prototype for the entry function for a hardware interrupt - */ -typedef void (*HwiP_Fxn)(uintptr_t arg); - -/*! - * @brief Basic HwiP Parameters - * - * Structure that contains the parameters passed into ::HwiP_create - * when creating a HwiP instance. The ::HwiP_Params_init function should - * be used to initialize the fields to default values before the application sets - * the fields manually. The HwiP default parameters are noted in - * HwiP_Params_init. - * - * Parameter enableInt specifies if the interrupt should be enabled - * upon creation of the HwiP object. The default is true. - */ -typedef struct HwiP_Params { - uintptr_t arg; /*!< Argument passed into the Hwi function. */ - uint32_t priority; /*!< Device specific priority. */ - bool enableInt; /*!< Enable interrupt on creation. */ -} HwiP_Params; - -/*! - * @brief Interrupt number posted by SwiP - * - * The SwiP module needs its scheduler to run at key points in SwiP - * processing. This is accomplished via an interrupt that is configured - * at the lowest possible interrupt priority level and is plugged with - * the SwiP scheduler. This interrupt must be the *only* interrupt at - * that lowest priority. SwiP will post this interrupt whenever its - * scheduler needs to run. - * - * The default value for your device should suffice, but if a different - * interrupt is needed to be used for SwiP scheduling then HwiP_swiPIntNum - * can be assigned with this interrupt (early on, before HwiPs are created - * and before any SwiP gets posted). - */ -extern int HwiP_swiPIntNum; - -/*! - * @brief Function to construct a hardware interrupt object. - * - * @param hwiP Pointer to HwiP_Struct object. - * @param interruptNum Interrupt Vector Id - * @param hwiFxn entry function of the hardware interrupt - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The HwiP default - * parameters are noted in ::HwiP_Params_init. - * - * @return A HwiP_Handle on success or a NULL on an error - */ -extern HwiP_Handle HwiP_construct(HwiP_Struct *hwiP, int interruptNum, - HwiP_Fxn hwiFxn, HwiP_Params *params); - -/*! - * @brief Function to destruct a hardware interrupt object - * - * @param hwiP Pointer to a HwiP_Struct object that was passed to - * HwiP_construct(). - * - * @return - */ -extern void HwiP_destruct(HwiP_Struct *hwiP); - -/*! - * @brief Function to clear a single interrupt - * - * @param interruptNum interrupt number to clear - */ -extern void HwiP_clearInterrupt(int interruptNum); - -/*! - * @brief Function to create an interrupt on CortexM devices - * - * @param interruptNum Interrupt Vector Id - * - * @param hwiFxn entry function of the hardware interrupt - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The HwiP default - * parameters are noted in ::HwiP_Params_init. - * - * @return A HwiP_Handle on success or a NULL on an error - */ -extern HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, - HwiP_Params *params); - -/*! - * @brief Function to delete an interrupt on CortexM devices - * - * @param handle returned from the HwiP_create call - * - * @return - */ -extern void HwiP_delete(HwiP_Handle handle); - -/*! - * @brief Function to disable interrupts to enter a critical region - * - * This function can be called multiple times, but must unwound in the reverse - * order. For example - * @code - * uintptr_t key1, key2; - * key1 = HwiP_disable(); - * key2 = HwiP_disable(); - * HwiP_restore(key2); - * HwiP_restore(key1); - * @endcode - * - * @return A key that must be passed to HwiP_restore to re-enable interrupts. - */ -extern uintptr_t HwiP_disable(void); - -/*! - * @brief Function to enable interrupts - */ -extern void HwiP_enable(void); - -/*! - * @brief Function to disable a single interrupt - * - * @param interruptNum interrupt number to disable - */ -extern void HwiP_disableInterrupt(int interruptNum); - -/*! - * @brief Function to enable a single interrupt - * - * @param interruptNum interrupt number to enable - */ -extern void HwiP_enableInterrupt(int interruptNum); - -/*! - * @brief Function to return a status based on whether it is in an interrupt - * context. - * - * @return A status: indicating whether the function was called in an - * ISR (true) or at thread level (false). - */ -extern bool HwiP_inISR(void); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * - arg: 0 - * - priority: ~0 - * - enableInt: true - * - * @param params Pointer to the instance configuration parameters. - */ -extern void HwiP_Params_init(HwiP_Params *params); - -/*! - * @brief Function to plug an interrupt vector - * - * @param interruptNum ID of interrupt to plug - * @param fxn ISR that services plugged interrupt - */ -extern void HwiP_plug(int interruptNum, void *fxn); - -/*! - * @brief Function to generate an interrupt - * - * @param interruptNum ID of interrupt to generate - */ -extern void HwiP_post(int interruptNum); - -/*! - * @brief Function to restore interrupts to exit a critical region - * - * @param key return from HwiP_disable - */ -extern void HwiP_restore(uintptr_t key); - -/*! - * @brief Function to overwrite HwiP function and arg - * - * @param hwiP handle returned from the HwiP_create or construct call - * @param fxn pointer to ISR function - * @param arg argument to ISR function - */ -extern void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg); - -/*! - * @brief Function to set the priority of a hardware interrupt - * - * @param interruptNum id of the interrupt to change - * @param priority new priority - */ -extern void HwiP_setPriority(int interruptNum, uint32_t priority); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_HwiP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiPCC32XX.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiPCC32XX.cpp deleted file mode 100755 index d9cac222573..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiPCC32XX.cpp +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== HwiPCC32XX_nortos.c ======== - */ - -#include -#include - -#include -#include - -/* Driver lib includes */ -#include -#include -#include -#include -#include - -#define MAX_INTERRUPTS 195 - -typedef struct _HwiP_Obj { - uint32_t intNum; - HwiP_Fxn fxn; - uintptr_t arg; -} HwiP_Obj; - -typedef struct Hwi_NVIC { - uint32_t RES_00; - uint32_t ICTR; - uint32_t RES_08; - uint32_t RES_0C; - uint32_t STCSR; - uint32_t STRVR; - uint32_t STCVR; - uint32_t STCALIB; - uint32_t RES_20[56]; - uint32_t ISER[8]; - uint32_t RES_120[24]; - uint32_t ICER[8]; - uint32_t RES_1A0[24]; - uint32_t ISPR[8]; - uint32_t RES_220[24]; - uint32_t ICPR[8]; - uint32_t RES_2A0[24]; - uint32_t IABR[8]; - uint32_t RES_320[56]; - uint8_t IPR[240]; - uint32_t RES_4F0[516]; - uint32_t CPUIDBR; - uint32_t ICSR; - uint32_t VTOR; - uint32_t AIRCR; - uint32_t SCR; - uint32_t CCR; - uint8_t SHPR[12]; - uint32_t SHCSR; - uint8_t MMFSR; - uint8_t BFSR; - uint16_t UFSR; - uint32_t HFSR; - uint32_t DFSR; - uint32_t MMAR; - uint32_t BFAR; - uint32_t AFSR; - uint32_t PFR0; - uint32_t PFR1; - uint32_t DFR0; - uint32_t AFR0; - uint32_t MMFR0; - uint32_t MMFR1; - uint32_t MMFR2; - uint32_t MMFR3; - uint32_t ISAR0; - uint32_t ISAR1; - uint32_t ISAR2; - uint32_t ISAR3; - uint32_t ISAR4; - uint32_t RES_D74[5]; - uint32_t CPACR; - uint32_t RES_D8C[93]; - uint32_t STI; - uint32_t RES_F04[12]; - uint32_t FPCCR; - uint32_t FPCAR; - uint32_t FPDSCR; - uint32_t MVFR0; - uint32_t MVFR1; - uint32_t RES_F48[34]; - uint32_t PID4; - uint32_t PID5; - uint32_t PID6; - uint32_t PID7; - uint32_t PID0; - uint32_t PID1; - uint32_t PID2; - uint32_t PID3; - uint32_t CID0; - uint32_t CID1; - uint32_t CID2; - uint32_t CID3; -} Hwi_NVIC; - -static Hwi_NVIC *Hwi_nvic = (Hwi_NVIC *)0xE000E000; - -static HwiP_Obj* HwiP_dispatchTable[MAX_INTERRUPTS] = { - 0 -}; -uintptr_t HwiP_key = 0; - -int HwiP_swiPIntNum = FAULT_PENDSV; - - -/* - * ======== HwiP_enable ======== - */ -void HwiP_enable(void) -{ - MAP_IntMasterEnable(); -} - -/* - * ======== HwiP_disable ======== - */ -uintptr_t HwiP_disable(void) -{ - return (MAP_IntMasterDisable()); -} - -/* - * ======== HwiP_restore ======== - */ -void HwiP_restore(uintptr_t alreadyDisabled) -{ - if (!alreadyDisabled) { - MAP_IntMasterEnable(); - } -} - -/* - * ======== HwiP_clearInterrupt ======== - */ -void HwiP_clearInterrupt(int interruptNum) -{ - MAP_IntPendClear((unsigned long)interruptNum); -} - -/* - * ======== HwiP_destruct ======== - */ -void HwiP_destruct(HwiP_Struct *handle) -{ - HwiP_Obj *obj = (HwiP_Obj *)handle; - - MAP_IntDisable((unsigned long)obj->intNum); - MAP_IntUnregister((unsigned long)obj->intNum); -} - -/* - * ======== HwiP_delete ======== - */ -void HwiP_delete(HwiP_Handle handle) -{ - HwiP_destruct((HwiP_Struct *)handle); - - free(handle); -} - -/* - * ======== HwiP_disableInterrupt ======== - */ -void HwiP_disableInterrupt(int interruptNum) -{ - MAP_IntDisable((unsigned long)interruptNum); -} - -/* - * ======== HwiP_dispatch ======== - */ -void HwiP_dispatch(void) -{ - Hwi_NVIC *Hwi_nvic = (Hwi_NVIC *)0xE000E000; - - /* Determine which interrupt has fired */ - uint32_t intNum = (Hwi_nvic->ICSR & 0x000000ff); - HwiP_Obj* obj = HwiP_dispatchTable[intNum]; - if (obj) { - (obj->fxn)(obj->arg); - } -} - -/* - * ======== HwiP_enableInterrupt ======== - */ -void HwiP_enableInterrupt(int interruptNum) -{ - MAP_IntEnable((unsigned long)interruptNum); -} - -/* - * ======== HwiP_construct ======== - */ -HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, - HwiP_Fxn hwiFxn, HwiP_Params *params) -{ - HwiP_Params defaultParams; - HwiP_Obj *obj = (HwiP_Obj *)handle; - - if (handle != NULL) { - if (params == NULL) { - params = &defaultParams; - HwiP_Params_init(&defaultParams); - } - - if ((params->priority & 0xFF) == 0xFF) { - /* SwiP_nortos.c uses INT_PRIORITY_LVL_7 as its scheduler */ - params->priority = INT_PRIORITY_LVL_6; - } - - if (interruptNum != HwiP_swiPIntNum && - params->priority == INT_PRIORITY_LVL_7) { - DebugP_log0("HwiP_construct: can't use reserved INT_PRIORITY_LVL_7"); - - handle = NULL; - } - else { - HwiP_dispatchTable[interruptNum] = obj; - obj->fxn = hwiFxn; - obj->arg = params->arg; - obj->intNum = (uint32_t)interruptNum; - - MAP_IntRegister((unsigned long)interruptNum, - (void(*)(void))HwiP_dispatch); - MAP_IntPrioritySet((unsigned long)interruptNum, params->priority); - - if (params->enableInt) { - MAP_IntEnable((unsigned long)interruptNum); - } - } - } - - return ((HwiP_Handle)handle); -} - -/* - * ======== HwiP_create ======== - */ -HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params) -{ - HwiP_Handle handle; - HwiP_Handle retHandle; - - handle = (HwiP_Handle)malloc(sizeof(HwiP_Obj)); - - /* - * Even though HwiP_construct will check handle for NULL and not do - * anything, we should check it here so that we can know afterwards - * that construct failed with non-NULL pointer and that we need to - * free the handle. - */ - if (handle != NULL) { - retHandle = HwiP_construct((HwiP_Struct *)handle, interruptNum, hwiFxn, - params); - if (retHandle == NULL) { - free(handle); - handle = NULL; - } - } - - return (handle); -} - -/* - * ======== HwiP_Params_init ======== - */ -void HwiP_Params_init(HwiP_Params *params) -{ - if (params != NULL) { - params->arg = 0; - params->priority = ~0; - params->enableInt = true; - } -} - -/* - * ======== HwiP_plug ======== - */ -void HwiP_plug(int interruptNum, void *fxn) -{ - MAP_IntRegister((unsigned long)interruptNum, (void(*)(void))fxn); -} - -/* - * ======== HwiP_setFunc ======== - */ -void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg) -{ - HwiP_Obj *obj = (HwiP_Obj *)hwiP; - - uintptr_t key = HwiP_disable(); - - obj->fxn = fxn; - obj->arg = arg; - - HwiP_restore(key); -} - -/* - * ======== HwiP_post ======== - */ -void HwiP_post(int interruptNum) -{ - IntPendSet((unsigned long)interruptNum); -} - -/* - * ======== HwiP_inISR ======== - */ -bool HwiP_inISR(void) -{ - bool stat; - - if ((Hwi_nvic->ICSR & 0x000000ff) == 0) { - stat = false; - } - else { - stat = true; - } - - return (stat); -} - -/* - * ======== HwiP_inSwi ======== - */ -bool HwiP_inSwi(void) -{ - uint32_t intNum = Hwi_nvic->ICSR & 0x000000ff; - if (intNum == (uint32_t)HwiP_swiPIntNum) { - /* Currently in a Swi */ - return (true); - } - - return (false); -} - -/* - * ======== HwiP_setPriority ======== - */ -void HwiP_setPriority(int interruptNum, uint32_t priority) -{ - MAP_IntPrioritySet((unsigned long)interruptNum, (unsigned char)priority); -} - -/* - * ======== HwiP_staticObjectSize ======== - */ -size_t HwiP_staticObjectSize(void) -{ - return (sizeof(HwiP_Obj)); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.cpp deleted file mode 100755 index b8457bbf911..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.cpp +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== MutexP_freertos.c ======== - */ - -#include -#include - - -/* - * ======== MutexP_create ======== - */ -MutexP_Handle MutexP_create(MutexP_Params *params) -{ - Mutex * p_mutex; - - p_mutex = new Mutex; - - return ((MutexP_Handle)p_mutex); -} - -/* - * ======== MutexP_delete ======== - */ -void MutexP_delete(MutexP_Handle handle) -{ - delete ((Mutex *)handle); -} - -/* - * ======== MutexP_lock ======== - */ -uintptr_t MutexP_lock(MutexP_Handle handle) -{ - Mutex * p_mutex = ( Mutex *)handle; - - /* Try 1 millisecond */ - while(p_mutex->trylock_for(1) == false); - return (0); -} - -/* - * ======== MutexP_Params_init ======== - */ -void MutexP_Params_init(MutexP_Params *params) -{ - params->callback = NULL; -} - -#if (configSUPPORT_STATIC_ALLOCATION == 1) -/* - * ======== MutexP_staticObjectSize ======== - */ -size_t MutexP_staticObjectSize(void) -{ - return (sizeof(StaticSemaphore_t)); -} -#endif - -/* - * ======== MutexP_unlock ======== - */ -void MutexP_unlock(MutexP_Handle handle, uintptr_t key) -{ - Mutex * p_mutex = (Mutex *)handle; - p_mutex->unlock(); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.h deleted file mode 100755 index 037bb553327..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file MutexP.h - * - * @brief Mutex module for the RTOS Porting Interface - * - * The MutexP module allows task to maintain critical region segments. The - * MutexP module has two main functions: ::MutexP_lock and ::MutexP_unlock. - * - * The MutexP module supports recursive calls to the MutexP_lock API by a - * single task. The same number of MutexP_unlock calls must be done for the - * mutex to be release. Note: the returned key must be provided in the LIFO - * order. For example: - * @code - * uintptr_t key1, key2; - * key1 = MutexP_lock(); - * key2 = MutexP_lock(); - * MutexP_lock(key2); - * MutexP_lock(key1); - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_dpl_MutexP__include -#define ti_dpl_MutexP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * MutexP object. - * - * nortos: 12 - * SysBIOS: 40 - */ -#define MutexP_STRUCT_SIZE (40) - -/*! - * @brief MutexP structure. - * - * Opaque structure that should be large enough to hold any of the - * RTOS specific MutexP objects. - */ -typedef union MutexP_Struct { - uint32_t dummy; /*!< Align object */ - char data[MutexP_STRUCT_SIZE]; -} MutexP_Struct; - -/*! - * @brief Status codes for MutexP APIs - */ -typedef enum MutexP_Status { - /*! API completed successfully */ - MutexP_OK = 0, - /*! API failed */ - MutexP_FAILURE = -1 -} MutexP_Status; - -/*! - * @brief Opaque client reference to an instance of a MutexP - * - * A MutexP_Handle returned from the ::MutexP_create represents that instance. - * and then is used in the other instance based functions (e.g. ::MutexP_lock, - * ::MutexP_unlock, etc.). - */ -typedef void *MutexP_Handle; - -/*! - * @brief Basic MutexP Parameters - * - * Structure that contains the parameters are passed into ::MutexP_create - * when creating a MutexP instance. The ::MutexP_Params_init function should - * be used to initialize the fields to default values before the application - * sets the fields manually. The MutexP default parameters are noted in - * ::MutexP_Params_init. - */ -typedef struct MutexP_Params { - void (*callback)(void); /*!< Callback while waiting for mutex unlock */ -} MutexP_Params; - - -/*! - * @brief Function to construct a mutex. - * - * @param handle Pointer to a MutexP_Struct object - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters (MutexP default - * parameters as noted in ::MutexP_Params_init. - * - * @return A MutexP_Handle on success or a NULL on an error - */ -extern MutexP_Handle MutexP_construct(MutexP_Struct *handle, - MutexP_Params *params); - -/*! - * @brief Function to destruct a mutex object - * - * @param mutexP Pointer to a MutexP_Struct object that was passed to - * MutexP_construct(). - * - * @return - */ -extern void MutexP_destruct(MutexP_Struct *mutexP); - -/*! - * @brief Function to create a mutex. - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The MutexP default - * parameters are noted in ::MutexP_Params_init. - * - * @return A MutexP_Handle on success or a NULL on an error - */ -extern MutexP_Handle MutexP_create(MutexP_Params *params); - -/*! - * @brief Function to delete a mutex. - * - * @param handle A MutexP_Handle returned from MutexP_create - */ -extern void MutexP_delete(MutexP_Handle handle); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * callback - NULL. - * - * @param params Pointer to the instance configuration parameters. - */ -extern void MutexP_Params_init(MutexP_Params *params); - -/*! - * @brief Function to lock a mutex. - * - * This function can only be called from a Task. It cannot be called from - * an interrupt. The lock will block until the mutex is available. - * - * Users of a mutex should make every attempt to minimize the duration that - * that they have it locked. This is to minimize latency. It is recommended - * that the users of the mutex do not block while they have the mutex locked. - * - * This function unlocks the mutex. If the mutex is locked multiple times - * by the caller, the same number of unlocks must be called. - * - * @param handle A MutexP_Handle returned from ::MutexP_create - * - * @return A key is returned. This key must be passed into ::MutexP_unlock. - */ -extern uintptr_t MutexP_lock(MutexP_Handle handle); - -/*! - * @brief Function to unlock a mutex - * - * This function unlocks the mutex. If the mutex is locked multiple times - * by the caller, the same number of unlocks must be called. The order of - * the keys must be reversed. For example - * @code - * uintptr_t key1, key2; - * key1 = MutexP_lock(); - * key2 = MutexP_lock(); - * MutexP_lock(key2); - * MutexP_lock(key1); - * @endcode - * - * @param handle A MutexP_Handle returned from ::MutexP_create - * - * @param key Return from ::MutexP_lock. - */ -extern void MutexP_unlock(MutexP_Handle handle, uintptr_t key); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_MutexP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/PowerCC32XX_mbed.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/PowerCC32XX_mbed.cpp deleted file mode 100755 index 4356822bf38..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/PowerCC32XX_mbed.cpp +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2015-2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * ======== PowerCC32XX.cpp ======== - */ - -#include -#include - -/* driverlib header files */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include - - -/* bitmask of constraints that disallow LPDS */ -#define LPDS_DISALLOWED (1 << PowerCC32XX_DISALLOW_LPDS) - -/* macro to pick two matching count values */ -#define COUNT_WITHIN_TRESHOLD(a, b, c, th) \ - ((((b) - (a)) <= (th)) ? (b) : (c)) - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - - -static volatile uint32_t idleTime = 0; - -void PowerCC32XX_sleepPolicy() -{ -#if (configUSE_TICKLESS_IDLE != 0) - int i = 0; - bool returnFromSleep = FALSE; - unsigned long constraintMask; - unsigned long long ullLowPowerTimeBeforeSleep, ullLowPowerTimeAfterSleep; - unsigned long long count[3]; - unsigned long long ullSleepTime; - unsigned long long time; - unsigned long long remain; - eSleepModeStatus eSleepStatus; - - /* - * Enter a critical section that will not effect interrupts - * bringing the MCU out of sleep mode. - */ - vPortEnterCritical(); - - /* query the declared constraints */ - constraintMask = Power_getConstraintMask(); - - /* check if we are allowed to go to LPDS */ - if ((constraintMask & LPDS_DISALLOWED) == 0) { - /* - * Read the current time from a time source that will remain - * operational while the microcontroller is in a low power state. - */ - /* - * Get the current RTC count, using the fast interface; to use the - * fast interface the count must be read three times, and then - * the value that matches on at least two of the reads is chosen - */ - for (i = 0; i < 3; i++) { - count[i] = MAP_PRCMSlowClkCtrFastGet(); - } - ullLowPowerTimeBeforeSleep = - COUNT_WITHIN_TRESHOLD(count[0], count[1], count[2], 1); - - /* Stop the timer that is generating the tick interrupt. */ - MAP_SysTickDisable(); - - /* Ensure it is still ok to enter the sleep mode. */ - eSleepStatus = eTaskConfirmSleepModeStatus(); - - if (eSleepStatus == eAbortSleep ) { - /* - * A task has been moved out of the Blocked state since this - * macro was executed, or a context siwth is being held pending. - * Do not enter a sleep state. Restart the tick and exit the - * critical section. - */ - MAP_SysTickEnable(); - vPortExitCritical(); - - returnFromSleep = FALSE; - } - else { - /* convert ticks to microseconds */ - time = idleTime * ClockP_getSystemTickPeriod(); - - /* check if can go to LPDS */ - if (time > Power_getTransitionLatency(PowerCC32XX_LPDS, - Power_TOTAL)) { - remain = ((time - PowerCC32XX_TOTALTIMELPDS) * 32768) / 1000000; - - /* set the LPDS wakeup time interval */ - MAP_PRCMLPDSIntervalSet(remain); - - /* enable the wake source to be timer */ - MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_TIMER); - - /* go to LPDS mode */ - Power_sleep(PowerCC32XX_LPDS); - - /* set 'returnFromSleep' to TRUE*/ - returnFromSleep = TRUE; - } - else { - MAP_SysTickEnable(); - vPortExitCritical(); - - returnFromSleep = FALSE; - } - } - } - else { - /* A constraint was set */ - vPortExitCritical(); - } - - if (returnFromSleep) { - /* - * Determine how long the microcontroller was actually in a low - * power state for, which will be less than xExpectedIdleTime if the - * microcontroller was brought out of low power mode by an interrupt - * other than that configured by the vSetWakeTimeInterrupt() call. - * Note that the scheduler is suspended before - * portSUPPRESS_TICKS_AND_SLEEP() is called, and resumed when - * portSUPPRESS_TICKS_AND_SLEEP() returns. Therefore no other - * tasks will execute until this function completes. - */ - for (i = 0; i < 3; i++) { - count[i] = MAP_PRCMSlowClkCtrFastGet(); - } - ullLowPowerTimeAfterSleep = - COUNT_WITHIN_TRESHOLD(count[0], count[1], count[2], 1); - - ullSleepTime = ullLowPowerTimeAfterSleep - ullLowPowerTimeBeforeSleep; - - ullSleepTime = ullSleepTime*1000; - ullSleepTime = ullSleepTime/32768; - - /* - * Correct the kernels tick count to account for the time the - * microcontroller spent in its low power state. - */ - vTaskStepTick((unsigned long)ullSleepTime); - - /* Restart the timer that is generating the tick interrupt. */ - MAP_SysTickEnable(); - - /* - * Exit the critical section - it might be possible to do this - * immediately after the prvSleep() calls. - */ - vPortExitCritical(); - } - else { - MAP_PRCMSleepEnter(); - } -#endif -} - -/* - * ======== PowerCC32XX_initPolicy ======== - */ -void PowerCC32XX_initPolicy() -{ -} -#if 0 -/* Tickless Hook */ -void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) -{ -#if (configUSE_TICKLESS_IDLE != 0) - idleTime = xExpectedIdleTime; - Power_idleFunc(); -#endif -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.cpp deleted file mode 100755 index 85c2336af9a..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.cpp +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * ======== SemaphoreP.c ======== - */ -#include -//#include -#include "mbed.h" - -/* - * Maximum count for a semaphore. - */ -#define MAXCOUNT 0xffff - -/* - * ======== SemaphoreP_create ======== - */ -SemaphoreP_Handle SemaphoreP_create(unsigned int count, - SemaphoreP_Params *params) -{ - SemaphoreP_Handle sem = NULL; - SemaphoreP_Params semParams; - - if (params == NULL) { - params = &semParams; - SemaphoreP_Params_init(params); - } - - if (params->mode == SemaphoreP_Mode_COUNTING) { -#if (configUSE_COUNTING_SEMAPHORES == 1) - Semaphore * p_sem = new Semaphore(0, count); - sem = (void*)p_sem; -#endif - } - else { - Semaphore * p_sem = new Semaphore(0, count); - sem = (void*)p_sem; - if ((sem != NULL) && (count != 0)) { - p_sem->release(); - } - } - return ((SemaphoreP_Handle)sem); -} - -/* - * ======== SemaphoreP_createBinary ======== - */ -SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count) -{ - SemaphoreP_Handle sem = NULL; - - Semaphore * p_sem = new Semaphore(count, 1); - - sem = (void*)p_sem; - if ((sem != NULL) && (count != 0)) { - p_sem->release(); - } - return ((SemaphoreP_Handle)sem); -} - -/* - * ======== SemaphoreP_delete ======== - */ -void SemaphoreP_delete(SemaphoreP_Handle handle) -{ - delete ((Semaphore *)handle); -} - -/* - * ======== SemaphoreP_Params_init ======== - */ -void SemaphoreP_Params_init(SemaphoreP_Params *params) -{ - params->mode = SemaphoreP_Mode_COUNTING; - params->callback = NULL; -} - -/* - * ======== SemaphoreP_pend ======== - */ -SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout) -{ - if (((Semaphore *)handle)->try_acquire_for(timeout)) - { - return (SemaphoreP_OK); - } - - return (SemaphoreP_TIMEOUT); -} - -/* - * ======== SemaphoreP_post ======== - */ -void SemaphoreP_post(SemaphoreP_Handle handle) -{ - ((Semaphore *)handle)->release(); -} - -#if (configSUPPORT_STATIC_ALLOCATION == 1) -/* - * ======== SemaphoreP_staticObjectSize ======== - */ -size_t SemaphoreP_staticObjectSize(void) -{ - return (sizeof(StaticSemaphore_t)); -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.h deleted file mode 100755 index 7753e2d75f2..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file SemaphoreP.h - * - * @brief Semaphore module for the RTOS Porting Interface - * - * Semaphores can be counting semaphores or binary semaphores. Counting - * semaphores keep track of the number of times the semaphore has been posted - * with post functions. This is useful, for example, if you have a group of - * resources that are shared between tasks. Such tasks might call pend() to see - * if a resource is available before using one. A count of zero for a counting - * semaphore denotes that it is not available. A positive count denotes - * how many times a SemaphoreP_pend can be called before it is blocked (or - * returns SemaphoreP_TIMEOUT). - * - * Binary semaphores can have only two states: available (count = 1) and - * unavailable (count = 0). They can be used to share a single resource - * between tasks. They can also be used for a basic signalling mechanism, where - * the semaphore can be posted multiple times. Binary semaphores do not keep - * track of the count; they simply track whether the semaphore has been posted - * or not. - * - * ============================================================================ - */ - -#ifndef ti_dpl_SemaphoreP__include -#define ti_dpl_SemaphoreP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * SemaphoreP object. - * - * nortos: 16 - * SysBIOS: 28 - */ -#define SemaphoreP_STRUCT_SIZE (28) - -/*! - * @brief SemaphoreP structure. - * - * Opaque structure that should be large enough to hold any of the - * RTOS specific SemaphoreP objects. - */ -typedef union SemaphoreP_Struct { - uint32_t dummy; /*!< Align object */ - char data[SemaphoreP_STRUCT_SIZE]; -} SemaphoreP_Struct; - -/*! - * @brief Wait forever define - */ -#define SemaphoreP_WAIT_FOREVER ~(0) - -/*! - * @brief No wait define - */ -#define SemaphoreP_NO_WAIT (0) - -/*! - * @brief Status codes for SemaphoreP APIs (for backwards compatibility) - */ -typedef enum SemaphoreP_Status { - /*! API completed successfully */ - SemaphoreP_OK = 0, - /*! API failed because of a timeout */ - SemaphoreP_TIMEOUT = -1 -} SemaphoreP_Status; - -/*! - * @brief Opaque client reference to an instance of a SemaphoreP - * - * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that - * instance and is used in the other instance based functions (e.g. - * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). - */ -typedef void *SemaphoreP_Handle; - -/*! - * @brief Mode of the semaphore - */ -typedef enum SemaphoreP_Mode { - SemaphoreP_Mode_COUNTING = 0x0, - SemaphoreP_Mode_BINARY = 0x1 -} SemaphoreP_Mode; - -/*! - * @brief Basic SemaphoreP Parameters - * - * Structure that contains the parameters are passed into ::SemaphoreP_create - * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function - * should be used to initialize the fields to default values before the - * application sets the fields manually. The SemaphoreP default parameters are - * noted in SemaphoreP_Params_init. - */ -typedef struct SemaphoreP_Params { - SemaphoreP_Mode mode; /*!< Mode for the semaphore */ - void (*callback)(void); /*!< Callback while pending for semaphore post */ -} SemaphoreP_Params; - -/*! - * @brief Default SemaphoreP instance parameters - * - * SemaphoreP_defaultParams represents the default parameters that are - * used when creating or constructing a SemaphoreP instance. - * SemaphoreP_Params_init() will use the contents of this structure for - * initializing the SemaphoreP_Params instance. - * - * SemaphoreP_defaultParams is exposed to the application for the purpose - * of allowing the application to change the default parameters for all - * SemaphoreP instances created thereafter. The main intent for allowing - * the default parameters to be changed is for setting a semaphore's - * callback function to Power_idleFunc(), so that the SOC can enter low - * power mode when pending on a semaphore. - */ -extern SemaphoreP_Params SemaphoreP_defaultParams; - - -/* - * SemaphoreP construct APIs can only be used if one of the OS's - * is defined. For FreeRTOS, configSUPPORT_STATIC_ALLOCATION also - * has to be set to 1 in FreeRTOSConfig.h. - */ -extern SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, - unsigned int count, SemaphoreP_Params *params); - -extern SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, - unsigned int count); - -extern void SemaphoreP_destruct(SemaphoreP_Struct *semP); - -/*! - * @brief Function to create a semaphore. - * - * @param count Initial count of the semaphore. For binary semaphores, - * only values of 0 or 1 are valid. - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters (SemaphoreP default - * parameters as noted in ::SemaphoreP_Params_init. - * - * @return A SemaphoreP_Handle on success or a NULL on an error - */ -extern SemaphoreP_Handle SemaphoreP_create(unsigned int count, - SemaphoreP_Params *params); - -/*! - * @brief Function to create a binary semaphore. - * - * This can be used instead of SemaphoreP_create() to create a binary - * semaphore. - * - * @param count Initial count of the binary semaphore. Only values - * of 0 or 1 are valid. - * - * @return A SemaphoreP_Handle on success or a NULL on an error - */ -extern SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count); - -/*! - * @brief Function to create a binary semaphore. - * - * This can be used instead of SemaphoreP_create() to create a binary - * semaphore. - * - * @param count Initial count of the binary semaphore. Only values - * of 0 or 1 are valid. - * - * @return A SemaphoreP_Handle on success or a NULL on an error - */ -extern SemaphoreP_Handle SemaphoreP_createBinaryCallback(unsigned int count, - void (*callback)(void)); - -/*! - * @brief Function to delete a semaphore. - * - * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create - */ -extern void SemaphoreP_delete(SemaphoreP_Handle handle); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * - mode: SemaphoreP_Mode_COUNTING - * - name: NULL - * - * @param params Pointer to the instance configuration parameters. - */ -extern void SemaphoreP_Params_init(SemaphoreP_Params *params); - -/*! - * @brief Function to pend (wait) on a semaphore. - * - * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create - * - * @param timeout Timeout (in ClockP ticks) to wait for the semaphore to - * be posted (signalled). - * - * @return Status of the functions - * - SemaphoreP_OK: Obtained the semaphore - * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. - */ -extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, - uint32_t timeout); - -/*! - * @brief Function to post (signal) a semaphore from task of ISR context. - * - * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create - */ -extern void SemaphoreP_post(SemaphoreP_Handle handle); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_SemaphoreP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SwiP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SwiP.h deleted file mode 100755 index 4f2b3f11d4d..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SwiP.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file SwiP.h - * - * @brief Software Interrupt module for the RTOS Porting Interface - * - * ============================================================================ - */ - -#ifndef ti_dpl_SwiP__include -#define ti_dpl_SwiP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * SwiP object. - * - * nortos: 40 - * SysBIOS: 52 - */ -#define SwiP_STRUCT_SIZE (52) - -/*! - * @brief SemaphoreP structure. - * - * Opaque structure that should be large enough to hold any of the - * RTOS specific SwiP objects. - */ -typedef union SwiP_Struct { - uint32_t dummy; /*!< Align object */ - char data[SwiP_STRUCT_SIZE]; -} SwiP_Struct; - -#include -#include -#include - -/*! - * @brief Opaque client reference to an instance of a SwiP - * - * A SwiP_Handle returned from the ::SwiP_create represents that instance. - */ -typedef void *SwiP_Handle; - -/*! - * @brief Status codes for SwiP APIs - * TODO: See if we need more error codes. - */ -typedef enum SwiP_Status { - SwiP_OK = 0, - SwiP_FAILURE = -1 -} SwiP_Status; - -/*! - * @brief Prototype for the entry function for a hardware interrupt - */ -typedef void (*SwiP_Fxn)(uintptr_t arg0, uintptr_t arg1); - -/*! - * @brief Basic SwiP Parameters - * - * Structure that contains the parameters passed into ::SwiP_create - * and ::SwiP_construct when creating or constructing a SwiP instance. - * The ::SwiP_Params_init function should be used to initialize the - * fields to default values before the application sets the fields - * manually. The SwiP default parameters are noted in ::SwiP_Params_init. - * - * Each SwiP object has a "trigger" used either to determine whether to - * post the SwiP or as a value that can be evaluated within the SwiP's - * function. - * - * The SwiP_andn and SwiP_dec functions post the SwiP - * if the trigger value transitions to 0. The SwiP_or and - * SwiP_inc functions also modify the trigger value. SwiP_or - * sets bits, and SwiP_andn clears bits. - */ -typedef struct SwiP_Params { - uintptr_t arg0; /*!< Argument passed into the SwiP function. */ - uintptr_t arg1; /*!< Argument passed into the SwiP function. */ - uint32_t priority; /*!< priority, 0 is min, 1, 2, ..., ~0 for max */ - uint32_t trigger; /*!< Initial SwiP trigger value. */ -} SwiP_Params; - -/*! - * @brief Function to construct a software interrupt object. - * - * @param swiP Pointer to SwiP_Struct object. - * @param swiFxn entry function of the software interrupt - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The SwiP default - * parameters are noted in ::SwiP_Params_init. - * - * @return A SwiP_Handle on success or a NULL on an error - */ -extern SwiP_Handle SwiP_construct(SwiP_Struct *swiP, SwiP_Fxn swiFxn, - SwiP_Params *params); - -/*! - * @brief Function to destruct a software interrupt object - * - * @param swiP Pointer to a SwiP_Struct object that was passed to - * SwiP_construct(). - * - * @return - */ -extern void SwiP_destruct(SwiP_Struct *swiP); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * - name: NULL - * - * @param params Pointer to the instance configuration parameters. - */ -extern void SwiP_Params_init(SwiP_Params *params); - -/*! - * @brief Function to create a software interrupt object. - * - * @param swiFxn entry function of the software interrupt - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The SwiP default - * parameters are noted in ::SwiP_Params_init. - * - * @return A SwiP_Handle on success or a NULL on an error - */ -extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, - SwiP_Params *params); - -/*! - * @brief Function to delete a software interrupt object - * - * @param handle returned from the SwiP_create call - * - */ -extern void SwiP_delete(SwiP_Handle handle); - -/*! - * @brief Function to disable software interrupts - * - * This function can be called multiple times, but must unwound in the reverse - * order. For example - * @code - * uintptr_t key1, key2; - * key1 = SwiP_disable(); - * key2 = SwiP_disable(); - * SwiP_restore(key2); - * SwiP_restore(key1); - * @endcode - * - * @return A key that must be passed to SwiP_restore to re-enable interrupts. - */ -extern uintptr_t SwiP_disable(void); - -/*! - * @brief Function to get the trigger value of the currently running SwiP. - * - */ -extern uint32_t SwiP_getTrigger(); - -/*! - * @brief Clear bits in SwiP's trigger. Post SwiP if trigger becomes 0. - * - * @param handle returned from the SwiP_create or SwiP_construct call - * @param mask inverse value to be ANDed - */ -extern void SwiP_andn(SwiP_Handle handle, uint32_t mask); - -/*! - * @brief Decrement SwiP's trigger value. Post SwiP if trigger becomes 0. - * - * @param handle returned from the SwiP_create or SwiP_construct call - */ -extern void SwiP_dec(SwiP_Handle handle); - -/*! - * @brief Increment the SwiP's trigger value and post the SwiP. - * - * @param handle returned from the SwiP_create or SwiP_construct call - */ -extern void SwiP_inc(SwiP_Handle handle); - -/*! - * @brief Function to return a status based on whether it is in a - * software interrupt context. - * - * @return A status: indicating whether the function was called in a - * software interrupt routine (true) or not (false). - */ -extern bool SwiP_inISR(void); - -/*! - * @brief Or the mask with the SwiP's trigger value and post the SwiP. - * - * @param handle returned from the SwiP_create or SwiP_construct call - * @param mask value to be ORed - */ -extern void SwiP_or(SwiP_Handle handle, uint32_t mask); - -/*! - * @brief Unconditionally post a software interrupt. - * - * @param handle returned from the SwiP_create or SwiP_construct call - */ -extern void SwiP_post(SwiP_Handle handle); - -/*! - * @brief Function to restore software interrupts - * - * @param key return from SwiP_disable - */ -extern void SwiP_restore(uintptr_t key); - -/*! - * @brief Function to set the priority of a software interrupt - * - * @param handle returned from the SwiP_create or SwiP_construct call - * @param priority new priority - */ -extern void SwiP_setPriority(SwiP_Handle handle, uint32_t priority); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_SwiP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SystemP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SystemP.h deleted file mode 100755 index b5aa4c1aea0..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SystemP.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** =========================================================================== - * @file SystemP.h - * - * @brief System module for the RTOS Porting Interface - * - * Basic system services for supporting printf-like output. - * - * =========================================================================== - */ - -#ifndef ti_dpl_SystemP__include -#define ti_dpl_SystemP__include - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -extern int SystemP_snprintf(char *buf, size_t n, const char *format,...); -extern int SystemP_vsnprintf(char *buf, size_t n, const char *format, va_list va); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_SemaphoreP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/device.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/device.h deleted file mode 100755 index d897e6e7d29..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/device.h +++ /dev/null @@ -1,731 +0,0 @@ -/* - * device.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __DEVICE_H__ -#define __DEVICE_H__ - - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup Device - \short Controls the behaviour of the CC31xx/CC32xx device (start/stop, events masking and obtaining specific device status) - -*/ - -/*! - - \addtogroup Device - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -/* Convert event id to event mask to be used in sl_DeviceEventMaskSet and sl_DeviceEventMaskGet */ -#define SL_DEVICE_EVENT_BIT(EventId) (SL_WLAN_VAL_2_MASK(EventId,1) ) - - - -typedef enum -{ - SL_DEVICE_EVENT_FATAL_DEVICE_ABORT = 1, - SL_DEVICE_EVENT_FATAL_DRIVER_ABORT, - SL_DEVICE_EVENT_FATAL_SYNC_LOSS, - SL_DEVICE_EVENT_FATAL_NO_CMD_ACK, - SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, - SL_DEVICE_EVENT_RESET_REQUEST, - SL_DEVICE_EVENT_ERROR, - SL_DEVICE_EVENT_MAX - -} SlDeviceEventId_e; - -typedef struct -{ - _i16 Status; - _u16 Caller; -}SlDeviceEventResetRequest_t; - -typedef enum -{ - SL_DEVICE_SOURCE_OTHER, - SL_DEVICE_SOURCE_WLAN, - SL_DEVICE_SOURCE_NETCFG, - SL_DEVICE_SOURCE_NETAPP, - SL_DEVICE_SOURCE_SECURITY, - - SL_DEVICE_SOURCE_LAST = 0xFF /* last one */ -}SlDeviceSource_e; - -typedef struct -{ - SlDeviceSource_e Source; - _i16 Code; -}SlDeviceEventError_t; - -typedef union -{ - SlDeviceEventResetRequest_t ResetRequest; - SlDeviceEventError_t Error; -}SlDeviceEventData_u; - - - -typedef enum -{ - SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING, - SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING_EXTERNAL_CONFIGURATION, - SL_DEVICE_RESET_REQUEST_NUM_OF_CALLERS -}SlDeviceResetRequestCaller_e; - -typedef struct -{ - _u32 Id; - SlDeviceEventData_u Data; -}SlDeviceEvent_t; - -/*! - \cond DOXYGEN_REMOVE -*/ -void slcb_DeviceEvtHdlr(SlDeviceEvent_t* pEvent); -/*! - \endcond -*/ - -typedef struct -{ - _u32 Code; - _u32 Value; -} SlDeviceFatalDeviceAssert_t; - - -typedef struct -{ - _u32 Code; -} SlDeviceFatalNoCmdAck_t, SlDeviceFatalCmdTimeout_t; - - -typedef union -{ - SlDeviceFatalDeviceAssert_t DeviceAssert; - SlDeviceFatalNoCmdAck_t NoCmdAck; - SlDeviceFatalCmdTimeout_t CmdTimeout; -}SlDeviceFatalData_u; - - -typedef struct -{ - _u32 Id; - SlDeviceFatalData_u Data; -}SlDeviceFatal_t; - - - -/* - Declare the different IDs for sl_DeviceGet and sl_DeviceSet - */ -#define SL_DEVICE_GENERAL (1) -#define SL_DEVICE_IOT (4) -#define SL_DEVICE_STATUS (2) - -/* - Declare the different Options for SL_DEVICE_GENERAL in sl_DeviceGet and sl_DeviceSet - */ -#define SL_DEVICE_GENERAL_DATE_TIME (11) -#define SL_DEVICE_GENERAL_PERSISTENT (5) -#define SL_DEVICE_GENERAL_VERSION (12) -/* - Declare the different Options for SL_DEVICE_IOT in sl_DeviceGet and sl_DeviceSet -*/ -#define SL_DEVICE_IOT_UDID (41) - -/* Events list to mask/unmask*/ -#define SL_DEVICE_EVENT_CLASS_DEVICE (1) -#define SL_DEVICE_EVENT_CLASS_WLAN (2) -#define SL_DEVICE_EVENT_CLASS_BSD (3) -#define SL_DEVICE_EVENT_CLASS_NETAPP (4) -#define SL_DEVICE_EVENT_CLASS_NETCFG (5) -#define SL_DEVICE_EVENT_CLASS_FS (6) -#define SL_DEVICE_EVENT_CLASS_NETUTIL (7) - - -/****************** DEVICE CLASS status ****************/ -#define SL_DEVICE_EVENT_DROPPED_DEVICE_ASYNC_GENERAL_ERROR (0x00000001L) -#define SL_DEVICE_STATUS_DEVICE_SMART_CONFIG_ACTIVE (0x80000000L) - -/****************** WLAN CLASS status ****************/ -#define SL_DEVICE_EVENT_DROPPED_WLAN_WLANASYNCONNECTEDRESPONSE (0x00000001L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_WLANASYNCDISCONNECTEDRESPONSE (0x00000002L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_STA_CONNECTED (0x00000004L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_STA_DISCONNECTED (0x00000008L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_P2P_DEV_FOUND (0x00000010L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_CONNECTION_FAILED (0x00000020L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_P2P_NEG_REQ_RECEIVED (0x00000040L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_RX_FILTERS (0x00000080L) -#define SL_DEVICE_STATUS_WLAN_STA_CONNECTED (0x80000000L) - -/****************** NETAPP CLASS status ****************/ -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPACQUIRED (0x00000001L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPACQUIRED_V6 (0x00000002L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_LEASED (0x00000004L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_RELEASED (0x00000008L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPV4_LOST (0x00000010L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_DHCP_ACQUIRE_TIMEOUT (0x00000020L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_COLLISION (0x00000040L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPV6_LOST (0x00000080L) - -/****************** BSD CLASS status ****************/ -#define SL_DEVICE_EVENT_DROPPED_SOCKET_TXFAILEDASYNCRESPONSE (0x00000001L) - -/****************** FS CLASS ****************/ - - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -#ifdef SL_IF_TYPE_UART -typedef struct -{ - _u32 BaudRate; - _u8 FlowControlEnable; - _u8 CommPort; -} SlDeviceUartIfParams_t; -#endif - -#ifdef SL_IF_TYPE_UART - -#define SL_DEVICE_BAUD_9600 (9600L) -#define SL_DEVICE_BAUD_14400 (14400L) -#define SL_DEVICE_BAUD_19200 (19200L) -#define SL_DEVICE_BAUD_38400 (38400L) -#define SL_DEVICE_BAUD_57600 (57600L) -#define SL_DEVICE_BAUD_115200 (115200L) -#define SL_DEVICE_BAUD_230400 (230400L) -#define SL_DEVICE_BAUD_460800 (460800L) -#define SL_DEVICE_BAUD_921600 (921600L) - -#endif - -typedef struct -{ - _u32 ChipId; - _u8 FwVersion[4]; - _u8 PhyVersion[4]; - _u8 NwpVersion[4]; - _u16 RomVersion; - _u16 Padding; -}SlDeviceVersion_t; - - -typedef struct -{ - /* time */ - _u32 tm_sec; - _u32 tm_min; - _u32 tm_hour; - /* date */ - _u32 tm_day; /* 1-31 */ - _u32 tm_mon; /* 1-12 */ - _u32 tm_year; /* YYYY 4 digits */ - _u32 tm_week_day; /* not required */ - _u32 tm_year_day; /* not required */ - _u32 reserved[3]; -}SlDateTime_t; - - -/******************************************************************************/ -/* Type declarations */ -/******************************************************************************/ -typedef struct -{ - _u32 ChipId; - _u32 MoreData; -}SlDeviceInitInfo_t; - -typedef void (*P_INIT_CALLBACK)(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo); - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - \brief Start the SimpleLink device - - This function initialize the communication interface, set the enable pin - of the device, and call to the init complete callback. - - \param[in] pIfHdl Opened Interface Object. In case the interface - must be opened outside the SimpleLink Driver, the - user might give the handler to be used in \n - any access of the communication interface with the - device (UART/SPI). \n - The SimpleLink driver will open an interface port - only if this parameter is null! \n - \param[in] pDevName The name of the device to open. Could be used when - the pIfHdl is null, to transfer information to the - open interface function \n - This pointer could be used to pass additional information to - sl_IfOpen in case it is required (e.g. UART com port name) - \param[in] pInitCallBack Pointer to function that would be called - on completion of the initialization process.\n - If this parameter is NULL the function is - blocked until the device initialization - is completed, otherwise the function returns - immediately. - - \return Returns the current active role (STA/AP/P2P) or an error code: - - ROLE_STA, ROLE_AP, ROLE_P2P in case of success, - otherwise in failure one of the following is return: - - SL_ERROR_ROLE_STA_ERR (Failure to load MAC/PHY in STA role) - - SL_ERROR_ROLE_AP_ERR (Failure to load MAC/PHY in AP role) - - SL_ERROR_ROLE_P2P_ERR (Failure to load MAC/PHY in P2P role) - - SL_ERROR_CALIB_FAIL (Failure of calibration) - - SL_ERROR_FS_CORRUPTED_ERR (FS is corrupted, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram)) - - SL_ERROR_FS_ALERT_ERR (Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram)) - - SL_ERROR_RESTORE_IMAGE_COMPLETE (Return to factory image completed, perform reset) - - SL_ERROR_GENERAL_ERR (General error during init) - - \sa sl_Stop - - \note Belongs to \ref basic_api - - \warning This function must be called before any other SimpleLink API is used, or after sl_Stop is called for reinit the device - \par Example: - - - Open interface without callback routine. The interface name and handler are - handled by the sl_IfOpen routine: - \code - if( sl_Start(NULL, NULL, NULL) < 0 ) - { - LOG("Error opening interface to device\n"); - } - \endcode -
- - - Open interface with a callback routine: - \code - void SimpleLinkInitCallback(_u32 status) - { - LOG("Handle SimpleLink Interface acording to ststus %d\n", status); - } - - void main(void) - { - if (sl_Start(NULL, NULL, SimpleLinkInitCallback) < 0) - { - LOG("Error opening interface to device\n"); - } - } - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_Start) -_i16 sl_Start(const void* pIfHdl, _i8* pDevName, const P_INIT_CALLBACK pInitCallBack); -#endif - -/*! - \brief Stop the SimpleLink device - - This function clears the enable pin of the device, closes the communication \n - interface and invokes the stop complete callback - - \param[in] Timeout Stop timeout in msec. Should be used to give the device time to finish \n - any transmission/reception that is not completed when the function was called. \n - Additional options: - - 0 Enter to hibernate immediately \n - - 0xFFFF Host waits for device's response before \n - hibernating, without timeout protection \n - - 0 < Timeout[msec] < 0xFFFF Host waits for device's response before \n - hibernating, with a defined timeout protection \n - This timeout defines the max time to wait. The NWP \n - response can be sent earlier than this timeout. - - \return Zero on success, or a negative value if an error occurred - - \sa sl_Start - - \note This API will shutdown the device and invoke the "i/f close" function regardless \n - if it was opened implicitly or explicitly. \n - It is up to the platform interface library to properly handle interface close \n - routine \n - Belongs to \ref basic_api \n - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Stop) -_i16 sl_Stop(const _u16 Timeout); -#endif - - -/*! - \brief Setting device configurations - - \param[in] DeviceSetId configuration id: - - SL_DEVICE_GENERAL - - \param[in] Option configurations option: - - SL_DEVICE_GENERAL_DATE_TIME - - SL_DEVICE_GENERAL_PERSISTENT - \param[in] ConfigLen configurations len - \param[in] pValues configurations values - - \return Zero on success, or a negative value if an error occurred - \par Persistent - SL_DEVICE_GENERAL_DATE_TIME - System Persistent (kept during hibernate only, See Note for details) \n - SL_DEVICE_GENERAL_PERSISTENT - Persistent - \sa - \note Persistency for SL_DEVICE_GENERAL_DATE_TIME - The original setted value will be kept as System Persistence.\n - The updated date and time though, will be kept during hibernate only. - \warning - \par Examples: - - - Setting device time and date example: - \code - SlDateTime_t dateTime= {0}; - dateTime.tm_day = (_u32)23; // Day of month (DD format) range 1-31 - dateTime.tm_mon = (_u32)6; // Month (MM format) in the range of 1-12 - dateTime.tm_year = (_u32)2014; // Year (YYYY format) - dateTime.tm_hour = (_u32)17; // Hours in the range of 0-23 - dateTime.tm_min = (_u32)55; // Minutes in the range of 0-59 - dateTime.tm_sec = (_u32)22; // Seconds in the range of 0-59 - sl_DeviceSet(SL_DEVICE_GENERAL, - SL_DEVICE_GENERAL_DATE_TIME, - sizeof(SlDateTime_t), - (_u8 *)(&dateTime)); - \endcode -
- - - Setting system persistent configuration:
- Sets the default system-wide configuration persistence mode. - In case true, all APIs that follow 'system configured' persistence (see persistence attribute noted per API) shall maintain the configured settings. - In case false, all calls to APIs that follow 'system configured' persistence shall be volatile. Configuration should revert to default after reset or power recycle - \code - _u8 persistent = 1; - sl_DeviceSet(SL_DEVICE_GENERAL, - SL_DEVICE_GENERAL_PERSISTENT, - sizeof(_u8), - (_u8 *)(&persistent)); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_DeviceSet) -_i16 sl_DeviceSet(const _u8 DeviceSetId ,const _u8 Option,const _u16 ConfigLen,const _u8 *pValues); -#endif - -/*! - \brief Internal function for getting device configurations - \param[in] DeviceGetId configuration id: - - SL_DEVICE_STATUS - - SL_DEVICE_GENERAL - - SL_DEVICE_IOT - - \param[out] pOption Get configurations option: - - SL_DEVICE_STATUS: - - SL_DEVICE_EVENT_CLASS_DEVICE - - SL_DEVICE_EVENT_CLASS_WLAN - - SL_DEVICE_EVENT_CLASS_BSD - - SL_DEVICE_EVENT_CLASS_NETAPP - - SL_DEVICE_EVENT_CLASS_NETCFG - - SL_DEVICE_EVENT_CLASS_FS - - SL_DEVICE_GENERAL: - - SL_DEVICE_GENERAL_VERSION - - SL_DEVICE_GENERAL_DATE_TIME - - SL_DEVICE_GENERAL_PERSISTENT - - SL_DEVICE_IOT: - - SL_DEVICE_IOT_UDID - - \param[out] pConfigLen The length of the allocated memory as input, when the - function complete, the value of this parameter would be - the len that actually read from the device.\n - If the device return length that is longer from the input - value, the function will cut the end of the returned structure - and will return SL_ESMALLBUF - \param[out] pValues Get requested configurations values - \return Zero on success, or a negative value if an error occurred - \sa - \note - \warning - \par Examples - - - Getting WLAN class status (status is always cleared on read): - \code - _u32 statusWlan; - _u8 pConfigOpt; - _u16 pConfigLen; - pConfigOpt = SL_DEVICE_EVENT_CLASS_WLAN; - pConfigLen = sizeof(_u32); - sl_DeviceGet(SL_DEVICE_STATUS,&pConfigOpt,&pConfigLen,(_u8 *)(&statusWlan)); - if (SL_DEVICE_STATUS_WLAN_STA_CONNECTED & statusWlan ) - { - printf("Device is connected\n"); - } - if (SL_DEVICE_EVENT_DROPPED_WLAN_RX_FILTERS & statusWlan ) - { - printf("RX filer event dropped\n"); - } - - \endcode -
- - - Getting version: - \code - SlDeviceVersion_t ver; - pConfigLen = sizeof(ver); - pConfigOpt = SL_DEVICE_GENERAL_VERSION; - sl_DeviceGet(SL_DEVICE_GENERAL,&pConfigOpt,&pConfigLen,(_u8 *)(&ver)); - printf("CHIP %d\nMAC 31.%d.%d.%d.%d\nPHY %d.%d.%d.%d\nNWP %d.%d.%d.%d\nROM %d\nHOST %d.%d.%d.%d\n", - ver.ChipId, - ver.FwVersion[0],ver.FwVersion[1], - ver.FwVersion[2],ver.FwVersion[3], - ver.PhyVersion[0],ver.PhyVersion[1], - ver.PhyVersion[2],ver.PhyVersion[3], - ver.NwpVersion[0],ver.NwpVersion[1],ver.NwpVersion[2],ver.NwpVersion[3], - ver.RomVersion, - SL_MAJOR_VERSION_NUM,SL_MINOR_VERSION_NUM,SL_VERSION_NUM,SL_SUB_VERSION_NUM); - - \endcode -
- - - Getting Device time and date: - \code - SlDateTime_t dateTime = {0}; - _i16 configLen = sizeof(SlDateTime_t); - _i8 configOpt = SL_DEVICE_GENERAL_DATE_TIME; - sl_DeviceGet(SL_DEVICE_GENERAL,&configOpt, &configLen,(_u8 *)(&dateTime)); - - printf("Day %d,Mon %d,Year %d,Hour %,Min %d,Sec %d\n",dateTime.tm_day,dateTime.tm_mon,dateTime.tm_year, - dateTime.tm_hour,dateTime.tm_min,dateTime.tm_sec); - \endcode - - - Getting persistency system configuration: - \code - _i16 configLen = sizeof(_u8); - _i8 configOpt = SL_DEVICE_GENERAL_PERSISTENT; - sl_DeviceGet(SL_DEVICE_GENERAL,&configOpt, &configLen,&persistent); - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_DeviceGet) -_i16 sl_DeviceGet(const _u8 DeviceGetId, _u8 *pOption,_u16 *pConfigLen, _u8 *pValues); -#endif - - -/*! - \brief Set asynchronous event mask - - Mask asynchronous events from the device.\n - Masked events do not generate asynchronous messages from the device.\n - By default - all events are active - - - - \param[in] EventClass The classification groups that the - mask is referred to. Need to be one of - the following: - - SL_DEVICE_EVENT_CLASS_DEVICE - - SL_DEVICE_EVENT_CLASS_WLAN - - SL_DEVICE_EVENT_CLASS_BSD - - SL_DEVICE_EVENT_CLASS_NETAPP - - SL_DEVICE_EVENT_CLASS_NETCFG - - SL_DEVICE_EVENT_CLASS_FS - - - \param[in] Mask Event Mask bitmap. Valid mask are (per group): - - SL_DEVICE_EVENT_CLASS_WLAN user events - - SL_WLAN_EVENT_CONNECT - - SL_WLAN_EVENT_P2P_CONNECT - - SL_WLAN_EVENT_DISCONNECT - - SL_WLAN_EVENT_P2P_DISCONNECT - - SL_WLAN_EVENT_STA_ADDED - - SL_WLAN_EVENT_STA_REMOVED - - SL_WLAN_EVENT_P2P_CLIENT_ADDED - - SL_WLAN_EVENT_P2P_CLIENT_REMOVED - - SL_WLAN_EVENT_P2P_DEVFOUND - - SL_WLAN_EVENT_P2P_REQUEST - - SL_WLAN_EVENT_P2P_CONNECTFAIL - - SL_WLAN_EVENT_PROVISIONING_STATUS - - SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED - - SL_WLAN_EVENT_RXFILTER - - - SL_DEVICE_EVENT_CLASS_DEVICE user events - - SL_DEVICE_EVENT_ERROR - - - SL_DEVICE_EVENT_CLASS_BSD user events - - SL_SOCKET_TX_FAILED_EVENT - - SL_SOCKET_ASYNC_EVENT - - - SL_DEVICE_EVENT_CLASS_NETAPP user events - - SL_NETAPP_EVENT_IPV4_ACQUIRED - - SL_NETAPP_EVENT_IPV6_ACQUIRED - - SL_NETAPP_EVENT_DHCPV4_LEASED - - SL_NETAPP_EVENT_DHCPV4_RELEASED - - SL_NETAPP_EVENT_IP_COLLISION - - SL_NETAPP_EVENT_IPV4_LOST - - SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT - - SL_NETAPP_EVENT_IPV6_LOST - - - \return Zero on success, or a negative value if an error occurred - \par Persistent System Persistent - \sa sl_DeviceEventMaskGet - - \note Belongs to \ref ext_api \n - \warning - \par Example - - - Masking connection/disconnection async events from WLAN class: - \code - sl_DeviceEventMaskSet(SL_DEVICE_EVENT_CLASS_WLAN, (SL_DEVICE_EVENT_BIT(SL_WLAN_EVENT_CONNECT) | SL_DEVICE_EVENT_BIT(SL_WLAN_EVENT_DISCONNECT) ) ); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskSet) -_i16 sl_DeviceEventMaskSet(const _u8 EventClass ,const _u32 Mask); -#endif - -/*! - \brief Get current event mask of the device - - Return the events bit mask from the device. In case event is - masked, the device will not send that event. - - \param[in] EventClass The classification groups that the - mask is referred to. Need to be one of - the following: - - SL_DEVICE_EVENT_CLASS_GLOBAL - - SL_DEVICE_EVENT_CLASS_DEVICE - - SL_DEVICE_EVENT_CLASS_WLAN - - SL_DEVICE_EVENT_CLASS_BSD - - SL_DEVICE_EVENT_CLASS_NETAPP - - SL_DEVICE_EVENT_CLASS_NETCFG - - SL_DEVICE_EVENT_CLASS_FS - - \param[out] pMask Pointer to mask bitmap where the - value should be stored. Bitmasks are the same as in \ref sl_DeviceEventMaskSet - - \return Zero on success, or a negative value if an error occurred - - \sa sl_DeviceEventMaskSet - - \note Belongs to \ref ext_api - - \warning - \par Example - - - Getting an event mask for WLAN class: - \code - _u32 maskWlan; - sl_DeviceEventMaskGet(SL_DEVICE_EVENT_CLASS_WLAN,&maskWlan); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskGet) -_i16 sl_DeviceEventMaskGet(const _u8 EventClass,_u32 *pMask); -#endif - - -/*! - \brief The SimpleLink task entry - - This function must be called from the main loop or from dedicated thread in - the following cases: - - Non-Os Platform - should be called from the mail loop - - Multi Threaded Platform when the user does not implement the external spawn functions - - should be called from dedicated thread allocated to the SimpleLink driver. - In this mode the function never return. - - \par parameters - None - - \return None - \sa - \note Belongs to \ref basic_api - - \warning This function must be called from a thread that is start running before - any call to other SimpleLink API -*/ -#if _SL_INCLUDE_FUNC(sl_Task) -void* sl_Task(void* pEntry); -#endif - - - - -/*! - \brief Setting the internal uart mode - - \param[in] pUartParams Pointer to the uart configuration parameter set: - - baudrate - up to 711 Kbps - - flow control - enable/disable - - comm port - the comm port number - - \return On success zero is returned, otherwise - Failed. - \par Persistent Non- Persistent - \sa - \note Belongs to \ref basic_api - - \warning This function must consider the host uart capability -*/ -#ifdef SL_IF_TYPE_UART -#if _SL_INCLUDE_FUNC(sl_DeviceUartSetMode) -_i16 sl_DeviceUartSetMode(const SlDeviceUartIfParams_t* pUartParams); -#endif -#endif - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __DEVICE_H__ */ - - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/errors.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/errors.h deleted file mode 100755 index a9ab823a168..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/errors.h +++ /dev/null @@ -1,736 +0,0 @@ -/* - * errors.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -#ifndef __ERROR_H__ -#define __ERROR_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - - -#define SL_RET_CODE_OK (0L) /* Success */ - -#define SL_ERROR_GENERAL_DEVICE (-6L) /* General device error */ - -/* BSD SOCKET ERRORS CODES */ - -#define SL_ERROR_BSD_SOC_ERROR (-1L) /* Failure */ -#define SL_ERROR_BSD_EINTR (-4L) /* Interrupted system call */ -#define SL_ERROR_BSD_E2BIG (-7L) /* length too big */ -#define SL_ERROR_BSD_INEXE (-8L) /* socket command in execution */ -#define SL_ERROR_BSD_EBADF (-9L) /* Bad file number */ -#define SL_ERROR_BSD_ENSOCK (-10L) /* The system limit on the total number of open socket, has been reached */ -#define SL_ERROR_BSD_EAGAIN (-11L) /* Try again */ -#define SL_ERROR_BSD_EWOULDBLOCK SL_ERROR_BSD_EAGAIN -#define SL_ERROR_BSD_ENOMEM (-12L) /* Out of memory */ -#define SL_ERROR_BSD_EACCES (-13L) /* Permission denied */ -#define SL_ERROR_BSD_EFAULT (-14L) /* Bad address */ -#define SL_ERROR_BSD_ECLOSE (-15L) /* close socket operation failed to transmit all queued packets */ -#define SL_ERROR_BSD_EALREADY_ENABLED (-21L) /* Transceiver - Transceiver already ON. there could be only one */ -#define SL_ERROR_BSD_EINVAL (-22L) /* Invalid argument */ -#define SL_ERROR_BSD_EAUTO_CONNECT_OR_CONNECTING (-69L) /* Transceiver - During connection, connected or auto mode started */ -#define SL_ERROR_BSD_CONNECTION_PENDING (-72L) /* Transceiver - Device is connected, disconnect first to open transceiver */ -#define SL_ERROR_BSD_EUNSUPPORTED_ROLE (-86L) /* Transceiver - Trying to start when WLAN role is AP or P2P GO */ -#define SL_ERROR_BSD_EDESTADDRREQ (-89L) /* Destination address required */ -#define SL_ERROR_BSD_EPROTOTYPE (-91L) /* Protocol wrong type for socket */ -#define SL_ERROR_BSD_ENOPROTOOPT (-92L) /* Protocol not available */ -#define SL_ERROR_BSD_EPROTONOSUPPORT (-93L) /* Protocol not supported */ -#define SL_ERROR_BSD_ESOCKTNOSUPPORT (-94L) /* Socket type not supported */ -#define SL_ERROR_BSD_EOPNOTSUPP (-95L) /* Operation not supported on transport endpoint */ -#define SL_ERROR_BSD_EAFNOSUPPORT (-97L) /* Address family not supported by protocol */ -#define SL_ERROR_BSD_EADDRINUSE (-98L) /* Address already in use */ -#define SL_ERROR_BSD_EADDRNOTAVAIL (-99L) /* Cannot assign requested address */ -#define SL_ERROR_BSD_ENETUNREACH (-101L) /* Network is unreachable */ -#define SL_ERROR_BSD_ENOBUFS (-105L) /* No buffer space available */ -#define SL_ERROR_BSD_EOBUFF SL_ENOBUFS -#define SL_ERROR_BSD_EISCONN (-106L) /* Transport endpoint is already connected */ -#define SL_ERROR_BSD_ENOTCONN (-107L) /* Transport endpoint is not connected */ -#define SL_ERROR_BSD_ETIMEDOUT (-110L) /* Connection timed out */ -#define SL_ERROR_BSD_ECONNREFUSED (-111L) /* Connection refused */ -#define SL_ERROR_BSD_EALREADY (-114L) /* Non blocking connect in progress, try again */ - -/* ssl tls security start with -300 offset */ -#define SL_ERROR_BSD_ESEC_CLOSE_NOTIFY (-300L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_UNEXPECTED_MESSAGE (-310L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_BAD_RECORD_MAC (-320L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_DECRYPTION_FAILED (-321L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_RECORD_OVERFLOW (-322L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_DECOMPRESSION_FAILURE (-330L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_HANDSHAKE_FAILURE (-340L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_NO_CERTIFICATE (-341L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE (-342L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_UNSUPPORTED_CERTIFICATE (-343L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_CERTIFICATE_REVOKED (-344L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_CERTIFICATE_EXPIRED (-345L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_CERTIFICATE_UNKNOWN (-346L) /* ssl/tls alerts */ - -#define SL_ERROR_BSD_ESEC_ILLEGAL_PARAMETER (-347L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_ACCESS_DENIED (-349L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_DECODE_ERROR (-350L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_DECRYPT_ERROR1 (-351L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_EXPORT_RESTRICTION (-360L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_PROTOCOL_VERSION (-370L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_INSUFFICIENT_SECURITY (-371L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_INTERNAL_ERROR (-380L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_USER_CANCELLED (-390L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_NO_RENEGOTIATION (-400L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_UNSUPPORTED_EXTENSION (-410L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_CERTIFICATE_UNOBTAINABLE (-411L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_UNRECOGNIZED_NAME (-412L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE_STATUS_RESPONSE (-413L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE_HASH_VALUE (-414L) /* ssl/tls alerts */ -/* propriety secure */ -#define SL_ERROR_BSD_ESECGENERAL (-450L) /* error secure level general error */ -#define SL_ERROR_BSD_ESECDECRYPT (-451L) /* error secure level, decrypt recv packet fail */ -#define SL_ERROR_BSD_ESECCLOSED (-452L) /* secure layrer is closed by other size , tcp is still connected */ -#define SL_ERROR_BSD_ESECSNOVERIFY (-453L) /* Connected without server verification */ -#define SL_ERROR_BSD_ESECNOCAFILE (-454L) /* error secure level CA file not found*/ -#define SL_ERROR_BSD_ESECMEMORY (-455L) /* error secure level No memory space available */ -#define SL_ERROR_BSD_ESECBADCAFILE (-456L) /* error secure level bad CA file */ -#define SL_ERROR_BSD_ESECBADCERTFILE (-457L) /* error secure level bad Certificate file */ -#define SL_ERROR_BSD_ESECBADPRIVATEFILE (-458L) /* error secure level bad private file */ -#define SL_ERROR_BSD_ESECBADDHFILE (-459L) /* error secure level bad DH file */ -#define SL_ERROR_BSD_ESECT00MANYSSLOPENED (-460L) /* MAX SSL Sockets are opened */ -#define SL_ERROR_BSD_ESECDATEERROR (-461L) /* connected with certificate date verification error */ -#define SL_ERROR_BSD_ESECHANDSHAKETIMEDOUT (-462L) /* connection timed out due to handshake time */ -#define SL_ERROR_BSD_ESECTXBUFFERNOTEMPTY (-463L) /* cannot start ssl connection while send buffer is full */ -#define SL_ERROR_BSD_ESECRXBUFFERNOTEMPTY (-464L) /* cannot start ssl connection while recv buffer is full */ -#define SL_ERROR_BSD_ESECSSLDURINGHANDSHAKE (-465L) /* cannot use while in hanshaking */ -#define SL_ERROR_BSD_ESECNOTALLOWEDWHENLISTENING (-466L) /* the operation is not allowed when listening, do before listen*/ -#define SL_ERROR_BSD_ESECCERTIFICATEREVOKED (-467L) /* connected but on of the certificates in the chain is revoked */ -#define SL_ERROR_BSD_ESECUNKNOWNROOTCA (-468L) /* connected but the root CA used to validate the peer is unknown */ -#define SL_ERROR_BSD_ESECWRONGPEERCERT (-469L) /* wrong peer cert (server cert) was received while trying to connect to server */ -#define SL_ERROR_BSD_ESECTCPDISCONNECTEDUNCOMPLETERECORD (-470L) /* the other side disconnected the TCP layer and didn't send the whole ssl record */ - -#define SL_ERROR_BSD_ESEC_BUFFER_E (-632L) /* output buffer too small or input too large */ -#define SL_ERROR_BSD_ESEC_ALGO_ID_E (-633L) /* setting algo id error */ -#define SL_ERROR_BSD_ESEC_PUBLIC_KEY_E (-634L) /* setting public key error */ -#define SL_ERROR_BSD_ESEC_DATE_E (-635L) /* setting date validity error */ -#define SL_ERROR_BSD_ESEC_SUBJECT_E (-636L) /* setting subject name error */ -#define SL_ERROR_BSD_ESEC_ISSUER_E (-637L) /* setting issuer name error */ -#define SL_ERROR_BSD_ESEC_CA_TRUE_E (-638L) /* setting CA basic constraint true error */ -#define SL_ERROR_BSD_ESEC_EXTENSIONS_E (-639L) /* setting extensions error */ -#define SL_ERROR_BSD_ESEC_ASN_PARSE_E (-640L) /* ASN parsing error, invalid input */ -#define SL_ERROR_BSD_ESEC_ASN_VERSION_E (-641L) /* ASN version error, invalid number */ -#define SL_ERROR_BSD_ESEC_ASN_GETINT_E (-642L) /* ASN get big int error, invalid data */ -#define SL_ERROR_BSD_ESEC_ASN_RSA_KEY_E (-643L) /* ASN key init error, invalid input */ -#define SL_ERROR_BSD_ESEC_ASN_OBJECT_ID_E (-644L) /* ASN object id error, invalid id */ -#define SL_ERROR_BSD_ESEC_ASN_TAG_NULL_E (-645L) /* ASN tag error, not null */ -#define SL_ERROR_BSD_ESEC_ASN_EXPECT_0_E (-646L) /* ASN expect error, not zero */ -#define SL_ERROR_BSD_ESEC_ASN_BITSTR_E (-647L) /* ASN bit string error, wrong id */ -#define SL_ERROR_BSD_ESEC_ASN_UNKNOWN_OID_E (-648L) /* ASN oid error, unknown sum id */ -#define SL_ERROR_BSD_ESEC_ASN_DATE_SZ_E (-649L) /* ASN date error, bad size */ -#define SL_ERROR_BSD_ESEC_ASN_BEFORE_DATE_E (-650L) /* ASN date error, current date before */ -#define SL_ERROR_BSD_ESEC_ASN_AFTER_DATE_E (-651L) /* ASN date error, current date after */ -#define SL_ERROR_BSD_ESEC_ASN_SIG_OID_E (-652L) /* ASN signature error, mismatched oid */ -#define SL_ERROR_BSD_ESEC_ASN_TIME_E (-653L) /* ASN time error, unknown time type */ -#define SL_ERROR_BSD_ESEC_ASN_INPUT_E (-654L) /* ASN input error, not enough data */ -#define SL_ERROR_BSD_ESEC_ASN_SIG_CONFIRM_E (-655L) /* ASN sig error, confirm failure */ -#define SL_ERROR_BSD_ESEC_ASN_SIG_HASH_E (-656L) /* ASN sig error, unsupported hash type */ -#define SL_ERROR_BSD_ESEC_ASN_SIG_KEY_E (-657L) /* ASN sig error, unsupported key type */ -#define SL_ERROR_BSD_ESEC_ASN_DH_KEY_E (-658L) /* ASN key init error, invalid input */ -#define SL_ERROR_BSD_ESEC_ASN_NTRU_KEY_E (-659L) /* ASN ntru key decode error, invalid input */ -#define SL_ERROR_BSD_ESEC_ASN_CRIT_EXT_E (-660L) /* ASN unsupported critical extension */ -#define SL_ERROR_BSD_ESEC_ECC_BAD_ARG_E (-670L) /* ECC input argument of wrong type */ -#define SL_ERROR_BSD_ESEC_ASN_ECC_KEY_E (-671L) /* ASN ECC bad input */ -#define SL_ERROR_BSD_ESEC_ECC_CURVE_OID_E (-672L) /* Unsupported ECC OID curve type */ -#define SL_ERROR_BSD_ESEC_BAD_FUNC_ARG (-673L) /* Bad function argument provided */ -#define SL_ERROR_BSD_ESEC_NOT_COMPILED_IN (-674L) /* Feature not compiled in */ -#define SL_ERROR_BSD_ESEC_UNICODE_SIZE_E (-675L) /* Unicode password too big */ -#define SL_ERROR_BSD_ESEC_NO_PASSWORD (-676L) /* no password provided by user */ -#define SL_ERROR_BSD_ESEC_ALT_NAME_E (-677L) /* alt name size problem, too big */ -#define SL_ERROR_BSD_ESEC_ASN_NO_SIGNER_E (-688L) /* ASN no signer to confirm failure */ -#define SL_ERROR_BSD_ESEC_ASN_CRL_CONFIRM_E (-689L) /* ASN CRL signature confirm failure */ -#define SL_ERROR_BSD_ESEC_ASN_CRL_NO_SIGNER_E (-690L) /* ASN CRL no signer to confirm failure */ -#define SL_ERROR_BSD_ESEC_ASN_OCSP_CONFIRM_E (-691L) /* ASN OCSP signature confirm failure */ -#define SL_ERROR_BSD_ESEC_VERIFY_FINISHED_ERROR (-704L) /* verify problem on finished */ -#define SL_ERROR_BSD_ESEC_VERIFY_MAC_ERROR (-705L) /* verify mac problem */ -#define SL_ERROR_BSD_ESEC_PARSE_ERROR (-706L) /* parse error on header */ -#define SL_ERROR_BSD_ESEC_UNKNOWN_HANDSHAKE_TYPE (-707L) /* weird handshake type */ -#define SL_ERROR_BSD_ESEC_SOCKET_ERROR_E (-708L) /* error state on socket */ -#define SL_ERROR_BSD_ESEC_SOCKET_NODATA (-709L) /* expected data, not there */ -#define SL_ERROR_BSD_ESEC_INCOMPLETE_DATA (-710L) /* don't have enough data to complete task */ -#define SL_ERROR_BSD_ESEC_UNKNOWN_RECORD_TYPE (-711L) /* unknown type in record hdr */ -#define SL_ERROR_BSD_ESEC_INNER_DECRYPT_ERROR (-712L) /* error during decryption */ -#define SL_ERROR_BSD_ESEC_FATAL_ERROR (-713L) /* recvd alert fatal error */ -#define SL_ERROR_BSD_ESEC_ENCRYPT_ERROR (-714L) /* error during encryption */ -#define SL_ERROR_BSD_ESEC_FREAD_ERROR (-715L) /* fread problem */ -#define SL_ERROR_BSD_ESEC_NO_PEER_KEY (-716L) /* need peer's key */ -#define SL_ERROR_BSD_ESEC_NO_PRIVATE_KEY (-717L) /* need the private key */ -#define SL_ERROR_BSD_ESEC_RSA_PRIVATE_ERROR (-718L) /* error during rsa priv op */ -#define SL_ERROR_BSD_ESEC_NO_DH_PARAMS (-719L) /* server missing DH params */ -#define SL_ERROR_BSD_ESEC_BUILD_MSG_ERROR (-720L) /* build message failure */ -#define SL_ERROR_BSD_ESEC_BAD_HELLO (-721L) /* client hello malformed */ -#define SL_ERROR_BSD_ESEC_DOMAIN_NAME_MISMATCH (-722L) /* peer subject name mismatch */ -#define SL_ERROR_BSD_ESEC_WANT_READ (-723L) /* want read, call again */ -#define SL_ERROR_BSD_ESEC_NOT_READY_ERROR (-724L) /* handshake layer not ready */ -#define SL_ERROR_BSD_ESEC_PMS_VERSION_ERROR (-725L) /* pre m secret version error */ -#define SL_ERROR_BSD_ESEC_WANT_WRITE (-727L) /* want write, call again */ -#define SL_ERROR_BSD_ESEC_BUFFER_ERROR (-728L) /* malformed buffer input */ -#define SL_ERROR_BSD_ESEC_VERIFY_CERT_ERROR (-729L) /* verify cert error */ -#define SL_ERROR_BSD_ESEC_VERIFY_SIGN_ERROR (-730L) /* verify sign error */ -#define SL_ERROR_BSD_ESEC_LENGTH_ERROR (-741L) /* record layer length error */ -#define SL_ERROR_BSD_ESEC_PEER_KEY_ERROR (-742L) /* can't decode peer key */ -#define SL_ERROR_BSD_ESEC_ZERO_RETURN (-743L) /* peer sent close notify */ -#define SL_ERROR_BSD_ESEC_SIDE_ERROR (-744L) /* wrong client/server type */ -#define SL_ERROR_BSD_ESEC_NO_PEER_CERT (-745L) /* peer didn't send key */ -#define SL_ERROR_BSD_ESEC_ECC_CURVETYPE_ERROR (-750L) /* Bad ECC Curve Type */ -#define SL_ERROR_BSD_ESEC_ECC_CURVE_ERROR (-751L) /* Bad ECC Curve */ -#define SL_ERROR_BSD_ESEC_ECC_PEERKEY_ERROR (-752L) /* Bad Peer ECC Key */ -#define SL_ERROR_BSD_ESEC_ECC_MAKEKEY_ERROR (-753L) /* Bad Make ECC Key */ -#define SL_ERROR_BSD_ESEC_ECC_EXPORT_ERROR (-754L) /* Bad ECC Export Key */ -#define SL_ERROR_BSD_ESEC_ECC_SHARED_ERROR (-755L) /* Bad ECC Shared Secret */ -#define SL_ERROR_BSD_ESEC_NOT_CA_ERROR (-757L) /* Not a CA cert error */ -#define SL_ERROR_BSD_ESEC_BAD_PATH_ERROR (-758L) /* Bad path for opendir */ -#define SL_ERROR_BSD_ESEC_BAD_CERT_MANAGER_ERROR (-759L) /* Bad Cert Manager */ -#define SL_ERROR_BSD_ESEC_OCSP_CERT_REVOKED (-760L) /* OCSP Certificate revoked */ -#define SL_ERROR_BSD_ESEC_CRL_CERT_REVOKED (-761L) /* CRL Certificate revoked */ -#define SL_ERROR_BSD_ESEC_CRL_MISSING (-762L) /* CRL Not loaded */ -#define SL_ERROR_BSD_ESEC_MONITOR_RUNNING_E (-763L) /* CRL Monitor already running */ -#define SL_ERROR_BSD_ESEC_THREAD_CREATE_E (-764L) /* Thread Create Error */ -#define SL_ERROR_BSD_ESEC_OCSP_NEED_URL (-765L) /* OCSP need an URL for lookup */ -#define SL_ERROR_BSD_ESEC_OCSP_CERT_UNKNOWN (-766L) /* OCSP responder doesn't know */ -#define SL_ERROR_BSD_ESEC_OCSP_LOOKUP_FAIL (-767L) /* OCSP lookup not successful */ -#define SL_ERROR_BSD_ESEC_MAX_CHAIN_ERROR (-768L) /* max chain depth exceeded */ -#define SL_ERROR_BSD_ESEC_NO_PEER_VERIFY (-778L) /* Need peer cert verify Error */ -#define SL_ERROR_BSD_ESEC_UNSUPPORTED_SUITE (-790L) /* unsupported cipher suite */ -#define SL_ERROR_BSD_ESEC_MATCH_SUITE_ERROR (-791L) /* can't match cipher suite */ - - -/* WLAN ERRORS CODES*/ -#define SL_ERROR_WLAN_KEY_ERROR (-2049L) -#define SL_ERROR_WLAN_INVALID_ROLE (-2050L) -#define SL_ERROR_WLAN_PREFERRED_NETWORKS_FILE_LOAD_FAILED (-2051L) -#define SL_ERROR_WLAN_CANNOT_CONFIG_SCAN_DURING_PROVISIONING (-2052L) -#define SL_ERROR_WLAN_INVALID_SECURITY_TYPE (-2054L) -#define SL_ERROR_WLAN_PASSPHRASE_TOO_LONG (-2055L) -#define SL_ERROR_WLAN_EAP_WRONG_METHOD (-2057L) -#define SL_ERROR_WLAN_PASSWORD_ERROR (-2058L) -#define SL_ERROR_WLAN_EAP_ANONYMOUS_LEN_ERROR (-2059L) -#define SL_ERROR_WLAN_SSID_LEN_ERROR (-2060L) -#define SL_ERROR_WLAN_USER_ID_LEN_ERROR (-2061L) -#define SL_ERROR_WLAN_PREFERRED_NETWORK_LIST_FULL (-2062L) -#define SL_ERROR_WLAN_PREFERRED_NETWORKS_FILE_WRITE_FAILED (-2063L) -#define SL_ERROR_WLAN_ILLEGAL_WEP_KEY_INDEX (-2064L) -#define SL_ERROR_WLAN_INVALID_DWELL_TIME_VALUES (-2065L) -#define SL_ERROR_WLAN_INVALID_POLICY_TYPE (-2066L) -#define SL_ERROR_WLAN_PM_POLICY_INVALID_OPTION (-2067L) -#define SL_ERROR_WLAN_PM_POLICY_INVALID_PARAMS (-2068L) -#define SL_ERROR_WLAN_WIFI_NOT_CONNECTED (-2069L) -#define SL_ERROR_WLAN_ILLEGAL_CHANNEL (-2070L) -#define SL_ERROR_WLAN_WIFI_ALREADY_DISCONNECTED (-2071L) -#define SL_ERROR_WLAN_TRANSCEIVER_ENABLED (-2072L) -#define SL_ERROR_WLAN_GET_NETWORK_LIST_EAGAIN (-2073L) -#define SL_ERROR_WLAN_GET_PROFILE_INVALID_INDEX (-2074L) -#define SL_ERROR_WLAN_FAST_CONN_DATA_INVALID (-2075L) -#define SL_ERROR_WLAN_NO_FREE_PROFILE (-2076L) -#define SL_ERROR_WLAN_AP_SCAN_INTERVAL_TOO_LOW (-2077L) -#define SL_ERROR_WLAN_SCAN_POLICY_INVALID_PARAMS (-2078L) - -#define SL_RXFL_OK (0L) /* O.K */ -#define SL_ERROR_RXFL_RANGE_COMPARE_PARAMS_ARE_INVALID (-2079L) -#define SL_ERROR_RXFL_RXFL_INVALID_PATTERN_LENGTH (-2080L) /* requested length for L1/L4 payload matching must not exceed 16 bytes */ -#define SL_ERROR_RXFL_ACTION_USER_EVENT_ID_TOO_BIG (-2081L) /* user action id for host event must not exceed SL_WLAN_RX_FILTER_MAX_USER_EVENT_ID */ -#define SL_ERROR_RXFL_OFFSET_TOO_BIG (-2082L) /* requested offset for L1/L4 payload matching must not exceed 1535 bytes */ -#define SL_ERROR_RXFL_STAT_UNSUPPORTED (-2083L) /* get rx filters statistics not supported */ -#define SL_ERROR_RXFL_INVALID_FILTER_ARG_UPDATE (-2084L) /* invalid filter args request */ -#define SL_ERROR_RXFL_INVALID_SYSTEM_STATE_TRIGGER_FOR_FILTER_TYPE (-2085L) /* system state not supported for this filter type */ -#define SL_ERROR_RXFL_INVALID_FUNC_ID_FOR_FILTER_TYPE (-2086L) /* function id not supported for this filter type */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_3 (-2087L) /* filter parent doesn't exist */ -#define SL_ERROR_RXFL_OUTPUT_OR_INPUT_BUFFER_LENGTH_TOO_SMALL (-2088L) /* ! The output buffer length is smaller than required for that operation */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_SOFTWARE_FILTER_NOT_FIT (-2089L) /* Node filter can't be child of software filter and vice_versa */ -#define SL_ERROR_RXFL_DEPENDENCY_IS_NOT_PERSISTENT (-2090L) /* Dependency filter is not persistent */ -#define SL_ERROR_RXFL_RXFL_ALLOCATION_PROBLEM (-2091L) -#define SL_ERROR_RXFL_SYSTEM_STATE_NOT_SUPPORTED_FOR_THIS_FILTER (-2092L) /* System state is not supported */ -#define SL_ERROR_RXFL_TRIGGER_USE_REG5_TO_REG8 (-2093L) /* Only counters 5 - 8 are allowed, for Tigger */ -#define SL_ERROR_RXFL_TRIGGER_USE_REG1_TO_REG4 (-2094L) /* Only counters 1 - 4 are allowed, for trigger */ -#define SL_ERROR_RXFL_ACTION_USE_REG5_TO_REG8 (-2095L) /* Only counters 5 - 8 are allowed, for action */ -#define SL_ERROR_RXFL_ACTION_USE_REG1_TO_REG4 (-2096L) /* Only counters 1 - 4 are allowed, for action */ -#define SL_ERROR_RXFL_FIELD_SUPPORT_ONLY_EQUAL_AND_NOTEQUAL (-2097L) /* Rule compare function Id is out of range */ -#define SL_ERROR_RXFL_WRONG_MULTICAST_BROADCAST_ADDRESS (-2098L) /* The address should be of type mutlicast or broadcast */ -#define SL_ERROR_RXFL_THE_FILTER_IS_NOT_OF_HEADER_TYPE (-2099L) /* The filter should be of header type */ -#define SL_ERROR_RXFL_WRONG_COMPARE_FUNC_FOR_BROADCAST_ADDRESS (-2100L) /* The compare funcion is not suitable for broadcast address */ -#define SL_ERROR_RXFL_WRONG_MULTICAST_ADDRESS (-2101L) /* The address should be of muticast type */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_IS_NOT_PERSISTENT (-2102L) /* The dependency filter is not persistent */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_IS_NOT_ENABLED (-2103L) /* The dependency filter is not enabled */ -#define SL_ERROR_RXFL_FILTER_HAS_CHILDS (-2104L) /* The filter has childs and can't be removed */ -#define SL_ERROR_RXFL_CHILD_IS_ENABLED (-2105L) /* Can't disable filter while the child is enabled */ -#define SL_ERROR_RXFL_DEPENDENCY_IS_DISABLED (-2106L) /* Can't enable filetr in case its depndency filter is disabled */ -#define SL_ERROR_RXFL_MAC_SEND_MATCHDB_FAILED (-2107L) -#define SL_ERROR_RXFL_MAC_SEND_ARG_DB_FAILED (-2108L) -#define SL_ERROR_RXFL_MAC_SEND_NODEDB_FAILED (-2109L) -#define SL_ERROR_RXFL_MAC_OPERTATION_RESUME_FAILED (-2110L) -#define SL_ERROR_RXFL_MAC_OPERTATION_HALT_FAILED (-2111L) -#define SL_ERROR_RXFL_NUMBER_OF_CONNECTION_POINTS_EXCEEDED (-2112L) /* Number of connection points exceeded */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_DEPENDENCY_ACTION_IS_DROP (-2113L) /* The dependent filter has Drop action, thus the filter can't be created */ -#define SL_ERROR_RXFL_FILTER_DO_NOT_EXISTS (-2114L) /* The filter doesn't exists */ -#define SL_ERROR_RXFL_DEPEDENCY_NOT_ON_THE_SAME_LAYER (-2115L) /* The filter and its dependency must be on the same layer */ -#define SL_ERROR_RXFL_NUMBER_OF_ARGS_EXCEEDED (-2116L) /* Number of arguments excceded */ -#define SL_ERROR_RXFL_ACTION_NO_REG_NUMBER (-2117L) /* Action require counter number */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_LAYER_DO_NOT_FIT (-2118L) /* the filter and its dependency should be from the same layer */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_SYSTEM_STATE_DO_NOT_FIT (-2119L) /* The filter and its dependency system state don't fit */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_2 (-2120L) /* The parent filter don't exist */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_1 (-2121L) /* The parent filter is null */ -#define SL_ERROR_RXFL_RULE_HEADER_ACTION_TYPE_NOT_SUPPORTED (-2122L) /* The action type is not supported */ -#define SL_ERROR_RXFL_RULE_HEADER_TRIGGER_COMPARE_FUNC_OUT_OF_RANGE (-2123L) /* The Trigger comparision function is out of range */ -#define SL_ERROR_RXFL_RULE_HEADER_TRIGGER_OUT_OF_RANGE (-2124L) /* The Trigger is out of range */ -#define SL_ERROR_RXFL_RULE_HEADER_COMPARE_FUNC_OUT_OF_RANGE (-2125L) /* The rule compare function is out of range */ -#define SL_ERROR_RXFL_FRAME_TYPE_NOT_SUPPORTED (-2126L) /* ASCII frame type string is illegal */ -#define SL_ERROR_RXFL_RULE_FIELD_ID_NOT_SUPPORTED (-2127L) /* Rule field ID is out of range */ -#define SL_ERROR_RXFL_RULE_HEADER_FIELD_ID_ASCII_NOT_SUPPORTED (-2128L) /* This ASCII field ID is not supported */ -#define SL_ERROR_RXFL_RULE_HEADER_NOT_SUPPORTED (-2129L) /* The header rule is not supported on current release */ -#define SL_ERROR_RXFL_RULE_HEADER_OUT_OF_RANGE (-2130L) /* The header rule is out of range */ -#define SL_ERROR_RXFL_RULE_HEADER_COMBINATION_OPERATOR_OUT_OF_RANGE (-2131L) /* Combination function Id is out of ramge */ -#define SL_ERROR_RXFL_RULE_HEADER_FIELD_ID_OUT_OF_RANGE (-2132L) /* rule field Id is out of range */ -#define SL_ERROR_RXFL_UPDATE_NOT_SUPPORTED (-2133L) /* Update not supported */ -#define SL_ERROR_RXFL_NO_FILTER_DATABASE_ALLOCATE (-2134L) -#define SL_ERROR_RXFL_ALLOCATION_FOR_GLOBALS_STRUCTURE_FAILED (-2135L) -#define SL_ERROR_RXFL_ALLOCATION_FOR_DB_NODE_FAILED (-2136L) -#define SL_ERROR_RXFL_READ_FILE_FILTER_ID_ILLEGAL (-2137L) -#define SL_ERROR_RXFL_READ_FILE_NUMBER_OF_FILTER_FAILED (-2138L) -#define SL_ERROR_RXFL_READ_FILE_FAILED (-2139L) -#define SL_ERROR_RXFL_NO_FILTERS_ARE_DEFINED (-2140L) /* No filters are defined in the system */ -#define SL_ERROR_RXFL_NUMBER_OF_FILTER_EXCEEDED (-2141L) /* Number of max filters excceded */ -#define SL_ERROR_RXFL_BAD_FILE_MODE (-2142L) -#define SL_ERROR_RXFL_FAILED_READ_NVFILE (-2143L) -#define SL_ERROR_RXFL_FAILED_INIT_STORAGE (-2144L) -#define SL_ERROR_RXFL_CONTINUE_WRITE_MUST_BE_MOD_4 (-2145L) -#define SL_ERROR_RXFL_FAILED_LOAD_FILE (-2146L) -#define SL_ERROR_RXFL_INVALID_HANDLE (-2147L) -#define SL_ERROR_RXFL_FAILED_TO_WRITE (-2148L) -#define SL_ERROR_RXFL_OFFSET_OUT_OF_RANGE (-2149L) -#define SL_ERROR_RXFL_ALLOC (-2150L) -#define SL_ERROR_RXFL_READ_DATA_LENGTH (-2151L) -#define SL_ERROR_RXFL_INVALID_FILE_ID (-2152L) -#define SL_ERROR_RXFL_FILE_FILTERS_NOT_EXISTS (-2153L) -#define SL_ERROR_RXFL_FILE_ALREADY_IN_USE (-2154L) -#define SL_ERROR_RXFL_INVALID_ARGS (-2155L) -#define SL_ERROR_RXFL_FAILED_TO_CREATE_FILE (-2156L) -#define SL_ERROR_RXFL_FS_ALREADY_LOADED (-2157L) -#define SL_ERROR_RXFL_UNKNOWN (-2158L) -#define SL_ERROR_RXFL_FAILED_TO_CREATE_LOCK_OBJ (-2159L) -#define SL_ERROR_RXFL_DEVICE_NOT_LOADED (-2160L) -#define SL_ERROR_RXFL_INVALID_MAGIC_NUM (-2161L) -#define SL_ERROR_RXFL_FAILED_TO_READ (-2162L) -#define SL_ERROR_RXFL_NOT_SUPPORTED (-2163L) -#define SL_ERROR_WLAN_INVALID_COUNTRY_CODE (-2164L) -#define SL_ERROR_WLAN_NVMEM_ACCESS_FAILED (-2165L) -#define SL_ERROR_WLAN_OLD_FILE_VERSION (-2166L) -#define SL_ERROR_WLAN_TX_POWER_OUT_OF_RANGE (-2167L) -#define SL_ERROR_WLAN_INVALID_AP_PASSWORD_LENGTH (-2168L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_PROVISIONING_ALREADY_STARTED (-2169L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_HTTP_SERVER_DISABLED (-2170L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_PROFILE_LIST_FULL (-2171L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_INVALID_PARAM (-2172L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_GENERAL_ERROR (-2173L) -#define SL_ERROR_WLAN_MULTICAST_EXCEED_MAX_ADDR (-2174L) -#define SL_ERROR_WLAN_MULTICAST_INVAL_ADDR (-2175L) -#define SL_ERROR_WLAN_AP_SCAN_INTERVAL_TOO_SHORT (-2176L) -#define SL_ERROR_WLAN_PROVISIONING_CMD_NOT_EXPECTED (-2177L) - - -#define SL_ERROR_WLAN_AP_ACCESS_LIST_NO_ADDRESS_TO_DELETE (-2178L) /* List is empty, no address to delete */ -#define SL_ERROR_WLAN_AP_ACCESS_LIST_FULL (-2179L) /* access list is full */ -#define SL_ERROR_WLAN_AP_ACCESS_LIST_DISABLED (-2180L) /* access list is disabled */ -#define SL_ERROR_WLAN_AP_ACCESS_LIST_MODE_NOT_SUPPORTED (-2181L) /* Trying to switch to unsupported mode */ -#define SL_ERROR_WLAN_AP_STA_NOT_FOUND (-2182L) /* trying to disconnect station which is not connected */ - - -/* DEVICE ERRORS CODES*/ -#define SL_ERROR_SUPPLICANT_ERROR (-4097L) -#define SL_ERROR_HOSTAPD_INIT_FAIL (-4098L) -#define SL_ERROR_HOSTAPD_INIT_IF_FAIL (-4099L) -#define SL_ERROR_WLAN_DRV_INIT_FAIL (-4100L) -#define SL_ERROR_FS_FILE_TABLE_LOAD_FAILED (-4102L) /* init file system failed */ -#define SL_ERROR_MDNS_ENABLE_FAIL (-4103L) /* mDNS enable failed */ -#define SL_ERROR_ROLE_STA_ERR (-4107L) /* Failure to load MAC/PHY in STA role */ -#define SL_ERROR_ROLE_AP_ERR (-4108L) /* Failure to load MAC/PHY in AP role */ -#define SL_ERROR_ROLE_P2P_ERR (-4109L) /* Failure to load MAC/PHY in P2P role */ -#define SL_ERROR_CALIB_FAIL (-4110L) /* Failure of calibration */ -#define SL_ERROR_FS_CORRUPTED_ERR (-4111L) /* FS is corrupted, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SL_ERROR_FS_ALERT_ERR (-4112L) /* Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SL_ERROR_RESTORE_IMAGE_COMPLETE (-4113L) /* Return to factory image completed, perform reset */ -#define SL_ERROR_UNKNOWN_ERR (-4114L) -#define SL_ERROR_GENERAL_ERR (-4115L) /* General error during init */ -#define SL_ERROR_WRONG_ROLE (-4116L) -#define SL_ERROR_INCOMPLETE_PROGRAMMING (-4117L) /* Error during programming, Program new image should be invoked (see sl_FsProgram) */ - - -#define SL_ERROR_PENDING_TXRX_STOP_TIMEOUT_EXP (-4118L) /* Timeout expired before completing all TX\RX */ -#define SL_ERROR_PENDING_TXRX_NO_TIMEOUT (-4119L) /* No Timeout , still have pending TX\RX */ -#define SL_ERROR_INVALID_PERSISTENT_CONFIGURATION (-4120L) /* persistency configuration can only be set to 0 (disabled) or 1 (enabled) */ - -/* NETAPP ERRORS CODES*/ -#define SL_ERROR_MDNS_CREATE_FAIL (-6145L) /* mDNS create failed */ -#define SL_ERROR_DEVICE_NAME_LEN_ERR (-6146L) /* Set Dev name error codes */ -#define SL_ERROR_DEVICE_NAME_INVALID (-6147L) /* Set Dev name error codes */ -#define SL_ERROR_DOMAIN_NAME_LEN_ERR (-6148L) /* Set domain name error codes */ -#define SL_ERROR_DOMAIN_NAME_INVALID (-6149L) /* Set domain name error codes */ -#define SL_ERROR_NET_APP_DNS_QUERY_NO_RESPONSE (-6150L) /* DNS query failed, no response */ -#define SL_ERROR_NET_APP_DNS_ERROR (-6151L) /* DNS internal error */ -#define SL_ERROR_NET_APP_DNS_NO_SERVER (-6152L) /* No DNS server was specified */ -#define SL_ERROR_NET_APP_DNS_TIMEOUTR (-6153L) /* mDNS parameters error */ -#define SL_ERROR_NET_APP_DNS_QUERY_FAILED (-6154L) /* DNS query failed; no DNS server sent an 'answer' */ -#define SL_ERROR_NET_APP_DNS_BAD_ADDRESS_ERROR (-6155L) /* Improperly formatted IPv4 or IPv6 address */ -#define SL_ERROR_NET_APP_DNS_SIZE_ERROR (-6156L) /* DNS destination size is too small */ -#define SL_ERROR_NET_APP_DNS_MALFORMED_PACKET (-6157L) /* Improperly formed or corrupted DNS packet received */ -#define SL_ERROR_NET_APP_DNS_BAD_ID_ERROR (-6158L) /* DNS packet from server does not match query ID */ -#define SL_ERROR_NET_APP_DNS_PARAM_ERROR (-6159L) /* Invalid params */ -#define SL_ERROR_NET_APP_DNS_SERVER_NOT_FOUND (-6160L) /* Server not found in Client list of DNS servers */ -#define SL_ERROR_NET_APP_DNS_PACKET_CREATE_ERROR (-6161L) /* Error creating DNS packet */ -#define SL_ERROR_NET_APP_DNS_EMPTY_DNS_SERVER_LIST (-6162L) /* DNS Client's list of DNS servers is empty */ -#define SL_ERROR_NET_APP_DNS_SERVER_AUTH_ERROR (-6163L) /* Server not able to authenticate answer/authority data */ -#define SL_ERROR_NET_APP_DNS_ZERO_GATEWAY_IP_ADDRESS (-6164L) /* DNS Client IP instance has a zero gateway IP address */ -#define SL_ERROR_NET_APP_DNS_MISMATCHED_RESPONSE (-6165L) /* Server response type does not match the query request */ -#define SL_ERROR_NET_APP_DNS_DUPLICATE_ENTRY (-6166L) /* Duplicate entry exists in DNS server table */ -#define SL_ERROR_NET_APP_DNS_RETRY_A_QUERY (-6167L) /* SOA status returned; web site only exists as IPv4 */ -#define SL_ERROR_NET_APP_DNS_INVALID_ADDRESS_TYPE (-6168L) /* IP address type (e.g. IPv6L) not supported */ -#define SL_ERROR_NET_APP_DNS_IPV6_NOT_SUPPORTED (-6169L) /* IPv6 disabled */ -#define SL_ERROR_NET_APP_DNS_NEED_MORE_RECORD_BUFFER (-6170L) /* The buffer size is not enough. */ -#define SL_ERROR_NET_APP_MDNS_ERROR (-6171L) /* MDNS internal error. */ -#define SL_ERROR_NET_APP_MDNS_PARAM_ERROR (-6172L) /* MDNS parameters error. */ -#define SL_ERROR_NET_APP_MDNS_CACHE_ERROR (-6173L) /* The Cache size is not enough. */ -#define SL_ERROR_NET_APP_MDNS_UNSUPPORTED_TYPE (-6174L) /* The unsupported resource record type. */ -#define SL_ERROR_NET_APP_MDNS_DATA_SIZE_ERROR (-6175L) /* The data size is too big. */ -#define SL_ERROR_NET_APP_MDNS_AUTH_ERROR (-6176L) /* Attempting to parse too large a data. */ -#define SL_ERROR_NET_APP_MDNS_PACKET_ERROR (-6177L) /* The packet can not add the resource record. */ -#define SL_ERROR_NET_APP_MDNS_DEST_ADDRESS_ERROR (-6178L) /* The destination address error. */ -#define SL_ERROR_NET_APP_MDNS_UDP_PORT_ERROR (-6179L) /* The udp port error. */ -#define SL_ERROR_NET_APP_MDNS_NOT_LOCAL_LINK (-6180L) /* The message that not originate from the local link. */ -#define SL_ERROR_NET_APP_MDNS_EXCEED_MAX_LABEL (-6181L) /* The data exceed the max laber size. */ -#define SL_ERROR_NET_APP_MDNS_EXIST_UNIQUE_RR (-6182L) /* At least one Unqiue record in the cache. */ -#define SL_ERROR_NET_APP_MDNS_EXIST_ANSWER (-6183L) /* At least one answer record in the cache. */ -#define SL_ERROR_NET_APP_MDNS_EXIST_SAME_QUERY (-6184L) /* Exist the same query. */ -#define SL_ERROR_NET_APP_MDNS_DUPLICATE_SERVICE (-6185L) /* Duplicate service. */ -#define SL_ERROR_NET_APP_MDNS_NO_ANSWER (-6186L) /* No response for one-shot query. */ -#define SL_ERROR_NET_APP_MDNS_NO_KNOWN_ANSWER (-6187L) /* No known answer for query. */ -#define SL_ERROR_NET_APP_MDNS_NAME_MISMATCH (-6188L) /* The name mismatch. */ -#define SL_ERROR_NET_APP_MDNS_NOT_STARTED (-6189L) /* MDNS does not start. */ -#define SL_ERROR_NET_APP_MDNS_HOST_NAME_ERROR (-6190L) /* MDNS host name error. */ -#define SL_ERROR_NET_APP_MDNS_NO_MORE_ENTRIES (-6191L) /* No more entries be found. */ -#define SL_ERROR_NET_APP_MDNS_SERVICE_TYPE_MISMATCH (-6192L) /* The service type mismatch */ -#define SL_ERROR_NET_APP_MDNS_LOOKUP_INDEX_ERROR (-6193L) /* Index is bigger than number of services. */ -#define SL_ERROR_NET_APP_MDNS_MAX_SERVICES_ERROR (-6194L) -#define SL_ERROR_NET_APP_MDNS_IDENTICAL_SERVICES_ERROR (-6195L) -#define SL_ERROR_NET_APP_MDNS_EXISTED_SERVICE_ERROR (-6196L) -#define SL_ERROR_NET_APP_MDNS_ERROR_SERVICE_NAME_ERROR (-6197L) -#define SL_ERROR_NET_APP_MDNS_RX_PACKET_ALLOCATION_ERROR (-6198L) -#define SL_ERROR_NET_APP_MDNS_BUFFER_SIZE_ERROR (-6199L) -#define SL_ERROR_NET_APP_MDNS_NET_APP_SET_ERROR (-6200L) -#define SL_ERROR_NET_APP_MDNS_GET_SERVICE_LIST_FLAG_ERROR (-6201L) -#define SL_ERROR_NET_APP_MDNS_MDNS_NO_CONFIGURATION_ERROR (-6202L) -#define SL_ERROR_NET_APP_MDNS_STATUS_ERROR (-6203L) -#define SL_ERROR_NET_APP_ENOBUFS (-6204L) -#define SL_ERROR_NET_APP_DNS_IPV6_REQ_BUT_IPV6_DISABLED (-6205L) /* trying to issue ipv6 DNS request but ipv6 is disabled */ -#define SL_ERROR_NET_APP_DNS_INVALID_FAMILY_TYPE (-6206L) /* Family type is not ipv4 and not ipv6 */ -#define SL_ERROR_NET_APP_DNS_REQ_TOO_BIG (-6207L) /* DNS request size is too big */ -#define SL_ERROR_NET_APP_DNS_ALLOC_ERROR (-6208L) /* Allocation error */ -#define SL_ERROR_NET_APP_DNS_EXECUTION_ERROR (-6209L) /* Execution error */ -#define SL_ERROR_NET_APP_P2P_ROLE_IS_NOT_CONFIGURED (-6210L) /* role p2p is not configured yet, should be CL or GO in order to execute command */ -#define SL_ERROR_NET_APP_INCORECT_ROLE_FOR_APP (-6211L) /* incorrect role for specific application */ -#define SL_ERROR_NET_APP_INCORECT_APP_MASK (-6212L) /* mask does not match any app */ -#define SL_ERROR_NET_APP_MDNS_ALREADY_STARTED (-6213L) /* mdns application already started */ -#define SL_ERROR_NET_APP_HTTP_SERVER_ALREADY_STARTED (-6214L) /* http server application already started */ - -#define SL_ERROR_NET_APP_HTTP_GENERAL_ERROR (-6216L) /* New error - Http handle request failed */ -#define SL_ERROR_NET_APP_HTTP_INVALID_TIMEOUT (-6217L) /* New error - Http timeout invalid argument */ -#define SL_ERROR_NET_APP_INVALID_URN_LENGTH (-6218L) /* invalid URN length */ -#define SL_ERROR_NET_APP_RX_BUFFER_LENGTH (-6219L) /* size of the requested services is smaller than size of the user buffer */ - -/* NETCFG ERRORS CODES*/ -#define SL_ERROR_STATIC_ADDR_SUBNET_ERROR (-8193L) -#define SL_ERROR_INCORRECT_IPV6_STATIC_LOCAL_ADDR (-8194L) /* Ipv6 Local address perfix is wrong */ -#define SL_ERROR_INCORRECT_IPV6_STATIC_GLOBAL_ADDR (-8195L) /* Ipv6 Global address perfix is wrong */ -#define SL_ERROR_IPV6_LOCAL_ADDR_SHOULD_BE_SET_FIRST (-8196L) /* Attempt to set ipv6 global address before ipv6 local address is set */ - - -/* FS ERRORS CODES*/ -#define SL_FS_OK (0L) -#define SL_ERROR_FS_EXTRACTION_WILL_START_AFTER_RESET (-10241L) -#define SL_ERROR_FS_NO_CERTIFICATE_STORE (-10242L) -#define SL_ERROR_FS_IMAGE_SHOULD_BE_AUTHENTICATE (-10243L) -#define SL_ERROR_FS_IMAGE_SHOULD_BE_ENCRYPTED (-10244L) -#define SL_ERROR_FS_IMAGE_CANT_BE_ENCRYPTED (-10245L) -#define SL_ERROR_FS_DEVELOPMENT_BOARD_WRONG_MAC (-10246L) -#define SL_ERROR_FS_DEVICE_NOT_SECURED (-10247L) -#define SL_ERROR_FS_SYSTEM_FILE_ACCESS_DENIED (-10248L) -#define SL_ERROR_FS_IMAGE_EXTRACT_EXPECTING_USER_KEY (-10249L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_CLOSE_FILE (-10250L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_WRITE_FILE (-10251L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_OPEN_FILE (-10252L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_IMAGE_HEADER (-10253L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_IMAGE_INFO (-10254L) -#define SL_ERROR_FS_IMAGE_EXTRACT_SET_ID_NOT_EXIST (-10255L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_DELETE_FILE (-10256L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_FORMAT_FS (-10257L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_LOAD_FS (-10258L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_DEV_INFO (-10259L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_DELETE_STORAGE (-10260L) -#define SL_ERROR_FS_IMAGE_EXTRACT_INCORRECT_IMAGE_LOCATION (-10261L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_CREATE_IMAGE_FILE (-10262L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_INIT (-10263L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_LOAD_FILE_TABLE (-10264L) -#define SL_ERROR_FS_IMAGE_EXTRACT_ILLEGAL_COMMAND (-10266L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_WRITE_FAT (-10267L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_RET_FACTORY_DEFAULT (-10268L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_READ_NV (-10269L) -#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_EXISTS (-10270L) -#define SL_ERROR_FS_PROGRAMMING_IN_PROCESS (-10271L) -#define SL_ERROR_FS_PROGRAMMING_ALREADY_STARTED (-10272L) -#define SL_ERROR_FS_CERT_IN_THE_CHAIN_REVOKED_SECURITY_ALERT (-10273L) -#define SL_ERROR_FS_INIT_CERTIFICATE_STORE (-10274L) -#define SL_ERROR_FS_PROGRAMMING_ILLEGAL_FILE (-10275L) -#define SL_ERROR_FS_PROGRAMMING_NOT_STARTED (-10276L) -#define SL_ERROR_FS_IMAGE_EXTRACT_NO_FILE_SYSTEM (-10277L) -#define SL_ERROR_FS_WRONG_INPUT_SIZE (-10278L) -#define SL_ERROR_FS_BUNDLE_FILE_SHOULD_BE_CREATED_WITH_FAILSAFE (-10279L) -#define SL_ERROR_FS_BUNDLE_NOT_CONTAIN_FILES (-10280L) -#define SL_ERROR_FS_BUNDLE_ALREADY_IN_STATE (-10281L) -#define SL_ERROR_FS_BUNDLE_NOT_IN_CORRECT_STATE (-10282L) -#define SL_ERROR_FS_BUNDLE_FILES_ARE_OPENED (-10283L) -#define SL_ERROR_FS_INCORRECT_FILE_STATE_FOR_OPERATION (-10284L) -#define SL_ERROR_FS_EMPTY_SFLASH (-10285L) -#define SL_ERROR_FS_FILE_IS_NOT_SECURE_AND_SIGN (-10286L) -#define SL_ERROR_FS_ROOT_CA_IS_UNKOWN (-10287L) -#define SL_ERROR_FS_FILE_HAS_NOT_BEEN_CLOSE_CORRECTLY (-10288L) -#define SL_ERROR_FS_WRONG_SIGNATURE_SECURITY_ALERT (-10289L) -#define SL_ERROR_FS_WRONG_SIGNATURE_OR_CERTIFIC_NAME_LENGTH (-10290L) -#define SL_ERROR_FS_NOT_16_ALIGNED (-10291L) -#define SL_ERROR_FS_CERT_CHAIN_ERROR_SECURITY_ALERT (-10292L) -#define SL_ERROR_FS_FILE_NAME_EXIST (-10293L) -#define SL_ERROR_FS_EXTENDED_BUF_ALREADY_ALLOC (-10294L) -#define SL_ERROR_FS_FILE_SYSTEM_NOT_SECURED (-10295L) -#define SL_ERROR_FS_OFFSET_NOT_16_BYTE_ALIGN (-10296L) -#define SL_ERROR_FS_FAILED_READ_NVMEM (-10297L) -#define SL_ERROR_FS_WRONG_FILE_NAME (-10298L) -#define SL_ERROR_FS_FILE_SYSTEM_IS_LOCKED (-10299L) -#define SL_ERROR_FS_SECURITY_ALERT (-10300L) -#define SL_ERROR_FS_FILE_INVALID_FILE_SIZE (-10301L) -#define SL_ERROR_FS_INVALID_TOKEN (-10302L) -#define SL_ERROR_FS_NO_DEVICE_IS_LOADED (-10303L) -#define SL_ERROR_FS_SECURE_CONTENT_INTEGRITY_FAILURE (-10304L) -#define SL_ERROR_FS_SECURE_CONTENT_RETRIVE_ASYMETRIC_KEY_ERROR (-10305L) -#define SL_ERROR_FS_OVERLAP_DETECTION_THRESHHOLD (-10306L) -#define SL_ERROR_FS_FILE_HAS_RESERVED_NV_INDEX (-10307L) -#define SL_ERROR_FS_FILE_MAX_SIZE_EXCEEDED (-10310L) -#define SL_ERROR_FS_INVALID_READ_BUFFER (-10311L) -#define SL_ERROR_FS_INVALID_WRITE_BUFFER (-10312L) -#define SL_ERROR_FS_FILE_IMAGE_IS_CORRUPTED (-10313L) -#define SL_ERROR_FS_SIZE_OF_FILE_EXT_EXCEEDED (-10314L) -#define SL_ERROR_FS_WARNING_FILE_NAME_NOT_KEPT (-10315L) -#define SL_ERROR_FS_MAX_OPENED_FILE_EXCEEDED (-10316L) -#define SL_ERROR_FS_FAILED_WRITE_NVMEM_HEADER (-10317L) -#define SL_ERROR_FS_NO_AVAILABLE_NV_INDEX (-10318L) -#define SL_ERROR_FS_FAILED_TO_ALLOCATE_MEM (-10319L) -#define SL_ERROR_FS_OPERATION_BLOCKED_BY_VENDOR (-10320L) -#define SL_ERROR_FS_FAILED_TO_READ_NVMEM_FILE_SYSTEM (-10321L) -#define SL_ERROR_FS_NOT_ENOUGH_STORAGE_SPACE (-10322L) -#define SL_ERROR_FS_INIT_WAS_NOT_CALLED (-10323L) -#define SL_ERROR_FS_FILE_SYSTEM_IS_BUSY (-10324L) -#define SL_ERROR_FS_INVALID_ACCESS_TYPE (-10325L) -#define SL_ERROR_FS_FILE_ALREADY_EXISTS (-10326L) -#define SL_ERROR_FS_PROGRAM_FAILURE (-10327L) -#define SL_ERROR_FS_NO_ENTRIES_AVAILABLE (-10328L) -#define SL_ERROR_FS_FILE_ACCESS_IS_DIFFERENT (-10329L) -#define SL_ERROR_FS_INVALID_FILE_MODE (-10330L) -#define SL_ERROR_FS_FAILED_READ_NVFILE (-10331L) -#define SL_ERROR_FS_FAILED_INIT_STORAGE (-10332L) -#define SL_ERROR_FS_FILE_HAS_NO_FAILSAFE (-10333L) -#define SL_ERROR_FS_NO_VALID_COPY_EXISTS (-10334L) -#define SL_ERROR_FS_INVALID_HANDLE (-10335L) -#define SL_ERROR_FS_FAILED_TO_WRITE (-10336L) -#define SL_ERROR_FS_OFFSET_OUT_OF_RANGE (-10337L) -#define SL_ERROR_FS_NO_MEMORY (-10338L) -#define SL_ERROR_FS_INVALID_LENGTH_FOR_READ (-10339L) -#define SL_ERROR_FS_WRONG_FILE_OPEN_FLAGS (-10340L) -#define SL_ERROR_FS_FILE_NOT_EXISTS (-10341L) -#define SL_ERROR_FS_IGNORE_COMMIT_ROLLBAC_FLAG (-10342L) /* commit rollback flag is not supported upon creation */ -#define SL_ERROR_FS_INVALID_ARGS (-10343L) -#define SL_ERROR_FS_FILE_IS_PENDING_COMMIT (-10344L) -#define SL_ERROR_FS_SECURE_CONTENT_SESSION_ALREADY_EXIST (-10345L) -#define SL_ERROR_FS_UNKNOWN (-10346L) -#define SL_ERROR_FS_FILE_NAME_RESERVED (-10347L) -#define SL_ERROR_FS_NO_FILE_SYSTEM (-10348L) -#define SL_ERROR_FS_INVALID_MAGIC_NUM (-10349L) -#define SL_ERROR_FS_FAILED_TO_READ_NVMEM (-10350L) -#define SL_ERROR_FS_NOT_SUPPORTED (-10351L) -#define SL_ERROR_FS_JTAG_IS_OPENED_NO_FORMAT_TO_PRDUCTION (-10352L) -#define SL_ERROR_FS_CONFIG_FILE_RET_READ_FAILED (-10353L) -#define SL_ERROR_FS_CONFIG_FILE_CHECSUM_ERROR_SECURITY_ALERT (-10354L) -#define SL_ERROR_FS_CONFIG_FILE_NO_SUCH_FILE (-10355L) -#define SL_ERROR_FS_CONFIG_FILE_MEMORY_ALLOCATION_FAILED (-10356L) -#define SL_ERROR_FS_IMAGE_HEADER_READ_FAILED (-10357L) -#define SL_ERROR_FS_CERT_STORE_DOWNGRADE (-10358L) -#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_VALID (-10359L) -#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_VERIFIED (-10360L) -#define SL_ERROR_FS_RESERVE_SIZE_IS_SMALLER (-10361L) -#define SL_ERROR_FS_WRONG_ALLOCATION_TABLE (-10362L) -#define SL_ERROR_FS_ILLEGAL_SIGNATURE (-10363L) -#define SL_ERROR_FS_FILE_ALREADY_OPENED_IN_PENDING_STATE (-10364L) -#define SL_ERROR_FS_INVALID_TOKEN_SECURITY_ALERT (-10365L) -#define SL_ERROR_FS_NOT_SECURE (-10366L) -#define SL_ERROR_FS_RESET_DURING_PROGRAMMING (-10367L) -#define SL_ERROR_FS_CONFIG_FILE_RET_WRITE_FAILED (-10368L) -#define SL_ERROR_FS_FILE_IS_ALREADY_OPENED (-10369L) -#define SL_ERROR_FS_FILE_IS_OPEN_FOR_WRITE (-10370L) -#define SL_ERROR_FS_ALERT_CANT_BE_SET_ON_NON_SECURE_DEVICE (-10371L) /* Alerts can be configured on non-secure device. */ -#define SL_ERROR_FS_WRONG_CERTIFICATE_FILE_NAME (-10372L) - - -/* NETUTIL ERRORS CODES */ -#define SL_ERROR_NETUTIL_CRYPTO_GENERAL (-12289L) -#define SL_ERROR_NETUTIL_CRYPTO_INVALID_INDEX (-12290L) -#define SL_ERROR_NETUTIL_CRYPTO_INVALID_PARAM (-12291L) -#define SL_ERROR_NETUTIL_CRYPTO_MEM_ALLOC (-12292L) -#define SL_ERROR_NETUTIL_CRYPTO_INVALID_DB_VER (-12293L) -#define SL_ERROR_NETUTIL_CRYPTO_UNSUPPORTED_OPTION (-12294L) -#define SL_ERROR_NETUTIL_CRYPTO_BUFFER_TOO_SMALL (-12295L) -#define SL_ERROR_NETUTIL_CRYPTO_EMPTY_DB_ENTRY (-12296L) -#define SL_ERROR_NETUTIL_CRYPTO_NON_TEMPORARY_KEY (-12297L) -#define SL_ERROR_NETUTIL_CRYPTO_DB_ENTRY_NOT_FREE (-12298L) -#define SL_ERROR_NETUTIL_CRYPTO_CORRUPTED_DB_FILE (-12299L) - - -/* GENERAL ERRORS CODES*/ -#define SL_ERROR_INVALID_OPCODE (-14337L) -#define SL_ERROR_INVALID_PARAM (-14338L) -#define SL_ERROR_STATUS_ERROR (-14341L) -#define SL_ERROR_NVMEM_ACCESS_FAILED (-14342L) -#define SL_ERROR_NOT_ALLOWED_NWP_LOCKED (-14343L) /* Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ - - -/* SECURITY ERRORS CODE */ -#define SL_ERROR_LOADING_CERTIFICATE_STORE (-28673L) - -/* Device is Locked! Return to Factory Image or Program new - image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SL_ERROR_DEVICE_LOCKED_SECURITY_ALERT (-28674L) - -#define SL_ERROR_LENGTH_ERROR_PREFIX (-30734L) -#define SL_ERROR_WAKELOCK_ERROR_PREFIX (-30735L) -#define SL_ERROR_DRV_START_FAIL (-30736L) -#define SL_ERROR_VALIDATION_ERROR (-30737L) -#define SL_ERROR_SETUP_FAILURE (-30738L) -#define SL_ERROR_HTTP_SERVER_ENABLE_FAILED (-30739L) -#define SL_ERROR_DHCP_SERVER_ENABLE_FAILED (-30740L) -#define SL_ERROR_WPS_NO_PIN_OR_WRONG_PIN_LEN (-30741L) - - -/* INTERNAL HOST ERRORS CODES*/ - -/* Receive this error in case there are no resources to issue the command - If possible, increase the number of MAX_CONCURRENT_ACTIONS (result in memory increaseL) - If not, try again later */ -#define SL_POOL_IS_EMPTY (-2000L) - -/* Receive this error in case a given length for RX buffer was too small. - Receive payload was bigger than the given buffer size. Therefore, payload is cut according to receive size - Recommend to increase buffer size */ -#define SL_ESMALLBUF (-2001L) - -/* Receive this error in case zero length is supplied to a "get" API - Recommend to supply length according to requested information (view options defines for helpL) */ -#define SL_EZEROLEN (-2002L) - -/* User supplied invalid parameter */ -#define SL_INVALPARAM (-2003L) - -/* Failed to open interface */ -#define SL_BAD_INTERFACE (-2004L) - -/* API has been aborted due to an error detected by host driver */ -#define SL_API_ABORTED (-2005L) - -/* Parameters are invalid */ -#define SL_RET_CODE_INVALID_INPUT (-2006L) - -/* Driver internal error */ -#define SL_RET_CODE_SELF_ERROR (-2007L) - -/* NWP internal error */ -#define SL_RET_CODE_NWP_IF_ERROR (-2008L) - -/* malloc error */ -#define SL_RET_CODE_MALLOC_ERROR (-2009L) - -/* protocol error */ -#define SL_RET_CODE_PROTOCOL_ERROR (-2010L) - -/* API has been aborted, command is not allowed in device lock state */ -#define SL_RET_CODE_DEV_LOCKED (-2011L) - -/* sl_Start cannot be invoked twice */ -#define SL_RET_CODE_DEV_ALREADY_STARTED (-2012L) - -/* SL API is in progress */ -#define SL_RET_CODE_API_COMMAND_IN_PROGRESS (-2013L) - -/* Provisioning is in progress - */ -#define SL_RET_CODE_PROVISIONING_IN_PROGRESS (-2014L) - -/* Wrong ping parameters - ping cannot be called with the following parameters: -1. infinite ping packet -2. report only when finished -3. no callback supplied */ -#define SL_RET_CODE_NET_APP_PING_INVALID_PARAMS (-2015L) - -/* SL select already in progress. - this error will be returned if app will try to call - sl_select blocking when there is already select trigger in progress */ -#define SL_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR (-2016L) - -#define SL_RET_CODE_STOP_IN_PROGRESS (-2017L) - -/* The device has not been started yet */ -#define SL_RET_CODE_DEV_NOT_STARTED (-2018L) - -/* The event link was not found in the list */ -#define SL_RET_CODE_EVENT_LINK_NOT_FOUND (-2019L) - -/* In case there are no free buffers for async event which arrived - during command context. In this case user needs to increase - MAX_CONCURRENT_ACTIONS at user.h */ -#define SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR (-2020L) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ERROR_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.c deleted file mode 100755 index 740aef035dd..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * eventreg.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include - - -typedef void (*_pSlDeviceFatalErrorEvtHdlr_t)(SlDeviceFatal_t *pSlFatalErrorEvent); -typedef void (*_pSlDeviceGeneralEvtHdlr_t)(SlDeviceEvent_t *pSlDeviceEvent); -typedef void (*_pSlWlanEvtHdlr)(SlWlanEvent_t* pSlWlanEvent); -typedef void (*_pSlNetAppEvtHdlr)(SlNetAppEvent_t* pSlNetAppEvent); -typedef void (*_pSlSockEvtHdlr)(SlSockEvent_t* pSlSockEvent); -typedef void (*_pSlNetAppHttpServerHdlr)(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); -typedef void (*_pSlNetAppRequestHdlr)(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -typedef void (*_pSlNetAppRequestMemFree)(_u8 *buffer); -typedef void (*_pSlSocketTriggerEventHandler)(SlSockTriggerEvent_t* pSlSockTriggerEvent); - - -typedef _i32 (*_pSlPropogationDeviceFatalErrorEvtHdlr_t)(SlDeviceFatal_t *pSlFatalErrorEvent); -typedef _i32 (*_pSlPropogationDeviceGeneralEvtHdlr_t)(SlDeviceEvent_t *pSlDeviceEvent); -typedef _i32 (*_pSlPropogationWlanEvtHdlr)(SlWlanEvent_t* pSlWlanEvent); -typedef _i32 (*_pSlPropogationNetAppEvtHdlr)(SlNetAppEvent_t* pSlNetAppEvent); -typedef _i32 (*_pSlPropogationSockEvtHdlr)(SlSockEvent_t* pSlSockEvent); -typedef _i32 (*_pSlPropogationNetAppHttpServerHdlr)(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); -typedef _i32 (*_pSlPropogationNetAppRequestHdlr)(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -typedef _i32 (*_pSlPropogationNetAppRequestMemFree)(_u8 *buffer); -typedef _i32 (*_pSlPropogationSocketTriggerEventHandler)(SlSockTriggerEvent_t* pSlSockTriggerEvent); - -#ifdef SL_RUNTIME_EVENT_REGISTERATION - -void* g_UserEvents[SL_NUM_OF_EVENT_TYPES] = {0}; -SlEventsListNode_t* g_LibsEvents[SL_NUM_OF_EVENT_TYPES] = {0}; - -#endif - - -_i32 _SlIsEventRegistered(SlEventHandler_e EventHandlerType) -{ -#ifdef SL_RUNTIME_EVENT_REGISTERATION - if( (NULL != g_LibsEvents[EventHandlerType]) || (NULL != g_UserEvents[EventHandlerType]) ) - { - return 1; - } -#endif - if(SL_EVENT_HDL_MEM_FREE == EventHandlerType) - { -#ifdef slcb_NetAppRequestMemFree - return 1; -#endif - } - if(SL_EVENT_HDL_SOCKET_TRIGGER == EventHandlerType) - { -#ifdef slcb_SocketTriggerEventHandler - return 1; -#endif - } - - return 0; -} - -#ifdef SL_RUNTIME_EVENT_REGISTERATION - -_i32 sl_RegisterEventHandler(SlEventHandler_e EventHandlerType , void* EventHandler) -{ - g_UserEvents[EventHandlerType] = EventHandler; - return 0; -} - -_i32 sl_RegisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode) -{ - EventHandlerNode->next = NULL; - - if(g_LibsEvents[EventHandlerType] == NULL) - { - g_LibsEvents[EventHandlerType] = EventHandlerNode; - } - else - { - SlEventsListNode_t* currentNode = g_LibsEvents[EventHandlerType]; - while(currentNode->next != NULL) - { - currentNode = currentNode->next; - } - - currentNode->next = EventHandlerNode; - } - return 0; -} - -_i32 sl_UnregisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[EventHandlerType]; - SlEventsListNode_t* lastNode = g_LibsEvents[EventHandlerType]; - int count = 0; - while(currentNode != NULL) - { - if(EventHandlerNode == currentNode) - { - if(count == 0) - { - g_LibsEvents[EventHandlerType] = g_LibsEvents[EventHandlerType]->next; - } - else - { - lastNode->next = currentNode->next; - } - return 0; - } - - if(count != 0) - { - lastNode = lastNode->next; - } - count++; - currentNode = currentNode->next; - } - - return SL_RET_CODE_EVENT_LINK_NOT_FOUND; -} - - -/* Event handlers section */ -void _SlDeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_FATAL_ERROR]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationDeviceFatalErrorEvtHdlr_t)(currentNode->event))(pSlFatalErrorEvent)) - { - return; - } - currentNode = currentNode->next; - } - - if (NULL != g_UserEvents[SL_EVENT_HDL_FATAL_ERROR]) - { - ((_pSlDeviceFatalErrorEvtHdlr_t)g_UserEvents[SL_EVENT_HDL_FATAL_ERROR])(pSlFatalErrorEvent); - } - -#ifdef slcb_DeviceFatalErrorEvtHdlr - else - { - slcb_DeviceFatalErrorEvtHdlr(pSlFatalErrorEvent); - } -#endif -} - - -void _SlDeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_DEVICE_GENERAL]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationDeviceGeneralEvtHdlr_t)(currentNode->event))(pSlDeviceEvent)) - { - return; - } - currentNode = currentNode->next; - } - - if (NULL != g_UserEvents[SL_EVENT_HDL_DEVICE_GENERAL]) - { - ((_pSlDeviceGeneralEvtHdlr_t)g_UserEvents[SL_EVENT_HDL_DEVICE_GENERAL])(pSlDeviceEvent); - } -#ifdef slcb_DeviceGeneralEvtHdlr - else - { - slcb_DeviceGeneralEvtHdlr(pSlDeviceEvent); - } -#endif -} - - -void _SlWlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_WLAN]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationWlanEvtHdlr)(currentNode->event))(pSlWlanEvent)) - { - return; - } - currentNode = currentNode->next; - } - - if (NULL != g_UserEvents[SL_EVENT_HDL_WLAN]) - { - ((_pSlWlanEvtHdlr)g_UserEvents[SL_EVENT_HDL_WLAN])(pSlWlanEvent); - } -#ifdef slcb_WlanEvtHdlr - else - { - slcb_WlanEvtHdlr(pSlWlanEvent); - } -#endif -} - - -void _SlNetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_NETAPP]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppEvtHdlr)(currentNode->event))(pSlNetAppEvent)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_NETAPP]) - { - ((_pSlNetAppEvtHdlr)g_UserEvents[SL_EVENT_HDL_NETAPP])(pSlNetAppEvent); - } -#ifdef slcb_NetAppEvtHdlr - else - { - slcb_NetAppEvtHdlr(pSlNetAppEvent); - } -#endif -} - - -void _SlSockEvtHdlr(SlSockEvent_t* pSlSockEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_SOCKET]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationSockEvtHdlr)(currentNode->event))(pSlSockEvent)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_SOCKET]) - { - ((_pSlSockEvtHdlr)g_UserEvents[SL_EVENT_HDL_SOCKET])(pSlSockEvent); - } - -#ifdef slcb_SockEvtHdlr - else - { - slcb_SockEvtHdlr(pSlSockEvent); - } -#endif -} - - -void _SlNetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_HTTP_SERVER]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppHttpServerHdlr)(currentNode->event))(pSlHttpServerEvent,pSlHttpServerResponse)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_HTTP_SERVER]) - { - ((_pSlNetAppHttpServerHdlr)g_UserEvents[SL_EVENT_HDL_HTTP_SERVER])(pSlHttpServerEvent,pSlHttpServerResponse); - } -#ifdef slcb_NetAppHttpServerHdlr - else - { - slcb_NetAppHttpServerHdlr(pSlHttpServerEvent,pSlHttpServerResponse); - } -#endif -} - - - -void _SlNetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_NETAPP_REQUEST]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppRequestHdlr)(currentNode->event))(pNetAppRequest,pNetAppResponse)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_NETAPP_REQUEST]) - { - ((_pSlNetAppRequestHdlr)g_UserEvents[SL_EVENT_HDL_NETAPP_REQUEST])(pNetAppRequest,pNetAppResponse); - } -#ifdef slcb_NetAppRequestHdlr - else - { - slcb_NetAppRequestHdlr(pNetAppRequest,pNetAppResponse); - } -#endif -} - - - -void _SlNetAppRequestMemFree (_u8 *buffer) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_MEM_FREE]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppRequestMemFree)(currentNode->event))(buffer)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_MEM_FREE]) - { - ((_pSlNetAppRequestMemFree)g_UserEvents[SL_EVENT_HDL_MEM_FREE])(buffer); - } -#ifdef slcb_NetAppRequestMemFree - else - { - slcb_NetAppRequestMemFree(buffer); - } -#endif -} - - -void _SlSocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_SOCKET_TRIGGER]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationSocketTriggerEventHandler)(currentNode->event))(pSlSockTriggerEvent)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_SOCKET_TRIGGER]) - { - ((_pSlSocketTriggerEventHandler)g_UserEvents[SL_EVENT_HDL_SOCKET_TRIGGER])(pSlSockTriggerEvent); - } -#ifdef slcb_SocketTriggerEventHandler - else - { - slcb_SocketTriggerEventHandler(pSlSockTriggerEvent); - } -#endif -} - -#endif /* SL_RUNTIME_EVENT_REGISTERATION */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.h deleted file mode 100755 index 4f2a66be7cc..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * eventreg.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef EVENTREG_H_ -#define EVENTREG_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! - \defgroup event_registration - \short Allows user to register event handlers dynamically. - -*/ -/*! - - \addtogroup event_registration - @{ - -*/ - -typedef enum -{ - SL_EVENT_HDL_FATAL_ERROR, - SL_EVENT_HDL_DEVICE_GENERAL, - SL_EVENT_HDL_WLAN, - SL_EVENT_HDL_NETAPP, - SL_EVENT_HDL_SOCKET, - SL_EVENT_HDL_HTTP_SERVER, - SL_EVENT_HDL_NETAPP_REQUEST, - SL_EVENT_HDL_MEM_FREE, - SL_EVENT_HDL_SOCKET_TRIGGER, - SL_NUM_OF_EVENT_TYPES -}SlEventHandler_e; - -typedef struct SlEventsListNode_s -{ - void *event; - struct SlEventsListNode_s *next; -}SlEventsListNode_t; - -#ifdef SL_RUNTIME_EVENT_REGISTERATION - -/*! - \brief register events in runtime - - this api enables registration of the SimpleLink host driver in runtime. - - \param[in] EventHandlerType event type - SlEventHandler_e - to register - - \param[in] EventHandler pointer to the event handler - - \return 0 on success, error otherwise - - \sa sl_RegisterEventHandler - - \note registration of event with NULL, clears any registered event. -*/ -_i32 sl_RegisterEventHandler(SlEventHandler_e EventHandlerType , void* EventHandler); - - - -_i32 _SlIsEventRegistered(SlEventHandler_e EventHandlerType); - -/****************************************************************************** - sl_RegisterLibsEventHandler - - \brief this function registers event handlers from external libraries in runtime. - - the allocation and memory maintenance of the SlEventsListNode_t is on the library - Responsibility. - - RETURNS: success or error code. -******************************************************************************/ - -_i32 sl_RegisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode); - -/****************************************************************************** - sl_UnregisterLibsEventHandler - - DESCRIPTION: - this function unregisters event handlers from external libraries in runtime. - the SlEventsListNode_t that was used for registration, must be used to unregister that event handler. - - the allocation and memory maintenance of the SlEventsListNode_t is on the library - Responsibility. - - RETURNS: success or error code. -******************************************************************************/ -_i32 sl_UnregisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode); - -/*! - - Close the Doxygen group. - @} - - */ - - -void _SlDeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent); -void _SlDeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent); -void _SlWlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent); -void _SlNetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent); -void _SlSockEvtHdlr(SlSockEvent_t* pSlSockEvent); -void _SlNetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); -void _SlNetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -void _SlNetAppRequestMemFree (_u8 *buffer); -void _SlSocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent); - -#endif /* SL_RUNTIME_EVENT_REGISTERATION */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - -#endif /* EVENTREG_H_ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/fs.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/fs.h deleted file mode 100755 index 6b95dc7f72a..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/fs.h +++ /dev/null @@ -1,850 +0,0 @@ -/* - * fs.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __FS_H__ -#define __FS_H__ - - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup FileSystem - \short Provides file system capabilities to TI's CC31XX that can be used by both the CC31XX device and the user - -*/ - -/*! - - \addtogroup FileSystem - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* Create file max size mode */ -#define SL_FS_OPEN_MODE_BIT_MASK (0xF8000000) -#define SL_NUM_OF_MODE_BIT (5) - -#define SL_FS_OPEN_FLAGS_BIT_MASK (0x07FE0000) -#define SL_NUM_OF_FLAGS_BIT (10) - -#define SL_FS_OPEN_MAXSIZE_BIT_MASK (0x1FFFF) -#define SL_NUM_OF_MAXSIZE_BIT (17) - - -/* - sl_FsGetInfo and sl_FsGetFileList flags - ------------------ -*/ - -#define SL_FS_INFO_OPEN_WRITE 0x1000 /* File is opened for write */ -#define SL_FS_INFO_OPEN_READ 0x800 /* File is opened for read */ - -#define SL_FS_INFO_MUST_COMMIT 0x1 /* File is currently open with SL_FS_WRITE_MUST_COMMIT */ -#define SL_FS_INFO_BUNDLE_FILE 0x2 /* File is currently open with SL_FS_WRITE_BUNDLE_FILE */ - -#define SL_FS_INFO_PENDING_COMMIT 0x4 /* File that was open with SL_FS_WRITE_MUST_COMMIT is closed */ -#define SL_FS_INFO_PENDING_BUNDLE_COMMIT 0x8 /* File that was open with SL_FS_WRITE_BUNDLE_FILE is closed */ - -#define SL_FS_INFO_NOT_FAILSAFE 0x20 /* File was not created with SL_FS_CREATE_FAILSAFE */ -#define SL_FS_INFO_NOT_VALID 0x100 /* No valid image exists for the file */ -#define SL_FS_INFO_SYS_FILE 0x40 /* File is system file */ -#define SL_FS_INFO_SECURE 0x10 /* File is secured */ -#define SL_FS_INFO_NOSIGNATURE 0x2000 /* File is unsigned, the flag is returns only for sl_FsGetInfo function and not for sl_FsGetFileList */ -#define SL_FS_INFO_PUBLIC_WRITE 0x200 /* File is open for public write */ -#define SL_FS_INFO_PUBLIC_READ 0x400 /* File is open for public read */ - - -/* - fs_Open flags - -------------- -*/ - -/* mode */ -#define SL_FS_CREATE ((_u32)0x1<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) -#define SL_FS_WRITE ((_u32)0x2<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) -#define SL_FS_OVERWRITE ((_u32)0x4<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) -#define SL_FS_READ ((_u32)0x8<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) -/* creation flags */ -#define SL_FS_CREATE_FAILSAFE ((_u32)0x1< - - - Create a non secure file if not already exists and open it for write - \code - DeviceFileHandle = sl_FsOpen((unsigned char *)DeviceFileName, - SL_FS_CREATE|SL_FS_OVERWRITE| SL_FS_CREATE_MAX_SIZE( MaxSize ), - NULL); - \endcode - - \note Some of the flags are creation flags and can only be set when the file is created. When opening the file for write the creation flags are ignored. For more information, refer to chapter 8 in the user manual. - -*/ - -#if _SL_INCLUDE_FUNC(sl_FsOpen) -_i32 sl_FsOpen(const _u8 *pFileName,const _u32 AccessModeAndMaxSize,_u32 *pToken); -#endif - -/*! - \brief Close file in storage device - - \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) - \param[in] pCeritificateFileName Certificate file, or NULL if irrelevant. - \param[in] pSignature The signature is SHA-1, the certificate chain may include SHA-256 - \param[in] SignatureLen The signature actual length - - \return Zero on success, or a negative value if an error occurred - \sa sl_FsRead sl_FsWrite sl_FsOpen - \note Call the fs_Close with signature = 'A' signature len = 1 for activating an abort action\n - Creating signature : OpenSSL> dgst -binary -sha1 -sign \.pem -out \.sig \.txt - \warning - \par Examples - - - Closing file: - \code - _i16 RetVal; - RetVal = sl_FsClose(FileHandle,0,0,0); - \endcode -
- - - Aborting file: - \code - _u8 Signature; - Signature = 'A'; - sl_FsClose(FileHandle,0,&Signature, 1); - \endcode - - \note In case the file was opened as not secure file or as secure-not signed, any certificate or signature provided are ignored, those fields should be set to NULL. -*/ -#if _SL_INCLUDE_FUNC(sl_FsClose) -_i16 sl_FsClose(const _i32 FileHdl,const _u8* pCeritificateFileName,const _u8* pSignature,const _u32 SignatureLen); -#endif - -/*! - \brief Read block of data from a file in storage device - - \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) - \param[in] Offset Offset to specific read block - \param[out] pData Pointer for the received data - \param[in] Len Length of the received data - - \return Number of read bytes on success, negative error code on failure - - \sa sl_FsClose sl_FsWrite sl_FsOpen - \note belongs to \ref basic_api - \warning - \par Example - - - Reading File: - \code - Status = sl_FsRead(FileHandle, 0, &readBuff[0], readSize); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsRead) -_i32 sl_FsRead(const _i32 FileHdl,_u32 Offset ,_u8* pData,_u32 Len); -#endif - -/*! - \brief Write block of data to a file in storage device - - \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) - \param[in] Offset Offset to specific block to be written - \param[in] pData Pointer the transmitted data to the storage device - \param[in] Len Length of the transmitted data - - \return Number of wireted bytes on success, negative error code on failure - - \sa - \note belongs to \ref basic_api - \warning - \par Example - - - Writing file: - \code - Status = sl_FsWrite(FileHandle, 0, &buff[0], readSize); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsWrite) -_i32 sl_FsWrite(const _i32 FileHdl,_u32 Offset,_u8* pData,_u32 Len); -#endif - -/*! - \brief Get information of a file - - \param[in] pFileName File name - \param[in] Token File token. if irrelevant set to 0. - \param[out] pFsFileInfo Returns the File's Information (SlFsFileInfo_t) - - Flags - - File size - - Allocated size - - Tokens - - \return Zero on success, negative error code on failure \n - When file not exists : SL_ERROR_FS_FILE_NOT_EXISTS - \note - - If the return value is SL_ERROR_FS_FILE_HAS_NOT_BEEN_CLOSE_CORRECTLY or SL_ERROR_FS_FILE_IS_ALREADY_OPENED information about the file is valid. - - Belongs to \ref basic_api - - \sa sl_FsOpen - \warning - \par Example - - - Getting file info: - \code - Status = sl_FsGetInfo("FileName.html",Token,&FsFileInfo); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsGetInfo) -_i16 sl_FsGetInfo(const _u8 *pFileName,const _u32 Token,SlFsFileInfo_t* pFsFileInfo); -#endif - -/*! - \brief Delete specific file from a storage or all files from a storage (format) - - \param[in] pFileName File Name - \param[in] Token File token. if irrelevant set to 0 - \return Zero on success, or a negative value if an error occurred - - \sa - \note belongs to \ref basic_api - \warning - \par Example - - - Deleting file: - \code - Status = sl_FsDel("FileName.html",Token); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsDel) -_i16 sl_FsDel(const _u8 *pFileName,const _u32 Token); -#endif - - - -/*! - \brief Controls various file system operations - - \param[in] Command , the command to execute, \see SlFsCtl_e - SL_FS_CTL_RESTORE , Return to factory default, return to factory image , see fs programming - SL_FS_CTL_ROLLBACK , Roll-back file which was created with 'SL_FS_WRITE_MUST_COMMIT' - SL_FS_CTL_COMMIT,Commit file which was created with 'SL_FS_WRITE_MUST_COMMIT' - SL_FS_CTL_RENAME, Rename file - SL_FS_CTL_GET_STORAGE_INFO, Total size of storage , available size of storage - SL_FS_CTL_BUNDLE_ROLLBACK, Rollback bundle files - SL_FS_CTL_BUNDLE_COMMIT, Commit Bundle files - \param[in] Token Set to NULL if not relevant to the command - \param[in] pFileName Set to NULL if not relevant to the command - \param[in] pData The data according the command. - \param[in] DataLen Length of data buffer - \param[out] pOutputData Buffer for the output data - \param[out] OutputDataLen Length of the output data buffer - \param[out] pNewToken The new valid file token, if irrelevant can be set to NULL. - \return - - Zero on success, or a negative value if an error occurred - - For SL_FS_CTL_BUNDLE_ROLLBACK, On success bundle the new bundle state is returned (see SlFsBundleState_e) else negative error number - - For SL_FS_CTL_BUNDLE_COMMIT, On success the new bundle state is returned (see SlFsBundleState_e) else negative error number - - \sa - \note belongs to \ref ext_api - \warning - \par Examples - - - SL_FS_CTL_ROLLBACK: - \code - FsControl.IncludeFilters = 0; - slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_FILE_ROLLBACK, Token, NWPfileName ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , pNewToken); - \endcode -
- - - SL_FS_CTL_COMMIT: - \code - FsControl.IncludeFilters = 0; - slRetVal = sl_FsCtl(SL_FS_CTL_COMMIT, Token, NWPfileName ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0, pNewToken ); - \endcode -
- - - SL_FS_CTL_RENAME: - \code - slRetVal = sl_FsCtl(SL_FS_CTL_RENAME, Token, NWPfileName, NewFileName, 0, NULL, 0, NULL ); - \endcode -
- - - SL_FS_CTL_GET_STORAGE_INFO: - \code - _i32 GetStorageInfo( SlFsControlGetStorageInfoResponse_t* pSlFsControlGetStorageInfoResponse ) - { - _i32 slRetVal; - - slRetVal = sl_FsCtl( ( SlFsCtl_e)SL_FS_CTL_GET_STORAGE_INFO, 0, NULL , NULL , 0, (_u8 *)pSlFsControlGetStorageInfoResponse, sizeof(SlFsControlGetStorageInfoResponse_t), NULL ); - return slRetVal; - } - \endcode -
- - - SL_FS_CTL_RESTORE: - \code - //Return 0 for OK, else Error - _i32 ProgramRetToImage( ) - { - _i32 slRetVal; - SlFsRetToFactoryCommand_t RetToFactoryCommand; - _i32 RetVal, ExtendedError; - - RetToFactoryCommand.Operation = SL_FS_FACTORY_RET_TO_IMAGE; - slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_RESTORE, 0, NULL , (_u8 *)&RetToFactoryCommand , sizeof(SlFsRetToFactoryCommand_t), NULL, 0 , NULL ); - if ((_i32)slRetVal < 0) - { - //Pay attention, for this function the slRetVal is composed from Signed RetVal & extended error - RetVal = (_i16)slRetVal>> 16; - ExtendedError = (_u16)slRetVal& 0xFFFF; - printf("\tError SL_FS_FACTORY_RET_TO_IMAGE, 5d, %d\n", RetVal, ExtendedError); - return slRetVal; - } - //Reset - sl_Stop(0); - Sleep(1000); - sl_Start(NULL, NULL, NULL); - - return slRetVal; - } - \endcode -
- - - SL_FS_CTL_BUNDLE_ROLLBACK: - \code - //return 0 for O.K else negative - _i32 BundleRollback() - { - _i32 slRetVal = 0; - SlFsControl_t FsControl; - FsControl.IncludeFilters = 0; //Use default behaviour - slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_BUNDLE_ROLLBACK, 0, NULL ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , NULL); - return slRetVal; - } - \endcode -
- - - SL_FS_CTL_BUNDLE_COMMIT: - \code - //return 0 for O.K else negative - _i32 BundleCommit() - { - _i32 slRetVal = 0; - SlFsControl_t FsControl; - FsControl.IncludeFilters = 0; //Use default behaviour - slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_BUNDLE_COMMIT, 0, NULL ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , NULL); - return slRetVal; - } - \endcode - */ -#if _SL_INCLUDE_FUNC(sl_FsCtl) -_i32 sl_FsCtl( SlFsCtl_e Command, _u32 Token, _u8 *pFileName, const _u8 *pData, _u16 DataLen, _u8 *pOutputData, _u16 OutputDataLen,_u32 *pNewToken ); -#endif -/*! - \brief Enables to format and configure the device with pre-prepared configuration - - \param[in] Flags For future use - \param[in] pKey In case the ucf is encrypted the encryption key, otherwise NULL - \param[in] pData The file is download in data chunks, the chunk size should be aligned to 16 bytes, if no data Set to NULL - \param[in] Len The length of pData in bytes - \return The return value is: - - On error < 0 , contains the error number and extended error number - - On success > 0, represent the number of bytes received - - On successful end == 0 , when all file chunks are download - \sa - \note belongs to \ref ext_api - \warning - \par Example - - - FS programming: - \code - - //Return 0 for OK, else Error - _i32 ProgramImage( char* UcfFileName, char * KeyFileName ) - { - #define PROGRAMMING_CHUNK_SIZE 4096 - _i32 slRetVal = 0; - SlFsKey_t Key; - FILE *hostFileHandle = NULL; - _u16 bytesRead; - _u8 DataBuf[PROGRAMMING_CHUNK_SIZE]; - FILE *KeyFileHandle = NULL; - short ErrorNum; - unsigned short ExtendedErrorNum; - time_t start,end; - double dif; - _u8* pKey = NULL; - errno_t err; - - if (KeyFileName != "") - { - //Read key - err = fopen_s( &KeyFileHandle, KeyFileName, "rb"); - if (err != 0) - { - return __LINE__;//error - } - fread((_u8*)&Key, 1, sizeof(SlFsKey_t), KeyFileHandle); - fclose(KeyFileHandle); - pKey = (_u8*)&Key; - } - - // Downlaoding the Data with the key, the key can be set only in the first chunk,no need to download it with each chunk - if (UcfFileName != "") - { - //Read data - err = fopen_s( &hostFileHandle, UcfFileName, "rb"); - if (err != 0) - { - return __LINE__;//error - } - - time (&start); - - bytesRead = fread(DataBuf, 1, PROGRAMMING_CHUNK_SIZE, hostFileHandle); - - while ( bytesRead ) - { - slRetVal = sl_FsProgram( DataBuf , bytesRead , (_u8*)pKey, 0 ); - if(slRetVal == SL_API_ABORTED)//timeout - { - return( slRetVal ); - } - else if (slRetVal < 0 )//error - { - ErrorNum = (long)slRetVal >> 16; - ExtendedErrorNum = (_u16)(slRetVal & 0xFFFF); - printf("\tError sl_FsProgram = %d , %d \n", ErrorNum, ExtendedErrorNum); - fclose(hostFileHandle); - return( ErrorNum ); - } - if(slRetVal == 0)//finished succesfully - break; - pKey = NULL;//no need to download the key with each chunk; - bytesRead = fread(DataBuf, 1, PROGRAMMING_CHUNK_SIZE, hostFileHandle); - } - - - time (&end); - dif = difftime (end,start); - #ifdef PRINT - printf ("\tProgramming took %.2lf seconds to run.\n", dif ); - #endif - //The file was downloaded but it was not detected by the programming as the EOF. - if((bytesRead == 0 ) && (slRetVal > 0 )) - { - return __LINE__;//error - } - - - fclose(hostFileHandle); - }//if (UcfFileName != "") - - //this scenario is in case the image was already "burned" to the SFLASH by external tool and only the key is downloaded - else if (KeyFileName != "") - { - slRetVal = sl_FsProgram(NULL , 0 , (_u8*)pKey, 0 ); - if (slRetVal < 0)//error - { - ErrorNum = (long)slRetVal >> 16; - ExtendedErrorNum = (_u16)slRetVal && 0xFF;; - printf("\tError sl_FsProgram = %d , %d \n", ErrorNum, ExtendedErrorNum); - fclose(hostFileHandle); - return( ErrorNum ); - } - } - - if( slRetVal == 0 ) - { - //Reset the nWP - sl_Stop(100); - Sleep(1000); - sl_Start(NULL, NULL, NULL); - Sleep(2000); - } - - return slRetVal; - - } - - \endcode -*/ - -#if _SL_INCLUDE_FUNC(sl_FsProgram) -_i32 sl_FsProgram(const _u8* pData , _u16 Len , const _u8 * pKey , _u32 Flags ); -#endif -/*! - \brief The list of file names, the files are retrieve in chunks - - \param[in, out] pIndex The first chunk should start with value of -1, afterwards the Index from the previous call should be set as input\n - Returns current chunk intex, start the next chunk from that number - \param[in] Count Number of entries to retrieve - \param[in] MaxEntryLen The total size of the buffer is Count * MaxEntryLen - \param[out] pBuff The buffer contains list of SlFileAttributes_t + file name - \param[in] Flags Is to retrieve file attributes see SlFileAttributes_t. - \return The actual number of entries which are contained in the buffer. On error negative number which contains the error number. - \sa - \note belongs to \ref ext_api - \warning - \par Example - - - Getting file list - \code - typedef struct - { - SlFileAttributes_t attribute; - char fileName[SL_FS_MAX_FILE_NAME_LENGTH]; - }slGetfileList_t; - - #define COUNT 5 - - void PrintFileListProperty(_u16 prop); - - INT32 GetFileList() - { - _i32 NumOfEntriesOrError = 1; - _i32 Index = -1; - slGetfileList_t File[COUNT]; - _i32 i; - _i32 RetVal = 0; - - printf("%\n"); - while( NumOfEntriesOrError > 0 ) - { - NumOfEntriesOrError = sl_FsGetFileList( &Index, COUNT, (_u8)(SL_FS_MAX_FILE_NAME_LENGTH + sizeof(SlFileAttributes_t)), (unsigned char*)File, SL_FS_GET_FILE_ATTRIBUTES); - if (NumOfEntriesOrError < 0) - { - RetVal = NumOfEntriesOrError;//error - break; - } - for (i = 0; i < NumOfEntriesOrError; i++) - { - printf("Name: %s\n", File[i].fileName); - printf("AllocatedBlocks: %5d ",File[i].attribute.FileAllocatedBlocks); - printf("MaxSize(byte): %5d \n", File[i].attribute.FileMaxSize); - PrintFileListProperty((_u16)File[i].attribute.Properties); - printf("%\n\n"); - } - } - printf("%\n"); - return RetVal;//0 means O.K - } - - void PrintFileListProperty(_u16 prop) - { - printf("Flags : "); - if (prop & SL_FS_INFO_MUST_COMMIT) - printf("Open file commit,"); - if (prop & SL_FS_INFO_BUNDLE_FILE) - printf("Open bundle commit,"); - if (prop & SL_FS_INFO_PENDING_COMMIT) - printf("Pending file commit,"); - if (prop & SL_FS_INFO_PENDING_BUNDLE_COMMIT) - printf("Pending bundle commit,"); - if (prop & SL_FS_INFO_SECURE) - printf("Secure,"); - if (prop & SL_FS_INFO_NOT_FAILSAFE) - printf("File safe,"); - if (prop & SL_FS_INFO_SYS_FILE) - printf("System,"); - if (prop & SL_FS_INFO_NOT_VALID) - printf("No valid copy,"); - if (prop & SL_FS_INFO_PUBLIC_WRITE) - printf("Public write,"); - if (prop & SL_FS_INFO_PUBLIC_READ) - printf("Public read,"); - } - - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsGetFileList) -_i32 sl_FsGetFileList(_i32* pIndex, _u8 Count, _u8 MaxEntryLen , _u8* pBuff, SlFileListFlags_t Flags ); -#endif - -/*! - - Close the Doxygen group. - @} - - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __FS_H__ */ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netapp.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netapp.h deleted file mode 100755 index e10526907d1..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netapp.h +++ /dev/null @@ -1,1334 +0,0 @@ -/* - * netapp.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __NETAPP_H__ -#define __NETAPP_H__ - - - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup NetApp - \short Activates networking applications, such as: HTTP Server, DHCP Server, Ping, DNS and mDNS - -*/ - -/*! - - \addtogroup NetApp - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* NetApp user events */ -typedef enum -{ - SL_NETAPP_EVENT_IPV4_ACQUIRED = 1, - SL_NETAPP_EVENT_IPV6_ACQUIRED, - SL_NETAPP_EVENT_IP_COLLISION, - SL_NETAPP_EVENT_DHCPV4_LEASED, - SL_NETAPP_EVENT_DHCPV4_RELEASED, - SL_NETAPP_EVENT_HTTP_TOKEN_GET, - SL_NETAPP_EVENT_HTTP_TOKEN_POST, - SL_NETAPP_EVENT_IPV4_LOST, - SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT, - SL_NETAPP_EVENT_IPV6_LOST, - SL_NETAPP_EVENT_RESERVED1, - SL_NETAPP_EVENT_RESERVED2, - SL_NETAPP_EVENT_RESERVED3, - SL_NETAPP_EVENT_MAX -} SlNetAppEventId_e; - - -#define SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT 0x1 -#define SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT ((_u32)0x1 << 31) -#define SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT ((_u32)0x1 << 30) -#define SL_NETAPP_MDNS_OPTION_UPDATE_TEXT ((_u32)0x1 << 29) -#define SL_NETAPP_MDNS_IPV4_ONLY_SERVICE (_u32)(0) /* default mode:zero bits 27,28*/ -#define SL_NETAPP_MDNS_IPV6_ONLY_SERVICE ((_u32)0x1 << 28) -#define SL_NETAPP_MDNS_IPV6_IPV4_SERVICE ((_u32)0x1 << 27) - - -/*ERROR code*/ -#define SL_NETAPP_RX_BUFFER_LENGTH_ERROR (-230) - -/* Http Server interface */ -#define SL_NETAPP_MAX_INPUT_STRING (64) /* because of WPA */ - -#define SL_NETAPP_MAX_AUTH_NAME_LEN (20) -#define SL_NETAPP_MAX_AUTH_PASSWORD_LEN (20) -#define SL_NETAPP_MAX_AUTH_REALM_LEN (20) - -#define SL_NETAPP_MAX_DEVICE_URN_LEN (32+1) -#define SL_NETAPP_MAX_DOMAIN_NAME_LEN (24+1) - -#define SL_NETAPP_MAX_ACTION_LEN (30) -#define SL_NETAPP_MAX_TOKEN_NAME_LEN (20) - - -#define SL_NETAPP_MAX_TOKEN_VALUE_LEN SL_NETAPP_MAX_INPUT_STRING - -#define SL_NETAPP_MAX_SERVICE_TEXT_SIZE (256) -#define SL_NETAPP_MAX_SERVICE_NAME_SIZE (60) -#define SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE (64) - - -/* Server Responses */ -#define SL_NETAPP_HTTPRESPONSE_NONE (0) -#define SL_NETAPP_HTTPSETTOKENVALUE (1) - -#define SL_NETAPP_FAMILY_MASK (0x80) - -/* mDNS types */ -#define SL_NETAPP_MASK_IPP_TYPE_OF_SERVICE (0x00000001) -#define SL_NETAPP_MASK_DEVICE_INFO_TYPE_OF_SERVICE (0x00000002) -#define SL_NETAPP_MASK_HTTP_TYPE_OF_SERVICE (0x00000004) -#define SL_NETAPP_MASK_HTTPS_TYPE_OF_SERVICE (0x00000008) -#define SL_NETAPP_MASK_WORKSATION_TYPE_OF_SERVICE (0x00000010) -#define SL_NETAPP_MASK_GUID_TYPE_OF_SERVICE (0x00000020) -#define SL_NETAPP_MASK_H323_TYPE_OF_SERVICE (0x00000040) -#define SL_NETAPP_MASK_NTP_TYPE_OF_SERVICE (0x00000080) -#define SL_NETAPP_MASK_OBJECITVE_TYPE_OF_SERVICE (0x00000100) -#define SL_NETAPP_MASK_RDP_TYPE_OF_SERVICE (0x00000200) -#define SL_NETAPP_MASK_REMOTE_TYPE_OF_SERVICE (0x00000400) -#define SL_NETAPP_MASK_RTSP_TYPE_OF_SERVICE (0x00000800) -#define SL_NETAPP_MASK_SIP_TYPE_OF_SERVICE (0x00001000) -#define SL_NETAPP_MASK_SMB_TYPE_OF_SERVICE (0x00002000) -#define SL_NETAPP_MASK_SOAP_TYPE_OF_SERVICE (0x00004000) -#define SL_NETAPP_MASK_SSH_TYPE_OF_SERVICE (0x00008000) -#define SL_NETAPP_MASK_TELNET_TYPE_OF_SERVICE (0x00010000) -#define SL_NETAPP_MASK_TFTP_TYPE_OF_SERVICE (0x00020000) -#define SL_NETAPP_MASK_XMPP_CLIENT_TYPE_OF_SERVICE (0x00040000) -#define SL_NETAPP_MASK_RAOP_TYPE_OF_SERVICE (0x00080000) -#define SL_NETAPP_MASK_ALL_TYPE_OF_SERVICE (0xFFFFFFFF) - -/********************************************************************************************************/ - -/* NetApp application IDs */ -#define SL_NETAPP_HTTP_SERVER_ID (0x01) -#define SL_NETAPP_DHCP_SERVER_ID (0x02) -#define SL_NETAPP_MDNS_ID (0x04) -#define SL_NETAPP_DNS_SERVER_ID (0x08) - -#define SL_NETAPP_DEVICE_ID (0x10) -#define SL_NETAPP_DNS_CLIENT_ID (0x20) -#define SL_NETAPP_STATUS (0x40) - -/* NetApp application set/get options */ -#define SL_NETAPP_DHCP_SRV_BASIC_OPT (0) - -/* HTTP server set/get options */ -#define SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER (0) -#define SL_NETAPP_HTTP_AUTH_CHECK (1) -#define SL_NETAPP_HTTP_AUTH_NAME (2) -#define SL_NETAPP_HTTP_AUTH_PASSWORD (3) -#define SL_NETAPP_HTTP_AUTH_REALM (4) -#define SL_NETAPP_HTTP_ROM_PAGES_ACCESS (5) -#define SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER (6) -#define SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE (7) /*Enable / disable of secondary port */ -#define SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE (8) -#define SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME (9) -#define SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME (10) -#define SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME (11) -#define SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME (12) -#define SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME (13) -#define SL_NETAPP_HTTP_TIMEOUT (14) - - -#define SL_NETAPP_MDNS_CONT_QUERY_OPT (1) -#define SL_NETAPP_MDNS_QEVETN_MASK_OPT (2) -#define SL_NETAPP_MDNS_TIMING_PARAMS_OPT (3) - -/* DNS server set/get options */ -#define SL_NETAPP_DNS_OPT_DOMAIN_NAME (0) - -/* Device Config set/get options */ -#define SL_NETAPP_DEVICE_URN (0) -#define SL_NETAPP_DEVICE_DOMAIN (1) - -/* DNS client set/get options */ -#define SL_NETAPP_DNS_CLIENT_TIME (0) - -/* Get active application bimap */ -#define SL_NETAPP_STATUS_ACTIVE_APP (0) - -#ifdef SL_TINY -#define SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH (63) -#else -#define SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH (255) -#endif - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef struct -{ - _u32 Ip; - _u32 Gateway; - _u32 Dns; -}SlIpV4AcquiredAsync_t; - -typedef enum -{ - SL_BSD_IPV6_ACQUIRED_TYPE_LOCAL = 1, - SL_BSD_IPV6_ACQUIRED_TYPE_GLOBAL = 2 -}SlIpV6AcquiredAsyncType_e; - -typedef struct -{ - _u32 Ip[4]; - _u32 Dns[4]; -}SlIpV6AcquiredAsync_t; - -typedef struct -{ - _u32 IpAddress; - _u32 LeaseTime; - _u8 Mac[6]; - _u16 Padding; -}SlIpLeasedAsync_t; - -typedef struct -{ - _u32 IpAddress; - _u8 Mac[6]; - _u16 Reason; -}SlIpReleasedAsync_t; - -typedef struct -{ - _u32 IpAddress; - _u8 DhcpMac[6]; - _u8 ConflictMac[6]; -}SlIpCollisionAsync_t; - -typedef struct -{ - _i16 Status; - _u16 Padding; -}SlIpV4Lost_t; - -typedef struct -{ - _u32 IpLost[4]; -}SlIpV6Lost_t; - -typedef struct -{ - _i16 Status; - _u16 Padding; -}SlDhcpIpAcquireTimeout_t; - -typedef union -{ - SlIpV4AcquiredAsync_t IpAcquiredV4; /* SL_NETAPP_EVENT_IPV4_ACQUIRED */ - SlIpV6AcquiredAsync_t IpAcquiredV6; /* SL_NETAPP_EVENT_IPV6_ACQUIRED */ - _u32 Sd; /* SL_SOCKET_TX_FAILED_EVENT */ - SlIpLeasedAsync_t IpLeased; /* SL_NETAPP_EVENT_DHCPV4_LEASED */ - SlIpReleasedAsync_t IpReleased; /* SL_NETAPP_EVENT_DHCPV4_RELEASED */ - SlIpV4Lost_t IpV4Lost; /* SL_NETAPP_EVENT_IPV4_LOST */ - SlDhcpIpAcquireTimeout_t DhcpIpAcquireTimeout; /* SL_NETAPP_DHCP_ACQUIRE_IPV4_TIMEOUT_EVENT */ - SlIpCollisionAsync_t IpCollision; /* SL_NETAPP_EVENT_IP_COLLISION */ - SlIpV6Lost_t IpV6Lost; /* SL_NETAPP_EVENT_IPV6_LOST */ -} SlNetAppEventData_u; - -typedef struct -{ - _u32 Id; - SlNetAppEventData_u Data; -}SlNetAppEvent_t; - -typedef struct -{ - _u32 PacketsSent; - _u32 PacketsReceived; - _u16 MinRoundTime; - _u16 MaxRoundTime; - _u16 AvgRoundTime; - _u32 TestTime; -}SlNetAppPingReport_t; - -typedef struct -{ - _u32 PingIntervalTime; /* delay between pings, in milliseconds */ - _u16 PingSize; /* ping packet size in bytes */ - _u16 PingRequestTimeout; /* timeout time for every ping in milliseconds */ - _u32 TotalNumberOfAttempts; /* max number of ping requests. 0 - forever */ - _u32 Flags; /* flag - 0 report only when finished, 1 - return response for every ping, 2 - stop after 1 successful ping. 4 - ipv4 header flag - don`t fragment packet */ - _u32 Ip; /* IPv4 address or IPv6 first 4 bytes */ - _u32 Ip1OrPadding; - _u32 Ip2OrPadding; - _u32 Ip3OrPadding; -}SlNetAppPingCommand_t; - -typedef struct -{ - _u8 Len; - _u8 *pData; -} SlNetAppHttpServerString_t; - -typedef struct -{ - _u8 ValueLen; - _u8 NameLen; - _u8 *pTokenValue; - _u8 *pTokenName; -} SlNetAppHttpServerData_t; - -typedef struct -{ - SlNetAppHttpServerString_t Action; - SlNetAppHttpServerString_t TokenName; - SlNetAppHttpServerString_t TokenValue; -}SlNetAppHttpServerPostData_t; - -typedef union -{ - SlNetAppHttpServerString_t HttpTokenName; /* SL_NETAPP_HTTPGETTOKENVALUE */ - SlNetAppHttpServerPostData_t HttpPostData; /* SL_NETAPP_HTTPPOSTTOKENVALUE */ -} SlNetAppHttpServerEventData_u; - -typedef union -{ - SlNetAppHttpServerString_t TokenValue; -} SlNetAppHttpServerResponsedata_u; - -typedef struct -{ - _u32 Event; - SlNetAppHttpServerEventData_u EventData; -}SlNetAppHttpServerEvent_t; - -typedef struct -{ - _u32 Response; - SlNetAppHttpServerResponsedata_u ResponseData; -}SlNetAppHttpServerResponse_t; - -/***************************************************************************************** -* NETAPP Request/Response/Send/Receive -******************************************************************************************/ -/* TODO: check what definitions are eventually needed */ -/* NETAPP http request types */ -#define SL_NETAPP_REQUEST_HTTP_GET 1 -#define SL_NETAPP_REQUEST_HTTP_POST 2 -#define SL_NETAPP_REQUEST_HTTP_PUT 3 -#define SL_NETAPP_REQUEST_HTTP_DELETE 4 - -#define SL_NETAPP_REQUEST_MAX_METADATA_LEN 1024 -#define SL_NETAPP_REQUEST_MAX_DATA_LEN 1364 /* Metadata + Payload */ - - -typedef enum -{ - SL_NETAPP_REQUEST_METADATA_TYPE_STATUS = 0, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_VERSION, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REQUEST_URI, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_QUERY_STRING, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_TYPE, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_LOCATION, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SERVER, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_USER_AGENT, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_COOKIE, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SET_COOKIE, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_UPGRADE, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REFERER, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ACCEPT, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_ENCODING, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_DISPOSITION, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONNECTION, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ETAG, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_DATE, - SL_NETAPP_REQUEST_METADATA_TYPE_HEADER_HOST, - SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_ENCODING, - SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_LANGUAGE, - SL_NETAPP_REQUEST_METADATA_TYPE_CONTENT_LANGUAGE, - SL_NETAPP_REQUEST_METADATA_TYPE_ORIGIN, - SL_NETAPP_REQUEST_METADATA_TYPE_ORIGIN_CONTROL_ACCESS, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_NONE -} SlNetAppMetadataHTTPTypes_e; - -typedef enum -{ - SL_NETAPP_RESPONSE_NONE = 0, /* No response */ - SL_NETAPP_RESPONSE_PENDING = 1, /* status will arrive in future NetApp Send call (in metadata) */ - - SL_NETAPP_HTTP_RESPONSE_101_SWITCHING_PROTOCOLS = 101, /* 101 Switching Protocol*/ - SL_NETAPP_HTTP_RESPONSE_200_OK = 200, /* 200 OK */ - SL_NETAPP_HTTP_RESPONSE_201_CREATED = 201, /* "HTTP/1.0 201 Created" */ - SL_NETAPP_HTTP_RESPONSE_202_ACCEPTED = 202, /* "HTTP/1.0 202 Accepted" */ - SL_NETAPP_HTTP_RESPONSE_204_OK_NO_CONTENT = 204, /* 204 No Content */ - SL_NETAPP_HTTP_RESPONSE_301_MOVED_PERMANENTLY = 301, /* "HTTP/1.0 301 Moved Permanently" */ - SL_NETAPP_HTTP_RESPONSE_302_MOVED_TEMPORARILY = 302, /* 302 Moved Temporarily (http 1.0) */ - SL_NETAPP_HTTP_RESPONSE_303_SEE_OTHER = 303, /* "HTTP/1.1 303 See Other" */ - SL_NETAPP_HTTP_RESPONSE_304_NOT_MODIFIED = 304, /* "HTTP/1.0 304 Not Modified" */ - SL_NETAPP_HTTP_RESPONSE_400_BAD_REQUEST = 400, /* "HTTP/1.0 400 Bad Request" */ - SL_NETAPP_HTTP_RESPONSE_403_FORBIDDEN = 403, /* "HTTP/1.0 403 Forbidden" */ - SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND = 404, /* 404 Not Found */ - SL_NETAPP_HTTP_RESPONSE_405_METHOD_NOT_ALLOWED = 405, /* "HTTP/1.0 405 Method Not Allowed" */ - SL_NETAPP_HTTP_RESPONSE_500_INTERNAL_SERVER_ERROR = 500, /* 500 Internal Server Error */ - SL_NETAPP_HTTP_RESPONSE_503_SERVICE_UNAVAILABLE = 503, /* "HTTP/1.0 503 Service Unavailable" */ - SL_NETAPP_HTTP_RESPONSE_504_GATEWAY_TIMEOUT = 504 /* "HTTP/1.0 504 Gateway Timeout" */ -} SlNetAppResponseCode_e; - - -#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION 0x00000001 -#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA 0x00000002 /* 0 - data is payload, 1 - data is metadata */ -#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_ACCUMULATION 0x00000004 -#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_ERROR 0x80000000 /* in that case the last two bytes represents the error code */ - -typedef struct -{ - _u16 MetadataLen; - _u8 *pMetadata; - _u16 PayloadLen; - _u8 *pPayload; - _u32 Flags; -} SlNetAppData_t; - -typedef struct -{ - _u8 AppId; - _u8 Type; - _u16 Handle; - SlNetAppData_t requestData; -} SlNetAppRequest_t; - -typedef struct -{ - _u16 Status; - SlNetAppData_t ResponseData; -} SlNetAppResponse_t; - -typedef struct -{ - _u32 lease_time; - _u32 ipv4_addr_start; - _u32 ipv4_addr_last; -}SlNetAppDhcpServerBasicOpt_t; - -/* mDNS parameters */ -typedef enum -{ - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE = 1, - SL_NETAPP_FULL_SERVICE_IPV4_TYPE, - SL_NETAPP_SHORT_SERVICE_IPV4_TYPE, - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE , - SL_NETAPP_FULL_SERVICE_IPV6_TYPE, - SL_NETAPP_SHORT_SERVICE_IPV6_TYPE -} SlNetAppGetServiceListType_e; - -typedef struct -{ - _u32 service_ipv4; - _u16 service_port; - _u16 Reserved; -}SlNetAppGetShortServiceIpv4List_t; - -typedef struct -{ - _u32 service_ipv4; - _u16 service_port; - _u16 Reserved; - _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; - _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; -}SlNetAppGetFullServiceIpv4List_t; - -typedef struct -{ - _u32 service_ipv4; - _u16 service_port; - _u16 Reserved; - _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; - _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; - _u8 service_text[SL_NETAPP_MAX_SERVICE_TEXT_SIZE]; -}SlNetAppGetFullServiceWithTextIpv4List_t; - -/* IPv6 entries */ -typedef struct -{ - _u32 service_ipv6[4]; - _u16 service_port; - _u16 Reserved; -}SlNetAppGetShortServiceIpv6List_t; - -typedef struct -{ - _u32 service_ipv6[4]; - _u16 service_port; - _u16 Reserved; - _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; - _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; -}SlNetAppGetFullServiceIpv6List_t; - -typedef struct -{ - _u32 service_ipv6[4]; - _u16 service_port; - _u16 Reserved; - _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; - _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; - _u8 service_text[SL_NETAPP_MAX_SERVICE_TEXT_SIZE]; -}SlNetAppGetFullServiceWithTextIpv6List_t; - -typedef struct -{ - /*The below parameters are used to configure the advertise times and interval - For example: - If: - Period is set to T - Repetitions are set to P - Telescopic factor is K=2 - The transmission shall be: - advertise P times - wait T - advertise P times - wait 4 * T - advertise P time - wait 16 * T ... (till max time reached / configuration changed / query issued) - */ - _u32 t; /* Number of ticks for the initial period. Default is 100 ticks for 1 second. */ - _u32 p; /* Number of repetitions. Default value is 1 */ - _u32 k; /* Telescopic factor. Default value is 2. */ - _u32 RetransInterval; /* Announcing retransmission interval */ - _u32 Maxinterval; /* Announcing max period interval */ - _u32 max_time; /* Announcing max time */ -}SlNetAppServiceAdvertiseTimingParameters_t; - -typedef struct -{ - _u16 MaxResponseTime; - _u16 NumOfRetries; -}SlNetAppDnsClientTime_t; - -/*****************************************************************************/ -/* Types declarations */ -/*****************************************************************************/ -typedef void (*P_SL_DEV_PING_CALLBACK)(SlNetAppPingReport_t*); - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - - -/*! - \brief Starts a network application - - Gets and starts network application for the current WLAN mode - - \param[in] AppBitMap Application bitmap, could be one or combination of the following: - - SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_DHCP_SERVER_ID - - SL_NETAPP_MDNS_ID - - SL_NETAPP_DNS_SERVER_ID - - \par Persistent - System Persistent - \return Zero on success, or negative error code on failure - - \sa sl_NetAppStop - \note This command activates the application for the current WLAN mode (AP or STA) - \warning - \par Example - - - Starting internal HTTP server + DHCP server: - \code - sl_NetAppStart(SL_NETAPP_HTTP_SERVER_ID | SL_NETAPP_DHCP_SERVER_ID) - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppStart) -_i16 sl_NetAppStart(const _u32 AppBitMap); -#endif -/*! - \brief Stops a network application - - Gets and stops network application for the current WLAN mode - - \param[in] AppBitMap Application id, could be one of the following: \n - - SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_DHCP_SERVER_ID - - SL_NETAPP_MDNS_ID - - SL_NETAPP_DNS_SERVER_ID - - \par Persistent - System Persistent - - \return Zero on success, or nagative error code on failure - - \sa sl_NetAppStart - \note This command disables the application for the current active WLAN mode (AP or STA) - \warning - \par Example - - - Stopping internal HTTP server: - \code - sl_NetAppStop(SL_NETAPP_HTTP_SERVER_ID); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppStop) -_i16 sl_NetAppStop(const _u32 AppBitMap); -#endif - -/*! - \brief Get host IP by name\n - Obtain the IP Address of machine on network, by machine name. - - \param[in] pHostName Host name - \param[in] NameLen Name length - \param[out] OutIpAddr This parameter is filled in with - host IP address. In case that host name is not - resolved, out_ip_addr is zero. - \param[in] Family Protocol family - - \return Zero on success, or negative on failure.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system\n - In this case try again later or increase MAX_CONCURRENT_ACTIONS - Possible DNS error codes: - - SL_NETAPP_DNS_QUERY_NO_RESPONSE - - SL_NETAPP_DNS_NO_SERVER - - SL_NETAPP_DNS_QUERY_FAILED - - SL_NETAPP_DNS_MALFORMED_PACKET - - SL_NETAPP_DNS_MISMATCHED_RESPONSE - - \sa - \note Only one sl_NetAppDnsGetHostByName can be handled at a time.\n - Calling this API while the same command is called from another thread, may result - in one of the two scenarios: - 1. The command will wait (internal) until the previous command finish, and then be executed. - 2. There are not enough resources and POOL_IS_EMPTY error will return.\n - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - \warning - In case an IP address in a string format is set as input, without any prefix (e.g. "1.2.3.4") the device will not - try to access the DNS and it will return the input address on the 'out_ip_addr' field - \par Example - - - Getting host by name: - \code - _u32 DestinationIP; - _u32 AddrSize; - _i16 SockId; - SlSockAddrIn_t Addr; - - sl_NetAppDnsGetHostByName("www.google.com", strlen("www.google.com"), &DestinationIP,SL_AF_INET); - - Addr.sin_family = SL_AF_INET; - Addr.sin_port = sl_Htons(80); - Addr.sin_addr.s_addr = sl_Htonl(DestinationIP); - AddrSize = sizeof(SlSockAddrIn_t); - SockId = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByName) -_i16 sl_NetAppDnsGetHostByName(_i8 * pHostName,const _u16 NameLen, _u32* OutIpAddr,const _u8 Family ); -#endif - -/*! - \brief Return service attributes like IP address, port and text according to service name\n - The user sets a service name Full/Part (see example below), and should get: - - IP of service - - The port of service - - The text of service - Hence it can make a connection to the specific service and use it. - It is similar to sl_NetAppDnsGetHostByName method.\n - It is done by a single shot ipv4 & ipv6 (if enabled) query with PTR type on the service name. - The command that is sent is from constant parameters and variables parameters. - - \param[in] pServiceName Service name can be full or partial. \n - Example for full service name: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local \n - . - Example for partial service name: - 1. _ipp._tcp.local - 2. _ftp._tcp.local - - \param[in] ServiceLen The length of the service name (in_pService). - \param[in] Family IPv4 or IPv6 (SL_AF_INET , SL_AF_INET6). - \param[out] pAddr Contains the IP address of the service. - \param[out] pPort Contains the port of the service. - \param[out] pTextLen Has 2 options. One as Input field and the other one as output: - - Input: \n - Contains the max length of the text that the user wants to get.\n - It means that if the text len of service is bigger that its value than - the text is cut to inout_TextLen value. - - Output: \n - Contain the length of the text that is returned. Can be full text or part of the text (see above). - - \param[out] pText Contains the text of the service full or partial - - \return Zero on success,\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system, - In this case try again later or increase MAX_CONCURRENT_ACTIONS\n - In case No service is found error SL_NETAPP_DNS_NO_ANSWER will be returned - \sa sl_NetAppDnsGetHostByName - \note The returns attributes belongs to the first service found. - There may be other services with the same service name that will response to the query. - The results of these responses are saved in the peer cache of the Device and should be read by another API.\n - - Only one sl_NetAppDnsGetHostByService can be handled at a time.\n - Calling this API while the same command is called from another thread, may result - in one of the two scenarios: - 1. The command will wait (internal) until the previous command finish, and then be executed. - 2. There are not enough resources and SL_POOL_IS_EMPTY error will return. - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - - \warning Text length can be 120 bytes only -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByService) -_i16 sl_NetAppDnsGetHostByService(_i8 *pServiceName, /* string containing all (or only part): name + subtype + service */ - const _u8 ServiceLen, - const _u8 Family, /* 4-IPv4 , 16-IPv6 */ - _u32 pAddr[], - _u32 *pPort, - _u16 *pTextLen, /* in: max len , out: actual len */ - _i8 *pText - ); - -#endif - -/*! - \brief Get service list\n - Insert into out pBuffer a list of peer's services that are in the NWP without issuing any queries (relying on pervious collected data).\n - The list is in a form of service struct. The user should chose the type - of the service struct like: - - Full service parameters with text. - - Full service parameters. - - Short service parameters (port and IP only) especially for tiny hosts. - - The different types of struct are made to give the - possibility to save memory in the host.\n - - The user can also chose how many max services to get and start point index - NWP peer cache.\n - For example: - 1. Get max of 3 full services from index 0. - - Up to 3 full services from index 0 are inserted into pBuffer (services that are in indexes 0,1,2). - 2. Get max of 4 full services from index 3. - - Up to 4 full services from index 3 are inserted into pBuffer (services that are in indexes 3,4,5,6). - 3. Get max of 2 int services from index 6. - - Up to 2 int services from index 6 are inserted into pBuffer (services that are in indexes 6,7). - See below - command parameters. - - \param[in] IndexOffset - The start index in the peer cache that from it the first service is returned. - \param[in] MaxServiceCount - The Max services that can be returned if existed or if not exceed the max index - in the peer cache - \param[in] Flags - an ENUM number that means which service struct to use (means which types of service to fill) - - use SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE for SlNetAppGetFullServiceWithTextIpv4List_t - - use SL_NETAPP_FULL_SERVICE_IPV4_TYPE for SlNetAppGetFullServiceIpv4List_t - - use SL_NETAPP_SHORT_SERVICE_IPV4_TYP SlNetAppGetShortServiceIpv4List_t - - use SL_NETAPP_FULL_SERVICE_IPV6_TYPE, SlNetAppGetFullServiceIpv6List_t - - use SL_NETAPP_SHORT_SERVICE_IPV6_TYPE SlNetAppGetShortServiceIpv6List_t - - use SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE SlNetAppGetFullServiceWithTextIpv6List_t - - \param[out] pBuffer - The Services are inserted into this buffer. In the struct form according to the bit that is set in the Flags - input parameter. - - \param[in] BufferLength - The allocated buffer length (pointed by pBuffer). - - \return ServiceFoundCount - The number of the services that were inserted into the buffer.\n - Zero means no service is found negative number means an error - \sa sl_NetAppMDNSRegisterService - \note - \warning - If the out pBuffer size is bigger than an RX packet(1480), than - an error is returned because there is no place in the RX packet.\n - The size is a multiply of MaxServiceCount and size of service struct(that is set - according to flag value). -*/ - -#if _SL_INCLUDE_FUNC(sl_NetAppGetServiceList) -_i16 sl_NetAppGetServiceList(const _u8 IndexOffset, - const _u8 MaxServiceCount, - const _u8 Flags, - _i8 *pBuffer, - const _u32 BufferLength - ); - -#endif - -/*! - \brief Unregister mDNS service\n - This function deletes the mDNS service from the mDNS package and the database. - - The mDNS service that is to be unregistered is a service that the application no longer wishes to provide. \n - The service name should be the full service name according to RFC - of the DNS-SD - meaning the value in name field in the SRV answer. - - Examples for service names: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local - - \param[in] pServiceName Full service name. \n - \param[in] ServiceNameLen The length of the service. - \param[in] Options bitwise parameters: \n - - SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT bit 0 - service is unique per interface (means that the service needs to be unique) - - SL_NETAPP_MDNS_IPV6_IPV4_SERVICE bit 27 - add this service to IPv6 interface, if exist (default is IPv4 service only) - - SL_NETAPP_MDNS_IPV6_ONLY_SERVICE bit 28 - add this service to IPv6 interface, but remove it from IPv4 (only IPv6 is available) - - SL_NETAPP_MDNS_OPTION_UPDATE_TEXT bit 29 - for update text fields (without reregister the service) - - SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT bit 30 - for setting a non persistent service - - SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT bit 31 - for internal use if the service should be added or deleted (set means ADD). - - \return Zero on success, or negative error code on failure - \par Persistent - Optionally persistent - \sa sl_NetAppMDNSRegisterService - \note - \warning - The size of the service length should be smaller than 255. -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppMDNSUnRegisterService) -_i16 sl_NetAppMDNSUnRegisterService(const _i8 *pServiceName,const _u8 ServiceNameLen,_u32 Options); -#endif - -/*! - \brief Register a new mDNS service\n - This function registers a new mDNS service to the mDNS package and the DB. \n - This registered service is a service offered by the application. - The service name should be full service name according to RFC - of the DNS-SD - meaning the value in name field in the SRV answer.\n - Example for service name: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local - - If the option is_unique is set, mDNS probes the service name to make sure - it is unique before starting to announce the service on the network. - Instance is the instance portion of the service name. - - \param[in] ServiceNameLen The length of the service. - \param[in] TextLen The length of the service should be smaller than 64. - \param[in] Port The port on this target host port. - \param[in] TTL The TTL of the service - \param[in] Options bitwise parameters: \n - - SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT bit 0 - service is unique per interface (means that the service needs to be unique) - - SL_NETAPP_MDNS_IPV6_IPV4_SERVICE bit 27 - add this service to IPv6 interface, if exist (default is IPv4 service only) - - SL_NETAPP_MDNS_IPV6_ONLY_SERVICE bit 28 - add this service to IPv6 interface, but remove it from IPv4 (only IPv6 is available) - - SL_NETAPP_MDNS_OPTION_UPDATE_TEXT bit 29 - for update text fields (without reregister the service) - - SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT bit 30 - for setting a non persistent service - - SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT bit 31 - for internal use if the service should be added or deleted (set means ADD). - - \param[in] pServiceName The service name. - \param[in] pText The description of the service. - should be as mentioned in the RFC - (according to type of the service IPP,FTP...) - - \return Zero on success, or negative error code on failure - - \par Persistent - Optionally persistent - - \sa sl_NetAppMDNSUnRegisterService - - \warning 1) Temporary - there is an allocation on stack of internal buffer. - Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. \n - It means that the sum of the text length and service name length cannot be bigger than - SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.\n - If it is - An error is returned. \n - 2) According to now from certain constraints the variables parameters are set in the - attribute part (contain constant parameters) - - \par Examples: - - - Register a new service: - \code - const signed char AddService[40] = "PC1._ipp._tcp.local"; - _u32 Options; - - Options = SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT | SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT; - sl_NetAppMDNSRegisterService(AddService,sizeof(AddService),"Service 1;payper=A3;size=5",strlen("Service 1;payper=A3;size=5"),1000,120,Options); - \endcode -
- - - Update text for existing service: - \code - Please Note! Update is for text only! Important to apply the same persistent flag options as original service registration.\n - - Options = SL_NETAPP_MDNS_OPTION_UPDATE_TEXT | SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT; - sl_NetAppMDNSRegisterService(AddService,sizeof(AddService),"Service 5;payper=A4;size=10",strlen("Service 5;payper=A4;size=10"),1000,120,Options); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) -_i16 sl_NetAppMDNSRegisterService( const _i8* pServiceName, - const _u8 ServiceNameLen, - const _i8* pText, - const _u8 TextLen, - const _u16 Port, - const _u32 TTL, - _u32 Options); -#endif - -/*! - \brief send ICMP ECHO_REQUEST to network hosts - - Ping uses the ICMP protocol's mandatory ECHO_REQUEST - - \param[in] pPingParams Pointer to the ping request structure: - - If flags parameter is set to 0, ping will report back once all requested pings are done (as defined by TotalNumberOfAttempts). - - If flags parameter is set to 1, ping will report back after every ping, for TotalNumberOfAttempts. - - If flags parameter is set to 2, ping will stop after the first successful ping, and report back for the successful ping, as well as any preceding failed ones. \n - - If flags parameter is set to 4, for ipv4 - don`t fragment the ping packet. This flag can be set with other flags. - For stopping an ongoing ping activity, set parameters IP address to 0 - \param[in] Family SL_AF_INET or SL_AF_INET6 - \param[out] pReport Ping pReport - \param[out] pPingCallback Callback function upon completion.\n - If callback is NULL, the API is blocked until data arrives - - \return Zero on success, or negative error code on failure.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa - \note Only one sl_NetAppPing can be handled at a time. - Calling this API while the same command is called from another thread, may result - in one of the two scenarios: - 1. The command will wait (internal) until the previous command finish, and then be executed. - 2. There are not enough resources and SL_POOL_IS_EMPTY error will return. - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - \warning - \par Example: - - - Sending 20 ping requests and reporting results to a callback routine when - all requests are sent: - \code - // callback routine - void pingRes(SlNetAppPingReport_t* pReport) - { - // handle ping results - } - - // ping activation - void PingTest() - { - SlNetAppPingReport_t report; - SlNetAppPingCommand_t pingCommand; - - pingCommand.Ip = SL_IPV4_VAL(10,1,1,200); // destination IP address is 10.1.1.200 - pingCommand.PingSize = 150; // size of ping, in bytes - pingCommand.PingIntervalTime = 100; // delay between pings, in milliseconds - pingCommand.PingRequestTimeout = 1000; // timeout for every ping in milliseconds - pingCommand.TotalNumberOfAttempts = 20; // max number of ping requests. 0 - forever - pingCommand.Flags = 0; // report only when finished - - sl_NetAppPing( &pingCommand, SL_AF_INET, &report, pingRes ); - } - \endcode -
- - - Stopping Ping command: - \code - Status = sl_NetAppPing(0, 0, 0, 0 ); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppPing) -_i16 sl_NetAppPing(const SlNetAppPingCommand_t* pPingParams,const _u8 Family, SlNetAppPingReport_t *pReport, const P_SL_DEV_PING_CALLBACK pPingCallback); -#endif - -/*! - \brief Setting network application configurations - - \param[in] AppId Application id, could be one of the following: - - SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_DHCP_SERVER_ID (AP Role only) - - SL_NETAPP_MDNS_ID - - SL_NETAPP_DNS_SERVER_ID - - SL_NETAPP_DEVICE_ID - - SL_NETAPP_DNS_CLIENT_ID - - \param[in] Option Set option, could be one of the following: - - For SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER - - SL_NETAPP_HTTP_AUTH_CHECK - - SL_NETAPP_HTTP_AUTH_NAME - - SL_NETAPP_HTTP_AUTH_PASSWORD - - SL_NETAPP_HTTP_AUTH_REALM - - SL_NETAPP_HTTP_ROM_PAGES_ACCESS - - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER - - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE - - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE - - SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME - - SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME - - SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME - - SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME - - SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME - - SL_NETAPP_HTTP_TIMEOUT - - For SL_NETAPP_DHCP_SERVER_ID: - - SL_NETAPP_DHCP_SRV_BASIC_OPT - - For SL_NETAPP_MDNS_ID: - - SL_NETAPP_MDNS_CONT_QUERY_OPT - - SL_NETAPP_MDNS_QEVETN_MASK_OPT - - SL_NETAPP_MDNS_TIMING_PARAMS_OPT - - For SL_NETAPP_DEVICE_ID: - - SL_NETAPP_DEVICE_URN - - SL_NETAPP_DEVICE_DOMAIN - - For SL_NETAPP_DNS_CLIENT_ID: - - SL_NETAPP_DNS_CLIENT_TIME - \param[in] OptionLen Option structure length - - \param[in] pOptionValue Pointer to the option structure - - \par Persistent - \par - Reset: - - SL_NETAPP_DEVICE_DOMAIN - - SL_NETAPP_DHCP_SRV_BASIC_OPT \n - \par - Non- Persistent: - - SL_NETAPP_HTTP_TIMEOUT - - SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME - - SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME \n - \par - System Persistent: - - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER - - SL_NETAPP_HTTP_AUTH_CHECK - - SL_NETAPP_HTTP_AUTH_NAME - - SL_NETAPP_HTTP_AUTH_PASSWORD - - SL_NETAPP_HTTP_AUTH_REALM - - SL_NETAPP_HTTP_ROM_PAGES_ACCESS - - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER - - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE - - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE - - SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME - - SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME - - SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME - - SL_NETAPP_MDNS_CONT_QUERY_OPT - - SL_NETAPP_MDNS_QEVETN_MASK_OPT - - SL_NETAPP_MDNS_TIMING_PARAMS_OPT - - SL_NETAPP_DEVICE_URN - - SL_NETAPP_DEVICE_ID - - SL_NETAPP_DNS_CLIENT_ID - - \return Zero on success, or negative value if an error occurred. - \sa sl_NetAppGet - \note - \warning - \par Example - - - Setting DHCP Server (AP mode) parameters example: - \code - SlNetAppDhcpServerBasicOpt_t dhcpParams; - _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t); - dhcpParams.lease_time = 4096; // lease time (in seconds) of the IP Address - dhcpParams.ipv4_addr_start = SL_IPV4_VAL(192,168,1,10); // first IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1) - dhcpParams.ipv4_addr_last = SL_IPV4_VAL(192,168,1,16); // last IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1) - sl_NetAppStop(SL_NETAPP_DHCP_SERVER_ID); // Stop DHCP server before settings - sl_NetAppSet(SL_NETAPP_DHCP_SERVER_ID, SL_NETAPP_DHCP_SRV_BASIC_OPT, outLen, (_u8* )&dhcpParams); // set parameters - sl_NetAppStart(SL_NETAPP_DHCP_SERVER_ID); // Start DHCP server with new settings - \endcode -
- - - Setting Device URN name:
- Device name, maximum length of 32 characters - Device name affects URN name, and WPS file "device name" in WPS I.E (STA-WPS / P2P) - In case no device URN name set, the default name is "mysimplelink" - In case of setting the device name with length 0, device will return to default name "mysimplelink" - Allowed characters in device name are: 'a - z' , 'A - Z' , '0-9' and '-' - \code - _u8 *my_device = "MY-SIMPLELINK-DEV"; - sl_NetAppSet (SL_NETAPP_DEVICE_ID, SL_NETAPP_DEVICE_URN, strlen(my_device), (_u8 *) my_device); - \endcode -
- - - Register new temporary HTTP service name for MDNS (not persistent): - \code - _u8 *my_http_temp_name = "New - Bonjour Service Name"; - sl_NetAppSet (SL_NETAPP_HTTP_SERVER_ID, SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME, strlen(my_http_temp_name), (_u8 *) my_http_temp_name); - \endcode -
- - - Remove registration of current HTTP internal MDNS service (not persistent) : - \code - _u8 *old_http_name = "0800285A7891@mysimplelink-022"; - sl_NetAppSet (SL_NETAPP_HTTP_SERVER_ID, SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME, strlen(old_http_name), (_u8 *) old_http_name); - \endcode -
- - - Set DNS client time example:
- Set DNS client (sl_NetAppDnsGetHostByName) timeout, two parameters max_response_time and number_retries. - number_retries: Max number of DNS request before sl_NetAppDnsGetHostByName failed, (up to 100 retries). - max_response_time: DNS request timeout changed every retry, it`s start with 100 millisecond and increased every retry up to max_response_time milliseconds, (up to 2 seconds) - \code - SlNetAppDnsClientTime_t time; - time.MaxResponseTime = 2000; - time.NumOfRetries = 30; - sl_NetAppSet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, sizeof(time), (_u8 *)&time); - - \endcode -
- - - - Start MDNS continuous querys:
- In a continuous mDNS query mode, the device keeps sending queries to the network according to a specific service name. - The query will be sent in IPv4 and IPv6 (if enabled) format. To see the completed list of responding services sl_NetAppGetServiceList() need to be called - \code - const signed char AddService[40] = "Printer._ipp._tcp.local"; - _i16 Status; - - Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_CONT_QUERY_OPT,strlen(AddService) , &AddService); - \endcode -
- - - Stop MDNS: - \code - Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_CONT_QUERY_OPT,0 , 0); - \endcode -
- - - Set MDNS timing parameters for service advertisement:
- This option allows to control and reconfigures the timing parameters for service advertisement - \code - SlNetAppServiceAdvertiseTimingParameters_t Timing; - _i16 Status; - - Timing.t = 200; // 2 seconds - Timing.p = 2; // 2 repetitions - Timing.k = 2; // Telescopic factor 2 - Timing.RetransInterval = 0; - Timing.Maxinterval = 0xFFFFFFFF; - Timing.max_time = 5; - - Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_TIMING_PARAMS_OPT,sizeof(Timing),&Timing); - - \endcode -
- - - User-defined service types to monitor:
- In cases that the user decides not to get responses from certain - types of services it should set the adapt bit in the event mask that is related to: - \code - // bit 0: _ipp - // bit 1: _device-info - // bit 2: _http - // bit 3: _https - // bit 4: _workstation - // bit 5: _guid - // bit 6: _h323 - // bit 7: _ntp - // bit 8: _objective - // bit 9: _rdp - // bit 10: _remote - // bit 11: _rtsp - // bit 12: _sip - // bit 13: _smb - // bit 14: _soap - // bit 15: _ssh - // bit 16: _telnet - // bit 17: _tftp - // bit 18: _xmpp-client - // bit 19: _raop - - _u32 EventMask; - _i16 Status; - - EventMask = BIT0 | BIT1 | BIT18; - Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_QEVETN_MASK_OPT,sizeof(EventMask),&EventMask); - \endcode -
-*/ -#if _SL_INCLUDE_FUNC(sl_NetAppSet) -_i16 sl_NetAppSet(const _u8 AppId ,const _u8 Option,const _u8 OptionLen,const _u8 *pOptionValue); -#endif - -/*! - \brief Getting network applications configurations - - \param[in] AppId Application id, could be one of the following: \n - - SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_DHCP_SERVER_ID - - SL_NETAPP_DNS_SERVER_ID - - SL_NETAPP_DEVICE_ID - - SL_NETAPP_DNS_CLIENT_ID - - \param[in] Option Get option, could be one of the following: \n - - SL_NETAPP_DHCP_SERVER_ID: - - SL_NETAPP_DHCP_SRV_BASIC_OPT - - SL_NETAPP_HTTP_SERVER_ID: - - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER - - SL_NETAPP_HTTP_AUTH_CHECK - - SL_NETAPP_HTTP_AUTH_NAME - - SL_NETAPP_HTTP_AUTH_PASSWORD - - SL_NETAPP_HTTP_AUTH_REALM - - SL_NETAPP_HTTP_ROM_PAGES_ACCESS - - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER - - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE - - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE - - SL_NETAPP_MDNS_ID: - - SL_NETAPP_MDNS_CONT_QUERY_OPT - - SL_NETAPP_MDNS_QEVETN_MASK_OPT - - SL_NETAPP_MDNS_TIMING_PARAMS_OPT - - SL_NETAPP_DEVICE_ID: - - SL_NETAPP_DEVICE_URN - - SL_NETAPP_DEVICE_DOMAIN - - SL_NETAPP_DNS_CLIENT_ID: - - SL_NETAPP_DNS_CLIENT_TIME - - \param[in] pOptionLen The length of the allocated memory as input, when the - function complete, the value of this parameter would be - the len that actually read from the device.\n - If the device return length that is longer from the input - value, the function will cut the end of the returned structure - and will return ESMALLBUF - - \param[out] pOptionValue pointer to the option structure which will be filled with the response from the device - - \return Zero on success, or negative value if an error occurred. - - \sa sl_NetAppSet - \note - \warning - \par Example - - - Getting DHCP Server parameters example: - \code - SlNetAppDhcpServerBasicOpt_t dhcpParams; - _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t); - sl_NetAppGet(SL_NETAPP_DHCP_SERVER_ID, SL_NETAPP_SET_DHCP_SRV_BASIC_OPT, &outLen, (_u8* )&dhcpParams); - - printf("DHCP Start IP %d.%d.%d.%d End IP %d.%d.%d.%d Lease time seconds %d\n", - SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,3),SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,2), - SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,1),SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,0), - SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,3),SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,2), - SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,1),SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,0), - dhcpParams.lease_time); - \endcode -
- - - Getting device URN name:
- Maximum length of 32 characters of device name. - Device name affects URN name, own SSID name in AP mode, and WPS file "device name" in WPS I.E (STA-WPS / P2P) - in case no device URN name set, the default name is "mysimplelink" - \code - _u8 my_device_name[SL_NETAPP_MAX_DEVICE_URN_LEN]; - sl_NetAppGet (SL_NETAPP_DEVICE_ID, SL_NETAPP_DEVICE_URN, strlen(my_device_name), (_u8 *)my_device_name); - \endcode -
- - - Getting DNS client time:
- Get DNS client (sl_NetAppDnsGetHostByName) timeout, two parameters max_response_time and number_retries. - number_retries: Max number of DNS request before sl_NetAppDnsGetHostByName failed. - max_response_time: DNS request timeout changed every retry, it`s start with 100 millisecond and increased every retry up to max_response_time milliseconds - \code - SlNetAppDnsClientTime_t time; - _u8 pOptionLen = sizeof(time); - sl_NetAppGet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, &pOptionLen, (_u8 *)&time); - \endcode -
- - - - Getting active applications:
- Get active applications for active role. return value is mask of the active application (similar defines as sl_NetAppStart\sl_NetAppStop): - \code - _u32 AppBitMap; - _u8 pOptionLen = sizeof(AppBitMap); - sl_NetAppGet (SL_NETAPP_STATUS, SL_NETAPP_STATUS_ACTIVE_APP, &pOptionLen, (_u8 *)&AppBitMap); - - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppGet) -_i16 sl_NetAppGet(const _u8 AppId, const _u8 Option,_u8 *pOptionLen, _u8 *pOptionValue); -#endif - -/*! - \brief Function for sending Netapp response or data following a Netapp request event (i.e. HTTP GET request) - - - \param[in] Handle Handle to send the data to. Should match the handle received in the Netapp request event - \param[in] DataLen Data Length - \param[in] pData Data to send. Can be just data payload or metadata (depends on flags) - \param[out] Flags Can have the following values: - - SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION - More data will arrive in subsequent calls to NetAppSend - - SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA - 0 - data is payload, 1 - data is metadata - - SL_NETAPP_REQUEST_RESPONSE_FLAGS_ACCUMULATION - The network processor should accumulate the data chunks and will process it when it is completelly received - - \return Zero on success, or negative error code on failure - - \sa sl_NetAppRecv - \note - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppSend) -_u16 sl_NetAppSend( _u16 Handle, _u16 DataLen, _u8 *pData, _u32 Flags); -#endif - -/*! - \brief Function for retrieving data from the network processor following a Netapp request event (i.e. HTTP POST request) - - \param[in] Handle Handle to receive data from. Should match the handle received in the Netapp request event - \param[in,out] *DataLen Max buffer size (in) / Actual data received (out) - \param[out] *pData Data received - \param[in,out] *Flags Can have the following values: - - SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION (out) - - More data is pending in the network processor. Application should continue reading the data by calling sl_NetAppRecv again - - \return Zero on success, or negative error code on failure - - \sa sl_NetAppSend - \note - \warning handle is received in the sl_NetAppRequestHandler callback. Handle is valid until all data is receive from the network processor. -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppRecv) -_SlReturnVal_t sl_NetAppRecv( _u16 Handle, _u16 *DataLen, _u8 *pData, _u32 *Flags); -#endif - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NETAPP_H__ */ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netcfg.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netcfg.h deleted file mode 100755 index 26c9ef8ba1e..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netcfg.h +++ /dev/null @@ -1,663 +0,0 @@ -/* - * netcfg.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - - -#ifndef __NETCFG_H__ -#define __NETCFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup NetCfg - \short Controls the configuration of the device addresses (i.e. IP and MAC addresses) - -*/ - -/*! - - \addtogroup NetCfg - @{ - -*/ - - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SL_MAC_ADDR_LEN (6) -#define SL_IPV6_ADDR_LEN (16) -#define SL_IPV4_VAL(add_3,add_2,add_1,add_0) ((((_u32)add_3 << 24) & 0xFF000000) | (((_u32)add_2 << 16) & 0xFF0000) | (((_u32)add_1 << 8) & 0xFF00) | ((_u32)add_0 & 0xFF) ) -#define SL_IPV6_VAL(add_1,add_2) ((((_u32)add_1 << 16) & 0xFFFF0000) | (((_u32)add_2 ) & 0x0000FFFF) ) -#define SL_IPV4_BYTE(val,index) ( (val >> (index*8)) & 0xFF ) - - -#define SL_NETCFG_IF_IPV6_STA_LOCAL (0x4) /* disable ipv6 local */ -#define SL_NETCFG_IF_IPV6_STA_GLOBAL (0x8) /* disable ipv6 global */ -#define SL_NETCFG_IF_DISABLE_IPV4_DHCP (0x40) /* disable ipv4 dhcp */ -#define SL_NETCFG_IF_IPV6_LOCAL_STATIC (0x80) /* enable ipv6 local static */ -#define SL_NETCFG_IF_IPV6_LOCAL_STATELESS (0x100) /* enable ipv6 local stateless */ -#define SL_NETCFG_IF_IPV6_LOCAL_STATEFUL (0x200) /* enable ipv6 local statefull */ -#define SL_NETCFG_IF_IPV6_GLOBAL_STATIC (0x400) /* enable ipv6 global static */ -#define SL_NETCFG_IF_IPV6_GLOBAL_STATEFUL (0x800) /* enable ipv6 global statefull */ -#define SL_NETCFG_IF_DISABLE_IPV4_LLA (0x1000) /* disable LLA feature. Relevant only in IPV4 */ -#define SL_NETCFG_IF_ENABLE_DHCP_RELEASE (0x2000) /* Enables DHCP release when WLAN disconnect command is issued */ -#define SL_NETCFG_IF_IPV6_GLOBAL_STATELESS (0x4000) /* enable ipv6 global stateless */ -#define SL_NETCFG_IF_DISABLE_FAST_RENEW (0x8000) /* fast renew disabled */ - - -#define SL_NETCFG_IF_STATE (0) -#define SL_NETCFG_ADDR_DHCP (1) -#define SL_NETCFG_ADDR_DHCP_LLA (2) -#define SL_NETCFG_ADDR_STATIC (4) -#define SL_NETCFG_ADDR_STATELESS (5) -#define SL_NETCFG_ADDR_STATEFUL (6) -#define SL_NETCFG_ADDR_RELEASE_IP_SET (7) -#define SL_NETCFG_ADDR_RELEASE_IP_OFF (8) -#define SL_NETCFG_ADDR_ENABLE_FAST_RENEW (9) -#define SL_NETCFG_ADDR_DISABLE_FAST_RENEW (10) -#define SL_NETCFG_ADDR_FAST_RENEW_MODE_NO_WAIT_ACK (11) -#define SL_NETCFG_ADDR_FAST_RENEW_MODE_WAIT_ACK (12) - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ -typedef enum -{ - SL_NETCFG_MAC_ADDRESS_SET = 1, - SL_NETCFG_MAC_ADDRESS_GET = 2, - SL_NETCFG_AP_STATIONS_NUM_CONNECTED = 3, - SL_NETCFG_AP_STATIONS_INFO_LIST = 4, - SL_NETCFG_AP_STATION_DISCONNECT = 5, - SL_NETCFG_IF = 6, - SL_NETCFG_IPV4_STA_ADDR_MODE = 7, - SL_NETCFG_IPV4_AP_ADDR_MODE = 8, - SL_NETCFG_IPV6_ADDR_LOCAL = 9, - SL_NETCFG_IPV6_ADDR_GLOBAL = 10, - SL_NETCFG_IPV4_DHCP_CLIENT = 11, - SL_NETCFG_IPV4_DNS_CLIENT = 12, - SL_NETCFG_RESERVED = 13, - MAX_SETTINGS = 0xFF -}SlNetCfg_e; - -typedef struct -{ - _u32 DnsSecondServerAddr; -}SlNetCfgIpV4DnsClientArgs_t; - - -typedef struct -{ - _u32 Ip; - _u32 Gateway; - _u32 Mask; - _u32 Dns[2]; - _u32 DhcpServer; - _u32 LeaseTime; - _u32 TimeToRenew; - _u8 DhcpState; - _u8 Reserved[3]; -} SlNetCfgIpv4DhcpClient_t; - -typedef enum -{ - SL_NETCFG_DHCP_CLIENT_UNKNOWN = 0, - SL_NETCFG_DHCP_CLIENT_DISABLED, - SL_NETCFG_DHCP_CLIENT_ENABLED, - SL_NETCFG_DHCP_CLIENT_BOUND, - SL_NETCFG_DHCP_CLIENT_RENEW, - SL_NETCFG_DHCP_CLIENT_REBIND -}SlNetCfgIpv4DhcpClientState_e; - - -typedef enum -{ - SL_NETCFG_DHCP_OPT_DISABLE_LLA = 0x2, /* 1=LLA disabled, 0=LLA enabled. */ - SL_NETCFG_DHCP_OPT_RELEASE_IP_BEFORE_DISCONNECT = 0x4, /* 1=DHCP release enabled, 0=DHCP release disabled */ - MAX_SL_NETCFG_DHCP_OPT = 0xFF -} SlNetCfgDhcpOption_e; - -typedef struct -{ - _u32 Ip; - _u32 IpMask; - _u32 IpGateway; - _u32 IpDnsServer; -}SlNetCfgIpV4Args_t; - -typedef struct -{ - _u32 Ip[4]; - _u32 IpDnsServer[4]; - _u32 IpV6Flags; /* bit 0: Indicate if the address is valid for use in the network (IPv6 DAD completed) . If not, try again later or set a different address. 1=Valid. Relevant for sl_NetCfgGet only. */ -}SlNetCfgIpV6Args_t; - -#define _SL_NETCFG_IPV6_ADDR_BIT_STATUS 0x01 -#define SL_IS_IPV6_ADDR_VALID(IpV6Flags) (IpV6Flags & _SL_NETCFG_IPV6_ADDR_BIT_STATUS) - -#define NET_CFG_STA_INFO_STATUS_DHCP_ADDR 1 - -typedef struct -{ - _u32 Ip; - _u8 MacAddr[6]; - _u16 Status; - _u8 Name[32]; -} SlNetCfgStaInfo_t; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - \brief Setting network configurations - - \param[in] ConfigId Configuration id: - - SL_NETCFG_IF - - SL_NETCFG_IPV4_STA_ADDR_MODE - - SL_NETCFG_IPV6_ADDR_LOCAL - - SL_NETCFG_IPV6_ADDR_GLOBAL - - SL_NETCFG_IPV4_AP_ADDR_MODE - - SL_NETCFG_MAC_ADDRESS_SET - - SL_NETCFG_AP_STATION_DISCONNECT - \param[in] ConfigOpt Configurations option: - - SL_NETCFG_IF_STATE - - SL_NETCFG_ADDR_DHCP - - SL_NETCFG_ADDR_DHCP_LLA - - SL_NETCFG_ADDR_STATIC - - SL_NETCFG_ADDR_STATELESS - - SL_NETCFG_ADDR_STATEFUL - - SL_NETCFG_ADDR_RELEASE_IP_SET - - SL_NETCFG_ADDR_RELEASE_IP_OFF - \param[in] ConfigLen Configurations len - \param[in] pValues Configurations values - \par Persistent - \par - Reset: - - SL_NETCFG_MAC_ADDRESS_SET - - SL_NETCFG_IPV4_AP_ADDR_MODE - \par - Non- Persistent: - - SL_NETCFG_AP_STATION_DISCONNECT - \par - System Persistent: - - SL_NETCFG_IPV4_STA_ADDR_MODE - - SL_NETCFG_IF - - SL_NETCFG_IPV6_ADDR_LOCAL - - SL_NETCFG_IPV6_ADDR_GLOBAL - - \return Non-negative value on success, or -1 for failure - \sa sl_NetCfgGet - \note - \warning - - \par Examples - - - SL_NETCFG_MAC_ADDRESS_SET:
- Setting MAC address to the Device. - The new MAC address will override the default MAC address and it be saved in the FileSystem. - Requires restarting the device for updating this setting. - \code - _u8 MAC_Address[6]; - MAC_Address[0] = 0x8; - MAC_Address[1] = 0x0; - MAC_Address[2] = 0x28; - MAC_Address[3] = 0x22; - MAC_Address[4] = 0x69; - MAC_Address[5] = 0x31; - sl_NetCfgSet(SL_NETCFG_MAC_ADDRESS_SET,1,SL_MAC_ADDR_LEN,(_u8 *)MAC_Address); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV4_STA_ADDR_MODE
: - Setting/Releasing a DHCP/DHCP LLA /STATIC STA IP address - - - SL_NETCFG_ADDR_STATIC:
- Setting a static IP address to the device working in STA mode or P2P client. - The IP address will be stored in the FileSystem. - \code - SlNetCfgIpV4Args_t ipV4; - ipV4.Ip = (_u32)SL_IPV4_VAL(10,1,1,201); // _u32 IP address - ipV4.IpMask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this STA/P2P - ipV4.IpGateway = (_u32)SL_IPV4_VAL(10,1,1,1); // _u32 Default gateway address - ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(8,16,32,64); // _u32 DNS server address - - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV4Args_t),(_u8 *)&ipV4); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_ADDR_DHCP:
- Setting IP address by DHCP to FileSystem using WLAN sta mode or P2P client. - This should be done once if using Serial Flash. - This is the system's default mode for acquiring an IP address after WLAN connection. - \code - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_DHCP,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_ADDR_DHCP_LLA:
- Setting DHCP LLA will runs LLA mechanism in case DHCP fails to acquire an address - SL_NETCFG_DHCP_OPT_RELEASE_IP_BEFORE_DISCONNECT - If set, enables sending a DHCP release frame to the server if user issues a WLAN disconnect command. - \code - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_DHCP_LLA,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_ADDR_RELEASE_IP_SET:
- Setting release ip before disconnect enables sending a DHCP release frame to the server if user issues a WLAN disconnect command. - \code - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_RELEASE_IP_SET,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_ADDR_RELEASE_IP_OFF:
- Setting release ip before disconnect disables sending a DHCP release frame to the server if user issues a WLAN disconnect command. - \code - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_RELEASE_IP_OFF,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV4_AP_ADDR_MODE:
- Setting a static IP address to the device working in AP mode or P2P go. - The IP address will be stored in the FileSystem. Requires restart. - \code - SlNetCfgIpV4Args_t ipV4; - ipV4.Ip = (_u32)SL_IPV4_VAL(10,1,1,201); // _u32 IP address - ipV4.IpMask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this AP/P2P - ipV4.IpGateway = (_u32)SL_IPV4_VAL(10,1,1,1); // _u32 Default gateway address - ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(8,16,32,64); // _u32 DNS server address - - sl_NetCfgSet(SL_NETCFG_IPV4_AP_ADDR_MODE,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV4Args_t),(_u8 *)&ipV4); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IF:
- Enable\Disable IPV6 interface - Local or/and Global address (Global could not be enabled without Local) - \code - _u32 IfBitmap = 0; - - IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL | SL_NETCFG_IF_IPV6_STA_GLOBAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_LOCAL:
- Setting a IPv6 Local static address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - SlNetCfgIpV6Args_t ipV6; - _u32 IfBitmap = 0; - - IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - - ipV6.Ip[0] = 0xfe800000; - ipV6.Ip[1] = 0x00000000; - ipV6.Ip[2] = 0x00004040; - ipV6.Ip[3] = 0x0000ce65; - - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV6Args_t),(_u8 *)&ipV6); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_LOCAL:
- Setting a IPv6 Local stateless address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - _u32 IfBitmap = 0; - IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATELESS,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_LOCAL:
- Setting a IPv6 Local statefull address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - _u32 IfBitmap = 0; - - IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATEFUL,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_GLOBAL:
- Setting a IPv6 Global static address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - SlNetCfgIpV6Args_t ipV6; - _u32 IfBitmap = 0; - - ipV6.Ip[0] = 0xfe80; - ipV6.Ip[1] = 0x03a; - ipV6.Ip[2] = 0x4040; - ipV6.Ip[3] = 0xce65; - - ipV6.IpDnsServer[0] = 0xa780; - ipV6.IpDnsServer[1] = 0x65e; - ipV6.IpDnsServer[2] = 0x8; - ipV6.IpDnsServer[3] = 0xce00; - - IfBitmap = SL_NETCFG_IF_IPV6_STA_GLOBAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_GLOBAL,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV6Args_t),(_u8 *)&ipV6); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_GLOBAL:
- Setting a IPv6 Global statefull address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - _u32 IfBitmap = 0; - IfBitmap = SL_NETCFG_IF_IPV6_STA_GLOBAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_GLOBAL,SL_NETCFG_ADDR_STATEFUL,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_AP_STATION_DISCONNECT:
- Disconnect AP station by mac address. - The AP connected stations list can be read by sl_NetCfgGet with options: SL_AP_STATIONS_NUM_CONNECTED, SL_AP_STATIONS_INFO_LIST - \code - _u8 ap_sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; - sl_NetCfgSet(SL_NETCFG_AP_STATION_DISCONNECT,1,SL_MAC_ADDR_LEN,(_u8 *)ap_sta_mac); - \endcode -
- - - SL_NETCFG_IPV4_DNS_CLIENT:
- Set additional IPv4 DNS address - \code - _i32 Status; - SlNetCfgIpV4DnsClientArgs_t DnsOpt; - DnsOpt.DnsSecondServerAddr = SL_IPV4_VAL(8,8,8,8); ; - Status = sl_NetCfgSet(SL_NETCFG_IPV4_DNS_CLIENT,0,sizeof(SlNetCfgIpV4DnsClientArgs_t),(unsigned char *)&DnsOpt); - if( Status ) - { - // error - } - \endcode -
- -*/ -#if _SL_INCLUDE_FUNC(sl_NetCfgSet) -_i16 sl_NetCfgSet(const _u16 ConfigId,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues); -#endif - - -/*! - \brief Getting network configurations - - \param[in] ConfigId Configuration id - - \param[out] pConfigOpt Get configurations option - - \param[out] pConfigLen The length of the allocated memory as input, when the - function complete, the value of this parameter would be - the len that actually read from the device.\n - If the device return length that is longer from the input - value, the function will cut the end of the returned structure - and will return ESMALLBUF - - \param[out] pValues - get configurations values - \return Zero on success, or -1 on failure - \sa sl_NetCfgSet - \note - \warning - \par Examples - - - SL_NETCFG_MAC_ADDRESS_GET:
- Get the device MAC address. - The returned MAC address is taken from FileSystem first. If the MAC address was not set by SL_MAC_ADDRESS_SET, the default MAC address - is retrieved from HW. - \code - _u8 macAddressVal[SL_MAC_ADDR_LEN]; - _u16 macAddressLen = SL_MAC_ADDR_LEN; - _u16 ConfigOpt = 0; - sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,&ConfigOpt,&macAddressLen,(_u8 *)macAddressVal); - \endcode -
- - - SL_NETCFG_IPV4_STA_ADDR_MODE:
- Get IP address from WLAN station or P2P client. A DHCP flag is returned to indicate if the IP address is static or from DHCP. - \code - _u16 len = sizeof(SlNetCfgIpV4Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC - SlNetCfgIpV4Args_t ipV4 = {0}; - sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&len,(_u8 *)&ipV4); - - printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", - (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", - SL_IPV4_BYTE(ipV4.Ip,3),SL_IPV4_BYTE(ipV4.Ip,2),SL_IPV4_BYTE(ipV4.Ip,1),SL_IPV4_BYTE(ipV4.Ip,0), - SL_IPV4_BYTE(ipV4.IpMask,3),SL_IPV4_BYTE(ipV4.IpMask,2),SL_IPV4_BYTE(ipV4.IpMask,1),SL_IPV4_BYTE(ipV4.IpMask,0), - SL_IPV4_BYTE(ipV4.IpGateway,3),SL_IPV4_BYTE(ipV4.IpGateway,2),SL_IPV4_BYTE(ipV4.IpGateway,1),SL_IPV4_BYTE(ipV4.IpGateway,0), - SL_IPV4_BYTE(ipV4.IpDnsServer,3),SL_IPV4_BYTE(ipV4.IpDnsServer,2),SL_IPV4_BYTE(ipV4.IpDnsServer,1),SL_IPV4_BYTE(ipV4.IpDnsServer,0)); - \endcode -
- - - SL_NETCFG_IPV4_AP_ADDR_MODE:
- Get static IP address for AP or P2P go. - \code - _u16 len = sizeof(SlNetCfgIpV4Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC - SlNetCfgIpV4Args_t ipV4 = {0}; - sl_NetCfgGet(SL_NETCFG_IPV4_AP_ADDR_MODE,&ConfigOpt,&len,(_u8 *)&ipV4); - - printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", - (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", - SL_IPV4_BYTE(ipV4.Ip,3),SL_IPV4_BYTE(ipV4.Ip,2),SL_IPV4_BYTE(ipV4.Ip,1),SL_IPV4_BYTE(ipV4.Ip,0), - SL_IPV4_BYTE(ipV4.IpMask,3),SL_IPV4_BYTE(ipV4.IpMask,2),SL_IPV4_BYTE(ipV4.IpMask,1),SL_IPV4_BYTE(ipV4.IpMask,0), - SL_IPV4_BYTE(ipV4.IpGateway,3),SL_IPV4_BYTE(ipV4.IpGateway,2),SL_IPV4_BYTE(ipV4.IpGateway,1),SL_IPV4_BYTE(ipV4.IpGateway,0), - SL_IPV4_BYTE(ipV4.IpDnsServer,3),SL_IPV4_BYTE(ipV4.IpDnsServer,2),SL_IPV4_BYTE(ipV4.IpDnsServer,1),SL_IPV4_BYTE(ipV4.IpDnsServer,0)); - \endcode -
- - - SL_NETCFG_IF:
- Get interface bitmap - \code - _u16 len; - _u32 IfBitmap; - len = sizeof(IfBitmap); - sl_NetCfgGet(SL_NETCFG_IF,NULL,&len,(_u8 *)&IfBitmap); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_LOCAL:
- Get IPV6 Local address (ipV6.ipV6IsValid holds the address status. 1=Valid, ipv6 DAD completed and address is valid for use) - \code - SlNetCfgIpV6Args_t ipV6; - _u16 len = sizeof(SlNetCfgIpV6Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_STATIC / SL_NETCFG_ADDR_STATELESS / SL_NETCFG_ADDR_STATEFUL - - sl_NetCfgGet(SL_NETCFG_IPV6_ADDR_LOCAL,&ConfigOpt,&len,(_u8 *)&ipV6); - if (SL_IS_IPV6_ADDR_VALID(ipV6.IpV6Flags)) - { - printf("Ipv6 Local Address is valid: %8x:%8x:%8x:%8x\n", ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0]); - } - else - { - printf("Ipv6 Local Address is not valid, wait for DAD to complete or configure a different address"); - } - - \endcode -
- - - SL_NETCFG_IPV6_ADDR_GLOBAL:
- Get IPV6 Global address (ipV6.ipV6IsValid holds the address status. 1=Valid, ipv6 DAD completed and address is valid for use) - \code - SlNetCfgIpV6Args_t ipV6; - _u16 len = sizeof(SlNetCfgIpV6Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_STATIC / SL_NETCFG_ADDR_STATEFUL - - if (SL_IS_IPV6_ADDR_VALID(ipV6.IpV6Flags)) - { - printf("Ipv6 Global Address is valid: %8x:%8x:%8x:%8x\n", ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0]); - } - else - { - printf("Ipv6 Global Address is not valid, wait for DAD to complete or configure a different address"); - } - - \endcode -
- - - SL_NETCFG_AP_STATIONS_NUM_CONNECTED:
- Get AP number of connected stations. - \code - _u8 num_ap_connected_sta; - _u16 len = sizeof(num_ap_connected_sta); - sl_NetCfgGet(SL_NETCFG_AP_STATIONS_NUM_CONNECTED, NULL, &len, &num_ap_connected_sta); - printf("AP number of connected stations = %d\n", num_ap_connected_sta); - - \endcode -
- - - SL_NETCFG_AP_STATIONS_INFO_LIST:
- Get AP full list of connected stationss. - \code - SlNetCfgStaInfo_t ApStaList[4]; - _u16 sta_info_len; - _u16 start_sta_index = 0; - int actual_num_sta; - int i; - - start_sta_index = 0; - sta_info_len = sizeof(ApStaList); - sl_NetCfgGet(SL_NETCFG_AP_STATIONS_INFO_LIST, &start_sta_index, &sta_info_len, (_u8 *)ApStaList); - - actual_num_sta = sta_info_len / sizeof(SlNetCfgStaInfo_t); - printf("-Print SL_NETCFG_AP_STATIONS_INFO_LIST actual num_stations = %d (upon sta_info_len = %d)\n", actual_num_sta, sta_info_len); - - for (i=0; iName); - printf(" MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", staInfo->MacAddr[0], staInfo->MacAddr[1], staInfo->MacAddr[2], staInfo->MacAddr[3], staInfo->MacAddr[4], staInfo->MacAddr[5]); - printf(" IP: %d.%d.%d.%d\n", SL_IPV4_BYTE(staInfo->Ip,3), SL_IPV4_BYTE(staInfo->Ip,2), SL_IPV4_BYTE(staInfo->Ip,1), SL_IPV4_BYTE(staInfo->Ip,0)); - } - - \endcode -
- - - SL_NETCFG_IPV4_DNS_CLIENT:
- Get secondary DNS address (DHCP and static configuration) - \code - _u16 ConfigOpt = 0; - _i32 Status; - _u16 pConfigLen = sizeof(SlNetCfgIpV4DnsClientArgs_t); - SlNetCfgIpV4DnsClientArgs_t DnsOpt; - Status = sl_NetCfgGet(SL_NETCFG_IPV4_DNS_CLIENT,&ConfigOpt,&pConfigLen,&DnsOpt); - if( Status ) - { - // error - } - \endcode -
- - - - SL_NETCFG_IPV4_DHCP_CLIENT:
- Get DHCP Client info - \code - _u16 ConfigOpt = 0; - _u16 pConfigLen = sizeof(SlNetCfgIpv4DhcpClient_t); - SlNetCfgIpv4DhcpClient_t dhcpCl; - SlNetCfgIpV4Args_t ipV4 = {0}; - - ret = sl_NetCfgGet(SL_NETCFG_IPV4_DHCP_CLIENT, &ConfigOpt, &pConfigLen, (_u8 *)&dhcpCl); - if(ret < 0) - { - printf("Error = %d\n", ret); - } - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_NetCfgGet) -_i16 sl_NetCfgGet(const _u16 ConfigId ,_u16 *pConfigOpt, _u16 *pConfigLen, _u8 *pValues); -#endif - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NETCFG_H__ */ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netutil.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netutil.h deleted file mode 100755 index f5b31b6ba0e..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netutil.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * netutil.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef __NETUTIL_H__ -#define __NETUTIL_H__ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup NetUtil - \short Networking related commands and configuration - -*/ - -/*! - - \addtogroup NetUtil - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* Set/get options */ -#define SL_NETUTIL_CRYPTO_PUBLIC_KEY (1) -#define SL_NETUTIL_CRYPTO_PUBLIC_KEY_INFO (2) -#define SL_NETUTIL_TRUE_RANDOM (3) - -/* Commands */ -#define SL_NETUTIL_CRYPTO_CMD_CREATE_CERT (1) -#define SL_NETUTIL_CRYPTO_CMD_SIGN_MSG (2) -#define SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG (3) -#define SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS (4) -#define SL_NETUTIL_CRYPTO_CMD_INSTALL_OP (5) -#define SL_NETUTIL_CMD_ARP_LOOKUP (6) - -/*****************************************************************************/ -/* Errors returned from the general error async event */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef struct -{ - _u8 *pOutputValues; - _u16 *pOutputLen; - _i16 Status; -}_SlNetUtilCmdData_t; - -/* Defines the size of the buffer that will be allocated */ -/* (on the stack) by the sl_UtilsCmd API. */ -#define SL_NETUTIL_CMD_BUFFER_SIZE (256) - -/* Enumeration of Signature types */ -#define SL_NETUTIL_CRYPTO_SIG_SHAwDSA (0) -#define SL_NETUTIL_CRYPTO_SIG_MD2wRSA (1) -#define SL_NETUTIL_CRYPTO_SIG_MD5wRSA (2) -#define SL_NETUTIL_CRYPTO_SIG_SHAwRSA (3) -#define SL_NETUTIL_CRYPTO_SIG_SHAwECDSA (4) -#define SL_NETUTIL_CRYPTO_SIG_SHA256wRSA (5) -#define SL_NETUTIL_CRYPTO_SIG_SHA256wECDSA (6) -#define SL_NETUTIL_CRYPTO_SIG_SHA384wRSA (7) -#define SL_NETUTIL_CRYPTO_SIG_SHA384wECDSA (8) -#define SL_NETUTIL_CRYPTO_SIG_SHA512wRSA (9) -#define SL_NETUTIL_CRYPTO_SIG_SHA512wECDSA (10) -#define SL_NETUTIL_CRYPTO_SIG_DIGESTwECDSA (11) -/* Add more signature-Types here */ - -/* Digest length definitions */ -#define SL_NETUTIL_CRYPTO_DGST_MD2_LEN_BYTES (16) -#define SL_NETUTIL_CRYPTO_DGST_MD5_LEN_BYTES (16) -#define SL_NETUTIL_CRYPTO_DGST_SHA_LEN_BYTES (20) -#define SL_NETUTIL_CRYPTO_DGST_SHA256_LEN_BYTES (32) -#define SL_NETUTIL_CRYPTO_DGST_SHA384_LEN_BYTES (48) -#define SL_NETUTIL_CRYPTO_DGST_SHA512_LEN_BYTES (64) - - -/* Enumeration of Create-Certificate sub-commands */ -#define SL_NETUTIL_CRYPTO_CERT_INIT (1) -#define SL_NETUTIL_CRYPTO_CERT_SIGN_AND_SAVE (2) -#define SL_NETUTIL_CRYPTO_CERT_VER (3) -#define SL_NETUTIL_CRYPTO_CERT_SERIAL (4) -#define SL_NETUTIL_CRYPTO_CERT_SIG_TYPE (5) -#define SL_NETUTIL_CRYPTO_CSR_SIGN_AND_SAVE (6) -#if 0 /* reserved for Issuer information - currently not supported */ -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_COUNTRY (6) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_STATE (7) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_LOCALITY (8) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_SUR (9) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_ORG (10) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_ORG_UNIT (11) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_COMMON_NAME (12) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_EMAIL (13) -#endif /* End - issuer information */ -#define SL_NETUTIL_CRYPTO_CERT_DAYS_VALID (14) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_COUNTRY (15) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_STATE (16) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_LOCALITY (17) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_SUR (18) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_ORG (19) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_ORG_UNIT (20) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_COMMON_NAME (21) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_EMAIL (22) -#define SL_NETUTIL_CRYPTO_CERT_IS_CA (23) - - -/* Enumeration of "Temp-Keys" commands */ -#define SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE (1) -#define SL_NETUTIL_CRYPTO_TEMP_KEYS_REMOVE (2) - -/* Enumeration of "Install/Uninstall" sub-commands */ -#define SL_NETUTIL_CRYPTO_INSTALL_SUB_CMD (1) -#define SL_NETUTIL_CRYPTO_UNINSTALL_SUB_CMD (2) - - -/* The reserved key for IOT Usage */ -#define SL_NETUTIL_CRYPTO_SERVICES_IOT_RESERVED_INDEX (0) - -/* The Temporary key for FS Usage */ -#define SL_NETUTIL_CRYPTO_FS_TEMP_KEYS_OBJ_ID (1) - - -/**********************************************/ -/* Public Key Info Structures and Definitions */ -/**********************************************/ - -/* Enumeration of Elliptic Curve "named" curves */ -#define SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_NONE (0) -#define SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_SECP256R1 (1) - -/* PLACE HOLDER for future definitions of custom-curve parameters */ -typedef struct -{ - _u8 Padding[4]; -} SlNetUtilCryptoEcCustomCurveParam_t; - - -/* Union holding the Elliptic Curve parameters. */ -typedef union -{ - _u8 NamedCurveParams; /* parameters for named-curve (the curve identifier) */ - SlNetUtilCryptoEcCustomCurveParam_t CustomCurveParams; /* parameters for custom curves */ -} SlNetUtilCryptoEcCurveParams_u; - - -/* ?curve-type? definitions */ -#define SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_NAMED (1) /* ECC Named Curve type */ -#define SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_CUSTOM (2) /* ECC Custom curve type */ - - -/* Enumeration of the supported public-key algorithms */ -#define SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_NONE (0) -#define SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_EC (1) - - -/* Structure for holding the Elliptic Curve Key parameters */ -typedef struct -{ - _u8 CurveType; /* defines curve type - custom or named */ - SlNetUtilCryptoEcCurveParams_u CurveParams; /* specific parameters of the curve (depends on curve_type) */ -} SlNetUtilCryptoEcKeyParams_t; - -/* Union for holding the Public Key parameters, depends on key algorithm */ -typedef union -{ - - SlNetUtilCryptoEcKeyParams_t EcParams; /* parameters for Elliptic Curve key */ - - /* add containers for other key types and algos here*/ -} SlNetUtilCryptoPubKeyParams_u; - -/* structure for holding all the meta-data about a key-pair */ -typedef struct -{ - _u8 KeyAlgo; - SlNetUtilCryptoPubKeyParams_u KeyParams; - _u8 KeyFileNameLen; - _u8 CertFileNameLen; -}SlNetUtilCryptoPubKeyInfo_t; - -/********************************************/ -/* NetUtil-Crypto Cmd "Attributes" structures */ -/********************************************/ -/* structure for holding all the attributes for a "Sign" Command */ -typedef struct -{ - _u32 ObjId; - _u32 SigType; - _u32 Flags; -} SlNetUtilCryptoCmdSignAttrib_t; - - -/* structure for holding all the attributes for a "Verify" Command */ -typedef struct -{ - _u32 ObjId; - _u32 SigType; - _u32 Flags; - _u16 MsgLen; - _u16 SigLen; -} SlNetUtilCryptoCmdVerifyAttrib_t; - -/* structure for holding all the attributes for a "Create Certificate" Command */ -typedef struct -{ - _u32 ObjId; - _u32 Flags; - _u16 SubCmd; -} SlNetUtilCryptoCmdCreateCertAttrib_t; - -/* structure for holding all the attributes for "Key management" Commands: */ -/* Temp-Key (create and delete), Install and un-Install. */ -typedef struct -{ - _u32 ObjId; - _u32 Flags; - _u16 SubCmd; -} SlNetUtilCryptoCmdKeyMgnt_t; - -/* structure for holding all the attributes for a "SL_NETUTIL_CMD_ARP_LOOKUP" Command */ -typedef struct -{ - _u16 NumOfRetries; /* number of retires for ARP request, range 1-20 */ - _u16 Timeout; /* timeout between ARP requests, range 10-500 mSec , 10 mSec resolution*/ -}NetUtilCmdArpLookupAttrib_t; - - -/******************************************************************************/ -/* Type declarations */ -/******************************************************************************/ - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - \brief Function for setting configurations of utilities - - \param[in] Option Identifier of the specific "set" operation to perform - \param[in] ObjID ID of the relevant object that this set operation will be performed on - \param[in] ValueLen Length of the value parameter - \param[in] pValues Pointer to the buffer holding the configurations values - - \return Zero on success, or negative error code on failure - \sa sl_NetUtilGet sl_NetUtilCmd - \note - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_NetUtilSet) -_i32 sl_NetUtilSet(const _u16 Option, const _u32 ObjID, const _u8 *pValues, const _u16 ValueLen); -#endif - -/*! - \brief Function for getting configurations of utilities - \param[in] Option Identifier of the specific "get" operation to perform - - SL_NETUTIL_CRYPTO_PUBLIC_KEY \n - Used to retrieve the public key from an installed key-pair. \n - Saved in a certain index. - - SL_NETUTIL_TRUE_RANDOM \n - Generates a random number using the internal TRNG of the NWP. \n - \param[in] ObjID ID of the relevant object that this set operation will be performed on - \param[in,out] pValueLen Pointer to the length of the value parameter\n - On input - provides the length of the buffer that the application allocates, and - will hold the output\n - On output - provides the actual length of the received data - \param[out] pValues Pointer to the buffer that the application allocates, and will hold - the received data. - \return Zero on success, or negative error code on failure. - \sa sl_NetUtilSet sl_NetUtilCmd - \note - \warning - \par Examples - - SL_NETUTIL_CRYPTO_PUBLIC_KEY: - \code - int16_t Status; - uint8_t configOpt = 0; - uint32_t objId = 0; - uint16_t configLen = 0; - uint8_t key_buf[256]; - - configOpt = SL_NETUTIL_CRYPTO_PUBLIC_KEY; - - objId = 1; - configLen = 255; - //get the Public key - Status = sl_NetUtilGet(configOpt, objId, key_buf, &configLen); - \endcode - - - SL_NETUTIL_TRUE_RANDOM: - \code - uint32_t randNum; - int32_t len = sizeof(uint32_t); - - sl_NetUtilGet(SL_NETUTIL_TRUE_RANDOM, 0, (uint8_t *)&randNum, &len); - \endcode -
-*/ -#if _SL_INCLUDE_FUNC(sl_NetUtilGet) -_i16 sl_NetUtilGet(const _u16 Option, const _u32 ObjID, _u8 *pValues, _u16 *pValueLen); -#endif - -/*! - \brief Function for performing utilities-related commands - \param[in] Cmd Identifier of the specific Command to perform - - SL_NETUTIL_CRYPTO_CMD_INSTALL_OP \n - Install / Uninstall key pairs in one or more of the crypto utils - key-pair management mechanism. \n - Key Must be an ECC key-pair using SECP256R1 curve and already programmed to file system, - in DER format.\n - Key installation is persistent. - - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS \n - Creates or removes a temporary key pair. \n - Key pair is created internally by the NWP. - Key pair is not persistent over power cycle. - - SL_NETUTIL_CRYPTO_CMD_SIGN_MSG \n - Signs with a digital signature a data buffer using ECDSA algorithm. \n - - SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG \n - Verify a digital signature given with a data buffer using ECDSA algorithm. \n - \param[in] pAttrib Pointer to the buffer holding the Attribute values - \param[in] AttribLen Length of the Attribute-values - \param[in] pInputValues Pointer to the buffer holding the input-value - \param[in] InputLen Length of the input-value - \param[out] pOutputValues Pointer to the buffer that the application allocates, and will hold the received data. - \param[in,out] pOutputLen Length of the output-value \n - On input - provides the length of the buffer that the application allocates, and - will hold the output\n - On output - provides the actual length of the received output-values - \return Zero on success, or negative error code on failure - \sa sl_NetUtilGet sl_NetUtilSet - \note The host driver API sl_NetUtilCmd is not valid for use with the CC3220R device. - \warning - \par Examples - - - SL_NETUTIL_CRYPTO_CMD_INSTALL_OP (install / uninstall crypto keys): - \code - // Install a key - SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; - SlNetUtilCryptoPubKeyInfo_t *pInfoKey; - uint8_t name[FILE_NAME_SIZE]; - int32_t Status; - int16_t resultLen; - - keyAttrib.ObjId = 5; // Key would be stored at index 5 - keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_INSTALL_SUB_CMD; - pInfoKey->KeyAlgo = SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_EC; - pInfoKey->KeyParams.EcParams.CurveType = SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_NAMED; //ECC curve - pInfoKey->KeyParams.EcParams.CurveParams.NamedCurveParams = SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_SECP256R1; // SECP256R1 curve only. - - pInfoKey->CertFileNameLen = 0; - name = ((uint8_t *)pInfoKey) + sizeof(SlNetUtilCryptoPubKeyInfo_t); - name += pInfoKey->CertFileNameLen; - strcpy((char *)name, "extkey.der"); // Private key name in file system. - pInfoKey->KeyFileNameLen = strlen("extkey.der")+1; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_INSTALL_OP, - (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), - (uint8_t *)pInfo, - sizeof(SlNetUtilCryptoPubKeyInfo_t) + pInfoKey->KeyFileNameLen, - NULL, &resultLen); - - // Uninstall the Key: - resultLen = 0; - keyAttrib.ObjId = 5; - keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_UNINSTALL_SUB_CMD; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_INSTALL_OP, (uint8_t *)&keyAttrib, - sizeof(SlNetUtilCryptoCmdKeyMgnt_t), NULL, 0 , NULL, &resultLen); - \endcode - - - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, (Create a temporary key ): - \code - - SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; - int32_t Status; - uint16_t resultLen; - keyAttrib.ObjId = 1; // key index is 1 - keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, - (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), - NULL, 0 , NULL, &resultLen); - \endcode - - - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, (Create a temporary key ): - \code - - SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; - int32_t Status; - uint16_t resultLen; - keyAttrib.ObjId = 1; // key index is 1 - keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, - (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), - NULL, 0 , NULL, &resultLen); - \endcode - - - SL_NETUTIL_CRYPTO_CMD_SIGN_MSG, (Sign a data buffer): - \code - int32_t Status; - int32_t configLen; - uint8_t messageBuff[1500]; - uint8_t sig_buf[256]; // This buffer shall contain the digital signature. - SlNetUtilCryptoCmdSignAttrib_t signAttrib; - - signAttrib.Flags = 0; - signAttrib.ObjId = 3; - signAttrib.SigType = SL_NETUTIL_CRYPTO_SIG_SHAwECDSA; // this is the only type supported - configLen = 255; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_SIGN_MSG, (uint8_t *)&signAttrib, - sizeof(SlNetUtilCryptoCmdSignAttrib_t), - messageBuff, sizeof(messageBuf), sig_buf, &configLen); - \endcode - - - SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG, (Verify a data buffer): - \code - - int32_t Status; - int32_t configLen; - uint8_t verifyBuf[2048]; - uint8_t messageBuff[1500]; - uint8_t sig_buf[256]; // This buffer contains the digital signature. - int32_t verifyResult; - SlNetUtilCryptoCmdVerifyAttrib_t verAttrib; - - memcpy(verifyBuf, messageBuf, sizeof(messageBuf)); // copy the message to verify buffer. - memcpy(verifyBuf + sizeof(messageBuff), sig_buf, configLen); // Append the signature to message buffer. - - verAttrib.Flags = 0; - verAttrib.ObjId = 3; - verAttrib.SigType = SL_NETUTIL_CRYPTO_SIG_SHAwECDSA; // this is the only type supported, if other hash algorithm - // is wanted, SL_NETUTIL_CRYPTO_SIG_DIGESTwECDSA is used and - // the verifyBuf should be the digest and MsgLen should be - // the digest size - verAttrib.MsgLen = sizeof(messageBuff); - verAttrib.SigLen = configLen; - configLen = 255; - resultLen = 4; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG, (uint8_t *)&verAttrib, - sizeof(SlNetUtilCryptoCmdVerifyAttrib_t), - verifyBuf, sizeof(messageBuf) + configLen, - (uint8_t *)&verifyResult , &resultLen); - \endcode -
- - \endcode - - - - -*/ -#if _SL_INCLUDE_FUNC(sl_NetUtilCmd) -_i16 sl_NetUtilCmd(const _u16 Cmd, const _u8 *pAttrib, const _u16 AttribLen, - const _u8 *pInputValues, const _u16 InputLen, - _u8 *pOutputValues,_u16 *pOutputLen ); -#endif - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NETUTIL_H__ */ - - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.cpp deleted file mode 100755 index 1c3b3e4f6c9..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.cpp +++ /dev/null @@ -1,496 +0,0 @@ -/* - * cc_pal.c - CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ -/****************************************************************************** -* cc_pal.cpp -* -* SimpleLink Wi-Fi abstraction file for CC32xx -******************************************************************************/ - -/* Board includes */ -#include "mbed.h" -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ti/devices/cc32xx/driverlib/rom.h" -#include "ti/devices/cc32xx/driverlib/rom_map.h" -#include -#include -#include -#include - -/* NWP_SPARE_REG_5 - (OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5) - - Bits 31:02 - Reserved - - Bits 01 - SLSTOP1 - NWP in Reset, Power Domain Down - - Bits 00 - Reserved -*/ -#define NWP_SPARE_REG_5 (OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5) -#define NWP_SPARE_REG_5_SLSTOP (0x00000002) - -/* ANA_DCDC_PARAMS0 - (HIB1P2_BASE + HIB1P2_O_ANA_DCDC_PARAMETERS0) - - Bits 31:28 - Reserved - - Bits 27 - Override PWM mode (==> PFM) - - Bits 26:00 - Reserved -*/ -#define ANA_DCDC_PARAMS0 (HIB1P2_BASE + HIB1P2_O_ANA_DCDC_PARAMETERS0) -#define ANA_DCDC_PARAMS0_PWMOVERRIDE (0x08000000) - -/* WAKENWP - (ARCM_BASE + APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST) - - Bits 31:01 - Reserved - - Bits 00 - Wake Request to NWP -*/ -#define WAKENWP (ARCM_BASE + APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST) -#define WAKENWP_WAKEREQ (APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST) - -/* NWP_PWR_STATE - (GPRCM_BASE + GPRCM_O_NWP_PWR_STATE) - - Bits 31:12 - Reserved - - Bits 11:08 - Active (0x3) - - Bits 07:00 - Reserved -*/ -#define NWP_PWR_STATE (GPRCM_BASE + GPRCM_O_NWP_PWR_STATE) -#define NWP_PWR_STATE_PWRMASK (0x00000F00) -#define NWP_PWR_STATE_PWRACTIVE (0x00000300) - -/* NWP_LPDS_WAKEUPCFG - (GPRCM_BASE + GPRCM_O_NWP_LPDS_WAKEUP_CFG) - - Bits 31:08 - Reserved - - Bits 07:00 - WakeUp Config AppsToNwp Wake (0x20) - reset condition -*/ -#define NWP_LPDS_WAKEUPCFG (GPRCM_BASE + GPRCM_O_NWP_LPDS_WAKEUP_CFG) -#define NWP_LPDS_WAKEUPCFG_APPS2NWP (0x00000020) -#define NWP_LPDS_WAKEUPCFG_TIMEOUT_MSEC (600) - -/* N2A_INT_MASK_SET - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_SET) */ -#define N2A_INT_MASK_SET (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_SET) -/* N2A_INT_MASK_CLR - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_CLR) */ -#define N2A_INT_MASK_CLR (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_CLR) -/* N2A_INT_ACK - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_ACK) */ -#define N2A_INT_ACK (COMMON_REG_BASE + COMMON_REG_O_NW_INT_ACK) -#define NWP_N2A_INT_ACK_TIMEOUT_MSEC (3000) - -/* A2N_INT_STS_CLR - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_CLR) */ -#define A2N_INT_STS_CLR (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_CLR) -/* A2N_INT_TRIG - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_TRIG) */ -#define A2N_INT_TRIG (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_TRIG) -/* A2N_INT_STS_RAW - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_RAW) */ -#define A2N_INT_STS_RAW (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_RAW) - -#define uSEC_DELAY(x) (ROM_UtilsDelayDirect(x*80/3)) -#define MAX_DMA_RECV_TRANSACTION_SIZE (4096) -#define SPI_RATE_20M (20000000) -#define SPI_RATE_30M (30000000) - -HwiP_Handle g_intHandle = 0; - -//**************************************************************************** -// LOCAL FUNCTIONS -//**************************************************************************** - -Fd_t spi_Open(char *ifName, unsigned long flags) -{ - void *lspi_hndl; - unsigned int lspi_index; - SPI_Params SPI_Config; - SPI_Params_init(&SPI_Config); - - /* configure the SPI settings */ - SPI_Config.transferMode = SPI_MODE_BLOCKING; - SPI_Config.mode = SPI_MASTER; - /* Check NWP generation */ - if((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_DIEID_READ_REG4) >> 24) & 0x02) - { - SPI_Config.bitRate = SPI_RATE_30M; - } - else - { - SPI_Config.bitRate = SPI_RATE_20M; - } - SPI_Config.dataSize = 32; - SPI_Config.frameFormat = SPI_POL0_PHA0; - - /* index of the link SPI initialization configuration in the SPI_Config table */ - lspi_index = 0; - lspi_hndl = SPI_open(lspi_index, &SPI_Config); - if(NULL == lspi_hndl) - { - return -1; - } - else - { - return (Fd_t)lspi_hndl; - } -} - - -int spi_Close(Fd_t fd) -{ - SPI_close((SPI_Handle)fd); - return 0; -} - - -int spi_Read(Fd_t fd, unsigned char *pBuff, int len) -{ - SPI_Transaction transact_details; - int read_size = 0; - - /* check if the link SPI has been initialized successfully */ - if(fd < 0) - { - return -1; - } - - transact_details.txBuf = NULL; - transact_details.arg = NULL; - while(len > 0) - { - /* DMA can transfer upto a maximum of 1024 words in one go. So, if - the data to be read is more than 1024 words, it will be done in - parts */ - /* length is received in bytes, should be specified in words for the - * SPI driver. - */ - if(len > MAX_DMA_RECV_TRANSACTION_SIZE) - { - transact_details.count = (MAX_DMA_RECV_TRANSACTION_SIZE +3)>>2; - transact_details.rxBuf = (void*)(pBuff + read_size); - if(SPI_transfer((SPI_Handle)fd, &transact_details)) - { - read_size += MAX_DMA_RECV_TRANSACTION_SIZE; - len = len - MAX_DMA_RECV_TRANSACTION_SIZE; - } - else - { - return -1; - } - - } - else - { - transact_details.count = (len+3)>>2; - transact_details.rxBuf = (void*)(pBuff + read_size); - if(SPI_transfer((SPI_Handle)fd, &transact_details)) - { - read_size += len; - len = 0; - return read_size; - } - else - { - return -1; - } - } - } - - return(read_size); -} - - -int spi_Write(Fd_t fd, unsigned char *pBuff, int len) -{ - SPI_Transaction transact_details; - int write_size = 0; - - /* check if the link SPI has been initialized successfully */ - if(fd < 0) - { - return -1; - } - - transact_details.rxBuf = NULL; - transact_details.arg = NULL; - while(len > 0) - { - /* configure the transaction details. - * length is received in bytes, should be specified in words for the SPI - * driver. - */ - if(len > MAX_DMA_RECV_TRANSACTION_SIZE) - { - transact_details.count = (MAX_DMA_RECV_TRANSACTION_SIZE +3)>>2; - transact_details.txBuf = (void*)(pBuff + write_size); - if(SPI_transfer((SPI_Handle)fd, &transact_details)) - { - write_size += MAX_DMA_RECV_TRANSACTION_SIZE; - len = len - MAX_DMA_RECV_TRANSACTION_SIZE; - } - else - { - return -1; - } - } - else - { - transact_details.count = (len+3)>>2; - transact_details.txBuf = (void*)(pBuff + write_size); - if(SPI_transfer((SPI_Handle)fd, &transact_details)) - { - write_size += len; - len = 0; - return write_size; - } - else - { - return -1; - } - } - } - - return(write_size); -} - - -int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) -{ - NVIC_ClearPendingIRQ(INT_NWPIC_IRQn); - NVIC_SetVector(INT_NWPIC_IRQn, (uint32_t)InterruptHdl); - NVIC_EnableIRQ(INT_NWPIC_IRQn); - return OS_OK; -} - - -void NwpMaskInterrupt() -{ - (*(unsigned long *)N2A_INT_MASK_SET) = 0x1; -} - - -void NwpUnMaskInterrupt() -{ - (*(unsigned long *)N2A_INT_MASK_CLR) = 0x1; -} - - -void NwpPowerOn(void) -{ - /* bring the 1.32 eco out of reset */ - HWREG(NWP_SPARE_REG_5) &= ~NWP_SPARE_REG_5_SLSTOP; - - /* Clear host IRQ indication */ - HWREG(N2A_INT_ACK) = 1; - - /* NWP Wake-up */ - HWREG(WAKENWP) = WAKENWP_WAKEREQ; - - //UnMask Host Interrupt - NwpUnMaskInterrupt(); -} - - -void NwpPowerOff(void) -{ - - volatile unsigned long apps_int_sts_raw; - volatile unsigned long sl_stop_ind = HWREG(NWP_SPARE_REG_5); - volatile unsigned long nwp_lpds_wake_cfg = HWREG(NWP_LPDS_WAKEUPCFG); - _SlTimeoutParams_t SlTimeoutInfo = {0}; - - if((nwp_lpds_wake_cfg != NWP_LPDS_WAKEUPCFG_APPS2NWP) && /* Check for NWP POR condition - APPS2NWP is reset condition */ - !(sl_stop_ind & NWP_SPARE_REG_5_SLSTOP)) /* Check if sl_stop was executed */ - { - HWREG(0xE000E104) = 0x200; /* Enable the out of band interrupt, this is not a wake-up source*/ - HWREG(A2N_INT_TRIG) = 0x1; /* Trigger out of band interrupt */ - HWREG(WAKENWP) = WAKENWP_WAKEREQ; /* Wake-up the NWP */ - - _SlDrvStartMeasureTimeout(&SlTimeoutInfo, NWP_N2A_INT_ACK_TIMEOUT_MSEC); - - /* Wait for the A2N_INT_TRIG to be cleared by the NWP to indicate it's awake and ready for shutdown. - * poll until APPs->NWP interrupt is cleared or timeout : - * for service pack 3.1.99.1 or higher, this condition is fulfilled in less than 1 mSec. - * Otherwise, in some cases it may require up to 3000 mSec of waiting. */ - - apps_int_sts_raw = HWREG(A2N_INT_STS_RAW); - while(!(apps_int_sts_raw & 0x1)) - { - if(_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) - { - break; - } - apps_int_sts_raw = HWREG(A2N_INT_STS_RAW); - } - - WAIT_NWP_SHUTDOWN_READY; - } - - /* Clear Out of band interrupt, Acked by the NWP */ - HWREG(A2N_INT_STS_CLR) = 0x1; - - /* Mask Host Interrupt */ - NwpMaskInterrupt(); - - /* Switch to PFM Mode */ - HWREG(ANA_DCDC_PARAMS0) &= ~ANA_DCDC_PARAMS0_PWMOVERRIDE; - - /* sl_stop ECO for PG1.32 devices */ - HWREG(NWP_SPARE_REG_5) |= NWP_SPARE_REG_5_SLSTOP; - - /* Wait for 20 uSec, which is the minimal time between on-off cycle */ - uSEC_DELAY(20); -} - - -int Semaphore_create_handle(SemaphoreP_Handle* pSemHandle) -{ - SemaphoreP_Params params; - - SemaphoreP_Params_init(¶ms); - - params.mode = SemaphoreP_Mode_BINARY; - -#ifndef SL_PLATFORM_MULTI_THREADED - params.callback = tiDriverSpawnCallback; -#endif - (*(pSemHandle)) = SemaphoreP_create(1, ¶ms); - - if(!(*(pSemHandle))) - { - return Semaphore_FAILURE ; - } - - return Semaphore_OK; -} - -int SemaphoreP_delete_handle(SemaphoreP_Handle* pSemHandle) -{ - if (pSemHandle) - { - SemaphoreP_delete(*(pSemHandle)); - return Semaphore_OK; - } - else - { - return Semaphore_FAILURE; - } -} - -int SemaphoreP_post_handle(SemaphoreP_Handle* pSemHandle) -{ - if (pSemHandle) - { - SemaphoreP_post(*(pSemHandle)); - return Semaphore_OK; - } - else - { - return Semaphore_FAILURE; - } -} - - -int Mutex_create_handle(MutexP_Handle* pMutexHandle) -{ - MutexP_Params params; - - MutexP_Params_init(¶ms); - -#ifndef SL_PLATFORM_MULTI_THREADED - params.callback = tiDriverSpawnCallback; -#endif - - if (pMutexHandle) - { - (*(pMutexHandle)) = MutexP_create(¶ms); - - if(*(pMutexHandle)) - { - return Mutex_OK; - } - } - return Mutex_FAILURE; -} - -int MutexP_delete_handle(MutexP_Handle* pMutexHandle) -{ - MutexP_delete(*(pMutexHandle)); - return(Mutex_OK); -} - -int Mutex_unlock(MutexP_Handle pMutexHandle) -{ - MutexP_unlock(pMutexHandle, 0); - return(Mutex_OK); -} - - -int Mutex_lock(MutexP_Handle pMutexHandle) -{ - MutexP_lock(pMutexHandle); - return(Mutex_OK); -} - - -unsigned long TimerGetCurrentTimestamp() -{ - // TODO: add the header file containing osKernelGetTickCount - //return (ClockP_getSystemTicks()); - return osKernelGetTickCount(); -} - - -void NwpWaitForShutDownInd() -{ - volatile unsigned long nwp_wakup_ind = HWREG(NWP_LPDS_WAKEUPCFG); - _SlTimeoutParams_t SlTimeoutInfo = {0}; - - _SlDrvStartMeasureTimeout(&SlTimeoutInfo, NWP_LPDS_WAKEUPCFG_TIMEOUT_MSEC); - - while(nwp_wakup_ind != NWP_LPDS_WAKEUPCFG_APPS2NWP) - { - if(_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) - { - return; - } - nwp_wakup_ind = HWREG(NWP_LPDS_WAKEUPCFG); - } - - return ; -} - -void* pthread_self(void) -{ - return ThisThread::get_id(); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.h deleted file mode 100755 index cf757cdbb8f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.h +++ /dev/null @@ -1,419 +0,0 @@ -/* - * cc_pal.h - CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ -/****************************************************************************** -* cc_pal.h -* -* SimpleLink Wi-Fi abstraction file for CC32xx -******************************************************************************/ - -#ifndef __CC31xx_PAL_H__ -#define __CC31xx_PAL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - - -#define MAX_QUEUE_SIZE (4) -#define OS_WAIT_FOREVER (0xFFFFFFFF) -#define OS_NO_WAIT (0) -#define OS_OK (0) - -#define Semaphore_OK (0) -#define Semaphore_FAILURE (-1) - -#define Mutex_OK (0) -#define Mutex_FAILURE (-1) - - -/*! - \brief type definition for the SPI channel file descriptor - - \note On each porting or platform the type could be whatever is needed - integer, pointer to structure etc. -*/ -typedef int Fd_t; - - -/*! - \brief type definition for the host interrupt handler - - \param pValue - pointer to any memory strcuture. The value of this pointer is given on - registration of a new interrupt handler - - \note -*/ - -typedef void (*SL_P_EVENT_HANDLER)(void); - -#define P_EVENT_HANDLER SL_P_EVENT_HANDLER - -/*! - \brief type definition for the host spawn function - - \param pValue - pointer to any memory strcuture. The value of this pointer is given on - invoking the spawn function. - - \note -*/ - -typedef signed short (*P_OS_SPAWN_ENTRY)(void* pValue); - -typedef struct -{ - P_OS_SPAWN_ENTRY pEntry; - void* pValue; -}tSimpleLinkSpawnMsg; - -/*! - \brief open spi communication port to be used for communicating with a SimpleLink device - - Given an interface name and option flags, this function opens the spi communication port - and creates a file descriptor. This file descriptor can be used afterwards to read and - write data from and to this specific spi channel. - The SPI speed, clock polarity, clock phase, chip select and all other attributes are all - set to hardcoded values in this function. - - \param ifName - points to the interface name/path. The interface name is an - optional attributes that the SimpleLink driver receives - on opening the device. in systems that the spi channel is - not implemented as part of the os device drivers, this - parameter could be NULL. - \param flags - option flags - - \return upon successful completion, the function shall open the spi channel and return - a non-negative integer representing the file descriptor. - Otherwise, -1 shall be returned - - \sa spi_Close , spi_Read , spi_Write - \note - \warning -*/ -Fd_t spi_Open(char *ifName, unsigned long flags); - -/*! - \brief closes an opened SPI communication port - - \param fd - file descriptor of an opened SPI channel - - \return upon successful completion, the function shall return 0. - Otherwise, -1 shall be returned - - \sa spi_Open - \note - \warning -*/ -int spi_Close(Fd_t fd); - -/*! - \brief attempts to read up to len bytes from SPI channel into a buffer starting at pBuff. - - \param fd - file descriptor of an opened SPI channel - - \param pBuff - points to first location to start writing the data - - \param len - number of bytes to read from the SPI channel - - \return upon successful completion, the function shall return 0. - Otherwise, -1 shall be returned - - \sa spi_Open , spi_Write - \note - \warning -*/ -int spi_Read(Fd_t fd, unsigned char *pBuff, int len); - -/*! - \brief attempts to write up to len bytes to the SPI channel - - \param fd - file descriptor of an opened SPI channel - - \param pBuff - points to first location to start getting the data from - - \param len - number of bytes to write to the SPI channel - - \return upon successful completion, the function shall return 0. - Otherwise, -1 shall be returned - - \sa spi_Open , spi_Read - \note This function could be implemented as zero copy and return only upon successful completion - of writing the whole buffer, but in cases that memory allocation is not too tight, the - function could copy the data to internal buffer, return back and complete the write in - parallel to other activities as long as the other SPI activities would be blocked untill - the entire buffer write would be completed - \warning -*/ -int spi_Write(Fd_t fd, unsigned char *pBuff, int len); - -/*! - \brief register an interrupt handler for the host IRQ - - \param InterruptHdl - pointer to interrupt handler function - - \param pValue - pointer to a memory strcuture that is passed to the interrupt handler. - - \return upon successful registration, the function shall return 0. - Otherwise, -1 shall be returned - - \sa - \note If there is already registered interrupt handler, the function should overwrite the old handler - with the new one - \warning -*/ -int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue); - - -/*! - \brief Masks host IRQ - - - \sa NwpUnMaskInterrupt - - \warning -*/ -void NwpMaskInterrupt(); - - -/*! - \brief Unmasks host IRQ - - - \sa NwpMaskInterrupt - - \warning -*/ -void NwpUnMaskInterrupt(); - - -/*! - \brief Preamble to the enabling the Network Processor. - Placeholder to implement any pre-process operations - before enabling networking operations. - - \sa sl_DeviceEnable - - \note belongs to \ref ported_sec - -*/ - -void NwpPowerOnPreamble(void); - - - -/*! - \brief Disable the Network Processor - - \sa sl_DeviceEnable - - \note belongs to \ref ported_sec -*/ -void NwpPowerOff(void); - - -/*! - \brief Enable the Network Processor - - \sa sl_DeviceDisable - - \note belongs to \ref ported_sec - -*/ -void NwpPowerOn(void); - - -/*! - \brief Creates a semaphore handle, using the driver porting layer of the core SDK. - - \param pSemHandle - pointer to a memory structure that would contain the handle. - - \return upon successful creation, the function shall return 0. - Otherwise, -1 shall be returned - - \note belongs to \ref ported_sec -*/ -int Semaphore_create_handle(SemaphoreP_Handle* pSemHandle); - - -/*! - \brief Deletes a semaphore handle, using the driver porting layer of the core SDK. - - \param pSemHandle - pointer to a memory structure that would contain the handle. - - \return The function shall return 0. - - \note belongs to \ref ported_sec -*/ -int SemaphoreP_delete_handle(SemaphoreP_Handle* pSemHandle); - - -/*! - \brief Post (signal) a semaphore handle, using the driver porting layer of the core SDK. - - \param pSemHandle - pointer to a memory structure that would contain the handle. - - \return The function shall return 0. - - \note belongs to \ref ported_sec -*/ -int SemaphoreP_post_handle(SemaphoreP_Handle* pSemHandle); - - -/*! - \brief Creates a mutex object handle, using the driver porting layer of the core SDK. - - \param pMutexHandle - pointer to a memory structure that would contain the handle. - - \return upon successful creation, the function shall return 0. - Otherwise, -1 shall be returned - - \note belongs to \ref ported_sec -*/ -int Mutex_create_handle(MutexP_Handle* pMutexHandle); - - -/*! - \brief Deletes a mutex object handle, using the driver porting layer of the core SDK. - - \param pMutexHandle - pointer to a memory structure that would contain the handle. - - \return the function shall return 0. - - \note belongs to \ref ported_sec -*/ -int MutexP_delete_handle(MutexP_Handle* pMutexHandle); - -/*! - \brief Unlocks a mutex object. - - \param pMutexHandle - pointer to a memory structure that contains the object. - - \return upon successful unlocking, the function shall return 0. - - \note belongs to \ref ported_sec -*/ -int Mutex_unlock(MutexP_Handle pMutexHandle); - - -/*! - \brief Locks a mutex object. - - \param pMutexHandle - pointer to a memory structure that contains the object. - - \return upon successful locking, the function shall return 0. - - \note belongs to \ref ported_sec - - \warning The lock will block until the mutex is available. -*/ -/*! - \brief Creates a mutex object handle, using the driver porting layer of the core SDK. - - \param pMutexHandle - pointer to a memory structure that would contain the handle. - - \return upon successful creation, the function shall return 0. - Otherwise, -1 shall be returned - - \note belongs to \ref ported_sec -*/ - - -/*! - \brief Deletes a mutex object handle, using the driver porting layer of the core SDK. - - \param pMutexHandle - pointer to a memory structure that would contain the handle. - - \return the function shall return 0. - - \note belongs to \ref ported_sec -*/ - -/*! - \brief Unlocks a mutex object. - - \param pMutexHandle - pointer to a memory structure that contains the object. - - \return upon successful unlocking, the function shall return 0. - - \note belongs to \ref ported_sec -*/ - - -/*! - \brief Locks a mutex object. - - \param pMutexHandle - pointer to a memory structure that contains the object. - - \return upon successful locking, the function shall return 0. - - \note belongs to \ref ported_sec - - \warning The lock will block until the mutex is available. -*/ -int Mutex_lock(MutexP_Handle pMutexHandle); - - -/*! - \brief Take a time stamp value. - - \return 32-bit value of the systick counter. - - \sa - - \warning -*/ -unsigned long TimerGetCurrentTimestamp(); - -/*! - \brief - - \return - - \sa - - \warning -*/ -void NwpWaitForShutDownInd(); - - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/user.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/user.h deleted file mode 100755 index 017b5a475d5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/user.h +++ /dev/null @@ -1,1332 +0,0 @@ -/* - * user.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -/****************************************************************************** -* user.h - CC31xx/CC32xx Host Driver Implementation -******************************************************************************/ - -#ifndef __USER_H__ -#define __USER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#include -#include - -typedef signed int _SlFd_t; - -#define SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS (_u32)(10) -#define SL_TIMESTAMP_MAX_VALUE (_u32)(0xFFFFFFFF) - -/*! - ****************************************************************************** - - \defgroup configuration_mem_mgm Configuration - Memory Management - - This section declare in which memory management model the SimpleLink driver - will run: - -# Static - -# Dynamic - - This section IS NOT REQUIRED in case Static model is selected. - - The default memory model is Static - - - @{ - - ***************************************************************************** -*/ - -/*! - \brief Defines whether the SimpleLink driver is working in dynamic - memory model or not - - When defined, the SimpleLink driver use dynamic allocations - if dynamic allocation is selected malloc and free functions - must be retrieved - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define SL_MEMORY_MGMT_DYNAMIC - -#ifdef SL_MEMORY_MGMT_DYNAMIC - - -#include -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_Malloc(Size) malloc(Size) - -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_Free(pMem) free(pMem) -#endif - - -/*! - - Close the Doxygen group. - @} - -*/ - -/*! - - \def MAX_CONCURRENT_ACTIONS - - \brief Defines the maximum number of concurrent action in the system - Min:1 , Max: 32 - - Actions which has async events as return, will be blocked until the event arrive - - \sa - - \note In case there are not enough resources for the actions needed in the system, - error is received: SL_POOL_IS_EMPTY - one option is to increase MAX_CONCURRENT_ACTIONS - (improves performance but results in memory consumption) - Other option is to call the API later (decrease performance) - - Async events which arrive during command context will be dynamically or static - allocated and handled in spawn context. If MAX_CONCURRENT_ACTIONS - is high, there will be more events which might arrive during this period. - Due to memory constrains MAX_CONCURRENT_ACTIONS is lower in static allocation mode. - - - \warning In case of setting to one, recommend to use non-blocking recv\recvfrom to allow - multiple socket recv -*/ -#ifndef SL_TINY_EXT -#ifdef SL_MEMORY_MGMT_DYNAMIC -#define MAX_CONCURRENT_ACTIONS 18 -#else -#define MAX_CONCURRENT_ACTIONS 5 -#endif -#else -#define MAX_CONCURRENT_ACTIONS 1 -#endif - /*! - \def SL_MAX_ASYNC_BUFFERS - - - - \brief Defines the maximum static buffers to store asycn events which - arrives during command context. The event is stored in a buffer (if free) - and handle in spwan cotext. value must be set to MAX_CONCURRENT_ACTIONS which - is the maximum simultaniuos async event which could arrive in command context. - value: MAX_CONCURRENT_ACTIONS - - \sa - - \note Events which arrive when there is no free buffer will be dropped. - If there is a command which is waiting on this event, it will be released - with error SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR. - In this case need to increase MAX_CONCURRENT_ACTIONS - (improves performance but results in memory consumption) - - - */ - -#define SL_MAX_ASYNC_BUFFERS MAX_CONCURRENT_ACTIONS -/*! - \def CPU_FREQ_IN_MHZ - \brief Defines CPU frequency for Host side, for better accuracy of busy loops, if any - \sa - \note - - \warning If not set the default CPU frequency is set to 200MHz - This option will be deprecated in future release -*/ - -/* #define CPU_FREQ_IN_MHZ 80 */ - - -/*! - ****************************************************************************** - - \defgroup configuration_capabilities Configuration - Capabilities Set - - This section IS NOT REQUIRED in case one of the following pre defined - capabilities set is in use: - - SL_TINY - - SL_SMALL - - SL_FULL - - PORTING ACTION: - - Define one of the pre-defined capabilities set or uncomment the - relevant definitions below to select the required capabilities - - @{ - - ******************************************************************************* -*/ -/*! - \def SL_RUNTIME_EVENT_REGISTERATION - - \brief Defines whether the SimpleLink driver uses dynamic event registration - or static precompiled event mechanism - \sa - - \note belongs to \ref configuration_sec - -*/ -#define SL_RUNTIME_EVENT_REGISTERATION - - -/*! - \def SL_INC_ARG_CHECK - - \brief Defines whether the SimpleLink driver perform argument check - or not - - When defined, the SimpleLink driver perform argument check on - function call. Removing this define could reduce some code - size and improve slightly the performances but may impact in - unpredictable behavior in case of invalid arguments - - \sa - - \note belongs to \ref configuration_sec - - \warning Removing argument check may cause unpredictable behavior in - case of invalid arguments. - In this case the user is responsible to argument validity - (for example all handlers must not be NULL) -*/ -#define SL_INC_ARG_CHECK - - -/*! - \brief Defines whether to include extended API in SimpleLink driver - or not - - When defined, the SimpleLink driver will include also all - exteded API of the included packages - - \sa ext_api - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_EXT_API - - -/*! - \brief Defines whether to include WLAN package in SimpleLink driver - or not - - When defined, the SimpleLink driver will include also - the WLAN package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_WLAN_PKG - - -/*! - \brief Defines whether to include SOCKET package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also - the SOCKET package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_SOCKET_PKG - - -/*! - \brief Defines whether to include NET_APP package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also the - NET_APP package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_NET_APP_PKG - - -/*! - \brief Defines whether to include NET_CFG package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also - the NET_CFG package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_NET_CFG_PKG - - -/*! - \brief Defines whether to include NVMEM package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also the - NVMEM package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_NVMEM_PKG - - -/*! - \brief Defines whether to include NVMEM extended package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also the - NVMEM extended package - - \sa - - \note belongs to \ref nvmem_ext - - \warning -*/ -#define SL_INC_NVMEM_EXT_PKG - - -/*! - \brief Defines whether to include socket server side APIs - in SimpleLink driver or not - - When defined, the SimpleLink driver will include also socket - server side APIs - - \sa server_side - - \note - - \warning -*/ -#define SL_INC_SOCK_SERVER_SIDE_API - - -/*! - \brief Defines whether to include socket client side APIs in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also socket - client side APIs - - \sa client_side - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_SOCK_CLIENT_SIDE_API - - -/*! - \brief Defines whether to include socket receive APIs in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also socket - receive side APIs - - \sa recv_api - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_SOCK_RECV_API - - -/*! - \brief Defines whether to include socket send APIs in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also socket - send side APIs - - \sa send_api - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_SOCK_SEND_API - - -/*! - - Close the Doxygen group. - @} - - */ - - -/*! - ****************************************************************************** - - \defgroup configuration_enable_device Configuration - Device Enable/Disable - - The enable/disable API provide mechanism to enable/disable the network processor - - - porting ACTION: - - None - @{ - - ****************************************************************************** - */ - -/*! - \brief Preamble to the enabling the Network Processor. - Placeholder to implement any pre-process operations - before enabling networking operations. - - \sa sl_DeviceEnable - - \note belongs to \ref configuration_sec - -*/ -#define sl_DeviceEnablePreamble() - - - -/*! - \brief Enable the Network Processor - - \sa sl_DeviceDisable - - \note belongs to \ref configuration_sec - -*/ -#define sl_DeviceEnable() NwpPowerOn() - - -/*! - \brief Disable the Network Processor - - \sa sl_DeviceEnable - - \note belongs to \ref configuration_sec -*/ -#define sl_DeviceDisable() NwpPowerOff() - - -/*! - - Close the Doxygen group. - @} - - */ - -/*! - ****************************************************************************** - - \defgroup configuration_interface Configuration - Communication Interface - - The SimpleLink device supports several standard communication protocol among SPI and - UART. CC32XX Host Driver implements SPI Communication Interface - - - \note In CC32XX, SPI implementation uses DMA in order to increase the utilization - of the communication channel. If user prefers to user UART, these interfaces - need to be redefined - - - porting ACTION: - - None - - @{ - - ****************************************************************************** -*/ - -#define _SlFd_t Fd_t - - -/*! - \brief Opens an interface communication port to be used for communicating - with a SimpleLink device - - Given an interface name and option flags, this function opens - the communication port and creates a file descriptor. - This file descriptor is used afterwards to read and write - data from and to this specific communication channel. - The speed, clock polarity, clock phase, chip select and all other - specific attributes of the channel are all should be set to hardcoded - in this function. - - \param ifName - points to the interface name/path. The interface name is an - optional attributes that the SimpleLink driver receives - on opening the driver (sl_Start). - In systems that the spi channel is not implemented as - part of the os device drivers, this parameter could be NULL. - - \param flags - optional flags parameters for future use - - \return upon successful completion, the function shall open the channel - and return a non-negative integer representing the file descriptor. - Otherwise, -1 shall be returned - - \sa sl_IfClose , sl_IfRead , sl_IfWrite - - \note The prototype of the function is as follow: - Fd_t xxx_IfOpen(char* pIfName , unsigned long flags); - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfOpen spi_Open - - -/*! - \brief Closes an opened interface communication port - - \param fd - file descriptor of opened communication channel - - \return upon successful completion, the function shall return 0. - Otherwise, -1 shall be returned - - \sa sl_IfOpen , sl_IfRead , sl_IfWrite - - \note The prototype of the function is as follow: - int xxx_IfClose(Fd_t Fd); - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfClose spi_Close - - -/*! - \brief Attempts to read up to len bytes from an opened communication channel - into a buffer starting at pBuff. - - \param fd - file descriptor of an opened communication channel - - \param pBuff - pointer to the first location of a buffer that contains enough - space for all expected data - - \param len - number of bytes to read from the communication channel - - \return upon successful completion, the function shall return the number of read bytes. - Otherwise, 0 shall be returned - - \sa sl_IfClose , sl_IfOpen , sl_IfWrite - - - \note The prototype of the function is as follow: - int xxx_IfRead(Fd_t Fd , char* pBuff , int Len); - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfRead spi_Read - - -/*! - \brief attempts to write up to len bytes to the SPI channel - - \param fd - file descriptor of an opened communication channel - - \param pBuff - pointer to the first location of a buffer that contains - the data to send over the communication channel - - \param len - number of bytes to write to the communication channel - - \return upon successful completion, the function shall return the number of sent bytes. - therwise, 0 shall be returned - - \sa sl_IfClose , sl_IfOpen , sl_IfRead - - \note This function could be implemented as zero copy and return only upon successful completion - of writing the whole buffer, but in cases that memory allocation is not too tight, the - function could copy the data to internal buffer, return back and complete the write in - parallel to other activities as long as the other SPI activities would be blocked until - the entire buffer write would be completed - - The prototype of the function is as follow: - int xxx_IfWrite(Fd_t Fd , char* pBuff , int Len); - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfWrite spi_Write - - -/*! - \brief register an interrupt handler routine for the host IRQ - - \param InterruptHdl - pointer to interrupt handler routine - - \param pValue - pointer to a memory structure that is passed - to the interrupt handler. - - \return upon successful registration, the function shall return 0. - Otherwise, -1 shall be returned - - \sa - - \note If there is already registered interrupt handler, the function - should overwrite the old handler with the new one - - \note If the handler is a null pointer, the function should un-register the - interrupt handler, and the interrupts can be disabled. - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfRegIntHdlr(InterruptHdl , pValue) NwpRegisterInterruptHandler(InterruptHdl , pValue) - - -/*! - \brief Masks the Host IRQ - - \sa sl_IfUnMaskIntHdlr - - - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfMaskIntHdlr() NwpMaskInterrupt() - - -/*! - \brief Unmasks the Host IRQ - - \sa sl_IfMaskIntHdlr - - - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfUnMaskIntHdlr() NwpUnMaskInterrupt() - - -/*! - \brief Write Handers for statistics debug on write - - \param interface handler - pointer to interrupt handler routine - - - \return no return value - - \sa - - \note An optional hooks for monitoring before and after write info - - \note belongs to \ref configuration_sec - - \warning -*/ -/* #define SL_START_WRITE_STAT */ - -#ifdef SL_START_WRITE_STAT -#define sl_IfStartWriteSequence -#define sl_IfEndWriteSequence -#endif - - -/*! - \brief Get the timer counter value (timestamp). - The timer must count from zero to its MAX value. - - \param None. - - - \return Returns 32-bit timer counter value (ticks unit) - - \sa - - \note - - \note belongs to \ref porting_sec - - \warning -*/ -#ifndef SL_TINY_EXT -#undef slcb_GetTimestamp -/* A timer must be started before using this function */ -#define slcb_GetTimestamp TimerGetCurrentTimestamp -#endif - - -/*! - \brief This macro wait for the NWP to raise a ready for shutdown indication. - - \param None. - - \note This function is unique for the CC32XX family - - \warning -*/ - -#define WAIT_NWP_SHUTDOWN_READY NwpWaitForShutDownInd() - - -/*! - Close the Doxygen group. - @} - -*/ - -/*! - ****************************************************************************** - - \defgroup configuration_os Configuration - Operating System - - The SimpleLink driver could run on two kind of platforms: - -# Non-Os / Single Threaded (default) - -# Multi-Threaded - - CC32XX SimpleLink Host Driver is ported on both Non-Os and Multi Threaded OS enviroment. - The Host driver is made OS independent by implementing an OS Abstraction layer. - Reference implementation for OS Abstraction is available for FreeRTOS and TI-RTOS. - - - If you choose to work in multi-threaded environment under different operating system you - will have to provide some basic adaptation routines to allow the driver to protect access to - resources for different threads (locking object) and to allow synchronization between threads - (sync objects). In additional the driver support running without dedicated thread allocated solely - to the SimpleLink driver. If you choose to work in this mode, you should also supply a spawn - method that will enable to run function on a temporary context. - - \note - This Macro is defined in the IDE to generate Driver for both OS and Non-OS - - porting ACTION: - - None - - @{ - - ****************************************************************************** -*/ - -#define SL_PLATFORM_MULTI_THREADED - -#ifdef SL_PLATFORM_MULTI_THREADED - -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define SL_OS_RET_CODE_OK ((int)OS_OK) - -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define SL_OS_WAIT_FOREVER ((uint32_t)OS_WAIT_FOREVER) - -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define SL_OS_NO_WAIT ((uint32_t)OS_NO_WAIT) - -/*! - \brief type definition for a time value - - \note On each configuration or platform the type could be whatever is needed - integer, pointer to structure etc. - - \note belongs to \ref configuration_sec -*/ -#define _SlTime_t uint32_t - - -#endif //SL_PLATFORM_MULTI_THREADED - -/*! - \brief type definition for a sync object container - - Sync object is object used to synchronize between two threads or thread and interrupt handler. - One thread is waiting on the object and the other thread send a signal, which then - release the waiting thread. - The signal must be able to be sent from interrupt context. - This object is generally implemented by binary semaphore or events. - - \note On each configuration or platform the type could be whatever is needed - integer, structure etc. - - \note belongs to \ref configuration_sec -*/ -#define _SlSyncObj_t SemaphoreP_Handle - - -/*! - \brief This function creates a sync object - - The sync object is used for synchronization between diffrent thread or ISR and - a thread. - - \param pSyncObj - pointer to the sync object control block - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjCreate(pSyncObj,pName) Semaphore_create_handle(pSyncObj) - - -/*! - \brief This function deletes a sync object - - \param pSyncObj - pointer to the sync object control block - - \return upon successful deletion the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjDelete(pSyncObj) SemaphoreP_delete_handle(pSyncObj) - - -/*! - \brief This function generates a sync signal for the object. - - All suspended threads waiting on this sync object are resumed - - \param pSyncObj - pointer to the sync object control block - - \return upon successful signaling the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note the function could be called from ISR context - \warning -*/ -#define sl_SyncObjSignal(pSyncObj) SemaphoreP_post_handle(pSyncObj) - - -/*! - \brief This function generates a sync signal for the object from Interrupt - - This is for RTOS that should signal from IRQ using a dedicated API - - \param pSyncObj - pointer to the sync object control block - - \return upon successful signaling the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note the function could be called from ISR context - \warning -*/ -#define sl_SyncObjSignalFromIRQ(pSyncObj) SemaphoreP_post_handle(pSyncObj) - - -/*! - \brief This function waits for a sync signal of the specific sync object - - \param pSyncObj - pointer to the sync object control block - \param Timeout - numeric value specifies the maximum number of mSec to - stay suspended while waiting for the sync signal - Currently, the SimpleLink driver uses only two values: - - OSI_WAIT_FOREVER - - OSI_NO_WAIT - - \return upon successful reception of the signal within the timeout window return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjWait(pSyncObj,Timeout) SemaphoreP_pend((*(pSyncObj)),Timeout) - -/*! - \brief type definition for a locking object container - - Locking object are used to protect a resource from mutual accesses of two or more threads. - The locking object should suppurt reentrant locks by a signal thread. - This object is generally implemented by mutex semaphore - - \note On each configuration or platform the type could be whatever is needed - integer, structure etc. - \note belongs to \ref configuration_sec -*/ -#define _SlLockObj_t MutexP_Handle - -/*! - \brief This function creates a locking object. - - The locking object is used for protecting a shared resources between different - threads. - - \param pLockObj - pointer to the locking object control block - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjCreate(pLockObj, pName) Mutex_create_handle(pLockObj) - - -/*! - \brief This function deletes a locking object. - - \param pLockObj - pointer to the locking object control block - - \return upon successful deletion the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjDelete(pLockObj) MutexP_delete_handle(pLockObj) - - -/*! - \brief This function locks a locking object. - - All other threads that call this function before this thread calls - the osi_LockObjUnlock would be suspended - - \param pLockObj - pointer to the locking object control block - \param Timeout - numeric value specifies the maximum number of mSec to - stay suspended while waiting for the locking object - Currently, the SimpleLink driver uses only two values: - - OSI_WAIT_FOREVER - - OSI_NO_WAIT - - - \return upon successful reception of the locking object the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjLock(pLockObj,Timeout) Mutex_lock(*(pLockObj)) - - -/*! - \brief This function unlock a locking object. - - \param pLockObj - pointer to the locking object control block - - \return upon successful unlocking the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjUnlock(pLockObj) Mutex_unlock(*(pLockObj)) - - -/*! - \brief This function call the pEntry callback from a different context - - \param pEntry - pointer to the entry callback function - - \param pValue - pointer to any type of memory structure that would be - passed to pEntry callback from the execution thread. - - \param flags - execution flags - reserved for future usage - - \return upon successful registration of the spawn the function should return 0 - (the function is not blocked till the end of the execution of the function - and could be returned before the execution is actually completed) - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - - \warning User must implement it's own 'os_Spawn' function. -*/ -//#define SL_PLATFORM_EXTERNAL_SPAWN - -#ifdef SL_PLATFORM_EXTERNAL_SPAWN -#define sl_Spawn(pEntry,pValue,flags) os_Spawn(pEntry,pValue,flags) -#endif - -/*! - * - Close the Doxygen group. - @} - - */ - -/*! - ****************************************************************************** - - \defgroup configuration_events Configuration - Event Handlers - - This section includes the asynchronous event handlers routines - - porting ACTION: - -define your routine as the value of this handler - - @{ - - ****************************************************************************** - */ - - - -/*! - \brief Fatal Error async event for inspecting fatal error events. - This event handles events/errors reported from the device/host driver - - \param[out] pSlFatalErrorEvent - - \par - Parameters: - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_DEVICE_ABORT , - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_DRIVER_ABORT , - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_NO_CMD_ACK , - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_SYNC_LOSS , - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT , - - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_DeviceFatalErrorEvtHdlr SimpleLinkFatalErrorEventHandler - -/*! - \brief General async event for inspecting general events. - This event handles events/errors reported from the device/host driver - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_DeviceGeneralEvtHdlr SimpleLinkGeneralEventHandler - -/*! - \brief WLAN Async event handler - - \param[out] pSlWlanEvent pointer to SlWlanEvent_t data - - \par - Parameters: - - - pSlWlanEvent->Event = SL_WLAN_CONNECT_EVENT , STA or P2P client connection indication event - - pSlWlanEvent->EventData.STAandP2PModeWlanConnected main fields: - - ssid_name - - ssid_len - - bssid - - go_peer_device_name - - go_peer_device_name_len - - - pSlWlanEvent->Event = SL_WLAN_DISCONNECT_EVENT , STA or P2P client disconnection event - - pSlWlanEvent->EventData.STAandP2PModeDisconnected main fields: - - ssid_name - - ssid_len - - reason_code - - - pSlWlanEvent->Event = SL_WLAN_STA_CONNECTED_EVENT , AP/P2P(Go) connected STA/P2P(Client) - - pSlWlanEvent->EventData.APModeStaConnected fields: - - go_peer_device_name - - mac - - go_peer_device_name_len - - wps_dev_password_id - - own_ssid: relevant for event sta-connected only - - own_ssid_len: relevant for event sta-connected only - - - pSlWlanEvent->Event = SL_WLAN_STA_DISCONNECTED_EVENT , AP/P2P(Go) disconnected STA/P2P(Client) - - pSlWlanEvent->EventData.APModestaDisconnected fields: - - go_peer_device_name - - mac - - go_peer_device_name_len - - wps_dev_password_id - - own_ssid: relevant for event sta-connected only - - own_ssid_len: relevant for event sta-connected only - - - pSlWlanEvent->Event = SL_WLAN_SMART_CONFIG_COMPLETE_EVENT - - pSlWlanEvent->EventData.smartConfigStartResponse fields: - - status - - ssid_len - - ssid - - private_token_len - - private_token - - - pSlWlanEvent->Event = SL_WLAN_SMART_CONFIG_STOP_EVENT - - pSlWlanEvent->EventData.smartConfigStopResponse fields: - - status - - - pSlWlanEvent->Event = SL_WLAN_P2P_DEV_FOUND_EVENT - - pSlWlanEvent->EventData.P2PModeDevFound fields: - - go_peer_device_name - - mac - - go_peer_device_name_len - - wps_dev_password_id - - own_ssid: relevant for event sta-connected only - - own_ssid_len: relevant for event sta-connected only - - - pSlWlanEvent->Event = SL_WLAN_P2P_NEG_REQ_RECEIVED_EVENT - - pSlWlanEvent->EventData.P2PModeNegReqReceived fields - - go_peer_device_name - - mac - - go_peer_device_name_len - - wps_dev_password_id - - own_ssid: relevant for event sta-connected only - - - pSlWlanEvent->Event = SL_WLAN_CONNECTION_FAILED_EVENT , P2P only - - pSlWlanEvent->EventData.P2PModewlanConnectionFailure fields: - - status - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_WlanEvtHdlr SimpleLinkWlanEventHandler - - -/*! - \brief NETAPP Async event handler - - \param[out] pSlNetApp pointer to SlNetAppEvent_t data - - \par - Parameters: - - pSlWlanEvent->Event = SL_NETAPP_IPV4_IPACQUIRED_EVENT, IPV4 acquired event - - pSlWlanEvent->EventData.ipAcquiredV4 fields: - - ip - - gateway - - dns - - - pSlWlanEvent->Event = SL_NETAPP_IP_LEASED_EVENT, AP or P2P go dhcp lease event - - pSlWlanEvent->EventData.ipLeased fields: - - ip_address - - lease_time - - mac - - - pSlWlanEvent->Event = SL_NETAPP_IP_RELEASED_EVENT, AP or P2P go dhcp ip release event - - pSlWlanEvent->EventData.ipReleased fields - - ip_address - - mac - - reason - - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_NetAppEvtHdlr SimpleLinkNetAppEventHandler - -/*! - \brief HTTP server async event - - \param[out] pSlHttpServerEvent pointer to SlHttpServerEvent_t - \param[in] pSlHttpServerResponse pointer to SlHttpServerResponse_t - - \par - Parameters: \n - - - pSlHttpServerEvent->Event = SL_NETAPP_HTTPGETTOKENVALUE_EVENT - - pSlHttpServerEvent->EventData fields: - - httpTokenName - - data - - len - - pSlHttpServerResponse->ResponseData fields: - - data - - len - - - pSlHttpServerEvent->Event = SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT - - pSlHttpServerEvent->EventData.httpPostData fields: - - action - - token_name - - token_value - - pSlHttpServerResponse->ResponseData fields: - - data - - len - - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_NetAppHttpServerHdlr SimpleLinkHttpServerEventHandler - - - -/*! - \brief A handler for handling Netapp requests. - Netapp request types: - For HTTP server: GET / POST (future: PUT / DELETE) - - \param - - \param - - \sa - - \note belongs to \ref porting_sec - - \warning -*/ - -#define slcb_NetAppRequestHdlr SimpleLinkNetAppRequestEventHandler - - - -/*! - \brief A handler for freeing the memory of the NetApp response. - - \param - - \param - - \sa - - \note belongs to \ref porting_sec - - \warning -*/ - -#define slcb_NetAppRequestMemFree SimpleLinkNetAppRequestMemFreeEventHandler - - - -/*! - \brief Socket Async event handler - - \param[out] pSlSockEvent pointer to SlSockEvent_t data - - \par - Parameters:\n - - pSlSockEvent->Event = SL_SOCKET_TX_FAILED_EVENT - - pSlSockEvent->EventData fields: - - sd - - status - - pSlSockEvent->Event = SL_SOCKET_ASYNC_EVENT - - pSlSockEvent->EventData fields: - - sd - - type: SSL_ACCEPT or RX_FRAGMENTATION_TOO_BIG or OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED - - val - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_SockEvtHdlr SimpleLinkSockEventHandler - - -/*! - \brief Trigger Async event handler. If define, sl_Select operates only in trigger mode. - To disable trigger mode, handler should not be defined. - - \param[out] pSlTriggerEvent pointer to SlSockTriggerEvent_t data - - \par - Parameters:\n - - pSlTriggerEvent->Event = SL_SOCKET_TRIGGER_EVENT_SELECT - - pSlTriggerEvent->EventData: Not in use - - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#ifndef SL_PLATFORM_MULTI_THREADED -#define slcb_SocketTriggerEventHandler SimpleLinkSocketTriggerEventHandler -#endif -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __USER_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/simplelink.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/simplelink.h deleted file mode 100755 index 9037e56e334..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/simplelink.h +++ /dev/null @@ -1,1253 +0,0 @@ -/* - * simplelink.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*! - \mainpage SimpleLink Driver - - \section intro_sec Introduction - - The SimpleLink(tm) CC31xx/CC32xx family allows to add Wi-Fi and networking capabilities - to low-cost embedded products without having prior Wi-Fi, RF or networking expertise.\n - The CC31xx/CC32xx is an ideal solution for microcontroller-based sensor and control - applications such as home appliances, home automation and smart metering.\n - The CC31xx/CC32xx has integrated a comprehensive TCP/IP network stack, Wi-Fi driver and - security supplicant leading to easier portability to microcontrollers, to an - ultra-low memory footprint, all without compromising the capabilities and robustness - of the final application. - - - - \section modules_sec Module Names - To make it simple, TI's SimpleLink CC31xx/CC32xx platform capabilities were divided into modules by topic (Silo).\n - These capabilities range from basic device management through wireless - network configuration, standard BSD socket and much more.\n - Listed below are the various modules in the SimpleLink CC31xx/CC32xx driver: - -# \ref Device - Controls the behaviour of the CC31xx/CC32xx device (start/stop, events masking and obtaining specific device status) - -# \ref FileSystem - Provides file system capabilities to TI's CC31XX that can be used by both the CC31XX device and the user. - -# \ref NetApp - Activates networking applications, such as: HTTP Server, DHCP Server, Ping, DNS and mDNS. - -# \ref NetCfg - Controls the configuration of the device addresses (i.e. IP and MAC addresses) - -# \ref NetUtil - Networking related commands and configuration - -# \ref Socket - Controls standard client/server sockets programming options and capabilities - -# \ref Wlan - Controls the use of the WiFi WLAN module including: - - Connection features, such as: profiles, policies, SmartConfig(tm) - - Advanced WLAN features, such as: scans, rx filters and rx statistics collection - -# \ref UserEvents - Function prototypes for event callback handlers - - \section persistency_sec Persistency - The SimpleLink(tm) device support few different persistency types for settings and configurations:\n - - Temporary - Effective immediately but returned to default after reset\n - - System Persistent - Effective immediately and kept after reset according\n - to system persistent mode\n - - Persistent - Effective immediately and kept after reset regardless the system persistent mode\n - - Optionally Persistent - Effective immediately and kept after reset according to a parameter in the API call\n - - Reset - Persistent but effective only after reset\n - \n - For all Set/Get function in this guide, the type of persistency per relevant parameters will be - described as part of the function description\n - - \section proting_sec Porting Guide - - The porting of the SimpleLink host driver to any new platform is based on few simple steps.\n - This guide takes you through this process step by step. Please follow the instructions - carefully to avoid any problems during this process and to enable efficient and proper - work with the device.\n - Please notice that all modifications and porting adjustments of the driver should be - made in the user.h header file only. Keeping this method ensure smoothly -transaction to new versions of the driver in the future!\n - -The porting process consists of few simple steps: --# Create user.h for the target platform --# Select the capabilities set --# Bind the device enable/disable line --# Writing your interface communication driver --# Choose your memory management model --# OS adaptation --# Set your asynchronous event handlers --# Testing - -For host interface details please refer to: -http://processors.wiki.ti.com/index.php/CC31xx_Host_Interface - -Please see the rest of the page for more details about the different steps. - - \subsection porting_step1 Step 1 - Create your own user.h file - - The first step is to create a user.h file that will include your configurations and - adjustments. \n - The file should be located in the porting directory (the porting directory is in the same level as the source directory)\n - It is recommended to use the empty template provided as part of this driver or - file of other platform such as MSP432 or CC32xx, from one of the wide range - of example applications provided by Texas Instruments. - - \subsection porting_step2 Step 2 - Select the capabilities set required for your application - - Texas Instruments built 3 different predefined sets of capabilities that would fit most of - the target applications.\n - It is recommended to try and choose one of this predefined capabilities set before going to - build your own customized set. If you find compatible set you can skip the rest of this step. - - The available sets are: - -# SL_TINY - Compatible to be used on platforms with very limited resources. Provides - the best in class low foot print in terms of Code and Data consumption. - -# SL_SMALL - Compatible to most common networking applications. Provide the most - common APIs with decent balance between code size, data size, functionality - and performances - -# SL_FULL - Provide access to all SimpleLink functionalities - - \subsection porting_step3 Step 3 - Bind the device enable/disable output line - - The CC31xx has two external hardware lines that can be used to enable/disable the device. - - nReset - - nHib - provides mechanism to enter the device into the least current consumption mode. In - this mode the RTC value is kept. - - The driver manipulates the enable/disable line automatically during sl_Start / sl_Stop.\n - Not connecting one these lines means that the driver could start only once (sl_Stop will not - work correctly and might lead to failure latter on) and the internal provisioning mechanism - could not be used.\n - - To bind these lines the following defines should be defined correctly: - - sl_DeviceEnable - - sl_DeviceDisable - - If some initializations required before the enable/disable macros are called the user can use also the following optional define - - sl_DeviceEnablePreamble - - \subsection porting_step4 Step 4 - Writing your interface communication driver - - The SimpleLink CC31xx has two standard communication interfaces - - SPI - - UART - - The device detects automatically the active interface during initialization. After the detection, the second interface could not be used.\n - - To wrap the driver for the communication channel the following functions should be implemented: - -# sl_IfOpen - -# sl_IfClose - -# sl_IfRead - -# sl_IfWrite - -# sl_IfRegIntHdlr - - The way these functions are implemented has direct effect on the performances of the SimpleLink - device on this target platform. DMA and Jitter Buffer should be considered.\n - - In some platforms the user need to mask the IRQ line when this interrupt could be masked. \n - The driver can call the mask/unmask whenever is needed. To allow this functionality the - user should implement also the following defines: - - sl_IfMaskIntHdlr - - sl_IfUnMaskIntHdlr - - By default the driver is writing the command in few transactions to allow zero-copy mechanism. \n - To enable a Jitter buffer for improving the communication line utilization, the can implement - also the following defines: - - sl_IfStartWriteSequence - - sl_IfEndWriteSequence - - \subsection porting_step5 Step 5 - Choose your memory management model - - The SimpleLink driver support two memory models: - - Static (default) - - Dynamic - - To enable the dynamic memory, the following pre-processor define should be set: \n - #define SL_MEMORY_MGMT_DYNAMIC - - And the following macros should be defined and supplied: - - sl_Malloc - - sl_Free - - Using the dynamic mode will allocate the required resources on sl_Start and release these resource on sl_Stop. - - \subsection porting_step6 Step 6 - OS adaptation - - The SimpleLink driver could run on two kind of platforms: - -# Non-Os / Single Threaded (default) - -# Multi-Threaded - - When building a multi-threaded application. the following pre-processor define must be set: \n - #define SL_PLATFORM_MULTI_THREADED - - If you choose to work in multi-threaded environment under operating system you will have to - provide some basic adaptation routines to allow the driver to protect access to resources - for different threads (locking object) and to allow synchronization between threads (sync objects). - In additional the driver support running without dedicated thread allocated solely to the - SimpleLink driver. If you choose to work in this mode, you should also supply a spawn method that - will enable to run function on a temporary context. - - - \subsection porting_step7 Step 7 - Set your asynchronous event handlers routines - - The SimpleLink device generate asynchronous events in several situations. - These asynchronous events could be masked. - In order to catch these events you have to provide handler routines. - Please notice that if you not provide a handler routine and the event is received, - the driver will drop this event without any indication of this drop. - - - \subsection porting_step8 Step 8 - Run diagnostic tools to validate the correctness of your porting - - The driver is delivered with some porting diagnostic tools to simplify the porting validation process - and to reduce issues latter. It is very important to follow carefully this process. - - The diagnostic process include: - -# Validating interface communication driver - -# Validating basic work with the device - - - \section annex_step Annex Persistency - The SimpleLink(tm) device support few different persistency types for settings and configurations:\n - - Temporary - Effective immediately but returned to default after reset\n - - System Persistent - Effective immediately and kept after reset according\n - - to system persistent mode\n - - Persistent - Effective immediately and kept after reset regardless the system persistent mode\n - - Optionally Persistent - Effective immediately and kept after reset according to a parameter in the API call\n - - Reset - Persistent but effective only after reset\n - -*/ - -#ifndef __SIMPLELINK_H__ -#define __SIMPLELINK_H__ - -/* define the default types - * If user wants to overwrite it, - * he need to undef and define again */ -#define _u8 unsigned char -#define _i8 signed char -#define _u16 unsigned short -#define _i16 signed short -#define _u32 unsigned long -#define _i32 signed long - -#define _volatile volatile -#define _const const - -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! - \defgroup UserEvents - \short Function prototypes for event callback handlers - -*/ - -/*! \attention Async event activation notes\n - Function prototypes for event callback handlers\n - Event handler function names should be defined in the user.h file\n - e.g.\n - "#define slcb_WlanEvtHdlr SLWlanEventHandler"\n - Indicates all WLAN events are handled by User func "SLWlanEventHandler"\n - Important notes:\n - 1. Event handlers cannot activate another SimpleLink API from the event's context - 2. Event's data is valid during event's context. Any application data - which is required for the user application should be copied or marked - into user's variables - 3. It is not recommended to delay the execution of the event callback handler - -*/ - -/*! - - \addtogroup UserEvents - @{ - -*/ - - -/*****************************************************************************/ -/* Macro declarations for Host Driver version */ -/*****************************************************************************/ -#define SL_DRIVER_VERSION "3.0.1.39" -#define SL_MAJOR_VERSION_NUM 3L -#define SL_MINOR_VERSION_NUM 0L -#define SL_VERSION_NUM 1L -#define SL_SUB_VERSION_NUM 39L - -/*****************************************************************************/ -/* Macro declarations for predefined configurations */ -/*****************************************************************************/ - -#ifdef SL_TINY -#undef SL_INC_ARG_CHECK -#undef SL_INC_EXT_API -#undef SL_INC_SOCK_SERVER_SIDE_API -#undef SL_INC_WLAN_PKG -#undef SL_INC_NET_CFG_PKG -#undef SL_INC_FS_PKG -#undef SL_INC_SET_UART_MODE -#undef SL_INC_NVMEM_PKG -#define SL_INC_SOCK_CLIENT_SIDE_API -#define SL_INC_SOCK_RECV_API -#define SL_INC_SOCK_SEND_API -#define SL_INC_SOCKET_PKG -#define SL_INC_NET_APP_PKG -#endif - -#ifdef SL_SMALL -#undef SL_INC_EXT_API -#undef SL_INC_NET_APP_PKG -#undef SL_INC_NET_CFG_PKG -#undef SL_INC_FS_PKG -#define SL_INC_ARG_CHECK -#define SL_INC_WLAN_PKG -#define SL_INC_SOCKET_PKG -#define SL_INC_SOCK_CLIENT_SIDE_API -#define SL_INC_SOCK_SERVER_SIDE_API -#define SL_INC_SOCK_RECV_API -#define SL_INC_SOCK_SEND_API -#define SL_INC_SET_UART_MODE -#endif - -#ifdef SL_FULL -#define SL_INC_EXT_API -#define SL_INC_NET_APP_PKG -#define SL_INC_NET_CFG_PKG -#define SL_INC_FS_PKG -#define SL_INC_ARG_CHECK -#define SL_INC_WLAN_PKG -#define SL_INC_SOCKET_PKG -#define SL_INC_SOCK_CLIENT_SIDE_API -#define SL_INC_SOCK_SERVER_SIDE_API -#define SL_INC_SOCK_RECV_API -#define SL_INC_SOCK_SEND_API -#define SL_INC_SET_UART_MODE -#endif - -/* #define sl_Memcpy memcpy */ -#define sl_Memset(addr, val, len) memset(addr, val, (size_t)len) -#define sl_Memcpy(dest, src, len) memcpy(dest, src, (size_t)len) -#define sl_Memmove(dest, src, len) memmove(dest, src, (size_t)len) - -#ifndef SL_TINY -#define SL_MAX_SOCKETS (_u8)(16) -#else -#define SL_MAX_SOCKETS (_u8)(2) -#endif - -/*****************************************************************************/ -/* Types definitions */ -/*****************************************************************************/ - -#ifndef NULL -#define NULL (0) -#endif - -#ifndef FALSE -#define FALSE (0) -#endif - -#ifndef TRUE -#define TRUE (!FALSE) -#endif - -typedef _u16 _SlOpcode_t; -typedef _u8 _SlArgSize_t; -typedef _i16 _SlDataSize_t; -typedef _i16 _SlReturnVal_t; - -/* - * This event status used to block or continue the event propagation - * through all the registered external libs/user application - * - */ - - typedef enum { - EVENT_PROPAGATION_BLOCK = 0, - EVENT_PROPAGATION_CONTINUE - } _SlEventPropogationStatus_e; - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - - -/* - objInclusion.h and user.h must be included before all api header files - objInclusion.h must be the last arrangement just before including the API header files - since it based on the other configurations to decide which object should be included -*/ -#include "source/objInclusion.h" -#include "trace.h" -#include "fs.h" -#include "sl_socket.h" -#include "netapp.h" -#include "wlan.h" -#include "device.h" -#include "netcfg.h" -#include "netutil.h" -#include "errors.h" -#include "eventreg.h" - -/*! - \cond DOXYGEN_IGNORE -*/ - /* In case of use dynamic event registration - * redirect the event to the internal mechanism */ -#if (defined(SL_RUNTIME_EVENT_REGISTERATION)) - -#define _SlDrvHandleFatalErrorEvents _SlDeviceFatalErrorEvtHdlr -#define _SlDrvHandleGeneralEvents _SlDeviceGeneralEvtHdlr -#define _SlDrvHandleWlanEvents _SlWlanEvtHdlr -#define _SlDrvHandleNetAppEvents _SlNetAppEvtHdlr -#define _SlDrvHandleSockEvents _SlSockEvtHdlr -#define _SlDrvHandleHttpServerEvents _SlNetAppHttpServerHdlr -#define _SlDrvHandleNetAppRequestEvents _SlNetAppRequestHdlr -#define _SlDrvHandleNetAppRequestMemFreeEvents _SlNetAppRequestMemFree -#define _SlDrvHandleSocketTriggerEvents _SlSocketTriggerEventHandler - -#else - - /* The fatal error events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_DeviceFatalErrorEvtHdlr -#define _SlDrvHandleFatalErrorEvents slcb_DeviceFatalErrorEvtHdlr -#endif - - /* The general events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_DeviceGeneralEvtHdlr -#define _SlDrvHandleGeneralEvents slcb_DeviceGeneralEvtHdlr -#endif - - /* The wlan events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_WlanEvtHdlr -#define _SlDrvHandleWlanEvents slcb_WlanEvtHdlr -#endif - - /* The NetApp events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_NetAppEvtHdlr -#define _SlDrvHandleNetAppEvents slcb_NetAppEvtHdlr -#endif - - /* The http server events dispatcher which is - * initialized to the user handler if exists */ -#ifdef slcb_NetAppHttpServerHdlr -#define _SlDrvHandleHttpServerEvents slcb_NetAppHttpServerHdlr -#endif - - /* The socket events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_SockEvtHdlr -#define _SlDrvHandleSockEvents slcb_SockEvtHdlr -#endif - - -/* The netapp requests dispatcher which is - * initialized to the user handler if exists */ -#ifdef slcb_NetAppRequestHdlr -#define _SlDrvHandleNetAppRequestEvents slcb_NetAppRequestHdlr -#endif - -/* The netapp request mem free requests dispatcher which is -* initialized to the user handler if exists */ -#ifdef slcb_NetAppRequestMemFree -#define _SlDrvHandleNetAppRequestMemFreeEvents slcb_NetAppRequestMemFree -#endif - -/* The netapp requests dispatcher which is -* initialized to the user handler if exists */ -#ifdef slcb_SocketTriggerEventHandler -#define _SlDrvHandleSocketTriggerEvents slcb_SocketTriggerEventHandler -#endif - - -#endif - -#define SL_CONCAT(x,y) x ## y -#define SL_CONCAT2(x,y) SL_CONCAT(x,y) - - -#if (!defined(SL_RUNTIME_EVENT_REGISTERATION)) - -/* - * The section below handles the external lib event registration - * according to the desired events it specified in its API header file. - * The external lib should be first installed by the user (see user.h) - */ -#ifdef SL_EXT_LIB_1 - -/* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib1GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_1, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib1WlanEventHandler SL_CONCAT2(SL_EXT_LIB_1, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib1NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_1, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib1HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_1, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib1SockEventHandler SL_CONCAT2(SL_EXT_LIB_1, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib1FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_1, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_1, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - - -#ifdef SL_EXT_LIB_2 - - /* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib2GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_2, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib2WlanEventHandler SL_CONCAT2(SL_EXT_LIB_2, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib2NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_2, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib2HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_2, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib2SockEventHandler SL_CONCAT2(SL_EXT_LIB_2, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib2FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_2, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_2, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - -#ifdef SL_EXT_LIB_3 - - /* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib3GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_3, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib3WlanEventHandler SL_CONCAT2(SL_EXT_LIB_3, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib3NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_3, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib3HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_3, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib3SockEventHandler SL_CONCAT2(SL_EXT_LIB_3, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib3FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_3, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_3, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - -#ifdef SL_EXT_LIB_4 - - /* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib4GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_4, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib4WlanEventHandler SL_CONCAT2(SL_EXT_LIB_4, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib4NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_4, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib4HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_4, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib4SockEventHandler SL_CONCAT2(SL_EXT_LIB_4, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib4FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_4, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_4, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - -#ifdef SL_EXT_LIB_5 - - /* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib5GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_5, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib5WlanEventHandler SL_CONCAT2(SL_EXT_LIB_5, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib5NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_5, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib5HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_5, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib5SockEventHandler SL_CONCAT2(SL_EXT_LIB_5, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib5FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_5, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_5, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - -#if defined(EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) -extern void _SlDrvHandleFatalErrorEvents(SlDeviceEvent_t *slFatalErrorEvent); -#endif - -#if defined(EXT_LIB_REGISTERED_GENERAL_EVENTS) -extern void _SlDrvHandleGeneralEvents(SlDeviceEvent_t *slGeneralEvent); -#endif - -#if defined(EXT_LIB_REGISTERED_WLAN_EVENTS) -extern void _SlDrvHandleWlanEvents(SlWlanEvent_t *slWlanEvent); -#endif - -#if defined (EXT_LIB_REGISTERED_NETAPP_EVENTS) -extern void _SlDrvHandleNetAppEvents(SlNetAppEvent_t *slNetAppEvent); -#endif - -#if defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) -extern void _SlDrvHandleHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse); -#endif - -#if defined(EXT_LIB_REGISTERED_SOCK_EVENTS) -extern void _SlDrvHandleSockEvents(SlSockEvent_t *slSockEvent); -#endif - -#if defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) -extern void _SlDrvHandleNetAppRequestEvents(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -#endif - -#endif //#if (defined(SL_RUNTIME_EVENT_REGISTERATION)) - -typedef _SlReturnVal_t (*_SlSpawnEntryFunc_t)(void* pValue); - -#define SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER (0x1) -#define SL_SPAWN_FLAG_FROM_CMD_CTX (0x2) -#define SL_SPAWN_FLAG_FROM_CMD_PROCESS (0x3) - -#ifdef SL_PLATFORM_MULTI_THREADED - #include "source/spawn.h" -#else - #include "source/nonos.h" -#endif - -/*! - \endcond -*/ - - -/* Async functions description*/ - - -/*! - \brief Fatal Error event for inspecting fatal error - - \param[out] pSlFatalErrorEvent pointer to SlDeviceFatal_t - \return None - \sa - \note - \warning - \par Example - \code - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_DEVICE_ABORT - Indicates a severe error occured and the device stopped - Use pSlDeviceFatal->Data.DeviceAssert fields - - Code: An idication of the abort type - - Value: The abort data - - - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_NO_CMD_ACK - Indicates that the command sent to the device had no ack - Use pSlDeviceFatal->Data.NoCmdAck fields - - Code: An idication of the cmd opcode - - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT - Indicates that the command got a timeout while waiting for its async response - Use pSlDeviceFatal->Data.CmdTimeout fields - - Code: An idication of the asyncevent opcode - - - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_DRIVER_ABORT - Indicates a severe error occured in the driver - Use pSlDeviceFatal->Data.DeviceAssert fields - - None. - - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_SYNC_LOSS - Indicates a sync loss with the device - Use pSlDeviceFatal->Data.DeviceAssert fields - - None. - \endcode - \code - Example for fatal error - printf(Abort type =%d Abort Data=0x%x\n\n", - pSlDeviceFatal->Data.deviceReport.AbortType, - pSlDeviceFatal->Data.deviceReport.AbortData); - \endcode -*/ -#if (defined(slcb_DeviceFatalErrorEvtHdlr)) -extern void slcb_DeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent); -#endif - - -/*! - \brief General async event for inspecting general events - - \param[out] pSlDeviceEvent pointer to SlDeviceEvent_t - \return None - \sa - \note - \warning - \par Example - \code - For pSlDeviceEvent->Id = SL_DEVICE_EVENT_RESET_REQUEST - Use pSlDeviceEvent->Data.ResetRequest fields - - Status: An error code indication from the device - - Source: The sender originator which is based on SlDeviceSource_e enum - - For pSlDeviceEvent->Id = SL_DEVICE_EVENT_ERROR - Use pSlDeviceEvent->Data.Error fields - - Code: An error code indication from the device - - Source: The sender originator which is based on SlErrorSender_e enum - \endcode - \code - Example for error event: - printf(General Event Handler - ID=%d Sender=%d\n\n", - pSlDeviceEvent->Data.Error.Code, // the error code - pSlDeviceEvent->Data.Error.Source); // the error source - \endcode - -*/ -#if (defined(slcb_DeviceGeneralEvtHdlr)) -extern void slcb_DeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent); -#endif - -/*! - \brief WLAN Async event handler - - \param[out] pSlWlanEvent pointer to SlWlanEvent_t data - \return None - \sa - \note - \warning - \par Example - \code - For pSlWlanEvent->Id = SL_WLAN_EVENT_CONNECT, STA connection indication event - Use pSlWlanEvent->Data.Connect main fields - - SsidLen - - SsidName - - Bssid - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CONNECT, P2P client connection indication event - Use pSlWlanEvent->Data.P2PConnect main fields - - SsidLen - - SsidName - - Bssid - - GoDeviceNameLen - - GoDeviceName - - For pSlWlanEvent->Id = SL_WLAN_EVENT_DISCONNECT, STA client disconnection event - Use pSlWlanEvent->Data.Disconnect main fields: - - SsidLen - - SsidName - - Bssid - - ReasonCode - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_DISCONNECT, P2P client disconnection event - Use pSlWlanEvent->Data.P2PDisconnect main fields: - - SsidLen - - SsidName - - Bssid - - ReasonCode - - GoDeviceNameLen - - GoDeviceName - - For pSlWlanEvent->Id = SL_WLAN_EVENT_STA_ADDED, AP connected STA - Use pSlWlanEvent->Data.STAAdded fields: - - Mac - - For pSlWlanEvent->Id = SL_WLAN_EVENT_STA_REMOVED, AP disconnected STA - Use pSlWlanEvent->Data.STARemoved fields: - - Mac - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CLIENT_ADDED, P2P(Go) connected P2P(Client) - Use pSlWlanEvent->Data.P2PClientAdded fields: - - Mac - - GoDeviceNameLen - - GoDeviceName - - OwnSsidLen - - OwnSsid - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CLIENT_REMOVED, P2P(Go) disconnected P2P(Client) - Use pSlWlanEvent->Data.P2PClientRemoved fields: - - Mac - - GoDeviceNameLen - - GoDeviceName - - OwnSsidLen - - OwnSsid - - For pSlWlanEvent->Id = SL_WLAN_P2P_DEV_FOUND_EVENT - Use pSlWlanEvent->Data.P2PDevFound fields: - - GoDeviceNameLen - - GoDeviceName - - Mac - - WpsMethod - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_REQUEST - Use pSlWlanEvent->Data.P2PRequest fields - - GoDeviceNameLen - - GoDeviceName - - Mac - - WpsMethod - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CONNECTFAIL, P2P only - Use pSlWlanEvent->Data.P2PConnectFail fields: - - Status - - For pSlWlanEvent->Id = SL_WLAN_EVENT_PROVISIONING_STATUS - Use pSlWlanEvent->Data.ProvisioningStatus fields - - Status - - For pSlWlanEvent->Id = SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED - Use pSlWlanEvent->Data.ProvisioningProfileAdded fields: - - Status - - SsidLen - - Ssid - - Reserved - \endcode -*/ -#if (defined(slcb_WlanEvtHdlr)) -extern void slcb_WlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent); -#endif - - -/*! - \brief NETAPP Async event handler - - \param[out] pSlNetAppEvent pointer to SlNetAppEvent_t data - \return None - \sa - \note - \warning - \par Example - \code - For pSlNetAppEvent->Id = SL_NETAPP_EVENT_IPV4_ACQUIRED/SL_NETAPP_EVENT_IPV6_ACQUIRED - Use pSlNetAppEvent->Data.ipAcquiredV4 (V6) fields - - ip - - gateway - - dns - - For pSlNetAppEvent->Id = SL_NETAPP_IP_LEASED_EVENT, AP or P2P go dhcp lease event - Use pSlNetAppEvent->Data.ipLeased fields - - ip_address - - lease_time - - mac - - For pSlNetApp->Id = SL_NETAPP_IP_RELEASED_EVENT, AP or P2P go dhcp ip release event - Use pSlNetAppEvent->Data.ipReleased fields - - ip_address - - mac - - reason - \endcode -*/ -#if (defined(slcb_NetAppEvtHdlr)) -extern void slcb_NetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent); -#endif - -/*! - \brief Socket Async event handler - - \param[out] pSlSockEvent pointer to SlSockEvent_t data - \return None - \sa - \note - \warning - \par Example - \code - For pSlSockEvent->Event = SL_SOCKET_TX_FAILED_EVENT - Use pSlSockEvent->SockTxFailData fields - - sd - - status - For pSlSockEvent->Event = SL_SOCKET_ASYNC_EVENT - Use pSlSockEvent->SockAsyncData fields - - sd - - type - - SL_SSL_ACCEPT - - SL_WLAN_RX_FRAGMENTATION_TOO_BIG - - SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED - - val - \endcode - -*/ -#if (defined(slcb_SockEvtHdlr)) -extern void slcb_SockEvtHdlr(SlSockEvent_t* pSlSockEvent); -#endif - -/*! - \brief HTTP server async event - - \param[out] pSlHttpServerEvent Pointer to SlNetAppHttpServerEvent_t - \param[in] pSlHttpServerResponse Pointer to SlNetAppHttpServerResponse_t - - \return None - \sa slcb_NetAppRequestHdlr - \note - \warning - \par Example - \code - For pSlHttpServerResponse->Event = SL_NETAPP_HTTPGETTOKENVALUE_EVENT - Use pSlHttpServerEvent->EventData fields - - httpTokenName - - data - - len - And pSlHttpServerResponse->ResponseData fields - - data - - len - - For pSlHttpServerEvent->Event = SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT - Use pSlHttpServerEvent->EventData.httpPostData fields - - action - - token_name - - token_value - And pSlHttpServerResponse->ResponseData fields: - - data - - len - \endcode -*/ -#if (defined(slcb_NetAppHttpServerHdlr)) -extern void slcb_NetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); -#endif - -/*! - \brief General netapp async event - - \param[out] pNetAppRequest Pointer to SlNetAppRequest_t - \param[in] pNetAppResponse Pointer to SlNetAppResponse_t - - \return None - \sa slcb_NetAppHttpServerHdlr - \note - \warning - \par Example - \code - TBD - \endcode -*/ -#if (defined(slcb_NetAppRequestHdlr)) -extern void slcb_NetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -#endif - -/*! - \brief A handler for freeing the memory of the NetApp response. - - \param[in,out] buffer Pointer to the buffer to free - - \return None - \sa - \note - \warning - \par Example - \code - TBD - \endcode -*/ -#if (defined(slcb_NetAppRequestMemFree)) -extern void slcb_NetAppRequestMemFree (_u8 *buffer); -#endif - -/*! - \brief Get the timer counter value (timestamp).\n - The timer must count from zero to its MAX value. - For non-os application, this routine must be implemented. - \param None - \return Returns 32-bit timer counter value (ticks unit) - \sa - \note - \note belongs to \ref porting_sec - \warning -*/ -#if defined (slcb_GetTimestamp) -extern _u32 slcb_GetTimestamp(void); -#endif - - -/*! - \brief Socket trigger routine. - This routine will notify the application that a netwrok activity has - been completed on the required socket/s. - - \param[out] pSlSockTriggerEvent pointer to SlSockTriggerEvent_t data - \return None. - \sa - \note - \note belongs to \ref porting_sec - \warning -*/ -#if (defined(slcb_SocketTriggerEventHandler)) -extern void slcb_SocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent); -#endif - - -/*! - Close the Doxygen group. - @} - - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SIMPLELINK_H__ */ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/sl_socket.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/sl_socket.h deleted file mode 100755 index e70c6f2ee85..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/sl_socket.h +++ /dev/null @@ -1,1550 +0,0 @@ -/* - * sl_socket.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __SL_SOCKET_H__ -#define __SL_SOCKET_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup Socket - \short Controls standard client/server sockets programming options and capabilities - -*/ -/*! - - \addtogroup Socket - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#undef SL_FD_SETSIZE -#define SL_FD_SETSIZE SL_MAX_SOCKETS /* Number of sockets to select on - same is max sockets! */ -#define SL_BSD_SOCKET_ID_MASK (0x1F) /* Index using the LBS 4 bits for socket id 0-7 */ - -/* Define some BSD protocol constants. */ -#define SL_SOCK_STREAM (1) /* TCP Socket */ -#define SL_SOCK_DGRAM (2) /* UDP Socket */ -#define SL_SOCK_RAW (3) /* Raw socket */ -#define SL_IPPROTO_TCP (6) /* TCP Raw Socket */ -#define SL_IPPROTO_UDP (17) /* UDP Raw Socket */ -#define SL_IPPROTO_RAW (255) /* Raw Socket */ -#define SL_SEC_SOCKET (100) /* Secured Socket Layer (SSL,TLS) */ - -/* Address families. */ -#define SL_AF_INET (2) /* IPv4 socket (UDP, TCP, etc) */ -#define SL_AF_INET6 (3) /* IPv6 socket (UDP, TCP, etc) */ -#define SL_AF_RF (6) /* data include RF parameter, All layer by user (Wifi could be disconnected) */ -#define SL_AF_PACKET (17) -/* Protocol families, same as address families. */ -#define SL_PF_INET AF_INET -#define SL_PF_INET6 AF_INET6 -#define SL_INADDR_ANY (0) /* bind any address */ -#define SL_IN6ADDR_ANY (0) - - -/* Max payload size by protocol */ -#define SL_SOCKET_PAYLOAD_TYPE_MASK (0xF0) /*4 bits type, 4 bits sockets id */ -#define SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER (0x80) /* 1536 bytes */ - -/* SL_SOCKET_EVENT_CLASS_BSD user events */ -#define SL_SOCKET_TX_FAILED_EVENT (1) -#define SL_SOCKET_ASYNC_EVENT (2) - - -/* SL_SOCKET_EVENT_CLASS_BSD user trigger events */ -#define SL_SOCKET_TRIGGER_EVENT_SELECT (1) - -#define SL_SOL_SOCKET (1) /* Define the socket option category. */ -#define SL_IPPROTO_IP (2) /* Define the IP option category. */ -#define SL_SOL_PHY_OPT (3) /* Define the PHY option category. */ - -#define SL_SO_RCVBUF (8) /* Setting TCP receive buffer size */ -#define SL_SO_KEEPALIVE (9) /* Connections are kept alive with periodic messages */ -#define SL_SO_LINGER (13) /* Socket lingers on close pending remaining send/receive packets. */ -#define SL_SO_RCVTIMEO (20) /* Enable receive timeout */ -#define SL_SO_NONBLOCKING (24) /* Enable . disable nonblocking mode */ -#define SL_SO_SECMETHOD (25) /* security metohd */ -#define SL_SO_SECURE_MASK (26) /* security mask */ -#define SL_SO_SECURE_FILES (27) /* security files */ -#define SL_SO_CHANGE_CHANNEL (28) /* This option is available only when transceiver started */ -#define SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME (30) /* This option used to configue secure file */ -#define SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME (31) /* This option used to configue secure file */ -#define SL_SO_SECURE_FILES_CA_FILE_NAME (32) /* This option used to configue secure file */ -#define SL_SO_SECURE_FILES_PEER_CERT_OR_DH_KEY_FILE_NAME (33) /* This option used to configue secure file - in server mode DH params file, and in client mode peer cert for domain verification */ -#define SL_SO_STARTTLS (35) /* initiate STARTTLS on non secure socket */ -#define SL_SO_SSL_CONNECTION_PARAMS (36) /* retrieve by getsockopt the connection params of the current SSL connection in to SlSockSSLConnectionParams_t*/ -#define SL_SO_KEEPALIVETIME (37) /* keepalive time out */ -#define SL_SO_SECURE_DISABLE_CERTIFICATE_STORE (38) /* disable certificate store */ -#define SL_SO_RX_NO_IP_BOUNDARY (39) /* connectionless socket disable rx boundary */ -#define SL_SO_SECURE_ALPN (40) /* set the ALPN bitmap list */ -#define SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP (41) /*set external challange for client certificate */ -#define SL_SO_SECURE_DOMAIN_NAME_VERIFICATION (42) /* set a domain name for verification */ - -#define SL_IP_MULTICAST_IF (60) /* Specify outgoing multicast interface */ -#define SL_IP_MULTICAST_TTL (61) /* Specify the TTL value to use for outgoing multicast packet. */ -#define SL_IP_ADD_MEMBERSHIP (65) /* Join IPv4 multicast membership */ -#define SL_IP_DROP_MEMBERSHIP (66) /* Leave IPv4 multicast membership */ -#define SL_IP_HDRINCL (67) /* Raw socket IPv4 header included. */ -#define SL_IP_RAW_RX_NO_HEADER (68) /* Proprietary socket option that does not includeIPv4/IPv6 header (and extension headers) on received raw sockets*/ -#define SL_IP_RAW_IPV6_HDRINCL (69) /* Transmitted buffer over IPv6 socket contains IPv6 header. */ -#define SL_IPV6_ADD_MEMBERSHIP (70) /* Join IPv6 multicast membership */ -#define SL_IPV6_DROP_MEMBERSHIP (71) /* Leave IPv6 multicast membership */ -#define SL_IPV6_MULTICAST_HOPS (72) /* Specify the hops value to use for outgoing multicast packet. */ - -#define SL_SO_PHY_RATE (100) /* WLAN Transmit rate */ -#define SL_SO_PHY_TX_POWER (101) /* TX Power level */ -#define SL_SO_PHY_NUM_FRAMES_TO_TX (102) /* Number of frames to transmit */ -#define SL_SO_PHY_PREAMBLE (103) /* Preamble for transmission */ -#define SL_SO_PHY_TX_INHIBIT_THRESHOLD (104) /* TX Inhibit Threshold (CCA) */ -#define SL_SO_PHY_TX_TIMEOUT (105) /* TX timeout for Transceiver frames (lifetime) in miliseconds (max value is 100ms) */ -#define SL_SO_PHY_ALLOW_ACKS (106) /* Enable sending ACKs in transceiver mode */ - -typedef enum -{ - SL_TX_INHIBIT_THRESHOLD_MIN = 1, - SL_TX_INHIBIT_THRESHOLD_LOW = 2, - SL_TX_INHIBIT_THRESHOLD_DEFAULT = 3, - SL_TX_INHIBIT_THRESHOLD_MED = 4, - SL_TX_INHIBIT_THRESHOLD_HIGH = 5, - SL_TX_INHIBIT_THRESHOLD_MAX = 6 -} SlTxInhibitThreshold_e; - -#define SL_SO_SEC_METHOD_SSLV3 (0) /* security metohd SSL v3*/ -#define SL_SO_SEC_METHOD_TLSV1 (1) /* security metohd TLS v1*/ -#define SL_SO_SEC_METHOD_TLSV1_1 (2) /* security metohd TLS v1_1*/ -#define SL_SO_SEC_METHOD_TLSV1_2 (3) /* security metohd TLS v1_2*/ -#define SL_SO_SEC_METHOD_SSLv3_TLSV1_2 (4) /* use highest possible version from SSLv3 - TLS 1.2*/ -#define SL_SO_SEC_METHOD_DLSV1 (5) /* security metohd DTL v1 */ - -#define SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA (1 << 0) -#define SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5 (1 << 1) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA (1 << 2) -#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA (1 << 3) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA (1 << 4) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA (1 << 5) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256 (1 << 6) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256 (1 << 7) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (1 << 8) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (1 << 9) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA (1 << 10) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA (1 << 11) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256 (1 << 12) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384 (1 << 13) -#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 14) -#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 15) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 16) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 17) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (1 << 18) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 (1 << 19) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 20) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 21) -#define SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 22) - -#define SL_SEC_MASK_SECURE_DEFAULT ((SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 << 1) - 1) - -#define SL_SECURE_ALPN_H1 (1 << 0) -#define SL_SECURE_ALPN_H2 (1 << 1) -#define SL_SECURE_ALPN_H2C (1 << 2) -#define SL_SECURE_ALPN_H2_14 (1 << 3) -#define SL_SECURE_ALPN_H2_16 (1 << 4) -#define SL_SECURE_ALPN_FULL_LIST ((SL_SECURE_ALPN_H2_16 << 1 ) - 1) - -#define SL_MSG_DONTWAIT (0x00000008) /* Nonblocking IO */ - -/* AP DHCP Server - IP Release reason code */ -#define SL_IP_LEASE_PEER_RELEASE (0) -#define SL_IP_LEASE_PEER_DECLINE (1) -#define SL_IP_LEASE_EXPIRED (2) - -/* possible types when receiving SL_SOCKET_ASYNC_EVENT*/ -#define SL_SSL_ACCEPT (0) /* accept failed due to ssl issue ( tcp pass) */ -#define SL_RX_FRAGMENTATION_TOO_BIG (1) /* connection less mode, rx packet fragmentation > 16K, packet is being released */ -#define SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED (2) /* remote side down from secure to unsecure */ -#define SL_SSL_NOTIFICATION_CONNECTED_SECURED (3) /* STARTTLS success */ -#define SL_SSL_NOTIFICATION_HANDSHAKE_FAILED (4) /* STARTTLS handshake faild */ -#define SL_SSL_NOTIFICATION_WRONG_ROOT_CA (5) /* Root CA configured is wrong, the name is in SocketAsyncEvent.EventData.extraInfo */ -#define SL_SOCKET_ASYNC_EVENT_SSL_NOTIFICATION_WRONG_ROOT_CA (5) -#define SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN (16) - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/* Internet address */ -typedef struct SlInAddr_t -{ -#ifndef s_addr - _u32 s_addr; /* Internet address 32 bits */ -#else - union S_un { - struct { _u8 s_b1,s_b2,s_b3,s_b4; } S_un_b; - struct { _u16 s_w1,s_w2; } S_un_w; - _u32 S_addr; - } S_un; -#endif -}SlInAddr_t; - -/* IpV6 or Ipv6 EUI64 */ -typedef struct SlIn6Addr_t -{ - union - { - _u8 _S6_u8[16]; - _u32 _S6_u32[4]; - } _S6_un; -}SlIn6Addr_t; - - -/* sockopt */ -typedef struct -{ - _u32 KeepaliveEnabled; /* 0 = disabled;1 = enabled; default = 1*/ -}SlSockKeepalive_t; - -typedef struct -{ - _u32 ReuseaddrEnabled; /* 0 = disabled; 1 = enabled; default = 1*/ -}SlSockReuseaddr_t; - -typedef struct -{ - _i32 RxIpNoBoundaryEnabled; /* 0 = keep IP boundary; 1 = don`t keep ip boundary; default = 0; */ -} SlSockRxNoIpBoundary_t; - -typedef struct -{ - _u32 WinSize; /* receive window size for tcp sockets */ -}SlSockWinsize_t; - -typedef struct -{ - _u32 NonBlockingEnabled;/* 0 = disabled;1 = enabled;default = 1*/ -}SlSockNonblocking_t; - -typedef struct -{ - _u8 Sd; - _u8 Type; - _i16 Val; - _i8 pExtraInfo[128]; -} SlSocketAsyncEvent_t; - -typedef struct -{ - _i16 Status; - _u8 Sd; - _u8 Padding; -} SlSockTxFailEventData_t; - - -typedef union -{ - SlSockTxFailEventData_t SockTxFailData; - SlSocketAsyncEvent_t SockAsyncData; -} SlSockEventData_u; - - -typedef struct -{ - _u32 Event; - SlSockEventData_u SocketAsyncEvent; -} SlSockEvent_t; - -typedef struct -{ - _u32 Event; - _u32 EventData; -} SlSockTriggerEvent_t; - - -typedef struct -{ - _u32 SecureALPN; -} SlSockSecureALPN_t; - -typedef struct -{ - _u32 SecureMask; -} SlSockSecureMask_t; - -typedef struct -{ - _u8 SecureMethod; -} SlSockSecureMethod_t; - -typedef struct -{ - _u16 SubjectNameXoredSha1; - _u16 IssuerNameXoredSha1; - _i8 FromDate[8]; - _i8 ToDate[8]; - _i8 SubjectName[SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN]; - _i8 IssuerName[SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN]; - _i8 SubjectNameLen; - _i8 IssuerNameLen; - _i8 Padding[2]; -} SlSockSSLCertInfo_t; - - -typedef struct -{ - _u32 SecureVersion; /* what version of SSL decided in the handshake */ - _u32 SecureCipherSuit; /* what Cipher Index was decided in the handshake */ - _u32 SecureIsPeerValidated; /* was the other peer verified */ - _u32 SecureALPNChosenProtocol; /* bit indicate one of the protocol defined above - SL_SECURE_ALPN_H1 - SL_SECURE_ALPN_H2 - SL_SECURE_ALPN_H2C - SL_SECURE_ALPN_H2_14 - SL_SECURE_ALPN_H2_16 - */ - SlSockSSLCertInfo_t SecurePeerCertinfo; -} SlSockSSLConnectionParams_t; - - - - -typedef enum -{ - SL_SOCK_TX_RATE_1M = 1, - SL_SOCK_TX_RATE_2M = 2, - SL_SOCK_TX_RATE_5_5M = 3, - SL_SOCK_TX_RATE_11M = 4, - SL_SOCK_TX_RATE_6M = 6, - SL_SOCK_TX_RATE_9M = 7, - SL_SOCK_TX_RATE_12M = 8, - SL_SOCK_TX_RATE_18M = 9, - SL_SOCK_TX_RATE_24M = 10, - SL_SOCK_TX_RATE_36M = 11, - SL_SOCK_TX_RATE_48M = 12, - SL_SOCK_TX_RATE_54M = 13, - SL_SOCK_TX_RATE_MCS_0 = 14, - SL_SOCK_TX_RATE_MCS_1 = 15, - SL_SOCK_TX_RATE_MCS_2 = 16, - SL_SOCK_TX_RATE_MCS_3 = 17, - SL_SOCK_TX_RATE_MCS_4 = 18, - SL_SOCK_TX_RATE_MCS_5 = 19, - SL_SOCK_TX_RATE_MCS_6 = 20, - SL_SOCK_TX_RATE_MCS_7 = 21, - SL_SOCK_TX_MAX_NUM_RATES = 0xFF -}slSockTransceiverTXRateTable_e; - - -typedef enum -{ - SL_SOCK_RX_RATE_1M = 0, - SL_SOCK_RX_RATE_2M = 1, - SL_SOCK_RX_RATE_5_5M = 2, - SL_SOCK_RX_RATE_11M = 3, - SL_SOCK_RX_RATE_6M = 4, - SL_SOCK_RX_RATE_9M = 5, - SL_SOCK_RX_RATE_12M = 6, - SL_SOCK_RX_RATE_18M = 7, - SL_SOCK_RX_RATE_24M = 8, - SL_SOCK_RX_RATE_36M = 9, - SL_SOCK_RX_RATE_48M = 10, - SL_SOCK_RX_RATE_54M = 11, - SL_SOCK_RX_RATE_MCS0 = 12, /* 6.5Mbps */ - SL_SOCK_RX_RATE_MCS1 = 13, /* 13Mbps */ - SL_SOCK_RX_RATE_MCS2 = 14, /* 19.5Mbps */ - SL_SOCK_RX_RATE_MCS3 = 15, /* 26Mbps */ - SL_SOCK_RX_RATE_MCS4 = 16, /* 39Mbps */ - SL_SOCK_RX_RATE_MCS5 = 17, /* 52Mbps */ - SL_SOCK_RX_RATE_MCS6 = 18, /* 58.5Mbps */ - SL_SOCK_RX_RATE_MCS7 = 19, /* 65Mbps */ - SL_SOCK_RX_RATE_MCS7_SGI = 20, /* 65Mbps+10% */ - -}SlSockTransceiverRXRates_e; - -typedef enum -{ - SL_BSD_SECURED_PRIVATE_KEY_IDX = 0, - SL_BSD_SECURED_CERTIFICATE_IDX, - SL_BSD_SECURED_CA_IDX, - SL_BSD_SECURED_DH_IDX -}SlSockSecureSocketFilesIndex_e; - -typedef struct -{ - SlInAddr_t imr_multiaddr; /* The IPv4 multicast address to join */ - SlInAddr_t imr_interface; /* The interface to use for this group */ -}SlSockIpMreq_t; - -typedef struct{ - SlIn6Addr_t ipv6mr_multiaddr; /* IPv6 multicast address of group */ - _u32 ipv6mr_interface; /*should be 0 to choose the default multicast interface*/ -}SlSockIpV6Mreq_t; - -typedef struct -{ - _u32 l_onoff; /* 0 = disabled; 1 = enabled; default = 0;*/ - _u32 l_linger; /* linger time in seconds; default = 0;*/ -}SlSocklinger_t; - -/* sockopt */ -typedef _i32 SlTime_t; -typedef _i32 SlSuseconds_t; - -typedef struct SlTimeval_t -{ - SlTime_t tv_sec; /* Seconds */ - SlSuseconds_t tv_usec; /* Microseconds */ -}SlTimeval_t; - -typedef _u16 SlSocklen_t; - -/* IpV4 socket address */ -typedef struct SlSockAddr_t -{ - _u16 sa_family; /* Address family (e.g. , AF_INET) */ - _u8 sa_data[14]; /* Protocol- specific address information*/ -}SlSockAddr_t; - -typedef struct SlSockAddrIn6_t -{ - _u16 sin6_family; /* AF_INET6 || AF_INET6_EUI_48*/ - _u16 sin6_port; /* Transport layer port. */ - _u32 sin6_flowinfo; /* IPv6 flow information. */ - SlIn6Addr_t sin6_addr; /* IPv6 address. */ - _u32 sin6_scope_id; /* set of interfaces for a scope. */ -}SlSockAddrIn6_t; - -/* Socket address, Internet style. */ - -typedef struct SlSockAddrIn_t -{ - _u16 sin_family; /* Internet Protocol (AF_INET). */ - _u16 sin_port; /* Address port (16 bits). */ - SlInAddr_t sin_addr; /* Internet address (32 bits). */ - _i8 sin_zero[8]; /* Not used. */ -}SlSockAddrIn_t; - -typedef struct -{ - _u8 SecureFiles[4]; -}SlSockSecureFiles_t; - -typedef struct SlFdSet_t /* The select socket array manager */ -{ - _u32 fd_array[(SL_FD_SETSIZE + (_u8)31)/(_u8)32]; /* Bit map of SOCKET Descriptors */ -} SlFdSet_t; - -typedef struct -{ - _u8 Rate; /* Received Rate, refer to slSockTransceiverRXRateTable_e */ - _u8 Channel; /* The received channel*/ - _i8 Rssi; /* The computed RSSI value in db of current frame */ - _u8 Padding; /* pad to align to 32 bits */ - _u32 Timestamp; /* Timestamp in microseconds */ -}SlTransceiverRxOverHead_t; - - - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Create an endpoint for communication - - The socket function creates a new socket of a certain socket type, identified - by an integer number, and allocates system resources to it.\n - This function is called by the application layer to obtain a socket handle. - - \param[in] Domain Specifies the protocol family of the created socket. - For example: - - SL_AF_INET for network protocol IPv4 - - SL_AF_INET6 for network protocol IPv6 - - SL_AF_RF for starting transceiver mode. Notes: - - sending and receiving any packet overriding 802.11 header - - for optimized power consumption the socket will be started in TX - only mode until receive command is activated - - \param[in] Type specifies the communication semantic, one of: - - SL_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) - - SL_SOCK_DGRAM (datagram service or Datagram Sockets) - - SL_SOCK_RAW (raw protocols atop the network layer) - - when used with AF_RF: - - SL_SOCK_DGRAM - L2 socket - - SL_SOCK_RAW - L1 socket - bypass WLAN CCA (Clear Channel Assessment) - The Protocol parameter is used to set the channel number. - \param[in] Protocol specifies a particular transport to be used with - the socket. \n - The most common are - - SL_IPPROTO_TCP - - SL_IPPROTO_UDP - The value 0 may be used to select a default - protocol from the selected domain and type - - \return On success, socket handle that is used for consequent socket operations. \n - A successful return code should be a positive number (int16)\n - On error, a negative (int16) value will be returned specifying the error code. - - SL_EAFNOSUPPORT - illegal domain parameter - - SL_EPROTOTYPE - illegal type parameter - - SL_EACCES - permission denied - - SL_ENSOCK - exceeded maximal number of socket - - SL_ENOMEM - memory allocation error - - SL_EINVAL - error in socket configuration - - SL_EPROTONOSUPPORT - illegal protocol parameter - - SL_EOPNOTSUPP - illegal combination of protocol and type parameters - - \sa sl_Close - \note belongs to \ref basic_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Socket) -_i16 sl_Socket(_i16 Domain, _i16 Type, _i16 Protocol); -#endif - -/*! - \brief Gracefully close socket - - This function causes the system to release resources allocated to a socket. \n - In case of TCP, the connection is terminated. - - \param[in] sd Socket handle (received in sl_Socket) - - \return Zero on success, or negative error code on failure - - \sa sl_Socket - \note belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Close) -_i16 sl_Close(_i16 sd); -#endif - -/*! - \brief Accept a connection on a socket - - This function is used with connection-based socket types (SOCK_STREAM).\n - It extracts the first connection request on the queue of pending - connections, creates a new connected socket, and returns a new file - descriptor referring to that socket.\n - The newly created socket is not in the listening state. The - original socket sd is unaffected by this call. \n - The argument sd is a socket that has been created with - sl_Socket(), bound to a local address with sl_Bind(), and is - listening for connections after a sl_Listen(). The argument \b - \e addr is a pointer to a sockaddr structure. This structure - is filled in with the address of the peer socket, as known to - the communications layer. The exact format of the address - returned addr is determined by the socket's address family. \n - The \b \e addrlen argument is a value-result argument: it - should initially contain the size of the structure pointed to - by addr, on return it will contain the actual length (in - bytes) of the address returned. - - \param[in] sd Socket descriptor (handle) - \param[out] addr The argument addr is a pointer - to a sockaddr structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - sockaddr:\n - code for the - address format. On this version - only AF_INET is supported.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - - \return On success, a socket handle.\n - On a non-blocking accept a possible negative value is SL_EAGAIN.\n - On failure, negative error code.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_Socket sl_Bind sl_Listen - \note Belongs to \ref server_side - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Accept) -_i16 sl_Accept(_i16 sd, SlSockAddr_t *addr, SlSocklen_t *addrlen); -#endif - -/*! - \brief Assign a name to a socket - - This function gives the socket the local address addr. - addr is addrlen bytes long. Traditionally, this is called - When a socket is created with socket, it exists in a name - space (address family) but has no name assigned. - It is necessary to assign a local address before a SOCK_STREAM - socket may receive connections. - - \param[in] sd Socket descriptor (handle) - \param[in] addr Specifies the destination - addrs\n sockaddr:\n - code for - the address format. On this - version only SL_AF_INET is - supported.\n - socket address, - the length depends on the code - format - \param[in] addrlen Contains the size of the structure pointed to by addr - - \return Zero on success, or negative error code on failure - - \sa sl_Socket sl_Accept sl_Listen - \note belongs to \ref basic_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Bind) -_i16 sl_Bind(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen); -#endif - -/*! - \brief Listen for connections on a socket - - The willingness to accept incoming connections and a queue - limit for incoming connections are specified with listen(), - and then the connections are accepted with accept. - The listen() call applies only to sockets of type SOCK_STREAM - The backlog parameter defines the maximum length the queue of - pending connections may grow to. - - \param[in] sd Socket descriptor (handle) - \param[in] backlog Specifies the listen queue depth. - - \return Zero on success, or negative error code on failure - - \sa sl_Socket sl_Accept sl_Bind - \note Belongs to \ref server_side - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Listen) -_i16 sl_Listen(_i16 sd, _i16 backlog); -#endif - -/*! - \brief Initiate a connection on a socket - - Function connects the socket referred to by the socket - descriptor sd, to the address specified by addr. The addrlen - argument specifies the size of addr. The format of the - address in addr is determined by the address space of the - socket. If it is of type SOCK_DGRAM, this call specifies the - peer with which the socket is to be associated; this address - is that to which datagrams are to be sent, and the only - address from which datagrams are to be received. If the - socket is of type SOCK_STREAM, this call attempts to make a - connection to another socket. The other socket is specified - by address, which is an address in the communications space - of the socket. - - - \param[in] sd Socket descriptor (handle) - \param[in] addr Specifies the destination addr\n - sockaddr:\n - code for the - address format. On this version - only AF_INET is supported.\n - - socket address, the length - depends on the code format - - \param[in] addrlen Contains the size of the structure pointed - to by addr - - \return On success, a socket handle.\n - On a non-blocking connect a possible negative value is SL_EALREADY. - On failure, negative value.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_Socket - \note belongs to \ref client_side - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Connect) -_i16 sl_Connect(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen); -#endif - -/*! - \brief Monitor socket activity - - Select allow a program to monitor multiple file descriptors, - waiting until one or more of the file descriptors become - "ready" for some class of I/O operation. - If trigger mode is enabled the active fdset is the one that was retrieved in the first triggered call. - To enable the trigger mode, an handler must be statically registered as slcb_SocketTriggerEventHandler in user.h - - - \param[in] nfds The highest-numbered file descriptor in any of the - three sets, plus 1. - \param[out] readsds Socket descriptors list for read monitoring and accept monitoring - \param[out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported - \param[out] exceptsds Socket descriptors list for exception monitoring, not supported. - \param[in] timeout Is an upper bound on the amount of time elapsed - before select() returns. Null or above 0xffff seconds means - infinity timeout. The minimum timeout is 10 milliseconds, - less than 10 milliseconds will be set automatically to 10 milliseconds. - Max microseconds supported is 0xfffc00. - In trigger mode the timout fields must be set to zero. - - \return On success, select() returns the number of - file descriptors contained in the three returned - descriptor sets (that is, the total number of bits that - are set in readfds, writefds, exceptfds) which may be - zero if the timeout expires before anything interesting - happens.\n On error, a negative value is returned. - readsds - return the sockets on which read request will - return without delay with valid data.\n - writesds - return the sockets on which write request - will return without delay.\n - exceptsds - return the sockets closed recently. \n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_Socket - \note If the timeout value set to less than 10ms it will automatically set - to 10ms to prevent overload of the system\n - Belongs to \ref basic_api - - Several threads can call sl_Select at the same time.\b - Calling this API while the same command is called from another thread, may result - in one of the following scenarios: - 1. The command will be executed alongside other select callers (success). - 2. The command will wait (internal) until the previous sl_select finish, and then be executed. - 3. There are not enough resources and SL_POOL_IS_EMPTY error will return. - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - - In case all the user sockets are open, sl_Select will exhibit the behavior mentioned in (2) - This is due to the fact sl_select supports multiple callers by utilizing one user socket internally. - User who wish to ensure multiple select calls at any given time, must reserve one socket out of the 16 given. - - \warning - multiple select calls aren't supported when trigger mode is active. The two are mutually exclusive. -*/ -#if _SL_INCLUDE_FUNC(sl_Select) -_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout); -#endif - - - -/*! - \brief Set socket options- - - This function manipulate the options associated with a socket.\n - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level.\n - - When manipulating socket options the level at which the option resides - and the name of the option must be specified. To manipulate options at - the socket level, level is specified as SOL_SOCKET. To manipulate - options at any other level the protocol number of the appropriate proto- - col controlling the option is supplied. For example, to indicate that an - option is to be interpreted by the TCP protocol, level should be set to - the protocol number of TCP; \n - - The parameters optval and optlen are used to access optval - - ues for setsockopt(). For getsockopt() they identify a - buffer in which the value for the requested option(s) are to - be returned. For getsockopt(), optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, option_value may be - NULL. - - \param[in] sd Socket handle - \param[in] level Defines the protocol level for this option - - SL_SOL_SOCKET Socket level configurations (L4, transport layer) - - SL_IPPROTO_IP IP level configurations (L3, network layer) - - SL_SOL_PHY_OPT Link level configurations (L2, link layer) - \param[in] optname Defines the option name to interrogate - - SL_SOL_SOCKET - - SL_SO_KEEPALIVE \n - Enable/Disable periodic keep alive. - Keeps TCP connections active by enabling the periodic transmission of messages \n - Timeout is 5 minutes.\n - Default: Enabled \n - This options takes SlSockKeepalive_t struct as parameter - - SL_SO_KEEPALIVETIME \n - Set keep alive timeout. - Value is in seconds \n - Default: 5 minutes \n - - SL_SO_RX_NO_IP_BOUNDARY \n - Enable/Disable rx ip boundary. - In connectionless socket (udp/raw), unread data is dropped (when recvfrom len parameter < data size), Enable this option in order to read the left data on the next recvfrom iteration - Default: Disabled, IP boundary kept, \n - This options takes SlSockRxNoIpBoundary_t struct as parameter - - SL_SO_RCVTIMEO \n - Sets the timeout value that specifies the maximum amount of time an input function waits until it completes. \n - Default: No timeout \n - This options takes SlTimeval_t struct as parameter - - SL_SO_RCVBUF \n - Sets tcp max recv window size. \n - This options takes SlSockWinsize_t struct as parameter - - SL_SO_NONBLOCKING \n - Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n - Default: Blocking. - This options takes SlSockNonblocking_t struct as parameter - - SL_SO_SECMETHOD \n - Sets method to tcp secured socket (SL_SEC_SOCKET) \n - Default: SL_SO_SEC_METHOD_SSLv3_TLSV1_2 \n - This options takes SlSockSecureMethod_t struct as parameter - - SL_SO_SECURE_MASK \n - Sets specific cipher to tcp secured socket (SL_SEC_SOCKET) \n - Default: "Best" cipher suitable to method \n - This options takes SlSockSecureMask_t struct as parameter - - SL_SO_SECURE_FILES_CA_FILE_NAME \n - Map secured socket to CA file by name \n - This options takes _u8 buffer as parameter - - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME \n - Map secured socket to private key by name \n - This options takes _u8 buffer as parameter - - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME \n - Map secured socket to certificate file by name \n - This options takes _u8 buffer as parameter - - SL_SO_SECURE_FILES_DH_KEY_FILE_NAME \n - Map secured socket to Diffie Hellman file by name \n - This options takes _u8 buffer as parameter - - SL_SO_CHANGE_CHANNEL \n - Sets channel in transceiver mode. - This options takes _u32 as channel number parameter - - SL_SO_SECURE_ALPN \n - Sets the ALPN list. the parameter is a bit map consist of or of the following values - - SL_SECURE_ALPN_H1 - SL_SECURE_ALPN_H2 - SL_SECURE_ALPN_H2C - SL_SECURE_ALPN_H2_14 - SL_SECURE_ALPN_H2_16 - SL_SECURE_ALPN_FULL_LIST - - SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP \n - Set with no parameter to indicate that the client uses external signature using netapp request.\n - needs netapp request handler\n - - SL_SO_SECURE_DOMAIN_NAME_VERIFICATION \n - Set a domain name, to check in ssl client connection. - - SL_IPPROTO_IP - - SL_IP_MULTICAST_TTL \n - Set the time-to-live value of outgoing multicast packets for this socket. \n - This options takes _u8 as parameter - - SL_IP_ADD_MEMBERSHIP \n - UDP socket, Join a multicast group. \n - This options takes SlSockIpMreq_t struct as parameter - - SL_IP_DROP_MEMBERSHIP \n - UDP socket, Leave a multicast group \n - This options takes SlSockIpMreq_t struct as parameter - - SL_IP_RAW_RX_NO_HEADER \n - Raw socket remove IP header from received data. \n - Default: data includes ip header \n - This options takes _u32 as parameter - - SL_IP_HDRINCL \n - RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. \n - When it is enabled, the packet must contain an IP header. \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes _u32 as parameter - - SL_IP_RAW_IPV6_HDRINCL (inactive) \n - RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes _u32 as parameter - - SL_SOL_PHY_OPT - - SL_SO_PHY_RATE \n - RAW socket, set WLAN PHY transmit rate \n - The values are based on SlWlanRateIndex_e \n - This options takes _u32 as parameter - - SL_SO_PHY_TX_POWER \n - RAW socket, set WLAN PHY TX power \n - Valid rage is 1-15 \n - This options takes _u32 as parameter - - SL_SO_PHY_NUM_FRAMES_TO_TX \n - RAW socket, set number of frames to transmit in transceiver mode. - Default: 1 packet - This options takes _u32 as parameter - - SL_SO_PHY_PREAMBLE \n - RAW socket, set WLAN PHY preamble for Long/Short\n - This options takes _u32 as parameter - - SL_SO_PHY_TX_INHIBIT_THRESHOLD \n - RAW socket, set WLAN Tx � Set CCA threshold. \n - The values are based on SlTxInhibitThreshold_e \n - This options takes _u32 as parameter - - SL_SO_PHY_TX_TIMEOUT \n - RAW socket, set WLAN Tx � changes the TX timeout (lifetime) of transceiver frames. \n - Value in Ms, maximum value is 100ms \n - This options takes _u32 as parameter - - SL_SO_PHY_ALLOW_ACKS \n - RAW socket, set WLAN Tx � Enable\Disable sending ACKs in transceiver mode \n - 0 = disabled / 1 = enabled \n - This options takes _u32 as parameter - - SL_SO_LINGER \n - Socket lingers on close pending remaining send/receive packets\n - - \param[in] optval Specifies a value for the option - \param[in] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - - \par Persistent - All params are Non- Persistent - \sa sl_getsockopt - \note Belongs to \ref basic_api - \warning - \par Examples - - - SL_SO_KEEPALIVE (disable Keepalive): - \code - SlSockKeepalive_t enableOption; - enableOption.KeepaliveEnabled = 0; - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_KEEPALIVE, (_u8 *)&enableOption,sizeof(enableOption)); - \endcode -
- - - SL_SO_KEEPALIVETIME (Set Keepalive timeout): - \code - _i16 Status; - _u32 TimeOut = 120; - sl_SetSockOpt(Sd, SL_SOL_SOCKET, SL_SO_KEEPALIVETIME,( _u8*) &TimeOut, sizeof(TimeOut)); - \endcode -
- - - SL_SO_RX_NO_IP_BOUNDARY (disable boundary): - \code - SlSockRxNoIpBoundary_t enableOption; - enableOption.RxIpNoBoundaryEnabled = 1; - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RX_NO_IP_BOUNDARY, (_u8 *)&enableOption,sizeof(enableOption)); - \endcode -
- - - SL_SO_RCVTIMEO: - \code - struct SlTimeval_t timeVal; - timeVal.tv_sec = 1; // Seconds - timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RCVTIMEO, (_u8 *)&timeVal, sizeof(timeVal)); // Enable receive timeout - \endcode -
- - - SL_SO_RCVBUF: - \code - SlSockWinsize_t size; - size.Winsize = 3000; // bytes - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RCVBUF, (_u8 *)&size, sizeof(size)); - \endcode -
- - - SL_SO_NONBLOCKING: - \code - - SlSockNonblocking_t enableOption; - enableOption.NonblockingEnabled = 1; - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_NONBLOCKING, (_u8 *)&enableOption,sizeof(enableOption)); // Enable/disable nonblocking mode - \endcode -
- - - SL_SO_SECMETHOD: - \code - SlSockSecureMethod_t method; - method.SecureMethod = SL_SO_SEC_METHOD_SSLV3; // security method we want to use - SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, SL_SEC_SOCKET); - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECMETHOD, (_u8 *)&method, sizeof(method)); - \endcode -
- - - SL_SO_SECURE_MASK: - \code - SlSockSecureMask_t cipher; - cipher.SecureMask = SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA; // cipher type - SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, SL_SEC_SOCKET); - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_MASK,(_u8 *)&cipher, sizeof(cipher)); - \endcode -
- - - SL_SO_SECURE_FILES_CA_FILE_NAME: - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_CA_FILE_NAME,"exuifaxCaCert.der",strlen("exuifaxCaCert.der")); - \endcode -
- - - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME; - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME,"myPrivateKey.der",strlen("myPrivateKey.der")); - \endcode -
- - - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME: - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME,"myCertificate.der",strlen("myCertificate.der")); - \endcode -
- - - SL_SO_SECURE_FILES_DH_KEY_FILE_NAME: - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_DH_KEY_FILE_NAME,"myDHinServerMode.der",strlen("myDHinServerMode.der")); - \endcode -
- - - - SL_IP_MULTICAST_TTL: - \code - _u8 ttl = 20; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_MULTICAST_TTL, &ttl, sizeof(ttl)); - \endcode -
- - - SL_IP_ADD_MEMBERSHIP: - \code - SlSockIpMreq_t mreq; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SL_IP_DROP_MEMBERSHIP: - \code - SlSockIpMreq_t mreq; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SL_SO_CHANGE_CHANNEL: - \code - _u32 newChannel = 6; // range is 1-13 - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_CHANGE_CHANNEL, &newChannel, sizeof(newChannel)); - \endcode -
- - - SL_SO_SECURE_ALPN: - \code - SlSockSecureALPN_t alpn; - alpn.SecureALPN = SL_SECURE_ALPN_H2 | SL_SECURE_ALPN_H2_14; - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_ALPN, &alpn, sizeof(SlSockSecureALPN_t)); - \endcode -
- - - SL_IP_RAW_RX_NO_HEADER: - \code - _u32 header = 1; // remove ip header - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_RAW_RX_NO_HEADER, &header, sizeof(header)); - \endcode -
- - - SL_IP_HDRINCL: - \code - _u32 header = 1; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SL_IP_RAW_IPV6_HDRINCL: - \code - _u32 header = 1; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_RAW_IPV6_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SL_SO_PHY_RATE: - \code - _u32 rate = 6; // see wlan.h SlWlanRateIndex_e for values - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_RATE, &rate, sizeof(rate)); - \endcode -
- - - SL_SO_PHY_TX_POWER: - \code - _u32 txpower = 1; // valid range is 1-15 - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_POWER, &txpower, sizeof(txpower)); - \endcode -
- - - SL_SO_PHY_NUM_FRAMES_TO_TX: - \code - _u32 numframes = 1; - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); - \endcode -
- - - SL_SO_PHY_PREAMBLE: - \code - _u32 preamble = 1; - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_PREAMBLE, &preamble, sizeof(preamble)); - \endcode -
- - - SL_SO_PHY_TX_INHIBIT_THRESHOLD: - \code - _u32 thrshld = SL_TX_INHIBIT_THRESHOLD_MED; - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_INHIBIT_THRESHOLD , &thrshld, sizeof(thrshld)); - \endcode -
- - - SL_SO_PHY_TX_TIMEOUT: - \code - _u32 timeout = 50; - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_TIMEOUT , &timeout, sizeof(timeout)); - \endcode -
- - - SL_SO_PHY_ALLOW_ACKS: - \code - _u32 acks = 1; // 0 = disabled / 1 = enabled - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_ALLOW_ACKS, &acks, sizeof(acks)); - \endcode -
- - - SL_SO_LINGER: - \code - SlSocklinger_t linger; - linger.l_onoff = 1; - linger.l_linger = 10; - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_LINGER, &linger, sizeof(linger)); - \endcode -
- - - SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP: - \code - int dummy; - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP, &dummy, sizeof(dummy)); - \endcode -
- - - SL_SO_SECURE_DOMAIN_NAME_VERIFICATION: - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_DOMAIN_NAME_VERIFICATION,"www.google.co.il",strlen("www.google.co.il")); - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_SetSockOpt) -_i16 sl_SetSockOpt(_i16 sd, _i16 level, _i16 optname, const void *optval, SlSocklen_t optlen); -#endif - -/*! - \brief Get socket options - - This function manipulate the options associated with a socket. - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level.\n - - When manipulating socket options the level at which the option resides - and the name of the option must be specified. To manipulate options at - the socket level, level is specified as SOL_SOCKET. To manipulate - options at any other level the protocol number of the appropriate - protocol controlling the option is supplied. For example, to indicate - that an option is to be interpreted by the TCP protocol, level should - be set to the protocol number of TCP; \n - - The parameters optval and optlen are used to access optvalues - for setsockopt(). For getsockopt() they identify a - buffer in which the value for the requested option(s) are to - be returned. For getsockopt(), optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, option_value may be - NULL. - - - \param[in] sd Socket handle - \param[in] level Defines the protocol level for this option - \param[in] optname defines the option name to interrogate - \param[out] optval Specifies a value for the option - \param[out] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - \sa sl_SetSockOpt - \note See sl_SetSockOpt - Belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_GetSockOpt) -_i16 sl_GetSockOpt(_i16 sd, _i16 level, _i16 optname, void *optval, SlSocklen_t *optlen); -#endif - -/*! - \brief Read data from TCP socket - - Function receives a message from a connection-mode socket - - \param[in] sd Socket handle - \param[out] buf Points to the buffer where the - message should be stored. - \param[in] len Specifies the length in bytes of - the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Specifies the type of message - reception. On this version, this parameter is not - supported. - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SL_EAGAIN.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_RecvFrom - \note Belongs to \ref recv_api - \warning - \par Examples - - - Receiving data using TCP socket: - \code - SlSockAddrIn_t Addr; - SlSockAddrIn_t LocalAddr; - _i16 AddrSize = sizeof(SlSockAddrIn_t); - _i16 SockID, newSockID; - _i16 Status; - _i8 Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SL_AF_INET; - LocalAddr.sin_port = sl_Htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - Addr.sin_family = SL_AF_INET; - Addr.sin_port = sl_Htons(5001); - Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); - - SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); - Status = sl_Bind(SockID, (SlSockAddr_t *)&LocalAddr, AddrSize); - Status = sl_Listen(SockID, 0); - newSockID = sl_Accept(SockID, (SlSockAddr_t*)&Addr, (SlSocklen_t*) &AddrSize); - Status = sl_Recv(newSockID, Buf, 1460, 0); - \endcode -
- - - Rx transceiver mode using a raw socket: - \code - _i8 buffer[1536]; - _i16 sd; - _u16 size; - SlTransceiverRxOverHead_t *transHeader; - sd = sl_Socket(SL_AF_RF,SL_SOCK_RAW,11); // channel 11 - while(1) - { - size = sl_Recv(sd,buffer,1536,0); - transHeader = (SlTransceiverRxOverHead_t *)buffer; - printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlTransceiverRxOverHead_t)],size); - } - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_Recv) -_i16 sl_Recv(_i16 sd, void *buf, _i16 len, _i16 flags); -#endif - -/*! - \brief Read data from socket - - Function receives a message from a connection-mode or - connectionless-mode socket - - \param[in] sd Socket handle - \param[out] buf Points to the buffer where the message should be stored. - \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Specifies the type of message - reception. On this version, this parameter is not - supported. - \param[in] from Pointer to an address structure - indicating the source - address.\n sockaddr:\n - code - for the address format. On this - version only AF_INET is - supported.\n - socket address, - the length depends on the code - format - \param[in] fromlen Source address structure - size. This parameter MUST be set to the size of the structure pointed to by addr. - - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SL_EAGAIN. - SL_RET_CODE_INVALID_INPUT (-2) will be returned if fromlen has incorrect length. \n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_Recv - \note Belongs to \ref recv_api - \warning - \par Example - - - Receiving data: - \code - SlSockAddrIn_t Addr; - SlSockAddrIn_t LocalAddr; - _i16 AddrSize = sizeof(SlSockAddrIn_t); - _i16 SockID; - _i16 Status; - _i8 Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SL_AF_INET; - LocalAddr.sin_port = sl_Htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - SockID = sl_Socket(SL_AF_INET,SL_SOCK_DGRAM, 0); - Status = sl_Bind(SockID, (SlSockAddr_t *)&LocalAddr, AddrSize); - Status = sl_RecvFrom(SockID, Buf, 1472, 0, (SlSockAddr_t *)&Addr, (SlSocklen_t*)&AddrSize); - - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_RecvFrom) -_i16 sl_RecvFrom(_i16 sd, void *buf, _i16 len, _i16 flags, SlSockAddr_t *from, SlSocklen_t *fromlen); -#endif - -/*! - \brief Write data to TCP socket - - This function is used to transmit a message to another socket. - Returns immediately after sending data to device. - In case of TCP failure an async event SL_SOCKET_TX_FAILED_EVENT is going to - be received.\n - In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the - frame data buffer for WLAN FCS - - \param[in] sd Socket handle - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len Message size in bytes. Range: 1-1460 bytes - \param[in] flags Specifies the type of message - transmission. On this version, this parameter is not - supported for TCP. - For transceiver mode, the SL_WLAN_RAW_RF_TX_PARAMS macro can be used to determine - transmission parameters (channel,rate,tx_power,preamble) - -rate need to be define using slSockTransceiverTXRateTable_e - - - \return Zero on success, or negative error code on failure - - \sa sl_SendTo - \note Belongs to \ref send_api - \warning - \par Example - - - Sending data: - \code - SlSockAddrIn_t Addr; - _i16 AddrSize = sizeof(SlSockAddrIn_t); - _i16 SockID; - _i16 Status; - _i8 Buf[SEND_BUF_LEN]; - - Addr.sin_family = SL_AF_INET; - Addr.sin_port = sl_Htons(5001); - Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); - - SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); - Status = sl_Connect(SockID, (SlSockAddr_t *)&Addr, AddrSize); - Status = sl_Send(SockID, Buf, 1460, 0 ); - \endcode - */ -#if _SL_INCLUDE_FUNC(sl_Send ) -_i16 sl_Send(_i16 sd, const void *buf, _i16 len, _i16 flags); -#endif - -/*! - \brief Write data to socket - - This function is used to transmit a message to another socket - (connection less socket SOCK_DGRAM, SOCK_RAW).\n - Returns immediately after sending data to device.\n - In case of transmission failure an async event SL_SOCKET_TX_FAILED_EVENT is going to - be received. - - \param[in] sd Socket handle - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len message size in bytes. Range: 1-1460 bytes - \param[in] flags Specifies the type of message - transmission. On this version, this parameter is not - supported - \param[in] to Pointer to an address structure - indicating the destination - address.\n sockaddr:\n - code - for the address format. On this - version only AF_INET is - supported.\n - socket address, - the length depends on the code - format - \param[in] tolen Destination address structure size - - \return Zero on success, or negative error code on failure - - \sa sl_Send - \note Belongs to \ref send_api - \warning - \par Example - - - Sending data: - \code - SlSockAddrIn_t Addr; - _i16 AddrSize = sizeof(SlSockAddrIn_t); - _i16 SockID; - _i16 Status; - _i8 Buf[SEND_BUF_LEN]; - - Addr.sin_family = SL_AF_INET; - Addr.sin_port = sl_Htons(5001); - Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); - - SockID = sl_Socket(SL_AF_INET,SL_SOCK_DGRAM, 0); - Status = sl_SendTo(SockID, Buf, 1472, 0, (SlSockAddr_t *)&Addr, AddrSize); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_SendTo) -_i16 sl_SendTo(_i16 sd, const void *buf, _i16 len, _i16 flags, const SlSockAddr_t *to, SlSocklen_t tolen); -#endif - -/*! - \brief Initiate TLS connection on a socket - - Function Initiate TLS connection on the socket referred to by - the socket descriptor sd. This function will works on blocking - mode until the TLS handshake success or fails. - - \param[in] sd Socket descriptor (handle) - - \return Zero on success, or negative error code on failure - - \sa sl_Socket - \note belongs to \ref client_side - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_StartTLS) -_i16 sl_StartTLS(_i16 sd); -#endif - -/*! - \brief Reorder the bytes of a 32-bit unsigned value - - This function is used to Reorder the bytes of a 32-bit unsigned value from processor order to network order. - - \param[in] val Variable to reorder - - \return Return the reorder variable, - - \sa sl_SendTo sl_Bind sl_Connect sl_RecvFrom sl_Accept - \note Belongs to \ref send_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Htonl ) -_u32 sl_Htonl( _u32 val ); - -#define sl_Ntohl sl_Htonl /* Reorder the bytes of a 16-bit unsigned value from network order to processor orde. */ -#endif - -/*! - \brief Reorder the bytes of a 16-bit unsigned value - - This function is used to Reorder the bytes of a 16-bit unsigned value from processor order to network order. - - \param[in] val Variable to reorder - - \return Return the reorder variable, - - \sa sl_SendTo sl_Bind sl_Connect sl_RecvFrom sl_Accept - \note Belongs to \ref send_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Htons ) -_u16 sl_Htons( _u16 val ); - -#define sl_Ntohs sl_Htons /* Reorder the bytes of a 16-bit unsigned value from network order to processor orde. */ -#endif - -/*! - \cond DOXYGEN_IGNORE -*/ - -/*! - \brief Select's SlFdSet_t SET function - - Sets current socket descriptor on SlFdSet_t container -*/ -void SL_SOCKET_FD_SET(_i16 fd, SlFdSet_t *fdset); - -/*! - \brief Select's SlFdSet_t CLR function - - Clears current socket descriptor on SlFdSet_t container -*/ -void SL_SOCKET_FD_CLR(_i16 fd, SlFdSet_t *fdset); - - -/*! - \brief Select's SlFdSet_t ISSET function - - Checks if current socket descriptor is set (TRUE/FALSE) - - \return Returns TRUE if set, FALSE if unset - -*/ -_i16 SL_SOCKET_FD_ISSET(_i16 fd, SlFdSet_t *fdset); - -/*! - \brief Select's SlFdSet_t ZERO function - - Clears all socket descriptors from SlFdSet_t -*/ -void SL_SOCKET_FD_ZERO(SlFdSet_t *fdset); - -/*! - \endcond -*/ - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SOCKET_H__ */ - - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetif/slnetifwifi.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetif/slnetifwifi.c deleted file mode 100755 index 9d9c2d15a22..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetif/slnetifwifi.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* Macro which split the 8bit security flags from the input flags */ -#define SPLIT_SEC_AND_INPUT_FLAGS(inputFlags, secFlags) (secFlags = inputFlags >> 24) - -/* Disable the 8bit security flags */ -#define SECURITY_FLAGS_IN_32BIT_REPRESENTATION (0xFF000000) -#define DISABLE_SEC_BITS_FROM_INPUT_FLAGS(inputFlags) (inputFlags &= ~SECURITY_FLAGS_IN_32BIT_REPRESENTATION) - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Global declarations */ -/*****************************************************************************/ - -/*! - SlNetIfConfigWifi structure contains all the function callbacks that are expected to be filled by the relevant network stack interface - Each interface has different capabilities, so not all the API's must be supported. - Interface that is not supporting a non-mandatory API are set to NULL -*/ -SlNetIf_Config_t SlNetIfConfigWifi = -{ - SlNetIfWifi_socket, // Callback function sockCreate in slnetif module - SlNetIfWifi_close, // Callback function sockClose in slnetif module - NULL, // Callback function sockShutdown in slnetif module - SlNetIfWifi_accept, // Callback function sockAccept in slnetif module - SlNetIfWifi_bind, // Callback function sockBind in slnetif module - SlNetIfWifi_listen, // Callback function sockListen in slnetif module - SlNetIfWifi_connect, // Callback function sockConnect in slnetif module - NULL, // Callback function sockGetPeerName in slnetif module - NULL, // Callback function sockGetLocalName in slnetif module - SlNetIfWifi_select, // Callback function sockSelect in slnetif module - SlNetIfWifi_setSockOpt, // Callback function sockSetOpt in slnetif module - SlNetIfWifi_getSockOpt, // Callback function sockGetOpt in slnetif module - SlNetIfWifi_recv, // Callback function sockRecv in slnetif module - SlNetIfWifi_recvFrom, // Callback function sockRecvFrom in slnetif module - SlNetIfWifi_send, // Callback function sockSend in slnetif module - SlNetIfWifi_sendTo, // Callback function sockSendTo in slnetif module - SlNetIfWifi_sockstartSec, // Callback function sockstartSec in slnetif module - SlNetIfWifi_getHostByName, // Callback function utilGetHostByName in slnetif module - SlNetIfWifi_getIPAddr, // Callback function ifGetIPAddr in slnetif module - SlNetIfWifi_getConnectionStatus, // Callback function ifGetConnectionStatus in slnetif module - SlNetIfWifi_loadSecObj, // Callback function ifLoadSecObj in slnetif module - NULL // Callback function ifCreateContext in slnetif module -}; - -static const int16_t StartSecOptName[10] = -{ - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME, - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME, - SL_SO_SECURE_FILES_CA_FILE_NAME, - SL_SO_SECURE_FILES_PEER_CERT_OR_DH_KEY_FILE_NAME, - SL_SO_SECMETHOD, - SL_SO_SECURE_MASK, - SL_SO_SECURE_ALPN, - SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP, - SL_SO_SECURE_DOMAIN_NAME_VERIFICATION, - SL_SO_SECURE_DISABLE_CERTIFICATE_STORE -}; - -static const int16_t socketType[8] = -{ - SL_SOCK_STREAM, - SL_SOCK_DGRAM, - SL_SOCK_RAW, - SLNETSOCK_SOCK_RX_MTR, - SL_SOCK_DGRAM, - SL_SOCK_RAW, - SLNETSOCK_SOCK_BRIDGE, - SLNETSOCK_SOCK_ROUTER, -}; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -//***************************************************************************** -// -// SlNetIfWifi_socket - Create an endpoint for communication -// -//***************************************************************************** -int16_t SlNetIfWifi_socket(void *ifContext, int16_t Domain, int16_t Type, int16_t Protocol, void **sdContext) -{ - /* Create socket and return the return value of the function */ - int16_t mappedSocketType = socketType[Type - 1]; - return (sl_Socket(Domain, mappedSocketType, Protocol)); -} - - -//***************************************************************************** -// -// SlNetIfWifi_close - Gracefully close socket -// -//***************************************************************************** -int32_t SlNetIfWifi_close(int16_t sd, void *sdContext) -{ - /* Close socket and return the return value of the function */ - return sl_Close(sd); -} - - -//***************************************************************************** -// -// SlNetIfWifi_accept - Accept a connection on a socket -// -//***************************************************************************** -int16_t SlNetIfWifi_accept(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext) -{ - return sl_Accept(sd, (SlSockAddr_t *)addr, addrlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_bind - Assign a name to a socket -// -//***************************************************************************** -int32_t SlNetIfWifi_bind(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen) -{ - return sl_Bind(sd, (const SlSockAddr_t *)addr, addrlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_listen - Listen for connections on a socket -// -//***************************************************************************** -int32_t SlNetIfWifi_listen(int16_t sd, void *sdContext, int16_t backlog) -{ - return sl_Listen(sd, backlog); -} - - -//***************************************************************************** -// -// SlNetIfWifi_connect - Initiate a connection on a socket -// -//***************************************************************************** -int32_t SlNetIfWifi_connect(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags) -{ - return sl_Connect(sd, (const SlSockAddr_t *)addr, addrlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_getSockName - Returns the local address info of the socket -// descriptor -// -//***************************************************************************** -int32_t SlNetIfWifi_getSockName(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen) -{ -// Not implemented in NWP - return SLNETERR_INVALPARAM; -} - - -//***************************************************************************** -// -// SlNetIfWifi_select - Monitor socket activity -// -//***************************************************************************** -int32_t SlNetIfWifi_select(void *ifContext, int16_t nfds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout) -{ - return sl_Select(nfds, (SlFdSet_t *)readsds, (SlFdSet_t *)writesds, (SlFdSet_t *)exceptsds, (struct SlTimeval_t *)timeout); -} - - -//***************************************************************************** -// -// SlNetIfWifi_setSockOpt - Set socket options -// -//***************************************************************************** -int32_t SlNetIfWifi_setSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen) -{ - return sl_SetSockOpt(sd, level, optname, optval, optlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_getSockOpt - Get socket options -// -//***************************************************************************** -int32_t SlNetIfWifi_getSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen) -{ - return sl_GetSockOpt(sd, level, optname, optval, optlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_recv - Read data from TCP socket -// -//***************************************************************************** -int32_t SlNetIfWifi_recv(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags) -{ - DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); - return sl_Recv(sd, buf, len, flags); -} - - -//***************************************************************************** -// -// SlNetIfWifi_recvFrom - Read data from socket -// -//***************************************************************************** -int32_t SlNetIfWifi_recvFrom(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen) -{ - DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); - return sl_RecvFrom(sd, buf, len, flags, (SlSockAddr_t *)from, fromlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_send - Write data to TCP socket -// -//***************************************************************************** -int32_t SlNetIfWifi_send(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags) -{ - DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); - return sl_Send(sd, buf, len, flags); -} - - -//***************************************************************************** -// -// SlNetIfWifi_sendTo - Write data to socket -// -//***************************************************************************** -int32_t SlNetIfWifi_sendTo(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen) -{ - DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); - return sl_SendTo(sd, buf, len, flags, (const SlSockAddr_t *)to, tolen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_sockstartSec - Start a security session on an opened socket -// -//***************************************************************************** -int32_t SlNetIfWifi_sockstartSec(int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags) -{ - SlNetSock_SecAttribNode_t *tempSecAttrib = *secAttrib; - int32_t retVal = SLNETERR_RET_CODE_OK; - - if ( 0 != (flags & SLNETSOCK_SEC_BIND_CONTEXT_ONLY) ) - { - /* run over all attributes and set them */ - while (NULL != tempSecAttrib) - { - if ( tempSecAttrib->attribName <= SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE) - { - retVal = sl_SetSockOpt(sd, SL_SOL_SOCKET, StartSecOptName[tempSecAttrib->attribName], tempSecAttrib->attribBuff, tempSecAttrib->attribBuffLen); - } - else - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - tempSecAttrib = tempSecAttrib->next; - } - } - - if ( 0 != (flags & SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY) ) - { - /* Start TLS session */ - retVal = sl_StartTLS(sd); - } - - return retVal; -} - - -//***************************************************************************** -// -// SlNetIfWifi_getHostByName - Obtain the IP Address of machine on network, by -// machine name -// -//***************************************************************************** -int32_t SlNetIfWifi_getHostByName(void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - - /* sl_NetAppDnsGetHostByName can receive only one ipAddr variable, so - only the first slot of the array will be used and the ipAddrLen will - be updated to 1 when function is successfully */ - retVal = sl_NetAppDnsGetHostByName((signed char *)name, nameLen, (_u32 *)ipAddr, family); - - if (retVal == SLNETERR_RET_CODE_OK) - { - *ipAddrLen = 1; - } - - return retVal; - - -} - - -//***************************************************************************** -// -// SlNetIfWifi_getIPAddr - Get IP Address of specific interface -// -//***************************************************************************** -int32_t SlNetIfWifi_getIPAddr(void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr) -{ - uint16_t ipAddrLen = sizeof(ipAddr); - return sl_NetCfgGet(addrType, addrConfig, &ipAddrLen, (unsigned char *)ipAddr); -} - - -//***************************************************************************** -// -// SlNetIfWifi_getConnectionStatus - Get interface connection status -// -//***************************************************************************** -int32_t SlNetIfWifi_getConnectionStatus(void *ifContext) -{ - SlWlanConnStatusParam_t connectionParams; - uint16_t Opt = 0; - int32_t retVal = 0; - uint16_t Size = 0; - - memset(&connectionParams, 0, sizeof(SlWlanConnStatusParam_t)); - - retVal = sl_WlanGet(SL_WLAN_CONNECTION_INFO, &Opt, &Size, (uint8_t *)&connectionParams); - - /* Check if the function returned an error */ - if (retVal < SLNETERR_RET_CODE_OK) - { - /* Return error code */ - return retVal; - } - return connectionParams.ConnStatus; -} - - -//***************************************************************************** -// -// SlNetIfWifi_loadSecObj - Load secured buffer to the network stack -// -//***************************************************************************** -int32_t SlNetIfWifi_loadSecObj(void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen) -{ - int32_t retVal; /* negative retVal is an error */ - char *deviceFileName = objName; - int32_t DeviceFileHandle = -1; - uint32_t Offset = 0; - uint32_t MasterToken = 0; - int32_t OpenFlags = 0; - uint8_t macAddress[SL_MAC_ADDR_LEN]; - uint16_t macAddressLen = SL_MAC_ADDR_LEN; - - /* Check if the inputs exists */ - if ( (NULL == objName) || (NULL == objBuff) ) - { - /* input not valid, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Print device Mac address */ - retVal = sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, &macAddress[0]); - - /* The masterToken is the Xor combination between the mac address of - the device and the object file name. */ - MasterToken = (uint32_t)deviceFileName ^ (uint32_t)macAddress; - - /* Create a file and write data. The file is secured, without - signature and with a fail safe commit, with vendor token which is - a Xor combination between the mac address of the device and the - object file name */ - OpenFlags = SL_FS_CREATE; - OpenFlags |= SL_FS_OVERWRITE; - OpenFlags |= SL_FS_CREATE_SECURE; - OpenFlags |= SL_FS_CREATE_VENDOR_TOKEN; - OpenFlags |= SL_FS_CREATE_NOSIGNATURE; - OpenFlags |= SL_FS_CREATE_FAILSAFE; - - /* Create a secure file if not exists and open it for write. */ - DeviceFileHandle = sl_FsOpen((unsigned char *)deviceFileName, OpenFlags | SL_FS_CREATE_MAX_SIZE( objBuffLen ), (unsigned long *)&MasterToken); - - /* Check if file created successfully */ - if ( DeviceFileHandle < SLNETERR_RET_CODE_OK ) - { - return DeviceFileHandle; - } - - Offset = 0; - /* Write the buffer to the new file */ - retVal = sl_FsWrite(DeviceFileHandle, Offset, (unsigned char *)objBuff, objBuffLen); - - /* Close the file */ - retVal = sl_FsClose(DeviceFileHandle, NULL, NULL , 0); - - return retVal; -} - -//***************************************************************************** -// -// SlNetIfWifi_CreateContext - Allocate and store interface data -// -//***************************************************************************** -int32_t SlNetIfWifi_CreateContext(uint16_t ifID, const char *ifName, void **context) -{ - return SLNETERR_RET_CODE_OK; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetifwifi.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetifwifi.h deleted file mode 100755 index 21b365a27f2..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetifwifi.h +++ /dev/null @@ -1,1230 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include -#include - -#ifndef __SLNETWIFI_SOCKET_H__ -#define __SLNETWIFI_SOCKET_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup WiFi Socket Stack - \short Controls standard client/server sockets programming options and capabilities - -*/ -/*! - - \addtogroup Socket - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* prototype ifConf */ -extern SlNetIf_Config_t SlNetIfConfigWifi; - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Create an endpoint for communication - - The SlNetIfWifi_socket function creates a new socket of a certain socket - type, identified by an integer number, and allocates system resources to - it.\n - This function is called by the application layer to obtain a socket descriptor (handle). - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - \param[in] domain Specifies the protocol family of the created socket. - For example: - - SLNETSOCK_AF_INET for network protocol IPv4 - - SLNETSOCK_AF_INET6 for network protocol IPv6 - - SLNETSOCK_AF_RF for starting transceiver mode. - Notes: - - sending and receiving any packet overriding 802.11 header - - for optimized power consumption the socket will be started in TX - only mode until receive command is activated - \param[in] type Specifies the socket type, which determines the semantics of communication over - the socket. The socket types supported by the system are implementation-dependent. - Possible socket types include: - - SLNETSOCK_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) - - SLNETSOCK_SOCK_DGRAM (datagram service or Datagram Sockets) - - SLNETSOCK_SOCK_RAW (raw protocols atop the network layer) - - when used with AF_RF: - - SLNETSOCK_SOCK_RX_MTR - - SLNETSOCK_SOCK_MAC_WITH_CCA - - SLNETSOCK_SOCK_MAC_WITH_NO_CCA - - SLNETSOCK_SOCK_BRIDGE - - SLNETSOCK_SOCK_ROUTER - \param[in] protocol Specifies a particular transport to be used with the socket.\n - The most common are - - SLNETSOCK_PROTO_TCP - - SLNETSOCK_PROTO_UDP - - SLNETSOCK_PROTO_RAW - - SLNETSOCK_PROTO_SECURE - The value 0 may be used to select a default - protocol from the selected domain and type - \param[in] sdContext Allocate and store socket data if needed for - using in other slnetwifi socket functions - - \return On success, socket descriptor (handle) that is used for consequent socket operations. \n - A successful return code should be a positive number (int16)\n - On error, a negative value will be returned specifying the error code. - - SLNETERR_BSD_EAFNOSUPPORT - illegal domain parameter - - SLNETERR_BSD_EPROTOTYPE - illegal type parameter - - SLNETERR_BSD_EACCES - permission denied - - SLNETERR_BSD_ENSOCK - exceeded maximal number of socket - - SLNETERR_BSD_ENOMEM - memory allocation error - - SLNETERR_BSD_EINVAL - error in socket configuration - - SLNETERR_BSD_EPROTONOSUPPORT - illegal protocol parameter - - SLNETERR_BSD_EOPNOTSUPP - illegal combination of protocol and type parameters - - \sa SlNetIfWifi_socket - \note - \warning -*/ -int16_t SlNetIfWifi_socket(void *ifContext, int16_t Domain, int16_t Type, int16_t Protocol, void **sdContext); - -/*! - \brief Gracefully close socket - - The SlNetIfWifi_close function causes the system to release resources allocated to a socket. \n - In case of TCP, the connection is terminated. - - \param[in] sd Socket descriptor (handle), received in SlNetIfWifi_socket - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_socket - \note - \warning -*/ -int32_t SlNetIfWifi_close(int16_t sd, void *sdContext); - -/*! - \brief Accept a connection on a socket - - The SlNetIfWifi_accept function is used with connection-based socket types (SOCK_STREAM).\n - It extracts the first connection request on the queue of pending - connections, creates a new connected socket, and returns a new file - descriptor referring to that socket.\n - The newly created socket is not in the listening state. The - original socket sd is unaffected by this call. \n - The argument sd is a socket that has been created with - SlNetIfWifi_socket(), bound to a local address with SlNetIfWifi_bind(), and is - listening for connections after a SlNetIfWifi_listen(). \n The argument - \e addr is a pointer to a sockaddr structure. This structure - is filled in with the address of the peer socket, as known to - the communications layer. \n The exact format of the address - returned addr is determined by the socket's address family. \n - The \b \e addrlen argument is a value-result argument: it - should initially contain the size of the structure pointed to - by addr, on return it will contain the actual length (in - bytes) of the address returned. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[out] addr The argument addr is a pointer - to a sockaddr structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - sockaddr:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - \param[in] flags Specifies socket descriptor flags. \n - The available flags are: - - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY - - SLNETSOCK_SEC_BIND_CONTEXT_ONLY - Note: This flags can be used in order to start - security session if needed - \param[in] acceptedSdContext Allocate and store data for the new socket - if needed in other to use it in other - slnetwifi socket functions - - \return On success, a socket descriptor.\n - On a non-blocking accept a possible negative value is SLNETERR_BSD_EAGAIN.\n - On failure, negative error code.\n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_Socket SlNetIfWifi_Bind SlNetIfWifi_Listen - \note - \warning -*/ -int16_t SlNetIfWifi_accept(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext); - -/*! - \brief Assign a name to a socket - - This SlNetIfWifi_bind function gives the socket the local address addr. - addr is addrlen bytes long. \n Traditionally, this is called - When a socket is created with socket, it exists in a name - space (address family) but has no name assigned. \n - It is necessary to assign a local address before a SOCK_STREAM - socket may receive connections. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] addr Specifies the destination - addrs\n sockaddr:\n - code for - the address format.\n - socket address, - the length depends on the code - format - \param[in] addrlen Contains the size of the structure pointed to by addr - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_Socket SlNetIfWifi_accept SlNetIfWifi_Listen - \note - \warning -*/ -int32_t SlNetIfWifi_bind(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen); - -/*! - \brief Listen for connections on a socket - - The willingness to accept incoming connections and a queue - limit for incoming connections are specified with SlNetIfWifi_listen(), - and then the connections are accepted with SlNetIfWifi_accept(). \n - The SlNetIfWifi_listen() call applies only to sockets of type SOCK_STREAM - The backlog parameter defines the maximum length the queue of - pending connections may grow to. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] backlog Specifies the listen queue depth. - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_Socket SlNetIfWifi_accept SlNetIfWifi_bind - \note - \warning -*/ -int32_t SlNetIfWifi_listen(int16_t sd, void *sdContext, int16_t backlog); - -/*! - \brief Initiate a connection on a socket - - Function connects the socket referred to by the socket - descriptor sd, to the address specified by addr. \n The addrlen - argument specifies the size of addr. \n The format of the - address in addr is determined by the address space of the - socket. \n If it is of type SLNETSOCK_SOCK_DGRAM, this call - specifies the peer with which the socket is to be associated; - this address is that to which datagrams are to be sent, and - the only address from which datagrams are to be received. \n If - the socket is of type SLNETSOCK_SOCK_STREAM, this call - attempts to make a connection to another socket. \n The other - socket is specified by address, which is an address in the - communications space of the socket. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] addr Specifies the destination addr\n - sockaddr:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[in] addrlen Contains the size of the structure pointed - to by addr - \param[in] flags Specifies socket descriptor flags. \n - The available flags are: - - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY - - SLNETSOCK_SEC_BIND_CONTEXT_ONLY - Note: This flags can be used in order to start - security session if needed - - \return On success, a socket descriptor (handle).\n - On a non-blocking connect a possible negative value is NETSCOK_EALREADY. - On failure, negative value.\n - NETSCOK_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_socket - \note - \warning -*/ -int32_t SlNetIfWifi_connect(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags); - -/*! - \brief Get local address info by socket descriptor\n - Returns the local address info of the socket descriptor. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[out] addr The argument addr is a pointer - to a SlNetSock_Addr_t structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - SlNetSock_Addr_t:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - - \return Zero on success, or negative on failure.\n - - - \sa SlNetSock_create SlNetSock_bind - \note If the provided buffer is too small the returned address will be - truncated and the addrlen will contain the actual size of the - socket address - \warning -*/ -int32_t SlNetIfWifi_getSockName(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); - -/*! - \brief Monitor socket activity - - SlNetIfWifi_send allow a program to monitor multiple file descriptors, - waiting until one or more of the file descriptors become - "ready" for some class of I/O operation. - If trigger mode is enabled the active sdset is the one that retrieved in the first triggered call. - To enable the trigger mode, an handler must be statically registered to the slcb_SocketTriggerEventHandler (user.h) - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - \param[in] nsds The highest-numbered file descriptor in any of the - three sets, plus 1. - \param[in,out] readsds Socket descriptors list for read monitoring and accept monitoring - \param[in,out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported - \param[in,out] exceptsds Socket descriptors list for exception monitoring, not supported. - \param[in] timeout Is an upper bound on the amount of time elapsed - before SlNetIfWifi_send() returns. Null or above 0xffff seconds means - infinity timeout. The minimum timeout is 10 milliseconds, - less than 10 milliseconds will be set automatically to 10 milliseconds. - Max microseconds supported is 0xfffc00. - In trigger mode the timeout fields must be set to zero. - - \return On success, SlNetIfWifi_send() returns the number of - file descriptors contained in the three returned - descriptor sets (that is, the total number of bits that - are set in readsds, writesds, exceptsds) which may be - zero if the timeout expires before anything interesting - happens.\n On error, a negative value is returned. - readsds - return the sockets on which Read request will - return without delay with valid data.\n - writesds - return the sockets on which Write request - will return without delay.\n - exceptsds - return the sockets closed recently. \n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_socket - \note If the timeout value set to less than 10ms it will automatically set - to 10ms to prevent overload of the system\n - - Only one SlNetIfWifi_send can be handled at a time. \b - Calling this API while the same command is called from another thread, may result - in one of the following scenarios: - 1. The command will wait (internal) until the previous command finish, and then be executed. - 2. There are not enough resources and SLNETERR_BSD_ENOMEM error will return. - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - 3. In case there is already a triggered SlNetIfWifi_send in progress, the following call will return - with SLNETSOCK_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR. - - \warning -*/ -int32_t SlNetIfWifi_select(void *ifContext, int16_t nfds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); - - -/*! - \brief Set socket options- - - The SlNetIfWifi_setSockOpt function manipulate the options associated with a socket.\n - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level.\n - - When manipulating socket options the level at which the option resides - and the name of the option must be specified. To manipulate options at - the socket level, level is specified as SOL_SOCKET. To manipulate - options at any other level the protocol number of the appropriate protocol - controlling the option is supplied. For example, to indicate that an - option is to be interpreted by the TCP protocol, level should be set to - the protocol number of TCP; \n - - The parameters optval and optlen are used to access opt_values - for SlNetIfWifi_setSockOpt(). For SlNetIfWifi_getSockOpt() they identify a - buffer in which the value for the requested option(s) are to - be returned. For SlNetIfWifi_getSockOpt(), optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, option_value may be - NULL. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] level Defines the protocol level for this option - - SLNETSOCK_LVL_SOCKET Socket level configurations (L4, transport layer) - - SLNETSOCK_LVL_IP IP level configurations (L3, network layer) - - SLNETSOCK_LVL_PHY Link level configurations (L2, link layer) - \param[in] optname Defines the option name to interrogate - - SLNETSOCK_LVL_SOCKET - - SLNETSOCK_OPSOCK_RCV_BUF \n - Sets tcp max recv window size. \n - This options takes SlNetSock_Winsize_t struct as parameter - - SLNETSOCK_OPSOCK_RCV_TIMEO \n - Sets the timeout value that specifies the maximum amount of time an input function waits until it completes. \n - Default: No timeout \n - This options takes SlNetSock_Timeval_t struct as parameter - - SLNETSOCK_OPSOCK_KEEPALIVE \n - Enable or Disable periodic keep alive. - Keeps TCP connections active by enabling the periodic transmission of messages \n - Timeout is 5 minutes.\n - Default: Enabled \n - This options takes SlNetSock_Keepalive_t struct as parameter - - SLNETSOCK_OPSOCK_KEEPALIVE_TIME \n - Set keep alive timeout. - Value is in seconds \n - Default: 5 minutes \n - - SLNETSOCK_OPSOCK_LINGER \n - Socket lingers on close pending remaining send/receive packets\n - - SLNETSOCK_OPSOCK_NON_BLOCKING \n - Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n - Default: Blocking. - This options takes SlNetSock_Nonblocking_t struct as parameter - - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY \n - Enable or Disable rx ip boundary. - In connectionless socket (udp/raw), unread data is dropped (when SlNetIfWifi_recvfrom len parameter < data size), Enable this option in order to read the left data on the next SlNetIfWifi_recvfrom iteration - Default: Disabled, IP boundary kept, \n - This options takes SlNetSock_NonIpBoundary_t struct as parameter - - SLNETSOCK_LVL_IP - - SLNETSOCK_OPIP_MULTICAST_TTL \n - Set the time-to-live value of outgoing multicast packets for this socket. \n - This options takes uint8_t as parameter - - SLNETSOCK_OPIP_ADD_MEMBERSHIP \n - UDP socket, Join a multicast group. \n - This options takes SlNetSock_IpMreq_t struct as parameter - - SLNETSOCK_OPIP_DROP_MEMBERSHIP \n - UDP socket, Leave a multicast group \n - This options takes SlNetSock_IpMreq_t struct as parameter - - SLNETSOCK_OPIP_HDRINCL \n - RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. \n - When it is enabled, the packet must contain an IP header. \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes uint32_t as parameter - - SLNETSOCK_OPIP_RAW_RX_NO_HEADER \n - Raw socket remove IP header from received data. \n - Default: data includes ip header \n - This options takes uint32_t as parameter - - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (inactive) \n - RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes uint32_t as parameter - - SLNETSOCK_LVL_PHY - - SLNETSOCK_OPPHY_CHANNEL \n - Sets channel in transceiver mode. - This options takes uint32_t as channel number parameter - - SLNETSOCK_OPPHY_RATE \n - RAW socket, set WLAN PHY transmit rate \n - The values are based on SlWlanRateIndex_e \n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_TX_POWER \n - RAW socket, set WLAN PHY TX power \n - Valid rage is 1-15 \n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX \n - RAW socket, set number of frames to transmit in transceiver mode. - Default: 1 packet - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_PREAMBLE \n - RAW socket, set WLAN PHY preamble for Long/Short\n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD \n - RAW socket, set WLAN Tx - Set CCA threshold. \n - The values are based on SlNetSockTxInhibitThreshold_e \n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_TX_TIMEOUT \n - RAW socket, set WLAN Tx - changes the TX timeout (lifetime) of transceiver frames. \n - Value in Ms, maximum value is 10ms \n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_ALLOW_ACKS \n - RAW socket, set WLAN Tx - Enable or Disable sending ACKs in transceiver mode \n - 0 = disabled / 1 = enabled \n - This options takes uint32_t as parameter - - - \param[in] optval Specifies a value for the option - \param[in] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - - \par Persistent - All params are Non- Persistent - \sa SlNetIfWifi_getSockOpt - \note - \warning - \par Examples - - - SLNETSOCK_OPSOCK_RCV_BUF: - \code - SlNetSock_Winsize_t size; - size.winsize = 3000; // bytes - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_BUF, (uint8_t *)&size, sizeof(size)); - \endcode -
- - - SLNETSOCK_OPSOCK_RCV_TIMEO: - \code - struct SlNetSock_Timeval_t timeVal; - timeVal.tv_sec = 1; // Seconds - timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_TIMEO, (uint8_t *)&timeVal, sizeof(timeVal)); // Enable receive timeout - \endcode -
- - - SLNETSOCK_OPSOCK_KEEPALIVE: //disable Keepalive - \code - SlNetSock_Keepalive_t enableOption; - enableOption.keepaliveEnabled = 0; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_KEEPALIVE_TIME: //Set Keepalive timeout - \code - int16_t Status; - uint32_t TimeOut = 120; - SlNetIfWifi_setSockOpt(Sd, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE_TIME, (uint8_t *)&TimeOut, sizeof(TimeOut)); - \endcode -
- - - SLNETSOCK_OPSOCK_NON_BLOCKING: //Enable or disable nonblocking mode - \code - SlNetSock_Nonblocking_t enableOption; - enableOption.nonBlockingEnabled = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_BLOCKING, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY: //disable boundary - \code - SlNetSock_NonIpBoundary_t enableOption; - enableOption.nonIpBoundaryEnabled = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_IP_BOUNDARY, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_LINGER: - \code - SlNetSock_linger_t linger; - linger.l_onoff = 1; - linger.l_linger = 10; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_LINGER, &linger, sizeof(linger)); - \endcode -
- - - SLNETSOCK_OPIP_MULTICAST_TTL: - \code - uint8_t ttl = 20; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_MULTICAST_TTL, &ttl, sizeof(ttl)); - \endcode -
- - - SLNETSOCK_OPIP_ADD_MEMBERSHIP: - \code - SlNetSock_IpMreq_t mreq; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SLNETSOCK_OPIP_DROP_MEMBERSHIP: - \code - SlNetSock_IpMreq_t mreq; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SLNETSOCK_OPIP_RAW_RX_NO_HEADER: - \code - uint32_t header = 1; // remove ip header - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_RX_NO_HEADER, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPIP_HDRINCL: - \code - uint32_t header = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL: - \code - uint32_t header = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_IPV6_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPPHY_CHANNEL: - \code - uint32_t newChannel = 6; // range is 1-13 - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPPHY_CHANNEL, &newChannel, sizeof(newChannel)); - \endcode -
- - - SLNETSOCK_OPPHY_RATE: - \code - uint32_t rate = 6; // see wlan.h SlWlanRateIndex_e for values - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_RATE, &rate, sizeof(rate)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_POWER: - \code - uint32_t txpower = 1; // valid range is 1-15 - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_POWER, &txpower, sizeof(txpower)); - \endcode -
- - - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX: - \code - uint32_t numframes = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); - \endcode -
- - - SLNETSOCK_OPPHY_PREAMBLE: - \code - uint32_t preamble = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_PREAMBLE, &preamble, sizeof(preamble)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD: - \code - uint32_t thrshld = SLNETSOCK_TX_INHIBIT_THRESHOLD_MED; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD , &thrshld, sizeof(thrshld)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_TIMEOUT: - \code - uint32_t timeout = 50; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_TIMEOUT , &timeout, sizeof(timeout)); - \endcode -
- - - SLNETSOCK_OPPHY_ALLOW_ACKS: - \code - uint32_t acks = 1; // 0 = disabled / 1 = enabled - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_ALLOW_ACKS, &acks, sizeof(acks)); - \endcode -
- -*/ -int32_t SlNetIfWifi_setSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); - -/*! - \brief Get socket options - - The SlNetIfWifi_getSockOpt function gets the options associated with a socket. - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level.\n - - The parameters optval and optlen identify a - buffer in which the value for the requested option(s) are to - be returned. optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, option_value may be - NULL. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] level Defines the protocol level for this option - \param[in] optname defines the option name to interrogate - \param[out] optval Specifies a value for the option - \param[out] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - \sa SlNetIfWifi_setSockOpt - \note - \warning -*/ -int32_t SlNetIfWifi_getSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); - -/*! - \brief Read data from TCP socket - - The SlNetIfWifi_recv function receives a message from a connection-mode socket - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[out] buf Points to the buffer where the - message should be stored. - \param[in] len Specifies the length in bytes of - the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Upper 8 bits specifies the security flags - Lower 24 bits specifies the type of message - reception. On this version, the lower 24 bits are not - supported - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SLNETERR_BSD_EAGAIN.\n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_recvFrom - \note - \warning - \par Examples - - - Receiving data using TCP socket: - \code - SlNetSock_AddrIn_t Addr; - SlNetSock_AddrIn_t LocalAddr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID, newSockID; - int16_t Status; - int8_t Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_port = SlNetSock_htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); - Status = SlNetIfWifi_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); - Status = SlNetIfWifi_listen(SockID, 0); - newSockID = SlNetIfWifi_accept(SockID, (SlNetSock_Addr_t*)&Addr, (SlNetSocklen_t*) &AddrSize); - Status = SlNetIfWifi_recv(newSockID, Buf, 1460, 0); - \endcode -
- - - Rx transceiver mode using a raw socket: - \code - int8_t buffer[1536]; - int16_t sd; - uint16_t size; - SlNetSock_TransceiverRxOverHead_t *transHeader; - sd = SlNetIfWifi_socket(SLNETSOCK_AF_RF, SLNETSOCK_SOCK_RAW, 11, 0, 0); // channel 11 - while(1) - { - size = SlNetIfWifi_recv(sd,buffer,1536,0); - transHeader = (SlNetSock_TransceiverRxOverHead_t *)buffer; - printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlNetSock_TransceiverRxOverHead_t)],size); - } - \endcode -*/ -int32_t SlNetIfWifi_recv(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags); - -/*! - \brief Read data from socket - - SlNetIfWifi_recvFrom function receives a message from a connection-mode or - connectionless-mode socket - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[out] buf Points to the buffer where the message should be stored. - \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Upper 8 bits specifies the security flags - Lower 24 bits specifies the type of message - reception. On this version, the lower 24 bits are not - supported - \param[in] from Pointer to an address structure - indicating the source - address.\n sockaddr:\n - code - for the address format.\n - socket address, - the length depends on the code - format - \param[in] fromlen Source address structure - size. This parameter MUST be set to the size of the structure pointed to by addr. - - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SLNETERR_BSD_EAGAIN. - SLNETSOCK_RET_CODE_INVALID_INPUT (-2) will be returned if fromlen has incorrect length. \n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_recv - \note - \warning - \par Example - - - Receiving data: - \code - SlNetSock_AddrIn_t Addr; - SlNetSock_AddrIn_t LocalAddr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_port = SlNetSock_htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); - Status = SlNetIfWifi_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); - Status = SlNetIfWifi_recvFrom(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, (SlNetSocklen_t*)&AddrSize); - - \endcode -*/ -int32_t SlNetIfWifi_recvFrom(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); - -/*! - \brief Write data to TCP socket - - The SlNetIfWifi_send function is used to transmit a message to another socket. - Returns immediately after sending data to device. - In case of TCP failure an async event SLNETSOCK_SOCKET_TX_FAILED_EVENT is going to - be received.\n - In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the - frame data buffer for WLAN FCS - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len Message size in bytes. Range: 1-1460 bytes - \param[in] flags Upper 8 bits specifies the security flags - Lower 24 bits specifies the type of message - reception. On this version, the lower 24 bits are not - supported for TCP. - For transceiver mode, the SLNETSOCK_WLAN_RAW_RF_TX_PARAMS macro can be used to determine - transmission parameters (channel,rate,tx_power,preamble) - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_sendTo - \note - \warning - \par Example - - - Sending data: - \code - SlNetSock_AddrIn_t Addr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[SEND_BUF_LEN]; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); - Status = SlNetIfWifi_connect(SockID, (SlNetSock_Addr_t *)&Addr, AddrSize); - Status = SlNetIfWifi_send(SockID, Buf, 1460, 0 ); - \endcode -*/ -int32_t SlNetIfWifi_send(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags); - -/*! - \brief Write data to socket - - The SlNetIfWifi_sendTo function is used to transmit a message on a connectionless socket - (connection less socket SLNETSOCK_SOCK_DGRAM, SLNETSOCK_SOCK_RAW).\n - Returns immediately after sending data to device.\n - In case of transmission failure an async event SLNETSOCK_SOCKET_TX_FAILED_EVENT is going to - be received. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len message size in bytes. Range: 1-1460 bytes - \param[in] flags Upper 8 bits specifies the security flags - Lower 24 bits specifies the type of message - reception. On this version, the lower 24 bits are not - supported - \param[in] to Pointer to an address structure - indicating the destination - address.\n sockaddr:\n - code - for the address format.\n - socket address, - the length depends on the code - format - \param[in] tolen Destination address structure size - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_send - \note - \warning - \par Example - - - Sending data: - \code - SlNetSock_AddrIn_t Addr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[SEND_BUF_LEN]; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); - Status = SlNetIfWifi_sendTo(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, AddrSize); - \endcode -*/ -int32_t SlNetIfWifi_sendTo(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); - - -/*! - \brief Start a security session on an opened socket - - The SlNetIfWifi_sockstartSec function is used start a security session on - an opened socket. If the security handle is NULL the session would - be started with the default security settings. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] secAttrib Secure attribute handle - \param[in] flags Specifies flags. \n - The available flags are: - - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY - - SLNETSOCK_SEC_BIND_CONTEXT_ONLY - - SLNETSOCK_SEC_IS_SERVER - - \return Zero on success, or negative error code - on failure - - \sa - \note - \warning - \par Example - - - start security session on an opened socket: - \code - - \endcode -*/ -int32_t SlNetIfWifi_sockstartSec(int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); - - -/*! - \brief Get host IP by name\n - Obtain the IP Address of machine on network, by machine name. - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - \param[in] ifBitmap Specifies the interfaces which the host ip - needs to be retrieved from (according to - the priority until one of them will return - an answer).\n - The values of the interface identifiers - is defined with the prefix SLNETIF_ID_ - which defined in slnetif.h - \param[in] name Host name - \param[in] nameLen Name length - \param[out] ipAddr This parameter is filled in with - host IP addresses. In case that host name is not - resolved, out_ip_addr is zero. - \param[in,out] ipAddrLen Holds the size of the ipAddr array, when function - successful, the ipAddrLen parameter will be updated with - the number of the IP addresses found. - \param[in] family Protocol family - - \return Zero on success, or negative on failure.\n - SLNETUTIL_POOL_IS_EMPTY may be return in case - there are no resources in the system\n - In this case try again later or increase - MAX_CONCURRENT_ACTIONS - Possible DNS error codes: - - SLNETUTIL_DNS_QUERY_NO_RESPONSE - - SLNETUTIL_DNS_NO_SERVER - - SLNETUTIL_DNS_QUERY_FAILED - - SLNETUTIL_DNS_MALFORMED_PACKET - - SLNETUTIL_DNS_MISMATCHED_RESPONSE - - \sa - \note Only one sl_NetAppDnsGetHostByName can be handled at a time.\n - Calling this API while the same command is called from another - thread, may result in one of the two scenarios: - 1. The command will wait (internal) until the previous command - finish, and then be executed. - 2. There are not enough resources and POOL_IS_EMPTY error will - return.\n - In this case, MAX_CONCURRENT_ACTIONS can be increased (result - in memory increase) or try again later to issue the command. - \warning - In case an IP address in a string format is set as input, without - any prefix (e.g. "1.2.3.4") the device will not try to access the - DNS and it will return the input address on the 'out_ip_addr' field - \par Example - - Getting host by name: - \code - uint16_t DestIPListSize = 1; - uint32_t DestIP[1]; - uint32_t ifID; - int16_t SockId; - SlNetSock_AddrIn_t LocalAddr; //address of the server to connect to - int32_t LocalAddrSize; - - SlNetIfWifi_getHostByName(0, "www.google.com", strlen("www.google.com"), (uint32_t *)DestIP, &DestIPListSize, SLNETSOCK_PF_INET); - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_addr.s_addr = SlNetUtil_htonl(DestIP[0]); - LocalAddr.sin_port = SlNetUtil_htons(80); - LocalAddrSize = sizeof(SlNetSock_AddrIn_t); - - SockId = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, ifID, 0); - - if (SockId >= 0) - { - status = SlNetIfWifi_connect(SockId, (SlNetSock_Addr_t *) &LocalAddr, LocalAddrSize); - } - \endcode -*/ -int32_t SlNetIfWifi_getHostByName(void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); - - -/*! - \brief Get IP Address of specific interface - - The SlNetIfWifi_getIPAddr function retrieve the IP address of a specific - interface according to the Address Type, IPv4, IPv6 LOCAL - or IPv6 GLOBAL.\n - - \n - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - \param[in] ifID Specifies the interface which its connection - state needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - \param[in] addrType Address type: - - SLNETIF_IPV4_ADDR - - SLNETIF_IPV6_ADDR_LOCAL - - SLNETIF_IPV6_ADDR_GLOBAL - \param[out] addrConfig Address config: - - SLNETIF_ADDR_CFG_UNKNOWN - - SLNETIF_ADDR_CFG_DHCP - - SLNETIF_ADDR_CFG_DHCP_LLA - - SLNETIF_ADDR_CFG_STATIC - - SLNETIF_ADDR_CFG_STATELESS - - SLNETIF_ADDR_CFG_STATEFUL - \param[out] ipAddr IP Address according to the Address Type - - \return Zero on success, or negative error code on failure - - \sa SlNetIfAddressType_e - \note - \warning - \par Examples - - \code - SlNetSock_In6Addr_t IPAdd; - uint16_t addressConfig = 0; - SlNetIfWifi_getIPAddr(SLNETIF_ID_1 ,SLNETIF_IPV6_ADDR_LOCAL ,&addressConfig ,(uint8_t *)ipAddr); - \endcode -
-*/ -int32_t SlNetIfWifi_getIPAddr(void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); - - -/*! - \brief Get interface connection status - - The SlNetIfWifi_getConnectionStatus function gets the connection status of the - interface (connected Or disconnected).\n - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - - \return Connection status of the interface on success, - or negative error code on failure - - \sa - \note - \warning - \par Examples - - \code - int16_t connection_status - connection_status = SlNetIfWifi_getConnectionStatus(); - \endcode -
-*/ -int32_t SlNetIfWifi_getConnectionStatus(void *ifContext); - - -/*! - \brief Load secured buffer to the network stack - - The SlNetSock_secLoadObj function loads buffer/files into the inputted - network stack for future usage of the socket SSL/TLS connection. - This option is relevant for network stacks with file system and also for - network stacks that lack file system that can store the secured files. - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - \param[in] objType Specifies the security object type which - could be one of the following:\n - - SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY - - SLNETIF_SEC_OBJ_TYPE_CERTIFICATE - - SLNETIF_SEC_OBJ_TYPE_DH_KEY - \param[in] objName Specifies the name/input identifier of the - secured buffer loaded - for file systems - this can be the file name - for plain text buffer loading this can be the - name of the object - \param[in] objNameLen Specifies the buffer name length to be loaded.\n - \param[in] objBuff Specifies the pointer to the secured buffer to - be loaded.\n - \param[in] objBuffLen Specifies the buffer length to be loaded.\n - - \return On success, buffer type handler index to be - used when attaching the secured buffer to a - socket.\n - A successful return code should be a positive - number (int16)\n - On error, a negative value will be returned - specifying the error code. - - SLNETERR_STATUS_ERROR - load operation failed - - \sa SlNetIfWifi_setSockOpt - \note - \warning -*/ -int32_t SlNetIfWifi_loadSecObj(void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen); - - -/*! - \brief Allocate and store interface data - - The SlNetIfWifi_CreateContext function stores interface related data.\n - - \param[in] ifContext Allocate and store interface data if needed. - Can be used in all slnetwifi interface functions - - \return Zero on success, or negative error code on failure. - - \sa - \note - \warning - \par Examples - - \code - void *ifContext; - connection_status = SlNetIfWifi_CreateContext(&context); - \endcode -
-*/ -int32_t SlNetIfWifi_CreateContext(uint16_t ifID, const char *ifName, void **ifContext); - - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SOCKET_H__ */ - - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/device.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/device.c deleted file mode 100755 index 423ab5d0a80..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/device.c +++ /dev/null @@ -1,782 +0,0 @@ -/* - * device.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include - -/*****************************************************************************/ -/* Internal functions */ -/*****************************************************************************/ - -static _i16 _SlDeviceGetStartResponseConvert(_i32 Status); -void _SlDeviceHandleResetRequestInternally(void); -void _SlDeviceResetRequestInitCompletedCB(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo); - -#ifdef SL_PLATFORM_MULTI_THREADED -extern void wait_us(int usec); -#endif - -#define RESET_REQUEST_STOP_TIMEOUT (300) - -#ifndef SL_IF_OPEN_FLAGS -#define SL_IF_OPEN_FLAGS (0x0) -#endif - -#ifndef SL_IF_UART_REOPEN_FLAGS -#define SL_IF_UART_REOPEN_FLAGS (0x1) -#endif - -typedef struct -{ - const void *pIfHdl; /* Holds the last opened interface handle */ - _i8 *pDevName; /* Holds the last opened interface parameters */ - _u32 ResetRequestSessionNumber; /* Special session number to be verified upon every reset request during provisioning */ -} _SlDeviceCb_t; - -_SlDeviceCb_t DeviceCB; /* the device control block */ - -static const _i16 StartResponseLUT[16] = -{ - ROLE_RESERVED, - ROLE_STA, - SL_ERROR_ROLE_STA_ERR, - ROLE_AP, - SL_ERROR_ROLE_AP_ERR, - ROLE_P2P, - SL_ERROR_ROLE_P2P_ERR, - SL_ERROR_CALIB_FAIL, - SL_ERROR_FS_CORRUPTED_ERR, - SL_ERROR_FS_ALERT_ERR, - SL_ERROR_RESTORE_IMAGE_COMPLETE, - SL_ERROR_INCOMPLETE_PROGRAMMING, - ROLE_RESERVED2, - SL_ERROR_GENERAL_ERR, - SL_ERROR_GENERAL_ERR, - SL_ERROR_GENERAL_ERR -}; - -static _i16 _SlDeviceGetStartResponseConvert(_i32 Status) -{ - return StartResponseLUT[Status & 0xF]; -} - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* sl_Task */ -/*****************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_Task) -void* sl_Task(void* pEntry) -{ -#ifdef _SlTaskEntry - return (void*)_SlTaskEntry(); -#else - return (void*)0; -#endif -} -#endif - -/*****************************************************************************/ -/* sl_Start */ -/*****************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_Start) -_i16 sl_Start(const void* pIfHdl, _i8* pDevName, const P_INIT_CALLBACK pInitCallBack) -{ - _u8 ObjIdx = MAX_CONCURRENT_ACTIONS; - InitComplete_t AsyncRsp; - - _SlDrvMemZero(&AsyncRsp, sizeof(InitComplete_t)); - - /* verify no error handling in progress. if in progress than - ignore the API execution and return immediately with an error */ - VERIFY_NO_ERROR_HANDLING_IN_PROGRESS(); - if (SL_IS_DEVICE_STARTED) - { - return SL_RET_CODE_DEV_ALREADY_STARTED; - } - /* Perform any preprocessing before enable networking services */ -#ifdef sl_DeviceEnablePreamble - sl_DeviceEnablePreamble(); -#endif - - /* ControlBlock init */ - (void)_SlDrvDriverCBInit(); - - /* open the interface: usually SPI or UART */ - if (NULL == pIfHdl) - { - g_pCB->FD = sl_IfOpen((void *)pDevName, SL_IF_OPEN_FLAGS); - } - else - { - g_pCB->FD = (_SlFd_t)pIfHdl; - } - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8 *)&AsyncRsp, START_STOP_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - if( g_pCB->FD >= (_SlFd_t)0) - { - /* store the interface parameters for the internal call of the - sl_start to be called upon reset request handling */ - DeviceCB.pIfHdl = pIfHdl; - DeviceCB.pDevName = pDevName; - - /* Mark that device is in progress! */ - SL_SET_DEVICE_START_IN_PROGRESS; - - sl_DeviceDisable(); - - sl_IfRegIntHdlr((SL_P_EVENT_HANDLER)_SlDrvRxIrqHandler, NULL); - - g_pCB->pInitCallback = pInitCallBack; - sl_DeviceEnable(); - - if (NULL == pInitCallBack) - { -#ifdef SL_TINY - _SlDrvSyncObjWaitForever(&g_pCB->ObjPool[ObjIdx].SyncObj); -#else - - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, INIT_COMPLETE_TIMEOUT, SL_OPCODE_DEVICE_INITCOMPLETE)); -#endif - - SL_UNSET_DEVICE_START_IN_PROGRESS; - - SL_SET_DEVICE_STARTED; - - /* release Pool Object */ - _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex); - return _SlDeviceGetStartResponseConvert(AsyncRsp.Status); - } - else - { - return SL_RET_CODE_OK; - } - } - return SL_BAD_INTERFACE; -} -#endif - -/*************************************************************************** -_SlDeviceHandleAsync_InitComplete - handles init complete signalling to -a waiting object -****************************************************************************/ -_SlReturnVal_t _SlDeviceHandleAsync_InitComplete(void *pVoidBuf) -{ - InitComplete_t *pMsgArgs = (InitComplete_t *)_SL_RESP_ARGS_START(pVoidBuf); - SlDeviceInitInfo_t DeviceInitInfo; - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - if(g_pCB->pInitCallback) - { - DeviceInitInfo.ChipId = pMsgArgs->ChipId; - DeviceInitInfo.MoreData = pMsgArgs->MoreData; - g_pCB->pInitCallback(_SlDeviceGetStartResponseConvert(pMsgArgs->Status), &DeviceInitInfo); - } - else - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(InitComplete_t)); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - if(g_pCB->pInitCallback) - { - SL_SET_DEVICE_STARTED; - SL_UNSET_DEVICE_START_IN_PROGRESS; - _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex); - } - - return SL_OS_RET_CODE_OK; - } - - -/*************************************************************************** -_SlDeviceHandleAsync_Stop - handles stop signalling to -a waiting object -****************************************************************************/ -void _SlDeviceHandleAsync_Stop(void *pVoidBuf) -{ - _BasicResponse_t *pMsgArgs = (_BasicResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - VERIFY_SOCKET_CB(NULL != g_pCB->StopCB.pAsyncRsp); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - if (g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs != NULL) - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(_BasicResponse_t)); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return; -} - - -/***************************************************************************** -sl_stop -******************************************************************************/ -typedef union -{ - SlDeviceStopCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlStopMsg_u; - -static const _SlCmdCtrl_t _SlStopCmdCtrl = -{ - SL_OPCODE_DEVICE_STOP_COMMAND, - (_SlArgSize_t)sizeof(SlDeviceStopCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -#if _SL_INCLUDE_FUNC(sl_Stop) -_i16 sl_Stop(const _u16 Timeout) -{ - _i16 RetVal=0; - _SlStopMsg_u Msg; - _BasicResponse_t AsyncRsp; - _u8 ObjIdx = MAX_CONCURRENT_ACTIONS; - _u8 ReleasePoolObject = FALSE; - _u8 IsProvInProgress = FALSE; - - /* In case the device has already stopped, - * return an error code . - */ - if (!SL_IS_DEVICE_STARTED) - { - return SL_RET_CODE_DEV_NOT_STARTED; - } - - /* NOTE: don't check VERIFY_API_ALLOWED(), this command is not - * filtered in error handling and also not filtered in NWP lock state. - * If we are in the middle of assert handling than ignore stopping - * the device with timeout and force immediate shutdown as we would like - * to avoid any additional commands to the NWP */ - if( (Timeout != 0) -#ifndef SL_TINY - && (!SL_IS_RESTART_REQUIRED) -#endif - ) - { - /* Clear the Async response structure */ - _SlDrvMemZero(&AsyncRsp, sizeof(_BasicResponse_t)); - - /* let the device make the shutdown using the defined timeout */ - Msg.Cmd.Timeout = Timeout; - - IsProvInProgress = SL_IS_PROVISIONING_IN_PROGRESS; - - /* if provisioning in progress do not take pool object as we are not going to wait for it */ - if (!IsProvInProgress) - { - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8 *)&AsyncRsp, START_STOP_ID, SL_MAX_SOCKETS); - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - ReleasePoolObject = TRUE; - } - - /* Set the stop-in-progress flag */ - SL_SET_DEVICE_STOP_IN_PROGRESS; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlStopCmdCtrl, &Msg, NULL)); - - /* Do not wait for stop async event if provisioning is in progress */ - if((SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) && (!(IsProvInProgress))) - { - -#ifdef SL_TINY - _SlDrvSyncObjWaitForever(&g_pCB->ObjPool[ObjIdx].SyncObj); - /* Wait for sync object to be signaled */ -#else - - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, STOP_DEVICE_TIMEOUT, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE)); -#endif - Msg.Rsp.status = AsyncRsp.status; - RetVal = Msg.Rsp.status; - } - - /* Release pool object only if taken */ - if (ReleasePoolObject == TRUE) - { - _SlDrvReleasePoolObj(ObjIdx); - } - - /* This macro wait for the NWP to raise a ready for shutdown indication. - * This function is unique for the CC32XX family, and expected to return - * in less than 600 mSec, which is the time takes for NWP to gracefully shutdown. */ - WAIT_NWP_SHUTDOWN_READY; - } - else - { - /* Set the stop-in-progress flag */ - SL_SET_DEVICE_STOP_IN_PROGRESS; - } - /* Release (signal) all active and pending commands */ - _SlDrvReleaseAllActivePendingPoolObj(); - -#ifdef SL_PLATFORM_MULTI_THREADED - /* Do not continue until all sync object deleted (in relevant context) */ - while (g_pCB->NumOfDeletedSyncObj < MAX_CONCURRENT_ACTIONS) - { - wait_us(100000); - } -#endif - sl_IfRegIntHdlr(NULL, NULL); - sl_DeviceDisable(); - RetVal = sl_IfClose(g_pCB->FD); - - (void)_SlDrvDriverCBDeinit(); - - /* clear the stop-in-progress flag */ - SL_UNSET_DEVICE_STOP_IN_PROGRESS; - - /* clear the device started flag */ - SL_UNSET_DEVICE_STARTED; - - return RetVal; -} -#endif - - -/***************************************************************************** -sl_DeviceEventMaskSet -*****************************************************************************/ -typedef union -{ - SlDeviceMaskEventSetCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlEventMaskSetMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskSet) - -static const _SlCmdCtrl_t _SlEventMaskSetCmdCtrl = -{ - SL_OPCODE_DEVICE_EVENTMASKSET, - (_SlArgSize_t)sizeof(SlDeviceMaskEventSetCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - - -_i16 sl_DeviceEventMaskSet(const _u8 EventClass ,const _u32 Mask) -{ - _SlEventMaskSetMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); - - Msg.Cmd.Group = EventClass; - Msg.Cmd.Mask = Mask; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlEventMaskSetCmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/****************************************************************************** -sl_EventMaskGet -******************************************************************************/ -typedef union -{ - SlDeviceMaskEventGetCommand_t Cmd; - SlDeviceMaskEventGetResponse_t Rsp; -}_SlEventMaskGetMsg_u; - - - -#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskGet) - -static const _SlCmdCtrl_t _SlEventMaskGetCmdCtrl = -{ - SL_OPCODE_DEVICE_EVENTMASKGET, - (_SlArgSize_t)sizeof(SlDeviceMaskEventGetCommand_t), - (_SlArgSize_t)sizeof(SlDeviceMaskEventGetResponse_t) -}; - - -_i16 sl_DeviceEventMaskGet(const _u8 EventClass,_u32 *pMask) -{ - _SlEventMaskGetMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); - - Msg.Cmd.Group = EventClass; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlEventMaskGetCmdCtrl, &Msg, NULL)); - - *pMask = Msg.Rsp.Mask; - - return SL_RET_CODE_OK; -} -#endif - - - -/****************************************************************************** -sl_DeviceGet -******************************************************************************/ - -typedef union -{ - SlDeviceSetGet_t Cmd; - SlDeviceSetGet_t Rsp; -}_SlDeviceMsgGet_u; - - - -#if _SL_INCLUDE_FUNC(sl_DeviceGet) - -static const _SlCmdCtrl_t _SlDeviceGetCmdCtrl = -{ - SL_OPCODE_DEVICE_DEVICEGET, - (_SlArgSize_t)sizeof(SlDeviceSetGet_t), - (_SlArgSize_t)sizeof(SlDeviceSetGet_t) -}; - -_i16 sl_DeviceGet(const _u8 DeviceGetId, _u8 *pOption,_u16 *pConfigLen, _u8 *pValues) -{ - _SlDeviceMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); - - if (*pConfigLen == 0) - { - return SL_EZEROLEN; - } - - if( pOption ) - { - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)*pConfigLen; - CmdExt.pRxPayload = (_u8 *)pValues; - - Msg.Cmd.DeviceSetId = DeviceGetId; - - Msg.Cmd.Option = (_u16)*pOption; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlDeviceGetCmdCtrl, &Msg, &CmdExt)); - - if( pOption ) - { - *pOption = (_u8)Msg.Rsp.Option; - } - - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pConfigLen = (_u16)CmdExt.RxPayloadLen; - - return SL_ESMALLBUF; - } - else - { - *pConfigLen = (_u16)CmdExt.ActualRxPayloadLen; - } - - return (_i16)Msg.Rsp.Status; - } - else - { - return SL_RET_CODE_INVALID_INPUT; - } -} -#endif - -/****************************************************************************** -sl_DeviceSet -******************************************************************************/ -typedef union -{ - SlDeviceSetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlDeviceMsgSet_u; - - - -#if _SL_INCLUDE_FUNC(sl_DeviceSet) - -static const _SlCmdCtrl_t _SlDeviceSetCmdCtrl = -{ - SL_OPCODE_DEVICE_DEVICESET, - (_SlArgSize_t)sizeof(SlDeviceSetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_DeviceSet(const _u8 DeviceSetId ,const _u8 Option,const _u16 ConfigLen,const _u8 *pValues) -{ - _SlDeviceMsgSet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); - - _SlDrvResetCmdExt(&CmdExt); - - CmdExt.TxPayload1Len = (ConfigLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *)pValues; - - Msg.Cmd.DeviceSetId = DeviceSetId; - Msg.Cmd.ConfigLen = ConfigLen; - Msg.Cmd.Option = Option; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlDeviceSetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/****************************************************************************** -_SlDeviceEventHandler - handles internally device async events -******************************************************************************/ -_SlReturnVal_t _SlDeviceEventHandler(void* pEventInfo) -{ - DeviceEventInfo_t* pInfo = (DeviceEventInfo_t*)pEventInfo; - _SlResponseHeader_t* pHdr = (_SlResponseHeader_t *)pInfo->pAsyncMsgBuff; - _BasicResponse_t *pMsgArgs = (_BasicResponse_t *)_SL_RESP_ARGS_START(pHdr); - SlDeviceEvent_t DeviceEvent; - - _SlDrvMemZero(&DeviceEvent, sizeof(DeviceEvent)); - - switch(pHdr->GenHeader.Opcode) - { - case SL_OPCODE_DEVICE_INITCOMPLETE: - _SlDeviceHandleAsync_InitComplete(pHdr); - break; - case SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE: - _SlDeviceHandleAsync_Stop(pHdr); - break; - case SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT: - { - SlDeviceResetRequestData_t *pResetRequestData = (SlDeviceResetRequestData_t*)pMsgArgs; - -#if defined(slcb_DeviceGeneralEvtHdlr) || defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) - if (pResetRequestData->Caller == SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING_EXTERNAL_CONFIGURATION) - { - /* call the registered events handlers (application/external lib) */ - DeviceEvent.Id = SL_DEVICE_EVENT_RESET_REQUEST; - DeviceEvent.Data.ResetRequest.Status = 0; - DeviceEvent.Data.ResetRequest.Caller = pResetRequestData->Caller; - _SlDrvHandleGeneralEvents(&DeviceEvent); - break; - } -#endif - - if (!_SlDrvIsApiInProgress() && SL_IS_PROVISIONING_IN_PROGRESS) - { - if (pResetRequestData->SessionNumber != DeviceCB.ResetRequestSessionNumber) - { - /* store the last session number */ - DeviceCB.ResetRequestSessionNumber = pResetRequestData->SessionNumber; - - /* perform the reset request */ - _SlDeviceHandleResetRequestInternally(); - } - } - } - break; - - case SL_OPCODE_DEVICE_ABORT: - { - /* release global lock of cmd context */ - if (pInfo->bInCmdContext == TRUE) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - -#ifndef SL_TINY - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_DEVICE_ABORT, - *((_u32*)pMsgArgs - 1), /* Abort type */ - *((_u32*)pMsgArgs)); /* Abort data */ -#endif - } - break; - - case SL_OPCODE_DEVICE_DEVICE_ASYNC_GENERAL_ERROR: - { -#if defined(slcb_DeviceGeneralEvtHdlr) || defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) - - DeviceEvent.Id = SL_DEVICE_EVENT_ERROR; - DeviceEvent.Data.Error.Code = pMsgArgs->status; - DeviceEvent.Data.Error.Source = (SlDeviceSource_e)pMsgArgs->sender; - _SlDrvHandleGeneralEvents(&DeviceEvent); -#endif - } - break; - - case SL_OPCODE_DEVICE_FLOW_CTRL_ASYNC_EVENT: - _SlFlowContSet((void *)pHdr); - break; - default: - SL_ERROR_TRACE2(MSG_306, "ASSERT: _SlDeviceEventHandler : invalid opcode = 0x%x = %1", pHdr->GenHeader.Opcode, pHdr->GenHeader.Opcode); - } - - return SL_OS_RET_CODE_OK; -} - - -void _SlDeviceResetRequestInitCompletedCB(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo) -{ - /* Do nothing...*/ -} - - -void _SlDeviceHandleResetRequestInternally(void) -{ - _u8 irqCountLast = RxIrqCnt; -#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) - _SlTimeoutParams_t TimeoutInfo={0}; - - _SlDrvStartMeasureTimeout(&TimeoutInfo, 2*RESET_REQUEST_STOP_TIMEOUT); -#endif - - /* Here we send stop command with timeout, but the API will not blocked - Till the stop complete event is received as we in the middle of async event handling */ - sl_Stop(RESET_REQUEST_STOP_TIMEOUT); - - /* wait till the stop complete cmd & async - event messages are received (2 Irqs) */ - do - { -#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) - if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) - { - break; - } -#endif - } - while((RxIrqCnt - irqCountLast) < 2); - - /* start the device again */ - sl_Start(DeviceCB.pIfHdl, DeviceCB.pDevName ,_SlDeviceResetRequestInitCompletedCB); - -} - - -/****************************************************************************** -sl_DeviceUartSetMode -******************************************************************************/ -#ifdef SL_IF_TYPE_UART -typedef union -{ - SlDeviceUartSetModeCommand_t Cmd; - SlDeviceUartSetModeResponse_t Rsp; -}_SlUartSetModeMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_DeviceUartSetMode) - - -const _SlCmdCtrl_t _SlUartSetModeCmdCtrl = -{ - SL_OPCODE_DEVICE_SETUARTMODECOMMAND, - (_SlArgSize_t)sizeof(SlDeviceUartSetModeCommand_t), - (_SlArgSize_t)sizeof(SlDeviceUartSetModeResponse_t) -}; - -_i16 sl_DeviceUartSetMode(const SlDeviceUartIfParams_t *pUartParams) -{ - _SlUartSetModeMsg_u Msg; - _u32 magicCode = (_u32)0xFFFFFFFF; - - Msg.Cmd.BaudRate = pUartParams->BaudRate; - Msg.Cmd.FlowControlEnable = pUartParams->FlowControlEnable; - - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlUartSetModeCmdCtrl, &Msg, NULL)); - - /* cmd response OK, we can continue with the handshake */ - if (SL_RET_CODE_OK == Msg.Rsp.status) - { - sl_IfMaskIntHdlr(); - - /* Close the comm port */ - sl_IfClose(g_pCB->FD); - - /* Re-open the comm port */ - sl_IfOpen((void * )pUartParams, SL_IF_UART_REOPEN_FLAGS); - - sl_IfUnMaskIntHdlr(); - - /* send the magic code and wait for the response */ - sl_IfWrite(g_pCB->FD, (_u8* )&magicCode, 4); - - magicCode = UART_SET_MODE_MAGIC_CODE; - sl_IfWrite(g_pCB->FD, (_u8* )&magicCode, 4); - - /* clear magic code */ - magicCode = 0; - - /* wait (blocking) till the magic code to be returned from device */ - sl_IfRead(g_pCB->FD, (_u8* )&magicCode, 4); - - /* check for the received magic code matching */ - if (UART_SET_MODE_MAGIC_CODE != magicCode) - { - _SL_ASSERT(0); - } - } - - return (_i16)Msg.Rsp.status; -} -#endif -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.c deleted file mode 100755 index 0c0313720a0..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.c +++ /dev/null @@ -1,3269 +0,0 @@ -/* - * driver.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#ifndef SL_PLATFORM_MULTI_THREADED - -#define GLOBAL_LOCK_CONTEXT_OWNER_APP (1) -#define GLOBAL_LOCK_CONTEXT_OWNER_SPAWN (2) - -_u8 gGlobalLockContextOwner = GLOBAL_LOCK_CONTEXT_OWNER_APP; - -#endif - -_u8 gGlobalLockCntRequested=0; -_u8 gGlobalLockCntReleased=0; - -#if defined(SL_PLATFORM_MULTI_THREADED) -extern void * pthread_self(void); -#endif -/* static functions declaration */ -static void _SlDrvUpdateApiInProgress(_i8 Value); - -#define API_IN_PROGRESS_UPDATE_NONE (0) -#define API_IN_PROGRESS_UPDATE_INCREMENT (1) -#define API_IN_PROGRESS_UPDATE_DECREMENT (-1) - -#define GLOBAL_LOCK_FLAGS_NONE (0x0) -#define GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS (0x1) /* Bit 0 */ -#define GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API (0x2) /* Bit 1*/ -#define GLOBAL_LOCK_FLAGS_STARTING_DEVICE (0x4) /* Bit 2 */ - - -/* 2 LSB of the N2H_SYNC_PATTERN are for sequence number -only in SPI interface -support backward sync pattern */ -#define N2H_SYNC_PATTERN_SEQ_NUM_BITS ((_u32)0x00000003) /* Bits 0..1 - use the 2 LBS for seq num */ -#define N2H_SYNC_PATTERN_SEQ_NUM_EXISTS ((_u32)0x00000004) /* Bit 2 - sign that sequence number exists in the sync pattern */ -#define N2H_SYNC_PATTERN_MASK ((_u32)0xFFFFFFF8) /* Bits 3..31 - constant SYNC PATTERN */ -#define N2H_SYNC_SPI_BUGS_MASK ((_u32)0x7FFF7F7F) /* Bits 7,15,31 - ignore the SPI (8,16,32 bites bus) error bits */ -#define BUF_SYNC_SPIM(pBuf) ((*(_u32 *)(pBuf)) & N2H_SYNC_SPI_BUGS_MASK) - -#define N2H_SYNC_SPIM (N2H_SYNC_PATTERN & N2H_SYNC_SPI_BUGS_MASK) -#define N2H_SYNC_SPIM_WITH_SEQ(TxSeqNum) ((N2H_SYNC_SPIM & N2H_SYNC_PATTERN_MASK) | N2H_SYNC_PATTERN_SEQ_NUM_EXISTS | ((TxSeqNum) & (N2H_SYNC_PATTERN_SEQ_NUM_BITS))) -#define MATCH_WOUT_SEQ_NUM(pBuf) ( BUF_SYNC_SPIM(pBuf) == N2H_SYNC_SPIM ) -#define MATCH_WITH_SEQ_NUM(pBuf, TxSeqNum) ( BUF_SYNC_SPIM(pBuf) == (N2H_SYNC_SPIM_WITH_SEQ(TxSeqNum)) ) -#define N2H_SYNC_PATTERN_MATCH(pBuf, TxSeqNum) \ - ( \ - ( (*((_u32 *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && ( MATCH_WITH_SEQ_NUM(pBuf, TxSeqNum) ) ) || \ - ( !(*((_u32 *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && ( MATCH_WOUT_SEQ_NUM(pBuf ) ) ) \ - ) - -#define OPCODE(_ptr) (((_SlResponseHeader_t *)(_ptr))->GenHeader.Opcode) -#define RSP_PAYLOAD_LEN(_ptr) (((_SlResponseHeader_t *)(_ptr))->GenHeader.Len - _SL_RESP_SPEC_HDR_SIZE) -#define SD(_ptr) (((SlSocketAddrResponse_u *)(_ptr))->IpV4.Sd) -/* Actual size of Recv/Recvfrom response data */ -#define ACT_DATA_SIZE(_ptr) (((SlSocketAddrResponse_u *)(_ptr))->IpV4.StatusOrLen) - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) -#define MULTI_SELECT_MASK (~(1 << SELECT_ID)) -#else -#define MULTI_SELECT_MASK (0xFFFFFFFF) -#endif -/* Internal function prototype declaration */ - - -/* General Events handling*/ -#if defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) - -typedef _SlEventPropogationStatus_e (*general_callback) (SlDeviceEvent_t *); - -static const general_callback general_callbacks[] = -{ -#ifdef SlExtLib1GeneralEventHandler - SlExtLib1GeneralEventHandler, -#endif - -#ifdef SlExtLib2GeneralEventHandler - SlExtLib2GeneralEventHandler, -#endif - -#ifdef SlExtLib3GeneralEventHandler - SlExtLib3GeneralEventHandler, -#endif - -#ifdef SlExtLib4GeneralEventHandler - SlExtLib4GeneralEventHandler, -#endif - -#ifdef SlExtLib5GeneralEventHandler - SlExtLib5GeneralEventHandler, -#endif -}; - -#undef _SlDrvHandleGeneralEvents - -/******************************************************************** - _SlDrvHandleGeneralEvents - Iterates through all the general(device) event handlers which are - registered by the external libs/user application. -*********************************************************************/ -void _SlDrvHandleGeneralEvents(SlDeviceEvent_t *slGeneralEvent) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(general_callbacks)/sizeof(general_callbacks[0]) ; i++ ) - { - if (EVENT_PROPAGATION_BLOCK == general_callbacks[i](slGeneralEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_DeviceGeneralEvtHdlr - slcb_DeviceGeneralEvtHdlr(slGeneralEvent); -#endif - -} -#endif - - -/* WLAN Events handling*/ - -#if defined (EXT_LIB_REGISTERED_WLAN_EVENTS) - -typedef _SlEventPropogationStatus_e (*wlan_callback) (SlWlanEvent_t *); - -static wlan_callback wlan_callbacks[] = -{ -#ifdef SlExtLib1WlanEventHandler - SlExtLib1WlanEventHandler, -#endif - -#ifdef SlExtLib2WlanEventHandler - SlExtLib2WlanEventHandler, -#endif - -#ifdef SlExtLib3WlanEventHandler - SlExtLib3WlanEventHandler, -#endif - -#ifdef SlExtLib4WlanEventHandler - SlExtLib4WlanEventHandler, -#endif - -#ifdef SlExtLib5WlanEventHandler - SlExtLib5WlanEventHandler, -#endif -}; - -#undef _SlDrvHandleWlanEvents - -/*********************************************************** - _SlDrvHandleWlanEvents - Iterates through all the wlan event handlers which are - registered by the external libs/user application. -************************************************************/ -void _SlDrvHandleWlanEvents(SlWlanEvent_t *slWlanEvent) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(wlan_callbacks)/sizeof(wlan_callbacks[0]) ; i++ ) - { - if ( EVENT_PROPAGATION_BLOCK == wlan_callbacks[i](slWlanEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_WlanEvtHdlr - slcb_WlanEvtHdlr(slWlanEvent); -#endif - -} -#endif - - -/* NetApp Events handling */ -#if defined (EXT_LIB_REGISTERED_NETAPP_EVENTS) - -typedef _SlEventPropogationStatus_e (*netApp_callback) (SlNetAppEvent_t *); - -static const netApp_callback netApp_callbacks[] = -{ -#ifdef SlExtLib1NetAppEventHandler - SlExtLib1NetAppEventHandler, -#endif - -#ifdef SlExtLib2NetAppEventHandler - SlExtLib2NetAppEventHandler, -#endif - -#ifdef SlExtLib3NetAppEventHandler - SlExtLib3NetAppEventHandler, -#endif - -#ifdef SlExtLib4NetAppEventHandler - SlExtLib4NetAppEventHandler, -#endif - -#ifdef SlExtLib5NetAppEventHandler - SlExtLib5NetAppEventHandler, -#endif -}; - -#undef _SlDrvHandleNetAppEvents - -/************************************************************ - _SlDrvHandleNetAppEvents - Iterates through all the net app event handlers which are - registered by the external libs/user application. -************************************************************/ -void _SlDrvHandleNetAppEvents(SlNetAppEvent_t *slNetAppEvent) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(netApp_callbacks)/sizeof(netApp_callbacks[0]) ; i++ ) - { - if (EVENT_PROPAGATION_BLOCK == netApp_callbacks[i](slNetAppEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_NetAppEvtHdlr - slcb_NetAppEvtHdlr(slNetAppEvent); -#endif - -} -#endif - - -/* Http Server Events handling */ -#if defined (EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) - -typedef _SlEventPropogationStatus_e (*httpServer_callback) (SlNetAppHttpServerEvent_t*, SlNetAppHttpServerResponse_t*); - -static const httpServer_callback httpServer_callbacks[] = -{ -#ifdef SlExtLib1HttpServerEventHandler - SlExtLib1HttpServerEventHandler, -#endif - -#ifdef SlExtLib2HttpServerEventHandler - SlExtLib2HttpServerEventHandler, -#endif - -#ifdef SlExtLib3HttpServerEventHandler - SlExtLib3HttpServerEventHandler, -#endif - -#ifdef SlExtLib4HttpServerEventHandler - SlExtLib4HttpServerEventHandler, -#endif - -#ifdef SlExtLib5HttpServerEventHandler - SlExtLib5HttpServerEventHandler, -#endif -}; - -#undef _SlDrvHandleHttpServerEvents - -/******************************************************************* - _SlDrvHandleHttpServerEvents - Iterates through all the http server event handlers which are - registered by the external libs/user application. -********************************************************************/ -void _SlDrvHandleHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse) -{ - _u8 i; - - /* Iterate over all the external libs handlers */ - for ( i = 0 ; i < sizeof(httpServer_callbacks)/sizeof(httpServer_callbacks[0]) ; i++ ) - { - if ( EVENT_PROPAGATION_BLOCK == httpServer_callbacks[i](slHttpServerEvent, slHttpServerResponse) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_NetAppHttpServerHdlr - slcb_NetAppHttpServerHdlr(slHttpServerEvent, slHttpServerResponse); -#endif - -} -#endif - - -/* Socket Events */ -#if defined (EXT_LIB_REGISTERED_SOCK_EVENTS) - -typedef _SlEventPropogationStatus_e (*sock_callback) (SlSockEvent_t *); - -static const sock_callback sock_callbacks[] = -{ -#ifdef SlExtLib1SockEventHandler - SlExtLib1SockEventHandler, -#endif - -#ifdef SlExtLib2SockEventHandler - SlExtLib2SockEventHandler, -#endif - -#ifdef SlExtLib3SockEventHandler - SlExtLib3SockEventHandler, -#endif - -#ifdef SlExtLib4SockEventHandler - SlExtLib4SockEventHandler, -#endif - -#ifdef SlExtLib5SockEventHandler - SlExtLib5SockEventHandler, -#endif -}; - -/************************************************************* - _SlDrvHandleSockEvents - Iterates through all the socket event handlers which are - registered by the external libs/user application. -**************************************************************/ -void _SlDrvHandleSockEvents(SlSockEvent_t *slSockEvent) -{ - _u8 i; - - /* Iterate over all the external libs handlers */ - for ( i = 0 ; i < sizeof(sock_callbacks)/sizeof(sock_callbacks[0]) ; i++ ) - { - if ( EVENT_PROPAGATION_BLOCK == sock_callbacks[i](slSockEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_SockEvtHdlr - slcb_SockEvtHdlr(slSockEvent); -#endif - -} - -#endif - -/* Fatal Error Events handling*/ -#if defined (EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) - -typedef _SlEventPropogationStatus_e (*fatal_error_callback) (SlDeviceEvent_t *); - -static const fatal_error_callback fatal_error_callbacks[] = -{ -#ifdef SlExtLib1FatalErrorEventHandler - SlExtLib1FatalErrorEventHandler, -#endif - -#ifdef SlExtLib2FatalErrorEventHandler - SlExtLib2FatalErrorEventHandler, -#endif - -#ifdef SlExtLib3FatalErrorEventHandler - SlExtLib3FatalErrorEventHandler, -#endif - -#ifdef SlExtLib4FatalErrorEventHandler - SlExtLib4FatalErrorEventHandler, -#endif - -#ifdef SlExtLib5FatalErrorEventHandler - SlExtLib5FatalErrorEventHandler, -#endif -}; - -#undef _SlDrvHandleFatalErrorEvents - -/******************************************************************** - _SlDrvHandleFatalErrorEvents - Iterates through all the fatal error (device) event handlers which are - registered by the external libs/user application. -*********************************************************************/ -void _SlDrvHandleFatalErrorEvents(SlDeviceFatal_t *slFatalErrorEvent) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(fatal_error_callbacks)/sizeof(fatal_error_callbacks[0]) ; i++ ) - { - if (EVENT_PROPAGATION_BLOCK == fatal_error_callbacks[i](slFatalErrorEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_DeviceFatalErrorEvtHdlr - slcb_DeviceFatalErrorEvtHdlr(slFatalErrorEvent); -#endif - -} -#endif - -/* NetApp request handler */ -#if defined (EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) - -typedef _SlEventPropogationStatus_e (*netapp_request_callback) (SlNetAppRequest_t*, SlNetAppResponse_t*); - -static const netapp_request_callback netapp_request_callbacks[] = -{ -#ifdef SlExtLib1NetAppRequestEventHandler - SlExtLib1NetAppRequestEventHandler, -#endif - -#ifdef SlExtLib2NetAppRequestEventHandler - SlExtLib2NetAppRequestEventHandler, -#endif - -#ifdef SlExtLib3NetAppRequestEventHandler - SlExtLib3NetAppRequestEventHandler, -#endif - -#ifdef SlExtLib4NetAppRequestEventHandler - SlExtLib4NetAppRequestEventHandler, -#endif - -#ifdef SlExtLib5NetAppRequestEventHandler - SlExtLib5NetAppRequestEventHandler, -#endif -}; - -#undef _SlDrvHandleNetAppRequestEvents - -/******************************************************************** - _SlDrvHandleNetAppRequest - Iterates through all the netapp request handlers which are - registered by the external libs/user application. -*********************************************************************/ -void _SlDrvHandleNetAppRequestEvents(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(netapp_request_callbacks)/sizeof(netapp_request_callbacks[0]) ; i++ ) - { - if (EVENT_PROPAGATION_BLOCK == netapp_request_callbacks[i](pNetAppRequest, pNetAppResponse) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_NetAppRequestHdlr - slcb_NetAppRequestHdlr(pNetAppRequest, pNetAppResponse); -#endif - -} -#endif - - -#ifndef SL_MEMORY_MGMT_DYNAMIC -typedef struct -{ - _u32 Align; -#ifdef SL_PLATFORM_MULTI_THREADED - _SlAsyncRespBuf_t AsyncBufPool[SL_MAX_ASYNC_BUFFERS]; -#endif - _u8 AsyncRespBuf[SL_ASYNC_MAX_MSG_LEN]; -}_SlStatMem_t; - -static _SlStatMem_t g_StatMem; -#endif - - -/*****************************************************************************/ -/* Variables */ -/*****************************************************************************/ -_SlDriverCb_t g_CB; -static const _SlSyncPattern_t g_H2NSyncPattern = H2N_SYNC_PATTERN; - -#ifndef SL_IF_TYPE_UART -static const _SlSyncPattern_t g_H2NCnysPattern = H2N_CNYS_PATTERN; -#endif -_volatile _u8 RxIrqCnt; - -_u16 g_SlDeviceStatus = 0; -_SlLockObj_t GlobalLockObj; -_u8 g_IsGlobalLockObjInit = 0; - - -#ifndef SL_TINY - - -const _SlActionLookup_t _SlActionLookupTable[] = -{ - {ACCEPT_ID, SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE, (_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Accept}, - {CONNECT_ID, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Connect}, - {SELECT_ID, SL_OPCODE_SOCKET_SELECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Select}, - {GETHOSYBYNAME_ID, SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_DnsGetHostByName}, - {GETHOSYBYSERVICE_ID, SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_DnsGetHostByService}, - {PING_ID, SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE, (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_PingResponse}, - {NETAPP_RECEIVE_ID, SL_OPCODE_NETAPP_RECEIVE, (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_NetAppReceive}, - {START_STOP_ID, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE,(_SlSpawnEntryFunc_t)_SlDeviceHandleAsync_Stop}, - {NETUTIL_CMD_ID, SL_OPCODE_NETUTIL_COMMANDASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetUtilHandleAsync_Cmd}, - {CLOSE_ID, SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Close}, - {START_TLS_ID, SL_OPCODE_SOCKET_SOCKETASYNCEVENT,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_StartTLS} -}; -#else -const _SlActionLookup_t _SlActionLookupTable[] = -{ - {CONNECT_ID, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Connect}, - {GETHOSYBYNAME_ID, SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_DnsGetHostByName}, - {START_STOP_ID, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE,(_SlSpawnEntryFunc_t)_SlDeviceHandleAsync_Stop}, - {CLOSE_ID, SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Close} -}; -#endif - - - -typedef struct -{ - _u16 opcode; - _u8 event; -} OpcodeKeyVal_t; - - -/* The table translates opcode to user's event type */ -const OpcodeKeyVal_t OpcodeTranslateTable[] = -{ - {SL_OPCODE_WLAN_STA_ASYNCCONNECTEDRESPONSE, SL_WLAN_EVENT_CONNECT}, - {SL_OPCODE_WLAN_P2PCL_ASYNCCONNECTEDRESPONSE, SL_WLAN_EVENT_P2P_CONNECT}, - {SL_OPCODE_WLAN_STA_ASYNCDISCONNECTEDRESPONSE, SL_WLAN_EVENT_DISCONNECT}, - {SL_OPCODE_WLAN_P2PCL_ASYNCDISCONNECTEDRESPONSE,SL_WLAN_EVENT_P2P_DISCONNECT}, - {SL_OPCODE_WLAN_ASYNC_STA_ADDED, SL_WLAN_EVENT_STA_ADDED}, - {SL_OPCODE_WLAN_ASYNC_P2PCL_ADDED,SL_WLAN_EVENT_P2P_CLIENT_ADDED}, - {SL_OPCODE_WLAN_ASYNC_STA_REMOVED, SL_WLAN_EVENT_STA_REMOVED}, - {SL_OPCODE_WLAN_ASYNC_P2PCL_REMOVED,SL_WLAN_EVENT_P2P_CLIENT_REMOVED}, - {SL_OPCODE_WLAN_P2P_DEV_FOUND,SL_WLAN_EVENT_P2P_DEVFOUND}, - {SL_OPCODE_WLAN_P2P_NEG_REQ_RECEIVED, SL_WLAN_EVENT_P2P_REQUEST}, - {SL_OPCODE_WLAN_P2P_CONNECTION_FAILED, SL_WLAN_EVENT_P2P_CONNECTFAIL}, - {SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT, SL_WLAN_EVENT_PROVISIONING_STATUS}, - {SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE, SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED}, - {SL_OPCODE_WLAN_RX_FILTER_ASYNC_RESPONSE,SL_WLAN_EVENT_RXFILTER}, - {SL_OPCODE_WLAN_RESERVED_RESPONSE, SL_WLAN_EVENT_RESERVED}, - - {SL_OPCODE_NETAPP_IPACQUIRED, SL_NETAPP_EVENT_IPV4_ACQUIRED}, - {SL_OPCODE_NETAPP_IPACQUIRED_V6, SL_NETAPP_EVENT_IPV6_ACQUIRED}, - {SL_OPCODE_NETAPP_IP_LEASED, SL_NETAPP_EVENT_DHCPV4_LEASED}, - {SL_OPCODE_NETAPP_IP_RELEASED, SL_NETAPP_EVENT_DHCPV4_RELEASED}, - {SL_OPCODE_NETAPP_IP_COLLISION, SL_NETAPP_EVENT_IP_COLLISION}, - {SL_OPCODE_NETAPP_IPV4_LOST, SL_NETAPP_EVENT_IPV4_LOST}, - {SL_OPCODE_NETAPP_DHCP_IPV4_ACQUIRE_TIMEOUT, SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT}, - {SL_OPCODE_NETAPP_IPV6_LOST_V6, SL_NETAPP_EVENT_IPV6_LOST}, - {SL_OPCODE_NETAPP_RESERVED1, SL_NETAPP_EVENT_RESERVED1}, - {SL_OPCODE_NETAPP_RESERVED2, SL_NETAPP_EVENT_RESERVED2}, - {SL_OPCODE_NETAPP_RESERVED3, SL_NETAPP_EVENT_RESERVED3}, - {SL_OPCODE_SOCKET_TXFAILEDASYNCRESPONSE, SL_SOCKET_TX_FAILED_EVENT}, - {SL_OPCODE_SOCKET_SOCKETASYNCEVENT, SL_SOCKET_ASYNC_EVENT} - -}; - - - -_SlDriverCb_t* g_pCB = NULL; -P_SL_DEV_PING_CALLBACK pPingCallBackFunc = NULL; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ -static _SlReturnVal_t _SlDrvMsgRead(_u16* outMsgReadLen, _u8** pAsyncBuf); -static _SlReturnVal_t _SlDrvMsgWrite(_SlCmdCtrl_t *pCmdCtrl,_SlCmdExt_t *pCmdExt, _u8 *pTxRxDescBuff); -static _SlReturnVal_t _SlDrvMsgReadCmdCtx(_u16 cmdOpcode, _u8 IsLockRequired); -static _SlReturnVal_t _SlDrvClassifyRxMsg(_SlOpcode_t Opcode ); -static _SlReturnVal_t _SlDrvRxHdrRead(_u8 *pBuf); -static void _SlDrvAsyncEventGenericHandler(_u8 bInCmdContext, _u8 *pAsyncBuffer); -static void _SlDrvRemoveFromList(_u8* ListIndex, _u8 ItemIndex); -static _SlReturnVal_t _SlDrvFindAndSetActiveObj(_SlOpcode_t Opcode, _u8 Sd); -static _SlReturnVal_t _SlDrvObjGlobalLockWaitForever(_u32 Flags); - -/*****************************************************************************/ -/* Internal functions */ -/*****************************************************************************/ - - -/***************************************************************************** -_SlDrvDriverCBInit - init Driver Control Block -*****************************************************************************/ - -_SlReturnVal_t _SlDrvDriverCBInit(void) -{ - _u8 Idx =0; - - g_pCB = &g_CB; - -#ifndef SL_PLATFORM_MULTI_THREADED - { - extern _SlNonOsCB_t g__SlNonOsCB; - sl_Memset(&g__SlNonOsCB, 0, sizeof(g__SlNonOsCB)); - } -#endif - - _SlDrvMemZero(g_pCB, (_u16)sizeof(_SlDriverCb_t)); - RxIrqCnt = 0; - OSI_RET_OK_CHECK( sl_SyncObjCreate(&g_pCB->CmdSyncObj, "CmdSyncObj") ); - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->CmdSyncObj); - - if (g_IsGlobalLockObjInit == 0) - { - OSI_RET_OK_CHECK( sl_LockObjCreate(&GlobalLockObj, "GlobalLockObj") ); - g_IsGlobalLockObjInit = 1; - } - - OSI_RET_OK_CHECK( sl_LockObjCreate(&g_pCB->ProtectionLockObj, "ProtectionLockObj") ); - g_pCB->NumOfDeletedSyncObj = 0; -#if defined(slcb_SocketTriggerEventHandler) - g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = MAX_CONCURRENT_ACTIONS; -#endif - /* Init Drv object */ - _SlDrvMemZero(&g_pCB->ObjPool[0], (_u16)(MAX_CONCURRENT_ACTIONS*sizeof(_SlPoolObj_t))); - /* place all Obj in the free list*/ - g_pCB->FreePoolIdx = 0; - - for (Idx = 0 ; Idx < MAX_CONCURRENT_ACTIONS ; Idx++) - { - g_pCB->ObjPool[Idx].NextIndex = Idx + 1; - g_pCB->ObjPool[Idx].AdditionalData = SL_MAX_SOCKETS; - - OSI_RET_OK_CHECK( sl_SyncObjCreate(&g_pCB->ObjPool[Idx].SyncObj, "SyncObj")); - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->ObjPool[Idx].SyncObj); - } - - g_pCB->ActivePoolIdx = MAX_CONCURRENT_ACTIONS; - g_pCB->PendingPoolIdx = MAX_CONCURRENT_ACTIONS; - -#ifdef SL_PLATFORM_MULTI_THREADED - -#ifdef SL_MEMORY_MGMT_DYNAMIC - /* reset the spawn messages list */ - g_pCB->spawnMsgList = NULL; -#else - for (Idx = 0; Idx < SL_MAX_ASYNC_BUFFERS; Idx++) - { - g_StatMem.AsyncBufPool[Idx].ActionIndex = 0xFF; - g_StatMem.AsyncBufPool[Idx].AsyncHndlr = NULL; - } -#endif -#else - /* clear the global lock owner */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); -#endif - /* Flow control init */ - g_pCB->FlowContCB.TxPoolCnt = FLOW_CONT_MIN; - OSI_RET_OK_CHECK(sl_LockObjCreate(&g_pCB->FlowContCB.TxLockObj, "TxLockObj")); - OSI_RET_OK_CHECK(sl_SyncObjCreate(&g_pCB->FlowContCB.TxSyncObj, "TxSyncObj")); - g_pCB->FlowContCB.MinTxPayloadSize = 1536; /* init maximum length */ - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - OSI_RET_OK_CHECK(sl_LockObjCreate(&g_pCB->MultiSelectCB.SelectLockObj, "SelectLockObj")); - OSI_RET_OK_CHECK(sl_SyncObjCreate(&g_pCB->MultiSelectCB.SelectSyncObj, "SelectSyncObj")); - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->MultiSelectCB.SelectSyncObj); - g_pCB->MultiSelectCB.CtrlSockFD = 0xFF; -#endif - return SL_OS_RET_CODE_OK; -} - -/***************************************************************************** -_SlDrvDriverCBDeinit - De init Driver Control Block -*****************************************************************************/ -_SlReturnVal_t _SlDrvDriverCBDeinit(void) -{ - _SlSpawnMsgItem_t* pCurr; - _SlSpawnMsgItem_t* pNext; - - /* Flow control de-init */ - g_pCB->FlowContCB.TxPoolCnt = 0; - - SL_SET_DEVICE_STATUS(0); - - SL_UNSET_DEVICE_STARTED; - - OSI_RET_OK_CHECK(sl_LockObjDelete(&g_pCB->FlowContCB.TxLockObj)); - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->FlowContCB.TxSyncObj)); -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - OSI_RET_OK_CHECK(sl_LockObjDelete(&g_pCB->MultiSelectCB.SelectLockObj)); - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->MultiSelectCB.SelectSyncObj)); -#endif - OSI_RET_OK_CHECK( sl_SyncObjDelete(&g_pCB->CmdSyncObj)); - - OSI_RET_OK_CHECK( sl_LockObjDelete(&g_pCB->ProtectionLockObj) ); - - g_pCB->FreePoolIdx = 0; - g_pCB->PendingPoolIdx = MAX_CONCURRENT_ACTIONS; - g_pCB->ActivePoolIdx = MAX_CONCURRENT_ACTIONS; - -#ifdef SL_MEMORY_MGMT_DYNAMIC - /* Release linked list of async buffers */ - pCurr = g_pCB->spawnMsgList; - while (NULL != pCurr) - { - pNext = pCurr->next; - sl_Free(pCurr->Buffer); - sl_Free(pCurr); - pCurr = pNext; - } - g_pCB->spawnMsgList = NULL; - -#endif - - g_pCB = NULL; - -#ifndef SL_TINY - /* Clear the restart device flag */ - SL_UNSET_RESTART_REQUIRED; -#endif - return SL_OS_RET_CODE_OK; -} - -/***************************************************************************** -_SlDrvRxIrqHandler - Interrupt handler -*****************************************************************************/ -_SlReturnVal_t _SlDrvRxIrqHandler(void *pValue) -{ - (void)pValue; - - sl_IfMaskIntHdlr(); - - RxIrqCnt++; - - if (TRUE == g_pCB->WaitForCmdResp) - { - OSI_RET_OK_CHECK( sl_SyncObjSignalFromIRQ(&g_pCB->CmdSyncObj) ); - } - else - { - (void)sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER); - } - return SL_OS_RET_CODE_OK; -} - -/***************************************************************************** -_SlDrvDriverIsApiAllowed - on LOCKED state, only 3 commands are allowed -*****************************************************************************/ -_SlReturnVal_t _SlDrvDriverIsApiAllowed(_u16 Silo) -{ - if (!SL_IS_COMMAND_ALLOWED) - { - if (SL_IS_DEVICE_STOP_IN_PROGRESS) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - if ((SL_IS_DEVICE_LOCKED) && (SL_OPCODE_SILO_FS != Silo)) - { - /* All APIs except the FS ones must be aborted if device is locked */ - return SL_RET_CODE_DEV_LOCKED; - } - if (SL_IS_RESTART_REQUIRED) - { - /* API has been aborted due command not allowed when Restart required */ - /* The opcodes allowed are: SL_OPCODE_DEVICE_STOP_COMMAND */ - return SL_API_ABORTED; - } - - if (!SL_IS_DEVICE_STARTED) - { - return SL_RET_CODE_DEV_NOT_STARTED; - } - - if (( SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_INITIATED_BY_USER) && !(SL_IS_PROVISIONING_API_ALLOWED)) - { - /* API has ignored due to provisioning in progress */ - return SL_RET_CODE_PROVISIONING_IN_PROGRESS; - } - - } - - return SL_OS_RET_CODE_OK; -} - - -/***************************************************************************** -_SlDrvCmdOp -*****************************************************************************/ -_SlReturnVal_t _SlDrvCmdOp( - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - _u8 IsLockRequired = TRUE; - - IsLockRequired = (SL_IS_PROVISIONING_IN_PROGRESS && (pCmdCtrl->Opcode == SL_OPCODE_DEVICE_STOP_COMMAND)) ? FALSE: TRUE; - - if (IsLockRequired) - { - _u32 GlobalLockFlags = GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS; - - /* check the special case of provisioning stop command */ - if (pCmdCtrl->Opcode == SL_OPCODE_WLAN_PROVISIONING_COMMAND) - { - SlWlanProvisioningParams_t *pParams = (SlWlanProvisioningParams_t *)pTxRxDescBuff; - - /* No timeout specifies it is a stop provisioning command */ - if (pParams->InactivityTimeoutSec == 0) - { - GlobalLockFlags |= GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API; - } - - } - - GlobalLockFlags |= (((_u32)pCmdCtrl->Opcode) << 16); - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GlobalLockFlags); - } - -#ifndef SL_TINY - /* In case the global was successfully taken but error in progress - it means it has been released as part of an error handling and we should abort immediately */ - if (SL_IS_RESTART_REQUIRED) - { - if (IsLockRequired) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - return SL_API_ABORTED; - } -#endif - - g_pCB->WaitForCmdResp = TRUE; - - SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdOp: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - - if(SL_OS_RET_CODE_OK == RetVal) - { - /* wait for respond */ - RetVal = _SlDrvMsgReadCmdCtx(pCmdCtrl->Opcode, IsLockRequired); /* will free global lock */ - SL_TRACE1(DBG_MSG, MSG_314, "\n\r_SlDrvCmdOp: exited _SlDrvMsgReadCmdCtx: %x\n\r", pCmdCtrl->Opcode); - } - else - { - if (IsLockRequired) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - } - - return RetVal; -} - -/***************************************************************************** -_SlDrvDataReadOp -*****************************************************************************/ -_SlReturnVal_t _SlDrvDataReadOp( - _SlSd_t Sd, - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - _SlArgsData_t pArgsData; - - /* Validate input arguments */ - _SL_ASSERT_ERROR(NULL != pCmdExt->pRxPayload, SL_RET_CODE_INVALID_INPUT); - - /* If zero bytes is requested, return error. */ - /* This allows us not to fill remote socket's IP address in return arguments */ - VERIFY_PROTOCOL(0 != pCmdExt->RxPayloadLen); - - /* Validate socket */ - if((Sd & SL_BSD_SOCKET_ID_MASK) >= SL_MAX_SOCKETS) - { - return SL_ERROR_BSD_EBADF; - } - - /*Use Obj to issue the command, if not available try later*/ - ObjIdx = _SlDrvWaitForPoolObj(RECV_ID, Sd & SL_BSD_SOCKET_ID_MASK); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - pArgsData.pData = pCmdExt->pRxPayload; - pArgsData.pArgs = (_u8 *)pTxRxDescBuff; - g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&pArgsData; - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - - /* Do Flow Control check/update for DataWrite operation */ - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->FlowContCB.TxLockObj); - - - /* Clear SyncObj for the case it was signaled before TxPoolCnt */ - /* dropped below '1' (last Data buffer was taken) */ - /* OSI_RET_OK_CHECK( sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj) ); */ - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->FlowContCB.TxSyncObj); - - if(g_pCB->FlowContCB.TxPoolCnt <= FLOW_CONT_MIN) - { - - /* If TxPoolCnt was increased by other thread at this moment, - TxSyncObj won't wait here */ -#if defined (SL_PLATFORM_MULTI_THREADED) - if (_SlDrvIsSpawnOwnGlobalLock()) - { - while (TRUE) - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->FlowContCB.TxSyncObj, SL_OS_NO_WAIT)) - { - break; - } - } - } - else -#endif - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->FlowContCB.TxSyncObj); - } - - } - - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); - -#ifndef SL_TINY - /* In case the global was successfully taken but error in progress - it means it has been released as part of an error handling and we should abort immediately */ - if (SL_IS_RESTART_REQUIRED) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - return SL_API_ABORTED; - } -#endif - - /* Here we consider the case in which some cmd has been sent to the NWP, - And its allocated packet has not been freed yet. */ - VERIFY_PROTOCOL(g_pCB->FlowContCB.TxPoolCnt > (FLOW_CONT_MIN - 1)); - g_pCB->FlowContCB.TxPoolCnt--; - - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, (_u8 *)pTxRxDescBuff); - - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - - if(SL_OS_RET_CODE_OK == RetVal) - { -#ifndef SL_TINY - /* in case socket is non-blocking one, the async event should be received immediately */ - if( g_pCB->SocketNonBlocking & (1<<(Sd & SL_BSD_SOCKET_ID_MASK) )) - { - _u16 opcodeAsyncEvent = (pCmdCtrl->Opcode == SL_OPCODE_SOCKET_RECV) ? SL_OPCODE_SOCKET_RECVASYNCRESPONSE : SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE; - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, opcodeAsyncEvent)); - } - else -#endif - { - /* Wait for response message. Will be signaled by _SlDrvMsgRead. */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); - } - - } - - _SlDrvReleasePoolObj(ObjIdx); - return RetVal; -} - -/* ******************************************************************************/ -/* _SlDrvDataWriteOp */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvDataWriteOp( - _SlSd_t Sd, - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal = SL_ERROR_BSD_EAGAIN; /* initiated as SL_EAGAIN for the non blocking mode */ - _u32 allocTxPoolPkts; - - while( 1 ) - { - /* Do Flow Control check/update for DataWrite operation */ - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->FlowContCB.TxLockObj); - - /* Clear SyncObj for the case it was signaled before TxPoolCnt */ - /* dropped below '1' (last Data buffer was taken) */ - /* OSI_RET_OK_CHECK( sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj) ); */ - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->FlowContCB.TxSyncObj); - - /* number of tx pool packet that will be used */ - allocTxPoolPkts = 1 + (pCmdExt->TxPayload1Len-1) / g_pCB->FlowContCB.MinTxPayloadSize; /* MinTxPayloadSize will be updated by Asunc event from NWP */ - /* we have indication that the last send has failed - socket is no longer valid for operations */ - if(g_pCB->SocketTXFailure & (1<<(Sd & SL_BSD_SOCKET_ID_MASK))) - { - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - return SL_ERROR_BSD_SOC_ERROR; - } - if(g_pCB->FlowContCB.TxPoolCnt <= FLOW_CONT_MIN + allocTxPoolPkts) - { - /* we have indication that this socket is set as blocking and we try to */ - /* unblock it - return an error */ - if( g_pCB->SocketNonBlocking & (1<<(Sd & SL_BSD_SOCKET_ID_MASK) )) - { -#if defined (SL_PLATFORM_MULTI_THREADED) - if (_SlDrvIsSpawnOwnGlobalLock()) - { - _SlInternalSpawnWaitForEvent(); - } -#endif - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - return RetVal; - } - /* If TxPoolCnt was increased by other thread at this moment, */ - /* TxSyncObj won't wait here */ -#if defined (SL_PLATFORM_MULTI_THREADED) - if (_SlDrvIsSpawnOwnGlobalLock()) - { - while (TRUE) - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->FlowContCB.TxSyncObj, SL_OS_NO_WAIT)) - { - break; - } - } - } - else -#endif - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->FlowContCB.TxSyncObj); - } - } - if(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN + allocTxPoolPkts ) - { - break; - } - else - { - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - } - } - - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); - -#ifndef SL_TINY - /* In case the global was succesffully taken but error in progress - it means it has been released as part of an error handling and we should abort immediately */ - if (SL_IS_RESTART_REQUIRED) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - return SL_API_ABORTED; - } -#endif - - /* Here we consider the case in which some cmd has been sent to the NWP, - And its allocated packet has not been freed yet. */ - VERIFY_PROTOCOL(g_pCB->FlowContCB.TxPoolCnt > (FLOW_CONT_MIN + allocTxPoolPkts -1) ); - g_pCB->FlowContCB.TxPoolCnt -= (_u8)allocTxPoolPkts; - - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - - SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdOp: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - - return RetVal; -} - -/* ******************************************************************************/ -/* _SlDrvMsgWrite */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvMsgWrite(_SlCmdCtrl_t *pCmdCtrl,_SlCmdExt_t *pCmdExt, _u8 *pTxRxDescBuff) -{ - _u8 sendRxPayload = FALSE; - _SL_ASSERT_ERROR(NULL != pCmdCtrl, SL_API_ABORTED); - - g_pCB->FunctionParams.pCmdCtrl = pCmdCtrl; - g_pCB->FunctionParams.pTxRxDescBuff = pTxRxDescBuff; - g_pCB->FunctionParams.pCmdExt = pCmdExt; - - g_pCB->TempProtocolHeader.Opcode = pCmdCtrl->Opcode; - g_pCB->TempProtocolHeader.Len = (_u16)(_SL_PROTOCOL_CALC_LEN(pCmdCtrl, pCmdExt)); - - if (pCmdExt && pCmdExt->RxPayloadLen < 0 ) - { - pCmdExt->RxPayloadLen = pCmdExt->RxPayloadLen * (-1); /* change sign */ - sendRxPayload = TRUE; - g_pCB->TempProtocolHeader.Len = g_pCB->TempProtocolHeader.Len + pCmdExt->RxPayloadLen; - } - -#ifdef SL_START_WRITE_STAT - sl_IfStartWriteSequence(g_pCB->FD); -#endif - -#ifdef SL_IF_TYPE_UART - /* Write long sync pattern */ - NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NSyncPattern.Long, 2*SYNC_PATTERN_LEN); -#else - /* Write short sync pattern */ - NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NSyncPattern.Short, SYNC_PATTERN_LEN); -#endif - - /* Header */ - NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_pCB->TempProtocolHeader, _SL_CMD_HDR_SIZE); - - /* Descriptors */ - if (pTxRxDescBuff && pCmdCtrl->TxDescLen > 0) - { - NWP_IF_WRITE_CHECK(g_pCB->FD, pTxRxDescBuff, - _SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen)); - } - - /* A special mode where Rx payload and Rx length are used as Tx as well */ - /* This mode requires no Rx payload on the response and currently used by fs_Close and sl_Send on */ - /* transceiver mode */ - if (sendRxPayload == TRUE ) - { - NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pRxPayload, - _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->RxPayloadLen)); - } - - - /* if the message has some payload */ - if (pCmdExt) - { - /* If the message has payload, it is mandatory that the message's arguments are protocol aligned. */ - /* Otherwise the aligning of arguments will create a gap between arguments and payload. */ - VERIFY_PROTOCOL(_SL_IS_PROTOCOL_ALIGNED_SIZE(pCmdCtrl->TxDescLen)); - - /* In case two seperated buffers were supplied we should merge the two buffers*/ - if ((pCmdExt->TxPayload1Len > 0) && (pCmdExt->TxPayload2Len > 0)) - { - _u8 BuffInTheMiddle[4]; - _u8 FirstPayloadReminder = 0; - _u8 SecondPayloadOffset = 0; - - FirstPayloadReminder = pCmdExt->TxPayload1Len & 3; /* calulate the first payload reminder */ - - /* we first write the 4-bytes aligned payload part */ - pCmdExt->TxPayload1Len -= FirstPayloadReminder; - - /* writing the first transaction*/ - NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload1, pCmdExt->TxPayload1Len); - - /* Only if we the first payload is not aligned we need the intermediate transaction */ - if (FirstPayloadReminder != 0) - { - /* here we count how many bytes we need to take from the second buffer */ - SecondPayloadOffset = 4 - FirstPayloadReminder; - - /* copy the first payload reminder */ - sl_Memcpy(&BuffInTheMiddle[0], pCmdExt->pTxPayload1 + pCmdExt->TxPayload1Len, FirstPayloadReminder); - - /* add the beginning of the second payload to complete 4-bytes transaction */ - sl_Memcpy(&BuffInTheMiddle[FirstPayloadReminder], pCmdExt->pTxPayload2, SecondPayloadOffset); - - /* write the second transaction of the 4-bytes buffer */ - NWP_IF_WRITE_CHECK(g_pCB->FD, &BuffInTheMiddle[0], 4); - } - - - /* if we still has bytes to write in the second buffer */ - if (pCmdExt->TxPayload2Len > SecondPayloadOffset) - { - /* write the third transaction (truncated second payload) */ - NWP_IF_WRITE_CHECK(g_pCB->FD, - pCmdExt->pTxPayload2 + SecondPayloadOffset, - _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload2Len - SecondPayloadOffset)); - } - - } - else if (pCmdExt->TxPayload1Len > 0) - { - /* Only 1 payload supplied (Payload1) so just align to 4 bytes and send it */ - NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload1, - _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload1Len)); - } - else if (pCmdExt->TxPayload2Len > 0) - { - /* Only 1 payload supplied (Payload2) so just align to 4 bytes and send it */ - NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload2, - _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload2Len)); - - } - } - - _SL_DBG_CNT_INC(MsgCnt.Write); - -#ifdef SL_START_WRITE_STAT - sl_IfEndWriteSequence(g_pCB->FD); -#endif - - return SL_OS_RET_CODE_OK; -} - -/* ******************************************************************************/ -/* _SlDrvMsgRead */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvMsgRead(_u16* outMsgReadLen, _u8** pOutAsyncBuf) -{ - /* alignment for small memory models */ - union - { - _u8 TempBuf[_SL_RESP_HDR_SIZE]; - _u32 DummyBuf[2]; - } uBuf; - _u8 TailBuffer[4]; - _u16 LengthToCopy; - _u16 AlignedLengthRecv; - _u8 *pAsyncBuf = NULL; - _u16 OpCode; - _u16 RespPayloadLen; - _u8 sd = SL_MAX_SOCKETS; - _SlReturnVal_t RetVal; - _SlRxMsgClass_e RxMsgClass; - - /* Save parameters in global CB */ - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = NULL; - _SlDrvMemZero(&TailBuffer[0], sizeof(TailBuffer)); - -#ifdef SL_TINY - VERIFY_RET_OK(_SlDrvRxHdrRead((_u8*)(uBuf.TempBuf))); -#else - if (_SlDrvRxHdrRead((_u8*)(uBuf.TempBuf)) == SL_API_ABORTED) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_SYNC_LOSS, 0, 0); - return SL_API_ABORTED; - } -#endif - - OpCode = OPCODE(uBuf.TempBuf); - RespPayloadLen = (_u16)(RSP_PAYLOAD_LEN(uBuf.TempBuf)); - - /* Update the NWP status */ - g_pCB->FlowContCB.TxPoolCnt = ((_SlResponseHeader_t *)uBuf.TempBuf)->TxPoolCnt; - g_pCB->SocketNonBlocking = ((_SlResponseHeader_t *)uBuf.TempBuf)->SocketNonBlocking; - g_pCB->SocketTXFailure = ((_SlResponseHeader_t *)uBuf.TempBuf)->SocketTXFailure; - g_pCB->FlowContCB.MinTxPayloadSize = ((_SlResponseHeader_t *)uBuf.TempBuf)->MinMaxPayload; - - SL_SET_DEVICE_STATUS(((_SlResponseHeader_t *)uBuf.TempBuf)->DevStatus); - - if(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->FlowContCB.TxSyncObj); - } - - /* Find the RX message class and set its Async event handler */ - _SlDrvClassifyRxMsg(OpCode); - - RxMsgClass = g_pCB->FunctionParams.AsyncExt.RxMsgClass; - - switch(RxMsgClass) - { - case ASYNC_EVT_CLASS: - { - VERIFY_PROTOCOL(NULL == pAsyncBuf); - -#ifdef SL_MEMORY_MGMT_DYNAMIC - *pOutAsyncBuf = (_u8*)sl_Malloc(SL_ASYNC_MAX_MSG_LEN); - -#else - *pOutAsyncBuf = g_StatMem.AsyncRespBuf; -#endif - /* set the local pointer to the allocated one */ - pAsyncBuf = *pOutAsyncBuf; - - MALLOC_OK_CHECK(pAsyncBuf); - - /* clear the async buffer */ - _SlDrvMemZero(pAsyncBuf, (_u16)SL_ASYNC_MAX_MSG_LEN); - sl_Memcpy(pAsyncBuf, uBuf.TempBuf, _SL_RESP_HDR_SIZE); - - /* add the protocol header length */ - *outMsgReadLen = _SL_RESP_HDR_SIZE; - - if (_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) <= SL_ASYNC_MAX_PAYLOAD_LEN) - { - AlignedLengthRecv = (_u16)_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen); - } - else - { - AlignedLengthRecv = (_u16)_SL_PROTOCOL_ALIGN_SIZE(SL_ASYNC_MAX_PAYLOAD_LEN); - } - - /* complete the read of the entire message to the async buffer */ - if (RespPayloadLen > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD, - pAsyncBuf + _SL_RESP_HDR_SIZE, - AlignedLengthRecv); - *outMsgReadLen += AlignedLengthRecv; - } - /* In case ASYNC RX buffer length is smaller then the received data length, dump the rest */ - if ((_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) > SL_ASYNC_MAX_PAYLOAD_LEN)) - { - AlignedLengthRecv = (_u16)(_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) - SL_ASYNC_MAX_PAYLOAD_LEN); - while (AlignedLengthRecv > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); - AlignedLengthRecv = AlignedLengthRecv - 4; - } - } - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - if ( -#ifndef SL_TINY - (SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE == OpCode) || - (SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE_V6 == OpCode) || -#endif - (SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE == OpCode) || - (SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT == OpCode) - ) - { - /* go over the active list if exist to find obj waiting for this Async event */ - sd = ((((SlSocketResponse_t *)(pAsyncBuf + _SL_RESP_HDR_SIZE))->Sd) & SL_BSD_SOCKET_ID_MASK); - } -#ifndef SL_TINY - if (SL_OPCODE_SOCKET_SOCKETASYNCEVENT == OpCode) - { - /* Save the socket descriptor which has been waiting for this opcode */ - sd = ((((SlSocketAsyncEvent_t *)(pAsyncBuf + _SL_RESP_HDR_SIZE))->Sd) & SL_BSD_SOCKET_ID_MASK); - } -#endif - - (void)_SlDrvFindAndSetActiveObj(OpCode, sd); - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - break; - } - - case RECV_RESP_CLASS: - { - _u8 ExpArgSize; /* Expected size of Recv/Recvfrom arguments */ - - switch(OpCode) - { - case SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE: - ExpArgSize = (_u8)RECVFROM_IPV4_ARGS_SIZE; - break; -#ifndef SL_TINY - case SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6: - ExpArgSize = (_u8)RECVFROM_IPV6_ARGS_SIZE; - break; -#endif - default: - /* SL_OPCODE_SOCKET_RECVASYNCRESPONSE: */ - ExpArgSize = (_u8)RECV_ARGS_SIZE; - } - - /* Read first 4 bytes of Recv/Recvfrom response to get SocketId and actual */ - /* response data length */ - NWP_IF_READ_CHECK(g_pCB->FD, &uBuf.TempBuf[4], RECV_ARGS_SIZE); - - /* Validate Socket ID and Received Length value. */ - VERIFY_PROTOCOL((SD(&uBuf.TempBuf[4])& SL_BSD_SOCKET_ID_MASK) < SL_MAX_SOCKETS); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - /* go over the active list if exist to find obj waiting for this Async event */ - RetVal = _SlDrvFindAndSetActiveObj(OpCode, SD(&uBuf.TempBuf[4]) & SL_BSD_SOCKET_ID_MASK); - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - /* This case is for reading the receive response sent by clearing the control socket. */ - if((RetVal == SL_RET_CODE_SELF_ERROR) && (SD(&uBuf.TempBuf[4]) == g_pCB->MultiSelectCB.CtrlSockFD)) - { - _u8 buffer[16]; - - sl_Memcpy(&buffer[0], &uBuf.TempBuf[4], RECV_ARGS_SIZE); - - if(ExpArgSize > (_u8)RECV_ARGS_SIZE) - { - NWP_IF_READ_CHECK(g_pCB->FD, - &buffer[RECV_ARGS_SIZE], - ExpArgSize - RECV_ARGS_SIZE); - } - - /* Here g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData contains requested(expected) Recv/Recvfrom DataSize. */ - /* Overwrite requested DataSize with actual one. */ - /* If error is received, this information will be read from arguments. */ - if(ACT_DATA_SIZE(&uBuf.TempBuf[4]) > 0) - { - - /* Read 4 bytes aligned from interface */ - /* therefore check the requested length and read only */ - /* 4 bytes aligned data. The rest unaligned (if any) will be read */ - /* and copied to a TailBuffer */ - LengthToCopy = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (3)); - AlignedLengthRecv = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (~3)); - if( AlignedLengthRecv >= 4) - { - NWP_IF_READ_CHECK(g_pCB->FD, &buffer[ExpArgSize], AlignedLengthRecv); - } - /* copy the unaligned part, if any */ - if( LengthToCopy > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); - /* copy TailBuffer unaligned part (1/2/3 bytes) */ - sl_Memcpy(&buffer[ExpArgSize + AlignedLengthRecv], TailBuffer, LengthToCopy); - } - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - else -#endif - { - /* if _SlDrvFindAndSetActiveObj returned an error, release the protection lock, and return. */ - if(RetVal < 0) - { - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_API_ABORTED; - } - - /* Verify data is waited on this socket. The pArgs should have been set by _SlDrvDataReadOp(). */ - VERIFY_SOCKET_CB(NULL != ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData))->pArgs); - - sl_Memcpy( ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pArgs, &uBuf.TempBuf[4], RECV_ARGS_SIZE); - - if(ExpArgSize > (_u8)RECV_ARGS_SIZE) - { - NWP_IF_READ_CHECK(g_pCB->FD, - ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pArgs + RECV_ARGS_SIZE, - ExpArgSize - RECV_ARGS_SIZE); - } - - /* Here g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData contains requested(expected) Recv/Recvfrom DataSize. */ - /* Overwrite requested DataSize with actual one. */ - /* If error is received, this information will be read from arguments. */ - if(ACT_DATA_SIZE(&uBuf.TempBuf[4]) > 0) - { - VERIFY_SOCKET_CB(NULL != ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData); - - /* Read 4 bytes aligned from interface */ - /* therefore check the requested length and read only */ - /* 4 bytes aligned data. The rest unaligned (if any) will be read */ - /* and copied to a TailBuffer */ - LengthToCopy = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (3)); - AlignedLengthRecv = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (~3)); - if( AlignedLengthRecv >= 4) - { - NWP_IF_READ_CHECK(g_pCB->FD,((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData, AlignedLengthRecv); - } - /* copy the unaligned part, if any */ - if( LengthToCopy > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); - /* copy TailBuffer unaligned part (1/2/3 bytes) */ - sl_Memcpy(((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData + AlignedLengthRecv,TailBuffer,LengthToCopy); - } - } - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - - break; - } - - case CMD_RESP_CLASS: - { - /* Some commands pass a maximum arguments size. */ - /* In this case Driver will send extra dummy patterns to NWP if */ - /* the response message is smaller than maximum. */ - /* When RxDescLen is not exact, using RxPayloadLen is forbidden! */ - /* If such case cannot be avoided - parse message here to detect */ - /* arguments/payload border. */ - NWP_IF_READ_CHECK(g_pCB->FD, - g_pCB->FunctionParams.pTxRxDescBuff, - _SL_PROTOCOL_ALIGN_SIZE(g_pCB->FunctionParams.pCmdCtrl->RxDescLen)); - - if((NULL != g_pCB->FunctionParams.pCmdExt) && (0 != g_pCB->FunctionParams.pCmdExt->RxPayloadLen)) - { - /* Actual size of command's response payload: - */ - _i16 ActDataSize = (_i16)(RSP_PAYLOAD_LEN(uBuf.TempBuf) - g_pCB->FunctionParams.pCmdCtrl->RxDescLen); - - g_pCB->FunctionParams.pCmdExt->ActualRxPayloadLen = ActDataSize; - - /* Check that the space prepared by user for the response data is sufficient. */ - if(ActDataSize <= 0) - { - g_pCB->FunctionParams.pCmdExt->RxPayloadLen = 0; - } - else - { - /* In case the user supplied Rx buffer length which is smaller then the received data length, copy according to user length */ - if (ActDataSize > g_pCB->FunctionParams.pCmdExt->RxPayloadLen) - { - LengthToCopy = (_u16)(g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (3)); - AlignedLengthRecv = (_u16)(g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (~3)); - } - else - { - LengthToCopy = (_u16)(ActDataSize & (3)); - AlignedLengthRecv = (_u16)(ActDataSize & (~3)); - } - /* Read 4 bytes aligned from interface */ - /* therefore check the requested length and read only */ - /* 4 bytes aligned data. The rest unaligned (if any) will be read */ - /* and copied to a TailBuffer */ - - if( AlignedLengthRecv >= 4) - { - NWP_IF_READ_CHECK(g_pCB->FD, - g_pCB->FunctionParams.pCmdExt->pRxPayload, - AlignedLengthRecv ); - - } - /* copy the unaligned part, if any */ - if( LengthToCopy > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); - /* copy TailBuffer unaligned part (1/2/3 bytes) */ - sl_Memcpy(g_pCB->FunctionParams.pCmdExt->pRxPayload + AlignedLengthRecv, - TailBuffer, - LengthToCopy); - ActDataSize = ActDataSize-4; - } - /* In case the user supplied Rx buffer length which is smaller then the received data length, dump the rest */ - if (ActDataSize > g_pCB->FunctionParams.pCmdExt->RxPayloadLen) - { - /* calculate the rest of the data size to dump */ - AlignedLengthRecv = (_u16)( (ActDataSize + 3 - g_pCB->FunctionParams.pCmdExt->RxPayloadLen) & (~3) ); - while( AlignedLengthRecv > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer, 4 ); - AlignedLengthRecv = AlignedLengthRecv - 4; - } - } - } - } - - break; - } - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - case MULTI_SELECT_RESP_CLASS: - { - /* In case we read Select Response from NWP, and we're not waiting for - * command complete, that means that a select command was send for a select Joiner. */ - - _u8 Idx; - - NWP_IF_READ_CHECK(g_pCB->FD, - (_u8*)(&g_pCB->MultiSelectCB.SelectCmdResp), - _SL_PROTOCOL_ALIGN_SIZE(sizeof(_BasicResponse_t))); - - if(g_pCB->MultiSelectCB.SelectCmdResp.status != SL_RET_CODE_OK) - { - /* If a select response returns without Status O.K, this means that - * something terribly wrong have happen. So we stop all waiting select callers, - * and return command error. */ - g_pCB->MultiSelectCB.ActiveSelect = FALSE; - - for(Idx = 0 ; Idx < MAX_CONCURRENT_ACTIONS ; Idx++) - { - if(g_pCB->MultiSelectCB.SelectEntry[Idx] != NULL) - { - sl_SyncObjSignal(&g_pCB->ObjPool[Idx].SyncObj); - } - } - /* Clean all table entries, and clear the global read/write fds */ - _SlDrvMemZero(&g_pCB->MultiSelectCB, sizeof(_SlMultiSelectCB_t)); - } - - break; - } -#endif - - default: - /* DUMMY_MSG_CLASS: Flow control message has no payload. */ - break; - } - - _SL_DBG_CNT_INC(MsgCnt.Read); - - /* Unmask Interrupt call */ - sl_IfUnMaskIntHdlr(); - - return SL_OS_RET_CODE_OK; -} - - -/* ******************************************************************************/ -/* _SlDrvAsyncEventGenericHandler */ -/* ******************************************************************************/ -static void _SlDrvAsyncEventGenericHandler(_u8 bInCmdContext, _u8 *pAsyncBuffer) -{ - _u32 SlAsyncEvent = 0; - _u8 OpcodeFound = FALSE; - _u8 i; - - _u32* pEventLocation = NULL; /* This pointer will override the async buffer with the translated event type */ - _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)pAsyncBuffer; - - - /* if no async event registered nothing to do..*/ - if (g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler == NULL) - { - return; - } - - /* In case we in the middle of the provisioning, filter out - all the async events except the provisioning ones */ - if ( (( SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_INITIATED_BY_USER) && !(SL_IS_PROVISIONING_API_ALLOWED)) && - (pHdr->GenHeader.Opcode != SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT) && - (pHdr->GenHeader.Opcode != SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT) && - (pHdr->GenHeader.Opcode != SL_OPCODE_DEVICE_INITCOMPLETE) && - (pHdr->GenHeader.Opcode != SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE) && - (pHdr->GenHeader.Opcode != SL_OPCODE_NETAPP_REQUEST) ) - { - return; - } - - /* Iterate through all the opcode in the table */ - for (i=0; i< (_u8)(sizeof(OpcodeTranslateTable) / sizeof(OpcodeKeyVal_t)); i++) - { - if (OpcodeTranslateTable[i].opcode == pHdr->GenHeader.Opcode) - { - SlAsyncEvent = OpcodeTranslateTable[i].event; - OpcodeFound = TRUE; - break; - } - } - - /* No Async event found in the table */ - if (OpcodeFound == FALSE) - { - if ((pHdr->GenHeader.Opcode & SL_OPCODE_SILO_MASK) == SL_OPCODE_SILO_DEVICE) - { - DeviceEventInfo_t deviceEvent; - - deviceEvent.pAsyncMsgBuff = pAsyncBuffer; - deviceEvent.bInCmdContext = bInCmdContext; - - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&deviceEvent); - } - else - { - /* This case handles all the async events handlers of the DEVICE & SOCK Silos which are handled internally. - For these cases we send the async even buffer as is */ - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(pAsyncBuffer); - } - } - else - { - /* calculate the event type location to be filled in the async buffer */ - pEventLocation = (_u32*)(pAsyncBuffer + sizeof (_SlResponseHeader_t) - sizeof(SlAsyncEvent)); - - /* Override the async buffer (before the data starts ) with our event type */ - *pEventLocation = SlAsyncEvent; - - /* call the event handler registered by the user with our async buffer which now holds - the User's event type and its related data */ - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(pEventLocation); - - } -} - -/* ******************************************************************************/ -/* _SlDrvMsgReadCmdCtx */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvMsgReadCmdCtx(_u16 cmdOpcode, _u8 IsLockRequired) -{ -#ifndef SL_TINY - _u32 CmdCmpltTimeout; - _i16 RetVal=0; - _u8 *pAsyncBuf = NULL; - - /* the sl_FsOpen/sl_FsProgram APIs may take long time */ - if ((cmdOpcode == SL_OPCODE_NVMEM_FILEOPEN) || (cmdOpcode == SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND)) - { - CmdCmpltTimeout = ((_u32)SL_DRIVER_TIMEOUT_LONG * 10); - } - else - { - /* For any FS command, the timeout will be the long one as the commnad response holds the full response data */ - CmdCmpltTimeout = (SL_OPCODE_SILO_FS & cmdOpcode)? (_u32)(SL_DRIVER_TIMEOUT_LONG) : (_u32)SL_DRIVER_TIMEOUT_SHORT; - } -#endif - - /* after command response is received and WaitForCmdResp */ - /* flag is set FALSE, it is necessary to read out all */ - /* Async messages in Commands context, because ssiDma_IsrHandleSignalFromSlave */ - /* could have dispatched some Async messages to g_NwpIf.CmdSyncObj */ - /* after command response but before this response has been processed */ - /* by spi_singleRead and WaitForCmdResp was set FALSE. */ - while (TRUE == g_pCB->WaitForCmdResp) - { - if(_SL_PENDING_RX_MSG(g_pCB)) - { - _u16 outMsgLen = 0; -#ifdef SL_TINY - VERIFY_RET_OK(_SlDrvMsgRead(&outMsgLen)); -#else - RetVal = _SlDrvMsgRead(&outMsgLen,&pAsyncBuf); - - if (RetVal != SL_OS_RET_CODE_OK) - { - g_pCB->WaitForCmdResp = FALSE; - - if ((IsLockRequired) && (RetVal != SL_API_ABORTED)) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - return SL_API_ABORTED; - } -#endif - g_pCB->RxDoneCnt++; - - if (CMD_RESP_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) - { - g_pCB->WaitForCmdResp = FALSE; - /* In case CmdResp has been read without waiting on CmdSyncObj - that */ - /* Sync object. That to prevent old signal to be processed. */ - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->CmdSyncObj); - } - else if (ASYNC_EVT_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) - { - -#ifdef SL_PLATFORM_MULTI_THREADED - /* Do not handle async events in command context */ - /* All async events data will be stored in list and handled in spawn context */ - RetVal = _SlSpawnMsgListInsert(outMsgLen, pAsyncBuf); - if (SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR == RetVal) - { - _SlFindAndReleasePendingCmd(); - } - -#else - _SlDrvAsyncEventGenericHandler(TRUE, pAsyncBuf); -#endif - -#ifdef SL_MEMORY_MGMT_DYNAMIC - sl_Free(pAsyncBuf); -#else - pAsyncBuf = NULL; -#endif - } -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - else if(MULTI_SELECT_RESP_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) - { - sl_SyncObjSignal(&g_pCB->MultiSelectCB.SelectSyncObj); - } -#endif - } - else - { -#ifdef SL_TINY - /* CmdSyncObj will be signaled by IRQ */ - _SlDrvSyncObjWaitForever(&g_pCB->CmdSyncObj); -#else - - RetVal = sl_SyncObjWait(&g_pCB->CmdSyncObj, CmdCmpltTimeout); - if (RetVal != 0) - { - g_pCB->WaitForCmdResp = FALSE; - - if (IsLockRequired) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - /* only if device started handle the fatal error */ - if (SL_IS_DEVICE_STARTED) - { - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_NO_CMD_ACK, cmdOpcode, (_u32)CmdCmpltTimeout); - } - - return SL_API_ABORTED; - } -#endif - } - } - -#ifdef SL_PLATFORM_MULTI_THREADED - if (_SlSpawnMsgListGetCount() > 0) - { - /* signal the spawn task to process the pending async events received during the cmd */ - sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_CMD_PROCESS); - } -#endif - - /* If there are more pending Rx Msgs after CmdResp is received, */ - /* that means that these are Async, Dummy or Read Data Msgs. */ - /* Spawn _SlDrvMsgReadSpawnCtx to trigger reading these messages from */ - /* Temporary context. */ - /* sl_Spawn is activated, using a different context */ - if (IsLockRequired) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - if(_SL_PENDING_RX_MSG(g_pCB)) - { - sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_CMD_CTX); - } - - return SL_OS_RET_CODE_OK; -} - -/* ******************************************************************************/ -/* _SlDrvMsgReadSpawnCtx */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvMsgReadSpawnCtx(void *pValue) -{ - _SlReturnVal_t RetVal = SL_OS_RET_CODE_OK; - _u16 outMsgLen = 0; - _u8 *pAsyncBuf = NULL; - -#ifdef SL_POLLING_MODE_USED - - /* for polling based systems */ - do - { - if (GlobalLockObj != NULL) - { - RetVal = sl_LockObjLock(&GlobalLockObj, 0); - - if (SL_OS_RET_CODE_OK != RetVal ) - { - if (TRUE == g_pCB->WaitForCmdResp) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->CmdSyncObj); - return SL_RET_CODE_OK; - } - } - - } - - } - while (SL_OS_RET_CODE_OK != RetVal); - -#else - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); -#endif - -#ifndef SL_PLATFORM_MULTI_THREADED - /* set the global lock owner (spawn context) */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_SPAWN); -#endif - /* pValue parameter is currently not in use */ - (void)pValue; - - /* Messages might have been read by CmdResp context. Therefore after */ - /* getting LockObj, check again where the Pending RX Msg is still present. */ - if(FALSE == (_SL_PENDING_RX_MSG(g_pCB))) - { -#ifndef SL_PLATFORM_MULTI_THREADED - /* clear the global lock owner (spawn context) */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); -#endif - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - - return SL_RET_CODE_OK; - } - -#ifdef SL_TINY - VERIFY_RET_OK(_SlDrvMsgRead(&outMsgLen)); -#else - RetVal = _SlDrvMsgRead(&outMsgLen,&pAsyncBuf); - - if (RetVal != SL_OS_RET_CODE_OK) - { - if (RetVal != SL_API_ABORTED) - { -#ifndef SL_PLATFORM_MULTI_THREADED - /* clear the global lock owner (spawn context) */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); -#endif - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - } - - return SL_API_ABORTED; - } -#endif - - g_pCB->RxDoneCnt++; - - switch(g_pCB->FunctionParams.AsyncExt.RxMsgClass) - { - case ASYNC_EVT_CLASS: - /* If got here and protected by LockObj a message is waiting */ - /* to be read */ - VERIFY_PROTOCOL(NULL != pAsyncBuf); - - - _SlDrvAsyncEventGenericHandler(FALSE, pAsyncBuf); - -#ifdef SL_MEMORY_MGMT_DYNAMIC - sl_Free(pAsyncBuf); -#else - pAsyncBuf = NULL; -#endif - break; - case DUMMY_MSG_CLASS: - case RECV_RESP_CLASS: - /* These types are legal in this context. Do nothing */ - break; - case CMD_RESP_CLASS: - /* Command response is illegal in this context - */ - /* One exception exists though: 'Select' response (SL_OPCODE_SOCKET_SELECTRESPONSE) Opcode = 0x1407 */ - break; -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - case MULTI_SELECT_RESP_CLASS: - /* If everything's OK, we signal for any other joiners to call 'Select'.*/ - sl_SyncObjSignal(&g_pCB->MultiSelectCB.SelectSyncObj); - break; -#endif - default: - _SL_ASSERT_ERROR(0, SL_API_ABORTED); - } -#ifndef SL_PLATFORM_MULTI_THREADED - /* clear the global lock owner (spawn context) */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); -#endif - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - - return(SL_RET_CODE_OK); -} - -/* - -#define SL_OPCODE_SILO_DEVICE ( 0x0 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_WLAN ( 0x1 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_SOCKET ( 0x2 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETAPP ( 0x3 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_FS ( 0x4 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETCFG ( 0x5 << SL_OPCODE_SILO_OFFSET ) - -*/ - -/* The Lookup table below holds the event handlers to be called according to the incoming - RX message SILO type */ -static const _SlSpawnEntryFunc_t RxMsgClassLUT[] = { - (_SlSpawnEntryFunc_t)_SlDeviceEventHandler, /* SL_OPCODE_SILO_DEVICE */ -#if defined(slcb_WlanEvtHdlr) || defined(EXT_LIB_REGISTERED_WLAN_EVENTS) - (_SlSpawnEntryFunc_t)_SlDrvHandleWlanEvents, /* SL_OPCODE_SILO_WLAN */ -#else - NULL, -#endif -#if defined (slcb_SockEvtHdlr) || defined(EXT_LIB_REGISTERED_SOCK_EVENTS) - (_SlSpawnEntryFunc_t)_SlDrvHandleSockEvents, /* SL_OPCODE_SILO_SOCKET */ -#else - NULL, -#endif -#if defined(slcb_NetAppEvtHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_EVENTS) - (_SlSpawnEntryFunc_t)_SlDrvHandleNetAppEvents, /* SL_OPCODE_SILO_NETAPP */ -#else - NULL, -#endif - NULL, /* SL_OPCODE_SILO_FS */ - NULL, /* SL_OPCODE_SILO_NETCFG */ - (_SlSpawnEntryFunc_t)_SlNetUtilHandleAsync_Cmd, /* SL_OPCODE_SILO_NETUTIL */ - NULL -}; - - -/* ******************************************************************************/ -/* _SlDrvClassifyRxMsg */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvClassifyRxMsg( - _SlOpcode_t Opcode) -{ - _SlSpawnEntryFunc_t AsyncEvtHandler = NULL; - _SlRxMsgClass_e RxMsgClass = CMD_RESP_CLASS; - _u8 Silo; - - - if (0 == (SL_OPCODE_SYNC & Opcode)) - { /* Async event has received */ - - if (SL_OPCODE_DEVICE_DEVICEASYNCDUMMY == Opcode) - { - RxMsgClass = DUMMY_MSG_CLASS; - } - else if ( (SL_OPCODE_SOCKET_RECVASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE == Opcode) -#ifndef SL_TINY - || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 == Opcode) -#endif - ) - { - RxMsgClass = RECV_RESP_CLASS; - } - else - { - /* This is Async Event class message */ - RxMsgClass = ASYNC_EVT_CLASS; - - /* Despite the fact that 4 bits are allocated in the SILO field, we actually have only 6 SILOs - So we can use the 8 options of SILO in look up table */ - Silo = (_u8)((Opcode >> SL_OPCODE_SILO_OFFSET) & 0x7); - - VERIFY_PROTOCOL(Silo < (_u8)(sizeof(RxMsgClassLUT)/sizeof(_SlSpawnEntryFunc_t))); - - /* Set the SILO's async event handler according to the LUT - If this specific event requires a direct async event handler, the - async event handler will be overwrite according to the action table */ - AsyncEvtHandler = RxMsgClassLUT[Silo]; - - if ((SL_OPCODE_NETAPP_HTTPGETTOKENVALUE == Opcode) || (SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE == Opcode) || - (SL_OPCODE_NETAPP_REQUEST == Opcode) || (SL_OPCODE_NETAPP_RESPONSE == Opcode) || (SL_OPCODE_NETAPP_SEND == Opcode)) - { - AsyncEvtHandler = _SlNetAppEventHandler; - } -#ifndef SL_TINY - else if (SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE == Opcode) - { - AsyncEvtHandler = (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_PingResponse; - } -#endif - } - } -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - else if((Opcode == SL_OPCODE_SOCKET_SELECTRESPONSE) && - (g_pCB->FunctionParams.pCmdCtrl->Opcode != SL_OPCODE_SOCKET_SELECT)) - { - /* Only in case this response came from a 'Select' sent in an Async event, Mark the message as MULTI_SELECT_RESPONSE */ - RxMsgClass = MULTI_SELECT_RESP_CLASS; - } -#endif - g_pCB->FunctionParams.AsyncExt.RxMsgClass = RxMsgClass; - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = AsyncEvtHandler; - - return SL_RET_CODE_OK; -} - - -/* ******************************************************************************/ -/* _SlDrvRxHdrRead */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvRxHdrRead(_u8 *pBuf) -{ - _u8 ShiftIdx; - _u8 TimeoutState = TIMEOUT_STATE_INIT_VAL; - _u8 SearchSync = TRUE; - _u8 SyncPattern[4]; -#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) - _SlTimeoutParams_t TimeoutInfo={0}; -#endif - -#ifndef SL_IF_TYPE_UART - /* 1. Write CNYS pattern to NWP when working in SPI mode only */ - NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NCnysPattern.Short, SYNC_PATTERN_LEN); -#endif - -#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) - _SlDrvStartMeasureTimeout(&TimeoutInfo, SYNC_PATTERN_TIMEOUT_IN_MSEC); -#endif - - /* 2. Read 8 bytes (protocol aligned) - expected to be the sync pattern */ - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], 8); - - /* read while first 4 bytes are different than last 4 bytes */ - while ( *(_u32 *)&pBuf[0] == *(_u32 *)&pBuf[4]) - { - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[4], 4); -#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) - if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) - { - return SL_API_ABORTED; - } -#endif - } - - /* scan for the sync pattern till found or timeout elapsed (if configured) */ - while (SearchSync && TimeoutState) - { - /* scan till we get the real sync pattern */ - for (ShiftIdx =0; ShiftIdx <=4 ; ShiftIdx++) - { - /* copy to local variable to ensure starting address which is 4-bytes aligned */ - sl_Memcpy(&SyncPattern[0], &pBuf[ShiftIdx], 4); - - /* sync pattern found so complete the read to 4 bytes aligned */ - if (N2H_SYNC_PATTERN_MATCH(&SyncPattern[0], g_pCB->TxSeqNum)) - { - /* copy the bytes following the sync pattern to the buffer start */ - sl_Memcpy(&pBuf[0], &pBuf[ShiftIdx + SYNC_PATTERN_LEN], 4); - - if (ShiftIdx != 0) - { - /* read the rest of the bytes (only if wer'e not aligned) (expected to complete the opcode + length fields ) */ - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[SYNC_PATTERN_LEN - ShiftIdx], ShiftIdx); - } - - /* here we except to get the opcode + length or false doubled sync..*/ - SearchSync = FALSE; - break; - } - } - - if (SearchSync == TRUE) - { - /* sync not found move top 4 bytes to bottom */ - *(_u32 *)&pBuf[0] = *(_u32 *)&pBuf[4]; - - /* read 4 more bytes to the buffer top */ - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[4], 4); - } - - #if (defined (slcb_GetTimestamp)) && (!defined (SL_TINY)) - - /* if we got here after first timeout detection, it means that we gave - one more chance, and we can now exit the loop with timeout expiry */ - if (TIMEOUT_ONE_MORE_SHOT == TimeoutState) - { - TimeoutState = TIMEOUT_STATE_EXPIRY; - break; - } - - /* Timeout occured. do not break now as we want to give one more chance in case - the timeout occured due to some external context switch */ - if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) - { - TimeoutState = TIMEOUT_ONE_MORE_SHOT; - } - -#endif - } /* end of while */ - -#if (defined (slcb_GetTimestamp)) && (!defined (SL_TINY)) - if (TIMEOUT_STATE_EXPIRY == TimeoutState) - { - return SL_API_ABORTED; - } -#endif - - /* 6. Scan for Double pattern. */ - while ( N2H_SYNC_PATTERN_MATCH(pBuf, g_pCB->TxSeqNum) ) - { - _SL_DBG_CNT_INC(Work.DoubleSyncPattern); - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], SYNC_PATTERN_LEN); - } - g_pCB->TxSeqNum++; - - /* 7. Here we've read Generic Header (4 bytes opcode+length). - * Now Read the Resp Specific header (4 more bytes). */ - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[SYNC_PATTERN_LEN], _SL_RESP_SPEC_HDR_SIZE); - - return SL_RET_CODE_OK; -} - -/* ***************************************************************************** */ -/* _SlDrvBasicCmd */ -/* ***************************************************************************** */ -typedef union -{ - _BasicResponse_t Rsp; -}_SlBasicCmdMsg_u; - - -#ifndef SL_TINY -_SlReturnVal_t _SlDrvBasicCmd(_SlOpcode_t Opcode) -{ - _SlBasicCmdMsg_u Msg; - _SlCmdCtrl_t CmdCtrl; - - _SlDrvMemZero(&Msg, (_u16)sizeof(_SlBasicCmdMsg_u)); - CmdCtrl.Opcode = Opcode; - CmdCtrl.TxDescLen = 0; - CmdCtrl.RxDescLen = (_SlArgSize_t)sizeof(_BasicResponse_t); - - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); - - return (_SlReturnVal_t)Msg.Rsp.status; -} -#endif - -/***************************************************************************** - _SlDrvCmdSend_noLock - Send SL command without waiting for command response - This function is unprotected and the caller should make - sure global lock is active. Used to send data within async event handler, where the driver is already locked. -*****************************************************************************/ -_SlReturnVal_t _SlDrvCmdSend_noLock( - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - _u8 WaitForCmdRespOriginalVal; - - _SlFunctionParams_t originalFuncParms; - - /* save the current RespWait flag before clearing it */ - WaitForCmdRespOriginalVal = g_pCB->WaitForCmdResp; - - /* save the current command paramaters */ - sl_Memcpy(&originalFuncParms, &g_pCB->FunctionParams, sizeof(_SlFunctionParams_t)); - - g_pCB->WaitForCmdResp = FALSE; - - SL_TRACE0(DBG_MSG, MSG_312, "_SlDrvCmdSend_noLock: call _SlDrvMsgWrite"); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - - /* restore the original RespWait flag */ - g_pCB->WaitForCmdResp = WaitForCmdRespOriginalVal; - - /* restore the original command paramaters */ - sl_Memcpy(&g_pCB->FunctionParams, &originalFuncParms, sizeof(_SlFunctionParams_t)); - - return RetVal; -} -/***************************************************************************** - _SlDrvCmdSend_noWait - Send SL command without waiting for command response - This function send command form any possiable context, without waiting. -*****************************************************************************/ -_SlReturnVal_t _SlDrvCmdSend_noWait( - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - - _SlFunctionParams_t originalFuncParms; - - SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdSend_noLock: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); - - /* Save the current function parameters */ - sl_Memcpy(&originalFuncParms, &g_pCB->FunctionParams, sizeof(_SlFunctionParams_t)); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - - /* Restore */ - sl_Memcpy(&g_pCB->FunctionParams, &originalFuncParms, sizeof(_SlFunctionParams_t)); - - return RetVal; -} - -/***************************************************************************** - _SlDrvCmdSend - Send SL command without waiting for command response -*****************************************************************************/ -#ifndef SL_TINY -_SlReturnVal_t _SlDrvCmdSend( - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - - _SlDrvObjLockWaitForever(&GlobalLockObj); - - g_pCB->WaitForCmdResp = FALSE; - - SL_TRACE1(DBG_MSG, MSG_312, "_SlDrvCmdSend: call _SlDrvMsgWrite:%x", pCmdCtrl->Opcode); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - - _SlDrvObjUnLock(&GlobalLockObj); - - return RetVal; -} - -#endif - - -/* ***************************************************************************** */ -/* _SlDrvProtectAsyncRespSetting */ -/* ***************************************************************************** */ -_SlReturnVal_t _SlDrvProtectAsyncRespSetting(_u8 *pAsyncRsp, _SlActionID_e ActionID, _u8 SocketID) -{ - _i16 ObjIdx; - - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvWaitForPoolObj(ActionID, SocketID); - - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - else if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return MAX_CONCURRENT_ACTIONS; - } - else - { - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - g_pCB->ObjPool[ObjIdx].pRespArgs = pAsyncRsp; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - - return ObjIdx; -} - - -/* ***************************************************************************** */ -/* _SlDrvIsSpawnOwnGlobalLock */ -/* ***************************************************************************** */ -_u8 _SlDrvIsSpawnOwnGlobalLock() -{ -#ifdef SL_PLATFORM_MULTI_THREADED - _u32 ThreadId = (_i32)pthread_self(); - return _SlInternalIsItSpawnThread(ThreadId); -#else - return (gGlobalLockContextOwner == GLOBAL_LOCK_CONTEXT_OWNER_SPAWN); -#endif -} - -/* ***************************************************************************** */ -/* _SlDrvWaitForPoolObj */ -/* ***************************************************************************** */ -_SlReturnVal_t _SlDrvWaitForPoolObj(_u8 ActionID, _u8 SocketID) -{ - _u8 CurrObjIndex = MAX_CONCURRENT_ACTIONS; - - /* Get free object */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - if (MAX_CONCURRENT_ACTIONS > g_pCB->FreePoolIdx) - { - /* save the current obj index */ - CurrObjIndex = g_pCB->FreePoolIdx; - /* set the new free index */ -#ifndef SL_TINY - if (MAX_CONCURRENT_ACTIONS > g_pCB->ObjPool[CurrObjIndex].NextIndex) - { - g_pCB->FreePoolIdx = g_pCB->ObjPool[CurrObjIndex].NextIndex; - } - else -#endif - { - /* No further free actions available */ - g_pCB->FreePoolIdx = MAX_CONCURRENT_ACTIONS; - } - } - else - { - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return CurrObjIndex; - } - g_pCB->ObjPool[CurrObjIndex].ActionID = (_u8)ActionID; - if (SL_MAX_SOCKETS > SocketID) - { - g_pCB->ObjPool[CurrObjIndex].AdditionalData = SocketID; - } -#ifndef SL_TINY - /*In case this action is socket related, SocketID bit will be on - In case SocketID is set to SL_MAX_SOCKETS, the socket is not relevant to the action. In that case ActionID bit will be on */ - while ( ( (SL_MAX_SOCKETS > SocketID) && (g_pCB->ActiveActionsBitmap & (1<ActiveActionsBitmap & ( MULTI_SELECT_MASK & (1<ObjPool[CurrObjIndex].ActionID = 0; - g_pCB->ObjPool[CurrObjIndex].AdditionalData = SL_MAX_SOCKETS; - g_pCB->FreePoolIdx = CurrObjIndex; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return MAX_CONCURRENT_ACTIONS; - } - /* action in progress - move to pending list */ - g_pCB->ObjPool[CurrObjIndex].NextIndex = g_pCB->PendingPoolIdx; - g_pCB->PendingPoolIdx = CurrObjIndex; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - /* wait for action to be free */ - (void)_SlDrvSyncObjWaitForever(&g_pCB->ObjPool[CurrObjIndex].SyncObj); - if (SL_IS_DEVICE_STOP_IN_PROGRESS) - { - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[CurrObjIndex].SyncObj)); - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - g_pCB->NumOfDeletedSyncObj++; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - /* set params and move to active (remove from pending list at _SlDrvReleasePoolObj) */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - } -#endif - /* mark as active. Set socket as active if action is on socket, otherwise mark action as active */ - if (SL_MAX_SOCKETS > SocketID) - { - g_pCB->ActiveActionsBitmap |= (1<ActiveActionsBitmap |= (1<ObjPool[CurrObjIndex].NextIndex = g_pCB->ActivePoolIdx; - g_pCB->ActivePoolIdx = CurrObjIndex; - - /* unlock */ - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - /* Increment the API in progress counter as this routine is called for every - API, which will be waiting for async event to be released */ - _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_INCREMENT); - - return CurrObjIndex; -} - -/* ******************************************************************************/ -/* _SlDrvReleasePoolObj */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvReleasePoolObj(_u8 ObjIdx) -{ -#ifndef SL_TINY - _u8 PendingIndex; -#endif - - /* Delete sync obj in case stop in progress and return */ - if (SL_IS_DEVICE_STOP_IN_PROGRESS) - { - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[ObjIdx].SyncObj)); - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - g_pCB->NumOfDeletedSyncObj++; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_RET_CODE_OK; - } - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - /* In Tiny mode, there is only one object pool so no pending actions are available */ -#ifndef SL_TINY - /* go over the pending list and release other pending action if needed */ - PendingIndex = g_pCB->PendingPoolIdx; - - while(MAX_CONCURRENT_ACTIONS > PendingIndex) - { - /* In case this action is socket related, SocketID is in use, otherwise will be set to SL_MAX_SOCKETS */ - if ( (g_pCB->ObjPool[PendingIndex].ActionID == g_pCB->ObjPool[ObjIdx].ActionID) && - ( (SL_MAX_SOCKETS == (g_pCB->ObjPool[PendingIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK)) || - ((SL_MAX_SOCKETS > (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)) && ( (g_pCB->ObjPool[PendingIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK) == (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK) ))) ) - { - /* remove from pending list */ - _SlDrvRemoveFromList(&g_pCB->PendingPoolIdx, PendingIndex); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[PendingIndex].SyncObj); - break; - } - PendingIndex = g_pCB->ObjPool[PendingIndex].NextIndex; - } -#endif - - if (SL_MAX_SOCKETS > (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)) - { - /* unset socketID */ - g_pCB->ActiveActionsBitmap &= ~(1<<(g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)); - } - else - { - /* unset actionID */ - g_pCB->ActiveActionsBitmap &= ~(1<ObjPool[ObjIdx].ActionID); - } - - /* delete old data */ - g_pCB->ObjPool[ObjIdx].pRespArgs = NULL; - g_pCB->ObjPool[ObjIdx].ActionID = 0; - g_pCB->ObjPool[ObjIdx].AdditionalData = SL_MAX_SOCKETS; - - /* remove from active list */ - _SlDrvRemoveFromList(&g_pCB->ActivePoolIdx, ObjIdx); - - /* move to free list */ - g_pCB->ObjPool[ObjIdx].NextIndex = g_pCB->FreePoolIdx; - g_pCB->FreePoolIdx = ObjIdx; - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - /* Here we decrement the API in progrees counter as we just released the pool object, - which is held till the API is finished (async event received) */ - _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_DECREMENT); - return SL_RET_CODE_OK; -} - -/* ******************************************************************************/ -/* _SlDrvReleaseAllActivePendingPoolObj */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvReleaseAllActivePendingPoolObj() -{ - _u8 ActiveIndex; - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - /* go over the active list and release each action with error */ - ActiveIndex = g_pCB->ActivePoolIdx; - - while (MAX_CONCURRENT_ACTIONS > ActiveIndex) - { - /* Set error in case sync objects release due to stop device command */ - if (g_pCB->ObjPool[ActiveIndex].ActionID == NETUTIL_CMD_ID) - { - ((_SlNetUtilCmdData_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->Status = SL_RET_CODE_STOP_IN_PROGRESS; - } - else if (g_pCB->ObjPool[ActiveIndex].ActionID == RECV_ID) - { - ((SlSocketResponse_t *)((_SlArgsData_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->pArgs)->StatusOrLen = SL_RET_CODE_STOP_IN_PROGRESS; - } - /* First 2 bytes of all async response holds the status except with NETUTIL_CMD_ID and RECV_ID */ - else - { - ((SlSocketResponse_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->StatusOrLen = SL_RET_CODE_STOP_IN_PROGRESS; - } - /* Signal the pool obj*/ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[ActiveIndex].SyncObj); - ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; - } - - /* go over the pending list and release each action */ - ActiveIndex = g_pCB->PendingPoolIdx; - - while (MAX_CONCURRENT_ACTIONS > ActiveIndex) - { - /* Signal the pool obj*/ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[ActiveIndex].SyncObj); - ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; - } - -#ifndef SL_TINY - /* Delete only unoccupied objects from the Free list, other obj (pending and active) - will be deleted from the relevant context */ - ActiveIndex = g_pCB->FreePoolIdx; - while(MAX_CONCURRENT_ACTIONS > ActiveIndex) -#endif - { - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[ActiveIndex].SyncObj)); - g_pCB->NumOfDeletedSyncObj++; - ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; - } - /* In case trigger select in progress, delete the sync obj */ -#if defined(slcb_SocketTriggerEventHandler) - if (MAX_CONCURRENT_ACTIONS != g_pCB->SocketTriggerSelect.Info.ObjPoolIdx) - { - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[g_pCB->SocketTriggerSelect.Info.ObjPoolIdx].SyncObj)); - g_pCB->NumOfDeletedSyncObj++; - } -#endif - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_RET_CODE_OK; -} - -/* ******************************************************************************/ -/* _SlDrvRemoveFromList */ -/* ******************************************************************************/ -static void _SlDrvRemoveFromList(_u8 *ListIndex, _u8 ItemIndex) -{ -#ifndef SL_TINY - _u8 Idx; -#endif - - if (MAX_CONCURRENT_ACTIONS == g_pCB->ObjPool[*ListIndex].NextIndex) - { - *ListIndex = MAX_CONCURRENT_ACTIONS; - } - /* As MAX_CONCURRENT_ACTIONS is equal to 1 in Tiny mode */ -#ifndef SL_TINY - /* need to remove the first item in the list and therefore update the global which holds this index */ - else if (*ListIndex == ItemIndex) - { - *ListIndex = g_pCB->ObjPool[ItemIndex].NextIndex; - } - else - { - Idx = *ListIndex; - - while(MAX_CONCURRENT_ACTIONS > Idx) - { - /* remove from list */ - if (g_pCB->ObjPool[Idx].NextIndex == ItemIndex) - { - g_pCB->ObjPool[Idx].NextIndex = g_pCB->ObjPool[ItemIndex].NextIndex; - break; - } - - Idx = g_pCB->ObjPool[Idx].NextIndex; - } - } -#endif -} - - -/* ******************************************************************************/ -/* _SlDrvFindAndSetActiveObj */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvFindAndSetActiveObj(_SlOpcode_t Opcode, _u8 Sd) -{ - _u8 ActiveIndex; - - ActiveIndex = g_pCB->ActivePoolIdx; - /* go over the active list if exist to find obj waiting for this Async event */ -#ifndef SL_TINY - while (MAX_CONCURRENT_ACTIONS > ActiveIndex) -#else - /* Only one Active action is availabe in tiny mode, so we can replace the loop with if condition */ - if (MAX_CONCURRENT_ACTIONS > ActiveIndex) -#endif - { - /* unset the Ipv4\IPv6 bit in the opcode if family bit was set */ - if (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) - { - Opcode &= ~SL_OPCODE_IPV6; - } - - if ((g_pCB->ObjPool[ActiveIndex].ActionID == RECV_ID) && (Sd == g_pCB->ObjPool[ActiveIndex].AdditionalData) && - ( (SL_OPCODE_SOCKET_RECVASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE == Opcode) -#ifndef SL_TINY - || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 == Opcode) -#endif - ) - ) - { - g_pCB->FunctionParams.AsyncExt.ActionIndex = ActiveIndex; - return SL_RET_CODE_OK; - } - /* In case this action is socket related, SocketID is in use, otherwise will be set to SL_MAX_SOCKETS */ - if ( (_SlActionLookupTable[ g_pCB->ObjPool[ActiveIndex].ActionID - MAX_SOCKET_ENUM_IDX].ActionAsyncOpcode == Opcode) && - ( ((Sd == (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK) ) && (SL_MAX_SOCKETS > Sd)) || (SL_MAX_SOCKETS == (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK)) ) ) - { - /* set handler */ - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = _SlActionLookupTable[ g_pCB->ObjPool[ActiveIndex].ActionID - MAX_SOCKET_ENUM_IDX].AsyncEventHandler; - g_pCB->FunctionParams.AsyncExt.ActionIndex = ActiveIndex; - return SL_RET_CODE_OK; - } - ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; - } - - return SL_RET_CODE_SELF_ERROR; -} - -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) -void _SlDrvDispatchHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse) -{ - _SlDrvHandleHttpServerEvents (slHttpServerEvent, slHttpServerResponse); -} -#endif - -#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) -void _SlDrvDispatchNetAppRequestEvents(SlNetAppRequest_t *slNetAppRequestEvent, SlNetAppResponse_t *slNetAppResponse) -{ - _SlDrvHandleNetAppRequestEvents (slNetAppRequestEvent, slNetAppResponse); -} -#endif - - -/* Wrappers for the object functions */ -_SlReturnVal_t _SlDrvSyncObjSignal(_SlSyncObj_t *pSyncObj) -{ - OSI_RET_OK_CHECK(sl_SyncObjSignal(pSyncObj)); - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvObjLockWaitForever(_SlLockObj_t *pLockObj) -{ - /* DPL_MG */ - OSI_RET_OK_CHECK(sl_LockObjLock(pLockObj, SL_OS_WAIT_FOREVER)); - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvProtectionObjLockWaitForever(void) -{ - OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER)); - - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvObjUnLock(_SlLockObj_t *pLockObj) -{ - OSI_RET_OK_CHECK(sl_LockObjUnlock(pLockObj)); - - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvProtectionObjUnLock(void) -{ - OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj)); - return SL_OS_RET_CODE_OK; -} - -static _SlReturnVal_t _SlDrvObjGlobalLockWaitForever(_u32 Flags) -{ - _SlReturnVal_t ret; - _u16 Opcode; - _u16 Silo; - _u8 UpdateApiInProgress = (Flags & GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); - _u16 IsProvStopApi = (Flags & GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API); - -#ifndef SL_TINY - if (SL_IS_RESTART_REQUIRED) - { - return SL_API_ABORTED; - } -#endif - - gGlobalLockCntRequested++; - - - ret = sl_LockObjLock(&GlobalLockObj, SL_OS_WAIT_FOREVER); - - /* start/stop device is in progress so return right away */ - if (SL_IS_DEVICE_START_IN_PROGRESS || SL_IS_DEVICE_STOP_IN_PROGRESS || SL_IS_PROVISIONING_IN_PROGRESS) - { - return ret; - } - - /* after the lock acquired check if API is allowed */ - if (0 == ret) - { - - Opcode = (Flags >> 16); - Silo = Opcode & ((0xF << SL_OPCODE_SILO_OFFSET)); - - /* After acquiring the lock, check if there is stop in progress */ - if (Opcode != SL_OPCODE_DEVICE_STOP_COMMAND) - { - _i16 Status = _SlDrvDriverIsApiAllowed(Silo); - - if (Status) - { - sl_LockObjUnlock(&GlobalLockObj); - return Status; - } - } - } - - /* if lock was successfully taken and increment of the API in progress is required */ - if ((0 == ret) && (UpdateApiInProgress)) - { - if (!SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_API_ALLOWED) - { - /* Increment the API in progress counter */ - _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_INCREMENT); - } - /* if we are in provisioning than don't abort the stop provisioning cmd.. */ - else if (FALSE == IsProvStopApi ) - { - /* Provisioning is active so release the lock immediately as - we do not want to allow more APIs to run. */ - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - return SL_RET_CODE_PROVISIONING_IN_PROGRESS; - } - } - - return ret; -} -_SlReturnVal_t _SlDrvGlobalObjUnLock(_u8 bDecrementApiInProgress) -{ - gGlobalLockCntReleased++; - - OSI_RET_OK_CHECK(sl_LockObjUnlock(&GlobalLockObj)); - - if (bDecrementApiInProgress) - { - _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_DECREMENT); - } - - return SL_OS_RET_CODE_OK; -} - -void _SlDrvMemZero(void* Addr, _u16 size) -{ - sl_Memset(Addr, 0, size); -} - - -void _SlDrvResetCmdExt(_SlCmdExt_t* pCmdExt) -{ - _SlDrvMemZero(pCmdExt, (_u16)sizeof (_SlCmdExt_t)); -} - - -#ifdef SL_TINY - -_SlReturnVal_t _SlDrvSyncObjWaitForever(_SlSyncObj_t *pSyncObj) -{ - return sl_SyncObjWait(pSyncObj, SL_OS_WAIT_FOREVER); -} - -#else -_SlReturnVal_t _SlDrvSyncObjWaitForever(_SlSyncObj_t *pSyncObj) -{ - _SlReturnVal_t RetVal = sl_SyncObjWait(pSyncObj, SL_OS_WAIT_FOREVER); - - /* if the wait is finished and we detect that restart is required (we in the middle of error handling), - than we should abort immediately from the current API command execution - */ - if (SL_IS_RESTART_REQUIRED) - { - return SL_API_ABORTED; - } - - return RetVal; -} - -#endif - - -#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) - -void _SlDrvStartMeasureTimeout(_SlTimeoutParams_t *pTimeoutInfo, _u32 TimeoutInMsec) -{ - _SlDrvMemZero(pTimeoutInfo, sizeof (_SlTimeoutParams_t)); - - pTimeoutInfo->Total10MSecUnits = TimeoutInMsec / 10; - pTimeoutInfo->TSPrev = slcb_GetTimestamp(); -} - -_u8 _SlDrvIsTimeoutExpired(_SlTimeoutParams_t *pTimeoutInfo) -{ - _u32 TSCount; - - pTimeoutInfo->TSCurr = slcb_GetTimestamp(); - - if (pTimeoutInfo->TSCurr >= pTimeoutInfo->TSPrev) - { - pTimeoutInfo->DeltaTicks = pTimeoutInfo->TSCurr - pTimeoutInfo->TSPrev; - } - else - { - pTimeoutInfo->DeltaTicks = (SL_TIMESTAMP_MAX_VALUE - pTimeoutInfo->TSPrev) + pTimeoutInfo->TSCurr; - } - - TSCount = pTimeoutInfo->DeltaTicksReminder + pTimeoutInfo->DeltaTicks; - - - if (TSCount > SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) - { - pTimeoutInfo->Total10MSecUnits -= (TSCount / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS); - pTimeoutInfo->DeltaTicksReminder = TSCount % SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS; - - if (pTimeoutInfo->Total10MSecUnits > 0) - { - pTimeoutInfo->TSPrev = pTimeoutInfo->TSCurr; - } - else - { - return TRUE; - } - } - - return FALSE; -} - -#endif - -void _SlDrvHandleFatalError(_u32 errorId, _u32 info1, _u32 info2) -{ - _u8 i; - SlDeviceFatal_t FatalEvent; - - _SlDrvMemZero(&FatalEvent, sizeof(FatalEvent)); - - if (SL_IS_RESTART_REQUIRED) - { - return; - } - - /* set the restart flag */ - SL_SET_RESTART_REQUIRED; - - /* Upon the deletion of the mutex, all thread waiting on this - mutex will return immediately with an error (i.e. MUTEX_DELETED status) */ - (void)sl_LockObjDelete(&GlobalLockObj); - - /* Mark the global lock as deleted */ - g_IsGlobalLockObjInit = 0; - - /* signal all waiting sync objects */ - for (i=0; i< MAX_CONCURRENT_ACTIONS; i++) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[i].SyncObj); - } - - /* prepare the event and notify the user app/ext libraries */ - FatalEvent.Id = errorId; - - switch (errorId) - { - case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: - { - /* set the Abort Type */ - FatalEvent.Data.DeviceAssert.Code = info1; - - /* set the Abort Data */ - FatalEvent.Data.DeviceAssert.Value = info2; - } - break; - - case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: - { - /* set the command opcode */ - FatalEvent.Data.NoCmdAck.Code = info1; - } - break; - - case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: - { - /* set the expected async event opcode */ - FatalEvent.Data.CmdTimeout.Code = info1; - } - break; - - case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: - case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: - /* No Info to transport */ - break; - - } - -#if defined(slcb_DeviceFatalErrorEvtHdlr) || defined (EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) - /* call the registered fatal error handlers */ - _SlDrvHandleFatalErrorEvents(&FatalEvent); -#endif -} - -_SlReturnVal_t _SlDrvSyncObjWaitTimeout(_SlSyncObj_t *pSyncObj, _u32 timeoutVal, _u32 asyncEventOpcode) -{ - _SlReturnVal_t ret = sl_SyncObjWait(pSyncObj, timeoutVal); - - /* if timeout occured...*/ - if (ret) - { - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, asyncEventOpcode, timeoutVal); - return SL_API_ABORTED; - } - else if (SL_IS_RESTART_REQUIRED) - { - return SL_API_ABORTED; - } - - return SL_RET_CODE_OK; -} - - -static void _SlDrvUpdateApiInProgress(_i8 Value) -{ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - g_pCB->ApiInProgressCnt += Value; - - SL_DRV_PROTECTION_OBJ_UNLOCK(); -} - -_i8 _SlDrvIsApiInProgress(void) -{ - if (g_pCB != NULL) - { - return (g_pCB->ApiInProgressCnt > 0); - } - - return TRUE; -} - - -#ifdef slcb_GetTimestamp - -void _SlDrvSleep(_u16 DurationInMsec) -{ - _SlTimeoutParams_t TimeoutInfo={0}; - - _SlDrvStartMeasureTimeout(&TimeoutInfo, DurationInMsec); - - while(!_SlDrvIsTimeoutExpired(&TimeoutInfo)); -} -#endif - -#ifndef SL_PLATFORM_MULTI_THREADED -void _SlDrvSetGlobalLockOwner(_u8 Owner) -{ - gGlobalLockContextOwner = Owner; -} -#endif - - -_SlReturnVal_t _SlDrvWaitForInternalAsyncEvent(_u8 ObjIdx , _u32 Timeout, _SlOpcode_t Opcode) -{ - -#if (defined(SL_PLATFORM_EXTERNAL_SPAWN) || !defined(SL_PLATFORM_MULTI_THREADED)) - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->ObjPool[ObjIdx].SyncObj); - return SL_OS_RET_CODE_OK; -#else - _SlTimeoutParams_t SlTimeoutInfo = { 0 }; - if (_SlDrvIsSpawnOwnGlobalLock()) - { -#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) - _SlDrvStartMeasureTimeout(&SlTimeoutInfo, Timeout); - while (!Timeout || !_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) -#endif - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_NO_WAIT)) - { - return SL_OS_RET_CODE_OK; - } - } - /* if timeout occured...*/ - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, Opcode, Timeout); - return SL_API_ABORTED; - } - else - { - if (Timeout) - { - SL_DRV_SYNC_OBJ_WAIT_TIMEOUT(&g_pCB->ObjPool[ObjIdx].SyncObj, Timeout, Opcode); - } - else - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->ObjPool[ObjIdx].SyncObj); - } - return SL_OS_RET_CODE_OK; - } - -#endif -} - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(SL_MEMORY_MGMT_DYNAMIC)) -_SlAsyncRespBuf_t* _SlGetStatSpawnListItem(_u16 AsyncEventLen) -{ - _u8 Idx = 0; - /* Find free buffer from the pool */ - while (Idx < SL_MAX_ASYNC_BUFFERS) - { - if (0xFF == g_StatMem.AsyncBufPool[Idx].ActionIndex) - { - /* copy buffer */ - return &g_StatMem.AsyncBufPool[Idx]; - } - Idx++; - } - return NULL; -} -#endif - -#if defined(SL_PLATFORM_MULTI_THREADED) -_SlReturnVal_t _SlSpawnMsgListInsert(_u16 AsyncEventLen, _u8 *pAsyncBuf) -{ - _SlReturnVal_t RetVal = SL_OS_RET_CODE_OK; - - /* protect the item insertion */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - -#ifdef SL_MEMORY_MGMT_DYNAMIC - _SlSpawnMsgItem_t* pCurr = NULL; - _SlSpawnMsgItem_t* pItem; - - pItem = (_SlSpawnMsgItem_t*)sl_Malloc(sizeof(_SlSpawnMsgItem_t)); - /* now allocate the buffer itself */ - pItem->Buffer = (void*)sl_Malloc(AsyncEventLen); - pItem->next = NULL; - /* if list is empty point to the allocated one */ - if (g_pCB->spawnMsgList == NULL) - { - g_pCB->spawnMsgList = pItem; - } - else - { - pCurr = g_pCB->spawnMsgList; - /* go to end of list */ - while (pCurr->next != NULL) - { - pCurr = pCurr->next; - } - /* we point to last item in list - add the new one */ - pCurr->next = pItem; - } -#else - _SlAsyncRespBuf_t* pItem = (_SlAsyncRespBuf_t*)_SlGetStatSpawnListItem(AsyncEventLen); -#endif - if (NULL != pItem) - { - /* save the action idx */ - pItem->ActionIndex = g_pCB->FunctionParams.AsyncExt.ActionIndex; - /* save the corresponding AsyncHndlr (if registered) */ - pItem->AsyncHndlr = g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler; - /* copy the async event that we read to the buffer */ - sl_Memcpy(pItem->Buffer, pAsyncBuf, AsyncEventLen); - } - else - { - RetVal = SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR; - } - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return RetVal; -} - -_SlReturnVal_t _SlSpawnMsgListProcess() -{ - -#ifdef SL_MEMORY_MGMT_DYNAMIC - _SlSpawnMsgItem_t* pHead = g_pCB->spawnMsgList; - _SlSpawnMsgItem_t* pCurr = pHead; - _SlSpawnMsgItem_t* pLast = pHead; - - while (pCurr != NULL) - { - /* lock during action */ - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); - /* load the async event params */ - g_pCB->FunctionParams.AsyncExt.ActionIndex = pCurr->ActionIndex; - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = pCurr->AsyncHndlr; - - pLast = pCurr; - pCurr = pCurr->next; - - /* move the list head to point to the next item (or null) */ - g_pCB->spawnMsgList = pCurr; - /* Handle async event: here we are in spawn context, after context - * switch from command context. */ - _SlDrvAsyncEventGenericHandler(FALSE, pLast->Buffer); - - /* free the copied buffer inside the item */ - sl_Free(pLast->Buffer); - - /* free the spawn msg item */ - sl_Free(pLast); - - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - } - -#else - _u8 i; - - for (i = 0; i < SL_MAX_ASYNC_BUFFERS; i++) - { - if (0xFF != g_StatMem.AsyncBufPool[i].ActionIndex) - { - /* lock during action */ - - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); - - /* load the async event params */ - g_pCB->FunctionParams.AsyncExt.ActionIndex = g_StatMem.AsyncBufPool[i].ActionIndex; - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = g_StatMem.AsyncBufPool[i].AsyncHndlr; - - /* Handle async event: here we are in spawn context, after context - * switch from command context. */ - _SlDrvAsyncEventGenericHandler(FALSE, (unsigned char *)&(g_StatMem.AsyncBufPool[i].Buffer)); - - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - g_StatMem.AsyncBufPool[i].ActionIndex = 0xFF; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - } -#endif - return SL_OS_RET_CODE_OK; -} - -_u16 _SlSpawnMsgListGetCount() -{ - _u16 NumOfItems = 0; -#ifdef SL_MEMORY_MGMT_DYNAMIC - _SlSpawnMsgItem_t* pCurr = g_pCB->spawnMsgList; - - /* protect the item insertion */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - while (pCurr != NULL) - { - NumOfItems++; - - pCurr = pCurr->next; - } - SL_DRV_PROTECTION_OBJ_UNLOCK(); - -#else - _u8 i; - /* protect counting parameters */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - for (i = 0; i < SL_MAX_ASYNC_BUFFERS; i++) - { - if (0xFF != g_StatMem.AsyncBufPool[i].ActionIndex) - { - NumOfItems++; - } - } - SL_DRV_PROTECTION_OBJ_UNLOCK(); -#endif - return NumOfItems; -} - - -void _SlFindAndReleasePendingCmd() -{ - /* In case there is no free buffer to store the async event until context switch release the command and return specific error */ - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR; - /* signal pending cmd */ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.h deleted file mode 100755 index bed0d8c6ef9..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.h +++ /dev/null @@ -1,515 +0,0 @@ -/* - * driver.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef __DRIVER_INT_H__ -#define __DRIVER_INT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define TIMEOUT_STATE_EXPIRY (0) -#define TIMEOUT_ONE_MORE_SHOT (1) -#define TIMEOUT_STATE_INIT_VAL (2) - -/* Timeouts for the sync objects */ -#ifndef SL_DRIVER_TIMEOUT_SHORT -#define SL_DRIVER_TIMEOUT_SHORT (10000) /* msec units */ -#endif -#ifndef SL_DRIVER_TIMEOUT_LONG -#define SL_DRIVER_TIMEOUT_LONG (65535) /* msec units */ -#endif - -#define INIT_COMPLETE_TIMEOUT SL_DRIVER_TIMEOUT_LONG -#define STOP_DEVICE_TIMEOUT SL_DRIVER_TIMEOUT_LONG - -#ifndef SYNC_PATTERN_TIMEOUT_IN_MSEC -#define SYNC_PATTERN_TIMEOUT_IN_MSEC (50) /* the sync patttern timeout in milliseconds units */ -#endif -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#ifndef CPU_FREQ_IN_MHZ - #define CPU_FREQ_IN_MHZ (200) -#endif -#define USEC_DELAY (50) - -#define SL_DRV_PROTECTION_OBJ_UNLOCK() (void)_SlDrvProtectionObjUnLock(); -#define SL_DRV_PROTECTION_OBJ_LOCK_FOREVER() (void)_SlDrvProtectionObjLockWaitForever(); -#define SL_DRV_OBJ_UNLOCK(pObj) (void)_SlDrvObjUnLock(pObj); -#define SL_DRV_OBJ_LOCK_FOREVER(pObj) (void)_SlDrvObjLockWaitForever(pObj); -#define SL_DRV_SYNC_OBJ_SIGNAL(pObj) (void)_SlDrvSyncObjSignal(pObj); -#define SL_DRV_SYNC_OBJ_CLEAR(pObj) (void)sl_SyncObjWait(pObj,SL_OS_NO_WAIT); - - -#ifdef SL_TINY -#define SL_DRV_SYNC_OBJ_WAIT_FOREVER(SyncObj) (void)_SlDrvSyncObjWaitForever(SyncObj); -#define SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(Flags) (void)_SlDrvObjGlobalLockWaitForever(Flags); -#define SL_DRV_LOCK_GLOBAL_UNLOCK(bDecrementApiInProgress) (void)_SlDrvGlobalObjUnLock(bDecrementApiInProgress); -#else -#define SL_DRV_SYNC_OBJ_WAIT_FOREVER(SyncObj) { \ -if (SL_API_ABORTED == _SlDrvSyncObjWaitForever(SyncObj)) \ -{ \ - return SL_API_ABORTED; \ -} \ -} -#define SL_DRV_SYNC_OBJ_WAIT_TIMEOUT(SyncObj, timeoutVal, opcode) { \ -if (SL_API_ABORTED == _SlDrvSyncObjWaitTimeout(SyncObj, timeoutVal, opcode)) \ -{ \ - return SL_API_ABORTED; \ -} \ -} -#define SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(Flags) { \ -_SlReturnVal_t retVal; \ - \ -retVal = _SlDrvObjGlobalLockWaitForever(Flags); \ -if (retVal) \ -{ \ - return retVal; \ -} \ -} - -#define SL_DRV_LOCK_GLOBAL_UNLOCK(bDecrementApiInProgress) { \ -_SlReturnVal_t retVal; \ - \ -retVal = _SlDrvGlobalObjUnLock(bDecrementApiInProgress); \ -if (retVal) \ -{ \ - return retVal; \ -} \ -} -#endif - -#define SL_IS_RESTART_REQUIRED (g_SlDeviceStatus & _SL_DRV_STATUS_BIT_RESTART_REQUIRED) /* bit 8 indicates restart is required due to fatal error */ -#define SL_IS_DEVICE_STARTED (g_SlDeviceStatus & _SL_DRV_STATUS_BIT_DEVICE_STARTED) /* bit 9 indicates device is started */ -#define SL_IS_DEVICE_LOCKED (g_SlDeviceStatus & _SL_DEV_STATUS_BIT_LOCKED) /* bits 0-7 devStatus from NWP, bit 2 = device locked */ -#define SL_IS_PROVISIONING_ACTIVE (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE)) /* bits 0-7 devStatus from NWP, bit 3 = provisioning active */ -#define SL_IS_PROVISIONING_INITIATED_BY_USER (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED)) /* bits 0-7 devStatus from NWP, bit 4 = provisioning initiated by the user */ -#define SL_IS_PROVISIONING_API_ALLOWED (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_ENABLE_API)) -#define SL_IS_DEVICE_STOP_IN_PROGRESS (!!(g_SlDeviceStatus & _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS)) -#define SL_IS_DEVICE_START_IN_PROGRESS (!!(g_SlDeviceStatus & _SL_DRV_STATUS_BIT_START_IN_PROGRESS)) - -#define SL_IS_PROVISIONING_IN_PROGRESS (!!(g_SlDeviceStatus & ( _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED | _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE))) -/* Check the following conditions: - 1. Device started - 2. Restart device is not required - 3. Provisioning is active - 4. Provisioning was already initiated by the user - 5. Device is not locked -*/ -#define SL_IS_COMMAND_ALLOWED ((g_SlDeviceStatus & (_SL_DRV_STATUS_BIT_DEVICE_STARTED | \ - _SL_DRV_STATUS_BIT_RESTART_REQUIRED | \ - _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE | \ - _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED | \ - _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS | \ - _SL_DEV_STATUS_BIT_LOCKED)) == 0x200) - -#define SL_SET_RESTART_REQUIRED (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_RESTART_REQUIRED) /* bit 8 indicates restart is required due to fatal error */ -#define SL_UNSET_RESTART_REQUIRED (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_RESTART_REQUIRED)) /* bit 8 indicates restart is required due to fatal error */ -#define SL_SET_DEVICE_STARTED (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_DEVICE_STARTED) /* bit 9 indicates device is started */ -#define SL_UNSET_DEVICE_STARTED (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_DEVICE_STARTED)) /* bit 9 indicates device is started */ - -#define SL_SET_DEVICE_STOP_IN_PROGRESS (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS) /* bit 10 indicates there is stop in progress */ -#define SL_UNSET_DEVICE_STOP_IN_PROGRESS (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_STOP_IN_PROGRESS)) /* bit 10 indicates there is stop in progress */ - -/* Start in progress */ -#define SL_SET_DEVICE_START_IN_PROGRESS (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_START_IN_PROGRESS) /* bit 11 indicates there is start in progress */ -#define SL_UNSET_DEVICE_START_IN_PROGRESS (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_START_IN_PROGRESS)) /* bit 11 indicates there is start in progress */ - - -#define SL_SET_DEVICE_STATUS(x) (g_SlDeviceStatus = ((g_SlDeviceStatus & 0xFF00) | (_u16)x) ) /* bits 0-7 devStatus from NWP */ - -#define _SL_PENDING_RX_MSG(pDriverCB) (RxIrqCnt != (pDriverCB)->RxDoneCnt) - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef struct _SlSpawnMsgItem_s -{ - _SlSpawnEntryFunc_t AsyncHndlr; - _u8 ActionIndex; - void *Buffer; - struct _SlSpawnMsgItem_s *next; -} _SlSpawnMsgItem_t; - - -typedef struct -{ - _u32 TSPrev; - _u32 TSCurr; - _u32 DeltaTicks; - _u32 DeltaTicksReminder; - _i32 Total10MSecUnits; -} _SlTimeoutParams_t; - -typedef struct -{ - _u8 *pAsyncMsgBuff; - _u8 bInCmdContext; -} DeviceEventInfo_t; - -typedef struct -{ - _SlOpcode_t Opcode; - _SlArgSize_t TxDescLen; - _SlArgSize_t RxDescLen; -}_SlCmdCtrl_t; - -typedef struct -{ - _u16 TxPayload1Len; - _u16 TxPayload2Len; - _i16 RxPayloadLen; - _i16 ActualRxPayloadLen; - _u8 *pTxPayload1; - _u8 *pTxPayload2; - _u8 *pRxPayload; -}_SlCmdExt_t; - -typedef struct _SlArgsData_t -{ - _u8 *pArgs; - _u8 *pData; -} _SlArgsData_t; - -typedef struct _SlPoolObj_t -{ - _SlSyncObj_t SyncObj; - _u8 *pRespArgs; - _u8 ActionID; - _u8 AdditionalData; /* use for socketID and one bit which indicate supprt IPV6 or not (1=support, 0 otherwise) */ - _u8 NextIndex; -} _SlPoolObj_t; - -typedef enum -{ - SOCKET_0, - SOCKET_1, - SOCKET_2, - SOCKET_3, - SOCKET_4, - SOCKET_5, - SOCKET_6, - SOCKET_7, - SOCKET_8, - SOCKET_9, - SOCKET_10, - SOCKET_11, - SOCKET_12, - SOCKET_13, - SOCKET_14, - SOCKET_15, - MAX_SOCKET_ENUM_IDX, -#ifndef SL_TINY - ACCEPT_ID = MAX_SOCKET_ENUM_IDX, - CONNECT_ID, -#else - CONNECT_ID = MAX_SOCKET_ENUM_IDX, -#endif -#ifndef SL_TINY - SELECT_ID, -#endif - GETHOSYBYNAME_ID, -#ifndef SL_TINY - GETHOSYBYSERVICE_ID, - PING_ID, - NETAPP_RECEIVE_ID, -#endif - START_STOP_ID, - NETUTIL_CMD_ID, - CLOSE_ID, - START_TLS_ID, - /**********/ - RECV_ID /* Please note!! this member must be the last in this action enum */ -}_SlActionID_e; - -typedef struct _SlActionLookup_t -{ - _u8 ActionID; - _u16 ActionAsyncOpcode; - _SlSpawnEntryFunc_t AsyncEventHandler; - -} _SlActionLookup_t; - -typedef struct -{ - _u8 TxPoolCnt; - _u16 MinTxPayloadSize; - _SlLockObj_t TxLockObj; - _SlSyncObj_t TxSyncObj; -}_SlFlowContCB_t; - -typedef enum -{ - RECV_RESP_CLASS, - CMD_RESP_CLASS, - ASYNC_EVT_CLASS, -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - MULTI_SELECT_RESP_CLASS, -#endif - DUMMY_MSG_CLASS -}_SlRxMsgClass_e; - -typedef struct -{ - _u8 ActionIndex; - _SlSpawnEntryFunc_t AsyncEvtHandler; /* place to write pointer to AsyncEvent handler (calc-ed by Opcode) */ - _SlRxMsgClass_e RxMsgClass; /* type of Rx message */ -} AsyncExt_t; - -typedef _u8 _SlSd_t; - -typedef struct -{ - _SlCmdCtrl_t *pCmdCtrl; - _u8 *pTxRxDescBuff; - _SlCmdExt_t *pCmdExt; - AsyncExt_t AsyncExt; -}_SlFunctionParams_t; - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - -typedef struct SlSelectEntry_t -{ - SlSelectAsyncResponse_t Response; - _u32 TimeStamp; - _u16 readlist; - _u16 writelist; - _u8 ObjIdx; -}_SlSelectEntry_t; - -typedef struct _SlMultiSelectCB_t -{ - _u16 readsds; - _u16 writesds; - _u16 CtrlSockFD; - _u8 ActiveSelect; - _u8 ActiveWaiters; - _BasicResponse_t SelectCmdResp; - _SlSyncObj_t SelectSyncObj; - _SlLockObj_t SelectLockObj; - _SlSelectEntry_t* SelectEntry[MAX_CONCURRENT_ACTIONS]; -}_SlMultiSelectCB_t; - -#else - -typedef enum -{ - SOCK_TRIGGER_READY, - SOCK_TRIGGER_WAITING_FOR_RESP, - SOCK_TRIGGER_RESP_RECEIVED -} _SlSockTriggerState_e; - -typedef struct -{ - _SlSockTriggerState_e State; - _u8 ObjPoolIdx; -} _SlSockTriggerData_t; - -typedef struct -{ - _SlSockTriggerData_t Info; - SlSelectAsyncResponse_t Resp; -} _SlSockTriggerSelect_t; - -#endif - -typedef struct -{ - _SlFd_t FD; - _SlCommandHeader_t TempProtocolHeader; - P_INIT_CALLBACK pInitCallback; - - _SlPoolObj_t ObjPool[MAX_CONCURRENT_ACTIONS]; - _u8 FreePoolIdx; - _u8 PendingPoolIdx; - _u8 ActivePoolIdx; - _u32 ActiveActionsBitmap; - _SlLockObj_t ProtectionLockObj; - - _SlSyncObj_t CmdSyncObj; - _u8 WaitForCmdResp; - _SlFlowContCB_t FlowContCB; - _u8 TxSeqNum; - _u8 RxDoneCnt; - _u16 SocketNonBlocking; - _u16 SocketTXFailure; - /* for stack reduction the parameters are globals */ - _SlFunctionParams_t FunctionParams; - - _u8 ActionIndex; - _i8 ApiInProgressCnt; /* Counts how many APIs are in progress */ - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - /* Multiple Select Control block */ - _SlMultiSelectCB_t MultiSelectCB; -#endif - -#if defined(slcb_SocketTriggerEventHandler) - /* Trigger mode control block */ - _SlSockTriggerSelect_t SocketTriggerSelect; -#endif - -#ifdef SL_MEMORY_MGMT_DYNAMIC - _SlSpawnMsgItem_t *spawnMsgList; -#endif - _u8 NumOfDeletedSyncObj; -}_SlDriverCb_t; - -typedef struct -{ - _SlSpawnEntryFunc_t AsyncHndlr; - _u8 ActionIndex; - _u8 Buffer[SL_ASYNC_MAX_MSG_LEN]; -}_SlAsyncRespBuf_t; - -extern _volatile _u8 RxIrqCnt; - -extern _SlLockObj_t GlobalLockObj; -extern _u16 g_SlDeviceStatus; - -extern _SlDriverCb_t* g_pCB; -extern P_SL_DEV_PING_CALLBACK pPingCallBackFunc; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ -extern _SlReturnVal_t _SlDrvDriverCBInit(void); -extern _SlReturnVal_t _SlDrvDriverCBDeinit(void); -extern _SlReturnVal_t _SlDrvRxIrqHandler(void *pValue); -extern _SlReturnVal_t _SlDrvCmdOp(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDrvCmdSend_noLock(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDrvCmdSend_noWait(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDrvCmdSend(_SlCmdCtrl_t *pCmdCtrl , void *pTxRxDescBuff , _SlCmdExt_t *pCmdExt); -extern _SlReturnVal_t _SlDrvDataReadOp(_SlSd_t Sd, _SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDrvDataWriteOp(_SlSd_t Sd, _SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDeviceHandleAsync_InitComplete(void *pVoidBuf); -extern _SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf); -extern _SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf); -extern _SlReturnVal_t _SlDrvGlobalObjUnLock(_u8 bDecrementApiInProgress); -extern _SlReturnVal_t _SlDrvDriverIsApiAllowed(_u16 Silo); -extern _SlReturnVal_t _SlDrvMsgReadSpawnCtx(void *pValue); -extern void _SlInternalSpawnWaitForEvent(void); -extern void _SlDrvSetGlobalLockOwner(_u8 Owner); -extern _u8 _SlDrvIsSpawnOwnGlobalLock(); -#ifndef SL_TINY -extern _SlReturnVal_t _SlDrvBasicCmd(_SlOpcode_t Opcode); -extern _SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf); -extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf); -extern _SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf); -extern _SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf); -extern _SlReturnVal_t _SlDrvReleaseAllActivePendingPoolObj(); - -#ifdef slcb_GetTimestamp -extern void _SlDrvStartMeasureTimeout(_SlTimeoutParams_t *pTimeoutInfo, _u32 TimeoutInMsec); -extern _u8 _SlDrvIsTimeoutExpired(_SlTimeoutParams_t *pTimeoutInfo); -extern void _SlDrvSleep(_u16 DurationInMsec); -#endif - -#endif - -#if defined(SL_PLATFORM_MULTI_THREADED) -extern void * pthread_self(void); -#endif - -extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf); -extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByAddr(void *pVoidBuf); -extern _SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf); -extern _SlReturnVal_t _SlNetAppEventHandler(void* pArgs); - -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) -extern void _SlDrvDispatchHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse); -#endif - -#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) -extern void _SlDrvDispatchNetAppRequestEvents(SlNetAppRequest_t *slNetAppRequestEvent, SlNetAppResponse_t *slNetAppResponse); -#endif - -extern void _SlDeviceHandleAsync_Stop(void *pVoidBuf); -extern void _SlNetUtilHandleAsync_Cmd(void *pVoidBuf); -extern _SlReturnVal_t _SlDrvWaitForPoolObj(_u8 ActionID, _u8 SocketID); -extern _SlReturnVal_t _SlDrvReleasePoolObj(_u8 pObj); -extern void _SlDrvReleaseAllPendingPoolObj(); -extern _SlReturnVal_t _SlDrvAlignSize(_u16 msgLen); -extern _SlReturnVal_t _SlDrvProtectAsyncRespSetting(_u8 *pAsyncRsp, _SlActionID_e ActionID, _u8 SocketID); -extern void _SlNetAppHandleAsync_NetAppReceive(void *pVoidBuf); - - -extern _SlReturnVal_t _SlDeviceEventHandler(void* pEventInfo); -extern _SlReturnVal_t _SlDrvSyncObjWaitForever(_SlSyncObj_t *pSyncObj); -extern _SlReturnVal_t _SlDrvObjLockWaitForever(_SlLockObj_t *pLockObj); -extern _SlReturnVal_t _SlDrvSyncObjWaitTimeout(_SlSyncObj_t *pSyncObj, - _u32 timeoutVal, - _u32 asyncEventOpcode); - -extern _SlReturnVal_t _SlDrvSyncObjSignal(_SlSyncObj_t *pSyncObj); -extern _SlReturnVal_t _SlDrvObjLock(_SlLockObj_t *pLockObj, _SlTime_t Timeout); -extern _SlReturnVal_t _SlDrvProtectionObjLockWaitForever(void); -extern _SlReturnVal_t _SlDrvObjUnLock(_SlLockObj_t *pLockObj); -extern _SlReturnVal_t _SlDrvProtectionObjUnLock(void); - -extern void _SlDrvMemZero(void* Addr, _u16 size); -extern void _SlDrvResetCmdExt(_SlCmdExt_t* pCmdExt); - -extern _i8 _SlDrvIsApiInProgress(void); -extern void _SlDrvHandleResetRequest(const void* pIfHdl, _i8* pDevName); -extern _SlReturnVal_t _SlDrvWaitForInternalAsyncEvent(_u8 ObjIdx, _u32 Timeout, _SlOpcode_t Opcode); -extern _SlReturnVal_t _SlSpawnMsgListInsert(_u16 AsyncEventLen, _u8 *pAsyncBuf); -extern _SlReturnVal_t _SlSpawnMsgListProcess(void); -extern _u16 _SlSpawnMsgListGetCount(void); -#ifndef SL_TINY -extern void _SlDrvHandleFatalError(_u32 errorId, _u32 info1, _u32 info2); -extern void _SlDrvHandleAssert(void); -extern void _SlFindAndReleasePendingCmd(); -#endif - -#define _SL_PROTOCOL_ALIGN_SIZE(msgLen) (((msgLen)+3) & (~3)) -#define _SL_IS_PROTOCOL_ALIGNED_SIZE(msgLen) (!((msgLen) & 3)) - - -#define _SL_PROTOCOL_CALC_LEN(pCmdCtrl,pCmdExt) ((pCmdExt) ? \ - (_SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen) + _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload1Len + pCmdExt->TxPayload2Len)) : \ - (_SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen))) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __DRIVER_INT_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.c deleted file mode 100755 index 5bdf01552af..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * flowcont.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include - - -/*****************************************************************************/ -/* _SlDrvFlowContInit */ -/*****************************************************************************/ -void _SlFlowContSet(void *pVoidBuf) -{ - SlDeviceFlowCtrlAsyncEvent_t *pFlowCtrlAsyncEvent = (SlDeviceFlowCtrlAsyncEvent_t *)_SL_RESP_ARGS_START(pVoidBuf); - - if (pFlowCtrlAsyncEvent->MinTxPayloadSize != 0) - { - g_pCB->FlowContCB.MinTxPayloadSize = pFlowCtrlAsyncEvent->MinTxPayloadSize; - } - -} - - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.h deleted file mode 100755 index 24670a6d4f5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * flowcont.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef __FLOWCONT_H__ -#define __FLOWCONT_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#define FLOW_CONT_MIN 2 - -extern void _SlFlowContSet(void *pVoidBuf); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __FLOWCONT_H__ */ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/fs.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/fs.c deleted file mode 100755 index 368d5049161..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/fs.c +++ /dev/null @@ -1,832 +0,0 @@ -/* - * fs.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#define sl_min(a,b) (((a) < (b)) ? (a) : (b)) -#define MAX_NVMEM_CHUNK_SIZE 1456 /*should be 16 bytes align, because of encryption data*/ - -/*****************************************************************************/ -/* Internal functions */ -/*****************************************************************************/ - -#ifndef SL_TINY -static _u16 _SlFsStrlen(const _u8 *buffer); - -static _u32 FsGetCreateFsMode(_u8 Mode, _u32 MaxSizeInBytes,_u32 AccessFlags); - -/*****************************************************************************/ -/* _SlFsStrlen */ -/*****************************************************************************/ -static _u16 _SlFsStrlen(const _u8 *buffer) -{ - _u16 len = 0; - if( buffer != NULL ) - { - while(*buffer++) len++; - } - return len; -} -#endif -/*****************************************************************************/ -/* _SlFsGetCreateFsMode */ -/*****************************************************************************/ - -/* Convert the user flag to the file System flag */ -#define FS_CONVERT_FLAGS( ModeAndMaxSize ) (((_u32)ModeAndMaxSize & SL_FS_OPEN_FLAGS_BIT_MASK)>>SL_NUM_OF_MAXSIZE_BIT) - -typedef enum -{ - FS_MODE_OPEN_READ = 0, - FS_MODE_OPEN_WRITE, - FS_MODE_OPEN_CREATE, - FS_MODE_OPEN_WRITE_CREATE_IF_NOT_EXIST -}FsFileOpenAccessType_e; - -#define FS_MODE_ACCESS_RESERVED_OFFSET (27) -#define FS_MODE_ACCESS_RESERVED_MASK (0x1F) -#define FS_MODE_ACCESS_FLAGS_OFFSET (16) -#define FS_MODE_ACCESS_FLAGS_MASK (0x7FF) -#define FS_MODE_ACCESS_OFFSET (12) -#define FS_MODE_ACCESS_MASK (0xF) -#define FS_MODE_OPEN_SIZE_GRAN_OFFSET (8) -#define FS_MODE_OPEN_SIZE_GRAN_MASK (0xF) -#define FS_MODE_OPEN_SIZE_OFFSET (0) -#define FS_MODE_OPEN_SIZE_MASK (0xFF) -#define FS_MAX_MODE_SIZE (0xFF) - -/* SizeGran is up to 4 bit , Size can be up to 8 bit */ -#define FS_MODE(Access, SizeGran, Size,Flags) (_u32)(((_u32)((Access) &FS_MODE_ACCESS_MASK)<= MaxSizeInBytes ) - break; - } - granNum = MaxSizeInBytes/granTable[granIdx]; - if( MaxSizeInBytes % granTable[granIdx] != 0 ) - granNum++; - - return (_u32)FS_MODE( Mode, granIdx, granNum, AccessFlags ); - -} - -#endif - -/*****************************************************************************/ -/* API functions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* sl_FsOpen */ -/*****************************************************************************/ -typedef union -{ - SlFsOpenCommand_t Cmd; - SlFsOpenResponse_t Rsp; -}_SlFsOpenMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsOpen) - -static const _SlCmdCtrl_t _SlFsOpenCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEOPEN, - (_SlArgSize_t)sizeof(SlFsOpenCommand_t), - (_SlArgSize_t)sizeof(SlFsOpenResponse_t) -}; - -_i32 sl_FsOpen(const _u8 *pFileName,const _u32 ModeAndMaxSize, _u32 *pToken) -{ - - _SlFsOpenMsg_u Msg; - _SlCmdExt_t CmdExt; - _i32 FileHandle; - _u32 MaxSizeInBytes; - _u32 OpenMode; - _u8 CreateMode; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ - CmdExt.pTxPayload1 = (_u8*)pFileName; - - OpenMode = ModeAndMaxSize & SL_FS_OPEN_MODE_BIT_MASK; - - /*convert from the interface flags to the device flags*/ - if( OpenMode == SL_FS_READ ) - { - Msg.Cmd.Mode = FS_MODE(FS_MODE_OPEN_READ, 0, 0, 0); - } - else if (( OpenMode == SL_FS_WRITE ) ||( OpenMode == SL_FS_OVERWRITE)) - { - Msg.Cmd.Mode = FS_MODE(FS_MODE_OPEN_WRITE, 0, 0, FS_CONVERT_FLAGS ( ModeAndMaxSize)); - } - /* one of the creation mode */ - else if ( ( OpenMode == (SL_FS_CREATE | SL_FS_OVERWRITE )) || ( OpenMode == SL_FS_CREATE) ||(OpenMode == (SL_FS_CREATE | SL_FS_WRITE ))) - { - /* test that the size is correct */ - MaxSizeInBytes = (ModeAndMaxSize & SL_FS_OPEN_MAXSIZE_BIT_MASK) * 256; - if (MaxSizeInBytes > 0xFF0000 ) - { - return SL_ERROR_FS_FILE_MAX_SIZE_EXCEEDED; - } - - CreateMode = ((OpenMode == (SL_FS_CREATE | SL_FS_OVERWRITE )) ? FS_MODE_OPEN_WRITE_CREATE_IF_NOT_EXIST : FS_MODE_OPEN_CREATE ); - - Msg.Cmd.Mode = FsGetCreateFsMode( CreateMode ,MaxSizeInBytes, FS_CONVERT_FLAGS ( ModeAndMaxSize) ); - } - else - { - return SL_ERROR_FS_INVALID_FILE_MODE; - } - - if(pToken != NULL) - { - Msg.Cmd.Token = *pToken; - } - else - { - Msg.Cmd.Token = 0; - } - - _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsOpenCmdCtrl, &Msg, &CmdExt); - FileHandle = (_i32)Msg.Rsp.FileHandle; - if (pToken != NULL) - { - *pToken = Msg.Rsp.Token; - } - - /* in case of an error, return the erros file handler as an error code */ - return FileHandle; -} -#endif - -/*****************************************************************************/ -/* sl_FsClose */ -/*****************************************************************************/ -typedef union -{ - SlFsCloseCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlFsCloseMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsClose) - -static const _SlCmdCtrl_t _SlFsCloseCmdCtrl = -{ - SL_OPCODE_NVMEM_FILECLOSE, - (_SlArgSize_t)sizeof(SlFsCloseCommand_t), - (_SlArgSize_t)sizeof(SlFsCloseResponse_t) -}; - -_i16 sl_FsClose(const _i32 FileHdl, const _u8* pCeritificateFileName,const _u8* pSignature ,const _u32 SignatureLen) -{ - _SlFsCloseMsg_u Msg; - _SlCmdExt_t ExtCtrl; - - _SlDrvMemZero(&Msg, (_u16)sizeof(SlFsCloseCommand_t)); - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - Msg.Cmd.FileHandle = (_u32)FileHdl; - if( pCeritificateFileName != NULL ) - { - Msg.Cmd.CertificFileNameLength = (_u32)((_SlFsStrlen(pCeritificateFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ - } - Msg.Cmd.SignatureLen = SignatureLen; - - _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); - - ExtCtrl.TxPayload1Len = (_u16)(((SignatureLen+3) & (~3))); /* align */ - ExtCtrl.pTxPayload1 = (_u8*)pSignature; - ExtCtrl.RxPayloadLen = (_i16)Msg.Cmd.CertificFileNameLength; - ExtCtrl.pRxPayload = (_u8*)pCeritificateFileName; /* Add signature */ - - if(ExtCtrl.pRxPayload != NULL && ExtCtrl.RxPayloadLen != 0) - { - ExtCtrl.RxPayloadLen = ExtCtrl.RxPayloadLen * (-1); - } - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsCloseCmdCtrl, &Msg, &ExtCtrl)); - - return (_i16)((_i16)Msg.Rsp.status); -} -#endif - - -/*****************************************************************************/ -/* sl_FsRead */ -/*****************************************************************************/ -typedef union -{ - SlFsReadCommand_t Cmd; - SlFsReadResponse_t Rsp; -}_SlFsReadMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsRead) - -static const _SlCmdCtrl_t _SlFsReadCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEREADCOMMAND, - (_SlArgSize_t)sizeof(SlFsReadCommand_t), - (_SlArgSize_t)sizeof(SlFsReadResponse_t) -}; - -_i32 sl_FsRead(const _i32 FileHdl,_u32 Offset, _u8* pData,_u32 Len) -{ - _SlFsReadMsg_u Msg; - _SlCmdExt_t ExtCtrl; - _u16 ChunkLen; - _SlReturnVal_t RetVal =0; - _i32 RetCount = 0; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); - - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); - ExtCtrl.RxPayloadLen = (_i16)ChunkLen; - ExtCtrl.pRxPayload = (_u8 *)(pData); - Msg.Cmd.Offset = Offset; - Msg.Cmd.Len = ChunkLen; - Msg.Cmd.FileHandle = (_u32)FileHdl; - do - { - RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsReadCmdCtrl, &Msg, &ExtCtrl); - if(SL_OS_RET_CODE_OK == RetVal) - { - if( Msg.Rsp.status < 0) - { - if( RetCount > 0) - { - return RetCount; - } - else - { - return Msg.Rsp.status; - } - } - RetCount += (_i32)Msg.Rsp.status; - Len -= ChunkLen; - Offset += ChunkLen; - Msg.Cmd.Offset = Offset; - ExtCtrl.pRxPayload += ChunkLen; - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); - ExtCtrl.RxPayloadLen = (_i16)ChunkLen; - Msg.Cmd.Len = ChunkLen; - Msg.Cmd.FileHandle = (_u32)FileHdl; - } - else - { - return RetVal; - } - }while(ChunkLen > 0); - - return (_i32)RetCount; -} -#endif - -/*****************************************************************************/ -/* sl_FsWrite */ -/*****************************************************************************/ -typedef union -{ - SlFsWriteCommand_t Cmd; - SlFsWriteResponse_t Rsp; -}_SlFsWriteMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsWrite) - -static const _SlCmdCtrl_t _SlFsWriteCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEWRITECOMMAND, - (_SlArgSize_t)sizeof(SlFsWriteCommand_t), - (_SlArgSize_t)sizeof(SlFsWriteResponse_t) -}; - -_i32 sl_FsWrite(const _i32 FileHdl,_u32 Offset, _u8* pData,_u32 Len) -{ - _SlFsWriteMsg_u Msg; - _SlCmdExt_t ExtCtrl; - _u16 ChunkLen; - _SlReturnVal_t RetVal; - _i32 RetCount = 0; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); - - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); - ExtCtrl.TxPayload1Len = ChunkLen; - ExtCtrl.pTxPayload1 = (_u8 *)(pData); - Msg.Cmd.Offset = Offset; - Msg.Cmd.Len = ChunkLen; - Msg.Cmd.FileHandle = (_u32)FileHdl; - - do - { - RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsWriteCmdCtrl, &Msg, &ExtCtrl); - if(SL_OS_RET_CODE_OK == RetVal) - { - if( Msg.Rsp.status < 0) - { - if( RetCount > 0) - { - return RetCount; - } - else - { - return Msg.Rsp.status; - } - } - - RetCount += (_i32)Msg.Rsp.status; - Len -= ChunkLen; - Offset += ChunkLen; - Msg.Cmd.Offset = Offset; - ExtCtrl.pTxPayload1 += ChunkLen; - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); - ExtCtrl.TxPayload1Len = ChunkLen; - Msg.Cmd.Len = ChunkLen; - Msg.Cmd.FileHandle = (_u32)FileHdl; - } - else - { - return RetVal; - } - }while(ChunkLen > 0); - - return (_i32)RetCount; -} -#endif - -/*****************************************************************************/ -/* sl_FsGetInfo */ -/*****************************************************************************/ -typedef union -{ - SlFsGetInfoCommand_t Cmd; - SlFsGetInfoResponse_t Rsp; -}_SlFsGetInfoMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsGetInfo) - -static const _SlCmdCtrl_t _SlFsGetInfoCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEGETINFOCOMMAND, - (_SlArgSize_t)sizeof(SlFsGetInfoCommand_t), - (_SlArgSize_t)sizeof(SlFsGetInfoResponse_t) -}; - -const _u16 FlagsTranslate[] = -{ - SL_FS_INFO_OPEN_WRITE, - SL_FS_INFO_OPEN_READ, - SL_FS_INFO_NOT_FAILSAFE, - SL_FS_INFO_NOT_VALID, - SL_FS_INFO_SYS_FILE, - SL_FS_INFO_MUST_COMMIT, - SL_FS_INFO_BUNDLE_FILE, - SL_FS_INFO_PENDING_COMMIT, - SL_FS_INFO_PENDING_BUNDLE_COMMIT, - 0, - SL_FS_INFO_SECURE, - SL_FS_INFO_NOSIGNATURE, - SL_FS_INFO_PUBLIC_WRITE, - SL_FS_INFO_PUBLIC_READ, - 0, - 0 -}; - -_i16 sl_FsGetInfo(const _u8 *pFileName,const _u32 Token,SlFsFileInfo_t* pFsFileInfo) -{ - _SlFsGetInfoMsg_u Msg; - _SlCmdExt_t CmdExt; - _u16 BitNum; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ - CmdExt.pTxPayload1 = (_u8*)pFileName; - - Msg.Cmd.Token = Token; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsGetInfoCmdCtrl, &Msg, &CmdExt)); - - /* convert flags */ - pFsFileInfo->Flags = 0; - for (BitNum = 0; BitNum < 16; BitNum++ ) - { - if (( Msg.Rsp.Flags >> BitNum) & 0x1 ) - { - pFsFileInfo->Flags |= FlagsTranslate[BitNum]; - } - } - - pFsFileInfo->Len = Msg.Rsp.FileLen; - pFsFileInfo->MaxSize = Msg.Rsp.AllocatedLen; - pFsFileInfo->Token[0] = Msg.Rsp.Token[0]; - pFsFileInfo->Token[1] = Msg.Rsp.Token[1]; - pFsFileInfo->Token[2] = Msg.Rsp.Token[2]; - pFsFileInfo->Token[3] = Msg.Rsp.Token[3]; - pFsFileInfo->StorageSize = Msg.Rsp.FileStorageSize; - pFsFileInfo->WriteCounter = Msg.Rsp.FileWriteCounter; - - return (_i16)((_i16)Msg.Rsp.Status); -} -#endif - -/*****************************************************************************/ -/* sl_FsDel */ -/*****************************************************************************/ -typedef union -{ - SlFsDeleteCommand_t Cmd; - SlFsDeleteResponse_t Rsp; -}_SlFsDeleteMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_FsDel) - -static const _SlCmdCtrl_t _SlFsDeleteCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEDELCOMMAND, - (_SlArgSize_t)sizeof(SlFsDeleteCommand_t), - (_SlArgSize_t)sizeof(SlFsDeleteResponse_t) -}; - -_i16 sl_FsDel(const _u8 *pFileName,const _u32 Token) -{ - _SlFsDeleteMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ - CmdExt.pTxPayload1 = (_u8*)pFileName; - Msg.Cmd.Token = Token; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsDeleteCmdCtrl, &Msg, &CmdExt)); - - return (_i16)((_i16)Msg.Rsp.status); -} -#endif - -/*****************************************************************************/ -/* sl_FsCtl */ -/*****************************************************************************/ -typedef union -{ - SlFsFileSysControlCommand_t Cmd; - SlFsFileSysControlResponse_t Rsp; -}_SlFsFileSysControlMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsCtl) - -const _SlCmdCtrl_t _SlFsFileSysControlCmdCtrl = -{ - SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLCOMMAND, - sizeof(SlFsFileSysControlCommand_t), - sizeof(SlFsFileSysControlResponse_t) -}; - -_i32 sl_FsCtl( SlFsCtl_e Command, _u32 Token, _u8 *pFileName, const _u8 *pData, _u16 DataLen, _u8 *pOutputData, _u16 OutputDataLen,_u32 *pNewToken ) -{ - _SlFsFileSysControlMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - Msg.Cmd.Token = Token; - Msg.Cmd.Operation = (_u8)Command; - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - if ((SL_FS_CTL_ROLLBACK == Command) || (SL_FS_CTL_COMMIT == Command )) - { - Msg.Cmd.FileNameLength = _SlFsStrlen(pFileName) + 1 ; - - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - /*the data is aligned*/ - CmdExt.RxPayloadLen = DataLen; - CmdExt.pRxPayload = (_u8 *)(pData); - - CmdExt.TxPayload1Len = (_SlFsStrlen(pFileName) + 4) & (~3); - CmdExt.pTxPayload1 = pFileName; - - Msg.Cmd.BufferLength = CmdExt.RxPayloadLen + CmdExt.TxPayload1Len; - - if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) - { - CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); - } - } - else if( SL_FS_CTL_RENAME == Command ) - { - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - Msg.Cmd.FileNameLength = (_SlFsStrlen(pFileName) + 4) & (~3); - - /*current file name*/ - CmdExt.RxPayloadLen = (_u16)Msg.Cmd.FileNameLength; - CmdExt.pRxPayload = pFileName; - - /*New file name*/ - CmdExt.TxPayload1Len = (_SlFsStrlen(pData) + 4) & (~3);; - CmdExt.pTxPayload1 = (_u8 *)(pData); - - Msg.Cmd.BufferLength = CmdExt.RxPayloadLen + CmdExt.TxPayload1Len; - - if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) - { - CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); - } - } - else - { - Msg.Cmd.FileNameLength = 0; - - CmdExt.TxPayload1Len = (DataLen + 3) & (~3); - CmdExt.pTxPayload1 = (_u8 *)(pData); - - CmdExt.RxPayloadLen = OutputDataLen; - CmdExt.pRxPayload = pOutputData; - - Msg.Cmd.BufferLength = CmdExt.TxPayload1Len; - } - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsFileSysControlCmdCtrl, &Msg, &CmdExt)); - - if( pNewToken != NULL ) - { - *pNewToken = Msg.Rsp.Token; - } - - return (_i32)((_i32)Msg.Rsp.Status); -} -#endif - - -/*****************************************************************************/ -/* sl_FsProgram */ -/*****************************************************************************/ -typedef union -{ - SlFsProgramCommand_t Cmd; - SlFsProgramResponse_t Rsp; -}_SlFsProgrammingMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsProgram) - -const _SlCmdCtrl_t _SlFsProgrammingCmdCtrl = -{ - SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND, - sizeof(SlFsProgramCommand_t), - sizeof(SlFsProgramResponse_t) -}; - -_i32 sl_FsProgram(const _u8* pData , _u16 DataLen ,const _u8 * pKey , _u32 Flags ) -{ - _SlFsProgrammingMsg_u Msg; - _SlCmdExt_t CmdExt; - _u16 ChunkLen; - - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - Msg.Cmd.Flags = (_u32)Flags; - - _SlDrvResetCmdExt(&CmdExt); - - /* no data and no key, called only for extracting the image */ - if( (DataLen == 0) && (pKey == NULL) ) - { - Msg.Cmd.ChunkLen = 0; - Msg.Cmd.KeyLen = 0; - Msg.Cmd.Flags = Flags; - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); - } - else if( (DataLen> 0) && ( pData == NULL)) - { - //return( ((_i32)SL_ERROR_FS_WRONG_INPUT_SIZE) << 16 ); - // Remove warning - return (_i16)( ((_u32)SL_ERROR_FS_WRONG_INPUT_SIZE) << 16 ); - } - else if( (DataLen == 0) && (pKey != NULL) ) - { - Msg.Cmd.ChunkLen = 0; - Msg.Cmd.KeyLen = sizeof(SlFsKey_t);; - Msg.Cmd.Flags = Flags; - CmdExt.pTxPayload1 = (_u8*)pKey; - CmdExt.TxPayload1Len = sizeof(SlFsKey_t); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); - } - else /* DataLen > 0 */ - { - if( (DataLen & 0xF) > 0) - { - return (_i32)(((_u32)SL_ERROR_FS_NOT_16_ALIGNED) << 16 ); - } - Msg.Cmd.Flags = Flags; - - CmdExt.pTxPayload1 = (_u8 *)pData; - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE, DataLen); - - while(ChunkLen > 0) - { - Msg.Cmd.ChunkLen = ChunkLen; - CmdExt.TxPayload1Len = ChunkLen; - if( pKey != NULL ) - { - Msg.Cmd.KeyLen = sizeof(SlFsKey_t); - CmdExt.RxPayloadLen = sizeof(SlFsKey_t); - CmdExt.pRxPayload = (_u8 *)pKey; - - if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) - { - CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); - } - } - else /* No key */ - { - Msg.Cmd.KeyLen = 0; - CmdExt.RxPayloadLen = 0; - CmdExt.pRxPayload = NULL; - } - - VERIFY_RET_OK( _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); - - if( Msg.Rsp.Status <= 0 ) /* Error or finished */ - { - return (_i32)(Msg.Rsp.Status); - } - - DataLen -= ChunkLen; - CmdExt.pTxPayload1 += ChunkLen; - - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE, DataLen); - } - } - - return (_i32)(Msg.Rsp.Status); -} -#endif - -/*****************************************************************************/ -/* sl_FsGetFileList */ -/*****************************************************************************/ -typedef union -{ - SlFsGetFileListCommand_t Cmd; - SlFsGetFileListResponse_t Rsp; -}_SlFsGetFileListMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsGetFileList) - -const _SlCmdCtrl_t _SlFsGetFileListCmdCtrl = -{ - SL_OPCODE_NVMEM_NVMEMGETFILELISTCOMMAND, - sizeof(SlFsGetFileListCommand_t), - sizeof(SlFsGetFileListResponse_t) -}; - -_i32 sl_FsGetFileList(_i32* pIndex, _u8 Count, _u8 MaxEntryLen , _u8* pBuff, SlFileListFlags_t Flags ) -{ - _SlFsGetFileListMsg_u Msg; - _SlCmdExt_t CmdExt; - _u16 OutputBufferSize; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvResetCmdExt(&CmdExt); - - Msg.Cmd.Index = *pIndex; - Msg.Cmd.MaxEntryLen = MaxEntryLen & (~3); /* round to modulu 4 */ - Msg.Cmd.Count = Count; - Msg.Cmd.Flags = (_u8)Flags; - - OutputBufferSize = Msg.Cmd.Count * Msg.Cmd.MaxEntryLen; - if( OutputBufferSize > MAX_NVMEM_CHUNK_SIZE ) - { - return SL_ERROR_FS_WRONG_INPUT_SIZE; - } - - CmdExt.RxPayloadLen = OutputBufferSize; - CmdExt.pRxPayload = pBuff; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsGetFileListCmdCtrl, &Msg, &CmdExt)); - - *pIndex = Msg.Rsp.Index; - - return (_i32)((_i32)Msg.Rsp.NumOfEntriesOrError); -} -#endif - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netapp.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netapp.c deleted file mode 100755 index 78c404d6b6d..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netapp.c +++ /dev/null @@ -1,1669 +0,0 @@ -/* - * netapp.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Functions prototypes */ -/*****************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf); - -#ifndef SL_TINY -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf); -_SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf); -static void _SlNetAppCopyPingResultsToReport(SlPingReportResponse_t *pResults,SlNetAppPingReport_t *pReport); -#endif - -_i16 _SlNetAppMDNSRegisterUnregisterService(const _i8* pServiceName, - const _u8 ServiceNameLen, - const _i8* pText, - const _u8 TextLen, - const _u16 Port, - const _u32 TTL, - const _u32 Options); - - -_u16 _SlNetAppSendTokenValue(SlNetAppHttpServerData_t * Token); - -_u16 _SlNetAppSendResponse( _u16 handle, SlNetAppResponse_t *NetAppResponse); - -#define SL_NETAPP_SERVICE_SIZE_MASK (0x7) -#define SL_NETAPP_PING_GUARD_INTERVAL (20000) - -static _u16 NetAppServiceSizeLUT[] = -{ - (_u16)sizeof(_BasicResponse_t), /* 0 - Default value */ - (_u16)sizeof(SlNetAppGetFullServiceWithTextIpv4List_t), /* 1 - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE */ - (_u16)sizeof(SlNetAppGetFullServiceIpv4List_t), /* 2 - SL_NETAPP_FULL_SERVICE_IPV4_TYPE */ - (_u16)sizeof(SlNetAppGetShortServiceIpv4List_t), /* 3 - SL_NETAPP_SHORT_SERVICE_IPV4_TYPE */ - (_u16)sizeof(SlNetAppGetFullServiceWithTextIpv6List_t), /* 4 - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE */ - (_u16)sizeof(SlNetAppGetFullServiceIpv6List_t), /* 5 - SL_NETAPP_FULL_SERVICE_IPV6_TYPE */ - (_u16)sizeof(SlNetAppGetShortServiceIpv6List_t), /* 6 - SL_NETAPP_SHORT_SERVICE_IPV6_TYPE */ - (_u16)sizeof(_BasicResponse_t), /* 7 - Default value */ -}; - -typedef union -{ - _NetAppStartStopCommand_t Cmd; - _NetAppStartStopResponse_t Rsp; -}_SlNetAppStartStopMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_NetAppStart) - -static const _SlCmdCtrl_t _SlNetAppStartCtrl = -{ - SL_OPCODE_NETAPP_START_COMMAND, - (_SlArgSize_t)sizeof(_NetAppStartStopCommand_t), - (_SlArgSize_t)sizeof(_NetAppStartStopResponse_t) -}; - -_i16 sl_NetAppStart(const _u32 AppBitMap) -{ - _SlNetAppStartStopMsg_u Msg; - Msg.Cmd.AppId = AppBitMap; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppStartCtrl, &Msg, NULL)); - - return Msg.Rsp.status; -} -#endif - -/***************************************************************************** - sl_NetAppStop -*****************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_NetAppStop) - -static const _SlCmdCtrl_t _SlNetAppStopCtrl = -{ - SL_OPCODE_NETAPP_STOP_COMMAND, - (_SlArgSize_t)sizeof(_NetAppStartStopCommand_t), - (_SlArgSize_t)sizeof(_NetAppStartStopResponse_t) -}; - -_i16 sl_NetAppStop(const _u32 AppBitMap) -{ - _SlNetAppStartStopMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - Msg.Cmd.AppId = AppBitMap; - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppStopCtrl, &Msg, NULL)); - - return Msg.Rsp.status; -} -#endif - - -/***************************************************************************** - sl_NetAppArpFlush -*****************************************************************************/ - -#if _SL_INCLUDE_FUNC(sl_NetAppArpFlush) - - -_i16 sl_NetAppArpFlush(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - return _SlDrvBasicCmd(SL_OPCODE_NETAPP_ARPFLUSH); -} -#endif - -/***************************************************************************** - sl_NetAppNdFlush -*****************************************************************************/ - -#if _SL_INCLUDE_FUNC(sl_NetAppNdFlush) - - -_i16 sl_NetAppNdFlush(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - return _SlDrvBasicCmd(SL_OPCODE_NETAPP_NDFLUSH_V6); -} -#endif - -/******************************************************************************/ -/* sl_NetAppGetServiceList */ -/******************************************************************************/ -typedef struct -{ - _u8 IndexOffest; - _u8 MaxServiceCount; - _u8 Flags; - _i8 Padding; -}NetappGetServiceListCMD_t; - -typedef union -{ - NetappGetServiceListCMD_t Cmd; - _BasicResponse_t Rsp; -}_SlNetappGetServiceListMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_NetAppGetServiceList) - -static const _SlCmdCtrl_t _SlGetServiceListeCtrl = -{ - SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE, - (_SlArgSize_t)sizeof(NetappGetServiceListCMD_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_NetAppGetServiceList(const _u8 IndexOffest, - const _u8 MaxServiceCount, - const _u8 Flags, - _i8 *pBuffer, - const _u32 BufferLength - ) -{ - - _i32 retVal= 0; - _SlNetappGetServiceListMsg_u Msg; - _SlCmdExt_t CmdExt; - _u16 ServiceSize = 0; - _u16 BufferSize = 0; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - /* - Calculate RX pBuffer size - WARNING: - if this size is BufferSize than 1480 error should be returned because there - is no place in the RX packet. - */ - ServiceSize = NetAppServiceSizeLUT[Flags & SL_NETAPP_SERVICE_SIZE_MASK]; - BufferSize = MaxServiceCount * ServiceSize; - - /* Check the size of the requested services is smaller than size of the user buffer. - If not an error is returned in order to avoid overwriting memory. */ - if(BufferLength < BufferSize) - { - return SL_ERROR_NET_APP_RX_BUFFER_LENGTH; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)BufferSize; - CmdExt.pRxPayload = (_u8 *)pBuffer; - - Msg.Cmd.IndexOffest = IndexOffest; - Msg.Cmd.MaxServiceCount = MaxServiceCount; - Msg.Cmd.Flags = Flags; - Msg.Cmd.Padding = 0; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetServiceListeCtrl, &Msg, &CmdExt)); - retVal = Msg.Rsp.status; - - return (_i16)retVal; -} - -#endif - -/*****************************************************************************/ -/* sl_mDNSRegisterService */ -/*****************************************************************************/ -/* - * The below struct depicts the constant parameters of the command/API RegisterService. - * - 1. ServiceLen - The length of the service should be smaller than SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - 2. TextLen - The length of the text should be smaller than SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - 3. port - The port on this target host. - 4. TTL - The TTL of the service - 5. Options - bitwise parameters: - bit 0 - is unique (means if the service needs to be unique) - bit 31 - for internal use if the service should be added or deleted (set means ADD). - bit 1-30 for future. - - NOTE: - - 1. There are another variable parameter is this API which is the service name and the text. - 2. According to now there is no warning and Async event to user on if the service is a unique. -* - */ - -typedef struct -{ - _u8 ServiceNameLen; - _u8 TextLen; - _u16 Port; - _u32 TTL; - _u32 Options; -}NetappMdnsSetService_t; - -typedef union -{ - NetappMdnsSetService_t Cmd; - _BasicResponse_t Rsp; -}_SlNetappMdnsRegisterServiceMsg_u; - -#if (_SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) || _SL_INCLUDE_FUNC(sl_NetAppMDNSUnregisterService)) - -static const _SlCmdCtrl_t _SlRegisterServiceCtrl = -{ - SL_OPCODE_NETAPP_MDNSREGISTERSERVICE, - (_SlArgSize_t)sizeof(NetappMdnsSetService_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -/****************************************************************************** - - sl_NetAppMDNSRegisterService - - CALLER user from its host - - - DESCRIPTION: - Add/delete service - The function manipulates the command that register the service and call - to the NWP in order to add/delete the service to/from the mDNS package and to/from the DB. - - This register service is a service offered by the application. - This unregister service is a service offered by the application before. - - The service name should be full service name according to RFC - of the DNS-SD - means the value in name field in SRV answer. - - Example for service name: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local - - If the option is_unique is set, mDNS probes the service name to make sure - it is unique before starting to announce the service on the network. - Instance is the instance portion of the service name. - - - - - PARAMETERS: - - The command is from constant parameters and variables parameters. - - Constant parameters are: - - ServiceLen - The length of the service. - TextLen - The length of the service should be smaller than 64. - port - The port on this target host. - TTL - The TTL of the service - Options - bitwise parameters: - bit 0 - is unique (means if the service needs to be unique) - bit 31 - for internal use if the service should be added or deleted (set means ADD). - bit 1-30 for future. - - The variables parameters are: - - Service name(full service name) - The service name. - Example for service name: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local - - Text - The description of the service. - should be as mentioned in the RFC - (according to type of the service IPP,FTP...) - - NOTE - pay attention - - 1. Temporary - there is an allocation on stack of internal buffer. - Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - It means that the sum of the text length and service name length cannot be bigger than - SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - If it is - An error is returned. - - 2. According to now from certain constraints the variables parameters are set in the - attribute part (contain constant parameters) - - - - RETURNS: Status - the immediate response of the command status. - 0 means success. - -******************************************************************************/ -_i16 _SlNetAppMDNSRegisterUnregisterService(const _i8* pServiceName, - const _u8 ServiceNameLen, - const _i8* pText, - const _u8 TextLen, - const _u16 Port, - const _u32 TTL, - const _u32 Options) -{ - _SlNetappMdnsRegisterServiceMsg_u Msg; - _SlCmdExt_t CmdExt ; - _i8 ServiceNameAndTextBuffer[SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH]; - _i8 *TextPtr; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - /* - - NOTE - pay attention - - 1. Temporary - there is an allocation on stack of internal buffer. - Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - It means that the sum of the text length and service name length cannot be bigger than - SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - If it is - An error is returned. - - 2. According to now from certain constraints the variables parameters are set in the - attribute part (contain constant parameters) - - */ - - /*build the attribute part of the command. - It contains the constant parameters of the command*/ - - Msg.Cmd.ServiceNameLen = ServiceNameLen; - Msg.Cmd.Options = Options; - Msg.Cmd.Port = Port; - Msg.Cmd.TextLen = TextLen; - Msg.Cmd.TTL = TTL; - - /*Build the payload part of the command - Copy the service name and text to one buffer. - NOTE - pay attention - The size of the service length + the text length should be smaller than 255, - Until the simplelink drive supports to variable length through SPI command. */ - if(TextLen + ServiceNameLen > (SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH - 1 )) /*-1 is for giving a place to set null termination at the end of the text*/ - { - return -1; - } - - _SlDrvMemZero(ServiceNameAndTextBuffer, (_u16)SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH); - - /*Copy the service name*/ - sl_Memcpy(ServiceNameAndTextBuffer, - pServiceName, - ServiceNameLen); - - if(TextLen > 0 ) - { - TextPtr = &ServiceNameAndTextBuffer[ServiceNameLen]; - /*Copy the text just after the service name*/ - sl_Memcpy(TextPtr, - pText, - TextLen); - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (TextLen + ServiceNameLen); - CmdExt.pTxPayload1 = (_u8 *)ServiceNameAndTextBuffer; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlRegisterServiceCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/**********************************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) - -_i16 sl_NetAppMDNSRegisterService(const _i8* pServiceName, - const _u8 ServiceNameLen, - const _i8* pText, - const _u8 TextLen, - const _u16 Port, - const _u32 TTL, - _u32 Options) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - /* - - NOTE - pay attention - - 1. Temporary - there is an allocation on stack of internal buffer. - Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - It means that the sum of the text length and service name length cannot be bigger than - SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - If it is - An error is returned. - - 2. According to now from certain constraints the variables parameters are set in the - attribute part (contain constant parameters) - - */ - - /*Set the add service bit in the options parameter. - In order not use different opcodes for the register service and unregister service - bit 31 in option is taken for this purpose. if it is set it means in NWP that the service should be added - if it is cleared it means that the service should be deleted and there is only meaning to pServiceName - and ServiceNameLen values. */ - Options |= SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT; - - return _SlNetAppMDNSRegisterUnregisterService(pServiceName, - ServiceNameLen, - pText, - TextLen, - Port, - TTL, - Options); -} -#endif -/**********************************************************************************************/ - - -/**********************************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_NetAppMDNSUnRegisterService) - -_i16 sl_NetAppMDNSUnRegisterService(const _i8* pServiceName, - const _u8 ServiceNameLen,_u32 Options) -{ - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - /* - - NOTE - pay attention - - The size of the service length should be smaller than 255, - Until the simplelink drive supports to variable length through SPI command. - - - */ - - /*Clear the add service bit in the options parameter. - In order not use different opcodes for the register service and unregister service - bit 31 in option is taken for this purpose. if it is set it means in NWP that the service should be added - if it is cleared it means that the service should be deleted and there is only meaning to pServiceName - and ServiceNameLen values.*/ - - Options &= (~SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT); - - return _SlNetAppMDNSRegisterUnregisterService( pServiceName, - ServiceNameLen, - NULL, - 0, - 0, - 0, - Options); - - -} -#endif -/**********************************************************************************************/ - - -/*****************************************************************************/ -/* sl_DnsGetHostByService */ -/*****************************************************************************/ -/* - * The below struct depicts the constant parameters of the command/API sl_DnsGetHostByService. - * - 1. ServiceLen - The length of the service should be smaller than 255. - 2. AddrLen - TIPv4 or IPv6 (SL_AF_INET , SL_AF_INET6). -* - */ - -typedef struct -{ - _u8 ServiceLen; - _u8 AddrLen; - _u16 Padding; -}_GetHostByServiceCommand_t; - -/* - * The below structure depict the constant parameters that are returned in the Async event answer - * according to command/API sl_DnsGetHostByService for IPv4 and IPv6. - * - 1Status - The status of the response. - 2.Address - Contains the IP address of the service. - 3.Port - Contains the port of the service. - 4.TextLen - Contains the max length of the text that the user wants to get. - it means that if the test of service is bigger that its value than - the text is cut to inout_TextLen value. - Output: Contain the length of the text that is returned. Can be full text or part - of the text (see above). -* -*/ - -typedef struct -{ - _u16 Status; - _u16 TextLen; - _u32 Port; - _u32 Address[4]; -}_GetHostByServiceIPv6AsyncResponse_t; - -/* - * The below struct contains pointers to the output parameters that the user gives - * - */ -typedef struct -{ - _i16 Status; - _u32 *out_pAddr; - _u32 *out_pPort; - _u16 *inout_TextLen; /* in: max len , out: actual len */ - _i8 *out_pText; -}_GetHostByServiceAsyncResponse_t; - -typedef union -{ - _GetHostByServiceCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlGetHostByServiceMsg_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByService) - -static const _SlCmdCtrl_t _SlGetHostByServiceCtrl = -{ - SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICE, - (_SlArgSize_t)sizeof(_GetHostByServiceCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -/******************************************************************************/ - -_i16 sl_NetAppDnsGetHostByService(_i8 *pServiceName, /* string containing all (or only part): name + subtype + service */ - const _u8 ServiceLen, - const _u8 Family, /* 4-IPv4 , 16-IPv6 */ - _u32 pAddr[], - _u32 *pPort, - _u16 *pTextLen, /* in: max len , out: actual len */ - _i8 *pText - ) -{ - _SlGetHostByServiceMsg_u Msg; - _SlCmdExt_t CmdExt ; - _GetHostByServiceAsyncResponse_t AsyncRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - _SlDrvMemZero(&AsyncRsp, sizeof(_GetHostByServiceAsyncResponse_t)); - -/* - Note: - 1. The return's attributes are belonged to first service that is found. - It can be other services with the same service name will response to - the query. The results of these responses are saved in the peer cache of the NWP, and - should be read by another API. - - 2. Text length can be 120 bytes only - not more - It is because of constraints in the NWP on the buffer that is allocated for the Async event. - - 3.The API waits to Async event by blocking. It means that the API is finished only after an Async event - is sent by the NWP. - - 4.No rolling option!!! - only PTR type is sent. - -*/ - /*build the attribute part of the command. - It contains the constant parameters of the command */ - - Msg.Cmd.ServiceLen = ServiceLen; - Msg.Cmd.AddrLen = Family; - - /*Build the payload part of the command - Copy the service name and text to one buffer.*/ - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = ServiceLen; - CmdExt.pTxPayload1 = (_u8 *)pServiceName; - - /*set pointers to the output parameters (the returned parameters). - This pointers are belonged to local struct that is set to global Async response parameter. - It is done in order not to run more than one sl_DnsGetHostByService at the same time. - The API should be run only if global parameter is pointed to NULL. */ - AsyncRsp.out_pText = pText; - AsyncRsp.inout_TextLen = (_u16* )pTextLen; - AsyncRsp.out_pPort = pPort; - AsyncRsp.out_pAddr = (_u32 *)&pAddr[0]; - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, GETHOSYBYSERVICE_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - if (SL_AF_INET6 == Family) - { - g_pCB->ObjPool[ObjIdx].AdditionalData |= SL_NETAPP_FAMILY_MASK; - } - /* Send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetHostByServiceCtrl, &Msg, &CmdExt)); - - /* If the immediate reponse is O.K. than wait for aSYNC event response. */ - if(SL_RET_CODE_OK == Msg.Rsp.status) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - - /* If we are - it means that Async event was sent. - The results are copied in the Async handle return functions */ - - Msg.Rsp.status = AsyncRsp.Status; - } - - _SlDrvReleasePoolObj(ObjIdx); - return Msg.Rsp.status; -} -#endif - -/******************************************************************************/ - -/****************************************************************************** - _SlNetAppHandleAsync_DnsGetHostByService - - CALLER NWP - Async event on sl_DnsGetHostByService with IPv4 Family - - - DESCRIPTION: - - Async event on sl_DnsGetHostByService command with IPv4 Family. - Return service attributes like IP address, port and text according to service name. - The user sets a service name Full/Part (see example below), and should get the: - 1. IP of the service - 2. The port of service. - 3. The text of service. - - Hence it can make a connection to the specific service and use it. - It is similar to get host by name method. - - It is done by a single shot query with PTR type on the service name. - - - - Note: - 1. The return's attributes are belonged to first service that is found. - It can be other services with the same service name will response to - the query. The results of these responses are saved in the peer cache of the NWP, and - should be read by another API. - - - PARAMETERS: - - pVoidBuf - is point to opcode of the event. - it contains the outputs that are given to the user - - outputs description: - - 1.out_pAddr[] - output: Contain the IP address of the service. - 2.out_pPort - output: Contain the port of the service. - 3.inout_TextLen - Input: Contain the max length of the text that the user wants to get. - it means that if the test of service is bigger that its value than - the text is cut to inout_TextLen value. - Output: Contain the length of the text that is returned. Can be full text or part - of the text (see above). - - 4.out_pText - Contain the text of the service (full or part see above- inout_TextLen description). - - * - - - RETURNS: success or fail. - -******************************************************************************/ -#ifndef SL_TINY -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf) -{ - _u16 TextLen; - _u16 UserTextLen; - _GetHostByServiceAsyncResponse_t* Res= NULL; - _GetHostByServiceIPv6AsyncResponse_t *pMsgArgs = (_GetHostByServiceIPv6AsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - /*Res pointed to mDNS global object struct */ - Res = (_GetHostByServiceAsyncResponse_t*)g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs; - /*IPv6*/ - if(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) - { - Res->out_pAddr[1] = pMsgArgs->Address[1]; /* Copy data from IPv6 address to Host user's pAddr. The array must be at least 4 cells of _u32 */ - Res->out_pAddr[2] = pMsgArgs->Address[2]; - Res->out_pAddr[3] = pMsgArgs->Address[3]; - } - - TextLen = pMsgArgs->TextLen; - - /*It is 4 bytes so we avoid from memcpy*/ - Res->out_pAddr[0] = pMsgArgs->Address[0]; /* Copy first cell data from IPv4/6 address to Host user's pAddr */ - Res->out_pPort[0] = pMsgArgs->Port; - Res->Status = (_i16)pMsgArgs->Status; - /*set to TextLen the text length of the user (input fromthe user).*/ - UserTextLen = Res->inout_TextLen[0]; - - /*Cut the service text if the user requested for smaller text.*/ - UserTextLen = (TextLen <= UserTextLen) ? TextLen : UserTextLen; - Res->inout_TextLen[0] = UserTextLen ; - - /************************************************************************************************** - - 2. Copy the payload part of the evnt (the text) to the payload part of the response - the lenght of the copy is according to the text length in the attribute part. */ - - /*IPv6*/ - if (g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) - { - sl_Memcpy(Res->out_pText, - (_i8 *)(& pMsgArgs[1]), /* & pMsgArgs[1] -> 1st byte after the fixed header = 1st byte of variable text.*/ - UserTextLen); - } - else - { - sl_Memcpy(Res->out_pText, - (_i8 *)(& pMsgArgs->Address[1]), /* & pMsgArgs[1] -> 1st byte after the fixed header = 1st byte of variable text.*/ - UserTextLen); - } - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - - return SL_OS_RET_CODE_OK; -} - -/*****************************************************************************/ -/* _SlNetAppHandleAsync_DnsGetHostByAddr */ -/*****************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByAddr(void *pVoidBuf) -{ - SL_TRACE0(DBG_MSG, MSG_303, "STUB: _SlNetAppHandleAsync_DnsGetHostByAddr not implemented yet!"); - return SL_OS_RET_CODE_OK; -} -#endif - -/*****************************************************************************/ -/* sl_DnsGetHostByName */ -/*****************************************************************************/ -typedef union -{ - NetAppGetHostByNameIPv4AsyncResponse_t IpV4; - NetAppGetHostByNameIPv6AsyncResponse_t IpV6; -}_GetHostByNameAsyncResponse_u; - -typedef union -{ - NetAppGetHostByNameCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlGetHostByNameMsg_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByName) -static const _SlCmdCtrl_t _SlGetHostByNameCtrl = -{ - SL_OPCODE_NETAPP_DNSGETHOSTBYNAME, - (_SlArgSize_t)sizeof(NetAppGetHostByNameCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_NetAppDnsGetHostByName(_i8 * pHostName,const _u16 NameLen, _u32* OutIpAddr,const _u8 Family ) -{ - _SlGetHostByNameMsg_u Msg; - _SlCmdExt_t ExtCtrl; - _GetHostByNameAsyncResponse_u AsyncRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - _SlDrvResetCmdExt(&ExtCtrl); - ExtCtrl.TxPayload1Len = NameLen; - ExtCtrl.pTxPayload1 = (_u8 *)pHostName; - - Msg.Cmd.Len = NameLen; - Msg.Cmd.Family = Family; - - /*Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvWaitForPoolObj(GETHOSYBYNAME_ID,SL_MAX_SOCKETS); - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp; - /*set bit to indicate IPv6 address is expected */ - if (SL_AF_INET6 == Family) - { - g_pCB->ObjPool[ObjIdx].AdditionalData |= SL_NETAPP_FAMILY_MASK; - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetHostByNameCtrl, &Msg, &ExtCtrl)); - - if(SL_RET_CODE_OK == Msg.Rsp.status) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - - Msg.Rsp.status = (_i16)AsyncRsp.IpV4.Status; - - if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) - { - sl_Memcpy((_i8 *)OutIpAddr, - (_i8 *)&AsyncRsp.IpV4.Ip0, - (SL_AF_INET == Family) ? SL_IPV4_ADDRESS_SIZE : SL_IPV6_ADDRESS_SIZE); - } - } - _SlDrvReleasePoolObj(ObjIdx); - return Msg.Rsp.status; -} -#endif - - -/******************************************************************************/ -/* _SlNetAppHandleAsync_DnsGetHostByName */ -/******************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf) -{ - NetAppGetHostByNameIPv4AsyncResponse_t *pMsgArgs = (NetAppGetHostByNameIPv4AsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - /*IPv6 */ - if(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(NetAppGetHostByNameIPv6AsyncResponse_t)); - } - /*IPv4 */ - else - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(NetAppGetHostByNameIPv4AsyncResponse_t)); - } - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_OS_RET_CODE_OK; -} - -#ifndef SL_TINY -static void _SlNetAppCopyPingResultsToReport(SlPingReportResponse_t *pResults,SlNetAppPingReport_t *pReport) -{ - pReport->PacketsSent = pResults->NumSendsPings; - pReport->PacketsReceived = pResults->NumSuccsessPings; - pReport->MinRoundTime = pResults->RttMin; - pReport->MaxRoundTime = pResults->RttMax; - pReport->AvgRoundTime = pResults->RttAvg; - pReport->TestTime = pResults->TestTime; -} - -/*****************************************************************************/ -/* _SlNetAppHandleAsync_PingResponse */ -/*****************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf) -{ - SlPingReportResponse_t *pMsgArgs = (SlPingReportResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - SlNetAppPingReport_t pingReport; - - if(pPingCallBackFunc) - { - _SlNetAppCopyPingResultsToReport(pMsgArgs,&pingReport); - pPingCallBackFunc(&pingReport); - } - else - { - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_SOCKET_CB(NULL != g_pCB->PingCB.PingAsync.pAsyncRsp); - - if (NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs) - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(SlPingReportResponse_t)); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - - return SL_OS_RET_CODE_OK; -} -#endif - -/*****************************************************************************/ -/* sl_NetAppPing */ -/*****************************************************************************/ -typedef union -{ - SlNetAppPingCommand_t Cmd; - SlPingReportResponse_t Rsp; -}_SlPingStartMsg_u; - -typedef enum -{ - CMD_PING_TEST_RUNNING = 0, - CMD_PING_TEST_STOPPED -}_SlPingStatus_e; - -#if _SL_INCLUDE_FUNC(sl_NetAppPing) -_i16 sl_NetAppPing(const SlNetAppPingCommand_t* pPingParams, const _u8 Family, SlNetAppPingReport_t *pReport, const P_SL_DEV_PING_CALLBACK pPingCallback) -{ - _SlCmdCtrl_t CmdCtrl = {0, (_SlArgSize_t)sizeof(SlNetAppPingCommand_t), (_SlArgSize_t)sizeof(_BasicResponse_t)}; - _SlPingStartMsg_u Msg; - SlPingReportResponse_t PingRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - _u32 PingTimeout = 0; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - if(NULL != pPingParams) - { - if(SL_AF_INET == Family) - { - CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART; - sl_Memcpy(&Msg.Cmd.Ip, &pPingParams->Ip, SL_IPV4_ADDRESS_SIZE); - } - else - { - CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART_V6; - sl_Memcpy(&Msg.Cmd.Ip, &pPingParams->Ip, SL_IPV6_ADDRESS_SIZE); - } - - Msg.Cmd.PingIntervalTime = pPingParams->PingIntervalTime; - Msg.Cmd.PingSize = pPingParams->PingSize; - Msg.Cmd.PingRequestTimeout = pPingParams->PingRequestTimeout; - Msg.Cmd.TotalNumberOfAttempts = pPingParams->TotalNumberOfAttempts; - Msg.Cmd.Flags = pPingParams->Flags; - - - /* calculate the ping timeout according to the parmas + the guard interval */ - PingTimeout = SL_NETAPP_PING_GUARD_INTERVAL + (pPingParams->PingIntervalTime * pPingParams->TotalNumberOfAttempts); - - if (Msg.Cmd.Ip != 0) - { - /* If the following conditions are met, return an error - Wrong ping parameters - ping cannot be called with the following parameters: - 1. infinite ping packet - 2. report only when finished - 3. no callback supplied */ - if ((pPingCallback == NULL) && (pPingParams->Flags == 0) && (pPingParams->TotalNumberOfAttempts == 0)) - { - return SL_RET_CODE_NET_APP_PING_INVALID_PARAMS; - } - - if( pPingCallback ) - { - pPingCallBackFunc = pPingCallback; - } - else - { - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvWaitForPoolObj(PING_ID,SL_MAX_SOCKETS); - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER)); - /* async response handler for non callback mode */ - g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&PingRsp; - pPingCallBackFunc = NULL; - OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj)); - } - } - } - /* Issue Stop Command */ - else - { - CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART; - Msg.Cmd.Ip = 0; - } - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); - if (Msg.Cmd.Ip != 0) - { - if(CMD_PING_TEST_RUNNING == (_i16)Msg.Rsp.Status || CMD_PING_TEST_STOPPED == (_i16)Msg.Rsp.Status ) - { - /* block waiting for results if no callback function is used */ - if( NULL == pPingCallback ) - { -#ifdef SL_TINY - _SlDrvSyncObjWaitForever(&g_pCB->ObjPool[ObjIdx].SyncObj); -#else - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, PingTimeout, SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE)); -#endif - - if( SL_OS_RET_CODE_OK == (_i16)PingRsp.Status ) - { - _SlNetAppCopyPingResultsToReport(&PingRsp,pReport); - } - _SlDrvReleasePoolObj(ObjIdx); - } - } - else - { /* ping failure, no async response */ - if( NULL == pPingCallback ) - { - _SlDrvReleasePoolObj(ObjIdx); - } - } - } - return (_i16)Msg.Rsp.Status; -} -#endif - -/*****************************************************************************/ -/* sl_NetAppSet */ -/*****************************************************************************/ -typedef union -{ - SlNetAppSetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlNetAppMsgSet_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppSet) - -static const _SlCmdCtrl_t _SlNetAppSetCmdCtrl = -{ - SL_OPCODE_NETAPP_NETAPPSET, - (_SlArgSize_t)sizeof(SlNetAppSetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_NetAppSet(const _u8 AppId ,const _u8 Option, const _u8 OptionLen, const _u8 *pOptionValue) -{ - _SlNetAppMsgSet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (OptionLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *)pOptionValue; - - Msg.Cmd.AppId = AppId; - Msg.Cmd.ConfigLen = OptionLen; - Msg.Cmd.ConfigOpt = Option; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppSetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*****************************************************************************/ -/* sl_NetAppSendTokenValue */ -/*****************************************************************************/ -typedef union -{ - SlNetAppHttpServerSendToken_t Cmd; - _BasicResponse_t Rsp; -}_SlNetAppMsgSendTokenValue_u; - -const _SlCmdCtrl_t _SlNetAppSendTokenValueCmdCtrl = -{ - SL_OPCODE_NETAPP_HTTPSENDTOKENVALUE, - (_SlArgSize_t)sizeof(SlNetAppHttpServerSendToken_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_u16 _SlNetAppSendTokenValue(SlNetAppHttpServerData_t * Token_value) -{ - _SlNetAppMsgSendTokenValue_u Msg; - _SlCmdExt_t CmdExt; - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - CmdExt.TxPayload1Len = (Token_value->ValueLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *) Token_value->pTokenValue; - - Msg.Cmd.TokenValueLen = Token_value->ValueLen; - Msg.Cmd.TokenNameLen = Token_value->NameLen; - sl_Memcpy(&Msg.Cmd.TokenName[0], Token_value->pTokenName, Token_value->NameLen); - - VERIFY_RET_OK(_SlDrvCmdSend_noLock((_SlCmdCtrl_t *)&_SlNetAppSendTokenValueCmdCtrl, &Msg, &CmdExt)); - - return Msg.Rsp.status; -} - -/*****************************************************************************/ -/* sl_NetAppSendResponse */ -/*****************************************************************************/ -#ifndef SL_TINY -typedef union -{ - SlProtocolNetAppResponse_t Cmd; - _BasicResponse_t Rsp; -}_SlNetAppMsgSendResponse_u; - -const _SlCmdCtrl_t _SlNetAppSendResponseCmdCtrl = -{ - SL_OPCODE_NETAPP_RESPONSE, - sizeof(SlProtocolNetAppResponse_t), - sizeof(_BasicResponse_t) -}; - -_u16 _SlNetAppSendResponse( _u16 handle, SlNetAppResponse_t *NetAppResponse) -{ - _SlNetAppMsgSendResponse_u Msg; - _SlCmdExt_t CmdExt; - _SlReturnVal_t RetVal; - _u16 dataLen; - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - dataLen = NetAppResponse->ResponseData.MetadataLen + NetAppResponse->ResponseData.PayloadLen; - - if ((NetAppResponse->ResponseData.MetadataLen <= SL_NETAPP_REQUEST_MAX_METADATA_LEN) && (dataLen <= SL_NETAPP_REQUEST_MAX_DATA_LEN)) - { - if (dataLen > 0) - { - /* Zero copy of the two parts: metadata + payload */ - CmdExt.pTxPayload1 = NetAppResponse->ResponseData.pMetadata; - CmdExt.TxPayload1Len = NetAppResponse->ResponseData.MetadataLen; - - CmdExt.pTxPayload2 = NetAppResponse->ResponseData.pPayload; - CmdExt.TxPayload2Len = NetAppResponse->ResponseData.PayloadLen; - } - else - { - CmdExt.pTxPayload1 = NULL; - CmdExt.pTxPayload2 = NULL; - } - - CmdExt.RxPayloadLen = 0; - CmdExt.pRxPayload = NULL; - - Msg.Cmd.Handle = handle; - Msg.Cmd.status = NetAppResponse->Status; - Msg.Cmd.MetadataLen = NetAppResponse->ResponseData.MetadataLen; - Msg.Cmd.PayloadLen = NetAppResponse->ResponseData.PayloadLen; - Msg.Cmd.Flags = NetAppResponse->ResponseData.Flags; - - RetVal = _SlDrvCmdSend_noLock((_SlCmdCtrl_t *)&_SlNetAppSendResponseCmdCtrl, &Msg, &CmdExt); - } - else - { - /* TODO: how to return the error code asynchronously? */ - RetVal = SL_ERROR_BSD_ENOMEM; - } - - return RetVal; -} - -/*****************************************************************************/ -/* sl_NetAppRecv */ -/*****************************************************************************/ -typedef union -{ - SlProtocolNetAppReceiveRequest_t Cmd; - _BasicResponse_t Rsp; /* Not used. do we need it? */ -}_SlNetAppReceiveMsg_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppRecv) - -const _SlCmdCtrl_t _SlNetAppReceiveCmdCtrl = -{ - SL_OPCODE_NETAPP_RECEIVEREQUEST, - sizeof(SlProtocolNetAppReceiveRequest_t), - sizeof(_BasicResponse_t) /* Where is this used? */ -}; - -_SlReturnVal_t sl_NetAppRecv( _u16 Handle, _u16 *DataLen, _u8 *pData, _u32 *Flags) -{ - _SlNetAppReceiveMsg_u Msg; - _SlCmdExt_t CmdExt; - SlProtocolNetAppReceive_t AsyncRsp; /* Will be filled when SL_OPCODE_NETAPP_RECEIVE async event is arrived */ - - _SlReturnVal_t RetVal; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - _SlArgsData_t pArgsData; - - /* Validate input arguments */ - if ((NULL == pData) || (0==DataLen)) - { - return SL_ERROR_BSD_EINVAL; - } - - /* Save the user RX bufer. Rx data will be copied into it on the SL_OPCODE_NETAPP_RECEIVE async event */ - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = *DataLen; - CmdExt.pRxPayload = pData; - - /* Prepare the command args */ - Msg.Cmd.Handle = Handle; - Msg.Cmd.MaxBufferLen = *DataLen; - Msg.Cmd.Flags = *Flags; - - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvWaitForPoolObj(NETAPP_RECEIVE_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - /* Save the AsyncRsp and cmdExt information for the SL_OPCODE_NETAPP_RECEIVE async event */ - AsyncRsp.Handle = Handle; /* Handle we are waiting for */ - AsyncRsp.Flags = 0; - AsyncRsp.PayloadLen = 0; /* 0 will indicate an error in the SL_OPCODE_NETAPP_RECEIVE async event and that no data arrived. */ - - _SlDrvProtectionObjLockWaitForever(); - - pArgsData.pData = (_u8 *) &CmdExt; - pArgsData.pArgs = (_u8 *) &AsyncRsp; - - g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&pArgsData; - - _SlDrvProtectionObjUnLock(); - - /* Send the command */ - RetVal = _SlDrvCmdSend((_SlCmdCtrl_t *)&_SlNetAppReceiveCmdCtrl, &Msg, &CmdExt); - - if(SL_OS_RET_CODE_OK == RetVal) - { - /* Wait for SL_OPCODE_NETAPP_RECEIVE async event. Will be signaled by _SlNetAppHandleAsync_NetAppReceive. */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); - - /* Update information for the user */ - *DataLen = AsyncRsp.PayloadLen; - *Flags = AsyncRsp.Flags; - } - - _SlDrvReleasePoolObj(ObjIdx); - - return RetVal; -} - -#endif - -/*****************************************************************************/ -/* _SlNetAppHandleAsync_NetAppReceive */ -/*****************************************************************************/ -void _SlNetAppHandleAsync_NetAppReceive(void *pVoidBuf) -{ - _u8 *pData; - _u16 len; - SlProtocolNetAppReceive_t *AsyncRsp; - _SlCmdExt_t *CmdExt; - SlProtocolNetAppReceive_t *pMsgArgs = (SlProtocolNetAppReceive_t *)_SL_RESP_ARGS_START(pVoidBuf); - - pData = (_u8 *)((SlProtocolNetAppReceive_t *)pMsgArgs + 1); /* Points to the netapp receive payload */ - - _SlDrvProtectionObjLockWaitForever(); - - if (NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs) - { - AsyncRsp = (SlProtocolNetAppReceive_t *) ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))-> pArgs; - CmdExt = (_SlCmdExt_t *) ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))-> pData; - - if (pMsgArgs->Handle == AsyncRsp->Handle) - { - if (pMsgArgs->PayloadLen <= CmdExt->RxPayloadLen) - { - len = pMsgArgs->PayloadLen; - } - else - { - len = CmdExt->RxPayloadLen; - } - - /* Copy the data to the user buffer */ - sl_Memcpy (CmdExt->pRxPayload, pData, len); - - /* Update len and flags */ - AsyncRsp->PayloadLen = len; - AsyncRsp->Flags = pMsgArgs->Flags; - } - } - - _SlDrvSyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - _SlDrvProtectionObjUnLock(); - - return; -} - -#endif - -/*****************************************************************************/ -/* sl_NetAppSend */ -/*****************************************************************************/ -typedef union -{ - SlProtocolNetAppSend_t Cmd; - _BasicResponse_t Rsp; -}_SlNetAppMsgSend_u; - -const _SlCmdCtrl_t _SlNetAppSendCmdCtrl = -{ - SL_OPCODE_NETAPP_SEND, - sizeof(SlProtocolNetAppSend_t), - sizeof(_BasicResponse_t) -}; - -_u16 sl_NetAppSend( _u16 Handle, _u16 DataLen, _u8* pData, _u32 Flags) -{ - _SlNetAppMsgSend_u Msg; - _SlCmdExt_t CmdExt; - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - if ((((Flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) == SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) && (DataLen <= SL_NETAPP_REQUEST_MAX_METADATA_LEN)) || - (((Flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) == 0) && (DataLen <= SL_NETAPP_REQUEST_MAX_DATA_LEN))) - { - CmdExt.TxPayload1Len = (DataLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *) pData; - - Msg.Cmd.Handle = Handle; - Msg.Cmd.DataLen = DataLen; - Msg.Cmd.Flags = Flags; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppSendCmdCtrl, &Msg, &CmdExt)); - } - else - { - Msg.Rsp.status = SL_ERROR_BSD_ENOMEM; - } - - return Msg.Rsp.status; -} - -/*****************************************************************************/ -/* sl_NetAppGet */ -/*****************************************************************************/ -typedef union -{ - SlNetAppSetGet_t Cmd; - SlNetAppSetGet_t Rsp; -}_SlNetAppMsgGet_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppGet) -static const _SlCmdCtrl_t _SlNetAppGetCmdCtrl = -{ - SL_OPCODE_NETAPP_NETAPPGET, - (_SlArgSize_t)sizeof(SlNetAppSetGet_t), - (_SlArgSize_t)sizeof(SlNetAppSetGet_t) -}; - -_i16 sl_NetAppGet(const _u8 AppId, const _u8 Option,_u8 *pOptionLen, _u8 *pOptionValue) -{ - _SlNetAppMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - if (*pOptionLen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(*pOptionLen); - CmdExt.pRxPayload = (_u8 *)pOptionValue; - - Msg.Cmd.AppId = AppId; - Msg.Cmd.ConfigOpt = Option; - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppGetCmdCtrl, &Msg, &CmdExt)); - - - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pOptionLen = (_u8)CmdExt.RxPayloadLen; - return SL_ESMALLBUF; - } - else - { - *pOptionLen = (_u8)CmdExt.ActualRxPayloadLen; - } - - return (_i16)Msg.Rsp.Status; -} -#endif - -/*****************************************************************************/ -/* _SlNetAppEventHandler */ -/*****************************************************************************/ -_SlReturnVal_t _SlNetAppEventHandler(void* pArgs) -{ - _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)pArgs; -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) - SlNetAppHttpServerEvent_t httpServerEvent; - SlNetAppHttpServerResponse_t httpServerResponse; -#endif - switch(pHdr->GenHeader.Opcode) - { - case SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE: - case SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE_V6: - _SlNetAppHandleAsync_DnsGetHostByName(pArgs); - break; -#ifndef SL_TINY - case SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE: - case SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE_V6: - _SlNetAppHandleAsync_DnsGetHostByService(pArgs); - break; - case SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE: - _SlNetAppHandleAsync_PingResponse(pArgs); - break; -#endif - - case SL_OPCODE_NETAPP_HTTPGETTOKENVALUE: - { -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) - _u8 *pTokenName; - SlNetAppHttpServerData_t Token_value; - SlNetAppHttpServerGetToken_t *httpGetToken = (SlNetAppHttpServerGetToken_t *)_SL_RESP_ARGS_START(pHdr); - pTokenName = (_u8 *)((SlNetAppHttpServerGetToken_t *)httpGetToken + 1); - - httpServerResponse.Response = SL_NETAPP_HTTPSETTOKENVALUE; - httpServerResponse.ResponseData.TokenValue.Len = SL_NETAPP_MAX_TOKEN_VALUE_LEN; - - /* Reuse the async buffer for getting the token value response from the user */ - httpServerResponse.ResponseData.TokenValue.pData = (_u8 *)_SL_RESP_ARGS_START(pHdr) + SL_NETAPP_MAX_TOKEN_NAME_LEN; - - httpServerEvent.Event = SL_NETAPP_EVENT_HTTP_TOKEN_GET; - httpServerEvent.EventData.HttpTokenName.Len = httpGetToken->TokenNameLen; - httpServerEvent.EventData.HttpTokenName.pData = pTokenName; - - Token_value.pTokenName = pTokenName; - - _SlDrvDispatchHttpServerEvents (&httpServerEvent, &httpServerResponse); - - Token_value.ValueLen = httpServerResponse.ResponseData.TokenValue.Len; - Token_value.NameLen = httpServerEvent.EventData.HttpTokenName.Len; - Token_value.pTokenValue = httpServerResponse.ResponseData.TokenValue.pData; - - _SlNetAppSendTokenValue(&Token_value); -#else - - _u8 *pTokenName; - SlNetAppHttpServerData_t Token_value; - SlNetAppHttpServerGetToken_t *httpGetToken = (SlNetAppHttpServerGetToken_t*)_SL_RESP_ARGS_START(pHdr); - pTokenName = (_u8 *)((SlNetAppHttpServerGetToken_t *)httpGetToken + 1); - - Token_value.pTokenName = pTokenName; - Token_value.ValueLen = 0; - Token_value.NameLen = httpGetToken->TokenNameLen; - Token_value.pTokenValue = NULL; - - _SlNetAppSendTokenValue(&Token_value); -#endif - } - break; - - case SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE: - { -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) - _u8 *pPostParams; - - SlNetAppHttpServerPostToken_t *httpPostTokenArgs = (SlNetAppHttpServerPostToken_t *)_SL_RESP_ARGS_START(pHdr); - pPostParams = (_u8 *)((SlNetAppHttpServerPostToken_t *)httpPostTokenArgs + 1); - - httpServerEvent.Event = SL_NETAPP_EVENT_HTTP_TOKEN_POST; - - httpServerEvent.EventData.HttpPostData.Action.Len = httpPostTokenArgs->PostActionLen; - httpServerEvent.EventData.HttpPostData.Action.pData = pPostParams; - pPostParams+=httpPostTokenArgs->PostActionLen; - - httpServerEvent.EventData.HttpPostData.TokenName.Len = httpPostTokenArgs->TokenNameLen; - httpServerEvent.EventData.HttpPostData.TokenName.pData = pPostParams; - pPostParams+=httpPostTokenArgs->TokenNameLen; - - httpServerEvent.EventData.HttpPostData.TokenValue.Len = httpPostTokenArgs->TokenValueLen; - httpServerEvent.EventData.HttpPostData.TokenValue.pData = pPostParams; - - httpServerResponse.Response = SL_NETAPP_HTTPRESPONSE_NONE; - - _SlDrvDispatchHttpServerEvents (&httpServerEvent, &httpServerResponse); -#endif - } - break; -#ifndef SL_TINY - case SL_OPCODE_NETAPP_REQUEST: - { -#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) - _u8 *pData; - SlNetAppRequest_t NetAppRequest; - SlNetAppResponse_t NetAppResponse; - _u16 status; - - /* Points to the Netapp request Arguments */ - SlProtocolNetAppRequest_t *protocol_NetAppRequest = (SlProtocolNetAppRequest_t*)_SL_RESP_ARGS_START(pHdr); - - NetAppRequest.AppId = protocol_NetAppRequest->AppId; - NetAppRequest.Type = protocol_NetAppRequest->RequestType; - NetAppRequest.Handle = protocol_NetAppRequest->Handle; - NetAppRequest.requestData.Flags = protocol_NetAppRequest->Flags; - - /* Prepare the Metadata*/ - pData = (_u8 *)((SlProtocolNetAppRequest_t *)protocol_NetAppRequest + 1);/* Points to the netapp request Data (start of Metadata + payload) */ - NetAppRequest.requestData.pMetadata = pData; /* Just pass the pointer */ - NetAppRequest.requestData.MetadataLen = protocol_NetAppRequest->MetadataLen; - - /* Preare the Payload */ - pData+=protocol_NetAppRequest->MetadataLen; - NetAppRequest.requestData.pPayload = pData; /* Just pass the pointer */ - NetAppRequest.requestData.PayloadLen = protocol_NetAppRequest->PayloadLen; - - /* Just in case - clear the response outout data */ - sl_Memset(&NetAppResponse, 0, sizeof (NetAppResponse)); - NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; - - /* Call the request handler dispatcher */ - _SlDrvDispatchNetAppRequestEvents (&NetAppRequest, &NetAppResponse); - - /* Handle the response */ - status = _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); - -#if (defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_NetAppRequestMemFree)) - if(1 == _SlIsEventRegistered(SL_EVENT_HDL_MEM_FREE)) - { - if ((NetAppResponse.ResponseData.MetadataLen > 0) && (NetAppResponse.ResponseData.pMetadata != NULL)) - { - _SlDrvHandleNetAppRequestMemFreeEvents (NetAppResponse.ResponseData.pMetadata); - } - - if ((NetAppResponse.ResponseData.PayloadLen > 0) && (NetAppResponse.ResponseData.pPayload != NULL)) - { - _SlDrvHandleNetAppRequestMemFreeEvents (NetAppResponse.ResponseData.pPayload); - } - } -#endif - - if (status != 0 ) - { - /* Error - just send resource not found */ - NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; - NetAppResponse.ResponseData.pMetadata = NULL; - NetAppResponse.ResponseData.MetadataLen = 0; - NetAppResponse.ResponseData.pPayload = NULL; - NetAppResponse.ResponseData.PayloadLen = 0; - NetAppResponse.ResponseData.Flags = 0; - - /* Handle the response */ - _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); - } -#else - - SlNetAppResponse_t NetAppResponse; - - /* Points to the Netapp request Arguments */ - SlProtocolNetAppRequest_t *protocol_NetAppRequest = (SlProtocolNetAppRequest_t *)_SL_RESP_ARGS_START(pHdr); - - /* Prepare the response */ - NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; - NetAppResponse.ResponseData.pMetadata = NULL; - NetAppResponse.ResponseData.MetadataLen = 0; - NetAppResponse.ResponseData.pPayload = NULL; - NetAppResponse.ResponseData.PayloadLen = 0; - NetAppResponse.ResponseData.Flags = 0; - - /* Handle the response */ - _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); -#endif - - } - break; -#endif - - default: - // SL_ERROR_TRACE2(MSG_305, "ASSERT: _SlNetAppEventHandler : invalid opcode = 0x%x = %1", pHdr->GenHeader.Opcode, pHdr->GenHeader.Opcode); - VERIFY_PROTOCOL(0); - } - - return SL_OS_RET_CODE_OK; -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netcfg.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netcfg.c deleted file mode 100755 index 702fc0a0038..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netcfg.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * netcfg.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -/*****************************************************************************/ -/* sl_NetCfgSet */ -/*****************************************************************************/ -typedef union -{ - SlNetCfgSetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlNetCfgMsgSet_u; - -#if _SL_INCLUDE_FUNC(sl_NetCfgSet) - -static const _SlCmdCtrl_t _SlNetCfgSetCmdCtrl = -{ - SL_OPCODE_DEVICE_NETCFG_SET_COMMAND, - (_SlArgSize_t)sizeof(SlNetCfgSetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_NetCfgSet(const _u16 ConfigId,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues) -{ - _SlNetCfgMsgSet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETCFG); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (ConfigLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *)pValues; - - Msg.Cmd.ConfigId = ConfigId; - Msg.Cmd.ConfigLen = ConfigLen; - Msg.Cmd.ConfigOpt = ConfigOpt; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetCfgSetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*****************************************************************************/ -/* sl_NetCfgGet */ -/*****************************************************************************/ -typedef union -{ - SlNetCfgSetGet_t Cmd; - SlNetCfgSetGet_t Rsp; -}_SlNetCfgMsgGet_u; - -#if _SL_INCLUDE_FUNC(sl_NetCfgGet) - -static const _SlCmdCtrl_t _SlNetCfgGetCmdCtrl = -{ - SL_OPCODE_DEVICE_NETCFG_GET_COMMAND, - (_SlArgSize_t)sizeof(SlNetCfgSetGet_t), - (_SlArgSize_t)sizeof(SlNetCfgSetGet_t) -}; - -_i16 sl_NetCfgGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues) -{ - _SlNetCfgMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETCFG); - - if (*pConfigLen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(*pConfigLen); - CmdExt.pRxPayload = (_u8 *)pValues; - - _SlDrvMemZero((void*) &Msg, sizeof(Msg)); - - Msg.Cmd.ConfigLen = *pConfigLen; - Msg.Cmd.ConfigId = ConfigId; - - if( pConfigOpt ) - { - Msg.Cmd.ConfigOpt = (_u16)*pConfigOpt; - } - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetCfgGetCmdCtrl, &Msg, &CmdExt)); - - if( pConfigOpt ) - { - *pConfigOpt = (_u8)Msg.Rsp.ConfigOpt; - } - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pConfigLen = (_u8)CmdExt.RxPayloadLen; - return SL_ESMALLBUF; - } - else - { - *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen; - } - - return Msg.Rsp.Status; -} -#endif - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netutil.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netutil.c deleted file mode 100755 index ff498794080..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netutil.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * netutil.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include - -/*****************************************************************************/ -/* Internal functions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - - -/****************************************************************************** -sl_UtilsGet -******************************************************************************/ - -typedef union -{ - SlNetUtilSetGet_t Cmd; - SlNetUtilSetGet_t Rsp; -} SlNetUtilMsgGet_u; - -#if _SL_INCLUDE_FUNC(sl_NetUtilGet) - -const _SlCmdCtrl_t _SlNetUtilGetCmdCtrl = -{ - SL_OPCODE_NETUTIL_GET, - sizeof(SlNetUtilSetGet_t), - sizeof(SlNetUtilSetGet_t) -}; - -_i16 sl_NetUtilGet(const _u16 Option, const _u32 ObjID, _u8 *pValues, _u16 *pValueLen) -{ - SlNetUtilMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = *pValueLen; - CmdExt.pRxPayload = (_u8 *)pValues; - - Msg.Cmd.Option = Option; - Msg.Cmd.ObjId = ObjID; - Msg.Cmd.ValueLen = *pValueLen; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetUtilGetCmdCtrl, &Msg, &CmdExt)); - - if(CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pValueLen = CmdExt.RxPayloadLen; - return SL_ESMALLBUF; - } - else - { - *pValueLen = CmdExt.ActualRxPayloadLen; - } - - return (_i16)Msg.Rsp.Status; -} -#endif - - -/*************************************************************************** -_SlNetUtilHandleAsync_Cmd - handles NetUtil Cmd response, signalling to -a waiting object -****************************************************************************/ -void _SlNetUtilHandleAsync_Cmd(void *pVoidBuf) -{ - _SlNetUtilCmdData_t *pOutData; - SlNetUtilCmdRsp_t *pMsgArgs = (SlNetUtilCmdRsp_t *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - pOutData = (_SlNetUtilCmdData_t*)g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs; - - pOutData->Status = pMsgArgs->Status; - - if(SL_RET_CODE_OK == pMsgArgs->Status) - { - if (*(pOutData->pOutputLen) < pMsgArgs->OutputLen) - { - pOutData->Status = SL_ESMALLBUF; - } - else - { - *(pOutData->pOutputLen) = pMsgArgs->OutputLen; - - if(*(pOutData->pOutputLen) > 0) - { - /* copy only the data from the global async buffer */ - sl_Memcpy(pOutData->pOutputValues, (char*)pMsgArgs + sizeof(SlNetUtilCmdRsp_t), *(pOutData->pOutputLen)); - } - } - } - - _SlDrvSyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - _SlDrvProtectionObjUnLock(); - return; -} - - -/***************************************************************************** -sl_NetUtilCmd -******************************************************************************/ -typedef union -{ - SlNetUtilCmd_t Cmd; - _BasicResponse_t Rsp; -} SlNetUtilCmdMsg_u; - -#if _SL_INCLUDE_FUNC(sl_NetUtilCmd) -const _SlCmdCtrl_t _SlNetUtilCmdCtrl = -{ - SL_OPCODE_NETUTIL_COMMAND, - sizeof(SlNetUtilCmd_t), - sizeof(_BasicResponse_t) -}; - -_i16 sl_NetUtilCmd(const _u16 Cmd, const _u8 *pAttrib, const _u16 AttribLen, - const _u8 *pInputValues, const _u16 InputLen, - _u8 *pOutputValues, _u16 *pOutputLen) -{ - _i16 RetVal=0; - SlNetUtilCmdMsg_u Msg; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - _SlCmdExt_t CmdExt; - _SlNetUtilCmdData_t OutData; - - /* prepare the Cmd (control structure and data-buffer) */ - Msg.Cmd.Cmd = Cmd; - Msg.Cmd.AttribLen = AttribLen; - Msg.Cmd.InputLen = InputLen; - Msg.Cmd.OutputLen = *pOutputLen; - - _SlDrvResetCmdExt(&CmdExt); - _SlDrvMemZero(&OutData, sizeof(_SlNetUtilCmdData_t)); - - if(AttribLen > 0) - { - CmdExt.pTxPayload1 = (_u8*)pAttrib; - CmdExt.TxPayload1Len = AttribLen; - } - - if (InputLen > 0) - { - CmdExt.pTxPayload2 = (_u8*)pInputValues; - CmdExt.TxPayload2Len = InputLen; - } - - /* Set the pointers to be filled upon the async event reception */ - OutData.pOutputValues = pOutputValues; - OutData.pOutputLen = pOutputLen; - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&OutData, NETUTIL_CMD_ID, SL_MAX_SOCKETS); - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetUtilCmdCtrl, &Msg, &CmdExt)); - - if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) - { - /* after the async event is signaled, the data will be copied to the pOutputValues buffer */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); - - /* the response header status */ - RetVal = OutData.Status; - - } - else - { - RetVal = Msg.Rsp.status; - } - _SlDrvReleasePoolObj((_u8)ObjIdx); - - return RetVal; -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.c deleted file mode 100755 index 011324492a9..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * nonos.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -#ifndef SL_PLATFORM_MULTI_THREADED - -#include "nonos.h" - -_SlNonOsCB_t g__SlNonOsCB; - -_SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags) -{ - _i8 i = 0; - - /* The parameter is currently not in use */ - (void)flags; - -#ifndef SL_TINY - for (i=0 ; iIsAllocated == FALSE) - { - pE->pValue = pValue; - pE->pEntry = pEntry; - pE->IsAllocated = TRUE; -#ifndef SL_TINY - break; -#endif - } - } - - return NONOS_RET_OK; -} - -_SlNonOsRetVal_t _SlNonOsHandleSpawnTask(void) -{ - _i8 i=0; - void* pValue; - -#ifndef SL_TINY - for (i=0 ; iIsAllocated == TRUE) - { - _SlSpawnEntryFunc_t pF = pE->pEntry; - pValue = pE->pValue; - - /* Clear the entry */ - pE->pEntry = NULL; - pE->pValue = NULL; - pE->IsAllocated = FALSE; - - /* execute the spawn function */ - pF(pValue); - } - } - return NONOS_RET_OK; -} - -void tiDriverSpawnCallback(void) -{ - /* If we are in cmd context and waiting for its cmd response - * do not handle async events from spawn, as the global lock was already taken when sending the command, - * and the Async event would be handled in read cmd context, so we do nothing. - */ - if (FALSE == g_pCB->WaitForCmdResp) - { - (void)_SlNonOsHandleSpawnTask(); - } -} - -#endif - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.h deleted file mode 100755 index 18bf9657431..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * nonos.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef __NONOS_H__ -#define __NONOS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef SL_PLATFORM_MULTI_THREADED - -/* This function call the user defined function, if defined, from the sync wait loop */ -/* The use case of this function is to allow nonos system to call a user function to put the device into sleep */ -/* The wake up should be activated after getting an interrupt from the device to Host */ -/* The user function must return without blocking to prevent a delay on the event handling */ -/* -#define _SlSyncWaitLoopCallback UserSleepFunction -*/ - -#ifndef SL_TINY_EXT -#define NONOS_MAX_SPAWN_ENTRIES (5) -#else -#define NONOS_MAX_SPAWN_ENTRIES (1) -#endif - -#define NONOS_WAIT_FOREVER ~(0UL) -#define NONOS_NO_WAIT (0x0) - -#define NONOS_RET_OK (0) -#define NONOS_RET_ERR (0xFF) -#define OSI_OK (NONOS_RET_OK) - -typedef struct -{ - _SlSpawnEntryFunc_t pEntry; - void* pValue; - _u8 IsAllocated; -}_SlNonOsSpawnEntry_t; - -typedef struct -{ - _SlNonOsSpawnEntry_t SpawnEntries[NONOS_MAX_SPAWN_ENTRIES]; -}_SlNonOsCB_t; - - -/*! - \brief type definition for the return values of this adaptation layer -*/ -typedef _u32 _SlNonOsRetVal_t; - -/*! - \brief type definition for a time value -*/ -typedef _u32 _SlNonOsTime_t; - - -#define _SlTime_t _SlNonOsTime_t - -#define SL_OS_WAIT_FOREVER NONOS_WAIT_FOREVER - -#define SL_OS_RET_CODE_OK NONOS_RET_OK - -#define SL_OS_NO_WAIT NONOS_NO_WAIT - - -/*! - \brief This function call the pEntry callback from a different context - - \param pEntry - pointer to the entry callback function - - \param pValue - pointer to any type of memory structure that would be - passed to pEntry callback from the execution thread. - - \param flags - execution flags - reserved for future usage - - \return upon successful registration of the spawn the function return 0 - (the function is not blocked till the end of the execution of the function - and could be returned before the execution is actually completed) - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -_SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); - - -/*! - \brief This function is called form the main context, while waiting on a sync object. - - \param None - - \return None - - \note - \warning -*/ -void tiDriverSpawnCallback(void); - - -/*! - \brief This function is called directly the main context, while in main task loop. - - \param None - - \return None - - \note - \warning -*/ -_SlNonOsRetVal_t _SlNonOsHandleSpawnTask(void); - -extern _SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); - -/***************************************************************************** - - Overwrite SimpleLink driver OS adaptation functions - - *****************************************************************************/ - -#undef sl_Spawn -#define sl_Spawn(pEntry,pValue,flags) _SlNonOsSpawn(pEntry,pValue,flags) - -#undef _SlTaskEntry -#define _SlTaskEntry _SlNonOsHandleSpawnTask - -#endif /* !SL_PLATFORM_MULTI_THREADED */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/objInclusion.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/objInclusion.h deleted file mode 100755 index 5a164970222..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/objInclusion.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * objInclusion.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -#include - - -#ifndef OBJINCLUSION_H_ -#define OBJINCLUSION_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** - - For future use - -*******************************************************************************/ - -#define __inln /* if inline functions requiered: #define __inln inline */ - -#define SL_DEVICE /* Device silo is currently always mandatory */ - - -/****************************************************************************** - - Qualifiers for package customizations - -*******************************************************************************/ - -#if defined (SL_DEVICE) -#define __dev 1 -#else -#define __dev 0 -#endif - -#if defined (SL_DEVICE) && defined (SL_INC_EXT_API) -#define __dev__ext 1 -#else -#define __dev__ext 0 -#endif - - -#if (!defined (SL_PLATFORM_MULTI_THREADED)) || (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) -#define __int__spwn 1 -#else -#define __int__spwn 0 -#endif - -#if defined (SL_INC_NET_APP_PKG) -#define __nap 1 -#else -#define __nap 0 -#endif - -#if defined (SL_INC_NET_APP_PKG) && defined (SL_INC_SOCK_CLIENT_SIDE_API) -#define __nap__clt 1 -#else -#define __nap__clt 0 -#endif - -#if defined (SL_INC_NET_APP_PKG) && defined (SL_INC_EXT_API) -#define __nap__ext 1 -#else -#define __nap__ext 0 -#endif - -#if defined (SL_INC_NET_CFG_PKG) -#define __ncg 1 -#else -#define __ncg 0 -#endif - -#if defined (SL_INC_NET_CFG_PKG) && defined (SL_INC_EXT_API) -#define __ncg__ext 1 -#else -#define __ncg__ext 0 -#endif - -#if defined (SL_INC_NVMEM_PKG) -#define __nvm 1 -#else -#define __nvm 0 -#endif - -#if defined (SL_INC_NVMEM_EXT_PKG) && defined (SL_INC_EXT_API) -#define __nvm__ext 1 -#else -#define __nvm__ext 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) -#define __sck 1 -#else -#define __sck 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_EXT_API) -#define __sck__ext 1 -#else -#define __sck__ext 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_SERVER_SIDE_API) -#define __sck__srv 1 -#else -#define __sck__srv 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_CLIENT_SIDE_API) -#define __sck__clt 1 -#else -#define __sck__clt 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_RECV_API) -#define __sck__rcv 1 -#else -#define __sck__rcv 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_SEND_API) -#define __sck__snd 1 -#else -#define __sck__snd 0 -#endif - -#if defined (SL_INC_WLAN_PKG) -#define __wln 1 -#else -#define __wln 0 -#endif - -#if defined (SL_INC_WLAN_PKG) && defined (SL_INC_EXT_API) -#define __wln__ext 1 -#else -#define __wln__ext 0 -#endif - -/* The return 1 is the function need to be included in the output */ -#define _SL_INCLUDE_FUNC(Name) (_SL_INC_##Name) - -/* Driver */ -#define _SL_INC_sl_NetAppStart __nap__ext -#define _SL_INC_sl_NetAppStop __nap__ext - -#define _SL_INC_sl_NetAppDnsGetHostByName __nap__clt - - -#define _SL_INC_sl_NetAppDnsGetHostByService __nap__ext -#define _SL_INC_sl_NetAppMDNSRegisterService __nap__ext -#define _SL_INC_sl_NetAppMDNSUnRegisterService __nap__ext -#define _SL_INC_sl_NetAppGetServiceList __nap__ext - - -#define _SL_INC_sl_DnsGetHostByAddr __nap__ext -#define _SL_INC_sl_NetAppPing __nap__ext -#define _SL_INC_sl_NetAppSet __nap__ext -#define _SL_INC_sl_NetAppGet __nap__ext -#define _SL_INC_sl_NetAppRecv __nap__ext -#define _SL_INC_sl_NetAppArpFlush __nap__ext -#define _SL_INC_sl_NetAppNdFlush __nap__ext - -#define _SL_INC_sl_NetAppSend __nap__ext - -/* FS */ -#define _SL_INC_sl_FsOpen __nvm - -#define _SL_INC_sl_FsClose __nvm - -#define _SL_INC_sl_FsRead __nvm - -#define _SL_INC_sl_FsWrite __nvm - -#define _SL_INC_sl_FsGetInfo __nvm - -#define _SL_INC_sl_FsDel __nvm - -#define _SL_INC_sl_FsCtl __nvm__ext - -#define _SL_INC_sl_FsProgram __nvm__ext - -#define _SL_INC_sl_FsGetFileList __nvm__ext - -/* netcfg */ -#define _SL_INC_sl_MacAdrrSet __ncg - -#define _SL_INC_sl_MacAdrrGet __ncg - -#define _SL_INC_sl_NetCfgGet __ncg - -#define _SL_INC_sl_NetCfgSet __ncg - -/* socket */ -#define _SL_INC_sl_Socket __sck - -#define _SL_INC_sl_Close __sck - -#define _SL_INC_sl_Accept __sck__srv - -#define _SL_INC_sl_Bind __sck - -#define _SL_INC_sl_Listen __sck__srv - -#define _SL_INC_sl_Connect __sck__clt - -#define _SL_INC_sl_Select __sck - -#define _SL_INC_sl_SetSockOpt __sck - -#define _SL_INC_sl_GetSockOpt __sck__ext - -#define _SL_INC_sl_Recv __sck__rcv - -#define _SL_INC_sl_RecvFrom __sck__rcv - -#define _SL_INC_sl_Write __sck__snd - -#define _SL_INC_sl_Send __sck__snd - -#define _SL_INC_sl_SendTo __sck__snd - -#define _SL_INC_sl_StartTLS __sck - -#define _SL_INC_sl_Htonl __sck - -#define _SL_INC_sl_Htons __sck - -/* wlan */ -#define _SL_INC_sl_WlanConnect __wln__ext - -#define _SL_INC_sl_WlanDisconnect __wln__ext - -#define _SL_INC_sl_WlanProfileAdd __wln__ext - -#define _SL_INC_sl_WlanProfileUpdate __wln__ext - -#define _SL_INC_sl_WlanProfileGet __wln__ext - -#define _SL_INC_sl_WlanProfileDel __wln__ext - -#define _SL_INC_sl_WlanPolicySet __wln__ext - -#define _SL_INC_sl_WlanPolicyGet __wln__ext - -#define _SL_INC_sl_WlanGetNetworkList __wln__ext - -#define _SL_INC_sl_WlanGetExtNetworkList __wln__ext - -#define _SL_INC_sl_WlanRxFilterAdd __wln__ext - -#define _SL_INC_sl_WlanRxFilterSet __wln__ext - -#define _SL_INC_sl_WlanRxFilterGet __wln__ext - -#define _SL_INC_sl_SmartConfigStart __wln - -#define _SL_INC_sl_SmartConfigOptSet __wln__ext - -#define _SL_INC_sl_WlanProvisioning __wln - -#define _SL_INC_sl_WlanSetMode __wln - -#define _SL_INC_sl_WlanSet __wln - -#define _SL_INC_sl_WlanGet __wln - -#define _SL_INC_sl_SmartConfigOptSet __wln__ext - -#define _SL_INC_sl_SmartConfigOptGet __wln__ext - -#define _SL_INC_sl_WlanRxStatStart __wln__ext - -#define _SL_INC_sl_WlanRxStatStop __wln__ext - -#define _SL_INC_sl_WlanRxStatGet __wln__ext - - -/* device */ -#define _SL_INC_sl_Task __int__spwn - -#define _SL_INC_sl_Start __dev - -#define _SL_INC_sl_Stop __dev - -#define _SL_INC_sl_StatusGet __dev - -#ifdef SL_IF_TYPE_UART -#define _SL_INC_sl_DeviceUartSetMode __dev__ext -#endif - -#define _SL_INC_sl_DeviceEventMaskGet __dev__ext - -#define _SL_INC_sl_DeviceEventMaskSet __dev__ext - -#define _SL_INC_sl_DeviceGet __dev__ext - -#define _SL_INC_sl_DeviceSet __dev__ext - -/* netutil */ -#define _SL_INC_sl_NetUtilGet __dev__ext - -#define _SL_INC_sl_NetUtilSet __dev__ext - -#define _SL_INC_sl_NetUtilCmd __dev__ext - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /*OBJINCLUSION_H_ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/protocol.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/protocol.h deleted file mode 100755 index e72a2aa5ac0..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/protocol.h +++ /dev/null @@ -1,1346 +0,0 @@ -/* - * protocol.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*******************************************************************************\ -* -* FILE NAME: protocol.h -* -* DESCRIPTION: Constant and data structure definitions and function -* prototypes for the SL protocol module, which implements -* processing of SimpleLink Commands. -* -* AUTHOR: -* -\*******************************************************************************/ - -#ifndef _SL_PROTOCOL_TYPES_H_ -#define _SL_PROTOCOL_TYPES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/**************************************************************************** -** -** User I/F pools definitions -** -****************************************************************************/ - -/**************************************************************************** -** -** Definitions for SimpleLink Commands -** -****************************************************************************/ - - -/* pattern for LE 8/16/32 or BE*/ -#define H2N_SYNC_PATTERN {0xBBDDEEFF,0x4321,0x34,0x12} -#define H2N_CNYS_PATTERN {0xBBDDEEFF,0x8765,0x78,0x56} - -#define H2N_DUMMY_PATTERN (_u32)0xFFFFFFFF -#define N2H_SYNC_PATTERN (_u32)0xABCDDCBA -#define SYNC_PATTERN_LEN (_u32)sizeof(_u32) -#define UART_SET_MODE_MAGIC_CODE (_u32)0xAA55AA55 -#define SPI_16BITS_BUG(pattern) (_u32)((_u32)pattern & (_u32)0xFFFF7FFF) -#define SPI_8BITS_BUG(pattern) (_u32)((_u32)pattern & (_u32)0xFFFFFF7F) - - -typedef struct -{ - _u16 Opcode; - _u16 Len; -}_SlGenericHeader_t; - - -typedef struct -{ - _u32 Long; - _u16 Short; - _u8 Byte1; - _u8 Byte2; -}_SlSyncPattern_t; - -typedef _SlGenericHeader_t _SlCommandHeader_t; - -typedef struct -{ - _SlGenericHeader_t GenHeader; - _u8 TxPoolCnt; - _u8 DevStatus; - _u16 MinMaxPayload; - _u16 SocketTXFailure; - _u16 SocketNonBlocking; -}_SlResponseHeader_t; - -#define _SL_RESP_SPEC_HDR_SIZE (sizeof(_SlResponseHeader_t) - sizeof(_SlGenericHeader_t)) -#define _SL_RESP_HDR_SIZE sizeof(_SlResponseHeader_t) -#define _SL_CMD_HDR_SIZE sizeof(_SlCommandHeader_t) - -#define _SL_RESP_ARGS_START(_pMsg) (((_SlResponseHeader_t *)(_pMsg)) + 1) - -/* Used only in NWP! */ -typedef struct -{ - _SlCommandHeader_t sl_hdr; - _u8 func_args_start; -} T_SCMD; - -/* _SlResponseHeader_t DevStatus bits */ -#define _SL_DEV_STATUS_BIT_WLAN_CONN 0x01 -#define _SL_DEV_STATUS_BIT_DROPPED_EVENTS 0x02 -#define _SL_DEV_STATUS_BIT_LOCKED 0x04 -#define _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE 0x08 -#define _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED 0x10 -#define _SL_DEV_STATUS_BIT_PRESERVATION 0x20 -#define _SL_DEV_STATUS_BIT_PROVISIONING_ENABLE_API 0x40 - - -/* Internal driver bits status (g_SlDeviceStatus) */ -#define _SL_DRV_STATUS_BIT_RESTART_REQUIRED 0x100 -#define _SL_DRV_STATUS_BIT_DEVICE_STARTED 0x200 -#define _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS 0x400 -#define _SL_DRV_STATUS_BIT_START_IN_PROGRESS 0x800 - -/**************************************************************************** -** OPCODES -****************************************************************************/ -#define SL_IPV4_IPV6_OFFSET ( 9 ) -#define SL_OPCODE_IPV4 ( 0x0 << SL_IPV4_IPV6_OFFSET ) -#define SL_OPCODE_IPV6 ( 0x1 << SL_IPV4_IPV6_OFFSET ) - -#define SL_SYNC_ASYNC_OFFSET ( 10 ) -#define SL_OPCODE_SYNC (0x1 << SL_SYNC_ASYNC_OFFSET ) -#define SL_OPCODE_SILO_OFFSET ( 11 ) -#define SL_OPCODE_SILO_MASK ( 0xF << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_DEVICE ( 0x0 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_WLAN ( 0x1 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_SOCKET ( 0x2 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETAPP ( 0x3 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_FS ( 0x4 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETCFG ( 0x5 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETUTIL ( 0x6 << SL_OPCODE_SILO_OFFSET ) - -#define SL_FAMILY_SHIFT (0x4) -#define SL_FLAGS_MASK (0xF) - -#define SL_OPCODE_DEVICE_INITCOMPLETE 0x0008 -#define SL_OPCODE_DEVICE_ABORT 0x000C -#define SL_OPCODE_DEVICE_STOP_COMMAND 0x8473 -#define SL_OPCODE_DEVICE_STOP_RESPONSE 0x0473 -#define SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE 0x0073 -#define SL_OPCODE_DEVICE_DEVICEASYNCDUMMY 0x0063 - -#define SL_OPCODE_DEVICE_VERSIONREADCOMMAND 0x8470 -#define SL_OPCODE_DEVICE_VERSIONREADRESPONSE 0x0470 -#define SL_OPCODE_DEVICE_DEVICE_ASYNC_GENERAL_ERROR 0x0078 -#define SL_OPCODE_DEVICE_FLOW_CTRL_ASYNC_EVENT 0x0079 - -#define SL_OPCODE_WLAN_WLANCONNECTCOMMAND 0x8C80 -#define SL_OPCODE_WLAN_WLANCONNECTRESPONSE 0x0C80 -#define SL_OPCODE_WLAN_STA_ASYNCCONNECTEDRESPONSE 0x0880 -#define SL_OPCODE_WLAN_P2PCL_ASYNCCONNECTEDRESPONSE 0x0892 - -#define SL_OPCODE_WLAN_WLANDISCONNECTCOMMAND 0x8C81 -#define SL_OPCODE_WLAN_WLANDISCONNECTRESPONSE 0x0C81 -#define SL_OPCODE_WLAN_STA_ASYNCDISCONNECTEDRESPONSE 0x0881 -#define SL_OPCODE_WLAN_P2PCL_ASYNCDISCONNECTEDRESPONSE 0x0894 - -#define SL_OPCODE_WLAN_ASYNC_STA_ADDED 0x082E -#define SL_OPCODE_WLAN_ASYNC_P2PCL_ADDED 0x0896 -#define SL_OPCODE_WLAN_ASYNC_STA_REMOVED 0x082F -#define SL_OPCODE_WLAN_ASYNC_P2PCL_REMOVED 0x0898 - -#define SL_OPCODE_WLAN_P2P_DEV_FOUND 0x0830 -#define SL_OPCODE_WLAN_P2P_CONNECTION_FAILED 0x0831 -#define SL_OPCODE_WLAN_P2P_NEG_REQ_RECEIVED 0x0832 - -#define SL_OPCODE_WLAN_WLANCONNECTEAPCOMMAND 0x8C82 -#define SL_OPCODE_WLAN_WLANCONNECTEAPCRESPONSE 0x0C82 -#define SL_OPCODE_WLAN_PROFILEADDCOMMAND 0x8C83 -#define SL_OPCODE_WLAN_PROFILEADDRESPONSE 0x0C83 -#define SL_OPCODE_WLAN_PROFILEUPDATECOMMAND 0x8CC2 -#define SL_OPCODE_WLAN_PROFILEUPDATERESPONSE 0x0CC2 -#define SL_OPCODE_WLAN_PROFILEEAPUPDATECOMMAND 0x8CC3 -#define SL_OPCODE_WLAN_PROFILEEAPUPDATERESPONSE 0x0CC0 -#define SL_OPCODE_WLAN_PROFILEGETCOMMAND 0x8C84 -#define SL_OPCODE_WLAN_PROFILEGETRESPONSE 0x0C84 -#define SL_OPCODE_WLAN_PROFILEDELCOMMAND 0x8C85 -#define SL_OPCODE_WLAN_PROFILEDELRESPONSE 0x0C85 -#define SL_OPCODE_WLAN_POLICYSETCOMMAND 0x8C86 -#define SL_OPCODE_WLAN_POLICYSETRESPONSE 0x0C86 -#define SL_OPCODE_WLAN_POLICYGETCOMMAND 0x8C87 -#define SL_OPCODE_WLAN_POLICYGETRESPONSE 0x0C87 -#define SL_OPCODE_WLAN_FILTERADD 0x8C88 -#define SL_OPCODE_WLAN_FILTERADDRESPONSE 0x0C88 -#define SL_OPCODE_WLAN_FILTERGET 0x8C89 -#define SL_OPCODE_WLAN_FILTERGETRESPONSE 0x0C89 -#define SL_OPCODE_WLAN_FILTERDELETE 0x8C8A -#define SL_OPCODE_WLAN_FILTERDELETERESPOSNE 0x0C8A -#define SL_OPCODE_WLAN_WLANGETSTATUSCOMMAND 0x8C8F -#define SL_OPCODE_WLAN_WLANGETSTATUSRESPONSE 0x0C8F -#define SL_OPCODE_WLAN_STARTTXCONTINUESCOMMAND 0x8CAA -#define SL_OPCODE_WLAN_STARTTXCONTINUESRESPONSE 0x0CAA -#define SL_OPCODE_WLAN_STOPTXCONTINUESCOMMAND 0x8CAB -#define SL_OPCODE_WLAN_STOPTXCONTINUESRESPONSE 0x0CAB -#define SL_OPCODE_WLAN_STARTRXSTATCOMMAND 0x8CAC -#define SL_OPCODE_WLAN_STARTRXSTATRESPONSE 0x0CAC -#define SL_OPCODE_WLAN_STOPRXSTATCOMMAND 0x8CAD -#define SL_OPCODE_WLAN_STOPRXSTATRESPONSE 0x0CAD -#define SL_OPCODE_WLAN_GETRXSTATCOMMAND 0x8CAF -#define SL_OPCODE_WLAN_GETRXSTATRESPONSE 0x0CAF -#define SL_OPCODE_WLAN_POLICYSETCOMMANDNEW 0x8CB0 -#define SL_OPCODE_WLAN_POLICYSETRESPONSENEW 0x0CB0 -#define SL_OPCODE_WLAN_POLICYGETCOMMANDNEW 0x8CB1 -#define SL_OPCODE_WLAN_POLICYGETRESPONSENEW 0x0CB1 - -#define SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE 0x08B2 -#define SL_OPCODE_WLAN_SET_MODE 0x8CB4 -#define SL_OPCODE_WLAN_SET_MODE_RESPONSE 0x0CB4 -#define SL_OPCODE_WLAN_CFG_SET 0x8CB5 -#define SL_OPCODE_WLAN_CFG_SET_RESPONSE 0x0CB5 -#define SL_OPCODE_WLAN_CFG_GET 0x8CB6 -#define SL_OPCODE_WLAN_CFG_GET_RESPONSE 0x0CB6 -#define SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND 0x8C67 -#define SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND_RESPONSE 0x0C67 -#define SL_OPCODE_WLAN_RESERVED_RESPONSE 0x08BA - -#define SL_OPCODE_SOCKET_SOCKET 0x9401 -#define SL_OPCODE_SOCKET_SOCKETRESPONSE 0x1401 -#define SL_OPCODE_SOCKET_CLOSE 0x9402 -#define SL_OPCODE_SOCKET_CLOSERESPONSE 0x1402 -#define SL_OPCODE_SOCKET_ACCEPT 0x9403 -#define SL_OPCODE_SOCKET_ACCEPTRESPONSE 0x1403 -#define SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE 0x1003 -#define SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE_V6 0x1203 -#define SL_OPCODE_SOCKET_BIND 0x9404 -#define SL_OPCODE_SOCKET_BIND_V6 0x9604 -#define SL_OPCODE_SOCKET_BINDRESPONSE 0x1404 -#define SL_OPCODE_SOCKET_LISTEN 0x9405 -#define SL_OPCODE_SOCKET_LISTENRESPONSE 0x1405 -#define SL_OPCODE_SOCKET_CONNECT 0x9406 -#define SL_OPCODE_SOCKET_CONNECT_V6 0x9606 -#define SL_OPCODE_SOCKET_CONNECTRESPONSE 0x1406 -#define SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE 0x1006 -#define SL_OPCODE_SOCKET_SELECT 0x9407 -#define SL_OPCODE_SOCKET_SELECTRESPONSE 0x1407 -#define SL_OPCODE_SOCKET_SELECTASYNCRESPONSE 0x1007 -#define SL_OPCODE_SOCKET_SETSOCKOPT 0x9408 -#define SL_OPCODE_SOCKET_SETSOCKOPTRESPONSE 0x1408 -#define SL_OPCODE_SOCKET_GETSOCKOPT 0x9409 -#define SL_OPCODE_SOCKET_GETSOCKOPTRESPONSE 0x1409 -#define SL_OPCODE_SOCKET_RECV 0x940A -#define SL_OPCODE_SOCKET_RECVASYNCRESPONSE 0x100A -#define SL_OPCODE_SOCKET_RECVFROM 0x940B -#define SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE 0x100B -#define SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 0x120B -#define SL_OPCODE_SOCKET_SEND 0x940C -#define SL_OPCODE_SOCKET_SENDTO 0x940D -#define SL_OPCODE_SOCKET_SENDTO_V6 0x960D -#define SL_OPCODE_SOCKET_TXFAILEDASYNCRESPONSE 0x100E -#define SL_OPCODE_SOCKET_SOCKETASYNCEVENT 0x100F -#define SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT 0x1010 -#define SL_OPCODE_NETAPP_START_COMMAND 0x9C0A -#define SL_OPCODE_NETAPP_START_RESPONSE 0x1C0A -#define SL_OPCODE_NETAPP_NETAPPSTARTRESPONSE 0x1C0A -#define SL_OPCODE_NETAPP_STOP_COMMAND 0x9C61 -#define SL_OPCODE_NETAPP_STOP_RESPONSE 0x1C61 -#define SL_OPCODE_NETAPP_NETAPPSET 0x9C0B -#define SL_OPCODE_NETAPP_NETAPPSETRESPONSE 0x1C0B -#define SL_OPCODE_NETAPP_NETAPPGET 0x9C27 -#define SL_OPCODE_NETAPP_NETAPPGETRESPONSE 0x1C27 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAME 0x9C20 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMERESPONSE 0x1C20 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE 0x1820 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE_V6 0x1A20 -#define SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE 0x9C71 -#define SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE_RESPONSE 0x1C72 -#define SL_OPCODE_NETAPP_MDNSREGISTERSERVICE 0x9C34 -#define SL_OPCODE_NETAPP_MDNSREGISTERSERVICERESPONSE 0x1C34 -#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICE 0x9C35 -#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICERESPONSE 0x1C35 -#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE 0x1835 -#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE_V6 0x1A35 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDR 0x9C26 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDR_V6 0x9E26 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDRRESPONSE 0x1C26 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDRASYNCRESPONSE 0x1826 -#define SL_OPCODE_NETAPP_PINGSTART 0x9C21 -#define SL_OPCODE_NETAPP_PINGSTART_V6 0x9E21 -#define SL_OPCODE_NETAPP_PINGSTARTRESPONSE 0x1C21 -#define SL_OPCODE_NETAPP_PINGREPORTREQUEST 0x9C22 -#define SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE 0x1822 -#define SL_OPCODE_NETAPP_ARPFLUSH 0x9C24 -#define SL_OPCODE_NETAPP_ARPFLUSHRESPONSE 0x1C24 -#define SL_OPCODE_NETAPP_NDFLUSH_V6 0x9EC2 -#define SL_OPCODE_NETAPP_NDFLUSHHRESPONSE_V6 0x1EC3 -#define SL_OPCODE_NETAPP_IPACQUIRED 0x1825 -#define SL_OPCODE_NETAPP_IPV4_LOST 0x1832 -#define SL_OPCODE_NETAPP_DHCP_IPV4_ACQUIRE_TIMEOUT 0x1833 -#define SL_OPCODE_LINK_QUALITY_EVENT 0x1834 -#define SL_OPCODE_NETAPP_IPACQUIRED_V6 0x1A25 -#define SL_OPCODE_NETAPP_IPV6_LOST_V6 0x1A32 -#define SL_OPCODE_NETAPP_IPERFSTARTCOMMAND 0x9C28 -#define SL_OPCODE_NETAPP_IPERFSTARTRESPONSE 0x1C28 -#define SL_OPCODE_NETAPP_IPERFSTOPCOMMAND 0x9C29 -#define SL_OPCODE_NETAPP_IPERFSTOPRESPONSE 0x1C29 -#define SL_OPCODE_NETAPP_CTESTSTARTCOMMAND 0x9C2A -#define SL_OPCODE_NETAPP_CTESTSTARTRESPONSE 0x1C2A -#define SL_OPCODE_NETAPP_CTESTASYNCRESPONSE 0x182A -#define SL_OPCODE_NETAPP_CTESTSTOPCOMMAND 0x9C2B -#define SL_OPCODE_NETAPP_CTESTSTOPRESPONSE 0x1C2B -#define SL_OPCODE_NETAPP_IP_LEASED 0x182C -#define SL_OPCODE_NETAPP_IP_RELEASED 0x182D -#define SL_OPCODE_NETAPP_HTTPGETTOKENVALUE 0x182E -#define SL_OPCODE_NETAPP_HTTPSENDTOKENVALUE 0x9C2F -#define SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE 0x1830 -#define SL_OPCODE_NETAPP_IP_COLLISION 0x1831 -#define SL_OPCODE_NETAPP_RESERVED1 0x18C4 -#define SL_OPCODE_NETAPP_RESERVED2 0x1AC5 -#define SL_OPCODE_NETAPP_RESERVED3 0x1AC6 - -#define SL_OPCODE_NETAPP_REQUEST 0x1878 -#define SL_OPCODE_NETAPP_RESPONSE 0x9C78 -#define SL_OPCODE_NETAPP_SEND 0x9C79 -#define SL_OPCODE_NETAPP_SENDRESPONSE 0x1C79 -#define SL_OPCODE_NETAPP_RECEIVEREQUEST 0x9C7A -#define SL_OPCODE_NETAPP_RECEIVE 0x187B - -#define SL_OPCODE_NVMEM_FILEOPEN 0xA43C -#define SL_OPCODE_NVMEM_FILEOPENRESPONSE 0x243C -#define SL_OPCODE_NVMEM_FILECLOSE 0xA43D -#define SL_OPCODE_NVMEM_FILECLOSERESPONSE 0x243D -#define SL_OPCODE_NVMEM_FILEREADCOMMAND 0xA440 -#define SL_OPCODE_NVMEM_FILEREADRESPONSE 0x2440 -#define SL_OPCODE_NVMEM_FILEWRITECOMMAND 0xA441 -#define SL_OPCODE_NVMEM_FILEWRITERESPONSE 0x2441 -#define SL_OPCODE_NVMEM_FILEGETINFOCOMMAND 0xA442 -#define SL_OPCODE_NVMEM_FILEGETINFORESPONSE 0x2442 -#define SL_OPCODE_NVMEM_FILEDELCOMMAND 0xA443 -#define SL_OPCODE_NVMEM_FILEDELRESPONSE 0x2443 -#define SL_OPCODE_NVMEM_NVMEMFORMATCOMMAND 0xA444 -#define SL_OPCODE_NVMEM_NVMEMFORMATRESPONSE 0x2444 -#define SL_OPCODE_NVMEM_NVMEMGETFILELISTCOMMAND 0xA448 -#define SL_OPCODE_NVMEM_NVMEMGETFILELISTRESPONSE 0x2448 - -#define SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND 0xA44A -#define SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGRESPONSE 0x244A -#define SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLCOMMAND 0xA44B -#define SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLRESPONSE 0x244B -#define SL_OPCODE_NVMEM_NVMEMBUNDLECONTROLCOMMAND 0xA44C -#define SL_OPCODE_NVMEM_NVMEMBUNDLECONTROLRESPONSE 0x244C - - -#define SL_OPCODE_DEVICE_SETDEBUGLEVELCOMMAND 0x846A -#define SL_OPCODE_DEVICE_SETDEBUGLEVELRESPONSE 0x046A - -#define SL_OPCODE_DEVICE_NETCFG_SET_COMMAND 0x8432 -#define SL_OPCODE_DEVICE_NETCFG_SET_RESPONSE 0x0432 -#define SL_OPCODE_DEVICE_NETCFG_GET_COMMAND 0x8433 -#define SL_OPCODE_DEVICE_NETCFG_GET_RESPONSE 0x0433 -/* */ -#define SL_OPCODE_DEVICE_SETUARTMODECOMMAND 0x846B -#define SL_OPCODE_DEVICE_SETUARTMODERESPONSE 0x046B -#define SL_OPCODE_DEVICE_SSISIZESETCOMMAND 0x846B -#define SL_OPCODE_DEVICE_SSISIZESETRESPONSE 0x046B - -/* */ -#define SL_OPCODE_DEVICE_EVENTMASKSET 0x8464 -#define SL_OPCODE_DEVICE_EVENTMASKSETRESPONSE 0x0464 -#define SL_OPCODE_DEVICE_EVENTMASKGET 0x8465 -#define SL_OPCODE_DEVICE_EVENTMASKGETRESPONSE 0x0465 - -#define SL_OPCODE_DEVICE_DEVICEGET 0x8466 -#define SL_OPCODE_DEVICE_DEVICEGETRESPONSE 0x0466 -#define SL_OPCODE_DEVICE_DEVICESET 0x84B7 -#define SL_OPCODE_DEVICE_DEVICESETRESPONSE 0x04B7 - -#define SL_OPCODE_WLAN_SCANRESULTSGETCOMMAND 0x8C8C -#define SL_OPCODE_WLAN_SCANRESULTSGETRESPONSE 0x0C8C -#define SL_OPCODE_WLAN_EXTSCANRESULTSGETCOMMAND 0x8C8D -#define SL_OPCODE_WLAN_EXTSCANRESULTSGETRESPONSE 0x0C8D -#define SL_OPCODE_WLAN_SMARTCONFIGOPTGET 0x8C8E -#define SL_OPCODE_WLAN_SMARTCONFIGOPTGETRESPONSE 0x0C8E - -#define SL_OPCODE_WLAN_PROVISIONING_COMMAND 0x8C98 -#define SL_OPCODE_WLAN_PROVISIONING_RESPONSE 0x0C98 -#define SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT 0x0099 -#define SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT 0x089A - -#define SL_OPCODE_FREE_BSD_RECV_BUFFER 0xCCCB -#define SL_OPCODE_FREE_NON_BSD_READ_BUFFER 0xCCCD - - -/* Rx Filters opcodes */ -#define SL_OPCODE_WLAN_WLANRXFILTERADDCOMMAND 0x8C6C -#define SL_OPCODE_WLAN_WLANRXFILTERADDRESPONSE 0x0C6C -#define SL_OPCODE_WLAN_WLANRXFILTERGETSTATISTICSINFOCOMMAND 0x8C6E -#define SL_OPCODE_WLAN_WLANRXFILTERGETSTATISTICSINFORESPONSE 0x0C6E -#define SL_OPCODE_WLAN_WLANRXFILTERGETINFO 0x8C70 -#define SL_OPCODE_WLAN_WLANRXFILTERGETINFORESPONSE 0x0C70 -#define SL_OPCODE_WLAN_RX_FILTER_ASYNC_RESPONSE 0x089D - -/* Utils */ -#define SL_OPCODE_NETUTIL_SET 0xB4BE -#define SL_OPCODE_NETUTIL_SETRESPONSE 0x34BE -#define SL_OPCODE_NETUTIL_GET 0xB4C0 -#define SL_OPCODE_NETUTIL_GETRESPONSE 0x34C0 -#define SL_OPCODE_NETUTIL_COMMAND 0xB4C1 -#define SL_OPCODE_NETUTIL_COMMANDRESPONSE 0x34C1 -#define SL_OPCODE_NETUTIL_COMMANDASYNCRESPONSE 0x30C1 - -/******************************************************************************************/ -/* Device structs */ -/******************************************************************************************/ -typedef _u32 InitStatus_t; - -typedef struct -{ - _i32 Status; - _i32 ChipId; - _i32 MoreData; -}InitComplete_t; - -typedef struct -{ - _i16 status; - _u16 sender; -}_BasicResponse_t; - -typedef struct -{ - _u32 SessionNumber; - _u16 Caller; - _u16 Padding; -}SlDeviceResetRequestData_t; - -typedef struct -{ - _u16 Timeout; - _u16 Padding; -}SlDeviceStopCommand_t; - -typedef struct -{ - _u32 Group; - _u32 Mask; -}SlDeviceMaskEventSetCommand_t; - -typedef _BasicResponse_t _DevMaskEventSetResponse_t; - -typedef struct -{ - _u32 Group; -} SlDeviceMaskEventGetCommand_t; - -typedef struct -{ - _u32 Group; - _u32 Mask; -} SlDeviceMaskEventGetResponse_t; - -typedef struct -{ - _u32 Group; -} SlDeviceStatusGetCommand_t; - -typedef struct -{ - _u32 Group; - _u32 Status; -} SlDeviceStatusGetResponse_t; - -typedef struct -{ - _u32 ChipId; - _u32 FwVersion[4]; - _u8 PhyVersion[4]; -} SlDeviceVersionReadResponsePart_t; - -typedef struct -{ - SlDeviceVersionReadResponsePart_t part; - _u32 NwpVersion[4]; - _u16 RomVersion; - _u16 Padding; -} SlDeviceVersionReadResponseFull_t; - -typedef struct -{ - _u16 MinTxPayloadSize; - _u8 padding[6]; -} SlDeviceFlowCtrlAsyncEvent_t; - -typedef struct -{ - _u32 BaudRate; - _u8 FlowControlEnable; -} SlDeviceUartSetModeCommand_t; - -typedef _BasicResponse_t SlDeviceUartSetModeResponse_t; - -/******************************************************/ - -typedef struct -{ - _u8 SsiSizeInBytes; - _u8 Padding[3]; -}_StellarisSsiSizeSet_t; - -/*****************************************************************************************/ -/* WLAN structs */ -/*****************************************************************************************/ -#define MAXIMAL_PASSWORD_LENGTH (64) - -typedef struct -{ - _u8 ProvisioningCmd; - _u8 RequestedRoleAfterSuccess; - _u16 InactivityTimeoutSec; - _u32 Flags; -} SlWlanProvisioningParams_t; - -typedef struct{ - _u8 SecType; - _u8 SsidLen; - _u8 Bssid[6]; - _u8 PasswordLen; -} SlWlanConnectCommon_t; - -#define SSID_STRING(pCmd) (_i8 *)((SlWlanConnectCommon_t *)(pCmd) + 1) -#define PASSWORD_STRING(pCmd) (SSID_STRING(pCmd) + ((SlWlanConnectCommon_t *)(pCmd))->SsidLen) - -typedef struct{ - SlWlanConnectCommon_t Common; - _u8 UserLen; - _u8 AnonUserLen; - _u8 CertIndex; - _u32 EapBitmask; -} SlWlanConnectEapCommand_t; - -#define EAP_SSID_STRING(pCmd) (_i8 *)((SlWlanConnectEapCommand_t *)(pCmd) + 1) -#define EAP_PASSWORD_STRING(pCmd) (EAP_SSID_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->Common.SsidLen) -#define EAP_USER_STRING(pCmd) (EAP_PASSWORD_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->Common.PasswordLen) -#define EAP_ANON_USER_STRING(pCmd) (EAP_USER_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->UserLen) - -typedef struct -{ - _u8 PolicyType; - _u8 Padding; - _u8 PolicyOption; - _u8 PolicyOptionLen; -} SlWlanPolicySetGet_t; - -typedef struct{ - _u32 MinDwellTime; - _u32 MaxDwellTime; - _u32 NumProbeResponse; - _u32 G_Channels_mask; - _i32 RssiThershold; - _i32 SnrThershold; - _i32 DefaultTXPower; - _u16 IntervalList[16]; -} SlWlanScanParamSetCommand_t; - -typedef struct{ - _i16 SecType; - _u8 SsidLen; - _u8 Priority; - _u8 Bssid[6]; - _u8 PasswordLen; - _u8 WepKeyId; -} SlWlanAddGetProfile_t; - -typedef struct{ - SlWlanAddGetProfile_t Common; - _u8 UserLen; - _u8 AnonUserLen; - _u8 CertIndex; - _u8 padding; - _u32 EapBitmask; -} SlWlanAddGetEapProfile_t; - - -typedef struct{ - _i16 SecType; - _u8 SsidLen; - _u8 Priority; - _u8 Bssid[6]; - _u8 PasswordLen; - _u8 WepKeyId; - _u32 Index; - _u8 UserLen; - _u8 AnonUserLen; - _u8 CertIndex; - _u8 padding; - _u32 EapBitmask; -} SlWlanUpdateProfile_t; - -#define PROFILE_SSID_STRING(pCmd) ((_i8 *)((SlWlanAddGetProfile_t *)(pCmd) + 1)) -#define PROFILE_PASSWORD_STRING(pCmd) (PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetProfile_t *)(pCmd))->SsidLen) - -#define EAP_PROFILE_SSID_STRING(pCmd) (_i8 *)((SlWlanAddGetEapProfile_t *)(pCmd) + 1) -#define EAP_PROFILE_PASSWORD_STRING(pCmd) (EAP_PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->Common.SsidLen) -#define EAP_PROFILE_USER_STRING(pCmd) (EAP_PROFILE_PASSWORD_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->Common.PasswordLen) -#define EAP_PROFILE_ANON_USER_STRING(pCmd) (EAP_PROFILE_USER_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->UserLen) - -#define PROFILE_SSID_STRING(pCmd) ((_i8 *)((SlWlanAddGetProfile_t *)(pCmd) + 1)) -#define PROFILE_PASSWORD_STRING(pCmd) (PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetProfile_t *)(pCmd))->SsidLen) - -#define UPDATE_PROFILE_SSID_STRING(pCmd) (_i8 *)((SlWlanUpdateProfile_t *)(pCmd) + 1) -#define UPDATE_PROFILE_PASSWORD_STRING(pCmd) (UPDATE_PROFILE_SSID_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->SsidLen) -#define UPDATE_PROFILE_USER_STRING(pCmd) (UPDATE_PROFILE_PASSWORD_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->PasswordLen) -#define UPDATE_PROFILE_ANON_USER_STRING(pCmd) (UPDATE_PROFILE_USER_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->UserLen) - - -typedef struct -{ - _u8 Index; - _u8 Padding[3]; -} SlWlanProfileDelGetCommand_t; - -typedef _BasicResponse_t _WlanGetNetworkListResponse_t; - -typedef struct -{ - _u8 Index; - _u8 Count; - _i8 padding[2]; -} SlWlanGetNetworkListCommand_t; - -typedef _BasicResponse_t _WlanGetExtNetworkListResponse_t; - -typedef struct -{ - _u8 Index; - _u8 Count; - _i8 padding[2]; -} SlWlanGetExtNetworkListCommand_t; - -typedef struct -{ - _u32 GroupIdBitmask; - _u8 Cipher; - _u8 PublicKeyLen; - _u8 Padding[2]; -} SlWlanSmartConfigParams_t; - -#define SMART_CONFIG_START_PUBLIC_KEY_STRING(pCmd) ((_i8 *)((SlWlanSmartConfigParams_t *)(pCmd) + 1)) - -typedef struct -{ - _u8 Mode; - _u8 Padding[3]; -} SlWlanSetMode_t; - -typedef struct -{ - _u16 Status; - _u16 ConfigId; - _u16 ConfigOpt; - _u16 ConfigLen; -} SlWlanCfgSetGet_t; - - -/* ******************************************************************************/ -/* RX filters - Start */ -/* ******************************************************************************/ - -typedef struct -{ - SlWlanRxFilterRuleType_t RuleType; - SlWlanRxFilterFlags_u Flags; - SlWlanRxFilterID_t FilterId; - _u8 Padding; - SlWlanRxFilterRule_u Rule; - SlWlanRxFilterTrigger_t Trigger; - SlWlanRxFilterAction_t Action; -} SlWlanRxFilterAddCommand_t; - -typedef struct -{ - SlWlanRxFilterID_t FilterId; - _i16 Status; - _u8 Padding[1]; -} SlWlanRxFilterAddCommandReponse_t; - -typedef struct -{ - _i16 Status; - _u8 Padding[2]; -} SlWlanRxFilterSetCommandReponse_t; - -typedef struct -{ - _i16 Status; - _u16 OutputBufferLength; - -} SlWlanRxFilterGetCommandReponse_t; - - -/* ******************************************************************************/ -/* RX filters -- End */ -/* ******************************************************************************/ - -typedef struct -{ - _u16 Status; - _u8 WlanRole; /* 0 = station, 2 = AP */ - _u8 Ipv6Enabled; - _u8 DhcpEnabled; - - _u32 Global[4]; - _u32 Local[4]; - _u32 DnsServer[4]; - _u8 DhcpState; -} SlNetappIpV6configRetArgs_t; - -typedef struct -{ - _u8 Ip[4]; - _u8 IpMask[4]; - _u8 IpGateway[4]; - _u8 IpDnsServer[4]; - _u8 IpStart[4]; - _u8 IpEnd[4]; -} SlNetCfgIpV4APArgs_t; - -typedef struct -{ - _u16 Status; - _u8 MacAddr[6]; -} SlMacAddressSetGet_t; - -typedef struct -{ - _u16 Status; - _u16 ConfigId; - _u16 ConfigOpt; - _u16 ConfigLen; -} SlNetCfgSetGet_t; - -typedef struct -{ - _u16 Status; - _u16 DeviceSetId; - _u16 Option; - _u16 ConfigLen; -} SlDeviceSetGet_t; - - -/******************************************************************************************/ -/* Socket structs */ -/******************************************************************************************/ - -typedef struct -{ - _u8 Domain; - _u8 Type; - _u8 Protocol; - _u8 Padding; -} SlSocketCommand_t; - -typedef struct -{ - _i16 StatusOrLen; - _u8 Sd; - _u8 Padding; -} SlSocketResponse_t; - -typedef struct -{ - _u8 Sd; - _u8 Family; - _u8 Padding1; - _u8 Padding2; -} SlAcceptCommand_t; - -typedef struct -{ - _i16 StatusOrLen; - _u8 Sd; - _u8 Family; - _u16 Port; - _u16 PaddingOrAddr; - _u32 Address; -} SlSocketAddrAsyncIPv4Response_t; - -typedef struct -{ - _i16 StatusOrLen; - _u8 Sd; - _u8 Family; - _u16 Port; - _u8 Address[6]; -} SlSocketAddrAsyncIPv6EUI48Response_t; - -typedef struct -{ - _i16 StatusOrLen; - _u8 Sd; - _u8 Family; - _u16 Port; - _u16 PaddingOrAddr; - _u32 Address[4]; -} SlSocketAddrAsyncIPv6Response_t; - -typedef struct -{ - _i16 LenOrPadding; - _u8 Sd; - _u8 FamilyAndFlags; - _u16 Port; - _u16 PaddingOrAddr; - _u32 Address; -} SlSocketAddrIPv4Command_t; - -typedef struct -{ - _i16 LenOrPadding; - _u8 Sd; - _u8 FamilyAndFlags; - _u16 Port; - _u8 Address[6]; -} SlSocketAddrIPv6EUI48Command_t; - -typedef struct -{ - _i16 LenOrPadding; - _u8 Sd; - _u8 FamilyAndFlags; - _u16 Port; - _u16 PaddingOrAddr; - _u32 Address[4]; -} SlSocketAddrIPv6Command_t; - -typedef union { - SlSocketAddrIPv4Command_t IpV4; - SlSocketAddrIPv6EUI48Command_t IpV6EUI48; -#ifdef SL_SUPPORT_IPV6 - SlSocketAddrIPv6Command_t IpV6; -#endif -} SlSocketAddrCommand_u; - -typedef union { - SlSocketAddrAsyncIPv4Response_t IpV4; - SlSocketAddrAsyncIPv6EUI48Response_t IpV6EUI48; -#ifdef SL_SUPPORT_IPV6 - SlSocketAddrAsyncIPv6Response_t IpV6; -#endif -} SlSocketAddrResponse_u; - -typedef struct -{ - _u8 Sd; - _u8 Backlog; - _u8 Padding1; - _u8 Padding2; -} SlListenCommand_t; - -typedef struct -{ - _u8 Sd; - _u8 Padding0; - _u8 Padding1; - _u8 Padding2; -} SlCloseCommand_t; - -typedef struct -{ - _u8 Nfds; - _u8 ReadFdsCount; - _u8 WriteFdsCount; - _u8 Padding; - _u16 ReadFds; - _u16 WriteFds; - _u16 tv_usec; - _u16 tv_sec; -} SlSelectCommand_t; - -typedef struct -{ - _u16 Status; - _u8 ReadFdsCount; - _u8 WriteFdsCount; - _u16 ReadFds; - _u16 WriteFds; -} SlSelectAsyncResponse_t; - -typedef struct -{ - _u8 Sd; - _u8 Level; - _u8 OptionName; - _u8 OptionLen; -} SlSetSockOptCommand_t; - -typedef struct -{ - _u8 Sd; - _u8 Level; - _u8 OptionName; - _u8 OptionLen; -} SlGetSockOptCommand_t; - -typedef struct -{ - _i16 Status; - _u8 Sd; - _u8 OptionLen; -} SlGetSockOptResponse_t; - -typedef struct -{ - _u16 StatusOrLen; - _u8 Sd; - _u8 FamilyAndFlags; -} SlSendRecvCommand_t; - -/***************************************************************************************** -* NETAPP structs -******************************************************************************************/ - -typedef _BasicResponse_t _NetAppStartStopResponse_t; - -typedef struct -{ - _u32 AppId; -}_NetAppStartStopCommand_t; - -typedef struct -{ - _u16 Status; - _u16 AppId; - _u16 ConfigOpt; - _u16 ConfigLen; -} SlNetAppSetGet_t; -typedef struct -{ - _u16 PortNumber; -} SlNetAppHttpServerGetSetPortNum_t; - -typedef struct -{ - _u8 AuthEnable; -} SlNetAppHttpServerGetSetAuthEnable_t; - -typedef struct _SlNetAppHttpServerGetToken_t -{ - _u8 TokenNameLen; - _u8 Padd1; - _u16 Padd2; -}SlNetAppHttpServerGetToken_t; - -typedef struct _SlNetAppHttpServerSendToken_t -{ - _u8 TokenValueLen; - _u8 TokenNameLen; - _u8 TokenName[SL_NETAPP_MAX_TOKEN_NAME_LEN]; - _u16 Padd; -} SlNetAppHttpServerSendToken_t; - -typedef struct _SlNetAppHttpServerPostToken_t -{ - _u8 PostActionLen; - _u8 TokenNameLen; - _u8 TokenValueLen; - _u8 padding; -} SlNetAppHttpServerPostToken_t; - -/***************************************************************************************** -* NETAPP Request/Response/Send/Receive -******************************************************************************************/ -typedef struct _SlProtocolNetAppRequest_t -{ - _u8 AppId; - _u8 RequestType; - _u16 Handle; - _u16 MetadataLen; - _u16 PayloadLen; - _u32 Flags; -} SlProtocolNetAppRequest_t; - -typedef struct _SlProtocolNetAppResponse_t -{ - _u16 Handle; - _u16 status; - _u16 MetadataLen; - _u16 PayloadLen; - _u32 Flags; -} SlProtocolNetAppResponse_t; - -typedef struct _SlProtocolNetAppSend_t -{ - _u16 Handle; - _u16 DataLen; /* can be data payload or metadata, depends on bit 1 in flags */ - _u32 Flags; -} SlProtocolNetAppSend_t; - -typedef struct _SlProtocolNetAppReceiveRequest_t -{ - _u16 Handle; - _u16 MaxBufferLen; - _u32 Flags; -} SlProtocolNetAppReceiveRequest_t; - -typedef struct _SlProtocolNetAppReceive_t -{ - _u16 Handle; - _u16 PayloadLen; - _u32 Flags; -} SlProtocolNetAppReceive_t; - -typedef struct -{ - _u16 Len; - _u8 Family; - _u8 Padding; -} NetAppGetHostByNameCommand_t; - -typedef struct -{ - _u16 Status; - _u16 Padding; - _u32 Ip0; - _u32 Ip1; - _u32 Ip2; - _u32 Ip3; -} NetAppGetHostByNameIPv6AsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u8 Padding1; - _u8 Padding2; - _u32 Ip0; -} NetAppGetHostByNameIPv4AsyncResponse_t; - -typedef enum -{ - CTST_BSD_UDP_TX, - CTST_BSD_UDP_RX, - CTST_BSD_TCP_TX, - CTST_BSD_TCP_RX, - CTST_BSD_TCP_SERVER_BI_DIR, - CTST_BSD_TCP_CLIENT_BI_DIR, - CTST_BSD_UDP_BI_DIR, - CTST_BSD_RAW_TX, - CTST_BSD_RAW_RX, - CTST_BSD_RAW_BI_DIR, - CTST_BSD_SECURED_TCP_TX, - CTST_BSD_SECURED_TCP_RX, - CTST_BSD_SECURED_TCP_SERVER_BI_DIR, - CTST_BSD_SECURED_TCP_CLIENT_BI_DIR, - CTST_BSD_UDP_TX_IPV6, - CTST_BSD_UDP_RX_IPV6, - CTST_BSD_TCP_TX_IPV6, - CTST_BSD_TCP_RX_IPV6, - CTST_BSD_TCP_SERVER_BI_DIR_IPV6, - CTST_BSD_TCP_CLIENT_BI_DIR_IPV6, - CTST_BSD_UDP_BI_DIR_IPV6, - CTST_BSD_RAW_TX_IPV6, - CTST_BSD_RAW_RX_IPV6, - CTST_BSD_RAW_BI_DIR_IPV6, - CTST_BSD_SECURED_TCP_TX_IPV6, - CTST_BSD_SECURED_TCP_RX_IPV6, - CTST_BSD_SECURED_TCP_SERVER_BI_DIR_IPV6, - CTST_BSD_SECURED_TCP_CLIENT_BI_DIR_IPV6, - CTST_RAW_TX, - CTST_RAW_RX - }CommTest_e; - -typedef struct _sl_protocol_CtestStartCommand_t -{ - _u32 Test; - _u16 DestPort; - _u16 SrcPort; - _u32 DestAddr[4]; - _u32 PayloadSize; - _u32 Timeout; - _u32 CsEnabled; - _u32 Secure; - _u32 RawProtocol; - _u8 Reserved1[4]; -}_CtestStartCommand_t; - -typedef struct -{ - _u8 Test; - _u8 Socket; - _i16 Status; - _u32 StartTime; - _u32 EndTime; - _u16 TxKbitsSec; - _u16 RxKbitsSec; - _u32 OutOfOrderPackets; - _u32 MissedPackets; - _i16 Token; -}_CtestAsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u16 RttMin; - _u16 RttMax; - _u16 RttAvg; - _u32 NumSuccsessPings; - _u32 NumSendsPings; - _u32 TestTime; -} SlPingReportResponse_t; - -typedef struct -{ - _u32 Ip; - _u32 Gateway; - _u32 Dns; -} IpV4AcquiredAsync_t; - -typedef enum -{ - ACQUIRED_IPV6_LOCAL = 1, - ACQUIRED_IPV6_GLOBAL -}IpV6AcquiredType_e; - -typedef struct -{ - _u32 Type; - _u32 Ip[4]; - _u32 Gateway[4]; - _u32 Dns[4]; -} IpV6AcquiredAsync_t; - -typedef union -{ - SlSocketCommand_t EventMask; - SlSendRecvCommand_t DeviceInit; -}_device_commands_t; - -/***************************************************************************************** -* FS structs -******************************************************************************************/ - -typedef struct -{ - _u32 FileHandle; - _u32 Offset; - _u16 Len; - _u16 Padding; -} SlFsReadCommand_t; - -typedef struct -{ - _u32 Mode; - _u32 Token; -} SlFsOpenCommand_t; - -typedef struct -{ - _u32 FileHandle; - _u32 Token; -} SlFsOpenResponse_t; - - -typedef struct -{ - _u32 FileHandle; - _u32 CertificFileNameLength; - _u32 SignatureLen; -} SlFsCloseCommand_t; - -typedef _BasicResponse_t SlFsReadResponse_t; -typedef _BasicResponse_t SlFsDeleteResponse_t; -typedef _BasicResponse_t SlFsCloseResponse_t; - -typedef struct -{ - _u16 Status; - _u16 Flags; - _u32 FileLen; - _u32 AllocatedLen; - _u32 Token[4]; - _u32 FileStorageSize; /* The total size that the file required on the storage */ - _u32 FileWriteCounter; /* number of times in which the file have been written successfully */ -} SlFsGetInfoResponse_t; - -typedef struct -{ - _u8 DeviceID; - _u8 Padding[3]; -} SlFsFormatCommand_t; - -typedef _BasicResponse_t SlFsFormatResponse_t; - -typedef struct -{ - _u32 Token; -} SlFsDeleteCommand_t; - -typedef SlFsDeleteCommand_t SlFsGetInfoCommand_t; - -typedef struct -{ - _u32 FileHandle; - _u32 Offset; - _u16 Len; - _u16 Padding; -} SlFsWriteCommand_t; - -typedef _BasicResponse_t SlFsWriteResponse_t; - -typedef struct -{ - _u32 Token; - _u8 Operation; - _u8 Padding[3]; - _u32 FileNameLength; - _u32 BufferLength; -} SlFsFileSysControlCommand_t; - -typedef struct -{ - _i32 Status; - _u32 Token; - _u32 Len; -} SlFsFileSysControlResponse_t; - -typedef struct -{ - _u16 IncludeFileFilters; - _u8 Operation; - _u8 Padding; -} SlFsBundleControlCommand_t; - -typedef struct -{ - _i32 Status; - _u8 BundleState; - _u8 Padding[3]; -} SlFsBundleControlResponse_t; - -typedef struct -{ - _u16 KeyLen; - _u16 ChunkLen; - _u32 Flags; -} SlFsProgramCommand_t; - -typedef struct -{ - _i32 Status; -} SlFsProgramResponse_t; - -typedef struct -{ - _i32 Index; /* start point is -1 */ - _u8 Count; - _u8 MaxEntryLen; - _u8 Flags; - _u8 Padding; -} SlFsGetFileListCommand_t; - -typedef struct -{ - _i32 NumOfEntriesOrError; - _i32 Index; /* -1 , nothing was read */ - _u32 OutputBufferLength; -} SlFsGetFileListResponse_t; - -/* TODO: Set MAx Async Payload length depending on flavor (Tiny, Small, etc.) */ - -#define SL_ASYNC_HTTP_SRV_EVENT_LEN 1600 /* size must be aligned to 4 */ -#ifdef SL_TINY -#define SL_ASYNC_MAX_PAYLOAD_LEN 120 /* size must be aligned to 4 */ -#elif defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) -#define SL_ASYNC_MAX_PAYLOAD_LEN SL_ASYNC_HTTP_SRV_EVENT_LEN -#else -#define SL_ASYNC_MAX_PAYLOAD_LEN 220 /* size must be aligned to 4 */ - -#endif - - - - -#define SL_ASYNC_MAX_MSG_LEN (_SL_RESP_HDR_SIZE + SL_ASYNC_MAX_PAYLOAD_LEN) - - - - -#define RECV_ARGS_SIZE (sizeof(SlSocketResponse_t)) -#define RECVFROM_IPV4_ARGS_SIZE (sizeof(SlSocketAddrAsyncIPv4Response_t)) -#define RECVFROM_IPV6_ARGS_SIZE (sizeof(SlSocketAddrAsyncIPv6Response_t)) - -#define SL_IPV4_ADDRESS_SIZE (sizeof(_u32)) -#define SL_IPV6_ADDRESS_SIZE (4 * sizeof(_u32)) - - -/***************************************************************************************** -* NetUtil structures -******************************************************************************************/ -/* Utils Set Get Header */ -typedef struct -{ - _u32 ObjId; - _i16 Status; - _u16 Option; - _u16 ValueLen; - _u8 Padding[2]; -} SlNetUtilSetGet_t; - - -/* NetUtil Command Header */ -typedef struct -{ - _u16 Cmd; - _u16 AttribLen; - _u16 InputLen; - _u16 OutputLen; -} SlNetUtilCmd_t; - -/* NetUtil Command Response Header */ -typedef struct -{ - _u32 ObjId; - _i16 Status; - _u16 Cmd; - _u16 OutputLen; - _u8 Padding[2]; -} SlNetUtilCmdRsp_t; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SL_PROTOCOL_TYPES_H_ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/sl_socket.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/sl_socket.c deleted file mode 100755 index f5d157566a6..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/sl_socket.c +++ /dev/null @@ -1,2011 +0,0 @@ -/* - * sl_socket.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -static void _SlSocketBuildAddress(const SlSockAddr_t *addr, SlSocketAddrCommand_u *pCmd); -_SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf); -_SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf); - -#ifndef SL_TINY -void _SlSocketParseAddress(SlSocketAddrResponse_u *pRsp, SlSockAddr_t *addr, SlSocklen_t *addrlen); -_SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf); -_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf); -_SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf); - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) -static _i16 _SlDrvClearCtrlSocket(void); -static _i8 _SlDrvGetNextTimeoutValue(void); -#endif -#endif - -/*******************************************************************************/ -/* Functions */ -/*******************************************************************************/ - - -/* ******************************************************************************/ -/* _SlSocketBuildAddress */ -/* ******************************************************************************/ -static void _SlSocketBuildAddress(const SlSockAddr_t *addr, SlSocketAddrCommand_u *pCmd) -{ - - /* Note: parsing of family and port in the generic way for all IPV4, IPV6 and EUI48 - is possible as long as these parameters are in the same offset and size for these - three families. */ - pCmd->IpV4.FamilyAndFlags = (_u8)((addr->sa_family << 4) & 0xF0); - pCmd->IpV4.Port = ((SlSockAddrIn_t *)addr)->sin_port; - - if(SL_AF_INET == addr->sa_family) - { - pCmd->IpV4.Address = ((SlSockAddrIn_t *)addr)->sin_addr.s_addr; - } -#ifdef SL_SUPPORT_IPV6 - else - { - sl_Memcpy(pCmd->IpV6.Address, ((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, 16 ); - } -#endif -} - -/*******************************************************************************/ -/* _SlSocketParseAddress */ -/*******************************************************************************/ - -#ifndef SL_TINY -void _SlSocketParseAddress(SlSocketAddrResponse_u *pRsp, SlSockAddr_t *addr, SlSocklen_t *addrlen) -{ - /* Note: parsing of family and port in the generic way for all IPV4, IPV6 and EUI48 */ - /* is possible as long as these parameters are in the same offset and size for these */ - /* three families. */ - addr->sa_family = pRsp->IpV4.Family; - ((SlSockAddrIn_t *)addr)->sin_port = pRsp->IpV4.Port; - - *addrlen = (SL_AF_INET == addr->sa_family) ? sizeof(SlSockAddrIn_t) : sizeof(SlSockAddrIn6_t); - - if(SL_AF_INET == addr->sa_family) - { - ((SlSockAddrIn_t *)addr)->sin_addr.s_addr = pRsp->IpV4.Address; - } -#ifdef SL_SUPPORT_IPV6 - else - { - sl_Memcpy(((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, pRsp->IpV6.Address, 16); - } -#endif -} -#endif - -/*******************************************************************************/ -/* sl_Socket */ -/*******************************************************************************/ -typedef union -{ - _u32 Dummy; - SlSocketCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlSockSocketMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Socket) - -static const _SlCmdCtrl_t _SlSockSocketCmdCtrl = -{ - SL_OPCODE_SOCKET_SOCKET, - (_SlArgSize_t)sizeof(SlSocketCommand_t), - (_SlArgSize_t)sizeof(SlSocketResponse_t) -}; - -_i16 sl_Socket(_i16 Domain, _i16 Type, _i16 Protocol) -{ - _SlSockSocketMsg_u Msg; - - Msg.Cmd.Domain = (_u8)Domain; - Msg.Cmd.Type = (_u8)Type; - Msg.Cmd.Protocol = (_u8)Protocol; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSockSocketCmdCtrl, &Msg, NULL)); - - if( Msg.Rsp.StatusOrLen < 0 ) - { - return ( Msg.Rsp.StatusOrLen); - } - else - { - return (_i16)((_u8)Msg.Rsp.Sd); - } -} -#endif - -/*******************************************************************************/ -/* sl_Close */ -/*******************************************************************************/ -typedef union -{ - SlCloseCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlSockCloseMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Close) - -static const _SlCmdCtrl_t _SlSockCloseCmdCtrl = -{ - SL_OPCODE_SOCKET_CLOSE, - (_SlArgSize_t)sizeof(SlCloseCommand_t), - (_SlArgSize_t)sizeof(SlSocketResponse_t) -}; - -_i16 sl_Close(_i16 sd) -{ - _SlSockCloseMsg_u Msg; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - SlSocketResponse_t AsyncRsp; - _SlReturnVal_t RetVal; - _u8 bSocketInAction = FALSE; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - Msg.Cmd.Sd = (_u8)sd; - _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketResponse_t)); - - /* check if the socket has already action in progress */ - bSocketInAction = !!(g_pCB->ActiveActionsBitmap & (1<sa_family) - { - case SL_AF_INET: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); - break; -#ifndef SL_TINY -#ifdef SL_SUPPORT_IPV6 - case SL_AF_INET6: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND_V6; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); - break; -#endif -#endif - case SL_AF_RF: - default: - return SL_RET_CODE_INVALID_INPUT; - } - - Msg.Cmd.IpV4.LenOrPadding = 0; - Msg.Cmd.IpV4.Sd = (_u8)sd; - - _SlSocketBuildAddress(addr, &Msg.Cmd); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); - - return Msg.Rsp.StatusOrLen; -} -#endif - -/*******************************************************************************/ -/* sl_Sendto */ -/*******************************************************************************/ -typedef union -{ - SlSocketAddrCommand_u Cmd; - /* no response for 'sendto' commands*/ -}_SlSendtoMsg_u; - -#if _SL_INCLUDE_FUNC(sl_SendTo) -_i16 sl_SendTo(_i16 sd, const void *pBuf, _i16 Len, _i16 flags, const SlSockAddr_t *to, SlSocklen_t tolen) -{ - _SlSendtoMsg_u Msg; - _SlCmdCtrl_t CmdCtrl = {0, 0, 0}; - _SlCmdExt_t CmdExt; - _i16 RetVal; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - /* RAW transceiver use only sl_Send */ - if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) - { - return SL_ERROR_BSD_SOC_ERROR; - } - else - { - if (Len < 1) - { - /* ignore */ - return 0; - } - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (_u16)Len; - CmdExt.pTxPayload1 = (_u8 *)pBuf; - - switch(to->sa_family) - { - case SL_AF_INET: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_SENDTO; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); - break; -#ifndef SL_TINY -#ifdef SL_SUPPORT_IPV6 - case SL_AF_INET6: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_SENDTO_V6; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); - break; -#endif -#endif - case SL_AF_RF: - default: - return SL_RET_CODE_INVALID_INPUT; - } - - Msg.Cmd.IpV4.LenOrPadding = Len; - Msg.Cmd.IpV4.Sd = (_u8)sd; - _SlSocketBuildAddress(to, &Msg.Cmd); - Msg.Cmd.IpV4.FamilyAndFlags |= flags & 0x0F; - - RetVal = _SlDrvDataWriteOp((_SlSd_t)sd, &CmdCtrl, &Msg, &CmdExt); - if(SL_OS_RET_CODE_OK != RetVal) - { - return RetVal; - } - - return (_i16)Len; -} -#endif - -/*******************************************************************************/ -/* sl_Recvfrom */ -/*******************************************************************************/ -typedef union -{ - SlSendRecvCommand_t Cmd; - SlSocketAddrResponse_u Rsp; -}_SlRecvfromMsg_u; - -static const _SlCmdCtrl_t _SlRecvfomCmdCtrl = -{ - SL_OPCODE_SOCKET_RECVFROM, - (_SlArgSize_t)sizeof(SlSendRecvCommand_t), - (_SlArgSize_t)sizeof(SlSocketAddrResponse_u) -}; - -#if _SL_INCLUDE_FUNC(sl_RecvFrom) -_i16 sl_RecvFrom(_i16 sd, void *buf, _i16 Len, _i16 flags, SlSockAddr_t *from, SlSocklen_t *fromlen) -{ - _SlRecvfromMsg_u Msg; - _SlCmdExt_t CmdExt; - _i16 RetVal; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - /* RAW transceiver use only sl_Recv */ - if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) - { - return SL_ERROR_BSD_SOC_ERROR; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = Len; - CmdExt.pRxPayload = (_u8 *)buf; - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.StatusOrLen = (_u16)Len; - - /* no size truncation in recv path */ - CmdExt.RxPayloadLen = (_i16)Msg.Cmd.StatusOrLen; - - Msg.Cmd.FamilyAndFlags = (_u8)(flags & 0x0F); - - if(sizeof(SlSockAddrIn_t) == *fromlen) - { - Msg.Cmd.FamilyAndFlags |= (SL_AF_INET << 4); - } - else if (sizeof(SlSockAddrIn6_t) == *fromlen) - { - Msg.Cmd.FamilyAndFlags |= (SL_AF_INET6 << 4); - } - else - { - return SL_RET_CODE_INVALID_INPUT; - } - - RetVal = _SlDrvDataReadOp((_SlSd_t)sd, (_SlCmdCtrl_t *)&_SlRecvfomCmdCtrl, &Msg, &CmdExt); - if( RetVal != SL_OS_RET_CODE_OK ) - { - return RetVal; - } - - RetVal = Msg.Rsp.IpV4.StatusOrLen; - - if(RetVal >= 0) - { - VERIFY_PROTOCOL(sd == (_i16)Msg.Rsp.IpV4.Sd); -#if 0 - _SlSocketParseAddress(&Msg.Rsp, from, fromlen); -#else - from->sa_family = Msg.Rsp.IpV4.Family; - if(SL_AF_INET == from->sa_family) - { - ((SlSockAddrIn_t *)from)->sin_port = Msg.Rsp.IpV4.Port; - ((SlSockAddrIn_t *)from)->sin_addr.s_addr = Msg.Rsp.IpV4.Address; - *fromlen = (SlSocklen_t)sizeof(SlSockAddrIn_t); - } -#ifdef SL_SUPPORT_IPV6 - else if(SL_AF_INET6 == from->sa_family) - { - VERIFY_PROTOCOL(*fromlen >= sizeof(SlSockAddrIn6_t)); - - ((SlSockAddrIn6_t *)from)->sin6_port = Msg.Rsp.IpV6.Port; - sl_Memcpy(((SlSockAddrIn6_t *)from)->sin6_addr._S6_un._S6_u32, Msg.Rsp.IpV6.Address, 16); - *fromlen = sizeof(SlSockAddrIn6_t); - } -#endif -#endif - } - - return (_i16)RetVal; -} -#endif - -/*******************************************************************************/ -/* sl_Connect */ -/*******************************************************************************/ -typedef union -{ - SlSocketAddrCommand_u Cmd; - SlSocketResponse_t Rsp; -}_SlSockConnectMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Connect) -_i16 sl_Connect(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen) -{ - _SlSockConnectMsg_u Msg; - _SlReturnVal_t RetVal; - _SlCmdCtrl_t CmdCtrl = {0, (_SlArgSize_t)0, (_SlArgSize_t)sizeof(SlSocketResponse_t)}; - SlSocketResponse_t AsyncRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketResponse_t)); - - switch(addr->sa_family) - { - case SL_AF_INET : - CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); - /* Do nothing - cmd already initialized to this type */ - break; -#ifdef SL_SUPPORT_IPV6 - case SL_AF_INET6: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT_V6; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); - break; -#endif - case SL_AF_RF: - default: - return SL_RET_CODE_INVALID_INPUT; - } - - Msg.Cmd.IpV4.LenOrPadding = 0; - Msg.Cmd.IpV4.Sd = (_u8)sd; - - _SlSocketBuildAddress(addr, &Msg.Cmd); - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, CONNECT_ID, (_u8)(sd & SL_BSD_SOCKET_ID_MASK)); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); - VERIFY_PROTOCOL(Msg.Rsp.Sd == (_u8)sd); - - RetVal = Msg.Rsp.StatusOrLen; - - if(SL_RET_CODE_OK == RetVal) - { -#ifndef SL_TINY - /*In case socket is non-blocking one, the async event should be received immediately */ - if( g_pCB->SocketNonBlocking & (1<<(sd & SL_BSD_SOCKET_ID_MASK) )) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE)); - } - else -#endif - { - - /* wait for async and get Data Read parameters */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); - } - - RetVal = AsyncRsp.StatusOrLen; - - if (0 <= RetVal) - { - VERIFY_PROTOCOL(AsyncRsp.Sd == (_u8)sd); - } - } - - _SlDrvReleasePoolObj(ObjIdx); - return RetVal; -} - -#endif - - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Connect */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf) -{ - SlSocketResponse_t *pMsgArgs = (SlSocketResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = pMsgArgs->StatusOrLen; - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Close */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf) -{ - SlSocketResponse_t *pMsgArgs = (SlSocketResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = pMsgArgs->StatusOrLen; - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -/*******************************************************************************/ -/* sl_Send */ -/*******************************************************************************/ -typedef union -{ - SlSendRecvCommand_t Cmd; - /* no response for 'sendto' commands*/ -}_SlSendMsg_u; - -static const _SlCmdCtrl_t _SlSendCmdCtrl = -{ - SL_OPCODE_SOCKET_SEND, - (_SlArgSize_t)sizeof(SlSendRecvCommand_t), - (_SlArgSize_t)0 -}; - -#if _SL_INCLUDE_FUNC(sl_Send) -_i16 sl_Send(_i16 sd, const void *pBuf, _i16 Len, _i16 flags) -{ - _SlSendMsg_u Msg; - _SlCmdExt_t CmdExt; - _i16 RetVal; - _u32 tempVal; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (_u16)Len; - CmdExt.pTxPayload1 = (_u8 *)pBuf; - - /* Only for RAW transceiver type socket, relay the flags parameter in the 2 bytes (4 byte aligned) before the actual payload */ - if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) - { - tempVal = (_u32)flags; - CmdExt.pRxPayload = (_u8 *)&tempVal; - CmdExt.RxPayloadLen = -4; /* the (-) sign is used to mark the rx buff as output buff as well*/ - } - else - { - CmdExt.pRxPayload = NULL; - if (Len < 1) - { - /* ignore */ - return 0; - } - } - - Msg.Cmd.StatusOrLen = Len; - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.FamilyAndFlags |= flags & 0x0F; - - RetVal = _SlDrvDataWriteOp((_u8)sd, (_SlCmdCtrl_t *)&_SlSendCmdCtrl, &Msg, &CmdExt); - if(SL_OS_RET_CODE_OK != RetVal) - { - return RetVal; - } - - return (_i16)Len; -} -#endif - -/*******************************************************************************/ -/* sl_Listen */ -/*******************************************************************************/ -typedef union -{ - SlListenCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlListenMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Listen) - -static const _SlCmdCtrl_t _SlListenCmdCtrl = -{ - SL_OPCODE_SOCKET_LISTEN, - (_SlArgSize_t)sizeof(SlListenCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t), -}; - -_i16 sl_Listen(_i16 sd, _i16 backlog) -{ - _SlListenMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.Backlog = (_u8)backlog; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlListenCmdCtrl, &Msg, NULL)); - return (_i16)Msg.Rsp.status; -} -#endif - -/*******************************************************************************/ -/* sl_Accept */ -/*******************************************************************************/ -typedef union -{ - SlAcceptCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlSockAcceptMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Accept) - -static const _SlCmdCtrl_t _SlAcceptCmdCtrl = -{ - SL_OPCODE_SOCKET_ACCEPT, - (_SlArgSize_t)sizeof(SlAcceptCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t), -}; - -_i16 sl_Accept(_i16 sd, SlSockAddr_t *addr, SlSocklen_t *addrlen) -{ - _SlSockAcceptMsg_u Msg; - _SlReturnVal_t RetVal; - SlSocketAddrResponse_u AsyncRsp; - - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - Msg.Cmd.Sd = (_u8)sd; - - if((addr != NULL) && (addrlen != NULL)) - { - /* If addr is present, addrlen has to be provided */ - Msg.Cmd.Family = (_u8)((sizeof(SlSockAddrIn_t) == *addrlen) ? SL_AF_INET : SL_AF_INET6); - } - else - { - /* In any other case, addrlen is ignored */ - Msg.Cmd.Family = (_u8)0; - } - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, ACCEPT_ID, (_u8)sd & SL_BSD_SOCKET_ID_MASK); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlAcceptCmdCtrl, &Msg, NULL)); - VERIFY_PROTOCOL(Msg.Rsp.Sd == (_u8)sd); - - RetVal = Msg.Rsp.StatusOrLen; - - if(SL_OS_RET_CODE_OK == RetVal) - { -#ifndef SL_TINY - /* in case socket is non-blocking one, the async event should be received immediately */ - if( g_pCB->SocketNonBlocking & (1<<(sd & SL_BSD_SOCKET_ID_MASK) )) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE)); - } - else -#endif - { - /* wait for async and get Data Read parameters */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - } - - RetVal = AsyncRsp.IpV4.StatusOrLen; - - if (0 <= RetVal) - { - VERIFY_PROTOCOL(AsyncRsp.IpV4.Sd == (_u8)sd); - } - - -#if 0 /* Kept for backup */ - _SlSocketParseAddress(&AsyncRsp, addr, addrlen); -#else - if((addr != NULL) && (addrlen != NULL)) - { - addr->sa_family = AsyncRsp.IpV4.Family; - - if(SL_AF_INET == addr->sa_family) - { - if( *addrlen == (SlSocklen_t)sizeof( SlSockAddrIn_t ) ) - { - ((SlSockAddrIn_t *)addr)->sin_port = AsyncRsp.IpV4.Port; - ((SlSockAddrIn_t *)addr)->sin_addr.s_addr = AsyncRsp.IpV4.Address; - } - else - { - *addrlen = 0; - } - } -#ifdef SL_SUPPORT_IPV6 - else if(SL_AF_INET6 == addr->sa_family) - { - if( *addrlen == sizeof( SlSockAddrIn6_t ) ) - { - ((SlSockAddrIn6_t *)addr)->sin6_port = AsyncRsp.IpV6.Port ; - sl_Memcpy(((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, AsyncRsp.IpV6.Address, 16); - } - else - { - *addrlen = 0; - } - } -#endif - } -#endif - } - - _SlDrvReleasePoolObj(ObjIdx); - return (_i16)RetVal; -} -#endif - - -/*******************************************************************************/ -/* sl_Htonl */ -/*******************************************************************************/ -_u32 sl_Htonl( _u32 val ) -{ - _u32 i = 1; - _i8 *p = (_i8 *)&i; - if (p[0] == 1) /* little endian */ - { - p[0] = ((_i8* )&val)[3]; - p[1] = ((_i8* )&val)[2]; - p[2] = ((_i8* )&val)[1]; - p[3] = ((_i8* )&val)[0]; - return i; - } - else /* big endian */ - { - return val; - } -} - -/*******************************************************************************/ -/* sl_Htonl */ -/*******************************************************************************/ -_u16 sl_Htons( _u16 val ) -{ - _i16 i = 1; - _i8 *p = (_i8 *)&i; - if (p[0] == 1) /* little endian */ - { - p[0] = ((_i8* )&val)[1]; - p[1] = ((_i8* )&val)[0]; - return (_u16)i; - } - else /* big endian */ - { - return val; - } -} - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Accept */ -/*******************************************************************************/ -#ifndef SL_TINY -_SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf) -{ - SlSocketAddrResponse_u *pMsgArgs = (SlSocketAddrResponse_u *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_PROTOCOL(( pMsgArgs->IpV4.Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs,sizeof(SlSocketAddrResponse_u)); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} -#endif - -/*******************************************************************************/ -/* sl_Recv */ -/*******************************************************************************/ -typedef union -{ - SlSendRecvCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlRecvMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Recv) - -static const _SlCmdCtrl_t _SlRecvCmdCtrl = -{ - SL_OPCODE_SOCKET_RECV, - (_SlArgSize_t)sizeof(SlSendRecvCommand_t), - (_SlArgSize_t)sizeof(SlSocketResponse_t) -}; - -_i16 sl_Recv(_i16 sd, void *pBuf, _i16 Len, _i16 flags) -{ - _SlRecvMsg_u Msg; - _SlCmdExt_t CmdExt; - _SlReturnVal_t status; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = Len; - CmdExt.pRxPayload = (_u8 *)pBuf; - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.StatusOrLen = (_u16)Len; - - /* no size truncation in recv path */ - CmdExt.RxPayloadLen = (_i16)Msg.Cmd.StatusOrLen; - - Msg.Cmd.FamilyAndFlags = (_u8)(flags & 0x0F); - - status = _SlDrvDataReadOp((_SlSd_t)sd, (_SlCmdCtrl_t *)&_SlRecvCmdCtrl, &Msg, &CmdExt); - if( status != SL_OS_RET_CODE_OK ) - { - return status; - } - - /* if the Device side sends less than expected it is not the Driver's role */ - /* the returned value could be smaller than the requested size */ - return (_i16)Msg.Rsp.StatusOrLen; -} -#endif - -/*******************************************************************************/ -/* sl_SetSockOpt */ -/*******************************************************************************/ -typedef union -{ - SlSetSockOptCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlSetSockOptMsg_u; - -static const _SlCmdCtrl_t _SlSetSockOptCmdCtrl = -{ - SL_OPCODE_SOCKET_SETSOCKOPT, - (_SlArgSize_t)sizeof(SlSetSockOptCommand_t), - (_SlArgSize_t)sizeof(SlSocketResponse_t) -}; - -#if _SL_INCLUDE_FUNC(sl_SetSockOpt) -_i16 sl_SetSockOpt(_i16 sd, _i16 level, _i16 optname, const void *optval, SlSocklen_t optlen) -{ - _SlSetSockOptMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = optlen; - CmdExt.pTxPayload1 = (_u8 *)optval; - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.Level = (_u8)level; - Msg.Cmd.OptionLen = (_u8)optlen; - Msg.Cmd.OptionName = (_u8)optname; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSetSockOptCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.StatusOrLen; -} -#endif - -/*******************************************************************************/ -/* sl_GetSockOpt */ -/*******************************************************************************/ -typedef union -{ - SlGetSockOptCommand_t Cmd; - SlGetSockOptResponse_t Rsp; -}_SlGetSockOptMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_GetSockOpt) - -static const _SlCmdCtrl_t _SlGetSockOptCmdCtrl = -{ - SL_OPCODE_SOCKET_GETSOCKOPT, - (_SlArgSize_t)sizeof(SlGetSockOptCommand_t), - (_SlArgSize_t)sizeof(SlGetSockOptResponse_t) -}; - -_i16 sl_GetSockOpt(_i16 sd, _i16 level, _i16 optname, void *optval, SlSocklen_t *optlen) -{ - _SlGetSockOptMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - if (*optlen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(*optlen); - CmdExt.pRxPayload = optval; - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.Level = (_u8)level; - Msg.Cmd.OptionLen = (_u8)(*optlen); - Msg.Cmd.OptionName = (_u8)optname; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetSockOptCmdCtrl, &Msg, &CmdExt)); - - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *optlen = Msg.Rsp.OptionLen; - return SL_ESMALLBUF; - } - else - { - *optlen = (_u8)CmdExt.ActualRxPayloadLen; - } - return (_i16)Msg.Rsp.Status; -} -#endif - -/********************************************************************************/ -/* sl_Select */ -/* ******************************************************************************/ -#ifndef SL_TINY -#if _SL_INCLUDE_FUNC(sl_Select) - -typedef union -{ - SlSelectCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlSelectMsg_u; - -static const _SlCmdCtrl_t _SlSelectCmdCtrl = -{ - SL_OPCODE_SOCKET_SELECT, - (_SlArgSize_t)sizeof(SlSelectCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -/********************************************************************************/ -/* SL_SOCKET_FD_SET */ -/* ******************************************************************************/ -void SL_SOCKET_FD_SET(_i16 fd, SlFdSet_t *fdset) -{ - fdset->fd_array[0] |= (1<< (fd & SL_BSD_SOCKET_ID_MASK)); -} - -/*******************************************************************************/ -/* SL_SOCKET_FD_CLR */ -/*******************************************************************************/ -void SL_SOCKET_FD_CLR(_i16 fd, SlFdSet_t *fdset) -{ - fdset->fd_array[0] &= ~(1<< (fd & SL_BSD_SOCKET_ID_MASK)); -} - -/*******************************************************************************/ -/* SL_SOCKET_FD_ISSET */ -/*******************************************************************************/ -_i16 SL_SOCKET_FD_ISSET(_i16 fd, SlFdSet_t *fdset) -{ - if( fdset->fd_array[0] & (1<< (fd & SL_BSD_SOCKET_ID_MASK)) ) - { - return 1; - } - return 0; -} - -/*******************************************************************************/ -/* SL_SOCKET_FD_ZERO */ -/*******************************************************************************/ -void SL_SOCKET_FD_ZERO(SlFdSet_t *fdset) -{ - fdset->fd_array[0] = 0; -} - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - -/*******************************************************************************/ -/* Multiple Select */ -/*******************************************************************************/ - -/* Multiple Select Defines */ -#define LOCAL_CTRL_PORT (3632) -#define SL_LOOPBACK_ADDR (0x0100007F) -#define DUMMY_BUF_SIZE (4) -#define CTRL_SOCK_FD (((_u16)(1)) << g_pCB->MultiSelectCB.CtrlSockFD) -#define SELECT_TIMEOUT ((_u16)0) -#define SELECT_NO_TIMEOUT (0xFFFFFFFF) - -/* Multiple Select Structures */ -_SlSelectMsg_u Msg; - -static const SlSockAddrIn_t _SlCtrlSockAddr = -{ - SL_AF_INET, - LOCAL_CTRL_PORT, - {SL_INADDR_ANY}, - {0,0,0,0,0,0,0,0} -}; - -static const SlSockAddrIn_t _SlCtrlSockRelease = -{ - SL_AF_INET, - LOCAL_CTRL_PORT, - {SL_LOOPBACK_ADDR}, - {0,0,0,0,0,0,0,0} -}; - -/*******************************************************************************/ -/* CountSetBits */ -/*******************************************************************************/ -static inline _u8 CountSetBits(_u16 fdList) -{ - _u8 Count = 0; - - while(fdList) - { - Count += (fdList & ((_u16)1)); - fdList = fdList >> 1; - } - - return Count; -} - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Select */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf) -{ - _SlReturnVal_t RetVal; - SlSelectAsyncResponse_t *pMsgArgs = (SlSelectAsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - _u8 RegIdx = 0; - _u32 time_now; - _u8 TimeoutEvent = 0; - _u16 SelectEvent = 0; - _u8 PendingSelect = FALSE; - - _SlDrvMemZero(&Msg, sizeof(_SlSelectMsg_u)); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Check if this context was triggered by a 'select joiner' only, - * without timeout occurring, in order to launch the next select as quick as possible */ - if((CTRL_SOCK_FD == pMsgArgs->ReadFds) && (pMsgArgs->Status != SELECT_TIMEOUT)) - { - RetVal = _SlDrvClearCtrlSocket(); - Msg.Cmd.ReadFds = g_pCB->MultiSelectCB.readsds; - Msg.Cmd.WriteFds = g_pCB->MultiSelectCB.writesds; - Msg.Cmd.ReadFds |= CTRL_SOCK_FD; - Msg.Cmd.tv_sec = 0xFFFF; - Msg.Cmd.tv_usec = 0xFFFF; - - RegIdx = _SlDrvGetNextTimeoutValue(); - - SL_TRACE3(DBG_MSG, MSG_312, "\n\rAdded caller: call Select with: Write:%x Sec:%d uSec:%d\n\r", - Msg.Cmd.WriteFds, Msg.Cmd.tv_sec, Msg.Cmd.tv_usec); - - RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL); - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return RetVal; - } - - /* If we're triggered by the NWP, take time-stamps to monitor the time-outs */ - time_now = ((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10); - - /* If it's a proper select response, or if timeout occurred, release the relevant waiters */ - for(RegIdx = 0 ; RegIdx < MAX_CONCURRENT_ACTIONS ; RegIdx++) - { - if(g_pCB->MultiSelectCB.SelectEntry[RegIdx] != NULL) - { - /* In case a certain entry has 100 mSec or less until it's timeout, the overhead - * caused by calling select again with it's fd lists is redundant, just return a time-out. */ - - TimeoutEvent = ((time_now + 100) >= g_pCB->MultiSelectCB.SelectEntry[RegIdx]->TimeStamp); - - if(pMsgArgs->Status != SELECT_TIMEOUT) - { - SelectEvent = ((g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist & pMsgArgs->ReadFds) || - (g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist & pMsgArgs->WriteFds)); - } - - if(SelectEvent || TimeoutEvent) - { - - - /* Clear the global select socket descriptor bitmaps */ - g_pCB->MultiSelectCB.readsds &= ~(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); - g_pCB->MultiSelectCB.writesds &= ~(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); - - if(SelectEvent) - { - /* set the corresponding fd lists. */ - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFds = (pMsgArgs->ReadFds & g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFds = (pMsgArgs->WriteFds & g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFdsCount = CountSetBits(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFdsCount = CountSetBits(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.Status = (g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFdsCount + - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFdsCount); - } - else - { - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.Status = SELECT_TIMEOUT; - } - - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFds &= ~(CTRL_SOCK_FD); - - /* Signal the waiting caller. */ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->MultiSelectCB.SelectEntry[RegIdx]->ObjIdx].SyncObj); - - /* Clean it's table entry */ - g_pCB->MultiSelectCB.SelectEntry[RegIdx] = NULL; - } - else - { - PendingSelect = TRUE; - } - } - } - - /* In case where A caller was added, but also some sockfd were set on the NWP, - * We clear the control socket. */ - if((pMsgArgs->ReadFds & CTRL_SOCK_FD) && (pMsgArgs->Status != SELECT_TIMEOUT)) - { - RetVal = _SlDrvClearCtrlSocket(); - } - - /* If more readers/Writers are present, send select again */ - if((0 != g_pCB->MultiSelectCB.readsds) || (0 != g_pCB->MultiSelectCB.writesds) || (TRUE == PendingSelect)) - { - Msg.Cmd.ReadFds = g_pCB->MultiSelectCB.readsds; - Msg.Cmd.ReadFds |= CTRL_SOCK_FD; - Msg.Cmd.WriteFds = g_pCB->MultiSelectCB.writesds; - - /* Set timeout to blocking, in case there is no caller with timeout value. */ - Msg.Cmd.tv_sec = 0xFFFF; - Msg.Cmd.tv_usec = 0xFFFF; - - /* Get the next awaiting timeout caller */ - RegIdx = _SlDrvGetNextTimeoutValue(); - - SL_TRACE3(DBG_MSG, MSG_312, "\n\rRelease Partial: call Select with: Read:%x Sec:%d uSec:%d\n\r", - Msg.Cmd.ReadFds, Msg.Cmd.tv_sec, Msg.Cmd.tv_usec); - - RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL); - } - else - { - while(g_pCB->MultiSelectCB.ActiveWaiters) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->MultiSelectCB.SelectSyncObj); - g_pCB->MultiSelectCB.ActiveWaiters--; - } - - g_pCB->MultiSelectCB.ActiveSelect = FALSE; - - SL_TRACE1(DBG_MSG, MSG_312, "\n\rSelect isn't Active: %d\n\r", g_pCB->MultiSelectCB.ActiveSelect); - } - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -/*******************************************************************************/ -/* SlDrvGetNextTimeoutValue */ -/*******************************************************************************/ -static _i8 _SlDrvGetNextTimeoutValue(void) -{ - _u32 time_now; - _i8 Found = -1; - _u8 idx = 0; - - /* Take a timestamp */ - time_now = ((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10); - - /* Go through all waiting time-outs, and select the closest */ - for(idx = 0 ; idx < MAX_CONCURRENT_ACTIONS ; idx++) - { - if(NULL != g_pCB->MultiSelectCB.SelectEntry[idx]) - { - /* Check if the time-stamp is bigger or equal to current time, and if it's the minimal time-stamp (closest event) */ - if(g_pCB->MultiSelectCB.SelectEntry[idx]->TimeStamp >= time_now) - { - if(Found == -1) - { - Found = idx; - } - else - { - if(g_pCB->MultiSelectCB.SelectEntry[idx]->TimeStamp <= g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp) - { - Found = idx; - } - } - } - } - } - - /* If a non-wait-forever index was found, calculate delta until closest event */ - if(g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp != SELECT_NO_TIMEOUT) - { - _i32 delta = (g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp - time_now); - - if(delta >= 0) - { - Msg.Cmd.tv_sec = (delta / 1000); - Msg.Cmd.tv_usec = (((delta % 1000) * 1000) >> 10); - } - else - { - /* if delta time calculated is negative, call a non-blocking select */ - Msg.Cmd.tv_sec = 0; - Msg.Cmd.tv_usec = 0; - } - } - - return Found; -} - -/*******************************************************************************/ -/* _SlDrvClearCtrlSocket */ -/*******************************************************************************/ -static _i16 _SlDrvClearCtrlSocket(void) -{ - _SlRecvfromMsg_u Msg; - _SlCmdExt_t CmdExt; - _u8 dummyBuf[DUMMY_BUF_SIZE]; - _SlReturnVal_t RetVal; - - /* Prepare a recvFrom Cmd */ - _SlDrvResetCmdExt(&CmdExt); - _SlDrvMemZero(&Msg, sizeof(_SlRecvfromMsg_u)); - - CmdExt.RxPayloadLen = DUMMY_BUF_SIZE; - CmdExt.pRxPayload = (_u8 *)&dummyBuf; - - Msg.Cmd.Sd = (_u8)g_pCB->MultiSelectCB.CtrlSockFD; - Msg.Cmd.StatusOrLen = (_u16)DUMMY_BUF_SIZE; - Msg.Cmd.FamilyAndFlags = (SL_AF_INET << 4); - - RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlRecvfomCmdCtrl, &Msg, &CmdExt); - - return RetVal; -} - -/*******************************************************************************/ -/* _SlDrvOpenCtrlSocket */ -/*******************************************************************************/ -static _i16 _SlDrvOpenCtrlSocket(void) -{ - _i16 retVal; - - /* In case a control socket is already open, return. */ - if(g_pCB->MultiSelectCB.CtrlSockFD != 0xFF) - { - return 0; - } - - /* Open a local control socket */ - retVal = sl_Socket(SL_AF_INET, SL_SOCK_DGRAM, 0); - - if(retVal == SL_ERROR_BSD_ENSOCK) - { - return 0; - } - else if(retVal < 0) - { - return retVal; - } - else - { - g_pCB->MultiSelectCB.CtrlSockFD = retVal; - } - - /* Bind it to local control port */ - retVal = sl_Bind(g_pCB->MultiSelectCB.CtrlSockFD, (const SlSockAddr_t *)&_SlCtrlSockAddr, sizeof(SlSockAddrIn_t)); - - return retVal; -} - -/*******************************************************************************/ -/* _SlDrvCloseCtrlSocket */ -/*******************************************************************************/ -static _i16 _SlDrvCloseCtrlSocket(void) -{ - _i16 retVal = 0; - _i16 sockfd = 0xFF; - - /* Close the internal Control socket */ - sockfd = g_pCB->MultiSelectCB.CtrlSockFD; - - if(sockfd != 0xFF) - { - /* Close the local control socket */ - retVal = sl_Close(sockfd); - } - - g_pCB->MultiSelectCB.CtrlSockFD = 0xFF; - - if(retVal < 0) - { - return SL_ERROR_BSD_SOC_ERROR; - } - - return retVal; -} - -/*******************************************************************************/ -/* to_Msec */ -/*******************************************************************************/ -static inline _u32 to_mSec(struct SlTimeval_t* timeout) -{ - return (((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10) + (timeout->tv_sec * 1000) + (timeout->tv_usec / 1000)); -} - -/*******************************************************************************/ -/* _SlDrvUnRegisterForSelectAsync */ -/*******************************************************************************/ -static _i16 _SlDrvUnRegisterForSelectAsync(_SlSelectEntry_t* pEntry, _u8 SelectInProgress) -{ - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Clear the global select fd lists */ - g_pCB->MultiSelectCB.readsds &= ~(pEntry->readlist); - g_pCB->MultiSelectCB.writesds &= ~(pEntry->writelist); - - /* Empty the caller's table entry. */ - g_pCB->MultiSelectCB.SelectEntry[pEntry->ObjIdx] = NULL; - - if(g_pCB->MultiSelectCB.ActiveSelect == FALSE) - { - _SlDrvCloseCtrlSocket(); - } - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Release it's pool object */ - _SlDrvReleasePoolObj(pEntry->ObjIdx); - - return SL_ERROR_BSD_SOC_ERROR; -} - -/*******************************************************************************/ -/* _SlDrvRegisterForSelectAsync */ -/*******************************************************************************/ -static _i16 _SlDrvRegisterForSelectAsync(_SlSelectEntry_t* pEntry, _SlSelectMsg_u* pMsg, struct SlTimeval_t *timeout, _u8 SelectInProgress) -{ - _SlReturnVal_t _RetVal = 0; - _u8 dummyBuf[4] = {0}; - - /* Register this caller's parameters */ - pEntry->readlist = pMsg->Cmd.ReadFds; - pEntry->writelist = pMsg->Cmd.WriteFds; - - if((pMsg->Cmd.tv_sec != 0xFFFF) && (timeout != NULL)) - { - pEntry->TimeStamp = to_mSec(timeout); - } - else - { - pEntry->TimeStamp = SELECT_NO_TIMEOUT; - } - - g_pCB->MultiSelectCB.readsds |= pMsg->Cmd.ReadFds; - g_pCB->MultiSelectCB.writesds |= pMsg->Cmd.WriteFds; - g_pCB->MultiSelectCB.SelectEntry[pEntry->ObjIdx] = pEntry; - - SL_TRACE3(DBG_MSG, MSG_312, "\n\rRegistered: Objidx:%d, sec:%d, usec%d\n\r", - pEntry->ObjIdx, pMsg->Cmd.tv_sec, pMsg->Cmd.tv_usec); - - if((!SelectInProgress) || (g_pCB->MultiSelectCB.ActiveSelect == FALSE)) - { - /* Add ctrl socket to the read list for this 'select' call */ - pMsg->Cmd.ReadFds |= CTRL_SOCK_FD; - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - _RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, pMsg, NULL); - - if((_RetVal == SL_RET_CODE_OK) && (g_pCB->MultiSelectCB.CtrlSockFD != 0xFF)) - { - /* Signal any waiting "Select" callers */ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->MultiSelectCB.SelectSyncObj); - } - } - else - { - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Wait here to be signaled by a successfully completed select caller */ - if (_SlDrvIsSpawnOwnGlobalLock()) - { - while (TRUE) - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->MultiSelectCB.SelectSyncObj, SL_OS_NO_WAIT)) - { - break; - } - } - } - else - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->MultiSelectCB.SelectSyncObj); - } - - _RetVal = sl_SendTo(g_pCB->MultiSelectCB.CtrlSockFD, - &dummyBuf[0], - sizeof(dummyBuf), - 0, - (const SlSockAddr_t *)&_SlCtrlSockRelease, - sizeof(SlSockAddrIn_t)); - } - - return _RetVal; -} - -/********************************************************************************/ -/* sl_Select */ -/* ******************************************************************************/ -_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout) -{ - _i16 ret; - _u8 isCaller = FALSE; - _SlSelectMsg_u Msg; - _SlSelectEntry_t SelectParams; - _u8 SelectInProgress = FALSE; - - /* verify that this API is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - _SlDrvMemZero(&Msg, sizeof(_SlSelectMsg_u)); - _SlDrvMemZero(&SelectParams, sizeof(_SlSelectEntry_t)); - - Msg.Cmd.Nfds = (_u8)nfds; - - if(readsds) - { - Msg.Cmd.ReadFds = (_u16)readsds->fd_array[0]; - } - - if(writesds) - { - Msg.Cmd.WriteFds = (_u16)writesds->fd_array[0]; - } - - if(NULL == timeout) - { - Msg.Cmd.tv_sec = 0xffff; - Msg.Cmd.tv_usec = 0xffff; - } - else - { - if(0xffff <= timeout->tv_sec) - { - Msg.Cmd.tv_sec = 0xffff; - } - else - { - Msg.Cmd.tv_sec = (_u16)timeout->tv_sec; - } - - /* this divides by 1024 to fit the result in a int16_t. - * Upon receiving, the NWP multiply this value by 1024. */ - timeout->tv_usec = (timeout->tv_usec >> 10); - - if(0xffff <= timeout->tv_usec) - { - Msg.Cmd.tv_usec = 0xffff; - } - else - { - Msg.Cmd.tv_usec = (_u16)timeout->tv_usec; - } - } - - while(FALSE == isCaller) - { - SelectParams.ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&SelectParams.Response, SELECT_ID, SL_MAX_SOCKETS); - - if(MAX_CONCURRENT_ACTIONS == SelectParams.ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Check if no other 'Select' calls are in progress */ - if(FALSE == g_pCB->MultiSelectCB.ActiveSelect) - { - g_pCB->MultiSelectCB.ActiveSelect = TRUE; - } - else - { - SelectInProgress = TRUE; - } - - if(!SelectInProgress) - { - ret = _SlDrvOpenCtrlSocket(); - - if(ret < 0) - { - _SlDrvCloseCtrlSocket(); - g_pCB->MultiSelectCB.ActiveSelect = FALSE; - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - _SlDrvReleasePoolObj(SelectParams.ObjIdx); - return ret; - } - else - { - /* All conditions are met for calling "Select" */ - isCaller = TRUE; - } - } - else if(g_pCB->MultiSelectCB.CtrlSockFD == 0xFF) - { - _SlDrvReleasePoolObj(SelectParams.ObjIdx); - - /* This is not a first select caller and all sockets are open, - * caller is expected to wait until select is inactive, - * before trying to register again. */ - g_pCB->MultiSelectCB.ActiveWaiters++; - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Wait here to be signaled by a successfully completed select caller */ - if (_SlDrvIsSpawnOwnGlobalLock()) - { - while (TRUE) - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->MultiSelectCB.SelectSyncObj, SL_OS_NO_WAIT)) - { - break; - } - } - } - else - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->MultiSelectCB.SelectSyncObj); - } - - - if((_i16)g_pCB->MultiSelectCB.SelectCmdResp.status != SL_RET_CODE_OK) - { - return (_i16)(g_pCB->MultiSelectCB.SelectCmdResp.status); - } - - SelectInProgress = FALSE; - } - else - { - /* All conditions are met for calling "Select" */ - isCaller = TRUE; - } - } - - /* Register this caller details for an select Async event. - * SelectLockObj is released inside this function, - * right before sending 'Select' command. */ - ret = _SlDrvRegisterForSelectAsync(&SelectParams, &Msg, timeout, SelectInProgress); - - if(ret < 0) - { - return (_SlDrvUnRegisterForSelectAsync(&SelectParams, SelectInProgress)); - } - - /* Wait here for a Async event, or command response in case select fails.*/ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(SelectParams.ObjIdx, 0, 0)); - _SlDrvReleasePoolObj(SelectParams.ObjIdx); - - ret = (_i16)g_pCB->MultiSelectCB.SelectCmdResp.status; - - if(ret == SL_RET_CODE_OK) - { - ret = (_i16)SelectParams.Response.Status; - - if(ret > SELECT_TIMEOUT) - { - if(readsds) - { - readsds->fd_array[0] = SelectParams.Response.ReadFds; - } - - if(writesds) - { - writesds->fd_array[0] = SelectParams.Response.WriteFds; - } - } - } - - return ret; -} - -#else - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Select */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf) -{ - SlSelectAsyncResponse_t *pMsgArgs = (SlSelectAsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); -#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - SlSockTriggerEvent_t SockTriggerEvent; -#endif - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(SlSelectAsyncResponse_t)); - -#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) - { - if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_WAITING_FOR_RESP) - { - - SockTriggerEvent.Event = SL_SOCKET_TRIGGER_EVENT_SELECT; - SockTriggerEvent.EventData = 0; - - g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_RESP_RECEIVED; - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - /* call the user handler */ - _SlDrvHandleSocketTriggerEvents(&SockTriggerEvent); - - return SL_OS_RET_CODE_OK; - } - else - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - } - else -#endif - { - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout) -{ - _SlSelectMsg_u Msg; - SlSelectAsyncResponse_t AsyncRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; -#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - _u8 IsNonBlocking = FALSE; -#endif - - /* verify that this API is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - -#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) - { - if( NULL != timeout ) - { - /* Set that we are in Non-Blocking mode */ - if ( (0 == timeout->tv_sec) && (0 == timeout->tv_usec) ) - { - IsNonBlocking = TRUE; - } - else - { - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - /* If there is a trigger select running in the progress abort the new blocking request */ - if (g_pCB->SocketTriggerSelect.Info.State > SOCK_TRIGGER_READY) - { - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR; - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - - if (IsNonBlocking == TRUE) - { - /* return EAGAIN if we alreay have select trigger in progress */ - if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_WAITING_FOR_RESP) - { - return SL_ERROR_BSD_EAGAIN; - } - /* return the stored response if already received */ - else if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_RESP_RECEIVED) - { - if( ((_i16)g_pCB->SocketTriggerSelect.Resp.Status) >= 0 ) - { - if( readsds ) - { - readsds->fd_array[0] = g_pCB->SocketTriggerSelect.Resp.ReadFds; - } - if( writesds ) - { - writesds->fd_array[0] = g_pCB->SocketTriggerSelect.Resp.WriteFds; - } - } - - /* Now relaese the pool object */ - _SlDrvReleasePoolObj(g_pCB->SocketTriggerSelect.Info.ObjPoolIdx); - - g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = MAX_CONCURRENT_ACTIONS; - - /* Reset the socket select trigger object */ - g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_READY; - - return (_i16)g_pCB->SocketTriggerSelect.Resp.Status; - } - } - } - } -#endif - - Msg.Cmd.Nfds = (_u8)nfds; - Msg.Cmd.ReadFdsCount = 0; - Msg.Cmd.WriteFdsCount = 0; - - Msg.Cmd.ReadFds = 0; - Msg.Cmd.WriteFds = 0; - - - if( readsds ) - { - Msg.Cmd.ReadFds = (_u16)readsds->fd_array[0]; - } - if( writesds ) - { - Msg.Cmd.WriteFds = (_u16)writesds->fd_array[0]; - } - if( NULL == timeout ) - { - Msg.Cmd.tv_sec = 0xffff; - Msg.Cmd.tv_usec = 0xffff; - } - else - { - if( 0xffff <= timeout->tv_sec ) - { - Msg.Cmd.tv_sec = 0xffff; - } - else - { - Msg.Cmd.tv_sec = (_u16)timeout->tv_sec; - } - - /* convert to milliseconds */ - timeout->tv_usec = timeout->tv_usec >> 10; - - if( 0xffff <= timeout->tv_usec ) - { - Msg.Cmd.tv_usec = 0xffff; - } - else - { - Msg.Cmd.tv_usec = (_u16)timeout->tv_usec; - } - - } - - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, SELECT_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL)); - - if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - - Msg.Rsp.status = (_i16)AsyncRsp.Status; - - /* this code handles the socket trigger mode case */ -#if((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) - { - /* if no data returned and we are in trigger mode, - send another select cmd but now with timeout infinite, - and return immediately with EAGAIN to the user */ - if ((IsNonBlocking == TRUE) && (AsyncRsp.Status == 0)) - { - /* set the select trigger-in-progress bit */ - g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_WAITING_FOR_RESP; - - Msg.Cmd.tv_sec = 0xffff; - Msg.Cmd.tv_usec = 0xffff; - - /* Release pool object and try to take another call */ - _SlDrvReleasePoolObj(ObjIdx); - - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&g_pCB->SocketTriggerSelect.Resp, SELECT_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* Save the pool index to be released only after the user read the response */ - g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = ObjIdx; - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL)); - return SL_ERROR_BSD_EAGAIN; - - } - } -#endif - - if( ((_i16)Msg.Rsp.status) >= 0 ) - { - if( readsds ) - { - readsds->fd_array[0] = AsyncRsp.ReadFds; - } - if( writesds ) - { - writesds->fd_array[0] = AsyncRsp.WriteFds; - } - } - } - - _SlDrvReleasePoolObj(ObjIdx); - return (_i16)Msg.Rsp.status; -} - -#endif /* defined(SL_PLATFORM_MULTI_THREADED) || !defined(slcb_SocketTriggerEventHandler) */ -#endif /* _SL_INCLUDE_FUNC(sl_Select) */ -#endif /* SL_TINY */ - -/*******************************************************************************/ -/* sl_StartTLS */ -/*******************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_StartTLS) -_i16 sl_StartTLS(_i16 sd) -{ - _SlReturnVal_t RetVal; - SlSocketAsyncEvent_t AsyncRsp; - _u32 tempValue; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketAsyncEvent_t)); - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, START_TLS_ID, (_u8)(sd & SL_BSD_SOCKET_ID_MASK)); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send Start TLS to sl_SetSockOpt */ - RetVal = sl_SetSockOpt(sd, SL_SOL_SOCKET, SL_SO_STARTTLS, &tempValue, sizeof(tempValue)); - - if(SL_RET_CODE_OK == RetVal) - { - /* wait for async and get Data Read parameters */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - - VERIFY_PROTOCOL(AsyncRsp.Sd == (_u8)sd); - - if (SL_SSL_NOTIFICATION_CONNECTED_SECURED == AsyncRsp.Type) - { - RetVal = SL_RET_CODE_OK; - } - else - { - RetVal = AsyncRsp.Val; - } - } - - _SlDrvReleasePoolObj(ObjIdx); - return RetVal; -} - -/*******************************************************************************/ -/* _SlSocketHandleAsync_StartTLS */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf) -{ - SlSocketAsyncEvent_t *pMsgArgs = (SlSocketAsyncEvent_t *)((_u32)pVoidBuf+sizeof(_u32)); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; - ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Type = pMsgArgs->Type; - ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Val = pMsgArgs->Val; - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.c deleted file mode 100755 index 169f54ce306..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * spawn.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - -typedef struct -{ - _SlSyncObj_t SyncObj; - _u8 IrqWriteCnt; - _u8 IrqReadCnt; - void* pIrqFuncValue; - -#ifdef SL_PLATFORM_MULTI_THREADED - _u32 ThreadId; -#endif -}_SlInternalSpawnCB_t; - -_SlInternalSpawnCB_t g_SlInternalSpawnCB; - -_u8 _SlInternalIsItSpawnThread(_u32 ThreadId) -{ - return (ThreadId == g_SlInternalSpawnCB.ThreadId); -} - -void _SlInternalSpawnWaitForEvent(void) -{ - - sl_SyncObjWait(&g_SlInternalSpawnCB.SyncObj, SL_OS_WAIT_FOREVER); - - /* - * call the processQ function will handle the pending async - * events already read from NWP, and only wait for handling - * the events that have been read only during command execution. */ - _SlSpawnMsgListProcess(); - - /* handle IRQ requests */ - while (g_SlInternalSpawnCB.IrqWriteCnt != g_SlInternalSpawnCB.IrqReadCnt) - { - /* handle the ones that came from ISR context*/ - _SlDrvMsgReadSpawnCtx(g_SlInternalSpawnCB.pIrqFuncValue); - g_SlInternalSpawnCB.IrqReadCnt++; - } - -} - -void* _SlInternalSpawnTaskEntry() -{ - - /* create and clear the sync object */ - sl_SyncObjCreate(&g_SlInternalSpawnCB.SyncObj,"SlSpawnSync"); - sl_SyncObjWait(&g_SlInternalSpawnCB.SyncObj,SL_OS_NO_WAIT); - - g_SlInternalSpawnCB.ThreadId = 0xFFFFFFFF; - -#ifdef SL_PLATFORM_MULTI_THREADED - g_SlInternalSpawnCB.ThreadId = (_i32)pthread_self(); -#endif - - g_SlInternalSpawnCB.IrqWriteCnt = 0; - g_SlInternalSpawnCB.IrqReadCnt = 0; - g_SlInternalSpawnCB.pIrqFuncValue = NULL; - - /* here we ready to execute entries */ - while (TRUE) - { - /* wait for event */ - _SlInternalSpawnWaitForEvent(); - } -} - -_i16 _SlInternalSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags) -{ - _i16 Res = 0; - - /* Increment the counter that specifies that async event has recived - from interrupt context and should be handled by the internal spawn task */ - if ((flags & SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER) || (flags & SL_SPAWN_FLAG_FROM_CMD_CTX)) - { - g_SlInternalSpawnCB.IrqWriteCnt++; - g_SlInternalSpawnCB.pIrqFuncValue = pValue; - SL_DRV_SYNC_OBJ_SIGNAL(&g_SlInternalSpawnCB.SyncObj); - return Res; - } - else if (flags & SL_SPAWN_FLAG_FROM_CMD_PROCESS) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_SlInternalSpawnCB.SyncObj); - } - - return Res; -} - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.h deleted file mode 100755 index e9410bd3e56..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * spawn.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ -#ifndef __SPAWN_H__ -#define __SPAWN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - -extern void* _SlInternalSpawnTaskEntry(); -extern _i16 _SlInternalSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); -extern _u8 _SlInternalIsItSpawnThread(_u32 ThreadId); -#undef sl_Spawn -#define sl_Spawn(pEntry,pValue,flags) _SlInternalSpawn(pEntry,pValue,flags) - -#undef _SlTaskEntry -#define _SlTaskEntry _SlInternalSpawnTaskEntry - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/wlan.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/wlan.c deleted file mode 100755 index b660f924bc5..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/wlan.c +++ /dev/null @@ -1,1208 +0,0 @@ -/* - * wlan.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#define MAX_SSID_LEN (32) -#define MAX_KEY_LEN (64) -#define MAX_USER_LEN (64) -#define MAX_ANON_USER_LEN (64) -#define MAX_SMART_CONFIG_KEY (16) - - -/***************************************************************************** -sl_WlanConnect -*****************************************************************************/ -typedef struct -{ - SlWlanConnectEapCommand_t Args; - _i8 Strings[SL_WLAN_SSID_MAX_LENGTH + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; -}_WlanConnectCmd_t; - -typedef union -{ - _WlanConnectCmd_t Cmd; - _BasicResponse_t Rsp; -}_SlWlanConnectMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanConnect) -_i16 sl_WlanConnect(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams) -{ - _SlWlanConnectMsg_u Msg; - _SlCmdCtrl_t CmdCtrl = {0,0,0}; - - _SlDrvMemZero(&Msg, (_u16)sizeof(_SlWlanConnectMsg_u)); - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - CmdCtrl.TxDescLen = 0;/* init */ - CmdCtrl.RxDescLen = (_SlArgSize_t)sizeof(_BasicResponse_t); - - /* verify SSID length */ - VERIFY_PROTOCOL(NameLen <= SL_WLAN_SSID_MAX_LENGTH); - /* verify SSID is not NULL */ - if( NULL == pName ) - { - return SL_INVALPARAM; - } - /* update SSID length */ - Msg.Cmd.Args.Common.SsidLen = (_u8)NameLen; - - /* Profile with no security */ - /* Enterprise security profile */ - if (NULL != pSecExtParams) - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_WLANCONNECTEAPCOMMAND; - CmdCtrl.TxDescLen += sizeof(SlWlanConnectEapCommand_t); - /* copy SSID */ - sl_Memcpy(EAP_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - /* Copy password if supplied */ - if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) - { - /* update security type */ - Msg.Cmd.Args.Common.SecType = pSecParams->Type; - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - /* update key length */ - Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; - ARG_CHECK_PTR(pSecParams->Key); - /* copy key */ - sl_Memcpy(EAP_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - CmdCtrl.TxDescLen += pSecParams->KeyLen; - } - else - { - Msg.Cmd.Args.Common.PasswordLen = 0; - } - - ARG_CHECK_PTR(pSecExtParams); - /* Update Eap bitmask */ - Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; - /* Update Certificate file ID index - currently not supported */ - Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; - /* verify user length */ - if (pSecExtParams->UserLen > MAX_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; - /* copy user name (identity) */ - if(pSecExtParams->UserLen > 0) - { - sl_Memcpy(EAP_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); - CmdCtrl.TxDescLen += pSecExtParams->UserLen; - } - /* verify Anonymous user length */ - if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; - /* copy Anonymous user */ - if(pSecExtParams->AnonUserLen > 0) - { - sl_Memcpy(EAP_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); - CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; - } - - } - - /* Regular or open security profile */ - else - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_WLANCONNECTCOMMAND; - CmdCtrl.TxDescLen += sizeof(SlWlanConnectCommon_t); - /* copy SSID */ - sl_Memcpy(SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - /* Copy password if supplied */ - if( NULL != pSecParams ) - { - /* update security type */ - Msg.Cmd.Args.Common.SecType = pSecParams->Type; - /* verify key length is valid */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - /* update key length */ - Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - /* copy key (could be no key in case of WPS pin) */ - if( NULL != pSecParams->Key ) - { - sl_Memcpy(PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - } - /* Profile with no security */ - else - { - Msg.Cmd.Args.Common.PasswordLen = 0; - Msg.Cmd.Args.Common.SecType = SL_WLAN_SEC_TYPE_OPEN; - } - } - /* If BSSID is not null, copy to buffer, otherwise set to 0 */ - if(NULL != pMacAddr) - { - sl_Memcpy(Msg.Cmd.Args.Common.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Common.Bssid)); - } - else - { - _SlDrvMemZero(Msg.Cmd.Args.Common.Bssid, (_u16)sizeof(Msg.Cmd.Args.Common.Bssid)); - } - - VERIFY_RET_OK ( _SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*******************************************************************************/ -/* sl_Disconnect */ -/* ******************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_WlanDisconnect) -_i16 sl_WlanDisconnect(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - return _SlDrvBasicCmd(SL_OPCODE_WLAN_WLANDISCONNECTCOMMAND); -} -#endif - -/******************************************************************************/ -/* sl_PolicySet */ -/******************************************************************************/ -typedef union -{ - SlWlanPolicySetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlPolicyMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanPolicySet) - -static const _SlCmdCtrl_t _SlPolicySetCmdCtrl = -{ - SL_OPCODE_WLAN_POLICYSETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_WlanPolicySet(const _u8 Type , const _u8 Policy, _u8 *pVal,const _u8 ValLen) -{ - _SlPolicyMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = ValLen; - CmdExt.pTxPayload1 = (_u8 *)pVal; - - Msg.Cmd.PolicyType = Type; - Msg.Cmd.PolicyOption = Policy; - Msg.Cmd.PolicyOptionLen = ValLen; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlPolicySetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/******************************************************************************/ -/* sl_PolicyGet */ -/******************************************************************************/ -typedef union -{ - SlWlanPolicySetGet_t Cmd; - SlWlanPolicySetGet_t Rsp; -}_SlPolicyGetMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanPolicyGet) - -static const _SlCmdCtrl_t _SlPolicyGetCmdCtrl = -{ - SL_OPCODE_WLAN_POLICYGETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t), - (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t) -}; - -_i16 sl_WlanPolicyGet(const _u8 Type ,_u8 *pPolicy,_u8 *pVal,_u8 *pValLen) -{ - _SlPolicyGetMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - if (*pValLen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(*pValLen); - CmdExt.pRxPayload = pVal; - - Msg.Cmd.PolicyType = Type; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlPolicyGetCmdCtrl, &Msg, &CmdExt)); - - - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pValLen = Msg.Rsp.PolicyOptionLen; - return SL_ESMALLBUF; - } - else - { - /* no pointer valus, fill the results into _i8 */ - *pValLen = (_u8)CmdExt.ActualRxPayloadLen; - *pPolicy = Msg.Rsp.PolicyOption; - - if( 0 == CmdExt.ActualRxPayloadLen ) - { - *pValLen = 1; - } - - } - return (_i16)SL_OS_RET_CODE_OK; -} -#endif - - -/*******************************************************************************/ -/* sl_ProfileAdd */ -/*******************************************************************************/ -typedef struct -{ - SlWlanAddGetEapProfile_t Args; - _i8 Strings[SL_WLAN_SSID_MAX_LENGTH + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; -}_SlProfileParams_t; - -typedef union -{ - _SlProfileParams_t Cmd; - _BasicResponse_t Rsp; -}_SlProfileAddMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanProfileAdd) -_i16 sl_WlanProfileAdd(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority,const _u32 Options) -{ - _SlProfileAddMsg_u Msg; - _SlCmdCtrl_t CmdCtrl = {0,0,0}; - CmdCtrl.TxDescLen = 0;/* init */ - CmdCtrl.RxDescLen = (_SlArgSize_t)(sizeof(_BasicResponse_t)); - - - /* Options parameter is currently not in use */ - (void)Options; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvMemZero(&Msg,sizeof(_SlProfileAddMsg_u)); - - /* update priority */ - Msg.Cmd.Args.Common.Priority = (_u8)Priority; - /* verify SSID is not NULL */ - if( NULL == pName ) - { - return SL_INVALPARAM; - } - /* verify SSID length */ - VERIFY_PROTOCOL(NameLen <= SL_WLAN_SSID_MAX_LENGTH); - /* update SSID length */ - Msg.Cmd.Args.Common.SsidLen = (_u8)NameLen; - - /* Enterprise security profile */ - if (NULL != pSecExtParams) - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND; - CmdCtrl.TxDescLen += sizeof(SlWlanAddGetEapProfile_t); - - /* copy SSID */ - sl_Memcpy(EAP_PROFILE_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - - /* Copy password if supplied */ - if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) - { - /* update security type */ - Msg.Cmd.Args.Common.SecType = (_i8)(pSecParams->Type); - - if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.Common.SecType ) - { - Msg.Cmd.Args.Common.WepKeyId = 0; - } - - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - VERIFY_PROTOCOL(pSecParams->KeyLen <= MAX_KEY_LEN); - /* update key length */ - Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - ARG_CHECK_PTR(pSecParams->Key); - /* copy key */ - sl_Memcpy(EAP_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - else - { - Msg.Cmd.Args.Common.PasswordLen = 0; - } - - ARG_CHECK_PTR(pSecExtParams); - /* Update Eap bitmask */ - Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; - /* Update Certificate file ID index - currently not supported */ - Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; - /* verify user length */ - if (pSecExtParams->UserLen > MAX_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; - /* copy user name (identity) */ - if(pSecExtParams->UserLen > 0) - { - sl_Memcpy(EAP_PROFILE_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); - CmdCtrl.TxDescLen += pSecExtParams->UserLen; - } - - /* verify Anonymous user length (for tunneled) */ - if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; - - /* copy Anonymous user */ - if(pSecExtParams->AnonUserLen > 0) - { - sl_Memcpy(EAP_PROFILE_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); - CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; - } - - } - /* Regular or open security profile */ - else - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEADDCOMMAND; - /* update commnad length */ - CmdCtrl.TxDescLen += sizeof(SlWlanAddGetProfile_t); - - if (NULL != pName) - { - /* copy SSID */ - sl_Memcpy(PROFILE_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - } - - /* Copy password if supplied */ - if( NULL != pSecParams ) - { - /* update security type */ - Msg.Cmd.Args.Common.SecType = (_i8)(pSecParams->Type); - - if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.Common.SecType ) - { - Msg.Cmd.Args.Common.WepKeyId = 0; - } - - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - /* update key length */ - Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - /* copy key (could be no key in case of WPS pin) */ - if( NULL != pSecParams->Key ) - { - sl_Memcpy(PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - } - else - { - Msg.Cmd.Args.Common.SecType = SL_WLAN_SEC_TYPE_OPEN; - Msg.Cmd.Args.Common.PasswordLen = 0; - } - } - - /* If BSSID is not null, copy to buffer, otherwise set to 0 */ - if(NULL != pMacAddr) - { - sl_Memcpy(Msg.Cmd.Args.Common.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Common.Bssid)); - } - else - { - _SlDrvMemZero(Msg.Cmd.Args.Common.Bssid, (_u16)sizeof(Msg.Cmd.Args.Common.Bssid)); - } - - VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/*******************************************************************************/ -/* sl_ProfileUpdate */ -/*******************************************************************************/ - -typedef struct -{ - SlWlanUpdateProfile_t Args; - _i8 Strings[MAX_SSID_LEN + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; -}_SlProfileUpdateParams_t; - -typedef union -{ - _SlProfileUpdateParams_t Cmd; - _BasicResponse_t Rsp; -}_SlProfileUpdateMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanProfileUpdate) -_i16 sl_WlanProfileUpdate(const _u32 Index, const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority) -{ - _SlProfileUpdateMsg_u Msg; - _SlCmdCtrl_t CmdCtrl = {0,0,0}; - CmdCtrl.TxDescLen = 0;/* init */ - CmdCtrl.RxDescLen = (_SlArgSize_t)(sizeof(_BasicResponse_t)); - - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvMemZero(&Msg,sizeof(_SlProfileUpdateParams_t)); - - Msg.Cmd.Args.Index = Index; - /* update priority */ - Msg.Cmd.Args.Priority = (_u8)Priority; - - /* verify SSID length */ - VERIFY_PROTOCOL(NameLen <= MAX_SSID_LEN); - /* update SSID length */ - Msg.Cmd.Args.SsidLen = (_u8)NameLen; - - - /* Enterprise security profile */ - if (NULL != pSecExtParams) - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEEAPUPDATECOMMAND; - CmdCtrl.TxDescLen += sizeof(SlWlanUpdateProfile_t); - - /* If SSID is supplied, copy it */ - if (NULL != pName) - { - sl_Memcpy(UPDATE_PROFILE_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - } - else - { - Msg.Cmd.Args.SsidLen = 0; - } - - - /* Copy password if supplied */ - if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) - { - /* update security type */ - Msg.Cmd.Args.SecType = (_i8)(pSecParams->Type); - - if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.SecType ) - { - Msg.Cmd.Args.WepKeyId = 0; - } - - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - VERIFY_PROTOCOL(pSecParams->KeyLen <= MAX_KEY_LEN); - /* update key length */ - Msg.Cmd.Args.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - ARG_CHECK_PTR(pSecParams->Key); - /* copy key */ - sl_Memcpy(UPDATE_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - else - { - Msg.Cmd.Args.PasswordLen = 0; - } - - ARG_CHECK_PTR(pSecExtParams); - /* Update Eap bitmask */ - Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; - /* Update Certificate file ID index - currently not supported */ - Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; - /* verify user length */ - if (pSecExtParams->UserLen > MAX_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; - /* copy user name (identity) */ - if(pSecExtParams->UserLen > 0) - { - sl_Memcpy(UPDATE_PROFILE_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); - CmdCtrl.TxDescLen += pSecExtParams->UserLen; - } - - /* verify Anonymous user length (for tunneled) */ - if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; - - /* copy Anonymous user */ - if(pSecExtParams->AnonUserLen > 0) - { - sl_Memcpy(UPDATE_PROFILE_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); - CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; - } - - } - /* Regular or open security profile */ - else - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEUPDATECOMMAND; - /* update commnad length */ - CmdCtrl.TxDescLen += sizeof(SlWlanUpdateProfile_t); - - if (NULL != pName) - { - /* copy SSID */ - sl_Memcpy(UPDATE_PROFILE_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - } - else - { - Msg.Cmd.Args.SsidLen = 0; - } - - /* Copy password if supplied */ - if( NULL != pSecParams ) - { - /* update security type */ - Msg.Cmd.Args.SecType = (_i8)(pSecParams->Type); - - if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.SecType ) - { - Msg.Cmd.Args.WepKeyId = 0; - } - - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - /* update key length */ - Msg.Cmd.Args.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - /* copy key (could be no key in case of WPS pin) */ - if( NULL != pSecParams->Key ) - { - sl_Memcpy(UPDATE_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - } - else - { - Msg.Cmd.Args.SecType = SL_WLAN_SEC_TYPE_OPEN; - Msg.Cmd.Args.PasswordLen = 0; - } - - } - - - /* If BSSID is not null, copy to buffer, otherwise set to 0 */ - if(NULL != pMacAddr) - { - sl_Memcpy(Msg.Cmd.Args.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Bssid)); - } - else - { - _SlDrvMemZero(Msg.Cmd.Args.Bssid, (_u16)sizeof(Msg.Cmd.Args.Bssid)); - } - - VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif -/*******************************************************************************/ -/* sl_ProfileGet */ -/*******************************************************************************/ -typedef union -{ - SlWlanProfileDelGetCommand_t Cmd; - _SlProfileParams_t Rsp; -}_SlProfileGetMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanProfileGet) - -static const _SlCmdCtrl_t _SlProfileGetCmdCtrl = -{ - SL_OPCODE_WLAN_PROFILEGETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanProfileDelGetCommand_t), - (_SlArgSize_t)sizeof(_SlProfileParams_t) -}; - -_i16 sl_WlanProfileGet(const _i16 Index,_i8* pName, _i16 *pNameLen, _u8 *pMacAddr, SlWlanSecParams_t* pSecParams, SlWlanGetSecParamsExt_t* pEntParams, _u32 *pPriority) -{ - _SlProfileGetMsg_u Msg; - Msg.Cmd.Index = (_u8)Index; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProfileGetCmdCtrl, &Msg, NULL)); - - pSecParams->Type = (_u8)(Msg.Rsp.Args.Common.SecType); - if (Msg.Rsp.Args.Common.SecType >= 0) - { - /* since password is not transferred in getprofile, password length should always be zero */ - pSecParams->KeyLen = Msg.Rsp.Args.Common.PasswordLen; - if (NULL != pEntParams) - { - pEntParams->EapMethod = Msg.Rsp.Args.EapBitmask; - pEntParams->UserLen = Msg.Rsp.Args.UserLen; - /* copy user name */ - if (pEntParams->UserLen > 0) - { - sl_Memcpy(pEntParams->User, EAP_PROFILE_USER_STRING(&Msg), pEntParams->UserLen); - } - pEntParams->AnonUserLen = Msg.Rsp.Args.AnonUserLen; - /* copy anonymous user name */ - if (pEntParams->AnonUserLen > 0) - { - sl_Memcpy(pEntParams->AnonUser, EAP_PROFILE_ANON_USER_STRING(&Msg), pEntParams->AnonUserLen); - } - } - - *pNameLen = (_i16)(Msg.Rsp.Args.Common.SsidLen); - *pPriority = Msg.Rsp.Args.Common.Priority; - - //if (NULL != Msg.Rsp.Args.Common.Bssid) - { - sl_Memcpy(pMacAddr, Msg.Rsp.Args.Common.Bssid, sizeof(Msg.Rsp.Args.Common.Bssid)); - } - - sl_Memset(pName, 0, SL_WLAN_SSID_MAX_LENGTH); - sl_Memcpy(pName, EAP_PROFILE_SSID_STRING(&Msg), *pNameLen); - } - return (_i16)Msg.Rsp.Args.Common.SecType; -} -#endif -/*******************************************************************************/ -/* sl_ProfileDel */ -/*******************************************************************************/ -typedef union -{ - SlWlanProfileDelGetCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlProfileDelMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanProfileDel) - -static const _SlCmdCtrl_t _SlProfileDelCmdCtrl = -{ - SL_OPCODE_WLAN_PROFILEDELCOMMAND, - (_SlArgSize_t)sizeof(SlWlanProfileDelGetCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_WlanProfileDel(const _i16 Index) -{ - _SlProfileDelMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - Msg.Cmd.Index = (_u8)Index; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProfileDelCmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/******************************************************************************/ -/* sl_WlanGetNetworkList */ -/******************************************************************************/ -typedef union -{ - SlWlanGetNetworkListCommand_t Cmd; - _WlanGetNetworkListResponse_t Rsp; -}_SlWlanGetNetworkListMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanGetNetworkList) - -static const _SlCmdCtrl_t _SlWlanGetNetworkListCtrl = -{ - SL_OPCODE_WLAN_SCANRESULTSGETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanGetNetworkListCommand_t), - (_SlArgSize_t)sizeof(_WlanGetNetworkListResponse_t) -}; - -_i16 sl_WlanGetNetworkList(const _u8 Index,const _u8 Count, SlWlanNetworkEntry_t *pEntries) -{ - _i16 retVal = 0; - _SlWlanGetNetworkListMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - if (Count == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(sizeof(SlWlanNetworkEntry_t)*(Count)); - CmdExt.pRxPayload = (_u8 *)pEntries; - - Msg.Cmd.Index = Index; - Msg.Cmd.Count = Count; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanGetNetworkListCtrl, &Msg, &CmdExt)); - retVal = Msg.Rsp.status; - - return (_i16)retVal; -} -#endif - -/******************************************************************************/ -/* sl_WlanGetExtNetworkList */ -/******************************************************************************/ -typedef union -{ - SlWlanGetExtNetworkListCommand_t Cmd; - _WlanGetExtNetworkListResponse_t Rsp; -}_SlWlanGetExtNetworkListMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanGetExtNetworkList) - -static const _SlCmdCtrl_t _SlWlanGetExtNetworkListCtrl = -{ - SL_OPCODE_WLAN_EXTSCANRESULTSGETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanGetExtNetworkListCommand_t), - (_SlArgSize_t)sizeof(_WlanGetExtNetworkListResponse_t) -}; - -_i16 sl_WlanGetExtNetworkList(const _u8 Index,const _u8 Count, SlWlanExtNetworkEntry_t *pEntries) -{ - _i16 retVal = 0; - _SlWlanGetExtNetworkListMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - if (Count == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(sizeof(SlWlanExtNetworkEntry_t)*(Count)); - CmdExt.pRxPayload = (_u8 *)pEntries; - - Msg.Cmd.Index = Index; - Msg.Cmd.Count = Count; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanGetExtNetworkListCtrl, &Msg, &CmdExt)); - retVal = Msg.Rsp.status; - - return (_i16)retVal; -} -#endif - - -/******************************************************************************/ -/* RX filters message command response structures */ -/******************************************************************************/ - - -typedef union -{ - SlWlanRxFilterAddCommand_t Cmd; - SlWlanRxFilterAddCommandReponse_t Rsp; -}_SlWlanRxFilterAddMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanRxFilterAdd) - -static const _SlCmdCtrl_t _SlWlanRxFilterAddtCmdCtrl = -{ - SL_OPCODE_WLAN_WLANRXFILTERADDCOMMAND, - (_SlArgSize_t)sizeof(SlWlanRxFilterAddCommand_t), - (_SlArgSize_t)sizeof(SlWlanRxFilterAddCommandReponse_t) -}; - - -/***************************************************************************** - RX filters -*****************************************************************************/ -_i16 sl_WlanRxFilterAdd(SlWlanRxFilterRuleType_t RuleType, - SlWlanRxFilterFlags_u Flags, - const SlWlanRxFilterRule_u* const pRule, - const SlWlanRxFilterTrigger_t* const pTrigger, - const SlWlanRxFilterAction_t* const pAction, - SlWlanRxFilterID_t* pFilterId) -{ - _SlWlanRxFilterAddMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - Msg.Cmd.RuleType = RuleType; - /* filterId is zero */ - Msg.Cmd.FilterId = 0; - Msg.Cmd.Flags = Flags; - sl_Memcpy( &(Msg.Cmd.Rule), pRule, sizeof(SlWlanRxFilterRule_u) ); - sl_Memcpy( &(Msg.Cmd.Trigger), pTrigger, sizeof(SlWlanRxFilterTrigger_t) ); - sl_Memcpy( &(Msg.Cmd.Action), pAction, sizeof(SlWlanRxFilterAction_t) ); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanRxFilterAddtCmdCtrl, &Msg, NULL) ); - *pFilterId = Msg.Rsp.FilterId; - return (_i16)Msg.Rsp.Status; -} -#endif - - -/*******************************************************************************/ -/* sl_WlanRxStatStart */ -/*******************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_WlanRxStatStart) -_i16 sl_WlanRxStatStart(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - return _SlDrvBasicCmd(SL_OPCODE_WLAN_STARTRXSTATCOMMAND); -} -#endif - -#if _SL_INCLUDE_FUNC(sl_WlanRxStatStop) -_i16 sl_WlanRxStatStop(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - return _SlDrvBasicCmd(SL_OPCODE_WLAN_STOPRXSTATCOMMAND); -} -#endif - -#if _SL_INCLUDE_FUNC(sl_WlanRxStatGet) -_i16 sl_WlanRxStatGet(SlWlanGetRxStatResponse_t *pRxStat,const _u32 Flags) -{ - _SlCmdCtrl_t CmdCtrl = {SL_OPCODE_WLAN_GETRXSTATCOMMAND, 0, (_SlArgSize_t)sizeof(SlWlanGetRxStatResponse_t)}; - /* Flags paramater is currently not in use */ - (void)Flags; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvMemZero(pRxStat, (_u16)sizeof(SlWlanGetRxStatResponse_t)); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, pRxStat, NULL)); - - return 0; -} -#endif - -/******************************************************************************/ -/* sl_WlanProvisioning */ -/******************************************************************************/ - -typedef struct -{ - SlWlanSmartConfigParams_t Args; - _i8 Key[MAX_SMART_CONFIG_KEY]; /* public key + groupId1 key + groupId2 key */ -}_SlSmartConfigArgs_t; - -typedef struct -{ - SlWlanProvisioningParams_t ProvParams; - _SlSmartConfigArgs_t SmartConfigParams; -}_SlProvisioning_t; - -typedef union -{ - _SlProvisioning_t Cmd; - _BasicResponse_t Rsp; -}_SlProvisioningStartMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanProvisioning) - -const _SlCmdCtrl_t _SlProvisioningCmdCtrl = -{ - SL_OPCODE_WLAN_PROVISIONING_COMMAND, - sizeof(_SlProvisioning_t), - sizeof(_BasicResponse_t) -}; - -_i16 sl_WlanProvisioning(_u8 ProvisioningCmd, _u8 RequestedRoleAfterSuccess, _u16 InactivityTimeoutSec, char *pSmartConfigKey, _u32 Flags) -{ - _SlProvisioningStartMsg_u Msg; - - /* Verify if we can send this command to the NWP - We can send only prov. stop command if command is not allowed */ - if ((!SL_IS_COMMAND_ALLOWED) && (!SL_IS_PROVISIONING_ACTIVE) && (InactivityTimeoutSec != 0)) - { - /* return with the correct error code */ - return _SlDrvDriverIsApiAllowed(SL_OPCODE_SILO_WLAN); - } - - /* If there is an API in progress and the timeout is not zero (it means the - command is not prov. stop) then abort and return an error code */ - if (_SlDrvIsApiInProgress() && (InactivityTimeoutSec !=0)) - { - return SL_RET_CODE_API_COMMAND_IN_PROGRESS; - } - - _SlDrvMemZero(&Msg, (_u16)sizeof (_SlProvisioningStartMsg_u)); - - Msg.Cmd.ProvParams.ProvisioningCmd = (_u8)ProvisioningCmd; - Msg.Cmd.ProvParams.RequestedRoleAfterSuccess = (_u8)RequestedRoleAfterSuccess; - Msg.Cmd.ProvParams.InactivityTimeoutSec = (_u16)InactivityTimeoutSec; - Msg.Cmd.ProvParams.Flags = Flags; - - /* Smart Config parameters */ - if (NULL != pSmartConfigKey) - { - Msg.Cmd.SmartConfigParams.Args.GroupIdBitmask = SL_WLAN_SMART_CONFIG_DEFAULT_GROUP; - Msg.Cmd.SmartConfigParams.Args.Cipher = SL_WLAN_SMART_CONFIG_DEFAULT_CIPHER; - Msg.Cmd.SmartConfigParams.Args.PublicKeyLen = SL_WLAN_SMART_CONFIG_KEY_LENGTH; - - /* copy keys (if exist) after command (one after another) */ - sl_Memcpy(Msg.Cmd.SmartConfigParams.Key, pSmartConfigKey, SL_WLAN_SMART_CONFIG_KEY_LENGTH); - } - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProvisioningCmdCtrl , &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*******************************************************************************/ -/* sl_WlanSetMode */ -/*******************************************************************************/ -typedef union -{ - SlWlanSetMode_t Cmd; - _BasicResponse_t Rsp; -}_SlwlanSetModeMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanSetMode) - -static const _SlCmdCtrl_t _SlWlanSetModeCmdCtrl = -{ - SL_OPCODE_WLAN_SET_MODE, - (_SlArgSize_t)sizeof(SlWlanSetMode_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -/* possible values are: -WLAN_SET_STA_MODE = 1 -WLAN_SET_AP_MODE = 2 -WLAN_SET_P2P_MODE = 3 */ -_i16 sl_WlanSetMode(const _u8 Mode) -{ - _SlwlanSetModeMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - Msg.Cmd.Mode = Mode; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanSetModeCmdCtrl , &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*******************************************************************************/ -/* sl_WlanSet */ -/* ******************************************************************************/ -typedef union -{ - SlWlanCfgSetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlWlanCfgSetMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanSet) - -static const _SlCmdCtrl_t _SlWlanCfgSetCmdCtrl = -{ - SL_OPCODE_WLAN_CFG_SET, - (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_WlanSet(const _u16 ConfigId ,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues) -{ - _SlWlanCfgSetMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (_u16)((ConfigLen+3) & (~3)); - CmdExt.pTxPayload1 = (_u8 *)pValues; - - Msg.Cmd.ConfigId = ConfigId; - Msg.Cmd.ConfigLen = ConfigLen; - Msg.Cmd.ConfigOpt = ConfigOpt; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanCfgSetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/******************************************************************************/ -/* sl_WlanGet */ -/******************************************************************************/ -typedef union -{ - SlWlanCfgSetGet_t Cmd; - SlWlanCfgSetGet_t Rsp; -}_SlWlanCfgMsgGet_u; - -#if _SL_INCLUDE_FUNC(sl_WlanGet) - -static const _SlCmdCtrl_t _SlWlanCfgGetCmdCtrl = -{ - SL_OPCODE_WLAN_CFG_GET, - (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t), - (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t) -}; - -_i16 sl_WlanGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues) -{ - _SlWlanCfgMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - if (*pConfigLen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)*pConfigLen; - CmdExt.pRxPayload = (_u8 *)pValues; - Msg.Cmd.ConfigLen = *pConfigLen; - Msg.Cmd.ConfigId = ConfigId; - if( pConfigOpt ) - { - Msg.Cmd.ConfigOpt = (_u16)*pConfigOpt; - } - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanCfgGetCmdCtrl, &Msg, &CmdExt)); - - if( pConfigOpt ) - { - *pConfigOpt = (_u8)Msg.Rsp.ConfigOpt; - } - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pConfigLen = (_u8)CmdExt.RxPayloadLen; - return SL_ESMALLBUF; - } - else - { - *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen; - } - - return (_i16)Msg.Rsp.Status; -} -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/trace.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/trace.h deleted file mode 100755 index 264c7662cb2..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/trace.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * trace.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -#include - -#ifndef __SIMPLELINK_TRACE_H__ -#define __SIMPLELINK_TRACE_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SL_SYNC_SCAN_THRESHOLD (( _u32 )2000) - -#ifdef SL_TINY -#define _SlDrvAssert(line ) { while(1); } -#else -#define _SlDrvAssert() _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_DRIVER_ABORT, 0, 0) -#endif - -#define _SL_ASSERT(expr) {if(!(expr)){ _SlDrvAssert();}} -#define _SL_ERROR(expr, error) {if(!(expr)){return (error);}} - -#define _SL_ASSERT_ERROR(expr, error) {if(!(expr)){_SlDrvAssert(); return (error);}} - -#define SL_HANDLING_ASSERT 2 -#define SL_HANDLING_ERROR 1 -#define SL_HANDLING_NONE 0 - -#ifndef SL_TINY -#define SL_SELF_COND_HANDLING SL_HANDLING_ASSERT -#define SL_PROTOCOL_HANDLING SL_HANDLING_ASSERT -#define SL_DRV_RET_CODE_HANDLING SL_HANDLING_ERROR -#define SL_NWP_IF_HANDLING SL_HANDLING_ASSERT -#define SL_OSI_RET_OK_HANDLING SL_HANDLING_ERROR -#define SL_MALLOC_OK_HANDLING SL_HANDLING_ASSERT -#define SL_USER_ARGS_HANDLING SL_HANDLING_ASSERT -#define SL_ERR_IN_PROGRESS_HANDLING SL_HANDLING_ERROR -#define SL_ERR_IN_API_ALLOWED SL_HANDLING_ERROR -#else -#define SL_SELF_COND_HANDLING SL_HANDLING_NONE -#define SL_PROTOCOL_HANDLING SL_HANDLING_NONE -#define SL_DRV_RET_CODE_HANDLING SL_HANDLING_NONE -#define SL_NWP_IF_HANDLING SL_HANDLING_NONE -#define SL_OSI_RET_OK_HANDLING SL_HANDLING_NONE -#define SL_MALLOC_OK_HANDLING SL_HANDLING_NONE -#define SL_USER_ARGS_HANDLING SL_HANDLING_NONE -#define SL_ERR_IN_PROGRESS_HANDLING SL_HANDLING_NONE -#define SL_ERR_IN_API_ALLOWED SL_HANDLING_NONE -#endif - - -#if (SL_ERR_IN_PROGRESS_HANDLING == SL_HANDLING_ERROR) -#define VERIFY_NO_ERROR_HANDLING_IN_PROGRESS() { \ - if (SL_IS_RESTART_REQUIRED) return SL_API_ABORTED; } -#else -#define VERIFY_NO_ERROR_HANDLING_IN_PROGRESS() -#endif - -#if (SL_ERR_IN_API_ALLOWED == SL_HANDLING_ERROR) -#define VERIFY_API_ALLOWED(Silo) { \ - _SlReturnVal_t status = _SlDrvDriverIsApiAllowed(Silo); \ - if ( status ) return status; } -#else -#define VERIFY_API_ALLOWED(Silo) -#endif - -#if (SL_DRV_RET_CODE_HANDLING == SL_HANDLING_ASSERT) -#define VERIFY_RET_OK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)} -#elif (SL_DRV_RET_CODE_HANDLING == SL_HANDLING_ERROR) -#define VERIFY_RET_OK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return (_SlReturnVal_t)_RetVal;} -#else -#define VERIFY_RET_OK(Func) (Func); -#endif - -#if (SL_PROTOCOL_HANDLING == SL_HANDLING_ASSERT) -#define VERIFY_PROTOCOL(expr) _SL_ASSERT(expr) -#elif (SL_PROTOCOL_HANDLING == SL_HANDLING_ERROR) -#define VERIFY_PROTOCOL(expr) _SL_ERROR(expr, SL_RET_CODE_PROTOCOL_ERROR) -#else -#define VERIFY_PROTOCOL(expr) -#endif - -#if (defined(PROTECT_SOCKET_ASYNC_RESP) && (SL_SELF_COND_HANDLING == SL_HANDLING_ASSERT)) -#define VERIFY_SOCKET_CB(expr) _SL_ASSERT(expr) -#elif (defined(PROTECT_SOCKET_ASYNC_RESP) && (SL_SELF_COND_HANDLING == SL_HANDLING_ERROR)) -#define VERIFY_SOCKET_CB(expr) _SL_ERROR(expr, SL_RET_CODE_SELF_ERROR) -#else -#define VERIFY_SOCKET_CB(expr) -#endif - -#if (SL_NWP_IF_HANDLING == SL_HANDLING_ASSERT) -#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { _i16 RetSize, ExpSize = (_i16)(len); RetSize = sl_IfWrite((fd),(pBuff),ExpSize); _SL_ASSERT(ExpSize == RetSize)} -#define NWP_IF_READ_CHECK(fd,pBuff,len) { _i16 RetSize, ExpSize = (_i16)(len); RetSize = sl_IfRead((fd),(pBuff),ExpSize); _SL_ASSERT(ExpSize == RetSize)} -#elif (SL_NWP_IF_HANDLING == SL_HANDLING_ERROR) -#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { _SL_ERROR((len == sl_IfWrite((fd),(pBuff),(len))), SL_RET_CODE_NWP_IF_ERROR);} -#define NWP_IF_READ_CHECK(fd,pBuff,len) { _SL_ERROR((len == sl_IfRead((fd),(pBuff),(len))), SL_RET_CODE_NWP_IF_ERROR);} -#else -#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { sl_IfWrite((fd),(pBuff),(len));} -#define NWP_IF_READ_CHECK(fd,pBuff,len) { sl_IfRead((fd),(pBuff),(len));} -#endif - -#if (SL_OSI_RET_OK_HANDLING == SL_HANDLING_ASSERT) -#define OSI_RET_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)} -#elif (SL_OSI_RET_OK_HANDLING == SL_HANDLING_ERROR) -#define OSI_RET_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return _RetVal;} -#else -#define OSI_RET_OK_CHECK(Func) (Func); -#endif - -#if (SL_MALLOC_OK_HANDLING == SL_HANDLING_ASSERT) -#define MALLOC_OK_CHECK(Ptr) _SL_ASSERT(NULL != Ptr) -#elif (SL_MALLOC_OK_HANDLING == SL_HANDLING_ERROR) -#define MALLOC_OK_CHECK(Ptr) _SL_ERROR((NULL != Ptr), SL_RET_CODE_MALLOC_ERROR) -#else -#define MALLOC_OK_CHECK(Ptr) -#endif - -#ifdef SL_INC_ARG_CHECK - -#if (SL_USER_ARGS_HANDLING == SL_HANDLING_ASSERT) -#define ARG_CHECK_PTR(Ptr) _SL_ASSERT(NULL != Ptr) -#elif (SL_USER_ARGS_HANDLING == SL_HANDLING_ERROR) -#define ARG_CHECK_PTR(Ptr) _SL_ERROR((NULL != Ptr), SL_RET_CODE_INVALID_INPUT) -#else -#define ARG_CHECK_PTR(Ptr) -#endif - -#else -#define ARG_CHECK_PTR(Ptr) -#endif - -/*#define SL_DBG_TRACE_ENABLE*/ -#ifdef SL_DBG_TRACE_ENABLE -#define SL_TRACE0(level,msg_id,str) printf(str) -#define SL_TRACE1(level,msg_id,str,p1) printf(str,(p1)) -#define SL_TRACE2(level,msg_id,str,p1,p2) printf(str,(p1),(p2)) -#define SL_TRACE3(level,msg_id,str,p1,p2,p3) printf(str,(p1),(p2),(p3)) -#define SL_TRACE4(level,msg_id,str,p1,p2,p3,p4) printf(str,(p1),(p2),(p3),(p4)) -#define SL_ERROR_TRACE(msg_id,str) printf(str) -#define SL_ERROR_TRACE1(msg_id,str,p1) printf(str,(p1)) -#define SL_ERROR_TRACE2(msg_id,str,p1,p2) printf(str,(p1),(p2)) -#define SL_ERROR_TRACE3(msg_id,str,p1,p2,p3) printf(str,(p1),(p2),(p3)) -#define SL_ERROR_TRACE4(msg_id,str,p1,p2,p3,p4) printf(str,(p1),(p2),(p3),(p4)) -#define SL_TRACE_FLUSH() -#else -#define SL_TRACE0(level,msg_id,str) -#define SL_TRACE1(level,msg_id,str,p1) -#define SL_TRACE2(level,msg_id,str,p1,p2) -#define SL_TRACE3(level,msg_id,str,p1,p2,p3) -#define SL_TRACE4(level,msg_id,str,p1,p2,p3,p4) -#define SL_ERROR_TRACE(msg_id,str) -#define SL_ERROR_TRACE1(msg_id,str,p1) -#define SL_ERROR_TRACE2(msg_id,str,p1,p2) -#define SL_ERROR_TRACE3(msg_id,str,p1,p2,p3) -#define SL_ERROR_TRACE4(msg_id,str,p1,p2,p3,p4) -#define SL_TRACE_FLUSH() -#endif - -/* #define SL_DBG_CNT_ENABLE */ -#ifdef SL_DBG_CNT_ENABLE -#define _SL_DBG_CNT_INC(Cnt) g_DbgCnt. ## Cnt++ -#define _SL_DBG_SYNC_LOG(index,value) {if(index < SL_DBG_SYNC_LOG_SIZE){*(_u32 *)&g_DbgCnt.SyncLog[index] = *(_u32 *)(value);}} - -#else -#define _SL_DBG_CNT_INC(Cnt) -#define _SL_DBG_SYNC_LOG(index,value) -#endif - -#define SL_DBG_LEVEL_1 1 -#define SL_DBG_LEVEL_2 2 -#define SL_DBG_LEVEL_3 4 -#define SL_DBG_LEVEL_MASK (SL_DBG_LEVEL_2|SL_DBG_LEVEL_3) - -#define SL_INCLUDE_DBG_FUNC(Name) ((Name ## _DBG_LEVEL) & SL_DBG_LEVEL_MASK) - -#define _SlDrvPrintStat_DBG_LEVEL SL_DBG_LEVEL_3 -#define _SlDrvOtherFunc_DBG_LEVEL SL_DBG_LEVEL_1 - -#ifdef __cplusplus -} -#endif - - -#endif /*__SIMPLELINK_TRACE_H__*/ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/wlan.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/wlan.h deleted file mode 100755 index 302d7c280eb..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/wlan.h +++ /dev/null @@ -1,2282 +0,0 @@ -/* - * wlan.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __WLAN_H__ -#define __WLAN_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -/*! - \defgroup Wlan - \short Controls the use of the WiFi WLAN module - -*/ -/*! - - \addtogroup Wlan - - Connection features, such as: profiles, policies, SmartConfig(tm) - - Advanced WLAN features, such as: scans, rx filters and rx statistics collection - - @{ - -*/ - -#define SL_WLAN_BSSID_LENGTH (6) -#define SL_WLAN_SSID_MAX_LENGTH (32) - -#define SL_WLAN_NUM_OF_RATE_INDEXES (20) -#define SL_WLAN_SIZE_OF_RSSI_HISTOGRAM (6) -#define SL_WLAN_SMART_CONFIG_KEY_LENGTH (16) -#define SL_WLAN_SMART_CONFIG_DEFAULT_CIPHER (1) -#define SL_WLAN_SMART_CONFIG_DEFAULT_GROUP (0) - -#define SL_WLAN_MAX_PROFILES (7) -#define SL_WLAN_DEL_ALL_PROFILES (255) - -typedef enum -{ - SL_WLAN_P2P_WPS_METHOD_DEFAULT, - SL_WLAN_P2P_WPS_METHOD_PIN_USER, - SL_WLAN_P2P_WPS_METHOD_PIN_MACHINE, - SL_WLAN_P2P_WPS_METHOD_REKEY, - SL_WLAN_P2P_WPS_METHOD_PBC, - SL_WLAN_P2P_WPS_METHOD_REGISTRAR -} SlWlanP2PWpsMethod_e; - -/* WLAN user events */ -typedef enum -{ - SL_WLAN_EVENT_CONNECT = 1, - SL_WLAN_EVENT_DISCONNECT, - SL_WLAN_EVENT_STA_ADDED, - SL_WLAN_EVENT_STA_REMOVED, - - SL_WLAN_EVENT_P2P_CONNECT, - SL_WLAN_EVENT_P2P_DISCONNECT, - SL_WLAN_EVENT_P2P_CLIENT_ADDED, - SL_WLAN_EVENT_P2P_CLIENT_REMOVED, - SL_WLAN_EVENT_P2P_DEVFOUND, - SL_WLAN_EVENT_P2P_REQUEST, - SL_WLAN_EVENT_P2P_CONNECTFAIL, - - SL_WLAN_EVENT_RXFILTER, - SL_WLAN_EVENT_PROVISIONING_STATUS, - SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED, - SL_WLAN_EVENT_RESERVED, - SL_WLAN_EVENT_MAX - -} SlWlanEventId_e; - - -/* WLAN Disconnect Reason Codes */ -#define SL_WLAN_DISCONNECT_UNSPECIFIED (1) - #define SL_WLAN_DISCONNECT_AUTH_NO_LONGER_VALID (2) - #define SL_WLAN_DISCONNECT_DEAUTH_SENDING_STA_LEAVING (3) - #define SL_WLAN_DISCONNECT_INACTIVITY (4) - #define SL_WLAN_DISCONNECT_TOO_MANY_STA (5) - #define SL_WLAN_DISCONNECT_FRAME_FROM_NONAUTH_STA (6) - #define SL_WLAN_DISCONNECT_FRAME_FROM_NONASSOC_STA (7) - #define SL_WLAN_DISCONNECT_DISS_SENDING_STA_LEAVING (8) - #define SL_WLAN_DISCONNECT_STA_NOT_AUTH (9) - #define SL_WLAN_DISCONNECT_POWER_CAPABILITY_INVALID (10) - #define SL_WLAN_DISCONNECT_SUPPORTED_CHANNELS_INVALID (11) - #define SL_WLAN_DISCONNECT_INVALID_IE (13) - #define SL_WLAN_DISCONNECT_MIC_FAILURE (14) - #define SL_WLAN_DISCONNECT_FOURWAY_HANDSHAKE_TIMEOUT (15) - #define SL_WLAN_DISCONNECT_GROUPKEY_HANDSHAKE_TIMEOUT (16) - #define SL_WLAN_DISCONNECT_REASSOC_INVALID_IE (17) - #define SL_WLAN_DISCONNECT_INVALID_GROUP_CIPHER (18) - #define SL_WLAN_DISCONNECT_INVALID_PAIRWISE_CIPHER (19) - #define SL_WLAN_DISCONNECT_INVALID_AKMP (20) - #define SL_WLAN_DISCONNECT_UNSUPPORTED_RSN_VERSION (21) - #define SL_WLAN_DISCONNECT_INVALID_RSN_CAPABILITIES (22) - #define SL_WLAN_DISCONNECT_IEEE_802_1X_AUTHENTICATION_FAILED (23) - #define SL_WLAN_DISCONNECT_CIPHER_SUITE_REJECTED (24) - #define SL_WLAN_DISCONNECT_DISASSOC_QOS (32) - #define SL_WLAN_DISCONNECT_DISASSOC_QOS_BANDWIDTH (33) - #define SL_WLAN_DISCONNECT_DISASSOC_EXCESSIVE_ACK_PENDING (34) - #define SL_WLAN_DISCONNECT_DISASSOC_TXOP_LIMIT (35) - #define SL_WLAN_DISCONNECT_STA_LEAVING (36) - #define SL_WLAN_DISCONNECT_STA_DECLINED (37) - #define SL_WLAN_DISCONNECT_STA_UNKNOWN_BA (38) - #define SL_WLAN_DISCONNECT_STA_TIMEOUT (39) - #define SL_WLAN_DISCONNECT_STA_UNSUPPORTED_CIPHER_SUITE (40) - #define SL_WLAN_DISCONNECT_USER_INITIATED (200) - #define SL_WLAN_DISCONNECT_AUTH_TIMEOUT (202) - #define SL_WLAN_DISCONNECT_ASSOC_TIMEOUT (203) - #define SL_WLAN_DISCONNECT_SECURITY_FAILURE (204) - #define SL_WLAN_DISCONNECT_WHILE_CONNNECTING (208) - #define SL_WLAN_DISCONNECT_MISSING_CERT (209) - #define SL_WLAN_DISCONNECT_CERTIFICATE_EXPIRED (210) - - - -#define SL_WLAN_STATUS_DISCONNECTED (0) -#define SL_WLAN_STATUS_SCANING (1) -#define SL_WLAN_STATUS_CONNECTING (2) -#define SL_WLAN_STATUS_CONNECTED (3) - -#define SL_WLAN_PROVISIONING_GENERAL_ERROR (0) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_NETWORK_NOT_FOUND (1) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_CONNECTION_FAILED (2) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_CONNECTION_SUCCESS_IP_NOT_ACQUIRED (3) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS_FEEDBACK_FAILED (4) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS (5) -#define SL_WLAN_PROVISIONING_ERROR_ABORT (6) -#define SL_WLAN_PROVISIONING_ERROR_ABORT_INVALID_PARAM (7) -#define SL_WLAN_PROVISIONING_ERROR_ABORT_HTTP_SERVER_DISABLED (8) -#define SL_WLAN_PROVISIONING_ERROR_ABORT_PROFILE_LIST_FULL (9) -#define SL_WLAN_PROVISIONING_ERROR_ABORT_PROVISIONING_ALREADY_STARTED (10) -#define SL_WLAN_PROVISIONING_AUTO_STARTED (11) -#define SL_WLAN_PROVISIONING_STOPPED (12) -#define SL_WLAN_PROVISIONING_SMART_CONFIG_SYNCED (13) -#define SL_WLAN_PROVISIONING_SMART_CONFIG_SYNC_TIMEOUT (14) -#define SL_WLAN_PROVISIONING_CONFIRMATION_WLAN_CONNECT (15) -#define SL_WLAN_PROVISIONING_CONFIRMATION_IP_ACQUIRED (16) -#define SL_WLAN_PROVISIONING_EXTERNAL_CONFIGURATION_READY (17) - -#define SL_WLAN_SEC_TYPE_OPEN (0) -#define SL_WLAN_SEC_TYPE_WEP (1) -#define SL_WLAN_SEC_TYPE_WPA (2) /* deprecated */ -#define SL_WLAN_SEC_TYPE_WPA_WPA2 (2) -#define SL_WLAN_SEC_TYPE_WPS_PBC (3) -#define SL_WLAN_SEC_TYPE_WPS_PIN (4) -#define SL_WLAN_SEC_TYPE_WPA_ENT (5) -#define SL_WLAN_SEC_TYPE_P2P_PBC (6) -#define SL_WLAN_SEC_TYPE_P2P_PIN_KEYPAD (7) -#define SL_WLAN_SEC_TYPE_P2P_PIN_DISPLAY (8) -#define SL_WLAN_SEC_TYPE_P2P_PIN_AUTO (9) /* NOT Supported yet */ -#define SL_WLAN_SEC_TYPE_WEP_SHARED (10) - -#define SL_TLS (0x1) -#define SL_MSCHAP (0x0) -#define SL_PSK (0x2) -#define SL_TTLS (0x10) -#define SL_PEAP0 (0x20) -#define SL_PEAP1 (0x40) -#define SL_FAST (0x80) - -#define SL_WLAN_FAST_AUTH_PROVISIONING (0x02) -#define SL_WLAN_FAST_UNAUTH_PROVISIONING (0x01) -#define SL_WLAN_FAST_NO_PROVISIONING (0x00) - -#define SL_WLAN_PROVISIONING_CMD_START_MODE_AP (0) -#define SL_WLAN_PROVISIONING_CMD_START_MODE_SC (1) -#define SL_WLAN_PROVISIONING_CMD_START_MODE_APSC (2) -#define SL_WLAN_PROVISIONING_CMD_START_MODE_APSC_EXTERNAL_CONFIGURATION (3) -#define SL_WLAN_PROVISIONING_CMD_STOP (4) -#define SL_WLAN_PROVISIONING_CMD_ABORT_EXTERNAL_CONFIRMATION (5) - -/* Provisioning API Flags */ -#define SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION (0x00000001) - -/* to be used only in provisioning stop command */ -#define SL_WLAN_PROVISIONING_REMAIN_IN_CURRENT_ROLE (0xFF) - - -#define SL_WLAN_EAPMETHOD_PHASE2_SHIFT (8) -#define SL_WLAN_EAPMETHOD_PAIRWISE_CIPHER_SHIFT (19) -#define SL_WLAN_EAPMETHOD_GROUP_CIPHER_SHIFT (27) - -#define SL_WLAN_WPA_CIPHER_CCMP (0x1) -#define SL_WLAN_WPA_CIPHER_TKIP (0x2) -#define SL_WLAN_CC31XX_DEFAULT_CIPHER (SL_WLAN_WPA_CIPHER_CCMP | SL_WLAN_WPA_CIPHER_TKIP) - -#define SL_WLAN_EAPMETHOD(phase1,phase2,pairwise_cipher,group_cipher) \ - ((phase1) | \ - ((phase2) << SL_WLAN_EAPMETHOD_PHASE2_SHIFT ) |\ - ((_u32)(pairwise_cipher) << SL_WLAN_EAPMETHOD_PAIRWISE_CIPHER_SHIFT ) |\ - ((_u32)(group_cipher) << SL_WLAN_EAPMETHOD_GROUP_CIPHER_SHIFT )) - -/* phase1 phase2 pairwise_cipher group_cipher */ -#define SL_WLAN_ENT_EAP_METHOD_TLS SL_WLAN_EAPMETHOD(SL_TLS, 0, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_TTLS_TLS SL_WLAN_EAPMETHOD(SL_TTLS, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_TTLS_MSCHAPv2 SL_WLAN_EAPMETHOD(SL_TTLS, SL_MSCHAP, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_TTLS_PSK SL_WLAN_EAPMETHOD(SL_TTLS, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP0_TLS SL_WLAN_EAPMETHOD(SL_PEAP0, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP0_MSCHAPv2 SL_WLAN_EAPMETHOD(SL_PEAP0, SL_MSCHAP, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP0_PSK SL_WLAN_EAPMETHOD(SL_PEAP0, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP1_TLS SL_WLAN_EAPMETHOD(SL_PEAP1, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP1_PSK SL_WLAN_EAPMETHOD(SL_PEAP1, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_FAST_AUTH_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_AUTH_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_FAST_UNAUTH_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_UNAUTH_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_FAST_NO_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_NO_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) - -#define SL_WLAN_LONG_PREAMBLE (0) -#define SL_WLAN_SHORT_PREAMBLE (1) - -#define SL_WLAN_RAW_RF_TX_PARAMS_CHANNEL_SHIFT (0) -#define SL_WLAN_RAW_RF_TX_PARAMS_RATE_SHIFT (6) -#define SL_WLAN_RAW_RF_TX_PARAMS_POWER_SHIFT (11) -#define SL_WLAN_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT (15) - -#define SL_WLAN_RAW_RF_TX_PARAMS(chan,rate,power,preamble) \ - ((chan << SL_WLAN_RAW_RF_TX_PARAMS_CHANNEL_SHIFT) | \ - (rate << SL_WLAN_RAW_RF_TX_PARAMS_RATE_SHIFT) | \ - (power << SL_WLAN_RAW_RF_TX_PARAMS_POWER_SHIFT) | \ - (preamble << SL_WLAN_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT)) - - -/* wlan config application IDs */ -#define SL_WLAN_CFG_AP_ID (0) -#define SL_WLAN_CFG_GENERAL_PARAM_ID (1) -#define SL_WLAN_CFG_P2P_PARAM_ID (2) -#define SL_WLAN_CFG_AP_ACCESS_LIST_ID (3) -#define SL_WLAN_RX_FILTERS_ID (4) -#define SL_WLAN_CONNECTION_INFO (5) - -/* wlan AP Config set/get options */ -#define SL_WLAN_AP_OPT_SSID (0) -#define SL_WLAN_AP_OPT_CHANNEL (3) -#define SL_WLAN_AP_OPT_HIDDEN_SSID (4) -#define SL_WLAN_AP_OPT_SECURITY_TYPE (6) -#define SL_WLAN_AP_OPT_PASSWORD (7) -#define SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE (9) -#define SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER (10) -#define SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER (11) - - - -#define SL_WLAN_P2P_OPT_DEV_NAME (12) -#define SL_WLAN_P2P_OPT_DEV_TYPE (13) -#define SL_WLAN_P2P_OPT_CHANNEL_N_REGS (14) -#define SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT (16) -#define SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS (18) /* change the scan channels and RSSI threshold using this configuration option */ -#define SL_WLAN_AP_OPT_MAX_STATIONS (19) -#define SL_WLAN_AP_ACCESS_LIST_ADD_MAC (20) -#define SL_WLAN_AP_ACCESS_LIST_DEL_MAC (21) -#define SL_WLAN_AP_ACCESS_LIST_DEL_IDX (22) -#define SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES (24) -#define SL_WLAN_AP_ACCESS_LIST_MODE (25) -#define SL_WLAN_AP_OPT_MAX_STA_AGING (26) - -#define SL_WLAN_RX_FILTER_STATE (27) -#define SL_WLAN_RX_FILTER_REMOVE (28) -#define SL_WLAN_RX_FILTER_STORE (29) -#define SL_WLAN_RX_FILTER_UPDATE_ARGS (30) -#define SL_WLAN_RX_FILTER_SYS_STATE (31) -#define SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH (32) -#define SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES (33) - - - -/* SmartConfig CIPHER options */ -#define SL_WLAN_SMART_CONFIG_CIPHER_SFLASH (0) /* password is not delivered by the application. The Simple Manager should - check if the keys are stored in the Flash. */ -#define SL_WLAN_SMART_CONFIG_CIPHER_AES (1) /* AES (other types are not supported) */ -#define SL_WLAN_SMART_CONFIG_CIPHER_NONE (0xFF) /* do not check in the flash */ - - -#define SL_WLAN_POLICY_CONNECTION (0x10) -#define SL_WLAN_POLICY_SCAN (0x20) -#define SL_WLAN_POLICY_PM (0x30) -#define SL_WLAN_POLICY_P2P (0x40) - -#define SL_WLAN_VAL_2_MASK(position,value) ((1 & (value))<<(position)) -#define SL_WLAN_MASK_2_VAL(position,mask) (((1 << position) & (mask)) >> (position)) - -#define SL_WLAN_CONNECTION_POLICY(Auto,Fast,anyP2P,autoProvisioning) (SL_WLAN_VAL_2_MASK(0,Auto) | SL_WLAN_VAL_2_MASK(1,Fast) | SL_WLAN_VAL_2_MASK(2,0) | SL_WLAN_VAL_2_MASK(3,anyP2P) | SL_WLAN_VAL_2_MASK(4,0) | SL_WLAN_VAL_2_MASK(5,autoProvisioning)) -#define SL_WLAN_SCAN_POLICY_EN(policy) (SL_WLAN_MASK_2_VAL(0,policy)) -#define SL_WLAN_SCAN_POLICY(Enable,Enable_Hidden) (SL_WLAN_VAL_2_MASK(0,Enable) | SL_WLAN_VAL_2_MASK(1,Enable_Hidden)) - - -#define SL_WLAN_ENABLE_SCAN (1) -#define SL_WLAN_DISABLE_SCAN (0) -#define SL_WLAN_ALLOW_HIDDEN_SSID_RESULTS (1) -#define SL_WLAN_BLOCK_HIDDEN_SSID_RESULTS (0) - -#define SL_WLAN_NORMAL_POLICY (0) -#define SL_WLAN_LOW_LATENCY_POLICY (1) -#define SL_WLAN_LOW_POWER_POLICY (2) -#define SL_WLAN_ALWAYS_ON_POLICY (3) -#define SL_WLAN_LONG_SLEEP_INTERVAL_POLICY (4) - -#define SL_WLAN_P2P_ROLE_NEGOTIATE (3) -#define SL_WLAN_P2P_ROLE_GROUP_OWNER (15) -#define SL_WLAN_P2P_ROLE_CLIENT (0) - -#define SL_WLAN_P2P_NEG_INITIATOR_ACTIVE (0) -#define SL_WLAN_P2P_NEG_INITIATOR_PASSIVE (1) -#define SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF (2) - -#define SL_WLAN_POLICY_VAL_2_OPTIONS(position,mask,policy) ((mask & policy) << position ) - -#define SL_WLAN_P2P_POLICY(p2pNegType,p2pNegInitiator) (SL_WLAN_POLICY_VAL_2_OPTIONS(0,0xF,(p2pNegType > SL_WLAN_P2P_ROLE_GROUP_OWNER ? SL_WLAN_P2P_ROLE_GROUP_OWNER : p2pNegType)) | \ - SL_WLAN_POLICY_VAL_2_OPTIONS(4,0x1,(p2pNegType > SL_WLAN_P2P_ROLE_GROUP_OWNER ? 1:0)) | \ - SL_WLAN_POLICY_VAL_2_OPTIONS(5,0x3, p2pNegInitiator)) - - -/* Info elements */ -#define SL_WLAN_INFO_ELEMENT_DEFAULT_ID (0) /* 221 will be used */ - -/* info element size is up to 252 bytes (+ 3 bytes of OUI). */ -#define SL_WLAN_INFO_ELEMENT_MAX_SIZE (252) - -/* For AP - the total length of all info elements is 300 bytes (for example - 4 info elements of 75 bytes each) */ -#define SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_AP (300) - -/* For P2P - the total length of all info elements is 160 bytes (for example - 4 info elements of 40 bytes each) */ -#define SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_P2P_GO (160) - -#define SL_WLAN_INFO_ELEMENT_AP_ROLE (0) -#define SL_WLAN_INFO_ELEMENT_P2P_GO_ROLE (1) - -/* we support up to 4 info elements per Role. */ -#define SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED (4) - -#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_0 (0x08) -#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_1 (0x00) -#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_2 (0x28) - -#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI (0x000000) /* 08, 00, 28 will be used */ - -#define SL_WLAN_AP_ACCESS_LIST_MODE_DISABLED 0 -#define SL_WLAN_AP_ACCESS_LIST_MODE_DENY_LIST 1 -#define SL_WLAN_MAX_ACCESS_LIST_STATIONS 8 - - -/* Scan results security information */ -#define SL_WLAN_SCAN_RESULT_GROUP_CIPHER(SecurityInfo) (SecurityInfo & 0xF) /* Possible values: NONE,SL_WLAN_CIPHER_BITMAP_TKIP,SL_WLAN_CIPHER_BITMAP_CCMP */ -#define SL_WLAN_SCAN_RESULT_UNICAST_CIPHER_BITMAP(SecurityInfo) ((SecurityInfo & 0xF0) >> 4 ) /* Possible values: NONE,SL_WLAN_CIPHER_BITMAP_WEP40,SL_WLAN_CIPHER_BITMAP_WEP104,SL_WLAN_CIPHER_BITMAP_TKIP,SL_WLAN_CIPHER_BITMAP_CCMP*/ -#define SL_WLAN_SCAN_RESULT_HIDDEN_SSID(SecurityInfo) (SecurityInfo & 0x2000 ) >> 13 /* Possible values: TRUE/FALSE */ -#define SL_WLAN_SCAN_RESULT_KEY_MGMT_SUITES_BITMAP(SecurityInfo) (SecurityInfo & 0x1800 ) >> 11 /* Possible values: SL_WLAN_KEY_MGMT_SUITE_802_1_X, SL_WLAN_KEY_MGMT_SUITE_PSK */ -#define SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(SecurityInfo) (SecurityInfo & 0x700 ) >> 8 /* Possible values: SL_WLAN_SECURITY_TYPE_BITMAP_OPEN, SL_WLAN_SECURITY_TYPE_BITMAP_WEP, SL_WLAN_SECURITY_TYPE_BITMAP_WPA, SL_WLAN_SECURITY_TYPE_BITMAP_WPA2, 0x6 (mix mode) SL_WLAN_SECURITY_TYPE_BITMAP_WPA | SL_WLAN_SECURITY_TYPE_BITMAP_WPA2 */ - -#define SL_WLAN_SECURITY_TYPE_BITMAP_OPEN 0x0 -#define SL_WLAN_SECURITY_TYPE_BITMAP_WEP 0x1 -#define SL_WLAN_SECURITY_TYPE_BITMAP_WPA 0x2 -#define SL_WLAN_SECURITY_TYPE_BITMAP_WPA2 0x4 - -#define SL_WLAN_CIPHER_BITMAP_WEP40 0x1 -#define SL_WLAN_CIPHER_BITMAP_WEP104 0x2 -#define SL_WLAN_CIPHER_BITMAP_TKIP 0x4 -#define SL_WLAN_CIPHER_BITMAP_CCMP 0x8 - -#define SL_WLAN_KEY_MGMT_SUITE_802_1_X 1 -#define SL_WLAN_KEY_MGMT_SUITE_PSK 2 - - - -#define SL_WLAN_RX_FILTER_MAX_FILTERS (64) /* Max number of filters is 64 filters */ -#define SL_WLAN_RX_FILTER_MAX_SYS_FILTERS_SETS (32) /* The Max number of system filters */ -#define SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS (2) -#define SL_WLAN_RX_FILTER_NUM_OF_FILTER_PAYLOAD_ARGS (2) -#define SL_WLAN_RX_FILTER_RANGE_ARGS (2) -#define SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID (64) -#define SL_WLAN_RX_FILTER_MAX_USER_EVENT_ID ( ( SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID ) - 1 ) - -/* Bit manipulation for 8 bit */ -#define SL_WLAN_ISBITSET8(x,i) ((x[i>>3] & (0x80>>(i&7)))!=0) /* Is bit set, 8 bit unsigned numbers = x , location = i */ -#define SL_WLAN_SETBIT8(x,i) x[i>>3]|=(0x80>>(i&7)); /* Set bit,8 bit unsigned numbers = x , location = i */ -#define SL_WLAN_CLEARBIT8(x,i) x[i>>3]&=(0x80>>(i&7))^0xFF; /* Clear bit,8 bit unsigned numbers = x , location = i */ - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef enum -{ - SL_WLAN_RATE_1M = 1, - SL_WLAN_RATE_2M = 2, - SL_WLAN_RATE_5_5M = 3, - SL_WLAN_RATE_11M = 4, - SL_WLAN_RATE_6M = 6, - SL_WLAN_RATE_9M = 7, - SL_WLAN_RATE_12M = 8, - SL_WLAN_RATE_18M = 9, - SL_WLAN_RATE_24M = 10, - SL_WLAN_RATE_36M = 11, - SL_WLAN_RATE_48M = 12, - SL_WLAN_RATE_54M = 13, - SL_WLAN_RATE_MCS_0 = 14, - SL_WLAN_RATE_MCS_1 = 15, - SL_WLAN_RATE_MCS_2 = 16, - SL_WLAN_RATE_MCS_3 = 17, - SL_WLAN_RATE_MCS_4 = 18, - SL_WLAN_RATE_MCS_5 = 19, - SL_WLAN_RATE_MCS_6 = 20, - SL_WLAN_RATE_MCS_7 = 21, - SL_WLAN_MAX_NUM_RATES = 0xFF -}SlWlanRateIndex_e; - -typedef enum -{ - SL_WLAN_DEV_PW_DEFAULT = 0, - SL_WLAN_DEV_PW_PIN_KEYPAD = 1, - SL_WLAN_DEV_PW_PUSH_BUTTON = 4, - SL_WLAN_DEV_PW_PIN_DISPLAY = 5 -} SlWlanP2pDevPwdMethod_e; - -typedef struct -{ - _u32 Status; - _u32 SsidLen; - _u8 Ssid[32]; - _u32 PrivateTokenLen; - _u8 PrivateToken[32]; -}SlWlanSmartConfigStartAsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u16 Padding; -}SlWlanSmartConfigStopAsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u16 Padding; -}SlWlanConnFailureAsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u16 Padding; -}SlWlanProvisioningStatusAsyncResponse_t; - -/* rx filter event struct - this event will be sent from the SL device - as a result of a passed rx filter - example: - suppose we have a filter with an action and we set the following: - SlWlanRxFilterAction_t Action; - Action.UserId = 2; - When the filter result is pass, an SlWlanEventRxFilterInfo_t event will be passed to the user as follows: - Type will be set to 0 - bit 2 in UserActionIdBitmap will be set in this event, because 2 is the user input for the action arg above. - an SlWlanEventRxFilterInfo_t event may have several bits set as a result of several rx filters causing different - events to pass */ - -typedef struct -{ - _u8 Type; /* Currently only event type 0 is supported. */ - _u8 UserActionIdBitmap[SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID / 8]; /* Bit X is set indicates that the filter with event action arg X passed. */ -}SlWlanEventRxFilterInfo_t; - -typedef enum -{ - ROLE_STA = 0, - ROLE_RESERVED = 1, - ROLE_AP = 2, - ROLE_P2P = 3, - ROLE_RESERVED2 = 4 -}SlWlanMode_e; - -typedef struct -{ - _u8 SsidLen; - _u8 SsidName[32]; - _u8 Bssid[6]; - _u8 Padding; -} SlWlanEventConnect_t; - -typedef struct -{ - _u8 SsidLen; - _u8 SsidName[32]; - _u8 Bssid[6]; - _u8 ReasonCode; -} SlWlanEventDisconnect_t; - -typedef struct -{ - _u8 Mac[6]; - _u8 Padding[2]; -}SlWlanEventSTAAdded_t, SlWlanEventSTARemoved_t; - - -typedef struct -{ - _u8 SsidLen; - _u8 SsidName[32]; - _u8 Bssid[6]; - _u8 Reserved; - _u8 GoDeviceNameLen; - _u8 GoDeviceName[32]; - _u8 Padding[3]; -} SlWlanEventP2PConnect_t; - -typedef struct -{ - _u8 SsidLen; - _u8 SsidName[32]; - _u8 Bssid[6]; - _u8 ReasonCode; - _u8 GoDeviceNameLen; - _u8 GoDeviceName[32]; - _u8 Padding[3]; -} SlWlanEventP2PDisconnect_t; - -typedef struct -{ - _u8 Mac[6]; - _u8 ClDeviceNameLen; - _u8 ClDeviceName[32]; - _u8 OwnSsidLen; - _u8 OwnSsid[32]; -}SlWlanEventP2PClientAdded_t, SlWlanEventP2PClientRemoved_t; - -typedef struct -{ - _u8 GoDeviceNameLen; - _u8 GoDeviceName[32]; - _u8 Mac[6]; - _u8 WpsMethod; -}SlWlanEventP2PDevFound_t, SlWlanEventP2PRequest_t; - -/**************************************************/ -typedef struct -{ - _u16 Status; - _u16 Padding; -}SlWlanEventP2PConnectFail_t; - -typedef struct -{ - _u8 ProvisioningStatus; - _u8 Role; - _u8 WlanStatus; - _u8 Ssidlen; - _u8 Ssid[32]; - _u32 Reserved; -}SlWlanEventProvisioningStatus_t; - -typedef struct -{ - _u32 Status; - _u32 SsidLen; - _u8 Ssid[32]; - _u32 ReservedLen; - _u8 Reserved[32]; -} SlWlanEventProvisioningProfileAdded_t; - -typedef union -{ - SlWlanEventConnect_t Connect; /* SL_WLAN_EVENT_CONNECT */ - SlWlanEventDisconnect_t Disconnect; /* SL_WLAN_EVENT_DISCONNECT */ - SlWlanEventSTAAdded_t STAAdded; /* SL_WLAN_EVENT_STA_ADDED */ - SlWlanEventSTARemoved_t STARemoved; /* SL_WLAN_EVENT_STA_REMOVED */ - SlWlanEventP2PConnect_t P2PConnect; /* SL_WLAN_EVENT_P2P_CONNECT */ - SlWlanEventP2PDisconnect_t P2PDisconnect; /* SL_WLAN_EVENT_P2P_DISCONNECT */ - SlWlanEventP2PClientAdded_t P2PClientAdded; /* SL_WLAN_EVENT_P2P_CLIENT_ADDED */ - SlWlanEventP2PClientRemoved_t P2PClientRemoved; /* SL_WLAN_EVENT_P2P_CLIENT_REMOVED */ - SlWlanEventP2PDevFound_t P2PDevFound; /* SL_WLAN_EVENT_P2P_DEVFOUND */ - SlWlanEventP2PRequest_t P2PRequest; /* SL_WLAN_EVENT_P2P_REQUEST */ - SlWlanEventP2PConnectFail_t P2PConnectFail; /* SL_WLAN_EVENT_P2P_CONNECTFAIL */ - SlWlanEventRxFilterInfo_t RxFilterInfo; /* SL_WLAN_EVENT_RXFILTER */ - SlWlanEventProvisioningStatus_t ProvisioningStatus; /* SL_WLAN_EVENT_PROVISIONING_STATUS */ - SlWlanEventProvisioningProfileAdded_t ProvisioningProfileAdded; /* SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED */ - -} SlWlanEventData_u; - -typedef struct -{ - _u32 Id; - SlWlanEventData_u Data; -} SlWlanEvent_t; - -typedef struct -{ - _u32 ReceivedValidPacketsNumber; /* sum of the packets that been received OK (include filtered) */ - _u32 ReceivedFcsErrorPacketsNumber; /* sum of the packets that been dropped due to FCS error */ - _u32 ReceivedAddressMismatchPacketsNumber; /* sum of the packets that been received but filtered out by one of the HW filters */ - _i16 AvarageDataCtrlRssi; /* average RSSI for all valid data packets received */ - _i16 AvarageMgMntRssi; /* average RSSI for all valid management packets received */ - _u16 RateHistogram[SL_WLAN_NUM_OF_RATE_INDEXES]; /* rate histogram for all valid packets received */ - _u16 RssiHistogram[SL_WLAN_SIZE_OF_RSSI_HISTOGRAM]; /* RSSI histogram from -40 until -87 (all below and above\n RSSI will appear in the first and last cells */ - _u32 StartTimeStamp; /* the time stamp started collecting the statistics in uSec */ - _u32 GetTimeStamp; /* the time stamp called the get statistics command */ -}SlWlanGetRxStatResponse_t; - -typedef struct -{ - _u8 Ssid[SL_WLAN_SSID_MAX_LENGTH]; - _u8 Bssid[SL_WLAN_BSSID_LENGTH]; - _u8 SsidLen; - _i8 Rssi; - _i16 SecurityInfo; - _u8 Channel; - _i8 Reserved[1]; -}SlWlanNetworkEntry_t; - -typedef struct -{ - _u8 Ssid[SL_WLAN_SSID_MAX_LENGTH]; - _u8 Bssid[SL_WLAN_BSSID_LENGTH]; - _u8 SsidLen; - _i8 Rssi; - _i16 SecurityInfo; - _u8 Channel; - _i8 Reserved[1]; - /* country info extended area */ - _u8 CountryStr[2]; - _u16 Supported_2_4G_Channels; - _u32 Supported_5_0G_Channels; -}SlWlanExtNetworkEntry_t; - -typedef struct -{ - _u8 Type; - _i8* Key; - _u8 KeyLen; -}SlWlanSecParams_t; - -typedef struct -{ - _i8* User; - _u8 UserLen; - _i8* AnonUser; - _u8 AnonUserLen; - _u8 CertIndex; /* not supported */ - _u32 EapMethod; -}SlWlanSecParamsExt_t; - -typedef struct -{ - _i8 User[64]; - _u8 UserLen; - _i8 AnonUser[64]; - _u8 AnonUserLen; - _u8 CertIndex; /* not supported */ - _u32 EapMethod; -}SlWlanGetSecParamsExt_t; - -#define SL_WLAN_CONNECTION_PROTOCOL_STA 1 -#define SL_WLAN_CONNECTION_PROTOCOL_P2PCL 2 - -typedef union -{ - SlWlanEventConnect_t StaConnect; - SlWlanEventP2PConnect_t P2PConnect; -} SlWlanConnectionInfo_u; - -typedef enum -{ - SL_WLAN_DISCONNECTED = 0, - SL_WLAN_CONNECTED_STA, - SL_WLAN_CONNECTED_P2PCL, - SL_WLAN_CONNECTED_P2PGO, - SL_WLAN_AP_CONNECTED_STATIONS -}SlWlanConnStatusFlags_e; - -typedef struct -{ - _u8 Mode; /* ROLE_STA, ROLE_AP, ROLE_P2P */ - _u8 ConnStatus; /* SlWlanConnStatusFlags_e */ - _u8 SecType; /* Current connection security type - (0 in case of disconnect or AP mode) SL_WLAN_SEC_TYPE_OPEN, SL_WLAN_SEC_TYPE_WEP, SL_WLAN_SEC_TYPE_WPA_WPA2, SL_WLAN_SEC_TYPE_WPA_ENT, SL_WLAN_SEC_TYPE_WPS_PBC, SL_WLAN_SEC_TYPE_WPS_PIN */ - _u8 Reserved; - SlWlanConnectionInfo_u ConnectionInfo; -}SlWlanConnStatusParam_t; - -typedef struct -{ - _u32 ChannelsMask; - _i32 RssiThreshold; -}SlWlanScanParamCommand_t; - -typedef struct -{ - _u8 Id; - _u8 Oui[3]; - _u16 Length; - _u8 Data[252]; -} SlWlanInfoElement_t; - -typedef struct -{ - _u8 Index; /* 0 - SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED */ - _u8 Role; /* bit0: AP = 0, GO = 1 */ - SlWlanInfoElement_t IE; -} SlWlanSetInfoElement_t; - -typedef struct -{ - _u16 Reserved; - _u16 Reserved2; - _u16 MaxSleepTimeMs; /* max sleep time in mSec For setting Long Sleep Interval policy use */ - _u16 Reserved3; -} SlWlanPmPolicyParams_t; - -typedef _i8 SlWlanRxFilterID_t; /* Unique filter ID which is allocated by the system , negative number means error */ - -/* Representation of filters Id as a bit field - The bit field is used to declare which filters are involved - in operation. Number of filter can be up to 128 filters. - i.e. 128 bits are needed. On the current release, up to 64 filters can be defined. */ -typedef _u8 SlWlanRxFilterIdMask_t[128/8]; - -typedef _u8 SlWlanRxFilterSysFilters_t; /* Describes the supported system filter sets*/ -/* possible values for SlWlanRxFilterSysFilters_t */ -#define SL_WLAN_RX_FILTER_ARP_AUTO_REPLY_SYS_FILTERS (0) -#define SL_WLAN_RX_FILTER_MULTICASTSIPV4_SYS_FILTERS (1) -#define SL_WLAN_RX_FILTER_MULTICASTSIPV6_SYS_FILTERS (2) -#define SL_WLAN_RX_FILTER_MULTICASTSWIFI_SYS_FILTERS (3) -#define SL_WLAN_RX_FILTER_SELF_MAC_ADDR_DROP_SYS_FILTERS (4) - -/* Describes the supported system filter sets, each bit represents different system filter set - The filter sets are defined at SlWlanRxFilterSysFilters_t */ -typedef _u8 SlWlanRxFilterSysFiltersMask_t[SL_WLAN_RX_FILTER_MAX_SYS_FILTERS_SETS/8]; - -typedef struct -{ - _u16 Offset; /* Offset in payload - Where in the payload to search for the pattern */ - _u8 Length; /* Pattern Length */ - _u8 Reserved; - _u8 Value[16]; /* Up to 16 bytes long (based on pattern length above) */ -}SlWlanRxFilterPatternArg_t; - -typedef _u8 SlWlanRxFilterRuleType_t; /* Different filter types */ -/* possible values for SlWlanRxFilterRuleType_t */ -#define SL_WLAN_RX_FILTER_HEADER (0) -#define SL_WLAN_RX_FILTER_COMBINATION (1) - -typedef _u8 SlWlanRxFilterFlags_u; -/* Possible values for SlWlanRxFilterFlags_u */ -#define SL_WLAN_RX_FILTER_BINARY (0x1) -#define SL_WLAN_RX_FILTER_PERSISTENT (0x8) -#define SL_WLAN_RX_FILTER_ENABLE (0x10) - -/* Used as comparison function for the header type arguments */ -typedef _u8 SlWlanRxFilterRuleHeaderCompareFunction_t; -/* Possible values for SlWlanRxFilterRuleHeaderCompareFunction_t */ -#define SL_WLAN_RX_FILTER_CMP_FUNC_IN_BETWEEN (0) -#define SL_WLAN_RX_FILTER_CMP_FUNC_EQUAL (1) -#define SL_WLAN_RX_FILTER_CMP_FUNC_NOT_EQUAL_TO (2) -#define SL_WLAN_RX_FILTER_CMP_FUNC_NOT_IN_BETWEEN (3) - -typedef _u8 SlWlanRxFilterTriggerCompareFunction_t; -/* Possible values for SlWlanRxFilterTriggerCompareFunction_t */ -#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_EQUAL (0) -#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_NOT_EQUAL_TO (1) /* arg1 == protocolVal ,not supported in current release */ -#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_SMALLER_THAN (2) /* arg1 == protocolVal */ -#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_BIGGER_THAN (3) /* arg1 == protocolVal */ - -typedef _u8 SlWlanRxFilterRuleHeaderField_t; /* Provides list of possible header types which may be defined as part of the rule */ -/* Possible values for SlWlanRxFilterRuleHeaderField_t */ -#define SL_WLAN_RX_FILTER_HFIELD_NULL (0) -#define SL_WLAN_RX_FILTER_HFIELD_FRAME_TYPE (1) /* 802.11 control\data\management */ -#define SL_WLAN_RX_FILTER_HFIELD_FRAME_SUBTYPE (2) /* 802.11 beacon\probe\.. */ -#define SL_WLAN_RX_FILTER_HFIELD_BSSID (3) /* 802.11 bssid type */ -#define SL_WLAN_RX_FILTER_HFIELD_MAC_SRC_ADDR (4) -#define SL_WLAN_RX_FILTER_HFIELD_MAC_DST_ADDR (5) -#define SL_WLAN_RX_FILTER_HFIELD_FRAME_LENGTH (6) -#define SL_WLAN_RX_FILTER_HFIELD_ETHER_TYPE (7) -#define SL_WLAN_RX_FILTER_HFIELD_IP_VERSION (8) -#define SL_WLAN_RX_FILTER_HFIELD_IP_PROTOCOL (9) /* TCP / UDP / ICMP / ICMPv6 / IGMP */ -#define SL_WLAN_RX_FILTER_HFIELD_IPV4_SRC_ADDR (10) -#define SL_WLAN_RX_FILTER_HFIELD_IPV4_DST_ADDR (11) -#define SL_WLAN_RX_FILTER_HFIELD_IPV6_SRC_ADRR (12) -#define SL_WLAN_RX_FILTER_HFIELD_IPV6_DST_ADDR (13) -#define SL_WLAN_RX_FILTER_HFIELD_PORT_SRC (14) -#define SL_WLAN_RX_FILTER_HFIELD_PORT_DST (15) -#define SL_WLAN_RX_FILTER_HFIELD_L4_PAYLOAD_PATTERN (19) /* use to look for patterns on the TCP and UDP payloads (after TCP/UDP header) */ -#define SL_WLAN_RX_FILTER_HFIELD_L1_PAYLOAD_PATTERN (20) /* use to look for patterns on the PHY payload (i.e. beginning of WLAN MAC header) */ -#define SL_WLAN_RX_FILTER_HFIELD_MAX_FIELD (21) /* Definition */ - -/* Holds the header ARGS which are used in case of HDR rule */ -typedef union -{ - /* buffer for pattern matching in payload up to 16 bytes (Binary Values) */ - SlWlanRxFilterPatternArg_t Pattern; - - /* Buffer for ipv4 address filter. binary arguments, number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Ipv4[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][4]; /* Binary Values for comparison */ - - /* Buffer for ipv4 address filter. Ascii arguments - IPv4 address: 4 bytes: ddd.ddd.ddd.ddd - 15 chars. Number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Ipv4Ascii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][16]; /* Ascii Values for comparison */ - - /* Buffer for ipv6 address filter. binary arguments, Ascii format is not supported. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Ipv6[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][16]; /* Binary Values for comparison */ - - /* Buffer for mac address filter. binary arguments. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Mac[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][6]; /* Binary Values for comparison */ - - /* Buffer for mac address filter. Ascii arguments - MAC address: 6 bytes: xx:xx:xx:xx:xx:xx - 17 chars. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ - _u8 MacAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][18]; /* Ascii Values for comparison */ - - /* Buffer for BSSID address filter. binary arguments. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Bssid[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][6]; /* Binary Values for comparison */ - - /* Buffer for frame length filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ - _u32 FrameLength[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ - - /* Buffer for port filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ - _u32 Port[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ - - /* Buffer for Ether filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS (according to host endianity) */ - _u32 EtherType[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ - - /* Buffer for ip version filter. Buffer for binary arguments. IP Version - 4 for IPV4 and 6 for IPV6 */ - _u8 IpVersion; - - /* Buffer for frame type filter. Buffer for binary arguments. Frame Type (0 - management, 1 - Control, 2 - Data) */ - _u8 Frametype[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; - - /* Buffer for frame subtype filter. Buffer for binary arguments. Frame Sub Type (checkout the full list in the 802.11 spec). e.g. Beacon=0x80, Data=0x08, Qos-Data=0x04, ACK=0xD4, etc. */ - _u8 FrameSubtype[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; - - /* Buffer for protocol type filter. Buffer for binary arguments. e.g. 1 � ICMP (IPV4 only), 2 - IGMP (IPV4 only), 6 � TCP. 17 � UDP, 58 � ICMPV6 */ - _u8 IpProtocol[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; - - /* Buffer for ip version filter. Buffer for ASCII arguments. Use for IP version field comparison settings: "IPV4", "IPV6" */ - _u8 IpVersionAscii[4]; - - /* Buffer for frame type filter. Buffer for ASCII arguments. Use for Frame type field comparison settings: "MGMT", "CTRL", "DATA" */ - _u8 FrametypeAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][4]; - - /* Buffer for protocol type filter. Buffer for ASCII arguments. Use for protocol field comparison settings: "ICMP", "IGMP", "TCP, "UDP", "ICMP6" */ - /* Note: Use memcpy with these strings instead of strcpy (no \0 should be at the end, as the array is 5 bytes long and ICMP6 is already 5 bytes long without the \0) */ - _u8 IpProtocolAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][5]; - -}SlWlanRxFilterHeaderArg_u; - -/* Defines the Header Args and mask */ -typedef struct -{ - SlWlanRxFilterHeaderArg_u Value; /* Argument for the comparison function */ - _u8 Mask[16]; /* the mask is used in order to enable partial comparison (bit level), Use the 0xFFFFFFFF in case you don't want to use mask */ - -}SlWlanRxFilterRuleHeaderArgs_t; - -/* defines the Header rule. The header rule defines the compare function on the protocol header - For example destMacAddre is between ( 12:6::78:77, 12:6::78:90 ) */ -typedef struct -{ - SlWlanRxFilterRuleHeaderArgs_t Args; /* Filter arguments */ - SlWlanRxFilterRuleHeaderField_t Field; /* Packet HDR field which will be compared to the argument */ - SlWlanRxFilterRuleHeaderCompareFunction_t CompareFunc; /* type of the comparison function */ - _u8 Padding[2]; -}SlWlanRxFilterRuleHeader_t; - -/* Optional operators for the combination type filterID1 is located in the first arg , filterId2 is the second arg */ -typedef _u8 SlWlanRxFilterRuleCombinationOperator_t; -/* Possible values for SlWlanRxFilterRuleCombinationOperator_t */ -#define SL_WLAN_RX_FILTER_COMBINED_FUNC_NOT (0) /* filterID1 */ -#define SL_WLAN_RX_FILTER_COMBINED_FUNC_AND (1) /* filterID1 && filterID2 */ -#define SL_WLAN_RX_FILTER_COMBINED_FUNC_OR (2) /* filterID1 && filterID2 */ - -/* Defines the structure which define the combination type filter - The combined filter enable to make operation on one or two filter, - for example filterId1 or and(filterId2,filterId3). */ -typedef struct -{ - SlWlanRxFilterRuleCombinationOperator_t Operator; /* combination operator */ - SlWlanRxFilterID_t CombinationFilterId[SL_WLAN_RX_FILTER_RANGE_ARGS]; /* filterID, may be one or two depends on the combination operator type */ - _u8 Padding; -}SlWlanRxFilterRuleCombination_t; - -/* Rule structure composed of behavioral flags and the filter rule definitions */ -typedef union -{ - SlWlanRxFilterRuleHeader_t Header; /* Filter is from type Header */ - SlWlanRxFilterRuleCombination_t Combination; /* Filter is from type Combination */ -}SlWlanRxFilterRule_u; - -/* Bit field which represents the roleId possible values - In the current release only Station (with or without promiscuous modes) and AP roles are supported. - Activating filters before P2P negotiations (i.e. decision whether role is CL or GO) may result with - unexpected behaviour. After this stage, filters can be activated whereas STA role is the equivalent of P2P CL role - AP role is the equivalent of P2P GO role. - */ -typedef _u8 SlWlanRxFilterTriggerRoles_t; -/* Possible values for SlWlanRxFilterTriggerRoles_t */ -#define SL_WLAN_RX_FILTER_ROLE_AP (1) -#define SL_WLAN_RX_FILTER_ROLE_STA (2) -#define SL_WLAN_RX_FILTER_ROLE_TRANCIEVER (4) -#define SL_WLAN_RX_FILTER_ROLE_NULL (0) - -typedef _u8 SlWlanRxFilterTriggerConnectionStates_t; -/* Possible values for SlWlanRxFilterTriggerConnectionStates_t */ -#define SL_WLAN_RX_FILTER_STATE_STA_CONNECTED (0x1) -#define SL_WLAN_RX_FILTER_STATE_STA_NOT_CONNECTED (0x2) -#define SL_WLAN_RX_FILTER_STATE_STA_HAS_IP (0x4) -#define SL_WLAN_RX_FILTER_STATE_STA_HAS_NO_IP (0x8) - -/* There are 8 possible counter. if no counter is needed set to NO_TRIGGER_COUNTER */ -typedef _u8 SlWlanRxFilterCounterId_t; -/* Possible values for SlWlanRxFilterCounterId_t */ -#define SL_WLAN_RX_FILTER_NO_TRIGGER_COUNTER (0) -#define SL_WLAN_RX_FILTER_COUNTER1 (1) -#define SL_WLAN_RX_FILTER_COUNTER2 (2) -#define SL_WLAN_RX_FILTER_COUNTER3 (3) -#define SL_WLAN_RX_FILTER_COUNTER4 (4) -#define SL_WLAN_RX_FILTER_COUNTER5 (5) -#define SL_WLAN_RX_FILTER_COUNTER6 (6) -#define SL_WLAN_RX_FILTER_COUNTER7 (7) -#define SL_WLAN_RX_FILTER_COUNTER8 (8) -#define SL_WLAN_RX_FILTER_MAX_COUNTER (9) - -/* The filter trigger, determine when the filter is triggered, - The filter is triggered in the following condition :\n - 1. The filter parent is triggered\n - 2. The requested connection type exists, i.e. wlan_connect\n - 3. The filter role is the same as the system role\n */ -typedef struct -{ - SlWlanRxFilterID_t ParentFilterID; /* The parent filter ID, this is the way to build filter tree. NULL value means tree root */ - SlWlanRxFilterCounterId_t Counter; /* Trigger only when reach counter threshold */ - SlWlanRxFilterTriggerConnectionStates_t ConnectionState; /* Trigger only with specific connection state */ - SlWlanRxFilterTriggerRoles_t Role; /* Trigger only with specific role */ - _u32 CounterVal; /* Value for the counter if set */ - SlWlanRxFilterTriggerCompareFunction_t CompareFunction; /* The compare function refers to the counter if set */ - _u8 Padding[3]; -} SlWlanRxFilterTrigger_t; - -/* The actions are executed only if the filter is matched,\n - * In case of false match the packet is transferred to the HOST. \n - * The action is composed of bit field structure, up to 2 actions can be defined per filter.\n */ -typedef _u8 SlWlanRxFilterActionType_t; -/* Possible values for SlWlanRxFilterActionType_t */ -#define SL_WLAN_RX_FILTER_ACTION_NULL (0x0) /* No action to execute*/ -#define SL_WLAN_RX_FILTER_ACTION_DROP (0x1) /* If not dropped ,The packet is passed to the next filter or in case it is the last filter to the host */ -#define SL_WLAN_RX_FILTER_ACTION_ON_REG_INCREASE (0x4) /* action increase counter registers */ -#define SL_WLAN_RX_FILTER_ACTION_ON_REG_DECREASE (0x8) /* action decrease counter registers */ -#define SL_WLAN_RX_FILTER_ACTION_ON_REG_RESET (0x10)/* action reset counter registers */ -#define SL_WLAN_RX_FILTER_ACTION_SEND_TEMPLATE (0x20)/* unsupported */ -#define SL_WLAN_RX_FILTER_ACTION_EVENT_TO_HOST (0x40)/* action can send events to host */ - -/* Several actions can be defined The action is executed in case the filter rule is matched. */ -typedef struct -{ - SlWlanRxFilterActionType_t Type; /* Determine which actions are supported */ - _u8 Counter; /* The counter in use. In case the action is of type increase\decrease\reset this arg will contain the counter number, The counter number values are as in ::SlWlanRxFilterCounterId_t.\n*/ - _u16 Reserved; /* Must be set to zero */ - _u8 UserId; /* In case action set to host event, user can set id which will return in the event arguments */ - _u8 Padding[3]; - -} SlWlanRxFilterAction_t; - -/* The supported operation: SL_WLAN_RX_FILTER_STATE, SL_WLAN_RX_FILTER_REMOVE */ -typedef struct -{ - SlWlanRxFilterIdMask_t FilterBitmap; - _u8 Padding[4]; - -} SlWlanRxFilterOperationCommandBuff_t; - -/* The supported operation: SL_WLAN_RX_FILTER_UPDATE_ARGS */ -typedef struct -{ - _u8 FilterId; - _u8 BinaryOrAscii; /* Set 1 for Binary argument representation, 0 - for Ascii representation */ - _u8 Padding[2]; - SlWlanRxFilterRuleHeaderArgs_t Args; - - -} SlWlanRxFilterUpdateArgsCommandBuff_t; - -/* Filters bitmap enable\disable status return value */ -typedef struct -{ - SlWlanRxFilterIdMask_t FilterIdMask; /* The filter set bit map */ - -}SlWlanRxFilterRetrieveStateBuff_t; - -/* Disbale/Enable system filters */ -typedef struct -{ - SlWlanRxFilterSysFiltersMask_t FilterBitmap; /* The filter set bit map */ - -} SlWlanRxFilterSysFiltersSetStateBuff_t; - -/* System filters status return value */ -typedef struct -{ - SlWlanRxFilterSysFiltersMask_t FilterBitmap; /* The filter get bit map */ - -} SlWlanRxFilterSysFiltersRetrieveStateBuff_t; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - - -/*! - \brief Connect to wlan network as a station - - \param[in] pName Up to 32 bytes in case of STA the name is the SSID of the Access Point - \param[in] NameLen Name length - \param[in] pMacAddr 6 bytes for MAC address - \param[in] pSecParams Security parameters (use NULL key for SL_WLAN_SEC_TYPE_OPEN)\n - security types options: - - SL_WLAN_SEC_TYPE_OPEN - - SL_WLAN_SEC_TYPE_WEP - - SL_WLAN_SEC_TYPE_WEP_SHARED - - SL_WLAN_SEC_TYPE_WPA_WPA2 - - SL_WLAN_SEC_TYPE_WPA_ENT - - SL_WLAN_SEC_TYPE_WPS_PBC - - SL_WLAN_SEC_TYPE_WPS_PIN - - \param[in] pSecExtParams Enterprise parameters (set NULL in case Enterprise parameters is not in use) - - \return Zero on success, or negative error code on failure - - - \sa sl_WlanDisconnect - \note Belongs to \ref ext_api - \warning In this version only single enterprise mode could be used\n - SL_WLAN_SEC_TYPE_WPA is a deprecated definition, the new definition is SL_WLAN_SEC_TYPE_WPA_WPA2 - \par Example - - - Connect without security: - \code - SlWlanSecParams_t secParams; - secParams.Key = ""; - secParams.KeyLen = 0; - secParams.Type = SL_WLAN_SEC_TYPE_OPEN; - sl_WlanConnect("ssid_name", strlen("ssid_name"),0,&secParams,0); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanConnect) -_i16 sl_WlanConnect(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams); -#endif - -/*! - \brief Wlan disconnect - - Disconnect connection - - \return Zero disconnected done successfully, other already disconnected - - \sa sl_WlanConnect - \note belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_WlanDisconnect) -_i16 sl_WlanDisconnect(void); -#endif - -/*! - \brief Add profile - - When auto start is enabled, the device connects to a - station from the profiles table. Up to 7 profiles (SL_WLAN_MAX_PROFILES) are - supported.\n If several profiles configured the device chose - the highest priority profile, within each priority group, - device will chose profile based on security policy, signal - strength, etc parameters. - - \param[in] pName Up to 32 bytes in case of STA the name is the - SSID of the Access Point.\n - In case of P2P the name is the remote device name. - \param[in] NameLen Name length - \param[in] pMacAddr 6 bytes for MAC address - \param[in] pSecParams Security parameters (use NULL key for SL_WLAN_SEC_TYPE_OPEN)\n - Security types options: - - SL_WLAN_SEC_TYPE_OPEN - - SL_WLAN_SEC_TYPE_WEP - - SL_WLAN_SEC_TYPE_WEP_SHARED - - SL_WLAN_SEC_TYPE_WPA_WPA2 - - SL_WLAN_SEC_TYPE_WPA_ENT - - SL_WLAN_SEC_TYPE_WPS_PBC - - SL_WLAN_SEC_TYPE_WPS_PIN - - \param[in] pSecExtParams Enterprise parameters - identity, identity length, - Anonymous, Anonymous length, CertIndex (not supported, - certificates need to be placed in a specific file ID), - EapMethod.\n Use NULL in case Enterprise parameters is not in use - - \param[in] Priority Profile priority. Lowest priority: 0, Highest priority: 15. - \param[in] Options Not supported - - \return Profile stored index on success, or negative error code on failure. - \par Persistent - Profiles are Persistent - \sa sl_WlanProfileGet , sl_WlanProfileDel - \note belongs to \ref ext_api - \warning Only one Enterprise profile is supported.\n - Please Note that in case of adding an existing profile (compared by pName,pMACAddr and security type) - the old profile will be deleted and the same index will be returned.\n - SL_WLAN_SEC_TYPE_WPA is a deprecated definition, the new definition is SL_WLAN_SEC_TYPE_WPA_WPA2 - -*/ -#if _SL_INCLUDE_FUNC(sl_WlanProfileAdd) -_i16 sl_WlanProfileAdd(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority,const _u32 Options); -#endif - -/*! - \brief Get profile - - Read profile from the device - - \param[in] Index Profile stored index, if index does not exists error is return - \param[out] pName Up to 32 bytes, in case of sta mode the name of the Access Point\n - In case of p2p mode the name of the Remote Device - \param[out] pNameLen Name length - \param[out] pMacAddr 6 bytes for MAC address - \param[out] pSecParams Security parameters. Security types options: - - SL_WLAN_SEC_TYPE_OPEN - - SL_WLAN_SEC_TYPE_WEP - - SL_WLAN_SEC_TYPE_WEP_SHARED - - SL_WLAN_SEC_TYPE_WPA_WPA2 - - SL_WLAN_SEC_TYPE_WPA_ENT - - SL_WLAN_SEC_TYPE_WPS_PBC - - SL_WLAN_SEC_TYPE_WPS_PIN - Key and key length are not return. In case of p2p security type pin the key refers to pin code - return due to security reasons. - \param[out] pSecExtParams Enterprise parameters - identity, identity - length, Anonymous, Anonymous length - CertIndex (not supported), EapMethod. - \param[out] pPriority Profile priority - - \return Profile security type is returned (0 or positive number) on success, or negative error code on failure - SL_ERROR_WLAN_GET_PROFILE_INVALID_INDEX is return is profile index does not exist - - \sa sl_WlanProfileAdd , sl_WlanProfileDel - \note belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_WlanProfileGet) -_i16 sl_WlanProfileGet(const _i16 Index,_i8* pName, _i16 *pNameLen, _u8 *pMacAddr, SlWlanSecParams_t* pSecParams, SlWlanGetSecParamsExt_t* pSecExtParams, _u32 *pPriority); -#endif - -/*! - \brief Delete WLAN profile - - Delete WLAN profile - - \param[in] Index number of profile to delete. Possible values are 0 to 6.\n - Index value SL_WLAN_DEL_ALL_PROFILES will delete all saved profiles - - \return Zero on success or a negative error code on failure - \par Persistent - Profile deletion is Persistent - \sa sl_WlanProfileAdd , sl_WlanProfileGet - \note belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_WlanProfileDel) -_i16 sl_WlanProfileDel(const _i16 Index); -#endif - -/*! - \brief Set policy values - - \param[in] Type Type of policy to be modified. The Options are: - - SL_WLAN_POLICY_CONNECTION - - SL_WLAN_POLICY_SCAN - - SL_WLAN_POLICY_PM - - SL_WLAN_POLICY_P2P - \param[in] Policy The option value which depends on action type - \param[in] pVal An optional value pointer - \param[in] ValLen An optional value length, in bytes - \return Zero on success or negative error code on failure. - \par Persistent - All parameters are System Persistent\n - Note that for SL_WLAN_POLICY_SCAN - Interval and Policy will be System persistent, but the hidden SSID option will not be persistent - - \sa sl_WlanPolicyGet - \note belongs to \ref ext_api - \warning - \par Example - - SL_WLAN_POLICY_CONNECTION:
defines options available to connect the CC31xx device to the AP: - The options below could be combined to a single action, if more than one action is required. - - - Auto Connect: If is set, the CC31xx device tries to automatically reconnect to one of its stored profiles, - each time the connection fails or the device is rebooted. To set this option, use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(1,0,0,0),NULL,0) - \endcode -
- - - - Fast Connect: If is set, the CC31xx device tries to establish a fast connection to AP. - To set this option, use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,1,0,0),NULL,0) - \endcode -
- - - P2P: If is set (relevant for P2P mode only), CC31xx/CC32xx device tries to automatically - connect to the first P2P device available, supporting push button only. To set this option, use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,0,1,0),NULL,0) - \endcode -
- - - Auto Provisioning - If is set, the CC31xx device will automatically start the provisioning process - after a long period of disconnection when profiles exist to set this option, use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,0,0,1),NULL,0) - \endcode \n - - - SL_WLAN_POLICY_SCAN:
defines system scan time interval. \nDefault interval is 10 minutes. - After settings scan interval, an immediate scan is activated.\n The next scan will be based on the interval settings. - For AP scan, minimum interval is 10 seconds. - - - With hidden SSID: For example, setting scan interval to 1 minute interval use including hidden ssid: - \code - _u32 intervalInSeconds = 60; - sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_SCAN_POLICY(1,1), (_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); - \endcode -
- - - No hidden SSID: setting scan interval to 1 minute interval use, not including hidden ssid: - \code - _u32 intervalInSeconds = 60; - sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_SCAN_POLICY(1,0), (_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); - \endcode -
- - - Disable scan: - \code - #define SL_WLAN_DISABLE_SCAN 0 - _u32 intervalInSeconds = 0; - sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_DISABLE_SCAN,(_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); - \endcode -
- - SL_WLAN_POLICY_PM:
defines a power management policy for Station mode only: - - Normal power management (default) policy use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_NORMAL_POLICY, NULL,0) - \endcode -
- - - Low latency power management policy use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LOW_LATENCY_POLICY, NULL,0) - \endcode -
- - - Low power management policy use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LOW_POWER_POLICY, NULL,0) - \endcode -
- - - Always on power management policy use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_ALWAYS_ON_POLICY, NULL,0) - \endcode -
- - - Long Sleep Interval policy use: - \code - SlWlanPmPolicyParams_t PmPolicyParams; - memset(&PmPolicyParams,0,sizeof(SlWlanPmPolicyParams_t)); - PmPolicyParams.MaxSleepTimeMs = 800; //max sleep time in mSec - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LONG_SLEEP_INTERVAL_POLICY, (_u8*)&PmPolicyParams,sizeof(PmPolicyParams)); - \endcode -
- - SL_WLAN_POLICY_P2P:
defines p2p negotiation policy parameters for P2P role: - - To set intent negotiation value, set on of the following:\n - SL_WLAN_P2P_ROLE_NEGOTIATE - intent 3 \n - SL_WLAN_P2P_ROLE_GROUP_OWNER - intent 15 \n - SL_WLAN_P2P_ROLE_CLIENT - intent 0 \n -
- - To set negotiation initiator value (initiator policy of first negotiation action frame), set on of the following: \n - SL_WLAN_P2P_NEG_INITIATOR_ACTIVE \n - SL_WLAN_P2P_NEG_INITIATOR_PASSIVE \n - SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF \n - \code - sl_WlanPolicySet(SL_WLAN_POLICY_P2P, SL_WLAN_P2P_POLICY(SL_WLAN_P2P_ROLE_NEGOTIATE,SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF),NULL,0); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanPolicySet) -_i16 sl_WlanPolicySet(const _u8 Type , const _u8 Policy, _u8 *pVal,const _u8 ValLen); -#endif -/*! - \brief Get policy values - - \param[in] Type - - SL_WLAN_POLICY_CONNECTION - - SL_WLAN_POLICY_SCAN - - SL_WLAN_POLICY_PM, SL_WLAN_POLICY_P2P - \param[out] pPolicy argument may be set to any value - \param[out] pVal The returned values, depends on each policy type, will be stored in the allocated buffer pointed by pVal - with a maximum buffer length set by the calling function and pointed to by argument *pValLen - \param[out] pValLen actual value length - \return Zero on success, or negative error code on failure - - \sa sl_WlanPolicySet - - \note belongs to \ref ext_api - - \warning The value pointed by the argument *pValLen should be set to a value different from 0 and - greater than the buffer length returned from the SL device. Otherwise, an error will be returned. - - \par Example - - - SL_WLAN_POLICY_CONNECTION - Get connection policy: - \code - _u8 Policy = 0; - int length = sizeof(PolicyOption); - int ret; - ret = sl_WlanPolicyGet(SL_WLAN_POLICY_CONNECTION ,&Policy,0,(_u8*)&length); - - if (Policy & SL_WLAN_CONNECTION_POLICY(1, 1 , 0 , 0 )) - { - printf("Connection Policy is set to Auto + Fast"); - } - \endcode -
- - - SL_WLAN_POLICY_SCAN - Get scan policy: - \code - int ScanInterval = 0; //default value is 600 seconds - _u8 Policy = 0; //default value is 0 (disabled) - int ret; - length = sizeof(ScanInterval); - ret = sl_WlanPolicyGet(SL_WLAN_POLICY_SCAN ,&Policy,(_u8*)&ScanInterval,(_u8*)&length); - - if (Policy & SL_WLAN_SCAN_POLICY(0 ,1)) - { - printf("Scan Policy is set to Scan visible ssid "); - } - if (Policy & SL_WLAN_SCAN_POLICY(1, 0)) - { - printf("Scan Policy is set to Scan hidden ssid "); - } - \endcode -
- - - SL_WLAN_POLICY_PM - Get power management policy: - \code - _u8 Policy = 0; - int ret; - SlWlanPmPolicyParams_t PmPolicyParams; - length = sizeof(PmPolicyParams); - ret = sl_WlanPolicyGet(SL_POLICY_PM ,&Policy,&PmPolicyParams,(_u8*)&length); - if (Policy == SL_WLAN_LONG_SLEEP_INTERVAL_POLICY ) - { - printf("Connection Policy is set to LONG SLEEP INTERVAL POLICY with interval = %d ",PmPolicyParams.MaxSleepTimeMs); - } - \endcode -
- - - SL_WLAN_POLICY_P2P - Get P2P policy: - \code - _u8 Policy = 0; - int ret; - length = sizeof(Policy); - ret = sl_WlanPolicyGet(SL_WLAN_POLICY_P2P ,&Policy,0,(_u8*)&length); - //SL_WLAN_P2P_POLICY(p2pNegType, p2pNegInitiator) - if (Policy & SL_WLAN_P2P_POLICY(0,SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF)) - { - printf("P2P Policy is set to Rand backoff"); - } - if (Policy & SL_WLAN_P2P_POLICY(SL_WLAN_P2P_ROLE_NEGOTIATE,0)) - { - printf("P2P Policy is set to Role Negotiate"); - } - \endcode -
- -*/ -#if _SL_INCLUDE_FUNC(sl_WlanPolicyGet) -_i16 sl_WlanPolicyGet(const _u8 Type ,_u8 *pPolicy,_u8 *pVal,_u8 *pValLen); -#endif -/*! - \brief Gets the WLAN scan operation results - - Gets scan results , gets entry from scan result table - - \param[in] Index Starting index identifier (range 0-29) for getting scan results - \param[in] Count How many entries to fetch. Max is (30-"Index"). - \param[out] pEntries Pointer to an allocated SlWlanNetworkEntry_t. - The number of array items should match "Count" \n - sec_type: - - SL_WLAN_SCAN_SEC_TYPE_OPEN - - SL_WLAN_SCAN_SEC_TYPE_WEP - - SL_WLAN_SCAN_SEC_TYPE_WPA - - SL_WLAN_SCAN_SEC_TYPE_WPA2 - - \return Number of valid networks list items - \sa - \note belongs to \ref ext_api - \warning This command do not initiate any active scanning action - \par Example - - - Fetching max 10 results: - \code - SlWlanNetworkEntry_t netEntries[10]; - _u8 i; - _i16 resultsCount = sl_WlanGetNetworkList(0,10,&netEntries[0]); - for(i=0; i< resultsCount; i++) - { - printf("%d. ",i+1); - printf("SSID: %.32s ",netEntries[i].Ssid); - printf("BSSID: %x:%x:%x:%x:%x:%x ",netEntries[i].Bssid[0],netEntries[i].Bssid[1],netEntries[i].Bssid[2],netEntries[i].Bssid[3],netEntries[i].Bssid[4],netEntries[i].Bssid[5]); - printf("Channel: %d ",netEntries[i].Channel); - printf("RSSI: %d ",netEntries[i].Rssi); - printf("Security type: %d ",SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(netEntries[i].SecurityInfo)); - printf("Group Cipher: %d ",SL_WLAN_SCAN_RESULT_GROUP_CIPHER(netEntries[i].SecurityInfo)); - printf("Unicast Cipher bitmap: %d ",SL_WLAN_SCAN_RESULT_UNICAST_CIPHER_BITMAP(netEntries[i].SecurityInfo)); - printf("Key Mgmt suites bitmap: %d ",SL_WLAN_SCAN_RESULT_KEY_MGMT_SUITES_BITMAP(netEntries[i].SecurityInfo)); - printf("Hidden SSID: %d\r\n",SL_WLAN_SCAN_RESULT_HIDDEN_SSID(netEntries[i].SecurityInfo)); - } - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanGetNetworkList) -_i16 sl_WlanGetNetworkList(const _u8 Index,const _u8 Count, SlWlanNetworkEntry_t *pEntries); -#endif - -/*! - \brief Start collecting wlan RX statistics, for unlimited time. - - \par Parameters - None - \return Zero on success, or negative error code on failure - - \sa sl_WlanRxStatStop sl_WlanRxStatGet - \note Belongs to \ref ext_api - \warning This API is deprecated and should be removed for next release - \par Example - - - Getting wlan RX statistics: - \code - void RxStatCollectTwice() - { - SlWlanGetRxStatResponse_t rxStat; - _i16 rawSocket; - _i8 DataFrame[200]; - struct SlTimeval_t timeval; - timeval.tv_sec = 0; // Seconds - timeval.tv_usec = 20000; // Microseconds. 10000 microseconds resolution - - sl_WlanRxStatStart(); // set statistics mode - - rawSocket = sl_Socket(SL_AF_RF, SL_SOCK_RAW, eChannel); - // set timeout - in case we have no activity for the specified channel - sl_SetSockOpt(rawSocket,SL_SOL_SOCKET,SL_SO_RCVTIMEO, &timeval, sizeof(timeval)); // Enable receive timeout - status = sl_Recv(rawSocket, DataFrame, sizeof(DataFrame), 0); - - Sleep(1000); // sleep for 1 sec - sl_WlanRxStatGet(&rxStat,0); // statistics has been cleared upon read - Sleep(1000); // sleep for 1 sec - sl_WlanRxStatGet(&rxStat,0); - } - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanRxStatStart) -_i16 sl_WlanRxStatStart(void); -#endif - -/*! - \brief Stop collecting wlan RX statistic, (if previous called sl_WlanRxStatStart) - - \par Parameters - None - \return Zero on success, or negative error code on failure - - \sa sl_WlanRxStatStart sl_WlanRxStatGet - \note Belongs to \ref ext_api - \warning This API is deprecated and should be removed for next release -*/ -#if _SL_INCLUDE_FUNC(sl_WlanRxStatStop) -_i16 sl_WlanRxStatStop(void); -#endif - - -/*! - \brief Get wlan RX statistics. Upon calling this command, the statistics counters will be cleared. - - \param[in] pRxStat Pointer to SlWlanGetRxStatResponse_t filled with Rx statistics results - \param[in] Flags Should be 0 ( not applicable right now, will be added the future ) - \return Zero on success, or negative error code on failure - - \sa sl_WlanRxStatStart sl_WlanRxStatStop - \note Belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_WlanRxStatGet) -_i16 sl_WlanRxStatGet(SlWlanGetRxStatResponse_t *pRxStat,const _u32 Flags); -#endif - - -/*! - \brief The simpleLink will switch to the appropriate role according to the provisioning mode requested - and will start the provisioning process. - - \param[in] ProvisioningCmd - - SL_WLAN_PROVISIONING_CMD_START_MODE_AP 0: Start AP provisioning (AP role) - - SL_WLAN_PROVISIONING_CMD_START_MODE_SC 1: Start Smart Config provisioning (STA role) - - SL_WLAN_PROVISIONING_CMD_START_MODE_APSC 2: Start AP+Smart Config provisioning (AP role) - - SL_WLAN_PROVISIONING_CMD_START_MODE_APSC_EXTERNAL_CONFIGURATION 3: Start AP + Smart Config + WAC provisioning (AP role) - - SL_WLAN_PROVISIONING_CMD_STOP 4: Stop provisioning - - SL_WLAN_PROVISIONING_CMD_ABORT_EXTERNAL_CONFIGURATIONC 5: - \param[in] RequestedRoleAfterSuccess The role that the SimpleLink will switch to in case of a successful provisioning. - 0: STA - 2: AP - 0xFF: stay in current role (relevant only in provisioning_stop) - \param[in] InactivityTimeoutSec - The period of time (in seconds) the system waits before it automatically - stops the provisioning process when no activity is detected. - set to 0 in order to stop provisioning. Minimum InactivityTimeoutSec is 30 seconds. - \param[in] pSmartConfigKey Smart Config key: public key for smart config process (relevant for smart config only) - \param[in] Flags Can have the following values: - - SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION - Confirmation phase will be completed externally by host (e.g. via cloud assist) - - - \return Zero on success, or negative error code on failure - - \sa - \warning - \par Example - - - Start Provisioning - start as STA after success with inactivity timeout of 10 minutes: - \code - sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC, ROLE_STA, 600, "Key0Key0Key0Key0", 0x0); - \endcode -
- - - Stop Provisioning: - \code - sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP,0xFF,0,NULL, 0x0); - \endcode -
- - - Start AP Provisioning with inactivity timeout of 10 minutes - \code - sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC,ROLE_AP,600,NULL, 0x0); - \endcode -
- - - Start AP Provisioning with inactivity timeout of 10 minutes and complete confirmation via user cloud assist - \code - sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC, ROLE_AP, 600, NULL, SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION); - \endcode -
- -*/ - -#if _SL_INCLUDE_FUNC(sl_WlanProvisioning) -_i16 sl_WlanProvisioning(_u8 ProvisioningCmd, _u8 RequestedRoleAfterSuccess, _u16 InactivityTimeoutSec, char *pSmartConfigKey, _u32 Flags); -#endif - - - -/*! - \brief Wlan set mode - - Setting WLAN mode - - \param[in] Mode WLAN mode to start the CC31xx device. Possible options are - - ROLE_STA - for WLAN station mode - - ROLE_AP - for WLAN AP mode - - ROLE_P2P -for WLAN P2P mode - \return Zero on success, or negative error code on failure - \par Persistent - Mode is Persistent - \sa sl_Start sl_Stop - \note Belongs to \ref ext_api - \warning After setting the mode the system must be restarted for activating the new mode - \par Example - - - Switch from any role to STA: - \code - sl_WlanSetMode(ROLE_STA); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_WlanSetMode) -_i16 sl_WlanSetMode(const _u8 Mode); -#endif - - -/*! - \brief Setting WLAN configurations - - \param[in] ConfigId - configuration id - - SL_WLAN_CFG_AP_ID - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_CFG_P2P_PARAM_ID - - SL_WLAN_RX_FILTERS_ID - - \param[in] ConfigOpt - configurations option - - SL_WLAN_CFG_AP_ID - - SL_WLAN_AP_OPT_SSID \n - Set SSID for AP mode. \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_CHANNEL \n - Set channel for AP mode. \n - The channel is dependant on the country code which is set. i.e. for "US" the channel should be in the range of [1-11] \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_HIDDEN_SSID \n - Set Hidden SSID Mode for AP mode.Hidden options: \n - 0: disabled \n - 1: Send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID \n - 2: Clear SSID (ASCII 0), but keep the original length (this may be required with some \n - clients that do not support empty SSID) and ignore probe requests for broadcast SSID \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_SECURITY_TYPE \n - Set Security type for AP mode. Security options are: - - Open security: SL_WLAN_SEC_TYPE_OPEN - - WEP security: SL_WLAN_SEC_TYPE_WEP - - WPA security: SL_WLAN_SEC_TYPE_WPA_WPA2 \n - This option takes _u8 pointer as a parameter - - SL_WLAN_AP_OPT_PASSWORD \n - Set Password for for AP mode (for WEP or for WPA): \n - Password - for WPA: 8 - 63 characters \n - for WEP: 5 / 13 characters (ascii) \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_MAX_STATIONS \n - Set Max AP stations - 1..4 - Note: can be less than the number of currently connected stations \n - max_stations - 1 characters \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_MAX_STA_AGING \n - Set Max station ageing time - default is 60 seconds \n - max_stations - 2 characters \n - This options takes _u16 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_MODE \n - Set AP access list mode - DISABLE, DENY_LIST \n - mode - 1 characters \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_ADD_MAC \n - Add MAC address to the AP access list: \n - mac_addr - 6 characters \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_DEL_MAC \n - Del MAC address from the AP access list: \n - mac_addr - 6 characters \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_DEL_IDX \n - Delete MAC address from index in the AP access list: \n - index - 1 character \n - This options takes _u8 buffer as parameter - - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE \n - Set Country Code for AP mode \n - This options takes _u8 2 bytes buffer as parameter - - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER \n - Set STA mode Tx power level \n - Number between 0-15, as dB offset from max power (0 will set MAX power) \n - This options takes _u8 as parameter - - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER - Set AP mode Tx power level \n - Number between 0-15, as dB offset from max power (0 will set MAX power) \n - This options takes _u8 as parameter - - SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT - Set Info Element for AP mode. \n - The Application can set up to SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED info elements per Role (AP / P2P GO). \n - To delete an info element use the relevant index and length = 0. \n - For AP - no more than SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_AP bytes can be stored for all info elements. \n - For P2P GO - no more than SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_P2P_GO bytes can be stored for all info elements. \n - This option takes SlWlanSetInfoElement_t as parameter - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS - Set scan parameters: RSSI threshold and channel mask. - - SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES - Set suspended profiles mask (set bits 2 and 4 to suspend profiles 2 and 4). - - - SL_WLAN_CFG_P2P_PARAM_ID - - SL_WLAN_P2P_OPT_DEV_TYPE \n - Set P2P Device type.Maximum length of 17 characters. Device type is published under P2P I.E, \n - allows to make devices easier to recognize. \n - In case no device type is set, the default type is "1-0050F204-1" \n - This options takes _u8 buffer as parameter - - SL_WLAN_P2P_OPT_CHANNEL_N_REGS \n - Set P2P Channels. \n - listen channel (either 1/6/11 for 2.4GHz) \n - listen regulatory class (81 for 2.4GHz) \n - oper channel (either 1/6/11 for 2.4GHz) \n - oper regulatory class (81 for 2.4GHz) \n - listen channel and regulatory class will determine the device listen channel during p2p find listen phase \n - oper channel and regulatory class will determine the operating channel preferred by this device (in case it is group owner this will be the operating channel) \n - channels should be one of the social channels (1/6/11). In case no listen/oper channel selected, a random 1/6/11 will be selected. - This option takes pointer to _u8[4] as parameter - - - SL_WLAN_RX_FILTERS_ID - - SL_WLAN_RX_FILTER_STATE \n - Enable or disable filters. The buffer input is SlWlanRxFilterOperationCommandBuff_t\n - - SL_WLAN_RX_FILTER_SYS_STATE \n - Enable or disable system filters. The buffer input is SlWlanRxFilterSysFiltersSetStateBuff_t\n - - SL_WLAN_RX_FILTER_REMOVE \n - Remove filters. The buffer input is SlWlanRxFilterOperationCommandBuff_t\n - - SL_WLAN_RX_FILTER_STORE \n - Save the filters as persistent. \n - - SL_WLAN_RX_FILTER_UPDATE_ARGS \n - Update filter arguments. The buffer input is SlWlanRxFilterUpdateArgsCommandBuff_t\n - - \param[in] ConfigLen - configurations len - - \param[in] pValues - configurations values - - \return Zero on success, or negative error code on failure - - \par Persistent - System Persistent: - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_CFG_P2P_PARAM_ID - - Reset: - - SL_WLAN_CFG_AP_ID - - Non- Persistent: - - SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH - \sa - \note - \warning - \par Examples - - - SL_WLAN_AP_OPT_SSID: - \code - _u8 str[33]; - memset(str, 0, 33); - memcpy(str, ssid, len); // ssid string of 32 characters - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_SSID, strlen(ssid), str); - \endcode -
- - - SL_WLAN_AP_OPT_CHANNEL: - \code - _u8 val = channel; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_CHANNEL, 1, (_u8 *)&val); - \endcode -
- - - SL_WLAN_AP_OPT_HIDDEN_SSID: - \code - _u8 val = hidden; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_HIDDEN_SSID, 1, (_u8 *)&val); - \endcode -
- - - SL_WLAN_AP_OPT_SECURITY_TYPE: - \code - _u8 val = SL_WLAN_SEC_TYPE_WPA_WPA2; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_SECURITY_TYPE, 1, (_u8 *)&val); - \endcode -
- - - SL_WLAN_AP_OPT_PASSWORD: - \code - _u8 str[65]; - _u16 len = strlen(password); - memset(str, 0, 65); - memcpy(str, password, len); - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_PASSWORD, len, (_u8 *)str); - \endcode -
- - - SL_WLAN_AP_OPT_MAX_STATIONS: - \code - _u8 max_ap_stations = 3; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_MAX_STATIONS, sizeof(max_ap_stations), (_u8 *)&max_ap_stations); - \endcode -
- - - SL_WLAN_AP_OPT_MAX_STA_AGING: - \code - _u16 max_ap_sta_aging = 60; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_MAX_STA_AGING, sizeof(max_ap_sta_aging), (_u8 *)&max_ap_sta_aging); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_MODE: - \code - _u8 access list_mode = SL_WLAN_AP_ACCESS_LIST_MODE_DENY_LIST; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_MODE, sizeof(access list_mode), (_u8 *)&access list_mode); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_ADD_MAC: - \code - _u8 sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_ADD_MAC, sizeof(sta_mac), (_u8 *)&sta_mac); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_DEL_MAC: - \code - _u8 sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_DEL_MAC, sizeof(sta_mac), (_u8 *)&sta_mac); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_DEL_IDX: - \code - _u8 sta_index = 0; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_DEL_IDX, sizeof(sta_index), (_u8 *)&sta_index); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER: - \code - _u8 stapower=(_u8)power; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER,1,(_u8 *)&stapower); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE: - \code - _u8* str = (_u8 *) country; // string of 2 characters. i.e. - "US" - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE, 2, str); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER: - \code - _u8 appower=(_u8)power; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER,1,(_u8 *)&appower); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES - \code - _u32 suspendedProfilesMask=(_u32)mask; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES,sizeof(suspendedProfilesMask),(_u32 *)&suspendedProfilesMask); - \endcode -
- - - SL_WLAN_P2P_OPT_DEV_TYPE: - \code - _u8 str[17]; - _u16 len = strlen(device_type); - memset(str, 0, 17); - memcpy(str, device_type, len); - sl_WlanSet(SL_WLAN_CFG_P2P_PARAM_ID, SL_WLAN_P2P_OPT_DEV_TYPE, len, str); - \endcode -
- - - SL_WLAN_P2P_OPT_CHANNEL_N_REGS - \code - _u8 str[4]; - str[0] = (_u8)11; // listen channel - str[1] = (_u8)81; // listen regulatory class - str[2] = (_u8)6; // oper channel - str[3] = (_u8)81; // oper regulatory class - sl_WlanSet(SL_WLAN_CFG_P2P_PARAM_ID, SL_WLAN_P2P_OPT_CHANNEL_N_REGS, 4, str); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT: - \code - SlWlanSetInfoElement_t infoele; - infoele.Index = Index; // Index of the info element. range: 0 - SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED - infoele.Role = Role; // SL_WLAN_INFO_ELEMENT_AP_ROLE (0) or SL_WLAN_INFO_ELEMENT_P2P_GO_ROLE (1) - infoele.IE.Id = Id; // Info element ID. if SL_WLAN_INFO_ELEMENT_DEFAULT_ID (0) is set, ID will be set to 221. - // Organization unique ID. If all 3 bytes are zero - it will be replaced with 08,00,28. - infoele.IE.Oui[0] = Oui0; // Organization unique ID first Byte - infoele.IE.Oui[1] = Oui1; // Organization unique ID second Byte - infoele.IE.Oui[2] = Oui2; // Organization unique ID third Byte - infoele.IE.Length = Len; // Length of the info element. must be smaller than 253 bytes - memset(infoele.IE.Data, 0, SL_WLAN_INFO_ELEMENT_MAX_SIZE); - if ( Len <= SL_WLAN_INFO_ELEMENT_MAX_SIZE ) - { - memcpy(infoele.IE.Data, IE, Len); // Info element. length of the info element is [0-252] - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT,sizeof(SlWlanSetInfoElement_t),(_u8* ) &infoele); - } - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS: - \code - SlWlanScanParamCommand_t ScanParamConfig; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS; - _u16 OptionLen = sizeof(ScanParamConfig); - // 2.4G channels bits order: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 - - ScanParamConfig.RssiThreshold = -70; - ScanParamConfig.ChannelsMask = 0x1FFF; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, &Option, &OptionLen, (_u8 *)&ScanParamConfig); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH: - \code - _u8 param = 1; // 1 means disable the server authentication - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH,1,¶m); - \endcode -
- - SL_WLAN_RX_FILTER_STORE: - \code - sl_WlanSet(SL_WLAN_RX_FILTERS_ID, SL_WLAN_RX_FILTER_STORE, 0, NULL); - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_WlanSet) -_i16 sl_WlanSet(const _u16 ConfigId ,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues); -#endif - -/*! - \brief Getting WLAN configurations - - \param[in] ConfigId - configuration id - - SL_WLAN_CFG_AP_ID - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_CFG_P2P_PARAM_ID - - SL_WLAN_CFG_AP_ACCESS_LIST_ID - - SL_WLAN_RX_FILTERS_ID - - \param[out] pConfigOpt - get configurations option - - SL_WLAN_CFG_AP_ID - - SL_WLAN_AP_OPT_SSID \n - Get SSID for AP mode. \n - Get up to 32 characters of SSID \n - This options takes _u8 as parameter - - SL_WLAN_AP_OPT_CHANNEL \n - Get channel for AP mode. \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_HIDDEN_SSID \n - Get Hidden SSID Mode for AP mode.Hidden options: \n - 0: disabled \n - 1: Send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID \n - 2: Clear SSID (ASCII 0), but keep the original length (this may be required with some \n - clients that do not support empty SSID) and ignore probe requests for broadcast SSID \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_SECURITY_TYPE \n - Get Security type for AP mode. Security options are: - - Open security: SL_WLAN_SEC_TYPE_OPEN - - WEP security: SL_WLAN_SEC_TYPE_WEP - - WPA security: SL_WLAN_SEC_TYPE_WPA_WPA2 \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_PASSWORD \n - Get Password for for AP mode (for WEP or for WPA): \n - Returns password - string, fills up to 64 characters. \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_MAX_STATIONS \n - Get Max AP allowed stations: \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_MAX_STA_AGING \n - Get AP aging time in seconds: \n - This options takes _u16 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES \n - Get AP access list number of entries: \n - This options takes _u8 buffer as parameter - - SL_WLAN_CFG_AP_ACCESS_LIST_ID - - The option is the start index in the access list \n - Get the AP access list from start index, the number of entries in the list is extracted from the request length. - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS \n - Get scan parameters. - This option uses SlWlanScanParamCommand_t as parameter - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE \n - Get Country Code for AP mode \n - This options takes _u8 buffer as parameter - - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER \n - Get STA mode Tx power level \n - Number between 0-15, as dB offset from max power (0 indicates MAX power) \n - This options takes _u8 as parameter - - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER - Get AP mode Tx power level \n - Number between 0-15, as dB offset from max power (0 indicates MAX power) \n - This options takes _u8 as parameter - - SL_WLAN_CFG_P2P_PARAM_ID - - SL_WLAN_P2P_OPT_CHANNEL_N_REGS \n - Get P2P Channels. \n - listen channel (either 1/6/11 for 2.4GHz) \n - listen regulatory class (81 for 2.4GHz) \n - oper channel (either 1/6/11 for 2.4GHz) \n - oper regulatory class (81 for 2.4GHz) \n - listen channel and regulatory class will determine the device listen channel during p2p find listen phase \n - oper channel and regulatory class will determine the operating channel preferred by this device (in case it is group owner this will be the operating channel) \n - channels should be one of the social channels (1/6/11). In case no listen/oper channel selected, a random 1/6/11 will be selected. \n - This option takes pointer to _u8[4] as parameter - - SL_WLAN_RX_FILTERS_ID - - SL_WLAN_RX_FILTER_STATE \n - Retrieves the filters enable/disable status. The buffer input is SlWlanRxFilterRetrieveStateBuff_t \n - - SL_WLAN_RX_FILTER_SYS_STATE \n - Retrieves the system filters enable/disable status. The buffer input is SlWlanRxFilterSysFiltersRetrieveStateBuff_t: - - \param[out] pConfigLen - The length of the allocated memory as input, when the - function complete, the value of this parameter would be - the len that actually read from the device. - If the device return length that is longer from the input - value, the function will cut the end of the returned structure - and will return SL_ESMALLBUF. - - - \param[out] pValues - get configurations values - \return Zero on success, or negative error code on failure - \sa sl_WlanSet - \note - In case the device was started as AP mode, but no SSID was set, the Get SSID will return "mysimplelink" and not "mysimplelink-xxyyzz" - \warning - \par Examples - - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS: - \code - SlWlanScanParamCommand_t ScanParamConfig; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS; - _u16 OptionLen = sizeof(SlWlanScanParamCommand_t); - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&ScanParamConfig); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER: - \code - _i32 TXPower = 0; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER; - _u16 OptionLen = sizeof(TXPower); - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&TXPower); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPTSTA_TX_POWER: - \code - _i32 TXPower = 0; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER; - _u16 OptionLen = sizeof(TXPower); - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&TXPower); - \endcode -
- - - SL_WLAN_P2P_OPT_DEV_TYPE: - \code - _i8 device_type[18]; - _u16 len = 18; - _u16 config_opt = SL_WLAN_P2P_OPT_DEV_TYPE; - sl_WlanGet(SL_WLAN_CFG_P2P_PARAM_ID, &config_opt , &len, (_u8* )device_type); - \endcode -
- - - SL_WLAN_AP_OPT_SSID: - \code - _i8 ssid[33]; - _u16 len = 33; - sl_Memset(ssid,0,33); - _u16 config_opt = SL_WLAN_AP_OPT_SSID; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt , &len, (_u8* )ssid); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE: - \code - _i8 country[3]; - _u16 len = 3; - _u16 config_opt = SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE; - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID, &config_opt, &len, (_u8* )country); - \endcode -
- - - SL_WLAN_AP_OPT_CHANNEL: - \code - _i8 channel; - _u16 len = 1; - _u16 config_opt = SL_WLAN_AP_OPT_CHANNEL; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&channel); - \endcode -
- - - SL_WLAN_AP_OPT_HIDDEN_SSID: - \code - _u8 hidden; - _u16 len = 1; - _u16 config_opt = SL_WLAN_AP_OPT_HIDDEN_SSID; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&hidden); - \endcode -
- - - SL_WLAN_AP_OPT_SECURITY_TYPE: - \code - _u8 sec_type; - _u16 len = 1; - _u16 config_opt = SL_WLAN_AP_OPT_SECURITY_TYPE; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&sec_type); - \endcode -
- - - SL_WLAN_AP_OPT_PASSWORD: - \code - _u8 password[64]; - _u16 len = 64; - sl_Memset(password,0,64); - _u16 config_opt = SL_WLAN_AP_OPT_PASSWORD; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )password); - \endcode -
- - - SL_WLAN_AP_OPT_MAX_STATIONS: - \code - _u8 max_ap_stations - _u16 len = 1; - _u16 config_opt = SL_WLAN_AP_OPT_MAX_STATIONS; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&max_ap_stations); - \endcode -
- - - SL_WLAN_AP_OPT_MAX_STA_AGING: - \code - _u16 ap_sta_aging; - _u16 len = 2; - _u16 config_opt = SL_WLAN_AP_OPT_MAX_STA_AGING; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&ap_sta_aging); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES: - \code - _u8 aclist_num_entries; - _u16 config_opt = SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES; - _u16 len = sizeof(aclist_num_entries); - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&aclist_num_entries); - \endcode -
- - - SL_WLAN_CFG_AP_ACCESS_LIST_ID: - \code - _u8 aclist_mac[SL_WLAN_MAX_ACCESS_LIST_STATIONS][MAC_LEN]; - unsigned char aclist_num_entries; - unsigned short config_opt; - unsigned short len; - int actual_aclist_num_entries; - unsigned short start_aclist_index; - unsigned short aclist_info_len; - int i; - - start_aclist_index = 0; - aclist_info_len = 2*MAC_LEN; - sl_WlanGet(SL_WLAN_CFG_AP_ACCESS_LIST_ID, &start_aclist_index, &aclist_info_len, (_u8 *)&aclist_mac[start_aclist_index]); - - actual_aclist_num_entries = aclist_info_len / MAC_LEN; - printf("-Print AP Deny list, num stations = %d\n", actual_aclist_num_entries); - for (i=0; i - - - SL_WLAN_P2P_OPT_CHANNEL_N_REGS: - \code - _u16 listen_channel,listen_reg,oper_channel,oper_reg; - _u16 len = 4; - _u16 config_opt = SL_WLAN_P2P_OPT_CHANNEL_N_REGS; - _u8 channel_n_regs[4]; - sl_WlanGet(SL_WLAN_CFG_P2P_PARAM_ID, &config_opt, &len, (_u8* )channel_n_regs); - listen_channel = channel_n_regs[0]; - listen_reg = channel_n_regs[1]; - oper_channel = channel_n_regs[2]; - oper_reg = channel_n_regs[3]; - \endcode -
- - - SL_WLAN_RX_FILTER_STATE: - \code - int ret = 0; - SlWlanRxFilterIdMask_t FilterIdMask; - _u16 len = sizeof(SlWlanRxFilterIdMask_t);; - _u16 config_opt = SL_WLAN_RX_FILTER_STATE; - memset(FilterIdMask,0,sizeof(FilterIdMask)); - ret = sl_WlanGet(SL_WLAN_RX_FILTERS_ID, &config_opt , &len, (_u8* )FilterIdMask); - \endcode -
- - - SL_WLAN_RX_FILTER_SYS_STATE: - \code - int ret = 0; - SlWlanRxFilterSysFiltersMask_t FilterSysIdMask; - _u16 len = sizeof(SlWlanRxFilterSysFiltersMask_t);; - _u16 config_opt = SL_WLAN_RX_FILTER_SYS_STATE; - memset(FilterSysIdMask,0,sizeof(FilterSysIdMask)); - ret = sl_WlanGet(SL_WLAN_RX_FILTERS_ID, &config_opt , &len, (_u8* )FilterSysIdMask); - \endcode -
- - - SL_WLAN_CONNECTION_INFO: - \code - _i16 RetVal = 0 ; - _u16 Len = sizeof(SlWlanConnStatusParam_t) ; - SlWlanConnStatusParam_t WlanConnectInfo ; - RetVal = sl_WlanGet(SL_WLAN_CONNECTION_INFO, NULL , &Len, (_u8*)&WlanConnectInfo); - \endcode -
- -*/ - -#if _SL_INCLUDE_FUNC(sl_WlanGet) -_i16 sl_WlanGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues); -#endif - -/*! - \brief Adds new filter rule to the system - - \param[in] RuleType The rule type - - SL_WLAN_RX_FILTER_HEADER - - SL_WLAN_RX_FILTER_COMBINATION - - \param[in] Flags Flags which set the type of header rule Args and sets the persistent flag - - SL_WLAN_RX_FILTER_BINARY - - SL_WLAN_RX_FILTER_PERSISTENT - - SL_WLAN_RX_FILTER_ENABLE - - \param[in] pRule Determine the filter rule logic - \param[in] pTrigger Determine when the rule is triggered also sets rule parent. - \param[in] pAction Sets the action to be executed in case the match functions pass - \param[out] pFilterId The filterId which was created - - \par Persistent Save the filters for persistent can be done by calling with SL_WLAN_RX_FILTER_STORE - - \return Zero on success, or negative error code on failure - \sa - \note - \warning - */ -#if _SL_INCLUDE_FUNC(sl_WlanRxFilterAdd) -_i16 sl_WlanRxFilterAdd( SlWlanRxFilterRuleType_t RuleType, - SlWlanRxFilterFlags_u Flags, - const SlWlanRxFilterRule_u* const pRule, - const SlWlanRxFilterTrigger_t* const pTrigger, - const SlWlanRxFilterAction_t* const pAction, - SlWlanRxFilterID_t* pFilterId); - -#endif - -/*! - - Close the Doxygen group. - @} - - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __WLAN_H__ */ - diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.c deleted file mode 100755 index 25b4dc9db0b..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.c +++ /dev/null @@ -1,1420 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== PowerCC32XX.c ======== - */ - -#include - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif -#include -#include - -#include - -#include -#include - -#if defined(__IAR_SYSTEMS_ICC__) -#include -#endif - -/* driverlib header files */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#define STATUS_BUSY 0x01 - -#define PowerCC32XX_SSPIReadStatusInstruction (0x05) -#define PowerCC32XX_SSPIPowerDownInstruction (0xB9) -#define PowerCC32XX_SSPISemaphoreTakeTries (4000000) -#define PowerCC32XX_SSPICSDelay 33 -#define uSEC_DELAY(x) (ROM_UtilsDelayDirect(x*80/3)) - -#define SYNCBARRIER() { \ - __asm(" dsb \n" \ - " isb \n"); \ -} - -/* Externs */ -extern const PowerCC32XX_ConfigV1 PowerCC32XX_config; - -/* Module_State */ -PowerCC32XX_ModuleState PowerCC32XX_module = { - { NULL, NULL}, /* list */ - 0, /* constraintsMask */ - Power_ACTIVE, /* state */ - /* dbRecords */ - { - PRCM_CAMERA, /* PERIPH_CAMERA */ - PRCM_I2S, /* PERIPH_MCASP */ - PRCM_SDHOST, /* PERIPH_MMCHS */ - PRCM_GSPI, /* PERIPH_MCSPI_A1 */ - PRCM_LSPI, /* PERIPH_MCSPI_A2 */ - PRCM_UDMA, /* PERIPH_UDMA_A */ - PRCM_GPIOA0, /* PERIPH_GPIO_A */ - PRCM_GPIOA1, /* PERIPH_GPIO_B */ - PRCM_GPIOA2, /* PERIPH_GPIO_C */ - PRCM_GPIOA3, /* PERIPH_GPIO_D */ - PRCM_GPIOA4, /* PERIPH_GPIO_E */ - PRCM_WDT, /* PERIPH_WDOG_A */ - PRCM_UARTA0, /* PERIPH_UART_A0 */ - PRCM_UARTA1, /* PERIPH_UART_A1 */ - PRCM_TIMERA0, /* PERIPH_GPT_A0 */ - PRCM_TIMERA1, /* PERIPH_GPT_A1 */ - PRCM_TIMERA2, /* PERIPH_GPT_A2 */ - PRCM_TIMERA3, /* PERIPH_GPT_A3 */ - PRCM_DTHE, /* PERIPH_CRYPTO */ - PRCM_SSPI, /* PERIPH_MCSPI_S0 */ - PRCM_I2CA0 /* PERIPH_I2C */ - }, - /* enablePolicy */ - FALSE, - /* initialized */ - FALSE, - /* refCount */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - /* constraintCounts */ - { 0, 0 }, - /* policyFxn */ - NULL -}; - -/* context save variable */ -PowerCC32XX_SaveRegisters PowerCC32XX_contextSave; - -typedef void (*LPDSFunc)(void); - -/* enter LPDS is an assembly function */ -// TODO: Uncomment this once the PowerCC32XX_enterLPDS has been implemented in assembly for all toolchains -//extern void PowerCC32XX_enterLPDS(LPDSFunc driverlibFunc); - -/* pin parking functions */ -void PowerCC32XX_parkPin(PowerCC32XX_Pin pin, PowerCC32XX_ParkState parkState, - uint32_t * previousState, uint16_t * previousDirection); -void PowerCC32XX_restoreParkedPin(PowerCC32XX_Pin pin, uint32_t type, - uint16_t direction); -void PowerCC32XX_shutdownSSPI(void); - -/* internal functions */ -static int_fast16_t notify(uint_fast16_t eventType); -static void restoreNVICRegs(void); -static void restorePeriphClocks(void); -static void saveNVICRegs(void); -static void parkPins(void); -static void restoreParkedPins(void); - -/* - * ======== Power_disablePolicy ======== - * Do not run the configured policy - */ -bool Power_disablePolicy(void) -{ - bool enablePolicy = PowerCC32XX_module.enablePolicy; - PowerCC32XX_module.enablePolicy = FALSE; - - DebugP_log0("Power: disable policy"); - - return (enablePolicy); -} - -/* - * ======== Power_enablePolicy ======== - * Run the configured policy - */ -void Power_enablePolicy(void) -{ - PowerCC32XX_module.enablePolicy = TRUE; - - DebugP_log0("Power: enable policy"); -} - -/* - * ======== Power_getConstraintMask ======== - * Get a bitmask indicating the constraints that have been registered with - * Power. - */ -uint_fast32_t Power_getConstraintMask(void) -{ - return (PowerCC32XX_module.constraintMask); -} - -/* - * ======== Power_getDependencyCount ======== - * Get the count of dependencies that are currently declared upon a resource. - */ -int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId) -{ - int_fast16_t status; - - if (resourceId >= PowerCC32XX_NUMRESOURCES) { - status = Power_EINVALIDINPUT; - } - else { - status = PowerCC32XX_module.refCount[resourceId]; - } - - return (status); -} - -/* - * ======== Power_getTransitionLatency ======== - * Get the transition latency for a sleep state. The latency is reported - * in units of microseconds. - */ -uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, - uint_fast16_t type) -{ - uint32_t latency = 0; - - if (type == Power_RESUME) { - latency = PowerCC32XX_RESUMETIMELPDS; - } - else { - latency = PowerCC32XX_TOTALTIMELPDS; - } - - return (latency); -} - -/* - * ======== Power_getTransitionState ======== - * Get the current sleep transition state. - */ -uint_fast16_t Power_getTransitionState(void) -{ - return (PowerCC32XX_module.state); -} - -/* - * ======== Power_idleFunc ======== - * Function needs to be plugged into the idle loop. - * It calls the configured policy function if the - * 'enablePolicy' flag is set. - */ -void Power_idleFunc() -{ - if (PowerCC32XX_module.enablePolicy) { - if (PowerCC32XX_module.policyFxn != NULL) { - DebugP_log1("Power: calling policy function (%p)", - (uintptr_t) PowerCC32XX_module.policyFxn); - (*(PowerCC32XX_module.policyFxn))(); - } - } -} - -/* - * ======== Power_init ======== - */ -int_fast16_t Power_init() -{ - /* if this function has already been called, just return */ - if (PowerCC32XX_module.initialized) { - return (Power_SOK); - } - - /* set module state field 'initialized' to true */ - PowerCC32XX_module.initialized = TRUE; - - /* set the module state enablePolicy field */ - PowerCC32XX_module.enablePolicy = PowerCC32XX_config.enablePolicy; - - /* call the config policy init function if its not null */ - if (PowerCC32XX_config.policyInitFxn != NULL) { - (*(PowerCC32XX_config.policyInitFxn))(); - } - - /* copy wakeup settings to module state */ - PowerCC32XX_module.wakeupConfig.enableGPIOWakeupLPDS = - PowerCC32XX_config.enableGPIOWakeupLPDS; - PowerCC32XX_module.wakeupConfig.enableGPIOWakeupShutdown = - PowerCC32XX_config.enableGPIOWakeupShutdown; - PowerCC32XX_module.wakeupConfig.enableNetworkWakeupLPDS = - PowerCC32XX_config.enableNetworkWakeupLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceLPDS = - PowerCC32XX_config.wakeupGPIOSourceLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeLPDS = - PowerCC32XX_config.wakeupGPIOTypeLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS = - PowerCC32XX_config.wakeupGPIOFxnLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg = - PowerCC32XX_config.wakeupGPIOFxnLPDSArg; - PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceShutdown = - PowerCC32XX_config.wakeupGPIOSourceShutdown; - PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeShutdown = - PowerCC32XX_config.wakeupGPIOTypeShutdown; - - /* now configure these wakeup settings in the device... */ - PowerCC32XX_configureWakeup(&PowerCC32XX_module.wakeupConfig); - - /* copy the Power policy function to module state */ - PowerCC32XX_module.policyFxn = PowerCC32XX_config.policyFxn; - - /* spin if too many pins were specified in the pin park array */ - if (PowerCC32XX_config.numPins > PowerCC32XX_NUMPINS) { - while(1){} - } - - return (Power_SOK); -} - -/* - * ======== Power_registerNotify ======== - * Register a function to be called on a specific power event. - */ -int_fast16_t Power_registerNotify(Power_NotifyObj * pNotifyObj, - uint_fast16_t eventTypes, Power_NotifyFxn notifyFxn, uintptr_t clientArg) -{ - int_fast16_t status = Power_SOK; - - /* check for NULL pointers */ - if ((pNotifyObj == NULL) || (notifyFxn == NULL)) { - status = Power_EINVALIDPOINTER; - } - - else { - /* fill in notify object elements */ - pNotifyObj->eventTypes = eventTypes; - pNotifyObj->notifyFxn = notifyFxn; - pNotifyObj->clientArg = clientArg; - - /* place notify object on event notification queue */ - List_put(&PowerCC32XX_module.notifyList, (List_Elem*)pNotifyObj); - } - - DebugP_log3( - "Power: register notify (%p), eventTypes (0x%x), notifyFxn (%p)", - (uintptr_t) pNotifyObj, eventTypes, (uintptr_t) notifyFxn); - - return (status); -} - -/* - * ======== Power_releaseConstraint ======== - * Release a previously declared constraint. - */ -int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) -{ - int_fast16_t status = Power_SOK; - uintptr_t key; - uint8_t count; - - /* first ensure constraintId is valid */ - if (constraintId >= PowerCC32XX_NUMCONSTRAINTS) { - status = Power_EINVALIDINPUT; - } - - /* if constraintId is OK ... */ - else { - - /* disable interrupts */ - key = HwiP_disable(); - - /* get the count of the constraint */ - count = PowerCC32XX_module.constraintCounts[constraintId]; - - /* ensure constraint count is not already zero */ - if (count == 0) { - status = Power_EFAIL; - } - - /* if not already zero ... */ - else { - /* decrement the count */ - count--; - - /* save the updated count */ - PowerCC32XX_module.constraintCounts[constraintId] = count; - - /* if constraint count reaches zero, remove constraint from mask */ - if (count == 0) { - PowerCC32XX_module.constraintMask &= ~(1 << constraintId); - } - } - - /* restore interrupts */ - HwiP_restore(key); - - DebugP_log1("Power: release constraint (%d)", constraintId); - } - - return (status); -} - -/* - * ======== Power_releaseDependency ======== - * Release a previously declared dependency. - */ -int_fast16_t Power_releaseDependency(uint_fast16_t resourceId) -{ - int_fast16_t status = Power_SOK; - uint8_t count; - uint32_t id; - uintptr_t key; - - /* first check that resourceId is valid */ - if (resourceId >= PowerCC32XX_NUMRESOURCES) { - status = Power_EINVALIDINPUT; - } - - /* if resourceId is OK ... */ - else { - - /* disable interrupts */ - key = HwiP_disable(); - - /* read the reference count */ - count = PowerCC32XX_module.refCount[resourceId]; - - /* ensure dependency count is not already zero */ - if (count == 0) { - status = Power_EFAIL; - } - - /* if not already zero ... */ - else { - - /* decrement the reference count */ - count--; - - /* if this was the last dependency being released.., */ - if (count == 0) { - /* deactivate this resource ... */ - id = PowerCC32XX_module.dbRecords[resourceId]; - - /* disable clk to peripheral */ - MAP_PRCMPeripheralClkDisable(id, - PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); - } - - /* save the updated count */ - PowerCC32XX_module.refCount[resourceId] = count; - } - - /* restore interrupts */ - HwiP_restore(key); - - DebugP_log1("Power: release dependency (%d)", resourceId); - } - - return (status); -} - -/* - * ======== Power_setConstraint ======== - * Declare an operational constraint. - */ -int_fast16_t Power_setConstraint(uint_fast16_t constraintId) -{ - int_fast16_t status = Power_SOK; - uintptr_t key; - - /* ensure that constraintId is valid */ - if (constraintId >= PowerCC32XX_NUMCONSTRAINTS) { - status = Power_EINVALIDINPUT; - } - - else { - - /* disable interrupts */ - key = HwiP_disable(); - - /* set the specified constraint in the constraintMask */ - PowerCC32XX_module.constraintMask |= 1 << constraintId; - - /* increment the specified constraint count */ - PowerCC32XX_module.constraintCounts[constraintId]++; - - /* restore interrupts */ - HwiP_restore(key); - - DebugP_log1("Power: set constraint (%d)", constraintId); - } - - return (status); -} - -/* - * ======== Power_setDependency ======== - * Declare a dependency upon a resource. - */ -int_fast16_t Power_setDependency(uint_fast16_t resourceId) -{ - int_fast16_t status = Power_SOK; - uint8_t count; - uint32_t id; - uintptr_t key; - - /* ensure resourceId is valid */ - if (resourceId >= PowerCC32XX_NUMRESOURCES) { - status = Power_EINVALIDINPUT; - } - - /* resourceId is OK ... */ - else { - - /* disable interrupts */ - key = HwiP_disable(); - - /* read and increment reference count */ - count = PowerCC32XX_module.refCount[resourceId]++; - - /* if resource was NOT activated previously ... */ - if (count == 0) { - /* now activate this resource ... */ - id = PowerCC32XX_module.dbRecords[resourceId]; - - /* enable the peripheral clock to the resource */ - MAP_PRCMPeripheralClkEnable(id, - PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); - - /* spin here until status returns TRUE */ - while(!MAP_PRCMPeripheralStatusGet(id)) { - } - } - - /* restore interrupts */ - HwiP_restore(key); - DebugP_log1("Power: set dependency (%d)", resourceId); - } - - return (status); -} - -/* - * ======== Power_setPolicy ======== - * Set the Power policy function - */ -void Power_setPolicy(Power_PolicyFxn policy) -{ - PowerCC32XX_module.policyFxn = policy; -} - -/* - * ======== Power_shutdown ======== - */ -int_fast16_t Power_shutdown(uint_fast16_t shutdownState, - uint_fast32_t shutdownTime) -{ - int_fast16_t status = Power_EFAIL; - uint32_t constraints; - uintptr_t hwiKey; - uint64_t counts; - - /* disable interrupts */ - hwiKey = HwiP_disable(); - - /* make sure shutdown request doesn't violate a constraint */ - constraints = Power_getConstraintMask(); - if (constraints & (1 << PowerCC32XX_DISALLOW_SHUTDOWN)) { - status = Power_ECHANGE_NOT_ALLOWED; - } - else { - if (PowerCC32XX_module.state == Power_ACTIVE) { - /* set new transition state to entering shutdown */ - PowerCC32XX_module.state = Power_ENTERING_SHUTDOWN; - - /* signal all clients registered for pre-shutdown notification */ - status = notify(PowerCC32XX_ENTERING_SHUTDOWN); - /* check for timeout or any other error */ - if (status != Power_SOK) { - PowerCC32XX_module.state = Power_ACTIVE; - HwiP_restore(hwiKey); - return (status); - } - /* shutdown the flash */ - PowerCC32XX_shutdownSSPI(); - /* if shutdown wakeup time was configured to be large enough */ - if (shutdownTime > (PowerCC32XX_TOTALTIMESHUTDOWN / 1000)) { - /* calculate the wakeup time for hibernate in RTC counts */ - counts = - (((uint64_t)(shutdownTime - - (PowerCC32XX_TOTALTIMESHUTDOWN / 1000)) - * 32768) / 1000); - - /* set the hibernate wakeup time */ - MAP_PRCMHibernateIntervalSet(counts); - - /* enable the wake source to be RTC */ - MAP_PRCMHibernateWakeupSourceEnable(PRCM_HIB_SLOW_CLK_CTR); - } - - /* enable IO retention */ - if (PowerCC32XX_config.ioRetentionShutdown) { - MAP_PRCMIORetentionEnable( - PowerCC32XX_config.ioRetentionShutdown); - } - - DebugP_log2( - "Power: entering shutdown state (%d), shutdownTime (%d)", - shutdownState, shutdownTime); - - /* enter hibernate - we should never return from here */ - MAP_PRCMHibernateEnter(); - } - else { - status = Power_EBUSY; - } - } - - /* set state to Power_ACTIVE */ - PowerCC32XX_module.state = Power_ACTIVE; - - /* re-enable interrupts */ - HwiP_restore(hwiKey); - - /* if get here, failed to shutdown, return error code */ - return (status); -} - -/* - * ======== Power_sleep ======== - */ -int_fast16_t Power_sleep(uint_fast16_t sleepState) -{ - int_fast16_t status = Power_SOK; - //uint32_t romMajorVer; - //uint32_t romMinorVer; - uint32_t preEvent; - uint32_t postEvent; - uint32_t semBits; - //bool earlyPG = true; - - /* first validate the sleep state */ - if (sleepState != PowerCC32XX_LPDS) { - status = Power_EINVALIDINPUT; - } - - else if (PowerCC32XX_module.state == Power_ACTIVE) { - - /* set transition state to entering sleep */ - PowerCC32XX_module.state = Power_ENTERING_SLEEP; - - /* setup sleep vars */ - preEvent = PowerCC32XX_ENTERING_LPDS; - postEvent = PowerCC32XX_AWAKE_LPDS; - - /* signal all clients registered for pre-sleep notification */ - status = notify(preEvent); - - /* check for timeout or any other error */ - if (status != Power_SOK) { - PowerCC32XX_module.state = Power_ACTIVE; - return (status); - } - - DebugP_log1("Power: sleep, sleepState (%d)", sleepState); - - /* invoke specific sequence to activate LPDS ...*/ - - /* enable RAM retention */ - MAP_PRCMSRAMRetentionEnable( - PowerCC32XX_config.ramRetentionMaskLPDS, - PRCM_SRAM_LPDS_RET); - - /* call the enter LPDS hook function if configured */ - if (PowerCC32XX_config.enterLPDSHookFxn != NULL) { - (*(PowerCC32XX_config.enterLPDSHookFxn))(); - } - - /* park pins, based upon board file definitions */ - if (PowerCC32XX_config.pinParkDefs != NULL) { - parkPins(); - } - - /* save the NVIC registers */ - saveNVICRegs(); - - /* check if PG >= 2.01 */ - /*romMajorVer = HWREG(0x00000400) & 0xFFFF; - romMinorVer = HWREG(0x00000400) >> 16; - if ((romMajorVer >= 3) || ((romMajorVer == 2) && (romMinorVer >= 1))) { - earlyPG = false; - }*/ - - /* call sync barrier */ - SYNCBARRIER(); - - /* now enter LPDS - function does not return... */ -// TODO:Uncomment -#if 0 - if (PowerCC32XX_config.keepDebugActiveDuringLPDS == TRUE) { - if (earlyPG) { - PowerCC32XX_enterLPDS(PRCMLPDSEnterKeepDebugIf); - } - else { - PowerCC32XX_enterLPDS(ROM_PRCMLPDSEnterKeepDebugIfDirect); - } - } - else { - if (earlyPG) { - PowerCC32XX_enterLPDS(PRCMLPDSEnter); - } - else { - PowerCC32XX_enterLPDS(ROM_PRCMLPDSEnterDirect); - } - } -#endif - /* return here after reset, from Power_resumeLPDS() */ - - /* restore NVIC registers */ - restoreNVICRegs(); - - /* restore clock to those peripherals with dependecy set */ - restorePeriphClocks(); - - /* call PRCMCC3200MCUInit() for any necessary post-LPDS restore */ - MAP_PRCMCC3200MCUInit(); - - /* take the GPIO semaphore bits for the MCU */ - semBits = HWREG(0x400F703C); - semBits = (semBits & ~0x3FF) | 0x155; - HWREG(0x400F703C) = semBits; - - /* call the resume LPDS hook function if configured */ - if (PowerCC32XX_config.resumeLPDSHookFxn != NULL) { - (*(PowerCC32XX_config.resumeLPDSHookFxn))(); - } - - /* re-enable Slow Clock Counter Interrupt */ - MAP_PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR); - - /* set transition state to EXITING_SLEEP */ - PowerCC32XX_module.state = Power_EXITING_SLEEP; - - /* - * signal clients registered for post-sleep notification; for example, - * a driver that needs to reinitialize its peripheral state, that was - * lost during LPDS - */ - status = notify(postEvent); - - /* restore pins parked before LPDS to their previous states */ - if (PowerCC32XX_config.pinParkDefs != NULL) { - restoreParkedPins(); - } - - /* if wake source was GPIO, optionally call wakeup function */ - if (MAP_PRCMLPDSWakeupCauseGet() == PRCM_LPDS_GPIO) { - if (PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS != NULL) { - (*(PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS)) - (PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg); - } - } - - /* now clear the transition state before re-enabling scheduler */ - PowerCC32XX_module.state = Power_ACTIVE; - } - else { - status = Power_EBUSY; - } - - return (status); -} - -/* - * ======== Power_unregisterNotify ======== - * Unregister for a power notification. - * - */ -void Power_unregisterNotify(Power_NotifyObj * pNotifyObj) -{ - uintptr_t key; - - /* disable interrupts */ - key = HwiP_disable(); - - /* remove notify object from its event queue */ - List_remove(&PowerCC32XX_module.notifyList, (List_Elem *)pNotifyObj); - - /* re-enable interrupts */ - HwiP_restore(key); - - DebugP_log1("Power: unregister notify (%p)", (uintptr_t) pNotifyObj); -} - -/*********************** CC32XX-specific functions **************************/ - -/* - * ======== PowerCC32XX_configureWakeup ======== - * Configure LPDS and shutdown wakeups; copy settings into driver state - */ -void PowerCC32XX_configureWakeup(PowerCC32XX_Wakeup *wakeup) -{ - /* configure network (Host IRQ) as wakeup source for LPDS */ - if (wakeup->enableNetworkWakeupLPDS) { - MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_HOST_IRQ); - } - else { - MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_HOST_IRQ); - } - PowerCC32XX_module.wakeupConfig.enableNetworkWakeupLPDS = - wakeup->enableNetworkWakeupLPDS; - - /* configure GPIO as wakeup source for LPDS */ - if (wakeup->enableGPIOWakeupLPDS) { - MAP_PRCMLPDSWakeUpGPIOSelect( - wakeup->wakeupGPIOSourceLPDS, - wakeup->wakeupGPIOTypeLPDS); - MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_GPIO); - } - else { - MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_GPIO); - } - PowerCC32XX_module.wakeupConfig.enableGPIOWakeupLPDS = - wakeup->enableGPIOWakeupLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceLPDS = - wakeup->wakeupGPIOSourceLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeLPDS = - wakeup->wakeupGPIOTypeLPDS; - - /* configure GPIO as wakeup source for Shutdown */ - if (wakeup->enableGPIOWakeupShutdown) { - MAP_PRCMHibernateWakeUpGPIOSelect( - wakeup->wakeupGPIOSourceShutdown, - wakeup->wakeupGPIOTypeShutdown); - MAP_PRCMHibernateWakeupSourceEnable( - wakeup->wakeupGPIOSourceShutdown); - } - else { - MAP_PRCMHibernateWakeupSourceDisable( - wakeup->wakeupGPIOSourceShutdown); - } - PowerCC32XX_module.wakeupConfig.enableGPIOWakeupShutdown = - wakeup->enableGPIOWakeupShutdown; - PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceShutdown = - wakeup->wakeupGPIOSourceShutdown; - PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeShutdown = - wakeup->wakeupGPIOTypeShutdown; - - /* copy the LPDS GPIO wakeup function and arg to module state */ - PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS = - wakeup->wakeupGPIOFxnLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg = - wakeup->wakeupGPIOFxnLPDSArg; -} - -/* - * ======== PowerCC32XX_disableIORetention ======== - * Disable IO retention and unlock pins after exit from Shutdown - */ -void PowerCC32XX_disableIORetention(unsigned long groupFlags) -{ - MAP_PRCMIORetentionDisable(groupFlags); -} - -/* - * ======== PowerCC32XX_getParkState ======== - * Get the current LPDS park state for a pin - */ -PowerCC32XX_ParkState PowerCC32XX_getParkState(PowerCC32XX_Pin pin) -{ - PowerCC32XX_ParkInfo parkInfo; - PowerCC32XX_ParkState state = PowerCC32XX_DONT_PARK; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* step thru the pin park array until find the pin */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* if this is the pin to be checked... */ - if (parkInfo.pin == pin) { - state = (PowerCC32XX_ParkState) parkInfo.parkState; - break; - } - } - - return (state); -} - -/* - * ======== PowerCC32XX_getWakeup ======== - * Get the current LPDS and shutdown wakeup configuration - */ -void PowerCC32XX_getWakeup(PowerCC32XX_Wakeup *wakeup) -{ - *wakeup = PowerCC32XX_module.wakeupConfig; -} - -/* - * ======== PowerCC32XX_parkPin ======== - * Park a device pin in preparation for LPDS - */ -void PowerCC32XX_parkPin(PowerCC32XX_Pin pin, PowerCC32XX_ParkState parkState, - uint32_t * previousType, uint16_t * previousDirection) -{ - unsigned long strength; - unsigned long type; - - /* get the current pin configuration */ - MAP_PinConfigGet(pin, &strength, &type); - - /* stash the current pin type */ - *previousType = type; - - /* get and stash the current pin direction */ - *previousDirection = (uint16_t)MAP_PinDirModeGet(pin); - - /* set pin type to the parking state */ - MAP_PinConfigSet(pin, strength, (unsigned long) parkState); - - /* set pin direction to input to HiZ the pin */ - MAP_PinDirModeSet(pin, PIN_DIR_MODE_IN); -} - -/* - * ======== PowerCC32XX_restoreParkedPin ======== - * Restore a pin that was previously parked with PowerCC32XX_parkPin - */ -void PowerCC32XX_restoreParkedPin(PowerCC32XX_Pin pin, uint32_t type, - uint16_t direction) -{ - unsigned long strength; - unsigned long currentType; - - /* get the current pin configuration */ - MAP_PinConfigGet(pin, &strength, ¤tType); - - /* restore the pin type */ - MAP_PinConfigSet(pin, strength, type); - - /* restore the pin direction */ - MAP_PinDirModeSet(pin, (unsigned long)direction); -} - -/* - * ======== PowerCC32XX_restoreParkState ======== - * Restore the LPDS park state for a pin - */ -void PowerCC32XX_restoreParkState(PowerCC32XX_Pin pin, - PowerCC32XX_ParkState state) -{ - PowerCC32XX_ParkInfo parkInfo; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* step thru the park array until find the pin to be updated */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* if this is the pin to be restored... */ - if (parkInfo.pin == pin) { - parkInfo.parkState = state; - PowerCC32XX_config.pinParkDefs[i] = parkInfo; - break; - } - } -} - -/* - * ======== PowerCC32XX_setParkState ======== - * Set a new LPDS park state for a pin - */ -void PowerCC32XX_setParkState(PowerCC32XX_Pin pin, uint32_t level) -{ - PowerCC32XX_ParkInfo parkInfo; - PowerCC32XX_ParkState state; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* first check if level indicates "don't park" */ - if (level == (uint32_t)~1) { - state = PowerCC32XX_DONT_PARK; - } - - /* else, check device revision to choose park state */ - /* if ES2.00 or later, drive the pin */ - else if((HWREG(0x00000400) & 0xFFFF) >= 2) { - state = (level) ? PowerCC32XX_DRIVE_HIGH : PowerCC32XX_DRIVE_LOW; - } - /* else, for earlier devices use the weak pull resistor */ - else { - state = (level) ? PowerCC32XX_WEAK_PULL_UP_STD : - PowerCC32XX_WEAK_PULL_DOWN_STD; - } - - /* step thru the park array until find the pin to be updated */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* if this is the pin to be updated... */ - if (parkInfo.pin == pin) { - parkInfo.parkState = state; - PowerCC32XX_config.pinParkDefs[i] = parkInfo; - break; - } - } -} - -/* - * ======== PowerCC32XX_shutdownSSPI ======== - * Put SPI flash into Deep Power Down mode - */ -void PowerCC32XX_shutdownSSPI(void) -{ - unsigned long status = 0; - - /* Acquire SSPI HwSpinlock. */ - if (0 != MAP_HwSpinLockTryAcquire(HWSPINLOCK_SSPI, PowerCC32XX_SSPISemaphoreTakeTries)){ - return; - } - - /* Enable clock for SSPI module */ - MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK); - - /* Reset SSPI at PRCM level and wait for reset to complete */ - MAP_PRCMPeripheralReset(PRCM_SSPI); - while(MAP_PRCMPeripheralStatusGet(PRCM_SSPI)== false){ - } - - /* Reset SSPI at module level */ - MAP_SPIReset(SSPI_BASE); - - /* Configure SSPI module */ - MAP_SPIConfigSetExpClk(SSPI_BASE,PRCMPeripheralClockGet(PRCM_SSPI), - 20000000,SPI_MODE_MASTER,SPI_SUB_MODE_0, - (SPI_SW_CTRL_CS | - SPI_4PIN_MODE | - SPI_TURBO_OFF | - SPI_CS_ACTIVELOW | - SPI_WL_8)); - - /* Enable SSPI module */ - MAP_SPIEnable(SSPI_BASE); - - /* Allow settling before enabling chip select */ - uSEC_DELAY(PowerCC32XX_SSPICSDelay); - - /* Enable chip select for the spi flash. */ - MAP_SPICSEnable(SSPI_BASE); - - /* Wait for spi flash. */ - do{ - /* Send status register read instruction and read back a dummy byte. */ - MAP_SPIDataPut(SSPI_BASE,PowerCC32XX_SSPIReadStatusInstruction); - MAP_SPIDataGet(SSPI_BASE,&status); - - /* Write a dummy byte then read back the actual status. */ - MAP_SPIDataPut(SSPI_BASE,0xFF); - MAP_SPIDataGet(SSPI_BASE,&status); - } while((status & 0xFF )== STATUS_BUSY); - - /* Disable chip select for the spi flash. */ - MAP_SPICSDisable(SSPI_BASE); - - /* Start another CS enable sequence for Power down command. */ - MAP_SPICSEnable(SSPI_BASE); - - /* Send Deep Power Down command to spi flash */ - MAP_SPIDataPut(SSPI_BASE,PowerCC32XX_SSPIPowerDownInstruction); - - /* Disable chip select for the spi flash. */ - MAP_SPICSDisable(SSPI_BASE); - - /* Release SSPI HwSpinlock. */ - MAP_HwSpinLockRelease(HWSPINLOCK_SSPI); - - return; -} - -/* - * ======== PowerCC32XX_reset ======== - * Software reset of specific peripheral. - */ -int_fast16_t PowerCC32XX_reset(uint_fast16_t resourceId) -{ - int_fast16_t status = Power_SOK; - uint32_t id; - - /* Ensure resourceId is valid */ - if (resourceId >= PowerCC32XX_NUMRESOURCES) { - status = Power_EINVALIDINPUT; - } - - /* resourceId is OK ... */ - else { - - id = PowerCC32XX_module.dbRecords[resourceId]; - /* Reset the peripheral */ - MAP_PRCMPeripheralReset(id); - } - return (status); -} - -/*************************internal functions ****************************/ - -/* - * ======== notify ======== - * Note: When this function is called hardware interrupts are disabled - */ -static int_fast16_t notify(uint_fast16_t eventType) -{ - int_fast16_t notifyStatus; - Power_NotifyFxn notifyFxn; - uintptr_t clientArg; - List_Elem *elem; - - /* if queue is empty, return immediately */ - if (!List_empty(&PowerCC32XX_module.notifyList)) { - /* point to first client notify object */ - elem = List_head(&PowerCC32XX_module.notifyList); - - /* walk the queue and notify each registered client of the event */ - do { - if (((Power_NotifyObj *)elem)->eventTypes & eventType) { - /* pull params from notify object */ - notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; - clientArg = ((Power_NotifyObj *)elem)->clientArg; - - /* call the client's notification function */ - notifyStatus = (int_fast16_t) (*(Power_NotifyFxn)notifyFxn)( - eventType, 0, clientArg); - - /* if client declared error stop all further notifications */ - if (notifyStatus != Power_NOTIFYDONE) { - return (Power_EFAIL); - } - } - - /* get next element in the notification queue */ - elem = List_next(elem); - - } while (elem != NULL); - } - - return (Power_SOK); -} - -/* - * ======== restoreNVICRegs ======== - * Restore the NVIC registers - */ -static void restoreNVICRegs(void) -{ - uint32_t i; - uint32_t *base_reg_addr; - - /* Restore the NVIC control registers */ - HWREG(NVIC_VTABLE) = PowerCC32XX_contextSave.nvicRegs.vectorTable; - HWREG(NVIC_ACTLR) = PowerCC32XX_contextSave.nvicRegs.auxCtrl; - HWREG(NVIC_APINT) = PowerCC32XX_contextSave.nvicRegs.appInt; - HWREG(NVIC_INT_CTRL) = PowerCC32XX_contextSave.nvicRegs.intCtrlState; - HWREG(NVIC_SYS_CTRL) = PowerCC32XX_contextSave.nvicRegs.sysCtrl; - HWREG(NVIC_CFG_CTRL) = PowerCC32XX_contextSave.nvicRegs.configCtrl; - HWREG(NVIC_SYS_PRI1) = PowerCC32XX_contextSave.nvicRegs.sysPri1; - HWREG(NVIC_SYS_PRI2) = PowerCC32XX_contextSave.nvicRegs.sysPri2; - HWREG(NVIC_SYS_PRI3) = PowerCC32XX_contextSave.nvicRegs.sysPri3; - HWREG(NVIC_SYS_HND_CTRL) = PowerCC32XX_contextSave.nvicRegs.sysHcrs; - - /* Systick registers */ - HWREG(NVIC_ST_CTRL) = PowerCC32XX_contextSave.nvicRegs.systickCtrl; - HWREG(NVIC_ST_RELOAD) = PowerCC32XX_contextSave.nvicRegs.systickReload; - HWREG(NVIC_ST_CAL) = PowerCC32XX_contextSave.nvicRegs.systickCalib; - - /* Restore the interrupt priority registers */ - base_reg_addr = (uint32_t *)NVIC_PRI0; - for(i = 0; i < PowerCC32XX_numNVICIntPriority; i++) { - base_reg_addr[i] = PowerCC32XX_contextSave.nvicRegs.intPriority[i]; - } - - /* Restore the interrupt enable registers */ - base_reg_addr = (uint32_t *)NVIC_EN0; - for(i = 0; i < PowerCC32XX_numNVICSetEnableRegs; i++) { - base_reg_addr[i] = PowerCC32XX_contextSave.nvicRegs.intSetEn[i]; - } - - /* Data and instruction sync barriers */ - SYNCBARRIER(); -} - -/* - * ======== restorePeriphClocks ======== - * Restores the peripheral clocks that had dependency set - */ -static void restorePeriphClocks(void) -{ - uint32_t dependCount; - uint32_t i; - - /* need to re-enable peripheral clocks to those with set dependency */ - for (i = 0; i < PowerCC32XX_NUMRESOURCES; i++) { - dependCount = Power_getDependencyCount(i); - if (dependCount > 0) { - MAP_PRCMPeripheralClkEnable(PowerCC32XX_module.dbRecords[i], - PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); - - while(!MAP_PRCMPeripheralStatusGet(PowerCC32XX_module.dbRecords[i])) { - } - } - } -} - -/* - * ======== saveNVICRegs ======== - * Save away the NVIC registers for LPDS mode. - */ -static void saveNVICRegs(void) -{ - uint32_t i; - uint32_t *base_reg_addr; - - /* Save the NVIC control registers */ - PowerCC32XX_contextSave.nvicRegs.vectorTable = HWREG(NVIC_VTABLE); - PowerCC32XX_contextSave.nvicRegs.auxCtrl = HWREG(NVIC_ACTLR); - PowerCC32XX_contextSave.nvicRegs.intCtrlState = HWREG(NVIC_INT_CTRL); - PowerCC32XX_contextSave.nvicRegs.appInt = HWREG(NVIC_APINT); - PowerCC32XX_contextSave.nvicRegs.sysCtrl = HWREG(NVIC_SYS_CTRL); - PowerCC32XX_contextSave.nvicRegs.configCtrl = HWREG(NVIC_CFG_CTRL); - PowerCC32XX_contextSave.nvicRegs.sysPri1 = HWREG(NVIC_SYS_PRI1); - PowerCC32XX_contextSave.nvicRegs.sysPri2 = HWREG(NVIC_SYS_PRI2); - PowerCC32XX_contextSave.nvicRegs.sysPri3 = HWREG(NVIC_SYS_PRI3); - PowerCC32XX_contextSave.nvicRegs.sysHcrs = HWREG(NVIC_SYS_HND_CTRL); - - /* Systick registers */ - PowerCC32XX_contextSave.nvicRegs.systickCtrl = HWREG(NVIC_ST_CTRL); - PowerCC32XX_contextSave.nvicRegs.systickReload = HWREG(NVIC_ST_RELOAD); - PowerCC32XX_contextSave.nvicRegs.systickCalib = HWREG(NVIC_ST_CAL); - - /* Save the interrupt enable registers */ - base_reg_addr = (uint32_t *)NVIC_EN0; - for (i = 0; i < PowerCC32XX_numNVICSetEnableRegs; i++) { - PowerCC32XX_contextSave.nvicRegs.intSetEn[i] = base_reg_addr[i]; - } - - /* Save the interrupt priority registers */ - base_reg_addr = (uint32_t *)NVIC_PRI0; - for (i = 0; i < PowerCC32XX_numNVICIntPriority; i++) { - PowerCC32XX_contextSave.nvicRegs.intPriority[i] = base_reg_addr[i]; - } -} - -/* - * ======== parkPins ======== - */ -static void parkPins(void) -{ - PowerCC32XX_ParkInfo parkInfo; - uint32_t antpadreg; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* for each pin in the park array ... */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* skip this pin if "don't park" is specified */ - if (parkInfo.parkState == PowerCC32XX_DONT_PARK) { - continue; - } - - /* if this is a special antenna select pin, stash current pad state */ - if (parkInfo.pin == PowerCC32XX_PIN29) { - antpadreg = 0x4402E108; - PowerCC32XX_module.stateAntPin29 = (uint16_t) HWREG(antpadreg); - } - else if (parkInfo.pin == PowerCC32XX_PIN30) { - antpadreg = 0x4402E10C; - PowerCC32XX_module.stateAntPin30 = (uint16_t) HWREG(antpadreg); - } - else { - antpadreg = 0; - } - - /* if this is antenna select pin, park via direct writes to pad reg */ - if (antpadreg != 0) { - HWREG(antpadreg) &= 0xFFFFF0EF; /* first clear bits 4, 8-11 */ - if (parkInfo.parkState == PowerCC32XX_NO_PULL_HIZ) { - HWREG(antpadreg) |= 0x00000C00; - } - else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_UP_STD) { - HWREG(antpadreg) |= 0x00000D00; - } - else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_DOWN_STD) { - HWREG(antpadreg) |= 0x00000E00; - } - else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_UP_OPENDRAIN) { - HWREG(antpadreg) |= 0x00000D10; - } - else if (parkInfo.parkState == - PowerCC32XX_WEAK_PULL_DOWN_OPENDRAIN) { - HWREG(antpadreg) |= 0x00000E10; - } - } - - /* else, for all other pins */ - else { - - /* if pin is NOT to be driven, park it to the specified state... */ - if ((parkInfo.parkState != PowerCC32XX_DRIVE_LOW) && - (parkInfo.parkState != PowerCC32XX_DRIVE_HIGH)) { - - PowerCC32XX_parkPin( - (PowerCC32XX_Pin)parkInfo.pin, - (PowerCC32XX_ParkState)parkInfo.parkState, - &PowerCC32XX_module.pinType[i], - &PowerCC32XX_module.pinDir[i]); - } - - /* - * else, now check if the pin CAN be driven (pins 45, 53, and 55 - * can't be driven) - */ - else if ((parkInfo.pin != PowerCC32XX_PIN45) && - (parkInfo.pin != PowerCC32XX_PIN53) && - (parkInfo.pin != PowerCC32XX_PIN55)){ - - /* - * must ensure pin mode is zero; first get/stash current mode, - * then set mode to zero - */ - PowerCC32XX_module.pinMode[i] = - (uint8_t)MAP_PinModeGet(parkInfo.pin); - MAP_PinModeSet(parkInfo.pin, 0); - - /* if pin is to be driven low, set the lock level to 0 */ - if (parkInfo.parkState == PowerCC32XX_DRIVE_LOW) { - MAP_PinLockLevelSet((PowerCC32XX_Pin)parkInfo.pin, 0); - PowerCC32XX_module.pinLockMask |= 1 << - PinToPadGet(parkInfo.pin); - } - - /* else, pin to be driven high, set lock level to 1 */ - else { - MAP_PinLockLevelSet((PowerCC32XX_Pin)parkInfo.pin, 1); - PowerCC32XX_module.pinLockMask |= 1 << - PinToPadGet(parkInfo.pin); - } - } - } - } - - /* if any pins are to be driven, lock them now */ - if (PowerCC32XX_module.pinLockMask) { - MAP_PinLock(PowerCC32XX_module.pinLockMask); - } -} - -/* - * ======== restoreParkedPins ======== - */ -static void restoreParkedPins(void) -{ - PowerCC32XX_ParkInfo parkInfo; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* first, unlock any locked pins (that were driven high or low) */ - if (PowerCC32XX_module.pinLockMask) { - MAP_PinUnlock(); - } - - /* now, for each pin in the park array ... */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* skip this pin if "don't park" is specified */ - if (parkInfo.parkState == PowerCC32XX_DONT_PARK) { - continue; - } - - /* if this is special antenna select pin: restore the saved pad state */ - if (parkInfo.pin == PowerCC32XX_PIN29) { - HWREG(0x4402E108) = ((HWREG(0x4402E108) & 0xFFFFF000) | - (PowerCC32XX_module.stateAntPin29 & 0x00000FFF)); - } - - else if (parkInfo.pin == PowerCC32XX_PIN30) { - HWREG(0x4402E10C) = ((HWREG(0x4402E10C) & 0xFFFFF000) | - (PowerCC32XX_module.stateAntPin30 & 0x00000FFF)); - } - - /* else if pin was driven during LPDS, restore the pin mode */ - else if ((parkInfo.parkState == PowerCC32XX_DRIVE_LOW) || - (parkInfo.parkState == PowerCC32XX_DRIVE_HIGH)) { - MAP_PinModeSet(parkInfo.pin, - (unsigned long)PowerCC32XX_module.pinMode[i]); - } - - /* else, restore all others */ - else { - /* if pin parked in a non-driven state, restore type & direction */ - if ((parkInfo.parkState != PowerCC32XX_DRIVE_LOW) && - (parkInfo.parkState != PowerCC32XX_DRIVE_HIGH)) { - - PowerCC32XX_restoreParkedPin( - (PowerCC32XX_Pin)parkInfo.pin, - PowerCC32XX_module.pinType[i], - PowerCC32XX_module.pinDir[i]); - } - } - } -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.h deleted file mode 100755 index 25db541469f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.h +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file PowerCC32XX.h - * - * @brief Power manager interface for the CC32XX - * - * The Power header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref Power.h for a complete description of APIs. - * - * ## Implementation # - * This module defines the power resources, constraints, events, sleep - * states and transition latencies for CC32XX. - * - * A reference power policy is provided which can transition the MCU from the - * active state to one of two sleep states: LPDS or Sleep. - * The policy looks at the estimated idle time remaining, and the active - * constraints, and determine which sleep state to transition to. The - * policy will give first preference to choosing LPDS, but if that is not - * appropriate (e.g., not enough idle time), it will choose Sleep. - * - * ============================================================================ - */ - -#ifndef ti_drivers_power_PowerCC32XX__include -#define ti_drivers_power_PowerCC32XX__include - -#include -#include -#include - -/* driverlib header files */ -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* latency values were measured with a logic analyzer, and rounded up */ - -/*! The latency to reserve for resuming from LPDS (usec) */ -#define PowerCC32XX_RESUMETIMELPDS 2500 - -/*! The total latency to reserve for entry to and exit from LPDS (usec) */ -#define PowerCC32XX_TOTALTIMELPDS 20000 - -/*! The total latency to reserve for entry to and exit from Shutdown (usec) */ -#define PowerCC32XX_TOTALTIMESHUTDOWN 500000 - -/* Power resources */ -#define PowerCC32XX_PERIPH_CAMERA 0 -/*!< Resource ID: Camera */ - -#define PowerCC32XX_PERIPH_I2S 1 -/*!< Resource ID: I2S */ - -#define PowerCC32XX_PERIPH_SDHOST 2 -/*!< Resource ID: SDHost */ - -#define PowerCC32XX_PERIPH_GSPI 3 -/*!< Resource ID: General Purpose SPI (GSPI) */ - -#define PowerCC32XX_PERIPH_LSPI 4 -/*!< Resource ID: LSPI */ - -#define PowerCC32XX_PERIPH_UDMA 5 -/*!< Resource ID: uDMA Controller */ - -#define PowerCC32XX_PERIPH_GPIOA0 6 -/*!< Resource ID: General Purpose I/O Port A0 */ - -#define PowerCC32XX_PERIPH_GPIOA1 7 -/*!< Resource ID: General Purpose I/O Port A1 */ - -#define PowerCC32XX_PERIPH_GPIOA2 8 -/*!< Resource ID: General Purpose I/O Port A2 */ - -#define PowerCC32XX_PERIPH_GPIOA3 9 -/*!< Resource ID: General Purpose I/O Port A3 */ - -#define PowerCC32XX_PERIPH_GPIOA4 10 -/*!< Resource ID: General Purpose I/O Port A4 */ - -#define PowerCC32XX_PERIPH_WDT 11 -/*!< Resource ID: Watchdog module */ - -#define PowerCC32XX_PERIPH_UARTA0 12 -/*!< Resource ID: UART 0 */ - -#define PowerCC32XX_PERIPH_UARTA1 13 -/*!< Resource ID: UART 1 */ - -#define PowerCC32XX_PERIPH_TIMERA0 14 -/*!< Resource ID: General Purpose Timer A0 */ - -#define PowerCC32XX_PERIPH_TIMERA1 15 -/*!< Resource ID: General Purpose Timer A1 */ - -#define PowerCC32XX_PERIPH_TIMERA2 16 -/*!< Resource ID: General Purpose Timer A2 */ - -#define PowerCC32XX_PERIPH_TIMERA3 17 -/*!< Resource ID: General Purpose Timer A3 */ - -#define PowerCC32XX_PERIPH_DTHE 18 -/*!< Resource ID: Cryptography Accelerator (DTHE) */ - -#define PowerCC32XX_PERIPH_SSPI 19 -/*!< Resource ID: Serial Flash SPI (SSPI) */ - -#define PowerCC32XX_PERIPH_I2CA0 20 -/*!< Resource ID: I2C */ - -/* \cond */ -#define PowerCC32XX_NUMRESOURCES 21 /* Number of resources in database */ -/* \endcond */ - -/* - * Power constraints on the CC32XX device - */ -#define PowerCC32XX_DISALLOW_LPDS 0 -/*!< Constraint: Disallow entry to Low Power Deep Sleep (LPDS) */ - -#define PowerCC32XX_DISALLOW_SHUTDOWN 1 -/*!< Constraint: Disallow entry to Shutdown */ - -/* \cond */ -#define PowerCC32XX_NUMCONSTRAINTS 2 /*!< number of constraints */ -/* \endcond */ - -/* - * Power events on the CC32XX device - * - * Each event must be a power of two, and the event IDs must be sequential - * without any gaps. - */ -#define PowerCC32XX_ENTERING_LPDS 0x1 -/*!< Power event: The device is entering the LPDS sleep state */ - -#define PowerCC32XX_ENTERING_SHUTDOWN 0x2 -/*!< Power event: The device is entering the Shutdown state */ - -#define PowerCC32XX_AWAKE_LPDS 0x4 -/*!< Power event: The device is waking from the LPDS sleep state */ - -/* \cond */ -#define PowerCC32XX_NUMEVENTS 3 /*!< number of events */ -/* \endcond */ - -/* Power sleep states */ -#define PowerCC32XX_LPDS 0x1 /*!< The LPDS sleep state */ - -/* \cond */ -/* Use by NVIC Register structure */ -#define PowerCC32XX_numNVICSetEnableRegs 6 -#define PowerCC32XX_numNVICIntPriority 49 -/* \endcond */ - -/* \cond */ -/* Number of pins that can be parked in LPDS */ -#define PowerCC32XX_NUMPINS 34 -/* \endcond */ - -/*! @brief Used to specify parking of a pin during LPDS */ -typedef struct PowerCC32XX_ParkInfo { - uint32_t pin; - /*!< The pin to be parked */ - uint32_t parkState; - /*!< The state to park the pin (an enumerated PowerCC32XX_ParkState) */ -} PowerCC32XX_ParkInfo; - -/*! @brief Power global configuration */ -typedef struct PowerCC32XX_ConfigV1 { - /*! Initialization function for the power policy */ - Power_PolicyInitFxn policyInitFxn; - /*! The power policy function */ - Power_PolicyFxn policyFxn; - /*! - * @brief Hook function called before entering LPDS - * - * This function is called after any notifications are complete, - * and before any pins are parked, just before entry to LPDS. - */ - void (*enterLPDSHookFxn)(void); - /*! - * @brief Hook function called when resuming from LPDS - * - * This function is called early in the wake sequence, before any - * notification functions are run. - */ - void (*resumeLPDSHookFxn)(void); - /*! Determines whether to run the power policy function */ - bool enablePolicy; - /*! Enable GPIO as a wakeup source for LPDS */ - bool enableGPIOWakeupLPDS; - /*! Enable GPIO as a wakeup source for shutdown */ - bool enableGPIOWakeupShutdown; - /*! Enable Network activity as a wakeup source for LPDS */ - bool enableNetworkWakeupLPDS; - /*! - * @brief The GPIO source for wakeup from LPDS - * - * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source - * for LPDS. The GPIO must be specified as one of the following (as - * defined in driverlib/prcm.h): PRCM_LPDS_GPIO2, PRCM_LPDS_GPIO4, - * PRCM_LPDS_GPIO11, PRCM_LPDS_GPIO13, PRCM_LPDS_GPIO17, PRCM_LPDS_GPIO24, - * PRCM_LPDS_GPIO26 - */ - uint32_t wakeupGPIOSourceLPDS; - /*! - * @brief The GPIO trigger type for wakeup from LPDS - * - * Value can be one of the following (defined in driverlib/prcm.h): - * PRCM_LPDS_LOW_LEVEL, PRCM_LPDS_HIGH_LEVEL, - * PRCM_LPDS_FALL_EDGE, PRCM_LPDS_RISE_EDGE - */ - uint32_t wakeupGPIOTypeLPDS; - /*! - * @brief Function to be called when the configured GPIO triggers wakeup - * from LPDS - * - * During LPDS the internal GPIO module is powered off, and special - * periphery logic is used instead to detect the trigger and wake the - * device. No GPIO interrupt service routine will be triggered in this - * case (even if an ISR is configured, and used normally to detect GPIO - * interrupts when not in LPDS). This function can be used in lieu of a - * GPIO ISR, to take specific action upon LPDS wakeup. - * - * A value of NULL indicates no GPIO wakeup function will be called. - * - * An argument for this wakeup function can be specified via - * wakeupGPIOFxnLPDSArg. - * - * Note that this wakeup function will be called as one of the last steps - * in Power_sleep(), after all notifications have been sent out, and after - * pins have been restored to their previous (non-parked) states. - */ - void (*wakeupGPIOFxnLPDS)(uint_least8_t argument); - /*! - * @brief The argument to be passed to wakeupGPIOFxnLPDS() - */ - uint_least8_t wakeupGPIOFxnLPDSArg; - /*! - * @brief The GPIO sources for wakeup from shutdown - * - * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source - * for Shutdown. The GPIO must be specified as one of the following (as - * defined in driverlib/prcm.h): PRCM_HIB_GPIO2, PRCM_HIB_GPIO4, - * PRCM_HIB_GPIO11, PRCM_HIB_GPIO13, PRCM_HIB_GPIO17, PRCM_HIB_GPIO24, - * PRCM_HIB_GPIO26 - */ - uint32_t wakeupGPIOSourceShutdown; - /*! - * @brief The GPIO trigger type for wakeup from shutdown - * - * Value can be one of the following (defined in driverlib/prcm.h): - * PRCM_HIB_LOW_LEVEL, PRCM_HIB_HIGH_LEVEL, - * PRCM_HIB_FALL_EDGE, PRCM_HIB_RISE_EDGE - */ - uint32_t wakeupGPIOTypeShutdown; - /*! - * @brief SRAM retention mask for LPDS - * - * Value can be a mask of the following (defined in driverlib/prcm.h): - * PRCM_SRAM_COL_1, PRCM_SRAM_COL_2, PRCM_SRAM_COL_3, - * PRCM_SRAM_COL_4 - */ - uint32_t ramRetentionMaskLPDS; - /*! - * @brief Keep debug interface active during LPDS - * - * This Boolean controls whether the debug interface will be left active - * when LPDS is entered. For best power savings this flag should be set - * to false. Setting the flag to true will enable better debug - * capability, but will prevent full LPDS, and will result in increased - * power consumption. - */ - bool keepDebugActiveDuringLPDS; - /*! - * @brief IO retention mask for Shutdown - * - * Value can be a mask of the following (defined in driverlib/prcm.h): - * PRCM_IO_RET_GRP_0, PRCM_IO_RET_GRP_1, PRCM_IO_RET_GRP_2 - * PRCM_IO_RET_GRP_3 - */ - uint32_t ioRetentionShutdown; - /*! - * @brief Pointer to an array of pins to be parked during LPDS - * - * A value of NULL will disable parking of any pins during LPDS - */ - PowerCC32XX_ParkInfo * pinParkDefs; - /*! - * @brief Number of pins to be parked during LPDS - */ - uint32_t numPins; -} PowerCC32XX_ConfigV1; - -/*! - * @cond NODOC - * NVIC registers that need to be saved before entering LPDS. - */ -typedef struct PowerCC32XX_NVICRegisters { - uint32_t vectorTable; - uint32_t auxCtrl; - uint32_t intCtrlState; - uint32_t appInt; - uint32_t sysCtrl; - uint32_t configCtrl; - uint32_t sysPri1; - uint32_t sysPri2; - uint32_t sysPri3; - uint32_t sysHcrs; - uint32_t systickCtrl; - uint32_t systickReload; - uint32_t systickCalib; - uint32_t intSetEn[PowerCC32XX_numNVICSetEnableRegs]; - uint32_t intPriority[PowerCC32XX_numNVICIntPriority]; -} PowerCC32XX_NVICRegisters; -/*! @endcond */ - -/*! - * @cond NODOC - * MCU core registers that need to be save before entering LPDS. - */ -typedef struct PowerCC32XX_MCURegisters { - uint32_t msp; - uint32_t psp; - uint32_t psr; - uint32_t primask; - uint32_t faultmask; - uint32_t basepri; - uint32_t control; -} PowerCC32XX_MCURegisters; -/*! @endcond */ - -/*! - * @cond NODOC - * Structure of context registers to save before entering LPDS. - */ -typedef struct PowerCC32XX_SaveRegisters { - PowerCC32XX_MCURegisters m4Regs; - PowerCC32XX_NVICRegisters nvicRegs; -} PowerCC32XX_SaveRegisters; -/*! @endcond */ - -/*! @brief Enumeration of states a pin can be parked in */ -typedef enum { - /*! No pull resistor, leave pin in a HIZ state */ - PowerCC32XX_NO_PULL_HIZ = PIN_TYPE_STD, - /*! Pull-up resistor for standard pin type */ - PowerCC32XX_WEAK_PULL_UP_STD = PIN_TYPE_STD_PU, - /*! Pull-down resistor for standard pin type */ - PowerCC32XX_WEAK_PULL_DOWN_STD = PIN_TYPE_STD_PD, - /*! Pull-up resistor for open drain pin type */ - PowerCC32XX_WEAK_PULL_UP_OPENDRAIN = PIN_TYPE_OD_PU, - /*! Pull-down resistor for open drain pin type */ - PowerCC32XX_WEAK_PULL_DOWN_OPENDRAIN = PIN_TYPE_OD_PD, - /*! Drive pin to a low logic state */ - PowerCC32XX_DRIVE_LOW, - /*! Drive pin to a high logic state */ - PowerCC32XX_DRIVE_HIGH, - /*! Take no action; do not park the pin */ - PowerCC32XX_DONT_PARK -} PowerCC32XX_ParkState; - -/*! @brief Enumeration of pins that can be parked */ -typedef enum { - /*! PIN_01 */ - PowerCC32XX_PIN01 = PIN_01, - /*! PIN_02 */ - PowerCC32XX_PIN02 = PIN_02, - /*! PIN_03 */ - PowerCC32XX_PIN03 = PIN_03, - /*! PIN_04 */ - PowerCC32XX_PIN04 = PIN_04, - /*! PIN_05 */ - PowerCC32XX_PIN05 = PIN_05, - /*! PIN_06 */ - PowerCC32XX_PIN06 = PIN_06, - /*! PIN_07 */ - PowerCC32XX_PIN07 = PIN_07, - /*! PIN_08 */ - PowerCC32XX_PIN08 = PIN_08, - /*! PIN_11 */ - PowerCC32XX_PIN11 = PIN_11, - /*! PIN_12 */ - PowerCC32XX_PIN12 = PIN_12, - /*! PIN_13 */ - PowerCC32XX_PIN13 = PIN_13, - /*! PIN_14 */ - PowerCC32XX_PIN14 = PIN_14, - /*! PIN_15 */ - PowerCC32XX_PIN15 = PIN_15, - /*! PIN_16 */ - PowerCC32XX_PIN16 = PIN_16, - /*! PIN_17 */ - PowerCC32XX_PIN17 = PIN_17, - /*! PIN_18 */ - PowerCC32XX_PIN18 = PIN_18, - /*! PIN_19 */ - PowerCC32XX_PIN19 = PIN_19, - /*! PIN_20 */ - PowerCC32XX_PIN20 = PIN_20, - /*! PIN_21 */ - PowerCC32XX_PIN21 = PIN_21, - /*! PIN_29 */ - PowerCC32XX_PIN29 = 0x1C, - /*! PIN_30 */ - PowerCC32XX_PIN30 = 0x1D, - /*! PIN_45 */ - PowerCC32XX_PIN45 = PIN_45, - /*! PIN_50 */ - PowerCC32XX_PIN50 = PIN_50, - /*! PIN_52 */ - PowerCC32XX_PIN52 = PIN_52, - /*! PIN_53 */ - PowerCC32XX_PIN53 = PIN_53, - /*! PIN_55 */ - PowerCC32XX_PIN55 = PIN_55, - /*! PIN_57 */ - PowerCC32XX_PIN57 = PIN_57, - /*! PIN_58 */ - PowerCC32XX_PIN58 = PIN_58, - /*! PIN_59 */ - PowerCC32XX_PIN59 = PIN_59, - /*! PIN_60 */ - PowerCC32XX_PIN60 = PIN_60, - /*! PIN_61 */ - PowerCC32XX_PIN61 = PIN_61, - /*! PIN_62 */ - PowerCC32XX_PIN62 = PIN_62, - /*! PIN_63 */ - PowerCC32XX_PIN63 = PIN_63, - /*! PIN_64 */ - PowerCC32XX_PIN64 = PIN_64 -} PowerCC32XX_Pin; - -/*! - * @brief Specify the wakeup sources for LPDS and Shutdown - * - * The wakeup sources for LPDS and Shutdown can be dynamically changed - * at runtime, via PowerCC32XX_configureWakeup(). The application - * should fill a structure of this type, and pass it as the parameter - * to PowerCC32XX_configureWakeup() to specify the new wakeup settings. - */ -typedef struct PowerCC32XX_Wakeup { - /*! Enable GPIO as a wakeup source for LPDS */ - bool enableGPIOWakeupLPDS; - /*! Enable GPIO as a wakeup source for shutdown */ - bool enableGPIOWakeupShutdown; - /*! Enable Network activity as a wakeup source for LPDS */ - bool enableNetworkWakeupLPDS; - /*! - * @brief The GPIO source for wakeup from LPDS - * - * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source - * for LPDS. The GPIO must be specified as one of the following (as - * defined in driverlib/prcm.h): PRCM_LPDS_GPIO2, PRCM_LPDS_GPIO4, - * PRCM_LPDS_GPIO11, PRCM_LPDS_GPIO13, PRCM_LPDS_GPIO17, PRCM_LPDS_GPIO24, - * PRCM_LPDS_GPIO26 - */ - uint32_t wakeupGPIOSourceLPDS; - /*! - * @brief The GPIO trigger type for wakeup from LPDS - * - * Value can be one of the following (defined in driverlib/prcm.h): - * PRCM_LPDS_LOW_LEVEL, PRCM_LPDS_HIGH_LEVEL, - * PRCM_LPDS_FALL_EDGE, PRCM_LPDS_RISE_EDGE - */ - uint32_t wakeupGPIOTypeLPDS; - /*! - * @brief Function to be called when the configured GPIO triggers wakeup - * from LPDS - * - * During LPDS the internal GPIO module is powered off, and special - * periphery logic is used instead to detect the trigger and wake the - * device. No GPIO interrupt service routine will be triggered in this - * case (even if an ISR is configured, and used normally to detect GPIO - * interrupts when not in LPDS). This function can be used in lieu of a - * GPIO ISR, to take specific action upon LPDS wakeup. - * - * A value of NULL indicates no GPIO wakeup function will be called. - * - * An argument for this wakeup function can be specified via - * wakeupGPIOFxnLPDSArg. - * - * Note that this wakeup function will be called as one of the last steps - * in Power_sleep(), after all notifications have been sent out, and after - * pins have been restored to their previous (non-parked) states. - */ - void (*wakeupGPIOFxnLPDS)(uint_least8_t argument); - /*! - * @brief The argument to be passed to wakeupGPIOFxnLPDS() - */ - uint_least8_t wakeupGPIOFxnLPDSArg; - /*! - * @brief The GPIO sources for wakeup from shutdown - * - * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source - * for Shutdown. The GPIO must be specified as one of the following (as - * defined in driverlib/prcm.h): PRCM_HIB_GPIO2, PRCM_HIB_GPIO4, - * PRCM_HIB_GPIO11, PRCM_HIB_GPIO13, PRCM_HIB_GPIO17, PRCM_HIB_GPIO24, - * PRCM_HIB_GPIO26 - */ - uint32_t wakeupGPIOSourceShutdown; - /*! - * @brief The GPIO trigger type for wakeup from shutdown - * - * Value can be one of the following (defined in driverlib/prcm.h): - * PRCM_HIB_LOW_LEVEL, PRCM_HIB_HIGH_LEVEL, - * PRCM_HIB_FALL_EDGE, PRCM_HIB_RISE_EDGE - */ - uint32_t wakeupGPIOTypeShutdown; -} PowerCC32XX_Wakeup; - -/*! - * @cond NODOC - * Internal structure defining Power module state. - */ -typedef struct PowerCC32XX_ModuleState { - List_List notifyList; - uint32_t constraintMask; - uint32_t state; - uint16_t dbRecords[PowerCC32XX_NUMRESOURCES]; - bool enablePolicy; - bool initialized; - uint8_t refCount[PowerCC32XX_NUMRESOURCES]; - uint8_t constraintCounts[PowerCC32XX_NUMCONSTRAINTS]; - Power_PolicyFxn policyFxn; - uint32_t pinType[PowerCC32XX_NUMPINS]; - uint16_t pinDir[PowerCC32XX_NUMPINS]; - uint8_t pinMode[PowerCC32XX_NUMPINS]; - uint16_t stateAntPin29; - uint16_t stateAntPin30; - uint32_t pinLockMask; - PowerCC32XX_Wakeup wakeupConfig; -} PowerCC32XX_ModuleState; -/*! @endcond */ - -/*! - * @brief Function configures wakeup for LPDS and shutdown - * - * This function allows the app to configure the GPIO source and - * type for waking up from LPDS and shutdown and the network host - * as a wakeup source for LPDS. This overwrites any previous - * wakeup settings. - * - * @param wakeup Settings applied to wakeup configuration - */ -void PowerCC32XX_configureWakeup(PowerCC32XX_Wakeup *wakeup); - -/*! OS-specific power policy initialization function */ -void PowerCC32XX_initPolicy(void); - -/*! - * @brief Function to get wakeup configuration settings - * - * This function allows an app to query the current LPDS and shutdown - * wakeup configuration settings. - * - * @param wakeup A PowerCC32XX_Wakeup structure to be written into - */ -void PowerCC32XX_getWakeup(PowerCC32XX_Wakeup *wakeup); - -/*! CC32XX-specific function to query the LPDS park state for a pin */ -PowerCC32XX_ParkState PowerCC32XX_getParkState(PowerCC32XX_Pin pin); - -/*! CC32XX-specific function to restore the LPDS park state for a pin */ -void PowerCC32XX_restoreParkState(PowerCC32XX_Pin pin, - PowerCC32XX_ParkState state); - -/*! CC32XX-specific function to dynamically set the LPDS park state for a pin */ -void PowerCC32XX_setParkState(PowerCC32XX_Pin pin, uint32_t level); - -/*! - * @brief Function to disable IO retention and unlock pin groups following - * exit from Shutdown. - * - * PowerCC32XX_ConfigV1.ioRetentionShutdown can be used to specify locking and - * retention of pin groups during Shutdown. Upon exit from Shutdown, and - * when appropriate, an application can call this function, to - * correspondingly disable IO retention, and unlock the specified pin groups. - * - * @param groupFlags A logical OR of one or more of the following - * flags (defined in driverlib/prcm.h): - * PRCM_IO_RET_GRP_0 - all pins except sFlash and JTAG interface - * PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 - * PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 - * PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 - */ -void PowerCC32XX_disableIORetention(unsigned long groupFlags); - -/*! OS-specific power policy function */ -void PowerCC32XX_sleepPolicy(void); - -/*! - * @brief Software reset of a resource - * - * This function performs a software reset of a resource. - * - * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. - * - * @param resourceId resource id - * - * @return Power_SOK on success, - * Power_EINVALIDINPUT if the reseourceId is invalid. - * - */ - int_fast16_t PowerCC32XX_reset(uint_fast16_t resourceId); - -/* \cond */ -#define Power_getPerformanceLevel(void) 0 -#define Power_setPerformanceLevel(level) Power_EFAIL -/* \endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_power_PowerCC32XX__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c deleted file mode 100644 index df8fcced168..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c +++ /dev/null @@ -1,720 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_STATE 0xC61 - -void PWMTimerCC32XX_close(PWM_Handle handle); -int_fast16_t PWMTimerCC32XX_control(PWM_Handle handle, uint_fast16_t cmd, - void *arg); -void PWMTimerCC32XX_init(PWM_Handle handle); -PWM_Handle PWMTimerCC32XX_open(PWM_Handle handle, PWM_Params *params); -int_fast16_t PWMTimerCC32XX_setDuty(PWM_Handle handle, uint32_t dutyValue); -int_fast16_t PWMTimerCC32XX_setPeriod(PWM_Handle handle, uint32_t periodValue); -void PWMTimerCC32XX_start(PWM_Handle handle); -void PWMTimerCC32XX_stop(PWM_Handle handle); - -/* PWM function table for PWMTimerCC32XX implementation */ -const PWM_FxnTable PWMTimerCC32XX_fxnTable = { - PWMTimerCC32XX_close, - PWMTimerCC32XX_control, - PWMTimerCC32XX_init, - PWMTimerCC32XX_open, - PWMTimerCC32XX_setDuty, - PWMTimerCC32XX_setPeriod, - PWMTimerCC32XX_start, - PWMTimerCC32XX_stop -}; - -/* - * Internal value to notify an error has occurred while calculating a duty - * or period. - */ -static const uint32_t PWM_INVALID_VALUE = (~0); - -/* - * GPT peripheral load & match registers are 16 bits wide. Max value which - * can be set is 65535. - */ -static const uint16_t PWM_MAX_MATCH_REG_VALUE = (~0); - -/* - * GPT peripherals have 24 bit resolution. The max period value which be - * set is 16777215. - */ -static const uint32_t PWM_MAX_PERIOD_COUNT = (0xFFFFFF); - -/* - * The following fields are used by CC32XX driverlib APIs and therefore - * must be populated by driverlib macro definitions. For CC32XX driverlib - * these definitions are found in: - * - inc/hw_memmap.h - * - driverlib/gpio.h - * - driverlib/pin.h - * - driverlib/timer.h - */ -static const uint32_t timerBaseAddresses[4] = { - TIMERA0_BASE, - TIMERA1_BASE, - TIMERA2_BASE, - TIMERA3_BASE, -}; - -static const uint32_t timerHalves[2] = { - TIMER_A, - TIMER_B, -}; - -static const uint32_t gpioBaseAddresses[4] = { - GPIOA0_BASE, - GPIOA1_BASE, - GPIOA2_BASE, - GPIOA3_BASE, -}; - -static const uint32_t gpioPinIndexes[8] = { - GPIO_PIN_0, - GPIO_PIN_1, - GPIO_PIN_2, - GPIO_PIN_3, - GPIO_PIN_4, - GPIO_PIN_5, - GPIO_PIN_6, - GPIO_PIN_7, -}; - -#define PinConfigTimerPort(config) (((config) >> 28) & 0xF) -#define PinConfigTimerHalf(config) (((config) >> 24) & 0xF) -#define PinConfigGPIOPort(config) (((config) >> 20) & 0xF) -#define PinConfigGPIOPinIndex(config) (((config) >> 16) & 0xF) -#define PinConfigPinMode(config) (((config) >> 8) & 0xF) -#define PinConfigPin(config) (((config) >> 0) & 0x3F) - -/* - * ======== getDutyCounts ======== - */ -static uint32_t getDutyCounts(PWM_Duty_Units dutyUnits, uint32_t dutyValue, - uint32_t periodCounts) -{ - uint32_t duty = 0; - ClockP_FreqHz freq; - - ClockP_getCpuFreq(&freq); - - switch (dutyUnits) { - case PWM_DUTY_COUNTS: - duty = dutyValue; - break; - - case PWM_DUTY_FRACTION: - duty = (((uint64_t) dutyValue) * ((uint64_t) periodCounts)) / - PWM_DUTY_FRACTION_MAX; - break; - - case PWM_DUTY_US: - duty = (dutyValue != 0) ? (dutyValue * (freq.lo/1000000)) - 1 : 0; - break; - - default: - /* Unsupported duty units return an invalid duty */ - duty = PWM_INVALID_VALUE; - } - - return (duty); -} - -/* - * ======== getPeriodCounts ======== - */ -static uint32_t getPeriodCounts(PWM_Period_Units periodUnits, - uint32_t periodValue) -{ - uint32_t period = 0; - ClockP_FreqHz freq; - - ClockP_getCpuFreq(&freq); - - switch (periodUnits) { - case PWM_PERIOD_COUNTS: - period = periodValue; - break; - - case PWM_PERIOD_HZ: - if (periodValue && periodValue <= freq.lo) { - period = (freq.lo / periodValue) - 1; - } - break; - - case PWM_PERIOD_US: - period = (periodValue * (freq.lo/1000000)) - 1; - break; - - default: - /* Unsupported period units return an invalid period */ - period = PWM_INVALID_VALUE; - } - - return (period); -} - -/* - * ======== getPowerMgrId ======== - */ -static uint_fast16_t getPowerMgrId(uint32_t baseAddr) -{ - switch (baseAddr) { - case GPIOA0_BASE: - return (PowerCC32XX_PERIPH_GPIOA0); - case GPIOA1_BASE: - return (PowerCC32XX_PERIPH_GPIOA1); - case GPIOA2_BASE: - return (PowerCC32XX_PERIPH_GPIOA2); - case GPIOA3_BASE: - return (PowerCC32XX_PERIPH_GPIOA3); - case GPIOA4_BASE: - return (PowerCC32XX_PERIPH_GPIOA4); - default: - /* Should never get here */ - return ((unsigned int) -1); - } -} - -/* - * ======== initHw ======== - */ -static int initHw(PWM_Handle handle, uint32_t period, uint32_t duty) -{ - uintptr_t key; - int32_t result; - uint32_t timerConfigVal; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - MAP_TimerDisable(timerBaseAddr, halfTimer); - - /* - * The CC32XX SDK TimerConfigure API halts both timers when it is - * used to configure a single half timer. The code below performs - * the register operations necessary to configure each half timer - * individually. - */ - /* Enable CCP to IO path */ - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_GPT_TRIG_SEL) = 0xFF; - - /* Split the timer and configure it as a PWM */ - timerConfigVal = ((halfTimer & (TIMER_CFG_A_PWM | TIMER_CFG_B_PWM)) | - TIMER_CFG_SPLIT_PAIR); - HWREG(timerBaseAddr + TIMER_O_CFG) |= (timerConfigVal >> 24); - if (halfTimer & TIMER_A) { - HWREG(timerBaseAddr + TIMER_O_TAMR) = timerConfigVal & 255; - } - else { - HWREG(timerBaseAddr + TIMER_O_TBMR) = (timerConfigVal >> 8) & 255; - } - - /* Set the peripheral output to active-high */ - MAP_TimerControlLevel(timerBaseAddr, halfTimer, true); - - HwiP_restore(key); - - result = PWMTimerCC32XX_setPeriod(handle, period); - if (result != PWM_STATUS_SUCCESS) { - return (result); - } - - result = PWMTimerCC32XX_setDuty(handle, duty); - if (result != PWM_STATUS_SUCCESS) { - return (result); - } - - return (PWM_STATUS_SUCCESS); -} - -/* - * ======== postNotifyFxn ======== - * Called by Power module when waking up from LPDS. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - PWM_Handle handle = (PWM_Handle) clientArg; - PWMTimerCC32XX_Object *object = handle->object; - - initHw(handle, object->period, object->duty); - - return (Power_NOTIFYDONE); -} - -/* - * ======== PWMTimerCC32XX_close ======== - * @pre Function assumes that the handle is not NULL - */ -void PWMTimerCC32XX_close(PWM_Handle handle) -{ - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - TimerCC32XX_SubTimer subTimer; - uint32_t timerBaseAddr; - uint32_t gpioBaseAddr; - uint32_t padRegister; - uintptr_t key; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - - subTimer = (TimerCC32XX_SubTimer) (TimerCC32XX_timer16A + - PinConfigTimerHalf(hwAttrs->pwmPin)); - - /* - * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr - * is set to 0 & the GPIO power dependencies are not released. - */ - gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) == 0xF) ? - 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; - - PWMTimerCC32XX_stop(handle); - - key = HwiP_disable(); - - TimerCC32XX_freeTimerResource(timerBaseAddr, subTimer); - - /* Remove GPIO power dependency if pin is GPIO capable */ - if (gpioBaseAddr) { - Power_releaseDependency(getPowerMgrId(gpioBaseAddr)); - } - - Power_unregisterNotify(&object->postNotify); - - padRegister = (PinToPadGet((hwAttrs->pwmPin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - - object->isOpen = false; - - HwiP_restore(key); - - DebugP_log1("PWM:(%p) is closed", (uintptr_t) handle); -} - -/* - * ======== PWMTimerCC32XX_control ======== - * @pre Function assumes that the handle is not NULL - */ -int_fast16_t PWMTimerCC32XX_control(PWM_Handle handle, uint_fast16_t cmd, - void *arg) -{ - /* No implementation yet */ - return (PWM_STATUS_UNDEFINEDCMD); -} - -/* - * ======== PWMTimerCC32XX_init ======== - * @pre Function assumes that the handle is not NULL - */ -void PWMTimerCC32XX_init(PWM_Handle handle) -{ -} - -/* - * ======== PWMTimerCC32XX_open ======== - * @pre Function assumes that the handle is not NULL - */ -PWM_Handle PWMTimerCC32XX_open(PWM_Handle handle, PWM_Params *params) -{ - uintptr_t key; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - TimerCC32XX_SubTimer subTimer; - uint32_t timerBaseAddr; - uint32_t gpioBaseAddr; - uint16_t pin; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - pin = PinConfigPin(hwAttrs->pwmPin); - - subTimer = (TimerCC32XX_SubTimer) (TimerCC32XX_timer16A + - PinConfigTimerHalf(hwAttrs->pwmPin)); - - key = HwiP_disable(); - - if (object->isOpen) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) already opened.", (uintptr_t) handle); - - return (NULL); - } - - if (!TimerCC32XX_allocateTimerResource(timerBaseAddr, subTimer)) { - HwiP_restore(key); - - DebugP_log1("Timer: 0x%X unavailable.", timerBaseAddr); - - return (NULL); - } - - object->isOpen = true; - - HwiP_restore(key); - - /* - * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr - * is set to 0 & the GPIO power dependencies are not set. - */ - gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) == 0xF) ? - 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; - - /* Set GPIO power dependency if pin is GPIO capable */ - if (gpioBaseAddr) { - /* Check GPIO power resource Id */ - if (getPowerMgrId(gpioBaseAddr) == ((unsigned int) -1)) { - TimerCC32XX_freeTimerResource(timerBaseAddr, subTimer); - - object->isOpen = false; - - DebugP_log1("PWM:(%p) Failed to determine GPIO power resource ID.", - (uintptr_t) handle); - - return (NULL); - } - - /* Register power dependency for GPIO port */ - Power_setDependency(getPowerMgrId(gpioBaseAddr)); - } - - Power_registerNotify(&object->postNotify, PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t) handle); - - /* - * Set PWM duty to initial value (not 0) - required when inverting - * output polarity to generate a duty equal to 0 or period. See comments in - * PWMTimerCC32XX_setDuty for more information. - */ - object->duty = 0; - object->period = 0; - object->dutyUnits = params->dutyUnits; - object->idleLevel = params->idleLevel; - object->periodUnits = params->periodUnits; - object->pwmStarted = 0; - - /* Initialize the peripheral & set the period & duty */ - if (initHw(handle, params->periodValue, params->dutyValue) != - PWM_STATUS_SUCCESS) { - PWMTimerCC32XX_close(handle); - - DebugP_log1("PWM:(%p) Failed set initial PWM configuration.", - (uintptr_t) handle); - - return (NULL); - } - - /* Configure the Power_pinParkState based on idleLevel param */ - PowerCC32XX_setParkState((PowerCC32XX_Pin) pin, - (object->idleLevel == PWM_IDLE_HIGH)); - - /* Called to set the initial idleLevel */ - PWMTimerCC32XX_stop(handle); - - DebugP_log3("PWM:(%p) opened; period set to: %d; duty set to: %d", - (uintptr_t) handle, params->periodValue, params->dutyValue); - - return (handle); -} - -/* - * ======== PWMTimerCC32XX_setDuty ======== - * @pre Function assumes that handle is not NULL - */ -int_fast16_t PWMTimerCC32XX_setDuty(PWM_Handle handle, uint32_t dutyValue) -{ - uintptr_t key; - uint32_t duty; - uint32_t period; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - period = object->period; - duty = getDutyCounts(object->dutyUnits, dutyValue, period); - - if (duty == PWM_INVALID_VALUE) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) duty units could not be determined.", - (uintptr_t) handle); - - return (PWM_STATUS_ERROR); - } - - if (duty > period) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) duty is out of range.", (uintptr_t) handle); - - return (PWM_STATUS_INVALID_DUTY); - } - - /* - * The timer peripheral cannot generate a duty equal to the period when - * the timer is counting down. In these cases the PWM duty is set to the - * period value (output remains low) and output polarity is inverted. - * Additionally, if the output is changed from the period the PWM output - * polarity must be inverted again. - * - * The code below uses the previous duty (object->duty) and the new duty to - * determine if the polarity should be inverted. - * For more details refer to the device specific datasheet and the following - * E2E post: - * http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/354826.aspx - */ - if (((duty == period) && (object->duty != period)) || - ((duty != period) && (object->duty == period))) { - HWREG(timerBaseAddr + TIMER_O_CTL) ^= - (halfTimer & (TIMER_CTL_TAPWML | TIMER_CTL_TBPWML)); - } - - /* - * Set & store the new duty. IMPORTANT: this must be saved after output - * inversion is determined and before the duty = 0 corner case. - */ - object->duty = duty; - - /* - * Special corner case, if duty is 0 we set it to the period without - * inverting output - */ - if (duty == 0) { - duty = period; - } - - MAP_TimerPrescaleMatchSet(timerBaseAddr, halfTimer, - duty / PWM_MAX_MATCH_REG_VALUE); - MAP_TimerMatchSet(timerBaseAddr, halfTimer, - duty % PWM_MAX_MATCH_REG_VALUE); - - HwiP_restore(key); - - DebugP_log2("PWM:(%p) duty set to: %d", (uintptr_t) handle, dutyValue); - - return (PWM_STATUS_SUCCESS); -} - -/* - * ======== PWMTimerCC32XX_setPeriod ======== - * @pre Function assumes that handle is not NULL - */ -int_fast16_t PWMTimerCC32XX_setPeriod(PWM_Handle handle, uint32_t periodValue) -{ - uintptr_t key; - uint32_t duty; - uint32_t period; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - duty = object->duty; - period = getPeriodCounts(object->periodUnits, periodValue); - - if (period == PWM_INVALID_VALUE) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) period units could not be determined.", - (uintptr_t) handle); - - return (PWM_STATUS_ERROR); - } - - if ((period == 0) || (period <= duty) || (period > PWM_MAX_PERIOD_COUNT)) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) period is out of range.", (uintptr_t) handle); - - return (PWM_STATUS_INVALID_PERIOD); - } - - /* Set the new period */ - object->period = period; - MAP_TimerPrescaleSet(timerBaseAddr, halfTimer, - period / PWM_MAX_MATCH_REG_VALUE); - MAP_TimerLoadSet(timerBaseAddr, halfTimer, - period % PWM_MAX_MATCH_REG_VALUE); - - HwiP_restore(key); - - DebugP_log2("PWM:(%p) period set to: %d", (uintptr_t) handle, periodValue); - - return (PWM_STATUS_SUCCESS); -} - -/* - * ======== PWMTimerCC32XX_start ======== - * @pre Function assumes that handle is not NULL - */ -void PWMTimerCC32XX_start(PWM_Handle handle) -{ - uintptr_t key; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - uint16_t pin; - uint16_t mode; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - pin = PinConfigPin(hwAttrs->pwmPin); - mode = PinConfigPinMode(hwAttrs->pwmPin); - - key = HwiP_disable(); - - /* - * GP timer ticks only in Active mode. Cannot be used in HIB or LPDS. - * Set constraint to disallow LPDS. - */ - if (!(object->pwmStarted)) { - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - object->pwmStarted = true; - } - - /* Start the timer & set pinmux to PWM mode */ - MAP_TimerEnable(timerBaseAddr, halfTimer); - - MAP_PinTypeTimer((unsigned long)pin, (unsigned long)mode); - - HwiP_restore(key); - - DebugP_log1("PWM:(%p) started.", (uintptr_t) handle); -} - -/* - * ======== PWMTimerCC32XX_stop ======== - * @pre Function assumes that handle is not NULL - */ -void PWMTimerCC32XX_stop(PWM_Handle handle) -{ - uintptr_t key; - uint8_t output; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - uint32_t gpioBaseAddr; - uint8_t gpioPinIndex; - uint16_t pin; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - pin = PinConfigPin(hwAttrs->pwmPin); - - /* - * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr - * is set to 0 & the GPIO power dependencies are not set. - */ - gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) == 0xF) ? - 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; - gpioPinIndex = (PinConfigGPIOPinIndex(hwAttrs->pwmPin) == 0xF) ? - 0 : gpioPinIndexes[PinConfigGPIOPinIndex(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - /* Remove the dependency to allow LPDS */ - if (object->pwmStarted) { - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - object->pwmStarted = false; - } - - /* Set pin as GPIO with IdleLevel value & stop the timer */ - output = (object->idleLevel) ? gpioPinIndex : 0; - MAP_PinTypeGPIO((unsigned long)pin, PIN_MODE_0, false); - - /* Only configure the pin as GPIO if the pin is GPIO capable */ - if (gpioBaseAddr) { - MAP_GPIODirModeSet(gpioBaseAddr, gpioPinIndex, GPIO_DIR_MODE_OUT); - MAP_GPIOPinWrite(gpioBaseAddr, gpioPinIndex, output); - } - - /* Stop the Timer */ - MAP_TimerDisable(timerBaseAddr, halfTimer); - - HwiP_restore(key); - - DebugP_log1("PWM:(%p) stopped.", (uintptr_t) handle); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.h deleted file mode 100644 index 18601e5d16f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*! ============================================================================ - * @file PWMTimerCC32XX.h - * - * @brief PWM driver implementation using CC32XX General Purpose Timers. - * - * The PWM header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref PWM.h for a complete description of the PWM - * driver APIs provided and examples of their use. - * - * ## Overview # - * This driver configures a CC32XX General Purpose Timer (GPT) in PWM mode. - * When in PWM mode, each GPT is divided into 2 PWM outputs. This driver - * manages each output as an independent PWM instance. The timer is - * automatically configured in count-down mode using the system clock as - * the source. - * - * The timers operate at the system clock frequency (80 MHz). So each timer - * tick is 12.5 ns. The period and duty registers are 16 bits wide; thus - * 8-bit prescalars are used to extend period and duty registers. The - * maximum value supported is 16777215 timer counts ((2^24) - 1) or - * 209715 microseconds. Updates to a PWM's period or duty will occur - * instantaneously (GPT peripherals do not have shadow registers). - * - * When stopped, the driver will configure the pin in GPIO mode & set the - * output to the PWM_IdleLevel specified in the params used during open. Users - * need be aware that while PIN 19 can be used for PWM it is not GPIO capable, - * so it cannot be set to the PWM_IdleLevel. Output voltage will be PWM output - * at the moment it is stopped. - * - * Finally, when this driver is opened, it automatically changes the - * PWM pin's parking configuration (used when entering low power modes) to - * correspond with the PWM_IDLE_LEVEL set in the PWM_params. However, this - * setting is not reverted once the driver is closed, it is the users - * responsibility to change the parking configuration if necessary. - * - * ### CC32xx PWM Driver Configuration # - * - * In order to use the PWM APIs, the application is required - * to define 4 configuration items in the application Board.c file: - * - * 1. An array of PWMTimerCC32XX_Object elements, which will be used by - * by the driver to maintain instance state. - * Below is an example PWMTimerCC32XX_Object array appropriate for the CC3220SF Launchpad - * board: - * @code - * #include - * #include - * - * PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; - * @endcode - * - * 2. An array of PWMTimerCC32XX_HWAttrsV2 elements that defines which - * pin will be used by the corresponding PWM instance - * (see @ref pwmPinIdentifiersCC32XX). - * Below is an example PWMTimerCC32XX_HWAttrsV2 array appropriate for the CC3220SF Launchpad - * board: - * @code - * const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { - * { - * .pwmPin = PWMTimerCC32XX_PIN_01 - * }, - * { - * .pwmPin = PWMTimerCC32XX_PIN_02 - * } - * }; - * @endcode - * - * 3. An array of @ref PWM_Config elements, one for each PWM instance. Each - * element of this array identifies the device-specific API function table, - * the device specific PWM object instance, and the device specific Hardware - * Attributes to be used for each PWM channel. - * Below is an example @ref PWM_Config array appropriate for the CC3220SF Launchpad - * board: - * @code - * const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { - * { - * .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - * .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], - * .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] - * }, - * { - * .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - * .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], - * .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] - * } - * }; - * @endcode - * - * 4. A global variable, PWM_count, that informs the driver how many PWM - * instances are defined: - * @code - * const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; - * @endcode - * - * ### Power Management # - * The TI-RTOS power management framework will try to put the device into the most - * power efficient mode whenever possible. Please see the technical reference - * manual for further details on each power mode. - * - * The PWMTimerCC32XX driver explicitly sets a power constraint when the - * PWM is running to prevent LPDS. - * The following statements are valid: - * - After PWM_open(): Clocks are enabled to the timer resource and the - * configured pwmPin. The device is still allowed - * to enter LPDS. - * - After PWM_start(): LPDS is disabled when PWM is running. - * - After PWM_stop(): Conditions are equal as for after PWM_open - * - After PWM_close(): The underlying GPTimer is turned off, and the clocks - * to the timer and pin are disabled.. - * - * ============================================================================= - */ - -#ifndef ti_driver_pwm_PWMTimerCC32XX__include -#define ti_driver_pwm_PWMTimerCC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! \cond */ -/* - * PWMTimer port/pin defines for pin configuration. - * - * The timer id (0, 1, 2, or 3) is stored in bits 31 - 28 - * The timer half (0 = A, 1 = B) is stored in bits 27 - 24 - * The GPIO port (0, 1, 2, or 3) is stored in bits 23 - 20 - * The GPIO pin index within the port (0 - 7) is stored in bits 19 - 16 - * The pin mode is stored in bits 11 - 8 - * The pin number is stored in bits 7 - 0 - * - * - * 31 - 28 27 - 24 23 - 20 19 - 16 11 - 8 7 - 0 - * ----------------------------------------------------------------------- - * | Timer id | Timer half | GPIO port | GPIO pin index | pin mode | pin | - * ----------------------------------------------------------------------- - * - * The CC32XX has fixed GPIO assignments and pin modes for a given pin. - * A PWM pin mode for a given pin has a fixed timer/timer-half. - */ -#define PWMTimerCC32XX_T0A (0x00 << 24) -#define PWMTimerCC32XX_T0B (0x01 << 24) -#define PWMTimerCC32XX_T1A (0x10 << 24) -#define PWMTimerCC32XX_T1B (0x11 << 24) -#define PWMTimerCC32XX_T2A (0x20 << 24) -#define PWMTimerCC32XX_T2B (0x21 << 24) -#define PWMTimerCC32XX_T3A (0x30 << 24) -#define PWMTimerCC32XX_T3B (0x31 << 24) - -#define PWMTimerCC32XX_GPIO9 (0x11 << 16) -#define PWMTimerCC32XX_GPIO10 (0x12 << 16) -#define PWMTimerCC32XX_GPIO11 (0x13 << 16) -#define PWMTimerCC32XX_GPIO24 (0x30 << 16) -#define PWMTimerCC32XX_GPIO25 (0x31 << 16) - -#define PWMTimerCC32XX_GPIONONE (0xFF << 16) -/*! \endcond */ - -/*! - * \defgroup pwmPinIdentifiersCC32XX PWMTimerCC32XX_HWAttrs 'pwmPin' field options - * @{ - */ -/*! - * @name PIN 01, GPIO10, uses Timer3A for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_01 (PWMTimerCC32XX_T3A | PWMTimerCC32XX_GPIO10 | 0x0300) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 02, GPIO11, uses Timer3B for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_02 (PWMTimerCC32XX_T3B | PWMTimerCC32XX_GPIO11 | 0x0301) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 17, GPIO24, uses Timer0A for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_17 (PWMTimerCC32XX_T0A | PWMTimerCC32XX_GPIO24 | 0x0510) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 19, uses Timer1B for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_19 (PWMTimerCC32XX_T1B | PWMTimerCC32XX_GPIONONE | 0x0812) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 21, GPIO25, uses Timer1A for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_21 (PWMTimerCC32XX_T1A | PWMTimerCC32XX_GPIO25 | 0x0914) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 64, GPIO9, uses Timer2B for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_64 (PWMTimerCC32XX_T2B | PWMTimerCC32XX_GPIO9 | 0x033F) /*!< @hideinitializer */ -/*! @} */ -/*! @} */ - -/** - * @addtogroup PWM_STATUS - * PWMTimerCC32XX_STATUS_* macros are command codes only defined in the - * PWMTimerCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add PWMTimerCC32XX_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup PWM_CMD - * PWMTimerCC32XX_CMD_* macros are command codes only defined in the - * PWMTimerCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add PWMTimerCC32XX_CMD_* macros here */ - -/** @}*/ - -/* PWM function table pointer */ -extern const PWM_FxnTable PWMTimerCC32XX_fxnTable; - -/*! - * @brief PWMTimerCC32XX Hardware attributes - * - * The 'pwmPin' field identifies which physical pin to use for a - * particular PWM channel as well as the corresponding Timer resource used - * to source the PWM signal. The encoded pin identifier macros for - * initializing the 'pwmPin' field must be selected from the - * @ref pwmPinIdentifiersCC32XX macros. - * - * A sample structure is shown below: - * @code - * const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC32XXHWAttrs[] = { - * { - * .pwmPin = PWMTimerCC32XX_PIN_01, - * }, - * { - * .pwmPin = PWMTimerCC32XX_PIN_02, - * } - * }; - * @endcode - */ -typedef struct PWMTimerCC32XX_HWAttrsV2 { - uint32_t pwmPin; /*!< Pin to output PWM signal on - (see @ref pwmPinIdentifiersCC32XX) */ -} PWMTimerCC32XX_HWAttrsV2; - -/*! - * @brief PWMTimerCC32XX Object - * - * The application must not access any member variables of this structure! - */ -typedef struct PWMTimerCC32XX_Object { - Power_NotifyObj postNotify; - uint32_t duty; /* Current duty cycle in Duty_Unites */ - uint32_t period; /* Current period PERIOD_Units */ - PWM_Duty_Units dutyUnits; /* Current duty cycle unit */ - PWM_Period_Units periodUnits; /* Current period unit */ - PWM_IdleLevel idleLevel; /* PWM idle level when stopped / not started */ - bool pwmStarted; /* Used to gate Power_set/releaseConstraint() calls */ - bool isOpen; /* open flag used to check if PWM is opened */ -} PWMTimerCC32XX_Object; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_driver_pwm_PWMTimerCC32XX__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.c deleted file mode 100755 index 22179683457..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.c +++ /dev/null @@ -1,803 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define MAX_DMA_TRANSFER_AMOUNT (1024) - -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_STATE 0xC61 - -void SPICC32XXDMA_close(SPI_Handle handle); -int_fast16_t SPICC32XXDMA_control(SPI_Handle handle, uint_fast16_t cmd, - void *arg); -void SPICC32XXDMA_init(SPI_Handle handle); -SPI_Handle SPICC32XXDMA_open(SPI_Handle handle, SPI_Params *params); -bool SPICC32XXDMA_transfer(SPI_Handle handle, SPI_Transaction *transaction); -void SPICC32XXDMA_transferCancel(SPI_Handle handle); - -/* SPI function table for SPICC32XXDMA implementation */ -const SPI_FxnTable SPICC32XXDMA_fxnTable = { - SPICC32XXDMA_close, - SPICC32XXDMA_control, - SPICC32XXDMA_init, - SPICC32XXDMA_open, - SPICC32XXDMA_transfer, - SPICC32XXDMA_transferCancel -}; - -static const uint32_t mode[] = { - SPI_MODE_MASTER, - SPI_MODE_SLAVE -}; - -/* - * This lookup table is used to configure the DMA channels for the appropriate - * (8bit, 16bit or 32bit) transfer sizes. - * Table for an SPI DMA RX channel. - */ -static const uint32_t dmaRxConfig[] = { - UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_1, - UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_1, - UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_1 -}; - -/* - * This lookup table is used to configure the DMA channels for the appropriate - * (8bit, 16bit or 32bit) transfer sizes. - * Table for an SPI DMA TX channel - */ -static const uint32_t dmaTxConfig[] = { - UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_1, - UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_1, - UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_NONE | UDMA_ARB_1 -}; - -/* - * This lookup table is used to configure the DMA channels for the appropriate - * (8bit, 16bit or 32bit) transfer sizes when either txBuf or rxBuf are NULL. - */ -static const uint32_t dmaNullConfig[] = { - UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1, - UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1, - UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1 -}; - -/* - * ======== blockingTransferCallback ======== - */ -static void blockingTransferCallback(SPI_Handle handle, - SPI_Transaction *transaction) -{ - SPICC32XXDMA_Object *object = handle->object; - - SemaphoreP_post(object->transferComplete); -} - -/* - * ======== configDMA ======== - * This functions configures the transmit and receive DMA channels for a given - * SPI_Handle and SPI_Transaction - */ -static void configDMA(SPICC32XXDMA_Object *object, - SPICC32XXDMA_HWAttrsV1 const *hwAttrs, SPI_Transaction *transaction) -{ - uintptr_t key; - void *buf; - uint32_t channelControlOptions; - uint8_t dataFrameSizeInBytes; - uint8_t optionsIndex; - - /* DMA options used vary according to data size. */ - if (object->dataSize < 9) { - optionsIndex = 0; - dataFrameSizeInBytes = sizeof(uint8_t); - } - else if (object->dataSize < 17) { - optionsIndex = 1; - dataFrameSizeInBytes = sizeof(uint16_t);; - } - else { - optionsIndex = 2; - dataFrameSizeInBytes = sizeof(uint32_t); - } - - /* - * The DMA has a max transfer amount of 1024. If the transaction is - * greater; we must transfer it in chunks. object->amtDataXferred has - * how much data has already been sent. - */ - if ((transaction->count - object->amtDataXferred) > MAX_DMA_TRANSFER_AMOUNT) { - object->currentXferAmt = MAX_DMA_TRANSFER_AMOUNT; - } - else { - object->currentXferAmt = (transaction->count - object->amtDataXferred); - } - - if (transaction->txBuf) { - channelControlOptions = dmaTxConfig[optionsIndex]; - /* - * Add an offset for the amount of data transfered. The offset is - * calculated by: object->amtDataXferred * (dataFrameSizeInBytes). - * This accounts for 8, 16 or 32-bit sized transfers. - */ - buf = (void *) ((uint32_t) transaction->txBuf + - ((uint32_t) object->amtDataXferred * dataFrameSizeInBytes)); - } - else { - channelControlOptions = dmaNullConfig[optionsIndex]; - *hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue; - buf = hwAttrs->scratchBufPtr; - } - - /* Setup the TX transfer characteristics & buffers */ - MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, - channelControlOptions); - MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, - UDMA_ATTR_ALTSELECT); - MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, - UDMA_MODE_BASIC, buf, (void *) (hwAttrs->baseAddr + MCSPI_O_TX0), - object->currentXferAmt); - - if (transaction->rxBuf) { - channelControlOptions = dmaRxConfig[optionsIndex]; - /* - * Add an offset for the amount of data transfered. The offset is - * calculated by: object->amtDataXferred * (dataFrameSizeInBytes). - * This accounts for 8 or 16-bit sized transfers. - */ - buf = (void *) ((uint32_t) transaction->rxBuf + - ((uint32_t) object->amtDataXferred * dataFrameSizeInBytes)); - } - else { - channelControlOptions = dmaNullConfig[optionsIndex]; - buf = hwAttrs->scratchBufPtr; - } - - /* Setup the RX transfer characteristics & buffers */ - MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, - channelControlOptions); - MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, - UDMA_ATTR_ALTSELECT); - MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, - UDMA_MODE_BASIC, (void *) (hwAttrs->baseAddr + MCSPI_O_RX0), buf, - object->currentXferAmt); - - /* A lock is needed because we are accessing shared uDMA memory */ - key = HwiP_disable(); - - MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex); - MAP_uDMAChannelAssign(hwAttrs->txChannelIndex); - - /* Enable DMA to generate interrupt on SPI peripheral */ - MAP_SPIDmaEnable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); - MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIIntEnable(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIWordCountSet(hwAttrs->baseAddr, object->currentXferAmt); - - /* Enable channels & start DMA transfers */ - MAP_uDMAChannelEnable(hwAttrs->txChannelIndex); - MAP_uDMAChannelEnable(hwAttrs->rxChannelIndex); - - HwiP_restore(key); - - MAP_SPIEnable(hwAttrs->baseAddr); - MAP_SPICSEnable(hwAttrs->baseAddr); -} - -/* - * ======== getDmaRemainingXfers ======== - */ -static inline uint32_t getDmaRemainingXfers(SPICC32XXDMA_HWAttrsV1 const *hwAttrs) { - uint32_t controlWord; - tDMAControlTable *controlTable; - - controlTable = MAP_uDMAControlBaseGet(); - controlWord = controlTable[(hwAttrs->rxChannelIndex & 0x3f)].ulControl; - - return (((controlWord & UDMA_CHCTL_XFERSIZE_M) >> 4) + 1); -} - -/* - * ======== getPowerMgrId ======== - */ -static uint16_t getPowerMgrId(uint32_t baseAddr) -{ - switch (baseAddr) { - case GSPI_BASE: - return (PowerCC32XX_PERIPH_GSPI); - case LSPI_BASE: - return (PowerCC32XX_PERIPH_LSPI); - default: - return (~0); - } -} - -/* - * ======== initHw ======== - */ -static void initHw(SPICC32XXDMA_Object *object, - SPICC32XXDMA_HWAttrsV1 const *hwAttrs) -{ - /* - * SPI peripheral should remain disabled until a transfer is requested. - * This is done to prevent the RX FIFO from gathering data from other - * transfers. - */ - MAP_SPICSDisable(hwAttrs->baseAddr); - MAP_SPIDisable(hwAttrs->baseAddr); - MAP_SPIReset(hwAttrs->baseAddr); - - MAP_SPIConfigSetExpClk(hwAttrs->baseAddr, - MAP_PRCMPeripheralClockGet(hwAttrs->spiPRCM), object->bitRate, - mode[object->spiMode], object->frameFormat, - (hwAttrs->csControl | hwAttrs->pinMode | hwAttrs->turboMode | - hwAttrs->csPolarity | ((object->dataSize - 1) << 7))); - - MAP_SPIFIFOEnable(hwAttrs->baseAddr, SPI_RX_FIFO | SPI_TX_FIFO); - MAP_SPIFIFOLevelSet(hwAttrs->baseAddr, object->txFifoTrigger, - object->rxFifoTrigger); -} - -/* - * ======== postNotifyFxn ======== - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - SPICC32XXDMA_Object *object = ((SPI_Handle) clientArg)->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = ((SPI_Handle) clientArg)->hwAttrs; - - initHw(object, hwAttrs); - - return (Power_NOTIFYDONE); -} - -/* - * ======== spiHwiFxn ======== - */ -static void spiHwiFxn(uintptr_t arg) -{ - uint32_t intFlags; - SPI_Transaction *msg; - SPICC32XXDMA_Object *object = ((SPI_Handle)arg)->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = ((SPI_Handle)arg)->hwAttrs; - - /* - * Although the DMATX interrupt is not used by this driver, it seems like - * it is still triggering DMA interrupts. The code below will clear & - * disable the interrupt thus reducing the amount of spurious interrupts. - */ - intFlags = MAP_SPIIntStatus(hwAttrs->baseAddr, false); - if (intFlags & SPI_INT_DMATX) { - MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMATX); - MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMATX); - } - - if (MAP_uDMAChannelIsEnabled(hwAttrs->rxChannelIndex)) { - /* DMA has not completed if the channel is still enabled */ - return; - } - - /* RX DMA channel has completed; disable peripheral */ - MAP_SPIDmaDisable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); - MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPICSDisable(hwAttrs->baseAddr); - MAP_SPIDisable(hwAttrs->baseAddr); - - if (object->transaction->count - object->amtDataXferred > - MAX_DMA_TRANSFER_AMOUNT) { - /* Data still remaining, configure another DMA transfer */ - object->amtDataXferred += object->currentXferAmt; - - configDMA(object, hwAttrs, object->transaction); - } - else { - /* All data sent; set status, perform callback & return */ - object->transaction->status = SPI_TRANSFER_COMPLETED; - - /* Release constraint since transaction is done */ - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* - * Use a temporary transaction pointer in case the callback function - * attempts to perform another SPI_transfer call - */ - msg = object->transaction; - - /* Indicate we are done with this transfer */ - object->transaction = NULL; - - object->transferCallbackFxn((SPI_Handle) arg, msg); - } -} - -/* - * ======== spiPollingTransfer ======== - */ -static inline void spiPollingTransfer(SPICC32XXDMA_Object *object, - SPICC32XXDMA_HWAttrsV1 const *hwAttrs, SPI_Transaction *transaction) -{ - uint8_t increment; - uint32_t dummyBuffer; - size_t transferCount; - void *rxBuf; - void *txBuf; - - if (transaction->rxBuf) { - rxBuf = transaction->rxBuf; - } - else { - rxBuf = hwAttrs->scratchBufPtr; - } - - if (transaction->txBuf) { - txBuf = transaction->txBuf; - } - else { - *hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue; - txBuf = hwAttrs->scratchBufPtr; - } - - if (object->dataSize < 9) { - increment = sizeof(uint8_t); - } - else if (object->dataSize < 17) { - increment = sizeof(uint16_t); - } - else { - increment = sizeof(uint32_t); - } - - transferCount = transaction->count; - - /* - * Start the polling transfer - we MUST set word count to 0; not doing so - * will raise spurious RX interrupts flags (though interrupts are not - * enabled). - */ - MAP_SPIWordCountSet(hwAttrs->baseAddr, 0); - MAP_SPIEnable(hwAttrs->baseAddr); - MAP_SPICSEnable(hwAttrs->baseAddr); - - while (transferCount--) { - if (object->dataSize < 9) { - MAP_SPIDataPut(hwAttrs->baseAddr, *((uint8_t *) txBuf)); - MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long *)&dummyBuffer); - *((uint8_t *) rxBuf) = (uint8_t) dummyBuffer; - } - else if (object->dataSize < 17) { - MAP_SPIDataPut(hwAttrs->baseAddr, *((uint16_t *) txBuf)); - MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long *) &dummyBuffer); - *((uint16_t *) rxBuf) = (uint16_t) dummyBuffer; - } - else { - MAP_SPIDataPut(hwAttrs->baseAddr, *((uint32_t *) txBuf)); - MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long * ) rxBuf); - } - - /* Only increment source & destination if buffers were provided */ - if (transaction->rxBuf) { - rxBuf = (void *) (((uint32_t) rxBuf) + increment); - } - if (transaction->txBuf) { - txBuf = (void *) (((uint32_t) txBuf) + increment); - } - } - - MAP_SPICSDisable(hwAttrs->baseAddr); - MAP_SPIDisable(hwAttrs->baseAddr); -} - -/* - * ======== SPICC32XXDMA_close ======== - */ -void SPICC32XXDMA_close(SPI_Handle handle) -{ - uint32_t padRegister; - SPICC32XXDMA_Object *object = handle->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - MAP_SPICSDisable(hwAttrs->baseAddr); - MAP_SPIDisable(hwAttrs->baseAddr); - MAP_SPIFIFODisable(hwAttrs->baseAddr, SPI_RX_FIFO | SPI_TX_FIFO); - - /* Release power dependency on SPI. */ - Power_releaseDependency(getPowerMgrId(hwAttrs->baseAddr)); - Power_unregisterNotify(&(object->notifyObj)); - - if (object->hwiHandle) { - HwiP_delete(object->hwiHandle); - } - if (object->transferComplete) { - SemaphoreP_delete(object->transferComplete); - } - - if (object->dmaHandle) { - UDMACC32XX_close(object->dmaHandle); - } - - /* Restore pin pads to their reset states */ - if (hwAttrs->mosiPin != SPICC32XXDMA_PIN_NO_CONFIG) { - padRegister = (PinToPadGet((hwAttrs->mosiPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - if (hwAttrs->misoPin != SPICC32XXDMA_PIN_NO_CONFIG) { - padRegister = (PinToPadGet((hwAttrs->misoPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - if (hwAttrs->clkPin != SPICC32XXDMA_PIN_NO_CONFIG) { - padRegister = (PinToPadGet((hwAttrs->clkPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - if ((hwAttrs->pinMode == SPI_4PIN_MODE) && - (hwAttrs->csPin != SPICC32XXDMA_PIN_NO_CONFIG)) { - padRegister = (PinToPadGet((hwAttrs->csPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - - object->isOpen = false; -} - -/* - * ======== SPICC32XXDMA_control ======== - */ -int_fast16_t SPICC32XXDMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg) -{ - return (SPI_STATUS_UNDEFINEDCMD); -} - -/* - * ======== SPICC32XXDMA_init ======== - */ -void SPICC32XXDMA_init(SPI_Handle handle) -{ - UDMACC32XX_init(); -} - -/* - * ======== SPICC32XXDMA_open ======== - */ -SPI_Handle SPICC32XXDMA_open(SPI_Handle handle, SPI_Params *params) -{ - uintptr_t key; - uint16_t pin; - uint16_t mode; - uint8_t powerMgrId; - HwiP_Params hwiParams; - SPICC32XXDMA_Object *object = handle->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - key = HwiP_disable(); - - if (object->isOpen) { - HwiP_restore(key); - - return (NULL); - } - object->isOpen = true; - - HwiP_restore(key); - - /* SPI_TI & SPI_MW are not supported */ - if (params->frameFormat == SPI_TI || params->frameFormat == SPI_MW) { - object->isOpen = false; - - return (NULL); - } - - /* Register power dependency - i.e. power up and enable clock for SPI. */ - powerMgrId = getPowerMgrId(hwAttrs->baseAddr); - if (powerMgrId > PowerCC32XX_NUMRESOURCES) { - object->isOpen = false; - - return (NULL); - } - Power_setDependency(powerMgrId); - Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t) handle); - - /* Configure the pins */ - if (hwAttrs->mosiPin != SPICC32XXDMA_PIN_NO_CONFIG) { - pin = (hwAttrs->mosiPin) & 0xff; - mode = (hwAttrs->mosiPin >> 8) & 0xff; - MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); - } - - if (hwAttrs->misoPin != SPICC32XXDMA_PIN_NO_CONFIG) { - pin = (hwAttrs->misoPin) & 0xff; - mode = (hwAttrs->misoPin >> 8) & 0xff; - MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); - } - - if (hwAttrs->clkPin != SPICC32XXDMA_PIN_NO_CONFIG) { - pin = (hwAttrs->clkPin) & 0xff; - mode = (hwAttrs->clkPin >> 8) & 0xff; - MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); - } - - if (hwAttrs->pinMode == SPI_4PIN_MODE) { - if (hwAttrs->csPin != SPICC32XXDMA_PIN_NO_CONFIG) { - pin = (hwAttrs->csPin) & 0xff; - mode = (hwAttrs->csPin >> 8) & 0xff; - MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); - } - } - - object->dmaHandle = UDMACC32XX_open(); - if (object->dmaHandle == NULL) { - SPICC32XXDMA_close(handle); - - return (NULL); - } - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t) handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, spiHwiFxn, &hwiParams); - if (object->hwiHandle == NULL) { - SPICC32XXDMA_close(handle); - - return (NULL); - } - - if (params->transferMode == SPI_MODE_BLOCKING) { - /* - * Create a semaphore to block task execution for the duration of the - * SPI transfer - */ - object->transferComplete = SemaphoreP_createBinary(0); - if (object->transferComplete == NULL) { - SPICC32XXDMA_close(handle); - - return (NULL); - } - - object->transferCallbackFxn = blockingTransferCallback; - } - else { - if (params->transferCallbackFxn == NULL) { - SPICC32XXDMA_close(handle); - - return (NULL); - } - - object->transferCallbackFxn = params->transferCallbackFxn; - } - - object->bitRate = params->bitRate; - object->dataSize = params->dataSize; - object->frameFormat = params->frameFormat; - object->spiMode = params->mode; - object->transaction = NULL; - object->transferMode = params->transferMode; - object->transferTimeout = params->transferTimeout; - - /* SPI FIFO trigger sizes vary based on data frame size */ - if (object->dataSize < 9) { - object->rxFifoTrigger = sizeof(uint8_t); - object->txFifoTrigger = sizeof(uint8_t); - } - else if (object->dataSize < 17) { - object->rxFifoTrigger = sizeof(uint16_t); - object->txFifoTrigger = sizeof(uint16_t); - } - else { - object->rxFifoTrigger = sizeof(uint32_t); - object->txFifoTrigger = sizeof(uint32_t); - } - - initHw(object, hwAttrs); - - return (handle); -} - -/* - * ======== SPICC32XXDMA_transfer ======== - */ -bool SPICC32XXDMA_transfer(SPI_Handle handle, SPI_Transaction *transaction) -{ - uintptr_t key; - uint8_t alignMask; - bool buffersAligned; - SPICC32XXDMA_Object *object = handle->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - if ((transaction->count == 0) || - (transaction->rxBuf == NULL && transaction->txBuf == NULL) || - (hwAttrs->scratchBufPtr == NULL && (transaction->rxBuf == NULL || - transaction->txBuf == NULL))) { - return (false); - } - - key = HwiP_disable(); - - /* - * alignMask is used to determine if the RX/TX buffers addresses are - * aligned to the data frame size. - */ - alignMask = (object->rxFifoTrigger - 1); - buffersAligned = ((((uint32_t) transaction->rxBuf & alignMask) == 0) && - (((uint32_t) transaction->txBuf & alignMask) == 0)); - - if (object->transaction) { - HwiP_restore(key); - - return (false); - } - else { - object->transaction = transaction; - object->transaction->status = SPI_TRANSFER_STARTED; - object->amtDataXferred = 0; - object->currentXferAmt = 0; - } - - HwiP_restore(key); - - /* Set constraints to guarantee transaction */ - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* Polling transfer if BLOCKING mode & transaction->count < threshold */ - if ((object->transferMode == SPI_MODE_BLOCKING && - transaction->count < hwAttrs->minDmaTransferSize) || !buffersAligned) { - spiPollingTransfer(object, hwAttrs, transaction); - - /* Transaction completed; set status & mark SPI ready */ - object->transaction->status = SPI_TRANSFER_COMPLETED; - object->transaction = NULL; - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - } - else { - /* Perform a DMA backed SPI transfer */ - configDMA(object, hwAttrs, transaction); - - if (object->transferMode == SPI_MODE_BLOCKING) { - if (SemaphoreP_pend(object->transferComplete, - object->transferTimeout) != SemaphoreP_OK) { - /* Timeout occurred; cancel the transfer */ - object->transaction->status = SPI_TRANSFER_FAILED; - SPICC32XXDMA_transferCancel(handle); - - /* - * TransferCancel() performs callback which posts - * transferComplete semaphore. This call consumes this extra post. - */ - SemaphoreP_pend(object->transferComplete, SemaphoreP_NO_WAIT); - - return (false); - } - } - } - - return (true); -} - -/* - * ======== SPICC32XXDMA_transferCancel ======== - */ -void SPICC32XXDMA_transferCancel(SPI_Handle handle) -{ - uintptr_t key; - SPI_Transaction *msg; - SPICC32XXDMA_Object *object = handle->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - /* - * There are 2 use cases in which to call transferCancel(): - * 1. The driver is in CALLBACK mode. - * 2. The driver is in BLOCKING mode & there has been a transfer timeout. - */ - if (object->transferMode == SPI_MODE_CALLBACK || - object->transaction->status == SPI_TRANSFER_FAILED) { - - key = HwiP_disable(); - - if (object->transaction == NULL || object->cancelInProgress) { - HwiP_restore(key); - - return; - } - object->cancelInProgress = true; - - /* Prevent interrupt from occurring while canceling the transfer */ - HwiP_disableInterrupt(hwAttrs->intNum); - HwiP_clearInterrupt(hwAttrs->intNum); - - /* Clear DMA configuration */ - MAP_uDMAChannelDisable(hwAttrs->rxChannelIndex); - MAP_uDMAChannelDisable(hwAttrs->txChannelIndex); - - MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIDmaDisable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); - - HwiP_restore(key); - - /* - * Disables peripheral, clears all registers & reinitializes it to - * parameters used in SPI_open() - */ - initHw(object, hwAttrs); - - HwiP_enableInterrupt(hwAttrs->intNum); - - /* - * Calculate amount of data which has already been sent & store - * it in transaction->count - */ - object->transaction->count = object->amtDataXferred + - (object->currentXferAmt - getDmaRemainingXfers(hwAttrs)); - - /* Set status CANCELED if we did not cancel due to timeout */ - if (object->transaction->status == SPI_TRANSFER_STARTED) { - object->transaction->status = SPI_TRANSFER_CANCELED; - } - - /* Release constraint set during transaction */ - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* - * Use a temporary transaction pointer in case the callback function - * attempts to perform another SPI_transfer call - */ - msg = object->transaction; - - /* Indicate we are done with this transfer */ - object->transaction = NULL; - object->cancelInProgress = false; - object->transferCallbackFxn(handle, msg); - } -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.h deleted file mode 100755 index 58f64a184cc..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.h +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file SPICC32XXDMA.h - * - * @brief SPI driver implementation for a CC32XX SPI controller using the - * micro DMA controller. - * - * The SPI header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref SPI.h for a complete description of APIs & example of use. - * - * This SPI driver implementation is designed to operate on a CC32XX SPI - * controller using a micro DMA controller. - * - * ## Frame Formats # - * This SPI controller supports 4 phase & polarity formats. Refer to the device - * specific data sheets & technical reference manuals for specifics on each - * format. - * - * ## SPI Chip Select # - * This SPI controller supports a hardware chip select pin. Refer to the - * device's user manual on how this hardware chip select pin behaves in regards - * to the SPI frame format. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Chip select typeSPI_MASTER modeSPI_SLAVE mode
Hardware chip selectNo action is needed by the application to select the peripheral.See the device documentation on it's chip select requirements.
Software chip selectThe application is responsible to ensure that correct SPI slave is - * selected before performing a SPI_transfer().See the device documentation on it's chip select requirements.
- * - * ## SPI data frames # - * SPI data frames can be any size from 4-bits to 32-bits. The SPI data - * frame size is set in ::SPI_Params.dataSize passed to SPI_open. - * The SPICC32XXDMA driver implementation makes assumptions on the element - * size of the ::SPI_Transaction txBuf and rxBuf arrays, based on the data - * frame size. If the data frame size is less than or equal to 8 bits, - * txBuf and rxBuf are assumed to be arrays of 8-bit uint8_t elements. - * If the data frame size is greater than 8 bits, but less than or equal - * to 16 bits, txBuf and rxBuf are assumed to be arrays of 16-bit uint16_t - * elements. Otherwise, txBuf and rxBuf are assumed to point to 32-bit - * uint32_t elements. - * - * data frame size | buffer element size | - * -------------- | ------------------- | - * 4-8 bits | uint8_t | - * 9-16 bits | uint16_t | - * 17-32 bits | uint32_t | - * - * Data buffers in transactions (rxBuf & txBuf) must be address aligned - * according to the data frame size. For example, if data frame is 9-bit - * (driver assumes buffers are uint16_t) rxBuf & txBuf must be aligned - * on a 16-bit address boundary, if data frame is 20-bit (driver assumes - * buffers are uint32_t) rxBuf & txBuf must be aligned on a 32-bit address - * boundary. - * - * ## DMA Interrupts # - * This driver is designed to operate with the micro DMA. The micro DMA - * generates an interrupt on the perpheral's interrupt vector. This - * implementation automatically installs a DMA aware hardware ISR to service - * the assigned micro DMA channels. - * - * ## DMA accessible memory # - * As this driver uses uDMA to transfer data/from data buffers, it is the - * responsibility of the application to ensure that these buffers reside in - * memory that is accessible by the DMA. - * - * ## Scratch Buffers # - * A uint32_t scratch buffer is used to allow SPI_transfers where txBuf or - * rxBuf are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer - * of size of the transfer count, a single DMA accessible uint32_t scratch - * buffer is used. When rxBuf is NULL, the uDMA will transfer all the SPI data - * receives into the scratch buffer as a "bit-bucket". When txBuf is NULL, the - * scratch buffer is initialized to defaultTxBufValue so the uDMA will send - * some known value. Each SPI driver instance must have its own scratch buffer. - * - * ## Polling SPI transfers # - * When used in blocking mode small SPI transfers are can be done by polling - * the peripheral & sending data frame-by-frame. This will not block the task - * which requested the transfer, but instead immediately perform the transfer - * & return. The minDmaTransferSize field in the hardware attributes is - * the threshold; if the transaction count is below the threshold a polling - * transfer is performed; otherwise a DMA transfer is done. This is intended - * to reduce the overhead of setting up a DMA transfer to only send a few - * data frames. Keep in mind that during polling transfers the current task - * is still being executed; there is no context switch to another task. - ******************************************************************************* - */ - -#ifndef ti_drivers_spi_SPICC32XXDMA__include -#define ti_drivers_spi_SPICC32XXDMA__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include - -/** - * @addtogroup SPI_STATUS - * SPICC32XXDMA_STATUS_* macros are command codes only defined in the - * SPICC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add SPICC32XXDMA_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup SPI_CMD - * SPICC32XXDMA_CMD_* macros are command codes only defined in the - * SPICC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add SPICC32XXDMA_CMD_* macros here */ - -/** @}*/ - -/* - * Macros defining possible SPI signal pin mux options - * - * The lower 8 bits of the macro refer to the pin, offset by 1, to match - * driverlib pin defines. For example, SPICC32XXDMA_PIN_05_CLK & 0xff = 4, - * which equals PIN_05 in driverlib pin.h. By matching the PIN_xx defines in - * driverlib pin.h, we can pass the pin directly to the driverlib functions. - * The upper 8 bits of the macro correspond to the pin mux confg mode - * value for the pin to operate in the SPI mode. - * - * PIN_62 is special for the SDSPI driver when using an SD Boosterpack, - * as PIN_62 doesn't have an assigned SPI function yet the SD Boosterpack - * has it tied to the CS signal. - */ -#define SPICC32XXDMA_PIN_05_CLK 0x0704 /*!< PIN 5 is used for SPI CLK */ -#define SPICC32XXDMA_PIN_06_MISO 0x0705 /*!< PIN 6 is used for MISO */ -#define SPICC32XXDMA_PIN_07_MOSI 0x0706 /*!< PIN 7 is used for MOSI */ -#define SPICC32XXDMA_PIN_08_CS 0x0707 /*!< PIN 8 is used for CS */ -#define SPICC32XXDMA_PIN_45_CLK 0x072C /*!< PIN 45 is used for SPI CLK */ -#define SPICC32XXDMA_PIN_50_CS 0x0931 /*!< PIN 50 is used for CS */ -#define SPICC32XXDMA_PIN_52_MOSI 0x0833 /*!< PIN 52 is used for MOSI */ -#define SPICC32XXDMA_PIN_53_MISO 0x0734 /*!< PIN 53 is used for MISO */ - -/*! - * @brief Indicates a pin is not to be configured by the SPICC32XXDMA driver. - */ -#define SPICC32XXDMA_PIN_NO_CONFIG 0xFFFF - -/* SPI function table pointer */ -extern const SPI_FxnTable SPICC32XXDMA_fxnTable; - -/*! - * @brief SPICC32XXDMA Hardware attributes - * - * These fields, with the exception of intPriority, - * are used by driverlib APIs and therefore must be populated by - * driverlib macro definitions. For CCWare these definitions are found in: - * - driverlib/prcm.h - * - driverlib/spi.h - * - driverlib/udma.h - * - inc/hw_memmap.h - * - inc/hw_ints.h - * - * intPriority is the SPI peripheral's interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's interrupt - * handler creation code, so you need to refer to the OS documentation - * for usage. For example, for SYS/BIOS applications, refer to the - * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of - * interrupt priorities. If the driver uses the ti.dpl interface - * instead of making OS calls directly, then the HwiP port handles the - * interrupt priority in an OS specific way. In the case of the SYS/BIOS - * port, intPriority is passed unmodified to Hwi_create(). - * - * A sample structure is shown below: - * @code - * #if defined(__TI_COMPILER_VERSION__) - * #pragma DATA_ALIGN(scratchBuf, 32) - * #elif defined(__IAR_SYSTEMS_ICC__) - * #pragma data_alignment=32 - * #elif defined(__GNUC__) - * __attribute__ ((aligned (32))) - * #endif - * uint32_t scratchBuf; - * - * const SPICC32XXDMA_HWAttrsV1 SPICC32XXDMAHWAttrs[] = { - * { - * .baseAddr = GSPI_BASE, - * .intNum = INT_GSPI, - * .intPriority = (~0), - * .spiPRCM = PRCM_GSPI, - * .csControl = SPI_HW_CTRL_CS, - * .csPolarity = SPI_CS_ACTIVELOW, - * .pinMode = SPI_4PIN_MODE, - * .turboMode = SPI_TURBO_OFF, - * .scratchBufPtr = &scratchBuf, - * .defaultTxBufValue = 0, - * .rxChannelIndex = UDMA_CH6_GSPI_RX, - * .txChannelIndex = UDMA_CH7_GSPI_TX, - * .minDmaTransferSize = 100, - * .mosiPin = SPICC32XXDMA_PIN_07_MOSI, - * .misoPin = SPICC32XXDMA_PIN_06_MISO, - * .clkPin = SPICC32XXDMA_PIN_05_CLK, - * .csPin = SPICC32XXDMA_PIN_08_CS, - * }, - * ... - * }; - * @endcode - */ -typedef struct SPICC32XXDMA_HWAttrsV1 { - /*! SPICC32XXDMA Peripheral's base address */ - uint32_t baseAddr; - - /*! SPICC32XXDMA Peripheral's interrupt vector */ - uint32_t intNum; - - /*! SPICC32XXDMA Peripheral's interrupt priority */ - uint32_t intPriority; - - /*! SPI PRCM peripheral number */ - uint32_t spiPRCM; - - /*! Specify if chip select line will be controlled by SW or HW */ - uint32_t csControl; - - uint32_t csPolarity; - - /*! Set peripheral to work in 3-pin or 4-pin mode */ - uint32_t pinMode; - - /*! Enable or disable SPI TURBO mode */ - uint32_t turboMode; - - /*! Address of a scratch buffer of size uint32_t */ - uint32_t *scratchBufPtr; - - /*! Default TX value if txBuf == NULL */ - uint32_t defaultTxBufValue; - - /*! uDMA RX channel index */ - uint32_t rxChannelIndex; - - /*! uDMA TX channel index */ - uint32_t txChannelIndex; - - /*! Minimum amout of data to start a uDMA transfer */ - uint32_t minDmaTransferSize; - - /*! GSPI MOSI pin assignment */ - uint16_t mosiPin; - - /*! GSPI MISO pin assignment */ - uint16_t misoPin; - - /*! GSPI CLK pin assignment */ - uint16_t clkPin; - - /*! GSPI CS pin assignment */ - uint16_t csPin; -} SPICC32XXDMA_HWAttrsV1; - -/*! - * @brief SPICC32XXDMA Object - * - * The application must not access any member variables of this structure! - */ -typedef struct SPICC32XXDMA_Object { - HwiP_Handle hwiHandle; - Power_NotifyObj notifyObj; - SemaphoreP_Handle transferComplete; - SPI_CallbackFxn transferCallbackFxn; - SPI_Transaction *transaction; - UDMACC32XX_Handle dmaHandle; - - size_t amtDataXferred; - size_t currentXferAmt; - uint32_t bitRate; - uint32_t dataSize; - uint32_t transferTimeout; - - SPI_Mode spiMode; - SPI_TransferMode transferMode; - SPI_FrameFormat frameFormat; - - bool cancelInProgress; - bool isOpen; - uint8_t rxFifoTrigger; - uint8_t txFifoTrigger; -} SPICC32XXDMA_Object, *SPICC32XXDMA_Handle; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_spi_SPICC32XXDMA__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.c deleted file mode 100755 index 84d7ed5f522..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== SPI.c ======== - */ - -#include -#include -#include -#include - -#include -#include - -extern const SPI_Config SPI_config[]; -extern const uint_least8_t SPI_count; - -/* Default SPI parameters structure */ -const SPI_Params SPI_defaultParams = { - SPI_MODE_BLOCKING, /* transferMode */ - SPI_WAIT_FOREVER, /* transferTimeout */ - NULL, /* transferCallbackFxn */ - SPI_MASTER, /* mode */ - 1000000, /* bitRate */ - 8, /* dataSize */ - SPI_POL0_PHA0, /* frameFormat */ - NULL /* custom */ -}; - -static bool isInitialized = false; - -/* - * ======== SPI_close ======== - */ -void SPI_close(SPI_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== SPI_control ======== - */ -int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, void *controlArg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, controlArg)); -} - -/* - * ======== SPI_init ======== - */ -void SPI_init(void) -{ - uint_least8_t i; - uint_fast8_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - /* Only initialize the first SPI instance, the 2nd instance is accessed via mbed OS */ - for (i = 0; i < /*SPI_count*/1; i++) { - SPI_config[i].fxnTablePtr->initFxn((SPI_Handle)&(SPI_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== SPI_open ======== - */ -SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params) -{ - SPI_Handle handle = NULL; - - if (isInitialized && (index < SPI_count)) { - /* If params are NULL use defaults */ - if (params == NULL) { - params = (SPI_Params *) &SPI_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (SPI_Handle)&(SPI_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== SPI_Params_init ======== - */ -void SPI_Params_init(SPI_Params *params) -{ - *params = SPI_defaultParams; -} - -/* - * ======== SPI_transfer ======== - */ -bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction) -{ - return (handle->fxnTablePtr->transferFxn(handle, transaction)); -} - -/* - * ======== SPI_transferCancel ======== - */ -void SPI_transferCancel(SPI_Handle handle) -{ - handle->fxnTablePtr->transferCancelFxn(handle); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.h deleted file mode 100755 index 650b5ec318c..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.h +++ /dev/null @@ -1,889 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file SPI.h - * - * @brief SPI driver interface - * - * The SPI driver interface provides device independent APIs, data types, - * and macros. The SPI header file should be included in an application as - * follows: - * @code - * #include - * @endcode - * - * # Overview # - * The Serial Peripheral Interface (SPI) driver is a generic, full-duplex - * driver that transmits and receives data on a SPI bus. SPI is sometimes - * called SSI (Synchronous Serial Interface). - * The SPI protocol defines the format of a data transfer over the SPI bus, - * but it leaves flow control, data formatting, and handshaking mechanisms - * to higher-level software layers. - * - * The APIs in this driver serve as an interface to a typical RTOS - * application. Its purpose is to redirect the SPI APIs to specific - * driver implementations which are specified using a pointer to a - * #SPI_FxnTable. The specific SPI implementations are responsible for - * creating all the RTOS specific primitives to allow for thread-safe - * operation. - * - * The SPI driver operates on some key definitions and assumptions: - * - The driver operates transparently from the chip select. Some SPI - * controllers feature a hardware chip select to assert SPI slave - * peripherals. See the specific peripheral implementations on chip - * select requirements. - * - * - The SPI protocol does not account for a built-in handshaking mechanism - * and neither does this SPI driver. Therefore, when operating in - * ::SPI_SLAVE mode, the application must provide such a mechanism to - * ensure that the SPI slave is ready for the SPI master. The SPI slave - * must call SPI_transfer() *before* the SPI master starts transmitting. - * Some example application mechanisms could include: - * - Timed delays on the SPI master to guarantee the SPI slave is ready - * for a SPI transaction. - * - A form of GPIO flow control from the slave to the SPI master to notify - * the master when ready. - * - * # Usage # - * - * To use the SPI driver to send data over the SPI bus, the application - * calls the following APIs: - * - SPI_init(): Initialize the SPI driver. - * - SPI_Params_init(): Initialize a #SPI_Params structure with default - * values. Then change the parameters from non-default values as - * needed. - * - SPI_open(): Open an instance of the SPI driver, passing the - * initialized parameters, or NULL, and an index (described later). - * - SPI_transfer(): Transmit/receive data. This function takes a - * #SPI_Transaction argument that specifies buffers for data to be - * transmitted/received. - * - SPI_close(): De-initialize the SPI instance. - * - * The following code example opens a SPI instance as a master SPI, - * and issues a transaction. - * - * @code - * SPI_Handle spi; - * SPI_Params spiParams; - * SPI_Transaction spiTransaction; - * uint8_t transmitBuffer[MSGSIZE]; - * uint8_t receiveBuffer[MSGSIZE]; - * bool transferOK; - * - * SPI_init(); // Initialize the SPI driver - * - * SPI_Params_init(&spiParams); // Initialize SPI parameters - * spiParams.dataSize = 8; // 8-bit data size - * - * spi = SPI_open(Board_SPI0, &spiParams); - * if (spi == NULL) { - * while (1); // SPI_open() failed - * } - * - * // Fill in transmitBuffer - * - * spiTransaction.count = MSGSIZE; - * spiTransaction.txBuf = (void *)transmitBuffer; - * spiTransaction.rxBuf = (void *)receiveBuffer; - * - * transferOK = SPI_transfer(spi, &spiTransaction); - * if (!transferOK) { - * // Error in SPI or transfer already in progress. - * while (1); - * } - * @endcode - * - * More details on usage are provided in the following subsections. - * - * ### SPI Driver Configuration # - * - * In order to use the SPI APIs, the application is required - * to provide device-specific SPI configuration in the Board.c file. - * The SPI driver interface defines a configuration data structure: - * - * @code - * typedef struct SPI_Config_ { - * SPI_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } SPI_Config; - * @endcode - * - * The application must declare an array of SPI_Config elements, named - * SPI_config[]. Each element of SPI_config[] must be populated with - * pointers to a device specific SPI driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the SPI peripheral's base address, and - * the MOSI and MISO pins. Each element in SPI_config[] corresponds to - * a SPI instance, and none of the elements should have NULL pointers. - * There is no correlation between the index and the - * peripheral designation (such as SPI0 or SPI1). For example, it is - * possible to use SPI_config[0] for SPI1. - * - * Because the SPI configuration is very device dependent, you will need to - * check the doxygen for the device specific SPI implementation. There you - * will find a description of the SPI hardware attributes. Please also - * refer to the Board.c file of any of your examples to see the SPI - * configuration. - * - * ### Initializing the SPI Driver # - * - * SPI_init() must be called before any other SPI APIs. This function - * iterates through the elements of the SPI_config[] array, calling - * the element's device implementation SPI initialization function. - * - * ### SPI Parameters - * - * The #SPI_Params structure is passed to the SPI_open() call. If NULL - * is passed for the parameters, SPI_open() uses default parameters. - * A #SPI_Params structure is initialized with default values by passing - * it to SPI_Params_init(). - * Some of the SPI parameters are described below. To see brief descriptions - * of all the parameters, see #SPI_Params. - * - * #### SPI Mode - * The SPI driver operates in both SPI master and SPI slave modes. - * Logically, the implementation is identical, however the difference - * between these two modes is driven by hardware. The default mode is - * ::SPI_MASTER, but can be set to slave mode by setting ::SPI_Params.mode - * to ::SPI_SLAVE in the parameters passed to SPI_open(). See - * Master/Slave Modes for further - * details. - * - * #### SPI Transfer Mode - * The SPI driver supports two transfer modes of operation: blocking and - * callback. The transfer mode is determined by the transferMode parameter - * in the SPI_Params data structure. The SPI driver - * defaults to blocking mode, if the application does not set it. - * Once a SPI driver is opened, the only way to change the operation mode - * is to close and re-open the SPI instance with the new transfer mode. - * - * In blocking mode, a task's code execution is blocked until a SPI - * transaction has completed or a timeout has occurred. This ensures - * that only one SPI transfer operates at a given time. Other tasks requesting - * SPI transfers while a transfer is currently taking place will receive - * a FALSE return value. If a timeout occurs the transfer is canceled, the - * task is unblocked & will receive a FALSE return value. The transaction - * count field will have the amount of frames which were transferred - * successfully before the timeout. In blocking mode, transfers cannot be - * performed in software or hardware ISR context. - * - * In callback mode, a SPI transaction functions asynchronously, which - * means that it does not block code execution. After a SPI transaction - * has been completed, the SPI driver calls a user-provided hook function. - * Callback mode is supported in the execution context of tasks and - * hardware interrupt routines. However, if a SPI transaction is - * requested while a transaction is taking place, SPI_transfer() returns - * FALSE. - * - * #### SPI Frame Formats and Data Size - * The SPI driver can configure the device's SPI peripheral to transfer - * data in several SPI format options: SPI (with various polarity and phase - * settings), TI, and Micro-wire. The frame format is set with - * SPI_Params.frameFormat. Some SPI implementations may not support all frame - * formats & the SPI driver will fail to opened. Refer to the device specific - * implementation documentation for details on which frame formats are - * supported. - * - * The smallest single unit of data transmitted onto the SPI bus is called - * a SPI frame and is of size SPI_Params.dataSize. A series of SPI frames - * transmitted/received on a SPI bus is known as a SPI transaction. - * - * ### Opening the SPI Driver # - * After initializing the SPI driver by calling SPI_init(), the application - * can open a SPI instance by calling SPI_open(). This function - * takes an index into the SPI_config[] array, and a SPI parameters data - * structure. The SPI instance is specified by the index of the SPI in - * SPI_config[]. Only one SPI index can be used at a time; - * calling SPI_open() a second time with the same index previously - * passed to SPI_open() will result in an error. You can, - * though, re-use the index if the instance is closed via SPI_close(). - * - * If no SPI_Params structure is passed to SPI_open(), default values are - * used. If the open call is successful, it returns a non-NULL value. - * - * Example opening a SPI driver instance in blocking mode: - * @code - * SPI_Handle spi; - * SPI_Params spiParams; - * - * SPI_Params_init(&spiParams); - * spiParams.transferMode = SPI_MODE_BLOCKING; - * spi = SPI_open(Board_SPI0, &spiParams); - * - * if (spi == NULL) { - * // Error opening SPI - * while(1); - * } - * @endcode - * - * Example opening a SPI driver instance in callback mode: - * @code - * SPI_Handle spi; - * SPI_Params spiParams; - * - * SPI_Params_init(&spiParams); - * spiParams.transferMode = SPI_MODE_CALLBACK; - * spiParams.transferCallbackFxn = UserCallbackFxn; - * - * spi = SPI_open(Board_SPI0, &spiParams); - * if (spi == NULL) { - * // Error opening SPI - * while (1); - * } - * @endcode - * - * - * ### SPI Transactions # - * - * A SPI transaction consists of a series of SPI frames - * transmitted/received on a SPI bus. A SPI transaction is performed - * using SPI_transfer(). SPI_transfer() accepts a pointer to a - * #SPI_Transaction structure that dictates the quantity of data to be - * sent and received. - * The SPI_Transaction.txBuf and SPI_Transaction.rxBuf are both pointers - * to data buffers. If txBuf is NULL, the driver sends SPI frames with all - * data set to the default value specified in the hardware attributes. If - * rxBuf is NULL, the driver discards all SPI frames received. SPI_transfer() - * of a SPI transaction is performed atomically. - * - * @warning The use of NULL as a sentinel txBuf or rxBuf value to determine - * whether the SPI transaction includes a tx or rx component implies - * that it is not possible to perform a transmit or receive transfer - * directly from/to a buffer with a base address of 0x00000000. To support - * this rare use-case, the application will have to manually copy the - * contents of location 0x00000000 to/from a temporary buffer before/after - * the tx/rx SPI transaction. - * - * When the SPI is opened, the dataSize value determines the element types - * of txBuf and rxBuf. If the dataSize is from 4 to 8 bits, the driver - * assumes the data buffers are of type uint8_t (unsigned char). If the - * dataSize is from 8 to 16 bits, the driver assumes the data buffers are - * of type uint16_t (unsigned short). If the dataSize is greater than - * 16 bits, the driver assumes the data buffers are uint32_t (unsigned long). - * Some SPI driver implementations may not support all data sizes; refer - * to device specific SPI implementation documentation for details on - * what data sizes are supported. - * - * The optional SPI_Transaction.arg variable can only be used when the - * SPI driver has been opened in callback mode. This variable is used to - * pass a user-defined value into the user-defined callback function. - * - * SPI_transfer() always performs full-duplex SPI transactions. This means - * the SPI simultaneously receives data as it transmits data. The application - * is responsible for formatting the data to be transmitted as well as - * determining whether the data received is meaningful. - * Specifics about SPI frame formatting and data sizes are provided in - * device-specific data sheets and technical reference manuals. - * - * The following code snippets perform SPI transactions. - * - * Example transferring 6-bit SPI frames. The transmit and receive - * buffers are of type uint8_t. - * @code - * SPI_Transaction spiTransaction; - * uint8_t transmitBuffer[BUFSIZE]; - * uint8_t receiveBuffer[BUFSIZE]; - * bool transferOK; - * - * SPI_Params_init(&spiParams); - * spiParams.dataSize = 6; - * spi = SPI_open(Board_SPI0, &spiParams); - * ... - * spiTransaction.count = someIntegerValue; - * spiTransaction.txBuf = transmitBuffer; - * spiTransaction.rxBuf = receiveBuffer; - * - * transferOK = SPI_transfer(spi, &spiTransaction); - * if (!transferOK) { - * // Error in SPI or transfer already in progress. - * } - * @endcode - * - * Example transferring 12-bit SPI frames. The transmit and receive - * buffers are of type uint16_t. - * @code - * SPI_Transaction spiTransaction; - * uint16_t transmitBuffer[BUFSIZE]; - * uint16_t receiveBuffer[BUFSIZE]; - * bool transferOK; - * - * SPI_Params_init(&spiParams); - * spiParams.dataSize = 12; - * spi = SPI_open(Board_SPI0, &spiParams); - * ... - * spiTransaction.count = someIntegerValue; - * spiTransaction.txBuf = transmitBuffer; - * spiTransaction.rxBuf = receiveBuffer; - * - * transferOK = SPI_transfer(spi, &spiTransaction); - * if (!transferOK) { - * // Error in SPI or transfer already in progress. - * } - * @endcode - * - * ### Canceling a transaction # - * SPI_transferCancel() is used to cancel a SPI transaction when the driver is - * used in ::SPI_MODE_CALLBACK mode. - * - * Calling this API while no transfer is in progress has no effect. If a - * transfer is in progress, it is canceled and the callback functions is - * called. - * The ::SPI_Status status field in the ::SPI_Transaction structure - * can be examined within the callback to determine if the transaction - * succeeded. - * - * Example: - * @code - * SPI_transferCancel(spi); - * @endcode - * - * - *

Master/Slave Modes

- * This SPI driver functions in both SPI master and SPI slave modes. - * Logically, the implementation is identical, however the difference between - * these two modes is driven by hardware. As a SPI master, the peripheral is - * in control of the clock signal and therefore will commence communications - * to the SPI slave immediately. As a SPI slave, the SPI driver prepares - * the peripheral to transmit and receive data in a way such that the - * peripheral is ready to transfer data when the SPI master initiates a - * transaction. - * - * ### Asserting on Chip Select - * The SPI protocol requires that the SPI master asserts a SPI slave's chip - * select pin prior to starting a SPI transaction. While this protocol is - * generally followed, various types of SPI peripherals have different - * timing requirements as to when and for how long the chip select pin must - * remain asserted for a SPI transaction. - * - * Commonly, the SPI master uses a hardware chip select to assert and - * de-assert the SPI slave for every data frame. In other cases, a SPI slave - * imposes the requirement of asserting the chip select over several SPI - * data frames. This is generally accomplished by using a regular, - * general-purpose output pin. Due to the complexity of such SPI peripheral - * implementations, this SPI driver has been designed to operate - * transparently to the SPI chip select. When the hardware chip - * select is used, the peripheral automatically selects/enables the - * peripheral. When using a software chip select, the application needs to - * handle the proper chip select and pin configuration. Chip select support - * will vary per SPI peripheral, refer to the device specific implementation - * documentation for details on chip select support. - * - * - _Hardware chip select_ No additional action by the application is - * required. - * - _Software chip select_ The application needs to handle the chip select - * assertion and de-assertion for the proper SPI peripheral. - * - * # Implementation # - * - * This module serves as the main interface for RTOS applications. Its - * purpose is to redirect the module's APIs to specific peripheral - * implementations which are specified using a pointer to a #SPI_FxnTable. - * - * The SPI driver interface module is joined (at link time) to an - * array of SPI_Config data structures named *SPI_config*. - * The SPI_config array is implemented in the application with each entry - * being an instance of a SPI peripheral. Each entry in *SPI_config* contains - * the following: - * - (SPI_FxnTable *) A pointer to a set of functions that implement a - * SPI peripheral. - * - (void *) A data object that is associated with the SPI_FxnTable. - * - (void *) The hardware attributes that are associated with the - * SPI_FxnTable. - * - ******************************************************************************* - */ - -#ifndef ti_drivers_SPI__include -#define ti_drivers_SPI__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * @defgroup SPI_CONTROL SPI_control command and status codes - * These SPI macros are reservations for SPI.h - * @{ - */ - -/*! - * Common SPI_control command code reservation offset. - * SPI driver implementations should offset command codes with SPI_CMD_RESERVED - * growing positively - * - * Example implementation specific command codes: - * @code - * #define SPIXYZ_CMD_COMMAND0 SPI_CMD_RESERVED + 0 - * #define SPIXYZ_CMD_COMMAND1 SPI_CMD_RESERVED + 1 - * @endcode - */ -#define SPI_CMD_RESERVED (32) - -/*! - * Common SPI_control status code reservation offset. - * SPI driver implementations should offset status codes with - * SPI_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define SPIXYZ_STATUS_ERROR0 SPI_STATUS_RESERVED - 0 - * #define SPIXYZ_STATUS_ERROR1 SPI_STATUS_RESERVED - 1 - * #define SPIXYZ_STATUS_ERROR2 SPI_STATUS_RESERVED - 2 - * @endcode - */ -#define SPI_STATUS_RESERVED (-32) - -/** - * @defgroup SPI_STATUS Status Codes - * SPI_STATUS_* macros are general status codes returned by SPI_control() - * @{ - * @ingroup SPI_CONTROL - */ - -/*! - * @brief Successful status code returned by SPI_control(). - * - * SPI_control() returns SPI_STATUS_SUCCESS if the control code was executed - * successfully. - */ -#define SPI_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by SPI_control(). - * - * SPI_control() returns SPI_STATUS_ERROR if the control code was not executed - * successfully. - */ -#define SPI_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by SPI_control() for undefined - * command codes. - * - * SPI_control() returns SPI_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define SPI_STATUS_UNDEFINEDCMD (-2) -/** @}*/ - -/** - * @defgroup SPI_CMD Command Codes - * SPI_CMD_* macros are general command codes for SPI_control(). Not all SPI - * driver implementations support these command codes. - * @{ - * @ingroup SPI_CONTROL - */ - -/* Add SPI_CMD_ here */ - -/** @}*/ - -/** @}*/ - -/*! - * @brief Wait forever define - */ -#define SPI_WAIT_FOREVER (~(0U)) - -/*! - * @brief A handle that is returned from a SPI_open() call. - */ -typedef struct SPI_Config_ *SPI_Handle; - -/*! - * @brief Status codes that are set by the SPI driver. - */ -typedef enum SPI_Status_ { - SPI_TRANSFER_COMPLETED = 0, /*!< SPI transfer completed */ - SPI_TRANSFER_STARTED, /*!< SPI transfer started and in progress */ - SPI_TRANSFER_CANCELED, /*!< SPI transfer was canceled */ - SPI_TRANSFER_FAILED, /*!< SPI transfer failed */ - SPI_TRANSFER_CSN_DEASSERT, /*!< SPI chip select was de-asserted */ - SPI_TRANSFER_PEND_CSN_ASSERT, /*!< SPI transfer is pending until the chip select is asserted */ - SPI_TRANSFER_QUEUED /*!< SPI transfer added to transaction queue */ -} SPI_Status; - -/*! - * @brief - * A ::SPI_Transaction data structure is used with SPI_transfer(). It indicates - * how many ::SPI_FrameFormat frames are sent and received from the buffers - * pointed to txBuf and rxBuf. - * The arg variable is an user-definable argument which gets passed to the - * ::SPI_CallbackFxn when the SPI driver is in ::SPI_MODE_CALLBACK. - */ -typedef struct SPI_Transaction_ { - /* User input (write-only) fields */ - size_t count; /*!< Number of frames for this transaction */ - void *txBuf; /*!< void * to a buffer with data to be transmitted */ - void *rxBuf; /*!< void * to a buffer to receive data */ - void *arg; /*!< Argument to be passed to the callback function */ - - /* User output (read-only) fields */ - SPI_Status status; /*!< Status code set by SPI_transfer */ - - void *nextPtr; /*!< Field used internally by the driver and must - never be accessed by the application. */ -} SPI_Transaction; - -/*! - * @brief The definition of a callback function used by the SPI driver - * when used in ::SPI_MODE_CALLBACK - * - * @param SPI_Handle SPI_Handle - * @param SPI_Transaction* SPI_Transaction* - */ -typedef void (*SPI_CallbackFxn) (SPI_Handle handle, - SPI_Transaction *transaction); -/*! - * @brief - * Definitions for various SPI modes of operation. - */ -typedef enum SPI_Mode_ { - SPI_MASTER = 0, /*!< SPI in master mode */ - SPI_SLAVE = 1 /*!< SPI in slave mode */ -} SPI_Mode; - -/*! - * @brief - * Definitions for various SPI data frame formats. - */ -typedef enum SPI_FrameFormat_ { - SPI_POL0_PHA0 = 0, /*!< SPI mode Polarity 0 Phase 0 */ - SPI_POL0_PHA1 = 1, /*!< SPI mode Polarity 0 Phase 1 */ - SPI_POL1_PHA0 = 2, /*!< SPI mode Polarity 1 Phase 0 */ - SPI_POL1_PHA1 = 3, /*!< SPI mode Polarity 1 Phase 1 */ - SPI_TI = 4, /*!< TI mode (not supported on all - implementations) */ - SPI_MW = 5 /*!< Micro-wire mode (not supported on all - implementations) */ -} SPI_FrameFormat; - -/*! - * @brief - * - * SPI transfer mode determines the whether the SPI controller operates - * synchronously or asynchronously. In ::SPI_MODE_BLOCKING mode SPI_transfer() - * blocks code execution until the SPI transaction has completed. In - * ::SPI_MODE_CALLBACK SPI_transfer() does not block code execution and instead - * calls a ::SPI_CallbackFxn callback function when the transaction has - * completed. - */ -typedef enum SPI_TransferMode_ { - /*! - * SPI_transfer() blocks execution. This mode can only be used when called - * within a Task context - */ - SPI_MODE_BLOCKING, - /*! - * SPI_transfer() does not block code execution and will call a - * ::SPI_CallbackFxn. This mode can be used in a Task, software or hardware - * interrupt context. - */ - SPI_MODE_CALLBACK -} SPI_TransferMode; - -/*! - * @brief SPI Parameters - * - * SPI Parameters are used to with the SPI_open() call. Default values for - * these parameters are set using SPI_Params_init(). - * - * @sa SPI_Params_init() - */ -typedef struct SPI_Params_ { - SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ - uint32_t transferTimeout; /*!< Transfer timeout in system - ticks */ - SPI_CallbackFxn transferCallbackFxn;/*!< Callback function pointer */ - SPI_Mode mode; /*!< Master or Slave mode */ - uint32_t bitRate; /*!< SPI bit rate in Hz */ - uint32_t dataSize; /*!< SPI data frame size in bits */ - SPI_FrameFormat frameFormat; /*!< SPI frame format */ - void *custom; /*!< Custom argument used by driver - implementation */ -} SPI_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_close(). - */ -typedef void (*SPI_CloseFxn) (SPI_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_control(). - */ -typedef int_fast16_t (*SPI_ControlFxn) (SPI_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_init(). - */ -typedef void (*SPI_InitFxn) (SPI_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_open(). - */ -typedef SPI_Handle (*SPI_OpenFxn) (SPI_Handle handle, SPI_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_transfer(). - */ -typedef bool (*SPI_TransferFxn) (SPI_Handle handle, - SPI_Transaction *transaction); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_transferCancel(). - */ -typedef void (*SPI_TransferCancelFxn) (SPI_Handle handle); - -/*! - * @brief The definition of a SPI function table that contains the - * required set of functions to control a specific SPI driver - * implementation. - */ -typedef struct SPI_FxnTable_ { - /*! Function to close the specified peripheral */ - SPI_CloseFxn closeFxn; - - /*! Function to implementation specific control function */ - SPI_ControlFxn controlFxn; - - /*! Function to initialize the given data object */ - SPI_InitFxn initFxn; - - /*! Function to open the specified peripheral */ - SPI_OpenFxn openFxn; - - /*! Function to initiate a SPI data transfer */ - SPI_TransferFxn transferFxn; - - /*! Function to cancel SPI data transfer */ - SPI_TransferCancelFxn transferCancelFxn; -} SPI_FxnTable; - -/*! - * @brief SPI Global configuration - * - * The SPI_Config structure contains a set of pointers used to characterize - * the SPI driver implementation. - * - * This structure needs to be defined before calling SPI_init() and it must - * not be changed thereafter. - * - * @sa SPI_init() - */ -typedef struct SPI_Config_ { - /*! Pointer to a table of driver-specific implementations of SPI APIs */ - SPI_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} SPI_Config; - -/*! - * @brief Function to close a SPI peripheral specified by the SPI handle - * - * @pre SPI_open() has to be called first. - * - * @param handle A SPI handle returned from SPI_open() - * - * @sa SPI_open() - */ -extern void SPI_close(SPI_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * SPI_Handle. - * - * Commands for SPI_control can originate from SPI.h or from implementation - * specific SPI*.h (_SPICC26XX.h_, _SPIMSP432.h_, etc.. ) files. - * While commands from SPI.h are API portable across driver implementations, - * not all implementations may support all these commands. - * Conversely, commands from driver implementation specific SPI*.h files add - * unique driver capabilities but are not API portable across all SPI driver - * implementations. - * - * Commands supported by SPI.h follow a SPI_CMD_\ naming - * convention.
- * Commands supported by SPI*.h follow a SPI*_CMD_\ naming - * convention.
- * Each control command defines @b arg differently. The types of @b arg are - * documented with each command. - * - * See @ref SPI_CMD "SPI_control command codes" for command codes. - * - * See @ref SPI_STATUS "SPI_control return status codes" for status codes. - * - * @pre SPI_open() has to be called first. - * - * @param handle A SPI handle returned from SPI_open() - * - * @param cmd SPI.h or SPI*.h commands. - * - * @param controlArg An optional R/W (read/write) command argument - * accompanied with cmd - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa SPI_open() - */ -extern int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, - void *controlArg); - -/*! - * @brief This function initializes the SPI module. - * - * @pre The SPI_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other SPI driver APIs. This function call does not modify any - * peripheral registers. - */ -extern void SPI_init(void); - -/*! - * @brief This function opens a given SPI peripheral. - * - * @pre SPI controller has been initialized using SPI_init() - * - * @param index Logical peripheral number for the SPI indexed into - * the SPI_config table - * - * @param params Pointer to an parameter block, if NULL it will use - * default values. All the fields in this structure are - * RO (read-only). - * - * @return A SPI_Handle on success or a NULL on an error or if it has been - * opened already. - * - * @sa SPI_init() - * @sa SPI_close() - */ -extern SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params); - -/*! - * @brief Function to initialize the SPI_Params struct to its defaults - * - * @param params An pointer to SPI_Params structure for - * initialization - * - * Defaults values are: - * transferMode = SPI_MODE_BLOCKING - * transferTimeout = SPI_WAIT_FOREVER - * transferCallbackFxn = NULL - * mode = SPI_MASTER - * bitRate = 1000000 (Hz) - * dataSize = 8 (bits) - * frameFormat = SPI_POL0_PHA0 - */ -extern void SPI_Params_init(SPI_Params *params); - -/*! - * @brief Function to perform SPI transactions - * - * If the SPI is in ::SPI_MASTER mode, it will immediately start the - * transaction. If the SPI is in ::SPI_SLAVE mode, it prepares the driver for - * a transaction with a SPI master device. The device will then wait until - * the master begins the transfer. - * - * In ::SPI_MODE_BLOCKING, %SPI_transfer() will block task execution until the - * transaction has completed or a timeout has occurred. - * - * In ::SPI_MODE_CALLBACK, %SPI_transfer() does not block task execution, but - * calls a ::SPI_CallbackFxn once the transfer has finished. This makes - * %SPI_tranfer() safe to be used within a Task, software or hardware - * interrupt context. - * - * From calling %SPI_transfer() until transfer completion, the SPI_Transaction - * structure must stay persistent and must not be altered by application code. - * It is also forbidden to modify the content of the SPI_Transaction.txBuffer - * during a transaction, even though the physical transfer might not have - * started yet. Doing this can result in data corruption. This is especially - * important for slave operations where %SPI_transfer() might be called a long - * time before the actual data transfer begins. - * - * @param handle A SPI_Handle - * - * @param transaction A pointer to a SPI_Transaction. All of the fields within - * transaction except SPI_Transaction.count and - * SPI_Transaction.status are WO (write-only) unless - * otherwise noted in the driver implementations. If a - * transaction timeout has occurred, SPI_Transaction.count - * will contain the number of frames that were transferred. - * Neither is it allowed to modify the transaction object nor - * the content of SPI_Transaction.txBuffer until the transfer - * has completed. - * - * @return true if started successfully; else false - * - * @sa SPI_open - * @sa SPI_transferCancel - */ -extern bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction); - -/*! - * @brief Function to cancel SPI transactions - * - * In ::SPI_MODE_BLOCKING, SPI_transferCancel has no effect. - * - * In ::SPI_MODE_CALLBACK, SPI_transferCancel() will stop an SPI transfer if - * if one is in progress. - * If a transaction was in progress, its callback function will be called - * in context from which this API is called from. The ::SPI_CallbackFxn - * function can determine if the transaction was successful or not by reading - * the ::SPI_Status status value in the ::SPI_Transaction structure. - * - * @param handle A SPI_Handle - * - * @sa SPI_open - * @sa SPI_transfer - */ -extern void SPI_transferCancel(SPI_Handle handle); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_SPI__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.c deleted file mode 100644 index 9abfbda61e2..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.c +++ /dev/null @@ -1,605 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -/* - * This macro is used to determine a logical shift value for the - * timerState.bitMask. Each timer peripheral occupies two bits in - * timerState.bitMask. - * - * The timer peripherals' base addresses have an offset of 0x1000 starting at - * 0x40030000. That byte is masked using 0xF000 which can result in a value - * ranging from 0x0000 to 0x3000 for this particular hardware instance. This - * value is then shifted right by 12 into the LSB. Lastly, the value is - * multiplied by two because there are two bits in the timerState.bitMask for - * each timer. The value returned is used for the logical shift. - */ -#define timerMaskShift(baseAddress) ((((baseAddress) & 0XF000) >> 12) * 2) - -void TimerCC32XX_close(Timer_Handle handle); -int_fast16_t TimerCC32XX_control(Timer_Handle handle, - uint_fast16_t cmd, void *arg); -uint32_t TimerCC32XX_getCount(Timer_Handle handle); -void TimerCC32XX_init(Timer_Handle handle); -Timer_Handle TimerCC32XX_open(Timer_Handle handle, Timer_Params *params); -int32_t TimerCC32XX_start(Timer_Handle handle); -void TimerCC32XX_stop(Timer_Handle handle); - -/* Internal static Functions */ -static void initHw(Timer_Handle handle); -static void getPrescaler(Timer_Handle handle); -static uint32_t getPowerMgrId(uint32_t baseAddress); -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); -static void TimerCC32XX_hwiIntFunction(uintptr_t arg); - -/* Function table for TimerCC32XX implementation */ -const Timer_FxnTable TimerCC32XX_fxnTable = { - .closeFxn = TimerCC32XX_close, - .openFxn = TimerCC32XX_open, - .startFxn = TimerCC32XX_start, - .stopFxn = TimerCC32XX_stop, - .initFxn = TimerCC32XX_init, - .getCountFxn = TimerCC32XX_getCount, - .controlFxn = TimerCC32XX_control -}; - -/* - * Internal Timer status structure - * - * bitMask: Each timer peripheral occupies two bits in the bitMask. The least - * significant bit represents the first half width timer, TimerCC32XX_timer16A - * and the most significant bit represents the second half width timer, - * TimerCC32XX_timer16B. If the full width timer, TimerCC32XX_timer32, is used, - * both bits are set to 1. - - * 31 - 8 7 - 6 5 - 4 3 - 2 1 - 0 - * ------------------------------------------------ - * | Reserved | Timer3 | Timer2 | Timer1 | Timer0 | - * ------------------------------------------------ - */ -static struct { - uint32_t bitMask; -} timerState; - -/* - * ======== initHw ======== - */ -static void initHw(Timer_Handle handle) -{ - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_Object const *object = handle->object; - - /* Ensure the timer is disabled */ - TimerDisable(hwAttrs->baseAddress, object->timer); - - if (object->timer == TIMER_A) { - - HWREG(hwAttrs->baseAddress + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD; - } - else { - - HWREG(hwAttrs->baseAddress + TIMER_O_TBMR) = TIMER_TBMR_TBMR_PERIOD; - } - - if (hwAttrs->subTimer == TimerCC32XX_timer32) { - - HWREG(hwAttrs->baseAddress + TIMER_O_CFG) = TIMER_CFG_32_BIT_TIMER; - } - else { - - HWREG(hwAttrs->baseAddress + TIMER_O_CFG) = TIMER_CFG_16_BIT; - } - - /* Disable all interrupts */ - HWREG(hwAttrs->baseAddress + TIMER_O_IMR) = ~object->timer; - - /* Writing the PSR Register has no effect for full width 32-bit mode */ - TimerPrescaleSet(hwAttrs->baseAddress, object->timer, object->prescaler); - TimerLoadSet(hwAttrs->baseAddress, object->timer, object->period); - - /* This function controls the stall response for the timer. When true, - * the timer stops counting if the processor enters debug mode. The - * default setting for the hardware is false. - */ - TimerControlStall(hwAttrs->baseAddress, object->timer, true); -} - -/* - * ========= getPrescaler ========= - * This function calculates the prescaler and timer interval load register - * for a half timer. The handle is assumed to contain a object->period which - * represents the number of clock cycles in the desired period. The calling - * function, TimerCC32XX_open() checks for overflow before calling this function. - * Therefore, this function is guaranteed to never fail. - */ -static void getPrescaler(Timer_Handle handle) -{ - TimerCC32XX_Object *object = handle->object; - uint32_t bestDiff = ~0, bestPsr = 0, bestIload = 0; - uint32_t diff, intervalLoad, prescaler; - - /* Loop over the 8-bit prescaler */ - for (prescaler = 1; prescaler < 256; prescaler++) { - - /* Calculate timer interval load */ - intervalLoad = object->period / (prescaler + 1); - - /* Will this fit in 16-bits? */ - if (intervalLoad > (uint16_t) ~0) { - continue; - } - - /* How close is the intervalLoad to what we actually want? */ - diff = object->period - intervalLoad * (prescaler + 1); - - /* If it is closer to what we want */ - if (diff <= bestDiff) { - - /* If its a perfect match */ - if (diff == 0) { - object->period = intervalLoad; - object->prescaler = prescaler; - - return; - } - - /* Snapshot in case we don't find something better */ - bestDiff = diff; - bestPsr = prescaler; - bestIload = intervalLoad; - } - } - - /* Never found a perfect match, settle for the best */ - object->period = bestIload; - object->prescaler = bestPsr; -} - -/* - * ======== getPowerMgrId ======== - */ -static uint32_t getPowerMgrId(uint32_t baseAddress) -{ - switch (baseAddress) { - - case TIMERA0_BASE: - - return (PowerCC32XX_PERIPH_TIMERA0); - - case TIMERA1_BASE: - - return (PowerCC32XX_PERIPH_TIMERA1); - - case TIMERA2_BASE: - - return (PowerCC32XX_PERIPH_TIMERA2); - - case TIMERA3_BASE: - - return (PowerCC32XX_PERIPH_TIMERA3); - - default: - - return ((uint32_t) -1); - } -} - -/* - * ======== postNotifyFxn ======== - * This functions is called when a transition from LPDS mode is made. - * clientArg should be a handle of a previously opened Timer instance. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - initHw((Timer_Handle) clientArg); - - return (Power_NOTIFYDONE); -} - -/* - * ======== TimerCC32XX_allocateTimerResource ======== - */ -bool TimerCC32XX_allocateTimerResource(uint32_t baseAddress, - TimerCC32XX_SubTimer subTimer) -{ - uintptr_t key; - uint32_t mask; - uint32_t powerMgrId; - bool status; - - powerMgrId = getPowerMgrId(baseAddress); - - if (powerMgrId == (uint32_t) -1) { - - return (false); - } - - mask = subTimer << timerMaskShift(baseAddress); - - key = HwiP_disable(); - - if (timerState.bitMask & mask) { - - status = false; - } - else { - - Power_setDependency(powerMgrId); - timerState.bitMask = timerState.bitMask | mask; - status = true; - } - - HwiP_restore(key); - - return (status); -} - -/* - * ======== TimerCC32XX_close ======== - */ -void TimerCC32XX_close(Timer_Handle handle) -{ - TimerCC32XX_Object *object = handle->object; - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - - /* Stopping the Timer before closing it */ - TimerCC32XX_stop(handle); - - Power_unregisterNotify(&(object->notifyObj)); - - if (object->hwiHandle) { - - HwiP_clearInterrupt(hwAttrs->intNum); - HwiP_delete(object->hwiHandle); - object->hwiHandle = NULL; - } - - if (object->timerSem) { - - SemaphoreP_delete(object->timerSem); - object->timerSem = NULL; - } - - TimerCC32XX_freeTimerResource(hwAttrs->baseAddress, hwAttrs->subTimer); -} - -/* - * ======== TimerCC32XX_control ======== - */ -int_fast16_t TimerCC32XX_control(Timer_Handle handle, - uint_fast16_t cmd, void *arg) -{ - return (Timer_STATUS_UNDEFINEDCMD); -} - -/* - * ======== TimerCC32XX_freeTimerResource ======== - */ -void TimerCC32XX_freeTimerResource(uint32_t baseAddress, - TimerCC32XX_SubTimer subTimer) -{ - uintptr_t key; - uint32_t mask; - - mask = subTimer << timerMaskShift(baseAddress); - - key = HwiP_disable(); - - timerState.bitMask = (timerState.bitMask & ~mask); - - Power_releaseDependency(getPowerMgrId(baseAddress)); - - HwiP_restore(key); -} - -/* - * ======== TimerCC32XX_getCount ======== - */ -uint32_t TimerCC32XX_getCount(Timer_Handle handle) -{ - TimerCC32XX_HWAttrs const *hWAttrs = handle->hwAttrs; - TimerCC32XX_Object const *object = handle->object; - uint32_t count; - - if (object->timer == TIMER_A) { - count = HWREG(hWAttrs->baseAddress + TIMER_O_TAR); - } - else { - count = HWREG(hWAttrs->baseAddress + TIMER_O_TBR); - } - - /* Virtual up counter */ - count = object->period - count; - - return (count); -} - -/* - * ======== TimerCC32XX_hwiIntFunction ======== - */ -void TimerCC32XX_hwiIntFunction(uintptr_t arg) -{ - Timer_Handle handle = (Timer_Handle) arg; - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_Object const *object = handle->object; - uint32_t interruptMask; - - /* Only clear the interrupt for this->object->timer */ - interruptMask = object->timer & (TIMER_TIMA_TIMEOUT | TIMER_TIMB_TIMEOUT); - TimerIntClear(hwAttrs->baseAddress, interruptMask); - - /* Hwi is not created when using Timer_FREE_RUNNING */ - if (object->mode != Timer_CONTINUOUS_CALLBACK) { - TimerCC32XX_stop(handle); - } - - if (object-> mode != Timer_ONESHOT_BLOCKING) { - object->callBack(handle); - } -} - -/* - * ======== TimerCC32XX_init ======== - */ -void TimerCC32XX_init(Timer_Handle handle) -{ - return; -} - -/* - * ======== TimerCC32XX_open ======== - */ -Timer_Handle TimerCC32XX_open(Timer_Handle handle, Timer_Params *params) -{ - TimerCC32XX_Object *object = handle->object; - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - SemaphoreP_Params semParams; - HwiP_Params hwiParams; - ClockP_FreqHz clockFreq; - - /* Check for valid parameters */ - if (((params->timerMode == Timer_ONESHOT_CALLBACK || - params->timerMode == Timer_CONTINUOUS_CALLBACK) && - params->timerCallback == NULL) || - params->period == 0) { - - return (NULL); - } - - if (!TimerCC32XX_allocateTimerResource(hwAttrs->baseAddress, - hwAttrs->subTimer)) { - - return (NULL); - } - - Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t) handle); - - object->mode = params->timerMode; - object->isRunning = false; - object->callBack = params->timerCallback; - object->period = params->period; - object->prescaler = 0; - - if (hwAttrs->subTimer == TimerCC32XX_timer16B) { - - object->timer = TIMER_B; - } - else { - - object->timer = TIMER_A; - } - - if (object->mode != Timer_FREE_RUNNING) { - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t) handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, - TimerCC32XX_hwiIntFunction, &hwiParams); - - if (object->hwiHandle == NULL) { - - TimerCC32XX_close(handle); - - return (NULL); - } - - } - - /* Creating the semaphore if mode is blocking */ - if (params->timerMode == Timer_ONESHOT_BLOCKING) { - - SemaphoreP_Params_init(&semParams); - semParams.mode = SemaphoreP_Mode_BINARY; - object->timerSem = SemaphoreP_create(0, &semParams); - - if (object->timerSem == NULL) { - - TimerCC32XX_close(handle); - - return (NULL); - } - } - - /* Formality; CC32XX System Clock fixed to 80.0 MHz */ - ClockP_getCpuFreq(&clockFreq); - - if (params->periodUnits == Timer_PERIOD_US) { - - /* Checks if the calculated period will fit in 32-bits */ - if (object->period >= ((uint32_t) ~0) / (clockFreq.lo / 1000000)) { - - TimerCC32XX_close(handle); - - return (NULL); - } - - object->period = object->period * (clockFreq.lo / 1000000); - } - else if (params->periodUnits == Timer_PERIOD_HZ) { - - /* If (object->period) > clockFreq */ - if ((object->period = clockFreq.lo / object->period) == 0) { - - TimerCC32XX_close(handle); - - return (NULL); - } - } - - /* If using a half timer */ - if (hwAttrs->subTimer != TimerCC32XX_timer32) { - - if (object->period > 0xFFFF) { - - /* 24-bit resolution for the half timer */ - if (object->period >= (1 << 24)) { - - TimerCC32XX_close(handle); - - return (NULL); - } - - getPrescaler(handle); - } - } - - initHw(handle); - - return (handle); -} - -/* - * ======== TimerCC32XX_start ======== - */ -int32_t TimerCC32XX_start(Timer_Handle handle) -{ - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_Object *object = handle->object; - uint32_t interruptMask; - uintptr_t key; - - interruptMask = object->timer & (TIMER_TIMB_TIMEOUT | TIMER_TIMA_TIMEOUT); - - key = HwiP_disable(); - - if (object->isRunning) { - - HwiP_restore(key); - - return (Timer_STATUS_ERROR); - } - - object->isRunning = true; - - if (object->hwiHandle) { - - TimerIntEnable(hwAttrs->baseAddress, interruptMask); - } - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* Reload the timer */ - if (object->timer == TIMER_A) { - HWREG(hwAttrs->baseAddress + TIMER_O_TAMR) |= TIMER_TAMR_TAILD; - } - else { - HWREG(hwAttrs->baseAddress + TIMER_O_TBMR) |= TIMER_TBMR_TBILD; - } - - TimerEnable(hwAttrs->baseAddress, object->timer); - - HwiP_restore(key); - - if (object->mode == Timer_ONESHOT_BLOCKING) { - - /* Pend forever, ~0 */ - SemaphoreP_pend(object->timerSem, ~0); - } - - return (Timer_STATUS_SUCCESS); -} - -/* - * ======== TimerCC32XX_stop ======== - */ -void TimerCC32XX_stop(Timer_Handle handle) -{ - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_Object *object = handle->object; - uint32_t interruptMask; - uintptr_t key; - bool flag = false; - - interruptMask = object->timer & (TIMER_TIMB_TIMEOUT | TIMER_TIMA_TIMEOUT); - - key = HwiP_disable(); - - if (object->isRunning) { - - object->isRunning = false; - - /* Post the Semaphore when called from the Hwi */ - if (object->mode == Timer_ONESHOT_BLOCKING) { - flag = true; - } - - TimerDisable(hwAttrs->baseAddress, object->timer); - TimerIntDisable(hwAttrs->baseAddress, interruptMask); - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - } - - HwiP_restore(key); - - if (flag) { - SemaphoreP_post(object->timerSem); - } -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.h deleted file mode 100644 index f8f3a0de91f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file TimerCC32XX.h - * @brief Timer driver interface for CC32XX devices - * - * # Operation # - * This driver implements half and full width general purpose timers for the - * CC32XX device. For CC32XX devices, the system clock is 80 MHz and a 16-bit - * timer has an 8-bit prescaler. The desired period may not always be - * achieved due to hardware limitations, such as the aforementioned. The timer - * resolution is limited to 12.5ns due to the 80 MHz clock. A timer period no - * greater than 209,714us can be achieved when operating in 16-bit mode. - * Similarly, a period no greater than 53,687,090us can be achieved when - * operating in 32-bit mode. The same time constraints apply to the 16-bit - * timer when attempting to use a frequency less than 5 Hertz. For additional - * details, refer to the device's technical reference manual. - * - * The timer always operates in count down mode. When using a half width timer, - * an 8-bit prescaler will be implemented by the driver if necessary. If the - * timer is operating in Timer_FREE_RUNNING, the timer will count down from the - * specified period to 0 before restarting. - * - * When using a half width timer, Timer_getCount() will return the - * value of the counter in bits 15:0 and bits 23:16 will contain the - * current free-running value of the prescaler. Bits 31:24 are always 0. - * When using a full width timer, Timer_getCount() will return the - * the value of the 32-bit timer. - * - * #Timer_ONESHOT_CALLBACK is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. When the timer interrupt - * is triggered, the specified callback function will be called. The timer - * will not generate another interrupt unless Timer_start() is called again. - * Calling Timer_stop() or Timer_close() after Timer_start() but, before the - * timer interrupt, will prevent the specified callback from ever being - * invoked. - * - * #Timer_ONESHOT_BLOCKING is a blocking call. A semaphore is used to block - * the calling thead's execution until the timer generates an interrupt. If - * Timer_stop() is called, the calling thread will become unblocked - * immediately. The behavior of the timer in this mode is similar to a sleep - * function. - * - * #Timer_CONTINUOUS_CALLBACK is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. When the timer interrupt is - * treiggered, the specified callback function will be called. The timer is - * automatically restarted and will continue to periodically generate - * interrupts until Timer_stop() is called. - * - * #Timer_FREE_RUNNING is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. The timer will not - * generate an interrupt in this mode. The timer will count down from the - * specified period until it reaches 0. The timer will automatically reload - * the period and start over. The timer will continue running until - * Timer_stop() is called. - * - * # Resource Allocation # - * Each general purpose timer block contains two timers, Timer A and Timer B, - * that can be configured to operate independently; or concatenated to operate - * as one 32-bit timer. This behavior is managed through a set of resource - * allocation APIs. For example, the TimerCC32XX_allocateTimerResource API - * will allocate a timer for exclusive use. Any attempt to allocate this - * resource in the future will result in a false value being returned from the - * allocation API. To free a timer resource, the TimerCC32XX_freeTimerResource - * is used. The application is not responsible for calling these allocation - * APIs directly. - * - * ============================================================================ - */ - -#ifndef ti_drivers_timer_TimerCC32XX__include -#define ti_drivers_timer_TimerCC32XX__include - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#include -#include -#include -#include - -/*! - * @def TimerCC32XX_SubTimer - * - * @brief Sub-timers on the CC32XX - * - * The timer peripheral supports full width and half width timer operation. - * Use the definitions in this enumerated type to specify a full width timer - * (32-bit) or half width timer (16-bit) in the hardware attributes. There are - * two half width timers per single timer peripheral. A 16-bit timer on this - * device has an 8-bit prescaler. - */ -typedef enum TimerCC32XX_SubTimer_ { - TimerCC32XX_timer16A = 0x0001, /*!< Half width timer A */ - TimerCC32XX_timer16B = 0x0002, /*!< Half width timer B */ - TimerCC32XX_timer32 = 0x0003, /*!< Full width timer */ -} TimerCC32XX_SubTimer; - -extern const Timer_FxnTable TimerCC32XX_fxnTable; - -/*! - * @brief TimerCC32XX Hardware Attributes - * - * Timer hardware attributes that tell the TimerCC32XX driver specific hardware - * configurations and interrupt/priority settings. - * - * A sample structure is shown below: - * @code - * const TimerCC32XX_HWAttrs timerCC32XXHWAttrs[] = - * { - * { - * .baseAddress = TIMERA0_BASE, - * .subTimer = TimerCC32XX_timer32, - * .intNum = INT_TIMERA0A, - * .intPriority = ~0 - * }, - * { - * .baseAddress = TIMERA1_BASE, - * .subTimer = TimerCC32XX_timer16A, - * .intNum = INT_TIMERA1A, - * .intPriority = ~0 - * }, - * { - * .baseAddress = TIMERA1_BASE, - * .subTimer = TimerCC32XX_timer16B, - * .intNum = INT_TIMERA1B, - * .intPriority = ~0 - * } - * }; - * @endcode - */ -typedef struct TimerCC32XX_HWAttrs_ { - /*! The base address of the timer peripheral. */ - uint32_t baseAddress; - - /*! Specifies a full width timer or half-width timer. */ - TimerCC32XX_SubTimer subTimer; - - /*! The hardware interrupt number for the timer peripheral. */ - uint32_t intNum; - - /*! The interrupt priority. */ - uint32_t intPriority; -} TimerCC32XX_HWAttrs; - -/*! - * @brief TimerCC32XX_Object - * - * The application must not access any member variables of this structure! - */ -typedef struct TimerCC32XX_Object_ { - HwiP_Handle hwiHandle; - Power_NotifyObj notifyObj; - SemaphoreP_Handle timerSem; - Timer_CallBackFxn callBack; - Timer_Mode mode; - uint32_t timer; - uint32_t period; - uint32_t prescaler; - bool isRunning; -} TimerCC32XX_Object; - -/*! - * @brief Function to allocate a timer peripheral. - * - * This function is intended to be used by any driver which implements a - * timer hardware peripheral. Calling this function will enable power to the - * timer peripheral specified by the parameter, baseAddress. - * - * @param baseAddress The base address of a timer hardware peripheral. - * - * @param subTimer The TimerCC32XX_subTimer to be allocated. - * - * @return A bool returning true if the timer resource was successfully - * allocated. If the base address is not valid or if the resource is - * not available, false is returned. - * - * @sa TimerCC32XX_freeTimerResource() - */ -extern bool TimerCC32XX_allocateTimerResource(uint32_t baseAddress, - TimerCC32XX_SubTimer subTimer); - -/*! - * @brief Function to de-allocate a timer peripheral. - * - * This function is intended to be used by any driver which implements a - * timer hardware peripheral. Calling this function will disable power to the - * timer peripheral specified by the parameter, baseAddress, if and only if - * the timer peripheral is no longer in use. - * - * @pre A successful call to TimerCC32XX_allocateTimerResource() using the - * baseAddress and subTimer must have been made prior to calling this - * API. - * - * @param baseAddress The base address of a timer hardware peripheral. - * - * @param subTimer The TimerCC32XX_subTimer to be freed. - * - * @sa TimerCC32XX_allocateTimerResource() - */ -extern void TimerCC32XX_freeTimerResource(uint32_t baseAddress, - TimerCC32XX_SubTimer subTimer); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_timer_TimerCC32XX__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.c deleted file mode 100755 index 970ae162263..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2015, 2017 Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== List.c ======== - */ -#include -#include - -#include -#include -#include - -/* - * ======== List_clearList ======== - */ -void List_clearList(List_List *list) -{ - uintptr_t key; - - key = HwiP_disable(); - - list->head = list->tail = NULL; - - HwiP_restore(key); -} - - - -/* - * ======== List_get ======== - */ -List_Elem *List_get(List_List *list) -{ - List_Elem *elem; - uintptr_t key; - - key = HwiP_disable(); - - elem = list->head; - - /* See if the List was empty */ - if (elem != NULL) { - list->head = elem->next; - if (elem->next != NULL) { - elem->next->prev = NULL; - } - else { - list->tail = NULL; - } - } - - HwiP_restore(key); - - return (elem); -} - - -/* - * ======== List_insert ======== - */ -void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) -{ - uintptr_t key; - - key = HwiP_disable(); - - newElem->next = curElem; - newElem->prev = curElem->prev; - if (curElem->prev != NULL) { - curElem->prev->next = newElem; - } - else { - list->head = newElem; - } - curElem->prev = newElem; - - HwiP_restore(key); -} - - -/* - * ======== List_put ======== - */ -void List_put(List_List *list, List_Elem *elem) -{ - uintptr_t key; - - key = HwiP_disable(); - - elem->next = NULL; - elem->prev = list->tail; - if (list->tail != NULL) { - list->tail->next = elem; - } - else { - list->head = elem; - } - - list->tail = elem; - - HwiP_restore(key); -} - -/* - * ======== List_putHead ======== - */ -void List_putHead(List_List *list, List_Elem *elem) -{ - uintptr_t key; - - key = HwiP_disable(); - - elem->next = list->head; - elem->prev = NULL; - if (list->head != NULL) { - list->head->prev = elem; - } - else { - list->tail = elem; - } - - list->head = elem; - - HwiP_restore(key); -} - -/* - * ======== List_remove ======== - */ -void List_remove(List_List *list, List_Elem *elem) -{ - uintptr_t key; - - key = HwiP_disable(); - - /* Handle the case where the elem to remove is the last one */ - if (elem->next == NULL) { - list->tail = elem->prev; - } - else { - elem->next->prev = elem->prev; - } - - /* Handle the case where the elem to remove is the first one */ - if (elem->prev == NULL) { - list->head = elem->next; - } - else { - elem->prev->next = elem->next; - } - - HwiP_restore(key); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.h deleted file mode 100755 index db99729a8c9..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file List.h - * - * @brief Linked List interface for use in drivers - * - * This module provides simple doubly-link list implementation. There are two - * main structures: - * - ::List_List: The structure that holds the start of a linked list. There - * is no API to create one. It is up to the driver to provide the structure - * itself. - * - ::List_Elem: The structure that must be in the structure that is placed - * onto a linked list. Generally it is the first field in the structure. For - * example: - * @code - * typedef struct MyStruct { - * List_Elem elem; - * void *buffer; - * } MyStruct; - * @endcode - * - * The following shows how to create a linked list with three elements. - * - * @code - * + denotes null-terminated - * _______ _______ _______ _______ - * |_______|----->|_______|----->|_______|--->|_______|--//---, - * ,----|_______| ,-|_______|<-----|_______|<---|_______|<-//-, + - * | List + elem elem elem | - * |_____________________________________________________________| - * @endcode - * - * The APIs ::List_get, ::List_put, and ::List_putHead are - * atomic. The other APIs are not necessarily atomic. In other words, when - * traversing a linked list, it is up to the application to provide - * thread-safety (e.g. HwiP_disable/restore or MutexP_pend/post). - * - * Initializing and adding an element to the tail and removing it - * @code - * typedef struct MyStruct { - * List_Elem elem; - * void *buffer; - * } MyStruct; - * - * List_List list; - * MyStruct foo; - * MyStruct *bar; - * - * List_clearList(&list); - * List_put(&list, (List_Elem *)&foo); - * bar = (MyStruct *)List_get(&list); - * @endcode - * - * The ::List_put and ::List_get APIs are used to maintain a first-in first-out - * (FIFO) linked list. - * - * The ::List_putHead and ::List_get APIs are used to maintain a last-in first-out - * (LIFO) linked list. - * - * Traversing a list from head to tail. Note: thread-safety calls are - * not shown here. - * @code - * List_List list; - * List_Elem *temp; - * - * for (temp = List_head(&list); temp != NULL; temp = List_next(temp)) { - * printf("address = 0x%x\n", temp); - * } - * @endcode - * - * Traversing a list from tail to head. Note: thread-safety calls are - * not shown here. - * @code - * List_List list; - * List_Elem *temp; - * - * for (temp = List_tail(&list); temp != NULL; temp = List_prev(temp)) { - * printf("address = 0x%x\n", temp); - * } - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_utils_List__include -#define ti_drivers_utils_List__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -typedef struct List_Elem { - struct List_Elem *next; - struct List_Elem *prev; -} List_Elem; - -typedef struct List_List { - List_Elem *head; - List_Elem *tail; -} List_List; - -/*! - * @brief Function to initialize the contents of a List_List - * - * @param list Pointer to a List_List structure that will be used to - * maintain a linked list - */ -extern void List_clearList(List_List *list); - -/*! - * @brief Function to test whether a linked list is empty - * - * @param list A pointer to a linked list - * - * @return true if empty, false if not empty - */ -static inline bool List_empty(List_List *list) -{ - return (list->head == NULL); -} - -/*! - * @brief Function to atomically get the first elem in a linked list - * - * @param list A pointer to a linked list - * - * @return Pointer the first elem in the linked list or NULL if empty - */ -extern List_Elem *List_get(List_List *list); - -/*! - * @brief Function to return the head of a linked list - * - * This function does not remove the head, it simply returns a pointer to - * it. This function is typically used when traversing a linked list. - * - * @param list A pointer to the linked list - * - * @return Pointer to the first elem in the linked list or NULL if empty - */ -static inline List_Elem *List_head(List_List *list) -{ - return (list->head); -} - -/*! - * @brief Function to insert an elem into a linked list - * - * @param list A pointer to the linked list - * - * @param newElem New elem to insert - * - * @param curElem Elem to insert the newElem in front of. - * This value cannot be NULL. - */ -extern void List_insert(List_List *list, List_Elem *newElem, - List_Elem *curElem); - -/*! - * @brief Function to return the next elem in a linked list - * - * This function does not remove the elem, it simply returns a pointer to - * next one. This function is typically used when traversing a linked list. - * - * @param elem Elem in the list - * - * @return Pointer to the next elem in linked list or NULL if at the end - */ -static inline List_Elem *List_next(List_Elem *elem) -{ - return (elem->next); -} - -/*! - * @brief Function to return the prev elem in a linked list - * - * This function does not remove the elem, it simply returns a pointer to - * prev one. This function is typically used when traversing a linked list. - * - * @param elem Elem in the list - * - * @return Pointer to the prev elem in linked list or NULL if at the beginning - */ -static inline List_Elem *List_prev(List_Elem *elem) -{ - return (elem->prev); -} - -/*! - * @brief Function to atomically put an elem onto the end of a linked list - * - * @param list A pointer to the linked list - * - * @param elem Element to place onto the end of the linked list - */ -extern void List_put(List_List *list, List_Elem *elem); - -/*! - * @brief Function to atomically put an elem onto the head of a linked list - * - * @param list A pointer to the linked list - * - * @param elem Element to place onto the beginning of the linked list - */ -extern void List_putHead(List_List *list, List_Elem *elem); - -/*! - * @brief Function to remove an elem from a linked list - * - * @param list A pointer to the linked list - * - * @param elem Element to be removed from a linked list - */ -extern void List_remove(List_List *list, List_Elem *elem); - -/*! - * @brief Function to return the tail of a linked list - * - * This function does not remove the tail, it simply returns a pointer to - * it. This function is typically used when traversing a linked list. - * - * @param list A pointer to the linked list - * - * @return Pointer to the last elem in the linked list or NULL if empty - */ -static inline List_Elem *List_tail(List_List *list) -{ - return (list->tail); -} - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_utils_List__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.c deleted file mode 100755 index ace4f012c59..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2015-2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -/* - * ======== RingBuf_construct ======== - */ -void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, - size_t bufSize) -{ - object->buffer = bufPtr; - object->length = bufSize; - object->count = 0; - object->head = bufSize - 1; - object->tail = 0; - object->maxCount = 0; -} - -/* - * ======== RingBuf_get ======== - */ -int RingBuf_get(RingBuf_Handle object, unsigned char *data) -{ - unsigned int key; - - key = HwiP_disable(); - - if (!object->count) { - HwiP_restore(key); - return -1; - } - - *data = object->buffer[object->tail]; - object->tail = (object->tail + 1) % object->length; - object->count--; - - HwiP_restore(key); - - return (object->count); -} - -/* - * ======== RingBuf_getCount ======== - */ -int RingBuf_getCount(RingBuf_Handle object) -{ - return (object->count); -} - -/* - * ======== RingBuf_isFull ======== - */ -bool RingBuf_isFull(RingBuf_Handle object) -{ - return (object->count == object->length); -} - -/* - * ======== RingBuf_getMaxCount ======== - */ -int RingBuf_getMaxCount(RingBuf_Handle object) -{ - return (object->maxCount); -} - -/* - * ======== RingBuf_peek ======== - */ -int RingBuf_peek(RingBuf_Handle object, unsigned char *data) -{ - unsigned int key; - int retCount; - - key = HwiP_disable(); - - *data = object->buffer[object->tail]; - retCount = object->count; - - HwiP_restore(key); - - return (retCount); -} - -/* - * ======== RingBuf_put ======== - */ -int RingBuf_put(RingBuf_Handle object, unsigned char data) -{ - unsigned int key; - unsigned int next; - - key = HwiP_disable(); - - if (object->count != object->length) { - next = (object->head + 1) % object->length; - object->buffer[next] = data; - object->head = next; - object->count++; - object->maxCount = (object->count > object->maxCount) ? - object->count : - object->maxCount; - } - else { - - HwiP_restore(key); - return (-1); - } - - HwiP_restore(key); - - return (object->count); -} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.h deleted file mode 100755 index 29e8c82433e..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2015, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef ti_drivers_uart_RingBuf__include -#define ti_drivers_uart_RingBuf__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -typedef struct RingBuf_Object { - unsigned char *buffer; - size_t length; - size_t count; - size_t head; - size_t tail; - size_t maxCount; -} RingBuf_Object, *RingBuf_Handle; - -/*! - * @brief Initialize circular buffer - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @param bufPtr Pointer to data buffer to be used for the circular buffer. - * The buffer is NOT stored in RingBuf_Object. - * - * @param bufSize The size of bufPtr in number of unsigned chars. - */ -void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, - size_t bufSize); - -/*! - * @brief Get an unsigned char from the end of the circular buffer and remove - * it. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @param data Pointer to an unsigned char to be filled with the data from - * the front of the circular buffer. - * - * @return Number of unsigned chars on the buffer after taking it out - * of the circular buffer. If it returns -1, the circular - * buffer was already empty and data is invalid. - */ -int RingBuf_get(RingBuf_Handle object, unsigned char *data); - -/*! - * @brief Get the number of unsigned chars currently stored on the circular - * buffer. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @return Number of unsigned chars on the circular buffer. - */ -int RingBuf_getCount(RingBuf_Handle object); - -/*! - * @brief Function to determine if the circular buffer is full or not. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @return true if circular buffer is full, else false. - */ -bool RingBuf_isFull(RingBuf_Handle object); - -/*! - * @brief A high-water mark indicating the largest number of unsigned chars - * stored on the circular buffer since it was constructed. - * - * @return Get the largest number of unsigned chars that were at one - * point in the circular buffer. - */ -int RingBuf_getMaxCount(RingBuf_Handle object); - -/*! - * @brief Get an unsigned char from the end of the circular buffer without - * removing it. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @param data Pointer to an unsigned char to be filled with the data from - * the front of the circular buffer. This function does not - * remove the data from the circular buffer. Do not evaluate - * data if the count returned is equal to 0. - * - * @return Number of unsigned chars on the circular buffer. If the - * number != 0, then data will contain the unsigned char at the - * end of the circular buffer. - */ -int RingBuf_peek(RingBuf_Handle object, unsigned char *data); - -/*! - * @brief Put an unsigned char into the end of the circular buffer. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @param data unsigned char to be placed at the end of the circular - * buffer. - * - * @return Number of unsigned chars on the buffer after it was added, - * or -1 if it's already full. - */ -int RingBuf_put(RingBuf_Handle object, unsigned char data); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_uart_RingBuf__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slneterr.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slneterr.h deleted file mode 100755 index 56e09fb5e35..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slneterr.h +++ /dev/null @@ -1,674 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#ifndef __SL_NET_ERR_H__ -#define __SL_NET_ERR_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup SlNetErr SlNetErr group - - \short Provide BSD and proprietary errors - -*/ -/*! - - \addtogroup SlNetErr - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SLNETERR_RET_CODE_OK (0L) /**< Success */ - -#define SLNETERR_GENERAL_DEVICE (-6L) /**< General device error */ - -/* BSD SOCKET ERRORS CODES */ - -#define SLNETERR_BSD_SOC_ERROR (-1L) /**< Failure */ -#define SLNETERR_BSD_ENXIO (-6L) /**< No such device or address */ -#define SLNETERR_BSD_INEXE (-8L) /**< socket command in execution */ -#define SLNETERR_BSD_EBADF (-9L) /**< Bad file number */ -#define SLNETERR_BSD_ENSOCK (-10L) /**< The system limit on the total number of open socket, has been reached */ -#define SLNETERR_BSD_EAGAIN (-11L) /**< Try again */ -#define SLNETERR_BSD_EWOULDBLOCK SLNETERR_BSD_EAGAIN -#define SLNETERR_BSD_ENOMEM (-12L) /**< Out of memory */ -#define SLNETERR_BSD_EACCES (-13L) /**< Permission denied */ -#define SLNETERR_BSD_EFAULT (-14L) /**< Bad address */ -#define SLNETERR_BSD_ECLOSE (-15L) /**< close socket operation failed to transmit all queued packets */ -#define SLNETERR_BSD_EALREADY_ENABLED (-21L) /**< Transceiver - Transceiver already ON. there could be only one */ -#define SLNETERR_BSD_EINVAL (-22L) /**< Invalid argument */ -#define SLNETERR_BSD_EAUTO_CONNECT_OR_CONNECTING (-69L) /**< Transceiver - During connection, connected or auto mode started */ -#define SLNETERR_BSD_CONNECTION_PENDING (-72L) /**< Transceiver - Device is connected, disconnect first to open transceiver */ -#define SLNETERR_BSD_EUNSUPPORTED_ROLE (-86L) /**< Transceiver - Trying to start when WLAN role is AP or P2P GO */ -#define SLNETERR_BSD_ENOTSOCK (-88L) /**< Socket operation on non-socket */ -#define SLNETERR_BSD_EDESTADDRREQ (-89L) /**< Destination address required */ -#define SLNETERR_BSD_EMSGSIZE (-90L) /**< Message too long */ -#define SLNETERR_BSD_EPROTOTYPE (-91L) /**< Protocol wrong type for socket */ -#define SLNETERR_BSD_ENOPROTOOPT (-92L) /**< Protocol not available */ -#define SLNETERR_BSD_EPROTONOSUPPORT (-93L) /**< Protocol not supported */ -#define SLNETERR_BSD_ESOCKTNOSUPPORT (-94L) /**< Socket type not supported */ -#define SLNETERR_BSD_EOPNOTSUPP (-95L) /**< Operation not supported on transport endpoint */ -#define SLNETERR_BSD_EAFNOSUPPORT (-97L) /**< Address family not supported by protocol */ -#define SLNETERR_BSD_EADDRINUSE (-98L) /**< Address already in use */ -#define SLNETERR_BSD_EADDRNOTAVAIL (-99L) /**< Cannot assign requested address */ -#define SLNETERR_BSD_ENETUNREACH (-101L) /**< Network is unreachable */ -#define SLNETERR_BSD_ECONNABORTED (-103L) /**< Software caused connection abort */ -#define SLNETERR_BSD_ECONNRESET (-104L) /**< Connection reset by peer */ -#define SLNETERR_BSD_ENOBUFS (-105L) /**< No buffer space available */ -#define SLNETERR_BSD_EOBUFF SLNETERR_BSD_ENOBUFS -#define SLNETERR_BSD_EISCONN (-106L) /**< Transport endpoint is already connected */ -#define SLNETERR_BSD_ENOTCONN (-107L) /**< Transport endpoint is not connected */ -#define SLNETERR_BSD_ESHUTDOWN (-108L) /**< Cannot send after transport endpoint shutdown */ -#define SLNETERR_BSD_ETIMEDOUT (-110L) /**< Connection timed out */ -#define SLNETERR_BSD_ECONNREFUSED (-111L) /**< Connection refused */ -#define SLNETERR_BSD_EHOSTDOWN (-112L) /**< Host is down */ -#define SLNETERR_BSD_EHOSTUNREACH (-113L) /**< No route to host */ -#define SLNETERR_BSD_EALREADY (-114L) /**< Non blocking connect in progress, try again */ - -/* ssl tls security start with -300 offset */ -#define SLNETERR_ESEC_CLOSE_NOTIFY (-300L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_UNEXPECTED_MESSAGE (-310L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_BAD_RECORD_MAC (-320L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_DECRYPTION_FAILED (-321L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_RECORD_OVERFLOW (-322L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_DECOMPRESSION_FAILURE (-330L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_HANDSHAKE_FAILURE (-340L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_NO_CERTIFICATE (-341L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_BAD_CERTIFICATE (-342L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_UNSUPPORTED_CERTIFICATE (-343L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_ILLEGAL_PARAMETER (-347L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_ACCESS_DENIED (-349L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_DECODE_ERROR (-350L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_DECRYPT_ERROR1 (-351L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_EXPORT_RESTRICTION (-360L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_PROTOCOL_VERSION (-370L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_INSUFFICIENT_SECURITY (-371L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_INTERNAL_ERROR (-380L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_USER_CANCELLED (-390L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_NO_RENEGOTIATION (-400L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_UNSUPPORTED_EXTENSION (-410L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_CERTIFICATE_UNOBTAINABLE (-411L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_UNRECOGNIZED_NAME (-412L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_BAD_CERTIFICATE_STATUS_RESPONSE (-413L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_BAD_CERTIFICATE_HASH_VALUE (-414L) /**< ssl/tls alerts */ - - -/* proprietary secure */ -#define SLNETERR_ESEC_GENERAL (-450L) /**< error secure level general error */ -#define SLNETERR_ESEC_DECRYPT (-451L) /**< error secure level, decrypt recv packet fail */ -#define SLNETERR_ESEC_CLOSED (-452L) /**< secure layer is closed by other size, tcp is still connected */ -#define SLNETERR_ESEC_SNO_VERIFY (-453L) /**< Connected without server verification */ -#define SLNETERR_ESEC_NO_CA_FILE (-454L) /**< error secure level CA file not found */ -#define SLNETERR_ESEC_MEMORY (-455L) /**< error secure level No memory space available */ -#define SLNETERR_ESEC_BAD_CA_FILE (-456L) /**< error secure level bad CA file */ -#define SLNETERR_ESEC_BAD_CERT_FILE (-457L) /**< error secure level bad Certificate file */ -#define SLNETERR_ESEC_BAD_PRIVATE_FILE (-458L) /**< error secure level bad private file */ -#define SLNETERR_ESEC_BAD_DH_FILE (-459L) /**< error secure level bad DH file */ -#define SLNETERR_ESEC_T00_MANY_SSL_OPENED (-460L) /**< MAX SSL Sockets are opened */ -#define SLNETERR_ESEC_DATE_ERROR (-461L) /**< connected with certificate date verification error */ -#define SLNETERR_ESEC_HAND_SHAKE_TIMED_OUT (-462L) /**< connection timed out due to handshake time */ -#define SLNETERR_ESEC_TX_BUFFER_NOT_EMPTY (-463L) /**< cannot start ssl connection while send buffer is full */ -#define SLNETERR_ESEC_RX_BUFFER_NOT_EMPTY (-464L) /**< cannot start ssl connection while recv buffer is full */ -#define SLNETERR_ESEC_SSL_DURING_HAND_SHAKE (-465L) /**< cannot use while in handshaking */ -#define SLNETERR_ESEC_NOT_ALLOWED_WHEN_LISTENING (-466L) /**< the operation is not allowed when listening, do before listen */ -#define SLNETERR_ESEC_CERTIFICATE_REVOKED (-467L) /**< connected but on of the certificates in the chain is revoked */ -#define SLNETERR_ESEC_UNKNOWN_ROOT_CA (-468L) /**< connected but the root CA used to validate the peer is unknown */ -#define SLNETERR_ESEC_WRONG_PEER_CERT (-469L) /**< wrong peer cert (server cert) was received while trying to connect to server */ -#define SLNETERR_ESEC_TCP_DISCONNECTED_UNCOMPLETE_RECORD (-470L) /**< the other side disconnected the TCP layer and didn't send the whole ssl record */ -#define SLNETERR_ESEC_HELLO_VERIFY_ERROR (-471L) /**< Hello verification failed in DTLS */ - -#define SLNETERR_ESEC_BUFFER_E (-632L) /**< output buffer too small or input too large */ -#define SLNETERR_ESEC_ALGO_ID_E (-633L) /**< setting algo id error */ -#define SLNETERR_ESEC_PUBLIC_KEY_E (-634L) /**< setting public key error */ -#define SLNETERR_ESEC_DATE_E (-635L) /**< setting date validity error */ -#define SLNETERR_ESEC_SUBJECT_E (-636L) /**< setting subject name error */ -#define SLNETERR_ESEC_ISSUER_E (-637L) /**< setting issuer name error */ -#define SLNETERR_ESEC_CA_TRUE_E (-638L) /**< setting CA basic constraint true error */ -#define SLNETERR_ESEC_EXTENSIONS_E (-639L) /**< setting extensions error */ -#define SLNETERR_ESEC_ASN_PARSE_E (-640L) /**< ASN parsing error, invalid input */ -#define SLNETERR_ESEC_ASN_VERSION_E (-641L) /**< ASN version error, invalid number */ -#define SLNETERR_ESEC_ASN_GETINT_E (-642L) /**< ASN get big int error, invalid data */ -#define SLNETERR_ESEC_ASN_RSA_KEY_E (-643L) /**< ASN key init error, invalid input */ -#define SLNETERR_ESEC_ASN_OBJECT_ID_E (-644L) /**< ASN object id error, invalid id */ -#define SLNETERR_ESEC_ASN_TAG_NULL_E (-645L) /**< ASN tag error, not null */ -#define SLNETERR_ESEC_ASN_EXPECT_0_E (-646L) /**< ASN expect error, not zero */ -#define SLNETERR_ESEC_ASN_BITSTR_E (-647L) /**< ASN bit string error, wrong id */ -#define SLNETERR_ESEC_ASN_UNKNOWN_OID_E (-648L) /**< ASN oid error, unknown sum id */ -#define SLNETERR_ESEC_ASN_DATE_SZ_E (-649L) /**< ASN date error, bad size */ -#define SLNETERR_ESEC_ASN_BEFORE_DATE_E (-650L) /**< ASN date error, current date before */ -#define SLNETERR_ESEC_ASN_AFTER_DATE_E (-651L) /**< ASN date error, current date after */ -#define SLNETERR_ESEC_ASN_SIG_OID_E (-652L) /**< ASN signature error, mismatched oid */ -#define SLNETERR_ESEC_ASN_TIME_E (-653L) /**< ASN time error, unknown time type */ -#define SLNETERR_ESEC_ASN_INPUT_E (-654L) /**< ASN input error, not enough data */ -#define SLNETERR_ESEC_ASN_SIG_CONFIRM_E (-655L) /**< ASN sig error, confirm failure */ -#define SLNETERR_ESEC_ASN_SIG_HASH_E (-656L) /**< ASN sig error, unsupported hash type */ -#define SLNETERR_ESEC_ASN_SIG_KEY_E (-657L) /**< ASN sig error, unsupported key type */ -#define SLNETERR_ESEC_ASN_DH_KEY_E (-658L) /**< ASN key init error, invalid input */ -#define SLNETERR_ESEC_ASN_NTRU_KEY_E (-659L) /**< ASN ntru key decode error, invalid input */ -#define SLNETERR_ESEC_ASN_CRIT_EXT_E (-660L) /**< ASN unsupported critical extension */ -#define SLNETERR_ESEC_ECC_BAD_ARG_E (-670L) /**< ECC input argument of wrong type */ -#define SLNETERR_ESEC_ASN_ECC_KEY_E (-671L) /**< ASN ECC bad input */ -#define SLNETERR_ESEC_ECC_CURVE_OID_E (-672L) /**< Unsupported ECC OID curve type */ -#define SLNETERR_ESEC_BAD_FUNC_ARG (-673L) /**< Bad function argument provided */ -#define SLNETERR_ESEC_NOT_COMPILED_IN (-674L) /**< Feature not compiled in */ -#define SLNETERR_ESEC_UNICODE_SIZE_E (-675L) /**< Unicode password too big */ -#define SLNETERR_ESEC_NO_PASSWORD (-676L) /**< no password provided by user */ -#define SLNETERR_ESEC_ALT_NAME_E (-677L) /**< alt name size problem, too big */ -#define SLNETERR_ESEC_ASN_NO_SIGNER_E (-688L) /**< ASN no signer to confirm failure */ -#define SLNETERR_ESEC_ASN_CRL_CONFIRM_E (-689L) /**< ASN CRL signature confirm failure */ -#define SLNETERR_ESEC_ASN_CRL_NO_SIGNER_E (-690L) /**< ASN CRL no signer to confirm failure */ -#define SLNETERR_ESEC_ASN_OCSP_CONFIRM_E (-691L) /**< ASN OCSP signature confirm failure */ -#define SLNETERR_ESEC_VERIFY_FINISHED_ERROR (-704L) /**< verify problem on finished */ -#define SLNETERR_ESEC_VERIFY_MAC_ERROR (-705L) /**< verify mac problem */ -#define SLNETERR_ESEC_PARSE_ERROR (-706L) /**< parse error on header */ -#define SLNETERR_ESEC_UNKNOWN_HANDSHAKE_TYPE (-707L) /**< weird handshake type */ -#define SLNETERR_ESEC_SOCKET_ERROR_E (-708L) /**< error state on socket */ -#define SLNETERR_ESEC_SOCKET_NODATA (-709L) /**< expected data, not there */ -#define SLNETERR_ESEC_INCOMPLETE_DATA (-710L) /**< don't have enough data to complete task */ -#define SLNETERR_ESEC_UNKNOWN_RECORD_TYPE (-711L) /**< unknown type in record hdr */ -#define SLNETERR_ESEC_INNER_DECRYPT_ERROR (-712L) /**< error during decryption */ -#define SLNETERR_ESEC_FATAL_ERROR (-713L) /**< recvd alert fatal error */ -#define SLNETERR_ESEC_ENCRYPT_ERROR (-714L) /**< error during encryption */ -#define SLNETERR_ESEC_FREAD_ERROR (-715L) /**< fread problem */ -#define SLNETERR_ESEC_NO_PEER_KEY (-716L) /**< need peer's key */ -#define SLNETERR_ESEC_NO_PRIVATE_KEY (-717L) /**< need the private key */ -#define SLNETERR_ESEC_RSA_PRIVATE_ERROR (-718L) /**< error during rsa priv op */ -#define SLNETERR_ESEC_NO_DH_PARAMS (-719L) /**< server missing DH params */ -#define SLNETERR_ESEC_BUILD_MSG_ERROR (-720L) /**< build message failure */ -#define SLNETERR_ESEC_BAD_HELLO (-721L) /**< client hello malformed */ -#define SLNETERR_ESEC_DOMAIN_NAME_MISMATCH (-722L) /**< peer subject name mismatch */ -#define SLNETERR_ESEC_WANT_READ (-723L) /**< want read, call again */ -#define SLNETERR_ESEC_NOT_READY_ERROR (-724L) /**< handshake layer not ready */ -#define SLNETERR_ESEC_PMS_VERSION_ERROR (-725L) /**< pre m secret version error */ -#define SLNETERR_ESEC_WANT_WRITE (-727L) /**< want write, call again */ -#define SLNETERR_ESEC_BUFFER_ERROR (-728L) /**< malformed buffer input */ -#define SLNETERR_ESEC_VERIFY_CERT_ERROR (-729L) /**< verify cert error */ -#define SLNETERR_ESEC_VERIFY_SIGN_ERROR (-730L) /**< verify sign error */ -#define SLNETERR_ESEC_LENGTH_ERROR (-741L) /**< record layer length error */ -#define SLNETERR_ESEC_PEER_KEY_ERROR (-742L) /**< can't decode peer key */ -#define SLNETERR_ESEC_ZERO_RETURN (-743L) /**< peer sent close notify */ -#define SLNETERR_ESEC_SIDE_ERROR (-744L) /**< wrong client/server type */ -#define SLNETERR_ESEC_NO_PEER_CERT (-745L) /**< peer didn't send key */ -#define SLNETERR_ESEC_ECC_CURVETYPE_ERROR (-750L) /**< Bad ECC Curve Type */ -#define SLNETERR_ESEC_ECC_CURVE_ERROR (-751L) /**< Bad ECC Curve */ -#define SLNETERR_ESEC_ECC_PEERKEY_ERROR (-752L) /**< Bad Peer ECC Key */ -#define SLNETERR_ESEC_ECC_MAKEKEY_ERROR (-753L) /**< Bad Make ECC Key */ -#define SLNETERR_ESEC_ECC_EXPORT_ERROR (-754L) /**< Bad ECC Export Key */ -#define SLNETERR_ESEC_ECC_SHARED_ERROR (-755L) /**< Bad ECC Shared Secret */ -#define SLNETERR_ESEC_NOT_CA_ERROR (-757L) /**< Not a CA cert error */ -#define SLNETERR_ESEC_BAD_PATH_ERROR (-758L) /**< Bad path for opendir */ -#define SLNETERR_ESEC_BAD_CERT_MANAGER_ERROR (-759L) /**< Bad Cert Manager */ -#define SLNETERR_ESEC_OCSP_CERT_REVOKED (-760L) /**< OCSP Certificate revoked */ -#define SLNETERR_ESEC_CRL_CERT_REVOKED (-761L) /**< CRL Certificate revoked */ -#define SLNETERR_ESEC_CRL_MISSING (-762L) /**< CRL Not loaded */ -#define SLNETERR_ESEC_MONITOR_RUNNING_E (-763L) /**< CRL Monitor already running */ -#define SLNETERR_ESEC_THREAD_CREATE_E (-764L) /**< Thread Create Error */ -#define SLNETERR_ESEC_OCSP_NEED_URL (-765L) /**< OCSP need an URL for lookup */ -#define SLNETERR_ESEC_OCSP_CERT_UNKNOWN (-766L) /**< OCSP responder doesn't know */ -#define SLNETERR_ESEC_OCSP_LOOKUP_FAIL (-767L) /**< OCSP lookup not successful */ -#define SLNETERR_ESEC_MAX_CHAIN_ERROR (-768L) /**< max chain depth exceeded */ -#define SLNETERR_ESEC_NO_PEER_VERIFY (-778L) /**< Need peer cert verify Error */ -#define SLNETERR_ESEC_UNSUPPORTED_SUITE (-790L) /**< unsupported cipher suite */ -#define SLNETERR_ESEC_MATCH_SUITE_ERROR (-791L) /**< can't match cipher suite */ - - - -/* WLAN ERRORS CODES*/ - -#define SLNETERR_WLAN_KEY_ERROR (-2049L) -#define SLNETERR_WLAN_INVALID_ROLE (-2050L) -#define SLNETERR_WLAN_PREFERRED_NETWORKS_FILE_LOAD_FAILED (-2051L) -#define SLNETERR_WLAN_CANNOT_CONFIG_SCAN_DURING_PROVISIONING (-2052L) -#define SLNETERR_WLAN_INVALID_SECURITY_TYPE (-2054L) -#define SLNETERR_WLAN_PASSPHRASE_TOO_LONG (-2055L) -#define SLNETERR_WLAN_EAP_WRONG_METHOD (-2057L) -#define SLNETERR_WLAN_PASSWORD_ERROR (-2058L) -#define SLNETERR_WLAN_EAP_ANONYMOUS_LEN_ERROR (-2059L) -#define SLNETERR_WLAN_SSID_LEN_ERROR (-2060L) -#define SLNETERR_WLAN_USER_ID_LEN_ERROR (-2061L) -#define SLNETERR_WLAN_PREFERRED_NETWORK_LIST_FULL (-2062L) -#define SLNETERR_WLAN_PREFERRED_NETWORKS_FILE_WRITE_FAILED (-2063L) -#define SLNETERR_WLAN_ILLEGAL_WEP_KEY_INDEX (-2064L) -#define SLNETERR_WLAN_INVALID_DWELL_TIME_VALUES (-2065L) -#define SLNETERR_WLAN_INVALID_POLICY_TYPE (-2066L) -#define SLNETERR_WLAN_PM_POLICY_INVALID_OPTION (-2067L) -#define SLNETERR_WLAN_PM_POLICY_INVALID_PARAMS (-2068L) -#define SLNETERR_WLAN_WIFI_NOT_CONNECTED (-2069L) -#define SLNETERR_WLAN_ILLEGAL_CHANNEL (-2070L) -#define SLNETERR_WLAN_WIFI_ALREADY_DISCONNECTED (-2071L) -#define SLNETERR_WLAN_TRANSCEIVER_ENABLED (-2072L) -#define SLNETERR_WLAN_GET_NETWORK_LIST_EAGAIN (-2073L) -#define SLNETERR_WLAN_GET_PROFILE_INVALID_INDEX (-2074L) -#define SLNETERR_WLAN_FAST_CONN_DATA_INVALID (-2075L) -#define SLNETERR_WLAN_NO_FREE_PROFILE (-2076L) -#define SLNETERR_WLAN_AP_SCAN_INTERVAL_TOO_LOW (-2077L) -#define SLNETERR_WLAN_SCAN_POLICY_INVALID_PARAMS (-2078L) - -#define SLNETERR_RXFL_OK (0L) /**< O.K */ -#define SLNETERR_RXFL_RANGE_COMPARE_PARAMS_ARE_INVALID (-2079L) -#define SLNETERR_RXFL_RXFL_INVALID_PATTERN_LENGTH (-2080L) /**< requested length for L1/L4 payload matching must not exceed 16 bytes */ -#define SLNETERR_RXFL_ACTION_USER_EVENT_ID_TOO_BIG (-2081L) /**< user action id for host event must not exceed SLNETERR_WLAN_RX_FILTER_MAX_USER_EVENT_ID */ -#define SLNETERR_RXFL_OFFSET_TOO_BIG (-2082L) /**< requested offset for L1/L4 payload matching must not exceed 1535 bytes */ -#define SLNETERR_RXFL_STAT_UNSUPPORTED (-2083L) /**< get rx filters statistics not supported */ -#define SLNETERR_RXFL_INVALID_FILTER_ARG_UPDATE (-2084L) /**< invalid filter args request */ -#define SLNETERR_RXFL_INVALID_SYSTEM_STATE_TRIGGER_FOR_FILTER_TYPE (-2085L) /**< system state not supported for this filter type */ -#define SLNETERR_RXFL_INVALID_FUNC_ID_FOR_FILTER_TYPE (-2086L) /**< function id not supported for this filter type */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_3 (-2087L) /**< filter parent doesn't exist */ -#define SLNETERR_RXFL_OUTPUT_OR_INPUT_BUFFER_LENGTH_TOO_SMALL (-2088L) /**< ! The output buffer length is smaller than required for that operation */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_SOFTWARE_FILTER_NOT_FIT (-2089L) /**< Node filter can't be child of software filter and vice_versa */ -#define SLNETERR_RXFL_DEPENDENCY_IS_NOT_PERSISTENT (-2090L) /**< Dependency filter is not persistent */ -#define SLNETERR_RXFL_RXFL_ALLOCATION_PROBLEM (-2091L) -#define SLNETERR_RXFL_SYSTEM_STATE_NOT_SUPPORTED_FOR_THIS_FILTER (-2092L) /**< System state is not supported */ -#define SLNETERR_RXFL_TRIGGER_USE_REG5_TO_REG8 (-2093L) /**< Only counters 5 - 8 are allowed, for trigger */ -#define SLNETERR_RXFL_TRIGGER_USE_REG1_TO_REG4 (-2094L) /**< Only counters 1 - 4 are allowed, for trigger */ -#define SLNETERR_RXFL_ACTION_USE_REG5_TO_REG8 (-2095L) /**< Only counters 5 - 8 are allowed, for action */ -#define SLNETERR_RXFL_ACTION_USE_REG1_TO_REG4 (-2096L) /**< Only counters 1 - 4 are allowed, for action */ -#define SLNETERR_RXFL_FIELD_SUPPORT_ONLY_EQUAL_AND_NOTEQUAL (-2097L) /**< Rule compare function Id is out of range */ -#define SLNETERR_RXFL_WRONG_MULTICAST_BROADCAST_ADDRESS (-2098L) /**< The address should be of type multicast or broadcast */ -#define SLNETERR_RXFL_THE_FILTER_IS_NOT_OF_HEADER_TYPE (-2099L) /**< The filter should be of header type */ -#define SLNETERR_RXFL_WRONG_COMPARE_FUNC_FOR_BROADCAST_ADDRESS (-2100L) /**< The compare function is not suitable for broadcast address */ -#define SLNETERR_RXFL_WRONG_MULTICAST_ADDRESS (-2101L) /**< The address should be of multicast type */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_IS_NOT_PERSISTENT (-2102L) /**< The dependency filter is not persistent */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_IS_NOT_ENABLED (-2103L) /**< The dependency filter is not enabled */ -#define SLNETERR_RXFL_FILTER_HAS_CHILDS (-2104L) /**< The filter has childs and can't be removed */ -#define SLNETERR_RXFL_CHILD_IS_ENABLED (-2105L) /**< Can't disable filter while the child is enabled */ -#define SLNETERR_RXFL_DEPENDENCY_IS_DISABLED (-2106L) /**< Can't enable filter in case its dependency filter is disabled */ -#define SLNETERR_RXFL_MAC_SEND_MATCHDB_FAILED (-2107L) -#define SLNETERR_RXFL_MAC_SEND_ARG_DB_FAILED (-2108L) -#define SLNETERR_RXFL_MAC_SEND_NODEDB_FAILED (-2109L) -#define SLNETERR_RXFL_MAC_OPERTATION_RESUME_FAILED (-2110L) -#define SLNETERR_RXFL_MAC_OPERTATION_HALT_FAILED (-2111L) -#define SLNETERR_RXFL_NUMBER_OF_CONNECTION_POINTS_EXCEEDED (-2112L) /**< Number of connection points exceeded */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_DEPENDENCY_ACTION_IS_DROP (-2113L) /**< The dependent filter has Drop action, thus the filter can't be created */ -#define SLNETERR_RXFL_FILTER_DO_NOT_EXISTS (-2114L) /**< The filter doesn't exists */ -#define SLNETERR_RXFL_DEPEDENCY_NOT_ON_THE_SAME_LAYER (-2115L) /**< The filter and its dependency must be on the same layer */ -#define SLNETERR_RXFL_NUMBER_OF_ARGS_EXCEEDED (-2116L) /**< Number of arguments exceeded */ -#define SLNETERR_RXFL_ACTION_NO_REG_NUMBER (-2117L) /**< Action require counter number */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_LAYER_DO_NOT_FIT (-2118L) /**< the filter and its dependency should be from the same layer */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_SYSTEM_STATE_DO_NOT_FIT (-2119L) /**< The filter and its dependency system state don't fit */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_2 (-2120L) /**< The parent filter don't exist */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_1 (-2121L) /**< The parent filter is null */ -#define SLNETERR_RXFL_RULE_HEADER_ACTION_TYPE_NOT_SUPPORTED (-2122L) /**< The action type is not supported */ -#define SLNETERR_RXFL_RULE_HEADER_TRIGGER_COMPARE_FUNC_OUT_OF_RANGE (-2123L) /**< The Trigger comparison function is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_TRIGGER_OUT_OF_RANGE (-2124L) /**< The Trigger is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_COMPARE_FUNC_OUT_OF_RANGE (-2125L) /**< The rule compare function is out of range */ -#define SLNETERR_RXFL_FRAME_TYPE_NOT_SUPPORTED (-2126L) /**< ASCII frame type string is illegal */ -#define SLNETERR_RXFL_RULE_FIELD_ID_NOT_SUPPORTED (-2127L) /**< Rule field ID is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_FIELD_ID_ASCII_NOT_SUPPORTED (-2128L) /**< This ASCII field ID is not supported */ -#define SLNETERR_RXFL_RULE_HEADER_NOT_SUPPORTED (-2129L) /**< The header rule is not supported on current release */ -#define SLNETERR_RXFL_RULE_HEADER_OUT_OF_RANGE (-2130L) /**< The header rule is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_COMBINATION_OPERATOR_OUT_OF_RANGE (-2131L) /**< Combination function Id is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_FIELD_ID_OUT_OF_RANGE (-2132L) /**< rule field Id is out of range */ -#define SLNETERR_RXFL_UPDATE_NOT_SUPPORTED (-2133L) /**< Update not supported */ -#define SLNETERR_RXFL_NO_FILTER_DATABASE_ALLOCATE (-2134L) -#define SLNETERR_RXFL_ALLOCATION_FOR_GLOBALS_STRUCTURE_FAILED (-2135L) -#define SLNETERR_RXFL_ALLOCATION_FOR_DB_NODE_FAILED (-2136L) -#define SLNETERR_RXFL_READ_FILE_FILTER_ID_ILLEGAL (-2137L) -#define SLNETERR_RXFL_READ_FILE_NUMBER_OF_FILTER_FAILED (-2138L) -#define SLNETERR_RXFL_READ_FILE_FAILED (-2139L) -#define SLNETERR_RXFL_NO_FILTERS_ARE_DEFINED (-2140L) /**< No filters are defined in the system */ -#define SLNETERR_RXFL_NUMBER_OF_FILTER_EXCEEDED (-2141L) /**< Number of max filters exceeded */ -#define SLNETERR_RXFL_BAD_FILE_MODE (-2142L) -#define SLNETERR_RXFL_FAILED_READ_NVFILE (-2143L) -#define SLNETERR_RXFL_FAILED_INIT_STORAGE (-2144L) -#define SLNETERR_RXFL_CONTINUE_WRITE_MUST_BE_MOD_4 (-2145L) -#define SLNETERR_RXFL_FAILED_LOAD_FILE (-2146L) -#define SLNETERR_RXFL_INVALID_HANDLE (-2147L) -#define SLNETERR_RXFL_FAILED_TO_WRITE (-2148L) -#define SLNETERR_RXFL_OFFSET_OUT_OF_RANGE (-2149L) -#define SLNETERR_RXFL_ALLOC (-2150L) -#define SLNETERR_RXFL_READ_DATA_LENGTH (-2151L) -#define SLNETERR_RXFL_INVALID_FILE_ID (-2152L) -#define SLNETERR_RXFL_FILE_FILTERS_NOT_EXISTS (-2153L) -#define SLNETERR_RXFL_FILE_ALREADY_IN_USE (-2154L) -#define SLNETERR_RXFL_INVALID_ARGS (-2155L) -#define SLNETERR_RXFL_FAILED_TO_CREATE_FILE (-2156L) -#define SLNETERR_RXFL_FS_ALREADY_LOADED (-2157L) -#define SLNETERR_RXFL_UNKNOWN (-2158L) -#define SLNETERR_RXFL_FAILED_TO_CREATE_LOCK_OBJ (-2159L) -#define SLNETERR_RXFL_DEVICE_NOT_LOADED (-2160L) -#define SLNETERR_RXFL_INVALID_MAGIC_NUM (-2161L) -#define SLNETERR_RXFL_FAILED_TO_READ (-2162L) -#define SLNETERR_RXFL_NOT_SUPPORTED (-2163L) -#define SLNETERR_WLAN_INVALID_COUNTRY_CODE (-2164L) -#define SLNETERR_WLAN_NVMEM_ACCESS_FAILED (-2165L) -#define SLNETERR_WLAN_OLD_FILE_VERSION (-2166L) -#define SLNETERR_WLAN_TX_POWER_OUT_OF_RANGE (-2167L) -#define SLNETERR_WLAN_INVALID_AP_PASSWORD_LENGTH (-2168L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_PROVISIONING_ALREADY_STARTED (-2169L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_HTTP_SERVER_DISABLED (-2170L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_PROFILE_LIST_FULL (-2171L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_INVALID_PARAM (-2172L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_GENERAL_ERROR (-2173L) -#define SLNETERR_WLAN_MULTICAST_EXCEED_MAX_ADDR (-2174L) -#define SLNETERR_WLAN_MULTICAST_INVAL_ADDR (-2175L) -#define SLNETERR_WLAN_AP_SCAN_INTERVAL_TOO_SHORT (-2176L) -#define SLNETERR_WLAN_PROVISIONING_CMD_NOT_EXPECTED (-2177L) - - -#define SLNETERR_WLAN_AP_ACCESS_LIST_NO_ADDRESS_TO_DELETE (-2178L) /**< List is empty, no address to delete */ -#define SLNETERR_WLAN_AP_ACCESS_LIST_FULL (-2179L) /**< access list is full */ -#define SLNETERR_WLAN_AP_ACCESS_LIST_DISABLED (-2180L) /**< access list is disabled */ -#define SLNETERR_WLAN_AP_ACCESS_LIST_MODE_NOT_SUPPORTED (-2181L) /**< Trying to switch to unsupported mode */ -#define SLNETERR_WLAN_AP_STA_NOT_FOUND (-2182L) /**< trying to disconnect station which is not connected */ - - - -/* DEVICE ERRORS CODES*/ -#define SLNETERR_SUPPLICANT_ERROR (-4097L) -#define SLNETERR_HOSTAPD_INIT_FAIL (-4098L) -#define SLNETERR_HOSTAPD_INIT_IF_FAIL (-4099L) -#define SLNETERR_WLAN_DRV_INIT_FAIL (-4100L) -#define SLNETERR_MDNS_ENABLE_FAIL (-4103L) /**< mDNS enable failed */ -#define SLNETERR_ROLE_STA_ERR (-4107L) /**< Failure to load MAC/PHY in STA role */ -#define SLNETERR_ROLE_AP_ERR (-4108L) /**< Failure to load MAC/PHY in AP role */ -#define SLNETERR_ROLE_P2P_ERR (-4109L) /**< Failure to load MAC/PHY in P2P role */ -#define SLNETERR_CALIB_FAIL (-4110L) /**< Failure of calibration */ -#define SLNETERR_RESTORE_IMAGE_COMPLETE (-4113L) /**< Return to factory image completed, perform reset */ -#define SLNETERR_UNKNOWN_ERR (-4114L) -#define SLNETERR_GENERAL_ERR (-4115L) /**< General error during init */ -#define SLNETERR_WRONG_ROLE (-4116L) -#define SLNETERR_INCOMPLETE_PROGRAMMING (-4117L) /**< Error during programming, Program new image should be invoked (see sl_FsProgram) */ - - -#define SLNETERR_PENDING_TXRX_STOP_TIMEOUT_EXP (-4118L) /**< Timeout expired before completing all TX/RX */ -#define SLNETERR_PENDING_TXRX_NO_TIMEOUT (-4119L) /**< No Timeout, still have pending TX/RX */ -#define SLNETERR_INVALID_PERSISTENT_CONFIGURATION (-4120L) /**< persistency configuration can only be set to 0 (disabled) or 1 (enabled) */ - - - -/* NETAPP ERRORS CODES*/ -#define SLNETERR_MDNS_CREATE_FAIL (-6145L) /**< mDNS create failed */ -#define SLNETERR_DEVICE_NAME_LEN_ERR (-6146L) /**< Set Dev name error codes */ -#define SLNETERR_DEVICE_NAME_INVALID (-6147L) /**< Set Dev name error codes */ -#define SLNETERR_DOMAIN_NAME_LEN_ERR (-6148L) /**< Set domain name error codes */ -#define SLNETERR_DOMAIN_NAME_INVALID (-6149L) /**< Set domain name error codes */ -#define SLNETERR_NET_APP_DNS_QUERY_NO_RESPONSE (-6150L) /**< DNS query failed, no response */ -#define SLNETERR_NET_APP_DNS_ERROR (-6151L) /**< DNS internal error */ -#define SLNETERR_NET_APP_DNS_NO_SERVER (-6152L) /**< No DNS server was specified */ -#define SLNETERR_NET_APP_DNS_TIMEOUTR (-6153L) /**< mDNS parameters error */ -#define SLNETERR_NET_APP_DNS_QUERY_FAILED (-6154L) /**< DNS query failed; no DNS server sent an 'answer' */ -#define SLNETERR_NET_APP_DNS_BAD_ADDRESS_ERROR (-6155L) /**< Improperly formatted IPv4 or IPv6 address */ -#define SLNETERR_NET_APP_DNS_SIZE_ERROR (-6156L) /**< DNS destination size is too small */ -#define SLNETERR_NET_APP_DNS_MALFORMED_PACKET (-6157L) /**< Improperly formed or corrupted DNS packet received */ -#define SLNETERR_NET_APP_DNS_BAD_ID_ERROR (-6158L) /**< DNS packet from server does not match query ID */ -#define SLNETERR_NET_APP_DNS_PARAM_ERROR (-6159L) /**< Invalid params */ -#define SLNETERR_NET_APP_DNS_SERVER_NOT_FOUND (-6160L) /**< Server not found in Client list of DNS servers */ -#define SLNETERR_NET_APP_DNS_PACKET_CREATE_ERROR (-6161L) /**< Error creating DNS packet */ -#define SLNETERR_NET_APP_DNS_EMPTY_DNS_SERVER_LIST (-6162L) /**< DNS Client's list of DNS servers is empty */ -#define SLNETERR_NET_APP_DNS_SERVER_AUTH_ERROR (-6163L) /**< Server not able to authenticate answer/authority data*/ -#define SLNETERR_NET_APP_DNS_ZERO_GATEWAY_IP_ADDRESS (-6164L) /**< DNS Client IP instance has a zero gateway IP address */ -#define SLNETERR_NET_APP_DNS_MISMATCHED_RESPONSE (-6165L) /**< Server response type does not match the query request*/ -#define SLNETERR_NET_APP_DNS_DUPLICATE_ENTRY (-6166L) /**< Duplicate entry exists in DNS server table */ -#define SLNETERR_NET_APP_DNS_RETRY_A_QUERY (-6167L) /**< SOA status returned; web site only exists as IPv4 */ -#define SLNETERR_NET_APP_DNS_INVALID_ADDRESS_TYPE (-6168L) /**< IP address type (e.g. IPv6L) not supported */ -#define SLNETERR_NET_APP_DNS_IPV6_NOT_SUPPORTED (-6169L) /**< IPv6 disabled */ -#define SLNETERR_NET_APP_DNS_NEED_MORE_RECORD_BUFFER (-6170L) /**< The buffer size is not enough. */ -#define SLNETERR_NET_APP_MDNS_ERROR (-6171L) /**< MDNS internal error. */ -#define SLNETERR_NET_APP_MDNS_PARAM_ERROR (-6172L) /**< MDNS parameters error. */ -#define SLNETERR_NET_APP_MDNS_CACHE_ERROR (-6173L) /**< The Cache size is not enough. */ -#define SLNETERR_NET_APP_MDNS_UNSUPPORTED_TYPE (-6174L) /**< The unsupported resource record type. */ -#define SLNETERR_NET_APP_MDNS_DATA_SIZE_ERROR (-6175L) /**< The data size is too big. */ -#define SLNETERR_NET_APP_MDNS_AUTH_ERROR (-6176L) /**< Attempting to parse too large a data. */ -#define SLNETERR_NET_APP_MDNS_PACKET_ERROR (-6177L) /**< The packet can not add the resource record. */ -#define SLNETERR_NET_APP_MDNS_DEST_ADDRESS_ERROR (-6178L) /**< The destination address error. */ -#define SLNETERR_NET_APP_MDNS_UDP_PORT_ERROR (-6179L) /**< The udp port error. */ -#define SLNETERR_NET_APP_MDNS_NOT_LOCAL_LINK (-6180L) /**< The message that not originate from the local link. */ -#define SLNETERR_NET_APP_MDNS_EXCEED_MAX_LABEL (-6181L) /**< The data exceed the max laber size. */ -#define SLNETERR_NET_APP_MDNS_EXIST_UNIQUE_RR (-6182L) /**< At least one Unqiue record in the cache. */ -#define SLNETERR_NET_APP_MDNS_EXIST_ANSWER (-6183L) /**< At least one answer record in the cache. */ -#define SLNETERR_NET_APP_MDNS_EXIST_SAME_QUERY (-6184L) /**< Exist the same query. */ -#define SLNETERR_NET_APP_MDNS_DUPLICATE_SERVICE (-6185L) /**< Duplicate service. */ -#define SLNETERR_NET_APP_MDNS_NO_ANSWER (-6186L) /**< No response for one-shot query. */ -#define SLNETERR_NET_APP_MDNS_NO_KNOWN_ANSWER (-6187L) /**< No known answer for query. */ -#define SLNETERR_NET_APP_MDNS_NAME_MISMATCH (-6188L) /**< The name mismatch. */ -#define SLNETERR_NET_APP_MDNS_NOT_STARTED (-6189L) /**< MDNS does not start. */ -#define SLNETERR_NET_APP_MDNS_HOST_NAME_ERROR (-6190L) /**< MDNS host name error. */ -#define SLNETERR_NET_APP_MDNS_NO_MORE_ENTRIES (-6191L) /**< No more entries be found. */ -#define SLNETERR_NET_APP_MDNS_SERVICE_TYPE_MISMATCH (-6192L) /**< The service type mismatch */ -#define SLNETERR_NET_APP_MDNS_LOOKUP_INDEX_ERROR (-6193L) /**< Index is bigger than number of services. */ -#define SLNETERR_NET_APP_MDNS_MAX_SERVICES_ERROR (-6194L) -#define SLNETERR_NET_APP_MDNS_IDENTICAL_SERVICES_ERROR (-6195L) -#define SLNETERR_NET_APP_MDNS_EXISTED_SERVICE_ERROR (-6196L) -#define SLNETERR_NET_APP_MDNS_ERROR_SERVICE_NAME_ERROR (-6197L) -#define SLNETERR_NET_APP_MDNS_RX_PACKET_ALLOCATION_ERROR (-6198L) -#define SLNETERR_NET_APP_MDNS_BUFFER_SIZE_ERROR (-6199L) -#define SLNETERR_NET_APP_MDNS_NET_APP_SET_ERROR (-6200L) -#define SLNETERR_NET_APP_MDNS_GET_SERVICE_LIST_FLAG_ERROR (-6201L) -#define SLNETERR_NET_APP_MDNS_MDNS_NO_CONFIGURATION_ERROR (-6202L) -#define SLNETERR_NET_APP_MDNS_STATUS_ERROR (-6203L) -#define SLNETERR_NET_APP_ENOBUFS (-6204L) -#define SLNETERR_NET_APP_DNS_IPV6_REQ_BUT_IPV6_DISABLED (-6205L) /**< trying to issue ipv6 DNS request but ipv6 is disabled */ -#define SLNETERR_NET_APP_DNS_INVALID_FAMILY_TYPE (-6206L) /**< Family type is not ipv4 and not ipv6 */ -#define SLNETERR_NET_APP_DNS_REQ_TOO_BIG (-6207L) /**< DNS request size is too big */ -#define SLNETERR_NET_APP_DNS_ALLOC_ERROR (-6208L) /**< Allocation error */ -#define SLNETERR_NET_APP_DNS_EXECUTION_ERROR (-6209L) /**< Execution error */ -#define SLNETERR_NET_APP_P2P_ROLE_IS_NOT_CONFIGURED (-6210L) /**< role p2p is not configured yet, should be CL or GO in order to execute command */ -#define SLNETERR_NET_APP_INCORECT_ROLE_FOR_APP (-6211L) /**< incorrect role for specific application */ -#define SLNETERR_NET_APP_INCORECT_APP_MASK (-6212L) /**< mask does not match any app */ -#define SLNETERR_NET_APP_MDNS_ALREADY_STARTED (-6213L) /**< mdns application already started */ -#define SLNETERR_NET_APP_HTTP_SERVER_ALREADY_STARTED (-6214L) /**< http server application already started */ - -#define SLNETERR_NET_APP_HTTP_GENERAL_ERROR (-6216L) /**< New error - Http handle request failed */ -#define SLNETERR_NET_APP_HTTP_INVALID_TIMEOUT (-6217L) /**< New error - Http timeout invalid argument */ -#define SLNETERR_NET_APP_INVALID_URN_LENGTH (-6218L) /**< invalid URN length */ -#define SLNETERR_NET_APP_RX_BUFFER_LENGTH (-6219L) /**< size of the requested services is smaller than size of the user buffer */ - - - -/*< NETCFG ERRORS CODES*/ -#define SLNETERR_STATIC_ADDR_SUBNET_ERROR (-8193L) -#define SLNETERR_INCORRECT_IPV6_STATIC_LOCAL_ADDR (-8194L) /**< Ipv6 Local address perfix is wrong */ -#define SLNETERR_INCORRECT_IPV6_STATIC_GLOBAL_ADDR (-8195L) /**< Ipv6 Global address perfix is wrong */ -#define SLNETERR_IPV6_LOCAL_ADDR_SHOULD_BE_SET_FIRST (-8195L) /**< Attempt to set ipv6 global address before ipv6 local address is set */ - - - -/* NETUTIL ERRORS CODES */ -#define SLNETERR_NETUTIL_CRYPTO_GENERAL (-12289L) -#define SLNETERR_NETUTIL_CRYPTO_INVALID_INDEX (-12290L) -#define SLNETERR_NETUTIL_CRYPTO_INVALID_PARAM (-12291L) -#define SLNETERR_NETUTIL_CRYPTO_MEM_ALLOC (-12292L) -#define SLNETERR_NETUTIL_CRYPTO_INVALID_DB_VER (-12293L) -#define SLNETERR_NETUTIL_CRYPTO_UNSUPPORTED_OPTION (-12294L) -#define SLNETERR_NETUTIL_CRYPTO_BUFFER_TOO_SMALL (-12295L) -#define SLNETERR_NETUTIL_CRYPTO_EMPTY_DB_ENTRY (-12296L) -#define SLNETERR_NETUTIL_CRYPTO_NON_TEMPORARY_KEY (-12297L) -#define SLNETERR_NETUTIL_CRYPTO_DB_ENTRY_NOT_FREE (-12298L) -#define SLNETERR_NETUTIL_CRYPTO_CORRUPTED_DB_FILE (-12299L) - - - -/* GENERAL ERRORS CODES*/ -#define SLNETERR_INVALID_OPCODE (-14337L) -#define SLNETERR_INVALID_PARAM (-14338L) -#define SLNETERR_STATUS_ERROR (-14341L) -#define SLNETERR_NVMEM_ACCESS_FAILED (-14342L) -#define SLNETERR_NOT_ALLOWED_NWP_LOCKED (-14343L) /**< Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ - -/* SECURITY ERRORS CODE */ -#define SLNETERR_LOADING_CERTIFICATE_STORE (-28673L) - -/* Device is Locked! Return to Factory Image or Program new - image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SLNETERR_DEVICE_LOCKED_SECURITY_ALERT (-28674L) - - - -/* INTERNAL HOST ERRORS CODES*/ - -/* Receive this error in case there are no resources to issue the command - If possible, increase the number of MAX_CONCURRENT_ACTIONS (result in memory increase) - If not, try again later */ -#define SLNETERR_POOL_IS_EMPTY (-2000L) - -/* Receive this error in case a given length for RX buffer was too small. - Receive payload was bigger than the given buffer size. Therefore, payload is cut according to receive size - Recommend to increase buffer size */ -#define SLNETERR_ESMALLBUF (-2001L) - -/* Receive this error in case zero length is supplied to a "get" API - Recommend to supply length according to requested information (view options defines for help) */ -#define SLNETERR_EZEROLEN (-2002L) - -/* User supplied invalid parameter */ -#define SLNETERR_INVALPARAM (-2003L) - -/* Failed to open interface */ -#define SLNETERR_BAD_INTERFACE (-2004L) - -/* API has been aborted due to an error detected by host driver */ -#define SLNETERR_API_ABORTED (-2005L) - -/* Parameters are invalid */ -#define SLNETERR_RET_CODE_INVALID_INPUT (-2006L) - -/* Driver internal error */ -#define SLNETERR_RET_CODE_SELF_ERROR (-2007L) - -/* NWP internal error */ -#define SLNETERR_RET_CODE_NWP_IF_ERROR (-2008L) - -/* malloc error */ -#define SLNETERR_RET_CODE_MALLOC_ERROR (-2009L) - -/* protocol error */ -#define SLNETERR_RET_CODE_PROTOCOL_ERROR (-2010L) - -/* API has been aborted, command is not allowed in device lock state */ -#define SLNETERR_RET_CODE_DEV_LOCKED (-2011L) - -/* SlNetSock_Start cannot be invoked twice */ -#define SLNETERR_RET_CODE_DEV_ALREADY_STARTED (-2012L) - -/* SL Net API is in progress */ -#define SLNETERR_RET_CODE_API_COMMAND_IN_PROGRESS (-2013L) - -/* Provisioning is in progress - */ -#define SLNETERR_RET_CODE_PROVISIONING_IN_PROGRESS (-2014L) - -/* Wrong ping parameters - ping cannot be called with the following parameters: -1. infinite ping packet -2. report only when finished -3. no callback supplied */ -#define SLNETERR_RET_CODE_NET_APP_PING_INVALID_PARAMS (-2015L) - - -/* SlNetSock select already in progress. - this error will be returned if app will try to call - SlNetSock_select blocking when there is already select trigger in progress */ -#define SLNETERR_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR (-2016L) - -#define SLNETERR_RET_CODE_STOP_IN_PROGRESS (-2017L) - - -/* The device has not been started yet */ -#define SLNETERR_RET_CODE_DEV_NOT_STARTED (-2018L) - -/* The event link was not found in the list */ -#define SLNETERR_RET_CODE_EVENT_LINK_NOT_FOUND (-2019L) - -/* Function couldn't find any free space/location */ -#define SLNETERR_RET_CODE_NO_FREE_SPACE (-2020L) - -/* Function couldn't execute correctly */ -#define SLNETERR_RET_CODE_FUNCTION_FAILED (-2021L) - -/* Mutex creation failed */ -#define SLNETERR_RET_CODE_MUTEX_CREATION_FAILED (-2022L) - -/* Function couldn't find the requested resource */ -#define SLNETERR_RET_CODE_COULDNT_FIND_RESOURCE (-2023L) - -/* Interface doesn't support the non mandatory function */ -#define SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN (-2024L) - -/* Socket creation in progress */ -#define SLNETERR_RET_CODE_SOCKET_CREATION_IN_PROGRESS (-2025L) - -/* Unsupported scenario, option or feature */ -#define SLNETERR_RET_CODE_UNSUPPORTED (-2026L) - - -/* sock related API's from SlNetIf_Config_t failed */ -#define SLNETSOCK_ERR_SOCKCREATE_FAILED (-3000L) -#define SLNETSOCK_ERR_SOCKCLOSE_FAILED (-3001L) -#define SLNETSOCK_ERR_SOCKSELECT_FAILED (-3002L) -#define SLNETSOCK_ERR_SOCKSETOPT_FAILED (-3003L) -#define SLNETSOCK_ERR_SOCKGETOPT_FAILED (-3004L) -#define SLNETSOCK_ERR_SOCKRECVFROM_FAILED (-3005L) -#define SLNETSOCK_ERR_SOCKSENDTO_FAILED (-3006L) -#define SLNETSOCK_ERR_SOCKSHUTDOWN_FAILED (-3007L) -#define SLNETSOCK_ERR_SOCKACCEPT_FAILED (-3008L) -#define SLNETSOCK_ERR_SOCKBIND_FAILED (-3009L) -#define SLNETSOCK_ERR_SOCKLISTEN_FAILED (-3000L) -#define SLNETSOCK_ERR_SOCKCONNECT_FAILED (-3001L) -#define SLNETSOCK_ERR_SOCKGETPEERNAME_FAILED (-3002L) -#define SLNETSOCK_ERR_SOCKGETLOCALNAME_FAILED (-3003L) -#define SLNETSOCK_ERR_SOCKRECV_FAILED (-3004L) -#define SLNETSOCK_ERR_SOCKSEND_FAILED (-3005L) -#define SLNETSOCK_ERR_SOCKSTARTSEC_FAILED (-3006L) - -/* util related API's from SlNetIf_Config_t failed */ -#define SLNETUTIL_ERR_UTILGETHOSTBYNAME_FAILED (-3100L) - -/* if related API's from SlNetIf_Config_t failed */ -#define SLNETIF_ERR_IFLOADSECOBJ_FAILED (-3200L) -#define SLNETIF_ERR_IFGETIPADDR_FAILED (-3201L) -#define SLNETIF_ERR_IFGETCONNECTIONSTATUS_FAILED (-3202L) -#define SLNETIF_ERR_IFCREATECONTEXT_FAILED (-3203L) - -/*! - - Close the Doxygen group. - @} - -*/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SL_NET_ERR_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetif.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetif.h deleted file mode 100755 index dfb58221578..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetif.h +++ /dev/null @@ -1,642 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#ifndef __SL_NET_IF_H__ -#define __SL_NET_IF_H__ - -#include -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup SlNetIf SlNetIf group - - \short Controls standard stack/interface options and capabilities - -*/ -/*! - - \addtogroup SlNetIf - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* Interface ID bit pool to be used in interface add and in socket creation */ -#define SLNETIF_ID_1 (1 << 0) //can be used for wifi interface -#define SLNETIF_ID_2 (1 << 1) //can be used for eth interface -#define SLNETIF_ID_3 (1 << 2) -#define SLNETIF_ID_4 (1 << 3) -#define SLNETIF_ID_5 (1 << 4) -#define SLNETIF_ID_6 (1 << 5) -#define SLNETIF_ID_7 (1 << 6) -#define SLNETIF_ID_8 (1 << 7) -#define SLNETIF_ID_9 (1 << 8) -#define SLNETIF_ID_10 (1 << 9) -#define SLNETIF_ID_11 (1 << 10) -#define SLNETIF_ID_12 (1 << 11) -#define SLNETIF_ID_13 (1 << 12) -#define SLNETIF_ID_14 (1 << 13) -#define SLNETIF_ID_15 (1 << 14) -#define SLNETIF_ID_16 (1 << 15) - -/* Maximum interfaces */ -#define SLNETIF_MAX_IF (16) - -/* this macro returns 0 when only one bit is set and a number when it isn't */ -#define ONLY_ONE_BIT_IS_SET(x) (((x > 0) && ((x & (x - 1)) == 0))?true:false) - - -/* Interface connection status bit pool to be used in set interface connection status function */ - -#define SLNETIF_STATUS_DISCONNECTED (0) -#define SLNETIF_STATUS_CONNECTED (1) - -/*! - \brief Interface state bit pool to be used in set interface state function -*/ -typedef enum -{ - SLNETIF_STATE_DISABLE = 0, - SLNETIF_STATE_ENABLE = 1 -} SlNetIfState_e; - -/*! - \brief Address type enum to be used in get ip address function -*/ -typedef enum -{ - SLNETIF_IPV4_ADDR = 0, - SLNETIF_IPV6_ADDR_LOCAL = 1, - SLNETIF_IPV6_ADDR_GLOBAL = 2 -} SlNetIfAddressType_e; - -/* Address config return values that can be retrieved in get ip address function */ -#define SLNETIF_ADDR_CFG_UNKNOWN (0) -#define SLNETIF_ADDR_CFG_DHCP (1) -#define SLNETIF_ADDR_CFG_DHCP_LLA (2) -#define SLNETIF_ADDR_CFG_STATIC (4) -#define SLNETIF_ADDR_CFG_STATELESS (5) -#define SLNETIF_ADDR_CFG_STATEFUL (6) - -/* Security object types for load Sec Obj function */ -#define SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY (1) -#define SLNETIF_SEC_OBJ_TYPE_CERTIFICATE (2) -#define SLNETIF_SEC_OBJ_TYPE_DH_KEY (3) - - -/* The 32bit queryBitmap structure - SlNetIf_queryIf function: - Bit 0 : Interface state - Check if interface state set to enable - Bit 1 : Interface connection status - Check if interface connection status is up - Bit 2 : Force answer - Return last found netIf, if none of the existing interfaces answers the query - Bits 3-31 : Reserved -*/ -#define SLNETIF_QUERY_IF_STATE_BIT (1 << 0) -#define SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT (1 << 1) -#define SLNETIF_QUERY_IF_ALLOW_PARTIAL_MATCH_BIT (1 << 2) - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/*! - \brief SlNetIf_Config_t structure contains all the function callbacks that are expected to be filled by the relevant network stack interface \n - Each interface has different capabilities, so not all the API's must be supported therefore an API's can be defined as: - - Mandatory API's - must be supported by the interface in order to be part of SlNetSock layer - - Non-Mandatory API's - can be supported, but not mandatory for basic SlNetSock proper operation - - \note Interface that is not supporting a non-mandatory API should set it to \b NULL in its function list - - \sa SlNetIf_Config_t -*/ -typedef struct SlNetIf_Config_t -{ - /* socket related API's */ - int16_t (*sockCreate) (void *ifContext, int16_t domain, int16_t type, int16_t protocol, void **sdContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_create */ - int32_t (*sockClose) (int16_t sd, void *sdContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_close */ - int32_t (*sockShutdown) (int16_t sd, void *sdContext, int16_t how); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_shutdown */ - int16_t (*sockAccept) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_accept */ - int32_t (*sockBind) (int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_bind */ - int32_t (*sockListen) (int16_t sd, void *sdContext, int16_t backlog); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_listen */ - int32_t (*sockConnect) (int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_connect */ - int32_t (*sockGetPeerName) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_getPeerName */ - int32_t (*sockGetLocalName) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_getSockName */ - int32_t (*sockSelect) (void *ifContext, int16_t nsds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_select */ - int32_t (*sockSetOpt) (int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_setOpt */ - int32_t (*sockGetOpt) (int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_getOpt */ - int32_t (*sockRecv) (int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_recv */ - int32_t (*sockRecvFrom) (int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_recvFrom */ - int32_t (*sockSend) (int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_send */ - int32_t (*sockSendTo) (int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_sendTo */ - int32_t (*sockstartSec) (int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_startSec */ - - /* util related API's */ - int32_t (*utilGetHostByName) (void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetUtil_getHostByName */ - - /* if related API's */ - int32_t (*ifGetIPAddr) (void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetIf_getIPAddr */ - int32_t (*ifGetConnectionStatus) (void *ifContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetIf_getConnectionStatus */ - int32_t (*ifLoadSecObj) (void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetIf_loadSecObj */ - int32_t (*ifCreateContext) (uint16_t ifID, const char *ifName, void **ifContext); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetIf_add */ - -} SlNetIf_Config_t; - - -/*! - \brief The SlNetIf_t structure holds the configuration of the interface - Its ID, name, flags and the configuration list - ::SlNetIf_Config_t. -*/ -typedef struct SlNetIf_t -{ - uint32_t ifID; - char *ifName; - int32_t flags; - SlNetIf_Config_t *ifConf; - void *ifContext; -} SlNetIf_t; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Initialize the SlNetIf module - - \param[in] flags For future usage, - The value 0 may be used in order to run the - default flags - - \return Zero on success, or negative error code on failure - -*/ -int32_t SlNetIf_init(int32_t flags); - -/*! - \brief Add a new SlNetIf-compatible interface to the system - - The SlNetIf_add function allows the application to add specific interfaces - with their priorities and function list.\n - This function gives full control to the application on the interfaces. - - \param[in] ifID Specifies the interface which needs - to be added.\n - The values of the interface identifier - is defined with the prefix SLNETIF_ID_ - which defined in slnetif.h - \param[in] ifName Specifies the name of the interface, - \b Note: Can be set to NULL, but when set to NULL - cannot be used with SlNetIf_getIDByName - \param[in] ifConf Specifies the function list for the - interface - \param[in] priority Specifies the priority needs to be - set (In ascending order). - Note: maximum priority is 15 - - \return Zero on success, or negative error code on failure - - \slnetif_not_threadsafe - - \par Examples - - \code - uint8_t priority = 10; - SlNetIf_add(SLNETIF_ID_1, "WiFi_Interface", &SlNetIfConfigWifi, priority); - \endcode -
-*/ -int32_t SlNetIf_add(uint16_t ifID, char *ifName, const SlNetIf_Config_t *ifConf, uint8_t priority); - - -/*! - \brief Get interface configuration from interface ID - - The SlNetIf_getIfByID function retrieves the configuration of the - requested interface. - - \param[in] ifID Specifies the interface which its configuration - needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return A pointer to the configuration of the - interface on success, or NULL on failure - - \sa SlNetIf_add() - - \slnetif_not_threadsafe - - \par Examples - - \code - SlNetIf_t *InterfaceName; - InterfaceName = SlNetIf_getNameByID(SLNETIF_ID_1); - \endcode -
-*/ -SlNetIf_t * SlNetIf_getIfByID(uint16_t ifID); - - -/*! - \brief Get highest priority interface configuration using interface bitmap - - The SlNetIf_getIfByID function retrieves highest priority interface - configuration that can be found in the interface bitmap, or the highest - exists when ifBitmap is zero. - - \param[in,out] ifBitmap Specifies the interface that needs to be checked - according to the queryBitmap and return the - interface with the highest priority.\n - The values of the interface Bitmap is a combination - of the interface identifiers defined with the prefix - SLNETIF_ID_ which defined in slnetif.h - Note: Zero is not a valid parameter, an error will - be returned - \param[in] queryBitmap Specifies the additional criterias for the query - that will be use along the interface priority and - interface ID.\n - queryBitmap bits: - - #SLNETIF_QUERY_IF_STATE_BIT - - #SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT - - \return A pointer to the configuration of the - interface on success, or NULL on failure - - \sa SlNetIf_add() - \slnetif_not_threadsafe - - \par Examples - - \code - SlNetIf_t *InterfaceName; - InterfaceName = SlNetIf_queryIf(SLNETIF_ID_1 | SLNETIF_ID_2 | SLNETIF_ID_3, SLNETIF_QUERY_IF_STATE_BIT | SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT); - \endcode -
-*/ -SlNetIf_t * SlNetIf_queryIf(uint32_t ifBitmap, uint32_t queryBitmap); - - -/*! - \brief Get interface Name from interface ID - - The SlNetIf_getNameByID function retrieves the name of the requested - interface. - - \param[in] ifID Specifies the interface which its name needs - to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return A pointer to the name of the interface on - success, or NULL on failure - - \sa SlNetIf_add() - \sa SlNetIf_getIDByName() - - \slnetif_not_threadsafe - - \par Examples - - \code - char *InterfaceName; - InterfaceName = SlNetIf_getNameByID(SLNETIF_ID_1); - \endcode -
-*/ -const char * SlNetIf_getNameByID(uint16_t ifID); - - -/*! - \brief Get interface ID from interface name - - The SlNetIf_getIDByName function retrieves the interface identifier of the - requested interface name. - - \param[in] ifName Specifies the interface which its interface - identifier needs to be retrieved.\n - - \return The interface identifier value of the interface - on success, or negative error code on failure - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \sa SlNetIf_add() - \sa SlNetIf_getNameByID() - \sa SlNetSock_getIfID() - - \note - Input NULL as ifName will return error code. - - When using more than one interface with the same - name, the ID of the highest priority interface - will be returned - \slnetif_not_threadsafe - - \par Examples - - \code - int16_t InterfaceID; - InterfaceID = SlNetIf_getIDByName("WiFi_Interface"); - \endcode -
-*/ -int32_t SlNetIf_getIDByName(char *ifName); - - -/*! - \brief Get interface priority - - The SlNetIf_getPriority function retrieves the priority of the - interface. - - \param[in] ifID Specifies the interface which its priority - needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return The priority value of the interface on success, - or negative error code on failure - - \sa SlNetIf_add() - \sa SlNetIf_setPriority() - - \slnetif_not_threadsafe - - \par Examples - - \code - int16_t Priority; - Priority = SlNetIf_getPriority(SLNETIF_ID_1); - \endcode -
-*/ -int32_t SlNetIf_getPriority(uint16_t ifID); - - -/*! - \brief Set interface priority - - The SlNetIf_setPriority function sets new priority to the requested interface. - - \param[in] ifID Specifies the interface which its priority - needs to be changed.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - \param[in] priority Specifies the priority needs to be set. - (In ascending order) - Note: maximum priority is 15 - - \return Zero on success, or negative error code on - failure - - \sa SlNetIf_add() - \sa SlNetIf_getPriority() - - \slnetif_not_threadsafe - - \par Examples - - \code - uint8_t priority = 10; - SlNetIf_setPriority(SLNETIF_ID_1, priority); - \endcode -
-*/ -int32_t SlNetIf_setPriority(uint16_t ifID, uint8_t priority); - - -/*! - \brief Set interface state - - Enable or disable the interface. - - \param[in] ifID Specifies the interface which its state - needs to be changed.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - \param[in] ifState Specifies the interface state.\n - The values of the interface state are defined - with the prefix SLNETIF_INTERFACE_ which - defined in slnetif.h - - \return Zero on success, or negative error code on - failure - - \sa SlNetIf_add() - \sa SlNetIf_getState() - - \slnetif_not_threadsafe - - \par Examples - - \code - SlNetIf_setState(SLNETIF_STATE_ENABLE); - \endcode -
-*/ -int32_t SlNetIf_setState(uint16_t ifID, SlNetIfState_e ifState); - - -/*! - \brief Get interface state - - Obtain the current state of the interface. - - \param[in] ifID Specifies the interface which its state needs - to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return State of the interface on success, or negative - error code on failure - - \sa SlNetIf_add() - \sa SlNetIf_setState() - - \slnetif_not_threadsafe - - \par Examples - - \code - int16_t InterfaceState - InterfaceState = SlNetIf_getState(SLNETIF_ID_1); - \endcode -
-*/ -int32_t SlNetIf_getState(uint16_t ifID); - - -/*! - \brief Get interface connection status - - Obtain the connection status of the interface. - - \param[in] ifID Specifies the interface which its connection - status needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return Connection status of the interface on success, - or negative error code on failure - - \sa SlNetIf_add() - - \slnetif_not_threadsafe - - \par Examples - - \code - int16_t connection_status - connection_status = SlNetIf_getConnectionStatus(SLNETIF_ID_1); - \endcode -
-*/ -int32_t SlNetIf_getConnectionStatus(uint16_t ifID); - - -/*! - \brief Get IP Address of specific interface - - The SlNetIf_getIPAddr function retrieve the IP address of a specific - interface according to the Address Type, IPv4, IPv6 LOCAL - or IPv6 GLOBAL. - - \param[in] ifID Specifies the interface which its connection - state needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - \param[in] addrType Address type: - - #SLNETIF_IPV4_ADDR - - #SLNETIF_IPV6_ADDR_LOCAL - - #SLNETIF_IPV6_ADDR_GLOBAL - \param[out] addrConfig Address config: - - #SLNETIF_ADDR_CFG_UNKNOWN - - #SLNETIF_ADDR_CFG_DHCP - - #SLNETIF_ADDR_CFG_DHCP_LLA - - #SLNETIF_ADDR_CFG_STATIC - - #SLNETIF_ADDR_CFG_STATELESS - - #SLNETIF_ADDR_CFG_STATEFUL - \param[out] ipAddr IP Address according to the Address Type - - \return Zero on success, or negative error code on failure - - \sa SlNetIfAddressType_e - - \slnetif_not_threadsafe - - \par Examples - - \code - SlNetSock_In6Addr_t IPAdd; - uint16_t addressConfig = 0; - SlNetIf_getIPAddr(SLNETIF_ID_1, SLNETIF_IPV6_ADDR_LOCAL, &addressConfig, (uint8_t *)ipAddr); - \endcode -
-*/ -int32_t SlNetIf_getIPAddr(uint16_t ifID, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); - - -/*! - \brief Load secured buffer to the network stack - - The SlNetSock_secLoadObj function loads buffer/files into the inputted - network stack for future usage of the socket SSL/TLS connection. - This option is relevant for network stacks with file system and also for - network stacks that lack file system that can store the secured files. - - \param[in] objType Specifies the security object type which - could be one of the following:\n - - #SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY - - #SLNETIF_SEC_OBJ_TYPE_CERTIFICATE - - #SLNETIF_SEC_OBJ_TYPE_DH_KEY - \param[in] objName Specifies the name/input identifier of the - secured buffer loaded - for file systems - this can be the file name - for plain text buffer loading this can be the - name of the object - \param[in] objNameLen Specifies the buffer name length to be loaded.\n - \param[in] objBuff Specifies the pointer to the secured buffer to - be loaded.\n - \param[in] objBuffLen Specifies the buffer length to be loaded.\n - \param[in] ifBitmap Specifies the interfaces which the security - objects needs to be added to.\n - The values of the interface identifiers - is defined with the prefix SLNETIF_ID_ - which defined in slnetif.h - - \return On success, buffer type handler index to be - used when attaching the secured buffer to a - socket.\n - A successful return code should be a positive - number (int16)\n - On error, a negative value will be returned - specifying the error code. - - #SLNETERR_STATUS_ERROR - load operation failed - - \sa SlNetSock_setOpt() - - \slnetif_not_threadsafe - -*/ -int32_t SlNetIf_loadSecObj(uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen, uint32_t ifBitmap); - -/*! - - Close the Doxygen group. - @} - -*/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SL_NET_IF_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetsock.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetsock.h deleted file mode 100755 index 804113a8aef..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetsock.h +++ /dev/null @@ -1,1846 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - /*! - - - \page SlNetSock_overview SlNetSock - - \section intro_sec Introduction - -SlNetSock provides a standard BSD API for TCP and UDP transport -layers, and a lower-level SlNetSock API for basic and extended -usage. Supported use cases include: - - - Support of multi interface (WiFi NS, Ethernet NDK) - - Selecting which interfaces the host will use, one or more. - - Support of different types of sockets (TCP, TLS, UDP, RAW, RF, etc.) - - BSD and proprietary errors - - The SlNetSock API's lead to easier portability to microcontrollers, - without compromising the capabilities and robustness of the final - application. - - - \section modules_sec Module Names - TI's SlNetSock layer is divided into the following software modules: - -# \ref SlNetSock - Controls standard client/server sockets options and capabilities - -# \ref SlNetIf - Controls standard stack/interface options and capabilities - -# \ref SlNetUtils - Provides sockets related commands and configuration - -# \ref SlNetErr - Provide BSD and proprietary errors - -In addition, SlNetSock provides a standard BSD API, built atop the -SlNet* APIs. The BSD headers are placed in ti/net/bsd directory, -which users should place on their include path. - -Also, there is a light -\subpage porting_guide "SL Interface Porting Guide" -with information available for adding SlNetSock support for other stacks. - - \page porting_guide SL Interface Porting Guide - - \section Introduction - -The generic SlNetSock layer sits between the application/service and -the interface stack. This guide describes the details of adding a network stack into the SlNetSock environment. - -The porting steps for adding new interface: - -# Create slnetifxxx file for the new interface - -# Select the capabilities set - -# Adding the interface to your application/service - -# Add the relevant functions to your application/service - -# Test your code to validate the correctness of your porting - - \subsection porting_step1 Step 1 - slnetifxxx.c and slnetifxxx.h file for your interface - - - Create slnetifxxx file (replace xxx with your interface/stack - name). Likely you will copy from an existing port. - - - Implement the needed API's. - -Each interface needs to provide a set of API's to work with the -interface. Some are mandatory, others are optional (but recommended). - - - Mandatory API's: - - \ref SlNetIf_Config_t.sockCreate "sockCreate" - - \ref SlNetIf_Config_t.sockClose "sockClose" - - \ref SlNetIf_Config_t.sockSelect "sockSelect" - - \ref SlNetIf_Config_t.sockSetOpt "sockSetOpt" - - \ref SlNetIf_Config_t.sockGetOpt "sockGetOpt" - - \ref SlNetIf_Config_t.sockRecvFrom "sockRecvFrom" - - \ref SlNetIf_Config_t.sockSendTo "sockSendTo" - - \ref SlNetIf_Config_t.ifGetIPAddr "ifGetIPAddr" - - \ref SlNetIf_Config_t.ifGetConnectionStatus "ifGetConnectionStatus" - - - The non-mandatory API's set: - - \ref SlNetIf_Config_t.sockShutdown "sockShutdown" - - \ref SlNetIf_Config_t.sockAccept "sockAccept" - - \ref SlNetIf_Config_t.sockBind "sockBind" - - \ref SlNetIf_Config_t.sockListen "sockListen" - - \ref SlNetIf_Config_t.sockConnect "sockConnect" - - \ref SlNetIf_Config_t.sockGetPeerName "sockGetPeerName" - - \ref SlNetIf_Config_t.sockGetLocalName "sockGetLocalName" - - \ref SlNetIf_Config_t.sockRecv "sockRecv" - - \ref SlNetIf_Config_t.sockSend "sockSend" - - \ref SlNetIf_Config_t.sockstartSec "sockstartSec" - - \ref SlNetIf_Config_t.utilGetHostByName "utilGetHostByName" - - \ref SlNetIf_Config_t.ifLoadSecObj "ifLoadSecOjb" - - \ref SlNetIf_Config_t.ifCreateContext "ifCreateContext" - - - \note The list of API's and more data can be found in ::SlNetIf_Config_t structure in SlNetIf module \n \n - - \subsection porting_step2 Step 2 - Select the capabilities set - - The capabilities prototype should be declared in your slnetifxxx.h and implemented in your slnetifxxx.c - - Each mandatory API's must be set, additional API's can be set or must - be set to NULL. - - An example config declaration for TI's SimpleLink CC31XX/CC32xx - - \code - SlNetIfConfig SlNetIfConfigWiFi = - { - SlNetIfWifi_socket, // Callback function sockCreate in slnetif module - SlNetIfWifi_close, // Callback function sockClose in slnetif module - NULL, // Callback function sockShutdown in slnetif module - SlNetIfWifi_accept, // Callback function sockAccept in slnetif module - SlNetIfWifi_bind, // Callback function sockBind in slnetif module - SlNetIfWifi_listen, // Callback function sockListen in slnetif module - SlNetIfWifi_connect, // Callback function sockConnect in slnetif module - NULL, // Callback function sockGetPeerName in slnetif module - NULL, // Callback function sockGetLocalName in slnetif module - SlNetIfWifi_select, // Callback function sockSelect in slnetif module - SlNetIfWifi_setSockOpt, // Callback function sockSetOpt in slnetif module - SlNetIfWifi_getSockOpt, // Callback function sockGetOpt in slnetif module - SlNetIfWifi_recv, // Callback function sockRecv in slnetif module - SlNetIfWifi_recvFrom, // Callback function sockRecvFrom in slnetif module - SlNetIfWifi_send, // Callback function sockSend in slnetif module - SlNetIfWifi_sendTo, // Callback function sockSendTo in slnetif module - SlNetIfWifi_sockstartSec, // Callback function sockstartSec in slnetif module - SlNetIfWifi_getHostByName, // Callback function utilGetHostByName in slnetif module - SlNetIfWifi_getIPAddr, // Callback function ifGetIPAddr in slnetif module - SlNetIfWifi_getConnectionStatus, // Callback function ifGetConnectionStatus in slnetif module - SlNetIfWifi_loadSecObj, // Callback function ifLoadSecObj in slnetif module - NULL // Callback function ifCreateContext in slnetif module - }; - \endcode - - In the example above the following API's are not supported by the interface, - and are set to NULL: - - sockShutdown - - sockGetPeerName - - sockGetLocalName - - utilGetHostByName - - ifCreateContext - - \subsection porting_step3 Step 3 - Adding the interface to your application/service - - \b Include the new file in the board header file in the application. - - \subsection porting_step4 Step 4 - Add the relevant functions to your application/service - - After configuring the capabilities of the interface, Adding the interface to the SlNetSock - is required. - - Use ::SlNetIf_add in order to add the interface and set his ID, Name, function list and priority. - Later on you need to use the BSD API's or SlNetSock API's for socket handling. - - \subsection porting_step5 Step 5 - Test your code to validate the correctness of your porting - - After porting the layer into your setup, validate that your code work as expected - -*/ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#ifndef __SL_NET_SOCK_H__ -#define __SL_NET_SOCK_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/*! - \defgroup SlNetSock SlNetSock group - - \short Controls standard client/server sockets options and capabilities - -*/ -/*! - - \addtogroup SlNetSock - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SLNETSOCK_MAX_CONCURRENT_SOCKETS (32) /**< Declares the maximum sockets that can be opened */ - -/* Address families. */ -#define SLNETSOCK_AF_UNSPEC (0) /**< Unspecified address family */ -#define SLNETSOCK_AF_INET (2) /**< IPv4 socket (UDP, TCP, etc) */ -#define SLNETSOCK_AF_INET6 (3) /**< IPv6 socket (UDP, TCP, etc) */ -#define SLNETSOCK_AF_RF (6) /**< Data include RF parameter, All layer by user (Wifi could be disconnected) */ -#define SLNETSOCK_AF_PACKET (17) /**< Network bypass */ - -/* Protocol families, same as address families. */ -#define SLNETSOCK_PF_UNSPEC SLNETSOCK_AF_UNSPEC -#define SLNETSOCK_PF_INET SLNETSOCK_AF_INET -#define SLNETSOCK_PF_INET6 SLNETSOCK_AF_INET6 - -/* Define argument types specifies the socket type. */ -#define SLNETSOCK_SOCK_STREAM (1) /**< TCP Socket */ -#define SLNETSOCK_SOCK_DGRAM (2) /**< UDP Socket */ -#define SLNETSOCK_SOCK_RAW (3) /**< Raw socket */ -#define SLNETSOCK_SOCK_RX_MTR (4) /**< RX Metrics socket */ -#define SLNETSOCK_SOCK_MAC_WITH_CCA (5) -#define SLNETSOCK_SOCK_MAC_WITH_NO_CCA (6) -#define SLNETSOCK_SOCK_BRIDGE (7) -#define SLNETSOCK_SOCK_ROUTER (8) - -/* Define some BSD protocol constants. */ -#define SLNETSOCK_PROTO_TCP (6) /**< TCP Raw Socket */ -#define SLNETSOCK_PROTO_UDP (17) /**< UDP Raw Socket */ -#define SLNETSOCK_PROTO_RAW (255) /**< Raw Socket */ -#define SLNETSOCK_PROTO_SECURE (100) /**< Secured Socket Layer (SSL,TLS) */ - -/* bind any addresses */ -#define SLNETSOCK_INADDR_ANY (0) -#define SLNETSOCK_IN6ADDR_ANY (0) - - -/* socket options */ - -/* possible values for the level parameter in slNetSock_setOpt / slNetSock_getOpt */ -#define SLNETSOCK_LVL_SOCKET (1) /**< Define the socket option category. */ -#define SLNETSOCK_LVL_IP (2) /**< Define the IP option category. */ -#define SLNETSOCK_LVL_PHY (3) /**< Define the PHY option category. */ - -/* possible values for the option parameter in slNetSock_setOpt / slNetSock_getOpt */ - -/* socket level options (SLNETSOCK_LVL_SOCKET) */ -#define SLNETSOCK_OPSOCK_RCV_BUF (8) /**< Setting TCP receive buffer size (window size) - This options takes SlNetSock_Winsize_t struct as parameter */ -#define SLNETSOCK_OPSOCK_RCV_TIMEO (20) /**< Enable receive timeout - This options takes SlNetSock_Timeval_t struct as parameter */ -#define SLNETSOCK_OPSOCK_KEEPALIVE (9) /**< Connections are kept alive with periodic messages - This options takes SlNetSock_Keepalive_t struct as parameter */ -#define SLNETSOCK_OPSOCK_KEEPALIVE_TIME (37) /**< keepalive time out - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPSOCK_LINGER (13) /**< Socket lingers on close pending remaining send/receive packets - This options takes SlNetSock_linger_t struct as parameter */ -#define SLNETSOCK_OPSOCK_NON_BLOCKING (24) /**< Enable/disable nonblocking mode - This options takes SlNetSock_Nonblocking_t struct as parameter */ -#define SLNETSOCK_OPSOCK_NON_IP_BOUNDARY (39) /**< connectionless socket disable rx boundary - This options takes SlNetSock_NonIpBoundary_t struct as parameter */ -#define SLNETSOCK_OPSOCK_ERROR (58) /**< Socket level error code */ -#define SLNETSOCK_OPSOCK_SLNETSOCKSD (59) /**< Used by the BSD layer in order to retrieve the slnetsock sd */ - -/* IP level options (SLNETSOCK_LVL_IP) */ -#define SLNETSOCK_OPIP_MULTICAST_TTL (61) /**< Specify the TTL value to use for outgoing multicast packet. - This options takes uint8_t as parameter */ -#define SLNETSOCK_OPIP_ADD_MEMBERSHIP (65) /**< Join IPv4 multicast membership - This options takes SlNetSock_IpMreq_t struct as parameter */ -#define SLNETSOCK_OPIP_DROP_MEMBERSHIP (66) /**< Leave IPv4 multicast membership - This options takes SlNetSock_IpMreq_t struct as parameter */ -#define SLNETSOCK_OPIP_HDRINCL (67) /**< Raw socket IPv4 header included - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPIP_RAW_RX_NO_HEADER (68) /**< Proprietary socket option that does not includeIPv4/IPv6 header (and extension headers) on received raw sockets - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (69) /**< Transmitted buffer over IPv6 socket contains IPv6 header - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPIPV6_ADD_MEMBERSHIP (70) /**< Join IPv6 multicast membership - This options takes SlNetSock_IpV6Mreq_t struct as parameter */ -#define SLNETSOCK_OPIPV6_DROP_MEMBERSHIP (71) /**< Leave IPv6 multicast membership - This options takes SlNetSock_IpV6Mreq_t struct as parameter */ -#define SLNETSOCK_OPIPV6_MULTICAST_HOPS (72) /**< Specify the hops value to use for outgoing multicast packet. */ - -/* PHY level options (SLNETSOCK_LVL_PHY) */ -#define SLNETSOCK_OPPHY_CHANNEL (28) /**< This option is available only when transceiver started - This options takes uint32_t as channel number parameter */ -#define SLNETSOCK_OPPHY_RATE (100) /**< WLAN Transmit rate - This options takes uint32_t as parameter based on SlWlanRateIndex_e */ -#define SLNETSOCK_OPPHY_TX_POWER (101) /**< TX Power level - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX (102) /**< Number of frames to transmit - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPPHY_PREAMBLE (103) /**< Preamble for transmission - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD (104) /**< TX Inhibit Threshold (CCA) - This options takes uint32_t as parameter based on SlNetSockTxInhibitThreshold_e */ -#define SLNETSOCK_OPPHY_TX_TIMEOUT (105) /**< TX timeout for Transceiver frames (lifetime) in miliseconds (max value is 100ms) - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPPHY_ALLOW_ACKS (106) /**< Enable sending ACKs in transceiver mode - This options takes uint32_t as parameter */ - -/*! - \brief The SlNetSockTxInhibitThreshold_e enumerations is used in SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD PHY level option -*/ -typedef enum -{ - SLNETSOCK_TX_INHIBIT_THRESHOLD_MIN = 1, - SLNETSOCK_TX_INHIBIT_THRESHOLD_LOW = 2, - SLNETSOCK_TX_INHIBIT_THRESHOLD_DEFAULT = 3, - SLNETSOCK_TX_INHIBIT_THRESHOLD_MED = 4, - SLNETSOCK_TX_INHIBIT_THRESHOLD_HIGH = 5, - SLNETSOCK_TX_INHIBIT_THRESHOLD_MAX = 6 -} SlNetSockTxInhibitThreshold_e; - -/*! - \brief The SlNetSockSecAttrib_e enumerations are used to declare security - attribute objects in SlNetSock_secAttribSet(). - - \sa SlNetSock_secAttribSet() -*/ -typedef enum -{ - SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY = 0, - SLNETSOCK_SEC_ATTRIB_LOCAL_CERT = 1, - SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA = 2, - SLNETSOCK_SEC_ATTRIB_DH_KEY = 3, - SLNETSOCK_SEC_ATTRIB_METHOD = 4, - SLNETSOCK_SEC_ATTRIB_CIPHERS = 5, - SLNETSOCK_SEC_ATTRIB_ALPN = 6, - SLNETSOCK_SEC_ATTRIB_EXT_CLIENT_CHLNG_RESP = 7, - SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME = 8, - - /*! - @c SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE is - currently only supported on CC3x20 devices. - - The certificate store is a file, provided by TI, - containing a list of known and trusted root CAs by TI. - For more information, see the CC3x20 documentation. - - The certificate store is used only in client mode. Servers - use a proprietary root CA to authenticate clients, and - therefore cannot use the certificate store. - - Using this attribute allows using root CA which isn't a - part of the provided certificate store. - */ - - SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE = 9 -} SlNetSockSecAttrib_e; - -/* available values for SLNETSOCK_SEC_ATTRIB_METHOD */ -#define SLNETSOCK_SEC_METHOD_SSLV3 (0) /**< security method SSL v3 */ -#define SLNETSOCK_SEC_METHOD_TLSV1 (1) /**< security method TLS v1 */ -#define SLNETSOCK_SEC_METHOD_TLSV1_1 (2) /**< security method TLS v1_1 */ -#define SLNETSOCK_SEC_METHOD_TLSV1_2 (3) /**< security method TLS v1_2 */ -#define SLNETSOCK_SEC_METHOD_SSLv3_TLSV1_2 (4) /**< use highest possible version from SSLv3 - TLS 1.2 */ -#define SLNETSOCK_SEC_METHOD_DLSV1 (5) /**< security method DTL v1 */ - -/* available values for SLNETSOCK_SEC_ATTRIB_CIPHERS. The value is bitmap! */ -#define SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_SHA (1 << 0) -#define SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_MD5 (1 << 1) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA (1 << 2) -#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_256_CBC_SHA (1 << 3) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA (1 << 4) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_RC4_128_SHA (1 << 5) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_128_CBC_SHA256 (1 << 6) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA256 (1 << 7) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (1 << 8) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (1 << 9) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA (1 << 10) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA (1 << 11) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_128_GCM_SHA256 (1 << 12) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_GCM_SHA384 (1 << 13) -#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 14) -#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 15) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 16) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 17) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (1 << 18) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 (1 << 19) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 20) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 21) -#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 22) -#define SLNETSOCK_SEC_CIPHER_FULL_LIST (0xFFFFFFFF) - -/* available values for SLNETSOCK_SEC_ATTRIB_ALPN */ -#define SLNETSOCK_SEC_ALPN_H1 (1 << 0) -#define SLNETSOCK_SEC_ALPN_H2 (1 << 1) -#define SLNETSOCK_SEC_ALPN_H2C (1 << 2) -#define SLNETSOCK_SEC_ALPN_H2_14 (1 << 3) -#define SLNETSOCK_SEC_ALPN_H2_16 (1 << 4) -#define SLNETSOCK_SEC_ALPN_FULL_LIST ((SLNETSOCK_SEC_ALPN_H2_16 << 1 ) - 1) - -/* available values for the flags of the SlNetSock_startSec function */ -#define SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY (1 << 0) /**< Sends the command that will start the security session for a specific socket descriptor */ -#define SLNETSOCK_SEC_BIND_CONTEXT_ONLY (1 << 1) /**< Binds the security context to a specific socket descriptor */ -#define SLNETSOCK_SEC_IS_SERVER (1 << 2) /**< Used to define if the socket is client/server socket */ - -/* available values for the flags of the SlNetSock_create function */ - -#define SLNETSOCK_CREATE_IF_STATE_ENABLE (1 << 0) /**< Creation of the socket will be on enabled state */ -#define SLNETSOCK_CREATE_IF_STATUS_CONNECTED (1 << 1) /**< Creation of the socket will be on status connected */ -#define SLNETSOCK_CREATE_ALLOW_PARTIAL_MATCH (1 << 2) /**< Creation of the socket will be on the interface with - the highest priority if the other flags will fail */ - -/* Definitions for shutting down some or all parts of a full duplex connection */ -#define SLNETSOCK_SHUT_RD (0) /**< Further receptions will be disallowed */ -#define SLNETSOCK_SHUT_WR (1) /**< Further transmissions will be disallowed */ -#define SLNETSOCK_SHUT_RDWR (2) /**< Further receptions and transmissions will be disallowed */ - -/* Length of address string representation */ -#define SLNETSOCK_INET6_ADDRSTRLEN (46) -#define SLNETSOCK_INET_ADDRSTRLEN (16) - -/* flags used in send/recv and friends. - * - * Note these flags must not exceed 24-bits. The implementation will - * OR the 8-bits of security flags into the remaining high 8 bits of - * 32-bit flag variables. - */ -#define SLNETSOCK_MSG_OOB (0x0001) -#define SLNETSOCK_MSG_PEEK (0x0002) -#define SLNETSOCK_MSG_WAITALL (0x0004) -#define SLNETSOCK_MSG_DONTWAIT (0x0008) -#define SLNETSOCK_MSG_DONTROUTE (0x0010) -#define SLNETSOCK_MSG_NOSIGNAL (0x0020) - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/*! - \brief Internet address -*/ -typedef struct SlNetSock_InAddr_t -{ -#ifndef s_addr - uint32_t s_addr; /* Internet address 32 bits */ -#else -/*! - \brief Different representations for in addr for different hosts. -*/ - union S_un - { - uint32_t S_addr; - struct - { - uint8_t s_b1,s_b2,s_b3,s_b4; - } S_un_b; - struct - { - uint16_t s_w1,s_w2; - } S_un_w; - } S_un; -#endif -} SlNetSock_InAddr_t; - -/*! - \brief IpV6 or Ipv6 EUI64 -*/ -typedef struct SlNetSock_In6Addr_t -{ - union - { - uint8_t _S6_u8[16]; - uint16_t _S6_u16[8]; - uint32_t _S6_u32[4]; - } _S6_un; -} SlNetSock_In6Addr_t; - -/*! - \brief The SlNetSock_Keepalive_t structure is used in #SLNETSOCK_OPSOCK_KEEPALIVE socket level option -*/ -typedef struct SlNetSock_Keepalive_t -{ - uint32_t keepaliveEnabled; /**< 0 = disabled;1 = enabled; default = 1 */ -} SlNetSock_Keepalive_t; - -/*! - \brief The SlNetSock_NonIpBoundary_t structure is used in #SLNETSOCK_OPSOCK_NON_IP_BOUNDARY socket level option -*/ -typedef struct SlNetSock_NonIpBoundary_t -{ - int32_t nonIpBoundaryEnabled; /**< 0 = keep IP boundary; 1 = don`t keep ip boundary; default = 0; */ -} SlNetSock_NonIpBoundary_t; - -/*! - \brief The SlNetSock_Winsize_t structure is used in #SLNETSOCK_OPSOCK_RCV_BUF socket level option -*/ -typedef struct SlNetSock_Winsize_t -{ - uint32_t winSize; /**< receive window size for tcp sockets */ -} SlNetSock_Winsize_t; - -/*! - \brief The SlNetSock_Nonblocking_t structure is used in #SLNETSOCK_OPSOCK_NON_BLOCKING socket level option -*/ -typedef struct SlNetSock_Nonblocking_t -{ - uint32_t nonBlockingEnabled; /**< 0 = disabled, 1 = enabled, default = 1*/ -} SlNetSock_Nonblocking_t; - -/*! - \brief Secure socket attribute context -*/ -typedef struct SlNetSock_SecAttribNode_t -{ - SlNetSockSecAttrib_e attribName; /**< Security attribute name */ - uint8_t *attribBuff; /**< Security attribute buffer */ - uint16_t attribBuffLen; /**< Security attribute buffer length */ - struct SlNetSock_SecAttribNode_t *next; -} SlNetSock_SecAttribNode_t; - -/*! - \brief Secure socket attribute handler -*/ -typedef SlNetSock_SecAttribNode_t * SlNetSockSecAttrib_t; - -/*! - \brief Secure ALPN structure -*/ -typedef struct SlNetSock_SecureALPN_t -{ - uint32_t secureALPN; -} SlNetSock_SecureALPN_t; - -/*! - \brief Secure Mask structure -*/ -typedef struct SlNetSock_SecureMask_t -{ - uint32_t secureMask; -} SlNetSock_SecureMask_t; - -/*! - \brief Secure Method structure -*/ -typedef struct SlNetSock_SecureMethod_t -{ - uint8_t secureMethod; -} SlNetSock_SecureMethod_t; - -/*! - \brief The SlNetSock_IpMreq_t structure is used in #SLNETSOCK_OPIP_ADD_MEMBERSHIP and #SLNETSOCK_OPIP_DROP_MEMBERSHIP IP level option -*/ -typedef struct SlNetSock_IpMreq_t -{ - SlNetSock_InAddr_t imr_multiaddr; /**< The IPv4 multicast address to join */ - uint32_t imr_interface; /**< The interface to use for this group */ -} SlNetSock_IpMreq_t; - -/*! - \brief The SlNetSock_IpV6Mreq_t structure is used in #SLNETSOCK_OPIPV6_ADD_MEMBERSHIP and #SLNETSOCK_OPIPV6_DROP_MEMBERSHIP IP level option -*/ -typedef struct SlNetSock_IpV6Mreq_t -{ - SlNetSock_In6Addr_t ipv6mr_multiaddr; /**< IPv6 multicast address of group */ - uint32_t ipv6mr_interface; /**< should be 0 to choose the default multicast interface */ -} SlNetSock_IpV6Mreq_t; - -/*! - \brief The SlNetSock_linger_t structure is used in #SLNETSOCK_OPSOCK_LINGER socket level option -*/ -typedef struct SlNetSock_linger_t -{ - uint32_t l_onoff; /**< 0 = disabled; 1 = enabled; default = 0; */ - uint32_t l_linger; /**< linger time in seconds; default = 0; */ -} SlNetSock_linger_t; - -/*! - \brief The SlNetSockTime_t is used for setting/getting time in seconds -*/ -typedef int32_t SlNetSockTime_t; -/*! - \brief The SlNetSockuseconds_t is used for setting/getting time in micro-seconds -*/ -typedef int32_t SlNetSockuseconds_t; - -/*! - \brief The SlNetSock_Timeval_t structure is used in #SLNETSOCK_OPSOCK_RCV_TIMEO socket level option -*/ -typedef struct SlNetSock_Timeval_t -{ - SlNetSockTime_t tv_sec; /**< Seconds */ - SlNetSockuseconds_t tv_usec; /**< Microseconds */ -} SlNetSock_Timeval_t; - -/*! - \brief The SlNetSocklen_t is used for declaring the socket length parameter -*/ -typedef uint16_t SlNetSocklen_t; - -/*! - \brief IpV4 socket address -*/ -typedef struct SlNetSock_Addr_t -{ - uint16_t sa_family; /**< Address family (e.g. AF_INET) */ - uint8_t sa_data[14]; /**< Protocol- specific address information */ -} SlNetSock_Addr_t; - -/*! - \brief SlNetSock IPv6 address, Internet style -*/ -typedef struct SlNetSock_AddrIn6_t -{ - uint16_t sin6_family; /**< SLNETSOCK_AF_INET6 */ - uint16_t sin6_port; /**< Transport layer port. */ - uint32_t sin6_flowinfo; /**< IPv6 flow information. */ - SlNetSock_In6Addr_t sin6_addr; /**< IPv6 address. */ - uint32_t sin6_scope_id; /**< set of interfaces for a scope. */ -} SlNetSock_AddrIn6_t; - -/*! - \brief SlNetSock IPv4 address, Internet style -*/ -typedef struct SlNetSock_AddrIn_t -{ - uint16_t sin_family; /**< Internet Protocol (AF_INET). */ - uint16_t sin_port; /**< Address port (16 bits). */ - SlNetSock_InAddr_t sin_addr; /**< Internet address (32 bits). */ - int8_t sin_zero[8]; /**< Not used. */ -} SlNetSock_AddrIn_t; - -/*! - \brief The SlNetSock_SdSet_t structure holds the sd array for SlNetSock_select function -*/ -typedef struct SlNetSock_SdSet_t /**< The select socket array manager */ -{ - uint32_t sdSetBitmap[(SLNETSOCK_MAX_CONCURRENT_SOCKETS + (uint8_t)31)/(uint8_t)32]; /* Bitmap of SOCKET Descriptors */ -} SlNetSock_SdSet_t; - - -/*! - \brief The SlNetSock_TransceiverRxOverHead_t structure holds the data for Rx transceiver mode using a raw socket when using SlNetSock_recv function -*/ -typedef struct SlNetSock_TransceiverRxOverHead_t -{ - uint8_t rate; /**< Received Rate */ - uint8_t channel; /**< The received channel */ - int8_t rssi; /**< The computed RSSI value in db of current frame */ - uint8_t padding; /**< pad to align to 32 bits */ - uint32_t timestamp; /**< Timestamp in microseconds */ -} SlNetSock_TransceiverRxOverHead_t; - - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Initialize the SlNetSock module - - \param[in] flags Reserved - - \return Zero on success, or negative error code on failure -*/ -int32_t SlNetSock_init(int32_t flags); - -/*! - - \brief Create an endpoint for communication - - SlNetSock_create() creates a new socket of a certain socket type, - identified by an integer number, and allocates system resources to it.\n - This function is called by the application layer to obtain a socket descriptor (handle). - - \param[in] domain Specifies the protocol family of the created socket. - For example: - - #SLNETSOCK_AF_INET for network protocol IPv4 - - #SLNETSOCK_AF_INET6 for network protocol IPv6 - - #SLNETSOCK_AF_RF for starting transceiver mode. - Notes: - - sending and receiving any packet overriding 802.11 header - - for optimized power consumption the socket will be started in TX - only mode until receive command is activated - \param[in] type Specifies the socket type, which determines the semantics of communication over - the socket. The socket types supported by the system are implementation-dependent. - Possible socket types include: - - #SLNETSOCK_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) - - #SLNETSOCK_SOCK_DGRAM (datagram service or Datagram Sockets) - - #SLNETSOCK_SOCK_RAW (raw protocols atop the network layer) - - when used with AF_RF: - - #SLNETSOCK_SOCK_RX_MTR - - #SLNETSOCK_SOCK_MAC_WITH_CCA - - #SLNETSOCK_SOCK_MAC_WITH_NO_CCA - - #SLNETSOCK_SOCK_BRIDGE - - #SLNETSOCK_SOCK_ROUTER - \param[in] protocol Specifies a particular transport to be used with the socket.\n - The most common are - - #SLNETSOCK_PROTO_TCP - - #SLNETSOCK_PROTO_UDP - - #SLNETSOCK_PROTO_RAW - - #SLNETSOCK_PROTO_SECURE - \param[in] ifBitmap Specifies the interface(s) which the socket will be create on - according to the priority until one of them will return an answer.\n - Value 0 is used in order to choose automatic interfaces selection - according to the priority interface list. - Value can be combination of interfaces by OR'ing multiple interfaces bit identifiers - (SLNETIFC_IDENT_ defined in slnetif.h) - Note: interface identifier bit must be configured prior to this socket creation - using SlNetIf_add(). - \param[in] flags Specifies flags. - - #SLNETSOCK_CREATE_IF_STATE_ENABLE - Creation of the socket will be on enabled state - - #SLNETSOCK_CREATE_IF_STATUS_CONNECTED - Creation of the socket will be on status connected - - #SLNETSOCK_CREATE_ALLOW_PARTIAL_MATCH - Creation of the socket will be on the interface with - the highest priority if the other flags will fail - The value 0 may be used in order to run the default flags: - - #SLNETSOCK_CREATE_IF_STATE_ENABLE - - #SLNETSOCK_CREATE_IF_STATUS_CONNECTED - - \return On success, socket descriptor (handle) that is used for consequent socket operations. \n - A successful return code should be a positive number\n - On error, a negative value will be returned specifying the error code. - - #SLNETERR_BSD_EAFNOSUPPORT - illegal domain parameter - - #SLNETERR_BSD_EPROTOTYPE - illegal type parameter - - #SLNETERR_BSD_EACCES - permission denied - - #SLNETERR_BSD_ENSOCK - exceeded maximal number of socket - - #SLNETERR_BSD_ENOMEM - memory allocation error - - #SLNETERR_BSD_EINVAL - error in socket configuration - - #SLNETERR_BSD_EPROTONOSUPPORT - illegal protocol parameter - - #SLNETERR_BSD_EOPNOTSUPP - illegal combination of protocol and type parameters - - \slnetsock_init_precondition - - \remark Not all platforms support all options. - - \remark A @c protocol value of zero can be used to select the default protocol from the selected @c domain and @c type. - - \sa SlNetSock_close() -*/ -int16_t SlNetSock_create(int16_t domain, int16_t type, int16_t protocol, uint32_t ifBitmap, int16_t flags); - - -/*! - \brief Gracefully close socket - - Release resources allocated to a socket. - - \param[in] sd Socket descriptor (handle), received in SlNetSock_create() - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \remark In the case of TCP, the connection is terminated. - - \sa SlNetSock_create() -*/ -int32_t SlNetSock_close(int16_t sd); - - -/*! - \brief Shutting down parts of a full-duplex connection - - Shuts down parts of a full-duplex connection according to how parameter.\n - - \param[in] sd Socket descriptor (handle), received in SlNetSock_create - \param[in] how Specifies which part of a full-duplex connection to shutdown. \n - The options are - - #SLNETSOCK_SHUT_RD - further receptions will be disallowed - - #SLNETSOCK_SHUT_WR - further transmissions will be disallowed - - #SLNETSOCK_SHUT_RDWR - further receptions and transmissions will be disallowed - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \sa SlNetSock_connect() - \sa SlNetSock_accept() -*/ -int32_t SlNetSock_shutdown(int16_t sd, int16_t how); - - -/*! - \brief Accept a connection on a socket - - The SlNetSock_accept function is used with connection-based socket types (#SLNETSOCK_SOCK_STREAM). - - It extracts the first connection request on the queue of pending - connections, creates a new connected socket, and returns a new file - descriptor referring to that socket. - - The newly created socket is not in the listening state. The - original socket sd is unaffected by this call. - - The argument sd is a socket that has been created with - SlNetSock_create(), bound to a local address with - SlNetSock_bind(), and is listening for connections after a - SlNetSock_listen(). - - The argument \c addr is a pointer to a sockaddr structure. This - structure is filled in with the address of the peer socket, as - known to the communications layer. - - The exact format of the address returned \c addr is determined by the socket's address family. - - \c addrlen is a value-result argument: it should initially contain - the size of the structure pointed to by addr, on return it will - contain the actual length (in bytes) of the address returned. - - \param[in] sd Socket descriptor (handle) - \param[out] addr The argument addr is a pointer - to a sockaddr structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - sockaddr:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - - \return On success, a socket descriptor.\n - On a non-blocking accept a possible negative value is #SLNETERR_BSD_EAGAIN.\n - On failure, negative error code.\n - #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \sa SlNetSock_bind() - \sa SlNetSock_listen() -*/ -int16_t SlNetSock_accept(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); - - -/*! - \brief Assign a name to a socket - - This SlNetSock_bind function gives the socket the local address - addr. addr is addrlen bytes long. - - Traditionally, this is called when a socket is created with - socket, it exists in a name space (address family) but has no name - assigned. - - It is necessary to assign a local address before a #SLNETSOCK_SOCK_STREAM - socket may receive connections. - - \param[in] sd Socket descriptor (handle) - \param[in] addr Specifies the destination - addrs\n sockaddr:\n - code for - the address format.\n - socket address, - the length depends on the code - format - \param[in] addrlen Contains the size of the structure pointed to by addr - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \sa SlNetSock_accept() - \sa SlNetSock_listen() -*/ -int32_t SlNetSock_bind(int16_t sd, const SlNetSock_Addr_t *addr, int16_t addrlen); - - -/*! - \brief Listen for connections on a socket - - The willingness to accept incoming connections and a queue - limit for incoming connections are specified with SlNetSock_listen(), - and then the connections are accepted with SlNetSock_accept(). - - \param[in] sd Socket descriptor (handle) - \param[in] backlog Specifies the listen queue depth. - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \remark The SlNetSock_listen() call applies only to sockets of - type #SLNETSOCK_SOCK_STREAM. - - \remark The \c backlog parameter defines the maximum length the queue of - pending connections may grow to. - - \sa SlNetSock_create() - \sa SlNetSock_accept() - \sa SlNetSock_bind() -*/ -int32_t SlNetSock_listen(int16_t sd, int16_t backlog); - - -/*! - \brief Initiate a connection on a socket - - Function connects the socket referred to by the socket - descriptor sd, to the address specified by \c addr. - - The format of the address in addr is determined by the address - space of the socket. - - If it is of type #SLNETSOCK_SOCK_DGRAM, this call specifies the - peer with which the socket is to be associated; this address is - that to which datagrams are to be sent, and the only address from - which datagrams are to be received. - - If the socket is of type #SLNETSOCK_SOCK_STREAM, this call - attempts to make a connection to another socket. - - The other socket is specified by address, which is an address in - the communications space of the socket. - - \param[in] sd Socket descriptor (handle) - \param[in] addr Specifies the destination addr\n - sockaddr:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[in] addrlen Contains the size of the structure pointed - to by addr - - \return On success, a socket descriptor (handle).\n - On failure, negative value.\n - On a non-blocking connect a possible negative value is #SLNETERR_BSD_EALREADY. - #SLNETERR_POOL_IS_EMPTY may be returned in case there are no resources in the system - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \note - \warning -*/ -int32_t SlNetSock_connect(int16_t sd, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen); - -/*! - \brief Return address info about the remote side of the connection - - Returns a struct SlNetSock_AddrIn_t - filled with information about the peer device that is connected - on the other side of the socket descriptor. - - \param[in] sd Socket descriptor (handle) - \param[out] addr returns the struct addr\n - SlNetSockAddrIn filled with information - about the peer device:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen Contains the size of the structure pointed - to by addr - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \sa SlNetSock_accept() - \sa SlNetSock_connect() -*/ -int32_t SlNetSock_getPeerName(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); - - -/*! - \brief Get local address info by socket descriptor - - Returns the local address info of the socket descriptor. - - \param[in] sd Socket descriptor (handle) - \param[out] addr The argument addr is a pointer - to a SlNetSock_Addr_t structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - SlNetSock_Addr_t:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - - \return Zero on success, or negative on failure. - - \slnetsock_init_precondition - - \remark If the provided buffer is too small the returned address - will be truncated and \c addrlen will contain the - actual size of the socket address. - - \sa SlNetSock_create() - \sa SlNetSock_bind() -*/ -int32_t SlNetSock_getSockName(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); - - -/*! - \brief Monitor socket activity - - SlNetSock_select() allow a program to monitor multiple file descriptors, - waiting until one or more of the file descriptors become - "ready" for some class of I/O operation. - - \param[in] nsds The highest-numbered file descriptor in any of the - three sets, plus 1. - \param[in,out] readsds Socket descriptors list for read monitoring and accept monitoring - \param[in,out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported - \param[in,out] exceptsds Socket descriptors list for exception monitoring, not supported. - \param[in] timeout Is an upper bound on the amount of time elapsed - before SlNetSock_select() returns. Null or above 0xffff seconds means - infinity timeout. The minimum timeout is 10 milliseconds, - less than 10 milliseconds will be set automatically to 10 milliseconds. - Max microseconds supported is 0xfffc00. - In trigger mode the timeout fields must be set to zero. - - \return On success, SlNetSock_select() returns the number of - file descriptors contained in the three returned - descriptor sets (that is, the total number of bits that - are set in readsds, writesds, exceptsds) which may be - zero if the timeout expires before anything interesting - happens.\n On error, a negative value is returned. - readsds - return the sockets on which Read request will - return without delay with valid data.\n - writesds - return the sockets on which Write request - will return without delay.\n - exceptsds - return the sockets closed recently. \n - #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - - \slnetsock_init_precondition - - \remark If \c timeout is set to less than 10ms it will - automatically set to 10ms to prevent overload of the - system - - \sa SlNetSock_create() -*/ -int32_t SlNetSock_select(int16_t nsds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); - - -/*! - \brief SlNetSock_select's SlNetSock_SdSet_t SET function - - Sets current socket descriptor on SlNetSock_SdSet_t container -*/ -int32_t SlNetSock_sdsSet(int16_t sd, SlNetSock_SdSet_t *sdset); - - -/*! - \brief SlNetSock_select's SlNetSock_SdSet_t CLR function - - Clears current socket descriptor on SlNetSock_SdSet_t container -*/ -int32_t SlNetSock_sdsClr(int16_t sd, SlNetSock_SdSet_t *sdset); - - -/*! - \brief SlNetSock_select's SlNetSock_SdSet_t ZERO function - - Clears all socket descriptors from SlNetSock_SdSet_t -*/ -int32_t SlNetSock_sdsClrAll(SlNetSock_SdSet_t *sdset); - - -/*! - \brief SlNetSock_select's SlNetSock_SdSet_t ISSET function - - Checks if current socket descriptor is set (true/false) - - \return Returns true if set, false if unset - -*/ -int32_t SlNetSock_sdsIsSet(int16_t sd, SlNetSock_SdSet_t *sdset); - - -/*! - \brief Set socket options - - SlNetSock_setOpt() manipulates the options associated with a socket. - - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level. - - When manipulating socket options the level at which the option resides - and the name of the option must be specified. To manipulate options at - the socket level, level is specified as #SLNETSOCK_LVL_SOCKET. To manipulate - options at any other level the protocol number of the appropriate protocol - controlling the option is supplied. For example, to indicate that an - option is to be interpreted by the TCP protocol, level should be set to - the protocol number of TCP. - - \c optval and \c optlen are used to access opt_values - for SlNetSock_setOpt(). For SlNetSock_getOpt() they identify a - buffer in which the value for the requested option(s) are to - be returned. For SlNetSock_getOpt(), \c optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, \c optval may be \c NULL. - - \param[in] sd Socket descriptor (handle) - \param[in] level Defines the protocol level for this option - - #SLNETSOCK_LVL_SOCKET - Socket level configurations (L4, transport layer) - - #SLNETSOCK_LVL_IP - IP level configurations (L3, network layer) - - #SLNETSOCK_LVL_PHY - Link level configurations (L2, link layer) - \param[in] optname Defines the option name to interrogate - - #SLNETSOCK_LVL_SOCKET - - #SLNETSOCK_OPSOCK_RCV_BUF\n - Sets tcp max recv window size.\n - This options takes SlNetSock_Winsize_t struct as parameter - - #SLNETSOCK_OPSOCK_RCV_TIMEO\n - Sets the timeout value that specifies the maximum amount of time an input function waits until it completes.\n - Default: No timeout\n - This options takes SlNetSock_Timeval_t struct as parameter - - #SLNETSOCK_OPSOCK_KEEPALIVE\n - Enable or Disable periodic keep alive. - Keeps TCP connections active by enabling the periodic transmission of messages \n - Timeout is 5 minutes.\n - Default: Enabled \n - This options takes SlNetSock_Keepalive_t struct as parameter - - #SLNETSOCK_OPSOCK_KEEPALIVE_TIME\n - Set keep alive timeout. - Value is in seconds \n - Default: 5 minutes \n - - #SLNETSOCK_OPSOCK_LINGER\n - Socket lingers on close pending remaining send/receive packets\n - - #SLNETSOCK_OPSOCK_NON_BLOCKING\n - Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n - Default: Blocking. - This options takes SlNetSock_Nonblocking_t struct as parameter - - #SLNETSOCK_OPSOCK_NON_IP_BOUNDARY\n - Enable or Disable rx ip boundary. - In connectionless socket (udp/raw), unread data is dropped (when SlNetSock_recvFrom() len parameter < data size), Enable this option in order to read the left data on the next SlNetSock_recvFrom() iteration\n - Default: Disabled, IP boundary kept\n - This options takes SlNetSock_NonIpBoundary_t struct as parameter - - #SLNETSOCK_LVL_IP - - #SLNETSOCK_OPIP_MULTICAST_TTL\n - Set the time-to-live value of outgoing multicast packets for this socket. \n - This options takes uint8_t as parameter - - #SLNETSOCK_OPIP_ADD_MEMBERSHIP \n - UDP socket, Join a multicast group. \n - This options takes SlNetSock_IpMreq_t struct as parameter - - #SLNETSOCK_OPIP_DROP_MEMBERSHIP \n - UDP socket, Leave a multicast group \n - This options takes SlNetSock_IpMreq_t struct as parameter - - #SLNETSOCK_OPIP_HDRINCL \n - RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. \n - When it is enabled, the packet must contain an IP header. \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPIP_RAW_RX_NO_HEADER \n - Raw socket remove IP header from received data. \n - Default: data includes ip header \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (inactive) \n - RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes uint32_t as parameter - - #SLNETSOCK_LVL_PHY - - #SLNETSOCK_OPPHY_CHANNEL \n - Sets channel in transceiver mode. - This options takes uint32_t as channel number parameter - - #SLNETSOCK_OPPHY_RATE \n - RAW socket, set WLAN PHY transmit rate \n - The values are based on SlWlanRateIndex_e \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_TX_POWER \n - RAW socket, set WLAN PHY TX power \n - Valid rage is 1-15 \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX \n - RAW socket, set number of frames to transmit in transceiver mode. - Default: 1 packet - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_PREAMBLE \n - RAW socket, set WLAN PHY preamble for Long/Short\n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD \n - RAW socket, set WLAN Tx - Set CCA threshold. \n - The values are based on SlNetSockTxInhibitThreshold_e \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_TX_TIMEOUT \n - RAW socket, set WLAN Tx - changes the TX timeout (lifetime) of transceiver frames. \n - Value in Ms, maximum value is 10ms \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_ALLOW_ACKS \n - RAW socket, set WLAN Tx - Enable or Disable sending ACKs in transceiver mode \n - 0 = disabled / 1 = enabled \n - This options takes uint32_t as parameter - - - \param[in] optval Specifies a value for the option - \param[in] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - - \par Persistent - All params are Non- Persistent - - \slnetsock_init_precondition - - \par Examples - - - SLNETSOCK_OPSOCK_RCV_BUF: - \code - SlNetSock_Winsize_t size; - size.winsize = 3000; // bytes - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_BUF, (uint8_t *)&size, sizeof(size)); - \endcode -
- - - SLNETSOCK_OPSOCK_RCV_TIMEO: - \code - struct SlNetSock_Timeval_t timeVal; - timeVal.tv_sec = 1; // Seconds - timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_TIMEO, (uint8_t *)&timeVal, sizeof(timeVal)); // Enable receive timeout - \endcode -
- - - SLNETSOCK_OPSOCK_KEEPALIVE: //disable Keepalive - \code - SlNetSock_Keepalive_t enableOption; - enableOption.keepaliveEnabled = 0; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_KEEPALIVE_TIME: //Set Keepalive timeout - \code - int16_t Status; - uint32_t TimeOut = 120; - SlNetSock_setOpt(Sd, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE_TIME, (uint8_t *)&TimeOut, sizeof(TimeOut)); - \endcode -
- - - SLNETSOCK_OPSOCK_NON_BLOCKING: //Enable or disable nonblocking mode - \code - SlNetSock_Nonblocking_t enableOption; - enableOption.nonBlockingEnabled = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_BLOCKING, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY: //disable boundary - \code - SlNetSock_NonIpBoundary_t enableOption; - enableOption.nonIpBoundaryEnabled = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_IP_BOUNDARY, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_LINGER: - \code - SlNetSock_linger_t linger; - linger.l_onoff = 1; - linger.l_linger = 10; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_LINGER, &linger, sizeof(linger)); - \endcode -
- - - SLNETSOCK_OPIP_MULTICAST_TTL: - \code - uint8_t ttl = 20; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_MULTICAST_TTL, &ttl, sizeof(ttl)); - \endcode -
- - - SLNETSOCK_OPIP_ADD_MEMBERSHIP: - \code - SlNetSock_IpMreq_t mreq; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SLNETSOCK_OPIP_DROP_MEMBERSHIP: - \code - SlNetSock_IpMreq_t mreq; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SLNETSOCK_OPIP_RAW_RX_NO_HEADER: - \code - uint32_t header = 1; // remove ip header - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_RX_NO_HEADER, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPIP_HDRINCL: - \code - uint32_t header = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL: - \code - uint32_t header = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_IPV6_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPPHY_CHANNEL: - \code - uint32_t newChannel = 6; // range is 1-13 - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPPHY_CHANNEL, &newChannel, sizeof(newChannel)); - \endcode -
- - - SLNETSOCK_OPPHY_RATE: - \code - uint32_t rate = 6; // see wlan.h SlWlanRateIndex_e for values - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_RATE, &rate, sizeof(rate)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_POWER: - \code - uint32_t txpower = 1; // valid range is 1-15 - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_POWER, &txpower, sizeof(txpower)); - \endcode -
- - - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX: - \code - uint32_t numframes = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); - \endcode -
- - - SLNETSOCK_OPPHY_PREAMBLE: - \code - uint32_t preamble = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_PREAMBLE, &preamble, sizeof(preamble)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD: - \code - uint32_t thrshld = SLNETSOCK_TX_INHIBIT_THRESHOLD_MED; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD, &thrshld, sizeof(thrshld)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_TIMEOUT: - \code - uint32_t timeout = 50; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_TIMEOUT, &timeout, sizeof(timeout)); - \endcode -
- - - SLNETSOCK_OPPHY_ALLOW_ACKS: - \code - uint32_t acks = 1; // 0 = disabled / 1 = enabled - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_ALLOW_ACKS, &acks, sizeof(acks)); - \endcode - - \sa slNetSock_create() - \sa SlNetSock_getOpt() -*/ -int32_t SlNetSock_setOpt(int16_t sd, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); - - -/*! - \brief Get socket options - - The SlNetSock_getOpt function gets the options associated with a socket. - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level. - - The parameters optval and optlen identify a - buffer in which the value for the requested option(s) are to - be returned. \c optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, \c optval may be \c NULL. - - - \param[in] sd Socket descriptor (handle) - \param[in] level Defines the protocol level for this option - \param[in] optname defines the option name to interrogate - \param[out] optval Specifies a value for the option - \param[out] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \sa SlNetSock_setOpt() -*/ -int32_t SlNetSock_getOpt(int16_t sd, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); - - -/*! - \brief Read data from TCP socket - - The SlNetSock_recv function receives a message from a connection-mode socket - - \param[in] sd Socket descriptor (handle) - \param[out] buf Points to the buffer where the - message should be stored. - \param[in] len Specifies the length in bytes of - the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Specifies the type of message - reception. On this version, this parameter is not - supported. - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SLNETERR_BSD_EAGAIN.\n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - - \slnetsock_init_precondition - - \par Examples - - - Receiving data using TCP socket: - \code - SlNetSock_AddrIn_t Addr; - SlNetSock_AddrIn_t LocalAddr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID, newSockID; - int16_t Status; - int8_t Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_port = SlNetSock_htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); - Status = SlNetSock_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); - Status = SlNetSock_listen(SockID, 0); - newSockID = SlNetSock_accept(SockID, (SlNetSock_Addr_t *)&Addr, (SlNetSocklen_t *)&AddrSize); - Status = SlNetSock_recv(newSockID, Buf, 1460, 0); - \endcode -
- - - Rx transceiver mode using a raw socket: - \code - int8_t buffer[1536]; - int16_t sd; - uint16_t size; - SlNetSock_TransceiverRxOverHead_t *transHeader; - sd = SlNetSock_create(SLNETSOCK_AF_RF, SLNETSOCK_SOCK_RAW, 11, 0, 0); // channel 11 - while(1) - { - size = SlNetSock_recv(sd,buffer,1536,0); - transHeader = (SlNetSock_TransceiverRxOverHead_t *)buffer; - printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlNetSock_TransceiverRxOverHead_t)],size); - } - \endcode - - \sa SlNetSock_create() - \sa SlNetSock_recvFrom() -*/ -int32_t SlNetSock_recv(int16_t sd, void *buf, uint32_t len, uint32_t flags); - - -/*! - \brief Read data from socket - - SlNetSock_recvFrom function receives a message from a connection-mode or - connectionless-mode socket - - \param[in] sd Socket descriptor (handle) - \param[out] buf Points to the buffer where the message should be stored. - \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Specifies the type of message - reception. On this version, this parameter is not - supported - \param[in] from Pointer to an address structure - indicating the source - address.\n sockaddr:\n - code - for the address format.\n - socket address, - the length depends on the code - format - \param[in] fromlen Source address structure - size. This parameter MUST be set to the size of the structure pointed to by addr. - - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is #SLNETERR_BSD_EAGAIN. - #SLNETERR_RET_CODE_INVALID_INPUT will be returned if fromlen has incorrect length.\n - #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - - \slnetsock_init_precondition - - \par Example - - - Receiving data: - \code - SlNetSock_AddrIn_t Addr; - SlNetSock_AddrIn_t LocalAddr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_port = SlNetSock_htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - SockID = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); - Status = SlNetSock_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); - Status = SlNetSock_recvFrom(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, (SlNetSocklen_t*)&AddrSize); - - \endcode - - \sa SlNetSock_create() - \sa SlNetSock_recv() -*/ -int32_t SlNetSock_recvFrom(int16_t sd, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); - - -/*! - \brief Write data to TCP socket - - Transmits a message to another socket. - Returns immediately after sending data to device. - In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the - frame data buffer for WLAN FCS - - \param[in] sd Socket descriptor (handle) - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len Message size in bytes. - \param[in] flags Specifies the type of message - transmission. On this version, this parameter is not - supported for TCP. - - \return Return the number of bytes sent, - or a negative value if an error occurred. - - \slnetsock_init_precondition - - \par Example - - - Sending data: - \code - SlNetSock_AddrIn_t Addr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[SEND_BUF_LEN]; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); - Status = SlNetSock_connect(SockID, (SlNetSock_Addr_t *)&Addr, AddrSize); - Status = SlNetSock_send(SockID, Buf, 1460, 0 ); - \endcode - - \sa SlNetSock_create() - \sa SlNetSock_sendTo() -*/ -int32_t SlNetSock_send(int16_t sd, const void *buf, uint32_t len, uint32_t flags); - - -/*! - \brief Write data to socket - - The SlNetSock_sendTo function is used to transmit a message on a connectionless socket - (connection less socket #SLNETSOCK_SOCK_DGRAM, #SLNETSOCK_SOCK_RAW). - - Returns immediately after sending data to device. - - \param[in] sd Socket descriptor (handle) - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len message size in bytes. - \param[in] flags Specifies the type of message - transmission. On this version, this parameter is not - supported - \param[in] to Pointer to an address structure - indicating the destination - address.\n sockaddr:\n - code - for the address format.\n - socket address, - the length depends on the code - format - \param[in] tolen Destination address structure size - - \return Return the number of bytes sent, - or a negative value if an error occurred.\n - - \slnetsock_init_precondition - - \par Example - - - Sending data: - \code - SlNetSock_AddrIn_t Addr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[SEND_BUF_LEN]; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); - Status = SlNetSock_sendTo(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, AddrSize); - \endcode - - \sa SlNetSock_create() - \sa SlNetSock_send() -*/ -int32_t SlNetSock_sendTo(int16_t sd, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); - - -/*! - \brief Get interface ID from socket descriptor (sd) - - Retrieves the priority of the requested interface. - - \param[in] sd Specifies the socket descriptor which its - interface identifier needs to be retrieved.\n - - \return The interface identifier value of the - interface on success, or negative error code - on failure The values of the interface - identifier is defined with the prefix - SLNETIF_ID_ which defined in slnetif.h - - \slnetsock_init_precondition - - \par Examples - - \code - int16_t InterfaceID; - InterfaceID = SlNetSock_getIfID(SLNETIF_ID_1); - \endcode - - \sa SlNetSock_create() - \sa SlNetIf_add() - \sa SlNetIf_getIDByName() -*/ -int32_t SlNetSock_getIfID(uint16_t sd); - - -/*! - \brief Creates a security attributes object - - Create a security attribute, which is required in order to start a secure session. - - \remark When the security attributes object is no longer needed, call - SlNetSock_secAttribDelete() to destroy it. - - \remark A single security object can be used to initiate several secure - sessions (provided they all have the same security attributes). - - \slnetsock_init_precondition - - \sa SlNetSock_startSec() - \sa SlNetSock_secAttribDelete() -*/ -SlNetSockSecAttrib_t *SlNetSock_secAttribCreate(void); - - -/*! - \brief Deletes a security attributes object - - \param[in] secAttrib Secure attribute handle - - \return Zero on success, or negative error code - on failure - - \slnetsock_init_precondition - - \remark \c secAttrib must be created using SlNetSock_secAttribCreate() - - \sa SlNetSock_secAttribCreate() - \sa SlNetSock_secAttribSet() - \sa SlNetSock_startSec() -*/ -int32_t SlNetSock_secAttribDelete(SlNetSockSecAttrib_t *secAttrib); - - -/*! - \brief set a security attribute - - The SlNetSock_secAttribSet function is used to set a security - attribute of a security attribute object. - - \param[in] secAttrib Secure attribute handle - \param[in] attribName Define the actual attribute to set. Applicable values: - - #SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY \n - Sets the private key corresponding to the local certificate \n - This attribute takes the name of security object containing the private key and the name's length (including the NULL terminating character) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_LOCAL_CERT \n - Sets the local certificate chain \n - This attribute takes the name of the security object containing the certificate and the name's length (including the NULL terminating character) as parameters \n - For certificate chains, each certificate in the chain can be added via a separate call to SlNetSock_secAttribSet, starting with the root certificate of the chain \n - - #SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA \n - Sets the root CA certificate \n - This attribute takes the name of the security object containing the certificate and the name's length (including the NULL terminating character) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_DH_KEY \n - Sets the DH Key \n - This attribute takes the name of the security object containing the DH Key and the name's length (including the NULL terminating character) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_METHOD \n - Sets the TLS protocol version \n - This attribute takes a SLNETSOCK_SEC_METHOD_* option and sizeof(uint8_t) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_CIPHERS \n - Sets the ciphersuites to be used for the connection \n - This attribute takes a bit mask formed using SLNETSOCK_SEC_CIPHER_* options and sizeof(uint32_t) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_ALPN \n - Sets the ALPN \n - This attribute takes a bit mask formed using SLNETSOCK_SEC_ALPN_* options and sizeof(uint32_t) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_EXT_CLIENT_CHLNG_RESP \n - Sets the EXT CLIENT CHLNG RESP \n - Format TBD \n - - #SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME \n - Sets the domain name for verification during connection \n - This attribute takes a string with the domain name and the string's length (including the NULL-terminating character) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE\n - Sets whether to disable the certificate store \n - This attribute takes 1 (disable) or 0 (enable) and sizeof(uint32_t) as parameters \n - - \param[in] val - \param[in] len - - \return Zero on success, or negative error code - on failure - - \slnetsock_init_precondition - - \note Once an attribute is set, it cannot be unset or set to something - different. Doing so may result in undefined behavior. - Instead, SlNetSock_secAttribDelete() should be called on the - existing object, and a new security object should be created with - the new attribute set. - - \note The @c SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE value - is currently being evaluated, and may be removed in a - future release. It is currently only supported on CC3x20 - devices. For more details, see - #SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE. - - \par Examples - - - SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY: - \code - #define PRIVATE_KEY_FILE "DummyKey" - SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY, PRIVATE_KEY_FILE, strlen(PRIVATE_KEY_FILE), srvKeyPem, srvKeyPemLen, SLNETIF_ID_2); - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY, PRIVATE_KEY_FILE, sizeof(PRIVATE_KEY_FILE)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_LOCAL_CERT: - \code - #define ROOT_CA_CERT_FILE "DummyCA" - #define TRUSTED_CERT_FILE "DummyTrustedCert" - - // create a local certificate chain - SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, ROOT_CA_CERT_FILE, strlen(ROOT_CA_CERT_FILE), srvCAPem, srvCAPemLen, SLNETIF_ID_2); - SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, TRUSTED_CERT_FILE, strlen(TRUSTED_CERT_FILE), srvCertPem, srvCertPemLen, SLNETIF_ID_2); - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_LOCAL_CERT, ROOT_CA_CERT_FILE, sizeof(ROOT_CA_CERT_FILE)); - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_LOCAL_CERT, TRUSTED_CERT_FILE, sizeof(TRUSTED_CERT_FILE)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA: - \code - #define ROOT_CA_CERT_FILE "DummyCA" - SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, ROOT_CA_CERT_FILE, strlen(ROOT_CA_CERT_FILE), srvCAPem, srvCAPemLen, SLNETIF_ID_2); - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA, ROOT_CA_CERT_FILE, sizeof(ROOT_CA_CERT_FILE)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_METHOD: - \code - uint8_t SecurityMethod = SLNETSOCK_SEC_METHOD_SSLV3; - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_METHOD, (void *)&(SecurityMethod), sizeof(SecurityMethod)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_CIPHERS: - \code - uint32_t SecurityCipher = SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_SHA | SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA; - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_METHOD, (void *)&(SecurityCipher), sizeof(SecurityCipher)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME: - \code - char addr[] = "www.ti.com"; - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME, (void *)addr, strlen(addr) + 1); - \endcode -
- - - \sa SlNetSock_secAttribCreate() -*/ -int32_t SlNetSock_secAttribSet(SlNetSockSecAttrib_t *secAttrib, SlNetSockSecAttrib_e attribName, void *val, uint16_t len); - - -/*! - \brief Start a security session on an opened socket - - \param[in] sd Socket descriptor (handle) - \param[in] secAttrib Secure attribute handle. This can be NULL only - if the SLNETSOCK_SEC_BIND_CONTEXT_ONLY flag is - not thrown. - \param[in] flags Specifies flags. \n - The available flags are: - - #SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY - - #SLNETSOCK_SEC_BIND_CONTEXT_ONLY - - #SLNETSOCK_SEC_IS_SERVER - - \return Zero on success, or negative error code - on failure - - \slnetsock_init_precondition - - \remark If \c secAttrib is \c NULL, the session will be started with - default security settings. - - \sa SlNetSock_create() - \sa SlNetSock_secAttribCreate() -*/ -int32_t SlNetSock_startSec(int16_t sd, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); - - -/*! - - Close the Doxygen group. - @} - -*/ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NET_SOCK_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetutils.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetutils.h deleted file mode 100755 index 51eb8d1e04f..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetutils.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#ifndef __SL_NET_UTILS_H__ -#define __SL_NET_UTILS_H__ - -#include "slnetsock.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup SlNetUtils SlNetUtils group - - \short Sockets related commands and configuration - -*/ -/*! - - \addtogroup SlNetUtils - @{ - -*/ - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/* Creating one address parameter from 4 separate address parameters */ -#define SLNETUTIL_IPV4_VAL(add_3,add_2,add_1,add_0) ((((uint32_t)add_3 << 24) & 0xFF000000) | (((uint32_t)add_2 << 16) & 0xFF0000) | (((uint32_t)add_1 << 8) & 0xFF00) | ((uint32_t)add_0 & 0xFF) ) - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Initialize the SlNetUtil module - - \param[in] flags Reserved - - \return Zero on success, or negative error code on failure -*/ -int32_t SlNetUtil_init(int32_t flags); - -/*! - \brief Get host IP by name\n - Obtain the IP Address of machine on network, by machine name. - - \param[in] ifBitmap Specifies the interfaces which the the host ip - needs to be retrieved from according tothe - priority until one of them will return an answer.\n - Value 0 is used in order to choose automatic - interfaces selection according to the priority - interface list. - Value can be combination of interfaces by OR'ing - multiple interfaces bit identifiers (SLNETIFC_IDENT_ - defined in slnetif.h) - Note: interface identifier bit must be configured - prior to this socket creation using SlNetIf_add(). - \param[in] name Host name - \param[in] nameLen Name length - \param[out] ipAddr This parameter is filled in with an array of - IP addresses. In case that host name is not - resolved, ipAddrLen is zero. - \param[in,out] ipAddrLen Holds the size of the ipAddr array, when function - successful, the ipAddrLen parameter will be updated with - the number of the IP addresses found. - \param[in] family Protocol family - - \return The interface ID of the interface which run - successfully the function, or negative on failure.\n - #SLNETERR_POOL_IS_EMPTY may be return in case - there are no resources in the system\n - Possible DNS error codes: - - #SLNETERR_NET_APP_DNS_QUERY_NO_RESPONSE - - #SLNETERR_NET_APP_DNS_NO_SERVER - - #SLNETERR_NET_APP_DNS_QUERY_FAILED - - #SLNETERR_NET_APP_DNS_MALFORMED_PACKET - - #SLNETERR_NET_APP_DNS_MISMATCHED_RESPONSE - - \slnetutil_init_precondition - - \warning - In case an IP address in a string format is set as input, without - any prefix (e.g. "1.2.3.4") the device will not try to access the - DNS and it will return the input address in the \c ipAddr field - \par Example - - Getting IPv4 using get host by name: - \code - uint16_t DestIPListSize = 1; - uint32_t DestIP[1]; - uint32_t ifID; - int16_t SockId; - SlNetSock_AddrIn_t LocalAddr; //address of the server to connect to - int32_t LocalAddrSize; - - ifID = SlNetUtil_getHostByName(0, "www.google.com", strlen("www.google.com"), DestIP, &DestIPListSize, SLNETSOCK_PF_INET); - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_addr.s_addr = SlNetUtil_htonl(DestIP[0]); - LocalAddr.sin_port = SlNetUtil_htons(80); - LocalAddrSize = sizeof(SlNetSock_AddrIn_t); - - SockId = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, ifID, 0); - - if (SockId >= 0) - { - status = SlNetSock_connect(SockId, (SlNetSock_Addr_t *)&LocalAddr, LocalAddrSize); - } - \endcode -*/ -int32_t SlNetUtil_getHostByName(uint32_t ifBitmap, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); - - -/*! - \brief Reorder the bytes of a 32-bit unsigned value - - This function is used to reorder the bytes of a 32-bit unsigned value - from host order to network order. - - \param[in] val Variable in host order - - \return Return the variable in network order - - \slnetutil_init_precondition - - \sa SlNetSock_bind() - \sa SlNetSock_connect() - \sa SlNetSock_recvFrom() - \sa SlNetSock_accept() -*/ -uint32_t SlNetUtil_htonl(uint32_t val); - - -/*! - \brief Reorder the bytes of a 32-bit unsigned value - - This function is used to reorder the bytes of a 32-bit unsigned - value from network order to host order. - - \param[in] val Variable in network order - - \return Return the variable in host order - - \slnetutil_init_precondition - - \sa SlNetSock_bind() - \sa SlNetSock_connect() - \sa SlNetSock_recvFrom() - \sa SlNetSock_accept() -*/ -uint32_t SlNetUtil_ntohl(uint32_t val); - - -/*! - \brief Reorder the bytes of a 16-bit unsigned value - - This functions is used to reorder the bytes of a 16-bit unsigned - value from host order to network order. - - \param[in] val Variable in host order - - \return Return the variable in network order - - \slnetutil_init_precondition - - \sa SlNetSock_bind() - \sa SlNetSock_connect() - \sa SlNetSock_recvFrom() - \sa SlNetSock_accept() -*/ -uint16_t SlNetUtil_htons(uint16_t val); - - -/*! - \brief Reorder the bytes of a 16-bit unsigned value - - This functions is used to reorder the bytes of a 16-bit unsigned value - from network order to host order. - - \param[in] val Variable in network order - - \return Return the variable in host order - - \slnetutil_init_precondition - - \sa SlNetSock_bind() - \sa SlNetSock_connect() - \sa SlNetSock_recvFrom() - \sa SlNetSock_accept() -*/ -uint16_t SlNetUtil_ntohs(uint16_t val); - - -/*! - \brief Converts IP address in binary representation to string representation - - This functions is used to converts IP address in binary representation - to IP address in string representation. - - \param[in] addrFamily Specifies the address family of the created - socket - For example: - - #SLNETSOCK_AF_INET for network address IPv4 - - #SLNETSOCK_AF_INET6 for network address IPv6 - \param[in] binaryAddr Pointer to an IP address structure indicating the - address in binary representation - \param[out] strAddr Pointer to the address string representation - for IPv4 or IPv6 according to the address - family - \param[in] strAddrLen Specifies the length of the StrAddress_dst, - the maximum length of the address in string - representation for IPv4 or IPv6 according to - the address family - - \return strAddr on success, or NULL on failure - - \slnetutil_init_precondition - - \par Example - - IPv4 demo of inet_ntop() - \code - SlNetSock_AddrIn_t sa; - char str[SLNETSOCK_INET_ADDRSTRLEN]; - - // store this IP address in sa: - SlNetUtil_inetPton(SLNETSOCK_AF_INET, "192.0.2.33", &(sa.sin_addr)); - // now get it back and print it - SlNetUtil_inetNtop(SLNETSOCK_AF_INET, &(sa.sin_addr), str, SLNETSOCK_INET_ADDRSTRLEN); - \endcode -*/ -const char *SlNetUtil_inetNtop(int16_t addrFamily, const void *binaryAddr, char *strAddr, SlNetSocklen_t strAddrLen); - - -/*! - \brief Converts IP address in string representation to binary representation - - This functions is used to converts IP address in string representation - to IP address in binary representation. - - \param[in] addrFamily Specifies the address family of the created - socket - For example: - - #SLNETSOCK_AF_INET for network address IPv4 - - #SLNETSOCK_AF_INET6 for network address IPv6 - \param[out] strAddr Specifies the IP address in string representation - for IPv4 or IPv6 according to the address - family - \param[in] binaryAddr Pointer to an address structure that will be - filled by the IP address in Binary representation - - \return 1 on success, -1 on failure, or 0 if the input - isn't a valid IP address - - \slnetutil_init_precondition - - \par Example - - IPv6 demo of inet_pton() - \code - SlNetSock_AddrIn6_t sa; - - // store this IP address in sa: - SlNetUtil_inetPton(SLNETSOCK_AF_INET6, "0:0:0:0:0:0:0:0", &(sa.sin6_addr)); - \endcode -*/ -int32_t SlNetUtil_inetPton(int16_t addrFamily, const char *strAddr, void *binaryAddr); - -/*! - - Close the Doxygen group. - @} - -*/ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SL_NET_UTILS_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c deleted file mode 100644 index f8456db5400..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Hardware entropy collector for the CC3200 - * - * Copyright (C) 2018-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* - * Reference: section 15.1.1.6 True Random Number in swru455e - */ - -#if defined(DEVICE_TRNG) - -#include "stdio.h" -#include "trng_api.h" -#include "ti/drivers/net/wifi/netutil.h" -#include "CC3220SF_Init.h" - -void trng_init(trng_t *obj) -{ - static bool trng_initialized = false; - - (void)obj; - if (!trng_initialized) { - int ret = CC3220SF_initSimplelink(); - if (ret == 0) { - trng_initialized = true; - } else { - printf("trng_init failed with %d\n", ret); - } - } -} - -void trng_free(trng_t *obj) -{ - (void)obj; -} - - -int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) -{ - _u16 bytes_count = length; - _i16 status; - - (void)obj; - /* Retrieve a buffer of true random numbers from the networking subsystem. - Maximum buffer length is 172 bytes for each retrieval. if the requested length exceeds 172 bytes, it is trimmed to 172 bytes.*/ - if (length > 172) { - bytes_count = 172; - } - if (output) { - status = sl_NetUtilGet(SL_NETUTIL_TRUE_RANDOM, 0, output, &bytes_count); - if (output_length) { - if (status == 0) { - *output_length = bytes_count; - return 0; - } else { - printf("sl_NetUtilGet failed with %d\n", status); - *output_length = 0; - } - } - } - return -1; -} - -#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c deleted file mode 100644 index a2603e8ee24..00000000000 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c +++ /dev/null @@ -1,95 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "stdlib.h" -#include "us_ticker_api.h" -#include "ti/devices/cc32xx/inc/hw_types.h" -#include "ti/devices/cc32xx/inc/hw_memmap.h" -#include "ti/devices/cc32xx/driverlib/ti_timer.h" - -/* There're 4 timers running from system clock (80MHz). Configure split 16b TimerA timer counting down. We'll post process it to make it appear count up. - * When the timer is configured in periodic down count mode, GPTMTAPR register acts as a true prescaler. A scaler of 80 yields 1MHz timer. - */ -#define US_TICKER_COUNTER_BITS 16u -#define US_TICKER_FREQ 1000000 - -bool us_ticker_initialized = false; - -const ticker_info_t *us_ticker_get_info() -{ - static const ticker_info_t info = { - US_TICKER_FREQ, - US_TICKER_COUNTER_BITS - }; - return &info; -} -void us_ticker_init(void) -{ - if (!us_ticker_initialized) { - TimerDisable(TIMERA0_BASE, TIMER_A); - TimerConfigure(TIMERA0_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC); - TimerIntClear(TIMERA0_BASE, TIMER_TIMA_DMA | TIMER_TIMA_MATCH | TIMER_CAPA_EVENT | - TIMER_CAPA_MATCH | TIMER_TIMA_TIMEOUT); - TimerPrescaleSet(TIMERA0_BASE, TIMER_A, (80 - 1)); - TimerEnable(TIMERA0_BASE, TIMER_A); - NVIC_ClearPendingIRQ(INT_TIMERA0A_IRQn); - NVIC_SetVector(INT_TIMERA0A_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(INT_TIMERA0A_IRQn); - us_ticker_initialized = true; - } else { - // Disable match interrupt. This is mbed OS requirement. - TimerIntDisable(TIMERA0_BASE, TIMER_TIMA_MATCH); - // Clear pending interrupt - TimerIntClear(TIMERA0_BASE, TIMER_TIMA_MATCH | TIMER_TIMA_TIMEOUT); - } -} - -uint32_t us_ticker_read(void) -{ - return (0xFFFF & ~TimerValueGet(TIMERA0_BASE, TIMER_A)); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Clear pending interrupt - TimerIntClear(TIMERA0_BASE, TIMER_TIMA_MATCH); - TimerMatchSet(TIMERA0_BASE, TIMER_A, 0xFFFF & (~(timestamp & 0xFFFF))); - TimerIntEnable(TIMERA0_BASE, TIMER_TIMA_MATCH); -} - -void us_ticker_disable_interrupt(void) -{ - TimerIntDisable(TIMERA0_BASE, TIMER_TIMA_MATCH); -} - -void us_ticker_clear_interrupt(void) -{ - TimerIntClear(TIMERA0_BASE, TIMER_TIMA_MATCH | TIMER_TIMA_TIMEOUT); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(INT_TIMERA0A_IRQn); -} - -void us_ticker_free(void) -{ - if (us_ticker_initialized) { - TimerDisable(TIMERA0_BASE, TIMER_A); - NVIC_DisableIRQ(INT_TIMERA0A_IRQn); - us_ticker_initialized = false; - } -} diff --git a/targets/TARGET_TI/TARGET_MSP432/PeripheralNames.h b/targets/TARGET_TI/TARGET_MSP432/PeripheralNames.h deleted file mode 100644 index d3d818f16da..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/PeripheralNames.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -/* mbed-os internally uses integer values - * for peripheral names. Instead of defining - * enums with new names, we simply reuse the - * macros for the base addresses of the - * peripheral units, which are defined in - * msp.h and are self-explanatory (see - * PeripheralPins.c). - * So the name types are simply typedefs - * to integers... - */ - -#define DEVICE_SPI_COUNT 8 - -typedef uint32_t ADCName; -typedef uint32_t UARTName; -typedef uint32_t I2CName; -typedef uint32_t SPIName; -typedef uint32_t PWMName; - -#endif diff --git a/targets/TARGET_TI/TARGET_MSP432/PeripheralPins.c b/targets/TARGET_TI/TARGET_MSP432/PeripheralPins.c deleted file mode 100644 index 830133a32cd..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/PeripheralPins.c +++ /dev/null @@ -1,163 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" -#include "PeripheralNames.h" -#include "cmsis.h" - -const PinMap PinMap_empty[] = { - { NC, NC, 0 } -}; - -/*** ADC ***/ -const PinMap PinMap_ADC[] = { - { P5_5, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 0) }, - { P5_4, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 1) }, - { P5_3, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 2) }, - { P5_2, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 3) }, - { P5_1, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 4) }, - { P5_0, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 5) }, - { P4_7, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 6) }, - { P4_6, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 7) }, - { P4_5, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 8) }, - { P4_4, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 9) }, - { P4_3, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 10) }, - { P4_2, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 11) }, - { P4_1, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 12) }, - { P4_0, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 13) }, - { P6_1, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 14) }, - { P6_0, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 15) }, - { P9_1, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 16) }, - { P9_0, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 17) }, - { P8_7, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 18) }, - { P8_6, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 19) }, - { P8_5, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 20) }, - { P8_4, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 21) }, - { P8_3, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 22) }, - { P8_2, ADC14_BASE, MSP432_PIN_DATA(SEL3, PIN_INPUT, PullNone, 23) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_ADC_Internal[] = { - { NC, NC, 0 } -}; - -//*** I2C *** -const PinMap PinMap_I2C_SDA[] = { - { P1_6, EUSCI_B0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { P6_4, EUSCI_B1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { P3_6, EUSCI_B2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { P6_6, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL2, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { P10_2, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_I2C_SCL[] = { - { P1_7, EUSCI_B0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { P6_5, EUSCI_B1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { P3_7, EUSCI_B2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { P6_7, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL2, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { P10_3, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, OpenDrainPullUp, 0) }, - { NC, NC, 0 } -}; - -//*** SERIAL *** -const PinMap PinMap_UART_TX[] = { - { P1_3, EUSCI_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 0) }, - { P2_3, EUSCI_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 0) }, - { P3_3, EUSCI_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 0) }, - { P9_7, EUSCI_A3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 0) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_UART_RX[] = { - { P1_2, EUSCI_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 0) }, - { P2_2, EUSCI_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 0) }, - { P3_2, EUSCI_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 0) }, - { P9_6, EUSCI_A3_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 0) }, - { NC, NC, 0 } -}; - -//*** SPI *** -const PinMap PinMap_SPI_MOSI[] = { - { P1_3, EUSCI_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 0) }, - { P2_3, EUSCI_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 1) }, - { P3_3, EUSCI_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 2) }, - { P9_7, EUSCI_A3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 3) }, - { P1_6, EUSCI_B0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 4) }, - { P6_4, EUSCI_B1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 5) }, - { P3_6, EUSCI_B2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 6) }, - { P6_6, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL2, PIN_OUTPUT, PullNone, 7) }, - { P10_2, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 7) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_SPI_MISO[] = { - { P1_2, EUSCI_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 0) }, - { P2_2, EUSCI_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 1) }, - { P3_2, EUSCI_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 2) }, - { P9_6, EUSCI_A3_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 3) }, - { P1_7, EUSCI_B0_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 4) }, - { P6_5, EUSCI_B1_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 5) }, - { P3_7, EUSCI_B2_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 6) }, - { P6_7, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL2, PIN_INPUT, PullNone, 7) }, - { P10_3, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL1, PIN_INPUT, PullNone, 7) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_SPI_SCLK[] = { - { P1_1, EUSCI_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 0) }, - { P2_1, EUSCI_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 1) }, - { P3_1, EUSCI_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 2) }, - { P9_5, EUSCI_A3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 3) }, - { P1_5, EUSCI_B0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 4) }, - { P6_3, EUSCI_B1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 5) }, - { P3_5, EUSCI_B2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 6) }, - { P8_1, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 7) }, - { P10_1, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 7) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_SPI_SSEL[] = { - { P1_0, EUSCI_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 0) }, - { P2_0, EUSCI_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 1) }, - { P3_0, EUSCI_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 2) }, - { P9_4, EUSCI_A3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 3) }, - { P1_4, EUSCI_B0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 4) }, - { P6_2, EUSCI_B1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 5) }, - { P3_4, EUSCI_B2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 6) }, - { P8_0, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 7) }, - { P10_0, EUSCI_B3_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 7) }, - { NC, NC, 0 } -}; - -const PinMap PinMap_PWM[] = { - { P2_4, TIMER_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 1) }, - { P2_5, TIMER_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 2) }, - { P2_6, TIMER_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 3) }, - { P2_7, TIMER_A0_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 4) }, - { P7_7, TIMER_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 1) }, - { P7_6, TIMER_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 2) }, - { P7_5, TIMER_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 3) }, - { P7_4, TIMER_A1_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 4) }, - { P5_6, TIMER_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 1) }, - { P5_7, TIMER_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 2) }, - { P6_6, TIMER_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 3) }, - { P6_7, TIMER_A2_BASE, MSP432_PIN_DATA(SEL1, PIN_OUTPUT, PullNone, 4) }, - { NC, NC, 0 } -}; - diff --git a/targets/TARGET_TI/TARGET_MSP432/PeripheralPins.h b/targets/TARGET_TI/TARGET_MSP432/PeripheralPins.h deleted file mode 100644 index b7fcdb3c2c9..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/PeripheralPins.h +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" - -typedef enum { - SEL0 = 0, - SEL1 = 1, - SEL2 = 2, - SEL3 = 3 -} pin_sel_t; - -#define MSP432_PIN_DATA(sel, dir, mode, channel) (sel | (dir << 8) | (mode << 16) | (channel << 24)) - -#define GET_DATA_SEL(data) ( data & 0xff) -#define GET_DATA_DIR(data) ((data >> 8) & 0xff) -#define GET_DATA_MODE(data) ((data >> 16) & 0xff) -#define GET_DATA_CHAN(data) ((data >> 24) & 0xff) - -extern const PinMap PinMap_empty[]; - -//*** ADC *** -#if DEVICE_ANALOGIN -extern const PinMap PinMap_ADC[]; -extern const PinMap PinMap_ADC_Internal[]; -#endif - -//*** I2C *** -#if DEVICE_I2C -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; -#endif - -//*** PWM *** -#if DEVICE_PWMOUT -extern const PinMap PinMap_PWM[]; -#endif - -//*** SERIAL *** -#if DEVICE_SERIAL -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -#endif - -//*** SPI *** -#if DEVICE_SPI -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_MSP432/PinNames.h b/targets/TARGET_TI/TARGET_MSP432/PinNames.h deleted file mode 100644 index 15c4882e8ce..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/PinNames.h +++ /dev/null @@ -1,152 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Macros to extract port/pin index from the PinName - * MSP432_PORT returns values 0...9, corresponing to P1...P10 - * MSP432_PIN returns values 0...7, corresponing to pin index - */ -#define MSP432_PORT_IDX(pin) (((uint32_t)pin & 0xF0) >> 4) -#define MSP432_PIN_IDX(pin) ((uint32_t)pin & 0x0F) - -/* - * The following defines are used by user applications. - * Since PinDirection and PinMode are not part of the - * mbed-os interface for GPIOs, care must be taken that - * the standard names (e.g. PIN_INPUT) are used so that - * cross-platform compatibility of source code is kept! - */ - -typedef enum { - PIN_INPUT = 0, - PIN_OUTPUT = 1 -} PinDirection; - -typedef enum { - PullNone, - PullUp, - PullDown, - OpenDrain, - OpenDrainPullUp, - OpenSource, - OpenSourcePullDown, - // Alias names - PullDefault = PullNone, - OpenDrainNoPull = OpenDrain, - OpenSourceNoPull = OpenSource -} PinMode; - -typedef enum { - P1_0 = 0x00, - P1_1 = 0x01, - P1_2 = 0x02, - P1_3 = 0x03, - P1_4 = 0x04, - P1_5 = 0x05, - P1_6 = 0x06, - P1_7 = 0x07, - P2_0 = 0x10, - P2_1 = 0x11, - P2_2 = 0x12, - P2_3 = 0x13, - P2_4 = 0x14, - P2_5 = 0x15, - P2_6 = 0x16, - P2_7 = 0x17, - P3_0 = 0x20, - P3_1 = 0x21, - P3_2 = 0x22, - P3_3 = 0x23, - P3_4 = 0x24, - P3_5 = 0x25, - P3_6 = 0x26, - P3_7 = 0x27, - P4_0 = 0x30, - P4_1 = 0x31, - P4_2 = 0x32, - P4_3 = 0x33, - P4_4 = 0x34, - P4_5 = 0x35, - P4_6 = 0x36, - P4_7 = 0x37, - P5_0 = 0x40, - P5_1 = 0x41, - P5_2 = 0x42, - P5_3 = 0x43, - P5_4 = 0x44, - P5_5 = 0x45, - P5_6 = 0x46, - P5_7 = 0x47, - P6_0 = 0x50, - P6_1 = 0x51, - P6_2 = 0x52, - P6_3 = 0x53, - P6_4 = 0x54, - P6_5 = 0x55, - P6_6 = 0x56, - P6_7 = 0x57, - P7_0 = 0x60, - P7_1 = 0x61, - P7_2 = 0x62, - P7_3 = 0x63, - P7_4 = 0x64, - P7_5 = 0x65, - P7_6 = 0x66, - P7_7 = 0x67, - P8_0 = 0x70, - P8_1 = 0x71, - P8_2 = 0x72, - P8_3 = 0x73, - P8_4 = 0x74, - P8_5 = 0x75, - P8_6 = 0x76, - P8_7 = 0x77, - P9_0 = 0x80, - P9_1 = 0x81, - P9_2 = 0x82, - P9_3 = 0x83, - P9_4 = 0x84, - P9_5 = 0x85, - P9_6 = 0x86, - P9_7 = 0x87, - P10_0 = 0x90, - P10_1 = 0x91, - P10_2 = 0x92, - P10_3 = 0x93, - P10_4 = 0x94, - P10_5 = 0x95, - - // Not connected - NC = (int)0xFFFFFFFF, - -#include "BoardPinNames.h" - -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_MSP432/PortNames.h b/targets/TARGET_TI/TARGET_MSP432/PortNames.h deleted file mode 100644 index a4c4b32d860..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/PortNames.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port1 = 0, - Port2 = 1, - Port3 = 2, - Port4 = 3, - Port5 = 4, - Port6 = 5, - Port7 = 6, - Port8 = 7, - Port9 = 8, - Port10 = 9, -} PortName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/TARGET_MSP432_LAUNCHPAD/BoardPinNames.h b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/TARGET_MSP432_LAUNCHPAD/BoardPinNames.h deleted file mode 100644 index 56519967e4e..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/TARGET_MSP432_LAUNCHPAD/BoardPinNames.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* This file will be included in PinNames.h (inside the PinName enum) - * - * It defines the names of the board-specific components, like - * - LEDs - * - Buttons - * - UARTS connected via e.g. USB - */ - -// mbed standard names for UARTs -STDIO_UART_TX = P1_3, -STDIO_UART_RX = P1_2, -USBTX = P1_3, -USBRX = P1_2, - -// mbed standard names for LEDs and Buttons -LED1 = P1_0, -LED2 = P2_0, -LED3 = P2_1, -LED4 = P2_2, -BUTTON1 = P1_1, -BUTTON2 = P1_4, - -// Alternative names for LEDs and Buttons -LED_RED = P1_0, -LED_RGB_RED = P2_0, -LED_RGB_GREEN = P2_1, -LED_RGB_BLUE = P2_2, -S1 = P1_1, -S2 = P1_4 diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_ARM_STD/msp432p401r.sct b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_ARM_STD/msp432p401r.sct deleted file mode 100644 index 8f6af05d627..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_ARM_STD/msp432p401r.sct +++ /dev/null @@ -1,40 +0,0 @@ -#! armcc -E - -/********************************************************** - * ARM CC linker script for Texas Instruments MSP432P401R - **********************************************************/ - -/* Device specific values */ - -#define ROM_START 0x00000000 -#define ROM_SIZE 0x00040000 -#define RAM_START 0x20000000 -#define RAM_SIZE 0x00010000 -#define STACK_SIZE 0x00000400 - -/* Common - Do not change */ - -#if !defined(MBED_APP_START) - #define MBED_APP_START ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE ROM_SIZE -#endif - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 RAM_START RAM_SIZE { - .ANY (+RW +ZI) - } - - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { - } - -} diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_GCC_ARM/msp432p401r.ld b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_GCC_ARM/msp432p401r.ld deleted file mode 100644 index 7b60b2e258a..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_GCC_ARM/msp432p401r.ld +++ /dev/null @@ -1,182 +0,0 @@ -/****************************************************** - * GCC linker script for Texas Instruments MSP432P401R - ******************************************************/ - -/* Device specific values */ - -#define ROM_START 0x00000000 -#define ROM_SIZE 0x00040000 -#define RAM_START 0x20000000 -#define RAM_SIZE 0x00010000 -#define INFO_START 0x00200000 -#define INFO_SIZE 0x00004000 - -/* Common - Do not change */ - -#if !defined(MBED_APP_START) - #define MBED_APP_START ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE ROM_SIZE -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -/* 0x1AC resevered for vectors; 8-byte aligned = 0x1B0 (0x1AC + 0x4)*/ -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Location counter can end up 2byte aligned with narrow Thumb code but - __etext is assumed by startup code to be the LMA of a section in RAM - which must be 4byte aligned */ - __etext = ALIGN (4); - __data_load__ = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_IAR/msp432p401r.icf b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_IAR/msp432p401r.icf deleted file mode 100644 index 3ccc6352bd8..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_IAR/msp432p401r.icf +++ /dev/null @@ -1,42 +0,0 @@ -/****************************************************** - * IAR linker script for Texas Instruments MSP432P401R - ******************************************************/ - -/* Device specific values */ - -define symbol ROM_START = 0x00000000; -define symbol ROM_SIZE = 0x00040000; -define symbol RAM_START = 0x20000000; -define symbol RAM_SIZE = 0x00010000; - -define symbol HEAP_SIZE = 0x8000; -define symbol ISR_STACK_SIZE = 0x400; - -/* Common - Do not change */ - -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = ROM_START; -} - -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = ROM_SIZE; -} - -define symbol RAM_REGION_START = RAM_START; -define symbol RAM_REGION_SIZE = RAM_SIZE; - -define memory mem with size = 4G; -define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; -define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; - -define block CSTACK with alignment = 8, size = ISR_STACK_SIZE { }; -define block HEAP with alignment = 8, size = HEAP_SIZE { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem: MBED_APP_START { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, block HEAP }; -place at end of RAM_region { block CSTACK }; diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp432p401r.h b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp432p401r.h deleted file mode 100644 index fa22ce497fb..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp432p401r.h +++ /dev/null @@ -1,6967 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P401R Register Definitions -* -* This file includes CMSIS compliant component and register definitions -* -* For legacy components the definitions that are compatible with MSP430 code, -* are included with msp432p401r_classic.h -* -* With CMSIS definitions, the register defines have been reformatted: -* ModuleName[ModuleInstance]->RegisterName -* -* Writing to CMSIS bit fields can be done through register level -* or via bitband area access: -* - ADC14->CTL0 |= ADC14_CTL0_ENC; -* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; -* -* File creation date: 2017-12-06 -* -******************************************************************************/ - -#ifndef __MSP432P401R_H__ -#define __MSP432P401R_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#define __MSP432_HEADER_VERSION__ 3230 - -/* Remap MSP432 intrinsics to ARM equivalents */ -#include "msp_compatibility.h" - -/****************************************************************************** -* include MSP430 legacy definitions to make porting of code from MSP430 * -* code base easier * -* With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in * -* your project to omit including the classic defines * -******************************************************************************/ -#ifndef NO_MSP_CLASSIC_DEFINES -#include "msp432p401r_classic.h" -#endif - - -#ifndef __CMSIS_CONFIG__ -#define __CMSIS_CONFIG__ - -/** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions - This file defines all structures and symbols for MSP432P401R: - - components and registers - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ - -/****************************************************************************** -* Processor and Core Peripherals * -******************************************************************************/ -/** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M4 Processor and Core Peripherals - @{ -*/ - -/****************************************************************************** -* CMSIS-compatible Interrupt Number Definition * -******************************************************************************/ -typedef enum IRQn -{ - /* Cortex-M4 Processor Exceptions Numbers */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - /* Peripheral Exceptions Numbers */ - PSS_IRQn = 0, /* 16 PSS Interrupt */ - CS_IRQn = 1, /* 17 CS Interrupt */ - PCM_IRQn = 2, /* 18 PCM Interrupt */ - WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ - FPU_IRQn = 4, /* 20 FPU Interrupt */ - FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/ - COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ - COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ - TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ - TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ - TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ - TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ - TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ - TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ - TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ - TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ - EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ - EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ - EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ - EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ - EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ - EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ - EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ - EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ - ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ - T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ - T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ - T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ - AES256_IRQn = 28, /* 44 AES256 Interrupt */ - RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ - DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ - DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ - DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ - DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ - DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ - PORT1_IRQn = 35, /* 51 Port1 Interrupt */ - PORT2_IRQn = 36, /* 52 Port2 Interrupt */ - PORT3_IRQn = 37, /* 53 Port3 Interrupt */ - PORT4_IRQn = 38, /* 54 Port4 Interrupt */ - PORT5_IRQn = 39, /* 55 Port5 Interrupt */ - PORT6_IRQn = 40 /* 56 Port6 Interrupt */ -} IRQn_Type; - -/****************************************************************************** -* Processor and Core Peripheral Section * -******************************************************************************/ -#define __CM4_REV 0x0001 /* Core revision r0p1 */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /* FPU present or not */ - -/****************************************************************************** -* Available Peripherals * -******************************************************************************/ -#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ -#define __MCU_HAS_AES256__ /*!< Module AES256 is available */ -#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ -#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ -#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ -#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ -#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ -#define __MCU_HAS_CS__ /*!< Module CS is available */ -#define __MCU_HAS_DIO__ /*!< Module DIO is available */ -#define __MCU_HAS_DMA__ /*!< Module DMA is available */ -#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ -#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ -#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ -#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ -#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ -#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ -#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ -#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ -#define __MCU_HAS_FLCTL__ /*!< Module FLCTL is available */ -#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ -#define __MCU_HAS_PCM__ /*!< Module PCM is available */ -#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ -#define __MCU_HAS_PSS__ /*!< Module PSS is available */ -#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ -#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ -#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ -#define __MCU_HAS_SYSCTL__ /*!< Module SYSCTL is available */ -#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ -#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ -#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ -#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ -#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ -#define __MCU_HAS_TLV__ /*!< Module TLV is available */ -#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ - -/* Definitions to show that specific ports are available */ - -#define __MSP432_HAS_PORTA_R__ -#define __MSP432_HAS_PORTB_R__ -#define __MSP432_HAS_PORTC_R__ -#define __MSP432_HAS_PORTD_R__ -#define __MSP432_HAS_PORTE_R__ -#define __MSP432_HAS_PORTJ_R__ - -#define __MSP432_HAS_PORT1_R__ -#define __MSP432_HAS_PORT2_R__ -#define __MSP432_HAS_PORT3_R__ -#define __MSP432_HAS_PORT4_R__ -#define __MSP432_HAS_PORT5_R__ -#define __MSP432_HAS_PORT6_R__ -#define __MSP432_HAS_PORT7_R__ -#define __MSP432_HAS_PORT8_R__ -#define __MSP432_HAS_PORT9_R__ -#define __MSP432_HAS_PORT10_R__ - - -/*@}*/ /* end of group MSP432P401R_CMSIS */ - -/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ -#ifdef __TI_ARM__ -/* disable the TI ULP advisor check for the core header file definitions */ -#pragma diag_push -#pragma CHECK_ULP("none") -#include "core_cm4.h" -#pragma diag_pop -#else -#include "core_cm4.h" -#endif - -/* System Header */ -#include "system_msp432p401r.h" - -/****************************************************************************** -* Definition of standard bits * -******************************************************************************/ -#define BIT0 (uint16_t)(0x0001) -#define BIT1 (uint16_t)(0x0002) -#define BIT2 (uint16_t)(0x0004) -#define BIT3 (uint16_t)(0x0008) -#define BIT4 (uint16_t)(0x0010) -#define BIT5 (uint16_t)(0x0020) -#define BIT6 (uint16_t)(0x0040) -#define BIT7 (uint16_t)(0x0080) -#define BIT8 (uint16_t)(0x0100) -#define BIT9 (uint16_t)(0x0200) -#define BITA (uint16_t)(0x0400) -#define BITB (uint16_t)(0x0800) -#define BITC (uint16_t)(0x1000) -#define BITD (uint16_t)(0x2000) -#define BITE (uint16_t)(0x4000) -#define BITF (uint16_t)(0x8000) -#define BIT(x) ((uint16_t)1 << (x)) - -/****************************************************************************** -* Device and peripheral memory map * -******************************************************************************/ -/** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping - @{ -*/ - -#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ -#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ - -#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ -#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ -#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ -#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ -#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ -#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ -#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ -#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ -#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ -#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ -#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define FLCTL_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL registers */ -#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ -#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ -#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ -#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ -#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ -#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ -#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL registers */ -#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ -#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ -#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ -#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ -#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ -#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ -#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ - - -/*@}*/ /* end of group MSP432P401R_MemoryMap */ - -/****************************************************************************** -* Definitions for bit band access * -******************************************************************************/ -#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) -#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) - -/* SRAM allows 32 bit bit band access */ -#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(volatile const uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) -/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ -#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(volatile const uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) - -/****************************************************************************** -* Peripheral register definitions * -******************************************************************************/ -/** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals - MSP432P401R Device Specific Peripheral registers structures - @{ -*/ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TI_ARM__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/****************************************************************************** -* ADC14 Registers -******************************************************************************/ -/** @addtogroup ADC14 MSP432P401R (ADC14) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ - __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ - __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ - __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ - __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ - __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ - uint32_t RESERVED0[9]; - __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ - __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ - __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ - __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ - __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ - __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ - __IO uint32_t IV; /*!< Interrupt Vector Register */ -} ADC14_Type; - -/*@}*/ /* end of group ADC14 */ - - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -/** @addtogroup AES256 MSP432P401R (AES256) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ - __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ - __IO uint16_t STAT; /*!< AES Accelerator Status Register */ - __O uint16_t KEY; /*!< AES Accelerator Key Register */ - __O uint16_t DIN; /*!< AES Accelerator Data In Register */ - __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ - __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ - __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ -} AES256_Type; - -/*@}*/ /* end of group AES256 */ - - -/****************************************************************************** -* CAPTIO Registers -******************************************************************************/ -/** @addtogroup CAPTIO MSP432P401R (CAPTIO) - @{ -*/ -typedef struct { - uint16_t RESERVED0[7]; - __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ -} CAPTIO_Type; - -/*@}*/ /* end of group CAPTIO */ - - -/****************************************************************************** -* COMP_E Registers -******************************************************************************/ -/** @addtogroup COMP_E MSP432P401R (COMP_E) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ - __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ - __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ - __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ - uint16_t RESERVED0[2]; - __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ - __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ -} COMP_E_Type; - -/*@}*/ /* end of group COMP_E */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -/** @addtogroup CRC32 MSP432P401R (CRC32) - @{ -*/ -typedef struct { - __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ - uint16_t RESERVED0; - __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ - uint16_t RESERVED1; - __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ - __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ - __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ - __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ - __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ - uint16_t RESERVED2; - __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ - uint16_t RESERVED3; - __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ - uint16_t RESERVED4[2]; - __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ -} CRC32_Type; - -/*@}*/ /* end of group CRC32 */ - - -/****************************************************************************** -* CS Registers -******************************************************************************/ -/** @addtogroup CS MSP432P401R (CS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t CTL2; /*!< Control 2 Register */ - __IO uint32_t CTL3; /*!< Control 3 Register */ - uint32_t RESERVED0[7]; - __IO uint32_t CLKEN; /*!< Clock Enable Register */ - __I uint32_t STAT; /*!< Status Register */ - uint32_t RESERVED1[2]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - uint32_t RESERVED2; - __I uint32_t IFG; /*!< Interrupt Flag Register */ - uint32_t RESERVED3; - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - uint32_t RESERVED4; - __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - uint32_t RESERVED5; - __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ - __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ -} CS_Type; - -/*@}*/ /* end of group CS */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -/** @addtogroup DIO MSP432P401R (DIO) - @{ -*/ -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ - uint16_t RESERVED0[3]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; - union { - __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ - struct { - __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ - __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ - }; - }; - union { - __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ - struct { - __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ - __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ - }; - }; - union { - __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ - struct { - __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ - __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ - }; - }; - __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ -} DIO_PORT_Interruptable_Type; - -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - uint16_t RESERVED0[4]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; -} DIO_PORT_Not_Interruptable_Type; - - -typedef struct { - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED0; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED1; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED2; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED3; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED4; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED5; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED6; - __I uint16_t IV; /*!< Port Interrupt Vector Value */ - uint8_t RESERVED7[6]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ - uint8_t RESERVED11; -} DIO_PORT_Odd_Interruptable_Type; - -typedef struct { - uint8_t RESERVED0; - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED1; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED2; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED3; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED4; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED5; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED6; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED7[9]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ - __I uint16_t IV; /*!< Port Interrupt Vector Value */ -} DIO_PORT_Even_Interruptable_Type; - -/*@}*/ /* end of group MSP432P401R_DIO */ - - -/****************************************************************************** -* DMA Registers -******************************************************************************/ -/** @addtogroup DMA MSP432P401R (DMA) - @{ -*/ -typedef struct { - __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ - __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ - uint32_t RESERVED1[28]; - __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ - __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ - __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ - uint32_t RESERVED2; - __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ - __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ -} DMA_Channel_Type; - -typedef struct { - __I uint32_t STAT; /*!< Status Register */ - __O uint32_t CFG; /*!< Configuration Register */ - __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ - __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ - __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ - __O uint32_t SWREQ; /*!< Channel Software Request Register */ - __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ - __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ - __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ - __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ - __IO uint32_t ENASET; /*!< Channel Enable Set Register */ - __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ - __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ - __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ - __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ - __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ - uint32_t RESERVED4[3]; - __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ -} DMA_Control_Type; - -/*@}*/ /* end of group DMA */ - - -/****************************************************************************** -* EUSCI_A Registers -******************************************************************************/ -/** @addtogroup EUSCI_A MSP432P401R (EUSCI_A) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ - __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ - __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ - uint16_t RESERVED1[3]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_Type; - -/*@}*/ /* end of group EUSCI_A */ - -/** @addtogroup EUSCI_A_SPI MSP432P401R (EUSCI_A_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ - uint16_t RESERVED1; - __IO uint16_t STATW; - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - uint16_t RESERVED2[5]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_SPI_Type; - -/*@}*/ /* end of group EUSCI_A_SPI */ - - -/****************************************************************************** -* EUSCI_B Registers -******************************************************************************/ -/** @addtogroup EUSCI_B MSP432P401R (EUSCI_B) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ - __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED1[2]; - __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ - __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ - __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ - __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ - __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ - __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ - __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ - uint16_t RESERVED2[4]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_Type; - -/*@}*/ /* end of group EUSCI_B */ - -/** @addtogroup EUSCI_B_SPI MSP432P401R (EUSCI_B_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ - __IO uint16_t STATW; - uint16_t RESERVED1; - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED2[13]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_SPI_Type; - -/*@}*/ /* end of group EUSCI_B_SPI */ - - -/****************************************************************************** -* FLCTL Registers -******************************************************************************/ -/** @addtogroup FLCTL MSP432P401R (FLCTL) - @{ -*/ -typedef struct { - __I uint32_t POWER_STAT; /*!< Power Status Register */ - uint32_t RESERVED0[3]; - __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ - __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ - uint32_t RESERVED1[2]; - __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ - __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ - __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ - uint32_t RESERVED2[4]; - __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ - __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ - uint32_t RESERVED3[3]; - __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ - __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ - __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ - uint32_t RESERVED4; - __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ - __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ - __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ - __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ - __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ - __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ - __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ - __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ - __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ - __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ - __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ - __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ - __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ - __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ - __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ - __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ - __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ - __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ - uint32_t RESERVED5[2]; - __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ - __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ - uint32_t RESERVED6[2]; - __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ - __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ - uint32_t RESERVED7[2]; - __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ - __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ - __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ - __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ - uint32_t RESERVED8[4]; - __IO uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ - __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ - __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ - __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ - __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ - __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ - __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ - __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ - __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ -} FLCTL_Type; - -/*@}*/ /* end of group FLCTL */ - - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Registers -******************************************************************************/ -/** @addtogroup SEC_ZONE_PARAMS MSP432P401R (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ - __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ - __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ - __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ - __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ - __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ - __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ - __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ - __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ - uint32_t RESERVED0[2]; -} SEC_ZONE_PARAMS_Type; - -/*@}*/ /* end of group SEC_ZONE_PARAMS */ - -/** @addtogroup SEC_ZONE_UPDATE MSP432P401R (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ - __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ - uint32_t RESERVED0; -} SEC_ZONE_UPDATE_Type; - -/*@}*/ /* end of group SEC_ZONE_UPDATE */ - -/** @addtogroup FL_BOOTOVER_MAILBOX MSP432P401R (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ - __IO uint32_t CMD; /*!< Command for Boot override operations. */ - uint32_t RESERVED0[2]; - __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ - __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ - __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ - __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ - __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ - uint32_t RESERVED1[2]; - SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; - __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ - __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ - __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ - uint32_t RESERVED2[2]; - __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ - __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ - __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ - uint32_t RESERVED3; - SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; - uint32_t RESERVED4; - __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ - __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ - __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ - __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ - uint32_t RESERVED5; - __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ - __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ - uint32_t RESERVED6[2]; - __IO uint32_t MB_END; /*!< Mailbox end */ -} FL_BOOTOVER_MAILBOX_Type; - -/*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ - - -/****************************************************************************** -* PCM Registers -******************************************************************************/ -/** @addtogroup PCM MSP432P401R (PCM) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PCM_Type; - -/*@}*/ /* end of group PCM */ - - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -/** @addtogroup PMAP MSP432P401R (PMAP) - @{ -*/ -typedef struct { - __IO uint16_t KEYID; - __IO uint16_t CTL; -} PMAP_COMMON_Type; - -typedef struct { - union { - __IO uint16_t PMAP_REGISTER[4]; - struct { - __IO uint8_t PMAP_REGISTER0; - __IO uint8_t PMAP_REGISTER1; - __IO uint8_t PMAP_REGISTER2; - __IO uint8_t PMAP_REGISTER3; - __IO uint8_t PMAP_REGISTER4; - __IO uint8_t PMAP_REGISTER5; - __IO uint8_t PMAP_REGISTER6; - __IO uint8_t PMAP_REGISTER7; - }; - }; -} PMAP_REGISTER_Type; - -/*@}*/ /* end of group PMAP */ - - -/****************************************************************************** -* PSS Registers -******************************************************************************/ -/** @addtogroup PSS MSP432P401R (PSS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - uint32_t RESERVED0[11]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PSS_Type; - -/*@}*/ /* end of group PSS */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -/** @addtogroup REF_A MSP432P401R (REF_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< REF Control Register 0 */ -} REF_A_Type; - -/*@}*/ /* end of group REF_A */ - - -/****************************************************************************** -* RSTCTL Registers -******************************************************************************/ -/** @addtogroup RSTCTL MSP432P401R (RSTCTL) - @{ -*/ -typedef struct { - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ - __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ - __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ - __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ - __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ - __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ - uint32_t RESERVED0[57]; - __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ - __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ - __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ - __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ - __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ - __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ - __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ - __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ - __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ - __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ -} RSTCTL_Type; - -/*@}*/ /* end of group RSTCTL */ - - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -/** @addtogroup RTC_C MSP432P401R (RTC_C) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< RTCCTL0 Register */ - __IO uint16_t CTL13; /*!< RTCCTL13 Register */ - __IO uint16_t OCAL; /*!< RTCOCAL Register */ - __IO uint16_t TCMP; /*!< RTCTCMP Register */ - __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ - __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ - __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ - __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ - __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ - __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ - __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ - __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ - __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ - __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ - __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ -} RTC_C_Type; - -/*@}*/ /* end of group RTC_C */ - -/** @addtogroup RTC_C_BCD MSP432P401R (RTC_C_BCD) - @{ -*/ -typedef struct { - uint16_t RESERVED0[8]; - __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ - __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ - __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ - __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ - __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ -} RTC_C_BCD_Type; - -/*@}*/ /* end of group RTC_C_BCD */ - - -/****************************************************************************** -* SYSCTL Registers -******************************************************************************/ -/** @addtogroup SYSCTL MSP432P401R (SYSCTL) - @{ -*/ -typedef struct { - __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ - __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ - __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ - __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ - __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ - __IO uint32_t SRAM_BANKEN; /*!< SRAM Bank Enable Register */ - __IO uint32_t SRAM_BANKRET; /*!< SRAM Bank Retention Control Register */ - uint32_t RESERVED0; - __I uint32_t FLASH_SIZE; /*!< Flash Size Register */ - uint32_t RESERVED1[3]; - __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ - uint32_t RESERVED2[3]; - __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ -} SYSCTL_Type; - -typedef struct { - __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ - __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ - __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ - uint32_t RESERVED7[2]; - __I uint32_t SYSTEM_STAT; /*!< System Status Register */ -} SYSCTL_Boot_Type; - -/*@}*/ /* end of group SYSCTL */ - - -/****************************************************************************** -* Timer32 Registers -******************************************************************************/ -/** @addtogroup Timer32 MSP432P401R (Timer32) - @{ -*/ -typedef struct { - __IO uint32_t LOAD; /*!< Timer Load Register */ - __I uint32_t VALUE; /*!< Timer Current Value Register */ - __IO uint32_t CONTROL; /*!< Timer Control Register */ - __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ - __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Timer Interrupt Status Register */ - __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ -} Timer32_Type; - -/*@}*/ /* end of group Timer32 */ - - -/****************************************************************************** -* Timer_A Registers -******************************************************************************/ -/** @addtogroup Timer_A MSP432P401R (Timer_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL; /*!< TimerAx Control Register */ - __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ - uint16_t RESERVED0[2]; - __IO uint16_t R; /*!< TimerA register */ - __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ - uint16_t RESERVED1[2]; - __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ - uint16_t RESERVED2[6]; - __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ -} Timer_A_Type; - -/*@}*/ /* end of group Timer_A */ - - -/****************************************************************************** -* TLV Registers -******************************************************************************/ -/** @addtogroup TLV MSP432P401R (TLV) - @{ -*/ -typedef struct { - __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ - __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ - __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ - __I uint32_t DEVICE_ID; /*!< Device ID */ - __I uint32_t HWREV; /*!< HW Revision */ - __I uint32_t BCREV; /*!< Boot Code Revision */ - __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ - __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ - __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ - __I uint32_t DIE_XPOS; /*!< Die X-Position */ - __I uint32_t DIE_YPOS; /*!< Die Y-Position */ - __I uint32_t WAFER_ID; /*!< Wafer ID */ - __I uint32_t LOT_ID; /*!< Lot ID */ - __I uint32_t RESERVED0; /*!< Reserved */ - __I uint32_t RESERVED1; /*!< Reserved */ - __I uint32_t RESERVED2; /*!< Reserved */ - __I uint32_t TEST_RESULTS; /*!< Test Results */ - __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ - __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ - __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED3; /*!< Reserved */ - __I uint32_t RESERVED4; /*!< Reserved */ - __I uint32_t RESERVED5; /*!< Reserved */ - __I uint32_t RESERVED6; /*!< Reserved */ - __I float DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I float DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED7; /*!< Reserved */ - __I uint32_t RESERVED8; /*!< Reserved */ - __I uint32_t RESERVED9; /*!< Reserved */ - __I uint32_t RESERVED10; /*!< Reserved */ - __I float DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I float DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ - __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ - __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ - __I uint32_t ADC_OFFSET; /*!< ADC Offset */ - __I uint32_t RESERVED11; /*!< Reserved */ - __I uint32_t RESERVED12; /*!< Reserved */ - __I uint32_t RESERVED13; /*!< Reserved */ - __I uint32_t RESERVED14; /*!< Reserved */ - __I uint32_t RESERVED15; /*!< Reserved */ - __I uint32_t RESERVED16; /*!< Reserved */ - __I uint32_t RESERVED17; /*!< Reserved */ - __I uint32_t RESERVED18; /*!< Reserved */ - __I uint32_t RESERVED19; /*!< Reserved */ - __I uint32_t RESERVED20; /*!< Reserved */ - __I uint32_t RESERVED21; /*!< Reserved */ - __I uint32_t RESERVED22; /*!< Reserved */ - __I uint32_t RESERVED23; /*!< Reserved */ - __I uint32_t RESERVED24; /*!< Reserved */ - __I uint32_t RESERVED25; /*!< Reserved */ - __I uint32_t RESERVED26; /*!< Reserved */ - __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ - __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ - __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ - __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ - __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ - __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ - __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ - __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ - __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ - __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ - __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ - __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ - __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ - __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ - __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ - __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ - __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ - __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ - __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ - __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ - __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ - __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ - __I uint32_t TLV_END; /*!< TLV End Word */ -} TLV_Type; - -/*@}*/ /* end of group TLV */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -/** @addtogroup WDT_A MSP432P401R (WDT_A) - @{ -*/ -typedef struct { - uint16_t RESERVED0[6]; - __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ -} WDT_A_Type; - -/*@}*/ /* end of group WDT_A */ - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TI_ARM__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - -/*@}*/ /* end of group MSP432P401R_Peripherals */ - -/****************************************************************************** -* Peripheral declaration * -******************************************************************************/ -/** @addtogroup MSP432P401R_PeripheralDecl MSP432P401R Peripheral Declaration - @{ -*/ - -#define ADC14 ((ADC14_Type *) ADC14_BASE) -#define AES256 ((AES256_Type *) AES256_BASE) -#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) -#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) -#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) -#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) -#define CRC32 ((CRC32_Type *) CRC32_BASE) -#define CS ((CS_Type *) CS_BASE) -#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) -#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) -#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) -#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) -#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) -#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) -#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) -#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) -#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) -#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) -#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) -#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) -#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) -#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) -#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) -#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) -#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) -#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) -#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) -#define FLCTL ((FLCTL_Type *) FLCTL_BASE) -#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) -#define PCM ((PCM_Type *) PCM_BASE) -#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) -#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) -#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) -#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) -#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) -#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) -#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) -#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) -#define PSS ((PSS_Type *) PSS_BASE) -#define REF_A ((REF_A_Type *) REF_A_BASE) -#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) -#define RTC_C ((RTC_C_Type *) RTC_C_BASE) -#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) -#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) -#define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000)) -#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) -#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) -#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) -#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) -#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) -#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) -#define TLV ((TLV_Type *) TLV_BASE) -#define WDT_A ((WDT_A_Type *) WDT_A_BASE) - - -/*@}*/ /* end of group MSP432P401R_PeripheralDecl */ - -/*@}*/ /* end of group MSP432P401R_Definitions */ - -#endif /* __CMSIS_CONFIG__ */ - -/****************************************************************************** -* Peripheral register control bits * -******************************************************************************/ - -/****************************************************************************** -* ADC14 Bits -******************************************************************************/ -/* ADC14_CTL0[SC] Bits */ -#define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ -#define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ -/* ADC14_CTL0[ENC] Bits */ -#define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ -#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ -/* ADC14_CTL0[ON] Bits */ -#define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ -#define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ -/* ADC14_CTL0[MSC] Bits */ -#define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ -#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ -/* ADC14_CTL0[SHT0] Bits */ -#define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ -#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ -#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ -#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ -#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ -#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ -#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ -#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ -/* ADC14_CTL0[SHT1] Bits */ -#define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ -#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ -#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ -#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ -#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ -#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ -#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ -#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ -/* ADC14_CTL0[BUSY] Bits */ -#define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ -#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ -/* ADC14_CTL0[CONSEQ] Bits */ -#define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ -#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ -#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ -#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ -#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ -#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ -#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ -#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ -/* ADC14_CTL0[SSEL] Bits */ -#define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ -#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ -#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ -#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ -#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ -#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ -#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ -/* ADC14_CTL0[DIV] Bits */ -#define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ -#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ -#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ -#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ -#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ -#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ -#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ -/* ADC14_CTL0[ISSH] Bits */ -#define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ -#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ -/* ADC14_CTL0[SHP] Bits */ -#define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ -#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ -/* ADC14_CTL0[SHS] Bits */ -#define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ -#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ -#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ -#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ -#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ -#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ -#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ -/* ADC14_CTL0[PDIV] Bits */ -#define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ -#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ -#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ -#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ -#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -/* ADC14_CTL1[PWRMD] Bits */ -#define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ -#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ -#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ -#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ -#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ - /* up to 1 Msps. */ -#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ - /* rate must not exceed 200 ksps. */ -/* ADC14_CTL1[REFBURST] Bits */ -#define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ -#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ -/* ADC14_CTL1[DF] Bits */ -#define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ -#define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ -/* ADC14_CTL1[RES] Bits */ -#define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ -#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ -#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ -#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ -#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -/* ADC14_CTL1[CSTARTADD] Bits */ -#define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ -#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ -/* ADC14_CTL1[BATMAP] Bits */ -#define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ -#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ -/* ADC14_CTL1[TCMAP] Bits */ -#define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ -#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ -/* ADC14_CTL1[CH0MAP] Bits */ -#define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ -#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ -/* ADC14_CTL1[CH1MAP] Bits */ -#define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ -#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ -/* ADC14_CTL1[CH2MAP] Bits */ -#define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ -#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ -/* ADC14_CTL1[CH3MAP] Bits */ -#define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ -#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ -/* ADC14_LO0[LO0] Bits */ -#define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ -#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ -/* ADC14_HI0[HI0] Bits */ -#define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ -#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ -/* ADC14_LO1[LO1] Bits */ -#define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ -#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ -/* ADC14_HI1[HI1] Bits */ -#define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ -#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ -/* ADC14_MCTLN[INCH] Bits */ -#define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ -#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ -#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ -#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ -#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ -#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ -#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ -#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -/* ADC14_MCTLN[EOS] Bits */ -#define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ -#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ -/* ADC14_MCTLN[VRSEL] Bits */ -#define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ -#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ -#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ -#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ -#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ -#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ -#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ -#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ -/* ADC14_MCTLN[DIF] Bits */ -#define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ -#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ -/* ADC14_MCTLN[WINC] Bits */ -#define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ -#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ -/* ADC14_MCTLN[WINCTH] Bits */ -#define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ -#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ -/* ADC14_MEMN[CONVRES] Bits */ -#define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ -#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ -/* ADC14_IER0[IE0] Bits */ -#define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ -#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ -/* ADC14_IER0[IE1] Bits */ -#define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ -#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ -/* ADC14_IER0[IE2] Bits */ -#define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ -#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ -/* ADC14_IER0[IE3] Bits */ -#define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ -#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ -/* ADC14_IER0[IE4] Bits */ -#define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ -#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ -/* ADC14_IER0[IE5] Bits */ -#define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ -#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ -/* ADC14_IER0[IE6] Bits */ -#define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ -#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ -/* ADC14_IER0[IE7] Bits */ -#define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ -#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ -/* ADC14_IER0[IE8] Bits */ -#define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ -#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ -/* ADC14_IER0[IE9] Bits */ -#define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ -#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ -/* ADC14_IER0[IE10] Bits */ -#define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ -#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ -/* ADC14_IER0[IE11] Bits */ -#define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ -#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ -/* ADC14_IER0[IE12] Bits */ -#define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ -#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ -/* ADC14_IER0[IE13] Bits */ -#define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ -#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ -/* ADC14_IER0[IE14] Bits */ -#define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ -#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ -/* ADC14_IER0[IE15] Bits */ -#define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ -#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ -/* ADC14_IER0[IE16] Bits */ -#define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ -#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ -/* ADC14_IER0[IE17] Bits */ -#define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ -#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ -/* ADC14_IER0[IE19] Bits */ -#define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ -#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ -/* ADC14_IER0[IE18] Bits */ -#define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ -#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ -/* ADC14_IER0[IE20] Bits */ -#define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ -#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ -/* ADC14_IER0[IE21] Bits */ -#define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ -#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ -/* ADC14_IER0[IE22] Bits */ -#define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ -#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ -/* ADC14_IER0[IE23] Bits */ -#define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ -#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ -/* ADC14_IER0[IE24] Bits */ -#define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ -#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE25] Bits */ -#define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ -#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE26] Bits */ -#define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ -#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE27] Bits */ -#define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ -#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE28] Bits */ -#define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ -#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE29] Bits */ -#define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ -#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE30] Bits */ -#define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ -#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE31] Bits */ -#define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ -#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ -/* ADC14_IER1[INIE] Bits */ -#define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ -#define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ -/* ADC14_IER1[LOIE] Bits */ -#define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ -#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ -/* ADC14_IER1[HIIE] Bits */ -#define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ -#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ -/* ADC14_IER1[OVIE] Bits */ -#define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ -#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ -/* ADC14_IER1[TOVIE] Bits */ -#define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ -#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ -/* ADC14_IER1[RDYIE] Bits */ -#define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ -#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ -/* ADC14_IFGR0[IFG0] Bits */ -#define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ -#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ -/* ADC14_IFGR0[IFG1] Bits */ -#define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ -#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ -/* ADC14_IFGR0[IFG2] Bits */ -#define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ -#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ -/* ADC14_IFGR0[IFG3] Bits */ -#define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ -#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ -/* ADC14_IFGR0[IFG4] Bits */ -#define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ -#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ -/* ADC14_IFGR0[IFG5] Bits */ -#define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ -#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ -/* ADC14_IFGR0[IFG6] Bits */ -#define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ -#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ -/* ADC14_IFGR0[IFG7] Bits */ -#define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ -#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ -/* ADC14_IFGR0[IFG8] Bits */ -#define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ -#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ -/* ADC14_IFGR0[IFG9] Bits */ -#define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ -#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ -/* ADC14_IFGR0[IFG10] Bits */ -#define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ -#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ -/* ADC14_IFGR0[IFG11] Bits */ -#define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ -#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ -/* ADC14_IFGR0[IFG12] Bits */ -#define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ -#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ -/* ADC14_IFGR0[IFG13] Bits */ -#define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ -#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ -/* ADC14_IFGR0[IFG14] Bits */ -#define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ -#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ -/* ADC14_IFGR0[IFG15] Bits */ -#define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ -#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ -/* ADC14_IFGR0[IFG16] Bits */ -#define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ -#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ -/* ADC14_IFGR0[IFG17] Bits */ -#define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ -#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ -/* ADC14_IFGR0[IFG18] Bits */ -#define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ -#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ -/* ADC14_IFGR0[IFG19] Bits */ -#define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ -#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ -/* ADC14_IFGR0[IFG20] Bits */ -#define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ -#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ -/* ADC14_IFGR0[IFG21] Bits */ -#define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ -#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ -/* ADC14_IFGR0[IFG22] Bits */ -#define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ -#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ -/* ADC14_IFGR0[IFG23] Bits */ -#define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ -#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ -/* ADC14_IFGR0[IFG24] Bits */ -#define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ -#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ -/* ADC14_IFGR0[IFG25] Bits */ -#define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ -#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ -/* ADC14_IFGR0[IFG26] Bits */ -#define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ -#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ -/* ADC14_IFGR0[IFG27] Bits */ -#define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ -#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ -/* ADC14_IFGR0[IFG28] Bits */ -#define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ -#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ -/* ADC14_IFGR0[IFG29] Bits */ -#define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ -#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ -/* ADC14_IFGR0[IFG30] Bits */ -#define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ -#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ -/* ADC14_IFGR0[IFG31] Bits */ -#define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ -#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ -/* ADC14_IFGR1[INIFG] Bits */ -#define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ -#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ -/* ADC14_IFGR1[LOIFG] Bits */ -#define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ -#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ -/* ADC14_IFGR1[HIIFG] Bits */ -#define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ -#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ -/* ADC14_IFGR1[OVIFG] Bits */ -#define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ -#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ -/* ADC14_IFGR1[TOVIFG] Bits */ -#define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ -#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ -/* ADC14_IFGR1[RDYIFG] Bits */ -#define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ -#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ -/* ADC14_CLRIFGR0[CLRIFG0] Bits */ -#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ -/* ADC14_CLRIFGR0[CLRIFG1] Bits */ -#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ -/* ADC14_CLRIFGR0[CLRIFG2] Bits */ -#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ -/* ADC14_CLRIFGR0[CLRIFG3] Bits */ -#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ -/* ADC14_CLRIFGR0[CLRIFG4] Bits */ -#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ -/* ADC14_CLRIFGR0[CLRIFG5] Bits */ -#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ -/* ADC14_CLRIFGR0[CLRIFG6] Bits */ -#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ -/* ADC14_CLRIFGR0[CLRIFG7] Bits */ -#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ -/* ADC14_CLRIFGR0[CLRIFG8] Bits */ -#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ -/* ADC14_CLRIFGR0[CLRIFG9] Bits */ -#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ -/* ADC14_CLRIFGR0[CLRIFG10] Bits */ -#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ -/* ADC14_CLRIFGR0[CLRIFG11] Bits */ -#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ -/* ADC14_CLRIFGR0[CLRIFG12] Bits */ -#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ -/* ADC14_CLRIFGR0[CLRIFG13] Bits */ -#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ -/* ADC14_CLRIFGR0[CLRIFG14] Bits */ -#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ -/* ADC14_CLRIFGR0[CLRIFG15] Bits */ -#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ -/* ADC14_CLRIFGR0[CLRIFG16] Bits */ -#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ -/* ADC14_CLRIFGR0[CLRIFG17] Bits */ -#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ -/* ADC14_CLRIFGR0[CLRIFG18] Bits */ -#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ -/* ADC14_CLRIFGR0[CLRIFG19] Bits */ -#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ -/* ADC14_CLRIFGR0[CLRIFG20] Bits */ -#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ -/* ADC14_CLRIFGR0[CLRIFG21] Bits */ -#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ -/* ADC14_CLRIFGR0[CLRIFG22] Bits */ -#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ -/* ADC14_CLRIFGR0[CLRIFG23] Bits */ -#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ -/* ADC14_CLRIFGR0[CLRIFG24] Bits */ -#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ -/* ADC14_CLRIFGR0[CLRIFG25] Bits */ -#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ -/* ADC14_CLRIFGR0[CLRIFG26] Bits */ -#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ -/* ADC14_CLRIFGR0[CLRIFG27] Bits */ -#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ -/* ADC14_CLRIFGR0[CLRIFG28] Bits */ -#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ -/* ADC14_CLRIFGR0[CLRIFG29] Bits */ -#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ -/* ADC14_CLRIFGR0[CLRIFG30] Bits */ -#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ -/* ADC14_CLRIFGR0[CLRIFG31] Bits */ -#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ -/* ADC14_CLRIFGR1[CLRINIFG] Bits */ -#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ -/* ADC14_CLRIFGR1[CLRLOIFG] Bits */ -#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ -/* ADC14_CLRIFGR1[CLRHIIFG] Bits */ -#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ -/* ADC14_CLRIFGR1[CLROVIFG] Bits */ -#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ -/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ -#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ -/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ -#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ - -/****************************************************************************** -* AES256 Bits -******************************************************************************/ -/* AES256_CTL0[OP] Bits */ -#define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ -#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ -#define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ -#define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ -#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ -#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ -#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ -#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ -/* AES256_CTL0[KL] Bits */ -#define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ -#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ -#define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ -#define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ -#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -/* AES256_CTL0[CM] Bits */ -#define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ -#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ -#define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ -#define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ -#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ -#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ -/* AES256_CTL0[SWRST] Bits */ -#define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ -#define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ -/* AES256_CTL0[RDYIFG] Bits */ -#define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ -#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ -/* AES256_CTL0[ERRFG] Bits */ -#define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ -#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ -/* AES256_CTL0[RDYIE] Bits */ -#define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ -#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ -/* AES256_CTL0[CMEN] Bits */ -#define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ -#define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ -/* AES256_CTL1[BLKCNT] Bits */ -#define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ -#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ -#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ -#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ -#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ -#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ -#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ -#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ -#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ -#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ -/* AES256_STAT[BUSY] Bits */ -#define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ -#define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ -/* AES256_STAT[KEYWR] Bits */ -#define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ -#define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ -/* AES256_STAT[DINWR] Bits */ -#define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ -#define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AES256_STAT[DOUTRD] Bits */ -#define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ -#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ -/* AES256_STAT[KEYCNT] Bits */ -#define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ -#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ -#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ -#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ -#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ -#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ -/* AES256_STAT[DINCNT] Bits */ -#define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ -#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ -#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ -#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ -#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ -#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ -/* AES256_STAT[DOUTCNT] Bits */ -#define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ -#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ -#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ -#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ -#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ -#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ -/* AES256_KEY[KEY0] Bits */ -#define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ -#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ -#define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ -#define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ -#define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ -#define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ -#define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ -#define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ -#define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ -#define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ -/* AES256_KEY[KEY1] Bits */ -#define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ -#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ -#define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ -#define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ -#define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ -#define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ -#define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ -#define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ -#define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ -#define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ -/* AES256_DIN[DIN0] Bits */ -#define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ -#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ -#define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ -#define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ -#define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ -#define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ -#define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ -#define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ -#define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ -#define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ -/* AES256_DIN[DIN1] Bits */ -#define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ -#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ -#define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ -#define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ -#define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ -#define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ -#define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ -#define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ -#define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ -#define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ -/* AES256_DOUT[DOUT0] Bits */ -#define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ -#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ -#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ -#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ -#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ -#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ -#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ -#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ -#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ -#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ -/* AES256_DOUT[DOUT1] Bits */ -#define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ -#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ -#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ -#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ -#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ -#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ -#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ -#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ -#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ -#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ -/* AES256_XDIN[XDIN0] Bits */ -#define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ -#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ -#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ -#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ -#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ -#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ -#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ -#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ -#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ -#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ -/* AES256_XDIN[XDIN1] Bits */ -#define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ -#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ -#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ -#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ -#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ -#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ -#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ -#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ -#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ -#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ -/* AES256_XIN[XIN0] Bits */ -#define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ -#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ -#define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ -#define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ -#define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ -#define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ -#define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ -#define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ -#define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ -#define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ -/* AES256_XIN[XIN1] Bits */ -#define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ -#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ -#define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ -#define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ -#define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ -#define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ -#define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ -#define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ -#define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ -#define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits -******************************************************************************/ -/* CAPTIO_CTL[PISEL] Bits */ -#define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ -#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ -#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ -#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ -#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ -#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ -#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ -#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ -#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ -#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ -#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ -#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ -#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ -/* CAPTIO_CTL[POSEL] Bits */ -#define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ -#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ -#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ -#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ -#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ -#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ -#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ -#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ -/* CAPTIO_CTL[EN] Bits */ -#define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ -#define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ -/* CAPTIO_CTL[STATE] Bits */ -#define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ -#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits -******************************************************************************/ -/* COMP_E_CTL0[IPSEL] Bits */ -#define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ -#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ -#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ -#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ -#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ -#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ -#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IPEN] Bits */ -#define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ -#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ -/* COMP_E_CTL0[IMSEL] Bits */ -#define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ -#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ -#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ -#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ -#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ -#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ -#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IMEN] Bits */ -#define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ -#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ -/* COMP_E_CTL1[OUT] Bits */ -#define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ -#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ -/* COMP_E_CTL1[OUTPOL] Bits */ -#define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ -#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ -/* COMP_E_CTL1[F] Bits */ -#define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ -#define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ -/* COMP_E_CTL1[IES] Bits */ -#define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ -#define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* COMP_E_CTL1[SHORT] Bits */ -#define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ -#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ -/* COMP_E_CTL1[EX] Bits */ -#define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ -#define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ -/* COMP_E_CTL1[FDLY] Bits */ -#define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ -#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ -#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ -#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ -#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ -#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ -#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ -#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ -/* COMP_E_CTL1[PWRMD] Bits */ -#define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ -#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ -#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ -#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ -#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ -#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ -#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ -/* COMP_E_CTL1[ON] Bits */ -#define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ -#define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ -/* COMP_E_CTL1[MRVL] Bits */ -#define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ -#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ -/* COMP_E_CTL1[MRVS] Bits */ -#define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ -#define COMP_E_CTL1_MRVS ((uint16_t)0x1000) -/* COMP_E_CTL2[REF0] Bits */ -#define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ -#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ -#define COMP_E_CTL2_REF00 ((uint16_t)0x0001) /*!< REF0 Bit 0 */ -#define COMP_E_CTL2_REF01 ((uint16_t)0x0002) /*!< REF0 Bit 1 */ -#define COMP_E_CTL2_REF02 ((uint16_t)0x0004) /*!< REF0 Bit 2 */ -#define COMP_E_CTL2_REF03 ((uint16_t)0x0008) /*!< REF0 Bit 3 */ -#define COMP_E_CTL2_REF04 ((uint16_t)0x0010) /*!< REF0 Bit 4 */ -#define COMP_E_CTL2_REF0_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ -#define COMP_E_CTL2_REF0_1 ((uint16_t)0x0001) /*!< Reference resistor tap for setting 1. */ -#define COMP_E_CTL2_REF0_2 ((uint16_t)0x0002) /*!< Reference resistor tap for setting 2. */ -#define COMP_E_CTL2_REF0_3 ((uint16_t)0x0003) /*!< Reference resistor tap for setting 3. */ -#define COMP_E_CTL2_REF0_4 ((uint16_t)0x0004) /*!< Reference resistor tap for setting 4. */ -#define COMP_E_CTL2_REF0_5 ((uint16_t)0x0005) /*!< Reference resistor tap for setting 5. */ -#define COMP_E_CTL2_REF0_6 ((uint16_t)0x0006) /*!< Reference resistor tap for setting 6. */ -#define COMP_E_CTL2_REF0_7 ((uint16_t)0x0007) /*!< Reference resistor tap for setting 7. */ -#define COMP_E_CTL2_REF0_8 ((uint16_t)0x0008) /*!< Reference resistor tap for setting 8. */ -#define COMP_E_CTL2_REF0_9 ((uint16_t)0x0009) /*!< Reference resistor tap for setting 9. */ -#define COMP_E_CTL2_REF0_10 ((uint16_t)0x000A) /*!< Reference resistor tap for setting 10. */ -#define COMP_E_CTL2_REF0_11 ((uint16_t)0x000B) /*!< Reference resistor tap for setting 11. */ -#define COMP_E_CTL2_REF0_12 ((uint16_t)0x000C) /*!< Reference resistor tap for setting 12. */ -#define COMP_E_CTL2_REF0_13 ((uint16_t)0x000D) /*!< Reference resistor tap for setting 13. */ -#define COMP_E_CTL2_REF0_14 ((uint16_t)0x000E) /*!< Reference resistor tap for setting 14. */ -#define COMP_E_CTL2_REF0_15 ((uint16_t)0x000F) /*!< Reference resistor tap for setting 15. */ -#define COMP_E_CTL2_REF0_16 ((uint16_t)0x0010) /*!< Reference resistor tap for setting 16. */ -#define COMP_E_CTL2_REF0_17 ((uint16_t)0x0011) /*!< Reference resistor tap for setting 17. */ -#define COMP_E_CTL2_REF0_18 ((uint16_t)0x0012) /*!< Reference resistor tap for setting 18. */ -#define COMP_E_CTL2_REF0_19 ((uint16_t)0x0013) /*!< Reference resistor tap for setting 19. */ -#define COMP_E_CTL2_REF0_20 ((uint16_t)0x0014) /*!< Reference resistor tap for setting 20. */ -#define COMP_E_CTL2_REF0_21 ((uint16_t)0x0015) /*!< Reference resistor tap for setting 21. */ -#define COMP_E_CTL2_REF0_22 ((uint16_t)0x0016) /*!< Reference resistor tap for setting 22. */ -#define COMP_E_CTL2_REF0_23 ((uint16_t)0x0017) /*!< Reference resistor tap for setting 23. */ -#define COMP_E_CTL2_REF0_24 ((uint16_t)0x0018) /*!< Reference resistor tap for setting 24. */ -#define COMP_E_CTL2_REF0_25 ((uint16_t)0x0019) /*!< Reference resistor tap for setting 25. */ -#define COMP_E_CTL2_REF0_26 ((uint16_t)0x001A) /*!< Reference resistor tap for setting 26. */ -#define COMP_E_CTL2_REF0_27 ((uint16_t)0x001B) /*!< Reference resistor tap for setting 27. */ -#define COMP_E_CTL2_REF0_28 ((uint16_t)0x001C) /*!< Reference resistor tap for setting 28. */ -#define COMP_E_CTL2_REF0_29 ((uint16_t)0x001D) /*!< Reference resistor tap for setting 29. */ -#define COMP_E_CTL2_REF0_30 ((uint16_t)0x001E) /*!< Reference resistor tap for setting 30. */ -#define COMP_E_CTL2_REF0_31 ((uint16_t)0x001F) /*!< Reference resistor tap for setting 31. */ -/* COMP_E_CTL2[RSEL] Bits */ -#define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ -#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ -/* COMP_E_CTL2[RS] Bits */ -#define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ -#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ -#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ -#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ -#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ -#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ -#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ -#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* COMP_E_CTL2[REF1] Bits */ -#define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ -#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ -#define COMP_E_CTL2_REF10 ((uint16_t)0x0100) /*!< REF1 Bit 0 */ -#define COMP_E_CTL2_REF11 ((uint16_t)0x0200) /*!< REF1 Bit 1 */ -#define COMP_E_CTL2_REF12 ((uint16_t)0x0400) /*!< REF1 Bit 2 */ -#define COMP_E_CTL2_REF13 ((uint16_t)0x0800) /*!< REF1 Bit 3 */ -#define COMP_E_CTL2_REF14 ((uint16_t)0x1000) /*!< REF1 Bit 4 */ -#define COMP_E_CTL2_REF1_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ -#define COMP_E_CTL2_REF1_1 ((uint16_t)0x0100) /*!< Reference resistor tap for setting 1. */ -#define COMP_E_CTL2_REF1_2 ((uint16_t)0x0200) /*!< Reference resistor tap for setting 2. */ -#define COMP_E_CTL2_REF1_3 ((uint16_t)0x0300) /*!< Reference resistor tap for setting 3. */ -#define COMP_E_CTL2_REF1_4 ((uint16_t)0x0400) /*!< Reference resistor tap for setting 4. */ -#define COMP_E_CTL2_REF1_5 ((uint16_t)0x0500) /*!< Reference resistor tap for setting 5. */ -#define COMP_E_CTL2_REF1_6 ((uint16_t)0x0600) /*!< Reference resistor tap for setting 6. */ -#define COMP_E_CTL2_REF1_7 ((uint16_t)0x0700) /*!< Reference resistor tap for setting 7. */ -#define COMP_E_CTL2_REF1_8 ((uint16_t)0x0800) /*!< Reference resistor tap for setting 8. */ -#define COMP_E_CTL2_REF1_9 ((uint16_t)0x0900) /*!< Reference resistor tap for setting 9. */ -#define COMP_E_CTL2_REF1_10 ((uint16_t)0x0A00) /*!< Reference resistor tap for setting 10. */ -#define COMP_E_CTL2_REF1_11 ((uint16_t)0x0B00) /*!< Reference resistor tap for setting 11. */ -#define COMP_E_CTL2_REF1_12 ((uint16_t)0x0C00) /*!< Reference resistor tap for setting 12. */ -#define COMP_E_CTL2_REF1_13 ((uint16_t)0x0D00) /*!< Reference resistor tap for setting 13. */ -#define COMP_E_CTL2_REF1_14 ((uint16_t)0x0E00) /*!< Reference resistor tap for setting 14. */ -#define COMP_E_CTL2_REF1_15 ((uint16_t)0x0F00) /*!< Reference resistor tap for setting 15. */ -#define COMP_E_CTL2_REF1_16 ((uint16_t)0x1000) /*!< Reference resistor tap for setting 16. */ -#define COMP_E_CTL2_REF1_17 ((uint16_t)0x1100) /*!< Reference resistor tap for setting 17. */ -#define COMP_E_CTL2_REF1_18 ((uint16_t)0x1200) /*!< Reference resistor tap for setting 18. */ -#define COMP_E_CTL2_REF1_19 ((uint16_t)0x1300) /*!< Reference resistor tap for setting 19. */ -#define COMP_E_CTL2_REF1_20 ((uint16_t)0x1400) /*!< Reference resistor tap for setting 20. */ -#define COMP_E_CTL2_REF1_21 ((uint16_t)0x1500) /*!< Reference resistor tap for setting 21. */ -#define COMP_E_CTL2_REF1_22 ((uint16_t)0x1600) /*!< Reference resistor tap for setting 22. */ -#define COMP_E_CTL2_REF1_23 ((uint16_t)0x1700) /*!< Reference resistor tap for setting 23. */ -#define COMP_E_CTL2_REF1_24 ((uint16_t)0x1800) /*!< Reference resistor tap for setting 24. */ -#define COMP_E_CTL2_REF1_25 ((uint16_t)0x1900) /*!< Reference resistor tap for setting 25. */ -#define COMP_E_CTL2_REF1_26 ((uint16_t)0x1A00) /*!< Reference resistor tap for setting 26. */ -#define COMP_E_CTL2_REF1_27 ((uint16_t)0x1B00) /*!< Reference resistor tap for setting 27. */ -#define COMP_E_CTL2_REF1_28 ((uint16_t)0x1C00) /*!< Reference resistor tap for setting 28. */ -#define COMP_E_CTL2_REF1_29 ((uint16_t)0x1D00) /*!< Reference resistor tap for setting 29. */ -#define COMP_E_CTL2_REF1_30 ((uint16_t)0x1E00) /*!< Reference resistor tap for setting 30. */ -#define COMP_E_CTL2_REF1_31 ((uint16_t)0x1F00) /*!< Reference resistor tap for setting 31. */ -/* COMP_E_CTL2[REFL] Bits */ -#define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ -#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ -#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ -#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ -#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -/* COMP_E_CTL2[REFACC] Bits */ -#define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ -#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ -/* COMP_E_CTL3[PD0] Bits */ -#define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ -#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ -/* COMP_E_CTL3[PD1] Bits */ -#define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ -#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ -/* COMP_E_CTL3[PD2] Bits */ -#define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ -#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ -/* COMP_E_CTL3[PD3] Bits */ -#define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ -#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ -/* COMP_E_CTL3[PD4] Bits */ -#define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ -#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ -/* COMP_E_CTL3[PD5] Bits */ -#define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ -#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ -/* COMP_E_CTL3[PD6] Bits */ -#define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ -#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ -/* COMP_E_CTL3[PD7] Bits */ -#define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ -#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ -/* COMP_E_CTL3[PD8] Bits */ -#define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ -#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ -/* COMP_E_CTL3[PD9] Bits */ -#define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ -#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ -/* COMP_E_CTL3[PD10] Bits */ -#define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ -#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ -/* COMP_E_CTL3[PD11] Bits */ -#define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ -#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ -/* COMP_E_CTL3[PD12] Bits */ -#define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ -#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ -/* COMP_E_CTL3[PD13] Bits */ -#define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ -#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ -/* COMP_E_CTL3[PD14] Bits */ -#define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ -#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ -/* COMP_E_CTL3[PD15] Bits */ -#define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ -#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ -/* COMP_E_INT[IFG] Bits */ -#define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ -#define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ -/* COMP_E_INT[IIFG] Bits */ -#define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ -#define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ -/* COMP_E_INT[RDYIFG] Bits */ -#define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ -#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ -/* COMP_E_INT[IE] Bits */ -#define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ -#define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ -/* COMP_E_INT[IIE] Bits */ -#define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ -#define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ -/* COMP_E_INT[RDYIE] Bits */ -#define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ -#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* COREDEBUG Bits -******************************************************************************/ - - -/****************************************************************************** -* CRC32 Bits -******************************************************************************/ - -/****************************************************************************** -* CS Bits -******************************************************************************/ -/* CS_KEY[KEY] Bits */ -#define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ -#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ -/* CS_CTL0[DCOTUNE] Bits */ -#define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ -#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ -/* CS_CTL0[DCORSEL] Bits */ -#define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ -#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ -#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ -#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ -#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ -#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ -#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ -#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ -#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ -#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ -#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ -/* CS_CTL0[DCORES] Bits */ -#define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ -#define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ -/* CS_CTL0[DCOEN] Bits */ -#define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ -#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ -/* CS_CTL1[SELM] Bits */ -#define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ -#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ -#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ -#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ -#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ -#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM_1 ((uint32_t)0x00000001) -#define CS_CTL1_SELM_2 ((uint32_t)0x00000002) -#define CS_CTL1_SELM_3 ((uint32_t)0x00000003) -#define CS_CTL1_SELM_4 ((uint32_t)0x00000004) -#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) -#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) -#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) -#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) -#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELS] Bits */ -#define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ -#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ -#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ -#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ -#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ -#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS_1 ((uint32_t)0x00000010) -#define CS_CTL1_SELS_2 ((uint32_t)0x00000020) -#define CS_CTL1_SELS_3 ((uint32_t)0x00000030) -#define CS_CTL1_SELS_4 ((uint32_t)0x00000040) -#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) -#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) -#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) -#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) -#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELA] Bits */ -#define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ -#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ -#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ -#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ -#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ -#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA_1 ((uint32_t)0x00000100) -#define CS_CTL1_SELA_2 ((uint32_t)0x00000200) -#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) -#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) -/* CS_CTL1[SELB] Bits */ -#define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ -#define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ -/* CS_CTL1[DIVM] Bits */ -#define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ -#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ -#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ -#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ -#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ -#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -/* CS_CTL1[DIVHS] Bits */ -#define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ -#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ -#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ -#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ -#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ -#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -/* CS_CTL1[DIVA] Bits */ -#define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ -#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ -#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ -#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ -#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ -#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -/* CS_CTL1[DIVS] Bits */ -#define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ -#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ -#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ -#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ -#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ -#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -/* CS_CTL2[LFXTDRIVE] Bits */ -#define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ -#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ -#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ -#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ -#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ -/* CS_CTL2[LFXT_EN] Bits */ -#define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ -#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[LFXTBYPASS] Bits */ -#define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ -#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ -/* CS_CTL2[HFXTDRIVE] Bits */ -#define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ -#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ -/* CS_CTL2[HFXTFREQ] Bits */ -#define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ -#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ -#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ -#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ -#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ -#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ -#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ -#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ -#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ -#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ -#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ -#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ -#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ -/* CS_CTL2[HFXT_EN] Bits */ -#define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ -#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[HFXTBYPASS] Bits */ -#define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ -#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ -/* CS_CTL3[FCNTLF] Bits */ -#define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ -#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ -#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ -#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ -#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ -#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ -/* CS_CTL3[RFCNTLF] Bits */ -#define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ -#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ -/* CS_CTL3[FCNTLF_EN] Bits */ -#define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ -#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ -/* CS_CTL3[FCNTHF] Bits */ -#define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ -#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ -#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ -#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ -#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ -/* CS_CTL3[RFCNTHF] Bits */ -#define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ -#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ -/* CS_CTL3[FCNTHF_EN] Bits */ -#define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ -#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ -/* CS_CLKEN[ACLK_EN] Bits */ -#define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ -#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ -/* CS_CLKEN[MCLK_EN] Bits */ -#define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ -#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ -/* CS_CLKEN[HSMCLK_EN] Bits */ -#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ -#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ -/* CS_CLKEN[SMCLK_EN] Bits */ -#define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ -#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ -/* CS_CLKEN[VLO_EN] Bits */ -#define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ -#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ -/* CS_CLKEN[REFO_EN] Bits */ -#define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ -#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ -/* CS_CLKEN[MODOSC_EN] Bits */ -#define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ -#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ -/* CS_CLKEN[REFOFSEL] Bits */ -#define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ -#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ -/* CS_STAT[DCO_ON] Bits */ -#define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ -#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ -/* CS_STAT[DCOBIAS_ON] Bits */ -#define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ -#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ -/* CS_STAT[HFXT_ON] Bits */ -#define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ -#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ -/* CS_STAT[MODOSC_ON] Bits */ -#define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ -#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ -/* CS_STAT[VLO_ON] Bits */ -#define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ -#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ -/* CS_STAT[LFXT_ON] Bits */ -#define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ -#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ -/* CS_STAT[REFO_ON] Bits */ -#define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ -#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ -/* CS_STAT[ACLK_ON] Bits */ -#define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ -#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ -/* CS_STAT[MCLK_ON] Bits */ -#define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ -#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ -/* CS_STAT[HSMCLK_ON] Bits */ -#define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ -#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ -/* CS_STAT[SMCLK_ON] Bits */ -#define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ -#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ -/* CS_STAT[MODCLK_ON] Bits */ -#define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ -#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ -/* CS_STAT[VLOCLK_ON] Bits */ -#define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ -#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ -/* CS_STAT[LFXTCLK_ON] Bits */ -#define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ -#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ -/* CS_STAT[REFOCLK_ON] Bits */ -#define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ -#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ -/* CS_STAT[ACLK_READY] Bits */ -#define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ -#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ -/* CS_STAT[MCLK_READY] Bits */ -#define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ -#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ -/* CS_STAT[HSMCLK_READY] Bits */ -#define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ -#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ -/* CS_STAT[SMCLK_READY] Bits */ -#define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ -#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ -/* CS_STAT[BCLK_READY] Bits */ -#define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ -#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ -/* CS_IE[LFXTIE] Bits */ -#define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ -#define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ -/* CS_IE[HFXTIE] Bits */ -#define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ -#define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ -/* CS_IE[DCOR_OPNIE] Bits */ -#define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ -#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ -/* CS_IE[FCNTLFIE] Bits */ -#define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ -#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ -/* CS_IE[FCNTHFIE] Bits */ -#define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ -#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ -/* CS_IFG[LFXTIFG] Bits */ -#define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ -#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ -/* CS_IFG[HFXTIFG] Bits */ -#define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ -#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ -/* CS_IFG[DCOR_SHTIFG] Bits */ -#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ -#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ -/* CS_IFG[DCOR_OPNIFG] Bits */ -#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ -#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ -/* CS_IFG[FCNTLFIFG] Bits */ -#define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ -#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ -/* CS_IFG[FCNTHFIFG] Bits */ -#define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ -#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ -/* CS_CLRIFG[CLR_LFXTIFG] Bits */ -#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_HFXTIFG] Bits */ -#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ -/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ -/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ -/* CS_SETIFG[SET_LFXTIFG] Bits */ -#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ -#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_HFXTIFG] Bits */ -#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ -#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ -#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ -#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ -/* CS_SETIFG[SET_FCNTHFIFG] Bits */ -#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ -/* CS_SETIFG[SET_FCNTLFIFG] Bits */ -#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ -/* CS_DCOERCAL0[DCO_TCCAL] Bits */ -#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ -#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ -/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ -/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ -/* Pre-defined bitfield values */ -#define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ - -/****************************************************************************** -* DIO Bits -******************************************************************************/ -/* DIO_IV[IV] Bits */ -#define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ -#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ -#define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ -#define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ -#define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ -#define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ -#define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ -#define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ -#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ - - -/****************************************************************************** -* DMA Bits -******************************************************************************/ -/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ -/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ -/* DMA_SW_CHTRIG[CH0] Bits */ -#define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ -/* DMA_SW_CHTRIG[CH1] Bits */ -#define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ -/* DMA_SW_CHTRIG[CH2] Bits */ -#define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ -/* DMA_SW_CHTRIG[CH3] Bits */ -#define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ -/* DMA_SW_CHTRIG[CH4] Bits */ -#define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ -/* DMA_SW_CHTRIG[CH5] Bits */ -#define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ -/* DMA_SW_CHTRIG[CH6] Bits */ -#define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ -/* DMA_SW_CHTRIG[CH7] Bits */ -#define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ -/* DMA_SW_CHTRIG[CH8] Bits */ -#define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ -/* DMA_SW_CHTRIG[CH9] Bits */ -#define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ -/* DMA_SW_CHTRIG[CH10] Bits */ -#define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ -/* DMA_SW_CHTRIG[CH11] Bits */ -#define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ -/* DMA_SW_CHTRIG[CH12] Bits */ -#define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ -/* DMA_SW_CHTRIG[CH13] Bits */ -#define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ -/* DMA_SW_CHTRIG[CH14] Bits */ -#define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ -/* DMA_SW_CHTRIG[CH15] Bits */ -#define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ -/* DMA_SW_CHTRIG[CH16] Bits */ -#define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ -/* DMA_SW_CHTRIG[CH17] Bits */ -#define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ -/* DMA_SW_CHTRIG[CH18] Bits */ -#define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ -/* DMA_SW_CHTRIG[CH19] Bits */ -#define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ -/* DMA_SW_CHTRIG[CH20] Bits */ -#define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ -/* DMA_SW_CHTRIG[CH21] Bits */ -#define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ -/* DMA_SW_CHTRIG[CH22] Bits */ -#define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ -/* DMA_SW_CHTRIG[CH23] Bits */ -#define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ -/* DMA_SW_CHTRIG[CH24] Bits */ -#define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ -/* DMA_SW_CHTRIG[CH25] Bits */ -#define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ -/* DMA_SW_CHTRIG[CH26] Bits */ -#define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ -/* DMA_SW_CHTRIG[CH27] Bits */ -#define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ -/* DMA_SW_CHTRIG[CH28] Bits */ -#define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ -/* DMA_SW_CHTRIG[CH29] Bits */ -#define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ -/* DMA_SW_CHTRIG[CH30] Bits */ -#define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ -/* DMA_SW_CHTRIG[CH31] Bits */ -#define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ -/* DMA_CHN_SRCCFG[DMA_SRC] Bits */ -#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ -#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[INT_SRC] Bits */ -#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[EN] Bits */ -#define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ -/* DMA_INT2_SRCCFG[INT_SRC] Bits */ -#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT2_SRCCFG[EN] Bits */ -#define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ -/* DMA_INT3_SRCCFG[INT_SRC] Bits */ -#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT3_SRCCFG[EN] Bits */ -#define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ -/* DMA_INT0_SRCFLG[CH0] Bits */ -#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH1] Bits */ -#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH2] Bits */ -#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH3] Bits */ -#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH4] Bits */ -#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH5] Bits */ -#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH6] Bits */ -#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH7] Bits */ -#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH8] Bits */ -#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH9] Bits */ -#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH10] Bits */ -#define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH11] Bits */ -#define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH12] Bits */ -#define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH13] Bits */ -#define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH14] Bits */ -#define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH15] Bits */ -#define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH16] Bits */ -#define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH17] Bits */ -#define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH18] Bits */ -#define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH19] Bits */ -#define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH20] Bits */ -#define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH21] Bits */ -#define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH22] Bits */ -#define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH23] Bits */ -#define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH24] Bits */ -#define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH25] Bits */ -#define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH26] Bits */ -#define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH27] Bits */ -#define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH28] Bits */ -#define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH29] Bits */ -#define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH30] Bits */ -#define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH31] Bits */ -#define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ -/* DMA_INT0_CLRFLG[CH0] Bits */ -#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH1] Bits */ -#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH2] Bits */ -#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH3] Bits */ -#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH4] Bits */ -#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH5] Bits */ -#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH6] Bits */ -#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH7] Bits */ -#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH8] Bits */ -#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH9] Bits */ -#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH10] Bits */ -#define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH11] Bits */ -#define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH12] Bits */ -#define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH13] Bits */ -#define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH14] Bits */ -#define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH15] Bits */ -#define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH16] Bits */ -#define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH17] Bits */ -#define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH18] Bits */ -#define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH19] Bits */ -#define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH20] Bits */ -#define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH21] Bits */ -#define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH22] Bits */ -#define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH23] Bits */ -#define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH24] Bits */ -#define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH25] Bits */ -#define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH26] Bits */ -#define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH27] Bits */ -#define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH28] Bits */ -#define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH29] Bits */ -#define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH30] Bits */ -#define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH31] Bits */ -#define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_STAT[MASTEN] Bits */ -#define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_STAT_MASTEN ((uint32_t)0x00000001) -/* DMA_STAT[STATE] Bits */ -#define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ -#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ -#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ -#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ -#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ -#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ -#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ -#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ -#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ -#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ -#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ -#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ -#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ -#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ -#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ -#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ -#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ -#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ -#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ -#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ -#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ -#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ -/* DMA_STAT[DMACHANS] Bits */ -#define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ -#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ -#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ -#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ -#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ -#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ -#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ -#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ -#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ -#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ -#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ -/* DMA_STAT[TESTSTAT] Bits */ -#define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ -#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ -#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ -#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ -#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ -#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ -#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ -#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ -/* DMA_CFG[MASTEN] Bits */ -#define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_CFG_MASTEN ((uint32_t)0x00000001) -/* DMA_CFG[CHPROTCTRL] Bits */ -#define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ -#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ -/* DMA_CTLBASE[ADDR] Bits */ -#define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ -#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ -/* DMA_ERRCLR[ERRCLR] Bits */ -#define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ -#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) -/* DMA channel definitions and memory structure alignment */ -#define __MCU_NUM_DMA_CHANNELS__ 8 -#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 -#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) - -/* UDMA_STAT Control Bits */ -#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ -#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ -#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ -#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ -#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ -#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ -#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ -#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ -#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ -#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ -#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ -#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ -#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ -#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ -#define UDMA_STAT_DMACHANS_S (16) - -/* UDMA_CFG Control Bits */ -#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ - -/* UDMA_CTLBASE Control Bits */ -#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ -#define UDMA_CTLBASE_ADDR_S (10) - -/* UDMA_ALTBASE Control Bits */ -#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ -#define UDMA_ALTBASE_ADDR_S ( 0) - -/* UDMA_WAITSTAT Control Bits */ -#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ - -/* UDMA_SWREQ Control Bits */ -#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ - -/* UDMA_USEBURSTSET Control Bits */ -#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ - -/* UDMA_USEBURSTCLR Control Bits */ -#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ - -/* UDMA_REQMASKSET Control Bits */ -#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ - -/* UDMA_REQMASKCLR Control Bits */ -#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ - -/* UDMA_ENASET Control Bits */ -#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ - -/* UDMA_ENACLR Control Bits */ -#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ - -/* UDMA_ALTSET Control Bits */ -#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ - -/* UDMA_ALTCLR Control Bits */ -#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ - -/* UDMA_PRIOSET Control Bits */ -#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ - -/* UDMA_PRIOCLR Control Bits */ -#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ - -/* UDMA_ERRCLR Control Bits */ -#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ - -/* UDMA_CHASGN Control Bits */ -#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ -#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ -#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ - -/* Micro Direct Memory Access (uDMA) offsets */ -#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ -#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ -#define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ - -/* UDMA_O_SRCENDP Control Bits */ -#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ -#define UDMA_SRCENDP_ADDR_S ( 0) - -/* UDMA_O_DSTENDP Control Bits */ -#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ -#define UDMA_DSTENDP_ADDR_S ( 0) - -/* UDMA_O_CHCTL Control Bits */ -#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ -#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ -#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ -#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ -#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ -#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ -#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ -#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ -#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ -#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ -#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ -#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ -#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ -#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ -#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ -#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ -#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ -#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ -#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ -#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ -#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ -#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ -#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ -#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ -#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ -#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ -#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ -#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ - -#define UDMA_CHCTL_XFERSIZE_S ( 4) - - -/****************************************************************************** -* DWT Bits -******************************************************************************/ - - -/****************************************************************************** -* EUSCI_A Bits -******************************************************************************/ -/* EUSCI_A_CTLW0[SWRST] Bits */ -#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_A_CTLW0[TXBRK] Bits */ -#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ -#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ -/* EUSCI_A_CTLW0[TXADDR] Bits */ -#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ -#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ -/* EUSCI_A_CTLW0[DORM] Bits */ -#define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ -#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ -/* EUSCI_A_CTLW0[BRKIE] Bits */ -#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ -#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ -/* EUSCI_A_CTLW0[RXEIE] Bits */ -#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ -#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ -/* EUSCI_A_CTLW0[SSEL] Bits */ -#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_A_CTLW0[SYNC] Bits */ -#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_A_CTLW0[MODE] Bits */ -#define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ -#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ -/* EUSCI_A_CTLW0[SPB] Bits */ -#define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ -#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ -/* EUSCI_A_CTLW0[SEVENBIT] Bits */ -#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_A_CTLW0[MSB] Bits */ -#define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_A_CTLW0[PAR] Bits */ -#define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ -#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ -/* EUSCI_A_CTLW0[PEN] Bits */ -#define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ -#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ -/* EUSCI_A_CTLW0[STEM] Bits */ -#define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_A_CTLW0[MST] Bits */ -#define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_A_CTLW0[CKPL] Bits */ -#define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_A_CTLW0[CKPH] Bits */ -#define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_A_CTLW1[GLIT] Bits */ -#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ -#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ -#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ -/* EUSCI_A_MCTLW[OS16] Bits */ -#define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ -#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ -/* EUSCI_A_MCTLW[BRF] Bits */ -#define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ -#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ -/* EUSCI_A_MCTLW[BRS] Bits */ -#define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ -#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ -/* EUSCI_A_STATW[BUSY] Bits */ -#define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_STATW[ADDR_IDLE] Bits */ -#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ -#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ -/* EUSCI_A_STATW[RXERR] Bits */ -#define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ -#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ -/* EUSCI_A_STATW[BRK] Bits */ -#define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ -#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ -/* EUSCI_A_STATW[PE] Bits */ -#define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ -#define EUSCI_A_STATW_PE ((uint16_t)0x0010) -/* EUSCI_A_STATW[OE] Bits */ -#define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_A_STATW[FE] Bits */ -#define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_A_STATW[LISTEN] Bits */ -#define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_A_STATW[SPI_BUSY] Bits */ -#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_RXBUF[RXBUF] Bits */ -#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_A_TXBUF[TXBUF] Bits */ -#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_A_ABCTL[ABDEN] Bits */ -#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ -#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ -/* EUSCI_A_ABCTL[BTOE] Bits */ -#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ -#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ -/* EUSCI_A_ABCTL[STOE] Bits */ -#define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ -#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ -/* EUSCI_A_ABCTL[DELIM] Bits */ -#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ -#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ -#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ -#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ -#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ -#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ -#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ -#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ -/* EUSCI_A_IRCTL[IREN] Bits */ -#define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ -#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ -/* EUSCI_A_IRCTL[IRTXCLK] Bits */ -#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ -#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ -/* EUSCI_A_IRCTL[IRTXPL] Bits */ -#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ -/* EUSCI_A_IRCTL[IRRXFE] Bits */ -#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ -/* EUSCI_A_IRCTL[IRRXPL] Bits */ -#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ -/* EUSCI_A_IRCTL[IRRXFL] Bits */ -#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ -/* EUSCI_A_IE[RXIE] Bits */ -#define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_A_IE[TXIE] Bits */ -#define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_A_IE[STTIE] Bits */ -#define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ -/* EUSCI_A_IE[TXCPTIE] Bits */ -#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ -#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ -/* EUSCI_A_IFG[RXIFG] Bits */ -#define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_A_IFG[TXIFG] Bits */ -#define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* EUSCI_A_IFG[STTIFG] Bits */ -#define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ -/* EUSCI_A_IFG[TXCPTIFG] Bits */ -#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ -#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* EUSCI_B Bits -******************************************************************************/ -/* EUSCI_B_CTLW0[SWRST] Bits */ -#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_B_CTLW0[TXSTT] Bits */ -#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ -#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ -/* EUSCI_B_CTLW0[TXSTP] Bits */ -#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ -#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ -/* EUSCI_B_CTLW0[TXNACK] Bits */ -#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ -#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ -/* EUSCI_B_CTLW0[TR] Bits */ -#define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ -#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ -/* EUSCI_B_CTLW0[TXACK] Bits */ -#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ -#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ -/* EUSCI_B_CTLW0[SSEL] Bits */ -#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ -#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_B_CTLW0[SYNC] Bits */ -#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_B_CTLW0[MODE] Bits */ -#define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ -#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ -/* EUSCI_B_CTLW0[MST] Bits */ -#define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_B_CTLW0[MM] Bits */ -#define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ -#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ -/* EUSCI_B_CTLW0[SLA10] Bits */ -#define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ -#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ -/* EUSCI_B_CTLW0[A10] Bits */ -#define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ -#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ -/* EUSCI_B_CTLW0[STEM] Bits */ -#define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_B_CTLW0[SEVENBIT] Bits */ -#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_B_CTLW0[MSB] Bits */ -#define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_B_CTLW0[CKPL] Bits */ -#define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_B_CTLW0[CKPH] Bits */ -#define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_B_CTLW1[GLIT] Bits */ -#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ -#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ -#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ -#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ -/* EUSCI_B_CTLW1[ASTP] Bits */ -#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ -#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ -#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ -#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ -#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* EUSCI_B_CTLW1[SWACK] Bits */ -#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ -#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ -/* EUSCI_B_CTLW1[STPNACK] Bits */ -#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ -#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ -/* EUSCI_B_CTLW1[CLTO] Bits */ -#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ -#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ -#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ -#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ -#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ -#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* EUSCI_B_CTLW1[ETXINT] Bits */ -#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ -#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ -/* EUSCI_B_STATW[BBUSY] Bits */ -#define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ -#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ -/* EUSCI_B_STATW[GC] Bits */ -#define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ -#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ -/* EUSCI_B_STATW[SCLLOW] Bits */ -#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ -#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ -/* EUSCI_B_STATW[BCNT] Bits */ -#define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ -#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ -/* EUSCI_B_STATW[SPI_BUSY] Bits */ -#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ -/* EUSCI_B_STATW[OE] Bits */ -#define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_B_STATW[FE] Bits */ -#define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_B_STATW[LISTEN] Bits */ -#define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_B_TBCNT[TBCNT] Bits */ -#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ -#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ -/* EUSCI_B_RXBUF[RXBUF] Bits */ -#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_B_TXBUF[TXBUF] Bits */ -#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_B_I2COA0[I2COA0] Bits */ -#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ -#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ -/* EUSCI_B_I2COA0[OAEN] Bits */ -#define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA0[GCEN] Bits */ -#define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ -#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ -/* EUSCI_B_I2COA1[I2COA1] Bits */ -#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ -#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ -/* EUSCI_B_I2COA1[OAEN] Bits */ -#define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA2[I2COA2] Bits */ -#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ -#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ -/* EUSCI_B_I2COA2[OAEN] Bits */ -#define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA3[I2COA3] Bits */ -#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ -#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ -/* EUSCI_B_I2COA3[OAEN] Bits */ -#define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_ADDRX[ADDRX] Bits */ -#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ -#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ -#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ -#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ -#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ -#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ -#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ -#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ -#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ -#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ -#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ -#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ -/* EUSCI_B_ADDMASK[ADDMASK] Bits */ -#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ -#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ -/* EUSCI_B_I2CSA[I2CSA] Bits */ -#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ -#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ -/* EUSCI_B_IE[RXIE0] Bits */ -#define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ -#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ -/* EUSCI_B_IE[TXIE0] Bits */ -#define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ -#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ -/* EUSCI_B_IE[STTIE] Bits */ -#define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ -/* EUSCI_B_IE[STPIE] Bits */ -#define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ -#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ -/* EUSCI_B_IE[ALIE] Bits */ -#define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ -#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ -/* EUSCI_B_IE[NACKIE] Bits */ -#define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ -#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ -/* EUSCI_B_IE[BCNTIE] Bits */ -#define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ -#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ -/* EUSCI_B_IE[CLTOIE] Bits */ -#define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ -#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ -/* EUSCI_B_IE[RXIE1] Bits */ -#define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ -#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ -/* EUSCI_B_IE[TXIE1] Bits */ -#define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ -#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ -/* EUSCI_B_IE[RXIE2] Bits */ -#define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ -#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ -/* EUSCI_B_IE[TXIE2] Bits */ -#define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ -#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ -/* EUSCI_B_IE[RXIE3] Bits */ -#define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ -#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ -/* EUSCI_B_IE[TXIE3] Bits */ -#define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ -#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ -/* EUSCI_B_IE[BIT9IE] Bits */ -#define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ -#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ -/* EUSCI_B_IE[RXIE] Bits */ -#define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_B_IE[TXIE] Bits */ -#define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_B_IFG[RXIFG0] Bits */ -#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ -#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ -/* EUSCI_B_IFG[TXIFG0] Bits */ -#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ -#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ -/* EUSCI_B_IFG[STTIFG] Bits */ -#define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ -/* EUSCI_B_IFG[STPIFG] Bits */ -#define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ -#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ -/* EUSCI_B_IFG[ALIFG] Bits */ -#define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ -#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ -/* EUSCI_B_IFG[NACKIFG] Bits */ -#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ -#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ -/* EUSCI_B_IFG[BCNTIFG] Bits */ -#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ -#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ -/* EUSCI_B_IFG[CLTOIFG] Bits */ -#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ -#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ -/* EUSCI_B_IFG[RXIFG1] Bits */ -#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ -#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ -/* EUSCI_B_IFG[TXIFG1] Bits */ -#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ -#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ -/* EUSCI_B_IFG[RXIFG2] Bits */ -#define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ -#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ -/* EUSCI_B_IFG[TXIFG2] Bits */ -#define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ -#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ -/* EUSCI_B_IFG[RXIFG3] Bits */ -#define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ -#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ -/* EUSCI_B_IFG[TXIFG3] Bits */ -#define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ -#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ -/* EUSCI_B_IFG[BIT9IFG] Bits */ -#define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ -#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ -/* EUSCI_B_IFG[RXIFG] Bits */ -#define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_B_IFG[TXIFG] Bits */ -#define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* FLCTL Bits -******************************************************************************/ -/* FLCTL_POWER_STAT[PSTAT] Bits */ -#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ -#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ -#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ -#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ -#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ -#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ -#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ -#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ -#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ -#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ -#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ -#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ -#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ -/* FLCTL_POWER_STAT[LDOSTAT] Bits */ -#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ -#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ -/* FLCTL_POWER_STAT[VREFSTAT] Bits */ -#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ -#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ -/* FLCTL_POWER_STAT[IREFSTAT] Bits */ -#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ -#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ -/* FLCTL_POWER_STAT[TRIMSTAT] Bits */ -#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ -#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ -/* FLCTL_POWER_STAT[RD_2T] Bits */ -#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ -#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ -/* FLCTL_BANK0_RDCTL[RD_MODE] Bits */ -#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_BANK0_RDCTL[BUFI] Bits */ -#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_BANK0_RDCTL[BUFD] Bits */ -#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_BANK0_RDCTL[WAIT] Bits */ -#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[RD_MODE] Bits */ -#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[BUFI] Bits */ -#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_BANK1_RDCTL[BUFD] Bits */ -#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[WAIT] Bits */ -#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_RDBRST_CTLSTAT[START] Bits */ -#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ -/* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */ -#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ -/* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */ -#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ -/* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */ -#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ -/* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */ -#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ -/* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ -/* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ -/* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */ -#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ -#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ -/* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ -#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ -#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ -/* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */ -#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ -#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ -/* FLCTL_PRG_CTLSTAT[ENABLE] Bits */ -#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ -/* FLCTL_PRG_CTLSTAT[MODE] Bits */ -#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ -/* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */ -#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ -/* FLCTL_PRG_CTLSTAT[VER_PST] Bits */ -#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ -#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ -/* FLCTL_PRG_CTLSTAT[STATUS] Bits */ -#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ -#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ -#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ -/* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */ -#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ -#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ -/* FLCTL_PRGBRST_CTLSTAT[START] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ -/* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ - /* FLCTL_PRGBRST_STARTADDR Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -/* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ -/* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ -/* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ -/* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ -/* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ -/* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ -/* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_ERASE_CTLSTAT[START] Bits */ -#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ -/* FLCTL_ERASE_CTLSTAT[MODE] Bits */ -#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ -/* FLCTL_ERASE_CTLSTAT[TYPE] Bits */ -#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ -#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ -#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ -#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ -#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ -/* FLCTL_ERASE_CTLSTAT[STATUS] Bits */ -#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ -#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ -#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ - /* unless explicitly cleared by SW) */ -/* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ - /* address */ -/* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ -/* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */ -#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ -#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ -/* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ -/* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */ -#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) -/* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */ -#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) -/* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */ -#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) -/* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */ -#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) -/* FLCTL_IFG[RDBRST] Bits */ -#define FLCTL_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_IFG[AVPRE] Bits */ -#define FLCTL_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_IFG[AVPST] Bits */ -#define FLCTL_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_IFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_IFG[PRG] Bits */ -#define FLCTL_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_IFG_PRG ((uint32_t)0x00000008) -/* FLCTL_IFG[PRGB] Bits */ -#define FLCTL_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_IFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_IFG[ERASE] Bits */ -#define FLCTL_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_IFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_IFG[BMRK] Bits */ -#define FLCTL_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_IFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_IFG[PRG_ERR] Bits */ -#define FLCTL_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_IE[RDBRST] Bits */ -#define FLCTL_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_IE_RDBRST ((uint32_t)0x00000001) -/* FLCTL_IE[AVPRE] Bits */ -#define FLCTL_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_IE_AVPRE ((uint32_t)0x00000002) -/* FLCTL_IE[AVPST] Bits */ -#define FLCTL_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_IE_AVPST ((uint32_t)0x00000004) -/* FLCTL_IE[PRG] Bits */ -#define FLCTL_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_IE_PRG ((uint32_t)0x00000008) -/* FLCTL_IE[PRGB] Bits */ -#define FLCTL_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_IE_PRGB ((uint32_t)0x00000010) -/* FLCTL_IE[ERASE] Bits */ -#define FLCTL_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_IE_ERASE ((uint32_t)0x00000020) -/* FLCTL_IE[BMRK] Bits */ -#define FLCTL_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_IE_BMRK ((uint32_t)0x00000100) -/* FLCTL_IE[PRG_ERR] Bits */ -#define FLCTL_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_CLRIFG[RDBRST] Bits */ -#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_CLRIFG[AVPRE] Bits */ -#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_CLRIFG[AVPST] Bits */ -#define FLCTL_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_CLRIFG[PRG] Bits */ -#define FLCTL_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_CLRIFG[PRGB] Bits */ -#define FLCTL_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_CLRIFG[ERASE] Bits */ -#define FLCTL_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_CLRIFG[BMRK] Bits */ -#define FLCTL_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_CLRIFG[PRG_ERR] Bits */ -#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_SETIFG[RDBRST] Bits */ -#define FLCTL_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_SETIFG[AVPRE] Bits */ -#define FLCTL_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_SETIFG[AVPST] Bits */ -#define FLCTL_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_SETIFG[PRG] Bits */ -#define FLCTL_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_SETIFG[PRGB] Bits */ -#define FLCTL_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_SETIFG[ERASE] Bits */ -#define FLCTL_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_SETIFG[BMRK] Bits */ -#define FLCTL_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_SETIFG[PRG_ERR] Bits */ -#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_READ_TIMCTL[SETUP] Bits */ -#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */ -#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ -#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ -/* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */ -#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ -#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ -/* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */ -#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */ -#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[HOLD] Bits */ -#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ -/* FLCTL_ERSVER_TIMCTL[SETUP] Bits */ -#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_LKGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */ -#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */ -#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */ -#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_ERASE_TIMCTL[SETUP] Bits */ -#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */ -#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_ERASE_TIMCTL[HOLD] Bits */ -#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ -/* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ -/* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */ -#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Bits -******************************************************************************/ - -/****************************************************************************** -* FPB Bits -******************************************************************************/ - - -/****************************************************************************** -* FPU Bits -******************************************************************************/ - - -/****************************************************************************** -* ITM Bits -******************************************************************************/ - - -/****************************************************************************** -* MPU Bits -******************************************************************************/ - -/* Pre-defined bitfield values */ - -/* MPU_RASR_SIZE Bitfield Bits */ -#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ -#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ -#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ -#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ -#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ -#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ -#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ -#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ -#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ -#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ -#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ -#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ -#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ -#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ -#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ -#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ -#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ -#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ -#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ -#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ -#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ -#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ -#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ -#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ -#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ -#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ -#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ -#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ - -/* MPU_RASR_AP Bitfield Bits */ -#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ -#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ -#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ - -/* MPU_RASR_XN Bitfield Bits */ -#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ -#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ - - -/****************************************************************************** -* NVIC Bits -******************************************************************************/ - -/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ -#define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ -#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ -#define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ -#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ -#define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ -#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ -#define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ -#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ -#define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ -#define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ -#define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ -#define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ -#define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ -#define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ -#define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ -#define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ -#define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ -#define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ -#define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ -#define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ -#define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ -#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ -#define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ -#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ -#define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ -#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ -#define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ -#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ -#define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ -#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ -#define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ -#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ -#define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ -#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ -#define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ -#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ -#define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ -#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ -#define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ -#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ -#define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ -#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ -#define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ -#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ -#define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ -#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ -#define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ -#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ -#define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ -#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ -#define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ -#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ -#define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ -#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ -#define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ -#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ -#define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ -#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ -#define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ -#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ -#define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ -#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ -#define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ -#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ -#define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ -#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ -#define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ -#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ -#define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ -#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ -#define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ -#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ -#define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ -#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ -#define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ -#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ -#define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ -#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ -#define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ -#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ -#define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ -#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ -#define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ -#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ -#define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ -#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ -#define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ -#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ -#define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ -#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ -#define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ -#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ -#define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ -#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ -#define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ -#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ -#define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ -#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ -#define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ -#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ -#define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ -#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ -#define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ -#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ -#define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ -#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ -#define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ -#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ -#define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ -#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ -#define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ -#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ -#define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ -#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ -#define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ -#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ - - -/****************************************************************************** -* PCM Bits -******************************************************************************/ -/* PCM_CTL0[AMR] Bits */ -#define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ -#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ -#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ -#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ -#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ -#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ -#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -/* PCM_CTL0[LPMR] Bits */ -#define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ -#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ -#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ -#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ -#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ -#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ -#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -/* PCM_CTL0[CPM] Bits */ -#define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ -#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ -#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ -#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ -#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ -#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ -#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ -#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ -#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ -#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ -/* PCM_CTL0[KEY] Bits */ -#define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_CTL1[LOCKLPM5] Bits */ -#define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ -#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ -/* PCM_CTL1[LOCKBKUP] Bits */ -#define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ -#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ -/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ -#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ -#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ -/* PCM_CTL1[PMR_BUSY] Bits */ -#define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ -#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ -/* PCM_CTL1[KEY] Bits */ -#define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_IE[LPM_INVALID_TR_IE] Bits */ -#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ -/* PCM_IE[LPM_INVALID_CLK_IE] Bits */ -#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ -/* PCM_IE[AM_INVALID_TR_IE] Bits */ -#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ -/* PCM_IE[DCDC_ERROR_IE] Bits */ -#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ -#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ -/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ -/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ -/* PCM_IFG[AM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ -/* PCM_IFG[DCDC_ERROR_IFG] Bits */ -#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ -#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ -/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ -/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ -/* Pre-defined bitfield values */ -#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ -#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ - - -/****************************************************************************** -* PMAP Bits -******************************************************************************/ -/* PMAP_CTL[LOCKED] Bits */ -#define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ -#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ -/* PMAP_CTL[PRECFG] Bits */ -#define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ -#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -#define PMAP_NONE 0 -#define PMAP_UCA0CLK 1 -#define PMAP_UCA0RXD 2 -#define PMAP_UCA0SOMI 2 -#define PMAP_UCA0TXD 3 -#define PMAP_UCA0SIMO 3 -#define PMAP_UCB0CLK 4 -#define PMAP_UCB0SDA 5 -#define PMAP_UCB0SIMO 5 -#define PMAP_UCB0SCL 6 -#define PMAP_UCB0SOMI 6 -#define PMAP_UCA1STE 7 -#define PMAP_UCA1CLK 8 -#define PMAP_UCA1RXD 9 -#define PMAP_UCA1SOMI 9 -#define PMAP_UCA1TXD 10 -#define PMAP_UCA1SIMO 10 -#define PMAP_UCA2STE 11 -#define PMAP_UCA2CLK 12 -#define PMAP_UCA2RXD 13 -#define PMAP_UCA2SOMI 13 -#define PMAP_UCA2TXD 14 -#define PMAP_UCA2SIMO 14 -#define PMAP_UCB2STE 15 -#define PMAP_UCB2CLK 16 -#define PMAP_UCB2SDA 17 -#define PMAP_UCB2SIMO 17 -#define PMAP_UCB2SCL 18 -#define PMAP_UCB2SOMI 18 -#define PMAP_TA0CCR0A 19 -#define PMAP_TA0CCR1A 20 -#define PMAP_TA0CCR2A 21 -#define PMAP_TA0CCR3A 22 -#define PMAP_TA0CCR4A 23 -#define PMAP_TA1CCR1A 24 -#define PMAP_TA1CCR2A 25 -#define PMAP_TA1CCR3A 26 -#define PMAP_TA1CCR4A 27 -#define PMAP_TA0CLK 28 -#define PMAP_CE0OUT 28 -#define PMAP_TA1CLK 29 -#define PMAP_CE1OUT 29 -#define PMAP_DMAE0 30 -#define PMAP_SMCLK 30 -#define PMAP_ANALOG 31 - -#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ - - -/****************************************************************************** -* PSS Bits -******************************************************************************/ -/* PSS_KEY[KEY] Bits */ -#define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ -#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ -/* PSS_CTL0[SVSMHOFF] Bits */ -#define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ -#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ -/* PSS_CTL0[SVSMHLP] Bits */ -#define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ -#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ -/* PSS_CTL0[SVSMHS] Bits */ -#define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ -#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ -/* PSS_CTL0[SVSMHTH] Bits */ -#define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ -#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ -/* PSS_CTL0[SVMHOE] Bits */ -#define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ -#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ -/* PSS_CTL0[SVMHOUTPOLAL] Bits */ -#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ -#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ -/* PSS_CTL0[DCDC_FORCE] Bits */ -#define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ -#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ -/* PSS_CTL0[VCORETRAN] Bits */ -#define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ -#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ -#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ -#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ -#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -/* PSS_IE[SVSMHIE] Bits */ -#define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ -#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ -/* PSS_IFG[SVSMHIFG] Bits */ -#define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ -#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ -/* PSS_CLRIFG[CLRSVSMHIFG] Bits */ -#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ -#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ -/* Pre-defined bitfield values */ -#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ - - -/****************************************************************************** -* REF_A Bits -******************************************************************************/ -/* REF_A_CTL0[ON] Bits */ -#define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ -#define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ -/* REF_A_CTL0[OUT] Bits */ -#define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ -#define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ -/* REF_A_CTL0[TCOFF] Bits */ -#define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ -#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ -/* REF_A_CTL0[VSEL] Bits */ -#define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ -#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ -#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ -#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ -#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REF_A_CTL0[GENOT] Bits */ -#define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ -#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ -/* REF_A_CTL0[BGOT] Bits */ -#define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ -#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ -/* REF_A_CTL0[GENACT] Bits */ -#define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ -#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ -/* REF_A_CTL0[BGACT] Bits */ -#define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ -#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ -/* REF_A_CTL0[GENBUSY] Bits */ -#define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ -#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ -/* REF_A_CTL0[BGMODE] Bits */ -#define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ -#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ -/* REF_A_CTL0[GENRDY] Bits */ -#define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ -#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ -/* REF_A_CTL0[BGRDY] Bits */ -#define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ -#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RSTCTL Bits -******************************************************************************/ -/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ -#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ -/* RSTCTL_RESET_REQ[HARD_REQ] Bits */ -#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ -/* RSTCTL_RESET_REQ[RSTKEY] Bits */ -#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ -#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ -/* RSTCTL_HARDRESET_STAT[SRC0] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC1] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC2] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC3] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC4] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC5] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC6] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC7] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC8] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC9] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC10] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC11] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC12] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC13] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC14] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC15] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_CLR[SRC0] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC1] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC2] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC3] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC4] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC5] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC6] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC7] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC8] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC9] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC10] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC11] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC12] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC13] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC14] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC15] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ -/* RSTCTL_HARDRESET_SET[SRC0] Bits */ -#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC1] Bits */ -#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC2] Bits */ -#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC3] Bits */ -#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC4] Bits */ -#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC5] Bits */ -#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC6] Bits */ -#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC7] Bits */ -#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC8] Bits */ -#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC9] Bits */ -#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC10] Bits */ -#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC11] Bits */ -#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC12] Bits */ -#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC13] Bits */ -#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC14] Bits */ -#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC15] Bits */ -#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_SET[SRC0] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC1] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC2] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC3] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC4] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC5] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC6] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC7] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC8] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC9] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC10] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC11] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC12] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC13] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC14] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC15] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ -#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ -/* RSTCTL_PSSRESET_STAT[BGREF] Bits */ -#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ -#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ -/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ -#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ -#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ -/* RSTCTL_PSSRESET_CLR[CLR] Bits */ -#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ -/* RSTCTL_PCMRESET_STAT[LPM35] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ -/* RSTCTL_PCMRESET_STAT[LPM45] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ -/* RSTCTL_PCMRESET_CLR[CLR] Bits */ -#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ -/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ -#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ -#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ -/* RSTCTL_PINRESET_CLR[CLR] Bits */ -#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ -/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ -/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ -#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ -/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ - /* resistor mode */ -/* RSTCTL_CSRESET_CLR[CLR] Bits */ -#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ - /* DCOR_SHTIFG flag in CSIFG register of clock system */ -/* Pre-defined bitfield values */ -#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ - - -/****************************************************************************** -* RTC_C Bits -******************************************************************************/ -/* RTC_C_CTL0[RDYIFG] Bits */ -#define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ -#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ -/* RTC_C_CTL0[AIFG] Bits */ -#define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ -#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ -/* RTC_C_CTL0[TEVIFG] Bits */ -#define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ -#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ -/* RTC_C_CTL0[OFIFG] Bits */ -#define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ -#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTC_C_CTL0[RDYIE] Bits */ -#define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ -#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ -/* RTC_C_CTL0[AIE] Bits */ -#define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ -#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ -/* RTC_C_CTL0[TEVIE] Bits */ -#define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ -#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ -/* RTC_C_CTL0[OFIE] Bits */ -#define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ -#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTC_C_CTL0[KEY] Bits */ -#define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ -#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ -/* RTC_C_CTL13[TEV] Bits */ -#define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ -#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ -#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ -#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ -#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ -#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ -#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ -#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ -/* RTC_C_CTL13[SSEL] Bits */ -#define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ -#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ -#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ -#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ -#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ -#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ -/* RTC_C_CTL13[RDY] Bits */ -#define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ -#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ -/* RTC_C_CTL13[MODE] Bits */ -#define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ -#define RTC_C_CTL13_MODE ((uint16_t)0x0020) -/* RTC_C_CTL13[HOLD] Bits */ -#define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ -#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ -/* RTC_C_CTL13[BCD] Bits */ -#define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ -#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ -/* RTC_C_CTL13[CALF] Bits */ -#define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ -#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ -#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ -#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ -#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ -#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ -/* RTC_C_OCAL[OCAL] Bits */ -#define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ -#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ -/* RTC_C_OCAL[OCALS] Bits */ -#define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ -#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ -/* RTC_C_TCMP[TCMPx] Bits */ -#define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ -#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ -/* RTC_C_TCMP[TCOK] Bits */ -#define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ -#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ -/* RTC_C_TCMP[TCRDY] Bits */ -#define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ -#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ -/* RTC_C_TCMP[TCMPS] Bits */ -#define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ -#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ -/* RTC_C_PS0CTL[RT0PSIFG] Bits */ -#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ -/* RTC_C_PS0CTL[RT0PSIE] Bits */ -#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ -/* RTC_C_PS0CTL[RT0IP] Bits */ -#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ -#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ -#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ -#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ -#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ -#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS1CTL[RT1PSIFG] Bits */ -#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ -/* RTC_C_PS1CTL[RT1PSIE] Bits */ -#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ -/* RTC_C_PS1CTL[RT1IP] Bits */ -#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ -#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ -#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ -#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ -#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ -#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS[RT0PS] Bits */ -#define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ -#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ -/* RTC_C_PS[RT1PS] Bits */ -#define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ -#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ -/* RTC_C_TIM0[SEC] Bits */ -#define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ -#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ -/* RTC_C_TIM0[MIN] Bits */ -#define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ -#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ -/* RTC_C_TIM0[SEC_LD] Bits */ -#define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ -#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ -/* RTC_C_TIM0[SEC_HD] Bits */ -#define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ -#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ -/* RTC_C_TIM0[MIN_LD] Bits */ -#define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_TIM0[MIN_HD] Bits */ -#define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_TIM1[HOUR] Bits */ -#define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ -#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ -/* RTC_C_TIM1[DOW] Bits */ -#define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ -#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ -/* RTC_C_TIM1[HOUR_LD] Bits */ -#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_TIM1[HOUR_HD] Bits */ -#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_DATE[DAY] Bits */ -#define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ -#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ -/* RTC_C_DATE[MON] Bits */ -#define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ -#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ -/* RTC_C_DATE[DAY_LD] Bits */ -#define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ -#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ -/* RTC_C_DATE[DAY_HD] Bits */ -#define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ -#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ -/* RTC_C_DATE[MON_LD] Bits */ -#define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ -#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ -/* RTC_C_DATE[MON_HD] Bits */ -#define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ -#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ -/* RTC_C_YEAR[YEAR_LB] Bits */ -#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ -#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ -/* RTC_C_YEAR[YEAR_HB] Bits */ -#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ -#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ -/* RTC_C_YEAR[YEAR] Bits */ -#define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ -#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ -/* RTC_C_YEAR[DEC] Bits */ -#define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ -#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ -/* RTC_C_YEAR[CENT_LD] Bits */ -#define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ -#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ -/* RTC_C_YEAR[CENT_HD] Bits */ -#define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ -#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ -/* RTC_C_AMINHR[MIN] Bits */ -#define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ -#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ -/* RTC_C_AMINHR[MINAE] Bits */ -#define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ -#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_AMINHR[HOUR] Bits */ -#define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ -#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ -/* RTC_C_AMINHR[HOURAE] Bits */ -#define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ -#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_AMINHR[MIN_LD] Bits */ -#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_AMINHR[MIN_HD] Bits */ -#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_LD] Bits */ -#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_HD] Bits */ -#define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_ADOWDAY[DOW] Bits */ -#define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ -#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ -/* RTC_C_ADOWDAY[DOWAE] Bits */ -#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ -#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY] Bits */ -#define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ -#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ -/* RTC_C_ADOWDAY[DAYAE] Bits */ -#define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ -#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY_LD] Bits */ -#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ -/* RTC_C_ADOWDAY[DAY_HD] Bits */ -#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ -/* Pre-defined bitfield values */ -#define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* SCB Bits -******************************************************************************/ -/* SCB_PFR0[STATE0] Bits */ -#define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ -#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ -#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ -#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ -#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ -#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ -#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ -#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_PFR0[STATE1] Bits */ -#define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ -#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ -#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ -#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ -#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ -#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ -#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ -#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ -#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ - /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ - /* can be added using the appropriate instruction attribute, but other 32-bit */ - /* basic instructions cannot.) */ -#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ -/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ -/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ -/* SCB_MMFR0[PMSA_SUPPORT] Bits */ -#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ -#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ -#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ -#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ -#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ -#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ -#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ -/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ - /* the entities within an inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ - /* inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ -/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ -/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ -/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ -/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ -#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ -#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ -#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ -#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ -#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ -#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ -#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ -#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ -/* SCB_ISAR0[BITFIELD_INSTRS] Bits */ -#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ -#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ -#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ -#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ -#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ -#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ -#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ -#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ -/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ -/* SCB_ISAR0[COPROC_INSTRS] Bits */ -#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ -#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ -#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ -#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ -#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ -#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ -#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ - /* such as CP15 or VFP */ -#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ -#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ -#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ -#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ -/* SCB_ISAR0[DEBUG_INSTRS] Bits */ -#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ -#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ -#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ -#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ -#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ -#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ -#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ -#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ -/* SCB_ISAR0[DIVIDE_INSTRS] Bits */ -#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ -#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ -#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ -#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ -#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ -#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ -#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ -#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ -/* SCB_ISAR1[ETEND_INSRS] Bits */ -#define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ -#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ -#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ -#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ -#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ -#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ -#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ -#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ -#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ -/* SCB_ISAR1[IFTHEN_INSTRS] Bits */ -#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ -#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ -#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ -#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ -#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ -#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ -#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ -#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ -/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ -#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ -/* SCB_ISAR1[INTERWORK_INSTRS] Bits */ -#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ -#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ -#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ -#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ -#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ -#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ -#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ -#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ -#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ -#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ -/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ -#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ -#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ -#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ -#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ -#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ -#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ -#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ -#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ -/* SCB_ISAR2[MEMHINT_INSTRS] Bits */ -#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ -#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ -#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ -#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ -/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ -/* SCB_ISAR2[MULT_INSTRS] Bits */ -#define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ -#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ -#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ -/* SCB_ISAR2[MULTS_INSTRS] Bits */ -#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ -#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ -#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ -#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ -/* SCB_ISAR2[MULTU_INSTRS] Bits */ -#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ -#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ -#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ -/* SCB_ISAR2[REVERSAL_INSTRS] Bits */ -#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ -#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ -#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ -#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ -#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ -#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ -#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ -#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ -#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ -/* SCB_ISAR3[SATRUATE_INSTRS] Bits */ -#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ -#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ -#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ -#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ -#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ -#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ -#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ -#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_ISAR3[SIMD_INSTRS] Bits */ -#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ -#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ -#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ -#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ -#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ -#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ -#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ -#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ -#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ -/* SCB_ISAR3[SVC_INSTRS] Bits */ -#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ -#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ -#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ -#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ -#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ -#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ -#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ -#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ -/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ -#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ -/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ -#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ -#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ -/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ -#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ -/* SCB_ISAR3[TRUENOP_INSTRS] Bits */ -#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ -#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ -#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ -#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ -#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ -#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ -#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ - /* register dependencies */ -#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ -/* SCB_ISAR4[UNPRIV_INSTRS] Bits */ -#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ -#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ -#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ -#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ -#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ -#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ -#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ -#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ -#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ -/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ -/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ -#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ -#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ -#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ -#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ -#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ -#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ -#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ - /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ -#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ -/* SCB_ISAR4[BARRIER_INSTRS] Bits */ -#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ -#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ -#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ -#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ -#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ -#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ -#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ -#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ -/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ -/* SCB_ISAR4[PSR_M_INSTRS] Bits */ -#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ -#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ -#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ -#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ -#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ -#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ -#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ -#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ -/* SCB_CPACR[CP11] Bits */ -#define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ -#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ -/* SCB_CPACR[CP10] Bits */ -#define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ -#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ -/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ -#define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ -#define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ -#define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ -#define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ -#define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ -#define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ -#define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ -#define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ -#define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ -#define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ -#define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ -#define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ - -/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ -#define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ -/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ -#define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ -/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ -#define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ -/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ -#define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ -/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ -#define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ -/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ -#define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ -/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ -#define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ -/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ -#define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ -/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ -#define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ -/* SCB_CFSR[SCB_CFSR_STKERR] Bits */ -#define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ -/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ -#define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ -/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ -#define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ -/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ -#define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ -/* SCB_CFSR[SCB_CFSR_INVPC] Bits */ -#define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ -/* SCB_CFSR[SCB_CFSR_NOCP] Bits */ -#define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ -/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ -#define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ -/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ -#define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ -/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ -#define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ -#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ -/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ -#define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ -#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ - - -/****************************************************************************** -* SCNSCB Bits -******************************************************************************/ - - -/****************************************************************************** -* SYSCTL Bits -******************************************************************************/ -/* SYSCTL_REBOOT_CTL[REBOOT] Bits */ -#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ -/* SYSCTL_REBOOT_CTL[WKEY] Bits */ -#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) -/* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ -/* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */ -#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ -#define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ -/* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */ -#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ -#define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /*!< SRAM Bank0 enable */ -/* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */ -#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ -#define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ -/* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /*!< BNK0_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /*!< Bank0 retention */ -/* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /*!< BNK1_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /*!< Bank1 retention */ -/* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /*!< BNK2_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /*!< Bank2 retention */ -/* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /*!< BNK3_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /*!< Bank3 retention */ -/* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /*!< BNK4_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /*!< Bank4 retention */ -/* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /*!< BNK5_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /*!< Bank5 retention */ -/* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /*!< BNK6_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /*!< Bank6 retention */ -/* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /*!< BNK7_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /*!< Bank7 retention */ -/* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */ -#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ -#define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ -/* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ -#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ -#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ -/* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_RESET_REQ[POR] Bits */ -#define SYSCTL_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ -#define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ -/* SYSCTL_RESET_REQ[REBOOT] Bits */ -#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ -#define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ -/* SYSCTL_RESET_REQ[WKEY] Bits */ -#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_RESET_STATOVER[SOFT] Bits */ -#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ -#define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ -/* SYSCTL_RESET_STATOVER[HARD] Bits */ -#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ -#define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ -/* SYSCTL_RESET_STATOVER[REBOOT] Bits */ -#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ -#define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ -/* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ -/* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ -/* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ -/* Pre-defined bitfield values */ -#define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bit 0 */ - /* cleared */ - - -/****************************************************************************** -* SYSTICK Bits -******************************************************************************/ - -/****************************************************************************** -* Timer32 Bits -******************************************************************************/ -/* TIMER32_CONTROL[ONESHOT] Bits */ -#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ -#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ -/* TIMER32_CONTROL[SIZE] Bits */ -#define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ -#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ -/* TIMER32_CONTROL[PRESCALE] Bits */ -#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ -#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ -#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ -#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ -#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ -#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ -#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ -/* TIMER32_CONTROL[IE] Bits */ -#define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ -#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ -/* TIMER32_CONTROL[MODE] Bits */ -#define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ -#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ -/* TIMER32_CONTROL[ENABLE] Bits */ -#define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ -#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) -/* TIMER32_RIS[RAW_IFG] Bits */ -#define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ -#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ -/* TIMER32_MIS[IFG] Bits */ -#define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ -#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ - - - -/****************************************************************************** -* TIMER_A Bits -******************************************************************************/ -/* TIMER_A_CTL[IFG] Bits */ -#define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ -#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ -/* TIMER_A_CTL[IE] Bits */ -#define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ -#define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ -/* TIMER_A_CTL[CLR] Bits */ -#define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ -#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ -/* TIMER_A_CTL[MC] Bits */ -#define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ -#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ -#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ -#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ -#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TIMER_A_CTL[ID] Bits */ -#define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ -#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ -#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ -#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ -#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ -#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ -/* TIMER_A_CTL[SSEL] Bits */ -#define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ -#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ -#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ -#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ -#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ -#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ -/* TIMER_A_CCTLN[CCIFG] Bits */ -#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ -#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ -/* TIMER_A_CCTLN[COV] Bits */ -#define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ -#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ -/* TIMER_A_CCTLN[OUT] Bits */ -#define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ -#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ -/* TIMER_A_CCTLN[CCI] Bits */ -#define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ -#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ -/* TIMER_A_CCTLN[CCIE] Bits */ -#define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ -#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ -/* TIMER_A_CCTLN[OUTMOD] Bits */ -#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ -#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ -#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ -#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ -#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ -#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ -#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ -#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ -#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ -#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ -#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ -#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ -#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ -/* TIMER_A_CCTLN[CAP] Bits */ -#define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ -#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ -/* TIMER_A_CCTLN[SCCI] Bits */ -#define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ -#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ -/* TIMER_A_CCTLN[SCS] Bits */ -#define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ -#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ -/* TIMER_A_CCTLN[CCIS] Bits */ -#define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ -#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ -#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ -#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ -#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ -#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ -/* TIMER_A_CCTLN[CM] Bits */ -#define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ -#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ -#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ -#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ -#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -/* TIMER_A_EX0[IDEX] Bits */ -#define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ -#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ -#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ -#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ -#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ -#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ -#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ - -/****************************************************************************** -* TLV Bits -******************************************************************************/ -/****************************************************************************** -* TLV table start and TLV tags * -******************************************************************************/ -#define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ - -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAG_END (0x0BD0E11D) - - -/****************************************************************************** -* TPIU Bits -******************************************************************************/ - - -/****************************************************************************** -* WDT_A Bits -******************************************************************************/ -/* WDT_A_CTL[IS] Bits */ -#define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ -#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ -#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ -#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ -#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ -#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDT_A_CTL[CNTCL] Bits */ -#define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ -#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ -/* WDT_A_CTL[TMSEL] Bits */ -#define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ -#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ -/* WDT_A_CTL[SSEL] Bits */ -#define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ -#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ -#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ -#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ -#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ -#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ -/* WDT_A_CTL[HOLD] Bits */ -#define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ -#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ -/* WDT_A_CTL[PW] Bits */ -#define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ -#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ -/* Pre-defined bitfield values */ -#define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ - - -/****************************************************************************** -* BSL * -******************************************************************************/ -#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ -#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ -#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) - -#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ -#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ -#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ -#define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ - -#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ - - -/****************************************************************************** -* Mailbox struct legacy definition * -******************************************************************************/ -#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type - -/****************************************************************************** -* Device Unlock Support * -******************************************************************************/ -/* unlock the device by: - * Load SYSCTL_SECDATA_UNLOCK register address into R0 - * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 - * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register - */ -#define UNLOCK_DEVICE\ - __asm(" MOVW.W R0, #0x3040");\ - __asm(" MOVT.W R0, #0xE004");\ - __asm(" MOVW.W R1, #0x695A");\ - __asm(" MOVT.W R1, #0x0000");\ - __asm(" STR R1, [R0]"); - -/****************************************************************************** -* -* The following are values that can be used to choose the command that will be -* run by the boot code. Perform a logical OR of these settings to create your -* general parameter command. -* -******************************************************************************/ -#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) -#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) -#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) -#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) -#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) -#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) -#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) -#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) -#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) -#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) -#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) -#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) -#define COMMAND_NONE ((uint32_t)0xFFFFFFFF) - -/****************************************************************************** -* -* The following are values that can be used to configure the BSL. Perform a -* logical OR of these settings to create your BSL parameter. -* -******************************************************************************/ -#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) - -#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) -#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) - -#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) -#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) -#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) -#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) -#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) -#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) -#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) - -#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) - -#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) -#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) -#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) -#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) - -#define BSL_CONFIG_I2C_ADD_OFFSET (16) - - -/****************************************************************************** -* ULP Advisor * -******************************************************************************/ -#ifdef __TI_ARM__ -#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) -#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) -#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) -#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) -#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) -#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) -#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) -#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) -#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) -#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P401R_H__ */ - diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp432p401r_classic.h b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp432p401r_classic.h deleted file mode 100644 index 3f91b1f39c7..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp432p401r_classic.h +++ /dev/null @@ -1,3623 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P401R Register Definitions -* -* This file includes MSP430 style component and register definitions -* for legacy components re-used in MSP432 -* -* File creation date: 2017-12-06 -* -******************************************************************************/ - -#ifndef __MSP432P401R_CLASSIC_H__ -#define __MSP432P401R_CLASSIC_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/****************************************************************************** -* Device memory map * -******************************************************************************/ -#define __MAIN_MEMORY_START__ (0x00000000) /*!< Main Flash memory start address */ -#define __MAIN_MEMORY_END__ (0x0003FFFF) /*!< Main Flash memory end address */ -#define __BSL_MEMORY_START__ (0x00202000) /*!< BSL memory start address */ -#define __BSL_MEMORY_END__ (0x00203FFF) /*!< BSL memory end address */ -#define __SRAM_START__ (0x20000000) /*!< SRAM memory start address */ -#define __SRAM_END__ (0x2000FFFF) /*!< SRAM memory end address */ - -/****************************************************************************** -* MSP-format peripheral registers * -******************************************************************************/ - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -#define AESACTL0 (HWREG16(0x40003C00)) /*!< AES Accelerator Control Register 0 */ -#define AESACTL1 (HWREG16(0x40003C02)) /*!< AES Accelerator Control Register 1 */ -#define AESASTAT (HWREG16(0x40003C04)) /*!< AES Accelerator Status Register */ -#define AESAKEY (HWREG16(0x40003C06)) /*!< AES Accelerator Key Register */ -#define AESADIN (HWREG16(0x40003C08)) /*!< AES Accelerator Data In Register */ -#define AESADOUT (HWREG16(0x40003C0A)) /*!< AES Accelerator Data Out Register */ -#define AESAXDIN (HWREG16(0x40003C0C)) /*!< AES Accelerator XORed Data In Register */ -#define AESAXIN (HWREG16(0x40003C0E)) /*!< AES Accelerator XORed Data In Register */ - -/* Register offsets from AES256_BASE address */ -#define OFS_AESACTL0 (0x0000) /*!< AES Accelerator Control Register 0 */ -#define OFS_AESACTL1 (0x0002) /*!< AES Accelerator Control Register 1 */ -#define OFS_AESASTAT (0x0004) /*!< AES Accelerator Status Register */ -#define OFS_AESAKEY (0x0006) /*!< AES Accelerator Key Register */ -#define OFS_AESADIN (0x0008) /*!< AES Accelerator Data In Register */ -#define OFS_AESADOUT (0x000A) /*!< AES Accelerator Data Out Register */ -#define OFS_AESAXDIN (0x000C) /*!< AES Accelerator XORed Data In Register */ -#define OFS_AESAXIN (0x000E) /*!< AES Accelerator XORed Data In Register */ - - -/****************************************************************************** -* CAPTIO0 Registers -******************************************************************************/ -#define CAPTIO0CTL (HWREG16(0x4000540E)) /*!< Capacitive Touch IO x Control Register */ - -/* Register offsets from CAPTIO0_BASE address */ -#define OFS_CAPTIO0CTL (0x000E) /*!< Capacitive Touch IO x Control Register */ - -#define CAPTIO0CTL_L (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */ -#define CAPTIO0CTL_H (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */ - -/****************************************************************************** -* CAPTIO1 Registers -******************************************************************************/ -#define CAPTIO1CTL (HWREG16(0x4000580E)) /*!< Capacitive Touch IO x Control Register */ - -/* Register offsets from CAPTIO1_BASE address */ -#define OFS_CAPTIO1CTL (0x000E) /*!< Capacitive Touch IO x Control Register */ - -#define CAPTIO1CTL_L (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */ -#define CAPTIO1CTL_H (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */ - -/****************************************************************************** -* COMP_E0 Registers -******************************************************************************/ -#define CE0CTL0 (HWREG16(0x40003400)) /*!< Comparator Control Register 0 */ -#define CE0CTL1 (HWREG16(0x40003402)) /*!< Comparator Control Register 1 */ -#define CE0CTL2 (HWREG16(0x40003404)) /*!< Comparator Control Register 2 */ -#define CE0CTL3 (HWREG16(0x40003406)) /*!< Comparator Control Register 3 */ -#define CE0INT (HWREG16(0x4000340C)) /*!< Comparator Interrupt Control Register */ -#define CE0IV (HWREG16(0x4000340E)) /*!< Comparator Interrupt Vector Word Register */ - -/* Register offsets from COMP_E0_BASE address */ -#define OFS_CE0CTL0 (0x0000) /*!< Comparator Control Register 0 */ -#define OFS_CE0CTL1 (0x0002) /*!< Comparator Control Register 1 */ -#define OFS_CE0CTL2 (0x0004) /*!< Comparator Control Register 2 */ -#define OFS_CE0CTL3 (0x0006) /*!< Comparator Control Register 3 */ -#define OFS_CE0INT (0x000C) /*!< Comparator Interrupt Control Register */ -#define OFS_CE0IV (0x000E) /*!< Comparator Interrupt Vector Word Register */ - - -/****************************************************************************** -* COMP_E1 Registers -******************************************************************************/ -#define CE1CTL0 (HWREG16(0x40003800)) /*!< Comparator Control Register 0 */ -#define CE1CTL1 (HWREG16(0x40003802)) /*!< Comparator Control Register 1 */ -#define CE1CTL2 (HWREG16(0x40003804)) /*!< Comparator Control Register 2 */ -#define CE1CTL3 (HWREG16(0x40003806)) /*!< Comparator Control Register 3 */ -#define CE1INT (HWREG16(0x4000380C)) /*!< Comparator Interrupt Control Register */ -#define CE1IV (HWREG16(0x4000380E)) /*!< Comparator Interrupt Vector Word Register */ - -/* Register offsets from COMP_E1_BASE address */ -#define OFS_CE1CTL0 (0x0000) /*!< Comparator Control Register 0 */ -#define OFS_CE1CTL1 (0x0002) /*!< Comparator Control Register 1 */ -#define OFS_CE1CTL2 (0x0004) /*!< Comparator Control Register 2 */ -#define OFS_CE1CTL3 (0x0006) /*!< Comparator Control Register 3 */ -#define OFS_CE1INT (0x000C) /*!< Comparator Interrupt Control Register */ -#define OFS_CE1IV (0x000E) /*!< Comparator Interrupt Vector Word Register */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -#define CRC32DI (HWREG16(0x40004000)) /*!< Data Input for CRC32 Signature Computation */ -#define CRC32DIRB (HWREG16(0x40004004)) /*!< Data In Reverse for CRC32 Computation */ -#define CRC32INIRES_LO (HWREG16(0x40004008)) /*!< CRC32 Initialization and Result, lower 16 bits */ -#define CRC32INIRES_HI (HWREG16(0x4000400A)) /*!< CRC32 Initialization and Result, upper 16 bits */ -#define CRC32RESR_LO (HWREG16(0x4000400C)) /*!< CRC32 Result Reverse, lower 16 bits */ -#define CRC32RESR_HI (HWREG16(0x4000400E)) /*!< CRC32 Result Reverse, Upper 16 bits */ -#define CRC16DI (HWREG16(0x40004010)) /*!< Data Input for CRC16 computation */ -#define CRC16DIRB (HWREG16(0x40004014)) /*!< CRC16 Data In Reverse */ -#define CRC16INIRES (HWREG16(0x40004018)) /*!< CRC16 Initialization and Result register */ -#define CRC16RESR (HWREG16(0x4000401E)) /*!< CRC16 Result Reverse */ - -/* Register offsets from CRC32_BASE address */ -#define OFS_CRC32DI (0x0000) /*!< Data Input for CRC32 Signature Computation */ -#define OFS_CRC32DIRB (0x0004) /*!< Data In Reverse for CRC32 Computation */ -#define OFS_CRC32INIRES_LO (0x0008) /*!< CRC32 Initialization and Result, lower 16 bits */ -#define OFS_CRC32INIRES_HI (0x000A) /*!< CRC32 Initialization and Result, upper 16 bits */ -#define OFS_CRC32RESR_LO (0x000C) /*!< CRC32 Result Reverse, lower 16 bits */ -#define OFS_CRC32RESR_HI (0x000E) /*!< CRC32 Result Reverse, Upper 16 bits */ -#define OFS_CRC16DI (0x0010) /*!< Data Input for CRC16 computation */ -#define OFS_CRC16DIRB (0x0014) /*!< CRC16 Data In Reverse */ -#define OFS_CRC16INIRES (0x0018) /*!< CRC16 Initialization and Result register */ -#define OFS_CRC16RESR (0x001E) /*!< CRC16 Result Reverse */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -#define PAIN (HWREG16(0x40004C00)) /*!< Port A Input */ -#define PAOUT (HWREG16(0x40004C02)) /*!< Port A Output */ -#define PADIR (HWREG16(0x40004C04)) /*!< Port A Direction */ -#define PAREN (HWREG16(0x40004C06)) /*!< Port A Resistor Enable */ -#define PADS (HWREG16(0x40004C08)) /*!< Port A Drive Strength */ -#define PASEL0 (HWREG16(0x40004C0A)) /*!< Port A Select 0 */ -#define PASEL1 (HWREG16(0x40004C0C)) /*!< Port A Select 1 */ -#define P1IV (HWREG16(0x40004C0E)) /*!< Port 1 Interrupt Vector Register */ -#define PASELC (HWREG16(0x40004C16)) /*!< Port A Complement Select */ -#define PAIES (HWREG16(0x40004C18)) /*!< Port A Interrupt Edge Select */ -#define PAIE (HWREG16(0x40004C1A)) /*!< Port A Interrupt Enable */ -#define PAIFG (HWREG16(0x40004C1C)) /*!< Port A Interrupt Flag */ -#define P2IV (HWREG16(0x40004C1E)) /*!< Port 2 Interrupt Vector Register */ -#define PBIN (HWREG16(0x40004C20)) /*!< Port B Input */ -#define PBOUT (HWREG16(0x40004C22)) /*!< Port B Output */ -#define PBDIR (HWREG16(0x40004C24)) /*!< Port B Direction */ -#define PBREN (HWREG16(0x40004C26)) /*!< Port B Resistor Enable */ -#define PBDS (HWREG16(0x40004C28)) /*!< Port B Drive Strength */ -#define PBSEL0 (HWREG16(0x40004C2A)) /*!< Port B Select 0 */ -#define PBSEL1 (HWREG16(0x40004C2C)) /*!< Port B Select 1 */ -#define P3IV (HWREG16(0x40004C2E)) /*!< Port 3 Interrupt Vector Register */ -#define PBSELC (HWREG16(0x40004C36)) /*!< Port B Complement Select */ -#define PBIES (HWREG16(0x40004C38)) /*!< Port B Interrupt Edge Select */ -#define PBIE (HWREG16(0x40004C3A)) /*!< Port B Interrupt Enable */ -#define PBIFG (HWREG16(0x40004C3C)) /*!< Port B Interrupt Flag */ -#define P4IV (HWREG16(0x40004C3E)) /*!< Port 4 Interrupt Vector Register */ -#define PCIN (HWREG16(0x40004C40)) /*!< Port C Input */ -#define PCOUT (HWREG16(0x40004C42)) /*!< Port C Output */ -#define PCDIR (HWREG16(0x40004C44)) /*!< Port C Direction */ -#define PCREN (HWREG16(0x40004C46)) /*!< Port C Resistor Enable */ -#define PCDS (HWREG16(0x40004C48)) /*!< Port C Drive Strength */ -#define PCSEL0 (HWREG16(0x40004C4A)) /*!< Port C Select 0 */ -#define PCSEL1 (HWREG16(0x40004C4C)) /*!< Port C Select 1 */ -#define P5IV (HWREG16(0x40004C4E)) /*!< Port 5 Interrupt Vector Register */ -#define PCSELC (HWREG16(0x40004C56)) /*!< Port C Complement Select */ -#define PCIES (HWREG16(0x40004C58)) /*!< Port C Interrupt Edge Select */ -#define PCIE (HWREG16(0x40004C5A)) /*!< Port C Interrupt Enable */ -#define PCIFG (HWREG16(0x40004C5C)) /*!< Port C Interrupt Flag */ -#define P6IV (HWREG16(0x40004C5E)) /*!< Port 6 Interrupt Vector Register */ -#define PDIN (HWREG16(0x40004C60)) /*!< Port D Input */ -#define PDOUT (HWREG16(0x40004C62)) /*!< Port D Output */ -#define PDDIR (HWREG16(0x40004C64)) /*!< Port D Direction */ -#define PDREN (HWREG16(0x40004C66)) /*!< Port D Resistor Enable */ -#define PDDS (HWREG16(0x40004C68)) /*!< Port D Drive Strength */ -#define PDSEL0 (HWREG16(0x40004C6A)) /*!< Port D Select 0 */ -#define PDSEL1 (HWREG16(0x40004C6C)) /*!< Port D Select 1 */ -#define P7IV (HWREG16(0x40004C6E)) /*!< Port 7 Interrupt Vector Register */ -#define PDSELC (HWREG16(0x40004C76)) /*!< Port D Complement Select */ -#define PDIES (HWREG16(0x40004C78)) /*!< Port D Interrupt Edge Select */ -#define PDIE (HWREG16(0x40004C7A)) /*!< Port D Interrupt Enable */ -#define PDIFG (HWREG16(0x40004C7C)) /*!< Port D Interrupt Flag */ -#define P8IV (HWREG16(0x40004C7E)) /*!< Port 8 Interrupt Vector Register */ -#define PEIN (HWREG16(0x40004C80)) /*!< Port E Input */ -#define PEOUT (HWREG16(0x40004C82)) /*!< Port E Output */ -#define PEDIR (HWREG16(0x40004C84)) /*!< Port E Direction */ -#define PEREN (HWREG16(0x40004C86)) /*!< Port E Resistor Enable */ -#define PEDS (HWREG16(0x40004C88)) /*!< Port E Drive Strength */ -#define PESEL0 (HWREG16(0x40004C8A)) /*!< Port E Select 0 */ -#define PESEL1 (HWREG16(0x40004C8C)) /*!< Port E Select 1 */ -#define P9IV (HWREG16(0x40004C8E)) /*!< Port 9 Interrupt Vector Register */ -#define PESELC (HWREG16(0x40004C96)) /*!< Port E Complement Select */ -#define PEIES (HWREG16(0x40004C98)) /*!< Port E Interrupt Edge Select */ -#define PEIE (HWREG16(0x40004C9A)) /*!< Port E Interrupt Enable */ -#define PEIFG (HWREG16(0x40004C9C)) /*!< Port E Interrupt Flag */ -#define P10IV (HWREG16(0x40004C9E)) /*!< Port 10 Interrupt Vector Register */ -#define PJIN (HWREG16(0x40004D20)) /*!< Port J Input */ -#define PJOUT (HWREG16(0x40004D22)) /*!< Port J Output */ -#define PJDIR (HWREG16(0x40004D24)) /*!< Port J Direction */ -#define PJREN (HWREG16(0x40004D26)) /*!< Port J Resistor Enable */ -#define PJDS (HWREG16(0x40004D28)) /*!< Port J Drive Strength */ -#define PJSEL0 (HWREG16(0x40004D2A)) /*!< Port J Select 0 */ -#define PJSEL1 (HWREG16(0x40004D2C)) /*!< Port J Select 1 */ -#define PJSELC (HWREG16(0x40004D36)) /*!< Port J Complement Select */ -#define P1IN (HWREG8(0x40004C00)) /*!< Port 1 Input */ -#define P2IN (HWREG8(0x40004C01)) /*!< Port 2 Input */ -#define P2OUT (HWREG8(0x40004C03)) /*!< Port 2 Output */ -#define P1OUT (HWREG8(0x40004C02)) /*!< Port 1 Output */ -#define P1DIR (HWREG8(0x40004C04)) /*!< Port 1 Direction */ -#define P2DIR (HWREG8(0x40004C05)) /*!< Port 2 Direction */ -#define P1REN (HWREG8(0x40004C06)) /*!< Port 1 Resistor Enable */ -#define P2REN (HWREG8(0x40004C07)) /*!< Port 2 Resistor Enable */ -#define P1DS (HWREG8(0x40004C08)) /*!< Port 1 Drive Strength */ -#define P2DS (HWREG8(0x40004C09)) /*!< Port 2 Drive Strength */ -#define P1SEL0 (HWREG8(0x40004C0A)) /*!< Port 1 Select 0 */ -#define P2SEL0 (HWREG8(0x40004C0B)) /*!< Port 2 Select 0 */ -#define P1SEL1 (HWREG8(0x40004C0C)) /*!< Port 1 Select 1 */ -#define P2SEL1 (HWREG8(0x40004C0D)) /*!< Port 2 Select 1 */ -#define P1SELC (HWREG8(0x40004C16)) /*!< Port 1 Complement Select */ -#define P2SELC (HWREG8(0x40004C17)) /*!< Port 2 Complement Select */ -#define P1IES (HWREG8(0x40004C18)) /*!< Port 1 Interrupt Edge Select */ -#define P2IES (HWREG8(0x40004C19)) /*!< Port 2 Interrupt Edge Select */ -#define P1IE (HWREG8(0x40004C1A)) /*!< Port 1 Interrupt Enable */ -#define P2IE (HWREG8(0x40004C1B)) /*!< Port 2 Interrupt Enable */ -#define P1IFG (HWREG8(0x40004C1C)) /*!< Port 1 Interrupt Flag */ -#define P2IFG (HWREG8(0x40004C1D)) /*!< Port 2 Interrupt Flag */ -#define P3IN (HWREG8(0x40004C20)) /*!< Port 3 Input */ -#define P4IN (HWREG8(0x40004C21)) /*!< Port 4 Input */ -#define P3OUT (HWREG8(0x40004C22)) /*!< Port 3 Output */ -#define P4OUT (HWREG8(0x40004C23)) /*!< Port 4 Output */ -#define P3DIR (HWREG8(0x40004C24)) /*!< Port 3 Direction */ -#define P4DIR (HWREG8(0x40004C25)) /*!< Port 4 Direction */ -#define P3REN (HWREG8(0x40004C26)) /*!< Port 3 Resistor Enable */ -#define P4REN (HWREG8(0x40004C27)) /*!< Port 4 Resistor Enable */ -#define P3DS (HWREG8(0x40004C28)) /*!< Port 3 Drive Strength */ -#define P4DS (HWREG8(0x40004C29)) /*!< Port 4 Drive Strength */ -#define P4SEL0 (HWREG8(0x40004C2B)) /*!< Port 4 Select 0 */ -#define P3SEL0 (HWREG8(0x40004C2A)) /*!< Port 3 Select 0 */ -#define P3SEL1 (HWREG8(0x40004C2C)) /*!< Port 3 Select 1 */ -#define P4SEL1 (HWREG8(0x40004C2D)) /*!< Port 4 Select 1 */ -#define P3SELC (HWREG8(0x40004C36)) /*!< Port 3 Complement Select */ -#define P4SELC (HWREG8(0x40004C37)) /*!< Port 4 Complement Select */ -#define P3IES (HWREG8(0x40004C38)) /*!< Port 3 Interrupt Edge Select */ -#define P4IES (HWREG8(0x40004C39)) /*!< Port 4 Interrupt Edge Select */ -#define P3IE (HWREG8(0x40004C3A)) /*!< Port 3 Interrupt Enable */ -#define P4IE (HWREG8(0x40004C3B)) /*!< Port 4 Interrupt Enable */ -#define P3IFG (HWREG8(0x40004C3C)) /*!< Port 3 Interrupt Flag */ -#define P4IFG (HWREG8(0x40004C3D)) /*!< Port 4 Interrupt Flag */ -#define P5IN (HWREG8(0x40004C40)) /*!< Port 5 Input */ -#define P6IN (HWREG8(0x40004C41)) /*!< Port 6 Input */ -#define P5OUT (HWREG8(0x40004C42)) /*!< Port 5 Output */ -#define P6OUT (HWREG8(0x40004C43)) /*!< Port 6 Output */ -#define P5DIR (HWREG8(0x40004C44)) /*!< Port 5 Direction */ -#define P6DIR (HWREG8(0x40004C45)) /*!< Port 6 Direction */ -#define P5REN (HWREG8(0x40004C46)) /*!< Port 5 Resistor Enable */ -#define P6REN (HWREG8(0x40004C47)) /*!< Port 6 Resistor Enable */ -#define P5DS (HWREG8(0x40004C48)) /*!< Port 5 Drive Strength */ -#define P6DS (HWREG8(0x40004C49)) /*!< Port 6 Drive Strength */ -#define P5SEL0 (HWREG8(0x40004C4A)) /*!< Port 5 Select 0 */ -#define P6SEL0 (HWREG8(0x40004C4B)) /*!< Port 6 Select 0 */ -#define P5SEL1 (HWREG8(0x40004C4C)) /*!< Port 5 Select 1 */ -#define P6SEL1 (HWREG8(0x40004C4D)) /*!< Port 6 Select 1 */ -#define P5SELC (HWREG8(0x40004C56)) /*!< Port 5 Complement Select */ -#define P6SELC (HWREG8(0x40004C57)) /*!< Port 6 Complement Select */ -#define P5IES (HWREG8(0x40004C58)) /*!< Port 5 Interrupt Edge Select */ -#define P6IES (HWREG8(0x40004C59)) /*!< Port 6 Interrupt Edge Select */ -#define P5IE (HWREG8(0x40004C5A)) /*!< Port 5 Interrupt Enable */ -#define P6IE (HWREG8(0x40004C5B)) /*!< Port 6 Interrupt Enable */ -#define P5IFG (HWREG8(0x40004C5C)) /*!< Port 5 Interrupt Flag */ -#define P6IFG (HWREG8(0x40004C5D)) /*!< Port 6 Interrupt Flag */ -#define P7IN (HWREG8(0x40004C60)) /*!< Port 7 Input */ -#define P8IN (HWREG8(0x40004C61)) /*!< Port 8 Input */ -#define P7OUT (HWREG8(0x40004C62)) /*!< Port 7 Output */ -#define P8OUT (HWREG8(0x40004C63)) /*!< Port 8 Output */ -#define P7DIR (HWREG8(0x40004C64)) /*!< Port 7 Direction */ -#define P8DIR (HWREG8(0x40004C65)) /*!< Port 8 Direction */ -#define P7REN (HWREG8(0x40004C66)) /*!< Port 7 Resistor Enable */ -#define P8REN (HWREG8(0x40004C67)) /*!< Port 8 Resistor Enable */ -#define P7DS (HWREG8(0x40004C68)) /*!< Port 7 Drive Strength */ -#define P8DS (HWREG8(0x40004C69)) /*!< Port 8 Drive Strength */ -#define P7SEL0 (HWREG8(0x40004C6A)) /*!< Port 7 Select 0 */ -#define P8SEL0 (HWREG8(0x40004C6B)) /*!< Port 8 Select 0 */ -#define P7SEL1 (HWREG8(0x40004C6C)) /*!< Port 7 Select 1 */ -#define P8SEL1 (HWREG8(0x40004C6D)) /*!< Port 8 Select 1 */ -#define P7SELC (HWREG8(0x40004C76)) /*!< Port 7 Complement Select */ -#define P8SELC (HWREG8(0x40004C77)) /*!< Port 8 Complement Select */ -#define P7IES (HWREG8(0x40004C78)) /*!< Port 7 Interrupt Edge Select */ -#define P8IES (HWREG8(0x40004C79)) /*!< Port 8 Interrupt Edge Select */ -#define P7IE (HWREG8(0x40004C7A)) /*!< Port 7 Interrupt Enable */ -#define P8IE (HWREG8(0x40004C7B)) /*!< Port 8 Interrupt Enable */ -#define P7IFG (HWREG8(0x40004C7C)) /*!< Port 7 Interrupt Flag */ -#define P8IFG (HWREG8(0x40004C7D)) /*!< Port 8 Interrupt Flag */ -#define P9IN (HWREG8(0x40004C80)) /*!< Port 9 Input */ -#define P10IN (HWREG8(0x40004C81)) /*!< Port 10 Input */ -#define P9OUT (HWREG8(0x40004C82)) /*!< Port 9 Output */ -#define P10OUT (HWREG8(0x40004C83)) /*!< Port 10 Output */ -#define P9DIR (HWREG8(0x40004C84)) /*!< Port 9 Direction */ -#define P10DIR (HWREG8(0x40004C85)) /*!< Port 10 Direction */ -#define P9REN (HWREG8(0x40004C86)) /*!< Port 9 Resistor Enable */ -#define P10REN (HWREG8(0x40004C87)) /*!< Port 10 Resistor Enable */ -#define P9DS (HWREG8(0x40004C88)) /*!< Port 9 Drive Strength */ -#define P10DS (HWREG8(0x40004C89)) /*!< Port 10 Drive Strength */ -#define P9SEL0 (HWREG8(0x40004C8A)) /*!< Port 9 Select 0 */ -#define P10SEL0 (HWREG8(0x40004C8B)) /*!< Port 10 Select 0 */ -#define P9SEL1 (HWREG8(0x40004C8C)) /*!< Port 9 Select 1 */ -#define P10SEL1 (HWREG8(0x40004C8D)) /*!< Port 10 Select 1 */ -#define P9SELC (HWREG8(0x40004C96)) /*!< Port 9 Complement Select */ -#define P10SELC (HWREG8(0x40004C97)) /*!< Port 10 Complement Select */ -#define P9IES (HWREG8(0x40004C98)) /*!< Port 9 Interrupt Edge Select */ -#define P10IES (HWREG8(0x40004C99)) /*!< Port 10 Interrupt Edge Select */ -#define P9IE (HWREG8(0x40004C9A)) /*!< Port 9 Interrupt Enable */ -#define P10IE (HWREG8(0x40004C9B)) /*!< Port 10 Interrupt Enable */ -#define P9IFG (HWREG8(0x40004C9C)) /*!< Port 9 Interrupt Flag */ -#define P10IFG (HWREG8(0x40004C9D)) /*!< Port 10 Interrupt Flag */ - -/* Register offsets from DIO_BASE address */ -#define OFS_PAIN (0x0000) /*!< Port A Input */ -#define OFS_PAOUT (0x0002) /*!< Port A Output */ -#define OFS_PADIR (0x0004) /*!< Port A Direction */ -#define OFS_PAREN (0x0006) /*!< Port A Resistor Enable */ -#define OFS_PADS (0x0008) /*!< Port A Drive Strength */ -#define OFS_PASEL0 (0x000A) /*!< Port A Select 0 */ -#define OFS_PASEL1 (0x000C) /*!< Port A Select 1 */ -#define OFS_P1IV (0x000E) /*!< Port 1 Interrupt Vector Register */ -#define OFS_PASELC (0x0016) /*!< Port A Complement Select */ -#define OFS_PAIES (0x0018) /*!< Port A Interrupt Edge Select */ -#define OFS_PAIE (0x001A) /*!< Port A Interrupt Enable */ -#define OFS_PAIFG (0x001C) /*!< Port A Interrupt Flag */ -#define OFS_P2IV (0x001E) /*!< Port 2 Interrupt Vector Register */ -#define OFS_PBIN (0x0020) /*!< Port B Input */ -#define OFS_PBOUT (0x0022) /*!< Port B Output */ -#define OFS_PBDIR (0x0024) /*!< Port B Direction */ -#define OFS_PBREN (0x0026) /*!< Port B Resistor Enable */ -#define OFS_PBDS (0x0028) /*!< Port B Drive Strength */ -#define OFS_PBSEL0 (0x002A) /*!< Port B Select 0 */ -#define OFS_PBSEL1 (0x002C) /*!< Port B Select 1 */ -#define OFS_P3IV (0x002E) /*!< Port 3 Interrupt Vector Register */ -#define OFS_PBSELC (0x0036) /*!< Port B Complement Select */ -#define OFS_PBIES (0x0038) /*!< Port B Interrupt Edge Select */ -#define OFS_PBIE (0x003A) /*!< Port B Interrupt Enable */ -#define OFS_PBIFG (0x003C) /*!< Port B Interrupt Flag */ -#define OFS_P4IV (0x003E) /*!< Port 4 Interrupt Vector Register */ -#define OFS_PCIN (0x0040) /*!< Port C Input */ -#define OFS_PCOUT (0x0042) /*!< Port C Output */ -#define OFS_PCDIR (0x0044) /*!< Port C Direction */ -#define OFS_PCREN (0x0046) /*!< Port C Resistor Enable */ -#define OFS_PCDS (0x0048) /*!< Port C Drive Strength */ -#define OFS_PCSEL0 (0x004A) /*!< Port C Select 0 */ -#define OFS_PCSEL1 (0x004C) /*!< Port C Select 1 */ -#define OFS_P5IV (0x004E) /*!< Port 5 Interrupt Vector Register */ -#define OFS_PCSELC (0x0056) /*!< Port C Complement Select */ -#define OFS_PCIES (0x0058) /*!< Port C Interrupt Edge Select */ -#define OFS_PCIE (0x005A) /*!< Port C Interrupt Enable */ -#define OFS_PCIFG (0x005C) /*!< Port C Interrupt Flag */ -#define OFS_P6IV (0x005E) /*!< Port 6 Interrupt Vector Register */ -#define OFS_PDIN (0x0060) /*!< Port D Input */ -#define OFS_PDOUT (0x0062) /*!< Port D Output */ -#define OFS_PDDIR (0x0064) /*!< Port D Direction */ -#define OFS_PDREN (0x0066) /*!< Port D Resistor Enable */ -#define OFS_PDDS (0x0068) /*!< Port D Drive Strength */ -#define OFS_PDSEL0 (0x006A) /*!< Port D Select 0 */ -#define OFS_PDSEL1 (0x006C) /*!< Port D Select 1 */ -#define OFS_P7IV (0x006E) /*!< Port 7 Interrupt Vector Register */ -#define OFS_PDSELC (0x0076) /*!< Port D Complement Select */ -#define OFS_PDIES (0x0078) /*!< Port D Interrupt Edge Select */ -#define OFS_PDIE (0x007A) /*!< Port D Interrupt Enable */ -#define OFS_PDIFG (0x007C) /*!< Port D Interrupt Flag */ -#define OFS_P8IV (0x007E) /*!< Port 8 Interrupt Vector Register */ -#define OFS_PEIN (0x0080) /*!< Port E Input */ -#define OFS_PEOUT (0x0082) /*!< Port E Output */ -#define OFS_PEDIR (0x0084) /*!< Port E Direction */ -#define OFS_PEREN (0x0086) /*!< Port E Resistor Enable */ -#define OFS_PEDS (0x0088) /*!< Port E Drive Strength */ -#define OFS_PESEL0 (0x008A) /*!< Port E Select 0 */ -#define OFS_PESEL1 (0x008C) /*!< Port E Select 1 */ -#define OFS_P9IV (0x008E) /*!< Port 9 Interrupt Vector Register */ -#define OFS_PESELC (0x0096) /*!< Port E Complement Select */ -#define OFS_PEIES (0x0098) /*!< Port E Interrupt Edge Select */ -#define OFS_PEIE (0x009A) /*!< Port E Interrupt Enable */ -#define OFS_PEIFG (0x009C) /*!< Port E Interrupt Flag */ -#define OFS_P10IV (0x009E) /*!< Port 10 Interrupt Vector Register */ -#define OFS_PJIN (0x0120) /*!< Port J Input */ -#define OFS_PJOUT (0x0122) /*!< Port J Output */ -#define OFS_PJDIR (0x0124) /*!< Port J Direction */ -#define OFS_PJREN (0x0126) /*!< Port J Resistor Enable */ -#define OFS_PJDS (0x0128) /*!< Port J Drive Strength */ -#define OFS_PJSEL0 (0x012A) /*!< Port J Select 0 */ -#define OFS_PJSEL1 (0x012C) /*!< Port J Select 1 */ -#define OFS_PJSELC (0x0136) /*!< Port J Complement Select */ -#define OFS_P1IN (0x0000) /*!< Port 1 Input */ -#define OFS_P2IN (0x0001) /*!< Port 2 Input */ -#define OFS_P2OUT (0x0003) /*!< Port 2 Output */ -#define OFS_P1OUT (0x0002) /*!< Port 1 Output */ -#define OFS_P1DIR (0x0004) /*!< Port 1 Direction */ -#define OFS_P2DIR (0x0005) /*!< Port 2 Direction */ -#define OFS_P1REN (0x0006) /*!< Port 1 Resistor Enable */ -#define OFS_P2REN (0x0007) /*!< Port 2 Resistor Enable */ -#define OFS_P1DS (0x0008) /*!< Port 1 Drive Strength */ -#define OFS_P2DS (0x0009) /*!< Port 2 Drive Strength */ -#define OFS_P1SEL0 (0x000A) /*!< Port 1 Select 0 */ -#define OFS_P2SEL0 (0x000B) /*!< Port 2 Select 0 */ -#define OFS_P1SEL1 (0x000C) /*!< Port 1 Select 1 */ -#define OFS_P2SEL1 (0x000D) /*!< Port 2 Select 1 */ -#define OFS_P1SELC (0x0016) /*!< Port 1 Complement Select */ -#define OFS_P2SELC (0x0017) /*!< Port 2 Complement Select */ -#define OFS_P1IES (0x0018) /*!< Port 1 Interrupt Edge Select */ -#define OFS_P2IES (0x0019) /*!< Port 2 Interrupt Edge Select */ -#define OFS_P1IE (0x001A) /*!< Port 1 Interrupt Enable */ -#define OFS_P2IE (0x001B) /*!< Port 2 Interrupt Enable */ -#define OFS_P1IFG (0x001C) /*!< Port 1 Interrupt Flag */ -#define OFS_P2IFG (0x001D) /*!< Port 2 Interrupt Flag */ -#define OFS_P3IN (0x0020) /*!< Port 3 Input */ -#define OFS_P4IN (0x0021) /*!< Port 4 Input */ -#define OFS_P3OUT (0x0022) /*!< Port 3 Output */ -#define OFS_P4OUT (0x0023) /*!< Port 4 Output */ -#define OFS_P3DIR (0x0024) /*!< Port 3 Direction */ -#define OFS_P4DIR (0x0025) /*!< Port 4 Direction */ -#define OFS_P3REN (0x0026) /*!< Port 3 Resistor Enable */ -#define OFS_P4REN (0x0027) /*!< Port 4 Resistor Enable */ -#define OFS_P3DS (0x0028) /*!< Port 3 Drive Strength */ -#define OFS_P4DS (0x0029) /*!< Port 4 Drive Strength */ -#define OFS_P4SEL0 (0x002B) /*!< Port 4 Select 0 */ -#define OFS_P3SEL0 (0x002A) /*!< Port 3 Select 0 */ -#define OFS_P3SEL1 (0x002C) /*!< Port 3 Select 1 */ -#define OFS_P4SEL1 (0x002D) /*!< Port 4 Select 1 */ -#define OFS_P3SELC (0x0036) /*!< Port 3 Complement Select */ -#define OFS_P4SELC (0x0037) /*!< Port 4 Complement Select */ -#define OFS_P3IES (0x0038) /*!< Port 3 Interrupt Edge Select */ -#define OFS_P4IES (0x0039) /*!< Port 4 Interrupt Edge Select */ -#define OFS_P3IE (0x003A) /*!< Port 3 Interrupt Enable */ -#define OFS_P4IE (0x003B) /*!< Port 4 Interrupt Enable */ -#define OFS_P3IFG (0x003C) /*!< Port 3 Interrupt Flag */ -#define OFS_P4IFG (0x003D) /*!< Port 4 Interrupt Flag */ -#define OFS_P5IN (0x0040) /*!< Port 5 Input */ -#define OFS_P6IN (0x0041) /*!< Port 6 Input */ -#define OFS_P5OUT (0x0042) /*!< Port 5 Output */ -#define OFS_P6OUT (0x0043) /*!< Port 6 Output */ -#define OFS_P5DIR (0x0044) /*!< Port 5 Direction */ -#define OFS_P6DIR (0x0045) /*!< Port 6 Direction */ -#define OFS_P5REN (0x0046) /*!< Port 5 Resistor Enable */ -#define OFS_P6REN (0x0047) /*!< Port 6 Resistor Enable */ -#define OFS_P5DS (0x0048) /*!< Port 5 Drive Strength */ -#define OFS_P6DS (0x0049) /*!< Port 6 Drive Strength */ -#define OFS_P5SEL0 (0x004A) /*!< Port 5 Select 0 */ -#define OFS_P6SEL0 (0x004B) /*!< Port 6 Select 0 */ -#define OFS_P5SEL1 (0x004C) /*!< Port 5 Select 1 */ -#define OFS_P6SEL1 (0x004D) /*!< Port 6 Select 1 */ -#define OFS_P5SELC (0x0056) /*!< Port 5 Complement Select */ -#define OFS_P6SELC (0x0057) /*!< Port 6 Complement Select */ -#define OFS_P5IES (0x0058) /*!< Port 5 Interrupt Edge Select */ -#define OFS_P6IES (0x0059) /*!< Port 6 Interrupt Edge Select */ -#define OFS_P5IE (0x005A) /*!< Port 5 Interrupt Enable */ -#define OFS_P6IE (0x005B) /*!< Port 6 Interrupt Enable */ -#define OFS_P5IFG (0x005C) /*!< Port 5 Interrupt Flag */ -#define OFS_P6IFG (0x005D) /*!< Port 6 Interrupt Flag */ -#define OFS_P7IN (0x0060) /*!< Port 7 Input */ -#define OFS_P8IN (0x0061) /*!< Port 8 Input */ -#define OFS_P7OUT (0x0062) /*!< Port 7 Output */ -#define OFS_P8OUT (0x0063) /*!< Port 8 Output */ -#define OFS_P7DIR (0x0064) /*!< Port 7 Direction */ -#define OFS_P8DIR (0x0065) /*!< Port 8 Direction */ -#define OFS_P7REN (0x0066) /*!< Port 7 Resistor Enable */ -#define OFS_P8REN (0x0067) /*!< Port 8 Resistor Enable */ -#define OFS_P7DS (0x0068) /*!< Port 7 Drive Strength */ -#define OFS_P8DS (0x0069) /*!< Port 8 Drive Strength */ -#define OFS_P7SEL0 (0x006A) /*!< Port 7 Select 0 */ -#define OFS_P8SEL0 (0x006B) /*!< Port 8 Select 0 */ -#define OFS_P7SEL1 (0x006C) /*!< Port 7 Select 1 */ -#define OFS_P8SEL1 (0x006D) /*!< Port 8 Select 1 */ -#define OFS_P7SELC (0x0076) /*!< Port 7 Complement Select */ -#define OFS_P8SELC (0x0077) /*!< Port 8 Complement Select */ -#define OFS_P7IES (0x0078) /*!< Port 7 Interrupt Edge Select */ -#define OFS_P8IES (0x0079) /*!< Port 8 Interrupt Edge Select */ -#define OFS_P7IE (0x007A) /*!< Port 7 Interrupt Enable */ -#define OFS_P8IE (0x007B) /*!< Port 8 Interrupt Enable */ -#define OFS_P7IFG (0x007C) /*!< Port 7 Interrupt Flag */ -#define OFS_P8IFG (0x007D) /*!< Port 8 Interrupt Flag */ -#define OFS_P9IN (0x0080) /*!< Port 9 Input */ -#define OFS_P10IN (0x0081) /*!< Port 10 Input */ -#define OFS_P9OUT (0x0082) /*!< Port 9 Output */ -#define OFS_P10OUT (0x0083) /*!< Port 10 Output */ -#define OFS_P9DIR (0x0084) /*!< Port 9 Direction */ -#define OFS_P10DIR (0x0085) /*!< Port 10 Direction */ -#define OFS_P9REN (0x0086) /*!< Port 9 Resistor Enable */ -#define OFS_P10REN (0x0087) /*!< Port 10 Resistor Enable */ -#define OFS_P9DS (0x0088) /*!< Port 9 Drive Strength */ -#define OFS_P10DS (0x0089) /*!< Port 10 Drive Strength */ -#define OFS_P9SEL0 (0x008A) /*!< Port 9 Select 0 */ -#define OFS_P10SEL0 (0x008B) /*!< Port 10 Select 0 */ -#define OFS_P9SEL1 (0x008C) /*!< Port 9 Select 1 */ -#define OFS_P10SEL1 (0x008D) /*!< Port 10 Select 1 */ -#define OFS_P9SELC (0x0096) /*!< Port 9 Complement Select */ -#define OFS_P10SELC (0x0097) /*!< Port 10 Complement Select */ -#define OFS_P9IES (0x0098) /*!< Port 9 Interrupt Edge Select */ -#define OFS_P10IES (0x0099) /*!< Port 10 Interrupt Edge Select */ -#define OFS_P9IE (0x009A) /*!< Port 9 Interrupt Enable */ -#define OFS_P10IE (0x009B) /*!< Port 10 Interrupt Enable */ -#define OFS_P9IFG (0x009C) /*!< Port 9 Interrupt Flag */ -#define OFS_P10IFG (0x009D) /*!< Port 10 Interrupt Flag */ - - -/****************************************************************************** -* EUSCI_A0 Registers -******************************************************************************/ -#define UCA0CTLW0 (HWREG16(0x40001000)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA0CTLW0_SPI (HWREG16(0x40001000)) -#define UCA0CTLW1 (HWREG16(0x40001002)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA0BRW (HWREG16(0x40001006)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA0BRW_SPI (HWREG16(0x40001006)) -#define UCA0MCTLW (HWREG16(0x40001008)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA0STATW (HWREG16(0x4000100A)) /*!< eUSCI_Ax Status Register */ -#define UCA0STATW_SPI (HWREG16(0x4000100A)) -#define UCA0RXBUF (HWREG16(0x4000100C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA0RXBUF_SPI (HWREG16(0x4000100C)) -#define UCA0TXBUF (HWREG16(0x4000100E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA0TXBUF_SPI (HWREG16(0x4000100E)) -#define UCA0ABCTL (HWREG16(0x40001010)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA0IRCTL (HWREG16(0x40001012)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA0IE (HWREG16(0x4000101A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA0IE_SPI (HWREG16(0x4000101A)) -#define UCA0IFG (HWREG16(0x4000101C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA0IFG_SPI (HWREG16(0x4000101C)) -#define UCA0IV (HWREG16(0x4000101E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA0IV_SPI (HWREG16(0x4000101E)) - -/* Register offsets from EUSCI_A0_BASE address */ -#define OFS_UCA0CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA0CTLW0_SPI (0x0000) -#define OFS_UCA0CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA0BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA0BRW_SPI (0x0006) -#define OFS_UCA0MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA0STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA0STATW_SPI (0x000A) -#define OFS_UCA0RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA0RXBUF_SPI (0x000C) -#define OFS_UCA0TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA0TXBUF_SPI (0x000E) -#define OFS_UCA0ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA0IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA0IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA0IE_SPI (0x001A) -#define OFS_UCA0IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA0IFG_SPI (0x001C) -#define OFS_UCA0IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA0IV_SPI (0x001E) - -#define UCA0CTL0 (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA0CTL1 (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA0BR0 (HWREG8_L(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA0BR1 (HWREG8_H(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA0IRTCTL (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA0IRRCTL (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A1 Registers -******************************************************************************/ -#define UCA1CTLW0 (HWREG16(0x40001400)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA1CTLW0_SPI (HWREG16(0x40001400)) -#define UCA1CTLW1 (HWREG16(0x40001402)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA1BRW (HWREG16(0x40001406)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA1BRW_SPI (HWREG16(0x40001406)) -#define UCA1MCTLW (HWREG16(0x40001408)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA1STATW (HWREG16(0x4000140A)) /*!< eUSCI_Ax Status Register */ -#define UCA1STATW_SPI (HWREG16(0x4000140A)) -#define UCA1RXBUF (HWREG16(0x4000140C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA1RXBUF_SPI (HWREG16(0x4000140C)) -#define UCA1TXBUF (HWREG16(0x4000140E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA1TXBUF_SPI (HWREG16(0x4000140E)) -#define UCA1ABCTL (HWREG16(0x40001410)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA1IRCTL (HWREG16(0x40001412)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA1IE (HWREG16(0x4000141A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA1IE_SPI (HWREG16(0x4000141A)) -#define UCA1IFG (HWREG16(0x4000141C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA1IFG_SPI (HWREG16(0x4000141C)) -#define UCA1IV (HWREG16(0x4000141E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA1IV_SPI (HWREG16(0x4000141E)) - -/* Register offsets from EUSCI_A1_BASE address */ -#define OFS_UCA1CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA1CTLW0_SPI (0x0000) -#define OFS_UCA1CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA1BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA1BRW_SPI (0x0006) -#define OFS_UCA1MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA1STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA1STATW_SPI (0x000A) -#define OFS_UCA1RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA1RXBUF_SPI (0x000C) -#define OFS_UCA1TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA1TXBUF_SPI (0x000E) -#define OFS_UCA1ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA1IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA1IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA1IE_SPI (0x001A) -#define OFS_UCA1IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA1IFG_SPI (0x001C) -#define OFS_UCA1IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA1IV_SPI (0x001E) - -#define UCA1CTL0 (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA1CTL1 (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA1BR0 (HWREG8_L(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA1BR1 (HWREG8_H(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA1IRTCTL (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA1IRRCTL (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A2 Registers -******************************************************************************/ -#define UCA2CTLW0 (HWREG16(0x40001800)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA2CTLW0_SPI (HWREG16(0x40001800)) -#define UCA2CTLW1 (HWREG16(0x40001802)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA2BRW (HWREG16(0x40001806)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA2BRW_SPI (HWREG16(0x40001806)) -#define UCA2MCTLW (HWREG16(0x40001808)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA2STATW (HWREG16(0x4000180A)) /*!< eUSCI_Ax Status Register */ -#define UCA2STATW_SPI (HWREG16(0x4000180A)) -#define UCA2RXBUF (HWREG16(0x4000180C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA2RXBUF_SPI (HWREG16(0x4000180C)) -#define UCA2TXBUF (HWREG16(0x4000180E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA2TXBUF_SPI (HWREG16(0x4000180E)) -#define UCA2ABCTL (HWREG16(0x40001810)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA2IRCTL (HWREG16(0x40001812)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA2IE (HWREG16(0x4000181A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA2IE_SPI (HWREG16(0x4000181A)) -#define UCA2IFG (HWREG16(0x4000181C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA2IFG_SPI (HWREG16(0x4000181C)) -#define UCA2IV (HWREG16(0x4000181E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA2IV_SPI (HWREG16(0x4000181E)) - -/* Register offsets from EUSCI_A2_BASE address */ -#define OFS_UCA2CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA2CTLW0_SPI (0x0000) -#define OFS_UCA2CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA2BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA2BRW_SPI (0x0006) -#define OFS_UCA2MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA2STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA2STATW_SPI (0x000A) -#define OFS_UCA2RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA2RXBUF_SPI (0x000C) -#define OFS_UCA2TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA2TXBUF_SPI (0x000E) -#define OFS_UCA2ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA2IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA2IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA2IE_SPI (0x001A) -#define OFS_UCA2IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA2IFG_SPI (0x001C) -#define OFS_UCA2IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA2IV_SPI (0x001E) - -#define UCA2CTL0 (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA2CTL1 (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA2BR0 (HWREG8_L(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA2BR1 (HWREG8_H(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA2IRTCTL (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA2IRRCTL (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A3 Registers -******************************************************************************/ -#define UCA3CTLW0 (HWREG16(0x40001C00)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA3CTLW0_SPI (HWREG16(0x40001C00)) -#define UCA3CTLW1 (HWREG16(0x40001C02)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA3BRW (HWREG16(0x40001C06)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA3BRW_SPI (HWREG16(0x40001C06)) -#define UCA3MCTLW (HWREG16(0x40001C08)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA3STATW (HWREG16(0x40001C0A)) /*!< eUSCI_Ax Status Register */ -#define UCA3STATW_SPI (HWREG16(0x40001C0A)) -#define UCA3RXBUF (HWREG16(0x40001C0C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA3RXBUF_SPI (HWREG16(0x40001C0C)) -#define UCA3TXBUF (HWREG16(0x40001C0E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA3TXBUF_SPI (HWREG16(0x40001C0E)) -#define UCA3ABCTL (HWREG16(0x40001C10)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA3IRCTL (HWREG16(0x40001C12)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA3IE (HWREG16(0x40001C1A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA3IE_SPI (HWREG16(0x40001C1A)) -#define UCA3IFG (HWREG16(0x40001C1C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA3IFG_SPI (HWREG16(0x40001C1C)) -#define UCA3IV (HWREG16(0x40001C1E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA3IV_SPI (HWREG16(0x40001C1E)) - -/* Register offsets from EUSCI_A3_BASE address */ -#define OFS_UCA3CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA3CTLW0_SPI (0x0000) -#define OFS_UCA3CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA3BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA3BRW_SPI (0x0006) -#define OFS_UCA3MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA3STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA3STATW_SPI (0x000A) -#define OFS_UCA3RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA3RXBUF_SPI (0x000C) -#define OFS_UCA3TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA3TXBUF_SPI (0x000E) -#define OFS_UCA3ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA3IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA3IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA3IE_SPI (0x001A) -#define OFS_UCA3IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA3IFG_SPI (0x001C) -#define OFS_UCA3IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA3IV_SPI (0x001E) - -#define UCA3CTL0 (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA3CTL1 (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA3BR0 (HWREG8_L(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA3BR1 (HWREG8_H(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA3IRTCTL (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA3IRRCTL (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_B0 Registers -******************************************************************************/ -#define UCB0CTLW0 (HWREG16(0x40002000)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB0CTLW0_SPI (HWREG16(0x40002000)) -#define UCB0CTLW1 (HWREG16(0x40002002)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB0BRW (HWREG16(0x40002006)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB0BRW_SPI (HWREG16(0x40002006)) -#define UCB0STATW (HWREG16(0x40002008)) /*!< eUSCI_Bx Status Register */ -#define UCB0STATW_SPI (HWREG16(0x40002008)) -#define UCB0TBCNT (HWREG16(0x4000200A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB0RXBUF (HWREG16(0x4000200C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB0RXBUF_SPI (HWREG16(0x4000200C)) -#define UCB0TXBUF (HWREG16(0x4000200E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB0TXBUF_SPI (HWREG16(0x4000200E)) -#define UCB0I2COA0 (HWREG16(0x40002014)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB0I2COA1 (HWREG16(0x40002016)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB0I2COA2 (HWREG16(0x40002018)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB0I2COA3 (HWREG16(0x4000201A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB0ADDRX (HWREG16(0x4000201C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB0ADDMASK (HWREG16(0x4000201E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB0I2CSA (HWREG16(0x40002020)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB0IE (HWREG16(0x4000202A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB0IE_SPI (HWREG16(0x4000202A)) -#define UCB0IFG (HWREG16(0x4000202C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB0IFG_SPI (HWREG16(0x4000202C)) -#define UCB0IV (HWREG16(0x4000202E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB0IV_SPI (HWREG16(0x4000202E)) - -/* Register offsets from EUSCI_B0_BASE address */ -#define OFS_UCB0CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB0CTLW0_SPI (0x0000) -#define OFS_UCB0CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB0BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB0BRW_SPI (0x0006) -#define OFS_UCB0STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB0STATW_SPI (0x0008) -#define OFS_UCB0TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB0RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB0RXBUF_SPI (0x000C) -#define OFS_UCB0TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB0TXBUF_SPI (0x000E) -#define OFS_UCB0I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB0I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB0I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB0I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB0ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB0ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB0I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB0IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB0IE_SPI (0x002A) -#define OFS_UCB0IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB0IFG_SPI (0x002C) -#define OFS_UCB0IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB0IV_SPI (0x002E) - -#define UCB0CTL0 (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB0CTL1 (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB0BR0 (HWREG8_L(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB0BR1 (HWREG8_H(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB0STAT (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */ -#define UCB0BCNT (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B1 Registers -******************************************************************************/ -#define UCB1CTLW0 (HWREG16(0x40002400)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB1CTLW0_SPI (HWREG16(0x40002400)) -#define UCB1CTLW1 (HWREG16(0x40002402)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB1BRW (HWREG16(0x40002406)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB1BRW_SPI (HWREG16(0x40002406)) -#define UCB1STATW (HWREG16(0x40002408)) /*!< eUSCI_Bx Status Register */ -#define UCB1STATW_SPI (HWREG16(0x40002408)) -#define UCB1TBCNT (HWREG16(0x4000240A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB1RXBUF (HWREG16(0x4000240C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB1RXBUF_SPI (HWREG16(0x4000240C)) -#define UCB1TXBUF (HWREG16(0x4000240E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB1TXBUF_SPI (HWREG16(0x4000240E)) -#define UCB1I2COA0 (HWREG16(0x40002414)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB1I2COA1 (HWREG16(0x40002416)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB1I2COA2 (HWREG16(0x40002418)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB1I2COA3 (HWREG16(0x4000241A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB1ADDRX (HWREG16(0x4000241C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB1ADDMASK (HWREG16(0x4000241E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB1I2CSA (HWREG16(0x40002420)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB1IE (HWREG16(0x4000242A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB1IE_SPI (HWREG16(0x4000242A)) -#define UCB1IFG (HWREG16(0x4000242C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB1IFG_SPI (HWREG16(0x4000242C)) -#define UCB1IV (HWREG16(0x4000242E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB1IV_SPI (HWREG16(0x4000242E)) - -/* Register offsets from EUSCI_B1_BASE address */ -#define OFS_UCB1CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB1CTLW0_SPI (0x0000) -#define OFS_UCB1CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB1BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB1BRW_SPI (0x0006) -#define OFS_UCB1STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB1STATW_SPI (0x0008) -#define OFS_UCB1TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB1RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB1RXBUF_SPI (0x000C) -#define OFS_UCB1TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB1TXBUF_SPI (0x000E) -#define OFS_UCB1I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB1I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB1I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB1I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB1ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB1ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB1I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB1IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB1IE_SPI (0x002A) -#define OFS_UCB1IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB1IFG_SPI (0x002C) -#define OFS_UCB1IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB1IV_SPI (0x002E) - -#define UCB1CTL0 (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB1CTL1 (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB1BR0 (HWREG8_L(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB1BR1 (HWREG8_H(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB1STAT (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */ -#define UCB1BCNT (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B2 Registers -******************************************************************************/ -#define UCB2CTLW0 (HWREG16(0x40002800)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB2CTLW0_SPI (HWREG16(0x40002800)) -#define UCB2CTLW1 (HWREG16(0x40002802)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB2BRW (HWREG16(0x40002806)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB2BRW_SPI (HWREG16(0x40002806)) -#define UCB2STATW (HWREG16(0x40002808)) /*!< eUSCI_Bx Status Register */ -#define UCB2STATW_SPI (HWREG16(0x40002808)) -#define UCB2TBCNT (HWREG16(0x4000280A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB2RXBUF (HWREG16(0x4000280C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB2RXBUF_SPI (HWREG16(0x4000280C)) -#define UCB2TXBUF (HWREG16(0x4000280E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB2TXBUF_SPI (HWREG16(0x4000280E)) -#define UCB2I2COA0 (HWREG16(0x40002814)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB2I2COA1 (HWREG16(0x40002816)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB2I2COA2 (HWREG16(0x40002818)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB2I2COA3 (HWREG16(0x4000281A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB2ADDRX (HWREG16(0x4000281C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB2ADDMASK (HWREG16(0x4000281E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB2I2CSA (HWREG16(0x40002820)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB2IE (HWREG16(0x4000282A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB2IE_SPI (HWREG16(0x4000282A)) -#define UCB2IFG (HWREG16(0x4000282C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB2IFG_SPI (HWREG16(0x4000282C)) -#define UCB2IV (HWREG16(0x4000282E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB2IV_SPI (HWREG16(0x4000282E)) - -/* Register offsets from EUSCI_B2_BASE address */ -#define OFS_UCB2CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB2CTLW0_SPI (0x0000) -#define OFS_UCB2CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB2BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB2BRW_SPI (0x0006) -#define OFS_UCB2STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB2STATW_SPI (0x0008) -#define OFS_UCB2TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB2RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB2RXBUF_SPI (0x000C) -#define OFS_UCB2TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB2TXBUF_SPI (0x000E) -#define OFS_UCB2I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB2I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB2I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB2I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB2ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB2ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB2I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB2IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB2IE_SPI (0x002A) -#define OFS_UCB2IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB2IFG_SPI (0x002C) -#define OFS_UCB2IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB2IV_SPI (0x002E) - -#define UCB2CTL0 (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB2CTL1 (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB2BR0 (HWREG8_L(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB2BR1 (HWREG8_H(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB2STAT (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */ -#define UCB2BCNT (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B3 Registers -******************************************************************************/ -#define UCB3CTLW0 (HWREG16(0x40002C00)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB3CTLW0_SPI (HWREG16(0x40002C00)) -#define UCB3CTLW1 (HWREG16(0x40002C02)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB3BRW (HWREG16(0x40002C06)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB3BRW_SPI (HWREG16(0x40002C06)) -#define UCB3STATW (HWREG16(0x40002C08)) /*!< eUSCI_Bx Status Register */ -#define UCB3STATW_SPI (HWREG16(0x40002C08)) -#define UCB3TBCNT (HWREG16(0x40002C0A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB3RXBUF (HWREG16(0x40002C0C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB3RXBUF_SPI (HWREG16(0x40002C0C)) -#define UCB3TXBUF (HWREG16(0x40002C0E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB3TXBUF_SPI (HWREG16(0x40002C0E)) -#define UCB3I2COA0 (HWREG16(0x40002C14)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB3I2COA1 (HWREG16(0x40002C16)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB3I2COA2 (HWREG16(0x40002C18)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB3I2COA3 (HWREG16(0x40002C1A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB3ADDRX (HWREG16(0x40002C1C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB3ADDMASK (HWREG16(0x40002C1E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB3I2CSA (HWREG16(0x40002C20)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB3IE (HWREG16(0x40002C2A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB3IE_SPI (HWREG16(0x40002C2A)) -#define UCB3IFG (HWREG16(0x40002C2C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB3IFG_SPI (HWREG16(0x40002C2C)) -#define UCB3IV (HWREG16(0x40002C2E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB3IV_SPI (HWREG16(0x40002C2E)) - -/* Register offsets from EUSCI_B3_BASE address */ -#define OFS_UCB3CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB3CTLW0_SPI (0x0000) -#define OFS_UCB3CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB3BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB3BRW_SPI (0x0006) -#define OFS_UCB3STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB3STATW_SPI (0x0008) -#define OFS_UCB3TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB3RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB3RXBUF_SPI (0x000C) -#define OFS_UCB3TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB3TXBUF_SPI (0x000E) -#define OFS_UCB3I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB3I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB3I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB3I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB3ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB3ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB3I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB3IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB3IE_SPI (0x002A) -#define OFS_UCB3IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB3IFG_SPI (0x002C) -#define OFS_UCB3IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB3IV_SPI (0x002E) - -#define UCB3CTL0 (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB3CTL1 (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB3BR0 (HWREG8_L(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB3BR1 (HWREG8_H(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB3STAT (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */ -#define UCB3BCNT (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -#define PMAPKEYID (HWREG16(0x40005000)) /*!< Port Mapping Key Register */ -#define PMAPCTL (HWREG16(0x40005002)) /*!< Port Mapping Control Register */ -#define P1MAP01 (HWREG16(0x40005008)) /*!< Port mapping register, P1.0 and P1.1 */ -#define P1MAP23 (HWREG16(0x4000500A)) /*!< Port mapping register, P1.2 and P1.3 */ -#define P1MAP45 (HWREG16(0x4000500C)) /*!< Port mapping register, P1.4 and P1.5 */ -#define P1MAP67 (HWREG16(0x4000500E)) /*!< Port mapping register, P1.6 and P1.7 */ -#define P2MAP01 (HWREG16(0x40005010)) /*!< Port mapping register, P2.0 and P2.1 */ -#define P2MAP23 (HWREG16(0x40005012)) /*!< Port mapping register, P2.2 and P2.3 */ -#define P2MAP45 (HWREG16(0x40005014)) /*!< Port mapping register, P2.4 and P2.5 */ -#define P2MAP67 (HWREG16(0x40005016)) /*!< Port mapping register, P2.6 and P2.7 */ -#define P3MAP01 (HWREG16(0x40005018)) /*!< Port mapping register, P3.0 and P3.1 */ -#define P3MAP23 (HWREG16(0x4000501A)) /*!< Port mapping register, P3.2 and P3.3 */ -#define P3MAP45 (HWREG16(0x4000501C)) /*!< Port mapping register, P3.4 and P3.5 */ -#define P3MAP67 (HWREG16(0x4000501E)) /*!< Port mapping register, P3.6 and P3.7 */ -#define P4MAP01 (HWREG16(0x40005020)) /*!< Port mapping register, P4.0 and P4.1 */ -#define P4MAP23 (HWREG16(0x40005022)) /*!< Port mapping register, P4.2 and P4.3 */ -#define P4MAP45 (HWREG16(0x40005024)) /*!< Port mapping register, P4.4 and P4.5 */ -#define P4MAP67 (HWREG16(0x40005026)) /*!< Port mapping register, P4.6 and P4.7 */ -#define P5MAP01 (HWREG16(0x40005028)) /*!< Port mapping register, P5.0 and P5.1 */ -#define P5MAP23 (HWREG16(0x4000502A)) /*!< Port mapping register, P5.2 and P5.3 */ -#define P5MAP45 (HWREG16(0x4000502C)) /*!< Port mapping register, P5.4 and P5.5 */ -#define P5MAP67 (HWREG16(0x4000502E)) /*!< Port mapping register, P5.6 and P5.7 */ -#define P6MAP01 (HWREG16(0x40005030)) /*!< Port mapping register, P6.0 and P6.1 */ -#define P6MAP23 (HWREG16(0x40005032)) /*!< Port mapping register, P6.2 and P6.3 */ -#define P6MAP45 (HWREG16(0x40005034)) /*!< Port mapping register, P6.4 and P6.5 */ -#define P6MAP67 (HWREG16(0x40005036)) /*!< Port mapping register, P6.6 and P6.7 */ -#define P7MAP01 (HWREG16(0x40005038)) /*!< Port mapping register, P7.0 and P7.1 */ -#define P7MAP23 (HWREG16(0x4000503A)) /*!< Port mapping register, P7.2 and P7.3 */ -#define P7MAP45 (HWREG16(0x4000503C)) /*!< Port mapping register, P7.4 and P7.5 */ -#define P7MAP67 (HWREG16(0x4000503E)) /*!< Port mapping register, P7.6 and P7.7 */ - -/* Register offsets from PMAP_BASE address */ -#define OFS_PMAPKEYID (0x0000) /*!< Port Mapping Key Register */ -#define OFS_PMAPCTL (0x0002) /*!< Port Mapping Control Register */ -#define OFS_P1MAP01 (0x0008) /*!< Port mapping register, P1.0 and P1.1 */ -#define OFS_P1MAP23 (0x000A) /*!< Port mapping register, P1.2 and P1.3 */ -#define OFS_P1MAP45 (0x000C) /*!< Port mapping register, P1.4 and P1.5 */ -#define OFS_P1MAP67 (0x000E) /*!< Port mapping register, P1.6 and P1.7 */ -#define OFS_P2MAP01 (0x0010) /*!< Port mapping register, P2.0 and P2.1 */ -#define OFS_P2MAP23 (0x0012) /*!< Port mapping register, P2.2 and P2.3 */ -#define OFS_P2MAP45 (0x0014) /*!< Port mapping register, P2.4 and P2.5 */ -#define OFS_P2MAP67 (0x0016) /*!< Port mapping register, P2.6 and P2.7 */ -#define OFS_P3MAP01 (0x0018) /*!< Port mapping register, P3.0 and P3.1 */ -#define OFS_P3MAP23 (0x001A) /*!< Port mapping register, P3.2 and P3.3 */ -#define OFS_P3MAP45 (0x001C) /*!< Port mapping register, P3.4 and P3.5 */ -#define OFS_P3MAP67 (0x001E) /*!< Port mapping register, P3.6 and P3.7 */ -#define OFS_P4MAP01 (0x0020) /*!< Port mapping register, P4.0 and P4.1 */ -#define OFS_P4MAP23 (0x0022) /*!< Port mapping register, P4.2 and P4.3 */ -#define OFS_P4MAP45 (0x0024) /*!< Port mapping register, P4.4 and P4.5 */ -#define OFS_P4MAP67 (0x0026) /*!< Port mapping register, P4.6 and P4.7 */ -#define OFS_P5MAP01 (0x0028) /*!< Port mapping register, P5.0 and P5.1 */ -#define OFS_P5MAP23 (0x002A) /*!< Port mapping register, P5.2 and P5.3 */ -#define OFS_P5MAP45 (0x002C) /*!< Port mapping register, P5.4 and P5.5 */ -#define OFS_P5MAP67 (0x002E) /*!< Port mapping register, P5.6 and P5.7 */ -#define OFS_P6MAP01 (0x0030) /*!< Port mapping register, P6.0 and P6.1 */ -#define OFS_P6MAP23 (0x0032) /*!< Port mapping register, P6.2 and P6.3 */ -#define OFS_P6MAP45 (0x0034) /*!< Port mapping register, P6.4 and P6.5 */ -#define OFS_P6MAP67 (0x0036) /*!< Port mapping register, P6.6 and P6.7 */ -#define OFS_P7MAP01 (0x0038) /*!< Port mapping register, P7.0 and P7.1 */ -#define OFS_P7MAP23 (0x003A) /*!< Port mapping register, P7.2 and P7.3 */ -#define OFS_P7MAP45 (0x003C) /*!< Port mapping register, P7.4 and P7.5 */ -#define OFS_P7MAP67 (0x003E) /*!< Port mapping register, P7.6 and P7.7 */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -#define REFCTL0 (HWREG16(0x40003000)) /*!< REF Control Register 0 */ - -/* Register offsets from REF_A_BASE address */ -#define OFS_REFCTL0 (0x0000) /*!< REF Control Register 0 */ - -#define REFCTL0_L (HWREG8_L(REFCTL0)) /* REF Control Register 0 */ -#define REFCTL0_H (HWREG8_H(REFCTL0)) /* REF Control Register 0 */ - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -#define RTCCTL0 (HWREG16(0x40004400)) /*!< RTCCTL0 Register */ -#define RTCCTL13 (HWREG16(0x40004402)) /*!< RTCCTL13 Register */ -#define RTCOCAL (HWREG16(0x40004404)) /*!< RTCOCAL Register */ -#define RTCTCMP (HWREG16(0x40004406)) /*!< RTCTCMP Register */ -#define RTCPS0CTL (HWREG16(0x40004408)) /*!< Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS1CTL (HWREG16(0x4000440A)) /*!< Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS (HWREG16(0x4000440C)) /*!< Real-Time Clock Prescale Timer Counter Register */ -#define RTCIV (HWREG16(0x4000440E)) /*!< Real-Time Clock Interrupt Vector Register */ -#define RTCTIM0 (HWREG16(0x40004410)) /*!< RTCTIM0 Register Hexadecimal Format */ -#define RTCTIM0_BCD (HWREG16(0x40004410)) -#define RTCTIM1 (HWREG16(0x40004412)) /*!< Real-Time Clock Hour, Day of Week */ -#define RTCTIM1_BCD (HWREG16(0x40004412)) -#define RTCDATE (HWREG16(0x40004414)) /*!< RTCDATE - Hexadecimal Format */ -#define RTCDATE_BCD (HWREG16(0x40004414)) -#define RTCYEAR (HWREG16(0x40004416)) /*!< RTCYEAR Register Hexadecimal Format */ -#define RTCYEAR_BCD (HWREG16(0x40004416)) -#define RTCAMINHR (HWREG16(0x40004418)) /*!< RTCMINHR - Hexadecimal Format */ -#define RTCAMINHR_BCD (HWREG16(0x40004418)) -#define RTCADOWDAY (HWREG16(0x4000441A)) /*!< RTCADOWDAY - Hexadecimal Format */ -#define RTCADOWDAY_BCD (HWREG16(0x4000441A)) -#define RTCBIN2BCD (HWREG16(0x4000441C)) /*!< Binary-to-BCD Conversion Register */ -#define RTCBCD2BIN (HWREG16(0x4000441E)) /*!< BCD-to-Binary Conversion Register */ - -/* Register offsets from RTC_C_BASE address */ -#define OFS_RTCCTL0 (0x0000) /*!< RTCCTL0 Register */ -#define OFS_RTCCTL13 (0x0002) /*!< RTCCTL13 Register */ -#define OFS_RTCOCAL (0x0004) /*!< RTCOCAL Register */ -#define OFS_RTCTCMP (0x0006) /*!< RTCTCMP Register */ -#define OFS_RTCPS0CTL (0x0008) /*!< Real-Time Clock Prescale Timer 0 Control Register */ -#define OFS_RTCPS1CTL (0x000A) /*!< Real-Time Clock Prescale Timer 1 Control Register */ -#define OFS_RTCPS (0x000C) /*!< Real-Time Clock Prescale Timer Counter Register */ -#define OFS_RTCIV (0x000E) /*!< Real-Time Clock Interrupt Vector Register */ -#define OFS_RTCTIM0 (0x0010) /*!< RTCTIM0 Register Hexadecimal Format */ -#define OFS_RTCTIM0_BCD (0x0010) -#define OFS_RTCTIM1 (0x0012) /*!< Real-Time Clock Hour, Day of Week */ -#define OFS_RTCTIM1_BCD (0x0012) -#define OFS_RTCDATE (0x0014) /*!< RTCDATE - Hexadecimal Format */ -#define OFS_RTCDATE_BCD (0x0014) -#define OFS_RTCYEAR (0x0016) /*!< RTCYEAR Register Hexadecimal Format */ -#define OFS_RTCYEAR_BCD (0x0016) -#define OFS_RTCAMINHR (0x0018) /*!< RTCMINHR - Hexadecimal Format */ -#define OFS_RTCAMINHR_BCD (0x0018) -#define OFS_RTCADOWDAY (0x001A) /*!< RTCADOWDAY - Hexadecimal Format */ -#define OFS_RTCADOWDAY_BCD (0x001A) -#define OFS_RTCBIN2BCD (0x001C) /*!< Binary-to-BCD Conversion Register */ -#define OFS_RTCBCD2BIN (0x001E) /*!< BCD-to-Binary Conversion Register */ - -#define RTCCTL0_L (HWREG8_L(RTCCTL0)) /* RTCCTL0 Register */ -#define RTCCTL0_H (HWREG8_H(RTCCTL0)) /* RTCCTL0 Register */ -#define RTCCTL1 (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL13_L (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL3 (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL13_H (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCOCAL_L (HWREG8_L(RTCOCAL)) /* RTCOCAL Register */ -#define RTCOCAL_H (HWREG8_H(RTCOCAL)) /* RTCOCAL Register */ -#define RTCTCMP_L (HWREG8_L(RTCTCMP)) /* RTCTCMP Register */ -#define RTCTCMP_H (HWREG8_H(RTCTCMP)) /* RTCTCMP Register */ -#define RTCPS0CTL_L (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS0CTL_H (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS1CTL_L (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS1CTL_H (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS0 (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS_L (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS1 (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS_H (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCSEC (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */ -#define RTCTIM0_L (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */ -#define RTCMIN (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */ -#define RTCTIM0_H (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */ -#define RTCHOUR (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */ -#define RTCTIM1_L (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */ -#define RTCDOW (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */ -#define RTCTIM1_H (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */ -#define RTCDAY (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */ -#define RTCDATE_L (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */ -#define RTCMON (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */ -#define RTCDATE_H (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */ -#define RTCAMIN (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */ -#define RTCAMINHR_L (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */ -#define RTCAHOUR (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */ -#define RTCAMINHR_H (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */ -#define RTCADOW (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */ -#define RTCADOWDAY_L (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */ -#define RTCADAY (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */ -#define RTCADOWDAY_H (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */ - -/****************************************************************************** -* TIMER_A0 Registers -******************************************************************************/ -#define TA0CTL (HWREG16(0x40000000)) /*!< TimerAx Control Register */ -#define TA0CCTL0 (HWREG16(0x40000002)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL1 (HWREG16(0x40000004)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL2 (HWREG16(0x40000006)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL3 (HWREG16(0x40000008)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL4 (HWREG16(0x4000000A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0R (HWREG16(0x40000010)) /*!< TimerA register */ -#define TA0CCR0 (HWREG16(0x40000012)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR1 (HWREG16(0x40000014)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR2 (HWREG16(0x40000016)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR3 (HWREG16(0x40000018)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR4 (HWREG16(0x4000001A)) /*!< Timer_A Capture/Compare Register */ -#define TA0EX0 (HWREG16(0x40000020)) /*!< TimerAx Expansion 0 Register */ -#define TA0IV (HWREG16(0x4000002E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A0_BASE address */ -#define OFS_TA0CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA0CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0R (0x0010) /*!< TimerA register */ -#define OFS_TA0CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA0IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A1 Registers -******************************************************************************/ -#define TA1CTL (HWREG16(0x40000400)) /*!< TimerAx Control Register */ -#define TA1CCTL0 (HWREG16(0x40000402)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL1 (HWREG16(0x40000404)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL2 (HWREG16(0x40000406)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL3 (HWREG16(0x40000408)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL4 (HWREG16(0x4000040A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1R (HWREG16(0x40000410)) /*!< TimerA register */ -#define TA1CCR0 (HWREG16(0x40000412)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR1 (HWREG16(0x40000414)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR2 (HWREG16(0x40000416)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR3 (HWREG16(0x40000418)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR4 (HWREG16(0x4000041A)) /*!< Timer_A Capture/Compare Register */ -#define TA1EX0 (HWREG16(0x40000420)) /*!< TimerAx Expansion 0 Register */ -#define TA1IV (HWREG16(0x4000042E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A1_BASE address */ -#define OFS_TA1CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA1CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1R (0x0010) /*!< TimerA register */ -#define OFS_TA1CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA1IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A2 Registers -******************************************************************************/ -#define TA2CTL (HWREG16(0x40000800)) /*!< TimerAx Control Register */ -#define TA2CCTL0 (HWREG16(0x40000802)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL1 (HWREG16(0x40000804)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL2 (HWREG16(0x40000806)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL3 (HWREG16(0x40000808)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL4 (HWREG16(0x4000080A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2R (HWREG16(0x40000810)) /*!< TimerA register */ -#define TA2CCR0 (HWREG16(0x40000812)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR1 (HWREG16(0x40000814)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR2 (HWREG16(0x40000816)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR3 (HWREG16(0x40000818)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR4 (HWREG16(0x4000081A)) /*!< Timer_A Capture/Compare Register */ -#define TA2EX0 (HWREG16(0x40000820)) /*!< TimerAx Expansion 0 Register */ -#define TA2IV (HWREG16(0x4000082E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A2_BASE address */ -#define OFS_TA2CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA2CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2R (0x0010) /*!< TimerA register */ -#define OFS_TA2CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA2IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A3 Registers -******************************************************************************/ -#define TA3CTL (HWREG16(0x40000C00)) /*!< TimerAx Control Register */ -#define TA3CCTL0 (HWREG16(0x40000C02)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL1 (HWREG16(0x40000C04)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL2 (HWREG16(0x40000C06)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL3 (HWREG16(0x40000C08)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL4 (HWREG16(0x40000C0A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3R (HWREG16(0x40000C10)) /*!< TimerA register */ -#define TA3CCR0 (HWREG16(0x40000C12)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR1 (HWREG16(0x40000C14)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR2 (HWREG16(0x40000C16)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR3 (HWREG16(0x40000C18)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR4 (HWREG16(0x40000C1A)) /*!< Timer_A Capture/Compare Register */ -#define TA3EX0 (HWREG16(0x40000C20)) /*!< TimerAx Expansion 0 Register */ -#define TA3IV (HWREG16(0x40000C2E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A3_BASE address */ -#define OFS_TA3CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA3CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3R (0x0010) /*!< TimerA register */ -#define OFS_TA3CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA3IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -#define WDTCTL (HWREG16(0x4000480C)) /*!< Watchdog Timer Control Register */ - -/* Register offsets from WDT_A_BASE address */ -#define OFS_WDTCTL (0x000C) /*!< Watchdog Timer Control Register */ - - -/****************************************************************************** -* Peripheral register control bits (legacy section) * -******************************************************************************/ - -/****************************************************************************** -* AES256 Bits (legacy section) -******************************************************************************/ -/* AESACTL0[AESOP] Bits */ -#define AESOP_OFS AES256_CTL0_OP_OFS /*!< AESOP Offset */ -#define AESOP_M AES256_CTL0_OP_MASK /*!< AES operation */ -#define AESOP0 AES256_CTL0_OP0 /*!< AESOP Bit 0 */ -#define AESOP1 AES256_CTL0_OP1 /*!< AESOP Bit 1 */ -#define AESOP_0 AES256_CTL0_OP_0 /*!< Encryption */ -#define AESOP_1 AES256_CTL0_OP_1 /*!< Decryption. The provided key is the same key used for encryption */ -#define AESOP_2 AES256_CTL0_OP_2 /*!< Generate first round key required for decryption */ -#define AESOP_3 AES256_CTL0_OP_3 /*!< Decryption. The provided key is the first round key required for decryption */ -/* AESACTL0[AESKL] Bits */ -#define AESKL_OFS AES256_CTL0_KL_OFS /*!< AESKL Offset */ -#define AESKL_M AES256_CTL0_KL_MASK /*!< AES key length */ -#define AESKL0 AES256_CTL0_KL0 /*!< AESKL Bit 0 */ -#define AESKL1 AES256_CTL0_KL1 /*!< AESKL Bit 1 */ -#define AESKL_0 AES256_CTL0_KL_0 /*!< AES128. The key size is 128 bit */ -#define AESKL_1 AES256_CTL0_KL_1 /*!< AES192. The key size is 192 bit. */ -#define AESKL_2 AES256_CTL0_KL_2 /*!< AES256. The key size is 256 bit */ -#define AESKL__128BIT AES256_CTL0_KL__128BIT /*!< AES128. The key size is 128 bit */ -#define AESKL__192BIT AES256_CTL0_KL__192BIT /*!< AES192. The key size is 192 bit. */ -#define AESKL__256BIT AES256_CTL0_KL__256BIT /*!< AES256. The key size is 256 bit */ -/* AESACTL0[AESCM] Bits */ -#define AESCM_OFS AES256_CTL0_CM_OFS /*!< AESCM Offset */ -#define AESCM_M AES256_CTL0_CM_MASK /*!< AES cipher mode select */ -#define AESCM0 AES256_CTL0_CM0 /*!< AESCM Bit 0 */ -#define AESCM1 AES256_CTL0_CM1 /*!< AESCM Bit 1 */ -#define AESCM_0 AES256_CTL0_CM_0 /*!< ECB */ -#define AESCM_1 AES256_CTL0_CM_1 /*!< CBC */ -#define AESCM_2 AES256_CTL0_CM_2 /*!< OFB */ -#define AESCM_3 AES256_CTL0_CM_3 /*!< CFB */ -#define AESCM__ECB AES256_CTL0_CM__ECB /*!< ECB */ -#define AESCM__CBC AES256_CTL0_CM__CBC /*!< CBC */ -#define AESCM__OFB AES256_CTL0_CM__OFB /*!< OFB */ -#define AESCM__CFB AES256_CTL0_CM__CFB /*!< CFB */ -/* AESACTL0[AESSWRST] Bits */ -#define AESSWRST_OFS AES256_CTL0_SWRST_OFS /*!< AESSWRST Offset */ -#define AESSWRST AES256_CTL0_SWRST /*!< AES software reset */ -/* AESACTL0[AESRDYIFG] Bits */ -#define AESRDYIFG_OFS AES256_CTL0_RDYIFG_OFS /*!< AESRDYIFG Offset */ -#define AESRDYIFG AES256_CTL0_RDYIFG /*!< AES ready interrupt flag */ -/* AESACTL0[AESERRFG] Bits */ -#define AESERRFG_OFS AES256_CTL0_ERRFG_OFS /*!< AESERRFG Offset */ -#define AESERRFG AES256_CTL0_ERRFG /*!< AES error flag */ -/* AESACTL0[AESRDYIE] Bits */ -#define AESRDYIE_OFS AES256_CTL0_RDYIE_OFS /*!< AESRDYIE Offset */ -#define AESRDYIE AES256_CTL0_RDYIE /*!< AES ready interrupt enable */ -/* AESACTL0[AESCMEN] Bits */ -#define AESCMEN_OFS AES256_CTL0_CMEN_OFS /*!< AESCMEN Offset */ -#define AESCMEN AES256_CTL0_CMEN /*!< AES cipher mode enable */ -/* AESACTL1[AESBLKCNT] Bits */ -#define AESBLKCNT_OFS AES256_CTL1_BLKCNT_OFS /*!< AESBLKCNT Offset */ -#define AESBLKCNT_M AES256_CTL1_BLKCNT_MASK /*!< Cipher Block Counter */ -#define AESBLKCNT0 AES256_CTL1_BLKCNT0 /*!< AESBLKCNT Bit 0 */ -#define AESBLKCNT1 AES256_CTL1_BLKCNT1 /*!< AESBLKCNT Bit 1 */ -#define AESBLKCNT2 AES256_CTL1_BLKCNT2 /*!< AESBLKCNT Bit 2 */ -#define AESBLKCNT3 AES256_CTL1_BLKCNT3 /*!< AESBLKCNT Bit 3 */ -#define AESBLKCNT4 AES256_CTL1_BLKCNT4 /*!< AESBLKCNT Bit 4 */ -#define AESBLKCNT5 AES256_CTL1_BLKCNT5 /*!< AESBLKCNT Bit 5 */ -#define AESBLKCNT6 AES256_CTL1_BLKCNT6 /*!< AESBLKCNT Bit 6 */ -#define AESBLKCNT7 AES256_CTL1_BLKCNT7 /*!< AESBLKCNT Bit 7 */ -/* AESASTAT[AESBUSY] Bits */ -#define AESBUSY_OFS AES256_STAT_BUSY_OFS /*!< AESBUSY Offset */ -#define AESBUSY AES256_STAT_BUSY /*!< AES accelerator module busy */ -/* AESASTAT[AESKEYWR] Bits */ -#define AESKEYWR_OFS AES256_STAT_KEYWR_OFS /*!< AESKEYWR Offset */ -#define AESKEYWR AES256_STAT_KEYWR /*!< All 16 bytes written to AESAKEY */ -/* AESASTAT[AESDINWR] Bits */ -#define AESDINWR_OFS AES256_STAT_DINWR_OFS /*!< AESDINWR Offset */ -#define AESDINWR AES256_STAT_DINWR /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AESASTAT[AESDOUTRD] Bits */ -#define AESDOUTRD_OFS AES256_STAT_DOUTRD_OFS /*!< AESDOUTRD Offset */ -#define AESDOUTRD AES256_STAT_DOUTRD /*!< All 16 bytes read from AESADOUT */ -/* AESASTAT[AESKEYCNT] Bits */ -#define AESKEYCNT_OFS AES256_STAT_KEYCNT_OFS /*!< AESKEYCNT Offset */ -#define AESKEYCNT_M AES256_STAT_KEYCNT_MASK /*!< Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */ -#define AESKEYCNT0 AES256_STAT_KEYCNT0 /*!< AESKEYCNT Bit 0 */ -#define AESKEYCNT1 AES256_STAT_KEYCNT1 /*!< AESKEYCNT Bit 1 */ -#define AESKEYCNT2 AES256_STAT_KEYCNT2 /*!< AESKEYCNT Bit 2 */ -#define AESKEYCNT3 AES256_STAT_KEYCNT3 /*!< AESKEYCNT Bit 3 */ -/* AESASTAT[AESDINCNT] Bits */ -#define AESDINCNT_OFS AES256_STAT_DINCNT_OFS /*!< AESDINCNT Offset */ -#define AESDINCNT_M AES256_STAT_DINCNT_MASK /*!< Bytes written via AESADIN, AESAXDIN or AESAXIN */ -#define AESDINCNT0 AES256_STAT_DINCNT0 /*!< AESDINCNT Bit 0 */ -#define AESDINCNT1 AES256_STAT_DINCNT1 /*!< AESDINCNT Bit 1 */ -#define AESDINCNT2 AES256_STAT_DINCNT2 /*!< AESDINCNT Bit 2 */ -#define AESDINCNT3 AES256_STAT_DINCNT3 /*!< AESDINCNT Bit 3 */ -/* AESASTAT[AESDOUTCNT] Bits */ -#define AESDOUTCNT_OFS AES256_STAT_DOUTCNT_OFS /*!< AESDOUTCNT Offset */ -#define AESDOUTCNT_M AES256_STAT_DOUTCNT_MASK /*!< Bytes read via AESADOUT */ -#define AESDOUTCNT0 AES256_STAT_DOUTCNT0 /*!< AESDOUTCNT Bit 0 */ -#define AESDOUTCNT1 AES256_STAT_DOUTCNT1 /*!< AESDOUTCNT Bit 1 */ -#define AESDOUTCNT2 AES256_STAT_DOUTCNT2 /*!< AESDOUTCNT Bit 2 */ -#define AESDOUTCNT3 AES256_STAT_DOUTCNT3 /*!< AESDOUTCNT Bit 3 */ -/* AESAKEY[AESKEY0] Bits */ -#define AESKEY0_OFS AES256_KEY_KEY0_OFS /*!< AESKEY0 Offset */ -#define AESKEY0_M AES256_KEY_KEY0_MASK /*!< AES key byte n when AESAKEY is written as half-word */ -#define AESKEY00 AES256_KEY_KEY00 /*!< AESKEY0 Bit 0 */ -#define AESKEY01 AES256_KEY_KEY01 /*!< AESKEY0 Bit 1 */ -#define AESKEY02 AES256_KEY_KEY02 /*!< AESKEY0 Bit 2 */ -#define AESKEY03 AES256_KEY_KEY03 /*!< AESKEY0 Bit 3 */ -#define AESKEY04 AES256_KEY_KEY04 /*!< AESKEY0 Bit 4 */ -#define AESKEY05 AES256_KEY_KEY05 /*!< AESKEY0 Bit 5 */ -#define AESKEY06 AES256_KEY_KEY06 /*!< AESKEY0 Bit 6 */ -#define AESKEY07 AES256_KEY_KEY07 /*!< AESKEY0 Bit 7 */ -/* AESAKEY[AESKEY1] Bits */ -#define AESKEY1_OFS AES256_KEY_KEY1_OFS /*!< AESKEY1 Offset */ -#define AESKEY1_M AES256_KEY_KEY1_MASK /*!< AES key byte n+1 when AESAKEY is written as half-word */ -#define AESKEY10 AES256_KEY_KEY10 /*!< AESKEY1 Bit 0 */ -#define AESKEY11 AES256_KEY_KEY11 /*!< AESKEY1 Bit 1 */ -#define AESKEY12 AES256_KEY_KEY12 /*!< AESKEY1 Bit 2 */ -#define AESKEY13 AES256_KEY_KEY13 /*!< AESKEY1 Bit 3 */ -#define AESKEY14 AES256_KEY_KEY14 /*!< AESKEY1 Bit 4 */ -#define AESKEY15 AES256_KEY_KEY15 /*!< AESKEY1 Bit 5 */ -#define AESKEY16 AES256_KEY_KEY16 /*!< AESKEY1 Bit 6 */ -#define AESKEY17 AES256_KEY_KEY17 /*!< AESKEY1 Bit 7 */ -/* AESADIN[AESDIN0] Bits */ -#define AESDIN0_OFS AES256_DIN_DIN0_OFS /*!< AESDIN0 Offset */ -#define AESDIN0_M AES256_DIN_DIN0_MASK /*!< AES data in byte n when AESADIN is written as half-word */ -#define AESDIN00 AES256_DIN_DIN00 /*!< AESDIN0 Bit 0 */ -#define AESDIN01 AES256_DIN_DIN01 /*!< AESDIN0 Bit 1 */ -#define AESDIN02 AES256_DIN_DIN02 /*!< AESDIN0 Bit 2 */ -#define AESDIN03 AES256_DIN_DIN03 /*!< AESDIN0 Bit 3 */ -#define AESDIN04 AES256_DIN_DIN04 /*!< AESDIN0 Bit 4 */ -#define AESDIN05 AES256_DIN_DIN05 /*!< AESDIN0 Bit 5 */ -#define AESDIN06 AES256_DIN_DIN06 /*!< AESDIN0 Bit 6 */ -#define AESDIN07 AES256_DIN_DIN07 /*!< AESDIN0 Bit 7 */ -/* AESADIN[AESDIN1] Bits */ -#define AESDIN1_OFS AES256_DIN_DIN1_OFS /*!< AESDIN1 Offset */ -#define AESDIN1_M AES256_DIN_DIN1_MASK /*!< AES data in byte n+1 when AESADIN is written as half-word */ -#define AESDIN10 AES256_DIN_DIN10 /*!< AESDIN1 Bit 0 */ -#define AESDIN11 AES256_DIN_DIN11 /*!< AESDIN1 Bit 1 */ -#define AESDIN12 AES256_DIN_DIN12 /*!< AESDIN1 Bit 2 */ -#define AESDIN13 AES256_DIN_DIN13 /*!< AESDIN1 Bit 3 */ -#define AESDIN14 AES256_DIN_DIN14 /*!< AESDIN1 Bit 4 */ -#define AESDIN15 AES256_DIN_DIN15 /*!< AESDIN1 Bit 5 */ -#define AESDIN16 AES256_DIN_DIN16 /*!< AESDIN1 Bit 6 */ -#define AESDIN17 AES256_DIN_DIN17 /*!< AESDIN1 Bit 7 */ -/* AESADOUT[AESDOUT0] Bits */ -#define AESDOUT0_OFS AES256_DOUT_DOUT0_OFS /*!< AESDOUT0 Offset */ -#define AESDOUT0_M AES256_DOUT_DOUT0_MASK /*!< AES data out byte n when AESADOUT is read as half-word */ -#define AESDOUT00 AES256_DOUT_DOUT00 /*!< AESDOUT0 Bit 0 */ -#define AESDOUT01 AES256_DOUT_DOUT01 /*!< AESDOUT0 Bit 1 */ -#define AESDOUT02 AES256_DOUT_DOUT02 /*!< AESDOUT0 Bit 2 */ -#define AESDOUT03 AES256_DOUT_DOUT03 /*!< AESDOUT0 Bit 3 */ -#define AESDOUT04 AES256_DOUT_DOUT04 /*!< AESDOUT0 Bit 4 */ -#define AESDOUT05 AES256_DOUT_DOUT05 /*!< AESDOUT0 Bit 5 */ -#define AESDOUT06 AES256_DOUT_DOUT06 /*!< AESDOUT0 Bit 6 */ -#define AESDOUT07 AES256_DOUT_DOUT07 /*!< AESDOUT0 Bit 7 */ -/* AESADOUT[AESDOUT1] Bits */ -#define AESDOUT1_OFS AES256_DOUT_DOUT1_OFS /*!< AESDOUT1 Offset */ -#define AESDOUT1_M AES256_DOUT_DOUT1_MASK /*!< AES data out byte n+1 when AESADOUT is read as half-word */ -#define AESDOUT10 AES256_DOUT_DOUT10 /*!< AESDOUT1 Bit 0 */ -#define AESDOUT11 AES256_DOUT_DOUT11 /*!< AESDOUT1 Bit 1 */ -#define AESDOUT12 AES256_DOUT_DOUT12 /*!< AESDOUT1 Bit 2 */ -#define AESDOUT13 AES256_DOUT_DOUT13 /*!< AESDOUT1 Bit 3 */ -#define AESDOUT14 AES256_DOUT_DOUT14 /*!< AESDOUT1 Bit 4 */ -#define AESDOUT15 AES256_DOUT_DOUT15 /*!< AESDOUT1 Bit 5 */ -#define AESDOUT16 AES256_DOUT_DOUT16 /*!< AESDOUT1 Bit 6 */ -#define AESDOUT17 AES256_DOUT_DOUT17 /*!< AESDOUT1 Bit 7 */ -/* AESAXDIN[AESXDIN0] Bits */ -#define AESXDIN0_OFS AES256_XDIN_XDIN0_OFS /*!< AESXDIN0 Offset */ -#define AESXDIN0_M AES256_XDIN_XDIN0_MASK /*!< AES data in byte n when AESAXDIN is written as half-word */ -#define AESXDIN00 AES256_XDIN_XDIN00 /*!< AESXDIN0 Bit 0 */ -#define AESXDIN01 AES256_XDIN_XDIN01 /*!< AESXDIN0 Bit 1 */ -#define AESXDIN02 AES256_XDIN_XDIN02 /*!< AESXDIN0 Bit 2 */ -#define AESXDIN03 AES256_XDIN_XDIN03 /*!< AESXDIN0 Bit 3 */ -#define AESXDIN04 AES256_XDIN_XDIN04 /*!< AESXDIN0 Bit 4 */ -#define AESXDIN05 AES256_XDIN_XDIN05 /*!< AESXDIN0 Bit 5 */ -#define AESXDIN06 AES256_XDIN_XDIN06 /*!< AESXDIN0 Bit 6 */ -#define AESXDIN07 AES256_XDIN_XDIN07 /*!< AESXDIN0 Bit 7 */ -/* AESAXDIN[AESXDIN1] Bits */ -#define AESXDIN1_OFS AES256_XDIN_XDIN1_OFS /*!< AESXDIN1 Offset */ -#define AESXDIN1_M AES256_XDIN_XDIN1_MASK /*!< AES data in byte n+1 when AESAXDIN is written as half-word */ -#define AESXDIN10 AES256_XDIN_XDIN10 /*!< AESXDIN1 Bit 0 */ -#define AESXDIN11 AES256_XDIN_XDIN11 /*!< AESXDIN1 Bit 1 */ -#define AESXDIN12 AES256_XDIN_XDIN12 /*!< AESXDIN1 Bit 2 */ -#define AESXDIN13 AES256_XDIN_XDIN13 /*!< AESXDIN1 Bit 3 */ -#define AESXDIN14 AES256_XDIN_XDIN14 /*!< AESXDIN1 Bit 4 */ -#define AESXDIN15 AES256_XDIN_XDIN15 /*!< AESXDIN1 Bit 5 */ -#define AESXDIN16 AES256_XDIN_XDIN16 /*!< AESXDIN1 Bit 6 */ -#define AESXDIN17 AES256_XDIN_XDIN17 /*!< AESXDIN1 Bit 7 */ -/* AESAXIN[AESXIN0] Bits */ -#define AESXIN0_OFS AES256_XIN_XIN0_OFS /*!< AESXIN0 Offset */ -#define AESXIN0_M AES256_XIN_XIN0_MASK /*!< AES data in byte n when AESAXIN is written as half-word */ -#define AESXIN00 AES256_XIN_XIN00 /*!< AESXIN0 Bit 0 */ -#define AESXIN01 AES256_XIN_XIN01 /*!< AESXIN0 Bit 1 */ -#define AESXIN02 AES256_XIN_XIN02 /*!< AESXIN0 Bit 2 */ -#define AESXIN03 AES256_XIN_XIN03 /*!< AESXIN0 Bit 3 */ -#define AESXIN04 AES256_XIN_XIN04 /*!< AESXIN0 Bit 4 */ -#define AESXIN05 AES256_XIN_XIN05 /*!< AESXIN0 Bit 5 */ -#define AESXIN06 AES256_XIN_XIN06 /*!< AESXIN0 Bit 6 */ -#define AESXIN07 AES256_XIN_XIN07 /*!< AESXIN0 Bit 7 */ -/* AESAXIN[AESXIN1] Bits */ -#define AESXIN1_OFS AES256_XIN_XIN1_OFS /*!< AESXIN1 Offset */ -#define AESXIN1_M AES256_XIN_XIN1_MASK /*!< AES data in byte n+1 when AESAXIN is written as half-word */ -#define AESXIN10 AES256_XIN_XIN10 /*!< AESXIN1 Bit 0 */ -#define AESXIN11 AES256_XIN_XIN11 /*!< AESXIN1 Bit 1 */ -#define AESXIN12 AES256_XIN_XIN12 /*!< AESXIN1 Bit 2 */ -#define AESXIN13 AES256_XIN_XIN13 /*!< AESXIN1 Bit 3 */ -#define AESXIN14 AES256_XIN_XIN14 /*!< AESXIN1 Bit 4 */ -#define AESXIN15 AES256_XIN_XIN15 /*!< AESXIN1 Bit 5 */ -#define AESXIN16 AES256_XIN_XIN16 /*!< AESXIN1 Bit 6 */ -#define AESXIN17 AES256_XIN_XIN17 /*!< AESXIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits (legacy section) -******************************************************************************/ -/* CAPTIO0CTL[CAPTIOPISEL] Bits */ -#define CAPTIOPISEL_OFS CAPTIO_CTL_PISEL_OFS /*!< CAPTIOPISEL Offset */ -#define CAPTIOPISEL_M CAPTIO_CTL_PISEL_MASK /*!< Capacitive Touch IO pin select */ -#define CAPTIOPISEL0 CAPTIO_CTL_PISEL0 /*!< CAPTIOPISEL Bit 0 */ -#define CAPTIOPISEL1 CAPTIO_CTL_PISEL1 /*!< CAPTIOPISEL Bit 1 */ -#define CAPTIOPISEL2 CAPTIO_CTL_PISEL2 /*!< CAPTIOPISEL Bit 2 */ -#define CAPTIOPISEL_0 CAPTIO_CTL_PISEL_0 /*!< Px.0 */ -#define CAPTIOPISEL_1 CAPTIO_CTL_PISEL_1 /*!< Px.1 */ -#define CAPTIOPISEL_2 CAPTIO_CTL_PISEL_2 /*!< Px.2 */ -#define CAPTIOPISEL_3 CAPTIO_CTL_PISEL_3 /*!< Px.3 */ -#define CAPTIOPISEL_4 CAPTIO_CTL_PISEL_4 /*!< Px.4 */ -#define CAPTIOPISEL_5 CAPTIO_CTL_PISEL_5 /*!< Px.5 */ -#define CAPTIOPISEL_6 CAPTIO_CTL_PISEL_6 /*!< Px.6 */ -#define CAPTIOPISEL_7 CAPTIO_CTL_PISEL_7 /*!< Px.7 */ -/* CAPTIO0CTL[CAPTIOPOSEL] Bits */ -#define CAPTIOPOSEL_OFS CAPTIO_CTL_POSEL_OFS /*!< CAPTIOPOSEL Offset */ -#define CAPTIOPOSEL_M CAPTIO_CTL_POSEL_MASK /*!< Capacitive Touch IO port select */ -#define CAPTIOPOSEL0 CAPTIO_CTL_POSEL0 /*!< CAPTIOPOSEL Bit 0 */ -#define CAPTIOPOSEL1 CAPTIO_CTL_POSEL1 /*!< CAPTIOPOSEL Bit 1 */ -#define CAPTIOPOSEL2 CAPTIO_CTL_POSEL2 /*!< CAPTIOPOSEL Bit 2 */ -#define CAPTIOPOSEL3 CAPTIO_CTL_POSEL3 /*!< CAPTIOPOSEL Bit 3 */ -#define CAPTIOPOSEL_0 CAPTIO_CTL_POSEL_0 /*!< Px = PJ */ -#define CAPTIOPOSEL_1 CAPTIO_CTL_POSEL_1 /*!< Px = P1 */ -#define CAPTIOPOSEL_2 CAPTIO_CTL_POSEL_2 /*!< Px = P2 */ -#define CAPTIOPOSEL_3 CAPTIO_CTL_POSEL_3 /*!< Px = P3 */ -#define CAPTIOPOSEL_4 CAPTIO_CTL_POSEL_4 /*!< Px = P4 */ -#define CAPTIOPOSEL_5 CAPTIO_CTL_POSEL_5 /*!< Px = P5 */ -#define CAPTIOPOSEL_6 CAPTIO_CTL_POSEL_6 /*!< Px = P6 */ -#define CAPTIOPOSEL_7 CAPTIO_CTL_POSEL_7 /*!< Px = P7 */ -#define CAPTIOPOSEL_8 CAPTIO_CTL_POSEL_8 /*!< Px = P8 */ -#define CAPTIOPOSEL_9 CAPTIO_CTL_POSEL_9 /*!< Px = P9 */ -#define CAPTIOPOSEL_10 CAPTIO_CTL_POSEL_10 /*!< Px = P10 */ -#define CAPTIOPOSEL_11 CAPTIO_CTL_POSEL_11 /*!< Px = P11 */ -#define CAPTIOPOSEL_12 CAPTIO_CTL_POSEL_12 /*!< Px = P12 */ -#define CAPTIOPOSEL_13 CAPTIO_CTL_POSEL_13 /*!< Px = P13 */ -#define CAPTIOPOSEL_14 CAPTIO_CTL_POSEL_14 /*!< Px = P14 */ -#define CAPTIOPOSEL_15 CAPTIO_CTL_POSEL_15 /*!< Px = P15 */ -#define CAPTIOPOSEL__PJ CAPTIO_CTL_POSEL__PJ /*!< Px = PJ */ -#define CAPTIOPOSEL__P1 CAPTIO_CTL_POSEL__P1 /*!< Px = P1 */ -#define CAPTIOPOSEL__P2 CAPTIO_CTL_POSEL__P2 /*!< Px = P2 */ -#define CAPTIOPOSEL__P3 CAPTIO_CTL_POSEL__P3 /*!< Px = P3 */ -#define CAPTIOPOSEL__P4 CAPTIO_CTL_POSEL__P4 /*!< Px = P4 */ -#define CAPTIOPOSEL__P5 CAPTIO_CTL_POSEL__P5 /*!< Px = P5 */ -#define CAPTIOPOSEL__P6 CAPTIO_CTL_POSEL__P6 /*!< Px = P6 */ -#define CAPTIOPOSEL__P7 CAPTIO_CTL_POSEL__P7 /*!< Px = P7 */ -#define CAPTIOPOSEL__P8 CAPTIO_CTL_POSEL__P8 /*!< Px = P8 */ -#define CAPTIOPOSEL__P9 CAPTIO_CTL_POSEL__P9 /*!< Px = P9 */ -#define CAPTIOPOSEL__P10 CAPTIO_CTL_POSEL__P10 /*!< Px = P10 */ -#define CAPTIOPOSEL__P11 CAPTIO_CTL_POSEL__P11 /*!< Px = P11 */ -#define CAPTIOPOSEL__P12 CAPTIO_CTL_POSEL__P12 /*!< Px = P12 */ -#define CAPTIOPOSEL__P13 CAPTIO_CTL_POSEL__P13 /*!< Px = P13 */ -#define CAPTIOPOSEL__P14 CAPTIO_CTL_POSEL__P14 /*!< Px = P14 */ -#define CAPTIOPOSEL__P15 CAPTIO_CTL_POSEL__P15 /*!< Px = P15 */ -/* CAPTIO0CTL[CAPTIOEN] Bits */ -#define CAPTIOEN_OFS CAPTIO_CTL_EN_OFS /*!< CAPTIOEN Offset */ -#define CAPTIOEN CAPTIO_CTL_EN /*!< Capacitive Touch IO enable */ -/* CAPTIO0CTL[CAPTIOSTATE] Bits */ -#define CAPTIOSTATE_OFS CAPTIO_CTL_STATE_OFS /*!< CAPTIOSTATE Offset */ -#define CAPTIOSTATE CAPTIO_CTL_STATE /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits (legacy section) -******************************************************************************/ -/* CE0CTL0[CEIPSEL] Bits */ -#define CEIPSEL_OFS COMP_E_CTL0_IPSEL_OFS /*!< CEIPSEL Offset */ -#define CEIPSEL_M COMP_E_CTL0_IPSEL_MASK /*!< Channel input selected for the V+ terminal */ -#define CEIPSEL0 COMP_E_CTL0_IPSEL0 /*!< CEIPSEL Bit 0 */ -#define CEIPSEL1 COMP_E_CTL0_IPSEL1 /*!< CEIPSEL Bit 1 */ -#define CEIPSEL2 COMP_E_CTL0_IPSEL2 /*!< CEIPSEL Bit 2 */ -#define CEIPSEL3 COMP_E_CTL0_IPSEL3 /*!< CEIPSEL Bit 3 */ -#define CEIPSEL_0 COMP_E_CTL0_IPSEL_0 /*!< Channel 0 selected */ -#define CEIPSEL_1 COMP_E_CTL0_IPSEL_1 /*!< Channel 1 selected */ -#define CEIPSEL_2 COMP_E_CTL0_IPSEL_2 /*!< Channel 2 selected */ -#define CEIPSEL_3 COMP_E_CTL0_IPSEL_3 /*!< Channel 3 selected */ -#define CEIPSEL_4 COMP_E_CTL0_IPSEL_4 /*!< Channel 4 selected */ -#define CEIPSEL_5 COMP_E_CTL0_IPSEL_5 /*!< Channel 5 selected */ -#define CEIPSEL_6 COMP_E_CTL0_IPSEL_6 /*!< Channel 6 selected */ -#define CEIPSEL_7 COMP_E_CTL0_IPSEL_7 /*!< Channel 7 selected */ -#define CEIPSEL_8 COMP_E_CTL0_IPSEL_8 /*!< Channel 8 selected */ -#define CEIPSEL_9 COMP_E_CTL0_IPSEL_9 /*!< Channel 9 selected */ -#define CEIPSEL_10 COMP_E_CTL0_IPSEL_10 /*!< Channel 10 selected */ -#define CEIPSEL_11 COMP_E_CTL0_IPSEL_11 /*!< Channel 11 selected */ -#define CEIPSEL_12 COMP_E_CTL0_IPSEL_12 /*!< Channel 12 selected */ -#define CEIPSEL_13 COMP_E_CTL0_IPSEL_13 /*!< Channel 13 selected */ -#define CEIPSEL_14 COMP_E_CTL0_IPSEL_14 /*!< Channel 14 selected */ -#define CEIPSEL_15 COMP_E_CTL0_IPSEL_15 /*!< Channel 15 selected */ -/* CE0CTL0[CEIPEN] Bits */ -#define CEIPEN_OFS COMP_E_CTL0_IPEN_OFS /*!< CEIPEN Offset */ -#define CEIPEN COMP_E_CTL0_IPEN /*!< Channel input enable for the V+ terminal */ -/* CE0CTL0[CEIMSEL] Bits */ -#define CEIMSEL_OFS COMP_E_CTL0_IMSEL_OFS /*!< CEIMSEL Offset */ -#define CEIMSEL_M COMP_E_CTL0_IMSEL_MASK /*!< Channel input selected for the - terminal */ -#define CEIMSEL0 COMP_E_CTL0_IMSEL0 /*!< CEIMSEL Bit 0 */ -#define CEIMSEL1 COMP_E_CTL0_IMSEL1 /*!< CEIMSEL Bit 1 */ -#define CEIMSEL2 COMP_E_CTL0_IMSEL2 /*!< CEIMSEL Bit 2 */ -#define CEIMSEL3 COMP_E_CTL0_IMSEL3 /*!< CEIMSEL Bit 3 */ -#define CEIMSEL_0 COMP_E_CTL0_IMSEL_0 /*!< Channel 0 selected */ -#define CEIMSEL_1 COMP_E_CTL0_IMSEL_1 /*!< Channel 1 selected */ -#define CEIMSEL_2 COMP_E_CTL0_IMSEL_2 /*!< Channel 2 selected */ -#define CEIMSEL_3 COMP_E_CTL0_IMSEL_3 /*!< Channel 3 selected */ -#define CEIMSEL_4 COMP_E_CTL0_IMSEL_4 /*!< Channel 4 selected */ -#define CEIMSEL_5 COMP_E_CTL0_IMSEL_5 /*!< Channel 5 selected */ -#define CEIMSEL_6 COMP_E_CTL0_IMSEL_6 /*!< Channel 6 selected */ -#define CEIMSEL_7 COMP_E_CTL0_IMSEL_7 /*!< Channel 7 selected */ -#define CEIMSEL_8 COMP_E_CTL0_IMSEL_8 /*!< Channel 8 selected */ -#define CEIMSEL_9 COMP_E_CTL0_IMSEL_9 /*!< Channel 9 selected */ -#define CEIMSEL_10 COMP_E_CTL0_IMSEL_10 /*!< Channel 10 selected */ -#define CEIMSEL_11 COMP_E_CTL0_IMSEL_11 /*!< Channel 11 selected */ -#define CEIMSEL_12 COMP_E_CTL0_IMSEL_12 /*!< Channel 12 selected */ -#define CEIMSEL_13 COMP_E_CTL0_IMSEL_13 /*!< Channel 13 selected */ -#define CEIMSEL_14 COMP_E_CTL0_IMSEL_14 /*!< Channel 14 selected */ -#define CEIMSEL_15 COMP_E_CTL0_IMSEL_15 /*!< Channel 15 selected */ -/* CE0CTL0[CEIMEN] Bits */ -#define CEIMEN_OFS COMP_E_CTL0_IMEN_OFS /*!< CEIMEN Offset */ -#define CEIMEN COMP_E_CTL0_IMEN /*!< Channel input enable for the - terminal */ -/* CE0CTL1[CEOUT] Bits */ -#define CEOUT_OFS COMP_E_CTL1_OUT_OFS /*!< CEOUT Offset */ -#define CEOUT COMP_E_CTL1_OUT /*!< Comparator output value */ -/* CE0CTL1[CEOUTPOL] Bits */ -#define CEOUTPOL_OFS COMP_E_CTL1_OUTPOL_OFS /*!< CEOUTPOL Offset */ -#define CEOUTPOL COMP_E_CTL1_OUTPOL /*!< Comparator output polarity */ -/* CE0CTL1[CEF] Bits */ -#define CEF_OFS COMP_E_CTL1_F_OFS /*!< CEF Offset */ -#define CEF COMP_E_CTL1_F /*!< Comparator output filter */ -/* CE0CTL1[CEIES] Bits */ -#define CEIES_OFS COMP_E_CTL1_IES_OFS /*!< CEIES Offset */ -#define CEIES COMP_E_CTL1_IES /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* CE0CTL1[CESHORT] Bits */ -#define CESHORT_OFS COMP_E_CTL1_SHORT_OFS /*!< CESHORT Offset */ -#define CESHORT COMP_E_CTL1_SHORT /*!< Input short */ -/* CE0CTL1[CEEX] Bits */ -#define CEEX_OFS COMP_E_CTL1_EX_OFS /*!< CEEX Offset */ -#define CEEX COMP_E_CTL1_EX /*!< Exchange */ -/* CE0CTL1[CEFDLY] Bits */ -#define CEFDLY_OFS COMP_E_CTL1_FDLY_OFS /*!< CEFDLY Offset */ -#define CEFDLY_M COMP_E_CTL1_FDLY_MASK /*!< Filter delay */ -#define CEFDLY0 COMP_E_CTL1_FDLY0 /*!< CEFDLY Bit 0 */ -#define CEFDLY1 COMP_E_CTL1_FDLY1 /*!< CEFDLY Bit 1 */ -#define CEFDLY_0 COMP_E_CTL1_FDLY_0 /*!< Typical filter delay of TBD (450) ns */ -#define CEFDLY_1 COMP_E_CTL1_FDLY_1 /*!< Typical filter delay of TBD (900) ns */ -#define CEFDLY_2 COMP_E_CTL1_FDLY_2 /*!< Typical filter delay of TBD (1800) ns */ -#define CEFDLY_3 COMP_E_CTL1_FDLY_3 /*!< Typical filter delay of TBD (3600) ns */ -/* CE0CTL1[CEPWRMD] Bits */ -#define CEPWRMD_OFS COMP_E_CTL1_PWRMD_OFS /*!< CEPWRMD Offset */ -#define CEPWRMD_M COMP_E_CTL1_PWRMD_MASK /*!< Power Mode */ -#define CEPWRMD0 COMP_E_CTL1_PWRMD0 /*!< CEPWRMD Bit 0 */ -#define CEPWRMD1 COMP_E_CTL1_PWRMD1 /*!< CEPWRMD Bit 1 */ -#define CEPWRMD_0 COMP_E_CTL1_PWRMD_0 /*!< High-speed mode */ -#define CEPWRMD_1 COMP_E_CTL1_PWRMD_1 /*!< Normal mode */ -#define CEPWRMD_2 COMP_E_CTL1_PWRMD_2 /*!< Ultra-low power mode */ -/* CE0CTL1[CEON] Bits */ -#define CEON_OFS COMP_E_CTL1_ON_OFS /*!< CEON Offset */ -#define CEON COMP_E_CTL1_ON /*!< Comparator On */ -/* CE0CTL1[CEMRVL] Bits */ -#define CEMRVL_OFS COMP_E_CTL1_MRVL_OFS /*!< CEMRVL Offset */ -#define CEMRVL COMP_E_CTL1_MRVL /*!< This bit is valid of CEMRVS is set to 1 */ -/* CE0CTL1[CEMRVS] Bits */ -#define CEMRVS_OFS COMP_E_CTL1_MRVS_OFS /*!< CEMRVS Offset */ -#define CEMRVS COMP_E_CTL1_MRVS -/* CE0CTL2[CEREF0] Bits */ -#define CEREF0_OFS COMP_E_CTL2_REF0_OFS /*!< CEREF0 Offset */ -#define CEREF0_M COMP_E_CTL2_REF0_MASK /*!< Reference resistor tap 0 */ -#define CEREF00 COMP_E_CTL2_REF00 /*!< CEREF0 Bit 0 */ -#define CEREF01 COMP_E_CTL2_REF01 /*!< CEREF0 Bit 1 */ -#define CEREF02 COMP_E_CTL2_REF02 /*!< CEREF0 Bit 2 */ -#define CEREF03 COMP_E_CTL2_REF03 /*!< CEREF0 Bit 3 */ -#define CEREF04 COMP_E_CTL2_REF04 /*!< CEREF0 Bit 4 */ -#define CEREF0_0 COMP_E_CTL2_REF0_0 /*!< Reference resistor tap for setting 0. */ -#define CEREF0_1 COMP_E_CTL2_REF0_1 /*!< Reference resistor tap for setting 1. */ -#define CEREF0_2 COMP_E_CTL2_REF0_2 /*!< Reference resistor tap for setting 2. */ -#define CEREF0_3 COMP_E_CTL2_REF0_3 /*!< Reference resistor tap for setting 3. */ -#define CEREF0_4 COMP_E_CTL2_REF0_4 /*!< Reference resistor tap for setting 4. */ -#define CEREF0_5 COMP_E_CTL2_REF0_5 /*!< Reference resistor tap for setting 5. */ -#define CEREF0_6 COMP_E_CTL2_REF0_6 /*!< Reference resistor tap for setting 6. */ -#define CEREF0_7 COMP_E_CTL2_REF0_7 /*!< Reference resistor tap for setting 7. */ -#define CEREF0_8 COMP_E_CTL2_REF0_8 /*!< Reference resistor tap for setting 8. */ -#define CEREF0_9 COMP_E_CTL2_REF0_9 /*!< Reference resistor tap for setting 9. */ -#define CEREF0_10 COMP_E_CTL2_REF0_10 /*!< Reference resistor tap for setting 10. */ -#define CEREF0_11 COMP_E_CTL2_REF0_11 /*!< Reference resistor tap for setting 11. */ -#define CEREF0_12 COMP_E_CTL2_REF0_12 /*!< Reference resistor tap for setting 12. */ -#define CEREF0_13 COMP_E_CTL2_REF0_13 /*!< Reference resistor tap for setting 13. */ -#define CEREF0_14 COMP_E_CTL2_REF0_14 /*!< Reference resistor tap for setting 14. */ -#define CEREF0_15 COMP_E_CTL2_REF0_15 /*!< Reference resistor tap for setting 15. */ -#define CEREF0_16 COMP_E_CTL2_REF0_16 /*!< Reference resistor tap for setting 16. */ -#define CEREF0_17 COMP_E_CTL2_REF0_17 /*!< Reference resistor tap for setting 17. */ -#define CEREF0_18 COMP_E_CTL2_REF0_18 /*!< Reference resistor tap for setting 18. */ -#define CEREF0_19 COMP_E_CTL2_REF0_19 /*!< Reference resistor tap for setting 19. */ -#define CEREF0_20 COMP_E_CTL2_REF0_20 /*!< Reference resistor tap for setting 20. */ -#define CEREF0_21 COMP_E_CTL2_REF0_21 /*!< Reference resistor tap for setting 21. */ -#define CEREF0_22 COMP_E_CTL2_REF0_22 /*!< Reference resistor tap for setting 22. */ -#define CEREF0_23 COMP_E_CTL2_REF0_23 /*!< Reference resistor tap for setting 23. */ -#define CEREF0_24 COMP_E_CTL2_REF0_24 /*!< Reference resistor tap for setting 24. */ -#define CEREF0_25 COMP_E_CTL2_REF0_25 /*!< Reference resistor tap for setting 25. */ -#define CEREF0_26 COMP_E_CTL2_REF0_26 /*!< Reference resistor tap for setting 26. */ -#define CEREF0_27 COMP_E_CTL2_REF0_27 /*!< Reference resistor tap for setting 27. */ -#define CEREF0_28 COMP_E_CTL2_REF0_28 /*!< Reference resistor tap for setting 28. */ -#define CEREF0_29 COMP_E_CTL2_REF0_29 /*!< Reference resistor tap for setting 29. */ -#define CEREF0_30 COMP_E_CTL2_REF0_30 /*!< Reference resistor tap for setting 30. */ -#define CEREF0_31 COMP_E_CTL2_REF0_31 /*!< Reference resistor tap for setting 31. */ -/* CE0CTL2[CERSEL] Bits */ -#define CERSEL_OFS COMP_E_CTL2_RSEL_OFS /*!< CERSEL Offset */ -#define CERSEL COMP_E_CTL2_RSEL /*!< Reference select */ -/* CE0CTL2[CERS] Bits */ -#define CERS_OFS COMP_E_CTL2_RS_OFS /*!< CERS Offset */ -#define CERS_M COMP_E_CTL2_RS_MASK /*!< Reference source */ -#define CERS0 COMP_E_CTL2_RS0 /*!< CERS Bit 0 */ -#define CERS1 COMP_E_CTL2_RS1 /*!< CERS Bit 1 */ -#define CERS_0 COMP_E_CTL2_RS_0 /*!< No current is drawn by the reference circuitry */ -#define CERS_1 COMP_E_CTL2_RS_1 /*!< VCC applied to the resistor ladder */ -#define CERS_2 COMP_E_CTL2_RS_2 /*!< Shared reference voltage applied to the resistor ladder */ -#define CERS_3 COMP_E_CTL2_RS_3 /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* CE0CTL2[CEREF1] Bits */ -#define CEREF1_OFS COMP_E_CTL2_REF1_OFS /*!< CEREF1 Offset */ -#define CEREF1_M COMP_E_CTL2_REF1_MASK /*!< Reference resistor tap 1 */ -#define CEREF10 COMP_E_CTL2_REF10 /*!< CEREF1 Bit 0 */ -#define CEREF11 COMP_E_CTL2_REF11 /*!< CEREF1 Bit 1 */ -#define CEREF12 COMP_E_CTL2_REF12 /*!< CEREF1 Bit 2 */ -#define CEREF13 COMP_E_CTL2_REF13 /*!< CEREF1 Bit 3 */ -#define CEREF14 COMP_E_CTL2_REF14 /*!< CEREF1 Bit 4 */ -#define CEREF1_0 COMP_E_CTL2_REF1_0 /*!< Reference resistor tap for setting 0. */ -#define CEREF1_1 COMP_E_CTL2_REF1_1 /*!< Reference resistor tap for setting 1. */ -#define CEREF1_2 COMP_E_CTL2_REF1_2 /*!< Reference resistor tap for setting 2. */ -#define CEREF1_3 COMP_E_CTL2_REF1_3 /*!< Reference resistor tap for setting 3. */ -#define CEREF1_4 COMP_E_CTL2_REF1_4 /*!< Reference resistor tap for setting 4. */ -#define CEREF1_5 COMP_E_CTL2_REF1_5 /*!< Reference resistor tap for setting 5. */ -#define CEREF1_6 COMP_E_CTL2_REF1_6 /*!< Reference resistor tap for setting 6. */ -#define CEREF1_7 COMP_E_CTL2_REF1_7 /*!< Reference resistor tap for setting 7. */ -#define CEREF1_8 COMP_E_CTL2_REF1_8 /*!< Reference resistor tap for setting 8. */ -#define CEREF1_9 COMP_E_CTL2_REF1_9 /*!< Reference resistor tap for setting 9. */ -#define CEREF1_10 COMP_E_CTL2_REF1_10 /*!< Reference resistor tap for setting 10. */ -#define CEREF1_11 COMP_E_CTL2_REF1_11 /*!< Reference resistor tap for setting 11. */ -#define CEREF1_12 COMP_E_CTL2_REF1_12 /*!< Reference resistor tap for setting 12. */ -#define CEREF1_13 COMP_E_CTL2_REF1_13 /*!< Reference resistor tap for setting 13. */ -#define CEREF1_14 COMP_E_CTL2_REF1_14 /*!< Reference resistor tap for setting 14. */ -#define CEREF1_15 COMP_E_CTL2_REF1_15 /*!< Reference resistor tap for setting 15. */ -#define CEREF1_16 COMP_E_CTL2_REF1_16 /*!< Reference resistor tap for setting 16. */ -#define CEREF1_17 COMP_E_CTL2_REF1_17 /*!< Reference resistor tap for setting 17. */ -#define CEREF1_18 COMP_E_CTL2_REF1_18 /*!< Reference resistor tap for setting 18. */ -#define CEREF1_19 COMP_E_CTL2_REF1_19 /*!< Reference resistor tap for setting 19. */ -#define CEREF1_20 COMP_E_CTL2_REF1_20 /*!< Reference resistor tap for setting 20. */ -#define CEREF1_21 COMP_E_CTL2_REF1_21 /*!< Reference resistor tap for setting 21. */ -#define CEREF1_22 COMP_E_CTL2_REF1_22 /*!< Reference resistor tap for setting 22. */ -#define CEREF1_23 COMP_E_CTL2_REF1_23 /*!< Reference resistor tap for setting 23. */ -#define CEREF1_24 COMP_E_CTL2_REF1_24 /*!< Reference resistor tap for setting 24. */ -#define CEREF1_25 COMP_E_CTL2_REF1_25 /*!< Reference resistor tap for setting 25. */ -#define CEREF1_26 COMP_E_CTL2_REF1_26 /*!< Reference resistor tap for setting 26. */ -#define CEREF1_27 COMP_E_CTL2_REF1_27 /*!< Reference resistor tap for setting 27. */ -#define CEREF1_28 COMP_E_CTL2_REF1_28 /*!< Reference resistor tap for setting 28. */ -#define CEREF1_29 COMP_E_CTL2_REF1_29 /*!< Reference resistor tap for setting 29. */ -#define CEREF1_30 COMP_E_CTL2_REF1_30 /*!< Reference resistor tap for setting 30. */ -#define CEREF1_31 COMP_E_CTL2_REF1_31 /*!< Reference resistor tap for setting 31. */ -/* CE0CTL2[CEREFL] Bits */ -#define CEREFL_OFS COMP_E_CTL2_REFL_OFS /*!< CEREFL Offset */ -#define CEREFL_M COMP_E_CTL2_REFL_MASK /*!< Reference voltage level */ -#define CEREFL0 COMP_E_CTL2_REFL0 /*!< CEREFL Bit 0 */ -#define CEREFL1 COMP_E_CTL2_REFL1 /*!< CEREFL Bit 1 */ -#define CEREFL_0 COMP_E_CTL2_CEREFL_0 /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define CEREFL_1 COMP_E_CTL2_CEREFL_1 /*!< 1.2 V is selected as shared reference voltage input */ -#define CEREFL_2 COMP_E_CTL2_CEREFL_2 /*!< 2.0 V is selected as shared reference voltage input */ -#define CEREFL_3 COMP_E_CTL2_CEREFL_3 /*!< 2.5 V is selected as shared reference voltage input */ -#define CEREFL__OFF COMP_E_CTL2_REFL__OFF /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define CEREFL__1P2V COMP_E_CTL2_REFL__1P2V /*!< 1.2 V is selected as shared reference voltage input */ -#define CEREFL__2P0V COMP_E_CTL2_REFL__2P0V /*!< 2.0 V is selected as shared reference voltage input */ -#define CEREFL__2P5V COMP_E_CTL2_REFL__2P5V /*!< 2.5 V is selected as shared reference voltage input */ -/* CE0CTL2[CEREFACC] Bits */ -#define CEREFACC_OFS COMP_E_CTL2_REFACC_OFS /*!< CEREFACC Offset */ -#define CEREFACC COMP_E_CTL2_REFACC /*!< Reference accuracy */ -/* CE0CTL3[CEPD0] Bits */ -#define CEPD0_OFS COMP_E_CTL3_PD0_OFS /*!< CEPD0 Offset */ -#define CEPD0 COMP_E_CTL3_PD0 /*!< Port disable */ -/* CE0CTL3[CEPD1] Bits */ -#define CEPD1_OFS COMP_E_CTL3_PD1_OFS /*!< CEPD1 Offset */ -#define CEPD1 COMP_E_CTL3_PD1 /*!< Port disable */ -/* CE0CTL3[CEPD2] Bits */ -#define CEPD2_OFS COMP_E_CTL3_PD2_OFS /*!< CEPD2 Offset */ -#define CEPD2 COMP_E_CTL3_PD2 /*!< Port disable */ -/* CE0CTL3[CEPD3] Bits */ -#define CEPD3_OFS COMP_E_CTL3_PD3_OFS /*!< CEPD3 Offset */ -#define CEPD3 COMP_E_CTL3_PD3 /*!< Port disable */ -/* CE0CTL3[CEPD4] Bits */ -#define CEPD4_OFS COMP_E_CTL3_PD4_OFS /*!< CEPD4 Offset */ -#define CEPD4 COMP_E_CTL3_PD4 /*!< Port disable */ -/* CE0CTL3[CEPD5] Bits */ -#define CEPD5_OFS COMP_E_CTL3_PD5_OFS /*!< CEPD5 Offset */ -#define CEPD5 COMP_E_CTL3_PD5 /*!< Port disable */ -/* CE0CTL3[CEPD6] Bits */ -#define CEPD6_OFS COMP_E_CTL3_PD6_OFS /*!< CEPD6 Offset */ -#define CEPD6 COMP_E_CTL3_PD6 /*!< Port disable */ -/* CE0CTL3[CEPD7] Bits */ -#define CEPD7_OFS COMP_E_CTL3_PD7_OFS /*!< CEPD7 Offset */ -#define CEPD7 COMP_E_CTL3_PD7 /*!< Port disable */ -/* CE0CTL3[CEPD8] Bits */ -#define CEPD8_OFS COMP_E_CTL3_PD8_OFS /*!< CEPD8 Offset */ -#define CEPD8 COMP_E_CTL3_PD8 /*!< Port disable */ -/* CE0CTL3[CEPD9] Bits */ -#define CEPD9_OFS COMP_E_CTL3_PD9_OFS /*!< CEPD9 Offset */ -#define CEPD9 COMP_E_CTL3_PD9 /*!< Port disable */ -/* CE0CTL3[CEPD10] Bits */ -#define CEPD10_OFS COMP_E_CTL3_PD10_OFS /*!< CEPD10 Offset */ -#define CEPD10 COMP_E_CTL3_PD10 /*!< Port disable */ -/* CE0CTL3[CEPD11] Bits */ -#define CEPD11_OFS COMP_E_CTL3_PD11_OFS /*!< CEPD11 Offset */ -#define CEPD11 COMP_E_CTL3_PD11 /*!< Port disable */ -/* CE0CTL3[CEPD12] Bits */ -#define CEPD12_OFS COMP_E_CTL3_PD12_OFS /*!< CEPD12 Offset */ -#define CEPD12 COMP_E_CTL3_PD12 /*!< Port disable */ -/* CE0CTL3[CEPD13] Bits */ -#define CEPD13_OFS COMP_E_CTL3_PD13_OFS /*!< CEPD13 Offset */ -#define CEPD13 COMP_E_CTL3_PD13 /*!< Port disable */ -/* CE0CTL3[CEPD14] Bits */ -#define CEPD14_OFS COMP_E_CTL3_PD14_OFS /*!< CEPD14 Offset */ -#define CEPD14 COMP_E_CTL3_PD14 /*!< Port disable */ -/* CE0CTL3[CEPD15] Bits */ -#define CEPD15_OFS COMP_E_CTL3_PD15_OFS /*!< CEPD15 Offset */ -#define CEPD15 COMP_E_CTL3_PD15 /*!< Port disable */ -/* CE0INT[CEIFG] Bits */ -#define CEIFG_OFS COMP_E_INT_IFG_OFS /*!< CEIFG Offset */ -#define CEIFG COMP_E_INT_IFG /*!< Comparator output interrupt flag */ -/* CE0INT[CEIIFG] Bits */ -#define CEIIFG_OFS COMP_E_INT_IIFG_OFS /*!< CEIIFG Offset */ -#define CEIIFG COMP_E_INT_IIFG /*!< Comparator output inverted interrupt flag */ -/* CE0INT[CERDYIFG] Bits */ -#define CERDYIFG_OFS COMP_E_INT_RDYIFG_OFS /*!< CERDYIFG Offset */ -#define CERDYIFG COMP_E_INT_RDYIFG /*!< Comparator ready interrupt flag */ -/* CE0INT[CEIE] Bits */ -#define CEIE_OFS COMP_E_INT_IE_OFS /*!< CEIE Offset */ -#define CEIE COMP_E_INT_IE /*!< Comparator output interrupt enable */ -/* CE0INT[CEIIE] Bits */ -#define CEIIE_OFS COMP_E_INT_IIE_OFS /*!< CEIIE Offset */ -#define CEIIE COMP_E_INT_IIE /*!< Comparator output interrupt enable inverted polarity */ -/* CE0INT[CERDYIE] Bits */ -#define CERDYIE_OFS COMP_E_INT_RDYIE_OFS /*!< CERDYIE Offset */ -#define CERDYIE COMP_E_INT_RDYIE /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* CRC32 Bits (legacy section) -******************************************************************************/ -/* DIO_PAIN[P1IN] Bits */ -#define P1IN_OFS ( 0) /*!< P1IN Offset */ -#define P1IN_M (0x00ff) /*!< Port 1 Input */ -/* DIO_PAIN[P2IN] Bits */ -#define P2IN_OFS ( 8) /*!< P2IN Offset */ -#define P2IN_M (0xff00) /*!< Port 2 Input */ -/* DIO_PAOUT[P2OUT] Bits */ -#define P2OUT_OFS ( 8) /*!< P2OUT Offset */ -#define P2OUT_M (0xff00) /*!< Port 2 Output */ -/* DIO_PAOUT[P1OUT] Bits */ -#define P1OUT_OFS ( 0) /*!< P1OUT Offset */ -#define P1OUT_M (0x00ff) /*!< Port 1 Output */ -/* DIO_PADIR[P1DIR] Bits */ -#define P1DIR_OFS ( 0) /*!< P1DIR Offset */ -#define P1DIR_M (0x00ff) /*!< Port 1 Direction */ -/* DIO_PADIR[P2DIR] Bits */ -#define P2DIR_OFS ( 8) /*!< P2DIR Offset */ -#define P2DIR_M (0xff00) /*!< Port 2 Direction */ -/* DIO_PAREN[P1REN] Bits */ -#define P1REN_OFS ( 0) /*!< P1REN Offset */ -#define P1REN_M (0x00ff) /*!< Port 1 Resistor Enable */ -/* DIO_PAREN[P2REN] Bits */ -#define P2REN_OFS ( 8) /*!< P2REN Offset */ -#define P2REN_M (0xff00) /*!< Port 2 Resistor Enable */ -/* DIO_PADS[P1DS] Bits */ -#define P1DS_OFS ( 0) /*!< P1DS Offset */ -#define P1DS_M (0x00ff) /*!< Port 1 Drive Strength */ -/* DIO_PADS[P2DS] Bits */ -#define P2DS_OFS ( 8) /*!< P2DS Offset */ -#define P2DS_M (0xff00) /*!< Port 2 Drive Strength */ -/* DIO_PASEL0[P1SEL0] Bits */ -#define P1SEL0_OFS ( 0) /*!< P1SEL0 Offset */ -#define P1SEL0_M (0x00ff) /*!< Port 1 Select 0 */ -/* DIO_PASEL0[P2SEL0] Bits */ -#define P2SEL0_OFS ( 8) /*!< P2SEL0 Offset */ -#define P2SEL0_M (0xff00) /*!< Port 2 Select 0 */ -/* DIO_PASEL1[P1SEL1] Bits */ -#define P1SEL1_OFS ( 0) /*!< P1SEL1 Offset */ -#define P1SEL1_M (0x00ff) /*!< Port 1 Select 1 */ -/* DIO_PASEL1[P2SEL1] Bits */ -#define P2SEL1_OFS ( 8) /*!< P2SEL1 Offset */ -#define P2SEL1_M (0xff00) /*!< Port 2 Select 1 */ -/* DIO_P1IV[P1IV] Bits */ -#define P1IV_OFS ( 0) /*!< P1IV Offset */ -#define P1IV_M (0x001f) /*!< Port 1 interrupt vector value */ -#define P1IV0 (0x0001) /*!< Port 1 interrupt vector value */ -#define P1IV1 (0x0002) /*!< Port 1 interrupt vector value */ -#define P1IV2 (0x0004) /*!< Port 1 interrupt vector value */ -#define P1IV3 (0x0008) /*!< Port 1 interrupt vector value */ -#define P1IV4 (0x0010) /*!< Port 1 interrupt vector value */ -#define P1IV_0 (0x0000) /*!< No interrupt pending */ -#define P1IV_2 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */ -#define P1IV_4 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */ -#define P1IV_6 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */ -#define P1IV_8 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */ -#define P1IV_10 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */ -#define P1IV_12 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */ -#define P1IV_14 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */ -#define P1IV_16 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */ -#define P1IV__NONE (0x0000) /*!< No interrupt pending */ -#define P1IV__P1IFG0 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */ -#define P1IV__P1IFG1 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */ -#define P1IV__P1IFG2 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */ -#define P1IV__P1IFG3 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */ -#define P1IV__P1IFG4 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */ -#define P1IV__P1IFG5 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */ -#define P1IV__P1IFG6 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */ -#define P1IV__P1IFG7 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */ -/* DIO_PASELC[P1SELC] Bits */ -#define P1SELC_OFS ( 0) /*!< P1SELC Offset */ -#define P1SELC_M (0x00ff) /*!< Port 1 Complement Select */ -/* DIO_PASELC[P2SELC] Bits */ -#define P2SELC_OFS ( 8) /*!< P2SELC Offset */ -#define P2SELC_M (0xff00) /*!< Port 2 Complement Select */ -/* DIO_PAIES[P1IES] Bits */ -#define P1IES_OFS ( 0) /*!< P1IES Offset */ -#define P1IES_M (0x00ff) /*!< Port 1 Interrupt Edge Select */ -/* DIO_PAIES[P2IES] Bits */ -#define P2IES_OFS ( 8) /*!< P2IES Offset */ -#define P2IES_M (0xff00) /*!< Port 2 Interrupt Edge Select */ -/* DIO_PAIE[P1IE] Bits */ -#define P1IE_OFS ( 0) /*!< P1IE Offset */ -#define P1IE_M (0x00ff) /*!< Port 1 Interrupt Enable */ -/* DIO_PAIE[P2IE] Bits */ -#define P2IE_OFS ( 8) /*!< P2IE Offset */ -#define P2IE_M (0xff00) /*!< Port 2 Interrupt Enable */ -/* DIO_PAIFG[P1IFG] Bits */ -#define P1IFG_OFS ( 0) /*!< P1IFG Offset */ -#define P1IFG_M (0x00ff) /*!< Port 1 Interrupt Flag */ -/* DIO_PAIFG[P2IFG] Bits */ -#define P2IFG_OFS ( 8) /*!< P2IFG Offset */ -#define P2IFG_M (0xff00) /*!< Port 2 Interrupt Flag */ -/* DIO_P2IV[P2IV] Bits */ -#define P2IV_OFS ( 0) /*!< P2IV Offset */ -#define P2IV_M (0x001f) /*!< Port 2 interrupt vector value */ -#define P2IV0 (0x0001) /*!< Port 2 interrupt vector value */ -#define P2IV1 (0x0002) /*!< Port 2 interrupt vector value */ -#define P2IV2 (0x0004) /*!< Port 2 interrupt vector value */ -#define P2IV3 (0x0008) /*!< Port 2 interrupt vector value */ -#define P2IV4 (0x0010) /*!< Port 2 interrupt vector value */ -#define P2IV_0 (0x0000) /*!< No interrupt pending */ -#define P2IV_2 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */ -#define P2IV_4 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */ -#define P2IV_6 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */ -#define P2IV_8 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */ -#define P2IV_10 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */ -#define P2IV_12 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */ -#define P2IV_14 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */ -#define P2IV_16 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */ -#define P2IV__NONE (0x0000) /*!< No interrupt pending */ -#define P2IV__P2IFG0 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */ -#define P2IV__P2IFG1 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */ -#define P2IV__P2IFG2 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */ -#define P2IV__P2IFG3 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */ -#define P2IV__P2IFG4 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */ -#define P2IV__P2IFG5 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */ -#define P2IV__P2IFG6 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */ -#define P2IV__P2IFG7 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */ -/* DIO_PBIN[P3IN] Bits */ -#define P3IN_OFS ( 0) /*!< P3IN Offset */ -#define P3IN_M (0x00ff) /*!< Port 3 Input */ -/* DIO_PBIN[P4IN] Bits */ -#define P4IN_OFS ( 8) /*!< P4IN Offset */ -#define P4IN_M (0xff00) /*!< Port 4 Input */ -/* DIO_PBOUT[P3OUT] Bits */ -#define P3OUT_OFS ( 0) /*!< P3OUT Offset */ -#define P3OUT_M (0x00ff) /*!< Port 3 Output */ -/* DIO_PBOUT[P4OUT] Bits */ -#define P4OUT_OFS ( 8) /*!< P4OUT Offset */ -#define P4OUT_M (0xff00) /*!< Port 4 Output */ -/* DIO_PBDIR[P3DIR] Bits */ -#define P3DIR_OFS ( 0) /*!< P3DIR Offset */ -#define P3DIR_M (0x00ff) /*!< Port 3 Direction */ -/* DIO_PBDIR[P4DIR] Bits */ -#define P4DIR_OFS ( 8) /*!< P4DIR Offset */ -#define P4DIR_M (0xff00) /*!< Port 4 Direction */ -/* DIO_PBREN[P3REN] Bits */ -#define P3REN_OFS ( 0) /*!< P3REN Offset */ -#define P3REN_M (0x00ff) /*!< Port 3 Resistor Enable */ -/* DIO_PBREN[P4REN] Bits */ -#define P4REN_OFS ( 8) /*!< P4REN Offset */ -#define P4REN_M (0xff00) /*!< Port 4 Resistor Enable */ -/* DIO_PBDS[P3DS] Bits */ -#define P3DS_OFS ( 0) /*!< P3DS Offset */ -#define P3DS_M (0x00ff) /*!< Port 3 Drive Strength */ -/* DIO_PBDS[P4DS] Bits */ -#define P4DS_OFS ( 8) /*!< P4DS Offset */ -#define P4DS_M (0xff00) /*!< Port 4 Drive Strength */ -/* DIO_PBSEL0[P4SEL0] Bits */ -#define P4SEL0_OFS ( 8) /*!< P4SEL0 Offset */ -#define P4SEL0_M (0xff00) /*!< Port 4 Select 0 */ -/* DIO_PBSEL0[P3SEL0] Bits */ -#define P3SEL0_OFS ( 0) /*!< P3SEL0 Offset */ -#define P3SEL0_M (0x00ff) /*!< Port 3 Select 0 */ -/* DIO_PBSEL1[P3SEL1] Bits */ -#define P3SEL1_OFS ( 0) /*!< P3SEL1 Offset */ -#define P3SEL1_M (0x00ff) /*!< Port 3 Select 1 */ -/* DIO_PBSEL1[P4SEL1] Bits */ -#define P4SEL1_OFS ( 8) /*!< P4SEL1 Offset */ -#define P4SEL1_M (0xff00) /*!< Port 4 Select 1 */ -/* DIO_P3IV[P3IV] Bits */ -#define P3IV_OFS ( 0) /*!< P3IV Offset */ -#define P3IV_M (0x001f) /*!< Port 3 interrupt vector value */ -#define P3IV0 (0x0001) /*!< Port 3 interrupt vector value */ -#define P3IV1 (0x0002) /*!< Port 3 interrupt vector value */ -#define P3IV2 (0x0004) /*!< Port 3 interrupt vector value */ -#define P3IV3 (0x0008) /*!< Port 3 interrupt vector value */ -#define P3IV4 (0x0010) /*!< Port 3 interrupt vector value */ -#define P3IV_0 (0x0000) /*!< No interrupt pending */ -#define P3IV_2 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */ -#define P3IV_4 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */ -#define P3IV_6 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */ -#define P3IV_8 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */ -#define P3IV_10 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */ -#define P3IV_12 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */ -#define P3IV_14 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */ -#define P3IV_16 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */ -#define P3IV__NONE (0x0000) /*!< No interrupt pending */ -#define P3IV__P3IFG0 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */ -#define P3IV__P3IFG1 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */ -#define P3IV__P3IFG2 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */ -#define P3IV__P3IFG3 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */ -#define P3IV__P3IFG4 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */ -#define P3IV__P3IFG5 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */ -#define P3IV__P3IFG6 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */ -#define P3IV__P3IFG7 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */ -/* DIO_PBSELC[P3SELC] Bits */ -#define P3SELC_OFS ( 0) /*!< P3SELC Offset */ -#define P3SELC_M (0x00ff) /*!< Port 3 Complement Select */ -/* DIO_PBSELC[P4SELC] Bits */ -#define P4SELC_OFS ( 8) /*!< P4SELC Offset */ -#define P4SELC_M (0xff00) /*!< Port 4 Complement Select */ -/* DIO_PBIES[P3IES] Bits */ -#define P3IES_OFS ( 0) /*!< P3IES Offset */ -#define P3IES_M (0x00ff) /*!< Port 3 Interrupt Edge Select */ -/* DIO_PBIES[P4IES] Bits */ -#define P4IES_OFS ( 8) /*!< P4IES Offset */ -#define P4IES_M (0xff00) /*!< Port 4 Interrupt Edge Select */ -/* DIO_PBIE[P3IE] Bits */ -#define P3IE_OFS ( 0) /*!< P3IE Offset */ -#define P3IE_M (0x00ff) /*!< Port 3 Interrupt Enable */ -/* DIO_PBIE[P4IE] Bits */ -#define P4IE_OFS ( 8) /*!< P4IE Offset */ -#define P4IE_M (0xff00) /*!< Port 4 Interrupt Enable */ -/* DIO_PBIFG[P3IFG] Bits */ -#define P3IFG_OFS ( 0) /*!< P3IFG Offset */ -#define P3IFG_M (0x00ff) /*!< Port 3 Interrupt Flag */ -/* DIO_PBIFG[P4IFG] Bits */ -#define P4IFG_OFS ( 8) /*!< P4IFG Offset */ -#define P4IFG_M (0xff00) /*!< Port 4 Interrupt Flag */ -/* DIO_P4IV[P4IV] Bits */ -#define P4IV_OFS ( 0) /*!< P4IV Offset */ -#define P4IV_M (0x001f) /*!< Port 4 interrupt vector value */ -#define P4IV0 (0x0001) /*!< Port 4 interrupt vector value */ -#define P4IV1 (0x0002) /*!< Port 4 interrupt vector value */ -#define P4IV2 (0x0004) /*!< Port 4 interrupt vector value */ -#define P4IV3 (0x0008) /*!< Port 4 interrupt vector value */ -#define P4IV4 (0x0010) /*!< Port 4 interrupt vector value */ -#define P4IV_0 (0x0000) /*!< No interrupt pending */ -#define P4IV_2 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */ -#define P4IV_4 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */ -#define P4IV_6 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */ -#define P4IV_8 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */ -#define P4IV_10 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */ -#define P4IV_12 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */ -#define P4IV_14 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */ -#define P4IV_16 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */ -#define P4IV__NONE (0x0000) /*!< No interrupt pending */ -#define P4IV__P4IFG0 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */ -#define P4IV__P4IFG1 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */ -#define P4IV__P4IFG2 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */ -#define P4IV__P4IFG3 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */ -#define P4IV__P4IFG4 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */ -#define P4IV__P4IFG5 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */ -#define P4IV__P4IFG6 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */ -#define P4IV__P4IFG7 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */ -/* DIO_PCIN[P5IN] Bits */ -#define P5IN_OFS ( 0) /*!< P5IN Offset */ -#define P5IN_M (0x00ff) /*!< Port 5 Input */ -/* DIO_PCIN[P6IN] Bits */ -#define P6IN_OFS ( 8) /*!< P6IN Offset */ -#define P6IN_M (0xff00) /*!< Port 6 Input */ -/* DIO_PCOUT[P5OUT] Bits */ -#define P5OUT_OFS ( 0) /*!< P5OUT Offset */ -#define P5OUT_M (0x00ff) /*!< Port 5 Output */ -/* DIO_PCOUT[P6OUT] Bits */ -#define P6OUT_OFS ( 8) /*!< P6OUT Offset */ -#define P6OUT_M (0xff00) /*!< Port 6 Output */ -/* DIO_PCDIR[P5DIR] Bits */ -#define P5DIR_OFS ( 0) /*!< P5DIR Offset */ -#define P5DIR_M (0x00ff) /*!< Port 5 Direction */ -/* DIO_PCDIR[P6DIR] Bits */ -#define P6DIR_OFS ( 8) /*!< P6DIR Offset */ -#define P6DIR_M (0xff00) /*!< Port 6 Direction */ -/* DIO_PCREN[P5REN] Bits */ -#define P5REN_OFS ( 0) /*!< P5REN Offset */ -#define P5REN_M (0x00ff) /*!< Port 5 Resistor Enable */ -/* DIO_PCREN[P6REN] Bits */ -#define P6REN_OFS ( 8) /*!< P6REN Offset */ -#define P6REN_M (0xff00) /*!< Port 6 Resistor Enable */ -/* DIO_PCDS[P5DS] Bits */ -#define P5DS_OFS ( 0) /*!< P5DS Offset */ -#define P5DS_M (0x00ff) /*!< Port 5 Drive Strength */ -/* DIO_PCDS[P6DS] Bits */ -#define P6DS_OFS ( 8) /*!< P6DS Offset */ -#define P6DS_M (0xff00) /*!< Port 6 Drive Strength */ -/* DIO_PCSEL0[P5SEL0] Bits */ -#define P5SEL0_OFS ( 0) /*!< P5SEL0 Offset */ -#define P5SEL0_M (0x00ff) /*!< Port 5 Select 0 */ -/* DIO_PCSEL0[P6SEL0] Bits */ -#define P6SEL0_OFS ( 8) /*!< P6SEL0 Offset */ -#define P6SEL0_M (0xff00) /*!< Port 6 Select 0 */ -/* DIO_PCSEL1[P5SEL1] Bits */ -#define P5SEL1_OFS ( 0) /*!< P5SEL1 Offset */ -#define P5SEL1_M (0x00ff) /*!< Port 5 Select 1 */ -/* DIO_PCSEL1[P6SEL1] Bits */ -#define P6SEL1_OFS ( 8) /*!< P6SEL1 Offset */ -#define P6SEL1_M (0xff00) /*!< Port 6 Select 1 */ -/* DIO_P5IV[P5IV] Bits */ -#define P5IV_OFS ( 0) /*!< P5IV Offset */ -#define P5IV_M (0x001f) /*!< Port 5 interrupt vector value */ -#define P5IV0 (0x0001) /*!< Port 5 interrupt vector value */ -#define P5IV1 (0x0002) /*!< Port 5 interrupt vector value */ -#define P5IV2 (0x0004) /*!< Port 5 interrupt vector value */ -#define P5IV3 (0x0008) /*!< Port 5 interrupt vector value */ -#define P5IV4 (0x0010) /*!< Port 5 interrupt vector value */ -#define P5IV_0 (0x0000) /*!< No interrupt pending */ -#define P5IV_2 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */ -#define P5IV_4 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */ -#define P5IV_6 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */ -#define P5IV_8 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */ -#define P5IV_10 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */ -#define P5IV_12 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */ -#define P5IV_14 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */ -#define P5IV_16 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */ -#define P5IV__NONE (0x0000) /*!< No interrupt pending */ -#define P5IV__P5IFG0 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */ -#define P5IV__P5IFG1 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */ -#define P5IV__P5IFG2 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */ -#define P5IV__P5IFG3 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */ -#define P5IV__P5IFG4 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */ -#define P5IV__P5IFG5 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */ -#define P5IV__P5IFG6 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */ -#define P5IV__P5IFG7 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */ -/* DIO_PCSELC[P5SELC] Bits */ -#define P5SELC_OFS ( 0) /*!< P5SELC Offset */ -#define P5SELC_M (0x00ff) /*!< Port 5 Complement Select */ -/* DIO_PCSELC[P6SELC] Bits */ -#define P6SELC_OFS ( 8) /*!< P6SELC Offset */ -#define P6SELC_M (0xff00) /*!< Port 6 Complement Select */ -/* DIO_PCIES[P5IES] Bits */ -#define P5IES_OFS ( 0) /*!< P5IES Offset */ -#define P5IES_M (0x00ff) /*!< Port 5 Interrupt Edge Select */ -/* DIO_PCIES[P6IES] Bits */ -#define P6IES_OFS ( 8) /*!< P6IES Offset */ -#define P6IES_M (0xff00) /*!< Port 6 Interrupt Edge Select */ -/* DIO_PCIE[P5IE] Bits */ -#define P5IE_OFS ( 0) /*!< P5IE Offset */ -#define P5IE_M (0x00ff) /*!< Port 5 Interrupt Enable */ -/* DIO_PCIE[P6IE] Bits */ -#define P6IE_OFS ( 8) /*!< P6IE Offset */ -#define P6IE_M (0xff00) /*!< Port 6 Interrupt Enable */ -/* DIO_PCIFG[P5IFG] Bits */ -#define P5IFG_OFS ( 0) /*!< P5IFG Offset */ -#define P5IFG_M (0x00ff) /*!< Port 5 Interrupt Flag */ -/* DIO_PCIFG[P6IFG] Bits */ -#define P6IFG_OFS ( 8) /*!< P6IFG Offset */ -#define P6IFG_M (0xff00) /*!< Port 6 Interrupt Flag */ -/* DIO_P6IV[P6IV] Bits */ -#define P6IV_OFS ( 0) /*!< P6IV Offset */ -#define P6IV_M (0x001f) /*!< Port 6 interrupt vector value */ -#define P6IV0 (0x0001) /*!< Port 6 interrupt vector value */ -#define P6IV1 (0x0002) /*!< Port 6 interrupt vector value */ -#define P6IV2 (0x0004) /*!< Port 6 interrupt vector value */ -#define P6IV3 (0x0008) /*!< Port 6 interrupt vector value */ -#define P6IV4 (0x0010) /*!< Port 6 interrupt vector value */ -#define P6IV_0 (0x0000) /*!< No interrupt pending */ -#define P6IV_2 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */ -#define P6IV_4 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */ -#define P6IV_6 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */ -#define P6IV_8 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */ -#define P6IV_10 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */ -#define P6IV_12 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */ -#define P6IV_14 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */ -#define P6IV_16 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */ -#define P6IV__NONE (0x0000) /*!< No interrupt pending */ -#define P6IV__P6IFG0 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */ -#define P6IV__P6IFG1 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */ -#define P6IV__P6IFG2 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */ -#define P6IV__P6IFG3 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */ -#define P6IV__P6IFG4 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */ -#define P6IV__P6IFG5 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */ -#define P6IV__P6IFG6 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */ -#define P6IV__P6IFG7 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */ -/* DIO_PDIN[P7IN] Bits */ -#define P7IN_OFS ( 0) /*!< P7IN Offset */ -#define P7IN_M (0x00ff) /*!< Port 7 Input */ -/* DIO_PDIN[P8IN] Bits */ -#define P8IN_OFS ( 8) /*!< P8IN Offset */ -#define P8IN_M (0xff00) /*!< Port 8 Input */ -/* DIO_PDOUT[P7OUT] Bits */ -#define P7OUT_OFS ( 0) /*!< P7OUT Offset */ -#define P7OUT_M (0x00ff) /*!< Port 7 Output */ -/* DIO_PDOUT[P8OUT] Bits */ -#define P8OUT_OFS ( 8) /*!< P8OUT Offset */ -#define P8OUT_M (0xff00) /*!< Port 8 Output */ -/* DIO_PDDIR[P7DIR] Bits */ -#define P7DIR_OFS ( 0) /*!< P7DIR Offset */ -#define P7DIR_M (0x00ff) /*!< Port 7 Direction */ -/* DIO_PDDIR[P8DIR] Bits */ -#define P8DIR_OFS ( 8) /*!< P8DIR Offset */ -#define P8DIR_M (0xff00) /*!< Port 8 Direction */ -/* DIO_PDREN[P7REN] Bits */ -#define P7REN_OFS ( 0) /*!< P7REN Offset */ -#define P7REN_M (0x00ff) /*!< Port 7 Resistor Enable */ -/* DIO_PDREN[P8REN] Bits */ -#define P8REN_OFS ( 8) /*!< P8REN Offset */ -#define P8REN_M (0xff00) /*!< Port 8 Resistor Enable */ -/* DIO_PDDS[P7DS] Bits */ -#define P7DS_OFS ( 0) /*!< P7DS Offset */ -#define P7DS_M (0x00ff) /*!< Port 7 Drive Strength */ -/* DIO_PDDS[P8DS] Bits */ -#define P8DS_OFS ( 8) /*!< P8DS Offset */ -#define P8DS_M (0xff00) /*!< Port 8 Drive Strength */ -/* DIO_PDSEL0[P7SEL0] Bits */ -#define P7SEL0_OFS ( 0) /*!< P7SEL0 Offset */ -#define P7SEL0_M (0x00ff) /*!< Port 7 Select 0 */ -/* DIO_PDSEL0[P8SEL0] Bits */ -#define P8SEL0_OFS ( 8) /*!< P8SEL0 Offset */ -#define P8SEL0_M (0xff00) /*!< Port 8 Select 0 */ -/* DIO_PDSEL1[P7SEL1] Bits */ -#define P7SEL1_OFS ( 0) /*!< P7SEL1 Offset */ -#define P7SEL1_M (0x00ff) /*!< Port 7 Select 1 */ -/* DIO_PDSEL1[P8SEL1] Bits */ -#define P8SEL1_OFS ( 8) /*!< P8SEL1 Offset */ -#define P8SEL1_M (0xff00) /*!< Port 8 Select 1 */ -/* DIO_P7IV[P7IV] Bits */ -#define P7IV_OFS ( 0) /*!< P7IV Offset */ -#define P7IV_M (0x001f) /*!< Port 7 interrupt vector value */ -#define P7IV0 (0x0001) /*!< Port 7 interrupt vector value */ -#define P7IV1 (0x0002) /*!< Port 7 interrupt vector value */ -#define P7IV2 (0x0004) /*!< Port 7 interrupt vector value */ -#define P7IV3 (0x0008) /*!< Port 7 interrupt vector value */ -#define P7IV4 (0x0010) /*!< Port 7 interrupt vector value */ -#define P7IV_0 (0x0000) /*!< No interrupt pending */ -#define P7IV_2 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */ -#define P7IV_4 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */ -#define P7IV_6 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */ -#define P7IV_8 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */ -#define P7IV_10 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */ -#define P7IV_12 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */ -#define P7IV_14 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */ -#define P7IV_16 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */ -#define P7IV__NONE (0x0000) /*!< No interrupt pending */ -#define P7IV__P7IFG0 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */ -#define P7IV__P7IFG1 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */ -#define P7IV__P7IFG2 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */ -#define P7IV__P7IFG3 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */ -#define P7IV__P7IFG4 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */ -#define P7IV__P7IFG5 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */ -#define P7IV__P7IFG6 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */ -#define P7IV__P7IFG7 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */ -/* DIO_PDSELC[P7SELC] Bits */ -#define P7SELC_OFS ( 0) /*!< P7SELC Offset */ -#define P7SELC_M (0x00ff) /*!< Port 7 Complement Select */ -/* DIO_PDSELC[P8SELC] Bits */ -#define P8SELC_OFS ( 8) /*!< P8SELC Offset */ -#define P8SELC_M (0xff00) /*!< Port 8 Complement Select */ -/* DIO_PDIES[P7IES] Bits */ -#define P7IES_OFS ( 0) /*!< P7IES Offset */ -#define P7IES_M (0x00ff) /*!< Port 7 Interrupt Edge Select */ -/* DIO_PDIES[P8IES] Bits */ -#define P8IES_OFS ( 8) /*!< P8IES Offset */ -#define P8IES_M (0xff00) /*!< Port 8 Interrupt Edge Select */ -/* DIO_PDIE[P7IE] Bits */ -#define P7IE_OFS ( 0) /*!< P7IE Offset */ -#define P7IE_M (0x00ff) /*!< Port 7 Interrupt Enable */ -/* DIO_PDIE[P8IE] Bits */ -#define P8IE_OFS ( 8) /*!< P8IE Offset */ -#define P8IE_M (0xff00) /*!< Port 8 Interrupt Enable */ -/* DIO_PDIFG[P7IFG] Bits */ -#define P7IFG_OFS ( 0) /*!< P7IFG Offset */ -#define P7IFG_M (0x00ff) /*!< Port 7 Interrupt Flag */ -/* DIO_PDIFG[P8IFG] Bits */ -#define P8IFG_OFS ( 8) /*!< P8IFG Offset */ -#define P8IFG_M (0xff00) /*!< Port 8 Interrupt Flag */ -/* DIO_P8IV[P8IV] Bits */ -#define P8IV_OFS ( 0) /*!< P8IV Offset */ -#define P8IV_M (0x001f) /*!< Port 8 interrupt vector value */ -#define P8IV0 (0x0001) /*!< Port 8 interrupt vector value */ -#define P8IV1 (0x0002) /*!< Port 8 interrupt vector value */ -#define P8IV2 (0x0004) /*!< Port 8 interrupt vector value */ -#define P8IV3 (0x0008) /*!< Port 8 interrupt vector value */ -#define P8IV4 (0x0010) /*!< Port 8 interrupt vector value */ -#define P8IV_0 (0x0000) /*!< No interrupt pending */ -#define P8IV_2 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */ -#define P8IV_4 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */ -#define P8IV_6 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */ -#define P8IV_8 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */ -#define P8IV_10 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */ -#define P8IV_12 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */ -#define P8IV_14 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */ -#define P8IV_16 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */ -#define P8IV__NONE (0x0000) /*!< No interrupt pending */ -#define P8IV__P8IFG0 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */ -#define P8IV__P8IFG1 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */ -#define P8IV__P8IFG2 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */ -#define P8IV__P8IFG3 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */ -#define P8IV__P8IFG4 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */ -#define P8IV__P8IFG5 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */ -#define P8IV__P8IFG6 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */ -#define P8IV__P8IFG7 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */ -/* DIO_PEIN[P9IN] Bits */ -#define P9IN_OFS ( 0) /*!< P9IN Offset */ -#define P9IN_M (0x00ff) /*!< Port 9 Input */ -/* DIO_PEIN[P10IN] Bits */ -#define P10IN_OFS ( 8) /*!< P10IN Offset */ -#define P10IN_M (0xff00) /*!< Port 10 Input */ -/* DIO_PEOUT[P9OUT] Bits */ -#define P9OUT_OFS ( 0) /*!< P9OUT Offset */ -#define P9OUT_M (0x00ff) /*!< Port 9 Output */ -/* DIO_PEOUT[P10OUT] Bits */ -#define P10OUT_OFS ( 8) /*!< P10OUT Offset */ -#define P10OUT_M (0xff00) /*!< Port 10 Output */ -/* DIO_PEDIR[P9DIR] Bits */ -#define P9DIR_OFS ( 0) /*!< P9DIR Offset */ -#define P9DIR_M (0x00ff) /*!< Port 9 Direction */ -/* DIO_PEDIR[P10DIR] Bits */ -#define P10DIR_OFS ( 8) /*!< P10DIR Offset */ -#define P10DIR_M (0xff00) /*!< Port 10 Direction */ -/* DIO_PEREN[P9REN] Bits */ -#define P9REN_OFS ( 0) /*!< P9REN Offset */ -#define P9REN_M (0x00ff) /*!< Port 9 Resistor Enable */ -/* DIO_PEREN[P10REN] Bits */ -#define P10REN_OFS ( 8) /*!< P10REN Offset */ -#define P10REN_M (0xff00) /*!< Port 10 Resistor Enable */ -/* DIO_PEDS[P9DS] Bits */ -#define P9DS_OFS ( 0) /*!< P9DS Offset */ -#define P9DS_M (0x00ff) /*!< Port 9 Drive Strength */ -/* DIO_PEDS[P10DS] Bits */ -#define P10DS_OFS ( 8) /*!< P10DS Offset */ -#define P10DS_M (0xff00) /*!< Port 10 Drive Strength */ -/* DIO_PESEL0[P9SEL0] Bits */ -#define P9SEL0_OFS ( 0) /*!< P9SEL0 Offset */ -#define P9SEL0_M (0x00ff) /*!< Port 9 Select 0 */ -/* DIO_PESEL0[P10SEL0] Bits */ -#define P10SEL0_OFS ( 8) /*!< P10SEL0 Offset */ -#define P10SEL0_M (0xff00) /*!< Port 10 Select 0 */ -/* DIO_PESEL1[P9SEL1] Bits */ -#define P9SEL1_OFS ( 0) /*!< P9SEL1 Offset */ -#define P9SEL1_M (0x00ff) /*!< Port 9 Select 1 */ -/* DIO_PESEL1[P10SEL1] Bits */ -#define P10SEL1_OFS ( 8) /*!< P10SEL1 Offset */ -#define P10SEL1_M (0xff00) /*!< Port 10 Select 1 */ -/* DIO_P9IV[P9IV] Bits */ -#define P9IV_OFS ( 0) /*!< P9IV Offset */ -#define P9IV_M (0x001f) /*!< Port 9 interrupt vector value */ -#define P9IV0 (0x0001) /*!< Port 9 interrupt vector value */ -#define P9IV1 (0x0002) /*!< Port 9 interrupt vector value */ -#define P9IV2 (0x0004) /*!< Port 9 interrupt vector value */ -#define P9IV3 (0x0008) /*!< Port 9 interrupt vector value */ -#define P9IV4 (0x0010) /*!< Port 9 interrupt vector value */ -#define P9IV_0 (0x0000) /*!< No interrupt pending */ -#define P9IV_2 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */ -#define P9IV_4 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */ -#define P9IV_6 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */ -#define P9IV_8 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */ -#define P9IV_10 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */ -#define P9IV_12 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */ -#define P9IV_14 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */ -#define P9IV_16 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */ -#define P9IV__NONE (0x0000) /*!< No interrupt pending */ -#define P9IV__P9IFG0 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */ -#define P9IV__P9IFG1 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */ -#define P9IV__P9IFG2 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */ -#define P9IV__P9IFG3 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */ -#define P9IV__P9IFG4 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */ -#define P9IV__P9IFG5 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */ -#define P9IV__P9IFG6 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */ -#define P9IV__P9IFG7 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */ -/* DIO_PESELC[P9SELC] Bits */ -#define P9SELC_OFS ( 0) /*!< P9SELC Offset */ -#define P9SELC_M (0x00ff) /*!< Port 9 Complement Select */ -/* DIO_PESELC[P10SELC] Bits */ -#define P10SELC_OFS ( 8) /*!< P10SELC Offset */ -#define P10SELC_M (0xff00) /*!< Port 10 Complement Select */ -/* DIO_PEIES[P9IES] Bits */ -#define P9IES_OFS ( 0) /*!< P9IES Offset */ -#define P9IES_M (0x00ff) /*!< Port 9 Interrupt Edge Select */ -/* DIO_PEIES[P10IES] Bits */ -#define P10IES_OFS ( 8) /*!< P10IES Offset */ -#define P10IES_M (0xff00) /*!< Port 10 Interrupt Edge Select */ -/* DIO_PEIE[P9IE] Bits */ -#define P9IE_OFS ( 0) /*!< P9IE Offset */ -#define P9IE_M (0x00ff) /*!< Port 9 Interrupt Enable */ -/* DIO_PEIE[P10IE] Bits */ -#define P10IE_OFS ( 8) /*!< P10IE Offset */ -#define P10IE_M (0xff00) /*!< Port 10 Interrupt Enable */ -/* DIO_PEIFG[P9IFG] Bits */ -#define P9IFG_OFS ( 0) /*!< P9IFG Offset */ -#define P9IFG_M (0x00ff) /*!< Port 9 Interrupt Flag */ -/* DIO_PEIFG[P10IFG] Bits */ -#define P10IFG_OFS ( 8) /*!< P10IFG Offset */ -#define P10IFG_M (0xff00) /*!< Port 10 Interrupt Flag */ -/* DIO_P10IV[P10IV] Bits */ -#define P10IV_OFS ( 0) /*!< P10IV Offset */ -#define P10IV_M (0x001f) /*!< Port 10 interrupt vector value */ -#define P10IV0 (0x0001) /*!< Port 10 interrupt vector value */ -#define P10IV1 (0x0002) /*!< Port 10 interrupt vector value */ -#define P10IV2 (0x0004) /*!< Port 10 interrupt vector value */ -#define P10IV3 (0x0008) /*!< Port 10 interrupt vector value */ -#define P10IV4 (0x0010) /*!< Port 10 interrupt vector value */ -#define P10IV_0 (0x0000) /*!< No interrupt pending */ -#define P10IV_2 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */ -#define P10IV_4 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */ -#define P10IV_6 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */ -#define P10IV_8 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */ -#define P10IV_10 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */ -#define P10IV_12 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */ -#define P10IV_14 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */ -#define P10IV_16 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */ -#define P10IV__NONE (0x0000) /*!< No interrupt pending */ -#define P10IV__P10IFG0 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */ -#define P10IV__P10IFG1 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */ -#define P10IV__P10IFG2 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */ -#define P10IV__P10IFG3 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */ -#define P10IV__P10IFG4 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */ -#define P10IV__P10IFG5 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */ -#define P10IV__P10IFG6 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */ -#define P10IV__P10IFG7 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */ - - -/****************************************************************************** -* EUSCI_A Bits (legacy section) -******************************************************************************/ -/* UCA0CTLW0[UCSWRST] Bits */ -#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */ -/* UCA0CTLW0[UCTXBRK] Bits */ -#define UCTXBRK_OFS EUSCI_A_CTLW0_TXBRK_OFS /*!< UCTXBRK Offset */ -#define UCTXBRK EUSCI_A_CTLW0_TXBRK /*!< Transmit break */ -/* UCA0CTLW0[UCTXADDR] Bits */ -#define UCTXADDR_OFS EUSCI_A_CTLW0_TXADDR_OFS /*!< UCTXADDR Offset */ -#define UCTXADDR EUSCI_A_CTLW0_TXADDR /*!< Transmit address */ -/* UCA0CTLW0[UCDORM] Bits */ -#define UCDORM_OFS EUSCI_A_CTLW0_DORM_OFS /*!< UCDORM Offset */ -#define UCDORM EUSCI_A_CTLW0_DORM /*!< Dormant */ -/* UCA0CTLW0[UCBRKIE] Bits */ -#define UCBRKIE_OFS EUSCI_A_CTLW0_BRKIE_OFS /*!< UCBRKIE Offset */ -#define UCBRKIE EUSCI_A_CTLW0_BRKIE /*!< Receive break character interrupt enable */ -/* UCA0CTLW0[UCRXEIE] Bits */ -#define UCRXEIE_OFS EUSCI_A_CTLW0_RXEIE_OFS /*!< UCRXEIE Offset */ -#define UCRXEIE EUSCI_A_CTLW0_RXEIE /*!< Receive erroneous-character interrupt enable */ -/* UCA0CTLW0[UCSSEL] Bits */ -#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */ -#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< UCLK */ -#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */ -#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */ -#define UCSSEL__UCLK EUSCI_A_CTLW0_SSEL__UCLK /*!< UCLK */ -#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */ -#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCA0CTLW0[UCSYNC] Bits */ -#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCA0CTLW0[UCMODE] Bits */ -#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */ -#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI_A mode */ -#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< UART mode */ -#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< Idle-line multiprocessor mode */ -#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< Address-bit multiprocessor mode */ -#define UCMODE_3 EUSCI_A_CTLW0_MODE_3 /*!< UART mode with automatic baud-rate detection */ -/* UCA0CTLW0[UCSPB] Bits */ -#define UCSPB_OFS EUSCI_A_CTLW0_SPB_OFS /*!< UCSPB Offset */ -#define UCSPB EUSCI_A_CTLW0_SPB /*!< Stop bit select */ -/* UCA0CTLW0[UC7BIT] Bits */ -#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */ -/* UCA0CTLW0[UCMSB] Bits */ -#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */ -#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */ -/* UCA0CTLW0[UCPAR] Bits */ -#define UCPAR_OFS EUSCI_A_CTLW0_PAR_OFS /*!< UCPAR Offset */ -#define UCPAR EUSCI_A_CTLW0_PAR /*!< Parity select */ -/* UCA0CTLW0[UCPEN] Bits */ -#define UCPEN_OFS EUSCI_A_CTLW0_PEN_OFS /*!< UCPEN Offset */ -#define UCPEN EUSCI_A_CTLW0_PEN /*!< Parity enable */ -/* UCA0CTLW0_SPI[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */ -/* UCA0CTLW0_SPI[UCSTEM] Bits */ -#define UCSTEM_OFS EUSCI_A_CTLW0_STEM_OFS /*!< UCSTEM Offset */ -#define UCSTEM EUSCI_A_CTLW0_STEM /*!< STE mode select in master mode. */ -/* UCA0CTLW0_SPI[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */ -//#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< Reserved */ -//#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */ -//#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCA0CTLW0_SPI[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCA0CTLW0_SPI[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI mode */ -//#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */ -//#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */ -/* UCA0CTLW0_SPI[UCMST] Bits */ -#define UCMST_OFS EUSCI_A_CTLW0_MST_OFS /*!< UCMST Offset */ -#define UCMST EUSCI_A_CTLW0_MST /*!< Master mode select */ -/* UCA0CTLW0_SPI[UC7BIT] Bits */ -//#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -//#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */ -/* UCA0CTLW0_SPI[UCMSB] Bits */ -//#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */ -//#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */ -/* UCA0CTLW0_SPI[UCCKPL] Bits */ -#define UCCKPL_OFS EUSCI_A_CTLW0_CKPL_OFS /*!< UCCKPL Offset */ -#define UCCKPL EUSCI_A_CTLW0_CKPL /*!< Clock polarity select */ -/* UCA0CTLW0_SPI[UCCKPH] Bits */ -#define UCCKPH_OFS EUSCI_A_CTLW0_CKPH_OFS /*!< UCCKPH Offset */ -#define UCCKPH EUSCI_A_CTLW0_CKPH /*!< Clock phase select */ -/* UCA0CTLW1[UCGLIT] Bits */ -#define UCGLIT_OFS EUSCI_A_CTLW1_GLIT_OFS /*!< UCGLIT Offset */ -#define UCGLIT_M EUSCI_A_CTLW1_GLIT_MASK /*!< Deglitch time */ -#define UCGLIT0 EUSCI_A_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */ -#define UCGLIT1 EUSCI_A_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */ -#define UCGLIT_0 EUSCI_A_CTLW1_GLIT_0 /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define UCGLIT_1 EUSCI_A_CTLW1_GLIT_1 /*!< Approximately 50 ns */ -#define UCGLIT_2 EUSCI_A_CTLW1_GLIT_2 /*!< Approximately 100 ns */ -#define UCGLIT_3 EUSCI_A_CTLW1_GLIT_3 /*!< Approximately 200 ns */ -/* UCA0MCTLW[UCOS16] Bits */ -#define UCOS16_OFS EUSCI_A_MCTLW_OS16_OFS /*!< UCOS16 Offset */ -#define UCOS16 EUSCI_A_MCTLW_OS16 /*!< Oversampling mode enabled */ -/* UCA0MCTLW[UCBRF] Bits */ -#define UCBRF_OFS EUSCI_A_MCTLW_BRF_OFS /*!< UCBRF Offset */ -#define UCBRF_M EUSCI_A_MCTLW_BRF_MASK /*!< First modulation stage select */ -/* UCA0MCTLW[UCBRS] Bits */ -#define UCBRS_OFS EUSCI_A_MCTLW_BRS_OFS /*!< UCBRS Offset */ -#define UCBRS_M EUSCI_A_MCTLW_BRS_MASK /*!< Second modulation stage select */ -/* UCA0STATW[UCBUSY] Bits */ -#define UCBUSY_OFS EUSCI_A_STATW_BUSY_OFS /*!< UCBUSY Offset */ -#define UCBUSY EUSCI_A_STATW_BUSY /*!< eUSCI_A busy */ -/* UCA0STATW[UCADDR_UCIDLE] Bits */ -#define UCADDR_UCIDLE_OFS EUSCI_A_STATW_ADDR_IDLE_OFS /*!< UCADDR_UCIDLE Offset */ -#define UCADDR_UCIDLE EUSCI_A_STATW_ADDR_IDLE /*!< Address received / Idle line detected */ -/* UCA0STATW[UCRXERR] Bits */ -#define UCRXERR_OFS EUSCI_A_STATW_RXERR_OFS /*!< UCRXERR Offset */ -#define UCRXERR EUSCI_A_STATW_RXERR /*!< Receive error flag */ -/* UCA0STATW[UCBRK] Bits */ -#define UCBRK_OFS EUSCI_A_STATW_BRK_OFS /*!< UCBRK Offset */ -#define UCBRK EUSCI_A_STATW_BRK /*!< Break detect flag */ -/* UCA0STATW[UCPE] Bits */ -#define UCPE_OFS EUSCI_A_STATW_PE_OFS /*!< UCPE Offset */ -#define UCPE EUSCI_A_STATW_PE -/* UCA0STATW[UCOE] Bits */ -#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */ -#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */ -/* UCA0STATW[UCFE] Bits */ -#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */ -#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */ -/* UCA0STATW[UCLISTEN] Bits */ -#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */ -/* UCA0STATW_SPI[UCBUSY] Bits */ -//#define UCBUSY_OFS EUSCI_A_STATW_SPI_BUSY_OFS /*!< UCBUSY Offset */ -//#define UCBUSY EUSCI_A_STATW_SPI_BUSY /*!< eUSCI_A busy */ -/* UCA0STATW_SPI[UCOE] Bits */ -//#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */ -//#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */ -/* UCA0STATW_SPI[UCFE] Bits */ -//#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */ -//#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */ -/* UCA0STATW_SPI[UCLISTEN] Bits */ -//#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -//#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */ -/* UCA0RXBUF[UCRXBUF] Bits */ -#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCA0RXBUF_SPI[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCA0TXBUF[UCTXBUF] Bits */ -#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCA0TXBUF_SPI[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCA0ABCTL[UCABDEN] Bits */ -#define UCABDEN_OFS EUSCI_A_ABCTL_ABDEN_OFS /*!< UCABDEN Offset */ -#define UCABDEN EUSCI_A_ABCTL_ABDEN /*!< Automatic baud-rate detect enable */ -/* UCA0ABCTL[UCBTOE] Bits */ -#define UCBTOE_OFS EUSCI_A_ABCTL_BTOE_OFS /*!< UCBTOE Offset */ -#define UCBTOE EUSCI_A_ABCTL_BTOE /*!< Break time out error */ -/* UCA0ABCTL[UCSTOE] Bits */ -#define UCSTOE_OFS EUSCI_A_ABCTL_STOE_OFS /*!< UCSTOE Offset */ -#define UCSTOE EUSCI_A_ABCTL_STOE /*!< Synch field time out error */ -/* UCA0ABCTL[UCDELIM] Bits */ -#define UCDELIM_OFS EUSCI_A_ABCTL_DELIM_OFS /*!< UCDELIM Offset */ -#define UCDELIM_M EUSCI_A_ABCTL_DELIM_MASK /*!< Break/synch delimiter length */ -#define UCDELIM0 EUSCI_A_ABCTL_DELIM0 /*!< UCDELIM Bit 0 */ -#define UCDELIM1 EUSCI_A_ABCTL_DELIM1 /*!< UCDELIM Bit 1 */ -#define UCDELIM_0 EUSCI_A_ABCTL_DELIM_0 /*!< 1 bit time */ -#define UCDELIM_1 EUSCI_A_ABCTL_DELIM_1 /*!< 2 bit times */ -#define UCDELIM_2 EUSCI_A_ABCTL_DELIM_2 /*!< 3 bit times */ -#define UCDELIM_3 EUSCI_A_ABCTL_DELIM_3 /*!< 4 bit times */ -/* UCA0IRCTL[UCIREN] Bits */ -#define UCIREN_OFS EUSCI_A_IRCTL_IREN_OFS /*!< UCIREN Offset */ -#define UCIREN EUSCI_A_IRCTL_IREN /*!< IrDA encoder/decoder enable */ -/* UCA0IRCTL[UCIRTXCLK] Bits */ -#define UCIRTXCLK_OFS EUSCI_A_IRCTL_IRTXCLK_OFS /*!< UCIRTXCLK Offset */ -#define UCIRTXCLK EUSCI_A_IRCTL_IRTXCLK /*!< IrDA transmit pulse clock select */ -/* UCA0IRCTL[UCIRTXPL] Bits */ -#define UCIRTXPL_OFS EUSCI_A_IRCTL_IRTXPL_OFS /*!< UCIRTXPL Offset */ -#define UCIRTXPL_M EUSCI_A_IRCTL_IRTXPL_MASK /*!< Transmit pulse length */ -/* UCA0IRCTL[UCIRRXFE] Bits */ -#define UCIRRXFE_OFS EUSCI_A_IRCTL_IRRXFE_OFS /*!< UCIRRXFE Offset */ -#define UCIRRXFE EUSCI_A_IRCTL_IRRXFE /*!< IrDA receive filter enabled */ -/* UCA0IRCTL[UCIRRXPL] Bits */ -#define UCIRRXPL_OFS EUSCI_A_IRCTL_IRRXPL_OFS /*!< UCIRRXPL Offset */ -#define UCIRRXPL EUSCI_A_IRCTL_IRRXPL /*!< IrDA receive input UCAxRXD polarity */ -/* UCA0IRCTL[UCIRRXFL] Bits */ -#define UCIRRXFL_OFS EUSCI_A_IRCTL_IRRXFL_OFS /*!< UCIRRXFL Offset */ -#define UCIRRXFL_M EUSCI_A_IRCTL_IRRXFL_MASK /*!< Receive filter length */ -/* UCA0IE[UCRXIE] Bits */ -#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */ -#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -/* UCA0IE[UCTXIE] Bits */ -#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */ -#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ -/* UCA0IE[UCSTTIE] Bits */ -#define UCSTTIE_OFS EUSCI_A_IE_STTIE_OFS /*!< UCSTTIE Offset */ -#define UCSTTIE EUSCI_A_IE_STTIE /*!< Start bit interrupt enable */ -/* UCA0IE[UCTXCPTIE] Bits */ -#define UCTXCPTIE_OFS EUSCI_A_IE_TXCPTIE_OFS /*!< UCTXCPTIE Offset */ -#define UCTXCPTIE EUSCI_A_IE_TXCPTIE /*!< Transmit complete interrupt enable */ -/* UCA0IE_SPI[UCRXIE] Bits */ -//#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */ -//#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -/* UCA0IE_SPI[UCTXIE] Bits */ -//#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */ -//#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ -/* UCA0IFG[UCRXIFG] Bits */ -#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCA0IFG[UCTXIFG] Bits */ -#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */ -/* UCA0IFG[UCSTTIFG] Bits */ -#define UCSTTIFG_OFS EUSCI_A_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */ -#define UCSTTIFG EUSCI_A_IFG_STTIFG /*!< Start bit interrupt flag */ -/* UCA0IFG[UCTXCPTIFG] Bits */ -#define UCTXCPTIFG_OFS EUSCI_A_IFG_TXCPTIFG_OFS /*!< UCTXCPTIFG Offset */ -#define UCTXCPTIFG EUSCI_A_IFG_TXCPTIFG /*!< Transmit ready interrupt enable */ -/* UCA0IFG_SPI[UCRXIFG] Bits */ -//#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -//#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCA0IFG_SPI[UCTXIFG] Bits */ -//#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -//#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */ - -/****************************************************************************** -* EUSCI_B Bits (legacy section) -******************************************************************************/ -/* UCB0CTLW0[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */ -/* UCB0CTLW0[UCTXSTT] Bits */ -#define UCTXSTT_OFS EUSCI_B_CTLW0_TXSTT_OFS /*!< UCTXSTT Offset */ -#define UCTXSTT EUSCI_B_CTLW0_TXSTT /*!< Transmit START condition in master mode */ -/* UCB0CTLW0[UCTXSTP] Bits */ -#define UCTXSTP_OFS EUSCI_B_CTLW0_TXSTP_OFS /*!< UCTXSTP Offset */ -#define UCTXSTP EUSCI_B_CTLW0_TXSTP /*!< Transmit STOP condition in master mode */ -/* UCB0CTLW0[UCTXNACK] Bits */ -#define UCTXNACK_OFS EUSCI_B_CTLW0_TXNACK_OFS /*!< UCTXNACK Offset */ -#define UCTXNACK EUSCI_B_CTLW0_TXNACK /*!< Transmit a NACK */ -/* UCB0CTLW0[UCTR] Bits */ -#define UCTR_OFS EUSCI_B_CTLW0_TR_OFS /*!< UCTR Offset */ -#define UCTR EUSCI_B_CTLW0_TR /*!< Transmitter/receiver */ -/* UCB0CTLW0[UCTXACK] Bits */ -#define UCTXACK_OFS EUSCI_B_CTLW0_TXACK_OFS /*!< UCTXACK Offset */ -#define UCTXACK EUSCI_B_CTLW0_TXACK /*!< Transmit ACK condition in slave mode */ -/* UCB0CTLW0[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */ -//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< UCLKI */ -//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */ -#define UCSSEL_3 EUSCI_B_CTLW0_UCSSEL_3 /*!< SMCLK */ -#define UCSSEL__UCLKI EUSCI_B_CTLW0_SSEL__UCLKI /*!< UCLKI */ -//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCB0CTLW0[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCB0CTLW0[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI_B mode */ -//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */ -/* UCB0CTLW0[UCMST] Bits */ -//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */ -//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */ -/* UCB0CTLW0[UCMM] Bits */ -#define UCMM_OFS EUSCI_B_CTLW0_MM_OFS /*!< UCMM Offset */ -#define UCMM EUSCI_B_CTLW0_MM /*!< Multi-master environment select */ -/* UCB0CTLW0[UCSLA10] Bits */ -#define UCSLA10_OFS EUSCI_B_CTLW0_SLA10_OFS /*!< UCSLA10 Offset */ -#define UCSLA10 EUSCI_B_CTLW0_SLA10 /*!< Slave addressing mode select */ -/* UCB0CTLW0[UCA10] Bits */ -#define UCA10_OFS EUSCI_B_CTLW0_A10_OFS /*!< UCA10 Offset */ -#define UCA10 EUSCI_B_CTLW0_A10 /*!< Own addressing mode select */ -/* UCB0CTLW0_SPI[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */ -/* UCB0CTLW0_SPI[UCSTEM] Bits */ -//#define UCSTEM_OFS EUSCI_B_CTLW0_STEM_OFS /*!< UCSTEM Offset */ -//#define UCSTEM EUSCI_B_CTLW0_STEM /*!< STE mode select in master mode. */ -/* UCB0CTLW0_SPI[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */ -//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< Reserved */ -//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */ -//#define UCSSEL_3 EUSCI_B_CTLW0_UCSSEL_3 /*!< SMCLK */ -//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCB0CTLW0_SPI[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCB0CTLW0_SPI[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI mode */ -//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */ -//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */ -//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */ -/* UCB0CTLW0_SPI[UCMST] Bits */ -//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */ -//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */ -/* UCB0CTLW0_SPI[UC7BIT] Bits */ -//#define UC7BIT_OFS EUSCI_B_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -//#define UC7BIT EUSCI_B_CTLW0_SEVENBIT /*!< Character length */ -/* UCB0CTLW0_SPI[UCMSB] Bits */ -//#define UCMSB_OFS EUSCI_B_CTLW0_MSB_OFS /*!< UCMSB Offset */ -//#define UCMSB EUSCI_B_CTLW0_MSB /*!< MSB first select */ -/* UCB0CTLW0_SPI[UCCKPL] Bits */ -//#define UCCKPL_OFS EUSCI_B_CTLW0_CKPL_OFS /*!< UCCKPL Offset */ -//#define UCCKPL EUSCI_B_CTLW0_CKPL /*!< Clock polarity select */ -/* UCB0CTLW0_SPI[UCCKPH] Bits */ -//#define UCCKPH_OFS EUSCI_B_CTLW0_CKPH_OFS /*!< UCCKPH Offset */ -//#define UCCKPH EUSCI_B_CTLW0_CKPH /*!< Clock phase select */ -/* UCB0CTLW1[UCGLIT] Bits */ -//#define UCGLIT_OFS EUSCI_B_CTLW1_GLIT_OFS /*!< UCGLIT Offset */ -//#define UCGLIT_M EUSCI_B_CTLW1_GLIT_MASK /*!< Deglitch time */ -//#define UCGLIT0 EUSCI_B_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */ -//#define UCGLIT1 EUSCI_B_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */ -//#define UCGLIT_0 EUSCI_B_CTLW1_GLIT_0 /*!< 50 ns */ -//#define UCGLIT_1 EUSCI_B_CTLW1_GLIT_1 /*!< 25 ns */ -//#define UCGLIT_2 EUSCI_B_CTLW1_GLIT_2 /*!< 12.5 ns */ -//#define UCGLIT_3 EUSCI_B_CTLW1_GLIT_3 /*!< 6.25 ns */ -/* UCB0CTLW1[UCASTP] Bits */ -#define UCASTP_OFS EUSCI_B_CTLW1_ASTP_OFS /*!< UCASTP Offset */ -#define UCASTP_M EUSCI_B_CTLW1_ASTP_MASK /*!< Automatic STOP condition generation */ -#define UCASTP0 EUSCI_B_CTLW1_ASTP0 /*!< UCASTP Bit 0 */ -#define UCASTP1 EUSCI_B_CTLW1_ASTP1 /*!< UCASTP Bit 1 */ -#define UCASTP_0 EUSCI_B_CTLW1_ASTP_0 /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define UCASTP_1 EUSCI_B_CTLW1_ASTP_1 /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define UCASTP_2 EUSCI_B_CTLW1_ASTP_2 /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* UCB0CTLW1[UCSWACK] Bits */ -#define UCSWACK_OFS EUSCI_B_CTLW1_SWACK_OFS /*!< UCSWACK Offset */ -#define UCSWACK EUSCI_B_CTLW1_SWACK /*!< SW or HW ACK control */ -/* UCB0CTLW1[UCSTPNACK] Bits */ -#define UCSTPNACK_OFS EUSCI_B_CTLW1_STPNACK_OFS /*!< UCSTPNACK Offset */ -#define UCSTPNACK EUSCI_B_CTLW1_STPNACK /*!< ACK all master bytes */ -/* UCB0CTLW1[UCCLTO] Bits */ -#define UCCLTO_OFS EUSCI_B_CTLW1_CLTO_OFS /*!< UCCLTO Offset */ -#define UCCLTO_M EUSCI_B_CTLW1_CLTO_MASK /*!< Clock low timeout select */ -#define UCCLTO0 EUSCI_B_CTLW1_CLTO0 /*!< UCCLTO Bit 0 */ -#define UCCLTO1 EUSCI_B_CTLW1_CLTO1 /*!< UCCLTO Bit 1 */ -#define UCCLTO_0 EUSCI_B_CTLW1_CLTO_0 /*!< Disable clock low timeout counter */ -#define UCCLTO_1 EUSCI_B_CTLW1_CLTO_1 /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define UCCLTO_2 EUSCI_B_CTLW1_CLTO_2 /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define UCCLTO_3 EUSCI_B_CTLW1_CLTO_3 /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* UCB0CTLW1[UCETXINT] Bits */ -#define UCETXINT_OFS EUSCI_B_CTLW1_ETXINT_OFS /*!< UCETXINT Offset */ -#define UCETXINT EUSCI_B_CTLW1_ETXINT /*!< Early UCTXIFG0 */ -/* UCB0STATW[UCBBUSY] Bits */ -#define UCBBUSY_OFS EUSCI_B_STATW_BBUSY_OFS /*!< UCBBUSY Offset */ -#define UCBBUSY EUSCI_B_STATW_BBUSY /*!< Bus busy */ -/* UCB0STATW[UCGC] Bits */ -#define UCGC_OFS EUSCI_B_STATW_GC_OFS /*!< UCGC Offset */ -#define UCGC EUSCI_B_STATW_GC /*!< General call address received */ -/* UCB0STATW[UCSCLLOW] Bits */ -#define UCSCLLOW_OFS EUSCI_B_STATW_SCLLOW_OFS /*!< UCSCLLOW Offset */ -#define UCSCLLOW EUSCI_B_STATW_SCLLOW /*!< SCL low */ -/* UCB0STATW[UCBCNT] Bits */ -#define UCBCNT_OFS EUSCI_B_STATW_BCNT_OFS /*!< UCBCNT Offset */ -#define UCBCNT_M EUSCI_B_STATW_BCNT_MASK /*!< Hardware byte counter value */ -/* UCB0STATW_SPI[UCBUSY] Bits */ -//#define UCBUSY_OFS EUSCI_B_STATW_SPI_BUSY_OFS /*!< UCBUSY Offset */ -//#define UCBUSY EUSCI_B_STATW_SPI_BUSY /*!< eUSCI_B busy */ -/* UCB0STATW_SPI[UCOE] Bits */ -//#define UCOE_OFS EUSCI_B_STATW_OE_OFS /*!< UCOE Offset */ -//#define UCOE EUSCI_B_STATW_OE /*!< Overrun error flag */ -/* UCB0STATW_SPI[UCFE] Bits */ -//#define UCFE_OFS EUSCI_B_STATW_FE_OFS /*!< UCFE Offset */ -//#define UCFE EUSCI_B_STATW_FE /*!< Framing error flag */ -/* UCB0STATW_SPI[UCLISTEN] Bits */ -//#define UCLISTEN_OFS EUSCI_B_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -//#define UCLISTEN EUSCI_B_STATW_LISTEN /*!< Listen enable */ -/* UCB0TBCNT[UCTBCNT] Bits */ -#define UCTBCNT_OFS EUSCI_B_TBCNT_TBCNT_OFS /*!< UCTBCNT Offset */ -#define UCTBCNT_M EUSCI_B_TBCNT_TBCNT_MASK /*!< Byte counter threshold value */ -/* UCB0RXBUF[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCB0RXBUF_SPI[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCB0TXBUF[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCB0TXBUF_SPI[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCB0I2COA0[I2COA0] Bits */ -#define I2COA0_OFS EUSCI_B_I2COA0_I2COA0_OFS /*!< I2COA0 Offset */ -#define I2COA0_M EUSCI_B_I2COA0_I2COA0_MASK /*!< I2C own address */ -/* UCB0I2COA0[UCOAEN] Bits */ -#define UCOAEN_OFS EUSCI_B_I2COA0_OAEN_OFS /*!< UCOAEN Offset */ -#define UCOAEN EUSCI_B_I2COA0_OAEN /*!< Own Address enable register */ -/* UCB0I2COA0[UCGCEN] Bits */ -#define UCGCEN_OFS EUSCI_B_I2COA0_GCEN_OFS /*!< UCGCEN Offset */ -#define UCGCEN EUSCI_B_I2COA0_GCEN /*!< General call response enable */ -/* UCB0I2COA1[I2COA1] Bits */ -#define I2COA1_OFS EUSCI_B_I2COA1_I2COA1_OFS /*!< I2COA1 Offset */ -#define I2COA1_M EUSCI_B_I2COA1_I2COA1_MASK /*!< I2C own address */ -/* UCB0I2COA1[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA1_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA1_OAEN /*!< Own Address enable register */ -/* UCB0I2COA2[I2COA2] Bits */ -#define I2COA2_OFS EUSCI_B_I2COA2_I2COA2_OFS /*!< I2COA2 Offset */ -#define I2COA2_M EUSCI_B_I2COA2_I2COA2_MASK /*!< I2C own address */ -/* UCB0I2COA2[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA2_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA2_OAEN /*!< Own Address enable register */ -/* UCB0I2COA3[I2COA3] Bits */ -#define I2COA3_OFS EUSCI_B_I2COA3_I2COA3_OFS /*!< I2COA3 Offset */ -#define I2COA3_M EUSCI_B_I2COA3_I2COA3_MASK /*!< I2C own address */ -/* UCB0I2COA3[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA3_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA3_OAEN /*!< Own Address enable register */ -/* UCB0ADDRX[ADDRX] Bits */ -#define ADDRX_OFS EUSCI_B_ADDRX_ADDRX_OFS /*!< ADDRX Offset */ -#define ADDRX_M EUSCI_B_ADDRX_ADDRX_MASK /*!< Received Address Register */ -#define ADDRX0 EUSCI_B_ADDRX_ADDRX0 /*!< ADDRX Bit 0 */ -#define ADDRX1 EUSCI_B_ADDRX_ADDRX1 /*!< ADDRX Bit 1 */ -#define ADDRX2 EUSCI_B_ADDRX_ADDRX2 /*!< ADDRX Bit 2 */ -#define ADDRX3 EUSCI_B_ADDRX_ADDRX3 /*!< ADDRX Bit 3 */ -#define ADDRX4 EUSCI_B_ADDRX_ADDRX4 /*!< ADDRX Bit 4 */ -#define ADDRX5 EUSCI_B_ADDRX_ADDRX5 /*!< ADDRX Bit 5 */ -#define ADDRX6 EUSCI_B_ADDRX_ADDRX6 /*!< ADDRX Bit 6 */ -#define ADDRX7 EUSCI_B_ADDRX_ADDRX7 /*!< ADDRX Bit 7 */ -#define ADDRX8 EUSCI_B_ADDRX_ADDRX8 /*!< ADDRX Bit 8 */ -#define ADDRX9 EUSCI_B_ADDRX_ADDRX9 /*!< ADDRX Bit 9 */ -/* UCB0ADDMASK[ADDMASK] Bits */ -#define ADDMASK_OFS EUSCI_B_ADDMASK_ADDMASK_OFS /*!< ADDMASK Offset */ -#define ADDMASK_M EUSCI_B_ADDMASK_ADDMASK_MASK -/* UCB0I2CSA[I2CSA] Bits */ -#define I2CSA_OFS EUSCI_B_I2CSA_I2CSA_OFS /*!< I2CSA Offset */ -#define I2CSA_M EUSCI_B_I2CSA_I2CSA_MASK /*!< I2C slave address */ -/* UCB0IE[UCRXIE0] Bits */ -#define UCRXIE0_OFS EUSCI_B_IE_RXIE0_OFS /*!< UCRXIE0 Offset */ -#define UCRXIE0 EUSCI_B_IE_RXIE0 /*!< Receive interrupt enable 0 */ -/* UCB0IE[UCTXIE0] Bits */ -#define UCTXIE0_OFS EUSCI_B_IE_TXIE0_OFS /*!< UCTXIE0 Offset */ -#define UCTXIE0 EUSCI_B_IE_TXIE0 /*!< Transmit interrupt enable 0 */ -/* UCB0IE[UCSTTIE] Bits */ -//#define UCSTTIE_OFS EUSCI_B_IE_STTIE_OFS /*!< UCSTTIE Offset */ -//#define UCSTTIE EUSCI_B_IE_STTIE /*!< START condition interrupt enable */ -/* UCB0IE[UCSTPIE] Bits */ -#define UCSTPIE_OFS EUSCI_B_IE_STPIE_OFS /*!< UCSTPIE Offset */ -#define UCSTPIE EUSCI_B_IE_STPIE /*!< STOP condition interrupt enable */ -/* UCB0IE[UCALIE] Bits */ -#define UCALIE_OFS EUSCI_B_IE_ALIE_OFS /*!< UCALIE Offset */ -#define UCALIE EUSCI_B_IE_ALIE /*!< Arbitration lost interrupt enable */ -/* UCB0IE[UCNACKIE] Bits */ -#define UCNACKIE_OFS EUSCI_B_IE_NACKIE_OFS /*!< UCNACKIE Offset */ -#define UCNACKIE EUSCI_B_IE_NACKIE /*!< Not-acknowledge interrupt enable */ -/* UCB0IE[UCBCNTIE] Bits */ -#define UCBCNTIE_OFS EUSCI_B_IE_BCNTIE_OFS /*!< UCBCNTIE Offset */ -#define UCBCNTIE EUSCI_B_IE_BCNTIE /*!< Byte counter interrupt enable */ -/* UCB0IE[UCCLTOIE] Bits */ -#define UCCLTOIE_OFS EUSCI_B_IE_CLTOIE_OFS /*!< UCCLTOIE Offset */ -#define UCCLTOIE EUSCI_B_IE_CLTOIE /*!< Clock low timeout interrupt enable */ -/* UCB0IE[UCRXIE1] Bits */ -#define UCRXIE1_OFS EUSCI_B_IE_RXIE1_OFS /*!< UCRXIE1 Offset */ -#define UCRXIE1 EUSCI_B_IE_RXIE1 /*!< Receive interrupt enable 1 */ -/* UCB0IE[UCTXIE1] Bits */ -#define UCTXIE1_OFS EUSCI_B_IE_TXIE1_OFS /*!< UCTXIE1 Offset */ -#define UCTXIE1 EUSCI_B_IE_TXIE1 /*!< Transmit interrupt enable 1 */ -/* UCB0IE[UCRXIE2] Bits */ -#define UCRXIE2_OFS EUSCI_B_IE_RXIE2_OFS /*!< UCRXIE2 Offset */ -#define UCRXIE2 EUSCI_B_IE_RXIE2 /*!< Receive interrupt enable 2 */ -/* UCB0IE[UCTXIE2] Bits */ -#define UCTXIE2_OFS EUSCI_B_IE_TXIE2_OFS /*!< UCTXIE2 Offset */ -#define UCTXIE2 EUSCI_B_IE_TXIE2 /*!< Transmit interrupt enable 2 */ -/* UCB0IE[UCRXIE3] Bits */ -#define UCRXIE3_OFS EUSCI_B_IE_RXIE3_OFS /*!< UCRXIE3 Offset */ -#define UCRXIE3 EUSCI_B_IE_RXIE3 /*!< Receive interrupt enable 3 */ -/* UCB0IE[UCTXIE3] Bits */ -#define UCTXIE3_OFS EUSCI_B_IE_TXIE3_OFS /*!< UCTXIE3 Offset */ -#define UCTXIE3 EUSCI_B_IE_TXIE3 /*!< Transmit interrupt enable 3 */ -/* UCB0IE[UCBIT9IE] Bits */ -#define UCBIT9IE_OFS EUSCI_B_IE_BIT9IE_OFS /*!< UCBIT9IE Offset */ -#define UCBIT9IE EUSCI_B_IE_BIT9IE /*!< Bit position 9 interrupt enable */ -/* UCB0IE_SPI[UCRXIE] Bits */ -//#define UCRXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Offset */ -//#define UCRXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -/* UCB0IE_SPI[UCTXIE] Bits */ -//#define UCTXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Offset */ -//#define UCTXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ -/* UCB0IFG[UCRXIFG0] Bits */ -#define UCRXIFG0_OFS EUSCI_B_IFG_RXIFG0_OFS /*!< UCRXIFG0 Offset */ -#define UCRXIFG0 EUSCI_B_IFG_RXIFG0 /*!< eUSCI_B receive interrupt flag 0 */ -/* UCB0IFG[UCTXIFG0] Bits */ -#define UCTXIFG0_OFS EUSCI_B_IFG_TXIFG0_OFS /*!< UCTXIFG0 Offset */ -#define UCTXIFG0 EUSCI_B_IFG_TXIFG0 /*!< eUSCI_B transmit interrupt flag 0 */ -/* UCB0IFG[UCSTTIFG] Bits */ -//#define UCSTTIFG_OFS EUSCI_B_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */ -//#define UCSTTIFG EUSCI_B_IFG_STTIFG /*!< START condition interrupt flag */ -/* UCB0IFG[UCSTPIFG] Bits */ -#define UCSTPIFG_OFS EUSCI_B_IFG_STPIFG_OFS /*!< UCSTPIFG Offset */ -#define UCSTPIFG EUSCI_B_IFG_STPIFG /*!< STOP condition interrupt flag */ -/* UCB0IFG[UCALIFG] Bits */ -#define UCALIFG_OFS EUSCI_B_IFG_ALIFG_OFS /*!< UCALIFG Offset */ -#define UCALIFG EUSCI_B_IFG_ALIFG /*!< Arbitration lost interrupt flag */ -/* UCB0IFG[UCNACKIFG] Bits */ -#define UCNACKIFG_OFS EUSCI_B_IFG_NACKIFG_OFS /*!< UCNACKIFG Offset */ -#define UCNACKIFG EUSCI_B_IFG_NACKIFG /*!< Not-acknowledge received interrupt flag */ -/* UCB0IFG[UCBCNTIFG] Bits */ -#define UCBCNTIFG_OFS EUSCI_B_IFG_BCNTIFG_OFS /*!< UCBCNTIFG Offset */ -#define UCBCNTIFG EUSCI_B_IFG_BCNTIFG /*!< Byte counter interrupt flag */ -/* UCB0IFG[UCCLTOIFG] Bits */ -#define UCCLTOIFG_OFS EUSCI_B_IFG_CLTOIFG_OFS /*!< UCCLTOIFG Offset */ -#define UCCLTOIFG EUSCI_B_IFG_CLTOIFG /*!< Clock low timeout interrupt flag */ -/* UCB0IFG[UCRXIFG1] Bits */ -#define UCRXIFG1_OFS EUSCI_B_IFG_RXIFG1_OFS /*!< UCRXIFG1 Offset */ -#define UCRXIFG1 EUSCI_B_IFG_RXIFG1 /*!< eUSCI_B receive interrupt flag 1 */ -/* UCB0IFG[UCTXIFG1] Bits */ -#define UCTXIFG1_OFS EUSCI_B_IFG_TXIFG1_OFS /*!< UCTXIFG1 Offset */ -#define UCTXIFG1 EUSCI_B_IFG_TXIFG1 /*!< eUSCI_B transmit interrupt flag 1 */ -/* UCB0IFG[UCRXIFG2] Bits */ -#define UCRXIFG2_OFS EUSCI_B_IFG_RXIFG2_OFS /*!< UCRXIFG2 Offset */ -#define UCRXIFG2 EUSCI_B_IFG_RXIFG2 /*!< eUSCI_B receive interrupt flag 2 */ -/* UCB0IFG[UCTXIFG2] Bits */ -#define UCTXIFG2_OFS EUSCI_B_IFG_TXIFG2_OFS /*!< UCTXIFG2 Offset */ -#define UCTXIFG2 EUSCI_B_IFG_TXIFG2 /*!< eUSCI_B transmit interrupt flag 2 */ -/* UCB0IFG[UCRXIFG3] Bits */ -#define UCRXIFG3_OFS EUSCI_B_IFG_RXIFG3_OFS /*!< UCRXIFG3 Offset */ -#define UCRXIFG3 EUSCI_B_IFG_RXIFG3 /*!< eUSCI_B receive interrupt flag 3 */ -/* UCB0IFG[UCTXIFG3] Bits */ -#define UCTXIFG3_OFS EUSCI_B_IFG_TXIFG3_OFS /*!< UCTXIFG3 Offset */ -#define UCTXIFG3 EUSCI_B_IFG_TXIFG3 /*!< eUSCI_B transmit interrupt flag 3 */ -/* UCB0IFG[UCBIT9IFG] Bits */ -#define UCBIT9IFG_OFS EUSCI_B_IFG_BIT9IFG_OFS /*!< UCBIT9IFG Offset */ -#define UCBIT9IFG EUSCI_B_IFG_BIT9IFG /*!< Bit position 9 interrupt flag */ -/* UCB0IFG_SPI[UCRXIFG] Bits */ -//#define UCRXIFG_OFS EUSCI_B_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -//#define UCRXIFG EUSCI_B_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCB0IFG_SPI[UCTXIFG] Bits */ -//#define UCTXIFG_OFS EUSCI_B_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -//#define UCTXIFG EUSCI_B_IFG_TXIFG /*!< Transmit interrupt flag */ - -/****************************************************************************** -* PMAP Bits (legacy section) -******************************************************************************/ -/* PMAPCTL[PMAPLOCKED] Bits */ -#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */ -#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */ -/* PMAPCTL[PMAPRECFG] Bits */ -#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */ -#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -/* PMAP_PMAPCTL[PMAPLOCKED] Bits */ -#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */ -#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */ -/* PMAP_PMAPCTL[PMAPRECFG] Bits */ -#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */ -#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */ - -#define PM_NONE PMAP_NONE -#define PM_UCA0CLK PMAP_UCA0CLK -#define PM_UCA0RXD PMAP_UCA0RXD -#define PM_UCA0SOMI PMAP_UCA0SOMI -#define PM_UCA0TXD PMAP_UCA0TXD -#define PM_UCA0SIMO PMAP_UCA0SIMO -#define PM_UCB0CLK PMAP_UCB0CLK -#define PM_UCB0SDA PMAP_UCB0SDA -#define PM_UCB0SIMO PMAP_UCB0SIMO -#define PM_UCB0SCL PMAP_UCB0SCL -#define PM_UCB0SOMI PMAP_UCB0SOMI -#define PM_UCA1STE PMAP_UCA1STE -#define PM_UCA1CLK PMAP_UCA1CLK -#define PM_UCA1RXD PMAP_UCA1RXD -#define PM_UCA1SOMI PMAP_UCA1SOMI -#define PM_UCA1TXD PMAP_UCA1TXD -#define PM_UCA1SIMO PMAP_UCA1SIMO -#define PM_UCA2STE PMAP_UCA2STE -#define PM_UCA2CLK PMAP_UCA2CLK -#define PM_UCA2RXD PMAP_UCA2RXD -#define PM_UCA2SOMI PMAP_UCA2SOMI -#define PM_UCA2TXD PMAP_UCA2TXD -#define PM_UCA2SIMO PMAP_UCA2SIMO -#define PM_UCB2STE PMAP_UCB2STE -#define PM_UCB2CLK PMAP_UCB2CLK -#define PM_UCB2SDA PMAP_UCB2SDA -#define PM_UCB2SIMO PMAP_UCB2SIMO -#define PM_UCB2SCL PMAP_UCB2SCL -#define PM_UCB2SOMI PMAP_UCB2SOMI -#define PM_TA0CCR0A PMAP_TA0CCR0A -#define PM_TA0CCR1A PMAP_TA0CCR1A -#define PM_TA0CCR2A PMAP_TA0CCR2A -#define PM_TA0CCR3A PMAP_TA0CCR3A -#define PM_TA0CCR4A PMAP_TA0CCR4A -#define PM_TA1CCR1A PMAP_TA1CCR1A -#define PM_TA1CCR2A PMAP_TA1CCR2A -#define PM_TA1CCR3A PMAP_TA1CCR3A -#define PM_TA1CCR4A PMAP_TA1CCR4A -#define PM_TA0CLK PMAP_TA0CLK -#define PM_CE0OUT PMAP_CE0OUT -#define PM_TA1CLK PMAP_TA1CLK -#define PM_CE1OUT PMAP_CE1OUT -#define PM_DMAE0 PMAP_DMAE0 -#define PM_SMCLK PMAP_SMCLK -#define PM_ANALOG PMAP_ANALOG - -#define PMAPKEY PMAP_KEYID_VAL /*!< Port Mapping Key */ -#define PMAPPWD PMAP_KEYID_VAL /*!< Legacy Definition: Mapping Key register */ -#define PMAPPW PMAP_KEYID_VAL /*!< Legacy Definition: Port Mapping Password */ - - -/****************************************************************************** -* REF_A Bits (legacy section) -******************************************************************************/ -/* REFCTL0[REFON] Bits */ -#define REFON_OFS REF_A_CTL0_ON_OFS /*!< REFON Offset */ -#define REFON REF_A_CTL0_ON /*!< Reference enable */ -/* REFCTL0[REFOUT] Bits */ -#define REFOUT_OFS REF_A_CTL0_OUT_OFS /*!< REFOUT Offset */ -#define REFOUT REF_A_CTL0_OUT /*!< Reference output buffer */ -/* REFCTL0[REFTCOFF] Bits */ -#define REFTCOFF_OFS REF_A_CTL0_TCOFF_OFS /*!< REFTCOFF Offset */ -#define REFTCOFF REF_A_CTL0_TCOFF /*!< Temperature sensor disabled */ -/* REFCTL0[REFVSEL] Bits */ -#define REFVSEL_OFS REF_A_CTL0_VSEL_OFS /*!< REFVSEL Offset */ -#define REFVSEL_M REF_A_CTL0_VSEL_MASK /*!< Reference voltage level select */ -#define REFVSEL0 REF_A_CTL0_VSEL0 /*!< REFVSEL Bit 0 */ -#define REFVSEL1 REF_A_CTL0_VSEL1 /*!< REFVSEL Bit 1 */ -#define REFVSEL_0 REF_A_CTL0_VSEL_0 /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REFVSEL_1 REF_A_CTL0_VSEL_1 /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REFVSEL_3 REF_A_CTL0_VSEL_3 /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REFCTL0[REFGENOT] Bits */ -#define REFGENOT_OFS REF_A_CTL0_GENOT_OFS /*!< REFGENOT Offset */ -#define REFGENOT REF_A_CTL0_GENOT /*!< Reference generator one-time trigger */ -/* REFCTL0[REFBGOT] Bits */ -#define REFBGOT_OFS REF_A_CTL0_BGOT_OFS /*!< REFBGOT Offset */ -#define REFBGOT REF_A_CTL0_BGOT /*!< Bandgap and bandgap buffer one-time trigger */ -/* REFCTL0[REFGENACT] Bits */ -#define REFGENACT_OFS REF_A_CTL0_GENACT_OFS /*!< REFGENACT Offset */ -#define REFGENACT REF_A_CTL0_GENACT /*!< Reference generator active */ -/* REFCTL0[REFBGACT] Bits */ -#define REFBGACT_OFS REF_A_CTL0_BGACT_OFS /*!< REFBGACT Offset */ -#define REFBGACT REF_A_CTL0_BGACT /*!< Reference bandgap active */ -/* REFCTL0[REFGENBUSY] Bits */ -#define REFGENBUSY_OFS REF_A_CTL0_GENBUSY_OFS /*!< REFGENBUSY Offset */ -#define REFGENBUSY REF_A_CTL0_GENBUSY /*!< Reference generator busy */ -/* REFCTL0[BGMODE] Bits */ -#define BGMODE_OFS REF_A_CTL0_BGMODE_OFS /*!< BGMODE Offset */ -#define BGMODE REF_A_CTL0_BGMODE /*!< Bandgap mode */ -/* REFCTL0[REFGENRDY] Bits */ -#define REFGENRDY_OFS REF_A_CTL0_GENRDY_OFS /*!< REFGENRDY Offset */ -#define REFGENRDY REF_A_CTL0_GENRDY /*!< Variable reference voltage ready status */ -/* REFCTL0[REFBGRDY] Bits */ -#define REFBGRDY_OFS REF_A_CTL0_BGRDY_OFS /*!< REFBGRDY Offset */ -#define REFBGRDY REF_A_CTL0_BGRDY /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RTC_C Bits (legacy section) -******************************************************************************/ -/* RTCCTL0[RTCRDYIFG] Bits */ -#define RTCRDYIFG_OFS RTC_C_CTL0_RDYIFG_OFS /*!< RTCRDYIFG Offset */ -#define RTCRDYIFG RTC_C_CTL0_RDYIFG /*!< Real-time clock ready interrupt flag */ -/* RTCCTL0[RTCAIFG] Bits */ -#define RTCAIFG_OFS RTC_C_CTL0_AIFG_OFS /*!< RTCAIFG Offset */ -#define RTCAIFG RTC_C_CTL0_AIFG /*!< Real-time clock alarm interrupt flag */ -/* RTCCTL0[RTCTEVIFG] Bits */ -#define RTCTEVIFG_OFS RTC_C_CTL0_TEVIFG_OFS /*!< RTCTEVIFG Offset */ -#define RTCTEVIFG RTC_C_CTL0_TEVIFG /*!< Real-time clock time event interrupt flag */ -/* RTCCTL0[RTCOFIFG] Bits */ -#define RTCOFIFG_OFS RTC_C_CTL0_OFIFG_OFS /*!< RTCOFIFG Offset */ -#define RTCOFIFG RTC_C_CTL0_OFIFG /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTCCTL0[RTCRDYIE] Bits */ -#define RTCRDYIE_OFS RTC_C_CTL0_RDYIE_OFS /*!< RTCRDYIE Offset */ -#define RTCRDYIE RTC_C_CTL0_RDYIE /*!< Real-time clock ready interrupt enable */ -/* RTCCTL0[RTCAIE] Bits */ -#define RTCAIE_OFS RTC_C_CTL0_AIE_OFS /*!< RTCAIE Offset */ -#define RTCAIE RTC_C_CTL0_AIE /*!< Real-time clock alarm interrupt enable */ -/* RTCCTL0[RTCTEVIE] Bits */ -#define RTCTEVIE_OFS RTC_C_CTL0_TEVIE_OFS /*!< RTCTEVIE Offset */ -#define RTCTEVIE RTC_C_CTL0_TEVIE /*!< Real-time clock time event interrupt enable */ -/* RTCCTL0[RTCOFIE] Bits */ -#define RTCOFIE_OFS RTC_C_CTL0_OFIE_OFS /*!< RTCOFIE Offset */ -#define RTCOFIE RTC_C_CTL0_OFIE /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTCCTL0[RTCKEY] Bits */ -#define RTCKEY_OFS RTC_C_CTL0_KEY_OFS /*!< RTCKEY Offset */ -#define RTCKEY_M RTC_C_CTL0_KEY_MASK /*!< Real-time clock key */ -/* RTCCTL13[RTCTEV] Bits */ -#define RTCTEV_OFS RTC_C_CTL13_TEV_OFS /*!< RTCTEV Offset */ -#define RTCTEV_M RTC_C_CTL13_TEV_MASK /*!< Real-time clock time event */ -#define RTCTEV0 RTC_C_CTL13_TEV0 /*!< RTCTEV Bit 0 */ -#define RTCTEV1 RTC_C_CTL13_TEV1 /*!< RTCTEV Bit 1 */ -#define RTCTEV_0 RTC_C_CTL13_TEV_0 /*!< Minute changed */ -#define RTCTEV_1 RTC_C_CTL13_TEV_1 /*!< Hour changed */ -#define RTCTEV_2 RTC_C_CTL13_TEV_2 /*!< Every day at midnight (00:00) */ -#define RTCTEV_3 RTC_C_CTL13_TEV_3 /*!< Every day at noon (12:00) */ -/* RTCCTL13[RTCSSEL] Bits */ -#define RTCSSEL_OFS RTC_C_CTL13_SSEL_OFS /*!< RTCSSEL Offset */ -#define RTCSSEL_M RTC_C_CTL13_SSEL_MASK /*!< Real-time clock source select */ -#define RTCSSEL0 RTC_C_CTL13_SSEL0 /*!< RTCSSEL Bit 0 */ -#define RTCSSEL1 RTC_C_CTL13_SSEL1 /*!< RTCSSEL Bit 1 */ -#define RTCSSEL_0 RTC_C_CTL13_SSEL_0 /*!< BCLK */ -#define RTCSSEL__BCLK RTC_C_CTL13_SSEL__BCLK /*!< BCLK */ -/* RTCCTL13[RTCRDY] Bits */ -#define RTCRDY_OFS RTC_C_CTL13_RDY_OFS /*!< RTCRDY Offset */ -#define RTCRDY RTC_C_CTL13_RDY /*!< Real-time clock ready */ -/* RTCCTL13[RTCMODE] Bits */ -#define RTCMODE_OFS RTC_C_CTL13_MODE_OFS /*!< RTCMODE Offset */ -#define RTCMODE RTC_C_CTL13_MODE -/* RTCCTL13[RTCHOLD] Bits */ -#define RTCHOLD_OFS RTC_C_CTL13_HOLD_OFS /*!< RTCHOLD Offset */ -#define RTCHOLD RTC_C_CTL13_HOLD /*!< Real-time clock hold */ -/* RTCCTL13[RTCBCD] Bits */ -#define RTCBCD_OFS RTC_C_CTL13_BCD_OFS /*!< RTCBCD Offset */ -#define RTCBCD RTC_C_CTL13_BCD /*!< Real-time clock BCD select */ -/* RTCCTL13[RTCCALF] Bits */ -#define RTCCALF_OFS RTC_C_CTL13_CALF_OFS /*!< RTCCALF Offset */ -#define RTCCALF_M RTC_C_CTL13_CALF_MASK /*!< Real-time clock calibration frequency */ -#define RTCCALF0 RTC_C_CTL13_CALF0 /*!< RTCCALF Bit 0 */ -#define RTCCALF1 RTC_C_CTL13_CALF1 /*!< RTCCALF Bit 1 */ -#define RTCCALF_0 RTC_C_CTL13_CALF_0 /*!< No frequency output to RTCCLK pin */ -#define RTCCALF_1 RTC_C_CTL13_CALF_1 /*!< 512 Hz */ -#define RTCCALF_2 RTC_C_CTL13_CALF_2 /*!< 256 Hz */ -#define RTCCALF_3 RTC_C_CTL13_CALF_3 /*!< 1 Hz */ -#define RTCCALF__NONE RTC_C_CTL13_CALF__NONE /*!< No frequency output to RTCCLK pin */ -#define RTCCALF__512 RTC_C_CTL13_CALF__512 /*!< 512 Hz */ -#define RTCCALF__256 RTC_C_CTL13_CALF__256 /*!< 256 Hz */ -#define RTCCALF__1 RTC_C_CTL13_CALF__1 /*!< 1 Hz */ -/* RTCOCAL[RTCOCAL] Bits */ -#define RTCOCAL_OFS RTC_C_OCAL_OCAL_OFS /*!< RTCOCAL Offset */ -#define RTCOCAL_M RTC_C_OCAL_OCAL_MASK /*!< Real-time clock offset error calibration */ -/* RTCOCAL[RTCOCALS] Bits */ -#define RTCOCALS_OFS RTC_C_OCAL_OCALS_OFS /*!< RTCOCALS Offset */ -#define RTCOCALS RTC_C_OCAL_OCALS /*!< Real-time clock offset error calibration sign */ -/* RTCTCMP[RTCTCMP] Bits */ -#define RTCTCMP_OFS RTC_C_TCMP_TCMPX_OFS /*!< RTCTCMP Offset */ -#define RTCTCMP_M RTC_C_TCMP_TCMPX_MASK /*!< Real-time clock temperature compensation */ -/* RTCTCMP[RTCTCOK] Bits */ -#define RTCTCOK_OFS RTC_C_TCMP_TCOK_OFS /*!< RTCTCOK Offset */ -#define RTCTCOK RTC_C_TCMP_TCOK /*!< Real-time clock temperature compensation write OK */ -/* RTCTCMP[RTCTCRDY] Bits */ -#define RTCTCRDY_OFS RTC_C_TCMP_TCRDY_OFS /*!< RTCTCRDY Offset */ -#define RTCTCRDY RTC_C_TCMP_TCRDY /*!< Real-time clock temperature compensation ready */ -/* RTCTCMP[RTCTCMPS] Bits */ -#define RTCTCMPS_OFS RTC_C_TCMP_TCMPS_OFS /*!< RTCTCMPS Offset */ -#define RTCTCMPS RTC_C_TCMP_TCMPS /*!< Real-time clock temperature compensation sign */ -/* RTCPS0CTL[RT0PSIFG] Bits */ -#define RT0PSIFG_OFS RTC_C_PS0CTL_RT0PSIFG_OFS /*!< RT0PSIFG Offset */ -#define RT0PSIFG RTC_C_PS0CTL_RT0PSIFG /*!< Prescale timer 0 interrupt flag */ -/* RTCPS0CTL[RT0PSIE] Bits */ -#define RT0PSIE_OFS RTC_C_PS0CTL_RT0PSIE_OFS /*!< RT0PSIE Offset */ -#define RT0PSIE RTC_C_PS0CTL_RT0PSIE /*!< Prescale timer 0 interrupt enable */ -/* RTCPS0CTL[RT0IP] Bits */ -#define RT0IP_OFS RTC_C_PS0CTL_RT0IP_OFS /*!< RT0IP Offset */ -#define RT0IP_M RTC_C_PS0CTL_RT0IP_MASK /*!< Prescale timer 0 interrupt interval */ -#define RT0IP0 RTC_C_PS0CTL_RT0IP0 /*!< RT0IP Bit 0 */ -#define RT0IP1 RTC_C_PS0CTL_RT0IP1 /*!< RT0IP Bit 1 */ -#define RT0IP2 RTC_C_PS0CTL_RT0IP2 /*!< RT0IP Bit 2 */ -#define RT0IP_0 RTC_C_PS0CTL_RT0IP_0 /*!< Divide by 2 */ -#define RT0IP_1 RTC_C_PS0CTL_RT0IP_1 /*!< Divide by 4 */ -#define RT0IP_2 RTC_C_PS0CTL_RT0IP_2 /*!< Divide by 8 */ -#define RT0IP_3 RTC_C_PS0CTL_RT0IP_3 /*!< Divide by 16 */ -#define RT0IP_4 RTC_C_PS0CTL_RT0IP_4 /*!< Divide by 32 */ -#define RT0IP_5 RTC_C_PS0CTL_RT0IP_5 /*!< Divide by 64 */ -#define RT0IP_6 RTC_C_PS0CTL_RT0IP_6 /*!< Divide by 128 */ -#define RT0IP_7 RTC_C_PS0CTL_RT0IP_7 /*!< Divide by 256 */ -#define RT0IP__2 RTC_C_PS0CTL_RT0IP__2 /*!< Divide by 2 */ -#define RT0IP__4 RTC_C_PS0CTL_RT0IP__4 /*!< Divide by 4 */ -#define RT0IP__8 RTC_C_PS0CTL_RT0IP__8 /*!< Divide by 8 */ -#define RT0IP__16 RTC_C_PS0CTL_RT0IP__16 /*!< Divide by 16 */ -#define RT0IP__32 RTC_C_PS0CTL_RT0IP__32 /*!< Divide by 32 */ -#define RT0IP__64 RTC_C_PS0CTL_RT0IP__64 /*!< Divide by 64 */ -#define RT0IP__128 RTC_C_PS0CTL_RT0IP__128 /*!< Divide by 128 */ -#define RT0IP__256 RTC_C_PS0CTL_RT0IP__256 /*!< Divide by 256 */ -/* RTCPS1CTL[RT1PSIFG] Bits */ -#define RT1PSIFG_OFS RTC_C_PS1CTL_RT1PSIFG_OFS /*!< RT1PSIFG Offset */ -#define RT1PSIFG RTC_C_PS1CTL_RT1PSIFG /*!< Prescale timer 1 interrupt flag */ -/* RTCPS1CTL[RT1PSIE] Bits */ -#define RT1PSIE_OFS RTC_C_PS1CTL_RT1PSIE_OFS /*!< RT1PSIE Offset */ -#define RT1PSIE RTC_C_PS1CTL_RT1PSIE /*!< Prescale timer 1 interrupt enable */ -/* RTCPS1CTL[RT1IP] Bits */ -#define RT1IP_OFS RTC_C_PS1CTL_RT1IP_OFS /*!< RT1IP Offset */ -#define RT1IP_M RTC_C_PS1CTL_RT1IP_MASK /*!< Prescale timer 1 interrupt interval */ -#define RT1IP0 RTC_C_PS1CTL_RT1IP0 /*!< RT1IP Bit 0 */ -#define RT1IP1 RTC_C_PS1CTL_RT1IP1 /*!< RT1IP Bit 1 */ -#define RT1IP2 RTC_C_PS1CTL_RT1IP2 /*!< RT1IP Bit 2 */ -#define RT1IP_0 RTC_C_PS1CTL_RT1IP_0 /*!< Divide by 2 */ -#define RT1IP_1 RTC_C_PS1CTL_RT1IP_1 /*!< Divide by 4 */ -#define RT1IP_2 RTC_C_PS1CTL_RT1IP_2 /*!< Divide by 8 */ -#define RT1IP_3 RTC_C_PS1CTL_RT1IP_3 /*!< Divide by 16 */ -#define RT1IP_4 RTC_C_PS1CTL_RT1IP_4 /*!< Divide by 32 */ -#define RT1IP_5 RTC_C_PS1CTL_RT1IP_5 /*!< Divide by 64 */ -#define RT1IP_6 RTC_C_PS1CTL_RT1IP_6 /*!< Divide by 128 */ -#define RT1IP_7 RTC_C_PS1CTL_RT1IP_7 /*!< Divide by 256 */ -#define RT1IP__2 RTC_C_PS1CTL_RT1IP__2 /*!< Divide by 2 */ -#define RT1IP__4 RTC_C_PS1CTL_RT1IP__4 /*!< Divide by 4 */ -#define RT1IP__8 RTC_C_PS1CTL_RT1IP__8 /*!< Divide by 8 */ -#define RT1IP__16 RTC_C_PS1CTL_RT1IP__16 /*!< Divide by 16 */ -#define RT1IP__32 RTC_C_PS1CTL_RT1IP__32 /*!< Divide by 32 */ -#define RT1IP__64 RTC_C_PS1CTL_RT1IP__64 /*!< Divide by 64 */ -#define RT1IP__128 RTC_C_PS1CTL_RT1IP__128 /*!< Divide by 128 */ -#define RT1IP__256 RTC_C_PS1CTL_RT1IP__256 /*!< Divide by 256 */ -/* RTCPS[RT0PS] Bits */ -#define RT0PS_OFS RTC_C_PS_RT0PS_OFS /*!< RT0PS Offset */ -#define RT0PS_M RTC_C_PS_RT0PS_MASK /*!< Prescale timer 0 counter value */ -/* RTCPS[RT1PS] Bits */ -#define RT1PS_OFS RTC_C_PS_RT1PS_OFS /*!< RT1PS Offset */ -#define RT1PS_M RTC_C_PS_RT1PS_MASK /*!< Prescale timer 1 counter value */ -/* RTCTIM0[SECONDS] Bits */ -#define SECONDS_OFS RTC_C_TIM0_SEC_OFS /*!< Seconds Offset */ -#define SECONDS_M RTC_C_TIM0_SEC_MASK /*!< Seconds (0 to 59) */ -/* RTCTIM0[MINUTES] Bits */ -#define MINUTES_OFS RTC_C_TIM0_MIN_OFS /*!< Minutes Offset */ -#define MINUTES_M RTC_C_TIM0_MIN_MASK /*!< Minutes (0 to 59) */ -/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */ -#define SECONDSLOWDIGIT_OFS RTC_C_TIM0_SEC_LD_OFS /*!< SecondsLowDigit Offset */ -#define SECONDSLOWDIGIT_M RTC_C_TIM0_SEC_LD_MASK /*!< Seconds low digit (0 to 9) */ -/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */ -#define SECONDSHIGHDIGIT_OFS RTC_C_TIM0_SEC_HD_OFS /*!< SecondsHighDigit Offset */ -#define SECONDSHIGHDIGIT_M RTC_C_TIM0_SEC_HD_MASK /*!< Seconds high digit (0 to 5) */ -/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */ -#define MINUTESLOWDIGIT_OFS RTC_C_TIM0_MIN_LD_OFS /*!< MinutesLowDigit Offset */ -#define MINUTESLOWDIGIT_M RTC_C_TIM0_MIN_LD_MASK /*!< Minutes low digit (0 to 9) */ -/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */ -#define MINUTESHIGHDIGIT_OFS RTC_C_TIM0_MIN_HD_OFS /*!< MinutesHighDigit Offset */ -#define MINUTESHIGHDIGIT_M RTC_C_TIM0_MIN_HD_MASK /*!< Minutes high digit (0 to 5) */ -/* RTCTIM1[HOURS] Bits */ -#define HOURS_OFS RTC_C_TIM1_HOUR_OFS /*!< Hours Offset */ -#define HOURS_M RTC_C_TIM1_HOUR_MASK /*!< Hours (0 to 23) */ -/* RTCTIM1[DAYOFWEEK] Bits */ -#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */ -#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */ -#define HOURSLOWDIGIT_OFS RTC_C_TIM1_HOUR_LD_OFS /*!< HoursLowDigit Offset */ -#define HOURSLOWDIGIT_M RTC_C_TIM1_HOUR_LD_MASK /*!< Hours low digit (0 to 9) */ -/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */ -#define HOURSHIGHDIGIT_OFS RTC_C_TIM1_HOUR_HD_OFS /*!< HoursHighDigit Offset */ -#define HOURSHIGHDIGIT_M RTC_C_TIM1_HOUR_HD_MASK /*!< Hours high digit (0 to 2) */ -/* RTCTIM1_BCD[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCDATE[DAY] Bits */ -#define DAY_OFS RTC_C_DATE_DAY_OFS /*!< Day Offset */ -#define DAY_M RTC_C_DATE_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */ -/* RTCDATE[MONTH] Bits */ -#define MONTH_OFS RTC_C_DATE_MON_OFS /*!< Month Offset */ -#define MONTH_M RTC_C_DATE_MON_MASK /*!< Month (1 to 12) */ -/* RTCDATE_BCD[DAYLOWDIGIT] Bits */ -#define DAYLOWDIGIT_OFS RTC_C_DATE_DAY_LD_OFS /*!< DayLowDigit Offset */ -#define DAYLOWDIGIT_M RTC_C_DATE_DAY_LD_MASK /*!< Day of month low digit (0 to 9) */ -/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */ -#define DAYHIGHDIGIT_OFS RTC_C_DATE_DAY_HD_OFS /*!< DayHighDigit Offset */ -#define DAYHIGHDIGIT_M RTC_C_DATE_DAY_HD_MASK /*!< Day of month high digit (0 to 3) */ -/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */ -#define MONTHLOWDIGIT_OFS RTC_C_DATE_MON_LD_OFS /*!< MonthLowDigit Offset */ -#define MONTHLOWDIGIT_M RTC_C_DATE_MON_LD_MASK /*!< Month low digit (0 to 9) */ -/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */ -#define MONTHHIGHDIGIT_OFS RTC_C_DATE_MON_HD_OFS /*!< MonthHighDigit Offset */ -#define MONTHHIGHDIGIT RTC_C_DATE_MON_HD /*!< Month high digit (0 or 1) */ -/* RTCYEAR[YEARLOWBYTE] Bits */ -#define YEARLOWBYTE_OFS RTC_C_YEAR_YEAR_LB_OFS /*!< YearLowByte Offset */ -#define YEARLOWBYTE_M RTC_C_YEAR_YEAR_LB_MASK /*!< Year low byte. Valid values for Year are 0 to 4095. */ -/* RTCYEAR[YEARHIGHBYTE] Bits */ -#define YEARHIGHBYTE_OFS RTC_C_YEAR_YEAR_HB_OFS /*!< YearHighByte Offset */ -#define YEARHIGHBYTE_M RTC_C_YEAR_YEAR_HB_MASK /*!< Year high byte. Valid values for Year are 0 to 4095. */ -/* RTCYEAR_BCD[YEAR] Bits */ -#define YEAR_OFS RTC_C_YEAR_YEAR_OFS /*!< Year Offset */ -#define YEAR_M RTC_C_YEAR_YEAR_MASK /*!< Year lowest digit (0 to 9) */ -/* RTCYEAR_BCD[DECADE] Bits */ -#define DECADE_OFS RTC_C_YEAR_DEC_OFS /*!< Decade Offset */ -#define DECADE_M RTC_C_YEAR_DEC_MASK /*!< Decade (0 to 9) */ -/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */ -#define CENTURYLOWDIGIT_OFS RTC_C_YEAR_CENT_LD_OFS /*!< CenturyLowDigit Offset */ -#define CENTURYLOWDIGIT_M RTC_C_YEAR_CENT_LD_MASK /*!< Century low digit (0 to 9) */ -/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */ -#define CENTURYHIGHDIGIT_OFS RTC_C_YEAR_CENT_HD_OFS /*!< CenturyHighDigit Offset */ -#define CENTURYHIGHDIGIT_M RTC_C_YEAR_CENT_HD_MASK /*!< Century high digit (0 to 4) */ -/* RTCAMINHR[MINUTES] Bits */ -//#define MINUTES_OFS RTC_C_AMINHR_MIN_OFS /*!< Minutes Offset */ -//#define MINUTES_M RTC_C_AMINHR_MIN_MASK /*!< Minutes (0 to 59) */ -/* RTCAMINHR[MINAE] Bits */ -#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */ -#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */ -/* RTCAMINHR[HOURS] Bits */ -//#define HOURS_OFS RTC_C_AMINHR_HOUR_OFS /*!< Hours Offset */ -//#define HOURS_M RTC_C_AMINHR_HOUR_MASK /*!< Hours (0 to 23) */ -/* RTCAMINHR[HOURAE] Bits */ -#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */ -#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */ -/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */ -//#define MINUTESLOWDIGIT_OFS RTC_C_AMINHR_MIN_LD_OFS /*!< MinutesLowDigit Offset */ -//#define MINUTESLOWDIGIT_M RTC_C_AMINHR_MIN_LD_MASK /*!< Minutes low digit (0 to 9) */ -/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */ -//#define MINUTESHIGHDIGIT_OFS RTC_C_AMINHR_MIN_HD_OFS /*!< MinutesHighDigit Offset */ -//#define MINUTESHIGHDIGIT_M RTC_C_AMINHR_MIN_HD_MASK /*!< Minutes high digit (0 to 5) */ -/* RTCAMINHR_BCD[MINAE] Bits */ -//#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */ -//#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */ -/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */ -//#define HOURSLOWDIGIT_OFS RTC_C_AMINHR_HOUR_LD_OFS /*!< HoursLowDigit Offset */ -//#define HOURSLOWDIGIT_M RTC_C_AMINHR_HOUR_LD_MASK /*!< Hours low digit (0 to 9) */ -/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */ -//#define HOURSHIGHDIGIT_OFS RTC_C_AMINHR_HOUR_HD_OFS /*!< HoursHighDigit Offset */ -//#define HOURSHIGHDIGIT_M RTC_C_AMINHR_HOUR_HD_MASK /*!< Hours high digit (0 to 2) */ -/* RTCAMINHR_BCD[HOURAE] Bits */ -//#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */ -//#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */ -/* RTCADOWDAY[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCADOWDAY[DOWAE] Bits */ -#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */ -#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */ -/* RTCADOWDAY[DAYOFMONTH] Bits */ -#define DAYOFMONTH_OFS RTC_C_ADOWDAY_DAY_OFS /*!< DayofMonth Offset */ -#define DAYOFMONTH_M RTC_C_ADOWDAY_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */ -/* RTCADOWDAY[DAYAE] Bits */ -#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */ -#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */ -/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCADOWDAY_BCD[DOWAE] Bits */ -//#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */ -//#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */ -/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */ -//#define DAYLOWDIGIT_OFS RTC_C_ADOWDAY_DAY_LD_OFS /*!< DayLowDigit Offset */ -//#define DAYLOWDIGIT_M RTC_C_ADOWDAY_DAY_LD_MASK /*!< Day of month low digit (0 to 9) */ -/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */ -//#define DAYHIGHDIGIT_OFS RTC_C_ADOWDAY_DAY_HD_OFS /*!< DayHighDigit Offset */ -//#define DAYHIGHDIGIT_M RTC_C_ADOWDAY_DAY_HD_MASK /*!< Day of month high digit (0 to 3) */ -/* RTCADOWDAY_BCD[DAYAE] Bits */ -//#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */ -//#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */ -/* Pre-defined bitfield values */ -#define RTCKEY RTC_C_KEY /*!< RTC_C Key Value for RTC_C write access */ -#define RTCKEY_H RTC_C_KEY_H /*!< RTC_C Key Value for RTC_C write access */ -#define RTCKEY_VAL RTC_C_KEY_VAL /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* TIMER_A Bits (legacy section) -******************************************************************************/ -/* TA0CTL[TAIFG] Bits */ -#define TAIFG_OFS TIMER_A_CTL_IFG_OFS /*!< TAIFG Offset */ -#define TAIFG TIMER_A_CTL_IFG /*!< TimerA interrupt flag */ -/* TA0CTL[TAIE] Bits */ -#define TAIE_OFS TIMER_A_CTL_IE_OFS /*!< TAIE Offset */ -#define TAIE TIMER_A_CTL_IE /*!< TimerA interrupt enable */ -/* TA0CTL[TACLR] Bits */ -#define TACLR_OFS TIMER_A_CTL_CLR_OFS /*!< TACLR Offset */ -#define TACLR TIMER_A_CTL_CLR /*!< TimerA clear */ -/* TA0CTL[MC] Bits */ -#define MC_OFS TIMER_A_CTL_MC_OFS /*!< MC Offset */ -#define MC_M TIMER_A_CTL_MC_MASK /*!< Mode control */ -#define MC0 TIMER_A_CTL_MC0 /*!< MC Bit 0 */ -#define MC1 TIMER_A_CTL_MC1 /*!< MC Bit 1 */ -#define MC_0 TIMER_A_CTL_MC_0 /*!< Stop mode: Timer is halted */ -#define MC_1 TIMER_A_CTL_MC_1 /*!< Up mode: Timer counts up to TAxCCR0 */ -#define MC_2 TIMER_A_CTL_MC_2 /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define MC_3 TIMER_A_CTL_MC_3 /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define MC__STOP TIMER_A_CTL_MC__STOP /*!< Stop mode: Timer is halted */ -#define MC__UP TIMER_A_CTL_MC__UP /*!< Up mode: Timer counts up to TAxCCR0 */ -#define MC__CONTINUOUS TIMER_A_CTL_MC__CONTINUOUS /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define MC__UPDOWN TIMER_A_CTL_MC__UPDOWN /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TA0CTL[ID] Bits */ -#define ID_OFS TIMER_A_CTL_ID_OFS /*!< ID Offset */ -#define ID_M TIMER_A_CTL_ID_MASK /*!< Input divider */ -#define ID0 TIMER_A_CTL_ID0 /*!< ID Bit 0 */ -#define ID1 TIMER_A_CTL_ID1 /*!< ID Bit 1 */ -#define ID_0 TIMER_A_CTL_ID_0 /*!< /1 */ -#define ID_1 TIMER_A_CTL_ID_1 /*!< /2 */ -#define ID_2 TIMER_A_CTL_ID_2 /*!< /4 */ -#define ID_3 TIMER_A_CTL_ID_3 /*!< /8 */ -#define ID__1 TIMER_A_CTL_ID__1 /*!< /1 */ -#define ID__2 TIMER_A_CTL_ID__2 /*!< /2 */ -#define ID__4 TIMER_A_CTL_ID__4 /*!< /4 */ -#define ID__8 TIMER_A_CTL_ID__8 /*!< /8 */ -/* TA0CTL[TASSEL] Bits */ -#define TASSEL_OFS TIMER_A_CTL_SSEL_OFS /*!< TASSEL Offset */ -#define TASSEL_M TIMER_A_CTL_SSEL_MASK /*!< TimerA clock source select */ -#define TASSEL0 TIMER_A_CTL_SSEL0 /*!< TASSEL Bit 0 */ -#define TASSEL1 TIMER_A_CTL_SSEL1 /*!< TASSEL Bit 1 */ -#define TASSEL_0 TIMER_A_CTL_TASSEL_0 /*!< TAxCLK */ -#define TASSEL_1 TIMER_A_CTL_TASSEL_1 /*!< ACLK */ -#define TASSEL_2 TIMER_A_CTL_TASSEL_2 /*!< SMCLK */ -#define TASSEL_3 TIMER_A_CTL_TASSEL_3 /*!< INCLK */ -#define TASSEL__TACLK TIMER_A_CTL_SSEL__TACLK /*!< TAxCLK */ -#define TASSEL__ACLK TIMER_A_CTL_SSEL__ACLK /*!< ACLK */ -#define TASSEL__SMCLK TIMER_A_CTL_SSEL__SMCLK /*!< SMCLK */ -#define TASSEL__INCLK TIMER_A_CTL_SSEL__INCLK /*!< INCLK */ -/* TA0CCTLn[CCIFG] Bits */ -#define CCIFG_OFS TIMER_A_CCTLN_CCIFG_OFS /*!< CCIFG Offset */ -#define CCIFG TIMER_A_CCTLN_CCIFG /*!< Capture/compare interrupt flag */ -/* TA0CCTLn[COV] Bits */ -#define COV_OFS TIMER_A_CCTLN_COV_OFS /*!< COV Offset */ -#define COV TIMER_A_CCTLN_COV /*!< Capture overflow */ -/* TA0CCTLn[OUT] Bits */ -#define OUT_OFS TIMER_A_CCTLN_OUT_OFS /*!< OUT Offset */ -//#define OUT TIMER_A_CCTLN_OUT /*!< Output */ -/* TA0CCTLn[CCI] Bits */ -#define CCI_OFS TIMER_A_CCTLN_CCI_OFS /*!< CCI Offset */ -#define CCI TIMER_A_CCTLN_CCI /*!< Capture/compare input */ -/* TA0CCTLn[CCIE] Bits */ -#define CCIE_OFS TIMER_A_CCTLN_CCIE_OFS /*!< CCIE Offset */ -#define CCIE TIMER_A_CCTLN_CCIE /*!< Capture/compare interrupt enable */ -/* TA0CCTLn[OUTMOD] Bits */ -#define OUTMOD_OFS TIMER_A_CCTLN_OUTMOD_OFS /*!< OUTMOD Offset */ -#define OUTMOD_M TIMER_A_CCTLN_OUTMOD_MASK /*!< Output mode */ -#define OUTMOD0 TIMER_A_CCTLN_OUTMOD0 /*!< OUTMOD Bit 0 */ -#define OUTMOD1 TIMER_A_CCTLN_OUTMOD1 /*!< OUTMOD Bit 1 */ -#define OUTMOD2 TIMER_A_CCTLN_OUTMOD2 /*!< OUTMOD Bit 2 */ -#define OUTMOD_0 TIMER_A_CCTLN_OUTMOD_0 /*!< OUT bit value */ -#define OUTMOD_1 TIMER_A_CCTLN_OUTMOD_1 /*!< Set */ -#define OUTMOD_2 TIMER_A_CCTLN_OUTMOD_2 /*!< Toggle/reset */ -#define OUTMOD_3 TIMER_A_CCTLN_OUTMOD_3 /*!< Set/reset */ -#define OUTMOD_4 TIMER_A_CCTLN_OUTMOD_4 /*!< Toggle */ -#define OUTMOD_5 TIMER_A_CCTLN_OUTMOD_5 /*!< Reset */ -#define OUTMOD_6 TIMER_A_CCTLN_OUTMOD_6 /*!< Toggle/set */ -#define OUTMOD_7 TIMER_A_CCTLN_OUTMOD_7 /*!< Reset/set */ -/* TA0CCTLn[CAP] Bits */ -#define CAP_OFS TIMER_A_CCTLN_CAP_OFS /*!< CAP Offset */ -#define CAP TIMER_A_CCTLN_CAP /*!< Capture mode */ -/* TA0CCTLn[SCCI] Bits */ -#define SCCI_OFS TIMER_A_CCTLN_SCCI_OFS /*!< SCCI Offset */ -#define SCCI TIMER_A_CCTLN_SCCI /*!< Synchronized capture/compare input */ -/* TA0CCTLn[SCS] Bits */ -#define SCS_OFS TIMER_A_CCTLN_SCS_OFS /*!< SCS Offset */ -#define SCS TIMER_A_CCTLN_SCS /*!< Synchronize capture source */ -/* TA0CCTLn[CCIS] Bits */ -#define CCIS_OFS TIMER_A_CCTLN_CCIS_OFS /*!< CCIS Offset */ -#define CCIS_M TIMER_A_CCTLN_CCIS_MASK /*!< Capture/compare input select */ -#define CCIS0 TIMER_A_CCTLN_CCIS0 /*!< CCIS Bit 0 */ -#define CCIS1 TIMER_A_CCTLN_CCIS1 /*!< CCIS Bit 1 */ -#define CCIS_0 TIMER_A_CCTLN_CCIS_0 /*!< CCIxA */ -#define CCIS_1 TIMER_A_CCTLN_CCIS_1 /*!< CCIxB */ -#define CCIS_2 TIMER_A_CCTLN_CCIS_2 /*!< GND */ -#define CCIS_3 TIMER_A_CCTLN_CCIS_3 /*!< VCC */ -#define CCIS__CCIA TIMER_A_CCTLN_CCIS__CCIA /*!< CCIxA */ -#define CCIS__CCIB TIMER_A_CCTLN_CCIS__CCIB /*!< CCIxB */ -#define CCIS__GND TIMER_A_CCTLN_CCIS__GND /*!< GND */ -#define CCIS__VCC TIMER_A_CCTLN_CCIS__VCC /*!< VCC */ -/* TA0CCTLn[CM] Bits */ -#define CM_OFS TIMER_A_CCTLN_CM_OFS /*!< CM Offset */ -#define CM_M TIMER_A_CCTLN_CM_MASK /*!< Capture mode */ -#define CM0 TIMER_A_CCTLN_CM0 /*!< CM Bit 0 */ -#define CM1 TIMER_A_CCTLN_CM1 /*!< CM Bit 1 */ -#define CM_0 TIMER_A_CCTLN_CM_0 /*!< No capture */ -#define CM_1 TIMER_A_CCTLN_CM_1 /*!< Capture on rising edge */ -#define CM_2 TIMER_A_CCTLN_CM_2 /*!< Capture on falling edge */ -#define CM_3 TIMER_A_CCTLN_CM_3 /*!< Capture on both rising and falling edges */ -#define CM__NONE TIMER_A_CCTLN_CM__NONE /*!< No capture */ -#define CM__RISING TIMER_A_CCTLN_CM__RISING /*!< Capture on rising edge */ -#define CM__FALLING TIMER_A_CCTLN_CM__FALLING /*!< Capture on falling edge */ -#define CM__BOTH TIMER_A_CCTLN_CM__BOTH /*!< Capture on both rising and falling edges */ -/* TA0EX0[TAIDEX] Bits */ -#define TAIDEX_OFS TIMER_A_EX0_IDEX_OFS /*!< TAIDEX Offset */ -#define TAIDEX_M TIMER_A_EX0_IDEX_MASK /*!< Input divider expansion */ -#define TAIDEX0 TIMER_A_EX0_IDEX0 /*!< TAIDEX Bit 0 */ -#define TAIDEX1 TIMER_A_EX0_IDEX1 /*!< TAIDEX Bit 1 */ -#define TAIDEX2 TIMER_A_EX0_IDEX2 /*!< TAIDEX Bit 2 */ -#define TAIDEX_0 TIMER_A_EX0_TAIDEX_0 /*!< Divide by 1 */ -#define TAIDEX_1 TIMER_A_EX0_TAIDEX_1 /*!< Divide by 2 */ -#define TAIDEX_2 TIMER_A_EX0_TAIDEX_2 /*!< Divide by 3 */ -#define TAIDEX_3 TIMER_A_EX0_TAIDEX_3 /*!< Divide by 4 */ -#define TAIDEX_4 TIMER_A_EX0_TAIDEX_4 /*!< Divide by 5 */ -#define TAIDEX_5 TIMER_A_EX0_TAIDEX_5 /*!< Divide by 6 */ -#define TAIDEX_6 TIMER_A_EX0_TAIDEX_6 /*!< Divide by 7 */ -#define TAIDEX_7 TIMER_A_EX0_TAIDEX_7 /*!< Divide by 8 */ -#define TAIDEX__1 TIMER_A_EX0_IDEX__1 /*!< Divide by 1 */ -#define TAIDEX__2 TIMER_A_EX0_IDEX__2 /*!< Divide by 2 */ -#define TAIDEX__3 TIMER_A_EX0_IDEX__3 /*!< Divide by 3 */ -#define TAIDEX__4 TIMER_A_EX0_IDEX__4 /*!< Divide by 4 */ -#define TAIDEX__5 TIMER_A_EX0_IDEX__5 /*!< Divide by 5 */ -#define TAIDEX__6 TIMER_A_EX0_IDEX__6 /*!< Divide by 6 */ -#define TAIDEX__7 TIMER_A_EX0_IDEX__7 /*!< Divide by 7 */ -#define TAIDEX__8 TIMER_A_EX0_IDEX__8 /*!< Divide by 8 */ - -/****************************************************************************** -* WDT_A Bits (legacy section) -******************************************************************************/ -/* WDTCTL[WDTIS] Bits */ -#define WDTIS_OFS WDT_A_CTL_IS_OFS /*!< WDTIS Offset */ -#define WDTIS_M WDT_A_CTL_IS_MASK /*!< Watchdog timer interval select */ -#define WDTIS0 WDT_A_CTL_IS0 /*!< WDTIS Bit 0 */ -#define WDTIS1 WDT_A_CTL_IS1 /*!< WDTIS Bit 1 */ -#define WDTIS2 WDT_A_CTL_IS2 /*!< WDTIS Bit 2 */ -#define WDTIS_0 WDT_A_CTL_IS_0 /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDTIS_1 WDT_A_CTL_IS_1 /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDTIS_2 WDT_A_CTL_IS_2 /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDTIS_3 WDT_A_CTL_IS_3 /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDTIS_4 WDT_A_CTL_IS_4 /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDTIS_5 WDT_A_CTL_IS_5 /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDTIS_6 WDT_A_CTL_IS_6 /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDTIS_7 WDT_A_CTL_IS_7 /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDTCTL[WDTCNTCL] Bits */ -#define WDTCNTCL_OFS WDT_A_CTL_CNTCL_OFS /*!< WDTCNTCL Offset */ -#define WDTCNTCL WDT_A_CTL_CNTCL /*!< Watchdog timer counter clear */ -/* WDTCTL[WDTTMSEL] Bits */ -#define WDTTMSEL_OFS WDT_A_CTL_TMSEL_OFS /*!< WDTTMSEL Offset */ -#define WDTTMSEL WDT_A_CTL_TMSEL /*!< Watchdog timer mode select */ -/* WDTCTL[WDTSSEL] Bits */ -#define WDTSSEL_OFS WDT_A_CTL_SSEL_OFS /*!< WDTSSEL Offset */ -#define WDTSSEL_M WDT_A_CTL_SSEL_MASK /*!< Watchdog timer clock source select */ -#define WDTSSEL0 WDT_A_CTL_SSEL0 /*!< WDTSSEL Bit 0 */ -#define WDTSSEL1 WDT_A_CTL_SSEL1 /*!< WDTSSEL Bit 1 */ -#define WDTSSEL_0 WDT_A_CTL_SSEL_0 /*!< SMCLK */ -#define WDTSSEL_1 WDT_A_CTL_SSEL_1 /*!< ACLK */ -#define WDTSSEL_2 WDT_A_CTL_SSEL_2 /*!< VLOCLK */ -#define WDTSSEL_3 WDT_A_CTL_SSEL_3 /*!< BCLK */ -#define WDTSSEL__SMCLK WDT_A_CTL_SSEL__SMCLK /*!< SMCLK */ -#define WDTSSEL__ACLK WDT_A_CTL_SSEL__ACLK /*!< ACLK */ -#define WDTSSEL__VLOCLK WDT_A_CTL_SSEL__VLOCLK /*!< VLOCLK */ -#define WDTSSEL__BCLK WDT_A_CTL_SSEL__BCLK /*!< BCLK */ -/* WDTCTL[WDTHOLD] Bits */ -#define WDTHOLD_OFS WDT_A_CTL_HOLD_OFS /*!< WDTHOLD Offset */ -#define WDTHOLD WDT_A_CTL_HOLD /*!< Watchdog timer hold */ -/* WDTCTL[WDTPW] Bits */ -#define WDTPW_OFS WDT_A_CTL_PW_OFS /*!< WDTPW Offset */ -#define WDTPW_M WDT_A_CTL_PW_MASK /*!< Watchdog timer password */ -/* Pre-defined bitfield values */ -#define WDTPW WDT_A_CTL_PW /*!< WDT Key Value for WDT write access */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P401R_CLASSIC_H__ */ diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp_compatibility.h b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp_compatibility.h deleted file mode 100644 index 549295674ea..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/msp_compatibility.h +++ /dev/null @@ -1,325 +0,0 @@ -//***************************************************************************** -// -// Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// MSP430 intrinsic redefinitions for use with MSP432 Family Devices -// -//**************************************************************************** - -/****************************************************************************** -* Definitions for 8/16/32-bit wide memory access * -******************************************************************************/ -#define HWREG8(x) (*((volatile uint8_t *)(x))) -#define HWREG16(x) (*((volatile uint16_t *)(x))) -#define HWREG32(x) (*((volatile uint32_t *)(x))) -#define HWREG(x) (HWREG16(x)) -#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x))) -#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1))) -#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x))) -#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1))) - -/****************************************************************************** -* Definitions for 8/16/32-bit wide bit band access * -******************************************************************************/ -#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) -#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) -#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) - -// Intrinsics with ARM equivalents -#if defined ( __TI_ARM__ ) /* TI CGT Compiler */ - -#define __sleep() __wfi() -#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } -#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } -#define __get_SP_register() __get_MSP() -#define __set_SP_register(x) __set_MSP(x) -#define __get_interrupt_state() __get_PRIMASK() -#define __set_interrupt_state(x) __set_PRIMASK(x) -#define __enable_interrupt() _enable_IRQ() -#define __enable_interrupts() _enable_IRQ() -#define __disable_interrupt() _disable_IRQ() -#define __disable_interrupts() _disable_IRQ() -#define __no_operation() __asm(" nop") - -#elif defined ( __ICCARM__ ) /* IAR Compiler */ - -#include - -#define __INLINE inline -#define __sleep() __WFI() -#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } -#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } - -#if (__VER__ < 8020002) -#define __get_SP_register() __get_MSP() -#define __set_SP_register() __set_MSP() -#define __get_interrupt_state() __get_PRIMASK() -#define __set_interrupt_state(x) __set_PRIMASK(x) -#define __enable_interrupt() __asm(" cpsie i") -#define __enable_interrupts() __asm(" cpsie i") -#define __disable_interrupt() __asm(" cpsid i") -#define __disable_interrupts() __asm(" cpsid i") -#define __no_operation() __asm(" nop") -#endif - -// Intrinsics without ARM equivalents -#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } - -#elif defined ( __CC_ARM ) /* ARM Compiler */ - -#define __sleep() __wfi() -#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } -#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } -#define __get_SP_register() __get_MSP() -#define __set_SP_register(x) __set_MSP(x) -#define __get_interrupt_state() __get_PRIMASK() -#define __set_interrupt_state(x) __set_PRIMASK(x) -#define __enable_interrupt() __asm(" cpsie i") -#define __enable_interrupts() __asm(" cpsie i") -#define __disable_interrupt() __asm(" cpsid i") -#define __disable_interrupts() __asm(" cpsid i") -#define __no_operation() __asm(" nop") - -// Intrinsics without ARM equivalents -#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } - -#elif defined ( __GNUC__ ) /* GCC Compiler */ -#undef __wfi -// ARM Compiler 6 seems to set __GNUC__ and has own definition of __wfi() ?? -//#define __wfi() __asm(" wfi") -#define __sleep() __wfi() -#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } -#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } -#define __get_SP_register() __get_MSP() -#define __set_SP_register(x) __set_MSP(x) -#define __get_interrupt_state() __get_PRIMASK() -#define __set_interrupt_state(x) __set_PRIMASK(x) -#define __enable_interrupt() __asm(" cpsie i") -#define __enable_interrupts() __asm(" cpsie i") -#define __disable_interrupt() __asm(" cpsid i") -#define __disable_interrupts() __asm(" cpsid i") -#define __no_operation() __asm(" nop") - -// Intrinsics without ARM equivalents -#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } - -#endif - -// Intrinsics without ARM equivalents -#define __low_power_mode_0() { __sleep(); } -#define __low_power_mode_1() { __sleep(); } -#define __low_power_mode_2() { __sleep(); } -#define __low_power_mode_3() { __deep_sleep(); } -#define __low_power_mode_4() { __deep_sleep(); } -#define __data16_read_addr(x) (*((volatile uint32_t *)(x))) -#define __data20_read_char(x) (*((volatile uint8_t *)(x))) -#define __data20_read_short(x) (*((volatile uint16_t *)(x))) -#define __data20_read_long(x) (*((volatile uint32_t *)(x))) -#define __data16_write_addr(x,y) { (*((volatile uint32_t *)(x))) } -#define __get_SR_register() 0 -#define __get_SR_register_on_exit() 0 - -// the following defines are deprecated and will be removed in future releases -#define ATLBASE ALTBASE -#define CS_CTL1_SELM_7 ((uint32_t)0x00000007) /*!< for future use. Defaults to DCOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELS_7 ((uint32_t)0x00000070) /*!< for furture use. Defaults to DCOCLK. Do not use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_3 ((uint32_t)0x00000300) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_4 ((uint32_t)0x00000400) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_5 ((uint32_t)0x00000500) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_6 ((uint32_t)0x00000600) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_7 ((uint32_t)0x00000700) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ - /* CS_CTL2[LFXTAGCOFF] Bits */ -#define CS_CTL2_LFXTAGCOFF_OFS ( 7) /*!< LFXTAGCOFF Bit Offset */ -#define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080) /*!< Disables the automatic gain control of the LFXT crystal */ - -/* CS_CTL3[FCNTHF2] Bits */ -#define CS_CTL3_FCNTHF2_OFS ( 8) /*!< FCNTHF2 Bit Offset */ -#define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300) /*!< FCNTHF2 Bit Mask */ -#define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100) /*!< FCNTHF2 Bit 0 */ -#define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200) /*!< FCNTHF2 Bit 1 */ -#define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300) /*!< 16384 cycles */ -/* CS_CTL3[RFCNTHF2] Bits */ -#define CS_CTL3_RFCNTHF2_OFS (10) /*!< RFCNTHF2 Bit Offset */ -#define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400) /*!< Reset start fault counter for HFXT2 */ -/* CS_CTL3[FCNTHF2_EN] Bits */ -#define CS_CTL3_FCNTHF2_EN_OFS (11) /*!< FCNTHF2_EN Bit Offset */ -#define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800) /*!< Enable start fault counter for HFXT2 */ -/* CS_STAT[HFXT2_ON] Bits */ -#define CS_STAT_HFXT2_ON_OFS ( 3) /*!< HFXT2_ON Bit Offset */ -#define CS_STAT_HFXT2_ON ((uint32_t)0x00000008) /*!< HFXT2 status */ -/* CS_IE[HFXT2IE] Bits */ -#define CS_IE_HFXT2IE_OFS ( 2) /*!< HFXT2IE Bit Offset */ -#define CS_IE_HFXT2IE ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag interrupt enable */ -/* CS_IE[FCNTHF2IE] Bits */ -#define CS_IE_FCNTHF2IE_OFS (10) /*!< FCNTHF2IE Bit Offset */ -#define CS_IE_FCNTHF2IE ((uint32_t)0x00000400) /*!< Start fault counter interrupt enable HFXT2 */ -/* CS_IE[PLLOOLIE] Bits */ -#define CS_IE_PLLOOLIE_OFS (12) /*!< PLLOOLIE Bit Offset */ -#define CS_IE_PLLOOLIE ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt enable */ -/* CS_IE[PLLLOSIE] Bits */ -#define CS_IE_PLLLOSIE_OFS (13) /*!< PLLLOSIE Bit Offset */ -#define CS_IE_PLLLOSIE ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt enable */ -/* CS_IE[PLLOORIE] Bits */ -#define CS_IE_PLLOORIE_OFS (14) /*!< PLLOORIE Bit Offset */ -#define CS_IE_PLLOORIE ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt enable */ -/* CS_IE[CALIE] Bits */ -#define CS_IE_CALIE_OFS (15) /*!< CALIE Bit Offset */ -#define CS_IE_CALIE ((uint32_t)0x00008000) /*!< REFCNT period counter interrupt enable */ -/* CS_IFG[HFXT2IFG] Bits */ -#define CS_IFG_HFXT2IFG_OFS ( 2) /*!< HFXT2IFG Bit Offset */ -#define CS_IFG_HFXT2IFG ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag */ -/* CS_IFG[FCNTHF2IFG] Bits */ -#define CS_IFG_FCNTHF2IFG_OFS (11) /*!< FCNTHF2IFG Bit Offset */ -#define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800) /*!< Start fault counter interrupt flag HFXT2 */ -/* CS_IFG[PLLOOLIFG] Bits */ -#define CS_IFG_PLLOOLIFG_OFS (12) /*!< PLLOOLIFG Bit Offset */ -#define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt flag */ -/* CS_IFG[PLLLOSIFG] Bits */ -#define CS_IFG_PLLLOSIFG_OFS (13) /*!< PLLLOSIFG Bit Offset */ -#define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt flag */ -/* CS_IFG[PLLOORIFG] Bits */ -#define CS_IFG_PLLOORIFG_OFS (14) /*!< PLLOORIFG Bit Offset */ -#define CS_IFG_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt flag */ -/* CS_IFG[CALIFG] Bits */ -#define CS_IFG_CALIFG_OFS (15) /*!< CALIFG Bit Offset */ -#define CS_IFG_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter expired */ -/* CS_CLRIFG[CLR_HFXT2IFG] Bits */ -#define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2) /*!< CLR_HFXT2IFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004) /*!< Clear HFXT2 oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_CALIFG] Bits */ -#define CS_CLRIFG_CLR_CALIFG_OFS (15) /*!< CLR_CALIFG Bit Offset */ -#define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter clear interrupt flag */ -/* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */ -#define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10) /*!< CLR_FCNTHF2IFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter clear interrupt flag HFXT2 */ -/* CS_CLRIFG[CLR_PLLOOLIFG] Bits */ -#define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12) /*!< CLR_PLLOOLIFG Bit Offset */ -#define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock clear interrupt flag */ -/* CS_CLRIFG[CLR_PLLLOSIFG] Bits */ -#define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13) /*!< CLR_PLLLOSIFG Bit Offset */ -#define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal clear interrupt flag */ -/* CS_CLRIFG[CLR_PLLOORIFG] Bits */ -#define CS_CLRIFG_CLR_PLLOORIFG_OFS (14) /*!< CLR_PLLOORIFG Bit Offset */ -#define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range clear interrupt flag */ -/* CS_SETIFG[SET_HFXT2IFG] Bits */ -#define CS_SETIFG_SET_HFXT2IFG_OFS ( 2) /*!< SET_HFXT2IFG Bit Offset */ -#define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004) /*!< Set HFXT2 oscillator fault interrupt flag */ -/* CS_SETIFG[SET_CALIFG] Bits */ -#define CS_SETIFG_SET_CALIFG_OFS (15) /*!< SET_CALIFG Bit Offset */ -#define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter set interrupt flag */ -/* CS_SETIFG[SET_FCNTHF2IFG] Bits */ -#define CS_SETIFG_SET_FCNTHF2IFG_OFS (10) /*!< SET_FCNTHF2IFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter set interrupt flag HFXT2 */ -/* CS_SETIFG[SET_PLLOOLIFG] Bits */ -#define CS_SETIFG_SET_PLLOOLIFG_OFS (12) /*!< SET_PLLOOLIFG Bit Offset */ -#define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock set interrupt flag */ -/* CS_SETIFG[SET_PLLLOSIFG] Bits */ -#define CS_SETIFG_SET_PLLLOSIFG_OFS (13) /*!< SET_PLLLOSIFG Bit Offset */ -#define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal set interrupt flag */ -/* CS_SETIFG[SET_PLLOORIFG] Bits */ -#define CS_SETIFG_SET_PLLOORIFG_OFS (14) /*!< SET_PLLOORIFG Bit Offset */ -#define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range set interrupt flag */ - -/* EUSCI_x_CTLW0[SSEL] Bits */ -#define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */ -#define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */ -#define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ - -/* RSTCTL_PSSRESET_STAT[SVSL] Bits */ -#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /*!< SVSL Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001) /*!< Indicates if POR was caused by an SVSL trip condition in the PSS */ - -/* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */ -#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /*!< DBG_SEC_ACT Bit Offset */ -#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008) /*!< Debug Security active */ -/* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */ -#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /*!< JTAG_SWD_LOCK_ACT Bit Offset */ -#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010) /*!< Indicates if JTAG and SWD Lock is active */ -/* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */ -#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /*!< IP_PROT_ACT Bit Offset */ -#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020) /*!< Indicates if IP protection is active */ - diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/startup_msp432p401r.c b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/startup_msp432p401r.c deleted file mode 100644 index 1ae6f4a6676..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/startup_msp432p401r.c +++ /dev/null @@ -1,339 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "system_msp432p401r.h" -#include "msp.h" -#include - -/*******************************************/ -/* Macro Definitions depending on compiler */ -/*******************************************/ -#if defined(__CC_ARM) - -#define WEAK_FUNC(FUN) \ -void FUN(void) __attribute__ ((weak)); -#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ -void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS))); - -#elif defined(__ICCARM__) - -#pragma diag_suppress=Pe1665 -#define WEAK_FUNC(FUN) void FUN(void); \ -_Pragma(_STRINGIFY(_WEAK_FUNC(FUN))) -#define _WEAK_FUNC(FUN) weak FUN -#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) void FUN(void); \ -_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS))) -#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) -#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS - -#elif defined(__GNUC__) - -#define WEAK_FUNC(FUN) \ -void FUN(void) __attribute__ ((weak)); -#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ -void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS))); - -#endif - -/**********************************************************/ -/* External variables and functions depending on compiler */ -/**********************************************************/ -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -// Entry point for the application. -extern void __main(void); -/* External symbols */ -extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit; -#elif defined(__ICCARM__) -// Entry point for the application. -extern void __iar_program_start(void); -/* External symbols */ -extern uint32_t CSTACK$$Limit; -#elif defined(__GNUC__) -/* Entry point for the application. */ -extern int _start(); -/* External symbols */ -extern uint32_t __data_load__; -extern uint32_t __data_start__; -extern uint32_t __data_end__; -extern uint32_t __StackTop; -#endif - -typedef void(*pFunc)(void); - -// Forward declaration of the EUSCI dispatch handlers. -static void EUSCIA0_IRQHandler(void); -static void EUSCIA1_IRQHandler(void); -static void EUSCIA2_IRQHandler(void); -static void EUSCIA3_IRQHandler(void); -static void EUSCIB0_IRQHandler(void); -static void EUSCIB1_IRQHandler(void); -static void EUSCIB2_IRQHandler(void); -static void EUSCIB3_IRQHandler(void); - -// Forward declaration of the default fault/reset handlers. -WEAK_FUNC(Default_Handler) -WEAK_FUNC(Reset_Handler) - -// Cortex-M4 Processor Exceptions -WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler) -WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler) -WEAK_ALIAS_FUNC(MemManage_Handler, Default_Handler) -WEAK_ALIAS_FUNC(BusFault_Handler, Default_Handler) -WEAK_ALIAS_FUNC(UsageFault_Handler, Default_Handler) -WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler) -WEAK_ALIAS_FUNC(DebugMon_Handler, Default_Handler) -WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler) -WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler) - -// Device specific interrupt handler -WEAK_ALIAS_FUNC(PSS_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(CS_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(PCM_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(WDT_A_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(FPU_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(FLCTL_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(COMP_E0_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(COMP_E1_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(TA0_0_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(TA0_N_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(TA1_0_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(TA1_N_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(TA2_0_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(TA2_N_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(TA3_0_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(TA3_N_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(ADC14_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(T32_INT1_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(T32_INT2_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(T32_INTC_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(AES256_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(RTC_C_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(DMA_ERR_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(DMA_INT3_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(DMA_INT2_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(DMA_INT1_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(DMA_INT0_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(PORT1_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(PORT2_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(PORT3_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(PORT4_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(PORT5_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(PORT6_IRQHandler, Default_Handler) - -// EUSCI specific interrupt handlers -WEAK_ALIAS_FUNC(EUSCIA0_UART_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIA1_UART_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIA2_UART_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIA3_UART_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIB0_I2C_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIB1_I2C_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIB2_I2C_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIB3_I2C_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIA0_SPI_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIA1_SPI_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIA2_SPI_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIA3_SPI_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIB0_SPI_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIB1_SPI_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIB2_SPI_IRQHandler, Default_Handler) -WEAK_ALIAS_FUNC(EUSCIB3_SPI_IRQHandler, Default_Handler) - -// Interrupt vector table. Note that the proper constructs must be placed on this -// to ensure that it ends up at physical address 0x0000.0000 or at the start of the -// program if located at a start address other than 0. -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -void (* const interruptVectors[])(void) __attribute__((section("RESET"), used)) = { - (pFunc) &Image$$ARM_LIB_STACK$$ZI$$Limit, // The initial stack pointer -#elif defined(__ICCARM__) -void (* const __vector_table[])(void) @ ".intvec" = { - (pFunc) &CSTACK$$Limit, // The initial stack pointer -#elif defined(__GNUC__) -void (* const interruptVectors[])(void) __attribute__((section(".isr_vector"))) = { - (pFunc) &__StackTop, // The initial stack pointer -#endif - Reset_Handler, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - MemManage_Handler, // The MPU fault handler - BusFault_Handler, // The bus fault handler - UsageFault_Handler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall handler - DebugMon_Handler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - PSS_IRQHandler, // PSS Interrupt - CS_IRQHandler, // CS Interrupt - PCM_IRQHandler, // PCM Interrupt - WDT_A_IRQHandler, // WDT_A Interrupt - FPU_IRQHandler, // FPU Interrupt - FLCTL_IRQHandler, // Flash Controller Interrupt - COMP_E0_IRQHandler, // COMP_E0 Interrupt - COMP_E1_IRQHandler, // COMP_E1 Interrupt - TA0_0_IRQHandler, // TA0_0 Interrupt - TA0_N_IRQHandler, // TA0_N Interrupt - TA1_0_IRQHandler, // TA1_0 Interrupt - TA1_N_IRQHandler, // TA1_N Interrupt - TA2_0_IRQHandler, // TA2_0 Interrupt - TA2_N_IRQHandler, // TA2_N Interrupt - TA3_0_IRQHandler, // TA3_0 Interrupt - TA3_N_IRQHandler, // TA3_N Interrupt - EUSCIA0_IRQHandler, // EUSCIA0 Interrupt - EUSCIA1_IRQHandler, // EUSCIA1 Interrupt - EUSCIA2_IRQHandler, // EUSCIA2 Interrupt - EUSCIA3_IRQHandler, // EUSCIA3 Interrupt - EUSCIB0_IRQHandler, // EUSCIB0 Interrupt - EUSCIB1_IRQHandler, // EUSCIB1 Interrupt - EUSCIB2_IRQHandler, // EUSCIB2 Interrupt - EUSCIB3_IRQHandler, // EUSCIB3 Interrupt - ADC14_IRQHandler, // ADC14 Interrupt - T32_INT1_IRQHandler, // T32_INT1 Interrupt - T32_INT2_IRQHandler, // T32_INT2 Interrupt - T32_INTC_IRQHandler, // T32_INTC Interrupt - AES256_IRQHandler, // AES256 Interrupt - RTC_C_IRQHandler, // RTC_C Interrupt - DMA_ERR_IRQHandler, // DMA_ERR Interrupt - DMA_INT3_IRQHandler, // DMA_INT3 Interrupt - DMA_INT2_IRQHandler, // DMA_INT2 Interrupt - DMA_INT1_IRQHandler, // DMA_INT1 Interrupt - DMA_INT0_IRQHandler, // DMA_INT0 Interrupt - PORT1_IRQHandler, // Port1 Interrupt - PORT2_IRQHandler, // Port2 Interrupt - PORT3_IRQHandler, // Port3 Interrupt - PORT4_IRQHandler, // Port4 Interrupt - PORT5_IRQHandler, // Port5 Interrupt - PORT6_IRQHandler // Port6 Interrupt -}; - -// The reset irq handler -void Reset_Handler(void) -{ - // Halt the WDT already here, because the following copy process - // from flash to SRAM (in case of GCC) might take so long that the - // WDT kicks in - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - // Call system initialization routine - SystemInit(); - // Jump to the main initialization routine. - __main(); -#elif defined(__ICCARM__) - // Call system initialization routine - SystemInit(); - // Jump to the main initialization routine. - __iar_program_start(); -#elif defined(__GNUC__) - uint32_t *pui32Src, *pui32Dest; - // Copy the data segment initializers from flash to SRAM. - pui32Src = &__data_load__; - for (pui32Dest = &__data_start__; pui32Dest < &__data_end__;) { - *pui32Dest++ = *pui32Src++; - } - // Call system initialization routine - SystemInit(); - // Jump to the main initialization routine. - _start(); -#endif -} - -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -void Default_Handler(void) -{ - // Enter an infinite loop. - while (1) { } -} - -// EUSCI interrupt dispatch handlers. These handlers will look at the current -// EUSCI mode (SPI, UART, I2C), and forward the call to the specific handlers. -void EUSCIA0_IRQHandler(void) -{ - if (EUSCI_A0->CTLW0 & EUSCI_A_CTLW0_SYNC) { - EUSCIA0_SPI_IRQHandler(); - } else { - EUSCIA0_UART_IRQHandler(); - } -} - -void EUSCIA1_IRQHandler(void) -{ - if (EUSCI_A1->CTLW0 & EUSCI_A_CTLW0_SYNC) { - EUSCIA1_SPI_IRQHandler(); - } else { - EUSCIA1_UART_IRQHandler(); - } -} - -void EUSCIA2_IRQHandler(void) -{ - if (EUSCI_A2->CTLW0 & EUSCI_A_CTLW0_SYNC) { - EUSCIA2_SPI_IRQHandler(); - } else { - EUSCIA2_UART_IRQHandler(); - } -} - -void EUSCIA3_IRQHandler(void) -{ - if (EUSCI_A3->CTLW0 & EUSCI_A_CTLW0_SYNC) { - EUSCIA3_SPI_IRQHandler(); - } else { - EUSCIA3_UART_IRQHandler(); - } -} - -void EUSCIB0_IRQHandler(void) -{ - if ((EUSCI_B0->CTLW0 & EUSCI_A_CTLW0_MODE_MASK) == EUSCI_A_CTLW0_MODE_3) { - EUSCIB0_I2C_IRQHandler(); - } else { - EUSCIB0_SPI_IRQHandler(); - } -} - -void EUSCIB1_IRQHandler(void) -{ - if ((EUSCI_B1->CTLW0 & EUSCI_A_CTLW0_MODE_MASK) == EUSCI_A_CTLW0_MODE_3) { - EUSCIB1_I2C_IRQHandler(); - } else { - EUSCIB1_SPI_IRQHandler(); - } -} - -void EUSCIB2_IRQHandler(void) -{ - if ((EUSCI_B2->CTLW0 & EUSCI_A_CTLW0_MODE_MASK) == EUSCI_A_CTLW0_MODE_3) { - EUSCIB2_I2C_IRQHandler(); - } else { - EUSCIB2_SPI_IRQHandler(); - } -} - -void EUSCIB3_IRQHandler(void) -{ - if ((EUSCI_B3->CTLW0 & EUSCI_A_CTLW0_MODE_MASK) == EUSCI_A_CTLW0_MODE_3) { - EUSCIB3_I2C_IRQHandler(); - } else { - EUSCIB3_SPI_IRQHandler(); - } -} diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/system_msp432p401r.c b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/system_msp432p401r.c deleted file mode 100644 index dcdda4aee96..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/system_msp432p401r.c +++ /dev/null @@ -1,459 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//////////////////////////////////// -// System startup code for MSP432 // -//////////////////////////////////// - -#include -#include "msp.h" - -// Internal clock frequencies, used for SystemCoreClockUpdate() -#define __VLOCLK 9400 -#define __MODCLK 25000000 -#define __REFOCLK_L 32768 -#define __REFOCLK_H 128000 -#define __SYSCLK 5000000 - -// Configuration items in targets.json -#define DCO_1500kHz 0 -#define DCO_3MHz 1 -#define DCO_6MHz 2 -#define DCO_12MHz 3 -#define DCO_24MHz 4 -#define DCO_48MHz 5 - -#define LFXT 0 -#define VLO 1 -#define REFO 2 -#define DCO 3 -#define MOD 4 -#define HFXT 5 - -#define DIV1 0 -#define DIV2 1 -#define DIV4 2 -#define DIV8 3 -#define DIV16 4 -#define DIV32 5 -#define DIV64 6 -#define DIV128 7 - -// Sanity check for HFXT and LFXT -#if ((MBED_CONF_TARGET_MCLK_SELECT == HFXT) || (MBED_CONF_TARGET_SMCLK_SELECT == HFXT)) -#ifndef MBED_CONF_TARGET_HFXT_HZ -#error No HFXT frequency specified (MBED_CONF_TARGET_HFXT_HZ) -#endif -#endif - -#if ((MBED_CONF_TARGET_MCLK_SELECT == LFXT) || (MBED_CONF_TARGET_SMCLK_SELECT == LFXT)) -#ifndef MBED_CONF_TARGET_LFXT_HZ -#error No LFXT frequency specified (MBED_CONF_TARGET_LFXT_HZ) -#endif -#endif - -// Calculate HFXTFREQ bits (for CSCTL2) -#if (MBED_CONF_TARGET_HFXT_HZ > 40000000) -#define HFXT_FREQ CS_CTL2_HFXTFREQ_6 | CS_CTL2_HFXTDRIVE -#elif (MBED_CONF_TARGET_HFXT_HZ > 32000000) -#define HFXT_FREQ CS_CTL2_HFXTFREQ_5 | CS_CTL2_HFXTDRIVE -#elif (MBED_CONF_TARGET_HFXT_HZ > 2400000) -#define HFXT_FREQ CS_CTL2_HFXTFREQ_4 | CS_CTL2_HFXTDRIVE -#elif (MBED_CONF_TARGET_HFXT_HZ > 16000000) -#define HFXT_FREQ CS_CTL2_HFXTFREQ_3 | CS_CTL2_HFXTDRIVE -#elif (MBED_CONF_TARGET_HFXT_HZ > 8000000) -#define HFXT_FREQ CS_CTL2_HFXTFREQ_2 | CS_CTL2_HFXTDRIVE -#elif (MBED_CONF_TARGET_HFXT_HZ > 4000000) -#define HFXT_FREQ CS_CTL2_HFXTFREQ_1 | CS_CTL2_HFXTDRIVE -#else -#define HFXT_FREQ CS_CTL2_HFXTFREQ_0 -#endif - -#define MCLK_DIVIDER (1 << MBED_CONF_TARGET_MCLK_DIV) -#define SMCLK_DIVIDER (1 << MBED_CONF_TARGET_SMCLK_DIV) - -// Evaluate the MCLK setting -#if (MBED_CONF_TARGET_MCLK_SELECT == LFXT) -#define __MASTER_CLOCK (MBED_CONF_TARGET_LFXT_HZ / MCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == VLO) -#define __MASTER_CLOCK (__VLOCLK / MCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == REFO) -#define __MASTER_CLOCK (__REFOCLK_L / MCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == DCO) -#define __MASTER_CLOCK ( (1500000 << MBED_CONF_TARGET_DCO_RSEL) / MCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == MOD) -#define __MASTER_CLOCK (__MODCLK / MCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == HFXT) -#define __MASTER_CLOCK (MBED_CONF_TARGET_HFXT_HZ / MCLK_DIVIDER) -#else -#error No MCLK source defined (MBED_CONF_TARGET_MCLK_SELECT) -#endif - -// Evaluate the SMCLK setting -#if (MBED_CONF_TARGET_MCLK_SELECT == LFXT) -#define __SUBSYS_CLOCK (MBED_CONF_TARGET_LFXT_HZ / SMCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == VLO) -#define __SUBSYS_CLOCK (__VLOCLK / SMCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == REFO) -#define __SUBSYS_CLOCK (__REFOCLK_L / SMCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == DCO) -#define __SUBSYS_CLOCK ((1500000 << MBED_CONF_TARGET_DCO_RSEL) / SMCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == MOD) -#define __SUBSYS_CLOCK (__MODCLK / SMCLK_DIVIDER) -#elif (MBED_CONF_TARGET_MCLK_SELECT == HFXT) -#define __SUBSYS_CLOCK (MBED_CONF_TARGET_HFXT_HZ / SMCLK_DIVIDER) -#else -#error No SMCLK source defined (MBED_CONF_TARGET_SMCLK_SELECT) -#endif - -// Global clock variables -uint32_t SystemCoreClock = __MASTER_CLOCK; // the value of MCLK in Hz -uint32_t SubsystemMasterClock = __SUBSYS_CLOCK; // the value of SMCLK in Hz - -// Global xtal frequencies. If the xtal oscillators are enabled -// during run-time, the frequencies have to be set here so that -// SystemCoreClockUpdate can use them. -uint32_t HfxtFrequency = 0; -uint32_t LfxtFrequency = 0; - -// -// Initialize the system -// -// @param none -// @return none -// -// @brief Setup the microcontroller system. -// -// Performs the following initialization steps: -// 1. Enables the FPU -// 2. Enables all SRAM banks -// 3. Sets up power regulator and VCORE -// 4. Enable Flash wait states if needed and read buffering -// 5. Enable HFXT and/or LFXT if needed -// 6. Configure the Clock System (CS) -// -void SystemInit(void) -{ - // Enable FPU (CP10 full access, CP11 full access) - SCB->CPACR |= (SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK); - // Enable all SRAM banks - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; - -#if (__MASTER_CLOCK >= 48000000) - // Switches to DCDC VCORE1 - while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR__AM_DCDC_VCORE1; - while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - // 1 flash wait states (BANK0 VCORE1 max is 16 MHz, - // BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL = FLCTL_BANK0_RDCTL_WAIT_1 | FLCTL_BANK0_RDCTL_BUFD - | FLCTL_BANK0_RDCTL_BUFI; - FLCTL->BANK1_RDCTL = FLCTL_BANK1_RDCTL_WAIT_1 | FLCTL_BANK1_RDCTL_BUFD - | FLCTL_BANK1_RDCTL_BUFI; -#elif (__MASTER_CLOCK >= 24000000) - // Switches to DCDC VCORE0 - while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR__AM_DCDC_VCORE0; - while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - // Enable read buffering and 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL = FLCTL_BANK0_RDCTL_WAIT_1 | FLCTL_BANK0_RDCTL_BUFD - | FLCTL_BANK0_RDCTL_BUFI; -#endif - - // Unlock CS module - CS->KEY = CS_KEY_VAL; - -#ifdef MBED_CONF_TARGET_HFXT_HZ - HfxtFrequency = MBED_CONF_TARGET_HFXT_HZ; - // Enable the HFXT crystal oscillator. - // Initialize PJ for HFXT - PJ->SEL0 |= BIT3; - PJ->SEL1 &= ~BIT3; - CS->CTL2 |= CS_CTL2_HFXT_EN | HFXT_FREQ; - // Wait for the HFXT to stabilize - while (CS->IFG & CS_IFG_HFXTIFG) { - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - } -#endif - -#ifdef MBED_CONF_TARGET_LFXT_HZ - LfxtFrequency = MBED_CONF_TARGET_LFXT_HZ; - // Enable the LFXT crystal oscillator. If the LFXT is not - // available, the system will switch automatically to - // REFOCLK with 32768Hz mode (less precision...). - // Initialize PJ for LFXT - PJ->SEL0 |= BIT0; - PJ->SEL1 &= ~BIT0; - // Enable LFXT - CS->CTL2 |= CS_CTL2_LFXT_EN; // Enable LFXT - // Wait for the XTAL to stabilize - while (CS->IFG & CS_IFG_LFXTIFG) { - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - } -#endif - - // Set CTL0 and CTL1 - CS->CTL0 =(MBED_CONF_TARGET_DCO_RSEL << CS_CTL0_DCORSEL_OFS) | - (MBED_CONF_TARGET_DCO_TUNE & 0x3ff); - CS->CTL1 = MBED_CONF_TARGET_MCLK_SELECT << CS_CTL1_SELM_OFS | - MBED_CONF_TARGET_MCLK_DIV << CS_CTL1_DIVM_OFS | - MBED_CONF_TARGET_SMCLK_SELECT << CS_CTL1_SELS_OFS | - MBED_CONF_TARGET_SMCLK_DIV << CS_CTL1_DIVS_OFS; - - // Lock CS module - CS->KEY = 0; - - // Update the global clock values. - SystemCoreClockUpdate(); -} - - -// -// Update SystemCoreClock and SubsystemMasterClock variables -// -// @param none -// @return none -// -// @brief Updates the SystemCoreClock with current core Clock -// retrieved from cpu registers. Also SubsystemMasterClock -// is updated, assuming that SMCLK has the same clock source -// as MCLK. -// -void SystemCoreClockUpdate(void) -{ - // Check which source is selected for MCLK - switch (CS->CTL1 & CS_CTL1_SELM_MASK) { - ////////////////////////// - case CS_CTL1_SELM__LFXTCLK: { - ////////////////////////// - // Clear pending LFXT fault condition (irq flag) - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 0; - // Check if we still have a LFXT fault - if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) { - // According to the TRM, a LFXT fault will - // always switch to REFOCLK with 32768Hz - SystemCoreClock = __REFOCLK_L; - } else { - SystemCoreClock = LfxtFrequency; - } - break; - } - ///////////////////////// - case CS_CTL1_SELM__VLOCLK: { - ///////////////////////// - SystemCoreClock = __VLOCLK; - break; - } - ////////////////////////// - case CS_CTL1_SELM__REFOCLK: { - ////////////////////////// - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) { - SystemCoreClock = __REFOCLK_H; - } else { - SystemCoreClock = __REFOCLK_L; - } - break; - } - ///////////////////////// - case CS_CTL1_SELM__DCOCLK: { - ///////////////////////// - // Set the center frequency - SystemCoreClock = 1500000 << ((CS->CTL0 & CS_CTL0_DCORSEL_MASK) - >> CS_CTL0_DCORSEL_OFS); - // Get DCO tune value - int16_t __DCOTUNE = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) - >> CS_CTL0_DCOTUNE_OFS; - // Check if we have a nonzero tune value - if (__DCOTUNE) { - // Convert 10 bits signed int to 16 bits signed int - if (__DCOTUNE & 0x200) { - __DCOTUNE |= 0xFC00; - } - // Get calibration data - float __DCO_CONSTK; - uint32_t __DCO_FCAL; - if (CS->CTL0 & CS_CTL0_DCORES) { - // external resistor - if ((CS->CTL0 & CS_CTL0_DCORSEL_MASK) == CS_CTL0_DCORSEL_5) { - // DCORSEL is 5 - __DCO_CONSTK = TLV->DCOER_CONSTK_RSEL5; - __DCO_FCAL = TLV->DCOER_FCAL_RSEL5; - } else { - // DCORSEL is 0..4 - __DCO_CONSTK = TLV->DCOER_CONSTK_RSEL04; - __DCO_FCAL = TLV->DCOER_FCAL_RSEL04; - } - } else { - // internal resistor - if ((CS->CTL0 & CS_CTL0_DCORSEL_MASK) == CS_CTL0_DCORSEL_5) { - // DCORSEL is 5 - __DCO_CONSTK = TLV->DCOIR_CONSTK_RSEL5; - __DCO_FCAL = TLV->DCOIR_FCAL_RSEL5; - } else { - // DCORSEL is 0..4 - __DCO_CONSTK = TLV->DCOIR_CONSTK_RSEL04; - __DCO_FCAL = TLV->DCOIR_FCAL_RSEL04; - } - } - // Calculate tuned frequency - float denom = 1.0f / __DCO_CONSTK + 768 - (float)__DCO_FCAL; - SystemCoreClock = (float)SystemCoreClock / (1.0f - (float)__DCOTUNE / denom); - } - break; - } - ///////////////////////// - case CS_CTL1_SELM__MODOSC: { - ///////////////////////// - SystemCoreClock = __MODCLK; - break; - } - ////////////////////////// - case CS_CTL1_SELM__HFXTCLK: { - ////////////////////////// - // Clear pending HFXT fault condition (irq flag) - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 0; - // Check if we still have a HFXT fault - if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) { - // According to the TRM, a HFXT fault will - // switch over to SYSOSC... - SystemCoreClock = __SYSCLK; - } else { - SystemCoreClock = HfxtFrequency; - } - break; - } - } - // Check which source is selected for SMCLK - switch (CS->CTL1 & CS_CTL1_SELS_MASK) { - ////////////////////////// - case CS_CTL1_SELS__LFXTCLK: { - ////////////////////////// - // Clear pending LFXT fault condition (irq flag) - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 0; - // Check if we still have a LFXT fault - if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) { - // According to the TRM, a LFXT fault will - // always switch to REFOCLK with 32768Hz - SubsystemMasterClock = __REFOCLK_L; - } else { - SubsystemMasterClock = LfxtFrequency; - } - break; - } - ///////////////////////// - case CS_CTL1_SELS__VLOCLK: { - ///////////////////////// - SubsystemMasterClock = __VLOCLK; - break; - } - ////////////////////////// - case CS_CTL1_SELS__REFOCLK: { - ////////////////////////// - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) { - SubsystemMasterClock = __REFOCLK_H; - } else { - SubsystemMasterClock = __REFOCLK_L; - } - break; - } - ///////////////////////// - case CS_CTL1_SELS__DCOCLK: { - ///////////////////////// - // Set the center frequency - SubsystemMasterClock = 1500000 << ((CS->CTL0 & CS_CTL0_DCORSEL_MASK) - >> CS_CTL0_DCORSEL_OFS); - // Get DCO tune value - int16_t __DCOTUNE = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) - >> CS_CTL0_DCOTUNE_OFS; - // Check if we have a nonzero tune value - if (__DCOTUNE) { - // Convert 10 bits signed int to 16 bits signed int - if (__DCOTUNE & 0x200) { - __DCOTUNE |= 0xFC00; - } - // Get calibration data - float __DCO_CONSTK; - uint32_t __DCO_FCAL; - if (CS->CTL0 & CS_CTL0_DCORES) { - // external resistor - if ((CS->CTL0 & CS_CTL0_DCORSEL_MASK) == CS_CTL0_DCORSEL_5) { - // DCORSEL is 5 - __DCO_CONSTK = TLV->DCOER_CONSTK_RSEL5; - __DCO_FCAL = TLV->DCOER_FCAL_RSEL5; - } else { - // DCORSEL is 0..4 - __DCO_CONSTK = TLV->DCOER_CONSTK_RSEL04; - __DCO_FCAL = TLV->DCOER_FCAL_RSEL04; - } - } else { - // internal resistor - if ((CS->CTL0 & CS_CTL0_DCORSEL_MASK) == CS_CTL0_DCORSEL_5) { - // DCORSEL is 5 - __DCO_CONSTK = TLV->DCOIR_CONSTK_RSEL5; - __DCO_FCAL = TLV->DCOIR_FCAL_RSEL5; - } else { - // DCORSEL is 0..4 - __DCO_CONSTK = TLV->DCOIR_CONSTK_RSEL04; - __DCO_FCAL = TLV->DCOIR_FCAL_RSEL04; - } - } - // Calculate tuned frequency - float denom = 1.0f / __DCO_CONSTK + 768 - (float)__DCO_FCAL; - SubsystemMasterClock = (float)SubsystemMasterClock / (1.0f - (float)__DCOTUNE / denom); - } - break; - } - ///////////////////////// - case CS_CTL1_SELS__MODOSC: { - ///////////////////////// - SubsystemMasterClock = __MODCLK; - break; - } - ////////////////////////// - case CS_CTL1_SELS__HFXTCLK: { - ////////////////////////// - // Clear pending HFXT fault condition (irq flag) - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 0; - // Check if we still have a HFXT fault - if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) { - // According to the TRM, a HFXT fault will - // switch over to SYSOSC... - SubsystemMasterClock = __SYSCLK; - } else { - SubsystemMasterClock = HfxtFrequency; - } - break; - } - } - - // Get the MCLK and SMCLK dividers - int32_t __DIVM = 1 << ((CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS); - int32_t __DIVS = 1 << ((CS->CTL1 & CS_CTL1_DIVS_MASK) >> CS_CTL1_DIVS_OFS); - - // Update SystemCoreClock (MCLK) with divider value - SystemCoreClock /= __DIVM; - // Update SubsystemMasterClock (SMCLK) with divider value - SubsystemMasterClock /= __DIVS; -} diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/system_msp432p401r.h b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/system_msp432p401r.h deleted file mode 100644 index 43c7f09bfc8..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/system_msp432p401r.h +++ /dev/null @@ -1,39 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SYSTEM_MSP432P401R_H -#define SYSTEM_MSP432P401R_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -// global clock variables -extern uint32_t SystemCoreClock; // MCLK in Hz -extern uint32_t SubsystemMasterClock; // SMCLK in Hz - -// CMSIS standard methods for system init and master clock update -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif // SYSTEM_MSP432P401R_H diff --git a/targets/TARGET_TI/TARGET_MSP432/analogin_api.c b/targets/TARGET_TI/TARGET_MSP432/analogin_api.c deleted file mode 100644 index 4eea941c632..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/analogin_api.c +++ /dev/null @@ -1,152 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Low-level implementation of ADC functionality for MSP432. The ADC - is very precise and has a resolution of 14 bits. In the default mode, - a ADC conversion is triggered when read() or read_u16() is called. - The program will then wait until the conversion result is available. - - Alternatively, MBED_CONF_TARGET_ADC_AUTO_SCAN can be set, which will - instruct the ADC to scan and convert all configured ADC channels - automatically (so the ADC is active all the time). The two read-functions - will then only read the result register, which will contain the latest - available conversion result. In this case the program will not have to - wait for the conversion result and the read-functions are faster! - */ - -#if DEVICE_ANALOGIN - -#include "analogin_api.h" -#include "mbed_assert.h" -#include - -static uint8_t next_mem_index = 0; - -/** Initialize the analogin peripheral - * - * Configures the pin used by analogin. - * @param obj The analogin object to initialize - * @param pin The analogin pin name - */ -void analogin_init(analogin_t *obj, PinName pin) -{ - /* Check if pin supports ADC function */ - MBED_ASSERT(pinmap_peripheral(pin, PinMap_ADC) == ADC14_BASE); - /* Check if we have used this pin already */ - uint8_t channel = GET_DATA_CHAN(pinmap_function(pin, PinMap_ADC)); - uint8_t index; - for (index = 0; index < next_mem_index; ++index) { - if ((ADC14->MCTL[index] & ADC14_MCTLN_INCH_MASK) == channel) { - /* Pin was used before. Set mem register index and return */ - obj->mem_index = index; - return; - } - } - /* Configure the GPIO pin */ - pinmap_pinout(pin, PinMap_ADC); - /* Fill the obj structure */ - obj->mem_index = next_mem_index++; - /* Reset ENC bit so the ADC can be configured */ - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 0; - /* Set up result buffer */ - ADC14->MCTL[obj->mem_index] = channel; - ADC14->MCTL[obj->mem_index] |= ADC14_MCTLN_VRSEL_0; -#ifdef MBED_CONF_TARGET_ADC_AUTO_SCAN - ADC14->MCTL[obj->mem_index] |= ADC14_MCTLN_EOS; - // Clear the former End-Of-Sequence bit - if (obj->mem_index) { - ADC14->MCTL[obj->mem_index - 1] &= ~ADC14_MCTLN_EOS; - } -#endif - /* Set up the control registers of ADC14 */ - ADC14->CTL1 = ADC14_CTL1_RES__14BIT | // 14 bit resolution - ADC14_CTL1_PWRMD_0; // normal power mode - ADC14->CTL0 = ADC14_CTL0_SSEL__MODCLK | // Use MODCLK (25MHz) - ADC14_CTL0_PDIV__1 | // clock pre-divider is 1 - ADC14_CTL0_DIV__1 | // clock divider 1 - ADC14_CTL0_SHS_0 | // use ADCSC bit as sample/hold trigger - ADC14_CTL0_SHP | // use sample/hold counter - ADC14_CTL0_SHT1__16 | // 16 cycles for sample/hold - ADC14_CTL0_SHT0__16 | // 16 cycles for sample/hold -#ifdef MBED_CONF_TARGET_ADC_AUTO_SCAN - ADC14_CTL0_CONSEQ_3 | // Repeat sequence of channels - ADC14_CTL0_MSC | // Multiple samples and conversion - ADC14_CTL0_ENC | // Enable conversion - ADC14_CTL0_SC | // Start conversion -#else - ADC14_CTL0_CONSEQ_0 | // Single channel, single conversion -#endif - ADC14_CTL0_ON; // switch on ADC module - /* Disable interrupts */ - ADC14->IER0 = 0; - ADC14->IER1 = 0; -} - -/* Read a 14-bit ADC result from a single channel */ -uint16_t adc_read_raw(uint8_t mem_index) -{ -#ifndef MBED_CONF_TARGET_ADC_AUTO_SCAN - /* Reset ENC bit so the ADC can be configured */ - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 0; - // set up start channel - ADC14->CTL1 &= ~ADC14_CTL1_CSTARTADD_MASK; - ADC14->CTL1 |= (mem_index << ADC14_CTL1_CSTARTADD_OFS); - // start the conversion process - ADC14->CTL0 |= ADC14_CTL0_SC | ADC14_CTL0_ENC; - // wait until active conversion is done - while (BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS)); -#endif - return ADC14->MEM[mem_index]; -} - -/** Read the input voltage, represented as a float in the range [0.0, 1.0] - * - * @param obj The analogin object - * @return A floating value representing the current input voltage - */ -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read_raw(obj->mem_index); - return (float)value * (1.0f / (float)0x3FFF); -} - -/** Read the value from analogin pin, represented as an unsigned 16bit value - * - * @param obj The analogin object - * @return An unsigned 16bit value representing the current input voltage - */ -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read_raw(obj->mem_index); - // 14-bit to 16-bit conversion - value = (value << 2) | (value >> 12); - return value; -} - -/** Get the pins that support analogin - * - * Return a PinMap array of pins that support analogin. The - * array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *analogin_pinmap(void) -{ - return PinMap_ADC; -} - -#endif /* DEVICE_ANALOG_IN */ diff --git a/targets/TARGET_TI/TARGET_MSP432/device.h b/targets/TARGET_TI/TARGET_MSP432/device.h deleted file mode 100644 index b2e97c8e7fe..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/device.h +++ /dev/null @@ -1,25 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -// Defines for compile-time optimization of us_ticker code. -#define US_TICKER_PERIOD_NUM 1 -#define US_TICKER_PERIOD_DEN 1 -#define US_TICKER_MASK 0xffff - -#include "objects.h" -#include "PeripheralPins.h" - diff --git a/targets/TARGET_TI/TARGET_MSP432/device/cmsis.h b/targets/TARGET_TI/TARGET_MSP432/device/cmsis.h deleted file mode 100644 index f21691ff356..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/device/cmsis.h +++ /dev/null @@ -1,27 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#undef DIR_H - -#include "msp.h" - -#undef CS - -#endif diff --git a/targets/TARGET_TI/TARGET_MSP432/device/msp.h b/targets/TARGET_TI/TARGET_MSP432/device/msp.h deleted file mode 100644 index f06ebd9c8bb..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/device/msp.h +++ /dev/null @@ -1,83 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432 Family Generic Include File -* -* File creation date: 12/06/17 -* -******************************************************************************/ - -#ifndef __MSP432_H__ -#define __MSP432_H__ - -/****************************************************************************** -* MSP432 devices * -******************************************************************************/ -#if defined (__MSP432P401R__) -#include "msp432p401r.h" - -#elif defined (__MSP432P401M__) -#include "msp432p401m.h" - -#elif defined (__MSP432P401Y__) -#include "msp432p401y.h" - -#elif defined (__MSP432P401V__) -#include "msp432p401v.h" - -#elif defined (__MSP432P411V__) -#include "msp432p411v.h" - -#elif defined (__MSP432P4011__) -#include "msp432p4011.h" - -#elif defined (__MSP432P4111__) -#include "msp432p4111.h" - -#elif defined (__MSP432P411Y__) -#include "msp432p411y.h" - -#elif defined (__MSP432E411Y__) -#include "msp432e411y.h" - -#elif defined (__MSP432E401Y__) -#include "msp432e401y.h" - -/****************************************************************************** -* Failed to match a default include file * -******************************************************************************/ -#else -#error "Failed to match a default include file" -#endif - -#endif /* __MSP432_H__ */ - diff --git a/targets/TARGET_TI/TARGET_MSP432/gpio_api.c b/targets/TARGET_TI/TARGET_MSP432/gpio_api.c deleted file mode 100644 index dc4c371aa36..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/gpio_api.c +++ /dev/null @@ -1,156 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Low-level implementation of gpio functionality for MSP432. - * This implementation uses bit-banding, so no masking of bits - * is necessary during simple get/set operations for a single pin. - */ - -#include -#include "gpio_api.h" -#include "mbed_assert.h" -#include "gpio_msp432.h" - -extern uint8_t open_drain[10]; -extern uint8_t open_source[10]; -extern uint8_t pull_up[10]; -extern uint8_t pull_down[10]; - -/* Helper macro to access single bits in the - * bitmap arrays above - */ -#define FLAG_SET(array) (array[obj->port_index] & obj->mask) - -/** Set the given pin as GPIO - * - * @param pin The pin to be set as GPIO - * @return The GPIO port mask for this pin - **/ -uint32_t gpio_set(PinName pin) -{ - pin_function(pin, MSP432_PIN_DATA(SEL0, PIN_INPUT, PullNone, 0)); - return 1 << MSP432_PIN_IDX(pin); -} - -/* Checks if gpio object is connected (pin was not initialized with NC) - * @param pin The pin to be set as GPIO - * @return 0 if port is initialized with NC - **/ -int gpio_is_connected(const gpio_t *obj) -{ - return obj->pin_base != 0; -} - -/** Initialize the GPIO pin - * - * @param obj The GPIO object to initialize - * @param pin The GPIO pin to initialize - */ -void gpio_init(gpio_t *obj, PinName pin) -{ - if (pin == (PinName)NC) { - obj->pin_base = 0; - return; - } - uint8_t port_index = MSP432_PORT_IDX(pin); - uint8_t pin_index = MSP432_PIN_IDX(pin); - if (port_index > 9 || pin_index > 7) { - obj->pin_base = 0; - return; - } - /* Initialize the gpio_t object */ - obj->pin = pin; - obj->mask = gpio_set(pin); - obj->port_index = port_index; - obj->pin_base = PIN_BASE(port_index, pin_index); - - /* Initialize the gpio flags */ - open_drain[port_index] &= ~obj->mask; - open_source[port_index] &= ~obj->mask; - pull_up[port_index] &= ~obj->mask; - pull_down[port_index] &= ~obj->mask; -} - -/** Set the input pin mode - * - * @param obj The GPIO object - * @param mode The pin mode to be set - */ -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -/** Set the pin direction - * - * @param obj The GPIO object - * @param direction The pin direction to be set - */ -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - PIN_REG(obj->pin_base, REG_DIR) = direction; -} - -/** Set the output value - * - * @param obj The GPIO object - * @param value The value to be set - */ -void gpio_write(gpio_t *obj, int value) -{ - if (FLAG_SET(open_drain)) { - if (FLAG_SET(pull_up)) { - if (value) { - PIN_REG(obj->pin_base, REG_DIR) = 0; - PIN_REG(obj->pin_base, REG_OUT) = 1; - } else { - PIN_REG(obj->pin_base, REG_OUT) = 0; - PIN_REG(obj->pin_base, REG_DIR) = 1; - } - } else { - // Open drain without pullup - PIN_REG(obj->pin_base, REG_DIR) = !value; - } - } else if (FLAG_SET(open_source)) { - if (FLAG_SET(pull_down)) { - if (value) { - PIN_REG(obj->pin_base, REG_OUT) = 1; - PIN_REG(obj->pin_base, REG_DIR) = 1; - } else { - PIN_REG(obj->pin_base, REG_DIR) = 0; - PIN_REG(obj->pin_base, REG_OUT) = 0; - } - } else { - // Open source without pull down - PIN_REG(obj->pin_base, REG_DIR) = value; - } - } else { - // Normal push/pull operation - PIN_REG(obj->pin_base, REG_OUT) = value; - } -} - -/** Read the input value - * - * @param obj The GPIO object - * @return An integer value 1 or 0 - */ -int gpio_read(gpio_t *obj) -{ - return PIN_REG(obj->pin_base, REG_IN); -} - diff --git a/targets/TARGET_TI/TARGET_MSP432/gpio_irq_api.c b/targets/TARGET_TI/TARGET_MSP432/gpio_irq_api.c deleted file mode 100644 index 9ee58cbf70a..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/gpio_irq_api.c +++ /dev/null @@ -1,219 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Low-level implementation of gpio interrupts for MSP432. - * This implementation uses bit-banding, so no masking of bits - * is necessary during simple get/set operations for a single pin. - * - * See hal/gpio_api.h for a detailed description of the following - * functions. - */ -#if DEVICE_INTERRUPTIN - -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "gpio_msp432.h" - -static uint32_t irq_ids [6][8] = {0}; -static uint8_t both_edges[6][8] = {0}; - -static gpio_irq_handler irq_handler = 0; - - -/** Initialize the GPIO IRQ pin - * - * @param obj The GPIO object to initialize - * @param pin The GPIO pin name - * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID (id != 0, 0 is reserved) - * @return -1 if pin is NC, 0 otherwise - */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - if (pin == (PinName)NC) { - obj->pin_base = 0; - return -1; - } - uint8_t port_index = MSP432_PORT_IDX(pin); - uint8_t pin_index = MSP432_PIN_IDX(pin); - if (port_index > 5 || pin_index > 7) { - obj->pin_base = 0; - error("IRQs not supported on GPIO P%d.%d\r\n", port_index + 1, pin_index); - return -1; - } - // Initialize the gpio_t object - obj->pin_base = PIN_BASE(port_index, pin_index); - obj->port = port_index; - obj->pin = pin_index; - obj->rise = 0; - obj->fall = 0; - // Store irq handler. We do not have to store - // a separate handler for every pin, because the - // InterruptIn-driver will always use the same one... - irq_handler = handler; - // Store the ID for this specific pin. It will be - // used as a pointer to one InterruptIn instance by - // the InterruptIn class. - irq_ids[port_index][pin_index] = id; - // Clear pending IRQ - PIN_REG(obj->pin_base, REG_IFG) = 0; - // Enable IRQs on this port - NVIC_EnableIRQ((IRQn_Type)(35 + port_index)); - return 0; -} - -/** Release the GPIO IRQ PIN - * - * @param obj The gpio object - */ -void gpio_irq_free(gpio_irq_t *obj) -{ - // Disable the interrupts - gpio_irq_disable(obj); - // Clear the ID - irq_ids[obj->port][obj->pin] = 0; - // Clear the gpio_irq_t object - obj->pin_base = 0; - obj->port = 0; - obj->pin = 0; - obj->rise = 0; - obj->fall = 0; -} - -/** Enable/disable pin IRQ event - * - * @param obj The GPIO object - * @param event The GPIO IRQ event - * @param enable The enable flag - */ -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - // Disable irqs for this pin while we are in the - // configuration process (so we have a chance to - // clear spurious interrupts. - PIN_REG(obj->pin_base, REG_IE) = 0; - switch (event) { - case IRQ_RISE: { - // Listen to rising edges - PIN_REG(obj->pin_base, REG_IES) = 0; - obj->rise = enable; - // Check if we have enabled both edges - both_edges[obj->port][obj->pin] = obj->rise && obj->fall; - break; - } - case IRQ_FALL: { - // Listen to falling edges - PIN_REG(obj->pin_base, REG_IES) = 1; - obj->fall = enable; - // Check if we have enabled both edges - both_edges[obj->port][obj->pin] = obj->rise && obj->fall; - break; - } - case IRQ_NONE: - default: - break; - } - // Enable IRQ as requested - enable ? gpio_irq_enable(obj) : gpio_irq_disable(obj); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - // Clear pending interrupts (just in case...) - PIN_REG(obj->pin_base, REG_IFG) = 0; - // Check if both edges need to be detected and - // set initial edge select accordingly - if (both_edges[obj->port][obj->pin]) { - PIN_REG(obj->pin_base, REG_IES) = PIN_REG(obj->pin_base, REG_IN); - // Make sure we don't accidently trigger a irq! - PIN_REG(obj->pin_base, REG_IFG) = 0; - } - // Enable irqs for this pin - PIN_REG(obj->pin_base, REG_IE) = 1; -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - // Disable irqs for this pin - PIN_REG(obj->pin_base, REG_IE) = 0; - // Clear pending interrupts - PIN_REG(obj->pin_base, REG_IFG) = 0; -} - -/**********************************/ -/* Interrupt handlers for P1...P6 */ -/**********************************/ -void handle_interrupt_in(uint8_t port, uint8_t pin) -{ - __IO uint8_t *pin_base = PIN_BASE(port, pin); - // Call the second-stage handler - if (irq_handler) { - irq_handler(irq_ids[port][pin], - PIN_REG(pin_base, REG_IN) ? IRQ_RISE : IRQ_FALL); - } - // Change the edge select when listening on both edges - if (both_edges[port][pin]) { - PIN_REG(pin_base, REG_IES) = PIN_REG(pin_base, REG_IN); - // Make sure we don't accidently trigger a irq! - PIN_REG(pin_base, REG_IFG) = 0; - } -} - -void PORT1_IRQHandler(void) -{ - uint32_t pin = P1->IV >> 1; - if (pin--) { - handle_interrupt_in(0, pin); - } -} -void PORT2_IRQHandler(void) -{ - uint32_t pin = P2->IV >> 1; - if (pin--) { - handle_interrupt_in(1, pin); - } -} -void PORT3_IRQHandler(void) -{ - uint32_t pin = P3->IV >> 1; - if (pin--) { - handle_interrupt_in(2, pin); - } -} -void PORT4_IRQHandler(void) -{ - uint32_t pin = P4->IV >> 1; - if (pin--) { - handle_interrupt_in(3, pin); - } -} -void PORT5_IRQHandler(void) -{ - uint32_t pin = P5->IV >> 1; - if (pin--) { - handle_interrupt_in(4, pin); - } -} -void PORT6_IRQHandler(void) -{ - uint32_t pin = P6->IV >> 1; - if (pin--) { - handle_interrupt_in(5, pin); - } -} - -#endif /* DEVICE_INTERRUPTIN */ diff --git a/targets/TARGET_TI/TARGET_MSP432/gpio_msp432.c b/targets/TARGET_TI/TARGET_MSP432/gpio_msp432.c deleted file mode 100644 index 217b7f6dc34..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/gpio_msp432.c +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis.h" - -// Bit-Band base addresses of the 10 GPIO ports -__IO uint8_t *gpio_bitband_base[10] = { - &BITBAND_PERI(P1->IN, 0), &BITBAND_PERI(P2->IN, 0), - &BITBAND_PERI(P3->IN, 0), &BITBAND_PERI(P4->IN, 0), - &BITBAND_PERI(P5->IN, 0), &BITBAND_PERI(P6->IN, 0), - &BITBAND_PERI(P7->IN, 0), &BITBAND_PERI(P8->IN, 0), - &BITBAND_PERI(P9->IN, 0), &BITBAND_PERI(P10->IN, 0) -}; - -// Standard base addresses of the 10 ports -__I uint8_t *port_base[10] = { - &P1->IN, &P2->IN, &P3->IN, &P4->IN, &P5->IN, - &P6->IN, &P7->IN, &P8->IN, &P9->IN, &P10->IN -}; diff --git a/targets/TARGET_TI/TARGET_MSP432/gpio_msp432.h b/targets/TARGET_TI/TARGET_MSP432/gpio_msp432.h deleted file mode 100644 index cd7b425df5a..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/gpio_msp432.h +++ /dev/null @@ -1,80 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file contains some bitband alias helper macros, - * so that the source code is more readable. - */ - -#ifndef GPIO_MSP432_H -#define GPIO_MSP432_H - -#include -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// GPIO register offsets -#define REG_IN 0x00 -#define REG_OUT 0x02 -#define REG_DIR 0x04 -#define REG_REN 0x06 -#define REG_SEL0 0x0a -#define REG_SEL1 0x0c -#define REG_IES 0x18 -#define REG_IE 0x1a -#define REG_IFG 0x1c - -/* - * Bit-Band base addresses of the 10 GPIO ports - */ -extern __IO uint8_t *gpio_bitband_base[10]; - -/* - * Port base addresses of the 10 GPIO ports - */ -extern __IO uint8_t *port_base[10]; - -/* - * Macro to calculate the bitband base address of a single pin. - * (within the IN-register, which has an offset of 0) - * port range: 0..10, corresponding to P1...P10,PJ - * pin range: 0..7 , corresponding to pin index - */ -#define PIN_BASE(port,pin) ((__IO uint8_t *) (gpio_bitband_base[port] + (pin<<2) )) - -/* - * Macro to calculate the adrdess of a pin within a given register. - * base: pin base address - * reg: offset to a specific register (REG_xxx) - */ -#define PIN_REG(base,reg) (*(base + (reg<<5))) - -/* - * Macro to calculate the adrdess of a port register. - * base: port base address - * reg: offset to a specific register (REG_xxx) - */ -#define PORT_REG(base,reg) (base + reg) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_MSP432/i2c_api.c b/targets/TARGET_TI/TARGET_MSP432/i2c_api.c deleted file mode 100644 index 498b4a26f82..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/i2c_api.c +++ /dev/null @@ -1,619 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Low-level implementation of I2C functionality for MSP432. - * This implementation does also support DEVICE_I2CSLAVE and DEVICE_I2C_ASYNCH. - */ - - -#if DEVICE_I2C - -#include "i2c_api.h" -#include "mbed_assert.h" - -/* With I2C_ASYNCH, our type i2c_s is embedded - * into a bigger structure (see i2c_api.h). So we - * need a macro to extract the i2c_s object. - */ -#if DEVICE_I2C_ASYNCH -#define I2C_S(obj) (&((obj)->i2c)) -#else -#define I2C_S(obj) (obj) -#endif - -#if DEVICE_I2C_ASYNCH -// Array with object pointers for ISR -i2c_t *i2c_objects[4] = {0}; -#endif - -/** Initialize the I2C peripheral. It sets the default parameters for I2C - * peripheral, and configures its specifieds pins. - * - * @param obj The I2C object - * @param sda The sda pin - * @param scl The scl pin - */ -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - struct i2c_s *objs = I2C_S(obj); - - /* Check if the pins support I2C */ - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - objs->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(objs->i2c != (I2CName)NC); - - /* Configure I2C pins */ - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, GET_DATA_MODE(pinmap_function(sda, PinMap_I2C_SDA))); - pin_mode(scl, GET_DATA_MODE(pinmap_function(scl, PinMap_I2C_SCL))); - - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Put EUSCI to reset state */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = 1; - /* Configure I2C mode */ - EUSCI->CTLW0 |= EUSCI_B_CTLW0_MST | /* master mode */ - EUSCI_B_CTLW0_MODE_3 | /* I2C mode */ - EUSCI_B_CTLW0_SSEL__SMCLK; /* SMCLK */ - EUSCI->CTLW1 = 0; - /* Set i2c clock to default 100 kHz */ - i2c_frequency(obj, 100000); - /* Disable and clear interrupts */ - EUSCI->IE = 0; - EUSCI->IFG = 0; - /* Clear the EUSCI reset state (enable module)*/ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = 0; -#if DEVICE_I2C_ASYNCH - // Store the object pointer for the ISR - int index = (((uint32_t)(objs->i2c)) >> 10) & 0x3; - i2c_objects[index] = obj; - objs->active = false; - /* Enable the NVIC irq for this I2C module */ - NVIC_EnableIRQ((IRQn_Type)(EUSCIB0_IRQn + index)); -#endif -} - -/** Configure the I2C frequency - * - * @param obj The I2C object - * @param hz Frequency in Hz - */ -void i2c_frequency(i2c_t *obj, int hz) -{ - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Set I2C speed */ - EUSCI->BRW = SubsystemMasterClock / hz; -} - -/** Send START command - * This method will also send the I2C address, along - * with the R/W bit! - * - * @param obj The I2C object - */ -int i2c_start(i2c_t *obj) -{ - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Trigger a START condition */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTT_OFS) = 1; - /* Wait until START condition and device address has been sent */ - while (BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTT_OFS)) ; - return 0; -} - -/** Send STOP command - * - * @param obj The I2C object - */ -int i2c_stop(i2c_t *obj) -{ - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Trigger a STOP condition */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = 1; - /* Wait until STOP condition has been sent */ - while (BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS)) ; - return 0; -} - -/** Blocking reading data - * - * @param obj The I2C object - * @param address 7-bit address (last bit is 1) - * @param data The buffer for receiving - * @param length Number of bytes to read - * @param stop Stop to be generated after the transfer is done - * @return Number of read bytes - */ -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - /* This I2C implementation does not support a missing STOP - * condition after a master read operation. To send the final - * NACK, we will always have to trigger a STOP condition! */ - MBED_ASSERT(stop); - /* Get the I2C base */ - struct i2c_s *objs = I2C_S(obj); - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Clear interrupt status and set slave address */ - EUSCI->IFG = 0; - EUSCI->I2CSA = address >> 1; - /* Set receiver mode and send START condition */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TR_OFS) = 0; - i2c_start(obj); - int i; - for (i = 0; i < length; ++i) { - // Check if last byte to receive - if (i + 1 == length) { - // We have to trigger a STOP condition to - // send the final NACK so the slave knows - // we do not want any more data. - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = 1; - } - // Wait until data is available - while (!BITBAND_PERI(EUSCI->IFG, EUSCI_B_IFG_RXIFG0_OFS)); - // read the data - data[i] = EUSCI->RXBUF; - } - if (!length) { - i2c_stop(obj); - } - return length; -} - -/** Blocking sending data - * - * @param obj The I2C object - * @param address 7-bit address (last bit is 0) - * @param data The buffer for sending - * @param length Number of bytes to write - * @param stop Stop to be generated after the transfer is done - * @return - * zero or non-zero - Number of written bytes - * negative - I2C_ERROR_XXX status - */ -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - /* Get the I2C base */ - struct i2c_s *objs = I2C_S(obj); - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Clear interrupt status and set slave address */ - EUSCI->IFG = 0; - EUSCI->I2CSA = address >> 1; - /* Set transmitter mode and send START condition */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TR_OFS) = 1; - i2c_start(obj); - int i; - for (i = 0; i < length; ++i) { - // Fill transmit buffer - EUSCI->TXBUF = data[i]; - // Wait until data is available or NACK - while (!(EUSCI->IFG & (EUSCI_B_IFG_TXIFG0 | EUSCI_B_IFG_NACKIFG))); - // Check NACK condition - if (BITBAND_PERI(EUSCI->IFG, EUSCI_B_IFG_NACKIFG_OFS)) { - // Generate STOP condition if requested - if (stop) { - i2c_stop(obj); - } - return i ? i - 1 : I2C_ERROR_NO_SLAVE; - } - } - /* Generate STOP condition if requested */ - if (stop) { - i2c_stop(obj); - } - return length; -} - -/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop() - * - * @param obj The I2C object - */ -void i2c_reset(i2c_t *obj) -{ - i2c_stop(obj); -} - -/** Read one byte - * - * @param obj The I2C object - * @param last Acknoledge - * @return The read byte - */ -int i2c_byte_read(i2c_t *obj, int last) -{ - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Trigger STOP if we receive the last byte */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = last; - /* Wait until data is available */ - while (!BITBAND_PERI(EUSCI->IFG, EUSCI_B_IFG_RXIFG0_OFS)); - // Return byte - return EUSCI->RXBUF; -} - -/** Write one byte - * - * @param obj The I2C object - * @param data Byte to be written - * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout. - */ -int i2c_byte_write(i2c_t *obj, int data) -{ - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Place character in buffer */ - EUSCI->TXBUF = data; - // Wait until byte has been sent or NACK - while (!(EUSCI->IFG & (EUSCI_B_IFG_TXIFG0 | EUSCI_B_IFG_NACKIFG))); - // return 1 if write was successfull - return BITBAND_PERI(EUSCI->IFG, EUSCI_B_IFG_NACKIFG_OFS) ? 0 : 1; -} - -/** Get the pins that support I2C SDA - * - * Return a PinMap array of pins that support I2C SDA in - * master mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *i2c_master_sda_pinmap(void) -{ - return PinMap_I2C_SDA; -} - -/** Get the pins that support I2C SCL - * - * Return a PinMap array of pins that support I2C SCL in - * master mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *i2c_master_scl_pinmap(void) -{ - return PinMap_I2C_SCL; -} - -#if DEVICE_I2CSLAVE - -/** Configure I2C as slave or master. - * @param obj The I2C object - * @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive - * @return non-zero if a value is available - */ -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Set master/slave mode */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_MST_OFS) = !enable_slave; -} - -/** Check to see if the I2C slave has been addressed. - * @param obj The I2C object - * @return The status - 1 - read addresses, 2 - write to all slaves, - * 3 write addressed, 0 - the slave has not been addressed - */ -int i2c_slave_receive(i2c_t *obj) -{ - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Check irq flags */ - if (EUSCI->IFG & EUSCI_B_IFG_TXIFG0) { - /* master wants to read, slave has to transmit */ - return 1; - } - if (EUSCI->IFG & EUSCI_B_IFG_RXIFG0) { - /* master has written, slave has to receive */ - return 3; - } - return 0; -} - -/** I2C slave reads data from master. - * @param obj The I2C object - * @param data The buffer for receiving - * @param length Number of bytes to read - * @return non-zero if a value is available - */ -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - /* Get the I2C base */ - struct i2c_s *objs = I2C_S(obj); - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - int i; - for (i = 0; i < length; ++i) { - // Wait until data is available - while (!BITBAND_PERI(EUSCI->IFG, EUSCI_B_IFG_RXIFG0_OFS)); - // read the data - data[i] = EUSCI->RXBUF; - } - return length; -} - -/** I2C slave writes data to master. - * @param obj The I2C object - * @param data The buffer for sending - * @param length Number of bytes to write - * @return non-zero if a value is available - */ -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - /* Get the I2C base */ - struct i2c_s *objs = I2C_S(obj); - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - int i; - for (i = 0; i < length; ++i) { - // Wait until data may be sent - while (!BITBAND_PERI(EUSCI->IFG, EUSCI_B_IFG_TXIFG0_OFS)); - // Fill transmit buffer - EUSCI->TXBUF = data[i]; - } - // Discard the next TXIFG, which is automatically triggered - // after sending the last byte. Without doing this, the - // receive()-method would detect a false slave-write! - while (!BITBAND_PERI(EUSCI->IFG, EUSCI_B_IFG_TXIFG0_OFS)); - BITBAND_PERI(EUSCI->IFG, EUSCI_B_IFG_TXIFG0_OFS) = 0; - return length; -} - -/** Configure I2C address. - * @param obj The I2C object - * @param idx Currently not used - * @param address The address to be set - * @param mask Currently not used - */ -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - /* Put EUSCI to reset state */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = 1; - /* Set own address. The EUSCI in I2C mode could - * also support multiple addresses (idx parameter) - * and an address mask, but this is currently not - * used by mbed-os drivers. */ - EUSCI->I2COA0 = (address >> 1) | EUSCI_B_I2COA0_OAEN; - /* Clear EUSCI reset state) */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = 0; -} - -/** Get the pins that support I2C SDA as slave - * - * Return a PinMap array of pins that support I2C SDA in - * slave mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *i2c_slave_sda_pinmap(void) -{ - return PinMap_I2C_SDA; -} - -/** Get the pins that support I2C SCL as slave - * - * Return a PinMap array of pins that support I2C SCL in - * slave mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *i2c_slave_scl_pinmap(void) -{ - return PinMap_I2C_SCL; -} - -#endif /* DEVICE_I2CSLAVE */ - - -#if DEVICE_I2C_ASYNCH - -/** Start I2C asynchronous transfer - * - * @param obj The I2C object - * @param tx The transmit buffer - * @param tx_length The number of bytes to transmit - * @param rx The receive buffer - * @param rx_length The number of bytes to receive - * @param address The address to be set - 7bit or 9bit - * @param stop If true, stop will be generated after the transfer is done - * @param handler The I2C IRQ handler to be set - * @param event Event mask for the transfer. See \ref hal_I2CEvents - * @param hint DMA hint usage - */ -void i2c_transfer_asynch(i2c_t *obj, - const void *tx, size_t tx_length, - void *rx, size_t rx_length, - uint32_t address, uint32_t stop, - uint32_t handler, uint32_t event, - DMAUsage hint) -{ - // We ignore DMA for now - (void) hint; - - struct i2c_s *objs = I2C_S(obj); - /* Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - - // Update object - obj->tx_buff.buffer = (void *)tx; - obj->tx_buff.length = tx_length; - obj->tx_buff.pos = 0; - obj->tx_buff.width = 8; - - obj->rx_buff.buffer = (void *)rx; - obj->rx_buff.length = rx_length; - obj->rx_buff.pos = 0; - obj->rx_buff.width = 8; - - objs->send_stop = stop; - objs->handler = (void (*)(void))handler; - objs->event = 0; - objs->available_events = event; - - /* Clear interrupt status and set slave address */ - EUSCI->IFG = 0; - EUSCI->I2CSA = address >> 1; - - // Start the ball rolling by either enabling TX or RX interrupts - if (tx_length) { - objs->active = true; - /* Set transmitter mode and send START condition */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TR_OFS) = 1; - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTT_OFS) = 1; - EUSCI->IE = EUSCI_B_IE_TXIE | EUSCI_B_IE_NACKIE; - } else if (rx_length) { - objs->active = true; - /* Set receiver mode and send START condition */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TR_OFS) = 0; - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTT_OFS) = 1; - EUSCI->IE = EUSCI_B_IE_RXIE; - } -} - -/** The asynchronous IRQ handler - * - * @param obj The I2C object which holds the transfer information - * @return Event flags if a transfer termination condition was met, otherwise return 0. - */ -uint32_t i2c_irq_handler_asynch(i2c_t *obj) -{ - struct i2c_s *objs = I2C_S(obj); - return (objs->event & objs->available_events); -} - -/** Attempts to determine if the I2C peripheral is already in use - * - * @param obj The I2C object - * @return Non-zero if the I2C module is active or zero if it is not - */ -uint8_t i2c_active(i2c_t *obj) -{ - struct i2c_s *objs = I2C_S(obj); - return objs->active; -} - -/** Abort asynchronous transfer - * - * This function does not perform any check - that should happen in upper layers. - * @param obj The I2C object - */ -void i2c_abort_asynch(i2c_t *obj) -{ - struct i2c_s *objs = I2C_S(obj); - // Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - EUSCI->IE = 0; - EUSCI->IFG = 0; - objs->active = false; -} - -/*************************/ -/* I2C interrupt handler */ -/*************************/ -void handle_I2C_Interrupt(i2c_t *obj) -{ - struct i2c_s *objs = I2C_S(obj); - // Get the I2C base */ - EUSCI_B_Type *EUSCI = (EUSCI_B_Type *)objs->i2c; - uint16_t vector = EUSCI->IV; - switch (vector) { - /* UCNACKIFG */ - case 0x04: { - objs->event = I2C_EVENT_TRANSFER_EARLY_NACK; - objs->handler(); - break; - } - /* UCRXIFG0 */ - case 0x16: { - struct buffer_s *rx_buff = &obj->rx_buff; - if (rx_buff->pos < rx_buff->length) { - ((uint8_t *)rx_buff->buffer)[rx_buff->pos] = EUSCI->RXBUF; - rx_buff->pos++; - } - if (rx_buff->pos + 1 == rx_buff->length) { - EUSCI->CTLW0 |= EUSCI_B_CTLW0_TXSTP; - } - if (rx_buff->pos == rx_buff->length) { - BITBAND_PERI(EUSCI->IE, EUSCI_B_IE_TXIE_OFS) = 0; - objs->active = false; - objs->event = I2C_EVENT_TRANSFER_COMPLETE; - objs->handler(); - } - break; - } - /* UCTXIFG0 */ - case 0x18: { - struct buffer_s *tx_buff = &obj->tx_buff; - if (tx_buff->pos < tx_buff->length) { - EUSCI->TXBUF = ((uint8_t *)tx_buff->buffer)[tx_buff->pos]; - tx_buff->pos++; - } else { - if (objs->send_stop) { - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = 1; - } - // Disable interrupts - EUSCI->IE = 0; - // Check if we have to receive data - if (obj->rx_buff.length) { - /* Set transmitter mode and send START condition */ - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TR_OFS) = 0; - BITBAND_PERI(EUSCI->CTLW0, EUSCI_B_CTLW0_TXSTT_OFS) = 1; - // Enable the RX interrupts - EUSCI->IE = EUSCI_B_IE_RXIE; - } else { - objs->active = false; - objs->event = I2C_EVENT_TRANSFER_COMPLETE; - objs->handler(); - } - } - break; - } - } -} - -void EUSCIB0_I2C_IRQHandler(void) -{ - handle_I2C_Interrupt(i2c_objects[0]); -} -void EUSCIB1_I2C_IRQHandler(void) -{ - handle_I2C_Interrupt(i2c_objects[1]); -} -void EUSCIB2_I2C_IRQHandler(void) -{ - handle_I2C_Interrupt(i2c_objects[2]); -} -void EUSCIB3_I2C_IRQHandler(void) -{ - handle_I2C_Interrupt(i2c_objects[3]); -} - -#endif // DEVICE_I2C_ASYNCH - -#endif // DEVICE_I2C - diff --git a/targets/TARGET_TI/TARGET_MSP432/objects.h b/targets/TARGET_TI/TARGET_MSP432/objects.h deleted file mode 100644 index 8b7bfced441..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/objects.h +++ /dev/null @@ -1,119 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint8_t mask; - uint8_t port_index; - __IO uint8_t *pin_base; -} gpio_t; - -struct gpio_irq_s { - uint8_t pin; - uint8_t port; - bool rise; - bool fall; - __IO uint8_t *pin_base; -}; - -struct port_s { - PortName port; - uint8_t mask; - __IO uint8_t *port_in; - __IO uint8_t *port_out; - __IO uint8_t *port_dir; -}; - -struct serial_s { - UARTName uart; - PinName pin_tx; - PinName pin_rx; -}; - -struct analogin_s { - uint8_t mem_index; -}; - -struct i2c_s { - I2CName i2c; -#if DEVICE_I2C_ASYNCH - bool active; - bool send_stop; - void (*handler)(); - uint8_t event; - uint8_t available_events; -#endif -}; - -struct spi_s { - SPIName spi; - uint8_t module; - PinName pin_miso; - PinName pin_mosi; - PinName pin_sclk; - PinName pin_ssel; - // Addresses of HW-registers - __IO uint16_t *EUSCI_CTLW0; - __IO uint16_t *EUSCI_BRW; - __IO uint16_t *EUSCI_STATW; - __I uint16_t *EUSCI_RXBUF; - __IO uint16_t *EUSCI_TXBUF; - __IO uint16_t *EUSCI_IE; - __IO uint16_t *EUSCI_IFG; - __I uint16_t *EUSCI_IV; -#if DEVICE_SPI_ASYNCH - bool active; - void (*handler)(); - uint8_t event; - uint8_t available_events; -#endif -}; - -struct pwmout_s { - PWMName pwm; - PinName pin; - uint8_t ccr_index; - uint32_t divider; - uint32_t pulse; - uint32_t ccr0; - float dutyCycle; -}; - -struct flash_s { - /* nothing to be stored for now */ - uint32_t dummy; -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TI/TARGET_MSP432/pinmap.c b/targets/TARGET_TI/TARGET_MSP432/pinmap.c deleted file mode 100644 index 8fc6f07e083..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/pinmap.c +++ /dev/null @@ -1,116 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "pinmap.h" -#include "mbed_assert.h" -#include "PeripheralPins.h" -#include "gpio_msp432.h" - -/* - * Bitmask arrays for gpio mode configuration - */ -uint8_t open_drain[10] = {0}; -uint8_t open_source[10] = {0}; -uint8_t pull_up[10] = {0}; -uint8_t pull_down[10] = {0}; - -/* - * Configure pin (SEL function and direction) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - uint8_t port_index = MSP432_PORT_IDX(pin); - uint8_t pin_index = MSP432_PIN_IDX(pin); - MBED_ASSERT(port_index < 10 && pin_index < 8); - - __IO uint8_t *pin_base = PIN_BASE(port_index, pin_index); - - // Set the SEL bits - uint8_t sel = GET_DATA_SEL(data); - PIN_REG(pin_base, REG_SEL0) = sel & 1; - PIN_REG(pin_base, REG_SEL1) = sel >> 1; - - // Set gpio direction - PIN_REG(pin_base, REG_DIR) = GET_DATA_DIR(data); -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - uint8_t port_index = MSP432_PORT_IDX(pin); - uint8_t pin_index = MSP432_PIN_IDX(pin); - MBED_ASSERT(port_index < 10 && pin_index < 8); - - __IO uint8_t *pin_base = PIN_BASE(port_index, pin_index); - - uint8_t mask = 1 << pin_index; - - // Set mode to default state - open_drain[port_index] &= ~mask; - open_source[port_index] &= ~mask; - pull_up[port_index] &= ~mask; - pull_down[port_index] &= ~mask; - PIN_REG(pin_base, REG_REN) = 0; - - switch (mode) { - case PullNone: { - break; - } - case PullUp: { - pull_up[port_index] |= mask; - PIN_REG(pin_base, REG_REN) = 1; - PIN_REG(pin_base, REG_OUT) = 1; - break; - } - case PullDown: { - pull_down[port_index] |= mask; - PIN_REG(pin_base, REG_REN) = 1; - PIN_REG(pin_base, REG_OUT) = 0; - break; - } - case OpenDrain: { - PIN_REG(pin_base, REG_DIR) = !PIN_REG(pin_base, REG_OUT); - open_drain[port_index] |= mask; - break; - } - case OpenDrainPullUp: { - open_drain[port_index] |= mask; - pull_up[port_index] |= mask; - PIN_REG(pin_base, REG_REN) = 1; - PIN_REG(pin_base, REG_DIR) = !PIN_REG(pin_base, REG_OUT); - break; - } - case OpenSource: { - open_source[port_index] |= mask; - PIN_REG(pin_base, REG_DIR) = PIN_REG(pin_base, REG_OUT); - break; - } - case OpenSourcePullDown: { - open_source[port_index] |= mask; - pull_down[port_index] |= mask; - PIN_REG(pin_base, REG_REN) = 1; - PIN_REG(pin_base, REG_DIR) = PIN_REG(pin_base, REG_OUT); - break; - } - } -} - diff --git a/targets/TARGET_TI/TARGET_MSP432/port_api.c b/targets/TARGET_TI/TARGET_MSP432/port_api.c deleted file mode 100644 index 8d3eefff243..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "port_api.h" -#include "gpio_msp432.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -/** Get the pin name from the port's pin number - * - * @param port The port name - * @param pin_n The pin number within the specified port - * @return The pin name for the port's pin number - */ -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)((port << 4) + pin_n); -} - -/** Initilize the port - * - * @param obj The port object to initialize - * @param port The port name - * @param mask The bitmask to identify which bits in the port should be included (0 - ignore) - * @param dir The port direction - */ -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - /* Initialize the port object */ - obj->port = port; - obj->mask = mask; - obj->port_in = PORT_REG(port_base[port], REG_IN); - obj->port_out = PORT_REG(port_base[port], REG_OUT); - obj->port_dir = PORT_REG(port_base[port], REG_DIR); - port_dir(obj, dir); -} - -/** Set the input port mode - * - * @param obj The port object - * @param mode THe port mode to be set - */ -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 8; i++) { - /* Is pin used ? */ - if (obj->mask & (1 << i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -/** Set port direction (in/out) - * - * @param obj The port object - * @param dir The port direction to be set - */ -void port_dir(port_t *obj, PinDirection dir) -{ - if (dir == PIN_OUTPUT) { - *obj->port_dir |= (obj->mask); - } else { - *obj->port_dir &= ~(obj->mask); - } -} - -/** Write value to the port - * - * @param obj The port object - * @param value The value to be set - */ -void port_write(port_t *obj, int value) -{ - *obj->port_out = (*obj->port_out & ~obj->mask) | (value & obj->mask); -} - -/** Read the current value on the port - * - * @param obj The port object - * @return An integer with each bit corresponding to an associated port pin setting - */ -int port_read(port_t *obj) -{ - return *obj->port_in & obj->mask; -} - -#endif /* DEVICE_PORTIN || DEVICE_PORTOUT */ diff --git a/targets/TARGET_TI/TARGET_MSP432/pwmout_api.c b/targets/TARGET_TI/TARGET_MSP432/pwmout_api.c deleted file mode 100644 index b684ab1e856..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/pwmout_api.c +++ /dev/null @@ -1,213 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Low-level implementation of PWM functionality for MSP432. - Only TIMER A0..A2 are used for PWM, because TIMER A3 is - already used for the us ticker. SMCLK is typically 3 MHz, - and the maximum pre-divider is 64. With TIMER A being a - 16 bit counter, we have a maximum period of - 64 * 65536 / 3000000 = 1.39 seconds! - In total there are 12 PWM outputs. Each 4 outputs - from one Timer-A module (A0..A2) shared the same period! - */ - -#include "pwmout_api.h" -#include "mbed_assert.h" -#include - -#if DEVICE_PWMOUT - -/** Initialize the pwm out peripheral and configure the pin - * - * @param obj The pwmout object to initialize - * @param pin The pwmout pin to initialize - */ -void pwmout_init(pwmout_t *obj, PinName pin) -{ - /* Get the peripheral name */ - obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(obj->pwm != (PWMName)NC); - /* Fill obj (get the index of the Capture/Compare Register (CCR)) */ - obj->pin = pin; - obj->ccr_index = GET_DATA_CHAN(pinmap_function(pin, PinMap_PWM)); - obj->pulse = 0; - obj->dutyCycle = 0.0f; - /* Configure PWM pin */ - pinmap_pinout(pin, PinMap_PWM); - /* Get the TIMER A base */ - Timer_A_Type *TA = (Timer_A_Type *)obj->pwm; - /* Configure the TIMER A and the CCR */ - TA->CTL = TIMER_A_CTL_SSEL__SMCLK | /* SMCLK clock source */ - TIMER_A_CTL_MC__UP | /* Up-mode (count to CCR0) */ - TIMER_A_CTL_CLR; /* Reset counter */ - /* Use reset/set mode (mode 7) */ - TA->CCTL[obj->ccr_index] = TIMER_A_CCTLN_OUTMOD_7; - // Set default period (20ms) - pwmout_period_us(obj, 20000); -} - -/** Deinitialize the pwmout object - * - * @param obj The pwmout object - */ -void pwmout_free(pwmout_t *obj) -{ - /* Get the TIMER A base */ - Timer_A_Type *TA = (Timer_A_Type *)obj->pwm; - /* Stop the timer */ - TA->CTL = 0; - /* De-configure the pin */ - pin_function(obj->pin, MSP432_PIN_DATA(SEL0, PIN_INPUT, PullNone, 0)); -} - -/** Set the output duty-cycle in range <0.0f, 1.0f> - * - * Value 0.0f represents 0 percentage, 1.0f represents 100 percent. - * @param obj The pwmout object - * @param percent The floating-point percentage number - */ -void pwmout_write(pwmout_t *obj, float percent) -{ - obj->dutyCycle = percent; - obj->pulse = (float)obj->ccr0 * percent; - /* Get the TIMER A base */ - Timer_A_Type *TA = (Timer_A_Type *)obj->pwm; - // Set the CCR register - TA->CCR[obj->ccr_index] = obj->pulse; -} - -/** Read the current float-point output duty-cycle - * - * @param obj The pwmout object - * @return A floating-point output duty-cycle - */ -float pwmout_read(pwmout_t *obj) -{ - return obj->dutyCycle; -} - -/** Set the PWM period specified in seconds, keeping the duty cycle the same - * - * Periods smaller than microseconds (the lowest resolution) are set to zero. - * @param obj The pwmout object - * @param seconds The floating-point seconds period - */ -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -/** Set the PWM period specified in miliseconds, keeping the duty cycle the same - * - * @param obj The pwmout object - * @param ms The milisecond period - */ -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -/** Set the PWM period specified in microseconds, keeping the duty cycle the same - * - * @param obj The pwmout object - * @param us The microsecond period - */ -void pwmout_period_us(pwmout_t *obj, int us) -{ - /* Calculate dividers and CCR0 */ - uint32_t clock_MHz = SubsystemMasterClock / 1000000; - clock_MHz *= us; - uint16_t id, ex0; - bool found = false; - for (id = 0; id < 4; id++) { - for (ex0 = 0; ex0 < 8; ex0++) { - obj->divider = (1 << id) * (ex0 + 1); - obj->ccr0 = clock_MHz / obj->divider; - if (obj->ccr0 < 0x10000) { - found = true; - break; - } - } - if (found) { - break; - } - } - MBED_ASSERT(found); - /* Get the TIMER A base */ - Timer_A_Type *TA = (Timer_A_Type *)obj->pwm; - // Set the calculated results - TA->CTL &= ~TIMER_A_CTL_ID_MASK; - TA->CTL |= (id << TIMER_A_CTL_ID_OFS); - TA->EX0 = ex0; - TA->CCR[0] = obj->ccr0 - 1; - /* Set the former duty cycle */ - pwmout_write(obj, obj->dutyCycle); -} - -/** Set the PWM pulsewidth specified in seconds, keeping the period the same. - * - * @param obj The pwmout object - * @param seconds The floating-point pulsewidth in seconds - */ -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same. - * - * @param obj The pwmout object - * @param ms The floating-point pulsewidth in miliseconds - */ -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -/** Set the PWM pulsewidth specified in microseconds, keeping the period the same. - * - * @param obj The pwmout object - * @param us The floating-point pulsewidth in microseconds - */ -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - obj->pulse = SubsystemMasterClock / 1000000; - obj->pulse *= us; - obj->pulse /= obj->divider; - MBED_ASSERT(obj->pulse <= obj->ccr0); - /* Set the new duty cycle */ - obj->dutyCycle = (float)obj->pulse / (float)obj->ccr0; - /* Get the TIMER A base */ - Timer_A_Type *TA = (Timer_A_Type *)obj->pwm; - // Set the CCR register - TA->CCR[obj->ccr_index] = obj->pulse; -} - -/** Get the pins that support PWM - * - * Return a PinMap array of pins that support PWM. - * The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *pwmout_pinmap(void) -{ - return PinMap_PWM; -} - -#endif - diff --git a/targets/TARGET_TI/TARGET_MSP432/serial_api.c b/targets/TARGET_TI/TARGET_MSP432/serial_api.c deleted file mode 100644 index 76baf615af3..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/serial_api.c +++ /dev/null @@ -1,406 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Low-level implementation of uart functionality for MSP432. - * This implementation does not (yet) support SERIAL_ASYNCH and SERIAL_FC. - */ - -#if DEVICE_SERIAL - -#include "serial_api.h" -#include "mbed_assert.h" -#include "mbed_error.h" -#include - -/* With SERIAL_ASYNCH, our type serial_s is embedded - * into a bigger structure (see serial_api.h). So we - * need a macro to extract the serial_s object. - */ -#if DEVICE_SERIAL_ASYNCH -#define SERIAL_S(obj) (&((obj)->serial)) -#else -#define SERIAL_S(obj) (obj) -#endif - -int stdio_uart_inited = 0; // used in mbed_retarget.cpp -serial_t stdio_uart; - -uart_irq_handler uart_handler = 0; -uint32_t serial_irq_ids[4] = {0}; - -/** Initialize the serial peripheral. It sets the default parameters for serial - * peripheral, and configures its specifieds pins. - * - * @param obj The serial object - * @param tx The TX pin name - * @param rx The RX pin name - */ -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *objs = SERIAL_S(obj); - uint8_t stdio_config = 0; - - /* Determine the UART to use (UART_A0...UART_A3) */ - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(objs->uart != (UARTName)NC); - /* Fill the obj structure */ - objs->uart = uart; - objs->pin_tx = tx; - objs->pin_rx = rx; - - /* Check if we selected the STDIO UART */ - if ((tx == STDIO_UART_TX) || (rx == STDIO_UART_RX)) { - stdio_config = 1; - } - /* Configure the TX and RX pins */ - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - /* put EUSCI module in reset state */ - EUSCI->CTLW0 = EUSCI_A_CTLW0_SWRST; - /* Configure SMCLK as clock source */ - EUSCI->CTLW0 |= EUSCI_A_CTLW0_SSEL__SMCLK; - /* Disable modulation stages */ - EUSCI->MCTLW &= ~(EUSCI_A_MCTLW_BRS_MASK | - EUSCI_A_MCTLW_BRF_MASK | - EUSCI_A_MCTLW_OS16); - /* Disable interrupts */ - EUSCI->IE = 0; - /* enable the UART module again */ - EUSCI->CTLW0 &= ~EUSCI_A_CTLW0_SWRST; - /* Set default baud rate */ - serial_baud(obj, 9600); - /* Copy config to stdio structure if needed */ - if (stdio_config) { - memcpy(&stdio_uart, obj, sizeof(serial_t)); - stdio_uart_inited = 1; - } -} - -/** Release the serial peripheral, not currently invoked. It requires further - * resource management. - * - * @param obj The serial object - */ -void serial_free(serial_t *obj) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - /* Wait for pending operations */ - while (EUSCI->STATW & EUSCI_A_STATW_BUSY); - /* Put UART to reset state */ - EUSCI->CTLW0 = EUSCI_A_CTLW0_SWRST; - /* De-configure the RX/TX lines */ - pin_function(objs->pin_tx, MSP432_PIN_DATA(SEL0, PIN_INPUT, PullNone, 0)); - pin_function(objs->pin_rx, MSP432_PIN_DATA(SEL0, PIN_INPUT, PullNone, 0)); -} - -/** Configure the baud rate - * - * @param obj The serial object - * @param baudrate The baud rate to be configured - */ -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - EUSCI->BRW = (uint16_t)(SubsystemMasterClock / baudrate); -} - -/** Configure the format. Set the number of bits, parity and the number of stop bits - * - * @param obj The serial object - * @param data_bits The number of data bits - * @param parity The parity - * @param stop_bits The number of stop bits - */ -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - /* put module in reset state */ - EUSCI->CTLW0 |= EUSCI_A_CTLW0_SWRST; - /* Configure data bits */ - switch (data_bits) { - case 7: - EUSCI->CTLW0 |= EUSCI_A_CTLW0_SEVENBIT; - break; - case 8: - EUSCI->CTLW0 &= ~EUSCI_A_CTLW0_SEVENBIT; - break; - default: - error("Unsupported UART data-bit size"); - } - /* Configure parity */ - switch (parity) { - case ParityNone: - EUSCI->CTLW0 &= ~EUSCI_A_CTLW0_PEN; - break; - case ParityOdd: - EUSCI->CTLW0 |= EUSCI_A_CTLW0_PEN; - EUSCI->CTLW0 &= ~EUSCI_A_CTLW0_PAR; - break; - case ParityEven: - EUSCI->CTLW0 |= EUSCI_A_CTLW0_PEN; - EUSCI->CTLW0 |= EUSCI_A_CTLW0_PAR; - break; - case ParityForced1: - case ParityForced0: - default: - error("Unsupported UART parity selection"); - } - /* Configure stop bits */ - switch (data_bits) { - case 1: - EUSCI->CTLW0 &= ~EUSCI_A_CTLW0_SPB; - break; - case 2: - EUSCI->CTLW0 |= EUSCI_A_CTLW0_SPB; - break; - default: - error("Unsupported UART stop-bit size"); - } - /* re-enable the UART module */ - EUSCI->CTLW0 &= ~EUSCI_A_CTLW0_SWRST; -} - -/** The serial interrupt handler registration - * - * @param obj The serial object - * @param handler The interrupt handler which will be invoked when the interrupt fires - * @param id The SerialBase object - */ -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - struct serial_s *objs = SERIAL_S(obj); - uart_handler = handler; - /* UART base addresses are - * EUSCI_A0 0x40001000 - * EUSCI_A1 0x40001400 - * EUSCI_A2 0x40001800 - * EUSCI_A3 0x40001c00 */ - uint8_t index = (((uint32_t)(objs->uart)) >> 10) & 0x3; - serial_irq_ids[index] = id; - /* Enable the NVIC irq for this UART */ - NVIC_EnableIRQ((IRQn_Type)(EUSCIA0_IRQn + index)); -} - -/** Configure serial interrupt. This function is used for word-approach - * - * @param obj The serial object - * @param irq The serial IRQ type (RX or TX) - * @param enable Set to non-zero to enable events, or zero to disable them - */ -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - switch (irq) { - case RxIrq: - BITBAND_PERI(EUSCI->IE, EUSCI_A_IE_RXIE_OFS) = enable; - break; - case TxIrq: - BITBAND_PERI(EUSCI->IE, EUSCI_A_IE_TXIE_OFS) = enable; - break; - } -} - -/** Get character. This is a blocking call, waiting for a character - * - * @param obj The serial object - */ -int serial_getc(serial_t *obj) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - /* Wait until the RX Buffer is filled.... */ - while ((EUSCI->IFG & EUSCI_A_IFG_RXIFG) == 0); - /*Transfer single char from RX buffer */ - return EUSCI->RXBUF; -} - -/** Send a character. This is a blocking call, waiting for a peripheral to be available - * for writing - * - * @param obj The serial object - * @param c The character to be sent - */ -void serial_putc(serial_t *obj, int c) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - /* Wait until the TX Buffer is empty.... */ - while ((EUSCI->IFG & EUSCI_A_IFG_TXIFG) == 0); - /* Transfer single char to TX buffer */ - EUSCI->TXBUF = (uint16_t)c; -} - -/** Check if the serial peripheral is readable - * - * @param obj The serial object - * @return Non-zero value if a character can be read, 0 if nothing to read - */ -int serial_readable(serial_t *obj) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - return EUSCI->IFG & EUSCI_A_IFG_RXIFG; -} - -/** Check if the serial peripheral is writable - * - * @param obj The serial object - * @return Non-zero value if a character can be written, 0 otherwise. - */ -int serial_writable(serial_t *obj) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - return EUSCI->IFG & EUSCI_A_IFG_TXIFG; -} - -/** Clear the serial peripheral - * - * @param obj The serial object - */ -void serial_clear(serial_t *obj) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - /* Clear all flags */ - EUSCI->IFG = 0; -} - -/** Set the break - * - * @param obj The serial object - */ -void serial_break_set(serial_t *obj) -{ - struct serial_s *objs = SERIAL_S(obj); - /* Get the UART base */ - EUSCI_A_Type *EUSCI = (EUSCI_A_Type *)objs->uart; - /* Wait until the TX Buffer is empty.... */ - while ((EUSCI->IFG & EUSCI_A_IFG_TXIFG) == 0); - /* Send break (automatically cleared) */ - EUSCI->CTLW0 |= EUSCI_A_CTLW0_TXBRK; -} - -/** Clear the break - * - * @param obj The serial object - */ -void serial_break_clear(serial_t *obj) -{ - /* Not needed because break flag is automatically cleared */ -} - -/** Configure the TX pin for UART function. - * - * @param tx The pin name used for TX - */ -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -/** Configure the serial for the flow control. It sets flow control in the hardware - * if a serial peripheral supports it, otherwise software emulation is used. - * - * @param obj The serial object - * @param type The type of the flow control. Look at the available FlowControl types. - * @param rxflow The TX pin name - * @param txflow The RX pin name - */ -//void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -//{ -// /* not used so far */ -//} - -/** Get the pins that support Serial TX - * - * Return a PinMap array of pins that support Serial TX. The - * array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *serial_tx_pinmap(void) -{ - return PinMap_UART_TX; -} - -/** Get the pins that support Serial RX - * - * Return a PinMap array of pins that support Serial RX. The - * array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *serial_rx_pinmap(void) -{ - return PinMap_UART_RX; -} - -/**************************/ -/* UART interrupt handler */ -/**************************/ -void handle_UART_Interrupt(uint8_t index, uint8_t vector) -{ - if (uart_handler) { - switch (vector) { - case 2: - uart_handler(serial_irq_ids[index], RxIrq); - break; - case 4: - uart_handler(serial_irq_ids[index], TxIrq); - break; - } - } -} - -void EUSCIA0_UART_IRQHandler(void) -{ - handle_UART_Interrupt(0, EUSCI_A0->IV); -} -void EUSCIA1_UART_IRQHandler(void) -{ - handle_UART_Interrupt(1, EUSCI_A1->IV); -} -void EUSCIA2_UART_IRQHandler(void) -{ - handle_UART_Interrupt(2, EUSCI_A2->IV); -} -void EUSCIA3_UART_IRQHandler(void) -{ - handle_UART_Interrupt(3, EUSCI_A3->IV); -} - -#endif /* DEVICE_SERIAL */ - diff --git a/targets/TARGET_TI/TARGET_MSP432/spi_api.c b/targets/TARGET_TI/TARGET_MSP432/spi_api.c deleted file mode 100644 index 27d384f1467..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/spi_api.c +++ /dev/null @@ -1,635 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Low-level implementation of SPI functionality for MSP432. - * This implementation does also support DEVICE_SPISLAVE and DEVICE_SPI_ASYNCH. - */ - -#include "spi_api.h" -#include "mbed_assert.h" - -#if DEVICE_SPI - -/* With SPI_ASYNCH, our type spi_s is embedded - * into a bigger structure (see spi_api.h). So we - * need a macro to extract the spi_s object. - */ -#if DEVICE_SPI_ASYNCH -#define SPI_S(obj) (&((obj)->spi)) -#else -#define SPI_S(obj) (obj) -#endif - -#if DEVICE_SPI_ASYNCH -// Array with object pointers for ISR -spi_t *spi_objects[8] = {0}; -#endif - -/** - * Returns a variant of the SPIName enum uniquely identifying a SPI peripheral of the device. - * @param[in] mosi The pin to use for MOSI - * @param[in] miso The pin to use for MISO - * @param[in] sclk The pin to use for SCLK - * @return An SPI peripheral identifier - */ -SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) -{ - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - - SPIName spi_per, spi_data; - // miso or mosi might be NC (3 wire SPI) - spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - MBED_ASSERT(spi_data != (SPIName)NC); - spi_per = (SPIName)pinmap_merge(spi_data, spi_sclk); - return spi_per; -} - -/** Initialize the SPI peripheral - * - * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral - * @param[out] obj The SPI object to initialize - * @param[in] mosi The pin to use for MOSI - * @param[in] miso The pin to use for MISO - * @param[in] sclk The pin to use for SCLK - * @param[in] ssel The pin to use for SSEL - */ -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - struct spi_s *objs = SPI_S(obj); - // Get the SPI peripheral - objs->spi = spi_get_peripheral_name(mosi, miso, sclk); - // Check if SSEL/CS fits - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - objs->spi = pinmap_merge(objs->spi, spi_ssel); - MBED_ASSERT(objs->spi != (SPIName)NC); - // Get the type of EUSCI interface (Type A or B) - objs->module = GET_DATA_CHAN(pinmap_function(mosi, PinMap_SPI_MOSI)); - // Set register addresses - if (objs->module < 4) { - // Get the SPI base - EUSCI_A_SPI_Type *EUSCI = (EUSCI_A_SPI_Type *)objs->spi; - objs->EUSCI_CTLW0 = &EUSCI->CTLW0; - objs->EUSCI_BRW = &EUSCI->BRW; - objs->EUSCI_STATW = &EUSCI->STATW; - objs->EUSCI_RXBUF = &EUSCI->RXBUF; - objs->EUSCI_TXBUF = &EUSCI->TXBUF; - objs->EUSCI_IE = &EUSCI->IE; - objs->EUSCI_IFG = &EUSCI->IFG; - objs->EUSCI_IV = &EUSCI->IV; - } else { - // Get the SPI base - EUSCI_B_SPI_Type *EUSCI = (EUSCI_B_SPI_Type *)objs->spi; - objs->EUSCI_CTLW0 = &EUSCI->CTLW0; - objs->EUSCI_BRW = &EUSCI->BRW; - objs->EUSCI_STATW = &EUSCI->STATW; - objs->EUSCI_RXBUF = &EUSCI->RXBUF; - objs->EUSCI_TXBUF = &EUSCI->TXBUF; - objs->EUSCI_IE = &EUSCI->IE; - objs->EUSCI_IFG = &EUSCI->IFG; - objs->EUSCI_IV = &EUSCI->IV; - } - /* Configure SPI pins */ - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - pinmap_pinout(ssel, PinMap_SPI_SSEL); - // Store pins in SPI object - objs->pin_miso = miso; - objs->pin_mosi = mosi; - objs->pin_sclk = sclk; - objs->pin_ssel = ssel; - /* Put EUSCI to reset state */ - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_SWRST_OFS) = 1; - /* Configure basic SPI mode */ - uint16_t ctlw0; - if (ssel == (PinName)NC) { - ctlw0 = EUSCI_B_CTLW0_MODE_0; // 3 pin SPI mode - } else { - ctlw0 = EUSCI_B_CTLW0_MODE_2 | // 4 pin SPI mode - EUSCI_A_CTLW0_STEM; // use STE as SSEL/CS - } - ctlw0 |= EUSCI_A_CTLW0_MSB | // MSB first - EUSCI_A_CTLW0_SYNC | // SYNC mode (SPI) - EUSCI_B_CTLW0_SSEL__SMCLK; // SMCLK as clock source - - *(objs->EUSCI_CTLW0) = ctlw0; - // Set SPI clock to default 1 MHz */ - spi_frequency(obj, 1000000); - // Disable and clear interrupts - *(objs->EUSCI_IE) = 0; - *(objs->EUSCI_IFG) = 0; - // Clear the EUSCI reset state (enable module) - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_SWRST_OFS) = 0; - -#if DEVICE_SPI_ASYNCH - // Store the object pointer for the ISR - spi_objects[objs->module] = obj; - objs->active = false; - /* Enable the NVIC irq for this SPI module */ - NVIC_EnableIRQ((IRQn_Type)(EUSCIA0_IRQn + objs->module)); -#endif -} - -/** Release a SPI object - * - * TODO: spi_free is currently unimplemented - * This will require reference counting at the C++ level to be safe - * - * Return the pins owned by the SPI object to their reset state - * Disable the SPI peripheral - * Disable the SPI clock - * @param[in] obj The SPI object to deinitialize - */ -void spi_free(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - // Put EUSCI to reset state - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_SWRST_OFS) = 1; - // Put pins to default state - int pin_data = MSP432_PIN_DATA(SEL0, PIN_INPUT, PullNone, 0); - pin_function(objs->pin_miso, pin_data); - pin_function(objs->pin_mosi, pin_data); - pin_function(objs->pin_sclk, pin_data); - pin_function(objs->pin_ssel, pin_data); -} - -/** Configure the SPI format - * - * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. - * The default bit order is MSB. - * @param[in,out] obj The SPI object to configure - * @param[in] bits The number of bits per frame - * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) - * @param[in] slave Zero for master mode or non-zero for slave mode - */ -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - struct spi_s *objs = SPI_S(obj); - // Put the EUSCI to reset state - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_SWRST_OFS) = 1; - // Set bit size - MBED_ASSERT((bits >= 7) && (bits <= 8)); - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_SEVENBIT_OFS) = (bits == 7); - // Set SPI clock polarity - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_CKPL_OFS) = (mode >> 1); - // Set SPI clock phase - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_CKPH_OFS) = (mode ^ 1); - // Set master/slave mode - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_MST_OFS) = !slave; - // Clear the EUSCI reset state (enable module) - BITBAND_PERI(*(objs->EUSCI_CTLW0), EUSCI_B_CTLW0_SWRST_OFS) = 0; -} - -/** Set the SPI baud rate - * - * Actual frequency may differ from the desired frequency due to available dividers and bus clock - * Configures the SPI peripheral's baud rate - * @param[in,out] obj The SPI object to configure - * @param[in] hz The baud rate in Hz - */ -void spi_frequency(spi_t *obj, int hz) -{ - struct spi_s *objs = SPI_S(obj); - *(objs->EUSCI_BRW) = SubsystemMasterClock / hz; -} - -/** Write a byte out in master mode and receive a value - * - * @param[in] obj The SPI peripheral to use for sending - * @param[in] value The value to send - * @return Returns the value received during send - */ -int spi_master_write(spi_t *obj, int value) -{ - struct spi_s *objs = SPI_S(obj); - *(objs->EUSCI_IFG) = 0; - *(objs->EUSCI_STATW) = 0; - /* Place character in buffer */ - *(objs->EUSCI_TXBUF) = value; - // Wait until byte has been received - while (!BITBAND_PERI(*(objs->EUSCI_IFG), EUSCI_B_IFG_RXIFG_OFS)); - return *(objs->EUSCI_RXBUF); -} - -/** Write a block out in master mode and receive a value - * - * The total number of bytes sent and received will be the maximum of - * tx_length and rx_length. The bytes written will be padded with the - * value 0xff. - * - * @param[in] obj The SPI peripheral to use for sending - * @param[in] tx_buffer Pointer to the byte-array of data to write to the device - * @param[in] tx_length Number of bytes to write, may be zero - * @param[in] rx_buffer Pointer to the byte-array of data to read from the device - * @param[in] rx_length Number of bytes to read, may be zero - * @param[in] write_fill Default data transmitted while performing a read - * @returns - * The number of bytes written and read from the device. This is - * maximum of tx_length and rx_length. - */ -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, - char write_fill) -{ - struct spi_s *objs = SPI_S(obj); - // Clear interrupt status - *(objs->EUSCI_IFG) = 0; - *(objs->EUSCI_STATW) = 0; - // Calculate maximum transfer length - int i, total = (tx_length > rx_length) ? tx_length : rx_length; - for (i = 0; i < total; i++) { - // Place character in buffer - *(objs->EUSCI_TXBUF) = (i < tx_length) ? tx_buffer[i] : write_fill; - // Wait until byte has been received - while (!BITBAND_PERI(*(objs->EUSCI_IFG), EUSCI_B_IFG_RXIFG_OFS)); - // Fill receive buffer - if (i < rx_length) { - rx_buffer[i] = *(objs->EUSCI_RXBUF); - } - } - return total; -} - - -/** Checks if the specified SPI peripheral is in use - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if the peripheral is currently transmitting - */ -int spi_busy(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - return *(objs->EUSCI_STATW) & EUSCI_B_STATW_SPI_BUSY; -} - -/** Get the module number - * - * @param[in] obj The SPI peripheral to check - * @return The module number - */ -uint8_t spi_get_module(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - return objs->module; -} - -/** Get the pins that support SPI MOSI - * - * Return a PinMap array of pins that support SPI MOSI in - * master mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *spi_master_mosi_pinmap(void) -{ - return PinMap_SPI_MOSI; -} - -/** Get the pins that support SPI MISO - * - * Return a PinMap array of pins that support SPI MISO in - * master mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *spi_master_miso_pinmap(void) -{ - return PinMap_SPI_MISO; -} - -/** Get the pins that support SPI CLK - * - * Return a PinMap array of pins that support SPI CLK in - * master mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *spi_master_clk_pinmap(void) -{ - return PinMap_SPI_SCLK; -} - -/** Get the pins that support SPI CS - * - * Return a PinMap array of pins that support SPI CS in - * master mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *spi_master_cs_pinmap(void) -{ - return PinMap_SPI_SSEL; -} - -#if DEVICE_SPISLAVE - -/** Check if a value is available to read - * - * @param[in] obj The SPI peripheral to check - * @return non-zero if a value is available - */ -int spi_slave_receive(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - return BITBAND_PERI(*(objs->EUSCI_IFG), EUSCI_B_IFG_RXIFG_OFS); -} - -/** Get a received value out of the SPI receive buffer in slave mode - * - * Blocks until a value is available - * @param[in] obj The SPI peripheral to read - * @return The value received - */ -int spi_slave_read(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - while (!BITBAND_PERI(*(objs->EUSCI_IFG), EUSCI_B_IFG_RXIFG_OFS)) ; - return *(objs->EUSCI_RXBUF); -} - -/** Write a value to the SPI peripheral in slave mode - * - * Blocks until the SPI peripheral can be written to - * @param[in] obj The SPI peripheral to write - * @param[in] value The value to write - */ -void spi_slave_write(spi_t *obj, int value) -{ - struct spi_s *objs = SPI_S(obj); - while (!BITBAND_PERI(*(objs->EUSCI_IFG), EUSCI_B_IFG_TXIFG_OFS)) ; - *(objs->EUSCI_TXBUF) = value; -} - -/** Get the pins that support SPI MOSI - * - * Return a PinMap array of pins that support SPI MOSI in - * slave mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *spi_slave_mosi_pinmap(void) -{ - return PinMap_SPI_MOSI; -} - -/** Get the pins that support SPI MISO - * - * Return a PinMap array of pins that support SPI MISO in - * slave mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *spi_slave_miso_pinmap(void) -{ - return PinMap_SPI_MISO; -} - -/** Get the pins that support SPI CLK - * - * Return a PinMap array of pins that support SPI CLK in - * slave mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *spi_slave_clk_pinmap(void) -{ - return PinMap_SPI_SCLK; -} - -/** Get the pins that support SPI CS - * - * Return a PinMap array of pins that support SPI CS in - * slave mode. The array is terminated with {NC, NC, 0}. - * - * @return PinMap array - */ -const PinMap *spi_slave_cs_pinmap(void) -{ - return PinMap_SPI_SSEL; -} - -#endif // DEVICE_SPISLAVE - -#if DEVICE_SPI_ASYNCH -/** - * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer - * @{ - */ - -/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff - * - * @param[in] obj The SPI object that holds the transfer information - * @param[in] tx The transmit buffer - * @param[in] tx_length The number of bytes to transmit - * @param[in] rx The receive buffer - * @param[in] rx_length The number of bytes to receive - * @param[in] bit_width The bit width of buffer words - * @param[in] event The logical OR of events to be registered - * @param[in] handler SPI interrupt handler - * @param[in] hint A suggestion for how to use DMA with this transfer - */ -void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, - uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ - // We ignore DMA for now - (void) hint; - - struct spi_s *objs = SPI_S(obj); - - // Update object - obj->tx_buff.buffer = (void *)tx; - obj->tx_buff.length = tx_length; - obj->tx_buff.pos = 0; - obj->tx_buff.width = bit_width; - - obj->rx_buff.buffer = (void *)rx; - obj->rx_buff.length = rx_length; - obj->rx_buff.pos = 0; - obj->rx_buff.width = bit_width; - - objs->handler = (void (*)(void))handler; - objs->event = 0; - objs->available_events = event; - - // Start the ball rolling by enabling TX/RX interrupts - uint16_t ie = 0; - if (tx_length) { - ie |= EUSCI_B_IE_TXIE; - } - if (rx_length) { - ie |= EUSCI_B_IE_RXIE; - } - if (ie) { - objs->active = true; - *(objs->EUSCI_IE) = ie; - } -} - -/** The asynchronous IRQ handler - * - * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination - * conditions, such as buffer overflows or transfer complete. - * @param[in] obj The SPI object that holds the transfer information - * @return Event flags if a transfer termination condition was met; otherwise 0. - */ -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - return (objs->event & objs->available_events); -} - -/** Attempts to determine if the SPI peripheral is already in use - * - * If a temporary DMA channel has been allocated, peripheral is in use. - * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA - * channel were allocated. - * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check - * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if - * there are any bytes in the FIFOs. - * @param[in] obj The SPI object to check for activity - * @return Non-zero if the SPI port is active or zero if it is not. - */ -uint8_t spi_active(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - return objs->active; -} - -/** Abort an SPI transfer - * - * @param obj The SPI peripheral to stop - */ -void spi_abort_asynch(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - *(objs->EUSCI_IE) = 0; - *(objs->EUSCI_IFG) = 0; - objs->active = false; -} - -/*************************/ -/* SPI interrupt handler */ -/*************************/ -void handle_SPI_Interrupt(spi_t *obj) -{ - struct spi_s *objs = SPI_S(obj); - -#if 0 - uint16_t ifg = *(objs->EUSCI_IFG); - if (ifg & EUSCI_B_IFG_RXIFG) { - struct buffer_s *rx_buff = &obj->rx_buff; - if (rx_buff->pos < rx_buff->length) { - ((uint8_t *)rx_buff->buffer)[rx_buff->pos] = *(objs->EUSCI_RXBUF); - rx_buff->pos++; - } - if (rx_buff->pos >= rx_buff->length) { - // Disable RX interrupts - *(objs->EUSCI_IE) &= ~EUSCI_B_IE_RXIE; - } - } - if (ifg & EUSCI_B_IFG_TXIFG) { - struct buffer_s *tx_buff = &obj->tx_buff; - if (tx_buff->pos < tx_buff->length) { - *(objs->EUSCI_TXBUF) = ((uint8_t *)tx_buff->buffer)[tx_buff->pos]; - tx_buff->pos++; - } else { - // Disable interrupts - *(objs->EUSCI_IE) = 0; - objs->active = false; - objs->event = SPI_EVENT_COMPLETE; - objs->handler(); - } - } -#endif - - uint16_t vector = *(objs->EUSCI_IV); - - switch (vector) { - /* UCRXIFG */ - case 0x02: { - struct buffer_s *rx_buff = &obj->rx_buff; - if (*(objs->EUSCI_STATW) & EUSCI_B_STATW_OE) { - objs->event = SPI_EVENT_RX_OVERFLOW; - objs->handler(); - } - if (rx_buff->pos < rx_buff->length) { - ((uint8_t *)rx_buff->buffer)[rx_buff->pos] = *(objs->EUSCI_RXBUF); - rx_buff->pos++; - } - if (rx_buff->pos >= rx_buff->length) { - // Disable RX interrupts - *(objs->EUSCI_IE) &= ~EUSCI_B_IE_RXIE; - } - break; - } - /* UCTXIFG */ - case 0x04: { - struct buffer_s *tx_buff = &obj->tx_buff; - if (tx_buff->pos < tx_buff->length) { - *(objs->EUSCI_TXBUF) = ((uint8_t *)tx_buff->buffer)[tx_buff->pos]; - tx_buff->pos++; - } else { - // Disable interrupts - *(objs->EUSCI_IE) = 0; - objs->active = false; - objs->event = SPI_EVENT_COMPLETE; - objs->handler(); - } - break; - } - } -} - -void EUSCIA0_SPI_IRQHandler(void) -{ - handle_SPI_Interrupt(spi_objects[0]); -} -void EUSCIA1_SPI_IRQHandler(void) -{ - handle_SPI_Interrupt(spi_objects[1]); -} -void EUSCIA2_SPI_IRQHandler(void) -{ - handle_SPI_Interrupt(spi_objects[2]); -} -void EUSCIA3_SPI_IRQHandler(void) -{ - handle_SPI_Interrupt(spi_objects[3]); -} -void EUSCIB0_SPI_IRQHandler(void) -{ - handle_SPI_Interrupt(spi_objects[4]); -} -void EUSCIB1_SPI_IRQHandler(void) -{ - handle_SPI_Interrupt(spi_objects[5]); -} -void EUSCIB2_SPI_IRQHandler(void) -{ - handle_SPI_Interrupt(spi_objects[6]); -} -void EUSCIB3_SPI_IRQHandler(void) -{ - handle_SPI_Interrupt(spi_objects[7]); -} - -#endif // DEVICE_SPI_ASYNCH - -#endif // DEVICE_SPI - diff --git a/targets/TARGET_TI/TARGET_MSP432/us_ticker_api.c b/targets/TARGET_TI/TARGET_MSP432/us_ticker_api.c deleted file mode 100644 index 77343a85434..00000000000 --- a/targets/TARGET_TI/TARGET_MSP432/us_ticker_api.c +++ /dev/null @@ -1,115 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Low-level implementation of the us ticker for MSP432. The Timer32 - * modules can not be used for this purpose, because they do not - * generate irqs in free-running mode. So the only remaing choice - * are the Timer A modules, which are only 16 bit, but support irqs - * when operated in continuous mode. Timer A3 is choosen here, which - * could be made configurable in the future. - * - * See hal/us_ticker_api.h for a detailed description of the following - * functions. - */ - -#if DEVICE_USTICKER - -#include -#include "us_ticker_api.h" -#include "mbed_assert.h" - -extern void us_ticker_irq_handler(void); - -void us_ticker_init(void) -{ - // Calculate the Timer A divisors (shift and remainder) - uint32_t prescale = SubsystemMasterClock / 1000000; - int shifts = 0; - for (shifts = 0; shifts < 3; shifts++) { - if (prescale & 0x1) { - break; - } else { - prescale >>= 1; - } - } - - // Check that we have at least a 1MHz clock - MBED_ASSERT(prescale && (prescale < 9)); - - // initialize the registers and set prescalers - TIMER_A3->CTL = (shifts << TIMER_A_CTL_ID_OFS) | - TIMER_A_CTL_SSEL__SMCLK | - TIMER_A_CTL_MC__CONTINUOUS; - TIMER_A3->CCTL[0] = 0; - TIMER_A3->EX0 = prescale - 1; - - // enable IRQ in NVIC - NVIC_EnableIRQ(TA3_0_IRQn); -} - -void us_ticker_free(void) -{ - // Reset the ctrl registers to default value - TIMER_A3->CTL = 0; - TIMER_A3->CCTL[0] = 0; - - // Disable timer interrupt - NVIC_DisableIRQ(TA3_0_IRQn); -} - -uint32_t us_ticker_read(void) -{ - return TIMER_A3->R; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - TIMER_A3->CCR [0] = timestamp; - TIMER_A3->CCTL[0] = TIMER_A_CCTLN_CCIE; -} - -void us_ticker_disable_interrupt(void) -{ - TIMER_A3->CCTL[0] &= ~TIMER_A_CCTLN_CCIE; -} - -void us_ticker_clear_interrupt(void) -{ - TIMER_A3->CCTL[0] &= ~TIMER_A_CCTLN_CCIFG; -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(TA3_0_IRQn); -} - -const ticker_info_t *us_ticker_get_info(void) -{ - static const ticker_info_t info = { - 1000000, // 1 MHz - 16 // 16 bit counter - }; - return &info; -} - -/* Timer_A3 interrupt handler */ -void TA3_0_IRQHandler() -{ - us_ticker_irq_handler(); -} - -#endif /* DEVICE_USTICKER */ diff --git a/targets/TARGET_TI/mbed_rtx.h b/targets/TARGET_TI/mbed_rtx.h deleted file mode 100644 index 1ebae061ae0..00000000000 --- a/targets/TARGET_TI/mbed_rtx.h +++ /dev/null @@ -1,36 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - -#include - -#ifndef INITIAL_SP - -#if defined(TARGET_CC3220SF) -#define INITIAL_SP (0x20040000UL) - -#elif defined(TARGET_MSP432P401R) -#define INITIAL_SP (0x20010000UL) - -#else -#error "INITIAL_SP is not defined for this target in the mbed_rtx.h file" -#endif - -#endif // INITIAL_SP - -#endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h deleted file mode 100644 index f9c8c5377a1..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h +++ /dev/null @@ -1,163 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SERIAL_0 = 0, - SERIAL_1, - SERIAL_2, - SERIAL_3, - SERIAL_4, - SERIAL_5, - INVALID_SERIAL = (int)NC -} UARTName; - -typedef enum { - ADC_AINA00 = 0, - ADC_AINA01, - ADC_AINA02, - ADC_AINA03, - ADC_AINA04, - ADC_AINA05, - ADC_AINA06, - ADC_AINA07, - ADC_AINA08, - ADC_AINA09, - ADC_AINA10, - ADC_AINA11, - ADC_AINA12, - ADC_AINA13, - ADC_AINA14, - ADC_AINA15, - ADC_AINA16, - ADC_AINA17, - ADC_AINA18, - ADC_AINA19, - ADC_AINA20, - INVALID_ADC = (int)NC -} ADCName; - -typedef enum { - DAC_A0 = 0, - DAC_A1, - INVALID_DAC = (int)NC -} DACName; - -typedef enum { - SPI_0 = 0, - SPI_1, - SPI_2, - SPI_3, - SPI_4, - INVALID_SPI = (int)NC -} SPIName; - -typedef enum { - I2C_0 = 0, - I2C_1, - I2C_2, - I2C_3, - INVALID_I2C = (int)NC -} I2CName; - -typedef enum { - PWM_0 = 0, - PWM_1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - INVALID_PWM = (int)NC -} PWMName; - -typedef enum { - GPIO_IRQ_00 = 0, - GPIO_IRQ_01, - GPIO_IRQ_02, - GPIO_IRQ_03, - GPIO_IRQ_04, - GPIO_IRQ_05, - GPIO_IRQ_06, - GPIO_IRQ_07, - GPIO_IRQ_08, - GPIO_IRQ_09, - GPIO_IRQ_10, - GPIO_IRQ_11, - GPIO_IRQ_12, - GPIO_IRQ_13, - GPIO_IRQ_14, - GPIO_IRQ_15, - GPIO_IRQ_16, - GPIO_IRQ_17_18, - GPIO_IRQ_19_22, - GPIO_IRQ_23_26, - GPIO_IRQ_27_28, - GPIO_IRQ_29, - GPIO_IRQ_30_31, - INVALID_GPIO_IRQ = (int)NC -} gpio_irqname; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART SERIAL_1 - -#define MBED_SPI0 PA1, PA2, PA0, PA4 -#define MBED_SPI1 PB3, PB4, PB2, PB5 -#define MBED_SPI2 PT3, PT4, PT2, PT1 -#define MBED_SPI3 PP4, PP3, PP5, PP6 -#define MBED_SPI4 PH5, PH6, PH4, PH0 - -#define MBED_UART0 PA1, PA2 -#define MBED_UART1 PJ1, PJ2 -#define MBED_UART2 PB2, PB3 -#define MBED_UART3 PA7, PA6 -#define MBED_UART4 PC4, PC5 -#define MBED_UART5 PN2, PN3 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 PC1, PC0 -#define MBED_I2C1 PA5, PA4 -#define MBED_I2C2 PL1, PL0 -#define MBED_I2C3 PT0, PT1 - -#define MBED_ANALOGIN0 A0 -#define MBED_ANALOGIN1 A1 -#define MBED_ANALOGIN2 A2 -#define MBED_ANALOGIN3 A3 -#define MBED_ANALOGIN4 A4 -#define MBED_ANALOGIN5 A5 - -#define MBED_PWMOUT0 PB0 -#define MBED_PWMOUT1 PC0 -#define MBED_PWMOUT2 PJ0 -#define MBED_PWMOUT3 PK2 -#define MBED_PWMOUT4 PN0 -#define MBED_PWMOUT5 PL5 -#define MBED_PWMOUT6 PG2 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h deleted file mode 100644 index e966a4f5fd7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0x1F) -#define PIN_POS(X) ((uint32_t)(X) & 0x7) - -// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction -#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0)) -#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) -#define PIN_DIR(X) ((X) & 0xffff) - -#define GPIO_NUM (15U) // total number of gpio -#define FRMAX (7U) -#define RESER (8U - (FRMAX)) - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INOUT -} PinDirection; - -typedef enum { - // TMPM3HQ Pin Names - PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, - PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, - PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, - PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, - PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, - PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, - PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, - PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, - PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, - PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, - PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, - PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, - PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, PT6, PT7, - PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, - PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, - - // Other mbed Pin Names - LED0 = PK4, - LED1 = PK5, - LED2 = PK6, - LED3 = PK7, - - // External data bus Pin Names - D0 = PG3, - D1 = PG4, - D2 = PG5, - D3 = PG2, - D4 = PG6, - D5 = PA0, - D6 = PL5, - D7 = PL6, - D8 = PT0, - D9 = PP0, - D10 = PT1, - D11 = PT3, - D12 = PT4, - D13 = PT2, - D14 = PA5, - D15 = PA4, - - DAC0 = PG0, - DAC1 = PG1, - // Analogue out pins - A0 = PF7, - A1 = PF6, - A2 = PF5, - A3 = PF4, - A4 = PF3, - A5 = PF2, - - // DAP_UART - USBTX = PJ1, - USBRX = PJ2, - MBEDIF_TXD = USBTX, - MBEDIF_RXD = USBRX, - - // Switches - SW1 = PP6, //DIP switch J7_1 - SW2 = PP7, //DIP switch J7_2 - SW3 = (int)0xFFFFFFFF, //Reset Button - SW4 = PV3, //Push button S2 - USER_BUTTON = PV3, - - // I2C pins - SDA = D14, - SCL = D15, - I2C_SDA = SDA, - I2C_SCL = SCL, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 0, - PullDown, - PullNone, - OpenDrain, - PullDefault -} PinMode; - -typedef enum { - DISABLE = 0, - ENABLE -} FunctionalState; - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h deleted file mode 100644 index 84bcf0b3da8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, - PortC, - PortD, - PortE, - PortF, - PortG, - PortH, - PortJ, - PortK, - PortL, - PortM, - PortN, - PortP, - PortR, - PortT, - PortU, - PortV -} PortName; - -#define IS_GPIO_PORT(param) ((param) <= PortV) // parameter checking for port number - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c deleted file mode 100644 index e043e2611f0..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c +++ /dev/null @@ -1,119 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogin_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" -#include "gpio_include.h" - -static const PinMap PinMap_ADC[] = { - {PD0, ADC_AINA00, PIN_DATA(0, 0)}, - {PD1, ADC_AINA01, PIN_DATA(0, 0)}, - {PD2, ADC_AINA02, PIN_DATA(0, 0)}, - {PD3, ADC_AINA03, PIN_DATA(0, 0)}, - {PE0, ADC_AINA04, PIN_DATA(0, 0)}, - {PE1, ADC_AINA05, PIN_DATA(0, 0)}, - {PE2, ADC_AINA06, PIN_DATA(0, 0)}, - {PE3, ADC_AINA07, PIN_DATA(0, 0)}, - {PE4, ADC_AINA08, PIN_DATA(0, 0)}, - {PE5, ADC_AINA09, PIN_DATA(0, 0)}, - {PE6, ADC_AINA10, PIN_DATA(0, 0)}, - {PF0, ADC_AINA11, PIN_DATA(0, 0)}, - {PF1, ADC_AINA12, PIN_DATA(0, 0)}, - {PF2, ADC_AINA13, PIN_DATA(0, 0)}, - {PF3, ADC_AINA14, PIN_DATA(0, 0)}, - {PF4, ADC_AINA15, PIN_DATA(0, 0)}, - {PF5, ADC_AINA16, PIN_DATA(0, 0)}, - {PF6, ADC_AINA17, PIN_DATA(0, 0)}, - {PF7, ADC_AINA18, PIN_DATA(0, 0)}, - {PD4, ADC_AINA19, PIN_DATA(0, 0)}, - {PD5, ADC_AINA20, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -/** - * [analogin_init] - * @param obj - * @param pin - * @description Initialize analog input - */ -void analogin_init(analogin_t *obj, PinName pin) -{ - // Check that pin belong to ADC module - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - // Assert that ADC channel is valid - MBED_ASSERT(obj->adc != (ADCName)NC); - obj->obj = TSB_ADA; - // ADC CG Fsys Enable - TSB_CG_FSYSENB_IPENB15 = ENABLE; - // ADC Clock Enable - TSB_CG_SPCLKEN_ADCKEN = ENABLE; - // Set pin function as ADC - pinmap_pinout(pin, PinMap_ADC); - // Set sample hold time and pre-scale clock - obj->obj->CLK = (ADC_SCLK_1 | ADC_SAMPLING_PERIOD_3V); - obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); - obj->obj->MOD1 = ADC_MOD1_AVDD5_3V; - obj->obj->MOD2 = ADC_MOD2_TMPM3Hx; -} - -/** - * [analogin_read_u16] - * @param obj - * @return An unsigned short in the range [0x00, 0x0FFF] - * @description Read the ADC input - */ -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t ADCResultValue = 0; - uint32_t ADCResultStored = 0; - - // Wait at least 3us to ensure the voltage is stable - wait_us(300); - // ADC configuration for data Conversion - obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); - obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); - obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE - | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); - obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); - // Wait until AD conversion complete - while( (obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE); - // Wait for register to update with convert value - wait_us(30); - // Convert result - ADCResultStored = (obj->obj->REG0 | obj->adc); - if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { - ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4); - } - return ADCResultValue; -} - -/** - * [analogin_read] - * @param obj - * @return A float in the range [0.0, 1.0] - * @description Read the ADC input - */ -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return ((float)(value * (1.0f / (float)ADC_12BIT_RANGE))); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c deleted file mode 100644 index dbf4b385b99..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c +++ /dev/null @@ -1,109 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogout_api.h" -#include "PeripheralNames.h" -#include "mbed_wait_api.h" -#include "pinmap.h" - -#define DAC_START ((uint32_t)0x00000001) -#define DAC_STOP ((uint32_t)0x00000000) - -static const PinMap PinMap_DAC[] = { - {DAC0, DAC_A0, PIN_DATA(0, 3)}, - {DAC1, DAC_A1, PIN_DATA(0, 3)}, - {NC, NC, 0} -}; - -static void analogout_start(dac_t *obj) -{ - obj->handler->CTL = DAC_START; // Supply Vref and enable DAC -} - -void analogout_init(dac_t *obj, PinName pin) -{ - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module - MBED_ASSERT(obj->dac != (DACName)NC); - - pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC - TSB_CG_FSYSENA_IPENA06 = ENABLE; - if (obj->dac == DAC_A0) { // Compute handler - obj->handler = TSB_DA0; - TSB_CG_FSYSENB_IPENB17 = ENABLE; - } else { - if (obj->dac == DAC_A1) { - obj->handler = TSB_DA1; - TSB_CG_FSYSENB_IPENB18 = ENABLE; - } else { - obj->handler = NULL; - } - } - obj->handler->CTL = DAC_STOP; -} - -void analogout_free(dac_t *obj) -{ - obj->handler->CTL = DAC_STOP; -} - -void analogout_write(dac_t *obj, float value) -{ - uint8_t outputcode; - - analogout_start(obj); - - if (value < 0.0f) { - value = 0.0f; - } else { - if (value >= 1.0f) { - value = 1.0f; - } - } - outputcode = (uint8_t)(value * 255.0f); - obj->handler->REG = outputcode; - wait_ms(3); -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - analogout_start(obj); - obj->handler->REG = (uint8_t)(value & 0xFF); - wait_ms(3); -} - -float analogout_read(dac_t *obj) -{ - float result; - uint32_t value = 0; - - value = ((obj->handler->REG) & (0xFF)); - result = ((float)value / 255.0f); - - return result; -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - uint16_t value = 0; - - value = (uint16_t)((obj->handler->REG) & (0xFF)); - - return value; -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device.h deleted file mode 100644 index ff9910ab575..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device.h +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 32 - -#include "objects.h" - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h deleted file mode 100644 index 0aaef3e355f..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h +++ /dev/null @@ -1,4539 +0,0 @@ -/** - ******************************************************************************* - * @file TMPM3HQ.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM3HQ' Device Series - * @version V1.0.0.1 - * $Date:: 2017-12-27 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER - * @{ - */ - -/** @addtogroup TMPM3HQ - * @{ - */ - -#ifndef __TMPM3HQ_H__ -#define __TMPM3HQ_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** TMPM3HQ Specific Interrupt Numbers *******************************************************************/ - INT00_IRQn = 0, /*!< Interrupt Pin 00 */ - INT01_IRQn = 1, /*!< Interrupt Pin 01 */ - INT02_IRQn = 2, /*!< Interrupt Pin 02 */ - INT03_IRQn = 3, /*!< Interrupt Pin 03 */ - INT04_IRQn = 4, /*!< Interrupt Pin 04 */ - INT05_IRQn = 5, /*!< Interrupt Pin 05 */ - INT06_IRQn = 6, /*!< Interrupt Pin 06 */ - INT07_IRQn = 7, /*!< Interrupt Pin 07 */ - INT08_IRQn = 8, /*!< Interrupt Pin 08 */ - INT09_IRQn = 9, /*!< Interrupt Pin 09 */ - INT10_IRQn = 10, /*!< Interrupt Pin 10 */ - INT11_IRQn = 11, /*!< Interrupt Pin 11 */ - INT12_IRQn = 12, /*!< Interrupt Pin 12 */ - INT13_IRQn = 13, /*!< Interrupt Pin 13 */ - INT14_IRQn = 14, /*!< Interrupt Pin 14 */ - INT15_IRQn = 15, /*!< Interrupt Pin 15 */ - INT16_IRQn = 16, /*!< Interrupt Pin 16 */ - INT17_18_IRQn = 17, /*!< Interrupt Pin 17_18 */ - INT19_22_IRQn = 18, /*!< Interrupt Pin 19_22 */ - INT23_26_IRQn = 19, /*!< Interrupt Pin 23_26 */ - INT27_28_IRQn = 20, /*!< Interrupt Pin 27_28 */ - INT29_IRQn = 21, /*!< Interrupt Pin 29 */ - INT30_31_IRQn = 22, /*!< Interrupt Pin 30_31 */ - INTEMG0_IRQn = 23, /*!< PMD0 EMG interrupt */ - INTOVV0_IRQn = 24, /*!< PMD0 OVV interrupt */ - INTPMD0_IRQn = 25, /*!< PMD0 interrupt */ - INTENC00_IRQn = 26, /*!< Encoder 0 interrupt 0 */ - INTENC01_IRQn = 27, /*!< Encoder 0 interrupt 1 */ - INTADAPDA_IRQn = 28, /*!< ADC conversion triggered by PMD is finished A */ - INTADAPDB_IRQn = 29, /*!< ADC conversion triggered by PMD is finished B */ - INTADACP0_IRQn = 30, /*!< ADC conversion monitoring function interrupt 0 */ - INTADACP1_IRQn = 31, /*!< ADC conversion monitoring function interrupt 1 */ - INTADATRG_IRQn = 32, /*!< ADC conversion triggered by General purpose is finished */ - INTADASGL_IRQn = 33, /*!< ADC conversion triggered by Single program is finished */ - INTADACNT_IRQn = 34, /*!< ADC conversion triggered by Continuity program is finished */ - INTT0RX_IRQn = 35, /*!< TSPI/SIO reception (channel 0) */ - INTT0TX_IRQn = 36, /*!< TSPI/SIO transmit (channel 0) */ - INTT0ERR_IRQn = 37, /*!< TSPI/SIO error (channel 0) */ - INTT1RX_IRQn = 38, /*!< TSPI/SIO reception (channel 1) */ - INTT1TX_IRQn = 39, /*!< TSPI/SIO transmit (channel 1) */ - INTT1ERR_IRQn = 40, /*!< TSPI/SIO error (channel 1) */ - INTT2RX_IRQn = 41, /*!< TSPI/SIO reception (channel 2) */ - INTT2TX_IRQn = 42, /*!< TSPI/SIO transmit (channel 2) */ - INTT2ERR_IRQn = 43, /*!< TSPI/SIO error (channel 2) */ - INTT3RX_IRQn = 44, /*!< TSPI/SIO reception (channel 3) */ - INTT3TX_IRQn = 45, /*!< TSPI/SIO transmit (channel 3) */ - INTT3ERR_IRQn = 46, /*!< TSPI/SIO error (channel 3) */ - INTT4RX_IRQn = 47, /*!< TSPI/SIO reception (channel 4) */ - INTT4TX_IRQn = 48, /*!< TSPI/SIO transmit (channel 4) */ - INTT4ERR_IRQn = 49, /*!< TSPI/SIO error (channel 4) */ - INTI2CWUP_IRQn = 50, /*!< Serial bus interface (WakeUp) interrupt (channel 0) */ - INTI2C0_IRQn = 51, /*!< I2C0 transmission and reception interrupt */ - INTI2C0AL_IRQn = 52, /*!< I2C0 arbitration lost interrupt */ - INTI2C0BF_IRQn = 53, /*!< I2C0 bus free interrupt */ - INTI2C0NA_IRQn = 54, /*!< I2C0 no ack interrupt */ - INTI2C1_IRQn = 55, /*!< I2C1 transmission and reception interrupt */ - INTI2C1AL_IRQn = 56, /*!< I2C1 arbitration lost interrupt */ - INTI2C1BF_IRQn = 57, /*!< I2C1 bus free interrupt */ - INTI2C1NA_IRQn = 58, /*!< I2C1 no ack interrupt */ - INTI2C2_IRQn = 59, /*!< I2C2 transmission and reception interrupt */ - INTI2C2AL_IRQn = 60, /*!< I2C2 arbitration lost interrupt */ - INTI2C2BF_IRQn = 61, /*!< I2C2 bus free interrupt */ - INTI2C2NA_IRQn = 62, /*!< I2C2 no ack interrupt */ - INTI2C3_IRQn = 63, /*!< I2C3 transmission and reception interrupt */ - INTI2C3AL_IRQn = 64, /*!< I2C3 arbitration lost interrupt */ - INTI2C3BF_IRQn = 65, /*!< I2C3 bus free interrupt */ - INTI2C3NA_IRQn = 66, /*!< I2C3 no ack interrupt */ - INTUART0RX_IRQn = 67, /*!< UART reception (channel 0) */ - INTUART0TX_IRQn = 68, /*!< UART transmit (channel 0) */ - INTUART0ERR_IRQn = 69, /*!< UART error (channel 0) */ - INTUART1RX_IRQn = 70, /*!< UART reception (channel 1) */ - INTUART1TX_IRQn = 71, /*!< UART transmit (channel 1) */ - INTUART1ERR_IRQn = 72, /*!< UART error (channel 1) */ - INTUART2RX_IRQn = 73, /*!< UART reception (channel 2) */ - INTUART2TX_IRQn = 74, /*!< UART transmit (channel 2) */ - INTUART2ERR_IRQn = 75, /*!< UART error (channel 2) */ - INTUART3RX_IRQn = 76, /*!< UART reception (channel 3) */ - INTUART3TX_IRQn = 77, /*!< UART transmit (channel 3) */ - INTUART3ERR_IRQn = 78, /*!< UART error (channel 3) */ - INTUART4RX_IRQn = 79, /*!< UART reception (channel 4) */ - INTUART4TX_IRQn = 80, /*!< UART transmit (channel 4) */ - INTUART4ERR_IRQn = 81, /*!< UART error (channel 4) */ - INTUART5RX_IRQn = 82, /*!< UART reception (channel 5) */ - INTUART5TX_IRQn = 83, /*!< UART transmit (channel 5) */ - INTUART5ERR_IRQn = 84, /*!< UART error (channel 5) */ - INTT32A00A_IRQn = 85, /*!< 32bit T32A00A compare match detection 0 / Over flow / under flow*/ - INTT32A00ACAP0_IRQn = 86, /*!< 32bit T32A00A input capture 0 */ - INTT32A00ACAP1_IRQn = 87, /*!< 32bit T32A00A input capture 1 */ - INTT32A00B_IRQn = 88, /*!< 32bit T32A00B compare match detection 0 / Over flow / under flow*/ - INTT32A00BCAP0_IRQn = 89, /*!< 32bit T32A00B input capture 0 */ - INTT32A00BCAP1_IRQn = 90, /*!< 32bit T32A00B input capture 1 */ - INTT32A00C_IRQn = 91, /*!< 32bit T32A00C compare match detection 0 / Over flow / under flow*/ - INTT32A00CCAP0_IRQn = 92, /*!< 32bit T32A00C input capture 0 */ - INTT32A00CCAP1_IRQn = 93, /*!< 32bit T32A00C input capture 1 */ - INTT32A01A_IRQn = 94, /*!< 32bit T32A01A compare match detection 0 / Over flow / under flow*/ - INTT32A01ACAP0_IRQn = 95, /*!< 32bit T32A01A input capture 0 */ - INTT32A01ACAP1_IRQn = 96, /*!< 32bit T32A01A input capture 1 */ - INTT32A01B_IRQn = 97, /*!< 32bit T32A01B compare match detection 0 / Over flow / under flow*/ - INTT32A01BCAP0_IRQn = 98, /*!< 32bit T32A01B input capture 0 */ - INTT32A01BCAP1_IRQn = 99, /*!< 32bit T32A01B input capture 1 */ - INTT32A01C_IRQn = 100, /*!< 32bit T32A01C compare match detection 0 / Over flow / under flow*/ - INTT32A01CCAP0_IRQn = 101, /*!< 32bit T32A01C input capture 0 */ - INTT32A01CCAP1_IRQn = 102, /*!< 32bit T32A01C input capture 1 */ - INTT32A02A_IRQn = 103, /*!< 32bit T32A02A compare match detection 0 / Over flow / under flow*/ - INTT32A02ACAP0_IRQn = 104, /*!< 32bit T32A02A input capture 0 */ - INTT32A02ACAP1_IRQn = 105, /*!< 32bit T32A02A input capture 1 */ - INTT32A02B_IRQn = 106, /*!< 32bit T32A02B compare match detection 0 / Over flow / under flow*/ - INTT32A02BCAP0_IRQn = 107, /*!< 32bit T32A02B input capture 0 */ - INTT32A02BCAP1_IRQn = 108, /*!< 32bit T32A02B input capture 1 */ - INTT32A02C_IRQn = 109, /*!< 32bit T32A02C compare match detection 0 / Over flow / under flow*/ - INTT32A02CCAP0_IRQn = 110, /*!< 32bit T32A02C input capture 0 */ - INTT32A02CCAP1_IRQn = 111, /*!< 32bit T32A02C input capture 1 */ - INTT32A03A_IRQn = 112, /*!< 32bit T32A03A compare match detection 0 / Over flow / under flow*/ - INTT32A03ACAP0_IRQn = 113, /*!< 32bit T32A03A input capture 0 */ - INTT32A03ACAP1_IRQn = 114, /*!< 32bit T32A03A input capture 1 */ - INTT32A03B_IRQn = 115, /*!< 32bit T32A03B compare match detection 0 / Over flow / under flow*/ - INTT32A03BCAP0_IRQn = 116, /*!< 32bit T32A03B input capture 0 */ - INTT32A03BCAP1_IRQn = 117, /*!< 32bit T32A03B input capture 1 */ - INTT32A03C_IRQn = 118, /*!< 32bit T32A03C compare match detection 0 / Over flow / under flow*/ - INTT32A03CCAP0_IRQn = 119, /*!< 32bit T32A03C input capture 0 */ - INTT32A03CCAP1_IRQn = 120, /*!< 32bit T32A03C input capture 1 */ - INTT32A04A_IRQn = 121, /*!< 32bit T32A04A compare match detection 0 / Over flow / under flow*/ - INTT32A04ACAP0_IRQn = 122, /*!< 32bit T32A04A input capture 0 */ - INTT32A04ACAP1_IRQn = 123, /*!< 32bit T32A04A input capture 1 */ - INTT32A04B_IRQn = 124, /*!< 32bit T32A04B compare match detection 0 / Over flow / under flow*/ - INTT32A04BCAP0_IRQn = 125, /*!< 32bit T32A04B input capture 0 */ - INTT32A04BCAP1_IRQn = 126, /*!< 32bit T32A04B input capture 1 */ - INTT32A04C_IRQn = 127, /*!< 32bit T32A04C compare match detection 0 / Over flow / under flow*/ - INTT32A04CCAP0_IRQn = 128, /*!< 32bit T32A04C input capture 0 */ - INTT32A04CCAP1_IRQn = 129, /*!< 32bit T32A04C input capture 1 */ - INTT32A05A_IRQn = 130, /*!< 32bit T32A05A compare match detection 0 / Over flow / under flow*/ - INTT32A05ACAP0_IRQn = 131, /*!< 32bit T32A05A input capture 0 */ - INTT32A05ACAP1_IRQn = 132, /*!< 32bit T32A05A input capture 1 */ - INTT32A05B_IRQn = 133, /*!< 32bit T32A05B compare match detection 0 / Over flow / under flow*/ - INTT32A05BCAP0_IRQn = 134, /*!< 32bit T32A05B input capture 0 */ - INTT32A05BCAP1_IRQn = 135, /*!< 32bit T32A05B input capture 1 */ - INTT32A05C_IRQn = 136, /*!< 32bit T32A05C compare match detection 0 / Over flow / under flow*/ - INTT32A05CCAP0_IRQn = 137, /*!< 32bit T32A05C input capture 0 */ - INTT32A05CCAP1_IRQn = 138, /*!< 32bit T32A05C input capture 1 */ - INTT32A06A_IRQn = 139, /*!< 32bit T32A06A compare match detection 0 / Over flow / under flow*/ - INTT32A06ACAP0_IRQn = 140, /*!< 32bit T32A06A input capture 0 */ - INTT32A06ACAP1_IRQn = 141, /*!< 32bit T32A06A input capture 1 */ - INTT32A06B_IRQn = 142, /*!< 32bit T32A06B compare match detection 0 / Over flow / under flow*/ - INTT32A06BCAP0_IRQn = 143, /*!< 32bit T32A06B input capture 0 */ - INTT32A06BCAP1_IRQn = 144, /*!< 32bit T32A06B input capture 1 */ - INTT32A06C_IRQn = 145, /*!< 32bit T32A06C compare match detection 0 / Over flow / under flow*/ - INTT32A06CCAP0_IRQn = 146, /*!< 32bit T32A06C input capture 0 */ - INTT32A06CCAP1_IRQn = 147, /*!< 32bit T32A06C input capture 1 */ - INTT32A07A_IRQn = 148, /*!< 32bit T32A07A compare match detection 0 / Over flow / under flow*/ - INTT32A07ACAP0_IRQn = 149, /*!< 32bit T32A07A input capture 0 */ - INTT32A07ACAP1_IRQn = 150, /*!< 32bit T32A07A input capture 1 */ - INTT32A07B_IRQn = 151, /*!< 32bit T32A07B compare match detection 0 / Over flow / under flow*/ - INTT32A07BCAP0_IRQn = 152, /*!< 32bit T32A07B input capture 0 */ - INTT32A07BCAP1_IRQn = 153, /*!< 32bit T32A07B input capture 1 */ - INTT32A07C_IRQn = 154, /*!< 32bit T32A07C compare match detection 0 / Over flow / under flow*/ - INTT32A07CCAP0_IRQn = 155, /*!< 32bit T32A07C input capture 0 */ - INTT32A07CCAP1_IRQn = 156, /*!< 32bit T32A07C input capture 1 */ - INTPARI_IRQn = 157, /*!< RAM parity interrupt */ - INTDMAATC_IRQn = 158, /*!< DMAA end of transfer */ - INTDMAAERR_IRQn = 159, /*!< DMAA transfer error */ - INTDMABTC_IRQn = 160, /*!< DMAB end of transfer */ - INTDMABERR_IRQn = 161, /*!< DMAB transfer error */ - INTRTC_IRQn = 162, /*!< Real time clock interrupt */ - INTRMC0_IRQn = 163, /*!< Remote control reception interrupt */ - INTFLCRDY_IRQn = 164, /*!< Code FLASH Ready interrupt */ - INTFLDRDY_IRQn = 165 /*!< Data FLASH Ready interrupt */ -} IRQn_Type; - -/** Processor and Core Peripheral Section */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_TMPM3HQ.h" /* TMPM3HQ System */ - -/** @addtogroup Device_Peripheral_registers - * @{ - */ - -/** Device Specific Peripheral registers structures */ - -/** - * @brief Interrupt control A Register - */ -typedef struct -{ - __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(A) 00 */ - uint8_t RESERVED0[31]; - __IO uint8_t IMC00; /*!< Interrupu Mode Control Register(A) 00 */ - __IO uint8_t IMC01; /*!< Interrupu Mode Control Register(A) 01 */ - __IO uint8_t IMC02; /*!< Interrupu Mode Control Register(A) 02 */ - __IO uint8_t IMC03; /*!< Interrupu Mode Control Register(A) 03 */ - uint8_t RESERVED1[12]; - __IO uint8_t IMC16; /*!< Interrupu Mode Control Register(A) 16 */ - __IO uint8_t IMC17; /*!< Interrupu Mode Control Register(A) 17 */ -} TSB_IA_TypeDef; - -/** - * @brief Reset LOSC Management register - */ -typedef struct -{ - __IO uint8_t LOSCCR; /*!< Low OSC Control Register */ - __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */ - __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ - __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ - uint8_t RESERVED0[11]; - __IO uint8_t PROTECT; /*!< Protect Register */ -} TSB_RLM_TypeDef; - -/** - * @brief I2C Wakeup control register - */ -typedef struct -{ - __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */ - __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */ - __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */ - __I uint8_t WUPSL; /*!< I2C Wakeup Status register */ -} TSB_I2CS_TypeDef; - -/** - * @brief LVD0 - */ -typedef struct -{ - __IO uint8_t CR; /*!< LVD Control register */ -} TSB_LVD_TypeDef; - -/** - * @brief DMA Controller - */ -typedef struct -{ - __I uint32_t STATUS; /*!< DMA Status Register */ - __O uint32_t CFG; /*!< DMA Configuration Register */ - __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ - __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base -Pointer Register*/ - uint32_t RESERVED0; - __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ - __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ - __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ - __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ - __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ - __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ - __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ - __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ - __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ - __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ - __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ - uint32_t RESERVED1[3]; - __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ -} TSB_DMA_TypeDef; - -/** - * @brief Digital analog converter (DAC) - */ -typedef struct -{ - __IO uint32_t CTL; /*!< DAC Control Register */ - __IO uint32_t REG; /*!< DAC output Register */ -} TSB_DA_TypeDef; - -/** - * @brief Serial Interface (TSPI) - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TSPI Control Register 0 */ - __IO uint32_t CR1; /*!< TSPI Control Register 1 */ - __IO uint32_t CR2; /*!< TSPI Control Register 2 */ - __IO uint32_t CR3; /*!< TSPI Control Register 3 */ - __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ - __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ - __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ - uint32_t RESERVED0[57]; - __IO uint32_t DR; /*!< TSPI Data Register */ - uint32_t RESERVED1[63]; - __IO uint32_t SR; /*!< TSPI Status Register */ - __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ -} TSB_TSPI_TypeDef; - -#if defined ( __CC_ARM ) /* RealView Compiler */ -#pragma anon_unions -#elif (defined (__ICCARM__)) /* ICC Compiler */ -#pragma language=extended -#endif - -/** - * @brief I2C - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control Register 1 */ - __IO uint32_t DBR; /*!< I2C Data Buffer Register */ - __IO uint32_t AR; /*!< I2C Bus address Register */ -union { - __O uint32_t CR2; /*!< I2C Control Register 2 */ - __I uint32_t SR; /*!< I2C Status Register */ - }; - __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ - __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ - __IO uint32_t ST; /*!< I2C Interrupt Register */ - __IO uint32_t OP; /*!< I2C Optiononal Function register */ - __I uint32_t PM; /*!< I2C Bus Monitor register */ - __IO uint32_t AR2; /*!< I2C Second Slave address register */ -} TSB_I2C_TypeDef; - -/** - * @brief ADC - */ -typedef struct -{ - __IO uint32_t CR0; /*!< AD Control Register 0 */ - __IO uint32_t CR1; /*!< AD Control Register 1 */ - __I uint32_t ST; /*!< AD Status Register */ - __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ - __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ - __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ - __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ - __IO uint32_t MOD3; /*!< AD Mode Control Register 3 */ - __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */ - __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */ - __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */ - __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ - __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ - uint32_t RESERVED0[3]; - __IO uint32_t PSEL0; /*!< AD PMD Trigger Program Number Select Register 0*/ - __IO uint32_t PSEL1; /*!< AD PMD Trigger Program Number Select Register 1*/ - __IO uint32_t PSEL2; /*!< AD PMD Trigger Program Number Select Register 2*/ - __IO uint32_t PSEL3; /*!< AD PMD Trigger Program Number Select Register 3*/ - __IO uint32_t PSEL4; /*!< AD PMD Trigger Program Number Select Register 4*/ - __IO uint32_t PSEL5; /*!< AD PMD Trigger Program Number Select Register 5*/ - __IO uint32_t PSEL6; /*!< AD PMD Trigger Program Number Select Register 6*/ - __IO uint32_t PSEL7; /*!< AD PMD Trigger Program Number Select Register 7*/ - __IO uint32_t PSEL8; /*!< AD PMD Trigger Program Number Select Register 8*/ - __IO uint32_t PSEL9; /*!< AD PMD Trigger Program Number Select Register 9*/ - __IO uint32_t PSEL10; /*!< AD PMD Trigger Program Number Select Register 10*/ - __IO uint32_t PSEL11; /*!< AD PMD Trigger Program Number Select Register 11*/ - __IO uint32_t PINTS0; /*!< AD PMD Trigger Interrupt Select Register 0 */ - __IO uint32_t PINTS1; /*!< AD PMD Trigger Interrupt Select Register 1 */ - __IO uint32_t PINTS2; /*!< AD PMD Trigger Interrupt Select Register 2 */ - __IO uint32_t PINTS3; /*!< AD PMD Trigger Interrupt Select Register 3 */ - __IO uint32_t PINTS4; /*!< AD PMD Trigger Interrupt Select Register 4 */ - __IO uint32_t PINTS5; /*!< AD PMD Trigger Interrupt Select Register 5 */ - __IO uint32_t PINTS6; /*!< AD PMD Trigger Interrupt Select Register 6 */ - __IO uint32_t PINTS7; /*!< AD PMD Trigger Interrupt Select Register 7 */ - __IO uint32_t PREGS; /*!< AD PMD Trigger Conversion Result Storage Select Register*/ - uint32_t RESERVED1[3]; - __IO uint32_t PSET0; /*!< AD PMD Trigger Program Register 0 */ - __IO uint32_t PSET1; /*!< AD PMD Trigger Program Register 1 */ - __IO uint32_t PSET2; /*!< AD PMD Trigger Program Register 2 */ - __IO uint32_t PSET3; /*!< AD PMD Trigger Program Register 3 */ - __IO uint32_t PSET4; /*!< AD PMD Trigger Program Register 4 */ - __IO uint32_t PSET5; /*!< AD PMD Trigger Program Register 5 */ - __IO uint32_t PSET6; /*!< AD PMD Trigger Program Register 6 */ - __IO uint32_t PSET7; /*!< AD PMD Trigger Program Register 7 */ - __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ - __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ - __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ - __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ - __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ - __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ - __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ - __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ - __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ - __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ - __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ - __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ - __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ - __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ - __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ - __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ - __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ - __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ - __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ - __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ - __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ - __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ - __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ - __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ - uint32_t RESERVED2[8]; - __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */ - __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ - __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ - __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ - __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ - __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ - __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ - __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ - __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ - __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ - __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ - __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ - __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ - __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ - __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ - __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ - __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ - __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ - __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ - __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ - __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ - __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ - __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ - __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ -} TSB_AD_TypeDef; - -/** - * @brief T32A - */ -typedef struct -{ - __IO uint32_t MOD; /*!< T32A Mode Register */ - uint32_t RESERVED0[15]; - __IO uint32_t RUNA; /*!< T32A Run Register A */ - __IO uint32_t CRA; /*!< T32A Counter control Register A */ - __IO uint32_t CAPCRA; /*!< T32A Capture control Register A */ - __IO uint32_t OUTCRA0; /*!< T32A Output control Register A0 */ - __IO uint32_t OUTCRA1; /*!< T32A Output control Register A1 */ - __IO uint32_t STA; /*!< T32A Status Register A */ - __IO uint32_t IMA; /*!< T32A Interrupt mask Register A */ - __I uint32_t TMRA; /*!< T32A Counter capture Register A */ - __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ - __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ - __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ - __I uint32_t CAPA0; /*!< T32A Timer capturer A0 */ - __I uint32_t CAPA1; /*!< T32A Timer capturer A1 */ - __IO uint32_t DMAA; /*!< T32A DMA Request Enabl eRegister A */ - uint32_t RESERVED1[2]; - __IO uint32_t RUNB; /*!< T32A Run Register B */ - __IO uint32_t CRB; /*!< T32A Counter control Register B */ - __IO uint32_t CAPCRB; /*!< T32A Capture control Register B */ - __IO uint32_t OUTCRB0; /*!< T32A Output control Register B0 */ - __IO uint32_t OUTCRB1; /*!< T32A Output control Register B1 */ - __IO uint32_t STB; /*!< T32A Status Register B */ - __IO uint32_t IMB; /*!< T32A Interrupt mask Register B */ - __I uint32_t TMRB; /*!< T32A Counter capture Register B */ - __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ - __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ - __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ - __I uint32_t CAPB0; /*!< T32A Timer capturer B0 */ - __I uint32_t CAPB1; /*!< T32A Timer capturer B1 */ - __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ - uint32_t RESERVED2[2]; - __IO uint32_t RUNC; /*!< T32A Run Register C */ - __IO uint32_t CRC; /*!< T32A Counter control Register C */ - __IO uint32_t CAPCRC; /*!< T32A Capture control Register C */ - __IO uint32_t OUTCRC0; /*!< T32A Output control Register C0 */ - __IO uint32_t OUTCRC1; /*!< T32A Output control Register C1 */ - __IO uint32_t STC; /*!< T32A Status Register C */ - __IO uint32_t IMC; /*!< T32A Interrupt mask Register C */ - __I uint32_t TMRC; /*!< T32A Counter capture Register C */ - __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ - __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ - __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ - __I uint32_t CAPC0; /*!< T32A Timer capturer C0 */ - __I uint32_t CAPC1; /*!< T32A Timer capturer C1 */ - __IO uint32_t DMAC; /*!< T32A DMA Request Enabl eRegister C */ - __IO uint32_t PLSCR; /*!< T32A Pulse count control register */ -} TSB_T32A_TypeDef; - -/** - * @brief UART - */ -typedef struct -{ - __IO uint32_t SWRST; /*!< UART Software reset register */ - __IO uint32_t CR0; /*!< UART Control register 0 */ - __IO uint32_t CR1; /*!< UART Control register 1 */ - __IO uint32_t CLK; /*!< UART Clock Control register */ - __IO uint32_t BRD; /*!< UART Baud rate register */ - __IO uint32_t TRANS; /*!< UART Transfer enable register */ - __IO uint32_t DR; /*!< UART Data register */ - __IO uint32_t SR; /*!< UART Status register */ - __IO uint32_t FIFOCLR; /*!< UART FIFO Clear register */ - __IO uint32_t ERR; /*!< UART Error register */ -} TSB_UART_TypeDef; - -/** - * @brief SIWD - */ -typedef struct -{ - __IO uint32_t PRO; /*!< SIWD Protect register */ - __IO uint32_t EN; /*!< SIWD Enable register */ - __O uint32_t CR; /*!< SIWD Control register */ - __IO uint32_t MOD; /*!< SIWD Mode register */ - __I uint32_t MONI; /*!< SIWD Monitor register */ - __IO uint32_t OSCCR; /*!< SIWD Oscillation control register */ -} TSB_SIWD_TypeDef; - -/** - * @brief DNF - */ -typedef struct -{ - __IO uint32_t CKCR; /*!< DNF clock Control register */ - __IO uint32_t ENCR; /*!< DNF Enable register */ -} TSB_DNF_TypeDef; - -/** - * @brief TRGSEL - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ - __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ - __IO uint32_t CR2; /*!< TSEL Control register 2 */ - __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ - __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ - __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ - __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ - __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ - __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ - __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ - __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ - __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ - __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ - __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ - __IO uint32_t CR14; /*!< TRGSEL Control register 14 */ - __IO uint32_t CR15; /*!< TRGSEL Control register 15 */ -} TSB_TSEL_TypeDef; - -/** - * @brief RAM Parity - */ -typedef struct -{ - __IO uint32_t CTL; /*!< RAMM Parity control register */ - __I uint32_t ST; /*!< RAMM Parity status register */ - __O uint32_t CLR; /*!< RAMM Parity status clear register */ - __I uint32_t EAD0; /*!< RAMM Parity Error address register 0 */ - __I uint32_t EAD1; /*!< RAMM Parity Error address register 1 */ - __I uint32_t EAD2; /*!< RAMM Parity Error address register 2 */ - __I uint32_t EAD3; /*!< RAMM Parity Error address register 3 */ -} TSB_RPAR_TypeDef; - -/** - * @brief CRC - */ -typedef struct -{ - __IO uint32_t DIN; /*!< CRC input data register */ - uint32_t RESERVED0[4]; - __IO uint32_t TYP; /*!< CRC data type register */ - uint32_t RESERVED1[5]; - __IO uint32_t CLC; /*!< CRC calculation result register */ -} TSB_CRC_TypeDef; - -/** - * @brief CMP - */ -typedef struct -{ - __IO uint32_t CTRLA; /*!< CMP control register A */ -} TSB_CMP_TypeDef; - -/** - * @brief Port A - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PA Data Register */ - __IO uint32_t CR; /*!< PA Control Register */ - __IO uint32_t FR1; /*!< PA Function Register 1 */ - __IO uint32_t FR2; /*!< PA Function Register 2 */ - __IO uint32_t FR3; /*!< PA Function Register 3 */ - __IO uint32_t FR4; /*!< PA Function Register 4 */ - __IO uint32_t FR5; /*!< PA Function Register 5 */ - __IO uint32_t FR6; /*!< PA Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PA Open Drain Control Register */ - __IO uint32_t PUP; /*!< PA Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PA Input Enable Control Register */ -} TSB_PA_TypeDef; - -/** - * @brief Port B - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PB Data Register */ - __IO uint32_t CR; /*!< PB Control Register */ - __IO uint32_t FR1; /*!< PB Function Register 1 */ - __IO uint32_t FR2; /*!< PB Function Register 2 */ - __IO uint32_t FR3; /*!< PB Function Register 3 */ - __IO uint32_t FR4; /*!< PB Function Register 4 */ - __IO uint32_t FR5; /*!< PB Function Register 5 */ - __IO uint32_t FR6; /*!< PB Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PB Open Drain Control Register */ - __IO uint32_t PUP; /*!< PB Pull-up Control Register */ - __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PB Input Enable Control Register */ -} TSB_PB_TypeDef; - -/** - * @brief Port C - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PC Data Register */ - __IO uint32_t CR; /*!< PC Control Register */ - __IO uint32_t FR1; /*!< PC Function Register 1 */ - __IO uint32_t FR2; /*!< PC Function Register 2 */ - __IO uint32_t FR3; /*!< PC Function Register 3 */ - __IO uint32_t FR4; /*!< PC Function Register 4 */ - __IO uint32_t FR5; /*!< PC Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PC Open Drain Control Register */ - __IO uint32_t PUP; /*!< PC Pull-up Control Register */ - __IO uint32_t PDN; /*!< PC Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PC Input Enable Control Register */ -} TSB_PC_TypeDef; - -/** - * @brief Port D - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PD Data Register */ - __IO uint32_t CR; /*!< PD Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PD Open Drain Control Register */ - __IO uint32_t PUP; /*!< PD Pull-up Control Register */ - __IO uint32_t PDN; /*!< PD Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PD Input Enable Control Register */ -} TSB_PD_TypeDef; - -/** - * @brief Port E - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PE Data Register */ - __IO uint32_t CR; /*!< PE Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PE Open Drain Control Register */ - __IO uint32_t PUP; /*!< PE Pull-up Control Register */ - __IO uint32_t PDN; /*!< PE Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PE Input Enable Control Register */ -} TSB_PE_TypeDef; - -/** - * @brief Port F - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PF Data Register */ - __IO uint32_t CR; /*!< PF Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PF Open Drain Control Register */ - __IO uint32_t PUP; /*!< PF Pull-up Control Register */ - __IO uint32_t PDN; /*!< PF Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PF Input Enable Control Register */ -} TSB_PF_TypeDef; - -/** - * @brief Port G - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PG Data Register */ - __IO uint32_t CR; /*!< PG Control Register */ - __IO uint32_t FR1; /*!< PG Function Register 1 */ - __IO uint32_t FR2; /*!< PG Function Register 2 */ - __IO uint32_t FR3; /*!< PG Function Register 3 */ - __IO uint32_t FR4; /*!< PG Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PG Open Drain Control Register */ - __IO uint32_t PUP; /*!< PG Pull-up Control Register */ - __IO uint32_t PDN; /*!< PG Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PG Input Enable Control Register */ -} TSB_PG_TypeDef; - -/** - * @brief Port H - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PH Data Register */ - __IO uint32_t CR; /*!< PH Control Register */ - __IO uint32_t FR1; /*!< PH Function Register 1 */ - uint32_t RESERVED0[7]; - __IO uint32_t OD; /*!< PH Open Drain Control Register */ - __IO uint32_t PUP; /*!< PH Pull-up Control Register */ - __IO uint32_t PDN; /*!< PH Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PH Input Enable Control Register */ -} TSB_PH_TypeDef; - -/** - * @brief Port J - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PJ Data Register */ - __IO uint32_t CR; /*!< PJ Control Register */ - __IO uint32_t FR1; /*!< PJ Function Register 1 */ - __IO uint32_t FR2; /*!< PJ Function Register 2 */ - __IO uint32_t FR3; /*!< PJ Function Register 3 */ - __IO uint32_t FR4; /*!< PJ Function Register 4 */ - __IO uint32_t FR5; /*!< PJ Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PJ Open Drain Control Register */ - __IO uint32_t PUP; /*!< PJ Pull-up Control Register */ - __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PJ Input Enable Control Register */ -} TSB_PJ_TypeDef; - -/** - * @brief Port K - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PK Data Register */ - __IO uint32_t CR; /*!< PK Control Register */ - __IO uint32_t FR1; /*!< PK Function Register 1 */ - __IO uint32_t FR2; /*!< PK Function Register 2 */ - __IO uint32_t FR3; /*!< PK Function Register 3 */ - __IO uint32_t FR4; /*!< PK Function Register 4 */ - __IO uint32_t FR5; /*!< PK Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PK Open Drain Control Register */ - __IO uint32_t PUP; /*!< PK Pull-up Control Register */ - __IO uint32_t PDN; /*!< PK Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PK Input Enable Control Register */ -} TSB_PK_TypeDef; - -/** - * @brief Port L - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PL Data Register */ - __IO uint32_t CR; /*!< PL Control Register */ - __IO uint32_t FR1; /*!< PL Function Register 1 */ - __IO uint32_t FR2; /*!< PL Function Register 2 */ - __IO uint32_t FR3; /*!< PL Function Register 3 */ - __IO uint32_t FR4; /*!< PL Function Register 4 */ - __IO uint32_t FR5; /*!< PL Function Register 4 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PL Open Drain Control Register */ - __IO uint32_t PUP; /*!< PL Pull-up Control Register */ - __IO uint32_t PDN; /*!< PL Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PL Input Enable Control Register */ -} TSB_PL_TypeDef; - -/** - * @brief Port M - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PM Data Register */ - __IO uint32_t CR; /*!< PM Control Register */ - __IO uint32_t FR1; /*!< PM Function Register 1 */ - __IO uint32_t FR2; /*!< PM Function Register 2 */ - __IO uint32_t FR3; /*!< PM Function Register 3 */ - __IO uint32_t FR4; /*!< PM Function Register 4 */ - __IO uint32_t FR5; /*!< PM Function Register 5 */ - __IO uint32_t FR6; /*!< PM Function Register 6 */ - uint32_t RESERVED0[2]; - __IO uint32_t OD; /*!< PM Open Drain Control Register */ - __IO uint32_t PUP; /*!< PM Pull-up Control Register */ - __IO uint32_t PDN; /*!< PM Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PM Input Enable Control Register */ -} TSB_PM_TypeDef; - -/** - * @brief Port N - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PN Data Register */ - __IO uint32_t CR; /*!< PN Control Register */ - __IO uint32_t FR1; /*!< PN Function Register 1 */ - __IO uint32_t FR2; /*!< PN Function Register 2 */ - __IO uint32_t FR3; /*!< PN Function Register 3 */ - __IO uint32_t FR4; /*!< PN Function Register 4 */ - __IO uint32_t FR5; /*!< PN Function Register 5 */ - uint32_t RESERVED0[3]; - __IO uint32_t OD; /*!< PN Open Drain Control Register */ - __IO uint32_t PUP; /*!< PN Pull-up Control Register */ - __IO uint32_t PDN; /*!< PN Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PN Input Enable Control Register */ -} TSB_PN_TypeDef; - -/** - * @brief Port P - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PP Data Register */ - __IO uint32_t CR; /*!< PP Control Register */ - __IO uint32_t FR1; /*!< PP Function Register 1 */ - __IO uint32_t FR2; /*!< PP Function Register 2 */ - __IO uint32_t FR3; /*!< PP Function Register 3 */ - __IO uint32_t FR4; /*!< PP Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PP Open Drain Control Register */ - __IO uint32_t PUP; /*!< PP Pull-up Control Register */ - __IO uint32_t PDN; /*!< PP Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PP Input Enable Control Register */ -} TSB_PP_TypeDef; - -/** - * @brief Port R - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PR Data Register */ - __IO uint32_t CR; /*!< PR Control Register */ - uint32_t RESERVED0[2]; - __IO uint32_t FR3; /*!< PR Function Register 3 */ - __IO uint32_t FR4; /*!< PR Function Register 4 */ - uint32_t RESERVED1[4]; - __IO uint32_t OD; /*!< PR Open Drain Control Register */ - __IO uint32_t PUP; /*!< PR Pull-up Control Register */ - __IO uint32_t PDN; /*!< PR Pull-Down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< PR Input Enable Control Register */ -} TSB_PR_TypeDef; - -/** - * @brief Port T - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PT Data Register */ - __IO uint32_t CR; /*!< PT Control Register */ - __IO uint32_t FR1; /*!< PT Function Register 1 */ - __IO uint32_t FR2; /*!< PT Function Register 2 */ - __IO uint32_t FR3; /*!< PT Function Register 3 */ - __IO uint32_t FR4; /*!< PT Function Register 4 */ - uint32_t RESERVED0[4]; - __IO uint32_t OD; /*!< PT Open Drain Control Register */ - __IO uint32_t PUP; /*!< PT Pull-up Control Register */ - __IO uint32_t PDN; /*!< PT Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PT Input Enable Control Register */ -} TSB_PT_TypeDef; - -/** - * @brief Port U - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PU Data Register */ - __IO uint32_t CR; /*!< PU Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< PU Open Drain Control Register */ - __IO uint32_t PUP; /*!< PU Pull-up Control Register */ - __IO uint32_t PDN; /*!< PU Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PU Input Enable Control Register */ -} TSB_PU_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t DATA; /*!< PV Data Register */ - __IO uint32_t CR; /*!< PV Control Register */ - __IO uint32_t FR1; /*!< PV Function Register 1 */ - __IO uint32_t FR2; /*!< PV Function Register 2 */ - uint32_t RESERVED0[6]; - __IO uint32_t OD; /*!< PV Open Drain Control Register */ - __IO uint32_t PUP; /*!< PV Pull-up Control Register */ - __IO uint32_t PDN; /*!< PV Pull-Down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< PV Input Enable Control Register */ -} TSB_PV_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint8_t SECR; /*!< RTC Sec setting register */ - __IO uint8_t MINR; /*!< RTC Min settging register */ - __IO uint8_t HOURR; /*!< RTC Hour setting register */ - uint8_t RESERVED0; - __IO uint8_t DAYR; /*!< RTC Day setting register */ - __IO uint8_t DATER; /*!< RTC Date setting register */ - __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */ - __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */ - __IO uint8_t PAGER; /*!< RTC Page register */ - uint8_t RESERVED1[3]; - __IO uint8_t RESTR; /*!< RTC Reset register */ - uint8_t RESERVED2; - __IO uint8_t PROTECT; /*!< RTC protect register */ - __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */ - __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */ - __IO uint8_t ADJSIGN; /*!< RTC clock adjust sign register */ -} TSB_RTC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t EN; /*!< RMC Enable Register */ - __IO uint32_t REN; /*!< RMC Receive Enable Register */ - __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ - __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ - __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ - __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ - __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ - __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ - __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ - __I uint32_t RSTAT; /*!< RMC Receive Status Register */ - __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ - __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ - __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ - __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */ -} TSB_RMC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t CR1; /*!< OFD Control Register 1 */ - __IO uint32_t CR2; /*!< OFD Control Register 2 */ - __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ - __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ - __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ - __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ - __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ - __I uint32_t STAT; /*!< OFD Status Register */ - __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */ -} TSB_OFD_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t PROTECT; /*!< CG Protect Register */ - __IO uint32_t OSCCR; /*!< CG Oscillation Control Register */ - __IO uint32_t SYSCR; /*!< CG System clock control register */ - __IO uint32_t STBYCR; /*!< CG Standby Control Register */ - __IO uint32_t SCOCR; /*!< CG SCOUT Control Register */ - uint32_t RESERVED0[3]; - __IO uint32_t PLL0SEL; /*!< CG PLL select register for fsys */ - uint32_t RESERVED1[3]; - __IO uint32_t WUPHCR; /*!< CG Warmup register for HOSC */ - __IO uint32_t WUPLCR; /*!< CG Low-speed oscillation warm-up register */ - uint32_t RESERVED2[6]; - __IO uint32_t FSYSENA; /*!< CG output control register A for fsys clock */ - __IO uint32_t FSYSENB; /*!< CG output control register B for fsys clock */ - __IO uint32_t FCEN; /*!< CG output control register for fc clock */ - __IO uint32_t SPCLKEN; /*!< CG Output control register for ADC AND TRACE CLOCK*/ -} TSB_CG_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t OSCPRO; /*!< TRM Protect register */ - __IO uint32_t OSCEN; /*!< TRM Enable register */ - __I uint32_t OSCINIT; /*!< TRM Initial trimming level monitor register */ - __IO uint32_t OSCSET; /*!< TRM Trimming level setting register */ -} TSB_TRM_TypeDef; - -/** - * @brief Interrupt control register B - */ -typedef struct -{ - uint8_t RESERVED0[16]; - __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(B) 00 */ - uint8_t RESERVED1[79]; - __IO uint8_t IMC000; /*!< Interrupu Mode Control Register(B) 000 */ - __IO uint8_t IMC001; /*!< Interrupu Mode Control Register(B) 001 */ - __IO uint8_t IMC002; /*!< Interrupu Mode Control Register(B) 002 */ - __IO uint8_t IMC003; /*!< Interrupu Mode Control Register(B) 003 */ - __IO uint8_t IMC004; /*!< Interrupu Mode Control Register(B) 004 */ - __IO uint8_t IMC005; /*!< Interrupu Mode Control Register(B) 005 */ - __IO uint8_t IMC006; /*!< Interrupu Mode Control Register(B) 006 */ - __IO uint8_t IMC007; /*!< Interrupu Mode Control Register(B) 007 */ - __IO uint8_t IMC008; /*!< Interrupu Mode Control Register(B) 008 */ - __IO uint8_t IMC009; /*!< Interrupu Mode Control Register(B) 009 */ - __IO uint8_t IMC010; /*!< Interrupu Mode Control Register(B) 010 */ - __IO uint8_t IMC011; /*!< Interrupu Mode Control Register(B) 011 */ - __IO uint8_t IMC012; /*!< Interrupu Mode Control Register(B) 012 */ - __IO uint8_t IMC013; /*!< Interrupu Mode Control Register(B) 013 */ - __IO uint8_t IMC014; /*!< Interrupu Mode Control Register(B) 014 */ - __IO uint8_t IMC015; /*!< Interrupu Mode Control Register(B) 015 */ - __IO uint8_t IMC016; /*!< Interrupu Mode Control Register(B) 016 */ - __IO uint8_t IMC017; /*!< Interrupu Mode Control Register(B) 017 */ - __IO uint8_t IMC018; /*!< Interrupu Mode Control Register(B) 018 */ - __IO uint8_t IMC019; /*!< Interrupu Mode Control Register(B) 019 */ - __IO uint8_t IMC020; /*!< Interrupu Mode Control Register(B) 020 */ - __IO uint8_t IMC021; /*!< Interrupu Mode Control Register(B) 021 */ - __IO uint8_t IMC022; /*!< Interrupu Mode Control Register(B) 022 */ - __IO uint8_t IMC023; /*!< Interrupu Mode Control Register(B) 023 */ - __IO uint8_t IMC024; /*!< Interrupu Mode Control Register(B) 024 */ - __IO uint8_t IMC025; /*!< Interrupu Mode Control Register(B) 025 */ - __IO uint8_t IMC026; /*!< Interrupu Mode Control Register(B) 026 */ - __IO uint8_t IMC027; /*!< Interrupu Mode Control Register(B) 027 */ - __IO uint8_t IMC028; /*!< Interrupu Mode Control Register(B) 028 */ - __IO uint8_t IMC029; /*!< Interrupu Mode Control Register(B) 029 */ - __IO uint8_t IMC030; /*!< Interrupu Mode Control Register(B) 030 */ - __IO uint8_t IMC031; /*!< Interrupu Mode Control Register(B) 031 */ - __IO uint8_t IMC032; /*!< Interrupu Mode Control Register(B) 032 */ - __IO uint8_t IMC033; /*!< Interrupt Mode Control Register(B) 033 */ - __IO uint8_t IMC034; /*!< Interrupt Mode Control Register(B) 034 */ - __IO uint8_t IMC035; /*!< Interrupt Mode Control Register(B) 035 */ - __IO uint8_t IMC036; /*!< Interrupt Mode Control Register(B) 036 */ - __IO uint8_t IMC037; /*!< Interrupt Mode Control Register(B) 037 */ - __IO uint8_t IMC038; /*!< Interrupt Mode Control Register(B) 038 */ - __IO uint8_t IMC039; /*!< Interrupt Mode Control Register(B) 039 */ - __IO uint8_t IMC040; /*!< Interrupt Mode Control Register(B) 040 */ - __IO uint8_t IMC041; /*!< Interrupt Mode Control Register(B) 041 */ - __IO uint8_t IMC042; /*!< Interrupt Mode Control Register(B) 042 */ - __IO uint8_t IMC043; /*!< Interrupt Mode Control Register(B) 043 */ - __IO uint8_t IMC044; /*!< Interrupt Mode Control Register(B) 044 */ - __IO uint8_t IMC045; /*!< Interrupt Mode Control Register(B) 045 */ - __IO uint8_t IMC046; /*!< Interrupt Mode Control Register(B) 046 */ - __IO uint8_t IMC047; /*!< Interrupt Mode Control Register(B) 047 */ - __IO uint8_t IMC048; /*!< Interrupt Mode Control Register(B) 048 */ - __IO uint8_t IMC049; /*!< Interrupt Mode Control Register(B) 049 */ - __IO uint8_t IMC050; /*!< Interrupt Mode Control Register(B) 050 */ - __IO uint8_t IMC051; /*!< Interrupt Mode Control Register(B) 051 */ - __IO uint8_t IMC052; /*!< Interrupt Mode Control Register(B) 052 */ - __IO uint8_t IMC053; /*!< Interrupt Mode Control Register(B) 053 */ - __IO uint8_t IMC054; /*!< Interrupt Mode Control Register(B) 054 */ - __IO uint8_t IMC055; /*!< Interrupt Mode Control Register(B) 055 */ - __IO uint8_t IMC056; /*!< Interrupt Mode Control Register(B) 056 */ - __IO uint8_t IMC057; /*!< Interrupt Mode Control Register(B) 057 */ - __IO uint8_t IMC058; /*!< Interrupt Mode Control Register(B) 058 */ - __IO uint8_t IMC059; /*!< Interrupt Mode Control Register(B) 059 */ - __IO uint8_t IMC060; /*!< Interrupt Mode Control Register(B) 060 */ - __IO uint8_t IMC061; /*!< Interrupt Mode Control Register(B) 061 */ - __IO uint8_t IMC062; /*!< Interrupt Mode Control Register(B) 062 */ - __IO uint8_t IMC063; /*!< Interrupt Mode Control Register(B) 063 */ - __IO uint8_t IMC064; /*!< Interrupt Mode Control Register(B) 064 */ - __IO uint8_t IMC065; /*!< Interrupt Mode Control Register(B) 065 */ - __IO uint8_t IMC066; /*!< Interrupu Mode Control Register(B) 066 */ - __IO uint8_t IMC067; /*!< Interrupu Mode Control Register(B) 067 */ - __IO uint8_t IMC068; /*!< Interrupu Mode Control Register(B) 068 */ - __IO uint8_t IMC069; /*!< Interrupu Mode Control Register(B) 069 */ - __IO uint8_t IMC070; /*!< Interrupu Mode Control Register(B) 070 */ - __IO uint8_t IMC071; /*!< Interrupu Mode Control Register(B) 071 */ - __IO uint8_t IMC072; /*!< Interrupu Mode Control Register(B) 072 */ - __IO uint8_t IMC073; /*!< Interrupu Mode Control Register(B) 073 */ - __IO uint8_t IMC074; /*!< Interrupu Mode Control Register(B) 074 */ - __IO uint8_t IMC075; /*!< Interrupu Mode Control Register(B) 075 */ - __IO uint8_t IMC076; /*!< Interrupu Mode Control Register(B) 076 */ - __IO uint8_t IMC077; /*!< Interrupu Mode Control Register(B) 077 */ - __IO uint8_t IMC078; /*!< Interrupu Mode Control Register(B) 078 */ - __IO uint8_t IMC079; /*!< Interrupu Mode Control Register(B) 079 */ - __IO uint8_t IMC080; /*!< Interrupu Mode Control Register(B) 080 */ - __IO uint8_t IMC081; /*!< Interrupu Mode Control Register(B) 081 */ - __IO uint8_t IMC082; /*!< Interrupu Mode Control Register(B) 082 */ - __IO uint8_t IMC083; /*!< Interrupu Mode Control Register(B) 083 */ - __IO uint8_t IMC084; /*!< Interrupu Mode Control Register(B) 084 */ - __IO uint8_t IMC085; /*!< Interrupu Mode Control Register(B) 085 */ - __IO uint8_t IMC086; /*!< Interrupu Mode Control Register(B) 086 */ - __IO uint8_t IMC087; /*!< Interrupu Mode Control Register(B) 087 */ - __IO uint8_t IMC088; /*!< Interrupu Mode Control Register(B) 088 */ - __IO uint8_t IMC089; /*!< Interrupu Mode Control Register(B) 089 */ - __IO uint8_t IMC090; /*!< Interrupu Mode Control Register(B) 090 */ - __IO uint8_t IMC091; /*!< Interrupu Mode Control Register(B) 091 */ - __IO uint8_t IMC092; /*!< Interrupu Mode Control Register(B) 092 */ - __IO uint8_t IMC093; /*!< Interrupu Mode Control Register(B) 093 */ - __IO uint8_t IMC094; /*!< Interrupu Mode Control Register(B) 094 */ -} TSB_IB_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __I uint32_t FLGNMI; /*!< Interrupt Monitor Flag 0 */ - __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 */ - uint32_t RESERVED0; - __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 */ - __I uint32_t FLG4; /*!< NMI Interrupt Monitor Flag 4 */ - __I uint32_t FLG5; /*!< NMI Interrupt Monitor Flag 5 */ -} TSB_IMN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t MDEN; /*!< PMD Enable Register */ - __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ - __IO uint32_t MDCR; /*!< PMD Control Register */ - __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ - __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ - __IO uint32_t RATE; /*!< PWM Frequency Register */ - __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ - __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ - __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ - uint32_t RESERVED0; - __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ - __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ - __O uint32_t EMGREL; /*!< PMD EMG Release Register */ - __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ - __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ - __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ - __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ - __IO uint32_t DTR; /*!< PMD Dead Time Register */ - __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ - __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ - __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ - __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ - __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ - __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ - __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ - __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ - __IO uint32_t VPWMPH; /*!< Phase difference setting of the V-phase PWM */ - __IO uint32_t WPWMPH; /*!< Phase difference setting of the W-phase PWM */ - __IO uint32_t MBUFCR; /*!< Update timing of the triple buffer */ - uint32_t RESERVED1; - __IO uint32_t DBGOUTCR; /*!< Debug output control */ -} TSB_PMD_TypeDef; - -/** - * @brief Encoder Input (ENC) - */ -typedef struct -{ - __IO uint32_t TNCR; /*!< ENC Control Register */ - __IO uint32_t RELOAD; /*!< ENC Reload Compare Register */ - __IO uint32_t INT; /*!< ENC INT Compare Register */ - __IO uint32_t CNT; /*!< ENC Counter/Capture Register */ - __IO uint32_t MCMP; /*!< ENC MCMP Compare Register */ - __IO uint32_t RATE; /*!< ENC Phase Count Rate Register */ - __I uint32_t STS; /*!< ENC Status Register */ - __IO uint32_t INPCR; /*!< ENC Input Process Cntrol Register */ - __IO uint32_t SMPDLY; /*!< ENC Sample Delay Register */ - __I uint32_t INPMON; /*!< ENC Input Moniter Register */ - __IO uint32_t CLKCR; /*!< ENC Sample Clock Control Register */ - __IO uint32_t INTCR; /*!< ENC Interrupt Reqyest Control Register */ - __I uint32_t INTF; /*!< ENC Interrupt Event Flag Register */ -} TSB_EN_TypeDef; - -/** - * @brief - */ -typedef struct -{ - uint32_t RESERVED0[4]; - __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ - __IO uint32_t SSR; /*!< Flash Security Status Register */ - __O uint32_t KCR; /*!< Flash Key Code Register */ - uint32_t RESERVED1; - __IO uint32_t SR0; /*!< Flash Status Register 0 */ - uint32_t RESERVED2[3]; - __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ - __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ - uint32_t RESERVED3[4]; - __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ - uint32_t RESERVED4; - __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ - __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ - uint32_t RESERVED5[4]; - __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ - uint32_t RESERVED6[37]; - __I uint32_t SR1; /*!< Flash Status Register 1 */ - __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ - uint32_t RESERVED7[14]; - __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ - uint32_t RESERVED8; - __IO uint32_t CR; /*!< Flash Control Register */ - __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ - __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ - uint32_t RESERVED9; - __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ -} TSB_FC_TypeDef; - - -/* Memory map */ -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x20000000UL) -#define PERI_BASE (0x40000000UL) - - -#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) -#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) -#define TSB_I2CS_BASE (PERI_BASE + 0x003E800UL) -#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) -#define TSB_DMAA_BASE (PERI_BASE + 0x004C000UL) -#define TSB_DMAB_BASE (PERI_BASE + 0x004D000UL) -#define TSB_DA0_BASE (PERI_BASE + 0x0054000UL) -#define TSB_DA1_BASE (PERI_BASE + 0x0055000UL) -#define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL) -#define TSB_TSPI1_BASE (PERI_BASE + 0x0099000UL) -#define TSB_TSPI2_BASE (PERI_BASE + 0x009A000UL) -#define TSB_TSPI3_BASE (PERI_BASE + 0x009B000UL) -#define TSB_TSPI4_BASE (PERI_BASE + 0x009C000UL) -#define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL) -#define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL) -#define TSB_I2C2_BASE (PERI_BASE + 0x00A2000UL) -#define TSB_I2C3_BASE (PERI_BASE + 0x00A3000UL) -#define TSB_ADA_BASE (PERI_BASE + 0x00B8800UL) -#define TSB_T32A0_BASE (PERI_BASE + 0x00BA000UL) -#define TSB_T32A1_BASE (PERI_BASE + 0x00BA100UL) -#define TSB_T32A2_BASE (PERI_BASE + 0x00BA200UL) -#define TSB_T32A3_BASE (PERI_BASE + 0x00BA300UL) -#define TSB_T32A4_BASE (PERI_BASE + 0x00BA400UL) -#define TSB_T32A5_BASE (PERI_BASE + 0x00BA500UL) -#define TSB_T32A6_BASE (PERI_BASE + 0x00BA600UL) -#define TSB_T32A7_BASE (PERI_BASE + 0x00BA700UL) -#define TSB_UART0_BASE (PERI_BASE + 0x00BB000UL) -#define TSB_UART1_BASE (PERI_BASE + 0x00BB100UL) -#define TSB_UART2_BASE (PERI_BASE + 0x00BB200UL) -#define TSB_UART3_BASE (PERI_BASE + 0x00BB300UL) -#define TSB_UART4_BASE (PERI_BASE + 0x00BBD00UL) -#define TSB_UART5_BASE (PERI_BASE + 0x00BBE00UL) -#define TSB_SIWD0_BASE (PERI_BASE + 0x00BB400UL) -#define TSB_DNFA_BASE (PERI_BASE + 0x00BB600UL) -#define TSB_DNFB_BASE (PERI_BASE + 0x00BB700UL) -#define TSB_TSEL0_BASE (PERI_BASE + 0x00BB800UL) -#define TSB_TSEL1_BASE (PERI_BASE + 0x00BB900UL) -#define TSB_RPAR_BASE (PERI_BASE + 0x00BBB00UL) -#define TSB_CRC_BASE (PERI_BASE + 0x00BBC00UL) -#define TSB_CMP_BASE (PERI_BASE + 0x00BC100UL) -#define TSB_PA_BASE (PERI_BASE + 0x00C0000UL) -#define TSB_PB_BASE (PERI_BASE + 0x00C0100UL) -#define TSB_PC_BASE (PERI_BASE + 0x00C0200UL) -#define TSB_PD_BASE (PERI_BASE + 0x00C0300UL) -#define TSB_PE_BASE (PERI_BASE + 0x00C0400UL) -#define TSB_PF_BASE (PERI_BASE + 0x00C0500UL) -#define TSB_PG_BASE (PERI_BASE + 0x00C0600UL) -#define TSB_PH_BASE (PERI_BASE + 0x00C0700UL) -#define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL) -#define TSB_PK_BASE (PERI_BASE + 0x00C0900UL) -#define TSB_PL_BASE (PERI_BASE + 0x00C0A00UL) -#define TSB_PM_BASE (PERI_BASE + 0x00C0B00UL) -#define TSB_PN_BASE (PERI_BASE + 0x00C0C00UL) -#define TSB_PP_BASE (PERI_BASE + 0x00C0D00UL) -#define TSB_PR_BASE (PERI_BASE + 0x00C0E00UL) -#define TSB_PT_BASE (PERI_BASE + 0x00C0F00UL) -#define TSB_PU_BASE (PERI_BASE + 0x00C1000UL) -#define TSB_PV_BASE (PERI_BASE + 0x00C1100UL) -#define TSB_RTC_BASE (PERI_BASE + 0x00CC000UL) -#define TSB_RMC0_BASE (PERI_BASE + 0x00E7000UL) -#define TSB_OFD_BASE (PERI_BASE + 0x00F1000UL) -#define TSB_CG_BASE (PERI_BASE + 0x00F3000UL) -#define TSB_TRM_BASE (PERI_BASE + 0x00F3200UL) -#define TSB_IB_BASE (PERI_BASE + 0x00F4E00UL) -#define TSB_IMN_BASE (PERI_BASE + 0x00F4F00UL) -#define TSB_PMD0_BASE (PERI_BASE + 0x00F6000UL) -#define TSB_EN0_BASE (PERI_BASE + 0x00F7000UL) -#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) - - -/* Peripheral declaration */ -#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) -#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) -#define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE) -#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) -#define TSB_DMAA (( TSB_DMA_TypeDef *) TSB_DMAA_BASE) -#define TSB_DMAB (( TSB_DMA_TypeDef *) TSB_DMAB_BASE) -#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) -#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) -#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) -#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) -#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) -#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) -#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) -#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) -#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) -#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) -#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) -#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) -#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) -#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) -#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) -#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) -#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) -#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) -#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) -#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) -#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) -#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) -#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) -#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) -#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) -#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) -#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) -#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) -#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) -#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) -#define TSB_TSEL1 (( TSB_TSEL_TypeDef *) TSB_TSEL1_BASE) -#define TSB_RPAR (( TSB_RPAR_TypeDef *) TSB_RPAR_BASE) -#define TSB_CRC (( TSB_CRC_TypeDef *) TSB_CRC_BASE) -#define TSB_CMP (( TSB_CMP_TypeDef *) TSB_CMP_BASE) -#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) -#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) -#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) -#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) -#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) -#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) -#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) -#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) -#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) -#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) -#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) -#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) -#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) -#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) -#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) -#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) -#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) -#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) -#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) -#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) -#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) -#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) -#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) -#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) -#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) -#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) -#define TSB_EN0 (( TSB_EN_TypeDef *) TSB_EN0_BASE) -#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) - - -/* Bit-Band for Device Specific Peripheral Registers */ -#define BITBAND_OFFSET (0x02000000UL) -#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) -#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) - - - - - - - -/* DMA Controller */ -#define TSB_DMAA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0))) -#define TSB_DMAA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0))) -#define TSB_DMAA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0))) - -#define TSB_DMAB_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAB->STATUS,0))) -#define TSB_DMAB_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAB->CFG,0))) -#define TSB_DMAB_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAB->ERRCLR,0))) - - -/* Digital analog converter (DAC) */ -#define TSB_DA0_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CTL,0))) - -#define TSB_DA1_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CTL,0))) - - -/* Serial Interface (TSPI) */ -#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) -#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) -#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) -#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) -#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) -#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) -#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) -#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) -#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) -#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) -#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) -#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) -#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16))) -#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) -#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) -#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) -#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) -#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) -#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) -#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) -#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) -#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) -#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) -#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) -#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) -#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) -#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) -#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) -#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) -#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) -#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) -#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) -#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) -#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) -#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) -#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) -#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) -#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) - -#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) -#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) -#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) -#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) -#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) -#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) -#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) -#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) -#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) -#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) -#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) -#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) -#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16))) -#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) -#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) -#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) -#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) -#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) -#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) -#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) -#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) -#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) -#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) -#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) -#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) -#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) -#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) -#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) -#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) -#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) -#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) -#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) -#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) -#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) -#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) -#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) -#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) -#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) - -#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) -#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) -#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) -#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) -#define TSB_TSPI2_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) -#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) -#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) -#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) -#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) -#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) -#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) -#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) -#define TSB_TSPI2_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,16))) -#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) -#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) -#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) -#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) -#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) -#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) -#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) -#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) -#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) -#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) -#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) -#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) -#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) -#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) -#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) -#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) -#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) -#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) -#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) -#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) -#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) -#define TSB_TSPI2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,0))) -#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) -#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) -#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) - -#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) -#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) -#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) -#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) -#define TSB_TSPI3_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) -#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) -#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) -#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) -#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) -#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) -#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) -#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) -#define TSB_TSPI3_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,16))) -#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) -#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) -#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) -#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) -#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) -#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) -#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) -#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) -#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) -#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) -#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) -#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) -#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) -#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) -#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) -#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) -#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) -#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) -#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) -#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) -#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) -#define TSB_TSPI3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,0))) -#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) -#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) -#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) - -#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) -#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) -#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) -#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) -#define TSB_TSPI4_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) -#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) -#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) -#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) -#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) -#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) -#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) -#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) -#define TSB_TSPI4_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,16))) -#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) -#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) -#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) -#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) -#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) -#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) -#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) -#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) -#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) -#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) -#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) -#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) -#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) -#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) -#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) -#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) -#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) -#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) -#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) -#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) -#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) -#define TSB_TSPI4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,0))) -#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) -#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) -#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) - - -/* I2C */ -#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) -#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) -#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) -#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) -#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) -#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) -#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) -#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) -#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) -#define TSB_I2C0_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) -#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) -#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) -#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) -#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) -#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) -#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) -#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) -#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) -#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) -#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) -#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) -#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) -#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) -#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) -#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) -#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) -#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) -#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) -#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) -#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) -#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) -#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) -#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) -#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) -#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) -#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) -#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) -#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) - -#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) -#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) -#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) -#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) -#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) -#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) -#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) -#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) -#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) -#define TSB_I2C1_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) -#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) -#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) -#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) -#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) -#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) -#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) -#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) -#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) -#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) -#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) -#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) -#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) -#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) -#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) -#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) -#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) -#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) -#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) -#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) -#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) -#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) -#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) -#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) -#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) -#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) -#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) -#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) -#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) - -#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) -#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) -#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) -#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) -#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) -#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) -#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) -#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) -#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) -#define TSB_I2C2_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) -#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) -#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) -#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) -#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) -#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) -#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) -#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) -#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) -#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) -#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) -#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) -#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) -#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) -#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) -#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) -#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) -#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) -#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) -#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) -#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) -#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) -#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) -#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) -#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) -#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) -#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) -#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) -#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) - -#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) -#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) -#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) -#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) -#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) -#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) -#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) -#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) -#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) -#define TSB_I2C3_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) -#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) -#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) -#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) -#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) -#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) -#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) -#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) -#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) -#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) -#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) -#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) -#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) -#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) -#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) -#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) -#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) -#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) -#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) -#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) -#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) -#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) -#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) -#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) -#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) -#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) -#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) -#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) -#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) - - -/* ADC */ -#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) -#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) -#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) -#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) -#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) -#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) -#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) -#define TSB_ADA_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) -#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) -#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) -#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) -#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) -#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) -#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) -#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) -#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) -#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) -#define TSB_ADA_CMPCR0_COMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) -#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) -#define TSB_ADA_CMPCR1_COMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) -#define TSB_ADA_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL0,7))) -#define TSB_ADA_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL1,7))) -#define TSB_ADA_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL2,7))) -#define TSB_ADA_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL3,7))) -#define TSB_ADA_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL4,7))) -#define TSB_ADA_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL5,7))) -#define TSB_ADA_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL6,7))) -#define TSB_ADA_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL7,7))) -#define TSB_ADA_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL8,7))) -#define TSB_ADA_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL9,7))) -#define TSB_ADA_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL10,7))) -#define TSB_ADA_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL11,7))) -#define TSB_ADA_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,7))) -#define TSB_ADA_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,15))) -#define TSB_ADA_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,23))) -#define TSB_ADA_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,31))) -#define TSB_ADA_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,7))) -#define TSB_ADA_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,15))) -#define TSB_ADA_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,23))) -#define TSB_ADA_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,31))) -#define TSB_ADA_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,7))) -#define TSB_ADA_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,15))) -#define TSB_ADA_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,23))) -#define TSB_ADA_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,31))) -#define TSB_ADA_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,7))) -#define TSB_ADA_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,15))) -#define TSB_ADA_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,23))) -#define TSB_ADA_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,31))) -#define TSB_ADA_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,7))) -#define TSB_ADA_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,15))) -#define TSB_ADA_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,23))) -#define TSB_ADA_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,31))) -#define TSB_ADA_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,7))) -#define TSB_ADA_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,15))) -#define TSB_ADA_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,23))) -#define TSB_ADA_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,31))) -#define TSB_ADA_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,7))) -#define TSB_ADA_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,15))) -#define TSB_ADA_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,23))) -#define TSB_ADA_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,31))) -#define TSB_ADA_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,7))) -#define TSB_ADA_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,15))) -#define TSB_ADA_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,23))) -#define TSB_ADA_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,31))) -#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) -#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) -#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) -#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) -#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) -#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) -#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) -#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) -#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) -#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) -#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) -#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) -#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) -#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) -#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) -#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) -#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) -#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) -#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) -#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) -#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) -#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) -#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) -#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) -#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) -#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) -#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) -#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) -#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) -#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) -#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) -#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) -#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) -#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) -#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) -#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) -#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) -#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) -#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) -#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) -#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) -#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) -#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) -#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) -#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) -#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) -#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) -#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) -#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) -#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) -#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) -#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) -#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) -#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) -#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) -#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) -#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) -#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) -#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) -#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) -#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) -#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) -#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) -#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) -#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) -#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) -#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) -#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) -#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) -#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) -#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) -#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) -#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) -#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) -#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) -#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) -#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) -#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) -#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) -#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) -#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) -#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) -#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) -#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) -#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) -#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) -#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) -#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) -#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) -#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) -#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) -#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) -#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) -#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) -#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) -#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) -#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) -#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) -#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) -#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) -#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) -#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) -#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) -#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) -#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) -#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) -#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) -#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) -#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) -#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) -#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) -#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) -#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) -#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) -#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) -#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) -#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) -#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) -#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) -#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) - - -/* T32A */ -#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) -#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) -#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) -#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) -#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) -#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) -#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) -#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) -#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) -#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) -#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) -#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) -#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) -#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) -#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) -#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) -#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) -#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) -#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) -#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) -#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) -#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) -#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) -#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) -#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) -#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) -#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) -#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) -#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) -#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) -#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) -#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) -#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) -#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) -#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) -#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) -#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) -#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) -#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) -#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) -#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) -#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) -#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) -#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) -#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) -#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) -#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) -#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) -#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) -#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) -#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) -#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) -#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) -#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) - -#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) -#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) -#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) -#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) -#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) -#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) -#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) -#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) -#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) -#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) -#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) -#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) -#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) -#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) -#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) -#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) -#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) -#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) -#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) -#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) -#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) -#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) -#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) -#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) -#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) -#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) -#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) -#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) -#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) -#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) -#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) -#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) -#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) -#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) -#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) -#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) -#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) -#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) -#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) -#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) -#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) -#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) -#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) -#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) -#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) -#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) -#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) -#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) -#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) -#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) -#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) -#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) -#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) -#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) - -#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) -#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) -#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) -#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) -#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) -#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) -#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) -#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) -#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) -#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) -#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) -#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) -#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) -#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) -#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) -#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) -#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) -#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) -#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) -#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) -#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) -#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) -#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) -#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) -#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) -#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) -#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) -#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) -#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) -#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) -#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) -#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) -#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) -#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) -#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) -#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) -#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) -#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) -#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) -#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) -#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) -#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) -#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) -#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) -#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) -#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) -#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) -#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) -#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) -#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) -#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) -#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) -#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) -#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) - -#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) -#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) -#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) -#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) -#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) -#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) -#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) -#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) -#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) -#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) -#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) -#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) -#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) -#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) -#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) -#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) -#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) -#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) -#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) -#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) -#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) -#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) -#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) -#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) -#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) -#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) -#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) -#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) -#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) -#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) -#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) -#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) -#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) -#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) -#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) -#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) -#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) -#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) -#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) -#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) -#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) -#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) -#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) -#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) -#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) -#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) -#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) -#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) -#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) -#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) -#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) -#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) -#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) -#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) - -#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) -#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) -#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) -#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) -#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) -#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) -#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) -#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) -#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) -#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) -#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) -#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) -#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) -#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) -#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) -#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) -#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) -#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) -#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) -#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) -#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) -#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) -#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) -#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) -#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) -#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) -#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) -#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) -#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) -#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) -#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) -#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) -#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) -#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) -#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) -#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) -#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) -#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) -#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) -#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) -#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) -#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) -#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) -#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) -#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) -#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) -#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) -#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) -#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) -#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) -#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) -#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) -#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) -#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) - -#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) -#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) -#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) -#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) -#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) -#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) -#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) -#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) -#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) -#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) -#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) -#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) -#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) -#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) -#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) -#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) -#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) -#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) -#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) -#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) -#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) -#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) -#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) -#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) -#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) -#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) -#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) -#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) -#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) -#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) -#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) -#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) -#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) -#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) -#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) -#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) -#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) -#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) -#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) -#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) -#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) -#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) -#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) -#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) -#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) -#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) -#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) -#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) -#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) -#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) -#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) -#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) -#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) -#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) - -#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) -#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) -#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) -#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) -#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) -#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) -#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) -#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) -#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) -#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) -#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) -#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) -#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) -#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) -#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) -#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) -#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) -#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) -#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) -#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) -#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) -#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) -#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) -#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) -#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) -#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) -#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) -#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) -#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) -#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) -#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) -#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) -#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) -#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) -#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) -#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) -#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) -#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) -#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) -#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) -#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) -#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) -#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) -#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) -#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) -#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) -#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) -#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) -#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) -#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) -#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) -#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) -#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) -#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) - -#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) -#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) -#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) -#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) -#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) -#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) -#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) -#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) -#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) -#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) -#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) -#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) -#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) -#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) -#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) -#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) -#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) -#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) -#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) -#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) -#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) -#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) -#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) -#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) -#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) -#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) -#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) -#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) -#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) -#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) -#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) -#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) -#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) -#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) -#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) -#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) -#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) -#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) -#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) -#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) -#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) -#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) -#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) -#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) -#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) -#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) -#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) -#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) -#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) -#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) -#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) -#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) -#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) -#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) - - -/* UART */ -#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) -#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) -#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) -#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) -#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) -#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) -#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) -#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) -#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) -#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) -#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) -#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) -#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) -#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) -#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) -#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) -#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) -#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) -#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) -#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) -#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) -#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) -#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) -#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) -#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) -#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) -#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) -#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) -#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) -#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) -#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) -#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) -#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) -#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) -#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) -#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) -#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) -#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) -#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) -#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) -#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) -#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) - -#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) -#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) -#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) -#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) -#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) -#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) -#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) -#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) -#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) -#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) -#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) -#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) -#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) -#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) -#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) -#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) -#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) -#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) -#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) -#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) -#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) -#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) -#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) -#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) -#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) -#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) -#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) -#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) -#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) -#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) -#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) -#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) -#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) -#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) -#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) -#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) -#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) -#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) -#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) -#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) -#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) -#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) - -#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) -#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) -#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) -#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) -#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) -#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) -#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) -#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) -#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) -#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) -#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) -#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) -#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) -#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) -#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) -#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) -#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) -#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) -#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) -#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) -#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) -#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) -#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) -#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) -#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) -#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) -#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) -#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) -#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) -#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) -#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) -#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) -#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) -#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) -#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) -#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) -#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) -#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) -#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) -#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) -#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) -#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) - -#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) -#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) -#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) -#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) -#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) -#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) -#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) -#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) -#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) -#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) -#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) -#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) -#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) -#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) -#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) -#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) -#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) -#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) -#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) -#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) -#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) -#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) -#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) -#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) -#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) -#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) -#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) -#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) -#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) -#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) -#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) -#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) -#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) -#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) -#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) -#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) -#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) -#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) -#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) -#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) -#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) -#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) - -#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) -#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) -#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) -#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) -#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) -#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) -#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) -#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) -#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) -#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) -#define TSB_UART4_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,16))) -#define TSB_UART4_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,17))) -#define TSB_UART4_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,18))) -#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) -#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) -#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) -#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) -#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) -#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) -#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) -#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) -#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) -#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) -#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) -#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) -#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) -#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) -#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) -#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) -#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) -#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) -#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) -#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) -#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) -#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) -#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) -#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) -#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) -#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) -#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) -#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) -#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) - -#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) -#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) -#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) -#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) -#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) -#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) -#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) -#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) -#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) -#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) -#define TSB_UART5_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,16))) -#define TSB_UART5_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,17))) -#define TSB_UART5_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,18))) -#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) -#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) -#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) -#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) -#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) -#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) -#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) -#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) -#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) -#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) -#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) -#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) -#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) -#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) -#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) -#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) -#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) -#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) -#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) -#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) -#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) -#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) -#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) -#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) -#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) -#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) -#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) -#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) -#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) - - -/* SIWD */ -#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) -#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) -#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) -#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) -#define TSB_SIWD0_OSCCR_OSCPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->OSCCR,0))) - - -/* DNF */ -#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) -#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) -#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) -#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) -#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) -#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) -#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) -#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) -#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) -#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) -#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) -#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) -#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) -#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) -#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) -#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) - -#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) -#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) -#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) -#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) -#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) -#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) -#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) -#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) -#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) -#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) -#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) -#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) -#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) -#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) -#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) -#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) - - -/* TRGSEL */ -#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) -#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) -#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) -#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) -#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) -#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) -#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) -#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) -#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) -#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) -#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) -#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) -#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) -#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) -#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) -#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) -#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) -#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) -#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) -#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) -#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) -#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) -#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) -#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) -#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) -#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) -#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) -#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) -#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) -#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) -#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) -#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) -#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) -#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) -#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) -#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) -#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) -#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) -#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) -#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) -#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) -#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) -#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) -#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) -#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) -#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) -#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) -#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) -#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) -#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) -#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) -#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) -#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) -#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) -#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) -#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) -#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) -#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) -#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) -#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) -#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) -#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) -#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) -#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) -#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) -#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) -#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) -#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) -#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) -#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) -#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) -#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) -#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) -#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) -#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) -#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) -#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) -#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) -#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) -#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) -#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) -#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) -#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) -#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) -#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) -#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) -#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) -#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) -#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) -#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) -#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) -#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) -#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) -#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) -#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) -#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) -#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) -#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) -#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) -#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) -#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) -#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) -#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) -#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) -#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) -#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) -#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) -#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) -#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) -#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) -#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) -#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) -#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) -#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) -#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) -#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) -#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) -#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) -#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) -#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) -#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) -#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) -#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) -#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) -#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) -#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) -#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) -#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) -#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) -#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) -#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) -#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) -#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) -#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) -#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) -#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) -#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) -#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) -#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) -#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) -#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) -#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) -#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) -#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) -#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) -#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) -#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) -#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) -#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) -#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) -#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) -#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) -#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) -#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) -#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) -#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) -#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) -#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) -#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) -#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) -#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) -#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) -#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) -#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) -#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) -#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) -#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) -#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) -#define TSB_TSEL0_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,0))) -#define TSB_TSEL0_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,1))) -#define TSB_TSEL0_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,2))) -#define TSB_TSEL0_CR14_EN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,8))) -#define TSB_TSEL0_CR14_OUTSEL57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,9))) -#define TSB_TSEL0_CR14_UPDN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,10))) -#define TSB_TSEL0_CR14_EN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,16))) -#define TSB_TSEL0_CR14_OUTSEL58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,17))) -#define TSB_TSEL0_CR14_UPDN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,18))) -#define TSB_TSEL0_CR14_EN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,24))) -#define TSB_TSEL0_CR14_OUTSEL59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,25))) -#define TSB_TSEL0_CR14_UPDN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,26))) -#define TSB_TSEL0_CR15_EN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,0))) -#define TSB_TSEL0_CR15_OUTSEL60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,1))) -#define TSB_TSEL0_CR15_UPDN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,2))) -#define TSB_TSEL0_CR15_EN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,8))) -#define TSB_TSEL0_CR15_OUTSEL61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,9))) -#define TSB_TSEL0_CR15_UPDN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,10))) -#define TSB_TSEL0_CR15_EN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,16))) -#define TSB_TSEL0_CR15_OUTSEL62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,17))) -#define TSB_TSEL0_CR15_UPDN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,18))) -#define TSB_TSEL0_CR15_EN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,24))) -#define TSB_TSEL0_CR15_OUTSEL63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,25))) -#define TSB_TSEL0_CR15_UPDN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,26))) - -#define TSB_TSEL1_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,0))) -#define TSB_TSEL1_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,1))) -#define TSB_TSEL1_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,2))) -#define TSB_TSEL1_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,8))) -#define TSB_TSEL1_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,9))) -#define TSB_TSEL1_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,10))) -#define TSB_TSEL1_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,16))) -#define TSB_TSEL1_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,17))) -#define TSB_TSEL1_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,18))) -#define TSB_TSEL1_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,24))) -#define TSB_TSEL1_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,25))) -#define TSB_TSEL1_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,26))) -#define TSB_TSEL1_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,0))) -#define TSB_TSEL1_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,1))) -#define TSB_TSEL1_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,2))) -#define TSB_TSEL1_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,8))) -#define TSB_TSEL1_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,9))) -#define TSB_TSEL1_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,10))) -#define TSB_TSEL1_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,16))) -#define TSB_TSEL1_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,17))) -#define TSB_TSEL1_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,18))) -#define TSB_TSEL1_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,24))) -#define TSB_TSEL1_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,25))) -#define TSB_TSEL1_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,26))) -#define TSB_TSEL1_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,0))) -#define TSB_TSEL1_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,1))) -#define TSB_TSEL1_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,2))) -#define TSB_TSEL1_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,8))) -#define TSB_TSEL1_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,9))) -#define TSB_TSEL1_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,10))) -#define TSB_TSEL1_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,16))) -#define TSB_TSEL1_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,17))) -#define TSB_TSEL1_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,18))) -#define TSB_TSEL1_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,24))) -#define TSB_TSEL1_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,25))) -#define TSB_TSEL1_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,26))) -#define TSB_TSEL1_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,0))) -#define TSB_TSEL1_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,1))) -#define TSB_TSEL1_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,2))) -#define TSB_TSEL1_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,8))) -#define TSB_TSEL1_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,9))) -#define TSB_TSEL1_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,10))) -#define TSB_TSEL1_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,16))) -#define TSB_TSEL1_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,17))) -#define TSB_TSEL1_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,18))) -#define TSB_TSEL1_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,24))) -#define TSB_TSEL1_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,25))) -#define TSB_TSEL1_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,26))) -#define TSB_TSEL1_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,0))) -#define TSB_TSEL1_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,1))) -#define TSB_TSEL1_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,2))) -#define TSB_TSEL1_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,8))) -#define TSB_TSEL1_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,9))) -#define TSB_TSEL1_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,10))) -#define TSB_TSEL1_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,16))) -#define TSB_TSEL1_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,17))) -#define TSB_TSEL1_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,18))) -#define TSB_TSEL1_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,24))) -#define TSB_TSEL1_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,25))) -#define TSB_TSEL1_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,26))) -#define TSB_TSEL1_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,0))) -#define TSB_TSEL1_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,1))) -#define TSB_TSEL1_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,2))) -#define TSB_TSEL1_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,8))) -#define TSB_TSEL1_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,9))) -#define TSB_TSEL1_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,10))) -#define TSB_TSEL1_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,16))) -#define TSB_TSEL1_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,17))) -#define TSB_TSEL1_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,18))) -#define TSB_TSEL1_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,24))) -#define TSB_TSEL1_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,25))) -#define TSB_TSEL1_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,26))) -#define TSB_TSEL1_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,0))) -#define TSB_TSEL1_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,1))) -#define TSB_TSEL1_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,2))) -#define TSB_TSEL1_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,8))) -#define TSB_TSEL1_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,9))) -#define TSB_TSEL1_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,10))) -#define TSB_TSEL1_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,16))) -#define TSB_TSEL1_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,17))) -#define TSB_TSEL1_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,18))) -#define TSB_TSEL1_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,24))) -#define TSB_TSEL1_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,25))) -#define TSB_TSEL1_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,26))) -#define TSB_TSEL1_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,0))) -#define TSB_TSEL1_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,1))) -#define TSB_TSEL1_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,2))) -#define TSB_TSEL1_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,8))) -#define TSB_TSEL1_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,9))) -#define TSB_TSEL1_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,10))) -#define TSB_TSEL1_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,16))) -#define TSB_TSEL1_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,17))) -#define TSB_TSEL1_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,18))) -#define TSB_TSEL1_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,24))) -#define TSB_TSEL1_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,25))) -#define TSB_TSEL1_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,26))) -#define TSB_TSEL1_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,0))) -#define TSB_TSEL1_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,1))) -#define TSB_TSEL1_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,2))) -#define TSB_TSEL1_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,8))) -#define TSB_TSEL1_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,9))) -#define TSB_TSEL1_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,10))) -#define TSB_TSEL1_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,16))) -#define TSB_TSEL1_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,17))) -#define TSB_TSEL1_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,18))) -#define TSB_TSEL1_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,24))) -#define TSB_TSEL1_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,25))) -#define TSB_TSEL1_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,26))) -#define TSB_TSEL1_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,0))) -#define TSB_TSEL1_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,1))) -#define TSB_TSEL1_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,2))) -#define TSB_TSEL1_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,8))) -#define TSB_TSEL1_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,9))) -#define TSB_TSEL1_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,10))) -#define TSB_TSEL1_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,16))) -#define TSB_TSEL1_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,17))) -#define TSB_TSEL1_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,18))) -#define TSB_TSEL1_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,24))) -#define TSB_TSEL1_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,25))) -#define TSB_TSEL1_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,26))) -#define TSB_TSEL1_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,0))) -#define TSB_TSEL1_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,1))) -#define TSB_TSEL1_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,2))) -#define TSB_TSEL1_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,8))) -#define TSB_TSEL1_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,9))) -#define TSB_TSEL1_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,10))) -#define TSB_TSEL1_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,16))) -#define TSB_TSEL1_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,17))) -#define TSB_TSEL1_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,18))) -#define TSB_TSEL1_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,24))) -#define TSB_TSEL1_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,25))) -#define TSB_TSEL1_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,26))) -#define TSB_TSEL1_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,0))) -#define TSB_TSEL1_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,1))) -#define TSB_TSEL1_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,2))) -#define TSB_TSEL1_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,8))) -#define TSB_TSEL1_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,9))) -#define TSB_TSEL1_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,10))) -#define TSB_TSEL1_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,16))) -#define TSB_TSEL1_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,17))) -#define TSB_TSEL1_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,18))) -#define TSB_TSEL1_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,24))) -#define TSB_TSEL1_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,25))) -#define TSB_TSEL1_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,26))) -#define TSB_TSEL1_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,0))) -#define TSB_TSEL1_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,1))) -#define TSB_TSEL1_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,2))) -#define TSB_TSEL1_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,8))) -#define TSB_TSEL1_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,9))) -#define TSB_TSEL1_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,10))) -#define TSB_TSEL1_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,16))) -#define TSB_TSEL1_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,17))) -#define TSB_TSEL1_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,18))) -#define TSB_TSEL1_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,24))) -#define TSB_TSEL1_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,25))) -#define TSB_TSEL1_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,26))) -#define TSB_TSEL1_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,0))) -#define TSB_TSEL1_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,1))) -#define TSB_TSEL1_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,2))) -#define TSB_TSEL1_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,8))) -#define TSB_TSEL1_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,9))) -#define TSB_TSEL1_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,10))) -#define TSB_TSEL1_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,16))) -#define TSB_TSEL1_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,17))) -#define TSB_TSEL1_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,18))) -#define TSB_TSEL1_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,24))) -#define TSB_TSEL1_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,25))) -#define TSB_TSEL1_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,26))) -#define TSB_TSEL1_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,0))) -#define TSB_TSEL1_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,1))) -#define TSB_TSEL1_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,2))) -#define TSB_TSEL1_CR14_EN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,8))) -#define TSB_TSEL1_CR14_OUTSEL57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,9))) -#define TSB_TSEL1_CR14_UPDN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,10))) -#define TSB_TSEL1_CR14_EN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,16))) -#define TSB_TSEL1_CR14_OUTSEL58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,17))) -#define TSB_TSEL1_CR14_UPDN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,18))) -#define TSB_TSEL1_CR14_EN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,24))) -#define TSB_TSEL1_CR14_OUTSEL59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,25))) -#define TSB_TSEL1_CR14_UPDN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,26))) -#define TSB_TSEL1_CR15_EN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,0))) -#define TSB_TSEL1_CR15_OUTSEL60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,1))) -#define TSB_TSEL1_CR15_UPDN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,2))) -#define TSB_TSEL1_CR15_EN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,8))) -#define TSB_TSEL1_CR15_OUTSEL61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,9))) -#define TSB_TSEL1_CR15_UPDN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,10))) -#define TSB_TSEL1_CR15_EN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,16))) -#define TSB_TSEL1_CR15_OUTSEL62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,17))) -#define TSB_TSEL1_CR15_UPDN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,18))) -#define TSB_TSEL1_CR15_EN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,24))) -#define TSB_TSEL1_CR15_OUTSEL63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,25))) -#define TSB_TSEL1_CR15_UPDN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,26))) - - -/* RAM Parity */ -#define TSB_RPAR_CTL_RPAREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR->CTL,0))) -#define TSB_RPAR_CTL_RPARF (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR->CTL,1))) -#define TSB_RPAR_ST_RPARFG0 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,0))) -#define TSB_RPAR_ST_RPARFG1 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,1))) -#define TSB_RPAR_ST_RPARFG2 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,2))) -#define TSB_RPAR_ST_RPARFG3 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,3))) -#define TSB_RPAR_CLR_RPARCLR0 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,0))) -#define TSB_RPAR_CLR_RPARCLR1 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,1))) -#define TSB_RPAR_CLR_RPARCLR2 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,2))) -#define TSB_RPAR_CLR_RPARCLR3 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,3))) - - - -/* CMP */ -#define TSB_CMP_CTRLA_CMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CMP->CTRLA,0))) -#define TSB_CMP_CTRLA_CMPISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CMP->CTRLA,1))) - - -/* Port A */ -#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) -#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) -#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) -#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) -#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) -#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) -#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) -#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) -#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) -#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) -#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) -#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) -#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) -#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) -#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) -#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) -#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) -#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) -#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) -#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) -#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) -#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) -#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) -#define TSB_PA_FR2_PA1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,1))) -#define TSB_PA_FR2_PA2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,2))) -#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) -#define TSB_PA_FR2_PA6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,6))) -#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) -#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) -#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) -#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) -#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) -#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) -#define TSB_PA_FR4_PA0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,0))) -#define TSB_PA_FR4_PA1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,1))) -#define TSB_PA_FR4_PA2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,2))) -#define TSB_PA_FR4_PA3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,3))) -#define TSB_PA_FR4_PA4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,4))) -#define TSB_PA_FR4_PA5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,5))) -#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) -#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) -#define TSB_PA_FR5_PA2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,2))) -#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) -#define TSB_PA_FR6_PA1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,1))) -#define TSB_PA_FR6_PA2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,2))) -#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) -#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) -#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) -#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) -#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) -#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) -#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) -#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) -#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) -#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) -#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) -#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) -#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) -#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) -#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) -#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) -#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) -#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) -#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) -#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) -#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) -#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) -#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) -#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) -#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) -#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) -#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) -#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) -#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) -#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) -#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) -#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) -#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) - - -/* Port B */ -#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) -#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) -#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) -#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) -#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) -#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) -#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) -#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) -#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) -#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) -#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) -#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) -#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) -#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) -#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) -#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) -#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) -#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) -#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) -#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) -#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) -#define TSB_PB_FR2_PB2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,2))) -#define TSB_PB_FR2_PB3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,3))) -#define TSB_PB_FR2_PB4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,4))) -#define TSB_PB_FR2_PB5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,5))) -#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) -#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) -#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) -#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) -#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) -#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) -#define TSB_PB_FR4_PB1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,1))) -#define TSB_PB_FR4_PB2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2))) -#define TSB_PB_FR4_PB3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3))) -#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) -#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) -#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) -#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) -#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) -#define TSB_PB_FR5_PB5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,5))) -#define TSB_PB_FR6_PB0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,0))) -#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) -#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) -#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) -#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) -#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) -#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) -#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) -#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) -#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) -#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) -#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) -#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) -#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) -#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) -#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) -#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) -#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) -#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) -#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) -#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) -#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) -#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) -#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) -#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) -#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) -#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) -#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) -#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) -#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) -#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) -#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) -#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) - - -/* Port C */ -#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) -#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) -#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) -#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) -#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) -#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) -#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) -#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) -#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) -#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) -#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) -#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) -#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) -#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) -#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) -#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) -#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) -#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) -#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) -#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) -#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) -#define TSB_PC_FR2_PC3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,3))) -#define TSB_PC_FR2_PC4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,4))) -#define TSB_PC_FR2_PC5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,5))) -#define TSB_PC_FR2_PC6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,6))) -#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) -#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) -#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) -#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) -#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) -#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) -#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) -#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) -#define TSB_PC_FR4_PC2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,2))) -#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) -#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) -#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) -#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) -#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) -#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) -#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) -#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) -#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) -#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) -#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) -#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) -#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) -#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) -#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) -#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) -#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) -#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) -#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) -#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) -#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) -#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) -#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) -#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) -#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) -#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) -#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) -#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) -#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) - - -/* Port D */ -#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) -#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) -#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) -#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) -#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) -#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) -#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) -#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) -#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) -#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) -#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) -#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) -#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) -#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) -#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) -#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) -#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) -#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) -#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) -#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) -#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) -#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) -#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) -#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) -#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) -#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) -#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) -#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) -#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) -#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) -#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) -#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) -#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) -#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) -#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) -#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) - - -/* Port E */ -#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) -#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) -#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) -#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) -#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) -#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) -#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) -#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) -#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) -#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) -#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) -#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) -#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) -#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) -#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) -#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) -#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) -#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) -#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) -#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) -#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) -#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) -#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) -#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) -#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) -#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) -#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) -#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) -#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) -#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) -#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) -#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) -#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) -#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) -#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) -#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) -#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) -#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) -#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) -#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) -#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) -#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) - - -/* Port F */ -#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) -#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) -#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) -#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) -#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) -#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) -#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) -#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) -#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) -#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) -#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) -#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) -#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) -#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) -#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) -#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) -#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) -#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) -#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) -#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) -#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) -#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) -#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) -#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) -#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) -#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) -#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) -#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) -#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) -#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) -#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) -#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) -#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) -#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) -#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) -#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) -#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) -#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) -#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) -#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) -#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) -#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) -#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) -#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) -#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) -#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) -#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) -#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) - - -/* Port G */ -#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) -#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) -#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) -#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) -#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) -#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) -#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) -#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) -#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) -#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) -#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) -#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) -#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) -#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) -#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) -#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) -#define TSB_PG_FR1_PG2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,2))) -#define TSB_PG_FR1_PG3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,3))) -#define TSB_PG_FR1_PG4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,4))) -#define TSB_PG_FR2_PG2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,2))) -#define TSB_PG_FR2_PG3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,3))) -#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) -#define TSB_PG_FR3_PG3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) -#define TSB_PG_FR3_PG4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,4))) -#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) -#define TSB_PG_FR3_PG6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,6))) -#define TSB_PG_FR3_PG7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,7))) -#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) -#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) -#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) -#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) -#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) -#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) -#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) -#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) -#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) -#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) -#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) -#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) -#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) -#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) -#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) -#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) -#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) -#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) -#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) -#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) -#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) -#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) -#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) -#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) -#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) -#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) -#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) -#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) -#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) -#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) -#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) -#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) -#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) -#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) -#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) - - -/* Port H */ -#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) -#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) -#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) -#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) -#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) -#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) -#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) -#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) -#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) -#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) -#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) -#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) -#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) -#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) -#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) -#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) -#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) -#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) -#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) -#define TSB_PH_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) -#define TSB_PH_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) -#define TSB_PH_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) -#define TSB_PH_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) -#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) -#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) -#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) -#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) -#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) -#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) -#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) -#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) -#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) -#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) -#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) -#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) -#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) -#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) -#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) -#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) - - -/* Port J */ -#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) -#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) -#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) -#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) -#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) -#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) -#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) -#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) -#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) -#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) -#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) -#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) -#define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0))) -#define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1))) -#define TSB_PJ_FR1_PJ2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,2))) -#define TSB_PJ_FR1_PJ3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,3))) -#define TSB_PJ_FR1_PJ4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,4))) -#define TSB_PJ_FR2_PJ1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,1))) -#define TSB_PJ_FR2_PJ2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,2))) -#define TSB_PJ_FR2_PJ3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,3))) -#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) -#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) -#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) -#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) -#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) -#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) -#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) -#define TSB_PJ_FR4_PJ0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,0))) -#define TSB_PJ_FR4_PJ1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,1))) -#define TSB_PJ_FR4_PJ2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,2))) -#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) -#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) -#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) -#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) -#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) -#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) -#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) -#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) -#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) -#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) -#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) -#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) -#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) -#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) -#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) -#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) -#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) -#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) -#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) -#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) -#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) -#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) -#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) -#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) -#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) -#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) -#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) -#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) -#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) -#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) - - -/* Port K */ -#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) -#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) -#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) -#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) -#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) -#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) -#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) -#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) -#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) -#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) -#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) -#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) -#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) -#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) -#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) -#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) -#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) -#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) -#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) -#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) -#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) -#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) -#define TSB_PK_FR2_PK2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,2))) -#define TSB_PK_FR2_PK3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,3))) -#define TSB_PK_FR2_PK4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,4))) -#define TSB_PK_FR3_PK2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,2))) -#define TSB_PK_FR3_PK3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,3))) -#define TSB_PK_FR3_PK4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,4))) -#define TSB_PK_FR3_PK5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,5))) -#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) -#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) -#define TSB_PK_FR4_PK2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,2))) -#define TSB_PK_FR4_PK3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,3))) -#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) -#define TSB_PK_FR5_PK0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,0))) -#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) -#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) -#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) -#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) -#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) -#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) -#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) -#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) -#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) -#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) -#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) -#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) -#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) -#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) -#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) -#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) -#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) -#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) -#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) -#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) -#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) -#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) -#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) -#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) -#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) -#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) -#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) -#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) -#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) -#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) -#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) -#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) -#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) - - -/* Port L */ -#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) -#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) -#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) -#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) -#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) -#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) -#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) -#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) -#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) -#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) -#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) -#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) -#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) -#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) -#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) -#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) -#define TSB_PL_FR1_PL0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,0))) -#define TSB_PL_FR1_PL1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,1))) -#define TSB_PL_FR1_PL2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,2))) -#define TSB_PL_FR1_PL3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,3))) -#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) -#define TSB_PL_FR2_PL1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,1))) -#define TSB_PL_FR2_PL2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,2))) -#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) -#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) -#define TSB_PL_FR3_PL1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,1))) -#define TSB_PL_FR3_PL2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,2))) -#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) -#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) -#define TSB_PL_FR3_PL5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,5))) -#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) -#define TSB_PL_FR3_PL7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,7))) -#define TSB_PL_FR4_PL5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,5))) -#define TSB_PL_FR4_PL6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,6))) -#define TSB_PL_FR4_PL7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,7))) -#define TSB_PL_FR5_PL0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,0))) -#define TSB_PL_FR5_PL1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,1))) -#define TSB_PL_FR5_PL2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,2))) -#define TSB_PL_FR5_PL3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,3))) -#define TSB_PL_FR5_PL4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,4))) -#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) -#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) -#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) -#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) -#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) -#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) -#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) -#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) -#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) -#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) -#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) -#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) -#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) -#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) -#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) -#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) -#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) -#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) -#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) -#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) -#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) -#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) -#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) -#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) -#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) -#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) -#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) -#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) -#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) -#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) -#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) -#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) - - -/* Port M */ -#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) -#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) -#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) -#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) -#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) -#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) -#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) -#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) -#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) -#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) -#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) -#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) -#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) -#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) -#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) -#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) -#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) -#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) -#define TSB_PM_FR1_PM2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,2))) -#define TSB_PM_FR1_PM3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,3))) -#define TSB_PM_FR1_PM4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,4))) -#define TSB_PM_FR2_PM1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,1))) -#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) -#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) -#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) -#define TSB_PM_FR3_PM0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,0))) -#define TSB_PM_FR3_PM1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,1))) -#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) -#define TSB_PM_FR3_PM3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,3))) -#define TSB_PM_FR3_PM4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,4))) -#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) -#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) -#define TSB_PM_FR4_PM2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,2))) -#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) -#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) -#define TSB_PM_FR4_PM5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,5))) -#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) -#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) -#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) -#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) -#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) -#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) -#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) -#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) -#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) -#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) -#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) -#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) -#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) -#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) -#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) -#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) -#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) -#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) -#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) -#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) -#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) -#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) -#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) -#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) -#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) -#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) -#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) -#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) -#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) -#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) -#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) -#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) -#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) -#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) -#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) -#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) -#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) -#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) -#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) -#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) -#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) - - -/* Port N */ -#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) -#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) -#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) -#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) -#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) -#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) -#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) -#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) -#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) -#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) -#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) -#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) -#define TSB_PN_FR1_PN0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,0))) -#define TSB_PN_FR1_PN1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,1))) -#define TSB_PN_FR1_PN2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,2))) -#define TSB_PN_FR1_PN3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,3))) -#define TSB_PN_FR1_PN4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,4))) -#define TSB_PN_FR2_PN0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,0))) -#define TSB_PN_FR2_PN1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,1))) -#define TSB_PN_FR2_PN2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,2))) -#define TSB_PN_FR2_PN3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,3))) -#define TSB_PN_FR3_PN0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,0))) -#define TSB_PN_FR3_PN1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,1))) -#define TSB_PN_FR3_PN2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,2))) -#define TSB_PN_FR3_PN3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,3))) -#define TSB_PN_FR3_PN4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,4))) -#define TSB_PN_FR3_PN5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,5))) -#define TSB_PN_FR4_PN0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,0))) -#define TSB_PN_FR4_PN1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,1))) -#define TSB_PN_FR4_PN2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,2))) -#define TSB_PN_FR5_PN3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,3))) -#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) -#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) -#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) -#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) -#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) -#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) -#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) -#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) -#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) -#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) -#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) -#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) -#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) -#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) -#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) -#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) -#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) -#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) -#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) -#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) -#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) -#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) -#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) -#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) - - -/* Port P */ -#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) -#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) -#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) -#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) -#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) -#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) -#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) -#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) -#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) -#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) -#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) -#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) -#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) -#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) -#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) -#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) -#define TSB_PP_FR1_PP3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,3))) -#define TSB_PP_FR1_PP4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,4))) -#define TSB_PP_FR1_PP5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,5))) -#define TSB_PP_FR1_PP6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,6))) -#define TSB_PP_FR1_PP7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,7))) -#define TSB_PP_FR2_PP0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) -#define TSB_PP_FR2_PP1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) -#define TSB_PP_FR2_PP2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) -#define TSB_PP_FR2_PP6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) -#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) -#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) -#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) -#define TSB_PP_FR3_PP6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) -#define TSB_PP_FR4_PP0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,0))) -#define TSB_PP_FR4_PP1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,1))) -#define TSB_PP_FR4_PP2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,2))) -#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) -#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) -#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) -#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) -#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) -#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) -#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) -#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) -#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) -#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) -#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) -#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) -#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) -#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) -#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) -#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) -#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) -#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) -#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) -#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) -#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) -#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) -#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) -#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) -#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) -#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) -#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) -#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) -#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) -#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) -#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) -#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) - - -/* Port R */ -#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) -#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) -#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) -#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) -#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) -#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) -#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) -#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) -#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) -#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) -#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) -#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) -#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) -#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) -#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) -#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) -#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) -#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) -#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) -#define TSB_PR_FR4_PR0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,0))) -#define TSB_PR_FR4_PR1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,1))) -#define TSB_PR_FR4_PR2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,2))) -#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) -#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) -#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) -#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) -#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) -#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) -#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) -#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) -#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) -#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) -#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) -#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) -#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) -#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) -#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) -#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) -#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) -#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) -#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) -#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) -#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) -#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) -#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) -#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) -#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) -#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) -#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) -#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) -#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) -#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) -#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) -#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) - - -/* Port T */ -#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) -#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) -#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) -#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) -#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) -#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) -#define TSB_PT_DATA_PT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,6))) -#define TSB_PT_DATA_PT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,7))) -#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) -#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) -#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) -#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) -#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) -#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) -#define TSB_PT_CR_PT6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,6))) -#define TSB_PT_CR_PT7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,7))) -#define TSB_PT_FR1_PT0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,0))) -#define TSB_PT_FR1_PT1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,1))) -#define TSB_PT_FR1_PT2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,2))) -#define TSB_PT_FR1_PT3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) -#define TSB_PT_FR1_PT4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,4))) -#define TSB_PT_FR2_PT0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,0))) -#define TSB_PT_FR2_PT1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,1))) -#define TSB_PT_FR3_PT1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,1))) -#define TSB_PT_FR3_PT2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,2))) -#define TSB_PT_FR3_PT3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) -#define TSB_PT_FR3_PT4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,4))) -#define TSB_PT_FR3_PT5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,5))) -#define TSB_PT_FR3_PT6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,6))) -#define TSB_PT_FR3_PT7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,7))) -#define TSB_PT_FR4_PT5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,5))) -#define TSB_PT_FR4_PT6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,6))) -#define TSB_PT_FR4_PT7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,7))) -#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) -#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) -#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) -#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) -#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) -#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) -#define TSB_PT_OD_PT6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,6))) -#define TSB_PT_OD_PT7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,7))) -#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) -#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) -#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) -#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) -#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) -#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) -#define TSB_PT_PUP_PT6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,6))) -#define TSB_PT_PUP_PT7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,7))) -#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) -#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) -#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) -#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) -#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) -#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) -#define TSB_PT_PDN_PT6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,6))) -#define TSB_PT_PDN_PT7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,7))) -#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) -#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) -#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) -#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) -#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) -#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) -#define TSB_PT_IE_PT6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,6))) -#define TSB_PT_IE_PT7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,7))) - - -/* Port U */ -#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) -#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) -#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) -#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) -#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) -#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) -#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) -#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) -#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) -#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) -#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) -#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) -#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) -#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) -#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) -#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) -#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) -#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) -#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) -#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) -#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) -#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) -#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) -#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) -#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) -#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) -#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) -#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) -#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) -#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) -#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) -#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) -#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) -#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) -#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) -#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) - - -/* */ -#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) -#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) -#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) -#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) -#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) -#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) -#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) -#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) -#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) -#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) -#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) -#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) -#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) -#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) -#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) -#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) -#define TSB_PV_FR1_PV5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,5))) -#define TSB_PV_FR1_PV6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,6))) -#define TSB_PV_FR1_PV7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,7))) -#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) -#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) -#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) -#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) -#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) -#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) -#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) -#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) -#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) -#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) -#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) -#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) -#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) -#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) -#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) -#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) -#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) -#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) -#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) -#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) -#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) -#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) -#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) -#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) -#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) -#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) -#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) -#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) -#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) -#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) -#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) -#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) -#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) -#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) - - -/* */ -#define TSB_RTC_ADJCTL_AJEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJCTL,0))) -#define TSB_RTC_ADJSIGN_ADJSIGN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJSIGN,0))) - - -/* */ -#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) -#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) -#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) -#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) -#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) -#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) -#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) -#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) -#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) -#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) -#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) -#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) -#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) - - -/* */ -#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) -#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) -#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) -#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) - - -/* */ -#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) -#define TSB_CG_OSCCR_IHOSC2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,3))) -#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) -#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) -#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) -#define TSB_CG_OSCCR_IHOSC2F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,19))) -#define TSB_CG_SCOCR_SCOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SCOCR,0))) -#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) -#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) -#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) -#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) -#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) -#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) -#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) -#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) -#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) -#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) -#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) -#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) -#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) -#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) -#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) -#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) -#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) -#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) -#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) -#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) -#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) -#define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13))) -#define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14))) -#define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15))) -#define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16))) -#define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17))) -#define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18))) -#define TSB_CG_FSYSENA_IPENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,19))) -#define TSB_CG_FSYSENA_IPENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,20))) -#define TSB_CG_FSYSENA_IPENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,21))) -#define TSB_CG_FSYSENA_IPENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,22))) -#define TSB_CG_FSYSENA_IPENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,23))) -#define TSB_CG_FSYSENA_IPENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,24))) -#define TSB_CG_FSYSENA_IPENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,25))) -#define TSB_CG_FSYSENA_IPENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,26))) -#define TSB_CG_FSYSENA_IPENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,27))) -#define TSB_CG_FSYSENA_IPENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,28))) -#define TSB_CG_FSYSENA_IPENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,29))) -#define TSB_CG_FSYSENA_IPENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,30))) -#define TSB_CG_FSYSENA_IPENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,31))) -#define TSB_CG_FSYSENB_IPENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,0))) -#define TSB_CG_FSYSENB_IPENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,1))) -#define TSB_CG_FSYSENB_IPENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,2))) -#define TSB_CG_FSYSENB_IPENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,3))) -#define TSB_CG_FSYSENB_IPENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,4))) -#define TSB_CG_FSYSENB_IPENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,5))) -#define TSB_CG_FSYSENB_IPENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,6))) -#define TSB_CG_FSYSENB_IPENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,7))) -#define TSB_CG_FSYSENB_IPENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,8))) -#define TSB_CG_FSYSENB_IPENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,9))) -#define TSB_CG_FSYSENB_IPENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,10))) -#define TSB_CG_FSYSENB_IPENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,11))) -#define TSB_CG_FSYSENB_IPENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,12))) -#define TSB_CG_FSYSENB_IPENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,13))) -#define TSB_CG_FSYSENB_IPENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,14))) -#define TSB_CG_FSYSENB_IPENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,15))) -#define TSB_CG_FSYSENB_IPENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,16))) -#define TSB_CG_FSYSENB_IPENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,17))) -#define TSB_CG_FSYSENB_IPENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,18))) -#define TSB_CG_FSYSENB_IPENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,19))) -#define TSB_CG_FSYSENB_IPENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,20))) -#define TSB_CG_FSYSENB_IPENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,21))) -#define TSB_CG_FSYSENB_IPENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,22))) -#define TSB_CG_FSYSENB_IPENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,23))) -#define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31))) -#define TSB_CG_FCEN_FCIPEN07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,7))) -#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) -#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) - - -/* */ -#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) - - - -/* */ -#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) -#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) -#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) -#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) -#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) -#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) -#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) -#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) -#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) -#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) -#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) -#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) -#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) -#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) -#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) -#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) -#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) -#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) -#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) -#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) -#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) -#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) -#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) -#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) -#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) -#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) -#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) -#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) -#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) -#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) -#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) -#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) -#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) -#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) -#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) -#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) -#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) -#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) -#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) -#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) -#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) -#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) -#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) -#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) -#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) -#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) -#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) -#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) -#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) -#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) -#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) -#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) -#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) -#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) -#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) -#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) -#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) -#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) -#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) -#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) -#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) -#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) -#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) -#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) -#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) -#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) -#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) -#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) -#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) -#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) -#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) -#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) -#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) -#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) -#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) -#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) -#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) -#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) -#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) -#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) -#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) -#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) -#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) -#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) -#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) -#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) -#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) -#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) -#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) -#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) -#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) -#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) -#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) -#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) -#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) -#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) -#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) -#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) -#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) -#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) -#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) -#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) -#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) - - -/* */ -#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) -#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) -#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) -#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) -#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) -#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) -#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) -#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) -#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) -#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) -#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) -#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) -#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) -#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) -#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) -#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) -#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) -#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) -#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) -#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) -#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) -#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) -#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) -#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) -#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) -#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) -#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) -#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) -#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) -#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) -#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) -#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) -#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) -#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) -#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) -#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) -#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) -#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) -#define TSB_PMD0_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,0))) -#define TSB_PMD0_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,3))) -#define TSB_PMD0_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,4))) -#define TSB_PMD0_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,8))) -#define TSB_PMD0_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,9))) -#define TSB_PMD0_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,10))) -#define TSB_PMD0_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,12))) -#define TSB_PMD0_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,16))) -#define TSB_PMD0_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,17))) -#define TSB_PMD0_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,18))) -#define TSB_PMD0_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,19))) -#define TSB_PMD0_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,20))) -#define TSB_PMD0_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,21))) -#define TSB_PMD0_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,31))) - - -/* Encoder Input (ENC) */ -#define TSB_EN0_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,6))) -#define TSB_EN0_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,7))) -#define TSB_EN0_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,10))) -#define TSB_EN0_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,11))) -#define TSB_EN0_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,12))) -#define TSB_EN0_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,16))) -#define TSB_EN0_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,21))) -#define TSB_EN0_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,24))) -#define TSB_EN0_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,25))) -#define TSB_EN0_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,28))) -#define TSB_EN0_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,0))) -#define TSB_EN0_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,1))) -#define TSB_EN0_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,2))) -#define TSB_EN0_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,12))) -#define TSB_EN0_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,13))) -#define TSB_EN0_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,14))) -#define TSB_EN0_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,0))) -#define TSB_EN0_INPCR_SYNCSPLND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,1))) -#define TSB_EN0_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,2))) -#define TSB_EN0_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,6))) -#define TSB_EN0_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,7))) -#define TSB_EN0_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,0))) -#define TSB_EN0_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,1))) -#define TSB_EN0_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,2))) -#define TSB_EN0_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,4))) -#define TSB_EN0_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,5))) -#define TSB_EN0_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,6))) -#define TSB_EN0_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,0))) -#define TSB_EN0_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,1))) -#define TSB_EN0_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,2))) -#define TSB_EN0_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,3))) -#define TSB_EN0_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,4))) -#define TSB_EN0_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,5))) -#define TSB_EN0_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,0))) -#define TSB_EN0_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,1))) -#define TSB_EN0_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,2))) -#define TSB_EN0_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,3))) -#define TSB_EN0_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,4))) -#define TSB_EN0_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,5))) - -/** @} */ /* End of group Device_Peripheral_registers */ - -#ifdef __cplusplus -} -#endif - -#endif /* __TMPM3HQ_H__ */ - -/** @} */ /* End of group TMPM3HQ */ -/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S deleted file mode 100644 index da09c62e25a..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S +++ /dev/null @@ -1,614 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM3HQ.s -; * @brief CMSIS Cortex-M3 Core Device Startup File for the -; * TOSHIBA 'TMPM3HQ' Device Series -; * @version V1.0.0.0 -; * $Date:: 2017-12-08 #$ -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt Pin 00 - DCD INT01_IRQHandler ; 1: Interrupt Pin 01 - DCD INT02_IRQHandler ; 2: Interrupt Pin 02 - DCD INT03_IRQHandler ; 3: Interrupt Pin 03 - DCD INT04_IRQHandler ; 4: Interrupt Pin 04 - DCD INT05_IRQHandler ; 5: Interrupt Pin 05 - DCD INT06_IRQHandler ; 6: Interrupt Pin 06 - DCD INT07_IRQHandler ; 7: Interrupt Pin 07 - DCD INT08_IRQHandler ; 8: Interrupt Pin 08 - DCD INT09_IRQHandler ; 9: Interrupt Pin 09 - DCD INT10_IRQHandler ; 10: Interrupt Pin 10 - DCD INT11_IRQHandler ; 11: Interrupt Pin 11 - DCD INT12_IRQHandler ; 12: Interrupt Pin 12 - DCD INT13_IRQHandler ; 13: Interrupt Pin 13 - DCD INT14_IRQHandler ; 14: Interrupt Pin 14 - DCD INT15_IRQHandler ; 15: Interrupt Pin 15 - DCD INT16_IRQHandler ; 16: Interrupt Pin 16 - DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18 - DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22 - DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26 - DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28 - DCD INT29_IRQHandler ; 21: Interrupt Pin 29 - DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31 - DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt - DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt - DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0 - DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1 - DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A - DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B - DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished - DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4) - DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0) - DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt - DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt - DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt - DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt - DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt - DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5) - DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0 - DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1 - DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0 - DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1 - DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0 - DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1 - DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0 - DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1 - DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0 - DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1 - DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0 - DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1 - DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0 - DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1 - DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0 - DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1 - DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0 - DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1 - DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0 - DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1 - DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0 - DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1 - DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0 - DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1 - DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0 - DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1 - DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0 - DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1 - DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0 - DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1 - DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0 - DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1 - DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0 - DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1 - DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0 - DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1 - DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0 - DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1 - DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0 - DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1 - DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0 - DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1 - DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0 - DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1 - DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0 - DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1 - DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0 - DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1 - DCD INTPARI_IRQHandler ; 157: RAM parity interrupt - DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer - DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error - DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer - DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error - DCD INTRTC_IRQHandler ; 162: Real time clock interrupt - DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt - DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt - DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt - - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT INT00_IRQHandler [WEAK] - EXPORT INT01_IRQHandler [WEAK] - EXPORT INT02_IRQHandler [WEAK] - EXPORT INT03_IRQHandler [WEAK] - EXPORT INT04_IRQHandler [WEAK] - EXPORT INT05_IRQHandler [WEAK] - EXPORT INT06_IRQHandler [WEAK] - EXPORT INT07_IRQHandler [WEAK] - EXPORT INT08_IRQHandler [WEAK] - EXPORT INT09_IRQHandler [WEAK] - EXPORT INT10_IRQHandler [WEAK] - EXPORT INT11_IRQHandler [WEAK] - EXPORT INT12_IRQHandler [WEAK] - EXPORT INT13_IRQHandler [WEAK] - EXPORT INT14_IRQHandler [WEAK] - EXPORT INT15_IRQHandler [WEAK] - EXPORT INT16_IRQHandler [WEAK] - EXPORT INT17_18_IRQHandler [WEAK] - EXPORT INT19_22_IRQHandler [WEAK] - EXPORT INT23_26_IRQHandler [WEAK] - EXPORT INT27_28_IRQHandler [WEAK] - EXPORT INT29_IRQHandler [WEAK] - EXPORT INT30_31_IRQHandler [WEAK] - EXPORT INTEMG0_IRQHandler [WEAK] - EXPORT INTOVV0_IRQHandler [WEAK] - EXPORT INTPMD0_IRQHandler [WEAK] - EXPORT INTENC00_IRQHandler [WEAK] - EXPORT INTENC01_IRQHandler [WEAK] - EXPORT INTADAPDA_IRQHandler [WEAK] - EXPORT INTADAPDB_IRQHandler [WEAK] - EXPORT INTADACP0_IRQHandler [WEAK] - EXPORT INTADACP1_IRQHandler [WEAK] - EXPORT INTADATRG_IRQHandler [WEAK] - EXPORT INTADASGL_IRQHandler [WEAK] - EXPORT INTADACNT_IRQHandler [WEAK] - EXPORT INTT0RX_IRQHandler [WEAK] - EXPORT INTT0TX_IRQHandler [WEAK] - EXPORT INTT0ERR_IRQHandler [WEAK] - EXPORT INTT1RX_IRQHandler [WEAK] - EXPORT INTT1TX_IRQHandler [WEAK] - EXPORT INTT1ERR_IRQHandler [WEAK] - EXPORT INTT2RX_IRQHandler [WEAK] - EXPORT INTT2TX_IRQHandler [WEAK] - EXPORT INTT2ERR_IRQHandler [WEAK] - EXPORT INTT3RX_IRQHandler [WEAK] - EXPORT INTT3TX_IRQHandler [WEAK] - EXPORT INTT3ERR_IRQHandler [WEAK] - EXPORT INTT4RX_IRQHandler [WEAK] - EXPORT INTT4TX_IRQHandler [WEAK] - EXPORT INTT4ERR_IRQHandler [WEAK] - EXPORT INTI2CWUP_IRQHandler [WEAK] - EXPORT INTI2C0_IRQHandler [WEAK] - EXPORT INTI2C0AL_IRQHandler [WEAK] - EXPORT INTI2C0BF_IRQHandler [WEAK] - EXPORT INTI2C0NA_IRQHandler [WEAK] - EXPORT INTI2C1_IRQHandler [WEAK] - EXPORT INTI2C1AL_IRQHandler [WEAK] - EXPORT INTI2C1BF_IRQHandler [WEAK] - EXPORT INTI2C1NA_IRQHandler [WEAK] - EXPORT INTI2C2_IRQHandler [WEAK] - EXPORT INTI2C2AL_IRQHandler [WEAK] - EXPORT INTI2C2BF_IRQHandler [WEAK] - EXPORT INTI2C2NA_IRQHandler [WEAK] - EXPORT INTI2C3_IRQHandler [WEAK] - EXPORT INTI2C3AL_IRQHandler [WEAK] - EXPORT INTI2C3BF_IRQHandler [WEAK] - EXPORT INTI2C3NA_IRQHandler [WEAK] - EXPORT INTUART0RX_IRQHandler [WEAK] - EXPORT INTUART0TX_IRQHandler [WEAK] - EXPORT INTUART0ERR_IRQHandler [WEAK] - EXPORT INTUART1RX_IRQHandler [WEAK] - EXPORT INTUART1TX_IRQHandler [WEAK] - EXPORT INTUART1ERR_IRQHandler [WEAK] - EXPORT INTUART2RX_IRQHandler [WEAK] - EXPORT INTUART2TX_IRQHandler [WEAK] - EXPORT INTUART2ERR_IRQHandler [WEAK] - EXPORT INTUART3RX_IRQHandler [WEAK] - EXPORT INTUART3TX_IRQHandler [WEAK] - EXPORT INTUART3ERR_IRQHandler [WEAK] - EXPORT INTUART4RX_IRQHandler [WEAK] - EXPORT INTUART4TX_IRQHandler [WEAK] - EXPORT INTUART4ERR_IRQHandler [WEAK] - EXPORT INTUART5RX_IRQHandler [WEAK] - EXPORT INTUART5TX_IRQHandler [WEAK] - EXPORT INTUART5ERR_IRQHandler [WEAK] - EXPORT INTT32A00A_IRQHandler [WEAK] - EXPORT INTT32A00ACAP0_IRQHandler [WEAK] - EXPORT INTT32A00ACAP1_IRQHandler [WEAK] - EXPORT INTT32A00B_IRQHandler [WEAK] - EXPORT INTT32A00BCAP0_IRQHandler [WEAK] - EXPORT INTT32A00BCAP1_IRQHandler [WEAK] - EXPORT INTT32A00C_IRQHandler [WEAK] - EXPORT INTT32A00CCAP0_IRQHandler [WEAK] - EXPORT INTT32A00CCAP1_IRQHandler [WEAK] - EXPORT INTT32A01A_IRQHandler [WEAK] - EXPORT INTT32A01ACAP0_IRQHandler [WEAK] - EXPORT INTT32A01ACAP1_IRQHandler [WEAK] - EXPORT INTT32A01B_IRQHandler [WEAK] - EXPORT INTT32A01BCAP0_IRQHandler [WEAK] - EXPORT INTT32A01BCAP1_IRQHandler [WEAK] - EXPORT INTT32A01C_IRQHandler [WEAK] - EXPORT INTT32A01CCAP0_IRQHandler [WEAK] - EXPORT INTT32A01CCAP1_IRQHandler [WEAK] - EXPORT INTT32A02A_IRQHandler [WEAK] - EXPORT INTT32A02ACAP0_IRQHandler [WEAK] - EXPORT INTT32A02ACAP1_IRQHandler [WEAK] - EXPORT INTT32A02B_IRQHandler [WEAK] - EXPORT INTT32A02BCAP0_IRQHandler [WEAK] - EXPORT INTT32A02BCAP1_IRQHandler [WEAK] - EXPORT INTT32A02C_IRQHandler [WEAK] - EXPORT INTT32A02CCAP0_IRQHandler [WEAK] - EXPORT INTT32A02CCAP1_IRQHandler [WEAK] - EXPORT INTT32A03A_IRQHandler [WEAK] - EXPORT INTT32A03ACAP0_IRQHandler [WEAK] - EXPORT INTT32A03ACAP1_IRQHandler [WEAK] - EXPORT INTT32A03B_IRQHandler [WEAK] - EXPORT INTT32A03BCAP0_IRQHandler [WEAK] - EXPORT INTT32A03BCAP1_IRQHandler [WEAK] - EXPORT INTT32A03C_IRQHandler [WEAK] - EXPORT INTT32A03CCAP0_IRQHandler [WEAK] - EXPORT INTT32A03CCAP1_IRQHandler [WEAK] - EXPORT INTT32A04A_IRQHandler [WEAK] - EXPORT INTT32A04ACAP0_IRQHandler [WEAK] - EXPORT INTT32A04ACAP1_IRQHandler [WEAK] - EXPORT INTT32A04B_IRQHandler [WEAK] - EXPORT INTT32A04BCAP0_IRQHandler [WEAK] - EXPORT INTT32A04BCAP1_IRQHandler [WEAK] - EXPORT INTT32A04C_IRQHandler [WEAK] - EXPORT INTT32A04CCAP0_IRQHandler [WEAK] - EXPORT INTT32A04CCAP1_IRQHandler [WEAK] - EXPORT INTT32A05A_IRQHandler [WEAK] - EXPORT INTT32A05ACAP0_IRQHandler [WEAK] - EXPORT INTT32A05ACAP1_IRQHandler [WEAK] - EXPORT INTT32A05B_IRQHandler [WEAK] - EXPORT INTT32A05BCAP0_IRQHandler [WEAK] - EXPORT INTT32A05BCAP1_IRQHandler [WEAK] - EXPORT INTT32A05C_IRQHandler [WEAK] - EXPORT INTT32A05CCAP0_IRQHandler [WEAK] - EXPORT INTT32A05CCAP1_IRQHandler [WEAK] - EXPORT INTT32A06A_IRQHandler [WEAK] - EXPORT INTT32A06ACAP0_IRQHandler [WEAK] - EXPORT INTT32A06ACAP1_IRQHandler [WEAK] - EXPORT INTT32A06B_IRQHandler [WEAK] - EXPORT INTT32A06BCAP0_IRQHandler [WEAK] - EXPORT INTT32A06BCAP1_IRQHandler [WEAK] - EXPORT INTT32A06C_IRQHandler [WEAK] - EXPORT INTT32A06CCAP0_IRQHandler [WEAK] - EXPORT INTT32A06CCAP1_IRQHandler [WEAK] - EXPORT INTT32A07A_IRQHandler [WEAK] - EXPORT INTT32A07ACAP0_IRQHandler [WEAK] - EXPORT INTT32A07ACAP1_IRQHandler [WEAK] - EXPORT INTT32A07B_IRQHandler [WEAK] - EXPORT INTT32A07BCAP0_IRQHandler [WEAK] - EXPORT INTT32A07BCAP1_IRQHandler [WEAK] - EXPORT INTT32A07C_IRQHandler [WEAK] - EXPORT INTT32A07CCAP0_IRQHandler [WEAK] - EXPORT INTT32A07CCAP1_IRQHandler [WEAK] - EXPORT INTPARI_IRQHandler [WEAK] - EXPORT INTDMAATC_IRQHandler [WEAK] - EXPORT INTDMAAERR_IRQHandler [WEAK] - EXPORT INTDMABTC_IRQHandler [WEAK] - EXPORT INTDMABERR_IRQHandler [WEAK] - EXPORT INTRTC_IRQHandler [WEAK] - EXPORT INTRMC0_IRQHandler [WEAK] - EXPORT INTFLCRDY_IRQHandler [WEAK] - EXPORT INTFLDRDY_IRQHandler [WEAK] - -INT00_IRQHandler -INT01_IRQHandler -INT02_IRQHandler -INT03_IRQHandler -INT04_IRQHandler -INT05_IRQHandler -INT06_IRQHandler -INT07_IRQHandler -INT08_IRQHandler -INT09_IRQHandler -INT10_IRQHandler -INT11_IRQHandler -INT12_IRQHandler -INT13_IRQHandler -INT14_IRQHandler -INT15_IRQHandler -INT16_IRQHandler -INT17_18_IRQHandler -INT19_22_IRQHandler -INT23_26_IRQHandler -INT27_28_IRQHandler -INT29_IRQHandler -INT30_31_IRQHandler -INTEMG0_IRQHandler -INTOVV0_IRQHandler -INTPMD0_IRQHandler -INTENC00_IRQHandler -INTENC01_IRQHandler -INTADAPDA_IRQHandler -INTADAPDB_IRQHandler -INTADACP0_IRQHandler -INTADACP1_IRQHandler -INTADATRG_IRQHandler -INTADASGL_IRQHandler -INTADACNT_IRQHandler -INTT0RX_IRQHandler -INTT0TX_IRQHandler -INTT0ERR_IRQHandler -INTT1RX_IRQHandler -INTT1TX_IRQHandler -INTT1ERR_IRQHandler -INTT2RX_IRQHandler -INTT2TX_IRQHandler -INTT2ERR_IRQHandler -INTT3RX_IRQHandler -INTT3TX_IRQHandler -INTT3ERR_IRQHandler -INTT4RX_IRQHandler -INTT4TX_IRQHandler -INTT4ERR_IRQHandler -INTI2CWUP_IRQHandler -INTI2C0_IRQHandler -INTI2C0AL_IRQHandler -INTI2C0BF_IRQHandler -INTI2C0NA_IRQHandler -INTI2C1_IRQHandler -INTI2C1AL_IRQHandler -INTI2C1BF_IRQHandler -INTI2C1NA_IRQHandler -INTI2C2_IRQHandler -INTI2C2AL_IRQHandler -INTI2C2BF_IRQHandler -INTI2C2NA_IRQHandler -INTI2C3_IRQHandler -INTI2C3AL_IRQHandler -INTI2C3BF_IRQHandler -INTI2C3NA_IRQHandler -INTUART0RX_IRQHandler -INTUART0TX_IRQHandler -INTUART0ERR_IRQHandler -INTUART1RX_IRQHandler -INTUART1TX_IRQHandler -INTUART1ERR_IRQHandler -INTUART2RX_IRQHandler -INTUART2TX_IRQHandler -INTUART2ERR_IRQHandler -INTUART3RX_IRQHandler -INTUART3TX_IRQHandler -INTUART3ERR_IRQHandler -INTUART4RX_IRQHandler -INTUART4TX_IRQHandler -INTUART4ERR_IRQHandler -INTUART5RX_IRQHandler -INTUART5TX_IRQHandler -INTUART5ERR_IRQHandler -INTT32A00A_IRQHandler -INTT32A00ACAP0_IRQHandler -INTT32A00ACAP1_IRQHandler -INTT32A00B_IRQHandler -INTT32A00BCAP0_IRQHandler -INTT32A00BCAP1_IRQHandler -INTT32A00C_IRQHandler -INTT32A00CCAP0_IRQHandler -INTT32A00CCAP1_IRQHandler -INTT32A01A_IRQHandler -INTT32A01ACAP0_IRQHandler -INTT32A01ACAP1_IRQHandler -INTT32A01B_IRQHandler -INTT32A01BCAP0_IRQHandler -INTT32A01BCAP1_IRQHandler -INTT32A01C_IRQHandler -INTT32A01CCAP0_IRQHandler -INTT32A01CCAP1_IRQHandler -INTT32A02A_IRQHandler -INTT32A02ACAP0_IRQHandler -INTT32A02ACAP1_IRQHandler -INTT32A02B_IRQHandler -INTT32A02BCAP0_IRQHandler -INTT32A02BCAP1_IRQHandler -INTT32A02C_IRQHandler -INTT32A02CCAP0_IRQHandler -INTT32A02CCAP1_IRQHandler -INTT32A03A_IRQHandler -INTT32A03ACAP0_IRQHandler -INTT32A03ACAP1_IRQHandler -INTT32A03B_IRQHandler -INTT32A03BCAP0_IRQHandler -INTT32A03BCAP1_IRQHandler -INTT32A03C_IRQHandler -INTT32A03CCAP0_IRQHandler -INTT32A03CCAP1_IRQHandler -INTT32A04A_IRQHandler -INTT32A04ACAP0_IRQHandler -INTT32A04ACAP1_IRQHandler -INTT32A04B_IRQHandler -INTT32A04BCAP0_IRQHandler -INTT32A04BCAP1_IRQHandler -INTT32A04C_IRQHandler -INTT32A04CCAP0_IRQHandler -INTT32A04CCAP1_IRQHandler -INTT32A05A_IRQHandler -INTT32A05ACAP0_IRQHandler -INTT32A05ACAP1_IRQHandler -INTT32A05B_IRQHandler -INTT32A05BCAP0_IRQHandler -INTT32A05BCAP1_IRQHandler -INTT32A05C_IRQHandler -INTT32A05CCAP0_IRQHandler -INTT32A05CCAP1_IRQHandler -INTT32A06A_IRQHandler -INTT32A06ACAP0_IRQHandler -INTT32A06ACAP1_IRQHandler -INTT32A06B_IRQHandler -INTT32A06BCAP0_IRQHandler -INTT32A06BCAP1_IRQHandler -INTT32A06C_IRQHandler -INTT32A06CCAP0_IRQHandler -INTT32A06CCAP1_IRQHandler -INTT32A07A_IRQHandler -INTT32A07ACAP0_IRQHandler -INTT32A07ACAP1_IRQHandler -INTT32A07B_IRQHandler -INTT32A07BCAP0_IRQHandler -INTT32A07BCAP1_IRQHandler -INTT32A07C_IRQHandler -INTT32A07CCAP0_IRQHandler -INTT32A07CCAP1_IRQHandler -INTPARI_IRQHandler -INTDMAATC_IRQHandler -INTDMAAERR_IRQHandler -INTDMABTC_IRQHandler -INTDMABERR_IRQHandler -INTRTC_IRQHandler -INTRMC0_IRQHandler -INTFLCRDY_IRQHandler -INTFLDRDY_IRQHandler - - B . - - ENDP - - ALIGN - END - diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct deleted file mode 100644 index d0e8c1b2a2b..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct +++ /dev/null @@ -1,39 +0,0 @@ -#! armcc -E -;; TMPM3HQFDFG scatter file - -;; Vector table starts at 0 -;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) -;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) -;; Initial PC == &__main (with LSB set to indicate Thumb) -;; These two values are provided by the library -;; Other vectors must be provided by the user -;; Code starts after the last possible vector -;; Data starts at 0x20000000 -;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) -;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) - -;; Compatible with ISSM model - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x80000 -{ - ER_IROM1 0x00000000 0x80000 - { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 0x200002D8 (0x10000 - 0x2D8) - { - .ANY (+RW, +ZI) - } - - ARM_LIB_STACK 0x200002D8+0x10000 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S deleted file mode 100644 index 113531b7715..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S +++ /dev/null @@ -1,582 +0,0 @@ -/** - ******************************************************************************* - * @file startup_TMPM3HQ.s - * @brief CMSIS Cortex-M3 Core Device Startup File for the - * TOSHIBA 'TMPM3HQ' Device Series - * @version V5.00 - * @date 2016/03/02 - *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - * - * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved - ******************************************************************************* - */ - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.if Heap_Size -.space Heap_Size -.endif -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop // Top of Stack - .long Reset_Handler // Reset Handler - .long NMI_Handler // NMI Handler - .long HardFault_Handler // Hard Fault Handler - .long MemManage_Handler // MPU Fault Handler - .long BusFault_Handler // Bus Fault Handler - .long UsageFault_Handler // Usage Fault Handler - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long SVC_Handler // SVCall Handler - .long DebugMon_Handler // Debug Monitor Handler - .long 0 // Reserved - .long PendSV_Handler // PendSV Handler - .long SysTick_Handler // SysTick Handler - - // External interrupts - .long INT00_IRQHandler // 0: Interrupt Pin0 - .long INT01_IRQHandler // 1: Interrupt Pin1 - .long INT02_IRQHandler // 2: Interrupt Pin2 - .long INT03_IRQHandler // 3: Interrupt Pin3 - .long INT04_IRQHandler // 4: Interrupt Pin4 - .long INT05_IRQHandler // 5: Interrupt Pin5 - .long INT06_IRQHandler // 6: Interrupt Pin6 - .long INT07_IRQHandler // 7: Interrupt Pin7 - .long INT08_IRQHandler // 8: Interrupt Pin8 - .long INT09_IRQHandler // 9: Interrupt Pin9 - .long INT10_IRQHandler // 10: Interrupt Pin10 - .long INT11_IRQHandler // 11: Interrupt Pin11 - .long INT12_IRQHandler // 12: Interrupt Pin12 - .long INT13_IRQHandler // 13: Interrupt Pin13 - .long INT14_IRQHandler // 14: Interrupt Pin14 - .long INT15_IRQHandler // 15: Interrupt Pin15 - .long INT16_IRQHandler // 16: Interrupt Pin 16 - .long INT17_18_IRQHandler // 17: Interrupt Pin 17_18 - .long INT19_22_IRQHandler // 18: Interrupt Pin 19_22 - .long INT23_26_IRQHandler // 19: Interrupt Pin 23_26 - .long INT27_28_IRQHandler // 20: Interrupt Pin 27_28 - .long INT29_IRQHandler // 21: Interrupt Pin 29 - .long INT30_31_IRQHandler // 22: Interrupt Pin 30_31 - .long INTEMG0_IRQHandler // 23: PMD0 EMG interrupt - .long INTOVV0_IRQHandler // 24: PMD0 OVV interrupt - .long INTPMD0_IRQHandler // 25: PMD0 interrupt - .long INTENC00_IRQHandler // 26: Encoder 0 interrupt 0 - .long INTENC01_IRQHandler // 27: Encoder 0 interrupt 1 - .long INTADAPDA_IRQHandler // 28: ADC conversion triggered by PMD is finished A - .long INTADAPDB_IRQHandler // 29: ADC conversion triggered by PMD is finished B - .long INTADACP0_IRQHandler // 30: ADC conversion monitoring function interrupt 0 - .long INTADACP1_IRQHandler // 31: ADC conversion monitoring function interrupt 1 - .long INTADATRG_IRQHandler // 32: ADC conversion triggered by General purpose is finished - .long INTADASGL_IRQHandler // 33: ADC conversion triggered by Single program is finished - .long INTADACNT_IRQHandler // 34: ADC conversion triggered by Continuity program is finished - .long INTT0RX_IRQHandler // 35: TSPI/SIO reception (channel 0) - .long INTT0TX_IRQHandler // 36: TSPI/SIO transmit (channel 0) - .long INTT0ERR_IRQHandler // 37: TSPI/SIO error (channel 0) - .long INTT1RX_IRQHandler // 38: TSPI/SIO reception (channel 1) - .long INTT1TX_IRQHandler // 39: TSPI/SIO transmit (channel 1) - .long INTT1ERR_IRQHandler // 40: TSPI/SIO error (channel 1) - .long INTT2RX_IRQHandler // 41: TSPI/SIO reception (channel 2) - .long INTT2TX_IRQHandler // 42: TSPI/SIO transmit (channel 2) - .long INTT2ERR_IRQHandler // 43: TSPI/SIO error (channel 2) - .long INTT3RX_IRQHandler // 44: TSPI/SIO reception (channel 3) - .long INTT3TX_IRQHandler // 45: TSPI/SIO transmit (channel 3) - .long INTT3ERR_IRQHandler // 46: TSPI/SIO error (channel 3) - .long INTT4RX_IRQHandler // 47: TSPI/SIO reception (channel 4) - .long INTT4TX_IRQHandler // 48: TSPI/SIO transmit (channel 4) - .long INTT4ERR_IRQHandler // 49: TSPI/SIO error (channel 4) - .long INTI2CWUP_IRQHandler // 50: Serial bus interface (WakeUp) interrupt (channel 0) - .long INTI2C0_IRQHandler // 51: I2C0 transmission and reception interrupt - .long INTI2C0AL_IRQHandler // 52: I2C0 arbitration lost interrupt - .long INTI2C0BF_IRQHandler // 53: I2C0 bus free interrupt - .long INTI2C0NA_IRQHandler // 54: I2C0 no ack interrupt - .long INTI2C1_IRQHandler // 55: I2C1 transmission and reception interrupt - .long INTI2C1AL_IRQHandler // 56: I2C1 arbitration lost interrupt - .long INTI2C1BF_IRQHandler // 57: I2C1 bus free interrupt - .long INTI2C1NA_IRQHandler // 58: I2C1 no ack interrupt - .long INTI2C2_IRQHandler // 59: I2C2 transmission and reception interrupt - .long INTI2C2AL_IRQHandler // 60: I2C2 arbitration lost interrupt - .long INTI2C2BF_IRQHandler // 61: I2C2 bus free interrupt - .long INTI2C2NA_IRQHandler // 62: I2C2 no ack interrupt - .long INTI2C3_IRQHandler // 63: I2C3 transmission and reception interrupt - .long INTI2C3AL_IRQHandler // 64: I2C3 arbitration lost interrupt - .long INTI2C3BF_IRQHandler // 65: I2C3 bus free interrupt - .long INTI2C3NA_IRQHandler // 66: I2C3 no ack interrupt - .long INTUART0RX_IRQHandler // 67: UART reception (channel 0) - .long INTUART0TX_IRQHandler // 68: UART transmit (channel 0) - .long INTUART0ERR_IRQHandler // 69: UART error (channel 0) - .long INTUART1RX_IRQHandler // 70: UART reception (channel 1) - .long INTUART1TX_IRQHandler // 71: UART transmit (channel 1) - .long INTUART1ERR_IRQHandler // 72: UART error (channel 1) - .long INTUART2RX_IRQHandler // 73: UART reception (channel 2) - .long INTUART2TX_IRQHandler // 74: UART transmit (channel 2) - .long INTUART2ERR_IRQHandler // 75: UART error (channel 2) - .long INTUART3RX_IRQHandler // 76: UART reception (channel 3) - .long INTUART3TX_IRQHandler // 77: UART transmit (channel 3) - .long INTUART3ERR_IRQHandler // 78: UART error (channel 3) - .long INTUART4RX_IRQHandler // 79: UART reception (channel 4) - .long INTUART4TX_IRQHandler // 80: UART transmit (channel 4) - .long INTUART4ERR_IRQHandler // 81: UART error (channel 4) - .long INTUART5RX_IRQHandler // 82: UART reception (channel 5) - .long INTUART5TX_IRQHandler // 83: UART transmit (channel 5) - .long INTUART5ERR_IRQHandler // 84: UART error (channel 5) - .long INTT32A00A_IRQHandler // 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - .long INTT32A00ACAP0_IRQHandler // 86: 32bit T32A00A input capture 0 - .long INTT32A00ACAP1_IRQHandler // 87: 32bit T32A00A input capture 1 - .long INTT32A00B_IRQHandler // 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - .long INTT32A00BCAP0_IRQHandler // 89: 32bit T32A00B input capture 0 - .long INTT32A00BCAP1_IRQHandler // 90: 32bit T32A00B input capture 1 - .long INTT32A00C_IRQHandler // 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - .long INTT32A00CCAP0_IRQHandler // 92: 32bit T32A00C input capture 0 - .long INTT32A00CCAP1_IRQHandler // 93: 32bit T32A00C input capture 1 - .long INTT32A01A_IRQHandler // 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - .long INTT32A01ACAP0_IRQHandler // 95: 32bit T32A01A input capture 0 - .long INTT32A01ACAP1_IRQHandler // 96: 32bit T32A01A input capture 1 - .long INTT32A01B_IRQHandler // 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - .long INTT32A01BCAP0_IRQHandler // 98: 32bit T32A01B input capture 0 - .long INTT32A01BCAP1_IRQHandler // 99: 32bit T32A01B input capture 1 - .long INTT32A01C_IRQHandler // 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - .long INTT32A01CCAP0_IRQHandler // 101: 32bit T32A01C input capture 0 - .long INTT32A01CCAP1_IRQHandler // 102: 32bit T32A01C input capture 1 - .long INTT32A02A_IRQHandler // 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - .long INTT32A02ACAP0_IRQHandler // 104: 32bit T32A02A input capture 0 - .long INTT32A02ACAP1_IRQHandler // 105: 32bit T32A02A input capture 1 - .long INTT32A02B_IRQHandler // 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - .long INTT32A02BCAP0_IRQHandler // 107: 32bit T32A02B input capture 0 - .long INTT32A02BCAP1_IRQHandler // 108: 32bit T32A02B input capture 1 - .long INTT32A02C_IRQHandler // 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - .long INTT32A02CCAP0_IRQHandler // 110: 32bit T32A02C input capture 0 - .long INTT32A02CCAP1_IRQHandler // 111: 32bit T32A02C input capture 1 - .long INTT32A03A_IRQHandler // 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - .long INTT32A03ACAP0_IRQHandler // 113: 32bit T32A03A input capture 0 - .long INTT32A03ACAP1_IRQHandler // 114: 32bit T32A03A input capture 1 - .long INTT32A03B_IRQHandler // 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - .long INTT32A03BCAP0_IRQHandler // 116: 32bit T32A03B input capture 0 - .long INTT32A03BCAP1_IRQHandler // 117: 32bit T32A03B input capture 1 - .long INTT32A03C_IRQHandler // 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - .long INTT32A03CCAP0_IRQHandler // 119: 32bit T32A03C input capture 0 - .long INTT32A03CCAP1_IRQHandler // 120: 32bit T32A03C input capture 1 - .long INTT32A04A_IRQHandler // 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - .long INTT32A04ACAP0_IRQHandler // 122: 32bit T32A04A input capture 0 - .long INTT32A04ACAP1_IRQHandler // 123: 32bit T32A04A input capture 1 - .long INTT32A04B_IRQHandler // 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - .long INTT32A04BCAP0_IRQHandler // 125: 32bit T32A04B input capture 0 - .long INTT32A04BCAP1_IRQHandler // 126: 32bit T32A04B input capture 1 - .long INTT32A04C_IRQHandler // 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - .long INTT32A04CCAP0_IRQHandler // 128: 32bit T32A04C input capture 0 - .long INTT32A04CCAP1_IRQHandler // 129: 32bit T32A04C input capture 1 - .long INTT32A05A_IRQHandler // 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - .long INTT32A05ACAP0_IRQHandler // 131: 32bit T32A05A input capture 0 - .long INTT32A05ACAP1_IRQHandler // 132: 32bit T32A05A input capture 1 - .long INTT32A05B_IRQHandler // 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - .long INTT32A05BCAP0_IRQHandler // 134: 32bit T32A05B input capture 0 - .long INTT32A05BCAP1_IRQHandler // 135: 32bit T32A05B input capture 1 - .long INTT32A05C_IRQHandler // 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - .long INTT32A05CCAP0_IRQHandler // 137: 32bit T32A05C input capture 0 - .long INTT32A05CCAP1_IRQHandler // 138: 32bit T32A05C input capture 1 - .long INTT32A06A_IRQHandler // 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - .long INTT32A06ACAP0_IRQHandler // 140: 32bit T32A06A input capture 0 - .long INTT32A06ACAP1_IRQHandler // 141: 32bit T32A06A input capture 1 - .long INTT32A06B_IRQHandler // 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - .long INTT32A06BCAP0_IRQHandler // 143: 32bit T32A06B input capture 0 - .long INTT32A06BCAP1_IRQHandler // 144: 32bit T32A06B input capture 1 - .long INTT32A06C_IRQHandler // 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - .long INTT32A06CCAP0_IRQHandler // 146: 32bit T32A06C input capture 0 - .long INTT32A06CCAP1_IRQHandler // 147: 32bit T32A06C input capture 1 - .long INTT32A07A_IRQHandler // 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - .long INTT32A07ACAP0_IRQHandler // 149: 32bit T32A07A input capture 0 - .long INTT32A07ACAP1_IRQHandler // 150: 32bit T32A07A input capture 1 - .long INTT32A07B_IRQHandler // 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - .long INTT32A07BCAP0_IRQHandler // 152: 32bit T32A07B input capture 0 - .long INTT32A07BCAP1_IRQHandler // 153: 32bit T32A07B input capture 1 - .long INTT32A07C_IRQHandler // 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - .long INTT32A07CCAP0_IRQHandler // 155: 32bit T32A07C input capture 0 - .long INTT32A07CCAP1_IRQHandler // 156: 32bit T32A07C input capture 1 - .long INTPARI_IRQHandler // 157: RAM parity interrupt - .long INTDMAATC_IRQHandler // 158: DMAA end of transfer - .long INTDMAAERR_IRQHandler // 159: DMAA transfer error - .long INTDMABTC_IRQHandler // 160: DMAB end of transfer - .long INTDMABERR_IRQHandler // 161: DMAB transfer error - .long INTRTC_IRQHandler // 162: Real time clock interrupt - .long INTRMC0_IRQHandler // 163: Remote control reception interrupt - .long INTFLCRDY_IRQHandler // 164: Code FLASH Ready interrupt - .long INTFLDRDY_IRQHandler // 165: Data FLASH Ready interrupt - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler INT00_IRQHandler - def_irq_handler INT01_IRQHandler - def_irq_handler INT02_IRQHandler - def_irq_handler INT03_IRQHandler - def_irq_handler INT04_IRQHandler - def_irq_handler INT05_IRQHandler - def_irq_handler INT06_IRQHandler - def_irq_handler INT07_IRQHandler - def_irq_handler INT08_IRQHandler - def_irq_handler INT09_IRQHandler - def_irq_handler INT10_IRQHandler - def_irq_handler INT11_IRQHandler - def_irq_handler INT12_IRQHandler - def_irq_handler INT13_IRQHandler - def_irq_handler INT14_IRQHandler - def_irq_handler INT15_IRQHandler - def_irq_handler INT16_IRQHandler - def_irq_handler INT17_18_IRQHandler - def_irq_handler INT19_22_IRQHandler - def_irq_handler INT23_26_IRQHandler - def_irq_handler INT27_28_IRQHandler - def_irq_handler INT29_IRQHandler - def_irq_handler INT30_31_IRQHandler - def_irq_handler INTEMG0_IRQHandler - def_irq_handler INTOVV0_IRQHandler - def_irq_handler INTPMD0_IRQHandler - def_irq_handler INTENC00_IRQHandler - def_irq_handler INTENC01_IRQHandler - def_irq_handler INTADAPDA_IRQHandler - def_irq_handler INTADAPDB_IRQHandler - def_irq_handler INTADACP0_IRQHandler - def_irq_handler INTADACP1_IRQHandler - def_irq_handler INTADATRG_IRQHandler - def_irq_handler INTADASGL_IRQHandler - def_irq_handler INTADACNT_IRQHandler - def_irq_handler INTT0RX_IRQHandler - def_irq_handler INTT0TX_IRQHandler - def_irq_handler INTT0ERR_IRQHandler - def_irq_handler INTT1RX_IRQHandler - def_irq_handler INTT1TX_IRQHandler - def_irq_handler INTT1ERR_IRQHandler - def_irq_handler INTT2RX_IRQHandler - def_irq_handler INTT2TX_IRQHandler - def_irq_handler INTT2ERR_IRQHandler - def_irq_handler INTT3RX_IRQHandler - def_irq_handler INTT3TX_IRQHandler - def_irq_handler INTT3ERR_IRQHandler - def_irq_handler INTT4RX_IRQHandler - def_irq_handler INTT4TX_IRQHandler - def_irq_handler INTT4ERR_IRQHandler - def_irq_handler INTI2CWUP_IRQHandler - def_irq_handler INTI2C0_IRQHandler - def_irq_handler INTI2C0AL_IRQHandler - def_irq_handler INTI2C0BF_IRQHandler - def_irq_handler INTI2C0NA_IRQHandler - def_irq_handler INTI2C1_IRQHandler - def_irq_handler INTI2C1AL_IRQHandler - def_irq_handler INTI2C1BF_IRQHandler - def_irq_handler INTI2C1NA_IRQHandler - def_irq_handler INTI2C2_IRQHandler - def_irq_handler INTI2C2AL_IRQHandler - def_irq_handler INTI2C2BF_IRQHandler - def_irq_handler INTI2C2NA_IRQHandler - def_irq_handler INTI2C3_IRQHandler - def_irq_handler INTI2C3AL_IRQHandler - def_irq_handler INTI2C3BF_IRQHandler - def_irq_handler INTI2C3NA_IRQHandler - def_irq_handler INTUART0RX_IRQHandler - def_irq_handler INTUART0TX_IRQHandler - def_irq_handler INTUART0ERR_IRQHandler - def_irq_handler INTUART1RX_IRQHandler - def_irq_handler INTUART1TX_IRQHandler - def_irq_handler INTUART1ERR_IRQHandler - def_irq_handler INTUART2RX_IRQHandler - def_irq_handler INTUART2TX_IRQHandler - def_irq_handler INTUART2ERR_IRQHandler - def_irq_handler INTUART3RX_IRQHandler - def_irq_handler INTUART3TX_IRQHandler - def_irq_handler INTUART3ERR_IRQHandler - def_irq_handler INTUART4RX_IRQHandler - def_irq_handler INTUART4TX_IRQHandler - def_irq_handler INTUART4ERR_IRQHandler - def_irq_handler INTUART5RX_IRQHandler - def_irq_handler INTUART5TX_IRQHandler - def_irq_handler INTUART5ERR_IRQHandler - def_irq_handler INTT32A00A_IRQHandler - def_irq_handler INTT32A00ACAP0_IRQHandler - def_irq_handler INTT32A00ACAP1_IRQHandler - def_irq_handler INTT32A00B_IRQHandler - def_irq_handler INTT32A00BCAP0_IRQHandler - def_irq_handler INTT32A00BCAP1_IRQHandler - def_irq_handler INTT32A00C_IRQHandler - def_irq_handler INTT32A00CCAP0_IRQHandler - def_irq_handler INTT32A00CCAP1_IRQHandler - def_irq_handler INTT32A01A_IRQHandler - def_irq_handler INTT32A01ACAP0_IRQHandler - def_irq_handler INTT32A01ACAP1_IRQHandler - def_irq_handler INTT32A01B_IRQHandler - def_irq_handler INTT32A01BCAP0_IRQHandler - def_irq_handler INTT32A01BCAP1_IRQHandler - def_irq_handler INTT32A01C_IRQHandler - def_irq_handler INTT32A01CCAP0_IRQHandler - def_irq_handler INTT32A01CCAP1_IRQHandler - def_irq_handler INTT32A02A_IRQHandler - def_irq_handler INTT32A02ACAP0_IRQHandler - def_irq_handler INTT32A02ACAP1_IRQHandler - def_irq_handler INTT32A02B_IRQHandler - def_irq_handler INTT32A02BCAP0_IRQHandler - def_irq_handler INTT32A02BCAP1_IRQHandler - def_irq_handler INTT32A02C_IRQHandler - def_irq_handler INTT32A02CCAP0_IRQHandler - def_irq_handler INTT32A02CCAP1_IRQHandler - def_irq_handler INTT32A03A_IRQHandler - def_irq_handler INTT32A03ACAP0_IRQHandler - def_irq_handler INTT32A03ACAP1_IRQHandler - def_irq_handler INTT32A03B_IRQHandler - def_irq_handler INTT32A03BCAP0_IRQHandler - def_irq_handler INTT32A03BCAP1_IRQHandler - def_irq_handler INTT32A03C_IRQHandler - def_irq_handler INTT32A03CCAP0_IRQHandler - def_irq_handler INTT32A03CCAP1_IRQHandler - def_irq_handler INTT32A04A_IRQHandler - def_irq_handler INTT32A04ACAP0_IRQHandler - def_irq_handler INTT32A04ACAP1_IRQHandler - def_irq_handler INTT32A04B_IRQHandler - def_irq_handler INTT32A04BCAP0_IRQHandler - def_irq_handler INTT32A04BCAP1_IRQHandler - def_irq_handler INTT32A04C_IRQHandler - def_irq_handler INTT32A04CCAP0_IRQHandler - def_irq_handler INTT32A04CCAP1_IRQHandler - def_irq_handler INTT32A05A_IRQHandler - def_irq_handler INTT32A05ACAP0_IRQHandler - def_irq_handler INTT32A05ACAP1_IRQHandler - def_irq_handler INTT32A05B_IRQHandler - def_irq_handler INTT32A05BCAP0_IRQHandler - def_irq_handler INTT32A05BCAP1_IRQHandler - def_irq_handler INTT32A05C_IRQHandler - def_irq_handler INTT32A05CCAP0_IRQHandler - def_irq_handler INTT32A05CCAP1_IRQHandler - def_irq_handler INTT32A06A_IRQHandler - def_irq_handler INTT32A06ACAP0_IRQHandler - def_irq_handler INTT32A06ACAP1_IRQHandler - def_irq_handler INTT32A06B_IRQHandler - def_irq_handler INTT32A06BCAP0_IRQHandler - def_irq_handler INTT32A06BCAP1_IRQHandler - def_irq_handler INTT32A06C_IRQHandler - def_irq_handler INTT32A06CCAP0_IRQHandler - def_irq_handler INTT32A06CCAP1_IRQHandler - def_irq_handler INTT32A07A_IRQHandler - def_irq_handler INTT32A07ACAP0_IRQHandler - def_irq_handler INTT32A07ACAP1_IRQHandler - def_irq_handler INTT32A07B_IRQHandler - def_irq_handler INTT32A07BCAP0_IRQHandler - def_irq_handler INTT32A07BCAP1_IRQHandler - def_irq_handler INTT32A07C_IRQHandler - def_irq_handler INTT32A07CCAP0_IRQHandler - def_irq_handler INTT32A07CCAP1_IRQHandler - def_irq_handler INTPARI_IRQHandler - def_irq_handler INTDMAATC_IRQHandler - def_irq_handler INTDMAAERR_IRQHandler - def_irq_handler INTDMABTC_IRQHandler - def_irq_handler INTDMABERR_IRQHandler - def_irq_handler INTRTC_IRQHandler - def_irq_handler INTRMC0_IRQHandler - def_irq_handler INTFLCRDY_IRQHandler - def_irq_handler INTFLDRDY_IRQHandler - - .end diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld deleted file mode 100644 index 7c9a2e765b3..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld +++ /dev/null @@ -1,166 +0,0 @@ -/* Linker script for Toshiba TMPM3HQ */ - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K - RAM (rwx) : ORIGIN = (0x20000000 + 0x2D8), LENGTH = (64K - 0x2D8) -} - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S deleted file mode 100644 index cbed3bdbe30..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S +++ /dev/null @@ -1,1107 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM3HQ.s -; * @brief CMSIS Cortex-M3 Core Device Startup File for the -; * TOSHIBA 'TMPM3HQ' Device Series -; * @version V1.0.0.0 -; * $Date:: 2017-12-08 #$ -; * -; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt Pin 00 - DCD INT01_IRQHandler ; 1: Interrupt Pin 01 - DCD INT02_IRQHandler ; 2: Interrupt Pin 02 - DCD INT03_IRQHandler ; 3: Interrupt Pin 03 - DCD INT04_IRQHandler ; 4: Interrupt Pin 04 - DCD INT05_IRQHandler ; 5: Interrupt Pin 05 - DCD INT06_IRQHandler ; 6: Interrupt Pin 06 - DCD INT07_IRQHandler ; 7: Interrupt Pin 07 - DCD INT08_IRQHandler ; 8: Interrupt Pin 08 - DCD INT09_IRQHandler ; 9: Interrupt Pin 09 - DCD INT10_IRQHandler ; 10: Interrupt Pin 10 - DCD INT11_IRQHandler ; 11: Interrupt Pin 11 - DCD INT12_IRQHandler ; 12: Interrupt Pin 12 - DCD INT13_IRQHandler ; 13: Interrupt Pin 13 - DCD INT14_IRQHandler ; 14: Interrupt Pin 14 - DCD INT15_IRQHandler ; 15: Interrupt Pin 15 - DCD INT16_IRQHandler ; 16: Interrupt Pin 16 - DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18 - DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22 - DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26 - DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28 - DCD INT29_IRQHandler ; 21: Interrupt Pin 29 - DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31 - DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt - DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt - DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0 - DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1 - DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A - DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B - DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished - DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4) - DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0) - DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt - DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt - DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt - DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt - DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt - DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5) - DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow - DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0 - DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1 - DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow - DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0 - DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1 - DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow - DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0 - DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1 - DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow - DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0 - DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1 - DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow - DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0 - DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1 - DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow - DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0 - DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1 - DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow - DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0 - DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1 - DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow - DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0 - DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1 - DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow - DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0 - DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1 - DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow - DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0 - DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1 - DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow - DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0 - DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1 - DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow - DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0 - DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1 - DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow - DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0 - DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1 - DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow - DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0 - DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1 - DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow - DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0 - DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1 - DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow - DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0 - DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1 - DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow - DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0 - DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1 - DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow - DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0 - DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1 - DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow - DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0 - DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1 - DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow - DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0 - DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1 - DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow - DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0 - DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1 - DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow - DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0 - DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1 - DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow - DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0 - DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1 - DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow - DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0 - DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1 - DCD INTPARI_IRQHandler ; 157: RAM parity interrupt - DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer - DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error - DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer - DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error - DCD INTRTC_IRQHandler ; 162: Real time clock interrupt - DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt - DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt - DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK INT00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT00_IRQHandler - B INT00_IRQHandler - - PUBWEAK INT01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT01_IRQHandler - B INT01_IRQHandler - - PUBWEAK INT02_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT02_IRQHandler - B INT02_IRQHandler - - PUBWEAK INT03_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT03_IRQHandler - B INT03_IRQHandler - - PUBWEAK INT04_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT04_IRQHandler - B INT04_IRQHandler - - PUBWEAK INT05_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT05_IRQHandler - B INT05_IRQHandler - - PUBWEAK INT06_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT06_IRQHandler - B INT06_IRQHandler - - PUBWEAK INT07_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT07_IRQHandler - B INT07_IRQHandler - - PUBWEAK INT08_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT08_IRQHandler - B INT08_IRQHandler - - PUBWEAK INT09_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT09_IRQHandler - B INT09_IRQHandler - - PUBWEAK INT10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT10_IRQHandler - B INT10_IRQHandler - - PUBWEAK INT11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT11_IRQHandler - B INT11_IRQHandler - - PUBWEAK INT12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT12_IRQHandler - B INT12_IRQHandler - - PUBWEAK INT13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT13_IRQHandler - B INT13_IRQHandler - - PUBWEAK INT14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT14_IRQHandler - B INT14_IRQHandler - - PUBWEAK INT15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT15_IRQHandler - B INT15_IRQHandler - - PUBWEAK INT16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT16_IRQHandler - B INT16_IRQHandler - - PUBWEAK INT17_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT17_18_IRQHandler - B INT17_18_IRQHandler - - PUBWEAK INT19_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT19_22_IRQHandler - B INT19_22_IRQHandler - - PUBWEAK INT23_26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT23_26_IRQHandler - B INT23_26_IRQHandler - - PUBWEAK INT27_28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT27_28_IRQHandler - B INT27_28_IRQHandler - - PUBWEAK INT29_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT29_IRQHandler - B INT29_IRQHandler - - PUBWEAK INT30_31_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT30_31_IRQHandler - B INT30_31_IRQHandler - - PUBWEAK INTEMG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTEMG0_IRQHandler - B INTEMG0_IRQHandler - - PUBWEAK INTOVV0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTOVV0_IRQHandler - B INTOVV0_IRQHandler - - PUBWEAK INTPMD0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPMD0_IRQHandler - B INTPMD0_IRQHandler - - PUBWEAK INTENC00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTENC00_IRQHandler - B INTENC00_IRQHandler - - PUBWEAK INTENC01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTENC01_IRQHandler - B INTENC01_IRQHandler - - PUBWEAK INTADAPDA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAPDA_IRQHandler - B INTADAPDA_IRQHandler - - PUBWEAK INTADAPDB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAPDB_IRQHandler - B INTADAPDB_IRQHandler - - PUBWEAK INTADACP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP0_IRQHandler - B INTADACP0_IRQHandler - - PUBWEAK INTADACP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP1_IRQHandler - B INTADACP1_IRQHandler - - PUBWEAK INTADATRG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADATRG_IRQHandler - B INTADATRG_IRQHandler - - PUBWEAK INTADASGL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADASGL_IRQHandler - B INTADASGL_IRQHandler - - PUBWEAK INTADACNT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACNT_IRQHandler - B INTADACNT_IRQHandler - - PUBWEAK INTT0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0RX_IRQHandler - B INTT0RX_IRQHandler - - PUBWEAK INTT0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0TX_IRQHandler - B INTT0TX_IRQHandler - - PUBWEAK INTT0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0ERR_IRQHandler - B INTT0ERR_IRQHandler - - PUBWEAK INTT1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1RX_IRQHandler - B INTT1RX_IRQHandler - - PUBWEAK INTT1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1TX_IRQHandler - B INTT1TX_IRQHandler - - PUBWEAK INTT1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1ERR_IRQHandler - B INTT1ERR_IRQHandler - - PUBWEAK INTT2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2RX_IRQHandler - B INTT2RX_IRQHandler - - PUBWEAK INTT2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2TX_IRQHandler - B INTT2TX_IRQHandler - - PUBWEAK INTT2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2ERR_IRQHandler - B INTT2ERR_IRQHandler - - PUBWEAK INTT3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3RX_IRQHandler - B INTT3RX_IRQHandler - - PUBWEAK INTT3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3TX_IRQHandler - B INTT3TX_IRQHandler - - PUBWEAK INTT3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3ERR_IRQHandler - B INTT3ERR_IRQHandler - - PUBWEAK INTT4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4RX_IRQHandler - B INTT4RX_IRQHandler - - PUBWEAK INTT4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4TX_IRQHandler - B INTT4TX_IRQHandler - - PUBWEAK INTT4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4ERR_IRQHandler - B INTT4ERR_IRQHandler - - PUBWEAK INTI2CWUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2CWUP_IRQHandler - B INTI2CWUP_IRQHandler - - PUBWEAK INTI2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0_IRQHandler - B INTI2C0_IRQHandler - - PUBWEAK INTI2C0AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0AL_IRQHandler - B INTI2C0AL_IRQHandler - - PUBWEAK INTI2C0BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0BF_IRQHandler - B INTI2C0BF_IRQHandler - - PUBWEAK INTI2C0NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0NA_IRQHandler - B INTI2C0NA_IRQHandler - - PUBWEAK INTI2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1_IRQHandler - B INTI2C1_IRQHandler - - PUBWEAK INTI2C1AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1AL_IRQHandler - B INTI2C1AL_IRQHandler - - PUBWEAK INTI2C1BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1BF_IRQHandler - B INTI2C1BF_IRQHandler - - PUBWEAK INTI2C1NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1NA_IRQHandler - B INTI2C1NA_IRQHandler - - PUBWEAK INTI2C2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2_IRQHandler - B INTI2C2_IRQHandler - - PUBWEAK INTI2C2AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2AL_IRQHandler - B INTI2C2AL_IRQHandler - - PUBWEAK INTI2C2BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2BF_IRQHandler - B INTI2C2BF_IRQHandler - - PUBWEAK INTI2C2NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2NA_IRQHandler - B INTI2C2NA_IRQHandler - - PUBWEAK INTI2C3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3_IRQHandler - B INTI2C3_IRQHandler - - PUBWEAK INTI2C3AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3AL_IRQHandler - B INTI2C3AL_IRQHandler - - PUBWEAK INTI2C3BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3BF_IRQHandler - B INTI2C3BF_IRQHandler - - PUBWEAK INTI2C3NA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3NA_IRQHandler - B INTI2C3NA_IRQHandler - - PUBWEAK INTUART0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0RX_IRQHandler - B INTUART0RX_IRQHandler - - PUBWEAK INTUART0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0TX_IRQHandler - B INTUART0TX_IRQHandler - - PUBWEAK INTUART0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0ERR_IRQHandler - B INTUART0ERR_IRQHandler - - PUBWEAK INTUART1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1RX_IRQHandler - B INTUART1RX_IRQHandler - - PUBWEAK INTUART1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1TX_IRQHandler - B INTUART1TX_IRQHandler - - PUBWEAK INTUART1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1ERR_IRQHandler - B INTUART1ERR_IRQHandler - - PUBWEAK INTUART2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2RX_IRQHandler - B INTUART2RX_IRQHandler - - PUBWEAK INTUART2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2TX_IRQHandler - B INTUART2TX_IRQHandler - - PUBWEAK INTUART2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2ERR_IRQHandler - B INTUART2ERR_IRQHandler - - PUBWEAK INTUART3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3RX_IRQHandler - B INTUART3RX_IRQHandler - - PUBWEAK INTUART3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3TX_IRQHandler - B INTUART3TX_IRQHandler - - PUBWEAK INTUART3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3ERR_IRQHandler - B INTUART3ERR_IRQHandler - - PUBWEAK INTUART4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4RX_IRQHandler - B INTUART4RX_IRQHandler - - PUBWEAK INTUART4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4TX_IRQHandler - B INTUART4TX_IRQHandler - - PUBWEAK INTUART4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4ERR_IRQHandler - B INTUART4ERR_IRQHandler - - PUBWEAK INTUART5RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5RX_IRQHandler - B INTUART5RX_IRQHandler - - PUBWEAK INTUART5TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5TX_IRQHandler - B INTUART5TX_IRQHandler - - PUBWEAK INTUART5ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5ERR_IRQHandler - B INTUART5ERR_IRQHandler - - PUBWEAK INTT32A00A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00A_IRQHandler - B INTT32A00A_IRQHandler - - PUBWEAK INTT32A00ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00ACAP0_IRQHandler - B INTT32A00ACAP0_IRQHandler - - PUBWEAK INTT32A00ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00ACAP1_IRQHandler - B INTT32A00ACAP1_IRQHandler - - PUBWEAK INTT32A00B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00B_IRQHandler - B INTT32A00B_IRQHandler - - PUBWEAK INTT32A00BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00BCAP0_IRQHandler - B INTT32A00BCAP0_IRQHandler - - PUBWEAK INTT32A00BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00BCAP1_IRQHandler - B INTT32A00BCAP1_IRQHandler - - PUBWEAK INTT32A00C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00C_IRQHandler - B INTT32A00C_IRQHandler - - PUBWEAK INTT32A00CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00CCAP0_IRQHandler - B INTT32A00CCAP0_IRQHandler - - PUBWEAK INTT32A00CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00CCAP1_IRQHandler - B INTT32A00CCAP1_IRQHandler - - PUBWEAK INTT32A01A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01A_IRQHandler - B INTT32A01A_IRQHandler - - PUBWEAK INTT32A01ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01ACAP0_IRQHandler - B INTT32A01ACAP0_IRQHandler - - PUBWEAK INTT32A01ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01ACAP1_IRQHandler - B INTT32A01ACAP1_IRQHandler - - PUBWEAK INTT32A01B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01B_IRQHandler - B INTT32A01B_IRQHandler - - PUBWEAK INTT32A01BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01BCAP0_IRQHandler - B INTT32A01BCAP0_IRQHandler - - PUBWEAK INTT32A01BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01BCAP1_IRQHandler - B INTT32A01BCAP1_IRQHandler - - PUBWEAK INTT32A01C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01C_IRQHandler - B INTT32A01C_IRQHandler - - PUBWEAK INTT32A01CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01CCAP0_IRQHandler - B INTT32A01CCAP0_IRQHandler - - PUBWEAK INTT32A01CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01CCAP1_IRQHandler - B INTT32A01CCAP1_IRQHandler - - PUBWEAK INTT32A02A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02A_IRQHandler - B INTT32A02A_IRQHandler - - PUBWEAK INTT32A02ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02ACAP0_IRQHandler - B INTT32A02ACAP0_IRQHandler - - PUBWEAK INTT32A02ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02ACAP1_IRQHandler - B INTT32A02ACAP1_IRQHandler - - PUBWEAK INTT32A02B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02B_IRQHandler - B INTT32A02B_IRQHandler - - PUBWEAK INTT32A02BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02BCAP0_IRQHandler - B INTT32A02BCAP0_IRQHandler - - PUBWEAK INTT32A02BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02BCAP1_IRQHandler - B INTT32A02BCAP1_IRQHandler - - PUBWEAK INTT32A02C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02C_IRQHandler - B INTT32A02C_IRQHandler - - PUBWEAK INTT32A02CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02CCAP0_IRQHandler - B INTT32A02CCAP0_IRQHandler - - PUBWEAK INTT32A02CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02CCAP1_IRQHandler - B INTT32A02CCAP1_IRQHandler - - PUBWEAK INTT32A03A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03A_IRQHandler - B INTT32A03A_IRQHandler - - PUBWEAK INTT32A03ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03ACAP0_IRQHandler - B INTT32A03ACAP0_IRQHandler - - PUBWEAK INTT32A03ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03ACAP1_IRQHandler - B INTT32A03ACAP1_IRQHandler - - PUBWEAK INTT32A03B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03B_IRQHandler - B INTT32A03B_IRQHandler - - PUBWEAK INTT32A03BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03BCAP0_IRQHandler - B INTT32A03BCAP0_IRQHandler - - PUBWEAK INTT32A03BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03BCAP1_IRQHandler - B INTT32A03BCAP1_IRQHandler - - PUBWEAK INTT32A03C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03C_IRQHandler - B INTT32A03C_IRQHandler - - PUBWEAK INTT32A03CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03CCAP0_IRQHandler - B INTT32A03CCAP0_IRQHandler - - PUBWEAK INTT32A03CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03CCAP1_IRQHandler - B INTT32A03CCAP1_IRQHandler - - PUBWEAK INTT32A04A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04A_IRQHandler - B INTT32A04A_IRQHandler - - PUBWEAK INTT32A04ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04ACAP0_IRQHandler - B INTT32A04ACAP0_IRQHandler - - PUBWEAK INTT32A04ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04ACAP1_IRQHandler - B INTT32A04ACAP1_IRQHandler - - PUBWEAK INTT32A04B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04B_IRQHandler - B INTT32A04B_IRQHandler - - PUBWEAK INTT32A04BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04BCAP0_IRQHandler - B INTT32A04BCAP0_IRQHandler - - PUBWEAK INTT32A04BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04BCAP1_IRQHandler - B INTT32A04BCAP1_IRQHandler - - PUBWEAK INTT32A04C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04C_IRQHandler - B INTT32A04C_IRQHandler - - PUBWEAK INTT32A04CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04CCAP0_IRQHandler - B INTT32A04CCAP0_IRQHandler - - PUBWEAK INTT32A04CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04CCAP1_IRQHandler - B INTT32A04CCAP1_IRQHandler - - PUBWEAK INTT32A05A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05A_IRQHandler - B INTT32A05A_IRQHandler - - PUBWEAK INTT32A05ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05ACAP0_IRQHandler - B INTT32A05ACAP0_IRQHandler - - PUBWEAK INTT32A05ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05ACAP1_IRQHandler - B INTT32A05ACAP1_IRQHandler - - PUBWEAK INTT32A05B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05B_IRQHandler - B INTT32A05B_IRQHandler - - PUBWEAK INTT32A05BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05BCAP0_IRQHandler - B INTT32A05BCAP0_IRQHandler - - PUBWEAK INTT32A05BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05BCAP1_IRQHandler - B INTT32A05BCAP1_IRQHandler - - PUBWEAK INTT32A05C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05C_IRQHandler - B INTT32A05C_IRQHandler - - PUBWEAK INTT32A05CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05CCAP0_IRQHandler - B INTT32A05CCAP0_IRQHandler - - PUBWEAK INTT32A05CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05CCAP1_IRQHandler - B INTT32A05CCAP1_IRQHandler - - PUBWEAK INTT32A06A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06A_IRQHandler - B INTT32A06A_IRQHandler - - PUBWEAK INTT32A06ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06ACAP0_IRQHandler - B INTT32A06ACAP0_IRQHandler - - PUBWEAK INTT32A06ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06ACAP1_IRQHandler - B INTT32A06ACAP1_IRQHandler - - PUBWEAK INTT32A06B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06B_IRQHandler - B INTT32A06B_IRQHandler - - PUBWEAK INTT32A06BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06BCAP0_IRQHandler - B INTT32A06BCAP0_IRQHandler - - PUBWEAK INTT32A06BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06BCAP1_IRQHandler - B INTT32A06BCAP1_IRQHandler - - PUBWEAK INTT32A06C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06C_IRQHandler - B INTT32A06C_IRQHandler - - PUBWEAK INTT32A06CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06CCAP0_IRQHandler - B INTT32A06CCAP0_IRQHandler - - PUBWEAK INTT32A06CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06CCAP1_IRQHandler - B INTT32A06CCAP1_IRQHandler - - PUBWEAK INTT32A07A_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07A_IRQHandler - B INTT32A07A_IRQHandler - - PUBWEAK INTT32A07ACAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07ACAP0_IRQHandler - B INTT32A07ACAP0_IRQHandler - - PUBWEAK INTT32A07ACAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07ACAP1_IRQHandler - B INTT32A07ACAP1_IRQHandler - - PUBWEAK INTT32A07B_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07B_IRQHandler - B INTT32A07B_IRQHandler - - PUBWEAK INTT32A07BCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07BCAP0_IRQHandler - B INTT32A07BCAP0_IRQHandler - - PUBWEAK INTT32A07BCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07BCAP1_IRQHandler - B INTT32A07BCAP1_IRQHandler - - PUBWEAK INTT32A07C_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07C_IRQHandler - B INTT32A07C_IRQHandler - - PUBWEAK INTT32A07CCAP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07CCAP0_IRQHandler - B INTT32A07CCAP0_IRQHandler - - PUBWEAK INTT32A07CCAP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07CCAP1_IRQHandler - B INTT32A07CCAP1_IRQHandler - - PUBWEAK INTPARI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPARI_IRQHandler - B INTPARI_IRQHandler - - PUBWEAK INTDMAATC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMAATC_IRQHandler - B INTDMAATC_IRQHandler - - PUBWEAK INTDMAAERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMAAERR_IRQHandler - B INTDMAAERR_IRQHandler - - PUBWEAK INTDMABTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMABTC_IRQHandler - B INTDMABTC_IRQHandler - - PUBWEAK INTDMABERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTDMABERR_IRQHandler - B INTDMABERR_IRQHandler - - PUBWEAK INTRTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRTC_IRQHandler - B INTRTC_IRQHandler - - PUBWEAK INTRMC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRMC0_IRQHandler - B INTRMC0_IRQHandler - - PUBWEAK INTFLCRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLCRDY_IRQHandler - B INTFLCRDY_IRQHandler - - PUBWEAK INTFLDRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLDRDY_IRQHandler - B INTFLDRDY_IRQHandler - - END diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf deleted file mode 100644 index 0d58c53864a..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf +++ /dev/null @@ -1,43 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x200002D8; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define symbol __BRAM_start__ = 0x20010000; -define symbol __BRAM_end__ = 0x200107FF; -define symbol __DFLASH_start__ = 0x30000000; -define symbol __DFLASH_end__ = 0x30007FFF; -define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ]; -define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in BRAM_region { section .backup_ram }; -place in DFLASH_region { section .data_flash }; diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h deleted file mode 100644 index 441eb0d0ef8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h +++ /dev/null @@ -1,12 +0,0 @@ -/* mbed Microcontroller Library - CMSIS for TMPM3HQ - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in TMPM3HQ specifics - */ -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "TMPM3HQ.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h deleted file mode 100644 index bb3ccde7a00..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for TMPM3HQ - * Copyright (c) 2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (182) -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c b/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c deleted file mode 100644 index 92a628a8563..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c +++ /dev/null @@ -1,342 +0,0 @@ -/** - ******************************************************************************* - * @file system_TMPM3Hy.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the - * TOSHIBA 'TMPM3Hy' Device Series - * @version 0.0.5.0 - * $Date:: 2017-07-01 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#include "TMPM3HQ.h" - -/*-------- <<< Start of configuration section >>> ----------------------------*/ - -/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ -#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ -#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ -#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ - -/* Clock Generator (CG) Configuration */ -#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ -#define SYSCR_Val (0x00000000UL) - -#define STBYCR_Val (0x00000000UL) - -#define CG_6M_MUL_13_328_FPLL (0x001C6535UL<<8U) /* fPLL = 6MHz * 13.328 */ -#define CG_8M_MUL_10_FPLL (0x00246028UL<<8U) /* fPLL = 8MHz * 10 */ -#define CG_10M_MUL_8_FPLL (0x002E6020UL<<8U) /* fPLL = 10MHz * 8 */ -#define CG_12M_MUL_6_656_FPLL (0x0036EA1AUL<<8U) /* fPLL = 12MHz * 6.656 */ -#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */ -#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */ -#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */ -#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */ - -#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) -#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) -#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD) - -#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE) -#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002) -#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) - -#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001) - -#if (CLOCK_SETUP) - #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100) - #define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL -#else - #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000) - #define PLL0SEL_Ready CG_10M_MUL_8_FPLL -#endif -#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) -#define PLL0SEL_MASK (0xFFFFFF00UL) - -/*-------- <<< End of configuration section >>> ------------------------------*/ - -/*-------- DEFINES -----------------------------------------------------------*/ -/* Define clocks */ -#define EOSC_6M (6000000UL) -#define EOSC_8M (8000000UL) -#define EOSC_10M (10000000UL) -#define EOSC_12M (12000000UL) -#define IOSC_10M (10000000UL) -#define EXTALH EOSC_12M /* External high-speed oscillator freq */ -#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ -#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */ -#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */ -#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ -#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */ -#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ -#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */ -#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */ -#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ -#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */ -#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ - -/* Configure Warm-up time */ -#define HZ_1M (1000000UL) -#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ -#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ -#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ -#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = warm-up time(us) * EXTALH / 16 */ -#if (CLOCK_SETUP) - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#else - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#endif -/* Determine core clock frequency according to settings */ -/* System clock is high-speed clock*/ -#if (CLOCK_SETUP) - #define CORE_TALH (EXTALH) -#else - #define CORE_TALH (IXTALH) -#endif - -#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ - #if (CORE_TALH == EOSC_6M) /* If input is 6MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_13_328_FPLL)) - #define __CORE_CLK EOSC_6M_DIV4_PLLON /* output clock is 79.97MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL)) - #define __CORE_CLK EOSC_6M_DIV8_PLLON /* output clock is 39.98MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 6MHz */ - #elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_10_FPLL)) - #define __CORE_CLK EOSC_8M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL)) - #define __CORE_CLK EOSC_8M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 8MHz */ - #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) - #define __CORE_CLK EOSC_10M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) - #define __CORE_CLK EOSC_10M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) - #define __CORE_CLK EOSC_12M_DIV4_PLLON /* output clock is 79.88MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) - #define __CORE_CLK EOSC_12M_DIV8_PLLON /* output clock is 39.94MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 12MHz */ - #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) - #define __CORE_CLK IOSC_10M_DIV4_PLLON /* output clock is 80MHz */ - #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) - #define __CORE_CLK IOSC_10M_DIV8_PLLON /* output clock is 40MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #else /* input clock not known */ - #define __CORE_CLK (0U) - #error "Core Oscillator Frequency invalid!" - #endif /* End switch input clock */ -#else - #define __CORE_CLK (CORE_TALH) -#endif - -#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */ - #define __CORE_SYS (__CORE_CLK) -#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */ - #define __CORE_SYS (__CORE_CLK / 2U) -#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */ - #define __CORE_SYS (__CORE_CLK / 4U ) -#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */ - #define __CORE_SYS (__CORE_CLK / 8U) -#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */ - #define __CORE_SYS (__CORE_CLK / 16U) -#else /* Gear -> reserved */ - #define __CORE_SYS (0U) -#endif - - -/* Clock Variable definitions */ -uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Update SystemCoreClock according register values. - */ -void SystemCoreClockUpdate(void) -{ /* Get Core Clock Frequency */ - uint32_t CoreClock = 0U; - uint32_t CoreClockInput = 0U; - uint32_t regval = 0U; - uint32_t oscsel = 0U; - uint32_t pll0sel = 0U; - uint32_t pll0on = 0U; - /* Determine clock frequency according to clock register values */ - /* System clock is high-speed clock */ - regval = TSB_CG->OSCCR; - oscsel = regval & CG_OSCCR_OSCSEL_SET; - if (oscsel) { /* If system clock is External high-speed oscillator freq */ - CoreClock = EXTALH; - } else { /* If system clock is Internal high-speed oscillator freq */ - CoreClock = IXTALH; - } - regval = TSB_CG->PLL0SEL; - pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; - pll0on = regval & CG_PLL0SEL_PLL0ON_SET; - if (pll0sel && pll0on) { /* If PLL enabled */ - if (CoreClock == EOSC_6M) { /* If input is 6MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_13_328_FPLL) { - CoreClockInput = EOSC_6M_DIV4_PLLON; /* output clock is 79.97MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) { - CoreClockInput = EOSC_6M_DIV8_PLLON; /* output clock is 39.98MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_8M) { /* If input is 8MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_10_FPLL) { - CoreClockInput = EOSC_8M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) { - CoreClockInput = EOSC_8M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) { - CoreClockInput = EOSC_10M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { - CoreClockInput = EOSC_10M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) { - CoreClockInput = EOSC_12M_DIV4_PLLON; /* output clock is 79.88MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) { - CoreClockInput = EOSC_12M_DIV8_PLLON; /* output clock is 39.94MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) { - CoreClockInput = IOSC_10M_DIV4_PLLON; /* output clock is 80MHz */ - } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { - CoreClockInput = IOSC_10M_DIV8_PLLON; /* output clock is 40MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else { - CoreClockInput = 0U; - } - } else { /* If PLL not used */ - CoreClockInput = CoreClock; - } - - switch (TSB_CG->SYSCR & 7U) { - case 0U: /* Gear -> fc */ - SystemCoreClock = CoreClockInput; - break; - case 1U: /* Gear -> fc/2 */ - SystemCoreClock = CoreClockInput / 2U; - break; - case 2U: /* Gear -> fc/4 */ - SystemCoreClock = CoreClockInput / 4U; - break; - case 3U: /* Gear -> fc/8 */ - if (CoreClockInput >= EOSC_8M) { - SystemCoreClock = CoreClockInput / 8U; - } else { - SystemCoreClock = 0U; - } - break; - case 4U: /* Gear -> fc/16 */ - if (CoreClockInput > EOSC_12M) { - SystemCoreClock = CoreClockInput / 16U; - } else { - SystemCoreClock = 0U; - } - break; - case 5U: - case 6U: - case 7U: - SystemCoreClock = 0U; - break; - default: - SystemCoreClock = 0U; - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ -#if (SIWD_SETUP) /* Watchdog Setup */ - /* SIWD Disable */ - TSB_SIWD0->EN = SIWDEN_Val; - TSB_SIWD0->CR = SIWDCR_Val; -#else - /* SIWD Enable (Setting after a Reset) */ -#endif - -#if (CLOCK_SETUP) /* Clock(external) Setup */ - TSB_CG->SYSCR = SYSCR_Val; - - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET); - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; - while (!TSB_CG_OSCCR_OSCF) { - ; - } /* Confirm CGOSCCR="1" */ - TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; -#else - /* Internal HOSC Enable (Setting after a Reset) */ -#endif - - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; - TSB_CG->PLL0SEL = PLL0SEL_Ready; - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ - TSB_CG->STBYCR = STBYCR_Val; - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - //Enable 32.768khz. - //TSB_RLM->LOSCCR = 0x01; - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Lockup */ - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; - while (!TSB_CG_PLL0SEL_PLL0ST) { - ; - } /*Confirm CGPLL0SEL = "1" */ -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h deleted file mode 100644 index 0dd2ddcdb54..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ***************************************************************************** - * @file system_TMPM3Hy.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM3Hy' Device Series - * @version V1.0.1.0 - * $Date:: 2017-07-01 #$ - * - * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ***************************************************************************** - */ - -#include - -#ifndef __SYSTEM_TMPM3HQ_H -#define __SYSTEM_TMPM3HQ_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c deleted file mode 100644 index a800f57e2ed..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c +++ /dev/null @@ -1,116 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_include.h" - -extern const PinMap PinMap_GPIO_IRQ[]; -#define GPIO_DATA PIN_DATA(0, 2) - -uint32_t gpio_set(PinName pin) -{ - // Check that pin is valid - MBED_ASSERT(pin != (PinName)NC); - // Checking pin name is not interrupt pins - // Set pin function as GPIO pin - pin_function(pin, GPIO_DATA); - // Return pin mask - return (1 << (pin & 0x07)); -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - // Store above pin mask, pin name into GPIO object - obj->pin = pin; - if (pin != NC) { - obj->mask = gpio_set(pin); - obj->port = (PortName) (pin >> 3); - TSB_CG->FSYSENA |= (1<<(obj->port)); - } -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -// Set gpio object pin direction -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - // Set direction - switch (direction) { - case PIN_INPUT: - pin_function(obj->pin, PIN_INPUT); - break; - - case PIN_OUTPUT: - pin_function(obj->pin, PIN_OUTPUT); - break; - - case PIN_INOUT: - pin_function(obj->pin, PIN_INOUT); - break; - - default: - error("Invalid direction\n"); - break; - } -} - -// Write gpio object pin data -void gpio_write(gpio_t *obj, int value) -{ - int port = 0; - uint8_t bit = 0; - uint32_t base; - - // Calculate port and pin position - port = PIN_PORT(obj->pin); - bit = PIN_POS(obj->pin); - - base = BITBAND_PORT_BASE(port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - if(value == GPIO_PIN_SET) - BITBAND_PORT_SET(base, bit); - else if(value == GPIO_PIN_RESET) - BITBAND_PORT_CLR(base, bit); - else - error("Invalid value\n"); -} - -// Read gpio object pin data -int gpio_read (gpio_t *obj) -{ - int port = 0; - uint8_t bit = 0; - uint32_t base; - uint32_t val; - int BitValue; - - // Calculate port and pin position - port = PIN_PORT(obj->pin); - bit = PIN_POS(obj->pin); - - base = BITBAND_PORT_BASE(port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - BITBAND_PORT_READ(val, base, bit); - if(val == GPIO_PIN_RESET) - BitValue = GPIO_PIN_RESET; - else - BitValue = GPIO_PIN_SET; - return (BitValue); -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h deleted file mode 100644 index 04b381798d4..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h +++ /dev/null @@ -1,355 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __GPIO_INCLUDE_H -#define __GPIO_INCLUDE_H - -#include -#include "TMPM3HQ.h" -#include "objects.h" -#include "serial_api.h" - -enum BitMode { - GPIO_PIN_RESET = 0, /* 0: Clear */ - GPIO_PIN_SET, /* 1: Set */ -}; - -enum PortFunction { - GPIO_Mode_DATA = 0x0, /* 0x0: PxDATA */ - GPIO_Mode_CR = 0x04, /* 0x4: PxCR */ - GPIO_Mode_FR1 = 0x08, /* 0x8: PxFR1 */ - GPIO_Mode_FR2 = 0x0C, /* 0xC: PxFR2 */ - GPIO_Mode_FR3 = 0x10, /* 0x10: PxFR3 */ - GPIO_Mode_FR4 = 0x14, /* 0x14: PxFR4 */ - GPIO_Mode_FR5 = 0x18, /* 0x18: PxFR5 */ - GPIO_Mode_FR6 = 0x1C, /* 0x1C: PxFR6 */ - GPIO_Mode_FR7 = 0x20, /* 0x20: PxFR7 */ - GPIO_Mode_OD = 0x28, /* 0x28: PxOD */ - GPIO_Mode_PUP = 0x2C, /* 0x2C: PxPUP */ - GPIO_Mode_PDN = 0x30, /* 0x30: PxPDN */ - GPIO_Mode_IE = 0x38 /* 0x38: PxIE */ -}; - -#define PORT_BASE (0x400C0000UL) /* Port Register Base Adress */ -#define BITBAND_PORT_OFFSET (0x0000100UL) /* Port Register Offset Value */ -#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) /* Operational target Port Adress */ -#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /* Operational target Control Register Adress */ -#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) /* Target Pin Bit set */ -#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) /* Target Pin Bit clear */ -#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) /* Target Pin Bit read */ - -/* PWM Macros */ -#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) -#define T32A_COUNT_DONT_START ((uint32_t)0x00000000) -#define T32A_RUN_DISABLE ((uint32_t)0x00000000) -#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) -#define T32A_OCR_DISABLE ((uint32_t)0x00000000) -#define T32A_MODE_16 ((uint32_t)0x00000000) /* 16bit Mode */ -#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /* prescaler */ -#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /* Enable */ -#define T32A_COUNT_UP ((uint32_t)0x00000000) /* count up */ -#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /* match up Timer Register */ -#define T32A_STOP_NON ((uint32_t)0x00000000) /* No use trigger */ -#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /* external trigger rising edge */ -#define T32A_OCR_SET ((uint32_t)0x00000001) /* Hi */ -#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /* Hi */ -#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /* Hi */ -#define T32A_IMx0_MASK_ALL ((uint32_t)0x0000000F) /* request */ -#define T32A_COUNT_DOWN ((uint32_t)0x00010000) -#define MAX_COUNTER_16B 0xFFFF -#define DEFAULT_CLOCK_DIVISION 32 -#define DEFAULT_PERIOD 0.02f - -/* RTC Configuration Macro */ -#define RTC_24_HOUR_MODE ((uint8_t)0x01) -#define PAGER_PAGE_ONE ((uint8_t)0x01) -#define PAGER_PAGE_ZERO ((uint8_t)0xEE) -#define RTC_CLK_ENABLE ((uint8_t)0x08) -#define RTC_CLK_DISABLE ((uint8_t)0xE7) -#define RTC_INT_ENABLE ((uint8_t)0x80) -#define RTC_CLEAR_ALL ((uint8_t)0x00) -#define RTC_RESET ((uint8_t)0xF7) -#define RTC_INT_SET ((uint8_t)0xFB) -#define RTC_INT_CLR ((uint8_t)0x04) -#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) -#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) -#define ELOSC_CFG_WARM_UP_TIME ((uint32_t)(5000)) /* Warm up time(us) */ -#define ELOSC_CFG_CLOCK ((uint32_t)(32768)) /* Clock(hz) */ -#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) /* WUPTL :High Bit Mask */ -#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) /* WULEF :Mask */ -#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) /* WULEF :[R] :Done */ -#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) /* WULON :[W] :Enable */ -#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) /* XTEN :[R/W] :Enable */ -#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro -#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro - -/* Serial Macros */ -#define UART0 TSB_UART0 -#define UART1 TSB_UART1 -#define UART2 TSB_UART2 -#define UART3 TSB_UART3 -#define UART4 TSB_UART4 -#define UART5 TSB_UART5 -#define UART_ENABLE_RX ((uint32_t)0x00000001) -#define UART_ENABLE_TX ((uint32_t)0x00000002) -#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /* SWRSTF :Mask */ -#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /* SWRSTF :During "Software Reset */ -#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /* SWRST :"10" */ -#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /* SWRST :"01" */ -#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /* TFCLR :Clear the transmit buff */ -#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /* RFCLR :Clear the receive buff */ -#define UART_PLESCALER_1 ((uint32_t)0x00000000) /* Boudrate Generator prescale 1/1 */ -#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /* Enable */ -#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /* Available */ -#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /* Available */ -#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) /* 1 stage */ -#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /* Minimum Value :K=0 */ -#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /* Maximum Value :K=63 */ -#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /* Minimum Value :N=1 */ -#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /* Maximum Value :N=65535 */ -typedef struct { - uint32_t ken; /* Enable/Disable Division Definition */ - uint32_t brk; /* Division Value K */ - uint32_t brn; /* Division Value N */ -} uart_boudrate_t; -/* Sleep Macros */ -#define CG_STBY_MODE_IDLE 0x00 -#define CG_STBY_MODE_STOP1 0x01 -#define EXTERNEL_OSC_MASK 0xFFFFFFF9 -#define IHOSC_CFG_WARM_UP_TIME ((uint32_t)(5000)) /* Warm up time(us) */ -#define IHOSC_CFG_CLOCK ((uint32_t)(10000000)) /* Clock(hz) */ -#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000) /* WUPT :High Bit Mask */ -#define CGWUPHCR_WUCLK_MASK ((uint32_t)0x00000100) /* WUCLK :Mask */ -#define CGWUPHCR_WUCLK_RW_IHOSC ((uint32_t)0x00000000) /* WUCLK :[R/W] :IHOSC */ - -/* SPI macros */ -typedef enum { - SPI_MASTER, - SPI_SLAVE -} spi_mode; -#define IS_SPI_MODULE(param) (((param) == SPI_0) || ((param) == SPI_1)) -#define TSPI_INT_ALL (uint32_t)0xF4 /* All above interrupt control */ -#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /* DR :Mask for 8bit */ -/* TSPI_SW_Reset SW Reset */ -#define TSPI_RESET10 ((uint32_t)0x00000010) /* RESET Pattarn 10 */ -#define TSPI_RESET01 ((uint32_t)0x00000001) /* RESET Pattarn 01 */ -/* TSPI_Enable TSPI Enable/Disable Control */ -#define TSPI_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_ENABLE ((uint32_t)0x00000001) /* Enable */ -/* TSPI_Triger_Control Triger Control */ -#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /* Enable */ -#define TSPI_SPI_MODE ((uint32_t)0x00000000) /* TSPI MODE */ -#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /* MASTER MODE */ -#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /* TWO WAY */ -#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /* Single Transfer Frame :0 */ -#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /* Low */ -#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /* Hi */ -#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /* 0 */ -#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /* 8 */ -#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ -/* TSPI_Baudrate_Clock */ -#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /* T16 */ -#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /* 1/3 */ -#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /* MSB first */ -#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /* 8 bit */ -#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /* 0 */ -#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ -#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ -#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ -#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ -#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /* 1st Edge Sampling */ -#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /* IDLE Term TSPII??SCK LOW */ -#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /* 1 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /* 1 x TSPIIxSCK */ -#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /* 1 x TSPIIxSCK */ -/* Format control1 Register */ -#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /* Odd Parity */ -#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /* Clear */ -#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /* Enable */ -#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /* TX_REACH_FILL_LEVEL_MASK */ -#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /* Send Data Complete Flag */ -#define TSPI_TX_DONE ((uint32_t)0x00400000) /* Send Data Complete */ -#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /* Disable MASK */ -#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /* Transfer Mode bit MASK */ -#define TSPI_RX_ONLY ((uint32_t)0x00000800) /* RECEIVE ONLY */ -#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /* Receive Data Complete Flag */ -#define TSPI_RX_DONE ((uint32_t)0x00000040) /* Send Data Complete */ -#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /* TX_REACH_FILL_LEVEL_MASK */ -#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /* Receive Data Complete Flag Clear */ -#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /* Clear */ - -/* Ticker Macros */ -#define T32A_MODE_32 ((uint32_t)0x00000001) -#define T32A_PRSCLx_32 ((uint32_t)0x30000000) -#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) -#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) -#define T32A_COUNT_STOP ((uint32_t)0x00000004) -#define T32A_COUNT_START ((uint32_t)0x00000002) -#define T32A_RUN_ENABLE ((uint32_t)0x00000001) - -/* I2C Macros */ - -#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080) -#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) -#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) -#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) -#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) -#define I2CxCR2_INIT ((uint32_t)0x00000008) -#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) -#define I2CxCR2_TRX ((uint32_t)0x00000040) -#define I2CxST_I2C ((uint32_t)0x00000001) -#define I2CxST_CLEAR ((uint32_t)0x0000000F) -#define I2CxCR1_ACK ((uint32_t)0x00000010) -#define I2CxSR_BB ((uint32_t)0x00000020) -#define I2CxSR_LRB ((uint32_t)0x00000001) -#define I2CxOP_RSTA ((uint32_t)0x00000008) -#define I2CxOP_SREN ((uint32_t)0x00000002) -#define I2CxOP_MFACK ((uint32_t)0x00000001) -#define I2CxOP_INIT ((uint32_t)0x00000084) -#define I2CxIE_CLEAR ((uint32_t)0x00000000) -#define I2CxPRS_PRCK ((uint32_t)0x0000000F) -#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) -// Slave Initial Settings. -#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) -#define I2CAR_SA_MASK ((uint32_t)0x000000FE) -#define I2CxSR_TRX ((uint32_t)0x00000040) -#define I2CxOP_SAST ((uint32_t)0x00000020) -#define I2CxIE_INTI2C ((uint32_t)0x00000001) -#define I2C_NO_DATA (0) -#define I2C_READ_ADDRESSED (1) -#define I2C_WRITE_GENERAL (2) -#define I2C_WRITE_ADDRESSED (3) -#define I2C_ACK (1) -#define I2C_TIMEOUT (100000) - -/* ADC macros */ -#define ADC_12BIT_RANGE 0xFFF -#define ADC_SCLK_1 ((uint32_t)0x00000000) /* SCLK : ADCLK/1 */ -#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /* RCUT : Normal */ -#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /* DACON : DAC on */ -#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /* ENINT :Disable */ -#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040) /* TRGS :Single */ -#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /* CNTDMEN :Disable */ -#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /* SGLDMEN :Disable */ -#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /* TRGDMEN :Disable */ -#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /* TRGEN :Disable */ -#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /* ADEN :Disable */ -#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /* ADEN :Enable */ -#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /* SGL :Enable */ -#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /* CNT :Disable */ -#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /* SNGF :Idle */ -#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /* SNGF :Running */ -#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /* ADRFn :Mask */ -#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /* ADRFn :Flag on */ -#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /* ADRn :Mask */ -#define ADC_SAMPLING_PERIOD_3V ((uint32_t)0x00000008) -#define ADC_MOD2_TMPM3Hx ((uint32_t)0x00000300) -#define ADC_MOD1_AVDD5_3V ((uint32_t)0x0000B001) - -/* RMC Include */ -#define RMC_LI_ENABLE ((uint32_t)0x80000000) /* Enable */ -#define RMC_EDI_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define RMC_LD_DISABLE ((uint32_t)0x00000000) /* Disable */ -#define RMC_PHM_DISABLE ((uint32_t)0x00000000) /* A remote control signal of the phase system isn't received */ -#define RMC_LL_MAX ((uint32_t)0x00000FF) /* Maximum Value(Disable Receiving End Interrupt) */ -#define RMC_THRESH_HIGH_MIN ((uint32_t)0x0000000) /* Minimum Value */ -#define RMC_POLARITY_POSITIVE ((uint32_t)0x0000000) /* Positive side */ -#define RMC_NOISE_REDUCTION_MIN ((uint32_t)0x0000000) /* Minimum Value */ -#define RMC_RX_DATA_BITS_MIN ((uint32_t)0x0000000) /* Minimum Value */ -#define RMC_CLK_LOW_SPEED ((uint32_t)0x00000000) /* Low speed clock(32.768kHz) */ -#define RMC_CYCLE_MAX_INT_OCCUR ((uint32_t)0x00002000) /* It occurs */ -#define RMC_LEADER_DETECT ((uint32_t)0x00000080) /* It detests */ -#define RMC_RX_BIT_NUM_MASK ((uint32_t)0x0000007F) /* Mask */ -#define RMCxEN_RMCEN_ENABLE ((uint32_t)0x00000001) /* RMCEN : Enable */ - -typedef struct { - uint32_t lcMax; /* Upper limit in a cycle period of leader detection */ - uint32_t lcMin; /* Lower limit in a cycle period of leader detection */ - uint32_t llMax; /* Upper limit in a low period of leader detection */ - uint32_t llMin; /* Lower limit in a low period of leader detection */ -} rmc_control1_t; - -typedef struct { - uint32_t lien; /* Enable a leader detection interrupt */ - uint32_t edien; /* Enable a remote control input falling edge interrupt */ - uint32_t cld; /* Enable a receive mode, that receives both remote control signals without leaders and with leaders */ - uint32_t phim; /* Setting of a remote control reception mode of the phase system */ - uint32_t ll; /* Setting at the timing of a "Receiving End Interrupt" by detection Low */ - uint32_t dmax; /* Setting at the timing of a "Receiving End Interrupt" by the cycle of the data bit */ -} rmc_control2_t; - -/* Receive Control Setting "3" */ -typedef struct { - uint32_t dath; /* Threshold value high setting of 3 price judgement of a Data bit */ - uint32_t datl; /* Threshold value low setting of 3 price judgement of a Data bit */ -} rmc_control3_t; - -/* Receive Control Setting "4" */ -typedef struct { - uint32_t po; /* Polarity choice of a remote control input signal */ - uint32_t nc; /* Setting of noise reduction time */ -} rmc_control4_t; - -/* Num of received end bit "1" */ -typedef struct { - uint32_t end1; /* Num of received data bits */ -} rmc_end1_t; - -/* Num of received end bit "2" */ -typedef struct { - uint32_t end2; /* Num of received data bits */ -} rmc_end2_t; - -/* Num of received end bit "3" */ -typedef struct { - uint32_t end3; /* Num of received data bits */ -} rmc_end3_t; - -/* Select source clock */ -typedef struct { - uint32_t clk; /* Select RMC sampling clock */ -} rmc_fssel_t; - -/* Initial setting structure definition */ -typedef struct { - rmc_control1_t cnt1; /* Receive Control Setting "1" */ - rmc_control2_t cnt2; /* Receive Control Setting "2" */ - rmc_control3_t cnt3; /* Receive Control Setting "3" */ - rmc_control4_t cnt4; /* Control4 setting */ - rmc_end1_t end1; /* Receive End Bit1 setting */ - rmc_end2_t end2; /* Receive End Bit2 setting */ - rmc_end3_t end3; /* Receive End Bit3 setting */ - rmc_fssel_t fssel; /* Select source clock */ -} rmc_initial_setting_t; - -/* RMC handle structure definition */ -typedef struct uart_handle { - TSB_RMC_TypeDef *p_instance; /* Registers base address */ - rmc_initial_setting_t init; /* Initial setting */ -} rmc_t; - -void rmc_init(rmc_t *p_obj); -void rmc_get_data(rmc_t *p_obj, uint32_t data[]); - - -#endif /* __GPIO_INCLUDE_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c deleted file mode 100644 index 890f0b16212..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c +++ /dev/null @@ -1,466 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_irq_api.h" -#include "mbed_error.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "gpio_include.h" -#include "mbed_critical.h" - -#define CHANNEL_NUM 32 - -const PinMap PinMap_GPIO_IRQ[] = { - {PC0, GPIO_IRQ_00, PIN_DATA(0, 0)}, - {PC1, GPIO_IRQ_01, PIN_DATA(0, 0)}, - {PC2, GPIO_IRQ_02, PIN_DATA(0, 0)}, - {PB1, GPIO_IRQ_03, PIN_DATA(0, 0)}, - {PJ4, GPIO_IRQ_04, PIN_DATA(0, 0)}, - {PK1, GPIO_IRQ_05, PIN_DATA(0, 0)}, - {PH3, GPIO_IRQ_06, PIN_DATA(0, 0)}, - {PA6, GPIO_IRQ_07, PIN_DATA(0, 0)}, - {PL3, GPIO_IRQ_08, PIN_DATA(0, 0)}, - {PM2, GPIO_IRQ_09, PIN_DATA(0, 0)}, - {PN3, GPIO_IRQ_10, PIN_DATA(0, 0)}, - {PA7, GPIO_IRQ_11, PIN_DATA(0, 0)}, - {PL4, GPIO_IRQ_12, PIN_DATA(0, 0)}, - {PK7, GPIO_IRQ_13, PIN_DATA(0, 0)}, - {PP3, GPIO_IRQ_14, PIN_DATA(0, 0)}, - {PM6, GPIO_IRQ_15, PIN_DATA(0, 0)}, - {PB7, GPIO_IRQ_16, PIN_DATA(0, 0)}, - {PV2, GPIO_IRQ_17_18, PIN_DATA(0, 0)}, - {PH4, GPIO_IRQ_19_22, PIN_DATA(0, 0)}, - {PT0, GPIO_IRQ_23_26, PIN_DATA(0, 0)}, - {PT1, GPIO_IRQ_23_26, PIN_DATA(0, 0)}, - {PG2, GPIO_IRQ_27_28, PIN_DATA(0, 0)}, - {PT7, GPIO_IRQ_29, PIN_DATA(0, 0)}, - {PU0, GPIO_IRQ_30_31, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; -static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState ); -cg_intactivestate CurrentState; -static void INT_IRQHandler(PinName pin, uint32_t index); -static uint32_t CheckPinNameIRQSRC(PinName pin); - -// Initialize gpio IRQ pin -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - uint8_t bit = 0; - uint32_t port_base = 0; - - // Get gpio interrupt ID - obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); - - // Disable interrupt by CPU - core_util_critical_section_enter(); - - // Calculate port and pin position - obj->port = (PortName)PIN_PORT(pin); - obj->pin = pin; - bit = PIN_POS(pin); - - port_base = BITBAND_PORT_BASE(obj->port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - BITBAND_PORT_CLR(port_base, bit); - // Enable gpio interrupt function - pinmap_pinout(pin, PinMap_GPIO_IRQ); - - // Get GPIO irq source - switch (obj->irq_id) { - case GPIO_IRQ_00: - obj->irq_src = CG_INT_SRC_01; - break; - case GPIO_IRQ_01: - obj->irq_src = CG_INT_SRC_02; - break; - case GPIO_IRQ_02: - obj->irq_src = CG_INT_SRC_03; - break; - case GPIO_IRQ_03: - obj->irq_src = CG_INT_SRC_04; - break; - case GPIO_IRQ_04: - obj->irq_src = CG_INT_SRC_05; - break; - case GPIO_IRQ_05: - obj->irq_src = CG_INT_SRC_06; - break; - case GPIO_IRQ_06: - obj->irq_src = CG_INT_SRC_07; - break; - case GPIO_IRQ_07: - obj->irq_src = CG_INT_SRC_08; - break; - case GPIO_IRQ_08: - obj->irq_src = CG_INT_SRC_09; - break; - case GPIO_IRQ_09: - obj->irq_src = CG_INT_SRC_0A; - break; - case GPIO_IRQ_10: - obj->irq_src = CG_INT_SRC_0B; - break; - case GPIO_IRQ_11: - obj->irq_src = CG_INT_SRC_0C; - break; - case GPIO_IRQ_12: - obj->irq_src = CG_INT_SRC_0D; - break; - case GPIO_IRQ_13: - obj->irq_src = CG_INT_SRC_0E; - break; - case GPIO_IRQ_14: - obj->irq_src = CG_INT_SRC_0F; - break; - case GPIO_IRQ_15: - obj->irq_src = CG_INT_SRC_10; - break; - case GPIO_IRQ_16: - obj->irq_src = CG_INT_SRC_11; - break; - case GPIO_IRQ_17_18: - obj->irq_src = CG_INT_SRC_12; - break; - case GPIO_IRQ_19_22: - obj->irq_src = CG_INT_SRC_14; - break; - case GPIO_IRQ_23_26: - obj->irq_src = CheckPinNameIRQSRC(pin); - break; - case GPIO_IRQ_27_28: - obj->irq_src = CG_INT_SRC_1C; - break; - case GPIO_IRQ_29: - obj->irq_src = CG_INT_SRC_1E; - break; - case GPIO_IRQ_30_31: - obj->irq_src = CG_INT_SRC_1F; - break; - default: - break; - } - - // Save irq handler - hal_irq_handler[obj->irq_src] = handler; - - // Save irq id - channel_ids[obj->irq_src] = id; - - // Initialize interrupt event as both edges detection - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - CurrentState = CG_INT_ACTIVE_STATE_BOTH_EDGES; - // Set interrupt event and enable INTx clear - SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE); - - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id); - - core_util_critical_section_exit(); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - // Clear gpio_irq - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Reset interrupt handler - hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; -} - -// Set interrupt event of gpio_irq object -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint8_t bit = 0; - uint32_t port_base = 0; - - //Disable GPIO interrupt on obj - gpio_irq_disable(obj); - if (enable) { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_RISING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_FALLING; - } - } else { - error("Not supported event\n"); - } - } else { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { - obj->event = CG_INT_ACTIVE_STATE_INVALID; - } else { - obj->event = CG_INT_ACTIVE_STATE_FALLING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { - obj->event = CG_INT_ACTIVE_STATE_INVALID; - } else { - obj->event = CG_INT_ACTIVE_STATE_RISING; - } - } else { - error("Not supported event\n"); - } - } - CurrentState = obj->event; - // Calculate port and pin position - bit = PIN_POS(obj->pin); - - port_base = BITBAND_PORT_BASE(obj->port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - - if(obj->event != CG_INT_ACTIVE_STATE_INVALID ) { - // Set interrupt event and enable INTx clear - SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE); - BITBAND_PORT_CLR(port_base, bit); - } else { - BITBAND_PORT_SET(port_base, bit); - } - //Enable GPIO interrupt on obj - gpio_irq_enable(obj); -} - -// Enable gpio_irq object -void gpio_irq_enable(gpio_irq_t *obj) -{ - // Clear and Enable gpio_irq object - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - NVIC_EnableIRQ((IRQn_Type)obj->irq_id); -} - -// Disable gpio_irq object -void gpio_irq_disable(gpio_irq_t *obj) -{ - // Disable gpio_irq object - NVIC_DisableIRQ((IRQn_Type)obj->irq_id); -} - -static void INT_IRQHandler(PinName pin, uint32_t index) -{ - int port = 0; - uint8_t bit = 0; - uint32_t data = 0; - uint32_t port_base = 0; - - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - - // Clear interrupt request - SetSTBYReleaseINTSrc((cg_intsrc)(CG_INT_SRC_01 + index), CurrentState, DISABLE); - - port_base = BITBAND_PORT_BASE(port); - port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); - BITBAND_PORT_READ(data, port_base, bit); - - switch (data) { - // Falling edge detection - case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); - break; - // Rising edge detection - case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); - break; - default: - break; - } - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_01 + index)); - - // Enable interrupt request - SetSTBYReleaseINTSrc((cg_intsrc)(CG_INT_SRC_01 + index), CurrentState, ENABLE); -} - -void INT00_IRQHandler(void) -{ - INT_IRQHandler(PC0, 0); -} - -void INT01_IRQHandler(void) -{ - INT_IRQHandler(PC1, 1); -} - -void INT02_IRQHandler(void) -{ - INT_IRQHandler(PC2, 2); -} - -void INT03_IRQHandler(void) -{ - INT_IRQHandler(PB1, 3); -} - -void INT04_IRQHandler(void) -{ - INT_IRQHandler(PJ4, 4); -} - -void INT05_IRQHandler(void) -{ - INT_IRQHandler(PK1, 5); -} - -void INT06_IRQHandler(void) -{ - INT_IRQHandler(PH3, 6); -} - -void INT07_IRQHandler(void) -{ - INT_IRQHandler(PA6, 7); -} - -void INT08_IRQHandler(void) -{ - INT_IRQHandler(PL3, 8); -} - -void INT09_IRQHandler(void) -{ - INT_IRQHandler(PM2, 9); -} - -void INT10_IRQHandler(void) -{ - INT_IRQHandler(PN3, 10); -} - -void INT11_IRQHandler(void) -{ - INT_IRQHandler(PA7, 11); -} - -void INT12_IRQHandler(void) -{ - INT_IRQHandler(PL4, 12); -} - -void INT13_IRQHandler(void) -{ - INT_IRQHandler(PK7, 13); -} - -void INT14_IRQHandler(void) -{ - INT_IRQHandler(PP3, 14); -} - -void INT15_IRQHandler(void) -{ - INT_IRQHandler(PM6, 15); -} - -void INT16_IRQHandler(void) -{ - INT_IRQHandler(PB7, 16); -} - -void INT17_18_IRQHandler(void) -{ - INT_IRQHandler(PV2, 17); -} - -void INT19_22_IRQHandler(void) -{ - INT_IRQHandler(PH4, 19); -} - -#define BIT22 (0x1 << 22) -#define BIT21 (0x1 << 21) -void INT23_26_IRQHandler(void) -{ - uint32_t int_num = TSB_IMN->FLG5; - if( int_num & BIT22) { - INT_IRQHandler(PT1, 24); - } else if(int_num & BIT21) { - INT_IRQHandler(PT0, 23); - } -} - -void INT27_28_IRQHandler(void) -{ - INT_IRQHandler(PG2, 27); -} - -void INT29_IRQHandler(void) -{ - INT_IRQHandler(PT7, 29); -} - -void INT30_31_IRQHandler(void) -{ - INT_IRQHandler(PU0, 30); -} - -static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState) -{ - __IO uint8_t *p_imc; - - if(intsource < 3U || intsource == 13U) { - if(intsource == 13U) { - intsource = (cg_intsrc)3U; - } - p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource)); - *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); - } else { - if(intsource > 13U) { - intsource -= 4; - } else { - intsource -= 3; - } - p_imc = (__IO uint8_t *)(&TSB_IB->IMC066 + (intsource)); - *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); - } - // Dummy read is need - { - __IO uint8_t imc = *p_imc; - } -} - -/** - * @brief Return INTSRC for gpio INT that enable more than one pin. - * @param pin PinName. - * @return GPIO IRQn_Type . - * @note You can expand func CheckPinNameIRQSRC if need to add other GPIO INT. - */ -static uint32_t CheckPinNameIRQSRC(PinName pin) -{ - switch(pin) - { - case PT0: - return CG_INT_SRC_18; - case PT1: - return CG_INT_SRC_19; - default: - break; - } - return -1; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h deleted file mode 100644 index 3569f438046..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h +++ /dev/null @@ -1,98 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define GPIO_BIT_VALUE_1 ((uint8_t)0x01) -#define GPIO_BIT_VALUE_0 ((uint8_t)0x00) -#define GPIO_BIT_ALL ((uint8_t)0xFF) - -typedef enum { - CG_INT_SRC_01 = 0U, - CG_INT_SRC_02, - CG_INT_SRC_03, - CG_INT_SRC_04, - CG_INT_SRC_05, - CG_INT_SRC_06, - CG_INT_SRC_07, - CG_INT_SRC_08, - CG_INT_SRC_09, - CG_INT_SRC_0A, - CG_INT_SRC_0B, - CG_INT_SRC_0C, - CG_INT_SRC_0D, - CG_INT_SRC_0E, - CG_INT_SRC_0F, - CG_INT_SRC_10, - CG_INT_SRC_11, - CG_INT_SRC_12, - CG_INT_SRC_13, - CG_INT_SRC_14, - CG_INT_SRC_15, - CG_INT_SRC_16, - CG_INT_SRC_17, - CG_INT_SRC_18, - CG_INT_SRC_19, - CG_INT_SRC_1A, - CG_INT_SRC_1B, - CG_INT_SRC_1C, - CG_INT_SRC_1D, - CG_INT_SRC_1E, - CG_INT_SRC_1F, - CG_INT_SRC_20 -} cg_intsrc; - -typedef enum { - CG_INT_ACTIVE_STATE_L = 0x00U, - CG_INT_ACTIVE_STATE_H = 0x02U, - CG_INT_ACTIVE_STATE_FALLING = 0x04U, - CG_INT_ACTIVE_STATE_RISING = 0x06U, - CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, - CG_INT_ACTIVE_STATE_INVALID = 0x0AU -} cg_intactivestate; - -typedef struct { - PinName pin; - uint32_t mask; - PortName port; -} gpio_t; - -struct gpio_irq_s { - uint32_t mask; - PortName port; - PinName pin; - uint32_t irq_id; - cg_intactivestate event; - cg_intsrc irq_src; -}; - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c deleted file mode 100644 index d4f80b1c079..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c +++ /dev/null @@ -1,400 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "mbed_error.h" -#include "pinmap.h" -#include "gpio_include.h" - -#if DEVICE_I2C_ASYNCH -#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) -#else -#define I2C_S(obj) (struct i2c_s *) (obj) -#endif - -static const PinMap PinMap_I2C_SDA[] = { - {PC1, I2C_0, PIN_DATA(1, 2)}, - {PA5, I2C_1, PIN_DATA(1, 2)}, - {PL1, I2C_2, PIN_DATA(3, 2)}, - {PT0, I2C_3, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PC0, I2C_0, PIN_DATA(1, 2)}, - {PA4, I2C_1, PIN_DATA(1, 2)}, - {PL0, I2C_2, PIN_DATA(3, 2)}, - {PT1, I2C_3, PIN_DATA(1, 2)}, - {NC, NC, 0} -}; - -// Clock setting structure definition -typedef struct { - uint32_t sck; - uint32_t prsck; -} I2C_clock_setting_t; - -static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { - 20, 24, 32, 48, 80, 144, 272, 528 -}; // SCK Divider value table - -I2C_clock_setting_t clk; -static uint32_t start_flag = 0; - -static int32_t wait_status(i2c_t *p_obj); -static void i2c_start_bit(i2c_t *obj); - -// Initialize the I2C peripheral. It sets the default parameters for I2C -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - struct i2c_s *obj_s = I2C_S(obj); - MBED_ASSERT(obj_s != NULL); - - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)i2c_name != NC); - - switch (i2c_name) { - case I2C_0: - TSB_CG_FSYSENB_IPENB11 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - obj_s->i2c = TSB_I2C0; - break; - case I2C_1: - TSB_CG_FSYSENB_IPENB12 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - obj_s->i2c = TSB_I2C1; - break; - case I2C_2: - TSB_CG_FSYSENB_IPENB13 = ENABLE; - TSB_CG_FSYSENA_IPENA10 = ENABLE; - obj_s->i2c = TSB_I2C2; - case I2C_3: - TSB_CG_FSYSENB_IPENB14 = ENABLE; - TSB_CG_FSYSENA_IPENA15 = ENABLE; - obj_s->i2c = TSB_I2C3; - break; - default: - error("I2C is not available"); - break; - } - - pinmap_pinout(sda, PinMap_I2C_SDA); - pin_mode(sda, OpenDrain); - pin_mode(sda, PullUp); - - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); - pin_mode(scl, PullUp); - - i2c_reset(obj); - i2c_frequency(obj, 100000); - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | - I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->IE = I2CxIE_CLEAR; -} - -// Configure the I2C frequency -void i2c_frequency(i2c_t *obj, int hz) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint64_t sck, tmp_sck; - uint64_t prsck, tmp_prsck; - uint64_t fscl, tmp_fscl; - uint64_t fx; - - SystemCoreClockUpdate(); - - if (hz <= 1000000) { - sck = tmp_sck = 0; - prsck = tmp_prsck = 1; - fscl = tmp_fscl = 0; - for (prsck = 1; prsck <= 32; prsck++) { - fx = ((uint64_t)SystemCoreClock / prsck); - if ((fx < 20000000U) && (fx > 6666666U)) { - for (sck = 0; sck <= 7; sck++) { - fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - tmp_sck = sck; - tmp_prsck = (prsck < 32) ? prsck : 0; - } - } - } - } - clk.sck = (uint32_t)tmp_sck; - clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0; - } - - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); -} - -int i2c_start(i2c_t *obj) -{ - start_flag = 1; // Start Condition - return 0; -} - -int i2c_stop(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t timeout = I2C_TIMEOUT; - - obj_s->i2c->CR2 = I2CxCR2_STOP_CONDITION; - while ((obj_s->i2c->SR & I2CxSR_BB) == I2CxSR_BB) { - if (timeout == 0) - break; - timeout--; - } - return 0; -} - -void i2c_reset(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->i2c->CR2 = I2CxCR2_SWRES_10; - obj_s->i2c->CR2 = I2CxCR2_SWRES_01; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - int32_t pdata = 0; - - if (length > 0) { - start_flag = 1; // Start Condition - if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { - while (count < length) { - pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - } - return (result); -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int32_t result = 0; - int32_t count = 0; - - start_flag = 1; // Start Condition - if (i2c_byte_write(obj, address) == I2C_ACK) { - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - result = count; - } else { - stop = 1; - result = I2C_ERROR_NO_SLAVE; - } - - if (stop) { // Stop Condition - i2c_stop(obj); - } - return (result); -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result; - - obj_s->i2c->ST = I2CxST_CLEAR; - if (last) { - obj_s->i2c->OP |= I2CxOP_MFACK; - } else { - obj_s->i2c->OP &= ~I2CxOP_MFACK; - } - obj_s->i2c->DBR = (0 & I2CxDBR_DB_MASK); - if (wait_status(obj) < 0) { - result = -1; - } else { - result = (int32_t)(obj_s->i2c->DBR & I2CxDBR_DB_MASK); - } - return (result); -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result; - - obj_s->i2c->ST = I2CxST_CLEAR; - if (start_flag == 1) { - obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK); - i2c_start_bit(obj); - start_flag = 0; - } else { - obj_s->i2c->DBR = (data & I2CxDBR_DB_MASK); - } - - if (wait_status(obj) < 0) { - return (-1); - } - - if (!((obj_s->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { - result = 1; - } else { - result = 0; - } - return (result); -} - -static void i2c_start_bit(i2c_t *obj) // Send START command -{ - struct i2c_s *obj_s = I2C_S(obj); - uint32_t opreg; - opreg = obj_s->i2c->OP; - opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); - if ((obj_s->i2c->SR & I2CxSR_BB)) { - opreg |= I2CxOP_SREN; - } - obj_s->i2c->OP = opreg; - obj_s->i2c->CR2 |= I2CxCR2_START_CONDITION; -} - -static int32_t wait_status(i2c_t *p_obj) -{ - struct i2c_s *p_obj_s = I2C_S(p_obj); - volatile int32_t timeout; - timeout = I2C_TIMEOUT; - while (!((p_obj_s->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) { - if ((timeout--) == 0) { - return (-1); - } - } - return (0); -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - struct i2c_s *obj_s = I2C_S(obj); - if (enable_slave) { - obj_s->i2c->OP = I2CxOP_SLAVE_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - obj_s->i2c->AR = (obj_s->address & I2CAR_SA_MASK); - obj_s->i2c->IE = I2CxIE_INTI2C; - } else { - i2c_reset(obj); - obj_s->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | - I2CxCR2_INIT); - obj_s->i2c->OP = I2CxOP_INIT; - obj_s->i2c->CR1 = (I2CxCR1_ACK | clk.sck); - obj_s->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); - NVIC_DisableIRQ(obj_s->IRQn); - NVIC_ClearPendingIRQ(obj_s->IRQn); - obj_s->i2c->ST = I2CxST_CLEAR; - } -} - -int i2c_slave_receive(i2c_t *obj) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t result = I2C_NO_DATA; - - if ((obj_s->i2c->ST & I2CxST_I2C) && (obj_s->i2c->OP & I2CxOP_SAST)) { - if ((obj_s->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) { - result = I2C_READ_ADDRESSED; - } else { - result = I2C_WRITE_ADDRESSED; - } - } - return (result); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - struct i2c_s *obj_s = I2C_S(obj); - int32_t count = 0; - - while (count < length) { - int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); - if ((obj_s->i2c->SR & I2CxSR_TRX)) { - return (count); - } else { - if (pdata < 0) { - break; - } - data[count++] = (uint8_t)pdata; - } - } - i2c_slave_mode(obj,1); - return (count); -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - int32_t count = 0; - - while (count < length) { - if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { - break; - } - } - i2c_slave_mode(obj,1); - return (count); -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - struct i2c_s *obj_s = I2C_S(obj); - obj_s->address = address & I2CAR_SA_MASK; - i2c_slave_mode(obj,1); -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h b/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h deleted file mode 100644 index 7a27af03e9f..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h +++ /dev/null @@ -1,113 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "TMPM3HQ.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t BaudRate; - uint32_t DataBits; - uint32_t StopBits; - uint32_t Parity; - uint32_t Mode; - uint32_t FlowCtrl; -} uart_inittypedef_t; - -struct port_s { - PortName port; - uint32_t mask; -}; - -typedef struct { - uint8_t PinDATA; - uint8_t PinCR; - uint8_t PinFR[FRMAX]; - uint8_t PinOD; - uint8_t PinPUP; - uint8_t PinPDN; - uint8_t PinIE; -} gpio_regtypedef_t; - -typedef struct { - __IO uint32_t DATA; - __IO uint32_t CR; - __IO uint32_t FR[FRMAX]; - uint32_t RESERVED0[1]; - __IO uint32_t OD; - __IO uint32_t PUP; - __IO uint32_t PDN; - uint32_t RESERVED1; - __IO uint32_t IE; -} TSB_Port_TypeDef; - -struct serial_s { - PinName pin; - uint32_t index; - TSB_UART_TypeDef * UARTx; - uart_inittypedef_t uart_config; -}; - -struct analogin_s { - PinName pin; - ADCName adc; - TSB_AD_TypeDef* obj; -}; - -struct dac_s { - DACName dac; - TSB_DA_TypeDef* handler; -}; - -struct pwmout_s { - PinName pin; - TSB_T32A_TypeDef * channel; - uint16_t trailing_timing; - uint16_t leading_timing; - uint16_t divisor; - float period; -}; - -struct i2c_s { - uint32_t address; - IRQn_Type IRQn; - TSB_I2C_TypeDef *i2c; -}; - -struct spi_s { - TSB_TSPI_TypeDef *spi; - SPIName module; - uint8_t bits; -}; - -extern const gpio_regtypedef_t GPIO_SFRs[]; -extern const uint32_t GPIO_Base[]; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c b/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c deleted file mode 100644 index 8566cd6dd7b..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c +++ /dev/null @@ -1,215 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "gpio_include.h" - -void pin_function(PinName pin, int function) -{ - int port = 0; - uint8_t bit = 0; - uint8_t func = 0; - uint8_t dir = 0; - uint32_t port_base = 0; - uint32_t mode_base = 0; - - /* Assert that pin is valid*/ - MBED_ASSERT(pin != NC); - - /* Calculate pin function and pin direction*/ - func = PIN_FUNC(function); - dir = PIN_DIR(function); - - /* Calculate port and pin position*/ - port = PIN_PORT(pin); - bit = PIN_POS(pin); - - port_base = BITBAND_PORT_BASE(port); - /* Initialization PxFR OFF */ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - BITBAND_PORT_CLR(mode_base, bit); - - /* Initialize Input */ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, bit); - switch (func) { - case 0: - break; - case 1: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - break; - case 2: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - break; - case 3: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - break; - case 4: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - break; - case 5: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - break; - case 6: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - break; - case 7: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - break; - default: - break; - } - if (func != 0) - BITBAND_PORT_SET(mode_base, bit); - if(dir == PIN_OUTPUT) { - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, bit); - } else if(dir == PIN_INOUT) { - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, bit); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, bit); - } -} - -void pin_mode(PinName pin, PinMode mode) -{ - int port = 0; - uint8_t bit = 0; - uint8_t val = 0; - - /* Assert that pin is valid*/ - MBED_ASSERT(pin != NC); - - /* Check if function is in range*/ - if (mode > OpenDrain) { - return; - } - - /* Calculate port and pin position*/ - port = PIN_PORT(pin); - bit = PIN_POS(pin); - val = (1 << bit); - - switch (port) { - case PortA: - if(mode == OpenDrain) TSB_PA->OD |= val; - else if(mode == PullUp) TSB_PA->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PA->PDN |= val; - break; - case PortB: - if(mode == OpenDrain) TSB_PB->OD |= val; - else if(mode == PullUp) TSB_PB->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PB->PDN |= val; - break; - case PortC: - if(mode == OpenDrain) TSB_PC->OD |= val; - else if(mode == PullUp) TSB_PC->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PC->PDN |= val; - break; - case PortD: - if(mode == OpenDrain) TSB_PD->OD |= val; - else if(mode == PullUp) TSB_PD->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PD->PDN |= val; - break; - case PortE: - if(mode == OpenDrain) TSB_PE->OD |= val; - else if(mode == PullUp) TSB_PE->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PE->PDN |= val; - break; - case PortF: - if(mode == OpenDrain) TSB_PF->OD |= val; - else if(mode == PullUp) TSB_PF->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PF->PDN |= val; - break; - case PortG: - if(mode == OpenDrain) TSB_PG->OD |= val; - else if(mode == PullUp) TSB_PG->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PG->PDN |= val; - break; - case PortH: - if(mode == PullDown) TSB_PH->PDN |= val; - break; - case PortJ: - if(mode == OpenDrain) TSB_PJ->OD |= val; - else if(mode == PullUp) TSB_PJ->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PJ->PDN |= val; - break; - case PortK: - if(mode == OpenDrain) TSB_PK->OD |= val; - else if(mode == PullUp) TSB_PK->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PK->PDN |= val; - break; - case PortL: - if(mode == OpenDrain) TSB_PL->OD |= val; - else if(mode == PullUp) TSB_PL->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PL->PDN |= val; - break; - case PortM: - if(mode == OpenDrain) TSB_PM->OD |= val; - else if(mode == PullUp) TSB_PM->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PM->PDN |= val; - break; - case PortN: - if(mode == OpenDrain) TSB_PN->OD |= val; - else if(mode == PullUp) TSB_PN->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PN->PDN |= val; - break; - case PortP: - if(mode == OpenDrain) TSB_PP->OD |= val; - else if(mode == PullUp) TSB_PP->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PP->PDN |= val; - break; - case PortR: - if(mode == OpenDrain) TSB_PR->OD |= val; - else if(mode == PullUp) TSB_PR->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PR->PDN |= val; - break; - case PortT: - if(mode == OpenDrain) TSB_PT->OD |= val; - else if(mode == PullUp) TSB_PT->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PT->PDN |= val; - break; - case PortU: - if(mode == OpenDrain) TSB_PU->OD |= val; - else if(mode == PullUp) TSB_PU->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PU->PDN |= val; - break; - case PortV: - if(mode == OpenDrain) TSB_PV->OD |= val; - else if(mode == PullUp) TSB_PV->PUP |= val; - else if(mode == PullDown || mode == PullDefault) TSB_PV->PDN |= val; - break; - default: - break; - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c deleted file mode 100644 index 3ff6359bee2..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c +++ /dev/null @@ -1,150 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_include.h" - -#define PORT_PIN_NUM 8 - -PinName port_pin(PortName port, int pin_n) -{ - PinName pin = NC; - pin = (PinName) ((port << 3 ) | pin_n); - return pin; -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(port <= PortV); - - // Store port and port mask for future use - obj->port = port; - obj->mask = mask; - // Enabling Port Clock Supply - TSB_CG->FSYSENA |= (1<<(obj->port)); - // Set port function and port direction - for (i = 0; i < PORT_PIN_NUM; i++) { - if (obj->mask & (1 << i)) { // If the pin is used - pin_function(port_pin(obj->port, i), dir); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - - // Set mode for masked pins - for (i = 0; i < PORT_PIN_NUM; i++) { - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint8_t bit = 0; - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - // Set direction for masked pins - switch (dir) { - case PIN_INPUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_INPUT); - } - } - break; - case PIN_OUTPUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_OUTPUT); - } - } - break; - case PIN_INOUT: - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - pin_function((PinName)bit, PIN_INOUT); - } - } - break; - default: - break; - } -} - -void port_write(port_t *obj, int value) -{ - uint8_t port_data = 0; - uint8_t data = 0; - int bit = 0; - uint8_t val = 0; - uint32_t base; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - base = BITBAND_PORT_BASE(obj->port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - // Get current data of port - for (bit = 7; bit >= 0; bit--) { - BITBAND_PORT_READ(val, base, bit); - port_data <<= 1; - port_data |= val; - } - // Calculate data to write to masked pins - data = (port_data & ~obj->mask) | (value & obj->mask); - for (bit = 0; bit < PORT_PIN_NUM; bit++) { - if (((obj->mask >> bit) & 0x01) == 0x01) { - if(((data >> bit) & 0x01) == GPIO_PIN_SET) { - BITBAND_PORT_SET(base, bit); - } else { - BITBAND_PORT_CLR(base, bit); - } - } - } -} - -int port_read(port_t *obj) -{ - uint8_t port_data = 0; - uint8_t data = 0; - int bit = 0; - uint8_t val = 0; - uint32_t base; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortV); - base = BITBAND_PORT_BASE(obj->port); - base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); - - // Get current data of port - for (bit = 7; bit >= 0; bit--) { - BITBAND_PORT_READ(val, base, bit); - port_data <<= 1; - port_data |= val; - } - // Calculate data of masked pins - data = port_data & obj->mask; - return data; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c deleted file mode 100644 index e83666fc95a..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c +++ /dev/null @@ -1,200 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pwmout_api.h" -#include "pinmap.h" -#include "gpio_include.h" - -static const PinMap PinMap_PWM[] = { - {PB0, PWM_0, PIN_DATA(5, 1)}, - {PC0, PWM_1, PIN_DATA(4, 1)}, - {PJ0, PWM_2, PIN_DATA(4, 1)}, - {PK2, PWM_3, PIN_DATA(4, 1)}, - {PN0, PWM_4, PIN_DATA(4, 1)}, - {PL5, PWM_5, PIN_DATA(4, 1)}, - {PG2, PWM_6, PIN_DATA(4, 1)}, - {NC, NC, 0} -}; - -static const uint32_t prescale_tbl[] = { - 2, 8, 32, 128, 256, 512, 1024 -}; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - uint16_t counter = 0; - - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); // Determine the pwm channel - MBED_ASSERT(pwm != (PWMName)NC); - - switch (pwm) { - case PWM_0: - obj->channel = TSB_T32A1; - TSB_CG_FSYSENA_IPENA25 = ENABLE; - TSB_CG_FSYSENA_IPENA01 = ENABLE; - break; - case PWM_1: - obj->channel = TSB_T32A2; - TSB_CG_FSYSENA_IPENA26 = ENABLE; - TSB_CG_FSYSENA_IPENA02 = ENABLE; - break; - case PWM_2: - obj->channel = TSB_T32A3; - TSB_CG_FSYSENA_IPENA27 = ENABLE; - TSB_CG_FSYSENA_IPENA08 = ENABLE; - break; - case PWM_3: - obj->channel = TSB_T32A4; - TSB_CG_FSYSENA_IPENA28 = ENABLE; - TSB_CG_FSYSENA_IPENA09 = ENABLE; - break; - case PWM_4: - obj->channel = TSB_T32A5; - TSB_CG_FSYSENA_IPENA29 = ENABLE; - TSB_CG_FSYSENA_IPENA12 = ENABLE; - break; - case PWM_5: - obj->channel = TSB_T32A6; - TSB_CG_FSYSENA_IPENA30 = ENABLE; - TSB_CG_FSYSENA_IPENA10 = ENABLE; - break; - case PWM_6: - obj->channel = TSB_T32A7; - TSB_CG_FSYSENA_IPENA31 = ENABLE; - TSB_CG_FSYSENA_IPENA06 = ENABLE; - break; - default: - obj->channel = NULL; - break; - } - - pinmap_pinout(pin, PinMap_PWM); // Set pin function as PWM - obj->pin = pin; - obj->period = DEFAULT_PERIOD; - obj->divisor = DEFAULT_CLOCK_DIVISION; - obj->channel->MOD = (T32A_MODE_32 | T32A_DBG_HALT_STOP); - obj->channel->RUNC = (T32A_COUNT_STOP | T32A_COUNT_DONT_START | T32A_RUN_DISABLE); - obj->channel->CRC = (T32A_PRSCLx_32 | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); - obj->channel->OUTCRC0 = T32A_OCR_DISABLE; - obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); - counter = ((DEFAULT_PERIOD * (SystemCoreClock)) / obj->divisor); - obj->channel->RGC0 = counter; - obj->channel->RGC1 = counter; - obj->trailing_timing = counter; - obj->leading_timing = counter; -} - -void pwmout_free(pwmout_t* obj) -{ - // Stops and clear count operation - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - pwmout_write(obj, 0); - obj->pin = NC; - obj->channel = NULL; - obj->trailing_timing = 0; - obj->leading_timing = 0; - obj->divisor = 0; -} - -void pwmout_write(pwmout_t* obj, float value) -{ - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); // Stop timer for setting clock again - obj->leading_timing = (obj->trailing_timing - - (obj->trailing_timing * value)); // leading_timing value - obj->channel->RGC0 = obj->leading_timing; // Setting TBxRG0 register - obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation -} - -float pwmout_read(pwmout_t* obj) -{ - float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) - / obj->trailing_timing); - return duty_cycle; -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - float seconds = 0; - int cycles = 0; - uint32_t clkdiv = 0; - int i = 0; - float duty_cycle = 0; - - seconds = (float)(us / 1000000.0f); - // Select highest timer resolution - for (i = 0; i < 7; ++i) { - cycles = (int)(((SystemCoreClock) / prescale_tbl[i]) * seconds); - if (cycles <= MAX_COUNTER_16B) { - clkdiv = i + 1; // range 1:7 - clkdiv <<= 28; - break; - } else { - cycles = MAX_COUNTER_16B; - clkdiv = 7; - clkdiv <<= 28; - } - } - // Stop timer for setting clock again - obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - // Restore the duty-cycle - duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) - / obj->trailing_timing); - obj->trailing_timing = cycles; - obj->leading_timing = (cycles - (cycles * duty_cycle)); - // Change the source clock division and period - obj->channel->MOD = T32A_MODE_32; - obj->channel->CRC = (clkdiv | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); - obj->channel->OUTCRC0 = T32A_OCR_DISABLE; - obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); - obj->channel->RGC0 = obj->leading_timing; - obj->channel->RGC1 = obj->trailing_timing; - obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float seconds = 0; - float value = 0; - - seconds = (float)(us / 1000000.0f); - value = (((seconds / obj->period) * 100.0f) / 100.0f); - - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c deleted file mode 100644 index 3b85770b6dc..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c +++ /dev/null @@ -1,471 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "serial_api.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_include.h" -#include "objects.h" - -static const PinMap PinMap_UART_TX[] = { - {PA1, SERIAL_0, PIN_DATA(1, 1)}, - {PJ1, SERIAL_1, PIN_DATA(1, 1)}, - {PB2, SERIAL_2, PIN_DATA(5, 1)}, - {PA6, SERIAL_3, PIN_DATA(2, 1)}, - {PV6, SERIAL_4, PIN_DATA(1, 1)}, - {PN2, SERIAL_5, PIN_DATA(2, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PA2, SERIAL_0, PIN_DATA(1, 0)}, - {PJ2, SERIAL_1, PIN_DATA(1, 0)}, - {PB3, SERIAL_2, PIN_DATA(5, 0)}, - {PA7, SERIAL_3, PIN_DATA(2, 0)}, - {PV7, SERIAL_4, PIN_DATA(1, 0)}, - {PN3, SERIAL_5, PIN_DATA(2, 0)}, - {NC, NC, 0} -}; - -#define UART_NUM 6 - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void uart_init(TSB_UART_TypeDef * UARTx, uart_inittypedef_t * InitStruct); -static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate); -static void uart_swreset(TSB_UART_TypeDef * UARTx); - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart_name != NC); - - obj->index = uart_name; - switch (uart_name) { /* Initialize UART instance */ - case SERIAL_0: - obj->UARTx = UART0; - TSB_CG_FSYSENB_IPENB05 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - break; - case SERIAL_1: - obj->UARTx = UART1; - TSB_CG_FSYSENB_IPENB06 = ENABLE; - TSB_CG_FSYSENA_IPENA08 = ENABLE; - break; - case SERIAL_2: - obj->UARTx = UART2; - TSB_CG_FSYSENB_IPENB07 = ENABLE; - TSB_CG_FSYSENA_IPENA01 = ENABLE; - break; - case SERIAL_3: - obj->UARTx = UART3; - TSB_CG_FSYSENB_IPENB08 = ENABLE; - TSB_CG_FSYSENA_IPENA00 = ENABLE; - break; - case SERIAL_4: - obj->UARTx = UART4; - TSB_CG_FSYSENB_IPENB09 = ENABLE; - TSB_CG_FSYSENA_IPENA17 = ENABLE; - break; - case SERIAL_5: - obj->UARTx = UART5; - TSB_CG_FSYSENB_IPENB10 = ENABLE; - TSB_CG_FSYSENA_IPENA12 = ENABLE; - break; - default: - error("UART is not available"); - break; - } - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC && rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX; - } else { - if (tx != NC) { - obj->uart_config.Mode = UART_ENABLE_TX; - } else { - if (rx != NC) { - obj->uart_config.Mode = UART_ENABLE_RX; - } - } - } - obj->uart_config.BaudRate = 9600; - obj->uart_config.DataBits = 8; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = ParityNone; - obj->uart_config.FlowCtrl = FlowControlNone; - - uart_init(obj->UARTx, &obj->uart_config); - is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - obj->UARTx->TRANS = 0; - obj->UARTx->CR0 = 0; - obj->UARTx->CR1 = 0; - - uart_swreset(obj->UARTx); - - obj->uart_config.BaudRate = 0; - obj->uart_config.DataBits = 0; - obj->uart_config.StopBits = 0; - obj->uart_config.Parity = 0; - obj->uart_config.Mode = 0; - obj->uart_config.FlowCtrl = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->uart_config.BaudRate = baudrate; - uart_init(obj->UARTx, &obj->uart_config); -} -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits - - obj->uart_config.DataBits = data_bits; - obj->uart_config.StopBits = stop_bits; - obj->uart_config.Parity = parity; - uart_init(obj->UARTx, &obj->uart_config); -} - -void INTUART0TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); -} - -void INTUART0RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); -} - -void INTUART1TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); -} - -void INTUART1RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); -} -void INTUART2TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], TxIrq); -} - -void INTUART2RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], RxIrq); -} - -void INTUART3TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], TxIrq); -} - -void INTUART3RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], RxIrq); -} - -void INTUART4TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], TxIrq); -} - -void INTUART4RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], RxIrq); -} - -void INTUART5TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], TxIrq); -} - -void INTUART5RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], RxIrq); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - switch (obj->index) { - case SERIAL_0: - if (irq == RxIrq) { - irq_n = INTUART0RX_IRQn; - } else { - irq_n = INTUART0TX_IRQn; - } - break; - case SERIAL_1: - if (irq == RxIrq) { - irq_n = INTUART1RX_IRQn; - } else { - irq_n = INTUART1TX_IRQn; - } - break; - case SERIAL_2: - if (irq == RxIrq) { - irq_n = INTUART2RX_IRQn; - } else { - irq_n = INTUART2TX_IRQn; - } - break; - case SERIAL_3: - if (irq == RxIrq) { - irq_n = INTUART3RX_IRQn; - } else { - irq_n = INTUART3TX_IRQn; - } - break; - case SERIAL_4: - if (irq == RxIrq) { - irq_n = INTUART4RX_IRQn; - } else { - irq_n = INTUART4TX_IRQn; - } - break; - case SERIAL_5: - if (irq == RxIrq) { - irq_n = INTUART5RX_IRQn; - } else { - irq_n = INTUART5TX_IRQn; - } - break; - default: - break; - } - NVIC_ClearPendingIRQ(irq_n); - if (enable) { - NVIC_EnableIRQ(irq_n); - } else { - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) -{ - int data = 0; - - while (!serial_readable(obj)) { // Wait until Rx buffer is full - // Do nothing - } - - if (obj->uart_config.Mode & UART_ENABLE_TX) { - obj->UARTx->TRANS &= 0x0D; - } - - data = data | (obj->UARTx->DR & 0xFFU); - - if (obj->uart_config.Mode & UART_ENABLE_TX) { - obj->UARTx->TRANS |= UART_ENABLE_TX; - } - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - - while (!serial_writable(obj)) { - // Do nothing - } - - if (obj->uart_config.Mode & UART_ENABLE_RX) { - obj->UARTx->TRANS &= 0x0E; - } - - obj->UARTx->DR = c & 0xFFU; - - if (obj->uart_config.Mode & UART_ENABLE_RX) { - obj->UARTx->TRANS |= UART_ENABLE_RX; - } -} - -int serial_readable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x0000000F) != 0) { - ret = 1; - } - return ret; -} - -int serial_writable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR &0x8000) == 0) { - ret = 1; - } - - return ret; -} - -void serial_clear(serial_t *obj) -{ - obj->UARTx->FIFOCLR = 0x03; -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - obj->UARTx->TRANS |= 0x08; -} - -void serial_break_clear(serial_t *obj) -{ - obj->UARTx->TRANS &= ~(0x08); -} - -static void uart_swreset(TSB_UART_TypeDef * UARTx) -{ - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } - - UARTx->SWRST = UARTxSWRST_SWRST_10; - UARTx->SWRST = UARTxSWRST_SWRST_01; - - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } -} - -static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate) -{ - uint32_t clock = 0U; - uint32_t k = 0U; - uint64_t tx = 0U; - uint64_t work = 1U; - uint64_t p_range64 = 0U; - uint64_t boud64 = 0; - uint64_t tx64 = 0; - uint64_t work64 = 1; - - SystemCoreClockUpdate(); // Get the peripheral I/O clock frequency - clock = SystemCoreClock; - tx = (uint64_t)((uint64_t)clock << 6); - tx /= work; - tx64 = (uint64_t)((uint64_t)clock << 8); - tx64 /= work64; - work = ((uint64_t)boudrate); - tx /= work; - tx >>= 4; - - boud64 = (64U * boudrate); - p_range64 = ((boud64 / 100) * 3); - - for (k=UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX); k++) { - work = tx + k; - if (work >= (uint64_t)((uint64_t)1 << 6)) { - work -= (uint64_t)((uint64_t)1 << 6); - work >>= 6; - if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { - work64 = work <<6; - work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); - work64 = (tx64 / work64); - if (((boud64 - p_range64) <= work64) && (work64 <= (boud64 + p_range64))) { - brddiviser->brn = work; - brddiviser->brk = k; - break; - } - } - } - } -} - -static void uart_init(TSB_UART_TypeDef * UARTx, uart_inittypedef_t * InitStruct) -{ - uart_boudrate_t UTx_brd = {0}; - uint32_t brk; - uint32_t tmp; - uint32_t parity_check; - uint32_t data_length; - - UARTx->CLK = UART_PLESCALER_1; // Register Setting - uart_get_boudrate_setting(&UTx_brd, InitStruct->BaudRate); - UTx_brd.ken = UART_DIVISION_ENABLE; - brk = (UTx_brd.brk << 16); - UARTx->BRD = (UTx_brd.ken | brk | UTx_brd.brn); - parity_check = (InitStruct->Parity == ParityOdd) ? 1 : ((InitStruct->Parity == ParityEven) ? 3 : 0); - data_length = (InitStruct->DataBits) == 8 ? 1 : (((InitStruct->DataBits) == 7) ? 0 : 2); - tmp = (((InitStruct->FlowCtrl) << 9) | ((InitStruct->StopBits) << 4) | (parity_check << 2) | data_length); - UARTx->CR0 = tmp; - UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); - UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); - UARTx->TRANS = InitStruct->Mode; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c b/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c deleted file mode 100644 index 9e1d93c2b1f..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "gpio_include.h" - -static void warming_up_time(void); - -void hal_sleep(void) -{ - // Set low power consumption mode IDLE - TSB_CG->STBYCR = CG_STBY_MODE_IDLE; - __DSB(); // Enter idle mode - __WFI(); -} - -void hal_deepsleep(void) -{ - uint32_t tmp; - // WDT sysclock enable - TSB_CG_FSYSENB_IPENB31 = ENABLE; - while ((TSB_FC->SR0 & 0x01) != 0x01); // Flash Wait - // Wait for end of Warming-up for IHOSC1 - while(TSB_CG_WUPHCR_WUEF); - // Set Warm-up clock to IHOSC1 - TSB_CG_WUPHCR_WUCLK = DISABLE; - // Set Warming-up time (xxxx) for IHOSC1 return from STOP1 mode - warming_up_time(); - // Set low power consumption mode STOP1 - TSB_CG->STBYCR = CG_STBY_MODE_STOP1; - // Set PLL of fsys to fosc(= PLL no USE) - TSB_CG_PLL0SEL_PLL0SEL = DISABLE; - // Wait for PLL status of fsys until off state(fosc = 0) - while(TSB_CG_PLL0SEL_PLL0ST); - TSB_CG_PLL0SEL_PLL0ON = DISABLE; // Stop PLL of fsys - TSB_CG_OSCCR_IHOSC1EN = ENABLE; // Enable IHOSC1 - TSB_CG_OSCCR_OSCSEL = DISABLE; // Set fosc to IHOSC1 - while(TSB_CG_OSCCR_OSCF); // Wait for fosc status until IHOSC1 - tmp = TSB_CG->OSCCR; // Set EHOSC off - tmp &= EXTERNEL_OSC_MASK; - TSB_CG->OSCCR = tmp; - TSB_CG_OSCCR_IHOSC2EN = DISABLE; //Stop IHOSC2 of OFD - // Wait for status of OFD until off ”0” - while(TSB_CG_OSCCR_IHOSC2F); - __DSB(); // Enter STOP1 mode - __WFI(); -} - -static void warming_up_time(void) -{ - uint32_t work; - uint64_t x; - x = (uint64_t)((uint64_t)(IHOSC_CFG_WARM_UP_TIME) * (uint64_t)(IHOSC_CFG_CLOCK)); - x = (uint64_t)(x / (uint64_t)(1000000)); - if (x > (uint64_t)(0xFFFF)) { - // invalid value - } - work = (uint32_t)x; - work &= (uint32_t)(0xFFFFFFF0); - work <<= 16; - work |= (uint32_t)(TSB_CG->WUPHCR & ~CGWUPHCR_WUPT_HIGH_MASK); - TSB_CG->WUPHCR = work; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c deleted file mode 100644 index 9865a4d0429..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c +++ /dev/null @@ -1,329 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "spi_api.h" -#include "mbed_error.h" -#include "pinmap.h" -#include "gpio_include.h" - -#if DEVICE_SPI_ASYNCH -#define SPI_S(obj) (struct spi_s *) (&((obj)->spi)) -#else -#define SPI_S(obj) (struct spi_s *) (obj) -#endif - -static const PinMap PinMap_SPI_SCLK[] = { - {PM0, SPI_0, PIN_DATA(3, 1)}, - {PB2, SPI_1, PIN_DATA(3, 1)}, - {PT2, SPI_2, PIN_DATA(1, 1)}, - {PP5, SPI_3, PIN_DATA(1, 1)}, - {PH4, SPI_4, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PM1, SPI_0, PIN_DATA(3, 1)}, - {PB3, SPI_1, PIN_DATA(3, 1)}, - {PT3, SPI_2, PIN_DATA(1, 1)}, - {PP4, SPI_3, PIN_DATA(1, 1)}, - {PH5, SPI_4, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PM2, SPI_0, PIN_DATA(3, 0)}, - {PB4, SPI_1, PIN_DATA(3, 0)}, - {PT4, SPI_2, PIN_DATA(1, 0)}, - {PP3, SPI_3, PIN_DATA(1, 0)}, - {PH6, SPI_4, PIN_DATA(1, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PM3, SPI_0, PIN_DATA(3, 1)}, - {PB5, SPI_1, PIN_DATA(3, 1)}, - {PT1, SPI_2, PIN_DATA(2, 1)}, - {PP6, SPI_3, PIN_DATA(1, 1)}, - {NC, NC, 0} -}; - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - // Check pin parameters - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj_s->module = (SPIName)pinmap_merge(spi_data, spi_cntl); - spi = obj_s->spi; - switch ((int)obj_s->module) { - case SPI_0: - TSB_CG_FSYSENA_IPENA11 = ENABLE; - TSB_CG_FSYSENB_IPENB00 = ENABLE; - spi = TSB_TSPI0; - break; - case SPI_1: - TSB_CG_FSYSENA_IPENA01 = ENABLE; - TSB_CG_FSYSENB_IPENB01 = ENABLE; - spi = TSB_TSPI1; - break; - case SPI_2: - TSB_CG_FSYSENA_IPENA15 = ENABLE; - TSB_CG_FSYSENB_IPENB02 = ENABLE; - spi = TSB_TSPI2; - break; - case SPI_3: - TSB_CG_FSYSENA_IPENA13 = ENABLE; - TSB_CG_FSYSENB_IPENB03 = ENABLE; - spi = TSB_TSPI3; - break; - case SPI_4: - TSB_CG_FSYSENA_IPENA07 = ENABLE; - TSB_CG_FSYSENB_IPENB04 = ENABLE; - spi = TSB_TSPI4; - break; - default: - error("Cannot found SPI module corresponding with input pins."); - break; - } - obj_s->spi = spi; - // pin out the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - - // TTSPI Software Reset - spi->CR0 = TSPI_RESET10; - spi->CR0 = TSPI_RESET01; - - // Wait for 2 clocks of reset completion - __NOP(); - __NOP(); - - // Enable the selected TSPI peripheral (TTSPIE) - spi->CR0 = TSPI_ENABLE; - spi->CR1 = 0; - spi->CR1 = TSPI_MASTER_OPEARTION; - spi->CR2 = 0; - spi->CR2 = (TSPI_TIDLE_LOW | TSPI_TXDEMP_HI); - // Format control0 Register Set - spi->FMTR0 = (TSPI_DATA_DIRECTION_MSB | TSPI_DATA_LENGTH_8 | - TSPI_MIN_IDLE_TIME_1); - // Format control1 Register Set - spi->FMTR1 = 0; - // Enable the selected TSPI peripheral - spi->CR0 |= TSPI_ENABLE; - spi_frequency(obj, 1000000); -} - -void spi_free(spi_t *obj) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - - spi = obj_s->spi; - spi->CR0 |= TSPI_DISABLE; - spi->CR2 = TSPI_INT_ALL; // Disable all interrupt -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - - obj_s->bits = bits; - spi = obj_s->spi; - obj_s->bits = bits; - spi->CR0 |= TSPI_DISABLE; - - if (bits >= 8 || bits <= 32) { - spi->FMTR0 |= (bits << 24); - } else { - // Do nothing - } - spi->FMTR0 |= (((mode >> 1) & 0x1) << 14); - spi->FMTR0 |= ((mode & 0x01) << 15); - spi->CR0 |= TSPI_ENABLE; -} - -void spi_frequency(spi_t *obj, int hz) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - int clk_div = 1; - uint32_t clocks = ((SystemCoreClock / 2) / hz); - obj_s->spi->CR0 |= TSPI_DISABLE; - - while (clk_div < 10) { - if (clocks < 16) { - break; - } - clk_div++; - clocks >>= 1; - } - clk_div--; - if (clk_div == 0) { - clocks++; - } - spi = obj_s->spi; - spi->CR0 |= TSPI_DISABLE; - spi->BR = ((clk_div << 4) | clocks); - spi->CR0 |= TSPI_ENABLE; -} - -int spi_master_write(spi_t *obj, int value) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - MBED_ASSERT(obj_s != NULL); - spi = obj_s->spi; - spi->CR3 |= TSPI_TX_BUFF_CLR_DONE; // FIFO Cear - // Check if the TSPI is already enabled - if((spi->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { - spi->CR0 |= TSPI_ENABLE; - } - // Enable TSPI Transmission Control - spi->CR1 |= TSPI_TRXE_ENABLE; - // Check the current fill level - if(((spi->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { - do { - spi->DR = (value & TSPI_DR_8BIT_MASK); - // check complete transmit - } while ((spi->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE); - spi->CR3 |= TSPI_TX_BUFF_CLR_DONE; - spi->CR1 &= TSPI_TRXE_DISABLE_MASK; - } - if((spi->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - // Enable TSPI Transmission Control - spi->CR1 |= TSPI_TRXE_ENABLE; - } - // Check if the TSPI is already enabled - if((spi->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { - // Enable TSPI Transmission Control - spi->CR0 |= TSPI_ENABLE; - } - value = 0; - // Wait until Receive Complete Flag is set to receive data - if((spi->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { - // Check the remain data exist - if((spi->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { - value = (spi->DR & TSPI_DR_8BIT_MASK); - } - spi->SR |= TSPI_RX_DONE_CLR; // Receive Complete Flag is clear - spi->CR2 |= TSPI_RX_BUFF_CLR_DONE; // FIFO Clear - spi->CR1 &= TSPI_TRXE_DISABLE_MASK; - } - return value; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_busy(spi_t *obj) -{ - struct spi_s *obj_s = SPI_S(obj); - TSB_TSPI_TypeDef* spi; - uint8_t result = 0; - - spi = obj_s->spi; - if( (spi->SR & (1<<7)) || (spi->SR & (1<<23))) { - result = 1; - } else { - result = 0; - } - return result; -} - -uint8_t spi_get_module(spi_t *obj) -{ - struct spi_s *obj_s = SPI_S(obj); - return (uint8_t)(obj_s->module); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c b/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c deleted file mode 100644 index 6a0ef9f8517..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c +++ /dev/null @@ -1,101 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "us_ticker_api.h" -#include "gpio_include.h" - - -#define T32A_INT_MASK ((uint32_t)0x0000000F) -#define TXZ_ENABLE 1 -static bool us_ticker_inited = false; // Is ticker initialized yet? - -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = { - 1248125, // (39.94 MHz / 32 ) - 32 // 32 bit counter - }; - return &info; -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) { - us_ticker_disable_interrupt(); - return; - } - us_ticker_inited = true; - - TSB_CG_FSYSENA_IPENA24 = TXZ_ENABLE; - TSB_T32A0->MOD = T32A_MODE_32; - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->CRC = T32A_PRSCLx_32; - TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); - - NVIC_SetVector(INTT32A00C_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(INTT32A00C_IRQn); -} - -uint32_t us_ticker_read(void) -{ - if (!us_ticker_inited) { - us_ticker_init(); - } - - return (TSB_T32A0->TMRC); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - NVIC_DisableIRQ(INTT32A00C_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->RGC1 = timestamp; - NVIC_EnableIRQ(INTT32A00C_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(INTT32A00C_IRQn); - NVIC_EnableIRQ(INTT32A00C_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - // Disable interrupts by NVIC - NVIC_DisableIRQ(INTT32A00C_IRQn); - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); - TSB_T32A0->STC = T32A_INT_MASK; -} - -void us_ticker_clear_interrupt(void) -{ - TSB_T32A0->STC = T32A_INT_MASK; - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); -} - -void us_ticker_free(void) -{ - TSB_T32A0->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - us_ticker_inited = false; - TSB_T32A0->STC = 0x0F; - // Clear Pending interrupt in NVIC - NVIC_ClearPendingIRQ(INTT32A00C_IRQn); - // Disable interrupt in NVIC - NVIC_DisableIRQ(INTT32A00C_IRQn); - // Disable Clock. - TSB_CG_FSYSENA_IPENA24 = 0; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc.h deleted file mode 100644 index 4ffb4cd46a1..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc.h +++ /dev/null @@ -1,499 +0,0 @@ -/** - ******************************************************************************* - * @file adc.h - * @brief This file provides all the functions prototypes for ADC driver. - * @version V1.0.0.0 - * $Date:: 2017-09-12 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __ADC_H -#define __ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -#include "adc_ch.h" -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @defgroup ADC ADC - * @brief ADC Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_define ADC Exported Define - * @{ - */ - -/** - * @defgroup ADC_ChannelMax Channel Num Max - * @brief Max Num of channel. - * @{ - */ - - #define ADC_NUM_MAX ((uint32_t)24) /*!< Max Num of conversion. */ -/** - * @} - */ /* End of group ADC_ChannelMax */ -/** - * @} - */ /* End of group ADC_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - @defgroup ADC_Exported_define ADC Exported Define - @{ - */ -/** @enum adc_sampling_period0_t - @brief Outside AIN sampling period. - */ -typedef enum -{ - ADC_SAMPLING_PERIOD0_XN = 0x00, /*!< SCLK Period (1/SCLK)xN */ - ADC_SAMPLING_PERIOD0_X2N = 0x08, /*!< SCLK Period (1/SCLK)x2N */ - ADC_SAMPLING_PERIOD0_X3N = 0x10, /*!< SCLK Period (1/SCLK)x3N */ - ADC_SAMPLING_PERIOD0_X4N = 0x18, /*!< SCLK Period (1/SCLK)x4N */ - ADC_SAMPLING_PERIOD0_X16N = 0x28, /*!< SCLK Period (1/SCLK)x16N */ - ADC_SAMPLING_PERIOD0_X64N = 0x38, /*!< SCLK Period (1/SCLK)x64N */ -}adc_sampling_period0_t; -/** @enum adc_sampling_period1_t - @brief Outside AIN sampling period. - */ -typedef enum -{ - ADC_SAMPLING_PERIOD1_XN = 0x000, /*!< SCLK Period (1/SCLK)xN */ - ADC_SAMPLING_PERIOD1_X2N = 0x100, /*!< SCLK Period (1/SCLK)x2N */ - ADC_SAMPLING_PERIOD1_X3N = 0x200, /*!< SCLK Period (1/SCLK)x3N */ - ADC_SAMPLING_PERIOD1_X4N = 0x300, /*!< SCLK Period (1/SCLK)x4N */ - ADC_SAMPLING_PERIOD1_X16N = 0x500, /*!< SCLK Period (1/SCLK)x16N */ - ADC_SAMPLING_PERIOD1_X64N = 0x700, /*!< SCLK Period (1/SCLK)x64N */ -}adc_sampling_period1_t; - -/*! @enum adc_sclk_t - @brief Select AD prescaler output (SCLK). - */ -typedef enum -{ - ADC_SCLK_1 = (0x00000000U), /*!< ADCLK/1 */ - ADC_SCLK_2 = (0x00000001U), /*!< ADCLK/2 */ - ADC_SCLK_4 = (0x00000002U), /*!< ADCLK/4 */ - ADC_SCLK_8 = (0x00000003U), /*!< ADCLK/8 */ - ADC_SCLK_16 = (0x00000004U), /*!< ADCLK/16 */ -}adc_sclk_t; - -/*! @enum adc_mod1_t - @brief Select SCLK Frequency Band (MOD1). - */ -typedef enum -{ - ADC_MOD1_SCLK_1 = (0x00001000U), /*!< SCLK =< 40MHz > */ - ADC_MOD1_SCLK_2 = (0x00003000U), /*!< 40MHz < SCLK =< 50MHz > */ - ADC_MOD1_SCLK_3 = (0x00004000U), /*!< 50MHz < SCLK =< 60MHz > */ - ADC_MOD1_SCLK_4 = (0x00106011U), /*!< 60MHz < SCLK =< 80MHz > */ -}adc_mod1_t; - -/*! @enum adc_mod2_t - @brief Select ADC Product Setting Value (MOD2). - */ -typedef enum -{ - ADC_MOD2_TMPM4G9 = (0x00000000U), /*!< TMPM4G9 */ - ADC_MOD2_CLEAR = (0x00000000U), /*!< Reset Value */ -}adc_mod2_t; - -/*! @enum adc_int_t - @brief Select Interrupt Enable/Disable. - */ -typedef enum -{ - ADC_INT_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_INT_ENABLE = (0x00000080U), /*!< Enable. */ -}adc_int_t; - -/*! @enum adc_conversion_t - @brief Select conversion method. - */ -typedef enum -{ - ADC_CONVERSION_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_CONVERSION_CNT = (0x00000100U), /*!< Continuation. */ - ADC_CONVERSION_SGL = (0x00000200U), /*!< Single. */ - ADC_CONVERSION_TRG = (0x00000300U), /*!< Universal Trigger. */ - ADC_CONVERSION_HPTG = (0x00000400U), /*!< High Priority Trigger. */ -}adc_conversion_t; - -/*! @enum adc_dma_int_t - @brief Select DMA interrupt method. - */ -typedef enum -{ - ADC_DMA_INT_SGL_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_DMA_INT_SGL_ENABLE = (0x00000020U), /*!< DMA Single interrupt Enable. */ - ADC_DMA_INT_CNT_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_DMA_INT_CNT_ENABLE = (0x00000040U), /*!< DMA Continuation interrupt Enable. */ - ADC_DMA_INT_TRG_DISABLE = (0x00000000U), /*!< Disable. */ - ADC_DMA_INT_TRG_ENABLE = (0x00000010U), /*!< DMA Universal Trigger interrupt Enable. */ - ADC_TRG_DISABLE = (0x00000000U), /*!< Universal Trigger Disable. */ - ADC_TRG_ENABLE = (0x00000001U), /*!< Universal Trigger Enable. */ - ADC_HPTG_DISABLE = (0x00000000U), /*!< High Priority Trigger Disable. */ - ADC_HPTG_ENABLE = (0x00000002U), /*!< High Priority Trigger Enable. */ -}adc_dma_int_t; - -/*! @enum adc_ain_range_t - @brief Range of AIN Macro Definisiton. - Range of AIN be set "(ADC_AIN_RANGE_MIN <= Value <= ADC_AIN_RANGE_MAX)". - */ -typedef enum -{ - ADC_AIN_RANGE_MIN = (0x00000000U), /*!< Minimum Value :AINx00 */ - ADC_AIN_RANGE_MAX = (0x00000017U), /*!< Maximum Value :AINx23 */ -}adc_ain_range_t; - -/*! @enum adc_status_t - @brief AD Running Status. - */ -typedef enum -{ - ADC_STATUS_MASK = (0x00000080U), /*!< for Mask. */ - ADC_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_STATUS_RUNNING = (0x00000080U), /*!< Running. */ -}adc_status_t; - -/*! @enum adc_cnt_status_t - @brief Continuity Conversion Running Status. - */ -typedef enum -{ - ADC_CNT_STATUS_MASK = (0x00000008U), /*!< for Mask. */ - ADC_CNT_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_CNT_STATUS_RUNNING = (0x00000008U), /*!< Running. */ -}adc_cnt_status_t; - -/*! @enum adc_sgl_status_t - @brief Single Conversion Running Status. - */ -typedef enum -{ - ADC_SGL_STATUS_MASK = (0x00000004U), /*!< for Mask. */ - ADC_SGL_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_SGL_STATUS_RUNNING = (0x00000004U), /*!< Running. */ -}adc_sgl_status_t; - -/*! @enum adc_trg_status_t - @brief Trigger Conversion Running Status. - */ -typedef enum -{ - ADC_TRG_STATUS_MASK = (0x00000002U), /*!< for Mask. */ - ADC_TRG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_TRG_STATUS_RUNNING = (0x00000002U), /*!< Running. */ -}adc_trg_status_t; - -/*! @enum adc_hpri_status_t - @brief Trigger Conversion Running Status. - */ -typedef enum -{ - ADC_HPTG_STATUS_MASK = (0x00000001U), /*!< for Mask. */ - ADC_HPTG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ - ADC_HPTG_STATUS_RUNNING = (0x00000001U), /*!< Running. */ -}adc_hpri_status_t; - -/*! @enum adcmpxen_t - @brief Select Enable, Disable setting(ADxCMPEN). - */ -typedef enum -{ - ADCMP3EN_DISABLE = (0x00000000U), /*!< Disable. */ - ADCMP3EN_ENABLE = (0x00000008U), /*!< Enable. */ - ADCMP2EN_DISABLE = (0x00000000U), /*!< Disable. */ - ADCMP2EN_ENABLE = (0x00000004U), /*!< Enable. */ - ADCMP1EN_DISABLE = (0x00000000U), /*!< Disable. */ - ADCMP1EN_ENABLE = (0x00000002U), /*!< Enable. */ - ADCMP0EN_DISABLE = (0x00000000U), /*!< Disable. */ - ADCMP0EN_ENABLE = (0x00000001U), /*!< Enable. */ -}adcmpxen_t; - -/*! @enum adcmpcnt_t - @brief Select Compare count num. - */ -typedef enum -{ - ADCMPCNT_1 = (0x00000000U), /*!< 1 time */ - ADCMPCNT_2 = (0x00000100U), /*!< 2 times */ - ADCMPCNT_3 = (0x00000200U), /*!< 3 times */ - ADCMPCNT_4 = (0x00000300U), /*!< 4 times */ - ADCMPCNT_5 = (0x00000400U), /*!< 5 times */ - ADCMPCNT_6 = (0x00000500U), /*!< 6 times */ - ADCMPCNT_7 = (0x00000600U), /*!< 7 times */ - ADCMPCNT_8 = (0x00000700U), /*!< 8 times */ - ADCMPCNT_9 = (0x00000800U), /*!< 9 times */ - ADCMPCNT_10 = (0x00000900U), /*!< 10 times */ - ADCMPCNT_11 = (0x00000a00U), /*!< 11 times */ - ADCMPCNT_12 = (0x00000b00U), /*!< 12 times */ - ADCMPCNT_13 = (0x00000c00U), /*!< 13 times */ - ADCMPCNT_14 = (0x00000d00U), /*!< 14 times */ - ADCMPCNT_15 = (0x00000e00U), /*!< 15 times */ - ADCMPCNT_16 = (0x00000f00U), /*!< 16 times */ -}adcmpcnt_t; - -/*! @enum adcmpcond_t - @brief Compare condition - */ -typedef enum -{ - ADCMPCond_CNT = (0x00000000U), /*!< Continuous */ - ADCMPCond_ACC = (0x00000040U), /*!< Accumulation */ -}adcmpcond_t; - -/*! @enum adcmpbigsml_t - @brief Compare Big, Small condition - */ -typedef enum -{ - ADCMPBigSml_Big = (0x00000000U), /*!< Big */ - ADCMPBigSml_Sml = (0x00000020U), /*!< Small */ -}adcmpbigsml_t; - -/*! @enum adcmpstr_t - @brief Select Compare Store register - */ -typedef enum -{ - ADCMPStr_Reg0 = (0x00000000U), /*!< ADxREG0 */ - ADCMPStr_Reg1 = (0x00000001U), /*!< ADxREG1 */ - ADCMPStr_Reg2 = (0x00000002U), /*!< ADxREG2 */ - ADCMPStr_Reg3 = (0x00000003U), /*!< ADxREG3 */ - ADCMPStr_Reg4 = (0x00000004U), /*!< ADxREG4 */ - ADCMPStr_Reg5 = (0x00000005U), /*!< ADxREG5 */ - ADCMPStr_Reg6 = (0x00000006U), /*!< ADxREG6 */ - ADCMPStr_Reg7 = (0x00000007U), /*!< ADxREG7 */ - ADCMPStr_Reg8 = (0x00000008U), /*!< ADxREG8 */ - ADCMPStr_Reg9 = (0x00000009U), /*!< ADxREG9 */ - ADCMPStr_Reg10 = (0x0000000aU), /*!< ADxREG10 */ - ADCMPStr_Reg11 = (0x0000000bU), /*!< ADxREG11 */ - ADCMPStr_Reg12 = (0x0000000cU), /*!< ADxREG12 */ - ADCMPStr_Reg13 = (0x0000000dU), /*!< ADxREG13 */ - ADCMPStr_Reg14 = (0x0000000eU), /*!< ADxREG14 */ - ADCMPStr_Reg15 = (0x0000000fU), /*!< ADxREG15 */ - ADCMPStr_Reg16 = (0x00000010U), /*!< ADxREG16 */ - ADCMPStr_Reg17 = (0x00000011U), /*!< ADxREG17 */ - ADCMPStr_Reg18 = (0x00000012U), /*!< ADxREG18 */ - ADCMPStr_Reg19 = (0x00000013U), /*!< ADxREG19 */ - ADCMPStr_Reg20 = (0x00000014U), /*!< ADxREG20 */ - ADCMPStr_Reg21 = (0x00000015U), /*!< ADxREG21 */ - ADCMPStr_Reg22 = (0x00000016U), /*!< ADxREG22 */ - ADCMPStr_Reg23 = (0x00000017U), /*!< ADxREG23 */ -}adcmpstr_t; -/*! @enum adcexazain_t - @brief Select AIN no. - */ - -typedef enum -{ - ADCEXAZSEL_AIN0 = 0, /*!< AIN0 */ - ADCEXAZSEL_AIN1, /*!< AIN1 */ - ADCEXAZSEL_AIN2, /*!< AIN2 */ - ADCEXAZSEL_AIN3, /*!< AIN3 */ - ADCEXAZSEL_AIN4, /*!< AIN4 */ - ADCEXAZSEL_AIN5, /*!< AIN5 */ - ADCEXAZSEL_AIN6, /*!< AIN6 */ - ADCEXAZSEL_AIN7, /*!< AIN7 */ - ADCEXAZSEL_AIN8, /*!< AIN8 */ - ADCEXAZSEL_AIN9, /*!< AIN9 */ - ADCEXAZSEL_AIN10, /*!< AIN10 */ - ADCEXAZSEL_AIN11, /*!< AIN11 */ - ADCEXAZSEL_AIN12, /*!< AIN12 */ - ADCEXAZSEL_AIN13, /*!< AIN13 */ - ADCEXAZSEL_AIN14, /*!< AIN14 */ - ADCEXAZSEL_AIN15, /*!< AIN15 */ - ADCEXAZSEL_AIN16, /*!< AIN16 */ - ADCEXAZSEL_AIN17, /*!< AIN17 */ - ADCEXAZSEL_AIN18, /*!< AIN18 */ - ADCEXAZSEL_AIN19, /*!< AIN19 */ - ADCEXAZSEL_AIN20, /*!< AIN20 */ - ADCEXAZSEL_AIN21, /*!< AIN21 */ - ADCEXAZSEL_AIN22, /*!< AIN22 */ - ADCEXAZSEL_AIN23, /*!< AIN23 */ -}adcexazain_t; -/*! @enum adcexazsel_t - @brief Select sampling period, EXAS0 or EXAS1. - */ -typedef enum -{ - ADCEXAZSEL_EXAZ0 = (0x00000000), /*< EXAZ0 */ - ADCEXAZSEL_EXAZ1 = (0x00000001), /*< EXAZ1 */ -}adcexazsel_t; - -/*! - @} - */ /* End of group ADC_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/*! - @defgroup ADC_Exported_typedef ADC Exported Typedef - @{ - */ - -/*----------------------------------*/ -/*! @struct adc_clock_t - @brief Clock information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - adc_sampling_period0_t exaz0; /*!< Outside AIN0 Sampling period. - : Use @ref adc_sampling_period0_t. */ - adc_sampling_period1_t exaz1; /*!< Outside AIN1 Sampling period. - : Use @ref adc_sampling_period1_t. */ - adc_sclk_t vadcld; /*!< Select AD prescaler output (SCLK). - : Use @ref adc_sclk_t. */ - uint32_t sampling_select; /*!< Sampling period select. : bit0-bit23 */ -} adc_clock_t; - -/*----------------------------------*/ -/*! @struct adc_cmpx_t - @brief Clock information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t CMPEN; /*!< Enable Register status */ - uint32_t CMPCNT; /*!< Compare count num. */ - uint32_t CMPCond; /*!< Compare condition */ - uint32_t CMPBigSml; /*!< Compare Big/Small condition */ - uint32_t StrReg; /*!< Compare Store register */ - uint32_t ADComp; /*!< ADxCMP0 register data */ - void (*handle)(uint32_t id, TXZ_Result result); /*!< Notity Compare Done. */ -} adc_cmpx_t; - -/*----------------------------------*/ -/*! @struct adc_initial_setting_t - @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - adc_clock_t clk; /*!< Clock setting. - : Use @ref adc_clock_t. */ - uint32_t mod1; /*!< AVDD3 voltage band setting. - : Use @ref adc_mod1_t. */ - uint32_t mod2; /*!< Product info setting. - : Use @ref adc_mod2_t. */ - adc_cmpx_t CMPxEN[4]; /*!< adc_cmpx_t. */ - - -} adc_initial_setting_t; - -/*----------------------------------*/ -/*! @struct adc_channel_setting_t - @brief Channel Setting. \n -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t interrupt; /*!< Interrupt Enable/Disable. - : Use @ref adc_dma_int_t. */ - uint32_t type; /*!< Conversion Type. - : Use @ref adc_conversion_t. */ - uint32_t ain; /*!< AIN. */ -} adc_channel_setting_t; - -/*----------------------------------*/ -/*! @struct adc_internal_info_t - @brief Driver internal information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - adc_ch_t ch[ADC_NUM_MAX]; /*!< Channel Instance. */ -} adc_internal_info_t; - -/*----------------------------------*/ -/*! @struct adc_t - @brief ADC handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_AD_TypeDef *p_instance; /*!< Registers base address. */ - adc_initial_setting_t init; /*!< Initial setting. */ - adc_internal_info_t info; /*!< Driver internal information. */ - struct - { - void (*single)(uint32_t id, TXZ_Result result); /*!< Notity Single Conversion Done. */ - void (*continuity)(uint32_t id, TXZ_Result result); /*!< Notity Continuity Conversion Done. */ - void (*trigger)(uint32_t id, TXZ_Result result); /*!< Notity Trigger Conversion Done. */ - void (*highpriority)(uint32_t id, TXZ_Result result); /*!< Notity HighPriority Conversion Done. */ - } handler; /*!< Handler structure. */ -} adc_t; - -/** - * @} - */ /* End of group ADC_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_functions ADC Exported Functions - * @{ - */ -TXZ_Result adc_init(adc_t *p_obj); -TXZ_Result adc_deinit(adc_t *p_obj); -TXZ_Result adc_mode1_setting(void); -TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting); -TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch); -TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); -TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); -TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value); -TXZ_Result adc_start(adc_t *p_obj); -TXZ_Result adc_stop(adc_t *p_obj); -TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status); -TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout); -void adc_compa_irq_handler( void ); -void adc_compb_irq_handler( void ); -void adc_single_irq_handler( void ); -void adc_continuity_irq_handler( void ); -void adc_trigger_irq_handler( void ); -/** - * @} - */ /* End of group ADC_Exported_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ADC_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_ch.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_ch.h deleted file mode 100644 index 098d889a8e6..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_ch.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - ******************************************************************************* - * @file adc_ch.h - * @brief This file provides all the functions prototypes for ADC driver. \n - * Channel Class. - * @version V1.0.0.0 - * $Date:: 2017-09-07 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __ADC_CH_H -#define __ADC_CH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @defgroup ADC ADC - * @brief ADC Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_define ADC Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_define ADC Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_typedef ADC Exported Typedef - * @{ - */ - -/*----------------------------------*/ -/*! @struct adc_ch_initial_setting_t - * @brief Initialize Setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t interrupt; /*!< Interrupt Enable/Disable. - : Use @ref adc_dma_int_t. */ - uint32_t type; /*!< Conversion Type. - : Use @ref adc_conversion_t. */ - uint32_t ain; /*!< AIN. */ -} adc_ch_initial_setting_t; - -/*----------------------------------*/ -/*! @struct adc_ch_t - * @brief ADC handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - __IO uint32_t *p_tset; /*!< ADxTSETn Address. */ - __I uint32_t *p_reg; /*!< ADxREGx Address. */ - adc_ch_initial_setting_t init; /*!< Initial setting. */ -} adc_ch_t; - -/** - * @} - */ /* End of group ADC_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Exported_functions ADC Exported Functions - * @{ - */ -uint32_t get_conversion_data(uint32_t reg); -TXZ_Result adc_ch_init(adc_ch_t *p_obj); -TXZ_Result adc_ch_deinit(adc_ch_t *p_obj); -TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj); -TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj); -TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value); -/** - * @} - */ /* End of group ADC_Exported_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ADC_CH_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_include.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_include.h deleted file mode 100644 index 011bc2967d4..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/adc_include.h +++ /dev/null @@ -1,349 +0,0 @@ -/** - ******************************************************************************* - * @file adc_include.h - * @brief This file provides internal common definition. - * @version V1.0.0.0 - * $Date:: 2017-09-07 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __ADC_INCLUDE_H -#define __ADC_INCLUDE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -#include "txz_hal.h" - -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @defgroup ADC ADC - * @brief ADC Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/** - * @defgroup NULL_Pointer NULL Pointer - * @brief NULL Pointer. - * @{ - */ -#define ADC_NULL ((void *)0) /*!< NULL Pointer. */ -/** - * @} - */ /* End of group NULL_Pointer */ - -/** - * @defgroup Parameter_Result Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define ADC_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define ADC_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group Parameter_Result */ - -/** - * @defgroup ADxCR0 ADxCR0 - * @brief ADxCR0 Register. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | ADEN | - * | 6-3 | - | - * | 2 | HPSGL | - * | 1 | SGL | - * | 0 | CNT | - * @{ - */ -/* ADEN */ -#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /*!< ADEN :Disable */ -#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /*!< ADEN :Enable */ -/* HPSGL */ -#define ADxCR0_HPSGL_ENABLE ((uint32_t)0x00000004) /*!< HPSGL :Enable */ -/* SGL */ -#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /*!< SGL :Enable */ -/* CNT */ -#define ADxCR0_CNT_MASK ((uint32_t)0x00000001) /*!< CNT :Mask */ -#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /*!< CNT :Disable */ -#define ADxCR0_CNT_ENABLE ((uint32_t)0x00000001) /*!< CNT :Enable */ -/** - * @} - */ /* End of group ADxCR0 */ - -/** - * @defgroup ADxCR1 ADxCR1 - * @brief ADxCR1 Register. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | HPDMEN | - * | 6 | CNTDMEN | - * | 5 | SGLDMEN | - * | 4 | TRGDMEN | - * | 3:2 | - | - * | 1 | HPTRGEN | - * | 0 | TRGEN | - * @{ - */ -/* HPDMEN */ -#define ADxCR1_HPDMEN_DISABLE ((uint32_t)0x00000000) /*!< HPDMEN :Disable */ -#define ADxCR1_HPDMEN_ENABLE ((uint32_t)0x00000080) /*!< HPDMEN :Enable */ -/* CNTDMEN */ -#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /*!< CNTDMEN :Disable */ -#define ADxCR1_CNTDMEN_ENABLE ((uint32_t)0x00000040) /*!< CNTDMEN :Enable */ -/* SGLDMEN */ -#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /*!< SGLDMEN :Disable */ -#define ADxCR1_SGLDMEN_ENABLE ((uint32_t)0x00000020) /*!< SGLDMEN :Enable */ -/* TRGDMEN */ -#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /*!< TRGDMEN :Disable */ -#define ADxCR1_TRGDMEN_ENABLE ((uint32_t)0x00000010) /*!< TRGDMEN :Enable */ -/* HPTRGEN */ -#define ADxCR1_HPTRGEN_DISABLE ((uint32_t)0x00000000) /*!< HPTRGEN :Disable */ -#define ADxCR1_HPTRGEN_ENABLE ((uint32_t)0x00000002) /*!< HPTRGEN :Enable */ -/* TRGEN */ -#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< TRGEN :Disable */ -#define ADxCR1_TRGEN_ENABLE ((uint32_t)0x00000001) /*!< TRGEN :Enable */ -/** - * @} - */ /* End of group ADxCR1 */ - -/** - * @defgroup ADxST ADxST - * @brief ADxST Register. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | ADBF | - * | 6-4 | - | - * | 3 | CNTF | - * | 2 | SNGF | - * | 1 | TRGF | - * | 0 | HPF | - * @{ - */ -/* ADBF */ -#define ADxST_ADBF_MASK ((uint32_t)0x00000080) /*!< ADBF :Mask. */ -#define ADxST_ADBF_IDLE ((uint32_t)0x00000000) /*!< ADBF :Idle. Can stop ADCLK. */ -#define ADxST_ADBF_RUN ((uint32_t)0x00000080) /*!< ADBF :Running. Can't stop ADCLK. */ -/* CNTF */ -#define ADxST_CNTF_MASK ((uint32_t)0x00000008) /*!< CNTF :Mask. */ -#define ADxST_CNTF_IDLE ((uint32_t)0x00000000) /*!< CNTF :Idle. */ -#define ADxST_CNTF_RUN ((uint32_t)0x00000008) /*!< CNTF :Running. */ -/* SNGF */ -#define ADxST_SNGF_MASK ((uint32_t)0x00000004) /*!< SNGF :Mask. */ -#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /*!< SNGF :Idle. */ -#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /*!< SNGF :Running. */ -/* TRGF */ -#define ADxST_TRGF_MASK ((uint32_t)0x00000002) /*!< TRGF :Mask. */ -#define ADxST_TRGF_IDLE ((uint32_t)0x00000000) /*!< TRGF :Idle. */ -#define ADxST_TRGF_RUN ((uint32_t)0x00000002) /*!< TRGF :Running. */ -/* PMDF */ -#define ADxST_HPF_MASK ((uint32_t)0x00000001) /*!< HPF :Mask. */ -#define ADxST_HPF_IDLE ((uint32_t)0x00000000) /*!< HPF :Idle. */ -#define ADxST_HPF_RUN ((uint32_t)0x00000001) /*!< HPF :Running. */ -/** - * @} - */ /* End of group ADxST */ - -/** - * @defgroup ADxMOD0 ADxMOD0. - * @brief ADxMOD0 Register. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-2 | - | - * | 1 | RCUT | - * | 0 | DACON | - * @{ - */ -/* RCUT */ -#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /*!< RCUT :Normal */ -#define ADxMOD0_RCUT_IREF_CUT ((uint32_t)0x00000002) /*!< RCUT :Iref cut */ -/* DACON */ -#define ADxMOD0_DACON_OFF ((uint32_t)0x00000000) /*!< DACON :DAC off */ -#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /*!< DACON :DAC on */ -/** - * @} - */ /* End of group ADxMOD0 */ - -/** - * @name ADxCMPEN Macro Definition. - * @brief ADxCMPEN Register Macro Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-4 | - | - * | 3 | CMP3EN | - * | 2 | CMP2EN | - * | 1 | CMP1EN | - * | 0 | CMP0EN | - * @{ - */ -/* CMP3EN */ -#define ADxCMPEN_CMP3EN_DISABLE ((uint32_t)0x00000000) /*!< CMP3EN :Disable */ -#define ADxCMPEN_CMP3EN_ENABLE ((uint32_t)0x00000008) /*!< CMP3EN :Enable */ -/* CMP2EN */ -#define ADxCMPEN_CMP2EN_DISABLE ((uint32_t)0x00000000) /*!< CMP2EN :Disable */ -#define ADxCMPEN_CMP2EN_ENABLE ((uint32_t)0x00000004) /*!< CMP2EN :Enable */ -/* CMP1EN */ -#define ADxCMPEN_CMP1EN_DISABLE ((uint32_t)0x00000000) /*!< CMP1EN :Disable */ -#define ADxCMPEN_CMP1EN_ENABLE ((uint32_t)0x00000002) /*!< CMP1EN :Enable */ -/* CMP0EN */ -#define ADxCMPEN_CMP0EN_DISABLE ((uint32_t)0x00000000) /*!< CMP0EN :Disable */ -#define ADxCMPEN_CMP0EN_ENABLE ((uint32_t)0x00000001) /*!< CMP0EN :Enable */ -/** - * @} - */ /* End of name ADxCMPEN Macro Definition */ - -/** - * @name ADxTSETn Macro Definition. - * @brief ADxTSETn Register Macro Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | ENINT0 | - * | 6-5 | TRGS0[1:0] | - * | 4-0 | AINST0[4:0]| - * @{ - */ -/* ENINT0 */ -#define ADxTSETn_ENINT_MASK ((uint32_t)0x00000080) /*!< ENINT :Mask */ -#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /*!< ENINT :Disable */ -#define ADxTSETn_ENINT_ENABLE ((uint32_t)0x00000080) /*!< ENINT :Enable */ -/* TRGS0[1:0] */ -#define ADxTSETn_TRGS_DISABLE ((uint32_t)0x00000000) /*!< TRGS :Disable */ -#define ADxTSETn_TRGS_CNT ((uint32_t)0x00000100) /*!< TRGS :Continuation */ -#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000200) /*!< TRGS :Single */ -#define ADxTSETn_TRGS_TRG ((uint32_t)0x00000300) /*!< TRGS :Universal Trigger */ -#define ADxTSETn_TRGS_PRI ((uint32_t)0x00000400) /*!< TRGS :Priority Trigger */ -/** - * @} - */ /* End of name ADxTSETn Macro Definition */ - -/** - * @name ADxREGn Macro Definition. - * @brief ADxREGn Register Macro Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-30 | - | - * | 29 | ADOVRF_Mn | - * | 28 | ADRF_Mn | - * | 27-16 | ADR_Mn[11:0] | - * | 15-4 | ADRn[11:0] | - * | 3-2 | - | - * | 1 | ADOVRFn | - * | 0 | ADRFn | - * @{ - */ -/* ADOVRF_Mn */ -#define ADxREGn_ADOVRF_Mn_MASK ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Mask */ -#define ADxREGn_ADOVRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ -#define ADxREGn_ADOVRF_Mn_ON ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Flag on */ -/* ADRF_Mn */ -#define ADxREGn_ADRF_Mn_MASK ((uint32_t)0x10000000) /*!< ADRF_Mn :Mask */ -#define ADxREGn_ADRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADRF_Mn :Flag off. */ -#define ADxREGn_ADRF_Mn_ON ((uint32_t)0x10000000) /*!< ADRF_Mn :Flag on */ -/* ADR_Mn */ -#define ADxREGn_ADR_Mn_MASK ((uint32_t)0x0FFF0000) /*!< ADR_Mn :Mask */ -/* ADRn */ -#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /*!< ADRn :Mask */ -/* ADOVRFn */ -#define ADxREGn_ADOVRFn_MASK ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Mask */ -#define ADxREGn_ADOVRFn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ -#define ADxREGn_ADOVRFn_ON ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Flag on */ -/* ADRFn */ -#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /*!< ADRFn :Mask */ -#define ADxREGn_ADRFn_OFF ((uint32_t)0x00000000) /*!< ADRFn :Flag off. */ -#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /*!< ADRFn :Flag on */ -/** - * @} - */ /* End of name ADxREGn Macro Definition */ - -/** - * @} - */ /* End of group ADC_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_typedef ADC Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Inline Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_fuctions ADC Private Fuctions - * @{ - */ -/* no define */ -/** - * @} - */ /* End of group ADC_Private_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ADC_INCLUDE_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_fc.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_fc.h deleted file mode 100644 index c9f80b2e027..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_fc.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - ******************************************************************************* - * @file fc.h - * @brief Flash_Userboot Sample Application. - * @version V1.0.0.0 - * $date:: $ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FC_H -#define __FC_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -#if defined(__FC_H) -/** @addtogroup Periph driver - * @{ - */ - -/** @defgroup fc - * @brief fc - * @{ - */ - - -/** @defgroup FlashApi_Exported_Types - * @{ - */ - -/** - * @enum fc_sr0_t - * @brief Enumerated type definition of the FCSR0 register. - */ -typedef enum { - FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */ -} fc_sr0_t; - -/*----------------------------------*/ -/** - * @enum fc_erase_kind_t - * @brief FC Erase Flash Kind structure definenition. -*/ -/*----------------------------------*/ -typedef enum { - FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */ - FC_ERASE_KIND_BLOCK = (0x00000030UL) /*!< Block Erase */ -} fc_erase_kind_t; - -typedef enum { - FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */ - FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */ - FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */ - FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */ - FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */ - FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */ - FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */ - FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */ - FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */ - FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */ - FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */ - FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */ - FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */ - FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */ - FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */ - FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */ - FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */ - FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */ - FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */ - FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */ - FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */ - FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */ - FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */ - FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */ - FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */ - FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */ - FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */ - FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */ - FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */ - FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */ - FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */ - FC_CODE_FLASH_PAGE31 /*!< (0x5E01F000UL), CODE FLASH Page31 */ -} fc_code_flash_page_number_t; - -/** @} */ -/* End of group FlashApi_Exported_Types */ - -/** @defgroup FlashApi_Exported_Constants - * @{ - */ - -//#define FC_RAMADDRESSTOP (0x20000000UL) /*!< RAM Address Top */ -//#define FC_RAMADDRESSEND (0x20003fffUL) /*!< RAM Address End */ -#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */ -//#define FC_CODEFLASHADDRESSEND (0x5E01FFFFUL) /*!< CODE FLASH Address End */ -#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */ -//#define FC_CODEFLASHPAGESIZE (0x1000) /*!< CODE FLASH PAGE SIZE */ -#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */ - -/** @} */ -/* End of group FlashApi_Exported_Constants */ - - - -/** @weakgroup FlashApi_Exported_FunctionPrototypes - * @{ - */ -TXZ_WorkState fc_get_status(fc_sr0_t status); -TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size); -TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages); -TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t lasr_page); -TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr); - -/** @} */ -/* End of group FlashApi_Exported_FunctionPrototypes */ - - -/** @} */ -/* End of group fc */ - -/** @} */ -/* End of group Periph_driver */ - -#endif /* defined(__FC_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __FC_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_rtc.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_rtc.h deleted file mode 100644 index 75380e3e6c7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/tmpm4g9_rtc.h +++ /dev/null @@ -1,386 +0,0 @@ -/** - ******************************************************************************* - * @file bsp_rtc.h - * @brief This file provides all the functions prototypes for RTC Class. - * @version V1.0.0.1 - * $Date:: 2017-09-01 08:26:38 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __BSP_RTC_H -#define __BSP_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -//#include "txz_sample_def.h" -#include "txz_driver_def.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup BSP_UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_define - * @{ - */ - -/** - * @defgroup RTC_RangeSec Range Second - * @brief Range of Second. - * @brief Range of Second "(RTC_RANGE_SEC_MIN <= Value <= RTC_RANGE_SEC_MAX)". - * @{ - */ -#define RTC_RANGE_SEC_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 sec */ -#define RTC_RANGE_SEC_MAX ((uint8_t)0x3B) /*!< Maximum Value :59 sec */ -/** - * @} - */ /* End of group RTC_RangeSec */ - -/** - * @defgroup RTC_RangeMin Range Minute - * @brief Range of Minute. - * @brief Range of Minute "(RTC_RANGE_MIN_MIN <= Value <= RTC_RANGE_MIN_MAX)". - * @{ - */ -#define RTC_RANGE_MIN_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 min */ -#define RTC_RANGE_MIN_MAX ((uint8_t)0x3B) /*!< Maximum Value :59 min */ -/** - * @} - */ /* End of group RTC_RangeMin */ - -/** - * @defgroup RTC_AlarmMin Alarm Minute - * @brief Compare/No Compare minute. - * @{ - */ -#define RTC_ALARM_MIN_OFF ((uint8_t)0x7F) /*!< No compare. */ -#define RTC_ALARM_MIN_ON ((uint8_t)0x00) /*!< Compare. */ -/** - * @} - */ /* End of group RTC_AlarmMin */ - -/** - * @defgroup RTC_Range24Hour Range 24 Hour - * @brief Range of 24 Hour. - * @brief Range of 24 Hour "(RTC_RANGE_24_HOUR_MIN <= Value <= RTC_RANGE_24_HOUR_MAX)". - * @{ - */ -#define RTC_RANGE_24_HOUR_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 hour */ -#define RTC_RANGE_24_HOUR_MAX ((uint8_t)0x17) /*!< Maximum Value :23 hour */ -/** - * @} - */ /* End of group RTC_Range24Hour */ - -/** - * @defgroup RTC_Range12Hour Range 12 Hour - * @brief Range of 12 Hour. - * @brief Range of 12 Hour "(RTC_RANGE_12_HOUR_MIN <= Value <= RTC_RANGE_12_HOUR_MAX)". - * @{ - */ -#define RTC_RANGE_12_HOUR_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 hour */ -#define RTC_RANGE_12_HOUR_MAX ((uint8_t)0x0B) /*!< Maximum Value :11 hour */ -/** - * @} - */ /* End of group RTC_Range12Hour */ - -/** - * @defgroup RTC_Meridiem Meridiem - * @brief AM/PM. - * @{ - */ -#define RTC_MERIDIEM_AM ((uint8_t)0x00) /*!< A.M. */ -#define RTC_MERIDIEM_PM ((uint8_t)0x20) /*!< P.M. */ -/** - * @} - */ /* End of group RTC_Meridiem */ - -/** - * @defgroup RTC_AlarmHour Alarm Hour - * @brief Compare/No Compare hour. - * @{ - */ -#define RTC_ALARM_HOUR_OFF ((uint8_t)0x3F) /*!< No compare. */ -#define RTC_ALARM_HOUR_ON ((uint8_t)0x00) /*!< Compare. */ -/** - * @} - */ /* End of group RTC_AlarmHour */ - -/** - * @defgroup RTC_Day Day Of Week - * @brief Day of week. - * @{ - */ -#define RTC_DAY_SUNDAY ((uint8_t)0x00) /*!< Sunday. */ -#define RTC_DAY_MONDAY ((uint8_t)0x01) /*!< Monday. */ -#define RTC_DAY_TUESDAY ((uint8_t)0x02) /*!< Tuesday. */ -#define RTC_DAY_WEDNESDAY ((uint8_t)0x03) /*!< Wednesday. */ -#define RTC_DAY_THURSDAY ((uint8_t)0x04) /*!< Thursday. */ -#define RTC_DAY_FRIDAY ((uint8_t)0x05) /*!< Friday. */ -#define RTC_DAY_SATURDAY ((uint8_t)0x06) /*!< Saturday. */ -/** - * @} - */ /* End of group RTC_Day */ - -/** - * @defgroup RTC_AlarmDay Alarm Day - * @brief Compare/No Compare day. - * @{ - */ -#define RTC_ALARM_DAY_OFF ((uint8_t)0x03) /*!< No compare. */ -#define RTC_ALARM_DAY_ON ((uint8_t)0x00) /*!< Compare. */ -/** - * @} - */ /* End of group RTC_AlarmDay */ - -/** - * @defgroup RTC_RangeDate Range Date - * @brief Range of Date. - * @brief Range of Date "(RTC_RANGE_DATE_MIN <= Value <= RTC_RANGE_DATE_MAX)". - * @{ - */ -#define RTC_RANGE_DATE_MIN ((uint8_t)0x00) /*!< Minimum Value :date 00 */ -#define RTC_RANGE_DATE_MAX ((uint8_t)0x1F) /*!< Maximum Value :date 31 */ -/** - * @} - */ /* End of group RTC_RangeDate */ - -/** - * @defgroup RTC_AlarmDate Alarm Date - * @brief Compare/No Compare date. - * @{ - */ -#define RTC_ALARM_DATE_OFF ((uint8_t)0x3F) /*!< No compare. */ -#define RTC_ALARM_DATE_ON ((uint8_t)0x00) /*!< Compare. */ -/** - * @} - */ /* End of group RTC_AlarmDate */ - -/** - * @defgroup RTC_Month Month - * @brief Month. - * @{ - */ -#define RTC_MONTH_JAN ((uint8_t)0x01) /*!< January. */ -#define RTC_MONTH_FEB ((uint8_t)0x02) /*!< February. */ -#define RTC_MONTH_MAR ((uint8_t)0x03) /*!< March. */ -#define RTC_MONTH_APR ((uint8_t)0x04) /*!< April. */ -#define RTC_MONTH_MAY ((uint8_t)0x05) /*!< May. */ -#define RTC_MONTH_JUN ((uint8_t)0x06) /*!< June. */ -#define RTC_MONTH_JUL ((uint8_t)0x07) /*!< July. */ -#define RTC_MONTH_AUG ((uint8_t)0x08) /*!< August. */ -#define RTC_MONTH_SEP ((uint8_t)0x09) /*!< September. */ -#define RTC_MONTH_OCT ((uint8_t)0x10) /*!< October. */ -#define RTC_MONTH_NOV ((uint8_t)0x11) /*!< November. */ -#define RTC_MONTH_DEC ((uint8_t)0x12) /*!< December. */ -/** - * @} - */ /* End of group RTC_Month */ - -/** - * @defgroup BSP_RTC_HourNotation Hour Notation - * @brief 24/12 Hour Notation. - * @{ - */ -#define RTC_HOUR_NOTATION_12 ((uint8_t)0x00) /*!< 12-hour notation. */ -#define RTC_HOUR_NOTATION_24 ((uint8_t)0x01) /*!< 24-hour notation. */ -/** - * @} - */ /* End of group BSP_RTC_HourNotation */ - -/** - * @defgroup RTC_RangeYear Range Year - * @brief Range of Year. - * @brief Range of Year "(RTC_RANGE_YEAR_MIN <= Value <= RTC_RANGE_YEAR_MAX)". - * @{ - */ -#define RTC_RANGE_YEAR_MIN ((uint8_t)0x00) /*!< Minimum Value :year 00 */ -#define RTC_RANGE_YEAR_MAX ((uint8_t)0x63) /*!< Maximum Value :year 99 */ -/** - * @} - */ /* End of group RTC_RangeYear */ - -/** - * @defgroup RTC_LeapYear Leap Year - * @brief Leap Year. - * @{ - */ -#define RTC_LEAP_YEAR_0 ((uint8_t)0x00) /*!< Leap year. */ -#define RTC_LEAP_YEAR_1 ((uint8_t)0x01) /*!< 1 year since leap year. */ -#define RTC_LEAP_YEAR_2 ((uint8_t)0x02) /*!< 2 years since leap year. */ -#define RTC_LEAP_YEAR_3 ((uint8_t)0x03) /*!< 3 years since leap year. */ -/** - * @} - */ /* End of group RTC_LeapYear */ - -/** - * @defgroup RTC_IntSource Interrupt Source Signal - * @brief Interrupt Source Signal. - * @{ - */ -#define RTC_INT_SRC_1HZ ((uint8_t)0x47) /*!< 1 Hz. */ -#define RTC_INT_SRC_2HZ ((uint8_t)0xC3) /*!< 2 Hz. */ -#define RTC_INT_SRC_4HZ ((uint8_t)0xC5) /*!< 4 Hz. */ -#define RTC_INT_SRC_8HZ ((uint8_t)0x01) /*!< 8 Hz. */ -#define RTC_INT_SRC_16HZ ((uint8_t)0xC6) /*!< 16 Hz. */ -#define RTC_INT_SRC_ALARM ((uint8_t)0xC7) /*!< Alarm. */ -/** - * @} - */ /* End of group RTC_IntSource */ - -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup BSP_UTILITIES_Exported_typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief RTC handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct uart_handle -{ - TSB_RTC_TypeDef *p_instance; /*!< Registers base address. */ -} rtc_t; -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup BSP_UTILITIES_Exported_functions - * @{ - */ -TXZ_Result m4g9_rtc_init(rtc_t *p_obj); -TXZ_Result rtc_deinit(rtc_t *p_obj); -TXZ_Result rtc_enable_int(rtc_t *p_obj); -TXZ_Result rtc_disable_int(rtc_t *p_obj); -TXZ_Result rtc_set_int_source(rtc_t *p_obj, uint8_t src); -TXZ_Result rtc_set_hour_notation(rtc_t *p_obj, uint8_t notation); -TXZ_Result rtc_get_hour_notation(rtc_t *p_obj, uint8_t *p_notation); -/* clock */ -TXZ_Result rtc_clock_enable(rtc_t *p_obj); -TXZ_Result rtc_clock_disable(rtc_t *p_obj); -TXZ_Result rtc_clock_reset_counter(rtc_t *p_obj); -TXZ_Result rtc_clock_set_sec(rtc_t *p_obj, uint8_t sec); -TXZ_Result rtc_clock_get_sec(rtc_t *p_obj, uint8_t *p_sec); -TXZ_Result rtc_clock_set_min(rtc_t *p_obj, uint8_t min); -TXZ_Result rtc_clock_get_min(rtc_t *p_obj, uint8_t *p_min); -TXZ_Result rtc_clock_set_hour_24(rtc_t *p_obj, uint8_t hour); -TXZ_Result rtc_clock_get_hour_24(rtc_t *p_obj, uint8_t *p_hour); -TXZ_Result rtc_clock_set_hour_12(rtc_t *p_obj, uint8_t meridiem, uint8_t hour); -TXZ_Result rtc_clock_get_hour_12(rtc_t *p_obj, uint8_t *p_meridiem, uint8_t *p_hour); -TXZ_Result rtc_clock_set_day(rtc_t *p_obj, uint8_t day); -TXZ_Result rtc_clock_get_day(rtc_t *p_obj, uint8_t *p_day); -TXZ_Result rtc_clock_set_date(rtc_t *p_obj, uint8_t date); -TXZ_Result rtc_clock_get_date(rtc_t *p_obj, uint8_t *p_date); -TXZ_Result rtc_clock_set_month(rtc_t *p_obj, uint8_t month); -TXZ_Result rtc_clock_get_month(rtc_t *p_obj, uint8_t *p_month); -TXZ_Result rtc_clock_set_year(rtc_t *p_obj, uint8_t year); -TXZ_Result rtc_clock_get_year(rtc_t *p_obj, uint8_t *p_year); -TXZ_Result rtc_clock_set_leap(rtc_t *p_obj, uint8_t leap); -TXZ_Result rtc_clock_get_leap(rtc_t *p_obj, uint8_t *p_leap); -/* alarm */ -TXZ_Result rtc_alarm_enable(rtc_t *p_obj); -TXZ_Result rtc_alarm_disable(rtc_t *p_obj); -TXZ_Result rtc_alarm_reset(rtc_t *p_obj); -TXZ_Result rtc_alarm_set_min(rtc_t *p_obj, uint8_t compare, uint8_t min); -TXZ_Result rtc_alarm_get_min(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_min); -TXZ_Result rtc_alarm_set_hour_24(rtc_t *p_obj, uint8_t compare, uint8_t hour); -TXZ_Result rtc_alarm_get_hour_24(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_hour); -TXZ_Result rtc_alarm_set_hour_12(rtc_t *p_obj, uint8_t compare, uint8_t meridiem, uint8_t hour); -TXZ_Result rtc_alarm_get_hour_12(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_meridiem, uint8_t *p_hour); -TXZ_Result rtc_alarm_set_day(rtc_t *p_obj, uint8_t compare, uint8_t day); -TXZ_Result rtc_alarm_get_day(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_day); -TXZ_Result rtc_alarm_set_date(rtc_t *p_obj, uint8_t compare, uint8_t date); -TXZ_Result rtc_alarm_get_date(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_date); -/** - * @} - */ /* End of group BSP_UTILITIES_Exported_functions */ - -/** - * @} - */ /* End of group BSP_UTILITIES */ - -/** - * @} - */ /* End of group Sample_Appli */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __BSP_RTC_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_cg.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_cg.h deleted file mode 100644 index 4244e9fa7f3..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_cg.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - ******************************************************************************* - * @file txz_cg.h - * @brief This file provides all the functions prototypes for CG driver. - * @version V1.0.0.0 - * $Date:: 2018-04-02 19:31:41 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __CG_H -#define __CG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup CG CG - * @brief CG Driver. - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup CG_Exported_define CG Exported Define - * @{ - */ -/* no define */ -/** - * @} - */ /* End of group CG_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup CG_Exported_define CG Exported Define - * @{ - */ -/* no define */ -/** - * @} - */ /* End of group CG_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup CG_Exported_typedef CG Exported Typedef - * @{ - */ -/** - * @brief CG member. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_CG_TypeDef *p_instance; /*!< Registers base address. */ -} cg_t; - -/** - * @} - */ /* End of group CG_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup CG_Exported_functions CG Exported Functions - * @{ - */ -uint32_t cg_get_fsysm(cg_t *p_obj); -uint32_t cg_get_phyt0(cg_t *p_obj); -uint32_t cg_get_mphyt0(cg_t *p_obj); -TXZ_Result cg_ihosc_enable(cg_t *p_obj); -TXZ_Result cg_ihosc_disable(cg_t *p_obj); -/** - * @} - */ /* End of group CG_Exported_functions */ - -/** - * @} - */ /* End of group CG */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __CG_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_driver_def.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_driver_def.h deleted file mode 100644 index 61fbc050717..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_driver_def.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - ******************************************************************************* - * @file txz_driver_def.h - * @brief All common macro and definition for TXZ peripheral drivers - * @version V1.0.0.0 - * $Date:: 2017-07-21 15:39:36 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TXZ_DRIVER_DEF_H -#define __TXZ_DRIVER_DEF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF - * @brief All common macro and definition for TXZ peripheral drivers - * @{ - */ - -/** @defgroup Device_Header_Included Device Header Included - * @brief Include the Device header file of a Target. - * @{ - */ -#include "TMPM4G9.h" /*!< TMPM4Gx Group Header file. */ -/** - * @} - */ /* End of group Device_Header */ - - -/** @defgroup TXZ_Exported_typedef TXZ Exported typedef - * @{ - */ -typedef enum { - TXZ_SUCCESS = 0U, - TXZ_ERROR = 1U -} TXZ_Result; - -typedef enum { - TXZ_BUSY = 0U, - TXZ_DONE = 1U -} TXZ_WorkState; - -typedef enum { - TXZ_DISABLE = 0U, - TXZ_ENABLE = 1U -} TXZ_FunctionalState; -/** - * @} - */ /* End of group TXZ_Exported_typedef */ - -/** @defgroup TXZ_Exported_macro TXZ Exported macro - * @{ - */ -#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) - -/** - * @brief To report the name of the source file and source line number where the - * assert_param error has occurred, "DEBUG" must be defined. And detailed - * definition of assert_failed() is needed to be implemented, which can be - * done, for example, in the main.c file. - */ -#ifdef DEBUG -void assert_failed(char *file, int32_t line); -#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) -#else -#define assert_param(expr) -#endif /* DEBUG */ -/** - * @} - */ /* End of group TXZ_Exported_macro */ - -/** - * @} - */ /* End of group Periph_Driver */ - -/** - * @} - */ /* End of group TXZ_DRIVER_DEF */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart.h deleted file mode 100644 index 4cd694b17e0..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart.h - * @brief This file provides all the functions prototypes for FUART driver. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __FUART_H -#define __FUART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup FUART FUART - * @brief FUART Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Exported_define FUART Exported Define - * @{ - */ - -/** - * @defgroup FUART_FifoMax Max Num of FIFO - * @brief Max Num of Tx/Rx Fifo. - * @{ - */ -#define FUART_TX_FIFO_MAX ((uint32_t)0x00000020) /*!< TX FIFO Max. */ -#define FUART_RX_FIFO_MAX ((uint32_t)0x00000020) /*!< RX FIFO Max. */ -/** - * @} - */ /* End of group UART_FifoMax */ - -/** - * @defgroup FUART_CTSHandshake CTS Handshake - * @brief Available CTS Handshake Macro Definisiton. - * @{ - */ -#define FUART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define FUART_CTS_ENABLE ((uint32_t)0x00008000) /*!< Available. */ -/** - * @} - */ /* End of group FUART_CTSHandshake */ - - -/** - * @defgroup FUART_RTSHandshake RTS Handshake - * @brief Available RTS Handshake Macro Definisiton. - * @{ - */ -#define FUART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define FUART_RTS_ENABLE ((uint32_t)0x00004000) /*!< Available. */ -/** - * @} - */ /* End of group FUART_RTSHandshake */ - -/** - * @defgroup FUART_FIFO FIFO Enable - * @brief FIFO Enable Bit Macro Definisiton. - * @{ - */ -#define FUART_FIFO_DISABLE ((uint32_t)0x00000000) /*!< Disable. */ -#define FUART_FIFO_ENABLE ((uint32_t)0x00000010) /*!< Enable. */ -/** - * @} - */ /* End of group FUART_FIFO */ - - -/** - * @defgroup FUART_StopBit Stop Bit - * @brief Stop Bit Macro Definisiton. - * @{ - */ -#define FUART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ -#define FUART_STOP_BIT_2 ((uint32_t)0x00000008) /*!< 2 bit */ -/** - * @} - */ /* End of group FUART_StopBit */ - - -/** - * @defgroup FUART_ParityBit Parity Bit - * @brief Parity Bit Macro Definisiton. - * @{ - */ -#define FUART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ -#define FUART_PARITY_BIT_EVEN ((uint32_t)0x00000004) /*!< Even Parity */ -/** - * @} - */ /* End of group FUART_ParityBit */ - - -/** - * @defgroup FUART_ParityEnable Parity Enable - * @brief Enable/Disable Parity Macro Definisiton. - * @{ - */ -#define FUART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group FUART_ParityEnable */ - -/** - * @defgroup FUART_StaticParityEnable Static Parity Enable - * @brief Enable/Disable Static Parity Macro Definisiton. - * @{ - */ -#define FUART_STATIC_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_STATIC_PARITY_ENABLE ((uint32_t)0x00000080) /*!< Enable */ -/** - * @} - */ /* End of group FUART_ParityEnable */ - -/** - * @defgroup FUART_DataLength Data Length - * @brief Data Length Macro Definisiton. - * @{ - */ -#define FUART_DATA_LENGTH_5 ((uint32_t)0x00000000) /*!< 5 bit */ -#define FUART_DATA_LENGTH_6 ((uint32_t)0x00000020) /*!< 6 bit */ -#define FUART_DATA_LENGTH_7 ((uint32_t)0x00000040) /*!< 7 bit */ -#define FUART_DATA_LENGTH_8 ((uint32_t)0x00000060) /*!< 8 bit */ -/** - * @} - */ /* End of group FUART_DataLength */ - -/** - * @defgroup FUART_FIFO_Level FIFO Level - * @brief FIFO Level Macro Definisiton. - * @{ - */ -#define FUART_FIFO_LEVEL_4 ((uint32_t)0x00000000) /*!< 4 level */ -#define FUART_FIFO_LEVEL_8 ((uint32_t)0x00000001) /*!< 8 level */ -#define FUART_FIFO_LEVEL_16 ((uint32_t)0x00000002) /*!< 16 level */ -#define FUART_FIFO_LEVEL_24 ((uint32_t)0x00000003) /*!< 24 level */ -#define FUART_FIFO_LEVEL_28 ((uint32_t)0x00000004) /*!< 28 level */ - -/** - * @} - */ /* End of group FUART_DataLength */ - -/** - * @defgroup FUART_TxInterrupt Tx Interrpt - * @brief Available Transmit Interrupt Macro Definisiton. - * @{ - */ -#define FUART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define FUART_TX_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ -/** - * @} - */ /* End of group FUART_TxInterrupt */ - - -/** - * @defgroup FUART_RxInterrupt Rx Interrpt - * @brief Available Receive Interrupt Macro Definisiton. - * @{ - */ -#define FUART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define FUART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ -/** - * @} - */ /* End of group FUART_RxInterrupt */ - - -/** - * @defgroup FUART_ErrorInterrupt Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -/** - * @defgroup FUART_OVER_RUN_ErrorInterrupt Over Run Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_OV_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_OV_ERR_INT_ENABLE ((uint32_t)0x00000400) /*!< Enable */ -/** - * @} - */ /* End of group FUART_OVER_RUN_ErrorInterrupt */ - -/** - * @defgroup FUART_BREAK_ErrorInterrupt Break Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_BK_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_BK_ERR_INT_ENABLE ((uint32_t)0x00000200) /*!< Enable */ -/** - * @} - */ /* End of group FUART_BREAK_ErrorInterrupt */ - -/** - * @defgroup FUART_PARITY_ErrorInterrupt Parity Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_PA_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_PA_ERR_INT_ENABLE ((uint32_t)0x00000100) /*!< Enable */ -/** - * @} - */ /* End of group FUART_PARITY_ErrorInterrupt */ - -/** - * @defgroup FUART_FRAMING_ErrorInterrupt Framing Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_FR_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_FR_ERR_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ -/** - * @} - */ /* End of group FUART_FRAMING_ErrorInterrupt */ - -/** - * @defgroup FUART_RX_TIMEOUT_ErrorInterrupt Rx Timeout Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define FUART_TO_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define FUART_TO_ERR_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ -/** - * @} - */ /* End of group FUART_RX_TIMEOUT_RUN_ErrorInterrupt */ -/** - * @} - */ /* End of group FUART_ErrorInterrupt */ - - -/** - * @defgroup FUART_RangeK Range K - * @brief Range of K Macro Definisiton. - * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= FUART_RANGE_K_MAX)". - * @{ - */ -#define FUART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ -#define FUART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ -/** - * @} - */ /* End of group FUART_RangeK */ - - -/** - * @defgroup FUART_RangeN Range N - * @brief Range of N Macro Definisiton. - * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= FUART_RANGE_N_MAX)". - * @{ - */ -#define FUART_RANGE_N_MIN ((uint32_t)0x00000002) /*!< Minimum Value :N=2 */ -#define FUART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ -/** - * @} - */ /* End of group FUART_RangeN */ - - -/** - * @defgroup FUART_OverrunErr Overrun Error - * @brief Overrun Error Macro Definisiton. - * @{ - */ -#define FUART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define FUART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ -/** - * @} - */ /* End of group FUART_OverrunErr */ - - -/** - * @defgroup FUART_BreakErr Break Error - * @brief Break Error Macro Definisiton. - * @{ - */ -#define FUART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define FUART_BREAK_ERR ((uint32_t)0x00000004) /*!< Error */ -/** - * @} - */ /* End of group FUART_BreakErr */ - - -/** - * @defgroup FUART_ParityErr Parity Error - * @brief Parity Error Macro Definisiton. - * @{ - */ -#define FUART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define FUART_PARITY_ERR ((uint32_t)0x00000002) /*!< Error */ -/** - * @} - */ /* End of group FUART_ParityErr */ - - -/** - * @defgroup FUART_FramingErr Framing Error - * @brief Framing Error Macro Definisiton. - * @{ - */ -#define FUART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define FUART_FRAMING_ERR ((uint32_t)0x00000001) /*!< Error */ -/** - * @} - */ /* End of group FUART_FramingErr */ - -/** - * @defgroup FUARTxFR FUARTxFR Register - * @brief FUARTxFR Register Definition. - * @{ - */ -/* FR */ -#define FUARTxFR_TXFE_MASK ((uint32_t)0x00000080) /*!< TXFE :Mask */ -#define FUARTxFR_RXFF_MASK ((uint32_t)0x00000040) /*!< RXFF :Mask */ -#define FUARTxFR_TXFF_MASK ((uint32_t)0x00000020) /*!< TXFF :Mask */ -#define FUARTxFR_RXFE_MASK ((uint32_t)0x00000010) /*!< RXFE :Mask */ -#define FUARTxFR_BUSY_MASK ((uint32_t)0x00000008) /*!< BUSY :Mask */ -#define FUARTxFR_CTS_MASK ((uint32_t)0x00000001) /*!< CTS :Mask */ - -#define FUARTxFR_TXFE_FLAG_SET ((uint32_t)0x00000080) /*!< TXFE :Flag Set */ -#define FUARTxFR_RXFF_FLAG_SET ((uint32_t)0x00000040) /*!< RXFF :Flag Set */ -#define FUARTxFR_TXFF_FLAG_SET ((uint32_t)0x00000020) /*!< TXFF :Flag Set */ -#define FUARTxFR_RXFE_FLAG_SET ((uint32_t)0x00000010) /*!< RXFE :Flag Set */ -#define FUARTxFR_BUSY_FLAG_SET ((uint32_t)0x00000008) /*!< BUSY :Flag Set */ -#define FUARTxFR_CTS_FLAG_SET ((uint32_t)0x00000001) /*!< CTS :Flag Set */ - -#define FUARTxFR_TXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFE :Flag Clear */ -#define FUARTxFR_RXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFF :Flag Clear */ -#define FUARTxFR_TXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFF :Flag Clear */ -#define FUARTxFR_RXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFE :Flag Clear */ -#define FUARTxFR_BUSY_FLAG_CLR ((uint32_t)0x00000000) /*!< BUSY :Flag Clear */ -#define FUARTxFR_CTS_FLAG_CLR ((uint32_t)0x00000000) /*!< CTS :Flag Clear */ -/** - * @} - */ /* End of group FUARTxFR */ - -/** - * @} - */ /* End of group FUART_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Exported_define FUART Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Exported_typedef FUART Exported Typedef - * @{ - */ - -/*----------------------------------*/ -/** - * @brief Receive event information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} fuart_receive_t; - -/*----------------------------------*/ -/** - * @brief Transmit data information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} fuart_transmit_t; - -/*----------------------------------*/ -/** - * @brief Boudrate setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t brk; /*!< Division Value K. - : K Range ( FUART_RANGE_K_MIN <= K =< FUART_RANGE_K_MAX ) @ref FUART_RangeK */ - uint32_t brn; /*!< Division Value N. - : N Range ( FUART_RANGE_N_MIN <= N =< FUART_RANGE_N_MAX ) @ref FUART_RangeN */ -} fuart_boudrate_t; - -/*----------------------------------*/ -/** - * @brief Transmit FIFO setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t inttx; /*!< Available Transmit Interrupt. - : Use @ref FUART_TxInterrupt */ - uint32_t level; /*!< Transmit Fill Level. - : Use @ref FUART_FIFO_Level */ -} fuart_tx_int_t; - -/*----------------------------------*/ -/** - * @brief Receive FIFO setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t intrx; /*!< Available Receive Interrupt. - : Use @ref FUART_RxInterrupt */ - uint32_t level; /*!< Receive Fill Level. - : Use @ref FUART_FIFO_Level */ -} fuart_rx_int_t; - -/*----------------------------------*/ -/** - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - fuart_boudrate_t boudrate; /*!< Boudrate setting. - : Use @ref fuart_boudrate_t */ - uint32_t interr; /*!< Available Error Interrupt. - : Use @ref FUART_ErrorInterrupt */ - fuart_tx_int_t tx_int; /*!< Transmit Interrupt setting. - : Use @ref fuart_tx_int_t */ - fuart_rx_int_t rx_int; /*!< Receive Interrupt setting. - : Use @ref fuart_rx_int_t */ - uint32_t ctse; /*!< Available CTS Handshake. - : Use @ref FUART_CTSHandshake */ - uint32_t rtse; /*!< Available RTS Handshake. - : Use @ref FUART_RTSHandshake */ - uint32_t stpa; /*!< Enable/Disable Static Parity. - : Use @ref FUART_StaticParityEnable */ - uint32_t sm; /*!< Data Length. - : Use @ref FUART_DataLength */ - uint32_t fifo; /*!< Available FIFO. - : Use @ref FUART_FIFO */ - uint32_t sblen; /*!< Stop Bit. - : Use @ref FUART_StopBit */ - uint32_t even; /*!< Odd/Even Parity Bit. - : Use @ref FUART_ParityBit */ - uint32_t pe; /*!< Enable/Disable Parity Bit. - : Use @ref FUART_ParityEnable */ -} fuart_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief FUART handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_FURT_TypeDef *p_instance; /*!< Registers base address. */ - fuart_initial_setting_t init; /*!< Initial setting. */ - /*------------------------------------------*/ - /*! - @brief Transmit Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t rp; /*!< Num of transmited data. */ - fuart_transmit_t info; /*!< Transmit Data Information. */ - void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ - } transmit; - /*------------------------------------------*/ - /*! - @brief Receive Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t wp; /*!< Num of received data. */ - fuart_receive_t info; /*!< Receive Data Information. */ - void (*handler)(uint32_t id, TXZ_Result result, fuart_receive_t *p_info); /*!< Receive Event handler. */ - } receive; -} fuart_t; - -/** - * @} - */ /* End of group FUART_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Exported_functions FUART Exported Functions - * @{ - */ -TXZ_Result fuart_init(fuart_t *p_obj); -TXZ_Result fuart_deinit(fuart_t *p_obj); -TXZ_Result fuart_discard_transmit(fuart_t *p_obj); -TXZ_Result fuart_discard_receive(fuart_t *p_obj); -TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info); -TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info); -void fuart_transmit_irq_handler(fuart_t *p_obj); -void fuart_receive_irq_handler(fuart_t *p_obj); -void fuart_error_irq_handler(fuart_t *p_obj); -void fuart_irq_handler(fuart_t *p_obj); -TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status); -TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error); -TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_setting); -/** - * @} - */ /* End of group FUART_Exported_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __UART_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_ex.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_ex.h deleted file mode 100644 index 674772d8322..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_ex.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart_ex.h - * @brief This file provides all the functions prototypes for FUART driver. - * @brief Extended functionality. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __FUART_EX_H -#define __FUART_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -#include "txz_fuart.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup FUART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Exported_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_functions - * @{ - */ -TXZ_Result fuart_send_break(fuart_t *p_obj); -TXZ_Result fuart_stop_break(fuart_t *p_obj); -/** - * @} - */ /* End of group FUART_Exported_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __FUART_EX_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_include.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_include.h deleted file mode 100644 index f94dc388510..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_fuart_include.h +++ /dev/null @@ -1,390 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart_include.h - * @brief This file provides internal common definition. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __FUART_INCLUDE_H -#define __FUART_INCLUDE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup FUART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/** - * @defgroup FUART_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define FUART_NULL ((void *)0) /*!< Null Pointer. */ -/** - * @} - */ /* End of group FUART_NullPointer */ - -/** - * @defgroup FUART_ParameterResult Parameter Check Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define FUART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define FUART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group FUART_ParameterResult */ - -/** - * @defgroup FUARTxDR FUARTxDR Register - * @brief FUARTxDR Register Definition. - * @{ - */ -/* DR */ -#define FUARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ -/** - * @} - */ /* End of group FUARTxDR */ - -/** - * @defgroup FUARTxCR FUARTxCR Register - * @brief FUARTxCR Register Definition. - * @{ - */ -#define FUARTxCR_CTSEN_MASK ((uint32_t)0x00008000) /*!< CTSEN :MASK. */ -#define FUARTxCR_RTSEN_MASK ((uint32_t)0x00004000) /*!< RTSEN :MASK. */ -#define FUARTxCR_RXE_MASK ((uint32_t)0x00000200) /*!< RXE :MASK. */ -#define FUARTxCR_TXE_MASK ((uint32_t)0x00000100) /*!< TXE :MASK. */ -#define FUARTxCR_UARTEN_MSK ((uint32_t)0x00000001) /*!< UARTEN :MASK. */ - -#define FUARTxCR_CTSEN_DISABLE ((uint32_t)0x00000000) /*!< CTSEN :Not Available. */ -#define FUARTxCR_RTSEN_DISABLE ((uint32_t)0x00000000) /*!< RTSEN :Not Available. */ -#define FUARTxCR_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable. */ -#define FUARTxCR_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable. */ -#define FUARTxCR_UARTEN_DISABLE ((uint32_t)0x00000000) /*!< UARTEN :Disable. */ - -#define FUARTxCR_CTSEN_ENABLE ((uint32_t)0x00008000) /*!< CTSEN :Available. */ -#define FUARTxCR_RTSEN_ENABLE ((uint32_t)0x00004000) /*!< RTSEN :Available. */ -#define FUARTxCR_RXE_ENABLE ((uint32_t)0x00000200) /*!< RXE :Enable. */ -#define FUARTxCR_TXE_ENABLE ((uint32_t)0x00000100) /*!< TXE :Enable. */ -#define FUARTxCR_UARTEN_ENABLE ((uint32_t)0x00000001) /*!< UARTEN :Enable. */ -/** - * @} - */ /* End of group FUARTxRSR */ - -/** - * @defgroup FUARTxRSR FUARTxRSR Register - * @brief FUARTxRSR Register Definition. - * @{ - */ -#define FUARTxRSR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ -#define FUARTxRSR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ -#define FUARTxRSR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ -#define FUARTxRSR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ - -#define FUARTxRSR_OE_ERR ((uint32_t)0x00000008) /*!< OE :Error */ -#define FUARTxRSR_BE_ERR ((uint32_t)0x00000004) /*!< BE :Error */ -#define FUARTxRSR_PE_ERR ((uint32_t)0x00000002) /*!< PE :Error */ -#define FUARTxRSR_FE_ERR ((uint32_t)0x00000001) /*!< FE :Error */ -/** - * @} - */ /* End of group FUARTxRSR */ - -/** - * @defgroup FUARTxECR FUARTxECR Register - * @brief FUARTxECR Register Definition. - * @{ - */ -/* ECR */ -#define FUARTxECR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ -#define FUARTxECR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ -#define FUARTxECR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ -#define FUARTxECR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ - -#define FUARTxECR_OE_CLR ((uint32_t)0x00000008) /*!< OE :Clear */ -#define FUARTxECR_BE_CLR ((uint32_t)0x00000004) /*!< BE :Clear */ -#define FUARTxECR_PE_CLR ((uint32_t)0x00000002) /*!< PE :Clear */ -#define FUARTxECR_FE_CLR ((uint32_t)0x00000001) /*!< FE :Clear */ - -/** - * @} - */ /* End of group FUARTxECR */ - -/** - * @defgroup FUARTxLCR_H FUARTxRSR Register - * @brief FUARTxLCR_H Register Definition. - * @{ - */ -#define FUARTxLCR_H_BRK_MASK ((uint32_t)0x00000001) /*!< BRK :Mask */ - -#define FUARTxLCR_H_BRK_SEND ((uint32_t)0x00000001) /*!< BRK :Send */ -#define FUARTxLCR_H_BRK_STOP ((uint32_t)0x00000000) /*!< BRK :Stop */ -/** - * @} - */ /* End of group FUARTxLCR_H */ - -/** - * @defgroup FUARTxRIS FUARTxRIS Register - * @brief FUARTxRIS Register Definition. - * @{ - */ -#define FUARTxRIS_OERIS_MASK ((uint32_t)0x00000400) /*!< OERIS :Mask */ -#define FUARTxRIS_BERIS_MASK ((uint32_t)0x00000200) /*!< BERIS :Mask */ -#define FUARTxRIS_PERIS_MASK ((uint32_t)0x00000100) /*!< PRRIS :Mask */ -#define FUARTxRIS_FERIS_MASK ((uint32_t)0x00000080) /*!< FERIS :Mask */ -#define FUARTxRIS_RTRIS_MASK ((uint32_t)0x00000040) /*!< RTRIS :Mask */ -#define FUARTxRIS_TXRIS_MASK ((uint32_t)0x00000020) /*!< TXRIS :Mask */ -#define FUARTxRIS_RXRIS_MASK ((uint32_t)0x00000010) /*!< RXRIS :Mask */ - -#define FUARTxRIS_OERIS_REQ ((uint32_t)0x00000400) /*!< OERIS :Request */ -#define FUARTxRIS_BERIS_REQ ((uint32_t)0x00000200) /*!< BERIS :Request */ -#define FUARTxRIS_PERIS_REQ ((uint32_t)0x00000100) /*!< PRRIS :Request */ -#define FUARTxRIS_FERIS_REQ ((uint32_t)0x00000080) /*!< FERIS :Request */ -#define FUARTxRIS_RTRIS_REQ ((uint32_t)0x00000040) /*!< RTRIS :Request */ -#define FUARTxRIS_TXRIS_REQ ((uint32_t)0x00000020) /*!< TXRIS :Request */ -#define FUARTxRIS_RXRIS_REQ ((uint32_t)0x00000010) /*!< RXRIS :Request */ - -/** - * @} - */ /* End of group FUARTxRIS */ - -/** - * @defgroup FUARTxMIS FUARTxMIS Register - * @brief FUARTxMIS Register Definition. - * @{ - */ -#define FUARTxMIS_OEMIS_MASK ((uint32_t)0x00000400) /*!< OEMIS :Mask */ -#define FUARTxMIS_BEMIS_MASK ((uint32_t)0x00000200) /*!< BEMIS :Mask */ -#define FUARTxMIS_PEMIS_MASK ((uint32_t)0x00000100) /*!< PRMIS :Mask */ -#define FUARTxMIS_FEMIS_MASK ((uint32_t)0x00000080) /*!< FEMIS :Mask */ -#define FUARTxMIS_RTMIS_MASK ((uint32_t)0x00000040) /*!< RTMIS :Mask */ -#define FUARTxMIS_TXMIS_MASK ((uint32_t)0x00000020) /*!< TXMIS :Mask */ -#define FUARTxMIS_RXMIS_MASK ((uint32_t)0x00000010) /*!< RXMIS :Mask */ - -#define FUARTxMIS_OEMIS_REQ ((uint32_t)0x00000400) /*!< OEMIS :Request */ -#define FUARTxMIS_BEMIS_REQ ((uint32_t)0x00000200) /*!< BEMIS :Request */ -#define FUARTxMIS_PEMIS_REQ ((uint32_t)0x00000100) /*!< PRMIS :Request */ -#define FUARTxMIS_FEMIS_REQ ((uint32_t)0x00000080) /*!< FEMIS :Request */ -#define FUARTxMIS_RTMIS_REQ ((uint32_t)0x00000040) /*!< RTMIS :Request */ -#define FUARTxMIS_TXMIS_REQ ((uint32_t)0x00000020) /*!< TXMIS :Request */ -#define FUARTxMIS_RXMIS_REQ ((uint32_t)0x00000010) /*!< RXMIS :Request */ - -/** - * @} - */ /* End of group FUARTxMIS */ - -/** - * @defgroup FUARTxICR FUARTxICR Register - * @brief FUARTxICR Register Definition. - * @{ - */ -#define FUARTxICR_OEIC_MASK ((uint32_t)0x00000400) /*!< OEIC :Mask */ -#define FUARTxICR_BEIC_MASK ((uint32_t)0x00000200) /*!< BEIC :Mask */ -#define FUARTxICR_PEIC_MASK ((uint32_t)0x00000100) /*!< PRIC :Mask */ -#define FUARTxICR_FEIC_MASK ((uint32_t)0x00000080) /*!< FEIC :Mask */ -#define FUARTxICR_RTIC_MASK ((uint32_t)0x00000040) /*!< RTIC :Mask */ -#define FUARTxICR_TXIC_MASK ((uint32_t)0x00000020) /*!< TXIC :Mask */ -#define FUARTxICR_RXIC_MASK ((uint32_t)0x00000010) /*!< RXIC :Mask */ - -#define FUARTxICR_OEIC_CLR ((uint32_t)0x00000400) /*!< OEIC :Request */ -#define FUARTxICR_BEIC_CLR ((uint32_t)0x00000200) /*!< BEIC :Request */ -#define FUARTxICR_PEIC_CLR ((uint32_t)0x00000100) /*!< PRIC :Request */ -#define FUARTxICR_FEIC_CLR ((uint32_t)0x00000080) /*!< FEIC :Request */ -#define FUARTxICR_RTIC_CLR ((uint32_t)0x00000040) /*!< RTIC :Request */ -#define FUARTxICR_TXIC_CLR ((uint32_t)0x00000020) /*!< TXIC :Request */ -#define FUARTxICR_RXIC_CLR ((uint32_t)0x00000010) /*!< RXIC :Request */ - -/** - * @} - */ /* End of group FUARTxICR */ - -/** - * @defgroup FUARTxDMACR FUARTxDMACR Register - * @brief FUARTxDMACR Register Definition. - * @{ - */ -#define FUARTxDMACR_RXDMAE_MASK ((uint32_t)0x00000001) /*!< RXDMAE :Mask */ -#define FUARTxDMACR_TXDMAE_MASK ((uint32_t)0x00000002) /*!< TXDMAE :Mask */ - -#define FUARTxDMACR_RXDMAE_ENABLE ((uint32_t)0x00000001) /*!< RXDMAE :Enable */ -#define FUARTxDMACR_TXDMAE_ENABLE ((uint32_t)0x00000002) /*!< TXDMAE :Enable */ - -#define FUARTxDMACR_RXDMAE_DISABLE ((uint32_t)0x00000000) /*!< RXDMAE :Disable */ -#define FUARTxDMACR_TXDMAE_DISABLE ((uint32_t)0x00000000) /*!< TXDMAE :Disable */ -/** - * @} - */ /* End of group FUARTxDMACR */ - - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Inline Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_fuctions - * @{ - */ -__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); -__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); -__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); -__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); -/*--------------------------------------------------*/ -/** - * @brief Disable FUARTxCR TXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 0; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 0; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable FUARTxCR TXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 1; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 1; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Disable FUARTxCR RXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 0; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 0; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable FUARTxCR RXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 1; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 1; -#endif -} - - -/** - * @} - */ /* End of group FUART_Private_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __UART_EX_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_gpio.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_gpio.h deleted file mode 100644 index fc21163d8c7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_gpio.h +++ /dev/null @@ -1,2406 +0,0 @@ -/** - ******************************************************************************* - * @file txz_gpio.h - * @brief This file provides all the functions prototypes for GPIO driver. - * @version V1.0.0. - * $Date:: 2017-11-09 16:44:27 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __GPIO_H -#define __GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define TMPM4G9 - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup GPIO GPIO - * @brief GPIO Driver. - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Exported_define GPIO Exported Define - * @{ - */ - - -/** - * @defgroup GPIO_Result Result - * @brief GPIO Result Macro Definition. - * @{ - */ -#define GPIO_RESULT_SUCCESS (0) /*!< Success */ -#define GPIO_RESULT_FAILURE (-1) /*!< Failure */ -#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ -/** - * @} - */ /* End of group GPIO_Result */ - -/** - * @} - */ /* End of group GPIO_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef - * @{ - */ - -/** - * @enum gpio_pinstate_t - * @brief Pin State Reset/Set Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PIN_RESET = 0, /*!< 0: Clear */ - GPIO_PIN_SET, /*!< 1: Set */ -}gpio_pinstate_t; - -/** - * @enum gpio_pininout_t - * @brief Pin Input/Output Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PIN_INPUT = 0, /*!< 0: Input */ - GPIO_PIN_OUTPUT, /*!< 1: Output */ - GPIO_PIN_INOUT, /*!< 2: Input/Output */ - GPIO_PIN_NOTINOUT, /*!< 3: Not Input/Output */ -}gpio_pininout_t; - -/** - * @enum gpio_gr_t - * @brief Port Group Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PORT_A = 0x0, /*!< 0: PA */ - GPIO_PORT_B, /*!< 1: PB */ - GPIO_PORT_C, /*!< 2: PC */ - GPIO_PORT_D, /*!< 3: PD */ - GPIO_PORT_E, /*!< 4: PE */ - GPIO_PORT_F, /*!< 5: PF */ - GPIO_PORT_G, /*!< 6: PG */ - GPIO_PORT_H, /*!< 7: PH */ - GPIO_PORT_J, /*!< 8: PJ */ - GPIO_PORT_K, /*!< 9: PK */ - GPIO_PORT_L, /*!< 10:PL */ - GPIO_PORT_M, /*!< 11: PM */ - GPIO_PORT_N, /*!< 12: PN */ - GPIO_PORT_P, /*!< 13: PP */ - GPIO_PORT_R, /*!< 14: PR */ - GPIO_PORT_T, /*!< 15: PT */ - GPIO_PORT_U, /*!< 16: PU */ - GPIO_PORT_V, /*!< 17: PV */ - GPIO_PORT_W, /*!< 18: PW */ - GPIO_PORT_Y, /*!< 19: PY */ - GPIO_GROUP_Max /*!< Max Number */ -}gpio_gr_t; - -/** - * @enum gpio_num_t - * @brief Port Number Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PORT_0 = 0x0, /*!< 0: Port0 */ - GPIO_PORT_1, /*!< 1: Port1 */ - GPIO_PORT_2, /*!< 2: Port2 */ - GPIO_PORT_3, /*!< 3: Port3 */ - GPIO_PORT_4, /*!< 4: Port4 */ - GPIO_PORT_5, /*!< 5: Port5 */ - GPIO_PORT_6, /*!< 6: Port6 */ - GPIO_PORT_7, /*!< 7: Port7 */ - GPIO_PORT_Max /*!< Max Number */ -}gpio_num_t; - -/** - * @enum gpio_fr_t - * @brief Port Function Number Enumerated Type Definition. - */ -typedef enum -{ - GPIO_FR_1 = 1, /*!< 1: PxFR1 */ - GPIO_FR_2, /*!< 2: PxFR2 */ - GPIO_FR_3, /*!< 3: PxFR3 */ - GPIO_FR_4, /*!< 4: PxFR4 */ - GPIO_FR_5, /*!< 5: PxFR5 */ - GPIO_FR_6, /*!< 6: PxFR6 */ - GPIO_FR_7, /*!< 7: PxFR7 */ - GPIO_FR_NA, /*!< 8: N/A */ - GPIO_FR_Max, /*!< Max Number */ -}gpio_fr_t; - -/** - * @enum gpio_mode_t - * @brief Port Mode Enumerated Type Definition. - */ -typedef enum -{ - GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */ - GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */ - GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */ - GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */ - GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */ - GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */ - GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */ - GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */ - GPIO_Mode_FR7 = 0x20, /*!< 0x20: PxFR7 */ - GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */ - GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */ - GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */ - GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */ -}gpio_mode_t; - -/** - * @enum gpio_pa0_func_t - * @brief PortA0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA0_INT02a = 0, /*!< 0: INT02a */ - GPIO_PA0_EA00 = GPIO_FR_1, /*!< PAFR1: EA00 */ - GPIO_PA0_T32A00INB1 = GPIO_FR_2, /*!< PAFR2: T32A00INB1 */ - GPIO_PA0_T32A00INA0 = GPIO_FR_3, /*!< PAFR3: T32A00INA0 */ - GPIO_PA0_T32A00INC0 = GPIO_FR_5, /*!< PAFR5: T32A00INC0 */ - GPIO_PA0_TSPI0CSIN = GPIO_FR_6, /*!< PAFR6: TSPI0CSIN */ - GPIO_PA0_TSPI0CS0 = GPIO_FR_7, /*!< PAFR7: TSPI0CS0 */ -}gpio_pa0_func_t; - -/** - * @enum gpio_pa1_func_t - * @brief PortA1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA1_EA01 = GPIO_FR_1, /*!< PAFR1: EA01 */ - GPIO_PA1_T32A00OUTA = GPIO_FR_3, /*!< PAFR3: T32A00OUTA */ - GPIO_PA1_T32A00OUTC = GPIO_FR_5, /*!< PAFR5: T32A00OUTC */ - GPIO_PA1_TSPI0CLK = GPIO_FR_7, /*!< PAFR7: TSPI0CLK */ -}gpio_pa1_func_t; - -/** - * @enum gpio_pa2_func_t - * @brief PortA2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA2_EA02 = GPIO_FR_1, /*!< PAFR1: EA02 */ - GPIO_PA2_T32A00OUTB = GPIO_FR_3, /*!< PAFR3: T32A00OUTB */ - GPIO_PA2_TSPI0RXD = GPIO_FR_7, /*!< PAFR7: TSPI0RXD */ -}gpio_pa2_func_t; - - /** - * @enum gpio_pa3_func_t - * @brief PortA3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA3_EA03 = GPIO_FR_1, /*!< PAFR1: EA03 */ - GPIO_PA3_T32A00INA1 = GPIO_FR_2, /*!< PAFR2: T32A00INA1 */ - GPIO_PA3_T32A00INB0 = GPIO_FR_3, /*!< PAFR3: T32A00INB0 */ - GPIO_PA3_T32A00INC1 = GPIO_FR_5, /*!< PAFR5: T32A00INC1 */ - GPIO_PA3_TSPI2CS1 = GPIO_FR_6, /*!< PAFR6: TSPI2CS1 */ - GPIO_PA3_TSPI0TXD = GPIO_FR_7, /*!< PAFR6: TSPI2CS1 */ -}gpio_pa3_func_t; - - /** - * @enum gpio_pa4_func_t - * @brief PortA4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA4_EA04 = GPIO_FR_1, /*!< PAFR1: EA04 */ - GPIO_PA4_T32A01INB1 = GPIO_FR_2, /*!< PAFR2: T32A01INB1 */ - GPIO_PA4_T32A01INA0 = GPIO_FR_3, /*!< PAFR3: T32A01INA0 */ - GPIO_PA4_T32A01INC0 = GPIO_FR_5, /*!< PAFR5: T32A01INC0 */ - GPIO_PA4_TSPI0CS1 = GPIO_FR_6, /*!< PAFR6: TSPI0CS1 */ - GPIO_PA4_TSPI2TXD = GPIO_FR_7, /*!< PAFR7: TSPI2TXD */ -}gpio_pa4_func_t; - -/** - * @enum gpio_pa5_func_t - * @brief PortA5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA5_EA05 = GPIO_FR_1, /*!< PAFR1: EA05 */ - GPIO_PA5_T32A01OUTA = GPIO_FR_3, /*!< PAFR3: T32A01OUTA */ - GPIO_PA5_T32A01OUTC = GPIO_FR_5, /*!< PAFR5: T32A01OUTC */ - GPIO_PA5_TSPI0CS2 = GPIO_FR_6, /*!< PAFR6: TSPI0CS2 */ - GPIO_PA5_TSPI2RXD = GPIO_FR_7, /*!< PAFR7: TSPI2RXD */ -}gpio_pa5_func_t; - -/** - * @enum gpio_pa6_func_t - * @brief PortA6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA6_EA06 = GPIO_FR_1, /*!< PAFR1: EA06 */ - GPIO_PA6_T32A01OUTB = GPIO_FR_3, /*!< PAFR3: T32A01OUTB */ - GPIO_PA6_TSPI0CS3 = GPIO_FR_6, /*!< PAFR6: TSPI0CS3 */ - GPIO_PA6_TSPI2SCK = GPIO_FR_7, /*!< PAFR7: TSPI2SCK */ -}gpio_pa6_func_t; - - -/** - * @enum gpio_pa7_func_t - * @brief PortA6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PA7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PA7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PA7_INT03a = 0, /*!< 0: INT03a */ - GPIO_PA7_EA07 = GPIO_FR_1, /*!< PAFR1: EA07 */ - GPIO_PA7_T32A01INA1 = GPIO_FR_2, /*!< PAFR2: T32A01INA1 */ - GPIO_PA7_T32A01INB0 = GPIO_FR_3, /*!< PAFR3: T32A01INB0 */ - GPIO_PA7_T32A01INC1 = GPIO_FR_5, /*!< PAFR5: T32A01INC1 */ - GPIO_PA7_TSPI2CSIN = GPIO_FR_6, /*!< PAFR6: TSPI2CSIN */ - GPIO_PA7_TSPI2CS0 = GPIO_FR_7, /*!< PAFR7: TSPI2CS0 */ -}gpio_pa7_func_t; - - - -/** - * @enum gpio_pb0_func_t - * @brief PortB0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB0_INT04a = 0, /*!< 0: INT04a */ - GPIO_PB0_EA08 = GPIO_FR_1, /*!< PBFR1: EA08 */ - GPIO_PB0_T32A02INB1 = GPIO_FR_2, /*!< PBFR2: T32A02INB1 */ - GPIO_PB0_T32A02INA0 = GPIO_FR_3, /*!< PBFR3: T32A02INA0 */ - GPIO_PB0_T32A02INC0 = GPIO_FR_5, /*!< PBFR5: T32A02INC0 */ -}gpio_pb0_func_t; - -/** - * @enum gpio_pb1_func_t - * @brief PortB1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB1_INT05a = 0, /*!< 0: INT05a */ - GPIO_PB1_EA09 = GPIO_FR_1, /*!< PBFR1: EA09 */ - GPIO_PB1_T32A02INA1 = GPIO_FR_2, /*!< PBFR2: T32A02INA1 */ - GPIO_PB1_T32A02INB0 = GPIO_FR_3, /*!< PBFR3: T32A02INB0 */ - GPIO_PB1_T32A02INC1 = GPIO_FR_5, /*!< PBFR5: T32A02INC1 */ - GPIO_PB1_HDMAREQB = GPIO_FR_6, /*!< PBFR6: HDMAREQB */ -}gpio_pb1_func_t; - -/** - * @enum gpio_pb2_func_t - * @brief PortB2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB2_EA10 = GPIO_FR_1, /*!< PBFR1: EA10 */ - GPIO_PB2_T32A02OUTA = GPIO_FR_3, /*!< PBFR3: T32A02OUTA */ - GPIO_PB2_T32A02OUTC = GPIO_FR_5, /*!< PBFR5: T32A02OUTC */ -}gpio_pb2_func_t; - - /** - * @enum gpio_pb3_func_t - * @brief PortB3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB3_EA11 = GPIO_FR_1, /*!< PBFR1: EA11 */ - GPIO_PB3_T32A02OUTB = GPIO_FR_3, /*!< PBFR3: T32A02OUTB */ -}gpio_pb3_func_t; - - /** - * @enum gpio_pb4_func_t - * @brief PortB4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB4_EA12 = GPIO_FR_1, /*!< PBFR1: EA12 */ - GPIO_PB4_T32A03OUTA = GPIO_FR_3, /*!< PBFR3: T32A03OUTA */ - GPIO_PB4_T32A03OUTC = GPIO_FR_5, /*!< PBFR5: T32A03OUTC */ -}gpio_pb4_func_t; - -/** - * @enum gpio_pb5_func_t - * @brief PortB5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB5_EA13 = GPIO_FR_1, /*!< PBFR1: EA13 */ - GPIO_PB5_T32A03OUTB = GPIO_FR_3, /*!< PBFR3: T32A03OUTB */ -}gpio_pb5_func_t; - -/** - * @enum gpio_pb6_func_t - * @brief PortB6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB6_INT06a = 0, /*!< 0: INT06a */ - GPIO_PB6_EA14 = GPIO_FR_1, /*!< PBFR1: EA14 */ - GPIO_PB6_T32A03INB1 = GPIO_FR_2, /*!< PBFR2: T32A03INB1 */ - GPIO_PB6_T32A03INA0 = GPIO_FR_3, /*!< PBFR3: T32A03INA0 */ - GPIO_PB6_T32A03INC0 = GPIO_FR_5, /*!< PBFR5: T32A03INC0 */ -}gpio_pb6_func_t; - -/** - * @enum gpio_pb7_func_t - * @brief PortB7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PB7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PB7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PB7_INT07a = 0, /*!< 0: INT07a */ - GPIO_PB7_EA15 = GPIO_FR_1, /*!< PBFR1: EA15 */ - GPIO_PB7_T32A03INA1 = GPIO_FR_2, /*!< PBFR2: T32A03INA1 */ - GPIO_PB7_T32A03INB0 = GPIO_FR_3, /*!< PBFR3: T32A03INB0 */ - GPIO_PB7_T32A03INC1 = GPIO_FR_5, /*!< PBFR5: T32A03INC1 */ -}gpio_pb7_func_t; - - -/** - * @enum gpio_pc0_func_t - * @brief PortC0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC0_INT12a = 0, /*!< 0: INT12a */ - GPIO_PC0_EA16 = GPIO_FR_1, /*!< PCFR1: EA16 */ - GPIO_PC0_T32A08INA0 = GPIO_FR_3, /*!< PCFR3: T32A08INA0 */ - GPIO_PC0_T32A08INC0 = GPIO_FR_5, /*!< PCFR5: T32A08INC0 */ -}gpio_pc0_func_t; - -/** - * @enum gpio_pc1_func_t - * @brief PortC1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC1_INT13a = 0, /*!< 0: INT13a */ - GPIO_PC1_EA17 = GPIO_FR_1, /*!< PCFR1: EA17 */ - GPIO_PC1_T32A08INB0 = GPIO_FR_3, /*!< PCFR3: T32A08INB0 */ - GPIO_PC1_T32A08INC1 = GPIO_FR_5, /*!< PCFR5: T32A08INC1 */ -}gpio_pc1_func_t; - -/** - * @enum gpio_pc2_func_t - * @brief PortC2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC2_EA18 = GPIO_FR_1, /*!< PCFR1: UT4TXDB */ - GPIO_PC2_T32A08OUTA = GPIO_FR_3, /*!< PCFR3: T32A08OUTA */ - GPIO_PC2_T32A08OUTC = GPIO_FR_5, /*!< PCFR5: T32A08OUTC */ -}gpio_pc2_func_t; - - /** - * @enum gpio_pc3_func_t - * @brief PortC3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC3_EA19 = GPIO_FR_1, /*!< PCFR1: EA19 */ - GPIO_PC3_T32A08OUTB = GPIO_FR_3, /*!< PCFR3: T32A08OUTB */ -}gpio_pc3_func_t; - - /** - * @enum gpio_pc4_func_t - * @brief PortC4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC4_EA20 = GPIO_FR_1, /*!< PCFR1: EA20 */ - GPIO_PC4_T32A10OUTA = GPIO_FR_3, /*!< PCFR3: T32A10OUTA */ - GPIO_PC4_T32A10OUTC = GPIO_FR_5, /*!< PCFR5: T32A10OUTC */ -}gpio_pc4_func_t; - -/** - * @enum gpio_pc5_func_t - * @brief PortC5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC5_EA21 = GPIO_FR_1, /*!< PCFR1: EA21 */ - GPIO_PC5_T32A10OUTB = GPIO_FR_3, /*!< PCFR3: T32A10OUTB */ -}gpio_pc5_func_t; - -/** - * @enum gpio_pc6_func_t - * @brief PortC6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC6_INT14a = 0, /*!< 0: INT14a */ - GPIO_PC6_EA22 = GPIO_FR_1, /*!< PCFR1: EA22 */ -}gpio_pc6_func_t; - -/** - * @enum gpio_pc7_func_t - * @brief PortC7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PC7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PC7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PC7_INT15a = 0, /*!< 0: INT15a */ - GPIO_PC7_EA23 = GPIO_FR_1, /*!< PCFR1: EA23 */ -}gpio_pc7_func_t; - -/** - * @enum gpio_pd0_func_t - * @brief PortD0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD0_ED00 = GPIO_FR_1, /*!< PCFR1: ED00 */ - GPIO_PD0_T32A04INB1 = GPIO_FR_2, /*!< PCFR2: T32A04INB1 */ - GPIO_PD0_T32A04INA0 = GPIO_FR_3, /*!< PCFR3: T32A04INA0 */ - GPIO_PD0_TSPI4CS0 = GPIO_FR_4, /*!< PCFR4: TSPI4CS0 */ - GPIO_PD0_T32A04INC0 = GPIO_FR_5, /*!< PCFR5: T32A04INC0 */ - GPIO_PD0_TSPI4CSIN = GPIO_FR_6, /*!< PCFR6: TSPI4CSIN */ - GPIO_PD0_UO0 = GPIO_FR_7, /*!< PCFR7: UO0 */ -}gpio_pd0_func_t; - -/** - * @enum gpio_pd1_func_t - * @brief PortD1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD1_ED01 = GPIO_FR_1, /*!< PCFR1: ED01 */ - GPIO_PD1_T32A04INA1 = GPIO_FR_2, /*!< PCFR2: T32A04INA1 */ - GPIO_PD1_T32A04INB0 = GPIO_FR_3, /*!< PCFR3: T32A04INB0 */ - GPIO_PD1_TSPI4SCK = GPIO_FR_4, /*!< PCFR4: TSPI4SCK */ - GPIO_PD1_T32A04INC1 = GPIO_FR_5, /*!< PCFR5: T32A04INC1 */ - GPIO_PD1_XO0 = GPIO_FR_7, /*!< PCFR7: XO0 */ -}gpio_pd1_func_t; - -/** - * @enum gpio_pd2_func_t - * @brief PortD2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD2_ED02 = GPIO_FR_1, /*!< PCFR1: ED02 */ - GPIO_PD2_T32A04OUTA = GPIO_FR_3, /*!< PCFR3: T32A04OUTA */ - GPIO_PD2_TSPI4RXD = GPIO_FR_4, /*!< PCFR4: TSPI4RXD */ - GPIO_PD2_T32A04OUTC = GPIO_FR_5, /*!< PCFR5: T32A04OUTC */ - GPIO_PD2_VO0 = GPIO_FR_7, /*!< PCFR7: VO0 */ -}gpio_pd2_func_t; - - /** - * @enum gpio_pd3_func_t - * @brief PortD3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD3_ED03 = GPIO_FR_1, /*!< PCFR1: ED03 */ - GPIO_PD3_T32A04OUTB = GPIO_FR_3, /*!< PCFR3: T32A04OUTB */ - GPIO_PD3_TSPI4TXD = GPIO_FR_4, /*!< PCFR4: TSPI4TXD */ - GPIO_PD3_YO0 = GPIO_FR_7, /*!< PCFR7: YO0 */ -}gpio_pd3_func_t; - -/** - * @enum gpio_pd4_func_t - * @brief PortD4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD4_ED04 = GPIO_FR_1, /*!< PCFR1: ED04 */ - GPIO_PD4_T32A05OUTA = GPIO_FR_3, /*!< PCFR3: T32A05OUTA */ - GPIO_PD4_T32A05OUTC = GPIO_FR_5, /*!< PCFR5: T32A05OUTC */ - GPIO_PD4_WO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ -}gpio_pd4_func_t; - -/** - * @enum gpio_pd5_func_t - * @brief PortD5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD5_ED05 = GPIO_FR_1, /*!< PCFR1: ED05 */ - GPIO_PD5_T32A05OUTB = GPIO_FR_3, /*!< PCFR3: T32A05OUTB */ - GPIO_PD5_ZO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ -}gpio_pd5_func_t; - -/** - * @enum gpio_pd6_func_t - * @brief PortD6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD6_ED06 = GPIO_FR_1, /*!< PCFR1: ED06 */ - GPIO_PD6_T32A05INB1 = GPIO_FR_2, /*!< PCFR2: T32A05INB1 */ - GPIO_PD6_T32A05INA0 = GPIO_FR_3, /*!< PCFR3: T32A05INA0 */ - GPIO_PD6_T32A05INC0 = GPIO_FR_5, /*!< PCFR5: T32A05INC0 */ - GPIO_PD6_EMG_N = GPIO_FR_7, /*!< PCFR7: EMG_N */ -}gpio_pd6_func_t; - -/** - * @enum gpio_pd7_func_t - * @brief PortD7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PD7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PD7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PD7_ED07 = GPIO_FR_1, /*!< PCFR1: ED07 */ - GPIO_PD7_T32A05INA1 = GPIO_FR_2, /*!< PCFR2: T32A05INA1 */ - GPIO_PD7_T32A05INB0 = GPIO_FR_3, /*!< PCFR3: T32A05INB0 */ - GPIO_PD7_T32A05INC1 = GPIO_FR_5, /*!< PCFR5: T32A05INC1 */ - GPIO_PD7_OVV0_N = GPIO_FR_7, /*!< PCFR7: OVV0_N */ -}gpio_pd7_func_t; - -/** - * @enum gpio_pe0_func_t - * @brief PortE0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE0_ED08 = GPIO_FR_1, /*!< PCFR1: ED08 */ - GPIO_PE0_T32A06INB1 = GPIO_FR_2, /*!< PCFR2: T32A06INB1 */ - GPIO_PE0_T32A06OUTB = GPIO_FR_3, /*!< PCFR3: T32A06OUTB */ - GPIO_PE0_EA23 = GPIO_FR_4, /*!< PCFR4: EA23 */ - GPIO_PE0_T32A06INA1 = GPIO_FR_5, /*!< PCFR5: T32A06INA1 */ - GPIO_PE0_UT0RTS_N = GPIO_FR_7, /*!< PCFR7: UT0RTS_N */ -}gpio_pe0_func_t; - -/** - * @enum gpio_pe1_func_t - * @brief PortE1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE1_ED09 = GPIO_FR_1, /*!< PCFR1: ED09 */ - GPIO_PE1_T32A06OUTA = GPIO_FR_3, /*!< PCFR3: T32A06OUTA */ - GPIO_PE1_EA22 = GPIO_FR_4, /*!< PCFR4: EA22 */ - GPIO_PE1_T32A06OUTC = GPIO_FR_5, /*!< PCFR5: T32A06OUTC */ - GPIO_PE1_UT0CTS_N = GPIO_FR_7, /*!< PCFR7: UT0CTS_N */ -}gpio_pe1_func_t; - -/** - * @enum gpio_pe2_func_t - * @brief PortE2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE2_ED10 = GPIO_FR_1, /*!< PCFR1: ED10 */ - GPIO_PE2_T32A06INA0 = GPIO_FR_3, /*!< PCFR3: T32A06INA0 */ - GPIO_PE2_EA21 = GPIO_FR_4, /*!< PCFR4: EA21 */ - GPIO_PE2_T32A06INC0 = GPIO_FR_5, /*!< PCFR5: T32A06INC0 */ - GPIO_PE2_UT0RXD = GPIO_FR_7, /*!< PCFR7: UT0RXD */ -}gpio_pe2_func_t; - - /** - * @enum gpio_pe3_func_t - * @brief PortE3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE3_ED11 = GPIO_FR_1, /*!< PCFR1: ED11 */ - GPIO_PE3_T32A06INB0 = GPIO_FR_3, /*!< PCFR3: T32A06INB0 */ - GPIO_PE3_EA20 = GPIO_FR_4, /*!< PCFR4: EA20 */ - GPIO_PE3_T32A06INC1 = GPIO_FR_5, /*!< PCFR5: T32A06INC1 */ - GPIO_PE3_UT0TXDA = GPIO_FR_7, /*!< PCFR7: UT0TXDA */ -}gpio_pe3_func_t; - - /** - * @enum gpio_pe4_func_t - * @brief PortE4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE4_ED12 = GPIO_FR_1, /*!< PCFR1: ED12 */ - GPIO_PE4_T32A07INA0 = GPIO_FR_3, /*!< PCFR3: T32A07INA0 */ - GPIO_PE4_EA19 = GPIO_FR_4, /*!< PCFR4: EA19 */ - GPIO_PE4_T32A07INC0 = GPIO_FR_5, /*!< PCFR5: T32A07INC0 */ - GPIO_PE4_ISDAIN0 = 0, /*!< 0: ISDAIN0 */ -}gpio_pe4_func_t; - -/** - * @enum gpio_pe5_func_t - * @brief PortE5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE5_ED13 = GPIO_FR_1, /*!< PCFR1: ED13 */ - GPIO_PE5_T32A07INB0 = GPIO_FR_3, /*!< PCFR3: T32A07INB0 */ - GPIO_PE5_EA18 = GPIO_FR_4, /*!< PCFR4: EA18 */ - GPIO_PE5_T32A07INC1 = GPIO_FR_5, /*!< PCFR5: T32A07INC1 */ - GPIO_PE5_ISDAIN1 = 0, /*!< 0: ISDAIN1 */ -}gpio_pe5_func_t; - -/** - * @enum gpio_pe6_func_t - * @brief PortE6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE6_ED14 = GPIO_FR_1, /*!< PCFR1: ED14 */ - GPIO_PE6_T32A07OUTA = GPIO_FR_3, /*!< PCFR3: T32A07OUTA */ - GPIO_PE6_EA17 = GPIO_FR_4, /*!< PCFR4: EA17 */ - GPIO_PE6_T32A07OUTC = GPIO_FR_5, /*!< PCFR5: T32A07OUTC */ - GPIO_PE6_ISDAIN2 = 0, /*!< 0: ISDAIN2 */ -}gpio_pe6_func_t; - -/** - * @enum gpio_pe7_func_t - * @brief PortE7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PE7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PE7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PE7_ED15 = GPIO_FR_1, /*!< PCFR1: ED15 */ - GPIO_PE7_T32A07INB1 = GPIO_FR_2, /*!< PCFR2: T32A07INB1 */ - GPIO_PE7_T32A07OUTB = GPIO_FR_3, /*!< PCFR3: T32A07OUTB */ - GPIO_PE7_EA16 = GPIO_FR_4, /*!< PCFR4: EA16 */ - GPIO_PE7_T32A07INA1 = GPIO_FR_5, /*!< PCFR5: T32A07INA1 */ - GPIO_PE7_ISDAIN3 = 0, /*!< 0: ISDAIN3 */ -}gpio_pe7_func_t; - -/** - * @enum gpio_pf0_func_t - * @brief PortF0 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF0_INT04b = 0, /*!< 0: INT04b */ - GPIO_PF0_ERD_N = GPIO_FR_1, /*!< PCFR1: ERD_N */ -}gpio_pf0_func_t; - -/** - * @enum gpio_pf1_func_t - * @brief PortF1 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF1_EWR_N = GPIO_FR_1, /*!< PCFR1: EWR_N */ -}gpio_pf1_func_t; - -/** - * @enum gpio_pf2_func_t - * @brief PortF2 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF2_I2C1SDA = GPIO_FR_7, /*!< PCFR7: I2C1SDA */ -}gpio_pf2_func_t; - - /** - * @enum gpio_pf3_func_t - * @brief PortF3 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF3_I2C1SCL = GPIO_FR_7, /*!< PCFR7: I2C1SCL */ -}gpio_pf3_func_t; - - /** - * @enum gpio_pf4_func_t - * @brief PortF4 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF4_ECS2_N = GPIO_FR_1, /*!< PCFR1: ECS2_N */ -}gpio_pf4_func_t; - - /** - * @enum gpio_pf5_func_t - * @brief PortF5 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF5_ECS3_N = GPIO_FR_1, /*!< PCFR1: ECS3_N */ -}gpio_pf5_func_t; - - /** - * @enum gpio_pf6_func_t - * @brief PortF6 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF6_EBELL_N = GPIO_FR_1, /*!< PCFR1: EBELL_N */ -}gpio_pf6_func_t; - - /** - * @enum gpio_pf7_func_t - * @brief PortF7 Function Enumerated TyPF Definition. - */ -typedef enum -{ - GPIO_PF7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PF7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PF7_INT05b = 0, /*!< 0: INT05b */ - GPIO_PF7_EBELH_N = GPIO_FR_1, /*!< PCFR1: EBELH_N */ -}gpio_pf7_func_t; - -/** - * @enum gpio_pg0_func_t - * @brief PortG0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG0_INT08a = 0, /*!< 0: INT08a */ - GPIO_PG0_EALE = GPIO_FR_1, /*!< PCFR1: EALE */ - GPIO_PG0_UT2RXD = GPIO_FR_3, /*!< PCFR3: UT2RXD */ - GPIO_PG0_UT2TXDA = GPIO_FR_5, /*!< PCFR5: UT2TXDA */ -}gpio_pg0_func_t; - -/** - * @enum gpio_pg1_func_t - * @brief PortG1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG1_INT09a = 0, /*!< 0: INT09a */ - GPIO_PG1_EWAIT_N = GPIO_FR_1, /*!< PCFR1: EWAIT_N */ - GPIO_PG1_UT2TXDA = GPIO_FR_3, /*!< PCFR3: UT2TXDA */ - GPIO_PG1_UT2RXD = GPIO_FR_5, /*!< PCFR5: UT2RXD */ -}gpio_pg1_func_t; - -/** - * @enum gpio_pg2_func_t - * @brief PortG2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG2_UT2RTS_N = GPIO_FR_3, /*!< PCFR3: UT2RTS_N */ - GPIO_PG2_RTCALARM = GPIO_FR_4, /*!< PCFR4: RTCALARM */ - GPIO_PG2_UT2CTS_N = GPIO_FR_5, /*!< PCFR5: UT2CTS_N */ - GPIO_PG2_I2C0SDA = GPIO_FR_7, /*!< PCFR7: I2C0SDA */ -}gpio_pg2_func_t; - -/** - * @enum gpio_pg3_func_t - * @brief PortG3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG3_UT2CTS_N = GPIO_FR_3, /*!< PCFR3: UT2CTS_N */ - GPIO_PG3_TRGIN = GPIO_FR_4, /*!< PCFR4: TRGIN */ - GPIO_PG3_UT2RTS_N = GPIO_FR_5, /*!< PCFR5: UT2RTS_N */ - GPIO_PG3_I2C0SCL = GPIO_FR_7, /*!< PCFR7: I2C0SCL */ -}gpio_pg3_func_t; - -/** - * @enum gpio_pg4_func_t - * @brief PortG4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG4_T32A02OUTB = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ - GPIO_PG4_FUT0IROUT = GPIO_FR_4, /*!< PCF41: FUT0IROUT */ - GPIO_PG4_FUT0TXD = GPIO_FR_5, /*!< PCFR5: FUT0TXD */ - GPIO_PG4_I2C2SDA = GPIO_FR_7, /*!< PCFR7: I2C2SDA */ -}gpio_pg4_func_t; - -/** - * @enum gpio_pg5_func_t - * @brief PortG5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG5_T32A02OUTA = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ - GPIO_PG5_T32A02OUTC = GPIO_FR_3, /*!< PCFR3: T32A02OUTC */ - GPIO_PG5_FUT0SI_SIRIN = GPIO_FR_4, /*!< PCFR4: FUT0SI_SIRIN */ - GPIO_PG5_FUT0RXD = GPIO_FR_5, /*!< PCFR5: FUT0RXD */ - GPIO_PG5_I2C2SCL = GPIO_FR_7, /*!< PCFR7: I2C2SCL */ -}gpio_pg5_func_t; - -/** - * @enum gpio_pg6_func_t - * @brief PortG6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG6_TRACECLK = GPIO_FR_1, /*!< PCFR1: TRACECLK */ - GPIO_PG6_NBD0CLK = GPIO_FR_4, /*!< PCFR4: NBD0CLK */ - GPIO_PG6_FUT0RTS_N = GPIO_FR_5, /*!< PCFR5: FUT0RTS_N */ -}gpio_pg6_func_t; - -/** - * @enum gpio_pg7_func_t - * @brief PortG7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PG7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PG7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PG7_TRACEDATA0 = GPIO_FR_1, /*!< PCFR1: TRACEDATA0 */ - GPIO_PG7_NBD0DATA0 = GPIO_FR_4, /*!< PCFR4: NBD0DATA0 */ - GPIO_PG7_FUT0CTS_N = GPIO_FR_5, /*!< PCFR5: FUT0CTS_N */ -}gpio_pg7_func_t; - -/** - * @enum gpio_ph0_func_t - * @brief PortH0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH0_TRACEDATA1 = GPIO_FR_1, /*!< PCFR1: TRACEDATA1 */ - GPIO_PH0_UT1RXD = GPIO_FR_3, /*!< PCFR3: UT1RXD */ - GPIO_PH0_NBD0DATA1 = GPIO_FR_4, /*!< PCFR4: NBD0DATA1 */ - GPIO_PH0_UT1TXDA = GPIO_FR_5, /*!< PCFR5: UT1TXDA */ -}gpio_ph0_func_t; - -/** - * @enum gpio_ph1_func_t - * @brief PortH1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH1_TRACEDATA2 = GPIO_FR_1, /*!< PCFR1: TRACEDATA2 */ - GPIO_PH1_UT1TXDA = GPIO_FR_3, /*!< PCFR3: UT1TXDA */ - GPIO_PH1_NBD0DATA2 = GPIO_FR_4, /*!< PCFR4: NBD0DATA2 */ - GPIO_PH1_UT1RXD = GPIO_FR_5, /*!< PCFR5: UT1RXD */ -}gpio_ph1_func_t; - -/** - * @enum gpio_ph2_func_t - * @brief PortH2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH2_TRACEDATA3 = GPIO_FR_1, /*!< PCFR1: TRACEDATA3 */ - GPIO_PH2_UT1RTS_N = GPIO_FR_3, /*!< PCFR3: UT1RTS_N */ - GPIO_PH2_NBD0DATA3 = GPIO_FR_4, /*!< PCFR4: NBD0DATA3 */ - GPIO_PH2_UT1CTS_N = GPIO_FR_5, /*!< PCFR5: UT1CTS_N */ -}gpio_ph2_func_t; - - /** - * @enum gpio_ph3_func_t - * @brief PortH3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH3_TDI = GPIO_FR_1, /*!< PCFR1: TDI */ - GPIO_PH3_UT1CTS_N = GPIO_FR_3, /*!< PCFR3: UT1CTS_N */ - GPIO_PH3_NBD0SYNC = GPIO_FR_4, /*!< PCFR4: NBD0SYNC */ - GPIO_PH3_UT1RTS_N = GPIO_FR_5, /*!< PCFR5: UT1RTS_N */ -}gpio_ph3_func_t; - - /** - * @enum gpio_ph4_func_t - * @brief PortH4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH4_SWDIO = GPIO_FR_1, /*!< PCFR1: SWDIO */ - GPIO_PH4_UT0RXD = GPIO_FR_3, /*!< PCFR3: UT0RXD */ - GPIO_PH4_UT0TXDA = GPIO_FR_5, /*!< PCFR5: UT0TXDA */ -}gpio_ph4_func_t; - - /** - * @enum gpio_ph5_func_t - * @brief PortH5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH5_TCK = GPIO_FR_1, /*!< PCFR1: TCK */ - GPIO_PH5_UT0TXDA = GPIO_FR_3, /*!< PCFR3: UT0TXDA */ - GPIO_PH5_UT0RXD = GPIO_FR_5, /*!< PCFR5: UT0RXD */ -}gpio_ph5_func_t; - - /** - * @enum gpio_ph6_func_t - * @brief PortH6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH6_TDO = GPIO_FR_1, /*!< PCFR1: TDO */ - GPIO_PH6_UT0RTS_N = GPIO_FR_3, /*!< PCFR3: UT0RTS_N */ - GPIO_PH6_UT0CTS_N = GPIO_FR_5, /*!< PCFR5: UT0CTS_N */ -}gpio_ph6_func_t; - - /** - * @enum gpio_ph7_func_t - * @brief PortH7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PH7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PH7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PH7_TRST_N = GPIO_FR_1, /*!< PCFR1: TRST_N */ - GPIO_PH7_UT0CTS_N = GPIO_FR_3, /*!< PCFR3: UT0CTS_N */ - GPIO_PH7_UT0RTS_N = GPIO_FR_5, /*!< PCFR5: UT0RTS_N */ -}gpio_ph7_func_t; - -/** - * @enum gpio_pj0_func_t - * @brief PortJ0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ0_UT5RXD = GPIO_FR_3, /*!< PJFR3: UT5RXD */ - GPIO_PJ0_UT5TXDA = GPIO_FR_5, /*!< PJFR5: UT5TXDA */ -}gpio_pj0_func_t; - -/** - * @enum gpio_pj1_func_t - * @brief PortJ1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ1_UT5TXDA = GPIO_FR_3, /*!< PJFR3: UT5TXDA */ - GPIO_PJ1_UT5RXD = GPIO_FR_5, /*!< PJFR5: UT5RXD */ -}gpio_pj1_func_t; - -/** - * @enum gpio_pj2_func_t - * @brief PortJ2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ2_UT5RTS_N = GPIO_FR_3, /*!< PJFR3: UT5RTS_N */ - GPIO_PJ2_UT5CTS_N = GPIO_FR_5, /*!< PJFR5: UT5CTS_N */ - GPIO_PJ2_I2C4SCL = GPIO_FR_7, /*!< PJFR7: I2C4SCL */ -}gpio_pj2_func_t; - - /** - * @enum gpio_pj3_func_t - * @brief PortJ3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ3_UT5CTS_N = GPIO_FR_3, /*!< PJFR3: UT5CTS_N */ - GPIO_PJ3_UT5RTS_N = GPIO_FR_5, /*!< PJFR5: UT5RTS_N */ - GPIO_PJ3_I2C4SDA = GPIO_FR_7, /*!< PJFR7: I2C4SDA */ -}gpio_pj3_func_t; - - /** - * @enum gpio_pj4_func_t - * @brief PortJ4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ4_T32A03INA0 = GPIO_FR_2, /*!< PJFR2: T32A03INA0 */ - GPIO_PJ4_T32A03INC0 = GPIO_FR_3, /*!< PJFR3: T32A03INC0 */ - GPIO_PJ4_FUT0TXD = GPIO_FR_5, /*!< PJFR5: FUT0TXD */ -}gpio_pj4_func_t; - -/** - * @enum gpio_pj5_func_t - * @brief PortJ5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ5_T32A03INB0 = GPIO_FR_2, /*!< PJFR2: T32A03INB0 */ - GPIO_PJ5_T32A03INC1 = GPIO_FR_3, /*!< PJFR3: T32A03INC1 */ - GPIO_PJ5_FUT0RXD = GPIO_FR_5, /*!< PJFR5: FUT0RXD */ -}gpio_pj5_func_t; - -/** - * @enum gpio_pj6_func_t - * @brief PortJ6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ6_FUT1TXD = GPIO_FR_5, /*!< PJFR5: FUT1TXD */ - GPIO_PJ6_I2C3SDA = GPIO_FR_7, /*!< PJFR7: I2C3SDA */ -}gpio_pj6_func_t; - -/** - * @enum gpio_pj7_func_t - * @brief PortJ7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PJ7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PJ7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PJ7_FUT1RXD = GPIO_FR_5, /*!< PJFR5: FUT1RXD */ - GPIO_PJ7_I2C3SCL = GPIO_FR_7, /*!< PJFR7: I2C3SCL */ -}gpio_pj7_func_t; - -/** - * @enum gpio_pk0_func_t - * @brief PortK0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK0_INT10a = 0, /*!< 0: INT10a */ - GPIO_PK0_ISDAOUT = GPIO_FR_1, /*!< PKFR1: ISDAOUT */ - GPIO_PK0_T32A00INA0 = GPIO_FR_2, /*!< PKFR2: T32A00INA0 */ - GPIO_PK0_T32A00INC0 = GPIO_FR_3, /*!< PKFR3: T32A00INC0 */ - GPIO_PK0_SMI0CS1_N = GPIO_FR_6, /*!< PKFR6: ISDAOUT */ -}gpio_pk0_func_t; - -/** - * @enum gpio_pk1_func_t - * @brief PortK1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK1_INT11a = 0, /*!< 0: INT11a */ - GPIO_PK1_ISDBOUT = GPIO_FR_1, /*!< PKFR1: ISDBOUT */ - GPIO_PK1_T32A00INB0 = GPIO_FR_2, /*!< PKFR2: T32A00INB0 */ - GPIO_PK1_T32A00INC1 = GPIO_FR_3, /*!< PKFR3: T32A00INC1 */ - GPIO_PK1_HDMAREQA = GPIO_FR_4, /*!< PKFR4: HDMAREQA */ -}gpio_pk1_func_t; - -/** - * @enum gpio_pk2_func_t - * @brief PortK2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK2_ECS0_N = GPIO_FR_1, /*!< PKFR1: ECS0_N */ - GPIO_PK2_SMI0D0 = GPIO_FR_6, /*!< PKFR6: SMI0D0 */ -}gpio_pk2_func_t; - - /** - * @enum gpio_pk3_func_t - * @brief PortK3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK3_ECS1_N = GPIO_FR_1, /*!< PKFR1: ECS1_N */ - GPIO_PK3_SMI0D1 = GPIO_FR_6, /*!< PKFR6: SMI0D1 */ -}gpio_pk3_func_t; - - /** - * @enum gpio_pk4_func_t - * @brief PortK4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK4_TSPI1CS1 = GPIO_FR_1, /*!< PKFR1: TSPI1CS1 */ - GPIO_PK4_TSPI3TXD = GPIO_FR_4, /*!< PKFR4: TSPI3TXD */ - GPIO_PK4_SMI0D2 = GPIO_FR_6, /*!< PKFR6: SMI0D2 */ -}gpio_pk4_func_t; - -/** - * @enum gpio_pk5_func_t - * @brief PortK5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK5_TSPI1CS2 = GPIO_FR_1, /*!< PKFR1: TSPI1CS2 */ - GPIO_PK5_TSPI3RXD = GPIO_FR_4, /*!< PKFR4: TSPI3RXD */ - GPIO_PK5_SMI0D3 = GPIO_FR_6, /*!< PKFR6: SMI0D3 */ -}gpio_pk5_func_t; - -/** - * @enum gpio_pk6_func_t - * @brief PortK6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK6_TSPI1CS3 = GPIO_FR_1, /*!< PKFR1: TSPI1CS3 */ - GPIO_PK6_T32A01INA0 = GPIO_FR_2, /*!< PKFR2: T32A01INA0 */ - GPIO_PK6_T32A01INC0 = GPIO_FR_3, /*!< PKFR3: T32A01INC0 */ - GPIO_PK6_TSPI3SCK = GPIO_FR_4, /*!< PKFR4: TSPI3SCK */ - GPIO_PK6_SMI0SCK = GPIO_FR_6, /*!< PKFR6: SMI0SCK */ -}gpio_pk6_func_t; - -/** - * @enum gpio_pk7_func_t - * @brief PortK7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PK7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PK7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PK7_INT00a = 0, /*!< 0: INT00a */ - GPIO_PK7_T32A01INB0 = GPIO_FR_2, /*!< PKFR2: T32A01INB0 */ - GPIO_PK7_T32A01INC1 = GPIO_FR_3, /*!< PKFR3: T32A01INC1 */ - GPIO_PK7_TSPI3CS0 = GPIO_FR_4, /*!< PKFR4: TSPI3CS0 */ - GPIO_PK7_SMI0CS0_N = GPIO_FR_6, /*!< PKFR6: SMI0CS0_N */ - GPIO_PK7_TSPI3CSIN = GPIO_FR_7, /*!< PKFR7: TSPI3CSIN */ -}gpio_pk7_func_t; - -/** - * @enum gpio_pl0_func_t - * @brief PortL0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL0_INT01a = 0, /*!< 0: INT01a */ - GPIO_PL0_T32A02INA0 = GPIO_FR_2, /*!< PLFR2: T32A02INA0 */ - GPIO_PL0_T32A02INC0 = GPIO_FR_3, /*!< PLFR3: T32A02INC0 */ - GPIO_PL0_TSPI1CSIN = GPIO_FR_6, /*!< PLFR6: TSPI1CSIN */ - GPIO_PL0_TSPI1CS0 = GPIO_FR_7, /*!< PLFR7: TSPI1CS0 */ -}gpio_pl0_func_t; - -/** - * @enum gpio_pl1_func_t - * @brief PortL1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL1_TPI1SCK = GPIO_FR_7, /*!< PLFR7: TPI1SCK */ -}gpio_pl1_func_t; - -/** - * @enum gpio_pl2_func_t - * @brief PortL2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL2_TSPI1RXD = GPIO_FR_7, /*!< PLFR7: TSPI1RXD */ -}gpio_pl2_func_t; - - /** - * @enum gpio_pl3_func_t - * @brief PortL3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL3_T32A02INB0 = GPIO_FR_2, /*!< PLFR2: T32A02INB0 */ - GPIO_PL3_T32A02INC1 = GPIO_FR_3, /*!< PLFR3: T32A02INC1 */ - GPIO_PL3_TSPI3CS1 = GPIO_FR_6, /*!< PLFR6: TSPI3CS1 */ - GPIO_PL3_TSPI1TXD = GPIO_FR_7, /*!< PLFR7: TSPI1TXD */ -}gpio_pl3_func_t; - - /** - * @enum gpio_pl4_func_t - * @brief PortL4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL4_INT12b = 0, /*!< 0: IN112b */ - GPIO_PL4_T32A08OUTA = GPIO_FR_2, /*!< PLFR2: T32A08OUTA */ - GPIO_PL4_T32A08OUTC = GPIO_FR_3, /*!< PLFR3: T32A08OUTC */ -}gpio_pl4_func_t; - -/** - * @enum gpio_pl5_func_t - * @brief PortL5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL5_INT13b = 0, /*!< 0: INT13b */ - GPIO_PL5_T32A08OUTB = GPIO_FR_2, /*!< PLFR2: T32A08OUTB */ -}gpio_pl5_func_t; - -/** - * @enum gpio_pl6_func_t - * @brief PortL6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL6_INT03b = 0, /*!< 0: INT03b */ - GPIO_PL6_T32A09OUTA = GPIO_FR_2, /*!< PLFR2: T32A09OUTA */ - GPIO_PL6_T32A09OUTC = GPIO_FR_3, /*!< PLFR3: T32A09OUTC */ -}gpio_pl6_func_t; - -/** - * @enum gpio_pl7_func_t - * @brief PortL7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PL7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PL7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PL7_TRGIN = GPIO_FR_1, /*!< PLFR1: TRGIN */ - GPIO_PL7_T32A09OUTB = GPIO_FR_2, /*!< PLFR2: T32A09OUTB */ -}gpio_pl7_func_t; - -/** - * @enum gpio_pm0_func_t - * @brief PortM0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM0_I2C3SDA = GPIO_FR_4, /*!< PMFR4: I2C3SDA */ - GPIO_PM0_UT4RXD = GPIO_FR_5, /*!< PMFR5: UT4RXD */ - GPIO_PM0_TSPI6TXD = GPIO_FR_6, /*!< PMFR6: TSPI6TXD */ - GPIO_PM0_UT4TXDA = GPIO_FR_7, /*!< PMFR7: UT4TXDA */ -}gpio_pm0_func_t; - -/** - * @enum gpio_pm1_func_t - * @brief PortM1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM1_I2C3SCL = GPIO_FR_4, /*!< PMFR4: I2C3SCL */ - GPIO_PM1_UT4TXDA = GPIO_FR_5, /*!< PMFR5: UT4TXDA */ - GPIO_PM1_TSPI6RXD = GPIO_FR_6, /*!< PMFR6: TSPI6RXD */ - GPIO_PM1_UT4RXD = GPIO_FR_7, /*!< PMFR7: UT4RXD */ -}gpio_pm1_func_t; - -/** - * @enum gpio_pm2_func_t - * @brief PortM2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM2_T32A11OUTA = GPIO_FR_2, /*!< PMFR2: T32A11OUTA */ - GPIO_PM2_T32A11OUTC = GPIO_FR_3, /*!< PMFR3: T32A11OUTC */ - GPIO_PM2_UT4RTS_N = GPIO_FR_5, /*!< PMFR5: UT4RTS_N */ - GPIO_PM2_TSPI6SCK = GPIO_FR_6, /*!< PMFR6: TSPI6SCK */ - GPIO_PM2_UT4CTS_N = GPIO_FR_7, /*!< PMFR7: UT4CTS_N */ -}gpio_pm2_func_t; - - /** - * @enum gpio_pm3_func_t - * @brief PortM3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM3_INT14b = 0, /*!< 0: INT14b */ - GPIO_PM3_T32A11OUTB = GPIO_FR_2, /*!< PMFR2: T32A11OUTB */ - GPIO_PM3_TSPI6CSIN = GPIO_FR_4, /*!< PMFR4: TSPI6CSIN */ - GPIO_PM3_UT4CTS_N = GPIO_FR_5, /*!< PMFR5: UT4CTS_N */ - GPIO_PM3_TSPI6CS0 = GPIO_FR_6, /*!< PMFR6: TSPI6CS0 */ - GPIO_PM3_UT4RTS_N = GPIO_FR_7, /*!< PMFR7: UT4RTS_N */ -}gpio_pm3_func_t; - - /** - * @enum gpio_pm4_func_t - * @brief PortM4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM4_INT15b = 0, /*!< 0: INT15b */ - GPIO_PM4_T32A06OUTB = GPIO_FR_2, /*!< PMFR2: T32A06OUTB */ - GPIO_PM4_TSPI7CSIN = GPIO_FR_4, /*!< PMFR4: TSPI7CSIN */ - GPIO_PM4_TSPI7CS0 = GPIO_FR_6, /*!< PMFR6: TSPI7CS0 */ - GPIO_PM4_FUT1CTS_N = GPIO_FR_7, /*!< PMFR7: FUT1CTS_N */ -}gpio_pm4_func_t; - -/** - * @enum gpio_pm5_func_t - * @brief PortM5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM5_T32A06OUTA = GPIO_FR_2, /*!< PMFR2: T32A06OUTA */ - GPIO_PM5_T32A06OUTC = GPIO_FR_3, /*!< PMFR3: T32A06OUTC */ - GPIO_PM5_TSPI7SCK = GPIO_FR_6, /*!< PMFR6: TSPI7SCK */ - GPIO_PM5_FUT1RTS_N = GPIO_FR_7, /*!< PMFR7: FUT1RTS_N */ -}gpio_pm5_func_t; - -/** - * @enum gpio_pm6_func_t - * @brief PortM6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM6_T32A07OUTA = GPIO_FR_2, /*!< PMFR2: T32A07OUTA */ - GPIO_PM6_T32A76OUTC = GPIO_FR_3, /*!< PMFR3: T32A07OUTC */ - GPIO_PM6_I2C4SDA = GPIO_FR_4, /*!< PMFR4: I2C4SDA */ - GPIO_PM6_FUT1IRIN = GPIO_FR_5, /*!< PMFR5: FUT1IRIN */ - GPIO_PM6_TSPI7RXD = GPIO_FR_6, /*!< PMFR6: TSPI7RXD */ - GPIO_PM6_FUT1RXD = GPIO_FR_7, /*!< PMFR7: FUT1RXD */ -}gpio_pm6_func_t; - -/** - * @enum gpio_pm7_func_t - * @brief PortM7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PM7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PM7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PM7_T32A07OUTB = GPIO_FR_2, /*!< PMFR2: T32A07OUTB */ - GPIO_PM7_I2C4SCL = GPIO_FR_4, /*!< PMFR4: I2C4SCL */ - GPIO_PM7_FUT1IROUT = GPIO_FR_5, /*!< PMFR5: FUT1IROUT */ - GPIO_PM7_TSPI7TXD = GPIO_FR_6, /*!< PMFR6: TSPI7TXD */ - GPIO_PM7_FUT1TXD = GPIO_FR_7, /*!< PMFR7: FUT1TXD */ -}gpio_pm7_func_t; - -/** - * @enum gpio_pn0_func_t - * @brief PortN0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN0_AINA00 = GPIO_FR_NA, /*!< N/A: AINA00 */ -}gpio_pn0_func_t; - -/** - * @enum gpio_pn1_func_t - * @brief PortN1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN1_AINA01 = GPIO_FR_NA, /*!< N/A: AINA01 */ -}gpio_pn1_func_t; - -/** - * @enum gpio_pn2_func_t - * @brief PortN2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN2_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN2_AINA02 = GPIO_FR_NA, /*!< N/A: AINA02 */ -}gpio_pn2_func_t; - -/** - * @enum gpio_pn3_func_t - * @brief PortN3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN3_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN3_AINA03 = GPIO_FR_NA, /*!< N/A: AINA03 */ -}gpio_pn3_func_t; - - /** - * @enum gpio_pn4_func_t - * @brief PortN4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN4_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN4_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN4_AINA04 = GPIO_FR_NA, /*!< N/A: AINA04 */ -}gpio_pn4_func_t; - -/** - * @enum gpio_pn5_func_t - * @brief PortN5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN5_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN5_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN5_AINA05 = GPIO_FR_NA, /*!< N/A: AINA05 */ -}gpio_pn5_func_t; - -/** - * @enum gpio_pn6_func_t - * @brief PortN6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN6_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN6_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN6_AINA06 = GPIO_FR_NA, /*!< N/A: AINA06 */ -}gpio_pn6_func_t; - -/** - * @enum gpio_pn7_func_t - * @brief PortN7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PN7_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PN7_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PN7_AINA07 = GPIO_FR_NA, /*!< N/A: AINA07 */ -}gpio_pn7_func_t; - -/** - * @enum gpio_pp0_func_t - * @brief PortP0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP0_AINA08 = 0, /*!< 0: AINA08 */ - GPIO_PP0_T32A04INA0 = GPIO_FR_2, /*!< PPFR2: T32A04INA0 */ - GPIO_PP0_T32A04INC0 = GPIO_FR_3, /*!< PPFR3: T32A04INC0 */ - GPIO_PP0_T32A04INB1 = GPIO_FR_5, /*!< PPFR5: T32A04INB1 */ -}gpio_pp0_func_t; - -/** - * @enum gpio_pp1_func_t - * @brief PortP1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP1_AINA09 = 0, /*!< 0: AINA09 */ - GPIO_PP1_T32A04INB0 = GPIO_FR_2, /*!< PPFR2: T32A04INB0 */ - GPIO_PP1_T32A04INC1 = GPIO_FR_3, /*!< PPFR3: T32A04INC1 */ - GPIO_PP1_T32A04INA1 = GPIO_FR_5, /*!< PPFR5: T32A04INA1 */ -}gpio_pp1_func_t; - -/** - * @enum gpio_pp2_func_t - * @brief PortP2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP2_AINA10 = 0, /*!< 0: AINA10 */ - GPIO_PP2_T32A05INA0 = GPIO_FR_2, /*!< PPFR2: T32A05INA0 */ - GPIO_PP2_T32A05INC0 = GPIO_FR_3, /*!< PPFR3: T32A05INC0 */ - GPIO_PP2_T32A05INB1 = GPIO_FR_5, /*!< PPFR5: T32A05INB1 */ -}gpio_pp2_func_t; - - /** - * @enum gpio_pp3_func_t - * @brief PortP3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP3_AINA11 = 0, /*!< 0: AINA11 */ - GPIO_PP3_T32A05INB0 = GPIO_FR_2, /*!< PPFR2: T32A05INB0 */ - GPIO_PP3_T32A05INC1 = GPIO_FR_3, /*!< PPFR3: T32A05INC1 */ - GPIO_PP3_T32A05INA1 = GPIO_FR_5, /*!< PPFR5: T32A05INA1 */ -}gpio_pp3_func_t; - - /** - * @enum gpio_pp4_func_t - * @brief PortP4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP4_AINA12 = 0, /*!< 0: AINA12 */ - GPIO_PP4_T32A06INA0 = GPIO_FR_2, /*!< PPFR2: T32A06INA0 */ - GPIO_PP4_T32A06INC0 = GPIO_FR_3, /*!< PPFR3: T32A06INC0 */ - GPIO_PP4_T32A06INB1 = GPIO_FR_5, /*!< PPFR5: T32A06INB1 */ -}gpio_pp4_func_t; - - /** - * @enum gpio_pp5_func_t - * @brief PortP5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP5_AINA13 = 0, /*!< 0: AINA13 */ - GPIO_PP5_T32A06INB0 = GPIO_FR_2, /*!< PPFR2: T32A06INB0 */ - GPIO_PP5_T32A06INC1 = GPIO_FR_3, /*!< PPFR3: T32A06INC1 */ - GPIO_PP5_T32A06INA1 = GPIO_FR_5, /*!< PPFR5: T32A06INA1 */ -}gpio_pp5_func_t; - -/** - * @enum gpio_pp6_func_t - * @brief PortP6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP6_AINA14 = 0, /*!< 0: AINA14 */ - GPIO_PP6_INT10b = 0, /*!< 0: INT10b */ - GPIO_PP6_T32A07INA0 = GPIO_FR_2, /*!< PPFR2: T32A07INA0 */ - GPIO_PP6_T32A07INC0 = GPIO_FR_3, /*!< PPFR3: T32A07INC0 */ - GPIO_PP6_T32A07INB1 = GPIO_FR_5, /*!< PPFR5: T32A07INB1 */ -}gpio_pp6_func_t; - - /** - * @enum gpio_pp7_func_t - * @brief PortP7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PP7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PP7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PP7_AINA15 = 0, /*!< 0: AINA15 */ - GPIO_PP7_INT11b = 0, /*!< 0: INT11b */ - GPIO_PP7_T32A07INB0 = GPIO_FR_2, /*!< PPFR2: T32A07INB0 */ - GPIO_PP7_T32A07INC1 = GPIO_FR_3, /*!< PPFR3: T32A07INC1 */ - GPIO_PP7_T32A07INA1 = GPIO_FR_5, /*!< PPFR5: T32A07INA1 */ -}gpio_pp7_func_t; - -/** - * @enum gpio_pr0_func_t - * @brief PortR0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR0_AINA16 = 0, /*!< 0: AINA16 */ - GPIO_PR0_T32A08INA0 = GPIO_FR_2, /*!< PRFR2: T32A08INA0 */ - GPIO_PR0_T32A08INC0 = GPIO_FR_3, /*!< PRFR3: T32A08INC0 */ -}gpio_pr0_func_t; - -/** - * @enum gpio_pr1_func_t - * @brief PortR1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR1_AINA17 = 0, /*!< 0: AINA17 */ - GPIO_PR1_T32A08INB0 = GPIO_FR_2, /*!< PRFR2: T32A08INB0 */ - GPIO_PR1_T32A08INC1 = GPIO_FR_3, /*!< PRFR3: T32A08INC1 */ -}gpio_pr1_func_t; - -/** - * @enum gpio_pr2_func_t - * @brief PortR2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR2_AINA18 = 0, /*!< 0: AINA18 */ - GPIO_PR2_T32A09INA0 = GPIO_FR_2, /*!< PRFR2: T32A09INA0 */ - GPIO_PR2_T32A09INC0 = GPIO_FR_3, /*!< PRFR3: T32A09INC0 */ -}gpio_pr2_func_t; - -/** - * @enum gpio_pr3_func_t - * @brief PortR3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR3_AINA19 = 0, /*!< 0: AINA19 */ - GPIO_PR3_T32A09INB0 = GPIO_FR_2, /*!< PRFR2: T32A09INB0 */ - GPIO_PR3_T32A09INC1 = GPIO_FR_3, /*!< PRFR3: T32A09INC1 */ -}gpio_pr3_func_t; - -/** - * @enum gpio_pr4_func_t - * @brief PortR4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR4_AINA20 = 0, /*!< 0: AINA20 */ - GPIO_PR4_T32A10INA0 = GPIO_FR_2, /*!< PRFR2: T32A10INA0 */ - GPIO_PR4_T32A10INC0 = GPIO_FR_3, /*!< PRFR3: T32A10INC0 */ -}gpio_pr4_func_t; - -/** - * @enum gpio_pr5_func_t - * @brief PortR5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR5_AINA21 = 0, /*!< 0: AINA21 */ - GPIO_PR5_T32A10INB0 = GPIO_FR_2, /*!< PRFR2: T32A10INB0 */ - GPIO_PR5_T32A10INC1 = GPIO_FR_3, /*!< PRFR3: T32A10INC1 */ -}gpio_pr5_func_t; - -/** - * @enum gpio_pr6_func_t - * @brief PortR6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR6_AINA22 = 0, /*!< 0: AINA22 */ - GPIO_PR6_T32A11INA0 = GPIO_FR_2, /*!< PRFR2: T32A11INA0 */ - GPIO_PR6_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC0 */ -}gpio_pr6_func_t; - -/** - * @enum gpio_pr7_func_t - * @brief PortR7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PR7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PR7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PR7_AINA23 = 0, /*!< 0: AINA23 */ - GPIO_PR7_T32A11INB0 = GPIO_FR_2, /*!< PRFR2: T32A11INB0 */ - GPIO_PR7_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC1 */ -}gpio_pr7_func_t; - - -/** - * @enum gpio_pt0_func_t - * @brief PortT0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PT0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PT0_DAC0 = GPIO_FR_NA, /*!< N/A: DAC0 */ -}gpio_pt0_func_t; - -/** - * @enum gpio_pt1_func_t - * @brief PortT1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PT1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ - GPIO_PT1_DAC1 = GPIO_FR_NA, /*!< N/A: DAC1 */ -}gpio_pt1_func_t; - -/** - * @enum gpio_pt2_func_t - * @brief PortT2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PT2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PT2_CEC0 = GPIO_FR_7, /*!< PTFR1: CEC0 Input/Output */ -}gpio_pt2_func_t; - -/** - * @enum gpio_pt3_func_t - * @brief PortT3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PT3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PT3_INT00b = 0, /*!< 0: INT00b */ - GPIO_PT3_RTCCLK = GPIO_FR_1, /*!< PTFR1: RTCCLK */ - GPIO_PT3_T32A03OUTA = GPIO_FR_2, /*!< PTFR2: T32A03OUTA */ - GPIO_PT3_T32A03OUTC = GPIO_FR_3, /*!< PTFR3: T32A03OUTC */ - GPIO_PT3_RXIN0 = 0, /*!< 0: RXIN0 */ - GPIO_PT3_MDMAREQA = GPIO_FR_6, /*!< PTFR6: MDMAREQA */ -}gpio_pt3_func_t; - -/** - * @enum gpio_pt4_func_t - * @brief PortT4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PT4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PT4_INT01b = 0, /*!< 0: INT01b */ - GPIO_PT4_RXIN1 = 0, /*!< 0: RXIN1 */ -}gpio_pt4_func_t; - -/** - * @enum gpio_pt5_func_t - * @brief PortT5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PT5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PT5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PT5_INT02b = 0, /*!< 0: INT02b */ - GPIO_PT5_T32A03OUTB = GPIO_FR_2, /*!< PTFR2: T32A03OUTB */ -}gpio_pt5_func_t; - -/** - * @enum gpio_pu0_func_t - * @brief PortU0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU0_T32A12OUTA = GPIO_FR_2, /*!< PUFR2: T32A12OUTA */ - GPIO_PU0_T32A12OUTC = GPIO_FR_3, /*!< PUFR3: T32A12OUTC */ - GPIO_PU0_UT4TXDA = GPIO_FR_7, /*!< PUFR7: UT4TXDA */ -}gpio_pu0_func_t; - -/** - * @enum gpio_pu1_func_t - * @brief PortU1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU1_T32A12OUTB = GPIO_FR_2, /*!< PUFR2: T32A12OUTB */ - GPIO_PU1_UT4RXD = GPIO_FR_7, /*!< PUFR7: UT4RXD */ -}gpio_pu1_func_t; - -/** - * @enum gpio_pu2_func_t - * @brief PortU2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU2_INT06b = 0, /*!< 0: INT06b */ - GPIO_PU2_T32A12INA0 = GPIO_FR_2, /*!< PUFR2: T32A12INA0 */ - GPIO_PU2_T32A12INC0 = GPIO_FR_3, /*!< PUFR3: T32A12INC0 */ - GPIO_PU2_UT4CTS_N = GPIO_FR_7, /*!< PUFR7: UT4CTS_N */ -}gpio_pu2_func_t; - -/** - * @enum gpio_pu3_func_t - * @brief PortU3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU3_INT07b = 0, /*!< 0: INT07b */ - GPIO_PU3_T32A12INB0 = GPIO_FR_2, /*!< PUFR2: T32A12INB0 */ - GPIO_PU3_T32A12INC1 = GPIO_FR_3, /*!< PUFR3: T32A12INC1 */ - GPIO_PU3_UT4RTS_N = GPIO_FR_7, /*!< PUFR7: UT4RTS_N */ -}gpio_pu3_func_t; - -/** - * @enum gpio_pu4_func_t - * @brief PortU4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU4_INT08b = 0, /*!< 0: INT08b */ - GPIO_PU4_T32A13INB0 = GPIO_FR_2, /*!< PUFR2: T32A13INB0 */ - GPIO_PU4_T32A13INC1 = GPIO_FR_3, /*!< PUFR3: T32A13INC1 */ - GPIO_PU4_UT3RTS_N = GPIO_FR_7, /*!< PUFR7: UT3RTS_N */ -}gpio_pu4_func_t; - -/** - * @enum gpio_pu5_func_t - * @brief PortU5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU5_INT09b = 0, /*!< 0: INT09b */ - GPIO_PU5_T32A13INA0 = GPIO_FR_2, /*!< PUFR2: T32A13INA0 */ - GPIO_PU5_T32A13INC0 = GPIO_FR_3, /*!< PUFR3: T32A13INC0 */ - GPIO_PU5_UT3CTS_N = GPIO_FR_7, /*!< PUFR7: UT3CTS_N */ -}gpio_pu5_func_t; - -/** - * @enum gpio_pu6_func_t - * @brief PortU6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU6_T32A13OUTA = GPIO_FR_2, /*!< PUFR2: T32A13OUTA */ - GPIO_PU6_T32A13OUTC = GPIO_FR_3, /*!< PUFR3: T32A13OUTC */ - GPIO_PU6_UT3RXD = GPIO_FR_7, /*!< PUFR7: UT3RXD */ -}gpio_pu6_func_t; - -/** - * @enum gpio_pu7_func_t - * @brief PortU7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PU7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PU7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PU7_T32A13OUTB = GPIO_FR_2, /*!< PUFR2: T32A13OUTB */ - GPIO_PU7_UT3TXDA = GPIO_FR_7, /*!< PUFR7: UT3TXDA */ -}gpio_pu7_func_t; - -/** - * @enum gpio_pv0_func_t - * @brief PortV0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV0_T32A09INA0 = GPIO_FR_2, /*!< PVFR2: T32A09INA0 */ - GPIO_PV0_T32A09INC0 = GPIO_FR_3, /*!< PVFR3: T32A09INC0 */ - GPIO_PV0_ISDBIN0 = 0, /*!< 0: ISDBIN0 */ - GPIO_PV0_UO0 = GPIO_FR_5, /*!< PVFR5: UO0 */ - GPIO_PV0_UT3RXD = GPIO_FR_6, /*!< PVFR6: UT3RXD */ - GPIO_PV0_UT3TXDA = GPIO_FR_7, /*!< PVFR7: UT3TXDA */ -}gpio_pv0_func_t; - -/** - * @enum gpio_pv1_func_t - * @brief PortV1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV1_T32A09INB0 = GPIO_FR_2, /*!< PVFR2: T32A09INB0 */ - GPIO_PV1_T32A09INC1 = GPIO_FR_3, /*!< PVFR3: T32A09INC1 */ - GPIO_PV1_ISDBIN1 = 0, /*!< 0: ISDBIN1 */ - GPIO_PV1_XO0 = GPIO_FR_5, /*!< PVFR5: XO0 */ - GPIO_PV1_UT3TXDA = GPIO_FR_6, /*!< PVFR6: UT3TXDA */ - GPIO_PV1_UT3RXD = GPIO_FR_7, /*!< PVFR7: UT3RXD */ -}gpio_pv1_func_t; - -/** - * @enum gpio_pv2_func_t - * @brief PortV2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV2_T32A09OUTA = GPIO_FR_2, /*!< PVFR2: T32A09OUTA */ - GPIO_PV2_T32A09OUTC = GPIO_FR_3, /*!< PVFR3: T32A09OUTC */ - GPIO_PV2_ISDBIN2 = 0, /*!< 0: ISDBIN2 */ - GPIO_PV2_VO0 = GPIO_FR_5, /*!< PVFR5: VO0 */ - GPIO_PV2_UT3RTS_N = GPIO_FR_6, /*!< PVFR6: UT3RTS_N */ - GPIO_PV2_UT3CTS_N = GPIO_FR_7, /*!< PVFR7: UT3CTS_N */ -}gpio_pv2_func_t; - -/** - * @enum gpio_pv3_func_t - * @brief PortV3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV3_T32A09OUTB = GPIO_FR_2, /*!< PVFR2: T32A09OUTB */ - GPIO_PV3_ISDBIN3 = 0, /*!< 0: ISDBIN3 */ - GPIO_PV3_YO0 = GPIO_FR_5, /*!< PVFR5: YO0 */ - GPIO_PV3_UT3CTS_N = GPIO_FR_6, /*!< PVFR6: UT3CTS_N */ - GPIO_PV3_UT3RTS_N = GPIO_FR_7, /*!< PVFR7: UT3RTS_N */ -}gpio_pv3_func_t; - -/** - * @enum gpio_pv4_func_t - * @brief PortV4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV4_T32A04OUTB = GPIO_FR_2, /*!< PVFR2: T32A04OUTB */ - GPIO_PV4_TSPI5RXD = GPIO_FR_4, /*!< PVFR4: TSPI5RXD */ - GPIO_PV4_WO0 = GPIO_FR_5, /*!< PVFR5: WO0 */ - GPIO_PV4_I2C2SCL = GPIO_FR_6, /*!< PVFR6: I2C2SCL */ - GPIO_PV4_UT1RXD = GPIO_FR_7, /*!< PVFR7: UT1RXD */ -}gpio_pv4_func_t; - -/** - * @enum gpio_pv5_func_t - * @brief PortV5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV5_T32A04OUTA = GPIO_FR_2, /*!< PVFR2: T32A04OUTA */ - GPIO_PV5_T32A04OUTC = GPIO_FR_3, /*!< PVFR3: T32A04OUTC */ - GPIO_PV5_TSPI5TXD = GPIO_FR_4, /*!< PVFR4: TSPI5TXD */ - GPIO_PV5_ZO0 = GPIO_FR_5, /*!< PVFR5: ZO0 */ - GPIO_PV5_I2CSDA = GPIO_FR_6, /*!< PVFR6: I2CSDA */ - GPIO_PV5_UT1TXDA = GPIO_FR_7, /*!< PVFR7: UT1TXDA */ -}gpio_pv5_func_t; - -/** - * @enum gpio_pv6_func_t - * @brief PortV6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV6_T32A05OUTA = GPIO_FR_2, /*!< PVFR2: T32A05OUTA */ - GPIO_PV6_T32A05OUTC = GPIO_FR_3, /*!< PVFR3: T32A05OUTC */ - GPIO_PV6_TSPI5SCK = GPIO_FR_4, /*!< PVFR4: TSPI5SCK */ - GPIO_PV6_EMG0_N = GPIO_FR_5, /*!< PVFR5: EMG0_N */ - GPIO_PV6_UT1CTS_N = GPIO_FR_7, /*!< PVFR7: UT1CTS_N */ -}gpio_pv6_func_t; - -/** - * @enum gpio_pv7_func_t - * @brief PortV7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PV7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PV7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PV7_T32A05OUTB = GPIO_FR_2, /*!< PVFR2: T32A05OUTB */ - GPIO_PV7_TSPI5CS0 = GPIO_FR_4, /*!< PVFR4: TSPI5CS0 */ - GPIO_PV7_OVV0_N = GPIO_FR_5, /*!< PVFR5: OVV0_N */ - GPIO_PV7_TSPI5CSIN = GPIO_FR_6, /*!< PVFR6: TSPI5CSIN */ - GPIO_PV7_UT1RTS_N = GPIO_FR_7, /*!< PVFR7: UT1RTS_N */ -}gpio_pv7_func_t; - -/** - * @enum gpio_pw0_func_t - * @brief PortW0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW0_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW0_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW0_TSPI8CS0 = GPIO_FR_4, /*!< PWFR4: TSPI8CS0 */ - GPIO_PW0_T32A00OUTB = GPIO_FR_5, /*!< PWFR5: T32A00OUTB */ - GPIO_PW0_TSPI8CSIN = GPIO_FR_6, /*!< PWFR6: TSPI8CSIN */ -}gpio_pw0_func_t; - -/** - * @enum gpio_pw1_func_t - * @brief PortW1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW1_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW1_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW1_TSPI8SCK = GPIO_FR_4, /*!< PWFR4: TSPI8SCK */ - GPIO_PW1_T32A00OUTA = GPIO_FR_5, /*!< PWFR5: T32A00OUTA */ - GPIO_PW1_T32A00OUTC = GPIO_FR_7, /*!< PWFR7: T32A00OUTC */ -}gpio_pw1_func_t; - -/** - * @enum gpio_pw2_func_t - * @brief PortW2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW2_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW2_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW2_TSPI8RXD = GPIO_FR_4, /*!< PWFR4: TSPI8RXD */ - GPIO_PW2_T32A01OUTA = GPIO_FR_5, /*!< PWFR5: T32A01OUTA */ - GPIO_PW2_T32A01OUTC = GPIO_FR_7, /*!< PWFR7: T32A01OUTC */ -}gpio_pw2_func_t; - -/** - * @enum gpio_pw3_func_t - * @brief PortW3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW3_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW3_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW3_TSPI8TXD = GPIO_FR_4, /*!< PWFR4: TSPI8TXD */ - GPIO_PW3_T32A01OUTB = GPIO_FR_5, /*!< PWFR5: T32A01OUTB */ -}gpio_pw3_func_t; - -/** - * @enum gpio_pw4_func_t - * @brief PortW4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW4_T32A11INA1 = GPIO_FR_3, /*!< PWFR3: T32A11INA1 */ - GPIO_PW4_T32A10OUTB = GPIO_FR_5, /*!< PWFR5: T32A10OUTB */ - GPIO_PW4_ISDCIN0 = 0, /*!< 0: ISDCIN0 */ - GPIO_PW4_T32A10INA0 = GPIO_FR_7, /*!< PWFR7: T32A10INA0 */ -}gpio_pw4_func_t; - -/** - * @enum gpio_pw5_func_t - * @brief PortW5 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW5_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW5_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW5_T32A10OUTA = GPIO_FR_5, /*!< PWFR5: T32A10OUTA */ - GPIO_PW5_ISDCIN1 = 0, /*!< 0: ISDCIN1 */ - GPIO_PW5_T32A10OUTC = GPIO_FR_7, /*!< PWFR7: T32A10OUTC */ -}gpio_pw5_func_t; - -/** - * @enum gpio_pw6_func_t - * @brief PortW6 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW6_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW6_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW6_T32A11OUTA = GPIO_FR_5, /*!< PWFR5: T32A11OUTA */ - GPIO_PW6_ISDCIN2 = 0, /*!< 0: ISDCIN2 */ - GPIO_PW6_T32A11OUTC = GPIO_FR_7, /*!< PWFR7: T32A11OUTC */ -}gpio_pw6_func_t; - -/** - * @enum gpio_pw7_func_t - * @brief PortW7 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PW7_INPUT = 0, /*!< 0: Input Port */ - GPIO_PW7_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PW7_T32A10INA1 = GPIO_FR_3, /*!< PWFR3: T32A10INA1 */ - GPIO_PW7_T32A11OUTB = GPIO_FR_5, /*!< PWFR5: T32A11OUTB */ - GPIO_PW7_ISDCIN3 = 0, /*!< 0: ISDCIN3 */ - GPIO_PW7_T32A11INA0 = GPIO_FR_7, /*!< PWFR7: T32A11INA0 */ -}gpio_pw7_func_t; - -/** - * @enum gpio_py0_func_t - * @brief PortY0 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PY0_X1 = GPIO_FR_NA, /*!< N/A: X1 */ -}gpio_py0_func_t; - -/** - * @enum gpio_py1_func_t - * @brief PortY1 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PY1_X2 = GPIO_FR_NA, /*!< N/A: X2 */ -}gpio_py1_func_t; - -/** - * @enum gpio_py2_func_t - * @brief PortY2 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PY2_XT1 = GPIO_FR_NA, /*!< N/A: XT1 */ -}gpio_py2_func_t; - -/** - * @enum gpio_py3_func_t - * @brief PortY3 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ - GPIO_PY3_XT2 = GPIO_FR_NA, /*!< N/A: XT2 */ -}gpio_py3_func_t; - -/** - * @enum gpio_py4_func_t - * @brief PortY4 Function Enumerated Type Definition. - */ -typedef enum -{ - GPIO_PY4_INPUT = 0, /*!< 0: Input Port */ - GPIO_PY4_OUTPUT = 0, /*!< 0: Output Port */ - GPIO_PY4_ISDCOUT = GPIO_FR_1, /*!< PYFR1: ISDCOUT */ - GPIO_PY4_EEXBCLK = GPIO_FR_4, /*!< PYFR4: EEXBCLK */ -}gpio_py4_func_t; - -/** - * @} - */ /* End of group GPIO_Exported_Typedef */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief GPIO handle structure definenition. -*/ -/*----------------------------------*/ -#if defined(TMPM4G6) -typedef struct gpio_pa_handle -{ - TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ - TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ - TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ - TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ - TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ - TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ - TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ - TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ - TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ - TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ - TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ - TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ - TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ -} _gpio_t; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) -typedef struct gpio_pa_handle -{ - TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ - TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ - TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ - TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ - TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ - TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ - TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ - TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ - TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ - TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ - TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ - TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ - TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ - TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ - TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ - TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ -} _gpio_t; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) -typedef struct gpio_pa_handle -{ - TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ - TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ - TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ - TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ - TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ - TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ - TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ - TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ - TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ - TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ - TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ - TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ - TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ - TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ - TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ - TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ - TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ -} _gpio_t; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) -typedef struct gpio_pa_handle -{ - TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ - TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ - TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ - TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ - TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ - TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ - TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ - TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ - TSB_PJ_TypeDef *p_pj_instance; /*!< Registers base address. */ - TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ - TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ - TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ - TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ - TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ - TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ - TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ - TSB_PU_TypeDef *p_pu_instance; /*!< Registers base address. */ - TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ - TSB_PW_TypeDef *p_pw_instance; /*!< Registers base address. */ - TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ -} _gpio_t; -#endif /* TMPM4G9 */ - -/** - * @} - */ /* End of group GPIO_Exported_Typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Exported_functions GPIO Exported Functions - * @{ - */ -TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group); -TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group); -TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val); -TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val); -TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout); -TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); -TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); -TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); -TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val); -TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate); - -/** - * @} - */ /* End of group GPIO_Exported_functions */ - -/** - * @} - */ /* End of group GPIO */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __GPIO_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_hal.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_hal.h deleted file mode 100644 index 0828e9f586e..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_hal.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - ******************************************************************************* - * @file txz_hal.h - * @brief This file provides all the functions prototypes for driver common part. - * @version V1.0.0.0 - * $Date:: 2017-08-09 11:01:04 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __HAL_H -#define __HAL_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup HAL HAL - * @brief HAL Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_macro HAL Exported Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Exported_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_define HAL Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_define HAL Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_typedef HAL Exported Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Exported_functions HAL Exported Functions - * @{ - */ - -void hal_inc_tick(void); -uint32_t hal_get_tick(void); - - -/** - * @} - */ /* End of group HAL_Exported_functions */ - -/** - * @} - */ /* End of group HAL */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __HAL_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c.h deleted file mode 100644 index 5150ea196c8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c.h +++ /dev/null @@ -1,843 +0,0 @@ -/** - ******************************************************************************* - * @file txz_i2c.h - * @brief This file provides all the functions prototypes for I2C Class. - * @version V1.0.0.4 - * $Date:: 2016-11-24 00:00:00 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __I2C_H -#define __I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -#ifdef DEBUG -/** - * @name I2C_NULL Pointer - * @brief NULL Pointer. - * @{ - */ -#define I2C_NULL ((void *)0) -/** - * @} - */ /* End of name I2C_NULL Pointer */ -#endif - -/** - * @name I2CxST Macro Definition. - * @brief I2CxST Register Macro Definition. - * @{ - */ -#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */ -#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */ -#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */ -#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */ -#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */ -/** - * @} - */ /* End of name I2CxST Macro Definition */ - -/** - * @name I2CxCR1 Macro Definition. - * @brief I2CxCR1 Register Macro Definition. - * @{ - */ -#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */ -#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */ -#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */ - -/** - * @} - */ /* End of name I2CxCR1 Macro Definition */ - -/** - * @name I2CxDBR Macro Definition. - * @brief I2CxDBR Register Macro Definition. - * @{ - */ -#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ -/** - * @} - */ /* End of name I2CxDBR Macro Definition */ - - -/** - * @name I2CxCR2 Macro Definition. - * @brief I2CxCR2 Register Macro Definition. - * @{ - */ -#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */ -#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */ -#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */ -#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */ -#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */ -#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */ -#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */ -#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */ - -/** - * @} - */ /* End of name I2CxCR2 Macro Definition */ - -/** - * @name I2CxSR Macro Definition. - * @brief I2CxSR Register Macro Definition. - * @{ - */ -#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */ -#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */ -#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */ -#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */ -#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ -#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */ -#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */ -#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */ -/** - * @} - */ /* End of name I2CxSR Macro Definition */ - -/** - * @name I2CxPRS Macro Definition. - * @brief I2CxPRS Register Macro Definition. - * @{ - */ -#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */ -/** - * @} - */ /* End of name I2CxPRS Macro Definition */ - -/** - * @name I2CxIE Macro Definition. - * @brief I2CxIE Register Macro Definition. - * @{ - */ -#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */ -#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */ -#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */ -#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */ -#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */ - -/** - * @} - */ /* End of name I2CxIE Macro Definition */ - - -/** - * @name I2CxOP Macro Definition. - * @brief I2CxOP Register Macro Definition. - * @{ - */ -#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */ -#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */ -#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */ -#define I2CxOP_NFSEL ((uint32_t)0x00000010) /*!< NFSEL */ -#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */ -#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */ -#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */ -#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */ -#ifndef I2C_MULTI_MASTER - #define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */ -#else - #define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */ -#endif -#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */ -/** - * @} - */ /* End of name I2CxOP Macro Definition */ - -/** - * @name I2CxAR Macro Definition. - * @brief I2CxAR Register Macro Definition. - * @{ - */ -#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */ -#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ -#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ - -/** - * @} - */ /* End of name I2CxAR Macro Definition */ - - -/** - * @name I2CxPM Macro Definition. - * @brief I2CxPM Register Macro Definition. - * @{ - */ -#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ -/** - * @} - */ /* End of name I2CxPM Macro Definition */ - -/** - * @name I2CxWUPCR_INT Macro Definition. - * @brief I2CxWUPCR_INT Register Macro Definition. - * @{ - */ -#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ -#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ -/** - * @} - */ /* End of name I2CxWUPCR_INT Macro Definition */ - -/** - * @name I2CxWUPCR_RST Macro Definition. - * @brief I2CxWUPCR_RST Register Macro Definition. - * @{ - */ -#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ -#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ -/** - * @} - */ /* End of name I2CxWUPCR_RST Macro Definition */ - - -/** - * @name I2CxWUPCR_ACK Macro Definition. - * @brief I2CxWUPCR_ACK Register Macro Definition. - * @{ - */ -#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ -#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ -/** - * @} - */ /* End of name I2CxWUPCR_RST Macro Definition */ -/** - * @} - */ /* End of group UTILITIES_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_typedef - * @{ - */ - -/*----------------------------------*/ -/** - * @brief Clock setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t sck; /*!< Select internal SCL output clock frequency. */ - uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */ -} I2C_clock_setting_t; - -/*----------------------------------*/ -/** - * @brief Wakeup Control setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t sgcdi; /*!< Select general call detect ON/OFF. */ - uint32_t ack; /*!< Select ACK output. */ - uint32_t reset; /*!< I2C BUS Rest. */ - uint32_t intend; /*!< Interrupt release. */ -} I2CS_wup_setting_t; - -/*----------------------------------*/ -/** - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - I2C_clock_setting_t clock; /*!< Serial clock setting. */ -} I2C_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */ -} I2CS_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief I2C handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */ - I2C_initial_setting_t init; /*!< Initial setting. */ -} I2C_t; -#if defined(I2CSxWUP_EN) -/*----------------------------------*/ -/** - * @brief I2CS handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */ - I2CS_initial_setting_t init; /*!< Initial setting. */ -} I2CS_t; -#endif -/** - * @} - */ /* End of group UTILITIES_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Inline Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ -__STATIC_INLINE void I2C_reset(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj); -__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj); -__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj); -__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data); -__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj); -__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack); -__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj); -__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj); -__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj); -__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj); -__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx); -__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj); -__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr); -__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj); - -/*--------------------------------------------------*/ -/** - * @brief I2C software reset. - * @param p_obj :I2C object. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_reset(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; - p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; - } -#else - p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; - p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief I2C bus port high - * @param p_obj :I2C object. - * @retval true :SDA and SCL Port High. - * @retval false :Bus Error. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); - } - return (0); -#else - return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Generate stop condition. - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; - } -#else - p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Read from Data buffer - * @param p_obj :I2C object. - * @retval result :Read data. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); - } - return (0); -#else - return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Write to Data buffer. - * @param p_obj :I2C object. - * @param data :Write data. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); - } -#else - p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return restart condition - * @param p_obj :I2C object. - * @retval true :Restart Detected. - * @retval false :Restart Non-Detected. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - __IO uint32_t opreg = p_obj->p_instance->OP; - p_obj->p_instance->OP &= ~I2CxOP_RSTA; - return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); - } - return (0); -#else - __IO uint32_t opreg = p_obj->p_instance->OP; - p_obj->p_instance->OP &= ~I2CxOP_RSTA; - return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Set Ack condition - * @param p_obj :I2C object. - * @param nack :1 NACK, 0 ACK. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - if (nack) - { - p_obj->p_instance->OP |= I2CxOP_MFACK; - } - else - { - p_obj->p_instance->OP &= ~I2CxOP_MFACK; - } - } -#else - if (nack) - { - p_obj->p_instance->OP |= I2CxOP_MFACK; - } - else - { - p_obj->p_instance->OP &= ~I2CxOP_MFACK; - } -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return received Ack condition - * @param p_obj :I2C object. - * @retval true :NACK Received. - * @retval false :ACK Received. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return Busy condition - * @param p_obj :I2C object. - * @retval true :I2C bus busy. - * @retval false :I2C bus free. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return The Master status - * @param p_obj :I2C object. - * @retval true :Master mode. - * @retval false :Slave mode. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Return The Transmitter - * @param p_obj :I2C object. - * @retval true :Transmitter. - * @retval false :Receiver. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Interrupt Status - * @param p_obj :I2C object. - * @retval true :Interruput Occured. - * @retval false :No Interruput Occured. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); - } - return (0); -#else - return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Interrupt Status Clear - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->ST = I2CxST_CLEAR; - } -#else - p_obj->p_instance->ST = I2CxST_CLEAR; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable Interrupt setting. - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->IE = I2CxIE_I2C; - } -#else - p_obj->p_instance->IE = I2CxIE_I2C; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable Interrupt setting. - * @param p_obj :I2C object. - * @param tx :Direction of transfer(1=tx 0=rx). - * @retval - - * @note For DMA transfer. - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - if (tx) - { - p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); - } - else - { - p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); - } - } -#else - if (tx) - { - p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); - } - else - { - p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); - } -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Disable Interrupt setting. - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->IE = I2CxIE_CLEAR; - } -#else - p_obj->p_instance->IE = I2CxIE_CLEAR; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Set slave address. - * @param p_obj :I2C object. - * @param addr :slave address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); - p_obj->p_instance->AR2 = I2CxAR2_INIT; - } -#else - p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); - p_obj->p_instance->AR2 = I2CxAR2_INIT; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Detecting Slave Address - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) - && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); - } - return (0); -#else - return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) - && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); -#endif -} - -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ -void I2C_init(I2C_t *p_obj); -void I2C_start_condition(I2C_t *p_obj, uint32_t data); -uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting); -void I2C_slave_init(I2C_t *p_obj); -#if defined(I2CSxWUP_EN) -void I2CS_init(I2CS_t *p_obj); -void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); -void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); -#endif -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/** - * @} - */ /* End of group UTILITIES */ - -/** - * @} - */ /* End of group Example */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __I2C_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c_api.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c_api.h deleted file mode 100644 index bc7c862515e..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_i2c_api.h +++ /dev/null @@ -1,311 +0,0 @@ -/** - ******************************************************************************* - * @file bsp_i2c.h - * @brief This file provides all the functions prototypes for I2C Driver. - * @version V1.0.0.2 - * $Date:: 2017-10-03 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __BSP_I2C_H -#define __BSP_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_i2c.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Exported_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_define - * @{ - */ -/** - * @defgroup I2C_NullPointer Null Pointer - * @brief I2C NULL Pointer. - * @{ - */ -#define I2C_NULL ((void *)0) -/** - * @} - */ /* End of group I2C_NullPointer */ - -/** - * @} - */ /* End of group UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_define - * @{ - */ - -/** - * @defgroup I2C_ACK I2C ACK Macros - * @brief I2C Type of Acknowledge. - * @{ - */ -#define I2C_NACK (0) /*!< NACK Received. */ -#define I2C_ACK (1) /*!< ACK Received. */ -/** - * @} - */ /* End of group I2C_ACK */ - - -/** - * @defgroup I2C_ERROR I2C ERROR Macros - * @brief I2C Error definitions. - * @{ - */ -#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */ -#if 0 -#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */ -#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */ -#endif -#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */ -#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */ -#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */ -/** - * @} - */ /* End of group I2C_ERROR */ - - -/** - * @defgroup I2C_Events I2C Events Macros - * @brief I2C Asynch Events. - * @{ - */ -#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */ -#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */ -#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */ -#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */ -#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK) -/** - * @} - */ /* End of group I2C_Events */ - -/** - * @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros - * @brief I2C Received Contents of Slave. - * @{ - */ -#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */ -#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */ -#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */ -#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */ -/** - * @} - */ /* End of group I2C_SlaveReceive */ - -/** - * @} - */ /* End of group UTILITIES_Exported_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_define - * @{ - */ - -/*----------------------------------*/ -/** - * @brief i2c Port Enumerated Type Definition. -*/ -/*----------------------------------*/ -typedef enum { - I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */ - I2C_PORT_PG3, /*!< 1: PG3 I2C0 */ - I2C_PORT_PF2, /*!< 2: PF2 I2C1 */ - I2C_PORT_PF3, /*!< 3: PF3 I2C1 */ - I2C_PORT_PG4, /*!< 4: PG4 I2C2 */ - I2C_PORT_PG5, /*!< 5: PG5 I2C2 */ - I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */ - I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */ - I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */ - I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */} -i2c_port_t; - -/*----------------------*/ -/* I2C Setting */ -/*----------------------*/ -/* #define I2C_CHANNEL0 */ -#define I2C_CHANNEL3 -/* #define I2C_CHANNEL2 */ -/* #define I2C_CHANNEL3 */ -/* #define I2C_CHANNEL4 */ -#if defined(I2C_CHANNEL0) - #define I2Cx_TEXT "I2C0" - #define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */ -#elif defined(I2C_CHANNEL1) - #define I2Cx_TEXT "I2C1" - #define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */ -#elif defined(I2C_CHANNEL2) - #define I2Cx_TEXT "I2C2" - #define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */ -#elif defined(I2C_CHANNEL3) - #define I2Cx_TEXT "I2C3" - #define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */ -#elif defined(I2C_CHANNEL4) - #define I2Cx_TEXT "I2C4" - #define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */ - #define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */ -#else - #error "target channel is non-select." -#endif - -/** - * @} - */ /* End of group UTILITIES_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief I2C internal information structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t bus_free; /*!< Bus free information. */ - uint8_t start; /*!< Start condition information. */ - uint32_t irqn; /*!< IRQ number table pointer. */ - struct - { - uint32_t address; /*!< Slave address. */ - uint32_t stop; /*!< Stop control */ - uint32_t event; /*!< I2C Event information. */ - uint32_t state; /*!< Transfer State. */ - } asynch; -} i2c_internal_info_t; - -/*----------------------------------*/ -/** - * @brief I2C buffer structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_buffer; /*!< Buffer address. */ - uint32_t length; /*!< Buffer length. */ - uint32_t pos; /*!< Buffer pointer. */ -} i2c_buffer_t; - -/*----------------------------------*/ -/** - * @brief I2C handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - I2C_t i2c; /*!< I2C class structure. */ - i2c_internal_info_t info; /*!< Internal Information. */ - i2c_buffer_t tx_buff; /*!< Tx buffer structure. */ - i2c_buffer_t rx_buff; /*!< Rx buffer structure. */ -} _i2c_t; - -/** - * @} - */ /* End of group UTILITIES_Exported_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_functions - * @{ - */ -TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl); -TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz); -void i2c_reset_t(_i2c_t *p_obj); -TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj); -TXZ_Result i2c_start_t(_i2c_t *p_obj); -TXZ_Result i2c_stop_t(_i2c_t *p_obj); -int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); -int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); -int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last); -int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data); -uint8_t i2c_active_t(_i2c_t *p_obj); -TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop); -uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj); -void i2c_abort_asynch_t(_i2c_t *p_obj); - -/* For slave */ -void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave); -int32_t i2c_slave_receive_t(_i2c_t *p_obj); -int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); -int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); -void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address); -TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length); -uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj); -void i2c_slave_abort_asynch_t(_i2c_t *p_obj); - -/** - * @} - */ /* End of group UTILITIES_Exported_functions */ - -/** - * @} - */ /* End of group UTILITIES */ - -/** - * @} - */ /* End of group Example */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __BSP_I2C_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_sample_def.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_sample_def.h deleted file mode 100644 index 8bbbd7e45e8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_sample_def.h +++ /dev/null @@ -1,30 +0,0 @@ -/** - ******************************************************************************* - * @file txz_sample_def.h - * @brief This file includes header files for sample application. - * @version V1.0.0.3 - * $Date:: 2017-10-26 13:33:43 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TXZ_SAMPLE_DEF_H -#define __TXZ_SAMPLE_DEF_H - -#include "txz_driver_def.h" -#include "txz_hal.h" -#if defined(TMPM4G9) - #include "txz_cg.h" - #include "txz_gpio.h" -#else - #include "txz_cg.h" - #include "txz_gpio.h" - #include "txz_dma.h" -#endif -#include "txz_uart.h" -#include "txz_t32a.h" -#endif /* __TXZ_SAMPLE_DEF_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_t32a.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_t32a.h deleted file mode 100644 index 35d2c87d835..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_t32a.h +++ /dev/null @@ -1,1024 +0,0 @@ -/** - ******************************************************************************* - * @file txz_t32a.h - * @brief This file provides all the functions prototypes for T32A driver. - * @version V1.0.0.7 - * $Date:: 2017-11-30 17:34:52 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __T32A_H -#define __T32A_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup T32A T32A - * @brief T32A Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Exported_define T32A Exported Define - * @{ - */ - -/** - * @defgroup T32A_Result Result - * @brief T32A Result Macro Definition. - * @{ - */ -#define T32A_RESULT_SUCCESS (0) /*!< Success */ -#define T32A_RESULT_FAILURE (-1) /*!< Failure */ -#define T32A_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ -/** - * @} - */ /* End of group T32A_Result */ - -/** - * @defgroup T32A_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define T32A_NULL ((void *)0) /*!< NULL Pointer For T32A */ -/** - * @} - */ /* End of group T32A_NullPointer */ - - /** - * @defgroup T32A_HALT T32A Debug HALT Control - * @brief Debug HALT Control Run/Stop HALT Macro Definition. - * @{ - */ -#define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) /*!< Run */ -#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /*!< Stop */ -/** - * @} - */ /* End of group T32A_HALT */ - - /** - * @defgroup T32A_MODE32 T32A 16bit/32bit MODE - * @brief T32A 16bit/32bit MODE MODE32 Macro Definition. - * @{ - */ -#define T32A_MODE_16 ((uint32_t)0x00000000) /*!< 16bit Mode */ -#define T32A_MODE_32 ((uint32_t)0x00000001) /*!< 32bit Mode */ -/** - * @} - */ /* End of group T32A_MODE32 */ - - /** - * @defgroup T32A_RUNFLGx T32A RUNFLG Control - * @brief Run/Stop RUNFLGx Macro Definition. - * @{ - */ -#define T32A_RUNFLG_RUN ((uint32_t)0x00000010) /*!< Run */ -#define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /*!< Stop */ -/** - * @} - */ /* End of group T32A_RUNFLGx */ - -/** - * @defgroup T32A_SFTSTPx T32A SW STOP Control - * @brief T32A SW STOPx SFTSTPx Macro Definition. - * @{ - */ -#define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) /*!< No effect */ -#define T32A_COUNT_STOP ((uint32_t)0x0000004) /*!< Counter Stop */ -/** - * @} - */ /* End of group T32A_SFTSTPx */ - -/** - * @defgroup T32A_SFTSTAx T32A SW START Control - * @brief T32A SW STARTx SFTSTAx Macro Definition. - * @{ - */ -#define T32A_COUNT_DONT_START ((uint32_t)0x0000000) /*!< No effect */ -#define T32A_COUNT_START ((uint32_t)0x0000002) /*!< Counter Start */ -/** - * @} - */ /* End of group T32A_SFTSTAx */ - -/** - * @defgroup T32A_RUNx T32A RUN Disable/Enable Control - * @brief RUN Disable/Enable RUNx Macro Definition. - * @{ - */ -#define T32A_RUN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define T32A_RUN_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group T32A_RUNx */ - - -/** - * @defgroup T32A_PRSCLx T32A PRESCALER Control - * @brief PRESCALER Control PRSCLx Macro Definition. - * @{ - */ -#define T32A_PRSCLx_1 ((uint32_t)0x00000000) /*!< 1/1 */ -#define T32A_PRSCLx_2 ((uint32_t)0x10000000) /*!< 1/2 */ -#define T32A_PRSCLx_8 ((uint32_t)0x20000000) /*!< 1/8 */ -#define T32A_PRSCLx_32 ((uint32_t)0x30000000) /*!< 1/32 */ -#define T32A_PRSCLx_128 ((uint32_t)0x40000000) /*!< 1/128 */ -#define T32A_PRSCLx_256 ((uint32_t)0x50000000) /*!< 1/256 */ -#define T32A_PRSCLx_512 ((uint32_t)0x60000000) /*!< 1/512 */ -#define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /*!< 1/1024 */ -/** - * @} - */ /* End of group T32A_PRSCLx */ - -/** - * @defgroup T32A_CLKx T32A COLCK Control - * @brief CLOCK Control CLKA Macro Definition. - * @{ - */ -#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /*!< prescaler */ -#define T32A_CLKx_INTRG ((uint32_t)0x01000000) /*!< internal triger */ -#define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) /*!< other timer rising edge */ -#define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) /*!< other timer trailing edge */ -#define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) /*!< external triger rising edge */ -#define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /*!< external triger trailing edge */ -/** - * @} - */ /* End of group T32A_CLKx */ - -/** - * @defgroup T32A_WBFx T32A Double Buffer Disable/Enable Control - * @brief Double Buffer Disable/Enable WBFx Macro Definition. - * @{ - */ -#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /*!< Enable */ -/** - * @} - */ /* End of group T32A_WBFx */ - - /** - * @defgroup T32A_UPDNx T32A Counter Up/Down Control - * @brief Counter Up/Down Control UPDNx Macro Definition. - * @{ - */ -#define T32A_COUNT_UP ((uint32_t)0x00000000) /*!< count up */ -#define T32A_COUNT_DOWN ((uint32_t)0x00010000) /*!< count down */ -#define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) /*!< count updown */ -#define T32A_COUNT_PLS ((uint32_t)0x00030000) /*!< count pulse */ -/** - * @} - */ /* End of group T32A_UPDNx */ - - /** - * @defgroup T32A_RELDx T32A Counter Reload Control - * @brief Counter Reload Control RELDx Macro Definition. - * @{ - */ -#define T32A_RELOAD_NON ((uint32_t)0x00000000) /*!< Nothing(Free run) */ -#define T32A_RELOAD_INTRG ((uint32_t)0x00000100) /*!< internal trigger */ -#define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) /*!< external trigger rising edge */ -#define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) /*!< external trigger trailing edge */ -#define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) /*!< other timer rising edge */ -#define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) /*!< other timer trailing edge */ -#define T32A_RELOAD_SYNC ((uint32_t)0x00000600) /*!< sync(slave channel) */ -#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /*!< match up Timer Register */ -/** - * @} - */ /* End of group T32A_RELDx */ - - /** - * @defgroup T32A_STOPx T32A Counter Stop Control - * @brief Counter Stop Control STOPx Macro Definition. - * @{ - */ -#define T32A_STOP_NON ((uint32_t)0x00000000) /*!< No use trigger */ -#define T32A_STOP_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ -#define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) /*!< external trigger rising edge */ -#define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) /*!< external trigger trailing edge */ -#define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) /*!< other timer rising edge */ -#define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) /*!< other timer trailing edge */ -#define T32A_STOP_SYNC ((uint32_t)0x00000060) /*!< sync(slave channel) */ -#define T32A_STOP_TREGx ((uint32_t)0x00000070) /*!< match up Timer Register A */ -/** - * @} - */ /* End of group T32A_STOPx */ - - - /** - * @defgroup T32A_STARTx T32A Counter Start Control - * @brief Counter Start Control STARTx Macro Definition. - * @{ - */ -#define T32A_START_NON ((uint32_t)0x00000000) /*!< No use trigger */ -#define T32A_START_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ -#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /*!< external trigger rising edge */ -#define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) /*!< external trigger trailing edge */ -#define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) /*!< other timer rising edge */ -#define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) /*!< other timer trailing edge */ -#define T32A_START_SYNC ((uint32_t)0x00000006) /*!< sync(slave channel) */ -#define T32A_START_Rsvd ((uint32_t)0x00000007) /*!< Reserved */ -/** - * @} - */ /* End of group T32A_STARTx */ - -/** - * @defgroup T32A_OCRx T32AxOUTA Control - * @brief T32AxOUTA Control OCRx Macro Definition. - * @{ - */ -#define T32A_OCR_DISABLE ((uint32_t)0x00000000) /*!< Nothig */ -#define T32A_OCR_SET ((uint32_t)0x00000001) /*!< Hi */ -#define T32A_OCR_CLR ((uint32_t)0x00000002) /*!< Low */ -#define T32A_OCR_INVERSION ((uint32_t)0x00000003) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRx */ - -/** - * @defgroup T32A_OCRCAPx1 T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 - * @brief T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 OCRCAPx1 Macro Definition. - * @{ - */ -#define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ -#define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) /*!< Hi */ -#define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) /*!< Low */ -#define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRCAPx1 */ - -/** - * @defgroup T32A_OCRCAPx0 T32AxOUTA Control of T32AxCAPx0 counter value - * @brief T32AxOUTA Control of T32AxCAPx0 T32AxRGx1 OCRCAPx0 Macro Definition. - * @{ - */ -#define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ -#define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) /*!< Hi */ -#define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) /*!< Low */ -#define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRCAPx0 */ - -/** - * @defgroup T32A_OCRCMPx1 T32AxOUTA Control of T32AxRGx1 Counter Value - * @brief T32AxOUTA Control of T32AxRGx1 Counter Value OCRCMPx1 Macro Definition. - * @{ - */ -#define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ -#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /*!< Hi */ -#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) /*!< Low */ -#define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRCMPx1 */ - -/** - * @defgroup T32A_OCRCMPx0 T32AxOUTA Control of T32AxRGx0 Counter Value - * @brief T32AxOUTA Control of T32AxRGx0 Counter Value OCRCMPx0 Macro Definition. - * @{ - */ -#define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ -#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /*!< Hi */ -#define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) /*!< Low */ -#define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /*!< inversion */ -/** - * @} - */ /* End of group T32A_OCRCMPx0 */ - -/** - * @defgroup T32A_RGx0 T32A Timer Register x0 MASK - * @brief T32A Timer Register A0 MASK RGx0 Macro Definition. - * @{ - */ -#define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_RGx0 */ - -/** - * @defgroup T32A_RGx1 T32A Timer Register x1 MASK - * @brief T32A Timer Register A1 MASK RGx1 Macro Definition. - * @{ - */ -#define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_RGx0 */ - -/** - * @defgroup T32A_TMRx T32A Counter Capture Register x MASK - * @brief T32A Counter Capture Register x MASK TMRx Macro Definition. - * @{ - */ -#define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_TMRx */ - -/** - * @defgroup T32A_RELD T32A Counter Reload Register x MASK - * @brief T32A Counter Reload Register x MASK TMRx Macro Definition. - * @{ - */ -#define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_RELD */ - - /** - * @defgroup T32A_CAPMx1 T32A Capture Control Register x1 - * @brief Capture Control Register A1 CAPMx1 Macro Definition. - * @{ - */ -#define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ -#define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ -#define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) /*!< INx0 rising edge */ -#define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) /*!< INx0 trailing edge */ -#define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) /*!< INx1 rising edge */ -#define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) /*!< INx1 trailing edge */ -#define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) /*!< other timer rising edge */ -#define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /*!< other timer trailing edge */ -/** - * @} - */ /* End of group T32A_CAPMx1 */ - - /** - * @defgroup T32A_CAPMx0 T32A Capture Control Register x0 - * @brief Capture Control Register x0 CAPMx0 Macro Definition. - * @{ - */ -#define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ -#define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ -#define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) /*!< INx0 rising edge */ -#define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) /*!< INx0 trailing edge */ -#define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) /*!< INx1 rising edge */ -#define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) /*!< INx1 trailing edge */ -#define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) /*!< other timer rising edge */ -#define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /*!< other timer trailing edge */ -/** - * @} - */ /* End of group T32A_CAPMx0 */ - -/** - * @defgroup T32A_CAPx0 T32A Capture Register x0 MASK - * @brief T32A Capture Register x0 MASK CAPx0 Macro Definition. - * @{ - */ -#define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_CAPx0 */ - -/** - * @defgroup T32A_CAPx1 T32A Capture Register x1 MASK - * @brief T32A Capture Register x1 MASK CAPx1 Macro Definition. - * @{ - */ -#define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ -#define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ -/** - * @} - */ /* End of group T32A_CAPx1 */ - -/** - * @defgroup T32A_IMSTERR T32A Statuserr Interrupt Request MASK - * @brief T32A Statuserr Interrupt Request MASK IMSTERR Macro Definition. - * @{ - */ -#define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) -#define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) -/** - * @} - */ /* End of group T32A_IMSTERR */ - -/** - * @defgroup T32A_IMUFx T32A Underflow Interrupt Request MASK - * @brief T32A Underflow Interrupt Request MASK IMUFx Macro Definition. - * @{ - */ -#define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ -#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /*!< request */ -/** - * @} - */ /* End of group T32A_IMUFx */ - -/** - * @defgroup T32A_IMOFx T32A Overflow Interrupt Request MASK - * @brief T32A Overflow Interrupt Request MASK IMOFx Macro Definition. - * @{ - */ -#define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ -#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /*!< request */ -/** - * @} - */ /* End of group T32A_IMOFx */ - -/** - * @defgroup T32A_IMx1 T32A Match Up T32AxRGx1 Interrupt Request MASK - * @brief T32A Match Up T32AxRGx1 Interrupt Request MASK IMx1 Macro Definition. - * @{ - */ -#define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ -#define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /*!< request */ -/** - * @} - */ /* End of group T32A_IMx1 */ - -/** - * @defgroup T32A_IMx0 T32A Match Up T32AxRGx0 Interrupt Request MASK - * @brief T32A Match Up T32AxRGx0 Interrupt Request MASK IMx0 Macro Definition. - * @{ - */ -#define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ -#define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /*!< request */ -/** - * @} - */ /* End of group T32A_IMx0 */ - -/** - * @defgroup T32A_INTSTERR T32A_Statuerr Flag Status - * @brief T32A Statuserr Flag Status INTSTERR Macro Definition. - * @{ - */ -#define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) -#define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) -/** - * @} - */ /* End of group T32A_INTSTERR */ - -/** - * @defgroup T32A_INTUFA T32A Underflow Flag Status - * @brief T32A Underflow Flag Status INTUFA Macro Definition. - * @{ - */ -#define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) /*!< Underflow Flag Mask */ -#define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /*!< Underflow Flag Clear */ -/** - * @} - */ /* End of group T32A_INTUFA */ - -/** - * @defgroup T32A_INTOFA T32A Overflow Flag Status - * @brief T32A Overflow Flag Status INTOFA Macro Definition. - * @{ - */ -#define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) /*!< Overflow Flag Mask */ -#define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /*!< Overflow Flag Clear */ -/** - * @} - */ /* End of group T32A_INTOFA */ - -/** - * @defgroup T32A_INTA1 T32A Match Up T32AxRGx1 Flag Status - * @brief T32A Match Up T32AxRGx1 Flag Status INTA1 Macro Definition. - * @{ - */ -#define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Mask */ -#define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Clear */ -/** - * @} - */ /* End of group T32A_INTA1 */ - -/** - * @defgroup T32A_INTA0 T32A Match Up T32AxRGx0 Flag Status - * @brief T32A Match Up T32AxRGx0 Flag Status INTA0 Macro Definition. - * @{ - */ -#define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Mask */ -#define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Clear */ -/** - * @} - */ /* End of group T32A_INTA0 */ - -/** - * @defgroup T32A_DMAENx2 T32A DMA Converter1 Request control - * @brief T32A DMA Converter1 Disable/Enable DMAENx2 Macro Definition. - * @{ - */ -#define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) /*!< disable */ -#define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /*!< enable */ -/** - * @} - */ /* End of group T32A_DMAENx2 */ - -/** - * @defgroup T32A_DMAENx1 T32A DMA InputCapture1 Request control - * @brief T32A DMA InputCapture1 Disable/Enable DMAENx1 Macro Definition. - * @{ - */ -#define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) /*!< disable */ -#define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /*!< enable */ -/** - * @} - */ /* End of group T32A_DMAENx1 */ - -/** - * @defgroup T32A_DMAENx0 T32A DMA InputCapture0 Request control - * @brief T32A DMA InputCapture0 Disable/Enable DMAENx0 Macro Definition. - * @{ - */ -#define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) /*!< disable */ -#define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /*!< enable */ -/** - * @} - */ /* End of group T32A_DMAENx0 */ - - /** - * @defgroup T32A_PDN T32A Pulse Mode Count Down Control - * @brief Pulse Mode Count Down Control PDN Macro Definition. - * @{ - */ -#define T32A_PDN_NON0 ((uint32_t)0x00000000) /*!< Do not count down */ -#define T32A_PDN_NON1 ((uint32_t)0x00001000) /*!< Do not count down */ -#define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) /*!< T32AxINC0 rising edge */ -#define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) /*!< T32AxINC0 trailing edge */ -#define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) /*!< T32AxINC1 rising edge */ -#define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) /*!< T32AxINC1 trailing edge */ -#define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) /*!< T32AxINC0 rising edge/trailing edge */ -#define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /*!< T32AxINC1 rising edge/trailing edge */ -/** - * @} - */ /* End of group T32A_PDN */ - - /** - * @defgroup T32A_PUP T32A Pulse Mode Count UP Control - * @brief Pulse Mode Count UP Control PUP Macro Definition. - * @{ - */ -#define T32A_PUP_NON0 ((uint32_t)0x00000000) /*!< Do not count up */ -#define T32A_PUP_NON1 ((uint32_t)0x00000100) /*!< Do not count up */ -#define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) /*!< T32AxINC0 rising edge */ -#define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) /*!< T32AxINC0 trailing edge */ -#define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) /*!< T32AxINC1 rising edge */ -#define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) /*!< T32AxINC1 trailing edge */ -#define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) /*!< T32AxINC0 rising edge/trailing edge */ -#define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /*!< T32AxINC1 rising edge/trailing edge */ -/** - * @} - */ /* End of group T32A_PUP */ - - /** - * @defgroup T32A_NF T32A Noise Filter control - * @brief Noise Filter control NF Macro Definition. - * @{ - */ -#define T32A_NF_NON ((uint32_t)0x00000000) /*!< Nothing */ -#define T32A_NF_2 ((uint32_t)0x00000010) /*!< Noise Filter less than 2/��T0 */ -#define T32A_NF_4 ((uint32_t)0x00000020) /*!< Noise Filter less than 4/��T0 */ -#define T32A_NF_8 ((uint32_t)0x00000030) /*!< Noise Filter less than 8/��T0 */ -/** - * @} - */ /* End of group T32A_NF */ - -/** - * @defgroup T32A_PDIR T32A Phase 2 Pulse Direction control - * @brief Phase 2 Pulse Direction control PDIR Macro Definition. - * @{ - */ -#define T32A_PDIR_FORWARD ((uint32_t)0x00000000) /*!< forward */ -#define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /*!< backward */ -/** - * @} - */ /* End of group T32A_PDIR */ - -/** - * @defgroup T32A_PMODE T32A Pulse Count Mode control - * @brief Pulse Count Mode control PDIR Macro Definition. - * @{ - */ -#define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) /*!< Phase 2 Pulse Counter Mode */ -#define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /*!< Phase 1 Pulse Counter Mode */ -/** - * @} - */ /* End of group T32A_PMODE */ - -/** - * @} - */ /* End of group T32A_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** @defgroup T32A_Exported_Typedef T32A Exported Typedef - * @{ - */ - -/** - * @enum t32_type_t - * @brief Use of Timer register. - */ -typedef enum -{ - T32A_TIMERA = 0, /*!< 0: Timer A */ - T32A_TIMERB, /*!< 1: Timer B */ - T32A_TIMERC, /*!< 2: Timer C */ - T32A_TIMERMAX, -}t32_type_t; - -/** - * @enum t32_regnum_t - * @brief Use of Timer register number. - */ -typedef enum -{ - T32A_REG0 = 0, /*!< 0: Register 0 */ - T32A_REG1, /*!< 1: Register 1 */ - T32A_RELOAD, /*!< 2: Reload Register */ -}t32_regnum_t; -/** - * @enum t32_mode_t - * @brief Use of Timer register. - */ -typedef enum -{ - T32A_MATCH = 0, /*!< 0: compare match detection 0 */ - T32A_OVERFLOW, /*!< 1: Overfloe detection */ - T32A_UNDERFLOW, /*!< 2: Underflow detection */ - T32A_CAPTURE0, /*!< 3: Capture 0 */ - T32A_CAPTURE1, /*!< 4: Capture 0 */ -}t32_mode_t; - -/** - * @enum t32_triger_t - * @brief Use of Timer register. - */ -typedef enum -{ - T32A_INTRG = 0, /*!< 0: internal triger */ - T32A_TIM_RISING_EDGE, /*!< 1: Same Channel other timer rising edge */ - T32A_TIM_TRAILING_EDGE, /*!< 2: Same Channel other timer trailing edge */ - T32A_EXTTRG_RISING_EDGE, /*!< 3: external triger rising edge */ - T32A_EXTTRG_TRAILING_EDGE, /*!< 4: external triger trailing edge */ -}t32_triger_t; -/** - * @} - */ /* End of group T32A_Exported_Typedef */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup T32A_Exported_Typedef T32A Exported Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @struct t32a_mode_t - * @brief TimerA Mode Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t halt; /*!< T32A Debug HALT Control. - : Use @ref T32A_HALT */ - uint32_t mode; /*!< T32A 16bit/32bit MODE . - : Use @ref T32A_MODE32 */ -} t32a_mode_t; - -/*----------------------------------*/ -/** - * @struct t32a_runx_t - * @brief TimerA Run Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t runflg; /*!< TimerA Run Control Flag. - : Use @ref T32A_RUNFLGx */ - uint32_t sftstp; /*!< SW Counter STOP Control. - : Use @ref T32A_SFTSTPx */ - uint32_t sftsta; /*!< SW Counter START Control. - : Use @ref T32A_SFTSTAx */ - uint32_t run; /*!< TimerA Run Control. - : Use @ref T32A_RUNx */ -} t32a_runx_t; - -/*----------------------------------*/ -/** - * @struct t32a_crx_t - * @brief Counter Register Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t prscl; /*!< T32A PRESCALER Control. - : Use @ref T32A_PRSCLx */ - uint32_t clk; /*!< T32A COLCK Control. - : Use @ref T32A_CLKx */ - uint32_t wbf; /*!< T32A Double Buffer Disable/Enable Control. - : Use @ref T32A_WBFx */ - uint32_t updn; /*!< T32A Counter Up/Down Control. - : Use @ref T32A_UPDNx */ - uint32_t reld; /*!< T32A Counter Reload Control. - : Use @ref T32A_RELDx */ - uint32_t stop; /*!< T32A Counter Stop Control. - : Use @ref T32A_STOPx */ - uint32_t start; /*!< T32A Counter Start Controlc. - : Use @ref T32A_STARTx */ -} t32a_crx_t; - -/*----------------------------------*/ -/** - * @struct t32a_outcrx0_t - * @brief TimerA Output Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t ocr; /*!< T32AxOUTA Control. - : Use @ref T32A_OCRx */ -} t32a_outcrx0_t; - -/*----------------------------------*/ -/** - * @struct t32a_outcrx1_t - * @brief T32AxOUTA Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t ocrcap1; /*!< T32AxOUTA Control of T32AxCAPx1 T32AxRGx1. - : Use @ref T32A_OCRCAPx1 */ - uint32_t ocrcap0; /*!< T32AxOUTA Control of T32AxCAPx0 T32AxRGx1. - : Use @ref T32A_OCRCAPx0 */ - uint32_t ocrcmp1; /*!< T32AxOUTA Control of T32AxRGx1 Counter Value - : Use @ref T32A_OCRCMPx1 */ - uint32_t ocrcmp0; /*!< T32AxOUTA Control of T32AxRGx0 Counter Value - : Use @ref T32A_OCRCMPx0 */ -} t32a_outcrx1_t; - -/*----------------------------------*/ -/** - * @struct t32a_capcrx_t - * @brief Capture Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t capmx1; /*!< T32A Capture Control Register x1. - : Use @ref T32A_CAPMx1 */ - uint32_t capmx0; /*!< T32A Capture Control Register A0. - : Use @ref T32A_CAPMx0 */ -} t32a_capcrx_t; - -/*----------------------------------*/ -/** - * @struct t32a_rgx0_t - * @brief T32A Timer Register x0 Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t rgx0; /*!< T32A Timer Register x0. - : Use @ref T32A_RGx0 */ -} t32a_rgx0_t; - -/*----------------------------------*/ -/** - * @struct t32a_rgx1_t - * @brief T32A Timer Register x1 Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t rgx1; /*!< T32A Timer Register x1. - : Use @ref T32A_RGx1 */ -} t32a_rgx1_t; - -/*----------------------------------*/ -/** - * @struct t32a_tmrx_t - * @brief T32A Counter Capture Register A Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tmrx; /*!< T32A Counter Capture Register x. - : Use @ref T32A_TMRx */ -} t32a_tmrx_t; - -/*----------------------------------*/ -/** - * @struct t32a_reldx_t - * @brief T32A Counter Reload Register Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t reld; /*!< T32A Counter Reload Register. - : Use @ref T32A_RELD */ -} t32a_reldx_t; - -/*----------------------------------*/ -/** - * @struct t32a_capx0_t - * @brief T32A Capture Register x0 Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t capx0; /*!< T32A Capture Register x0. - : Use @ref T32A_CAPx0 */ -} t32a_capx0_t; - -/*----------------------------------*/ -/** - * @struct t32a_capx1_t - * @brief T32A Capture Register x0 Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t capx1; /*!< T32A Capture Register x1. - : Use @ref T32A_CAPx1 */ -} t32a_capx1_t; - -/*----------------------------------*/ -/** - * @struct t32a_imx_t - * @brief Interrupt mask register Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t imsterr; /*!< T32A State Transition Err Interrupt Request MASK (Only use Timer C). - : Use @ref T32A_IMSTERR */ - uint32_t imuf; /*!< T32A Underflow Interrupt Request MASK. - : Use @ref T32A_IMUFx */ - uint32_t imof; /*!< T32A Underflow Interrupt Request MASK. - : Use @ref T32A_IMOFx */ - uint32_t imx1; /*!< T32A Match Up T32AxRGx1 Interrupt Request MASK. - : Use @ref T32A_IMx1 */ - uint32_t imx0; /*!< T32A Match Up T32AxRGx0 Interrupt Request MASK. - : Use @ref T32A_IMx0 */ -} t32a_imx_t; - -/*----------------------------------*/ -/** - * @struct t32a_stx_t - * @brief Status register structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t intsterr; /*!< T32A State Transition Err Flag Status (Only use Timer C). - : Use @ref T32A_INTSTERR */ - uint32_t intuf; /*!< T32A Underflow Flag Status. - : Use @ref T32A_INTUFA */ - uint32_t intof; /*!< T32A Overflow Flag Status. - : Use @ref T32A_INTOFA */ - uint32_t intx1; /*!< T32A Match Up T32AxRGx1 Flag Status. - : Use @ref T32A_INTA1 */ - uint32_t intx0; /*!< T32A Match Up T32AxRGx0 Flag Status. - : Use @ref T32A_INTA0 */ -} t32a_stx_t; - -/*----------------------------------*/ -/** - * @struct t32a_dma_req_t - * @brief DMA Request register setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t dmaenx2; /*!< T32A DMA Converter1 Request control. - : Use @ref T32A_DMAENx2 */ - uint32_t dmaenx1; /*!< T32A DMA InputCapture1 Request control. - : Use @ref T32A_DMAENx1 */ - uint32_t dmaenx0; /*!< T32A DMA InputCapture0 Request control. - : Use @ref T32A_DMAENx0 */ -} t32a_dma_req_t; - -/*----------------------------------*/ -/** - * @struct t32a_pulse_cr_t - * @brief Pulse Count Control register setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t pdn; /*!< Pulse Mode Count Down Control. - : Use @ref T32A_PDN */ - uint32_t pup; /*!< Pulse Mode Count UP Control. - : Use @ref T32A_PUP */ - uint32_t nf; /*!< Noise Filter control. - : Use @ref T32A_NF */ - uint32_t pdir; /*!< Phase 2 Pulse Direction control. - : Use @ref T32A_PDIR */ - uint32_t pmode; /*!< Pulse Count Mode control. - : Use @ref T32A_PMODE */ -} t32a_pulse_cr_t; - -/** - * @struct t32a_initial_setting_t - * @brief Initial Timer setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - t32a_runx_t runx; /*!< Timer Run Control Setting */ - t32a_crx_t crx; /*!< Counter Register Control Setting */ - t32a_outcrx0_t outcrx0; /*!< Timer Output Control Setting */ - t32a_outcrx1_t outcrx1; /*!< T32AxOUTx Control Setting */ - t32a_capcrx_t capcrx; /*!< Capture Control Setting */ - t32a_rgx0_t rgx0; /*!< T32A Timer Register x0 Setting */ - t32a_rgx1_t rgx1; /*!< T32A Timer Register x1 Setting */ - t32a_tmrx_t tmrx; /*!< T32A Counter Capture Register Setting */ - t32a_reldx_t reldx; /*!< T32A Counter Reload Register Setting */ - t32a_capx0_t capx0; /*!< T32A Capture Register x0 Setting */ - t32a_capx1_t capx1; /*!< T32A Capture Register x1 Setting */ - t32a_imx_t imx; /*!< Interrupt mask register Setting */ - t32a_dma_req_t dma_req; /*!< DMA Request register Setting */ - t32a_pulse_cr_t pls_cr; /*!< Pulse Count Control Register Setting (Only use Timer C) */ - void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Event handler. */ - void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap0 Event handler. */ - void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap1 Event handler. */ -} t32a_initial_setting_t; - -/** - * @struct t32a_initial_mode_t - * @brief Initial Mode setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - t32a_mode_t mode; /*!< Timer Mode Setting */ -} t32a_initial_mode_t; - - -/*----------------------------------*/ -/** - * @brief T32A handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct t32a_handle -{ - TSB_T32A_TypeDef *p_instance; /*!< Registers base address. */ - t32a_initial_mode_t init_mode; /*!< Timer Mode Initial Setting */ - t32a_initial_setting_t init[T32A_TIMERMAX]; /*!< Initial setting. */ -}t32a_t; - -/** @} */ -/* End of group T32A_Exported_Types */ -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Exported_functions T32A Exported Functions - * @{ - */ -TXZ_Result t32a_mode_init(t32a_t *p_obj); -TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type); -TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value); -TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val); -TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type); -void t32a_timer_IRQHandler(t32a_t *p_obj); -void t32a_timer_cap0_IRQHandler(t32a_t *p_obj); -void t32a_timer_cap1_IRQHandler(t32a_t *p_obj); -TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl); -/** - * @} - */ /* End of group T32A_Exported_functions */ - -/** - * @} - */ /* End of group T32A */ - -/** - * @} - */ /* End of group Periph_Driver */ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __T32A_H */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_tspi.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_tspi.h deleted file mode 100644 index 1f422aa07d1..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_tspi.h +++ /dev/null @@ -1,1322 +0,0 @@ -/** - ******************************************************************************* - * @file txz_tspi.h - * @brief This file provides all the functions prototypes for TSPI driver. - * @version V1.0.0.3 - * $Date:: 2018-02-28 13:37:55 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __TSPI_H -#define __TSPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup TSPI TSPI - * @brief TSPI Driver. - * @{ - */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Exported_define TSPI Exported Define - * @{ - */ -/** - * @defgroup TSPI_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define TSPI_NULL ((void *)0) -/** - * @} - */ /* End of group TSPI_NullPointer */ - -/** - * @defgroup TSPI_ParameterResult Parameter Check Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group TSPI_ParameterResult */ - - -/** - * @defgroup TSPI_Result Result - * @brief TSPI Result Macro Definition. - * @{ - */ -#define TSPI_RESULT_SUCCESS (0) /*!< Success */ -#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ -/** - * @} - */ /* End of group TSPI_Result */ - -/** - * @defgroup TSPI_SW_Reset SW Reset - * @brief Software Rest Macro Definition. - * @{ - */ -#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattarn 10 */ -#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattarn 01 */ -/** - * @} - */ /* End of group TSPI_SW_Reset */ - - -/** - * @defgroup TSPI_Enable TSPI Enable/Disable Control - * @brief Enable/Disable TSPIE Macro Definition. - * @{ - */ -#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_Enable */ - -/** - * @defgroup TSPI_Triger_Control Triger Control - * @brief Enable/Disable TRGEN Macro Definition. - * @{ - */ -#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_Transmission_Control */ - -/** - * @defgroup TSPI_Transmission_Control Transmission Control - * @brief Enable/Disable TRXE Macro Definition. - * @{ - */ -#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ -#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ -/** - * @} - */ /* End of group TSPI_Transmission_Control */ - -/** - * @defgroup TSPI_Transmission_Mode Transmission Mode - * @brief TSPIIMS Mode Macro Definisiton. - * @{ - */ -#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ -#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ -/** - * @} - */ /* End of group TSPI_Transmission_Mode */ - - -/** - * @defgroup TSPI_Operation_Select Operation Select - * @brief Master/Slave MSTR Operation Macro Definisiton. - * @{ - */ -#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /*!< MASTER MODE */ -#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ -/** - * @} - */ /* End of group TSPI_Operation_Select */ - - -/** - * @defgroup TSPI_Transfer_Mode Transfer Mode - * @brief Transfer Mode TMMD Macro Definisiton. - * @{ - */ -#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ -#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ -#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ -#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ -/** - * @} - */ /* End of group TSPI_Transfer_Mode */ - - -/** - * @defgroup TSPI_CSSEL_Select CSSEL Select - * @brief TSPIIxCS0/1/2/3 Select Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ -#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ -#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ -#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ -/** - * @} - */ /* End of group TSPI_CSSEL_Select */ - -/** - * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range - * @brief Transfer Frame Range Macro Definisiton. - * @{ - */ -#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /*!< Single Transfer Frame :0 */ -#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ -/** - * @} - */ /* End of group TSPI_Transfer_Frame_Range */ -/** - * @defgroup TSPI_IDLE_Output_value IDLE Output Value - * @brief IDLE time Output Value TIDLE Macro Definisiton. - * @{ - */ -#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ -#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ -#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ -#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ -/** - * @} - */ /* End of group TSPI_IDLE_Output_value */ - -/** - * @defgroup TSPI_RXDLY_value RXDLY Value - * @brief IDLE time Output Value TIDLE Macro Definisiton. - * @{ - */ -#define TSPI_RXDLY_SET ((uint32_t)0x00010000) /*!< RXDLY SET */ -/** - * @} - */ /* End of group TSPI_RXDLY_value*/ - - - /** - * @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value - * @brief In case of Under Run Output Value TXDEMP Macro Definisiton. - * @{ - */ -#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ -#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ -/** - * @} - */ /* End of group TSPI_Underrun_Output_value */ - - -/** - * @defgroup TSPI_TxFillLevel Tx Fill Level - * @brief Transmit Fill Level Macro Definisiton. - * @{ - */ -#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ -#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ -#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ -#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ -#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ -#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ -#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ -#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ -/*! - * @} - */ /* End of group TSPI_TxFillLevel */ - - -/** - * @defgroup TSPI_RxFillLevel Rx Fill Level - * @brief Receive Fill Level Macro Definisiton. - * @{ - */ -#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 8 */ -#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ -#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ -#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ -#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ -#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ -#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ -#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ -#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_RxFillLevel */ - - -/** - * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrpt - * @brief Enable/Disable Transmit FIFO Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxFIFOInterrupt */ - - -/** - * @defgroup TSPI_TxInterrupt Tx Interrpt - * @brief Enable/Disable Transmit Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxInterrupt */ - - -/** - * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrpt - * @brief Enable/Disable Receive FIFO Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxFIFOInterrupt */ - - -/** - * @defgroup TSPI_RxInterrupt Rx Interrpt - * @brief Enable/Disable Receive Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxInterrupt */ - - -/** - * @defgroup TSPI_ErrorInterrupt Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_ErrorInterrupt */ - - -/** - * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt - * @brief Enable/Disable Transmit DMA Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ -#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_TxDMAInterrupt */ - - -/** - * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt - * @brief Enable/Disable Receive DMA Interrupt Macro Definisiton. - * @{ - */ -#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ -#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_RxDMAInterrupt */ - - -/** - * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear - * @brief Tx Buffer Clear Macro Definisiton. - * @{ - */ -#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ -/** - * @} - */ /* End of group TSPI_Tx_Buffer_Clear */ - - -/** - * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear - * @brief Rx Buffer Clear Macro Definisiton. - * @{ - */ -#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ -/** - * @} - */ /* End of group TSPI_Rx_Buffer_Clear */ - - -/** - * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock - * @brief Baudrate Input Clock Macro Definisiton. - * @{ - */ -#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ -#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ -#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ -#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ -#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ -#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ -#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ -#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ -#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ -#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ -/** - * @} - */ /* End of group TSPI_Baudrate_Clock */ - - -/** - * @defgroup TSPI_Baudrate_Divider Baudrate Divider - * @brief Baudrate IDivider Macro Definisiton. - * @{ - */ -#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ -#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ -#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ -#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ -#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ -#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ -#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ -#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ -#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ -#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ -#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ -#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ -#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ -#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ -#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ -#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ -/** - * @} - */ /* End of group TSPI_Baudrate_Divider */ - - -/** - * @defgroup TSPI_DataDirection Data Direction - * @brief Data Direction Macro Definisiton. - * @{ - */ -#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ -#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ -/*! - * @} - */ /* End of group TSPI_DataDirection */ - - -/** - * @defgroup TSPI_DataLength Data Length - * @brief Data Length Macro Definisiton. - * @{ - */ -#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ -#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ -#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ -#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ -#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ -#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ -#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ -#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ -#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ -#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ -#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ -#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ -#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ -#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ -#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ -#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ -#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ -#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ -#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ -#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ -#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ -#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ -#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ -#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ -#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ -#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ -/** - * @} - */ /* End of group TSPI_DataLength */ - - -/** - * @defgroup TSPI_Frame_Interval_Time Frame Interval time - * @brief Frame Interval time Macro Definisiton. - * @{ - */ -#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ -#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Frame_Interval_Time */ - - -/** - * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity - * @brief TSPIxCS3 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS3_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity - * @brief TSPIxCS2 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS2_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity - * @brief TSPIxCS1 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS1_Polarity */ - - -/** - * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity - * @brief TSPIxCS0 Polarity Macro Definisiton. - * @{ - */ -#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ -#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ -/** - * @} - */ /* End of group TSPI_TSPIxCS0_Polarity */ - - -/** - * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity - * @brief Serial Clock Polarity Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ -#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ -/** - * @} - */ /* End of group Serial Clock Polarity */ - - -/** - * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity - * @brief Serial Clock IDLE Polarity Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ -#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ -/** - * @} - */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ - - -/** - * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time - * @brief Minimum IDLE Time Macro Definisiton. - * @{ - */ -#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ -#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Minimum_IDLE_Time */ - - -/** - * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay - * @brief Serial Clock Delay Macro Definisiton. - * @{ - */ -#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ -#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Serial_Clock_Delay */ - - -/** - * @defgroup TSPI_Negate_Delay Negate Delay - * @brief Negate Delay Macro Definisiton. - * @{ - */ -#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ -#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ -#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ -#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ -#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ -#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ -#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ -#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ -#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ -#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ -#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ -#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ -#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ -#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ -#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ -#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ -/** - * @} - */ /* End of group TSPI_Negate_Delay */ - - -/** - * @defgroup TSPI_ParityEnable Parity Enable - * @brief Enable/Disable Parity Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ -/** - * @} - */ /* End of group TSPI_ParityEnable */ - - -/** - * @defgroup TSPI_ParityBit Parity Bit - * @brief Parity Bit Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ -#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ -/** - * @} - */ /* End of group TSPI_ParityBit */ - - -/** - * @defgroup TSPI_Status_Setting_flag Status Setting Flag - * @brief Enable/Disable Status Setting Flag Macro Definisiton. - * @{ - */ -#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ -#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ -/** - * @} - */ /* End of group TSPI_Status_Setting_flag */ - - -/** - * @defgroup TSPI_TxState Transmitting State Flag - * @brief Transmitting State Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ -#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ -#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ -/** - * @} - */ /* End of group TSPI_TxState */ - - -/** - * @defgroup TSPI_TxDone Transmitting Complete Flag - * @brief Transmitting Complete Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ -#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ -#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ -/** - * @} - */ /* End of group TSPI_TxDone */ - - -/** - * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrpt Flag - * @brief Transmitting FIFO Interrpt Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ -#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ -#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ -/** - * @} - */ /* End of group TSPI_TxFIFOInterruptFlag */ - -/** - * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag - * @brief Transmitting FIFO Empty Flag Macro Definisiton. - * @{ - */ -#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ -#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ -/** - * @} - */ /* End of group TSPI_TxFIFOEmptyFlag */ - -/** - * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level - * @brief Current Transmitting FIFO Level Macro Definisiton. - * @{ - */ -#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ -#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ -#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ -#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ -#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ -#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ -#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ -#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ -/** - * @} - */ /* End of group TSPI_TxReachFillLevel */ - - -/** - * @defgroup TSPI_RxState Receive State Flag - * @brief Receive State Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ -#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ -#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ -/** - * @} - */ /* End of group TSPI_RxState */ - - -/** - * @defgroup TSPI_RxDone Receive Complete Flag - * @brief Receive Complete Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ -#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ -#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ -/** - * @} - */ /* End of group TSPI_RxDone */ - - -/** - * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrpt Flag - * @brief Rx FIFO Interrpt Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ -#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ -#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ -/** - * @} - */ /* End of group TSPI_RxFIFOInterruptFlag */ - -/** - * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag - * @brief Receiving FIFO Full Flag Macro Definisiton. - * @{ - */ -#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ -#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ -/** - * @} - */ /* End of group TSPI_RxFIFOFullFlag */ - - -/** - * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level - * @brief Current Receive FIFO Level Macro Definisiton. - * @{ - */ -#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ -#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ -#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ -#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ -#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ -#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ -#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ -#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ -#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ -/** - * @} - */ /* End of group TSPI_RxReachFillLevel */ - - -/** - * @defgroup TSPI_TRGErr Triger Error - * @brief Triger Error Macro Definisiton. - * @{ - */ -#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ -#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_TRGErr */ - -/** - * @defgroup TSPI_UnderrunErr Underrun Error - * @brief Underrun Error Macro Definisiton. - * @{ - */ -#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ -#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_UnderrunErr */ - -/** - * @defgroup TSPI_OverrunErr Overrun Error - * @brief Overrun Error Macro Definisiton. - * @{ - */ -#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ -#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_OverrunErr */ - - -/** - * @defgroup TSPI_ParityErr Parity Error - * @brief Parity Error Macro Definisiton. - * @{ - */ -#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ -#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ -/** - * @} - */ /* End of group TSPI_ParityErr */ - - /** - * @defgroup TSPI_Data_allign Data allign - * @brief Data allign Macro Definisiton. - * @{ - */ -#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ -#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ -#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ -/** - * @} - */ /* End of group TSPI_Data_allign */ - - /** - * @defgroup TSPI_FifoMax FIFO MAX - * @brief FIFO MAX LEVEL - * @{ - */ -#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ -/** - * @} - */ /* End of group TSPI_FifoMax */ - - /** - * @defgroup TSPI_ErrCode Error Code - * @brief Error Code Macro Definisiton. - * @{ - */ -#define NOERROR ((uint32_t)0x00000000) /*!< no error */ -#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ -#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ -#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ -#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ -#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ -#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ -#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ -#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ -#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ -#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ -/** -* @} - */ /* End of group TSPI_ErrCode */ - - /** - * @defgroup TSPI_Buffer_Size Receive Buffer size - * @brief Error Code Macro Definisiton. - * @{ - */ -#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ -/** -* @} - */ /* End of group TSPI_Buffer_Size */ -/** - * @} - */ /* End of group TSPI_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef - * @{ - */ -/* No define */ -/** - * @} - */ /* End of group TSPI_Exported_Typedef */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @struct tspi_receive8_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive8_t; - -/*----------------------------------*/ -/** - * @struct tspi_receive16_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive16_t; - -/** - * @struct tspi_receive32_t - * @brief Receive event information structure definenition. - * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} tspi_receive32_t; - -/*----------------------------------*/ -/** - * @struct tspi_receive_t - * @brief Receive event information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ - tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ - tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ -} tspi_receive_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit8_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit8_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit16_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit16_t; -/*----------------------------------*/ -/** - * @struct tspi_transmit32_t - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} tspi_transmit32_t; - -/*----------------------------------*/ -/** - * @struct tspi_transmit_t - * @brief Transmit data information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ - tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ - tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ -} tspi_transmit_t; - -/*----------------------------------*/ -/** - * @struct tspi_control1_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t trgen; /*!< TRGEN Transmission Triger Control. - : Use @ref TSPI_Triger_Control */ - uint32_t trxe; /*!< TRXE Transmission Control. - : Use @ref TSPI_Transmission_Control */ - uint32_t tspims; /*!< TSPI/SIO Transmission Mode. - : Use @ref TSPI_Transmission_Mode */ - uint32_t mstr; /*!< Master/Slave Operation Select. - : Use @ref TSPI_Operation_Select */ - uint32_t tmmd; /*!< Transfer Mode Select. - : Use @ref TSPI_Transfer_Mode */ - uint32_t cssel; /*!< CSSEL Select. - : Use @ref TSPI_CSSEL_Select */ - uint32_t fc; /*!< Transfer Frame Value. - : Range ( TSPI_TRANS_RANGE_SINGLE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ -} tspi_control1_t; - -/*----------------------------------*/ -/** - * @struct tspi_control2_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tidle; /*!< IDLE Output Value. - : Use @ref TSPI_IDLE_Output_value */ - uint32_t txdemp; /*!< Under Run Occur Output Value. - : Use @ref TSPI_IDLE_Output_value */ - uint32_t rxdly; /*!< Fsys Select. - : Use @ref TSPI_RXDLY_value */ - uint32_t til; /*!< Transmit Fill Level. - : Use @ref TSPI_TxFillLevel */ - uint32_t ril; /*!< Receive Fill Level. - : Use @ref TSPI_RxFillLevel */ - uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. - : Use @ref TSPI_TxFIFOInterrupt */ - uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. - : Use @ref TSPI_TxInterrupt */ - uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. - : Use @ref TSPI_RxFIFOInterrupt */ - uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. - : Use @ref TSPI_RxInterrupt */ - uint32_t interr; /*!< Enable/Disable Error Interrupt. - : Use @ref TSPI_ErrorInterrupt */ - uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. - : Use @ref TSPI_TxDMAInterrupt */ - uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. - : Use @ref TSPI_RxDMAInterrupt */ -} tspi_control2_t; - -/*----------------------------------*/ -/** - * @struct tspi_control3_t - * @brief Control Setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tfempclr; /*!< Transmit Buffer Clear. - : Use @ref TSPI_Tx_Buffer_Clear */ - uint32_t rffllclr; /*!< Receive Buffer Clear. - : Use @ref TSPI_Rx_Buffer_Clear */ -} tspi_control3_t; - -/*----------------------------------*/ -/** - * @struct tspi_baudrate_t - * @brief Clock setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t brck; /*!< Baudrate Input Clock. - : Use @ref TSPI_Baudrate_Clock */ - uint32_t brs; /*!< Baudrate Divider. - : Use @ref TSPI_Baudrate_Divider */ -} tspi_baudrate_t; - -/*----------------------------------*/ -/** - * @struct tspi_fmtr0_t - * @brief Format control0. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t dir; /*!< Data Direction. - : Use @ref TSPI_DataDirection */ - uint32_t fl; /*!< Data Length. - : Use @ref TSPI_DataLength */ - uint32_t fint; /*!< Frame Interval time. - : Use @ref TSPI_Frame_Interval_Time */ - uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS3_Polarity */ - uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS2_Polarity */ - uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS1_Polarity */ - uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. - : Use @ref TSPI_TSPIxCS0_Polarity */ - uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. - : Use @ref TSPI_Serial_Clock_Polarity */ - uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. - : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ - uint32_t csint; /*!< Minimum IDLE Time. - : Use @ref TSPI_Minimum_IDLE_Time */ - uint32_t cssckdl; /*!< Serial Clock Delay. - : Use @ref TSPI_Serial_Clock_Delay */ - uint32_t sckcsdl; /*!< Negate Delay. - : Use @ref TSPI_Negate_Delay */ -} tspi_fmtr0_t; - -/*----------------------------------*/ -/** - * @struct tspi_fmtr1_t - * @brief Format control1. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t reserved; /*!< SIO Slave MOde. - : */ - uint32_t vpe; /*!< Enable/Disable Parity Function. - : Use @ref TSPI_ParityEnable */ - uint32_t vpm; /*!< Odd/Even Parity Bit. - : Use @ref TSPI_ParityBit */ -} tspi_fmtr1_t; - -/*----------------------------------*/ -/** - * @struct tspi_status_t - * @brief Status register. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. - : Use @ref TSPI_Status_Setting_flag */ - uint32_t txrun; /*!< Stop/Active Tx Active Flag. - : Use @ref TSPI_TxState */ - uint32_t txend; /*!< Tx Data Send Complete Flag. - : Use @ref TSPI_TxDone */ - uint32_t inttxwf; /*!< Tx FIFO Interrpt Flag. - : Use @ref TSPI_TxFIFOInterruptFlag */ - uint32_t tfemp; /*!< Tx FIFO Empty Flag. - : Use @ref TSPI_TxFIFOEmptyFlag */ - uint32_t tlvll; /*!< Tx Reach Fill Level - : Use @ref TSPI_TxReachFillLevel */ - uint32_t rxrun; /*!< Stop/Active Rx Active Flag. - : Use @ref TSPI_RxState */ - uint32_t rxend; /*!< Rx Data Receive Complete Flag. - : Use @ref TSPI_RxDone */ - uint32_t intrxff; /*!< Rx FIFO Interrpt Flag - : Use @ref TSPI_RxFIFOInterruptFlag */ - uint32_t rffll; /*!< Rx FIFO Full Flag - : Use @ref TSPI_RxFIFOFullFlag */ - uint32_t rlvl; /*!< Rx Reach Fill Level - : Use @ref TSPI_RxReachFillLevel */ -} tspi_status_t; - -/*----------------------------------*/ -/** - * @struct tspi_error_t - * @brief Error flag. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t udrerr; /*!< Underrun Error. - : Use @ref TSPI_UnderrunErr */ - uint32_t ovrerr; /*!< Overrun Error. - : Use @ref TSPI_OverrunErr */ - uint32_t perr; /*!< Parity Error. - : Use @ref TSPI_ParityErr */ -} tspi_error_t; - - -/*----------------------------------*/ -/** - * @struct tspi_initial_setting_t - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - tspi_control1_t cnt1; /*!< Control1 setting. - : Use @ref tspi_control1_t */ - tspi_control2_t cnt2; /*!< Control2 setting. - : Use @ref tspi_control2_t */ - tspi_control3_t cnt3; /*!< Control2 setting. - : Use @ref tspi_control2_t */ - tspi_baudrate_t brd; /*!< Baudrate setting. - : Use @ref tspi_baudrate_t */ - tspi_fmtr0_t fmr0; /*!< Format control0 setting. - : Use @ref tspi_fmtr0_t */ - tspi_fmtr1_t fmr1; /*!< Format control1 setting. - : Use @ref tspi_fmtr1_t */ -} tspi_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief TSPI handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct tspi_handle -{ - TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ - tspi_initial_setting_t init; /*!< Initial setting. */ - uint32_t errcode; /*!< ErrorCode */ - /*------------------------------------------*/ - /*! - @brief Transmit Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t rp; /*!< Num of transmited data. */ - tspi_transmit_t info; /*!< Transmit Data Information. */ - uint8_t tx_allign; /*!< Transmit Data length Information. */ - void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ - } transmit; - /*------------------------------------------*/ - /*! - @brief Receive Informatin. - */ - /*------------------------------------------*/ - struct - { - tspi_receive_t info; /*!< Receive Data Information. */ - uint8_t rx_allign; /*!< Receive Data length Information. */ - void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ - } receive; -} tspi_t; -/** - * @} - */ /* End of group TSPI_Exported_Typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Exported_functions TSPI Exported Functions - * @{ - */ -TXZ_Result tspi_init(tspi_t *p_obj); -TXZ_Result tspi_deinit(tspi_t *p_obj); -TXZ_Result tspi_format(tspi_t *p_obj); -TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); -TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); -TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); -TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); -TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); -TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info); -void tspi_irq_handler_transmit(tspi_t *p_obj); -void tspi_irq_handler_receive(tspi_t *p_obj); -void tspi_error_irq_handler(tspi_t *p_obj); -TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); -TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); -TXZ_Result tspi_error_clear(tspi_t *p_obj); -TXZ_Result tspi_discard_transmit(tspi_t *p_obj); -TXZ_Result tspi_discard_receive(tspi_t *p_obj); -/** - * @} - */ /* End of group TSPI_Exported_functions */ -/** - * @} - */ /* End of group TSPI */ -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __TSPI_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart.h deleted file mode 100644 index fb78eb6e171..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart.h +++ /dev/null @@ -1,812 +0,0 @@ -/** - ******************************************************************************* - * @file txz_uart.h - * @brief This file provides all the functions prototypes for UART driver. - * @version V1.0.0.0 - * $Date:: 2017-07-21 15:39:36 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __UART_H -#define __UART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @defgroup UART UART - * @brief UART Driver. - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Exported_define UART Exported Define - * @{ - */ - -/** - * @defgroup UART_FifoMax Max Num of FIFO - * @brief Max Num of Tx/Rx Fifo. - * @{ - */ -#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */ -#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */ -/** - * @} - */ /* End of group UART_FifoMax */ - -/** - * @defgroup UART_HalfClockSelect Half Clock Select - * @brief Output Terminal Select - * @{ - */ -#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */ -#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */ -/** - * @} - */ /* End of group UART_HalfClockSelect */ - -/** - * @defgroup UART_HalfClockMode Half Clock Mode - * @brief Half Clock Mode Setting. - * @{ - */ -#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */ -#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */ -/** - * @} - */ /* End of group UART_HalfClockMode */ - -/** - * @defgroup UART_HalfClockCTR Half Clock Mode Control - * @brief Half Clock Control. - * @{ - */ -#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */ -#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */ -/** - * @} - */ /* End of group UART_HalfClockCTR */ - -/** - * @defgroup UART_LoopBack Loop Back Function - * @brief Half Clock Control. - * @{ - */ -#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */ -#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */ -/** - * @} - */ /* End of group UART_LoopBack */ - - -/** - * @defgroup UART_NoiseFilter Noise Filter - * @brief Noise Filter Setting. - * @{ - */ -#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */ -#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */ -#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */ -#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */ -#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */ -#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */ -#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */ -#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */ -/** - * @} - */ /* End of group UART_NoiseFilter */ - - -/** - * @defgroup UART_CTSHandshake CTS Handshake - * @brief Available CTS Handshake Macro Definisiton. - * @{ - */ -#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */ -/** - * @} - */ /* End of group UART_CTSHandshake */ - - -/** - * @defgroup UART_RTSHandshake RTS Handshake - * @brief Available RTS Handshake Macro Definisiton. - * @{ - */ -#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */ -/** - * @} - */ /* End of group UART_RTSHandshake */ - - -/** - * @defgroup UART_DataComplementation Data Complementation - * @brief Enable/Disable Data Signal Complementation Macro Definisiton. - * @{ - */ -#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */ -/** - * @} - */ /* End of group UART_DataComplementation */ - - -/** - * @defgroup UART_DataDirection Data Direction - * @brief Data Direction Macro Definisiton. - * @{ - */ -#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ -#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */ -/*! - * @} - */ /* End of group UART_DataDirection */ - - -/** - * @defgroup UART_StopBit Stop Bit - * @brief Stop Bit Macro Definisiton. - * @{ - */ -#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ -#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */ -/** - * @} - */ /* End of group UART_StopBit */ - - -/** - * @defgroup UART_ParityBit Parity Bit - * @brief Parity Bit Macro Definisiton. - * @{ - */ -#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ -#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */ -/** - * @} - */ /* End of group UART_ParityBit */ - - -/** - * @defgroup UART_ParityEnable Parity Enable - * @brief Enable/Disable Parity Macro Definisiton. - * @{ - */ -#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */ -/** - * @} - */ /* End of group UART_ParityEnable */ - - -/** - * @defgroup UART_DataLength Data Length - * @brief Data Length Macro Definisiton. - * @{ - */ -#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */ -#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */ -#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */ -/** - * @} - */ /* End of group UART_DataLength */ - - -/** - * @defgroup UART_TxFillLevelRange Tx Fill Level Range - * @brief Transmit Fill Level Range Macro Definisiton. - * @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)". - * @{ - */ -#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */ -#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */ -/*! - * @} - */ /* End of group UART_TxFillLevelRange */ - - -/** - * @defgroup UART_RxFillLevelRange Rx Fill Level Range - * @brief Receive Fill Level Range Macro Definisiton. - * @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)". - * @{ - */ -#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */ -#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */ -/** - * @} - */ /* End of group UART_RxFillLevelRange */ - - -/** - * @defgroup UART_TxFIFOInterrupt Tx FIFO Interrpt - * @brief Available Transmit FIFO Interrupt Macro Definisiton. - * @{ - */ -#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */ -/** - * @} - */ /* End of group UART_TxFIFOInterrupt */ - - -/** - * @defgroup UART_TxInterrupt Tx Interrpt - * @brief Available Transmit Interrupt Macro Definisiton. - * @{ - */ -#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */ -/** - * @} - */ /* End of group UART_TxInterrupt */ - - -/** - * @defgroup UART_RxFIFOInterrupt Rx FIFO Interrpt - * @brief Available Receive FIFO Interrupt Macro Definisiton. - * @{ - */ -#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ -/** - * @} - */ /* End of group UART_RxFIFOInterrupt */ - - -/** - * @defgroup UART_RxInterrupt Rx Interrpt - * @brief Available Receive Interrupt Macro Definisiton. - * @{ - */ -#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ -#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ -/** - * @} - */ /* End of group UART_RxInterrupt */ - - -/** - * @defgroup UART_ErrorInterrupt Error Interrupt - * @brief Enable/Disable Error Interrupt Macro Definisiton. - * @{ - */ -#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ -/** - * @} - */ /* End of group UART_ErrorInterrupt */ - - -/** - * @defgroup UART_Prescaler Prescaler - * @brief Prescaler Macro Definisiton. - * @{ - */ -#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */ -#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */ -#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */ -#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */ -#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */ -#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */ -#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */ -#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */ -#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */ -#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */ -/** - * @} - */ /* End of group UART_Prescaler */ - - -/** - * @defgroup UART_Clock_Mask Clock Mask - * @brief Clock Mask Macro Definisiton. - * @{ - */ -#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */ -/** - * @} - */ /* End of group UART_Clock_Mask */ - - -/** - * @defgroup UART_Division Division - * @brief Enable/Disable Division Macro Definisiton. - * @{ - */ -#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ -#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */ -/** - * @} - */ /* End of group UART_Division */ - - -/** - * @defgroup UART_RangeK Range K - * @brief Range of K Macro Definisiton. - * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)". - * @{ - */ -#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ -#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ -/** - * @} - */ /* End of group UART_RangeK */ - - -/** - * @defgroup UART_RangeN Range N - * @brief Range of N Macro Definisiton. - * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)". - * @{ - */ -#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */ -#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ -/** - * @} - */ /* End of group UART_RangeN */ - - -/** - * @defgroup UART_SettingEnable Setting Enable - * @brief Enable/Disable Setting Macro Definisiton. - * @{ - */ -#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */ -#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ -#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ -/** - * @} - */ /* End of group UART_SettingEnable */ - - -/** - * @defgroup UART_TxState Tx State - * @brief Transmitting State Macro Definisiton. - * @{ - */ -#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */ -#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ -#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */ -/** - * @} - */ /* End of group UART_TxState */ - - -/** - * @defgroup UART_TxDone Transmitting Done - * @brief Transmitting Done Macro Definisiton. - * @{ - */ -#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */ -#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */ -/** - * @} - */ /* End of group UART_TxDone */ - - -/** - * @defgroup UART_TxReachFillLevel Tx Reach Fill Level - * @brief Reach Transmitting Fill Level Macro Definisiton. - * @{ - */ -#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */ -#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */ -/** - * @} - */ /* End of group UART_TxReachFillLevel */ - - -/** - * @defgroup UART_TxFifoLevel Tx FIFO Fill Level - * @brief Transmitting FIFO Fill Level Macro Definisiton. - * @{ - */ -#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */ -/** - * @} - */ /* End of group UART_TxFifoLevel */ - - -/** - * @defgroup UART_RxState Rx State - * @brief Receive State Macro Definisiton. - * @{ - */ -#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */ -#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ -#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */ -/** - * @} - */ /* End of group UART_RxState */ - - -/** - * @defgroup UART_RxDone Rx Done - * @brief Receive Done Macro Definisiton. - * @{ - */ -#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */ -#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */ -/** - * @} - */ /* End of group UART_RxDone */ - - -/** - * @defgroup UART_RxReachFillLevel Rx Reach Fill Level - * @brief Reach Receive Fill Level Macro Definisiton. - * @{ - */ -#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */ -#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */ -/** - * @} - */ /* End of group UART_RxReachFillLevel */ - - -/** - * @defgroup UART_RxFifoLevel Rx FIFO Fill Level - * @brief Receive FIFO Fill Level Macro Definisiton. - * @{ - */ -#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */ -/** - * @} - */ /* End of group UART_RxFifoLevel */ - - -/** - * @defgroup UART_TriggerErr Trigger Error - * @brief Trigger Error Macro Definisiton. - * @{ - */ -#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */ -/** - * @} - */ /* End of group UART_TxTriggerErr */ - - -/** - * @defgroup UART_OverrunErr Overrun Error - * @brief Overrun Error Macro Definisiton. - * @{ - */ -#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ -/** - * @} - */ /* End of group UART_OverrunErr */ - - -/** - * @defgroup UART_ParityErr Parity Error - * @brief Parity Error Macro Definisiton. - * @{ - */ -#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */ -/** - * @} - */ /* End of group UART_ParityErr */ - - -/** - * @defgroup UART_FramingErr Framing Error - * @brief Framing Error Macro Definisiton. - * @{ - */ -#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */ -/** - * @} - */ /* End of group UART_FramingErr */ - - -/** - * @defgroup UART_BreakErr Break Error - * @brief Break Error Macro Definisiton. - * @{ - */ -#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ -#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */ -/** - * @} - */ /* End of group UART_BreakErr */ - -/** - * @} - */ /* End of group UART_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Exported_define UART Exported Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Exported_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Exported_typedef UART Exported Typedef - * @{ - */ - -/*----------------------------------*/ -/** - * @brief Receive event information structure definenition. - * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this. - * @attention "num" must be over FIFO max num. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} uart_receive8_t; - -/*----------------------------------*/ -/** - * @brief Receive event information structure definenition. - * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to receive data. */ - uint32_t num; /*!< The number of receive data. */ -} uart_receive16_t; - -/*----------------------------------*/ -/** - * @brief Receive event information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - uart_receive8_t rx8; /*!< @ref uart_receive8_t */ - uart_receive16_t rx16; /*!< @ref uart_receive16_t */ -} uart_receive_t; - -/*----------------------------------*/ -/** - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint8_t *p_data; /*!< The buffer to transmit data. */ - uint32_t num; /*!< The number of transmit data. */ -} uart_transmit8_t; - -/*----------------------------------*/ -/** - * @brief Transmit data information structure definenition. - * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this. -*/ -/*----------------------------------*/ -typedef struct -{ - uint16_t *p_data; /*!< The buffer to transmit data. - Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */ - uint32_t num; /*!< The number of transmit data. */ -} uart_transmit16_t; - -/*----------------------------------*/ -/** - * @brief Transmit data information structure definenition. -*/ -/*----------------------------------*/ -typedef union -{ - uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */ - uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */ -} uart_transmit_t; - -/*----------------------------------*/ -/** - * @brief Clock setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t prsel; /*!< Prescaler. - : Use @ref UART_Prescaler */ -} uart_clock_t; - -/*----------------------------------*/ -/** - * @brief Boudrate setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t ken; /*!< Enable/Disable Division Definisiton. - : Use @ref UART_Division */ - uint32_t brk; /*!< Division Value K. - : K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */ - uint32_t brn; /*!< Division Value N. - : N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */ -} uart_boudrate_t; - -/*----------------------------------*/ -/** - * @brief Transmit FIFO setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t inttx; /*!< Available Transmit FIFO Interrupt. - : Use @ref UART_TxFIFOInterrupt */ - uint32_t level; /*!< Transmit Fill Level. - : Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */ -} uart_tx_fifo_t; - -/*----------------------------------*/ -/** - * @brief Receive FIFO setting. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t intrx; /*!< Available Receive FIFO Interrupt. - : Use @ref UART_RxFIFOInterrupt */ - uint32_t level; /*!< Receive Fill Level. - : Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */ -} uart_rx_fifo_t; - -/*----------------------------------*/ -/** - * @brief Initial setting structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - uint32_t id; /*!< ID: User value. */ - uart_clock_t clock; /*!< Clock setting. - : Use @ref uart_clock_t */ - uart_boudrate_t boudrate; /*!< Boudrate setting. - : Use @ref uart_boudrate_t */ - uint32_t inttx; /*!< Available Transmit Interrupt. - : Use @ref UART_TxInterrupt */ - uint32_t intrx; /*!< Available Receive Interrupt. - : Use @ref UART_RxInterrupt */ - uint32_t interr; /*!< Available Error Interrupt. - : Use @ref UART_ErrorInterrupt */ - uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting. - : Use @ref uart_tx_fifo_t */ - uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting. - : Use @ref uart_rx_fifo_t */ - uint32_t hct; /*!< Half Clock Terminal Select. - : Use @ref UART_HalfClockSelect */ - uint32_t hcm; /*!< Half Clock Mode Select. - : Use @ref UART_HalfClockMode */ - uint32_t hcc; /*!< Half Clock Control. - : Use @ref UART_HalfClockCTR */ - uint32_t lbc; /*!< Loop Back Control. - : Use @ref UART_LoopBack */ - uint32_t nf; /*!< UTxRXD Noise Filter. - : Use @ref UART_NoiseFilter */ - uint32_t ctse; /*!< Available CTS Handshake. - : Use @ref UART_CTSHandshake */ - uint32_t rtse; /*!< Available RTS Handshake. - : Use @ref UART_RTSHandshake */ - uint32_t iv; /*!< Data Signal Complementation. - : Use @ref UART_DataComplementation */ - uint32_t dir; /*!< Data Direction. - : Use @ref UART_DataDirection */ - uint32_t sblen; /*!< Stop Bit. - : Use @ref UART_StopBit */ - uint32_t even; /*!< Odd/Even Parity Bit. - : Use @ref UART_ParityBit */ - uint32_t pe; /*!< Enable/Disable Parity Bit. - : Use @ref UART_ParityEnable */ - uint32_t sm; /*!< Data Length. - : Use @ref UART_DataLength */ -} uart_initial_setting_t; - -/*----------------------------------*/ -/** - * @brief UART handle structure definenition. -*/ -/*----------------------------------*/ -typedef struct -{ - TSB_UART_TypeDef *p_instance; /*!< Registers base address. */ - uart_initial_setting_t init; /*!< Initial setting. */ - /*------------------------------------------*/ - /*! - @brief Transmit Informatin. - */ - /*------------------------------------------*/ - struct - { - uint32_t rp; /*!< Num of transmited data. */ - uart_transmit_t info; /*!< Transmit Data Information. */ - void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ - } transmit; - /*------------------------------------------*/ - /*! - @brief Receive Informatin. - */ - /*------------------------------------------*/ - struct - { - uart_receive_t info; /*!< Receive Data Information. */ - void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */ - } receive; -} uart_t; - -/** - * @} - */ /* End of group UART_Exported_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Exported_functions UART Exported Functions - * @{ - */ -TXZ_Result uart_init(uart_t *p_obj); -TXZ_Result uart_deinit(uart_t *p_obj); -TXZ_Result uart_discard_transmit(uart_t *p_obj); -TXZ_Result uart_discard_receive(uart_t *p_obj); -TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info); -TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info); -void uart_transmit_irq_handler(uart_t *p_obj); -void uart_receive_irq_handler(uart_t *p_obj); -void uart_error_irq_handler(uart_t *p_obj); -TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status); -TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error); -TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting); -/** - * @} - */ /* End of group UART_Exported_functions */ - -/** - * @} - */ /* End of group UART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __UART_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart_include.h b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart_include.h deleted file mode 100644 index 95357511930..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/inc/txz_uart_include.h +++ /dev/null @@ -1,476 +0,0 @@ -/** - ******************************************************************************* - * @file txz_uart_include.h - * @brief This file provides internal common definition. - * @version V1.0.0.0 - * $Date:: 2017-07-21 15:39:36 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -/*------------------------------------------------------------------------------*/ -/* Define to prevent recursive inclusion */ -/*------------------------------------------------------------------------------*/ -#ifndef __UART_INCLUDE_H -#define __UART_INCLUDE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_driver_def.h" - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup UART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Private_define - * @{ - */ - -/** - * @defgroup UART_NullPointer Null Pointer - * @brief Null Pointer. - * @{ - */ -#define UART_NULL ((void *)0) -/** - * @} - */ /* End of group UART_NullPointer */ - -/** - * @defgroup UART_ParameterResult Parameter Check Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of group UART_ParameterResult */ - -/** - * @defgroup UARTxSWRST UARTxSWRST Register - * @brief UARTxSWRST Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-8 | - | - * | 7 | SWRSTF | - * | 6:2 | - | - * | 1:0 | SWRST | - * @{ - */ -/* SWRSTF */ -#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */ -#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */ -#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */ -/* SWRST */ -#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */ -#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */ -/** - * @} - */ /* End of group UARTxSWRST */ - -/** - * @defgroup UARTxCR0 UARTxCR0 Register - * @brief UARTxCR0 Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-19 | - | - * | 18 | HBSST | - * | 17 | HBSMD | - * | 16 | HBSEN | - * | 15 | LPB | - * | 14-12 | NF[2:0] | - * | 11 | - | - * | 10 | CTSE | - * | 9 | RTSE | - * | 8 | WU | - * | 7 | - | - * | 6 | IV | - * | 5 | DIR | - * | 4 | SBLEN | - * | 3 | EVEN | - * | 2 | PE | - * | 1-0 | SM[1:0] | - * @{ - */ -/* HBSST */ -#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */ -/* HBSMD */ -#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */ -/* HBSEN */ -#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */ -#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */ -#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */ -/* LPB */ -#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */ -#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */ -#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */ -/* WU */ -#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */ -#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */ -#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */ -/** - * @} - */ /* End of group UARTxCR0 */ - -/** - * @defgroup UARTxCR1 UARTxCR1 Register - * @brief UARTxCR1 Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-15 | - | - * | 14-12 | TIL[2:0] | - * | 11 | - | - * | 10-8 | RIL[2:0] | - * | 7 | INTTXFE | - * | 6 | INTTXWE | - * | 5 | INTRXFE | - * | 4 | INTRXWE | - * | 3 | - | - * | 2 | INTERR | - * | 1 | DMATE | - * | 0 | DMARE | - * @{ - */ -/* RIL */ -#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */ -/* DMATE */ -#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */ -#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */ -#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */ -/* DMARE */ -#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */ -#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */ -#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */ -/** - * @} - */ /* End of group UARTxCR1 */ - -/** - * @defgroup UARTxTRANS UARTxTRANS Register - * @brief UARTxTRANS Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-4 | - | - * | 3 | BK | - * | 2 | TXTRG | - * | 1 | TXE | - * | 0 | RXE | - * @{ - */ -/* BK */ -#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */ -#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */ -#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */ -/* TXTRG */ -#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */ -#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */ -#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */ -/* TXE */ -#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */ -#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */ -#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */ -/* RXE */ -#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */ -#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */ -#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */ -/* TXE,RXE */ -#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */ -/** - * @} - */ /* End of group UARTxTRANS */ - -/** - * @defgroup UARTxDR UARTxDR Register - * @brief UARTxDR Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-19 | - | - * | 18 | PERR | - * | 17 | FERR | - * | 16 | BERR | - * | 15:9 | - | - * | 8:0 | DR | - * @{ - */ -/* DR */ -#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */ -#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ -#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */ -/** - * @} - */ /* End of group UARTxDR */ - -/** - * @defgroup UARTxSR UARTxSR Register - * @brief UARTxSR Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31 | SUE | - * | 30:16 | - | - * | 15 | TXRUN | - * | 14 | TXEND | - * | 13 | TXFF | - * | 12 | - | - * | 11:8 | TLVL | - * | 7 | RXRUN | - * | 6 | RXEND | - * | 5 | RXFF | - * | 4 | - | - * | 3:0 | RLVL | - * @{ - */ -/* SUE */ -#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */ -/* TXEND */ -#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */ -#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */ -#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */ -/* TXFF */ -#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */ -#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */ -#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */ -/* TLVL */ -#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */ -/* RXEND */ -#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */ -#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */ -#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */ -/* RXFF */ -#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */ -#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */ -#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */ -/* RLVL */ -#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */ -/** - * @} - */ /* End of group UARTxSR */ - -/** - * @defgroup UARTxFIFOCLR UARTxFIFOCLR Register - * @brief UARTxFIFOCLR Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-2 | - | - * | 1 | TFCLR | - * | 0 | RFCLR | - * @{ - */ -/* TFCLR */ -#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */ -/* RFCLR */ -#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */ -/** - * @} - */ /* End of group UARTxFIFOCLR */ - -/** - * @defgroup UARTxERR UARTxERR Register - * @brief UARTxERR Register Definition. - * @details Detail. - * | Bit | Bit Symbol | - * | :--- | :--- | - * | 31-5 | - | - * | 4 | TRGERR | - * | 3 | OVRERR | - * | 2 | PERR | - * | 1 | FERR | - * | 0 | BERR | - * @{ - */ -/* TRGERR */ -#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */ -#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */ -#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */ -#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */ -/* OVRERR */ -#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */ -#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */ -#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */ -#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */ -/* PERR */ -#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */ -#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */ -#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */ -#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */ -/* FERR */ -#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */ -#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */ -#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */ -#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */ -/* BERR */ -#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */ -#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */ -#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */ -#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */ -/** - * @} - */ /* End of group UARTxERR */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Private_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Inline Functions */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Private_fuctions - * @{ - */ -__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); -__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); -__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); -__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); -/*--------------------------------------------------*/ -/** - * @brief Disable UARTxTRANS TXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 0; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 0; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable UARTxTRANS TXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 1; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 1; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Disable UARTxTRANS RXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 0; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 0; -#endif -} - -/*--------------------------------------------------*/ -/** - * @brief Enable UARTxTRANS RXE. - * @param p_instance: Instance address. - * @retval - - * @note Bitband Access - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) -{ -#ifdef DEBUG - if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) - { - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 1; - } -#else - (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 1; -#endif -} - - -/** - * @} - */ /* End of group UART_Private_functions */ - -/** - * @} - */ /* End of group UART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __UART_EX_H */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc.c deleted file mode 100644 index e7ecba3c6e6..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc.c +++ /dev/null @@ -1,1200 +0,0 @@ -/** - ******************************************************************************* - * @file adc.c - * @brief This file provides API functions for ADC driver. - * @version V1.0.0.0 - * $Date:: 2017-09-07 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "adc_include.h" -#include "adc_ch.h" -#include "adc.h" - -#if defined(__ADC_H) -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @addtogroup ADC - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - - -/** - * @} - */ /* End of group ADC_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_macro ADC Private Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_Enumeration ADC Private Enumeration - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_Enumeration */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_typedef ADC Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Variable Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_variable ADC Private Variable Definition - * @{ - */ -static adc_t *p_AdcObj; -/** - * @} - */ /* End of group ADC_Private_variable */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_fuctions ADC Private Fuctions - * @{ - */ -static int32_t check_param_sampling_period0(adc_sampling_period0_t param); -static int32_t check_param_sampling_period1(adc_sampling_period1_t param); -static int32_t check_param_prescaler_output(adc_sclk_t param); -static int32_t check_param_interrupt(adc_int_t param); -static int32_t check_param_type(adc_conversion_t param); -static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max); -static void clear_ch_instance_info(adc_ch_t *p_ch); - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_sampling_period0(adc_sampling_period0_t param) - * @brief Check the Sampling Period's parameter. - * @param[in] param :Sampling Period's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_sampling_period0(adc_sampling_period0_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_SAMPLING_PERIOD0_XN: - case ADC_SAMPLING_PERIOD0_X2N: - case ADC_SAMPLING_PERIOD0_X3N: - case ADC_SAMPLING_PERIOD0_X4N: - case ADC_SAMPLING_PERIOD0_X16N: - case ADC_SAMPLING_PERIOD0_X64N: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_sampling_period1(adc_sampling_period1_t param) - * @brief Check the Sampling Period's parameter. - * @param[in] param :Sampling Period's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_sampling_period1(adc_sampling_period1_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_SAMPLING_PERIOD1_XN: - case ADC_SAMPLING_PERIOD1_X2N: - case ADC_SAMPLING_PERIOD1_X3N: - case ADC_SAMPLING_PERIOD1_X4N: - case ADC_SAMPLING_PERIOD1_X16N: - case ADC_SAMPLING_PERIOD1_X64N: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_prescaler_output(adc_sclk_t param) - * @brief Check the AD Prescaler Output's parameter. - * @param[in] param :AD Prescaler Output's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_SCLK"ADC_SCLK_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_prescaler_output(adc_sclk_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_SCLK_1: - case ADC_SCLK_2: - case ADC_SCLK_4: - case ADC_SCLK_8: - case ADC_SCLK_16: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_interrupt(adc_int_t param) - * @brief Check the Interrupt's parameter. - * @param[in] param :Interrupt's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_IntEnable"ADC_INT_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_interrupt(adc_int_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_INT_DISABLE: - case ADC_INT_ENABLE: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_type(adc_conversion_t param) - * @brief Check the Conversion Type's parameter. - * @param[in] param :Conversion Type's parameter - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note Macro definition is ADC_Conversion"ADC_CONVERSION_xxxx". - */ -/*--------------------------------------------------*/ -static int32_t check_param_type(adc_conversion_t param) -{ - int32_t result = ADC_PARAM_NG; - - switch (param) - { - case ADC_CONVERSION_DISABLE: - case ADC_CONVERSION_CNT: - case ADC_CONVERSION_SGL: - case ADC_CONVERSION_TRG: - case ADC_CONVERSION_HPTG: - result = ADC_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) - * @brief Check the AIN Range's parameter. - * @param[in] ain :AIN Range's parameter - * @param[in] min :Range Min. - * @param[in] max :Range Max. - * @retval ADC_PARAM_OK :Success. - * @retval ADC_PARAM_NG :Failure. - * @note - - */ -/*--------------------------------------------------*/ -static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) -{ - int32_t result = ADC_PARAM_NG; - - if (min == 0) - { - if (ain <= max) - { - result = ADC_PARAM_OK; - } - } - else - { - if ((min <= ain) && (ain <= max)) - { - result = ADC_PARAM_OK; - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn static void clear_ch_instance_info(adc_ch_t *p_ch) - * @brief Channel Instance Information Clear. - * @param[in] p_ch :Channel Instance Address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -static void clear_ch_instance_info(adc_ch_t *p_ch) -{ - p_ch->p_tset = ADC_NULL; - p_ch->p_reg = ADC_NULL; - p_ch->init.type = ADC_CONVERSION_DISABLE; -} -/*--------------------------------------------------*/ -/*! - * @fn static void adc_compa_irq_handler( void ) - * @brief IRQ Handler for Compare_A done. - * @param - - * @retval - - * @note Call by Compare_A Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_compa_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->init.CMPxEN[0].handle != ADC_NULL)) - { - p_AdcObj->init.CMPxEN[0].handle(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_compb_irq_handler( void ) - * @brief IRQ Handler for Compare_B done. - * @param - - * @retval - - * @note Call by Compare_B Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_compb_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->init.CMPxEN[1].handle != ADC_NULL)) - { - p_AdcObj->init.CMPxEN[1].handle(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_single_irq_handler( void ) - * @brief IRQ Handler for single conversion done. - * @param - - * @retval - - * @note Call by Single Conversion Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_single_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->handler.single != ADC_NULL)) - { - p_AdcObj->handler.single(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_continuity_irq_handler( void ) - * @brief IRQ Handler for continuity conversion done. - * @param - - * @retval - - * @note Call by Continuity Conversion Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_continuity_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->handler.continuity != ADC_NULL)) - { - p_AdcObj->handler.continuity(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_trigger_irq_handler( void ) - * @brief IRQ Handler for trigger conversion done. - * @param - - * @retval - - * @note Call by Trigger Conversion Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_trigger_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->handler.trigger != ADC_NULL)) - { - p_AdcObj->handler.trigger(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/*--------------------------------------------------*/ -/*! - * @fn static void adc_highpriority_irq_handler( void ) - * @brief IRQ Handler for highpriority conversion done. - * @param - - * @retval - - * @note Call by HigPriority Conversion Done IRQ Handler. - */ -/*--------------------------------------------------*/ -void adc_highpriority_irq_handler( void ) -{ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if ((p_AdcObj != ADC_NULL) && - (p_AdcObj->handler.highpriority != ADC_NULL)) - { - p_AdcObj->handler.highpriority(p_AdcObj->init.id, TXZ_SUCCESS); - } -} - -/** - * @} - */ /* End of group ADC_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup ADC_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_init(adc_t *p_obj) - * @brief Initialize the ADC object. - * @param[in] p_obj :ADC object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. After initialization, 3us of stabilization time is needed. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_init(adc_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - /* Check the parameter. */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if ((void*)(p_obj->p_instance) == (void*)0) - { - result = TXZ_ERROR; - } - if (check_param_sampling_period0(p_obj->init.clk.exaz0) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if (check_param_sampling_period1(p_obj->init.clk.exaz1) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if (p_obj->init.clk.sampling_select > 0x0100000) - { - result = TXZ_ERROR; - } - if (check_param_prescaler_output(p_obj->init.clk.vadcld) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if(result == TXZ_SUCCESS) - { - /*------------------------------*/ - /* Init Variable */ - /*------------------------------*/ - uint32_t i; - - for (i=0; iinfo.ch[i]); - } - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxCLK ---*/ - p_obj->p_instance->CLK = ((uint32_t)p_obj->init.clk.exaz0 | (uint32_t)p_obj->init.clk.exaz1 | (uint32_t)p_obj->init.clk.vadcld); - /*--- ADxEXAZSEL ---*/ - p_obj->p_instance->EXAZSEL = (uint32_t)p_obj->init.clk.sampling_select; - /*--- ADxMOD0 ---*/ - p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); - /*--- ADxMOD1 ---*/ - p_obj->p_instance->MOD1 = p_obj->init.mod1; - /*--- ADxMOD2 ---*/ - p_obj->p_instance->MOD2 = p_obj->init.mod2; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_deinit(adc_t *p_obj) - * @brief Release the ADC object. - * @param[in] p_obj :ADC object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_deinit(adc_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t i; - adc_ch_t *p_ch; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxCR0 ---*/ - p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); - /*------------------------------*/ - /* Wait Stop */ - /*------------------------------*/ - /*--- ADxST ---*/ - /* When all convetion stop, ADxST is set "0". */ - while(p_obj->p_instance->ST != 0) - { - /* no processing */ - } - /*------------------------------*/ - /* Channel Class Destruct */ - /*------------------------------*/ - for (i=0; iinfo.ch[i]; - if (p_ch->init.type == ADC_CONVERSION_DISABLE) - { - if (adc_ch_deinit(p_ch) == TXZ_SUCCESS) - { - clear_ch_instance_info(p_ch); - } - } - } - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxCMPEN ---*/ - p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE); - /*--- ADxCR1 ---*/ - p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); - /*--- ADxMOD0 ---*/ - p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF); - /*--- ADxMOD1 ---*/ - p_obj->p_instance->MOD1 = ADC_MOD1_SCLK_3; - /*--- ADxMOD2 ---*/ - p_obj->p_instance->MOD2 = ADC_MOD2_CLEAR; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) - * @brief ADC Channel Setting - * @param[in] p_obj :ADC object. - * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). - * @param[in] p_setting :Channel Setting Source Address. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0) || - ((void*)(p_setting) == (void*)0) || - (ch >= ADC_NUM_MAX)) - { - result = TXZ_ERROR; - } - if (check_param_interrupt((adc_int_t)p_setting->interrupt) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if (check_param_type((adc_conversion_t)p_setting->type) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if (check_param_ain((adc_ain_range_t)p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX) == ADC_PARAM_NG) - { - result = TXZ_ERROR; - } - if(result == TXZ_SUCCESS) - { - /*------------------------------*/ - /* Channel Class Construct */ - /*------------------------------*/ - adc_ch_t *p_ch = &p_obj->info.ch[ch]; - - p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch); - p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch); - p_ch->init.interrupt = p_setting->interrupt; - p_ch->init.type = p_setting->type; - p_ch->init.ain = p_setting->ain; - result = adc_ch_init(p_ch); - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) - * @brief ADC Channel Clear - * @param[in] p_obj :ADC object. - * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - (ch >= ADC_NUM_MAX)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Channel Class Destruct */ - /*------------------------------*/ - adc_ch_t *p_ch = &p_obj->info.ch[ch]; - - result = adc_ch_deinit(p_ch); - /* Init Variable */ - clear_ch_instance_info(p_ch); - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) - * @brief Initialize the ADC Compare register - * @param[in] p_obj :ADC object. - * @param[in] p_cmpx_t :Clock information structure. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - * @attention After initialization, 3us of stabilization time is needed. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_cmpx_t) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Init Variable */ - /*------------------------------*/ - if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) - { - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; - } - if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) - { - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; - } - if (p_cmpx_t->CMPEN == ADCMP2EN_DISABLE) - { - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP2EN_ENABLE; - } - if (p_cmpx_t->CMPEN == ADCMP3EN_DISABLE) - { - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP3EN_ENABLE; - } - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - if (p_cmpx_t->CMPEN == ADCMP0EN_ENABLE) - { - p_obj->init.CMPxEN[0].CMPEN = p_cmpx_t->CMPEN; - p_obj->init.CMPxEN[0].CMPCNT = p_cmpx_t->CMPCNT; - p_obj->init.CMPxEN[0].CMPCond = p_cmpx_t->CMPCond; - p_obj->init.CMPxEN[0].CMPBigSml = p_cmpx_t->CMPBigSml; - p_obj->init.CMPxEN[0].StrReg = p_cmpx_t->StrReg; - p_obj->init.CMPxEN[0].ADComp = p_cmpx_t->ADComp; - p_obj->init.CMPxEN[0].handle = p_cmpx_t->handle; - p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; - p_obj->p_instance->CMPCR0 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; - p_obj->p_instance->CMP0 = p_cmpx_t->ADComp; - } - else if (p_cmpx_t->CMPEN == ADCMP1EN_ENABLE) - { - p_obj->init.CMPxEN[1].CMPEN = p_cmpx_t->CMPEN; - p_obj->init.CMPxEN[1].CMPCNT = p_cmpx_t->CMPCNT; - p_obj->init.CMPxEN[1].CMPCond = p_cmpx_t->CMPCond; - p_obj->init.CMPxEN[1].CMPBigSml = p_cmpx_t->CMPBigSml; - p_obj->init.CMPxEN[1].StrReg = p_cmpx_t->StrReg; - p_obj->init.CMPxEN[1].ADComp = p_cmpx_t->ADComp; - p_obj->init.CMPxEN[1].handle = p_cmpx_t->handle; - p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; - p_obj->p_instance->CMPCR1 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; - p_obj->p_instance->CMP1 = p_cmpx_t->ADComp; - } - else if (p_cmpx_t->CMPEN == ADCMP2EN_ENABLE) - { - p_obj->init.CMPxEN[2].CMPEN = p_cmpx_t->CMPEN; - p_obj->init.CMPxEN[2].CMPCNT = p_cmpx_t->CMPCNT; - p_obj->init.CMPxEN[2].CMPCond = p_cmpx_t->CMPCond; - p_obj->init.CMPxEN[2].CMPBigSml = p_cmpx_t->CMPBigSml; - p_obj->init.CMPxEN[2].StrReg = p_cmpx_t->StrReg; - p_obj->init.CMPxEN[2].ADComp = p_cmpx_t->ADComp; - p_obj->init.CMPxEN[2].handle = p_cmpx_t->handle; - p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; - p_obj->p_instance->CMPCR2 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; - p_obj->p_instance->CMP2 = p_cmpx_t->ADComp; - } - else if (p_cmpx_t->CMPEN == ADCMP3EN_ENABLE) - { - p_obj->init.CMPxEN[3].CMPEN = p_cmpx_t->CMPEN; - p_obj->init.CMPxEN[3].CMPCNT = p_cmpx_t->CMPCNT; - p_obj->init.CMPxEN[3].CMPCond = p_cmpx_t->CMPCond; - p_obj->init.CMPxEN[3].CMPBigSml = p_cmpx_t->CMPBigSml; - p_obj->init.CMPxEN[3].StrReg = p_cmpx_t->StrReg; - p_obj->init.CMPxEN[3].ADComp = p_cmpx_t->ADComp; - p_obj->init.CMPxEN[3].handle = p_cmpx_t->handle; - p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; - p_obj->p_instance->CMPCR3 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; - p_obj->p_instance->CMP3 = p_cmpx_t->ADComp; - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) - * @brief Release the ADC Compare register - * @param[in] p_obj :ADC object. - * @param[in] p_cmpx_t :Clock information structure. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - * @attention After initialization, 3us of stabilization time is needed. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) -{ - TXZ_Result result = TXZ_SUCCESS; - p_AdcObj = p_obj; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_cmpx_t) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) - { - p_obj->init.CMPxEN[0].CMPEN = 0; - p_obj->init.CMPxEN[0].CMPCNT = 0; - p_obj->init.CMPxEN[0].CMPCond = 0; - p_obj->init.CMPxEN[0].CMPBigSml = 0; - p_obj->init.CMPxEN[0].StrReg = 0; - p_obj->init.CMPxEN[0].ADComp = 0; - p_obj->init.CMPxEN[0].handle = (void*)0; - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; - p_obj->p_instance->CMPCR0 = 0; - p_obj->p_instance->CMP0 = 0; - } - else if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) - { - p_obj->init.CMPxEN[1].CMPEN = 0; - p_obj->init.CMPxEN[1].CMPCNT = 0; - p_obj->init.CMPxEN[1].CMPCond = 0; - p_obj->init.CMPxEN[1].CMPBigSml = 0; - p_obj->init.CMPxEN[1].StrReg = 0; - p_obj->init.CMPxEN[1].ADComp = 0; - p_obj->init.CMPxEN[1].handle = (void*)0; - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; - p_obj->p_instance->CMPCR1 = 0; - p_obj->p_instance->CMP1 = 0; - } - else if (p_cmpx_t->CMPEN == ADCMP2EN_DISABLE) - { - p_obj->init.CMPxEN[2].CMPEN = 0; - p_obj->init.CMPxEN[2].CMPCNT = 0; - p_obj->init.CMPxEN[2].CMPCond = 0; - p_obj->init.CMPxEN[2].CMPBigSml = 0; - p_obj->init.CMPxEN[2].StrReg = 0; - p_obj->init.CMPxEN[2].ADComp = 0; - p_obj->init.CMPxEN[2].handle = (void*)0; - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP2EN_ENABLE; - p_obj->p_instance->CMPCR2 = 0; - p_obj->p_instance->CMP2 = 0; - } - else if (p_cmpx_t->CMPEN == ADCMP3EN_DISABLE) - { - p_obj->init.CMPxEN[3].CMPEN = 0; - p_obj->init.CMPxEN[3].CMPCNT = 0; - p_obj->init.CMPxEN[3].CMPCond = 0; - p_obj->init.CMPxEN[3].CMPBigSml = 0; - p_obj->init.CMPxEN[3].StrReg = 0; - p_obj->init.CMPxEN[3].ADComp = 0; - p_obj->init.CMPxEN[3].handle = (void*)0; - p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP3EN_ENABLE; - p_obj->p_instance->CMPCR3 = 0; - p_obj->p_instance->CMP3 = 0; - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) - * @brief Get AD value - * @param[in] p_obj :ADC object. - * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). - * @param p_value :AD value. Destination address. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) -{ - TXZ_Result result = TXZ_ERROR; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0) || - ((void*)(p_value) == (void*)0) || - (ch >= ADC_NUM_MAX)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Get Value */ - /*------------------------------*/ - adc_ch_t *p_ch = &p_obj->info.ch[ch]; - - result = adc_ch_get_value(p_ch, p_value); - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_start(adc_t *p_obj) - * @brief Start Conversion. - * @param[in] p_obj :ADC object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_start(adc_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Enable Conversion */ - /*------------------------------*/ - uint32_t i; - adc_ch_t *p_ch; - uint32_t cr0 = (ADxCR0_ADEN_ENABLE | ADxCR0_CNT_DISABLE); - uint32_t cr1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); - - for (i=0; iinfo.ch[i]; - switch (p_ch->init.type) - { - case ADC_CONVERSION_CNT: - cr0 |= ADxCR0_CNT_ENABLE; - break; - case ADC_CONVERSION_SGL: - cr0 |= ADxCR0_SGL_ENABLE; - break; - case ADC_CONVERSION_TRG: - cr1 |= ADxCR1_TRGEN_ENABLE; - break; - case ADC_CONVERSION_HPTG: - cr1 |= ADxCR1_HPTRGEN_ENABLE; - break; - default: - /* no processing */ - break; - } - } - /*--- ADxCR1 ---*/ - p_obj->p_instance->CR1 = cr1; - /*--- ADxCR0 ---*/ - p_obj->p_instance->CR0 = cr0; - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_stop(adc_t *p_obj) - * @brief Stop Conversion. - * @param[in] p_obj :ADC object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_stop(adc_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t i; - adc_ch_t *p_ch; - uint32_t value; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Disable Conversion */ - /*------------------------------*/ - /*--- ADxCR0 ---*/ - p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); - /*------------------------------*/ - /* Wait Stop */ - /*------------------------------*/ - /*--- ADxST ---*/ - /* When all convetion stop, ADxST is set "0". */ - while(p_obj->p_instance->ST != 0) - { - /* no processing */ - } - /*------------------------------*/ - /* Dummy Read */ - /*------------------------------*/ - /* Read is needed before the next convertion. */ - for (i=0; iinfo.ch[i]; - if (p_ch->init.type == ADC_CONVERSION_DISABLE) - { - if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS) - { - /* no processing */ - } - } - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) - * @brief Wait for single conversion to be completed - * @param[in] p_obj :ADC object. - * @param[in] timeout :Timeout(tick). - * @retval TXZ_DONE :Success. - * @retval TXZ_BUSY :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) -{ - TXZ_WorkState result = TXZ_BUSY; - TXZ_WorkState loopBreak = TXZ_BUSY; - uint32_t base = hal_get_tick(); - uint32_t current = 0; - uint32_t status; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0)) - { - result = TXZ_DONE; - } - else - { - /*------------------------------*/ - /* Check Status */ - /*------------------------------*/ - while(loopBreak == TXZ_BUSY) - { - /*--- Check Status ---*/ - /* Read status. */ - status = p_obj->p_instance->ST; - /* Check status. */ - if ((status & ADxST_SNGF_MASK) == ADxST_SNGF_IDLE) - { - result = TXZ_DONE; - loopBreak = TXZ_DONE; - } - else - { - /*--- Check Timeout ---*/ - if (timeout == 0) - { - loopBreak = TXZ_DONE; - } - else - { - current = hal_get_tick(); - if (current > base) - { - if ((current - base) >= timeout) - { - loopBreak = TXZ_DONE; - } - } - else - { - base = current; - } - } - } - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @fn TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) - * @brief Get Conversion Status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-8 | - | - | - * | 7 | ADBF | AD Running Flag. Use @ref adc_status_t. | - * | 6-4 | - | - | - * | 3 | CNTF | Continuity Conversion Running Flag. Use @ref adc_cnt_status_t. | - * | 2 | SNGF | Single Conversion Running Flag. Use @ref adc_sgl_status_t. | - * | 1 | TRGF | Trigger Conversion Running Flag. Use @ref adc_trg_status_t. | - * | 0 | - | - | - * - * @param[in] p_obj :ADC object. - * @param[out] p_status :Conversion Status. Destination address. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((void*)(p_obj->p_instance) == (void*)0) || - ((void*)(p_status) == (void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Read Register */ - /*------------------------------*/ - *p_status = p_obj->p_instance->ST; - } - - return (result); -} -/** - * @} - */ /* End of group ADC_Exported_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__ADC_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc_ch.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc_ch.c deleted file mode 100644 index cddd4de4cf4..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/adc_ch.c +++ /dev/null @@ -1,351 +0,0 @@ -/** - ******************************************************************************* - * @file adc_ch.c - * @brief This file provides API functions for ADC driver. \n - * Channel Class. - * @version V1.0.0.0 - * $Date:: 2017-09-07 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "adc_include.h" -#include "adc_ch.h" - -#if defined(__ADC_CH_H) -/** - * @addtogroup Periph_Driver Peripheral Driver - * @{ - */ - -/** - * @addtogroup ADC - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_define ADC Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_typedef ADC Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group ADC_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup ADC_Private_fuctions ADC Private Fuctions - * @{ - */ -#ifdef DEBUG - /* no define */ -#endif - -/** - * @} - */ /* End of group ADC_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup ADC_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/*! - * @fn static uint32_t get_conversion_data(uint32_t reg) - * @brief Get convertion data from ADxREGn. - * @param[in] reg :ADxREGn data. - * @retval Convertion data. - * @note - - */ -/*--------------------------------------------------*/ -uint32_t get_conversion_data(uint32_t reg) -{ - uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4); - - return (result); -} -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_init(adc_ch_t *p_obj) - * @brief Initialize the ADC Channel object. - * @param[in][out] p_obj :ADC Channel object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_init(adc_ch_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((volatile void*)(p_obj->p_tset) == (volatile void*)0) || - ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxREGx ---*/ - /* Read is needed before the next convertion. */ - { - volatile uint32_t reg; - reg = *p_obj->p_reg; - } - /*--- ADxTSET ---*/ - *p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain); - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) - * @brief Release the ADC Channel object. - * @param[in][out] p_obj :ADC Channel object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxTSET ---*/ - *p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0); - /*--- ADxREGx ---*/ - /* Read is needed before the next convertion. */ - { - volatile uint32_t reg; - reg = *p_obj->p_reg; - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) - * @brief Enable Interrupt. - * @param[in][out] p_obj :ADC Channel object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((volatile void*)(p_obj->p_tset) == (volatile void*)0) || - ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxTSET ---*/ - { - uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); - - *p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) - * @brief Disable Interrupt. - * @param[in][out] p_obj :ADC Channel object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has stoped. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if (((void*)(p_obj) == (void*)0) || - ((volatile void*)(p_obj->p_tset) == (volatile void*)0) || - ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0)) - { - result = TXZ_ERROR; - } - else - { - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- ADxTSET ---*/ - { - uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); - - *p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) - * @brief Get conversion value. - * @param p_obj :ADC Channel object. - * @param p_value :AD value. Destination address. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @pre Conversion has done. - */ -/*--------------------------------------------------*/ -TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) -{ - TXZ_Result result = TXZ_ERROR; - uint32_t reg; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else - { - reg = *p_obj->p_reg; - /*------------------------------*/ - /* Check Result */ - /*------------------------------*/ - if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) - { - *p_value = get_conversion_data(reg); - result = TXZ_SUCCESS; - } - } - - return (result); -} -/** - * @} - */ /* End of group ADC_Exported_functions */ - -/** - * @} - */ /* End of group ADC */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__ADC_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/tmpm4g9_fc.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/tmpm4g9_fc.c deleted file mode 100644 index 564d8270577..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/tmpm4g9_fc.c +++ /dev/null @@ -1,646 +0,0 @@ -/** - ******************************************************************************* - * @file fc.c - * @brief Flash_Userboot Sample Application. - * @version V1.0.1.0 - * $Date:: 2017-06-23 13:52:12 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include -#include "tmpm4g9_fc.h" -//#include "txz_sample_def.h" - -/** - * @addtogroup Example - * @{ - */ - -/** - * @defgroup Flash_Userboot Flash_Userboot Sample Appli - * @{ - */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ -#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ -#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ -#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */ -#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ -#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ -#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ - -/****************** Changed by TSIP *************************************/ -///* Area Selection All */ -#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) -#define FC_AREASEL_AREA0 (uint32_t)(0x00000777UL) //select Area 0,1 and 2 -#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0888UL) //mask Area 0,1 and 2 -#define FC_AREASEL_WRITE_MODE (uint32_t)(0x1C000000UL) - -static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = { - (0x5E000000UL), /*!< CODE FLASH Page0 */ - (0x5E001000UL), /*!< CODE FLASH Page1 */ - (0x5E002000UL), /*!< CODE FLASH Page2 */ - (0x5E003000UL), /*!< CODE FLASH Page3 */ - (0x5E004000UL), /*!< CODE FLASH Page4 */ - (0x5E005000UL), /*!< CODE FLASH Page5 */ - (0x5E006000UL), /*!< CODE FLASH Page6 */ - (0x5E007000UL), /*!< CODE FLASH Page7 */ - (0x5E008000UL), /*!< CODE FLASH Page8 */ - (0x5E009000UL), /*!< CODE FLASH Page9 */ - (0x5E00A000UL), /*!< CODE FLASH Page10 */ - (0x5E00B000UL), /*!< CODE FLASH Page11 */ - (0x5E00C000UL), /*!< CODE FLASH Page12 */ - (0x5E00D000UL), /*!< CODE FLASH Page13 */ - (0x5E00E000UL), /*!< CODE FLASH Page14 */ - (0x5E00F000UL), /*!< CODE FLASH Page15 */ - (0x5E010000UL), /*!< CODE FLASH Page16 */ - (0x5E011000UL), /*!< CODE FLASH Page17 */ - (0x5E012000UL), /*!< CODE FLASH Page18 */ - (0x5E013000UL), /*!< CODE FLASH Page19 */ - (0x5E014000UL), /*!< CODE FLASH Page20 */ - (0x5E015000UL), /*!< CODE FLASH Page21 */ - (0x5E016000UL), /*!< CODE FLASH Page22 */ - (0x5E017000UL), /*!< CODE FLASH Page23 */ - (0x5E018000UL), /*!< CODE FLASH Page24 */ - (0x5E019000UL), /*!< CODE FLASH Page25 */ - (0x5E01A000UL), /*!< CODE FLASH Page26 */ - (0x5E01B000UL), /*!< CODE FLASH Page27 */ - (0x5E01C000UL), /*!< CODE FLASH Page28 */ - (0x5E01D000UL), /*!< CODE FLASH Page29 */ - (0x5E01E000UL), /*!< CODE FLASH Page30 */ - (0x5E01F000UL) /*!< CODE FLASH Page31 */ -}; - -/** - * @} - */ /* End of group Flash_Userboot_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define - * @{ - */ -/** - * @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef - * @{ - */ - -/** - * @} - */ /* End of group Flash_Userboot_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables - * @{ - */ -/** - * @} - */ /* End of group Flash_Userboot_Private_variables */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions - * @{ - */ -__STATIC_INLINE TXZ_Result fc_enable_areasel(void); -__STATIC_INLINE TXZ_Result fc_disable_areasel(void); -static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size); -static TXZ_Result fc_verify_check(uint32_t* src_address, uint32_t* dst_address, uint32_t size); -static TXZ_Result fc_erase_command(uint32_t* flash_top_address, uint32_t* erase_top_address, fc_erase_kind_t kind); -static TXZ_Result fc_blank_check(uint32_t* address, uint32_t size); - -/*--------------------------------------------------*/ -/** - * @brief Enables the AREA0. - * @param - - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function write the FCAREASEL regiset. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -__STATIC_INLINE TXZ_Result fc_enable_areasel(void) -{ - TXZ_Result retval = TXZ_ERROR; - /* Writes the FCKER register the KEYCODE. */ - TSB_FC->KCR = FC_KCR_KEYCODE; - - /* Selects the area0 */ - { - uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; - TSB_FC->AREASEL = reg | FC_AREASEL_AREA0; - } - - /* Confirms the FCAREASEL register the SSF0 was set. */ - while(1){ - uint32_t i = TSB_FC->AREASEL; - if((i & FC_AREASEL_WRITE_MODE) == FC_AREASEL_WRITE_MODE){ - retval = TXZ_SUCCESS; - break; - } - } - - return(retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Disables the AREA0. - * @param - - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function write the FCAREASEL regiset. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -__STATIC_INLINE TXZ_Result fc_disable_areasel(void) -{ - TXZ_Result retval = TXZ_ERROR; - - /* Writes the FCKER register the KEYCODE. */ - TSB_FC->KCR = FC_KCR_KEYCODE; - - /* Selects the area0 */ - { - uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; - TSB_FC->AREASEL = reg | FC_AREASEL_EXPECT_AREA0; - } - - /* Confirms the SSF0 of the FCAREASEL register is not set. */ - while(1){ - uint32_t i = TSB_FC->AREASEL; - if((i & FC_AREASEL_WRITE_MODE) != FC_AREASEL_WRITE_MODE){ - retval = TXZ_SUCCESS; - break; - } - } - - return(retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Writes data of the Flash ROM. - * @param uint32_t* : src_address - * @param uint32_t* : dst_address - * @param uint32_t : size - * @return - - * @note It works in the inner RAM. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size) -{ - TXZ_Result retval; - /******** Changed/Added by TSIP next 12 lines *************/ - volatile uint32_t* addr1; - volatile uint32_t* addr2; - if(dst_address <= (uint32_t *)0x0007FFFFUL) { - addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); - addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); - } else if(dst_address <= (uint32_t *)0x000FFFFF) { - addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR + 0x10000); - addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR + 0x10000); - } else { - addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR + 0x100000); - addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR + 0x100000); - } - volatile uint32_t* addr3 = (uint32_t *) ((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP); - uint32_t* source = (uint32_t *) src_address; - - /* Enables the AREA0. Write Mode. */ - retval = fc_enable_areasel(); - - if(retval == TXZ_SUCCESS){ - uint32_t i; - - *addr1 = (0x000000AAUL); /* bus cycle 1 */ - *addr2 = (0x00000055UL); /* bus cycle 2 */ - *addr1 = (0x000000A0UL); /* bus cycle 3 */ - for(i=(0UL); iSR0 & (uint32_t)status; - - /* Confirms the specific status of the flash ROM */ - if(work32 == (uint32_t)status){ - retval = TXZ_DONE; - } - - return (retval); -} - -/*--------------------------------------------------*/ -/** - * @brief Auto write command of the code flash ROM. - * @param uint32_t* : src_address - * @param uint32_t* : dst_address - * @param uint32_t : size - * @return Result. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note It works in the inner RAM. - * This function writes 16bytes data to the code Flash ROM. - */ -/*--------------------------------------------------*/ -#if defined ( __GNUC__ ) /* GCC Compiler */ -__attribute__((section(".ram_func"))) -#endif -#if defined ( __ICCARM__ ) // IAR Compiler -__ramfunc -#endif -TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size) -{ - TXZ_Result retval = TXZ_SUCCESS; - - /* Checks the code Flash ROM status */ - if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){ - - uint32_t i; - /* Checks the code Flash ROM status */ - for(i=0;ip_instance)); -#endif /* #ifdef DEBUG */ - - /* System core clock update */ - SystemCoreClockUpdate(); - - switch (p_obj->p_instance->SYSCR & CG_MCKSELGST_MASK) - { - case CG_MCKSELGST_1: /* fsysm -> fc/PRCK */ - result = SystemCoreClock / CG_FSYSM_1_DIV; - break; - case CG_MCKSELGST_2: /* fsysm -> fc/PRCK/2 */ - result = SystemCoreClock / CG_FSYSM_2_DIV; - break; - case CG_MCKSELGST_4: /* fsysm -> fc/PRCK/4 */ - result = SystemCoreClock / CG_FSYSM_4_DIV; - break; - default: - result = 0U; - break; - } - return (result); - -} - -/*--------------------------------------------------*/ -/** - * @brief Update PrescalerClock according register values. - * @param p_obj :CG object. - * @retval PrescalerClock Frequency. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -uint32_t cg_get_phyt0(cg_t *p_obj) -{ - uint32_t result = 0U; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the CG_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /* System core clock update */ - SystemCoreClockUpdate(); - - /* Get Gear status. */ - switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) - { - case CG_FSYS_1: /* Gear -> fc */ - result = SystemCoreClock * CG_FSYS_1_MUL; - break; - case CG_FSYS_2: /* Gear -> fc/2 */ - result = SystemCoreClock * CG_FSYS_2_MUL; - break; - case CG_FSYS_4: /* Gear -> fc/4 */ - result = SystemCoreClock * CG_FSYS_4_MUL; - break; - case CG_FSYS_8: /* Gear -> fc/8 */ - result = SystemCoreClock * CG_FSYS_8_MUL; - break; - case CG_FSYS_16: /* Gear -> fc/16 */ - result = SystemCoreClock * CG_FSYS_16_MUL; - break; - default: - result = 0U; - break; - } - - switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) - { - case CG_PRCKST_1: /* ��T0 -> fc */ - result /= CG_PRCK_1_DIV; - break; - case CG_PRCKST_2: /* ��T0 -> fc/2 */ - result /= CG_PRCK_2_DIV; - break; - case CG_PRCKST_4: /* ��T0 -> fc/4 */ - result /= CG_PRCK_4_DIV; - break; - case CG_PRCKST_8: /* ��T0 -> fc/8 */ - result /= CG_PRCK_8_DIV; - break; - case CG_PRCKST_16: /* ��T0 -> fc/16 */ - result /= CG_PRCK_16_DIV; - break; - case CG_PRCKST_32: /* ��T0 -> fc/32 */ - result /= CG_PRCK_32_DIV; - break; - case CG_PRCKST_64: /* ��T0 -> fc/64 */ - result /= CG_PRCK_64_DIV; - break; - case CG_PRCKST_128: /* ��T0 -> fc/128 */ - result /= CG_PRCK_128_DIV; - break; - case CG_PRCKST_256: /* ��T0 -> fc/256 */ - result /= CG_PRCK_256_DIV; - break; - case CG_PRCKST_512: /* ��T0 -> fc/512 */ - result /= CG_PRCK_512_DIV; - break; - default: - result = 0U; - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Update Middle PrescalerClock according register values. - * @param p_obj :CG object. - * @retval Middle PrescalerClock Frequency. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -uint32_t cg_get_mphyt0(cg_t *p_obj) -{ - uint32_t result = 0U; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the CG_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /* System core clock update */ - SystemCoreClockUpdate(); - - /* Get Gear status. */ - switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) - { - case CG_FSYS_1: /* Gear -> fc */ - result = SystemCoreClock * CG_FSYS_1_MUL; - break; - case CG_FSYS_2: /* Gear -> fc/2 */ - result = SystemCoreClock * CG_FSYS_2_MUL; - break; - case CG_FSYS_4: /* Gear -> fc/4 */ - result = SystemCoreClock * CG_FSYS_4_MUL; - break; - case CG_FSYS_8: /* Gear -> fc/8 */ - result = SystemCoreClock * CG_FSYS_8_MUL; - break; - case CG_FSYS_16: /* Gear -> fc/16 */ - result = SystemCoreClock * CG_FSYS_16_MUL; - break; - default: - result = 0U; - break; - } - switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) - { - case CG_PRCKST_1: /* ��T0 -> fc */ - result /= CG_PRCK_1_DIV; - break; - case CG_PRCKST_2: /* ��T0 -> fc/2 */ - result /= CG_PRCK_2_DIV; - break; - case CG_PRCKST_4: /* ��T0 -> fc/4 */ - result /= CG_PRCK_4_DIV; - break; - case CG_PRCKST_8: /* ��T0 -> fc/8 */ - result /= CG_PRCK_8_DIV; - break; - case CG_PRCKST_16: /* ��T0 -> fc/16 */ - result /= CG_PRCK_16_DIV; - break; - case CG_PRCKST_32: /* ��T0 -> fc/32 */ - result /= CG_PRCK_32_DIV; - break; - case CG_PRCKST_64: /* ��T0 -> fc/64 */ - result /= CG_PRCK_64_DIV; - break; - case CG_PRCKST_128: /* ��T0 -> fc/128 */ - result /= CG_PRCK_128_DIV; - break; - case CG_PRCKST_256: /* ��T0 -> fc/256 */ - result /= CG_PRCK_256_DIV; - break; - case CG_PRCKST_512: /* ��T0 -> fc/512 */ - result /= CG_PRCK_512_DIV; - break; - default: - result = 0U; - break; - } - - switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) - { - case CG_MCKSELPST_1: /* ��T0 -> fc/PRCK */ - result /= CG_FSYSM_1_DIV; - break; - case CG_MCKSELPST_2: /* ��T0 -> fc/PRCK/2 */ - result /= CG_FSYSM_2_DIV; - break; - case CG_MCKSELPST_4: /* ��T0 -> fc/PRCK/4 */ - result /= CG_FSYSM_4_DIV; - break; - default: - result = 0U; - break; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Set Internal high-speed oscillator enable. - * @param p_obj :CG object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result cg_ihosc_enable(cg_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the CG_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /* Internal high-speed oscillator is enable. */ - (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR,CG_IHOSC1EN))) = CG_IHOSC_ENABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Set Internal high-speed oscillator disable. - * @param p_obj :CG object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result cg_ihosc_disable(cg_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the CG_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /* Internal high-speed oscillator is disable. */ - (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR,CG_IHOSC1EN))) = CG_IHOSC_DISABLE; - - return (result); -} -/** - * @} - */ /* End of group CG_Exported_functions */ - -/** - * @} - */ /* End of group CG */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__CG_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart.c deleted file mode 100644 index 157ceaab0cb..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart.c +++ /dev/null @@ -1,1438 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart.c - * @brief This file provides API functions for FUART driver. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_fuart_include.h" -#include "txz_fuart.h" - -#if defined(__FUART_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup FUART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_define FUART Private Define - * @{ - */ - -/** - * @defgroup FUART_BourateConfig Bourate Setting Configuration - * @brief Bourate Setting Configuration. - * @{ - */ -#define FUART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ -#define FUART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ -#define FUART_CFG_GET_BOUDRATE FUART_CFG_GET_BOUDRATE_ENABLE /*!< Disable/Enable Get Bourate Setting */ - -#define FUART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ -#define FUART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ -#define FUART_CFG_GET_BOUDRATE_TYPE FUART_CFG_GET_BOUDRATE_TYPE_ALL /*!< Get Bourate Type Setting */ - -#define FUART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)1) /*!< Error Margin(%). */ -#define FUART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ -/** - * @} - */ /* End of group FUART_BourateConfig */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_define FUART Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_define FUART Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_typedef FUART Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup FUART_Private_fuctions FUART Private Fuctions - * @{ - */ -#ifdef DEBUG - __STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); - __STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); - __STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); - __STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); - __STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); - __STATIC_INLINE int32_t check_param_data_length(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_int(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_int(uint32_t param); - __STATIC_INLINE int32_t check_param_err_int(uint32_t param); - __STATIC_INLINE int32_t check_param_rangeK(uint32_t param); - __STATIC_INLINE int32_t check_param_rangeN(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); -#endif /* #ifdef DEBUG */ -#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) - static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); -#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the CTS Handshake's parameter. - * @param param :CTS Handshake's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_CTSHandshake"UART_CTS_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_CTS_DISABLE: - case FUART_CTS_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the RTS Handshake's parameter. - * @param param :RTS Handshake's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RTSHandshake"UART_RTS_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_RTS_DISABLE: - case FUART_RTS_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Stop Bit's parameter. - * @param param :Stop Bit's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_StopBit"UART_STOP_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_STOP_BIT_1: - case FUART_STOP_BIT_2: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Bit's parameter. - * @param param :Parity Bit's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_ParityBit"UART_PARITY_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_PARITY_BIT_ODD: - case FUART_PARITY_BIT_EVEN: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Enable's parameter. - * @param param :Parity Enable's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_ParityEnable"UART_PARITY_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_PARITY_DISABLE: - case FUART_PARITY_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Length's parameter. - * @param param :Data Length's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_DataLength"UART_DATA_LENGTH_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_data_length(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_DATA_LENGTH_5: - case FUART_DATA_LENGTH_6: - case FUART_DATA_LENGTH_7: - case FUART_DATA_LENGTH_8: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Fill Level Range's parameter. - * @param param :Tx Fill Level Range's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_FIFO_LEVEL_4: - case FUART_FIFO_LEVEL_8: - case FUART_FIFO_LEVEL_16: - case FUART_FIFO_LEVEL_24: - case FUART_FIFO_LEVEL_28: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Fill Level's parameter. - * @param param :Rx Fill Level's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_FIFO_LEVEL_4: - case FUART_FIFO_LEVEL_8: - case FUART_FIFO_LEVEL_16: - case FUART_FIFO_LEVEL_24: - case FUART_FIFO_LEVEL_28: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Interrpt's parameter. - * @param param :Tx Interrpt's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_TX_INT_DISABLE: - case FUART_TX_INT_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Interrpt's parameter. - * @param param :Rx Interrpt's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RxInterrupt"UART_RX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - switch (param) - { - case FUART_RX_INT_DISABLE: - case FUART_RX_INT_ENABLE: - result = FUART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Error Interrpt's parameter. - * @param param :Error Interrpt's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_err_int(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - param &= ~(FUART_OV_ERR_INT_ENABLE | FUART_BK_ERR_INT_ENABLE | FUART_PA_ERR_INT_ENABLE | FUART_FR_ERR_INT_ENABLE | FUART_TO_ERR_INT_ENABLE); - - if(param == 0){ - result = FUART_PARAM_OK; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Range K's parameter. - * @param param :Range K's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RangeK"UART_RANGE_K_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - /*--- Now, FUART_RANGE_K_MIN is 0. ---*/ -#if 0 - if ((FUART_RANGE_K_MIN <= param) && (param <= FUART_RANGE_K_MAX)) -#else - if (param <= FUART_RANGE_K_MAX) -#endif - { - result = FUART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Range N's parameter. - * @param param :Range N's parameter - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note Macro definition is @ref FUART_RangeN"UART_RANGE_N_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - if ((FUART_RANGE_N_MIN <= param) && (param <= FUART_RANGE_N_MAX)) - { - result = FUART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the num of buff for transmit. - * @param param :Num of buff. - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - if (param != 0) - { - result = FUART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the num of buff for receive. - * @param param :Num of buff. - * @retval FUART_PARAM_OK :Valid - * @retval FUART_PARAM_NG :Invalid - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) -{ - int32_t result = FUART_PARAM_NG; - - if (param != 0) - { - result = FUART_PARAM_OK; - } - - return (result); -} -#endif /* #ifdef DEBUG */ - -#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) -/*--------------------------------------------------*/ -/** - * @brief Check the within error margin. - * @param boudrate :Boudrate(bps). - * @param clock :Clock(hz). - * @param boudrate :Boudrate(bps). - * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" - * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" - * @param p_range64 :Error range(after fixed point bit shift). - * @retval TXZ_SUCCESS :Within error margin. - * @retval TXZ_ERROR :Without error margin. - * @note For N+(64-K)/64 division. - */ -/*--------------------------------------------------*/ -static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) -{ - TXZ_Result result = TXZ_ERROR; - uint64_t boud64 = 0; - uint64_t tx64 = 0; - uint64_t work64 = 0; - - /* phi T0 */ - tx64 = (uint64_t)((uint64_t)clock << (FUART_CFG_BOUDRATE_FIXED_POINT_BIT+2)); - - /* Bourate */ - boud64 = (uint64_t)((uint64_t)boudrate << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); - *p_range64 = ((boud64/100)*FUART_CFG_BOUDRATE_ERROR_RANGE); - /* BourateX */ - work64 = (uint64_t)((uint64_t)n << 6); - work64 = (uint64_t)(work64 + (uint64_t)k); - work64 = (tx64 / work64); - if (boud64 >= *p_range64) - { - if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) - { - if( boud64 < work64 ) - { - *p_range64 = (work64 - boud64); - } - else - { - *p_range64 = (boud64 - work64); - } - result = TXZ_SUCCESS; - } - } - - return (result); -} -#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ - -/** - * @} - */ /* End of group FUART_Private_functions */ - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Initialize the FUART object. - * @param p_obj :FUART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_init(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); - assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); - assert_param(check_param_tx_int(p_obj->init.tx_int.inttx)); - assert_param(check_param_rx_int(p_obj->init.rx_int.intrx)); - assert_param(check_param_err_int(p_obj->init.interr)); - assert_param(check_param_tx_fill_level_range(p_obj->init.tx_int.level)); - assert_param(check_param_rx_fill_level_range(p_obj->init.rx_int.level)); - assert_param(check_param_cts_handshake(p_obj->init.ctse)); - assert_param(check_param_rts_handshake(p_obj->init.rtse)); - assert_param(check_param_stop_bit(p_obj->init.sblen)); - assert_param(check_param_parity_bit(p_obj->init.even)); - assert_param(check_param_parity_enable(p_obj->init.pe)); - assert_param(check_param_data_length(p_obj->init.sm)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable FUART */ - /*------------------------------*/ - p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | - FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); - /*------------------------------*/ - /* Interrupt Disable */ - /*------------------------------*/ - p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | - FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | - FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); - /*------------------------------*/ - /* Interrupt Clear */ - /*------------------------------*/ - p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | - FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | - FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); - - /*------------------------------*/ - /* FIFO Disable */ - /*------------------------------*/ - p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - p_obj->p_instance->BRD = p_obj->init.boudrate.brn; - p_obj->p_instance->FBRD = p_obj->init.boudrate.brk; - p_obj->p_instance->LCR_H = (p_obj->init.stpa | p_obj->init.sm | - p_obj->init.fifo | p_obj->init.sblen | - p_obj->init.even | p_obj->init.pe); - p_obj->p_instance->IFLS = ((p_obj->init.rx_int.level << 3) | p_obj->init.tx_int.level); - p_obj->p_instance->IMSC = (p_obj->init.interr | p_obj->init.tx_int.inttx | p_obj->init.rx_int.intrx); - p_obj->p_instance->CR = (p_obj->init.ctse | p_obj->init.rtse | FUARTxCR_UARTEN_ENABLE); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the FUART object. - * @param p_obj :FUART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_deinit(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable FUART */ - /*------------------------------*/ - p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | - FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); - /*------------------------------*/ - /* Interrupt Disable */ - /*------------------------------*/ - p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | - FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | - FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); - /*------------------------------*/ - /* Interrupt Clear */ - /*------------------------------*/ - p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | - FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | - FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); - /*------------------------------*/ - /* FIFO Disable */ - /*------------------------------*/ - p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard transmit. - * @param p_obj :FUART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears transmit's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_discard_transmit(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - disable_FUARTxCR_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Interrupt Clear */ - /*------------------------------*/ - p_obj->p_instance->ICR = FUARTxICR_TXIC_CLR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard receive. - * @param p_obj :FUART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears receive's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_discard_receive(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - disable_FUARTxCR_RXE(p_obj->p_instance); - /*------------------------------*/ - /* Interrupt Clear */ - /*------------------------------*/ - p_obj->p_instance->ICR = FUARTxICR_RXIC_CLR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data. Non-Blocking Communication. - * @param p_obj :FUART object. - * @param p_info :The information of transmit data. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); - assert_param(check_param_tx_buff_num(p_info->num)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - disable_FUARTxCR_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - p_obj->transmit.info.p_data = p_info->p_data; - p_obj->transmit.info.num = p_info->num; - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - volatile uint32_t fr_reg; - - fr_reg = p_obj->p_instance->FR; - while((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /*--- FUARTxDR ---*/ - if (p_obj->transmit.info.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else{ - break; - } - fr_reg = p_obj->p_instance->FR; - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to TXE(=1). */ - /* Bitband Access. */ - enable_FUARTxCR_TXE(p_obj->p_instance); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Non-Blocking Communication. - * @param p_obj :FUART object. - * @param p_info :The information of receive buffer. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref FUART_FifoMax) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - volatile uint8_t dummy; - volatile uint32_t fr_reg; - uint32_t rx_count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); - assert_param(check_param_rx_buff_num(p_info->num)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /* Write to RXE(=0). */ - /* Bitband Access. */ - disable_FUARTxCR_RXE(p_obj->p_instance); - /* FIFO CLR */ - fr_reg = p_obj->p_instance->FR; - while((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) - { - dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); - if(p_obj->init.fifo == 1) - { - if(++rx_count > FUART_RX_FIFO_MAX) - { - break; - } - } - else{ - if(++rx_count > 1) - { - break; - } - } - fr_reg = p_obj->p_instance->FR; - } - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->receive.wp = 0; - p_obj->receive.info.p_data = p_info->p_data; - p_obj->receive.info.num = p_info->num; - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to RXE(=1). */ - /* Bitband Access. */ - enable_FUARTxCR_RXE(p_obj->p_instance); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for transmit. - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_transmit_irq_handler(fuart_t *p_obj) -{ - uint32_t cr_reg; - volatile uint32_t fr_reg; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current FUARTxCR */ - cr_reg = p_obj->p_instance->CR; - /*------------------------------*/ - /* Transmit Status Check */ - /*------------------------------*/ - if ((cr_reg & FUARTxCR_TXE_MASK) == FUARTxCR_TXE_ENABLE) - { - if (p_obj->transmit.info.num <= p_obj->transmit.rp) - { - /*=== Transmit Done!! ===*/ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - /* disable_FUARTxCR_TXE(p_obj->p_instance); */ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != FUART_NULL) - { - /* Call the transmit handler with TXZ_SUCCESS. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); - } - } - else - { - fr_reg = p_obj->p_instance->FR; - while((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /*--- FUARTxDR ---*/ - if (p_obj->transmit.info.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else{ - break; - } - fr_reg = p_obj->p_instance->FR; - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for receive. - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_receive_irq_handler(fuart_t *p_obj) -{ - uint32_t cr_reg; - volatile uint32_t fr_reg; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current FUARTxCR */ - cr_reg = p_obj->p_instance->CR; - /*------------------------------*/ - /* Receive Status Check */ - /*------------------------------*/ - if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) - { - uint32_t rx_count = 0; - - fr_reg = p_obj->p_instance->FR; - while((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) - { - *(p_obj->receive.info.p_data + p_obj->receive.wp) = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); - p_obj->receive.wp += 1; - if(p_obj->receive.wp >= p_obj->receive.info.num) - { - break; - } - if(p_obj->init.fifo == 1) - { - if(++rx_count >= FUART_RX_FIFO_MAX) - { - break; - } - } - else{ - break; - } - fr_reg = p_obj->p_instance->FR; - } - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if(p_obj->receive.wp >= p_obj->receive.info.num) - { - if(p_obj->receive.handler != FUART_NULL) - { - fuart_receive_t param; - param.p_data = p_obj->receive.info.p_data; - param.num = p_obj->receive.wp; - p_obj->receive.wp = 0; - /* Call the receive handler with TXZ_SUCCESS. */ - p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for error. - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_error_irq_handler(fuart_t *p_obj) -{ - uint32_t cr_reg; - uint32_t error; - uint32_t ecr_reg = 0x00; - uint32_t icr_reg = 0x00; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current FUARTxCR */ - cr_reg = p_obj->p_instance->CR; - /*------------------------------*/ - /* Error Registar Control */ - /*------------------------------*/ - /* Read current FUARTxRSR. */ - error = p_obj->p_instance->RSR; - /* Now, no clear the error flag. */ - /*------------------------------*/ - /* Error Check */ - /*------------------------------*/ - /*--- FUARTxRSR ---*/ - /* Check the receive error. */ - { - TXZ_Result err = TXZ_SUCCESS; - /* OVER RUN */ - if ((error & FUARTxRSR_OE_MASK) == FUARTxRSR_OE_ERR) - { - volatile uint8_t dummy; - - icr_reg |= FUARTxICR_OEIC_CLR; - ecr_reg |= FUARTxECR_OE_CLR; - dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); - err = TXZ_ERROR; - } - /* BREAK */ - if ((error & FUARTxRSR_BE_MASK) == FUARTxRSR_BE_ERR) - { - icr_reg |= FUARTxICR_BEIC_CLR; - ecr_reg |= FUARTxECR_BE_CLR; - err = TXZ_ERROR; - } - /* PARITY */ - if ((error & FUARTxRSR_PE_MASK) == FUARTxRSR_PE_ERR) - { - icr_reg |= FUARTxICR_PEIC_CLR; - ecr_reg |= FUARTxECR_PE_CLR; - err = TXZ_ERROR; - } - /* FRAMING */ - if ((error & FUARTxRSR_FE_MASK) == FUARTxRSR_FE_ERR) - { - icr_reg |= FUARTxICR_FEIC_CLR; - ecr_reg |= FUARTxECR_FE_CLR; - err = TXZ_ERROR; - } - if (err == TXZ_ERROR) - { - p_obj->p_instance->ICR = icr_reg; - p_obj->p_instance->ECR = ecr_reg; - /*------------------------------*/ - /* Receive Check */ - /*------------------------------*/ - if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) - { - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- FUARTxCR ---*/ - /* Write to RXE(=0). */ - /* Bitband Access. */ - disable_FUARTxCR_RXE(p_obj->p_instance); - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != FUART_NULL) - { - /* Call the receive handler with TXZ_ERROR. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); - } - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for timeout error. - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_timeout_error_irq_handler(fuart_t *p_obj) -{ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != FUART_NULL) - { - /* Call the receive handler with TXZ_ERROR. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler . - * @param p_obj :FUART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void fuart_irq_handler(fuart_t *p_obj) -{ - uint32_t interrupt_status = p_obj->p_instance->MIS; - if((interrupt_status & FUARTxMIS_RXMIS_MASK) == FUARTxMIS_RXMIS_REQ) - { - p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RXMIS_MASK; - fuart_receive_irq_handler(p_obj); - } - if((interrupt_status & FUARTxMIS_TXMIS_MASK) == FUARTxMIS_TXMIS_REQ) - { - p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_TXMIS_MASK; - fuart_transmit_irq_handler(p_obj); - } - if((interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK)) != 0) - { - p_obj->p_instance->ICR = interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK); - fuart_error_irq_handler(p_obj); - } - if((interrupt_status & FUARTxMIS_RTMIS_MASK) != 0) - { - p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RTMIS_MASK; - fuart_timeout_error_irq_handler(p_obj); - } -} - - -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | 31-8 | - | - | - * | 7 | TXFE | Transmit FIFO Empty Flag. | - * | 6 | RXFF | Reach Receive Fill Level Flag. | - * | 5 | TXFF | Reach Transmit Fill Level Flag. | | - * | 4 | RXFE | Receive FIFO Empty Flag. | - * | 3 | BUSY | Transmit BUSY Flag. | - * | 2-1 | - | - | - * | 0 | CTS | FUTxCTS Flag. | - * - * @param p_obj :FUART object. - * @param p_status :Save area for status. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_status)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Read */ - /*------------------------------*/ - /*--- FUARTxFR ---*/ - /* Read current FUARTxFR. */ - *p_status = p_obj->p_instance->FR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get error information. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-4 | - | - | - * | 3 | OVRERR | Overrun Error. Use @ref FUART_OverrunErr. | - * | 2 | PERR | Parity Error. Use @ref FUART_ParityErr. | - * | 1 | FERR | Framing Error. Use @ref FUART_FramingErr. | - * | 0 | BERR | Break Error Flag. Use @ref FUART_BreakErr. | - * - * @param p_obj :FUART object. - * @param p_error :Save area for error. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_error)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Error Read */ - /*------------------------------*/ - /*--- FUARTxRSR ---*/ - /* Read current FUARTxRSR. */ - *p_error = p_obj->p_instance->RSR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get the setting of boudrate. - * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". - * @param boudrate :Boudrate(bps). - * @param p_brd :Save area for Division Setting. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Not support setting. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_brd) -{ - TXZ_Result result = TXZ_ERROR; -#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) - uint64_t tx = 0; - uint64_t work = 0; - uint64_t range64 = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_brd)); - /* Check the parameter of FUARTxCLK. */ -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Calculate Division Setting */ - /*------------------------------*/ - if ((clock > 0) && (boudrate > 0)) - { - /*--- phi T0 ---*/ - tx = (uint64_t)((uint64_t)clock << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); - - /*--- N+(K/64) division ---*/ - { - uint8_t k = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - - work = ((uint64_t)boudrate); - tx /= work; - tx >>= 4; - for (k = FUART_RANGE_K_MIN; (k <= FUART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) - { - work = tx - (uint64_t)k; - work >>= FUART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ - if ((FUART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= FUART_RANGE_N_MAX)) - { - uint64_t workRange = 0; - /* Verification */ - if (verification_boudrate64(clock, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) - { -#if (FUART_CFG_GET_BOUDRATE_TYPE == FUART_CFG_GET_BOUDRATE_TYPE_ALL) - /* Compare the previous range. */ - if (result == TXZ_SUCCESS) - { - if (range64 > workRange) - { - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - range64 = workRange; - } - } - else - { - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - range64 = workRange; - } - result = TXZ_SUCCESS; -#else - /* Finish!! */ - if (result == TXZ_SUCCESS) - { - if (range64 > workRange) - { - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - } - } - else - { - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - } - result = TXZ_SUCCESS; - loopBreak = TXZ_DONE; -#endif - } - } - } - } - } -#endif /* (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ - - return (result); -} - -/** - * @} - */ /* End of group FUART_Exported_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__UART_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart_ex.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart_ex.c deleted file mode 100644 index 131037c5f73..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_fuart_ex.c +++ /dev/null @@ -1,206 +0,0 @@ -/** - ******************************************************************************* - * @file txz_fuart_ex.c - * @brief This file provides API functions for FUART driver. - * @brief Extended functionality. - * @version V1.0.0.0 - * $Date:: 2017-08-06 10:43:01 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_fuart_include.h" -#include "txz_fuart_ex.h" - -#if defined(__FUART_EX_H) - -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup UART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group FUART_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Private_fuctions - * @{ - */ - -/** - * @} - */ /* End of group FUART_Private_functions */ - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup FUART_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Send Break. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_send_break(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Set Break */ - /*------------------------------*/ - { - uint32_t trans = p_obj->p_instance->LCR_H; - - trans &= ~FUARTxLCR_H_BRK_MASK; - trans |= FUARTxLCR_H_BRK_SEND; - p_obj->p_instance->LCR_H = trans; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Stop Break. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result fuart_stop_break(fuart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the FUART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Set Break */ - /*------------------------------*/ - { - uint32_t trans = p_obj->p_instance->LCR_H; - - trans &= ~FUARTxLCR_H_BRK_MASK; - trans |= FUARTxLCR_H_BRK_STOP; - p_obj->p_instance->LCR_H = trans; - } - - return (result); -} - - -/** - * @} - */ /* End of group FUART_Exported_functions */ - -/** - * @} - */ /* End of group FUART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__UART_EX_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_gpio.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_gpio.c deleted file mode 100644 index f7f84fd125e..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_gpio.c +++ /dev/null @@ -1,4751 +0,0 @@ -/** - ******************************************************************************* - * @file txz_gpio.c - * @brief This file provides API functions for GPIO driver. - * @version V1.0.0.2 - * $Date:: 2018-04-11 14:13:48 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_gpio.h" - -#if defined(__GPIO_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup GPIO - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Private_define GPIO Private Define - * @{ - */ -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ - -/** - * @name Bit Operation Macro - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PORT_BASE (0x400E0000UL) /*!< Port Register Base Adress */ -#define BITBAND_PORT_OFFSET (0x0000100UL) /*!< Port Register Offset Value */ -#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (uint32_t)(gr)) ) /*!< Operational target Port Adress */ -#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /*!< Operational target Control Register Adress */ -#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)(base)) |= (uint32_t)(0x0000001UL<< (bitnum))) /*!< Target Pin Bit set */ -#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)(base)) &= ~((uint32_t)(0x0000001UL<< (bitnum)))) /*!< Target Pin Bit clear */ -#define BITBAND_PORT_READ(val, base, bitnum) ((val) = ((*((__IO uint32_t *)(base)) & (uint32_t)(0x0000001UL<< (bitnum))) >> (bitnum))) /*!< Target Pin Bit read */ -/** - * @} - */ /* End of Bit Operation Macro */ -/** - * @} - */ /* End of group GPIO_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Private_define GPIO Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group GPIO_Private_define */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Private_typedef GPIO Private Typedef - * @{ - */ -/*! - * @brief Pin Exist Table - * @details Bit0 :GPIO_Mode_DATA - * @details Bit1 :GPIO_Mode_CR - * @details Bit2 :GPIO_Mode_FR1 - * @details Bit3 :GPIO_Mode_FR2 - * @details Bit4 :GPIO_Mode_FR3 - * @details Bit5 :GPIO_Mode_FR4 - * @details Bit6 :GPIO_Mode_FR5 - * @details Bit7 :GPIO_Mode_FR6 - * @details Bit8 :GPIO_Mode_FR7 - * @details Bit9 :GPIO_Mode_OD - * @details Bit10 :GPIO_Mode_PUP - * @details Bit11 :GPIO_Mode_PDN - * @details Bit12 :GPIO_Mode_IE - */ -#if defined(TMPM4G6) -static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = -{ - /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ - { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */ - { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_C */ - { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */ - { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */ - { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x0000, 0x0000, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */ - { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */ - { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */ - { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */ - { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_M */ - { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */ - { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_R */ - { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_T */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_V */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */ - { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */ -}; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) -static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = -{ - /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ - { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */ - { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */ - { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_C */ - { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */ - { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */ - { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */ - { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */ - { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */ - { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */ - { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_M */ - { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */ - { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */ - { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_R */ - { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */ - { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */ - { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */ -}; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) -static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = -{ - /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ - { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */ - { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */ - { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E07, 0x1E07 }, /** GPIO_PORT_C */ - { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */ - { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */ - { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */ - { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */ - { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */ - { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */ - { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */ - { 0x1FE3, 0x1FE3, 0x1FDB, 0x1FEB, 0x1FAB, 0x1F9B, 0x1FFB, 0x1FEB }, /** GPIO_PORT_M */ - { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */ - { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */ - { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B }, /** GPIO_PORT_R */ - { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */ - { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */ - { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */ - { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */ -}; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) -static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = -{ - /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ - { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */ - { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */ - { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E07, 0x1E07 }, /** GPIO_PORT_C */ - { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */ - { 0x1F7F, 0x1E47, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */ - { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */ - { 0x1E57, 0x1E57, 0x1F03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */ - { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */ - { 0x1E53, 0x1E53, 0x1F53, 0x1F53, 0x1E5B, 0x1E5B, 0x1F43, 0x1F43 }, /** GPIO_PORT_J */ - { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */ - { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x1E1B, 0x1E0B, 0x1E1B, 0x1E0F }, /** GPIO_PORT_L */ - { 0x1FE3, 0x1FE3, 0x1FDB, 0x1FEB, 0x1FAB, 0x1F9B, 0x1FFB, 0x1FEB }, /** GPIO_PORT_M */ - { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */ - { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */ - { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B }, /** GPIO_PORT_R */ - { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */ - { 0x1F1B, 0x1F0B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F0B }, /** GPIO_PORT_U */ - { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */ - { 0x1EE3, 0x1F63, 0x1F63, 0x1E63, 0x1FD3, 0x1FC3, 0x1FC3, 0x1FD3 }, /** GPIO_PORT_W */ - { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */ -}; -#endif /* TMPM4G9 */ - -/** - * @} - */ /* End of group GPIO_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup GPIO_Private_fuctions GPIO Private Fuctions - * @{ - */ - -static uint8_t change_mode_to_num( uint32_t mode ); -static uint8_t change_func_to_num( uint32_t mode ); -static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); -static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); -/*--------------------------------------------------*/ -/*! - * @fn static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) - * @brief Check the Pin Exist. - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t - * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - */ -/*--------------------------------------------------*/ - -static uint8_t change_mode_to_num( uint32_t mode ) -{ - uint8_t retVal = 0; - - if (mode == GPIO_Mode_DATA) {retVal = 0;} - else if (mode == GPIO_Mode_CR) {retVal = 1;} - else if (mode == GPIO_Mode_FR1) {retVal = 2;} - else if (mode == GPIO_Mode_FR2) {retVal = 3;} - else if (mode == GPIO_Mode_FR3) {retVal = 4;} - else if (mode == GPIO_Mode_FR4) {retVal = 5;} - else if (mode == GPIO_Mode_FR5) {retVal = 6;} - else if (mode == GPIO_Mode_FR6) {retVal = 7;} - else if (mode == GPIO_Mode_FR7) {retVal = 8;} - else if (mode == GPIO_Mode_OD) {retVal = 9;} - else if (mode == GPIO_Mode_PUP) {retVal = 10;} - else if (mode == GPIO_Mode_PDN) {retVal = 11;} - else if (mode == GPIO_Mode_IE) {retVal = 12;} - else {retVal = 13;} - - return retVal; -} - -static uint8_t change_func_to_num( uint32_t mode ) -{ - uint8_t retVal = 0; - - if (mode == GPIO_FR_1) {retVal = 2;} - else if (mode == GPIO_FR_2) {retVal = 3;} - else if (mode == GPIO_FR_3) {retVal = 4;} - else if (mode == GPIO_FR_4) {retVal = 5;} - else if (mode == GPIO_FR_5) {retVal = 6;} - else if (mode == GPIO_FR_6) {retVal = 7;} - else if (mode == GPIO_FR_7) {retVal = 8;} - else if (mode == GPIO_FR_NA) {retVal = 1;} - else if (mode == 0) {retVal = 1;} - else {retVal = 13;} - - return retVal; -} - -static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) -{ - int32_t result = PARAM_NG; - uint8_t chgmode; - uint16_t tmp; - - chgmode = change_mode_to_num(mode); - if ((chgmode < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) - { - tmp = (PinExistTbl[group][num] >> chgmode) & 0x01; - result = PARAM_OK; - if (tmp == 0){ result = PARAM_NG;} - } - else - { - result = PARAM_NG; - } - - return (result); -} -static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) -{ - int32_t result = PARAM_NG; - uint8_t chgfunc; - uint16_t tmp; - - chgfunc = change_func_to_num(mode); - /* param check skip if func is INPUT or OUTPUT */ - if(chgfunc == 1) - { - return (PARAM_OK); - } - if ((chgfunc < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) - { - tmp = (PinExistTbl[group][num] >> chgfunc) & 0x01; - result = PARAM_OK; - if (tmp == 0){ result = PARAM_NG;} - } - else - { - result = PARAM_NG; - } - - return (result); -} -/** - * @} - */ /* End of group GPIO_Private_functions */ - - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup GPIO_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) - * @brief Initialize the GPIO object. - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) -{ - TXZ_Result result = TXZ_SUCCESS; - - /* Check the NULL of address. */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else - { - switch (group) - { -#if defined(TMPM4G6) - case GPIO_PORT_A: - /* PA Clock Enable */ - TSB_CG_FSYSMENB_IPMENB02 = 1U; - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - break; - case GPIO_PORT_B: - /* PB Clock Enable */ - TSB_CG_FSYSMENB_IPMENB03 = 1U; - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - break; - case GPIO_PORT_D: - /* PD Clock Enable */ - TSB_CG_FSYSMENB_IPMENB05 = 1U; - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - break; - case GPIO_PORT_E: - /* PE Clock Enable */ - TSB_CG_FSYSMENB_IPMENB06 = 1U; - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - break; - case GPIO_PORT_F: - /* PF Clock Enable */ - TSB_CG_FSYSMENB_IPMENB07= 1U; - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - break; - case GPIO_PORT_G: - /* PG Clock Enable */ - TSB_CG_FSYSMENB_IPMENB08 = 1U; - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - break; - case GPIO_PORT_H: - /* PH Clock Enable */ - TSB_CG_FSYSMENB_IPMENB09 = 1U; - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF8; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - break; - case GPIO_PORT_K: - /* PK Clock Enable */ - TSB_CG_FSYSMENB_IPMENB11 = 1U; - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - break; - case GPIO_PORT_L: - /* PL Clock Enable */ - TSB_CG_FSYSMENB_IPMENB12 = 1U; - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - break; - case GPIO_PORT_N: - /* PN Clock Enable */ - TSB_CG_FSYSMENB_IPMENB14 = 1U; - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - break; - case GPIO_PORT_P: - /* PP Clock Enable */ - TSB_CG_FSYSMENB_IPMENB15 = 1U; - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - break; - case GPIO_PORT_T: - /* PT Clock Enable */ - TSB_CG_FSYSMENB_IPMENB16 = 1U; - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - break; - case GPIO_PORT_Y: - /* PY Clock Enable */ - TSB_CG_FSYSMENB_IPMENB21 = 1U; - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - break; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) - case GPIO_PORT_A: - /* PA Clock Enable */ - TSB_CG_FSYSMENB_IPMENB02 = 1U; - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - break; - case GPIO_PORT_B: - /* PB Clock Enable */ - TSB_CG_FSYSMENB_IPMENB03 = 1U; - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - break; - case GPIO_PORT_C: - /* PC Clock Enable */ - TSB_CG_FSYSMENB_IPMENB04 = 1U; - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - break; - case GPIO_PORT_D: - /* PD Clock Enable */ - TSB_CG_FSYSMENB_IPMENB05 = 1U; - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - break; - case GPIO_PORT_E: - /* PE Clock Enable */ - TSB_CG_FSYSMENB_IPMENB06 = 1U; - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - break; - case GPIO_PORT_F: - /* PF Clock Enable */ - TSB_CG_FSYSMENB_IPMENB07= 1U; - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - break; - case GPIO_PORT_G: - /* PG Clock Enable */ - TSB_CG_FSYSMENB_IPMENB08 = 1U; - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - break; - case GPIO_PORT_H: - /* PH Clock Enable */ - TSB_CG_FSYSMENB_IPMENB09 = 1U; - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF8; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - break; - case GPIO_PORT_K: - /* PK Clock Enable */ - TSB_CG_FSYSMENB_IPMENB11 = 1U; - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - break; - case GPIO_PORT_L: - /* PL Clock Enable */ - TSB_CG_FSYSMENB_IPMENB12 = 1U; - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - break; - case GPIO_PORT_N: - /* PN Clock Enable */ - TSB_CG_FSYSMENB_IPMENB14 = 1U; - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - break; - case GPIO_PORT_P: - /* PP Clock Enable */ - TSB_CG_FSYSMENB_IPMENB15 = 1U; - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - break; - case GPIO_PORT_R: - /* PR Clock Enable */ - TSB_CG_FSYSMENB_IPMENB16 = 1U; - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - break; - case GPIO_PORT_T: - /* PT Clock Enable */ - TSB_CG_FSYSMENB_IPMENB17 = 1U; - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - break; - case GPIO_PORT_V: - /* PV Clock Enable */ - TSB_CG_FSYSMENB_IPMENB19 = 1U; - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - break; - case GPIO_PORT_Y: - /* PY Clock Enable */ - TSB_CG_FSYSMENB_IPMENB21 = 1U; - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - break; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) - case GPIO_PORT_A: - /* PA Clock Enable */ - TSB_CG_FSYSMENB_IPMENB02 = 1U; - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - break; - case GPIO_PORT_B: - /* PB Clock Enable */ - TSB_CG_FSYSMENB_IPMENB03 = 1U; - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - break; - case GPIO_PORT_C: - /* PC Clock Enable */ - TSB_CG_FSYSMENB_IPMENB04 = 1U; - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - break; - case GPIO_PORT_D: - /* PD Clock Enable */ - TSB_CG_FSYSMENB_IPMENB05 = 1U; - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - break; - case GPIO_PORT_E: - /* PE Clock Enable */ - TSB_CG_FSYSMENB_IPMENB06 = 1U; - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - break; - case GPIO_PORT_F: - /* PF Clock Enable */ - TSB_CG_FSYSMENB_IPMENB07= 1U; - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - break; - case GPIO_PORT_G: - /* PG Clock Enable */ - TSB_CG_FSYSMENB_IPMENB08 = 1U; - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - break; - case GPIO_PORT_H: - /* PH Clock Enable */ - TSB_CG_FSYSMENB_IPMENB09 = 1U; - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF8; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - break; - case GPIO_PORT_K: - /* PK Clock Enable */ - TSB_CG_FSYSMENB_IPMENB11 = 1U; - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - break; - case GPIO_PORT_L: - /* PL Clock Enable */ - TSB_CG_FSYSMENB_IPMENB12 = 1U; - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - break; - case GPIO_PORT_M: - /* PM Clock Enable */ - TSB_CG_FSYSMENB_IPMENB13 = 1U; - p_obj->p_pm_instance->DATA = 0x00; - p_obj->p_pm_instance->CR = 0x00; - p_obj->p_pm_instance->FR2 = 0x00; - p_obj->p_pm_instance->FR3 = 0x00; - p_obj->p_pm_instance->FR4 = 0x00; - p_obj->p_pm_instance->FR5 = 0x00; - p_obj->p_pm_instance->FR6 = 0x00; - p_obj->p_pm_instance->FR7 = 0x00; - p_obj->p_pm_instance->OD = 0x00; - p_obj->p_pm_instance->PUP = 0x00; - p_obj->p_pm_instance->PDN = 0x00; - p_obj->p_pm_instance->IE = 0x00; - break; - case GPIO_PORT_N: - /* PN Clock Enable */ - TSB_CG_FSYSMENB_IPMENB14 = 1U; - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - break; - case GPIO_PORT_P: - /* PP Clock Enable */ - TSB_CG_FSYSMENB_IPMENB15 = 1U; - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - break; - case GPIO_PORT_R: - /* PR Clock Enable */ - TSB_CG_FSYSMENB_IPMENB16 = 1U; - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - break; - case GPIO_PORT_T: - /* PT Clock Enable */ - TSB_CG_FSYSMENB_IPMENB17 = 1U; - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - break; - case GPIO_PORT_V: - /* PV Clock Enable */ - TSB_CG_FSYSMENB_IPMENB19 = 1U; - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - break; - case GPIO_PORT_Y: - /* PY Clock Enable */ - TSB_CG_FSYSMENB_IPMENB21 = 1U; - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - break; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) - case GPIO_PORT_A: - /* PA Clock Enable */ - TSB_CG_FSYSMENB_IPMENB02 = 1U; - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - break; - case GPIO_PORT_B: - /* PB Clock Enable */ - TSB_CG_FSYSMENB_IPMENB03 = 1U; - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - break; - case GPIO_PORT_C: - /* PC Clock Enable */ - TSB_CG_FSYSMENB_IPMENB04 = 1U; - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - break; - case GPIO_PORT_D: - /* PD Clock Enable */ - TSB_CG_FSYSMENB_IPMENB05 = 1U; - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - break; - case GPIO_PORT_E: - /* PE Clock Enable */ - TSB_CG_FSYSMENB_IPMENB06 = 1U; - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - break; - case GPIO_PORT_F: - /* PF Clock Enable */ - TSB_CG_FSYSMENB_IPMENB07= 1U; - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - break; - case GPIO_PORT_G: - /* PG Clock Enable */ - TSB_CG_FSYSMENB_IPMENB08 = 1U; - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - break; - case GPIO_PORT_H: - /* PH Clock Enable */ - TSB_CG_FSYSMENB_IPMENB09 = 1U; - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF8; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - break; - case GPIO_PORT_J: - /* PJ Clock Enable */ - TSB_CG_FSYSMENB_IPMENB10 = 1U; - p_obj->p_pj_instance->DATA = 0x00; - p_obj->p_pj_instance->CR = 0x00; - p_obj->p_pj_instance->FR2 = 0x00; - p_obj->p_pj_instance->FR3 = 0x00; - p_obj->p_pj_instance->FR5 = 0x00; - p_obj->p_pj_instance->FR7 = 0x00; - p_obj->p_pj_instance->OD = 0x00; - p_obj->p_pj_instance->PUP = 0x00; - p_obj->p_pj_instance->PDN = 0x00; - p_obj->p_pj_instance->IE = 0x00; - break; - case GPIO_PORT_K: - /* PK Clock Enable */ - TSB_CG_FSYSMENB_IPMENB11 = 1U; - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - break; - case GPIO_PORT_L: - /* PL Clock Enable */ - TSB_CG_FSYSMENB_IPMENB12 = 1U; - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - break; - case GPIO_PORT_M: - /* PM Clock Enable */ - TSB_CG_FSYSMENB_IPMENB13 = 1U; - p_obj->p_pm_instance->DATA = 0x00; - p_obj->p_pm_instance->CR = 0x00; - p_obj->p_pm_instance->FR2 = 0x00; - p_obj->p_pm_instance->FR3 = 0x00; - p_obj->p_pm_instance->FR4 = 0x00; - p_obj->p_pm_instance->FR5 = 0x00; - p_obj->p_pm_instance->FR6 = 0x00; - p_obj->p_pm_instance->FR7 = 0x00; - p_obj->p_pm_instance->OD = 0x00; - p_obj->p_pm_instance->PUP = 0x00; - p_obj->p_pm_instance->PDN = 0x00; - p_obj->p_pm_instance->IE = 0x00; - break; - case GPIO_PORT_N: - /* PN Clock Enable */ - TSB_CG_FSYSMENB_IPMENB14 = 1U; - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - break; - case GPIO_PORT_P: - /* PP Clock Enable */ - TSB_CG_FSYSMENB_IPMENB15 = 1U; - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - break; - case GPIO_PORT_R: - /* PR Clock Enable */ - TSB_CG_FSYSMENB_IPMENB16 = 1U; - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - break; - case GPIO_PORT_T: - /* PT Clock Enable */ - TSB_CG_FSYSMENB_IPMENB17 = 1U; - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - break; - case GPIO_PORT_U: - /* PU Clock Enable */ - TSB_CG_FSYSMENB_IPMENB18 = 1U; - p_obj->p_pu_instance->DATA = 0x00; - p_obj->p_pu_instance->CR = 0x00; - p_obj->p_pu_instance->FR2 = 0x00; - p_obj->p_pu_instance->FR3 = 0x00; - p_obj->p_pu_instance->FR7 = 0x00; - p_obj->p_pu_instance->OD = 0x00; - p_obj->p_pu_instance->PUP = 0x00; - p_obj->p_pu_instance->PDN = 0x00; - p_obj->p_pu_instance->IE = 0x00; - break; - case GPIO_PORT_V: - /* PV Clock Enable */ - TSB_CG_FSYSMENB_IPMENB19 = 1U; - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - break; - case GPIO_PORT_W: - /* PW Clock Enable */ - TSB_CG_FSYSMENB_IPMENB20 = 1U; - p_obj->p_pw_instance->DATA = 0x00; - p_obj->p_pw_instance->CR = 0x00; - p_obj->p_pw_instance->FR3 = 0x00; - p_obj->p_pw_instance->FR4 = 0x00; - p_obj->p_pw_instance->FR5 = 0x00; - p_obj->p_pw_instance->FR6 = 0x00; - p_obj->p_pw_instance->FR7 = 0x00; - p_obj->p_pw_instance->OD = 0x00; - p_obj->p_pw_instance->PUP = 0x00; - p_obj->p_pw_instance->PDN = 0x00; - p_obj->p_pw_instance->IE = 0x00; - break; - case GPIO_PORT_Y: - /* PY Clock Enable */ - TSB_CG_FSYSMENB_IPMENB21 = 1U; - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - break; -#endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - return (result); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) - * @brief Release the GPIO object. - * @param p_obj :GPIO object. - * @param group :GPIO Port Group.: Use @ref gpio_gr_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) -{ - TXZ_Result result = TXZ_SUCCESS; - - /* Check the NULL of address. */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else - { - /* Disable the selected GPIO peripheral */ - switch (group) - { -#if defined(TMPM4G6) - case GPIO_PORT_A: - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - /* PA Clock Disable */ - TSB_CG_FSYSMENB_IPMENB02 = 0U; - break; - case GPIO_PORT_B: - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - /* PB Clock Disable */ - TSB_CG_FSYSMENB_IPMENB03 = 0U; - break; - case GPIO_PORT_D: - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - /* PD Clock Disable */ - TSB_CG_FSYSMENB_IPMENB05 = 0U; - break; - case GPIO_PORT_E: - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - /* PE Clock Disable */ - TSB_CG_FSYSMENB_IPMENB06 = 0U; - break; - case GPIO_PORT_F: - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - /* PF Clock Disable */ - TSB_CG_FSYSMENB_IPMENB07= 0U; - break; - case GPIO_PORT_G: - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - /* PG Clock Disable */ - TSB_CG_FSYSMENB_IPMENB08 = 0U; - break; - case GPIO_PORT_H: - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF0; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - /* PH Clock Disable */ - TSB_CG_FSYSMENB_IPMENB09 = 0U; - break; - case GPIO_PORT_K: - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - /* PK Clock Disable */ - TSB_CG_FSYSMENB_IPMENB11 = 0U; - break; - case GPIO_PORT_L: - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - /* PL Clock Disable */ - TSB_CG_FSYSMENB_IPMENB12 = 0U; - break; - case GPIO_PORT_N: - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - /* PN Clock Disable */ - TSB_CG_FSYSMENB_IPMENB14 = 0U; - break; - case GPIO_PORT_P: - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - /* PP Clock Disable */ - TSB_CG_FSYSMENB_IPMENB15 = 0U; - break; - case GPIO_PORT_T: - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - /* PT Clock Disable */ - TSB_CG_FSYSMENB_IPMENB16 = 0U; - break; - case GPIO_PORT_Y: - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - /* PY Clock Disable */ - TSB_CG_FSYSMENB_IPMENB21 = 0U; - break; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) - case GPIO_PORT_A: - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - /* PA Clock Disable */ - TSB_CG_FSYSMENB_IPMENB02 = 0U; - break; - case GPIO_PORT_B: - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - /* PB Clock Disable */ - TSB_CG_FSYSMENB_IPMENB03 = 0U; - break; - case GPIO_PORT_C: - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - /* PC Clock Disable */ - TSB_CG_FSYSMENB_IPMENB04 = 0U; - break; - case GPIO_PORT_D: - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - /* PD Clock Disable */ - TSB_CG_FSYSMENB_IPMENB05 = 0U; - break; - case GPIO_PORT_E: - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - /* PE Clock Disable */ - TSB_CG_FSYSMENB_IPMENB06 = 0U; - break; - case GPIO_PORT_F: - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - /* PF Clock Disable */ - TSB_CG_FSYSMENB_IPMENB07= 0U; - break; - case GPIO_PORT_G: - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - /* PG Clock Disable */ - TSB_CG_FSYSMENB_IPMENB08 = 0U; - break; - case GPIO_PORT_H: - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF0; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - /* PH Clock Disable */ - TSB_CG_FSYSMENB_IPMENB09 = 0U; - break; - case GPIO_PORT_K: - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - /* PK Clock Disable */ - TSB_CG_FSYSMENB_IPMENB11 = 0U; - break; - case GPIO_PORT_L: - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - /* PL Clock Disable */ - TSB_CG_FSYSMENB_IPMENB12 = 0U; - break; - case GPIO_PORT_N: - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - /* PN Clock Disable */ - TSB_CG_FSYSMENB_IPMENB14 = 0U; - break; - case GPIO_PORT_P: - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - /* PP Clock Disable */ - TSB_CG_FSYSMENB_IPMENB15 = 0U; - break; - case GPIO_PORT_R: - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - /* PR Clock Disable */ - TSB_CG_FSYSMENB_IPMENB16 = 0U; - break; - case GPIO_PORT_T: - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - /* PT Clock Disable */ - TSB_CG_FSYSMENB_IPMENB17 = 0U; - break; - case GPIO_PORT_V: - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - /* PV Clock Disable */ - TSB_CG_FSYSMENB_IPMENB19 = 0U; - break; - case GPIO_PORT_Y: - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - /* PY Clock Disable */ - TSB_CG_FSYSMENB_IPMENB21 = 0U; - break; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) - case GPIO_PORT_A: - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - /* PA Clock Disable */ - TSB_CG_FSYSMENB_IPMENB02 = 0U; - break; - case GPIO_PORT_B: - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - /* PB Clock Disable */ - TSB_CG_FSYSMENB_IPMENB03 = 0U; - break; - case GPIO_PORT_C: - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - /* PC Clock Disable */ - TSB_CG_FSYSMENB_IPMENB04 = 0U; - break; - case GPIO_PORT_D: - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - /* PD Clock Disable */ - TSB_CG_FSYSMENB_IPMENB05 = 0U; - break; - case GPIO_PORT_E: - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - /* PE Clock Disable */ - TSB_CG_FSYSMENB_IPMENB06 = 0U; - break; - case GPIO_PORT_F: - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - /* PF Clock Disable */ - TSB_CG_FSYSMENB_IPMENB07= 0U; - break; - case GPIO_PORT_G: - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - /* PG Clock Disable */ - TSB_CG_FSYSMENB_IPMENB08 = 0U; - break; - case GPIO_PORT_H: - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF0; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - /* PH Clock Disable */ - TSB_CG_FSYSMENB_IPMENB09 = 0U; - break; - case GPIO_PORT_K: - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - /* PK Clock Disable */ - TSB_CG_FSYSMENB_IPMENB11 = 0U; - break; - case GPIO_PORT_L: - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - /* PL Clock Disable */ - TSB_CG_FSYSMENB_IPMENB12 = 0U; - break; - case GPIO_PORT_M: - p_obj->p_pm_instance->DATA = 0x00; - p_obj->p_pm_instance->CR = 0x00; - p_obj->p_pm_instance->FR2 = 0x00; - p_obj->p_pm_instance->FR3 = 0x00; - p_obj->p_pm_instance->FR4 = 0x00; - p_obj->p_pm_instance->FR5 = 0x00; - p_obj->p_pm_instance->FR6 = 0x00; - p_obj->p_pm_instance->FR7 = 0x00; - p_obj->p_pm_instance->OD = 0x00; - p_obj->p_pm_instance->PUP = 0x00; - p_obj->p_pm_instance->PDN = 0x00; - p_obj->p_pm_instance->IE = 0x00; - /* PM Clock Disable */ - TSB_CG_FSYSMENB_IPMENB13 = 0U; - break; - case GPIO_PORT_N: - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - /* PN Clock Disable */ - TSB_CG_FSYSMENB_IPMENB14 = 0U; - break; - case GPIO_PORT_P: - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - /* PP Clock Disable */ - TSB_CG_FSYSMENB_IPMENB15 = 0U; - break; - case GPIO_PORT_R: - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - /* PR Clock Disable */ - TSB_CG_FSYSMENB_IPMENB16 = 0U; - break; - case GPIO_PORT_T: - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - /* PT Clock Disable */ - TSB_CG_FSYSMENB_IPMENB17 = 0U; - break; - case GPIO_PORT_V: - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - /* PV Clock Disable */ - TSB_CG_FSYSMENB_IPMENB19 = 0U; - break; - case GPIO_PORT_Y: - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - /* PY Clock Disable */ - TSB_CG_FSYSMENB_IPMENB21 = 0U; - break; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) - case GPIO_PORT_A: - p_obj->p_pa_instance->DATA = 0x00; - p_obj->p_pa_instance->CR = 0x00; - p_obj->p_pa_instance->FR1 = 0x00; - p_obj->p_pa_instance->FR2 = 0x00; - p_obj->p_pa_instance->FR3 = 0x00; - p_obj->p_pa_instance->FR5 = 0x00; - p_obj->p_pa_instance->FR6 = 0x00; - p_obj->p_pa_instance->FR7 = 0x00; - p_obj->p_pa_instance->OD = 0x00; - p_obj->p_pa_instance->PUP = 0x00; - p_obj->p_pa_instance->PDN = 0x00; - p_obj->p_pa_instance->IE = 0x00; - /* PA Clock Disable */ - TSB_CG_FSYSMENB_IPMENB02 = 0U; - break; - case GPIO_PORT_B: - p_obj->p_pb_instance->DATA = 0x00; - p_obj->p_pb_instance->CR = 0x00; - p_obj->p_pb_instance->FR1 = 0x00; - p_obj->p_pb_instance->FR2 = 0x00; - p_obj->p_pb_instance->FR3 = 0x00; - p_obj->p_pb_instance->FR5 = 0x00; - p_obj->p_pb_instance->FR6 = 0x00; - p_obj->p_pb_instance->OD = 0x00; - p_obj->p_pb_instance->PUP = 0x00; - p_obj->p_pb_instance->PDN = 0x00; - p_obj->p_pb_instance->IE = 0x00; - /* PB Clock Disable */ - TSB_CG_FSYSMENB_IPMENB03 = 0U; - break; - case GPIO_PORT_C: - p_obj->p_pc_instance->DATA = 0x00; - p_obj->p_pc_instance->CR = 0x00; - p_obj->p_pc_instance->FR1 = 0x00; - p_obj->p_pc_instance->FR3 = 0x00; - p_obj->p_pc_instance->FR5 = 0x00; - p_obj->p_pc_instance->OD = 0x00; - p_obj->p_pc_instance->PUP = 0x00; - p_obj->p_pc_instance->PDN = 0x00; - p_obj->p_pc_instance->IE = 0x00; - /* PC Clock Disable */ - TSB_CG_FSYSMENB_IPMENB04 = 0U; - break; - case GPIO_PORT_D: - p_obj->p_pd_instance->DATA = 0x00; - p_obj->p_pd_instance->CR = 0x00; - p_obj->p_pd_instance->FR1 = 0x00; - p_obj->p_pd_instance->FR2 = 0x00; - p_obj->p_pd_instance->FR3 = 0x00; - p_obj->p_pd_instance->FR4 = 0x00; - p_obj->p_pd_instance->FR5 = 0x00; - p_obj->p_pd_instance->FR6 = 0x00; - p_obj->p_pd_instance->FR7 = 0x00; - p_obj->p_pd_instance->OD = 0x00; - p_obj->p_pd_instance->PUP = 0x00; - p_obj->p_pd_instance->PDN = 0x00; - p_obj->p_pd_instance->IE = 0x00; - /* PD Clock Disable */ - TSB_CG_FSYSMENB_IPMENB05 = 0U; - break; - case GPIO_PORT_E: - p_obj->p_pe_instance->DATA = 0x00; - p_obj->p_pe_instance->CR = 0x00; - p_obj->p_pe_instance->FR1 = 0x00; - p_obj->p_pe_instance->FR2 = 0x00; - p_obj->p_pe_instance->FR3 = 0x00; - p_obj->p_pe_instance->FR4 = 0x00; - p_obj->p_pe_instance->FR5 = 0x00; - p_obj->p_pe_instance->FR7 = 0x00; - p_obj->p_pe_instance->OD = 0x00; - p_obj->p_pe_instance->PUP = 0x00; - p_obj->p_pe_instance->PDN = 0x00; - p_obj->p_pe_instance->IE = 0x00; - /* PE Clock Disable */ - TSB_CG_FSYSMENB_IPMENB06 = 0U; - break; - case GPIO_PORT_F: - p_obj->p_pf_instance->DATA = 0x00; - p_obj->p_pf_instance->CR = 0x00; - p_obj->p_pf_instance->FR1 = 0x00; - p_obj->p_pf_instance->FR7 = 0x00; - p_obj->p_pf_instance->OD = 0x00; - p_obj->p_pf_instance->PUP = 0x00; - p_obj->p_pf_instance->PDN = 0x00; - p_obj->p_pf_instance->IE = 0x00; - /* PF Clock Disable */ - TSB_CG_FSYSMENB_IPMENB07= 0U; - break; - case GPIO_PORT_G: - p_obj->p_pg_instance->DATA = 0x00; - p_obj->p_pg_instance->CR = 0x00; - p_obj->p_pg_instance->FR1 = 0x00; - p_obj->p_pg_instance->FR2 = 0x00; - p_obj->p_pg_instance->FR3 = 0x00; - p_obj->p_pg_instance->FR4 = 0x00; - p_obj->p_pg_instance->FR5 = 0x00; - p_obj->p_pg_instance->FR7 = 0x00; - p_obj->p_pg_instance->OD = 0x00; - p_obj->p_pg_instance->PUP = 0x00; - p_obj->p_pg_instance->PDN = 0x00; - p_obj->p_pg_instance->IE = 0x00; - /* PG Clock Disable */ - TSB_CG_FSYSMENB_IPMENB08 = 0U; - break; - case GPIO_PORT_H: - p_obj->p_ph_instance->DATA = 0x00; - p_obj->p_ph_instance->CR = 0x50; - p_obj->p_ph_instance->FR1 = 0xF0; - p_obj->p_ph_instance->FR3 = 0x00; - p_obj->p_ph_instance->FR4 = 0x00; - p_obj->p_ph_instance->FR5 = 0x00; - p_obj->p_ph_instance->OD = 0x00; - p_obj->p_ph_instance->PUP = 0x98; - p_obj->p_ph_instance->PDN = 0x20; - p_obj->p_ph_instance->IE = 0xB8; - /* PH Clock Disable */ - TSB_CG_FSYSMENB_IPMENB09 = 0U; - break; - case GPIO_PORT_J: - p_obj->p_pj_instance->DATA = 0x00; - p_obj->p_pj_instance->CR = 0x00; - p_obj->p_pj_instance->FR2 = 0x00; - p_obj->p_pj_instance->FR3 = 0x00; - p_obj->p_pj_instance->FR5 = 0x00; - p_obj->p_pj_instance->FR7 = 0x00; - p_obj->p_pj_instance->OD = 0x00; - p_obj->p_pj_instance->PUP = 0x00; - p_obj->p_pj_instance->PDN = 0x00; - p_obj->p_pj_instance->IE = 0x00; - /* PJ Clock Disable */ - TSB_CG_FSYSMENB_IPMENB10 = 0U; - break; - case GPIO_PORT_K: - p_obj->p_pk_instance->DATA = 0x00; - p_obj->p_pk_instance->CR = 0x00; - p_obj->p_pk_instance->FR1 = 0x00; - p_obj->p_pk_instance->FR2 = 0x00; - p_obj->p_pk_instance->FR3 = 0x00; - p_obj->p_pk_instance->FR4 = 0x00; - p_obj->p_pk_instance->FR6 = 0x00; - p_obj->p_pk_instance->FR7 = 0x00; - p_obj->p_pk_instance->OD = 0x00; - p_obj->p_pk_instance->PUP = 0x00; - p_obj->p_pk_instance->PDN = 0x00; - p_obj->p_pk_instance->IE = 0x00; - /* PK Clock Disable */ - TSB_CG_FSYSMENB_IPMENB11 = 0U; - break; - case GPIO_PORT_L: - p_obj->p_pl_instance->DATA = 0x00; - p_obj->p_pl_instance->CR = 0x00; - p_obj->p_pl_instance->FR1 = 0x00; - p_obj->p_pl_instance->FR2 = 0x00; - p_obj->p_pl_instance->FR3 = 0x00; - p_obj->p_pl_instance->FR6 = 0x00; - p_obj->p_pl_instance->FR7 = 0x00; - p_obj->p_pl_instance->OD = 0x00; - p_obj->p_pl_instance->PUP = 0x00; - p_obj->p_pl_instance->PDN = 0x00; - p_obj->p_pl_instance->IE = 0x00; - /* PL Clock Disable */ - TSB_CG_FSYSMENB_IPMENB12 = 0U; - break; - case GPIO_PORT_M: - p_obj->p_pm_instance->DATA = 0x00; - p_obj->p_pm_instance->CR = 0x00; - p_obj->p_pm_instance->FR2 = 0x00; - p_obj->p_pm_instance->FR3 = 0x00; - p_obj->p_pm_instance->FR4 = 0x00; - p_obj->p_pm_instance->FR5 = 0x00; - p_obj->p_pm_instance->FR6 = 0x00; - p_obj->p_pm_instance->FR7 = 0x00; - p_obj->p_pm_instance->OD = 0x00; - p_obj->p_pm_instance->PUP = 0x00; - p_obj->p_pm_instance->PDN = 0x00; - p_obj->p_pm_instance->IE = 0x00; - /* PM Clock Disable */ - TSB_CG_FSYSMENB_IPMENB13 = 0U; - break; - case GPIO_PORT_N: - p_obj->p_pn_instance->DATA = 0x00; - p_obj->p_pn_instance->CR = 0x00; - p_obj->p_pn_instance->OD = 0x00; - p_obj->p_pn_instance->PUP = 0x00; - p_obj->p_pn_instance->PDN = 0x00; - p_obj->p_pn_instance->IE = 0x00; - /* PN Clock Disable */ - TSB_CG_FSYSMENB_IPMENB14 = 0U; - break; - case GPIO_PORT_P: - p_obj->p_pp_instance->DATA = 0x00; - p_obj->p_pp_instance->CR = 0x00; - p_obj->p_pp_instance->FR2 = 0x00; - p_obj->p_pp_instance->FR3 = 0x00; - p_obj->p_pp_instance->FR5 = 0x00; - p_obj->p_pp_instance->OD = 0x00; - p_obj->p_pp_instance->PUP = 0x00; - p_obj->p_pp_instance->PDN = 0x00; - p_obj->p_pp_instance->IE = 0x00; - /* PP Clock Disable */ - TSB_CG_FSYSMENB_IPMENB15 = 0U; - break; - case GPIO_PORT_R: - p_obj->p_pr_instance->DATA = 0x00; - p_obj->p_pr_instance->CR = 0x00; - p_obj->p_pr_instance->FR2 = 0x00; - p_obj->p_pr_instance->FR3 = 0x00; - p_obj->p_pr_instance->OD = 0x00; - p_obj->p_pr_instance->PUP = 0x00; - p_obj->p_pr_instance->PDN = 0x00; - p_obj->p_pr_instance->IE = 0x00; - /* PR Clock Disable */ - TSB_CG_FSYSMENB_IPMENB16 = 0U; - break; - case GPIO_PORT_T: - p_obj->p_pt_instance->DATA = 0x00; - p_obj->p_pt_instance->CR = 0x00; - p_obj->p_pt_instance->FR1 = 0x00; - p_obj->p_pt_instance->FR2 = 0x00; - p_obj->p_pt_instance->FR3 = 0x00; - p_obj->p_pt_instance->FR6 = 0x00; - p_obj->p_pt_instance->FR7 = 0x00; - p_obj->p_pt_instance->OD = 0x00; - p_obj->p_pt_instance->PUP = 0x00; - p_obj->p_pt_instance->PDN = 0x00; - p_obj->p_pt_instance->IE = 0x00; - /* PT Clock Disable */ - TSB_CG_FSYSMENB_IPMENB17 = 0U; - break; - case GPIO_PORT_U: - p_obj->p_pu_instance->DATA = 0x00; - p_obj->p_pu_instance->CR = 0x00; - p_obj->p_pu_instance->FR2 = 0x00; - p_obj->p_pu_instance->FR3 = 0x00; - p_obj->p_pu_instance->FR7 = 0x00; - p_obj->p_pu_instance->OD = 0x00; - p_obj->p_pu_instance->PUP = 0x00; - p_obj->p_pu_instance->PDN = 0x00; - p_obj->p_pu_instance->IE = 0x00; - /* PU Clock Disable */ - TSB_CG_FSYSMENB_IPMENB18 = 0U; - break; - case GPIO_PORT_V: - p_obj->p_pv_instance->DATA = 0x00; - p_obj->p_pv_instance->CR = 0x00; - p_obj->p_pv_instance->FR2 = 0x00; - p_obj->p_pv_instance->FR3 = 0x00; - p_obj->p_pv_instance->FR4 = 0x00; - p_obj->p_pv_instance->FR5 = 0x00; - p_obj->p_pv_instance->FR6 = 0x00; - p_obj->p_pv_instance->FR7 = 0x00; - p_obj->p_pv_instance->OD = 0x00; - p_obj->p_pv_instance->PUP = 0x00; - p_obj->p_pv_instance->PDN = 0x00; - p_obj->p_pv_instance->IE = 0x00; - /* PV Clock Disable */ - TSB_CG_FSYSMENB_IPMENB19 = 0U; - break; - case GPIO_PORT_W: - p_obj->p_pw_instance->DATA = 0x00; - p_obj->p_pw_instance->CR = 0x00; - p_obj->p_pw_instance->FR3 = 0x00; - p_obj->p_pw_instance->FR4 = 0x00; - p_obj->p_pw_instance->FR5 = 0x00; - p_obj->p_pw_instance->FR6 = 0x00; - p_obj->p_pw_instance->FR7 = 0x00; - p_obj->p_pw_instance->OD = 0x00; - p_obj->p_pw_instance->PUP = 0x00; - p_obj->p_pw_instance->PDN = 0x00; - p_obj->p_pw_instance->IE = 0x00; - /* PW Clock Disable */ - TSB_CG_FSYSMENB_IPMENB20 = 0U; - break; - case GPIO_PORT_Y: - p_obj->p_py_instance->DATA = 0x00; - p_obj->p_py_instance->CR = 0x00; - p_obj->p_py_instance->FR1 = 0x00; - p_obj->p_py_instance->FR4 = 0x00; - p_obj->p_py_instance->OD = 0x00; - p_obj->p_py_instance->PUP = 0x00; - p_obj->p_py_instance->PDN = 0x00; - p_obj->p_py_instance->IE = 0x00; - /* PY Clock Disable */ - TSB_CG_FSYSMENB_IPMENB21 = 0U; - break; -#endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - return (result); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) - * @brief Port Mode Write - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t - * @param[in] val :value - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - int32_t i; - int32_t param_result = PARAM_NG; - - /* Check the parameters, the NULL of address */ - for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) - { - param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); - if(param_result == PARAM_OK) - { - break; - } - else - { - result = TXZ_ERROR; - } - } - if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG)) - { - result = TXZ_ERROR; - } - else - { - switch (group) - { -#if defined(TMPM4G6) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;} - break; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;} - break; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;} - break; - case GPIO_PORT_M: - if(mode == GPIO_Mode_DATA) {p_obj->p_pm_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pm_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pm_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pm_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pm_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pm_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pm_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pm_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pm_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pm_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pm_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pm_instance->IE = val;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;} - break; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;} - break; - case GPIO_PORT_J: - if(mode == GPIO_Mode_DATA) {p_obj->p_pj_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pj_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pj_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pj_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pj_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pj_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pj_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pj_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pj_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pj_instance->IE = val;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;} - break; - case GPIO_PORT_M: - if(mode == GPIO_Mode_DATA) {p_obj->p_pm_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pm_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pm_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pm_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pm_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pm_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pm_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pm_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pm_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pm_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pm_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pm_instance->IE = val;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;} - break; - case GPIO_PORT_U: - if(mode == GPIO_Mode_DATA) {p_obj->p_pu_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pu_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pu_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pu_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pu_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pu_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pu_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pu_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pu_instance->IE = val;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;} - else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;} - break; - case GPIO_PORT_W: - if(mode == GPIO_Mode_DATA) {p_obj->p_pw_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_pw_instance->CR = val;} - else if(mode == GPIO_Mode_FR3) {p_obj->p_pw_instance->FR3 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_pw_instance->FR4 = val;} - else if(mode == GPIO_Mode_FR5) {p_obj->p_pw_instance->FR5 = val;} - else if(mode == GPIO_Mode_FR6) {p_obj->p_pw_instance->FR6 = val;} - else if(mode == GPIO_Mode_FR7) {p_obj->p_pw_instance->FR7 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_pw_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_pw_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_pw_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_pw_instance->IE = val;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;} - else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;} - else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;} - else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;} - else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;} - else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;} - else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;} - else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;} - break; -#endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - return (result); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) - * @brief Port Mode Read - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t - * @param[out] val :Store of value - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) -{ - TXZ_Result result = TXZ_SUCCESS; - int32_t param_result = PARAM_NG; - int32_t i; - - /* Check the parameters, the NULL of address */ - for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++ ) - { - param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); - if(param_result == PARAM_OK) - { - break; - } - else - { - result = TXZ_ERROR; - } - } - if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG)) - { - result = TXZ_ERROR; - } - else - { - switch (group) - { -#if defined(TMPM4G6) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;} - break; -#endif /* TMPM4G6 */ -#if defined(TMPM4G7) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;} - break; -#endif /* TMPM4G7 */ -#if defined(TMPM4G8) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;} - break; - case GPIO_PORT_M: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pm_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pm_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pm_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pm_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pm_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pm_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pm_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pm_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pm_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pm_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pm_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pm_instance->IE;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;} - break; -#endif /* TMPM4G8 */ -#if defined(TMPM4G9) - case GPIO_PORT_A: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;} - break; - case GPIO_PORT_B: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;} - break; - case GPIO_PORT_C: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;} - break; - case GPIO_PORT_D: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;} - break; - case GPIO_PORT_E: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;} - break; - case GPIO_PORT_F: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;} - break; - case GPIO_PORT_G: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;} - break; - case GPIO_PORT_H: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;} - break; - case GPIO_PORT_J: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pj_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pj_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pj_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pj_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pj_instance->FR5;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pj_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pj_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pj_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pj_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pj_instance->IE;} - break; - case GPIO_PORT_K: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;} - break; - case GPIO_PORT_L: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;} - break; - case GPIO_PORT_M: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pm_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pm_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pm_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pm_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pm_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pm_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pm_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pm_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pm_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pm_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pm_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pm_instance->IE;} - break; - case GPIO_PORT_N: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;} - break; - case GPIO_PORT_P: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;} - break; - case GPIO_PORT_R: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;} - break; - case GPIO_PORT_T: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;} - break; - case GPIO_PORT_U: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pu_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pu_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pu_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pu_instance->FR3;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pu_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pu_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pu_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pu_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pu_instance->IE;} - break; - case GPIO_PORT_V: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;} - else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;} - break; - case GPIO_PORT_W: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pw_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pw_instance->CR;} - else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pw_instance->FR3;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pw_instance->FR4;} - else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pw_instance->FR5;} - else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pw_instance->FR6;} - else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pw_instance->FR7;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pw_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pw_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pw_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pw_instance->IE;} - break; - case GPIO_PORT_Y: - if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;} - else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;} - else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;} - else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;} - else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;} - else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;} - else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;} - else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;} - break; -#endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - } - } - - return result; -} - -/*--------------------------------------------------*/ -/** - * @brief Port Function switching - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param func :GPIO Portxx Func. : Use @ref gpio_pa0_func_t - @ref gpio_pl4_func_t - * @param inout :GPIO Input/Output.: Use @ref gpio_pininout_t - * @retval GPIO_RESULT_SUCCESS :Success. - * @retval GPIO_RESULT_FAILURE :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t port_base; - uint32_t mode_base; - int32_t param_result = PARAM_NG; - - /* Check the parameters, the NULL of address */ - param_result = check_param_func_pin_exist(p_obj, group, num, func); - if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG)) - { - result = TXZ_ERROR; - } - else - { - switch (group) - { - #if defined(TMPM4G6) - case GPIO_PORT_A: - port_base = (uint32_t)p_obj->p_pa_instance; - break; - case GPIO_PORT_B: - port_base = (uint32_t)p_obj->p_pb_instance; - break; - case GPIO_PORT_D: - port_base = (uint32_t)p_obj->p_pd_instance; - break; - case GPIO_PORT_E: - port_base = (uint32_t)p_obj->p_pe_instance; - break; - case GPIO_PORT_F: - port_base = (uint32_t)p_obj->p_pf_instance; - break; - case GPIO_PORT_G: - port_base = (uint32_t)p_obj->p_pg_instance; - break; - case GPIO_PORT_H: - port_base = (uint32_t)p_obj->p_ph_instance; - break; - case GPIO_PORT_K: - port_base = (uint32_t)p_obj->p_pk_instance; - break; - case GPIO_PORT_L: - port_base = (uint32_t)p_obj->p_pl_instance; - break; - case GPIO_PORT_N: - port_base = (uint32_t)p_obj->p_pn_instance; - break; - case GPIO_PORT_P: - port_base = (uint32_t)p_obj->p_pp_instance; - break; - case GPIO_PORT_T: - port_base = (uint32_t)p_obj->p_pt_instance; - break; - case GPIO_PORT_Y: - port_base = (uint32_t)p_obj->p_py_instance; - break; - #endif /* TMPM4G6 */ - #if defined(TMPM4G7) - case GPIO_PORT_A: - port_base = (uint32_t)p_obj->p_pa_instance; - break; - case GPIO_PORT_B: - port_base = (uint32_t)p_obj->p_pb_instance; - break; - case GPIO_PORT_C: - port_base = (uint32_t)p_obj->p_pc_instance; - break; - case GPIO_PORT_D: - port_base = (uint32_t)p_obj->p_pd_instance; - break; - case GPIO_PORT_E: - port_base = (uint32_t)p_obj->p_pe_instance; - break; - case GPIO_PORT_F: - port_base = (uint32_t)p_obj->p_pf_instance; - break; - case GPIO_PORT_G: - port_base = (uint32_t)p_obj->p_pg_instance; - break; - case GPIO_PORT_H: - port_base = (uint32_t)p_obj->p_ph_instance; - break; - case GPIO_PORT_K: - port_base = (uint32_t)p_obj->p_pk_instance; - break; - case GPIO_PORT_L: - port_base = (uint32_t)p_obj->p_pl_instance; - break; - case GPIO_PORT_N: - port_base = (uint32_t)p_obj->p_pn_instance; - break; - case GPIO_PORT_P: - port_base = (uint32_t)p_obj->p_pp_instance; - break; - case GPIO_PORT_R: - port_base = (uint32_t)p_obj->p_pr_instance; - break; - case GPIO_PORT_T: - port_base = (uint32_t)p_obj->p_pt_instance; - break; - case GPIO_PORT_V: - port_base = (uint32_t)p_obj->p_pv_instance; - break; - case GPIO_PORT_Y: - port_base = (uint32_t)p_obj->p_py_instance; - break; - #endif /* TMPM4G7 */ - #if defined(TMPM4G8) - case GPIO_PORT_A: - port_base = (uint32_t)p_obj->p_pa_instance; - break; - case GPIO_PORT_B: - port_base = (uint32_t)p_obj->p_pb_instance; - break; - case GPIO_PORT_C: - port_base = (uint32_t)p_obj->p_pc_instance; - break; - case GPIO_PORT_D: - port_base = (uint32_t)p_obj->p_pd_instance; - break; - case GPIO_PORT_E: - port_base = (uint32_t)p_obj->p_pe_instance; - break; - case GPIO_PORT_F: - port_base = (uint32_t)p_obj->p_pf_instance; - break; - case GPIO_PORT_G: - port_base = (uint32_t)p_obj->p_pg_instance; - break; - case GPIO_PORT_H: - port_base = (uint32_t)p_obj->p_ph_instance; - break; - case GPIO_PORT_K: - port_base = (uint32_t)p_obj->p_pk_instance; - break; - case GPIO_PORT_L: - port_base = (uint32_t)p_obj->p_pl_instance; - break; - case GPIO_PORT_M: - port_base = (uint32_t)p_obj->p_pm_instance; - break; - case GPIO_PORT_N: - port_base = (uint32_t)p_obj->p_pn_instance; - break; - case GPIO_PORT_P: - port_base = (uint32_t)p_obj->p_pp_instance; - break; - case GPIO_PORT_R: - port_base = (uint32_t)p_obj->p_pr_instance; - break; - case GPIO_PORT_T: - port_base = (uint32_t)p_obj->p_pt_instance; - break; - case GPIO_PORT_V: - port_base = (uint32_t)p_obj->p_pv_instance; - break; - case GPIO_PORT_Y: - port_base = (uint32_t)p_obj->p_py_instance; - break; - #endif /* TMPM4G8 */ - #if defined(TMPM4G9) - case GPIO_PORT_A: - port_base = (uint32_t)p_obj->p_pa_instance; - break; - case GPIO_PORT_B: - port_base = (uint32_t)p_obj->p_pb_instance; - break; - case GPIO_PORT_C: - port_base = (uint32_t)p_obj->p_pc_instance; - break; - case GPIO_PORT_D: - port_base = (uint32_t)p_obj->p_pd_instance; - break; - case GPIO_PORT_E: - port_base = (uint32_t)p_obj->p_pe_instance; - break; - case GPIO_PORT_F: - port_base = (uint32_t)p_obj->p_pf_instance; - break; - case GPIO_PORT_G: - port_base = (uint32_t)p_obj->p_pg_instance; - break; - case GPIO_PORT_H: - port_base = (uint32_t)p_obj->p_ph_instance; - break; - case GPIO_PORT_J: - port_base = (uint32_t)p_obj->p_pj_instance; - break; - case GPIO_PORT_K: - port_base = (uint32_t)p_obj->p_pk_instance; - break; - case GPIO_PORT_L: - port_base = (uint32_t)p_obj->p_pl_instance; - break; - case GPIO_PORT_M: - port_base = (uint32_t)p_obj->p_pm_instance; - break; - case GPIO_PORT_N: - port_base = (uint32_t)p_obj->p_pn_instance; - break; - case GPIO_PORT_P: - port_base = (uint32_t)p_obj->p_pp_instance; - break; - case GPIO_PORT_R: - port_base = (uint32_t)p_obj->p_pr_instance; - break; - case GPIO_PORT_T: - port_base = (uint32_t)p_obj->p_pt_instance; - break; - case GPIO_PORT_U: - port_base = (uint32_t)p_obj->p_pu_instance; - break; - case GPIO_PORT_V: - port_base = (uint32_t)p_obj->p_pv_instance; - break; - case GPIO_PORT_W: - port_base = (uint32_t)p_obj->p_pw_instance; - break; - case GPIO_PORT_Y: - port_base = (uint32_t)p_obj->p_py_instance; - break; - #endif /* TMPM4G9 */ - default: - result = TXZ_ERROR; - } - if(result == TXZ_ERROR) - { - return (result); - } - - /* Initialization PxFR OFF */ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - BITBAND_PORT_CLR(mode_base, num); - - /* Initialize Input/Output */ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - - switch (func) { - case 0: - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_1: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_2: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_3: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_4: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_5: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - } - break; - case GPIO_FR_6: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_7: - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); - BITBAND_PORT_SET(mode_base, num); - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - case GPIO_FR_NA: - if(inout== GPIO_PIN_OUTPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_CLR(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_INPUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_CLR(mode_base, num); - }else if(inout== GPIO_PIN_INOUT){ - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); - BITBAND_PORT_SET(mode_base, num); - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); - BITBAND_PORT_SET(mode_base, num); - }else if(inout== GPIO_PIN_NOTINOUT){ - /* No Process */ - } - break; - default: - result = TXZ_ERROR; - return (result); - } - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Set Pull up mode - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t port_base; - uint32_t mode_base; - - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PUP) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - port_base = BITBAND_PORT_BASE(group); - - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PUP); - if (val == GPIO_PIN_SET) - { - BITBAND_PORT_SET(mode_base, num); - } - else if (val == GPIO_PIN_RESET) - { - BITBAND_PORT_CLR(mode_base, num); - } - else{ result = TXZ_ERROR;} - } - - return result; -} - -/*--------------------------------------------------*/ -/** - * @brief Set Pull down mode - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t port_base; - uint32_t mode_base; - - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PDN) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - port_base = BITBAND_PORT_BASE(group); - - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PDN); - if (val == GPIO_PIN_SET) - { - BITBAND_PORT_SET(mode_base, num); - } - else if (val == GPIO_PIN_RESET) - { - BITBAND_PORT_CLR(mode_base, num); - } - else{ result = TXZ_ERROR;} - } - - return result; -} - -/*--------------------------------------------------*/ -/** - * @brief Set Open drain mode - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t port_base; - uint32_t mode_base; - - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_OD) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - port_base = BITBAND_PORT_BASE(group); - - mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_OD); - if (val == GPIO_PIN_SET) - { - BITBAND_PORT_SET(mode_base, num); - } - else if (val == GPIO_PIN_RESET) - { - BITBAND_PORT_CLR(mode_base, num); - } - else{ result = TXZ_ERROR;} - } - - return result; -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) - * @brief Port Bit Write - * @param p_obj :GPIO object. - * @param group :GPIO Port Group. : Use @ref gpio_gr_t - * @param num :GPIO Port Number. : Use @ref gpio_num_t - * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t - * @param val :GPIO Pin Reset/Set. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t base; - - /* Check the parameters */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - base = BITBAND_PORT_BASE(group); - base = BITBAND_PORT_MODE_BASE(base, mode); - if (val == GPIO_PIN_SET){ BITBAND_PORT_SET(base, num);} - else if (val == GPIO_PIN_RESET){ BITBAND_PORT_CLR(base, num);} - else{ result = TXZ_ERROR;} - } - - return (result); -} - -/*--------------------------------------------------*/ -/*! - * @fn TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) - * @brief Port Bit Read - * @param[in] p_obj :GPIO object. - * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t - * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t - * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t - * @param[out] *pinstate : store Value of GPIO BitPin. : Use @ref gpio_pinstate_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, no processing.: Use @ref gpio_pinstate_t - */ -/*--------------------------------------------------*/ -TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t base; - uint32_t val; - - /* Check the parameters */ - if ((void*)(p_obj) == (void*)0) - { - result = TXZ_ERROR; - } - else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) - { - result = TXZ_ERROR; - } - else - { - base = BITBAND_PORT_BASE(group); - base = BITBAND_PORT_MODE_BASE(base, mode); - BITBAND_PORT_READ(val, base, num); - if(val == GPIO_PIN_RESET){ *pinstate = GPIO_PIN_RESET;} - else if (val == GPIO_PIN_SET){ *pinstate = GPIO_PIN_SET;} - else{ result = TXZ_ERROR;} - } - - return result; -} - -/** - * @} - */ /* End of group GPIO_Exported_functions */ - -/** - * @} - */ /* End of group GPIO */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__GPIO_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_hal.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_hal.c deleted file mode 100644 index 26c3c1fc293..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_hal.c +++ /dev/null @@ -1,175 +0,0 @@ -/** - ******************************************************************************* - * @file txz_hal.c - * @brief This file provides API functions for driver common part. - * @version V1.0.0.0 - * $Date:: 2017-08-09 11:01:04 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_hal.h" - -#if defined(__HAL_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup HAL - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_macro HAL Private Macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_macro */ - - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_define HAL Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_define HAL Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_define HAL Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_typedef HAL Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group HAL_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup HAL_Private_fuctions HAL Private Fuctions - * @{ - */ - -static uint32_t tick; - -/** - * @} - */ /* End of group HAL_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup HAL_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Increment a tick value. - * @param - - * @retval - - * @note Please call by user. - * @note In the sample, this variable is incremented each 1ms timer interrupt. - */ -/*--------------------------------------------------*/ -void hal_inc_tick(void) -{ - tick++; -} - -/*--------------------------------------------------*/ -/** - * @brief Provides a tick value. - * @param - - * @return Tick value. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -uint32_t hal_get_tick(void) -{ - return(tick); -} - -/** - * @} - */ /* End of group HAL_Exported_functions */ - -/** - * @} - */ /* End of group HAL */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__HAL_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c.c deleted file mode 100644 index f9f30720f1b..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c.c +++ /dev/null @@ -1,415 +0,0 @@ -/** - ******************************************************************************* - * @file txz_i2c.c - * @brief This file provides API functions for I2C Class. - * @version V1.0.0.2 - * $Date:: 2016-11-08 00:00:00 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_i2c.h" - -#if defined(__I2C_H) - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_macro */ - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_variables - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_variables */ - -/*------------------------------------------------------------------------------*/ -/* Const Table */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_const - * @{ - */ -/*----------------------------------*/ -/** - * @brief SCK Divider value table. - * @details SCK = b000 - b111. - * @note NFSEL=0 (Digital Setting) Divider value. -*/ -/*----------------------------------*/ -static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20,24,32,48,80,144,272,528 }; -static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 }; - -/** - * @} - */ /* End of group UTILITIES_Private_const */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ - -/*--------------------------------------------------*/ -/** - * @brief Initializing I2C Regester - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2C_init(I2C_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE; - p_obj->p_instance->OP = I2CxOP_INIT; - p_obj->p_instance->CR1 = (I2CxCR1_ACK | /* I2CxCR1_NOACK | */ p_obj->init.clock.sck); - p_obj->p_instance->AR = I2CxAR_INIT; - p_obj->p_instance->AR2 = I2CxAR2_INIT; - p_obj->p_instance->CR2 = I2CxCR2_INIT; - p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); - p_obj->p_instance->IE = I2CxIE_CLEAR; -} - -/*--------------------------------------------------*/ -/** - * @brief Generate start condition - * @param p_obj :I2C object. - * @param data :Slave address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2C_start_condition(I2C_t *p_obj, uint32_t data) -{ - __IO uint32_t opreg; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - opreg = p_obj->p_instance->OP; - opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); - if(I2C_master(p_obj)){ - if ((p_obj->p_instance->SR & I2CxSR_BB)) - { - opreg |= I2CxOP_SREN; - } - } - p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); - p_obj->p_instance->OP = opreg; - p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); - p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION; -} - -/*--------------------------------------------------*/ -/** - * @brief Return the I2c clock setting - * @param p_obj :I2C object. - * @param frequency :Maximum frequency. - * @param fsys :SystemCoreClock. - * @param p_setting :Clock data pointer. - * @retval Non-zero :Scl frequency. - * @retval 0 :Error. - * @note - - */ -/*--------------------------------------------------*/ -uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting) -{ - uint32_t result = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_setting)); -#endif /* #ifdef DEBUG */ - - if (frequency <= 1000000) - { - uint64_t sck, tmp_sck; - uint64_t prsck, tmp_prsck; - uint64_t fscl, tmp_fscl; - uint64_t fx; - uint64_t max_fx, min_fx; - uint64_t low_width,low_width_min; - - sck = tmp_sck = 0; - prsck = tmp_prsck = 1; - fscl = tmp_fscl = 0; - - if(frequency <= 400000) - { - max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */ - min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */ - low_width_min = 1600; - } - else - { - max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */ - min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */ - low_width_min = 675; - } - for (prsck = 1; prsck <= 32; prsck++) - { - fx = ((uint64_t)fsys / prsck); - - if ((fx < max_fx) && (fx >= min_fx)) - { - for (sck = 0; sck <= 7; sck++) - { - low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys; - if(low_width < low_width_min) - { - continue; - } - fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); - - if ((fscl <= frequency) && (fscl > tmp_fscl)) - { - tmp_fscl = fscl; - tmp_sck = sck; - tmp_prsck = (prsck < 32)? prsck: 0; - } - } - } - } - result = (uint32_t)tmp_fscl; - p_setting->sck = (uint32_t)tmp_sck; - p_setting->prsck = (tmp_prsck < 32)? (uint32_t)tmp_prsck: 0; - } - else - { - result = 0; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Slave mode setting. - * @param p_obj :I2C object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2C_slave_init(I2C_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - p_obj->p_instance->OP = I2CxOP_SLAVE_INIT; - p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck); - p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); - p_obj->p_instance->CR2 = I2CxCR2_INIT; - p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); - p_obj->p_instance->IE = 1; -} -#if defined(I2CSxWUP_EN) -/*--------------------------------------------------*/ -/** - * @brief I2C Wakeup Control setting. - * @param p_obj :I2CS object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2CS_init(I2CS_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - p_obj->p_instance->WUPCR1 = (p-obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend); -} - -/*--------------------------------------------------*/ -/** - * @brief Primary Slave Address setting. - * @param p_obj :I2CS object. - * @param addr :Primary Slave Address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - p_obj->p_instance->WUPCR2 = (0x0000000E & adr); -} - -/*--------------------------------------------------*/ -/** - * @brief Secondary Slave Address setting. - * @param p_obj :I2CS object. - * @param addr :Secondary Slave Address. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - p_obj->p_instance->WUPCR3 = (0x0000000E & adr); - p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */ -} -#endif -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/** - * @} - */ /* End of group UTILITIES */ - -/** - * @} - */ /* End of group Example */ - -#endif /* defined(__I2C_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c_api.c deleted file mode 100644 index 4a1bab48336..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_i2c_api.c +++ /dev/null @@ -1,1865 +0,0 @@ -/** - ******************************************************************************* - * @file bsp_i2c.c - * @brief This file provides API functions for BSP I2C driver. - * @version V1.0.0.1 - * $Date:: 2017-10-03 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_i2c_api.h" - -#if defined(__BSP_I2C_H) - -/** - * @addtogroup Example - * @{ - */ - -/** - * @addtogroup UTILITIES - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Macro Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_macro - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_macro */ - -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ - -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define I2C_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define I2C_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ - -/** - * @name timeout - * @brief This timeouts are not based on accurate values, this just guarantee that - the application will not remain stuck if the I2C communication is corrupted. - * @{ - */ -#define I2C_TIMEOUT (100000) /*>! fail safe. */ - -/** - * @} - */ /* End of name timeout */ - -#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ -#define I2C_CH0 (0) /*!< I2C Channel 0. */ -#define I2C_CH1 (1) /*!< I2C Channel 1. */ -#define I2C_CH2 (2) /*!< I2C Channel 2. */ -#define I2C_CH3 (3) /*!< I2C Channel 3. */ -#define I2C_CH4 (4) /*!< I2C Channel 3. */ -#define I2C_CH_NUM (5) /*!< Number of I2C Channel. */ - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_define - * @{ - */ -/*----------------------------------*/ -/** - * @brief Transfer State. -*/ -/*----------------------------------*/ -enum { - I2C_TRANSFER_STATE_IDLE = 0U, /*!< Idle. */ - I2C_TRANSFER_STATE_BUSY /*!< Busy. */ -} TransferState; - -/** - * @} - */ /* End of group UTILITIES_Private_define */ - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_typedef - * @{ - */ - -/*----------------------------------*/ -/** - * @brief For IRQn_Type number definition. -*/ -/*----------------------------------*/ -typedef struct -{ - IRQn_Type i2c; - IRQn_Type al; - IRQn_Type bf; - IRQn_Type na; -} i2c_irq_t; - -/** - * @} - */ /* End of group UTILITIES_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_variables - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UTILITIES_Private_variables */ - -/*------------------------------------------------------------------------------*/ -/* Const Table */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_const - * @{ - */ -/*----------------------------------*/ -/** - * @brief Channel 0 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = -{ - { INTI2C0_IRQn, INTI2C0AL_IRQn, INTI2C0BF_IRQn, INTI2C0NACK_IRQn } -}; - -/*----------------------------------*/ -/** - * @brief Channel 1 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = -{ - { INTI2C1_IRQn, INTI2C1AL_IRQn, INTI2C1BF_IRQn, INTI2C1NACK_IRQn } -}; - -/*----------------------------------*/ -/** - * @brief Channel 2 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = -{ - { INTI2C2_IRQn, INTI2C2AL_IRQn, INTI2C2BF_IRQn, INTI2C2NACK_IRQn } -}; - -/*----------------------------------*/ -/** - * @brief Channel 3 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH3_IRQN_TBL[1] = -{ - { INTI2C3_IRQn, INTI2C3AL_IRQn, INTI2C3BF_IRQn, INTI2C3NACK_IRQn } -}; - -/*----------------------------------*/ -/** - * @brief Channel 4 IRQn_Type number table. -*/ -/*----------------------------------*/ -static const i2c_irq_t I2C_CH4_IRQN_TBL[1] = -{ - { INTI2C4_IRQn, INTI2C4AL_IRQn, INTI2C4BF_IRQn, INTI2C4NACK_IRQn } -}; -/** - * @} - */ /* End of group UTILITIES_Private_const */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Private_functions - * @{ - */ -#ifdef DEBUG -__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn); -__STATIC_INLINE int32_t check_param_address(int32_t address); -#endif -__STATIC_INLINE void enable_irq(uint32_t irqn); -__STATIC_INLINE void disable_irq(uint32_t irqn); -__STATIC_INLINE void clear_irq(uint32_t irqn); -__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl); -__STATIC_INLINE uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn); -__STATIC_INLINE void reset_asynch(_i2c_t *p_obj); -__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj); -static void i2c_irq_handler(_i2c_t *p_obj); -static void i2c_slave_irq_handler(_i2c_t *p_obj); - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Compare the IRQn's parameter. - * @param irqn :I2C IRQn List. - * @retval I2C_PARAM_OK :Available. - * @retval I2C_PARAM_NG :Not Available. - * @note -. - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn) -{ - int32_t result = I2C_PARAM_NG; - - if (irqn == (uint32_t)&I2C_CH0_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - if (irqn == (uint32_t)&I2C_CH1_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - if (irqn == (uint32_t)&I2C_CH2_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - if (irqn == (uint32_t)&I2C_CH3_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - if (irqn == (uint32_t)&I2C_CH4_IRQN_TBL) - { - result = I2C_PARAM_OK; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Compare the Slave address's parameter. - * @param address :Address. - * @retval I2C_PARAM_OK :Available. - * @retval I2C_PARAM_NG :Not Available. - * @note Here, 10bit address has not supported. - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_address(int32_t address) -{ - int32_t result = I2C_PARAM_NG; - - if ((address >= 0) && (address <= 255)) - { - result = I2C_PARAM_OK; - } - return (result); -} -#endif - -/*--------------------------------------------------*/ -/** - * @brief Enable I2C IRQ - * @param irqn :I2C IRQn List. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void enable_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(check_param_irqn(irqn)); -#endif /* #ifdef DEBUG */ - NVIC_EnableIRQ(p_irqn->i2c); -} - -/*--------------------------------------------------*/ -/** - * @brief Disable I2C IRQ - * @param irqn :I2C IRQn List. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void disable_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(check_param_irqn(irqn)); -#endif /* #ifdef DEBUG */ - NVIC_DisableIRQ(p_irqn->i2c); - NVIC_DisableIRQ(p_irqn->al); - NVIC_DisableIRQ(p_irqn->bf); - NVIC_DisableIRQ(p_irqn->na); -} - -/*--------------------------------------------------*/ -/** - * @brief ClearPending I2C IRQ - * @param irqn :I2C IRQn List. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void clear_irq(uint32_t irqn) -{ - i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(check_param_irqn(irqn)); -#endif /* #ifdef DEBUG */ - NVIC_ClearPendingIRQ(p_irqn->i2c); - NVIC_ClearPendingIRQ(p_irqn->al); - NVIC_ClearPendingIRQ(p_irqn->bf); - NVIC_ClearPendingIRQ(p_irqn->na); -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PG2, PG3) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) - { - /* Port G */ - - /* SCL */ - TSB_PG_IE_PG3IE = 0; /* Input :Disable */ - TSB_PG_CR_PG3C = 0; /* Output :Disable */ - TSB_PG_OD_PG3OD = 1; /* OD Control :Open Drain */ - TSB_PG_PUP_PG3UP = 0; /* Pull-up :Disable */ - TSB_PG_PDN_PG3DN = 0; /* Pull-down :Disable */ - TSB_PG_DATA_PG3 = 0; /* Data :0 */ - TSB_PG_FR7_PG3F7 = 1; /* Function :I2C0SCL */ - TSB_PG_IE_PG3IE = 1; /* Input :Enable */ - TSB_PG_CR_PG3C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PG_IE_PG2IE = 0; /* Input :Disable */ - TSB_PG_CR_PG2C = 0; /* Output :Disable */ - TSB_PG_OD_PG2OD = 1; /* OD Control :Open Drain */ - TSB_PG_PUP_PG2UP = 0; /* Pull-up :Disable */ - TSB_PG_PDN_PG2DN = 0; /* Pull-down :Disable */ - TSB_PG_DATA_PG2 = 0; /* Data :0 */ - TSB_PG_FR7_PG2F7 = 1; /* Function :I2C0SDA */ - TSB_PG_IE_PG2IE = 1; /* Input :Enable */ - TSB_PG_CR_PG2C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PF2, PF3) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) - { - /* Port F */ - - /* SCL */ - TSB_PF_IE_PF3IE = 0; /* Input :Disable */ - TSB_PF_CR_PF3C = 0; /* Output :Disable */ - TSB_PF_OD_PF3OD = 1; /* OD Control :Open Drain */ - TSB_PF_PUP_PF3UP = 0; /* Pull-up :Disable */ - TSB_PF_PDN_PF3DN = 0; /* Pull-down :Disable */ - TSB_PF_DATA_PF3 = 0; /* Data :0 */ - TSB_PF_FR7_PF3F7 = 1; /* Function :I2C0SCL */ - TSB_PF_IE_PF3IE = 1; /* Input :Enable */ - TSB_PF_CR_PF3C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PF_IE_PF2IE = 0; /* Input :Disable */ - TSB_PF_CR_PF2C = 0; /* Output :Disable */ - TSB_PF_OD_PF2OD = 1; /* OD Control :Open Drain */ - TSB_PF_PUP_PF2UP = 0; /* Pull-up :Disable */ - TSB_PF_PDN_PF2DN = 0; /* Pull-down :Disable */ - TSB_PF_DATA_PF2 = 0; /* Data :0 */ - TSB_PF_FR7_PF2F7 = 1; /* Function :I2C0SDA */ - TSB_PF_IE_PF2IE = 1; /* Input :Enable */ - TSB_PF_CR_PF2C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PG4, PG5) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) - { - /* Port G */ - - /* SCL */ - TSB_PG_IE_PG5IE = 0; /* Input :Disable */ - TSB_PG_CR_PG5C = 0; /* Output :Disable */ - TSB_PG_OD_PG5OD = 1; /* OD Control :Open Drain */ - TSB_PG_PUP_PG5UP = 0; /* Pull-up :Disable */ - TSB_PG_PDN_PG5DN = 0; /* Pull-down :Disable */ - TSB_PG_DATA_PG5 = 0; /* Data :0 */ - TSB_PG_FR7_PG5F7 = 1; /* Function :I2C0SCL */ - TSB_PG_IE_PG5IE = 1; /* Input :Enable */ - TSB_PG_CR_PG5C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PG_IE_PG4IE = 0; /* Input :Disable */ - TSB_PG_CR_PG4C = 0; /* Output :Disable */ - TSB_PG_OD_PG4OD = 1; /* OD Control :Open Drain */ - TSB_PG_PUP_PG4UP = 0; /* Pull-up :Disable */ - TSB_PG_PDN_PG4DN = 0; /* Pull-down :Disable */ - TSB_PG_DATA_PG4 = 0; /* Data :0 */ - TSB_PG_FR7_PG4F7 = 1; /* Function :I2C0SDA */ - TSB_PG_IE_PG4IE = 1; /* Input :Enable */ - TSB_PG_CR_PG4C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PM0, PM1) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) - { - /* Port M */ - - /* SCL */ - TSB_PJ_IE_PJ6IE = 0; /* Input :Disable */ - TSB_PJ_CR_PJ6C = 0; /* Output :Disable */ - TSB_PJ_OD_PJ6OD = 1; /* OD Control :Open Drain */ - TSB_PJ_PUP_PJ6UP = 0; /* Pull-up :Disable */ - TSB_PJ_PDN_PJ6DN = 0; /* Pull-down :Disable */ - TSB_PJ_DATA_PJ6 = 0; /* Data :0 */ - TSB_PJ_FR7_PJ6F7 = 1; /* Function :I2C3SCL */ - TSB_PJ_IE_PJ6IE = 1; /* Input :Enable */ - TSB_PJ_CR_PJ6C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PJ_IE_PJ7IE = 0; /* Input :Disable */ - TSB_PJ_CR_PJ7C = 0; /* Output :Disable */ - TSB_PJ_OD_PJ7OD = 1; /* OD Control :Open Drain */ - TSB_PJ_PUP_PJ7UP = 0; /* Pull-up :Disable */ - TSB_PJ_PDN_PJ7DN = 0; /* Pull-down :Disable */ - TSB_PJ_DATA_PJ7 = 0; /* Data :0 */ - TSB_PJ_FR7_PJ7F7 = 1; /* Function :I2C3SDA */ - TSB_PJ_IE_PJ7IE = 1; /* Input :Enable */ - TSB_PJ_CR_PJ7C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Port Setting (PM6, PM7) - * @param sda :SDA port. - * @param scl :SCL port. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl) -{ - if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) - { - /* Port M */ - - /* SCL */ - TSB_PJ_IE_PJ2IE = 0; /* Input :Disable */ - TSB_PJ_CR_PJ2C = 0; /* Output :Disable */ - TSB_PJ_OD_PJ2OD = 1; /* OD Control :Open Drain */ - TSB_PJ_PUP_PJ2UP = 0; /* Pull-up :Disable */ - TSB_PJ_PDN_PJ2DN = 0; /* Pull-down :Disable */ - TSB_PJ_DATA_PJ2 = 0; /* Data :0 */ - TSB_PJ_FR7_PJ2F7 = 1; /* Function :I2C3SCL */ - TSB_PJ_IE_PJ2IE = 1; /* Input :Enable */ - TSB_PJ_CR_PJ2C = 1; /* Output :Enable */ - - /* SDA */ - TSB_PJ_IE_PJ3IE = 0; /* Input :Disable */ - TSB_PJ_CR_PJ3C = 0; /* Output :Disable */ - TSB_PJ_OD_PJ3OD = 1; /* OD Control :Open Drain */ - TSB_PJ_PUP_PJ3UP = 0; /* Pull-up :Disable */ - TSB_PJ_PDN_PJ3DN = 0; /* Pull-down :Disable */ - TSB_PJ_DATA_PJ3 = 0; /* Data :0 */ - TSB_PJ_FR7_PJ3F7 = 1; /* Function :I2C3SDA */ - TSB_PJ_IE_PJ3IE = 1; /* Input :Enable */ - TSB_PJ_CR_PJ3C = 1; /* Output :Enable */ - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Setting - * @param ch :I2C Channel. - * @param p_irqn :Destination Address of a I2C IRQn List. - * @retval non-zero :Instance Address. - * @retval zero :Channel not supported. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn) -{ - uint32_t instance = 0; - - switch (ch) - { - case I2C_CH0: - instance = (uint32_t)TSB_I2C0; - *p_irqn = (uint32_t)&I2C_CH0_IRQN_TBL; - break; - - case I2C_CH1: - instance = (uint32_t)TSB_I2C1; - *p_irqn = (uint32_t)&I2C_CH1_IRQN_TBL; - break; - - case I2C_CH2: - instance = (uint32_t)TSB_I2C2; - *p_irqn = (uint32_t)&I2C_CH2_IRQN_TBL; - break; - - case I2C_CH3: - instance = (uint32_t)TSB_I2C3; - *p_irqn = (uint32_t)&I2C_CH3_IRQN_TBL; - break; - - case I2C_CH4: - instance = (uint32_t)TSB_I2C4; - *p_irqn = (uint32_t)&I2C_CH4_IRQN_TBL; - break; - - default: - break; - } - return (instance); -} - -/*--------------------------------------------------*/ -/** - * @brief Reset Asynch Transfer - * @param p_obj :i2c object - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE void reset_asynch(_i2c_t *p_obj) -{ - disable_irq(p_obj->info.irqn); - I2C_disable_interrupt(&p_obj->i2c); -} - -__STATIC_INLINE int32_t I2C_status_arbitration(I2C_t *p_obj) -{ -#ifdef DEBUG - if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) - { - return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); - } - return (0); -#else - return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); -#endif -} -/*--------------------------------------------------*/ -/** - * @brief Waiting i2c status - * @param p_obj :i2c object - * @retval 0 :Success. - * @retval -1 :Failure. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj) -{ - int32_t timeout; - - timeout = I2C_TIMEOUT; - while (!I2C_int_status(&p_obj->i2c)) - { - if (I2C_status_arbitration(&p_obj->i2c)) - { - volatile uint32_t dummy = 0; - dummy = I2C_read_data(&p_obj->i2c); - return (-5); - } - if ((timeout--) == 0) - { - return (-1); - } - } - if (I2C_status_arbitration(&p_obj->i2c)) - { - volatile uint32_t dummy = 0; - dummy = I2C_read_data(&p_obj->i2c); - return (-5); - } - return (0); -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Transfer handler - * @param p_obj :i2c object. - * @retval - - * @note Called by i2c_irq_handler_asynch_t. - */ -/*--------------------------------------------------*/ -static void i2c_irq_handler(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_clear_int_status(&p_obj->i2c); - - if ((!I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) - { - p_obj->info.asynch.event = I2C_EVENT_ERROR; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - else - { - if (I2C_transmitter(&p_obj->i2c)) - { - int32_t start = I2C_restart(&p_obj->i2c); - - if (!I2C_get_ack(&p_obj->i2c)) - { - if (p_obj->tx_buff.pos < p_obj->tx_buff.length) - { - I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); - } - else if (p_obj->rx_buff.length != 0) - { - I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); - } - else - { - if (p_obj->info.asynch.stop) - { - I2C_stop_condition(&p_obj->i2c); - } - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - else - { - if (p_obj->tx_buff.pos < p_obj->tx_buff.length) - { - if (p_obj->tx_buff.pos == 0) - { - p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - else - { - p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - else if (p_obj->rx_buff.length != 0) - { - if (p_obj->tx_buff.pos == 0) - { - p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - else - { - p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - else - { - if (p_obj->info.asynch.stop) - { - I2C_stop_condition(&p_obj->i2c); - } - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - } - else - { - int32_t start = I2C_restart(&p_obj->i2c); - - if (p_obj->rx_buff.pos < p_obj->rx_buff.length) - { - if (!start) - { - p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); - } - } - if (p_obj->rx_buff.pos < p_obj->rx_buff.length) - { - I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1)? 0: 1))); - I2C_write_data(&p_obj->i2c, 0); - } - else - { - if (p_obj->info.asynch.stop) - { - I2C_stop_condition(&p_obj->i2c); - } - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - } - if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) - { - reset_asynch(p_obj); - } -} - -/*--------------------------------------------------*/ -/** - * @brief I2C Transfer handler - * @param p_obj :i2c object. - * @retval - - * @note Called by i2c_slave_irq_handler_asynch_t. - */ -/*--------------------------------------------------*/ -static void i2c_slave_irq_handler(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_clear_int_status(&p_obj->i2c); - - if ((I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) - { - p_obj->info.asynch.event = I2C_EVENT_ERROR; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - else - { - int32_t start = I2C_slave_detected(&p_obj->i2c); - if (start) - { - uint8_t sa = (uint8_t)I2C_read_data(&p_obj->i2c); - } - if (I2C_transmitter(&p_obj->i2c)) - { - if (!I2C_get_ack(&p_obj->i2c)) - { - if (p_obj->tx_buff.pos < p_obj->tx_buff.length) - { - I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); - } - else - { /* dummy, wait nack */ - I2C_write_data(&p_obj->i2c, 0); - } - } - else - { - /* error event not be set */ - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - else - { - if (p_obj->rx_buff.pos < p_obj->rx_buff.length) - { - if (!start) - { - p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); - } - } - if (p_obj->rx_buff.pos < p_obj->rx_buff.length) - { - I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1)? 0: 1))); - I2C_write_data(&p_obj->i2c, 0); - } - else - { - p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - } - } - } - if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) - { - reset_asynch(p_obj); - I2C_slave_init(&p_obj->i2c); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Enable I2C IRQ - * @param p_obj :i2c object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void i2c_enable_irq(_i2c_t *p_obj) -{ - enable_irq(p_obj->info.irqn); -} - -/*--------------------------------------------------*/ -/** - * @brief Disable I2C IRQ - * @param p_obj :i2c object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void i2c_disable_irq(_i2c_t *p_obj) -{ - disable_irq(p_obj->info.irqn); -} - -/** - * @} - */ /* End of group UTILITIES_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UTILITIES_Exported_functions - * @{ - */ - -/*--------------------------------------------------*/ -/** - * @brief Initialize the I2C Driver - * @param p_obj :i2c object. - * @param sda :SDA port. - * @param scl :SCL port. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl) -{ - TXZ_Result result = TXZ_ERROR; - uint32_t instance = 0; - uint32_t irqn = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - /* ch0 */ - if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) - { - set_port_ch0(sda, scl); - instance = set_i2c(I2C_CH0, &irqn); - } - /* ch1 */ - if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) - { - set_port_ch1(sda, scl); - instance = set_i2c(I2C_CH1, &irqn); - } - /* ch2 */ - if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) - { - set_port_ch2(sda, scl); - instance = set_i2c(I2C_CH2, &irqn); - } - /* ch3 */ - if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) - { - set_port_ch3(sda, scl); - instance = set_i2c(I2C_CH3, &irqn); - } - /* ch4 */ - if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) - { - set_port_ch4(sda, scl); - instance = set_i2c(I2C_CH3, &irqn); - } - - if ((instance != 0) && (irqn != 0)) - { - disable_irq(irqn); - clear_irq(irqn); - - /* Set irqn table */ - p_obj->info.irqn = irqn; - - /* Set instance */ - p_obj->i2c.p_instance = (TSB_I2C_TypeDef *)instance; - - /* I2C Reset */ - i2c_reset_t(p_obj); - - /* Set Frequency Default at 100KHz */ - if (i2c_frequency_t(p_obj, 100000) == TXZ_SUCCESS) - { - result = TXZ_SUCCESS; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Reset I2C peripheral - * @param p_obj :i2c object. - * @retval - - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_reset_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - /* Software reset */ - I2C_reset(&p_obj->i2c); -} - -/*--------------------------------------------------*/ -/** - * @brief Configure the I2C frequency - * @param p_obj :i2c object. - * @param hz :frequency in Hz. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz) -{ - TXZ_Result result = TXZ_ERROR; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - if (I2C_port_high(&p_obj->i2c)) - { - uint32_t fval; - - SystemCoreClockUpdate(); - - fval = I2C_get_clock_setting(&p_obj->i2c, (uint32_t)hz, SystemCoreClock, &p_obj->i2c.init.clock); - if (fval != 0) - { - //I2C_init(&p_obj->i2c); - p_obj->info.bus_free = 0; - p_obj->info.start = 0; - p_obj->info.asynch.address = 0; - p_obj->info.asynch.stop = 0; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - p_obj->info.asynch.event = 0; - p_obj->tx_buff.p_buffer = I2C_NULL; - p_obj->tx_buff.length = 0; - p_obj->tx_buff.pos = 0; - p_obj->rx_buff.p_buffer = I2C_NULL; - p_obj->rx_buff.length = 0; - p_obj->rx_buff.pos = 0; - result = TXZ_SUCCESS; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check bus free on the I2C bus. - * @param p_obj :i2c object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - p_obj->info.bus_free = 1; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Creates a start condition on the I2C bus. - * @param p_obj :i2c object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure.(now, not use) - * @note Start condition is not generate yet, after this function returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_start_t(_i2c_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - p_obj->info.start = 1; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Creates a stop condition on the I2C bus. - * @param p_obj :i2c object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Master and blocking function. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_stop_t(_i2c_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - int32_t timeout; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_stop_condition(&p_obj->i2c); - p_obj->info.bus_free = 0; - p_obj->info.start = 0; - - timeout = I2C_TIMEOUT; - while (i2c_active_t(p_obj)) - { - if ((timeout--) == 0) - { - result = TXZ_ERROR; - break; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Blocking reading data - * @param p_obj :i2c object. - * @param address :Slave address(7-bit) and last bit is 0. - * @param p_data :Address of Read data. - * @param length :Number of the bytes to read. - * @param stop :Stop to be generated after the transfer is done. - * @retval Number of read bytes. - * @note Master and blocking function. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) -{ - int32_t result = 0; - int32_t count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_data)); - assert_param(check_param_address(address)); -#endif /* #ifdef DEBUG */ - - if (length > 0) - { - /* Start Condition */ - if (i2c_start_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - result = i2c_byte_write_t(p_obj, (int32_t)((uint32_t)address | 1U)); - if (result == I2C_ACK) - { - /* Read all bytes */ - while (count < length) - { - int32_t data = i2c_byte_read_t(p_obj, ((count < (length - 1))? 0: 1)); - if (data < 0) - { - result = data; - break; - } - p_data[count++] = (uint8_t)data; - } - result = count; - } - else if (result == I2C_ERROR_ARBITRATION) - { - } - else if (result == (-2)) //I2C_ERROR_BUS_BUSY - { - } - else - { - stop = 1; - result = (-1) ;//I2C_ERROR_NO_SLAVE; - } - /* Stop Condition */ - if (stop) - { - if (i2c_stop_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Blocking sending data - * @param p_obj :i2c object. - * @param address :Slave address(7-bit) and last bit is 0. - * @param p_data :Destination address of Write data. - * @param length :Number of the bytes to write. - * @param stop :Stop to be generated after the transfer is done. - * @retval Number of write bytes. - * @note Master and blocking function. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) -{ - int32_t result = 0; - int32_t count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_data)); - assert_param(check_param_address(address)); -#endif /* #ifdef DEBUG */ - - /* Start Condition */ - if (i2c_start_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - result = i2c_byte_write_t(p_obj, address); - if (result == I2C_ACK) - { - /* Write all bytes */ - while (count < length) - { - int32_t data = i2c_byte_write_t(p_obj, (int32_t)p_data[count++]); - if (data < I2C_ACK) - { - result = data; - break; - } - } - if(result >=0){ - result = count; - } - } - else if (result == I2C_ERROR_ARBITRATION) - { - } - else if (result == (-2)) //I2C_ERROR_BUS_BUSY - { - } - else - { - stop = 1; - result = (-1); //I2C_ERROR_NO_SLAVE; - } - /* Stop Condition */ - if (stop) - { - if (i2c_stop_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Read one byte - * @param p_obj :i2c object. - * @param last :last acknowledge. - * @retval The read byte (but -1 is timout error). - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last) -{ - int32_t result; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_clear_int_status(&p_obj->i2c); - I2C_set_ack(&p_obj->i2c, last); - I2C_write_data(&p_obj->i2c, 0); - result = wait_status(p_obj); - if (result < 0) - { - // result = -1; - } - else - { - result = (int32_t)I2C_read_data(&p_obj->i2c); - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Write one byte - * @param p_obj :i2c object. - * @param data :Write data. - * @retval 0 :NACK was received. - * @retval 1 :ACK was received. - * @retval -1 :Timout error. - * @note Macro definition of return values is @ref I2C_ACK. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data) -{ - int32_t result; - int32_t timeout; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - I2C_clear_int_status(&p_obj->i2c); - if (p_obj->info.start == 1) - { - p_obj->info.start = 0; - if (p_obj->info.bus_free == 1) - { - timeout = I2C_TIMEOUT; - while (i2c_active_t(p_obj)) - { - if ((timeout--) == 0) - { - p_obj->info.bus_free = 0; - return (-1); - } - } - } - /* Start Condition */ - I2C_start_condition(&p_obj->i2c, (uint32_t)data); - if ((p_obj->info.bus_free == 1) && (!I2C_master(&p_obj->i2c))) - { - p_obj->i2c.p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); - p_obj->info.bus_free = 0; - if (I2C_status_arbitration(&p_obj->i2c)) - { - return (-5); - } - return (-2); - } - } - else - { - I2C_write_data(&p_obj->i2c, (uint32_t)data); - } - p_obj->info.bus_free = 0; - result = wait_status(p_obj); - if (result < 0) - { - return (result); - } - if (!I2C_get_ack(&p_obj->i2c)) - { - result = 1; - } - else - { - result = 0; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Attempts to determine if the I2C bus is already in use - * @param p_obj :i2c object. - * @retval 0 :Non-active. - * @retval 1 :Active. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -uint8_t i2c_active_t(_i2c_t *p_obj) -{ - uint8_t result; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - if (I2C_status_busy(&p_obj->i2c)) - { - result = 1; - } - else - { - result = 0; - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Start I2C asynchronous transfer - * @param p_obj :i2c object. - * @param p_tx :Buffer of write data. - * @param tx_length :Length of write data. - * @param p_rx :Buffer of read data. - * @param rx_length :Length of read data. - * @param address :Slave address(7-bit) and last bit is 0. - * @param stop :Stop to be generated after the transfer is done. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Master and non-blocking function. - * @note Events of this function will be notified on i2c_irq_handler_asynch_t. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop) -{ - TXZ_Result result = TXZ_ERROR; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(check_param_address(address)); -#endif /* #ifdef DEBUG */ - - if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) - { - if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) - { - reset_asynch(p_obj); - I2C_clear_int_status(&p_obj->i2c); - clear_irq(p_obj->info.irqn); - p_obj->info.asynch.address = (uint32_t)address; - p_obj->info.asynch.event = 0; - p_obj->info.asynch.stop = (uint32_t)stop; - p_obj->tx_buff.p_buffer = p_tx; - p_obj->tx_buff.length = (uint32_t)tx_length; - p_obj->tx_buff.pos = 0; - p_obj->rx_buff.p_buffer = p_rx; - p_obj->rx_buff.length = (uint32_t)rx_length; - p_obj->rx_buff.pos = 0; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; - I2C_enable_interrupt(&p_obj->i2c); - if ((tx_length == 0) && (rx_length != 0)) - { - I2C_start_condition(&p_obj->i2c, (uint32_t)((uint32_t)address | 1U)); - } - else - { - I2C_start_condition(&p_obj->i2c, (uint32_t)address); - } - p_obj->info.bus_free = 0; - p_obj->info.start = 0; - enable_irq(p_obj->info.irqn); - result = TXZ_SUCCESS; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief The asynchronous IRQ handler - * @param p_obj :i2c object. - * @retval zero :Transfer in progress. - * @retval non-zero :Event information. - * @note Macro definition of return values is @ref I2C_Events. - * @attention This function should be implement as INTI2Cx_IRQHandler. - */ -/*--------------------------------------------------*/ -uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - i2c_irq_handler(p_obj); - - return (p_obj->info.asynch.event & I2C_EVENT_ALL); -} - -/*--------------------------------------------------*/ -/** - * @brief Abort asynchronous transfer - * @param p_obj :i2c object. - * @retval - - * @note After error event occurred on i2c_irq_handler_asynch_t, - * @note call this function and clear error status. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_abort_asynch_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - reset_asynch(p_obj); - if (i2c_stop_t(p_obj) == TXZ_SUCCESS) - { - /* no processing */ - } - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - i2c_reset_t(p_obj); - I2C_init(&p_obj->i2c); - clear_irq(p_obj->info.irqn); -} - -/*--------------------------------------------------*/ -/** - * @brief Configure I2C as slave or master. - * @param p_obj :i2c object. - * @param enable_slave :Enable slave mode. - * @retval - - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - disable_irq(p_obj->info.irqn); - - if (enable_slave) - { - I2C_slave_init(&p_obj->i2c); - } - else - { - /* Slave Disable Settings. */ - i2c_reset_t(p_obj); - I2C_init(&p_obj->i2c); - } - p_obj->info.bus_free = 0; - p_obj->info.start = 0; - I2C_clear_int_status(&p_obj->i2c); -} - -/*--------------------------------------------------*/ -/** - * @brief Check to see if the I2C slave has been addressed. - * @param p_obj :i2c object. - * @retval I2C_NO_DATA :The slave has not been addressed. - * @retval I2C_READ_ADDRESSED :Read addresses. - * @retval I2C_WRITE_GENERAL :Write to all slaves(now, not support). - * @retval I2C_WRITE_ADDRESSED :Write addressed. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_slave_receive_t(_i2c_t *p_obj) -{ - int32_t result = I2C_NO_DATA; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - if (I2C_slave_detected(&p_obj->i2c)) - { - uint32_t sa = I2C_read_data(&p_obj->i2c); - - if (!I2C_transmitter(&p_obj->i2c)) - { - result = I2C_WRITE_ADDRESSED; - } - else - { - result = I2C_READ_ADDRESSED; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Blocking reading data. - * @param p_obj :i2c object. - * @param p_data :Destination address of read data. - * @param length :Number of bytes to read. - * @retval Number of read bytes. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) -{ - int32_t count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_data)); -#endif /* #ifdef DEBUG */ - - /* Read all bytes */ - while (count < length) - { - I2C_clear_int_status(&p_obj->i2c); - I2C_set_ack(&p_obj->i2c, ((count < (length - 1))? 0: 1)); - I2C_write_data(&p_obj->i2c, 0); - if (wait_status(p_obj) < 0) - { - break; - } - if (I2C_slave_detected(&p_obj->i2c)) - { - return (count); - } - p_data[count++] = (uint8_t)I2C_read_data(&p_obj->i2c); - } - I2C_slave_init(&p_obj->i2c); - return (count); -} - -/*--------------------------------------------------*/ -/** - * @brief Blocking sending data. - * @param p_obj :i2c object. - * @param p_data :Source address of write data. - * @param length :Number of bytes to write. - * @retval Number of written bytes. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) -{ - int32_t count = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_data)); -#endif /* #ifdef DEBUG */ - - /* Write all bytes */ - while (count < length) - { - I2C_clear_int_status(&p_obj->i2c); - I2C_write_data(&p_obj->i2c, (uint32_t)p_data[count++]); - if (wait_status(p_obj) < 0) - { - break; - } - if (!I2C_get_ack(&p_obj->i2c)) - { - /* continue */ - } - else - { - break; - } - } - I2C_slave_init(&p_obj->i2c); - return (count); -} - -/*--------------------------------------------------*/ -/** - * @brief Configure I2C slave address. - * @param p_obj :i2c object. - * @param address :Address to be set. - * @retval - - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(check_param_address((int32_t)address)); -#endif /* #ifdef DEBUG */ - - I2C_set_address(&p_obj->i2c, address); -} - - -/*--------------------------------------------------*/ -/** - * @brief Start I2C asynchronous transfer - * @param p_obj :i2c object. - * @param p_tx :Buffer of write data. - * @param tx_length :Length of write data. - * @param p_rx :Buffer of read data. - * @param rx_length :Length of read data. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Slave and non-blocking function. - * @note Events of this function will be notified on i2c_slave_irq_handler_asynch_t. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length) -{ - TXZ_Result result = TXZ_ERROR; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) - { - if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) - { - reset_asynch(p_obj); - I2C_clear_int_status(&p_obj->i2c); - clear_irq(p_obj->info.irqn); - p_obj->info.asynch.address = 0; - p_obj->info.asynch.event = 0; - p_obj->info.asynch.stop = 0; - p_obj->tx_buff.p_buffer = p_tx; - p_obj->tx_buff.length = (uint32_t)tx_length; - p_obj->tx_buff.pos = 0; - p_obj->rx_buff.p_buffer = p_rx; - p_obj->rx_buff.length = (uint32_t)rx_length; - p_obj->rx_buff.pos = 0; - p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; - I2C_enable_interrupt(&p_obj->i2c); - enable_irq(p_obj->info.irqn); - result = TXZ_SUCCESS; - } - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief The asynchronous IRQ handler - * @param p_obj :i2c object. - * @retval zero :Transfer in progress. - * @retval non-zero :Event information. - * @note Macro definition of return values is @ref I2C_Events. - * @attention This function should be implement as INTI2Cx_IRQHandler. - */ -/*--------------------------------------------------*/ -uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - i2c_slave_irq_handler(p_obj); - - return (p_obj->info.asynch.event & I2C_EVENT_ALL); -} - -/*--------------------------------------------------*/ -/** - * @brief Abort asynchronous transfer - * @param p_obj :i2c object. - * @retval - - * @note For a non-blocking function. - * @note After error event occurred on i2c_slave_irq_handler_asynch_t, - * @note call this function and clear error status. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void i2c_slave_abort_asynch_t(_i2c_t *p_obj) -{ - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif /* #ifdef DEBUG */ - - reset_asynch(p_obj); - p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; - I2C_slave_init(&p_obj->i2c); - I2C_clear_int_status(&p_obj->i2c); - clear_irq(p_obj->info.irqn); -} - -/** - * @} - */ /* End of group UTILITIES_Exported_functions */ - -/** - * @} - */ /* End of group UTILITIES */ - -/** - * @} - */ /* End of group Example */ - -#endif /* defined(__BSP_I2C_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_t32a.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_t32a.c deleted file mode 100644 index fd4c7507cb0..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_t32a.c +++ /dev/null @@ -1,2034 +0,0 @@ - /** - ******************************************************************************* - * @file txz_t32a.c - * @brief This file provides API functions for T32A driver. - * @version V1.0.0.7 - * $Date:: 2018-03-30 13:56:50 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_t32a.h" - -#if defined(__T32A_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup T32A - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Private_define T32A Private Define - * @{ - */ -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ -/** - * @} - */ /* End of group T32A_Private_typedef */ -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Private_define T32A Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group T32A_Private_define */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Private_typedef T32A Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group T32A_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Member */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup T32A_Private_member T32A Private Member - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group T32A_Private_member */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup T32A_Private_fuctions TSPI Private Fuctions - * @{ - */ -#ifdef DEBUG - __INLINE static int32_t check_param_mode_halt(uint32_t param); - __INLINE static int32_t check_param_mode_mode32(uint32_t param); - __INLINE static int32_t check_param_runx_sftstpx(uint32_t param); - __INLINE static int32_t check_param_runx_sftstax(uint32_t param); - __INLINE static int32_t check_param_runx_runx(uint32_t param); - __INLINE static int32_t check_param_crx_prsclx(uint32_t param); - __INLINE static int32_t check_param_crx_clkx(uint32_t param); - __INLINE static int32_t check_param_crx_wbfx(uint32_t param); - __INLINE static int32_t check_param_crx_updnx(uint32_t param); - __INLINE static int32_t check_param_crx_reldx(uint32_t param); - __INLINE static int32_t check_param_crx_stopx(uint32_t param); - __INLINE static int32_t check_param_crx_startx(uint32_t param); - __INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param); - __INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param); - __INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param); - __INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param); - __INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param); - __INLINE static int32_t check_param_capcrx_capmx1(uint32_t param); - __INLINE static int32_t check_param_capcrx_capmx0(uint32_t param); - __INLINE static int32_t check_param_rgx0_rgx0(uint32_t param); - __INLINE static int32_t check_param_rgx1_rgx1(uint32_t param); - __INLINE static int32_t check_param_reldx_reld(uint32_t param); - __INLINE static int32_t check_param_imx_imsterr(uint32_t param); - __INLINE static int32_t check_param_imx_imufx(uint32_t param); - __INLINE static int32_t check_param_imx_imofx(uint32_t param); - __INLINE static int32_t check_param_imx_imx1(uint32_t param); - __INLINE static int32_t check_param_imx_imx0(uint32_t param); - __INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param); - __INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param); - __INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param); - __INLINE static int32_t check_param_pls_cr_pdn(uint32_t param); - __INLINE static int32_t check_param_pls_cr_pup(uint32_t param); - __INLINE static int32_t check_param_pls_cr_nf(uint32_t param); - __INLINE static int32_t check_param_pls_cr_pdir(uint32_t param); - __INLINE static int32_t check_param_pls_cr_pmode(uint32_t param); -#endif - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the Mode HALT's parameter. - * @param param :Mode HALT's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_HALT - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_mode_halt(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_DBG_HALT_RUN: - case T32A_DBG_HALT_STOP: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Mode mode32's parameter. - * @param param :Mode mode32's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_MODE32 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_mode_mode32(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_MODE_16: - case T32A_MODE_32: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the SW Counter STOP Control's parameter. - * @param param :SW Counter STOP Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_SFTSTPx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_runx_sftstpx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_COUNT_DONT_STOP: - case T32A_COUNT_STOP: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the SW START Control's parameter. - * @param param :SW START Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_SFTSTAx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_runx_sftstax(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_COUNT_DONT_START: - case T32A_COUNT_START: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A RUN Disable/Enable Control's parameter. - * @param param :T32A RUN Disable/Enable Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PRSCLx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_runx_runx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_RUN_DISABLE: - case T32A_RUN_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A PRESCALER Control's parameter. - * @param param :T32A PRESCALER Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PRSCLx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_prsclx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PRSCLx_1: - case T32A_PRSCLx_2: - case T32A_PRSCLx_8: - case T32A_PRSCLx_32: - case T32A_PRSCLx_128: - case T32A_PRSCLx_256: - case T32A_PRSCLx_512: - case T32A_PRSCLx_1024: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A PRESCALER Control's parameter. - * @param param :T32A PRESCALER Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_CLKx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_clkx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_CLKx_PRSCLx: - case T32A_CLKx_INTRG: - case T32A_CLKx_TIM_RISING_EDGE: - case T32A_CLKx_TIM_TRAILING_EDGE: - case T32A_CLKx_EXTTRG_RISING_EDGE: - case T32A_CLKx_EXTTRG_TRAILING_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Double Buffer Disable/Enable Control's parameter. - * @param param :Double Buffer Disable/Enable Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_WBFx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_wbfx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_WBF_DISABLE: - case T32A_WBF_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Up/Down Control's parameter. - * @param param :T32A Counter Up/Down Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_UPDNx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_updnx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_COUNT_UP: - case T32A_COUNT_DOWN: - case T32A_COUNT_UPDOWN: - case T32A_COUNT_PLS: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Reload Control's parameter. - * @param param :T32A Counter Reload Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_RELDx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_reldx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_RELOAD_NON: - case T32A_RELOAD_INTRG: - case T32A_RELOAD_EXTTRG_RISING_EDGE: - case T32A_RELOAD_EXTTRG_TRAILING_EDGE: - case T32A_RELOAD_TIM_RISING_EDGE: - case T32A_RELOAD_TIM_TRAILING_EDGE: - case T32A_RELOAD_SYNC: - case T32A_RELOAD_TREGx: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Stop Control's parameter. - * @param param :T32A Counter Stop Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_STOPx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_stopx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_STOP_NON: - case T32A_STOP_INTRG: - case T32A_STOP_EXTTRG_RISING_EDGE: - case T32A_STOP_EXTTRG_TRAILING_EDGE: - case T32A_STOP_TIM_RISING_EDGE: - case T32A_STOP_TIM_TRAILING_EDGE: - case T32A_STOP_SYNC: - case T32A_STOP_TREGx: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Start Control's parameter. - * @param param :T32A Counter Start Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_STARTx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_crx_startx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_START_NON: - case T32A_START_INTRG: - case T32A_START_EXTTRG_RISING_EDGE: - case T32A_START_EXTTRG_TRAILING_EDGE: - case T32A_START_TIM_RISING_EDGE: - case T32A_START_TIM_TRAILING_EDGE: - case T32A_START_SYNC: - result = PARAM_OK; - break; - case T32A_START_Rsvd: - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control's parameter. - * @param param :T32AxOUTA Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCR_DISABLE: - case T32A_OCR_SET: - case T32A_OCR_CLR: - case T32A_OCR_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter. - * @param param :T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRCAPx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCRCAPx1_DISABLE: - case T32A_OCRCAPx1_SET: - case T32A_OCRCAPx1_CLR: - case T32A_OCRCAPx1_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter. - * @param param :T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRCAPx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCRCAPx0_DISABLE: - case T32A_OCRCAPx0_SET: - case T32A_OCRCAPx0_CLR: - case T32A_OCRCAPx0_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. - * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRCMPx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCRCMPx1_DISABLE: - case T32A_OCRCMPx1_SET: - case T32A_OCRCMPx1_CLR: - case T32A_OCRCMPx1_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. - * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_OCRCMPx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_OCRCMPx0_DISABLE: - case T32A_OCRCMPx0_SET: - case T32A_OCRCMPx0_CLR: - case T32A_OCRCMPx0_INVERSION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Capture Control Register A1's parameter. - * @param param :T32A Capture Control Register A1's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_CAPMx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_CAPMx1_DISABLE: - case T32A_CAPMx1_INTRG: - case T32A_CAPMx1_INx0_RISING_EDGE: - case T32A_CAPMx1_INx0_TRAILING_EDGE: - case T32A_CAPMx1_INx1_RISING_EDGE: - case T32A_CAPMx1_INx1_TRAILING_EDGE: - case T32A_CAPMx1_TIM_RISING_EDGE: - case T32A_CAPMx1_TIM_TRAILING_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Capture Control Register A0's parameter. - * @param param :T32A Capture Control Register A0's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_CAPMx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_CAPMx0_DISABLE: - case T32A_CAPMx0_INTRG: - case T32A_CAPMx0_INx0_RISING_EDGE: - case T32A_CAPMx0_INx0_TRAILING_EDGE: - case T32A_CAPMx0_INx1_RISING_EDGE: - case T32A_CAPMx0_INx1_TRAILING_EDGE: - case T32A_CAPMx0_TIM_RISING_EDGE: - case T32A_CAPMx0_TIM_TRAILING_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Timer Register A0's parameter. - * @param param :T32A Timer Register A0's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_RGx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - if (param <= T32A_RGx0_MASK){ - result = PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Timer Register A1's parameter. - * @param param :T32A Timer Register A1's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_RGx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - if (param <= T32A_RGx1_MASK){ - result = PARAM_OK; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Counter Reload Register A's parameter. - * @param param :T32A Counter Reload Register A's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_RELD - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_reldx_reld(uint32_t param) -{ - int32_t result = PARAM_NG; - - if (param <= T32A_RELDx_MASK){ - result = PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Statuserr Interrupt Request MASK's parameter. - * @param param :T32A Statuserr Interrupt Request MASK's parameter. - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMSTEER - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imsterr(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMSTERR_MASK_NOREQ: - case T32A_IMSTERR_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Overflow Interrupt Request MASK's parameter. - * @param param :T32A Overflow Interrupt Request MASK's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMUFx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imufx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMOFx_MASK_NOREQ: - case T32A_IMOFx_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Overflow Interrupt Request MASK's parameter. - * @param param :T32A Overflow Interrupt Request MASK's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMOFx - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imofx(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMOFx_MASK_NOREQ: - case T32A_IMOFx_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter. - * @param param :T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMx1_MASK_NOREQ: - case T32A_IMx1_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter. - * @param param :T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_IMx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_imx_imx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_IMx0_MASK_NOREQ: - case T32A_IMx0_MASK_REQ: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A DMA Converter1 Request control's parameter. - * @param param :T32A DMA Converter1 Request control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_DMAENx2 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_DMAENx2_DISABLE: - case T32A_DMAENx2_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A DMA InputCapture1 Request control's parameter. - * @param param :T32A DMA InputCapture1 Request control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_DMAENx1 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_DMAENx1_DISABLE: - case T32A_DMAENx1_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A DMA InputCapture0 Request control's parameter. - * @param param :T32A DMA InputCapture0 Request control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_DMAENx0 - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_DMAENx0_DISABLE: - case T32A_DMAENx0_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Pulse Mode Count Down Control's parameter. - * @param param :T32A Pulse Mode Count Down Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PDN - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PDN_NON0: - case T32A_PDN_NON1: - case T32A_PDN_INC0_RISING_EDGE: - case T32A_PDN_INC0_TRAILING_EDGE: - case T32A_PDN_INC1_RISING_EDGE: - case T32A_PDN_INC1_TRAILING_EDGE: - case T32A_PDN_INC0_BOTH_EDGE: - case T32A_PDN_INC1_BOTH_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Pulse Mode Count UP Control's parameter. - * @param param :T32A Pulse Mode Count UP Control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PUP - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_pup(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PUP_NON0: - case T32A_PUP_NON1: - case T32A_PUP_INC0_RISING_EDGE: - case T32A_PUP_INC0_TRAILING_EDGE: - case T32A_PUP_INC1_RISING_EDGE: - case T32A_PUP_INC1_TRAILING_EDGE: - case T32A_PUP_INC0_BOTH_EDGE: - case T32A_PUP_INC1_BOTH_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Noise Filter control's parameter. - * @param param :T32A Noise Filter control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_NF - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_nf(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_NF_NON: - case T32A_NF_2: - case T32A_NF_4: - case T32A_NF_8: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Phase 2 Pulse Direction control's parameter. - * @param param :T32A Phase 2 Pulse Direction control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PDIR - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PDIR_FORWARD: - case T32A_PDIR_BACKWARD: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the T32A Pulse Count Mode control's parameter. - * @param param :T32A Pulse Count Mode control's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref T32A_PMODE - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case T32A_PMODE_PHASE_2: - case T32A_PMODE_PHASE_1: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - - - -#endif -/** - * @} - */ /* End of group T32A_Private_functions */ - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup T32A_Exported_functions - - */ -/*--------------------------------------------------*/ -/** - * @brief Mode Initialize the T32A object. - * @param p_obj :T32A object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_mode_init(t32a_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - check_param_mode_halt(p_obj->init_mode.mode.halt); - check_param_mode_mode32(p_obj->init_mode.mode.mode); -#endif /* DEBUG */ - /* Timer Mode Set */ - p_obj->p_instance->MOD = 0; - p_obj->p_instance->MOD = (p_obj->init_mode.mode.halt | p_obj->init_mode.mode.mode); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Initialize the T32A object. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_timer_init(t32a_t *p_obj,uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - /* Check the parameter of TimerA Mode Set */ - check_param_mode_halt(p_obj->init_mode.mode.halt); - check_param_mode_mode32(p_obj->init_mode.mode.mode); - /* Check the parameter of TimerA Run Control Set */ - check_param_runx_sftstpx(p_obj->init[type].runx.sftstp); - check_param_runx_sftstax(p_obj->init[type].runx.sftsta); - check_param_runx_runx(p_obj->init[type].runx.run); - /* Check the parameter of Counter Register Control Set */ - check_param_crx_prsclx(p_obj->init[type].crx.prscl); - check_param_crx_clkx(p_obj->init[type].crx.clk); - check_param_crx_wbfx(p_obj->init[type].crx.wbf); - check_param_crx_updnx(p_obj->init[type].crx.updn); - check_param_crx_reldx(p_obj->init[type].crx.reld); - check_param_crx_stopx(p_obj->init[type].crx.stop); - check_param_crx_startx(p_obj->init[type].crx.start); - /* Check the parameter of TimerA Output Control Set */ - check_param_outcrx0_ocrx(p_obj->init[type].outcrx0.ocr); - /* Check the parameter of T32AxOUTA Control Set */ - check_param_outcrx1_ocrcapx1(p_obj->init[type].outcrx1.ocrcap1); - check_param_outcrx1_ocrcapx0(p_obj->init[type].outcrx1.ocrcap0); - check_param_outcrx1_ocrcmpx1(p_obj->init[type].outcrx1.ocrcmp1); - check_param_outcrx1_ocrcmpx0(p_obj->init[type].outcrx1.ocrcmp0); - /* Check the parameter of Capture Control Set */ - check_param_capcrx_capmx1(p_obj->init[type].capcrx.capmx1); - check_param_capcrx_capmx0(p_obj->init[type].capcrx.capmx0); - /* Check the parameter of T32A Timer Register 0 Set */ - check_param_rgx0_rgx0(p_obj->init[type].rgx0.rgx0); - /* Check the parameter of T32A Timer Register 1 Set */ - check_param_rgx1_rgx1(p_obj->init[type].rgx1.rgx1); - /* Check the parameter of T32A Counter Reload Register Set */ - check_param_reldx_reld(p_obj->init[type].reldx.reld); - /* Check the parameter of Interrupt mask register Set */ - check_param_imx_imsterr(p_obj->init[type].imx.imsterr); - check_param_imx_imufx(p_obj->init[type].imx.imuf); - check_param_imx_imofx(p_obj->init[type].imx.imof); - check_param_imx_imx1(p_obj->init[type].imx.imx1); - check_param_imx_imx0(p_obj->init[type].imx.imx0); - /* Check the parameter of DMA Request register Set */ - check_param_dma_req_dmaenx2(p_obj->init[type].dma_req.dmaenx2); - check_param_dma_req_dmaenx1(p_obj->init[type].dma_req.dmaenx1); - check_param_dma_req_dmaenx0(p_obj->init[type].dma_req.dmaenx0); -#endif - - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - if(p_obj->init_mode.mode.mode != T32A_MODE_16) { - result = TXZ_ERROR; - return (result); - } - /* TimerA Run Control Disable */ - p_obj->p_instance->RUNA = 0; - /* Counter Register Control Set */ - p_obj->p_instance->CRA = 0; - p_obj->p_instance->CRA = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ - p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start ); - /* TimerA Output Control Set */ - p_obj->p_instance->OUTCRA0 = 0; - p_obj->p_instance->OUTCRA0 = p_obj->init[type].outcrx0.ocr; - /* T32AxOUTA Control Set */ - p_obj->p_instance->OUTCRA1 = 0; - p_obj->p_instance->OUTCRA1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ - p_obj->init[type].outcrx1.ocrcmp0 ); - /* T32A Timer Register A0 Set */ - p_obj->p_instance->RGA0 = 0; - p_obj->p_instance->RGA0 = p_obj->init[type].rgx0.rgx0; - /* T32A Timer Register A1 Set */ - p_obj->p_instance->RGA1 = 0; - p_obj->p_instance->RGA1 = p_obj->init[type].rgx1.rgx1; - /* T32A Counter Reload Register Set */ - p_obj->p_instance->RELDA = 0; - p_obj->p_instance->RELDA = p_obj->init[type].reldx.reld; - /* TimerB Capture Control Set */ - p_obj->p_instance->CAPCRA = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); - /* Interrupt mask register Set */ - p_obj->p_instance->IMA = 0; - p_obj->p_instance->IMA = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ - p_obj->init[type].imx.imx0 ); - /* DMA Request register Set */ - p_obj->p_instance->DMAA = 0; - p_obj->p_instance->DMAA = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 ); - /* TimerA Run Control Set */ - p_obj->p_instance->RUNA = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); - break; - case T32A_TIMERB: - /* Timer B */ - if(p_obj->init_mode.mode.mode != T32A_MODE_16) { - result = TXZ_ERROR; - return (result); - } - /* TimerB Run Control Disable */ - p_obj->p_instance->RUNB = 0; - /* Counter Register Control Set */ - p_obj->p_instance->CRB = 0; - p_obj->p_instance->CRB = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ - p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start ); - /* TimerB Output Control Set */ - p_obj->p_instance->OUTCRB0 = 0; - p_obj->p_instance->OUTCRB0 = p_obj->init[type].outcrx0.ocr; - /* T32AxOUTB Control Set */ - p_obj->p_instance->OUTCRB1 = 0; - p_obj->p_instance->OUTCRB1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ - p_obj->init[type].outcrx1.ocrcmp0 ); - /* T32A Timer Register B0 Set */ - p_obj->p_instance->RGB0 = 0; - p_obj->p_instance->RGB0 = p_obj->init[type].rgx0.rgx0; - /* T32A Timer Register B1 Set */ - p_obj->p_instance->RGB1 = 0; - p_obj->p_instance->RGB1 = p_obj->init[type].rgx1.rgx1; - /* T32A Counter Reload Register Set */ - p_obj->p_instance->RELDB = 0; - p_obj->p_instance->RELDB = p_obj->init[type].reldx.reld; - /* TimerB Capture Control Set */ - p_obj->p_instance->CAPCRB = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); - /* Interrupt mask register Set */ - p_obj->p_instance->IMB = 0; - p_obj->p_instance->IMB = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ - p_obj->init[type].imx.imx0 ); - /* DMA Request register Set */ - p_obj->p_instance->DMAB = 0; - p_obj->p_instance->DMAB = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 ); - /* TimerB Run Control Set */ - p_obj->p_instance->RUNB = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); - break; - case T32A_TIMERC: - /* Timer C */ - if(p_obj->init_mode.mode.mode != T32A_MODE_32) { - result = TXZ_ERROR; - return (result); - } - /* TimerC Run Control Disable */ - p_obj->p_instance->RUNC = 0; - #ifdef DEBUG - /* Pulse Count Control register Set */ - check_param_pls_cr_pdn(p_obj->init[type].pls_cr.pdn); - check_param_pls_cr_pup(p_obj->init[type].pls_cr.pup); - check_param_pls_cr_nf(p_obj->init[type].pls_cr.nf); - check_param_pls_cr_pdir(p_obj->init[type].pls_cr.pdir); - check_param_pls_cr_pmode(p_obj->init[type].pls_cr.pmode); - #endif - /* Counter Register Control Set */ - p_obj->p_instance->CRC = 0; - p_obj->p_instance->CRC = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ - p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start ); - /* TimerC Output Control Set */ - p_obj->p_instance->OUTCRC0 = 0; - p_obj->p_instance->OUTCRC0 = p_obj->init[type].outcrx0.ocr; - /* T32AxOUTC Control Set */ - p_obj->p_instance->OUTCRC1 = 0; - p_obj->p_instance->OUTCRC1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ - p_obj->init[type].outcrx1.ocrcmp0 ); - /* T32A Timer Register C0 Set */ - p_obj->p_instance->RGC0 = 0; - p_obj->p_instance->RGC0 = p_obj->init[type].rgx0.rgx0; - /* T32A Timer Register C1 Set */ - p_obj->p_instance->RGC1 = 0; - p_obj->p_instance->RGC1 = p_obj->init[type].rgx1.rgx1; - /* T32A Counter Reload Register Set */ - p_obj->p_instance->RELDC = 0; - p_obj->p_instance->RELDC = p_obj->init[type].reldx.reld; - /* TimerC Capture Control Set */ - p_obj->p_instance->CAPCRC = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); - /* Interrupt mask register Set */ - p_obj->p_instance->IMC = 0; - p_obj->p_instance->IMC = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ - p_obj->init[type].imx.imx0 ); - /* DMA Request register Set */ - p_obj->p_instance->DMAC = 0; - p_obj->p_instance->DMAC = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 ); - /* Pulse Count Control register Set */ - p_obj->p_instance->PLSCR = 0; - p_obj->p_instance->PLSCR = (p_obj->init[type].pls_cr.pdn | p_obj->init[type].pls_cr.pup | p_obj->init[type].pls_cr.nf | \ - p_obj->init[type].pls_cr.pdir | p_obj->init[type].pls_cr.pmode); - /* TimerC Run Control Set */ - p_obj->p_instance->RUNC = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); - break; - default: - result = TXZ_ERROR; - return (result); - } - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the T32A object. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - /* Disable the selected T32A peripheral */ - p_obj->p_instance->RUNA = T32A_RUN_DISABLE; - break; - case T32A_TIMERB: - /* Timer B */ - /* Disable the selected T32A peripheral */ - p_obj->p_instance->RUNB = T32A_RUN_DISABLE; - break; - case T32A_TIMERC: - /* Timer C */ - /* Disable the selected T32A peripheral */ - p_obj->p_instance->RUNC = T32A_RUN_DISABLE; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Timer Start in interrupt mode. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - if(((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0){ - /* Timer A RUN */ - p_obj->p_instance->RUNA |= T32A_RUN_ENABLE; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - case T32A_TIMERB: - if(((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0){ - /* Timer B RUN */ - p_obj->p_instance->RUNB |= T32A_RUN_ENABLE; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - case T32A_TIMERC: - if(((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0){ - /* Timer C RUN */ - p_obj->p_instance->RUNC |= T32A_RUN_ENABLE; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Timer Stop in interrupt mode. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - /* Timer A Stop */ - p_obj->p_instance->RUNA = T32A_RUN_DISABLE; - break; - case T32A_TIMERB: - /* Timer B Stop */ - p_obj->p_instance->RUNB = T32A_RUN_DISABLE; - break; - case T32A_TIMERC: - /* SW Counter Stop & Timer C Stop */ - p_obj->p_instance->RUNC = T32A_RUN_DISABLE; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Timer Start in interrupt mode. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - if(((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0){ - /* Timer A SW Counter start */ - p_obj->p_instance->RUNA |= T32A_COUNT_START; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - case T32A_TIMERB: - if(((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0){ - /* Timer SW Counter start */ - p_obj->p_instance->RUNB |= T32A_COUNT_START; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - case T32A_TIMERC: - if(((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0){ - /* Timer C SW Counter start */ - p_obj->p_instance->RUNC |= T32A_COUNT_START; - }else{ - result = TXZ_ERROR; - return (result); - } - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Timer Stop in interrupt mode. - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - /* TimerA SW Counter Stop */ - p_obj->p_instance->RUNA = T32A_COUNT_STOP; - break; - case T32A_TIMERB: - /* Timer B SW Counter Stop */ - p_obj->p_instance->RUNB = T32A_COUNT_STOP; - break; - case T32A_TIMERC: - /* Timer C SW Counter Stop */ - p_obj->p_instance->RUNC = T32A_COUNT_STOP; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Timer Register Value Setting - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @param num :T32A Register Number. : Use @ref t32_regnum_t - * @param value :Setting Value. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value) -{ - TXZ_Result result = TXZ_SUCCESS; -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - if(num == T32A_REG0) {p_obj->p_instance->RGA0 = value;} - else if(num == T32A_REG1) {p_obj->p_instance->RGA1 = value;} - else if(num == T32A_RELOAD) {p_obj->p_instance->RELDA = value;} - break; - case T32A_TIMERB: - /* Timer B */ - if(num == T32A_REG0) {p_obj->p_instance->RGB0 = value;} - else if(num == T32A_REG1) {p_obj->p_instance->RGB1 = value;} - else if(num == T32A_RELOAD) {p_obj->p_instance->RELDB = value;} - break; - case T32A_TIMERC: - /* Timer C */ - if(num == T32A_REG0) {p_obj->p_instance->RGC0 = value;} - else if(num == T32A_REG1) {p_obj->p_instance->RGC1 = value;} - else if(num == T32A_RELOAD) {p_obj->p_instance->RELDC = value;} - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Timer Register Value Read - * @param p_obj :T32A object. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @param p_val :Save area for register value. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val) -{ - TXZ_Result result = TXZ_SUCCESS; - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - *p_val = p_obj->p_instance->TMRA; - break; - case T32A_TIMERB: - /* Timer B */ - *p_val = p_obj->p_instance->TMRB; - break; - case T32A_TIMERC: - /* Timer C */ - *p_val = p_obj->p_instance->TMRC; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-4 | - | - | - * | 3 | INTUFA | Under Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | - * | 2 | INTOFA | Over Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | - * | 1 | INTx1 | Match up TimerRegister x1 Intterrupt. Use @ref T32A_INTx1_FLG_MASK. | - * | 0 | INTx0 | Match up TimerRegister x0 Intterrupt. Use @ref T32A_INTx0_FLG_MASK. | - * - * @param p_obj :T32A object. - * @param p_status :Save area for status. - * @param type :T32A Timer Type. : Use @ref t32_type_t - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_status)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Read */ - /*------------------------------*/ - switch (type) - { - case T32A_TIMERA: - /* Timer A */ - *p_status = p_obj->p_instance->STA; - break; - case T32A_TIMERB: - /* Timer B */ - *p_status = p_obj->p_instance->STB; - break; - case T32A_TIMERC: - /* Timer C */ - *p_status = p_obj->p_instance->STC; - break; - default: - result = TXZ_ERROR; - return (result); - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for Timer interrupt. - * @param p_obj :T32A object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void t32a_timer_IRQHandler(t32a_t *p_obj) -{ - uint32_t status_a, status_b, status_c; - /*------------------------------*/ - /* Get Status */ - /*------------------------------*/ - (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); - (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); - (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); - - if(status_a != 0){ - /*------------------------------*/ - /* Call Handler Timer A */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERA].handler_T != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERA].handler_T(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); - } - } - if(status_b != 0){ - /*------------------------------*/ - /* Call Handler Timer B */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERB].handler_T != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERB].handler_T(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); - } - } - if(status_c != 0){ - /*------------------------------*/ - /* Call Handler Timer C */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERC].handler_T != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERC].handler_T(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS); - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Timer Capture0 Handler for Timer Capture0 interrupt. - * @param p_obj :T32A object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void t32a_timer_cap0_IRQHandler(t32a_t *p_obj) -{ - uint32_t status_a, status_b, status_c; - /*------------------------------*/ - /* Get Status */ - /*------------------------------*/ - (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); - (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); - (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); - - if(status_a != 0){ - /*------------------------------*/ - /* Call Handler Timer A */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERA].handler_TC0 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERA].handler_TC0(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); - } - } - if(status_b != 0){ - /*------------------------------*/ - /* Call Handler Timer B */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERB].handler_TC0 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERB].handler_TC0(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); - } - } - if(status_c != 0){ - /*------------------------------*/ - /* Call Handler Timer C */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERC].handler_TC0 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERC].handler_TC0(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS); - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Timer Capture1 Handler for Timer Capture1 interrupt. - * @param p_obj :T32A object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note An initial value of default is set at the - reset status value. If needed, please - rewrite and use an initial value. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -void t32a_timer_cap1_IRQHandler(t32a_t *p_obj) -{ - uint32_t status_a, status_b, status_c; - /*------------------------------*/ - /* Get Status */ - /*------------------------------*/ - (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); - (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); - (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); - - if(status_a != 0){ - /*------------------------------*/ - /* Call Handler Timer A */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERA].handler_TC1 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERA].handler_TC1(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); - } - } - if(status_b != 0){ - /*------------------------------*/ - /* Call Handler Timer B */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERB].handler_TC1 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERB].handler_TC1(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); - } - } - if(status_c != 0){ - /*------------------------------*/ - /* Call Handler Timer C */ - /*------------------------------*/ - if (p_obj->init[T32A_TIMERC].handler_TC1 != T32A_NULL) - { - /* Call the handler with Status Register Value & SUCCESS. */ - p_obj->init[T32A_TIMERC].handler_TC1(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS); - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief Calculate timer value to set timer register. - * @param p_value: time value store pointer. - * @param time: The require period which the uint is us. - * @param prescaler: System Clock Freq - * @param prscl: Select the division for source clock @ref T32A_PRSCLx. - * @retval the value set to Tmrb timer register. - */ -/*--------------------------------------------------*/ -TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl) -{ - TXZ_Result result = TXZ_SUCCESS; - uint64_t denominator; - uint64_t numerator; - uint32_t div; - - /* div */ - switch (prscl) - { - case T32A_PRSCLx_1: - div = 1; - break; - case T32A_PRSCLx_2: - div = 2; - break; - case T32A_PRSCLx_8: - div = 8; - break; - case T32A_PRSCLx_32: - div = 32; - break; - case T32A_PRSCLx_128: - div = 128; - break; - case T32A_PRSCLx_256: - div = 256; - break; - case T32A_PRSCLx_512: - div = 512; - break; - case T32A_PRSCLx_1024: - div = 1024; - break; - default: - div = 1; - break; - } - /*-----------------------------------------------*/ - /* "1"counter (s) = 1 / fs */ - /* "1"counter (s) = 1 / (prescaler / div) */ - /* "1"counter (us) = (10^6) / (prescaler / div) */ - /* "1"counter (us) = ((10^6) * div)/prescaler */ - /* "x"counter (us) = time */ - /*-----------------------------------------------*/ - /* x : time = 1 : ((10^6) * div)/prescaler */ - /*-----------------------------------------------*/ - /* x = time / (((10^6) * div)/prescaler) */ - /* = (prescaler * time) / ((10^6) * div) */ - /*-----------------------------------------------*/ - denominator = (uint64_t)((uint64_t)(prescaler) * (uint64_t)(time)); - numerator = (uint64_t)((uint64_t)(1000000) * (uint64_t)div); - denominator = (uint64_t)(denominator / numerator); - /* result */ - if ((denominator == (uint64_t)(0)) || (denominator > (uint64_t)(0xFFFF))) - { - result = TXZ_ERROR; - } - else - { - *p_value = (uint32_t)denominator; - } - - return (result); -} - -/** - * @} - */ /* End of group T32A_Exported_functions */ - -/** - * @} - */ /* End of group T32A */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__T32A_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_tspi.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_tspi.c deleted file mode 100644 index e8854d75105..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_tspi.c +++ /dev/null @@ -1,2830 +0,0 @@ -/** - ******************************************************************************* - * @file txz_tspi.c - * @brief This file provides API functions for TSPI driver. - * @version V1.0.0.0 - * $Date:: 2018-01-25 17:07:20 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_tspi.h" - -#if defined(__TSPI_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup TSPI - * @{ - */ - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_define TSPI Private Define - * @{ - */ -/** - * @name TSPI NULL Pointer - * @brief Null Pointer for TSPI - * @{ - */ -#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ -/** - * @} - */ /* End of name TSPI NULL Pointer */ - -/** - * @name Parameter Result - * @brief Whether the parameter is specified or not. - * @{ - */ -#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ -#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ -/** - * @} - */ /* End of name Parameter Result */ - -/** - * @name FIFO Max Num. - * @brief Transfer's/Receive's FIFO Max Num. - * @{ - */ -#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ -#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ -/** - * @} - */ /* End of name FIFO Max Num */ - -/** - * @name TSPIxDR_MASK Macro Definition. - * @brief TSPIxDR_MASK Macro Definition. - * @{ - */ -/* DR */ -#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ -#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ -/** - * @} - */ /* End of name TSPIxDR_MASK Macro Definition */ - -/** - * @name TSPI _DATA_LENGTH Macro Definition. - * @brief TSPI DATA LENGTH Macro Definition. - * @{ - */ -#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ -#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ -#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ -#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ -#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ -#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ -#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ -#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ -#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ -#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ -#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ -#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ -#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ -#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ -#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ -#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ -#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ -#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ -#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ -#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ -#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ -#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ -#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ -#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ -#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ -/** - * @} - */ /* End of name TSPI _DATA_LENGTH Macro Definition */ -/** - * @} - */ /* End of group TSPI_Private_typedef */ -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_define TSPI Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group TSPI_Private_define */ -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_typedef TSPI Private Typedef - * @{ - */ -/*----------------------------------*/ -/** - * @brief TSPI mask array. -*/ -/*----------------------------------*/ -static uint32_t mask[32] ={ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - TSPI_DR_8BIT_MASK, - TSPI_DR_9BIT_MASK, - TSPI_DR_10BIT_MASK, - TSPI_DR_11BIT_MASK, - TSPI_DR_12BIT_MASK, - TSPI_DR_13BIT_MASK, - TSPI_DR_14BIT_MASK, - TSPI_DR_15BIT_MASK, - TSPI_DR_16BIT_MASK, - TSPI_DR_17BIT_MASK, - TSPI_DR_18BIT_MASK, - TSPI_DR_19BIT_MASK, - TSPI_DR_20BIT_MASK, - TSPI_DR_21BIT_MASK, - TSPI_DR_22BIT_MASK, - TSPI_DR_23BIT_MASK, - TSPI_DR_24BIT_MASK, - TSPI_DR_25BIT_MASK, - TSPI_DR_26BIT_MASK, - TSPI_DR_27BIT_MASK, - TSPI_DR_28BIT_MASK, - TSPI_DR_29BIT_MASK, - TSPI_DR_30BIT_MASK, - TSPI_DR_31BIT_MASK -}; - -/** - * @} - */ /* End of group TSPI_Private_typedef */ - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup TSPI_Private_fuctions TSPI Private Fuctions - * @{ - */ - -#ifdef DEBUG - __INLINE static int32_t check_param_transmit_enable(uint32_t param); - __INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); - __INLINE static int32_t check_param_transmit_master(uint32_t param); - __INLINE static int32_t check_param_transmit_mode(uint32_t param); - __INLINE static int32_t check_param_transmit_sel_select(uint32_t param); - __INLINE static int32_t check_param_frame_range(uint32_t param); - __INLINE static int32_t check_param_idle_imp(uint32_t param); - __INLINE static int32_t check_param_underrun_imp(uint32_t param); - __INLINE static int32_t check_param_tx_fill_level(uint32_t param); - __INLINE static int32_t check_param_rx_fill_level(uint32_t param); - __INLINE static int32_t check_param_tx_fifo_int(uint32_t param); - __INLINE static int32_t check_param_rx_fifo_int(uint32_t param); - __INLINE static int32_t check_param_err_int(uint32_t param); - __INLINE static int32_t check_param_tx_dma_int(uint32_t param); - __INLINE static int32_t check_param_rx_dma_int(uint32_t param); - __INLINE static int32_t check_param_input_clock(uint32_t param); - __INLINE static int32_t check_param_input_divider(uint32_t param); - __INLINE static int32_t check_param_data_direction(uint32_t param); - __INLINE static int32_t check_param_frame_length(uint32_t param); - __INLINE static int32_t check_param_frame_interval(uint32_t param); - __INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); - __INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); - __INLINE static int32_t check_param_clock_edge_imp(uint32_t param); - __INLINE static int32_t check_param_clock_idle_imp(uint32_t param); - __INLINE static int32_t check_param_min_idle_time(uint32_t param); - __INLINE static int32_t check_param_clock_delay(uint32_t param); - __INLINE static int32_t check_param_negate_delay(uint32_t param); - __INLINE static int32_t check_param_parity_enable(uint32_t param); - __INLINE static int32_t check_param_parity_bit(uint32_t param); -#endif - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Enable's parameter. - * @param param :Transmit Enable's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transmission_Control - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_enable(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TRXE_DISABLE: - case TSPI_TRXE_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Mode's parameter. - * @param param :Transmit Mode's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transmission_Mode - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SPI_MODE: - case TSPI_SIO_MODE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Master/Slave parameter. - * @param param :Transmit Master/Slave parameter (Only support Master mode) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Operation_Select - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_master(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_MASTER_OPEARTION: - case TSPI_SLAVE_OPERATION: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transfer Mode's parameter. - * @param param :Transfer Mode's parameter (not support Two Way) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transfer_Mode - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_mode(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TWO_WAY: - case TSPI_TX_ONLY: - case TSPI_RX_ONLY: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Sel Select's parameter. - * @param param :Transmit Sel Select's parameter (not support Two Way) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_CSSEL_Select - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS0_ENABLE: - case TSPI_TSPIxCS1_ENABLE: - case TSPI_TSPIxCS2_ENABLE: - case TSPI_TSPIxCS3_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Transmit Frame Range's parameter. - * @param param :TransmitFrame Range's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Transfer_Frame_Range - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_range(uint32_t param) - -{ - int32_t result = PARAM_NG; - - if ((TSPI_TRANS_RANGE_SINGLE == param) || (param <= TSPI_TRANS_RANGE_MAX)){ - result = PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the IDLE Output Value's parameter. - * @param param :IDLE Output Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_IDLE_Output_value - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_idle_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TIDLE_Hiz: - case TSPI_TIDLE_LAST_DATA: - case TSPI_TIDLE_LOW: - case TSPI_TIDLE_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Underrun Occur Output Value's parameter. - * @param param :Underrun Occur Output Value's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Underrun_Output_value - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_underrun_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TXDEMP_LOW: - case TSPI_TXDEMP_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Fill Level's parameter. - * @param param :Tx Fill Level's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxFillLevel - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_fill_level(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_FILL_LEVEL_0: - case TSPI_TX_FILL_LEVEL_1: - case TSPI_TX_FILL_LEVEL_2: - case TSPI_TX_FILL_LEVEL_3: - case TSPI_TX_FILL_LEVEL_4: - case TSPI_TX_FILL_LEVEL_5: - case TSPI_TX_FILL_LEVEL_6: - case TSPI_TX_FILL_LEVEL_7: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Fill Level's parameter. - * @param param :Rx Fill Level's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxFillLevel - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_fill_level(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_FILL_LEVEL_0: - case TSPI_RX_FILL_LEVEL_1: - case TSPI_RX_FILL_LEVEL_2: - case TSPI_RX_FILL_LEVEL_3: - case TSPI_RX_FILL_LEVEL_4: - case TSPI_RX_FILL_LEVEL_5: - case TSPI_RX_FILL_LEVEL_6: - case TSPI_RX_FILL_LEVEL_7: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx FIFO Interrpt's parameter. - * @param param :Tx FIFO Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_FIFO_INT_DISABLE: - case TSPI_TX_FIFO_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Interrpt's parameter. - * @param param :Tx Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_INT_DISABLE: - case TSPI_TX_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx FIFO Interrpt's parameter. - * @param param :Rx FIFO Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxFIFOInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_FIFO_INT_DISABLE: - case TSPI_RX_FIFO_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Interrpt's parameter. - * @param param :Rx Interrpt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_INT_DISABLE: - case TSPI_RX_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Error Interrupt's parameter. - * @param param :Error Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ErrorInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_err_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_ERR_INT_DISABLE: - case TSPI_ERR_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx DMA Interrupt's parameter. - * @param param :Tx DMA Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TxDMAInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tx_dma_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TX_DMA_INT_DISABLE: - case TSPI_TX_DMA_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx DMA Interrupt's parameter. - * @param param :Rx DMA Interrupt's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_RxDMAInterrupt - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_rx_dma_int(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_RX_DMA_INT_DISABLE: - case TSPI_RX_DMA_INT_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Input Clock's parameter. - * @param param :Input Clock's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Baudrate_Clock - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_input_clock(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_BR_CLOCK_0: - case TSPI_BR_CLOCK_1: - case TSPI_BR_CLOCK_2: - case TSPI_BR_CLOCK_4: - case TSPI_BR_CLOCK_8: - case TSPI_BR_CLOCK_16: - case TSPI_BR_CLOCK_32: - case TSPI_BR_CLOCK_64: - case TSPI_BR_CLOCK_128: - case TSPI_BR_CLOCK_256: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Baudrate Divider's parameter. - * @param param :Baudrate Divider's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Baudrate_Clock - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_input_divider(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_BR_DIVIDER_16: - case TSPI_BR_DIVIDER_1: - case TSPI_BR_DIVIDER_2: - case TSPI_BR_DIVIDER_3: - case TSPI_BR_DIVIDER_4: - case TSPI_BR_DIVIDER_5: - case TSPI_BR_DIVIDER_6: - case TSPI_BR_DIVIDER_7: - case TSPI_BR_DIVIDER_8: - case TSPI_BR_DIVIDER_9: - case TSPI_BR_DIVIDER_10: - case TSPI_BR_DIVIDER_11: - case TSPI_BR_DIVIDER_12: - case TSPI_BR_DIVIDER_13: - case TSPI_BR_DIVIDER_14: - case TSPI_BR_DIVIDER_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Direction's parameter. - * @param param :Data Direction's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_data_direction(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_DATA_DIRECTION_LSB: - case TSPI_DATA_DIRECTION_MSB: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Length's parameter. - * @param param :Data Length's parameter (Only support 8bit DATA) - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_length(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_DATA_LENGTH_8: - case TSPI_DATA_LENGTH_9: - case TSPI_DATA_LENGTH_10: - case TSPI_DATA_LENGTH_11: - case TSPI_DATA_LENGTH_12: - case TSPI_DATA_LENGTH_13: - case TSPI_DATA_LENGTH_14: - case TSPI_DATA_LENGTH_15: - case TSPI_DATA_LENGTH_16: - case TSPI_DATA_LENGTH_17: - case TSPI_DATA_LENGTH_18: - case TSPI_DATA_LENGTH_19: - case TSPI_DATA_LENGTH_20: - case TSPI_DATA_LENGTH_21: - case TSPI_DATA_LENGTH_22: - case TSPI_DATA_LENGTH_23: - case TSPI_DATA_LENGTH_24: - case TSPI_DATA_LENGTH_25: - case TSPI_DATA_LENGTH_26: - case TSPI_DATA_LENGTH_27: - case TSPI_DATA_LENGTH_28: - case TSPI_DATA_LENGTH_29: - case TSPI_DATA_LENGTH_30: - case TSPI_DATA_LENGTH_31: - case TSPI_DATA_LENGTH_32: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Frame Interval's parameter. - * @param param :Frame Interval's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Frame_Interval_Time - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_frame_interval(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_INTERVAL_TIME_0: - case TSPI_INTERVAL_TIME_1: - case TSPI_INTERVAL_TIME_2: - case TSPI_INTERVAL_TIME_3: - case TSPI_INTERVAL_TIME_4: - case TSPI_INTERVAL_TIME_5: - case TSPI_INTERVAL_TIME_6: - case TSPI_INTERVAL_TIME_7: - case TSPI_INTERVAL_TIME_8: - case TSPI_INTERVAL_TIME_9: - case TSPI_INTERVAL_TIME_10: - case TSPI_INTERVAL_TIME_11: - case TSPI_INTERVAL_TIME_12: - case TSPI_INTERVAL_TIME_13: - case TSPI_INTERVAL_TIME_14: - case TSPI_INTERVAL_TIME_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS3 Polarity's parameter. - * @param param :TTSPIxCS3 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS3_NEGATIVE: - case TSPI_TSPIxCS3_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS2 Polarity's parameter. - * @param param :TTSPIxCS2 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS2_NEGATIVE: - case TSPI_TSPIxCS2_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS1 Polarity's parameter. - * @param param :TTSPIxCS1 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS1_NEGATIVE: - case TSPI_TSPIxCS1_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the TTSPIxCS0 Polarity's parameter. - * @param param :TTSPIxCS0 Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_TSPIxCS0_NEGATIVE: - case TSPI_TSPIxCS0_POSITIVE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock Polarity's parameter. - * @param param :Serial Clock Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_Polarity - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_1ST_EDGE: - case TSPI_SERIAL_CK_2ND_EDGE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock IDLE Polarity's parameter. - * @param param :Serial Clock IDLE Polarity's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_IDLE_LOW: - case TSPI_SERIAL_CK_IDLE_HI: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Minimum IDLE Time's parameter. - * @param param :Minimum IDLE Time's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Minimum_IDLE_Time - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_min_idle_time(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_MIN_IDLE_TIME_1: - case TSPI_MIN_IDLE_TIME_2: - case TSPI_MIN_IDLE_TIME_3: - case TSPI_MIN_IDLE_TIME_4: - case TSPI_MIN_IDLE_TIME_5: - case TSPI_MIN_IDLE_TIME_6: - case TSPI_MIN_IDLE_TIME_7: - case TSPI_MIN_IDLE_TIME_8: - case TSPI_MIN_IDLE_TIME_9: - case TSPI_MIN_IDLE_TIME_10: - case TSPI_MIN_IDLE_TIME_11: - case TSPI_MIN_IDLE_TIME_12: - case TSPI_MIN_IDLE_TIME_13: - case TSPI_MIN_IDLE_TIME_14: - case TSPI_MIN_IDLE_TIME_15: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Serial Clock Delay's parameter. - * @param param :Serial Clock Delay's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Serial_Clock_Delay - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_clock_delay(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_SERIAL_CK_DELAY_1: - case TSPI_SERIAL_CK_DELAY_2: - case TSPI_SERIAL_CK_DELAY_3: - case TSPI_SERIAL_CK_DELAY_4: - case TSPI_SERIAL_CK_DELAY_5: - case TSPI_SERIAL_CK_DELAY_6: - case TSPI_SERIAL_CK_DELAY_7: - case TSPI_SERIAL_CK_DELAY_8: - case TSPI_SERIAL_CK_DELAY_9: - case TSPI_SERIAL_CK_DELAY_10: - case TSPI_SERIAL_CK_DELAY_11: - case TSPI_SERIAL_CK_DELAY_12: - case TSPI_SERIAL_CK_DELAY_13: - case TSPI_SERIAL_CK_DELAY_14: - case TSPI_SERIAL_CK_DELAY_15: - case TSPI_SERIAL_CK_DELAY_16: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Negate Delay's parameter. - * @param param :Negate Delay's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_Negate_Delay - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_negate_delay(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_NEGATE_1: - case TSPI_NEGATE_2: - case TSPI_NEGATE_3: - case TSPI_NEGATE_4: - case TSPI_NEGATE_5: - case TSPI_NEGATE_6: - case TSPI_NEGATE_7: - case TSPI_NEGATE_8: - case TSPI_NEGATE_9: - case TSPI_NEGATE_10: - case TSPI_NEGATE_11: - case TSPI_NEGATE_12: - case TSPI_NEGATE_13: - case TSPI_NEGATE_14: - case TSPI_NEGATE_15: - case TSPI_NEGATE_16: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Enable's parameter. - * @param param :Parity Enable's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_parity_enable(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_PARITY_DISABLE: - case TSPI_PARITY_ENABLE: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Bit's parameter. - * @param param :Parity Bit's parameter - * @retval PARAM_OK :Valid - * @retval PARAM_NG :Invalid - * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__INLINE static int32_t check_param_parity_bit(uint32_t param) -{ - int32_t result = PARAM_NG; - - switch (param) - { - case TSPI_PARITY_BIT_ODD: - case TSPI_PARITY_BIT_EVEN: - result = PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -#endif -/** - * @} - */ /* End of group TSPI_Private_functions */ - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup TSPI_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Initialize the TSPI object. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_init(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - /* Check the parameter of TTSPIxCR1. */ - assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); - assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); - assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); - assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); - assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); - assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); - /* Check the parameter of TTSPIxCR2 */ - assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); - assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); - assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); - assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); - assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); - assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); - assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); - assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); - assert_param(check_param_err_int(p_obj->init.cnt2.interr)); - assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); - assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); - /* Check the parameter of TTSPIxBR */ - assert_param(check_param_input_clock(p_obj->init.brd.brck)); - assert_param(check_param_input_divider(p_obj->init.brd.brs)); - /* Check the parameter of TTSPIxFMTR0 */ - assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); - assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); - assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); - assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); - assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); - assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); - assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); - assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); - assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); - assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); - assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); - assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); - /* Check the parameter of TTSPIxFMTR1 */ - assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); - assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); -#endif - - - /* TSPI Software Reset */ - p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); - p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE);; - - /* Wait for 2 clocks of reset completion */ - __NOP(); - __NOP(); - - /* Enable the selected TSPI peripheral (TSPIE)*/ - p_obj->p_instance->CR0 = TSPI_ENABLE; - - /* Control1 Register1 Set*/ - p_obj->p_instance->CR1 = 0x00001C01U; - p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ - p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims| p_obj->init.cnt1.trgen); - /* Control2 Register Set */ - p_obj->p_instance->CR2 = 0x00E10100U; - p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ - p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe |p_obj->init.cnt2.inttxwe | \ - p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare ); - - /* Control3 Register is FIFO clear, do nothing */ - - /* Baudrate Register Set */ - p_obj->p_instance->BR = 0U; - p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); - - /* Format control0 Register Set */ - p_obj->p_instance->FMTR0 = 0x8800C400U; - p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ - p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ - p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); - - /* Format control1 Register Set*/ - p_obj->p_instance->FMTR1 = 0U; - p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); - - /* not created */ - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the TSPI object. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_deinit(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Disable the selected TSPI peripheral */ - p_obj->p_instance->CR0 = TSPI_DISABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data.. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @param timeout :Timeout duration. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_info is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t err=0; - uint32_t length = 0; - - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - p_obj->errcode = NOERROR; - - /* Check the Transfer Mode setting */ - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - p_obj->errcode = TRANSMITMODEERR; - result = TXZ_ERROR; - return (result); - } - - /* Transmit data check*/ - if((p_info->tx8.p_data == TSPI_NULL ) || (p_info->tx8.num == 0)) - { - p_obj->errcode = DATABUFEMPERR; - result = TXZ_ERROR; - return (result); - } - - /* FIFO Cear */ - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /* Check the Frame length setting */ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); - /* Blocking Communication support frame length 8bit (1 byte) only */ - if (length == (TSPI_DATA_LENGTH_8 >> 24)) { - p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; - }else{ - p_obj->errcode = DATALENGTHERR; - result = TXZ_ERROR; - return (result); - } - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - /* Transmit Data write to D ata Register */ - while (p_info->tx8.num > 0) - { - /* Check the current fill level */ - if(((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) - { - *((__IO uint8_t*)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); - p_info->tx8.num--; - /* check complete transmit */ - if((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) - { - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - else - { - /* Enable TSPI Transmission Control */ - if(p_info->tx8.num==0){ - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - return (result); - } - else { - /* Next transmit data sending */ - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - } - - } - }else{ - p_obj->errcode = FIFOFULLERR; - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - - } - /* check complete transmit */ - while((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) - { - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - /* Check Error Flag */ - if((tspi_get_error(p_obj, &err)) != TXZ_ERROR) - { - if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} - else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} - else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} - }else{ - result = TXZ_ERROR; - return (result); - } - if(p_obj->errcode == NOERROR) { - //p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - return (result); - }else{ - result = TXZ_ERROR; - return (result); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @param timeout :Timeout duration. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_info is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t err=0; - uint32_t length = 0; - uint32_t count = 0; - uint32_t index = 0; -// uint32_t level = 0; - - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - p_obj->errcode = NOERROR; - - /* Check the Transfer Mode setting */ - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { - p_obj->errcode = TRANSMITMODEERR; - result = TXZ_ERROR; - return (result); - } - if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - } - - /* Transmit data check*/ - if((p_info->rx8.p_data == TSPI_NULL ) || (p_info->rx8.num == 0)) - { - result = TXZ_ERROR; - return (result); - } - count = p_info->rx8.num; - - /* Check the Frame length setting */ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - /* Blocking Communication support frame length 8bit (1 byte) only */ - if (length == (TSPI_DATA_LENGTH_8 >> 24)) { - p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; - }else{ - p_obj->errcode = DATALENGTHERR; - result = TXZ_ERROR; - return (result); - } - - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - while (timeout > 0) - { - /* Wait until Receive Complete Flag is set to receive data */ - if((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) - { - while (count > 0) { - /* Check the remain data exist */ - if((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0){ - p_info->rx8.p_data[index] = (*((__IO uint8_t*)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); - count--; - index++; - }else{ - p_obj->errcode = FIFOFULLERR; - timeout--; - if(timeout == 0) { - p_obj->errcode = TIMEOUTERR; - result = TXZ_ERROR; - return (result); - } - } - } - /* Receive Complete Flag is clear */ - p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; - /* FIFO Cear */ - p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - return (result); - } - else {timeout--;} - } - /* Timeout management */ - p_obj->errcode = TIMEOUTERR; - - /* Check Error Flag set */ - if((tspi_get_error(p_obj, &err)) != TXZ_ERROR) - { - if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;} - else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;} - else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;} - }else{ - result = TXZ_ERROR; - return (result); - } - - result = TXZ_ERROR; - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; - p_obj->transmit.info.tx8.num = p_info->tx8.num; - p_obj->transmit.tx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; - p_obj->transmit.info.tx16.num = p_info->tx16.num; - p_obj->transmit.tx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; - p_obj->transmit.info.tx32.num = p_info->tx32.num; - p_obj->transmit.tx_allign = 32; - } - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - /* transmit data length set */ - - /*--- TSPIxSR ---*/ - /* Read FIFO fill level. */ - /* Read current TLVL. */ - __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Empty FIFO Num */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - /*--- TSPIxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - { - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - return (result); -} - - - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - //p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; - p_obj->receive.info.rx8.num = p_info->rx8.num; - p_obj->receive.rx_allign = 8; - - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; - p_obj->receive.info.rx16.num = p_info->rx16.num; - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; - p_obj->receive.info.rx32.num = p_info->rx32.num; - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data DMA. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of transmit data. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; - p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; - p_obj->transmit.info.tx8.num = p_info->tx8.num; - p_obj->transmit.tx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; - p_obj->transmit.info.tx16.num = p_info->tx16.num; - p_obj->transmit.tx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; - p_obj->transmit.info.tx32.num = p_info->tx32.num; - p_obj->transmit.tx_allign = 32; - } - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - /* transmit data length set */ - - /*--- TSPIxSR ---*/ - /* Read FIFO fill level. */ - /* Read current TLVL. */ - __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Empty FIFO Num */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - /*--- TSPIxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - { - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /* Write to DMATE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR2 & TSPI_TX_DMA_INT_ENABLE) != TSPI_TX_DMA_INT_ENABLE) - { - p_obj->p_instance->CR2 |= TSPI_TX_DMA_INT_ENABLE; - } - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data DMA. Non-Blocking Communication. - * @param p_obj :TSPI object. - * @param p_info :The information of receive buffer. - * @retval SUCCESS :Success. - * @retval FAILURE :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t length = 0; - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) - { - /* 8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); - } - else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); - } - else - { - /* 17 - 32 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; - p_obj->receive.info.rx8.num = p_info->rx8.num; - p_obj->receive.rx_allign = 8; - - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; - p_obj->receive.info.rx16.num = p_info->rx16.num; - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; - p_obj->receive.info.rx32.num = p_info->rx32.num; - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /* Write to DMARE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR2 & TSPI_RX_DMA_INT_ENABLE) != TSPI_RX_DMA_INT_ENABLE) - { - p_obj->p_instance->CR2 |= TSPI_RX_DMA_INT_ENABLE; - } - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for transmit. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_irq_handler_transmit(tspi_t *p_obj) -{ - __IO uint32_t status; - - uint32_t length; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current TSPIxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - //p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_TX_FIFO_INT_CLR); - /*------------------------------*/ - /* Data length setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); - /*------------------------------*/ - /* Transmit Status Check */ - /*------------------------------*/ - /* Check the transmit's end flag. */ - if (((status & TSPI_TX_DONE_FLAG ) == TSPI_TX_DONE) || - ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) - { - TXZ_WorkState txDone = TXZ_BUSY; - /* Read FIFO fill level. */ - __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); - tlvl >>= 8; - /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ - if (tlvl > TRANSFER_FIFO_MAX_NUM) - { - tlvl = TRANSFER_FIFO_MAX_NUM; - } - /* Get the empty num in FIFO. */ - { - __IO uint32_t work = tlvl; - tlvl = (TRANSFER_FIFO_MAX_NUM - work); - } - if (tlvl == TRANSFER_FIFO_MAX_NUM) - { - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->transmit.tx_allign = 8; - if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->transmit.tx_allign = 16; - if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - else - { - /* 17 - 32 bit */ - p_obj->transmit.tx_allign = 32; - if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - } - } - if (txDone == TXZ_DONE) - { - /*=== Transmit Done!! ===*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != TSPI_NULL) - { - /* Call the transmit handler with SUCCESS. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); - } - } - else - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /* Only the empty number of FIFO is a transmission data set. */ - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->transmit.tx_allign) - { - case 8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 16: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case 32: - if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - #if 0 - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - #endif - } - } -} -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for receive. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_irq_handler_receive(tspi_t *p_obj) -{ - __IO uint32_t status; - - uint32_t length = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current TSPIxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to RXEND(=1), and RXFF(=1). */ - //p_obj->p_instance->SR = (TSPI_RX_DONE_CLR | TSPI_RX_FIFO_INT_CLR); - /*------------------------------*/ - /* Data length setting */ - /*------------------------------*/ - length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); - if(length == DATA_LENGTH_8) - { - /* 8 bit */ - p_obj->receive.rx_allign = 8; - } - else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) ) - { - /* 9 - 16 bit */ - p_obj->receive.rx_allign = 16; - } - else - { - /* 17 - 32 bit */ - p_obj->receive.rx_allign = 32; - } - /*------------------------------*/ - /* Receive Status Check */ - /*------------------------------*/ - /* Check the receive's end flag. */ - if (((status & TSPI_RX_DONE_FLAG ) == TSPI_RX_DONE) || - ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) - { - /* Read FIFO fill level. */ - __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); - //__IO uint32_t rlvl = 7; - /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ - if (rlvl > RECEIVE_FIFO_MAX_NUM) - { - rlvl = RECEIVE_FIFO_MAX_NUM; - } - /*------------------------------*/ - /* Data Read */ - /*------------------------------*/ - /* Read FIFO data. */ - if (rlvl != 0) - { - uint32_t i; - for (i=0; ireceive.rx_allign) - { - case 8: - *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); - break; - case 16: - *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); - break; - case 32: - *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); - break; - default: - /* no process */ - break; - } - } - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != TSPI_NULL) - { - tspi_receive_t param; - - switch (p_obj->receive.rx_allign) - { - case 8: - param.rx8.p_data = p_obj->receive.info.rx8.p_data; - param.rx8.num = rlvl; - break; - case 16: - param.rx16.p_data = p_obj->receive.info.rx16.p_data; - param.rx16.num = rlvl; - break; - case 32: - param.rx32.p_data = p_obj->receive.info.rx32.p_data; - param.rx32.num = rlvl; - break; - default: - /* no process */ - break; - } - /* Call the receive handler with SUCCESS. */ - p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for error. - * @param p_obj :TSPI object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void tspi_error_irq_handler(tspi_t *p_obj) -{ - __IO uint32_t error; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Error Registar Control */ - /*------------------------------*/ - /* Read current TSPIxERR. */ - error = p_obj->p_instance->ERR; - /* Now, no clear the error flag. */ - /*------------------------------*/ - /* Error Check */ - /*------------------------------*/ - /*--- TSPIxERR ---*/ - /* Check the transmit error. */ - /* TRGERR */ - if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) - { - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != TSPI_NULL) - { - /* Call the transmit handler with FAILURE. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); - } - } - /* Check the receive error. */ - { - TXZ_Result err = TXZ_SUCCESS; - /* UNDERERR */ - if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) - { - err = TXZ_ERROR; - } - /* OVRERR */ - if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) - { - err = TXZ_ERROR; - } - /* PERR */ - if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) - { - err = TXZ_ERROR; - } - if (err == TXZ_ERROR) - { - /*------------------------------*/ - /* Receive Check */ - /*------------------------------*/ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=0). */ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != TSPI_NULL) - { - /* Call the receive handler with FAILURE. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); - } - } - } -} - - -/*--------------------------------------------------*/ -/** - * @brief Data Format setting - * @param p_obj :TSPI object. - * @retval - - * @note When p_obj is NULL, no processing. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_format(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - /* Check the parameter of TTSPIxFMTR0 */ - assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); - assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); - assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); - assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); - assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); - assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); - assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); - assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); - assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); - assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); - assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); - assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); - /* Check the parameter of TTSPIxFMTR1 */ - assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); - assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); -#endif - - - /* Format control1 Register Set*/ - p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); - /* Format control0 Register Set */ - p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ - p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ - p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl ); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | - * | 30-24 | - | - | - * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | - * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | - * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | - * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | - * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | - * | 15-8 | - | - | - * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | - * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | - * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | - * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | - * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | - * - * @param p_obj :TSPI object. - * @param p_status :Save area for status. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_status is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Return TSPI state */ - *p_status = p_obj->p_instance->SR; - if(p_status != TSPI_NULL){ return (result);} - else { - result = TXZ_ERROR; - return (result); - } -} - -/*--------------------------------------------------*/ -/** - * @brief Get error information. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-3 | - | - | - * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | - * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | - * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | - * - * @param p_obj :TSPI object. - * @param p_error :Save area for error. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_error is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - - /* Return TSPI ERROR */ - *p_error = p_obj->p_instance->ERR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Error information clear. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-3 | - | - | - * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | - * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | - * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | - * - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note When p_obj is NULL, "Failure" is returned. - * @note When p_error is NULL, "Failure" is returned. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_error_clear(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - /* Check the parameters */ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); -#endif - p_obj->p_instance->ERR = (TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard transmit. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears transmit's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_discard_transmit(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- TSPIxTRXE ---*/ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- TSPIxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - /*--- TSPIxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - /*--- TSPIxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1). */ - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR ); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard receive. - * @param p_obj :TSPI object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears receive's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result tspi_discard_receive(tspi_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the TSPI_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- TSPIxTRXE ---*/ - p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- TSPIxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); - /*--- TSPIxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); - /*--- TSPIxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ - p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR |TSPI_OVERRUN_ERR | TSPI_PARITY_ERR ); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- TSPIxTRANS ---*/ - /* Write to TRXE(=1). */ - /* Check if the TSPI is already enabled */ - if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) - { - p_obj->p_instance->CR0 |= TSPI_ENABLE; - } - - /* Enable TSPI Transmission Control */ - p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; - - return (result); -} - - -/** - * @} - */ /* End of group TSPI_Exported_functions */ - -/** - * @} - */ /* End of group TSPI */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__TSPI_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_uart.c b/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_uart.c deleted file mode 100644 index 6ef89e65e51..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/Periph_Driver/src/txz_uart.c +++ /dev/null @@ -1,1910 +0,0 @@ -/** - ******************************************************************************* - * @file txz_uart.c - * @brief This file provides API functions for UART driver. - * @version V1.0.0.1 - * $Date:: 2018-04-02 19:31:41 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -#ifdef __cplusplus - extern "C" { -#endif - -/*------------------------------------------------------------------------------*/ -/* Includes */ -/*------------------------------------------------------------------------------*/ -#include "txz_uart_include.h" -#include "txz_uart.h" - -#if defined(__UART_H) -/** - * @addtogroup Periph_Driver - * @{ - */ - -/** - * @addtogroup UART - * @{ - */ -/*------------------------------------------------------------------------------*/ -/* Configuration */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_define UART Private Define - * @{ - */ - -/** - * @defgroup UART_BourateConfig Bourate Setting Configuration - * @brief Bourate Setting Configuration. - * @{ - */ -#define UART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ -#define UART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ -#define UART_CFG_GET_BOUDRATE UART_CFG_GET_BOUDRATE_ENABLE /* Disable/Enable Get Bourate Setting */ - -#define UART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ -#define UART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ -#define UART_CFG_GET_BOUDRATE_TYPE UART_CFG_GET_BOUDRATE_TYPE_ALL - -#define UART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)3) /*!< Error Margin(%). */ -#define UART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ -/** - * @} - */ /* End of group UART_BourateConfig */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Macro Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_define UART Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Enumerated Type Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_define UART Private Define - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_define */ - - -/*------------------------------------------------------------------------------*/ -/* Structure Definition */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_typedef UART Private Typedef - * @{ - */ - -/* no define */ - -/** - * @} - */ /* End of group UART_Private_typedef */ - - -/*------------------------------------------------------------------------------*/ -/* Private Function */ -/*------------------------------------------------------------------------------*/ -/** - * @defgroup UART_Private_fuctions UART Private Fuctions - * @{ - */ -#ifdef DEBUG - __STATIC_INLINE int32_t check_param_noize_filter(uint32_t param); - __STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); - __STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); - __STATIC_INLINE int32_t check_param_data_complemention(uint32_t param); - __STATIC_INLINE int32_t check_param_data_direction(uint32_t param); - __STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); - __STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); - __STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); - __STATIC_INLINE int32_t check_param_data_length(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_int(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_int(uint32_t param); - __STATIC_INLINE int32_t check_param_err_int(uint32_t param); - __STATIC_INLINE int32_t check_param_prescaler(uint32_t param); - __STATIC_INLINE int32_t check_param_division(uint32_t param); - __STATIC_INLINE int32_t check_param_rangeK(uint32_t param); - __STATIC_INLINE int32_t check_param_rangeN(uint32_t param); - __STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); - __STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); -#endif /* #ifdef DEBUG */ -__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level); -__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level); -#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) - static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); -#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ - -#ifdef DEBUG -/*--------------------------------------------------*/ -/** - * @brief Check the Noize Fileter's parameter. - * @param param :Noize fileter's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_NoiseFilter"UART_NOISE_FILTER_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_NOISE_FILTER_NON: - case UART_NOISE_FILTER_2_T0: - case UART_NOISE_FILTER_4_T0: - case UART_NOISE_FILTER_8_T0: - case UART_NOISE_FILTER_2_CLOCK: - case UART_NOISE_FILTER_3_CLOCK: - case UART_NOISE_FILTER_4_CLOCK: - case UART_NOISE_FILTER_5_CLOCK: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the CTS Handshake's parameter. - * @param param :CTS Handshake's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_CTSHandshake"UART_CTS_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_CTS_DISABLE: - case UART_CTS_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the RTS Handshake's parameter. - * @param param :RTS Handshake's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RTSHandshake"UART_RTS_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_RTS_DISABLE: - case UART_RTS_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Complementation's parameter. - * @param param :Data Complementation's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_DataComplementation"UART_DATA_COMPLEMENTION_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_DATA_COMPLEMENTION_DISABLE: - case UART_DATA_COMPLEMENTION_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Direction's parameter. - * @param param :Data Direction's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_DataDirection"UART_DATA_DIRECTION_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_data_direction(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_DATA_DIRECTION_LSB: - case UART_DATA_DIRECTION_MSB: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Stop Bit's parameter. - * @param param :Stop Bit's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_StopBit"UART_STOP_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_STOP_BIT_1: - case UART_STOP_BIT_2: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Bit's parameter. - * @param param :Parity Bit's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_ParityBit"UART_PARITY_BIT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_PARITY_BIT_ODD: - case UART_PARITY_BIT_EVEN: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Parity Enable's parameter. - * @param param :Parity Enable's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_ParityEnable"UART_PARITY_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_PARITY_DISABLE: - case UART_PARITY_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Data Length's parameter. - * @param param :Data Length's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_DataLength"UART_DATA_LENGTH_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_data_length(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_DATA_LENGTH_7: - case UART_DATA_LENGTH_8: - case UART_DATA_LENGTH_9: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Fill Level Range's parameter. - * @param param :Tx Fill Level Range's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - /*--- Now, UART_TX_FILL_RANGE_MIN is 0. ---*/ -#if 0 - if ((UART_TX_FILL_RANGE_MIN <= param) && (param <= UART_TX_FILL_RANGE_MAX)) -#else - if (param <= UART_TX_FILL_RANGE_MAX) -#endif - { - result = UART_PARAM_OK; - } - - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Fill Level's parameter. - * @param param :Rx Fill Level's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - if ((UART_RX_FILL_RANGE_MIN <= param) && (param <= UART_RX_FILL_RANGE_MAX)) - { - result = UART_PARAM_OK; - } - - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx FIFO Interrpt's parameter. - * @param param :Tx FIFO Interrpt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_TxFIFOInterrupt"UART_TX_FIFO_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_TX_FIFO_INT_DISABLE: - case UART_TX_FIFO_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Tx Interrpt's parameter. - * @param param :Tx Interrpt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_TxInterrupt"UART_TX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_TX_INT_DISABLE: - case UART_TX_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx FIFO Interrpt's parameter. - * @param param :Rx FIFO Interrpt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RxFIFOInterrupt"UART_RX_FIFO_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_RX_FIFO_INT_DISABLE: - case UART_RX_FIFO_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Rx Interrpt's parameter. - * @param param :Rx Interrpt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RxInterrupt"UART_RX_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_RX_INT_DISABLE: - case UART_RX_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Error Interrupt's parameter. - * @param param :Error Interrupt's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_ErrorInterrupt"UART_ERR_INT_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_err_int(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_ERR_INT_DISABLE: - case UART_ERR_INT_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Prescaler's parameter. - * @param param :Prescaler's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_Prescaler"UART_PLESCALER_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_prescaler(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_PLESCALER_1: - case UART_PLESCALER_2: - case UART_PLESCALER_4: - case UART_PLESCALER_8: - case UART_PLESCALER_16: - case UART_PLESCALER_32: - case UART_PLESCALER_64: - case UART_PLESCALER_128: - case UART_PLESCALER_256: - case UART_PLESCALER_512: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} -/*--------------------------------------------------*/ -/** - * @brief Check the Division's parameter. - * @param param :Division's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_Division"UART_DIVISION_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_division(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - switch (param) - { - case UART_DIVISION_DISABLE: - case UART_DIVISION_ENABLE: - result = UART_PARAM_OK; - break; - default: - /* no process */ - break; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Range K's parameter. - * @param param :Range K's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RangeK"UART_RANGE_K_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - /*--- Now, UART_RANGE_K_MIN is 0. ---*/ -#if 0 - if ((UART_RANGE_K_MIN <= param) && (param <= UART_RANGE_K_MAX)) -#else - if (param <= UART_RANGE_K_MAX) -#endif - { - result = UART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the Range N's parameter. - * @param param :Range N's parameter - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note Macro definition is @ref UART_RangeN"UART_RANGE_N_xxxx". - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - if ((UART_RANGE_N_MIN <= param) && (param <= UART_RANGE_N_MAX)) - { - result = UART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the num of buff for transmit. - * @param param :Num of buff. - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - if (param != 0) - { - result = UART_PARAM_OK; - } - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Check the num of buff for receive. - * @param param :Num of buff. - * @retval UART_PARAM_OK :Valid - * @retval UART_PARAM_NG :Invalid - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) -{ - int32_t result = UART_PARAM_NG; - - if (param >= 8) - { - result = UART_PARAM_OK; - } - - return (result); -} -#endif /* #ifdef DEBUG */ - -/*--------------------------------------------------*/ -/** - * @brief Convert Tx FIFO fill level to register. - * @param level :Fill Level. - * @retval Register value. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level) -{ - uint32_t result = (level << 12); - - return(result); -} - -/*--------------------------------------------------*/ -/** - * @brief Convert Rx FIFO fill level to register. - * @param level :Fill Level. - * @retval Register value. - * @note - - */ -/*--------------------------------------------------*/ -__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level) -{ - uint32_t result; - - if (level < 8) - { - result = (level << 8); - } - else - { - result = 0; - } - - return(result); -} - -#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) -/*--------------------------------------------------*/ -/** - * @brief Check the within error margin. - * @param boudrate :Boudrate(bps). - * @param clock :Clock(hz). - * @param p_clk :Select Clock Setting. - * @param boudrate :Boudrate(bps). - * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" - * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" - * @param p_range64 :Error range(after fixed point bit shift). - * @retval TXZ_SUCCESS :Within error margin. - * @retval TXZ_ERROR :Without error margin. - * @note For N+(64-K)/64 division. - */ -/*--------------------------------------------------*/ -static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) -{ - TXZ_Result result = TXZ_ERROR; - uint64_t boud64 = 0; - uint64_t tx64 = 0; - uint64_t work64 = 0; - - /* phi Tx */ - uint32_t prescaler = (p_clk->prsel >> 4); - - work64 = (uint64_t)((uint64_t)1 << prescaler); - tx64 = (uint64_t)((uint64_t)clock << (UART_CFG_BOUDRATE_FIXED_POINT_BIT+2)); - tx64 /= work64; - - /* Bourate */ - boud64 = (uint64_t)((uint64_t)boudrate << UART_CFG_BOUDRATE_FIXED_POINT_BIT); - *p_range64 = ((boud64/100)*UART_CFG_BOUDRATE_ERROR_RANGE); - /* BourateX */ - work64 = (uint64_t)((uint64_t)n << 6); - work64 = (uint64_t)(work64 + (64-(uint64_t)k)); - work64 = (tx64 / work64); - if (boud64 >= *p_range64) - { - if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) - { - if( boud64 < work64 ) - { - *p_range64 = (work64 - boud64); - } - else - { - *p_range64 = (boud64 - work64); - } - result = TXZ_SUCCESS; - } - } - - return (result); -} -#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ - -/** - * @} - */ /* End of group UART_Private_functions */ - - -/*------------------------------------------------------------------------------*/ -/* Public Function */ -/*------------------------------------------------------------------------------*/ -/** - * @addtogroup UART_Exported_functions - * @{ - */ -/*--------------------------------------------------*/ -/** - * @brief Initialize the UART object. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_init(uart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(check_param_prescaler(p_obj->init.clock.prsel)); - assert_param(check_param_division(p_obj->init.boudrate.ken)); - assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); - assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); - assert_param(check_param_tx_int(p_obj->init.inttx)); - assert_param(check_param_rx_int(p_obj->init.intrx)); - assert_param(check_param_err_int(p_obj->init.interr)); - assert_param(check_param_tx_fifo_int(p_obj->init.txfifo.inttx)); - assert_param(check_param_tx_fill_level_range(p_obj->init.txfifo.level)); - assert_param(check_param_rx_fifo_int(p_obj->init.rxfifo.intrx)); - assert_param(check_param_rx_fill_level_range(p_obj->init.rxfifo.level)); - assert_param(check_param_noize_filter(p_obj->init.nf)); - assert_param(check_param_cts_handshake(p_obj->init.ctse)); - assert_param(check_param_rts_handshake(p_obj->init.rtse)); - assert_param(check_param_data_complemention(p_obj->init.iv)); - assert_param(check_param_data_direction(p_obj->init.dir)); - assert_param(check_param_stop_bit(p_obj->init.sblen)); - assert_param(check_param_parity_bit(p_obj->init.even)); - assert_param(check_param_parity_enable(p_obj->init.pe)); - assert_param(check_param_data_length(p_obj->init.sm)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* SW Reset */ - /*------------------------------*/ - /*--- UARTxSWRST ---*/ - /* SW Reset initializes UARTxTRANS, UARTxDR, UARTxSR, UARTxERR. */ - /* Wait to "SWRSTF = 0". */ - while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) - { - /* no process */ - } - /* Write to SWRST(=10). */ - p_obj->p_instance->SWRST = UARTxSWRST_SWRST_10; - /* Write to SWRST(=01). */ - p_obj->p_instance->SWRST = UARTxSWRST_SWRST_01; - /* Wait to "SWRSTF = 0". */ - while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) - { - /* no process */ - } - /*------------------------------*/ - /* FIFO Clear */ - /*------------------------------*/ - /*--- UARTxFIFOCLR ---*/ - /* Write to TFCLR(=1), and RFCLR(=1) */ - p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); - /*------------------------------*/ - /* Register Setting */ - /*------------------------------*/ - /*--- UARTxCLK ---*/ - /* Reflecting "p_obj->init.clk" */ - p_obj->p_instance->CLK = (p_obj->init.clock.prsel & UART_UARTxCLK_MASK); - /*--- UARTxBRD ---*/ - /* Reflecting "p_obj->init.brd" */ - /* Be careful, BRK needs to bit shit. */ - { - uint32_t brk = (p_obj->init.boudrate.brk << 16); - p_obj->p_instance->BRD = (p_obj->init.boudrate.ken | brk | p_obj->init.boudrate.brn); - } - /*--- UARTxCR0 ---*/ - /* Reflecting "p_obj->init.cnt0" */ - p_obj->p_instance->CR0 = (p_obj->init.hct | p_obj->init.hcm | - p_obj->init.hcc | p_obj->init.lbc | - p_obj->init.nf | p_obj->init.ctse | - p_obj->init.rtse | p_obj->init.iv | - p_obj->init.dir | p_obj->init.sblen | - p_obj->init.even | p_obj->init.pe | - p_obj->init.sm); - /*--- UARTxCR1 ---*/ - /* Reflecting "p_obj->init.cnt1" */ - /* Fixed: "DMATE=0", "DMARE=0". */ - /* Be careful, "TIL", "RIL" need to bit shit. */ - p_obj->p_instance->CR1 = (convert_tx_fifo_fill_level_to_reg(p_obj->init.txfifo.level) | - convert_rx_fifo_fill_level_to_reg(p_obj->init.rxfifo.level) | - p_obj->init.txfifo.inttx | p_obj->init.inttx | - p_obj->init.rxfifo.intrx | p_obj->init.intrx | - p_obj->init.interr); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Release the UART object. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_deinit(uart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ - p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | - UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); - /*--- UARTxCR1 ---*/ - p_obj->p_instance->CR1 = 0; - /*--- UARTxCR0 ---*/ - p_obj->p_instance->CR0 = 0; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard transmit. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears transmit's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_discard_transmit(uart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t trans = 0; - uint32_t count = 10000000; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Read current UARTxTRANS value. */ - trans = p_obj->p_instance->TRANS; - /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ - p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | - UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- UARTxSR ---*/ - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); - while((p_obj->p_instance->SR & UART_TX_STATE_MASK) == UART_TX_STATE_RUN) - { - if(--count == 0) - { - break; - } - } - /*--- UARTxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to TFCLR(=1). */ - p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR); - /*--- UARTxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to TRGERR(=1). */ - p_obj->p_instance->ERR = (UARTxERR_TRGERR_W_CLEAR); - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /* Return RXE setting to UARTxTRANS */ - p_obj->p_instance->TRANS = (trans & UARTxTRANS_RXE_MASK); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Discard receive. - * @param p_obj :UART object. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note This function clears receive's fifo, end flag and error info. - * @attention This function is not available in interrupt. - * @attention Use after interrupt is disabled. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_discard_receive(uart_t *p_obj) -{ - TXZ_Result result = TXZ_SUCCESS; - uint32_t trans = 0; - uint32_t count = 10000000; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transfer */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Read current UARTxTRANS value. */ - trans = p_obj->p_instance->TRANS; - /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ - p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | - UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); - /*------------------------------*/ - /* Refresh Setting */ - /*------------------------------*/ - /*--- UARTxSR ---*/ - /* Clear the receive's end flag. */ - /* Write to RXEND(=1), and RXFF(=1). */ - p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); - while((p_obj->p_instance->SR & UART_RX_STATE_MASK) == UART_RX_STATE_RUN) - { - if(--count == 0) - { - break; - } - } - /*--- UARTxFIFOCLR ---*/ - /* Clear the transmit's FIFO. */ - /* Write to RFCLR(=1). */ - p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_RFCLR_CLEAR); - /*--- UARTxERR ---*/ - /* Clear the trigger error flag. */ - /* Write to OVRERR(=1), PERR(=1), and FERR(=1), BERR(=1) */ - p_obj->p_instance->ERR = (UARTxERR_OVRERR_W_CLEAR | UARTxERR_PERR_W_CLEAR | - UARTxERR_FERR_W_CLEAR | UARTxERR_BERR_W_CLEAR); - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /* Return TXE setting to UARTxTRANS */ - p_obj->p_instance->TRANS = (trans & (UARTxTRANS_BK_MASK | UARTxTRANS_TXTRG_MASK | UARTxTRANS_TXE_MASK)); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Transmit data. Non-Blocking Communication. - * @param p_obj :UART object. - * @param p_info :The information of transmit data. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Asynchronous Processing. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if (p_obj->init.sm == UART_DATA_LENGTH_9 ) - { - /* 9 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); - assert_param(check_param_tx_buff_num(p_info->tx16.num)); - } - else - { - /* 7/8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); - assert_param(check_param_tx_buff_num(p_info->tx8.num)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - p_obj->transmit.rp = 0; - if (p_obj->init.sm == UART_DATA_LENGTH_9) - { - /* 9 bit */ - p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; - p_obj->transmit.info.tx16.num = p_info->tx16.num; - } - else - { - /* 7/8 bit */ - p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; - p_obj->transmit.info.tx8.num = p_info->tx8.num; - } - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - { - /*--- UARTxSR ---*/ - /* Read FIFO fill level. */ - /* Read current TLVL. */ - uint32_t tlvl = (p_obj->p_instance->SR & UARTxSR_TLVL_MASK); - tlvl >>= 8; - /* FIFO Max = UART_TX_FIFO_MAX */ - if (tlvl > UART_TX_FIFO_MAX) - { - tlvl = UART_TX_FIFO_MAX; - } - /* Empty FIFO Num */ - { - uint32_t work = tlvl; - tlvl = (UART_TX_FIFO_MAX - work); - } - /*--- UARTxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - { - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->init.sm) - { - case UART_DATA_LENGTH_9: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case UART_DATA_LENGTH_8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case UART_DATA_LENGTH_7: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - /*------------------------------*/ - /* Enable Transmit */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to TXE(=1). */ - /* Bitband Access. */ - enable_UARTxTRANS_TXE(p_obj->p_instance); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Receive data. Non-Blocking Communication. - * @param p_obj :UART object. - * @param p_info :The information of receive buffer. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note Asynchronous Processing. - * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref UART_FifoMax) num. - * @attention This function is not available in interrupt. - */ -/*--------------------------------------------------*/ -TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_info)); - /* Check the parameter of transmit. */ - if (p_obj->init.sm == UART_DATA_LENGTH_9 ) - { - /* 9 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); - assert_param(check_param_rx_buff_num(p_info->rx16.num)); - } - else - { - /* 7/8 bit */ - assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); - assert_param(check_param_rx_buff_num(p_info->rx8.num)); - } -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /* Write to RXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_RXE(p_obj->p_instance); - /*------------------------------*/ - /* Information Setting */ - /*------------------------------*/ - if (p_obj->init.sm == UART_DATA_LENGTH_9 ) - { - /* 9 bit */ - p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; - p_obj->receive.info.rx16.num = p_info->rx16.num; - } - else - { - /* 7/8 bit */ - p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; - p_obj->receive.info.rx8.num = p_info->rx8.num; - } - /*------------------------------*/ - /* Enable Receive */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to RXE(=1). */ - /* Bitband Access. */ - enable_UARTxTRANS_RXE(p_obj->p_instance); - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for transmit. - * @param p_obj :UART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void uart_transmit_irq_handler(uart_t *p_obj) -{ - uint32_t trans; - uint32_t status; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current UARTxTRANS */ - trans = p_obj->p_instance->TRANS; - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current UARTxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to TXEND(=1), and TXFF(=1). */ - p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); - /*------------------------------*/ - /* Transmit Status Check */ - /*------------------------------*/ - if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) - { - /*---- UARTxSR ---*/ - /* Check the transmit's end flag. */ - if (((status & UARTxSR_TXEND_MASK) == UARTxSR_TXEND_R_END) || - ((status & UARTxSR_TXFF_MASK) == UARTxSR_TXFF_R_REACHED)) - { - TXZ_WorkState txDone = TXZ_BUSY; - /* Read FIFO fill level. */ - uint32_t tlvl = (status & UARTxSR_TLVL_MASK); - tlvl >>= 8; - /* FIFO Max = UART_TX_FIFO_MAX */ - if (tlvl > UART_TX_FIFO_MAX) - { - tlvl = UART_TX_FIFO_MAX; - } - /* Get the empty num in FIFO. */ - { - uint32_t work = tlvl; - tlvl = (UART_TX_FIFO_MAX - work); - } - if (tlvl == UART_TX_FIFO_MAX) - { - switch (p_obj->init.sm) - { - case UART_DATA_LENGTH_9: - if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - break; - default: - if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) - { - txDone = TXZ_DONE; - } - break; - } - } - if (txDone == TXZ_DONE) - { - /*=== Transmit Done!! ===*/ - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != UART_NULL) - { - /* Call the transmit handler with TXZ_SUCCESS. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); - } - } - else - { - /*=== Transmit Continue ===*/ - /*------------------------------*/ - /* Data Setting */ - /*------------------------------*/ - /*--- UARTxDR ---*/ - /* Only the empty number of FIFO is a transmission data set. */ - uint32_t i = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - /* Set data to FIFO. */ - for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) - { - switch (p_obj->init.sm) - { - case UART_DATA_LENGTH_9: - if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case UART_DATA_LENGTH_8: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - case UART_DATA_LENGTH_7: - if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) - { - p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); - p_obj->transmit.rp += 1; - } - else - { - loopBreak = TXZ_DONE; - } - break; - default: - /* no process */ - break; - } - } - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for receive. - * @param p_obj :UART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void uart_receive_irq_handler(uart_t *p_obj) -{ - uint32_t trans; - uint32_t status; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current UARTxTRANS */ - trans = p_obj->p_instance->TRANS; - /*------------------------------*/ - /* Status Registar Control */ - /*------------------------------*/ - /* Read current UARTxSR. */ - status = p_obj->p_instance->SR; - /* Clear the transmit's end flag. */ - /* Write to RXEND(=1), and RXFF(=1). */ - p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); - /*------------------------------*/ - /* Receive Status Check */ - /*------------------------------*/ - if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) - { - /* Check the receive's end flag. */ - if (((status & UARTxSR_RXEND_MASK) == UARTxSR_RXEND_R_END) || - ((status & UARTxSR_RXFF_MASK) == UARTxSR_RXFF_R_REACHED)) - { - /* Read FIFO fill level. */ - uint32_t rlvl = (status & UARTxSR_RLVL_MASK); - /* FIFO Max = UART_RX_FIFO_MAX */ - if (rlvl > UART_RX_FIFO_MAX) - { - rlvl = UART_RX_FIFO_MAX; - } - /*------------------------------*/ - /* Data Read */ - /*------------------------------*/ - /* Read FIFO data. */ - if (rlvl != 0) - { - uint32_t i; - for (i=0; iinit.sm) - { - case UART_DATA_LENGTH_9: - *(p_obj->receive.info.rx16.p_data + i) = (uint16_t)(p_obj->p_instance->DR & UARTxDR_DR_9BIT_MASK); - break; - case UART_DATA_LENGTH_8: - *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_8BIT_MASK); - break; - case UART_DATA_LENGTH_7: - *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_7BIT_MASK); - break; - default: - /* no process */ - break; - } - } - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != UART_NULL) - { - uart_receive_t param; - - if (p_obj->init.sm == UART_DATA_LENGTH_9) - { - param.rx16.p_data = p_obj->receive.info.rx16.p_data; - param.rx16.num = rlvl; - } - else - { - param.rx8.p_data = p_obj->receive.info.rx8.p_data; - param.rx8.num = rlvl; - } - /* Call the receive handler with TXZ_SUCCESS. */ - p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); - } - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief IRQ Handler for error. - * @param p_obj :UART object. - * @retval - - * @note - - */ -/*--------------------------------------------------*/ -void uart_error_irq_handler(uart_t *p_obj) -{ - uint32_t trans; - uint32_t error; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Trans Registar */ - /*------------------------------*/ - /* Read current UARTxTRANS */ - trans = p_obj->p_instance->TRANS; - /*------------------------------*/ - /* Error Registar Control */ - /*------------------------------*/ - /* Read current UARTxERR. */ - error = p_obj->p_instance->ERR; - /* Now, no clear the error flag. */ - /*------------------------------*/ - /* Error Check */ - /*------------------------------*/ - /*--- UARTxERR ---*/ - /* Check the transmit error. */ - /* TRGERR */ - if ((error & UARTxERR_TRGERR_MASK) == UARTxERR_TRGERR_R_ERR) - { - /*------------------------------*/ - /* Transmit Check */ - /*------------------------------*/ - if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) - { - /*------------------------------*/ - /* Disable Transmit */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to TXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_TXE(p_obj->p_instance); - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->transmit.handler != UART_NULL) - { - /* Call the transmit handler with TXZ_ERROR. */ - p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); - } - } - } - /* Check the receive error. */ - { - TXZ_Result err = TXZ_SUCCESS; - /* OVRERR */ - if ((error & UARTxERR_OVRERR_MASK) == UARTxERR_OVRERR_R_ERR) - { - err = TXZ_ERROR; - } - /* PERR */ - if ((error & UARTxERR_PERR_MASK) == UARTxERR_PERR_R_ERR) - { - err = TXZ_ERROR; - } - /* FERR */ - if ((error & UARTxERR_FERR_MASK) == UARTxERR_FERR_R_ERR) - { - err = TXZ_ERROR; - } - /* BERR */ - if ((error & UARTxERR_BERR_MASK) == UARTxERR_BERR_R_ERR) - { - err = TXZ_ERROR; - } - if (err == TXZ_ERROR) - { - /*------------------------------*/ - /* Receive Check */ - /*------------------------------*/ - if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) - { - /*------------------------------*/ - /* Disable Receive */ - /*------------------------------*/ - /*--- UARTxTRANS ---*/ - /* Write to RXE(=0). */ - /* Bitband Access. */ - disable_UARTxTRANS_RXE(p_obj->p_instance); - /*------------------------------*/ - /* Call Handler */ - /*------------------------------*/ - if (p_obj->receive.handler != UART_NULL) - { - /* Call the receive handler with TXZ_ERROR. */ - p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, UART_NULL); - } - } - } - } -} - -/*--------------------------------------------------*/ -/** - * @brief Get status. - * @details Status bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31 | SUE | Setting Enable Flag. Use @ref UART_SettingEnable. | - * | 30-16 | - | - | - * | 15 | TXRUN | Transmitting State Flag. Use @ref UART_TxState. | - * | 14 | TXEND | Transmitting Done Flag. Use @ref UART_TxDone. | - * | 13 | TXFF | Reach Transmitting Fill Level Flag. Use @ref UART_TxReachFillLevel. | - * | 12 | - | - | - * | 11-8 | TLVL | Current Transmitting FIFO Level. Use @ref UART_TxFifoLevel | - * | 7 | RXRUN | Receive State Flag. Use @ref UART_RxState. | - * | 6 | RXEND | Receive Done Flag. Use @ref UART_RxDone. | - * | 5 | RXFF | Reach Receive Fill Level Flag. Use @ref UART_RxReachFillLevel | - * | 4 | - | - | - * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref UART_RxFifoLevel | - * - * @param p_obj :UART object. - * @param p_status :Save area for status. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_status)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Status Read */ - /*------------------------------*/ - /*--- UARTxSR ---*/ - /* Read current UARTxSR. */ - *p_status = p_obj->p_instance->SR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get error information. - * @details Error bits. - * | Bit | Bit Symbol | Function | - * | :--- | :--- | :--- | - * | 31-5 | - | - | - * | 4 | TRGERR | Transmitting Trigger Error. Use @ref UART_TriggerErr. | - * | 3 | OVRERR | Overrun Error. Use @ref UART_OverrunErr. | - * | 2 | PERR | Parity Error. Use @ref UART_ParityErr. | - * | 1 | FERR | Framing Error. Use @ref UART_FramingErr. | - * | 0 | BERR | Break Error Flag. Use @ref UART_BreakErr. | - * - * @param p_obj :UART object. - * @param p_error :Save area for error. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Failure. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error) -{ - TXZ_Result result = TXZ_SUCCESS; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the UART_NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_obj)); - assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); - assert_param(IS_POINTER_NOT_NULL(p_error)); -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Error Read */ - /*------------------------------*/ - /*--- UARTxERR ---*/ - /* Read current UARTxERR. */ - *p_error = p_obj->p_instance->ERR; - - return (result); -} - -/*--------------------------------------------------*/ -/** - * @brief Get the setting of boudrate. - * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". - * @param p_clk :Select Clock Setting. - * @param boudrate :Boudrate(bps). - * @param p_brd :Save area for Division Setting. - * @retval TXZ_SUCCESS :Success. - * @retval TXZ_ERROR :Not support setting. - * @note - - */ -/*--------------------------------------------------*/ -TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_brd) -{ - TXZ_Result result = TXZ_ERROR; -#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) - uint64_t tx = 0; - uint64_t work = 0; - uint64_t range64 = 0; - - /*------------------------------*/ - /* Parameter Check */ - /*------------------------------*/ -#ifdef DEBUG - /* Check the NULL of address. */ - assert_param(IS_POINTER_NOT_NULL(p_clk)); - assert_param(IS_POINTER_NOT_NULL(p_brd)); - /* Check the parameter of UARTxCLK. */ -#endif /* #ifdef DEBUG */ - /*------------------------------*/ - /* Calculate Division Setting */ - /*------------------------------*/ - if ((clock > 0) && (boudrate > 0)) - { - /*--- phi Tx ---*/ - uint32_t prescaler = (p_clk->prsel >> 4); - - work = (uint64_t)((uint64_t)1 << prescaler); - tx = (uint64_t)((uint64_t)clock << UART_CFG_BOUDRATE_FIXED_POINT_BIT); - tx /= work; - - /*--- N+(64-K)/64 division ---*/ - { - uint8_t k = 0; - TXZ_WorkState loopBreak = TXZ_BUSY; - - work = ((uint64_t)boudrate); - tx /= work; - tx >>= 4; - for (k=UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) - { - work = tx + (uint64_t)k; - if (work >= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT)) - { - work -= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT); - work >>= UART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ - if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) - { - uint64_t workRange = 0; - - /* Verification */ - if (verification_boudrate64(clock, p_clk, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) - { -#if (UART_CFG_GET_BOUDRATE_TYPE == UART_CFG_GET_BOUDRATE_TYPE_ALL) - /* Compare the previous range. */ - if (result == TXZ_SUCCESS) - { - if (range64 > workRange) - { - p_brd->ken = UART_DIVISION_ENABLE; - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - range64 = workRange; - } - } - else - { - p_brd->ken = UART_DIVISION_ENABLE; - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - range64 = workRange; - } - result = TXZ_SUCCESS; -#else - /* Finish!! */ - if (result == TXZ_SUCCESS) - { - if (range64 > workRange) - { - p_brd->ken = UART_DIVISION_ENABLE; - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - } - } - else - { - p_brd->ken = UART_DIVISION_ENABLE; - p_brd->brk = (uint32_t)k; - p_brd->brn = (uint32_t)work; - } - result = TXZ_SUCCESS; - loopBreak = TXZ_DONE; -#endif - } - } - } - } - } - } -#endif /* (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ - - return (result); -} - -/** - * @} - */ /* End of group UART_Exported_functions */ - -/** - * @} - */ /* End of group UART */ - -/** - * @} - */ /* End of group Periph_Driver */ - -#endif /* defined(__UART_H) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/PeripheralNames.h b/targets/TARGET_TT/TARGET_TT_M4G9/PeripheralNames.h deleted file mode 100644 index ecef2da7544..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/PeripheralNames.h +++ /dev/null @@ -1,187 +0,0 @@ -/* mbed Microcontroller Library -* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved -* SPDX-License-Identifier: Apache-2.0 -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SERIAL_0 = 0, - SERIAL_1, - SERIAL_2, - SERIAL_3, - SERIAL_4, - SERIAL_5, - SERIAL_6, - SERIAL_7, - INVALID_SERIAL = (int)NC -} UARTName; - -typedef enum { - DAC_0 = 0, - DAC_1, - INVALID_DAC = (int)NC -} DACName; - -typedef enum { - PWM_0 = 0, - PWM_1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11, - PWM_12, - INVALID_PWM = (int)NC -} PWMName; - -typedef enum { - ADC_A0, - ADC_A1, - ADC_A2, - ADC_A3, - ADC_A4, - ADC_A5, - ADC_A6, - ADC_A7, - ADC_A8, - ADC_A9, - ADC_A10, - ADC_A11, - ADC_A12, - ADC_A13, - ADC_A14, - ADC_A15, - ADC_A16, - ADC_A17, - ADC_A18, - ADC_A19, - ADC_A20, - ADC_A21, - ADC_A22, - ADC_A23, - INVALID_ADC = (int)NC -} ADCName; - -typedef enum { - I2C_0 = 0, - I2C_1, - I2C_2, - I2C_3, - I2C_4, - INVALID_I2C = (int)NC -} I2CName; - -typedef enum { - SPI_0 = 0, - SPI_1, - SPI_2, - SPI_3, - SPI_4, - SPI_5, - INVALID_SPI = (int)NC -} SPIName; - -typedef enum { - GPIO_IRQ_0 = 0, - GPIO_IRQ_1 = 1, - GPIO_IRQ_2 = 2, - GPIO_IRQ_3 = 3, - GPIO_IRQ_4 = 4, - GPIO_IRQ_5 = 5, - GPIO_IRQ_6 = 6, - GPIO_IRQ_7 = 7, - GPIO_IRQ_8 = 8, - GPIO_IRQ_9 = 9, - GPIO_IRQ_A = 10, - GPIO_IRQ_B = 11, - GPIO_IRQ_C = 12, - GPIO_IRQ_D = 13, - GPIO_IRQ_E = 14, - GPIO_IRQ_F = 15, - INVALID_GPIO_IRQ = (int)NC -} GPIO_IRQName; - -// DAP UART -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -#define SERIAL_TX PU0 -#define SERIAL_RX PU1 - -#define STDIO_UART SERIAL_4 - -// TxD RxD -#define MBED_UART0 PE3, PE2 -#define MBED_UART1 PH1, PH0 -#define MBED_UART2 PG1, PG0 -#define MBED_UART3 PU7, PU6 -#define MBED_UART4 PM1, PM0 -#define MBED_UART5 PJ1, PJ0 -#define MBED_UART6 PG4, PG5 -#define MBED_UART7 PJ6, PJ7 -#define MBED_UARTUSB USBTX, USBRX - -// SDA SCK -#define MBED_I2C0 PG2, PG3 -#define MBED_I2C1 PF2, PF3 -#define MBED_I2C2 PG4, PG5 -#define MBED_I2C3 PJ6, PJ7 -#define MBED_I2C4 PJ3, PJ2 - -// MOSI, MISO, SCLK SS -#define MBED_SPI0 PA3, PA2, PA1, PA0 -#define MBED_SPI1 PL3, PL2, PL1, PL0 -#define MBED_SPI2 PA4, PA5, PA6, PA7 -#define MBED_SPI3 PK4, PK5, PK6, PK7 -#define MBED_SPI4 PD3, PD2, PD1, PD0 -#define MBED_SPI5 PM0, PM1, PM2, PM3 - -#define MBED_ANALOGIN0 A0 -#define MBED_ANALOGIN1 A1 -#define MBED_ANALOGIN2 A2 -#define MBED_ANALOGIN3 A3 -#define MBED_ANALOGIN4 A4 -#define MBED_ANALOGIN5 A5 - -#define MBED_PWMOUT0 PA5 -#define MBED_PWMOUT1 PB2 -#define MBED_PWMOUT2 PB4 -#define MBED_PWMOUT3 PD2 -#define MBED_PWMOUT4 PD4 -#define MBED_PWMOUT5 PE1 -#define MBED_PWMOUT6 PE6 -#define MBED_PWMOUT7 PC2 -#define MBED_PWMOUT8 PL6 -#define MBED_PWMOUT9 PC4 -#define MBED_PWMOUT10 PM2 -#define MBED_PWMOUT11 PU0 -#define MBED_PWMOUT12 PU6 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h b/targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h deleted file mode 100644 index 28b0b37b20d..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/PinNames.h +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF) -#define PIN_POS(X) ((uint32_t)(X) & 0x7) - -// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction -#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) -#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) -#define PIN_DIR(X) ((X) & 0xffff) - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - PIN_INOUT -} PinDirection; - -typedef enum { - // TMPM4G9 Pin Names - PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, - PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, - PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, - PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, - PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, - PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, - PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, PN6, PN7, - PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, - PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, - PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, - PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, PU6, PU7, - PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, - PW0 = 18 << 3, PW1, PW2, PW3, PW4, PW5, PW6, PW7, - PY0 = 19 << 3, PY1, PY2, PY3, PY4, - - // Other mbed Pin Names - LED0 = PE4, - LED1 = PE5, - LED2 = PE6, - LED3 = PE7, - - // External data bus Pin Names - D0 = PJ0, - D1 = PJ1, - D2 = PF4, - D3 = PB2, - D4 = PF5, - D5 = PB4, - D6 = PC2, - D7 = PF6, - D8 = PA4, - D9 = PC4, - D10 = PA6, - D11 = PA3, - D12 = PA2, - D13 = PA1, - D14 = PG2, - D15 = PG3, - - // Analogue out pins - A0 = PN0, - A1 = PN1, - A2 = PN2, - A3 = PN3, - A4 = PN4, - A5 = PN5, - - // USB2_UART - USBTX = PU0, - USBRX = PU1, - MBEDIF_TXD = USBTX, - MBEDIF_RXD = USBRX, - - MBED_CONF_APP_UART0_TX = PE3, - MBED_CONF_APP_UART0_RX = PE2, - - // Switches - SW1 = (int)0xFFFFFFFF, //Reset Button - SW2 = PL4, //Push button S2 - SW3 = PM0, //DIP switch J7_1 - SW4 = PM1, //DIP switch J7_2 - USER_BUTTON = PL4, - - // I2C pins - SDA = PG2, - SCL = PG3, - I2C_SDA = SDA, - I2C_SCL = SCL, - - // SPI pins - SPI_MOSI = D11, - SPI_MISO = D12, - SPI_SCK = D13, - SPI_CS = D10, - - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 0, - PullDown, - PullNone, - OpenDrain, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/PortNames.h b/targets/TARGET_TT/TARGET_TT_M4G9/PortNames.h deleted file mode 100644 index 3a3a0bda28c..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/PortNames.h +++ /dev/null @@ -1,50 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB, - PortC, - PortD, - PortE, - PortF, - PortG, - PortH, - PortJ, - PortK, - PortL, - PortM, - PortN, - PortP, - PortR, - PortT, - PortU, - PortV, - PortW, - PortY -} PortName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/analogin_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/analogin_api.c deleted file mode 100644 index 35a3f5fd79d..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/analogin_api.c +++ /dev/null @@ -1,138 +0,0 @@ -/* mbed Microcontroller Library -* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved -* SPDX-License-Identifier: Apache-2.0 -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ -#include "analogin_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" -#include "mbed_wait_api.h" -#include "mbed_error.h" -#include "adc_include.h" - -#define ADC_12BIT_RANGE 0xFFF -#define CONVERSION_FLAG 0x4 - -static const PinMap PinMap_ADC[] = { - {PN0, ADC_A0, PIN_DATA(0, 0)}, - {PN1, ADC_A1, PIN_DATA(0, 0)}, - {PN2, ADC_A2, PIN_DATA(0, 0)}, - {PN3, ADC_A3, PIN_DATA(0, 0)}, - {PN4, ADC_A4, PIN_DATA(0, 0)}, - {PN5, ADC_A5, PIN_DATA(0, 0)}, - {PN6, ADC_A6, PIN_DATA(0, 0)}, - {PN7, ADC_A7, PIN_DATA(0, 0)}, - {PP0, ADC_A8, PIN_DATA(0, 0)}, - {PP1, ADC_A9, PIN_DATA(0, 0)}, - {PP2, ADC_A10, PIN_DATA(0, 0)}, - {PP3, ADC_A11, PIN_DATA(0, 0)}, - {PP4, ADC_A12, PIN_DATA(0, 0)}, - {PP5, ADC_A13, PIN_DATA(0, 0)}, - {PP6, ADC_A14, PIN_DATA(0, 0)}, - {PP7, ADC_A15, PIN_DATA(0, 0)}, - {PR0, ADC_A16, PIN_DATA(0, 0)}, - {PR1, ADC_A17, PIN_DATA(0, 0)}, - {PR2, ADC_A18, PIN_DATA(0, 0)}, - {PR3, ADC_A19, PIN_DATA(0, 0)}, - {PR4, ADC_A20, PIN_DATA(0, 0)}, - {PR5, ADC_A21, PIN_DATA(0, 0)}, - {PR6, ADC_A22, PIN_DATA(0, 0)}, - {PR7, ADC_A23, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Check that pin belong to ADC module - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Enable ADC clock supply - TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE; - TSB_CG_SPCLKEN_ADCKEN = TXZ_ENABLE; - TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE; - - // Enable clock for GPIO - if(obj->adc <= ADC_A7) { - TSB_CG_FSYSMENB_IPMENB14 = TXZ_ENABLE; - } else if(obj->adc <= ADC_A15) { - TSB_CG_FSYSMENB_IPMENB15 = TXZ_ENABLE; - } else { - TSB_CG_FSYSMENB_IPMENB16 = TXZ_ENABLE; - } - - // Set pin function as ADC - pinmap_pinout(pin, PinMap_ADC); - - // Initialize - obj->p_adc.p_instance = TSB_ADA; - obj->p_adc.init.clk.exaz0 = ADC_SAMPLING_PERIOD0_XN; - obj->p_adc.init.clk.exaz1 = ADC_SAMPLING_PERIOD1_XN; - obj->p_adc.init.clk.vadcld = ADC_SCLK_1; - obj->p_adc.init.mod1 = ADC_MOD1_SCLK_3; - obj->p_adc.init.mod2 = ADC_MOD2_TMPM4G9; - obj->p_adc.handler.single = NULL; - obj->p_adc.handler.continuity = NULL; - obj->p_adc.handler.trigger = NULL; - obj->p_adc.handler.highpriority = NULL; - - if (adc_init(&obj->p_adc) != TXZ_SUCCESS) { - error("Failed : ADC Initialization"); - } - - // ADC channel setting - obj->param.interrupt = ADC_INT_DISABLE; - obj->param.type = ADC_CONVERSION_SGL; - obj->param.ain = obj->adc; - - if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) { - error("Failed : ADC channel setting"); - } -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint32_t adc_result = 0; - - // Assert that ADC channel is valid - MBED_ASSERT(obj->adc != (ADCName)NC); - - if (adc_start(&obj->p_adc) == TXZ_SUCCESS) { - // adc started - } - - // wait for Continuous conversion program flag clear. - while((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) { - // Do nothing... - } - - if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) { - error("Failed : To read ADC converted result"); - } - - if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) { - error("Failed : To Stop ADC Conversion"); - } - return (uint16_t)adc_result; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return (float)(value * (1.0f / (float)ADC_12BIT_RANGE)); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/analogout_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/analogout_api.c deleted file mode 100644 index bdbf9b3e4dd..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/analogout_api.c +++ /dev/null @@ -1,127 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "cmsis.h" -#include "analogout_api.h" -#include "pinmap.h" - -#define REG_DAC_DAxCR_REN_DISABLE ((uint32_t)0x00000000) // DAC Control Disable. -#define REG_DAC_DAxCR_REN_ENABLE ((uint32_t)0x00000001) // DAC Control Enable. -#define DAC_RANGE (0xFF) // 8 bits -#define DAC_NB_BITS (8) -#define DAC0_CLR_IN_CLR_OUT (1) // As per TRM DAC pin inout mode should be neither in nor out -#define DAC1_CLR_IN_CLR_OUT (2) -#define MAX_ANALOG_VAL (1.0f) -#define MIN_ANALOG_VAL (0.0f) -#define MAX_DIGITAL_VAL (0xFF) -#define MIN_DIGITAL_VAL (0x00) - -static const PinMap PinMap_DAC[] = { - {PT0, DAC_0, PIN_DATA(0, 1)}, - {PT1, DAC_1, PIN_DATA(0, 1)}, - {NC, NC, 0} -}; - -static inline void dac_write(dac_t *obj,int val) -{ - // Set the DAC output - obj->DACx->REG = (val &= DAC_RANGE); -} - -static inline int dac_read(dac_t *obj) -{ - return ((obj->DACx->REG) & DAC_RANGE); -} - -void analogout_init(dac_t *obj, PinName pin) -{ - DACName dac_name = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(dac_name != (DACName)NC); - obj->dac = dac_name; - switch (dac_name) { - case DAC_0: - obj->DACx = TSB_DA0; - //Enable clock for DAC0 and Port T - TSB_CG_FSYSMENA_IPMENA04 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; - break; - case DAC_1: - obj->DACx = TSB_DA1; - //Enable clock for DAC1 and Port T - TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; - break; - default: - break; - } - // Pinout the chosen DAC - pinmap_pinout(pin, PinMap_DAC); - //DAC pins as neither input and nor output - if(dac_name == DAC_0) { - TSB_PT->CR &= ~(DAC0_CLR_IN_CLR_OUT); - TSB_PT->IE &= ~(DAC0_CLR_IN_CLR_OUT); - } else if(dac_name == DAC_1) { - TSB_PT->CR &= ~(DAC1_CLR_IN_CLR_OUT); - TSB_PT->IE &= ~(DAC1_CLR_IN_CLR_OUT); - } else { - return; - } - - //Enable DAC - obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE; - analogout_write_u16(obj, MIN_DIGITAL_VAL); -} - -void analogout_free(dac_t *obj) -{ - obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE; - obj->dac = (DACName)NC; -} - -void analogout_write(dac_t *obj, float value) -{ - if (value < MIN_ANALOG_VAL) { - dac_write(obj, MIN_DIGITAL_VAL); - } else if (value > MAX_ANALOG_VAL) { - dac_write(obj,DAC_RANGE); - } else { - dac_write(obj, value * (float)DAC_RANGE); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - // writing higher 8-bits to Data Register - dac_write(obj, (value >> (16 - DAC_NB_BITS))); -} - -float analogout_read(dac_t *obj) -{ - uint32_t value = dac_read(obj); - return (float)value * (MAX_ANALOG_VAL / (float)DAC_RANGE); -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - uint32_t value = dac_read(obj); - //Upper and lower byte stored with read value - return ((value << (16 - DAC_NB_BITS)) | value); -} - -const PinMap *analogout_pinmap() -{ - return PinMap_DAC; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device.h b/targets/TARGET_TT/TARGET_TT_M4G9/device.h deleted file mode 100644 index d05e3ffe69c..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device.h +++ /dev/null @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 32 - -#include "objects.h" -#include - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TMPM4G9.h b/targets/TARGET_TT/TARGET_TT_M4G9/device/TMPM4G9.h deleted file mode 100644 index 89371d636e8..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TMPM4G9.h +++ /dev/null @@ -1,6129 +0,0 @@ -/** - ******************************************************************************* - * @file TMPM4G9.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM4G9' Device Series - * @version V1.0.9.0 - * $Date:: 2018-04-02 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER - * @{ - */ - -/** @addtogroup TMPM4G9 - * @{ - */ - -#ifndef __TMPM4G9_H__ -#define __TMPM4G9_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ***************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ - -/****** TMPM4G9 Specific Interrupt Numbers *******************************************************************/ - INT00_IRQn = 0, /*!< Interrupt pin 00a/00b */ - INT01_IRQn = 1, /*!< Interrupt pin 01a/00b */ - INT02_IRQn = 2, /*!< Interrupt pin 02a/00b */ - INT03_IRQn = 3, /*!< Interrupt pin 03a/03b */ - INT04_IRQn = 4, /*!< Interrupt pin 04a/04b */ - INT05_IRQn = 5, /*!< Interrupt pin 05a/05b */ - INT06_IRQn = 6, /*!< Interrupt pin 06a/06b */ - INT07_IRQn = 7, /*!< Interrupt pin 07a/07b */ - INT08_IRQn = 8, /*!< Interrupt pin 08a/08b */ - INT09_IRQn = 9, /*!< Interrupt pin 09a/09b */ - INT10_IRQn = 10, /*!< Interrupt pin 10a/10b */ - INT11_IRQn = 11, /*!< Interrupt pin 11a/11b */ - INT12_IRQn = 12, /*!< Interrupt pin 12a/12b */ - INT13_IRQn = 13, /*!< Interrupt pin 13a/13b */ - INT14_IRQn = 14, /*!< Interrupt pin 14a/14b */ - INT15_IRQn = 15, /*!< Interrupt pin 15a/15b */ - INTRTC_IRQn = 16, /*!< Real time clock(XHz) interrupt */ - INTCEC0RX_IRQn = 17, /*!< CEC reception interrupt (channel 0) */ - INTCEC0TX_IRQn = 18, /*!< CEC transmission interrupt (channel 0) */ - INTISDA_IRQn = 19, /*!< Interval Sensing Detector Interrupt (Unit A) */ - INTISDB_IRQn = 20, /*!< Interval Sensing Detector Interrupt (Unit B) */ - INTISDC_IRQn = 21, /*!< Interval Sensing Detector Interrupt (Unit C) */ - INTRMC0_IRQn = 22, /*!< Remote control reception interrupt 0 */ - INTRMC1_IRQn = 23, /*!< Remote control reception interrupt 1 */ - INTLTTMR0_IRQn = 24, /*!< Long Term Timer Interrupt(channel 0) */ - INTHDMAATC_IRQn = 25, /*!< HDMA Complete of transfer(Unit A) */ - INTHDMAAERR_IRQn = 26, /*!< HDMA transfer error(Unit A) */ - INTHDMABTC_IRQn = 27, /*!< HDMA end of transfer(Unit B) */ - INTHDMABERR_IRQn = 28, /*!< HDMA transfer error(Unit B) */ - INTMDMAATC_IRQn = 29, /*!< MDMA Complete of transfer(Unit A) */ - INTT32A00_A_CT_IRQn = 30, /*!< T32A00 TimerA All Interrupt/Timer Interrupt C */ - INTT32A00_B_C01_CPC_IRQn = 31, /*!< T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A01_A_CT_IRQn = 32, /*!< T32A01 TimerA All Interrupt/Timer Interrupt C */ - INTT32A01_B_C01_CPC_IRQn = 33, /*!< T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A02_A_CT_IRQn = 34, /*!< T32A02 TimerA All Interrupt/Timer Interrupt C */ - INTT32A02_B_C01_CPC_IRQn = 35, /*!< T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A03_A_CT_IRQn = 36, /*!< T32A03 TimerA All Interrupt/Timer Interrupt C */ - INTT32A03_B_C01_CPC_IRQn = 37, /*!< T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A04_A_CT_IRQn = 38, /*!< T32A04 TimerA All Interrupt/Timer Interrupt C */ - INTT32A04_B_C01_CPC_IRQn = 39, /*!< T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A05_A_CT_IRQn = 40, /*!< T32A05 TimerA All Interrupt/Timer Interrupt C */ - INTT32A05_B_C01_CPC_IRQn = 41, /*!< T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A06_A_CT_IRQn = 42, /*!< T32A06 TimerA All Interrupt/Timer Interrupt C */ - INTT32A06_B_C01_CPC_IRQn = 43, /*!< T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A07_A_CT_IRQn = 44, /*!< T32A07 TimerA All Interrupt/Timer Interrupt C */ - INTT32A07_B_C01_CPC_IRQn = 45, /*!< T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A08_A_CT_IRQn = 46, /*!< T32A08 TimerA All Interrupt/Timer Interrupt C */ - INTT32A08_B_C01_CPC_IRQn = 47, /*!< T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A09_A_CT_IRQn = 48, /*!< T32A09 TimerA All Interrupt/Timer Interrupt C */ - INTT32A09_B_C01_CPC_IRQn = 49, /*!< T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A10_A_CT_IRQn = 50, /*!< T32A10 TimerA All Interrupt/Timer Interrupt C */ - INTT32A10_B_C01_CPC_IRQn = 51, /*!< T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A11_A_CT_IRQn = 52, /*!< T32A11 TimerA All Interrupt/Timer Interrupt C */ - INTT32A11_B_C01_CPC_IRQn = 53, /*!< T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A12_A_CT_IRQn = 54, /*!< T32A12 TimerA All Interrupt/Timer Interrupt C */ - INTT32A12_B_C01_CPC_IRQn = 55, /*!< T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTT32A13_A_CT_IRQn = 56, /*!< T32A13 TimerA All Interrupt/Timer Interrupt C */ - INTT32A13_B_C01_CPC_IRQn = 57, /*!< T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/ - INTEMG0_IRQn = 58, /*!< PMD0 EMG interrupt */ - INTOVV0_IRQn = 59, /*!< PMD0 OVV interrupt */ - INTPWM0_IRQn = 60, /*!< PMD0 interrupt */ - INTT0RX_IRQn = 61, /*!< TSPI/SIO reception (channel 0) */ - INTT0TX_IRQn = 62, /*!< TSPI/SIO transmit (channel 0) */ - INTT0ERR_IRQn = 63, /*!< TSPI/SIO error (channel 0) */ - INTT1RX_IRQn = 64, /*!< TSPI/SIO reception (channel 1) */ - INTT1TX_IRQn = 65, /*!< TSPI/SIO transmit (channel 1) */ - INTT1ERR_IRQn = 66, /*!< TSPI/SIO error (channel 1) */ - INTT2RX_IRQn = 67, /*!< TSPI/SIO reception (channel 2) */ - INTT2TX_IRQn = 68, /*!< TSPI/SIO transmit (channel 2) */ - INTT2ERR_IRQn = 69, /*!< TSPI/SIO error (channel 2) */ - INTT3RX_IRQn = 70, /*!< TSPI/SIO reception (channel 3) */ - INTT3TX_IRQn = 71, /*!< TSPI/SIO transmit (channel 3) */ - INTT3ERR_IRQn = 72, /*!< TSPI/SIO error (channel 3) */ - INTT4RX_IRQn = 73, /*!< TSPI/SIO reception (channel 4) */ - INTT4TX_IRQn = 74, /*!< TSPI/SIO transmit (channel 4) */ - INTT4ERR_IRQn = 75, /*!< TSPI/SIO error (channel 4) */ - INTT5RX_IRQn = 76, /*!< TSPI/SIO reception (channel 5) */ - INTT5TX_IRQn = 77, /*!< TSPI/SIO transmit (channel 5) */ - INTT5ERR_IRQn = 78, /*!< TSPI/SIO error (channel 5) */ - INTT6RX_IRQn = 79, /*!< TSPI/SIO reception (channel 6) */ - INTT6TX_IRQn = 80, /*!< TSPI/SIO transmit (channel 6) */ - INTT6ERR_IRQn = 81, /*!< TSPI/SIO error (channel 6) */ - INTT7RX_IRQn = 82, /*!< TSPI/SIO reception (channel 7) */ - INTT7TX_IRQn = 83, /*!< TSPI/SIO transmit (channel 7) */ - INTT7ERR_IRQn = 84, /*!< TSPI/SIO error (channel 7) */ - INTT8RX_IRQn = 85, /*!< TSPI/SIO reception (channel 8) */ - INTT8TX_IRQn = 86, /*!< TSPI/SIO transmit (channel 8) */ - INTT8ERR_IRQn = 87, /*!< TSPI/SIO error (channel 8) */ - INTSMI0_IRQn = 88, /*!< Serial Memory Interface Interrupt */ - INTUART0RX_IRQn = 89, /*!< UART reception (channel 0) */ - INTUART0TX_IRQn = 90, /*!< UART transmit (channel 0) */ - INTUART0ERR_IRQn = 91, /*!< UART error (channel 0) */ - INTUART1RX_IRQn = 92, /*!< UART reception (channel 1) */ - INTUART1TX_IRQn = 93, /*!< UART transmit (channel 1) */ - INTUART1ERR_IRQn = 94, /*!< UART error (channel 1) */ - INTUART2RX_IRQn = 95, /*!< UART reception (channel 2) */ - INTUART2TX_IRQn = 96, /*!< UART transmit (channel 2) */ - INTUART2ERR_IRQn = 97, /*!< UART error (channel 2) */ - INTUART3RX_IRQn = 98, /*!< UART reception (channel 3) */ - INTUART3TX_IRQn = 99, /*!< UART transmit (channel 3) */ - INTUART3ERR_IRQn = 100, /*!< UART error (channel 3) */ - INTUART4RX_IRQn = 101, /*!< UART reception (channel 4) */ - INTUART4TX_IRQn = 102, /*!< UART transmit (channel 4) */ - INTUART4ERR_IRQn = 103, /*!< UART error (channel 4) */ - INTUART5RX_IRQn = 104, /*!< UART reception (channel 5) */ - INTUART5TX_IRQn = 105, /*!< UART transmit (channel 5) */ - INTUART5ERR_IRQn = 106, /*!< UART error (channel 5) */ - INTFUART0_IRQn = 107, /*!< FUART Interrupt(channel 0) */ - INTFUART1_IRQn = 108, /*!< FUART Interrupt(channel 1) */ - INTI2C0_IRQn = 109, /*!< I2C0 transmission and reception interrupt */ - INTI2C0AL_IRQn = 110, /*!< I2C0 arbitration lost interrupt */ - INTI2C0BF_IRQn = 111, /*!< I2C0 bus free interrupt */ - INTI2C0NACK_IRQn = 112, /*!< I2C0 no ack interrupt */ - INTI2C1_IRQn = 113, /*!< I2C1 transmission and reception interrupt */ - INTI2C1AL_IRQn = 114, /*!< I2C1 arbitration lost interrupt */ - INTI2C1BF_IRQn = 115, /*!< I2C1 bus free interrupt */ - INTI2C1NACK_IRQn = 116, /*!< I2C1 no ack interrupt */ - INTI2C2_IRQn = 117, /*!< I2C2 transmission and reception interrupt */ - INTI2C2AL_IRQn = 118, /*!< I2C2 arbitration lost interrupt */ - INTI2C2BF_IRQn = 119, /*!< I2C2 bus free interrupt */ - INTI2C2NACK_IRQn = 120, /*!< I2C2 no ack interrupt */ - INTI2C3_IRQn = 121, /*!< I2C3 transmission and reception interrupt */ - INTI2C3AL_IRQn = 122, /*!< I2C3 arbitration lost interrupt */ - INTI2C3BF_IRQn = 123, /*!< I2C3 bus free interrupt */ - INTI2C3NACK_IRQn = 124, /*!< I2C3 no ack interrupt */ - INTI2C4_IRQn = 125, /*!< I2C4 transmission and reception interrupt */ - INTI2C4AL_IRQn = 126, /*!< I2C4 arbitration lost interrupt */ - INTI2C4BF_IRQn = 127, /*!< I2C4 bus free interrupt */ - INTI2C4NACK_IRQn = 128, /*!< I2C4 no ack interrupt */ - INTADACP0_IRQn = 129, /*!< ADC conversion monitoring function interrupt 0 */ - INTADACP1_IRQn = 130, /*!< ADC conversion monitoring function interrupt 1 */ - INTADATRG_IRQn = 131, /*!< ADC conversion triggered by General purpose is finished */ - INTADASGL_IRQn = 132, /*!< ADC conversion triggered by Single program is finished */ - INTADACNT_IRQn = 133, /*!< ADC conversion triggered by Continuity program is finished */ - INTADAHP_IRQn = 134, /*!< ADC High Priority AD conversion interrupt */ - INTFLDRDY_IRQn = 135, /*!< Data FLASH Ready interrupt */ - INTFLCRDY0_IRQn = 136, /*!< Code FLASH Area0/1 Ready interrupt */ - INTFLCRDY1_IRQn = 137, /*!< Code FLASH Area2 Ready interrupt */ - INTMDMAABERR_IRQn = 139, /*!< MDMA bus error(Unit A) */ - INTMDMAADERR_IRQn = 140 /*!< MDMA descriptor error(Unit A) */ -} IRQn_Type; - -/** Processor and Core Peripheral Section */ - -/* Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_TMPM4G9.h" /* TMPM4G9 System */ - -/** @addtogroup Device_Peripheral_registers - * @{ - */ - -/** Device Specific Peripheral registers structures */ - -/** - * @brief DMA Controller - */ -typedef struct -{ - __I uint32_t INTSTATUS; /*!< DMAC Interrupt Status Register */ - __I uint32_t INTTCSTATUS; /*!< DMAC Interrupt Terminal Count Status Register*/ - __O uint32_t INTTCCLEAR; /*!< DMAC Interrupt Terminal Count Clear Register */ - __I uint32_t INTERRORSTATUS; /*!< DMAC Interrupt Error Status Register */ - __O uint32_t INTERRCLR; /*!< DMAC Interrupt Error Clear Register */ - __I uint32_t RAWINTTCSTATUS; /*!< DMAC Raw Interrupt Terminal Count Status Register*/ - __I uint32_t RAWINTERRORSTATUS; /*!< DMAC Raw Error Interrupt Status Register */ - __I uint32_t ENBLDCHNS; /*!< DMAC Enabled Channel Register */ - __IO uint32_t SOFTBREQ; /*!< DMAC Software Burst Request Register */ - __IO uint32_t SOFTSREQ; /*!< DMAC Software Single Request Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CONFIGURATION; /*!< DMAC Configuration Register */ - uint32_t RESERVED1[51]; - __IO uint32_t C0SRCADDR; /*!< DMAC Channel 0 Source Address Register */ - __IO uint32_t C0DESTADDR; /*!< DMAC Channel 0 Destination Address Register */ - __IO uint32_t C0LLI; /*!< DMAC Channel 0 Linked List Item Register */ - __IO uint32_t C0CONTROL; /*!< DMAC Channel 0 Control Register */ - __IO uint32_t C0CONFIGURATION; /*!< DMAC Channel 0 Configuration Register */ - uint32_t RESERVED2[3]; - __IO uint32_t C1SRCADDR; /*!< DMAC Channel 1 Source Address Register */ - __IO uint32_t C1DESTADDR; /*!< DMAC Channel 1 Destination Address Register */ - __IO uint32_t C1LLI; /*!< DMAC Channel 1 Linked List Item Register */ - __IO uint32_t C1CONTROL; /*!< DMAC Channel 1 Control Register */ - __IO uint32_t C1CONFIGURATION; /*!< DMAC Channel 1 Configuration Register */ -} TSB_DMAC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t MAP0; /*!< SMIF Flash Memory Map0 Register */ - __IO uint32_t MAP1; /*!< SMIF Flash Memory Map1 Register */ - __IO uint32_t DACR0; /*!< SMIF Direct Access Control Register 0 */ - __IO uint32_t DACR1; /*!< SMIF Direct Access Control Register 1 */ - __IO uint32_t DRCR0; /*!< SMIF Direct Read Control Register 0 */ - __IO uint32_t DRCR1; /*!< SMIF Direct Read Control Register 1 */ - uint32_t RESERVED0[250]; - __IO uint32_t RACR0; /*!< SMIF Program Register Access Control Register 0*/ - __IO uint32_t RACR1; /*!< SMIF Program Register Access Control Register 1*/ - __IO uint32_t INT; /*!< SMIF Program Register Access Interrupt Enable Register*/ - __IO uint32_t STAT; /*!< SMIF Program Register Access Status Register */ - uint32_t RESERVED1[60]; - __IO uint32_t PBUF0; /*!< SMIF Program Register Primary Buffer Data Register 0*/ - __IO uint32_t PBUF1; /*!< SMIF Program Register Primary Buffer Data Register 1*/ - uint32_t RESERVED2[62]; - __IO uint32_t SBUF00; /*!< SMIF Program Register Secondary Buffer Data Register 00*/ - __IO uint32_t SBUF01; /*!< SMIF Program Register Secondary Buffer Data Register 01*/ - __IO uint32_t SBUF02; /*!< SMIF Program Register Secondary Buffer Data Register 02*/ - __IO uint32_t SBUF03; /*!< SMIF Program Register Secondary Buffer Data Register 03*/ - __IO uint32_t SBUF04; /*!< SMIF Program Register Secondary Buffer Data Register 04*/ - __IO uint32_t SBUF05; /*!< SMIF Program Register Secondary Buffer Data Register 05*/ - __IO uint32_t SBUF06; /*!< SMIF Program Register Secondary Buffer Data Register 06*/ - __IO uint32_t SBUF07; /*!< SMIF Program Register Secondary Buffer Data Register 07*/ - __IO uint32_t SBUF08; /*!< SMIF Program Register Secondary Buffer Data Register 08*/ - __IO uint32_t SBUF09; /*!< SMIF Program Register Secondary Buffer Data Register 09*/ - __IO uint32_t SBUF10; /*!< SMIF Program Register Secondary Buffer Data Register 10*/ - __IO uint32_t SBUF11; /*!< SMIF Program Register Secondary Buffer Data Register 11*/ - __IO uint32_t SBUF12; /*!< SMIF Program Register Secondary Buffer Data Register 12*/ - __IO uint32_t SBUF13; /*!< SMIF Program Register Secondary Buffer Data Register 13*/ - __IO uint32_t SBUF14; /*!< SMIF Program Register Secondary Buffer Data Register 14*/ - __IO uint32_t SBUF15; /*!< SMIF Program Register Secondary Buffer Data Register 15*/ - __IO uint32_t SBUF16; /*!< SMIF Program Register Secondary Buffer Data Register 16*/ - __IO uint32_t SBUF17; /*!< SMIF Program Register Secondary Buffer Data Register 17*/ - __IO uint32_t SBUF18; /*!< SMIF Program Register Secondary Buffer Data Register 18*/ - __IO uint32_t SBUF19; /*!< SMIF Program Register Secondary Buffer Data Register 19*/ - __IO uint32_t SBUF20; /*!< SMIF Program Register Secondary Buffer Data Register 20*/ - __IO uint32_t SBUF21; /*!< SMIF Program Register Secondary Buffer Data Register 21*/ - __IO uint32_t SBUF22; /*!< SMIF Program Register Secondary Buffer Data Register 22*/ - __IO uint32_t SBUF23; /*!< SMIF Program Register Secondary Buffer Data Register 23*/ - __IO uint32_t SBUF24; /*!< SMIF Program Register Secondary Buffer Data Register 24*/ - __IO uint32_t SBUF25; /*!< SMIF Program Register Secondary Buffer Data Register 25*/ - __IO uint32_t SBUF26; /*!< SMIF Program Register Secondary Buffer Data Register 26*/ - __IO uint32_t SBUF27; /*!< SMIF Program Register Secondary Buffer Data Register 27*/ - __IO uint32_t SBUF28; /*!< SMIF Program Register Secondary Buffer Data Register 28*/ - __IO uint32_t SBUF29; /*!< SMIF Program Register Secondary Buffer Data Register 29*/ - __IO uint32_t SBUF30; /*!< SMIF Program Register Secondary Buffer Data Register 30*/ - __IO uint32_t SBUF31; /*!< SMIF Program Register Secondary Buffer Data Register 31*/ - __IO uint32_t SBUF32; /*!< SMIF Program Register Secondary Buffer Data Register 32*/ - __IO uint32_t SBUF33; /*!< SMIF Program Register Secondary Buffer Data Register 33*/ - __IO uint32_t SBUF34; /*!< SMIF Program Register Secondary Buffer Data Register 34*/ - __IO uint32_t SBUF35; /*!< SMIF Program Register Secondary Buffer Data Register 35*/ - __IO uint32_t SBUF36; /*!< SMIF Program Register Secondary Buffer Data Register 36*/ - __IO uint32_t SBUF37; /*!< SMIF Program Register Secondary Buffer Data Register 37*/ - __IO uint32_t SBUF38; /*!< SMIF Program Register Secondary Buffer Data Register 38*/ - __IO uint32_t SBUF39; /*!< SMIF Program Register Secondary Buffer Data Register 39*/ - __IO uint32_t SBUF40; /*!< SMIF Program Register Secondary Buffer Data Register 40*/ - __IO uint32_t SBUF41; /*!< SMIF Program Register Secondary Buffer Data Register 41*/ - __IO uint32_t SBUF42; /*!< SMIF Program Register Secondary Buffer Data Register 42*/ - __IO uint32_t SBUF43; /*!< SMIF Program Register Secondary Buffer Data Register 43*/ - __IO uint32_t SBUF44; /*!< SMIF Program Register Secondary Buffer Data Register 44*/ - __IO uint32_t SBUF45; /*!< SMIF Program Register Secondary Buffer Data Register 45*/ - __IO uint32_t SBUF46; /*!< SMIF Program Register Secondary Buffer Data Register 46*/ - __IO uint32_t SBUF47; /*!< SMIF Program Register Secondary Buffer Data Register 47*/ - __IO uint32_t SBUF48; /*!< SMIF Program Register Secondary Buffer Data Register 48*/ - __IO uint32_t SBUF49; /*!< SMIF Program Register Secondary Buffer Data Register 49*/ - __IO uint32_t SBUF50; /*!< SMIF Program Register Secondary Buffer Data Register 50*/ - __IO uint32_t SBUF51; /*!< SMIF Program Register Secondary Buffer Data Register 51*/ - __IO uint32_t SBUF52; /*!< SMIF Program Register Secondary Buffer Data Register 52*/ - __IO uint32_t SBUF53; /*!< SMIF Program Register Secondary Buffer Data Register 53*/ - __IO uint32_t SBUF54; /*!< SMIF Program Register Secondary Buffer Data Register 54*/ - __IO uint32_t SBUF55; /*!< SMIF Program Register Secondary Buffer Data Register 55*/ - __IO uint32_t SBUF56; /*!< SMIF Program Register Secondary Buffer Data Register 56*/ - __IO uint32_t SBUF57; /*!< SMIF Program Register Secondary Buffer Data Register 57*/ - __IO uint32_t SBUF58; /*!< SMIF Program Register Secondary Buffer Data Register 58*/ - __IO uint32_t SBUF59; /*!< SMIF Program Register Secondary Buffer Data Register 59*/ - __IO uint32_t SBUF60; /*!< SMIF Program Register Secondary Buffer Data Register 60*/ - __IO uint32_t SBUF61; /*!< SMIF Program Register Secondary Buffer Data Register 61*/ - __IO uint32_t SBUF62; /*!< SMIF Program Register Secondary Buffer Data Register 62*/ - __IO uint32_t SBUF63; /*!< SMIF Program Register Secondary Buffer Data Register 63*/ -} TSB_SMI_TypeDef; - -/** - * @brief Interrupt control A Register - */ -typedef struct -{ - __IO uint8_t NIC00; /*!< Non Maskable interrupt Mode Control Register A 00*/ - uint8_t RESERVED0[31]; - __IO uint8_t IMC00; /*!< interrupt Mode Control Register A 00 */ - __IO uint8_t IMC01; /*!< interrupt Mode Control Register A 01 */ - __IO uint8_t IMC02; /*!< interrupt Mode Control Register A 02 */ - __IO uint8_t IMC03; /*!< interrupt Mode Control Register A 03 */ - __IO uint8_t IMC04; /*!< interrupt Mode Control Register A 04 */ - __IO uint8_t IMC05; /*!< interrupt Mode Control Register A 05 */ - __IO uint8_t IMC06; /*!< interrupt Mode Control Register A 06 */ - __IO uint8_t IMC07; /*!< interrupt Mode Control Register A 07 */ - __IO uint8_t IMC08; /*!< interrupt Mode Control Register A 08 */ - __IO uint8_t IMC09; /*!< interrupt Mode Control Register A 09 */ - __IO uint8_t IMC10; /*!< interrupt Mode Control Register A 10 */ - __IO uint8_t IMC11; /*!< interrupt Mode Control Register A 11 */ - __IO uint8_t IMC12; /*!< interrupt Mode Control Register A 12 */ - __IO uint8_t IMC13; /*!< interrupt Mode Control Register A 13 */ - __IO uint8_t IMC14; /*!< interrupt Mode Control Register A 14 */ - __IO uint8_t IMC15; /*!< interrupt Mode Control Register A 15 */ - __IO uint8_t IMC16; /*!< interrupt Mode Control Register A 16 */ - __IO uint8_t IMC17; /*!< interrupt Mode Control Register A 17 */ - __IO uint8_t IMC18; /*!< interrupt Mode Control Register A 18 */ - __IO uint8_t IMC19; /*!< interrupt Mode Control Register A 19 */ - __IO uint8_t IMC20; /*!< interrupt Mode Control Register A 20 */ - __IO uint8_t IMC21; /*!< interrupt Mode Control Register A 21 */ - __IO uint8_t IMC22; /*!< interrupt Mode Control Register A 22 */ - __IO uint8_t IMC23; /*!< interrupt Mode Control Register A 23 */ - __IO uint8_t IMC24; /*!< interrupt Mode Control Register A 24 */ - __IO uint8_t IMC25; /*!< interrupt Mode Control Register A 25 */ - __IO uint8_t IMC26; /*!< interrupt Mode Control Register A 26 */ - __IO uint8_t IMC27; /*!< interrupt Mode Control Register A 27 */ - __IO uint8_t IMC28; /*!< interrupt Mode Control Register A 28 */ - __IO uint8_t IMC29; /*!< interrupt Mode Control Register A 29 */ - __IO uint8_t IMC30; /*!< interrupt Mode Control Register A 30 */ - __IO uint8_t IMC31; /*!< interrupt Mode Control Register A 31 */ - uint8_t RESERVED1[17]; - __IO uint8_t IMC49; /*!< interrupt Mode Control Register A 49 */ - __IO uint8_t IMC50; /*!< interrupt Mode Control Register A 50 */ - __IO uint8_t IMC51; /*!< interrupt Mode Control Register A 51 */ - __IO uint8_t IMC52; /*!< interrupt Mode Control Register A 52 */ - __IO uint8_t IMC53; /*!< interrupt Mode Control Register A 53 */ - __IO uint8_t IMC54; /*!< interrupt Mode Control Register A 54 */ - __IO uint8_t IMC55; /*!< interrupt Mode Control Register A 55 */ - __IO uint8_t IMC56; /*!< interrupt Mode Control Register A 56 */ - __IO uint8_t IMC57; /*!< interrupt Mode Control Register A 57 */ -} TSB_IA_TypeDef; - -/** - * @brief Reset Low power Management Register - */ -typedef struct -{ - __IO uint8_t LOSCCR; /*!< Low OSC and IHOSC2 clock supply Control Register*/ - __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */ - __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ - __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ - uint8_t RESERVED0[11]; - __IO uint8_t PROTECT; /*!< Protect Register */ -} TSB_RLM_TypeDef; - -/** - * @brief LVD0 - */ -typedef struct -{ - __IO uint8_t CR1; /*!< LVD Control register1 */ - __IO uint8_t CR2; /*!< LVD Control register2 */ - __IO uint8_t LVL1; /*!< LVD detection voltage select register 1 */ - __IO uint8_t LVL2; /*!< LVD detection voltage select register 2 */ - __I uint8_t SR; /*!< LVD status register */ -} TSB_LVD_TypeDef; - -/** - * @brief TRGSEL - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ - __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ - __IO uint32_t CR2; /*!< TSEL Control register 2 */ - __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ - __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ - __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ - __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ - __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ - __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ - __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ - __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ - __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ - __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ - __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ -} TSB_TSEL_TypeDef; - -/** - * @brief Long Term Timer(LTTMR) - */ -typedef struct -{ - __IO uint8_t CR0; /*!< Long Term Control Register */ - __IO uint8_t VALL; /*!< Long Term Setting Register */ - __IO uint8_t VALH; /*!< Long Term Setting Register */ -} TSB_LTT_TypeDef; - -/** - * @brief Serial Interface (TSPI) - */ -typedef struct -{ - __IO uint32_t CR0; /*!< TSPI Control Register 0 */ - __IO uint32_t CR1; /*!< TSPI Control Register 1 */ - __IO uint32_t CR2; /*!< TSPI Control Register 2 */ - __IO uint32_t CR3; /*!< TSPI Control Register 3 */ - __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ - __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ - __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ - uint32_t RESERVED0[57]; - __IO uint32_t DR; /*!< TSPI Data Register */ - uint32_t RESERVED1[63]; - __IO uint32_t SR; /*!< TSPI Status Register */ - __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ -} TSB_TSPI_TypeDef; - -/** - * @brief External Bus Interface(EXB) - */ -typedef struct -{ - __IO uint32_t MOD; /*!< External Bus Mode Control Register */ - uint32_t RESERVED0[3]; - __IO uint32_t AS0; /*!< External Bus Base Address and CS Space setting Register 0*/ - __IO uint32_t AS1; /*!< External Bus Base Address and CS Space setting Register 1 */ - __IO uint32_t AS2; /*!< External Bus Base Address and CS Space setting Register 2*/ - __IO uint32_t AS3; /*!< External Bus Base Address and CS Space setting Register 3*/ - uint32_t RESERVED1[8]; - __IO uint32_t CS0; /*!< Chip Select and Wait Controller Register 0 */ - __IO uint32_t CS1; /*!< Chip Select and Wait Controller Register 1 */ - __IO uint32_t CS2; /*!< Chip Select and Wait Controller Register 2 */ - __IO uint32_t CS3; /*!< Chip Select and Wait Controller Register 3 */ - uint32_t RESERVED2[4]; - __IO uint32_t CLKCTL; /*!< Clock output controlRegister */ -} TSB_EXB_TypeDef; - -/** - * @brief Clock Generator (CG) - */ -typedef struct -{ - __IO uint32_t PROTECT; /*!< Protect Register */ - __IO uint32_t OSCCR; /*!< Oscillation Control Register */ - __IO uint32_t SYSCR; /*!< System Clock Control Register */ - __IO uint32_t STBYCR; /*!< Standby Control Register */ - uint32_t RESERVED0[4]; - __IO uint32_t PLL0SEL; /*!< PLL Selection Register 0 */ - uint32_t RESERVED1[3]; - __IO uint32_t WUPHCR; /*!< High OSC Warming-up Register */ - __IO uint32_t WUPLCR; /*!< Low OSC Warming-up Register */ - uint32_t RESERVED2[4]; - __IO uint32_t FSYSMENA; /*!< Middle fsys Supply Stop Register A */ - __IO uint32_t FSYSMENB; /*!< Middle fsys Supply Stop Register A */ - __IO uint32_t FSYSENA; /*!< High fsys Supply Stop Register A */ - uint32_t RESERVED3; - __IO uint32_t FCEN; /*!< FC Supply Stop Register */ - __IO uint32_t SPCLKEN; /*!< ADC TRACE Clock Supply Stop Register */ - uint32_t RESERVED4[2]; - __IO uint32_t EXTEND2; /*!< Extend for MDMAC Register */ -} TSB_CG_TypeDef; - -/** - * @brief Interrupt Control B Register - */ -typedef struct -{ - uint8_t RESERVED0[16]; - __IO uint8_t NIC00; /*!< Non maskable interrupt Control Register 00 */ - uint8_t RESERVED1[79]; - __IO uint8_t IMC000; /*!< interrupt Mode Control Register 000 */ - __IO uint8_t IMC001; /*!< interrupt Mode Control Register 001 */ - __IO uint8_t IMC002; /*!< interrupt Mode Control Register 002 */ - __IO uint8_t IMC003; /*!< interrupt Mode Control Register 003 */ - __IO uint8_t IMC004; /*!< interrupt Mode Control Register 004 */ - __IO uint8_t IMC005; /*!< interrupt Mode Control Register 005 */ - __IO uint8_t IMC006; /*!< interrupt Mode Control Register 006 */ - __IO uint8_t IMC007; /*!< interrupt Mode Control Register 007 */ - __IO uint8_t IMC008; /*!< interrupt Mode Control Register 008 */ - __IO uint8_t IMC009; /*!< interrupt Mode Control Register 009 */ - __IO uint8_t IMC010; /*!< interrupt Mode Control Register 010 */ - __IO uint8_t IMC011; /*!< interrupt Mode Control Register 011 */ - __IO uint8_t IMC012; /*!< interrupt Mode Control Register 012 */ - __IO uint8_t IMC013; /*!< interrupt Mode Control Register 013 */ - __IO uint8_t IMC014; /*!< interrupt Mode Control Register 014 */ - __IO uint8_t IMC015; /*!< interrupt Mode Control Register 015 */ - __IO uint8_t IMC016; /*!< interrupt Mode Control Register 016 */ - __IO uint8_t IMC017; /*!< interrupt Mode Control Register 017 */ - __IO uint8_t IMC018; /*!< interrupt Mode Control Register 018 */ - __IO uint8_t IMC019; /*!< interrupt Mode Control Register 019 */ - __IO uint8_t IMC020; /*!< interrupt Mode Control Register 020 */ - __IO uint8_t IMC021; /*!< interrupt Mode Control Register 021 */ - __IO uint8_t IMC022; /*!< interrupt Mode Control Register 022 */ - __IO uint8_t IMC023; /*!< interrupt Mode Control Register 023 */ - __IO uint8_t IMC024; /*!< interrupt Mode Control Register 024 */ - __IO uint8_t IMC025; /*!< interrupt Mode Control Register 025 */ - __IO uint8_t IMC026; /*!< interrupt Mode Control Register 026 */ - __IO uint8_t IMC027; /*!< interrupt Mode Control Register 027 */ - __IO uint8_t IMC028; /*!< interrupt Mode Control Register 028 */ - __IO uint8_t IMC029; /*!< interrupt Mode Control Register 029 */ - __IO uint8_t IMC030; /*!< interrupt Mode Control Register 030 */ - __IO uint8_t IMC031; /*!< interrupt Mode Control Register 031 */ - __IO uint8_t IMC032; /*!< interrupt Mode Control Register 032 */ - __IO uint8_t IMC033; /*!< interrupt Mode Control Register 033 */ - __IO uint8_t IMC034; /*!< interrupt Mode Control Register 034 */ - __IO uint8_t IMC035; /*!< interrupt Mode Control Register 035 */ - __IO uint8_t IMC036; /*!< interrupt Mode Control Register 036 */ - __IO uint8_t IMC037; /*!< interrupt Mode Control Register 037 */ - __IO uint8_t IMC038; /*!< interrupt Mode Control Register 038 */ - __IO uint8_t IMC039; /*!< interrupt Mode Control Register 039 */ - __IO uint8_t IMC040; /*!< interrupt Mode Control Register 040 */ - __IO uint8_t IMC041; /*!< interrupt Mode Control Register 041 */ - __IO uint8_t IMC042; /*!< interrupt Mode Control Register 042 */ - __IO uint8_t IMC043; /*!< interrupt Mode Control Register 043 */ - __IO uint8_t IMC044; /*!< interrupt Mode Control Register 044 */ - __IO uint8_t IMC045; /*!< interrupt Mode Control Register 045 */ - __IO uint8_t IMC046; /*!< interrupt Mode Control Register 046 */ - __IO uint8_t IMC047; /*!< interrupt Mode Control Register 047 */ - __IO uint8_t IMC048; /*!< interrupt Mode Control Register 048 */ - __IO uint8_t IMC049; /*!< interrupt Mode Control Register 049 */ - __IO uint8_t IMC050; /*!< interrupt Mode Control Register 050 */ - __IO uint8_t IMC051; /*!< interrupt Mode Control Register 051 */ - __IO uint8_t IMC052; /*!< interrupt Mode Control Register 052 */ - __IO uint8_t IMC053; /*!< interrupt Mode Control Register 053 */ - __IO uint8_t IMC054; /*!< interrupt Mode Control Register 054 */ - __IO uint8_t IMC055; /*!< interrupt Mode Control Register 055 */ - __IO uint8_t IMC056; /*!< interrupt Mode Control Register 056 */ - __IO uint8_t IMC057; /*!< interrupt Mode Control Register 057 */ - __IO uint8_t IMC058; /*!< interrupt Mode Control Register 058 */ - __IO uint8_t IMC059; /*!< interrupt Mode Control Register 059 */ - __IO uint8_t IMC060; /*!< interrupt Mode Control Register 060 */ - __IO uint8_t IMC061; /*!< interrupt Mode Control Register 061 */ - __IO uint8_t IMC062; /*!< interrupt Mode Control Register 062 */ - __IO uint8_t IMC063; /*!< interrupt Mode Control Register 063 */ - __IO uint8_t IMC064; /*!< interrupt Mode Control Register 064 */ - __IO uint8_t IMC065; /*!< interrupt Mode Control Register 065 */ - __IO uint8_t IMC066; /*!< interrupt Mode Control Register 066 */ - __IO uint8_t IMC067; /*!< interrupt Mode Control Register 067 */ - __IO uint8_t IMC068; /*!< interrupt Mode Control Register 068 */ - __IO uint8_t IMC069; /*!< interrupt Mode Control Register 069 */ - __IO uint8_t IMC070; /*!< interrupt Mode Control Register 070 */ - __IO uint8_t IMC071; /*!< interrupt Mode Control Register 071 */ - __IO uint8_t IMC072; /*!< interrupt Mode Control Register 072 */ - __IO uint8_t IMC073; /*!< interrupt Mode Control Register 073 */ - __IO uint8_t IMC074; /*!< interrupt Mode Control Register 074 */ - __IO uint8_t IMC075; /*!< interrupt Mode Control Register 075 */ - __IO uint8_t IMC076; /*!< interrupt Mode Control Register 076 */ - __IO uint8_t IMC077; /*!< interrupt Mode Control Register 077 */ - __IO uint8_t IMC078; /*!< interrupt Mode Control Register 078 */ - __IO uint8_t IMC079; /*!< interrupt Mode Control Register 079 */ - __IO uint8_t IMC080; /*!< interrupt Mode Control Register 080 */ - __IO uint8_t IMC081; /*!< interrupt Mode Control Register 081 */ - __IO uint8_t IMC082; /*!< interrupt Mode Control Register 082 */ - __IO uint8_t IMC083; /*!< interrupt Mode Control Register 083 */ - __IO uint8_t IMC084; /*!< interrupt Mode Control Register 084 */ - __IO uint8_t IMC085; /*!< interrupt Mode Control Register 085 */ - __IO uint8_t IMC086; /*!< interrupt Mode Control Register 086 */ - __IO uint8_t IMC087; /*!< interrupt Mode Control Register 087 */ - __IO uint8_t IMC088; /*!< interrupt Mode Control Register 088 */ - __IO uint8_t IMC089; /*!< interrupt Mode Control Register 089 */ - __IO uint8_t IMC090; /*!< interrupt Mode Control Register 090 */ - __IO uint8_t IMC091; /*!< interrupt Mode Control Register 091 */ - __IO uint8_t IMC092; /*!< interrupt Mode Control Register 092 */ - __IO uint8_t IMC093; /*!< interrupt Mode Control Register 093 */ - __IO uint8_t IMC094; /*!< interrupt Mode Control Register 094 */ - __IO uint8_t IMC095; /*!< interrupt Mode Control Register 095 */ - __IO uint8_t IMC096; /*!< interrupt Mode Control Register 096 */ - __IO uint8_t IMC097; /*!< interrupt Mode Control Register 097 */ - __IO uint8_t IMC098; /*!< interrupt Mode Control Register 098 */ - __IO uint8_t IMC099; /*!< interrupt Mode Control Register 099 */ - __IO uint8_t IMC100; /*!< interrupt Mode Control Register 100 */ - __IO uint8_t IMC101; /*!< interrupt Mode Control Register 101 */ - __IO uint8_t IMC102; /*!< interrupt Mode Control Register 102 */ - __IO uint8_t IMC103; /*!< interrupt Mode Control Register 103 */ - __IO uint8_t IMC104; /*!< interrupt Mode Control Register 104 */ - __IO uint8_t IMC105; /*!< interrupt Mode Control Register 105 */ - __IO uint8_t IMC106; /*!< interrupt Mode Control Register 106 */ - __IO uint8_t IMC107; /*!< interrupt Mode Control Register 107 */ - __IO uint8_t IMC108; /*!< interrupt Mode Control Register 108 */ - __IO uint8_t IMC109; /*!< interrupt Mode Control Register 109 */ - __IO uint8_t IMC110; /*!< interrupt Mode Control Register 110 */ - __IO uint8_t IMC111; /*!< interrupt Mode Control Register 111 */ - __IO uint8_t IMC112; /*!< interrupt Mode Control Register 112 */ - __IO uint8_t IMC113; /*!< interrupt Mode Control Register 113 */ - __IO uint8_t IMC114; /*!< interrupt Mode Control Register 114 */ - __IO uint8_t IMC115; /*!< interrupt Mode Control Register 115 */ - __IO uint8_t IMC116; /*!< interrupt Mode Control Register 116 */ - __IO uint8_t IMC117; /*!< interrupt Mode Control Register 117 */ - __IO uint8_t IMC118; /*!< interrupt Mode Control Register 118 */ - __IO uint8_t IMC119; /*!< interrupt Mode Control Register 119 */ - __IO uint8_t IMC120; /*!< interrupt Mode Control Register 120 */ - __IO uint8_t IMC121; /*!< interrupt Mode Control Register 121 */ - __IO uint8_t IMC122; /*!< interrupt Mode Control Register 122 */ - __IO uint8_t IMC123; /*!< interrupt Mode Control Register 123 */ - __IO uint8_t IMC124; /*!< interrupt Mode Control Register 124 */ - __IO uint8_t IMC125; /*!< interrupt Mode Control Register 125 */ - __IO uint8_t IMC126; /*!< interrupt Mode Control Register 126 */ - __IO uint8_t IMC127; /*!< interrupt Mode Control Register 127 */ - __IO uint8_t IMC128; /*!< interrupt Mode Control Register 128 */ - __IO uint8_t IMC129; /*!< interrupt Mode Control Register 129 */ - __IO uint8_t IMC130; /*!< interrupt Mode Control Register 130 */ - __IO uint8_t IMC131; /*!< interrupt Mode Control Register 131 */ - __IO uint8_t IMC132; /*!< interrupt Mode Control Register 132 */ - __IO uint8_t IMC133; /*!< interrupt Mode Control Register 133 */ - __IO uint8_t IMC134; /*!< interrupt Mode Control Register 134 */ - __IO uint8_t IMC135; /*!< interrupt Mode Control Register 135 */ - __IO uint8_t IMC136; /*!< interrupt Mode Control Register 136 */ - __IO uint8_t IMC137; /*!< interrupt Mode Control Register 137 */ - __IO uint8_t IMC138; /*!< interrupt Mode Control Register 138 */ - __IO uint8_t IMC139; /*!< interrupt Mode Control Register 139 */ - __IO uint8_t IMC140; /*!< interrupt Mode Control Register 140 */ - __IO uint8_t IMC141; /*!< interrupt Mode Control Register 141 */ -} TSB_IB_TypeDef; - -/** - * @brief Interrupt Monitor Register - */ -typedef struct -{ - __I uint32_t FLGNMI; /*!< NMI Interrupt Monitor Flag 0 */ - __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 (032 - 063) */ - __I uint32_t FLG2; /*!< Interrupt Monitor Flag 2 (064 - 095) */ - __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 (096 - 127) */ - __I uint32_t FLG4; /*!< Interrupt Monitor Flag 4 (128 - 159) */ - __I uint32_t FLG5; /*!< Interrupt Monitor Flag 5 (160 - 191) */ - __I uint32_t FLG6; /*!< Interrupt Monitor Flag 6 (192 - 223) */ - __I uint32_t FLG7; /*!< Interrupt Monitor Flag 7 (224 - 225) */ -} TSB_IMN_TypeDef; - -/** - * @brief DNF - */ -typedef struct -{ - __IO uint32_t CKCR; /*!< DNF clock Control register */ - __IO uint32_t ENCR; /*!< DNF Enable register */ -} TSB_DNF_TypeDef; - -/** - * @brief Watchdog Timer (WD) - */ -typedef struct -{ - __IO uint32_t PRO; /*!< SIWD Protect Register */ - __IO uint32_t EN; /*!< SIWD Enable Register */ - __O uint32_t CR; /*!< SIWD Control Register */ - __IO uint32_t MOD; /*!< SIWD Mode Register */ - __I uint32_t MONI; /*!< SIWD Monitor Register */ -} TSB_SIWD_TypeDef; - -/** - * @brief NBD - */ -typedef struct -{ - __IO uint32_t CR0; /*!< NBD control register 0 */ - __IO uint32_t CR1; /*!< NBD control register 1 */ -} TSB_NBD_TypeDef; - -/** - * @brief Malti Porpose Direct Memory Accsess(MDMA) - */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint32_t CEN; /*!< MDMAC Channel Enable Register */ - __IO uint32_t REQ; /*!< MDMAC Transfer Request Register */ - __IO uint32_t SUS; /*!< MDMAC Transfer Suspension Register */ - __IO uint32_t ACT; /*!< MDMAC Transfer Active Register */ - __IO uint32_t END; /*!< MDMAC Transfer End Register */ - __IO uint32_t PRI; /*!< MDMAC Priority Setting Register */ - __IO uint32_t ENE; /*!< MDMAC End Interrupt Enable Register */ - __IO uint32_t DTAB; /*!< MDMAC Channel Information Address Register */ - uint32_t RESERVED1; - __I uint32_t CHN; /*!< MDMAC Channel Number Register */ - __I uint32_t XFTYP; /*!< MDMAC Channel Number Register */ - __I uint32_t XFSAD; /*!< MDMAC Transfer Source Address Register */ - __I uint32_t XFDAD; /*!< MDMAC Transfer Destination Address Register */ - __I uint32_t XFSIZ; /*!< MDMAC Transfer Size Register */ - __I uint32_t DSADS; /*!< MDMAC Descriptor Address Register */ - __I uint32_t DSNUM; /*!< MDMAC Descriptor Number Register */ - uint32_t RESERVED2[3]; - __I uint32_t C00XFTYP; /*!< MDMAC Channel 00 Number Avoidance Register */ - __I uint32_t C00XFSAD; /*!< MDMAC Channel 00 Transfer Source Address Avoidance Register*/ - __I uint32_t C00XFDAD; /*!< MDMAC Channel 00 Transfer Destination Address Avoidance Register*/ - __I uint32_t C00XFSIZ; /*!< MDMAC Channel 00 Transfer Size Avoidance Register*/ - __I uint32_t C00DSADS; /*!< MDMAC Channel 00 Descriptor Address Avoidance Register*/ - __I uint32_t C00DSNUM; /*!< MDMAC Channel 00 Descriptor Number Avoidance Register*/ - uint32_t RESERVED3[2]; - __I uint32_t C01XFTYP; /*!< MDMAC Channel 01 Number Avoidance Register */ - __I uint32_t C01XFSAD; /*!< MDMAC Channel 01 Transfer Source Address Avoidance Register*/ - __I uint32_t C01XFDAD; /*!< MDMAC Channel 01 Transfer Destination Address Avoidance Register*/ - __I uint32_t C01XFSIZ; /*!< MDMAC Channel 01 Transfer Size Avoidance Register*/ - __I uint32_t C01DSADS; /*!< MDMAC Channel 01 Descriptor Address Avoidance Register*/ - __I uint32_t C01DSNUM; /*!< MDMAC Channel 01 Descriptor Number Avoidance Register*/ - uint32_t RESERVED4[2]; - __I uint32_t C02XFTYP; /*!< MDMAC Channel 02 Number Avoidance Register */ - __I uint32_t C02XFSAD; /*!< MDMAC Channel 02 Transfer Source Address Avoidance Register*/ - __I uint32_t C02XFDAD; /*!< MDMAC Channel 02 Transfer Destination Address Avoidance Register*/ - __I uint32_t C02XFSIZ; /*!< MDMAC Channel 02 Transfer Size Avoidance Register*/ - __I uint32_t C02DSADS; /*!< MDMAC Channel 02 Descriptor Address Avoidance Register*/ - __I uint32_t C02DSNUM; /*!< MDMAC Channel 02 Descriptor Number Avoidance Register*/ - uint32_t RESERVED5[2]; - __I uint32_t C03XFTYP; /*!< MDMAC Channel 03 Number Avoidance Register */ - __I uint32_t C03XFSAD; /*!< MDMAC Channel 03 Transfer Source Address Avoidance Register*/ - __I uint32_t C03XFDAD; /*!< MDMAC Channel 03 Transfer Destination Address Avoidance Register*/ - __I uint32_t C03XFSIZ; /*!< MDMAC Channel 03 Transfer Size Avoidance Register*/ - __I uint32_t C03DSADS; /*!< MDMAC Channel 03 Descriptor Address Avoidance Register*/ - __I uint32_t C03DSNUM; /*!< MDMAC Channel 03 Descriptor Number Avoidance Register*/ - uint32_t RESERVED6[2]; - __I uint32_t C04XFTYP; /*!< MDMAC Channel 04 Number Avoidance Register */ - __I uint32_t C04XFSAD; /*!< MDMAC Channel 04 Transfer Source Address Avoidance Register*/ - __I uint32_t C04XFDAD; /*!< MDMAC Channel 04 Transfer Destination Address Avoidance Register*/ - __I uint32_t C04XFSIZ; /*!< MDMAC Channel 04 Transfer Size Avoidance Register*/ - __I uint32_t C04DSADS; /*!< MDMAC Channel 04 Descriptor Address Avoidance Register*/ - __I uint32_t C04DSNUM; /*!< MDMAC Channel 04 Descriptor Number Avoidance Register*/ - uint32_t RESERVED7[2]; - __I uint32_t C05XFTYP; /*!< MDMAC Channel 05 Number Avoidance Register */ - __I uint32_t C05XFSAD; /*!< MDMAC Channel 05 Transfer Source Address Avoidance Register*/ - __I uint32_t C05XFDAD; /*!< MDMAC Channel 05 Transfer Destination Address Avoidance Register*/ - __I uint32_t C05XFSIZ; /*!< MDMAC Channel 05 Transfer Size Avoidance Register*/ - __I uint32_t C05DSADS; /*!< MDMAC Channel 05 Descriptor Address Avoidance Register*/ - __I uint32_t C05DSNUM; /*!< MDMAC Channel 05 Descriptor Number Avoidance Register*/ - uint32_t RESERVED8[2]; - __I uint32_t C06XFTYP; /*!< MDMAC Channel 06 Number Avoidance Register */ - __I uint32_t C06XFSAD; /*!< MDMAC Channel 06 Transfer Source Address Avoidance Register*/ - __I uint32_t C06XFDAD; /*!< MDMAC Channel 06 Transfer Destination Address Avoidance Register*/ - __I uint32_t C06XFSIZ; /*!< MDMAC Channel 06 Transfer Size Avoidance Register*/ - __I uint32_t C06DSADS; /*!< MDMAC Channel 06 Descriptor Address Avoidance Register*/ - __I uint32_t C06DSNUM; /*!< MDMAC Channel 06 Descriptor Number Avoidance Register*/ - uint32_t RESERVED9[2]; - __I uint32_t C07XFTYP; /*!< MDMAC Channel 07 Number Avoidance Register */ - __I uint32_t C07XFSAD; /*!< MDMAC Channel 07 Transfer Source Address Avoidance Register*/ - __I uint32_t C07XFDAD; /*!< MDMAC Channel 07 Transfer Destination Address Avoidance Register*/ - __I uint32_t C07XFSIZ; /*!< MDMAC Channel 07 Transfer Size Avoidance Register*/ - __I uint32_t C07DSADS; /*!< MDMAC Channel 07 Descriptor Address Avoidance Register*/ - __I uint32_t C07DSNUM; /*!< MDMAC Channel 07 Descriptor Number Avoidance Register*/ - uint32_t RESERVED10[2]; - __I uint32_t C08XFTYP; /*!< MDMAC Channel 08 Number Avoidance Register */ - __I uint32_t C08XFSAD; /*!< MDMAC Channel 08 Transfer Source Address Avoidance Register*/ - __I uint32_t C08XFDAD; /*!< MDMAC Channel 08 Transfer Destination Address Avoidance Register*/ - __I uint32_t C08XFSIZ; /*!< MDMAC Channel 08 Transfer Size Avoidance Register*/ - __I uint32_t C08DSADS; /*!< MDMAC Channel 08 Descriptor Address Avoidance Register*/ - __I uint32_t C08DSNUM; /*!< MDMAC Channel 08 Descriptor Number Avoidance Register*/ - uint32_t RESERVED11[2]; - __I uint32_t C09XFTYP; /*!< MDMAC Channel 09 Number Avoidance Register */ - __I uint32_t C09XFSAD; /*!< MDMAC Channel 09 Transfer Source Address Avoidance Register*/ - __I uint32_t C09XFDAD; /*!< MDMAC Channel 09 Transfer Destination Address Avoidance Register*/ - __I uint32_t C09XFSIZ; /*!< MDMAC Channel 09 Transfer Size Avoidance Register*/ - __I uint32_t C09DSADS; /*!< MDMAC Channel 09 Descriptor Address Avoidance Register*/ - __I uint32_t C09DSNUM; /*!< MDMAC Channel 09 Descriptor Number Avoidance Register*/ - uint32_t RESERVED12[2]; - __I uint32_t C10XFTYP; /*!< MDMAC Channel 10 Number Avoidance Register */ - __I uint32_t C10XFSAD; /*!< MDMAC Channel 10 Transfer Source Address Avoidance Register*/ - __I uint32_t C10XFDAD; /*!< MDMAC Channel 10 Transfer Destination Address Avoidance Register*/ - __I uint32_t C10XFSIZ; /*!< MDMAC Channel 10 Transfer Size Avoidance Register*/ - __I uint32_t C10DSADS; /*!< MDMAC Channel 10 Descriptor Address Avoidance Register*/ - __I uint32_t C10DSNUM; /*!< MDMAC Channel 10 Descriptor Number Avoidance Register*/ - uint32_t RESERVED13[2]; - __I uint32_t C11XFTYP; /*!< MDMAC Channel 11 Number Avoidance Register */ - __I uint32_t C11XFSAD; /*!< MDMAC Channel 11 Transfer Source Address Avoidance Register*/ - __I uint32_t C11XFDAD; /*!< MDMAC Channel 11 Transfer Destination Address Avoidance Register*/ - __I uint32_t C11XFSIZ; /*!< MDMAC Channel 11 Transfer Size Avoidance Register*/ - __I uint32_t C11DSADS; /*!< MDMAC Channel 11 Descriptor Address Avoidance Register*/ - __I uint32_t C11DSNUM; /*!< MDMAC Channel 11 Descriptor Number Avoidance Register*/ - uint32_t RESERVED14[2]; - __I uint32_t C12XFTYP; /*!< MDMAC Channel 12 Number Avoidance Register */ - __I uint32_t C12XFSAD; /*!< MDMAC Channel 12 Transfer Source Address Avoidance Register*/ - __I uint32_t C12XFDAD; /*!< MDMAC Channel 12 Transfer Destination Address Avoidance Register*/ - __I uint32_t C12XFSIZ; /*!< MDMAC Channel 12 Transfer Size Avoidance Register*/ - __I uint32_t C12DSADS; /*!< MDMAC Channel 12 Descriptor Address Avoidance Register*/ - __I uint32_t C12DSNUM; /*!< MDMAC Channel 12 Descriptor Number Avoidance Register*/ - uint32_t RESERVED15[2]; - __I uint32_t C13XFTYP; /*!< MDMAC Channel 13 Number Avoidance Register */ - __I uint32_t C13XFSAD; /*!< MDMAC Channel 13 Transfer Source Address Avoidance Register*/ - __I uint32_t C13XFDAD; /*!< MDMAC Channel 13 Transfer Destination Address Avoidance Register*/ - __I uint32_t C13XFSIZ; /*!< MDMAC Channel 13 Transfer Size Avoidance Register*/ - __I uint32_t C13DSADS; /*!< MDMAC Channel 13 Descriptor Address Avoidance Register*/ - __I uint32_t C13DSNUM; /*!< MDMAC Channel 13 Descriptor Number Avoidance Register*/ - uint32_t RESERVED16[2]; - __I uint32_t C14XFTYP; /*!< MDMAC Channel 14 Number Avoidance Register */ - __I uint32_t C14XFSAD; /*!< MDMAC Channel 14 Transfer Source Address Avoidance Register*/ - __I uint32_t C14XFDAD; /*!< MDMAC Channel 14 Transfer Destination Address Avoidance Register*/ - __I uint32_t C14XFSIZ; /*!< MDMAC Channel 14 Transfer Size Avoidance Register*/ - __I uint32_t C14DSADS; /*!< MDMAC Channel 14 Descriptor Address Avoidance Register*/ - __I uint32_t C14DSNUM; /*!< MDMAC Channel 14 Descriptor Number Avoidance Register*/ - uint32_t RESERVED17[2]; - __I uint32_t C15XFTYP; /*!< MDMAC Channel 15 Number Avoidance Register */ - __I uint32_t C15XFSAD; /*!< MDMAC Channel 15 Transfer Source Address Avoidance Register*/ - __I uint32_t C15XFDAD; /*!< MDMAC Channel 15 Transfer Destination Address Avoidance Register*/ - __I uint32_t C15XFSIZ; /*!< MDMAC Channel 15 Transfer Size Avoidance Register*/ - __I uint32_t C15DSADS; /*!< MDMAC Channel 15 Descriptor Address Avoidance Register*/ - __I uint32_t C15DSNUM; /*!< MDMAC Channel 15 Descriptor Number Avoidance Register*/ - uint32_t RESERVED18[2]; - __I uint32_t C16XFTYP; /*!< MDMAC Channel 16 Number Avoidance Register */ - __I uint32_t C16XFSAD; /*!< MDMAC Channel 16 Transfer Source Address Avoidance Register*/ - __I uint32_t C16XFDAD; /*!< MDMAC Channel 16 Transfer Destination Address Avoidance Register*/ - __I uint32_t C16XFSIZ; /*!< MDMAC Channel 16 Transfer Size Avoidance Register*/ - __I uint32_t C16DSADS; /*!< MDMAC Channel 16 Descriptor Address Avoidance Register*/ - __I uint32_t C16DSNUM; /*!< MDMAC Channel 16 Descriptor Number Avoidance Register*/ - uint32_t RESERVED19[2]; - __I uint32_t C17XFTYP; /*!< MDMAC Channel 17 Number Avoidance Register */ - __I uint32_t C17XFSAD; /*!< MDMAC Channel 17 Transfer Source Address Avoidance Register*/ - __I uint32_t C17XFDAD; /*!< MDMAC Channel 17 Transfer Destination Address Avoidance Register*/ - __I uint32_t C17XFSIZ; /*!< MDMAC Channel 17 Transfer Size Avoidance Register*/ - __I uint32_t C17DSADS; /*!< MDMAC Channel 17 Descriptor Address Avoidance Register*/ - __I uint32_t C17DSNUM; /*!< MDMAC Channel 17 Descriptor Number Avoidance Register*/ - uint32_t RESERVED20[2]; - __I uint32_t C18XFTYP; /*!< MDMAC Channel 18 Number Avoidance Register */ - __I uint32_t C18XFSAD; /*!< MDMAC Channel 18 Transfer Source Address Avoidance Register*/ - __I uint32_t C18XFDAD; /*!< MDMAC Channel 18 Transfer Destination Address Avoidance Register*/ - __I uint32_t C18XFSIZ; /*!< MDMAC Channel 18 Transfer Size Avoidance Register*/ - __I uint32_t C18DSADS; /*!< MDMAC Channel 18 Descriptor Address Avoidance Register*/ - __I uint32_t C18DSNUM; /*!< MDMAC Channel 18 Descriptor Number Avoidance Register*/ - uint32_t RESERVED21[2]; - __I uint32_t C19XFTYP; /*!< MDMAC Channel 19 Number Avoidance Register */ - __I uint32_t C19XFSAD; /*!< MDMAC Channel 19 Transfer Source Address Avoidance Register*/ - __I uint32_t C19XFDAD; /*!< MDMAC Channel 19 Transfer Destination Address Avoidance Register*/ - __I uint32_t C19XFSIZ; /*!< MDMAC Channel 19 Transfer Size Avoidance Register*/ - __I uint32_t C19DSADS; /*!< MDMAC Channel 19 Descriptor Address Avoidance Register*/ - __I uint32_t C19DSNUM; /*!< MDMAC Channel 19 Descriptor Number Avoidance Register*/ - uint32_t RESERVED22[2]; - __I uint32_t C20XFTYP; /*!< MDMAC Channel 20 Number Avoidance Register */ - __I uint32_t C20XFSAD; /*!< MDMAC Channel 20 Transfer Source Address Avoidance Register*/ - __I uint32_t C20XFDAD; /*!< MDMAC Channel 20 Transfer Destination Address Avoidance Register*/ - __I uint32_t C20XFSIZ; /*!< MDMAC Channel 20 Transfer Size Avoidance Register*/ - __I uint32_t C20DSADS; /*!< MDMAC Channel 20 Descriptor Address Avoidance Register*/ - __I uint32_t C20DSNUM; /*!< MDMAC Channel 20 Descriptor Number Avoidance Register*/ - uint32_t RESERVED23[2]; - __I uint32_t C21XFTYP; /*!< MDMAC Channel 21 Number Avoidance Register */ - __I uint32_t C21XFSAD; /*!< MDMAC Channel 21 Transfer Source Address Avoidance Register*/ - __I uint32_t C21XFDAD; /*!< MDMAC Channel 21 Transfer Destination Address Avoidance Register*/ - __I uint32_t C21XFSIZ; /*!< MDMAC Channel 21 Transfer Size Avoidance Register*/ - __I uint32_t C21DSADS; /*!< MDMAC Channel 21 Descriptor Address Avoidance Register*/ - __I uint32_t C21DSNUM; /*!< MDMAC Channel 21 Descriptor Number Avoidance Register*/ - uint32_t RESERVED24[2]; - __I uint32_t C22XFTYP; /*!< MDMAC Channel 22 Number Avoidance Register */ - __I uint32_t C22XFSAD; /*!< MDMAC Channel 22 Transfer Source Address Avoidance Register*/ - __I uint32_t C22XFDAD; /*!< MDMAC Channel 22 Transfer Destination Address Avoidance Register*/ - __I uint32_t C22XFSIZ; /*!< MDMAC Channel 22 Transfer Size Avoidance Register*/ - __I uint32_t C22DSADS; /*!< MDMAC Channel 22 Descriptor Address Avoidance Register*/ - __I uint32_t C22DSNUM; /*!< MDMAC Channel 22 Descriptor Number Avoidance Register*/ - uint32_t RESERVED25[2]; - __I uint32_t C23XFTYP; /*!< MDMAC Channel 23 Number Avoidance Register */ - __I uint32_t C23XFSAD; /*!< MDMAC Channel 23 Transfer Source Address Avoidance Register*/ - __I uint32_t C23XFDAD; /*!< MDMAC Channel 23 Transfer Destination Address Avoidance Register*/ - __I uint32_t C23XFSIZ; /*!< MDMAC Channel 23 Transfer Size Avoidance Register*/ - __I uint32_t C23DSADS; /*!< MDMAC Channel 23 Descriptor Address Avoidance Register*/ - __I uint32_t C23DSNUM; /*!< MDMAC Channel 23 Descriptor Number Avoidance Register*/ - uint32_t RESERVED26[2]; - __I uint32_t C24XFTYP; /*!< MDMAC Channel 24 Number Avoidance Register */ - __I uint32_t C24XFSAD; /*!< MDMAC Channel 24 Transfer Source Address Avoidance Register*/ - __I uint32_t C24XFDAD; /*!< MDMAC Channel 24 Transfer Destination Address Avoidance Register*/ - __I uint32_t C24XFSIZ; /*!< MDMAC Channel 24 Transfer Size Avoidance Register*/ - __I uint32_t C24DSADS; /*!< MDMAC Channel 24 Descriptor Address Avoidance Register*/ - __I uint32_t C24DSNUM; /*!< MDMAC Channel 24 Descriptor Number Avoidance Register*/ - uint32_t RESERVED27[2]; - __I uint32_t C25XFTYP; /*!< MDMAC Channel 25 Number Avoidance Register */ - __I uint32_t C25XFSAD; /*!< MDMAC Channel 25 Transfer Source Address Avoidance Register*/ - __I uint32_t C25XFDAD; /*!< MDMAC Channel 25 Transfer Destination Address Avoidance Register*/ - __I uint32_t C25XFSIZ; /*!< MDMAC Channel 25 Transfer Size Avoidance Register*/ - __I uint32_t C25DSADS; /*!< MDMAC Channel 25 Descriptor Address Avoidance Register*/ - __I uint32_t C25DSNUM; /*!< MDMAC Channel 25 Descriptor Number Avoidance Register*/ - uint32_t RESERVED28[2]; - __I uint32_t C26XFTYP; /*!< MDMAC Channel 26 Number Avoidance Register */ - __I uint32_t C26XFSAD; /*!< MDMAC Channel 26 Transfer Source Address Avoidance Register*/ - __I uint32_t C26XFDAD; /*!< MDMAC Channel 26 Transfer Destination Address Avoidance Register*/ - __I uint32_t C26XFSIZ; /*!< MDMAC Channel 26 Transfer Size Avoidance Register*/ - __I uint32_t C26DSADS; /*!< MDMAC Channel 26 Descriptor Address Avoidance Register*/ - __I uint32_t C26DSNUM; /*!< MDMAC Channel 26 Descriptor Number Avoidance Register*/ - uint32_t RESERVED29[2]; - __I uint32_t C27XFTYP; /*!< MDMAC Channel 27 Number Avoidance Register */ - __I uint32_t C27XFSAD; /*!< MDMAC Channel 27 Transfer Source Address Avoidance Register*/ - __I uint32_t C27XFDAD; /*!< MDMAC Channel 27 Transfer Destination Address Avoidance Register*/ - __I uint32_t C27XFSIZ; /*!< MDMAC Channel 27 Transfer Size Avoidance Register*/ - __I uint32_t C27DSADS; /*!< MDMAC Channel 27 Descriptor Address Avoidance Register*/ - __I uint32_t C27DSNUM; /*!< MDMAC Channel 27 Descriptor Number Avoidance Register*/ - uint32_t RESERVED30[2]; - __I uint32_t C28XFTYP; /*!< MDMAC Channel 28 Number Avoidance Register */ - __I uint32_t C28XFSAD; /*!< MDMAC Channel 28 Transfer Source Address Avoidance Register*/ - __I uint32_t C28XFDAD; /*!< MDMAC Channel 28 Transfer Destination Address Avoidance Register*/ - __I uint32_t C28XFSIZ; /*!< MDMAC Channel 28 Transfer Size Avoidance Register*/ - __I uint32_t C28DSADS; /*!< MDMAC Channel 28 Descriptor Address Avoidance Register*/ - __I uint32_t C28DSNUM; /*!< MDMAC Channel 28 Descriptor Number Avoidance Register*/ - uint32_t RESERVED31[2]; - __I uint32_t C29XFTYP; /*!< MDMAC Channel 29 Number Avoidance Register */ - __I uint32_t C29XFSAD; /*!< MDMAC Channel 29 Transfer Source Address Avoidance Register*/ - __I uint32_t C29XFDAD; /*!< MDMAC Channel 29 Transfer Destination Address Avoidance Register*/ - __I uint32_t C29XFSIZ; /*!< MDMAC Channel 29 Transfer Size Avoidance Register*/ - __I uint32_t C29DSADS; /*!< MDMAC Channel 29 Descriptor Address Avoidance Register*/ - __I uint32_t C29DSNUM; /*!< MDMAC Channel 29 Descriptor Number Avoidance Register*/ - uint32_t RESERVED32[2]; - __I uint32_t C30XFTYP; /*!< MDMAC Channel 30 Number Avoidance Register */ - __I uint32_t C30XFSAD; /*!< MDMAC Channel 30 Transfer Source Address Avoidance Register*/ - __I uint32_t C30XFDAD; /*!< MDMAC Channel 30 Transfer Destination Address Avoidance Register*/ - __I uint32_t C30XFSIZ; /*!< MDMAC Channel 30 Transfer Size Avoidance Register*/ - __I uint32_t C30DSADS; /*!< MDMAC Channel 30 Descriptor Address Avoidance Register*/ - __I uint32_t C30DSNUM; /*!< MDMAC Channel 30 Descriptor Number Avoidance Register*/ - uint32_t RESERVED33[2]; - __I uint32_t C31XFTYP; /*!< MDMAC Channel 31 Number Avoidance Register */ - __I uint32_t C31XFSAD; /*!< MDMAC Channel 31 Transfer Source Address Avoidance Register*/ - __I uint32_t C31XFDAD; /*!< MDMAC Channel 31 Transfer Destination Address Avoidance Register*/ - __I uint32_t C31XFSIZ; /*!< MDMAC Channel 31 Transfer Size Avoidance Register*/ - __I uint32_t C31DSADS; /*!< MDMAC Channel 31 Descriptor Address Avoidance Register*/ - __I uint32_t C31DSNUM; /*!< MDMAC Channel 31 Descriptor Number Avoidance Register*/ - uint32_t RESERVED34[238]; - __IO uint32_t MSK; /*!< MDMAC Mask Register */ -} TSB_MDMA_TypeDef; - -#if defined ( __CC_ARM ) /* RealView Compiler */ -#pragma anon_unions -#elif (defined (__ICCARM__)) /* ICC Compiler */ -#pragma language=extended -#endif - -/** - * @brief ARM Prime Cell PL011 - */ -typedef struct -{ - __IO uint32_t DR; /*!< Data Register */ -union { - __I uint32_t RSR; /*!< Receive Status Register */ - __O uint32_t ECR; /*!< Error Clear Register */ - }; - uint32_t RESERVED0[4]; - __I uint32_t FR; /*!< Flag Register */ - uint32_t RESERVED1; - __IO uint32_t ILPR; /*!< IrDA Low-power Counter register */ - __IO uint32_t BRD; /*!< Integer Baud Rate Register */ - __IO uint32_t FBRD; /*!< Fractional Baud Rate Register */ - __IO uint32_t LCR_H; /*!< Line Control Register */ - __IO uint32_t CR; /*!< Cntrol Register */ - __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select Register */ - __IO uint32_t IMSC; /*!< Interrupt Mask set/Clear Register */ - __I uint32_t RIS; /*!< Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Masked Interrupt Status Register */ - __O uint32_t ICR; /*!< Interrupt Clear Register */ - __IO uint32_t DMACR; /*!< DMA Control Register */ -} TSB_FURT_TypeDef; - -/** - * @brief ADC - */ -typedef struct -{ - __IO uint32_t CR0; /*!< AD Control Register 0 */ - __IO uint32_t CR1; /*!< AD Control Register 1 */ - __I uint32_t ST; /*!< AD Status Register */ - __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ - __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ - __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ - __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ - uint32_t RESERVED0; - __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */ - __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */ - __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */ - __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ - __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ - __IO uint32_t CMPCR2; /*!< AD Conversion Monitor Function setting Register 2*/ - __IO uint32_t CMPCR3; /*!< AD Conversion Monitor Function setting Register 3*/ - __IO uint32_t CMP2; /*!< AD Conversion Result Comparison Register 2 */ - __IO uint32_t CMP3; /*!< AD Conversion Result Comparison Register 3 */ - uint32_t RESERVED1[30]; - __IO uint32_t EXAZSEL; /*!< AIN sampling period selection register */ - __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ - __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ - __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ - __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ - __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ - __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ - __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ - __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ - __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ - __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ - __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ - __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ - __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ - __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ - __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ - __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ - __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ - __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ - __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ - __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ - __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ - __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ - __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ - __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ - uint32_t RESERVED2[8]; - __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */ - __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ - __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ - __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ - __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ - __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ - __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ - __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ - __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ - __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ - __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ - __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ - __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ - __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ - __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ - __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ - __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ - __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ - __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ - __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ - __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ - __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ - __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ - __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ -} TSB_AD_TypeDef; - -/** - * @brief Digital analog converter (DAC) - */ -typedef struct -{ - __IO uint32_t CR; /*!< DAC Control Register */ - __IO uint32_t REG; /*!< DAC output Register */ -} TSB_DA_TypeDef; - -/** - * @brief 16-bit Timer/Event Counter (TB) - */ -typedef struct -{ - __IO uint32_t MOD; /*!< T32A Mode Register */ - uint32_t RESERVED0[15]; - __IO uint32_t RUNA; /*!< T32A Run Register A */ - __IO uint32_t CRA; /*!< T32A Counter Control Register A */ - __IO uint32_t CAPCRA; /*!< T32A Capture Control Register A */ - __O uint32_t OUTCRA0; /*!< T32A Output Control Register A0 */ - __IO uint32_t OUTCRA1; /*!< T32A Output Control Register A1 */ - __IO uint32_t STA; /*!< T32A Status Register A */ - __IO uint32_t IMA; /*!< T32A Interrupt Mask Register A */ - __I uint32_t TMRA; /*!< T32A Counter Capture Register A */ - __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ - __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ - __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ - __I uint32_t CAPA0; /*!< T32A Timer Capture A0 Register */ - __I uint32_t CAPA1; /*!< T32A Timer Cupture A1 Register */ - __IO uint32_t DMAA; /*!< T32A DMA Request Enable Register A */ - uint32_t RESERVED1[2]; - __IO uint32_t RUNB; /*!< T32A Run Register B */ - __IO uint32_t CRB; /*!< T32A Counter Control Register B */ - __IO uint32_t CAPCRB; /*!< T32A Capture Control Register B */ - __O uint32_t OUTCRB0; /*!< T32A Output Control Register B0 */ - __IO uint32_t OUTCRB1; /*!< T32A Output Control Register B1 */ - __IO uint32_t STB; /*!< T32A Status Register B */ - __IO uint32_t IMB; /*!< T32A Interrupt Mask Register B */ - __I uint32_t TMRB; /*!< T32A Counter Capture Register B */ - __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ - __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ - __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ - __I uint32_t CAPB0; /*!< T32A Timer Capture B0 Register */ - __I uint32_t CAPB1; /*!< T32A Timer Capture B1 Register */ - __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ - uint32_t RESERVED2[2]; - __IO uint32_t RUNC; /*!< T32A Run Register C */ - __IO uint32_t CRC; /*!< T32A Counter Control Register C */ - __IO uint32_t CAPCRC; /*!< T32A Capture Control Register C */ - __O uint32_t OUTCRC0; /*!< T32A Output Control Register C0 */ - __IO uint32_t OUTCRC1; /*!< T32A Output Control Register C1 */ - __IO uint32_t STC; /*!< T32A Status Register C */ - __IO uint32_t IMC; /*!< T32A Interrupt Mask Register C */ - __I uint32_t TMRC; /*!< T32A Counter Capture Register C */ - __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ - __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ - __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ - __I uint32_t CAPC0; /*!< T32A Timer Capture C0 Register */ - __I uint32_t CAPC1; /*!< T32A Capture Register C1 */ - __IO uint32_t DMAC; /*!< T32A DMA Request Enable Register C */ - __IO uint32_t PLSCR; /*!< T32A Pulse Count Control Register */ -} TSB_T32A_TypeDef; - -/** - * @brief UART - */ -typedef struct -{ - __IO uint32_t SWRST; /*!< UART Software Reset Register */ - __IO uint32_t CR0; /*!< UART Control Register 0 */ - __IO uint32_t CR1; /*!< UART Control Register 1 */ - __IO uint32_t CLK; /*!< UART Clock Control Register */ - __IO uint32_t BRD; /*!< UART Baud Rate Register */ - __IO uint32_t TRANS; /*!< UART Transfer Enable Register */ - __IO uint32_t DR; /*!< UART Data Register */ - __IO uint32_t SR; /*!< UART Status Register */ - __O uint32_t FIFOCLR; /*!< UART FIFO Clear Register */ - __IO uint32_t ERR; /*!< UART Error Register */ -} TSB_UART_TypeDef; - -/** - * @brief I2C - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control Register 1 */ - __IO uint32_t DBR; /*!< I2C Data Buffer Register */ - __IO uint32_t AR; /*!< I2C Bus address Register */ -union { - __O uint32_t CR2; /*!< I2C Control Register 2 */ - __I uint32_t SR; /*!< I2C Status Register */ - }; - __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ - __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ - __IO uint32_t ST; /*!< Interrupt Register */ - __IO uint32_t OP; /*!< Optiononal Function register */ - __I uint32_t PM; /*!< Bus Monitor register */ - __IO uint32_t AR2; /*!< Second Slave address register */ -} TSB_I2C_TypeDef; - -/** - * @brief Port A - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port A Data Register */ - __IO uint32_t CR; /*!< Port A Output Control Register */ - __IO uint32_t FR1; /*!< Port A Function Register 1 */ - __IO uint32_t FR2; /*!< Port A Function Register 2 */ - __IO uint32_t FR3; /*!< Port A Function Register 3 */ - uint32_t RESERVED0; - __IO uint32_t FR5; /*!< Port A Function Register 5 */ - __IO uint32_t FR6; /*!< Port A Function Register 6 */ - __IO uint32_t FR7; /*!< Port A Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port A Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port A Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port A Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port A Input Control Register */ -} TSB_PA_TypeDef; - -/** - * @brief Port B - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port B Data Register */ - __IO uint32_t CR; /*!< Port B Output Control Register */ - __IO uint32_t FR1; /*!< Port B Function Register 1 */ - __IO uint32_t FR2; /*!< Port B Function Register 2 */ - __IO uint32_t FR3; /*!< Port B Function Register 3 */ - uint32_t RESERVED0; - __IO uint32_t FR5; /*!< Port B Function Register 5 */ - __IO uint32_t FR6; /*!< Port B Function Register 6 */ - uint32_t RESERVED1[2]; - __IO uint32_t OD; /*!< Port B Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port B Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port B Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port B Input Control Register */ -} TSB_PB_TypeDef; - -/** - * @brief Port C - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port C Data Register */ - __IO uint32_t CR; /*!< Port C Output Control Register */ - __IO uint32_t FR1; /*!< Port C Function Register 1 */ - uint32_t RESERVED0; - __IO uint32_t FR3; /*!< Port C Function Register 3 */ - uint32_t RESERVED1; - __IO uint32_t FR5; /*!< Port C Function Register 5 */ - uint32_t RESERVED2[3]; - __IO uint32_t OD; /*!< Port C Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port C Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port C Pull-down Control Register */ - uint32_t RESERVED3; - __IO uint32_t IE; /*!< Port C Input Control Register */ -} TSB_PC_TypeDef; - -/** - * @brief Port D - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port D Data Register */ - __IO uint32_t CR; /*!< Port D Output Control Register */ - __IO uint32_t FR1; /*!< Port D Function Register 1 */ - __IO uint32_t FR2; /*!< Port D Function Register 2 */ - __IO uint32_t FR3; /*!< Port D Function Register 3 */ - __IO uint32_t FR4; /*!< Port D Function Register 4 */ - __IO uint32_t FR5; /*!< Port D Function Register 5 */ - __IO uint32_t FR6; /*!< Port D Function Register 6 */ - __IO uint32_t FR7; /*!< Port D Function Register 7 */ - uint32_t RESERVED0; - __IO uint32_t OD; /*!< Port D Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port D Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port D Pull-down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< Port D Input Control Register */ -} TSB_PD_TypeDef; - -/** - * @brief Port E - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port E Data Register */ - __IO uint32_t CR; /*!< Port E Output Control Register */ - __IO uint32_t FR1; /*!< Port E Function Register 1 */ - __IO uint32_t FR2; /*!< Port E Function Register 2 */ - __IO uint32_t FR3; /*!< Port E Function Register 3 */ - __IO uint32_t FR4; /*!< Port E Function Register 4 */ - __IO uint32_t FR5; /*!< Port E Function Register 5 */ - uint32_t RESERVED0; - __IO uint32_t FR7; /*!< Port E Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port E Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port E Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port E Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port E Input Control Register */ -} TSB_PE_TypeDef; - -/** - * @brief Port F - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port F Data Register */ - __IO uint32_t CR; /*!< Port F Output Control Register */ - __IO uint32_t FR1; /*!< Port F Function Register 1 */ - uint32_t RESERVED0[5]; - __IO uint32_t FR7; /*!< Port F Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port F Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port F Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port F Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port F Input Control Register */ -} TSB_PF_TypeDef; - -/** - * @brief Port G - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port G Data Register */ - __IO uint32_t CR; /*!< Port G Output Control Register */ - __IO uint32_t FR1; /*!< Port G Function Register 1 */ - __IO uint32_t FR2; /*!< Port G Function Register 2 */ - __IO uint32_t FR3; /*!< Port G Function Register 3 */ - __IO uint32_t FR4; /*!< Port G Function Register 4 */ - __IO uint32_t FR5; /*!< Port G Function Register 5 */ - uint32_t RESERVED0; - __IO uint32_t FR7; /*!< Port G Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port G Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port G Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port G Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port G Input Control Register */ -} TSB_PG_TypeDef; - -/** - * @brief Port H - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port H Data Register */ - __IO uint32_t CR; /*!< Port H Output Control Register */ - __IO uint32_t FR1; /*!< Port H Function Register 1 */ - uint32_t RESERVED0; - __IO uint32_t FR3; /*!< Port H Function Register 3 */ - __IO uint32_t FR4; /*!< Port H Function Register 4 */ - __IO uint32_t FR5; /*!< Port H Function Register 5 */ - uint32_t RESERVED1[3]; - __IO uint32_t OD; /*!< Port H Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port H Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port H Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port H Input Control Register */ -} TSB_PH_TypeDef; - -/** - * @brief Port J - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port J Data Register */ - __IO uint32_t CR; /*!< Port J Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port J Function Register 2 */ - __IO uint32_t FR3; /*!< Port J Function Register 3 */ - uint32_t RESERVED1; - __IO uint32_t FR5; /*!< Port J Function Register 5 */ - uint32_t RESERVED2; - __IO uint32_t FR7; /*!< Port J Function Register 7 */ - uint32_t RESERVED3; - __IO uint32_t OD; /*!< Port J Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port J Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port J Pull-down Control Register */ - uint32_t RESERVED4; - __IO uint32_t IE; /*!< Port J Input Control Register */ -} TSB_PJ_TypeDef; - -/** - * @brief Port K - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port K Data Register */ - __IO uint32_t CR; /*!< Port K Output Control Register */ - __IO uint32_t FR1; /*!< Port K Function Register 1 */ - __IO uint32_t FR2; /*!< Port K Function Register 2 */ - __IO uint32_t FR3; /*!< Port K Function Register 3 */ - __IO uint32_t FR4; /*!< Port K Function Register 4 */ - uint32_t RESERVED0; - __IO uint32_t FR6; /*!< Port K Function Register 6 */ - __IO uint32_t FR7; /*!< Port K Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port K Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port K Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port K Pull-up Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port K Input Control Register */ -} TSB_PK_TypeDef; - -/** - * @brief Port L - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port L Data Register */ - __IO uint32_t CR; /*!< Port L Output Control Register */ - __IO uint32_t FR1; /*!< Port L Function Register 1 */ - __IO uint32_t FR2; /*!< Port L Function Register 2 */ - __IO uint32_t FR3; /*!< Port L Function Register 3 */ - uint32_t RESERVED0[2]; - __IO uint32_t FR6; /*!< Port L Function Register 6 */ - __IO uint32_t FR7; /*!< Port L Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port L Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port L Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port L Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port L Input Control Register */ -} TSB_PL_TypeDef; - -/** - * @brief Port M - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port M Data Register */ - __IO uint32_t CR; /*!< Port M Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port M Function Register 2 */ - __IO uint32_t FR3; /*!< Port M Function Register 3 */ - __IO uint32_t FR4; /*!< Port M Function Register 4 */ - __IO uint32_t FR5; /*!< Port M Function Register 5 */ - __IO uint32_t FR6; /*!< Port M Function Register 6 */ - __IO uint32_t FR7; /*!< Port M Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port M Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port M Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port M Pull-up Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port M Input Control Register */ -} TSB_PM_TypeDef; - -/** - * @brief Port N - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port N Data Register */ - __IO uint32_t CR; /*!< Port N Output Control Register */ - uint32_t RESERVED0[8]; - __IO uint32_t OD; /*!< Port N Opend Drain Control Register */ - __IO uint32_t PUP; /*!< Port N Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port N Pull-down Control Register */ - uint32_t RESERVED1; - __IO uint32_t IE; /*!< Port N Input Control Register */ -} TSB_PN_TypeDef; - -/** - * @brief Port P - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port P Data Register */ - __IO uint32_t CR; /*!< Port P Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port P Function Register 2 */ - __IO uint32_t FR3; /*!< Port P Function Register 3 */ - uint32_t RESERVED1; - __IO uint32_t FR5; /*!< Port P Function Register 5 */ - uint32_t RESERVED2[3]; - __IO uint32_t OD; /*!< Port P Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port P Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port P Pull-down Control Register */ - uint32_t RESERVED3; - __IO uint32_t IE; /*!< Port P Input Control Register */ -} TSB_PP_TypeDef; - -/** - * @brief Port R - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port R Data Register */ - __IO uint32_t CR; /*!< Port R Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port R Function Register 2 */ - __IO uint32_t FR3; /*!< Port R Function Register 3 */ - uint32_t RESERVED1[5]; - __IO uint32_t OD; /*!< Port R Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port R Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port R Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port R Input Control Register */ -} TSB_PR_TypeDef; - -/** - * @brief Port T - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port T Data Register */ - __IO uint32_t CR; /*!< Port T Output Control Register */ - __IO uint32_t FR1; /*!< Port T Function Register 1 */ - __IO uint32_t FR2; /*!< Port T Function Register 2 */ - __IO uint32_t FR3; /*!< Port T Function Register 3 */ - uint32_t RESERVED0[2]; - __IO uint32_t FR6; /*!< Port T Function Register 6 */ - __IO uint32_t FR7; /*!< Port T Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port T Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port T Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port T Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port T Input Control Register */ -} TSB_PT_TypeDef; - -/** - * @brief Port U - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port U Data Register */ - __IO uint32_t CR; /*!< Port U Output Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port U Function Register 2 */ - __IO uint32_t FR3; /*!< Port U Function Register 3 */ - uint32_t RESERVED1[3]; - __IO uint32_t FR7; /*!< Port U Function Register 7 */ - uint32_t RESERVED2; - __IO uint32_t OD; /*!< Port U Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port U Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port U Pull-down Control Register */ - uint32_t RESERVED3; - __IO uint32_t IE; /*!< Port U Input Control Register */ -} TSB_PU_TypeDef; - -/** - * @brief Port V - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port V Data Register */ - __IO uint32_t CR; /*!< Port V OutPut Control Register */ - uint32_t RESERVED0; - __IO uint32_t FR2; /*!< Port V Function Register 2 */ - __IO uint32_t FR3; /*!< Port V Function Register 3 */ - __IO uint32_t FR4; /*!< Port V Function Register 4 */ - __IO uint32_t FR5; /*!< Port V Function Register 5 */ - __IO uint32_t FR6; /*!< Port V Function Register 6 */ - __IO uint32_t FR7; /*!< Port V Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port V Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port V Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port V Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port V InPut Control Register */ -} TSB_PV_TypeDef; - -/** - * @brief Port W - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port W Data Register */ - __IO uint32_t CR; /*!< Port W OutPut Control Register */ - uint32_t RESERVED0[2]; - __IO uint32_t FR3; /*!< Port W Function Register 3 */ - __IO uint32_t FR4; /*!< Port W Function Register 4 */ - __IO uint32_t FR5; /*!< Port W Function Register 5 */ - __IO uint32_t FR6; /*!< Port W Function Register 6 */ - __IO uint32_t FR7; /*!< Port W Function Register 7 */ - uint32_t RESERVED1; - __IO uint32_t OD; /*!< Port W Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port W Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port W Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port W InPut Control Register */ -} TSB_PW_TypeDef; - -/** - * @brief Port Y - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Port Y Data Register */ - __IO uint32_t CR; /*!< Port Y OutPut Control Register */ - __IO uint32_t FR1; /*!< Port Y Function Register 1 */ - uint32_t RESERVED0[2]; - __IO uint32_t FR4; /*!< Port Y Function Register 4 */ - uint32_t RESERVED1[4]; - __IO uint32_t OD; /*!< Port Y Open Drain Control Register */ - __IO uint32_t PUP; /*!< Port Y Pull-up Control Register */ - __IO uint32_t PDN; /*!< Port Y Pull-down Control Register */ - uint32_t RESERVED2; - __IO uint32_t IE; /*!< Port Y InPut Control Register */ -} TSB_PY_TypeDef; - -/** - * @brief Internal High-speed Oscillation Adjustment - */ -typedef struct -{ - __IO uint32_t OSCPRO; /*!< TRM Protection Register */ - __IO uint32_t OSCEN; /*!< TRM Enable Register */ - __I uint32_t OSCINIT; /*!< TRM Initial Trimming Level Monitor Register */ - __IO uint32_t OSCSET; /*!< TRM Trimming Level Setting Register */ -} TSB_TRM_TypeDef; - -/** - * @brief Oscillation Frequency Detector (OFD) - */ -typedef struct -{ - __IO uint32_t CR1; /*!< OFD Control Register 1 */ - __IO uint32_t CR2; /*!< OFD Control Register 2 */ - __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ - __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ - __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ - __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ - __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ - __I uint32_t STAT; /*!< OFD Status Register */ - __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */ -} TSB_OFD_TypeDef; - -/** - * @brief Real Time Clock (RTC) - */ -typedef struct -{ - __IO uint8_t SECR; /*!< RTC Sec setting register */ - __IO uint8_t MINR; /*!< RTC Min settging register */ - __IO uint8_t HOURR; /*!< RTC Hour setting register */ - uint8_t RESERVED0; - __IO uint8_t DAYR; /*!< RTC Day setting register */ - __IO uint8_t DATER; /*!< RTC Date setting register */ - __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */ - __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */ - __IO uint8_t PAGER; /*!< RTC Page register */ - uint8_t RESERVED1[3]; - __IO uint8_t RESTR; /*!< RTC Reset register */ - uint8_t RESERVED2; - __IO uint8_t PROTECT; /*!< RTC protect register */ - __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */ - __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */ - __IO uint8_t ADJSIGN; /*!< RTC clock adjust sign register */ -} TSB_RTC_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t EN; /*!< CEC Enable Register */ - __IO uint32_t ADD; /*!< CEC Logical Address Register */ - __O uint32_t RESET; /*!< CEC Software Reset Register */ - __IO uint32_t REN; /*!< CEC Receive Enable Register */ - __I uint32_t RBUF; /*!< CEC Receive Buffer Register */ - __IO uint32_t RCR1; /*!< CEC Receive Control Register 1 */ - __IO uint32_t RCR2; /*!< CEC Receive Control Register 2 */ - __IO uint32_t RCR3; /*!< CEC Receive Control Register 3 */ - __IO uint32_t TEN; /*!< CEC Transmit Enable Register */ - __IO uint32_t TBUF; /*!< CEC Transmit Buffer Register */ - __IO uint32_t TCR; /*!< CEC Transmit Control Register */ - __I uint32_t RSTAT; /*!< CEC Receive Interrupt Status Register */ - __I uint32_t TSTAT; /*!< CEC Transmit Interrupt Status Register */ - __IO uint32_t FSSEL; /*!< CEC sampling clock selection Register */ -} TSB_CEC_TypeDef; - -/** - * @brief Remote Control Signal Preprocessor (RMC) - */ -typedef struct -{ - __IO uint32_t EN; /*!< RMC Enable Register */ - __IO uint32_t REN; /*!< RMC Receive Enable Register */ - __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ - __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ - __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ - __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ - __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ - __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ - __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ - __I uint32_t RSTAT; /*!< RMC Receive Status Register */ - __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ - __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ - __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ - __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */ -} TSB_RMC_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t MDEN; /*!< PMD Enable Register */ - __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ - __IO uint32_t MDCR; /*!< PMD Control Register */ - __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ - __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ - __IO uint32_t RATE; /*!< PWM Frequency Register */ - __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ - __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ - __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ - __IO uint32_t MODESEL; /*!< PMD Mode Select Register */ - __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ - __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ - __O uint32_t EMGREL; /*!< PMD EMG Release Register */ - __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ - __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ - __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ - __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ - __IO uint32_t DTR; /*!< PMD Dead Time Register */ - __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ - __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ - __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ - __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ - __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ - __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ - __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ - __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ - __IO uint32_t VPWMPH; /*!< Phase difference setting of the V-phase PWM */ - __IO uint32_t WPWMPH; /*!< Phase difference setting of the W-phase PWM */ - __IO uint32_t MBUFCR; /*!< Update timing of the triple buffer */ - __IO uint32_t SYNCCR; /*!< Synchronization control between the PMD channel*/ -} TSB_PMD_TypeDef; - -/** - * @brief - */ -typedef struct -{ - __IO uint32_t EN; /*!< Interval Sencing Detector(ISD) */ - __IO uint32_t CLKCR; /*!< Clock Control Register */ - __IO uint32_t OCR0; /*!< Output Control Register 0 */ - __IO uint32_t OCR1; /*!< Output Control Register 1 */ - __IO uint32_t ICR; /*!< Input Control Register */ - __IO uint32_t CR; /*!< Control Register */ - __I uint32_t BR; /*!< Buffer Register */ - __I uint32_t SR; /*!< Status Register */ - __IO uint32_t INTCR; /*!< interrupt Control Register */ -} TSB_ISD_TypeDef; - -/** - * @brief - */ -typedef struct -{ - uint32_t RESERVED0[4]; - __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ - __IO uint32_t SSR; /*!< Flash Security Status Register */ - __O uint32_t KCR; /*!< Flash Key Code Register */ - uint32_t RESERVED1; - __IO uint32_t SR0; /*!< Flash Status Register 0 */ - uint32_t RESERVED2[3]; - __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ - __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ - uint32_t RESERVED3; - __I uint32_t PSR3; /*!< Flash Protect Status Register 3 */ - __I uint32_t PSR4; /*!< Flash Protect Status Register 4 */ - uint32_t RESERVED4; - __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ - uint32_t RESERVED5; - __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ - __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ - uint32_t RESERVED6; - __IO uint32_t PMR3; /*!< Flash Protect Mask Register 3 */ - __IO uint32_t PMR4; /*!< Flash Protect Mask Register 4 */ - uint32_t RESERVED7; - __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ - uint32_t RESERVED8[37]; - __I uint32_t SR1; /*!< Flash Status Register 1 */ - __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ - uint32_t RESERVED9[14]; - __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ - uint32_t RESERVED10; - __IO uint32_t CR; /*!< Flash Control Register */ - __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ - __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ - uint32_t RESERVED11; - __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ -} TSB_FC_TypeDef; - - -/* Memory map */ -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x20000000UL) -#define PERI_BASE (0x40000000UL) - - -#define TSB_DMACA_BASE (PERI_BASE + 0x0000000UL) -#define TSB_DMACB_BASE (PERI_BASE + 0x0001000UL) -#define TSB_SMI0_BASE (PERI_BASE + 0x000C000UL) -#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) -#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) -#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) -#define TSB_TSEL0_BASE (PERI_BASE + 0x00A0400UL) -#define TSB_LTT0_BASE (PERI_BASE + 0x003FF00UL) -#define TSB_TSPI0_BASE (PERI_BASE + 0x006A000UL) -#define TSB_TSPI1_BASE (PERI_BASE + 0x006A400UL) -#define TSB_TSPI2_BASE (PERI_BASE + 0x006A800UL) -#define TSB_TSPI3_BASE (PERI_BASE + 0x006AC00UL) -#define TSB_TSPI4_BASE (PERI_BASE + 0x006B000UL) -#define TSB_TSPI5_BASE (PERI_BASE + 0x006B400UL) -#define TSB_TSPI6_BASE (PERI_BASE + 0x00CB800UL) -#define TSB_TSPI7_BASE (PERI_BASE + 0x00CBC00UL) -#define TSB_TSPI8_BASE (PERI_BASE + 0x00CC000UL) -#define TSB_EXB_BASE (PERI_BASE + 0x0076000UL) -#define TSB_CG_BASE (PERI_BASE + 0x0083000UL) -#define TSB_IB_BASE (PERI_BASE + 0x0083200UL) -#define TSB_IMN_BASE (PERI_BASE + 0x0083300UL) -#define TSB_DNFA_BASE (PERI_BASE + 0x00A0200UL) -#define TSB_DNFB_BASE (PERI_BASE + 0x00A0300UL) -#define TSB_SIWD0_BASE (PERI_BASE + 0x00A0600UL) -#define TSB_NBD_BASE (PERI_BASE + 0x00A2000UL) -#define TSB_MDMAA_BASE (PERI_BASE + 0x00A4000UL) -#define TSB_FURT0_BASE (PERI_BASE + 0x00A8000UL) -#define TSB_FURT1_BASE (PERI_BASE + 0x00A9000UL) -#define TSB_ADA_BASE (PERI_BASE + 0x00BA000UL) -#define TSB_DA0_BASE (PERI_BASE + 0x00BC800UL) -#define TSB_DA1_BASE (PERI_BASE + 0x00BC900UL) -#define TSB_T32A0_BASE (PERI_BASE + 0x00C1000UL) -#define TSB_T32A1_BASE (PERI_BASE + 0x00C1400UL) -#define TSB_T32A2_BASE (PERI_BASE + 0x00C1800UL) -#define TSB_T32A3_BASE (PERI_BASE + 0x00C1C00UL) -#define TSB_T32A4_BASE (PERI_BASE + 0x00C2000UL) -#define TSB_T32A5_BASE (PERI_BASE + 0x00C2400UL) -#define TSB_T32A6_BASE (PERI_BASE + 0x00C2800UL) -#define TSB_T32A7_BASE (PERI_BASE + 0x00C2C00UL) -#define TSB_T32A8_BASE (PERI_BASE + 0x00C3000UL) -#define TSB_T32A9_BASE (PERI_BASE + 0x00C3400UL) -#define TSB_T32A10_BASE (PERI_BASE + 0x00C3800UL) -#define TSB_T32A11_BASE (PERI_BASE + 0x00C3C00UL) -#define TSB_T32A12_BASE (PERI_BASE + 0x00C4000UL) -#define TSB_T32A13_BASE (PERI_BASE + 0x00C4400UL) -#define TSB_UART0_BASE (PERI_BASE + 0x00CE000UL) -#define TSB_UART1_BASE (PERI_BASE + 0x00CE400UL) -#define TSB_UART2_BASE (PERI_BASE + 0x00CE800UL) -#define TSB_UART3_BASE (PERI_BASE + 0x00CEC00UL) -#define TSB_UART4_BASE (PERI_BASE + 0x00CF000UL) -#define TSB_UART5_BASE (PERI_BASE + 0x00CF400UL) -#define TSB_I2C0_BASE (PERI_BASE + 0x00D1000UL) -#define TSB_I2C1_BASE (PERI_BASE + 0x00D2000UL) -#define TSB_I2C2_BASE (PERI_BASE + 0x00D3000UL) -#define TSB_I2C3_BASE (PERI_BASE + 0x00D4000UL) -#define TSB_I2C4_BASE (PERI_BASE + 0x00D5000UL) -#define TSB_PA_BASE (PERI_BASE + 0x00E0000UL) -#define TSB_PB_BASE (PERI_BASE + 0x00E0100UL) -#define TSB_PC_BASE (PERI_BASE + 0x00E0200UL) -#define TSB_PD_BASE (PERI_BASE + 0x00E0300UL) -#define TSB_PE_BASE (PERI_BASE + 0x00E0400UL) -#define TSB_PF_BASE (PERI_BASE + 0x00E0500UL) -#define TSB_PG_BASE (PERI_BASE + 0x00E0600UL) -#define TSB_PH_BASE (PERI_BASE + 0x00E0700UL) -#define TSB_PJ_BASE (PERI_BASE + 0x00E0800UL) -#define TSB_PK_BASE (PERI_BASE + 0x00E0900UL) -#define TSB_PL_BASE (PERI_BASE + 0x00E0A00UL) -#define TSB_PM_BASE (PERI_BASE + 0x00E0B00UL) -#define TSB_PN_BASE (PERI_BASE + 0x00E0C00UL) -#define TSB_PP_BASE (PERI_BASE + 0x00E0D00UL) -#define TSB_PR_BASE (PERI_BASE + 0x00E0E00UL) -#define TSB_PT_BASE (PERI_BASE + 0x00E0F00UL) -#define TSB_PU_BASE (PERI_BASE + 0x00E1000UL) -#define TSB_PV_BASE (PERI_BASE + 0x00E1100UL) -#define TSB_PW_BASE (PERI_BASE + 0x00E1200UL) -#define TSB_PY_BASE (PERI_BASE + 0x00E1300UL) -#define TSB_TRM_BASE (PERI_BASE + 0x00E3100UL) -#define TSB_OFD_BASE (PERI_BASE + 0x00E4000UL) -#define TSB_RTC_BASE (PERI_BASE + 0x00E4800UL) -#define TSB_CEC0_BASE (PERI_BASE + 0x00E8000UL) -#define TSB_RMC0_BASE (PERI_BASE + 0x00E8100UL) -#define TSB_RMC1_BASE (PERI_BASE + 0x00E8200UL) -#define TSB_PMD0_BASE (PERI_BASE + 0x00E9000UL) -#define TSB_ISDA_BASE (PERI_BASE + 0x00F0000UL) -#define TSB_ISDB_BASE (PERI_BASE + 0x00F0100UL) -#define TSB_ISDC_BASE (PERI_BASE + 0x00F0200UL) -#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) - - -/* Peripheral declaration */ -#define TSB_DMACA (( TSB_DMAC_TypeDef *) TSB_DMACA_BASE) -#define TSB_DMACB (( TSB_DMAC_TypeDef *) TSB_DMACB_BASE) -#define TSB_SMI0 (( TSB_SMI_TypeDef *) TSB_SMI0_BASE) -#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) -#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) -#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) -#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) -#define TSB_LTT0 (( TSB_LTT_TypeDef *) TSB_LTT0_BASE) -#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) -#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) -#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) -#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) -#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) -#define TSB_TSPI5 (( TSB_TSPI_TypeDef *) TSB_TSPI5_BASE) -#define TSB_TSPI6 (( TSB_TSPI_TypeDef *) TSB_TSPI6_BASE) -#define TSB_TSPI7 (( TSB_TSPI_TypeDef *) TSB_TSPI7_BASE) -#define TSB_TSPI8 (( TSB_TSPI_TypeDef *) TSB_TSPI8_BASE) -#define TSB_EXB (( TSB_EXB_TypeDef *) TSB_EXB_BASE) -#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) -#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) -#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) -#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) -#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) -#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) -#define TSB_NBD (( TSB_NBD_TypeDef *) TSB_NBD_BASE) -#define TSB_MDMAA (( TSB_MDMA_TypeDef *) TSB_MDMAA_BASE) -#define TSB_FURT0 (( TSB_FURT_TypeDef *) TSB_FURT0_BASE) -#define TSB_FURT1 (( TSB_FURT_TypeDef *) TSB_FURT1_BASE) -#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) -#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) -#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) -#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) -#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) -#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) -#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) -#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) -#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) -#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) -#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) -#define TSB_T32A8 (( TSB_T32A_TypeDef *) TSB_T32A8_BASE) -#define TSB_T32A9 (( TSB_T32A_TypeDef *) TSB_T32A9_BASE) -#define TSB_T32A10 (( TSB_T32A_TypeDef *)TSB_T32A10_BASE) -#define TSB_T32A11 (( TSB_T32A_TypeDef *)TSB_T32A11_BASE) -#define TSB_T32A12 (( TSB_T32A_TypeDef *)TSB_T32A12_BASE) -#define TSB_T32A13 (( TSB_T32A_TypeDef *)TSB_T32A13_BASE) -#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) -#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) -#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) -#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) -#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) -#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) -#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) -#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) -#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) -#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) -#define TSB_I2C4 (( TSB_I2C_TypeDef *) TSB_I2C4_BASE) -#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) -#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) -#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) -#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) -#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) -#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) -#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) -#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) -#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) -#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) -#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) -#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) -#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) -#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) -#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) -#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) -#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) -#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) -#define TSB_PW (( TSB_PW_TypeDef *) TSB_PW_BASE) -#define TSB_PY (( TSB_PY_TypeDef *) TSB_PY_BASE) -#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) -#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) -#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) -#define TSB_CEC0 (( TSB_CEC_TypeDef *) TSB_CEC0_BASE) -#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) -#define TSB_RMC1 (( TSB_RMC_TypeDef *) TSB_RMC1_BASE) -#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) -#define TSB_ISDA (( TSB_ISD_TypeDef *) TSB_ISDA_BASE) -#define TSB_ISDB (( TSB_ISD_TypeDef *) TSB_ISDB_BASE) -#define TSB_ISDC (( TSB_ISD_TypeDef *) TSB_ISDC_BASE) -#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) - - -/* Bit-Band for Device Specific Peripheral Registers */ -#define BITBAND_OFFSET (0x02000000UL) -#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) -#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) - - - -/* DMA Controller */ -#define TSB_DMACA_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,0))) -#define TSB_DMACA_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,1))) -#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,0))) -#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,1))) -#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,0))) -#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,1))) -#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,0))) -#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,1))) -#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,0))) -#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,1))) -#define TSB_DMACA_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,0))) -#define TSB_DMACA_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,1))) -#define TSB_DMACA_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->CONFIGURATION,0))) -#define TSB_DMACA_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,26))) -#define TSB_DMACA_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,27))) -#define TSB_DMACA_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,31))) -#define TSB_DMACA_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,0))) -#define TSB_DMACA_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,14))) -#define TSB_DMACA_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,15))) -#define TSB_DMACA_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,16))) -#define TSB_DMACA_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,17))) -#define TSB_DMACA_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,18))) -#define TSB_DMACA_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,26))) -#define TSB_DMACA_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,27))) -#define TSB_DMACA_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,31))) -#define TSB_DMACA_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,0))) -#define TSB_DMACA_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,14))) -#define TSB_DMACA_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,15))) -#define TSB_DMACA_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,16))) -#define TSB_DMACA_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,17))) -#define TSB_DMACA_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,18))) - -#define TSB_DMACB_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,0))) -#define TSB_DMACB_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,1))) -#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,0))) -#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,1))) -#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,0))) -#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,1))) -#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,0))) -#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,1))) -#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,0))) -#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,1))) -#define TSB_DMACB_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,0))) -#define TSB_DMACB_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,1))) -#define TSB_DMACB_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->CONFIGURATION,0))) -#define TSB_DMACB_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,26))) -#define TSB_DMACB_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,27))) -#define TSB_DMACB_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,31))) -#define TSB_DMACB_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,0))) -#define TSB_DMACB_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,14))) -#define TSB_DMACB_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,15))) -#define TSB_DMACB_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,16))) -#define TSB_DMACB_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,17))) -#define TSB_DMACB_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,18))) -#define TSB_DMACB_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,26))) -#define TSB_DMACB_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,27))) -#define TSB_DMACB_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,31))) -#define TSB_DMACB_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,0))) -#define TSB_DMACB_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,14))) -#define TSB_DMACB_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,15))) -#define TSB_DMACB_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,16))) -#define TSB_DMACB_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,17))) -#define TSB_DMACB_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,18))) - - -/* */ -#define TSB_SMI0_MAP0_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,0))) -#define TSB_SMI0_MAP1_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP1,0))) -#define TSB_SMI0_DACR0_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR0,6))) -#define TSB_SMI0_DACR1_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR1,6))) -#define TSB_SMI0_RACR1_CYCGO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,0))) -#define TSB_SMI0_RACR1_CSNUM (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,1))) -#define TSB_SMI0_RACR1_PBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,4))) -#define TSB_SMI0_RACR1_SBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,5))) -#define TSB_SMI0_INT_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,0))) -#define TSB_SMI0_STAT_CYCDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,0))) -#define TSB_SMI0_STAT_CYCPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,1))) - - - - - -/* TRGSEL */ -#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) -#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) -#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) -#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) -#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) -#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) -#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) -#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) -#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) -#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) -#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) -#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) -#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) -#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) -#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) -#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) -#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) -#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) -#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) -#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) -#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) -#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) -#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) -#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) -#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) -#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) -#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) -#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) -#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) -#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) -#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) -#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) -#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) -#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) -#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) -#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) -#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) -#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) -#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) -#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) -#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) -#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) -#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) -#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) -#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) -#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) -#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) -#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) -#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) -#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) -#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) -#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) -#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) -#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) -#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) -#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) -#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) -#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) -#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) -#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) -#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) -#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) -#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) -#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) -#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) -#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) -#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) -#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) -#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) -#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) -#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) -#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) -#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) -#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) -#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) -#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) -#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) -#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) -#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) -#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) -#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) -#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) -#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) -#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) -#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) -#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) -#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) -#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) -#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) -#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) -#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) -#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) -#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) -#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) -#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) -#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) -#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) -#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) -#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) -#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) -#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) -#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) -#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) -#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) -#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) -#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) -#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) -#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) -#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) -#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) -#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) -#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) -#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) -#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) -#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) -#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) -#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) -#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) -#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) -#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) -#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) -#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) -#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) -#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) -#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) -#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) -#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) -#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) -#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) -#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) -#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) -#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) -#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) -#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) -#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) -#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) -#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) -#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) -#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) -#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) -#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) -#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) -#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) -#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) -#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) -#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) -#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) -#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) -#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) -#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) -#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) -#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) -#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) -#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) -#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) -#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) -#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) -#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) -#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) -#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) -#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) -#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) -#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) -#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) -#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) -#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) -#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) -#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) - - - -/* Serial Interface (TSPI) */ -#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) -#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) -#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) -#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) -#define TSB_TSPI0_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) -#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) -#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) -#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) -#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) -#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) -#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) -#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) -#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16))) -#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) -#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) -#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) -#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) -#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) -#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) -#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) -#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) -#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) -#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) -#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) -#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) -#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) -#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) -#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) -#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) -#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) -#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) -#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) -#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) -#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) -#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) -#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) -#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) - -#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) -#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) -#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) -#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) -#define TSB_TSPI1_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) -#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) -#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) -#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) -#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) -#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) -#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) -#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) -#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16))) -#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) -#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) -#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) -#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) -#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) -#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) -#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) -#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) -#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) -#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) -#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) -#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) -#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) -#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) -#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) -#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) -#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) -#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) -#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) -#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) -#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) -#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) -#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) -#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) - -#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) -#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) -#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) -#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) -#define TSB_TSPI2_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) -#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) -#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) -#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) -#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) -#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) -#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) -#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) -#define TSB_TSPI2_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,16))) -#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) -#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) -#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) -#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) -#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) -#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) -#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) -#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) -#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) -#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) -#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) -#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) -#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) -#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) -#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) -#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) -#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) -#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) -#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) -#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) -#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) -#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) -#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) -#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) - -#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) -#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) -#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) -#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) -#define TSB_TSPI3_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) -#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) -#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) -#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) -#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) -#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) -#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) -#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) -#define TSB_TSPI3_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,16))) -#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) -#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) -#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) -#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) -#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) -#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) -#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) -#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) -#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) -#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) -#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) -#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) -#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) -#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) -#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) -#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) -#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) -#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) -#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) -#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) -#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) -#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) -#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) -#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) - -#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) -#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) -#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) -#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) -#define TSB_TSPI4_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) -#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) -#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) -#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) -#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) -#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) -#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) -#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) -#define TSB_TSPI4_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,16))) -#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) -#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) -#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) -#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) -#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) -#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) -#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) -#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) -#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) -#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) -#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) -#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) -#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) -#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) -#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) -#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) -#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) -#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) -#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) -#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) -#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) -#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) -#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) -#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) - -#define TSB_TSPI5_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR0,0))) -#define TSB_TSPI5_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,12))) -#define TSB_TSPI5_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,13))) -#define TSB_TSPI5_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,14))) -#define TSB_TSPI5_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,15))) -#define TSB_TSPI5_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,0))) -#define TSB_TSPI5_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,1))) -#define TSB_TSPI5_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,2))) -#define TSB_TSPI5_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,4))) -#define TSB_TSPI5_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,5))) -#define TSB_TSPI5_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,6))) -#define TSB_TSPI5_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,7))) -#define TSB_TSPI5_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,16))) -#define TSB_TSPI5_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,21))) -#define TSB_TSPI5_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,0))) -#define TSB_TSPI5_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,1))) -#define TSB_TSPI5_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,14))) -#define TSB_TSPI5_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,15))) -#define TSB_TSPI5_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,16))) -#define TSB_TSPI5_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,17))) -#define TSB_TSPI5_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,18))) -#define TSB_TSPI5_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,19))) -#define TSB_TSPI5_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,31))) -#define TSB_TSPI5_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,0))) -#define TSB_TSPI5_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,1))) -#define TSB_TSPI5_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,4))) -#define TSB_TSPI5_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,5))) -#define TSB_TSPI5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,6))) -#define TSB_TSPI5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,7))) -#define TSB_TSPI5_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,20))) -#define TSB_TSPI5_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,21))) -#define TSB_TSPI5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,22))) -#define TSB_TSPI5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,23))) -#define TSB_TSPI5_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,31))) -#define TSB_TSPI5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,1))) -#define TSB_TSPI5_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,2))) -#define TSB_TSPI5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,3))) - -#define TSB_TSPI6_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR0,0))) -#define TSB_TSPI6_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,12))) -#define TSB_TSPI6_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,13))) -#define TSB_TSPI6_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,14))) -#define TSB_TSPI6_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,15))) -#define TSB_TSPI6_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,0))) -#define TSB_TSPI6_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,1))) -#define TSB_TSPI6_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,2))) -#define TSB_TSPI6_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,4))) -#define TSB_TSPI6_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,5))) -#define TSB_TSPI6_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,6))) -#define TSB_TSPI6_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,7))) -#define TSB_TSPI6_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,16))) -#define TSB_TSPI6_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,21))) -#define TSB_TSPI6_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,0))) -#define TSB_TSPI6_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,1))) -#define TSB_TSPI6_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,14))) -#define TSB_TSPI6_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,15))) -#define TSB_TSPI6_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,16))) -#define TSB_TSPI6_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,17))) -#define TSB_TSPI6_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,18))) -#define TSB_TSPI6_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,19))) -#define TSB_TSPI6_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,31))) -#define TSB_TSPI6_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,0))) -#define TSB_TSPI6_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,1))) -#define TSB_TSPI6_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,4))) -#define TSB_TSPI6_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,5))) -#define TSB_TSPI6_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,6))) -#define TSB_TSPI6_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,7))) -#define TSB_TSPI6_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,20))) -#define TSB_TSPI6_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,21))) -#define TSB_TSPI6_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,22))) -#define TSB_TSPI6_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,23))) -#define TSB_TSPI6_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,31))) -#define TSB_TSPI6_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,1))) -#define TSB_TSPI6_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,2))) -#define TSB_TSPI6_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,3))) - -#define TSB_TSPI7_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR0,0))) -#define TSB_TSPI7_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,12))) -#define TSB_TSPI7_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,13))) -#define TSB_TSPI7_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,14))) -#define TSB_TSPI7_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,15))) -#define TSB_TSPI7_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,0))) -#define TSB_TSPI7_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,1))) -#define TSB_TSPI7_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,2))) -#define TSB_TSPI7_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,4))) -#define TSB_TSPI7_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,5))) -#define TSB_TSPI7_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,6))) -#define TSB_TSPI7_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,7))) -#define TSB_TSPI7_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,16))) -#define TSB_TSPI7_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,21))) -#define TSB_TSPI7_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,0))) -#define TSB_TSPI7_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,1))) -#define TSB_TSPI7_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,14))) -#define TSB_TSPI7_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,15))) -#define TSB_TSPI7_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,16))) -#define TSB_TSPI7_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,17))) -#define TSB_TSPI7_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,18))) -#define TSB_TSPI7_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,19))) -#define TSB_TSPI7_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,31))) -#define TSB_TSPI7_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,0))) -#define TSB_TSPI7_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,1))) -#define TSB_TSPI7_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,4))) -#define TSB_TSPI7_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,5))) -#define TSB_TSPI7_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,6))) -#define TSB_TSPI7_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,7))) -#define TSB_TSPI7_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,20))) -#define TSB_TSPI7_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,21))) -#define TSB_TSPI7_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,22))) -#define TSB_TSPI7_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,23))) -#define TSB_TSPI7_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,31))) -#define TSB_TSPI7_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,1))) -#define TSB_TSPI7_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,2))) -#define TSB_TSPI7_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,3))) - -#define TSB_TSPI8_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR0,0))) -#define TSB_TSPI8_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,12))) -#define TSB_TSPI8_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,13))) -#define TSB_TSPI8_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,14))) -#define TSB_TSPI8_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,15))) -#define TSB_TSPI8_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,0))) -#define TSB_TSPI8_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,1))) -#define TSB_TSPI8_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,2))) -#define TSB_TSPI8_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,4))) -#define TSB_TSPI8_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,5))) -#define TSB_TSPI8_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,6))) -#define TSB_TSPI8_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,7))) -#define TSB_TSPI8_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,16))) -#define TSB_TSPI8_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,21))) -#define TSB_TSPI8_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,0))) -#define TSB_TSPI8_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,1))) -#define TSB_TSPI8_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,14))) -#define TSB_TSPI8_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,15))) -#define TSB_TSPI8_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,16))) -#define TSB_TSPI8_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,17))) -#define TSB_TSPI8_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,18))) -#define TSB_TSPI8_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,19))) -#define TSB_TSPI8_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,31))) -#define TSB_TSPI8_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,0))) -#define TSB_TSPI8_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,1))) -#define TSB_TSPI8_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,4))) -#define TSB_TSPI8_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,5))) -#define TSB_TSPI8_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,6))) -#define TSB_TSPI8_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,7))) -#define TSB_TSPI8_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,20))) -#define TSB_TSPI8_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,21))) -#define TSB_TSPI8_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,22))) -#define TSB_TSPI8_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,23))) -#define TSB_TSPI8_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,31))) -#define TSB_TSPI8_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,1))) -#define TSB_TSPI8_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,2))) -#define TSB_TSPI8_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,3))) - - -/* External Bus Interface(EXB) */ -#define TSB_EXB_MOD_EXBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->MOD,0))) -#define TSB_EXB_CS0_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,0))) -#define TSB_EXB_CS0_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,12))) -#define TSB_EXB_CS0_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,13))) -#define TSB_EXB_CS1_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,0))) -#define TSB_EXB_CS1_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,12))) -#define TSB_EXB_CS1_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,13))) -#define TSB_EXB_CS2_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,0))) -#define TSB_EXB_CS2_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,12))) -#define TSB_EXB_CS2_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,13))) -#define TSB_EXB_CS3_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,0))) -#define TSB_EXB_CS3_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,12))) -#define TSB_EXB_CS3_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,13))) -#define TSB_EXB_CLKCTL_CLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CLKCTL,0))) - - -/* Clock Generator (CG) */ -#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) -#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) -#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) -#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) -#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) -#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) -#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) -#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) -#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) -#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) -#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) -#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) -#define TSB_CG_FSYSMENA_IPMENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,0))) -#define TSB_CG_FSYSMENA_IPMENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,1))) -#define TSB_CG_FSYSMENA_IPMENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,2))) -#define TSB_CG_FSYSMENA_IPMENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,3))) -#define TSB_CG_FSYSMENA_IPMENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,4))) -#define TSB_CG_FSYSMENA_IPMENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,5))) -#define TSB_CG_FSYSMENA_IPMENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,6))) -#define TSB_CG_FSYSMENA_IPMENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,7))) -#define TSB_CG_FSYSMENA_IPMENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,8))) -#define TSB_CG_FSYSMENA_IPMENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,9))) -#define TSB_CG_FSYSMENA_IPMENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,10))) -#define TSB_CG_FSYSMENA_IPMENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,11))) -#define TSB_CG_FSYSMENA_IPMENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,12))) -#define TSB_CG_FSYSMENA_IPMENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,13))) -#define TSB_CG_FSYSMENA_IPMENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,14))) -#define TSB_CG_FSYSMENA_IPMENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,15))) -#define TSB_CG_FSYSMENA_IPMENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,16))) -#define TSB_CG_FSYSMENA_IPMENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,17))) -#define TSB_CG_FSYSMENA_IPMENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,18))) -#define TSB_CG_FSYSMENA_IPMENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,19))) -#define TSB_CG_FSYSMENA_IPMENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,20))) -#define TSB_CG_FSYSMENA_IPMENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,21))) -#define TSB_CG_FSYSMENA_IPMENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,22))) -#define TSB_CG_FSYSMENA_IPMENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,23))) -#define TSB_CG_FSYSMENA_IPMENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,24))) -#define TSB_CG_FSYSMENA_IPMENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,25))) -#define TSB_CG_FSYSMENA_IPMENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,26))) -#define TSB_CG_FSYSMENA_IPMENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,27))) -#define TSB_CG_FSYSMENA_IPMENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,28))) -#define TSB_CG_FSYSMENA_IPMENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,29))) -#define TSB_CG_FSYSMENA_IPMENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,30))) -#define TSB_CG_FSYSMENA_IPMENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,31))) -#define TSB_CG_FSYSMENB_IPMENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,0))) -#define TSB_CG_FSYSMENB_IPMENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,1))) -#define TSB_CG_FSYSMENB_IPMENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,2))) -#define TSB_CG_FSYSMENB_IPMENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,3))) -#define TSB_CG_FSYSMENB_IPMENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,4))) -#define TSB_CG_FSYSMENB_IPMENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,5))) -#define TSB_CG_FSYSMENB_IPMENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,6))) -#define TSB_CG_FSYSMENB_IPMENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,7))) -#define TSB_CG_FSYSMENB_IPMENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,8))) -#define TSB_CG_FSYSMENB_IPMENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,9))) -#define TSB_CG_FSYSMENB_IPMENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,10))) -#define TSB_CG_FSYSMENB_IPMENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,11))) -#define TSB_CG_FSYSMENB_IPMENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,12))) -#define TSB_CG_FSYSMENB_IPMENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,13))) -#define TSB_CG_FSYSMENB_IPMENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,14))) -#define TSB_CG_FSYSMENB_IPMENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,15))) -#define TSB_CG_FSYSMENB_IPMENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,16))) -#define TSB_CG_FSYSMENB_IPMENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,17))) -#define TSB_CG_FSYSMENB_IPMENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,18))) -#define TSB_CG_FSYSMENB_IPMENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,19))) -#define TSB_CG_FSYSMENB_IPMENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,20))) -#define TSB_CG_FSYSMENB_IPMENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,21))) -#define TSB_CG_FSYSMENB_IPMENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,22))) -#define TSB_CG_FSYSMENB_IPMENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,23))) -#define TSB_CG_FSYSMENB_IPMENB24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,24))) -#define TSB_CG_FSYSMENB_IPMENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,28))) -#define TSB_CG_FSYSMENB_IPMENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,29))) -#define TSB_CG_FSYSMENB_IPMENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,30))) -#define TSB_CG_FSYSMENB_IPMENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,31))) -#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) -#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) -#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) -#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) -#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) -#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) -#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) -#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) -#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) -#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) -#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) -#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) -#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) -#define TSB_CG_FCEN_FCIPEN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,23))) -#define TSB_CG_FCEN_FCIPEN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,26))) -#define TSB_CG_FCEN_FCIPEN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,27))) -#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) -#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) -#define TSB_CG_EXTEND2_RSV20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,0))) -#define TSB_CG_EXTEND2_RSV21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,1))) -#define TSB_CG_EXTEND2_RSV22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,2))) - - - -/* Interrupt Monitor Register */ -#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) -#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) -#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) -#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) -#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) -#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) -#define TSB_IMN_FLG1_INT036FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,4))) -#define TSB_IMN_FLG1_INT037FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,5))) -#define TSB_IMN_FLG1_INT038FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,6))) -#define TSB_IMN_FLG1_INT039FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,7))) -#define TSB_IMN_FLG1_INT040FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,8))) -#define TSB_IMN_FLG1_INT041FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,9))) -#define TSB_IMN_FLG1_INT042FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,10))) -#define TSB_IMN_FLG1_INT043FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,11))) -#define TSB_IMN_FLG1_INT044FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,12))) -#define TSB_IMN_FLG1_INT045FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,13))) -#define TSB_IMN_FLG1_INT046FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,14))) -#define TSB_IMN_FLG1_INT047FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,15))) -#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) -#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) -#define TSB_IMN_FLG1_INT050FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,18))) -#define TSB_IMN_FLG1_INT051FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,19))) -#define TSB_IMN_FLG1_INT052FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,20))) -#define TSB_IMN_FLG1_INT053FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,21))) -#define TSB_IMN_FLG1_INT054FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,22))) -#define TSB_IMN_FLG1_INT055FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,23))) -#define TSB_IMN_FLG1_INT056FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,24))) -#define TSB_IMN_FLG1_INT057FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,25))) -#define TSB_IMN_FLG1_INT058FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,26))) -#define TSB_IMN_FLG1_INT059FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,27))) -#define TSB_IMN_FLG1_INT060FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,28))) -#define TSB_IMN_FLG1_INT061FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,29))) -#define TSB_IMN_FLG1_INT062FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,30))) -#define TSB_IMN_FLG1_INT063FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,31))) -#define TSB_IMN_FLG2_INT081FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,17))) -#define TSB_IMN_FLG2_INT082FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,18))) -#define TSB_IMN_FLG2_INT083FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,19))) -#define TSB_IMN_FLG2_INT084FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,20))) -#define TSB_IMN_FLG2_INT085FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,21))) -#define TSB_IMN_FLG2_INT086FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,22))) -#define TSB_IMN_FLG2_INT087FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,23))) -#define TSB_IMN_FLG2_INT088FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,24))) -#define TSB_IMN_FLG2_INT089FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,25))) -#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) -#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) -#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) -#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) -#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) -#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) -#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) -#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) -#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) -#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) -#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) -#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) -#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) -#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) -#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) -#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) -#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) -#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) -#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) -#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) -#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) -#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) -#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) -#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) -#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) -#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) -#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) -#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) -#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) -#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) -#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) -#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) -#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) -#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) -#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) -#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) -#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) -#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) -#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) -#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) -#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) -#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) -#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) -#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) -#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) -#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) -#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) -#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) -#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) -#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) -#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) -#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) -#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) -#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) -#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) -#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) -#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) -#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) -#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) -#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) -#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) -#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) -#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) -#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) -#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) -#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) -#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) -#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) -#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) -#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) -#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) -#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) -#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) -#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) -#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) -#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) -#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) -#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) -#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) -#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) -#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) -#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) -#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) -#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) -#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) -#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) -#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) -#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) -#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) -#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) -#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) -#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) -#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) -#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) -#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) -#define TSB_IMN_FLG5_INT191FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,31))) -#define TSB_IMN_FLG6_INT192FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,0))) -#define TSB_IMN_FLG6_INT193FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,1))) -#define TSB_IMN_FLG6_INT194FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,2))) -#define TSB_IMN_FLG6_INT195FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,3))) -#define TSB_IMN_FLG6_INT196FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,4))) -#define TSB_IMN_FLG6_INT197FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,5))) -#define TSB_IMN_FLG6_INT198FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,6))) -#define TSB_IMN_FLG6_INT199FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,7))) -#define TSB_IMN_FLG6_INT200FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,8))) -#define TSB_IMN_FLG6_INT201FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,9))) -#define TSB_IMN_FLG6_INT202FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,10))) -#define TSB_IMN_FLG6_INT203FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,11))) -#define TSB_IMN_FLG6_INT204FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,12))) -#define TSB_IMN_FLG6_INT205FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,13))) -#define TSB_IMN_FLG6_INT206FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,14))) -#define TSB_IMN_FLG6_INT207FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,15))) -#define TSB_IMN_FLG6_INT208FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,16))) -#define TSB_IMN_FLG6_INT209FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,17))) -#define TSB_IMN_FLG6_INT210FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,18))) -#define TSB_IMN_FLG6_INT211FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,19))) -#define TSB_IMN_FLG6_INT212FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,20))) -#define TSB_IMN_FLG6_INT213FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,21))) -#define TSB_IMN_FLG6_INT214FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,22))) -#define TSB_IMN_FLG6_INT215FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,23))) -#define TSB_IMN_FLG6_INT216FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,24))) -#define TSB_IMN_FLG6_INT217FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,25))) -#define TSB_IMN_FLG6_INT218FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,26))) -#define TSB_IMN_FLG6_INT219FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,27))) -#define TSB_IMN_FLG6_INT220FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,28))) -#define TSB_IMN_FLG6_INT221FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,29))) -#define TSB_IMN_FLG6_INT222FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,30))) -#define TSB_IMN_FLG6_INT223FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,31))) -#define TSB_IMN_FLG7_INT224FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,0))) -#define TSB_IMN_FLG7_INT225FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,1))) -#define TSB_IMN_FLG7_INT226FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,2))) -#define TSB_IMN_FLG7_INT227FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,3))) -#define TSB_IMN_FLG7_INT228FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,4))) -#define TSB_IMN_FLG7_INT229FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,5))) -#define TSB_IMN_FLG7_INT230FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,6))) -#define TSB_IMN_FLG7_INT231FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,7))) -#define TSB_IMN_FLG7_INT232FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,8))) -#define TSB_IMN_FLG7_INT233FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,9))) -#define TSB_IMN_FLG7_INT234FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,10))) -#define TSB_IMN_FLG7_INT235FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,11))) - - -/* DNF */ -#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) -#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) -#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) -#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) -#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) -#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) -#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) -#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) -#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) -#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) -#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) -#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) -#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) -#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) -#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) -#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) - -#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) -#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) -#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) -#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) -#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) -#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) -#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) -#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) -#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) -#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) -#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) -#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) -#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) -#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) -#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) -#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) - - -/* Watchdog Timer (WD) */ -#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) -#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) -#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) -#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) - - -/* NBD */ -#define TSB_NBD_CR0_NBDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_NBD->CR0,0))) - - -/* Malti Porpose Direct Memory Accsess(MDMA) */ -#define TSB_MDMAA_XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,16))) -#define TSB_MDMAA_XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,24))) -#define TSB_MDMAA_DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->DSNUM,8))) -#define TSB_MDMAA_C00XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,16))) -#define TSB_MDMAA_C00XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,24))) -#define TSB_MDMAA_C00DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00DSNUM,8))) -#define TSB_MDMAA_C01XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,16))) -#define TSB_MDMAA_C01XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,24))) -#define TSB_MDMAA_C01DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01DSNUM,8))) -#define TSB_MDMAA_C02XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,16))) -#define TSB_MDMAA_C02XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,24))) -#define TSB_MDMAA_C02DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02DSNUM,8))) -#define TSB_MDMAA_C03XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,16))) -#define TSB_MDMAA_C03XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,24))) -#define TSB_MDMAA_C03DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03DSNUM,8))) -#define TSB_MDMAA_C04XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,16))) -#define TSB_MDMAA_C04XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,24))) -#define TSB_MDMAA_C04DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04DSNUM,8))) -#define TSB_MDMAA_C05XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,16))) -#define TSB_MDMAA_C05XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,24))) -#define TSB_MDMAA_C05DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05DSNUM,8))) -#define TSB_MDMAA_C06XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,16))) -#define TSB_MDMAA_C06XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,24))) -#define TSB_MDMAA_C06DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06DSNUM,8))) -#define TSB_MDMAA_C07XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,16))) -#define TSB_MDMAA_C07XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,24))) -#define TSB_MDMAA_C07DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07DSNUM,8))) -#define TSB_MDMAA_C08XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,16))) -#define TSB_MDMAA_C08XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,24))) -#define TSB_MDMAA_C08DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08DSNUM,8))) -#define TSB_MDMAA_C09XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,16))) -#define TSB_MDMAA_C09XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,24))) -#define TSB_MDMAA_C09DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09DSNUM,8))) -#define TSB_MDMAA_C10XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,16))) -#define TSB_MDMAA_C10XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,24))) -#define TSB_MDMAA_C10DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10DSNUM,8))) -#define TSB_MDMAA_C11XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,16))) -#define TSB_MDMAA_C11XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,24))) -#define TSB_MDMAA_C11DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11DSNUM,8))) -#define TSB_MDMAA_C12XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,16))) -#define TSB_MDMAA_C12XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,24))) -#define TSB_MDMAA_C12DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12DSNUM,8))) -#define TSB_MDMAA_C13XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,16))) -#define TSB_MDMAA_C13XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,24))) -#define TSB_MDMAA_C13DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13DSNUM,8))) -#define TSB_MDMAA_C14XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,16))) -#define TSB_MDMAA_C14XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,24))) -#define TSB_MDMAA_C14DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14DSNUM,8))) -#define TSB_MDMAA_C15XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,16))) -#define TSB_MDMAA_C15XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,24))) -#define TSB_MDMAA_C15DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15DSNUM,8))) -#define TSB_MDMAA_C16XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,16))) -#define TSB_MDMAA_C16XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,24))) -#define TSB_MDMAA_C16DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16DSNUM,8))) -#define TSB_MDMAA_C17XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,16))) -#define TSB_MDMAA_C17XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,24))) -#define TSB_MDMAA_C17DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17DSNUM,8))) -#define TSB_MDMAA_C18XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,16))) -#define TSB_MDMAA_C18XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,24))) -#define TSB_MDMAA_C18DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18DSNUM,8))) -#define TSB_MDMAA_C19XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,16))) -#define TSB_MDMAA_C19XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,24))) -#define TSB_MDMAA_C19DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19DSNUM,8))) -#define TSB_MDMAA_C20XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,16))) -#define TSB_MDMAA_C20XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,24))) -#define TSB_MDMAA_C20DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20DSNUM,8))) -#define TSB_MDMAA_C21XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,16))) -#define TSB_MDMAA_C21XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,24))) -#define TSB_MDMAA_C21DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21DSNUM,8))) -#define TSB_MDMAA_C22XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,16))) -#define TSB_MDMAA_C22XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,24))) -#define TSB_MDMAA_C22DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22DSNUM,8))) -#define TSB_MDMAA_C23XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,16))) -#define TSB_MDMAA_C23XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,24))) -#define TSB_MDMAA_C23DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23DSNUM,8))) -#define TSB_MDMAA_C24XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,16))) -#define TSB_MDMAA_C24XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,24))) -#define TSB_MDMAA_C24DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24DSNUM,8))) -#define TSB_MDMAA_C25XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,16))) -#define TSB_MDMAA_C25XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,24))) -#define TSB_MDMAA_C25DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25DSNUM,8))) -#define TSB_MDMAA_C26XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,16))) -#define TSB_MDMAA_C26XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,24))) -#define TSB_MDMAA_C26DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26DSNUM,8))) -#define TSB_MDMAA_C27XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,16))) -#define TSB_MDMAA_C27XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,24))) -#define TSB_MDMAA_C27DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27DSNUM,8))) -#define TSB_MDMAA_C28XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,16))) -#define TSB_MDMAA_C28XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,24))) -#define TSB_MDMAA_C28DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28DSNUM,8))) -#define TSB_MDMAA_C29XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,16))) -#define TSB_MDMAA_C29XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,24))) -#define TSB_MDMAA_C29DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29DSNUM,8))) -#define TSB_MDMAA_C30XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,16))) -#define TSB_MDMAA_C30XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,24))) -#define TSB_MDMAA_C30DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30DSNUM,8))) -#define TSB_MDMAA_C31XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,16))) -#define TSB_MDMAA_C31XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,24))) -#define TSB_MDMAA_C31DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31DSNUM,8))) -#define TSB_MDMAA_MSK_MSK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,0))) -#define TSB_MDMAA_MSK_MSK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,1))) -#define TSB_MDMAA_MSK_MSK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,2))) -#define TSB_MDMAA_MSK_MSK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,3))) -#define TSB_MDMAA_MSK_MSK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,4))) -#define TSB_MDMAA_MSK_MSK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,5))) -#define TSB_MDMAA_MSK_MSK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,6))) -#define TSB_MDMAA_MSK_MSK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,7))) -#define TSB_MDMAA_MSK_MSK8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,8))) -#define TSB_MDMAA_MSK_MSK9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,9))) -#define TSB_MDMAA_MSK_MSK10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,10))) -#define TSB_MDMAA_MSK_MSK11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,11))) -#define TSB_MDMAA_MSK_MSK12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,12))) -#define TSB_MDMAA_MSK_MSK13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,13))) -#define TSB_MDMAA_MSK_MSK14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,14))) -#define TSB_MDMAA_MSK_MSK15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,15))) -#define TSB_MDMAA_MSK_MSK16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,16))) -#define TSB_MDMAA_MSK_MSK17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,17))) -#define TSB_MDMAA_MSK_MSK18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,18))) -#define TSB_MDMAA_MSK_MSK19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,19))) -#define TSB_MDMAA_MSK_MSK20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,20))) -#define TSB_MDMAA_MSK_MSK21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,21))) -#define TSB_MDMAA_MSK_MSK22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,22))) -#define TSB_MDMAA_MSK_MSK23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,23))) -#define TSB_MDMAA_MSK_MSK24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,24))) -#define TSB_MDMAA_MSK_MSK25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,25))) -#define TSB_MDMAA_MSK_MSK26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,26))) -#define TSB_MDMAA_MSK_MSK27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,27))) -#define TSB_MDMAA_MSK_MSK28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,28))) -#define TSB_MDMAA_MSK_MSK29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,29))) -#define TSB_MDMAA_MSK_MSK30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,30))) -#define TSB_MDMAA_MSK_MSK31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,31))) - - -/* ARM Prime Cell PL011 */ -#define TSB_FURT0_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,8))) -#define TSB_FURT0_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,9))) -#define TSB_FURT0_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,10))) -#define TSB_FURT0_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,11))) -#define TSB_FURT0_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,0))) -#define TSB_FURT0_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,1))) -#define TSB_FURT0_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,2))) -#define TSB_FURT0_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,3))) -#define TSB_FURT0_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,0))) -#define TSB_FURT0_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,3))) -#define TSB_FURT0_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,4))) -#define TSB_FURT0_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,5))) -#define TSB_FURT0_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,6))) -#define TSB_FURT0_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,7))) -#define TSB_FURT0_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,0))) -#define TSB_FURT0_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,1))) -#define TSB_FURT0_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,2))) -#define TSB_FURT0_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,3))) -#define TSB_FURT0_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,4))) -#define TSB_FURT0_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,7))) -#define TSB_FURT0_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,0))) -#define TSB_FURT0_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,1))) -#define TSB_FURT0_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,2))) -#define TSB_FURT0_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,8))) -#define TSB_FURT0_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,9))) -#define TSB_FURT0_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,14))) -#define TSB_FURT0_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,15))) -#define TSB_FURT0_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,4))) -#define TSB_FURT0_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,5))) -#define TSB_FURT0_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,6))) -#define TSB_FURT0_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,7))) -#define TSB_FURT0_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,8))) -#define TSB_FURT0_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,9))) -#define TSB_FURT0_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,10))) -#define TSB_FURT0_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,4))) -#define TSB_FURT0_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,5))) -#define TSB_FURT0_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,6))) -#define TSB_FURT0_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,7))) -#define TSB_FURT0_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,8))) -#define TSB_FURT0_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,9))) -#define TSB_FURT0_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,10))) -#define TSB_FURT0_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,4))) -#define TSB_FURT0_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,5))) -#define TSB_FURT0_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,6))) -#define TSB_FURT0_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,7))) -#define TSB_FURT0_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,8))) -#define TSB_FURT0_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,9))) -#define TSB_FURT0_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,10))) -#define TSB_FURT0_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,4))) -#define TSB_FURT0_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,5))) -#define TSB_FURT0_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,6))) -#define TSB_FURT0_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,7))) -#define TSB_FURT0_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,8))) -#define TSB_FURT0_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,9))) -#define TSB_FURT0_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,10))) -#define TSB_FURT0_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,0))) -#define TSB_FURT0_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,1))) -#define TSB_FURT0_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,2))) - -#define TSB_FURT1_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,8))) -#define TSB_FURT1_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,9))) -#define TSB_FURT1_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,10))) -#define TSB_FURT1_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,11))) -#define TSB_FURT1_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,0))) -#define TSB_FURT1_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,1))) -#define TSB_FURT1_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,2))) -#define TSB_FURT1_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,3))) -#define TSB_FURT1_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,0))) -#define TSB_FURT1_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,3))) -#define TSB_FURT1_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,4))) -#define TSB_FURT1_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,5))) -#define TSB_FURT1_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,6))) -#define TSB_FURT1_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,7))) -#define TSB_FURT1_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,0))) -#define TSB_FURT1_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,1))) -#define TSB_FURT1_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,2))) -#define TSB_FURT1_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,3))) -#define TSB_FURT1_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,4))) -#define TSB_FURT1_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,7))) -#define TSB_FURT1_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,0))) -#define TSB_FURT1_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,1))) -#define TSB_FURT1_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,2))) -#define TSB_FURT1_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,8))) -#define TSB_FURT1_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,9))) -#define TSB_FURT1_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,14))) -#define TSB_FURT1_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,15))) -#define TSB_FURT1_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,4))) -#define TSB_FURT1_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,5))) -#define TSB_FURT1_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,6))) -#define TSB_FURT1_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,7))) -#define TSB_FURT1_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,8))) -#define TSB_FURT1_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,9))) -#define TSB_FURT1_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,10))) -#define TSB_FURT1_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,4))) -#define TSB_FURT1_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,5))) -#define TSB_FURT1_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,6))) -#define TSB_FURT1_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,7))) -#define TSB_FURT1_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,8))) -#define TSB_FURT1_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,9))) -#define TSB_FURT1_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,10))) -#define TSB_FURT1_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,4))) -#define TSB_FURT1_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,5))) -#define TSB_FURT1_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,6))) -#define TSB_FURT1_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,7))) -#define TSB_FURT1_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,8))) -#define TSB_FURT1_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,9))) -#define TSB_FURT1_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,10))) -#define TSB_FURT1_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,4))) -#define TSB_FURT1_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,5))) -#define TSB_FURT1_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,6))) -#define TSB_FURT1_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,7))) -#define TSB_FURT1_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,8))) -#define TSB_FURT1_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,9))) -#define TSB_FURT1_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,10))) -#define TSB_FURT1_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,0))) -#define TSB_FURT1_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,1))) -#define TSB_FURT1_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,2))) - - -/* ADC */ -#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) -#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) -#define TSB_ADA_CR0_HPSGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,2))) -#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) -#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) -#define TSB_ADA_CR1_HPTRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,1))) -#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) -#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) -#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) -#define TSB_ADA_CR1_HPDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,7))) -#define TSB_ADA_ST_HPF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) -#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) -#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) -#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) -#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) -#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) -#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) -#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) -#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) -#define TSB_ADA_CMPEN_CMP2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,2))) -#define TSB_ADA_CMPEN_CMP3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,3))) -#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) -#define TSB_ADA_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) -#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) -#define TSB_ADA_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) -#define TSB_ADA_CMPCR2_ADBIG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR2,5))) -#define TSB_ADA_CMPCR2_CMPCND2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR2,6))) -#define TSB_ADA_CMPCR3_ADBIG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR3,5))) -#define TSB_ADA_CMPCR3_CMPCND3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR3,6))) -#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) -#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) -#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) -#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) -#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) -#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) -#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) -#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) -#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) -#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) -#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) -#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) -#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) -#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) -#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) -#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) -#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) -#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) -#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) -#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) -#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) -#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) -#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) -#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) -#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) -#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) -#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) -#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) -#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) -#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) -#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) -#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) -#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) -#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) -#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) -#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) -#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) -#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) -#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) -#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) -#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) -#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) -#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) -#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) -#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) -#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) -#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) -#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) -#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) -#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) -#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) -#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) -#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) -#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) -#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) -#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) -#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) -#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) -#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) -#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) -#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) -#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) -#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) -#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) -#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) -#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) -#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) -#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) -#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) -#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) -#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) -#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) -#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) -#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) -#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) -#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) -#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) -#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) -#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) -#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) -#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) -#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) -#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) -#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) -#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) -#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) -#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) -#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) -#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) -#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) -#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) -#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) -#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) -#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) -#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) -#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) -#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) -#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) -#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) -#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) -#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) -#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) -#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) -#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) -#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) -#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) -#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) -#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) -#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) -#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) -#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) -#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) -#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) -#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) -#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) -#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) -#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) -#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) -#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) -#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) - - -/* Digital analog converter (DAC) */ -#define TSB_DA0_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CR,0))) - -#define TSB_DA1_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CR,0))) - - -/* 16-bit Timer/Event Counter (TB) */ -#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) -#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) -#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) -#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) -#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) -#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) -#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) -#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) -#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) -#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) -#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) -#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) -#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) -#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) -#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) -#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) -#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) -#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) -#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) -#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) -#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) -#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) -#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) -#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) -#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) -#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) -#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) -#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) -#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) -#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) -#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) -#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) -#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) -#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) -#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) -#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) -#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) -#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) -#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) -#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) -#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) -#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) -#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) -#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) -#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) -#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) -#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) -#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) -#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) -#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) -#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) -#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) -#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) -#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) - -#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) -#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) -#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) -#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) -#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) -#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) -#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) -#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) -#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) -#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) -#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) -#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) -#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) -#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) -#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) -#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) -#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) -#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) -#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) -#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) -#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) -#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) -#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) -#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) -#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) -#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) -#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) -#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) -#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) -#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) -#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) -#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) -#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) -#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) -#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) -#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) -#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) -#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) -#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) -#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) -#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) -#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) -#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) -#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) -#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) -#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) -#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) -#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) -#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) -#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) -#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) -#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) -#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) -#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) - -#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) -#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) -#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) -#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) -#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) -#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) -#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) -#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) -#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) -#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) -#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) -#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) -#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) -#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) -#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) -#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) -#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) -#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) -#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) -#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) -#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) -#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) -#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) -#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) -#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) -#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) -#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) -#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) -#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) -#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) -#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) -#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) -#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) -#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) -#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) -#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) -#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) -#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) -#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) -#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) -#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) -#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) -#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) -#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) -#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) -#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) -#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) -#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) -#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) -#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) -#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) -#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) -#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) -#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) - -#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) -#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) -#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) -#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) -#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) -#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) -#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) -#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) -#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) -#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) -#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) -#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) -#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) -#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) -#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) -#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) -#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) -#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) -#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) -#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) -#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) -#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) -#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) -#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) -#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) -#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) -#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) -#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) -#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) -#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) -#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) -#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) -#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) -#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) -#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) -#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) -#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) -#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) -#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) -#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) -#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) -#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) -#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) -#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) -#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) -#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) -#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) -#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) -#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) -#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) -#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) -#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) -#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) -#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) - -#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) -#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) -#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) -#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) -#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) -#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) -#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) -#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) -#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) -#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) -#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) -#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) -#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) -#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) -#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) -#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) -#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) -#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) -#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) -#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) -#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) -#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) -#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) -#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) -#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) -#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) -#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) -#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) -#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) -#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) -#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) -#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) -#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) -#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) -#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) -#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) -#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) -#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) -#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) -#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) -#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) -#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) -#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) -#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) -#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) -#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) -#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) -#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) -#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) -#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) -#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) -#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) -#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) -#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) - -#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) -#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) -#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) -#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) -#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) -#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) -#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) -#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) -#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) -#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) -#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) -#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) -#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) -#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) -#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) -#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) -#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) -#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) -#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) -#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) -#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) -#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) -#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) -#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) -#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) -#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) -#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) -#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) -#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) -#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) -#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) -#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) -#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) -#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) -#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) -#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) -#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) -#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) -#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) -#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) -#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) -#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) -#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) -#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) -#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) -#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) -#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) -#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) -#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) -#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) -#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) -#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) -#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) -#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) - -#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) -#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) -#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) -#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) -#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) -#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) -#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) -#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) -#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) -#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) -#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) -#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) -#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) -#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) -#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) -#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) -#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) -#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) -#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) -#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) -#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) -#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) -#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) -#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) -#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) -#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) -#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) -#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) -#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) -#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) -#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) -#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) -#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) -#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) -#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) -#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) -#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) -#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) -#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) -#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) -#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) -#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) -#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) -#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) -#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) -#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) -#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) -#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) -#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) -#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) -#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) -#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) -#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) -#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) - -#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) -#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) -#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) -#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) -#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) -#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) -#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) -#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) -#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) -#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) -#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) -#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) -#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) -#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) -#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) -#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) -#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) -#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) -#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) -#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) -#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) -#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) -#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) -#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) -#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) -#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) -#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) -#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) -#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) -#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) -#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) -#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) -#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) -#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) -#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) -#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) -#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) -#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) -#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) -#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) -#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) -#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) -#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) -#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) -#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) -#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) -#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) -#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) -#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) -#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) -#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) -#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) -#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) -#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) - -#define TSB_T32A8_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,0))) -#define TSB_T32A8_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,1))) -#define TSB_T32A8_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,0))) -#define TSB_T32A8_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,1))) -#define TSB_T32A8_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,2))) -#define TSB_T32A8_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,4))) -#define TSB_T32A8_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRA,20))) -#define TSB_T32A8_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,0))) -#define TSB_T32A8_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,1))) -#define TSB_T32A8_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,2))) -#define TSB_T32A8_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,3))) -#define TSB_T32A8_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,0))) -#define TSB_T32A8_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,1))) -#define TSB_T32A8_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,2))) -#define TSB_T32A8_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,3))) -#define TSB_T32A8_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,0))) -#define TSB_T32A8_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,1))) -#define TSB_T32A8_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,2))) -#define TSB_T32A8_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,0))) -#define TSB_T32A8_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,1))) -#define TSB_T32A8_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,2))) -#define TSB_T32A8_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,4))) -#define TSB_T32A8_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRB,20))) -#define TSB_T32A8_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,0))) -#define TSB_T32A8_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,1))) -#define TSB_T32A8_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,2))) -#define TSB_T32A8_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,3))) -#define TSB_T32A8_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,0))) -#define TSB_T32A8_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,1))) -#define TSB_T32A8_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,2))) -#define TSB_T32A8_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,3))) -#define TSB_T32A8_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,0))) -#define TSB_T32A8_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,1))) -#define TSB_T32A8_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,2))) -#define TSB_T32A8_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,0))) -#define TSB_T32A8_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,1))) -#define TSB_T32A8_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,2))) -#define TSB_T32A8_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,4))) -#define TSB_T32A8_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRC,20))) -#define TSB_T32A8_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,0))) -#define TSB_T32A8_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,1))) -#define TSB_T32A8_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,2))) -#define TSB_T32A8_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,3))) -#define TSB_T32A8_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,4))) -#define TSB_T32A8_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,0))) -#define TSB_T32A8_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,1))) -#define TSB_T32A8_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,2))) -#define TSB_T32A8_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,3))) -#define TSB_T32A8_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,4))) -#define TSB_T32A8_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,0))) -#define TSB_T32A8_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,1))) -#define TSB_T32A8_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,2))) -#define TSB_T32A8_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,0))) -#define TSB_T32A8_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,1))) - -#define TSB_T32A9_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,0))) -#define TSB_T32A9_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,1))) -#define TSB_T32A9_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,0))) -#define TSB_T32A9_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,1))) -#define TSB_T32A9_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,2))) -#define TSB_T32A9_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,4))) -#define TSB_T32A9_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRA,20))) -#define TSB_T32A9_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,0))) -#define TSB_T32A9_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,1))) -#define TSB_T32A9_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,2))) -#define TSB_T32A9_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,3))) -#define TSB_T32A9_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,0))) -#define TSB_T32A9_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,1))) -#define TSB_T32A9_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,2))) -#define TSB_T32A9_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,3))) -#define TSB_T32A9_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,0))) -#define TSB_T32A9_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,1))) -#define TSB_T32A9_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,2))) -#define TSB_T32A9_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,0))) -#define TSB_T32A9_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,1))) -#define TSB_T32A9_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,2))) -#define TSB_T32A9_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,4))) -#define TSB_T32A9_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRB,20))) -#define TSB_T32A9_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,0))) -#define TSB_T32A9_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,1))) -#define TSB_T32A9_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,2))) -#define TSB_T32A9_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,3))) -#define TSB_T32A9_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,0))) -#define TSB_T32A9_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,1))) -#define TSB_T32A9_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,2))) -#define TSB_T32A9_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,3))) -#define TSB_T32A9_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,0))) -#define TSB_T32A9_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,1))) -#define TSB_T32A9_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,2))) -#define TSB_T32A9_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,0))) -#define TSB_T32A9_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,1))) -#define TSB_T32A9_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,2))) -#define TSB_T32A9_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,4))) -#define TSB_T32A9_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRC,20))) -#define TSB_T32A9_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,0))) -#define TSB_T32A9_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,1))) -#define TSB_T32A9_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,2))) -#define TSB_T32A9_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,3))) -#define TSB_T32A9_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,4))) -#define TSB_T32A9_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,0))) -#define TSB_T32A9_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,1))) -#define TSB_T32A9_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,2))) -#define TSB_T32A9_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,3))) -#define TSB_T32A9_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,4))) -#define TSB_T32A9_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,0))) -#define TSB_T32A9_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,1))) -#define TSB_T32A9_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,2))) -#define TSB_T32A9_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,0))) -#define TSB_T32A9_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,1))) - -#define TSB_T32A10_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,0))) -#define TSB_T32A10_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,1))) -#define TSB_T32A10_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,0))) -#define TSB_T32A10_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,1))) -#define TSB_T32A10_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,2))) -#define TSB_T32A10_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,4))) -#define TSB_T32A10_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRA,20))) -#define TSB_T32A10_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,0))) -#define TSB_T32A10_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,1))) -#define TSB_T32A10_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,2))) -#define TSB_T32A10_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,3))) -#define TSB_T32A10_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,0))) -#define TSB_T32A10_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,1))) -#define TSB_T32A10_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,2))) -#define TSB_T32A10_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,3))) -#define TSB_T32A10_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,0))) -#define TSB_T32A10_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,1))) -#define TSB_T32A10_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,2))) -#define TSB_T32A10_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,0))) -#define TSB_T32A10_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,1))) -#define TSB_T32A10_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,2))) -#define TSB_T32A10_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,4))) -#define TSB_T32A10_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRB,20))) -#define TSB_T32A10_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,0))) -#define TSB_T32A10_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,1))) -#define TSB_T32A10_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,2))) -#define TSB_T32A10_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,3))) -#define TSB_T32A10_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,0))) -#define TSB_T32A10_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,1))) -#define TSB_T32A10_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,2))) -#define TSB_T32A10_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,3))) -#define TSB_T32A10_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,0))) -#define TSB_T32A10_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,1))) -#define TSB_T32A10_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,2))) -#define TSB_T32A10_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,0))) -#define TSB_T32A10_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,1))) -#define TSB_T32A10_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,2))) -#define TSB_T32A10_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,4))) -#define TSB_T32A10_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRC,20))) -#define TSB_T32A10_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,0))) -#define TSB_T32A10_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,1))) -#define TSB_T32A10_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,2))) -#define TSB_T32A10_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,3))) -#define TSB_T32A10_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,4))) -#define TSB_T32A10_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,0))) -#define TSB_T32A10_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,1))) -#define TSB_T32A10_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,2))) -#define TSB_T32A10_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,3))) -#define TSB_T32A10_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,4))) -#define TSB_T32A10_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,0))) -#define TSB_T32A10_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,1))) -#define TSB_T32A10_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,2))) -#define TSB_T32A10_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,0))) -#define TSB_T32A10_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,1))) - -#define TSB_T32A11_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,0))) -#define TSB_T32A11_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,1))) -#define TSB_T32A11_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,0))) -#define TSB_T32A11_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,1))) -#define TSB_T32A11_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,2))) -#define TSB_T32A11_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,4))) -#define TSB_T32A11_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRA,20))) -#define TSB_T32A11_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,0))) -#define TSB_T32A11_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,1))) -#define TSB_T32A11_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,2))) -#define TSB_T32A11_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,3))) -#define TSB_T32A11_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,0))) -#define TSB_T32A11_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,1))) -#define TSB_T32A11_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,2))) -#define TSB_T32A11_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,3))) -#define TSB_T32A11_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,0))) -#define TSB_T32A11_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,1))) -#define TSB_T32A11_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,2))) -#define TSB_T32A11_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,0))) -#define TSB_T32A11_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,1))) -#define TSB_T32A11_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,2))) -#define TSB_T32A11_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,4))) -#define TSB_T32A11_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRB,20))) -#define TSB_T32A11_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,0))) -#define TSB_T32A11_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,1))) -#define TSB_T32A11_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,2))) -#define TSB_T32A11_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,3))) -#define TSB_T32A11_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,0))) -#define TSB_T32A11_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,1))) -#define TSB_T32A11_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,2))) -#define TSB_T32A11_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,3))) -#define TSB_T32A11_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,0))) -#define TSB_T32A11_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,1))) -#define TSB_T32A11_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,2))) -#define TSB_T32A11_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,0))) -#define TSB_T32A11_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,1))) -#define TSB_T32A11_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,2))) -#define TSB_T32A11_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,4))) -#define TSB_T32A11_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRC,20))) -#define TSB_T32A11_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,0))) -#define TSB_T32A11_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,1))) -#define TSB_T32A11_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,2))) -#define TSB_T32A11_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,3))) -#define TSB_T32A11_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,4))) -#define TSB_T32A11_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,0))) -#define TSB_T32A11_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,1))) -#define TSB_T32A11_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,2))) -#define TSB_T32A11_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,3))) -#define TSB_T32A11_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,4))) -#define TSB_T32A11_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,0))) -#define TSB_T32A11_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,1))) -#define TSB_T32A11_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,2))) -#define TSB_T32A11_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,0))) -#define TSB_T32A11_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,1))) - -#define TSB_T32A12_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,0))) -#define TSB_T32A12_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,1))) -#define TSB_T32A12_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,0))) -#define TSB_T32A12_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,1))) -#define TSB_T32A12_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,2))) -#define TSB_T32A12_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,4))) -#define TSB_T32A12_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRA,20))) -#define TSB_T32A12_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,0))) -#define TSB_T32A12_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,1))) -#define TSB_T32A12_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,2))) -#define TSB_T32A12_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,3))) -#define TSB_T32A12_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,0))) -#define TSB_T32A12_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,1))) -#define TSB_T32A12_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,2))) -#define TSB_T32A12_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,3))) -#define TSB_T32A12_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,0))) -#define TSB_T32A12_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,1))) -#define TSB_T32A12_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,2))) -#define TSB_T32A12_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,0))) -#define TSB_T32A12_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,1))) -#define TSB_T32A12_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,2))) -#define TSB_T32A12_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,4))) -#define TSB_T32A12_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRB,20))) -#define TSB_T32A12_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,0))) -#define TSB_T32A12_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,1))) -#define TSB_T32A12_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,2))) -#define TSB_T32A12_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,3))) -#define TSB_T32A12_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,0))) -#define TSB_T32A12_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,1))) -#define TSB_T32A12_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,2))) -#define TSB_T32A12_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,3))) -#define TSB_T32A12_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,0))) -#define TSB_T32A12_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,1))) -#define TSB_T32A12_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,2))) -#define TSB_T32A12_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,0))) -#define TSB_T32A12_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,1))) -#define TSB_T32A12_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,2))) -#define TSB_T32A12_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,4))) -#define TSB_T32A12_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRC,20))) -#define TSB_T32A12_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,0))) -#define TSB_T32A12_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,1))) -#define TSB_T32A12_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,2))) -#define TSB_T32A12_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,3))) -#define TSB_T32A12_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,4))) -#define TSB_T32A12_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,0))) -#define TSB_T32A12_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,1))) -#define TSB_T32A12_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,2))) -#define TSB_T32A12_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,3))) -#define TSB_T32A12_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,4))) -#define TSB_T32A12_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,0))) -#define TSB_T32A12_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,1))) -#define TSB_T32A12_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,2))) -#define TSB_T32A12_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,0))) -#define TSB_T32A12_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,1))) - -#define TSB_T32A13_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,0))) -#define TSB_T32A13_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,1))) -#define TSB_T32A13_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,0))) -#define TSB_T32A13_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,1))) -#define TSB_T32A13_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,2))) -#define TSB_T32A13_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,4))) -#define TSB_T32A13_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRA,20))) -#define TSB_T32A13_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,0))) -#define TSB_T32A13_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,1))) -#define TSB_T32A13_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,2))) -#define TSB_T32A13_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,3))) -#define TSB_T32A13_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,0))) -#define TSB_T32A13_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,1))) -#define TSB_T32A13_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,2))) -#define TSB_T32A13_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,3))) -#define TSB_T32A13_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,0))) -#define TSB_T32A13_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,1))) -#define TSB_T32A13_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,2))) -#define TSB_T32A13_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,0))) -#define TSB_T32A13_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,1))) -#define TSB_T32A13_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,2))) -#define TSB_T32A13_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,4))) -#define TSB_T32A13_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRB,20))) -#define TSB_T32A13_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,0))) -#define TSB_T32A13_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,1))) -#define TSB_T32A13_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,2))) -#define TSB_T32A13_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,3))) -#define TSB_T32A13_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,0))) -#define TSB_T32A13_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,1))) -#define TSB_T32A13_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,2))) -#define TSB_T32A13_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,3))) -#define TSB_T32A13_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,0))) -#define TSB_T32A13_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,1))) -#define TSB_T32A13_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,2))) -#define TSB_T32A13_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,0))) -#define TSB_T32A13_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,1))) -#define TSB_T32A13_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,2))) -#define TSB_T32A13_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,4))) -#define TSB_T32A13_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRC,20))) -#define TSB_T32A13_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,0))) -#define TSB_T32A13_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,1))) -#define TSB_T32A13_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,2))) -#define TSB_T32A13_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,3))) -#define TSB_T32A13_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,4))) -#define TSB_T32A13_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,0))) -#define TSB_T32A13_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,1))) -#define TSB_T32A13_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,2))) -#define TSB_T32A13_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,3))) -#define TSB_T32A13_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,4))) -#define TSB_T32A13_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,0))) -#define TSB_T32A13_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,1))) -#define TSB_T32A13_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,2))) -#define TSB_T32A13_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,0))) -#define TSB_T32A13_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,1))) - - -/* UART */ -#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) -#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) -#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) -#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) -#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) -#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) -#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) -#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) -#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) -#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) -#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) -#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) -#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) -#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) -#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) -#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) -#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) -#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) -#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) -#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) -#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) -#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) -#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) -#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) -#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) -#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) -#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) -#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) -#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) -#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) -#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) -#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) -#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) -#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) -#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) -#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) -#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) -#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) -#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) - -#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) -#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) -#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) -#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) -#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) -#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) -#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) -#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) -#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) -#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) -#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) -#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) -#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) -#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) -#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) -#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) -#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) -#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) -#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) -#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) -#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) -#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) -#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) -#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) -#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) -#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) -#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) -#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) -#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) -#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) -#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) -#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) -#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) -#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) -#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) -#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) -#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) -#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) -#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) - -#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) -#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) -#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) -#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) -#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) -#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) -#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) -#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) -#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) -#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) -#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) -#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) -#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) -#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) -#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) -#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) -#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) -#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) -#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) -#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) -#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) -#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) -#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) -#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) -#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) -#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) -#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) -#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) -#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) -#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) -#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) -#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) -#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) -#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) -#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) -#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) -#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) -#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) -#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) - -#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) -#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) -#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) -#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) -#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) -#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) -#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) -#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) -#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) -#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) -#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) -#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) -#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) -#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) -#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) -#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) -#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) -#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) -#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) -#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) -#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) -#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) -#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) -#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) -#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) -#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) -#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) -#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) -#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) -#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) -#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) -#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) -#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) -#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) -#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) -#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) -#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) -#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) -#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) - -#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) -#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) -#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) -#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) -#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) -#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) -#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) -#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) -#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) -#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) -#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) -#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) -#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) -#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) -#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) -#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) -#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) -#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) -#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) -#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) -#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) -#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) -#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) -#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) -#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) -#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) -#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) -#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) -#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) -#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) -#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) -#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) -#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) -#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) -#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) -#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) -#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) -#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) -#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) - -#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) -#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) -#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) -#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) -#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) -#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) -#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) -#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) -#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) -#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) -#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) -#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) -#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) -#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) -#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) -#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) -#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) -#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) -#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) -#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) -#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) -#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) -#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) -#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) -#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) -#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) -#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) -#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) -#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) -#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) -#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) -#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) -#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) -#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) -#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) -#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) -#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) -#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) -#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) - - -/* I2C */ -#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) -#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) -#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) -#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) -#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) -#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) -#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) -#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) -#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) -#define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) -#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) -#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) -#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) -#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) -#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) -#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) -#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) -#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) -#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) -#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) -#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) -#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) -#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) -#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) -#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) -#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) -#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) -#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) -#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) -#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) -#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) -#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) -#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) -#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) -#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) -#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) -#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) -#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) - -#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) -#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) -#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) -#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) -#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) -#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) -#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) -#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) -#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) -#define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) -#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) -#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) -#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) -#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) -#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) -#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) -#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) -#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) -#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) -#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) -#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) -#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) -#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) -#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) -#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) -#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) -#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) -#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) -#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) -#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) -#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) -#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) -#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) -#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) -#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) -#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) -#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) -#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) - -#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) -#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) -#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) -#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) -#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) -#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) -#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) -#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) -#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) -#define TSB_I2C2_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) -#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) -#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) -#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) -#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) -#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) -#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) -#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) -#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) -#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) -#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) -#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) -#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) -#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) -#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) -#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) -#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) -#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) -#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) -#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) -#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) -#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) -#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) -#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) -#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) -#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) -#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) -#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) -#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) - -#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) -#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) -#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) -#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) -#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) -#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) -#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) -#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) -#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) -#define TSB_I2C3_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) -#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) -#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) -#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) -#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) -#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) -#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) -#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) -#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) -#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) -#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) -#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) -#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) -#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) -#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) -#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) -#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) -#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) -#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) -#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) -#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) -#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) -#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) -#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) -#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) -#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) -#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) -#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) -#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) - -#define TSB_I2C4_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,3))) -#define TSB_I2C4_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,4))) -#define TSB_I2C4_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR,0))) -#define TSB_I2C4_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,3))) -#define TSB_I2C4_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,4))) -#define TSB_I2C4_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,5))) -#define TSB_I2C4_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,6))) -#define TSB_I2C4_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,7))) -#define TSB_I2C4_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,0))) -#define TSB_I2C4_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,1))) -#define TSB_I2C4_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,2))) -#define TSB_I2C4_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,3))) -#define TSB_I2C4_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,4))) -#define TSB_I2C4_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,5))) -#define TSB_I2C4_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,6))) -#define TSB_I2C4_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,7))) -#define TSB_I2C4_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,0))) -#define TSB_I2C4_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,1))) -#define TSB_I2C4_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,2))) -#define TSB_I2C4_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,3))) -#define TSB_I2C4_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,4))) -#define TSB_I2C4_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,5))) -#define TSB_I2C4_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,6))) -#define TSB_I2C4_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,0))) -#define TSB_I2C4_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,1))) -#define TSB_I2C4_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,2))) -#define TSB_I2C4_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,3))) -#define TSB_I2C4_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,0))) -#define TSB_I2C4_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,1))) -#define TSB_I2C4_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,2))) -#define TSB_I2C4_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,3))) -#define TSB_I2C4_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,4))) -#define TSB_I2C4_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,5))) -#define TSB_I2C4_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,6))) -#define TSB_I2C4_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,7))) -#define TSB_I2C4_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,0))) -#define TSB_I2C4_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,1))) -#define TSB_I2C4_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR2,0))) - - -/* Port A */ -#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) -#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) -#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) -#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) -#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) -#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) -#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) -#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) -#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) -#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) -#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) -#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) -#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) -#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) -#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) -#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) -#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) -#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) -#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) -#define TSB_PA_FR1_PA3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3))) -#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) -#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) -#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) -#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) -#define TSB_PA_FR2_PA0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,0))) -#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) -#define TSB_PA_FR2_PA4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,4))) -#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) -#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) -#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) -#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) -#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) -#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) -#define TSB_PA_FR3_PA5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,5))) -#define TSB_PA_FR3_PA6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,6))) -#define TSB_PA_FR3_PA7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,7))) -#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) -#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) -#define TSB_PA_FR5_PA3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,3))) -#define TSB_PA_FR5_PA4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,4))) -#define TSB_PA_FR5_PA5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,5))) -#define TSB_PA_FR5_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,7))) -#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) -#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) -#define TSB_PA_FR6_PA4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,4))) -#define TSB_PA_FR6_PA5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,5))) -#define TSB_PA_FR6_PA6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,6))) -#define TSB_PA_FR6_PA7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,7))) -#define TSB_PA_FR7_PA0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,0))) -#define TSB_PA_FR7_PA1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,1))) -#define TSB_PA_FR7_PA2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,2))) -#define TSB_PA_FR7_PA3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,3))) -#define TSB_PA_FR7_PA4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,4))) -#define TSB_PA_FR7_PA5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,5))) -#define TSB_PA_FR7_PA6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,6))) -#define TSB_PA_FR7_PA7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,7))) -#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) -#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) -#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) -#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) -#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) -#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) -#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) -#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) -#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) -#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) -#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) -#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) -#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) -#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) -#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) -#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) -#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) -#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) -#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) -#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) -#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) -#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) -#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) -#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) -#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) -#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) -#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) -#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) -#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) -#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) -#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) -#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) - - -/* Port B */ -#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) -#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) -#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) -#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) -#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) -#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) -#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) -#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) -#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) -#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) -#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) -#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) -#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) -#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) -#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) -#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) -#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) -#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) -#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) -#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) -#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) -#define TSB_PB_FR1_PB6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,6))) -#define TSB_PB_FR1_PB7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,7))) -#define TSB_PB_FR2_PB0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,0))) -#define TSB_PB_FR2_PB1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,1))) -#define TSB_PB_FR2_PB6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,6))) -#define TSB_PB_FR2_PB7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,7))) -#define TSB_PB_FR3_PB0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,0))) -#define TSB_PB_FR3_PB1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,1))) -#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) -#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) -#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) -#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) -#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) -#define TSB_PB_FR3_PB7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,7))) -#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) -#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) -#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) -#define TSB_PB_FR5_PB4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,4))) -#define TSB_PB_FR5_PB6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,6))) -#define TSB_PB_FR5_PB7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,7))) -#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) -#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) -#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) -#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) -#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) -#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) -#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) -#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) -#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) -#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) -#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) -#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) -#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) -#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) -#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) -#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) -#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) -#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) -#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) -#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) -#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) -#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) -#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) -#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) -#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) -#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) -#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) -#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) -#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) -#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) -#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) -#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) -#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) - - -/* Port C */ -#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) -#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) -#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) -#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) -#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) -#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) -#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) -#define TSB_PC_DATA_PC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,7))) -#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) -#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) -#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) -#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) -#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) -#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) -#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) -#define TSB_PC_CR_PC7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,7))) -#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) -#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) -#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) -#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) -#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) -#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) -#define TSB_PC_FR1_PC7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,7))) -#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) -#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) -#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) -#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) -#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) -#define TSB_PC_FR5_PC1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,1))) -#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) -#define TSB_PC_FR5_PC4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,4))) -#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) -#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) -#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) -#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) -#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) -#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) -#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) -#define TSB_PC_OD_PC7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,7))) -#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) -#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) -#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) -#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) -#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) -#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) -#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) -#define TSB_PC_PUP_PC7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,7))) -#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) -#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) -#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) -#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) -#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) -#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) -#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) -#define TSB_PC_PDN_PC7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,7))) -#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) -#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) -#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) -#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) -#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) -#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) -#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) -#define TSB_PC_IE_PC7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,7))) - - -/* Port D */ -#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) -#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) -#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) -#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) -#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) -#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) -#define TSB_PD_DATA_PD6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,6))) -#define TSB_PD_DATA_PD7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,7))) -#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) -#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) -#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) -#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) -#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) -#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) -#define TSB_PD_CR_PD6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,6))) -#define TSB_PD_CR_PD7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,7))) -#define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1))) -#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) -#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) -#define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4))) -#define TSB_PD_FR1_PD5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,5))) -#define TSB_PD_FR1_PD6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,6))) -#define TSB_PD_FR1_PD7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,7))) -#define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0))) -#define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1))) -#define TSB_PD_FR2_PD6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,6))) -#define TSB_PD_FR2_PD7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,7))) -#define TSB_PD_FR3_PD0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,0))) -#define TSB_PD_FR3_PD1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,1))) -#define TSB_PD_FR3_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,2))) -#define TSB_PD_FR3_PD3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,3))) -#define TSB_PD_FR3_PD4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,4))) -#define TSB_PD_FR3_PD5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,5))) -#define TSB_PD_FR3_PD6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,6))) -#define TSB_PD_FR3_PD7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,7))) -#define TSB_PD_FR4_PD0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,0))) -#define TSB_PD_FR4_PD1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,1))) -#define TSB_PD_FR4_PD2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,2))) -#define TSB_PD_FR4_PD3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,3))) -#define TSB_PD_FR5_PD0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,0))) -#define TSB_PD_FR5_PD1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,1))) -#define TSB_PD_FR5_PD2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,2))) -#define TSB_PD_FR5_PD4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,4))) -#define TSB_PD_FR5_PD6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,6))) -#define TSB_PD_FR5_PD7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,7))) -#define TSB_PD_FR6_PD0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,0))) -#define TSB_PD_FR7_PD0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,0))) -#define TSB_PD_FR7_PD1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,1))) -#define TSB_PD_FR7_PD2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,2))) -#define TSB_PD_FR7_PD3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,3))) -#define TSB_PD_FR7_PD4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,4))) -#define TSB_PD_FR7_PD5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,5))) -#define TSB_PD_FR7_PD6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,6))) -#define TSB_PD_FR7_PD7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,7))) -#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) -#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) -#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) -#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) -#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) -#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) -#define TSB_PD_OD_PD6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,6))) -#define TSB_PD_OD_PD7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,7))) -#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) -#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) -#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) -#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) -#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) -#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) -#define TSB_PD_PUP_PD6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,6))) -#define TSB_PD_PUP_PD7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,7))) -#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) -#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) -#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) -#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) -#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) -#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) -#define TSB_PD_PDN_PD6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,6))) -#define TSB_PD_PDN_PD7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,7))) -#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) -#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) -#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) -#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) -#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) -#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) -#define TSB_PD_IE_PD6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,6))) -#define TSB_PD_IE_PD7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,7))) - - -/* Port E */ -#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) -#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) -#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) -#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) -#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) -#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) -#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) -#define TSB_PE_DATA_PE7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7))) -#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) -#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) -#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) -#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) -#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) -#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) -#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) -#define TSB_PE_CR_PE7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7))) -#define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0))) -#define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1))) -#define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2))) -#define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3))) -#define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4))) -#define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5))) -#define TSB_PE_FR1_PE6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,6))) -#define TSB_PE_FR1_PE7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,7))) -#define TSB_PE_FR2_PE0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,0))) -#define TSB_PE_FR2_PE7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,7))) -#define TSB_PE_FR3_PE0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,0))) -#define TSB_PE_FR3_PE1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,1))) -#define TSB_PE_FR3_PE2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,2))) -#define TSB_PE_FR3_PE3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,3))) -#define TSB_PE_FR3_PE4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,4))) -#define TSB_PE_FR3_PE5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,5))) -#define TSB_PE_FR3_PE6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,6))) -#define TSB_PE_FR3_PE7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,7))) -#define TSB_PE_FR4_PE0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,0))) -#define TSB_PE_FR4_PE1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,1))) -#define TSB_PE_FR4_PE2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,2))) -#define TSB_PE_FR4_PE3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3))) -#define TSB_PE_FR4_PE4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4))) -#define TSB_PE_FR4_PE5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,5))) -#define TSB_PE_FR4_PE6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,6))) -#define TSB_PE_FR4_PE7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,7))) -#define TSB_PE_FR5_PE0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,0))) -#define TSB_PE_FR5_PE1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1))) -#define TSB_PE_FR5_PE2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2))) -#define TSB_PE_FR5_PE3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3))) -#define TSB_PE_FR5_PE4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,4))) -#define TSB_PE_FR5_PE5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,5))) -#define TSB_PE_FR5_PE6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,6))) -#define TSB_PE_FR5_PE7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,7))) -#define TSB_PE_FR7_PE0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,0))) -#define TSB_PE_FR7_PE1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,1))) -#define TSB_PE_FR7_PE2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,2))) -#define TSB_PE_FR7_PE3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,3))) -#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) -#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) -#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) -#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) -#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) -#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) -#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) -#define TSB_PE_OD_PE7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7))) -#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) -#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) -#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) -#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) -#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) -#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) -#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) -#define TSB_PE_PUP_PE7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7))) -#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) -#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) -#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) -#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) -#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) -#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) -#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) -#define TSB_PE_PDN_PE7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,7))) -#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) -#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) -#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) -#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) -#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) -#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) -#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) -#define TSB_PE_IE_PE7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7))) - - -/* Port F */ -#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) -#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) -#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) -#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) -#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) -#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) -#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) -#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) -#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) -#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) -#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) -#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) -#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) -#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) -#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) -#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) -#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) -#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) -#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) -#define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5))) -#define TSB_PF_FR1_PF6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6))) -#define TSB_PF_FR1_PF7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7))) -#define TSB_PF_FR7_PF2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,2))) -#define TSB_PF_FR7_PF3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,3))) -#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) -#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) -#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) -#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) -#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) -#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) -#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) -#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) -#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) -#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) -#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) -#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) -#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) -#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) -#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) -#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) -#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) -#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) -#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) -#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) -#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) -#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) -#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) -#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) -#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) -#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) -#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) -#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) -#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) -#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) -#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) -#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) - - -/* Port G */ -#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) -#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) -#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) -#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) -#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) -#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) -#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) -#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) -#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) -#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) -#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) -#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) -#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) -#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) -#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) -#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) -#define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0))) -#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) -#define TSB_PG_FR1_PG6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6))) -#define TSB_PG_FR1_PG7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,7))) -#define TSB_PG_FR2_PG4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,4))) -#define TSB_PG_FR2_PG5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,5))) -#define TSB_PG_FR3_PG0F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,0))) -#define TSB_PG_FR3_PG1F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,1))) -#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) -#define TSB_PG_FR3_PG3F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) -#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) -#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) -#define TSB_PG_FR4_PG3F4 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) -#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) -#define TSB_PG_FR4_PG5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,5))) -#define TSB_PG_FR4_PG6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,6))) -#define TSB_PG_FR4_PG7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,7))) -#define TSB_PG_FR5_PG0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0))) -#define TSB_PG_FR5_PG1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1))) -#define TSB_PG_FR5_PG2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2))) -#define TSB_PG_FR5_PG3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,3))) -#define TSB_PG_FR5_PG4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,4))) -#define TSB_PG_FR5_PG5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,5))) -#define TSB_PG_FR5_PG6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,6))) -#define TSB_PG_FR5_PG7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,7))) -#define TSB_PG_FR7_PG2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,2))) -#define TSB_PG_FR7_PG3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,3))) -#define TSB_PG_FR7_PG4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,4))) -#define TSB_PG_FR7_PG5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,5))) -#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) -#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) -#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) -#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) -#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) -#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) -#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) -#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) -#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) -#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) -#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) -#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) -#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) -#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) -#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) -#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) -#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) -#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) -#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) -#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) -#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) -#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) -#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) -#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) -#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) -#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) -#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) -#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) -#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) -#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) -#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) -#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) - - -/* Port H */ -#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) -#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) -#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) -#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) -#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) -#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) -#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) -#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) -#define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0))) -#define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1))) -#define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2))) -#define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3))) -#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) -#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) -#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) -#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) -#define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0))) -#define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1))) -#define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2))) -#define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3))) -#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) -#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) -#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) -#define TSB_PH_FR1_PH7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,7))) -#define TSB_PH_FR3_PH0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,0))) -#define TSB_PH_FR3_PH1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,1))) -#define TSB_PH_FR3_PH2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,2))) -#define TSB_PH_FR3_PH3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,3))) -#define TSB_PH_FR3_PH4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,4))) -#define TSB_PH_FR3_PH5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,5))) -#define TSB_PH_FR3_PH6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,6))) -#define TSB_PH_FR3_PH7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,7))) -#define TSB_PH_FR4_PH0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,0))) -#define TSB_PH_FR4_PH1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,1))) -#define TSB_PH_FR4_PH2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,2))) -#define TSB_PH_FR4_PH3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,3))) -#define TSB_PH_FR5_PH0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,0))) -#define TSB_PH_FR5_PH1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,1))) -#define TSB_PH_FR5_PH2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,2))) -#define TSB_PH_FR5_PH3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,3))) -#define TSB_PH_FR5_PH4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,4))) -#define TSB_PH_FR5_PH5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,5))) -#define TSB_PH_FR5_PH6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,6))) -#define TSB_PH_FR5_PH7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,7))) -#define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0))) -#define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1))) -#define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2))) -#define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3))) -#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) -#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) -#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) -#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) -#define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0))) -#define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1))) -#define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2))) -#define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3))) -#define TSB_PH_PUP_PH4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) -#define TSB_PH_PUP_PH5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) -#define TSB_PH_PUP_PH6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) -#define TSB_PH_PUP_PH7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) -#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) -#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) -#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) -#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) -#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) -#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) -#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) -#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) -#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) -#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) -#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) -#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) -#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) -#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) -#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) -#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) - - -/* Port J */ -#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) -#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) -#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) -#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) -#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) -#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) -#define TSB_PJ_DATA_PJ6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,6))) -#define TSB_PJ_DATA_PJ7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,7))) -#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) -#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) -#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) -#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) -#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) -#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) -#define TSB_PJ_CR_PJ6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,6))) -#define TSB_PJ_CR_PJ7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,7))) -#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) -#define TSB_PJ_FR2_PJ5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,5))) -#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) -#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) -#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) -#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) -#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) -#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) -#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) -#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) -#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) -#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) -#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) -#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) -#define TSB_PJ_FR5_PJ6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,6))) -#define TSB_PJ_FR5_PJ7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,7))) -#define TSB_PJ_FR7_PJ2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,2))) -#define TSB_PJ_FR7_PJ3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,3))) -#define TSB_PJ_FR7_PJ6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,6))) -#define TSB_PJ_FR7_PJ7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,7))) -#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) -#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) -#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) -#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) -#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) -#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) -#define TSB_PJ_OD_PJ6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,6))) -#define TSB_PJ_OD_PJ7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,7))) -#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) -#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) -#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) -#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) -#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) -#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) -#define TSB_PJ_PUP_PJ6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,6))) -#define TSB_PJ_PUP_PJ7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,7))) -#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) -#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) -#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) -#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) -#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) -#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) -#define TSB_PJ_PDN_PJ6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,6))) -#define TSB_PJ_PDN_PJ7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,7))) -#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) -#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) -#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) -#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) -#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) -#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) -#define TSB_PJ_IE_PJ6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,6))) -#define TSB_PJ_IE_PJ7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,7))) - - -/* Port K */ -#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) -#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) -#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) -#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) -#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) -#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) -#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) -#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) -#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) -#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) -#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) -#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) -#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) -#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) -#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) -#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) -#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) -#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) -#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) -#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) -#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) -#define TSB_PK_FR1_PK5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,5))) -#define TSB_PK_FR2_PK0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,0))) -#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) -#define TSB_PK_FR2_PK6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,6))) -#define TSB_PK_FR2_PK7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,7))) -#define TSB_PK_FR3_PK0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,0))) -#define TSB_PK_FR3_PK1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,1))) -#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) -#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) -#define TSB_PK_FR4_PK1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,1))) -#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) -#define TSB_PK_FR4_PK5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,5))) -#define TSB_PK_FR4_PK6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,6))) -#define TSB_PK_FR4_PK7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,7))) -#define TSB_PK_FR6_PK2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,2))) -#define TSB_PK_FR6_PK3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,3))) -#define TSB_PK_FR6_PK4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,4))) -#define TSB_PK_FR6_PK5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,5))) -#define TSB_PK_FR6_PK6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,6))) -#define TSB_PK_FR6_PK7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,7))) -#define TSB_PK_FR7_PK7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR7,7))) -#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) -#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) -#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) -#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) -#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) -#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) -#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) -#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) -#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) -#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) -#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) -#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) -#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) -#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) -#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) -#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) -#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) -#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) -#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) -#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) -#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) -#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) -#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) -#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) -#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) -#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) -#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) -#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) -#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) -#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) -#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) -#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) - - -/* Port L */ -#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) -#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) -#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) -#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) -#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) -#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) -#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) -#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) -#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) -#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) -#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) -#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) -#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) -#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) -#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) -#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) -#define TSB_PL_FR1_PL7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,7))) -#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) -#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) -#define TSB_PL_FR2_PL4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,4))) -#define TSB_PL_FR2_PL5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,5))) -#define TSB_PL_FR2_PL6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,6))) -#define TSB_PL_FR2_PL7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,7))) -#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) -#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) -#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) -#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) -#define TSB_PL_FR6_PL0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,0))) -#define TSB_PL_FR6_PL3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,3))) -#define TSB_PL_FR7_PL0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,0))) -#define TSB_PL_FR7_PL1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,1))) -#define TSB_PL_FR7_PL2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,2))) -#define TSB_PL_FR7_PL3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,3))) -#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) -#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) -#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) -#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) -#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) -#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) -#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) -#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) -#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) -#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) -#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) -#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) -#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) -#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) -#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) -#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) -#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) -#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) -#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) -#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) -#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) -#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) -#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) -#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) -#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) -#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) -#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) -#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) -#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) -#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) -#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) -#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) - - -/* Port M */ -#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) -#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) -#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) -#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) -#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) -#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) -#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) -#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) -#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) -#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) -#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) -#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) -#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) -#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) -#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) -#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) -#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) -#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) -#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) -#define TSB_PM_FR2_PM5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,5))) -#define TSB_PM_FR2_PM6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,6))) -#define TSB_PM_FR2_PM7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,7))) -#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) -#define TSB_PM_FR3_PM5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,5))) -#define TSB_PM_FR3_PM6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,6))) -#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) -#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) -#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) -#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) -#define TSB_PM_FR4_PM6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,6))) -#define TSB_PM_FR4_PM7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,7))) -#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) -#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) -#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) -#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) -#define TSB_PM_FR5_PM6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,6))) -#define TSB_PM_FR5_PM7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,7))) -#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) -#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) -#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) -#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) -#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) -#define TSB_PM_FR6_PM5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,5))) -#define TSB_PM_FR6_PM6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,6))) -#define TSB_PM_FR6_PM7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,7))) -#define TSB_PM_FR7_PM0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,0))) -#define TSB_PM_FR7_PM1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,1))) -#define TSB_PM_FR7_PM2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,2))) -#define TSB_PM_FR7_PM3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,3))) -#define TSB_PM_FR7_PM4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,4))) -#define TSB_PM_FR7_PM5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,5))) -#define TSB_PM_FR7_PM6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,6))) -#define TSB_PM_FR7_PM7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,7))) -#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) -#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) -#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) -#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) -#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) -#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) -#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) -#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) -#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) -#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) -#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) -#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) -#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) -#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) -#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) -#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) -#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) -#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) -#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) -#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) -#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) -#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) -#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) -#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) -#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) -#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) -#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) -#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) -#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) -#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) -#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) -#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) - - -/* Port N */ -#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) -#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) -#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) -#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) -#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) -#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) -#define TSB_PN_DATA_PN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,6))) -#define TSB_PN_DATA_PN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,7))) -#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) -#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) -#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) -#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) -#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) -#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) -#define TSB_PN_CR_PN6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,6))) -#define TSB_PN_CR_PN7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,7))) -#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) -#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) -#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) -#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) -#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) -#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) -#define TSB_PN_OD_PN6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,6))) -#define TSB_PN_OD_PN7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,7))) -#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) -#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) -#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) -#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) -#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) -#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) -#define TSB_PN_PUP_PN6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,6))) -#define TSB_PN_PUP_PN7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,7))) -#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) -#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) -#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) -#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) -#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) -#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) -#define TSB_PN_PDN_PN6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,6))) -#define TSB_PN_PDN_PN7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,7))) -#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) -#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) -#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) -#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) -#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) -#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) -#define TSB_PN_IE_PN6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,6))) -#define TSB_PN_IE_PN7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,7))) - - -/* Port P */ -#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) -#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) -#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) -#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) -#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) -#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) -#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) -#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) -#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) -#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) -#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) -#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) -#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) -#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) -#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) -#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) -#define TSB_PP_FR2_PP0FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) -#define TSB_PP_FR2_PP1FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) -#define TSB_PP_FR2_PP2FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) -#define TSB_PP_FR2_PP3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,3))) -#define TSB_PP_FR2_PP4FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,4))) -#define TSB_PP_FR2_PP5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,5))) -#define TSB_PP_FR2_PP6FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) -#define TSB_PP_FR2_PP7FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,7))) -#define TSB_PP_FR3_PP0FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) -#define TSB_PP_FR3_PP1FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) -#define TSB_PP_FR3_PP2FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) -#define TSB_PP_FR3_PP3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,3))) -#define TSB_PP_FR3_PP4FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,4))) -#define TSB_PP_FR3_PP5FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,5))) -#define TSB_PP_FR3_PP6FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) -#define TSB_PP_FR3_PP7FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,7))) -#define TSB_PP_FR5_PP0FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,0))) -#define TSB_PP_FR5_PP1FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,1))) -#define TSB_PP_FR5_PP2FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,2))) -#define TSB_PP_FR5_PP3FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,3))) -#define TSB_PP_FR5_PP4FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,4))) -#define TSB_PP_FR5_PP5FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,5))) -#define TSB_PP_FR5_PP6FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,6))) -#define TSB_PP_FR5_PP7FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,7))) -#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) -#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) -#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) -#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) -#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) -#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) -#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) -#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) -#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) -#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) -#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) -#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) -#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) -#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) -#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) -#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) -#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) -#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) -#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) -#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) -#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) -#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) -#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) -#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) -#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) -#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) -#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) -#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) -#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) -#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) -#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) -#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) - - -/* Port R */ -#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) -#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) -#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) -#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) -#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) -#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) -#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) -#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) -#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) -#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) -#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) -#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) -#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) -#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) -#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) -#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) -#define TSB_PR_FR2_PR0FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,0))) -#define TSB_PR_FR2_PR1FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,1))) -#define TSB_PR_FR2_PR2FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,2))) -#define TSB_PR_FR2_PR3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,3))) -#define TSB_PR_FR2_PR4FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,4))) -#define TSB_PR_FR2_PR5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,5))) -#define TSB_PR_FR2_PR6FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,6))) -#define TSB_PR_FR2_PR7FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,7))) -#define TSB_PR_FR3_PR0FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) -#define TSB_PR_FR3_PR1FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) -#define TSB_PR_FR3_PR2FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) -#define TSB_PR_FR3_PR3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,3))) -#define TSB_PR_FR3_PR4FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,4))) -#define TSB_PR_FR3_PR5FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,5))) -#define TSB_PR_FR3_PR6FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,6))) -#define TSB_PR_FR3_PR7FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,7))) -#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) -#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) -#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) -#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) -#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) -#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) -#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) -#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) -#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) -#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) -#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) -#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) -#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) -#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) -#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) -#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) -#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) -#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) -#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) -#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) -#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) -#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) -#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) -#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) -#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) -#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) -#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) -#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) -#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) -#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) -#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) -#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) - - -/* Port T */ -#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) -#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) -#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) -#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) -#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) -#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) -#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) -#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) -#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) -#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) -#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) -#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) -#define TSB_PT_FR1_PT3FR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) -#define TSB_PT_FR2_PT3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,3))) -#define TSB_PT_FR2_PT5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,5))) -#define TSB_PT_FR3_PT3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) -#define TSB_PT_FR6_PT3FR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR6,3))) -#define TSB_PT_FR7_PT2FR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR7,2))) -#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) -#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) -#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) -#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) -#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) -#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) -#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) -#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) -#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) -#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) -#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) -#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) -#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) -#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) -#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) -#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) -#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) -#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) -#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) -#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) -#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) -#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) -#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) -#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) - - -/* Port U */ -#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) -#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) -#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) -#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) -#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) -#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) -#define TSB_PU_DATA_PU6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,6))) -#define TSB_PU_DATA_PU7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,7))) -#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) -#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) -#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) -#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) -#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) -#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) -#define TSB_PU_CR_PU6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,6))) -#define TSB_PU_CR_PU7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,7))) -#define TSB_PU_FR2_PU0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,0))) -#define TSB_PU_FR2_PU1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,1))) -#define TSB_PU_FR2_PU2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,2))) -#define TSB_PU_FR2_PU3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,3))) -#define TSB_PU_FR2_PU4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,4))) -#define TSB_PU_FR2_PU5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,5))) -#define TSB_PU_FR2_PU6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,6))) -#define TSB_PU_FR2_PU7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,7))) -#define TSB_PU_FR3_PU0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,0))) -#define TSB_PU_FR3_PU2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,2))) -#define TSB_PU_FR3_PU3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,3))) -#define TSB_PU_FR3_PU4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,4))) -#define TSB_PU_FR3_PU5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,5))) -#define TSB_PU_FR3_PU6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,6))) -#define TSB_PU_FR7_PU0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,0))) -#define TSB_PU_FR7_PU1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,1))) -#define TSB_PU_FR7_PU2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,2))) -#define TSB_PU_FR7_PU3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,3))) -#define TSB_PU_FR7_PU4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,4))) -#define TSB_PU_FR7_PU5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,5))) -#define TSB_PU_FR7_PU6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,6))) -#define TSB_PU_FR7_PU7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,7))) -#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) -#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) -#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) -#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) -#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) -#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) -#define TSB_PU_OD_PU6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,6))) -#define TSB_PU_OD_PU7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,7))) -#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) -#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) -#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) -#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) -#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) -#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) -#define TSB_PU_PUP_PU6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,6))) -#define TSB_PU_PUP_PU7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,7))) -#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) -#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) -#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) -#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) -#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) -#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) -#define TSB_PU_PDN_PU6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,6))) -#define TSB_PU_PDN_PU7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,7))) -#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) -#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) -#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) -#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) -#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) -#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) -#define TSB_PU_IE_PU6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,6))) -#define TSB_PU_IE_PU7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,7))) - - -/* Port V */ -#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) -#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) -#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) -#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) -#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) -#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) -#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) -#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) -#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) -#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) -#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) -#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) -#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) -#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) -#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) -#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) -#define TSB_PV_FR2_PV0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,0))) -#define TSB_PV_FR2_PV1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,1))) -#define TSB_PV_FR2_PV2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,2))) -#define TSB_PV_FR2_PV3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,3))) -#define TSB_PV_FR2_PV4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,4))) -#define TSB_PV_FR2_PV5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,5))) -#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) -#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) -#define TSB_PV_FR3_PV0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,0))) -#define TSB_PV_FR3_PV1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,1))) -#define TSB_PV_FR3_PV2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,2))) -#define TSB_PV_FR3_PV5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,5))) -#define TSB_PV_FR3_PV6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,6))) -#define TSB_PV_FR4_PV4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,4))) -#define TSB_PV_FR4_PV5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,5))) -#define TSB_PV_FR4_PV6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,6))) -#define TSB_PV_FR4_PV7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,7))) -#define TSB_PV_FR5_PV0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,0))) -#define TSB_PV_FR5_PV1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,1))) -#define TSB_PV_FR5_PV2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,2))) -#define TSB_PV_FR5_PV3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,3))) -#define TSB_PV_FR5_PV4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,4))) -#define TSB_PV_FR5_PV5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,5))) -#define TSB_PV_FR5_PV6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,6))) -#define TSB_PV_FR5_PV7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,7))) -#define TSB_PV_FR6_PV0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,0))) -#define TSB_PV_FR6_PV1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,1))) -#define TSB_PV_FR6_PV2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,2))) -#define TSB_PV_FR6_PV3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,3))) -#define TSB_PV_FR6_PV4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,4))) -#define TSB_PV_FR6_PV5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,5))) -#define TSB_PV_FR6_PV7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,7))) -#define TSB_PV_FR7_PV0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,0))) -#define TSB_PV_FR7_PV1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,1))) -#define TSB_PV_FR7_PV2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,2))) -#define TSB_PV_FR7_PV3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,3))) -#define TSB_PV_FR7_PV4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,4))) -#define TSB_PV_FR7_PV5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,5))) -#define TSB_PV_FR7_PV6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,6))) -#define TSB_PV_FR7_PV7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,7))) -#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) -#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) -#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) -#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) -#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) -#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) -#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) -#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) -#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) -#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) -#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) -#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) -#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) -#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) -#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) -#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) -#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) -#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) -#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) -#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) -#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) -#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) -#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) -#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) -#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) -#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) -#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) -#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) -#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) -#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) -#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) -#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) - - -/* Port W */ -#define TSB_PW_DATA_PW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,0))) -#define TSB_PW_DATA_PW1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,1))) -#define TSB_PW_DATA_PW2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,2))) -#define TSB_PW_DATA_PW3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,3))) -#define TSB_PW_DATA_PW4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,4))) -#define TSB_PW_DATA_PW5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,5))) -#define TSB_PW_DATA_PW6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,6))) -#define TSB_PW_DATA_PW7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,7))) -#define TSB_PW_CR_PW0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,0))) -#define TSB_PW_CR_PW1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,1))) -#define TSB_PW_CR_PW2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,2))) -#define TSB_PW_CR_PW3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,3))) -#define TSB_PW_CR_PW4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,4))) -#define TSB_PW_CR_PW5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,5))) -#define TSB_PW_CR_PW6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,6))) -#define TSB_PW_CR_PW7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,7))) -#define TSB_PW_FR3_PW4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,4))) -#define TSB_PW_FR3_PW7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,7))) -#define TSB_PW_FR4_PW0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,0))) -#define TSB_PW_FR4_PW1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,1))) -#define TSB_PW_FR4_PW2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,2))) -#define TSB_PW_FR4_PW3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,3))) -#define TSB_PW_FR5_PW0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,0))) -#define TSB_PW_FR5_PW1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,1))) -#define TSB_PW_FR5_PW2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,2))) -#define TSB_PW_FR5_PW3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,3))) -#define TSB_PW_FR5_PW4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,4))) -#define TSB_PW_FR5_PW5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,5))) -#define TSB_PW_FR5_PW6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,6))) -#define TSB_PW_FR5_PW7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,7))) -#define TSB_PW_FR6_PW0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR6,0))) -#define TSB_PW_FR7_PW1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,1))) -#define TSB_PW_FR7_PW2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,2))) -#define TSB_PW_FR7_PW4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,4))) -#define TSB_PW_FR7_PW5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,5))) -#define TSB_PW_FR7_PW6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,6))) -#define TSB_PW_FR7_PW7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,7))) -#define TSB_PW_OD_PW0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,0))) -#define TSB_PW_OD_PW1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,1))) -#define TSB_PW_OD_PW2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,2))) -#define TSB_PW_OD_PW3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,3))) -#define TSB_PW_OD_PW4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,4))) -#define TSB_PW_OD_PW5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,5))) -#define TSB_PW_OD_PW6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,6))) -#define TSB_PW_OD_PW7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,7))) -#define TSB_PW_PUP_PW0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,0))) -#define TSB_PW_PUP_PW1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,1))) -#define TSB_PW_PUP_PW2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,2))) -#define TSB_PW_PUP_PW3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,3))) -#define TSB_PW_PUP_PW4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,4))) -#define TSB_PW_PUP_PW5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,5))) -#define TSB_PW_PUP_PW6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,6))) -#define TSB_PW_PUP_PW7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,7))) -#define TSB_PW_PDN_PW0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,0))) -#define TSB_PW_PDN_PW1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,1))) -#define TSB_PW_PDN_PW2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,2))) -#define TSB_PW_PDN_PW3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,3))) -#define TSB_PW_PDN_PW4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,4))) -#define TSB_PW_PDN_PW5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,5))) -#define TSB_PW_PDN_PW6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,6))) -#define TSB_PW_PDN_PW7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,7))) -#define TSB_PW_IE_PW0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,0))) -#define TSB_PW_IE_PW1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,1))) -#define TSB_PW_IE_PW2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,2))) -#define TSB_PW_IE_PW3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,3))) -#define TSB_PW_IE_PW4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,4))) -#define TSB_PW_IE_PW5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,5))) -#define TSB_PW_IE_PW6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,6))) -#define TSB_PW_IE_PW7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,7))) - - -/* Port Y */ -#define TSB_PY_DATA_PY0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,0))) -#define TSB_PY_DATA_PY1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,1))) -#define TSB_PY_DATA_PY2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,2))) -#define TSB_PY_DATA_PY3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,3))) -#define TSB_PY_DATA_PY4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,4))) -#define TSB_PY_CR_PY4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->CR,4))) -#define TSB_PY_FR1_PY4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR1,4))) -#define TSB_PY_FR4_PY4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR4,4))) -#define TSB_PY_OD_PY4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->OD,4))) -#define TSB_PY_PUP_PY0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,0))) -#define TSB_PY_PUP_PY1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,1))) -#define TSB_PY_PUP_PY2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,2))) -#define TSB_PY_PUP_PY3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,3))) -#define TSB_PY_PUP_PY4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,4))) -#define TSB_PY_PDN_PY0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,0))) -#define TSB_PY_PDN_PY1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,1))) -#define TSB_PY_PDN_PY2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,2))) -#define TSB_PY_PDN_PY3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,3))) -#define TSB_PY_PDN_PY4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,4))) -#define TSB_PY_IE_PY0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,0))) -#define TSB_PY_IE_PY1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,1))) -#define TSB_PY_IE_PY2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,2))) -#define TSB_PY_IE_PY3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,3))) -#define TSB_PY_IE_PY4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,4))) - - -/* Internal High-speed Oscillation Adjustment */ -#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) - - -/* Oscillation Frequency Detector (OFD) */ -#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) -#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) -#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) -#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) - - - -/* Consumer Electronics Control (CEC) */ -#define TSB_CEC0_EN_CECEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->EN,0))) -#define TSB_CEC0_RESET_CECRESET (*((__O uint32_t *)BITBAND_PERI(&TSB_CEC0->RESET,0))) -#define TSB_CEC0_REN_CECREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->REN,0))) -#define TSB_CEC0_RBUF_CECEOM (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,8))) -#define TSB_CEC0_RBUF_CECACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,9))) -#define TSB_CEC0_RCR1_CECOTH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,0))) -#define TSB_CEC0_RCR1_CECRIHLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,1))) -#define TSB_CEC0_RCR1_CECACKDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,24))) -#define TSB_CEC0_RCR3_CECWAVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,0))) -#define TSB_CEC0_RCR3_CECRSTAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,1))) -#define TSB_CEC0_TEN_CECTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,0))) -#define TSB_CEC0_TEN_CECTRANS (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,1))) -#define TSB_CEC0_TBUF_CECTEOM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TBUF,8))) -#define TSB_CEC0_TCR_CECBRD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TCR,4))) -#define TSB_CEC0_RSTAT_CECRIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,0))) -#define TSB_CEC0_RSTAT_CECRISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,1))) -#define TSB_CEC0_RSTAT_CECRIMAX (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,2))) -#define TSB_CEC0_RSTAT_CECRIMIN (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,3))) -#define TSB_CEC0_RSTAT_CECRIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,4))) -#define TSB_CEC0_RSTAT_CECRIOR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,5))) -#define TSB_CEC0_RSTAT_CECRIWAV (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,6))) -#define TSB_CEC0_TSTAT_CECTISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,0))) -#define TSB_CEC0_TSTAT_CECTIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,1))) -#define TSB_CEC0_TSTAT_CECTIAL (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,2))) -#define TSB_CEC0_TSTAT_CECTIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,3))) -#define TSB_CEC0_TSTAT_CECTIUR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,4))) -#define TSB_CEC0_FSSEL_CECCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->FSSEL,0))) - - -/* Remote Control Signal Preprocessor (RMC) */ -#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) -#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) -#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) -#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) -#define TSB_RMC0_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,29))) -#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) -#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) -#define TSB_RMC0_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR3,15))) -#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) -#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) -#define TSB_RMC0_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,8))) -#define TSB_RMC0_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,11))) -#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) -#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) -#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) -#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) -#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) - -#define TSB_RMC1_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->EN,0))) -#define TSB_RMC1_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->REN,0))) -#define TSB_RMC1_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,24))) -#define TSB_RMC1_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,25))) -#define TSB_RMC1_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,29))) -#define TSB_RMC1_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,30))) -#define TSB_RMC1_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,31))) -#define TSB_RMC1_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR3,15))) -#define TSB_RMC1_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR4,7))) -#define TSB_RMC1_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,7))) -#define TSB_RMC1_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,8))) -#define TSB_RMC1_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,11))) -#define TSB_RMC1_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,12))) -#define TSB_RMC1_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,13))) -#define TSB_RMC1_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,14))) -#define TSB_RMC1_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,15))) -#define TSB_RMC1_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->FSSEL,0))) - - -/* */ -#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) -#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) -#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) -#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) -#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) -#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) -#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) -#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) -#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) -#define TSB_PMD0_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,0))) -#define TSB_PMD0_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,1))) -#define TSB_PMD0_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,2))) -#define TSB_PMD0_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,3))) -#define TSB_PMD0_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,7))) -#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) -#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) -#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) -#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) -#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) -#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) -#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) -#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) -#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) -#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) -#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) -#define TSB_PMD0_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,14))) -#define TSB_PMD0_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,15))) -#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) -#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) -#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) -#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) -#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) -#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) -#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) -#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) -#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) -#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) -#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) -#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) -#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) -#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) -#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) -#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) -#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) -#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) -#define TSB_PMD0_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->SYNCCR,0))) - - -/* */ -#define TSB_ISDA_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->EN,0))) -#define TSB_ISDA_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,0))) -#define TSB_ISDA_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,1))) -#define TSB_ISDA_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->OCR0,0))) -#define TSB_ISDA_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CR,0))) -#define TSB_ISDA_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,0))) -#define TSB_ISDA_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,1))) -#define TSB_ISDA_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,2))) -#define TSB_ISDA_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,3))) -#define TSB_ISDA_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,0))) -#define TSB_ISDA_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,1))) -#define TSB_ISDA_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,2))) -#define TSB_ISDA_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,3))) -#define TSB_ISDA_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->INTCR,0))) - -#define TSB_ISDB_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->EN,0))) -#define TSB_ISDB_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,0))) -#define TSB_ISDB_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,1))) -#define TSB_ISDB_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->OCR0,0))) -#define TSB_ISDB_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CR,0))) -#define TSB_ISDB_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,0))) -#define TSB_ISDB_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,1))) -#define TSB_ISDB_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,2))) -#define TSB_ISDB_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,3))) -#define TSB_ISDB_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,0))) -#define TSB_ISDB_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,1))) -#define TSB_ISDB_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,2))) -#define TSB_ISDB_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,3))) -#define TSB_ISDB_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->INTCR,0))) - -#define TSB_ISDC_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->EN,0))) -#define TSB_ISDC_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,0))) -#define TSB_ISDC_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,1))) -#define TSB_ISDC_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->OCR0,0))) -#define TSB_ISDC_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CR,0))) -#define TSB_ISDC_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,0))) -#define TSB_ISDC_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,1))) -#define TSB_ISDC_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,2))) -#define TSB_ISDC_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,3))) -#define TSB_ISDC_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,0))) -#define TSB_ISDC_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,1))) -#define TSB_ISDC_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,2))) -#define TSB_ISDC_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,3))) -#define TSB_ISDC_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->INTCR,0))) - -/** @} */ /* End of group Device_Peripheral_registers */ - -#ifdef __cplusplus -} -#endif - -#endif /* __TMPM4G9_H__ */ - -/** @} */ /* End of group TMPM4G9 */ -/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/startup_TMPM4G9.S b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/startup_TMPM4G9.S deleted file mode 100644 index 4483a37c88c..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/startup_TMPM4G9.S +++ /dev/null @@ -1,533 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM4G9.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for the -; * TOSHIBA 'TMPM4G9' Device Series -; * @version V1.0.6.0 -; * $Date:: 2017-10-04 #$ -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved -; ******************************************************************************* -; */ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b - DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b - DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b - DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b - DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b - DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b - DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b - DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b - DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b - DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b - DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b - DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b - DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b - DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b - DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b - DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b - DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt - DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) - DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) - DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector Interrupt (Unit A) - DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector Interrupt (Unit B) - DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector Interrupt (Unit C) - DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 - DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 - DCD INTLTTMR_IRQHandler ; 24: Long Term Timer Interrupt - DCD INTHDMAATC_IRQHandler ; 25: HDMA Complete of transfer(Unit A) - DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) - DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) - DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) - DCD INTMDMAATC_IRQHandler ; 29: MDMA Complete of transfer(Unit A) - DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A00_B_C01_CPC_IRQHandler; 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A01_B_C01_CPC_IRQHandler; 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A02_B_C01_CPC_IRQHandler; 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A03_B_C01_CPC_IRQHandler; 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A04_B_C01_CPC_IRQHandler; 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A05_B_C01_CPC_IRQHandler; 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A06_B_C01_CPC_IRQHandler; 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A07_B_C01_CPC_IRQHandler; 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A08_B_C01_CPC_IRQHandler; 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A09_B_C01_CPC_IRQHandler; 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A10_B_C01_CPC_IRQHandler; 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A11_B_C01_CPC_IRQHandler; 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A12_B_C01_CPC_IRQHandler; 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A13_B_C01_CPC_IRQHandler; 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt - DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt - DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) - DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) - DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) - DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) - DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) - DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) - DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) - DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) - DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) - DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) - DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) - DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) - DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) - DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface Interrupt - DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) - DCD INTFUART0_IRQHandler ; 107: FUART Interrupt(channel 0) - DCD INTFUART1_IRQHandler ; 108: FUART Interrupt(channel 1) - DCD INTI2C0_IRQHandler ; 109: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 110: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 111: I2C0 bus free interrupt - DCD INTI2C0NACK_IRQHandler ; 112: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 113: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 114: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 115: I2C1 bus free interrupt - DCD INTI2C1NACK_IRQHandler ; 116: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 117: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 118: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 119: I2C2 bus free interrupt - DCD INTI2C2NACK_IRQHandler ; 120: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 121: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 122: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 123: I2C3 bus free interrupt - DCD INTI2C3NACK_IRQHandler ; 124: I2C3 no ack interrupt - DCD INTI2C4_IRQHandler ; 125: I2C4 transmission and reception interrupt - DCD INTI2C4AL_IRQHandler ; 126: I2C4 arbitration lost interrupt - DCD INTI2C4BF_IRQHandler ; 127: I2C4 bus free interrupt - DCD INTI2C4NACK_IRQHandler ; 128: I2C4 no ack interrupt - DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished - DCD INTADAHP_IRQHandler ; 134: ADC High Priority AD conversion interrupt - DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt - DCD INTFLCRDY0_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt - DCD INTFLCRDY1_IRQHandler ; 137: Code FLASH Area2 Ready interrupt - DCD 0 ; 138: Reserved - DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) - DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT INT00_IRQHandler [WEAK] - EXPORT INT01_IRQHandler [WEAK] - EXPORT INT02_IRQHandler [WEAK] - EXPORT INT03_IRQHandler [WEAK] - EXPORT INT04_IRQHandler [WEAK] - EXPORT INT05_IRQHandler [WEAK] - EXPORT INT06_IRQHandler [WEAK] - EXPORT INT07_IRQHandler [WEAK] - EXPORT INT08_IRQHandler [WEAK] - EXPORT INT09_IRQHandler [WEAK] - EXPORT INT10_IRQHandler [WEAK] - EXPORT INT11_IRQHandler [WEAK] - EXPORT INT12_IRQHandler [WEAK] - EXPORT INT13_IRQHandler [WEAK] - EXPORT INT14_IRQHandler [WEAK] - EXPORT INT15_IRQHandler [WEAK] - EXPORT INTRTC_IRQHandler [WEAK] - EXPORT INTCEC0RX_IRQHandler [WEAK] - EXPORT INTCEC0TX_IRQHandler [WEAK] - EXPORT INTISDA_IRQHandler [WEAK] - EXPORT INTISDB_IRQHandler [WEAK] - EXPORT INTISDC_IRQHandler [WEAK] - EXPORT INTRMC0_IRQHandler [WEAK] - EXPORT INTRMC1_IRQHandler [WEAK] - EXPORT INTLTTMR_IRQHandler [WEAK] - EXPORT INTHDMAATC_IRQHandler [WEAK] - EXPORT INTHDMAAERR_IRQHandler [WEAK] - EXPORT INTHDMABTC_IRQHandler [WEAK] - EXPORT INTHDMABERR_IRQHandler [WEAK] - EXPORT INTMDMAATC_IRQHandler [WEAK] - EXPORT INTT32A00_A_CT_IRQHandler [WEAK] - EXPORT INTT32A00_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A01_A_CT_IRQHandler [WEAK] - EXPORT INTT32A01_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A02_A_CT_IRQHandler [WEAK] - EXPORT INTT32A02_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A03_A_CT_IRQHandler [WEAK] - EXPORT INTT32A03_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A04_A_CT_IRQHandler [WEAK] - EXPORT INTT32A04_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A05_A_CT_IRQHandler [WEAK] - EXPORT INTT32A05_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A06_A_CT_IRQHandler [WEAK] - EXPORT INTT32A06_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A07_A_CT_IRQHandler [WEAK] - EXPORT INTT32A07_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A08_A_CT_IRQHandler [WEAK] - EXPORT INTT32A08_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A09_A_CT_IRQHandler [WEAK] - EXPORT INTT32A09_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A10_A_CT_IRQHandler [WEAK] - EXPORT INTT32A10_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A11_A_CT_IRQHandler [WEAK] - EXPORT INTT32A11_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A12_A_CT_IRQHandler [WEAK] - EXPORT INTT32A12_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTT32A13_A_CT_IRQHandler [WEAK] - EXPORT INTT32A13_B_C01_CPC_IRQHandler[WEAK] - EXPORT INTEMG0_IRQHandler [WEAK] - EXPORT INTOVV0_IRQHandler [WEAK] - EXPORT INTPWM0_IRQHandler [WEAK] - EXPORT INTT0RX_IRQHandler [WEAK] - EXPORT INTT0TX_IRQHandler [WEAK] - EXPORT INTT0ERR_IRQHandler [WEAK] - EXPORT INTT1RX_IRQHandler [WEAK] - EXPORT INTT1TX_IRQHandler [WEAK] - EXPORT INTT1ERR_IRQHandler [WEAK] - EXPORT INTT2RX_IRQHandler [WEAK] - EXPORT INTT2TX_IRQHandler [WEAK] - EXPORT INTT2ERR_IRQHandler [WEAK] - EXPORT INTT3RX_IRQHandler [WEAK] - EXPORT INTT3TX_IRQHandler [WEAK] - EXPORT INTT3ERR_IRQHandler [WEAK] - EXPORT INTT4RX_IRQHandler [WEAK] - EXPORT INTT4TX_IRQHandler [WEAK] - EXPORT INTT4ERR_IRQHandler [WEAK] - EXPORT INTT5RX_IRQHandler [WEAK] - EXPORT INTT5TX_IRQHandler [WEAK] - EXPORT INTT5ERR_IRQHandler [WEAK] - EXPORT INTT6RX_IRQHandler [WEAK] - EXPORT INTT6TX_IRQHandler [WEAK] - EXPORT INTT6ERR_IRQHandler [WEAK] - EXPORT INTT7RX_IRQHandler [WEAK] - EXPORT INTT7TX_IRQHandler [WEAK] - EXPORT INTT7ERR_IRQHandler [WEAK] - EXPORT INTT8RX_IRQHandler [WEAK] - EXPORT INTT8TX_IRQHandler [WEAK] - EXPORT INTT8ERR_IRQHandler [WEAK] - EXPORT INTSMI0_IRQHandler [WEAK] - EXPORT INTUART0RX_IRQHandler [WEAK] - EXPORT INTUART0TX_IRQHandler [WEAK] - EXPORT INTUART0ERR_IRQHandler [WEAK] - EXPORT INTUART1RX_IRQHandler [WEAK] - EXPORT INTUART1TX_IRQHandler [WEAK] - EXPORT INTUART1ERR_IRQHandler [WEAK] - EXPORT INTUART2RX_IRQHandler [WEAK] - EXPORT INTUART2TX_IRQHandler [WEAK] - EXPORT INTUART2ERR_IRQHandler [WEAK] - EXPORT INTUART3RX_IRQHandler [WEAK] - EXPORT INTUART3TX_IRQHandler [WEAK] - EXPORT INTUART3ERR_IRQHandler [WEAK] - EXPORT INTUART4RX_IRQHandler [WEAK] - EXPORT INTUART4TX_IRQHandler [WEAK] - EXPORT INTUART4ERR_IRQHandler [WEAK] - EXPORT INTUART5RX_IRQHandler [WEAK] - EXPORT INTUART5TX_IRQHandler [WEAK] - EXPORT INTUART5ERR_IRQHandler [WEAK] - EXPORT INTFUART0_IRQHandler [WEAK] - EXPORT INTFUART1_IRQHandler [WEAK] - EXPORT INTI2C0_IRQHandler [WEAK] - EXPORT INTI2C0AL_IRQHandler [WEAK] - EXPORT INTI2C0BF_IRQHandler [WEAK] - EXPORT INTI2C0NACK_IRQHandler [WEAK] - EXPORT INTI2C1_IRQHandler [WEAK] - EXPORT INTI2C1AL_IRQHandler [WEAK] - EXPORT INTI2C1BF_IRQHandler [WEAK] - EXPORT INTI2C1NACK_IRQHandler [WEAK] - EXPORT INTI2C2_IRQHandler [WEAK] - EXPORT INTI2C2AL_IRQHandler [WEAK] - EXPORT INTI2C2BF_IRQHandler [WEAK] - EXPORT INTI2C2NACK_IRQHandler [WEAK] - EXPORT INTI2C3_IRQHandler [WEAK] - EXPORT INTI2C3AL_IRQHandler [WEAK] - EXPORT INTI2C3BF_IRQHandler [WEAK] - EXPORT INTI2C3NACK_IRQHandler [WEAK] - EXPORT INTI2C4_IRQHandler [WEAK] - EXPORT INTI2C4AL_IRQHandler [WEAK] - EXPORT INTI2C4BF_IRQHandler [WEAK] - EXPORT INTI2C4NACK_IRQHandler [WEAK] - EXPORT INTADACP0_IRQHandler [WEAK] - EXPORT INTADACP1_IRQHandler [WEAK] - EXPORT INTADATRG_IRQHandler [WEAK] - EXPORT INTADASGL_IRQHandler [WEAK] - EXPORT INTADACNT_IRQHandler [WEAK] - EXPORT INTADAHP_IRQHandler [WEAK] - EXPORT INTFLDRDY_IRQHandler [WEAK] - EXPORT INTFLCRDY0_IRQHandler [WEAK] - EXPORT INTFLCRDY1_IRQHandler [WEAK] - EXPORT INTMDMAABERR_IRQHandler [WEAK] - EXPORT INTMDMAADERR_IRQHandler [WEAK] - -INT00_IRQHandler -INT01_IRQHandler -INT02_IRQHandler -INT03_IRQHandler -INT04_IRQHandler -INT05_IRQHandler -INT06_IRQHandler -INT07_IRQHandler -INT08_IRQHandler -INT09_IRQHandler -INT10_IRQHandler -INT11_IRQHandler -INT12_IRQHandler -INT13_IRQHandler -INT14_IRQHandler -INT15_IRQHandler -INTRTC_IRQHandler -INTCEC0RX_IRQHandler -INTCEC0TX_IRQHandler -INTISDA_IRQHandler -INTISDB_IRQHandler -INTISDC_IRQHandler -INTRMC0_IRQHandler -INTRMC1_IRQHandler -INTLTTMR_IRQHandler -INTHDMAATC_IRQHandler -INTHDMAAERR_IRQHandler -INTHDMABTC_IRQHandler -INTHDMABERR_IRQHandler -INTMDMAATC_IRQHandler -INTT32A00_A_CT_IRQHandler -INTT32A00_B_C01_CPC_IRQHandler -INTT32A01_A_CT_IRQHandler -INTT32A01_B_C01_CPC_IRQHandler -INTT32A02_A_CT_IRQHandler -INTT32A02_B_C01_CPC_IRQHandler -INTT32A03_A_CT_IRQHandler -INTT32A03_B_C01_CPC_IRQHandler -INTT32A04_A_CT_IRQHandler -INTT32A04_B_C01_CPC_IRQHandler -INTT32A05_A_CT_IRQHandler -INTT32A05_B_C01_CPC_IRQHandler -INTT32A06_A_CT_IRQHandler -INTT32A06_B_C01_CPC_IRQHandler -INTT32A07_A_CT_IRQHandler -INTT32A07_B_C01_CPC_IRQHandler -INTT32A08_A_CT_IRQHandler -INTT32A08_B_C01_CPC_IRQHandler -INTT32A09_A_CT_IRQHandler -INTT32A09_B_C01_CPC_IRQHandler -INTT32A10_A_CT_IRQHandler -INTT32A10_B_C01_CPC_IRQHandler -INTT32A11_A_CT_IRQHandler -INTT32A11_B_C01_CPC_IRQHandler -INTT32A12_A_CT_IRQHandler -INTT32A12_B_C01_CPC_IRQHandler -INTT32A13_A_CT_IRQHandler -INTT32A13_B_C01_CPC_IRQHandler -INTEMG0_IRQHandler -INTOVV0_IRQHandler -INTPWM0_IRQHandler -INTT0RX_IRQHandler -INTT0TX_IRQHandler -INTT0ERR_IRQHandler -INTT1RX_IRQHandler -INTT1TX_IRQHandler -INTT1ERR_IRQHandler -INTT2RX_IRQHandler -INTT2TX_IRQHandler -INTT2ERR_IRQHandler -INTT3RX_IRQHandler -INTT3TX_IRQHandler -INTT3ERR_IRQHandler -INTT4RX_IRQHandler -INTT4TX_IRQHandler -INTT4ERR_IRQHandler -INTT5RX_IRQHandler -INTT5TX_IRQHandler -INTT5ERR_IRQHandler -INTT6RX_IRQHandler -INTT6TX_IRQHandler -INTT6ERR_IRQHandler -INTT7RX_IRQHandler -INTT7TX_IRQHandler -INTT7ERR_IRQHandler -INTT8RX_IRQHandler -INTT8TX_IRQHandler -INTT8ERR_IRQHandler -INTSMI0_IRQHandler -INTUART0RX_IRQHandler -INTUART0TX_IRQHandler -INTUART0ERR_IRQHandler -INTUART1RX_IRQHandler -INTUART1TX_IRQHandler -INTUART1ERR_IRQHandler -INTUART2RX_IRQHandler -INTUART2TX_IRQHandler -INTUART2ERR_IRQHandler -INTUART3RX_IRQHandler -INTUART3TX_IRQHandler -INTUART3ERR_IRQHandler -INTUART4RX_IRQHandler -INTUART4TX_IRQHandler -INTUART4ERR_IRQHandler -INTUART5RX_IRQHandler -INTUART5TX_IRQHandler -INTUART5ERR_IRQHandler -INTFUART0_IRQHandler -INTFUART1_IRQHandler -INTI2C0_IRQHandler -INTI2C0AL_IRQHandler -INTI2C0BF_IRQHandler -INTI2C0NACK_IRQHandler -INTI2C1_IRQHandler -INTI2C1AL_IRQHandler -INTI2C1BF_IRQHandler -INTI2C1NACK_IRQHandler -INTI2C2_IRQHandler -INTI2C2AL_IRQHandler -INTI2C2BF_IRQHandler -INTI2C2NACK_IRQHandler -INTI2C3_IRQHandler -INTI2C3AL_IRQHandler -INTI2C3BF_IRQHandler -INTI2C3NACK_IRQHandler -INTI2C4_IRQHandler -INTI2C4AL_IRQHandler -INTI2C4BF_IRQHandler -INTI2C4NACK_IRQHandler -INTADACP0_IRQHandler -INTADACP1_IRQHandler -INTADATRG_IRQHandler -INTADASGL_IRQHandler -INTADACNT_IRQHandler -INTADAHP_IRQHandler -INTFLDRDY_IRQHandler -INTFLCRDY0_IRQHandler -INTFLCRDY1_IRQHandler -INTMDMAABERR_IRQHandler -INTMDMAADERR_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct deleted file mode 100644 index 74f7394e479..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct +++ /dev/null @@ -1,50 +0,0 @@ -#! armcc -E -I. --cpu Cortex-M4 -;; TMPM4G9F15FG scatter file - -;; Vector table starts at 0 -;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) -;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) -;; Initial PC == &__main (with LSB set to indicate Thumb) -;; These two values are provided by the library -;; Other vectors must be provided by the user -;; Code starts after the last possible vector -;; Data starts at 0x20000000 -;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) -;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) - -;; Compatible with ISSM model - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x000180000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; TMPM4G9: 1536 KB FLASH (0x180000) + 192 KB SRAM (0x30000) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region -{ - ER_IROM1 MBED_APP_START MBED_APP_SIZE - { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 0x20000320 (0x30000 - 0x320 - Stack_Size) - { - tmpm4g9_fc.o (+RO) - .ANY (+RW, +ZI) - } - - ARM_LIB_STACK (0x20000320+0x30000) EMPTY -Stack_Size { ; stack - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S deleted file mode 100644 index b4c47bbb495..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S +++ /dev/null @@ -1,532 +0,0 @@ -/** - ******************************************************************************* - * @file startup_TMPM4G9.s - * @brief CMSIS Cortex-M4F Core Device Startup File for the - * TOSHIBA 'TMPM4G9' Device Series - * @version - * @date - *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ******************************************************************************* - */ - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.if Heap_Size -.space Heap_Size -.endif -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long INT00_IRQHandler // 0: Interrupt pin 00a/00b - .long INT01_IRQHandler // 1: Interrupt pin 01a/00b - .long INT02_IRQHandler // 2: Interrupt pin 02a/00b - .long INT03_IRQHandler // 3: Interrupt pin 03a/03b - .long INT04_IRQHandler // 4: Interrupt pin 04a/04b - .long INT05_IRQHandler // 5: Interrupt pin 05a/05b - .long INT06_IRQHandler // 6: Interrupt pin 06a/06b - .long INT07_IRQHandler // 7: Interrupt pin 07a/07b - .long INT08_IRQHandler // 8: Interrupt pin 08a/08b - .long INT09_IRQHandler // 9: Interrupt pin 09a/09b - .long INT10_IRQHandler // 10: Interrupt pin 10a/10b - .long INT11_IRQHandler // 11: Interrupt pin 11a/11b - .long INT12_IRQHandler // 12: Interrupt pin 12a/12b - .long INT13_IRQHandler // 13: Interrupt pin 13a/13b - .long INT14_IRQHandler // 14: Interrupt pin 14a/14b - .long INT15_IRQHandler // 15: Interrupt pin 15a/15b - .long INTRTC_IRQHandler // 16: Real time clock(XHz) interrupt - .long INTCEC0RX_IRQHandler // 17: CEC reception interrupt (channel 0) - .long INTCEC0TX_IRQHandler // 18: CEC transmission interrupt (channel 0) - .long INTISDA_IRQHandler // 19: Interval Sensing Detector Interrupt (Unit A) - .long INTISDB_IRQHandler // 20: Interval Sensing Detector Interrupt (Unit B) - .long INTISDC_IRQHandler // 21: Interval Sensing Detector Interrupt (Unit C) - .long INTRMC0_IRQHandler // 22: Remote control reception interrupt 0 - .long INTRMC1_IRQHandler // 23: Remote control reception interrupt 1 - .long INTLTTMR_IRQHandler // 24: Long Term Timer Interrupt - .long INTHDMAATC_IRQHandler // 25: HDMA Complete of transfer(Unit A) - .long INTHDMAAERR_IRQHandler // 26: HDMA transfer error(Unit A) - .long INTHDMABTC_IRQHandler // 27: HDMA end of transfer(Unit B) - .long INTHDMABERR_IRQHandler // 28: HDMA transfer error(Unit B) - .long INTMDMAATC_IRQHandler // 29: MDMA Complete of transfer(Unit A) - .long INTT32A00_A_CT_IRQHandler // 30: T32A00 TimerA All Interrupt/Timer Interrupt C - .long INTT32A00_B_C01_CPC_IRQHandler// 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A01_A_CT_IRQHandler // 32: T32A01 TimerA All Interrupt/Timer Interrupt C - .long INTT32A01_B_C01_CPC_IRQHandler// 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A02_A_CT_IRQHandler // 34: T32A02 TimerA All Interrupt/Timer Interrupt C - .long INTT32A02_B_C01_CPC_IRQHandler// 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A03_A_CT_IRQHandler // 36: T32A03 TimerA All Interrupt/Timer Interrupt C - .long INTT32A03_B_C01_CPC_IRQHandler// 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A04_A_CT_IRQHandler // 38: T32A04 TimerA All Interrupt/Timer Interrupt C - .long INTT32A04_B_C01_CPC_IRQHandler// 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A05_A_CT_IRQHandler // 40: T32A05 TimerA All Interrupt/Timer Interrupt C - .long INTT32A05_B_C01_CPC_IRQHandler// 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A06_A_CT_IRQHandler // 42: T32A06 TimerA All Interrupt/Timer Interrupt C - .long INTT32A06_B_C01_CPC_IRQHandler// 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A07_A_CT_IRQHandler // 44: T32A07 TimerA All Interrupt/Timer Interrupt C - .long INTT32A07_B_C01_CPC_IRQHandler// 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A08_A_CT_IRQHandler // 46: T32A08 TimerA All Interrupt/Timer Interrupt C - .long INTT32A08_B_C01_CPC_IRQHandler// 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A09_A_CT_IRQHandler // 48: T32A09 TimerA All Interrupt/Timer Interrupt C - .long INTT32A09_B_C01_CPC_IRQHandler// 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A10_A_CT_IRQHandler // 50: T32A10 TimerA All Interrupt/Timer Interrupt C - .long INTT32A10_B_C01_CPC_IRQHandler// 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A11_A_CT_IRQHandler // 52: T32A11 TimerA All Interrupt/Timer Interrupt C - .long INTT32A11_B_C01_CPC_IRQHandler// 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A12_A_CT_IRQHandler // 54: T32A12 TimerA All Interrupt/Timer Interrupt C - .long INTT32A12_B_C01_CPC_IRQHandler// 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTT32A13_A_CT_IRQHandler // 56: T32A13 TimerA All Interrupt/Timer Interrupt C - .long INTT32A13_B_C01_CPC_IRQHandler// 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - .long INTEMG0_IRQHandler // 58: PMD0 EMG interrupt - .long INTOVV0_IRQHandler // 59: PMD0 OVV interrupt - .long INTPWM0_IRQHandler // 60: PMD0 interrupt - .long INTT0RX_IRQHandler // 61: TSPI/SIO reception (channel 0) - .long INTT0TX_IRQHandler // 62: TSPI/SIO transmit (channel 0) - .long INTT0ERR_IRQHandler // 63: TSPI/SIO error (channel 0) - .long INTT1RX_IRQHandler // 64: TSPI/SIO reception (channel 1) - .long INTT1TX_IRQHandler // 65: TSPI/SIO transmit (channel 1) - .long INTT1ERR_IRQHandler // 66: TSPI/SIO error (channel 1) - .long INTT2RX_IRQHandler // 67: TSPI/SIO reception (channel 2) - .long INTT2TX_IRQHandler // 68: TSPI/SIO transmit (channel 2) - .long INTT2ERR_IRQHandler // 69: TSPI/SIO error (channel 2) - .long INTT3RX_IRQHandler // 70: TSPI/SIO reception (channel 3) - .long INTT3TX_IRQHandler // 71: TSPI/SIO transmit (channel 3) - .long INTT3ERR_IRQHandler // 72: TSPI/SIO error (channel 3) - .long INTT4RX_IRQHandler // 73: TSPI/SIO reception (channel 4) - .long INTT4TX_IRQHandler // 74: TSPI/SIO transmit (channel 4) - .long INTT4ERR_IRQHandler // 75: TSPI/SIO error (channel 4) - .long INTT5RX_IRQHandler // 76: TSPI/SIO reception (channel 5) - .long INTT5TX_IRQHandler // 77: TSPI/SIO transmit (channel 5) - .long INTT5ERR_IRQHandler // 78: TSPI/SIO error (channel 5) - .long INTT6RX_IRQHandler // 79: TSPI/SIO reception (channel 6) - .long INTT6TX_IRQHandler // 80: TSPI/SIO transmit (channel 6) - .long INTT6ERR_IRQHandler // 81: TSPI/SIO error (channel 6) - .long INTT7RX_IRQHandler // 82: TSPI/SIO reception (channel 7) - .long INTT7TX_IRQHandler // 83: TSPI/SIO transmit (channel 7) - .long INTT7ERR_IRQHandler // 84: TSPI/SIO error (channel 7) - .long INTT8RX_IRQHandler // 85: TSPI/SIO reception (channel 8) - .long INTT8TX_IRQHandler // 86: TSPI/SIO transmit (channel 8) - .long INTT8ERR_IRQHandler // 87: TSPI/SIO error (channel 8) - .long INTSMI0_IRQHandler // 88: Serial Memory Interface Interrupt - .long INTUART0RX_IRQHandler // 89: UART reception (channel 0) - .long INTUART0TX_IRQHandler // 90: UART transmit (channel 0) - .long INTUART0ERR_IRQHandler // 91: UART error (channel 0) - .long INTUART1RX_IRQHandler // 92: UART reception (channel 1) - .long INTUART1TX_IRQHandler // 93: UART transmit (channel 1) - .long INTUART1ERR_IRQHandler // 94: UART error (channel 1) - .long INTUART2RX_IRQHandler // 95: UART reception (channel 2) - .long INTUART2TX_IRQHandler // 96: UART transmit (channel 2) - .long INTUART2ERR_IRQHandler // 97: UART error (channel 2) - .long INTUART3RX_IRQHandler // 98: UART reception (channel 3) - .long INTUART3TX_IRQHandler // 99: UART transmit (channel 3) - .long INTUART3ERR_IRQHandler // 100: UART error (channel 3) - .long INTUART4RX_IRQHandler // 101: UART reception (channel 4) - .long INTUART4TX_IRQHandler // 102: UART transmit (channel 4) - .long INTUART4ERR_IRQHandler // 103: UART error (channel 4) - .long INTUART5RX_IRQHandler // 104: UART reception (channel 5) - .long INTUART5TX_IRQHandler // 105: UART transmit (channel 5) - .long INTUART5ERR_IRQHandler // 106: UART error (channel 5) - .long INTFUART0_IRQHandler // 107: FUART Interrupt(channel 0) - .long INTFUART1_IRQHandler // 108: FUART Interrupt(channel 1) - .long INTI2C0_IRQHandler // 109: I2C0 transmission and reception interrupt - .long INTI2C0AL_IRQHandler // 110: I2C0 arbitration lost interrupt - .long INTI2C0BF_IRQHandler // 111: I2C0 bus free interrupt - .long INTI2C0NACK_IRQHandler // 112: I2C0 no ack interrupt - .long INTI2C1_IRQHandler // 113: I2C1 transmission and reception interrupt - .long INTI2C1AL_IRQHandler // 114: I2C1 arbitration lost interrupt - .long INTI2C1BF_IRQHandler // 115: I2C1 bus free interrupt - .long INTI2C1NACK_IRQHandler // 116: I2C1 no ack interrupt - .long INTI2C2_IRQHandler // 117: I2C2 transmission and reception interrupt - .long INTI2C2AL_IRQHandler // 118: I2C2 arbitration lost interrupt - .long INTI2C2BF_IRQHandler // 119: I2C2 bus free interrupt - .long INTI2C2NACK_IRQHandler // 120: I2C2 no ack interrupt - .long INTI2C3_IRQHandler // 121: I2C3 transmission and reception interrupt - .long INTI2C3AL_IRQHandler // 122: I2C3 arbitration lost interrupt - .long INTI2C3BF_IRQHandler // 123: I2C3 bus free interrupt - .long INTI2C3NACK_IRQHandler // 124: I2C3 no ack interrupt - .long INTI2C4_IRQHandler // 125: I2C4 transmission and reception interrupt - .long INTI2C4AL_IRQHandler // 126: I2C4 arbitration lost interrupt - .long INTI2C4BF_IRQHandler // 127: I2C4 bus free interrupt - .long INTI2C4NACK_IRQHandler // 128: I2C4 no ack interrupt - .long INTADACP0_IRQHandler // 129: ADC conversion monitoring function interrupt 0 - .long INTADACP1_IRQHandler // 130: ADC conversion monitoring function interrupt 1 - .long INTADATRG_IRQHandler // 131: ADC conversion triggered by General purpose is finished - .long INTADASGL_IRQHandler // 132: ADC conversion triggered by Single program is finished - .long INTADACNT_IRQHandler // 133: ADC conversion triggered by Continuity program is finished - .long INTADAHP_IRQHandler // 134: ADC High Priority AD conversion interrupt - .long INTFLDRDY_IRQHandler // 135: Data FLASH Ready interrupt - .long INTFLCRDY0_IRQHandler // 136: Code FLASH Area0/1 Ready interrupt - .long INTFLCRDY1_IRQHandler // 137: Code FLASH Area2 Ready interrupt - .long 0 // 138: Reserved - .long INTMDMAABERR_IRQHandler // 139: MDMA bus error(Unit A) - .long INTMDMAADERR_IRQHandler // 140: MDMA descriptor error(Unit A) - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler INT00_IRQHandler - def_irq_handler INT01_IRQHandler - def_irq_handler INT02_IRQHandler - def_irq_handler INT03_IRQHandler - def_irq_handler INT04_IRQHandler - def_irq_handler INT05_IRQHandler - def_irq_handler INT06_IRQHandler - def_irq_handler INT07_IRQHandler - def_irq_handler INT08_IRQHandler - def_irq_handler INT09_IRQHandler - def_irq_handler INT10_IRQHandler - def_irq_handler INT11_IRQHandler - def_irq_handler INT12_IRQHandler - def_irq_handler INT13_IRQHandler - def_irq_handler INT14_IRQHandler - def_irq_handler INT15_IRQHandler - def_irq_handler INTRTC_IRQHandler - def_irq_handler INTCEC0RX_IRQHandler - def_irq_handler INTCEC0TX_IRQHandler - def_irq_handler INTISDA_IRQHandler - def_irq_handler INTISDB_IRQHandler - def_irq_handler INTISDC_IRQHandler - def_irq_handler INTRMC0_IRQHandler - def_irq_handler INTRMC1_IRQHandler - def_irq_handler INTLTTMR_IRQHandler - def_irq_handler INTHDMAATC_IRQHandler - def_irq_handler INTHDMAAERR_IRQHandler - def_irq_handler INTHDMABTC_IRQHandler - def_irq_handler INTHDMABERR_IRQHandler - def_irq_handler INTMDMAATC_IRQHandler - def_irq_handler INTT32A00_A_CT_IRQHandler - def_irq_handler INTT32A00_B_C01_CPC_IRQHandler - def_irq_handler INTT32A01_A_CT_IRQHandler - def_irq_handler INTT32A01_B_C01_CPC_IRQHandler - def_irq_handler INTT32A02_A_CT_IRQHandler - def_irq_handler INTT32A02_B_C01_CPC_IRQHandler - def_irq_handler INTT32A03_A_CT_IRQHandler - def_irq_handler INTT32A03_B_C01_CPC_IRQHandler - def_irq_handler INTT32A04_A_CT_IRQHandler - def_irq_handler INTT32A04_B_C01_CPC_IRQHandler - def_irq_handler INTT32A05_A_CT_IRQHandler - def_irq_handler INTT32A05_B_C01_CPC_IRQHandler - def_irq_handler INTT32A06_A_CT_IRQHandler - def_irq_handler INTT32A06_B_C01_CPC_IRQHandler - def_irq_handler INTT32A07_A_CT_IRQHandler - def_irq_handler INTT32A07_B_C01_CPC_IRQHandler - def_irq_handler INTT32A08_A_CT_IRQHandler - def_irq_handler INTT32A08_B_C01_CPC_IRQHandler - def_irq_handler INTT32A09_A_CT_IRQHandler - def_irq_handler INTT32A09_B_C01_CPC_IRQHandler - def_irq_handler INTT32A10_A_CT_IRQHandler - def_irq_handler INTT32A10_B_C01_CPC_IRQHandler - def_irq_handler INTT32A11_A_CT_IRQHandler - def_irq_handler INTT32A11_B_C01_CPC_IRQHandler - def_irq_handler INTT32A12_A_CT_IRQHandler - def_irq_handler INTT32A12_B_C01_CPC_IRQHandler - def_irq_handler INTT32A13_A_CT_IRQHandler - def_irq_handler INTT32A13_B_C01_CPC_IRQHandler - def_irq_handler INTEMG0_IRQHandler - def_irq_handler INTOVV0_IRQHandler - def_irq_handler INTPWM0_IRQHandler - def_irq_handler INTT0RX_IRQHandler - def_irq_handler INTT0TX_IRQHandler - def_irq_handler INTT0ERR_IRQHandler - def_irq_handler INTT1RX_IRQHandler - def_irq_handler INTT1TX_IRQHandler - def_irq_handler INTT1ERR_IRQHandler - def_irq_handler INTT2RX_IRQHandler - def_irq_handler INTT2TX_IRQHandler - def_irq_handler INTT2ERR_IRQHandler - def_irq_handler INTT3RX_IRQHandler - def_irq_handler INTT3TX_IRQHandler - def_irq_handler INTT3ERR_IRQHandler - def_irq_handler INTT4RX_IRQHandler - def_irq_handler INTT4TX_IRQHandler - def_irq_handler INTT4ERR_IRQHandler - def_irq_handler INTT5RX_IRQHandler - def_irq_handler INTT5TX_IRQHandler - def_irq_handler INTT5ERR_IRQHandler - def_irq_handler INTT6RX_IRQHandler - def_irq_handler INTT6TX_IRQHandler - def_irq_handler INTT6ERR_IRQHandler - def_irq_handler INTT7RX_IRQHandler - def_irq_handler INTT7TX_IRQHandler - def_irq_handler INTT7ERR_IRQHandler - def_irq_handler INTT8RX_IRQHandler - def_irq_handler INTT8TX_IRQHandler - def_irq_handler INTT8ERR_IRQHandler - def_irq_handler INTSMI0_IRQHandler - def_irq_handler INTUART0RX_IRQHandler - def_irq_handler INTUART0TX_IRQHandler - def_irq_handler INTUART0ERR_IRQHandler - def_irq_handler INTUART1RX_IRQHandler - def_irq_handler INTUART1TX_IRQHandler - def_irq_handler INTUART1ERR_IRQHandler - def_irq_handler INTUART2RX_IRQHandler - def_irq_handler INTUART2TX_IRQHandler - def_irq_handler INTUART2ERR_IRQHandler - def_irq_handler INTUART3RX_IRQHandler - def_irq_handler INTUART3TX_IRQHandler - def_irq_handler INTUART3ERR_IRQHandler - def_irq_handler INTUART4RX_IRQHandler - def_irq_handler INTUART4TX_IRQHandler - def_irq_handler INTUART4ERR_IRQHandler - def_irq_handler INTUART5RX_IRQHandler - def_irq_handler INTUART5TX_IRQHandler - def_irq_handler INTUART5ERR_IRQHandler - def_irq_handler INTFUART0_IRQHandler - def_irq_handler INTFUART1_IRQHandler - def_irq_handler INTI2C0_IRQHandler - def_irq_handler INTI2C0AL_IRQHandler - def_irq_handler INTI2C0BF_IRQHandler - def_irq_handler INTI2C0NACK_IRQHandler - def_irq_handler INTI2C1_IRQHandler - def_irq_handler INTI2C1AL_IRQHandler - def_irq_handler INTI2C1BF_IRQHandler - def_irq_handler INTI2C1NACK_IRQHandler - def_irq_handler INTI2C2_IRQHandler - def_irq_handler INTI2C2AL_IRQHandler - def_irq_handler INTI2C2BF_IRQHandler - def_irq_handler INTI2C2NACK_IRQHandler - def_irq_handler INTI2C3_IRQHandler - def_irq_handler INTI2C3AL_IRQHandler - def_irq_handler INTI2C3BF_IRQHandler - def_irq_handler INTI2C3NACK_IRQHandler - def_irq_handler INTI2C4_IRQHandler - def_irq_handler INTI2C4AL_IRQHandler - def_irq_handler INTI2C4BF_IRQHandler - def_irq_handler INTI2C4NACK_IRQHandler - def_irq_handler INTADACP0_IRQHandler - def_irq_handler INTADACP1_IRQHandler - def_irq_handler INTADATRG_IRQHandler - def_irq_handler INTADASGL_IRQHandler - def_irq_handler INTADACNT_IRQHandler - def_irq_handler INTADAHP_IRQHandler - def_irq_handler INTFLDRDY_IRQHandler - def_irq_handler INTFLCRDY0_IRQHandler - def_irq_handler INTFLCRDY1_IRQHandler - //def_irq_handler 0 - def_irq_handler INTMDMAABERR_IRQHandler - def_irq_handler INTMDMAADERR_IRQHandler - - .end diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld deleted file mode 100644 index 3a3a846b764..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld +++ /dev/null @@ -1,214 +0,0 @@ -/* Linker script for Toshiba TMPM4G9 */ - -/* Linker script to configure memory regions. */ - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x180000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = 0x20000320, LENGTH = (192K - 0x320) -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - *(.ram_func*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/startup_TMPM4G9.S b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/startup_TMPM4G9.S deleted file mode 100644 index ac05911602d..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/startup_TMPM4G9.S +++ /dev/null @@ -1,952 +0,0 @@ -;/** -; ******************************************************************************* -; * @file startup_TMPM4G9.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for the -; * TOSHIBA 'TMPM4G9' Device Series -; * @version V1.0.9.0 -; * $Date:: 2018-04-02 #$ -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2018 All rights reserved -; ******************************************************************************* -; */ -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b - DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b - DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b - DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b - DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b - DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b - DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b - DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b - DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b - DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b - DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b - DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b - DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b - DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b - DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b - DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b - DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt - DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) - DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) - DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector Interrupt (Unit A) - DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector Interrupt (Unit B) - DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector Interrupt (Unit C) - DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 - DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 - DCD INTLTTMR0_IRQHandler ; 24: Long Term Timer Interrupt(channel 0) - DCD INTHDMAATC_IRQHandler ; 25: HDMA Complete of transfer(Unit A) - DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) - DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) - DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) - DCD INTMDMAATC_IRQHandler ; 29: MDMA Complete of transfer(Unit A) - DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A00_B_C01_CPC_IRQHandler; 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A01_B_C01_CPC_IRQHandler; 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A02_B_C01_CPC_IRQHandler; 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A03_B_C01_CPC_IRQHandler; 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A04_B_C01_CPC_IRQHandler; 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A05_B_C01_CPC_IRQHandler; 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A06_B_C01_CPC_IRQHandler; 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A07_B_C01_CPC_IRQHandler; 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A08_B_C01_CPC_IRQHandler; 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A09_B_C01_CPC_IRQHandler; 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A10_B_C01_CPC_IRQHandler; 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A11_B_C01_CPC_IRQHandler; 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A12_B_C01_CPC_IRQHandler; 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA All Interrupt/Timer Interrupt C - DCD INTT32A13_B_C01_CPC_IRQHandler; 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C - DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt - DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt - DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt - DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) - DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) - DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) - DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) - DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) - DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) - DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) - DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) - DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) - DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) - DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) - DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) - DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) - DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) - DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) - DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) - DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) - DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) - DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) - DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) - DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) - DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) - DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) - DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) - DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) - DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) - DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) - DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface Interrupt - DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) - DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) - DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) - DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) - DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) - DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) - DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) - DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) - DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) - DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) - DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) - DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) - DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) - DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) - DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) - DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) - DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) - DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) - DCD INTFUART0_IRQHandler ; 107: FUART Interrupt(channel 0) - DCD INTFUART1_IRQHandler ; 108: FUART Interrupt(channel 1) - DCD INTI2C0_IRQHandler ; 109: I2C0 transmission and reception interrupt - DCD INTI2C0AL_IRQHandler ; 110: I2C0 arbitration lost interrupt - DCD INTI2C0BF_IRQHandler ; 111: I2C0 bus free interrupt - DCD INTI2C0NACK_IRQHandler ; 112: I2C0 no ack interrupt - DCD INTI2C1_IRQHandler ; 113: I2C1 transmission and reception interrupt - DCD INTI2C1AL_IRQHandler ; 114: I2C1 arbitration lost interrupt - DCD INTI2C1BF_IRQHandler ; 115: I2C1 bus free interrupt - DCD INTI2C1NACK_IRQHandler ; 116: I2C1 no ack interrupt - DCD INTI2C2_IRQHandler ; 117: I2C2 transmission and reception interrupt - DCD INTI2C2AL_IRQHandler ; 118: I2C2 arbitration lost interrupt - DCD INTI2C2BF_IRQHandler ; 119: I2C2 bus free interrupt - DCD INTI2C2NACK_IRQHandler ; 120: I2C2 no ack interrupt - DCD INTI2C3_IRQHandler ; 121: I2C3 transmission and reception interrupt - DCD INTI2C3AL_IRQHandler ; 122: I2C3 arbitration lost interrupt - DCD INTI2C3BF_IRQHandler ; 123: I2C3 bus free interrupt - DCD INTI2C3NACK_IRQHandler ; 124: I2C3 no ack interrupt - DCD INTI2C4_IRQHandler ; 125: I2C4 transmission and reception interrupt - DCD INTI2C4AL_IRQHandler ; 126: I2C4 arbitration lost interrupt - DCD INTI2C4BF_IRQHandler ; 127: I2C4 bus free interrupt - DCD INTI2C4NACK_IRQHandler ; 128: I2C4 no ack interrupt - DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 - DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 - DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished - DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished - DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished - DCD INTADAHP_IRQHandler ; 134: ADC High Priority AD conversion interrupt - DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt - DCD INTFLCRDY0_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt - DCD INTFLCRDY1_IRQHandler ; 137: Code FLASH Area2 Ready interrupt - DCD 0 ; 138: Reserved - DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) - DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK INT00_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT00_IRQHandler - B INT00_IRQHandler - - PUBWEAK INT01_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT01_IRQHandler - B INT01_IRQHandler - - PUBWEAK INT02_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT02_IRQHandler - B INT02_IRQHandler - - PUBWEAK INT03_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT03_IRQHandler - B INT03_IRQHandler - - PUBWEAK INT04_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT04_IRQHandler - B INT04_IRQHandler - - PUBWEAK INT05_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT05_IRQHandler - B INT05_IRQHandler - - PUBWEAK INT06_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT06_IRQHandler - B INT06_IRQHandler - - PUBWEAK INT07_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT07_IRQHandler - B INT07_IRQHandler - - PUBWEAK INT08_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT08_IRQHandler - B INT08_IRQHandler - - PUBWEAK INT09_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT09_IRQHandler - B INT09_IRQHandler - - PUBWEAK INT10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT10_IRQHandler - B INT10_IRQHandler - - PUBWEAK INT11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT11_IRQHandler - B INT11_IRQHandler - - PUBWEAK INT12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT12_IRQHandler - B INT12_IRQHandler - - PUBWEAK INT13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT13_IRQHandler - B INT13_IRQHandler - - PUBWEAK INT14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT14_IRQHandler - B INT14_IRQHandler - - PUBWEAK INT15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INT15_IRQHandler - B INT15_IRQHandler - - PUBWEAK INTRTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRTC_IRQHandler - B INTRTC_IRQHandler - - PUBWEAK INTCEC0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTCEC0RX_IRQHandler - B INTCEC0RX_IRQHandler - - PUBWEAK INTCEC0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTCEC0TX_IRQHandler - B INTCEC0TX_IRQHandler - - PUBWEAK INTISDA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTISDA_IRQHandler - B INTISDA_IRQHandler - - PUBWEAK INTISDB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTISDB_IRQHandler - B INTISDB_IRQHandler - - PUBWEAK INTISDC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTISDC_IRQHandler - B INTISDC_IRQHandler - - PUBWEAK INTRMC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRMC0_IRQHandler - B INTRMC0_IRQHandler - - PUBWEAK INTRMC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTRMC1_IRQHandler - B INTRMC1_IRQHandler - - PUBWEAK INTLTTMR0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTLTTMR0_IRQHandler - B INTLTTMR0_IRQHandler - - PUBWEAK INTHDMAATC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTHDMAATC_IRQHandler - B INTHDMAATC_IRQHandler - - PUBWEAK INTHDMAAERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTHDMAAERR_IRQHandler - B INTHDMAAERR_IRQHandler - - PUBWEAK INTHDMABTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTHDMABTC_IRQHandler - B INTHDMABTC_IRQHandler - - PUBWEAK INTHDMABERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTHDMABERR_IRQHandler - B INTHDMABERR_IRQHandler - - PUBWEAK INTMDMAATC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTMDMAATC_IRQHandler - B INTMDMAATC_IRQHandler - - PUBWEAK INTT32A00_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00_A_CT_IRQHandler - B INTT32A00_A_CT_IRQHandler - - PUBWEAK INTT32A00_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A00_B_C01_CPC_IRQHandler - B INTT32A00_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A01_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01_A_CT_IRQHandler - B INTT32A01_A_CT_IRQHandler - - PUBWEAK INTT32A01_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A01_B_C01_CPC_IRQHandler - B INTT32A01_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A02_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02_A_CT_IRQHandler - B INTT32A02_A_CT_IRQHandler - - PUBWEAK INTT32A02_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A02_B_C01_CPC_IRQHandler - B INTT32A02_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A03_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03_A_CT_IRQHandler - B INTT32A03_A_CT_IRQHandler - - PUBWEAK INTT32A03_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A03_B_C01_CPC_IRQHandler - B INTT32A03_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A04_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04_A_CT_IRQHandler - B INTT32A04_A_CT_IRQHandler - - PUBWEAK INTT32A04_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A04_B_C01_CPC_IRQHandler - B INTT32A04_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A05_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05_A_CT_IRQHandler - B INTT32A05_A_CT_IRQHandler - - PUBWEAK INTT32A05_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A05_B_C01_CPC_IRQHandler - B INTT32A05_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A06_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06_A_CT_IRQHandler - B INTT32A06_A_CT_IRQHandler - - PUBWEAK INTT32A06_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A06_B_C01_CPC_IRQHandler - B INTT32A06_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A07_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07_A_CT_IRQHandler - B INTT32A07_A_CT_IRQHandler - - PUBWEAK INTT32A07_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A07_B_C01_CPC_IRQHandler - B INTT32A07_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A08_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A08_A_CT_IRQHandler - B INTT32A08_A_CT_IRQHandler - - PUBWEAK INTT32A08_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A08_B_C01_CPC_IRQHandler - B INTT32A08_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A09_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A09_A_CT_IRQHandler - B INTT32A09_A_CT_IRQHandler - - PUBWEAK INTT32A09_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A09_B_C01_CPC_IRQHandler - B INTT32A09_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A10_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A10_A_CT_IRQHandler - B INTT32A10_A_CT_IRQHandler - - PUBWEAK INTT32A10_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A10_B_C01_CPC_IRQHandler - B INTT32A10_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A11_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A11_A_CT_IRQHandler - B INTT32A11_A_CT_IRQHandler - - PUBWEAK INTT32A11_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A11_B_C01_CPC_IRQHandler - B INTT32A11_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A12_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A12_A_CT_IRQHandler - B INTT32A12_A_CT_IRQHandler - - PUBWEAK INTT32A12_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A12_B_C01_CPC_IRQHandler - B INTT32A12_B_C01_CPC_IRQHandler - - PUBWEAK INTT32A13_A_CT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A13_A_CT_IRQHandler - B INTT32A13_A_CT_IRQHandler - - PUBWEAK INTT32A13_B_C01_CPC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT32A13_B_C01_CPC_IRQHandler - B INTT32A13_B_C01_CPC_IRQHandler - - PUBWEAK INTEMG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTEMG0_IRQHandler - B INTEMG0_IRQHandler - - PUBWEAK INTOVV0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTOVV0_IRQHandler - B INTOVV0_IRQHandler - - PUBWEAK INTPWM0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTPWM0_IRQHandler - B INTPWM0_IRQHandler - - PUBWEAK INTT0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0RX_IRQHandler - B INTT0RX_IRQHandler - - PUBWEAK INTT0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0TX_IRQHandler - B INTT0TX_IRQHandler - - PUBWEAK INTT0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT0ERR_IRQHandler - B INTT0ERR_IRQHandler - - PUBWEAK INTT1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1RX_IRQHandler - B INTT1RX_IRQHandler - - PUBWEAK INTT1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1TX_IRQHandler - B INTT1TX_IRQHandler - - PUBWEAK INTT1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT1ERR_IRQHandler - B INTT1ERR_IRQHandler - - PUBWEAK INTT2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2RX_IRQHandler - B INTT2RX_IRQHandler - - PUBWEAK INTT2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2TX_IRQHandler - B INTT2TX_IRQHandler - - PUBWEAK INTT2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT2ERR_IRQHandler - B INTT2ERR_IRQHandler - - PUBWEAK INTT3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3RX_IRQHandler - B INTT3RX_IRQHandler - - PUBWEAK INTT3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3TX_IRQHandler - B INTT3TX_IRQHandler - - PUBWEAK INTT3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT3ERR_IRQHandler - B INTT3ERR_IRQHandler - - PUBWEAK INTT4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4RX_IRQHandler - B INTT4RX_IRQHandler - - PUBWEAK INTT4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4TX_IRQHandler - B INTT4TX_IRQHandler - - PUBWEAK INTT4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT4ERR_IRQHandler - B INTT4ERR_IRQHandler - - PUBWEAK INTT5RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT5RX_IRQHandler - B INTT5RX_IRQHandler - - PUBWEAK INTT5TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT5TX_IRQHandler - B INTT5TX_IRQHandler - - PUBWEAK INTT5ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT5ERR_IRQHandler - B INTT5ERR_IRQHandler - - PUBWEAK INTT6RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT6RX_IRQHandler - B INTT6RX_IRQHandler - - PUBWEAK INTT6TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT6TX_IRQHandler - B INTT6TX_IRQHandler - - PUBWEAK INTT6ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT6ERR_IRQHandler - B INTT6ERR_IRQHandler - - PUBWEAK INTT7RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT7RX_IRQHandler - B INTT7RX_IRQHandler - - PUBWEAK INTT7TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT7TX_IRQHandler - B INTT7TX_IRQHandler - - PUBWEAK INTT7ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT7ERR_IRQHandler - B INTT7ERR_IRQHandler - - PUBWEAK INTT8RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT8RX_IRQHandler - B INTT8RX_IRQHandler - - PUBWEAK INTT8TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT8TX_IRQHandler - B INTT8TX_IRQHandler - - PUBWEAK INTT8ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTT8ERR_IRQHandler - B INTT8ERR_IRQHandler - - PUBWEAK INTSMI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTSMI0_IRQHandler - B INTSMI0_IRQHandler - - PUBWEAK INTUART0RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0RX_IRQHandler - B INTUART0RX_IRQHandler - - PUBWEAK INTUART0TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0TX_IRQHandler - B INTUART0TX_IRQHandler - - PUBWEAK INTUART0ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART0ERR_IRQHandler - B INTUART0ERR_IRQHandler - - PUBWEAK INTUART1RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1RX_IRQHandler - B INTUART1RX_IRQHandler - - PUBWEAK INTUART1TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1TX_IRQHandler - B INTUART1TX_IRQHandler - - PUBWEAK INTUART1ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART1ERR_IRQHandler - B INTUART1ERR_IRQHandler - - PUBWEAK INTUART2RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2RX_IRQHandler - B INTUART2RX_IRQHandler - - PUBWEAK INTUART2TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2TX_IRQHandler - B INTUART2TX_IRQHandler - - PUBWEAK INTUART2ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART2ERR_IRQHandler - B INTUART2ERR_IRQHandler - - PUBWEAK INTUART3RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3RX_IRQHandler - B INTUART3RX_IRQHandler - - PUBWEAK INTUART3TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3TX_IRQHandler - B INTUART3TX_IRQHandler - - PUBWEAK INTUART3ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART3ERR_IRQHandler - B INTUART3ERR_IRQHandler - - PUBWEAK INTUART4RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4RX_IRQHandler - B INTUART4RX_IRQHandler - - PUBWEAK INTUART4TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4TX_IRQHandler - B INTUART4TX_IRQHandler - - PUBWEAK INTUART4ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART4ERR_IRQHandler - B INTUART4ERR_IRQHandler - - PUBWEAK INTUART5RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5RX_IRQHandler - B INTUART5RX_IRQHandler - - PUBWEAK INTUART5TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5TX_IRQHandler - B INTUART5TX_IRQHandler - - PUBWEAK INTUART5ERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTUART5ERR_IRQHandler - B INTUART5ERR_IRQHandler - - PUBWEAK INTFUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFUART0_IRQHandler - B INTFUART0_IRQHandler - - PUBWEAK INTFUART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFUART1_IRQHandler - B INTFUART1_IRQHandler - - PUBWEAK INTI2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0_IRQHandler - B INTI2C0_IRQHandler - - PUBWEAK INTI2C0AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0AL_IRQHandler - B INTI2C0AL_IRQHandler - - PUBWEAK INTI2C0BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0BF_IRQHandler - B INTI2C0BF_IRQHandler - - PUBWEAK INTI2C0NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C0NACK_IRQHandler - B INTI2C0NACK_IRQHandler - - PUBWEAK INTI2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1_IRQHandler - B INTI2C1_IRQHandler - - PUBWEAK INTI2C1AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1AL_IRQHandler - B INTI2C1AL_IRQHandler - - PUBWEAK INTI2C1BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1BF_IRQHandler - B INTI2C1BF_IRQHandler - - PUBWEAK INTI2C1NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C1NACK_IRQHandler - B INTI2C1NACK_IRQHandler - - PUBWEAK INTI2C2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2_IRQHandler - B INTI2C2_IRQHandler - - PUBWEAK INTI2C2AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2AL_IRQHandler - B INTI2C2AL_IRQHandler - - PUBWEAK INTI2C2BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2BF_IRQHandler - B INTI2C2BF_IRQHandler - - PUBWEAK INTI2C2NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C2NACK_IRQHandler - B INTI2C2NACK_IRQHandler - - PUBWEAK INTI2C3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3_IRQHandler - B INTI2C3_IRQHandler - - PUBWEAK INTI2C3AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3AL_IRQHandler - B INTI2C3AL_IRQHandler - - PUBWEAK INTI2C3BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3BF_IRQHandler - B INTI2C3BF_IRQHandler - - PUBWEAK INTI2C3NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C3NACK_IRQHandler - B INTI2C3NACK_IRQHandler - - PUBWEAK INTI2C4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C4_IRQHandler - B INTI2C4_IRQHandler - - PUBWEAK INTI2C4AL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C4AL_IRQHandler - B INTI2C4AL_IRQHandler - - PUBWEAK INTI2C4BF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C4BF_IRQHandler - B INTI2C4BF_IRQHandler - - PUBWEAK INTI2C4NACK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTI2C4NACK_IRQHandler - B INTI2C4NACK_IRQHandler - - PUBWEAK INTADACP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP0_IRQHandler - B INTADACP0_IRQHandler - - PUBWEAK INTADACP1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACP1_IRQHandler - B INTADACP1_IRQHandler - - PUBWEAK INTADATRG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADATRG_IRQHandler - B INTADATRG_IRQHandler - - PUBWEAK INTADASGL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADASGL_IRQHandler - B INTADASGL_IRQHandler - - PUBWEAK INTADACNT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADACNT_IRQHandler - B INTADACNT_IRQHandler - - PUBWEAK INTADAHP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTADAHP_IRQHandler - B INTADAHP_IRQHandler - - PUBWEAK INTFLDRDY_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLDRDY_IRQHandler - B INTFLDRDY_IRQHandler - - PUBWEAK INTFLCRDY0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLCRDY0_IRQHandler - B INTFLCRDY0_IRQHandler - - PUBWEAK INTFLCRDY1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTFLCRDY1_IRQHandler - B INTFLCRDY1_IRQHandler - - PUBWEAK INTMDMAABERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTMDMAABERR_IRQHandler - B INTMDMAABERR_IRQHandler - - PUBWEAK INTMDMAADERR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -INTMDMAADERR_IRQHandler - B INTMDMAADERR_IRQHandler - - END diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/tmpm4g9f15.icf b/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/tmpm4g9f15.icf deleted file mode 100644 index e79c3b90b34..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/TOOLCHAIN_IAR/tmpm4g9f15.icf +++ /dev/null @@ -1,45 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x180000; } -define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000320; -define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; -define symbol __ICFEDIT_region_BRAM_start__ = 0x20030000; -define symbol __ICFEDIT_region_BRAM_end__ = 0x200307FF; -/*-Sizes-*/ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __ICFEDIT_size_cstack__ = 0x0400; -define symbol __ICFEDIT_size_heap__ = 0x6000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -initialize by copy { section RAMCODE }; - -/* Place both in a block */ -define block RamCode { section RAMCODE }; -define block RamCodeInit { section RAMCODE_init }; - -/* Place them in ROM and RAM */ -place in ROM_region { block RamCodeInit }; -place in RAM_region { block RamCode }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in ROM_region { readonly }; diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis.h b/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis.h deleted file mode 100644 index 6bcd9c1fb09..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis.h +++ /dev/null @@ -1,12 +0,0 @@ -/* mbed Microcontroller Library - CMSIS for TMPM4G9 - * Copyright (C) 2011 ARM Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * A generic CMSIS include header, pulling in TMPM4G9 specifics - */ -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "TMPM4G9.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis_nvic.h b/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis_nvic.h deleted file mode 100644 index 3b46a6c8810..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/cmsis_nvic.h +++ /dev/null @@ -1,28 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for TMPM4G9 - * Copyright (c) 2011 ARM Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - - -#if defined(__ICCARM__) - #pragma section=".intvec" - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) -#elif defined(__CC_ARM) - extern uint32_t Load$$LR$$LR_IROM1$$Base[]; - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) -#elif defined(__GNUC__) - extern uint32_t vectors[]; - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors) -#else - #error "Flash vector address not set for this toolchain" -#endif - - -#define NVIC_NUM_VECTORS (157) -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.c b/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.c deleted file mode 100644 index d2208ec40c1..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.c +++ /dev/null @@ -1,338 +0,0 @@ -/** - ******************************************************************************* - * @file system_TMPM4G9.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the - * TOSHIBA 'TMPM4Gx' Device Series - * @version 1.0.0.0 - * $Date:: 2018-04-02 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - ******************************************************************************* - */ - -#include "TMPM4G9.h" - -/*-------- <<< Start of configuration section >>> ----------------------------*/ - -/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ -#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ -#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ -#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ - -/* Clock Generator (CG) Configuration */ -#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ -#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ -#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ - -#define STBYCR_Val (0x00000000UL) - -#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */ -#define CG_10M_MUL_16_FPLL (0x002E5020UL<<8U) /* fPLL = 10MHz * 16 */ -#define CG_12M_MUL_13_3125_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.3125 */ -#define CG_16M_MUL_10_FPLL (0x0048D014UL<<8U) /* fPLL = 16MHz * 10 */ -#define CG_20M_MUL_8_FPLL (0x005AD010UL<<8U) /* fPLL = 20MHz * 8 */ - -#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL) -#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) -#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) -#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) - -#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) -#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) -#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) - -#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) -#define CG_OSCCR_EOSCEN_SET (0x00000002UL) -#define CG_OSCCR_OSCSEL_SET (0x00000100UL) - -#define CG_WUPHCR_WUON_START_SET (0x00000001UL) - -#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ -#if (CLOCK_SETUP) - #define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ - #define PLL0SEL_Ready CG_12M_MUL_13_3125_FPLL -#else - #define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */ - #define PLL0SEL_Ready CG_12M_MUL_13_3125_FPLL -#endif -#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) -#define PLL0SEL_MASK (0xFFFFFF00UL) - -/*-------- <<< End of configuration section >>> ------------------------------*/ - -/*-------- DEFINES -----------------------------------------------------------*/ -/* Define clocks */ -#define EOSC_8M (8000000UL) -#define EOSC_10M (10000000UL) -#define EOSC_12M (12000000UL) -#define EOSC_16M (16000000UL) -#define EOSC_20M (20000000UL) -#define IOSC_10M (10000000UL) -#define EXTALH EOSC_12M /* External high-speed oscillator freq */ -#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ -#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */ -#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ -#define EOSC_12M_DIV2_PLLON (159750000UL) /* 12.00MHz * 26.6250 / 2 */ -#define EOSC_16M_DIV2_PLLON (160000000UL) /* 16.00MHz * 20.0000 / 2 */ -#define EOSC_20M_DIV2_PLLON (160000000UL) /* 20.00MHz * 16.0000 / 2 */ -#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ - -/* Configure Warm-up time */ -#define HZ_1M (1000000UL) -#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ -#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ -#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ -#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = (warm-up time(us) * IXTALH - 16) / 16 */ -#if (CLOCK_SETUP) - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#else - #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) - #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) -#endif - -/* Determine core clock frequency according to settings */ -/* System clock is high-speed clock*/ -#if (CLOCK_SETUP) - #define CORE_TALH (EXTALH) -#else - #define CORE_TALH (IXTALH) -#endif - -#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ - #if (CORE_TALH == EOSC_8M) /* If input is 8MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_20_FPLL)) - #define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 8MHz */ - #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) - #define __CORE_CLK EOSC_10M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_13_3125_FPLL) - #define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 159.75MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 12MHz */ - #elif (CORE_TALH == EOSC_16M) /* If input is 16MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_16M_MUL_10_FPLL) - #define __CORE_CLK EOSC_16M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 16MHz */ - #elif (CORE_TALH == EOSC_20M) /* If input is 20MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_20M_MUL_8_FPLL) - #define __CORE_CLK EOSC_20M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 20MHz */ - #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ - #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) - #define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 160MHz */ - #else /* fc -> reserved */ - #define __CORE_CLK (0U) - #endif /* End input is 10MHz */ - #else /* input clock not known */ - #define __CORE_CLK (0U) - #error "Core Oscillator Frequency invalid!" - #endif /* End switch input clock */ -#else - #define __CORE_CLK (CORE_TALH) -#endif - -#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */ - #define __CORE_SYS (__CORE_CLK) -#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */ - #define __CORE_SYS (__CORE_CLK / 2U) -#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */ - #define __CORE_SYS (__CORE_CLK / 4U ) -#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */ - #define __CORE_SYS (__CORE_CLK / 8U) -#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */ - #define __CORE_SYS (__CORE_CLK / 16U) -#else /* Gear -> reserved */ - #define __CORE_SYS (0U) -#endif - - -/* Clock Variable definitions */ -uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ -uint32_t CoreClockInput = 0U; - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Update SystemCoreClock according register values. - */ -void SystemCoreClockUpdate(void) -{ /* Get Core Clock Frequency */ - uint32_t CoreClock = 0U; - uint32_t regval = 0U; - - uint32_t oscsel = 0U; - uint32_t pll0sel = 0U; - uint32_t pll0on = 0U; - - CoreClockInput = 0U; - /* Determine clock frequency according to clock register values */ - /* System clock is high-speed clock */ - regval = TSB_CG->OSCCR; - oscsel = regval & CG_OSCCR_OSCSEL_SET; - if (oscsel) { /* If system clock is External high-speed oscillator freq */ - CoreClock = EXTALH; - } else { /* If system clock is Internal high-speed oscillator freq */ - CoreClock = IXTALH; - } - regval = TSB_CG->PLL0SEL; - pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; - pll0on = regval & CG_PLL0SEL_PLL0ON_SET; - if (pll0sel && pll0on) { /* If PLL enabled */ - if (CoreClock == EOSC_8M) { /* If input is 8MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_20_FPLL) { - CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) { - CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_13_3125_FPLL) { - CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 159.75MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_16M) { /* If input is 16MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_16M_MUL_10_FPLL) { - CoreClockInput = EOSC_16M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == EOSC_20M) { /* If input is 20MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_20M_MUL_8_FPLL) { - CoreClockInput = EOSC_20M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ - if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) { - CoreClockInput = IOSC_10M_DIV2_PLLON; /* output clock is 160MHz */ - } else { - CoreClockInput = 0U; /* fc -> reserved */ - } - } else { - CoreClockInput = 0U; - } - } else { /* If PLL not used */ - CoreClockInput = CoreClock; - } - - switch (TSB_CG->SYSCR & 7U) { - case 0U: /* Gear -> fc */ - SystemCoreClock = CoreClockInput; - break; - case 1U: /* Gear -> fc/2 */ - SystemCoreClock = CoreClockInput / 2U; - break; - case 2U: /* Gear -> fc/4 */ - SystemCoreClock = CoreClockInput / 4U; - break; - case 3U: /* Gear -> fc/8 */ - SystemCoreClock = CoreClockInput / 8U; - break; - case 4U: /* Gear -> fc/16 */ - SystemCoreClock = CoreClockInput / 16U; - break; - case 5U: - case 6U: - case 7U: - SystemCoreClock = 0U; - break; - default: - SystemCoreClock = 0U; - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ -#if (SIWD_SETUP) /* Watchdog Setup */ - /* SIWD Disable */ - TSB_SIWD0->EN = SIWDEN_Val; - TSB_SIWD0->CR = SIWDCR_Val; -#else - /* SIWD Enable (Setting after a Reset) */ -#endif - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */ - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ -#endif - -#if (CLOCK_SETUP) /* Clock(external) Setup */ - TSB_CG->SYSCR = SYSCR_GEAR_Val; - - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET); - TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; - TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; - while (!TSB_CG_OSCCR_OSCF) { - ; - } /* Confirm CGOSCCR="1" */ - TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; -#else - /* Internal HOSC Enable (Setting after a Reset) */ -#endif - - TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set */ - while((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val)) - != ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))){ - ; - } - - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ - TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; - TSB_CG->PLL0SEL = PLL0SEL_Ready; - TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Warm-up */ - - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ - TSB_CG->STBYCR = STBYCR_Val; - TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); - //TSB_RLM->LOSCCR = 0x03; - while (TSB_CG_WUPHCR_WUEF) { - ; - } /* Lockup */ - TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; - while (!TSB_CG_PLL0SEL_PLL0ST) { - ; - } /*Confirm CGPLL0SEL = "1" */ -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.h b/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.h deleted file mode 100644 index 9ea28b81a03..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/device/system_TMPM4G9.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - ***************************************************************************** - * @file system_TMPM4G9.h - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the - * TOSHIBA 'TMPM4G9' Device Series - * @version V0.0.0.0 - * $Date:: 2018-04-02 #$ - * - * SPDX-License-Identifier: Apache-2.0 - * - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved - ***************************************************************************** - */ - -#include - -#ifndef __SYSTEM_TMPM4G9_H -#define __SYSTEM_TMPM4G9_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t CoreClockInput; /*!< High speed Clock Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/flash_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/flash_api.c deleted file mode 100644 index f3e30e424a4..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/flash_api.c +++ /dev/null @@ -1,130 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_api.h" -#include "mbed_critical.h" -#include "tmpm4g9_fc.h" - -#define PROGRAM_WIRTE_MAX (16U) // Page program could be written 16 bytes/4 words once -#define SECTOR_SIZE (0x8000) // 32KB each sectors or block -#define FLASH_CHIP_SIZE (0x00180000) // Flash chip size is 1536KByte -#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL) - -#define SUCCESS (0U) -#define FAIL (-1) -// IHOSC1EN -#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask -#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable -#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable - -static void internal_hosc_enable(void); - -int32_t flash_init(flash_t *obj) -{ - obj->flash_inited = 0; - obj->flash_inited = 1; - internal_hosc_enable(); // Internal HOSC enable - return 0; -} - -int32_t flash_free(flash_t *obj) -{ - obj->flash_inited = 0; - - return 0; -} - -int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - int status = FAIL; - - if (obj->flash_inited == 0) { - flash_init(obj); - } - - // We need to prevent flash accesses during erase operation - core_util_critical_section_enter(); - - if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t*)address)) { - status = SUCCESS; - } else { - // Do nothing - } - - core_util_critical_section_exit(); - - return status; -} - -int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - int status = SUCCESS; - - address &= MASK_CHIP_ID_FROM_ADD; - - // We need to prevent flash accesses during program operation - core_util_critical_section_enter(); - - if (TXZ_SUCCESS == fc_write_code_flash((uint32_t*)data, (uint32_t*)address, size)) { - // Do nothing - } else { - status = FAIL; - } - - core_util_critical_section_exit(); - - return status; -} - -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ - if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) { - return SECTOR_SIZE; - } else { - // Do nothing - } - - return MBED_FLASH_INVALID_SIZE; -} - -uint32_t flash_get_page_size(const flash_t *obj) -{ - return PROGRAM_WIRTE_MAX; -} - -uint32_t flash_get_start_address(const flash_t *obj) -{ - return FC_CODE_FLASH_ADDRESS_TOP; -} - -uint32_t flash_get_size(const flash_t *obj) -{ - return FLASH_CHIP_SIZE; -} - -static void internal_hosc_enable(void) -{ - uint32_t work; - work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); - TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); -} - -uint8_t flash_get_erase_value(const flash_t *obj) -{ - (void)obj; - - return 0xFF; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/gpio_api.c deleted file mode 100644 index c30f3f1f450..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_api.c +++ /dev/null @@ -1,125 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "mbed_error.h" -#include "txz_gpio.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define GPIO_DATA PIN_DATA(0, 2) -#define ALT_FUNC_GPIO 0U - -_gpio_t gpio_port_add = { - .p_pa_instance = TSB_PA, - .p_pb_instance = TSB_PB, - .p_pc_instance = TSB_PC, - .p_pd_instance = TSB_PD, - .p_pe_instance = TSB_PE, - .p_pf_instance = TSB_PF, - .p_pg_instance = TSB_PG, - .p_ph_instance = TSB_PH, - .p_pj_instance = TSB_PJ, - .p_pk_instance = TSB_PK, - .p_pl_instance = TSB_PL, - .p_pm_instance = TSB_PM, - .p_pn_instance = TSB_PN, - .p_pp_instance = TSB_PP, - .p_pr_instance = TSB_PR, - .p_pt_instance = TSB_PT, - .p_pu_instance = TSB_PU, - .p_pv_instance = TSB_PV, - .p_pw_instance = TSB_PW, - .p_py_instance = TSB_PY -}; - -uint32_t gpio_set(PinName pin) -{ - // Check that pin is valid - MBED_ASSERT(pin != (PinName)NC); - - // Set pin function as GPIO pin - pin_function(pin, GPIO_DATA); - - // Return pin mask - return (1 << (pin & 0x07)); -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - // Store above pin mask, pin name into GPIO object - obj->pin = pin; - if (pin != NC) { - obj->pin_num = PIN_POS(pin); - obj->mask = gpio_set(pin); - obj->port = (PortName) PIN_PORT(pin); - //Enable clock for particular port - TSB_CG->FSYSMENB |= (1 << ((obj->port) + 2)); - } -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - // Set pin mode - pin_mode(obj->pin, mode); -} - -// Set gpio object pin direction -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - // Set direction - switch (direction) { - case PIN_INPUT: - // Set pin input - gpio_func(&gpio_port_add, - (gpio_gr_t)obj->port, - (gpio_num_t)obj->pin_num, - (uint32_t)ALT_FUNC_GPIO, - GPIO_PIN_INPUT); - break; - case PIN_OUTPUT: - // Set pin output - gpio_func(&gpio_port_add, - (gpio_gr_t)obj->port, - (gpio_num_t)obj->pin_num, - (uint32_t)ALT_FUNC_GPIO, - GPIO_PIN_OUTPUT); - break; - case PIN_INOUT: - // Set pin both input and output - gpio_func(&gpio_port_add, - (gpio_gr_t)obj->port, - (gpio_num_t)obj->pin_num, - (uint32_t)ALT_FUNC_GPIO, - GPIO_PIN_INOUT); - break; - default: - break; - } -} - -void gpio_write(gpio_t *obj, int value) -{ - // Write gpio object pin data - gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value); -} - -int gpio_read(gpio_t *obj) -{ - // Read gpio object pin data - gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable - gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val); - return val; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_irq_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/gpio_irq_api.c deleted file mode 100644 index a487732e502..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_irq_api.c +++ /dev/null @@ -1,281 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_irq_api.h" -#include "mbed_critical.h" -#include "mbed_error.h" -#include "txz_gpio.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define CHANNEL_NUM (16) -#define DISABLE (0) -#define ENABLE (1) -#define CLR_INT_FLAG (0xC0) - -const PinMap PinMap_GPIO_IRQ[] = { - {PK7, GPIO_IRQ_0, PIN_DATA(0, 0)}, - {PL0, GPIO_IRQ_1, PIN_DATA(0, 0)}, - {PA0, GPIO_IRQ_2, PIN_DATA(0, 0)}, - {PA7, GPIO_IRQ_3, PIN_DATA(0, 0)}, - {PB0, GPIO_IRQ_4, PIN_DATA(0, 0)}, - {PB1, GPIO_IRQ_5, PIN_DATA(0, 0)}, - {PB6, GPIO_IRQ_6, PIN_DATA(0, 0)}, - {PB7, GPIO_IRQ_7, PIN_DATA(0, 0)}, - {PG0, GPIO_IRQ_8, PIN_DATA(0, 0)}, - {PG1, GPIO_IRQ_9, PIN_DATA(0, 0)}, - {PK0, GPIO_IRQ_A, PIN_DATA(0, 0)}, - {PK1, GPIO_IRQ_B, PIN_DATA(0, 0)}, - {PC0, GPIO_IRQ_C, PIN_DATA(0, 0)}, - {PC1, GPIO_IRQ_D, PIN_DATA(0, 0)}, - {PC6, GPIO_IRQ_E, PIN_DATA(0, 0)}, - {PC7, GPIO_IRQ_F, PIN_DATA(0, 0)}, - {NC, NC, 0} -}; - -extern _gpio_t gpio_port_add; - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; -static CG_INTActiveState CurrentState; - -static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t); -static void INT_IRQHandler(PinName, uint32_t); - -void INT00_IRQHandler(void) -{ - INT_IRQHandler(PK7, 0); -} - -void INT01_IRQHandler(void) -{ - INT_IRQHandler(PL0, 1); -} - -void INT02_IRQHandler(void) -{ - INT_IRQHandler(PA0, 2); -} - -void INT03_IRQHandler(void) -{ - INT_IRQHandler(PA7, 3); -} - -void INT04_IRQHandler(void) -{ - INT_IRQHandler(PB0, 4); -} - -void INT05_IRQHandler(void) -{ - INT_IRQHandler(PB1, 5); -} - -void INT06_IRQHandler(void) -{ - INT_IRQHandler(PB6, 6); -} - -void INT07_IRQHandler(void) -{ - INT_IRQHandler(PB7, 7); -} - -void INT08_IRQHandler(void) -{ - INT_IRQHandler(PG0, 8); -} - -void INT09_IRQHandler(void) -{ - INT_IRQHandler(PG1, 9); -} - -void INT10_IRQHandler(void) -{ - INT_IRQHandler(PK0, 10); -} - -void INT11_IRQHandler(void) -{ - INT_IRQHandler(PK1, 11); -} - -void INT12_IRQHandler(void) -{ - INT_IRQHandler(PC0, 12); -} -void INT13_IRQHandler(void) -{ - INT_IRQHandler(PC1, 13); -} -void INT14_IRQHandler(void) -{ - INT_IRQHandler(PC6, 14); -} -void INT15_IRQHandler(void) -{ - INT_IRQHandler(PC7, 15); -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - // Get gpio interrupt ID - obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); - core_util_critical_section_enter(); - // Get GPIO port and pin num - obj->port = (PortName)PIN_PORT(pin); - obj->pin_num = PIN_POS(pin); - // Set pin level as LOW - gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0); - // Enable gpio interrupt function - pinmap_pinout(pin, PinMap_GPIO_IRQ); - // Get GPIO irq source - obj->irq_src = (CG_INTSrc)obj->irq_id; - // Save irq handler - hal_irq_handler[obj->irq_src] = handler; - // Save irq id - channel_ids[obj->irq_src] = id; - // Initialize interrupt event as both edges detection - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Set interrupt event and enable INTx clear - CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); - core_util_critical_section_exit();; - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - // Clear gpio_irq - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Reset interrupt handler - hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - //Disable GPIO interrupt on obj - gpio_irq_disable(obj); - if (enable) { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || - (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_RISING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || - (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_FALLING; - } - } else { - error("Not supported event\n"); - } - } else { - // Get gpio interrupt event - if (event == IRQ_RISE) { - if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || - (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_FALLING; - } - } else if (event == IRQ_FALL) { - if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || - (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { - obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; - } else { - obj->event = CG_INT_ACTIVE_STATE_RISING; - } - } else { - error("Not supported event\n"); - } - } - CurrentState = obj->event; - if (obj->event != CG_INT_ACTIVE_STATE_INVALID ) { - // Set interrupt event and enable INTx clear - CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); - gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0); - } else { - gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1); - } - // Clear interrupt request - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - // Enable GPIO interrupt on obj - gpio_irq_enable(obj); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - // Clear and Enable gpio_irq object - NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - NVIC_EnableIRQ((IRQn_Type)obj->irq_id); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - // Disable gpio_irq object - NVIC_DisableIRQ((IRQn_Type)obj->irq_id); -} - -static void INT_IRQHandler(PinName pin, uint32_t index) -{ - PortName port; - gpio_pinstate_t data = GPIO_PIN_RESET; - uint8_t pin_num; - - pin_num = PIN_POS(pin); - port = (PortName)PIN_PORT(pin); - // Clear interrupt request - CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE); - // Get pin value - gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data); - switch (data) { - // Falling edge detection - case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); - break; - // Rising edge detection - case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); - break; - default: - break; - } - // Clear gpio pending interrupt - NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index)); - // Enable interrupt request - CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE); -} - -static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState) -{ - uint8_t *ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2)); - //clear pending falling and rising edge bit - *ptr = CLR_INT_FLAG; - *ptr = (ActiveState | NewState); - { - uint8_t regval = *ptr; - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_object.h b/targets/TARGET_TT/TARGET_TT_M4G9/gpio_object.h deleted file mode 100644 index c579368d239..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/gpio_object.h +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "txz_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - PortName port; - uint32_t pin_num; - uint32_t mask; -} gpio_t; - -typedef enum { - CG_INT_SRC_0 = 0U, - CG_INT_SRC_1, - CG_INT_SRC_2, - CG_INT_SRC_3, - CG_INT_SRC_4, - CG_INT_SRC_5, - CG_INT_SRC_6, - CG_INT_SRC_7, - CG_INT_SRC_8, - CG_INT_SRC_9, - CG_INT_SRC_A, - CG_INT_SRC_B, - CG_INT_SRC_C, - CG_INT_SRC_D, - CG_INT_SRC_E, - CG_INT_SRC_F -} CG_INTSrc; - -typedef enum { - CG_INT_ACTIVE_STATE_L = 0x00U, - CG_INT_ACTIVE_STATE_H = 0x02U, - CG_INT_ACTIVE_STATE_FALLING = 0x04U, - CG_INT_ACTIVE_STATE_RISING = 0x06U, - CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, - CG_INT_ACTIVE_STATE_INVALID = 0x0AU -} CG_INTActiveState; - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return (obj->pin != (PinName)NC); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/i2c_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/i2c_api.c deleted file mode 100644 index 57551473c97..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/i2c_api.c +++ /dev/null @@ -1,216 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" - -#if DEVICE_I2C - -#include -#include -#include -#include "mbed_error.h" -#include "txz_i2c_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define MAX_I2C_FREQ 1000000 - -static const PinMap PinMap_I2C_SDA[] = { - {PG2, I2C_0, PIN_DATA(7, 2)}, - {PF2, I2C_1, PIN_DATA(7, 2)}, - {PG4, I2C_2, PIN_DATA(7, 2)}, - {PJ6, I2C_3, PIN_DATA(7, 2)}, - {PJ3, I2C_4, PIN_DATA(7, 2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PG3, I2C_0, PIN_DATA(7, 2)}, - {PF3, I2C_1, PIN_DATA(7, 2)}, - {PG5, I2C_2, PIN_DATA(7, 2)}, - {PJ7, I2C_3, PIN_DATA(7, 2)}, - {PJ2, I2C_4, PIN_DATA(7, 2)}, - {NC, NC, 0} -}; - -// Initialize the I2C peripheral. It sets the default parameters for I2C -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - MBED_ASSERT(obj != NULL); - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)i2c_name != NC); - - switch(i2c_name) { - case I2C_0: - // Enable clock for I2C_0 - TSB_CG_FSYSMENA_IPMENA29 = TXZ_ENABLE; - //Enable clok for GPIO G - TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C0; - obj->my_i2c.info.irqn = INTI2C0_IRQn; - break; - case I2C_1: - // Enable clock for I2C_1 - TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; - //Enable clok for GPIO F - TSB_CG_FSYSMENB_IPMENB07 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C1; - obj->my_i2c.info.irqn = INTI2C1_IRQn; - break; - case I2C_2: - // Enable clock for I2C_2 - TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; - //Enable clok for GPIO G - TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C2; - obj->my_i2c.info.irqn = INTI2C2_IRQn; - break; - case I2C_3: - // Enable clock for I2C_3 - TSB_CG_FSYSMENB_IPMENB00 = TXZ_ENABLE; - //Enable clok for GPIO J - TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C3; - obj->my_i2c.info.irqn = INTI2C3_IRQn; - break; - case I2C_4: - // Enable clock for I2C_4 - TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; - //Enable clok for GPIO J - TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; - obj->my_i2c.i2c.p_instance = TSB_I2C4; - obj->my_i2c.info.irqn = INTI2C4_IRQn; - break; - default: - error("I2C is not available"); - break; - } - - pinmap_pinout(sda, PinMap_I2C_SDA); - pin_mode(sda, OpenDrain); - pin_mode(sda, PullUp); - - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); - pin_mode(scl, PullUp); - - i2c_reset(obj); - i2c_frequency(obj, 100000); - I2C_init(&obj->my_i2c.i2c); -} - -// Configure the I2C frequency -void i2c_frequency(i2c_t *obj, int hz) -{ - if (hz <= MAX_I2C_FREQ) { - i2c_frequency_t(&obj->my_i2c, hz); - } else { - error("Failed : Max I2C frequency is 1000000"); - } -} - -int i2c_start(i2c_t *obj) -{ - i2c_start_t(&obj->my_i2c); - return TXZ_SUCCESS; -} - -int i2c_stop(i2c_t *obj) -{ - i2c_stop_t(&obj->my_i2c); - return TXZ_SUCCESS; -} - -void i2c_reset(i2c_t *obj) -{ - // Software reset - i2c_reset_t(&obj->my_i2c); -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int32_t count = i2c_read_t(&obj->my_i2c, address, (uint8_t *)data, length, stop); - return count; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int32_t count = i2c_write_t(&obj->my_i2c, address, (uint8_t *)data, length, stop); - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - int32_t data = i2c_byte_read_t(&obj->my_i2c, last); - return data; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - int32_t result = i2c_byte_write_t(&obj->my_i2c, data); - return result; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - i2c_slave_mode_t(&obj->my_i2c, enable_slave); -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - i2c_slave_address_t(&obj->my_i2c, address); -} - -int i2c_slave_receive(i2c_t *obj) -{ - int32_t result = i2c_slave_receive_t(&obj->my_i2c); - return result; -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - int32_t count = i2c_slave_read_t(&obj->my_i2c, (uint8_t *)data, length); - return count; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - int32_t count = i2c_slave_write_t(&obj->my_i2c, (uint8_t *)data, length); - return count; -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/objects.h b/targets/TARGET_TT/TARGET_TT_M4G9/objects.h deleted file mode 100644 index d4f385074c7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/objects.h +++ /dev/null @@ -1,105 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "PortNames.h" -#include "PeripheralNames.h" -#include "gpio_object.h" -#include "txz_gpio.h" -#include "txz_uart.h" -#include "txz_fuart.h" -#include "txz_tspi.h" -#include "txz_t32a.h" -#include "txz_cg.h" -#include "txz_driver_def.h" -#include "adc.h" -#include "txz_i2c_api.h" -#include "txz_i2c.h" -#include "txz_fuart_include.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct port_s { - PortName port; - uint32_t mask; -}; - -struct dac_s { - DACName dac; - TSB_DA_TypeDef *DACx; -}; - -struct serial_s { - uint32_t index; - uint32_t mode; - TSB_UART_TypeDef *UARTx; - TSB_FURT_TypeDef *FUARTx; - uart_boudrate_t boud_obj; - fuart_boudrate_t fboud_obj; -}; - -struct pwmout_s { - PinName pin; - uint32_t trailing_timing; - uint32_t leading_timing; - uint32_t divisor; - float period; - t32a_t p_t32a; - uint32_t type; -}; - -struct spi_s { - tspi_t p_obj; - SPIName module; - uint8_t bits; -}; - -struct gpio_irq_s { - PortName port; - uint8_t pin_num; - uint32_t irq_id; - CG_INTActiveState event; - CG_INTSrc irq_src; -}; - -struct flash_s { - int flash_inited; -}; - -struct analogin_s { - PinName pin; - adc_t p_adc; - adc_channel_setting_t param; - ADCName adc; -}; - -struct i2c_s { - uint32_t index; - int address; - _i2c_t my_i2c; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/pinmap.c b/targets/TARGET_TT/TARGET_TT_M4G9/pinmap.c deleted file mode 100644 index 0f612fb224b..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/pinmap.c +++ /dev/null @@ -1,98 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "mbed_error.h" -#include "pinmap.h" -#include "txz_gpio.h" - -#define PIN_FUNC_MAX 8 - -extern _gpio_t gpio_port_add; - -void pin_function(PinName pin, int function) -{ - uint32_t port = 0; - uint8_t bit = 0; - uint8_t func = 0; - uint8_t dir = 0; - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Calculate pin function and pin direction - func = PIN_FUNC(function); - dir = PIN_DIR(function); - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - // find function is in range or not - if (func <= PIN_FUNC_MAX) { - // Set pin function and direction if direction is in range - switch (dir) { - case PIN_INPUT: - // Set pin input - gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT); - break; - case PIN_OUTPUT: - // Set pin output - gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT); - break; - case PIN_INOUT: - // Set pin both input and output - gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT); - break; - default: - break; - } - } else { - // do nothing - } -} - -void pin_mode(PinName pin, PinMode mode) -{ - uint32_t port = 0; - uint8_t bit = 0; - - // Assert that pin is valid - MBED_ASSERT(pin != NC); - - // Check if function is in range - if (mode > OpenDrain) { - return; - } - // Calculate port and pin position - port = PIN_PORT(pin); - bit = PIN_POS(pin); - // Set pin mode - switch (mode) { - case PullNone: - gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); - gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); - gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); - break; - case PullUp: - gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); - break; - case PullDown: - gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); - break; - case OpenDrain: - gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); - break; - default: - break; - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/port_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/port_api.c deleted file mode 100644 index d1f687baca7..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/port_api.c +++ /dev/null @@ -1,140 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "mbed_assert.h" -#include "mbed_error.h" -#include "txz_gpio.h" -#include "pinmap.h" - -#define PORT_PIN_NUM (8) -#define ALT_FUNC_GPIO (0U) - -extern _gpio_t gpio_port_add; -static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num); - -PinName port_pin(PortName port, int pin_n) -{ - PinName pin = NC; - pin = (PinName)((port << 3) | pin_n); - return pin; -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(port <= PortY); - - // Store port and port mask for future use - obj->port = port; - obj->mask = mask; - //Enable the clock for particular port - _gpio_init(&gpio_port_add, obj->port); - // Set port function and port direction - for (i = 0; i < PORT_PIN_NUM; i++) { - // If the pin is used - if (obj->mask & (1 << i)) { - pin_function(port_pin(obj->port, i), dir); - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint8_t i = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortY); - - // Set mode for masked pins - for (i = 0; i < PORT_PIN_NUM; i++) { - // If the pin is used - if (obj->mask & (1 << i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint8_t i = 0; - // Assert that port is valid - MBED_ASSERT(obj->port <= PortY); - - for (i = 0; i < PORT_PIN_NUM; i++) { - // Set direction for masked pins - if (obj->mask & (1 << i)) { - gpio_pin_dir(obj, dir, i); - } - } -} - -void port_write(port_t *obj, int value) -{ - uint32_t port_data = 0; - uint32_t data = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortY); - - // Get current data of port - gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); - - // Calculate data to write to masked pins - data = (port_data & ~obj->mask) | (value & obj->mask); - - // Write data to masked pins of the port - gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data); -} - -int port_read(port_t *obj) -{ - uint32_t port_data = 0; - uint32_t data = 0; - - // Assert that port is valid - MBED_ASSERT(obj->port <= PortY); - - // Get current data of port - gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); - - // Calculate data of masked pins - data = port_data & obj->mask; - - return data; -} - -static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num) -{ - switch (dir) { - case PIN_INPUT: - // Set pin input - gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT); - break; - case PIN_OUTPUT: - // Set pin output - gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT); - break; - case PIN_INOUT: - // Set pin both input and output - gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT); - break; - default: - //error("Invalid direction\n"); - break; - } -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/pwmout_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/pwmout_api.c deleted file mode 100644 index 66224c7d7aa..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/pwmout_api.c +++ /dev/null @@ -1,225 +0,0 @@ -/* mbed Microcontroller Library -* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved -* SPDX-License-Identifier: Apache-2.0 -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ -#include "pwmout_api.h" -#include "PeripheralNames.h" -#include "pinmap.h" - -#define GPIO_CLK_OFFSET 2 -// Because Timer operating frequency is 2.5 MhZ -#define CALCULATE_RGC1_VAL 2.5 - -static const PinMap PinMap_PWM[] = { - {PA5, PWM_0, PIN_DATA(5, 1)}, - {PB2, PWM_1, PIN_DATA(5, 1)}, - {PB4, PWM_2, PIN_DATA(5, 1)}, - {PD2, PWM_3, PIN_DATA(5, 1)}, - {PD4, PWM_4, PIN_DATA(5, 1)}, - {PE1, PWM_5, PIN_DATA(5, 1)}, - {PE6, PWM_6, PIN_DATA(5, 1)}, - {PC2, PWM_7, PIN_DATA(5, 1)}, - {PL6, PWM_8, PIN_DATA(3, 1)}, - {PC4, PWM_9, PIN_DATA(5, 1)}, - {PM2, PWM_10, PIN_DATA(3, 1)}, - {PU0, PWM_11, PIN_DATA(3, 1)}, - {PU6, PWM_12, PIN_DATA(3, 1)}, - {NC, NC, 0} -}; - -void pwmout_init(pwmout_t *obj, PinName pin) -{ - // Determine the pwm channel - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - //Assert input is valid - MBED_ASSERT(pwm != (PWMName)NC); - switch (pwm) { - case PWM_0: - obj->p_t32a.p_instance = TSB_T32A1; - // Clock enable of T32A ch01 - TSB_CG_FSYSMENA_IPMENA07 = TXZ_ENABLE; - break; - case PWM_1: - obj->p_t32a.p_instance = TSB_T32A2; - // Clock enable of T32A ch02 - TSB_CG_FSYSMENA_IPMENA08 = TXZ_ENABLE; - break; - case PWM_2: - obj->p_t32a.p_instance = TSB_T32A3; - // Clock enable of T32A ch03 - TSB_CG_FSYSMENA_IPMENA09 = TXZ_ENABLE; - break; - case PWM_3: - obj->p_t32a.p_instance = TSB_T32A4; - // Clock enable of T32A ch04 - TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE; - break; - case PWM_4: - obj->p_t32a.p_instance = TSB_T32A5; - // Clock enable of T32A ch05 - TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE; - break; - case PWM_5: - obj->p_t32a.p_instance = TSB_T32A6; - // Clock enable of T32A ch06 - TSB_CG_FSYSMENA_IPMENA12 = TXZ_ENABLE; - break; - case PWM_6: - obj->p_t32a.p_instance = TSB_T32A7; - // Clock enable of T32A ch07 - TSB_CG_FSYSMENA_IPMENA13 = TXZ_ENABLE; - break; - case PWM_7: - obj->p_t32a.p_instance = TSB_T32A8; - // Clock enable of T32A ch08 - TSB_CG_FSYSMENA_IPMENA14 = TXZ_ENABLE; - break; - case PWM_8: - obj->p_t32a.p_instance = TSB_T32A9; - // Clock enable of T32A ch09 - TSB_CG_FSYSMENA_IPMENA15 = TXZ_ENABLE; - break; - case PWM_9: - obj->p_t32a.p_instance = TSB_T32A10; - // Clock enable of T32A ch10 - TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE; - break; - case PWM_10: - obj->p_t32a.p_instance = TSB_T32A11; - // Clock enable of T32A ch11 - TSB_CG_FSYSMENA_IPMENA17 = TXZ_ENABLE; - break; - case PWM_11: - obj->p_t32a.p_instance = TSB_T32A12; - // Clock enable of T32A ch12 - TSB_CG_FSYSMENA_IPMENA18 = TXZ_ENABLE; - break; - case PWM_12: - obj->p_t32a.p_instance = TSB_T32A13; - // Clock enable of T32A ch13 - TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE; - break; - default: - obj->p_t32a.p_instance = NULL; - break; - } - if(obj->p_t32a.p_instance == NULL) - return; - - // Enable clock for GPIO port. - TSB_CG->FSYSMENB |= (TXZ_ENABLE << ((PIN_PORT(pin)) + GPIO_CLK_OFFSET)); - - // Set pin function as PWM - pinmap_pinout(pin, PinMap_PWM); - - // Default to 20ms, 0% duty cycle - pwmout_period_ms(obj, 20); -} - -void pwmout_free(pwmout_t *obj) -{ - // Stop PWM - obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - obj->trailing_timing = TXZ_DISABLE; - obj->leading_timing = TXZ_DISABLE; - obj->p_t32a.p_instance = NULL; -} - -void pwmout_write(pwmout_t *obj, float value) -{ - // Stop PWM - obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - - if (value <= 0.0f) { - value = TXZ_DISABLE; - } else if (value >= 1.0f) { - value = TXZ_ENABLE; - } - - // Store the new leading_timing value - obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value); - - // Setting T32A_RGA0 register - obj->p_t32a.p_instance->RGC0 = obj->leading_timing; - - // Start PWM - obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -float pwmout_read(pwmout_t *obj) -{ - float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing; - return duty_cycle; -} - -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, (int)(seconds * 1000000.0f)); -} - -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, (ms * 1000)); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t *obj, int us) -{ - uint32_t prscl = 0; - float duty_cycle = 0; - float seconds = (float)((us) / 1000000.0f); - - obj->period = seconds; - // Restore the duty-cycle - duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); - prscl = T32A_PRSCLx_32; - obj->trailing_timing = (us * CALCULATE_RGC1_VAL); - obj->leading_timing = ((obj->trailing_timing)- (obj->trailing_timing * duty_cycle)); - - obj->p_t32a.p_instance->MOD = T32A_MODE_32; - obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); - obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx); - obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ | - T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ); - obj->p_t32a.p_instance->RGC0 = obj->leading_timing; - obj->p_t32a.p_instance->RGC1 = obj->trailing_timing; - obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE; - obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET); - obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, (seconds * 1000000.0f)); -} - -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, (ms * 1000)); -} - -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - float seconds = 0; - float value = 0; - - seconds = (float)(us / 1000000.0f); - value = (((seconds / obj->period) * 100.0f) / 100.0f); - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/serial_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/serial_api.c deleted file mode 100644 index 099a7cf7926..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/serial_api.c +++ /dev/null @@ -1,420 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "mbed_error.h" -#include "serial_api.h" -#include "pinmap.h" - -#define UART_NUM 8 -#define UART_ENABLE_RX ((uint32_t)0x00000001) -#define UART_ENABLE_TX ((uint32_t)0x00000002) -#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) -#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) -#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) -#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) -#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) -#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) -#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) -#define FUART_ENABLE_RX ((uint32_t)0x00000200) -#define FUART_ENABLE_TX ((uint32_t)0x00000100) -#define BAUDRATE_DEFAULT (9600) -#define CLR_REGISTER (0x00) - -static const PinMap PinMap_UART_TX[] = { - {PE3, SERIAL_0, PIN_DATA(7, 1)}, - {PH1, SERIAL_1, PIN_DATA(3, 1)}, - {PG1, SERIAL_2, PIN_DATA(3, 1)}, - {PU7, SERIAL_3, PIN_DATA(7, 1)}, - {PU0, SERIAL_4, PIN_DATA(7, 1)}, - {PJ1, SERIAL_5, PIN_DATA(3, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PE2, SERIAL_0, PIN_DATA(7, 0)}, - {PH0, SERIAL_1, PIN_DATA(3, 0)}, - {PG0, SERIAL_2, PIN_DATA(3, 0)}, - {PU6, SERIAL_3, PIN_DATA(7, 0)}, - {PU1, SERIAL_4, PIN_DATA(7, 0)}, - {PJ0, SERIAL_5, PIN_DATA(3, 0)}, - {NC, NC, 0} -}; - -static int serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void uart_swreset(TSB_UART_TypeDef *UARTx); -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - obj->mode = 0; - cg_t paramCG; - paramCG.p_instance = TSB_CG; - uart_clock_t prescal = {0}; - - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart_name != NC); - - obj->index = uart_name; - // Initialize UART instance - switch (uart_name) { - case SERIAL_0: - obj->UARTx = TSB_UART0; - //Enable clock for UART0 and Port E - TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB06 = TXZ_ENABLE; - break; - case SERIAL_1: - obj->UARTx = TSB_UART1; - //Enable clock for UART1 and Port H - TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB09 = TXZ_ENABLE; - break; - case SERIAL_2: - obj->UARTx = TSB_UART2; - //Enable clock for UART2 and Port G - TSB_CG_FSYSMENA_IPMENA25 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; - break; - case SERIAL_3: - obj->UARTx = TSB_UART3; - //Enable clock for UART3 and Port U - TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE; - break; - case SERIAL_4: - obj->UARTx = TSB_UART4; - //Enable clock for UART4 and Port U - TSB_CG_FSYSMENA_IPMENA27 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE; - break; - case SERIAL_5: - obj->UARTx = TSB_UART5; - //Enable clock for UART5 and Port J - TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; - break; - default: - break; - } - //Set alternate function - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC && rx != NC) { - obj->mode = UART_ENABLE_RX | UART_ENABLE_TX; - } else { - if (tx != NC) { - obj->mode = UART_ENABLE_TX; - } else { - if (rx != NC) { - obj->mode = UART_ENABLE_RX; - } - } - } - //software reset - uart_swreset(obj->UARTx); - //mbed default configurations - obj->UARTx->CR0 |= (1U); // data lengh 8 bit No parity one stop bit - prescal.prsel = UART_PLESCALER_1; - uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj); - obj->UARTx->BRD |=((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); - obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO - obj->UARTx->TRANS |= obj->mode; // Enable TX RX block. - obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); - is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - obj->UARTx->TRANS = CLR_REGISTER; - obj->UARTx->CR0 = CLR_REGISTER; - obj->UARTx->CR1 = CLR_REGISTER; - obj->UARTx = CLR_REGISTER; - uart_swreset(obj->UARTx); - obj->index = (uint32_t)NC; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - cg_t paramCG; - paramCG.p_instance = TSB_CG; - uart_clock_t prescal; - prescal.prsel = UART_PLESCALER_1; - uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, baudrate, &obj->boud_obj); - obj->UARTx->BRD = CLR_REGISTER; //clear BRD register - obj->UARTx->BRD |=((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - uint32_t parity_check = 0; - uint32_t data_length = 0; - uint32_t tmp = 0; - uint32_t sblen = 0; - - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits - parity_check = ((parity == ParityOdd) ? 1 :((parity == ParityEven) ? 3 : 0)); - data_length = (data_bits == 8 ? 1 :((data_bits == 7) ? 0 : 2)); - sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits - tmp = ((sblen << 4) |(parity_check << 2) | data_length); - obj->UARTx->CR0 = tmp; -} - -// INTERRUPT HANDLING -void INTUART0RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); -} - -void INTUART0TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); -} - -void INTUART1RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); -} - -void INTUART1TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); -} - -void INTUART2RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], RxIrq); -} - -void INTUART2TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_2], TxIrq); -} - -void INTUART3RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], RxIrq); -} - -void INTUART3TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_3], TxIrq); -} - -void INTUART4RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], RxIrq); -} - -void INTUART4TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_4], TxIrq); -} - -void INTUART5RX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], RxIrq); -} - -void INTUART5TX_IRQHandler(void) -{ - irq_handler(serial_irq_ids[SERIAL_5], TxIrq); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - switch (obj->index) { - case SERIAL_0: - if (irq == RxIrq) { - irq_n = INTUART0RX_IRQn; - } else { - irq_n = INTUART0TX_IRQn; - } - break; - case SERIAL_1: - if (irq == RxIrq) { - irq_n = INTUART1RX_IRQn; - } else { - irq_n = INTUART1TX_IRQn; - } - break; - case SERIAL_2: - if (irq == RxIrq) { - irq_n = INTUART2RX_IRQn; - } else { - irq_n = INTUART2TX_IRQn; - } - break; - case SERIAL_3: - if (irq == RxIrq) { - irq_n = INTUART3RX_IRQn; - } else { - irq_n = INTUART3TX_IRQn; - } - break; - case SERIAL_4: - if (irq == RxIrq) { - irq_n = INTUART4RX_IRQn; - } else { - irq_n = INTUART4TX_IRQn; - } - break; - case SERIAL_5: - if (irq == RxIrq) { - irq_n = INTUART5RX_IRQn; - } else { - irq_n = INTUART5TX_IRQn; - } - break; - default: - break; - } - - NVIC_ClearPendingIRQ(irq_n); - - if (enable) { - NVIC_EnableIRQ(irq_n); - } else { - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) -{ - int data = 0; - - while (!serial_readable(obj)) { // Wait until Rx buffer is full - // Do nothing - } - //Read Data Register - data = (obj->UARTx->DR & 0xFFU); - obj->UARTx->SR |= (1U << 6); // clear RXEND flag - - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)) { - // Do nothing - } - //Write Data Register - obj->UARTx->DR = (c & 0xFF); - while((obj->UARTx->SR & (1U << 14)) == 0) { - } - obj->UARTx->SR |= (1U << 14); // clear TXEND flag -} - -int serial_readable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x000F) != 0) { - ret = 1; - } - - return ret; -} - -int serial_writable(serial_t *obj) -{ - int ret = 0; - - if ((obj->UARTx->SR & 0x8000) == 0) { - ret = 1; - } - - return ret; -} - -// Pause transmission -void serial_break_set(serial_t *obj) -{ - obj->UARTx->TRANS |= 0x08; -} - -// Switch to normal transmission -void serial_break_clear(serial_t *obj) -{ - obj->UARTx->TRANS &= ~(0x08); -} - -static void uart_swreset(TSB_UART_TypeDef *UARTx) -{ - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } - - UARTx->SWRST = UARTxSWRST_SWRST_10; - UARTx->SWRST = UARTxSWRST_SWRST_01; - - while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { - // No process - } -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/sleep.c b/targets/TARGET_TT/TARGET_TT_M4G9/sleep.c deleted file mode 100644 index 565a00253f3..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/sleep.c +++ /dev/null @@ -1,125 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" - -// Number of warm-up cycle = (warming up time (s) / clock period (s)) - 16 -#define CG_WUODR_INT_5MS ((uint16_t)0x0C34) -#define CG_STBY_MODE_IDLE 0x0 -#define CG_STBY_MODE_STOP1 0x1 -#define EXTERNEL_OSC_MASK 0xFFFFFFF1 -#define SIWDT_DISABLE 0xB1 -#define WUPT_LOWER_MASK 0x000F -#define WUPT_UPPER_MASK 0xFFF0 - -static void external_losc_enable(void); - -void hal_sleep(void) -{ - // Set low power consumption mode IDLE - TSB_CG->STBYCR = CG_STBY_MODE_IDLE; - - // Enter idle mode - __DSB(); - __WFI(); -} - -void hal_deepsleep(void) -{ - uint32_t wupt_lower = 0U; - uint32_t wupt_upper = 0U; - uint32_t tmp = 0U; - - TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE; - - TSB_SIWD0->EN = TXZ_DISABLE; - TSB_SIWD0->CR = SIWDT_DISABLE; - - - while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) { - // Flash wait - } - - while (TSB_CG_WUPHCR_WUEF) { - // Wait for end of Warming-up for IHOSC1 - } - - TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE; - wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); - wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); - TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); - TSB_CG->STBYCR = CG_STBY_MODE_STOP1; - TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE; - - - while (TSB_CG_PLL0SEL_PLL0ST) { - // Wait for PLL status of fsys until off state(fosc=0) - } - - // Stop PLL of fsys - TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE; - TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE; - TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE; - - while (TSB_CG_OSCCR_OSCF) { - // Wait for fosc status until IHOSC1 = 0 - } - - tmp = TSB_CG->OSCCR; - tmp &= EXTERNEL_OSC_MASK; - TSB_CG->OSCCR = tmp; - - - // Enter stop1 mode - __DSB(); - __WFI(); - - // Switch over from IHOSC to EHOSC - // After coming out off sleep mode, Restore the clock setting to EHOSC. - external_losc_enable(); -} - -static void external_losc_enable(void) -{ - uint32_t wupt_lower = 0U; - uint32_t wupt_upper = 0U; - - // Enable high-speed oscillator - TSB_CG->OSCCR |= (TXZ_ENABLE << 1); - - // Select internal(fIHOSC) as warm-up clock - wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); - wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); - TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); - - // Start warm-up - TSB_CG->WUPHCR |= TXZ_ENABLE; - - // Wait until EHOSC become stable - while ((TSB_CG->WUPHCR & 0x0002)) { - // Do nothing - } - - // Set fosc source - TSB_CG->OSCCR |= (1 << 8); - - // Wait for to become "1" - while (!((TSB_CG->OSCCR & 0x200)>> 9)) { - // Do nothing... - } - - // Stop IHOSC - TSB_CG->OSCCR &= ~TXZ_ENABLE; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/spi_api.c b/targets/TARGET_TT/TARGET_TT_M4G9/spi_api.c deleted file mode 100644 index 49292988401..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/spi_api.c +++ /dev/null @@ -1,341 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "spi_api.h" -#include "mbed_error.h" -#include "txz_tspi.h" -#include "pinmap.h" - -#define TIMEOUT (1000) -#define BAUDRATE_1MHZ_BRS (0xA) -#define BAUDRATE_1MHZ_BRCK (0x30) - -static const PinMap PinMap_SPI_SCLK[] = { - {PA1, SPI_0, PIN_DATA(7, 1)}, - {PL1, SPI_1, PIN_DATA(7, 1)}, - {PA6, SPI_2, PIN_DATA(7, 1)}, - {PK6, SPI_3, PIN_DATA(4, 1)}, - {PD1, SPI_4, PIN_DATA(4, 1)}, - {PM2, SPI_5, PIN_DATA(6, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PA3, SPI_0, PIN_DATA(7, 1)}, - {PL3, SPI_1, PIN_DATA(7, 1)}, - {PA4, SPI_2, PIN_DATA(7, 1)}, - {PK4, SPI_3, PIN_DATA(4, 1)}, - {PD3, SPI_4, PIN_DATA(4, 1)}, - {PM0, SPI_5, PIN_DATA(6, 1)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PA2, SPI_0, PIN_DATA(7, 0)}, - {PL2, SPI_1, PIN_DATA(7, 0)}, - {PA5, SPI_2, PIN_DATA(7, 0)}, - {PK5, SPI_3, PIN_DATA(4, 0)}, - {PD2, SPI_4, PIN_DATA(4, 0)}, - {PM1, SPI_5, PIN_DATA(6, 0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PA0, SPI_0, PIN_DATA(7, 1)}, - {PL0, SPI_1, PIN_DATA(7, 1)}, - {PA7, SPI_2, PIN_DATA(7, 1)}, - {PK7, SPI_3, PIN_DATA(4, 1)}, - {PD0, SPI_4, PIN_DATA(4, 1)}, - {PM3, SPI_5, PIN_DATA(6, 1)}, - {NC, NC, 0} -}; -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Check pin parameters - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk); - obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->module!= NC); - - // Identify SPI module to use - switch ((int)obj->module) { - case SPI_0: - obj->p_obj.p_instance = TSB_TSPI0; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA04 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; - break; - case SPI_1: - obj->p_obj.p_instance = TSB_TSPI1; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA05 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB12 = TXZ_ENABLE; - break; - case SPI_2: - obj->p_obj.p_instance = TSB_TSPI2; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA06 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; - break; - case SPI_3: - obj->p_obj.p_instance = TSB_TSPI3; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA07 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB11 = TXZ_ENABLE; - break; - case SPI_4: - obj->p_obj.p_instance = TSB_TSPI4; - //Enable clock for particular Port and SPI - TSB_CG_FSYSENA_IPENA08 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB05 = TXZ_ENABLE; - break; - case SPI_5: - obj->p_obj.p_instance = TSB_TSPI6; - //Enable clock for particular Port and SPI - TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE; - TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE; - break; - default: - obj->p_obj.p_instance = NULL; - obj->module = (SPIName)NC; - error("Cannot found SPI module corresponding with input pins."); - break; - } - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - - // Default configurations 8 bit, 1Mhz frequency - //Control 1 configurations - obj->p_obj.init.id = (uint32_t)obj->module; - obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled - obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication - obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode - obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // master mode operation - obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) - obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid - obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // transfer single frame at a time contineously - - //Control 2 configurations - obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; - obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low - obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_SET; - obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level - obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level - obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; - obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; - obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; - obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; - obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; - obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; - obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; - - //Control 3 configurations - obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear - obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear - - //baudrate settings - 1Mhz default - obj->p_obj.init.brd.brck = BAUDRATE_1MHZ_BRCK; - obj->p_obj.init.brd.brs = BAUDRATE_1MHZ_BRS; - - //Format Control 0 settings - obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first - obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; - obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; - - //Special control on polarity of signal and generation timing - obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; - obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; - obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; - obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; - - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; - obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; - obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; - obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; - - //Format Control 1 settings tspi_fmtr1_t - obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; - obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; - - obj->bits = (uint8_t)TSPI_DATA_LENGTH_8; - - //initialize SPI - tspi_init(&obj->p_obj); -} - -void spi_free(spi_t *obj) -{ - tspi_deinit(&obj->p_obj); - obj->module = (SPIName)NC; -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - MBED_ASSERT((slave == 0U)); // 0: master mode, 1: slave mode - MBED_ASSERT((bits >= 8) && (bits <= 32)); - - obj->bits = bits; - obj->p_obj.init.fmr0.fl = (bits << 24); - - if((mode >> 1) & 0x1) { - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; - } else { - obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; - } - - if(mode & 0x1) { - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; - } else { - obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; - } - - tspi_init(&obj->p_obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - SystemCoreClockUpdate(); - uint8_t brs = 0, brck = 0; - uint16_t prsck = 1; - uint64_t fscl = 0, tmp_fscl = 0; - uint64_t fx = 0; - uint64_t tmpvar = SystemCoreClock / 2; - - for (prsck = 1; prsck <= 512; prsck *= 2) { - fx = ((uint64_t)tmpvar / prsck); - for (brs = 1; brs <= 16; brs++) { - fscl = fx /brs; - if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { - tmp_fscl = fscl; - obj->p_obj.init.brd.brck = (brck << 4); - if(brs == 16) { - obj->p_obj.init.brd.brs = 0; - } else { - obj->p_obj.init.brd.brs = brs; - } - } - } - brck ++; - } - - tspi_init(&obj->p_obj); -} - -int spi_master_write(spi_t *obj, int value) -{ - uint8_t ret_value = 0; - - tspi_transmit_t send_obj; - tspi_receive_t rec_obj; - - // Transmit data - send_obj.tx8.p_data = (uint8_t *)&value; - send_obj.tx8.num = 1; - tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT); - - // Read received data - rec_obj.rx8.p_data = &ret_value; - rec_obj.rx8.num = 1; - tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT); - - return ret_value; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) -{ - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_busy(spi_t *obj) -{ - int ret = 1; - uint32_t status; - tspi_get_status(&obj->p_obj, &status); - if((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { - ret = 0; - } - - return ret; -} - -uint8_t spi_get_module(spi_t *obj) -{ - return (uint8_t)(obj->module); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} diff --git a/targets/TARGET_TT/TARGET_TT_M4G9/us_ticker.c b/targets/TARGET_TT/TARGET_TT_M4G9/us_ticker.c deleted file mode 100644 index 38de88f50db..00000000000 --- a/targets/TARGET_TT/TARGET_TT_M4G9/us_ticker.c +++ /dev/null @@ -1,106 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "us_ticker_api.h" -#include "TMPM4G9.h" -#include "txz_t32a.h" - -#define CLR_TIMER_INT_FLAG (uint8_t)0x41 - -static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? - -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = { - 2496094, - 32 - }; - return &info; -} - -// initialize us_ticker -void us_ticker_init(void) -{ - if (us_ticker_inited) { - us_ticker_disable_interrupt(); - return; - } - us_ticker_inited = 1; - - // Enable clock for T32A0 - TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE; - - // T32A ch0 TimerC Reg Match/Over Flow/Under Flow - TSB_IB->IMC006 = TXZ_ENABLE; - - // Configure Timer T32A0 - TSB_T32A0->MOD = T32A_MODE_32; - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->CRC = T32A_PRSCLx_32; - TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); - NVIC_SetVector(INTT32A00_A_CT_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); -} - -uint32_t us_ticker_read(void) -{ - uint32_t ret_val = 0; - - if (!us_ticker_inited) { - us_ticker_init(); - } - - ret_val = (TSB_T32A0->TMRC); - return ret_val; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); - TSB_T32A0->RGC1 = timestamp ; - NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); - TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(INTT32A00_A_CT_IRQn); - NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - // Disable interrupts in NVIC - TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; - NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); - NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); -} - -void us_ticker_clear_interrupt(void) -{ - TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; - NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); -} - -void us_ticker_free(void) -{ - TSB_T32A0->RUNC = T32A_RUN_DISABLE; - TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; - NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); - NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); - TSB_CG_FSYSMENA_IPMENA06 = TXZ_DISABLE; -} diff --git a/targets/TARGET_TT/mbed_rtx.h b/targets/TARGET_TT/mbed_rtx.h deleted file mode 100644 index 1f9bc5c3191..00000000000 --- a/targets/TARGET_TT/mbed_rtx.h +++ /dev/null @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - - -#if defined(TARGET_TT_M3HQ) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20010000UL) -#endif - -#endif - -#if defined(TARGET_TT_M4G9) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20030000UL) -#endif - - -#endif - -#endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_WIO_EMW3166/libwiced_drivers.ar similarity index 100% rename from targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar rename to targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_WIO_EMW3166/libwiced_drivers.ar diff --git a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_WIO_EMW3166/libwiced_drivers.a similarity index 100% rename from targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a rename to targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_WIO_EMW3166/libwiced_drivers.a diff --git a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_WIO_EMW3166/libwiced_drivers.a similarity index 100% rename from targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a rename to targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_WIO_EMW3166/libwiced_drivers.a diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h b/targets/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h deleted file mode 100644 index 41b46421123..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h +++ /dev/null @@ -1,76 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" -#include "PinNames.h" -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_0 = (int)W7500x_ADC_BASE -} ADCName; - -typedef enum { - UART_0 = (int)W7500x_UART0_BASE, - UART_1 = (int)W7500x_UART1_BASE, - UART_2 = (int)W7500x_UART2_BASE -} UARTName; - - -typedef enum { - SPI_0 = (int)SSP0_BASE, - SPI_1 = (int)SSP1_BASE -} SPIName; - -typedef enum { - I2C_0 = (int)I2C0_BASE, - I2C_1 = (int)I2C1_BASE -} I2CName; - -typedef enum { - PWM_0 = (int)PWM_CH0_BASE, - PWM_1 = (int)PWM_CH1_BASE, - PWM_2 = (int)PWM_CH2_BASE, - PWM_3 = (int)PWM_CH3_BASE, - PWM_4 = (int)PWM_CH4_BASE, - PWM_5 = (int)PWM_CH5_BASE, - PWM_6 = (int)PWM_CH6_BASE, - PWM_7 = (int)PWM_CH7_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h b/targets/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h deleted file mode 100644 index 27930461f3a..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h +++ /dev/null @@ -1,60 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - - -//*** ADC *** -extern const PinMap PinMap_ADC[]; - -//*** SERIAL *** -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -//*** I2C *** -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - - -//*** SPI *** - -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SSEL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/PortNames.h b/targets/TARGET_WIZNET/TARGET_W7500x/PortNames.h deleted file mode 100644 index 6a8638752eb..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/PortNames.h +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB = 1, - PortC = 2, - PortD = 3, -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c deleted file mode 100644 index 574a13a6231..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c +++ /dev/null @@ -1,133 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" -#include "PeripheralNames.h" -#include "pinmap.h" - - -//*** ADC *** -const PinMap PinMap_ADC[] = { - {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 - {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 - {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 - {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 - {PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4 - {PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5 - {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6 - {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7 - {NC, NC, 0} -}; - - -//*** SERIAL *** -const PinMap PinMap_UART_TX[] = { - {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {NC, NC, 0} -}; - -//*** I2C *** -const PinMap PinMap_I2C_SDA[] = { - {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_SCLK[] = { - {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_PWM[] = { - {PA_0 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_1 , PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_6 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_3 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_10, PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_11, PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)} -}; - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h deleted file mode 100644 index 98d42a6836f..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h +++ /dev/null @@ -1,231 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM -#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE) << 8) | ((PUPD) << 4) | ((AFNUM) << 0))) -#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F) -#define WIZ_PIN_AFNUM(X) (((X) >> 0) & 0x0F) -#define WIZ_PIN_MODE(X) (((X) >> 8) & 0x0F) -#define WIZ_MODE_INPUT (0) -#define WIZ_MODE_OUTPUT (1) -#define WIZ_MODE_AF (2) - -#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */ -#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */ -#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */ -#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */ - - -#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D) -#define WIZ_PIN_NUM(X) ((uint32_t)(X) & 0xF) // pin number -#define WIZ_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit - - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - - -typedef enum { - // W7500x PORT[5:4] + PIN[3:0]) - PA_0 = 0x000, - PA_1 = 0x001, - PA_2 = 0x002, - PA_3 = 0x003, - PA_4 = 0x004, - PA_5 = 0x005, - PA_6 = 0x006, - PA_7 = 0x007, - PA_8 = 0x008, - PA_9 = 0x009, - PA_10 = 0x00A, - PA_11 = 0x00B, - PA_12 = 0x00C, - PA_13 = 0x00D, - PA_14 = 0x00E, - PA_15 = 0x00F, - - PB_0 = 0x010, - PB_1 = 0x011, - PB_2 = 0x012, - PB_3 = 0x013, - PB_4 = 0x014, - PB_5 = 0x015, - PB_6 = 0x016, - PB_7 = 0x017, - PB_8 = 0x018, - PB_9 = 0x019, - PB_10 = 0x01A, - PB_11 = 0x01B, - PB_12 = 0x01C, - PB_13 = 0x01D, - PB_14 = 0x01E, - PB_15 = 0x01F, - - PC_0 = 0x020, - PC_1 = 0x021, - PC_2 = 0x022, - PC_3 = 0x023, - PC_4 = 0x024, - PC_5 = 0x025, - PC_6 = 0x026, - PC_7 = 0x027, - PC_8 = 0x028, - PC_9 = 0x029, - - PC_10 = 0x02A, - PC_11 = 0x02B, - PC_12 = 0x02C, - PC_13 = 0x02D, - PC_14 = 0x02E, - PC_15 = 0x02F, - - PD_0 = 0x030, - PD_1 = 0x031, - PD_2 = 0x032, - PD_3 = 0x033, - PD_4 = 0x034, - - PA_00 = PA_0, - PA_01 = PA_1, - PA_02 = PA_2, - PA_03 = PA_3, - PA_04 = PA_4, - PA_05 = PA_5, - PA_06 = PA_6, - PA_07 = PA_7, - PA_08 = PA_8, - PA_09 = PA_9, - - PB_00 = PB_0, - PB_01 = PB_1, - PB_02 = PB_2, - PB_03 = PB_3, - PB_04 = PB_4, - PB_05 = PB_5, - PB_06 = PB_6, - PB_07 = PB_7, - PB_08 = PB_8, - PB_09 = PB_9, - - PC_00 = PC_0, - PC_01 = PC_1, - PC_02 = PC_2, - PC_03 = PC_3, - PC_04 = PC_4, - PC_05 = PC_5, - PC_06 = PC_6, - PC_07 = PC_7, - PC_08 = PC_8, - PC_09 = PC_9, - - PD_00 = PD_0, - PD_01 = PD_1, - PD_02 = PD_2, - PD_03 = PD_3, - PD_04 = PD_4, - - // Arduino connector namings - A0 = PC_15, // AIN0 - A1 = PC_14, // AIN1 - A2 = PC_13, // AIN2 - A3 = PC_12, // AIN3 - A4 = PC_11, // AIN4 - A5 = PC_10, // AIN5 - A6 = PC_9, // AIN6 - A7 = PC_8, // AIN7 - D0 = PA_14, - D1 = PA_13, - D2 = PC_1, - D3 = PC_0, - D4 = PA_2, - D5 = PA_1, - D6 = PA_0, - D7 = PC_6, - D8 = PC_7, - D9 = PC_4, - D10 = PA_5, - D11 = PA_8, - D12 = PA_7, - D13 = PA_6, - D14 = PA_10, - D15 = PA_9, - - // Generic signals namings - LED_RED = PC_8, - LED_GREEN = PC_9, - LED_BLUE = PC_5, - - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_BLUE, - - LEDR = LED_RED, - LEDG = LED_GREEN, - LEDB = LED_BLUE, - - USBTX = PC_2, - USBRX = PC_3, - - //Use SPI1 - SD_SEL = PB_0, // SPI1_CS - SD_CLK = PB_1, // SPI1_CLK - SD_MISO = PB_2, // MOSI1 - SD_MOSI = PB_3, // MISO1 - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullNone -} PinMode; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h deleted file mode 100644 index 951130a3571..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h +++ /dev/null @@ -1,61 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define STDIO_UART_TX PC_2 -#define STDIO_UART_RX PC_3 -#define STDIO_UART UART_1 - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_MICRO/W7500.sct b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_MICRO/W7500.sct deleted file mode 100644 index 044b6231ccc..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_MICRO/W7500.sct +++ /dev/null @@ -1,43 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x00020000 -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00004000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S deleted file mode 100644 index 30757ae38be..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S +++ /dev/null @@ -1,182 +0,0 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM0.s -; * @brief CMSIS Cortex-M0 Core Device Startup File for -; * Device CMSDK_CM0 -; * @version V3.01 -; * @date 06. March 2012 -; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER - -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler PROC - EXPORT SSP0_Handler [WEAK] - EXPORT SSP1_Handler [WEAK] - EXPORT UART0_Handler [WEAK] - EXPORT UART1_Handler [WEAK] - EXPORT UART2_Handler [WEAK] - EXPORT I2C0_Handler [WEAK] - EXPORT I2C1_Handler [WEAK] - EXPORT PORT0_Handler [WEAK] - EXPORT PORT1_Handler [WEAK] - EXPORT PORT2_Handler [WEAK] - EXPORT PORT3_Handler [WEAK] - EXPORT DMA_Handler [WEAK] - EXPORT DUALTIMER0_Handler [WEAK] - EXPORT DUALTIMER1_Handler [WEAK] - EXPORT PWM0_Handler [WEAK] - EXPORT PWM1_Handler [WEAK] - EXPORT PWM2_Handler [WEAK] - EXPORT PWM3_Handler [WEAK] - EXPORT PWM4_Handler [WEAK] - EXPORT PWM5_Handler [WEAK] - EXPORT PWM6_Handler [WEAK] - EXPORT PWM7_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT WZTOE_Handler [WEAK] - EXPORT EXTI_Handler [WEAK] -SSP0_Handler -SSP1_Handler -UART0_Handler -UART1_Handler -UART2_Handler -I2C0_Handler -I2C1_Handler -PORT0_Handler -PORT1_Handler -PORT2_Handler -PORT3_Handler -DMA_Handler -DUALTIMER0_Handler -DUALTIMER1_Handler -PWM0_Handler -PWM1_Handler -PWM2_Handler -PWM3_Handler -PWM4_Handler -PWM5_Handler -PWM6_Handler -PWM7_Handler -RTC_Handler -ADC_Handler -WZTOE_Handler -EXTI_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_STD/W7500.sct b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_STD/W7500.sct deleted file mode 100644 index eab548eb575..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_STD/W7500.sct +++ /dev/null @@ -1,25 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00020000 { ; load region size_region - ER_IROM1 0x00000000 0x00020000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00004000-Stack_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x20000000+0x00004000) EMPTY -Stack_Size { ; stack - } -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_STD/startup_W7500x.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_STD/startup_W7500x.S deleted file mode 100644 index 30757ae38be..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_STD/startup_W7500x.S +++ /dev/null @@ -1,182 +0,0 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM0.s -; * @brief CMSIS Cortex-M0 Core Device Startup File for -; * Device CMSDK_CM0 -; * @version V3.01 -; * @date 06. March 2012 -; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER - -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler PROC - EXPORT SSP0_Handler [WEAK] - EXPORT SSP1_Handler [WEAK] - EXPORT UART0_Handler [WEAK] - EXPORT UART1_Handler [WEAK] - EXPORT UART2_Handler [WEAK] - EXPORT I2C0_Handler [WEAK] - EXPORT I2C1_Handler [WEAK] - EXPORT PORT0_Handler [WEAK] - EXPORT PORT1_Handler [WEAK] - EXPORT PORT2_Handler [WEAK] - EXPORT PORT3_Handler [WEAK] - EXPORT DMA_Handler [WEAK] - EXPORT DUALTIMER0_Handler [WEAK] - EXPORT DUALTIMER1_Handler [WEAK] - EXPORT PWM0_Handler [WEAK] - EXPORT PWM1_Handler [WEAK] - EXPORT PWM2_Handler [WEAK] - EXPORT PWM3_Handler [WEAK] - EXPORT PWM4_Handler [WEAK] - EXPORT PWM5_Handler [WEAK] - EXPORT PWM6_Handler [WEAK] - EXPORT PWM7_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT WZTOE_Handler [WEAK] - EXPORT EXTI_Handler [WEAK] -SSP0_Handler -SSP1_Handler -UART0_Handler -UART1_Handler -UART2_Handler -I2C0_Handler -I2C1_Handler -PORT0_Handler -PORT1_Handler -PORT2_Handler -PORT3_Handler -DMA_Handler -DUALTIMER0_Handler -DUALTIMER1_Handler -PWM0_Handler -PWM1_Handler -PWM2_Handler -PWM3_Handler -PWM4_Handler -PWM5_Handler -PWM6_Handler -PWM7_Handler -RTC_Handler -ADC_Handler -WZTOE_Handler -EXTI_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/W7500.ld b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/W7500.ld deleted file mode 100644 index 2bab185cc48..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/W7500.ld +++ /dev/null @@ -1,160 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */ - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S deleted file mode 100644 index 48966901cbc..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S +++ /dev/null @@ -1,259 +0,0 @@ -/* File: startup_W7500.s - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.4 - * Date: 20 Dezember 2012 - * - */ -/* Copyright (c) 2011 - 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x200 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - -/* Vector Table */ - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long SSP0_Handler /* 16+ 0: SSP 0 Handler */ - .long SSP1_Handler /* 16+ 1: SSP 1 Handler */ - .long UART0_Handler /* 16+ 2: UART 0 Handler */ - .long UART1_Handler /* 16+ 3: UART 1 Handler */ - .long UART2_Handler /* 16+ 4: UART 2 Handler */ - .long I2C0_Handler /* 16+ 5: I2C 0 Handler */ - .long I2C1_Handler /* 16+ 6: I2C 1 Handler */ - .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */ - .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */ - .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */ - .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */ - .long DMA_Handler /* 16+11: DMA Combined Handler */ - .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */ - .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */ - .long PWM0_Handler /* 16+ 14: PWM0 Handler */ - .long PWM1_Handler /* 16+ 15: PWM1 Handler */ - .long PWM2_Handler /* 16+ 16: PWM2 Handler */ - .long PWM3_Handler /* 16+ 17: PWM3 Handler */ - .long PWM4_Handler /* 16+ 18: PWM4 Handler */ - .long PWM5_Handler /* 16+ 19: PWM5 Handler */ - .long PWM6_Handler /* 16+ 20: PWM6 Handler */ - .long PWM7_Handler /* 16+ 21: PWM7 Handler */ - .long RTC_Handler /* 16+ 22: RTC Handler */ - .long ADC_Handler /* 16+ 23: ADC Handler */ - .long WZTOE_Handler /* 16+ 24: WZTOE Handler */ - .long EXTI_Handler /* 16+ 25: EXTI Handler */ - - .size __isr_vector, . - __isr_vector -/* Reset Handler */ - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - subs r2, r1 - ble .LC3 - - movs r0, 0 -.LC2: - str r0, [r1, r2] - subs r2, 4 - bge .LC2 -.LC3: -#endif /* __STARTUP_CLEAR_BSS */ - - bl _start - //bl main - - .pool - .size Reset_Handler, . - Reset_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - -/* System Exception Handlers */ - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - -/* IRQ Handlers */ - - def_default_handler SSP0_Handler - def_default_handler SSP1_Handler - def_default_handler UART0_Handler - def_default_handler UART1_Handler - def_default_handler UART2_Handler - def_default_handler I2C0_Handler - def_default_handler I2C1_Handler - def_default_handler PORT0_Handler - def_default_handler PORT1_Handler - def_default_handler PORT2_Handler - def_default_handler PORT3_Handler - - def_default_handler DMA_Handler - def_default_handler DUALTIMER0_Handler - def_default_handler DUALTIMER1_Handler - def_default_handler PWM0_Handler - def_default_handler PWM1_Handler - def_default_handler PWM2_Handler - def_default_handler PWM3_Handler - def_default_handler PWM4_Handler - def_default_handler PWM5_Handler - def_default_handler PWM6_Handler - def_default_handler PWM7_Handler - def_default_handler RTC_Handler - def_default_handler ADC_Handler - def_default_handler WZTOE_Handler - def_default_handler EXTI_Handler - - /* - def_default_handler Default_Handler - .weak DEF_IRQHandler - .set DEF_IRQHandler, Default_Handler - */ - - .end - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf deleted file mode 100644 index 0aac2ee3ee5..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00020000; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20004000; -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x00000C00; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.S deleted file mode 100644 index 1b28c47f624..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.S +++ /dev/null @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright �� 2016 -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c deleted file mode 100644 index 03ad45093e5..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c +++ /dev/null @@ -1,136 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" -#include "PeripheralNames.h" -#include "pinmap.h" - - -//*** ADC *** -const PinMap PinMap_ADC[] = { - {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 - {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 - {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 - {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 - {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6 - {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7 - {NC, NC, 0} -}; - - -//*** SERIAL *** -const PinMap PinMap_UART_TX[] = { - {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PB_2, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, - {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PA_9, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, - {PC_10, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PC_6, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PB_3, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, - {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PA_10, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, - {PC_11, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PC_7, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, - {NC, NC, 0} -}; - -//*** I2C *** -const PinMap PinMap_I2C_SDA[] = { - {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC, NC, 0} -}; - -//*** SPI *** -const PinMap PinMap_SPI_SCLK[] = { - {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_PWM[] = { - {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_9 , PWM_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_1 , PWM_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_3 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_6 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {NC , NC , 0} -}; - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h deleted file mode 100644 index 5ad1ce7f8d1..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h +++ /dev/null @@ -1,228 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM -#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE) << 8) | ((PUPD) << 4) | ((AFNUM) << 0))) -#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F) -#define WIZ_PIN_AFNUM(X) (((X) >> 0) & 0x0F) -#define WIZ_PIN_MODE(X) (((X) >> 8) & 0x0F) -#define WIZ_MODE_INPUT (0) -#define WIZ_MODE_OUTPUT (1) -#define WIZ_MODE_AF (2) - -#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */ -#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */ -#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */ -#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */ - - -#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D) -#define WIZ_PIN_NUM(X) ((uint32_t)(X) & 0xF) // pin number -#define WIZ_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit - - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - - -typedef enum { - // W7500x PORT[5:4] + PIN[3:0]) - PA_0 = 0x000, - PA_1 = 0x001, - PA_2 = 0x002, - PA_3 = 0x003, - PA_4 = 0x004, - PA_5 = 0x005, - PA_6 = 0x006, - PA_7 = 0x007, - PA_8 = 0x008, - PA_9 = 0x009, - PA_10 = 0x00A, - PA_11 = 0x00B, - PA_12 = 0x00C, - PA_13 = 0x00D, - PA_14 = 0x00E, - PA_15 = 0x00F, - - PB_0 = 0x010, - PB_1 = 0x011, - PB_2 = 0x012, - PB_3 = 0x013, - PB_4 = 0x014, - PB_5 = 0x015, - PB_6 = 0x016, - PB_7 = 0x017, - PB_8 = 0x018, - PB_9 = 0x019, - PB_10 = 0x01A, - PB_11 = 0x01B, - PB_12 = 0x01C, - PB_13 = 0x01D, - PB_14 = 0x01E, - PB_15 = 0x01F, - - PC_0 = 0x020, - PC_1 = 0x021, - PC_2 = 0x022, - PC_3 = 0x023, - PC_4 = 0x024, - PC_5 = 0x025, - PC_6 = 0x026, - PC_7 = 0x027, - PC_8 = 0x028, - PC_9 = 0x029, - - PC_10 = 0x02A, - PC_11 = 0x02B, - PC_12 = 0x02C, - PC_13 = 0x02D, - PC_14 = 0x02E, - PC_15 = 0x02F, - - PD_0 = 0x030, - PD_1 = 0x031, - PD_2 = 0x032, - PD_3 = 0x033, - PD_4 = 0x034, - - PA_00 = PA_0, - PA_01 = PA_1, - PA_02 = PA_2, - PA_03 = PA_3, - PA_04 = PA_4, - PA_05 = PA_5, - PA_06 = PA_6, - PA_07 = PA_7, - PA_08 = PA_8, - PA_09 = PA_9, - - PB_00 = PB_0, - PB_01 = PB_1, - PB_02 = PB_2, - PB_03 = PB_3, - PB_04 = PB_4, - PB_05 = PB_5, - PB_06 = PB_6, - PB_07 = PB_7, - PB_08 = PB_8, - PB_09 = PB_9, - - PC_00 = PC_0, - PC_01 = PC_1, - PC_02 = PC_2, - PC_03 = PC_3, - PC_04 = PC_4, - PC_05 = PC_5, - PC_06 = PC_6, - PC_07 = PC_7, - PC_08 = PC_8, - PC_09 = PC_9, - - PD_00 = PD_0, - PD_01 = PD_1, - PD_02 = PD_2, - PD_03 = PD_3, - PD_04 = PD_4, - - - // Generic signals namings - LED1 = PA_01, - LED2 = PA_02, - LED3 = LED1, - LED4 = LED2, - - USBTX = PC_10, - USBRX = PC_11, - - // For ECO - P5 = PA_5, - P6 = PA_6, - P7 = PA_7, - P8 = PA_8, - P9 = PA_9, - P10 = PA_10, - P11 = PA_11, - P12 = PA_12, - P13 = PA_13, - P14 = PA_14, - P15 = PB_0, - P16 = PB_1, - P17 = PB_2, - P18 = PB_3, - P19 = PC_5, - P20 = PC_4, - P21 = PC_0, - P22 = PC_1, - P23 = PC_2, - P24 = PC_3, - P25 = PC_8, - P26 = PC_9, - P27 = PC_12, - P28 = PC_13, - P29 = PC_14, - P30 = PC_15, - P31 = PC_6, - P32 = PC_7, - - //Use SPI1 - SD_SEL = PB_0, // SPI1_CS - SD_CLK = PB_1, // SPI1_CLK - SD_MISO = PB_2, // MOSI1 - SD_MOSI = PB_3, // MISO1 - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullNone -} PinMode; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h deleted file mode 100644 index 1a077b07eaa..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h +++ /dev/null @@ -1,61 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define STDIO_UART_TX PC_10 -#define STDIO_UART_RX PC_11 -#define STDIO_UART UART_2 - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_MICRO/W7500.sct b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_MICRO/W7500.sct deleted file mode 100644 index 044b6231ccc..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_MICRO/W7500.sct +++ /dev/null @@ -1,43 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x00020000 -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00004000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S deleted file mode 100644 index 30757ae38be..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S +++ /dev/null @@ -1,182 +0,0 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM0.s -; * @brief CMSIS Cortex-M0 Core Device Startup File for -; * Device CMSDK_CM0 -; * @version V3.01 -; * @date 06. March 2012 -; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER - -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler PROC - EXPORT SSP0_Handler [WEAK] - EXPORT SSP1_Handler [WEAK] - EXPORT UART0_Handler [WEAK] - EXPORT UART1_Handler [WEAK] - EXPORT UART2_Handler [WEAK] - EXPORT I2C0_Handler [WEAK] - EXPORT I2C1_Handler [WEAK] - EXPORT PORT0_Handler [WEAK] - EXPORT PORT1_Handler [WEAK] - EXPORT PORT2_Handler [WEAK] - EXPORT PORT3_Handler [WEAK] - EXPORT DMA_Handler [WEAK] - EXPORT DUALTIMER0_Handler [WEAK] - EXPORT DUALTIMER1_Handler [WEAK] - EXPORT PWM0_Handler [WEAK] - EXPORT PWM1_Handler [WEAK] - EXPORT PWM2_Handler [WEAK] - EXPORT PWM3_Handler [WEAK] - EXPORT PWM4_Handler [WEAK] - EXPORT PWM5_Handler [WEAK] - EXPORT PWM6_Handler [WEAK] - EXPORT PWM7_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT WZTOE_Handler [WEAK] - EXPORT EXTI_Handler [WEAK] -SSP0_Handler -SSP1_Handler -UART0_Handler -UART1_Handler -UART2_Handler -I2C0_Handler -I2C1_Handler -PORT0_Handler -PORT1_Handler -PORT2_Handler -PORT3_Handler -DMA_Handler -DUALTIMER0_Handler -DUALTIMER1_Handler -PWM0_Handler -PWM1_Handler -PWM2_Handler -PWM3_Handler -PWM4_Handler -PWM5_Handler -PWM6_Handler -PWM7_Handler -RTC_Handler -ADC_Handler -WZTOE_Handler -EXTI_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_STD/W7500.sct b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_STD/W7500.sct deleted file mode 100644 index eab548eb575..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_STD/W7500.sct +++ /dev/null @@ -1,25 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00020000 { ; load region size_region - ER_IROM1 0x00000000 0x00020000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00004000-Stack_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x20000000+0x00004000) EMPTY -Stack_Size { ; stack - } -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_STD/startup_W7500x.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_STD/startup_W7500x.S deleted file mode 100644 index 30757ae38be..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_STD/startup_W7500x.S +++ /dev/null @@ -1,182 +0,0 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM0.s -; * @brief CMSIS Cortex-M0 Core Device Startup File for -; * Device CMSDK_CM0 -; * @version V3.01 -; * @date 06. March 2012 -; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER - -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler PROC - EXPORT SSP0_Handler [WEAK] - EXPORT SSP1_Handler [WEAK] - EXPORT UART0_Handler [WEAK] - EXPORT UART1_Handler [WEAK] - EXPORT UART2_Handler [WEAK] - EXPORT I2C0_Handler [WEAK] - EXPORT I2C1_Handler [WEAK] - EXPORT PORT0_Handler [WEAK] - EXPORT PORT1_Handler [WEAK] - EXPORT PORT2_Handler [WEAK] - EXPORT PORT3_Handler [WEAK] - EXPORT DMA_Handler [WEAK] - EXPORT DUALTIMER0_Handler [WEAK] - EXPORT DUALTIMER1_Handler [WEAK] - EXPORT PWM0_Handler [WEAK] - EXPORT PWM1_Handler [WEAK] - EXPORT PWM2_Handler [WEAK] - EXPORT PWM3_Handler [WEAK] - EXPORT PWM4_Handler [WEAK] - EXPORT PWM5_Handler [WEAK] - EXPORT PWM6_Handler [WEAK] - EXPORT PWM7_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT WZTOE_Handler [WEAK] - EXPORT EXTI_Handler [WEAK] -SSP0_Handler -SSP1_Handler -UART0_Handler -UART1_Handler -UART2_Handler -I2C0_Handler -I2C1_Handler -PORT0_Handler -PORT1_Handler -PORT2_Handler -PORT3_Handler -DMA_Handler -DUALTIMER0_Handler -DUALTIMER1_Handler -PWM0_Handler -PWM1_Handler -PWM2_Handler -PWM3_Handler -PWM4_Handler -PWM5_Handler -PWM6_Handler -PWM7_Handler -RTC_Handler -ADC_Handler -WZTOE_Handler -EXTI_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/W7500.ld b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/W7500.ld deleted file mode 100644 index 2bab185cc48..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/W7500.ld +++ /dev/null @@ -1,160 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */ - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S deleted file mode 100644 index 48966901cbc..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S +++ /dev/null @@ -1,259 +0,0 @@ -/* File: startup_W7500.s - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.4 - * Date: 20 Dezember 2012 - * - */ -/* Copyright (c) 2011 - 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x200 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - -/* Vector Table */ - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long SSP0_Handler /* 16+ 0: SSP 0 Handler */ - .long SSP1_Handler /* 16+ 1: SSP 1 Handler */ - .long UART0_Handler /* 16+ 2: UART 0 Handler */ - .long UART1_Handler /* 16+ 3: UART 1 Handler */ - .long UART2_Handler /* 16+ 4: UART 2 Handler */ - .long I2C0_Handler /* 16+ 5: I2C 0 Handler */ - .long I2C1_Handler /* 16+ 6: I2C 1 Handler */ - .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */ - .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */ - .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */ - .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */ - .long DMA_Handler /* 16+11: DMA Combined Handler */ - .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */ - .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */ - .long PWM0_Handler /* 16+ 14: PWM0 Handler */ - .long PWM1_Handler /* 16+ 15: PWM1 Handler */ - .long PWM2_Handler /* 16+ 16: PWM2 Handler */ - .long PWM3_Handler /* 16+ 17: PWM3 Handler */ - .long PWM4_Handler /* 16+ 18: PWM4 Handler */ - .long PWM5_Handler /* 16+ 19: PWM5 Handler */ - .long PWM6_Handler /* 16+ 20: PWM6 Handler */ - .long PWM7_Handler /* 16+ 21: PWM7 Handler */ - .long RTC_Handler /* 16+ 22: RTC Handler */ - .long ADC_Handler /* 16+ 23: ADC Handler */ - .long WZTOE_Handler /* 16+ 24: WZTOE Handler */ - .long EXTI_Handler /* 16+ 25: EXTI Handler */ - - .size __isr_vector, . - __isr_vector -/* Reset Handler */ - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - subs r2, r1 - ble .LC3 - - movs r0, 0 -.LC2: - str r0, [r1, r2] - subs r2, 4 - bge .LC2 -.LC3: -#endif /* __STARTUP_CLEAR_BSS */ - - bl _start - //bl main - - .pool - .size Reset_Handler, . - Reset_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - -/* System Exception Handlers */ - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - -/* IRQ Handlers */ - - def_default_handler SSP0_Handler - def_default_handler SSP1_Handler - def_default_handler UART0_Handler - def_default_handler UART1_Handler - def_default_handler UART2_Handler - def_default_handler I2C0_Handler - def_default_handler I2C1_Handler - def_default_handler PORT0_Handler - def_default_handler PORT1_Handler - def_default_handler PORT2_Handler - def_default_handler PORT3_Handler - - def_default_handler DMA_Handler - def_default_handler DUALTIMER0_Handler - def_default_handler DUALTIMER1_Handler - def_default_handler PWM0_Handler - def_default_handler PWM1_Handler - def_default_handler PWM2_Handler - def_default_handler PWM3_Handler - def_default_handler PWM4_Handler - def_default_handler PWM5_Handler - def_default_handler PWM6_Handler - def_default_handler PWM7_Handler - def_default_handler RTC_Handler - def_default_handler ADC_Handler - def_default_handler WZTOE_Handler - def_default_handler EXTI_Handler - - /* - def_default_handler Default_Handler - .weak DEF_IRQHandler - .set DEF_IRQHandler, Default_Handler - */ - - .end - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf deleted file mode 100644 index 0aac2ee3ee5..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00020000; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20004000; -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x00000C00; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.S deleted file mode 100644 index 1b28c47f624..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.S +++ /dev/null @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright �� 2016 -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c deleted file mode 100644 index 8023470f43d..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" -#include "PeripheralNames.h" -#include "pinmap.h" - - -//*** ADC *** -const PinMap PinMap_ADC[] = { - {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 - {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 - {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 - {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 - {PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4 - {PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5 - {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6 - {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7 - {NC, NC, 0} -}; - - -//*** SERIAL *** -const PinMap PinMap_UART_TX[] = { - {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PC_10, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {PC_11, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, - {NC, NC, 0} -}; - -//*** I2C *** -const PinMap PinMap_I2C_SDA[] = { - {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_SCLK[] = { - {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , 0} -}; - -const PinMap PinMap_PWM[] = { - {PA_0 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_1 , PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_6 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, - {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_3 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, - {PC_10, PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {PC_11, PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, - {NC , NC , WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)} -}; - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PinNames.h b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PinNames.h deleted file mode 100644 index 15b6f4a0f96..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PinNames.h +++ /dev/null @@ -1,230 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM -#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE) << 8) | ((PUPD) << 4) | ((AFNUM) << 0))) -#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F) -#define WIZ_PIN_AFNUM(X) (((X) >> 0) & 0x0F) -#define WIZ_PIN_MODE(X) (((X) >> 8) & 0x0F) -#define WIZ_MODE_INPUT (0) -#define WIZ_MODE_OUTPUT (1) -#define WIZ_MODE_AF (2) - -#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */ -#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */ -#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */ -#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */ - - -#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D) -#define WIZ_PIN_NUM(X) ((uint32_t)(X) & 0xF) // pin number -#define WIZ_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit - - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - - -typedef enum { - // W7500x PORT[5:4] + PIN[3:0]) - PA_0 = 0x000, - PA_1 = 0x001, - PA_2 = 0x002, - PA_3 = 0x003, - PA_4 = 0x004, - PA_5 = 0x005, - PA_6 = 0x006, - PA_7 = 0x007, - PA_8 = 0x008, - PA_9 = 0x009, - PA_10 = 0x00A, - PA_11 = 0x00B, - PA_12 = 0x00C, - PA_13 = 0x00D, - PA_14 = 0x00E, - PA_15 = 0x00F, - - PB_0 = 0x010, - PB_1 = 0x011, - PB_2 = 0x012, - PB_3 = 0x013, - PB_4 = 0x014, - PB_5 = 0x015, - PB_6 = 0x016, - PB_7 = 0x017, - PB_8 = 0x018, - PB_9 = 0x019, - PB_10 = 0x01A, - PB_11 = 0x01B, - PB_12 = 0x01C, - PB_13 = 0x01D, - PB_14 = 0x01E, - PB_15 = 0x01F, - - PC_0 = 0x020, - PC_1 = 0x021, - PC_2 = 0x022, - PC_3 = 0x023, - PC_4 = 0x024, - PC_5 = 0x025, - PC_6 = 0x026, - PC_7 = 0x027, - PC_8 = 0x028, - PC_9 = 0x029, - - PC_10 = 0x02A, - PC_11 = 0x02B, - PC_12 = 0x02C, - PC_13 = 0x02D, - PC_14 = 0x02E, - PC_15 = 0x02F, - - PD_0 = 0x030, - PD_1 = 0x031, - PD_2 = 0x032, - PD_3 = 0x033, - PD_4 = 0x034, - - PA_00 = PA_0, - PA_01 = PA_1, - PA_02 = PA_2, - PA_03 = PA_3, - PA_04 = PA_4, - PA_05 = PA_5, - PA_06 = PA_6, - PA_07 = PA_7, - PA_08 = PA_8, - PA_09 = PA_9, - - PB_00 = PB_0, - PB_01 = PB_1, - PB_02 = PB_2, - PB_03 = PB_3, - PB_04 = PB_4, - PB_05 = PB_5, - PB_06 = PB_6, - PB_07 = PB_7, - PB_08 = PB_8, - PB_09 = PB_9, - - PC_00 = PC_0, - PC_01 = PC_1, - PC_02 = PC_2, - PC_03 = PC_3, - PC_04 = PC_4, - PC_05 = PC_5, - PC_06 = PC_6, - PC_07 = PC_7, - PC_08 = PC_8, - PC_09 = PC_9, - - PD_00 = PD_0, - PD_01 = PD_1, - PD_02 = PD_2, - PD_03 = PD_3, - PD_04 = PD_4, - - // Arduino connector namings - A0 = PC_15, // AIN0 - A1 = PC_14, // AIN1 - A2 = PC_13, // AIN2 - A3 = PC_12, // AIN3 - A4 = PC_9, // AIN4 - A5 = PC_8, // AIN5 - - D0 = PA_14, - D1 = PA_13, - D2 = PC_3, - D3 = PC_2, - D4 = PA_2, - D5 = PA_1, - D6 = PA_0, - D7 = PA_12, - D8 = PA_11, - D9 = PC_1, - D10 = PA_5, - D11 = PA_8, - D12 = PA_7, - D13 = PA_6, - D14 = PA_10, - D15 = PA_9, - - // Generic signals namings - LED_RED = PC_0, - LED_GREEN = PC_4, - LED_BLUE = PC_5, - - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_BLUE, - - LEDR = LED_RED, - LEDG = LED_GREEN, - LEDB = LED_BLUE, - - USBTX = PC_10, - USBRX = PC_11, - - //Use SPI1 - SD_SEL = PB_0, // SPI1_CS - SD_CLK = PB_1, // SPI1_CLK - SD_MISO = PB_2, // MOSI1 - SD_MOSI = PB_3, // MISO1 - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullNone -} PinMode; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device.h b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device.h deleted file mode 100644 index c633df117be..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device.h +++ /dev/null @@ -1,60 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define STDIO_UART_TX PC_10 -#define STDIO_UART_RX PC_11 -#define STDIO_UART UART_2 - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_MICRO/W7500.sct b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_MICRO/W7500.sct deleted file mode 100644 index 044b6231ccc..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_MICRO/W7500.sct +++ /dev/null @@ -1,43 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x00020000 -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00004000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S deleted file mode 100644 index 30757ae38be..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_MICRO/startup_W7500x.S +++ /dev/null @@ -1,182 +0,0 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM0.s -; * @brief CMSIS Cortex-M0 Core Device Startup File for -; * Device CMSDK_CM0 -; * @version V3.01 -; * @date 06. March 2012 -; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER - -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler PROC - EXPORT SSP0_Handler [WEAK] - EXPORT SSP1_Handler [WEAK] - EXPORT UART0_Handler [WEAK] - EXPORT UART1_Handler [WEAK] - EXPORT UART2_Handler [WEAK] - EXPORT I2C0_Handler [WEAK] - EXPORT I2C1_Handler [WEAK] - EXPORT PORT0_Handler [WEAK] - EXPORT PORT1_Handler [WEAK] - EXPORT PORT2_Handler [WEAK] - EXPORT PORT3_Handler [WEAK] - EXPORT DMA_Handler [WEAK] - EXPORT DUALTIMER0_Handler [WEAK] - EXPORT DUALTIMER1_Handler [WEAK] - EXPORT PWM0_Handler [WEAK] - EXPORT PWM1_Handler [WEAK] - EXPORT PWM2_Handler [WEAK] - EXPORT PWM3_Handler [WEAK] - EXPORT PWM4_Handler [WEAK] - EXPORT PWM5_Handler [WEAK] - EXPORT PWM6_Handler [WEAK] - EXPORT PWM7_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT WZTOE_Handler [WEAK] - EXPORT EXTI_Handler [WEAK] -SSP0_Handler -SSP1_Handler -UART0_Handler -UART1_Handler -UART2_Handler -I2C0_Handler -I2C1_Handler -PORT0_Handler -PORT1_Handler -PORT2_Handler -PORT3_Handler -DMA_Handler -DUALTIMER0_Handler -DUALTIMER1_Handler -PWM0_Handler -PWM1_Handler -PWM2_Handler -PWM3_Handler -PWM4_Handler -PWM5_Handler -PWM6_Handler -PWM7_Handler -RTC_Handler -ADC_Handler -WZTOE_Handler -EXTI_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_STD/W7500.sct b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_STD/W7500.sct deleted file mode 100644 index eab548eb575..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_STD/W7500.sct +++ /dev/null @@ -1,25 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00020000 { ; load region size_region - ER_IROM1 0x00000000 0x00020000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00004000-Stack_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x20000000+0x00004000) EMPTY -Stack_Size { ; stack - } -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_STD/startup_W7500x.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_STD/startup_W7500x.S deleted file mode 100644 index 30757ae38be..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_STD/startup_W7500x.S +++ /dev/null @@ -1,182 +0,0 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM0.s -; * @brief CMSIS Cortex-M0 Core Device Startup File for -; * Device CMSDK_CM0 -; * @version V3.01 -; * @date 06. March 2012 -; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER - -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler PROC - EXPORT SSP0_Handler [WEAK] - EXPORT SSP1_Handler [WEAK] - EXPORT UART0_Handler [WEAK] - EXPORT UART1_Handler [WEAK] - EXPORT UART2_Handler [WEAK] - EXPORT I2C0_Handler [WEAK] - EXPORT I2C1_Handler [WEAK] - EXPORT PORT0_Handler [WEAK] - EXPORT PORT1_Handler [WEAK] - EXPORT PORT2_Handler [WEAK] - EXPORT PORT3_Handler [WEAK] - EXPORT DMA_Handler [WEAK] - EXPORT DUALTIMER0_Handler [WEAK] - EXPORT DUALTIMER1_Handler [WEAK] - EXPORT PWM0_Handler [WEAK] - EXPORT PWM1_Handler [WEAK] - EXPORT PWM2_Handler [WEAK] - EXPORT PWM3_Handler [WEAK] - EXPORT PWM4_Handler [WEAK] - EXPORT PWM5_Handler [WEAK] - EXPORT PWM6_Handler [WEAK] - EXPORT PWM7_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT WZTOE_Handler [WEAK] - EXPORT EXTI_Handler [WEAK] -SSP0_Handler -SSP1_Handler -UART0_Handler -UART1_Handler -UART2_Handler -I2C0_Handler -I2C1_Handler -PORT0_Handler -PORT1_Handler -PORT2_Handler -PORT3_Handler -DMA_Handler -DUALTIMER0_Handler -DUALTIMER1_Handler -PWM0_Handler -PWM1_Handler -PWM2_Handler -PWM3_Handler -PWM4_Handler -PWM5_Handler -PWM6_Handler -PWM7_Handler -RTC_Handler -ADC_Handler -WZTOE_Handler -EXTI_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/W7500.ld b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/W7500.ld deleted file mode 100644 index 2bab185cc48..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/W7500.ld +++ /dev/null @@ -1,160 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */ - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/startup_W7500.S deleted file mode 100644 index 48966901cbc..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/startup_W7500.S +++ /dev/null @@ -1,259 +0,0 @@ -/* File: startup_W7500.s - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.4 - * Date: 20 Dezember 2012 - * - */ -/* Copyright (c) 2011 - 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x200 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - -/* Vector Table */ - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long SSP0_Handler /* 16+ 0: SSP 0 Handler */ - .long SSP1_Handler /* 16+ 1: SSP 1 Handler */ - .long UART0_Handler /* 16+ 2: UART 0 Handler */ - .long UART1_Handler /* 16+ 3: UART 1 Handler */ - .long UART2_Handler /* 16+ 4: UART 2 Handler */ - .long I2C0_Handler /* 16+ 5: I2C 0 Handler */ - .long I2C1_Handler /* 16+ 6: I2C 1 Handler */ - .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */ - .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */ - .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */ - .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */ - .long DMA_Handler /* 16+11: DMA Combined Handler */ - .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */ - .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */ - .long PWM0_Handler /* 16+ 14: PWM0 Handler */ - .long PWM1_Handler /* 16+ 15: PWM1 Handler */ - .long PWM2_Handler /* 16+ 16: PWM2 Handler */ - .long PWM3_Handler /* 16+ 17: PWM3 Handler */ - .long PWM4_Handler /* 16+ 18: PWM4 Handler */ - .long PWM5_Handler /* 16+ 19: PWM5 Handler */ - .long PWM6_Handler /* 16+ 20: PWM6 Handler */ - .long PWM7_Handler /* 16+ 21: PWM7 Handler */ - .long RTC_Handler /* 16+ 22: RTC Handler */ - .long ADC_Handler /* 16+ 23: ADC Handler */ - .long WZTOE_Handler /* 16+ 24: WZTOE Handler */ - .long EXTI_Handler /* 16+ 25: EXTI Handler */ - - .size __isr_vector, . - __isr_vector -/* Reset Handler */ - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - subs r2, r1 - ble .LC3 - - movs r0, 0 -.LC2: - str r0, [r1, r2] - subs r2, 4 - bge .LC2 -.LC3: -#endif /* __STARTUP_CLEAR_BSS */ - - bl _start - //bl main - - .pool - .size Reset_Handler, . - Reset_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - -/* System Exception Handlers */ - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - -/* IRQ Handlers */ - - def_default_handler SSP0_Handler - def_default_handler SSP1_Handler - def_default_handler UART0_Handler - def_default_handler UART1_Handler - def_default_handler UART2_Handler - def_default_handler I2C0_Handler - def_default_handler I2C1_Handler - def_default_handler PORT0_Handler - def_default_handler PORT1_Handler - def_default_handler PORT2_Handler - def_default_handler PORT3_Handler - - def_default_handler DMA_Handler - def_default_handler DUALTIMER0_Handler - def_default_handler DUALTIMER1_Handler - def_default_handler PWM0_Handler - def_default_handler PWM1_Handler - def_default_handler PWM2_Handler - def_default_handler PWM3_Handler - def_default_handler PWM4_Handler - def_default_handler PWM5_Handler - def_default_handler PWM6_Handler - def_default_handler PWM7_Handler - def_default_handler RTC_Handler - def_default_handler ADC_Handler - def_default_handler WZTOE_Handler - def_default_handler EXTI_Handler - - /* - def_default_handler Default_Handler - .weak DEF_IRQHandler - .set DEF_IRQHandler, Default_Handler - */ - - .end - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf deleted file mode 100644 index 0aac2ee3ee5..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00020000; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20004000; -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x00000C00; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.S deleted file mode 100644 index 1b28c47f624..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.S +++ /dev/null @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright �� 2016 -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c deleted file mode 100644 index 294bfa7eeea..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c +++ /dev/null @@ -1,56 +0,0 @@ -#include "W7500x.h" -#include "W7500x_adc.h" - -void ADC_PowerDownEnable (FunctionalState NewState) -{ - if (NewState != DISABLE) ADC->ADC_CTR = ADC_CTR_PWD_PD; - else ADC->ADC_CTR = ADC_CTR_PWD_NRMOP; -} - -void ADC_ChannelSelect (ADC_CH num) -{ - assert_param(IS_ADC_CH_NUM(num)); - ADC->ADC_CHSEL = num; -} - -void ADC_Start (void) -{ - ADC->ADC_START = ADC_START_START; -} - -uint16_t ADC_ReadData (void) -{ - return ((uint16_t)ADC->ADC_DATA); -} - -void ADC_InterruptMask (FunctionalState NewState) -{ - if (NewState != DISABLE) ADC->ADC_INT = ADC_INT_MASK_ENA; - else ADC->ADC_INT = ADC_INT_MASK_DIS; -} - -uint8_t ADC_IsInterrupt (void) -{ - return (((uint8_t)ADC->ADC_INT && 0x01ul)); -} - -void ADC_InterruptClear (void) -{ - ADC->ADC_INT = ADC_INTCLEAR; -} - -void ADC_Init (void) -{ - // ADC_CLK on - ADC_PowerDownEnable(ENABLE); - ADC_PowerDownEnable(DISABLE); - //ADC_ChannelSelect(num); -} - -void ADC_DeInit (void) -{ - // ADC_CLK off - ADC_PowerDownEnable(ENABLE); - ADC_InterruptMask(DISABLE); -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.h b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.h deleted file mode 100644 index 7985370e332..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - ****************************************************************************** - * @file - * @author - * @version - * @date - * @brief This file contains all the functions prototypes for the ADC - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __W7500X_ADC_H -#define __W7500X_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "W7500x.h" - -typedef enum { ADC_CH0 = 0, - ADC_CH1 = 1, - ADC_CH2 = 2, - ADC_CH3 = 3, - ADC_CH4 = 4, - ADC_CH5 = 5, - ADC_CH6 = 6, - ADC_CH7 = 7, - ADC_CH15 = 15} ADC_CH; - -#define IS_ADC_CH_NUM(NUM) (((NUM) == ADC_CH0) || \ - ((NUM) == ADC_CH1) || \ - ((NUM) == ADC_CH2) || \ - ((NUM) == ADC_CH3) || \ - ((NUM) == ADC_CH4) || \ - ((NUM) == ADC_CH5) || \ - ((NUM) == ADC_CH6) || \ - ((NUM) == ADC_CH7) || \ - ((NUM) == ADC_CH15)) - -void ADC_Init(void); -void ADC_DeInit(void); -void ADC_PowerDownEnable (FunctionalState NewState); -void ADC_ChannelSelect (ADC_CH num); -void ADC_Start (void); -uint16_t ADC_ReadData (void); -void ADC_InterruptMask (FunctionalState NewState); -uint8_t ADC_IsInterrupt (void); -void ADC_InterruptClear (void); - -#ifdef __cplusplus - } -#endif - -#endif //__W7500X_ADC_H diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_conf.h b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_conf.h deleted file mode 100644 index 871a6db3e6e..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_conf.h +++ /dev/null @@ -1,16 +0,0 @@ -#include "W7500x_gpio.h" -#include "W7500x_exti.h" -#include "W7500x_pwm.h" -#include "W7500x_uart.h" -#include "W7500x_i2c.h" -#include "W7500x_adc.h" -#include "W7500x_dualtimer.h" -#include "system_W7500x.h" - - -#ifdef USE_FULL_ASSERT - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__)) -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.c deleted file mode 100644 index f533e1d2ba6..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.c +++ /dev/null @@ -1,276 +0,0 @@ -#include "W7500x_crg.h" - -void CRG_DeInit(void) -{ -//To Do -} - -void CRG_OSC_PowerDownEnable(FunctionalState NewState) -{ - if(NewState != DISABLE) CRG->OSC_PDR = CRG_OSC_PDR_PD; - else CRG->OSC_PDR = CRG_OSC_PDR_NRMLOP; -} - -void CRG_PLL_PowerDownEnable(FunctionalState NewState) -{ - if(NewState != DISABLE) CRG->PLL_PDR = CRG_PLL_PDR_PD; - else CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP; -} - -void CRG_PLL_OutputEnable(FunctionalState NewState) -{ - if(NewState != DISABLE) CRG->PLL_OER = CRG_PLL_OER_EN; - else CRG->PLL_OER = CRG_PLL_OER_DIS; -} - -void CRG_PLL_BypassEnable(FunctionalState NewState) -{ - if(NewState != DISABLE) CRG->PLL_BPR = CRG_PLL_BPR_EN; - else CRG->PLL_BPR = CRG_PLL_BPR_DIS; -} - -void CRG_PLL_InputFrequencySelect(CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_PLL_SRC(src)); - - if( src == CRG_RCLK ) CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; - else CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; -} - -void CRG_FCLK_SourceSelect(CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_FCLK_SRC(src)); - - if ( src == CRG_RCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_RCLK; - else if ( src == CRG_OCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_OCLK; - else CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK; -} - -void CRG_FCLK_SetPrescale(CRG_PREDIV prediv) -{ - assert_param(IS_CRG_FCLK_PREDIV(prediv)); - - if ( prediv == CRG_PREDIV1 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1; - else if ( prediv == CRG_PREDIV2 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV2; - else if ( prediv == CRG_PREDIV4 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV4; - else CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV8; -} - -void CRG_SSPCLK_SourceSelect(CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_SSPCLK_SRC(src)); - - if ( src == CRG_CLK_DIS ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS; - else if ( src == CRG_MCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; - else if ( src == CRG_RCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_RCLK; - else CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_OCLK; -} - -void CRG_SSPCLK_SetPrescale(CRG_PREDIV prediv) -{ - assert_param(IS_CRG_SSPCLK_PREDIV(prediv)); - - if ( prediv == CRG_PREDIV1 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; - else if ( prediv == CRG_PREDIV2 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV2; - else if ( prediv == CRG_PREDIV4 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV4; - else CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV8; -} - -void CRG_ADCCLK_SourceSelect(CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_ADCCLK_SRC(src)); - - if ( src == CRG_CLK_DIS ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS; - else if ( src == CRG_MCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_MCLK; - else if ( src == CRG_RCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_RCLK; - else CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_OCLK; -} - -void CRG_ADCCLK_SetPrescale(CRG_PREDIV prediv) -{ - assert_param(IS_CRG_ADCCLK_PREDIV(prediv)); - - if ( prediv == CRG_PREDIV1 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1; - else if ( prediv == CRG_PREDIV2 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV2; - else if ( prediv == CRG_PREDIV4 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV4; - else CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV8; -} - -void CRG_TIMERCLK_SourceSelect(CRG_TIMER num, CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_TIMERCLK_NUM(num)); - assert_param(IS_CRG_TIMERCLK_SRC(src)); - - if ( src == CRG_CLK_DIS ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_DIS); - else if ( src == CRG_MCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_MCLK); - else if ( src == CRG_RCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_RCLK); - else CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_OCLK); -} - -void CRG_TIMERCLK_SetPrescale(CRG_TIMER num, CRG_PREDIV prediv) -{ - assert_param(IS_CRG_TIMERCLK_NUM(num)); - assert_param(IS_CRG_TIMERCLK_PREDIV(prediv)); - - if ( prediv == CRG_PREDIV1 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV1); - else if ( prediv == CRG_PREDIV2 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV2); - else if ( prediv == CRG_PREDIV4 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV4); - else if ( prediv == CRG_PREDIV8 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV8); - else if ( prediv == CRG_PREDIV16 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV16); - else if ( prediv == CRG_PREDIV32 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV32); - else if ( prediv == CRG_PREDIV64 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV64); - else CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV128); -} - -void CRG_PWMCLK_SourceSelect(CRG_PWM num, CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_PWMCLK_NUM(num)); - assert_param(IS_CRG_PWMCLK_SRC(src)); - - if ( src == CRG_CLK_DIS ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_DIS); - else if ( src == CRG_MCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_MCLK); - else if ( src == CRG_RCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_RCLK); - else CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_OCLK); -} - -void CRG_PWMCLK_SetPrescale(CRG_PWM num, CRG_PREDIV prediv) -{ - assert_param(IS_CRG_PWMCLK_NUM(num)); - assert_param(IS_CRG_PWMCLK_PREDIV(prediv)); - - if ( prediv == CRG_PREDIV1 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV1); - else if ( prediv == CRG_PREDIV2 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV2); - else if ( prediv == CRG_PREDIV4 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV4); - else if ( prediv == CRG_PREDIV8 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV8); - else if ( prediv == CRG_PREDIV16 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV16); - else if ( prediv == CRG_PREDIV32 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV32); - else if ( prediv == CRG_PREDIV64 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV64); - else CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV128); -} - -void CRG_RTC_HS_SourceSelect(CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_RTC_HS_SRC(src)); - - if ( src == CRG_CLK_DIS ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_DIS; - else if ( src == CRG_MCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_MCLK; - else if ( src == CRG_RCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_RCLK; - else CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_OCLK; - - if ( src != CRG_CLK_DIS ) CRG_RTC_SourceSelect(CRG_CLK_HIGH); -} - -void CRG_RTC_HS_SetPrescale(CRG_PREDIV prediv) -{ - assert_param(IS_CRG_RTC_HS_PREDIV(prediv)); - - if ( prediv == CRG_PREDIV1 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV1; - else if ( prediv == CRG_PREDIV2 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV2; - else if ( prediv == CRG_PREDIV4 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV4; - else if ( prediv == CRG_PREDIV8 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV8; - else if ( prediv == CRG_PREDIV16 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV16; - else if ( prediv == CRG_PREDIV32 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV32; - else if ( prediv == CRG_PREDIV64 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV64; - else CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV128; -} - -void CRG_RTC_SourceSelect(CRG_CLK_LOW_SOURCE src) -{ - assert_param(IS_CRG_RTC_LOW_SRC(src)); - - if (src == CRG_CLK_LOW) - { - CRG_RTC_HS_SourceSelect(CRG_CLK_DIS); - CRG->RTC_SSR = CRG_RTC_SSR_LW; - } - else - { - CRG->RTC_SSR = CRG_RTC_SSR_HS; - } -} - -void CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_WDOGCLK_HS_SRC(src)); - - if ( src == CRG_CLK_DIS ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_DIS; - else if ( src == CRG_MCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_MCLK; - else if ( src == CRG_RCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_RCLK; - else CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_OCLK; - - if ( src != CRG_CLK_DIS ) CRG_WDOGCLK_SourceSelect(CRG_CLK_HIGH); -} - -void CRG_WDOGCLK_HS_SetPrescale(CRG_PREDIV prediv) -{ - assert_param(IS_CRG_WDOGCLK_HS_PREDIV(prediv)); - - if ( prediv == CRG_PREDIV1 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV1; - else if ( prediv == CRG_PREDIV2 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV2; - else if ( prediv == CRG_PREDIV4 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV4; - else if ( prediv == CRG_PREDIV8 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV8; - else if ( prediv == CRG_PREDIV16 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV16; - else if ( prediv == CRG_PREDIV32 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV32; - else if ( prediv == CRG_PREDIV64 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV64; - else CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV128; -} - -void CRG_WDOGCLK_SourceSelect(CRG_CLK_LOW_SOURCE src) -{ - assert_param(IS_CRG_WDOGCLK_LOW_SRC(src)); - - if (src == CRG_CLK_LOW) - { - CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_DIS); - CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_LW; - } - else - { - CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_HS; - } -} - -void CRG_UARTCLK_SourceSelect(CRG_CLK_SOURCE src) -{ - assert_param(IS_CRG_UARTCLK_SRC(src)); - - if ( src == CRG_CLK_DIS ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_DIS; - else if ( src == CRG_MCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK; - else if ( src == CRG_RCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; - else CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK; -} - -void CRG_UARTCLK_SetPrescale(CRG_PREDIV prediv) -{ - assert_param(IS_CRG_UARTCLK_PREDIV(prediv)); - - if ( prediv == CRG_PREDIV1 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1; - else if ( prediv == CRG_PREDIV2 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV2; - else if ( prediv == CRG_PREDIV4 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV4; - else CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV8; -} - -void CRG_MII_Enable(FunctionalState rx_clk, FunctionalState tx_clk) -{ - assert_param(IS_FUNCTIONAL_STATE(rx_clk)); - assert_param(IS_FUNCTIONAL_STATE(tx_clk)); - - if ( rx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_RXCLK; - else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_RXCLK); - - if ( tx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_TXCLK; - else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_TXCLK); -} - -void CRG_SetMonitoringClock(uint32_t value) -{ - assert_param(IS_CRG_MONCLK_SSR(value)); - - CRG->MONCLK_SSR = value; -} - -uint32_t CRG_GetMonitoringClock(void) -{ - return (uint8_t)CRG->MONCLK_SSR; -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.h b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.h deleted file mode 100644 index 28a60d1e459..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.h +++ /dev/null @@ -1,145 +0,0 @@ -/** - ****************************************************************************** - * @file - * @author - * @version - * @date - * @brief This file contains all the functions prototypes for the Clock Reset Generator - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __W7500X_CRG_H -#define __W7500X_CRG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "W7500x.h" - -// It will be in W7500x_crg.h -typedef enum { CRG_CLK_DIS = 0, CRG_MCLK, CRG_RCLK, CRG_OCLK } CRG_CLK_SOURCE; -typedef enum { CRG_CLK_HIGH = 0, CRG_CLK_LOW } CRG_CLK_LOW_SOURCE; -typedef enum { CRG_PREDIV1 = 0, CRG_PREDIV2, CRG_PREDIV4, CRG_PREDIV8, CRG_PREDIV16, \ - CRG_PREDIV32, CRG_PREDIV64, CRG_PREDIV128 } CRG_PREDIV; -typedef enum { CRG_TIMER0 = 0, CRG_TIMER1 } CRG_TIMER; -typedef enum { CRG_PWM0 = 0, CRG_PWM1, CRG_PWM2, CRG_PWM3, CRG_PWM4, CRG_PWM5, CRG_PWM6, CRG_PWM7 } CRG_PWM; - - - -#define IS_CRG_PLL_SRC(SRC) (((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) -#define IS_CRG_FCLK_SRC(SRC) (((SRC) == CRG_MCLK) || ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) - -#define CRG_CLK_SRC_DEFAULT(SRC) (((SRC) == CRG_CLK_DIS) || ((SRC) == CRG_MCLK) || \ - ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) -#define CRG_CLK_SRC_LOW(SRC) (((SRC) == CRG_CLK_HIGH) || ((SRC) == CRG_CLK_LOW)) - -#define CRG_CLK_PREDIV_DEFAULT(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \ - ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8)) -#define CRG_CLK_PREDIV_ADVANCE(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \ - ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8) || \ - ((DIV) == CRG_PREDIV16) || ((DIV) == CRG_PREDIV32) || \ - ((DIV) == CRG_PREDIV64) || ((DIV) == CRG_PREDIV128)) - - -#define IS_CRG_FCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) - -#define IS_CRG_SSPCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) -#define IS_CRG_SSPCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) - -#define IS_CRG_ADCCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) -#define IS_CRG_ADCCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) - - - - - -#define IS_CRG_TIMERCLK_NUM(NUM) (((NUM) == CRG_TIMER0) || ((NUM) == CRG_TIMER1)) -#define IS_CRG_TIMERCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) -#define IS_CRG_TIMERCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) - -#define CRG_SET_TIMERCLK_SSR(NUM,VALUE) \ - (*((volatile uint32_t *)(CRG->TIMER0CLK_SSR) + (0x10ul * NUM)) = VALUE) -#define CRG_SET_TIMERCLK_PREDIV(NUM,VALUE) \ - (*((volatile uint32_t *)(CRG->TIMER0CLK_PVSR) + (0x10ul * NUM)) = VALUE) -//#define CRG_SET_TIMERCLK_SSR(num,value) CRG->TIMER##num##CLK_SSR = value -//#define CRG_SET_TIMERCLK_PREDIV(num,value) CRG->TIMER##num##CLK_PVSR = value - - -#define IS_CRG_PWMCLK_NUM(NUM) (((NUM) == CRG_PWM0) || ((NUM) == CRG_PWM1) || \ - ((NUM) == CRG_PWM2) || ((NUM) == CRG_PWM3) || \ - ((NUM) == CRG_PWM4) || ((NUM) == CRG_PWM5) || \ - ((NUM) == CRG_PWM6) || ((NUM) == CRG_PWM7) ) -#define IS_CRG_PWMCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) -#define IS_CRG_PWMCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) - -#define CRG_SET_PWMCLK_SSR(NUM,VALUE) \ - (*((volatile uint32_t *)(CRG->PWM0CLK_SSR) + (0x10ul * NUM)) = VALUE) -#define CRG_SET_PWMCLK_PREDIV(NUM,VALUE) \ - (*((volatile uint32_t *)(CRG->PWM0CLK_PVSR) + (0x10ul * NUM)) = VALUE) -//#define CRG_SET_PWMCLK_SSR(num,value) CRG->PWM##num##CLK_SSR = value -//#define CRG_SET_PWMCLK_PREDIV(num,value) CRG->PWM##num##CLK_PVSR = value - -#define IS_CRG_RTC_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) -#define IS_CRG_RTC_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) -#define IS_CRG_RTC_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC) - -#define IS_CRG_WDOGCLK_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) -#define IS_CRG_WDOGCLK_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) -#define IS_CRG_WDOGCLK_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC) - -#define IS_CRG_UARTCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) -#define IS_CRG_UARTCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) - -#define IS_CRG_MONCLK_SSR(value) (((value) >= 0x00ul) || ((value) <= 0x13ul)) - -void CRG_DeInit(void); -void CRG_OSC_PowerDownEnable (FunctionalState NewState); -void CRG_PLL_PowerDownEnable (FunctionalState NewState); -void CRG_PLL_OutputEnable (FunctionalState NewState); -void CRG_PLL_BypassEnable (FunctionalState NewState); -void CRG_PLL_InputFrequencySelect (CRG_CLK_SOURCE src); - -void CRG_FCLK_SourceSelect (CRG_CLK_SOURCE src); -void CRG_FCLK_SetPrescale (CRG_PREDIV prediv); - -void CRG_SSPCLK_SourceSelect (CRG_CLK_SOURCE src); -void CRG_SSPCLK_SetPrescale (CRG_PREDIV prediv); - -void CRG_ADCCLK_SourceSelect (CRG_CLK_SOURCE src); -void CRG_ADCCLK_SetPrescale (CRG_PREDIV prediv); - -void CRG_TIMERCLK_SourceSelect (CRG_TIMER num, CRG_CLK_SOURCE src); -void CRG_TIMERCLK_SetPrescale (CRG_TIMER num, CRG_PREDIV prediv); - -void CRG_PWMCLK_SourceSelect (CRG_PWM num, CRG_CLK_SOURCE src); -void CRG_PWMCLK_SetPrescale (CRG_PWM num, CRG_PREDIV prediv); - -void CRG_RTC_HS_SourceSelect (CRG_CLK_SOURCE src); -void CRG_RTC_HS_SetPrescale (CRG_PREDIV prediv); -void CRG_RTC_SourceSelect (CRG_CLK_LOW_SOURCE src); - -void CRG_WDOGCLK_HS_SourceSelect (CRG_CLK_SOURCE src); -void CRG_WDOGCLK_HS_SetPrescale (CRG_PREDIV prediv); -void CRG_WDOGCLK_SourceSelect (CRG_CLK_LOW_SOURCE src); - -void CRG_UARTCLK_SourceSelect (CRG_CLK_SOURCE src); -void CRG_UARTCLK_SetPrescale (CRG_PREDIV prediv); - -void CRG_MII_Enable (FunctionalState rx_clk, FunctionalState tx_clk); - -void CRG_SetMonitoringClock (uint32_t value); -uint32_t CRG_GetMonitoringClock (void); - - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_dualtimer.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_dualtimer.c deleted file mode 100644 index 4b28fa56f54..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_dualtimer.c +++ /dev/null @@ -1,206 +0,0 @@ -/** - ****************************************************************************** - * @file W7500x_stdPeriph_Driver/src/W7500x_dualtimer.c - * @author IOP Team - * @version v1.0.0 - * @date 01-May-2015 - * @brief This file contains all the functions prototypes for the dualtimer - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Includes -------------------------------------------*/ -#include "W7500x.h" -#include "W7500x_dualtimer.h" - -void DUALTIMER_ClockEnable(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - if(DUALTIMERn == DUALTIMER0_0) - TIMCLKEN0_0 = DUALTIMER_Clock_Enable; - else if(DUALTIMERn == DUALTIMER0_1) - TIMCLKEN0_1 = DUALTIMER_Clock_Enable; - else if(DUALTIMERn == DUALTIMER1_0) - TIMCLKEN1_0 = DUALTIMER_Clock_Enable; - else if(DUALTIMERn == DUALTIMER1_1) - TIMCLKEN1_1 = DUALTIMER_Clock_Enable; -} - -void DUALTIMER_ClockDisable(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - if(DUALTIMERn == DUALTIMER0_0) - TIMCLKEN0_0 = DUALTIMER_Clock_Disable; - else if(DUALTIMERn == DUALTIMER0_1) - TIMCLKEN0_1 = DUALTIMER_Clock_Disable; - else if(DUALTIMERn == DUALTIMER1_0) - TIMCLKEN1_0 = DUALTIMER_Clock_Disable; - else if(DUALTIMERn == DUALTIMER1_1) - TIMCLKEN1_1 = DUALTIMER_Clock_Disable; -} - -void DUALTIMER_DeInit(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - DUALTIMER_Stop(DUALTIMERn); - - DUALTIMERn->TimerLoad = 0x0; - DUALTIMERn->TimerControl = 0x20; - DUALTIMERn->TimerBGLoad = 0x0; -} - -void DUALTIMER_Init(DUALTIMER_TypeDef* DUALTIMERn, DUALTIMER_InitTypDef* DUALTIMER_InitStruct) -{ - uint32_t tmp = 0; - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - assert_param(IS_DUALTIMER_TimerMode(DUALTIMER_InitStruct->TimerControl_Mode)); - assert_param(IS_DUALTIMER_TimerPre(DUALTIMER_InitStruct->TimerControl_Pre)); - assert_param(IS_DUALTIMER_TimerSize(DUALTIMER_InitStruct->TimerControl_Size)); - assert_param(IS_DUALTIMER_OneShot(DUALTIMER_InitStruct->TimerControl_OneShot)); - - DUALTIMER_Stop(DUALTIMERn); - - DUALTIMERn->TimerLoad = DUALTIMER_InitStruct->TimerLoad; - - tmp = DUALTIMERn->TimerControl; - tmp |= (DUALTIMER_InitStruct->TimerControl_Mode << DUALTIMER_TimerControl_TimerMode_Pos); - tmp |= (DUALTIMER_InitStruct->TimerControl_Pre << DUALTIMER_TimerControl_Pre_Pos); - tmp |= (DUALTIMER_InitStruct->TimerControl_Size << DUALTIMER_TimerControl_Size_Pos); - tmp |= (DUALTIMER_InitStruct->TimerControl_OneShot << DUALTIMER_TimerControl_OneShot_Pos); - //Reset values not used - tmp &= 0xEF; - - DUALTIMERn->TimerControl = tmp; -} - -void DUALTIMER_IntConfig(DUALTIMER_TypeDef* DUALTIMERn, FunctionalState state) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - if(state == ENABLE) - DUALTIMERn->TimerControl |= (DUALTIMER_TimerControl_IntEnable << DUALTIMER_TimerControl_IntEnable_Pos); - else - DUALTIMERn->TimerControl &= ~(DUALTIMER_TimerControl_IntEnable << DUALTIMER_TimerControl_IntEnable_Pos); -} - -void DUALTIMER_IntClear(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - DUALTIMERn->TimerIntClr = DUALTIMER_Int_Clear; -} - -ITStatus DUALTIMER_GetIntStatus(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - return (ITStatus)DUALTIMERn->TimerMIS; -} - -FlagStatus DUALTIMER_GetIntEnableStatus(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - return (FlagStatus)((DUALTIMERn->TimerControl >> DUALTIMER_TimerControl_IntEnable_Pos) & 0x1); -} - -void DUALTIMER_Start(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - DUALTIMERn->TimerControl |= (DUALTIMER_TimerControl_TimerEnable << DUALTIMER_TimerControl_TimerEnable_Pos); -} - -void DUALTIMER_Stop(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - DUALTIMERn->TimerControl &= ~(DUALTIMER_TimerControl_TimerEnable << DUALTIMER_TimerControl_TimerEnable_Pos); -} - -uint32_t DUALTIMER_GetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - return DUALTIMERn->TimerLoad; -} - -void DUALTIMER_SetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerLoad) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - DUALTIMERn->TimerLoad = TimerLoad; -} - -uint32_t DUALTIMER_GetTimerValue(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - return DUALTIMERn->TimerValue; -} - -uint32_t DUALTIMER_GetTimerControl(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - return DUALTIMERn->TimerControl; -} - -void DUALTIMER_SetTimerControl(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerControl) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - DUALTIMERn->TimerControl = TimerControl; -} - -uint32_t DUALTIMER_GetTimerRIS(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - return DUALTIMERn->TimerRIS; -} - -uint32_t DUALTIMER_GetTimerMIS(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - return DUALTIMERn->TimerMIS; -} - -uint32_t DUALTIMER_GetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - return DUALTIMERn->TimerBGLoad; -} - -void DUALTIMER_SetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerBGLoad) -{ - /* Check the parameters */ - assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn)); - - DUALTIMERn->TimerBGLoad = TimerBGLoad; -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_dualtimer.h b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_dualtimer.h deleted file mode 100644 index 014f3fd6358..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_dualtimer.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - ****************************************************************************** - * @file W7500x_stdPeriph_Driver/inc/W7500x_dualtimer.h - * @author IOP Team - * @version V1.0.0 - * @date 01-May-2015 - * @brief This file contains all the functions prototypes for the dualtimer - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __W7500X_DUALTIMER_H -#define __W7500X_DUALTIMER_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "W7500x.h" - -/**********************************************************************************************/ -/**********************************************************************************************/ -// This structure and define must be in W7500x.h -/**********************************************************************************************/ -/**********************************************************************************************/ - -typedef struct -{ - uint32_t TimerLoad; - uint32_t TimerControl_Mode; - uint32_t TimerControl_Pre; - uint32_t TimerControl_Size; - uint32_t TimerControl_OneShot; -}DUALTIMER_InitTypDef; - - -#define IS_DUALTIMER_TimerMode(MODE) (MODE <= 1) -#define IS_DUALTIMER_TimerPre(PREE) (PRE <= 2) -#define IS_DUALTIMER_TimerSize(SIZE) (SIZE <= 1) -#define IS_DUALTIMER_OneShot(ONESHOT) (ONESHOT <= 1) - - - - - - -#define DUALTIMER_Int_Clear 0x1ul - -#define DUALTIMER_Clock_Enable 0x1ul -#define DUALTIMER_Clock_Disable ~DUALTIMER_Clock_Enable - - -#define IS_DUALTIMER_ALL_CH(CH) ((CH == DUALTIMER0_0) || \ - (CH == DUALTIMER0_1) || \ - (CH == DUALTIMER1_0) || \ - (CH == DUALTIMER1_1)) - - - -void DUALTIMER_ClockEnable(DUALTIMER_TypeDef* DUALTIMERn); -void DUALTIMER_ClockDisable(DUALTIMER_TypeDef* DUALTIMERn); -void DUALTIMER_DeInit(DUALTIMER_TypeDef* DUALTIMERn); -void DUALTIMER_Init(DUALTIMER_TypeDef* DUALTIMERn, DUALTIMER_InitTypDef* DUALTIMER_InitStruct); -void DUALTIMER_IntConfig(DUALTIMER_TypeDef* DUALTIMERn, FunctionalState state); -void DUALTIMER_IntClear(DUALTIMER_TypeDef* DUALTIMERn); -ITStatus DUALTIMER_GetIntStatus(DUALTIMER_TypeDef* DUALTIMERn); -FlagStatus DUALTIMER_GetIntEnableStatus(DUALTIMER_TypeDef* DUALTIMERn); -void DUALTIMER_Start(DUALTIMER_TypeDef* DUALTIMERn); -void DUALTIMER_Stop(DUALTIMER_TypeDef* DUALTIMERn); -uint32_t DUALTIMER_GetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn); -void DUALTIMER_SetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerLoad); -uint32_t DUALTIMER_GetTimerValue(DUALTIMER_TypeDef* DUALTIMERn); -uint32_t DUALTIMER_GetTimerControl(DUALTIMER_TypeDef* DUALTIMERn); -void DUALTIMER_SetTimerControl(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerControl); -uint32_t DUALTIMER_GetTimerRIS(DUALTIMER_TypeDef* DUALTIMERn); -uint32_t DUALTIMER_GetTimerMIS(DUALTIMER_TypeDef* DUALTIMERn); -uint32_t DUALTIMER_GetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn); -void DUALTIMER_SetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerBGLoad); - - - -//======================= Interrupt handler ============================== -//void DUALTIMER0_Handler(); -//void DUALTIMER1_Handler(); - - -#ifdef __cplusplus - } -#endif - - -#endif //__W7500X_DUALTIMER_H diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_exti.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_exti.c deleted file mode 100644 index c3008f58034..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_exti.c +++ /dev/null @@ -1,158 +0,0 @@ -#include "W7500x.h" -#include "W7500x_exti.h" -#include "W7500x_gpio.h" - - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - uint32_t i, loop =16; - for(i=0; iPort[i] = 0x00; - EXTI_PB->Port[i] = 0x00; - EXTI_PC->Port[i] = 0x00; - } - for(i=0; i<5; i++) - { - EXTI_PD->Port[i] = 0x00; - } -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; - P_Port_Def *px_exti; - - assert_param(IS_PAD_TYPE(Px)); - - if (Px == PAD_PA) px_exti = EXTI_PA; - else if (Px == PAD_PB) px_exti = EXTI_PB; - else if (Px == PAD_PC) px_exti = EXTI_PC; - else - { - px_exti = (P_Port_Def*)EXTI_PD; - loop = 5; - } - - for(pinpos = 0x00; pinpos < loop; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - - currentpin = (EXTI_InitStruct->EXTI_Line) & pos; - if(currentpin == pos) - { - px_exti->Port[pinpos] |= EXTI_Px_INTEN_ENABLE; - - if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising) - px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE; - else - px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE; - } - } - -} - -void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity ) -{ - uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; - P_Port_Def *px_exti; - - assert_param(IS_PAD_TYPE(Px)); - - if (Px == PAD_PA) px_exti = EXTI_PA; - else if (Px == PAD_PB) px_exti = EXTI_PB; - else if (Px == PAD_PC) px_exti = EXTI_PC; - else - { - px_exti = (P_Port_Def*)EXTI_PD; - loop = 5; - } - - for(pinpos = 0x00; pinpos < loop; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - - currentpin = GPIO_Pin & pos; - if(currentpin == pos) - { - if(Polarity == EXTI_Trigger_Rising) - px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE; - else - px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE; - } - } - -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = 0xFF; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; -} - -uint16_t EXTI_Px_GetEXTEN(PAD_Type Px) -{ - uint32_t i, loop = 16; - uint16_t ret=0; - P_Port_Def *px_exti; - - assert_param(IS_PAD_TYPE(Px)); - - if (Px == PAD_PA) px_exti = EXTI_PA; - else if (Px == PAD_PB) px_exti = EXTI_PB; - else if (Px == PAD_PC) px_exti = EXTI_PC; - else - { - px_exti = (P_Port_Def*)EXTI_PD; - loop = 5; - } - - for(i = 0x00; i < loop; i++) - { - ret |= (((px_exti->Port[i]&0x2)>>1)<Port[i]&0x1)<DATA = 0x0000; - GPIOx->DATAOUT = 0x0000; - GPIOx->OUTENCLR = 0xFFFF; - GPIOx->INTENCLR = 0xFFFF; - GPIOx->INTTYPESET = 0x0000; - - /* DeInit GPIOx - * Pad Control Register - * Pad Extern interrupt Enable Register - * Pad Alternate Function Select Register - */ - if (GPIOx == GPIOA) - { - px_pcr = PA_PCR; - px_afsr = PA_AFSR; - } - else if (GPIOx == GPIOB) - { - px_pcr = PB_PCR; - px_afsr = PB_AFSR; - } - else if (GPIOx == GPIOC) - { - px_pcr = PC_PCR; - px_afsr = PC_AFSR; - } - else // if (GPIOx == GPIOD) - { - px_pcr = (P_Port_Def*)PD_PCR; - px_afsr = (P_Port_Def*)PD_AFSR; - loop = 5; - } - - for(i=0; iPort[i] = 0x60; - px_afsr->Port[i] = PAD_AF0; - - } -} - -void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; - P_Port_Def *px_pcr; - - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - if (GPIOx == GPIOA) px_pcr = PA_PCR; - else if (GPIOx == GPIOB) px_pcr = PB_PCR; - else if (GPIOx == GPIOC) px_pcr = PC_PCR; - else - { - px_pcr = (P_Port_Def*)PD_PCR; - loop = 5; - } - - for(pinpos = 0x00; pinpos < loop; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if(currentpin == pos) - { - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) - { - GPIOx->OUTENSET = pos; - } - else // GPIO_Mode_In - { - GPIOx->OUTENCLR = pos; - } - - // Configure pull-up pull-down bits - if(GPIO_InitStruct->GPIO_Pad & Px_PCR_PUPD_UP) - { - px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN); - px_pcr->Port[pinpos] |= Px_PCR_PUPD_UP; - } - else - { - px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN); - px_pcr->Port[pinpos] |= Px_PCR_PUPD_DOWN; - } - - // Configure Driving stregnth selections bit - if(GPIO_InitStruct->GPIO_Pad & Px_PCR_DS_HIGH) - { - px_pcr->Port[pinpos] |= Px_PCR_DS_HIGH; - } - else - { - px_pcr->Port[pinpos] &= ~(Px_PCR_DS_HIGH); - } - - // Configure Input buffer enable selection bit - if(GPIO_InitStruct->GPIO_Pad & Px_PCR_IE) - { - px_pcr->Port[pinpos] |= Px_PCR_IE; - } - else - { - px_pcr->Port[pinpos] &= ~(Px_PCR_IE); - } - - // Configure input type (CMOS input or Summit trigger input) select bit - if(GPIO_InitStruct->GPIO_Pad & Px_PCR_CS_SUMMIT) - { - px_pcr->Port[pinpos] |= Px_PCR_CS_SUMMIT; - } - else - { - px_pcr->Port[pinpos] &= ~(Px_PCR_CS_SUMMIT); - } - } - } -} - -void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Pad = (GPIOPad_TypeDef)(GPIO_SUMMIT|GPIO_IE|GPIO_PuPd_UP); -} - - -uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if((GPIOx->DATA & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -uint16_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - return ((uint16_t)GPIOx->DATA); -} - -uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - - - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if((GPIOx->DATAOUT & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} -uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALLPERIPH(GPIOx)); - return ((uint16_t)GPIOx->DATAOUT); -} - -void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if (GPIO_Pin < 256) - (GPIOx->LB_MASKED[(uint8_t) (GPIO_Pin)]) = 0xFFFF; - else - (GPIOx->UB_MASKED[(uint8_t) ((GPIO_Pin) >> 8)]) = 0xFFFF; -} - -void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if (GPIO_Pin < 256) - (GPIOx->LB_MASKED[(uint8_t) (GPIO_Pin)]) = 0x0; - else - (GPIOx->UB_MASKED[(uint8_t) (GPIO_Pin >> 8)]) = 0x0; -} - -void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - uint32_t temp_gpio_lb; - uint32_t temp_gpio_ub; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - temp_gpio_lb = (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]); - temp_gpio_ub = (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]); - - if (GPIO_Pin < 256) - { - if(BitVal) - (GPIOx->LB_MASKED[(uint8_t) (GPIO_Pin)]) = 0xFFFF; - else - (GPIOx->LB_MASKED[(uint8_t) (GPIO_Pin)]) = 0x0; - } - else - { - if(BitVal) - (GPIOx->UB_MASKED[(uint8_t) (GPIO_Pin)]) = 0xFFFF; - else - (GPIOx->UB_MASKED[(uint8_t) (GPIO_Pin)]) = 0x0; - } -} - -void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->DATAOUT = PortVal; -} - -void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF) -{ - int i; - uint16_t idx =0x1; - assert_param(IS_PAD_Type(Px)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - for(i=0;i<16;i++) - { - if(GPIO_Pin & (idx<Port[i] &= ~(0x03ul); - PA_AFSR->Port[i] = P_AF; - } - else if(Px == PAD_PB) - { - assert_param(IS_PB_NUM(i)); - PB_AFSR->Port[i] &= ~(0x03ul); - PB_AFSR->Port[i] = P_AF; - } - else if(Px == PAD_PC) - { - assert_param(IS_PC_NUM(i)); - PC_AFSR->Port[i] &= ~(0x03ul); - PC_AFSR->Port[i] = P_AF; - } - else - { - assert_param(IS_PD_NUM(i)); - PD_AFSR->Port[i] &= ~(0x03ul); - PD_AFSR->Port[i] = P_AF; - } - } - } -} - -void GPIO_OutEnClr(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->OUTENCLR = GPIO_Pin; -} - -void GPIO_OutEnSet(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->OUTENSET = GPIO_Pin; -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.h b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.h deleted file mode 100644 index 53efdb8c57e..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - ****************************************************************************** - * @file - * @author - * @version - * @date - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __W7500X_HAL_GPIO_H -#define __W7500X_HAL_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "W7500x.h" - -#define GPIO_Pin_0 (uint16_t)(0x01 << 0) // Pin 0 Selected -#define GPIO_Pin_1 (uint16_t)(0x01 << 1) // Pin 1 Selected -#define GPIO_Pin_2 (uint16_t)(0x01 << 2) // Pin 2 Selected -#define GPIO_Pin_3 (uint16_t)(0x01 << 3) // Pin 3 Selected -#define GPIO_Pin_4 (uint16_t)(0x01 << 4) // Pin 4 Selected -#define GPIO_Pin_5 (uint16_t)(0x01 << 5) // Pin 5 Selected -#define GPIO_Pin_6 (uint16_t)(0x01 << 6) // Pin 6 Selected -#define GPIO_Pin_7 (uint16_t)(0x01 << 7) // Pin 7 Selected -#define GPIO_Pin_8 (uint16_t)(0x01 << 8) // Pin 8 Selected -#define GPIO_Pin_9 (uint16_t)(0x01 << 9) // Pin 9 Selected -#define GPIO_Pin_10 (uint16_t)(0x01 << 10) // Pin 10 Selected -#define GPIO_Pin_11 (uint16_t)(0x01 << 11) // Pin 11 Selected -#define GPIO_Pin_12 (uint16_t)(0x01 << 12) // Pin 12 Selected -#define GPIO_Pin_13 (uint16_t)(0x01 << 13) // Pin 13 Selected -#define GPIO_Pin_14 (uint16_t)(0x01 << 14) // Pin 14 Selected -#define GPIO_Pin_15 (uint16_t)(0x01 << 15) // Pin 15 Selected -#define GPIO_Pin_All (uint16_t)(0xFFFF) // All pins Selected - - -#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || \ - (((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || \ - (((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || \ - (((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || \ - (((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || \ - (((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || \ - (((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || \ - (((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15) ) - - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) ) - -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02 /*!< GPIO Alternate function Mode */ -}GPIOMode_TypeDef; - -typedef enum -{ - GPIO_NO_PUPD = 0x0ul, - GPIO_PuPd_UP = Px_PCR_PUPD_UP, - GPIO_PuPd_DOWN = Px_PCR_PUPD_DOWN, - GPIO_PuPd_Default = 0x0ul, - GPIO_DS = Px_PCR_DS_HIGH, - GPIO_IE = Px_PCR_IE, - GPIO_SUMMIT = Px_PCR_CS_SUMMIT -}GPIOPad_TypeDef; - -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_UP) || ((PUPD) == GPIO_PuPd_DOWN)) - -typedef struct -{ - uint32_t GPIO_Pin; - GPIOMode_TypeDef GPIO_Mode; - GPIOPad_TypeDef GPIO_Pad; -}GPIO_InitTypeDef; - -typedef enum -{ - Falling = 0, - Rising = 1 -}GPIOPol_TypeDef; - -typedef enum -{ - Reset = 0, - Set = 1 -}GPIOSet_TypeDef; - -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; - - -#define IS_PAD_TYPE(Px) (((Px) == PAD_PA) || ((Px) == PAD_PB) || \ - ((Px) == PAD_PC) || ((Px) == PAD_PD)) - -#define IS_PA_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) -#define IS_PB_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) -#define IS_PC_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) -#define IS_PD_NUM(NUM) (((NUM)>=0) && ((NUM)< 5)) - -#define IS_PAD_AF(AF) (((AF) == PAD_AF0) || ((AF) == PAD_AF1) || \ - ((AF) == PAD_AF2) || ((AF) == PAD_AF3)) - - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION_ == Bit_RESET) || (ACTION) ==Bit_SET)) - -void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx); -void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void HAL_PAD_AFConfig(PAD_Type Px, uint16_t Pnum, PAD_AF_TypeDef P_AF); - -void GPIO_OutEnClr(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_OutEnSet(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - - -#ifdef __cplusplus -} -#endif - -#endif // __W7500X_HAL_GPIO_H diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_i2c.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_i2c.c deleted file mode 100644 index 5efe1ac9fc8..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_i2c.c +++ /dev/null @@ -1,288 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -/*include -------------------------------------*/ -#include "W7500x.h" -#include "W7500x_i2c.h" -#include "W7500x_gpio.h" - -GPIO_InitTypeDef GPIO_InitDef; - -uint32_t I2C_Init(I2C_ConfigStruct* conf) -{ - uint32_t scl_port_num; - uint32_t scl_pin_index; - uint32_t sda_port_num; - uint32_t sda_pin_index; - - scl_port_num = I2C_PORT(conf->scl); - scl_pin_index = I2C_PIN_INDEX(conf->scl); - - sda_port_num = I2C_PORT(conf->sda); - sda_pin_index = I2C_PIN_INDEX(conf->sda); - - //SCL setting - GPIO_InitDef.GPIO_Pin = scl_pin_index; - GPIO_InitDef.GPIO_Mode = GPIO_Mode_OUT; - - HAL_GPIO_Init((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), &GPIO_InitDef); - HAL_GPIO_SetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index); - - //SDA setting - GPIO_InitDef.GPIO_Pin = sda_pin_index; - GPIO_InitDef.GPIO_Mode = GPIO_Mode_IN; - - HAL_GPIO_Init((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), &GPIO_InitDef); - HAL_GPIO_ResetBits((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index); - - //Pin muxing - HAL_PAD_AFConfig((PAD_Type)scl_port_num, (uint16_t)scl_pin_index, PAD_AF1); - HAL_PAD_AFConfig((PAD_Type)sda_port_num, (uint16_t)sda_pin_index, PAD_AF1); - - return 0; -} - -void I2C_WriteBitSCL(I2C_ConfigStruct* conf, uint8_t data) -{ - uint32_t scl_port_num = I2C_PORT(conf->scl); - uint32_t scl_pin_index = I2C_PIN_INDEX(conf->scl); - - if(data == 1) - HAL_GPIO_SetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index); - else - HAL_GPIO_ResetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index); - -} - -void I2C_WriteBitSDA(I2C_ConfigStruct* conf, uint8_t data) -{ - uint32_t sda_port_num = I2C_PORT(conf->sda); - uint32_t sda_pin_index = I2C_PIN_INDEX(conf->sda); - - if(data == 1) - GPIO_OutEnClr((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index); - else - GPIO_OutEnSet((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index); - -} - -uint8_t I2C_ReadBitSDA(I2C_ConfigStruct* conf) -{ - uint32_t sda_port_num = I2C_PORT(conf->sda); - uint32_t sda_pin_index = I2C_PIN_INDEX(conf->sda); - - if(HAL_GPIO_ReadInputDataBit((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index)) - return 1; - - return 0; -} - -void I2C_Start(I2C_ConfigStruct* conf) -{ - I2C_WriteBitSCL(conf, 1); - I2C_WriteBitSDA(conf, 1); - - I2C_WriteBitSDA(conf, 0); - I2C_WriteBitSCL(conf, 0); -} - -void I2C_Stop(I2C_ConfigStruct* conf) -{ - I2C_WriteBitSCL(conf, 0); - I2C_WriteBitSDA(conf, 0); - - I2C_WriteBitSCL(conf, 1); - I2C_WriteBitSDA(conf, 1); -} - -uint8_t I2C_WriteByte(I2C_ConfigStruct* conf, uint8_t data) -{ - int i; - uint8_t ret; - - //Write byte - for(i=0; i<8; i++) - { - if((data << i) & 0x80) - I2C_WriteBitSDA(conf, 1); - else - I2C_WriteBitSDA(conf, 0); - - I2C_WriteBitSCL(conf, 1); - I2C_WriteBitSCL(conf, 0); - } - //Make clk for receiving ack - I2C_WriteBitSDA(conf, 1); - I2C_WriteBitSCL(conf, 1); - //Read Ack/Nack - ret = I2C_ReadBitSDA(conf); - - I2C_WriteBitSCL(conf, 0); - - return ret; -} - -void I2C_SendACK(I2C_ConfigStruct* conf) -{ - I2C_WriteBitSDA(conf, 0); - I2C_WriteBitSCL(conf, 1); - - I2C_WriteBitSCL(conf, 0); -} - -void I2C_SendNACK(I2C_ConfigStruct* conf) -{ - I2C_WriteBitSDA(conf, 1); - I2C_WriteBitSCL(conf, 1); - - I2C_WriteBitSCL(conf, 0); -} - -uint8_t I2C_ReadByte(I2C_ConfigStruct* conf) -{ - int i; - uint8_t ret = 0; - - I2C_WriteBitSDA(conf, 1); //out enable clear(GPIO is input) - - //Read byte - for(i=0; i<8; i++) - { - I2C_WriteBitSCL(conf, 1); - ret = (ret << 1) | (I2C_ReadBitSDA(conf)); - I2C_WriteBitSCL(conf, 0); - } - - return ret; -} - -int I2C_Write(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len) -{ - int i; - - I2C_Start(conf); - - //Write addr - if(I2C_WriteByte(conf, addr) != 0) - { - //printf("Received NACK at address phase!!\r\n"); - return -1; - } - - //Write data - for(i=0; i> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D) -#define I2C_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit - -uint32_t I2C_Init(I2C_ConfigStruct* conf); - -void I2C_WriteBitSDA(I2C_ConfigStruct* conf, uint8_t data); -void I2C_WriteBitSCL(I2C_ConfigStruct* conf, uint8_t data); -uint8_t I2C_ReadBitSDA(I2C_ConfigStruct* conf); - -void I2C_SendACK(I2C_ConfigStruct* conf); -void I2C_SendNACK(I2C_ConfigStruct* conf); - -uint8_t I2C_WriteByte(I2C_ConfigStruct* conf, uint8_t data); -uint8_t I2C_ReadByte(I2C_ConfigStruct* conf); - -void I2C_Start(I2C_ConfigStruct* conf); -void I2C_Stop(I2C_ConfigStruct* conf); - -int I2C_Write(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len); -int I2C_WriteRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len); -int I2C_Read(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len); -int I2C_ReadRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len); - - - #endif //__W7500X_I2C_H - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.c deleted file mode 100644 index aff33d39150..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.c +++ /dev/null @@ -1,906 +0,0 @@ -/** - ****************************************************************************** - * @file - * @author - * @version - * @date - * @brief This file contains all the functions prototypes for the UART - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Includes -------------------------------------------*/ -#include "W7500x.h" -#include "W7500x_pwm.h" - -void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn) -{ - if( PWM_CHn == PWM_CH0 ) - { - PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register - PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register - PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register - PWM_CH0->IER = 0; ///< Interrupt enable register - PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear | - PWM_CHn_ICR_OverflowInterruptClear | - PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register - PWM_CH0->PR = 0; ///< Prescale register - PWM_CH0->MR = 0; ///< Match register - PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register - PWM_CH0->UDMR = 0; ///< Up Dowm mode register - PWM_CH0->TCMR = 0; ///< Timer Counter mode register - PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register - PWM_CH0->CMR = 0; ///< Capture mode register - PWM_CH0->PDMR = 0; ///< Periodic Mode register - PWM_CH0->DZER = 0; ///< Dead Zone Enable register - PWM_CH0->DZCR = 0; ///< Dead Zone Counter register - } - else if( PWM_CHn == PWM_CH1 ) - { - PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register - PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register - PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register - PWM_CH1->IER = 0; ///< Interrupt enable register - PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear | - PWM_CHn_ICR_OverflowInterruptClear | - PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register - PWM_CH1->PR = 0; ///< Prescale register - PWM_CH1->MR = 0; ///< Match register - PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register - PWM_CH1->UDMR = 0; ///< Up Dowm mode register - PWM_CH1->TCMR = 0; ///< Timer Counter mode register - PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register - PWM_CH1->CMR = 0; ///< Capture mode register - PWM_CH1->PDMR = 0; ///< Periodic Mode register - PWM_CH1->DZER = 0; ///< Dead Zone Enable register - PWM_CH1->DZCR = 0; ///< Dead Zone Counter register - } - else if( PWM_CHn == PWM_CH2) - { - PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register - PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register - PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register - PWM_CH2->IER = 0; ///< Interrupt enable register - PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear | - PWM_CHn_ICR_OverflowInterruptClear | - PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register - PWM_CH2->PR = 0; ///< Prescale register - PWM_CH2->MR = 0; ///< Match register - PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register - PWM_CH2->UDMR = 0; ///< Up Dowm mode register - PWM_CH2->TCMR = 0; ///< Timer Counter mode register - PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register - PWM_CH2->CMR = 0; ///< Capture mode register - PWM_CH2->PDMR = 0; ///< Periodic Mode register - PWM_CH2->DZER = 0; ///< Dead Zone Enable register - PWM_CH2->DZCR = 0; ///< Dead Zone Counter register - } - else if( PWM_CHn == PWM_CH3 ) - { - PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register - PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register - PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register - PWM_CH3->IER = 0; ///< Interrupt enable register - PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear | - PWM_CHn_ICR_OverflowInterruptClear | - PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register - PWM_CH3->MR = 0; ///< Match register - PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register - PWM_CH3->UDMR = 0; ///< Up Dowm mode register - PWM_CH3->TCMR = 0; ///< Timer Counter mode register - PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register - PWM_CH3->CMR = 0; ///< Capture mode register - PWM_CH3->PDMR = 0; ///< Periodic Mode register - PWM_CH3->DZER = 0; ///< Dead Zone Enable register - PWM_CH3->DZCR = 0; ///< Dead Zone Counter register - } - else if( PWM_CHn == PWM_CH4 ) - { - PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register - PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register - PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register - PWM_CH4->IER = 0; ///< Interrupt enable register - PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear | - PWM_CHn_ICR_OverflowInterruptClear | - PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register - PWM_CH4->PR = 0; ///< Prescale register - PWM_CH4->MR = 0; ///< Match register - PWM_CH4->LR = 0xFFFF; ///< Limit register - PWM_CH4->UDMR = 0; ///< Up Dowm mode register - PWM_CH4->TCMR = 0; ///< Timer Counter mode register - PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register - PWM_CH4->CMR = 0; ///< Capture mode register - PWM_CH4->PDMR = 0; ///< Periodic Mode register - PWM_CH4->DZER = 0; ///< Dead Zone Enable register - PWM_CH4->DZCR = 0; ///< Dead Zone Counter register - } - else if( PWM_CHn == PWM_CH5 ) - { - PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register - PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register - PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register - PWM_CH5->IER = 0; ///< Interrupt enable register - PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear | - PWM_CHn_ICR_OverflowInterruptClear | - PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register - PWM_CH5->PR = 0; ///< Prescale register - PWM_CH5->MR = 0; ///< Match register - PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register - PWM_CH5->UDMR = 0; ///< Up Dowm mode register - PWM_CH5->TCMR = 0; ///< Timer Counter mode register - PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register - PWM_CH5->CMR = 0; ///< Capture mode register - PWM_CH5->PDMR = 0; ///< Periodic Mode register - PWM_CH5->DZER = 0; ///< Dead Zone Enable register - PWM_CH5->DZCR = 0; ///< Dead Zone Counter register - } - else if( PWM_CHn == PWM_CH6 ) - { - PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register - PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register - PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register - PWM_CH6->IER = 0; ///< Interrupt enable register - PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear | - PWM_CHn_ICR_OverflowInterruptClear | - PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register - PWM_CH6->PR = 0; ///< Prescale register - PWM_CH6->MR = 0; ///< Match register - PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register - PWM_CH6->UDMR = 0; ///< Up Dowm mode register - PWM_CH6->TCMR = 0; ///< Timer Counter mode register - PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register - PWM_CH6->CMR = 0; ///< Capture mode register - PWM_CH6->PDMR = 0; ///< Periodic Mode register - PWM_CH6->DZER = 0; ///< Dead Zone Enable register - PWM_CH6->DZCR = 0; ///< Dead Zone Counter register - } - else if( PWM_CHn == PWM_CH7 ) - { - PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register - PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register - PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register - PWM_CH7->IER = 0; ///< Interrupt enable register - PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear | - PWM_CHn_ICR_OverflowInterruptClear | - PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register - PWM_CH7->PR = 0; ///< Prescale register - PWM_CH7->MR = 0; ///< Match register - PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register - PWM_CH7->UDMR = 0; ///< Up Dowm mode register - PWM_CH7->TCMR = 0; ///< Timer Counter mode register - PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register - PWM_CH7->CMR = 0; ///< Capture mode register - PWM_CH7->PDMR = 0; ///< Periodic Mode register - PWM_CH7->DZER = 0; ///< Dead Zone Enable register - PWM_CH7->DZCR = 0; ///< Dead Zone Counter register - } -} - - -void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet -{ - /* Stop PWM_CHn */ - PWM_CHn_Stop(PWM_CHn); - /* Select Timer/Counter mode as Timer mode */ - PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; - /* Set Prescale register value */ - PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR; - /* Set Match register value */ - PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR; - /* Set Limit register value */ - PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR; - /* Select Up-down mode */ - PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR; - /* Select Periodic mode */ - PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR; -} - -void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR)); - assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR)); - assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR)); - assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR)); - assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR)); - assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR)); - - /* Stop PWM_CHn */ - PWM_CHn_Stop(PWM_CHn); - /* Select Timer/Counter mode as Timer mode */ - PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; - /* Set Prescale register value */ - PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR; - /* Set Match register value */ - PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR; - /* Set Limit register value */ - PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR; - /* Select Up-down mode */ - PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR; - /* Select Periodic mode */ - PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR; - /* Select Capture mode */ - PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR; - /* External input enable */ - PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable; -} - -void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - /* Stop PWM_CHn */ - PWM_CHn_Stop(PWM_CHn); - /* Select Timer/Counter mode as Timer mode */ - PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; - /* Set Match register value */ - PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR; - /* Set Limit register value */ - PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR; - /* Select Up-down mode */ - PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR; - /* Select Periodic mode */ - PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR; - /* Select Counter mode */ - PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR; - /* Enable external input */ - PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable; -} - -void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR)); - assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR)); - assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR)); - assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR)); - assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR)); - assert_param(IS_PWM_Deadznoe(PWM_CHn)); - - /* Stop PWM_CHn */ - PWM_CHn_Stop(PWM_CHn); - /* Select Timer/Counter mode as Timer mode */ - PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; - /* Set Prescale register value */ - PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR; - /* Set Match register value */ - PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR; - /* Set Limit register value */ - PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR; - /* Select Up-down mode */ - PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR; - /* Select Periodic mode */ - PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR; - /* Enable Dead Zone generation */ - PWM_CHn->DZER = PWM_CHn_DZER_Enable; - /* Set Dead Zone Counter */ - PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR; -} - -void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_Output(outputEnDisable)); - if( PWM_CHn->DZER ) - assert_param(IS_PWM_Deadznoe(PWM_CHn)); - - /* Stop PWM_CHn */ - PWM_CHn_Stop(PWM_CHn); - /*Config PWM output and External input */ - PWM_CHn->PEEER = outputEnDisable; -} - -void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) -{ - PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable); -} - -void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) -{ - PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable); -} - -void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - /* Stop PWM_CHn */ - PWM_CHn_Stop(PWM_CHn); - - if(state == ENABLE) - { - if(PWM_CHn == PWM_CH0) { - PWM->IER |= PWM_IER_IE0_Enable; - } - else if(PWM_CHn == PWM_CH1) { - PWM->IER |= PWM_IER_IE1_Enable; - } - else if(PWM_CHn == PWM_CH2) { - PWM->IER |= PWM_IER_IE2_Enable; - } - else if(PWM_CHn == PWM_CH3) { - PWM->IER |= PWM_IER_IE3_Enable; - } - else if(PWM_CHn == PWM_CH4) { - PWM->IER |= PWM_IER_IE4_Enable; - } - else if(PWM_CHn == PWM_CH5) { - PWM->IER |= PWM_IER_IE5_Enable; - } - else if(PWM_CHn == PWM_CH6) { - PWM->IER |= PWM_IER_IE6_Enable; - } - else if(PWM_CHn == PWM_CH7) { - PWM->IER |= PWM_IER_IE7_Enable; - } - } - else - { - if(PWM_CHn == PWM_CH0) { - PWM->IER &= PWM_IER_IE0_Disable; - } - else if(PWM_CHn == PWM_CH1) { - PWM->IER &= PWM_IER_IE1_Disable; - } - else if(PWM_CHn == PWM_CH2) { - PWM->IER &= PWM_IER_IE2_Disable; - } - else if(PWM_CHn == PWM_CH3) { - PWM->IER &= PWM_IER_IE3_Disable; - } - else if(PWM_CHn == PWM_CH4) { - PWM->IER &= PWM_IER_IE4_Disable; - } - else if(PWM_CHn == PWM_CH5) { - PWM->IER &= PWM_IER_IE5_Disable; - } - else if(PWM_CHn == PWM_CH6) { - PWM->IER &= PWM_IER_IE6_Disable; - } - else if(PWM_CHn == PWM_CH7) { - PWM->IER &= PWM_IER_IE7_Disable; - } - } -} - -FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) -{ - FlagStatus ret_val = RESET; - - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - if(PWM_CHn == PWM_CH0) { - ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0); - } - else if(PWM_CHn == PWM_CH1) { - ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1); - } - else if(PWM_CHn == PWM_CH2) { - ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2); - } - else if(PWM_CHn == PWM_CH3) { - ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3); - } - else if(PWM_CHn == PWM_CH4) { - ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4); - } - else if(PWM_CHn == PWM_CH5) { - ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5); - } - else if(PWM_CHn == PWM_CH6) { - ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6); - } - else if(PWM_CHn == PWM_CH7) { - ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7); - } - - return ret_val; -} - -void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - - assert_param(IS_PWM_CHn_IER(PWM_CHn_IER)); - - /* Stop PWM_CHn */ - PWM_CHn_Stop(PWM_CHn); - - if(state == ENABLE) - PWM_CHn->IER |= PWM_CHn_IER; - else - PWM_CHn->IER &= ~PWM_CHn_IER; -} - -uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->IER; -} - -uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->IR; -} - -void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR) -{ - /* Check the parameters */ - - PWM_CHn->ICR = PWM_CHn_ICR; -} - -void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - /* Set Start Stop register */ - if(PWM_CHn == PWM_CH0) { - PWM->SSR |= PWM_SSR_SS0_Start; - } - else if(PWM_CHn == PWM_CH1) { - PWM->SSR |= PWM_SSR_SS1_Start; - } - else if(PWM_CHn == PWM_CH2) { - PWM->SSR |= PWM_SSR_SS2_Start; - } - else if(PWM_CHn == PWM_CH3) { - PWM->SSR |= PWM_SSR_SS3_Start; - } - else if(PWM_CHn == PWM_CH4) { - PWM->SSR |= PWM_SSR_SS4_Start; - } - else if(PWM_CHn == PWM_CH5) { - PWM->SSR |= PWM_SSR_SS5_Start; - } - else if(PWM_CHn == PWM_CH6) { - PWM->SSR |= PWM_SSR_SS6_Start; - } - else if(PWM_CHn == PWM_CH7) { - PWM->SSR |= PWM_SSR_SS7_Start; - } -} - -void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete -{ - /* Set Start Stop register */ - PWM->SSR |= ssr_bit_flag; -} - -void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Reset Start Stop register */ - if(PWM_CHn == PWM_CH0) { - PWM->SSR &= PWM_SSR_SS0_Stop; - } - else if(PWM_CHn == PWM_CH1) { - PWM->SSR &= PWM_SSR_SS1_Stop; - } - else if(PWM_CHn == PWM_CH2) { - PWM->SSR &= PWM_SSR_SS2_Stop; - } - else if(PWM_CHn == PWM_CH3) { - PWM->SSR &= PWM_SSR_SS3_Stop; - } - else if(PWM_CHn == PWM_CH4) { - PWM->SSR &= PWM_SSR_SS4_Stop; - } - else if(PWM_CHn == PWM_CH5) { - PWM->SSR &= PWM_SSR_SS5_Stop; - } - else if(PWM_CHn == PWM_CH6) { - PWM->SSR &= PWM_SSR_SS6_Stop; - } - else if(PWM_CHn == PWM_CH7) { - PWM->SSR &= PWM_SSR_SS7_Stop; - } -} - -void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete -{ - /* Reset Start Stop register */ - PWM->SSR &= ~ssr_bit_flag; -} - -void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn) -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - /* Set Pause register */ - if(PWM_CHn == PWM_CH0) { - PWM->PSR |= PWM_PSR_PS0_Pause; - } - else if(PWM_CHn == PWM_CH1) { - PWM->PSR |= PWM_PSR_PS1_Pause; - } - else if(PWM_CHn == PWM_CH2) { - PWM->PSR |= PWM_PSR_PS2_Pause; - } - else if(PWM_CHn == PWM_CH3) { - PWM->PSR |= PWM_PSR_PS3_Pause; - } - else if(PWM_CHn == PWM_CH4) { - PWM->PSR |= PWM_PSR_PS4_Pause; - } - else if(PWM_CHn == PWM_CH5) { - PWM->PSR |= PWM_PSR_PS5_Pause; - } - else if(PWM_CHn == PWM_CH6) { - PWM->PSR |= PWM_PSR_PS6_Pause; - } - else if(PWM_CHn == PWM_CH7) { - PWM->PSR |= PWM_PSR_PS7_Pause; - } -} - -void PWM_Multi_Pause(uint32_t psr_bit_flag) -{ - PWM->PSR |= psr_bit_flag; -} - -void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn) -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - /* Reset Pause register */ - if(PWM_CHn == PWM_CH0) { - PWM->PSR &= PWM_PSR_PS0_Restart; - } - else if(PWM_CHn == PWM_CH1) { - PWM->PSR &= PWM_PSR_PS1_Restart; - } - else if(PWM_CHn == PWM_CH2) { - PWM->PSR &= PWM_PSR_PS2_Restart; - } - else if(PWM_CHn == PWM_CH3) { - PWM->PSR &= PWM_PSR_PS3_Restart; - } - else if(PWM_CHn == PWM_CH4) { - PWM->PSR &= PWM_PSR_PS4_Restart; - } - else if(PWM_CHn == PWM_CH5) { - PWM->PSR &= PWM_PSR_PS5_Restart; - } - else if(PWM_CHn == PWM_CH6) { - PWM->PSR &= PWM_PSR_PS6_Restart; - } - else if(PWM_CHn == PWM_CH7) { - PWM->PSR &= PWM_PSR_PS7_Restart; - } -} - -void PWM_Multi_Restart(uint32_t psr_bit_flag) -{ - PWM->PSR &= ~psr_bit_flag; -} - - -uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->TCR; -} - -uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->PCR; -} - -uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->PR; -} - -void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_PR_FILTER(PR)); - - PWM_CHn->PR = PR; -} - -uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->MR; -} - -void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - PWM_CHn->MR = MR; -} - -uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->LR; -} - -void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - PWM_CHn->LR = LR; -} - -uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->UDMR; -} - -void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_CHn_UDMR(UDMR)); - - PWM_CHn->UDMR = UDMR; -} - -uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->TCMR; -} - -void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_CHn_TCMR(TCMR)); - - PWM_CHn->TCMR = TCMR; -} - -uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->PEEER; -} - -void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_CHn_PEEER(PEEER)); - - PWM_CHn->PEEER = PEEER; -} - -uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->CMR; -} - -void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_CHn_CMR(CMR)); - - PWM_CHn->CMR = CMR; -} - -uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn) -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->CR; -} - -uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->PDMR; -} - -void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_CHn_PDMR(PDMR)); - - PWM_CHn->PDMR = PDMR; -} - -uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->DZER; -} - -void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_CHn_DZER(DZER)); - - PWM_CHn->DZER = DZER; -} - -uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - - return PWM_CHn->DZCR; -} - -void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete -{ - /* Check the parameters */ - assert_param(IS_PWM_ALL_CH(PWM_CHn)); - assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR)); - - PWM_CHn->DZCR = DZCR; -} - -void PWM_CH0_ClearMatchInt(void) -{ - PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear); -} - -void PWM_CH0_ClearOverflowInt(void) -{ - PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear); -} - -void PWM_CH0_ClearCaptureInt(void) -{ - PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear); -} - -void PWM_CH1_ClearMatchInt(void) -{ - PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear); -} - -void PWM_CH1_ClearOverflowInt(void) -{ - PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear); -} - -void PWM_CH1_ClearCaptureInt(void) -{ - PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear); -} - -void PWM_CH2_ClearMatchInt(void) -{ - PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear); -} - -void PWM_CH2_ClearOverflowInt(void) -{ - PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear); -} - -void PWM_CH2_ClearCaptureInt(void) -{ - PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear); -} - -void PWM_CH3_ClearMatchInt(void) -{ - PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear); -} - -void PWM_CH3_ClearOverflowInt(void) -{ - PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear); -} - -void PWM_CH3_ClearCaptureInt(void) -{ - PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear); -} - -void PWM_CH4_ClearMatchInt(void) -{ - PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear); -} - -void PWM_CH4_ClearOverflowInt(void) -{ - PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear); -} - -void PWM_CH4_ClearCaptureInt(void) -{ - PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear); -} - -void PWM_CH5_ClearMatchInt(void) -{ - PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear); -} - -void PWM_CH5_ClearOverflowInt(void) -{ - PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear); -} - -void PWM_CH5_ClearCaptureInt(void) -{ - PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear); -} - -void PWM_CH6_ClearMatchInt(void) -{ - PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear); -} - -void PWM_CH6_ClearOverflowInt(void) -{ - PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear); -} - -void PWM_CH6_ClearCaptureInt(void) -{ - PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear); -} - -void PWM_CH7_ClearMatchInt(void) -{ - PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear); -} - -void PWM_CH7_ClearOverflowInt(void) -{ - PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear); -} - -void PWM_CH7_ClearCaptureInt(void) -{ - PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear); -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h deleted file mode 100644 index d3d44c376cc..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - ****************************************************************************** - * @file - * @author - * @version - * @date - * @brief This file contains all the functions prototypes for the UART - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __W7500X_PWM_H -#define __W7500X_PWM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "W7500x.h" - -/**********************************************************************************************/ -/**********************************************************************************************/ -// This structure and define must be in W7500x.h -/**********************************************************************************************/ -/**********************************************************************************************/ - -typedef struct -{ - uint32_t PWM_CHn_PEEER; -}PWM_CtrlPWMOutputTypeDef; - -typedef struct -{ - uint32_t PWM_CHn_PR; - uint32_t PWM_CHn_MR; - uint32_t PWM_CHn_LR; - uint32_t PWM_CHn_UDMR; - uint32_t PWM_CHn_PDMR; - uint32_t PWM_CHn_DZCR; -}PWM_DeadzoneModeInitTypDef; - -#define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \ - (CHn == PWM_CH1) || \ - (CHn == PWM_CH2) || \ - (CHn == PWM_CH3) || \ - (CHn == PWM_CH4) || \ - (CHn == PWM_CH5) || \ - (CHn == PWM_CH6) || \ - (CHn == PWM_CH7)) - -#define PWM_IER_IE0_Enable (0x1ul << 0) -#define PWM_IER_IE1_Enable (0x1ul << 1) -#define PWM_IER_IE2_Enable (0x1ul << 2) -#define PWM_IER_IE3_Enable (0x1ul << 3) -#define PWM_IER_IE4_Enable (0x1ul << 4) -#define PWM_IER_IE5_Enable (0x1ul << 5) -#define PWM_IER_IE6_Enable (0x1ul << 6) -#define PWM_IER_IE7_Enable (0x1ul << 7) - -#define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable -#define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable -#define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable -#define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable -#define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable -#define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable -#define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable -#define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable - -#define PWM_SSR_SS0_Start (0x1ul << 0) -#define PWM_SSR_SS1_Start (0x1ul << 1) -#define PWM_SSR_SS2_Start (0x1ul << 2) -#define PWM_SSR_SS3_Start (0x1ul << 3) -#define PWM_SSR_SS4_Start (0x1ul << 4) -#define PWM_SSR_SS5_Start (0x1ul << 5) -#define PWM_SSR_SS6_Start (0x1ul << 6) -#define PWM_SSR_SS7_Start (0x1ul << 7) - -#define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start -#define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start -#define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start -#define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start -#define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start -#define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start -#define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start -#define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start - -#define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF) - -#define PWM_PSR_PS0_Pause (0x1ul << 0) -#define PWM_PSR_PS1_Pause (0x1ul << 1) -#define PWM_PSR_PS2_Pause (0x1ul << 2) -#define PWM_PSR_PS3_Pause (0x1ul << 3) -#define PWM_PSR_PS4_Pause (0x1ul << 4) -#define PWM_PSR_PS5_Pause (0x1ul << 5) -#define PWM_PSR_PS6_Pause (0x1ul << 6) -#define PWM_PSR_PS7_Pause (0x1ul << 7) - -#define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause -#define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause -#define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause -#define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause -#define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause -#define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause -#define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause -#define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause - -#define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF) - -#define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable -#define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable -#define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable -#define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7) - -#define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask -#define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask -#define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask - -#define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0) -#define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1) -#define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2) -#define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7 - -/* -#define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \ - ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \ - ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \ - ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \ - ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \ - ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \ - ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \ - ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7))) -*/ - - -#define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F) - - -#define PWM_CHn_UDMR_UpCount (0x0ul) -#define PWM_CHn_UDMR_DownCount (0x1ul) -#define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \ - (MODE == PWM_CHn_UDMR_DownCount)) - -#define PWM_CHn_TCMR_TimerMode (0x0ul) -#define PWM_CHn_TCMR_RisingCounterMode (0x1ul) -#define PWM_CHn_TCMR_FallingCounterMode (0x2ul) -#define PWM_CHn_TCMR_BothCounterMode (0x3ul) -#define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \ - (MODE == PWM_CHn_TCMR_FallingCounterMode) || \ - (MODE == PWM_CHn_TCMR_BothCounterMode)) - -#define PWM_CHn_PEEER_Disable (0x0ul) -#define PWM_CHn_PEEER_ExtEnable (0x1ul) -#define PWM_CHn_PEEER_PWMEnable (0x2ul) -#define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \ - (ENABLE == PWM_CHn_PEEER_ExtEnable) || \ - (ENABLE == PWM_CHn_PEEER_PWMEnable)) - -#define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \ - (ENABLE == PWM_CHn_PEEER_PWMEnable)) - -#define PWM_CHn_CMR_RisingEdge 0x0ul -#define PWM_CHn_CMR_FallingEdge 0x1ul -#define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \ - (MODE == PWM_CHn_CMR_FallingEdge)) - -#define PWM_CHn_PDMR_Oneshot (0x0ul) -#define PWM_CHn_PDMR_Periodic (0x1ul) -#define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \ - (MODE == PWM_CHn_PDMR_Oneshot)) - -#define PWM_CHn_DZER_Enable (0x1ul) -#define PWM_CHn_DZER_Disable (0x0ul) -#define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \ - (ENABLE == PWM_CHn_DZER_Disable)) - -#define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \ - ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \ - ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \ - ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \ - ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \ - ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \ - ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \ - ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable))) - -#define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF) - - - - - - -void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn); -void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct); -void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct); -void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct); -void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct); -void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ); -void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ; -void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ; -void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state); -FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state); -void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn); -void PWM_Multi_Start(uint32_t ssr_bit_flag); -void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn); -void PWM_Multi_Stop(uint32_t ssr_bit_flag); -void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn); -void PWM_Multi_Pause(uint32_t psr_bit_flag); -void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn); -void PWM_Multi_Restart(uint32_t psr_bit_flag); -uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn); -uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR); -uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn); -uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn); -uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR); -uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR); -uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR); -uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR); -uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR); -uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER); -uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR); -uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn); -uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR); -void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER); -uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn); -void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR); -void PWM_CH0_ClearMatchInt(void); -void PWM_CH0_ClearOverflowInt(void); -void PWM_CH0_ClearCaptureInt(void); -void PWM_CH1_ClearMatchInt(void); -void PWM_CH1_ClearOverflowInt(void); -void PWM_CH1_ClearCaptureInt(void); -void PWM_CH2_ClearMatchInt(void); -void PWM_CH2_ClearOverflowInt(void); -void PWM_CH2_ClearCaptureInt(void); -void PWM_CH3_ClearMatchInt(void); -void PWM_CH3_ClearOverflowInt(void); -void PWM_CH3_ClearCaptureInt(void); -void PWM_CH4_ClearMatchInt(void); -void PWM_CH4_ClearOverflowInt(void); -void PWM_CH4_ClearCaptureInt(void); -void PWM_CH5_ClearMatchInt(void); -void PWM_CH5_ClearOverflowInt(void); -void PWM_CH5_ClearCaptureInt(void); -void PWM_CH6_ClearMatchInt(void); -void PWM_CH6_ClearOverflowInt(void); -void PWM_CH6_ClearCaptureInt(void); -void PWM_CH7_ClearMatchInt(void); -void PWM_CH7_ClearOverflowInt(void); -void PWM_CH7_ClearCaptureInt(void); - - -void PWM0_Handler(void); -void PWM1_Handler(void); -void PWM2_Handler(void); -void PWM3_Handler(void); -void PWM4_Handler(void); -void PWM5_Handler(void); -void PWM6_Handler(void); -void PWM7_Handler(void); - - - - -//Temporary macro======= -#define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL))) -//====================== - - -#ifdef __cplusplus -} -#endif - - -#endif //__W7500X_PWM_H - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c deleted file mode 100644 index e7436ef509a..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c +++ /dev/null @@ -1,647 +0,0 @@ -/******************************************************************************************************************************************************* - * Copyright �� 2016 - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), - * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*********************************************************************************************************************************************************/ -/** - ****************************************************************************** - * @file W7500x_stdPeriph_Driver/src/W7500x_uart.c - * @author IOP Team - * @version v1.0.0 - * @date 01-May-2015 - * @brief This file contains all the functions prototypes for the uart - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "W7500x_uart.h" - -/** @addtogroup W7500x_Periph_Driver - * @{ - */ - -/** @defgroup UART - * @brief UART driver modules - * @{ - */ - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup UART_Private_Functions - * @{ - */ - -/** - * @brief Fills each UART_InitStruct member with its default value. - * @param UART_StructInit: pointer to a UART_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void UART_StructInit(UART_InitTypeDef* UART_InitStruct) -{ - /* UART_InitStruct members default value */ - UART_InitStruct->UART_BaudRate = 115200; - UART_InitStruct->UART_WordLength = UART_WordLength_8b ; - UART_InitStruct->UART_StopBits = UART_StopBits_1; - UART_InitStruct->UART_Parity = UART_Parity_No ; - UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx; - UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ; -} - -/* Function check */ -/* This function is checking now. Update or remove maybe. */ -//Why be???? -void UART_DeInit(UART_TypeDef *UARTx) -{ - -} - -/** - * @brief Initializes the UART peripheral according to the specified - * parameters in the UART_InitStruct . - * @param UARTx: where x can be 1, 2 or 3 - * @param UART_InitStruct: pointer to a UART_InitTypeDef structure that contains - * the configuration information for the specified UART peripheral. - * @retval None - */ - -uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct) -{ - - float baud_divisor; - uint32_t tmpreg=0x00, uartclock=0x00; - uint32_t integer_baud = 0x00, fractional_baud = 0x00; - - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength)); - assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); - assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); - assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); - - /* Write to UART CR */ - UARTx->CR &= ~(UART_CR_UARTEN); - - /* Set baudrate */ - /* CRG_UARTCLK_SSR_RCLK: Set UART Clock using internal Oscilator ( 8MHz ) */ - /* CRG_UARTCLK_SSR_OCLK: Set UART Clock using external Oscilator */ - CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz ) - //CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK; // Set UART Clock using external Oscilator - - /* Set uartclock */ - uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR); - - /*----------------------------- UARTx IBRD and FBRD Configuration ------------------------------*/ - baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate)); - integer_baud = (uint32_t)baud_divisor; - fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5); - - UARTx->IBRD = integer_baud; - UARTx->FBRD = fractional_baud; - - - tmpreg = UARTx->LCR_H; - tmpreg &= ~(0x00EE); - tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity); - UARTx->LCR_H = tmpreg; - - tmpreg = UARTx->CR; - tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN); - tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl); - UARTx->CR = tmpreg; - - /* Debug */ - /* UARTx->LCR_H |=0x10; */ - /* UARTx->IFLS | = 0x00; */ - - UARTx->CR |= UART_CR_UARTEN; - - return 0; -} - -/** - * @brief UART_FIFO_Enable - * @param case rx_fifo_level=0: 1/8 full, case rx_fifo_level=1: 1/4 full, case rx_fifo_level=2: 1/2 full, - * case rx_fifo_level=3: 3/4 full, case rx_fifo_level=4: 7/8 full - * @param case tx_fifo_level=0: 1/8 full, case tx_fifo_level=1: 1/4 full, case tx_fifo_level=2: 1/2 full, - * case tx_fifo_level=3: 3/4 full, case tx_fifo_level=4: 7/8 full - * @retval None - */ - -void UART_FIFO_Enable(UART_TypeDef *UARTx, uint16_t rx_fifo_level, uint16_t tx_fifo_level) -{ - UARTx->LCR_H |= UART_LCR_H_FEN; - UARTx->IFLS = (UART_IFLS_RXIFLSEL(rx_fifo_level) | UART_IFLS_TXIFLSEL(tx_fifo_level)); -} - -/** - * @brief UART_FIFO_Disable - * @param UARTx: Define structure at "W7500x.h" - * @retval None - */ -void UART_FIFO_Disable(UART_TypeDef *UARTx) -{ - UARTx->LCR_H &= ~(UART_LCR_H_FEN); -} - -/** - * @brief UART_SendData - * @param UARTx: Define structure at "W7500x.h" - * @param Data: Unsigned short value - * @retval None - */ -void UART_SendData(UART_TypeDef* UARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - UARTx->DR = Data; -} - -/** - * @brief UART_ReceiveData - * @param UARTx: Define structure at "W7500x.h" - * @retval None - */ -uint16_t UART_ReceiveData(UART_TypeDef* UARTx) -{ - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - return (uint16_t)(UARTx->DR); -} - -/** - * @brief UART_SendBreak - * @param UARTx: Define structure at "W7500x.h" - * @retval None - */ -void UART_SendBreak(UART_TypeDef* UARTx) -{ - assert_param(IS_UART_01_PERIPH(UARTx)); - - UARTx->LCR_H |= UART_LCR_H_BRK; -} - -/** - * @brief UART_GetRecvStatus - * @param UARTx: Define structure at "W7500x.h" - * @param UART_RECV_STATUS - * @retval bitstatus - */ -FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS)); - - if( (UARTx->STATUS.RSR & UART_RECV_STATUS) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief UART_ClearRecvStatus - * @param UARTx: Define structure at "W7500x.h" - * @param UART_RECV_STATUS - * @retval None - */ -void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) -{ - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS)); - - /* Set STATUS.ECR*/ - UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS; -} - -/** - * @brief UART_GetFlagStatus - * @param UARTx: Define structure at "W7500x.h" - * @param UART_FLAG - * @retval bitstatus - */ -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - assert_param(IS_UART_FLAG(UART_FLAG)); - - if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET) - { - /* bitstatus setting to SET*/ - bitstatus = SET; - } - else - { - /*bitstatus setting to RESET*/ - bitstatus = RESET; - } - - return bitstatus; - -} - -/* Function check */ -/* This function is checking now. Update or remove maybe. */ -//Why be? - -void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG) -{ - -} - - -/** - * @brief UART_ITConfig - * @param UARTx: Define structure at "W7500x.h" - * @param UART_IT - * @param NewState - * @retval None - */ -void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - assert_param(IS_UART_IT_FLAG(UART_IT)); - - if ( NewState != DISABLE ) - { - /*Set the IMSC*/ - UARTx->IMSC |= UART_IT; - } - else - { - /*Set the ICR*/ - UARTx->ICR |= UART_IT; - } -} - -/** - * @brief UART_GetITStatus - * @param UARTx: Define structure at "W7500x.h" - * @param UART_IT - * @param bitstatus - * @retval None - */ -ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - assert_param(IS_UART_IT_FLAG(UART_IT)); - - if ((UARTx->MIS & UART_IT) != (uint16_t)RESET) - { - /*Set bitstatus = SET */ - bitstatus = SET; - } - else - { - /*Set bitstatus = RESET */ - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief UART_ITPendingBit - * @param UARTx: Define structure at "W7500x.h" - * @param UART_IT - * @retval None - */ -void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT) -{ - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - assert_param(IS_UART_IT_FLAG(UART_IT)); - - /* Set ICR */ - UARTx->ICR |= UART_IT; -} - -/** - * @brief UART_DMA_Config - * @param UARTx: Define structure at "W7500x.h" - * @param UART_DMA_CONTROL - * @retval None - */ -void UART_DMA_Config(UART_TypeDef* UARTx, uint16_t UART_DMA_CONTROL) -{ - /* Check the parameters */ - assert_param(IS_UART_01_PERIPH(UARTx)); - assert_param(IS_UART_DMA_CONTROL(UART_DMA_CONTROL)); - - /*Set DMACR */ - UARTx->DMACR |= UART_DMA_CONTROL; -} - -/* Function check */ -/* This function is checking now. Update or remove maybe. */ -//Why be? -void S_UART_DeInit() -{ - -} - -/** - * @brief S_UART_Init - * @param baud - * @retval None - */ -uint32_t S_UART_Init(uint32_t baud) -{ - uint32_t tmpreg=0x00; - - S_UART_SetBaud(baud); - - /* Set temp register for UART2 CTRL */ - tmpreg = UART2->CTRL; - tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); - tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); - - /* Write to UART2 CTRL */ - UART2->CTRL = tmpreg; - - return 0; -} - -/** - * @brief S_UART_SetBaud - * @param baud - * @retval None - */ -void S_UART_SetBaud(uint32_t baud) -{ - uint32_t uartclock = 0x00, integer_baud = 0x00; - - /* Check the parameters */ - assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode)); - - if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK) - { - /* Set uartclock: INTERN_XTAL */ - uartclock = INTERN_XTAL; - } - else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK) - { - /* Set uartclock: EXTERN_XTAL */ - uartclock = EXTERN_XTAL; - } - else - { - /* Set uartclock: GetSystemClock */ - uartclock = GetSystemClock(); - } - - /* Set (Calculate) integer_baud */ - integer_baud = (uint32_t)(uartclock / baud); - /* Write UART2 BAUDDIV */ - UART2->BAUDDIV = integer_baud; -} - - -/** - * @brief S_UART_SendData - * @param Data - * @retval None - */ -void S_UART_SendData(uint16_t Data) -{ - while(UART2->STATE & S_UART_STATE_TX_BUF_FULL); - /* Write UART2 DATA */ - UART2->DATA = Data; -} - - -/** - * @brief S_UART_ReceiveData - * @retval UART2 DATA - */ -uint16_t S_UART_ReceiveData() -{ - return (uint16_t)(UART2->DATA); -} - - -/** - * @brief S_UART_GetFlagStatus - * @param UART_STATE - * @retval bitstatus - */ -FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_STATE) -{ - FlagStatus bitstatus = RESET; - - assert_param(IS_S_UART_STATE(S_UART_STATE)); - - if ((UART2->STATE & S_UART_STATE) != (FlagStatus)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - - -/** - * @brief S_UART_SetCTRL - * @param S_UART_CTRL - * @param NewState - * @retval None - */ -void S_UART_SetCTRL(uint16_t S_UART_CTRL, FunctionalState NewState) -{ - if ( NewState != DISABLE ) - { - UART2->CTRL |= S_UART_CTRL; - } - else - { - UART2->CTRL &= ~(S_UART_CTRL); - } -} - - -/** - * @brief S_UART_ITConfig - * @param S_UART_CTRL - * @param NewState - * @retval None - */ -void S_UART_ITConfig(uint16_t S_UART_CTRL, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_S_UART_CTRL_FLAG(S_UART_CTRL)); - - if ( NewState != DISABLE ) - { - /* Set UART2 CTRL: S_UART_CTRL */ - UART2->CTRL |= S_UART_CTRL; - } - else - { - /*Set UART2 CTRL: ~S_UART_CTRL */ - UART2->CTRL &= ~(S_UART_CTRL); - } -} - - -/** - * @brief S_UART_GetTStatus - * @param S_UART_INTSTATUS - * @retval bitstatus - */ -ITStatus S_UART_GetITStatus(uint16_t S_UART_INTSTATUS) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS)); - - if ((UART2->INT.STATUS & (S_UART_INTSTATUS)) != (uint16_t) RESET) - { - /* Set bitstatus: SET */ - bitstatus = SET; - } - else - { - /* Set bitstatus: RESET */ - bitstatus = RESET; - } - - return bitstatus; -} - - -/** - * @brief S_UART_ClearITPendingBit - * @param S_UART_INTSTATUS - * @retval None - */ -void S_UART_ClearITPendingBit(uint16_t S_UART_INTSTATUS) -{ - /* Check the parameters */ - assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS)); - /* Write UART2 INT.CLEAR: S_UART_INSTATUS */ - UART2->INT.CLEAR |= (S_UART_INTSTATUS); -} - - - -/**************************************************/ -// It will be moved to application board's driver */ -/**************************************************/ - - -uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch) -{ - UART_SendData(UARTx,ch); - - while(UARTx->FR & UART_FR_BUSY); - - return (ch); -} - - - -void UartPuts(UART_TypeDef* UARTx, uint8_t *str) -{ - uint8_t ch; - - do{ - ch = *str; - if(ch != (uint8_t)0x0) - { - UartPutc(UARTx, ch); - } - *str++; - }while(ch != 0); -} - - -uint8_t UartGetc(UART_TypeDef* UARTx) -{ - while(UARTx->FR & UART_FR_RXFE); - - return (UARTx->DR & 0xFF); -} - - -uint8_t S_UartPutc(uint8_t ch) -{ - S_UART_SendData(ch); - - return (ch); -} - - - -void S_UartPuts(uint8_t *str) -{ - uint8_t ch; - - do{ - ch = *str; - if(ch != (uint8_t)0x0) - { - S_UART_SendData(ch); - } - *str++; - }while(ch != 0); -} - - -uint8_t S_UartGetc() -{ - while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 ); - return (uint8_t)S_UART_ReceiveData(); -} - - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h deleted file mode 100644 index e85d3d73ca4..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h +++ /dev/null @@ -1,362 +0,0 @@ -/******************************************************************************************************************************************************* - * Copyright �� 2016 - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), - * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*********************************************************************************************************************************************************/ -/** - ****************************************************************************** - * @file W7500x_stdPeriph_Driver/inc/W7500x_uart.h - * @author IOP Team - * @version V1.0.0 - * @date 01-May-2015 - * @brief This file contains all the functions prototypes for the UART - * firmware library. - ****************************************************************************** - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __W7500X_UART_H -#define __W7500X_UART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "W7500x.h" - - -/** @addtogroup W7500x_Periph_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - - -/** - * @brief UART Init Structure definition - */ - -typedef struct -{ - uint32_t UART_BaudRate; - uint16_t UART_WordLength; - uint16_t UART_StopBits; - uint16_t UART_Parity; - uint16_t UART_Mode; - uint16_t UART_HardwareFlowControl; -} UART_InitTypeDef; - -/** - * @} - */ - - -/** @defgroup UART_Exported_Constants - * @{ - */ - -#define IS_UART_01_PERIPH(PERIPH) (((PERIPH) == UART0) || ((PERIPH) == UART1)) -#define IS_UART_2_PERIPH(PERIPH) ((PERIPH) == UART2) - -/** - * @} - */ - - - -/** @addtogroup UART_Word_Length - * @{ - */ - -#define UART_WordLength_8b ((uint16_t)UART_LCR_H_WLEN(3)) -#define UART_WordLength_7b ((uint16_t)UART_LCR_H_WLEN(2)) -#define UART_WordLength_6b ((uint16_t)UART_LCR_H_WLEN(1)) -#define UART_WordLength_5b ((uint16_t)UART_LCR_H_WLEN(0)) -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_8b) || \ - ((LENGTH) == UART_WordLength_7b) || \ - ((LENGTH) == UART_WordLength_6b) || \ - ((LENGTH) == UART_WordLength_5b) ) -/** - * @} - */ - - -/** @addtogroup UART_Parity - * @{ - */ - -#define UART_Parity_No ((uint16_t)0x0000) -#define UART_Parity_Even ((uint16_t)(UART_LCR_H_PEN | UART_LCR_H_EPS)) -#define UART_Parity_Odd ((uint16_t)(UART_LCR_H_PEN)) -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \ - ((PARITY) == UART_Parity_Even) || \ - ((PARITY) == UART_Parity_Odd)) - -/** - * @} - */ - - -/** @addtogroup UART_Stop_Bits - * @{ - */ - -#define UART_StopBits_1 ((uint16_t)0x0000) -#define UART_StopBits_2 ((uint16_t)(UART_LCR_H_STP2)) -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \ - ((STOPBITS) == UART_StopBits_2)) -/** - * @} - */ - - -/** @addtogroup UART_Mode - * @{ - */ - -#define UART_Mode_Rx ((uint16_t)(UART_CR_RXE)) -#define UART_Mode_Tx ((uint16_t)(UART_CR_TXE)) -#define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \ - ((MODE) == UART_Mode_Tx) || \ - ((MODE) == (UART_Mode_Rx | UART_Mode_Tx))) - -/** - * @} - */ - - -/** @addtogroup UART_Hardware_Flow_Control - * @{ - */ - -#define UART_HardwareFlowControl_None ((uint16_t)0x0000) -#define UART_HardwareFlowControl_RTS ((uint16_t)UART_CR_RTSEn) -#define UART_HardwareFlowControl_CTS ((uint16_t)UART_CR_CTSEn) -#define UART_HardwareFlowControl_RTS_CTS ((uint16_t)(UART_CR_RTSEn | UART_CR_CTSEn)) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) \ - (((CONTROL) == UART_HardwareFlowControl_None) || \ - ((CONTROL) == UART_HardwareFlowControl_RTS) || \ - ((CONTROL) == UART_HardwareFlowControl_CTS) || \ - ((CONTROL) == UART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - - -/** @addtogroup UART_DMA_Control - * @{ - */ - -#define UART_DMAControl_DMAONERR ((uint16_t)UART_DMACR_DMAONERR) -#define UART_DMAControl_RXDMAE ((uint16_t)UART_DMACR_TXDMAE) -#define UART_DMAControl_TXDMAE ((uint16_t)UART_DMACR_RXDMAE) -#define IS_UART_DMA_CONTROL(CONTROL) \ - (((CONTROL) == UART_DMAControl_DMAONERR) || \ - ((CONTROL) == UART_DMAControl_TXDMAE) || \ - ((CONTROL) == UART_DMAControl_RXDMAE)) -/** - * @} - */ - - -/** @addtogroup UART_Receive Status - * @{ - */ - -#define UART_RECV_STATUS_OE ((uint16_t)0x01UL << 3) /*!< Overrun error */ -#define UART_RECV_STATUS_BE ((uint16_t)0x01UL << 2) /*!< Break error */ -#define UART_RECV_STATUS_PE ((uint16_t)0x01UL << 1) /*!< Parity error */ -#define UART_RECV_STATUS_FE ((uint16_t)0x01UL << 0) /*!< Framing error */ -#define IS_UART_RECV_STATUS(FLAG) (((FLAG) == UART_RECV_STATUS_OE) || ((FLAG) == UART_RECV_STATUS_BE) || \ - ((FLAG) == UART_RECV_STATUS_PE) || ((FLAG) == UART_RECV_STATUS_FE)) -/** - * @} - */ - - - -/** @addtogroup UART_Flags - * @{ - */ - -#define UART_FLAG_RI ((uint16_t)0x01UL << 8) /*!< Ring indicator */ -#define UART_FLAG_TXFE ((uint16_t)0x01UL << 7) /*!< Transmit FIFO empty */ -#define UART_FLAG_RXFF ((uint16_t)0x01UL << 6) /*!< Receive FIFO full */ -#define UART_FLAG_TXFF ((uint16_t)0x01UL << 5) /*!< Transmit FIFO full */ -#define UART_FLAG_RXFE ((uint16_t)0x01UL << 4) /*!< Receive FIFO empty */ -#define UART_FLAG_BUSY ((uint16_t)0x01UL << 3) /*!< UART busy */ -#define UART_FLAG_DCD ((uint16_t)0x01UL << 2) /*!< Data carrier detect */ -#define UART_FLAG_DSR ((uint16_t)0x01UL << 1) /*!< Data set ready */ -#define UART_FLAG_CTS ((uint16_t)0x01UL << 0) /*!< Clear to send */ -#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_RI) || ((FLAG) == UART_FLAG_TXFE) || \ - ((FLAG) == UART_FLAG_RXFF) || ((FLAG) == UART_FLAG_TXFF) || \ - ((FLAG) == UART_FLAG_RXFE) || ((FLAG) == UART_FLAG_BUSY) || \ - ((FLAG) == UART_FLAG_DCD) || ((FLAG) == UART_FLAG_DSR) || \ - ((FLAG) == UART_FLAG_CTS)) - -/** - * @} - */ - - -/** @addtogroup UART_IT_Flags - * @{ - */ - -#define UART_IT_FLAG_OEI ((uint16_t)0x01UL << 10) /*!< Overrun error interrupt */ -#define UART_IT_FLAG_BEI ((uint16_t)0x01UL << 9) /*!< Break error interrupt */ -#define UART_IT_FLAG_PEI ((uint16_t)0x01UL << 8) /*!< Parity error interrupt */ -#define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */ -#define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */ -#define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */ -#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */ -#define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */ -#define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */ -#define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */ -#define UART_IT_FLAG_RIMI ((uint16_t)0x01UL << 0) /*!< UARTRI modem interrupt */ -#define IS_UART_IT_FLAG(FLAG) (((FLAG) == UART_IT_FLAG_OEI) || ((FLAG) == UART_IT_FLAG_BEI) || \ - ((FLAG) == UART_IT_FLAG_PEI) || ((FLAG) == UART_IT_FLAG_FEI) || \ - ((FLAG) == UART_IT_FLAG_RTI) || ((FLAG) == UART_IT_FLAG_TXI) || \ - ((FLAG) == UART_IT_FLAG_RXI) || ((FLAG) == UART_IT_FLAG_DSRMI) || \ - ((FLAG) == UART_IT_FLAG_DCDMI)|| ((FLAG) == UART_IT_FLAG_CTSMI) || \ - ((FLAG) == UART_IT_FLAG_RIMI)) -/** - * @} - */ -/** @addtogroup UART_FIFO_Level Select - * @{ - */ - -#define UART_IFLS_RXIFLSEL7_8 ((uint16_t)(UART_IFLS_RXIFLSEL(4))) -#define UART_IFLS_RXIFLSEL3_4 ((uint16_t)(UART_IFLS_RXIFLSEL(3))) -#define UART_IFLS_RXIFLSEL1_2 ((uint16_t)(UART_IFLS_RXIFLSEL(2))) -#define UART_IFLS_RXIFLSEL1_4 ((uint16_t)(UART_IFLS_RXIFLSEL(1))) -#define UART_IFLS_RXIFLSEL1_8 ((uint16_t)(UART_IFLS_RXIFLSEL(0))) -#define UART_IFLS_TXIFLSEL7_8 ((uint16_t)(UART_IFLS_TXIFLSEL(4))) -#define UART_IFLS_TXIFLSEL3_4 ((uint16_t)(UART_IFLS_TXIFLSEL(3))) -#define UART_IFLS_TXIFLSEL1_2 ((uint16_t)(UART_IFLS_TXIFLSEL(2))) -#define UART_IFLS_TXIFLSEL1_4 ((uint16_t)(UART_IFLS_TXIFLSEL(1))) -#define UART_IFLS_TXIFLSEL1_8 ((uint16_t)(UART_IFLS_TXIFLSEL(0))) - -#define IS_UART_FIFO_Level(FLAG) (((FLAG) == UART_IFLS_RXIFLSEL7_8) || ((FLAG) == UART_IFLS_RXIFLSEL3_4)|| \ - ((FLAG) == UART_IFLS_RXIFLSEL1_2)|| ((FLAG) == UART_IFLS_RXIFLSEL1_4)|| ((FLAG) == UART_IFLS_RXIFLSEL1_8)||\ - ((FLAG) == UART_IFLS_TXIFLSEL7_8)|| ((FLAG) == UART_IFLS_TXIFLSEL3_4)|| \ - ((FLAG) == UART_IFLS_TXIFLSEL1_2)|| ((FLAG) == UART_IFLS_TXIFLSEL1_4)||((FLAG) == UART_IFLS_TXIFLSEL1_8)) - -/** - * @} - */ - -/** @addtogroup S_UART_Flags - * @{ - */ -#define S_UART_STATE_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */ -#define S_UART_STATE_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */ -#define S_UART_STATE_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */ -#define S_UART_STATE_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */ -#define IS_S_UART_STATE(FLAG) (((FLAG) == S_UART_STATE_RXO) || ((FLAG) == S_UART_STATE_TXO) || \ - ((FLAG) == S_UART_STATE_RXF) || ((FLAG) == S_UART_STATE_TXF)) -/** - * @} - */ - - -/** @addtogroup S_UART_CTRL_Flags - * @{ - */ - -#define S_UART_CTRL_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */ -#define S_UART_CTRL_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */ -#define S_UART_CTRL_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */ -#define S_UART_CTRL_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */ -#define S_UART_CTRL_RX ((uint16_t)0x01UL << 1) /*!< RX */ -#define S_UART_CTRL_TX ((uint16_t)0x01UL << 0) /*!< TX */ - - -#define IS_S_UART_CTRL_FLAG(FLAG) (((FLAG) == S_UART_CTRL_FLAG_RXOI) || ((FLAG) == S_UART_CTRL_FLAG_TXOI) || \ - ((FLAG) == S_UART_CTRL_FLAG_RXI) || ((FLAG) == S_UART_CTRL_FLAG_TXI) || \ - ((FLAG) == S_UART_CTRL_FLAG_RX) || ((FLAG) == S_UART_CTRL_FLAG_TX)) -/** - * @} - */ - - -/** @addtogroup S_UART_IT_Flags - * @{ - */ - -#define S_UART_INTSTATUS_RXOI ((uint16_t)0x01UL << 3) /*!< RX overrun interrupt */ -#define S_UART_INTSTATUS_TXOI ((uint16_t)0x01UL << 2) /*!< TX overrun interrupt */ -#define S_UART_INTSTATUS_RXI ((uint16_t)0x01UL << 1) /*!< RX interrupt */ -#define S_UART_INTSTATUS_TXI ((uint16_t)0x01UL << 0) /*!< TX interrupt */ -#define IS_S_UART_INTSTATUS(FLAG) (((FLAG) == S_UART_INTSTATUS_RXOI) || ((FLAG) == S_UART_INTSTATUS_TXOI) || \ - ((FLAG) == S_UART_INTSTATUS_RXI) || ((FLAG) == S_UART_INTSTATUS_TXI)) -/** - * @} - */ - - -void UART_StructInit (UART_InitTypeDef* UART_InitStruct); - -uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct); -void UART_FIFO_Enable (UART_TypeDef *UARTx, uint16_t rx_fifo_level, uint16_t tx_fifo_level); -void UART_FIFO_Disable (UART_TypeDef *UARTx); -void UART_SendData (UART_TypeDef* UARTx, uint16_t Data); -uint16_t UART_ReceiveData (UART_TypeDef* UARTx); -void UART_SendBreak (UART_TypeDef* UARTx); -void UART_ClearRecvStatus (UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS); -FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG); -void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState); -ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT); -void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT); -void UART_DMA_Config(UART_TypeDef* UARTx, uint16_t UART_DMA_CONTROL); - -uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch); -void UartPuts (UART_TypeDef* UARTx, uint8_t *str); -uint8_t UartGetc (UART_TypeDef* UARTx); - -void S_UART_DeInit (void); -uint32_t S_UART_Init (uint32_t baud); -void S_UART_SetBaud (uint32_t baud); -void S_UART_SetCTRL (uint16_t S_UART_CTRL, FunctionalState NewState); -void S_UART_SendData (uint16_t Data); -uint16_t S_UART_ReceiveData(void); - -uint8_t S_UartPutc (uint8_t ch); -void S_UartPuts (uint8_t *str); -uint8_t S_UartGetc (void); - -FlagStatus S_UART_GetFlagStatus (uint16_t S_UART_STATE); -void S_UART_ITConfig (uint16_t S_UART_CTRL, FunctionalState NewState); - -ITStatus S_UART_GetITStatus (uint16_t S_UART_IT); -void S_UART_ClearITPendingBit(uint16_t S_UART_IT); - - -#ifdef __cplusplus -} -#endif - - -#endif // __W7500X_UART_H - -/** - * @} - */ - -/** - * @} - */ diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c deleted file mode 100644 index 310663c0618..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c +++ /dev/null @@ -1,122 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "mbed_wait_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "W7500x_adc.h" -#include "PeripheralPins.h" - - -ADC_TypeDef * AdcHandle; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); - - // Save pin number for the read function - obj->pin = pin; - - // The ADC initialization - ADC_Init(); -} - -static inline uint16_t adc_read(analogin_t *obj) -{ - ADC_CH adc_ch; - - switch (obj->pin) { - case PC_15: - adc_ch = ADC_CH0; - break; - case PC_14: - adc_ch = ADC_CH1; - break; - case PC_13: - adc_ch = ADC_CH2; - break; - case PC_12: - adc_ch = ADC_CH3; - break; - case PC_11: - adc_ch = ADC_CH4; - break; - case PC_10: - adc_ch = ADC_CH5; - break; - case PC_09: - adc_ch = ADC_CH6; - break; - case PC_08: - adc_ch = ADC_CH7; - break; - default: - return 0; - } - - ADC_ChannelSelect(adc_ch); - ADC_Start(); - - // Wait end of conversion and get value - while(ADC_IsInterrupt()); - return ADC_ReadData(); -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/device/W7500x.h b/targets/TARGET_WIZNET/TARGET_W7500x/device/W7500x.h deleted file mode 100644 index b4a6946c76c..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/device/W7500x.h +++ /dev/null @@ -1,1191 +0,0 @@ -/**************************************************************************//** - * @file W7500x.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for - * Device W7500x - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2010-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef W7500x_H -#define W7500x_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup W7500x_Definitions W7500x Definitions - This file defines all structures and symbols for W7500x: - - registers and bitfields - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ - - -/******************************************************************************/ -/* Processor and Core Peripherals */ -/******************************************************************************/ -/** @addtogroup W7500x_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M0 Processor and Core Peripherals - @{ -*/ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers **************************************************/ - -/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ - NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ -/****** W7500x Specific Interrupt Numbers *********************************************************/ - SSP0_IRQn = 0, /*!< SSP 0 Interrupt */ - SSP1_IRQn = 1, /*!< SSP 1 Interrupt */ - UART0_IRQn = 2, /*!< UART 0 Interrupt */ - UART1_IRQn = 3, /*!< UART 1 Interrupt */ - UART2_IRQn = 4, /*!< UART 2 Interrupt */ - I2C0_IRQn = 5, /*!< I2C 0 Interrupt */ - I2C1_IRQn = 6, /*!< I2C 1 Interrupt */ - PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */ - PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */ - PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */ - PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */ - DMA_IRQn = 11, /*!< DMA combined Interrupt */ - DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */ - DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */ - PWM0_IRQn = 14, /*!< PWM 0 Interrupt */ - PWM1_IRQn = 15, /*!< PWM 1 Interrupt */ - PWM2_IRQn = 16, /*!< PWM 2 Interrupt */ - PWM3_IRQn = 17, /*!< PWM 3 Interrupt */ - PWM4_IRQn = 18, /*!< PWM 4 Interrupt */ - PWM5_IRQn = 19, /*!< PWM 5 Interrupt */ - PWM6_IRQn = 20, /*!< PWM 6 Interrupt */ - PWM7_IRQn = 21, /*!< PWM 7 Interrupt */ - RTC_IRQn = 22, /*!< RTC Interrupt */ - ADC_IRQn = 23, /*!< ADC Interrupt */ - WZTOE_IRQn = 24, /*!< WZTOE Interrupt */ - EXTI_IRQn = 25 /*!< EXTI Interrupt */ -} IRQn_Type; - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M0 Processor and Core Peripherals */ -#define __CM0_REV 0x0000 /*!< Core Revision r0p0 */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ - -/*@}*/ /* end of group W7500x_CMSIS */ - - -#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ -#include "system_W7500x.h" /* W7500x System include file */ - - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - - - - -/** - * @} - */ - - - - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Clock Reset Generator - */ -typedef struct -{ - __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */ - uint32_t RESERVED0[3]; - __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */ - __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */ - __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */ - __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */ - __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */ - uint32_t RESERVED1[3]; - __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */ - __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */ - uint32_t RESERVED2[2]; - __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */ - __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */ - uint32_t RESERVED3[6]; - __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */ - __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */ - uint32_t RESERVED4[2]; - __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */ - __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */ - uint32_t RESERVED5[2]; - __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */ - __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */ - uint32_t RESERVED6[10]; - __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */ - __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */ - uint32_t RESERVED7[2]; - __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */ - __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */ - uint32_t RESERVED8[2]; - __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */ - __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */ - uint32_t RESERVED9[2]; - __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */ - __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */ - uint32_t RESERVED10[2]; - __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */ - __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */ - uint32_t RESERVED11[2]; - __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */ - __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */ - uint32_t RESERVED12[2]; - __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */ - __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */ - uint32_t RESERVED13[2]; - __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */ - __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */ - uint32_t RESERVED14[2]; - __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */ - __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */ - uint32_t RESERVED15; - __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */ - - __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */ - __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */ - uint32_t RESERVED16; - __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */ - - __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */ - __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */ - uint32_t RESERVED17[2]; - __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */ - uint32_t RESERVED18[3]; - __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */ -}CRG_TypeDef; - - -/** - * @brief UART - */ -typedef struct -{ - __IO uint32_t DR; /*!< Data, Address offset : 0x00 */ - union { - __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */ - __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */ - } STATUS; - uint32_t RESERVED0[4]; - __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */ - uint32_t RESERVED1; - __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */ - __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */ - __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */ - __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */ - __IO uint32_t CR; /*!< Control, Address offset : 0x30 */ - __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */ - __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */ - __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */ - __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */ - __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */ - __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */ -} UART_TypeDef; - - -/** - * @brief Simple UART - */ -typedef struct -{ - __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ - __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ - __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ - union { - __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ - __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ - }INT; - __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */ - -} S_UART_TypeDef; - -/** - * @brief Analog Digital Converter - */ - -typedef struct -{ - __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */ - __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */ - __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */ - __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */ - __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */ - uint32_t RESERVED0[2]; - __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */ -}ADC_TypeDef; - -/** - * @brief dualtimer - */ -typedef struct -{ - __IO uint32_t TimerLoad; // Timer Load - __I uint32_t TimerValue; // Timer Counter Current Value - __IO uint32_t TimerControl; // Timer Control - // TimerEn: Timer Enable - // TimerMode: Timer Mode - // <0=> Freerunning-mode - // <1=> Periodic mode - // IntEnable: Interrupt Enable - // TimerPre: Timer Prescale - // <0=> / 1 - // <1=> / 16 - // <2=> / 256 - // <3=> Undefined! - // TimerSize: Timer Size - // <0=> 16-bit counter - // <1=> 32-bit counter - // OneShot: One-shoot mode - // <0=> Wrapping mode - // <1=> One-shot mode - // - __O uint32_t TimerIntClr; // Timer Interrupt Clear - __I uint32_t TimerRIS; // Timer Raw Interrupt Status - __I uint32_t TimerMIS; // Timer Masked Interrupt Status - __IO uint32_t TimerBGLoad; // Background Load Register -} DUALTIMER_TypeDef; - -/** - * @brief GPIO - */ -typedef struct -{ - __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */ - __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */ - uint32_t RESERVED0[2]; - __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */ - __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */ - __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */ - __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */ - __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */ - __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */ - __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */ - __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */ - __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */ - __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */ - union { - __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */ - __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */ - }Interrupt; - uint32_t RESERVED3[241]; - __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */ - __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */ -} GPIO_TypeDef; - -typedef struct -{ - __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */ - /* Port_01, offset : 0x04 */ - /* Port_02, offset : 0x08 */ - /* Port_03, offset : 0x0C */ - /* Port_04, offset : 0x10 */ - /* Port_05, offset : 0x14 */ - /* Port_06, offset : 0x18 */ - /* Port_07, offset : 0x1C */ - /* Port_08, offset : 0x20 */ - /* Port_09, offset : 0x24 */ - /* Port_10, offset : 0x28 */ - /* Port_11, offset : 0x2C */ - /* Port_12, offset : 0x30 */ - /* Port_13, offset : 0x34 */ - /* Port_14, offset : 0x38 */ - /* Port_15, offset : 0x3C */ -} P_Port_Def; - -typedef struct -{ - __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */ - /* Port_01, offset : 0x04 */ - /* Port_02, offset : 0x08 */ - /* Port_03, offset : 0x0C */ - /* Port_04, offset : 0x10 */ -} P_Port_D_Def; - -/** - * @brief I2C Register structure definition - */ -typedef struct -{ - __IO uint32_t PRER; //0x00 - __IO uint32_t CTR; //0x04 - __IO uint32_t CMDR; //0x08 - __I uint32_t SR; //0x0C - __IO uint32_t TSR; //0x10 - __IO uint32_t SADDR; //0x14 - __IO uint32_t TXR; //0x18 - __I uint32_t RXR; //0x1C - __I uint32_t ISR; //0x20 - __IO uint32_t ISCR; //0x24 - __IO uint32_t ISMR; //0x28 -}I2C_TypeDef; - -/** - * @brief PWM Register structure definition - */ -typedef struct -{ - __IO uint32_t IER; //Interrupt enable register - // <7> IE7 : Channel 7 interrupt enable - // <6> IE6 : Channel 6 interrupt enable - // <5> IE5 : Channel 5 interrupt enable - // <4> IE4 : Channel 4 interrupt enable - // <3> IE3 : Channel 3 interrupt enable - // <2> IE2 : Channel 2 interrupt enable - // <1> IE1 : Channel 1 interrupt enable - // <0> IE0 : Channel 0 interrupt enable - - __IO uint32_t SSR; //Start Stop register - // <7> SS7 : Channel 7 TC start or stop - // <6> SS6 : Channel 6 TC start or stop - // <5> SS5 : Channel 5 TC start or stop - // <4> SS4 : Channel 4 TC start or stop - // <3> SS3 : Channel 3 TC start or stop - // <2> SS2 : Channel 2 TC start or stop - // <1> SS1 : Channel 1 TC start or stop - // <0> SS0 : Channel 0 TC start or stop - - __IO uint32_t PSR; //Pause register - // <7> PS7 : Channel 7 TC pasue - // <6> PS6 : Channel 6 TC pasue - // <5> PS5 : Channel 5 TC pasue - // <4> PS4 : Channel 4 TC pasue - // <3> PS3 : Channel 3 TC pasue - // <2> PS2 : Channel 2 TC pasue - // <1> PS1 : Channel 1 TC pasue - // <0> PS0 : Channel 0 TC pasue -} PWM_TypeDef; - -typedef struct -{ - __I uint32_t IR; //Interrupt register - // <2> CI : Capture interrupt - // <1> OI : Overflow interrupt - // <0> MI : Match interrupt - - __IO uint32_t IER; //Interrupt enable register - // <2> CIE : Capture interrupt enable - // <1> OIE : Overflow interrupt enable - // <0> MIE : Match interrupt enable - - __O uint32_t ICR; //Interrupt clear register - // <2> CIC : Capture interrupt clear - // <1> OIC : Overflow interrupt clear - // <0> MIC : Match interrupt clear - - __I uint32_t TCR; //Timer/Counter register - // <0..31> TCR : Timer/Counter register - - __I uint32_t PCR; //Prescale counter register - // <0..5> PCR : Prescale Counter register - - __IO uint32_t PR; //Prescale register - // <0..5> PR : prescale register - - __IO uint32_t MR; //Match register - // <0..31> MR : Match register - - __IO uint32_t LR; //Limit register - // <0..31> LR : Limit register - __IO uint32_t UDMR; //Up-Down mode register - // <0> UDM : Up-down mode - - __IO uint32_t TCMR; //Timer/Counter mode register - // <0> TCM : Timer/Counter mode - - __IO uint32_t PEEER; //PWM output enable and external input enable register - // <0..1> PEEE : PWM output enable and external input enable - - __IO uint32_t CMR; //Capture mode register - // <0> CM : Capture mode - - __IO uint32_t CR; //Capture register - // <0..31> CR : Capture register - - __IO uint32_t PDMR; //Periodic mode register - // <0> PDM : Periodic mode - - __IO uint32_t DZER; //Dead-zone enable register - // <0> DZE : Dead-zone enable - - __IO uint32_t DZCR; //Dead-zone counter register - // <0..9> DZC : Dead-zone counter -} PWM_CHn_TypeDef; - -typedef struct -{ - __IO uint32_t PWM_CHn_PR; //Prescale register - // <0..5> PR : prescale register - __IO uint32_t PWM_CHn_MR; //Match register - // <0..31> MR : Match register - __IO uint32_t PWM_CHn_LR; //Limit register - // <0..31> LR : Limit register - __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register - // <0> UDM : Up-down mode - __IO uint32_t PWM_CHn_PDMR; //Periodic mode register - // <0> PDM : Periodic mode -}PWM_TimerModeInitTypeDef; - -typedef struct -{ - __IO uint32_t PWM_CHn_PR; //Prescale register - // <0..5> PR : prescale register - __IO uint32_t PWM_CHn_MR; //Match register - // <0..31> MR : Match register - __IO uint32_t PWM_CHn_LR; //Limit register - // <0..31> LR : Limit register - __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register - // <0> UDM : Up-down mode - __IO uint32_t PWM_CHn_PDMR; //Periodic mode register - // <0> PDM : Peiodic mode - __IO uint32_t PWM_CHn_CMR; //Capture mode register - // <0> CM : Capture mode -}PWM_CaptureModeInitTypeDef; - -typedef struct -{ - __IO uint32_t PWM_CHn_MR; - __IO uint32_t PWM_CHn_LR; - __IO uint32_t PWM_CHn_UDMR; - __IO uint32_t PWM_CHn_PDMR; - __IO uint32_t PWM_CHn_TCMR; -}PWM_CounterModeInitTypeDef; - - -/** - * @brief Random Number generator - */ -typedef struct -{ - __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */ - __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */ - __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */ - __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */ - __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */ - __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */ -}RNG_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __IO uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; - __IO uint32_t DMACR; -} SSP_TypeDef; - -typedef struct -{ - __IO uint32_t WatchdogLoad; // Watchdog Load Register - __I uint32_t WatchdogValue; // Watchdog Value Register - __IO uint32_t WatchdogControl; // Watchdog Control Register - // RESEN: Reset enable - // INTEN: Interrupt enable - // - __O uint32_t WatchdogIntClr; // Watchdog Clear Interrupt Register - __I uint32_t WatchdogRIS; // Watchdog Raw Interrupt Status Register - __I uint32_t WatchdogMIS; // Watchdog Interrupt Status Register - uint32_t RESERVED[762]; - __IO uint32_t WatchdogLock; // Watchdog Lock Register -}WATCHDOG_TypeDef; - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -/* Peripheral and SRAM base address */ -#define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ -#define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ -#define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ - -#define W7500x_RAM_BASE (0x20000000UL) -#define W7500x_APB1_BASE (0x40000000UL) -#define W7500x_APB2_BASE (0x41000000UL) -#define W7500x_AHB_BASE (0x42000000UL) - -#define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL) -#define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL) -#define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL) - -#define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL) -#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL) - -#define W7500x_INFO_BGT (0x0003FDB8) -#define W7500x_INFO_OSC (0x0003FDBC) - -#define W7500x_TRIM_BGT (0x41001210) -#define W7500x_TRIM_OSC (0x41001004) - -#define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul) -#define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul) - -#define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL) - -#define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL -#define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL) -#define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL) -#define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL) - -#define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL) - -#define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL) - -#define I2C0_BASE (W7500x_APB1_BASE + 0x8000) -#define I2C1_BASE (W7500x_APB1_BASE + 0x9000) - -#define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL) - -#define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL) - -#define SSP0_BASE (0x4000A000) -#define SSP1_BASE (0x4000B000) - -#define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL) - -/** - * @} - */ - - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define CRG ((CRG_TypeDef *) W7500x_CRG_BASE) - -#define UART0 ((UART_TypeDef *) W7500x_UART0_BASE) -#define UART1 ((UART_TypeDef *) W7500x_UART1_BASE) -#define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE) - -#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE) - -#define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) ) -#define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul)) -#define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) ) -#define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul)) - -#define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */ -#define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */ -#define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */ -#define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */ - -#define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) ) -#define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) ) -#define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) ) -#define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) ) - -#define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */ -#define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */ -#define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */ -#define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */ - -#define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */ -#define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */ -#define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */ -#define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */ - -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) - - -#define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul) -#define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul) -#define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul) -#define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul) - -#define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL )) -#define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE)) -#define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL)) -#define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL)) -#define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL)) -#define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL)) -#define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL)) -#define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL)) -#define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL)) - -#define PWM_CH0_BASE (W7500x_PWM_BASE) -#define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL) -#define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL) -#define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL) -#define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL) -#define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL) -#define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL) -#define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL) - -#define RNG ((RNG_TypeDef *) W7500x_RNG_BASE) - -#define SSP0 ((SSP_TypeDef*) (SSP0_BASE)) -#define SSP1 ((SSP_TypeDef*) (SSP1_BASE)) - -#define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE) - -/** - * @} - */ - - - -/******************************************************************************/ -/* */ -/* Clock Reset Generator */ -/* */ -/******************************************************************************/ -/**************** Bit definition for CRG_OSC_PDR **************************/ -#define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation -#define CRG_OSC_PDR_PD (0x1ul) // Power Down -/**************** Bit definition for CRG_PLL_PDR **************************/ -#define CRG_PLL_PDR_PD (0x0ul) // Power Down -#define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation -/**************** Bit definition for CRG_PLL_FCR **************************/ -//ToDo -/**************** Bit definition for CRG_PLL_OER **************************/ -#define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable -#define CRG_PLL_OER_EN (0x1ul) // Clock out is enable -/**************** Bit definition for CRG_PLL_BPR **************************/ -#define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation -#define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock -/**************** Bit definition for CRG_PLL_IFSR **************************/ -#define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_FCLK_SSR **************************/ -#define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK) -#define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_FCLK_PVSR **************************/ -#define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) -#define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2 -#define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4 -#define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8 -/**************** Bit definition for CRG_SSPCLK_SSR **************************/ -#define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock -#define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) -#define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_SSPCLK_PVSR **************************/ -#define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) -#define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2 -#define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4 -#define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8 -/**************** Bit definition for CRG_ADCCLK_SSR **************************/ -#define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock -#define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) -#define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_ADCCLK_PVSR **************************/ -#define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) -#define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2 -#define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4 -#define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8 -/**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/ -#define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock -#define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) -#define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/ -#define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) -#define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2 -#define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4 -#define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8 -#define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16 -#define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32 -#define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64 -#define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128 -/**************** Bit definition for CRG_PWMnCLK_SSR **************************/ -#define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock -#define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) -#define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_PWMnCLK_PVSR **************************/ -#define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) -#define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2 -#define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4 -#define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8 -#define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16 -#define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32 -#define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64 -#define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128 -/**************** Bit definition for CRG_RTC_HS_SSR **************************/ -#define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock -#define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK) -#define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_RTC_HS_PVSR **************************/ -#define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass) -#define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2 -#define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4 -#define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8 -#define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16 -#define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32 -#define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64 -#define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128 -/**************** Bit definition for CRG_RTC_SSR **************************/ -#define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock) -#define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock) -/**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/ -#define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock -#define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK) -#define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/ -#define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass) -#define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2 -#define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4 -#define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8 -#define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16 -#define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32 -#define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64 -#define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128 -/**************** Bit definition for CRG_WDOGCLK_SSR **************************/ -#define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock) -#define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock) -/**************** Bit definition for CRG_UARTCLK_SSR **************************/ -#define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock -#define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) -#define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -/**************** Bit definition for CRG_UARTCLK_PVSR **************************/ -#define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) -#define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2 -#define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4 -#define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8 -/**************** Bit definition for CRG_MIICLK_ECR **************************/ -#define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N -#define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N -/**************** Bit definition for CRG_MONCLK_SSR **************************/ -#define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK) -#define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK -#define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) -#define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) -#define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK -#define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK -#define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0 -#define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1 -#define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0 -#define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1 -#define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2 -#define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3 -#define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4 -#define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5 -#define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6 -#define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7 -#define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK -#define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK -#define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK -#define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK - -/******************************************************************************/ -/* */ -/* UART */ -/* */ -/******************************************************************************/ -/****************** Bit definition for UART Data(UARTDR) register *************************/ -#define UART_DR_OE (0x01ul << 11) // Overrun Error -#define UART_DR_BE (0x01ul << 10) // Break Error -#define UART_DR_PE (0x01ul << 9) // Parity Error -#define UART_DR_FE (0x01ul << 8) // Framing Error -//#define UART_DR_DR // ToDo -/***************** Bit definition for UART Receive Status(UARTRSR) register ***************/ -#define UARTR_SR_OE (0x01ul << 3) // Overrun Error -#define UARTR_SR_BE (0x01ul << 2) // Break Error -#define UARTR_SR_PE (0x01ul << 1) // Parity Error -#define UARTR_SR_FE (0x01ul << 0) // Framing Error -/***************** Bit definition for UART Error Clear(UARTECR) register ******************/ -#define UARTE_CR_OE (0x01ul << 3) // Overrun Error -#define UARTE_CR_BE (0x01ul << 2) // Break Error -#define UARTE_CR_PE (0x01ul << 1) // Parity Error -#define UARTE_CR_FE (0x01ul << 0) // Framing Error -/****************** Bit definition for UART Flags(UARTFR) register ************************/ -#define UART_FR_RI (0x01ul << 8) // Ring indicator -#define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty -#define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full -#define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full -#define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty -#define UART_FR_BUSY (0x01ul << 3) // UART busy -#define UART_FR_DCD (0x01ul << 2) // Data carrier detect -#define UART_FR_DSR (0x01ul << 1) // Data set ready -#define UART_FR_CTS (0x01ul << 0) // Clear to send -/********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/ -#define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255) -/********************* Bit definition for Line Control(UARTLCR_H) register *****************/ -#define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select -#define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits ) -#define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs -#define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select -#define UART_LCR_H_EPS (0x1ul << 2) // Even parity select -#define UART_LCR_H_PEN (0x1ul << 1) // Parity enable -#define UART_LCR_H_BRK (0x1ul << 0) // Send break -/********************* Bit definition for Contro(UARTCR) register *************************/ -#define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable -#define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable -#define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output -#define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output -#define UART_CR_RTS (0x1ul << 11) // Request to send -#define UART_CR_DTR (0x1ul << 10) // Data transmit ready -#define UART_CR_RXE (0x1ul << 9) // Receive enable -#define UART_CR_TXE (0x1ul << 8) // Transmit enable -#define UART_CR_LBE (0x1ul << 7) // Loop-back enable -#define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode -#define UART_CR_SIREN (0x1ul << 1) // SIR enable -#define UART_CR_UARTEN (0x1ul << 0) // UART enable -/******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/ -#define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full) -#define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full) -/******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/ -#define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask -#define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask -#define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask -#define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask -#define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask -#define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask -#define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask -#define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask -#define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask -#define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask -#define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask -/*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/ -#define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status -#define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status -#define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status -#define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status -#define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status -#define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status -#define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status -#define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status -#define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status -#define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status -#define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status -/************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/ -#define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status -#define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status -#define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status -#define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status -#define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status -#define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status -#define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status -#define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status -#define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status -#define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status -#define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status -/*************** Bit definition for Interrupt Clear(UARTICR) register ************************/ -#define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear -#define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear -#define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear -#define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear -#define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear -#define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear -#define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear -#define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear -#define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear -#define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear -#define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear -/***************** Bit definition for DMA Control(UARTDMACR) register ************************/ -#define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error -#define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable -#define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable - -/******************************************************************************/ -/* */ -/* Simple UART */ -/* */ -/******************************************************************************/ -/***************** Bit definition for S_UART Data () register ************************/ -#define S_UART_DATA (0xFFul << 0) -/***************** Bit definition for S_UART State() register ************************/ -#define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear. -#define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only. -#define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only. -/***************** Bit definition for S_UART Control() register ************************/ -#define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only. -#define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable. -#define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable. -#define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable. -#define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable. -#define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable. -#define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable. -/***************** Bit definition for S_UART Interrupt() register ************************/ -#define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear -#define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear -#define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear -#define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear - -/******************************************************************************/ -/* */ -/* Analog Digital Register */ -/* */ -/******************************************************************************/ - -/*********************** Bit definition for ADC_CTR ***********************/ -//#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation -//#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation -#define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation -#define ADC_CTR_PWD_PD (0x3ul) // Power down -/*********************** Bit definition for ADC_CHSEL ***********************/ -#define ADC_CHSEL_CH0 (0x0ul) // Channel 0 -#define ADC_CHSEL_CH1 (0x1ul) // Channel 1 -#define ADC_CHSEL_CH2 (0x2ul) // Channel 2 -#define ADC_CHSEL_CH3 (0x3ul) // Channel 3 -#define ADC_CHSEL_CH4 (0x4ul) // Channel 4 -#define ADC_CHSEL_CH5 (0x5ul) // Channel 5 -#define ADC_CHSEL_CH6 (0x6ul) // Channel 6 -#define ADC_CHSEL_CH7 (0x7ul) // Channel 7 -#define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V) -/*********************** Bit definition for ADC_START ***********************/ -#define ADC_START_START (0x1ul) // ADC conversion start -/*********************** Bit definition for ADC_DATA ***********************/ -//ToDo (Readonly) - -/*********************** Bit definition for ADC_INT ***********************/ -#define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable -#define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable -//ToDo (Readonly) - -/*********************** Bit definition for ADC_INTCLR ***********************/ -#define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear - -#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL) -#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE) - -/******************************************************************************/ -/* */ -/* Dual Timer */ -/* */ -/******************************************************************************/ - -/*********************** Bit definition for dualtimer ***********************/ -#define DUALTIMER_TimerControl_TimerDIsable 0x0ul -#define DUALTIMER_TimerControl_TimerEnable 0x1ul -#define DUALTIMER_TimerControl_TimerEnable_Pos 7 - -#define DUALTIMER_TimerControl_FreeRunning 0x0ul -#define DUALTIMER_TimerControl_Periodic 0x1ul -#define DUALTIMER_TimerControl_TimerMode_Pos 6 - -#define DUALTIMER_TimerControl_IntDisable 0x0ul -#define DUALTIMER_TimerControl_IntEnable 0x1ul -#define DUALTIMER_TimerControl_IntEnable_Pos 5 - -#define DUALTIMER_TimerControl_Pre_1 0x0ul -#define DUALTIMER_TimerControl_Pre_16 0x1ul -#define DUALTIMER_TimerControl_Pre_256 0x2ul -#define DUALTIMER_TimerControl_Pre_Pos 2 - -#define DUALTIMER_TimerControl_Size_16 0x0ul -#define DUALTIMER_TimerControl_Size_32 0x1ul -#define DUALTIMER_TimerControl_Size_Pos 1 - -#define DUALTIMER_TimerControl_Wrapping 0x0ul -#define DUALTIMER_TimerControl_OneShot 0x1ul -#define DUALTIMER_TimerControl_OneShot_Pos 0 - -/******************************************************************************/ -/* */ -/* External Interrupt */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for Px_IER **************************/ -#define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0) -#define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0) -#define EXTI_Px_INTEN_DISABLE (0x00ul << 1) -#define EXTI_Px_INTEN_ENABLE (0x01ul << 1) - -/******************************************************************************/ -/* */ -/* GPIO */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for Px_AFSR **************************/ -#define Px_AFSR_AF0 (0x00ul) -#define Px_AFSR_AF1 (0x01ul) -#define Px_AFSR_AF2 (0x02ul) -#define Px_AFSR_AF3 (0x03ul) -/**************** Bit definition for Px_PCR **************************/ -#define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down -#define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up -#define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving -#define Px_PCR_OD (0x01ul << 3) // Open Drain -#define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable -#define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer - -/******************************************************************************/ -/* */ -/* I2C */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for I2C_CTR **************************/ -#define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80 -#define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40 -#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20 -#define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10 -#define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08 -#define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04 - -/**************** Bit definition for I2C_CMDR **************************/ -#define I2C_CMDR_STA (0x01ul << 7 ) // 0x80 -#define I2C_CMDR_STO (0x01ul << 6 ) // 0x40 -#define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20 -#define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10 - -/**************** Bit definition for I2C_ISCR **************************/ -#define I2C_ISCR_RST (0x01ul << 1) // 0x01 - -/**************** Bit definition for I2C_SR **************************/ -#define I2C_SR_TX (0x01ul << 9 ) // 0x200 -#define I2C_SR_RX (0x01ul << 8 ) // 0x100 -#define I2C_SR_ACKT (0x01ul << 7 ) // 0x080 -#define I2C_SR_BT (0x01ul << 6 ) // 0x040 -#define I2C_SR_SA (0x01ul << 5 ) // 0x020 -#define I2C_SR_SB (0x01ul << 4 ) // 0x010 -#define I2C_SR_AL (0x01ul << 3 ) // 0x008 -#define I2C_SR_TO (0x01ul << 2 ) // 0x004 -#define I2C_SR_SRW (0x01ul << 1 ) // 0x002 -#define I2C_SR_ACKR (0x01ul << 0 ) // 0x001 - -/**************** Bit definition for I2C_ISR **************************/ -#define I2C_ISR_STAE (0x01ul << 4 ) // 0x010 -#define I2C_ISR_STOE (0x01ul << 3 ) // 0x008 -#define I2C_ISR_TOE (0x01ul << 2 ) // 0x004 -#define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002 -#define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001 - -/**************** Bit definition for I2C_ISMR **************************/ -#define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010 -#define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008 -#define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004 -#define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002 -#define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001 - -/******************************************************************************/ -/* */ -/* PWM */ -/* */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Random number generator Register */ -/* */ -/******************************************************************************/ - -/*********************** Bit definition for RNG_RUN ***********************/ -#define RNG_RUN_STOP (0x0ul) // STOP RNG shift register -#define RNG_RUN_RUN (0x1ul) // RUN RNG shift register -/*********************** Bit definition for RNG_SEED ***********************/ -//ToDo - -/*********************** Bit definition for RNG_CLKSEL ***********************/ -#define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register -#define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register -/*********************** Bit definition for RNG_ENABLE ***********************/ -#define RNG_MANUAL_DISABLE (0x0ul) // RNG disble -#define RNG_MANUAL_ENABLE (0x1ul) // RNG enable -/*********************** Bit definition for RNG_RN ***********************/ -//ToDo - -/*********************** Bit definition for RNG_POLY ***********************/ -//ToDo - - - -typedef enum -{ - PAD_PA = 0, - PAD_PB, - PAD_PC, - PAD_PD -}PAD_Type; - -typedef enum -{ - PAD_AF0 = Px_AFSR_AF0, - PAD_AF1 = Px_AFSR_AF1, - PAD_AF2 = Px_AFSR_AF2, - PAD_AF3 = Px_AFSR_AF3 -}PAD_AF_TypeDef; - - -#if !defined (USE_HAL_DRIVER) -#define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - - - -#if defined (USE_HAL_DRIVER) -// #include "system_W7500x.h" -// #include "W7500x_conf.h" -#endif - -#ifdef USE_FULL_ASSERT - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__)) -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* W7500x_H */ - - - -/************************ (C) COPYRIGHT Wiznet *****END OF FILE****/ diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis.h b/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis.h deleted file mode 100644 index 59a30a998ad..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis.h +++ /dev/null @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * A generic CMSIS include header - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "W7500x.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis_nvic.c b/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis_nvic.c deleted file mode 100644 index 71da98cf15b..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis_nvic.c +++ /dev/null @@ -1,47 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash - - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; - - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - // Return the vector - return vectors[IRQn + 16]; -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis_nvic.h b/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis_nvic.h deleted file mode 100644 index 3d1e0ed80f1..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/device/cmsis_nvic.h +++ /dev/null @@ -1,51 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS 41 -#define NVIC_USER_IRQ_OFFSET 16 - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/device/system_W7500x.c b/targets/TARGET_WIZNET/TARGET_W7500x/device/system_W7500x.c deleted file mode 100644 index 46193b12b02..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/device/system_W7500x.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************//** - * @file system_CMSDK_CM0.c - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for - * Device CMSDK - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2010-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include "system_W7500x.h" - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ -//#define SYSCLK_EXTERN_OSC - - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemFrequency = 0; /*!< System Clock Frequency (Core Clock) */ -uint32_t SystemCoreClock = 0; /*!< Processor Clock Frequency */ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint8_t M,N,OD; - -#ifdef SYSCLK_EXTERN_OSC - CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; -#else - CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; -#endif - OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1)); - N = (CRG->PLL_FCR >> 8 ) & 0x3F; - M = (CRG->PLL_FCR >> 16) & 0x3F; - -#ifdef SYSCLK_EXTERN_OSC - SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD; -#else - SystemCoreClock = INTERN_XTAL * M / N * 1 / OD; -#endif -} - -uint32_t GetSystemClock() -{ - return SystemCoreClock; -} - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - uint8_t M,N,OD; - - (*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT))); - (*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC))); - - - // Set PLL input frequency -#ifdef SYSCLK_EXTERN_OSC - CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; -#else - CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; -#endif - OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1)); - N = (CRG->PLL_FCR >> 8 ) & 0x3F; - M = (CRG->PLL_FCR >> 16) & 0x3F; - -#ifdef SYSCLK_EXTERN_OSC - SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD; -#else - SystemCoreClock = INTERN_XTAL * M / N * 1 / OD; -#endif -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/device/system_W7500x.h b/targets/TARGET_WIZNET/TARGET_W7500x/device/system_W7500x.h deleted file mode 100644 index 74af23d9d8d..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/device/system_W7500x.h +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************//** - * @file system_W7500x.h - * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for - * Device W7500x - * @version V3.10 - * @date 23. November 2012 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef SYSTEM_W7500x_H /* ToDo: replace '' with your device name */ -#define SYSTEM_W7500x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "W7500x.h" - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t GetSystemClock(void); /*!< Get System Clock Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define EXTERN_XTAL (8000000UL) /* External Oscillator Frequency */ -#define INTERN_XTAL (8000000UL) /* Internal Oscillator Frequency */ - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_W7500x_H */ diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/gpio_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/gpio_api.c deleted file mode 100644 index 9747c01b2d9..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/gpio_api.c +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" - -extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, Px_AFSR_AF1)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - obj->port_num = WIZ_PORT(pin); - obj->pin_index = WIZ_PIN_INDEX(pin); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(obj->port_num); - obj->reg_data_in = &gpio->DATA; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); - obj->mode = mode; -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - obj->direction = direction; - - pin_function(obj->pin, WIZ_PIN_DATA(obj->direction, obj->mode, 1)); -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c deleted file mode 100644 index d64ee892467..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c +++ /dev/null @@ -1,183 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -static gpio_irq_handler irq_handler; - -static uint32_t channel_ids[4][16]; - - -#ifdef __cplusplus -extern "C"{ -#endif -void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num); - -void PORT0_Handler(void) -{ - NVIC_ClearPendingIRQ(PORT0_IRQn); - port_generic_handler(GPIOA, 0); -} - -void PORT1_Handler(void) -{ - port_generic_handler(GPIOB, 1); -} - -void PORT2_Handler(void) -{ - port_generic_handler(GPIOC, 2); -} - -void PORT3_Handler(void) -{ - port_generic_handler(GPIOD, 3); -} - -void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num) -{ - int i = 0; - int loop = 16; - - if(GPIOx == GPIOD) loop = 5; - - for(i=0; iInterrupt.INTSTATUS & (1 << i)) - { - GPIOx->Interrupt.INTCLEAR |= (1 << i); - if(GPIOx->INTPOLSET >> i) //rising - irq_handler(channel_ids[port_num][i], IRQ_RISE); - else //falling - irq_handler(channel_ids[port_num][i], IRQ_FALL); - } - } -} - -#ifdef __cplusplus -} -#endif - - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - obj->port_num = WIZ_PORT(pin); - obj->pin_num = WIZ_PIN_NUM(pin); - obj->pin_index = WIZ_PIN_INDEX(pin); - - //gpio_irq_disable(obj); - - if (pin == NC) return -1; - - if(obj->port_num == 0) - obj->irq_n = PORT0_IRQn; - else if(obj->port_num == 1) - obj->irq_n = PORT1_IRQn; - else if(obj->port_num == 2) - obj->irq_n = PORT2_IRQn; - else - obj->irq_n = PORT3_IRQn; - - obj->pin = pin; - obj->event = EDGE_NONE; - - // Enable EXTI interrupt - NVIC_ClearPendingIRQ(obj->irq_n); - NVIC_EnableIRQ(obj->irq_n); - - channel_ids[obj->port_num][obj->pin_num] = id; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - channel_ids[obj->port_num][obj->pin_num] = 0; - - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(obj->port_num); - - if (enable) { - if (event == IRQ_RISE) { - gpio->INTPOLSET |= obj->pin_index; - obj->event = EDGE_RISE; - obj->rise_null = 0; - } - else if (event == IRQ_FALL) { - gpio->INTPOLCLR |= obj->pin_index; - obj->event = EDGE_FALL; - obj->fall_null = 0; - } - - - gpio->INTENCLR |= obj->pin_index; - gpio->INTTYPESET |= obj->pin_index; - gpio->INTENSET |= obj->pin_index; - - - } else { - if (event == IRQ_RISE) { - obj->rise_null = 1; - if(obj->fall_null) - gpio->INTENCLR |= obj->pin_index; - } - else if (event == IRQ_FALL) { - obj->fall_null = 1; - if(obj->rise_null) - gpio->INTENCLR |= obj->pin_index; - } - } -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/gpio_object.h b/targets/TARGET_WIZNET/TARGET_W7500x/gpio_object.h deleted file mode 100644 index 005fa7ec17f..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/gpio_object.h +++ /dev/null @@ -1,102 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "W7500x_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t pin_index; - uint32_t port_num; - uint32_t direction; - uint32_t mode; - __IO uint32_t *reg_data_in; -} gpio_t; - - -extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); - - -static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pin != (PinName)NC); - - uint32_t port_num = WIZ_PORT(obj->pin); - uint32_t pin_index = WIZ_PIN_INDEX(obj->pin); - - GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(port_num); - - - if (value) - { - HAL_GPIO_SetBits(gpio, pin_index); - } - else - { - HAL_GPIO_ResetBits(gpio, pin_index); - } -} - -static inline int gpio_read(gpio_t *obj) { - int ret; - - MBED_ASSERT(obj->pin != (PinName)NC); - - uint32_t port_num = WIZ_PORT(obj->pin); - - GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(port_num); - - if(obj->direction == PIN_OUTPUT) - { - ret = ( HAL_GPIO_ReadOutputData(gpio) & obj->pin_index ) ? 1 : 0; - } - else - { - ret = ((*obj->reg_data_in & obj->pin_index) ? 1 : 0); - } - - return ret; -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/i2c_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/i2c_api.c deleted file mode 100644 index bcaaa51cb73..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/i2c_api.c +++ /dev/null @@ -1,202 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "i2c_api.h" - - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -#include "mbed_wait_api.h" -#include "us_ticker_api.h" -#include "W7500x_i2c.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x1000) -#define LONG_TIMEOUT ((int)0xFFFF) - - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - I2C_ConfigStruct conf; - - //Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->I2Cx = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->I2Cx != (I2CName)NC); - - obj->sda = sda; - obj->scl = scl; - obj->ADDRESS = 0x0; - obj->is_setAddress = 0; - - conf.sda = (I2C_PinName)obj->sda; - conf.scl = (I2C_PinName)obj->scl; - - I2C_Init(&conf); -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_ConfigStruct conf; - conf.sda = (I2C_PinName)obj->sda; - conf.scl = (I2C_PinName)obj->scl; - - I2C_Start(&conf); - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_ConfigStruct conf; - conf.sda = (I2C_PinName)obj->sda; - conf.scl = (I2C_PinName)obj->scl; - - I2C_Stop(&conf); - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_ConfigStruct conf; - - conf.sda = (I2C_PinName)obj->sda; - conf.scl = (I2C_PinName)obj->scl; - - - if(stop) - { - if(I2C_Read(&conf, address, (uint8_t*)data, length) != 0) - return -1; - } - else - { - if(I2C_ReadRepeated(&conf, address, (uint8_t*)data, length) != 0) - return -1; - } - - return length; - -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_ConfigStruct conf; - - conf.sda = (I2C_PinName)obj->sda; - conf.scl = (I2C_PinName)obj->scl; - - - if(stop) - { - if(I2C_Write(&conf, address, (uint8_t*)data, length) != 0) - return -1; - } - else - { - if(I2C_WriteRepeated(&conf, address, (uint8_t*)data, length) != 0) - return -1; - } - - return length; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - uint8_t ret; - I2C_ConfigStruct conf; - - conf.sda = (I2C_PinName)obj->sda; - conf.scl = (I2C_PinName)obj->scl; - - ret = I2C_ReadByte(&conf); - - if(last) - I2C_SendNACK(&conf); - else - I2C_SendACK(&conf); - - return (int)ret; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_ConfigStruct conf; - - conf.sda = (I2C_PinName)obj->sda; - conf.scl = (I2C_PinName)obj->scl; - - if(I2C_WriteByte(&conf, (uint8_t)data)) // NACK - return 0; - else //ack - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - - -#endif // DEVICE_I2C diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c b/targets/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c deleted file mode 100644 index 7e55f87031e..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c +++ /dev/null @@ -1,39 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "cmsis.h" - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemInit(); - SysTick_Config((GetSystemClock()/1000)); -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/objects.h b/targets/TARGET_WIZNET/TARGET_W7500x/objects.h deleted file mode 100644 index 8b75ce95886..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/objects.h +++ /dev/null @@ -1,105 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "PortNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t event; - PinName pin; - uint32_t pin_index; - uint32_t pin_num; - uint32_t port_num; - uint32_t rise_null; - uint32_t fall_null; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -struct analogin_s { - ADCName adc; - PinName pin; -}; - -struct serial_s { - UARTName uart; - int index; // Used by irq - uint32_t baudrate; - uint32_t databits; - uint32_t stopbits; - uint32_t parity; - PinName pin_tx; - PinName pin_rx; -}; - -struct spi_s { - SSP_TypeDef *spi; -}; - -struct i2c_s { - I2CName I2Cx; - PinName sda; - PinName scl; - uint16_t ADDRESS; - uint16_t is_setAddress; -}; - -struct pwmout_s { - PWM_CHn_TypeDef * PWM_CHx; - PinName pin; - uint32_t period; - uint32_t pulse; - uint32_t PrescalerValue; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/pinmap.c b/targets/TARGET_WIZNET/TARGET_W7500x/pinmap.c deleted file mode 100644 index 4c1470e1a49..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/pinmap.c +++ /dev/null @@ -1,149 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" -#include "W7500x.h" -#include "W7500x_gpio.h" - - -uint32_t Get_GPIO_BaseAddress(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch(port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - break; - case PortB: - gpio_add = GPIOB_BASE; - break; - case PortC: - gpio_add = GPIOC_BASE; - break; - case PortD: - gpio_add = GPIOD_BASE; - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (input, output, alternate function or analog) + output speed + AF - */ - -void pin_function(PinName pin, int data) { - MBED_ASSERT(pin != (PinName)NC); - // Get the pin informations - uint32_t mode = WIZ_PIN_MODE(data); - uint32_t pupd = WIZ_PIN_PUPD(data); - uint32_t afnum = WIZ_PIN_AFNUM(data); - - uint32_t port_num = WIZ_PORT(pin); - uint32_t pin_index = WIZ_PIN_INDEX(pin); - - GPIO_TypeDef *gpio; - - // Configure Alternate Function - // Warning: Must be done before the GPIO is initialized - switch (afnum) { - case 0: - HAL_PAD_AFConfig((PAD_Type)port_num, (uint16_t)pin_index, (PAD_AF_TypeDef)Px_AFSR_AF0); - break; - case 1: - HAL_PAD_AFConfig((PAD_Type)port_num, (uint16_t)pin_index, (PAD_AF_TypeDef)Px_AFSR_AF1); - break; - case 2: - HAL_PAD_AFConfig((PAD_Type)port_num, (uint16_t)pin_index, (PAD_AF_TypeDef)Px_AFSR_AF2); - break; - case 3: - HAL_PAD_AFConfig((PAD_Type)port_num, (uint16_t)pin_index, (PAD_AF_TypeDef)Px_AFSR_AF3); - break; - default: - break; - } - - if(mode == WIZ_MODE_AF) - return; - - // Configure GPIO - gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(port_num); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = pin_index; - GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode; - GPIO_InitStructure.GPIO_Pad = (GPIOPad_TypeDef)pupd; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode pupd) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t port_num = WIZ_PORT(pin); - uint32_t pin_num = WIZ_PIN_NUM(pin); - - switch(port_num) { - case PortA: - if(pupd != 0) { - PA_PCR->Port[pin_num] &= 0xFFFFFFFC; - } - PA_PCR->Port[pin_num] |= pupd; - break; - case PortB: - if(pupd != 0) { - PB_PCR->Port[pin_num] &= 0xFFFFFFFC; - } - PB_PCR->Port[pin_num] |= pupd; - break; - case PortC: - if(pupd != 0) { - PC_PCR->Port[pin_num] &= 0xFFFFFFFC; - } - PC_PCR->Port[pin_num] |= pupd; - break; - case PortD: - if(pupd != 0) { - PD_PCR->Port[pin_num] &= 0xFFFFFFFC; - } - PD_PCR->Port[pin_num] |= pupd; - break; - default: - error("Pinmap error: wrong port number."); - return; - } -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/port_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/port_api.c deleted file mode 100644 index 42e3ae48a2d..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/port_api.c +++ /dev/null @@ -1,111 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); - -//port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -PinName port_pin(PortName port, int pin_n) -{ - int af_num = 0; - - if( (port == 2) && ((pin_n == 0) || (pin_n == 1) || (pin_n == 4) || (pin_n == 8) || (pin_n == 9)) ) - { - af_num = 1; - } - - - return (PinName)(pin_n + (port << 4) + (af_num << 8)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_num = (uint32_t)port; - - // Enable GPIO clock - GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(port_num); - - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->DATA; - obj->reg_out = &gpio->DATAOUT; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), WIZ_PIN_DATA(WIZ_MODE_OUTPUT, WIZ_GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c deleted file mode 100644 index 775547f888a..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c +++ /dev/null @@ -1,150 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "pwmout_api.h" - -#if DEVICE_PWMOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" -#include "W7500x_pwm.h" - -static PWM_TimerModeInitTypeDef TimerModeStructure; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->PWM_CHx = (PWM_CHn_TypeDef *)pinmap_peripheral(pin, PinMap_PWM); - - if (obj->PWM_CHx == (PWM_CHn_TypeDef *)NC) { - error("PWM error: pinout mapping failed."); - } - - // Configure GPIO - pinmap_pinout(pin, PinMap_PWM); - - GetSystemClock(); - - obj->pin = pin; - - pwmout_period_us(obj, 20000); // 20 ms per default -} - -void pwmout_free(pwmout_t* obj) -{ - // Configure GPIO - pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { - value = 1.0; - } - - obj->pulse = (uint32_t)((float)obj->period * value); - - PWM_CHn_Stop(obj->PWM_CHx); - - TimerModeStructure.PWM_CHn_PR = obj->PrescalerValue - 1; - TimerModeStructure.PWM_CHn_MR = obj->pulse; - TimerModeStructure.PWM_CHn_LR = obj->period; - TimerModeStructure.PWM_CHn_UDMR = PWM_CHn_UDMR_UpCount; - TimerModeStructure.PWM_CHn_PDMR = PWM_CHn_PDMR_Periodic; - - PWM_TimerModeInit(obj->PWM_CHx, &TimerModeStructure); - - PWM_CHn_Start(obj->PWM_CHx); -} - -float pwmout_read(pwmout_t* obj) -{ - float value = 0; - if (obj->period > 0) { - value = (float)(obj->pulse) / (float)(obj->period); - } - return ((value > (float)1.0) ? (float)(1.0) : (value)); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - PWM_CHn_Stop(obj->PWM_CHx); - // Update the SystemCoreClock variable - SystemCoreClockUpdate(); - - obj->period = (us * 2) - 1; - obj->pulse = us / 2; - - obj->PrescalerValue = (SystemCoreClock / 1000000) / 2; - TimerModeStructure.PWM_CHn_PR = obj->PrescalerValue - 1; - TimerModeStructure.PWM_CHn_MR = obj->pulse; - TimerModeStructure.PWM_CHn_LR = obj->period; - TimerModeStructure.PWM_CHn_UDMR = PWM_CHn_UDMR_UpCount; - TimerModeStructure.PWM_CHn_PDMR = PWM_CHn_PDMR_Periodic; - - PWM_TimerModeInit(obj->PWM_CHx, &TimerModeStructure); - PWM_CtrlPWMOutputEnable(obj->PWM_CHx); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float value = (float)(2 * us) / (float)obj->period; - pwmout_write(obj, value); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/serial_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/serial_api.c deleted file mode 100644 index f7c395da72a..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/serial_api.c +++ /dev/null @@ -1,445 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "W7500x_uart.h" - -#define UART_NUM (3) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; - - -static uart_irq_handler irq_handler; -static UART_TypeDef *UART; - - -UART_InitTypeDef UART_InitStructure; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - if(obj->index == 2) // For UART2, It is simple UART. - { - SystemCoreClockUpdate(); - //S_UART_Init(obj->baudrate); - S_UART_SetCTRL((S_UART_CTRL_RX_EN|S_UART_CTRL_TX_EN), DISABLE); - S_UART_SetBaud(obj->baudrate); - - if(obj->pin_rx == NC) - { - S_UART_SetCTRL(S_UART_CTRL_TX_EN, ENABLE); - } - else if(obj->pin_tx == NC) - { - S_UART_SetCTRL(S_UART_CTRL_RX_EN, ENABLE); - } - else - { - S_UART_SetCTRL((S_UART_CTRL_TX_EN|S_UART_CTRL_RX_EN),ENABLE); - } - } - else // For UART0 and UART1. - { - UART = (UART_TypeDef *)(obj->uart); - UART_InitStructure.UART_BaudRate = obj->baudrate; - UART_InitStructure.UART_WordLength = obj->databits; - UART_InitStructure.UART_StopBits = obj->stopbits; - UART_InitStructure.UART_Parity = obj->parity; - UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; - - - if (obj->pin_rx == NC) { - UART_InitStructure.UART_Mode = UART_Mode_Tx; - } else if (obj->pin_tx == NC) { - UART_InitStructure.UART_Mode = UART_Mode_Rx; - } else { - UART_InitStructure.UART_Mode = (UART_Mode_Rx | UART_Mode_Tx); - } - - UART_Init(UART,&UART_InitStructure); - } -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock - if (obj->uart == UART_0) { - obj->index = 0; - } - - if (obj->uart == UART_1) { - obj->index = 1; - } - - if (obj->uart == UART_2) { - obj->index = 2; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WordLength_8b; - obj->stopbits = UART_StopBits_1; - obj->parity = UART_Parity_No; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_0) { - } - - if (obj->uart == UART_1) { - } - if (obj->uart == UART_2) { - } - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 7) { - obj->databits = UART_WordLength_7b; - } else { - obj->databits = UART_WordLength_8b; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_Parity_Odd; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_Parity_Even; - break; - default: // ParityNone - obj->parity = UART_Parity_No; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_StopBits_2; - } else { - obj->stopbits = UART_StopBits_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UART = (UART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if( UART_GetITStatus(UART,UART_IT_FLAG_TXI) != RESET ){ - irq_handler(serial_irq_ids[id], TxIrq); - UART_ClearITPendingBit(UART,UART_IT_FLAG_TXI); - } - if( UART_GetITStatus(UART,UART_IT_FLAG_RXI) != RESET ){ - irq_handler(serial_irq_ids[id], RxIrq); - } - } -} - -static void uart2_irq() -{ - if(serial_irq_ids[2] != 0){ - if( S_UART_GetITStatus(S_UART_INTSTATUS_TXI) != RESET ){ - S_UART_ClearITPendingBit(S_UART_INTSTATUS_TXI); - irq_handler(serial_irq_ids[2], TxIrq); - } - if( S_UART_GetITStatus(S_UART_INTSTATUS_RXI) != RESET ) { - S_UART_ClearITPendingBit(S_UART_INTSTATUS_RXI); - irq_handler(serial_irq_ids[2], RxIrq); - } - } -} - -#ifdef __cplusplus -extern "C"{ -#endif -void UART0_Handler() -{ - uart_irq(UART_0, 0); -} - -void UART1_Handler() -{ - uart_irq(UART_1, 1); -} - -void UART2_Handler() -{ - uart2_irq(); -} -#ifdef __cplusplus -} -#endif - - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - - if (obj->uart == UART_2) - { - irq_n = UART2_IRQn; - - if (enable){ - if (irq == RxIrq){ - S_UART_ITConfig(S_UART_CTRL_RXI,ENABLE); - } else { - S_UART_ITConfig(S_UART_CTRL_TXI,ENABLE); - } - NVIC_ClearPendingIRQ(irq_n); - NVIC_EnableIRQ(irq_n); - } else { // disable - S_UART_ITConfig((S_UART_CTRL_RXI|S_UART_CTRL_TXI),DISABLE); - NVIC_DisableIRQ(irq_n); - } - } - else - { - UART = (UART_TypeDef *)(obj->uart); - - if (obj->uart == UART_0) { - irq_n = UART0_IRQn; - } - - if (obj->uart == UART_1) { - irq_n = UART1_IRQn; - } - - if (enable) { - if (irq == RxIrq) { - UART_ITConfig(UART,UART_IT_FLAG_RXI,ENABLE); - } else { // TxIrq - UART_ITConfig(UART,UART_IT_FLAG_TXI,ENABLE); - } - - NVIC_ClearPendingIRQ(irq_n); - NVIC_EnableIRQ(irq_n); - } else { // disable - UART_ITConfig(UART,(UART_IT_FLAG_RXI|UART_IT_FLAG_TXI),DISABLE); - NVIC_DisableIRQ(irq_n); - } - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - if (obj->uart == UART_2) - { - S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart); - - while( (uart->STATE & S_UART_STATE_RX_BUF_FULL) == 0 ); - return (uint16_t)(uart->DATA); - } - else - { - UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); - while(uart->FR & UART_FR_RXFE); - - return (uart->DR & 0xFF); - } -} - -void serial_putc(serial_t *obj, int c) -{ - if (obj->uart == UART_2) - { - S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart); - - while(uart->STATE & S_UART_STATE_TX_BUF_FULL); - uart->DATA = (uint32_t)(c & (uint16_t)0xFF); - } - else - { - UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); - - uart->DR = (uint32_t)(c & (uint16_t)0xFF); - while(uart->FR & UART_FR_BUSY); - } -} - -int serial_readable(serial_t *obj) -{ - int status; - - if (obj->uart == UART_2) - { - S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart); - status = ((uart->STATE & S_UART_STATE_RX_BUF_FULL) ? 1 : 0); - } - else - { - UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); - // Check if data is received - status = ((uart->FR & UART_FR_RXFE) ? 0: 1); - } - - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - - if (obj->uart == UART_2) - { - S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart); - status = ((uart->STATE & S_UART_STATE_TX_BUF_FULL) ? 0 : 1); - } - else - { - UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((uart->FR & UART_FR_BUSY) ? 0: 1); - } - return status; -} - -void serial_clear(serial_t *obj) -{ -// UartHandle.Instance = (USART_TypeDef *)(obj->uart); -// __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); -// __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - //pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - // [TODO] -} - -void serial_break_clear(serial_t *obj) -{ - // [TODO] -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} - -#endif diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/sleep.c b/targets/TARGET_WIZNET/TARGET_W7500x/sleep.c deleted file mode 100644 index acd0030bcef..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/sleep.c +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "mbed_interface.h" - -void hal_sleep(void) -{ - // To Do -} - -void hal_deepsleep(void) -{ - // To Do -} diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/spi_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/spi_api.c deleted file mode 100644 index 6fef99b672e..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/spi_api.c +++ /dev/null @@ -1,257 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "mbed_assert.h" -#include - -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -static inline int ssp_disable(spi_t *obj); -static inline int ssp_enable(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - obj->spi = (SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->spi != NC); - - // enable power and clocking - switch ((int)obj->spi) { - case SPI_0: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; //PLL output clock - case SPI_1: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; - } - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) {} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - ssp_disable(obj); - MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3)); - - int polarity = (mode & 0x2) ? 1 : 0; - int phase = (mode & 0x1) ? 1 : 0; - - // set it up - int DSS = bits - 1; // DSS (data select size) - int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity - int SPH = (phase) ? 1 : 0; // SPH - clock out phase - - int FRF = 0; // FRF (frame format) = SPI - uint32_t tmp = obj->spi->CR0; - tmp &= ~(0xFFFF); - tmp |= DSS << 0 - | FRF << 4 - | SPO << 6 - | SPH << 7; - obj->spi->CR0 = tmp; - - tmp = obj->spi->CR1; - tmp &= ~(0xD); - tmp |= 0 << 0 // LBM - loop back mode - off - | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave - | 0 << 3; // SOD - slave output disable - na - obj->spi->CR1 = tmp; - - ssp_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - ssp_disable(obj); - - // setup the spi clock diveder to /1 - switch ((int)obj->spi) { - case SPI_0: - CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass) - break; - case SPI_1: - CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass) - break; - } - - uint32_t HCLK = SystemCoreClock; - - int prescaler; - - for (prescaler = 2; prescaler <= 254; prescaler += 2) { - int prescale_hz = HCLK / prescaler; - - // calculate the divider - int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); - - // check we can support the divider - if (divider < 256) { - // prescaler - obj->spi->CPSR = prescaler; - - // divider - obj->spi->CR0 &= ~(0xFFFF << 8); - obj->spi->CR0 |= (divider - 1) << 8; - ssp_enable(obj); - return; - } - } - error("Couldn't setup requested SPI frequency"); -} - -static inline int ssp_disable(spi_t *obj) { - return obj->spi->CR1 &= ~(1 << 1); -} - -static inline int ssp_enable(spi_t *obj) { - return obj->spi->CR1 |= (1 << 1); -} - -static inline int ssp_readable(spi_t *obj) { - return obj->spi->SR & (1 << 2); -} - -static inline int ssp_writeable(spi_t *obj) { - return obj->spi->SR & (1 << 1); -} - -static inline void ssp_write(spi_t *obj, int value) { - while (!ssp_writeable(obj)); - obj->spi->DR = value; -} - -static inline int ssp_read(spi_t *obj) { - while (!ssp_readable(obj)); - return obj->spi->DR; -} - -static inline int ssp_busy(spi_t *obj) { - return (obj->spi->SR & (1 << 4)) ? (1) : (0); -} - -int spi_master_write(spi_t *obj, int value) { - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive(spi_t *obj) { - return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); -} - -int spi_slave_read(spi_t *obj) { - return obj->spi->DR; -} - -void spi_slave_write(spi_t *obj, int value) { - while (ssp_writeable(obj) == 0) ; - obj->spi->DR = value; -} - -int spi_busy(spi_t *obj) { - return ssp_busy(obj); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/us_ticker.c b/targets/TARGET_WIZNET/TARGET_W7500x/us_ticker.c deleted file mode 100644 index 14232d33c9b..00000000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/us_ticker.c +++ /dev/null @@ -1,137 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" -#include "system_W7500x.h" -#include "W7500x_dualtimer.h" -#include "W7500x_pwm.h" - -#define TIMER_0 DUALTIMER0_0 -#define TIMER_1 PWM_CH1 -#define TIMER_IRQn DUALTIMER0_IRQn - -static PWM_TimerModeInitTypeDef TimerInitType; -static DUALTIMER_InitTypDef TimerHandler; - -static int us_ticker_inited = 0; - - -#ifdef __cplusplus -extern "C"{ -#endif - -void DUALTIMER0_Handler(void) -{ - DUALTIMER_IntClear(DUALTIMER0_0); - us_ticker_irq_handler(); -} - -#ifdef __cplusplus -} -#endif - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - SystemCoreClockUpdate(); - TimerInitType.PWM_CHn_PR = (GetSystemClock() / 1000000) -1; - TimerInitType.PWM_CHn_LR = 0xFFFFFFFF; - TimerInitType.PWM_CHn_PDMR = 1; - - PWM_TimerModeInit(TIMER_1, &TimerInitType); - PWM_CHn_Start(TIMER_1); -} - - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) us_ticker_init(); - return (TIMER_1->TCR); -} - - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - int32_t dev = 0; - - if (!us_ticker_inited) - { - us_ticker_init(); - } - - dev = (int32_t)(timestamp - us_ticker_read()); - dev = dev * ((GetSystemClock() / 1000000) / 16); - - DUALTIMER_ClockEnable(TIMER_0); - DUALTIMER_Stop(TIMER_0); - - TimerHandler.TimerControl_Mode = DUALTIMER_TimerControl_Periodic; - TimerHandler.TimerControl_OneShot = DUALTIMER_TimerControl_OneShot; - TimerHandler.TimerControl_Pre = DUALTIMER_TimerControl_Pre_16; - TimerHandler.TimerControl_Size = DUALTIMER_TimerControl_Size_32; - - TimerHandler.TimerLoad = (uint32_t)dev; - - DUALTIMER_Init(TIMER_0, &TimerHandler); - - DUALTIMER_IntConfig(TIMER_0, ENABLE); - - NVIC_EnableIRQ(TIMER_IRQn); - - DUALTIMER_Start(TIMER_0); - - -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(TIMER_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - NVIC_DisableIRQ(TIMER_IRQn); - - DUALTIMER_IntConfig(TIMER_0, DISABLE); -} - -void us_ticker_clear_interrupt(void) -{ - DUALTIMER_IntClear(TIMER_0); -} - -void us_ticker_free(void) -{ - -} diff --git a/targets/TARGET_WIZNET/mbed_rtx.h b/targets/TARGET_WIZNET/mbed_rtx.h deleted file mode 100644 index bf8630cbab7..00000000000 --- a/targets/TARGET_WIZNET/mbed_rtx.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - -#if defined(TARGET_WIZWIKI_W7500) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20004000UL) -#endif - -#elif defined(TARGET_WIZWIKI_W7500P) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20004000UL) -#endif - - -#elif defined(TARGET_WIZWIKI_W7500ECO) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x20004000UL) -#endif - -#endif // - -#endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index b50531dc971..3605fbf6a0b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3992,7 +3992,7 @@ "device_name": "STM32F412ZG", "bootloader_supported": true }, - "MTB_MXCHIP_EMW3166": { + "WIO_EMW3166": { "inherits": [ "FAMILY_STM32" ], @@ -4223,42 +4223,6 @@ ], "device_name": "STM32F413ZH" }, - "ELMO_F411RE": { - "inherits": [ - "FAMILY_STM32" - ], - "supported_form_factors": [ - "ARDUINO" - ], - "core": "Cortex-M4F", - "default_toolchain": "uARM", - "extra_labels_add": [ - "STM32F4", - "STM32F411xE" - ], - "macros_add": [ - "STM32F411xE" - ], - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM" - ], - "detect_code": [ - "0410" - ], - "device_has_add": [ - "MPU" - ], - "device_has_remove": [ - "SERIAL_FC" - ], - "default_lib": "small", - "release_versions": [ - "2" - ], - "device_name": "STM32F411RE" - }, "NUCLEO_F429ZI": { "inherits": [ "FAMILY_STM32" @@ -5545,45 +5509,6 @@ "device_name": "STM32L476RG", "bootloader_supported": true }, - "SILICA_SENSOR_NODE": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M4F", - "default_toolchain": "GCC_ARM", - "extra_labels_add": [ - "STM32L4", - "STM32L476xG", - "STM32L476JG" - ], - "config": { - "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", - "value": "USE_PLL_MSI", - "macro_name": "CLOCK_SOURCE" - } - }, - "detect_code": [ - "0766" - ], - "macros_add": [ - "STM32L476xx", - "USBHOST_OTHER" - ], - "device_has_add": [ - "ANALOGOUT", - "CAN", - "CRC", - "SERIAL_ASYNCH", - "TRNG", - "FLASH", - "MPU" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32L476JG" - }, "NUCLEO_L486RG": { "inherits": [ "FAMILY_STM32" @@ -7099,136 +7024,6 @@ ], "device_name": "STM32F401VC" }, - "MODULE_UBLOX_ODIN_W2": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M4F", - "extra_labels_add": [ - "STM32F4", - "STM32F439xI", - "CORDIO", - "CORDIO_ODIN_W2" - ], - "macros_add": [ - "STM32F439xx", - "MBEDTLS_CONFIG_HW_SUPPORT", - "HSE_VALUE=24000000", - "HSE_STARTUP_TIMEOUT=5000", - "CB_INTERFACE_SDIO", - "CB_CHIP_WL18XX", - "SUPPORT_80211D_ALWAYS", - "WLAN_ENABLED", - "CB_FEATURE_802DOT11W", - "CB_FEATURE_802DOT11R", - "CB_FEATURE_PMKCACHING", - "MBEDTLS_ARC4_C", - "MBEDTLS_DES_C", - "MBEDTLS_MD4_C", - "MBEDTLS_MD5_C", - "MBEDTLS_SHA1_C", - "MBED_MPU_CUSTOM" - ], - "device_has_add": [ - "CAN", - "EMAC", - "TRNG", - "FLASH", - "WIFI", - "SERIAL" - ], - "features": [ - "BLE" - ], - "device_has_remove": [], - "device_name": "STM32F439ZI", - "public": false, - "bootloader_supported": true, - "config": { - "BLE_STACK_UBX": { - "help": "It should be set to true to enable ublox ODIN own stack/driver rather than CORDIO", - "value": false, - "macro_name": "BLE_STACK_UBX" - } - }, - "overrides": { - "network-default-interface-type": "WIFI" - } - }, - "UBLOX_EVK_ODIN_W2": { - "inherits": [ - "MODULE_UBLOX_ODIN_W2" - ], - "supported_form_factors": [ - "ARDUINO" - ], - "device_has_remove": [], - "extra_labels_add": [ - "PSA" - ], - "components_add": [ - "SD", - "FLASHIAP" - ], - "config": { - "stdio_uart_tx_help": { - "help": "Value: D8(default) or D1" - }, - "stdio_uart_rx_help": { - "help": "Value: D2(default) or D0" - } - }, - "overrides": { - "stdio_uart_tx": "D8", - "stdio_uart_rx": "D2" - }, - "detect_code": [ - "1236" - ] - }, - "MBED_CONNECT_ODIN": { - "inherits": [ - "MODULE_UBLOX_ODIN_W2" - ], - "config": { - "stdio_uart_tx_help": { - "help": "Value: PA_9(default) or PD_8" - }, - "stdio_uart_rx_help": { - "help": "Value: PA_10(default) or PD_9" - } - }, - "overrides": { - "stdio_uart_tx": "PA_9", - "stdio_uart_rx": "PA_10" - }, - "detect_code": [ - "2410" - ] - }, - "MTB_UBLOX_ODIN_W2": { - "inherits": [ - "MODULE_UBLOX_ODIN_W2" - ], - "overrides": { - "lse_available": 0 - }, - "detect_code": [ - "0450" - ] - }, - "OKDO_ODIN_W2": { - "inherits": [ - "MODULE_UBLOX_ODIN_W2" - ], - "device_has_remove": [], - "overrides": { - "lse_available": 0 - }, - "detect_code": [ - "1280" - ] - }, "UBLOX_C030": { "inherits": [ "FAMILY_STM32" @@ -9006,26 +8801,6 @@ "5500" ] }, - "VK_RZ_A1H": { - "inherits": [ - "RZ_A1XX" - ], - "extra_labels_add": [ - "RZA1H", - "VKRZA1H", - "RZ_A1_EMAC" - ], - "device_has_add": [ - "EMAC" - ], - "release_versions": [ - "2", - "5" - ], - "detect_code": [ - "C002" - ] - }, "GR_LYCHEE": { "inherits": [ "RZ_A1XX" @@ -10546,29 +10321,77 @@ "2042" ] }, - "WIZWIKI_W7500": { - "supported_form_factors": [ - "ARDUINO" + "MCU_NRF51_UNIFIED": { + "inherits": [ + "Target" ], "core": "Cortex-M0", - "extra_labels": [ - "WIZNET", - "W7500x", - "WIZwiki_W7500" - ], + "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex", "macros": [ + "BOARD_PCA10028", + "NRF51", + "TARGET_NRF51822", + "BLE_STACK_SUPPORT_REQD", + "SOFTDEVICE_PRESENT", + "S130", + "TARGET_MCU_NRF51822", "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" + "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", + "NO_SYSTICK", + "MBED_TICKLESS" + ], + "MERGE_BOOTLOADER": false, + "extra_labels": [ + "NORDIC", + "MCU_NRF51", + "MCU_NRF51822_UNIFIED", + "NRF5x", + "NRF51", + "SDK_11", + "NORDIC_SOFTDEVICE" ], + "OUTPUT_EXT": "hex", + "is_disk_virtual": true, "supported_toolchains": [ - "uARM", "ARM", "GCC_ARM", "IAR" ], - "inherits": [ - "Target" + "public": false, + "MERGE_SOFT_DEVICE": true, + "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [ + { + "boot": "", + "name": "s130_nrf51_2.0.0_softdevice.hex", + "offset": 110592 + } + ], + "detect_code": [ + "1070" + ], + "post_binary_hook": { + "function": "MCU_NRF51Code.binary_hook", + "toolchains": [ + "ARM_STD", + "GCC_ARM", + "IAR" + ] + }, + "program_cycle_s": 6, + "features": [ + "BLE" ], + "config": { + "lf_clock_src": { + "value": "NRF_LF_SRC_XTAL", + "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC" + }, + "uart_hwfc": { + "help": "Value: 1 for enable, 0 for disable", + "value": 1, + "macro_name": "MBED_CONF_NORDIC_UART_HWFC" + } + }, "device_has": [ "ANALOGIN", "I2C", @@ -10578,441 +10401,19 @@ "PORTOUT", "PWMOUT", "SERIAL", + "SLEEP", "SPI", - "SPISLAVE", - "STDIO_MESSAGES", - "USTICKER" - ], - "release_versions": [ - "2", - "5" - ], - "detect_code": [ - "2201" + "SPISLAVE" ] }, - "WIZWIKI_W7500P": { - "supported_form_factors": [ - "ARDUINO" + "MCU_NRF51_16K_UNIFIED_S130": { + "inherits": [ + "MCU_NRF51_UNIFIED" ], - "core": "Cortex-M0", - "extra_labels": [ - "WIZNET", - "W7500x", - "WIZwiki_W7500P" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "uARM", - "ARM", - "GCC_ARM", - "IAR" - ], - "inherits": [ - "Target" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SPI", - "SPISLAVE", - "STDIO_MESSAGES", - "USTICKER" - ], - "release_versions": [ - "2", - "5" - ], - "detect_code": [ - "2203" - ] - }, - "WIZWIKI_W7500ECO": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0", - "extra_labels": [ - "WIZNET", - "W7500x", - "WIZwiki_W7500ECO" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "uARM", - "ARM", - "GCC_ARM", - "IAR" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SPI", - "SPISLAVE", - "STDIO_MESSAGES", - "USTICKER" - ], - "release_versions": [ - "2", - "5" - ], - "detect_code": [ - "2202" - ] - }, - "SAMR21G18A": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0+", - "macros": [ - "__SAMR21G18A__", - "I2C_MASTER_CALLBACK_MODE=true", - "EXTINT_CALLBACK_MODE=true", - "USART_CALLBACK_MODE=true", - "TC_ASYNC=true" - ], - "extra_labels": [ - "Atmel", - "SAM_CortexM0P", - "SAMR21" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARMC5", - "uARM" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "RESET_REASON", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPISLAVE", - "SPI_ASYNCH" - ], - "release_versions": [ - "2" - ], - "device_name": "ATSAMR21G18A", - "detect_code": [ - "0900" - ] - }, - "SAMD21J18A": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0+", - "macros": [ - "__SAMD21J18A__", - "I2C_MASTER_CALLBACK_MODE=true", - "EXTINT_CALLBACK_MODE=true", - "USART_CALLBACK_MODE=true", - "TC_ASYNC=true" - ], - "extra_labels": [ - "Atmel", - "SAM_CortexM0P", - "SAMD21" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARMC5", - "uARM" - ], - "device_has": [ - "ANALOGIN", - "ANALOGOUT", - "I2C", - "I2CSLAVE", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPISLAVE", - "SPI_ASYNCH" - ], - "release_versions": [ - "2" - ], - "device_name": "ATSAMD21J18A", - "detect_code": [ - "0915" - ] - }, - "SAMD21G18A": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0+", - "macros": [ - "__SAMD21G18A__", - "I2C_MASTER_CALLBACK_MODE=true", - "EXTINT_CALLBACK_MODE=true", - "USART_CALLBACK_MODE=true", - "TC_ASYNC=true" - ], - "extra_labels": [ - "Atmel", - "SAM_CortexM0P", - "SAMD21" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARMC5", - "uARM" - ], - "device_has": [ - "ANALOGIN", - "ANALOGOUT", - "I2C", - "I2CSLAVE", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPISLAVE", - "SPI_ASYNCH" - ], - "release_versions": [ - "2" - ], - "device_name": "ATSAMD21G18A", - "detect_code": [ - "0905" - ] - }, - "SAML21J18A": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0+", - "macros": [ - "__SAML21J18A__", - "I2C_MASTER_CALLBACK_MODE=true", - "EXTINT_CALLBACK_MODE=true", - "USART_CALLBACK_MODE=true", - "TC_ASYNC=true" - ], - "extra_labels": [ - "Atmel", - "SAM_CortexM0P", - "SAML21" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARMC5", - "uARM" - ], - "device_has": [ - "ANALOGIN", - "ANALOGOUT", - "I2C", - "I2CSLAVE", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPISLAVE", - "SPI_ASYNCH" - ], - "device_name": "ATSAML21J18A", - "detect_code": [ - "0910" - ] - }, - "SAMG55J19": { - "inherits": [ - "Target" - ], - "core": "Cortex-M4F", - "extra_labels": [ - "Atmel", - "SAM_CortexM4", - "SAMG55" - ], - "macros": [ - "__SAMG55J19__", - "BOARD=75", - "I2C_MASTER_CALLBACK_MODE=true", - "EXTINT_CALLBACK_MODE=true", - "USART_CALLBACK_MODE=true", - "TC_ASYNC=true" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "uARM" - ], - "default_toolchain": "ARM", - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPISLAVE", - "SPI_ASYNCH", - "MPU" - ], - "default_lib": "std", - "device_name": "ATSAMG55J19", - "detect_code": [ - "0920" - ] - }, - "MCU_NRF51_UNIFIED": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0", - "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex", - "macros": [ - "BOARD_PCA10028", - "NRF51", - "TARGET_NRF51822", - "BLE_STACK_SUPPORT_REQD", - "SOFTDEVICE_PRESENT", - "S130", - "TARGET_MCU_NRF51822", - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", - "NO_SYSTICK", - "MBED_TICKLESS" - ], - "MERGE_BOOTLOADER": false, - "extra_labels": [ - "NORDIC", - "MCU_NRF51", - "MCU_NRF51822_UNIFIED", - "NRF5x", - "NRF51", - "SDK_11", - "NORDIC_SOFTDEVICE" - ], - "OUTPUT_EXT": "hex", - "is_disk_virtual": true, - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "public": false, - "MERGE_SOFT_DEVICE": true, - "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [ - { - "boot": "", - "name": "s130_nrf51_2.0.0_softdevice.hex", - "offset": 110592 - } - ], - "detect_code": [ - "1070" - ], - "post_binary_hook": { - "function": "MCU_NRF51Code.binary_hook", - "toolchains": [ - "ARM_STD", - "GCC_ARM", - "IAR" - ] - }, - "program_cycle_s": 6, - "features": [ - "BLE" - ], - "config": { - "lf_clock_src": { - "value": "NRF_LF_SRC_XTAL", - "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC" - }, - "uart_hwfc": { - "help": "Value: 1 for enable, 0 for disable", - "value": 1, - "macro_name": "MBED_CONF_NORDIC_UART_HWFC" - } - }, - "device_has": [ - "ANALOGIN", - "I2C", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ] - }, - "MCU_NRF51_16K_UNIFIED_S130": { - "inherits": [ - "MCU_NRF51_UNIFIED" - ], - "extra_labels_add": [ - "MCU_NORDIC_16K", - "MCU_NRF51_16K_S130", - "MCU_NRF51_16K" + "extra_labels_add": [ + "MCU_NORDIC_16K", + "MCU_NRF51_16K_S130", + "MCU_NRF51_16K" ], "macros_add": [ "TARGET_MCU_NORDIC_16K", @@ -12136,166 +11537,6 @@ "SARA_NBIOT" ] }, - "MCU_RTL8195A": { - "core": "Cortex-M3", - "default_toolchain": "GCC_ARM", - "macros": [ - "__RTL8195A__", - "CONFIG_PLATFORM_8195A", - "CONFIG_MBED_ENABLED", - "PLATFORM_CMSIS_RTOS", - "MBED_FAULT_HANDLER_DISABLED", - "MBED_MPU_CUSTOM" - ], - "inherits": [ - "Target" - ], - "extra_labels": [ - "Realtek", - "AMEBA", - "RTW_EMAC" - ], - "device_has": [ - "ANALOGIN", - "ANALOGOUT", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SPI", - "TRNG", - "FLASH", - "USTICKER" - ], - "public": false, - "supported_toolchains": [ - "GCC_ARM", - "ARM" - ], - "post_binary_hook": { - "function": "RTL8195ACode.binary_hook", - "toolchains": [ - "ARM_STD", - "GCC_ARM" - ] - }, - "release_versions": [], - "overrides": { - "network-default-interface-type": "WIFI" - } - }, - "REALTEK_RTL8195AM": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_RTL8195A" - ], - "detect_code": [ - "4600" - ], - "extra_labels_add": [ - "RTL8195A" - ] - }, - "VBLUNO51_LEGACY": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF51_32K" - ], - "detect_code": [ - "C006" - ], - "overrides": { - "uart_hwfc": 0 - }, - "extra_labels_add": [ - "VBLUNO51" - ] - }, - "VBLUNO51_BOOT": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF51_32K_BOOT" - ], - "detect_code": [ - "C006" - ], - "overrides": { - "uart_hwfc": 0 - }, - "extra_labels_add": [ - "VBLUNO51" - ], - "macros_add": [ - "TARGET_VBLUNO51" - ] - }, - "VBLUNO51_OTA": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF51_32K_OTA" - ], - "detect_code": [ - "C006" - ], - "overrides": { - "uart_hwfc": 0 - }, - "extra_labels_add": [ - "VBLUNO51" - ], - "macros_add": [ - "TARGET_VBLUNO51" - ] - }, - "VBLUNO51": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF51_32K_UNIFIED" - ], - "detect_code": [ - "C006" - ], - "overrides": { - "uart_hwfc": 0 - }, - "device_has": [ - "USTICKER", - "LPTICKER", - "ANALOGIN", - "I2C", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPI_ASYNCH", - "SPISLAVE" - ], - "release_versions": [ - "2" - ], - "device_name": "nRF51822_xxAC" - }, "DISCO_L496AG": { "inherits": [ "FAMILY_STM32" @@ -12695,38 +11936,6 @@ "mbed_ram_size": "0x40000", "release_versions": [ "5" ] }, - "VBLUNO52": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF52832" - ], - "release_versions": [ - "5" - ], - "device_name": "nRF52832_xxAA", - "macros_add": [ - "CONFIG_GPIO_AS_PINRESET", - "NRF52_PAN_12", - "NRF52_PAN_15", - "NRF52_PAN_20", - "NRF52_PAN_30", - "NRF52_PAN_31", - "NRF52_PAN_36", - "NRF52_PAN_51", - "NRF52_PAN_53", - "NRF52_PAN_54", - "NRF52_PAN_55", - "NRF52_PAN_58", - "NRF52_PAN_62", - "NRF52_PAN_63", - "NRF52_PAN_64" - ], - "overrides": { - "console-uart-flow-control": "RTSCTS" - } - }, "MCU_M480": { "core": "Cortex-M4F", "default_toolchain": "ARM", @@ -14261,86 +13470,28 @@ "PORTOUT", "PWMOUT", "RESET_REASON", - "RTC", - "SERIAL", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPI_ASYNCH", - "SPISLAVE", - "I2C", - "I2C_ASYNCH", - "I2CSLAVE", - "STDIO_MESSAGES", - "FLASH", - "MPU" - ], - "device_name": "TMPM3HQFDFG", - "detect_code": [ - "7014" - ], - "release_versions": [ - "5" - ] - }, - "RDA5981X": { - "inherits": [ - "Target" - ], - "core": "Cortex-M4F", - "public": true, - "extra_labels": [ - "RDA", - "UNO_91H", - "FLASH_CMSIS_ALGO", - "RDA_EMAC" - ], - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "macros": [ - "CMSIS_NVIC_VIRTUAL", - "CMSIS_NVIC_VIRTUAL_HEADER_FILE=\"RDA5981_nvic_virtual.h\"" - ], - "device_has": [ - "USTICKER", - "PORTIN", - "PORTOUT", - "PORTINOUT", - "INTERRUPTIN", - "EMAC", + "RTC", "SERIAL", "SERIAL_FC", - "STDIO_MESSAGES", - "PWMOUT", - "SPI", "SLEEP", - "ANALOGIN", + "SPI", + "SPI_ASYNCH", + "SPISLAVE", + "I2C", + "I2C_ASYNCH", + "I2CSLAVE", + "STDIO_MESSAGES", "FLASH", - "TRNG" + "MPU" + ], + "device_name": "TMPM3HQFDFG", + "detect_code": [ + "7014" ], "release_versions": [ - "2", "5" ] }, - "UNO_91H": { - "inherits": [ - "RDA5981X" - ], - "detect_code": [ - "8001" - ], - "components_add": [ - "FLASHIAP" - ], - "overrides": { - "network-default-interface-type": "WIFI" - }, - "bootloader_supported": false - }, "GD32_Target": { "inherits": [ "Target" @@ -14406,48 +13557,6 @@ "network-default-interface-type": "ETHERNET" } }, - "TT_M3HQ": { - "inherits": [ - "Target" - ], - "core": "Cortex-M3", - "is_disk_virtual": true, - "extra_labels": [ - "TT" - ], - "macros": [ - "__TT_M3HQ__" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "device_has": [ - "ANALOGIN", - "USTICKER", - "ANALOGOUT", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "I2C", - "I2CSLAVE", - "STDIO_MESSAGES", - "MPU" - ], - "device_name": "TMPM3HQFDFG", - "detect_code": [ - "8012" - ], - "release_versions": [ - "5" - ] - }, "GD32_F450ZI": { "inherits": [ "GD32_Target" @@ -14496,85 +13605,6 @@ "network-default-interface-type": "ETHERNET" } }, - "GD32_E103VB": { - "inherits": [ - "GD32_Target" - ], - "supported_form_factors": [ - "ARDUINO" - ], - "core": "Cortex-M4F", - "extra_labels_add": [ - "GD32E10X", - "GD32E103VB" - ], - "device_has_add": [ - "RTC", - "I2C", - "CAN", - "I2CSLAVE", - "ANALOGOUT", - "SPI", - "SPISLAVE", - "SERIAL_ASYNCH", - "SERIAL_FC", - "FLASH", - "SLEEP" - ], - "detect_code": [ - "1703" - ], - "macros_add": [ - "GD32E10X" - ], - "release_versions": [ - "5" - ] - }, - "TT_M4G9": { - "inherits": [ - "Target" - ], - "core": "Cortex-M4F", - "is_disk_virtual": true, - "extra_labels": [ - "TT" - ], - "macros": [ - "__TT_M4G9__" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "device_has": [ - "USTICKER", - "ANALOGIN", - "ANALOGOUT", - "SERIAL", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SLEEP", - "SPI", - "STDIO_MESSAGES", - "FLASH", - "MPU" - ], - "device_name": "TMPM4G9F15FG", - "detect_code": [ - "8013" - ], - "release_versions": [ - "5" - ], - "bootloader_supported": true - }, "EP_AGORA": { "inherits": [ "MCU_NRF52840" @@ -14624,177 +13654,6 @@ ], "device_name": "STM32L151CBxxA" }, - "TI": { - "inherits": [ - "Target" - ], - "public": false, - "extra_labels": [ - "TI" - ] - }, - "CC32XX": { - "inherits": [ - "TI" - ], - "public": false, - "release_versions": [ - "5" - ] - }, - "CC3220SF": { - "inherits": [ - "CC32XX" - ], - "public": false, - "macros": [ - "MBED_MPU_CUSTOM" - ], - "core": "Cortex-M4", - "device_name": "CC3220SF" - }, - "CC3220SF_LAUNCHXL": { - "inherits": [ - "CC3220SF" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "components_add": [ - "SD", - "FLASHIAP" - ], - "device_has": [ - "USTICKER", - "SERIAL", - "SERIAL_FC", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "INTERRUPTIN", - "SPI", - "ANALOGIN", - "FLASH", - "TRNG", - "RTC" - ], - "bootloader_supported": true, - "overrides": { - "network-default-interface-type": "WIFI" - } - }, - "MSP432": { - "inherits": [ - "TI" - ], - "core": "Cortex-M4F", - "public": false, - "extra_labels": [ - "MSP432" - ], - "macros": [ - "MBED_MPU_CUSTOM" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "config": { - "hfxt_hz": { - "help": "Defines the HFXT frequency in Hz (e.g. 48000000)", - "value": null - }, - "lfxt_hz": { - "help": "Defines the LFXT frequency in Hz (e.g. 32768)", - "value": null - }, - "dco_rsel": { - "help": "Defines the DCO center frequency (3/6/12/24/48 MHz)", - "accepted_values": "DCO_1500kHz|DCO_3MHz|DCO_6MHz|DCO_12MHz|DCO_24MHz|DCO_48MHz", - "value": "DCO_3MHz" - }, - "dco_tune": { - "help": "Defines the DCO tuning value (-512...511)", - "value": 0 - }, - "mclk_select": { - "help": "Selects the MCLK source", - "accepted_values": "LFXT, VLO, REFO, DCO, MOD, HFXT", - "value": "DCO" - }, - "mclk_div": { - "help": "Selects the MCLK divider (1/2/4/8/16/32/64/128)", - "accepted_values": "DIV1, DIV2, DIV4, DIV8, DIV16, DIV32, DIV64, DIV128", - "value": "DIV1" - }, - "smclk_select": { - "help": "Selects the SMCLK source", - "accepted_values": "LFXT, VLO, REFO, DCO, MOD, HFXT", - "value": "DCO" - }, - "smclk_div": { - "help": "Selects the SMCLK divider (1/2/4/8/16/32/64/128)", - "accepted_values": "DIV1, DIV2, DIV4, DIV8, DIV16, DIV32, DIV64, DIV128", - "value": "DIV1" - }, - "adc_auto_scan": { - "help": "Enables automatic conversion of all ADC channels", - "value": 0 - } - }, - "device_has": [ - "ANALOGIN", - "I2C", - "I2C_ASYNCH", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SPI", - "SPI_ASYNCH", - "SPISLAVE", - "STDIO_MESSAGES", - "USTICKER" - ] - }, - "MSP432P401R": { - "inherits": [ - "MSP432" - ], - "extra_labels_add": [ - "MSP432P401R" - ], - "macros_add": [ - "__MSP432P401R__" - ], - "device_name": "MSP432P401R" - }, - "MSP432_LAUNCHPAD": { - "inherits": [ - "MSP432P401R" - ], - "supported_form_factors": [ - "LAUNCHPAD_40" - ], - "overrides": { - "hfxt_hz": 48000000, - "mclk_select": "HFXT", - "smclk_select": "HFXT", - "smclk_div": "DIV2", - "adc_auto_scan": 1 - }, - "release_versions": [ - "2", - "5" - ] - }, "MCU_M261": { "core": "Cortex-M23", "default_toolchain": "ARMC6", diff --git a/tools/test/config/config_test.py b/tools/test/config/config_test.py index 5f999c7e70c..12ff3e5ea86 100644 --- a/tools/test/config/config_test.py +++ b/tools/test/config/config_test.py @@ -203,7 +203,7 @@ def test_init_override_app_config(target): mock_json_file_to_dict.assert_any_call(app_config) assert config.app_config_data == mock_return -@pytest.mark.parametrize("target", ["K64F", "UBLOX_EVK_ODIN_W2"]) +@pytest.mark.parametrize("target", ["K64F"]) @pytest.mark.parametrize("overrides", [ {}, {"restrict_size": "0x200"}, diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json index 73f8d46f40c..3d57587e259 100644 --- a/tools/test/examples/examples.json +++ b/tools/test/examples/examples.json @@ -293,7 +293,7 @@ "targets" : ["DISCO_F469NI", "DISCO_F746NG", "K66F", "NUCLEO_F429ZI", "NUCLEO_F439ZI", "NUCLEO_F746ZG", "NUCLEO_F756ZG", "NUCLEO_F767ZI", - "NUMAKER_PFM_NUC472", "UBLOX_EVK_ODIN_W2"], + "NUMAKER_PFM_NUC472"], "toolchains" : [], "exporters": [], "compile" : true, @@ -307,7 +307,7 @@ "sub-repo-example": false, "subs": [], "features" : [], - "targets" : ["K64F", "NUCLEO_F429ZI", "UBLOX_EVK_ODIN_W2"], + "targets" : ["K64F", "NUCLEO_F429ZI"], "toolchains" : [], "exporters": [], "compile" : true, diff --git a/tools/test_configs/config_paths.json b/tools/test_configs/config_paths.json index e51851b1cbc..5f9dfecbaee 100644 --- a/tools/test_configs/config_paths.json +++ b/tools/test_configs/config_paths.json @@ -3,9 +3,6 @@ "HEAPBLOCKDEVICE": "HeapBlockDevice.json", "HEAPBLOCKDEVICE_AND_ETHERNET": "HeapBlockDeviceAndEthernetInterface.json", "HEAPBLOCKDEVICE_AND_WIFI": "HeapBlockDeviceAndWifiInterface.json", - "ODIN_WIFI" : "OdinInterface.json", - "ODIN_ETHERNET" : "Odin_EthernetInterface.json", - "REALTEK_WIFI" : "RealtekInterface.json", "ESP8266_WIFI" : "ESP8266Interface.json", "ISM43362_WIFI" : "ISM43362Interface.json", "IDW0XX1_WIFI" : "SpwfSAInterface.json", @@ -14,6 +11,5 @@ "THREAD_END_DEVICE" : "ThreadInterface_end_device.json", "THREAD_ROUTER" : "ThreadInterface_router.json", "NO_NETWORK": "no_network.json", - "NANOSTACK_MAC_TESTER": "NanostackMACTester.json", - "CC3220SF_WIFI": "CC3220SFInterface.json" + "NANOSTACK_MAC_TESTER": "NanostackMACTester.json" } diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index e9bdb0587e3..08a8d93bb55 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -1,14 +1,4 @@ { - "UBLOX_EVK_ODIN_W2": { - "nsapi.socket-stats-enable": true, - "default_test_configuration": "NONE", - "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI", "HEAPBLOCKDEVICE_AND_ETHERNET"] - }, - "REALTEK_RTL8195AM": { - "nsapi.socket-stats-enable": true, - "default_test_configuration": "NONE", - "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"] - }, "K64F": { "nsapi.socket-stats-enable": true, "default_test_configuration": "HEAPBLOCKDEVICE_AND_ETHERNET", @@ -29,11 +19,6 @@ "default_test_configuration": "NONE", "test_configurations": ["ISM43362_WIFI"] }, - "MTB_UBLOX_ODIN_W2": { - "nsapi.socket-stats-enable": true, - "default_test_configuration": "NONE", - "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"] - }, "MTB_ADV_WISE_1530": { "nsapi.socket-stats-enable": true, "default_test_configuration": "NONE", @@ -43,7 +28,7 @@ "default_test_configuration": "NONE", "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"] }, - "MTB_MXCHIP_EMW3166": { + "WIO_EMW3166": { "default_test_configuration": "NONE", "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"] }, @@ -66,10 +51,5 @@ "TB_SENSE_1": { "default_test_configuration": "NO_NETWORK", "test_configurations": ["6LOWPAN_HOST", "6LOWPAN_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER"] - }, - "CC3220SF": { - "nsapi.socket-stats-enable": true, - "default_test_configuration": "CC3220SF_WIFI", - "test_configurations": ["CC3220SF_WIFI"] } }